diff options
Diffstat (limited to 'drivers/pinctrl')
| -rw-r--r-- | drivers/pinctrl/mediatek/Kconfig | 4 | ||||
| -rw-r--r-- | drivers/pinctrl/mediatek/Makefile | 1 | ||||
| -rw-r--r-- | drivers/pinctrl/mediatek/pinctrl-mt7622.c | 474 | ||||
| -rw-r--r-- | drivers/pinctrl/mediatek/pinctrl-mt7623.c | 650 | ||||
| -rw-r--r-- | drivers/pinctrl/mediatek/pinctrl-mt7629.c | 174 | ||||
| -rw-r--r-- | drivers/pinctrl/mediatek/pinctrl-mt7981.c | 270 | ||||
| -rw-r--r-- | drivers/pinctrl/mediatek/pinctrl-mt7986.c | 145 | ||||
| -rw-r--r-- | drivers/pinctrl/mediatek/pinctrl-mt7988.c | 1274 | ||||
| -rw-r--r-- | drivers/pinctrl/mediatek/pinctrl-mt8512.c | 24 | ||||
| -rw-r--r-- | drivers/pinctrl/mediatek/pinctrl-mt8516.c | 18 | ||||
| -rw-r--r-- | drivers/pinctrl/mediatek/pinctrl-mt8518.c | 20 | ||||
| -rw-r--r-- | drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 22 | ||||
| -rw-r--r-- | drivers/pinctrl/mediatek/pinctrl-mtk-common.h | 8 | ||||
| -rw-r--r-- | drivers/pinctrl/rockchip/pinctrl-rk3568.c | 56 |
14 files changed, 2224 insertions, 916 deletions
diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig index 27e8998e59a..34d23cece51 100644 --- a/drivers/pinctrl/mediatek/Kconfig +++ b/drivers/pinctrl/mediatek/Kconfig @@ -24,6 +24,10 @@ config PINCTRL_MT7986 bool "MT7986 SoC pinctrl driver" select PINCTRL_MTK +config PINCTRL_MT7988 + bool "MT7988 SoC pinctrl driver" + select PINCTRL_MTK + config PINCTRL_MT8512 bool "MT8512 SoC pinctrl driver" select PINCTRL_MTK diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile index 6e733759f58..de39d1ea436 100644 --- a/drivers/pinctrl/mediatek/Makefile +++ b/drivers/pinctrl/mediatek/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o obj-$(CONFIG_PINCTRL_MT7981) += pinctrl-mt7981.o obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o +obj-$(CONFIG_PINCTRL_MT7988) += pinctrl-mt7988.o obj-$(CONFIG_PINCTRL_MT8512) += pinctrl-mt8512.o obj-$(CONFIG_PINCTRL_MT8516) += pinctrl-mt8516.o obj-$(CONFIG_PINCTRL_MT8518) += pinctrl-mt8518.o diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7622.c b/drivers/pinctrl/mediatek/pinctrl-mt7622.c index bf4e9a28e9d..114f2602b28 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7622.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7622.c @@ -233,283 +233,285 @@ static const struct mtk_pin_desc mt7622_pins[] = { */ /* EMMC */ -static int mt7622_emmc_pins[] = { 40, 41, 42, 43, 44, 45, 47, 48, 49, 50, }; -static int mt7622_emmc_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; +static const int mt7622_emmc_pins[] = { + 40, 41, 42, 43, 44, 45, 47, 48, 49, 50, }; +static const int mt7622_emmc_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; -static int mt7622_emmc_rst_pins[] = { 37, }; -static int mt7622_emmc_rst_funcs[] = { 1, }; +static const int mt7622_emmc_rst_pins[] = { 37, }; +static const int mt7622_emmc_rst_funcs[] = { 1, }; /* LED for EPHY */ -static int mt7622_ephy_leds_pins[] = { 86, 91, 92, 93, 94, }; -static int mt7622_ephy_leds_funcs[] = { 0, 0, 0, 0, 0, }; -static int mt7622_ephy0_led_pins[] = { 86, }; -static int mt7622_ephy0_led_funcs[] = { 0, }; -static int mt7622_ephy1_led_pins[] = { 91, }; -static int mt7622_ephy1_led_funcs[] = { 2, }; -static int mt7622_ephy2_led_pins[] = { 92, }; -static int mt7622_ephy2_led_funcs[] = { 2, }; -static int mt7622_ephy3_led_pins[] = { 93, }; -static int mt7622_ephy3_led_funcs[] = { 2, }; -static int mt7622_ephy4_led_pins[] = { 94, }; -static int mt7622_ephy4_led_funcs[] = { 2, }; +static const int mt7622_ephy_leds_pins[] = { 86, 91, 92, 93, 94, }; +static const int mt7622_ephy_leds_funcs[] = { 0, 0, 0, 0, 0, }; +static const int mt7622_ephy0_led_pins[] = { 86, }; +static const int mt7622_ephy0_led_funcs[] = { 0, }; +static const int mt7622_ephy1_led_pins[] = { 91, }; +static const int mt7622_ephy1_led_funcs[] = { 2, }; +static const int mt7622_ephy2_led_pins[] = { 92, }; +static const int mt7622_ephy2_led_funcs[] = { 2, }; +static const int mt7622_ephy3_led_pins[] = { 93, }; +static const int mt7622_ephy3_led_funcs[] = { 2, }; +static const int mt7622_ephy4_led_pins[] = { 94, }; +static const int mt7622_ephy4_led_funcs[] = { 2, }; /* Embedded Switch */ -static int mt7622_esw_pins[] = { 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, - 62, 63, 64, 65, 66, 67, 68, 69, 70, }; -static int mt7622_esw_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, }; -static int mt7622_esw_p0_p1_pins[] = { 51, 52, 53, 54, 55, 56, 57, 58, }; -static int mt7622_esw_p0_p1_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, }; -static int mt7622_esw_p2_p3_p4_pins[] = { 59, 60, 61, 62, 63, 64, 65, 66, 67, - 68, 69, 70, }; -static int mt7622_esw_p2_p3_p4_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, }; +static const int mt7622_esw_pins[] = { + 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, + 69, 70, }; +static const int mt7622_esw_funcs[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; +static const int mt7622_esw_p0_p1_pins[] = { 51, 52, 53, 54, 55, 56, 57, 58, }; +static const int mt7622_esw_p0_p1_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, }; +static const int mt7622_esw_p2_p3_p4_pins[] = { + 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, }; +static const int mt7622_esw_p2_p3_p4_funcs[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; /* RGMII via ESW */ -static int mt7622_rgmii_via_esw_pins[] = { 59, 60, 61, 62, 63, 64, 65, 66, - 67, 68, 69, 70, }; -static int mt7622_rgmii_via_esw_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, }; +static const int mt7622_rgmii_via_esw_pins[] = { + 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, }; +static const int mt7622_rgmii_via_esw_funcs[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; /* RGMII via GMAC1 */ -static int mt7622_rgmii_via_gmac1_pins[] = { 59, 60, 61, 62, 63, 64, 65, 66, - 67, 68, 69, 70, }; -static int mt7622_rgmii_via_gmac1_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, - 2, }; +static const int mt7622_rgmii_via_gmac1_pins[] = { + 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, }; +static const int mt7622_rgmii_via_gmac1_funcs[] = { + 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; /* RGMII via GMAC2 */ -static int mt7622_rgmii_via_gmac2_pins[] = { 25, 26, 27, 28, 29, 30, 31, 32, - 33, 34, 35, 36, }; -static int mt7622_rgmii_via_gmac2_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, }; +static const int mt7622_rgmii_via_gmac2_pins[] = { + 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, }; +static const int mt7622_rgmii_via_gmac2_funcs[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; /* I2C */ -static int mt7622_i2c0_pins[] = { 14, 15, }; -static int mt7622_i2c0_funcs[] = { 0, 0, }; -static int mt7622_i2c1_0_pins[] = { 55, 56, }; -static int mt7622_i2c1_0_funcs[] = { 0, 0, }; -static int mt7622_i2c1_1_pins[] = { 73, 74, }; -static int mt7622_i2c1_1_funcs[] = { 3, 3, }; -static int mt7622_i2c1_2_pins[] = { 87, 88, }; -static int mt7622_i2c1_2_funcs[] = { 0, 0, }; -static int mt7622_i2c2_0_pins[] = { 57, 58, }; -static int mt7622_i2c2_0_funcs[] = { 0, 0, }; -static int mt7622_i2c2_1_pins[] = { 75, 76, }; -static int mt7622_i2c2_1_funcs[] = { 3, 3, }; -static int mt7622_i2c2_2_pins[] = { 89, 90, }; -static int mt7622_i2c2_2_funcs[] = { 0, 0, }; +static const int mt7622_i2c0_pins[] = { 14, 15, }; +static const int mt7622_i2c0_funcs[] = { 0, 0, }; +static const int mt7622_i2c1_0_pins[] = { 55, 56, }; +static const int mt7622_i2c1_0_funcs[] = { 0, 0, }; +static const int mt7622_i2c1_1_pins[] = { 73, 74, }; +static const int mt7622_i2c1_1_funcs[] = { 3, 3, }; +static const int mt7622_i2c1_2_pins[] = { 87, 88, }; +static const int mt7622_i2c1_2_funcs[] = { 0, 0, }; +static const int mt7622_i2c2_0_pins[] = { 57, 58, }; +static const int mt7622_i2c2_0_funcs[] = { 0, 0, }; +static const int mt7622_i2c2_1_pins[] = { 75, 76, }; +static const int mt7622_i2c2_1_funcs[] = { 3, 3, }; +static const int mt7622_i2c2_2_pins[] = { 89, 90, }; +static const int mt7622_i2c2_2_funcs[] = { 0, 0, }; /* I2S */ -static int mt7622_i2s_in_mclk_bclk_ws_pins[] = { 3, 4, 5, }; -static int mt7622_i2s_in_mclk_bclk_ws_funcs[] = { 3, 3, 0, }; -static int mt7622_i2s1_in_data_pins[] = { 1, }; -static int mt7622_i2s1_in_data_funcs[] = { 0, }; -static int mt7622_i2s2_in_data_pins[] = { 16, }; -static int mt7622_i2s2_in_data_funcs[] = { 0, }; -static int mt7622_i2s3_in_data_pins[] = { 17, }; -static int mt7622_i2s3_in_data_funcs[] = { 0, }; -static int mt7622_i2s4_in_data_pins[] = { 18, }; -static int mt7622_i2s4_in_data_funcs[] = { 0, }; -static int mt7622_i2s_out_mclk_bclk_ws_pins[] = { 3, 4, 5, }; -static int mt7622_i2s_out_mclk_bclk_ws_funcs[] = { 0, 0, 0, }; -static int mt7622_i2s1_out_data_pins[] = { 2, }; -static int mt7622_i2s1_out_data_funcs[] = { 0, }; -static int mt7622_i2s2_out_data_pins[] = { 19, }; -static int mt7622_i2s2_out_data_funcs[] = { 0, }; -static int mt7622_i2s3_out_data_pins[] = { 20, }; -static int mt7622_i2s3_out_data_funcs[] = { 0, }; -static int mt7622_i2s4_out_data_pins[] = { 21, }; -static int mt7622_i2s4_out_data_funcs[] = { 0, }; +static const int mt7622_i2s_in_mclk_bclk_ws_pins[] = { 3, 4, 5, }; +static const int mt7622_i2s_in_mclk_bclk_ws_funcs[] = { 3, 3, 0, }; +static const int mt7622_i2s1_in_data_pins[] = { 1, }; +static const int mt7622_i2s1_in_data_funcs[] = { 0, }; +static const int mt7622_i2s2_in_data_pins[] = { 16, }; +static const int mt7622_i2s2_in_data_funcs[] = { 0, }; +static const int mt7622_i2s3_in_data_pins[] = { 17, }; +static const int mt7622_i2s3_in_data_funcs[] = { 0, }; +static const int mt7622_i2s4_in_data_pins[] = { 18, }; +static const int mt7622_i2s4_in_data_funcs[] = { 0, }; +static const int mt7622_i2s_out_mclk_bclk_ws_pins[] = { 3, 4, 5, }; +static const int mt7622_i2s_out_mclk_bclk_ws_funcs[] = { 0, 0, 0, }; +static const int mt7622_i2s1_out_data_pins[] = { 2, }; +static const int mt7622_i2s1_out_data_funcs[] = { 0, }; +static const int mt7622_i2s2_out_data_pins[] = { 19, }; +static const int mt7622_i2s2_out_data_funcs[] = { 0, }; +static const int mt7622_i2s3_out_data_pins[] = { 20, }; +static const int mt7622_i2s3_out_data_funcs[] = { 0, }; +static const int mt7622_i2s4_out_data_pins[] = { 21, }; +static const int mt7622_i2s4_out_data_funcs[] = { 0, }; /* IR */ -static int mt7622_ir_0_tx_pins[] = { 16, }; -static int mt7622_ir_0_tx_funcs[] = { 4, }; -static int mt7622_ir_1_tx_pins[] = { 59, }; -static int mt7622_ir_1_tx_funcs[] = { 5, }; -static int mt7622_ir_2_tx_pins[] = { 99, }; -static int mt7622_ir_2_tx_funcs[] = { 3, }; -static int mt7622_ir_0_rx_pins[] = { 17, }; -static int mt7622_ir_0_rx_funcs[] = { 4, }; -static int mt7622_ir_1_rx_pins[] = { 60, }; -static int mt7622_ir_1_rx_funcs[] = { 5, }; -static int mt7622_ir_2_rx_pins[] = { 100, }; -static int mt7622_ir_2_rx_funcs[] = { 3, }; +static const int mt7622_ir_0_tx_pins[] = { 16, }; +static const int mt7622_ir_0_tx_funcs[] = { 4, }; +static const int mt7622_ir_1_tx_pins[] = { 59, }; +static const int mt7622_ir_1_tx_funcs[] = { 5, }; +static const int mt7622_ir_2_tx_pins[] = { 99, }; +static const int mt7622_ir_2_tx_funcs[] = { 3, }; +static const int mt7622_ir_0_rx_pins[] = { 17, }; +static const int mt7622_ir_0_rx_funcs[] = { 4, }; +static const int mt7622_ir_1_rx_pins[] = { 60, }; +static const int mt7622_ir_1_rx_funcs[] = { 5, }; +static const int mt7622_ir_2_rx_pins[] = { 100, }; +static const int mt7622_ir_2_rx_funcs[] = { 3, }; /* MDIO */ -static int mt7622_mdc_mdio_pins[] = { 23, 24, }; -static int mt7622_mdc_mdio_funcs[] = { 0, 0, }; +static const int mt7622_mdc_mdio_pins[] = { 23, 24, }; +static const int mt7622_mdc_mdio_funcs[] = { 0, 0, }; /* PCIE */ -static int mt7622_pcie0_0_waken_pins[] = { 14, }; -static int mt7622_pcie0_0_waken_funcs[] = { 2, }; -static int mt7622_pcie0_0_clkreq_pins[] = { 15, }; -static int mt7622_pcie0_0_clkreq_funcs[] = { 2, }; -static int mt7622_pcie0_1_waken_pins[] = { 79, }; -static int mt7622_pcie0_1_waken_funcs[] = { 4, }; -static int mt7622_pcie0_1_clkreq_pins[] = { 80, }; -static int mt7622_pcie0_1_clkreq_funcs[] = { 4, }; -static int mt7622_pcie1_0_waken_pins[] = { 14, }; -static int mt7622_pcie1_0_waken_funcs[] = { 3, }; -static int mt7622_pcie1_0_clkreq_pins[] = { 15, }; -static int mt7622_pcie1_0_clkreq_funcs[] = { 3, }; - -static int mt7622_pcie0_pad_perst_pins[] = { 83, }; -static int mt7622_pcie0_pad_perst_funcs[] = { 0, }; -static int mt7622_pcie1_pad_perst_pins[] = { 84, }; -static int mt7622_pcie1_pad_perst_funcs[] = { 0, }; +static const int mt7622_pcie0_0_waken_pins[] = { 14, }; +static const int mt7622_pcie0_0_waken_funcs[] = { 2, }; +static const int mt7622_pcie0_0_clkreq_pins[] = { 15, }; +static const int mt7622_pcie0_0_clkreq_funcs[] = { 2, }; +static const int mt7622_pcie0_1_waken_pins[] = { 79, }; +static const int mt7622_pcie0_1_waken_funcs[] = { 4, }; +static const int mt7622_pcie0_1_clkreq_pins[] = { 80, }; +static const int mt7622_pcie0_1_clkreq_funcs[] = { 4, }; +static const int mt7622_pcie1_0_waken_pins[] = { 14, }; +static const int mt7622_pcie1_0_waken_funcs[] = { 3, }; +static const int mt7622_pcie1_0_clkreq_pins[] = { 15, }; +static const int mt7622_pcie1_0_clkreq_funcs[] = { 3, }; + +static const int mt7622_pcie0_pad_perst_pins[] = { 83, }; +static const int mt7622_pcie0_pad_perst_funcs[] = { 0, }; +static const int mt7622_pcie1_pad_perst_pins[] = { 84, }; +static const int mt7622_pcie1_pad_perst_funcs[] = { 0, }; /* PMIC bus */ -static int mt7622_pmic_bus_pins[] = { 71, 72, }; -static int mt7622_pmic_bus_funcs[] = { 0, 0, }; +static const int mt7622_pmic_bus_pins[] = { 71, 72, }; +static const int mt7622_pmic_bus_funcs[] = { 0, 0, }; /* Parallel NAND */ -static int mt7622_pnand_pins[] = { 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, - 48, 49, 50, }; -static int mt7622_pnand_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, }; +static const int mt7622_pnand_pins[] = { + 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, }; +static const int mt7622_pnand_funcs[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; /* PWM */ -static int mt7622_pwm_ch1_0_pins[] = { 51, }; -static int mt7622_pwm_ch1_0_funcs[] = { 3, }; -static int mt7622_pwm_ch1_1_pins[] = { 73, }; -static int mt7622_pwm_ch1_1_funcs[] = { 4, }; -static int mt7622_pwm_ch1_2_pins[] = { 95, }; -static int mt7622_pwm_ch1_2_funcs[] = { 0, }; -static int mt7622_pwm_ch2_0_pins[] = { 52, }; -static int mt7622_pwm_ch2_0_funcs[] = { 3, }; -static int mt7622_pwm_ch2_1_pins[] = { 74, }; -static int mt7622_pwm_ch2_1_funcs[] = { 4, }; -static int mt7622_pwm_ch2_2_pins[] = { 96, }; -static int mt7622_pwm_ch2_2_funcs[] = { 0, }; -static int mt7622_pwm_ch3_0_pins[] = { 53, }; -static int mt7622_pwm_ch3_0_funcs[] = { 3, }; -static int mt7622_pwm_ch3_1_pins[] = { 75, }; -static int mt7622_pwm_ch3_1_funcs[] = { 4, }; -static int mt7622_pwm_ch3_2_pins[] = { 97, }; -static int mt7622_pwm_ch3_2_funcs[] = { 0, }; -static int mt7622_pwm_ch4_0_pins[] = { 54, }; -static int mt7622_pwm_ch4_0_funcs[] = { 3, }; -static int mt7622_pwm_ch4_1_pins[] = { 67, }; -static int mt7622_pwm_ch4_1_funcs[] = { 3, }; -static int mt7622_pwm_ch4_2_pins[] = { 76, }; -static int mt7622_pwm_ch4_2_funcs[] = { 4, }; -static int mt7622_pwm_ch4_3_pins[] = { 98, }; -static int mt7622_pwm_ch4_3_funcs[] = { 0, }; -static int mt7622_pwm_ch5_0_pins[] = { 68, }; -static int mt7622_pwm_ch5_0_funcs[] = { 3, }; -static int mt7622_pwm_ch5_1_pins[] = { 77, }; -static int mt7622_pwm_ch5_1_funcs[] = { 4, }; -static int mt7622_pwm_ch5_2_pins[] = { 99, }; -static int mt7622_pwm_ch5_2_funcs[] = { 0, }; -static int mt7622_pwm_ch6_0_pins[] = { 69, }; -static int mt7622_pwm_ch6_0_funcs[] = { 3, }; -static int mt7622_pwm_ch6_1_pins[] = { 78, }; -static int mt7622_pwm_ch6_1_funcs[] = { 4, }; -static int mt7622_pwm_ch6_2_pins[] = { 81, }; -static int mt7622_pwm_ch6_2_funcs[] = { 4, }; -static int mt7622_pwm_ch6_3_pins[] = { 100, }; -static int mt7622_pwm_ch6_3_funcs[] = { 0, }; -static int mt7622_pwm_ch7_0_pins[] = { 70, }; -static int mt7622_pwm_ch7_0_funcs[] = { 3, }; -static int mt7622_pwm_ch7_1_pins[] = { 82, }; -static int mt7622_pwm_ch7_1_funcs[] = { 4, }; -static int mt7622_pwm_ch7_2_pins[] = { 101, }; -static int mt7622_pwm_ch7_2_funcs[] = { 0, }; +static const int mt7622_pwm_ch1_0_pins[] = { 51, }; +static const int mt7622_pwm_ch1_0_funcs[] = { 3, }; +static const int mt7622_pwm_ch1_1_pins[] = { 73, }; +static const int mt7622_pwm_ch1_1_funcs[] = { 4, }; +static const int mt7622_pwm_ch1_2_pins[] = { 95, }; +static const int mt7622_pwm_ch1_2_funcs[] = { 0, }; +static const int mt7622_pwm_ch2_0_pins[] = { 52, }; +static const int mt7622_pwm_ch2_0_funcs[] = { 3, }; +static const int mt7622_pwm_ch2_1_pins[] = { 74, }; +static const int mt7622_pwm_ch2_1_funcs[] = { 4, }; +static const int mt7622_pwm_ch2_2_pins[] = { 96, }; +static const int mt7622_pwm_ch2_2_funcs[] = { 0, }; +static const int mt7622_pwm_ch3_0_pins[] = { 53, }; +static const int mt7622_pwm_ch3_0_funcs[] = { 3, }; +static const int mt7622_pwm_ch3_1_pins[] = { 75, }; +static const int mt7622_pwm_ch3_1_funcs[] = { 4, }; +static const int mt7622_pwm_ch3_2_pins[] = { 97, }; +static const int mt7622_pwm_ch3_2_funcs[] = { 0, }; +static const int mt7622_pwm_ch4_0_pins[] = { 54, }; +static const int mt7622_pwm_ch4_0_funcs[] = { 3, }; +static const int mt7622_pwm_ch4_1_pins[] = { 67, }; +static const int mt7622_pwm_ch4_1_funcs[] = { 3, }; +static const int mt7622_pwm_ch4_2_pins[] = { 76, }; +static const int mt7622_pwm_ch4_2_funcs[] = { 4, }; +static const int mt7622_pwm_ch4_3_pins[] = { 98, }; +static const int mt7622_pwm_ch4_3_funcs[] = { 0, }; +static const int mt7622_pwm_ch5_0_pins[] = { 68, }; +static const int mt7622_pwm_ch5_0_funcs[] = { 3, }; +static const int mt7622_pwm_ch5_1_pins[] = { 77, }; +static const int mt7622_pwm_ch5_1_funcs[] = { 4, }; +static const int mt7622_pwm_ch5_2_pins[] = { 99, }; +static const int mt7622_pwm_ch5_2_funcs[] = { 0, }; +static const int mt7622_pwm_ch6_0_pins[] = { 69, }; +static const int mt7622_pwm_ch6_0_funcs[] = { 3, }; +static const int mt7622_pwm_ch6_1_pins[] = { 78, }; +static const int mt7622_pwm_ch6_1_funcs[] = { 4, }; +static const int mt7622_pwm_ch6_2_pins[] = { 81, }; +static const int mt7622_pwm_ch6_2_funcs[] = { 4, }; +static const int mt7622_pwm_ch6_3_pins[] = { 100, }; +static const int mt7622_pwm_ch6_3_funcs[] = { 0, }; +static const int mt7622_pwm_ch7_0_pins[] = { 70, }; +static const int mt7622_pwm_ch7_0_funcs[] = { 3, }; +static const int mt7622_pwm_ch7_1_pins[] = { 82, }; +static const int mt7622_pwm_ch7_1_funcs[] = { 4, }; +static const int mt7622_pwm_ch7_2_pins[] = { 101, }; +static const int mt7622_pwm_ch7_2_funcs[] = { 0, }; /* SD */ -static int mt7622_sd_0_pins[] = { 16, 17, 18, 19, 20, 21, }; -static int mt7622_sd_0_funcs[] = { 2, 2, 2, 2, 2, 2, }; -static int mt7622_sd_1_pins[] = { 25, 26, 27, 28, 29, 30, }; -static int mt7622_sd_1_funcs[] = { 2, 2, 2, 2, 2, 2, }; +static const int mt7622_sd_0_pins[] = { 16, 17, 18, 19, 20, 21, }; +static const int mt7622_sd_0_funcs[] = { 2, 2, 2, 2, 2, 2, }; +static const int mt7622_sd_1_pins[] = { 25, 26, 27, 28, 29, 30, }; +static const int mt7622_sd_1_funcs[] = { 2, 2, 2, 2, 2, 2, }; /* Serial NAND */ -static int mt7622_snfi_pins[] = { 8, 9, 10, 11, 12, 13, }; -static int mt7622_snfi_funcs[] = { 2, 2, 2, 2, 2, 2, }; +static const int mt7622_snfi_pins[] = { 8, 9, 10, 11, 12, 13, }; +static const int mt7622_snfi_funcs[] = { 2, 2, 2, 2, 2, 2, }; /* SPI NOR */ -static int mt7622_spi_pins[] = { 8, 9, 10, 11, 12, 13 }; -static int mt7622_spi_funcs[] = { 0, 0, 0, 0, 0, 0, }; +static const int mt7622_spi_pins[] = { 8, 9, 10, 11, 12, 13 }; +static const int mt7622_spi_funcs[] = { 0, 0, 0, 0, 0, 0, }; /* SPIC */ -static int mt7622_spic0_0_pins[] = { 63, 64, 65, 66, }; -static int mt7622_spic0_0_funcs[] = { 4, 4, 4, 4, }; -static int mt7622_spic0_1_pins[] = { 79, 80, 81, 82, }; -static int mt7622_spic0_1_funcs[] = { 3, 3, 3, 3, }; -static int mt7622_spic1_0_pins[] = { 67, 68, 69, 70, }; -static int mt7622_spic1_0_funcs[] = { 4, 4, 4, 4, }; -static int mt7622_spic1_1_pins[] = { 73, 74, 75, 76, }; -static int mt7622_spic1_1_funcs[] = { 0, 0, 0, 0, }; -static int mt7622_spic2_0_pins[] = { 10, 11, 12, 13, }; -static int mt7622_spic2_0_funcs[] = { 0, 0, 0, 0, }; -static int mt7622_spic2_0_wp_hold_pins[] = { 8, 9, }; -static int mt7622_spic2_0_wp_hold_funcs[] = { 0, 0, }; +static const int mt7622_spic0_0_pins[] = { 63, 64, 65, 66, }; +static const int mt7622_spic0_0_funcs[] = { 4, 4, 4, 4, }; +static const int mt7622_spic0_1_pins[] = { 79, 80, 81, 82, }; +static const int mt7622_spic0_1_funcs[] = { 3, 3, 3, 3, }; +static const int mt7622_spic1_0_pins[] = { 67, 68, 69, 70, }; +static const int mt7622_spic1_0_funcs[] = { 4, 4, 4, 4, }; +static const int mt7622_spic1_1_pins[] = { 73, 74, 75, 76, }; +static const int mt7622_spic1_1_funcs[] = { 0, 0, 0, 0, }; +static const int mt7622_spic2_0_pins[] = { 10, 11, 12, 13, }; +static const int mt7622_spic2_0_funcs[] = { 0, 0, 0, 0, }; +static const int mt7622_spic2_0_wp_hold_pins[] = { 8, 9, }; +static const int mt7622_spic2_0_wp_hold_funcs[] = { 0, 0, }; /* TDM */ -static int mt7622_tdm_0_out_mclk_bclk_ws_pins[] = { 8, 9, 10, }; -static int mt7622_tdm_0_out_mclk_bclk_ws_funcs[] = { 3, 3, 3, }; -static int mt7622_tdm_0_in_mclk_bclk_ws_pins[] = { 11, 12, 13, }; -static int mt7622_tdm_0_in_mclk_bclk_ws_funcs[] = { 3, 3, 3, }; -static int mt7622_tdm_0_out_data_pins[] = { 20, }; -static int mt7622_tdm_0_out_data_funcs[] = { 3, }; -static int mt7622_tdm_0_in_data_pins[] = { 21, }; -static int mt7622_tdm_0_in_data_funcs[] = { 3, }; -static int mt7622_tdm_1_out_mclk_bclk_ws_pins[] = { 57, 58, 59, }; -static int mt7622_tdm_1_out_mclk_bclk_ws_funcs[] = { 3, 3, 3, }; -static int mt7622_tdm_1_in_mclk_bclk_ws_pins[] = { 60, 61, 62, }; -static int mt7622_tdm_1_in_mclk_bclk_ws_funcs[] = { 3, 3, 3, }; -static int mt7622_tdm_1_out_data_pins[] = { 55, }; -static int mt7622_tdm_1_out_data_funcs[] = { 3, }; -static int mt7622_tdm_1_in_data_pins[] = { 56, }; -static int mt7622_tdm_1_in_data_funcs[] = { 3, }; +static const int mt7622_tdm_0_out_mclk_bclk_ws_pins[] = { 8, 9, 10, }; +static const int mt7622_tdm_0_out_mclk_bclk_ws_funcs[] = { 3, 3, 3, }; +static const int mt7622_tdm_0_in_mclk_bclk_ws_pins[] = { 11, 12, 13, }; +static const int mt7622_tdm_0_in_mclk_bclk_ws_funcs[] = { 3, 3, 3, }; +static const int mt7622_tdm_0_out_data_pins[] = { 20, }; +static const int mt7622_tdm_0_out_data_funcs[] = { 3, }; +static const int mt7622_tdm_0_in_data_pins[] = { 21, }; +static const int mt7622_tdm_0_in_data_funcs[] = { 3, }; +static const int mt7622_tdm_1_out_mclk_bclk_ws_pins[] = { 57, 58, 59, }; +static const int mt7622_tdm_1_out_mclk_bclk_ws_funcs[] = { 3, 3, 3, }; +static const int mt7622_tdm_1_in_mclk_bclk_ws_pins[] = { 60, 61, 62, }; +static const int mt7622_tdm_1_in_mclk_bclk_ws_funcs[] = { 3, 3, 3, }; +static const int mt7622_tdm_1_out_data_pins[] = { 55, }; +static const int mt7622_tdm_1_out_data_funcs[] = { 3, }; +static const int mt7622_tdm_1_in_data_pins[] = { 56, }; +static const int mt7622_tdm_1_in_data_funcs[] = { 3, }; /* UART */ -static int mt7622_uart0_0_tx_rx_pins[] = { 6, 7, }; -static int mt7622_uart0_0_tx_rx_funcs[] = { 0, 0, }; -static int mt7622_uart1_0_tx_rx_pins[] = { 55, 56, }; -static int mt7622_uart1_0_tx_rx_funcs[] = { 2, 2, }; -static int mt7622_uart1_0_rts_cts_pins[] = { 57, 58, }; -static int mt7622_uart1_0_rts_cts_funcs[] = { 2, 2, }; -static int mt7622_uart1_1_tx_rx_pins[] = { 73, 74, }; -static int mt7622_uart1_1_tx_rx_funcs[] = { 2, 2, }; -static int mt7622_uart1_1_rts_cts_pins[] = { 75, 76, }; -static int mt7622_uart1_1_rts_cts_funcs[] = { 2, 2, }; -static int mt7622_uart2_0_tx_rx_pins[] = { 3, 4, }; -static int mt7622_uart2_0_tx_rx_funcs[] = { 2, 2, }; -static int mt7622_uart2_0_rts_cts_pins[] = { 1, 2, }; -static int mt7622_uart2_0_rts_cts_funcs[] = { 2, 2, }; -static int mt7622_uart2_1_tx_rx_pins[] = { 51, 52, }; -static int mt7622_uart2_1_tx_rx_funcs[] = { 0, 0, }; -static int mt7622_uart2_1_rts_cts_pins[] = { 53, 54, }; -static int mt7622_uart2_1_rts_cts_funcs[] = { 0, 0, }; -static int mt7622_uart2_2_tx_rx_pins[] = { 59, 60, }; -static int mt7622_uart2_2_tx_rx_funcs[] = { 4, 4, }; -static int mt7622_uart2_2_rts_cts_pins[] = { 61, 62, }; -static int mt7622_uart2_2_rts_cts_funcs[] = { 4, 4, }; -static int mt7622_uart2_3_tx_rx_pins[] = { 95, 96, }; -static int mt7622_uart2_3_tx_rx_funcs[] = { 3, 3, }; -static int mt7622_uart3_0_tx_rx_pins[] = { 57, 58, }; -static int mt7622_uart3_0_tx_rx_funcs[] = { 5, 5, }; -static int mt7622_uart3_1_tx_rx_pins[] = { 81, 82, }; -static int mt7622_uart3_1_tx_rx_funcs[] = { 0, 0, }; -static int mt7622_uart3_1_rts_cts_pins[] = { 79, 80, }; -static int mt7622_uart3_1_rts_cts_funcs[] = { 0, 0, }; -static int mt7622_uart4_0_tx_rx_pins[] = { 61, 62, }; -static int mt7622_uart4_0_tx_rx_funcs[] = { 5, 5, }; -static int mt7622_uart4_1_tx_rx_pins[] = { 91, 92, }; -static int mt7622_uart4_1_tx_rx_funcs[] = { 0, 0, }; -static int mt7622_uart4_1_rts_cts_pins[] = { 93, 94 }; -static int mt7622_uart4_1_rts_cts_funcs[] = { 0, 0, }; -static int mt7622_uart4_2_tx_rx_pins[] = { 97, 98, }; -static int mt7622_uart4_2_tx_rx_funcs[] = { 2, 2, }; -static int mt7622_uart4_2_rts_cts_pins[] = { 95, 96 }; -static int mt7622_uart4_2_rts_cts_funcs[] = { 2, 2, }; +static const int mt7622_uart0_0_tx_rx_pins[] = { 6, 7, }; +static const int mt7622_uart0_0_tx_rx_funcs[] = { 0, 0, }; +static const int mt7622_uart1_0_tx_rx_pins[] = { 55, 56, }; +static const int mt7622_uart1_0_tx_rx_funcs[] = { 2, 2, }; +static const int mt7622_uart1_0_rts_cts_pins[] = { 57, 58, }; +static const int mt7622_uart1_0_rts_cts_funcs[] = { 2, 2, }; +static const int mt7622_uart1_1_tx_rx_pins[] = { 73, 74, }; +static const int mt7622_uart1_1_tx_rx_funcs[] = { 2, 2, }; +static const int mt7622_uart1_1_rts_cts_pins[] = { 75, 76, }; +static const int mt7622_uart1_1_rts_cts_funcs[] = { 2, 2, }; +static const int mt7622_uart2_0_tx_rx_pins[] = { 3, 4, }; +static const int mt7622_uart2_0_tx_rx_funcs[] = { 2, 2, }; +static const int mt7622_uart2_0_rts_cts_pins[] = { 1, 2, }; +static const int mt7622_uart2_0_rts_cts_funcs[] = { 2, 2, }; +static const int mt7622_uart2_1_tx_rx_pins[] = { 51, 52, }; +static const int mt7622_uart2_1_tx_rx_funcs[] = { 0, 0, }; +static const int mt7622_uart2_1_rts_cts_pins[] = { 53, 54, }; +static const int mt7622_uart2_1_rts_cts_funcs[] = { 0, 0, }; +static const int mt7622_uart2_2_tx_rx_pins[] = { 59, 60, }; +static const int mt7622_uart2_2_tx_rx_funcs[] = { 4, 4, }; +static const int mt7622_uart2_2_rts_cts_pins[] = { 61, 62, }; +static const int mt7622_uart2_2_rts_cts_funcs[] = { 4, 4, }; +static const int mt7622_uart2_3_tx_rx_pins[] = { 95, 96, }; +static const int mt7622_uart2_3_tx_rx_funcs[] = { 3, 3, }; +static const int mt7622_uart3_0_tx_rx_pins[] = { 57, 58, }; +static const int mt7622_uart3_0_tx_rx_funcs[] = { 5, 5, }; +static const int mt7622_uart3_1_tx_rx_pins[] = { 81, 82, }; +static const int mt7622_uart3_1_tx_rx_funcs[] = { 0, 0, }; +static const int mt7622_uart3_1_rts_cts_pins[] = { 79, 80, }; +static const int mt7622_uart3_1_rts_cts_funcs[] = { 0, 0, }; +static const int mt7622_uart4_0_tx_rx_pins[] = { 61, 62, }; +static const int mt7622_uart4_0_tx_rx_funcs[] = { 5, 5, }; +static const int mt7622_uart4_1_tx_rx_pins[] = { 91, 92, }; +static const int mt7622_uart4_1_tx_rx_funcs[] = { 0, 0, }; +static const int mt7622_uart4_1_rts_cts_pins[] = { 93, 94 }; +static const int mt7622_uart4_1_rts_cts_funcs[] = { 0, 0, }; +static const int mt7622_uart4_2_tx_rx_pins[] = { 97, 98, }; +static const int mt7622_uart4_2_tx_rx_funcs[] = { 2, 2, }; +static const int mt7622_uart4_2_rts_cts_pins[] = { 95, 96 }; +static const int mt7622_uart4_2_rts_cts_funcs[] = { 2, 2, }; /* Watchdog */ -static int mt7622_watchdog_pins[] = { 78, }; -static int mt7622_watchdog_funcs[] = { 0, }; +static const int mt7622_watchdog_pins[] = { 78, }; +static const int mt7622_watchdog_funcs[] = { 0, }; /* WLAN LED */ -static int mt7622_wled_pins[] = { 85, }; -static int mt7622_wled_funcs[] = { 0, }; +static const int mt7622_wled_pins[] = { 85, }; +static const int mt7622_wled_funcs[] = { 0, }; static const struct mtk_group_desc mt7622_groups[] = { PINCTRL_PIN_GROUP("emmc", mt7622_emmc), @@ -719,7 +721,7 @@ static const struct mtk_function_desc mt7622_functions[] = { {"watchdog", mt7622_wdt_groups, ARRAY_SIZE(mt7622_wdt_groups)}, }; -static struct mtk_pinctrl_soc mt7622_data = { +static const struct mtk_pinctrl_soc mt7622_data = { .name = "mt7622_pinctrl", .reg_cal = mt7622_reg_cals, .pins = mt7622_pins, diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7623.c b/drivers/pinctrl/mediatek/pinctrl-mt7623.c index 2e3ae34b8ba..2703e6f754c 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7623.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7623.c @@ -692,377 +692,377 @@ static const struct mtk_pin_desc mt7623_pins[] = { */ /* AUDIO EXT CLK */ -static int mt7623_aud_ext_clk0_pins[] = { 208, }; -static int mt7623_aud_ext_clk0_funcs[] = { 1, }; -static int mt7623_aud_ext_clk1_pins[] = { 209, }; -static int mt7623_aud_ext_clk1_funcs[] = { 1, }; +static const int mt7623_aud_ext_clk0_pins[] = { 208, }; +static const int mt7623_aud_ext_clk0_funcs[] = { 1, }; +static const int mt7623_aud_ext_clk1_pins[] = { 209, }; +static const int mt7623_aud_ext_clk1_funcs[] = { 1, }; /* DISP PWM */ -static int mt7623_disp_pwm_0_pins[] = { 72, }; -static int mt7623_disp_pwm_0_funcs[] = { 5, }; -static int mt7623_disp_pwm_1_pins[] = { 203, }; -static int mt7623_disp_pwm_1_funcs[] = { 2, }; -static int mt7623_disp_pwm_2_pins[] = { 208, }; -static int mt7623_disp_pwm_2_funcs[] = { 5, }; +static const int mt7623_disp_pwm_0_pins[] = { 72, }; +static const int mt7623_disp_pwm_0_funcs[] = { 5, }; +static const int mt7623_disp_pwm_1_pins[] = { 203, }; +static const int mt7623_disp_pwm_1_funcs[] = { 2, }; +static const int mt7623_disp_pwm_2_pins[] = { 208, }; +static const int mt7623_disp_pwm_2_funcs[] = { 5, }; /* ESW */ -static int mt7623_esw_int_pins[] = { 273, }; -static int mt7623_esw_int_funcs[] = { 1, }; -static int mt7623_esw_rst_pins[] = { 277, }; -static int mt7623_esw_rst_funcs[] = { 1, }; +static const int mt7623_esw_int_pins[] = { 273, }; +static const int mt7623_esw_int_funcs[] = { 1, }; +static const int mt7623_esw_rst_pins[] = { 277, }; +static const int mt7623_esw_rst_funcs[] = { 1, }; /* EPHY */ -static int mt7623_ephy_pins[] = { 262, 263, 264, 265, 266, 267, 268, - 269, 270, 271, 272, 274, }; -static int mt7623_ephy_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; +static const int mt7623_ephy_pins[] = { 262, 263, 264, 265, 266, 267, 268, + 269, 270, 271, 272, 274, }; +static const int mt7623_ephy_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; /* EXT_SDIO */ -static int mt7623_ext_sdio_pins[] = { 236, 237, 238, 239, 240, 241, }; -static int mt7623_ext_sdio_funcs[] = { 1, 1, 1, 1, 1, 1, }; +static const int mt7623_ext_sdio_pins[] = { 236, 237, 238, 239, 240, 241, }; +static const int mt7623_ext_sdio_funcs[] = { 1, 1, 1, 1, 1, 1, }; /* HDMI RX */ -static int mt7623_hdmi_rx_pins[] = { 247, 248, }; -static int mt7623_hdmi_rx_funcs[] = { 1, 1 }; -static int mt7623_hdmi_rx_i2c_pins[] = { 244, 245, }; -static int mt7623_hdmi_rx_i2c_funcs[] = { 1, 1 }; +static const int mt7623_hdmi_rx_pins[] = { 247, 248, }; +static const int mt7623_hdmi_rx_funcs[] = { 1, 1 }; +static const int mt7623_hdmi_rx_i2c_pins[] = { 244, 245, }; +static const int mt7623_hdmi_rx_i2c_funcs[] = { 1, 1 }; /* HDMI TX */ -static int mt7623_hdmi_cec_pins[] = { 122, }; -static int mt7623_hdmi_cec_funcs[] = { 1, }; -static int mt7623_hdmi_htplg_pins[] = { 123, }; -static int mt7623_hdmi_htplg_funcs[] = { 1, }; -static int mt7623_hdmi_i2c_pins[] = { 124, 125, }; -static int mt7623_hdmi_i2c_funcs[] = { 1, 1 }; +static const int mt7623_hdmi_cec_pins[] = { 122, }; +static const int mt7623_hdmi_cec_funcs[] = { 1, }; +static const int mt7623_hdmi_htplg_pins[] = { 123, }; +static const int mt7623_hdmi_htplg_funcs[] = { 1, }; +static const int mt7623_hdmi_i2c_pins[] = { 124, 125, }; +static const int mt7623_hdmi_i2c_funcs[] = { 1, 1 }; /* I2C */ -static int mt7623_i2c0_pins[] = { 75, 76, }; -static int mt7623_i2c0_funcs[] = { 1, 1, }; -static int mt7623_i2c1_0_pins[] = { 57, 58, }; -static int mt7623_i2c1_0_funcs[] = { 1, 1, }; -static int mt7623_i2c1_1_pins[] = { 242, 243, }; -static int mt7623_i2c1_1_funcs[] = { 4, 4, }; -static int mt7623_i2c1_2_pins[] = { 85, 86, }; -static int mt7623_i2c1_2_funcs[] = { 3, 3, }; -static int mt7623_i2c1_3_pins[] = { 105, 106, }; -static int mt7623_i2c1_3_funcs[] = { 3, 3, }; -static int mt7623_i2c1_4_pins[] = { 124, 125, }; -static int mt7623_i2c1_4_funcs[] = { 4, 4, }; -static int mt7623_i2c2_0_pins[] = { 77, 78, }; -static int mt7623_i2c2_0_funcs[] = { 1, 1, }; -static int mt7623_i2c2_1_pins[] = { 89, 90, }; -static int mt7623_i2c2_1_funcs[] = { 3, 3, }; -static int mt7623_i2c2_2_pins[] = { 109, 110, }; -static int mt7623_i2c2_2_funcs[] = { 3, 3, }; -static int mt7623_i2c2_3_pins[] = { 122, 123, }; -static int mt7623_i2c2_3_funcs[] = { 4, 4, }; +static const int mt7623_i2c0_pins[] = { 75, 76, }; +static const int mt7623_i2c0_funcs[] = { 1, 1, }; +static const int mt7623_i2c1_0_pins[] = { 57, 58, }; +static const int mt7623_i2c1_0_funcs[] = { 1, 1, }; +static const int mt7623_i2c1_1_pins[] = { 242, 243, }; +static const int mt7623_i2c1_1_funcs[] = { 4, 4, }; +static const int mt7623_i2c1_2_pins[] = { 85, 86, }; +static const int mt7623_i2c1_2_funcs[] = { 3, 3, }; +static const int mt7623_i2c1_3_pins[] = { 105, 106, }; +static const int mt7623_i2c1_3_funcs[] = { 3, 3, }; +static const int mt7623_i2c1_4_pins[] = { 124, 125, }; +static const int mt7623_i2c1_4_funcs[] = { 4, 4, }; +static const int mt7623_i2c2_0_pins[] = { 77, 78, }; +static const int mt7623_i2c2_0_funcs[] = { 1, 1, }; +static const int mt7623_i2c2_1_pins[] = { 89, 90, }; +static const int mt7623_i2c2_1_funcs[] = { 3, 3, }; +static const int mt7623_i2c2_2_pins[] = { 109, 110, }; +static const int mt7623_i2c2_2_funcs[] = { 3, 3, }; +static const int mt7623_i2c2_3_pins[] = { 122, 123, }; +static const int mt7623_i2c2_3_funcs[] = { 4, 4, }; /* I2S */ -static int mt7623_i2s0_pins[] = { 49, 72, 73, 74, 126, }; -static int mt7623_i2s0_funcs[] = { 1, 1, 1, 1, 1, }; -static int mt7623_i2s1_pins[] = { 33, 34, 35, 36, 37, }; -static int mt7623_i2s1_funcs[] = { 1, 1, 1, 1, 1, }; -static int mt7623_i2s2_bclk_lrclk_mclk_pins[] = { 50, 52, 188, }; -static int mt7623_i2s2_bclk_lrclk_mclk_funcs[] = { 1, 1, 1, }; -static int mt7623_i2s2_data_in_pins[] = { 51, }; -static int mt7623_i2s2_data_in_funcs[] = { 1, }; -static int mt7623_i2s2_data_0_pins[] = { 203, }; -static int mt7623_i2s2_data_0_funcs[] = { 9, }; -static int mt7623_i2s2_data_1_pins[] = { 38, }; -static int mt7623_i2s2_data_1_funcs[] = { 4, }; -static int mt7623_i2s3_bclk_lrclk_mclk_pins[] = { 191, 192, 193, }; -static int mt7623_i2s3_bclk_lrclk_mclk_funcs[] = { 1, 1, 1, }; -static int mt7623_i2s3_data_in_pins[] = { 190, }; -static int mt7623_i2s3_data_in_funcs[] = { 1, }; -static int mt7623_i2s3_data_0_pins[] = { 204, }; -static int mt7623_i2s3_data_0_funcs[] = { 9, }; -static int mt7623_i2s3_data_1_pins[] = { 2, }; -static int mt7623_i2s3_data_1_funcs[] = { 0, }; -static int mt7623_i2s4_pins[] = { 194, 195, 196, 197, 198, }; -static int mt7623_i2s4_funcs[] = { 1, 1, 1, 1, 1, }; -static int mt7623_i2s5_pins[] = { 16, 17, 30, 31, 32, }; -static int mt7623_i2s5_funcs[] = { 1, 1, 1, 1, 1, }; +static const int mt7623_i2s0_pins[] = { 49, 72, 73, 74, 126, }; +static const int mt7623_i2s0_funcs[] = { 1, 1, 1, 1, 1, }; +static const int mt7623_i2s1_pins[] = { 33, 34, 35, 36, 37, }; +static const int mt7623_i2s1_funcs[] = { 1, 1, 1, 1, 1, }; +static const int mt7623_i2s2_bclk_lrclk_mclk_pins[] = { 50, 52, 188, }; +static const int mt7623_i2s2_bclk_lrclk_mclk_funcs[] = { 1, 1, 1, }; +static const int mt7623_i2s2_data_in_pins[] = { 51, }; +static const int mt7623_i2s2_data_in_funcs[] = { 1, }; +static const int mt7623_i2s2_data_0_pins[] = { 203, }; +static const int mt7623_i2s2_data_0_funcs[] = { 9, }; +static const int mt7623_i2s2_data_1_pins[] = { 38, }; +static const int mt7623_i2s2_data_1_funcs[] = { 4, }; +static const int mt7623_i2s3_bclk_lrclk_mclk_pins[] = { 191, 192, 193, }; +static const int mt7623_i2s3_bclk_lrclk_mclk_funcs[] = { 1, 1, 1, }; +static const int mt7623_i2s3_data_in_pins[] = { 190, }; +static const int mt7623_i2s3_data_in_funcs[] = { 1, }; +static const int mt7623_i2s3_data_0_pins[] = { 204, }; +static const int mt7623_i2s3_data_0_funcs[] = { 9, }; +static const int mt7623_i2s3_data_1_pins[] = { 2, }; +static const int mt7623_i2s3_data_1_funcs[] = { 0, }; +static const int mt7623_i2s4_pins[] = { 194, 195, 196, 197, 198, }; +static const int mt7623_i2s4_funcs[] = { 1, 1, 1, 1, 1, }; +static const int mt7623_i2s5_pins[] = { 16, 17, 30, 31, 32, }; +static const int mt7623_i2s5_funcs[] = { 1, 1, 1, 1, 1, }; /* IR */ -static int mt7623_ir_pins[] = { 46, }; -static int mt7623_ir_funcs[] = { 1, }; +static const int mt7623_ir_pins[] = { 46, }; +static const int mt7623_ir_funcs[] = { 1, }; /* LCD */ -static int mt7623_mipi_tx_pins[] = { 91, 92, 93, 94, 95, 96, 97, 98, - 99, 100, }; -static int mt7623_mipi_tx_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; -static int mt7623_dsi_te_pins[] = { 84, }; -static int mt7623_dsi_te_funcs[] = { 1, }; -static int mt7623_lcm_rst_pins[] = { 83, }; -static int mt7623_lcm_rst_funcs[] = { 1, }; +static const int mt7623_mipi_tx_pins[] = { 91, 92, 93, 94, 95, 96, 97, 98, + 99, 100, }; +static const int mt7623_mipi_tx_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; +static const int mt7623_dsi_te_pins[] = { 84, }; +static const int mt7623_dsi_te_funcs[] = { 1, }; +static const int mt7623_lcm_rst_pins[] = { 83, }; +static const int mt7623_lcm_rst_funcs[] = { 1, }; /* MDC/MDIO */ -static int mt7623_mdc_mdio_pins[] = { 275, 276, }; -static int mt7623_mdc_mdio_funcs[] = { 1, 1, }; +static const int mt7623_mdc_mdio_pins[] = { 275, 276, }; +static const int mt7623_mdc_mdio_funcs[] = { 1, 1, }; /* MSDC */ -static int mt7623_msdc0_pins[] = { 111, 112, 113, 114, 115, 116, 117, 118, - 119, 120, 121, }; -static int mt7623_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; -static int mt7623_msdc1_pins[] = { 105, 106, 107, 108, 109, 110, }; -static int mt7623_msdc1_funcs[] = { 1, 1, 1, 1, 1, 1, }; -static int mt7623_msdc1_ins_pins[] = { 261, }; -static int mt7623_msdc1_ins_funcs[] = { 1, }; -static int mt7623_msdc1_wp_0_pins[] = { 29, }; -static int mt7623_msdc1_wp_0_funcs[] = { 1, }; -static int mt7623_msdc1_wp_1_pins[] = { 55, }; -static int mt7623_msdc1_wp_1_funcs[] = { 3, }; -static int mt7623_msdc1_wp_2_pins[] = { 209, }; -static int mt7623_msdc1_wp_2_funcs[] = { 2, }; -static int mt7623_msdc2_pins[] = { 85, 86, 87, 88, 89, 90, }; -static int mt7623_msdc2_funcs[] = { 1, 1, 1, 1, 1, 1, }; -static int mt7623_msdc3_pins[] = { 249, 250, 251, 252, 253, 254, 255, 256, - 257, 258, 259, 260, }; -static int mt7623_msdc3_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; +static const int mt7623_msdc0_pins[] = { 111, 112, 113, 114, 115, 116, 117, 118, + 119, 120, 121, }; +static const int mt7623_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; +static const int mt7623_msdc1_pins[] = { 105, 106, 107, 108, 109, 110, }; +static const int mt7623_msdc1_funcs[] = { 1, 1, 1, 1, 1, 1, }; +static const int mt7623_msdc1_ins_pins[] = { 261, }; +static const int mt7623_msdc1_ins_funcs[] = { 1, }; +static const int mt7623_msdc1_wp_0_pins[] = { 29, }; +static const int mt7623_msdc1_wp_0_funcs[] = { 1, }; +static const int mt7623_msdc1_wp_1_pins[] = { 55, }; +static const int mt7623_msdc1_wp_1_funcs[] = { 3, }; +static const int mt7623_msdc1_wp_2_pins[] = { 209, }; +static const int mt7623_msdc1_wp_2_funcs[] = { 2, }; +static const int mt7623_msdc2_pins[] = { 85, 86, 87, 88, 89, 90, }; +static const int mt7623_msdc2_funcs[] = { 1, 1, 1, 1, 1, 1, }; +static const int mt7623_msdc3_pins[] = { 249, 250, 251, 252, 253, 254, 255, 256, + 257, 258, 259, 260, }; +static const int mt7623_msdc3_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; /* NAND */ -static int mt7623_nandc_pins[] = { 43, 47, 48, 111, 112, 113, 114, 115, - 116, 117, 118, 119, 120, 121, }; -static int mt7623_nandc_funcs[] = { 1, 1, 1, 4, 4, 4, 4, 4, 4, 4, 4, 4, - 4, 4, }; -static int mt7623_nandc_ceb0_pins[] = { 45, }; -static int mt7623_nandc_ceb0_funcs[] = { 1, }; -static int mt7623_nandc_ceb1_pins[] = { 44, }; -static int mt7623_nandc_ceb1_funcs[] = { 1, }; +static const int mt7623_nandc_pins[] = { 43, 47, 48, 111, 112, 113, 114, 115, + 116, 117, 118, 119, 120, 121, }; +static const int mt7623_nandc_funcs[] = { 1, 1, 1, 4, 4, 4, 4, 4, 4, 4, 4, 4, + 4, 4, }; +static const int mt7623_nandc_ceb0_pins[] = { 45, }; +static const int mt7623_nandc_ceb0_funcs[] = { 1, }; +static const int mt7623_nandc_ceb1_pins[] = { 44, }; +static const int mt7623_nandc_ceb1_funcs[] = { 1, }; /* RTC */ -static int mt7623_rtc_pins[] = { 10, }; -static int mt7623_rtc_funcs[] = { 1, }; +static const int mt7623_rtc_pins[] = { 10, }; +static const int mt7623_rtc_funcs[] = { 1, }; /* OTG */ -static int mt7623_otg_iddig0_0_pins[] = { 29, }; -static int mt7623_otg_iddig0_0_funcs[] = { 1, }; -static int mt7623_otg_iddig0_1_pins[] = { 44, }; -static int mt7623_otg_iddig0_1_funcs[] = { 2, }; -static int mt7623_otg_iddig0_2_pins[] = { 236, }; -static int mt7623_otg_iddig0_2_funcs[] = { 2, }; -static int mt7623_otg_iddig1_0_pins[] = { 27, }; -static int mt7623_otg_iddig1_0_funcs[] = { 2, }; -static int mt7623_otg_iddig1_1_pins[] = { 47, }; -static int mt7623_otg_iddig1_1_funcs[] = { 2, }; -static int mt7623_otg_iddig1_2_pins[] = { 238, }; -static int mt7623_otg_iddig1_2_funcs[] = { 2, }; -static int mt7623_otg_drv_vbus0_0_pins[] = { 28, }; -static int mt7623_otg_drv_vbus0_0_funcs[] = { 1, }; -static int mt7623_otg_drv_vbus0_1_pins[] = { 45, }; -static int mt7623_otg_drv_vbus0_1_funcs[] = { 2, }; -static int mt7623_otg_drv_vbus0_2_pins[] = { 237, }; -static int mt7623_otg_drv_vbus0_2_funcs[] = { 2, }; -static int mt7623_otg_drv_vbus1_0_pins[] = { 26, }; -static int mt7623_otg_drv_vbus1_0_funcs[] = { 2, }; -static int mt7623_otg_drv_vbus1_1_pins[] = { 48, }; -static int mt7623_otg_drv_vbus1_1_funcs[] = { 2, }; -static int mt7623_otg_drv_vbus1_2_pins[] = { 239, }; -static int mt7623_otg_drv_vbus1_2_funcs[] = { 2, }; +static const int mt7623_otg_iddig0_0_pins[] = { 29, }; +static const int mt7623_otg_iddig0_0_funcs[] = { 1, }; +static const int mt7623_otg_iddig0_1_pins[] = { 44, }; +static const int mt7623_otg_iddig0_1_funcs[] = { 2, }; +static const int mt7623_otg_iddig0_2_pins[] = { 236, }; +static const int mt7623_otg_iddig0_2_funcs[] = { 2, }; +static const int mt7623_otg_iddig1_0_pins[] = { 27, }; +static const int mt7623_otg_iddig1_0_funcs[] = { 2, }; +static const int mt7623_otg_iddig1_1_pins[] = { 47, }; +static const int mt7623_otg_iddig1_1_funcs[] = { 2, }; +static const int mt7623_otg_iddig1_2_pins[] = { 238, }; +static const int mt7623_otg_iddig1_2_funcs[] = { 2, }; +static const int mt7623_otg_drv_vbus0_0_pins[] = { 28, }; +static const int mt7623_otg_drv_vbus0_0_funcs[] = { 1, }; +static const int mt7623_otg_drv_vbus0_1_pins[] = { 45, }; +static const int mt7623_otg_drv_vbus0_1_funcs[] = { 2, }; +static const int mt7623_otg_drv_vbus0_2_pins[] = { 237, }; +static const int mt7623_otg_drv_vbus0_2_funcs[] = { 2, }; +static const int mt7623_otg_drv_vbus1_0_pins[] = { 26, }; +static const int mt7623_otg_drv_vbus1_0_funcs[] = { 2, }; +static const int mt7623_otg_drv_vbus1_1_pins[] = { 48, }; +static const int mt7623_otg_drv_vbus1_1_funcs[] = { 2, }; +static const int mt7623_otg_drv_vbus1_2_pins[] = { 239, }; +static const int mt7623_otg_drv_vbus1_2_funcs[] = { 2, }; /* PCIE */ -static int mt7623_pcie0_0_perst_pins[] = { 208, }; -static int mt7623_pcie0_0_perst_funcs[] = { 3, }; -static int mt7623_pcie0_1_perst_pins[] = { 22, }; -static int mt7623_pcie0_1_perst_funcs[] = { 2, }; -static int mt7623_pcie1_0_perst_pins[] = { 209, }; -static int mt7623_pcie1_0_perst_funcs[] = { 3, }; -static int mt7623_pcie1_1_perst_pins[] = { 23, }; -static int mt7623_pcie1_1_perst_funcs[] = { 2, }; -static int mt7623_pcie2_0_perst_pins[] = { 24, }; -static int mt7623_pcie2_0_perst_funcs[] = { 2, }; -static int mt7623_pcie2_1_perst_pins[] = { 29, }; -static int mt7623_pcie2_1_perst_funcs[] = { 6, }; -static int mt7623_pcie0_0_wake_pins[] = { 28, }; -static int mt7623_pcie0_0_wake_funcs[] = { 6, }; -static int mt7623_pcie0_1_wake_pins[] = { 251, }; -static int mt7623_pcie0_1_wake_funcs[] = { 6, }; -static int mt7623_pcie1_0_wake_pins[] = { 27, }; -static int mt7623_pcie1_0_wake_funcs[] = { 6, }; -static int mt7623_pcie1_1_wake_pins[] = { 253, }; -static int mt7623_pcie1_1_wake_funcs[] = { 6, }; -static int mt7623_pcie2_0_wake_pins[] = { 26, }; -static int mt7623_pcie2_0_wake_funcs[] = { 6, }; -static int mt7623_pcie2_1_wake_pins[] = { 255, }; -static int mt7623_pcie2_1_wake_funcs[] = { 6, }; -static int mt7623_pcie0_clkreq_pins[] = { 250, }; -static int mt7623_pcie0_clkreq_funcs[] = { 6, }; -static int mt7623_pcie1_clkreq_pins[] = { 252, }; -static int mt7623_pcie1_clkreq_funcs[] = { 6, }; -static int mt7623_pcie2_clkreq_pins[] = { 254, }; -static int mt7623_pcie2_clkreq_funcs[] = { 6, }; +static const int mt7623_pcie0_0_perst_pins[] = { 208, }; +static const int mt7623_pcie0_0_perst_funcs[] = { 3, }; +static const int mt7623_pcie0_1_perst_pins[] = { 22, }; +static const int mt7623_pcie0_1_perst_funcs[] = { 2, }; +static const int mt7623_pcie1_0_perst_pins[] = { 209, }; +static const int mt7623_pcie1_0_perst_funcs[] = { 3, }; +static const int mt7623_pcie1_1_perst_pins[] = { 23, }; +static const int mt7623_pcie1_1_perst_funcs[] = { 2, }; +static const int mt7623_pcie2_0_perst_pins[] = { 24, }; +static const int mt7623_pcie2_0_perst_funcs[] = { 2, }; +static const int mt7623_pcie2_1_perst_pins[] = { 29, }; +static const int mt7623_pcie2_1_perst_funcs[] = { 6, }; +static const int mt7623_pcie0_0_wake_pins[] = { 28, }; +static const int mt7623_pcie0_0_wake_funcs[] = { 6, }; +static const int mt7623_pcie0_1_wake_pins[] = { 251, }; +static const int mt7623_pcie0_1_wake_funcs[] = { 6, }; +static const int mt7623_pcie1_0_wake_pins[] = { 27, }; +static const int mt7623_pcie1_0_wake_funcs[] = { 6, }; +static const int mt7623_pcie1_1_wake_pins[] = { 253, }; +static const int mt7623_pcie1_1_wake_funcs[] = { 6, }; +static const int mt7623_pcie2_0_wake_pins[] = { 26, }; +static const int mt7623_pcie2_0_wake_funcs[] = { 6, }; +static const int mt7623_pcie2_1_wake_pins[] = { 255, }; +static const int mt7623_pcie2_1_wake_funcs[] = { 6, }; +static const int mt7623_pcie0_clkreq_pins[] = { 250, }; +static const int mt7623_pcie0_clkreq_funcs[] = { 6, }; +static const int mt7623_pcie1_clkreq_pins[] = { 252, }; +static const int mt7623_pcie1_clkreq_funcs[] = { 6, }; +static const int mt7623_pcie2_clkreq_pins[] = { 254, }; +static const int mt7623_pcie2_clkreq_funcs[] = { 6, }; /* the pcie_*_rev are only used for MT7623 */ -static int mt7623_pcie0_0_rev_perst_pins[] = { 208, }; -static int mt7623_pcie0_0_rev_perst_funcs[] = { 11, }; -static int mt7623_pcie0_1_rev_perst_pins[] = { 22, }; -static int mt7623_pcie0_1_rev_perst_funcs[] = { 10, }; -static int mt7623_pcie1_0_rev_perst_pins[] = { 209, }; -static int mt7623_pcie1_0_rev_perst_funcs[] = { 11, }; -static int mt7623_pcie1_1_rev_perst_pins[] = { 23, }; -static int mt7623_pcie1_1_rev_perst_funcs[] = { 10, }; -static int mt7623_pcie2_0_rev_perst_pins[] = { 24, }; -static int mt7623_pcie2_0_rev_perst_funcs[] = { 11, }; -static int mt7623_pcie2_1_rev_perst_pins[] = { 29, }; -static int mt7623_pcie2_1_rev_perst_funcs[] = { 14, }; +static const int mt7623_pcie0_0_rev_perst_pins[] = { 208, }; +static const int mt7623_pcie0_0_rev_perst_funcs[] = { 11, }; +static const int mt7623_pcie0_1_rev_perst_pins[] = { 22, }; +static const int mt7623_pcie0_1_rev_perst_funcs[] = { 10, }; +static const int mt7623_pcie1_0_rev_perst_pins[] = { 209, }; +static const int mt7623_pcie1_0_rev_perst_funcs[] = { 11, }; +static const int mt7623_pcie1_1_rev_perst_pins[] = { 23, }; +static const int mt7623_pcie1_1_rev_perst_funcs[] = { 10, }; +static const int mt7623_pcie2_0_rev_perst_pins[] = { 24, }; +static const int mt7623_pcie2_0_rev_perst_funcs[] = { 11, }; +static const int mt7623_pcie2_1_rev_perst_pins[] = { 29, }; +static const int mt7623_pcie2_1_rev_perst_funcs[] = { 14, }; /* PCM */ -static int mt7623_pcm_clk_0_pins[] = { 18, }; -static int mt7623_pcm_clk_0_funcs[] = { 1, }; -static int mt7623_pcm_clk_1_pins[] = { 17, }; -static int mt7623_pcm_clk_1_funcs[] = { 3, }; -static int mt7623_pcm_clk_2_pins[] = { 35, }; -static int mt7623_pcm_clk_2_funcs[] = { 3, }; -static int mt7623_pcm_clk_3_pins[] = { 50, }; -static int mt7623_pcm_clk_3_funcs[] = { 3, }; -static int mt7623_pcm_clk_4_pins[] = { 74, }; -static int mt7623_pcm_clk_4_funcs[] = { 3, }; -static int mt7623_pcm_clk_5_pins[] = { 191, }; -static int mt7623_pcm_clk_5_funcs[] = { 3, }; -static int mt7623_pcm_clk_6_pins[] = { 196, }; -static int mt7623_pcm_clk_6_funcs[] = { 3, }; -static int mt7623_pcm_sync_0_pins[] = { 19, }; -static int mt7623_pcm_sync_0_funcs[] = { 1, }; -static int mt7623_pcm_sync_1_pins[] = { 30, }; -static int mt7623_pcm_sync_1_funcs[] = { 3, }; -static int mt7623_pcm_sync_2_pins[] = { 36, }; -static int mt7623_pcm_sync_2_funcs[] = { 3, }; -static int mt7623_pcm_sync_3_pins[] = { 52, }; -static int mt7623_pcm_sync_3_funcs[] = { 31, }; -static int mt7623_pcm_sync_4_pins[] = { 73, }; -static int mt7623_pcm_sync_4_funcs[] = { 3, }; -static int mt7623_pcm_sync_5_pins[] = { 192, }; -static int mt7623_pcm_sync_5_funcs[] = { 3, }; -static int mt7623_pcm_sync_6_pins[] = { 197, }; -static int mt7623_pcm_sync_6_funcs[] = { 3, }; -static int mt7623_pcm_rx_0_pins[] = { 20, }; -static int mt7623_pcm_rx_0_funcs[] = { 1, }; -static int mt7623_pcm_rx_1_pins[] = { 16, }; -static int mt7623_pcm_rx_1_funcs[] = { 3, }; -static int mt7623_pcm_rx_2_pins[] = { 34, }; -static int mt7623_pcm_rx_2_funcs[] = { 3, }; -static int mt7623_pcm_rx_3_pins[] = { 51, }; -static int mt7623_pcm_rx_3_funcs[] = { 3, }; -static int mt7623_pcm_rx_4_pins[] = { 72, }; -static int mt7623_pcm_rx_4_funcs[] = { 3, }; -static int mt7623_pcm_rx_5_pins[] = { 190, }; -static int mt7623_pcm_rx_5_funcs[] = { 3, }; -static int mt7623_pcm_rx_6_pins[] = { 195, }; -static int mt7623_pcm_rx_6_funcs[] = { 3, }; -static int mt7623_pcm_tx_0_pins[] = { 21, }; -static int mt7623_pcm_tx_0_funcs[] = { 1, }; -static int mt7623_pcm_tx_1_pins[] = { 32, }; -static int mt7623_pcm_tx_1_funcs[] = { 3, }; -static int mt7623_pcm_tx_2_pins[] = { 33, }; -static int mt7623_pcm_tx_2_funcs[] = { 3, }; -static int mt7623_pcm_tx_3_pins[] = { 38, }; -static int mt7623_pcm_tx_3_funcs[] = { 3, }; -static int mt7623_pcm_tx_4_pins[] = { 49, }; -static int mt7623_pcm_tx_4_funcs[] = { 3, }; -static int mt7623_pcm_tx_5_pins[] = { 189, }; -static int mt7623_pcm_tx_5_funcs[] = { 3, }; -static int mt7623_pcm_tx_6_pins[] = { 194, }; -static int mt7623_pcm_tx_6_funcs[] = { 3, }; +static const int mt7623_pcm_clk_0_pins[] = { 18, }; +static const int mt7623_pcm_clk_0_funcs[] = { 1, }; +static const int mt7623_pcm_clk_1_pins[] = { 17, }; +static const int mt7623_pcm_clk_1_funcs[] = { 3, }; +static const int mt7623_pcm_clk_2_pins[] = { 35, }; +static const int mt7623_pcm_clk_2_funcs[] = { 3, }; +static const int mt7623_pcm_clk_3_pins[] = { 50, }; +static const int mt7623_pcm_clk_3_funcs[] = { 3, }; +static const int mt7623_pcm_clk_4_pins[] = { 74, }; +static const int mt7623_pcm_clk_4_funcs[] = { 3, }; +static const int mt7623_pcm_clk_5_pins[] = { 191, }; +static const int mt7623_pcm_clk_5_funcs[] = { 3, }; +static const int mt7623_pcm_clk_6_pins[] = { 196, }; +static const int mt7623_pcm_clk_6_funcs[] = { 3, }; +static const int mt7623_pcm_sync_0_pins[] = { 19, }; +static const int mt7623_pcm_sync_0_funcs[] = { 1, }; +static const int mt7623_pcm_sync_1_pins[] = { 30, }; +static const int mt7623_pcm_sync_1_funcs[] = { 3, }; +static const int mt7623_pcm_sync_2_pins[] = { 36, }; +static const int mt7623_pcm_sync_2_funcs[] = { 3, }; +static const int mt7623_pcm_sync_3_pins[] = { 52, }; +static const int mt7623_pcm_sync_3_funcs[] = { 31, }; +static const int mt7623_pcm_sync_4_pins[] = { 73, }; +static const int mt7623_pcm_sync_4_funcs[] = { 3, }; +static const int mt7623_pcm_sync_5_pins[] = { 192, }; +static const int mt7623_pcm_sync_5_funcs[] = { 3, }; +static const int mt7623_pcm_sync_6_pins[] = { 197, }; +static const int mt7623_pcm_sync_6_funcs[] = { 3, }; +static const int mt7623_pcm_rx_0_pins[] = { 20, }; +static const int mt7623_pcm_rx_0_funcs[] = { 1, }; +static const int mt7623_pcm_rx_1_pins[] = { 16, }; +static const int mt7623_pcm_rx_1_funcs[] = { 3, }; +static const int mt7623_pcm_rx_2_pins[] = { 34, }; +static const int mt7623_pcm_rx_2_funcs[] = { 3, }; +static const int mt7623_pcm_rx_3_pins[] = { 51, }; +static const int mt7623_pcm_rx_3_funcs[] = { 3, }; +static const int mt7623_pcm_rx_4_pins[] = { 72, }; +static const int mt7623_pcm_rx_4_funcs[] = { 3, }; +static const int mt7623_pcm_rx_5_pins[] = { 190, }; +static const int mt7623_pcm_rx_5_funcs[] = { 3, }; +static const int mt7623_pcm_rx_6_pins[] = { 195, }; +static const int mt7623_pcm_rx_6_funcs[] = { 3, }; +static const int mt7623_pcm_tx_0_pins[] = { 21, }; +static const int mt7623_pcm_tx_0_funcs[] = { 1, }; +static const int mt7623_pcm_tx_1_pins[] = { 32, }; +static const int mt7623_pcm_tx_1_funcs[] = { 3, }; +static const int mt7623_pcm_tx_2_pins[] = { 33, }; +static const int mt7623_pcm_tx_2_funcs[] = { 3, }; +static const int mt7623_pcm_tx_3_pins[] = { 38, }; +static const int mt7623_pcm_tx_3_funcs[] = { 3, }; +static const int mt7623_pcm_tx_4_pins[] = { 49, }; +static const int mt7623_pcm_tx_4_funcs[] = { 3, }; +static const int mt7623_pcm_tx_5_pins[] = { 189, }; +static const int mt7623_pcm_tx_5_funcs[] = { 3, }; +static const int mt7623_pcm_tx_6_pins[] = { 194, }; +static const int mt7623_pcm_tx_6_funcs[] = { 3, }; /* PWM */ -static int mt7623_pwm_ch1_0_pins[] = { 203, }; -static int mt7623_pwm_ch1_0_funcs[] = { 1, }; -static int mt7623_pwm_ch1_1_pins[] = { 208, }; -static int mt7623_pwm_ch1_1_funcs[] = { 2, }; -static int mt7623_pwm_ch1_2_pins[] = { 72, }; -static int mt7623_pwm_ch1_2_funcs[] = { 4, }; -static int mt7623_pwm_ch1_3_pins[] = { 88, }; -static int mt7623_pwm_ch1_3_funcs[] = { 3, }; -static int mt7623_pwm_ch1_4_pins[] = { 108, }; -static int mt7623_pwm_ch1_4_funcs[] = { 3, }; -static int mt7623_pwm_ch2_0_pins[] = { 204, }; -static int mt7623_pwm_ch2_0_funcs[] = { 1, }; -static int mt7623_pwm_ch2_1_pins[] = { 53, }; -static int mt7623_pwm_ch2_1_funcs[] = { 5, }; -static int mt7623_pwm_ch2_2_pins[] = { 88, }; -static int mt7623_pwm_ch2_2_funcs[] = { 6, }; -static int mt7623_pwm_ch2_3_pins[] = { 108, }; -static int mt7623_pwm_ch2_3_funcs[] = { 6, }; -static int mt7623_pwm_ch2_4_pins[] = { 209, }; -static int mt7623_pwm_ch2_4_funcs[] = { 5, }; -static int mt7623_pwm_ch3_0_pins[] = { 205, }; -static int mt7623_pwm_ch3_0_funcs[] = { 1, }; -static int mt7623_pwm_ch3_1_pins[] = { 55, }; -static int mt7623_pwm_ch3_1_funcs[] = { 5, }; -static int mt7623_pwm_ch3_2_pins[] = { 89, }; -static int mt7623_pwm_ch3_2_funcs[] = { 6, }; -static int mt7623_pwm_ch3_3_pins[] = { 109, }; -static int mt7623_pwm_ch3_3_funcs[] = { 6, }; -static int mt7623_pwm_ch4_0_pins[] = { 206, }; -static int mt7623_pwm_ch4_0_funcs[] = { 1, }; -static int mt7623_pwm_ch4_1_pins[] = { 90, }; -static int mt7623_pwm_ch4_1_funcs[] = { 6, }; -static int mt7623_pwm_ch4_2_pins[] = { 110, }; -static int mt7623_pwm_ch4_2_funcs[] = { 6, }; -static int mt7623_pwm_ch4_3_pins[] = { 124, }; -static int mt7623_pwm_ch4_3_funcs[] = { 5, }; -static int mt7623_pwm_ch5_0_pins[] = { 207, }; -static int mt7623_pwm_ch5_0_funcs[] = { 1, }; -static int mt7623_pwm_ch5_1_pins[] = { 125, }; -static int mt7623_pwm_ch5_1_funcs[] = { 5, }; +static const int mt7623_pwm_ch1_0_pins[] = { 203, }; +static const int mt7623_pwm_ch1_0_funcs[] = { 1, }; +static const int mt7623_pwm_ch1_1_pins[] = { 208, }; +static const int mt7623_pwm_ch1_1_funcs[] = { 2, }; +static const int mt7623_pwm_ch1_2_pins[] = { 72, }; +static const int mt7623_pwm_ch1_2_funcs[] = { 4, }; +static const int mt7623_pwm_ch1_3_pins[] = { 88, }; +static const int mt7623_pwm_ch1_3_funcs[] = { 3, }; +static const int mt7623_pwm_ch1_4_pins[] = { 108, }; +static const int mt7623_pwm_ch1_4_funcs[] = { 3, }; +static const int mt7623_pwm_ch2_0_pins[] = { 204, }; +static const int mt7623_pwm_ch2_0_funcs[] = { 1, }; +static const int mt7623_pwm_ch2_1_pins[] = { 53, }; +static const int mt7623_pwm_ch2_1_funcs[] = { 5, }; +static const int mt7623_pwm_ch2_2_pins[] = { 88, }; +static const int mt7623_pwm_ch2_2_funcs[] = { 6, }; +static const int mt7623_pwm_ch2_3_pins[] = { 108, }; +static const int mt7623_pwm_ch2_3_funcs[] = { 6, }; +static const int mt7623_pwm_ch2_4_pins[] = { 209, }; +static const int mt7623_pwm_ch2_4_funcs[] = { 5, }; +static const int mt7623_pwm_ch3_0_pins[] = { 205, }; +static const int mt7623_pwm_ch3_0_funcs[] = { 1, }; +static const int mt7623_pwm_ch3_1_pins[] = { 55, }; +static const int mt7623_pwm_ch3_1_funcs[] = { 5, }; +static const int mt7623_pwm_ch3_2_pins[] = { 89, }; +static const int mt7623_pwm_ch3_2_funcs[] = { 6, }; +static const int mt7623_pwm_ch3_3_pins[] = { 109, }; +static const int mt7623_pwm_ch3_3_funcs[] = { 6, }; +static const int mt7623_pwm_ch4_0_pins[] = { 206, }; +static const int mt7623_pwm_ch4_0_funcs[] = { 1, }; +static const int mt7623_pwm_ch4_1_pins[] = { 90, }; +static const int mt7623_pwm_ch4_1_funcs[] = { 6, }; +static const int mt7623_pwm_ch4_2_pins[] = { 110, }; +static const int mt7623_pwm_ch4_2_funcs[] = { 6, }; +static const int mt7623_pwm_ch4_3_pins[] = { 124, }; +static const int mt7623_pwm_ch4_3_funcs[] = { 5, }; +static const int mt7623_pwm_ch5_0_pins[] = { 207, }; +static const int mt7623_pwm_ch5_0_funcs[] = { 1, }; +static const int mt7623_pwm_ch5_1_pins[] = { 125, }; +static const int mt7623_pwm_ch5_1_funcs[] = { 5, }; /* PWRAP */ -static int mt7623_pwrap_pins[] = { 0, 1, 2, 3, 4, 5, 6, }; -static int mt7623_pwrap_funcs[] = { 1, 1, 1, 1, 1, 1, 1, }; +static const int mt7623_pwrap_pins[] = { 0, 1, 2, 3, 4, 5, 6, }; +static const int mt7623_pwrap_funcs[] = { 1, 1, 1, 1, 1, 1, 1, }; /* SPDIF */ -static int mt7623_spdif_in0_0_pins[] = { 56, }; -static int mt7623_spdif_in0_0_funcs[] = { 3, }; -static int mt7623_spdif_in0_1_pins[] = { 201, }; -static int mt7623_spdif_in0_1_funcs[] = { 1, }; -static int mt7623_spdif_in1_0_pins[] = { 54, }; -static int mt7623_spdif_in1_0_funcs[] = { 3, }; -static int mt7623_spdif_in1_1_pins[] = { 202, }; -static int mt7623_spdif_in1_1_funcs[] = { 1, }; -static int mt7623_spdif_out_pins[] = { 202, }; -static int mt7623_spdif_out_funcs[] = { 1, }; +static const int mt7623_spdif_in0_0_pins[] = { 56, }; +static const int mt7623_spdif_in0_0_funcs[] = { 3, }; +static const int mt7623_spdif_in0_1_pins[] = { 201, }; +static const int mt7623_spdif_in0_1_funcs[] = { 1, }; +static const int mt7623_spdif_in1_0_pins[] = { 54, }; +static const int mt7623_spdif_in1_0_funcs[] = { 3, }; +static const int mt7623_spdif_in1_1_pins[] = { 202, }; +static const int mt7623_spdif_in1_1_funcs[] = { 1, }; +static const int mt7623_spdif_out_pins[] = { 202, }; +static const int mt7623_spdif_out_funcs[] = { 1, }; /* SPI */ -static int mt7623_spi0_pins[] = { 53, 54, 55, 56, }; -static int mt7623_spi0_funcs[] = { 1, 1, 1, 1, }; -static int mt7623_spi1_pins[] = { 7, 199, 8, 9, }; -static int mt7623_spi1_funcs[] = { 1, 1, 1, 1, }; -static int mt7623_spi2_pins[] = { 101, 104, 102, 103, }; -static int mt7623_spi2_funcs[] = { 1, 1, 1, 1, }; +static const int mt7623_spi0_pins[] = { 53, 54, 55, 56, }; +static const int mt7623_spi0_funcs[] = { 1, 1, 1, 1, }; +static const int mt7623_spi1_pins[] = { 7, 199, 8, 9, }; +static const int mt7623_spi1_funcs[] = { 1, 1, 1, 1, }; +static const int mt7623_spi2_pins[] = { 101, 104, 102, 103, }; +static const int mt7623_spi2_funcs[] = { 1, 1, 1, 1, }; /* UART */ -static int mt7623_uart0_0_txd_rxd_pins[] = { 79, 80, }; -static int mt7623_uart0_0_txd_rxd_funcs[] = { 1, 1, }; -static int mt7623_uart0_1_txd_rxd_pins[] = { 87, 88, }; -static int mt7623_uart0_1_txd_rxd_funcs[] = { 5, 5, }; -static int mt7623_uart0_2_txd_rxd_pins[] = { 107, 108, }; -static int mt7623_uart0_2_txd_rxd_funcs[] = { 5, 5, }; -static int mt7623_uart0_3_txd_rxd_pins[] = { 123, 122, }; -static int mt7623_uart0_3_txd_rxd_funcs[] = { 5, 5, }; -static int mt7623_uart0_rts_cts_pins[] = { 22, 23, }; -static int mt7623_uart0_rts_cts_funcs[] = { 1, 1, }; -static int mt7623_uart1_0_txd_rxd_pins[] = { 81, 82, }; -static int mt7623_uart1_0_txd_rxd_funcs[] = { 1, 1, }; -static int mt7623_uart1_1_txd_rxd_pins[] = { 89, 90, }; -static int mt7623_uart1_1_txd_rxd_funcs[] = { 5, 5, }; -static int mt7623_uart1_2_txd_rxd_pins[] = { 109, 110, }; -static int mt7623_uart1_2_txd_rxd_funcs[] = { 5, 5, }; -static int mt7623_uart1_rts_cts_pins[] = { 24, 25, }; -static int mt7623_uart1_rts_cts_funcs[] = { 1, 1, }; -static int mt7623_uart2_0_txd_rxd_pins[] = { 14, 15, }; -static int mt7623_uart2_0_txd_rxd_funcs[] = { 1, 1, }; -static int mt7623_uart2_1_txd_rxd_pins[] = { 200, 201, }; -static int mt7623_uart2_1_txd_rxd_funcs[] = { 6, 6, }; -static int mt7623_uart2_rts_cts_pins[] = { 242, 243, }; -static int mt7623_uart2_rts_cts_funcs[] = { 1, 1, }; -static int mt7623_uart3_txd_rxd_pins[] = { 242, 243, }; -static int mt7623_uart3_txd_rxd_funcs[] = { 2, 2, }; -static int mt7623_uart3_rts_cts_pins[] = { 26, 27, }; -static int mt7623_uart3_rts_cts_funcs[] = { 1, 1, }; +static const int mt7623_uart0_0_txd_rxd_pins[] = { 79, 80, }; +static const int mt7623_uart0_0_txd_rxd_funcs[] = { 1, 1, }; +static const int mt7623_uart0_1_txd_rxd_pins[] = { 87, 88, }; +static const int mt7623_uart0_1_txd_rxd_funcs[] = { 5, 5, }; +static const int mt7623_uart0_2_txd_rxd_pins[] = { 107, 108, }; +static const int mt7623_uart0_2_txd_rxd_funcs[] = { 5, 5, }; +static const int mt7623_uart0_3_txd_rxd_pins[] = { 123, 122, }; +static const int mt7623_uart0_3_txd_rxd_funcs[] = { 5, 5, }; +static const int mt7623_uart0_rts_cts_pins[] = { 22, 23, }; +static const int mt7623_uart0_rts_cts_funcs[] = { 1, 1, }; +static const int mt7623_uart1_0_txd_rxd_pins[] = { 81, 82, }; +static const int mt7623_uart1_0_txd_rxd_funcs[] = { 1, 1, }; +static const int mt7623_uart1_1_txd_rxd_pins[] = { 89, 90, }; +static const int mt7623_uart1_1_txd_rxd_funcs[] = { 5, 5, }; +static const int mt7623_uart1_2_txd_rxd_pins[] = { 109, 110, }; +static const int mt7623_uart1_2_txd_rxd_funcs[] = { 5, 5, }; +static const int mt7623_uart1_rts_cts_pins[] = { 24, 25, }; +static const int mt7623_uart1_rts_cts_funcs[] = { 1, 1, }; +static const int mt7623_uart2_0_txd_rxd_pins[] = { 14, 15, }; +static const int mt7623_uart2_0_txd_rxd_funcs[] = { 1, 1, }; +static const int mt7623_uart2_1_txd_rxd_pins[] = { 200, 201, }; +static const int mt7623_uart2_1_txd_rxd_funcs[] = { 6, 6, }; +static const int mt7623_uart2_rts_cts_pins[] = { 242, 243, }; +static const int mt7623_uart2_rts_cts_funcs[] = { 1, 1, }; +static const int mt7623_uart3_txd_rxd_pins[] = { 242, 243, }; +static const int mt7623_uart3_txd_rxd_funcs[] = { 2, 2, }; +static const int mt7623_uart3_rts_cts_pins[] = { 26, 27, }; +static const int mt7623_uart3_rts_cts_funcs[] = { 1, 1, }; /* Watchdog */ -static int mt7623_watchdog_0_pins[] = { 11, }; -static int mt7623_watchdog_0_funcs[] = { 1, }; -static int mt7623_watchdog_1_pins[] = { 121, }; -static int mt7623_watchdog_1_funcs[] = { 5, }; +static const int mt7623_watchdog_0_pins[] = { 11, }; +static const int mt7623_watchdog_0_funcs[] = { 1, }; +static const int mt7623_watchdog_1_pins[] = { 121, }; +static const int mt7623_watchdog_1_funcs[] = { 5, }; static const struct mtk_group_desc mt7623_groups[] = { PINCTRL_PIN_GROUP("aud_ext_clk0", mt7623_aud_ext_clk0), @@ -1362,7 +1362,7 @@ static const struct mtk_function_desc mt7623_functions[] = { {"watchdog", mt7623_wdt_groups, ARRAY_SIZE(mt7623_wdt_groups)}, }; -static struct mtk_pinctrl_soc mt7623_data = { +static const struct mtk_pinctrl_soc mt7623_data = { .name = "mt7623_pinctrl", .reg_cal = mt7623_reg_cals, .pins = mt7623_pins, diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7629.c b/drivers/pinctrl/mediatek/pinctrl-mt7629.c index 5d4bec22346..45d4def316d 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7629.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7629.c @@ -180,118 +180,118 @@ static const struct mtk_pin_desc mt7629_pins[] = { */ /* WF 5G */ -static int mt7629_wf0_5g_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, }; -static int mt7629_wf0_5g_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; +static const int mt7629_wf0_5g_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, }; +static const int mt7629_wf0_5g_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; /* LED for EPHY */ -static int mt7629_ephy_leds_pins[] = { 12, 13, 14, 15, 16, 17, 18, }; -static int mt7629_ephy_leds_funcs[] = { 1, 1, 1, 1, 1, 1, 1, }; -static int mt7629_ephy_led0_pins[] = { 12, }; -static int mt7629_ephy_led0_funcs[] = { 1, }; -static int mt7629_ephy_led1_pins[] = { 13, }; -static int mt7629_ephy_led1_funcs[] = { 1, }; -static int mt7629_ephy_led2_pins[] = { 14, }; -static int mt7629_ephy_led2_funcs[] = { 1, }; -static int mt7629_ephy_led3_pins[] = { 15, }; -static int mt7629_ephy_led3_funcs[] = { 1, }; -static int mt7629_ephy_led4_pins[] = { 16, }; -static int mt7629_ephy_led4_funcs[] = { 1, }; -static int mt7629_wf2g_led_pins[] = { 17, }; -static int mt7629_wf2g_led_funcs[] = { 1, }; -static int mt7629_wf5g_led_pins[] = { 18, }; -static int mt7629_wf5g_led_funcs[] = { 1, }; +static const int mt7629_ephy_leds_pins[] = { 12, 13, 14, 15, 16, 17, 18, }; +static const int mt7629_ephy_leds_funcs[] = { 1, 1, 1, 1, 1, 1, 1, }; +static const int mt7629_ephy_led0_pins[] = { 12, }; +static const int mt7629_ephy_led0_funcs[] = { 1, }; +static const int mt7629_ephy_led1_pins[] = { 13, }; +static const int mt7629_ephy_led1_funcs[] = { 1, }; +static const int mt7629_ephy_led2_pins[] = { 14, }; +static const int mt7629_ephy_led2_funcs[] = { 1, }; +static const int mt7629_ephy_led3_pins[] = { 15, }; +static const int mt7629_ephy_led3_funcs[] = { 1, }; +static const int mt7629_ephy_led4_pins[] = { 16, }; +static const int mt7629_ephy_led4_funcs[] = { 1, }; +static const int mt7629_wf2g_led_pins[] = { 17, }; +static const int mt7629_wf2g_led_funcs[] = { 1, }; +static const int mt7629_wf5g_led_pins[] = { 18, }; +static const int mt7629_wf5g_led_funcs[] = { 1, }; /* LED for EPHY used as JTAG */ -static int mt7629_ephy_leds_jtag_pins[] = { 12, 13, 14, 15, 16, }; -static int mt7629_ephy_leds_jtag_funcs[] = { 7, 7, 7, 7, 7, }; +static const int mt7629_ephy_leds_jtag_pins[] = { 12, 13, 14, 15, 16, }; +static const int mt7629_ephy_leds_jtag_funcs[] = { 7, 7, 7, 7, 7, }; /* Watchdog */ -static int mt7629_watchdog_pins[] = { 11, }; -static int mt7629_watchdog_funcs[] = { 1, }; +static const int mt7629_watchdog_pins[] = { 11, }; +static const int mt7629_watchdog_funcs[] = { 1, }; /* LED for GPHY */ -static int mt7629_gphy_leds_0_pins[] = { 21, 22, 23, }; -static int mt7629_gphy_leds_0_funcs[] = { 2, 2, 2, }; -static int mt7629_gphy_led1_0_pins[] = { 21, }; -static int mt7629_gphy_led1_0_funcs[] = { 2, }; -static int mt7629_gphy_led2_0_pins[] = { 22, }; -static int mt7629_gphy_led2_0_funcs[] = { 2, }; -static int mt7629_gphy_led3_0_pins[] = { 23, }; -static int mt7629_gphy_led3_0_funcs[] = { 2, }; -static int mt7629_gphy_leds_1_pins[] = { 57, 58, 59, }; -static int mt7629_gphy_leds_1_funcs[] = { 1, 1, 1, }; -static int mt7629_gphy_led1_1_pins[] = { 57, }; -static int mt7629_gphy_led1_1_funcs[] = { 1, }; -static int mt7629_gphy_led2_1_pins[] = { 58, }; -static int mt7629_gphy_led2_1_funcs[] = { 1, }; -static int mt7629_gphy_led3_1_pins[] = { 59, }; -static int mt7629_gphy_led3_1_funcs[] = { 1, }; +static const int mt7629_gphy_leds_0_pins[] = { 21, 22, 23, }; +static const int mt7629_gphy_leds_0_funcs[] = { 2, 2, 2, }; +static const int mt7629_gphy_led1_0_pins[] = { 21, }; +static const int mt7629_gphy_led1_0_funcs[] = { 2, }; +static const int mt7629_gphy_led2_0_pins[] = { 22, }; +static const int mt7629_gphy_led2_0_funcs[] = { 2, }; +static const int mt7629_gphy_led3_0_pins[] = { 23, }; +static const int mt7629_gphy_led3_0_funcs[] = { 2, }; +static const int mt7629_gphy_leds_1_pins[] = { 57, 58, 59, }; +static const int mt7629_gphy_leds_1_funcs[] = { 1, 1, 1, }; +static const int mt7629_gphy_led1_1_pins[] = { 57, }; +static const int mt7629_gphy_led1_1_funcs[] = { 1, }; +static const int mt7629_gphy_led2_1_pins[] = { 58, }; +static const int mt7629_gphy_led2_1_funcs[] = { 1, }; +static const int mt7629_gphy_led3_1_pins[] = { 59, }; +static const int mt7629_gphy_led3_1_funcs[] = { 1, }; /* I2C */ -static int mt7629_i2c_0_pins[] = { 19, 20, }; -static int mt7629_i2c_0_funcs[] = { 1, 1, }; -static int mt7629_i2c_1_pins[] = { 53, 54, }; -static int mt7629_i2c_1_funcs[] = { 1, 1, }; +static const int mt7629_i2c_0_pins[] = { 19, 20, }; +static const int mt7629_i2c_0_funcs[] = { 1, 1, }; +static const int mt7629_i2c_1_pins[] = { 53, 54, }; +static const int mt7629_i2c_1_funcs[] = { 1, 1, }; /* SPI */ -static int mt7629_spi_0_pins[] = { 21, 22, 23, 24, }; -static int mt7629_spi_0_funcs[] = { 1, 1, 1, 1, }; -static int mt7629_spi_1_pins[] = { 62, 63, 64, 65, }; -static int mt7629_spi_1_funcs[] = { 1, 1, 1, 1, }; -static int mt7629_spi_wp_pins[] = { 66, }; -static int mt7629_spi_wp_funcs[] = { 1, }; -static int mt7629_spi_hold_pins[] = { 67, }; -static int mt7629_spi_hold_funcs[] = { 1, }; +static const int mt7629_spi_0_pins[] = { 21, 22, 23, 24, }; +static const int mt7629_spi_0_funcs[] = { 1, 1, 1, 1, }; +static const int mt7629_spi_1_pins[] = { 62, 63, 64, 65, }; +static const int mt7629_spi_1_funcs[] = { 1, 1, 1, 1, }; +static const int mt7629_spi_wp_pins[] = { 66, }; +static const int mt7629_spi_wp_funcs[] = { 1, }; +static const int mt7629_spi_hold_pins[] = { 67, }; +static const int mt7629_spi_hold_funcs[] = { 1, }; /* UART */ -static int mt7629_uart1_0_txd_rxd_pins[] = { 25, 26, }; -static int mt7629_uart1_0_txd_rxd_funcs[] = { 1, 1, }; -static int mt7629_uart1_1_txd_rxd_pins[] = { 53, 54, }; -static int mt7629_uart1_1_txd_rxd_funcs[] = { 2, 2, }; -static int mt7629_uart2_0_txd_rxd_pins[] = { 29, 30, }; -static int mt7629_uart2_0_txd_rxd_funcs[] = { 1, 1, }; -static int mt7629_uart2_1_txd_rxd_pins[] = { 57, 58, }; -static int mt7629_uart2_1_txd_rxd_funcs[] = { 2, 2, }; -static int mt7629_uart1_0_cts_rts_pins[] = { 27, 28, }; -static int mt7629_uart1_0_cts_rts_funcs[] = { 1, 1, }; -static int mt7629_uart1_1_cts_rts_pins[] = { 55, 56, }; -static int mt7629_uart1_1_cts_rts_funcs[] = { 2, 2, }; -static int mt7629_uart2_0_cts_rts_pins[] = { 31, 32, }; -static int mt7629_uart2_0_cts_rts_funcs[] = { 1, 1, }; -static int mt7629_uart2_1_cts_rts_pins[] = { 59, 60, }; -static int mt7629_uart2_1_cts_rts_funcs[] = { 2, 2, }; -static int mt7629_uart0_txd_rxd_pins[] = { 68, 69, }; -static int mt7629_uart0_txd_rxd_funcs[] = { 1, 1, }; +static const int mt7629_uart1_0_txd_rxd_pins[] = { 25, 26, }; +static const int mt7629_uart1_0_txd_rxd_funcs[] = { 1, 1, }; +static const int mt7629_uart1_1_txd_rxd_pins[] = { 53, 54, }; +static const int mt7629_uart1_1_txd_rxd_funcs[] = { 2, 2, }; +static const int mt7629_uart2_0_txd_rxd_pins[] = { 29, 30, }; +static const int mt7629_uart2_0_txd_rxd_funcs[] = { 1, 1, }; +static const int mt7629_uart2_1_txd_rxd_pins[] = { 57, 58, }; +static const int mt7629_uart2_1_txd_rxd_funcs[] = { 2, 2, }; +static const int mt7629_uart1_0_cts_rts_pins[] = { 27, 28, }; +static const int mt7629_uart1_0_cts_rts_funcs[] = { 1, 1, }; +static const int mt7629_uart1_1_cts_rts_pins[] = { 55, 56, }; +static const int mt7629_uart1_1_cts_rts_funcs[] = { 2, 2, }; +static const int mt7629_uart2_0_cts_rts_pins[] = { 31, 32, }; +static const int mt7629_uart2_0_cts_rts_funcs[] = { 1, 1, }; +static const int mt7629_uart2_1_cts_rts_pins[] = { 59, 60, }; +static const int mt7629_uart2_1_cts_rts_funcs[] = { 2, 2, }; +static const int mt7629_uart0_txd_rxd_pins[] = { 68, 69, }; +static const int mt7629_uart0_txd_rxd_funcs[] = { 1, 1, }; /* MDC/MDIO */ -static int mt7629_mdc_mdio_pins[] = { 49, 50, }; -static int mt7629_mdc_mdio_funcs[] = { 1, 1, }; +static const int mt7629_mdc_mdio_pins[] = { 49, 50, }; +static const int mt7629_mdc_mdio_funcs[] = { 1, 1, }; /* PCIE */ -static int mt7629_pcie_pereset_pins[] = { 51, }; -static int mt7629_pcie_pereset_funcs[] = { 1, }; -static int mt7629_pcie_wake_pins[] = { 55, }; -static int mt7629_pcie_wake_funcs[] = { 1, }; -static int mt7629_pcie_clkreq_pins[] = { 56, }; -static int mt7629_pcie_clkreq_funcs[] = { 1, }; +static const int mt7629_pcie_pereset_pins[] = { 51, }; +static const int mt7629_pcie_pereset_funcs[] = { 1, }; +static const int mt7629_pcie_wake_pins[] = { 55, }; +static const int mt7629_pcie_wake_funcs[] = { 1, }; +static const int mt7629_pcie_clkreq_pins[] = { 56, }; +static const int mt7629_pcie_clkreq_funcs[] = { 1, }; /* PWM */ -static int mt7629_pwm_0_pins[] = { 52, }; -static int mt7629_pwm_0_funcs[] = { 1, }; -static int mt7629_pwm_1_pins[] = { 61, }; -static int mt7629_pwm_1_funcs[] = { 2, }; +static const int mt7629_pwm_0_pins[] = { 52, }; +static const int mt7629_pwm_0_funcs[] = { 1, }; +static const int mt7629_pwm_1_pins[] = { 61, }; +static const int mt7629_pwm_1_funcs[] = { 2, }; /* WF 2G */ -static int mt7629_wf0_2g_pins[] = { 70, 71, 72, 73, 74, 75, 76, 77, 78, }; -static int mt7629_wf0_2g_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, }; +static const int mt7629_wf0_2g_pins[] = { 70, 71, 72, 73, 74, 75, 76, 77, 78, }; +static const int mt7629_wf0_2g_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, }; /* SNFI */ -static int mt7629_snfi_pins[] = { 62, 63, 64, 65, 66, 67 }; -static int mt7629_snfi_funcs[] = { 2, 2, 2, 2, 2, 2 }; +static const int mt7629_snfi_pins[] = { 62, 63, 64, 65, 66, 67 }; +static const int mt7629_snfi_funcs[] = { 2, 2, 2, 2, 2, 2 }; /* SPI NOR */ -static int mt7629_snor_pins[] = { 62, 63, 64, 65, 66, 67 }; -static int mt7629_snor_funcs[] = { 1, 1, 1, 1, 1, 1 }; +static const int mt7629_snor_pins[] = { 62, 63, 64, 65, 66, 67 }; +static const int mt7629_snor_funcs[] = { 1, 1, 1, 1, 1, 1 }; static const struct mtk_group_desc mt7629_groups[] = { PINCTRL_PIN_GROUP("wf0_5g", mt7629_wf0_5g), @@ -385,7 +385,7 @@ static const struct mtk_function_desc mt7629_functions[] = { {"jtag", mt7629_jtag_groups, ARRAY_SIZE(mt7629_jtag_groups)}, }; -static struct mtk_pinctrl_soc mt7629_data = { +static const struct mtk_pinctrl_soc mt7629_data = { .name = "mt7629_pinctrl", .reg_cal = mt7629_reg_cals, .pins = mt7629_pins, diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7981.c b/drivers/pinctrl/mediatek/pinctrl-mt7981.c index d8875241cb6..3fa198ed79c 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7981.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c @@ -570,242 +570,246 @@ static const struct mtk_pin_desc mt7981_pins[] = { }; /* WA_AICE */ -static int mt7981_wa_aice1_pins[] = { 0, 1, }; -static int mt7981_wa_aice1_funcs[] = { 2, 2, }; +static const int mt7981_wa_aice1_pins[] = { 0, 1, }; +static const int mt7981_wa_aice1_funcs[] = { 2, 2, }; -static int mt7981_wa_aice2_pins[] = { 0, 1, }; -static int mt7981_wa_aice2_funcs[] = { 3, 3, }; +static const int mt7981_wa_aice2_pins[] = { 0, 1, }; +static const int mt7981_wa_aice2_funcs[] = { 3, 3, }; -static int mt7981_wa_aice3_pins[] = { 28, 29, }; -static int mt7981_wa_aice3_funcs[] = { 3, 3, }; +static const int mt7981_wa_aice3_pins[] = { 28, 29, }; +static const int mt7981_wa_aice3_funcs[] = { 3, 3, }; -static int mt7981_wm_aice1_pins[] = { 9, 10, }; -static int mt7981_wm_aice1_funcs[] = { 2, 2, }; +static const int mt7981_wm_aice1_pins[] = { 9, 10, }; +static const int mt7981_wm_aice1_funcs[] = { 2, 2, }; -static int mt7981_wm_aice2_pins[] = { 30, 31, }; -static int mt7981_wm_aice2_funcs[] = { 5, 5, }; +static const int mt7981_wm_aice2_pins[] = { 30, 31, }; +static const int mt7981_wm_aice2_funcs[] = { 5, 5, }; /* WM_UART */ -static int mt7981_wm_uart_0_pins[] = { 0, 1, }; -static int mt7981_wm_uart_0_funcs[] = { 5, 5, }; +static const int mt7981_wm_uart_0_pins[] = { 0, 1, }; +static const int mt7981_wm_uart_0_funcs[] = { 5, 5, }; -static int mt7981_wm_uart_1_pins[] = { 20, 21, }; -static int mt7981_wm_uart_1_funcs[] = { 4, 4, }; +static const int mt7981_wm_uart_1_pins[] = { 20, 21, }; +static const int mt7981_wm_uart_1_funcs[] = { 4, 4, }; -static int mt7981_wm_uart_2_pins[] = { 30, 31, }; -static int mt7981_wm_uart_2_funcs[] = { 3, 3, }; +static const int mt7981_wm_uart_2_pins[] = { 30, 31, }; +static const int mt7981_wm_uart_2_funcs[] = { 3, 3, }; /* DFD */ -static int mt7981_dfd_pins[] = { 0, 1, 4, 5, }; -static int mt7981_dfd_funcs[] = { 5, 5, 6, 6, }; +static const int mt7981_dfd_pins[] = { 0, 1, 4, 5, }; +static const int mt7981_dfd_funcs[] = { 5, 5, 6, 6, }; /* SYS_WATCHDOG */ -static int mt7981_watchdog_pins[] = { 2, }; -static int mt7981_watchdog_funcs[] = { 1, }; +static const int mt7981_watchdog_pins[] = { 2, }; +static const int mt7981_watchdog_funcs[] = { 1, }; -static int mt7981_watchdog1_pins[] = { 13, }; -static int mt7981_watchdog1_funcs[] = { 5, }; +static const int mt7981_watchdog1_pins[] = { 13, }; +static const int mt7981_watchdog1_funcs[] = { 5, }; /* PCIE_PERESET_N */ -static int mt7981_pcie_pereset_pins[] = { 3, }; -static int mt7981_pcie_pereset_funcs[] = { 1, }; +static const int mt7981_pcie_pereset_pins[] = { 3, }; +static const int mt7981_pcie_pereset_funcs[] = { 1, }; /* JTAG */ -static int mt7981_jtag_pins[] = { 4, 5, 6, 7, 8, }; -static int mt7981_jtag_funcs[] = { 1, 1, 1, 1, 1, }; +static const int mt7981_jtag_pins[] = { 4, 5, 6, 7, 8, }; +static const int mt7981_jtag_funcs[] = { 1, 1, 1, 1, 1, }; /* WM_JTAG */ -static int mt7981_wm_jtag_0_pins[] = { 4, 5, 6, 7, 8, }; -static int mt7981_wm_jtag_0_funcs[] = { 2, 2, 2, 2, 2, }; +static const int mt7981_wm_jtag_0_pins[] = { 4, 5, 6, 7, 8, }; +static const int mt7981_wm_jtag_0_funcs[] = { 2, 2, 2, 2, 2, }; -static int mt7981_wm_jtag_1_pins[] = { 20, 21, 22, 23, 24, }; -static int mt7981_wm_jtag_1_funcs[] = { 5, 5, 5, 5, 5, }; +static const int mt7981_wm_jtag_1_pins[] = { 20, 21, 22, 23, 24, }; +static const int mt7981_wm_jtag_1_funcs[] = { 5, 5, 5, 5, 5, }; /* WO0_JTAG */ -static int mt7981_wo0_jtag_0_pins[] = { 9, 10, 11, 12, 13, }; -static int mt7981_wo0_jtag_0_funcs[] = { 1, 1, 1, 1, 1, }; +static const int mt7981_wo0_jtag_0_pins[] = { 9, 10, 11, 12, 13, }; +static const int mt7981_wo0_jtag_0_funcs[] = { 1, 1, 1, 1, 1, }; -static int mt7981_wo0_jtag_1_pins[] = { 25, 26, 27, 28, 29, }; -static int mt7981_wo0_jtag_1_funcs[] = { 5, 5, 5, 5, 5, }; +static const int mt7981_wo0_jtag_1_pins[] = { 25, 26, 27, 28, 29, }; +static const int mt7981_wo0_jtag_1_funcs[] = { 5, 5, 5, 5, 5, }; /* UART2 */ -static int mt7981_uart2_0_pins[] = { 4, 5, 6, 7, }; -static int mt7981_uart2_0_funcs[] = { 3, 3, 3, 3, }; +static const int mt7981_uart2_0_pins[] = { 4, 5, 6, 7, }; +static const int mt7981_uart2_0_funcs[] = { 3, 3, 3, 3, }; /* GBE_LED0 */ -static int mt7981_gbe_led0_pins[] = { 8, }; -static int mt7981_gbe_led0_funcs[] = { 3, }; +static const int mt7981_gbe_led0_pins[] = { 8, }; +static const int mt7981_gbe_led0_funcs[] = { 3, }; /* PTA_EXT */ -static int mt7981_pta_ext_0_pins[] = { 4, 5, 6, }; -static int mt7981_pta_ext_0_funcs[] = { 4, 4, 4, }; +static const int mt7981_pta_ext_0_pins[] = { 4, 5, 6, }; +static const int mt7981_pta_ext_0_funcs[] = { 4, 4, 4, }; -static int mt7981_pta_ext_1_pins[] = { 22, 23, 24, }; -static int mt7981_pta_ext_1_funcs[] = { 4, 4, 4, }; +static const int mt7981_pta_ext_1_pins[] = { 22, 23, 24, }; +static const int mt7981_pta_ext_1_funcs[] = { 4, 4, 4, }; /* PWM2 */ -static int mt7981_pwm2_pins[] = { 7, }; -static int mt7981_pwm2_funcs[] = { 4, }; +static const int mt7981_pwm2_pins[] = { 7, }; +static const int mt7981_pwm2_funcs[] = { 4, }; /* NET_WO0_UART_TXD */ -static int mt7981_net_wo0_uart_txd_0_pins[] = { 8, }; -static int mt7981_net_wo0_uart_txd_0_funcs[] = { 4, }; +static const int mt7981_net_wo0_uart_txd_0_pins[] = { 8, }; +static const int mt7981_net_wo0_uart_txd_0_funcs[] = { 4, }; -static int mt7981_net_wo0_uart_txd_1_pins[] = { 14, }; -static int mt7981_net_wo0_uart_txd_1_funcs[] = { 3, }; +static const int mt7981_net_wo0_uart_txd_1_pins[] = { 14, }; +static const int mt7981_net_wo0_uart_txd_1_funcs[] = { 3, }; -static int mt7981_net_wo0_uart_txd_2_pins[] = { 15, }; -static int mt7981_net_wo0_uart_txd_2_funcs[] = { 4, }; +static const int mt7981_net_wo0_uart_txd_2_pins[] = { 15, }; +static const int mt7981_net_wo0_uart_txd_2_funcs[] = { 4, }; /* SPI1 */ -static int mt7981_spi1_0_pins[] = { 4, 5, 6, 7, }; -static int mt7981_spi1_0_funcs[] = { 5, 5, 5, 5, }; +static const int mt7981_spi1_0_pins[] = { 4, 5, 6, 7, }; +static const int mt7981_spi1_0_funcs[] = { 5, 5, 5, 5, }; /* I2C */ -static int mt7981_i2c0_0_pins[] = { 6, 7, }; -static int mt7981_i2c0_0_funcs[] = { 6, 6, }; +static const int mt7981_i2c0_0_pins[] = { 6, 7, }; +static const int mt7981_i2c0_0_funcs[] = { 6, 6, }; -static int mt7981_i2c0_1_pins[] = { 30, 31, }; -static int mt7981_i2c0_1_funcs[] = { 4, 4, }; +static const int mt7981_i2c0_1_pins[] = { 30, 31, }; +static const int mt7981_i2c0_1_funcs[] = { 4, 4, }; -static int mt7981_i2c0_2_pins[] = { 36, 37, }; -static int mt7981_i2c0_2_funcs[] = { 2, 2, }; +static const int mt7981_i2c0_2_pins[] = { 36, 37, }; +static const int mt7981_i2c0_2_funcs[] = { 2, 2, }; -static int mt7981_u2_phy_i2c_pins[] = { 30, 31, }; -static int mt7981_u2_phy_i2c_funcs[] = { 6, 6, }; +static const int mt7981_u2_phy_i2c_pins[] = { 30, 31, }; +static const int mt7981_u2_phy_i2c_funcs[] = { 6, 6, }; -static int mt7981_u3_phy_i2c_pins[] = { 32, 33, }; -static int mt7981_u3_phy_i2c_funcs[] = { 3, 3, }; +static const int mt7981_u3_phy_i2c_pins[] = { 32, 33, }; +static const int mt7981_u3_phy_i2c_funcs[] = { 3, 3, }; -static int mt7981_sgmii1_phy_i2c_pins[] = { 32, 33, }; -static int mt7981_sgmii1_phy_i2c_funcs[] = { 2, 2, }; +static const int mt7981_sgmii1_phy_i2c_pins[] = { 32, 33, }; +static const int mt7981_sgmii1_phy_i2c_funcs[] = { 2, 2, }; -static int mt7981_sgmii0_phy_i2c_pins[] = { 32, 33, }; -static int mt7981_sgmii0_phy_i2c_funcs[] = { 5, 5, }; +static const int mt7981_sgmii0_phy_i2c_pins[] = { 32, 33, }; +static const int mt7981_sgmii0_phy_i2c_funcs[] = { 5, 5, }; /* DFD_NTRST */ -static int mt7981_dfd_ntrst_pins[] = { 8, }; -static int mt7981_dfd_ntrst_funcs[] = { 6, }; +static const int mt7981_dfd_ntrst_pins[] = { 8, }; +static const int mt7981_dfd_ntrst_funcs[] = { 6, }; /* PWM0 */ -static int mt7981_pwm0_0_pins[] = { 13, }; -static int mt7981_pwm0_0_funcs[] = { 2, }; +static const int mt7981_pwm0_0_pins[] = { 13, }; +static const int mt7981_pwm0_0_funcs[] = { 2, }; -static int mt7981_pwm0_1_pins[] = { 15, }; -static int mt7981_pwm0_1_funcs[] = { 1, }; +static const int mt7981_pwm0_1_pins[] = { 15, }; +static const int mt7981_pwm0_1_funcs[] = { 1, }; /* PWM1 */ -static int mt7981_pwm1_0_pins[] = { 14, }; -static int mt7981_pwm1_0_funcs[] = { 2, }; +static const int mt7981_pwm1_0_pins[] = { 14, }; +static const int mt7981_pwm1_0_funcs[] = { 2, }; -static int mt7981_pwm1_1_pins[] = { 15, }; -static int mt7981_pwm1_1_funcs[] = { 3, }; +static const int mt7981_pwm1_1_pins[] = { 15, }; +static const int mt7981_pwm1_1_funcs[] = { 3, }; /* GBE_LED1 */ -static int mt7981_gbe_led1_pins[] = { 13, }; -static int mt7981_gbe_led1_funcs[] = { 3, }; +static const int mt7981_gbe_led1_pins[] = { 13, }; +static const int mt7981_gbe_led1_funcs[] = { 3, }; /* PCM */ -static int mt7981_pcm_pins[] = { 9, 10, 11, 12, 13, 25 }; -static int mt7981_pcm_funcs[] = { 4, 4, 4, 4, 4, 4, }; +static const int mt7981_pcm_pins[] = { 9, 10, 11, 12, 13, 25 }; +static const int mt7981_pcm_funcs[] = { 4, 4, 4, 4, 4, 4, }; /* UDI */ -static int mt7981_udi_pins[] = { 9, 10, 11, 12, 13, }; -static int mt7981_udi_funcs[] = { 6, 6, 6, 6, 6, }; +static const int mt7981_udi_pins[] = { 9, 10, 11, 12, 13, }; +static const int mt7981_udi_funcs[] = { 6, 6, 6, 6, 6, }; /* DRV_VBUS */ -static int mt7981_drv_vbus_pins[] = { 14, }; -static int mt7981_drv_vbus_funcs[] = { 1, }; +static const int mt7981_drv_vbus_pins[] = { 14, }; +static const int mt7981_drv_vbus_funcs[] = { 1, }; /* EMMC */ -static int mt7981_emmc_45_pins[] = { 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, }; -static int mt7981_emmc_45_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; +static const int mt7981_emmc_45_pins[] = { + 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, }; +static const int mt7981_emmc_45_funcs[] = { + 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; /* SNFI */ -static int mt7981_snfi_pins[] = { 16, 17, 18, 19, 20, 21, }; -static int mt7981_snfi_funcs[] = { 3, 3, 3, 3, 3, 3, }; +static const int mt7981_snfi_pins[] = { 16, 17, 18, 19, 20, 21, }; +static const int mt7981_snfi_funcs[] = { 3, 3, 3, 3, 3, 3, }; /* SPI0 */ -static int mt7981_spi0_pins[] = { 16, 17, 18, 19, }; -static int mt7981_spi0_funcs[] = { 1, 1, 1, 1, }; +static const int mt7981_spi0_pins[] = { 16, 17, 18, 19, }; +static const int mt7981_spi0_funcs[] = { 1, 1, 1, 1, }; /* SPI0 */ -static int mt7981_spi0_wp_hold_pins[] = { 20, 21, }; -static int mt7981_spi0_wp_hold_funcs[] = { 1, 1, }; +static const int mt7981_spi0_wp_hold_pins[] = { 20, 21, }; +static const int mt7981_spi0_wp_hold_funcs[] = { 1, 1, }; /* SPI1 */ -static int mt7981_spi1_1_pins[] = { 22, 23, 24, 25, }; -static int mt7981_spi1_1_funcs[] = { 1, 1, 1, 1, }; +static const int mt7981_spi1_1_pins[] = { 22, 23, 24, 25, }; +static const int mt7981_spi1_1_funcs[] = { 1, 1, 1, 1, }; /* SPI2 */ -static int mt7981_spi2_pins[] = { 26, 27, 28, 29, }; -static int mt7981_spi2_funcs[] = { 1, 1, 1, 1, }; +static const int mt7981_spi2_pins[] = { 26, 27, 28, 29, }; +static const int mt7981_spi2_funcs[] = { 1, 1, 1, 1, }; /* SPI2 */ -static int mt7981_spi2_wp_hold_pins[] = { 30, 31, }; -static int mt7981_spi2_wp_hold_funcs[] = { 1, 1, }; +static const int mt7981_spi2_wp_hold_pins[] = { 30, 31, }; +static const int mt7981_spi2_wp_hold_funcs[] = { 1, 1, }; /* UART1 */ -static int mt7981_uart1_0_pins[] = { 16, 17, 18, 19, }; -static int mt7981_uart1_0_funcs[] = { 4, 4, 4, 4, }; +static const int mt7981_uart1_0_pins[] = { 16, 17, 18, 19, }; +static const int mt7981_uart1_0_funcs[] = { 4, 4, 4, 4, }; -static int mt7981_uart1_1_pins[] = { 26, 27, 28, 29, }; -static int mt7981_uart1_1_funcs[] = { 2, 2, 2, 2, }; +static const int mt7981_uart1_1_pins[] = { 26, 27, 28, 29, }; +static const int mt7981_uart1_1_funcs[] = { 2, 2, 2, 2, }; /* UART2 */ -static int mt7981_uart2_1_pins[] = { 22, 23, 24, 25, }; -static int mt7981_uart2_1_funcs[] = { 3, 3, 3, 3, }; +static const int mt7981_uart2_1_pins[] = { 22, 23, 24, 25, }; +static const int mt7981_uart2_1_funcs[] = { 3, 3, 3, 3, }; /* UART0 */ -static int mt7981_uart0_pins[] = { 32, 33, }; -static int mt7981_uart0_funcs[] = { 1, 1, }; +static const int mt7981_uart0_pins[] = { 32, 33, }; +static const int mt7981_uart0_funcs[] = { 1, 1, }; /* PCIE_CLK_REQ */ -static int mt7981_pcie_clk_pins[] = { 34, }; -static int mt7981_pcie_clk_funcs[] = { 2, }; +static const int mt7981_pcie_clk_pins[] = { 34, }; +static const int mt7981_pcie_clk_funcs[] = { 2, }; /* PCIE_WAKE_N */ -static int mt7981_pcie_wake_pins[] = { 35, }; -static int mt7981_pcie_wake_funcs[] = { 2, }; +static const int mt7981_pcie_wake_pins[] = { 35, }; +static const int mt7981_pcie_wake_funcs[] = { 2, }; /* MDC_MDIO */ -static int mt7981_smi_mdc_mdio_pins[] = { 36, 37, }; -static int mt7981_smi_mdc_mdio_funcs[] = { 1, 1, }; +static const int mt7981_smi_mdc_mdio_pins[] = { 36, 37, }; +static const int mt7981_smi_mdc_mdio_funcs[] = { 1, 1, }; -static int mt7981_gbe_ext_mdc_mdio_pins[] = { 36, 37, }; -static int mt7981_gbe_ext_mdc_mdio_funcs[] = { 3, 3, }; +static const int mt7981_gbe_ext_mdc_mdio_pins[] = { 36, 37, }; +static const int mt7981_gbe_ext_mdc_mdio_funcs[] = { 3, 3, }; /* WF0_MODE1 */ -static int mt7981_wf0_mode1_pins[] = { 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, - 50, 51, 52, 53, 54, 55, 56 }; -static int mt7981_wf0_mode1_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1 }; +static const int mt7981_wf0_mode1_pins[] = { + 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56 }; +static const int mt7981_wf0_mode1_funcs[] = { + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }; /* WF0_MODE3 */ -static int mt7981_wf0_mode3_pins[] = { 45, 46, 47, 48, 49, 51 }; -static int mt7981_wf0_mode3_funcs[] = { 2, 2, 2, 2, 2, 2 }; +static const int mt7981_wf0_mode3_pins[] = { 45, 46, 47, 48, 49, 51 }; +static const int mt7981_wf0_mode3_funcs[] = { 2, 2, 2, 2, 2, 2 }; /* WF2G_LED */ -static int mt7981_wf2g_led0_pins[] = { 30, }; -static int mt7981_wf2g_led0_funcs[] = { 2, }; +static const int mt7981_wf2g_led0_pins[] = { 30, }; +static const int mt7981_wf2g_led0_funcs[] = { 2, }; -static int mt7981_wf2g_led1_pins[] = { 34, }; -static int mt7981_wf2g_led1_funcs[] = { 1, }; +static const int mt7981_wf2g_led1_pins[] = { 34, }; +static const int mt7981_wf2g_led1_funcs[] = { 1, }; /* WF5G_LED */ -static int mt7981_wf5g_led0_pins[] = { 31, }; -static int mt7981_wf5g_led0_funcs[] = { 2, }; +static const int mt7981_wf5g_led0_pins[] = { 31, }; +static const int mt7981_wf5g_led0_funcs[] = { 2, }; -static int mt7981_wf5g_led1_pins[] = { 35, }; -static int mt7981_wf5g_led1_funcs[] = { 1, }; +static const int mt7981_wf5g_led1_pins[] = { 35, }; +static const int mt7981_wf5g_led1_funcs[] = { 1, }; /* MT7531_INT */ -static int mt7981_mt7531_int_pins[] = { 38, }; -static int mt7981_mt7531_int_funcs[] = { 1, }; +static const int mt7981_mt7531_int_pins[] = { 38, }; +static const int mt7981_mt7531_int_funcs[] = { 1, }; /* ANT_SEL */ -static int mt7981_ant_sel_pins[] = { 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 34, 35 }; -static int mt7981_ant_sel_funcs[] = { 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6 }; +static const int mt7981_ant_sel_pins[] = { + 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 34, 35 }; +static const int mt7981_ant_sel_funcs[] = { + 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6 }; static const struct mtk_group_desc mt7981_groups[] = { /* @GPIO(0,1): WA_AICE(2) */ @@ -1012,7 +1016,7 @@ static const char *const mt7981_pinctrl_register_base_names[] = { "iocfg_lb_base", "iocfg_bl_base", "iocfg_tm_base", "iocfg_tl_base", }; -static struct mtk_pinctrl_soc mt7981_data = { +static const struct mtk_pinctrl_soc mt7981_data = { .name = "mt7981_pinctrl", .reg_cal = mt7981_reg_cals, .pins = mt7981_pins, diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7986.c b/drivers/pinctrl/mediatek/pinctrl-mt7986.c index 449e5adcd9a..819d64488f3 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7986.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7986.c @@ -554,114 +554,117 @@ static const struct mtk_io_type_desc mt7986_io_type_desc[] = { * The hardware probably has multiple combinations of these pinouts. */ -static int mt7986_watchdog_pins[] = { 0, }; -static int mt7986_watchdog_funcs[] = { 1, }; +static const int mt7986_watchdog_pins[] = { 0, }; +static const int mt7986_watchdog_funcs[] = { 1, }; -static int mt7986_wifi_led_pins[] = { 1, 2, }; -static int mt7986_wifi_led_funcs[] = { 1, 1, }; +static const int mt7986_wifi_led_pins[] = { 1, 2, }; +static const int mt7986_wifi_led_funcs[] = { 1, 1, }; -static int mt7986_i2c_pins[] = { 3, 4, }; -static int mt7986_i2c_funcs[] = { 1, 1, }; +static const int mt7986_i2c_pins[] = { 3, 4, }; +static const int mt7986_i2c_funcs[] = { 1, 1, }; -static int mt7986_uart1_0_pins[] = { 7, 8, 9, 10, }; -static int mt7986_uart1_0_funcs[] = { 3, 3, 3, 3, }; +static const int mt7986_uart1_0_pins[] = { 7, 8, 9, 10, }; +static const int mt7986_uart1_0_funcs[] = { 3, 3, 3, 3, }; -static int mt7986_spi1_0_pins[] = { 11, 12, 13, 14, }; -static int mt7986_spi1_0_funcs[] = { 3, 3, 3, 3, }; +static const int mt7986_spi1_0_pins[] = { 11, 12, 13, 14, }; +static const int mt7986_spi1_0_funcs[] = { 3, 3, 3, 3, }; -static int mt7986_pwm1_1_pins[] = { 20, }; -static int mt7986_pwm1_1_funcs[] = { 2, }; +static const int mt7986_pwm1_1_pins[] = { 20, }; +static const int mt7986_pwm1_1_funcs[] = { 2, }; -static int mt7986_pwm0_pins[] = { 21, }; -static int mt7986_pwm0_funcs[] = { 1, }; +static const int mt7986_pwm0_pins[] = { 21, }; +static const int mt7986_pwm0_funcs[] = { 1, }; -static int mt7986_pwm1_0_pins[] = { 22, }; -static int mt7986_pwm1_0_funcs[] = { 1, }; +static const int mt7986_pwm1_0_pins[] = { 22, }; +static const int mt7986_pwm1_0_funcs[] = { 1, }; -static int mt7986_emmc_45_pins[] = { +static const int mt7986_emmc_45_pins[] = { 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, }; -static int mt7986_emmc_45_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; +static const int mt7986_emmc_45_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; -static int mt7986_snfi_pins[] = { 23, 24, 25, 26, 27, 28, }; -static int mt7986_snfi_funcs[] = { 1, 1, 1, 1, 1, 1, }; +static const int mt7986_snfi_pins[] = { 23, 24, 25, 26, 27, 28, }; +static const int mt7986_snfi_funcs[] = { 1, 1, 1, 1, 1, 1, }; -static int mt7986_spi1_1_pins[] = { 23, 24, 25, 26, }; -static int mt7986_spi1_1_funcs[] = { 3, 3, 3, 3, }; +static const int mt7986_spi1_1_pins[] = { 23, 24, 25, 26, }; +static const int mt7986_spi1_1_funcs[] = { 3, 3, 3, 3, }; -static int mt7986_uart1_1_pins[] = { 23, 24, 25, 26, }; -static int mt7986_uart1_1_funcs[] = { 4, 4, 4, 4, }; +static const int mt7986_uart1_1_pins[] = { 23, 24, 25, 26, }; +static const int mt7986_uart1_1_funcs[] = { 4, 4, 4, 4, }; -static int mt7986_spi1_2_pins[] = { 29, 30, 31, 32, }; -static int mt7986_spi1_2_funcs[] = { 1, 1, 1, 1, }; +static const int mt7986_spi1_2_pins[] = { 29, 30, 31, 32, }; +static const int mt7986_spi1_2_funcs[] = { 1, 1, 1, 1, }; -static int mt7986_uart1_2_pins[] = { 29, 30, 31, 32, }; -static int mt7986_uart1_2_funcs[] = { 3, 3, 3, 3, }; +static const int mt7986_uart1_2_pins[] = { 29, 30, 31, 32, }; +static const int mt7986_uart1_2_funcs[] = { 3, 3, 3, 3, }; -static int mt7986_uart2_0_pins[] = { 29, 30, 31, 32, }; -static int mt7986_uart2_0_funcs[] = { 4, 4, 4, 4, }; +static const int mt7986_uart2_0_pins[] = { 29, 30, 31, 32, }; +static const int mt7986_uart2_0_funcs[] = { 4, 4, 4, 4, }; -static int mt7986_spi0_pins[] = { 33, 34, 35, 36, }; -static int mt7986_spi0_funcs[] = { 1, 1, 1, 1, }; +static const int mt7986_spi0_pins[] = { 33, 34, 35, 36, }; +static const int mt7986_spi0_funcs[] = { 1, 1, 1, 1, }; -static int mt7986_spi0_wp_hold_pins[] = { 37, 38, }; -static int mt7986_spi0_wp_hold_funcs[] = { 1, 1, }; +static const int mt7986_spi0_wp_hold_pins[] = { 37, 38, }; +static const int mt7986_spi0_wp_hold_funcs[] = { 1, 1, }; -static int mt7986_uart2_1_pins[] = { 33, 34, 35, 36, }; -static int mt7986_uart2_1_funcs[] = { 3, 3, 3, 3, }; +static const int mt7986_uart2_1_pins[] = { 33, 34, 35, 36, }; +static const int mt7986_uart2_1_funcs[] = { 3, 3, 3, 3, }; -static int mt7986_uart1_3_rx_tx_pins[] = { 35, 36, }; -static int mt7986_uart1_3_rx_tx_funcs[] = { 2, 2, }; +static const int mt7986_uart1_3_rx_tx_pins[] = { 35, 36, }; +static const int mt7986_uart1_3_rx_tx_funcs[] = { 2, 2, }; -static int mt7986_uart1_3_cts_rts_pins[] = { 37, 38, }; -static int mt7986_uart1_3_cts_rts_funcs[] = { 2, 2, }; +static const int mt7986_uart1_3_cts_rts_pins[] = { 37, 38, }; +static const int mt7986_uart1_3_cts_rts_funcs[] = { 2, 2, }; -static int mt7986_spi1_3_pins[] = { 33, 34, 35, 36, }; -static int mt7986_spi1_3_funcs[] = { 4, 4, 4, 4, }; +static const int mt7986_spi1_3_pins[] = { 33, 34, 35, 36, }; +static const int mt7986_spi1_3_funcs[] = { 4, 4, 4, 4, }; -static int mt7986_uart0_pins[] = { 39, 40, }; -static int mt7986_uart0_funcs[] = { 1, 1, }; +static const int mt7986_uart0_pins[] = { 39, 40, }; +static const int mt7986_uart0_funcs[] = { 1, 1, }; -static int mt7986_pcie_reset_pins[] = { 41, }; -static int mt7986_pcie_reset_funcs[] = { 1, }; +static const int mt7986_pcie_reset_pins[] = { 41, }; +static const int mt7986_pcie_reset_funcs[] = { 1, }; -static int mt7986_uart1_pins[] = { 42, 43, 44, 45, }; -static int mt7986_uart1_funcs[] = { 1, 1, 1, 1, }; +static const int mt7986_uart1_pins[] = { 42, 43, 44, 45, }; +static const int mt7986_uart1_funcs[] = { 1, 1, 1, 1, }; -static int mt7986_uart2_pins[] = { 46, 47, 48, 49, }; -static int mt7986_uart2_funcs[] = { 1, 1, 1, 1, }; +static const int mt7986_uart2_pins[] = { 46, 47, 48, 49, }; +static const int mt7986_uart2_funcs[] = { 1, 1, 1, 1, }; -static int mt7986_emmc_51_pins[] = { +static const int mt7986_emmc_51_pins[] = { 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, }; -static int mt7986_emmc_51_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; +static const int mt7986_emmc_51_funcs[] = { + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; -static int mt7986_pcm_pins[] = { 62, 63, 64, 65, }; -static int mt7986_pcm_funcs[] = { 1, 1, 1, 1, }; +static const int mt7986_pcm_pins[] = { 62, 63, 64, 65, }; +static const int mt7986_pcm_funcs[] = { 1, 1, 1, 1, }; -static int mt7986_i2s_pins[] = { 62, 63, 64, 65, }; -static int mt7986_i2s_funcs[] = { 1, 1, 1, 1, }; +static const int mt7986_i2s_pins[] = { 62, 63, 64, 65, }; +static const int mt7986_i2s_funcs[] = { 1, 1, 1, 1, }; -static int mt7986_switch_int_pins[] = { 66, }; -static int mt7986_switch_int_funcs[] = { 1, }; +static const int mt7986_switch_int_pins[] = { 66, }; +static const int mt7986_switch_int_funcs[] = { 1, }; -static int mt7986_mdc_mdio_pins[] = { 67, 68, }; -static int mt7986_mdc_mdio_funcs[] = { 1, 1, }; +static const int mt7986_mdc_mdio_pins[] = { 67, 68, }; +static const int mt7986_mdc_mdio_funcs[] = { 1, 1, }; -static int mt7986_wf_2g_pins[] = {74, 75, 76, 77, 78, 79, 80, 81, 82, 83, }; -static int mt7986_wf_2g_funcs[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; +static const int mt7986_wf_2g_pins[] = { + 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, }; +static const int mt7986_wf_2g_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; -static int mt7986_wf_5g_pins[] = {91, 92, 93, 94, 95, 96, 97, 98, 99, 100, }; -static int mt7986_wf_5g_funcs[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; +static const int mt7986_wf_5g_pins[] = { + 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, }; +static const int mt7986_wf_5g_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; -static int mt7986_wf_dbdc_pins[] = { +static const int mt7986_wf_dbdc_pins[] = { 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, }; -static int mt7986_wf_dbdc_funcs[] = { +static const int mt7986_wf_dbdc_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; -static int mt7986_pcie_clk_pins[] = { 9, }; -static int mt7986_pcie_clk_funcs[] = { 1, }; +static const int mt7986_pcie_clk_pins[] = { 9, }; +static const int mt7986_pcie_clk_funcs[] = { 1, }; -static int mt7986_pcie_wake_pins[] = { 10, }; -static int mt7986_pcie_wake_funcs[] = { 1, }; +static const int mt7986_pcie_wake_pins[] = { 10, }; +static const int mt7986_pcie_wake_funcs[] = { 1, }; static const struct mtk_group_desc mt7986_groups[] = { PINCTRL_PIN_GROUP("watchdog", mt7986_watchdog), @@ -738,7 +741,7 @@ static const struct mtk_function_desc mt7986_functions[] = { {"wifi", mt7986_wf_groups, ARRAY_SIZE(mt7986_wf_groups)}, }; -static struct mtk_pinctrl_soc mt7986_data = { +static const struct mtk_pinctrl_soc mt7986_data = { .name = "mt7986_pinctrl", .reg_cal = mt7986_reg_cals, .pins = mt7986_pins, diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7988.c b/drivers/pinctrl/mediatek/pinctrl-mt7988.c new file mode 100644 index 00000000000..03a38e83dfa --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mt7988.c @@ -0,0 +1,1274 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 MediaTek Inc. + * Author: Sam Shih <sam.shih@mediatek.com> + */ + +#include <dm.h> +#include "pinctrl-mtk-common.h" + +enum MT7988_PINCTRL_REG_PAGE { + GPIO_BASE, + IOCFG_TR_BASE, + IOCFG_BR_BASE, + IOCFG_RB_BASE, + IOCFG_LB_BASE, + IOCFG_TL_BASE, +}; + +#define MT7988_TYPE0_PIN(_number, _name) \ + MTK_TYPED_PIN(_number, _name, DRV_GRP4, IO_TYPE_GRP0) + +#define MT7988_TYPE1_PIN(_number, _name) \ + MTK_TYPED_PIN(_number, _name, DRV_GRP4, IO_TYPE_GRP1) + +#define MT7988_TYPE2_PIN(_number, _name) \ + MTK_TYPED_PIN(_number, _name, DRV_FIXED, IO_TYPE_GRP2) + +#define PIN_FIELD_GPIO(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \ + PIN_FIELD_BASE_CALC(_s_pin, _e_pin, GPIO_BASE, _s_addr, _x_addrs, \ + _s_bit, _x_bits, 32, 0) + +#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ + _x_bits) \ + PIN_FIELD_BASE_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, \ + _s_bit, _x_bits, 32, 0) + +#define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ + _x_bits) \ + PIN_FIELD_BASE_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, \ + _s_bit, _x_bits, 32, 1) + +static const struct mtk_pin_field_calc mt7988_pin_mode_range[] = { + PIN_FIELD_GPIO(0, 83, 0x300, 0x10, 0, 4), +}; + +static const struct mtk_pin_field_calc mt7988_pin_dir_range[] = { + PIN_FIELD_GPIO(0, 83, 0x0, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt7988_pin_di_range[] = { + PIN_FIELD_GPIO(0, 83, 0x200, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt7988_pin_do_range[] = { + PIN_FIELD_GPIO(0, 83, 0x100, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt7988_pin_ies_range[] = { + PIN_FIELD_BASE(0, 0, IOCFG_TL_BASE, 0x30, 0x10, 13, 1), + PIN_FIELD_BASE(1, 1, IOCFG_TL_BASE, 0x30, 0x10, 14, 1), + PIN_FIELD_BASE(2, 2, IOCFG_TL_BASE, 0x30, 0x10, 11, 1), + PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x30, 0x10, 12, 1), + PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x30, 0x10, 0, 1), + PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x30, 0x10, 9, 1), + PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x30, 0x10, 10, 1), + + PIN_FIELD_BASE(7, 7, IOCFG_LB_BASE, 0x30, 0x10, 8, 1), + PIN_FIELD_BASE(8, 8, IOCFG_LB_BASE, 0x30, 0x10, 6, 1), + PIN_FIELD_BASE(9, 9, IOCFG_LB_BASE, 0x30, 0x10, 5, 1), + PIN_FIELD_BASE(10, 10, IOCFG_LB_BASE, 0x30, 0x10, 3, 1), + + PIN_FIELD_BASE(11, 11, IOCFG_TR_BASE, 0x40, 0x10, 0, 1), + PIN_FIELD_BASE(12, 12, IOCFG_TR_BASE, 0x40, 0x10, 21, 1), + PIN_FIELD_BASE(13, 13, IOCFG_TR_BASE, 0x40, 0x10, 1, 1), + PIN_FIELD_BASE(14, 14, IOCFG_TR_BASE, 0x40, 0x10, 2, 1), + + PIN_FIELD_BASE(15, 15, IOCFG_TL_BASE, 0x30, 0x10, 7, 1), + PIN_FIELD_BASE(16, 16, IOCFG_TL_BASE, 0x30, 0x10, 8, 1), + PIN_FIELD_BASE(17, 17, IOCFG_TL_BASE, 0x30, 0x10, 3, 1), + PIN_FIELD_BASE(18, 18, IOCFG_TL_BASE, 0x30, 0x10, 4, 1), + + PIN_FIELD_BASE(19, 19, IOCFG_LB_BASE, 0x30, 0x10, 7, 1), + PIN_FIELD_BASE(20, 20, IOCFG_LB_BASE, 0x30, 0x10, 4, 1), + + PIN_FIELD_BASE(21, 21, IOCFG_RB_BASE, 0x50, 0x10, 17, 1), + PIN_FIELD_BASE(22, 22, IOCFG_RB_BASE, 0x50, 0x10, 23, 1), + PIN_FIELD_BASE(23, 23, IOCFG_RB_BASE, 0x50, 0x10, 20, 1), + PIN_FIELD_BASE(24, 24, IOCFG_RB_BASE, 0x50, 0x10, 19, 1), + PIN_FIELD_BASE(25, 25, IOCFG_RB_BASE, 0x50, 0x10, 21, 1), + PIN_FIELD_BASE(26, 26, IOCFG_RB_BASE, 0x50, 0x10, 22, 1), + PIN_FIELD_BASE(27, 27, IOCFG_RB_BASE, 0x50, 0x10, 18, 1), + PIN_FIELD_BASE(28, 28, IOCFG_RB_BASE, 0x50, 0x10, 25, 1), + PIN_FIELD_BASE(29, 29, IOCFG_RB_BASE, 0x50, 0x10, 26, 1), + PIN_FIELD_BASE(30, 30, IOCFG_RB_BASE, 0x50, 0x10, 27, 1), + PIN_FIELD_BASE(31, 31, IOCFG_RB_BASE, 0x50, 0x10, 24, 1), + PIN_FIELD_BASE(32, 32, IOCFG_RB_BASE, 0x50, 0x10, 28, 1), + PIN_FIELD_BASE(33, 33, IOCFG_RB_BASE, 0x60, 0x10, 0, 1), + PIN_FIELD_BASE(34, 34, IOCFG_RB_BASE, 0x50, 0x10, 31, 1), + PIN_FIELD_BASE(35, 35, IOCFG_RB_BASE, 0x50, 0x10, 29, 1), + PIN_FIELD_BASE(36, 36, IOCFG_RB_BASE, 0x50, 0x10, 30, 1), + PIN_FIELD_BASE(37, 37, IOCFG_RB_BASE, 0x60, 0x10, 1, 1), + PIN_FIELD_BASE(38, 38, IOCFG_RB_BASE, 0x50, 0x10, 11, 1), + PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x50, 0x10, 10, 1), + PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x50, 0x10, 0, 1), + PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x50, 0x10, 1, 1), + PIN_FIELD_BASE(42, 42, IOCFG_RB_BASE, 0x50, 0x10, 9, 1), + PIN_FIELD_BASE(43, 43, IOCFG_RB_BASE, 0x50, 0x10, 8, 1), + PIN_FIELD_BASE(44, 44, IOCFG_RB_BASE, 0x50, 0x10, 7, 1), + PIN_FIELD_BASE(45, 45, IOCFG_RB_BASE, 0x50, 0x10, 6, 1), + PIN_FIELD_BASE(46, 46, IOCFG_RB_BASE, 0x50, 0x10, 5, 1), + PIN_FIELD_BASE(47, 47, IOCFG_RB_BASE, 0x50, 0x10, 4, 1), + PIN_FIELD_BASE(48, 48, IOCFG_RB_BASE, 0x50, 0x10, 3, 1), + PIN_FIELD_BASE(49, 49, IOCFG_RB_BASE, 0x50, 0x10, 2, 1), + PIN_FIELD_BASE(50, 50, IOCFG_RB_BASE, 0x50, 0x10, 15, 1), + PIN_FIELD_BASE(51, 51, IOCFG_RB_BASE, 0x50, 0x10, 12, 1), + PIN_FIELD_BASE(52, 52, IOCFG_RB_BASE, 0x50, 0x10, 13, 1), + PIN_FIELD_BASE(53, 53, IOCFG_RB_BASE, 0x50, 0x10, 14, 1), + PIN_FIELD_BASE(54, 54, IOCFG_RB_BASE, 0x50, 0x10, 16, 1), + + PIN_FIELD_BASE(55, 55, IOCFG_TR_BASE, 0x40, 0x10, 14, 1), + PIN_FIELD_BASE(56, 56, IOCFG_TR_BASE, 0x40, 0x10, 15, 1), + PIN_FIELD_BASE(57, 57, IOCFG_TR_BASE, 0x40, 0x10, 13, 1), + PIN_FIELD_BASE(58, 58, IOCFG_TR_BASE, 0x40, 0x10, 4, 1), + PIN_FIELD_BASE(59, 59, IOCFG_TR_BASE, 0x40, 0x10, 5, 1), + PIN_FIELD_BASE(60, 60, IOCFG_TR_BASE, 0x40, 0x10, 6, 1), + PIN_FIELD_BASE(61, 61, IOCFG_TR_BASE, 0x40, 0x10, 3, 1), + PIN_FIELD_BASE(62, 62, IOCFG_TR_BASE, 0x40, 0x10, 7, 1), + PIN_FIELD_BASE(63, 63, IOCFG_TR_BASE, 0x40, 0x10, 20, 1), + PIN_FIELD_BASE(64, 64, IOCFG_TR_BASE, 0x40, 0x10, 8, 1), + PIN_FIELD_BASE(65, 65, IOCFG_TR_BASE, 0x40, 0x10, 9, 1), + PIN_FIELD_BASE(66, 66, IOCFG_TR_BASE, 0x40, 0x10, 10, 1), + PIN_FIELD_BASE(67, 67, IOCFG_TR_BASE, 0x40, 0x10, 11, 1), + PIN_FIELD_BASE(68, 68, IOCFG_TR_BASE, 0x40, 0x10, 12, 1), + + PIN_FIELD_BASE(69, 69, IOCFG_TL_BASE, 0x30, 0x10, 1, 1), + PIN_FIELD_BASE(70, 70, IOCFG_TL_BASE, 0x30, 0x10, 2, 1), + PIN_FIELD_BASE(71, 71, IOCFG_TL_BASE, 0x30, 0x10, 5, 1), + PIN_FIELD_BASE(72, 72, IOCFG_TL_BASE, 0x30, 0x10, 6, 1), + + PIN_FIELD_BASE(73, 73, IOCFG_LB_BASE, 0x30, 0x10, 10, 1), + PIN_FIELD_BASE(74, 74, IOCFG_LB_BASE, 0x30, 0x10, 1, 1), + PIN_FIELD_BASE(75, 75, IOCFG_LB_BASE, 0x30, 0x10, 11, 1), + PIN_FIELD_BASE(76, 76, IOCFG_LB_BASE, 0x30, 0x10, 9, 1), + PIN_FIELD_BASE(77, 77, IOCFG_LB_BASE, 0x30, 0x10, 2, 1), + PIN_FIELD_BASE(78, 78, IOCFG_LB_BASE, 0x30, 0x10, 0, 1), + PIN_FIELD_BASE(79, 79, IOCFG_LB_BASE, 0x30, 0x10, 12, 1), + + PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x40, 0x10, 18, 1), + PIN_FIELD_BASE(81, 81, IOCFG_TR_BASE, 0x40, 0x10, 19, 1), + PIN_FIELD_BASE(82, 82, IOCFG_TR_BASE, 0x40, 0x10, 16, 1), + PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0x40, 0x10, 17, 1), +}; + +static const struct mtk_pin_field_calc mt7988_pin_smt_range[] = { + PIN_FIELD_BASE(0, 0, IOCFG_TL_BASE, 0xc0, 0x10, 13, 1), + PIN_FIELD_BASE(1, 1, IOCFG_TL_BASE, 0xc0, 0x10, 14, 1), + PIN_FIELD_BASE(2, 2, IOCFG_TL_BASE, 0xc0, 0x10, 11, 1), + PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0xc0, 0x10, 12, 1), + PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0xc0, 0x10, 0, 1), + PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0xc0, 0x10, 9, 1), + PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0xc0, 0x10, 10, 1), + + PIN_FIELD_BASE(7, 7, IOCFG_LB_BASE, 0xb0, 0x10, 8, 1), + PIN_FIELD_BASE(8, 8, IOCFG_LB_BASE, 0xb0, 0x10, 6, 1), + PIN_FIELD_BASE(9, 9, IOCFG_LB_BASE, 0xb0, 0x10, 5, 1), + PIN_FIELD_BASE(10, 10, IOCFG_LB_BASE, 0xb0, 0x10, 3, 1), + + PIN_FIELD_BASE(11, 11, IOCFG_TR_BASE, 0xe0, 0x10, 0, 1), + PIN_FIELD_BASE(12, 12, IOCFG_TR_BASE, 0xe0, 0x10, 21, 1), + PIN_FIELD_BASE(13, 13, IOCFG_TR_BASE, 0xe0, 0x10, 1, 1), + PIN_FIELD_BASE(14, 14, IOCFG_TR_BASE, 0xe0, 0x10, 2, 1), + + PIN_FIELD_BASE(15, 15, IOCFG_TL_BASE, 0xc0, 0x10, 7, 1), + PIN_FIELD_BASE(16, 16, IOCFG_TL_BASE, 0xc0, 0x10, 8, 1), + PIN_FIELD_BASE(17, 17, IOCFG_TL_BASE, 0xc0, 0x10, 3, 1), + PIN_FIELD_BASE(18, 18, IOCFG_TL_BASE, 0xc0, 0x10, 4, 1), + + PIN_FIELD_BASE(19, 19, IOCFG_LB_BASE, 0xb0, 0x10, 7, 1), + PIN_FIELD_BASE(20, 20, IOCFG_LB_BASE, 0xb0, 0x10, 4, 1), + + PIN_FIELD_BASE(21, 21, IOCFG_RB_BASE, 0x140, 0x10, 17, 1), + PIN_FIELD_BASE(22, 22, IOCFG_RB_BASE, 0x140, 0x10, 23, 1), + PIN_FIELD_BASE(23, 23, IOCFG_RB_BASE, 0x140, 0x10, 20, 1), + PIN_FIELD_BASE(24, 24, IOCFG_RB_BASE, 0x140, 0x10, 19, 1), + PIN_FIELD_BASE(25, 25, IOCFG_RB_BASE, 0x140, 0x10, 21, 1), + PIN_FIELD_BASE(26, 26, IOCFG_RB_BASE, 0x140, 0x10, 22, 1), + PIN_FIELD_BASE(27, 27, IOCFG_RB_BASE, 0x140, 0x10, 18, 1), + PIN_FIELD_BASE(28, 28, IOCFG_RB_BASE, 0x140, 0x10, 25, 1), + PIN_FIELD_BASE(29, 29, IOCFG_RB_BASE, 0x140, 0x10, 26, 1), + PIN_FIELD_BASE(30, 30, IOCFG_RB_BASE, 0x140, 0x10, 27, 1), + PIN_FIELD_BASE(31, 31, IOCFG_RB_BASE, 0x140, 0x10, 24, 1), + PIN_FIELD_BASE(32, 32, IOCFG_RB_BASE, 0x140, 0x10, 28, 1), + PIN_FIELD_BASE(33, 33, IOCFG_RB_BASE, 0x150, 0x10, 0, 1), + PIN_FIELD_BASE(34, 34, IOCFG_RB_BASE, 0x140, 0x10, 31, 1), + PIN_FIELD_BASE(35, 35, IOCFG_RB_BASE, 0x140, 0x10, 29, 1), + PIN_FIELD_BASE(36, 36, IOCFG_RB_BASE, 0x140, 0x10, 30, 1), + PIN_FIELD_BASE(37, 37, IOCFG_RB_BASE, 0x150, 0x10, 1, 1), + PIN_FIELD_BASE(38, 38, IOCFG_RB_BASE, 0x140, 0x10, 11, 1), + PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x140, 0x10, 10, 1), + PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x140, 0x10, 0, 1), + PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x140, 0x10, 1, 1), + PIN_FIELD_BASE(42, 42, IOCFG_RB_BASE, 0x140, 0x10, 9, 1), + PIN_FIELD_BASE(43, 43, IOCFG_RB_BASE, 0x140, 0x10, 8, 1), + PIN_FIELD_BASE(44, 44, IOCFG_RB_BASE, 0x140, 0x10, 7, 1), + PIN_FIELD_BASE(45, 45, IOCFG_RB_BASE, 0x140, 0x10, 6, 1), + PIN_FIELD_BASE(46, 46, IOCFG_RB_BASE, 0x140, 0x10, 5, 1), + PIN_FIELD_BASE(47, 47, IOCFG_RB_BASE, 0x140, 0x10, 4, 1), + PIN_FIELD_BASE(48, 48, IOCFG_RB_BASE, 0x140, 0x10, 3, 1), + PIN_FIELD_BASE(49, 49, IOCFG_RB_BASE, 0x140, 0x10, 2, 1), + PIN_FIELD_BASE(50, 50, IOCFG_RB_BASE, 0x140, 0x10, 15, 1), + PIN_FIELD_BASE(51, 51, IOCFG_RB_BASE, 0x140, 0x10, 12, 1), + PIN_FIELD_BASE(52, 52, IOCFG_RB_BASE, 0x140, 0x10, 13, 1), + PIN_FIELD_BASE(53, 53, IOCFG_RB_BASE, 0x140, 0x10, 14, 1), + PIN_FIELD_BASE(54, 54, IOCFG_RB_BASE, 0x140, 0x10, 16, 1), + + PIN_FIELD_BASE(55, 55, IOCFG_TR_BASE, 0xe0, 0x10, 14, 1), + PIN_FIELD_BASE(56, 56, IOCFG_TR_BASE, 0xe0, 0x10, 15, 1), + PIN_FIELD_BASE(57, 57, IOCFG_TR_BASE, 0xe0, 0x10, 13, 1), + PIN_FIELD_BASE(58, 58, IOCFG_TR_BASE, 0xe0, 0x10, 4, 1), + PIN_FIELD_BASE(59, 59, IOCFG_TR_BASE, 0xe0, 0x10, 5, 1), + PIN_FIELD_BASE(60, 60, IOCFG_TR_BASE, 0xe0, 0x10, 6, 1), + PIN_FIELD_BASE(61, 61, IOCFG_TR_BASE, 0xe0, 0x10, 3, 1), + PIN_FIELD_BASE(62, 62, IOCFG_TR_BASE, 0xe0, 0x10, 7, 1), + PIN_FIELD_BASE(63, 63, IOCFG_TR_BASE, 0xe0, 0x10, 20, 1), + PIN_FIELD_BASE(64, 64, IOCFG_TR_BASE, 0xe0, 0x10, 8, 1), + PIN_FIELD_BASE(65, 65, IOCFG_TR_BASE, 0xe0, 0x10, 9, 1), + PIN_FIELD_BASE(66, 66, IOCFG_TR_BASE, 0xe0, 0x10, 10, 1), + PIN_FIELD_BASE(67, 67, IOCFG_TR_BASE, 0xe0, 0x10, 11, 1), + PIN_FIELD_BASE(68, 68, IOCFG_TR_BASE, 0xe0, 0x10, 12, 1), + + PIN_FIELD_BASE(69, 69, IOCFG_TL_BASE, 0xc0, 0x10, 1, 1), + PIN_FIELD_BASE(70, 70, IOCFG_TL_BASE, 0xc0, 0x10, 2, 1), + PIN_FIELD_BASE(71, 71, IOCFG_TL_BASE, 0xc0, 0x10, 5, 1), + PIN_FIELD_BASE(72, 72, IOCFG_TL_BASE, 0xc0, 0x10, 6, 1), + + PIN_FIELD_BASE(73, 73, IOCFG_LB_BASE, 0xb0, 0x10, 10, 1), + PIN_FIELD_BASE(74, 74, IOCFG_LB_BASE, 0xb0, 0x10, 1, 1), + PIN_FIELD_BASE(75, 75, IOCFG_LB_BASE, 0xb0, 0x10, 11, 1), + PIN_FIELD_BASE(76, 76, IOCFG_LB_BASE, 0xb0, 0x10, 9, 1), + PIN_FIELD_BASE(77, 77, IOCFG_LB_BASE, 0xb0, 0x10, 2, 1), + PIN_FIELD_BASE(78, 78, IOCFG_LB_BASE, 0xb0, 0x10, 0, 1), + PIN_FIELD_BASE(79, 79, IOCFG_LB_BASE, 0xb0, 0x10, 12, 1), + + PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0xe0, 0x10, 18, 1), + PIN_FIELD_BASE(81, 81, IOCFG_TR_BASE, 0xe0, 0x10, 19, 1), + PIN_FIELD_BASE(82, 82, IOCFG_TR_BASE, 0xe0, 0x10, 16, 1), + PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0xe0, 0x10, 17, 1), +}; + +static const struct mtk_pin_field_calc mt7988_pin_pu_range[] = { + PIN_FIELD_BASE(7, 7, IOCFG_LB_BASE, 0x60, 0x10, 5, 1), + PIN_FIELD_BASE(8, 8, IOCFG_LB_BASE, 0x60, 0x10, 4, 1), + PIN_FIELD_BASE(9, 9, IOCFG_LB_BASE, 0x60, 0x10, 3, 1), + PIN_FIELD_BASE(10, 10, IOCFG_LB_BASE, 0x60, 0x10, 2, 1), + + PIN_FIELD_BASE(13, 13, IOCFG_TR_BASE, 0x70, 0x10, 0, 1), + PIN_FIELD_BASE(14, 14, IOCFG_TR_BASE, 0x70, 0x10, 1, 1), + PIN_FIELD_BASE(63, 63, IOCFG_TR_BASE, 0x70, 0x10, 2, 1), + + PIN_FIELD_BASE(75, 75, IOCFG_LB_BASE, 0x60, 0x10, 7, 1), + PIN_FIELD_BASE(76, 76, IOCFG_LB_BASE, 0x60, 0x10, 6, 1), + PIN_FIELD_BASE(77, 77, IOCFG_LB_BASE, 0x60, 0x10, 1, 1), + PIN_FIELD_BASE(78, 78, IOCFG_LB_BASE, 0x60, 0x10, 0, 1), + PIN_FIELD_BASE(79, 79, IOCFG_LB_BASE, 0x60, 0x10, 8, 1), +}; + +static const struct mtk_pin_field_calc mt7988_pin_pd_range[] = { + PIN_FIELD_BASE(7, 7, IOCFG_LB_BASE, 0x40, 0x10, 5, 1), + PIN_FIELD_BASE(8, 8, IOCFG_LB_BASE, 0x40, 0x10, 4, 1), + PIN_FIELD_BASE(9, 9, IOCFG_LB_BASE, 0x40, 0x10, 3, 1), + PIN_FIELD_BASE(10, 10, IOCFG_LB_BASE, 0x40, 0x10, 2, 1), + + PIN_FIELD_BASE(13, 13, IOCFG_TR_BASE, 0x50, 0x10, 0, 1), + PIN_FIELD_BASE(14, 14, IOCFG_TR_BASE, 0x50, 0x10, 1, 1), + + PIN_FIELD_BASE(15, 15, IOCFG_TL_BASE, 0x40, 0x10, 4, 1), + PIN_FIELD_BASE(16, 16, IOCFG_TL_BASE, 0x40, 0x10, 5, 1), + PIN_FIELD_BASE(17, 17, IOCFG_TL_BASE, 0x40, 0x10, 0, 1), + PIN_FIELD_BASE(18, 18, IOCFG_TL_BASE, 0x40, 0x10, 1, 1), + + PIN_FIELD_BASE(63, 63, IOCFG_TR_BASE, 0x50, 0x10, 2, 1), + PIN_FIELD_BASE(71, 71, IOCFG_TL_BASE, 0x40, 0x10, 2, 1), + PIN_FIELD_BASE(72, 72, IOCFG_TL_BASE, 0x40, 0x10, 3, 1), + + PIN_FIELD_BASE(75, 75, IOCFG_LB_BASE, 0x40, 0x10, 7, 1), + PIN_FIELD_BASE(76, 76, IOCFG_LB_BASE, 0x40, 0x10, 6, 1), + PIN_FIELD_BASE(77, 77, IOCFG_LB_BASE, 0x40, 0x10, 1, 1), + PIN_FIELD_BASE(78, 78, IOCFG_LB_BASE, 0x40, 0x10, 0, 1), + PIN_FIELD_BASE(79, 79, IOCFG_LB_BASE, 0x40, 0x10, 8, 1), +}; + +static const struct mtk_pin_field_calc mt7988_pin_drv_range[] = { + PIN_FIELD_BASE(0, 0, IOCFG_TL_BASE, 0x00, 0x10, 21, 3), + PIN_FIELD_BASE(1, 1, IOCFG_TL_BASE, 0x00, 0x10, 24, 3), + PIN_FIELD_BASE(2, 2, IOCFG_TL_BASE, 0x00, 0x10, 15, 3), + PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x00, 0x10, 18, 3), + PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x00, 0x10, 0, 3), + PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x00, 0x10, 9, 3), + PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x00, 0x10, 12, 3), + + PIN_FIELD_BASE(7, 7, IOCFG_LB_BASE, 0x00, 0x10, 24, 3), + PIN_FIELD_BASE(8, 8, IOCFG_LB_BASE, 0x00, 0x10, 28, 3), + PIN_FIELD_BASE(9, 9, IOCFG_LB_BASE, 0x00, 0x10, 15, 3), + PIN_FIELD_BASE(10, 10, IOCFG_LB_BASE, 0x00, 0x10, 9, 3), + + PIN_FIELD_BASE(11, 11, IOCFG_TR_BASE, 0x00, 0x10, 0, 3), + PIN_FIELD_BASE(12, 12, IOCFG_TR_BASE, 0x20, 0x10, 3, 3), + PIN_FIELD_BASE(13, 13, IOCFG_TR_BASE, 0x00, 0x10, 3, 3), + PIN_FIELD_BASE(14, 14, IOCFG_TR_BASE, 0x00, 0x10, 6, 3), + + PIN_FIELD_BASE(19, 19, IOCFG_LB_BASE, 0x00, 0x10, 21, 3), + PIN_FIELD_BASE(20, 20, IOCFG_LB_BASE, 0x00, 0x10, 12, 3), + + PIN_FIELD_BASE(21, 21, IOCFG_RB_BASE, 0x10, 0x10, 21, 3), + PIN_FIELD_BASE(22, 22, IOCFG_RB_BASE, 0x20, 0x10, 9, 3), + PIN_FIELD_BASE(23, 23, IOCFG_RB_BASE, 0x20, 0x10, 0, 3), + PIN_FIELD_BASE(24, 24, IOCFG_RB_BASE, 0x10, 0x10, 27, 3), + PIN_FIELD_BASE(25, 25, IOCFG_RB_BASE, 0x20, 0x10, 3, 3), + PIN_FIELD_BASE(26, 26, IOCFG_RB_BASE, 0x20, 0x10, 6, 3), + PIN_FIELD_BASE(27, 27, IOCFG_RB_BASE, 0x10, 0x10, 24, 3), + PIN_FIELD_BASE(28, 28, IOCFG_RB_BASE, 0x20, 0x10, 15, 3), + PIN_FIELD_BASE(29, 29, IOCFG_RB_BASE, 0x20, 0x10, 18, 3), + PIN_FIELD_BASE(30, 30, IOCFG_RB_BASE, 0x20, 0x10, 21, 3), + PIN_FIELD_BASE(31, 31, IOCFG_RB_BASE, 0x20, 0x10, 12, 3), + PIN_FIELD_BASE(32, 32, IOCFG_RB_BASE, 0x20, 0x10, 24, 3), + PIN_FIELD_BASE(33, 33, IOCFG_RB_BASE, 0x30, 0x10, 6, 3), + PIN_FIELD_BASE(34, 34, IOCFG_RB_BASE, 0x30, 0x10, 3, 3), + PIN_FIELD_BASE(35, 35, IOCFG_RB_BASE, 0x20, 0x10, 27, 3), + PIN_FIELD_BASE(36, 36, IOCFG_RB_BASE, 0x30, 0x10, 0, 3), + PIN_FIELD_BASE(37, 37, IOCFG_RB_BASE, 0x30, 0x10, 9, 3), + PIN_FIELD_BASE(38, 38, IOCFG_RB_BASE, 0x10, 0x10, 3, 3), + PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x10, 0x10, 0, 3), + PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x00, 0x10, 0, 3), + PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x00, 0x10, 3, 3), + PIN_FIELD_BASE(42, 42, IOCFG_RB_BASE, 0x00, 0x10, 27, 3), + PIN_FIELD_BASE(43, 43, IOCFG_RB_BASE, 0x00, 0x10, 24, 3), + PIN_FIELD_BASE(44, 44, IOCFG_RB_BASE, 0x00, 0x10, 21, 3), + PIN_FIELD_BASE(45, 45, IOCFG_RB_BASE, 0x00, 0x10, 18, 3), + PIN_FIELD_BASE(46, 46, IOCFG_RB_BASE, 0x00, 0x10, 15, 3), + PIN_FIELD_BASE(47, 47, IOCFG_RB_BASE, 0x00, 0x10, 12, 3), + PIN_FIELD_BASE(48, 48, IOCFG_RB_BASE, 0x00, 0x10, 9, 3), + PIN_FIELD_BASE(49, 49, IOCFG_RB_BASE, 0x00, 0x10, 6, 3), + PIN_FIELD_BASE(50, 50, IOCFG_RB_BASE, 0x10, 0x10, 15, 3), + PIN_FIELD_BASE(51, 51, IOCFG_RB_BASE, 0x10, 0x10, 6, 3), + PIN_FIELD_BASE(52, 52, IOCFG_RB_BASE, 0x10, 0x10, 9, 3), + PIN_FIELD_BASE(53, 53, IOCFG_RB_BASE, 0x10, 0x10, 12, 3), + PIN_FIELD_BASE(54, 54, IOCFG_RB_BASE, 0x10, 0x10, 18, 3), + + PIN_FIELD_BASE(55, 55, IOCFG_TR_BASE, 0x10, 0x10, 12, 3), + PIN_FIELD_BASE(56, 56, IOCFG_TR_BASE, 0x10, 0x10, 15, 3), + PIN_FIELD_BASE(57, 57, IOCFG_TR_BASE, 0x10, 0x10, 9, 3), + PIN_FIELD_BASE(58, 58, IOCFG_TR_BASE, 0x00, 0x10, 12, 3), + PIN_FIELD_BASE(59, 59, IOCFG_TR_BASE, 0x00, 0x10, 15, 3), + PIN_FIELD_BASE(60, 60, IOCFG_TR_BASE, 0x00, 0x10, 18, 3), + PIN_FIELD_BASE(61, 61, IOCFG_TR_BASE, 0x00, 0x10, 9, 3), + PIN_FIELD_BASE(62, 62, IOCFG_TR_BASE, 0x00, 0x10, 21, 3), + PIN_FIELD_BASE(63, 63, IOCFG_TR_BASE, 0x20, 0x10, 0, 3), + PIN_FIELD_BASE(64, 64, IOCFG_TR_BASE, 0x00, 0x10, 24, 3), + PIN_FIELD_BASE(65, 65, IOCFG_TR_BASE, 0x00, 0x10, 27, 3), + PIN_FIELD_BASE(66, 66, IOCFG_TR_BASE, 0x10, 0x10, 0, 3), + PIN_FIELD_BASE(67, 67, IOCFG_TR_BASE, 0x10, 0x10, 3, 3), + PIN_FIELD_BASE(68, 68, IOCFG_TR_BASE, 0x10, 0x10, 6, 3), + + PIN_FIELD_BASE(69, 69, IOCFG_TL_BASE, 0x00, 0x10, 3, 3), + PIN_FIELD_BASE(70, 70, IOCFG_TL_BASE, 0x00, 0x10, 6, 3), + + PIN_FIELD_BASE(73, 73, IOCFG_LB_BASE, 0x10, 0x10, 0, 3), + PIN_FIELD_BASE(74, 74, IOCFG_LB_BASE, 0x00, 0x10, 3, 3), + PIN_FIELD_BASE(75, 75, IOCFG_LB_BASE, 0x10, 0x10, 3, 3), + PIN_FIELD_BASE(76, 76, IOCFG_LB_BASE, 0x00, 0x10, 27, 3), + PIN_FIELD_BASE(77, 77, IOCFG_LB_BASE, 0x00, 0x10, 6, 3), + PIN_FIELD_BASE(78, 78, IOCFG_LB_BASE, 0x00, 0x10, 0, 3), + PIN_FIELD_BASE(79, 79, IOCFG_LB_BASE, 0x10, 0x10, 6, 3), + + PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x10, 0x10, 24, 3), + PIN_FIELD_BASE(81, 81, IOCFG_TR_BASE, 0x10, 0x10, 27, 3), + PIN_FIELD_BASE(82, 82, IOCFG_TR_BASE, 0x10, 0x10, 18, 3), + PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0x10, 0x10, 21, 3), +}; + +static const struct mtk_pin_field_calc mt7988_pin_pupd_range[] = { + PIN_FIELD_BASE(0, 0, IOCFG_TL_BASE, 0x50, 0x10, 7, 1), + PIN_FIELD_BASE(1, 1, IOCFG_TL_BASE, 0x50, 0x10, 8, 1), + PIN_FIELD_BASE(2, 2, IOCFG_TL_BASE, 0x50, 0x10, 5, 1), + PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x50, 0x10, 6, 1), + PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x50, 0x10, 0, 1), + PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x50, 0x10, 3, 1), + PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x50, 0x10, 4, 1), + + PIN_FIELD_BASE(11, 11, IOCFG_TR_BASE, 0x60, 0x10, 0, 1), + PIN_FIELD_BASE(12, 12, IOCFG_TR_BASE, 0x60, 0x10, 18, 1), + + PIN_FIELD_BASE(19, 19, IOCFG_LB_BASE, 0x50, 0x10, 2, 1), + PIN_FIELD_BASE(20, 20, IOCFG_LB_BASE, 0x50, 0x10, 1, 1), + + PIN_FIELD_BASE(21, 21, IOCFG_RB_BASE, 0x70, 0x10, 17, 1), + PIN_FIELD_BASE(22, 22, IOCFG_RB_BASE, 0x70, 0x10, 23, 1), + PIN_FIELD_BASE(23, 23, IOCFG_RB_BASE, 0x70, 0x10, 20, 1), + PIN_FIELD_BASE(24, 24, IOCFG_RB_BASE, 0x70, 0x10, 19, 1), + PIN_FIELD_BASE(25, 25, IOCFG_RB_BASE, 0x70, 0x10, 21, 1), + PIN_FIELD_BASE(26, 26, IOCFG_RB_BASE, 0x70, 0x10, 22, 1), + PIN_FIELD_BASE(27, 27, IOCFG_RB_BASE, 0x70, 0x10, 18, 1), + PIN_FIELD_BASE(28, 28, IOCFG_RB_BASE, 0x70, 0x10, 25, 1), + PIN_FIELD_BASE(29, 29, IOCFG_RB_BASE, 0x70, 0x10, 26, 1), + PIN_FIELD_BASE(30, 30, IOCFG_RB_BASE, 0x70, 0x10, 27, 1), + PIN_FIELD_BASE(31, 31, IOCFG_RB_BASE, 0x70, 0x10, 24, 1), + PIN_FIELD_BASE(32, 32, IOCFG_RB_BASE, 0x70, 0x10, 28, 1), + PIN_FIELD_BASE(33, 33, IOCFG_RB_BASE, 0x80, 0x10, 0, 1), + PIN_FIELD_BASE(34, 34, IOCFG_RB_BASE, 0x70, 0x10, 31, 1), + PIN_FIELD_BASE(35, 35, IOCFG_RB_BASE, 0x70, 0x10, 29, 1), + PIN_FIELD_BASE(36, 36, IOCFG_RB_BASE, 0x70, 0x10, 30, 1), + PIN_FIELD_BASE(37, 37, IOCFG_RB_BASE, 0x80, 0x10, 1, 1), + PIN_FIELD_BASE(38, 38, IOCFG_RB_BASE, 0x70, 0x10, 11, 1), + PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x70, 0x10, 10, 1), + PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x70, 0x10, 0, 1), + PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x70, 0x10, 1, 1), + PIN_FIELD_BASE(42, 42, IOCFG_RB_BASE, 0x70, 0x10, 9, 1), + PIN_FIELD_BASE(43, 43, IOCFG_RB_BASE, 0x70, 0x10, 8, 1), + PIN_FIELD_BASE(44, 44, IOCFG_RB_BASE, 0x70, 0x10, 7, 1), + PIN_FIELD_BASE(45, 45, IOCFG_RB_BASE, 0x70, 0x10, 6, 1), + PIN_FIELD_BASE(46, 46, IOCFG_RB_BASE, 0x70, 0x10, 5, 1), + PIN_FIELD_BASE(47, 47, IOCFG_RB_BASE, 0x70, 0x10, 4, 1), + PIN_FIELD_BASE(48, 48, IOCFG_RB_BASE, 0x70, 0x10, 3, 1), + PIN_FIELD_BASE(49, 49, IOCFG_RB_BASE, 0x70, 0x10, 2, 1), + PIN_FIELD_BASE(50, 50, IOCFG_RB_BASE, 0x70, 0x10, 15, 1), + PIN_FIELD_BASE(51, 51, IOCFG_RB_BASE, 0x70, 0x10, 12, 1), + PIN_FIELD_BASE(52, 52, IOCFG_RB_BASE, 0x70, 0x10, 13, 1), + PIN_FIELD_BASE(53, 53, IOCFG_RB_BASE, 0x70, 0x10, 14, 1), + PIN_FIELD_BASE(54, 54, IOCFG_RB_BASE, 0x70, 0x10, 16, 1), + + PIN_FIELD_BASE(55, 55, IOCFG_TR_BASE, 0x60, 0x10, 12, 1), + PIN_FIELD_BASE(56, 56, IOCFG_TR_BASE, 0x60, 0x10, 13, 1), + PIN_FIELD_BASE(57, 57, IOCFG_TR_BASE, 0x60, 0x10, 11, 1), + PIN_FIELD_BASE(58, 58, IOCFG_TR_BASE, 0x60, 0x10, 2, 1), + PIN_FIELD_BASE(59, 59, IOCFG_TR_BASE, 0x60, 0x10, 3, 1), + PIN_FIELD_BASE(60, 60, IOCFG_TR_BASE, 0x60, 0x10, 4, 1), + PIN_FIELD_BASE(61, 61, IOCFG_TR_BASE, 0x60, 0x10, 1, 1), + PIN_FIELD_BASE(62, 62, IOCFG_TR_BASE, 0x60, 0x10, 5, 1), + PIN_FIELD_BASE(64, 64, IOCFG_TR_BASE, 0x60, 0x10, 6, 1), + PIN_FIELD_BASE(65, 65, IOCFG_TR_BASE, 0x60, 0x10, 7, 1), + PIN_FIELD_BASE(66, 66, IOCFG_TR_BASE, 0x60, 0x10, 8, 1), + PIN_FIELD_BASE(67, 67, IOCFG_TR_BASE, 0x60, 0x10, 9, 1), + PIN_FIELD_BASE(68, 68, IOCFG_TR_BASE, 0x60, 0x10, 10, 1), + + PIN_FIELD_BASE(69, 69, IOCFG_TL_BASE, 0x50, 0x10, 1, 1), + PIN_FIELD_BASE(70, 70, IOCFG_TL_BASE, 0x50, 0x10, 2, 1), + + PIN_FIELD_BASE(73, 73, IOCFG_LB_BASE, 0x50, 0x10, 3, 1), + PIN_FIELD_BASE(74, 74, IOCFG_LB_BASE, 0x50, 0x10, 0, 1), + + PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x60, 0x10, 16, 1), + PIN_FIELD_BASE(81, 81, IOCFG_TR_BASE, 0x60, 0x10, 17, 1), + PIN_FIELD_BASE(82, 82, IOCFG_TR_BASE, 0x60, 0x10, 14, 1), + PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0x60, 0x10, 15, 1), +}; + +static const struct mtk_pin_field_calc mt7988_pin_r0_range[] = { + PIN_FIELD_BASE(0, 0, IOCFG_TL_BASE, 0x60, 0x10, 7, 1), + PIN_FIELD_BASE(1, 1, IOCFG_TL_BASE, 0x60, 0x10, 8, 1), + PIN_FIELD_BASE(2, 2, IOCFG_TL_BASE, 0x60, 0x10, 5, 1), + PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x60, 0x10, 6, 1), + PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x60, 0x10, 0, 1), + PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x60, 0x10, 3, 1), + PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x60, 0x10, 4, 1), + + PIN_FIELD_BASE(11, 11, IOCFG_TR_BASE, 0x80, 0x10, 0, 1), + PIN_FIELD_BASE(12, 12, IOCFG_TR_BASE, 0x80, 0x10, 18, 1), + + PIN_FIELD_BASE(19, 19, IOCFG_LB_BASE, 0x70, 0x10, 2, 1), + PIN_FIELD_BASE(20, 20, IOCFG_LB_BASE, 0x70, 0x10, 1, 1), + + PIN_FIELD_BASE(21, 21, IOCFG_RB_BASE, 0x90, 0x10, 17, 1), + PIN_FIELD_BASE(22, 22, IOCFG_RB_BASE, 0x90, 0x10, 23, 1), + PIN_FIELD_BASE(23, 23, IOCFG_RB_BASE, 0x90, 0x10, 20, 1), + PIN_FIELD_BASE(24, 24, IOCFG_RB_BASE, 0x90, 0x10, 19, 1), + PIN_FIELD_BASE(25, 25, IOCFG_RB_BASE, 0x90, 0x10, 21, 1), + PIN_FIELD_BASE(26, 26, IOCFG_RB_BASE, 0x90, 0x10, 22, 1), + PIN_FIELD_BASE(27, 27, IOCFG_RB_BASE, 0x90, 0x10, 18, 1), + PIN_FIELD_BASE(28, 28, IOCFG_RB_BASE, 0x90, 0x10, 25, 1), + PIN_FIELD_BASE(29, 29, IOCFG_RB_BASE, 0x90, 0x10, 26, 1), + PIN_FIELD_BASE(30, 30, IOCFG_RB_BASE, 0x90, 0x10, 27, 1), + PIN_FIELD_BASE(31, 31, IOCFG_RB_BASE, 0x90, 0x10, 24, 1), + PIN_FIELD_BASE(32, 32, IOCFG_RB_BASE, 0x90, 0x10, 28, 1), + PIN_FIELD_BASE(33, 33, IOCFG_RB_BASE, 0xa0, 0x10, 0, 1), + PIN_FIELD_BASE(34, 34, IOCFG_RB_BASE, 0x90, 0x10, 31, 1), + PIN_FIELD_BASE(35, 35, IOCFG_RB_BASE, 0x90, 0x10, 29, 1), + PIN_FIELD_BASE(36, 36, IOCFG_RB_BASE, 0x90, 0x10, 30, 1), + PIN_FIELD_BASE(37, 37, IOCFG_RB_BASE, 0xa0, 0x10, 1, 1), + PIN_FIELD_BASE(38, 38, IOCFG_RB_BASE, 0x90, 0x10, 11, 1), + PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x90, 0x10, 10, 1), + PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x90, 0x10, 0, 1), + PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x90, 0x10, 1, 1), + PIN_FIELD_BASE(42, 42, IOCFG_RB_BASE, 0x90, 0x10, 9, 1), + PIN_FIELD_BASE(43, 43, IOCFG_RB_BASE, 0x90, 0x10, 8, 1), + PIN_FIELD_BASE(44, 44, IOCFG_RB_BASE, 0x90, 0x10, 7, 1), + PIN_FIELD_BASE(45, 45, IOCFG_RB_BASE, 0x90, 0x10, 6, 1), + PIN_FIELD_BASE(46, 46, IOCFG_RB_BASE, 0x90, 0x10, 5, 1), + PIN_FIELD_BASE(47, 47, IOCFG_RB_BASE, 0x90, 0x10, 4, 1), + PIN_FIELD_BASE(48, 48, IOCFG_RB_BASE, 0x90, 0x10, 3, 1), + PIN_FIELD_BASE(49, 49, IOCFG_RB_BASE, 0x90, 0x10, 2, 1), + PIN_FIELD_BASE(50, 50, IOCFG_RB_BASE, 0x90, 0x10, 15, 1), + PIN_FIELD_BASE(51, 51, IOCFG_RB_BASE, 0x90, 0x10, 12, 1), + PIN_FIELD_BASE(52, 52, IOCFG_RB_BASE, 0x90, 0x10, 13, 1), + PIN_FIELD_BASE(53, 53, IOCFG_RB_BASE, 0x90, 0x10, 14, 1), + PIN_FIELD_BASE(54, 54, IOCFG_RB_BASE, 0x90, 0x10, 16, 1), + + PIN_FIELD_BASE(55, 55, IOCFG_TR_BASE, 0x80, 0x10, 12, 1), + PIN_FIELD_BASE(56, 56, IOCFG_TR_BASE, 0x80, 0x10, 13, 1), + PIN_FIELD_BASE(57, 57, IOCFG_TR_BASE, 0x80, 0x10, 11, 1), + PIN_FIELD_BASE(58, 58, IOCFG_TR_BASE, 0x80, 0x10, 2, 1), + PIN_FIELD_BASE(59, 59, IOCFG_TR_BASE, 0x80, 0x10, 3, 1), + PIN_FIELD_BASE(60, 60, IOCFG_TR_BASE, 0x80, 0x10, 4, 1), + PIN_FIELD_BASE(61, 61, IOCFG_TR_BASE, 0x80, 0x10, 1, 1), + PIN_FIELD_BASE(62, 62, IOCFG_TR_BASE, 0x80, 0x10, 5, 1), + PIN_FIELD_BASE(64, 64, IOCFG_TR_BASE, 0x80, 0x10, 6, 1), + PIN_FIELD_BASE(65, 65, IOCFG_TR_BASE, 0x80, 0x10, 7, 1), + PIN_FIELD_BASE(66, 66, IOCFG_TR_BASE, 0x80, 0x10, 8, 1), + PIN_FIELD_BASE(67, 67, IOCFG_TR_BASE, 0x80, 0x10, 9, 1), + PIN_FIELD_BASE(68, 68, IOCFG_TR_BASE, 0x80, 0x10, 10, 1), + + PIN_FIELD_BASE(69, 69, IOCFG_TL_BASE, 0x60, 0x10, 1, 1), + PIN_FIELD_BASE(70, 70, IOCFG_TL_BASE, 0x60, 0x10, 2, 1), + + PIN_FIELD_BASE(73, 73, IOCFG_LB_BASE, 0x70, 0x10, 3, 1), + PIN_FIELD_BASE(74, 74, IOCFG_LB_BASE, 0x70, 0x10, 0, 1), + + PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x80, 0x10, 16, 1), + PIN_FIELD_BASE(81, 81, IOCFG_TR_BASE, 0x80, 0x10, 17, 1), + PIN_FIELD_BASE(82, 82, IOCFG_TR_BASE, 0x80, 0x10, 14, 1), + PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0x80, 0x10, 15, 1), +}; + +static const struct mtk_pin_field_calc mt7988_pin_r1_range[] = { + PIN_FIELD_BASE(0, 0, IOCFG_TL_BASE, 0x70, 0x10, 7, 1), + PIN_FIELD_BASE(1, 1, IOCFG_TL_BASE, 0x70, 0x10, 8, 1), + PIN_FIELD_BASE(2, 2, IOCFG_TL_BASE, 0x70, 0x10, 5, 1), + PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x70, 0x10, 6, 1), + PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x70, 0x10, 0, 1), + PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x70, 0x10, 3, 1), + PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x70, 0x10, 4, 1), + + PIN_FIELD_BASE(11, 11, IOCFG_TR_BASE, 0x90, 0x10, 0, 1), + PIN_FIELD_BASE(12, 12, IOCFG_TR_BASE, 0x90, 0x10, 18, 1), + + PIN_FIELD_BASE(19, 19, IOCFG_LB_BASE, 0x80, 0x10, 2, 1), + PIN_FIELD_BASE(20, 20, IOCFG_LB_BASE, 0x80, 0x10, 1, 1), + + PIN_FIELD_BASE(21, 21, IOCFG_RB_BASE, 0xb0, 0x10, 17, 1), + PIN_FIELD_BASE(22, 22, IOCFG_RB_BASE, 0xb0, 0x10, 23, 1), + PIN_FIELD_BASE(23, 23, IOCFG_RB_BASE, 0xb0, 0x10, 20, 1), + PIN_FIELD_BASE(24, 24, IOCFG_RB_BASE, 0xb0, 0x10, 19, 1), + PIN_FIELD_BASE(25, 25, IOCFG_RB_BASE, 0xb0, 0x10, 21, 1), + PIN_FIELD_BASE(26, 26, IOCFG_RB_BASE, 0xb0, 0x10, 22, 1), + PIN_FIELD_BASE(27, 27, IOCFG_RB_BASE, 0xb0, 0x10, 18, 1), + PIN_FIELD_BASE(28, 28, IOCFG_RB_BASE, 0xb0, 0x10, 25, 1), + PIN_FIELD_BASE(29, 29, IOCFG_RB_BASE, 0xb0, 0x10, 26, 1), + PIN_FIELD_BASE(30, 30, IOCFG_RB_BASE, 0xb0, 0x10, 27, 1), + PIN_FIELD_BASE(31, 31, IOCFG_RB_BASE, 0xb0, 0x10, 24, 1), + PIN_FIELD_BASE(32, 32, IOCFG_RB_BASE, 0xb0, 0x10, 28, 1), + PIN_FIELD_BASE(33, 33, IOCFG_RB_BASE, 0xc0, 0x10, 0, 1), + PIN_FIELD_BASE(34, 34, IOCFG_RB_BASE, 0xb0, 0x10, 31, 1), + PIN_FIELD_BASE(35, 35, IOCFG_RB_BASE, 0xb0, 0x10, 29, 1), + PIN_FIELD_BASE(36, 36, IOCFG_RB_BASE, 0xb0, 0x10, 30, 1), + PIN_FIELD_BASE(37, 37, IOCFG_RB_BASE, 0xc0, 0x10, 1, 1), + PIN_FIELD_BASE(38, 38, IOCFG_RB_BASE, 0xb0, 0x10, 11, 1), + PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0xb0, 0x10, 10, 1), + PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0xb0, 0x10, 0, 1), + PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0xb0, 0x10, 1, 1), + PIN_FIELD_BASE(42, 42, IOCFG_RB_BASE, 0xb0, 0x10, 9, 1), + PIN_FIELD_BASE(43, 43, IOCFG_RB_BASE, 0xb0, 0x10, 8, 1), + PIN_FIELD_BASE(44, 44, IOCFG_RB_BASE, 0xb0, 0x10, 7, 1), + PIN_FIELD_BASE(45, 45, IOCFG_RB_BASE, 0xb0, 0x10, 6, 1), + PIN_FIELD_BASE(46, 46, IOCFG_RB_BASE, 0xb0, 0x10, 5, 1), + PIN_FIELD_BASE(47, 47, IOCFG_RB_BASE, 0xb0, 0x10, 4, 1), + PIN_FIELD_BASE(48, 48, IOCFG_RB_BASE, 0xb0, 0x10, 3, 1), + PIN_FIELD_BASE(49, 49, IOCFG_RB_BASE, 0xb0, 0x10, 2, 1), + PIN_FIELD_BASE(50, 50, IOCFG_RB_BASE, 0xb0, 0x10, 15, 1), + PIN_FIELD_BASE(51, 51, IOCFG_RB_BASE, 0xb0, 0x10, 12, 1), + PIN_FIELD_BASE(52, 52, IOCFG_RB_BASE, 0xb0, 0x10, 13, 1), + PIN_FIELD_BASE(53, 53, IOCFG_RB_BASE, 0xb0, 0x10, 14, 1), + PIN_FIELD_BASE(54, 54, IOCFG_RB_BASE, 0xb0, 0x10, 16, 1), + + PIN_FIELD_BASE(55, 55, IOCFG_TR_BASE, 0x90, 0x10, 12, 1), + PIN_FIELD_BASE(56, 56, IOCFG_TR_BASE, 0x90, 0x10, 13, 1), + PIN_FIELD_BASE(57, 57, IOCFG_TR_BASE, 0x90, 0x10, 11, 1), + PIN_FIELD_BASE(58, 58, IOCFG_TR_BASE, 0x90, 0x10, 2, 1), + PIN_FIELD_BASE(59, 59, IOCFG_TR_BASE, 0x90, 0x10, 3, 1), + PIN_FIELD_BASE(60, 60, IOCFG_TR_BASE, 0x90, 0x10, 4, 1), + PIN_FIELD_BASE(61, 61, IOCFG_TR_BASE, 0x90, 0x10, 1, 1), + PIN_FIELD_BASE(62, 62, IOCFG_TR_BASE, 0x90, 0x10, 5, 1), + PIN_FIELD_BASE(64, 64, IOCFG_TR_BASE, 0x90, 0x10, 6, 1), + PIN_FIELD_BASE(65, 65, IOCFG_TR_BASE, 0x90, 0x10, 7, 1), + PIN_FIELD_BASE(66, 66, IOCFG_TR_BASE, 0x90, 0x10, 8, 1), + PIN_FIELD_BASE(67, 67, IOCFG_TR_BASE, 0x90, 0x10, 9, 1), + PIN_FIELD_BASE(68, 68, IOCFG_TR_BASE, 0x90, 0x10, 10, 1), + + PIN_FIELD_BASE(69, 69, IOCFG_TL_BASE, 0x70, 0x10, 1, 1), + PIN_FIELD_BASE(70, 70, IOCFG_TL_BASE, 0x70, 0x10, 2, 1), + + PIN_FIELD_BASE(73, 73, IOCFG_LB_BASE, 0x80, 0x10, 3, 1), + PIN_FIELD_BASE(74, 74, IOCFG_LB_BASE, 0x80, 0x10, 0, 1), + + PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x90, 0x10, 16, 1), + PIN_FIELD_BASE(81, 81, IOCFG_TR_BASE, 0x90, 0x10, 17, 1), + PIN_FIELD_BASE(82, 82, IOCFG_TR_BASE, 0x90, 0x10, 14, 1), + PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0x90, 0x10, 15, 1), +}; + +static const struct mtk_pin_reg_calc mt7988_reg_cals[] = { + [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7988_pin_mode_range), + [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7988_pin_dir_range), + [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7988_pin_di_range), + [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7988_pin_do_range), + [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7988_pin_smt_range), + [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7988_pin_ies_range), + [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7988_pin_pu_range), + [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7988_pin_pd_range), + [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7988_pin_drv_range), + [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7988_pin_pupd_range), + [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7988_pin_r0_range), + [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7988_pin_r1_range), +}; + +static const struct mtk_pin_desc mt7988_pins[] = { + MT7988_TYPE0_PIN(0, "UART2_RXD"), + MT7988_TYPE0_PIN(1, "UART2_TXD"), + MT7988_TYPE0_PIN(2, "UART2_CTS"), + MT7988_TYPE0_PIN(3, "UART2_RTS"), + MT7988_TYPE0_PIN(4, "GPIO_A"), + MT7988_TYPE0_PIN(5, "SMI_0_MDC"), + MT7988_TYPE0_PIN(6, "SMI_0_MDIO"), + MT7988_TYPE1_PIN(7, "PCIE30_2L_0_WAKE_N"), + MT7988_TYPE1_PIN(8, "PCIE30_2L_0_CLKREQ_N"), + MT7988_TYPE1_PIN(9, "PCIE30_1L_1_WAKE_N"), + MT7988_TYPE1_PIN(10, "PCIE30_1L_1_CLKREQ_N"), + MT7988_TYPE0_PIN(11, "GPIO_P"), + MT7988_TYPE0_PIN(12, "WATCHDOG"), + MT7988_TYPE1_PIN(13, "GPIO_RESET"), + MT7988_TYPE1_PIN(14, "GPIO_WPS"), + MT7988_TYPE2_PIN(15, "PMIC_I2C_SCL"), + MT7988_TYPE2_PIN(16, "PMIC_I2C_SDA"), + MT7988_TYPE2_PIN(17, "I2C_1_SCL"), + MT7988_TYPE2_PIN(18, "I2C_1_SDA"), + MT7988_TYPE0_PIN(19, "PCIE30_2L_0_PRESET_N"), + MT7988_TYPE0_PIN(20, "PCIE30_1L_1_PRESET_N"), + MT7988_TYPE0_PIN(21, "PWMD1"), + MT7988_TYPE0_PIN(22, "SPI0_WP"), + MT7988_TYPE0_PIN(23, "SPI0_HOLD"), + MT7988_TYPE0_PIN(24, "SPI0_CSB"), + MT7988_TYPE0_PIN(25, "SPI0_MISO"), + MT7988_TYPE0_PIN(26, "SPI0_MOSI"), + MT7988_TYPE0_PIN(27, "SPI0_CLK"), + MT7988_TYPE0_PIN(28, "SPI1_CSB"), + MT7988_TYPE0_PIN(29, "SPI1_MISO"), + MT7988_TYPE0_PIN(30, "SPI1_MOSI"), + MT7988_TYPE0_PIN(31, "SPI1_CLK"), + MT7988_TYPE0_PIN(32, "SPI2_CLK"), + MT7988_TYPE0_PIN(33, "SPI2_MOSI"), + MT7988_TYPE0_PIN(34, "SPI2_MISO"), + MT7988_TYPE0_PIN(35, "SPI2_CSB"), + MT7988_TYPE0_PIN(36, "SPI2_HOLD"), + MT7988_TYPE0_PIN(37, "SPI2_WP"), + MT7988_TYPE0_PIN(38, "EMMC_RSTB"), + MT7988_TYPE0_PIN(39, "EMMC_DSL"), + MT7988_TYPE0_PIN(40, "EMMC_CK"), + MT7988_TYPE0_PIN(41, "EMMC_CMD"), + MT7988_TYPE0_PIN(42, "EMMC_DATA_7"), + MT7988_TYPE0_PIN(43, "EMMC_DATA_6"), + MT7988_TYPE0_PIN(44, "EMMC_DATA_5"), + MT7988_TYPE0_PIN(45, "EMMC_DATA_4"), + MT7988_TYPE0_PIN(46, "EMMC_DATA_3"), + MT7988_TYPE0_PIN(47, "EMMC_DATA_2"), + MT7988_TYPE0_PIN(48, "EMMC_DATA_1"), + MT7988_TYPE0_PIN(49, "EMMC_DATA_0"), + MT7988_TYPE0_PIN(50, "PCM_FS_I2S_LRCK"), + MT7988_TYPE0_PIN(51, "PCM_CLK_I2S_BCLK"), + MT7988_TYPE0_PIN(52, "PCM_DRX_I2S_DIN"), + MT7988_TYPE0_PIN(53, "PCM_DTX_I2S_DOUT"), + MT7988_TYPE0_PIN(54, "PCM_MCK_I2S_MCLK"), + MT7988_TYPE0_PIN(55, "UART0_RXD"), + MT7988_TYPE0_PIN(56, "UART0_TXD"), + MT7988_TYPE0_PIN(57, "PWMD0"), + MT7988_TYPE0_PIN(58, "JTAG_JTDI"), + MT7988_TYPE0_PIN(59, "JTAG_JTDO"), + MT7988_TYPE0_PIN(60, "JTAG_JTMS"), + MT7988_TYPE0_PIN(61, "JTAG_JTCLK"), + MT7988_TYPE0_PIN(62, "JTAG_JTRST_N"), + MT7988_TYPE1_PIN(63, "USB_DRV_VBUS_P1"), + MT7988_TYPE0_PIN(64, "LED_A"), + MT7988_TYPE0_PIN(65, "LED_B"), + MT7988_TYPE0_PIN(66, "LED_C"), + MT7988_TYPE0_PIN(67, "LED_D"), + MT7988_TYPE0_PIN(68, "LED_E"), + MT7988_TYPE0_PIN(69, "GPIO_B"), + MT7988_TYPE0_PIN(70, "GPIO_C"), + MT7988_TYPE2_PIN(71, "I2C_2_SCL"), + MT7988_TYPE2_PIN(72, "I2C_2_SDA"), + MT7988_TYPE0_PIN(73, "PCIE30_2L_1_PRESET_N"), + MT7988_TYPE0_PIN(74, "PCIE30_1L_0_PRESET_N"), + MT7988_TYPE1_PIN(75, "PCIE30_2L_1_WAKE_N"), + MT7988_TYPE1_PIN(76, "PCIE30_2L_1_CLKREQ_N"), + MT7988_TYPE1_PIN(77, "PCIE30_1L_0_WAKE_N"), + MT7988_TYPE1_PIN(78, "PCIE30_1L_0_CLKREQ_N"), + MT7988_TYPE1_PIN(79, "USB_DRV_VBUS_P0"), + MT7988_TYPE0_PIN(80, "UART1_RXD"), + MT7988_TYPE0_PIN(81, "UART1_TXD"), + MT7988_TYPE0_PIN(82, "UART1_CTS"), + MT7988_TYPE0_PIN(83, "UART1_RTS"), +}; + +/* jtag */ +static const int mt7988_tops_jtag0_0_pins[] = { 0, 1, 2, 3, 4 }; +static const int mt7988_tops_jtag0_0_funcs[] = { 2, 2, 2, 2, 2 }; + +static const int mt7988_wo0_jtag_pins[] = { 50, 51, 52, 53, 54 }; +static const int mt7988_wo0_jtag_funcs[] = { 3, 3, 3, 3, 3 }; + +static const int mt7988_wo1_jtag_pins[] = { 50, 51, 52, 53, 54 }; +static const int mt7988_wo1_jtag_funcs[] = { 4, 4, 4, 4, 4 }; + +static const int mt7988_wo2_jtag_pins[] = { 50, 51, 52, 53, 54 }; +static const int mt7988_wo2_jtag_funcs[] = { 5, 5, 5, 5, 5 }; + +static const int mt7988_jtag_pins[] = { 58, 59, 60, 61, 62 }; +static const int mt7988_jtag_funcs[] = { 1, 1, 1, 1, 1 }; + +static const int mt7988_tops_jtag0_1_pins[] = { 58, 59, 60, 61, 62 }; +static const int mt7988_tops_jtag0_1_funcs[] = { 4, 4, 4, 4, 4 }; + +/* int_usxgmii */ +static const int mt7988_int_usxgmii_pins[] = { 2, 3 }; +static const int mt7988_int_usxgmii_funcs[] = { 3, 3 }; + +/* pwm */ +static const int mt7988_pwm0_pins[] = { 57 }; +static const int mt7988_pwm0_funcs[] = { 1 }; + +static const int mt7988_pwm1_pins[] = { 21 }; +static const int mt7988_pwm1_funcs[] = { 1 }; + +static const int mt7988_pwm2_pins[] = { 80 }; +static const int mt7988_pwm2_funcs[] = { 2 }; + +static const int mt7988_pwm3_pins[] = { 81 }; +static const int mt7988_pwm3_funcs[] = { 2 }; + +static const int mt7988_pwm4_pins[] = { 82 }; +static const int mt7988_pwm4_funcs[] = { 2 }; + +static const int mt7988_pwm5_pins[] = { 83 }; +static const int mt7988_pwm5_funcs[] = { 2 }; + +static const int mt7988_pwm6_pins[] = { 69 }; +static const int mt7988_pwm6_funcs[] = { 3 }; + +static const int mt7988_pwm7_pins[] = { 70 }; +static const int mt7988_pwm7_funcs[] = { 3 }; + +/* dfd */ +static const int mt7988_dfd_pins[] = { 0, 1, 2, 3, 4 }; +static const int mt7988_dfd_funcs[] = { 4, 4, 4, 4, 4 }; + +/* i2c */ +static const int mt7988_xfi_phy0_i2c0_pins[] = { 0, 1 }; +static const int mt7988_xfi_phy0_i2c0_funcs[] = { 5, 5 }; + +static const int mt7988_xfi_phy1_i2c0_pins[] = { 0, 1 }; +static const int mt7988_xfi_phy1_i2c0_funcs[] = { 6, 6 }; + +static const int mt7988_xfi_phy_pll_i2c0_pins[] = { 3, 4 }; +static const int mt7988_xfi_phy_pll_i2c0_funcs[] = { 5, 5 }; + +static const int mt7988_xfi_phy_pll_i2c1_pins[] = { 3, 4 }; +static const int mt7988_xfi_phy_pll_i2c1_funcs[] = { 6, 6 }; + +static const int mt7988_i2c0_0_pins[] = { 5, 6 }; +static const int mt7988_i2c0_0_funcs[] = { 2, 2 }; + +static const int mt7988_i2c1_sfp_pins[] = { 5, 6 }; +static const int mt7988_i2c1_sfp_funcs[] = { 4, 4 }; + +static const int mt7988_xfi_pextp_phy0_i2c_pins[] = { 5, 6 }; +static const int mt7988_xfi_pextp_phy0_i2c_funcs[] = { 5, 5 }; + +static const int mt7988_xfi_pextp_phy1_i2c_pins[] = { 5, 6 }; +static const int mt7988_xfi_pextp_phy1_i2c_funcs[] = { 6, 6 }; + +static const int mt7988_i2c0_1_pins[] = { 15, 16 }; +static const int mt7988_i2c0_1_funcs[] = { 1, 1 }; + +static const int mt7988_u30_phy_i2c0_pins[] = { 15, 16 }; +static const int mt7988_u30_phy_i2c0_funcs[] = { 2, 2 }; + +static const int mt7988_u32_phy_i2c0_pins[] = { 15, 16 }; +static const int mt7988_u32_phy_i2c0_funcs[] = { 3, 3 }; + +static const int mt7988_xfi_phy0_i2c1_pins[] = { 15, 16 }; +static const int mt7988_xfi_phy0_i2c1_funcs[] = { 5, 5 }; + +static const int mt7988_xfi_phy1_i2c1_pins[] = { 15, 16 }; +static const int mt7988_xfi_phy1_i2c1_funcs[] = { 6, 6 }; + +static const int mt7988_xfi_phy_pll_i2c2_pins[] = { 15, 16 }; +static const int mt7988_xfi_phy_pll_i2c2_funcs[] = { 7, 7 }; + +static const int mt7988_i2c1_0_pins[] = { 17, 18 }; +static const int mt7988_i2c1_0_funcs[] = { 1, 1 }; + +static const int mt7988_u30_phy_i2c1_pins[] = { 17, 18 }; +static const int mt7988_u30_phy_i2c1_funcs[] = { 2, 2 }; + +static const int mt7988_u32_phy_i2c1_pins[] = { 17, 18 }; +static const int mt7988_u32_phy_i2c1_funcs[] = { 3, 3 }; + +static const int mt7988_xfi_phy_pll_i2c3_pins[] = { 17, 18 }; +static const int mt7988_xfi_phy_pll_i2c3_funcs[] = { 4, 4 }; + +static const int mt7988_sgmii0_i2c_pins[] = { 17, 18 }; +static const int mt7988_sgmii0_i2c_funcs[] = { 5, 5 }; + +static const int mt7988_sgmii1_i2c_pins[] = { 17, 18 }; +static const int mt7988_sgmii1_i2c_funcs[] = { 6, 6 }; + +static const int mt7988_i2c1_2_pins[] = { 69, 70 }; +static const int mt7988_i2c1_2_funcs[] = { 2, 2 }; + +static const int mt7988_i2c2_0_pins[] = { 69, 70 }; +static const int mt7988_i2c2_0_funcs[] = { 4, 4 }; + +static const int mt7988_i2c2_1_pins[] = { 71, 72 }; +static const int mt7988_i2c2_1_funcs[] = { 1, 1 }; + +/* eth */ +static const int mt7988_mdc_mdio0_pins[] = { 5, 6 }; +static const int mt7988_mdc_mdio0_funcs[] = { 1, 1 }; + +static const int mt7988_2p5g_ext_mdio_pins[] = { 28, 29 }; +static const int mt7988_2p5g_ext_mdio_funcs[] = { 6, 6 }; + +static const int mt7988_gbe_ext_mdio_pins[] = { 30, 31 }; +static const int mt7988_gbe_ext_mdio_funcs[] = { 6, 6 }; + +static const int mt7988_mdc_mdio1_pins[] = { 69, 70 }; +static const int mt7988_mdc_mdio1_funcs[] = { 1, 1 }; + +/* pcie */ +static const int mt7988_pcie_wake_n0_0_pins[] = { 7 }; +static const int mt7988_pcie_wake_n0_0_funcs[] = { 1 }; + +static const int mt7988_pcie_clk_req_n0_0_pins[] = { 8 }; +static const int mt7988_pcie_clk_req_n0_0_funcs[] = { 1 }; + +static const int mt7988_pcie_wake_n3_0_pins[] = { 9 }; +static const int mt7988_pcie_wake_n3_0_funcs[] = { 1 }; + +static const int mt7988_pcie_clk_req_n3_pins[] = { 10 }; +static const int mt7988_pcie_clk_req_n3_funcs[] = { 1 }; + +static const int mt7988_pcie_clk_req_n0_1_pins[] = { 10 }; +static const int mt7988_pcie_clk_req_n0_1_funcs[] = { 2 }; + +static const int mt7988_pcie_p0_phy_i2c_pins[] = { 7, 8 }; +static const int mt7988_pcie_p0_phy_i2c_funcs[] = { 3, 3 }; + +static const int mt7988_pcie_p1_phy_i2c_pins[] = { 7, 8 }; +static const int mt7988_pcie_p1_phy_i2c_funcs[] = { 4, 4 }; + +static const int mt7988_pcie_p3_phy_i2c_pins[] = { 9, 10 }; +static const int mt7988_pcie_p3_phy_i2c_funcs[] = { 4, 4 }; + +static const int mt7988_pcie_p2_phy_i2c_pins[] = { 7, 8 }; +static const int mt7988_pcie_p2_phy_i2c_funcs[] = { 5, 5 }; + +static const int mt7988_ckm_phy_i2c_pins[] = { 9, 10 }; +static const int mt7988_ckm_phy_i2c_funcs[] = { 5, 5 }; + +static const int mt7988_pcie_wake_n0_1_pins[] = { 13 }; +static const int mt7988_pcie_wake_n0_1_funcs[] = { 2 }; + +static const int mt7988_pcie_wake_n3_1_pins[] = { 14 }; +static const int mt7988_pcie_wake_n3_1_funcs[] = { 2 }; + +static const int mt7988_pcie_2l_0_pereset_pins[] = { 19 }; +static const int mt7988_pcie_2l_0_pereset_funcs[] = { 1 }; + +static const int mt7988_pcie_1l_1_pereset_pins[] = { 20 }; +static const int mt7988_pcie_1l_1_pereset_funcs[] = { 1 }; + +static const int mt7988_pcie_clk_req_n2_1_pins[] = { 63 }; +static const int mt7988_pcie_clk_req_n2_1_funcs[] = { 2 }; + +static const int mt7988_pcie_2l_1_pereset_pins[] = { 73 }; +static const int mt7988_pcie_2l_1_pereset_funcs[] = { 1 }; + +static const int mt7988_pcie_1l_0_pereset_pins[] = { 74 }; +static const int mt7988_pcie_1l_0_pereset_funcs[] = { 1 }; + +static const int mt7988_pcie_wake_n1_0_pins[] = { 75 }; +static const int mt7988_pcie_wake_n1_0_funcs[] = { 1 }; + +static const int mt7988_pcie_clk_req_n1_pins[] = { 76 }; +static const int mt7988_pcie_clk_req_n1_funcs[] = { 1 }; + +static const int mt7988_pcie_wake_n2_0_pins[] = { 77 }; +static const int mt7988_pcie_wake_n2_0_funcs[] = { 1 }; + +static const int mt7988_pcie_clk_req_n2_0_pins[] = { 78 }; +static const int mt7988_pcie_clk_req_n2_0_funcs[] = { 1 }; + +static const int mt7988_pcie_wake_n2_1_pins[] = { 79 }; +static const int mt7988_pcie_wake_n2_1_funcs[] = { 2 }; + +/* pmic */ +static const int mt7988_pmic_pins[] = { 11 }; +static const int mt7988_pmic_funcs[] = { 1 }; + +/* watchdog */ +static const int mt7988_watchdog_pins[] = { 12 }; +static const int mt7988_watchdog_funcs[] = { 1 }; + +/* spi */ +static const int mt7988_spi0_wp_hold_pins[] = { 22, 23 }; +static const int mt7988_spi0_wp_hold_funcs[] = { 1, 1 }; + +static const int mt7988_spi0_pins[] = { 24, 25, 26, 27 }; +static const int mt7988_spi0_funcs[] = { 1, 1, 1, 1 }; + +static const int mt7988_spi1_pins[] = { 28, 29, 30, 31 }; +static const int mt7988_spi1_funcs[] = { 1, 1, 1, 1 }; + +static const int mt7988_spi2_pins[] = { 32, 33, 34, 35 }; +static const int mt7988_spi2_funcs[] = { 1, 1, 1, 1 }; + +static const int mt7988_spi2_wp_hold_pins[] = { 36, 37 }; +static const int mt7988_spi2_wp_hold_funcs[] = { 1, 1 }; + +/* flash */ +static const int mt7988_snfi_pins[] = { 22, 23, 24, 25, 26, 27 }; +static const int mt7988_snfi_funcs[] = { 2, 2, 2, 2, 2, 2 }; + +static const int mt7988_emmc_45_pins[] = { + 21, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37 }; +static const int mt7988_emmc_45_funcs[] = { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5 }; + +static const int mt7988_emmc_51_pins[] = { + 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49 }; +static const int mt7988_emmc_51_funcs[] = { + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }; + +/* uart */ +static const int mt7988_uart2_pins[] = { 0, 1, 2, 3 }; +static const int mt7988_uart2_funcs[] = { 1, 1, 1, 1 }; + +static const int mt7988_tops_uart0_0_pins[] = { 22, 23 }; +static const int mt7988_tops_uart0_0_funcs[] = { 3, 3 }; + +static const int mt7988_uart2_0_pins[] = { 28, 29, 30, 31 }; +static const int mt7988_uart2_0_funcs[] = { 2, 2, 2, 2 }; + +static const int mt7988_uart1_0_pins[] = { 32, 33, 34, 35 }; +static const int mt7988_uart1_0_funcs[] = { 2, 2, 2, 2 }; + +static const int mt7988_uart2_1_pins[] = { 32, 33, 34, 35 }; +static const int mt7988_uart2_1_funcs[] = { 3, 3, 3, 3 }; + +static const int mt7988_net_wo0_uart_txd_0_pins[] = { 28 }; +static const int mt7988_net_wo0_uart_txd_0_funcs[] = { 3 }; + +static const int mt7988_net_wo1_uart_txd_0_pins[] = { 29 }; +static const int mt7988_net_wo1_uart_txd_0_funcs[] = { 3 }; + +static const int mt7988_net_wo2_uart_txd_0_pins[] = { 30 }; +static const int mt7988_net_wo2_uart_txd_0_funcs[] = { 3 }; + +static const int mt7988_tops_uart1_0_pins[] = { 28, 29 }; +static const int mt7988_tops_uart1_0_funcs[] = { 4, 4 }; + +static const int mt7988_tops_uart0_1_pins[] = { 30, 31 }; +static const int mt7988_tops_uart0_1_funcs[] = { 4, 4 }; + +static const int mt7988_tops_uart1_1_pins[] = { 36, 37 }; +static const int mt7988_tops_uart1_1_funcs[] = { 3, 3 }; + +static const int mt7988_uart0_pins[] = { 55, 56 }; +static const int mt7988_uart0_funcs[] = { 1, 1 }; + +static const int mt7988_tops_uart0_2_pins[] = { 55, 56 }; +static const int mt7988_tops_uart0_2_funcs[] = { 2, 2 }; + +static const int mt7988_uart2_2_pins[] = { 50, 51, 52, 53 }; +static const int mt7988_uart2_2_funcs[] = { 2, 2, 2, 2 }; + +static const int mt7988_uart1_1_pins[] = { 58, 59, 60, 61 }; +static const int mt7988_uart1_1_funcs[] = { 2, 2, 2, 2 }; + +static const int mt7988_uart2_3_pins[] = { 58, 59, 60, 61 }; +static const int mt7988_uart2_3_funcs[] = { 3, 3, 3, 3 }; + +static const int mt7988_uart1_2_pins[] = { 80, 81, 82, 83 }; +static const int mt7988_uart1_2_funcs[] = { 1, 1, 1, 1 }; + +static const int mt7988_tops_uart1_2_pins[] = { 80, 81 }; +static const int mt7988_tops_uart1_2_funcs[] = { 4, 4, }; + +static const int mt7988_net_wo0_uart_txd_1_pins[] = { 80 }; +static const int mt7988_net_wo0_uart_txd_1_funcs[] = { 3 }; + +static const int mt7988_net_wo1_uart_txd_1_pins[] = { 81 }; +static const int mt7988_net_wo1_uart_txd_1_funcs[] = { 3 }; + +static const int mt7988_net_wo2_uart_txd_1_pins[] = { 82 }; +static const int mt7988_net_wo2_uart_txd_1_funcs[] = { 3 }; + +/* udi */ +static const int mt7988_udi_pins[] = { 32, 33, 34, 35, 36 }; +static const int mt7988_udi_funcs[] = { 4, 4, 4, 4, 4 }; + +/* pcm */ +static const int mt7988_pcm_pins[] = { 50, 51, 52, 53, 54 }; +static const int mt7988_pcm_funcs[] = { 1, 1, 1, 1, 1 }; + +/* led */ +static const int mt7988_gbe_led1_pins[] = { 58, 59, 60, 61 }; +static const int mt7988_gbe_led1_funcs[] = { 6, 6, 6, 6 }; + +static const int mt7988_2p5gbe_led1_pins[] = { 62 }; +static const int mt7988_2p5gbe_led1_funcs[] = { 6 }; + +static const int mt7988_gbe_led0_pins[] = { 64, 65, 66, 67 }; +static const int mt7988_gbe_led0_funcs[] = { 1, 1, 1, 1 }; + +static const int mt7988_2p5gbe_led0_pins[] = { 68 }; +static const int mt7988_2p5gbe_led0_funcs[] = { 1 }; + +/* usb */ +static const int mt7988_drv_vbus_p1_pins[] = { 63 }; +static const int mt7988_drv_vbus_p1_funcs[] = { 1 }; + +static const int mt7988_drv_vbus_pins[] = { 79 }; +static const int mt7988_drv_vbus_funcs[] = { 1 }; + +static const struct mtk_group_desc mt7988_groups[] = { + PINCTRL_PIN_GROUP("uart2", mt7988_uart2), + PINCTRL_PIN_GROUP("tops_jtag0_0", mt7988_tops_jtag0_0), + PINCTRL_PIN_GROUP("int_usxgmii", mt7988_int_usxgmii), + PINCTRL_PIN_GROUP("dfd", mt7988_dfd), + PINCTRL_PIN_GROUP("xfi_phy0_i2c0", mt7988_xfi_phy0_i2c0), + PINCTRL_PIN_GROUP("xfi_phy1_i2c0", mt7988_xfi_phy1_i2c0), + PINCTRL_PIN_GROUP("xfi_phy_pll_i2c0", mt7988_xfi_phy_pll_i2c0), + PINCTRL_PIN_GROUP("xfi_phy_pll_i2c1", mt7988_xfi_phy_pll_i2c1), + PINCTRL_PIN_GROUP("i2c0_0", mt7988_i2c0_0), + PINCTRL_PIN_GROUP("i2c1_sfp", mt7988_i2c1_sfp), + PINCTRL_PIN_GROUP("xfi_pextp_phy0_i2c", mt7988_xfi_pextp_phy0_i2c), + PINCTRL_PIN_GROUP("xfi_pextp_phy1_i2c", mt7988_xfi_pextp_phy1_i2c), + PINCTRL_PIN_GROUP("mdc_mdio0", mt7988_mdc_mdio0), + PINCTRL_PIN_GROUP("pcie_wake_n0_0", mt7988_pcie_wake_n0_0), + PINCTRL_PIN_GROUP("pcie_clk_req_n0_0", mt7988_pcie_clk_req_n0_0), + PINCTRL_PIN_GROUP("pcie_wake_n3_0", mt7988_pcie_wake_n3_0), + PINCTRL_PIN_GROUP("pcie_clk_req_n3", mt7988_pcie_clk_req_n3), + PINCTRL_PIN_GROUP("pcie_clk_req_n0_1", mt7988_pcie_clk_req_n0_1), + PINCTRL_PIN_GROUP("pcie_p0_phy_i2c", mt7988_pcie_p0_phy_i2c), + PINCTRL_PIN_GROUP("pcie_p1_phy_i2c", mt7988_pcie_p1_phy_i2c), + PINCTRL_PIN_GROUP("pcie_p2_phy_i2c", mt7988_pcie_p2_phy_i2c), + PINCTRL_PIN_GROUP("pcie_p3_phy_i2c", mt7988_pcie_p3_phy_i2c), + PINCTRL_PIN_GROUP("ckm_phy_i2c", mt7988_ckm_phy_i2c), + PINCTRL_PIN_GROUP("pcie_pmic", mt7988_pmic), + PINCTRL_PIN_GROUP("watchdog", mt7988_watchdog), + PINCTRL_PIN_GROUP("pcie_wake_n0_1", mt7988_pcie_wake_n0_1), + PINCTRL_PIN_GROUP("pcie_wake_n3_1", mt7988_pcie_wake_n3_1), + PINCTRL_PIN_GROUP("i2c0_1", mt7988_i2c0_1), + PINCTRL_PIN_GROUP("u30_phy_i2c0", mt7988_u30_phy_i2c0), + PINCTRL_PIN_GROUP("u32_phy_i2c0", mt7988_u32_phy_i2c0), + PINCTRL_PIN_GROUP("xfi_phy0_i2c1", mt7988_xfi_phy0_i2c1), + PINCTRL_PIN_GROUP("xfi_phy1_i2c1", mt7988_xfi_phy1_i2c1), + PINCTRL_PIN_GROUP("xfi_phy_pll_i2c2", mt7988_xfi_phy_pll_i2c2), + PINCTRL_PIN_GROUP("i2c1_0", mt7988_i2c1_0), + PINCTRL_PIN_GROUP("u30_phy_i2c1", mt7988_u30_phy_i2c1), + PINCTRL_PIN_GROUP("u32_phy_i2c1", mt7988_u32_phy_i2c1), + PINCTRL_PIN_GROUP("xfi_phy_pll_i2c3", mt7988_xfi_phy_pll_i2c3), + PINCTRL_PIN_GROUP("sgmii0_i2c", mt7988_sgmii0_i2c), + PINCTRL_PIN_GROUP("sgmii1_i2c", mt7988_sgmii1_i2c), + PINCTRL_PIN_GROUP("pcie_2l_0_pereset", mt7988_pcie_2l_0_pereset), + PINCTRL_PIN_GROUP("pcie_1l_1_pereset", mt7988_pcie_1l_1_pereset), + PINCTRL_PIN_GROUP("pwm1", mt7988_pwm1), + PINCTRL_PIN_GROUP("spi0_wp_hold", mt7988_spi0_wp_hold), + PINCTRL_PIN_GROUP("spi0", mt7988_spi0), + PINCTRL_PIN_GROUP("spi1", mt7988_spi1), + PINCTRL_PIN_GROUP("spi2", mt7988_spi2), + PINCTRL_PIN_GROUP("spi2_wp_hold", mt7988_spi2_wp_hold), + PINCTRL_PIN_GROUP("snfi", mt7988_snfi), + PINCTRL_PIN_GROUP("tops_uart0_0", mt7988_tops_uart0_0), + PINCTRL_PIN_GROUP("uart2_0", mt7988_uart2_0), + PINCTRL_PIN_GROUP("uart1_0", mt7988_uart1_0), + PINCTRL_PIN_GROUP("uart2_1", mt7988_uart2_1), + PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7988_net_wo0_uart_txd_0), + PINCTRL_PIN_GROUP("net_wo1_uart_txd_0", mt7988_net_wo1_uart_txd_0), + PINCTRL_PIN_GROUP("net_wo2_uart_txd_0", mt7988_net_wo2_uart_txd_0), + PINCTRL_PIN_GROUP("tops_uart0_0", mt7988_tops_uart1_0), + PINCTRL_PIN_GROUP("tops_uart0_1", mt7988_tops_uart0_1), + PINCTRL_PIN_GROUP("tops_uart1_1", mt7988_tops_uart1_1), + PINCTRL_PIN_GROUP("udi", mt7988_udi), + PINCTRL_PIN_GROUP("emmc_45", mt7988_emmc_45), + PINCTRL_PIN_GROUP("emmc_51", mt7988_emmc_51), + PINCTRL_PIN_GROUP("2p5g_ext_mdio", mt7988_2p5g_ext_mdio), + PINCTRL_PIN_GROUP("gbe_ext_mdio", mt7988_gbe_ext_mdio), + PINCTRL_PIN_GROUP("pcm", mt7988_pcm), + PINCTRL_PIN_GROUP("uart0", mt7988_uart0), + PINCTRL_PIN_GROUP("tops_uart0_2", mt7988_tops_uart0_2), + PINCTRL_PIN_GROUP("uart2_2", mt7988_uart2_2), + PINCTRL_PIN_GROUP("wo0_jtag", mt7988_wo0_jtag), + PINCTRL_PIN_GROUP("wo1_jtag", mt7988_wo1_jtag), + PINCTRL_PIN_GROUP("wo2_jtag", mt7988_wo2_jtag), + PINCTRL_PIN_GROUP("pwm0", mt7988_pwm0), + PINCTRL_PIN_GROUP("jtag", mt7988_jtag), + PINCTRL_PIN_GROUP("tops_jtag0_1", mt7988_tops_jtag0_1), + PINCTRL_PIN_GROUP("uart2_3", mt7988_uart2_3), + PINCTRL_PIN_GROUP("uart1_1", mt7988_uart1_1), + PINCTRL_PIN_GROUP("gbe_led1", mt7988_gbe_led1), + PINCTRL_PIN_GROUP("2p5gbe_led1", mt7988_2p5gbe_led1), + PINCTRL_PIN_GROUP("gbe_led0", mt7988_gbe_led0), + PINCTRL_PIN_GROUP("2p5gbe_led0", mt7988_2p5gbe_led0), + PINCTRL_PIN_GROUP("drv_vbus_p1", mt7988_drv_vbus_p1), + PINCTRL_PIN_GROUP("pcie_clk_req_n2_1", mt7988_pcie_clk_req_n2_1), + PINCTRL_PIN_GROUP("mdc_mdio1", mt7988_mdc_mdio1), + PINCTRL_PIN_GROUP("i2c1_2", mt7988_i2c1_2), + PINCTRL_PIN_GROUP("pwm6", mt7988_pwm6), + PINCTRL_PIN_GROUP("pwm7", mt7988_pwm7), + PINCTRL_PIN_GROUP("i2c2_0", mt7988_i2c2_0), + PINCTRL_PIN_GROUP("i2c2_1", mt7988_i2c2_1), + PINCTRL_PIN_GROUP("pcie_2l_1_pereset", mt7988_pcie_2l_1_pereset), + PINCTRL_PIN_GROUP("pcie_1l_0_pereset", mt7988_pcie_1l_0_pereset), + PINCTRL_PIN_GROUP("pcie_wake_n1_0", mt7988_pcie_wake_n1_0), + PINCTRL_PIN_GROUP("pcie_clk_req_n1", mt7988_pcie_clk_req_n1), + PINCTRL_PIN_GROUP("pcie_wake_n2_0", mt7988_pcie_wake_n2_0), + PINCTRL_PIN_GROUP("pcie_clk_req_n2_0", mt7988_pcie_clk_req_n2_0), + PINCTRL_PIN_GROUP("drv_vbus", mt7988_drv_vbus), + PINCTRL_PIN_GROUP("pcie_wake_n2_1", mt7988_pcie_wake_n2_1), + PINCTRL_PIN_GROUP("uart1_2", mt7988_uart1_2), + PINCTRL_PIN_GROUP("pwm2", mt7988_pwm2), + PINCTRL_PIN_GROUP("pwm3", mt7988_pwm3), + PINCTRL_PIN_GROUP("pwm4", mt7988_pwm4), + PINCTRL_PIN_GROUP("pwm5", mt7988_pwm5), + PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7988_net_wo0_uart_txd_0), + PINCTRL_PIN_GROUP("net_wo1_uart_txd_0", mt7988_net_wo1_uart_txd_0), + PINCTRL_PIN_GROUP("net_wo2_uart_txd_0", mt7988_net_wo2_uart_txd_0), + PINCTRL_PIN_GROUP("tops_uart1_2", mt7988_tops_uart1_2), + PINCTRL_PIN_GROUP("net_wo0_uart_txd_1", mt7988_net_wo0_uart_txd_1), + PINCTRL_PIN_GROUP("net_wo1_uart_txd_1", mt7988_net_wo1_uart_txd_1), + PINCTRL_PIN_GROUP("net_wo2_uart_txd_1", mt7988_net_wo2_uart_txd_1), +}; + +static const struct mtk_io_type_desc mt7988_io_type_desc[] = { + [IO_TYPE_GRP0] = { + .name = "18OD33", + .bias_set = mtk_pinconf_bias_set_pupd_r1_r0, + .drive_set = mtk_pinconf_drive_set_v1, + .input_enable = mtk_pinconf_input_enable_v1, + }, + [IO_TYPE_GRP1] = { + .name = "18A01", + .bias_set = mtk_pinconf_bias_set_pu_pd, + .drive_set = mtk_pinconf_drive_set_v1, + .input_enable = mtk_pinconf_input_enable_v1, + }, + [IO_TYPE_GRP2] = { + .name = "I2C", + .input_enable = mtk_pinconf_input_enable_v1, + }, +}; + +/* Joint those groups owning the same capability in user point of view which + * allows that people tend to use through the device tree. + */ +static const char *const mt7988_jtag_groups[] = { "tops_jtag0_0", "wo0_jtag", + "wo1_jtag", "wo2_jtag", "jtag", "tops_jtag0_1", }; +static const char *const mt7988_int_usxgmii_groups[] = { "int_usxgmii", }; +static const char *const mt7988_pwm_groups[] = { "pwm0", "pwm1", "pwm2", "pwm3", + "pwm4", "pwm5", "pwm6", "pwm7" }; +static const char *const mt7988_dfd_groups[] = { "dfd", }; +static const char *const mt7988_i2c_groups[] = { "xfi_phy0_i2c0", + "xfi_phy1_i2c0", "xfi_phy_pll_i2c0", "xfi_phy_pll_i2c1", "i2c0_0", + "i2c1_sfp", "xfi_pextp_phy0_i2c", "xfi_pextp_phy1_i2c", "i2c0_1", + "u30_phy_i2c0", "u32_phy_i2c0", "xfi_phy0_i2c1", "xfi_phy1_i2c1", + "xfi_phy_pll_i2c2", "i2c1_0", "u30_phy_i2c1", "u32_phy_i2c1", + "xfi_phy_pll_i2c3", "sgmii0_i2c", "sgmii1_i2c", "i2c1_2", "i2c2_0", + "i2c2_1", }; +static const char *const mt7988_ethernet_groups[] = { "mdc_mdio0", + "2p5g_ext_mdio", "gbe_ext_mdio", "mdc_mdio1", }; +static const char *const mt7988_pcie_groups[] = { "pcie_wake_n0_0", + "pcie_clk_req_n0_0", "pcie_wake_n3_0", "pcie_clk_req_n3", + "pcie_p0_phy_i2c", "pcie_p1_phy_i2c", "pcie_p3_phy_i2", + "pcie_p2_phy_i2c", "ckm_phy_i2c", "pcie_wake_n0_1", "pcie_wake_n3_1", + "pcie_2l_0_pereset", "pcie_1l_1_pereset", "pcie_clk_req_n2_1", + "pcie_2l_1_perese", "pcie_1l_0_pereset", "pcie_wake_n1_0", + "cie_clk_req_n1", "pcie_wake_n2_0", "pcie_wake_n2_1", }; +static const char *const mt7988_pmic_groups[] = { "pmic", }; +static const char *const mt7988_wdt_groups[] = { "watchdog", }; +static const char *const mt7988_spi_groups[] = { "spi0", "spi0_wp_hold", + "spi1", "spi2", "spi2_wp_hold", }; +static const char *const mt7988_flash_groups[] = { "emmc_45", "snfi", + "emmc_51" }; +static const char *const mt7988_uart_groups[] = { "uart2", "tops_uart0_0", + "uart2_0", "uart1_0", "uart2_1", + "net_wo0_uart_txd_0", "net_wo1_uart_txd_0", "net_wo2_uart_txd_0", + "tops_uart1_0", "ops_uart0_1", "ops_uart1_1", + "uart0", "tops_uart0_2", "uart1_1", + "uart2_3", "uart1_2", "tops_uart1_2", + "net_wo0_uart_txd_1", "net_wo1_uart_txd_1", "net_wo2_uart_txd_1", }; +static const char *const mt7988_udi_groups[] = { "udi", }; +static const char *const mt7988_pcm_groups[] = { "pcm", }; +static const char *const mt7988_led_groups[] = { "gbe_led1", "2p5gbe_led1", + "gbe_led0", "2p5gbe_led0", "wf5g_led0", "wf5g_led1", }; +static const char *const mt7988_usb_groups[] = { "drv_vbus", "drv_vbus_p1", }; + +static const struct mtk_function_desc mt7988_functions[] = { + {"jtag", mt7988_jtag_groups, ARRAY_SIZE(mt7988_jtag_groups)}, + {"int_usxgmii", mt7988_int_usxgmii_groups, + ARRAY_SIZE(mt7988_int_usxgmii_groups)}, + {"pwm", mt7988_pwm_groups, ARRAY_SIZE(mt7988_pwm_groups)}, + {"dfd", mt7988_dfd_groups, ARRAY_SIZE(mt7988_dfd_groups)}, + {"i2c", mt7988_i2c_groups, ARRAY_SIZE(mt7988_i2c_groups)}, + {"eth", mt7988_ethernet_groups, ARRAY_SIZE(mt7988_ethernet_groups)}, + {"pcie", mt7988_pcie_groups, ARRAY_SIZE(mt7988_pcie_groups)}, + {"pmic", mt7988_pmic_groups, ARRAY_SIZE(mt7988_pmic_groups)}, + {"watchdog", mt7988_wdt_groups, ARRAY_SIZE(mt7988_wdt_groups)}, + {"spi", mt7988_spi_groups, ARRAY_SIZE(mt7988_spi_groups)}, + {"flash", mt7988_flash_groups, ARRAY_SIZE(mt7988_flash_groups)}, + {"uart", mt7988_uart_groups, ARRAY_SIZE(mt7988_uart_groups)}, + {"udi", mt7988_udi_groups, ARRAY_SIZE(mt7988_udi_groups)}, + {"pcm", mt7988_pcm_groups, ARRAY_SIZE(mt7988_pcm_groups)}, + {"usb", mt7988_usb_groups, ARRAY_SIZE(mt7988_usb_groups)}, + {"led", mt7988_led_groups, ARRAY_SIZE(mt7988_led_groups)}, +}; + +static const char *const mt7988_pinctrl_register_base_names[] = { + "gpio_base", "iocfg_tr_base", "iocfg_br_base", "iocfg_rb_base", + "iocfg_lb_base", "iocfg_tl_base", +}; + +static const struct mtk_pinctrl_soc mt7988_data = { + .name = "mt7988_pinctrl", + .reg_cal = mt7988_reg_cals, + .pins = mt7988_pins, + .npins = ARRAY_SIZE(mt7988_pins), + .grps = mt7988_groups, + .ngrps = ARRAY_SIZE(mt7988_groups), + .funcs = mt7988_functions, + .nfuncs = ARRAY_SIZE(mt7988_functions), + .io_type = mt7988_io_type_desc, + .ntype = ARRAY_SIZE(mt7988_io_type_desc), + .gpio_mode = 0, + .base_names = mt7988_pinctrl_register_base_names, + .nbase_names = ARRAY_SIZE(mt7988_pinctrl_register_base_names), + .base_calc = 1, +}; + +static int mtk_pinctrl_mt7988_probe(struct udevice *dev) +{ + return mtk_pinctrl_common_probe(dev, &mt7988_data); +} + +static const struct udevice_id mt7988_pctrl_match[] = { + {.compatible = "mediatek,mt7988-pinctrl"}, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(mt7988_pinctrl) = { + .name = "mt7988_pinctrl", + .id = UCLASS_PINCTRL, + .of_match = mt7988_pctrl_match, + .ops = &mtk_pinctrl_ops, + .probe = mtk_pinctrl_mt7988_probe, + .priv_auto = sizeof(struct mtk_pinctrl_priv), +}; diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8512.c b/drivers/pinctrl/mediatek/pinctrl-mt8512.c index 3d9c0abe36b..bc5fb83ac68 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8512.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8512.c @@ -315,12 +315,12 @@ static const struct mtk_pin_desc mt8512_pins[] = { */ /* UART */ -static int mt8512_uart0_0_rxd_txd_pins[] = { 52, 53, }; -static int mt8512_uart0_0_rxd_txd_funcs[] = { 1, 1, }; -static int mt8512_uart1_0_rxd_txd_pins[] = { 54, 55, }; -static int mt8512_uart1_0_rxd_txd_funcs[] = { 1, 1, }; -static int mt8512_uart2_0_rxd_txd_pins[] = { 28, 29, }; -static int mt8512_uart2_0_rxd_txd_funcs[] = { 1, 1, }; +static const int mt8512_uart0_0_rxd_txd_pins[] = { 52, 53, }; +static const int mt8512_uart0_0_rxd_txd_funcs[] = { 1, 1, }; +static const int mt8512_uart1_0_rxd_txd_pins[] = { 54, 55, }; +static const int mt8512_uart1_0_rxd_txd_funcs[] = { 1, 1, }; +static const int mt8512_uart2_0_rxd_txd_pins[] = { 28, 29, }; +static const int mt8512_uart2_0_rxd_txd_funcs[] = { 1, 1, }; /* Joint those groups owning the same capability in user point of view which * allows that people tend to use through the device tree. @@ -330,13 +330,13 @@ static const char *const mt8512_uart_groups[] = { "uart0_0_rxd_txd", "uart2_0_rxd_txd", }; /* SNAND */ -static int mt8512_snfi_pins[] = { 71, 76, 77, 78, 79, 80, }; -static int mt8512_snfi_funcs[] = { 3, 3, 3, 3, 3, 3, }; +static const int mt8512_snfi_pins[] = { 71, 76, 77, 78, 79, 80, }; +static const int mt8512_snfi_funcs[] = { 3, 3, 3, 3, 3, 3, }; /* MMC0 */ -static int mt8512_msdc0_pins[] = { 76, 77, 78, 79, 80, 81, 82, 83, 84, - 85, 86, }; -static int mt8512_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; +static const int mt8512_msdc0_pins[] = { 76, 77, 78, 79, 80, 81, 82, 83, 84, + 85, 86, }; +static const int mt8512_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; static const struct mtk_group_desc mt8512_groups[] = { PINCTRL_PIN_GROUP("uart0_0_rxd_txd", mt8512_uart0_0_rxd_txd), @@ -356,7 +356,7 @@ static const struct mtk_function_desc mt8512_functions[] = { {"snand", mt8512_msdc_groups, ARRAY_SIZE(mt8512_msdc_groups)}, }; -static struct mtk_pinctrl_soc mt8512_data = { +static const struct mtk_pinctrl_soc mt8512_data = { .name = "mt8512_pinctrl", .reg_cal = mt8512_reg_cals, .pins = mt8512_pins, diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8516.c b/drivers/pinctrl/mediatek/pinctrl-mt8516.c index 6f94f762d98..7487d6f0605 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8516.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8516.c @@ -326,12 +326,12 @@ static const struct mtk_pin_desc mt8516_pins[] = { */ /* UART */ -static int mt8516_uart0_0_rxd_txd_pins[] = { 62, 63, }; -static int mt8516_uart0_0_rxd_txd_funcs[] = { 1, 1, }; -static int mt8516_uart1_0_rxd_txd_pins[] = { 64, 65, }; -static int mt8516_uart1_0_rxd_txd_funcs[] = { 1, 1, }; -static int mt8516_uart2_0_rxd_txd_pins[] = { 34, 35, }; -static int mt8516_uart2_0_rxd_txd_funcs[] = { 1, 1, }; +static const int mt8516_uart0_0_rxd_txd_pins[] = { 62, 63, }; +static const int mt8516_uart0_0_rxd_txd_funcs[] = { 1, 1, }; +static const int mt8516_uart1_0_rxd_txd_pins[] = { 64, 65, }; +static const int mt8516_uart1_0_rxd_txd_funcs[] = { 1, 1, }; +static const int mt8516_uart2_0_rxd_txd_pins[] = { 34, 35, }; +static const int mt8516_uart2_0_rxd_txd_funcs[] = { 1, 1, }; /* Joint those groups owning the same capability in user point of view which * allows that people tend to use through the device tree. @@ -341,9 +341,9 @@ static const char *const mt8516_uart_groups[] = { "uart0_0_rxd_txd", "uart2_0_rxd_txd", }; /* MMC0 */ -static int mt8516_msdc0_pins[] = { 110, 111, 112, 113, 114, 115, 116, 117, 118, - 119, 120, }; -static int mt8516_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; +static const int mt8516_msdc0_pins[] = { 110, 111, 112, 113, 114, 115, 116, 117, + 118, 119, 120, }; +static const int mt8516_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; static const struct mtk_group_desc mt8516_groups[] = { PINCTRL_PIN_GROUP("uart0_0_rxd_txd", mt8516_uart0_0_rxd_txd), diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8518.c b/drivers/pinctrl/mediatek/pinctrl-mt8518.c index ed51bd3bbc0..66fcfdff144 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8518.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8518.c @@ -346,12 +346,12 @@ static const struct mtk_pin_desc mt8518_pins[] = { */ /* UART */ -static int mt8518_uart0_0_rxd_txd_pins[] = { 104, 105, }; -static int mt8518_uart0_0_rxd_txd_funcs[] = { 1, 1, }; -static int mt8518_uart1_0_rxd_txd_pins[] = { 52, 53, }; -static int mt8518_uart1_0_rxd_txd_funcs[] = { 1, 1, }; -static int mt8518_uart2_0_rxd_txd_pins[] = { 106, 107, }; -static int mt8518_uart2_0_rxd_txd_funcs[] = { 1, 1, }; +static const int mt8518_uart0_0_rxd_txd_pins[] = { 104, 105, }; +static const int mt8518_uart0_0_rxd_txd_funcs[] = { 1, 1, }; +static const int mt8518_uart1_0_rxd_txd_pins[] = { 52, 53, }; +static const int mt8518_uart1_0_rxd_txd_funcs[] = { 1, 1, }; +static const int mt8518_uart2_0_rxd_txd_pins[] = { 106, 107, }; +static const int mt8518_uart2_0_rxd_txd_funcs[] = { 1, 1, }; /* Joint those groups owning the same capability in user point of view which * allows that people tend to use through the device tree. @@ -361,9 +361,9 @@ static const char *const mt8518_uart_groups[] = { "uart0_0_rxd_txd", "uart2_0_rxd_txd", }; /* MMC0 */ -static int mt8518_msdc0_pins[] = { 3, 4, 5, 6, 7, 8, 9, 10, 11, - 12, 13, }; -static int mt8518_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; +static const int mt8518_msdc0_pins[] = { 3, 4, 5, 6, 7, 8, 9, 10, 11, + 12, 13, }; +static const int mt8518_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; static const struct mtk_group_desc mt8518_groups[] = { PINCTRL_PIN_GROUP("uart0_0_rxd_txd", mt8518_uart0_0_rxd_txd), @@ -380,7 +380,7 @@ static const struct mtk_function_desc mt8518_functions[] = { {"msdc", mt8518_msdc_groups, ARRAY_SIZE(mt8518_msdc_groups)}, }; -static struct mtk_pinctrl_soc mt8518_data = { +static const struct mtk_pinctrl_soc mt8518_data = { .name = "mt8518_pinctrl", .reg_cal = mt8518_reg_cals, .pins = mt8518_pins, diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c index 5a4d58b3272..0baef57c1c2 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c @@ -304,6 +304,19 @@ static const char *mtk_get_function_name(struct udevice *dev, return priv->soc->funcs[selector].name; } +static int mtk_pinmux_set(struct udevice *dev, unsigned int pin_selector, + unsigned int func_selector) +{ + int err; + + err = mtk_hw_set_value(dev, pin_selector, PINCTRL_PIN_REG_MODE, + func_selector); + if (err) + return err; + + return 0; +} + static int mtk_pinmux_group_set(struct udevice *dev, unsigned int group_selector, unsigned int func_selector) @@ -314,7 +327,7 @@ static int mtk_pinmux_group_set(struct udevice *dev, int i; for (i = 0; i < grp->num_pins; i++) { - int *pin_modes = grp->data; + const int *pin_modes = grp->data; mtk_hw_set_value(dev, grp->pins[i], PINCTRL_PIN_REG_MODE, pin_modes[i]); @@ -513,7 +526,7 @@ int mtk_pinconf_drive_set_v0(struct udevice *dev, u32 pin, u32 arg) return err; } - return 0; + return err; } int mtk_pinconf_drive_set_v1(struct udevice *dev, u32 pin, u32 arg) @@ -531,7 +544,7 @@ int mtk_pinconf_drive_set_v1(struct udevice *dev, u32 pin, u32 arg) return err; } - return 0; + return err; } int mtk_pinconf_drive_set(struct udevice *dev, u32 pin, u32 arg) @@ -647,6 +660,7 @@ const struct pinctrl_ops mtk_pinctrl_ops = { .get_group_name = mtk_get_group_name, .get_functions_count = mtk_get_functions_count, .get_function_name = mtk_get_function_name, + .pinmux_set = mtk_pinmux_set, .pinmux_group_set = mtk_pinmux_group_set, #if CONFIG_IS_ENABLED(PINCONF) .pinconf_num_params = ARRAY_SIZE(mtk_conf_params), @@ -769,7 +783,7 @@ static int mtk_gpiochip_register(struct udevice *parent) #endif int mtk_pinctrl_common_probe(struct udevice *dev, - struct mtk_pinctrl_soc *soc) + const struct mtk_pinctrl_soc *soc) { struct mtk_pinctrl_priv *priv = dev_get_priv(dev); int ret = 0; diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h index 0d9596fa72c..c948b808434 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h @@ -174,9 +174,9 @@ struct mtk_pin_desc { */ struct mtk_group_desc { const char *name; - int *pins; + const int *pins; int num_pins; - void *data; + const void *data; }; /** @@ -233,7 +233,7 @@ struct mtk_pinctrl_soc { */ struct mtk_pinctrl_priv { void __iomem *base[MAX_BASE_CALC]; - struct mtk_pinctrl_soc *soc; + const struct mtk_pinctrl_soc *soc; }; extern const struct pinctrl_ops mtk_pinctrl_ops; @@ -242,7 +242,7 @@ extern const struct pinctrl_ops mtk_pinctrl_ops; void mtk_rmw(struct udevice *dev, u32 reg, u32 mask, u32 set); void mtk_i_rmw(struct udevice *dev, u8 i, u32 reg, u32 mask, u32 set); int mtk_pinctrl_common_probe(struct udevice *dev, - struct mtk_pinctrl_soc *soc); + const struct mtk_pinctrl_soc *soc); #if CONFIG_IS_ENABLED(PINCONF) diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3568.c b/drivers/pinctrl/rockchip/pinctrl-rk3568.c index 314edb5a606..1d439198260 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3568.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3568.c @@ -113,11 +113,9 @@ static int rk3568_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) struct rockchip_pinctrl_priv *priv = bank->priv; int iomux_num = (pin / 8); struct regmap *regmap; - int reg, ret, mask; + int reg, mask; u8 bit; - u32 data; - - debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux); + u32 data, rmask; if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) regmap = priv->regmap_pmu; @@ -131,10 +129,10 @@ static int rk3568_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) mask = 0xf; data = (mask << (bit + 16)); + rmask = data | (data >> 16); data |= (mux & mask) << bit; - ret = regmap_write(regmap, reg, data); - return ret; + return regmap_update_bits(regmap, reg, rmask, data); } #define RK3568_PULL_PMU_OFFSET 0x20 @@ -225,7 +223,7 @@ static int rk3568_set_pull(struct rockchip_pin_bank *bank, struct regmap *regmap; int reg, ret; u8 bit, type; - u32 data; + u32 data, rmask; if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT) return -ENOTSUPP; @@ -249,52 +247,59 @@ static int rk3568_set_pull(struct rockchip_pin_bank *bank, /* enable the write to the equivalent lower bits */ data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16); - + rmask = data | (data >> 16); data |= (ret << bit); - ret = regmap_write(regmap, reg, data); - return ret; + return regmap_update_bits(regmap, reg, rmask, data); } +#define GRF_GPIO1C5_DS 0x0840 +#define GRF_GPIO2A2_DS 0x0844 +#define GRF_GPIO2B0_DS 0x0848 +#define GRF_GPIO3A0_DS 0x084c +#define GRF_GPIO3A6_DS 0x0850 +#define GRF_GPIO4A0_DS 0x0854 + static int rk3568_set_drive(struct rockchip_pin_bank *bank, int pin_num, int strength) { struct regmap *regmap; - int reg; - u32 data; + int reg, ret; + u32 data, rmask; u8 bit; int drv = (1 << (strength + 1)) - 1; - int ret = 0; rk3568_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit); /* enable the write to the equivalent lower bits */ data = ((1 << RK3568_DRV_BITS_PER_PIN) - 1) << (bit + 16); + rmask = data | (data >> 16); data |= (drv << bit); - ret = regmap_write(regmap, reg, data); + ret = regmap_update_bits(regmap, reg, rmask, data); if (ret) return ret; if (bank->bank_num == 1 && pin_num == 21) - reg = 0x0840; + reg = GRF_GPIO1C5_DS; else if (bank->bank_num == 2 && pin_num == 2) - reg = 0x0844; + reg = GRF_GPIO2A2_DS; else if (bank->bank_num == 2 && pin_num == 8) - reg = 0x0848; + reg = GRF_GPIO2B0_DS; else if (bank->bank_num == 3 && pin_num == 0) - reg = 0x084c; + reg = GRF_GPIO3A0_DS; else if (bank->bank_num == 3 && pin_num == 6) - reg = 0x0850; + reg = GRF_GPIO3A6_DS; else if (bank->bank_num == 4 && pin_num == 0) - reg = 0x0854; + reg = GRF_GPIO4A0_DS; else return 0; data = ((1 << RK3568_DRV_BITS_PER_PIN) - 1) << 16; - data |= drv; + rmask = data | (data >> 16); + data |= drv >> 6; - return regmap_write(regmap, reg, data); + return regmap_update_bits(regmap, reg, rmask, data); } static int rk3568_set_schmitt(struct rockchip_pin_bank *bank, @@ -302,16 +307,17 @@ static int rk3568_set_schmitt(struct rockchip_pin_bank *bank, { struct regmap *regmap; int reg; - u32 data; + u32 data, rmask; u8 bit; rk3568_calc_schmitt_reg_and_bit(bank, pin_num, ®map, ®, &bit); /* enable the write to the equivalent lower bits */ data = ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1) << (bit + 16); - data |= (enable << bit); + rmask = data | (data >> 16); + data |= ((enable ? 0x2 : 0x1) << bit); - return regmap_write(regmap, reg, data); + return regmap_update_bits(regmap, reg, rmask, data); } static struct rockchip_pin_bank rk3568_pin_banks[] = { |