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-rw-r--r--drivers/reset/Kconfig11
-rw-r--r--drivers/reset/Makefile2
-rw-r--r--drivers/reset/ast2500-reset.c104
-rw-r--r--drivers/reset/reset-ast2500.c109
4 files changed, 115 insertions, 111 deletions
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index b60e11f98b2..33c2736554e 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -72,15 +72,14 @@ config RESET_UNIPHIER
Say Y if you want to control reset signals provided by System Control
block, Media I/O block, Peripheral Block.
-config AST2500_RESET
+config RESET_AST2500
bool "Reset controller driver for AST2500 SoCs"
- depends on DM_RESET && WDT_ASPEED
+ depends on DM_RESET
default y if ASPEED_AST2500
help
- Support for reset controller on AST2500 SoC. This controller uses
- watchdog to reset different peripherals and thus only supports
- resets that are supported by watchdog. The main limitation though
- is that some reset signals, like I2C or MISC reset multiple devices.
+ Support for reset controller on AST2500 SoC.
+ Say Y if you want to control reset signals of different peripherals
+ through System Control Unit (SCU).
config RESET_ROCKCHIP
bool "Reset controller driver for Rockchip SoCs"
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 10a7973f823..fa52aa33291 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -14,7 +14,7 @@ obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o
obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o
obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o
obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
-obj-$(CONFIG_AST2500_RESET) += ast2500-reset.o
+obj-$(CONFIG_RESET_AST2500) += reset-ast2500.o
obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o
obj-$(CONFIG_RESET_MESON) += reset-meson.o
obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
diff --git a/drivers/reset/ast2500-reset.c b/drivers/reset/ast2500-reset.c
deleted file mode 100644
index beb5cd8fa8c..00000000000
--- a/drivers/reset/ast2500-reset.c
+++ /dev/null
@@ -1,104 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2017 Google, Inc
- */
-
-#include <common.h>
-#include <dm.h>
-#include <log.h>
-#include <misc.h>
-#include <reset.h>
-#include <reset-uclass.h>
-#include <wdt.h>
-#include <asm/io.h>
-#include <asm/arch/scu_ast2500.h>
-#include <asm/arch/wdt.h>
-
-struct ast2500_reset_priv {
- /* WDT used to perform resets. */
- struct udevice *wdt;
- struct ast2500_scu *scu;
-};
-
-static int ast2500_ofdata_to_platdata(struct udevice *dev)
-{
- struct ast2500_reset_priv *priv = dev_get_priv(dev);
- int ret;
-
- ret = uclass_get_device_by_phandle(UCLASS_WDT, dev, "aspeed,wdt",
- &priv->wdt);
- if (ret) {
- debug("%s: can't find WDT for reset controller", __func__);
- return ret;
- }
-
- return 0;
-}
-
-static int ast2500_reset_assert(struct reset_ctl *reset_ctl)
-{
- struct ast2500_reset_priv *priv = dev_get_priv(reset_ctl->dev);
- u32 reset_mode, reset_mask;
- bool reset_sdram;
- int ret;
-
- /*
- * To reset SDRAM, a specifal flag in SYSRESET register
- * needs to be enabled first
- */
- reset_mode = ast_reset_mode_from_flags(reset_ctl->id);
- reset_mask = ast_reset_mask_from_flags(reset_ctl->id);
- reset_sdram = reset_mode == WDT_CTRL_RESET_SOC &&
- (reset_mask & WDT_RESET_SDRAM);
-
- if (reset_sdram) {
- ast_scu_unlock(priv->scu);
- setbits_le32(&priv->scu->sysreset_ctrl1,
- SCU_SYSRESET_SDRAM_WDT);
- ret = wdt_expire_now(priv->wdt, reset_ctl->id);
- clrbits_le32(&priv->scu->sysreset_ctrl1,
- SCU_SYSRESET_SDRAM_WDT);
- ast_scu_lock(priv->scu);
- } else {
- ret = wdt_expire_now(priv->wdt, reset_ctl->id);
- }
-
- return ret;
-}
-
-static int ast2500_reset_request(struct reset_ctl *reset_ctl)
-{
- debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
- reset_ctl->dev, reset_ctl->id);
-
- return 0;
-}
-
-static int ast2500_reset_probe(struct udevice *dev)
-{
- struct ast2500_reset_priv *priv = dev_get_priv(dev);
-
- priv->scu = ast_get_scu();
-
- return 0;
-}
-
-static const struct udevice_id ast2500_reset_ids[] = {
- { .compatible = "aspeed,ast2500-reset" },
- { }
-};
-
-struct reset_ops ast2500_reset_ops = {
- .rst_assert = ast2500_reset_assert,
- .request = ast2500_reset_request,
-};
-
-U_BOOT_DRIVER(ast2500_reset) = {
- .name = "ast2500_reset",
- .id = UCLASS_RESET,
- .of_match = ast2500_reset_ids,
- .probe = ast2500_reset_probe,
- .ops = &ast2500_reset_ops,
- .ofdata_to_platdata = ast2500_ofdata_to_platdata,
- .priv_auto_alloc_size = sizeof(struct ast2500_reset_priv),
-};
diff --git a/drivers/reset/reset-ast2500.c b/drivers/reset/reset-ast2500.c
new file mode 100644
index 00000000000..e7b5c7decab
--- /dev/null
+++ b/drivers/reset/reset-ast2500.c
@@ -0,0 +1,109 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2017 Google, Inc
+ * Copyright 2020 ASPEED Technology Inc.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <log.h>
+#include <misc.h>
+#include <reset.h>
+#include <reset-uclass.h>
+#include <linux/err.h>
+#include <asm/io.h>
+#include <asm/arch/scu_ast2500.h>
+
+struct ast2500_reset_priv {
+ struct ast2500_scu *scu;
+};
+
+static int ast2500_reset_request(struct reset_ctl *reset_ctl)
+{
+ debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
+ reset_ctl->dev, reset_ctl->id);
+
+ return 0;
+}
+
+static int ast2500_reset_free(struct reset_ctl *reset_ctl)
+{
+ debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
+ reset_ctl->dev, reset_ctl->id);
+
+ return 0;
+}
+
+static int ast2500_reset_assert(struct reset_ctl *reset_ctl)
+{
+ struct ast2500_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+ struct ast2500_scu *scu = priv->scu;
+
+ debug("%s: reset_ctl->id: %lu\n", __func__, reset_ctl->id);
+
+ if (reset_ctl->id < 32)
+ setbits_le32(&scu->sysreset_ctrl1, BIT(reset_ctl->id));
+ else
+ setbits_le32(&scu->sysreset_ctrl2, BIT(reset_ctl->id - 32));
+
+ return 0;
+}
+
+static int ast2500_reset_deassert(struct reset_ctl *reset_ctl)
+{
+ struct ast2500_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+ struct ast2500_scu *scu = priv->scu;
+
+ debug("%s: reset_ctl->id: %lu\n", __func__, reset_ctl->id);
+
+ if (reset_ctl->id < 32)
+ clrbits_le32(&scu->sysreset_ctrl1, BIT(reset_ctl->id));
+ else
+ clrbits_le32(&scu->sysreset_ctrl2, BIT(reset_ctl->id - 32));
+
+ return 0;
+}
+
+static int ast2500_reset_probe(struct udevice *dev)
+{
+ int rc;
+ struct ast2500_reset_priv *priv = dev_get_priv(dev);
+ struct udevice *scu_dev;
+
+ /* get SCU base from clock device */
+ rc = uclass_get_device_by_driver(UCLASS_CLK,
+ DM_GET_DRIVER(aspeed_ast2500_scu), &scu_dev);
+ if (rc) {
+ debug("%s: clock device not found, rc=%d\n", __func__, rc);
+ return rc;
+ }
+
+ priv->scu = devfdt_get_addr_ptr(scu_dev);
+ if (IS_ERR_OR_NULL(priv->scu)) {
+ debug("%s: invalid SCU base pointer\n", __func__);
+ return PTR_ERR(priv->scu);
+ }
+
+ return 0;
+}
+
+static const struct udevice_id ast2500_reset_ids[] = {
+ { .compatible = "aspeed,ast2500-reset" },
+ { }
+};
+
+struct reset_ops ast2500_reset_ops = {
+ .request = ast2500_reset_request,
+ .rfree = ast2500_reset_free,
+ .rst_assert = ast2500_reset_assert,
+ .rst_deassert = ast2500_reset_deassert,
+};
+
+U_BOOT_DRIVER(ast2500_reset) = {
+ .name = "ast2500_reset",
+ .id = UCLASS_RESET,
+ .of_match = ast2500_reset_ids,
+ .probe = ast2500_reset_probe,
+ .ops = &ast2500_reset_ops,
+ .priv_auto_alloc_size = sizeof(struct ast2500_reset_priv),
+};
generated by cgit v1.2.3 (git 2.0.4) at 2025-10-12 17:13:11 +0000