4 files changed, 48 insertions, 2 deletions

diff --git a/drivers/spi/atmel_spi.c b/drivers/spi/atmel_spi.c
index 76491142318..4701b79f161 100644
--- a/drivers/spi/atmel_spi.c
+++ b/drivers/spi/atmel_spi.c
@@ -296,6 +296,9 @@ static void atmel_spi_cs_activate(struct udevice *dev)
 	struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
 	u32 cs = slave_plat->cs;
 
+	if (!dm_gpio_is_valid(&priv->cs_gpios[cs]))
+		return;
+
 	dm_gpio_set_value(&priv->cs_gpios[cs], 0);
 }
 
@@ -306,6 +309,9 @@ static void atmel_spi_cs_deactivate(struct udevice *dev)
 	struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
 	u32 cs = slave_plat->cs;
 
+	if (!dm_gpio_is_valid(&priv->cs_gpios[cs]))
+		return;
+
 	dm_gpio_set_value(&priv->cs_gpios[cs], 1);
 }
 
@@ -473,6 +479,9 @@ static int atmel_spi_probe(struct udevice *bus)
 	}
 
 	for(i = 0; i < ARRAY_SIZE(priv->cs_gpios); i++) {
+		if (!dm_gpio_is_valid(&priv->cs_gpios[i]))
+			continue;
+
 		dm_gpio_set_dir_flags(&priv->cs_gpios[i],
 				      GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
 	}
diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c
index 8a894501097..76d376ac445 100644
--- a/drivers/spi/omap3_spi.c
+++ b/drivers/spi/omap3_spi.c
@@ -692,6 +692,5 @@ U_BOOT_DRIVER(omap3_spi) = {
 	.probe = omap3_spi_probe,
 	.ops    = &omap3_spi_ops,
 	.priv_auto_alloc_size = sizeof(struct omap3_spi_priv),
-	.probe = omap3_spi_probe,
 };
 #endif
diff --git a/drivers/spi/stm32_qspi.c b/drivers/spi/stm32_qspi.c
index 05358ebf4cd..f0434a4413d 100644
--- a/drivers/spi/stm32_qspi.c
+++ b/drivers/spi/stm32_qspi.c
@@ -17,6 +17,7 @@
 #include <errno.h>
 #include <asm/arch/stm32.h>
 #include <asm/arch/stm32_defs.h>
+#include <clk.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -457,7 +458,20 @@ static int stm32_qspi_probe(struct udevice *bus)
 
 	priv->max_hz = plat->max_hz;
 
-	clock_setup(QSPI_CLOCK_CFG);
+#ifdef CONFIG_CLK
+	int ret;
+	struct clk clk;
+	ret = clk_get_by_index(bus, 0, &clk);
+	if (ret < 0)
+		return ret;
+
+	ret = clk_enable(&clk);
+
+	if (ret) {
+		dev_err(bus, "failed to enable clock\n");
+		return ret;
+	}
+#endif
 
 	setbits_le32(&priv->regs->cr, STM32_QSPI_CR_SSHIFT);
 
diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c
index 5a9b1f0f2ee..2b77f1ccdcf 100644
--- a/drivers/spi/zynq_spi.c
+++ b/drivers/spi/zynq_spi.c
@@ -56,6 +56,8 @@ struct zynq_spi_platdata {
 	struct zynq_spi_regs *regs;
 	u32 frequency;		/* input frequency */
 	u32 speed_hz;
+	uint deactivate_delay_us;	/* Delay to wait after deactivate */
+	uint activate_delay_us;		/* Delay to wait after activate */
 };
 
 /* zynq spi priv */
@@ -63,6 +65,7 @@ struct zynq_spi_priv {
 	struct zynq_spi_regs *regs;
 	u8 cs;
 	u8 mode;
+	ulong last_transaction_us;	/* Time of last transaction end */
 	u8 fifo_depth;
 	u32 freq;		/* required frequency */
 };
@@ -78,6 +81,10 @@ static int zynq_spi_ofdata_to_platdata(struct udevice *bus)
 	/* FIXME: Use 250MHz as a suitable default */
 	plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
 					250000000);
+	plat->deactivate_delay_us = fdtdec_get_int(blob, node,
+					"spi-deactivate-delay", 0);
+	plat->activate_delay_us = fdtdec_get_int(blob, node,
+						 "spi-activate-delay", 0);
 	plat->speed_hz = plat->frequency / 2;
 
 	debug("%s: regs=%p max-frequency=%d\n", __func__,
@@ -133,10 +140,19 @@ static int zynq_spi_probe(struct udevice *bus)
 static void spi_cs_activate(struct udevice *dev)
 {
 	struct udevice *bus = dev->parent;
+	struct zynq_spi_platdata *plat = bus->platdata;
 	struct zynq_spi_priv *priv = dev_get_priv(bus);
 	struct zynq_spi_regs *regs = priv->regs;
 	u32 cr;
 
+	/* If it's too soon to do another transaction, wait */
+	if (plat->deactivate_delay_us && priv->last_transaction_us) {
+		ulong delay_us;		/* The delay completed so far */
+		delay_us = timer_get_us() - priv->last_transaction_us;
+		if (delay_us < plat->deactivate_delay_us)
+			udelay(plat->deactivate_delay_us - delay_us);
+	}
+
 	clrbits_le32(&regs->cr, ZYNQ_SPI_CR_CS_MASK);
 	cr = readl(&regs->cr);
 	/*
@@ -147,15 +163,23 @@ static void spi_cs_activate(struct udevice *dev)
 	 */
 	cr |= (~(1 << priv->cs) << ZYNQ_SPI_CR_SS_SHIFT) & ZYNQ_SPI_CR_CS_MASK;
 	writel(cr, &regs->cr);
+
+	if (plat->activate_delay_us)
+		udelay(plat->activate_delay_us);
 }
 
 static void spi_cs_deactivate(struct udevice *dev)
 {
 	struct udevice *bus = dev->parent;
+	struct zynq_spi_platdata *plat = bus->platdata;
 	struct zynq_spi_priv *priv = dev_get_priv(bus);
 	struct zynq_spi_regs *regs = priv->regs;
 
 	setbits_le32(&regs->cr, ZYNQ_SPI_CR_CS_MASK);
+
+	/* Remember time of this transaction so we can honour the bus delay */
+	if (plat->deactivate_delay_us)
+		priv->last_transaction_us = timer_get_us();
 }
 
 static int zynq_spi_claim_bus(struct udevice *dev)