diff options
Diffstat (limited to 'drivers/spi')
| -rw-r--r-- | drivers/spi/Kconfig | 12 | ||||
| -rw-r--r-- | drivers/spi/atcspi200_spi.c | 2 | ||||
| -rw-r--r-- | drivers/spi/cadence_qspi.c | 39 | ||||
| -rw-r--r-- | drivers/spi/cf_spi.c | 482 | ||||
| -rw-r--r-- | drivers/spi/designware_spi.c | 8 | ||||
| -rw-r--r-- | drivers/spi/renesas_rpc_spi.c | 12 | ||||
| -rw-r--r-- | drivers/spi/rk_spi.c | 167 |
7 files changed, 473 insertions, 249 deletions
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index fb794adae72..7044da35d68 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -87,6 +87,12 @@ config CADENCE_QSPI used to access the SPI NOR flash on platforms embedding this Cadence IP core. +config CF_SPI + bool "ColdFire SPI driver" + help + Enable the ColdFire SPI driver. This driver can be used on + some m68k SoCs. + config DESIGNWARE_SPI bool "Designware SPI driver" help @@ -133,7 +139,7 @@ config MPC8XX_SPI config MT7621_SPI bool "MediaTek MT7621 SPI driver" - depends on ARCH_MT7620 + depends on SOC_MT7628 help Enable the MT7621 SPI driver. This driver can be used to access the SPI NOR flash on platforms embedding this Ralink / MediaTek @@ -173,7 +179,7 @@ config PL022_SPI config RENESAS_RPC_SPI bool "Renesas RPC SPI driver" - depends on RCAR_GEN3 + depends on RCAR_GEN3 || RZA1 imply SPI_FLASH_BAR help Enable the Renesas RPC SPI driver, used to access SPI NOR flash @@ -222,7 +228,7 @@ config SPI_SUNXI config STM32_QSPI bool "STM32F7 QSPI driver" - depends on STM32F7 || ARCH_STM32MP + depends on STM32F4 || STM32F7 || ARCH_STM32MP help Enable the STM32F7 Quad-SPI (QSPI) driver. This driver can be used to access the SPI NOR flash chips on platforms embedding diff --git a/drivers/spi/atcspi200_spi.c b/drivers/spi/atcspi200_spi.c index af96c6d21e5..e0cc3234440 100644 --- a/drivers/spi/atcspi200_spi.c +++ b/drivers/spi/atcspi200_spi.c @@ -6,8 +6,8 @@ * Author: Rick Chen (rick@andestech.com) */ -#include <clk.h> #include <common.h> +#include <clk.h> #include <malloc.h> #include <spi.h> #include <asm/io.h> diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index 41c87004d8c..e2e54cd2772 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -18,8 +18,6 @@ #define CQSPI_INDIRECT_READ 2 #define CQSPI_INDIRECT_WRITE 3 -DECLARE_GLOBAL_DATA_PTR; - static int cadence_spi_write_speed(struct udevice *bus, uint hz) { struct cadence_spi_platdata *plat = bus->platdata; @@ -295,36 +293,37 @@ static int cadence_spi_xfer(struct udevice *dev, unsigned int bitlen, static int cadence_spi_ofdata_to_platdata(struct udevice *bus) { struct cadence_spi_platdata *plat = bus->platdata; - const void *blob = gd->fdt_blob; - int node = dev_of_offset(bus); - int subnode; + ofnode subnode; plat->regbase = (void *)devfdt_get_addr_index(bus, 0); plat->ahbbase = (void *)devfdt_get_addr_index(bus, 1); - plat->is_decoded_cs = fdtdec_get_bool(blob, node, "cdns,is-decoded-cs"); - plat->fifo_depth = fdtdec_get_uint(blob, node, "cdns,fifo-depth", 128); - plat->fifo_width = fdtdec_get_uint(blob, node, "cdns,fifo-width", 4); - plat->trigger_address = fdtdec_get_uint(blob, node, - "cdns,trigger-address", 0); + plat->is_decoded_cs = dev_read_bool(bus, "cdns,is-decoded-cs"); + plat->fifo_depth = dev_read_u32_default(bus, "cdns,fifo-depth", 128); + plat->fifo_width = dev_read_u32_default(bus, "cdns,fifo-width", 4); + plat->trigger_address = dev_read_u32_default(bus, + "cdns,trigger-address", + 0); /* All other paramters are embedded in the child node */ - subnode = fdt_first_subnode(blob, node); - if (subnode < 0) { + subnode = dev_read_first_subnode(bus); + if (!ofnode_valid(subnode)) { printf("Error: subnode with SPI flash config missing!\n"); return -ENODEV; } /* Use 500 KHz as a suitable default */ - plat->max_hz = fdtdec_get_uint(blob, subnode, "spi-max-frequency", - 500000); + plat->max_hz = ofnode_read_u32_default(subnode, "spi-max-frequency", + 500000); /* Read other parameters from DT */ - plat->page_size = fdtdec_get_uint(blob, subnode, "page-size", 256); - plat->block_size = fdtdec_get_uint(blob, subnode, "block-size", 16); - plat->tshsl_ns = fdtdec_get_uint(blob, subnode, "cdns,tshsl-ns", 200); - plat->tsd2d_ns = fdtdec_get_uint(blob, subnode, "cdns,tsd2d-ns", 255); - plat->tchsh_ns = fdtdec_get_uint(blob, subnode, "cdns,tchsh-ns", 20); - plat->tslch_ns = fdtdec_get_uint(blob, subnode, "cdns,tslch-ns", 20); + plat->page_size = ofnode_read_u32_default(subnode, "page-size", 256); + plat->block_size = ofnode_read_u32_default(subnode, "block-size", 16); + plat->tshsl_ns = ofnode_read_u32_default(subnode, "cdns,tshsl-ns", + 200); + plat->tsd2d_ns = ofnode_read_u32_default(subnode, "cdns,tsd2d-ns", + 255); + plat->tchsh_ns = ofnode_read_u32_default(subnode, "cdns,tchsh-ns", 20); + plat->tslch_ns = ofnode_read_u32_default(subnode, "cdns,tslch-ns", 20); debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n", __func__, plat->regbase, plat->ahbbase, plat->max_hz, diff --git a/drivers/spi/cf_spi.c b/drivers/spi/cf_spi.c index 522631cbbf9..923ff6f3114 100644 --- a/drivers/spi/cf_spi.c +++ b/drivers/spi/cf_spi.c @@ -6,23 +6,28 @@ * * Copyright (C) 2004-2009 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * Support for DM and DT, non-DM code removed. + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> + * + * TODO: fsl_dspi.c should work as a driver for the DSPI module. */ #include <common.h> +#include <dm.h> +#include <dm/platform_data/spi_coldfire.h> #include <spi.h> #include <malloc.h> -#include <asm/immap.h> +#include <asm/coldfire/dspi.h> +#include <asm/io.h> -struct cf_spi_slave { - struct spi_slave slave; +struct coldfire_spi_priv { + struct dspi *regs; uint baudrate; + int mode; int charbit; }; -extern void cfspi_port_conf(void); -extern int cfspi_claim_bus(uint bus, uint cs); -extern void cfspi_release_bus(uint bus, uint cs); - DECLARE_GLOBAL_DATA_PTR; #ifndef CONFIG_SPI_IDLE_VAL @@ -33,163 +38,193 @@ DECLARE_GLOBAL_DATA_PTR; #endif #endif -#if defined(CONFIG_CF_DSPI) -/* DSPI specific mode */ -#define SPI_MODE_MOD 0x00200000 -#define SPI_DBLRATE 0x00100000 - -static inline struct cf_spi_slave *to_cf_spi_slave(struct spi_slave *slave) +/* + * DSPI specific mode + * + * bit 31 - 28: Transfer size 3 to 16 bits + * 27 - 26: PCS to SCK delay prescaler + * 25 - 24: After SCK delay prescaler + * 23 - 22: Delay after transfer prescaler + * 21 : Allow overwrite for bit 31-22 and bit 20-8 + * 20 : Double baud rate + * 19 - 16: PCS to SCK delay scaler + * 15 - 12: After SCK delay scaler + * 11 - 8: Delay after transfer scaler + * 7 - 0: SPI_CPHA, SPI_CPOL, SPI_LSB_FIRST + */ +#define SPI_MODE_MOD 0x00200000 +#define SPI_MODE_DBLRATE 0x00100000 + +#define SPI_MODE_XFER_SZ_MASK 0xf0000000 +#define SPI_MODE_DLY_PRE_MASK 0x0fc00000 +#define SPI_MODE_DLY_SCA_MASK 0x000fff00 + +#define MCF_FRM_SZ_16BIT DSPI_CTAR_TRSZ(0xf) +#define MCF_DSPI_SPEED_BESTMATCH 0x7FFFFFFF +#define MCF_DSPI_MAX_CTAR_REGS 8 + +/* Default values */ +#define MCF_DSPI_DEFAULT_SCK_FREQ 10000000 +#define MCF_DSPI_DEFAULT_MAX_CS 4 +#define MCF_DSPI_DEFAULT_MODE 0 + +#define MCF_DSPI_DEFAULT_CTAR (DSPI_CTAR_TRSZ(7) | \ + DSPI_CTAR_PCSSCK_1CLK | \ + DSPI_CTAR_PASC(0) | \ + DSPI_CTAR_PDT(0) | \ + DSPI_CTAR_CSSCK(0) | \ + DSPI_CTAR_ASC(0) | \ + DSPI_CTAR_DT(1) | \ + DSPI_CTAR_BR(6)) + +#define MCF_CTAR_MODE_MASK (MCF_FRM_SZ_16BIT | \ + DSPI_CTAR_PCSSCK(3) | \ + DSPI_CTAR_PASC_7CLK | \ + DSPI_CTAR_PDT(3) | \ + DSPI_CTAR_CSSCK(0x0f) | \ + DSPI_CTAR_ASC(0x0f) | \ + DSPI_CTAR_DT(0x0f)) + +#define setup_ctrl(ctrl, cs) ((ctrl & 0xFF000000) | ((1 << cs) << 16)) + +static inline void cfspi_tx(struct coldfire_spi_priv *cfspi, + u32 ctrl, u16 data) { - return container_of(slave, struct cf_spi_slave, slave); + /* + * Need to check fifo level here + */ + while ((readl(&cfspi->regs->sr) & 0x0000F000) >= 0x4000) + ; + + writel(ctrl | data, &cfspi->regs->tfr); } -static void cfspi_init(void) +static inline u16 cfspi_rx(struct coldfire_spi_priv *cfspi) { - volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; - cfspi_port_conf(); /* port configuration */ - - dspi->mcr = DSPI_MCR_MSTR | DSPI_MCR_CSIS7 | DSPI_MCR_CSIS6 | - DSPI_MCR_CSIS5 | DSPI_MCR_CSIS4 | DSPI_MCR_CSIS3 | - DSPI_MCR_CSIS2 | DSPI_MCR_CSIS1 | DSPI_MCR_CSIS0 | - DSPI_MCR_CRXF | DSPI_MCR_CTXF; + while ((readl(&cfspi->regs->sr) & 0x000000F0) == 0) + ; - /* Default setting in platform configuration */ -#ifdef CONFIG_SYS_DSPI_CTAR0 - dspi->ctar[0] = CONFIG_SYS_DSPI_CTAR0; -#endif -#ifdef CONFIG_SYS_DSPI_CTAR1 - dspi->ctar[1] = CONFIG_SYS_DSPI_CTAR1; -#endif -#ifdef CONFIG_SYS_DSPI_CTAR2 - dspi->ctar[2] = CONFIG_SYS_DSPI_CTAR2; -#endif -#ifdef CONFIG_SYS_DSPI_CTAR3 - dspi->ctar[3] = CONFIG_SYS_DSPI_CTAR3; -#endif -#ifdef CONFIG_SYS_DSPI_CTAR4 - dspi->ctar[4] = CONFIG_SYS_DSPI_CTAR4; -#endif -#ifdef CONFIG_SYS_DSPI_CTAR5 - dspi->ctar[5] = CONFIG_SYS_DSPI_CTAR5; -#endif -#ifdef CONFIG_SYS_DSPI_CTAR6 - dspi->ctar[6] = CONFIG_SYS_DSPI_CTAR6; -#endif -#ifdef CONFIG_SYS_DSPI_CTAR7 - dspi->ctar[7] = CONFIG_SYS_DSPI_CTAR7; -#endif + return readw(&cfspi->regs->rfr); } -static void cfspi_tx(u32 ctrl, u16 data) +static int coldfire_spi_claim_bus(struct udevice *dev) { - volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; + struct udevice *bus = dev->parent; + struct coldfire_spi_priv *cfspi = dev_get_priv(bus); + struct dspi *dspi = cfspi->regs; + struct dm_spi_slave_platdata *slave_plat = + dev_get_parent_platdata(dev); - while ((dspi->sr & 0x0000F000) >= 4) ; + if ((in_be32(&dspi->sr) & DSPI_SR_TXRXS) != DSPI_SR_TXRXS) + return -1; - dspi->tfr = (ctrl | data); + /* Clear FIFO and resume transfer */ + clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF); + + dspi_chip_select(slave_plat->cs); + + return 0; } -static u16 cfspi_rx(void) +static int coldfire_spi_release_bus(struct udevice *dev) { - volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; + struct udevice *bus = dev->parent; + struct coldfire_spi_priv *cfspi = dev_get_priv(bus); + struct dspi *dspi = cfspi->regs; + struct dm_spi_slave_platdata *slave_plat = + dev_get_parent_platdata(dev); - while ((dspi->sr & 0x000000F0) == 0) ; + /* Clear FIFO */ + clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF); - return (dspi->rfr & 0xFFFF); + dspi_chip_unselect(slave_plat->cs); + + return 0; } -static int cfspi_xfer(struct spi_slave *slave, uint bitlen, const void *dout, - void *din, ulong flags) +static int coldfire_spi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, + unsigned long flags) { - struct cf_spi_slave *cfslave = to_cf_spi_slave(slave); + struct udevice *bus = dev_get_parent(dev); + struct coldfire_spi_priv *cfspi = dev_get_priv(bus); + struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); u16 *spi_rd16 = NULL, *spi_wr16 = NULL; u8 *spi_rd = NULL, *spi_wr = NULL; - static u32 ctrl = 0; + static u32 ctrl; uint len = bitlen >> 3; - if (cfslave->charbit == 16) { + if (cfspi->charbit == 16) { bitlen >>= 1; - spi_wr16 = (u16 *) dout; - spi_rd16 = (u16 *) din; + spi_wr16 = (u16 *)dout; + spi_rd16 = (u16 *)din; } else { - spi_wr = (u8 *) dout; - spi_rd = (u8 *) din; + spi_wr = (u8 *)dout; + spi_rd = (u8 *)din; } if ((flags & SPI_XFER_BEGIN) == SPI_XFER_BEGIN) ctrl |= DSPI_TFR_CONT; - ctrl = (ctrl & 0xFF000000) | ((1 << slave->cs) << 16); + ctrl = setup_ctrl(ctrl, slave_plat->cs); if (len > 1) { int tmp_len = len - 1; + while (tmp_len--) { - if (dout != NULL) { - if (cfslave->charbit == 16) - cfspi_tx(ctrl, *spi_wr16++); + if (dout) { + if (cfspi->charbit == 16) + cfspi_tx(cfspi, ctrl, *spi_wr16++); else - cfspi_tx(ctrl, *spi_wr++); - cfspi_rx(); + cfspi_tx(cfspi, ctrl, *spi_wr++); + cfspi_rx(cfspi); } - if (din != NULL) { - cfspi_tx(ctrl, CONFIG_SPI_IDLE_VAL); - if (cfslave->charbit == 16) - *spi_rd16++ = cfspi_rx(); + if (din) { + cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL); + if (cfspi->charbit == 16) + *spi_rd16++ = cfspi_rx(cfspi); else - *spi_rd++ = cfspi_rx(); + *spi_rd++ = cfspi_rx(cfspi); } } len = 1; /* remaining byte */ } - if ((flags & SPI_XFER_END) == SPI_XFER_END) + if (flags & SPI_XFER_END) ctrl &= ~DSPI_TFR_CONT; if (len) { - if (dout != NULL) { - if (cfslave->charbit == 16) - cfspi_tx(ctrl, *spi_wr16); + if (dout) { + if (cfspi->charbit == 16) + cfspi_tx(cfspi, ctrl, *spi_wr16); else - cfspi_tx(ctrl, *spi_wr); - cfspi_rx(); + cfspi_tx(cfspi, ctrl, *spi_wr); + cfspi_rx(cfspi); } - if (din != NULL) { - cfspi_tx(ctrl, CONFIG_SPI_IDLE_VAL); - if (cfslave->charbit == 16) - *spi_rd16 = cfspi_rx(); + if (din) { + cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL); + if (cfspi->charbit == 16) + *spi_rd16 = cfspi_rx(cfspi); else - *spi_rd = cfspi_rx(); + *spi_rd = cfspi_rx(cfspi); } } else { /* dummy read */ - cfspi_tx(ctrl, CONFIG_SPI_IDLE_VAL); - cfspi_rx(); + cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL); + cfspi_rx(cfspi); } return 0; } -static struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave, - uint mode) +static int coldfire_spi_set_speed(struct udevice *bus, uint max_hz) { - /* - * bit definition for mode: - * bit 31 - 28: Transfer size 3 to 16 bits - * 27 - 26: PCS to SCK delay prescaler - * 25 - 24: After SCK delay prescaler - * 23 - 22: Delay after transfer prescaler - * 21 : Allow overwrite for bit 31-22 and bit 20-8 - * 20 : Double baud rate - * 19 - 16: PCS to SCK delay scaler - * 15 - 12: After SCK delay scaler - * 11 - 8: Delay after transfer scaler - * 7 - 0: SPI_CPHA, SPI_CPOL, SPI_LSB_FIRST - */ - volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; + struct coldfire_spi_priv *cfspi = dev_get_priv(bus); + struct dspi *dspi = cfspi->regs; int prescaler[] = { 2, 3, 5, 7 }; int scaler[] = { 2, 4, 6, 8, @@ -198,57 +233,41 @@ static struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave, 4096, 8192, 16384, 32768 }; int i, j, pbrcnt, brcnt, diff, tmp, dbr = 0; - int best_i, best_j, bestmatch = 0x7FFFFFFF, baud_speed; - u32 bus_setup = 0; + int best_i, best_j, bestmatch = MCF_DSPI_SPEED_BESTMATCH, baud_speed; + u32 bus_setup; + + cfspi->baudrate = max_hz; + + /* Read current setup */ + bus_setup = readl(&dspi->ctar[bus->seq]); tmp = (prescaler[3] * scaler[15]); /* Maximum and minimum baudrate it can handle */ - if ((cfslave->baudrate > (gd->bus_clk >> 1)) || - (cfslave->baudrate < (gd->bus_clk / tmp))) { + if ((cfspi->baudrate > (gd->bus_clk >> 1)) || + (cfspi->baudrate < (gd->bus_clk / tmp))) { printf("Exceed baudrate limitation: Max %d - Min %d\n", (int)(gd->bus_clk >> 1), (int)(gd->bus_clk / tmp)); - return NULL; + return -1; } /* Activate Double Baud when it exceed 1/4 the bus clk */ - if ((CONFIG_SYS_DSPI_CTAR0 & DSPI_CTAR_DBR) || - (cfslave->baudrate > (gd->bus_clk / (prescaler[0] * scaler[0])))) { + if ((bus_setup & DSPI_CTAR_DBR) || + (cfspi->baudrate > (gd->bus_clk / (prescaler[0] * scaler[0])))) { bus_setup |= DSPI_CTAR_DBR; dbr = 1; } - if (mode & SPI_CPOL) - bus_setup |= DSPI_CTAR_CPOL; - if (mode & SPI_CPHA) - bus_setup |= DSPI_CTAR_CPHA; - if (mode & SPI_LSB_FIRST) - bus_setup |= DSPI_CTAR_LSBFE; - /* Overwrite default value set in platform configuration file */ - if (mode & SPI_MODE_MOD) { - - if ((mode & 0xF0000000) == 0) - bus_setup |= - dspi->ctar[cfslave->slave.bus] & 0x78000000; - else - bus_setup |= ((mode & 0xF0000000) >> 1); - + if (cfspi->mode & SPI_MODE_MOD) { /* * Check to see if it is enabled by default in platform * config, or manual setting passed by mode parameter */ - if (mode & SPI_DBLRATE) { + if (cfspi->mode & SPI_MODE_DBLRATE) { bus_setup |= DSPI_CTAR_DBR; dbr = 1; } - bus_setup |= (mode & 0x0FC00000) >> 4; /* PSCSCK, PASC, PDT */ - bus_setup |= (mode & 0x000FFF00) >> 4; /* CSSCK, ASC, DT */ - } else - bus_setup |= (dspi->ctar[cfslave->slave.bus] & 0x78FCFFF0); - - cfslave->charbit = - ((dspi->ctar[cfslave->slave.bus] & 0x78000000) == - 0x78000000) ? 16 : 8; + } pbrcnt = sizeof(prescaler) / sizeof(int); brcnt = sizeof(scaler) / sizeof(int); @@ -259,10 +278,10 @@ static struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave, for (j = 0; j < brcnt; j++) { tmp = (baud_speed / scaler[j]) * (1 + dbr); - if (tmp > cfslave->baudrate) - diff = tmp - cfslave->baudrate; + if (tmp > cfspi->baudrate) + diff = tmp - cfspi->baudrate; else - diff = cfslave->baudrate - tmp; + diff = cfspi->baudrate - tmp; if (diff < bestmatch) { bestmatch = diff; @@ -271,65 +290,174 @@ static struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave, } } } + + bus_setup &= ~(DSPI_CTAR_PBR(0x03) | DSPI_CTAR_BR(0x0f)); bus_setup |= (DSPI_CTAR_PBR(best_i) | DSPI_CTAR_BR(best_j)); - dspi->ctar[cfslave->slave.bus] = bus_setup; + writel(bus_setup, &dspi->ctar[bus->seq]); - return &cfslave->slave; + return 0; } -#endif /* CONFIG_CF_DSPI */ -#ifdef CONFIG_CMD_SPI -int spi_cs_is_valid(unsigned int bus, unsigned int cs) +static int coldfire_spi_set_mode(struct udevice *bus, uint mode) { - if (((cs >= 0) && (cs < 8)) && ((bus >= 0) && (bus < 8))) - return 1; - else - return 0; -} + struct coldfire_spi_priv *cfspi = dev_get_priv(bus); + struct dspi *dspi = cfspi->regs; + u32 bus_setup = 0; -void spi_init(void) -{ - cfspi_init(); -} + cfspi->mode = mode; -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode) -{ - struct cf_spi_slave *cfslave; + if (cfspi->mode & SPI_CPOL) + bus_setup |= DSPI_CTAR_CPOL; + if (cfspi->mode & SPI_CPHA) + bus_setup |= DSPI_CTAR_CPHA; + if (cfspi->mode & SPI_LSB_FIRST) + bus_setup |= DSPI_CTAR_LSBFE; - if (!spi_cs_is_valid(bus, cs)) - return NULL; + /* Overwrite default value set in platform configuration file */ + if (cfspi->mode & SPI_MODE_MOD) { + if ((cfspi->mode & SPI_MODE_XFER_SZ_MASK) == 0) + bus_setup |= + readl(&dspi->ctar[bus->seq]) & MCF_FRM_SZ_16BIT; + else + bus_setup |= + ((cfspi->mode & SPI_MODE_XFER_SZ_MASK) >> 1); - cfslave = spi_alloc_slave(struct cf_spi_slave, bus, cs); - if (!cfslave) - return NULL; + /* PSCSCK, PASC, PDT */ + bus_setup |= (cfspi->mode & SPI_MODE_DLY_PRE_MASK) >> 4; + /* CSSCK, ASC, DT */ + bus_setup |= (cfspi->mode & SPI_MODE_DLY_SCA_MASK) >> 4; + } else { + bus_setup |= + (readl(&dspi->ctar[bus->seq]) & MCF_CTAR_MODE_MASK); + } + + cfspi->charbit = + ((readl(&dspi->ctar[bus->seq]) & MCF_FRM_SZ_16BIT) == + MCF_FRM_SZ_16BIT) ? 16 : 8; - cfslave->baudrate = max_hz; + setbits_be32(&dspi->ctar[bus->seq], bus_setup); - /* specific setup */ - return cfspi_setup_slave(cfslave, mode); + return 0; } -void spi_free_slave(struct spi_slave *slave) +static int coldfire_spi_probe(struct udevice *bus) { - struct cf_spi_slave *cfslave = to_cf_spi_slave(slave); + struct coldfire_spi_platdata *plat = dev_get_platdata(bus); + struct coldfire_spi_priv *cfspi = dev_get_priv(bus); + struct dspi *dspi = cfspi->regs; + int i; - free(cfslave); -} + cfspi->regs = (struct dspi *)plat->regs_addr; -int spi_claim_bus(struct spi_slave *slave) -{ - return cfspi_claim_bus(slave->bus, slave->cs); + cfspi->baudrate = plat->speed_hz; + cfspi->mode = plat->mode; + + for (i = 0; i < MCF_DSPI_MAX_CTAR_REGS; i++) { + unsigned int ctar = 0; + + if (plat->ctar[i][0] == 0) + break; + + ctar = DSPI_CTAR_TRSZ(plat->ctar[i][0]) | + DSPI_CTAR_PCSSCK(plat->ctar[i][1]) | + DSPI_CTAR_PASC(plat->ctar[i][2]) | + DSPI_CTAR_PDT(plat->ctar[i][3]) | + DSPI_CTAR_CSSCK(plat->ctar[i][4]) | + DSPI_CTAR_ASC(plat->ctar[i][5]) | + DSPI_CTAR_DT(plat->ctar[i][6]) | + DSPI_CTAR_BR(plat->ctar[i][7]); + + writel(ctar, &cfspi->regs->ctar[i]); + } + + /* Default CTARs */ + for (i = 0; i < MCF_DSPI_MAX_CTAR_REGS; i++) + writel(MCF_DSPI_DEFAULT_CTAR, &dspi->ctar[i]); + + dspi->mcr = DSPI_MCR_MSTR | DSPI_MCR_CSIS7 | DSPI_MCR_CSIS6 | + DSPI_MCR_CSIS5 | DSPI_MCR_CSIS4 | DSPI_MCR_CSIS3 | + DSPI_MCR_CSIS2 | DSPI_MCR_CSIS1 | DSPI_MCR_CSIS0 | + DSPI_MCR_CRXF | DSPI_MCR_CTXF; + + return 0; } -void spi_release_bus(struct spi_slave *slave) +void spi_init(void) { - cfspi_release_bus(slave->bus, slave->cs); } -int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, - void *din, unsigned long flags) +#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +static int coldfire_dspi_ofdata_to_platdata(struct udevice *bus) { - return cfspi_xfer(slave, bitlen, dout, din, flags); + fdt_addr_t addr; + struct coldfire_spi_platdata *plat = bus->platdata; + const void *blob = gd->fdt_blob; + int node = dev_of_offset(bus); + int *ctar, len; + + addr = devfdt_get_addr(bus); + if (addr == FDT_ADDR_T_NONE) + return -ENOMEM; + + plat->regs_addr = addr; + + plat->num_cs = fdtdec_get_int(blob, node, "num-cs", + MCF_DSPI_DEFAULT_MAX_CS); + + plat->speed_hz = fdtdec_get_int(blob, node, "spi-max-frequency", + MCF_DSPI_DEFAULT_SCK_FREQ); + + plat->mode = fdtdec_get_int(blob, node, "spi-mode", + MCF_DSPI_DEFAULT_MODE); + + memset(plat->ctar, 0, sizeof(plat->ctar)); + + ctar = (int *)fdt_getprop(blob, node, "ctar-params", &len); + + if (ctar && len) { + int i, q, ctar_regs; + + ctar_regs = len / sizeof(unsigned int) / MAX_CTAR_FIELDS; + + if (ctar_regs > MAX_CTAR_REGS) + ctar_regs = MAX_CTAR_REGS; + + for (i = 0; i < ctar_regs; i++) { + for (q = 0; q < MAX_CTAR_FIELDS; q++) + plat->ctar[i][q] = *ctar++; + } + } + + debug("DSPI: regs=%pa, max-frequency=%d, num-cs=%d, mode=%d\n", + (void *)plat->regs_addr, + plat->speed_hz, plat->num_cs, plat->mode); + + return 0; } -#endif /* CONFIG_CMD_SPI */ + +static const struct udevice_id coldfire_spi_ids[] = { + { .compatible = "fsl,mcf-dspi" }, + { } +}; +#endif + +static const struct dm_spi_ops coldfire_spi_ops = { + .claim_bus = coldfire_spi_claim_bus, + .release_bus = coldfire_spi_release_bus, + .xfer = coldfire_spi_xfer, + .set_speed = coldfire_spi_set_speed, + .set_mode = coldfire_spi_set_mode, +}; + +U_BOOT_DRIVER(coldfire_spi) = { + .name = "spi_coldfire", + .id = UCLASS_SPI, +#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) + .of_match = coldfire_spi_ids, + .ofdata_to_platdata = coldfire_dspi_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct coldfire_spi_platdata), +#endif + .probe = coldfire_spi_probe, + .ops = &coldfire_spi_ops, + .priv_auto_alloc_size = sizeof(struct coldfire_spi_priv), +}; diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c index dadb6fa18b0..7d58cfae55e 100644 --- a/drivers/spi/designware_spi.c +++ b/drivers/spi/designware_spi.c @@ -22,8 +22,6 @@ #include <linux/iopoll.h> #include <asm/io.h> -DECLARE_GLOBAL_DATA_PTR; - /* Register offsets */ #define DW_SPI_CTRL0 0x00 #define DW_SPI_CTRL1 0x04 @@ -155,14 +153,12 @@ static int request_gpio_cs(struct udevice *bus) static int dw_spi_ofdata_to_platdata(struct udevice *bus) { struct dw_spi_platdata *plat = bus->platdata; - const void *blob = gd->fdt_blob; - int node = dev_of_offset(bus); plat->regs = (struct dw_spi *)devfdt_get_addr(bus); /* Use 500KHz as a suitable default */ - plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency", - 500000); + plat->frequency = dev_read_u32_default(bus, "spi-max-frequency", + 500000); debug("%s: regs=%p max-frequency=%d\n", __func__, plat->regs, plat->frequency); diff --git a/drivers/spi/renesas_rpc_spi.c b/drivers/spi/renesas_rpc_spi.c index bec9095ff4b..bb2e7748fe4 100644 --- a/drivers/spi/renesas_rpc_spi.c +++ b/drivers/spi/renesas_rpc_spi.c @@ -409,27 +409,30 @@ static int rpc_spi_probe(struct udevice *dev) priv->regs = plat->regs; priv->extr = plat->extr; - +#if CONFIG_IS_ENABLED(CLK) clk_enable(&priv->clk); - +#endif return 0; } static int rpc_spi_ofdata_to_platdata(struct udevice *bus) { struct rpc_spi_platdata *plat = dev_get_platdata(bus); - struct rpc_spi_priv *priv = dev_get_priv(bus); - int ret; plat->regs = dev_read_addr_index(bus, 0); plat->extr = dev_read_addr_index(bus, 1); +#if CONFIG_IS_ENABLED(CLK) + struct rpc_spi_priv *priv = dev_get_priv(bus); + int ret; + ret = clk_get_by_index(bus, 0, &priv->clk); if (ret < 0) { printf("%s: Could not get clock for %s: %d\n", __func__, bus->name, ret); return ret; } +#endif plat->freq = dev_read_u32_default(bus, "spi-max-freq", 50000000); @@ -448,6 +451,7 @@ static const struct udevice_id rpc_spi_ids[] = { { .compatible = "renesas,rpc-r8a77965" }, { .compatible = "renesas,rpc-r8a77970" }, { .compatible = "renesas,rpc-r8a77995" }, + { .compatible = "renesas,rpc-r7s72100" }, { } }; diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c index 14437c0a9af..a68553b75bf 100644 --- a/drivers/spi/rk_spi.c +++ b/drivers/spi/rk_spi.c @@ -2,6 +2,8 @@ /* * spi driver for rockchip * + * (C) 2019 Theobroma Systems Design und Consulting GmbH + * * (C) Copyright 2015 Google, Inc * * (C) Copyright 2008-2013 Rockchip Electronics @@ -16,14 +18,19 @@ #include <spi.h> #include <linux/errno.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/periph.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/periph.h> #include <dm/pinctrl.h> #include "rk_spi.h" /* Change to 1 to output registers at the start of each transaction */ #define DEBUG_RK_SPI 0 +struct rockchip_spi_params { + /* RXFIFO overruns and TXFIFO underruns stop the master clock */ + bool master_manages_fifo; +}; + struct rockchip_spi_platdata { #if CONFIG_IS_ENABLED(OF_PLATDATA) struct dtd_rockchip_rk3288_spi of_plat; @@ -40,11 +47,8 @@ struct rockchip_spi_priv { unsigned int max_freq; unsigned int mode; ulong last_transaction_us; /* Time of last transaction end */ - u8 bits_per_word; /* max 16 bits per word */ - u8 n_bytes; unsigned int speed_hz; unsigned int last_speed_hz; - unsigned int tmode; uint input_rate; }; @@ -130,8 +134,13 @@ static void spi_cs_activate(struct udevice *dev, uint cs) if (plat->deactivate_delay_us && priv->last_transaction_us) { ulong delay_us; /* The delay completed so far */ delay_us = timer_get_us() - priv->last_transaction_us; - if (delay_us < plat->deactivate_delay_us) - udelay(plat->deactivate_delay_us - delay_us); + if (delay_us < plat->deactivate_delay_us) { + ulong additional_delay_us = + plat->deactivate_delay_us - delay_us; + debug("%s: delaying by %ld us\n", + __func__, additional_delay_us); + udelay(additional_delay_us); + } } debug("activate cs%u\n", cs); @@ -263,8 +272,6 @@ static int rockchip_spi_probe(struct udevice *bus) } priv->input_rate = ret; debug("%s: rate = %u\n", __func__, priv->input_rate); - priv->bits_per_word = 8; - priv->tmode = TMOD_TR; /* Tx & Rx */ return 0; } @@ -274,28 +281,10 @@ static int rockchip_spi_claim_bus(struct udevice *dev) struct udevice *bus = dev->parent; struct rockchip_spi_priv *priv = dev_get_priv(bus); struct rockchip_spi *regs = priv->regs; - u8 spi_dfs, spi_tf; uint ctrlr0; /* Disable the SPI hardware */ - rkspi_enable_chip(regs, 0); - - switch (priv->bits_per_word) { - case 8: - priv->n_bytes = 1; - spi_dfs = DFS_8BIT; - spi_tf = HALF_WORD_OFF; - break; - case 16: - priv->n_bytes = 2; - spi_dfs = DFS_16BIT; - spi_tf = HALF_WORD_ON; - break; - default: - debug("%s: unsupported bits: %dbits\n", __func__, - priv->bits_per_word); - return -EPROTONOSUPPORT; - } + rkspi_enable_chip(regs, false); if (priv->speed_hz != priv->last_speed_hz) rkspi_set_clk(priv, priv->speed_hz); @@ -304,7 +293,7 @@ static int rockchip_spi_claim_bus(struct udevice *dev) ctrlr0 = OMOD_MASTER << OMOD_SHIFT; /* Data Frame Size */ - ctrlr0 |= spi_dfs << DFS_SHIFT; + ctrlr0 |= DFS_8BIT << DFS_SHIFT; /* set SPI mode 0..3 */ if (priv->mode & SPI_CPOL) @@ -325,7 +314,7 @@ static int rockchip_spi_claim_bus(struct udevice *dev) ctrlr0 |= FBM_MSB << FBM_SHIFT; /* Byte and Halfword Transform */ - ctrlr0 |= spi_tf << HALF_WORD_TX_SHIFT; + ctrlr0 |= HALF_WORD_OFF << HALF_WORD_TX_SHIFT; /* Rxd Sample Delay */ ctrlr0 |= 0 << RXDSD_SHIFT; @@ -334,7 +323,7 @@ static int rockchip_spi_claim_bus(struct udevice *dev) ctrlr0 |= FRF_SPI << FRF_SHIFT; /* Tx and Rx mode */ - ctrlr0 |= (priv->tmode & TMOD_MASK) << TMOD_SHIFT; + ctrlr0 |= TMOD_TR << TMOD_SHIFT; writel(ctrlr0, ®s->ctrlr0); @@ -351,6 +340,83 @@ static int rockchip_spi_release_bus(struct udevice *dev) return 0; } +static inline int rockchip_spi_16bit_reader(struct udevice *dev, + u8 **din, int *len) +{ + struct udevice *bus = dev->parent; + const struct rockchip_spi_params * const data = + (void *)dev_get_driver_data(bus); + struct rockchip_spi_priv *priv = dev_get_priv(bus); + struct rockchip_spi *regs = priv->regs; + const u32 saved_ctrlr0 = readl(®s->ctrlr0); +#if defined(DEBUG) + u32 statistics_rxlevels[33] = { }; +#endif + u32 frames = *len / 2; + u8 *in = (u8 *)(*din); + u32 max_chunk_size = SPI_FIFO_DEPTH; + + if (!frames) + return 0; + + /* + * If we know that the hardware will manage RXFIFO overruns + * (i.e. stop the SPI clock until there's space in the FIFO), + * we the allow largest possible chunk size that can be + * represented in CTRLR1. + */ + if (data && data->master_manages_fifo) + max_chunk_size = 0x10000; + + // rockchip_spi_configure(dev, mode, size) + rkspi_enable_chip(regs, false); + clrsetbits_le32(®s->ctrlr0, + TMOD_MASK << TMOD_SHIFT, + TMOD_RO << TMOD_SHIFT); + /* 16bit data frame size */ + clrsetbits_le32(®s->ctrlr0, DFS_MASK, DFS_16BIT); + + /* Update caller's context */ + const u32 bytes_to_process = 2 * frames; + *din += bytes_to_process; + *len -= bytes_to_process; + + /* Process our frames */ + while (frames) { + u32 chunk_size = min(frames, max_chunk_size); + + frames -= chunk_size; + + writew(chunk_size - 1, ®s->ctrlr1); + rkspi_enable_chip(regs, true); + + do { + u32 rx_level = readw(®s->rxflr); +#if defined(DEBUG) + statistics_rxlevels[rx_level]++; +#endif + chunk_size -= rx_level; + while (rx_level--) { + u16 val = readw(regs->rxdr); + *in++ = val & 0xff; + *in++ = val >> 8; + } + } while (chunk_size); + + rkspi_enable_chip(regs, false); + } + +#if defined(DEBUG) + debug("%s: observed rx_level during processing:\n", __func__); + for (int i = 0; i <= 32; ++i) + if (statistics_rxlevels[i]) + debug("\t%2d: %d\n", i, statistics_rxlevels[i]); +#endif + /* Restore the original transfer setup and return error-free. */ + writel(saved_ctrlr0, ®s->ctrlr0); + return 0; +} + static int rockchip_spi_xfer(struct udevice *dev, unsigned int bitlen, const void *dout, void *din, unsigned long flags) { @@ -362,7 +428,7 @@ static int rockchip_spi_xfer(struct udevice *dev, unsigned int bitlen, const u8 *out = dout; u8 *in = din; int toread, towrite; - int ret; + int ret = 0; debug("%s: dout=%p, din=%p, len=%x, flags=%lx\n", __func__, dout, din, len, flags); @@ -373,8 +439,18 @@ static int rockchip_spi_xfer(struct udevice *dev, unsigned int bitlen, if (flags & SPI_XFER_BEGIN) spi_cs_activate(dev, slave_plat->cs); + /* + * To ensure fast loading of firmware images (e.g. full U-Boot + * stage, ATF, Linux kernel) from SPI flash, we optimise the + * case of read-only transfers by using the full 16bits of each + * FIFO element. + */ + if (!out) + ret = rockchip_spi_16bit_reader(dev, &in, &len); + + /* This is the original 8bit reader/writer code */ while (len > 0) { - int todo = min(len, 0xffff); + int todo = min(len, 0x10000); rkspi_enable_chip(regs, false); writel(todo - 1, ®s->ctrlr1); @@ -397,9 +473,18 @@ static int rockchip_spi_xfer(struct udevice *dev, unsigned int bitlen, toread--; } } - ret = rkspi_wait_till_not_busy(regs); - if (ret) - break; + + /* + * In case that there's a transmit-component, we need to wait + * until the control goes idle before we can disable the SPI + * control logic (as this will implictly flush the FIFOs). + */ + if (out) { + ret = rkspi_wait_till_not_busy(regs); + if (ret) + break; + } + len -= todo; } @@ -446,10 +531,16 @@ static const struct dm_spi_ops rockchip_spi_ops = { */ }; +const struct rockchip_spi_params rk3399_spi_params = { + .master_manages_fifo = true, +}; + static const struct udevice_id rockchip_spi_ids[] = { { .compatible = "rockchip,rk3288-spi" }, - { .compatible = "rockchip,rk3368-spi" }, - { .compatible = "rockchip,rk3399-spi" }, + { .compatible = "rockchip,rk3368-spi", + .data = (ulong)&rk3399_spi_params }, + { .compatible = "rockchip,rk3399-spi", + .data = (ulong)&rk3399_spi_params }, { } }; |