diff options
Diffstat (limited to 'drivers/usb/host/dwc2.h')
| -rw-r--r-- | drivers/usb/host/dwc2.h | 638 |
1 files changed, 288 insertions, 350 deletions
diff --git a/drivers/usb/host/dwc2.h b/drivers/usb/host/dwc2.h index 6bd98b481f2..a01edc5eff3 100644 --- a/drivers/usb/host/dwc2.h +++ b/drivers/usb/host/dwc2.h @@ -8,356 +8,294 @@ #include <linux/bitops.h> -#define DWC2_GOTGCTL_SESREQSCS BIT(0) -#define DWC2_GOTGCTL_SESREQ BIT(1) -#define DWC2_GOTGCTL_HSTNEGSCS BIT(8) -#define DWC2_GOTGCTL_HNPREQ BIT(9) -#define DWC2_GOTGCTL_HSTSETHNPEN BIT(10) -#define DWC2_GOTGCTL_DEVHNPEN BIT(11) -#define DWC2_GOTGCTL_CONIDSTS BIT(16) -#define DWC2_GOTGCTL_DBNCTIME BIT(17) -#define DWC2_GOTGCTL_ASESVLD BIT(18) -#define DWC2_GOTGCTL_BSESVLD BIT(19) -#define DWC2_GOTGCTL_OTGVER BIT(20) -#define DWC2_GOTGINT_SESENDDET BIT(2) -#define DWC2_GOTGINT_SESREQSUCSTSCHNG BIT(8) -#define DWC2_GOTGINT_HSTNEGSUCSTSCHNG BIT(9) -#define DWC2_GOTGINT_RESERVER10_16_MASK GENMASK(16, 10) -#define DWC2_GOTGINT_HSTNEGDET BIT(17) -#define DWC2_GOTGINT_ADEVTOUTCHNG BIT(18) -#define DWC2_GOTGINT_DEBDONE BIT(19) -#define DWC2_GAHBCFG_GLBLINTRMSK BIT(0) -#define DWC2_GAHBCFG_HBURSTLEN_SINGLE (0 << 1) -#define DWC2_GAHBCFG_HBURSTLEN_INCR (1 << 1) -#define DWC2_GAHBCFG_HBURSTLEN_INCR4 (3 << 1) -#define DWC2_GAHBCFG_HBURSTLEN_INCR8 (5 << 1) -#define DWC2_GAHBCFG_HBURSTLEN_INCR16 (7 << 1) -#define DWC2_GAHBCFG_HBURSTLEN_MASK GENMASK(4, 1) -#define DWC2_GAHBCFG_DMAENABLE BIT(5) -#define DWC2_GAHBCFG_NPTXFEMPLVL_TXFEMPLVL BIT(7) -#define DWC2_GAHBCFG_PTXFEMPLVL BIT(8) -#define DWC2_GUSBCFG_TOUTCAL_MASK GENMASK(2, 0) -#define DWC2_GUSBCFG_PHYIF BIT(3) -#define DWC2_GUSBCFG_ULPI_UTMI_SEL BIT(4) -#define DWC2_GUSBCFG_FSINTF BIT(5) -#define DWC2_GUSBCFG_PHYSEL BIT(6) -#define DWC2_GUSBCFG_DDRSEL BIT(7) -#define DWC2_GUSBCFG_SRPCAP BIT(8) -#define DWC2_GUSBCFG_HNPCAP BIT(9) -#define DWC2_GUSBCFG_USBTRDTIM_MASK GENMASK(13, 10) -#define DWC2_GUSBCFG_NPTXFRWNDEN BIT(14) -#define DWC2_GUSBCFG_PHYLPWRCLKSEL BIT(15) -#define DWC2_GUSBCFG_OTGUTMIFSSEL BIT(16) -#define DWC2_GUSBCFG_ULPI_FSLS BIT(17) -#define DWC2_GUSBCFG_ULPI_AUTO_RES BIT(18) -#define DWC2_GUSBCFG_ULPI_CLK_SUS_M BIT(19) -#define DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV BIT(20) -#define DWC2_GUSBCFG_ULPI_INT_VBUS_INDICATOR BIT(21) -#define DWC2_GUSBCFG_TERM_SEL_DL_PULSE BIT(22) -#define DWC2_GUSBCFG_INDICATOR_PASSTHROUGH BIT(24) -#define DWC2_GUSBCFG_IC_USB_CAP BIT(26) -#define DWC2_GUSBCFG_IC_TRAFFIC_PULL_REMOVE BIT(27) -#define DWC2_GUSBCFG_TX_END_DELAY BIT(28) -#define DWC2_GUSBCFG_FORCEHOSTMODE BIT(29) -#define DWC2_GUSBCFG_FORCEDEVMODE BIT(30) -#define DWC2_GLPMCTL_LPM_CAP_EN BIT(0) -#define DWC2_GLPMCTL_APPL_RESP BIT(1) -#define DWC2_GLPMCTL_HIRD_MASK GENMASK(5, 2) -#define DWC2_GLPMCTL_REM_WKUP_EN BIT(6) -#define DWC2_GLPMCTL_EN_UTMI_SLEEP BIT(7) -#define DWC2_GLPMCTL_HIRD_THRES_MASK GENMASK(12, 8) -#define DWC2_GLPMCTL_LPM_RESP_MASK GENMASK(14, 13) -#define DWC2_GLPMCTL_PRT_SLEEP_STS BIT(15) -#define DWC2_GLPMCTL_SLEEP_STATE_RESUMEOK BIT(16) -#define DWC2_GLPMCTL_LPM_CHAN_INDEX_MASK GENMASK(20, 17) -#define DWC2_GLPMCTL_RETRY_COUNT_MASK GENMASK(23, 21) -#define DWC2_GLPMCTL_SEND_LPM BIT(24) -#define DWC2_GLPMCTL_RETRY_COUNT_STS_MASK GENMASK(27, 25) -#define DWC2_GLPMCTL_HSIC_CONNECT BIT(30) -#define DWC2_GLPMCTL_INV_SEL_HSIC BIT(31) -#define DWC2_GRSTCTL_CSFTRST BIT(0) -#define DWC2_GRSTCTL_HSFTRST BIT(1) -#define DWC2_GRSTCTL_HSTFRM BIT(2) -#define DWC2_GRSTCTL_INTKNQFLSH BIT(3) -#define DWC2_GRSTCTL_RXFFLSH BIT(4) -#define DWC2_GRSTCTL_TXFFLSH BIT(5) -#define DWC2_GRSTCTL_TXFNUM_MASK GENMASK(10, 6) -#define DWC2_GRSTCTL_DMAREQ BIT(30) -#define DWC2_GRSTCTL_AHBIDLE BIT(31) -#define DWC2_GINTMSK_MODEMISMATCH BIT(1) -#define DWC2_GINTMSK_OTGINTR BIT(2) -#define DWC2_GINTMSK_SOFINTR BIT(3) -#define DWC2_GINTMSK_RXSTSQLVL BIT(4) -#define DWC2_GINTMSK_NPTXFEMPTY BIT(5) -#define DWC2_GINTMSK_GINNAKEFF BIT(6) -#define DWC2_GINTMSK_GOUTNAKEFF BIT(7) -#define DWC2_GINTMSK_I2CINTR BIT(9) -#define DWC2_GINTMSK_ERLYSUSPEND BIT(10) -#define DWC2_GINTMSK_USBSUSPEND BIT(11) -#define DWC2_GINTMSK_USBRESET BIT(12) -#define DWC2_GINTMSK_ENUMDONE BIT(13) -#define DWC2_GINTMSK_ISOOUTDROP BIT(14) -#define DWC2_GINTMSK_EOPFRAME BIT(15) -#define DWC2_GINTMSK_EPMISMATCH BIT(17) -#define DWC2_GINTMSK_INEPINTR BIT(18) -#define DWC2_GINTMSK_OUTEPINTR BIT(19) -#define DWC2_GINTMSK_INCOMPLISOIN BIT(20) -#define DWC2_GINTMSK_INCOMPLISOOUT BIT(21) -#define DWC2_GINTMSK_PORTINTR BIT(24) -#define DWC2_GINTMSK_HCINTR BIT(25) -#define DWC2_GINTMSK_PTXFEMPTY BIT(26) -#define DWC2_GINTMSK_LPMTRANRCVD BIT(27) -#define DWC2_GINTMSK_CONIDSTSCHNG BIT(28) -#define DWC2_GINTMSK_DISCONNECT BIT(29) -#define DWC2_GINTMSK_SESSREQINTR BIT(30) -#define DWC2_GINTMSK_WKUPINTR BIT(31) -#define DWC2_GINTSTS_CURMODE_HOST BIT(0) -#define DWC2_GINTSTS_MODEMISMATCH BIT(1) -#define DWC2_GINTSTS_OTGINTR BIT(2) -#define DWC2_GINTSTS_SOFINTR BIT(3) -#define DWC2_GINTSTS_RXSTSQLVL BIT(4) -#define DWC2_GINTSTS_NPTXFEMPTY BIT(5) -#define DWC2_GINTSTS_GINNAKEFF BIT(6) -#define DWC2_GINTSTS_GOUTNAKEFF BIT(7) -#define DWC2_GINTSTS_I2CINTR BIT(9) -#define DWC2_GINTSTS_ERLYSUSPEND BIT(10) -#define DWC2_GINTSTS_USBSUSPEND BIT(11) -#define DWC2_GINTSTS_USBRESET BIT(12) -#define DWC2_GINTSTS_ENUMDONE BIT(13) -#define DWC2_GINTSTS_ISOOUTDROP BIT(14) -#define DWC2_GINTSTS_EOPFRAME BIT(15) -#define DWC2_GINTSTS_INTOKENRX BIT(16) -#define DWC2_GINTSTS_EPMISMATCH BIT(17) -#define DWC2_GINTSTS_INEPINT BIT(18) -#define DWC2_GINTSTS_OUTEPINTR BIT(19) -#define DWC2_GINTSTS_INCOMPLISOIN BIT(20) -#define DWC2_GINTSTS_INCOMPLISOOUT BIT(21) -#define DWC2_GINTSTS_PORTINTR BIT(24) -#define DWC2_GINTSTS_HCINTR BIT(25) -#define DWC2_GINTSTS_PTXFEMPTY BIT(26) -#define DWC2_GINTSTS_LPMTRANRCVD BIT(27) -#define DWC2_GINTSTS_CONIDSTSCHNG BIT(28) -#define DWC2_GINTSTS_DISCONNECT BIT(29) -#define DWC2_GINTSTS_SESSREQINTR BIT(30) -#define DWC2_GINTSTS_WKUPINTR BIT(31) -#define DWC2_GRXSTS_EPNUM_MASK GENMASK(3, 0) -#define DWC2_GRXSTS_BCNT_MASK GENMASK(14, 4) -#define DWC2_GRXSTS_DPID_MASK GENMASK(16, 15) -#define DWC2_GRXSTS_PKTSTS_MASK GENMASK(20, 17) -#define DWC2_GRXSTS_FN_MASK GENMASK(24, 21) -#define DWC2_FIFOSIZE_STARTADDR_MASK GENMASK(15, 0) -#define DWC2_FIFOSIZE_DEPTH_MASK GENMASK(31, 16) -#define DWC2_GNPTXSTS_NPTXFSPCAVAIL_MASK GENMASK(15, 0) -#define DWC2_GNPTXSTS_NPTXQSPCAVAIL_MASK GENMASK(23, 16) -#define DWC2_GNPTXSTS_NPTXQTOP_TERMINATE BIT(24) -#define DWC2_GNPTXSTS_NPTXQTOP_TOKEN_MASK GENMASK(26, 25) -#define DWC2_GNPTXSTS_NPTXQTOP_CHNEP_MASK GENMASK(30, 27) -#define DWC2_DTXFSTS_TXFSPCAVAIL_MASK GENMASK(15, 0) -#define DWC2_GI2CCTL_RWDATA_MASK GENMASK(7, 0) -#define DWC2_GI2CCTL_REGADDR_MASK GENMASK(15, 8) -#define DWC2_GI2CCTL_ADDR_MASK GENMASK(22, 16) -#define DWC2_GI2CCTL_I2CEN BIT(23) -#define DWC2_GI2CCTL_ACK BIT(24) -#define DWC2_GI2CCTL_I2CSUSPCTL BIT(25) -#define DWC2_GI2CCTL_I2CDEVADDR_MASK GENMASK(27, 26) -#define DWC2_GI2CCTL_RW BIT(30) -#define DWC2_GI2CCTL_BSYDNE BIT(31) -#define DWC2_HWCFG1_EP_DIR0_MASK GENMASK(1, 0) -#define DWC2_HWCFG1_EP_DIR1_MASK GENMASK(3, 2) -#define DWC2_HWCFG1_EP_DIR2_MASK GENMASK(5, 4) -#define DWC2_HWCFG1_EP_DIR3_MASK GENMASK(7, 6) -#define DWC2_HWCFG1_EP_DIR4_MASK GENMASK(9, 8) -#define DWC2_HWCFG1_EP_DIR5_MASK GENMASK(11, 10) -#define DWC2_HWCFG1_EP_DIR6_MASK GENMASK(13, 12) -#define DWC2_HWCFG1_EP_DIR7_MASK GENMASK(15, 14) -#define DWC2_HWCFG1_EP_DIR8_MASK GENMASK(17, 16) -#define DWC2_HWCFG1_EP_DIR9_MASK GENMASK(19, 18) -#define DWC2_HWCFG1_EP_DIR10_MASK GENMASK(21, 20) -#define DWC2_HWCFG1_EP_DIR11_MASK GENMASK(23, 22) -#define DWC2_HWCFG1_EP_DIR12_MASK GENMASK(25, 24) -#define DWC2_HWCFG1_EP_DIR13_MASK GENMASK(27, 26) -#define DWC2_HWCFG1_EP_DIR14_MASK GENMASK(29, 28) -#define DWC2_HWCFG1_EP_DIR15_MASK GENMASK(31, 30) -#define DWC2_HWCFG2_OP_MODE_MASK GENMASK(2, 0) -#define DWC2_HWCFG2_ARCHITECTURE_SLAVE_ONLY (0x0 << 3) -#define DWC2_HWCFG2_ARCHITECTURE_EXT_DMA (0x1 << 3) -#define DWC2_HWCFG2_ARCHITECTURE_INT_DMA (0x2 << 3) -#define DWC2_HWCFG2_ARCHITECTURE_MASK GENMASK(4, 3) -#define DWC2_HWCFG2_POINT2POINT BIT(5) -#define DWC2_HWCFG2_HS_PHY_TYPE_MASK GENMASK(7, 6) -#define DWC2_HWCFG2_FS_PHY_TYPE_MASK GENMASK(9, 8) -#define DWC2_HWCFG2_NUM_DEV_EP_MASK GENMASK(13, 10) -#define DWC2_HWCFG2_NUM_HOST_CHAN_MASK GENMASK(17, 14) -#define DWC2_HWCFG2_PERIO_EP_SUPPORTED BIT(18) -#define DWC2_HWCFG2_DYNAMIC_FIFO BIT(19) -#define DWC2_HWCFG2_MULTI_PROC_INT BIT(20) -#define DWC2_HWCFG2_NONPERIO_TX_Q_DEPTH_MASK GENMASK(23, 22) -#define DWC2_HWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK GENMASK(25, 24) -#define DWC2_HWCFG2_DEV_TOKEN_Q_DEPTH_MASK GENMASK(30, 26) -#define DWC2_HWCFG3_XFER_SIZE_CNTR_WIDTH_MASK GENMASK(3, 0) -#define DWC2_HWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK GENMASK(6, 4) -#define DWC2_HWCFG3_OTG_FUNC BIT(7) -#define DWC2_HWCFG3_I2C BIT(8) -#define DWC2_HWCFG3_VENDOR_CTRL_IF BIT(9) -#define DWC2_HWCFG3_OPTIONAL_FEATURES BIT(10) -#define DWC2_HWCFG3_SYNCH_RESET_TYPE BIT(11) -#define DWC2_HWCFG3_OTG_ENABLE_IC_USB BIT(12) -#define DWC2_HWCFG3_OTG_ENABLE_HSIC BIT(13) -#define DWC2_HWCFG3_OTG_LPM_EN BIT(15) -#define DWC2_HWCFG3_DFIFO_DEPTH_MASK GENMASK(31, 16) -#define DWC2_HWCFG4_NUM_DEV_PERIO_IN_EP_MASK GENMASK(3, 0) -#define DWC2_HWCFG4_POWER_OPTIMIZ BIT(4) -#define DWC2_HWCFG4_MIN_AHB_FREQ_MASK GENMASK(13, 5) -#define DWC2_HWCFG4_UTMI_PHY_DATA_WIDTH_MASK GENMASK(15, 14) -#define DWC2_HWCFG4_NUM_DEV_MODE_CTRL_EP_MASK GENMASK(19, 16) -#define DWC2_HWCFG4_IDDIG_FILT_EN BIT(20) -#define DWC2_HWCFG4_VBUS_VALID_FILT_EN BIT(21) -#define DWC2_HWCFG4_A_VALID_FILT_EN BIT(22) -#define DWC2_HWCFG4_B_VALID_FILT_EN BIT(23) -#define DWC2_HWCFG4_SESSION_END_FILT_EN BIT(24) -#define DWC2_HWCFG4_DED_FIFO_EN BIT(25) -#define DWC2_HWCFG4_NUM_IN_EPS_MASK GENMASK(29, 26) -#define DWC2_HWCFG4_DESC_DMA BIT(30) -#define DWC2_HWCFG4_DESC_DMA_DYN BIT(31) -#define DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ 0 -#define DWC2_HCFG_FSLSPCLKSEL_48_MHZ 1 -#define DWC2_HCFG_FSLSPCLKSEL_6_MHZ 2 -#define DWC2_HCFG_FSLSPCLKSEL_MASK GENMASK(1, 0) -#define DWC2_HCFG_FSLSSUPP BIT(2) -#define DWC2_HCFG_DESCDMA BIT(23) -#define DWC2_HCFG_FRLISTEN_MASK GENMASK(25, 24) -#define DWC2_HCFG_PERSCHEDENA BIT(26) -#define DWC2_HCFG_PERSCHEDSTAT BIT(27) -#define DWC2_HFIR_FRINT_MASK GENMASK(15, 0) -#define DWC2_HFNUM_FRNUM_MASK GENMASK(15, 0) -#define DWC2_HFNUM_FRREM_MASK GENMASK(31, 16) -#define DWC2_HFNUM_MAX_FRNUM 0x3FFF -#define DWC2_HPTXSTS_PTXFSPCAVAIL_MASK GENMASK(15, 0) -#define DWC2_HPTXSTS_PTXQSPCAVAIL_MASK GENMASK(23, 16) -#define DWC2_HPTXSTS_PTXQTOP_TERMINATE BIT(24) -#define DWC2_HPTXSTS_PTXQTOP_TOKEN_MASK GENMASK(26, 25) -#define DWC2_HPTXSTS_PTXQTOP_CHNUM_MASK GENMASK(30, 27) -#define DWC2_HPTXSTS_PTXQTOP_ODD BIT(31) -#define DWC2_HPRT0_PRTCONNSTS BIT(0) -#define DWC2_HPRT0_PRTCONNDET BIT(1) -#define DWC2_HPRT0_PRTENA BIT(2) -#define DWC2_HPRT0_PRTENCHNG BIT(3) -#define DWC2_HPRT0_PRTOVRCURRACT BIT(4) -#define DWC2_HPRT0_PRTOVRCURRCHNG BIT(5) -#define DWC2_HPRT0_PRTRES BIT(6) -#define DWC2_HPRT0_PRTSUSP BIT(7) -#define DWC2_HPRT0_PRTRST BIT(8) -#define DWC2_HPRT0_PRTLNSTS_MASK GENMASK(11, 10) -#define DWC2_HPRT0_PRTPWR BIT(12) -#define DWC2_HPRT0_PRTTSTCTL_MASK GENMASK(16, 13) -#define DWC2_HPRT0_PRTSPD_HIGH (0 << 17) -#define DWC2_HPRT0_PRTSPD_FULL (1 << 17) -#define DWC2_HPRT0_PRTSPD_LOW (2 << 17) -#define DWC2_HPRT0_PRTSPD_MASK GENMASK(18, 17) -#define DWC2_HPRT0_W1C_MASK (DWC2_HPRT0_PRTCONNDET | \ - DWC2_HPRT0_PRTENA | \ - DWC2_HPRT0_PRTENCHNG | \ - DWC2_HPRT0_PRTOVRCURRCHNG) -#define DWC2_HAINT_CH0 BIT(0) -#define DWC2_HAINT_CH1 BIT(1) -#define DWC2_HAINT_CH2 BIT(2) -#define DWC2_HAINT_CH3 BIT(3) -#define DWC2_HAINT_CH4 BIT(4) -#define DWC2_HAINT_CH5 BIT(5) -#define DWC2_HAINT_CH6 BIT(6) -#define DWC2_HAINT_CH7 BIT(7) -#define DWC2_HAINT_CH8 BIT(8) -#define DWC2_HAINT_CH9 BIT(9) -#define DWC2_HAINT_CH10 BIT(10) -#define DWC2_HAINT_CH11 BIT(11) -#define DWC2_HAINT_CH12 BIT(12) -#define DWC2_HAINT_CH13 BIT(13) -#define DWC2_HAINT_CH14 BIT(14) -#define DWC2_HAINT_CH15 BIT(15) -#define DWC2_HAINT_CHINT_MASK GENMASK(15, 0) -#define DWC2_HAINTMSK_CH0 BIT(0) -#define DWC2_HAINTMSK_CH1 BIT(1) -#define DWC2_HAINTMSK_CH2 BIT(2) -#define DWC2_HAINTMSK_CH3 BIT(3) -#define DWC2_HAINTMSK_CH4 BIT(4) -#define DWC2_HAINTMSK_CH5 BIT(5) -#define DWC2_HAINTMSK_CH6 BIT(6) -#define DWC2_HAINTMSK_CH7 BIT(7) -#define DWC2_HAINTMSK_CH8 BIT(8) -#define DWC2_HAINTMSK_CH9 BIT(9) -#define DWC2_HAINTMSK_CH10 BIT(10) -#define DWC2_HAINTMSK_CH11 BIT(11) -#define DWC2_HAINTMSK_CH12 BIT(12) -#define DWC2_HAINTMSK_CH13 BIT(13) -#define DWC2_HAINTMSK_CH14 BIT(14) -#define DWC2_HAINTMSK_CH15 BIT(15) -#define DWC2_HAINTMSK_CHINT_MASK GENMASK(15, 0) -#define DWC2_HCCHAR_MPS_MASK GENMASK(10, 0) -#define DWC2_HCCHAR_EPNUM_MASK GENMASK(14, 11) -#define DWC2_HCCHAR_EPDIR BIT(15) -#define DWC2_HCCHAR_LSPDDEV BIT(17) -#define DWC2_HCCHAR_EPTYPE_CONTROL 0 -#define DWC2_HCCHAR_EPTYPE_ISOC 1 -#define DWC2_HCCHAR_EPTYPE_BULK 2 -#define DWC2_HCCHAR_EPTYPE_INTR 3 -#define DWC2_HCCHAR_EPTYPE_MASK GENMASK(19, 18) -#define DWC2_HCCHAR_MULTICNT_MASK GENMASK(21, 20) -#define DWC2_HCCHAR_DEVADDR_MASK GENMASK(28, 22) -#define DWC2_HCCHAR_ODDFRM BIT(29) -#define DWC2_HCCHAR_CHDIS BIT(30) -#define DWC2_HCCHAR_CHEN BIT(31) -#define DWC2_HCSPLT_PRTADDR_MASK GENMASK(6, 0) -#define DWC2_HCSPLT_HUBADDR_MASK GENMASK(13, 7) -#define DWC2_HCSPLT_XACTPOS_MASK GENMASK(15, 14) -#define DWC2_HCSPLT_COMPSPLT BIT(16) -#define DWC2_HCSPLT_SPLTENA BIT(31) -#define DWC2_HCINT_XFERCOMP BIT(0) -#define DWC2_HCINT_CHHLTD BIT(1) -#define DWC2_HCINT_AHBERR BIT(2) -#define DWC2_HCINT_STALL BIT(3) -#define DWC2_HCINT_NAK BIT(4) -#define DWC2_HCINT_ACK BIT(5) -#define DWC2_HCINT_NYET BIT(6) -#define DWC2_HCINT_XACTERR BIT(7) -#define DWC2_HCINT_BBLERR BIT(8) -#define DWC2_HCINT_FRMOVRUN BIT(9) -#define DWC2_HCINT_DATATGLERR BIT(10) -#define DWC2_HCINT_BNA BIT(11) -#define DWC2_HCINT_XCS_XACT BIT(12) -#define DWC2_HCINT_FRM_LIST_ROLL BIT(13) -#define DWC2_HCINTMSK_XFERCOMPL BIT(0) -#define DWC2_HCINTMSK_CHHLTD BIT(1) -#define DWC2_HCINTMSK_AHBERR BIT(2) -#define DWC2_HCINTMSK_STALL BIT(3) -#define DWC2_HCINTMSK_NAK BIT(4) -#define DWC2_HCINTMSK_ACK BIT(5) -#define DWC2_HCINTMSK_NYET BIT(6) -#define DWC2_HCINTMSK_XACTERR BIT(7) -#define DWC2_HCINTMSK_BBLERR BIT(8) -#define DWC2_HCINTMSK_FRMOVRUN BIT(9) -#define DWC2_HCINTMSK_DATATGLERR BIT(10) -#define DWC2_HCINTMSK_BNA BIT(11) -#define DWC2_HCINTMSK_XCS_XACT BIT(12) -#define DWC2_HCINTMSK_FRM_LIST_ROLL BIT(13) -#define DWC2_HCTSIZ_XFERSIZE_MASK GENMASK(18, 0) -#define DWC2_HCTSIZ_SCHINFO_MASK GENMASK(7, 0) -#define DWC2_HCTSIZ_NTD_MASK GENMASK(15, 8) -#define DWC2_HCTSIZ_PKTCNT_MASK GENMASK(28, 19) -#define DWC2_HCTSIZ_PID_MASK GENMASK(30, 29) -#define DWC2_HCTSIZ_DOPNG BIT(31) -#define DWC2_HCDMA_CTD_MASK GENMASK(10, 3) -#define DWC2_HCDMA_DMA_ADDR_MASK GENMASK(31, 11) -#define DWC2_PCGCCTL_STOPPCLK BIT(0) -#define DWC2_PCGCCTL_GATEHCLK BIT(1) -#define DWC2_PCGCCTL_PWRCLMP BIT(2) -#define DWC2_PCGCCTL_RSTPDWNMODULE BIT(3) -#define DWC2_PCGCCTL_PHYSUSPENDED BIT(4) -#define DWC2_PCGCCTL_ENBL_SLEEP_GATING BIT(5) -#define DWC2_PCGCCTL_PHY_IN_SLEEP BIT(6) -#define DWC2_PCGCCTL_DEEP_SLEEP BIT(7) -#define DWC2_SNPSID_DEVID_VER_2xx (0x4f542 << 12) -#define DWC2_SNPSID_DEVID_VER_3xx (0x4f543 << 12) -#define DWC2_SNPSID_DEVID_MASK GENMASK(31, 12) +#define GOTGCTL_CHIRPEN BIT(27) +#define GOTGCTL_MULT_VALID_BC_MASK GENMASK(26, 22) +#define GOTGCTL_CURMODE_HOST BIT(21) +#define GOTGCTL_OTGVER BIT(20) +#define GOTGCTL_BSESVLD BIT(19) +#define GOTGCTL_ASESVLD BIT(18) +#define GOTGCTL_DBNC_SHORT BIT(17) +#define GOTGCTL_CONID_B BIT(16) +#define GOTGCTL_DBNCE_FLTR_BYPASS BIT(15) +#define GOTGCTL_DEVHNPEN BIT(11) +#define GOTGCTL_HSTSETHNPEN BIT(10) +#define GOTGCTL_HNPREQ BIT(9) +#define GOTGCTL_HSTNEGSCS BIT(8) +#define GOTGCTL_BVALOVAL BIT(7) +#define GOTGCTL_BVALOEN BIT(6) +#define GOTGCTL_AVALOVAL BIT(5) +#define GOTGCTL_AVALOEN BIT(4) +#define GOTGCTL_VBVALOVAL BIT(3) +#define GOTGCTL_VBVALOEN BIT(2) +#define GOTGCTL_SESREQ BIT(1) +#define GOTGCTL_SESREQSCS BIT(0) + +#define GOTGINT_DBNCE_DONE BIT(19) +#define GOTGINT_A_DEV_TOUT_CHG BIT(18) +#define GOTGINT_HST_NEG_DET BIT(17) +#define GOTGINT_HST_NEG_SUC_STS_CHNG BIT(9) +#define GOTGINT_SES_REQ_SUC_STS_CHNG BIT(8) +#define GOTGINT_SES_END_DET BIT(2) + +#define GAHBCFG_AHB_SINGLE BIT(23) +#define GAHBCFG_NOTI_ALL_DMA_WRIT BIT(22) +#define GAHBCFG_REM_MEM_SUPP BIT(21) +#define GAHBCFG_P_TXF_EMP_LVL BIT(8) +#define GAHBCFG_NP_TXF_EMP_LVL BIT(7) +#define GAHBCFG_DMA_EN BIT(5) +#define GAHBCFG_HBSTLEN_MASK GENMASK(4, 1) +#define GAHBCFG_HBSTLEN_SINGLE 0 +#define GAHBCFG_HBSTLEN_INCR 1 +#define GAHBCFG_HBSTLEN_INCR4 3 +#define GAHBCFG_HBSTLEN_INCR8 5 +#define GAHBCFG_HBSTLEN_INCR16 7 +#define GAHBCFG_GLBL_INTR_EN BIT(0) +#define GAHBCFG_CTRL_MASK (GAHBCFG_P_TXF_EMP_LVL | \ + GAHBCFG_NP_TXF_EMP_LVL | \ + GAHBCFG_DMA_EN | \ + GAHBCFG_GLBL_INTR_EN) + +#define GUSBCFG_FORCEDEVMODE BIT(30) +#define GUSBCFG_FORCEHOSTMODE BIT(29) +#define GUSBCFG_TXENDDELAY BIT(28) +#define GUSBCFG_ICTRAFFICPULLREMOVE BIT(27) +#define GUSBCFG_ICUSBCAP BIT(26) +#define GUSBCFG_ULPI_INT_PROT_DIS BIT(25) +#define GUSBCFG_INDICATORPASSTHROUGH BIT(24) +#define GUSBCFG_INDICATORCOMPLEMENT BIT(23) +#define GUSBCFG_TERMSELDLPULSE BIT(22) +#define GUSBCFG_ULPI_INT_VBUS_IND BIT(21) +#define GUSBCFG_ULPI_EXT_VBUS_DRV BIT(20) +#define GUSBCFG_ULPI_CLK_SUSP_M BIT(19) +#define GUSBCFG_ULPI_AUTO_RES BIT(18) +#define GUSBCFG_ULPI_FS_LS BIT(17) +#define GUSBCFG_OTG_UTMI_FS_SEL BIT(16) +#define GUSBCFG_PHY_LP_CLK_SEL BIT(15) +#define GUSBCFG_USBTRDTIM_MASK GENMASK(14, 10) +#define GUSBCFG_HNPCAP BIT(9) +#define GUSBCFG_SRPCAP BIT(8) +#define GUSBCFG_DDRSEL BIT(7) +#define GUSBCFG_PHYSEL BIT(6) +#define GUSBCFG_FSINTF BIT(5) +#define GUSBCFG_ULPI_UTMI_SEL BIT(4) +#define GUSBCFG_PHYIF16 BIT(3) +#define GUSBCFG_TOUTCAL_MASK GENMASK(2, 0) + +#define GRSTCTL_AHBIDLE BIT(31) +#define GRSTCTL_DMAREQ BIT(30) +#define GRSTCTL_CSFTRST_DONE BIT(29) +#define GRSTCTL_TXFNUM_MASK GENMASK(10, 6) +#define GRSTCTL_TXFFLSH BIT(5) +#define GRSTCTL_RXFFLSH BIT(4) +#define GRSTCTL_IN_TKNQ_FLSH BIT(3) +#define GRSTCTL_FRMCNTRRST BIT(2) +#define GRSTCTL_HSFTRST BIT(1) +#define GRSTCTL_CSFTRST BIT(0) +#define GRSTCTL_TXFNUM_ALL 0x10 + +#define GINTSTS_WKUPINT BIT(31) +#define GINTSTS_SESSREQINT BIT(30) +#define GINTSTS_DISCONNINT BIT(29) +#define GINTSTS_CONIDSTSCHNG BIT(28) +#define GINTSTS_LPMTRANRCVD BIT(27) +#define GINTSTS_PTXFEMP BIT(26) +#define GINTSTS_HCHINT BIT(25) +#define GINTSTS_PRTINT BIT(24) +#define GINTSTS_RESETDET BIT(23) +#define GINTSTS_FET_SUSP BIT(22) +#define GINTSTS_INCOMPL_IP BIT(21) +#define GINTSTS_INCOMPL_SOOUT BIT(21) +#define GINTSTS_INCOMPL_SOIN BIT(20) +#define GINTSTS_OEPINT BIT(19) +#define GINTSTS_IEPINT BIT(18) +#define GINTSTS_EPMIS BIT(17) +#define GINTSTS_RESTOREDONE BIT(16) +#define GINTSTS_EOPF BIT(15) +#define GINTSTS_ISOUTDROP BIT(14) +#define GINTSTS_ENUMDONE BIT(13) +#define GINTSTS_USBRST BIT(12) +#define GINTSTS_USBSUSP BIT(11) +#define GINTSTS_ERLYSUSP BIT(10) +#define GINTSTS_I2CINT BIT(9) +#define GINTSTS_ULPI_CK_INT BIT(8) +#define GINTSTS_GOUTNAKEFF BIT(7) +#define GINTSTS_GINNAKEFF BIT(6) +#define GINTSTS_NPTXFEMP BIT(5) +#define GINTSTS_RXFLVL BIT(4) +#define GINTSTS_SOF BIT(3) +#define GINTSTS_OTGINT BIT(2) +#define GINTSTS_MODEMIS BIT(1) +#define GINTSTS_CURMODE_HOST BIT(0) + +#define FIFOSIZE_DEPTH_MASK GENMASK(31, 16) +#define FIFOSIZE_STARTADDR_MASK GENMASK(15, 0) + +#define GI2CCTL_BSYDNE BIT(31) +#define GI2CCTL_RW BIT(30) +#define GI2CCTL_I2CDATSE0 BIT(28) +#define GI2CCTL_I2CDEVADDR_MASK GENMASK(27, 26) +#define GI2CCTL_I2CSUSPCTL BIT(25) +#define GI2CCTL_ACK BIT(24) +#define GI2CCTL_I2CEN BIT(23) +#define GI2CCTL_ADDR_MASK GENMASK(22, 16) +#define GI2CCTL_REGADDR_MASK GENMASK(15, 8) +#define GI2CCTL_RWDATA_MASK GENMASK(7, 0) + +#define GHWCFG2_OTG_ENABLE_IC_USB BIT(31) +#define GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK GENMASK(30, 26) +#define GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK GENMASK(25, 24) +#define GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK GENMASK(23, 22) +#define GHWCFG2_MULTI_PROC_INT BIT(20) +#define GHWCFG2_DYNAMIC_FIFO BIT(19) +#define GHWCFG2_PERIO_EP_SUPPORTED BIT(18) +#define GHWCFG2_NUM_HOST_CHAN_MASK GENMASK(17, 14) +#define GHWCFG2_NUM_DEV_EP_MASK GENMASK(13, 10) +#define GHWCFG2_FS_PHY_TYPE_MASK GENMASK(9, 8) +#define GHWCFG2_FS_PHY_TYPE_NOT_SUPPORTED 0 +#define GHWCFG2_FS_PHY_TYPE_DEDICATED 1 +#define GHWCFG2_FS_PHY_TYPE_SHARED_UTMI 2 +#define GHWCFG2_FS_PHY_TYPE_SHARED_ULPI 3 +#define GHWCFG2_HS_PHY_TYPE_MASK GENMASK(7, 6) +#define GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED 0 +#define GHWCFG2_HS_PHY_TYPE_UTMI 1 +#define GHWCFG2_HS_PHY_TYPE_ULPI 2 +#define GHWCFG2_HS_PHY_TYPE_UTMI_ULPI 3 +#define GHWCFG2_POINT2POINT BIT(5) +#define GHWCFG2_ARCHITECTURE_MASK GENMASK(4, 3) +#define GHWCFG2_SLAVE_ONLY_ARCH 0 +#define GHWCFG2_EXT_DMA_ARCH 1 +#define GHWCFG2_INT_DMA_ARCH 2 +#define GHWCFG2_OP_MODE_MASK GENMASK(2, 0) +#define GHWCFG2_OP_MODE_HNP_SRP_CAPABLE 0 +#define GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE 1 +#define GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE 2 +#define GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE 3 +#define GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE 4 +#define GHWCFG2_OP_MODE_SRP_CAPABLE_HOST 5 +#define GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST 6 +#define GHWCFG2_OP_MODE_UNDEFINED 7 + +#define GHWCFG4_DESC_DMA_DYN BIT(31) +#define GHWCFG4_DESC_DMA BIT(30) +#define GHWCFG4_NUM_IN_EPS_MASK GENMASK(29, 26) +#define GHWCFG4_DED_FIFO_EN BIT(25) +#define GHWCFG4_SESSION_END_FILT_EN BIT(24) +#define GHWCFG4_B_VALID_FILT_EN BIT(23) +#define GHWCFG4_A_VALID_FILT_EN BIT(22) +#define GHWCFG4_VBUS_VALID_FILT_EN BIT(21) +#define GHWCFG4_IDDIG_FILT_EN BIT(20) +#define GHWCFG4_NUM_DEV_MODE_CTRL_EP_MASK GENMASK(19, 16) +#define GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK GENMASK(15, 14) +#define GHWCFG4_UTMI_PHY_DATA_WIDTH_8 0 +#define GHWCFG4_UTMI_PHY_DATA_WIDTH_16 1 +#define GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16 2 +#define GHWCFG4_ACG_SUPPORTED BIT(12) +#define GHWCFG4_IPG_ISOC_SUPPORTED BIT(11) +#define GHWCFG4_SERVICE_INTERVAL_SUPPORTED BIT(10) +#define GHWCFG4_XHIBER BIT(7) +#define GHWCFG4_HIBER BIT(6) +#define GHWCFG4_MIN_AHB_FREQ BIT(5) +#define GHWCFG4_POWER_OPTIMIZ BIT(4) +#define GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK GENMASK(3, 0) + +#define HCFG_MODECHTIMEN BIT(31) +#define HCFG_PERSCHEDENA BIT(26) +#define HCFG_FRLISTEN_MASK GENMASK(25, 24) +#define HCFG_FRLISTEN_8 0 +#define HCFG_FRLISTEN_16 1 +#define HCFG_FRLISTEN_32 2 +#define HCFG_FRLISTEN_64 3 +#define HCFG_DESCDMA BIT(23) +#define HCFG_RESVALID_MASK GENMASK(15, 8) +#define HCFG_ENA32KHZ BIT(7) +#define HCFG_FSLSSUPP BIT(2) +#define HCFG_FSLSPCLKSEL_MASK GENMASK(2, 0) +#define HCFG_FSLSPCLKSEL_30_60_MHZ 0 +#define HCFG_FSLSPCLKSEL_48_MHZ 1 +#define HCFG_FSLSPCLKSEL_6_MHZ 2 + +#define HFIR_FRINT_MASK GENMASK(15, 0) +#define HFIR_RLDCTRL BIT(16) + +#define HFNUM_FRREM_MASK GENMASK(31, 16) +#define HFNUM_FRNUM_MASK GENMASK(15, 0) + +#define HPRT0_SPD_MASK GENMASK(18, 17) +#define HPRT0_SPD_HIGH_SPEED 0 +#define HPRT0_SPD_FULL_SPEED 1 +#define HPRT0_SPD_LOW_SPEED 2 +#define HPRT0_TSTCTL_MASK GENMASK(16, 13) +#define HPRT0_PWR BIT(12) +#define HPRT0_LNSTS_MASK GENMASK(11, 10) +#define HPRT0_RST BIT(8) +#define HPRT0_SUSP BIT(7) +#define HPRT0_RES BIT(6) +#define HPRT0_OVRCURRCHG BIT(5) +#define HPRT0_OVRCURRACT BIT(4) +#define HPRT0_ENACHG BIT(3) +#define HPRT0_ENA BIT(2) +#define HPRT0_CONNDET BIT(1) +#define HPRT0_CONNSTS BIT(0) +#define HPRT0_W1C_MASK (HPRT0_CONNDET | \ + HPRT0_ENA | \ + HPRT0_ENACHG | \ + HPRT0_OVRCURRCHG) + +#define HCCHAR_CHENA BIT(31) +#define HCCHAR_CHDIS BIT(30) +#define HCCHAR_ODDFRM BIT(29) +#define HCCHAR_DEVADDR_MASK GENMASK(28, 22) +#define HCCHAR_MULTICNT_MASK GENMASK(21, 20) +#define HCCHAR_EPTYPE_MASK GENMASK(19, 18) +#define HCCHAR_EPTYPE_CONTROL 0 +#define HCCHAR_EPTYPE_ISOC 1 +#define HCCHAR_EPTYPE_BULK 2 +#define HCCHAR_EPTYPE_INTR 3 +#define HCCHAR_LSPDDEV BIT(17) +#define HCCHAR_EPDIR BIT(15) +#define HCCHAR_EPNUM_MASK GENMASK(14, 11) +#define HCCHAR_MPS_MASK GENMASK(10, 0) + +#define HCSPLT_SPLTENA BIT(31) +#define HCSPLT_COMPSPLT BIT(16) +#define HCSPLT_XACTPOS_MASK GENMASK(15, 14) +#define HCSPLT_XACTPOS_MID 0 +#define HCSPLT_XACTPOS_END 1 +#define HCSPLT_XACTPOS_BEGIN 2 +#define HCSPLT_XACTPOS_ALL 3 +#define HCSPLT_HUBADDR_MASK GENMASK(13, 7) +#define HCSPLT_PRTADDR_MASK GENMASK(6, 0) + +#define HCINTMSK_FRM_LIST_ROLL BIT(13) +#define HCINTMSK_XCS_XACT BIT(12) +#define HCINTMSK_BNA BIT(11) +#define HCINTMSK_DATATGLERR BIT(10) +#define HCINTMSK_FRMOVRUN BIT(9) +#define HCINTMSK_BBLERR BIT(8) +#define HCINTMSK_XACTERR BIT(7) +#define HCINTMSK_NYET BIT(6) +#define HCINTMSK_ACK BIT(5) +#define HCINTMSK_NAK BIT(4) +#define HCINTMSK_STALL BIT(3) +#define HCINTMSK_AHBERR BIT(2) +#define HCINTMSK_CHHLTD BIT(1) +#define HCINTMSK_XFERCOMPL BIT(0) + +#define TSIZ_DOPNG BIT(31) +#define TSIZ_SC_MC_PID_MASK GENMASK(30, 29) +#define TSIZ_SC_MC_PID_DATA0 0 +#define TSIZ_SC_MC_PID_DATA2 1 +#define TSIZ_SC_MC_PID_DATA1 2 +#define TSIZ_SC_MC_PID_MDATA 3 +#define TSIZ_SC_MC_PID_SETUP 3 +#define TSIZ_PKTCNT_MASK GENMASK(28, 19) +#define TSIZ_NTD_MASK GENMASK(15, 8) +#define TSIZ_SCHINFO_MASK GENMASK(7, 0) +#define TSIZ_XFERSIZE_MASK GENMASK(18, 0) + +#define GSNPSID_ID_MASK GENMASK(31, 16) +#define GSNPSID_OTG_ID 0x4f54 +#define GSNPSID_VER_MASK GENMASK(15, 0) /* Host controller specific */ #define DWC2_HC_PID_DATA0 0 |