diff options
Diffstat (limited to 'drivers/video')
| -rw-r--r-- | drivers/video/Kconfig | 9 | ||||
| -rw-r--r-- | drivers/video/Makefile | 1 | ||||
| -rw-r--r-- | drivers/video/sharp-lq101r1sx01.c | 282 | ||||
| -rw-r--r-- | drivers/video/tegra20/tegra-dc.c | 2 | ||||
| -rw-r--r-- | drivers/video/tegra20/tegra-dsi.c | 95 | ||||
| -rw-r--r-- | drivers/video/tegra20/tegra-dsi.h | 15 |
6 files changed, 396 insertions, 8 deletions
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 6e79694fd19..3c3cebaacd0 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -599,6 +599,15 @@ config VIDEO_LCD_SAMSUNG_LTL106HL02 LCD module found in Microsoft Surface 2. The panel has a FullHD resolution (1920x1080). +config VIDEO_LCD_SHARP_LQ101R1SX01 + tristate "Sharp LQ101R1SX01 2560x1600 DSI video mode panel" + depends on PANEL && BACKLIGHT + select VIDEO_MIPI_DSI + help + Say Y here if you want to enable support for Sharp LQ101R1SX01 + LCD module found in ASUS Transformer TF701T. The panel has a + WQXGA resolution (2560x1600). + config VIDEO_LCD_SSD2828 bool "SSD2828 bridge chip" ---help--- diff --git a/drivers/video/Makefile b/drivers/video/Makefile index af8b2b266e2..5a00438ce06 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -64,6 +64,7 @@ obj-$(CONFIG_VIDEO_LCD_RAYDIUM_RM68200) += raydium-rm68200.o obj-$(CONFIG_VIDEO_LCD_RENESAS_R61307) += renesas-r61307.o obj-$(CONFIG_VIDEO_LCD_RENESAS_R69328) += renesas-r69328.o obj-$(CONFIG_VIDEO_LCD_SAMSUNG_LTL106HL02) += samsung-ltl106hl02.o +obj-$(CONFIG_VIDEO_LCD_SHARP_LQ101R1SX01) += sharp-lq101r1sx01.o obj-$(CONFIG_VIDEO_LCD_SSD2828) += ssd2828.o obj-$(CONFIG_VIDEO_LCD_TDO_TL070WSH30) += tdo-tl070wsh30.o obj-$(CONFIG_VIDEO_MCDE_SIMPLE) += mcde_simple.o diff --git a/drivers/video/sharp-lq101r1sx01.c b/drivers/video/sharp-lq101r1sx01.c new file mode 100644 index 00000000000..5d8453fd796 --- /dev/null +++ b/drivers/video/sharp-lq101r1sx01.c @@ -0,0 +1,282 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Sharp LQ101R1SX01 DSI panel driver + * + * Copyright (C) 2014 NVIDIA Corporation + * Copyright (c) 2023 Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#include <backlight.h> +#include <dm.h> +#include <panel.h> +#include <log.h> +#include <mipi_dsi.h> +#include <linux/delay.h> +#include <power/regulator.h> + +struct sharp_lq101r1sx01_priv { + struct udevice *backlight; + struct udevice *panel_sec; + struct udevice *vcc; +}; + +static struct display_timing default_timing = { + .pixelclock.typ = 278000000, + .hactive.typ = 2560, + .hfront_porch.typ = 128, + .hback_porch.typ = 64, + .hsync_len.typ = 64, + .vactive.typ = 1600, + .vfront_porch.typ = 4, + .vback_porch.typ = 8, + .vsync_len.typ = 32, +}; + +static int sharp_lq101r1sx01_write(struct mipi_dsi_device *dsi, + u16 offset, u8 value) +{ + u8 payload[3] = { offset >> 8, offset & 0xff, value }; + int ret; + + ret = mipi_dsi_generic_write(dsi, payload, sizeof(payload)); + if (ret < 0) { + log_debug("%s: failed to write %02x to %04x: %zd\n", + __func__, value, offset, ret); + return ret; + } + + ret = mipi_dsi_dcs_nop(dsi); + if (ret < 0) { + log_debug("%s: failed to send DCS nop: %zd\n", + __func__, ret); + return ret; + } + + udelay(20); + + return 0; +} + +static int sharp_setup_symmetrical_split(struct mipi_dsi_device *left, + struct mipi_dsi_device *right, + struct display_timing *timing) +{ + int ret; + + ret = mipi_dsi_dcs_set_column_address(left, 0, + timing->hactive.typ / 2 - 1); + if (ret < 0) { + log_debug("%s: failed to set column address: %d\n", + __func__, ret); + return ret; + } + + ret = mipi_dsi_dcs_set_page_address(left, 0, timing->vactive.typ - 1); + if (ret < 0) { + log_debug("%s: failed to set page address: %d\n", + __func__, ret); + return ret; + } + + ret = mipi_dsi_dcs_set_column_address(right, timing->hactive.typ / 2, + timing->hactive.typ - 1); + if (ret < 0) { + log_debug("%s: failed to set column address: %d\n", + __func__, ret); + return ret; + } + + ret = mipi_dsi_dcs_set_page_address(right, 0, timing->vactive.typ - 1); + if (ret < 0) { + log_debug("%s: failed to set page address: %d\n", + __func__, ret); + return ret; + } + + return 0; +} + +static int sharp_lq101r1sx01_enable_backlight(struct udevice *dev) +{ + struct sharp_lq101r1sx01_priv *priv = dev_get_priv(dev); + + if (!priv->panel_sec) + return 0; + + struct mipi_dsi_panel_plat *plat = dev_get_plat(dev); + struct mipi_dsi_panel_plat *plat_sec = dev_get_plat(priv->panel_sec); + struct mipi_dsi_device *link1 = plat->device; + struct mipi_dsi_device *link2 = plat_sec->device; + int ret; + + ret = mipi_dsi_dcs_exit_sleep_mode(link1); + if (ret < 0) { + log_debug("%s: failed to exit sleep mode: %d\n", + __func__, ret); + return ret; + } + + /* set left-right mode */ + ret = sharp_lq101r1sx01_write(link1, 0x1000, 0x2a); + if (ret < 0) { + log_debug("%s: failed to set left-right mode: %d\n", + __func__, ret); + return ret; + } + + /* enable command mode */ + ret = sharp_lq101r1sx01_write(link1, 0x1001, 0x01); + if (ret < 0) { + log_debug("%s: failed to enable command mode: %d\n", + __func__, ret); + return ret; + } + + ret = mipi_dsi_dcs_set_pixel_format(link1, MIPI_DCS_PIXEL_FMT_24BIT); + if (ret < 0) { + log_debug("%s: failed to set pixel format: %d\n", + __func__, ret); + return ret; + } + + /* + * TODO: The device supports both left-right and even-odd split + * configurations, but this driver currently supports only the left- + * right split. To support a different mode a mechanism needs to be + * put in place to communicate the configuration back to the DSI host + * controller. + */ + ret = sharp_setup_symmetrical_split(link1, link2, &default_timing); + if (ret < 0) { + log_debug("%s: failed to set up symmetrical split: %d\n", + __func__, ret); + return ret; + } + + ret = mipi_dsi_dcs_set_display_on(link1); + if (ret < 0) { + log_debug("%s: failed to set panel on: %d\n", + __func__, ret); + return ret; + } + mdelay(20); + + return 0; +} + +static int sharp_lq101r1sx01_set_backlight(struct udevice *dev, int percent) +{ + struct sharp_lq101r1sx01_priv *priv = dev_get_priv(dev); + int ret; + + if (!priv->panel_sec) + return 0; + + ret = backlight_enable(priv->backlight); + if (ret) + return ret; + + return backlight_set_brightness(priv->backlight, percent); +} + +static int sharp_lq101r1sx01_timings(struct udevice *dev, + struct display_timing *timing) +{ + memcpy(timing, &default_timing, sizeof(*timing)); + return 0; +} + +static int sharp_lq101r1sx01_of_to_plat(struct udevice *dev) +{ + struct sharp_lq101r1sx01_priv *priv = dev_get_priv(dev); + int ret; + + /* If node has no link2 it is secondary panel */ + if (!dev_read_bool(dev, "link2")) + return 0; + + ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev, + "link2", &priv->panel_sec); + if (ret) { + log_debug("%s: cannot get secondary panel: ret = %d\n", + __func__, ret); + return ret; + } + + ret = uclass_get_device_by_phandle(UCLASS_PANEL_BACKLIGHT, dev, + "backlight", &priv->backlight); + if (ret) { + log_debug("%s: cannot get backlight: ret = %d\n", + __func__, ret); + return ret; + } + + ret = uclass_get_device_by_phandle(UCLASS_REGULATOR, dev, + "power-supply", &priv->vcc); + if (ret) { + log_debug("%s: cannot get power-supply: ret = %d\n", + __func__, ret); + return ret; + } + + return 0; +} + +static int sharp_lq101r1sx01_hw_init(struct udevice *dev) +{ + struct sharp_lq101r1sx01_priv *priv = dev_get_priv(dev); + int ret; + + if (!priv->panel_sec) + return 0; + + ret = regulator_set_enable_if_allowed(priv->vcc, 1); + if (ret) { + log_debug("%s: enabling power-supply failed (%d)\n", + __func__, ret); + return ret; + } + + /* + * According to the datasheet, the panel needs around 10 ms to fully + * power up. At least another 120 ms is required before exiting sleep + * mode to make sure the panel is ready. Throw in another 20 ms for + * good measure. + */ + mdelay(150); + + return 0; +} + +static int sharp_lq101r1sx01_probe(struct udevice *dev) +{ + struct mipi_dsi_panel_plat *plat = dev_get_plat(dev); + + /* fill characteristics of DSI data link */ + plat->lanes = 4; + plat->format = MIPI_DSI_FMT_RGB888; + + return sharp_lq101r1sx01_hw_init(dev); +} + +static const struct panel_ops sharp_lq101r1sx01_ops = { + .enable_backlight = sharp_lq101r1sx01_enable_backlight, + .set_backlight = sharp_lq101r1sx01_set_backlight, + .get_display_timing = sharp_lq101r1sx01_timings, +}; + +static const struct udevice_id sharp_lq101r1sx01_ids[] = { + { .compatible = "sharp,lq101r1sx01" }, + { } +}; + +U_BOOT_DRIVER(sharp_lq101r1sx01) = { + .name = "sharp_lq101r1sx01", + .id = UCLASS_PANEL, + .of_match = sharp_lq101r1sx01_ids, + .ops = &sharp_lq101r1sx01_ops, + .of_to_plat = sharp_lq101r1sx01_of_to_plat, + .probe = sharp_lq101r1sx01_probe, + .plat_auto = sizeof(struct mipi_dsi_panel_plat), + .priv_auto = sizeof(struct sharp_lq101r1sx01_priv), +}; diff --git a/drivers/video/tegra20/tegra-dc.c b/drivers/video/tegra20/tegra-dc.c index accabbf4dbb..d24aa375b39 100644 --- a/drivers/video/tegra20/tegra-dc.c +++ b/drivers/video/tegra20/tegra-dc.c @@ -26,8 +26,6 @@ #include "tegra-dc.h" -DECLARE_GLOBAL_DATA_PTR; - /* Holder of Tegra per-SOC DC differences */ struct tegra_dc_soc_info { bool has_timer; diff --git a/drivers/video/tegra20/tegra-dsi.c b/drivers/video/tegra20/tegra-dsi.c index 35a8e6c176b..6327266dd22 100644 --- a/drivers/video/tegra20/tegra-dsi.c +++ b/drivers/video/tegra20/tegra-dsi.c @@ -20,6 +20,7 @@ #include <asm/gpio.h> #include <asm/io.h> #include <asm/arch/clock.h> +#include <asm/arch-tegra/clk_rst.h> #include "tegra-dc.h" #include "tegra-dsi.h" @@ -50,6 +51,10 @@ struct tegra_dsi_priv { int host_fifo_depth; u32 version; + + /* for ganged-mode support */ + struct udevice *master; + struct udevice *slave; }; static void tegra_dc_enable_controller(struct udevice *dev) @@ -595,6 +600,17 @@ static void tegra_dsi_set_phy_timing(struct dsi_timing_reg *ptiming, writel(value, &ptiming->dsi_bta_timing); } +static void tegra_dsi_ganged_enable(struct udevice *dev, unsigned int start, + unsigned int size) +{ + struct tegra_dsi_priv *priv = dev_get_priv(dev); + struct dsi_ganged_mode_reg *ganged = &priv->dsi->ganged; + + writel(start, &ganged->ganged_mode_start); + writel(size << 16 | size, &ganged->ganged_mode_size); + writel(DSI_GANGED_MODE_CONTROL_ENABLE, &ganged->ganged_mode_ctrl); +} + static void tegra_dsi_configure(struct udevice *dev, unsigned long mode_flags) { @@ -679,9 +695,19 @@ static void tegra_dsi_configure(struct udevice *dev, writel(hact << 16 | hbp, &len->dsi_pkt_len_2_3); writel(hfp, &len->dsi_pkt_len_4_5); writel(0x0f0f << 16, &len->dsi_pkt_len_6_7); + + /* set SOL delay (for non-burst mode only) */ + writel(8 * mul / div, &misc->dsi_sol_delay); } else { - /* 1 byte (DCS command) + pixel data */ - value = 1 + timing->hactive.typ * mul / div; + if (priv->master || priv->slave) { + /* + * For ganged mode, assume symmetric left-right mode. + */ + value = 1 + (timing->hactive.typ / 2) * mul / div; + } else { + /* 1 byte (DCS command) + pixel data */ + value = 1 + timing->hactive.typ * mul / div; + } writel(0, &len->dsi_pkt_len_0_1); writel(value << 16, &len->dsi_pkt_len_2_3); @@ -691,10 +717,40 @@ static void tegra_dsi_configure(struct udevice *dev, value = MIPI_DCS_WRITE_MEMORY_START << 8 | MIPI_DCS_WRITE_MEMORY_CONTINUE; writel(value, &len->dsi_dcs_cmds); + + /* set SOL delay */ + if (priv->master || priv->slave) { + unsigned long delay, bclk, bclk_ganged; + unsigned int lanes = device->lanes; + unsigned long htotal = timing->hactive.typ + timing->hfront_porch.typ + + timing->hback_porch.typ + timing->hsync_len.typ; + + /* SOL to valid, valid to FIFO and FIFO write delay */ + delay = 4 + 4 + 2; + delay = DIV_ROUND_UP(delay * mul, div * lanes); + /* FIFO read delay */ + delay = delay + 6; + + bclk = DIV_ROUND_UP(htotal * mul, div * lanes); + bclk_ganged = DIV_ROUND_UP(bclk * lanes / 2, lanes); + value = bclk - bclk_ganged + delay + 20; + } else { + /* TODO: revisit for non-ganged mode */ + value = 8 * mul / div; + } + + writel(value, &misc->dsi_sol_delay); } - /* set SOL delay (for non-burst mode only) */ - writel(8 * mul / div, &misc->dsi_sol_delay); + if (priv->slave) { + /* + * TODO: Support modes other than symmetrical left-right + * split. + */ + tegra_dsi_ganged_enable(dev, 0, timing->hactive.typ / 2); + tegra_dsi_ganged_enable(priv->slave, timing->hactive.typ / 2, + timing->hactive.typ / 2); + } } static int tegra_dsi_encoder_enable(struct udevice *dev) @@ -774,6 +830,9 @@ static int tegra_dsi_encoder_enable(struct udevice *dev) value |= DSI_POWER_CONTROL_ENABLE; writel(value, &misc->dsi_pwr_ctrl); + if (priv->slave) + tegra_dsi_encoder_enable(priv->slave); + return 0; } @@ -803,6 +862,14 @@ static void tegra_dsi_init_clocks(struct udevice *dev) unsigned int mul, div; unsigned long bclk, plld; + if (!priv->slave) { + /* Change DSIB clock parent to match DSIA */ + struct clk_rst_ctlr *clkrst = + (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + + clrbits_le32(&clkrst->plld2.pll_base, BIT(25)); /* DSIB_CLK_SRC */ + } + tegra_dsi_get_muldiv(device->format, &mul, &div); bclk = (priv->timing.pixelclock.typ * mul) / @@ -854,6 +921,24 @@ static void tegra_dsi_init_clocks(struct udevice *dev) reset_set_enable(priv->dsi_clk, 0); } +static int tegra_dsi_ganged_probe(struct udevice *dev) +{ + struct tegra_dsi_priv *mpriv = dev_get_priv(dev); + struct udevice *gangster; + + uclass_get_device_by_phandle(UCLASS_PANEL, dev, + "nvidia,ganged-mode", &gangster); + if (gangster) { + /* Ganged mode is set */ + struct tegra_dsi_priv *spriv = dev_get_priv(gangster); + + mpriv->slave = gangster; + spriv->master = dev; + } + + return 0; +} + static int tegra_dsi_bridge_probe(struct udevice *dev) { struct tegra_dsi_priv *priv = dev_get_priv(dev); @@ -873,6 +958,8 @@ static int tegra_dsi_bridge_probe(struct udevice *dev) priv->video_fifo_depth = 1920; priv->host_fifo_depth = 64; + tegra_dsi_ganged_probe(dev); + ret = reset_get_by_name(dev, "dsi", &reset_ctl); if (ret) { log_debug("%s: reset_get_by_name() failed: %d\n", diff --git a/drivers/video/tegra20/tegra-dsi.h b/drivers/video/tegra20/tegra-dsi.h index 69dac4bd1b8..683c5e31a34 100644 --- a/drivers/video/tegra20/tegra-dsi.h +++ b/drivers/video/tegra20/tegra-dsi.h @@ -98,9 +98,9 @@ struct dsi_timeout_reg { uint dsi_to_tally; /* _DSI_TO_TALLY_0 */ }; -/* DSI PAD control register 0x04b ~ 0x04e */ +/* DSI PAD control register 0x04b ~ 0x052 */ struct dsi_pad_ctrl_reg { - /* Address 0x04b ~ 0x04e */ + /* Address 0x04b ~ 0x052 */ uint pad_ctrl; /* _PAD_CONTROL_0 */ uint pad_ctrl_cd; /* _PAD_CONTROL_CD_0 */ uint pad_cd_status; /* _PAD_CD_STATUS_0 */ @@ -111,6 +111,14 @@ struct dsi_pad_ctrl_reg { uint pad_ctrl_4; /* _PAD_CONTROL_4 */ }; +/* DSI ganged mode register 0x053 ~ 0x04e */ +struct dsi_ganged_mode_reg { + /* Address 0x053 ~ 0x055 */ + uint ganged_mode_ctrl; /* _DSI_GANGED_MODE_CONTROL_0 */ + uint ganged_mode_start; /* _DSI_GANGED_MODE_START_0 */ + uint ganged_mode_size; /* _DSI_GANGED_MODE_SIZE_0 */ +}; + /* Display Serial Interface (DSI_) regs */ struct dsi_ctlr { struct dsi_syncpt_reg syncpt; /* SYNCPT register 0x000 ~ 0x002 */ @@ -133,6 +141,7 @@ struct dsi_ctlr { uint reserved5[4]; /* reserved_5[4] */ struct dsi_pad_ctrl_reg pad; /* PAD registers 0x04b ~ 0x04e */ + struct dsi_ganged_mode_reg ganged; /* GANGED registers 0x053 ~ 0x055 */ }; #define DSI_POWER_CONTROL_ENABLE BIT(0) @@ -202,6 +211,8 @@ struct dsi_ctlr { #define DSI_PAD_PREEMP_PD(x) (((x) & 0x3) << 4) #define DSI_PAD_PREEMP_PU(x) (((x) & 0x3) << 0) +#define DSI_GANGED_MODE_CONTROL_ENABLE BIT(0) + /* * pixel format as used in the DSI_CONTROL_FORMAT field */ |