diff options
Diffstat (limited to 'drivers/video')
| -rw-r--r-- | drivers/video/bridge/dp501.c | 2 | ||||
| -rw-r--r-- | drivers/video/hx8238d.c | 2 | ||||
| -rw-r--r-- | drivers/video/nexell_display.c | 1 | ||||
| -rw-r--r-- | drivers/video/zynqmp/zynqmp_dpsub.h | 2 |
4 files changed, 4 insertions, 3 deletions
diff --git a/drivers/video/bridge/dp501.c b/drivers/video/bridge/dp501.c index 9937cfe095b..0ad589304aa 100644 --- a/drivers/video/bridge/dp501.c +++ b/drivers/video/bridge/dp501.c @@ -99,7 +99,7 @@ #define SD_DB15 0x4F /* Aux Channel and PCS */ -#define DPCD_REV 0X50 +#define DPCD_REV 0x50 #define MAX_LINK_RATE 0x51 #define MAX_LANE_COUNT 0x52 #define MAX_DOWNSPREAD 0x53 diff --git a/drivers/video/hx8238d.c b/drivers/video/hx8238d.c index 2491a32810e..f0220e4cc07 100644 --- a/drivers/video/hx8238d.c +++ b/drivers/video/hx8238d.c @@ -22,7 +22,7 @@ DECLARE_GLOBAL_DATA_PTR; #define HX8238D_OUTPUT_CTRL_ADDR 0x01 #define HX8238D_LCD_AC_CTRL_ADDR 0x02 #define HX8238D_POWER_CTRL_1_ADDR 0x03 -#define HX8238D_DATA_CLR_CTRL_ADDR 0X04 +#define HX8238D_DATA_CLR_CTRL_ADDR 0x04 #define HX8238D_FUNCTION_CTRL_ADDR 0x05 #define HX8238D_LED_CTRL_ADDR 0x08 #define HX8238D_CONT_BRIGHT_CTRL_ADDR 0x0A diff --git a/drivers/video/nexell_display.c b/drivers/video/nexell_display.c index 7bda33fb16e..ea3776258a0 100644 --- a/drivers/video/nexell_display.c +++ b/drivers/video/nexell_display.c @@ -10,6 +10,7 @@ #include <config.h> #include <command.h> #include <dm.h> +#include <env.h> #include <mapmem.h> #include <malloc.h> #include <linux/compat.h> diff --git a/drivers/video/zynqmp/zynqmp_dpsub.h b/drivers/video/zynqmp/zynqmp_dpsub.h index 7d2737e31aa..dc549559cae 100644 --- a/drivers/video/zynqmp/zynqmp_dpsub.h +++ b/drivers/video/zynqmp/zynqmp_dpsub.h @@ -553,7 +553,7 @@ struct zynqmp_dpsub_priv { #define DPDMA_DESCRIPTOR_LINE_SIZE_STRIDE_SHIFT 18 #define DPDMA_DESCRIPTOR_SRC_ADDR_WIDTH 32U #define DPDMA_DESCRIPTOR_ADDR_EXT_SRC_ADDR_EXT_SHIFT 16U -#define DPDMA_CH0_DSCR_STRT_ADDR 0X0204U +#define DPDMA_CH0_DSCR_STRT_ADDR 0x0204U #define DPDMA_CH_OFFSET 0x100U #define DPDMA_CH0_CNTL 0x0218U #define DPDMA_CH3_CNTL 0x0518U |