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-rw-r--r--drivers/Makefile39
-rw-r--r--drivers/clk/Kconfig12
-rw-r--r--drivers/clk/Makefile2
-rw-r--r--drivers/clk/rockchip/clk_rk3036.c9
-rw-r--r--drivers/clk/rockchip/clk_rk3188.c15
-rw-r--r--drivers/clk/rockchip/clk_rk322x.c14
-rw-r--r--drivers/clk/rockchip/clk_rk3288.c12
-rw-r--r--drivers/clk/rockchip/clk_rk3328.c9
-rw-r--r--drivers/clk/rockchip/clk_rk3368.c306
-rw-r--r--drivers/clk/rockchip/clk_rk3399.c27
-rw-r--r--drivers/clk/rockchip/clk_rv1108.c3
-rw-r--r--drivers/core/Kconfig23
-rw-r--r--drivers/core/Makefile4
-rw-r--r--drivers/net/gmac_rockchip.c78
-rw-r--r--drivers/pinctrl/rockchip/pinctrl_rk3368.c577
-rw-r--r--drivers/ram/Kconfig11
-rw-r--r--drivers/ram/Makefile2
-rw-r--r--drivers/ram/rockchip/Makefile7
-rw-r--r--drivers/ram/rockchip/dmc-rk3368.c1007
-rw-r--r--drivers/spi/rk_spi.c9
-rw-r--r--drivers/timer/Kconfig25
-rw-r--r--drivers/timer/Makefile3
-rw-r--r--drivers/timer/rockchip_timer.c107
-rw-r--r--drivers/timer/timer-uclass.c8
24 files changed, 2190 insertions, 119 deletions
diff --git a/drivers/Makefile b/drivers/Makefile
index 0cbfa5d07b8..dab5c182c2c 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -2,33 +2,35 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_$(SPL_TPL_)DM) += core/
-obj-$(CONFIG_$(SPL_)CLK) += clk/
-obj-$(CONFIG_$(SPL_)LED) += led/
-obj-$(CONFIG_$(SPL_)PHY) += phy/
-obj-$(CONFIG_$(SPL_)PINCTRL) += pinctrl/
-obj-$(CONFIG_$(SPL_)RAM) += ram/
+obj-$(CONFIG_$(SPL_TPL_)CLK) += clk/
+obj-$(CONFIG_$(SPL_TPL_)DM) += core/
+obj-$(CONFIG_$(SPL_TPL_)DRIVERS_MISC_SUPPORT) += misc/ sysreset/ firmware/
+obj-$(CONFIG_$(SPL_TPL_)I2C_SUPPORT) += i2c/
+obj-$(CONFIG_$(SPL_TPL_)LED) += led/
+obj-$(CONFIG_$(SPL_TPL_)MMC_SUPPORT) += mmc/
+obj-$(CONFIG_$(SPL_TPL_)NAND_SUPPORT) += mtd/nand/
+obj-$(CONFIG_$(SPL_TPL_)PHY) += phy/
+obj-$(CONFIG_$(SPL_TPL_)PINCTRL) += pinctrl/
+obj-$(CONFIG_$(SPL_TPL_)RAM) += ram/
+obj-$(CONFIG_$(SPL_TPL_)SERIAL_SUPPORT) += serial/
+obj-$(CONFIG_$(SPL_TPL_)SPI_FLASH_SUPPORT) += mtd/spi/
+obj-$(CONFIG_$(SPL_TPL_)SPI_SUPPORT) += spi/
+obj-$(CONFIG_$(SPL_TPL_)TIMER) += timer/
+ifndef CONFIG_TPL_BUILD
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_SPL_CPU_SUPPORT) += cpu/
obj-$(CONFIG_SPL_CRYPTO_SUPPORT) += crypto/
-obj-$(CONFIG_SPL_I2C_SUPPORT) += i2c/
obj-$(CONFIG_SPL_GPIO_SUPPORT) += gpio/
-obj-$(CONFIG_SPL_MMC_SUPPORT) += mmc/
obj-$(CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT) += ddr/fsl/
obj-$(CONFIG_ARMADA_38X) += ddr/marvell/a38x/
obj-$(CONFIG_ARMADA_XP) += ddr/marvell/axp/
obj-$(CONFIG_ALTERA_SDRAM) += ddr/altera/
-obj-$(CONFIG_SPL_SERIAL_SUPPORT) += serial/
-obj-$(CONFIG_SPL_SPI_SUPPORT) += spi/
obj-$(CONFIG_SPL_POWER_SUPPORT) += power/ power/pmic/
obj-$(CONFIG_SPL_POWER_SUPPORT) += power/regulator/
-obj-$(CONFIG_SPL_DRIVERS_MISC_SUPPORT) += misc/ sysreset/ firmware/
obj-$(CONFIG_SPL_MTD_SUPPORT) += mtd/
-obj-$(CONFIG_SPL_NAND_SUPPORT) += mtd/nand/
obj-$(CONFIG_SPL_ONENAND_SUPPORT) += mtd/onenand/
-obj-$(CONFIG_SPL_SPI_FLASH_SUPPORT) += mtd/spi/
obj-$(CONFIG_SPL_UBI) += mtd/ubispl/
obj-$(CONFIG_SPL_DMA_SUPPORT) += dma/
obj-$(CONFIG_SPL_ETH_SUPPORT) += net/
@@ -37,7 +39,6 @@ obj-$(CONFIG_SPL_USBETH_SUPPORT) += net/phy/
obj-$(CONFIG_SPL_PCI_SUPPORT) += pci/
obj-$(CONFIG_SPL_PCH_SUPPORT) += pch/
obj-$(CONFIG_SPL_RTC_SUPPORT) += rtc/
-obj-$(CONFIG_SPL_TIMER_SUPPORT) += timer/
obj-$(CONFIG_SPL_MUSB_NEW_SUPPORT) += usb/musb-new/
obj-$(CONFIG_SPL_USB_GADGET_SUPPORT) += usb/gadget/
obj-$(CONFIG_SPL_USB_GADGET_SUPPORT) += usb/gadget/udc/
@@ -49,18 +50,13 @@ obj-$(CONFIG_SPL_SATA_SUPPORT) += ata/ scsi/
obj-$(CONFIG_SPL_USB_HOST_SUPPORT) += block/
obj-$(CONFIG_SPL_MMC_SUPPORT) += block/
obj-$(CONFIG_SPL_FPGA_SUPPORT) += fpga/
+
+endif
endif
ifdef CONFIG_TPL_BUILD
-obj-$(CONFIG_TPL_I2C_SUPPORT) += i2c/
-obj-$(CONFIG_TPL_DRIVERS_MISC_SUPPORT) += misc/ sysreset/ firmware/
-obj-$(CONFIG_TPL_MMC_SUPPORT) += mmc/
obj-$(CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT) += ddr/fsl/
-obj-$(CONFIG_TPL_NAND_SUPPORT) += mtd/nand/
-obj-$(CONFIG_TPL_SERIAL_SUPPORT) += serial/
-obj-$(CONFIG_TPL_SPI_FLASH_SUPPORT) += mtd/spi/
-obj-$(CONFIG_TPL_SPI_SUPPORT) += spi/
endif
@@ -88,7 +84,6 @@ obj-y += scsi/
obj-y += sound/
obj-y += spmi/
obj-y += sysreset/
-obj-y += timer/
obj-y += tpm/
obj-y += video/
obj-y += watchdog/
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 60bd706fa2b..7765148876d 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -12,7 +12,7 @@ config CLK
config SPL_CLK
bool "Enable clock support in SPL"
- depends on CLK
+ depends on CLK && SPL_DM
help
The clock subsystem adds a small amount of overhead to the image.
If this is acceptable and you have a need to use clock drivers in
@@ -20,6 +20,16 @@ config SPL_CLK
setting up clocks within SPL, and allows the same drivers to be
used as U-Boot proper.
+config TPL_CLK
+ bool "Enable clock support in TPL"
+ depends on CLK && TPL_DM
+ help
+ The clock subsystem adds a small amount of overhead to the image.
+ If this is acceptable and you have a need to use clock drivers in
+ SPL, enable this option. It might provide a cleaner interface to
+ setting up clocks within TPL, and allows the same drivers to be
+ used as U-Boot proper.
+
config CLK_BCM6345
bool "Clock controller driver for BCM6345"
depends on CLK && ARCH_BMIPS
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 159f285f9a2..b7735933be5 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -5,7 +5,7 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_CLK) += clk-uclass.o clk_fixed_rate.o
+obj-$(CONFIG_$(SPL_TPL_)CLK) += clk-uclass.o clk_fixed_rate.o
obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
obj-$(CONFIG_SANDBOX) += clk_sandbox.o
obj-$(CONFIG_SANDBOX) += clk_sandbox_test.o
diff --git a/drivers/clk/rockchip/clk_rk3036.c b/drivers/clk/rockchip/clk_rk3036.c
index 5ecf5129d81..83f4ae6ca39 100644
--- a/drivers/clk/rockchip/clk_rk3036.c
+++ b/drivers/clk/rockchip/clk_rk3036.c
@@ -235,7 +235,7 @@ static ulong rockchip_mmc_get_clk(struct rk3036_cru *cru, uint clk_general_rate,
}
src_rate = mux == EMMC_SEL_24M ? OSC_HZ : clk_general_rate;
- return DIV_TO_RATE(src_rate, div);
+ return DIV_TO_RATE(src_rate, div) / 2;
}
static ulong rockchip_mmc_set_clk(struct rk3036_cru *cru, uint clk_general_rate,
@@ -247,10 +247,11 @@ static ulong rockchip_mmc_set_clk(struct rk3036_cru *cru, uint clk_general_rate,
debug("%s: clk_general_rate=%u\n", __func__, clk_general_rate);
/* mmc clock auto divide 2 in internal */
- src_clk_div = (clk_general_rate / 2 + freq - 1) / freq;
+ src_clk_div = DIV_ROUND_UP(clk_general_rate / 2, freq);
- if (src_clk_div > 0x7f) {
- src_clk_div = (OSC_HZ / 2 + freq - 1) / freq;
+ if (src_clk_div > 128) {
+ src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq);
+ assert(src_clk_div - 1 < 128);
mux = EMMC_SEL_24M;
} else {
mux = EMMC_SEL_GPLL;
diff --git a/drivers/clk/rockchip/clk_rk3188.c b/drivers/clk/rockchip/clk_rk3188.c
index 6f303328783..8c2c9bc1d87 100644
--- a/drivers/clk/rockchip/clk_rk3188.c
+++ b/drivers/clk/rockchip/clk_rk3188.c
@@ -71,9 +71,6 @@ enum {
SOCSTS_GPLL_LOCK = 1 << 8,
};
-#define RATE_TO_DIV(input_rate, output_rate) \
- ((input_rate) / (output_rate) - 1);
-
#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
#define PLL_DIVISORS(hz, _nr, _no) {\
@@ -287,7 +284,7 @@ static ulong rockchip_mmc_get_clk(struct rk3188_cru *cru, uint gclk_rate,
return -EINVAL;
}
- return DIV_TO_RATE(gclk_rate, div);
+ return DIV_TO_RATE(gclk_rate, div) / 2;
}
static ulong rockchip_mmc_set_clk(struct rk3188_cru *cru, uint gclk_rate,
@@ -296,7 +293,8 @@ static ulong rockchip_mmc_set_clk(struct rk3188_cru *cru, uint gclk_rate,
int src_clk_div;
debug("%s: gclk_rate=%u\n", __func__, gclk_rate);
- src_clk_div = RATE_TO_DIV(gclk_rate, freq);
+ /* mmc clock defaulg div 2 internal, need provide double in cru */
+ src_clk_div = DIV_ROUND_UP(gclk_rate / 2, freq) - 1;
assert(src_clk_div <= 0x3f);
switch (periph) {
@@ -350,8 +348,9 @@ static ulong rockchip_spi_get_clk(struct rk3188_cru *cru, uint gclk_rate,
static ulong rockchip_spi_set_clk(struct rk3188_cru *cru, uint gclk_rate,
int periph, uint freq)
{
- int src_clk_div = RATE_TO_DIV(gclk_rate, freq);
+ int src_clk_div = DIV_ROUND_UP(gclk_rate, freq) - 1;
+ assert(src_clk_div < 128);
switch (periph) {
case SCLK_SPI0:
assert(src_clk_div <= SPI0_DIV_MASK);
@@ -400,8 +399,8 @@ static void rkclk_init(struct rk3188_cru *cru, struct rk3188_grf *grf,
* reparent aclk_cpu_pre from apll to gpll
* set up dependent divisors for PCLK/HCLK and ACLK clocks.
*/
- aclk_div = RATE_TO_DIV(GPLL_HZ, CPU_ACLK_HZ);
- assert((aclk_div + 1) * CPU_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
+ aclk_div = DIV_ROUND_UP(GPLL_HZ, CPU_ACLK_HZ) - 1;
+ assert((aclk_div + 1) * CPU_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);
rk_clrsetreg(&cru->cru_clksel_con[0],
CPU_ACLK_PLL_MASK << CPU_ACLK_PLL_SHIFT |
diff --git a/drivers/clk/rockchip/clk_rk322x.c b/drivers/clk/rockchip/clk_rk322x.c
index fdeb816e231..d7f6a3c313e 100644
--- a/drivers/clk/rockchip/clk_rk322x.c
+++ b/drivers/clk/rockchip/clk_rk322x.c
@@ -26,9 +26,6 @@ enum {
OUTPUT_MIN_HZ = 24 * 1000000,
};
-#define RATE_TO_DIV(input_rate, output_rate) \
- ((input_rate) / (output_rate) - 1);
-
#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
#define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
@@ -239,7 +236,7 @@ static ulong rockchip_mmc_get_clk(struct rk322x_cru *cru, uint clk_general_rate,
}
src_rate = mux == EMMC_SEL_24M ? OSC_HZ : clk_general_rate;
- return DIV_TO_RATE(src_rate, div);
+ return DIV_TO_RATE(src_rate, div) / 2;
}
static ulong rockchip_mmc_set_clk(struct rk322x_cru *cru, uint clk_general_rate,
@@ -250,11 +247,12 @@ static ulong rockchip_mmc_set_clk(struct rk322x_cru *cru, uint clk_general_rate,
debug("%s: clk_general_rate=%u\n", __func__, clk_general_rate);
- /* mmc clock auto divide 2 in internal */
- src_clk_div = (clk_general_rate / 2 + freq - 1) / freq;
+ /* mmc clock defaulg div 2 internal, need provide double in cru */
+ src_clk_div = DIV_ROUND_UP(clk_general_rate / 2, freq);
- if (src_clk_div > 0x7f) {
- src_clk_div = (OSC_HZ / 2 + freq - 1) / freq;
+ if (src_clk_div > 128) {
+ src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq);
+ assert(src_clk_div - 1 < 128);
mux = EMMC_SEL_24M;
} else {
mux = EMMC_SEL_GPLL;
diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c
index 792ee76509f..478195b10b0 100644
--- a/drivers/clk/rockchip/clk_rk3288.c
+++ b/drivers/clk/rockchip/clk_rk3288.c
@@ -118,9 +118,6 @@ enum {
SOCSTS_NPLL_LOCK = 1 << 9,
};
-#define RATE_TO_DIV(input_rate, output_rate) \
- ((input_rate) / (output_rate) - 1);
-
#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
#define PLL_DIVISORS(hz, _nr, _no) {\
@@ -530,10 +527,12 @@ static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate,
int mux;
debug("%s: gclk_rate=%u\n", __func__, gclk_rate);
- src_clk_div = RATE_TO_DIV(gclk_rate, freq);
+ /* mmc clock default div 2 internal, need provide double in cru */
+ src_clk_div = DIV_ROUND_UP(gclk_rate / 2, freq);
if (src_clk_div > 0x3f) {
- src_clk_div = RATE_TO_DIV(OSC_HZ, freq);
+ src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq);
+ assert(src_clk_div < 0x40);
mux = EMMC_PLL_SELECT_24MHZ;
assert((int)EMMC_PLL_SELECT_24MHZ ==
(int)MMC0_PLL_SELECT_24MHZ);
@@ -607,7 +606,8 @@ static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint gclk_rate,
int src_clk_div;
debug("%s: clk_general_rate=%u\n", __func__, gclk_rate);
- src_clk_div = RATE_TO_DIV(gclk_rate, freq);
+ src_clk_div = DIV_ROUND_UP(gclk_rate, freq) - 1;
+ assert(src_clk_div < 128);
switch (periph) {
case SCLK_SPI0:
rk_clrsetreg(&cru->cru_clksel_con[25],
diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c
index 2065a8a65b9..c3a6650de03 100644
--- a/drivers/clk/rockchip/clk_rk3328.c
+++ b/drivers/clk/rockchip/clk_rk3328.c
@@ -412,9 +412,9 @@ static ulong rk3328_mmc_get_clk(struct rk3328_cru *cru, uint clk_id)
if ((con & CLK_EMMC_PLL_MASK) >> CLK_EMMC_PLL_SHIFT
== CLK_EMMC_PLL_SEL_24M)
- return DIV_TO_RATE(OSC_HZ, div);
+ return DIV_TO_RATE(OSC_HZ, div) / 2;
else
- return DIV_TO_RATE(GPLL_HZ, div);
+ return DIV_TO_RATE(GPLL_HZ, div) / 2;
}
static ulong rk3328_mmc_set_clk(struct rk3328_cru *cru,
@@ -436,11 +436,12 @@ static ulong rk3328_mmc_set_clk(struct rk3328_cru *cru,
return -EINVAL;
}
/* Select clk_sdmmc/emmc source from GPLL by default */
- src_clk_div = GPLL_HZ / set_rate;
+ /* mmc clock defaulg div 2 internal, need provide double in cru */
+ src_clk_div = DIV_ROUND_UP(GPLL_HZ / 2, set_rate);
if (src_clk_div > 127) {
/* use 24MHz source for 400KHz clock */
- src_clk_div = OSC_HZ / set_rate;
+ src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate);
rk_clrsetreg(&cru->clksel_con[con_id],
CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
CLK_EMMC_PLL_SEL_24M << CLK_EMMC_PLL_SHIFT |
diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c
index e1d9aeb8e54..2be1f572d72 100644
--- a/drivers/clk/rockchip/clk_rk3368.c
+++ b/drivers/clk/rockchip/clk_rk3368.c
@@ -1,13 +1,16 @@
/*
* (C) Copyright 2017 Rockchip Electronics Co., Ltd
* Author: Andy Yan <andy.yan@rock-chips.com>
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
* SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
#include <clk-uclass.h>
#include <dm.h>
+#include <dt-structs.h>
#include <errno.h>
+#include <mapmem.h>
#include <syscon.h>
#include <asm/arch/clock.h>
#include <asm/arch/cru_rk3368.h>
@@ -18,6 +21,12 @@
DECLARE_GLOBAL_DATA_PTR;
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+struct rk3368_clk_plat {
+ struct dtd_rockchip_rk3368_cru dtd;
+};
+#endif
+
struct pll_div {
u32 nr;
u32 nf;
@@ -30,9 +39,6 @@ struct pll_div {
#define GPLL_HZ (576 * 1000 * 1000)
#define CPLL_HZ (400 * 1000 * 1000)
-#define RATE_TO_DIV(input_rate, output_rate) \
- ((input_rate) / (output_rate) - 1);
-
#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
#define PLL_DIVISORS(hz, _nr, _no) { \
@@ -41,10 +47,16 @@ struct pll_div {
(_nr * _no) == hz, #hz "Hz cannot be hit with PLL " \
"divisors on line " __stringify(__LINE__));
+#if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)
static const struct pll_div apll_l_init_cfg = PLL_DIVISORS(APLL_L_HZ, 12, 2);
static const struct pll_div apll_b_init_cfg = PLL_DIVISORS(APLL_B_HZ, 1, 2);
+#if !defined(CONFIG_TPL_BUILD)
static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 2);
static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 6);
+#endif
+#endif
+
+static ulong rk3368_clk_get_rate(struct clk *clk);
/* Get pll rate by id */
static uint32_t rkclk_pll_get_rate(struct rk3368_cru *cru,
@@ -73,8 +85,9 @@ static uint32_t rkclk_pll_get_rate(struct rk3368_cru *cru,
}
}
+#if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)
static int rkclk_set_pll(struct rk3368_cru *cru, enum rk3368_pll_id pll_id,
- const struct pll_div *div, bool has_bwadj)
+ const struct pll_div *div)
{
struct rk3368_pll *pll = &cru->pll[pll_id];
/* All PLLs have same VCO and output frequency range restrictions*/
@@ -92,6 +105,12 @@ static int rkclk_set_pll(struct rk3368_cru *cru, enum rk3368_pll_id pll_id,
((div->nr - 1) << PLL_NR_SHIFT) |
((div->no - 1) << PLL_OD_SHIFT));
writel((div->nf - 1) << PLL_NF_SHIFT, &pll->con1);
+ /*
+ * BWADJ should be set to NF / 2 to ensure the nominal bandwidth.
+ * Compare the RK3368 TRM, section "3.6.4 PLL Bandwidth Adjustment".
+ */
+ clrsetbits_le32(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1);
+
udelay(10);
/* return from reset */
@@ -106,15 +125,23 @@ static int rkclk_set_pll(struct rk3368_cru *cru, enum rk3368_pll_id pll_id,
return 0;
}
+#endif
+#if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)
static void rkclk_init(struct rk3368_cru *cru)
{
u32 apllb, aplll, dpll, cpll, gpll;
- rkclk_set_pll(cru, APLLB, &apll_b_init_cfg, false);
- rkclk_set_pll(cru, APLLL, &apll_l_init_cfg, false);
- rkclk_set_pll(cru, GPLL, &gpll_init_cfg, false);
- rkclk_set_pll(cru, CPLL, &cpll_init_cfg, false);
+ rkclk_set_pll(cru, APLLB, &apll_b_init_cfg);
+ rkclk_set_pll(cru, APLLL, &apll_l_init_cfg);
+#if !defined(CONFIG_TPL_BUILD)
+ /*
+ * If we plan to return to the boot ROM, we can't increase the
+ * GPLL rate from the SPL stage.
+ */
+ rkclk_set_pll(cru, GPLL, &gpll_init_cfg);
+ rkclk_set_pll(cru, CPLL, &cpll_init_cfg);
+#endif
apllb = rkclk_pll_get_rate(cru, APLLB);
aplll = rkclk_pll_get_rate(cru, APLLL);
@@ -125,17 +152,19 @@ static void rkclk_init(struct rk3368_cru *cru)
debug("%s apllb(%d) apll(%d) dpll(%d) cpll(%d) gpll(%d)\n",
__func__, apllb, aplll, dpll, cpll, gpll);
}
+#endif
+#if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC_SUPPORT)
static ulong rk3368_mmc_get_clk(struct rk3368_cru *cru, uint clk_id)
{
u32 div, con, con_id, rate;
u32 pll_rate;
switch (clk_id) {
- case SCLK_SDMMC:
+ case HCLK_SDMMC:
con_id = 50;
break;
- case SCLK_EMMC:
+ case HCLK_EMMC:
con_id = 51;
break;
case SCLK_SDIO0:
@@ -146,7 +175,7 @@ static ulong rk3368_mmc_get_clk(struct rk3368_cru *cru, uint clk_id)
}
con = readl(&cru->clksel_con[con_id]);
- switch ((con & MMC_PLL_SEL_MASK) >> MMC_PLL_SEL_SHIFT) {
+ switch (con & MMC_PLL_SEL_MASK) {
case MMC_PLL_SEL_GPLL:
pll_rate = rkclk_pll_get_rate(cru, GPLL);
break;
@@ -154,6 +183,8 @@ static ulong rk3368_mmc_get_clk(struct rk3368_cru *cru, uint clk_id)
pll_rate = OSC_HZ;
break;
case MMC_PLL_SEL_CPLL:
+ pll_rate = rkclk_pll_get_rate(cru, CPLL);
+ break;
case MMC_PLL_SEL_USBPHY_480M:
default:
return -EINVAL;
@@ -161,23 +192,76 @@ static ulong rk3368_mmc_get_clk(struct rk3368_cru *cru, uint clk_id)
div = (con & MMC_CLK_DIV_MASK) >> MMC_CLK_DIV_SHIFT;
rate = DIV_TO_RATE(pll_rate, div);
+ debug("%s: raw rate %d (post-divide by 2)\n", __func__, rate);
return rate >> 1;
}
-static ulong rk3368_mmc_set_clk(struct rk3368_cru *cru,
- ulong clk_id, ulong rate)
+static ulong rk3368_mmc_find_best_rate_and_parent(struct clk *clk,
+ ulong rate,
+ u32 *best_mux,
+ u32 *best_div)
+{
+ int i;
+ ulong best_rate = 0;
+ const ulong MHz = 1000000;
+ const struct {
+ u32 mux;
+ ulong rate;
+ } parents[] = {
+ { .mux = MMC_PLL_SEL_CPLL, .rate = CPLL_HZ },
+ { .mux = MMC_PLL_SEL_GPLL, .rate = GPLL_HZ },
+ { .mux = MMC_PLL_SEL_24M, .rate = 24 * MHz }
+ };
+
+ debug("%s: target rate %ld\n", __func__, rate);
+ for (i = 0; i < ARRAY_SIZE(parents); ++i) {
+ /*
+ * Find the largest rate no larger than the target-rate for
+ * the current parent.
+ */
+ ulong parent_rate = parents[i].rate;
+ u32 div = DIV_ROUND_UP(parent_rate, rate);
+ u32 adj_div = div;
+ ulong new_rate = parent_rate / adj_div;
+
+ debug("%s: rate %ld, parent-mux %d, parent-rate %ld, div %d\n",
+ __func__, rate, parents[i].mux, parents[i].rate, div);
+
+ /* Skip, if not representable */
+ if ((div - 1) > MMC_CLK_DIV_MASK)
+ continue;
+
+ /* Skip, if we already have a better (or equal) solution */
+ if (new_rate <= best_rate)
+ continue;
+
+ /* This is our new best rate. */
+ best_rate = new_rate;
+ *best_mux = parents[i].mux;
+ *best_div = div - 1;
+ }
+
+ debug("%s: best_mux = %x, best_div = %d, best_rate = %ld\n",
+ __func__, *best_mux, *best_div, best_rate);
+
+ return best_rate;
+}
+
+static ulong rk3368_mmc_set_clk(struct clk *clk, ulong rate)
{
- u32 div;
- u32 con_id;
- u32 gpll_rate = rkclk_pll_get_rate(cru, GPLL);
+ struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
+ struct rk3368_cru *cru = priv->cru;
+ ulong clk_id = clk->id;
+ u32 con_id, mux = 0, div = 0;
- div = RATE_TO_DIV(gpll_rate, rate << 1);
+ /* Find the best parent and rate */
+ rk3368_mmc_find_best_rate_and_parent(clk, rate << 1, &mux, &div);
switch (clk_id) {
- case SCLK_SDMMC:
+ case HCLK_SDMMC:
con_id = 50;
break;
- case SCLK_EMMC:
+ case HCLK_EMMC:
con_id = 51;
break;
case SCLK_SDIO0:
@@ -187,33 +271,154 @@ static ulong rk3368_mmc_set_clk(struct rk3368_cru *cru,
return -EINVAL;
}
- if (div > 0x3f) {
- div = RATE_TO_DIV(OSC_HZ, rate);
- rk_clrsetreg(&cru->clksel_con[con_id],
- MMC_PLL_SEL_MASK | MMC_CLK_DIV_MASK,
- (MMC_PLL_SEL_24M << MMC_PLL_SEL_SHIFT) |
- (div << MMC_CLK_DIV_SHIFT));
- } else {
- rk_clrsetreg(&cru->clksel_con[con_id],
- MMC_PLL_SEL_MASK | MMC_CLK_DIV_MASK,
- (MMC_PLL_SEL_GPLL << MMC_PLL_SEL_SHIFT) |
- div << MMC_CLK_DIV_SHIFT);
- }
+ rk_clrsetreg(&cru->clksel_con[con_id],
+ MMC_PLL_SEL_MASK | MMC_CLK_DIV_MASK,
+ mux | div);
return rk3368_mmc_get_clk(cru, clk_id);
}
+#endif
+
+#if IS_ENABLED(CONFIG_TPL_BUILD)
+static ulong rk3368_ddr_set_clk(struct rk3368_cru *cru, ulong set_rate)
+{
+ const struct pll_div *dpll_cfg = NULL;
+ const ulong MHz = 1000000;
+
+ /* Fout = ((Fin /NR) * NF )/ NO */
+ static const struct pll_div dpll_1200 = PLL_DIVISORS(1200 * MHz, 1, 1);
+ static const struct pll_div dpll_1332 = PLL_DIVISORS(1332 * MHz, 2, 1);
+ static const struct pll_div dpll_1600 = PLL_DIVISORS(1600 * MHz, 3, 2);
+
+ switch (set_rate) {
+ case 1200*MHz:
+ dpll_cfg = &dpll_1200;
+ break;
+ case 1332*MHz:
+ dpll_cfg = &dpll_1332;
+ break;
+ case 1600*MHz:
+ dpll_cfg = &dpll_1600;
+ break;
+ default:
+ error("Unsupported SDRAM frequency!,%ld\n", set_rate);
+ }
+ rkclk_set_pll(cru, DPLL, dpll_cfg);
+
+ return set_rate;
+}
+#endif
+
+#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
+static ulong rk3368_gmac_set_clk(struct rk3368_cru *cru,
+ ulong clk_id, ulong set_rate)
+{
+ /*
+ * This models the 'assigned-clock-parents = <&ext_gmac>' from
+ * the DTS and switches to the 'ext_gmac' clock parent.
+ */
+ rk_setreg(&cru->clksel_con[43], GMAC_MUX_SEL_EXTCLK);
+ return set_rate;
+}
+#endif
+
+/*
+ * RK3368 SPI clocks have a common divider-width (7 bits) and a single bit
+ * to select either CPLL or GPLL as the clock-parent. The location within
+ * the enclosing CLKSEL_CON (i.e. div_shift and sel_shift) are variable.
+ */
+
+struct spi_clkreg {
+ uint8_t reg; /* CLKSEL_CON[reg] register in CRU */
+ uint8_t div_shift;
+ uint8_t sel_shift;
+};
+
+/*
+ * The entries are numbered relative to their offset from SCLK_SPI0.
+ */
+static const struct spi_clkreg spi_clkregs[] = {
+ [0] = { .reg = 45, .div_shift = 0, .sel_shift = 7, },
+ [1] = { .reg = 45, .div_shift = 8, .sel_shift = 15, },
+ [2] = { .reg = 46, .div_shift = 8, .sel_shift = 15, },
+};
+
+static inline u32 extract_bits(u32 val, unsigned width, unsigned shift)
+{
+ return (val >> shift) & ((1 << width) - 1);
+}
+
+static ulong rk3368_spi_get_clk(struct rk3368_cru *cru, ulong clk_id)
+{
+ const struct spi_clkreg *spiclk = NULL;
+ u32 div, val;
+
+ switch (clk_id) {
+ case SCLK_SPI0 ... SCLK_SPI2:
+ spiclk = &spi_clkregs[clk_id - SCLK_SPI0];
+ break;
+
+ default:
+ error("%s: SPI clk-id %ld not supported\n", __func__, clk_id);
+ return -EINVAL;
+ }
+
+ val = readl(&cru->clksel_con[spiclk->reg]);
+ div = extract_bits(val, 7, spiclk->div_shift);
+
+ debug("%s: div 0x%x\n", __func__, div);
+ return DIV_TO_RATE(GPLL_HZ, div);
+}
+
+static ulong rk3368_spi_set_clk(struct rk3368_cru *cru, ulong clk_id, uint hz)
+{
+ const struct spi_clkreg *spiclk = NULL;
+ int src_clk_div;
+
+ src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz);
+ assert(src_clk_div < 127);
+
+ switch (clk_id) {
+ case SCLK_SPI0 ... SCLK_SPI2:
+ spiclk = &spi_clkregs[clk_id - SCLK_SPI0];
+ break;
+
+ default:
+ error("%s: SPI clk-id %ld not supported\n", __func__, clk_id);
+ return -EINVAL;
+ }
+
+ rk_clrsetreg(&cru->clksel_con[spiclk->reg],
+ ((0x7f << spiclk->div_shift) |
+ (0x1 << spiclk->sel_shift)),
+ ((src_clk_div << spiclk->div_shift) |
+ (1 << spiclk->sel_shift)));
+
+ return rk3368_spi_get_clk(cru, clk_id);
+}
static ulong rk3368_clk_get_rate(struct clk *clk)
{
struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
ulong rate = 0;
- debug("%s id:%ld\n", __func__, clk->id);
+ debug("%s: id %ld\n", __func__, clk->id);
switch (clk->id) {
+ case PLL_CPLL:
+ rate = rkclk_pll_get_rate(priv->cru, CPLL);
+ break;
+ case PLL_GPLL:
+ rate = rkclk_pll_get_rate(priv->cru, GPLL);
+ break;
+ case SCLK_SPI0 ... SCLK_SPI2:
+ rate = rk3368_spi_get_clk(priv->cru, clk->id);
+ break;
+#if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC_SUPPORT)
case HCLK_SDMMC:
case HCLK_EMMC:
rate = rk3368_mmc_get_clk(priv->cru, clk->id);
break;
+#endif
default:
return -ENOENT;
}
@@ -223,15 +428,31 @@ static ulong rk3368_clk_get_rate(struct clk *clk)
static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate)
{
- struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
+ __maybe_unused struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
ulong ret = 0;
debug("%s id:%ld rate:%ld\n", __func__, clk->id, rate);
switch (clk->id) {
- case SCLK_SDMMC:
- case SCLK_EMMC:
- ret = rk3368_mmc_set_clk(priv->cru, clk->id, rate);
+ case SCLK_SPI0 ... SCLK_SPI2:
+ ret = rk3368_spi_set_clk(priv->cru, clk->id, rate);
break;
+#if IS_ENABLED(CONFIG_TPL_BUILD)
+ case CLK_DDR:
+ ret = rk3368_ddr_set_clk(priv->cru, rate);
+ break;
+#endif
+#if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC_SUPPORT)
+ case HCLK_SDMMC:
+ case HCLK_EMMC:
+ ret = rk3368_mmc_set_clk(clk, rate);
+ break;
+#endif
+#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
+ case SCLK_MAC:
+ /* select the external clock */
+ ret = rk3368_gmac_set_clk(priv->cru, clk->id, rate);
+ break;
+#endif
default:
return -ENOENT;
}
@@ -246,18 +467,26 @@ static struct clk_ops rk3368_clk_ops = {
static int rk3368_clk_probe(struct udevice *dev)
{
- struct rk3368_clk_priv *priv = dev_get_priv(dev);
+ struct rk3368_clk_priv __maybe_unused *priv = dev_get_priv(dev);
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+ struct rk3368_clk_plat *plat = dev_get_platdata(dev);
+ priv->cru = map_sysmem(plat->dtd.reg[1], plat->dtd.reg[3]);
+#endif
+#if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)
rkclk_init(priv->cru);
+#endif
return 0;
}
static int rk3368_clk_ofdata_to_platdata(struct udevice *dev)
{
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
struct rk3368_clk_priv *priv = dev_get_priv(dev);
priv->cru = (struct rk3368_cru *)devfdt_get_addr(dev);
+#endif
return 0;
}
@@ -284,6 +513,9 @@ U_BOOT_DRIVER(rockchip_rk3368_cru) = {
.id = UCLASS_CLK,
.of_match = rk3368_clk_ids,
.priv_auto_alloc_size = sizeof(struct rk3368_clk_priv),
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+ .platdata_auto_alloc_size = sizeof(struct rk3368_clk_plat),
+#endif
.ofdata_to_platdata = rk3368_clk_ofdata_to_platdata,
.ops = &rk3368_clk_ops,
.bind = rk3368_clk_bind,
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index 53d2a3f85da..3edafea1400 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -676,8 +676,8 @@ static ulong rk3399_spi_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz)
const struct spi_clkreg *spiclk = NULL;
int src_clk_div;
- src_clk_div = RATE_TO_DIV(GPLL_HZ, hz);
- assert(src_clk_div < 127);
+ src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1;
+ assert(src_clk_div < 128);
switch (clk_id) {
case SCLK_SPI1 ... SCLK_SPI5:
@@ -750,18 +750,21 @@ static ulong rk3399_mmc_get_clk(struct rk3399_cru *cru, uint clk_id)
case HCLK_SDMMC:
case SCLK_SDMMC:
con = readl(&cru->clksel_con[16]);
+ /* dwmmc controller have internal div 2 */
+ div = 2;
break;
case SCLK_EMMC:
con = readl(&cru->clksel_con[21]);
+ div = 1;
break;
default:
return -EINVAL;
}
- div = (con & CLK_EMMC_DIV_CON_MASK) >> CLK_EMMC_DIV_CON_SHIFT;
+ div *= (con & CLK_EMMC_DIV_CON_MASK) >> CLK_EMMC_DIV_CON_SHIFT;
if ((con & CLK_EMMC_PLL_MASK) >> CLK_EMMC_PLL_SHIFT
== CLK_EMMC_PLL_SEL_24M)
- return DIV_TO_RATE(24*1000*1000, div);
+ return DIV_TO_RATE(OSC_HZ, div);
else
return DIV_TO_RATE(GPLL_HZ, div);
}
@@ -776,11 +779,13 @@ static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru,
case HCLK_SDMMC:
case SCLK_SDMMC:
/* Select clk_sdmmc source from GPLL by default */
- src_clk_div = GPLL_HZ / set_rate;
+ /* mmc clock defaulg div 2 internal, provide double in cru */
+ src_clk_div = DIV_ROUND_UP(GPLL_HZ / 2, set_rate);
- if (src_clk_div > 127) {
+ if (src_clk_div > 128) {
/* use 24MHz source for 400KHz clock */
- src_clk_div = 24*1000*1000 / set_rate;
+ src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate);
+ assert(src_clk_div - 1 < 128);
rk_clrsetreg(&cru->clksel_con[16],
CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
CLK_EMMC_PLL_SEL_24M << CLK_EMMC_PLL_SHIFT |
@@ -794,8 +799,8 @@ static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru,
break;
case SCLK_EMMC:
/* Select aclk_emmc source from GPLL */
- src_clk_div = GPLL_HZ / aclk_emmc;
- assert(src_clk_div - 1 < 31);
+ src_clk_div = DIV_ROUND_UP(GPLL_HZ , aclk_emmc);
+ assert(src_clk_div - 1 < 32);
rk_clrsetreg(&cru->clksel_con[21],
ACLK_EMMC_PLL_SEL_MASK | ACLK_EMMC_DIV_CON_MASK,
@@ -803,8 +808,8 @@ static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru,
(src_clk_div - 1) << ACLK_EMMC_DIV_CON_SHIFT);
/* Select clk_emmc source from GPLL too */
- src_clk_div = GPLL_HZ / set_rate;
- assert(src_clk_div - 1 < 127);
+ src_clk_div = DIV_ROUND_UP(GPLL_HZ, set_rate);
+ assert(src_clk_div - 1 < 128);
rk_clrsetreg(&cru->clksel_con[22],
CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
diff --git a/drivers/clk/rockchip/clk_rv1108.c b/drivers/clk/rockchip/clk_rv1108.c
index 818293dfe87..cf966bbdc33 100644
--- a/drivers/clk/rockchip/clk_rv1108.c
+++ b/drivers/clk/rockchip/clk_rv1108.c
@@ -25,9 +25,6 @@ enum {
OUTPUT_MIN_HZ = 24 * 1000000,
};
-#define RATE_TO_DIV(input_rate, output_rate) \
- ((input_rate) / (output_rate) - 1);
-
#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
#define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig
index f8b19a48cc0..7afef1f9a3f 100644
--- a/drivers/core/Kconfig
+++ b/drivers/core/Kconfig
@@ -97,7 +97,17 @@ config REGMAP
config SPL_REGMAP
bool "Support register maps in SPL"
- depends on DM
+ depends on SPL_DM
+ help
+ Hardware peripherals tend to have one or more sets of registers
+ which can be accessed to control the hardware. A register map
+ models this with a simple read/write interface. It can in principle
+ support any bus type (I2C, SPI) but so far this only supports
+ direct memory access.
+
+config TPL_REGMAP
+ bool "Support register maps in TPL"
+ depends on TPL_DM
help
Hardware peripherals tend to have one or more sets of registers
which can be accessed to control the hardware. A register map
@@ -116,7 +126,16 @@ config SYSCON
config SPL_SYSCON
bool "Support system controllers in SPL"
- depends on REGMAP
+ depends on SPL_REGMAP
+ help
+ Many SoCs have a number of system controllers which are dealt with
+ as a group by a single driver. Some common functionality is provided
+ by this uclass, including accessing registers via regmap and
+ assigning a unique number to each.
+
+config TPL_SYSCON
+ bool "Support system controllers in TPL"
+ depends on TPL_REGMAP
help
Many SoCs have a number of system controllers which are dealt with
as a group by a single driver. Some common functionality is provided
diff --git a/drivers/core/Makefile b/drivers/core/Makefile
index fd2d4de0c83..3d68c70b57c 100644
--- a/drivers/core/Makefile
+++ b/drivers/core/Makefile
@@ -9,8 +9,8 @@ obj-$(CONFIG_DEVRES) += devres.o
obj-$(CONFIG_$(SPL_)DM_DEVICE_REMOVE) += device-remove.o
obj-$(CONFIG_$(SPL_)SIMPLE_BUS) += simple-bus.o
obj-$(CONFIG_DM) += dump.o
-obj-$(CONFIG_$(SPL_)REGMAP) += regmap.o
-obj-$(CONFIG_$(SPL_)SYSCON) += syscon-uclass.o
+obj-$(CONFIG_$(SPL_TPL_)REGMAP) += regmap.o
+obj-$(CONFIG_$(SPL_TPL_)SYSCON) += syscon-uclass.o
obj-$(CONFIG_OF_LIVE) += of_access.o of_addr.o
ifndef CONFIG_DM_DEV_READ_INLINE
obj-$(CONFIG_OF_CONTROL) += read.o
diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c
index c9f9e839bad..586ccbff0a7 100644
--- a/drivers/net/gmac_rockchip.c
+++ b/drivers/net/gmac_rockchip.c
@@ -16,6 +16,7 @@
#include <asm/arch/clock.h>
#include <asm/arch/hardware.h>
#include <asm/arch/grf_rk3288.h>
+#include <asm/arch/grf_rk3368.h>
#include <asm/arch/grf_rk3399.h>
#include <dm/pinctrl.h>
#include <dt-bindings/clock/rk3288-cru.h>
@@ -83,6 +84,38 @@ static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv)
return 0;
}
+static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+{
+ struct rk3368_grf *grf;
+ int clk;
+ enum {
+ RK3368_GMAC_CLK_SEL_2_5M = 2 << 4,
+ RK3368_GMAC_CLK_SEL_25M = 3 << 4,
+ RK3368_GMAC_CLK_SEL_125M = 0 << 4,
+ RK3368_GMAC_CLK_SEL_MASK = GENMASK(5, 4),
+ };
+
+ switch (priv->phydev->speed) {
+ case 10:
+ clk = RK3368_GMAC_CLK_SEL_2_5M;
+ break;
+ case 100:
+ clk = RK3368_GMAC_CLK_SEL_25M;
+ break;
+ case 1000:
+ clk = RK3368_GMAC_CLK_SEL_125M;
+ break;
+ default:
+ debug("Unknown phy speed: %d\n", priv->phydev->speed);
+ return -EINVAL;
+ }
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ rk_clrsetreg(&grf->soc_con15, RK3368_GMAC_CLK_SEL_MASK, clk);
+
+ return 0;
+}
+
static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev *priv)
{
struct rk3399_grf_regs *grf;
@@ -129,6 +162,44 @@ static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT);
}
+static void rk3368_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
+{
+ struct rk3368_grf *grf;
+ enum {
+ RK3368_GMAC_PHY_INTF_SEL_RGMII = 1 << 9,
+ RK3368_GMAC_PHY_INTF_SEL_MASK = GENMASK(11, 9),
+ RK3368_RMII_MODE_MASK = BIT(6),
+ RK3368_RMII_MODE = BIT(6),
+ };
+ enum {
+ RK3368_RXCLK_DLY_ENA_GMAC_MASK = BIT(15),
+ RK3368_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
+ RK3368_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(15),
+ RK3368_TXCLK_DLY_ENA_GMAC_MASK = BIT(7),
+ RK3368_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
+ RK3368_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(7),
+ RK3368_CLK_RX_DL_CFG_GMAC_SHIFT = 8,
+ RK3368_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8),
+ RK3368_CLK_TX_DL_CFG_GMAC_SHIFT = 0,
+ RK3368_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0),
+ };
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ rk_clrsetreg(&grf->soc_con15,
+ RK3368_RMII_MODE_MASK | RK3368_GMAC_PHY_INTF_SEL_MASK,
+ RK3368_GMAC_PHY_INTF_SEL_RGMII);
+
+ rk_clrsetreg(&grf->soc_con16,
+ RK3368_RXCLK_DLY_ENA_GMAC_MASK |
+ RK3368_TXCLK_DLY_ENA_GMAC_MASK |
+ RK3368_CLK_RX_DL_CFG_GMAC_MASK |
+ RK3368_CLK_TX_DL_CFG_GMAC_MASK,
+ RK3368_RXCLK_DLY_ENA_GMAC_ENABLE |
+ RK3368_TXCLK_DLY_ENA_GMAC_ENABLE |
+ pdata->rx_delay << RK3368_CLK_RX_DL_CFG_GMAC_SHIFT |
+ pdata->tx_delay << RK3368_CLK_TX_DL_CFG_GMAC_SHIFT);
+}
+
static void rk3399_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
{
struct rk3399_grf_regs *grf;
@@ -208,6 +279,11 @@ const struct rk_gmac_ops rk3288_gmac_ops = {
.set_to_rgmii = rk3288_gmac_set_to_rgmii,
};
+const struct rk_gmac_ops rk3368_gmac_ops = {
+ .fix_mac_speed = rk3368_gmac_fix_mac_speed,
+ .set_to_rgmii = rk3368_gmac_set_to_rgmii,
+};
+
const struct rk_gmac_ops rk3399_gmac_ops = {
.fix_mac_speed = rk3399_gmac_fix_mac_speed,
.set_to_rgmii = rk3399_gmac_set_to_rgmii,
@@ -216,6 +292,8 @@ const struct rk_gmac_ops rk3399_gmac_ops = {
static const struct udevice_id rockchip_gmac_ids[] = {
{ .compatible = "rockchip,rk3288-gmac",
.data = (ulong)&rk3288_gmac_ops },
+ { .compatible = "rockchip,rk3368-gmac",
+ .data = (ulong)&rk3368_gmac_ops },
{ .compatible = "rockchip,rk3399-gmac",
.data = (ulong)&rk3399_gmac_ops },
{ }
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3368.c b/drivers/pinctrl/rockchip/pinctrl_rk3368.c
index bdf0758c0cc..81ce2e31a7f 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rk3368.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3368.c
@@ -1,8 +1,11 @@
/*
* (C) Copyright 2017 Rockchip Electronics Co., Ltd
* Author: Andy Yan <andy.yan@rock-chips.com>
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
+ *
* SPDX-License-Identifier: GPL-2.0+
*/
+
#include <common.h>
#include <dm.h>
#include <errno.h>
@@ -16,6 +19,428 @@
DECLARE_GLOBAL_DATA_PTR;
+/* PMUGRF_GPIO0B_IOMUX */
+enum {
+ GPIO0B5_SHIFT = 10,
+ GPIO0B5_MASK = GENMASK(GPIO0B5_SHIFT + 1, GPIO0B5_SHIFT),
+ GPIO0B5_GPIO = 0,
+ GPIO0B5_SPI2_CSN0 = (2 << GPIO0B5_SHIFT),
+
+ GPIO0B4_SHIFT = 8,
+ GPIO0B4_MASK = GENMASK(GPIO0B4_SHIFT + 1, GPIO0B4_SHIFT),
+ GPIO0B4_GPIO = 0,
+ GPIO0B4_SPI2_CLK = (2 << GPIO0B4_SHIFT),
+
+ GPIO0B3_SHIFT = 6,
+ GPIO0B3_MASK = GENMASK(GPIO0B3_SHIFT + 1, GPIO0B3_SHIFT),
+ GPIO0B3_GPIO = 0,
+ GPIO0B3_SPI2_TXD = (2 << GPIO0B3_SHIFT),
+
+ GPIO0B2_SHIFT = 4,
+ GPIO0B2_MASK = GENMASK(GPIO0B2_SHIFT + 1, GPIO0B2_SHIFT),
+ GPIO0B2_GPIO = 0,
+ GPIO0B2_SPI2_RXD = (2 << GPIO0B2_SHIFT),
+};
+
+/*GRF_GPIO0C_IOMUX*/
+enum {
+ GPIO0C7_SHIFT = 14,
+ GPIO0C7_MASK = GENMASK(GPIO0C7_SHIFT + 1, GPIO0C7_SHIFT),
+ GPIO0C7_GPIO = 0,
+ GPIO0C7_LCDC_D19 = (1 << GPIO0C7_SHIFT),
+ GPIO0C7_TRACE_D9 = (2 << GPIO0C7_SHIFT),
+ GPIO0C7_UART1_RTSN = (3 << GPIO0C7_SHIFT),
+
+ GPIO0C6_SHIFT = 12,
+ GPIO0C6_MASK = GENMASK(GPIO0C6_SHIFT + 1, GPIO0C6_SHIFT),
+ GPIO0C6_GPIO = 0,
+ GPIO0C6_LCDC_D18 = (1 << GPIO0C6_SHIFT),
+ GPIO0C6_TRACE_D8 = (2 << GPIO0C6_SHIFT),
+ GPIO0C6_UART1_CTSN = (3 << GPIO0C6_SHIFT),
+
+ GPIO0C5_SHIFT = 10,
+ GPIO0C5_MASK = GENMASK(GPIO0C5_SHIFT + 1, GPIO0C5_SHIFT),
+ GPIO0C5_GPIO = 0,
+ GPIO0C5_LCDC_D17 = (1 << GPIO0C5_SHIFT),
+ GPIO0C5_TRACE_D7 = (2 << GPIO0C5_SHIFT),
+ GPIO0C5_UART1_SOUT = (3 << GPIO0C5_SHIFT),
+
+ GPIO0C4_SHIFT = 8,
+ GPIO0C4_MASK = GENMASK(GPIO0C4_SHIFT + 1, GPIO0C4_SHIFT),
+ GPIO0C4_GPIO = 0,
+ GPIO0C4_LCDC_D16 = (1 << GPIO0C4_SHIFT),
+ GPIO0C4_TRACE_D6 = (2 << GPIO0C4_SHIFT),
+ GPIO0C4_UART1_SIN = (3 << GPIO0C4_SHIFT),
+
+ GPIO0C3_SHIFT = 6,
+ GPIO0C3_MASK = GENMASK(GPIO0C3_SHIFT + 1, GPIO0C3_SHIFT),
+ GPIO0C3_GPIO = 0,
+ GPIO0C3_LCDC_D15 = (1 << GPIO0C3_SHIFT),
+ GPIO0C3_TRACE_D5 = (2 << GPIO0C3_SHIFT),
+ GPIO0C3_MCU_JTAG_TDO = (3 << GPIO0C3_SHIFT),
+
+ GPIO0C2_SHIFT = 4,
+ GPIO0C2_MASK = GENMASK(GPIO0C2_SHIFT + 1, GPIO0C2_SHIFT),
+ GPIO0C2_GPIO = 0,
+ GPIO0C2_LCDC_D14 = (1 << GPIO0C2_SHIFT),
+ GPIO0C2_TRACE_D4 = (2 << GPIO0C2_SHIFT),
+ GPIO0C2_MCU_JTAG_TDI = (3 << GPIO0C2_SHIFT),
+
+ GPIO0C1_SHIFT = 2,
+ GPIO0C1_MASK = GENMASK(GPIO0C1_SHIFT + 1, GPIO0C1_SHIFT),
+ GPIO0C1_GPIO = 0,
+ GPIO0C1_LCDC_D13 = (1 << GPIO0C1_SHIFT),
+ GPIO0C1_TRACE_D3 = (2 << GPIO0C1_SHIFT),
+ GPIO0C1_MCU_JTAG_TRTSN = (3 << GPIO0C1_SHIFT),
+
+ GPIO0C0_SHIFT = 0,
+ GPIO0C0_MASK = GENMASK(GPIO0C0_SHIFT + 1, GPIO0C0_SHIFT),
+ GPIO0C0_GPIO = 0,
+ GPIO0C0_LCDC_D12 = (1 << GPIO0C0_SHIFT),
+ GPIO0C0_TRACE_D2 = (2 << GPIO0C0_SHIFT),
+ GPIO0C0_MCU_JTAG_TDO = (3 << GPIO0C0_SHIFT),
+};
+
+/*GRF_GPIO0D_IOMUX*/
+enum {
+ GPIO0D7_SHIFT = 14,
+ GPIO0D7_MASK = GENMASK(GPIO0D7_SHIFT + 1, GPIO0D7_SHIFT),
+ GPIO0D7_GPIO = 0,
+ GPIO0D7_LCDC_DCLK = (1 << GPIO0D7_SHIFT),
+ GPIO0D7_TRACE_CTL = (2 << GPIO0D7_SHIFT),
+ GPIO0D7_PMU_DEBUG5 = (3 << GPIO0D7_SHIFT),
+
+ GPIO0D6_SHIFT = 12,
+ GPIO0D6_MASK = GENMASK(GPIO0D6_SHIFT + 1, GPIO0D6_SHIFT),
+ GPIO0D6_GPIO = 0,
+ GPIO0D6_LCDC_DEN = (1 << GPIO0D6_SHIFT),
+ GPIO0D6_TRACE_CLK = (2 << GPIO0D6_SHIFT),
+ GPIO0D6_PMU_DEBUG4 = (3 << GPIO0D6_SHIFT),
+
+ GPIO0D5_SHIFT = 10,
+ GPIO0D5_MASK = GENMASK(GPIO0D5_SHIFT + 1, GPIO0D5_SHIFT),
+ GPIO0D5_GPIO = 0,
+ GPIO0D5_LCDC_VSYNC = (1 << GPIO0D5_SHIFT),
+ GPIO0D5_TRACE_D15 = (2 << GPIO0D5_SHIFT),
+ GPIO0D5_PMU_DEBUG3 = (3 << GPIO0D5_SHIFT),
+
+ GPIO0D4_SHIFT = 8,
+ GPIO0D4_MASK = GENMASK(GPIO0D4_SHIFT + 1, GPIO0D4_SHIFT),
+ GPIO0D4_GPIO = 0,
+ GPIO0D4_LCDC_HSYNC = (1 << GPIO0D4_SHIFT),
+ GPIO0D4_TRACE_D14 = (2 << GPIO0D4_SHIFT),
+ GPIO0D4_PMU_DEBUG2 = (3 << GPIO0D4_SHIFT),
+
+ GPIO0D3_SHIFT = 6,
+ GPIO0D3_MASK = GENMASK(GPIO0D3_SHIFT + 1, GPIO0D3_SHIFT),
+ GPIO0D3_GPIO = 0,
+ GPIO0D3_LCDC_D23 = (1 << GPIO0D3_SHIFT),
+ GPIO0D3_TRACE_D13 = (2 << GPIO0D3_SHIFT),
+ GPIO0D3_UART4_SIN = (3 << GPIO0D3_SHIFT),
+
+ GPIO0D2_SHIFT = 4,
+ GPIO0D2_MASK = GENMASK(GPIO0D2_SHIFT + 1, GPIO0D2_SHIFT),
+ GPIO0D2_GPIO = 0,
+ GPIO0D2_LCDC_D22 = (1 << GPIO0D2_SHIFT),
+ GPIO0D2_TRACE_D12 = (2 << GPIO0D2_SHIFT),
+ GPIO0D2_UART4_SOUT = (3 << GPIO0D2_SHIFT),
+
+ GPIO0D1_SHIFT = 2,
+ GPIO0D1_MASK = GENMASK(GPIO0D1_SHIFT + 1, GPIO0D1_SHIFT),
+ GPIO0D1_GPIO = 0,
+ GPIO0D1_LCDC_D21 = (1 << GPIO0D1_SHIFT),
+ GPIO0D1_TRACE_D11 = (2 << GPIO0D1_SHIFT),
+ GPIO0D1_UART4_RTSN = (3 << GPIO0D1_SHIFT),
+
+ GPIO0D0_SHIFT = 0,
+ GPIO0D0_MASK = GENMASK(GPIO0D0_SHIFT + 1, GPIO0D0_SHIFT),
+ GPIO0D0_GPIO = 0,
+ GPIO0D0_LCDC_D20 = (1 << GPIO0D0_SHIFT),
+ GPIO0D0_TRACE_D10 = (2 << GPIO0D0_SHIFT),
+ GPIO0D0_UART4_CTSN = (3 << GPIO0D0_SHIFT),
+};
+
+/*GRF_GPIO2A_IOMUX*/
+enum {
+ GPIO2A7_SHIFT = 14,
+ GPIO2A7_MASK = GENMASK(GPIO2A7_SHIFT + 1, GPIO2A7_SHIFT),
+ GPIO2A7_GPIO = 0,
+ GPIO2A7_SDMMC0_D2 = (1 << GPIO2A7_SHIFT),
+ GPIO2A7_JTAG_TCK = (2 << GPIO2A7_SHIFT),
+
+ GPIO2A6_SHIFT = 12,
+ GPIO2A6_MASK = GENMASK(GPIO2A6_SHIFT + 1, GPIO2A6_SHIFT),
+ GPIO2A6_GPIO = 0,
+ GPIO2A6_SDMMC0_D1 = (1 << GPIO2A6_SHIFT),
+ GPIO2A6_UART2_SIN = (2 << GPIO2A6_SHIFT),
+
+ GPIO2A5_SHIFT = 10,
+ GPIO2A5_MASK = GENMASK(GPIO2A5_SHIFT + 1, GPIO2A5_SHIFT),
+ GPIO2A5_GPIO = 0,
+ GPIO2A5_SDMMC0_D0 = (1 << GPIO2A5_SHIFT),
+ GPIO2A5_UART2_SOUT = (2 << GPIO2A5_SHIFT),
+
+ GPIO2A4_SHIFT = 8,
+ GPIO2A4_MASK = GENMASK(GPIO2A4_SHIFT + 1, GPIO2A4_SHIFT),
+ GPIO2A4_GPIO = 0,
+ GPIO2A4_FLASH_DQS = (1 << GPIO2A4_SHIFT),
+ GPIO2A4_EMMC_CLKOUT = (2 << GPIO2A4_SHIFT),
+
+ GPIO2A3_SHIFT = 6,
+ GPIO2A3_MASK = GENMASK(GPIO2A3_SHIFT + 1, GPIO2A3_SHIFT),
+ GPIO2A3_GPIO = 0,
+ GPIO2A3_FLASH_CSN3 = (1 << GPIO2A3_SHIFT),
+ GPIO2A3_EMMC_RSTNOUT = (2 << GPIO2A3_SHIFT),
+
+ GPIO2A2_SHIFT = 4,
+ GPIO2A2_MASK = GENMASK(GPIO2A2_SHIFT + 1, GPIO2A2_SHIFT),
+ GPIO2A2_GPIO = 0,
+ GPIO2A2_FLASH_CSN2 = (1 << GPIO2A2_SHIFT),
+
+ GPIO2A1_SHIFT = 2,
+ GPIO2A1_MASK = GENMASK(GPIO2A1_SHIFT + 1, GPIO2A1_SHIFT),
+ GPIO2A1_GPIO = 0,
+ GPIO2A1_FLASH_CSN1 = (1 << GPIO2A1_SHIFT),
+
+ GPIO2A0_SHIFT = 0,
+ GPIO2A0_MASK = GENMASK(GPIO2A0_SHIFT + 1, GPIO2A0_SHIFT),
+ GPIO2A0_GPIO = 0,
+ GPIO2A0_FLASH_CSN0 = (1 << GPIO2A0_SHIFT),
+};
+
+/*GRF_GPIO2D_IOMUX*/
+enum {
+ GPIO2D7_SHIFT = 14,
+ GPIO2D7_MASK = GENMASK(GPIO2D7_SHIFT + 1, GPIO2D7_SHIFT),
+ GPIO2D7_GPIO = 0,
+ GPIO2D7_SDIO0_D3 = (1 << GPIO2D7_SHIFT),
+
+ GPIO2D6_SHIFT = 12,
+ GPIO2D6_MASK = GENMASK(GPIO2D6_SHIFT + 1, GPIO2D6_SHIFT),
+ GPIO2D6_GPIO = 0,
+ GPIO2D6_SDIO0_D2 = (1 << GPIO2D6_SHIFT),
+
+ GPIO2D5_SHIFT = 10,
+ GPIO2D5_MASK = GENMASK(GPIO2D5_SHIFT + 1, GPIO2D5_SHIFT),
+ GPIO2D5_GPIO = 0,
+ GPIO2D5_SDIO0_D1 = (1 << GPIO2D5_SHIFT),
+
+ GPIO2D4_SHIFT = 8,
+ GPIO2D4_MASK = GENMASK(GPIO2D4_SHIFT + 1, GPIO2D4_SHIFT),
+ GPIO2D4_GPIO = 0,
+ GPIO2D4_SDIO0_D0 = (1 << GPIO2D4_SHIFT),
+
+ GPIO2D3_SHIFT = 6,
+ GPIO2D3_MASK = GENMASK(GPIO2D3_SHIFT + 1, GPIO2D3_SHIFT),
+ GPIO2D3_GPIO = 0,
+ GPIO2D3_UART0_RTS0 = (1 << GPIO2D3_SHIFT),
+
+ GPIO2D2_SHIFT = 4,
+ GPIO2D2_MASK = GENMASK(GPIO2D2_SHIFT + 1, GPIO2D2_SHIFT),
+ GPIO2D2_GPIO = 0,
+ GPIO2D2_UART0_CTS0 = (1 << GPIO2D2_SHIFT),
+
+ GPIO2D1_SHIFT = 2,
+ GPIO2D1_MASK = GENMASK(GPIO2D1_SHIFT + 1, GPIO2D1_SHIFT),
+ GPIO2D1_GPIO = 0,
+ GPIO2D1_UART0_SOUT = (1 << GPIO2D1_SHIFT),
+
+ GPIO2D0_SHIFT = 0,
+ GPIO2D0_MASK = GENMASK(GPIO2D0_SHIFT + 1, GPIO2D0_SHIFT),
+ GPIO2D0_GPIO = 0,
+ GPIO2D0_UART0_SIN = (1 << GPIO2D0_SHIFT),
+};
+
+/* GRF_GPIO1B_IOMUX */
+enum {
+ GPIO1B7_SHIFT = 14,
+ GPIO1B7_MASK = GENMASK(GPIO1B7_SHIFT + 1, GPIO1B7_SHIFT),
+ GPIO1B7_GPIO = 0,
+ GPIO1B7_SPI1_CSN0 = (2 << GPIO1B7_SHIFT),
+
+ GPIO1B6_SHIFT = 12,
+ GPIO1B6_MASK = GENMASK(GPIO1B6_SHIFT + 1, GPIO1B6_SHIFT),
+ GPIO1B6_GPIO = 0,
+ GPIO1B6_SPI1_CLK = (2 << GPIO1B6_SHIFT),
+};
+
+/* GRF_GPIO1C_IOMUX */
+enum {
+ GPIO1C7_SHIFT = 14,
+ GPIO1C7_MASK = GENMASK(GPIO1C7_SHIFT + 1, GPIO1C7_SHIFT),
+ GPIO1C7_GPIO = 0,
+ GPIO1C7_EMMC_DATA5 = (2 << GPIO1C7_SHIFT),
+ GPIO1C7_SPI0_TXD = (3 << GPIO1C7_SHIFT),
+
+ GPIO1C6_SHIFT = 12,
+ GPIO1C6_MASK = GENMASK(GPIO1C6_SHIFT + 1, GPIO1C6_SHIFT),
+ GPIO1C6_GPIO = 0,
+ GPIO1C6_EMMC_DATA4 = (2 << GPIO1C6_SHIFT),
+ GPIO1C6_SPI0_RXD = (3 << GPIO1C6_SHIFT),
+
+ GPIO1C5_SHIFT = 10,
+ GPIO1C5_MASK = GENMASK(GPIO1C5_SHIFT + 1, GPIO1C5_SHIFT),
+ GPIO1C5_GPIO = 0,
+ GPIO1C5_EMMC_DATA3 = (2 << GPIO1C5_SHIFT),
+
+ GPIO1C4_SHIFT = 8,
+ GPIO1C4_MASK = GENMASK(GPIO1C4_SHIFT + 1, GPIO1C4_SHIFT),
+ GPIO1C4_GPIO = 0,
+ GPIO1C4_EMMC_DATA2 = (2 << GPIO1C4_SHIFT),
+
+ GPIO1C3_SHIFT = 6,
+ GPIO1C3_MASK = GENMASK(GPIO1C3_SHIFT + 1, GPIO1C3_SHIFT),
+ GPIO1C3_GPIO = 0,
+ GPIO1C3_EMMC_DATA1 = (2 << GPIO1C3_SHIFT),
+
+ GPIO1C2_SHIFT = 4,
+ GPIO1C2_MASK = GENMASK(GPIO1C2_SHIFT + 1, GPIO1C2_SHIFT),
+ GPIO1C2_GPIO = 0,
+ GPIO1C2_EMMC_DATA0 = (2 << GPIO1C2_SHIFT),
+
+ GPIO1C1_SHIFT = 2,
+ GPIO1C1_MASK = GENMASK(GPIO1C1_SHIFT + 1, GPIO1C1_SHIFT),
+ GPIO1C1_GPIO = 0,
+ GPIO1C1_SPI1_RXD = (2 << GPIO1C1_SHIFT),
+
+ GPIO1C0_SHIFT = 0,
+ GPIO1C0_MASK = GENMASK(GPIO1C0_SHIFT + 1, GPIO1C0_SHIFT),
+ GPIO1C0_GPIO = 0,
+ GPIO1C0_SPI1_TXD = (2 << GPIO1C0_SHIFT),
+};
+
+/* GRF_GPIO1D_IOMUX*/
+enum {
+ GPIO1D5_SHIFT = 10,
+ GPIO1D5_MASK = GENMASK(GPIO1D5_SHIFT + 1, GPIO1D5_SHIFT),
+ GPIO1D5_GPIO = 0,
+ GPIO1D5_SPI0_CLK = (2 << GPIO1D5_SHIFT),
+
+ GPIO1D3_SHIFT = 6,
+ GPIO1D3_MASK = GENMASK(GPIO1D3_SHIFT + 1, GPIO1D3_SHIFT),
+ GPIO1D3_GPIO = 0,
+ GPIO1D3_EMMC_PWREN = (2 << GPIO1D3_SHIFT),
+
+ GPIO1D2_SHIFT = 4,
+ GPIO1D2_MASK = GENMASK(GPIO1D2_SHIFT + 1, GPIO1D2_SHIFT),
+ GPIO1D2_GPIO = 0,
+ GPIO1D2_EMMC_CMD = (2 << GPIO1D2_SHIFT),
+
+ GPIO1D1_SHIFT = 2,
+ GPIO1D1_MASK = GENMASK(GPIO1D1_SHIFT + 1, GPIO1D1_SHIFT),
+ GPIO1D1_GPIO = 0,
+ GPIO1D1_EMMC_DATA7 = (2 << GPIO1D1_SHIFT),
+ GPIO1D1_SPI0_CSN1 = (3 << GPIO1D1_SHIFT),
+
+ GPIO1D0_SHIFT = 0,
+ GPIO1D0_MASK = GENMASK(GPIO1D0_SHIFT + 1, GPIO1D0_SHIFT),
+ GPIO1D0_GPIO = 0,
+ GPIO1D0_EMMC_DATA6 = (2 << GPIO1D0_SHIFT),
+ GPIO1D0_SPI0_CSN0 = (3 << GPIO1D0_SHIFT),
+};
+
+
+/*GRF_GPIO3B_IOMUX*/
+enum {
+ GPIO3B7_SHIFT = 14,
+ GPIO3B7_MASK = GENMASK(GPIO3B7_SHIFT + 1, GPIO3B7_SHIFT),
+ GPIO3B7_GPIO = 0,
+ GPIO3B7_MAC_RXD0 = (1 << GPIO3B7_SHIFT),
+
+ GPIO3B6_SHIFT = 12,
+ GPIO3B6_MASK = GENMASK(GPIO3B6_SHIFT + 1, GPIO3B6_SHIFT),
+ GPIO3B6_GPIO = 0,
+ GPIO3B6_MAC_TXD3 = (1 << GPIO3B6_SHIFT),
+
+ GPIO3B5_SHIFT = 10,
+ GPIO3B5_MASK = GENMASK(GPIO3B5_SHIFT + 1, GPIO3B5_SHIFT),
+ GPIO3B5_GPIO = 0,
+ GPIO3B5_MAC_TXEN = (1 << GPIO3B5_SHIFT),
+
+ GPIO3B4_SHIFT = 8,
+ GPIO3B4_MASK = GENMASK(GPIO3B4_SHIFT + 1, GPIO3B4_SHIFT),
+ GPIO3B4_GPIO = 0,
+ GPIO3B4_MAC_COL = (1 << GPIO3B4_SHIFT),
+
+ GPIO3B3_SHIFT = 6,
+ GPIO3B3_MASK = GENMASK(GPIO3B3_SHIFT + 1, GPIO3B3_SHIFT),
+ GPIO3B3_GPIO = 0,
+ GPIO3B3_MAC_CRS = (1 << GPIO3B3_SHIFT),
+
+ GPIO3B2_SHIFT = 4,
+ GPIO3B2_MASK = GENMASK(GPIO3B2_SHIFT + 1, GPIO3B2_SHIFT),
+ GPIO3B2_GPIO = 0,
+ GPIO3B2_MAC_TXD2 = (1 << GPIO3B2_SHIFT),
+
+ GPIO3B1_SHIFT = 2,
+ GPIO3B1_MASK = GENMASK(GPIO3B1_SHIFT + 1, GPIO3B1_SHIFT),
+ GPIO3B1_GPIO = 0,
+ GPIO3B1_MAC_TXD1 = (1 << GPIO3B1_SHIFT),
+
+ GPIO3B0_SHIFT = 0,
+ GPIO3B0_MASK = GENMASK(GPIO3B0_SHIFT + 1, GPIO3B0_SHIFT),
+ GPIO3B0_GPIO = 0,
+ GPIO3B0_MAC_TXD0 = (1 << GPIO3B0_SHIFT),
+ GPIO3B0_PWM0 = (2 << GPIO3B0_SHIFT),
+};
+
+/*GRF_GPIO3C_IOMUX*/
+enum {
+ GPIO3C6_SHIFT = 12,
+ GPIO3C6_MASK = GENMASK(GPIO3C6_SHIFT + 1, GPIO3C6_SHIFT),
+ GPIO3C6_GPIO = 0,
+ GPIO3C6_MAC_CLK = (1 << GPIO3C6_SHIFT),
+
+ GPIO3C5_SHIFT = 10,
+ GPIO3C5_MASK = GENMASK(GPIO3C5_SHIFT + 1, GPIO3C5_SHIFT),
+ GPIO3C5_GPIO = 0,
+ GPIO3C5_MAC_RXEN = (1 << GPIO3C5_SHIFT),
+
+ GPIO3C4_SHIFT = 8,
+ GPIO3C4_MASK = GENMASK(GPIO3C4_SHIFT + 1, GPIO3C4_SHIFT),
+ GPIO3C4_GPIO = 0,
+ GPIO3C4_MAC_RXDV = (1 << GPIO3C4_SHIFT),
+
+ GPIO3C3_SHIFT = 6,
+ GPIO3C3_MASK = GENMASK(GPIO3C3_SHIFT + 1, GPIO3C3_SHIFT),
+ GPIO3C3_GPIO = 0,
+ GPIO3C3_MAC_MDC = (1 << GPIO3C3_SHIFT),
+
+ GPIO3C2_SHIFT = 4,
+ GPIO3C2_MASK = GENMASK(GPIO3C2_SHIFT + 1, GPIO3C2_SHIFT),
+ GPIO3C2_GPIO = 0,
+ GPIO3C2_MAC_RXD3 = (1 << GPIO3C2_SHIFT),
+
+ GPIO3C1_SHIFT = 2,
+ GPIO3C1_MASK = GENMASK(GPIO3C1_SHIFT + 1, GPIO3C1_SHIFT),
+ GPIO3C1_GPIO = 0,
+ GPIO3C1_MAC_RXD2 = (1 << GPIO3C1_SHIFT),
+
+ GPIO3C0_SHIFT = 0,
+ GPIO3C0_MASK = GENMASK(GPIO3C0_SHIFT + 1, GPIO3C0_SHIFT),
+ GPIO3C0_GPIO = 0,
+ GPIO3C0_MAC_RXD1 = (1 << GPIO3C0_SHIFT),
+};
+
+/*GRF_GPIO3D_IOMUX*/
+enum {
+ GPIO3D4_SHIFT = 8,
+ GPIO3D4_MASK = GENMASK(GPIO3D4_SHIFT + 1, GPIO3D4_SHIFT),
+ GPIO3D4_GPIO = 0,
+ GPIO3D4_MAC_TXCLK = (1 << GPIO3D4_SHIFT),
+ GPIO3D4_SPI1_CNS1 = (2 << GPIO3D4_SHIFT),
+
+ GPIO3D1_SHIFT = 2,
+ GPIO3D1_MASK = GENMASK(GPIO3D1_SHIFT + 1, GPIO3D1_SHIFT),
+ GPIO3D1_GPIO = 0,
+ GPIO3D1_MAC_RXCLK = (1 << GPIO3D1_SHIFT),
+
+ GPIO3D0_SHIFT = 0,
+ GPIO3D0_MASK = GENMASK(GPIO3D0_SHIFT + 1, GPIO3D0_SHIFT),
+ GPIO3D0_GPIO = 0,
+ GPIO3D0_MAC_MDIO = (1 << GPIO3D0_SHIFT),
+};
+
struct rk3368_pinctrl_priv {
struct rk3368_grf *grf;
struct rk3368_pmu_grf *pmugrf;
@@ -31,8 +456,7 @@ static void pinctrl_rk3368_uart_config(struct rk3368_pinctrl_priv *priv,
case PERIPH_ID_UART2:
rk_clrsetreg(&grf->gpio2a_iomux,
GPIO2A6_MASK | GPIO2A5_MASK,
- GPIO2A6_UART2_SIN << GPIO2A6_SHIFT |
- GPIO2A5_UART2_SOUT << GPIO2A5_SHIFT);
+ GPIO2A6_UART2_SIN | GPIO2A5_UART2_SOUT);
break;
case PERIPH_ID_UART0:
break;
@@ -44,10 +468,8 @@ static void pinctrl_rk3368_uart_config(struct rk3368_pinctrl_priv *priv,
rk_clrsetreg(&pmugrf->gpio0d_iomux,
GPIO0D0_MASK | GPIO0D1_MASK |
GPIO0D2_MASK | GPIO0D3_MASK,
- GPIO0D0_GPIO << GPIO0D0_SHIFT |
- GPIO0D1_GPIO << GPIO0D1_SHIFT |
- GPIO0D2_UART4_SOUT << GPIO0D2_SHIFT |
- GPIO0D3_UART4_SIN << GPIO0D3_SHIFT);
+ GPIO0D0_GPIO | GPIO0D1_GPIO |
+ GPIO0D2_UART4_SOUT | GPIO0D3_UART4_SIN);
break;
default:
debug("uart id = %d iomux error!\n", uart_id);
@@ -55,6 +477,121 @@ static void pinctrl_rk3368_uart_config(struct rk3368_pinctrl_priv *priv,
}
}
+static void pinctrl_rk3368_spi_config(struct rk3368_pinctrl_priv *priv,
+ int spi_id)
+{
+ struct rk3368_grf *grf = priv->grf;
+ struct rk3368_pmu_grf *pmugrf = priv->pmugrf;
+
+ switch (spi_id) {
+ case PERIPH_ID_SPI0:
+ /*
+ * eMMC can only be connected with 4 bits, when SPI0 is used.
+ * This is all-or-nothing, so we assume that if someone asks us
+ * to configure SPI0, that their eMMC interface is unused or
+ * configured appropriately.
+ */
+ rk_clrsetreg(&grf->gpio1d_iomux,
+ GPIO1D0_MASK | GPIO1D1_MASK |
+ GPIO1D5_MASK,
+ GPIO1D0_SPI0_CSN0 | GPIO1D1_SPI0_CSN1 |
+ GPIO1D5_SPI0_CLK);
+ rk_clrsetreg(&grf->gpio1c_iomux,
+ GPIO1C6_MASK | GPIO1C7_MASK,
+ GPIO1C6_SPI0_RXD | GPIO1C7_SPI0_TXD);
+ break;
+ case PERIPH_ID_SPI1:
+ /*
+ * We don't implement support for configuring SPI1_CSN#1, as it
+ * conflicts with the GMAC (MAC TX clk-out).
+ */
+ rk_clrsetreg(&grf->gpio1b_iomux,
+ GPIO1B6_MASK | GPIO1B7_MASK,
+ GPIO1B6_SPI1_CLK | GPIO1B7_SPI1_CSN0);
+ rk_clrsetreg(&grf->gpio1c_iomux,
+ GPIO1C0_MASK | GPIO1C1_MASK,
+ GPIO1C0_SPI1_TXD | GPIO1C1_SPI1_RXD);
+ break;
+ case PERIPH_ID_SPI2:
+ rk_clrsetreg(&pmugrf->gpio0b_iomux,
+ GPIO0B2_MASK | GPIO0B3_MASK |
+ GPIO0B4_MASK | GPIO0B5_MASK,
+ GPIO0B2_SPI2_RXD | GPIO0B3_SPI2_TXD |
+ GPIO0B4_SPI2_CLK | GPIO0B5_SPI2_CSN0);
+ break;
+ default:
+ debug("%s: spi id = %d iomux error!\n", __func__, spi_id);
+ break;
+ }
+}
+
+#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
+static void pinctrl_rk3368_gmac_config(struct rk3368_grf *grf, int gmac_id)
+{
+ rk_clrsetreg(&grf->gpio3b_iomux,
+ GPIO3B0_MASK | GPIO3B1_MASK |
+ GPIO3B2_MASK | GPIO3B5_MASK |
+ GPIO3B6_MASK | GPIO3B7_MASK,
+ GPIO3B0_MAC_TXD0 | GPIO3B1_MAC_TXD1 |
+ GPIO3B2_MAC_TXD2 | GPIO3B5_MAC_TXEN |
+ GPIO3B6_MAC_TXD3 | GPIO3B7_MAC_RXD0);
+ rk_clrsetreg(&grf->gpio3c_iomux,
+ GPIO3C0_MASK | GPIO3C1_MASK |
+ GPIO3C2_MASK | GPIO3C3_MASK |
+ GPIO3C4_MASK | GPIO3C5_MASK |
+ GPIO3C6_MASK,
+ GPIO3C0_MAC_RXD1 | GPIO3C1_MAC_RXD2 |
+ GPIO3C2_MAC_RXD3 | GPIO3C3_MAC_MDC |
+ GPIO3C4_MAC_RXDV | GPIO3C5_MAC_RXEN |
+ GPIO3C6_MAC_CLK);
+ rk_clrsetreg(&grf->gpio3d_iomux,
+ GPIO3D0_MASK | GPIO3D1_MASK |
+ GPIO3D4_MASK,
+ GPIO3D0_MAC_MDIO | GPIO3D1_MAC_RXCLK |
+ GPIO3D4_MAC_TXCLK);
+}
+#endif
+
+static void pinctrl_rk3368_sdmmc_config(struct rk3368_grf *grf, int mmc_id)
+{
+ switch (mmc_id) {
+ case PERIPH_ID_EMMC:
+ debug("mmc id = %d setting registers!\n", mmc_id);
+ rk_clrsetreg(&grf->gpio1c_iomux,
+ GPIO1C2_MASK | GPIO1C3_MASK |
+ GPIO1C4_MASK | GPIO1C5_MASK |
+ GPIO1C6_MASK | GPIO1C7_MASK,
+ GPIO1C2_EMMC_DATA0 |
+ GPIO1C3_EMMC_DATA1 |
+ GPIO1C4_EMMC_DATA2 |
+ GPIO1C5_EMMC_DATA3 |
+ GPIO1C6_EMMC_DATA4 |
+ GPIO1C7_EMMC_DATA5);
+ rk_clrsetreg(&grf->gpio1d_iomux,
+ GPIO1D0_MASK | GPIO1D1_MASK |
+ GPIO1D2_MASK | GPIO1D3_MASK,
+ GPIO1D0_EMMC_DATA6 |
+ GPIO1D1_EMMC_DATA7 |
+ GPIO1D2_EMMC_CMD |
+ GPIO1D3_EMMC_PWREN);
+ rk_clrsetreg(&grf->gpio2a_iomux,
+ GPIO2A3_MASK | GPIO2A4_MASK,
+ GPIO2A3_EMMC_RSTNOUT |
+ GPIO2A4_EMMC_CLKOUT);
+ break;
+ case PERIPH_ID_SDCARD:
+ /*
+ * We assume that the BROM has already set this up
+ * correctly for us and that there's nothing to do
+ * here.
+ */
+ break;
+ default:
+ debug("mmc id = %d iomux error!\n", mmc_id);
+ break;
+ }
+}
+
static int rk3368_pinctrl_request(struct udevice *dev, int func, int flags)
{
struct rk3368_pinctrl_priv *priv = dev_get_priv(dev);
@@ -68,6 +605,20 @@ static int rk3368_pinctrl_request(struct udevice *dev, int func, int flags)
case PERIPH_ID_UART4:
pinctrl_rk3368_uart_config(priv, func);
break;
+ case PERIPH_ID_SPI0:
+ case PERIPH_ID_SPI1:
+ case PERIPH_ID_SPI2:
+ pinctrl_rk3368_spi_config(priv, func);
+ break;
+ case PERIPH_ID_EMMC:
+ case PERIPH_ID_SDCARD:
+ pinctrl_rk3368_sdmmc_config(priv->grf, func);
+ break;
+#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
+ case PERIPH_ID_GMAC:
+ pinctrl_rk3368_gmac_config(priv->grf, func);
+ break;
+#endif
default:
return -EINVAL;
}
@@ -97,6 +648,20 @@ static int rk3368_pinctrl_get_periph_id(struct udevice *dev,
return PERIPH_ID_UART1;
case 55:
return PERIPH_ID_UART0;
+ case 44:
+ return PERIPH_ID_SPI0;
+ case 45:
+ return PERIPH_ID_SPI1;
+ case 41:
+ return PERIPH_ID_SPI2;
+ case 35:
+ return PERIPH_ID_EMMC;
+ case 32:
+ return PERIPH_ID_SDCARD;
+#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
+ case 27:
+ return PERIPH_ID_GMAC;
+#endif
}
return -ENOENT;
diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig
index 61afd7a92a4..836be25507b 100644
--- a/drivers/ram/Kconfig
+++ b/drivers/ram/Kconfig
@@ -10,13 +10,22 @@ config RAM
config SPL_RAM
bool "Enable RAM support in SPL"
- depends on RAM
+ depends on RAM && SPL_DM
help
The RAM subsystem adds a small amount of overhead to the image.
If this is acceptable and you have a need to use RAM drivers in
SPL, enable this option. It might provide a cleaner interface to
setting up RAM (e.g. SDRAM / DDR) within SPL.
+config TPL_RAM
+ bool "Enable RAM support in SPL"
+ depends on RAM && TPL_DM
+ help
+ The RAM subsystem adds a small amount of overhead to the image.
+ If this is acceptable and you have a need to use RAM drivers in
+ TPL, enable this option. It might provide a cleaner interface to
+ setting up RAM (e.g. SDRAM / DDR) within TPL.
+
config STM32_SDRAM
bool "Enable STM32 SDRAM support"
depends on RAM
diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile
index c409c480fc7..51ae6be6550 100644
--- a/drivers/ram/Makefile
+++ b/drivers/ram/Makefile
@@ -8,3 +8,5 @@ obj-$(CONFIG_RAM) += ram-uclass.o
obj-$(CONFIG_SANDBOX) += sandbox_ram.o
obj-$(CONFIG_STM32_SDRAM) += stm32_sdram.o
obj-$(CONFIG_ARCH_BMIPS) += bmips_ram.o
+
+obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
diff --git a/drivers/ram/rockchip/Makefile b/drivers/ram/rockchip/Makefile
new file mode 100644
index 00000000000..b09d03c2c9d
--- /dev/null
+++ b/drivers/ram/rockchip/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-$(CONFIG_ROCKCHIP_RK3368) = dmc-rk3368.o
diff --git a/drivers/ram/rockchip/dmc-rk3368.c b/drivers/ram/rockchip/dmc-rk3368.c
new file mode 100644
index 00000000000..ca7b1ff0c84
--- /dev/null
+++ b/drivers/ram/rockchip/dmc-rk3368.c
@@ -0,0 +1,1007 @@
+/*
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <dt-bindings/memory/rk3368-dmc.h>
+#include <dt-structs.h>
+#include <ram.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cru_rk3368.h>
+#include <asm/arch/grf_rk3368.h>
+#include <asm/arch/ddr_rk3368.h>
+#include <asm/arch/sdram.h>
+#include <asm/arch/sdram_common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct dram_info {
+ struct ram_info info;
+ struct clk ddr_clk;
+ struct rk3368_cru *cru;
+ struct rk3368_grf *grf;
+ struct rk3368_ddr_pctl *pctl;
+ struct rk3368_ddrphy *phy;
+ struct rk3368_pmu_grf *pmugrf;
+ struct rk3368_msch *msch;
+};
+
+struct rk3368_sdram_params {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+ struct dtd_rockchip_rk3368_dmc of_plat;
+#endif
+ struct rk3288_sdram_pctl_timing pctl_timing;
+ u32 trefi_mem_ddr3;
+ struct rk3288_sdram_channel chan;
+ struct regmap *map;
+ u32 ddr_freq;
+ u32 memory_schedule;
+ u32 ddr_speed_bin;
+ u32 tfaw_mult;
+};
+
+/* PTCL bits */
+enum {
+ /* PCTL_DFISTCFG0 */
+ DFI_INIT_START = BIT(0),
+ DFI_DATA_BYTE_DISABLE_EN = BIT(2),
+
+ /* PCTL_DFISTCFG1 */
+ DFI_DRAM_CLK_SR_EN = BIT(0),
+ DFI_DRAM_CLK_DPD_EN = BIT(1),
+ ODT_LEN_BL8_W_SHIFT = 16,
+
+ /* PCTL_DFISTCFG2 */
+ DFI_PARITY_INTR_EN = BIT(0),
+ DFI_PARITY_EN = BIT(1),
+
+ /* PCTL_DFILPCFG0 */
+ TLP_RESP_TIME_SHIFT = 16,
+ LP_SR_EN = BIT(8),
+ LP_PD_EN = BIT(0),
+
+ /* PCTL_DFIODTCFG */
+ RANK0_ODT_WRITE_SEL = BIT(3),
+ RANK1_ODT_WRITE_SEL = BIT(11),
+
+ /* PCTL_SCFG */
+ HW_LOW_POWER_EN = BIT(0),
+
+ /* PCTL_MCMD */
+ START_CMD = BIT(31),
+ MCMD_RANK0 = BIT(20),
+ MCMD_RANK1 = BIT(21),
+ DESELECT_CMD = 0,
+ PREA_CMD,
+ REF_CMD,
+ MRS_CMD,
+ ZQCS_CMD,
+ ZQCL_CMD,
+ RSTL_CMD,
+ MRR_CMD = 8,
+ DPDE_CMD,
+
+ /* PCTL_POWCTL */
+ POWER_UP_START = BIT(0),
+
+ /* PCTL_POWSTAT */
+ POWER_UP_DONE = BIT(0),
+
+ /* PCTL_SCTL */
+ INIT_STATE = 0,
+ CFG_STATE,
+ GO_STATE,
+ SLEEP_STATE,
+ WAKEUP_STATE,
+
+ /* PCTL_STAT */
+ LP_TRIG_SHIFT = 4,
+ LP_TRIG_MASK = 7,
+ PCTL_STAT_MSK = 7,
+ INIT_MEM = 0,
+ CONFIG,
+ CONFIG_REQ,
+ ACCESS,
+ ACCESS_REQ,
+ LOW_POWER,
+ LOW_POWER_ENTRY_REQ,
+ LOW_POWER_EXIT_REQ,
+
+ /* PCTL_MCFG */
+ DDR2_DDR3_BL_8 = BIT(0),
+ DDR3_EN = BIT(5),
+ TFAW_TRRD_MULT4 = (0 << 18),
+ TFAW_TRRD_MULT5 = (1 << 18),
+ TFAW_TRRD_MULT6 = (2 << 18),
+};
+
+#define DDR3_MR0_WR(n) \
+ ((n <= 8) ? ((n - 4) << 9) : (((n >> 1) & 0x7) << 9))
+#define DDR3_MR0_CL(n) \
+ ((((n - 4) & 0x7) << 4) | (((n - 4) & 0x8) >> 2))
+#define DDR3_MR0_BL8 \
+ (0 << 0)
+#define DDR3_MR0_DLL_RESET \
+ (1 << 8)
+#define DDR3_MR1_RTT120OHM \
+ ((0 << 9) | (1 << 6) | (0 << 2))
+#define DDR3_MR2_TWL(n) \
+ (((n - 5) & 0x7) << 3)
+
+
+#ifdef CONFIG_TPL_BUILD
+
+static void ddr_set_noc_spr_err_stall(struct rk3368_grf *grf, bool enable)
+{
+ if (enable)
+ rk_setreg(&grf->ddrc0_con0, NOC_RSP_ERR_STALL);
+ else
+ rk_clrreg(&grf->ddrc0_con0, NOC_RSP_ERR_STALL);
+}
+
+static void ddr_set_ddr3_mode(struct rk3368_grf *grf, bool ddr3_mode)
+{
+ if (ddr3_mode)
+ rk_setreg(&grf->ddrc0_con0, MSCH0_MAINDDR3_DDR3);
+ else
+ rk_clrreg(&grf->ddrc0_con0, MSCH0_MAINDDR3_DDR3);
+}
+
+static void ddrphy_config(struct rk3368_ddrphy *phy,
+ u32 tcl, u32 tal, u32 tcwl)
+{
+ int i;
+
+ /* Set to DDR3 mode */
+ clrsetbits_le32(&phy->reg[1], 0x3, 0x0);
+
+ /* DDRPHY_REGB: CL, AL */
+ clrsetbits_le32(&phy->reg[0xb], 0xff, tcl << 4 | tal);
+ /* DDRPHY_REGC: CWL */
+ clrsetbits_le32(&phy->reg[0xc], 0x0f, tcwl);
+
+ /* Update drive-strength */
+ writel(0xcc, &phy->reg[0x11]);
+ writel(0xaa, &phy->reg[0x16]);
+ /*
+ * Update NRCOMP/PRCOMP for all 4 channels (for details of all
+ * affected registers refer to the documentation of DDRPHY_REG20
+ * and DDRPHY_REG21 in the RK3368 TRM.
+ */
+ for (i = 0; i < 4; ++i) {
+ writel(0xcc, &phy->reg[0x20 + i * 0x10]);
+ writel(0x44, &phy->reg[0x21 + i * 0x10]);
+ }
+
+ /* Enable write-leveling calibration bypass */
+ setbits_le32(&phy->reg[2], BIT(3));
+}
+
+static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
+{
+ int i;
+
+ for (i = 0; i < n / sizeof(u32); i++)
+ writel(*src++, dest++);
+}
+
+static void send_command(struct rk3368_ddr_pctl *pctl, u32 rank, u32 cmd)
+{
+ u32 mcmd = START_CMD | cmd | rank;
+
+ debug("%s: writing %x to MCMD\n", __func__, mcmd);
+ writel(mcmd, &pctl->mcmd);
+ while (readl(&pctl->mcmd) & START_CMD)
+ /* spin */;
+}
+
+static void send_mrs(struct rk3368_ddr_pctl *pctl,
+ u32 rank, u32 mr_num, u32 mr_data)
+{
+ u32 mcmd = START_CMD | MRS_CMD | rank | (mr_num << 17) | (mr_data << 4);
+
+ debug("%s: writing %x to MCMD\n", __func__, mcmd);
+ writel(mcmd, &pctl->mcmd);
+ while (readl(&pctl->mcmd) & START_CMD)
+ /* spin */;
+}
+
+static int memory_init(struct rk3368_ddr_pctl *pctl,
+ struct rk3368_sdram_params *params)
+{
+ u32 mr[4];
+ const ulong timeout_ms = 500;
+ ulong tmp;
+
+ /*
+ * Power up DRAM by DDR_PCTL_POWCTL[0] register of PCTL and
+ * wait power up DRAM finish with DDR_PCTL_POWSTAT[0] register
+ * of PCTL.
+ */
+ writel(POWER_UP_START, &pctl->powctl);
+
+ tmp = get_timer(0);
+ do {
+ if (get_timer(tmp) > timeout_ms) {
+ error("%s: POWER_UP_START did not complete in %ld ms\n",
+ __func__, timeout_ms);
+ return -ETIME;
+ }
+ } while (!(readl(&pctl->powstat) & POWER_UP_DONE));
+
+ /* Configure MR0 through MR3 */
+ mr[0] = DDR3_MR0_WR(params->pctl_timing.twr) |
+ DDR3_MR0_CL(params->pctl_timing.tcl) |
+ DDR3_MR0_DLL_RESET;
+ mr[1] = DDR3_MR1_RTT120OHM;
+ mr[2] = DDR3_MR2_TWL(params->pctl_timing.tcwl);
+ mr[3] = 0;
+
+ /*
+ * Also see RK3368 Technical Reference Manual:
+ * "16.6.2 Initialization (DDR3 Initialization Sequence)"
+ */
+ send_command(pctl, MCMD_RANK0 | MCMD_RANK1, DESELECT_CMD);
+ udelay(1);
+ send_command(pctl, MCMD_RANK0 | MCMD_RANK1, PREA_CMD);
+ send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 2, mr[2]);
+ send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 3, mr[3]);
+ send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 1, mr[1]);
+ send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 0, mr[0]);
+ send_command(pctl, MCMD_RANK0 | MCMD_RANK1, ZQCL_CMD);
+
+ return 0;
+}
+
+static void move_to_config_state(struct rk3368_ddr_pctl *pctl)
+{
+ /*
+ * Also see RK3368 Technical Reference Manual:
+ * "16.6.1 State transition of PCTL (Moving to Config State)"
+ */
+ u32 state = readl(&pctl->stat) & PCTL_STAT_MSK;
+
+ switch (state) {
+ case LOW_POWER:
+ writel(WAKEUP_STATE, &pctl->sctl);
+ while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS)
+ /* spin */;
+
+ /* fall-through */
+ case ACCESS:
+ case INIT_MEM:
+ writel(CFG_STATE, &pctl->sctl);
+ while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG)
+ /* spin */;
+ break;
+
+ case CONFIG:
+ return;
+
+ default:
+ break;
+ }
+}
+
+static void move_to_access_state(struct rk3368_ddr_pctl *pctl)
+{
+ /*
+ * Also see RK3368 Technical Reference Manual:
+ * "16.6.1 State transition of PCTL (Moving to Access State)"
+ */
+ u32 state = readl(&pctl->stat) & PCTL_STAT_MSK;
+
+ switch (state) {
+ case LOW_POWER:
+ if (((readl(&pctl->stat) >> LP_TRIG_SHIFT) &
+ LP_TRIG_MASK) == 1)
+ return;
+
+ writel(WAKEUP_STATE, &pctl->sctl);
+ while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS)
+ /* spin */;
+
+ /* fall-through */
+ case INIT_MEM:
+ writel(CFG_STATE, &pctl->sctl);
+ while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG)
+ /* spin */;
+
+ /* fall-through */
+ case CONFIG:
+ writel(GO_STATE, &pctl->sctl);
+ while ((readl(&pctl->stat) & PCTL_STAT_MSK) == CONFIG)
+ /* spin */;
+ break;
+
+ case ACCESS:
+ return;
+
+ default:
+ break;
+ }
+}
+
+static void ddrctl_reset(struct rk3368_cru *cru)
+{
+ const u32 ctl_reset = BIT(3) | BIT(2);
+ const u32 phy_reset = BIT(1) | BIT(0);
+
+ /*
+ * The PHY reset should be released before the PCTL reset.
+ *
+ * Note that the following sequence (including the number of
+ * us to delay between releasing the PHY and PCTL reset) has
+ * been adapted per feedback received from Rockchips, so do
+ * not try to optimise.
+ */
+ rk_setreg(&cru->softrst_con[10], ctl_reset | phy_reset);
+ udelay(1);
+ rk_clrreg(&cru->softrst_con[10], phy_reset);
+ udelay(5);
+ rk_clrreg(&cru->softrst_con[10], ctl_reset);
+}
+
+static void ddrphy_reset(struct rk3368_ddrphy *ddrphy)
+{
+ /*
+ * The analog part of the PHY should be release at least 1000
+ * DRAM cycles before the digital part of the PHY (waiting for
+ * 5us will ensure this for a DRAM clock as low as 200MHz).
+ */
+ clrbits_le32(&ddrphy->reg[0], BIT(3) | BIT(2));
+ udelay(1);
+ setbits_le32(&ddrphy->reg[0], BIT(2));
+ udelay(5);
+ setbits_le32(&ddrphy->reg[0], BIT(3));
+}
+
+static void ddrphy_config_delays(struct rk3368_ddrphy *ddrphy, u32 freq)
+{
+ u32 dqs_dll_delay;
+
+ setbits_le32(&ddrphy->reg[0x13], BIT(4));
+ clrbits_le32(&ddrphy->reg[0x14], BIT(3));
+
+ setbits_le32(&ddrphy->reg[0x26], BIT(4));
+ clrbits_le32(&ddrphy->reg[0x27], BIT(3));
+
+ setbits_le32(&ddrphy->reg[0x36], BIT(4));
+ clrbits_le32(&ddrphy->reg[0x37], BIT(3));
+
+ setbits_le32(&ddrphy->reg[0x46], BIT(4));
+ clrbits_le32(&ddrphy->reg[0x47], BIT(3));
+
+ setbits_le32(&ddrphy->reg[0x56], BIT(4));
+ clrbits_le32(&ddrphy->reg[0x57], BIT(3));
+
+ if (freq <= 400000000)
+ setbits_le32(&ddrphy->reg[0xa4], 0x1f);
+ else
+ clrbits_le32(&ddrphy->reg[0xa4], 0x1f);
+
+ if (freq < 681000000)
+ dqs_dll_delay = 3; /* 67.5 degree delay */
+ else
+ dqs_dll_delay = 2; /* 45 degree delay */
+
+ writel(dqs_dll_delay, &ddrphy->reg[0x28]);
+ writel(dqs_dll_delay, &ddrphy->reg[0x38]);
+ writel(dqs_dll_delay, &ddrphy->reg[0x48]);
+ writel(dqs_dll_delay, &ddrphy->reg[0x58]);
+}
+
+static int dfi_cfg(struct rk3368_ddr_pctl *pctl)
+{
+ const ulong timeout_ms = 200;
+ ulong tmp;
+
+ writel(DFI_DATA_BYTE_DISABLE_EN, &pctl->dfistcfg0);
+
+ writel(DFI_DRAM_CLK_SR_EN | DFI_DRAM_CLK_DPD_EN,
+ &pctl->dfistcfg1);
+ writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2);
+ writel(7 << TLP_RESP_TIME_SHIFT | LP_SR_EN | LP_PD_EN,
+ &pctl->dfilpcfg0);
+
+ writel(1, &pctl->dfitphyupdtype0);
+
+ writel(0x1f, &pctl->dfitphyrdlat);
+ writel(0, &pctl->dfitphywrdata);
+ writel(0, &pctl->dfiupdcfg); /* phyupd and ctrlupd disabled */
+
+ setbits_le32(&pctl->dfistcfg0, DFI_INIT_START);
+
+ tmp = get_timer(0);
+ do {
+ if (get_timer(tmp) > timeout_ms) {
+ error("%s: DFI init did not complete within %ld ms\n",
+ __func__, timeout_ms);
+ return -ETIME;
+ }
+ } while ((readl(&pctl->dfiststat0) & 1) == 0);
+
+ return 0;
+}
+
+static inline u32 ps_to_tCK(const u32 ps, const ulong freq)
+{
+ const ulong MHz = 1000000;
+ return DIV_ROUND_UP(ps * freq, 1000000 * MHz);
+}
+
+static inline u32 ns_to_tCK(const u32 ns, const ulong freq)
+{
+ return ps_to_tCK(ns * 1000, freq);
+}
+
+static inline u32 tCK_to_ps(const ulong tCK, const ulong freq)
+{
+ const ulong MHz = 1000000;
+ return DIV_ROUND_UP(tCK * 1000000 * MHz, freq);
+}
+
+static int pctl_calc_timings(struct rk3368_sdram_params *params,
+ ulong freq)
+{
+ struct rk3288_sdram_pctl_timing *pctl_timing = &params->pctl_timing;
+ const ulong MHz = 1000000;
+ u32 tccd;
+ u32 tfaw_as_ps;
+
+ if (params->ddr_speed_bin != DDR3_1600K) {
+ error("%s: unimplemented DDR3 speed bin %d\n",
+ __func__, params->ddr_speed_bin);
+ return -1;
+ }
+
+ /* PCTL is clocked at 1/2 the DRAM clock; err on the side of caution */
+ pctl_timing->togcnt1u = DIV_ROUND_UP(freq, 2 * MHz);
+ pctl_timing->togcnt100n = DIV_ROUND_UP(freq / 10, 2 * MHz);
+
+ pctl_timing->tinit = 200; /* 200 usec */
+ pctl_timing->trsth = 500; /* 500 usec */
+ pctl_timing->trefi = 78; /* 7.8usec = 78 * 100ns */
+ params->trefi_mem_ddr3 = ns_to_tCK(pctl_timing->trefi * 100, freq);
+
+ if (freq <= (400 * MHz)) {
+ pctl_timing->tcl = 6;
+ pctl_timing->tcwl = 10;
+ } else if (freq <= (533 * MHz)) {
+ pctl_timing->tcl = 8;
+ pctl_timing->tcwl = 6;
+ } else if (freq <= (666 * MHz)) {
+ pctl_timing->tcl = 10;
+ pctl_timing->tcwl = 7;
+ } else {
+ pctl_timing->tcl = 11;
+ pctl_timing->tcwl = 8;
+ }
+
+ pctl_timing->tmrd = 4; /* 4 tCK (all speed bins) */
+ pctl_timing->trfc = ns_to_tCK(350, freq); /* tRFC: 350 (max) @ 8GBit */
+ pctl_timing->trp = max(4u, ps_to_tCK(13750, freq));
+ /*
+ * JESD-79:
+ * READ to WRITE Command Delay = RL + tCCD / 2 + 2tCK - WL
+ */
+ tccd = 4;
+ pctl_timing->trtw = pctl_timing->tcl + tccd/2 + 2 - pctl_timing->tcwl;
+ pctl_timing->tal = 0;
+ pctl_timing->tras = ps_to_tCK(35000, freq);
+ pctl_timing->trc = ps_to_tCK(48750, freq);
+ pctl_timing->trcd = ps_to_tCK(13750, freq);
+ pctl_timing->trrd = max(4u, ps_to_tCK(7500, freq));
+ pctl_timing->trtp = max(4u, ps_to_tCK(7500, freq));
+ pctl_timing->twr = ps_to_tCK(15000, freq);
+ /* The DDR3 mode-register does only support even values for tWR > 8. */
+ if (pctl_timing->twr > 8)
+ pctl_timing->twr = (pctl_timing->twr + 1) & ~1;
+ pctl_timing->twtr = max(4u, ps_to_tCK(7500, freq));
+ pctl_timing->texsr = 512; /* tEXSR(max) is tDLLLK */
+ pctl_timing->txp = max(3u, ps_to_tCK(6000, freq));
+ pctl_timing->txpdll = max(10u, ps_to_tCK(24000, freq));
+ pctl_timing->tzqcs = max(64u, ps_to_tCK(80000, freq));
+ pctl_timing->tzqcsi = 10000; /* as used by Rockchip */
+ pctl_timing->tdqs = 1; /* fixed for DDR3 */
+ pctl_timing->tcksre = max(5u, ps_to_tCK(10000, freq));
+ pctl_timing->tcksrx = max(5u, ps_to_tCK(10000, freq));
+ pctl_timing->tcke = max(3u, ps_to_tCK(5000, freq));
+ pctl_timing->tmod = max(12u, ps_to_tCK(15000, freq));
+ pctl_timing->trstl = ns_to_tCK(100, freq);
+ pctl_timing->tzqcl = max(256u, ps_to_tCK(320000, freq)); /* tZQoper */
+ pctl_timing->tmrr = 0;
+ pctl_timing->tckesr = pctl_timing->tcke + 1; /* JESD-79: tCKE + 1tCK */
+ pctl_timing->tdpd = 0; /* RK3368 TRM: "allowed values for DDR3: 0" */
+
+
+ /*
+ * The controller can represent tFAW as 4x, 5x or 6x tRRD only.
+ * We want to use the smallest multiplier that satisfies the tFAW
+ * requirements of the given speed-bin. If necessary, we stretch out
+ * tRRD to allow us to operate on a 6x multiplier for tFAW.
+ */
+ tfaw_as_ps = 40000; /* 40ns: tFAW for DDR3-1600K, 2KB page-size */
+ if (tCK_to_ps(pctl_timing->trrd * 6, freq) < tfaw_as_ps) {
+ /* If tFAW is > 6 x tRRD, we need to stretch tRRD */
+ pctl_timing->trrd = ps_to_tCK(DIV_ROUND_UP(40000, 6), freq);
+ params->tfaw_mult = TFAW_TRRD_MULT6;
+ } else if (tCK_to_ps(pctl_timing->trrd * 5, freq) < tfaw_as_ps) {
+ params->tfaw_mult = TFAW_TRRD_MULT6;
+ } else if (tCK_to_ps(pctl_timing->trrd * 4, freq) < tfaw_as_ps) {
+ params->tfaw_mult = TFAW_TRRD_MULT5;
+ } else {
+ params->tfaw_mult = TFAW_TRRD_MULT4;
+ }
+
+ return 0;
+}
+
+static void pctl_cfg(struct rk3368_ddr_pctl *pctl,
+ struct rk3368_sdram_params *params,
+ struct rk3368_grf *grf)
+{
+ /* Configure PCTL timing registers */
+ params->pctl_timing.trefi |= BIT(31); /* see PCTL_TREFI */
+ copy_to_reg(&pctl->togcnt1u, &params->pctl_timing.togcnt1u,
+ sizeof(params->pctl_timing));
+ writel(params->trefi_mem_ddr3, &pctl->trefi_mem_ddr3);
+
+ /* Set up ODT write selector and ODT write length */
+ writel((RANK0_ODT_WRITE_SEL | RANK1_ODT_WRITE_SEL), &pctl->dfiodtcfg);
+ writel(7 << ODT_LEN_BL8_W_SHIFT, &pctl->dfiodtcfg1);
+
+ /* Set up the CL/CWL-dependent timings of DFI */
+ writel((params->pctl_timing.tcl - 1) / 2 - 1, &pctl->dfitrddataen);
+ writel((params->pctl_timing.tcwl - 1) / 2 - 1, &pctl->dfitphywrlat);
+
+ /* DDR3 */
+ writel(params->tfaw_mult | DDR3_EN | DDR2_DDR3_BL_8, &pctl->mcfg);
+ writel(0x001c0004, &grf->ddrc0_con0);
+
+ setbits_le32(&pctl->scfg, HW_LOW_POWER_EN);
+}
+
+static int ddrphy_data_training(struct rk3368_ddr_pctl *pctl,
+ struct rk3368_ddrphy *ddrphy)
+{
+ const u32 trefi = readl(&pctl->trefi);
+ const ulong timeout_ms = 500;
+ ulong tmp;
+
+ /* disable auto-refresh */
+ writel(0 | BIT(31), &pctl->trefi);
+
+ clrsetbits_le32(&ddrphy->reg[2], 0x33, 0x20);
+ clrsetbits_le32(&ddrphy->reg[2], 0x33, 0x21);
+
+ tmp = get_timer(0);
+ do {
+ if (get_timer(tmp) > timeout_ms) {
+ error("%s: did not complete within %ld ms\n",
+ __func__, timeout_ms);
+ return -ETIME;
+ }
+ } while ((readl(&ddrphy->reg[0xff]) & 0xf) != 0xf);
+
+ send_command(pctl, MCMD_RANK0 | MCMD_RANK1, PREA_CMD);
+ clrsetbits_le32(&ddrphy->reg[2], 0x33, 0x20);
+ /* resume auto-refresh */
+ writel(trefi | BIT(31), &pctl->trefi);
+
+ return 0;
+}
+
+static int sdram_col_row_detect(struct udevice *dev)
+{
+ struct dram_info *priv = dev_get_priv(dev);
+ struct rk3368_sdram_params *params = dev_get_platdata(dev);
+ struct rk3368_ddr_pctl *pctl = priv->pctl;
+ struct rk3368_msch *msch = priv->msch;
+ const u32 test_pattern = 0x5aa5f00f;
+ int row, col;
+ uintptr_t addr;
+
+ move_to_config_state(pctl);
+ writel(6, &msch->ddrconf);
+ move_to_access_state(pctl);
+
+ /* Detect col */
+ for (col = 11; col >= 9; col--) {
+ writel(0, CONFIG_SYS_SDRAM_BASE);
+ addr = CONFIG_SYS_SDRAM_BASE +
+ (1 << (col + params->chan.bw - 1));
+ writel(test_pattern, addr);
+ if ((readl(addr) == test_pattern) &&
+ (readl(CONFIG_SYS_SDRAM_BASE) == 0))
+ break;
+ }
+
+ if (col == 8) {
+ error("%s: col detect error\n", __func__);
+ return -EINVAL;
+ }
+
+ move_to_config_state(pctl);
+ writel(15, &msch->ddrconf);
+ move_to_access_state(pctl);
+
+ /* Detect row*/
+ for (row = 16; row >= 12; row--) {
+ writel(0, CONFIG_SYS_SDRAM_BASE);
+ addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1));
+ writel(test_pattern, addr);
+ if ((readl(addr) == test_pattern) &&
+ (readl(CONFIG_SYS_SDRAM_BASE) == 0))
+ break;
+ }
+
+ if (row == 11) {
+ error("%s: row detect error\n", __func__);
+ return -EINVAL;
+ }
+
+ /* Record results */
+ debug("%s: col %d, row %d\n", __func__, col, row);
+ params->chan.col = col;
+ params->chan.cs0_row = row;
+ params->chan.cs1_row = row;
+ params->chan.row_3_4 = 0;
+
+ return 0;
+}
+
+static int msch_niu_config(struct rk3368_msch *msch,
+ struct rk3368_sdram_params *params)
+{
+ int i;
+ const u8 cols = params->chan.col - ((params->chan.bw == 2) ? 0 : 1);
+ const u8 rows = params->chan.cs0_row;
+
+ /*
+ * The DDR address-translation table always assumes a 32bit
+ * bus and the comparison below takes care of adjusting for
+ * a 16bit bus (i.e. one column-address is consumed).
+ */
+ const struct {
+ u8 rows;
+ u8 columns;
+ u8 type;
+ } ddrconf_table[] = {
+ /*
+ * C-B-R-D patterns are first. For these we require an
+ * exact match for the columns and rows (as there's
+ * one entry per possible configuration).
+ */
+ [0] = { .rows = 13, .columns = 10, .type = DMC_MSCH_CBRD },
+ [1] = { .rows = 14, .columns = 10, .type = DMC_MSCH_CBRD },
+ [2] = { .rows = 15, .columns = 10, .type = DMC_MSCH_CBRD },
+ [3] = { .rows = 16, .columns = 10, .type = DMC_MSCH_CBRD },
+ [4] = { .rows = 14, .columns = 11, .type = DMC_MSCH_CBRD },
+ [5] = { .rows = 15, .columns = 11, .type = DMC_MSCH_CBRD },
+ [6] = { .rows = 16, .columns = 11, .type = DMC_MSCH_CBRD },
+ [7] = { .rows = 13, .columns = 9, .type = DMC_MSCH_CBRD },
+ [8] = { .rows = 14, .columns = 9, .type = DMC_MSCH_CBRD },
+ [9] = { .rows = 15, .columns = 9, .type = DMC_MSCH_CBRD },
+ [10] = { .rows = 16, .columns = 9, .type = DMC_MSCH_CBRD },
+ /*
+ * 11 through 13 are C-R-B-D patterns. These are
+ * matched for an exact number of columns and to
+ * ensure that the hardware uses at least as many rows
+ * as the pattern requires (i.e. we make sure that
+ * there's no gaps up until we hit the device/chip-select;
+ * however, these patterns can accept up to 16 rows,
+ * as the row-address continues right after the CS
+ * switching)
+ */
+ [11] = { .rows = 15, .columns = 10, .type = DMC_MSCH_CRBD },
+ [12] = { .rows = 14, .columns = 11, .type = DMC_MSCH_CRBD },
+ [13] = { .rows = 13, .columns = 10, .type = DMC_MSCH_CRBD },
+ /*
+ * 14 and 15 are catch-all variants using a C-B-D-R
+ * scheme (i.e. alternating the chip-select every time
+ * C-B overflows) and stuffing the remaining C-bits
+ * into the top. Matching needs to make sure that the
+ * number of columns is either an exact match (i.e. we
+ * can use less the the maximum number of rows) -or-
+ * that the columns exceed what is given in this table
+ * and the rows are an exact match (in which case the
+ * remaining C-bits will be stuffed onto the top after
+ * the device/chip-select switches).
+ */
+ [14] = { .rows = 16, .columns = 10, .type = DMC_MSCH_CBDR },
+ [15] = { .rows = 16, .columns = 9, .type = DMC_MSCH_CBDR },
+ };
+
+ /*
+ * For C-B-R-D, we need an exact match (i.e. both for the number of
+ * columns and rows), while for C-B-D-R, only the the number of
+ * columns needs to match.
+ */
+ for (i = 0; i < ARRAY_SIZE(ddrconf_table); i++) {
+ bool match = false;
+
+ /* If this entry if for a different matcher, then skip it */
+ if (ddrconf_table[i].type != params->memory_schedule)
+ continue;
+
+ /*
+ * Match according to the rules (exact/inexact/at-least)
+ * documented in the ddrconf_table above.
+ */
+ switch (params->memory_schedule) {
+ case DMC_MSCH_CBRD:
+ match = (ddrconf_table[i].columns == cols) &&
+ (ddrconf_table[i].rows == rows);
+ break;
+
+ case DMC_MSCH_CRBD:
+ match = (ddrconf_table[i].columns == cols) &&
+ (ddrconf_table[i].rows <= rows);
+ break;
+
+ case DMC_MSCH_CBDR:
+ match = (ddrconf_table[i].columns == cols) ||
+ ((ddrconf_table[i].columns <= cols) &&
+ (ddrconf_table[i].rows == rows));
+ break;
+
+ default:
+ break;
+ }
+
+ if (match) {
+ debug("%s: setting ddrconf 0x%x\n", __func__, i);
+ writel(i, &msch->ddrconf);
+ return 0;
+ }
+ }
+
+ error("%s: ddrconf (NIU config) not found\n", __func__);
+ return -EINVAL;
+}
+
+static void dram_all_config(struct udevice *dev)
+{
+ struct dram_info *priv = dev_get_priv(dev);
+ struct rk3368_pmu_grf *pmugrf = priv->pmugrf;
+ struct rk3368_sdram_params *params = dev_get_platdata(dev);
+ const struct rk3288_sdram_channel *info = &params->chan;
+ u32 sys_reg = 0;
+ const int chan = 0;
+
+ sys_reg |= DDR3 << SYS_REG_DDRTYPE_SHIFT;
+ sys_reg |= 0 << SYS_REG_NUM_CH_SHIFT;
+
+ sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(chan);
+ sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(chan);
+ sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(chan);
+ sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(chan);
+ sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(chan);
+ sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(chan);
+ sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(chan);
+ sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(chan);
+ sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(chan);
+
+ writel(sys_reg, &pmugrf->os_reg[2]);
+}
+
+static int setup_sdram(struct udevice *dev)
+{
+ struct dram_info *priv = dev_get_priv(dev);
+ struct rk3368_sdram_params *params = dev_get_platdata(dev);
+
+ struct rk3368_ddr_pctl *pctl = priv->pctl;
+ struct rk3368_ddrphy *ddrphy = priv->phy;
+ struct rk3368_cru *cru = priv->cru;
+ struct rk3368_grf *grf = priv->grf;
+ struct rk3368_msch *msch = priv->msch;
+
+ int ret;
+
+ /* The input clock (i.e. DPLL) needs to be 2x the DRAM frequency */
+ ret = clk_set_rate(&priv->ddr_clk, 2 * params->ddr_freq);
+ if (ret < 0) {
+ debug("%s: could not set DDR clock: %d\n", __func__, ret);
+ return ret;
+ }
+
+ /* Update the read-latency for the RK3368 */
+ writel(0x32, &msch->readlatency);
+
+ /* Initialise the DDR PCTL and DDR PHY */
+ ddrctl_reset(cru);
+ ddrphy_reset(ddrphy);
+ ddrphy_config_delays(ddrphy, params->ddr_freq);
+ dfi_cfg(pctl);
+ /* Configure relative system information of grf_ddrc0_con0 register */
+ ddr_set_ddr3_mode(grf, true);
+ ddr_set_noc_spr_err_stall(grf, true);
+ /* Calculate timings */
+ pctl_calc_timings(params, params->ddr_freq);
+ /* Initialise the device timings in protocol controller */
+ pctl_cfg(pctl, params, grf);
+ /* Configure AL, CL ... information of PHY registers */
+ ddrphy_config(ddrphy,
+ params->pctl_timing.tcl,
+ params->pctl_timing.tal,
+ params->pctl_timing.tcwl);
+
+ /* Initialize DRAM and configure with mode-register values */
+ ret = memory_init(pctl, params);
+ if (ret)
+ goto error;
+
+ move_to_config_state(pctl);
+ /* Perform data-training */
+ ddrphy_data_training(pctl, ddrphy);
+ move_to_access_state(pctl);
+
+ /* TODO(prt): could detect rank in training... */
+ params->chan.rank = 2;
+ /* TODO(prt): bus width is not auto-detected (yet)... */
+ params->chan.bw = 2; /* 32bit wide bus */
+ params->chan.dbw = params->chan.dbw; /* 32bit wide bus */
+
+ /* DDR3 is always 8 bank */
+ params->chan.bk = 3;
+ /* Detect col and row number */
+ ret = sdram_col_row_detect(dev);
+ if (ret)
+ goto error;
+
+ /* Configure NIU DDR configuration */
+ ret = msch_niu_config(msch, params);
+ if (ret)
+ goto error;
+
+ /* set up OS_REG to communicate w/ next stage and OS */
+ dram_all_config(dev);
+
+ return 0;
+
+error:
+ printf("DRAM init failed!\n");
+ hang();
+}
+#endif
+
+static int rk3368_dmc_ofdata_to_platdata(struct udevice *dev)
+{
+ int ret = 0;
+
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+ struct rk3368_sdram_params *plat = dev_get_platdata(dev);
+
+ ret = regmap_init_mem(dev, &plat->map);
+ if (ret)
+ return ret;
+#endif
+
+ return ret;
+}
+
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+static int conv_of_platdata(struct udevice *dev)
+{
+ struct rk3368_sdram_params *plat = dev_get_platdata(dev);
+ struct dtd_rockchip_rk3368_dmc *of_plat = &plat->of_plat;
+ int ret;
+
+ plat->ddr_freq = of_plat->rockchip_ddr_frequency;
+ plat->ddr_speed_bin = of_plat->rockchip_ddr_speed_bin;
+ plat->memory_schedule = of_plat->rockchip_memory_schedule;
+
+ ret = regmap_init_mem_platdata(dev, of_plat->reg,
+ ARRAY_SIZE(of_plat->reg) / 2,
+ &plat->map);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+#endif
+
+static int rk3368_dmc_probe(struct udevice *dev)
+{
+#ifdef CONFIG_TPL_BUILD
+ struct rk3368_sdram_params *plat = dev_get_platdata(dev);
+ struct rk3368_ddr_pctl *pctl;
+ struct rk3368_ddrphy *ddrphy;
+ struct rk3368_cru *cru;
+ struct rk3368_grf *grf;
+ struct rk3368_msch *msch;
+ int ret;
+ struct udevice *dev_clk;
+#endif
+ struct dram_info *priv = dev_get_priv(dev);
+
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+ ret = conv_of_platdata(dev);
+ if (ret)
+ return ret;
+#endif
+
+ priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
+ debug("%s: pmugrf=%p\n", __func__, priv->pmugrf);
+
+#ifdef CONFIG_TPL_BUILD
+ pctl = regmap_get_range(plat->map, 0);
+ ddrphy = regmap_get_range(plat->map, 1);
+ msch = syscon_get_first_range(ROCKCHIP_SYSCON_MSCH);
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+
+ priv->pctl = pctl;
+ priv->phy = ddrphy;
+ priv->msch = msch;
+ priv->grf = grf;
+
+ ret = rockchip_get_clk(&dev_clk);
+ if (ret)
+ return ret;
+ priv->ddr_clk.id = CLK_DDR;
+ ret = clk_request(dev_clk, &priv->ddr_clk);
+ if (ret)
+ return ret;
+
+ cru = rockchip_get_cru();
+ priv->cru = cru;
+ if (IS_ERR(priv->cru))
+ return PTR_ERR(priv->cru);
+
+ ret = setup_sdram(dev);
+ if (ret)
+ return ret;
+#endif
+
+ priv->info.base = 0;
+ priv->info.size =
+ rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg[2]);
+
+ /*
+ * we use the 0x00000000~0xfdffffff space since 0xff000000~0xffffffff
+ * is SoC register space (i.e. reserved), and 0xfe000000~0xfeffffff is
+ * inaccessible for some IP controller.
+ */
+ priv->info.size = min(priv->info.size, (size_t)0xfe000000);
+
+ return 0;
+}
+
+static int rk3368_dmc_get_info(struct udevice *dev, struct ram_info *info)
+{
+ struct dram_info *priv = dev_get_priv(dev);
+
+ *info = priv->info;
+ return 0;
+}
+
+static struct ram_ops rk3368_dmc_ops = {
+ .get_info = rk3368_dmc_get_info,
+};
+
+
+static const struct udevice_id rk3368_dmc_ids[] = {
+ { .compatible = "rockchip,rk3368-dmc" },
+ { }
+};
+
+U_BOOT_DRIVER(dmc_rk3368) = {
+ .name = "rockchip_rk3368_dmc",
+ .id = UCLASS_RAM,
+ .of_match = rk3368_dmc_ids,
+ .ops = &rk3368_dmc_ops,
+ .probe = rk3368_dmc_probe,
+ .priv_auto_alloc_size = sizeof(struct dram_info),
+ .ofdata_to_platdata = rk3368_dmc_ofdata_to_platdata,
+ .probe = rk3368_dmc_probe,
+ .priv_auto_alloc_size = sizeof(struct dram_info),
+ .platdata_auto_alloc_size = sizeof(struct rk3368_sdram_params),
+};
diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c
index 7921ea0d754..c70d6362770 100644
--- a/drivers/spi/rk_spi.c
+++ b/drivers/spi/rk_spi.c
@@ -210,6 +210,14 @@ static int rockchip_spi_ofdata_to_platdata(struct udevice *bus)
static int rockchip_spi_calc_modclk(ulong max_freq)
{
+ /*
+ * While this is not strictly correct for the RK3368, as the
+ * GPLL will be 576MHz, things will still work, as the
+ * clk_set_rate(...) implementation in our clock-driver will
+ * chose the next closest rate not exceeding what we request
+ * based on the output of this function.
+ */
+
unsigned div;
const unsigned long gpll_hz = 594000000UL;
@@ -443,6 +451,7 @@ static const struct dm_spi_ops rockchip_spi_ops = {
static const struct udevice_id rockchip_spi_ids[] = {
{ .compatible = "rockchip,rk3288-spi" },
+ { .compatible = "rockchip,rk3368-spi" },
{ .compatible = "rockchip,rk3399-spi" },
{ }
};
diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index c6663033311..13f122350b2 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -9,6 +9,24 @@ config TIMER
will be used. The timer is usually a 32 bits free-running up
counter. There may be no real tick, and no timer interrupt.
+config SPL_TIMER
+ bool "Enable driver model for timer drivers in SPL"
+ depends on TIMER && SPL
+ help
+ Enable support for timer drivers in SPL. These can be used to get
+ a timer value when in SPL, or perhaps for implementing a delay
+ function. This enables the drivers in drivers/timer as part of an
+ SPL build.
+
+config TPL_TIMER
+ bool "Enable driver model for timer drivers in TPL"
+ depends on TIMER && TPL
+ help
+ Enable support for timer drivers in TPL. These can be used to get
+ a timer value when in TPL, or perhaps for implementing a delay
+ function. This enables the drivers in drivers/timer as part of an
+ TPL build.
+
config TIMER_EARLY
bool "Allow timer to be used early in U-Boot"
depends on TIMER
@@ -85,4 +103,11 @@ config AE3XX_TIMER
help
Select this to enable a timer for AE3XX devices.
+config ROCKCHIP_TIMER
+ bool "Rockchip timer support"
+ depends on TIMER
+ help
+ Select this to enable support for the timer found on
+ Rockchip devices.
+
endmenu
diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
index ced7bd66bd3..fa7ce7c8358 100644
--- a/drivers/timer/Makefile
+++ b/drivers/timer/Makefile
@@ -4,7 +4,7 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_TIMER) += timer-uclass.o
+obj-y += timer-uclass.o
obj-$(CONFIG_ALTERA_TIMER) += altera_timer.o
obj-$(CONFIG_SANDBOX_TIMER) += sandbox_timer.o
obj-$(CONFIG_X86_TSC_TIMER) += tsc_timer.o
@@ -14,3 +14,4 @@ obj-$(CONFIG_STI_TIMER) += sti-timer.o
obj-$(CONFIG_ARC_TIMER) += arc_timer.o
obj-$(CONFIG_AG101P_TIMER) += ag101p_timer.o
obj-$(CONFIG_AE3XX_TIMER) += ae3xx_timer.o
+obj-$(CONFIG_ROCKCHIP_TIMER) += rockchip_timer.o
diff --git a/drivers/timer/rockchip_timer.c b/drivers/timer/rockchip_timer.c
new file mode 100644
index 00000000000..0848033c662
--- /dev/null
+++ b/drivers/timer/rockchip_timer.c
@@ -0,0 +1,107 @@
+/*
+ * Copyright (C) 2017 Theobroma Systems Design und Consulting GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <mapmem.h>
+#include <asm/arch/timer.h>
+#include <dt-structs.h>
+#include <timer.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+struct rockchip_timer_plat {
+ struct dtd_rockchip_rk3368_timer dtd;
+};
+#endif
+
+/* Driver private data. Contains timer id. Could be either 0 or 1. */
+struct rockchip_timer_priv {
+ struct rk_timer *timer;
+};
+
+static int rockchip_timer_get_count(struct udevice *dev, u64 *count)
+{
+ struct rockchip_timer_priv *priv = dev_get_priv(dev);
+ uint64_t timebase_h, timebase_l;
+ uint64_t cntr;
+
+ timebase_l = readl(&priv->timer->timer_curr_value0);
+ timebase_h = readl(&priv->timer->timer_curr_value1);
+
+ /* timers are down-counting */
+ cntr = timebase_h << 32 | timebase_l;
+ *count = ~0ull - cntr;
+ return 0;
+}
+
+static int rockchip_clk_ofdata_to_platdata(struct udevice *dev)
+{
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+ struct rockchip_timer_priv *priv = dev_get_priv(dev);
+
+ priv->timer = (struct rk_timer *)devfdt_get_addr(dev);
+#endif
+
+ return 0;
+}
+
+static int rockchip_timer_start(struct udevice *dev)
+{
+ struct rockchip_timer_priv *priv = dev_get_priv(dev);
+ const uint64_t reload_val = ~0uLL;
+ const uint32_t reload_val_l = reload_val & 0xffffffff;
+ const uint32_t reload_val_h = reload_val >> 32;
+
+ /* disable timer and reset all control */
+ writel(0, &priv->timer->timer_ctrl_reg);
+ /* write reload value */
+ writel(reload_val_l, &priv->timer->timer_load_count0);
+ writel(reload_val_h, &priv->timer->timer_load_count1);
+ /* enable timer */
+ writel(1, &priv->timer->timer_ctrl_reg);
+
+ return 0;
+}
+
+static int rockchip_timer_probe(struct udevice *dev)
+{
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+ struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct rockchip_timer_priv *priv = dev_get_priv(dev);
+ struct rockchip_timer_plat *plat = dev_get_platdata(dev);
+
+ priv->timer = map_sysmem(plat->dtd.reg[1], plat->dtd.reg[3]);
+ uc_priv->clock_rate = plat->dtd.clock_frequency;
+#endif
+
+ return rockchip_timer_start(dev);
+}
+
+static const struct timer_ops rockchip_timer_ops = {
+ .get_count = rockchip_timer_get_count,
+};
+
+static const struct udevice_id rockchip_timer_ids[] = {
+ { .compatible = "rockchip,rk3368-timer" },
+ {}
+};
+
+U_BOOT_DRIVER(arc_timer) = {
+ .name = "rockchip_rk3368_timer",
+ .id = UCLASS_TIMER,
+ .of_match = rockchip_timer_ids,
+ .probe = rockchip_timer_probe,
+ .ops = &rockchip_timer_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+ .priv_auto_alloc_size = sizeof(struct rockchip_timer_priv),
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+ .platdata_auto_alloc_size = sizeof(struct rockchip_timer_plat),
+#endif
+ .ofdata_to_platdata = rockchip_clk_ofdata_to_platdata,
+};
diff --git a/drivers/timer/timer-uclass.c b/drivers/timer/timer-uclass.c
index ec10b282882..a84755f4c5a 100644
--- a/drivers/timer/timer-uclass.c
+++ b/drivers/timer/timer-uclass.c
@@ -42,6 +42,7 @@ unsigned long notrace timer_get_rate(struct udevice *dev)
static int timer_pre_probe(struct udevice *dev)
{
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
struct clk timer_clk;
int err;
@@ -56,6 +57,7 @@ static int timer_pre_probe(struct udevice *dev)
} else
uc_priv->clock_rate = fdtdec_get_int(gd->fdt_blob,
dev_of_offset(dev), "clock-frequency", 0);
+#endif
return 0;
}
@@ -81,16 +83,18 @@ u64 timer_conv_64(u32 count)
int notrace dm_timer_init(void)
{
- const void *blob = gd->fdt_blob;
+ __maybe_unused const void *blob = gd->fdt_blob;
struct udevice *dev = NULL;
- int node;
+ int node = -ENOENT;
int ret;
if (gd->timer)
return 0;
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
/* Check for a chosen timer to be used for tick */
node = fdtdec_get_chosen_node(blob, "tick-timer");
+#endif
if (node < 0) {
/* No chosen timer, trying first available timer */
ret = uclass_first_device_err(UCLASS_TIMER, &dev);
generated by cgit v1.2.3 (git 2.0.4) at 2024-11-10 04:40:50 +0000