diff options
Diffstat (limited to 'drivers')
97 files changed, 1118 insertions, 437 deletions
diff --git a/drivers/clk/aspeed/clk_ast2600.c b/drivers/clk/aspeed/clk_ast2600.c index eecfacd7fc0..a15909329bb 100644 --- a/drivers/clk/aspeed/clk_ast2600.c +++ b/drivers/clk/aspeed/clk_ast2600.c @@ -1143,8 +1143,6 @@ static void ast2600_clk_dump(struct udevice *dev) ret = clk_get_rate(&clk); rate = ret; - clk_free(&clk); - if (ret == -EINVAL) { printf("clk ID %lu not supported yet\n", aspeed_clk_names[i].id); diff --git a/drivers/clk/at91/compat.c b/drivers/clk/at91/compat.c index 2fdc2fbd554..ee67093c607 100644 --- a/drivers/clk/at91/compat.c +++ b/drivers/clk/at91/compat.c @@ -516,7 +516,6 @@ static ulong periph_get_rate(struct clk *clk) { struct udevice *dev; struct clk clk_dev; - ulong clk_rate; int ret; dev = dev_get_parent(clk->dev); @@ -525,11 +524,7 @@ static ulong periph_get_rate(struct clk *clk) if (ret) return ret; - clk_rate = clk_get_rate(&clk_dev); - - clk_free(&clk_dev); - - return clk_rate; + return clk_get_rate(&clk_dev); } static struct clk_ops periph_clk_ops = { @@ -762,7 +757,6 @@ static ulong generic_clk_get_rate(struct clk *clk) struct pmc_plat *plat = dev_get_plat(clk->dev); struct at91_pmc *pmc = plat->reg_base; struct clk parent; - ulong clk_rate; u32 tmp, gckdiv; u8 clock_source, parent_index; int ret; @@ -778,11 +772,7 @@ static ulong generic_clk_get_rate(struct clk *clk) if (ret) return 0; - clk_rate = clk_get_rate(&parent) / (gckdiv + 1); - - clk_free(&parent); - - return clk_rate; + return clk_get_rate(&parent) / (gckdiv + 1); } static ulong generic_clk_set_rate(struct clk *clk, ulong rate) diff --git a/drivers/clk/clk-gpio.c b/drivers/clk/clk-gpio.c index 26d795b9783..4ed14306575 100644 --- a/drivers/clk/clk-gpio.c +++ b/drivers/clk/clk-gpio.c @@ -3,19 +3,23 @@ * Copyright (C) 2023 Marek Vasut <marek.vasut+renesas@mailbox.org> */ -#include <asm/gpio.h> -#include <common.h> +#include <clk.h> #include <clk-uclass.h> #include <dm.h> +#include <linux/clk-provider.h> + +#include <asm/gpio.h> struct clk_gpio_priv { - struct gpio_desc enable; + struct gpio_desc enable; /* GPIO, controlling the gate */ + struct clk *clk; /* Gated clock */ }; static int clk_gpio_enable(struct clk *clk) { struct clk_gpio_priv *priv = dev_get_priv(clk->dev); + clk_enable(priv->clk); dm_gpio_set_value(&priv->enable, 1); return 0; @@ -26,21 +30,45 @@ static int clk_gpio_disable(struct clk *clk) struct clk_gpio_priv *priv = dev_get_priv(clk->dev); dm_gpio_set_value(&priv->enable, 0); + clk_disable(priv->clk); return 0; } +static ulong clk_gpio_get_rate(struct clk *clk) +{ + struct clk_gpio_priv *priv = dev_get_priv(clk->dev); + + return clk_get_rate(priv->clk); +} + const struct clk_ops clk_gpio_ops = { .enable = clk_gpio_enable, .disable = clk_gpio_disable, + .get_rate = clk_gpio_get_rate, }; static int clk_gpio_probe(struct udevice *dev) { struct clk_gpio_priv *priv = dev_get_priv(dev); + int ret; + + priv->clk = devm_clk_get(dev, NULL); + if (IS_ERR(priv->clk)) { + log_debug("%s: Could not get gated clock: %ld\n", + __func__, PTR_ERR(priv->clk)); + return PTR_ERR(priv->clk); + } - return gpio_request_by_name(dev, "enable-gpios", 0, - &priv->enable, GPIOD_IS_OUT); + ret = gpio_request_by_name(dev, "enable-gpios", 0, + &priv->enable, GPIOD_IS_OUT); + if (ret) { + log_debug("%s: Could not decode enable-gpios (%d)\n", + __func__, ret); + return ret; + } + + return 0; } /* diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index 3e9d68feb3c..ed6e60bc484 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -437,8 +437,6 @@ int clk_release_all(struct clk *clk, unsigned int count) ret = clk_disable(&clk[i]); if (ret && ret != -ENOSYS) return ret; - - clk_free(&clk[i]); } return 0; @@ -461,24 +459,9 @@ int clk_request(struct udevice *dev, struct clk *clk) return ops->request(clk); } -void clk_free(struct clk *clk) -{ - const struct clk_ops *ops; - - debug("%s(clk=%p)\n", __func__, clk); - if (!clk_valid(clk)) - return; - ops = clk_dev_ops(clk->dev); - - if (ops->rfree) - ops->rfree(clk); - return; -} - ulong clk_get_rate(struct clk *clk) { const struct clk_ops *ops; - ulong ret; debug("%s(clk=%p)\n", __func__, clk); if (!clk_valid(clk)) @@ -488,11 +471,7 @@ ulong clk_get_rate(struct clk *clk) if (!ops->get_rate) return -ENOSYS; - ret = ops->get_rate(clk); - if (ret) - return log_ret(ret); - - return 0; + return ops->get_rate(clk); } struct clk *clk_get_parent(struct clk *clk) @@ -791,22 +770,12 @@ bool clk_is_match(const struct clk *p, const struct clk *q) return false; } -static void devm_clk_release(struct udevice *dev, void *res) -{ - clk_free(res); -} - -static int devm_clk_match(struct udevice *dev, void *res, void *data) -{ - return res == data; -} - struct clk *devm_clk_get(struct udevice *dev, const char *id) { int rc; struct clk *clk; - clk = devres_alloc(devm_clk_release, sizeof(struct clk), __GFP_ZERO); + clk = devm_kzalloc(dev, sizeof(*clk), GFP_KERNEL); if (unlikely(!clk)) return ERR_PTR(-ENOMEM); @@ -814,21 +783,9 @@ struct clk *devm_clk_get(struct udevice *dev, const char *id) if (rc) return ERR_PTR(rc); - devres_add(dev, clk); return clk; } -void devm_clk_put(struct udevice *dev, struct clk *clk) -{ - int rc; - - if (!clk) - return; - - rc = devres_release(dev, devm_clk_release, devm_clk_match, clk); - WARN_ON(rc); -} - int clk_uclass_post_probe(struct udevice *dev) { /* diff --git a/drivers/clk/clk-xlnx-clock-wizard.c b/drivers/clk/clk-xlnx-clock-wizard.c index 70ee3af1074..a10a843f11f 100644 --- a/drivers/clk/clk-xlnx-clock-wizard.c +++ b/drivers/clk/clk-xlnx-clock-wizard.c @@ -137,7 +137,6 @@ static int clk_wzrd_probe(struct udevice *dev) ret = clk_enable(&clk_in1); if (ret) { dev_err(dev, "failed to enable clock\n"); - clk_free(&clk_in1); return ret; } diff --git a/drivers/clk/clk_sandbox.c b/drivers/clk/clk_sandbox.c index 636914db8ca..73d943f9e09 100644 --- a/drivers/clk/clk_sandbox.c +++ b/drivers/clk/clk_sandbox.c @@ -101,17 +101,6 @@ static int sandbox_clk_request(struct clk *clk) return 0; } -static void sandbox_clk_free(struct clk *clk) -{ - struct sandbox_clk_priv *priv = dev_get_priv(clk->dev); - - if (clk->id >= SANDBOX_CLK_ID_COUNT) - return; - - priv->requested[clk->id] = false; - return; -} - static struct clk_ops sandbox_clk_ops = { .round_rate = sandbox_clk_round_rate, .get_rate = sandbox_clk_get_rate, @@ -119,7 +108,6 @@ static struct clk_ops sandbox_clk_ops = { .enable = sandbox_clk_enable, .disable = sandbox_clk_disable, .request = sandbox_clk_request, - .rfree = sandbox_clk_free, }; static int sandbox_clk_probe(struct udevice *dev) diff --git a/drivers/clk/clk_sandbox_test.c b/drivers/clk/clk_sandbox_test.c index c695b69321e..c224dc1d2cb 100644 --- a/drivers/clk/clk_sandbox_test.c +++ b/drivers/clk/clk_sandbox_test.c @@ -135,18 +135,6 @@ int sandbox_clk_test_disable_bulk(struct udevice *dev) return clk_disable_bulk(&sbct->bulk); } -int sandbox_clk_test_free(struct udevice *dev) -{ - struct sandbox_clk_test *sbct = dev_get_priv(dev); - int i; - - devm_clk_put(dev, sbct->clkps[SANDBOX_CLK_TEST_ID_DEVM1]); - for (i = 0; i < SANDBOX_CLK_TEST_NON_DEVM_COUNT; i++) - clk_free(&sbct->clks[i]); - - return 0; -} - int sandbox_clk_test_release_bulk(struct udevice *dev) { struct sandbox_clk_test *sbct = dev_get_priv(dev); diff --git a/drivers/clk/clk_versaclock.c b/drivers/clk/clk_versaclock.c index 699df3cf3ee..bbe72256032 100644 --- a/drivers/clk/clk_versaclock.c +++ b/drivers/clk/clk_versaclock.c @@ -1000,26 +1000,18 @@ int versaclock_probe(struct udevice *dev) return 0; free_out: - for (n = 1; n < vc5->chip_info->clk_out_cnt; n++) { - clk_free(&vc5->clk_out[n].hw); + for (n = 1; n < vc5->chip_info->clk_out_cnt; n++) free(out_name[n]); - } free_selb: - clk_free(&vc5->clk_out[0].hw); free(outsel_name); free_fod: - for (n = 0; n < vc5->chip_info->clk_fod_cnt; n++) { - clk_free(&vc5->clk_fod[n].hw); + for (n = 0; n < vc5->chip_info->clk_fod_cnt; n++) free(fod_name[n]); - } free_pll: - clk_free(&vc5->clk_pll.hw); free(pll_name); free_pfd: - clk_free(&vc5->clk_pfd); free(pfd_name); free_mux: - clk_free(&vc5->clk_mux); free(mux_name); return ret; diff --git a/drivers/clk/clk_zynq.c b/drivers/clk/clk_zynq.c index 34f964d72af..e3cefe2e0c7 100644 --- a/drivers/clk/clk_zynq.c +++ b/drivers/clk/clk_zynq.c @@ -491,8 +491,6 @@ static void zynq_clk_dump(struct udevice *dev) rate = clk_get_rate(&clk); - clk_free(&clk); - if ((rate == (unsigned long)-ENOSYS) || (rate == (unsigned long)-ENXIO)) printf("%10s%20s\n", name, "unknown"); diff --git a/drivers/clk/clk_zynqmp.c b/drivers/clk/clk_zynqmp.c index 0ffac194a19..e23f7da3f92 100644 --- a/drivers/clk/clk_zynqmp.c +++ b/drivers/clk/clk_zynqmp.c @@ -757,8 +757,6 @@ static void zynqmp_clk_dump(struct udevice *dev) rate = clk_get_rate(&clk); - clk_free(&clk); - if ((rate == (unsigned long)-ENOSYS) || (rate == (unsigned long)-ENXIO) || (rate == (unsigned long)-EIO)) diff --git a/drivers/clk/imx/clk-imx8.c b/drivers/clk/imx/clk-imx8.c index 9600672e071..d39b87b2e24 100644 --- a/drivers/clk/imx/clk-imx8.c +++ b/drivers/clk/imx/clk-imx8.c @@ -62,8 +62,6 @@ static void imx8_clk_dump(struct udevice *dev) ret = clk_get_rate(&clk); rate = ret; - clk_free(&clk); - if (ret == -EINVAL) { printf("clk ID %lu not supported yet\n", imx8_clk_names[i].id); diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig index cdc9d6f76ce..ee33c611400 100644 --- a/drivers/clk/meson/Kconfig +++ b/drivers/clk/meson/Kconfig @@ -29,3 +29,13 @@ config CLK_MESON_A1 help Enable clock support for the Amlogic A1 SoC family, such as the A113L + +config CLK_MESON_MSR + bool "Enable clock measure driver for Amlogic SoCs" + depends on CLK && ARCH_MESON + depends on CMD_CLK + default ARCH_MESON + help + Enable measuring a set of internal Amlogic SoC clock frequencies + using the Hardware Clock Measure registers and print them using + the clk dump command. diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile index d975f07aab0..c7a446e86c4 100644 --- a/drivers/clk/meson/Makefile +++ b/drivers/clk/meson/Makefile @@ -9,3 +9,4 @@ obj-$(CONFIG_CLK_MESON_AXG) += axg-ao.o obj-$(CONFIG_CLK_MESON_G12A) += g12a.o obj-$(CONFIG_CLK_MESON_G12A) += g12a-ao.o obj-$(CONFIG_CLK_MESON_A1) += a1.o +obj-$(CONFIG_CLK_MESON_MSR) += clk-measure.o diff --git a/drivers/clk/meson/clk-measure.c b/drivers/clk/meson/clk-measure.c new file mode 100644 index 00000000000..f653fc63552 --- /dev/null +++ b/drivers/clk/meson/clk-measure.c @@ -0,0 +1,634 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Based on Linux driver from: + * (C) Copyright 2018 - BayLibre, SAS + * Author: Neil Armstrong <narmstrong@baylibre.com> + * (C) Copyright 2023 - Neil Armstrong <neil.armstrong@linaro.org> + */ + +#include <log.h> +#include <clk-uclass.h> +#include <div64.h> +#include <dm.h> +#include <time.h> +#include <regmap.h> +#include <syscon.h> +#include <linux/bitops.h> +#include <linux/bitfield.h> +#include <linux/delay.h> +#include <linux/err.h> +#include <linux/kernel.h> + +#define MSR_CLK_DUTY 0x0 +#define MSR_CLK_REG0 0x4 +#define MSR_CLK_REG1 0x8 +#define MSR_CLK_REG2 0xc + +#define MSR_DURATION GENMASK(15, 0) +#define MSR_ENABLE BIT(16) +#define MSR_CONT BIT(17) /* continuous measurement */ +#define MSR_INTR BIT(18) /* interrupts */ +#define MSR_RUN BIT(19) +#define MSR_CLK_SRC GENMASK(26, 20) +#define MSR_BUSY BIT(31) + +#define MSR_VAL_MASK GENMASK(15, 0) + +#define DIV_MIN 32 +#define DIV_STEP 32 +#define DIV_MAX 640 + +#define CLK_MSR_MAX 128 + +struct meson_msr_id { + unsigned int id; + const char *name; +}; + +struct meson_msr { + struct regmap *regmap; + struct meson_msr_id *msr_table; +}; + +#define CLK_MSR_ID(__id, __name) \ + [__id] = {.id = __id, .name = __name,} + +static struct meson_msr_id clk_msr_m8[CLK_MSR_MAX] = { + CLK_MSR_ID(0, "ring_osc_out_ee0"), + CLK_MSR_ID(1, "ring_osc_out_ee1"), + CLK_MSR_ID(2, "ring_osc_out_ee2"), + CLK_MSR_ID(3, "a9_ring_osck"), + CLK_MSR_ID(6, "vid_pll"), + CLK_MSR_ID(7, "clk81"), + CLK_MSR_ID(8, "encp"), + CLK_MSR_ID(9, "encl"), + CLK_MSR_ID(11, "eth_rmii"), + CLK_MSR_ID(13, "amclk"), + CLK_MSR_ID(14, "fec_clk_0"), + CLK_MSR_ID(15, "fec_clk_1"), + CLK_MSR_ID(16, "fec_clk_2"), + CLK_MSR_ID(18, "a9_clk_div16"), + CLK_MSR_ID(19, "hdmi_sys"), + CLK_MSR_ID(20, "rtc_osc_clk_out"), + CLK_MSR_ID(21, "i2s_clk_in_src0"), + CLK_MSR_ID(22, "clk_rmii_from_pad"), + CLK_MSR_ID(23, "hdmi_ch0_tmds"), + CLK_MSR_ID(24, "lvds_fifo"), + CLK_MSR_ID(26, "sc_clk_int"), + CLK_MSR_ID(28, "sar_adc"), + CLK_MSR_ID(30, "mpll_clk_test_out"), + CLK_MSR_ID(31, "audac_clkpi"), + CLK_MSR_ID(32, "vdac"), + CLK_MSR_ID(33, "sdhc_rx"), + CLK_MSR_ID(34, "sdhc_sd"), + CLK_MSR_ID(35, "mali"), + CLK_MSR_ID(36, "hdmi_tx_pixel"), + CLK_MSR_ID(38, "vdin_meas"), + CLK_MSR_ID(39, "pcm_sclk"), + CLK_MSR_ID(40, "pcm_mclk"), + CLK_MSR_ID(41, "eth_rx_tx"), + CLK_MSR_ID(42, "pwm_d"), + CLK_MSR_ID(43, "pwm_c"), + CLK_MSR_ID(44, "pwm_b"), + CLK_MSR_ID(45, "pwm_a"), + CLK_MSR_ID(46, "pcm2_sclk"), + CLK_MSR_ID(47, "ddr_dpll_pt"), + CLK_MSR_ID(48, "pwm_f"), + CLK_MSR_ID(49, "pwm_e"), + CLK_MSR_ID(59, "hcodec"), + CLK_MSR_ID(60, "usb_32k_alt"), + CLK_MSR_ID(61, "gpio"), + CLK_MSR_ID(62, "vid2_pll"), + CLK_MSR_ID(63, "mipi_csi_cfg"), +}; + +static struct meson_msr_id clk_msr_gx[CLK_MSR_MAX] = { + CLK_MSR_ID(0, "ring_osc_out_ee_0"), + CLK_MSR_ID(1, "ring_osc_out_ee_1"), + CLK_MSR_ID(2, "ring_osc_out_ee_2"), + CLK_MSR_ID(3, "a53_ring_osc"), + CLK_MSR_ID(4, "gp0_pll"), + CLK_MSR_ID(6, "enci"), + CLK_MSR_ID(7, "clk81"), + CLK_MSR_ID(8, "encp"), + CLK_MSR_ID(9, "encl"), + CLK_MSR_ID(10, "vdac"), + CLK_MSR_ID(11, "rgmii_tx"), + CLK_MSR_ID(12, "pdm"), + CLK_MSR_ID(13, "amclk"), + CLK_MSR_ID(14, "fec_0"), + CLK_MSR_ID(15, "fec_1"), + CLK_MSR_ID(16, "fec_2"), + CLK_MSR_ID(17, "sys_pll_div16"), + CLK_MSR_ID(18, "sys_cpu_div16"), + CLK_MSR_ID(19, "hdmitx_sys"), + CLK_MSR_ID(20, "rtc_osc_out"), + CLK_MSR_ID(21, "i2s_in_src0"), + CLK_MSR_ID(22, "eth_phy_ref"), + CLK_MSR_ID(23, "hdmi_todig"), + CLK_MSR_ID(26, "sc_int"), + CLK_MSR_ID(28, "sar_adc"), + CLK_MSR_ID(31, "mpll_test_out"), + CLK_MSR_ID(32, "vdec"), + CLK_MSR_ID(35, "mali"), + CLK_MSR_ID(36, "hdmi_tx_pixel"), + CLK_MSR_ID(37, "i958"), + CLK_MSR_ID(38, "vdin_meas"), + CLK_MSR_ID(39, "pcm_sclk"), + CLK_MSR_ID(40, "pcm_mclk"), + CLK_MSR_ID(41, "eth_rx_or_rmii"), + CLK_MSR_ID(42, "mp0_out"), + CLK_MSR_ID(43, "fclk_div5"), + CLK_MSR_ID(44, "pwm_b"), + CLK_MSR_ID(45, "pwm_a"), + CLK_MSR_ID(46, "vpu"), + CLK_MSR_ID(47, "ddr_dpll_pt"), + CLK_MSR_ID(48, "mp1_out"), + CLK_MSR_ID(49, "mp2_out"), + CLK_MSR_ID(50, "mp3_out"), + CLK_MSR_ID(51, "nand_core"), + CLK_MSR_ID(52, "sd_emmc_b"), + CLK_MSR_ID(53, "sd_emmc_a"), + CLK_MSR_ID(55, "vid_pll_div_out"), + CLK_MSR_ID(56, "cci"), + CLK_MSR_ID(57, "wave420l_c"), + CLK_MSR_ID(58, "wave420l_b"), + CLK_MSR_ID(59, "hcodec"), + CLK_MSR_ID(60, "alt_32k"), + CLK_MSR_ID(61, "gpio_msr"), + CLK_MSR_ID(62, "hevc"), + CLK_MSR_ID(66, "vid_lock"), + CLK_MSR_ID(70, "pwm_f"), + CLK_MSR_ID(71, "pwm_e"), + CLK_MSR_ID(72, "pwm_d"), + CLK_MSR_ID(73, "pwm_c"), + CLK_MSR_ID(75, "aoclkx2_int"), + CLK_MSR_ID(76, "aoclk_int"), + CLK_MSR_ID(77, "rng_ring_osc_0"), + CLK_MSR_ID(78, "rng_ring_osc_1"), + CLK_MSR_ID(79, "rng_ring_osc_2"), + CLK_MSR_ID(80, "rng_ring_osc_3"), + CLK_MSR_ID(81, "vapb"), + CLK_MSR_ID(82, "ge2d"), +}; + +static struct meson_msr_id clk_msr_axg[CLK_MSR_MAX] = { + CLK_MSR_ID(0, "ring_osc_out_ee_0"), + CLK_MSR_ID(1, "ring_osc_out_ee_1"), + CLK_MSR_ID(2, "ring_osc_out_ee_2"), + CLK_MSR_ID(3, "a53_ring_osc"), + CLK_MSR_ID(4, "gp0_pll"), + CLK_MSR_ID(5, "gp1_pll"), + CLK_MSR_ID(7, "clk81"), + CLK_MSR_ID(9, "encl"), + CLK_MSR_ID(17, "sys_pll_div16"), + CLK_MSR_ID(18, "sys_cpu_div16"), + CLK_MSR_ID(20, "rtc_osc_out"), + CLK_MSR_ID(23, "mmc_clk"), + CLK_MSR_ID(28, "sar_adc"), + CLK_MSR_ID(31, "mpll_test_out"), + CLK_MSR_ID(40, "mod_eth_tx_clk"), + CLK_MSR_ID(41, "mod_eth_rx_clk_rmii"), + CLK_MSR_ID(42, "mp0_out"), + CLK_MSR_ID(43, "fclk_div5"), + CLK_MSR_ID(44, "pwm_b"), + CLK_MSR_ID(45, "pwm_a"), + CLK_MSR_ID(46, "vpu"), + CLK_MSR_ID(47, "ddr_dpll_pt"), + CLK_MSR_ID(48, "mp1_out"), + CLK_MSR_ID(49, "mp2_out"), + CLK_MSR_ID(50, "mp3_out"), + CLK_MSR_ID(51, "sd_emmm_c"), + CLK_MSR_ID(52, "sd_emmc_b"), + CLK_MSR_ID(61, "gpio_msr"), + CLK_MSR_ID(66, "audio_slv_lrclk_c"), + CLK_MSR_ID(67, "audio_slv_lrclk_b"), + CLK_MSR_ID(68, "audio_slv_lrclk_a"), + CLK_MSR_ID(69, "audio_slv_sclk_c"), + CLK_MSR_ID(70, "audio_slv_sclk_b"), + CLK_MSR_ID(71, "audio_slv_sclk_a"), + CLK_MSR_ID(72, "pwm_d"), + CLK_MSR_ID(73, "pwm_c"), + CLK_MSR_ID(74, "wifi_beacon"), + CLK_MSR_ID(75, "tdmin_lb_lrcl"), + CLK_MSR_ID(76, "tdmin_lb_sclk"), + CLK_MSR_ID(77, "rng_ring_osc_0"), + CLK_MSR_ID(78, "rng_ring_osc_1"), + CLK_MSR_ID(79, "rng_ring_osc_2"), + CLK_MSR_ID(80, "rng_ring_osc_3"), + CLK_MSR_ID(81, "vapb"), + CLK_MSR_ID(82, "ge2d"), + CLK_MSR_ID(84, "audio_resample"), + CLK_MSR_ID(85, "audio_pdm_sys"), + CLK_MSR_ID(86, "audio_spdifout"), + CLK_MSR_ID(87, "audio_spdifin"), + CLK_MSR_ID(88, "audio_lrclk_f"), + CLK_MSR_ID(89, "audio_lrclk_e"), + CLK_MSR_ID(90, "audio_lrclk_d"), + CLK_MSR_ID(91, "audio_lrclk_c"), + CLK_MSR_ID(92, "audio_lrclk_b"), + CLK_MSR_ID(93, "audio_lrclk_a"), + CLK_MSR_ID(94, "audio_sclk_f"), + CLK_MSR_ID(95, "audio_sclk_e"), + CLK_MSR_ID(96, "audio_sclk_d"), + CLK_MSR_ID(97, "audio_sclk_c"), + CLK_MSR_ID(98, "audio_sclk_b"), + CLK_MSR_ID(99, "audio_sclk_a"), + CLK_MSR_ID(100, "audio_mclk_f"), + CLK_MSR_ID(101, "audio_mclk_e"), + CLK_MSR_ID(102, "audio_mclk_d"), + CLK_MSR_ID(103, "audio_mclk_c"), + CLK_MSR_ID(104, "audio_mclk_b"), + CLK_MSR_ID(105, "audio_mclk_a"), + CLK_MSR_ID(106, "pcie_refclk_n"), + CLK_MSR_ID(107, "pcie_refclk_p"), + CLK_MSR_ID(108, "audio_locker_out"), + CLK_MSR_ID(109, "audio_locker_in"), +}; + +static struct meson_msr_id clk_msr_g12a[CLK_MSR_MAX] = { + CLK_MSR_ID(0, "ring_osc_out_ee_0"), + CLK_MSR_ID(1, "ring_osc_out_ee_1"), + CLK_MSR_ID(2, "ring_osc_out_ee_2"), + CLK_MSR_ID(3, "sys_cpu_ring_osc"), + CLK_MSR_ID(4, "gp0_pll"), + CLK_MSR_ID(6, "enci"), + CLK_MSR_ID(7, "clk81"), + CLK_MSR_ID(8, "encp"), + CLK_MSR_ID(9, "encl"), + CLK_MSR_ID(10, "vdac"), + CLK_MSR_ID(11, "eth_tx"), + CLK_MSR_ID(12, "hifi_pll"), + CLK_MSR_ID(13, "mod_tcon"), + CLK_MSR_ID(14, "fec_0"), + CLK_MSR_ID(15, "fec_1"), + CLK_MSR_ID(16, "fec_2"), + CLK_MSR_ID(17, "sys_pll_div16"), + CLK_MSR_ID(18, "sys_cpu_div16"), + CLK_MSR_ID(19, "lcd_an_ph2"), + CLK_MSR_ID(20, "rtc_osc_out"), + CLK_MSR_ID(21, "lcd_an_ph3"), + CLK_MSR_ID(22, "eth_phy_ref"), + CLK_MSR_ID(23, "mpll_50m"), + CLK_MSR_ID(24, "eth_125m"), + CLK_MSR_ID(25, "eth_rmii"), + CLK_MSR_ID(26, "sc_int"), + CLK_MSR_ID(27, "in_mac"), + CLK_MSR_ID(28, "sar_adc"), + CLK_MSR_ID(29, "pcie_inp"), + CLK_MSR_ID(30, "pcie_inn"), + CLK_MSR_ID(31, "mpll_test_out"), + CLK_MSR_ID(32, "vdec"), + CLK_MSR_ID(33, "sys_cpu_ring_osc_1"), + CLK_MSR_ID(34, "eth_mpll_50m"), + CLK_MSR_ID(35, "mali"), + CLK_MSR_ID(36, "hdmi_tx_pixel"), + CLK_MSR_ID(37, "cdac"), + CLK_MSR_ID(38, "vdin_meas"), + CLK_MSR_ID(39, "bt656"), + CLK_MSR_ID(41, "eth_rx_or_rmii"), + CLK_MSR_ID(42, "mp0_out"), + CLK_MSR_ID(43, "fclk_div5"), + CLK_MSR_ID(44, "pwm_b"), + CLK_MSR_ID(45, "pwm_a"), + CLK_MSR_ID(46, "vpu"), + CLK_MSR_ID(47, "ddr_dpll_pt"), + CLK_MSR_ID(48, "mp1_out"), + CLK_MSR_ID(49, "mp2_out"), + CLK_MSR_ID(50, "mp3_out"), + CLK_MSR_ID(51, "sd_emmc_c"), + CLK_MSR_ID(52, "sd_emmc_b"), + CLK_MSR_ID(53, "sd_emmc_a"), + CLK_MSR_ID(54, "vpu_clkc"), + CLK_MSR_ID(55, "vid_pll_div_out"), + CLK_MSR_ID(56, "wave420l_a"), + CLK_MSR_ID(57, "wave420l_c"), + CLK_MSR_ID(58, "wave420l_b"), + CLK_MSR_ID(59, "hcodec"), + CLK_MSR_ID(61, "gpio_msr"), + CLK_MSR_ID(62, "hevcb"), + CLK_MSR_ID(63, "dsi_meas"), + CLK_MSR_ID(64, "spicc_1"), + CLK_MSR_ID(65, "spicc_0"), + CLK_MSR_ID(66, "vid_lock"), + CLK_MSR_ID(67, "dsi_phy"), + CLK_MSR_ID(68, "hdcp22_esm"), + CLK_MSR_ID(69, "hdcp22_skp"), + CLK_MSR_ID(70, "pwm_f"), + CLK_MSR_ID(71, "pwm_e"), + CLK_MSR_ID(72, "pwm_d"), + CLK_MSR_ID(73, "pwm_c"), + CLK_MSR_ID(75, "hevcf"), + CLK_MSR_ID(77, "rng_ring_osc_0"), + CLK_MSR_ID(78, "rng_ring_osc_1"), + CLK_MSR_ID(79, "rng_ring_osc_2"), + CLK_MSR_ID(80, "rng_ring_osc_3"), + CLK_MSR_ID(81, "vapb"), + CLK_MSR_ID(82, "ge2d"), + CLK_MSR_ID(83, "co_rx"), + CLK_MSR_ID(84, "co_tx"), + CLK_MSR_ID(89, "hdmi_todig"), + CLK_MSR_ID(90, "hdmitx_sys"), + CLK_MSR_ID(91, "sys_cpub_div16"), + CLK_MSR_ID(92, "sys_pll_cpub_div16"), + CLK_MSR_ID(94, "eth_phy_rx"), + CLK_MSR_ID(95, "eth_phy_pll"), + CLK_MSR_ID(96, "vpu_b"), + CLK_MSR_ID(97, "cpu_b_tmp"), + CLK_MSR_ID(98, "ts"), + CLK_MSR_ID(99, "ring_osc_out_ee_3"), + CLK_MSR_ID(100, "ring_osc_out_ee_4"), + CLK_MSR_ID(101, "ring_osc_out_ee_5"), + CLK_MSR_ID(102, "ring_osc_out_ee_6"), + CLK_MSR_ID(103, "ring_osc_out_ee_7"), + CLK_MSR_ID(104, "ring_osc_out_ee_8"), + CLK_MSR_ID(105, "ring_osc_out_ee_9"), + CLK_MSR_ID(106, "ephy_test"), + CLK_MSR_ID(107, "au_dac_g128x"), + CLK_MSR_ID(108, "audio_locker_out"), + CLK_MSR_ID(109, "audio_locker_in"), + CLK_MSR_ID(110, "audio_tdmout_c_sclk"), + CLK_MSR_ID(111, "audio_tdmout_b_sclk"), + CLK_MSR_ID(112, "audio_tdmout_a_sclk"), + CLK_MSR_ID(113, "audio_tdmin_lb_sclk"), + CLK_MSR_ID(114, "audio_tdmin_c_sclk"), + CLK_MSR_ID(115, "audio_tdmin_b_sclk"), + CLK_MSR_ID(116, "audio_tdmin_a_sclk"), + CLK_MSR_ID(117, "audio_resample"), + CLK_MSR_ID(118, "audio_pdm_sys"), + CLK_MSR_ID(119, "audio_spdifout_b"), + CLK_MSR_ID(120, "audio_spdifout"), + CLK_MSR_ID(121, "audio_spdifin"), + CLK_MSR_ID(122, "audio_pdm_dclk"), +}; + +static struct meson_msr_id clk_msr_sm1[CLK_MSR_MAX] = { + CLK_MSR_ID(0, "ring_osc_out_ee_0"), + CLK_MSR_ID(1, "ring_osc_out_ee_1"), + CLK_MSR_ID(2, "ring_osc_out_ee_2"), + CLK_MSR_ID(3, "ring_osc_out_ee_3"), + CLK_MSR_ID(4, "gp0_pll"), + CLK_MSR_ID(5, "gp1_pll"), + CLK_MSR_ID(6, "enci"), + CLK_MSR_ID(7, "clk81"), + CLK_MSR_ID(8, "encp"), + CLK_MSR_ID(9, "encl"), + CLK_MSR_ID(10, "vdac"), + CLK_MSR_ID(11, "eth_tx"), + CLK_MSR_ID(12, "hifi_pll"), + CLK_MSR_ID(13, "mod_tcon"), + CLK_MSR_ID(14, "fec_0"), + CLK_MSR_ID(15, "fec_1"), + CLK_MSR_ID(16, "fec_2"), + CLK_MSR_ID(17, "sys_pll_div16"), + CLK_MSR_ID(18, "sys_cpu_div16"), + CLK_MSR_ID(19, "lcd_an_ph2"), + CLK_MSR_ID(20, "rtc_osc_out"), + CLK_MSR_ID(21, "lcd_an_ph3"), + CLK_MSR_ID(22, "eth_phy_ref"), + CLK_MSR_ID(23, "mpll_50m"), + CLK_MSR_ID(24, "eth_125m"), + CLK_MSR_ID(25, "eth_rmii"), + CLK_MSR_ID(26, "sc_int"), + CLK_MSR_ID(27, "in_mac"), + CLK_MSR_ID(28, "sar_adc"), + CLK_MSR_ID(29, "pcie_inp"), + CLK_MSR_ID(30, "pcie_inn"), + CLK_MSR_ID(31, "mpll_test_out"), + CLK_MSR_ID(32, "vdec"), + CLK_MSR_ID(34, "eth_mpll_50m"), + CLK_MSR_ID(35, "mali"), + CLK_MSR_ID(36, "hdmi_tx_pixel"), + CLK_MSR_ID(37, "cdac"), + CLK_MSR_ID(38, "vdin_meas"), + CLK_MSR_ID(39, "bt656"), + CLK_MSR_ID(40, "arm_ring_osc_out_4"), + CLK_MSR_ID(41, "eth_rx_or_rmii"), + CLK_MSR_ID(42, "mp0_out"), + CLK_MSR_ID(43, "fclk_div5"), + CLK_MSR_ID(44, "pwm_b"), + CLK_MSR_ID(45, "pwm_a"), + CLK_MSR_ID(46, "vpu"), + CLK_MSR_ID(47, "ddr_dpll_pt"), + CLK_MSR_ID(48, "mp1_out"), + CLK_MSR_ID(49, "mp2_out"), + CLK_MSR_ID(50, "mp3_out"), + CLK_MSR_ID(51, "sd_emmc_c"), + CLK_MSR_ID(52, "sd_emmc_b"), + CLK_MSR_ID(53, "sd_emmc_a"), + CLK_MSR_ID(54, "vpu_clkc"), + CLK_MSR_ID(55, "vid_pll_div_out"), + CLK_MSR_ID(56, "wave420l_a"), + CLK_MSR_ID(57, "wave420l_c"), + CLK_MSR_ID(58, "wave420l_b"), + CLK_MSR_ID(59, "hcodec"), + CLK_MSR_ID(60, "arm_ring_osc_out_5"), + CLK_MSR_ID(61, "gpio_msr"), + CLK_MSR_ID(62, "hevcb"), + CLK_MSR_ID(63, "dsi_meas"), + CLK_MSR_ID(64, "spicc_1"), + CLK_MSR_ID(65, "spicc_0"), + CLK_MSR_ID(66, "vid_lock"), + CLK_MSR_ID(67, "dsi_phy"), + CLK_MSR_ID(68, "hdcp22_esm"), + CLK_MSR_ID(69, "hdcp22_skp"), + CLK_MSR_ID(70, "pwm_f"), + CLK_MSR_ID(71, "pwm_e"), + CLK_MSR_ID(72, "pwm_d"), + CLK_MSR_ID(73, "pwm_c"), + CLK_MSR_ID(74, "arm_ring_osc_out_6"), + CLK_MSR_ID(75, "hevcf"), + CLK_MSR_ID(76, "arm_ring_osc_out_7"), + CLK_MSR_ID(77, "rng_ring_osc_0"), + CLK_MSR_ID(78, "rng_ring_osc_1"), + CLK_MSR_ID(79, "rng_ring_osc_2"), + CLK_MSR_ID(80, "rng_ring_osc_3"), + CLK_MSR_ID(81, "vapb"), + CLK_MSR_ID(82, "ge2d"), + CLK_MSR_ID(83, "co_rx"), + CLK_MSR_ID(84, "co_tx"), + CLK_MSR_ID(85, "arm_ring_osc_out_8"), + CLK_MSR_ID(86, "arm_ring_osc_out_9"), + CLK_MSR_ID(87, "mipi_dsi_phy"), + CLK_MSR_ID(88, "cis2_adapt"), + CLK_MSR_ID(89, "hdmi_todig"), + CLK_MSR_ID(90, "hdmitx_sys"), + CLK_MSR_ID(91, "nna_core"), + CLK_MSR_ID(92, "nna_axi"), + CLK_MSR_ID(93, "vad"), + CLK_MSR_ID(94, "eth_phy_rx"), + CLK_MSR_ID(95, "eth_phy_pll"), + CLK_MSR_ID(96, "vpu_b"), + CLK_MSR_ID(97, "cpu_b_tmp"), + CLK_MSR_ID(98, "ts"), + CLK_MSR_ID(99, "arm_ring_osc_out_10"), + CLK_MSR_ID(100, "arm_ring_osc_out_11"), + CLK_MSR_ID(101, "arm_ring_osc_out_12"), + CLK_MSR_ID(102, "arm_ring_osc_out_13"), + CLK_MSR_ID(103, "arm_ring_osc_out_14"), + CLK_MSR_ID(104, "arm_ring_osc_out_15"), + CLK_MSR_ID(105, "arm_ring_osc_out_16"), + CLK_MSR_ID(106, "ephy_test"), + CLK_MSR_ID(107, "au_dac_g128x"), + CLK_MSR_ID(108, "audio_locker_out"), + CLK_MSR_ID(109, "audio_locker_in"), + CLK_MSR_ID(110, "audio_tdmout_c_sclk"), + CLK_MSR_ID(111, "audio_tdmout_b_sclk"), + CLK_MSR_ID(112, "audio_tdmout_a_sclk"), + CLK_MSR_ID(113, "audio_tdmin_lb_sclk"), + CLK_MSR_ID(114, "audio_tdmin_c_sclk"), + CLK_MSR_ID(115, "audio_tdmin_b_sclk"), + CLK_MSR_ID(116, "audio_tdmin_a_sclk"), + CLK_MSR_ID(117, "audio_resample"), + CLK_MSR_ID(118, "audio_pdm_sys"), + CLK_MSR_ID(119, "audio_spdifout_b"), + CLK_MSR_ID(120, "audio_spdifout"), + CLK_MSR_ID(121, "audio_spdifin"), + CLK_MSR_ID(122, "audio_pdm_dclk"), + CLK_MSR_ID(123, "audio_resampled"), + CLK_MSR_ID(124, "earcrx_pll"), + CLK_MSR_ID(125, "earcrx_pll_test"), + CLK_MSR_ID(126, "csi_phy0"), + CLK_MSR_ID(127, "csi2_data"), +}; + +static int meson_clk_msr_measure_id(struct meson_msr *priv, unsigned int id, + unsigned int duration) +{ + unsigned int val; + int ret; + + regmap_write(priv->regmap, MSR_CLK_REG0, 0); + + /* Set measurement duration */ + regmap_update_bits(priv->regmap, MSR_CLK_REG0, MSR_DURATION, + FIELD_PREP(MSR_DURATION, duration - 1)); + + /* Set ID */ + regmap_update_bits(priv->regmap, MSR_CLK_REG0, MSR_CLK_SRC, + FIELD_PREP(MSR_CLK_SRC, id)); + + /* Enable & Start */ + regmap_update_bits(priv->regmap, MSR_CLK_REG0, + MSR_RUN | MSR_ENABLE, + MSR_RUN | MSR_ENABLE); + + ret = regmap_read_poll_timeout(priv->regmap, MSR_CLK_REG0, + val, !(val & MSR_BUSY), 10, 10000); + if (ret) + return ret; + + /* Disable */ + regmap_update_bits(priv->regmap, MSR_CLK_REG0, MSR_ENABLE, 0); + + /* Get the value in multiple of gate time counts */ + regmap_read(priv->regmap, MSR_CLK_REG2, &val); + + if (val >= MSR_VAL_MASK) + return -EINVAL; + + return DIV_ROUND_CLOSEST_ULL((val & MSR_VAL_MASK) * 1000000ULL, + duration); +} + +static int meson_clk_msr_best_id(struct meson_msr *priv, unsigned int id, + unsigned int *precision) +{ + unsigned int duration = DIV_MAX; + int ret; + + /* Start from max duration and down to min duration */ + do { + ret = meson_clk_msr_measure_id(priv, id, duration); + if (ret >= 0) + *precision = (2 * 1000000) / duration; + else + duration -= DIV_STEP; + } while (duration >= DIV_MIN && ret == -EINVAL); + + return ret; +} + +static void meson_clk_msr_dump(struct udevice *dev) +{ + struct meson_msr *priv = dev_get_priv(dev); + unsigned int precision = 0; + int val, i; + + printf(" clock rate precision\n"); + printf("---------------------------------------------\n"); + + for (i = 0 ; i < CLK_MSR_MAX ; ++i) { + if (!priv->msr_table[i].name) + continue; + + val = meson_clk_msr_best_id(priv, i, &precision); + if (val < 0) + return; + + printf(" %-20s %10d +/-%dHz\n", + priv->msr_table[i].name, val, precision); + } +} + +static int meson_clk_msr_xlate(struct clk *clk, struct ofnode_phandle_args *args) +{ + /* This driver doesn't expose any clocks */ + return -EINVAL; +} + +static int meson_clk_msr_probe(struct udevice *dev) +{ + struct meson_msr *priv = dev_get_priv(dev); + int ret; + + priv->msr_table = (struct meson_msr_id *)dev_get_driver_data(dev); + + ret = regmap_init_mem(dev_ofnode(dev), &priv->regmap); + if (ret) + return ret; + + return 0; +} + +static struct clk_ops meson_clk_msr_ops = { + .of_xlate = meson_clk_msr_xlate, + .dump = meson_clk_msr_dump, +}; + +static const struct udevice_id meson_clk_msr_ids[] = { + { + .compatible = "amlogic,meson-gx-clk-measure", + .data = (ulong)clk_msr_gx, + }, + { + .compatible = "amlogic,meson8-clk-measure", + .data = (ulong)clk_msr_m8, + }, + { + .compatible = "amlogic,meson8b-clk-measure", + .data = (ulong)clk_msr_m8, + }, + { + .compatible = "amlogic,meson-axg-clk-measure", + .data = (ulong)clk_msr_axg, + }, + { + .compatible = "amlogic,meson-g12a-clk-measure", + .data = (ulong)clk_msr_g12a, + }, + { + .compatible = "amlogic,meson-sm1-clk-measure", + .data = (ulong)clk_msr_sm1, + }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(meson_clk_msr) = { + .name = "meson_clk_msr", + .id = UCLASS_CLK, + .of_match = meson_clk_msr_ids, + .priv_auto = sizeof(struct meson_msr), + .ops = &meson_clk_msr_ops, + .probe = meson_clk_msr_probe, +}; diff --git a/drivers/clk/mvebu/armada-37xx-periph.c b/drivers/clk/mvebu/armada-37xx-periph.c index 1a7097029ae..f5c9bd735c1 100644 --- a/drivers/clk/mvebu/armada-37xx-periph.c +++ b/drivers/clk/mvebu/armada-37xx-periph.c @@ -454,7 +454,6 @@ static int armada_37xx_periph_clk_set_parent(struct clk *clk, if (parent->dev != check_parent.dev) ret = -EINVAL; - clk_free(&check_parent); if (ret < 0) return ret; @@ -596,7 +595,6 @@ static int armada_37xx_periph_clk_probe(struct udevice *dev) } priv->parents[i] = clk_get_rate(&clk); - clk_free(&clk); } return 0; diff --git a/drivers/cpu/riscv_cpu.c b/drivers/cpu/riscv_cpu.c index 034b9b49c05..5d1026b37da 100644 --- a/drivers/cpu/riscv_cpu.c +++ b/drivers/cpu/riscv_cpu.c @@ -11,6 +11,7 @@ #include <errno.h> #include <log.h> #include <asm/global_data.h> +#include <asm/sbi.h> #include <dm/device-internal.h> #include <dm/lists.h> #include <linux/bitops.h> @@ -45,7 +46,6 @@ static int riscv_cpu_get_info(const struct udevice *dev, struct cpu_info *info) ret = clk_get_rate(&clk); if (!IS_ERR_VALUE(ret)) info->cpu_freq = ret; - clk_free(&clk); } if (!info->cpu_freq) @@ -95,13 +95,24 @@ static int riscv_cpu_bind(struct udevice *dev) struct cpu_plat *plat = dev_get_parent_plat(dev); struct driver *drv; int ret; + long mvendorid; /* save the hart id */ plat->cpu_id = dev_read_addr(dev); + /* provide data for SMBIOS */ if (IS_ENABLED(CONFIG_64BIT)) plat->family = 0x201; else plat->family = 0x200; + if (CONFIG_IS_ENABLED(RISCV_SMODE)) { + /* + * For RISC-V CPUs the SMBIOS Processor ID field contains + * the Machine Vendor ID from CSR mvendorid. + */ + ret = sbi_get_mvendorid(&mvendorid); + if (!ret) + plat->id[0] = mvendorid; + } /* first examine the property in current cpu node */ ret = dev_read_u32(dev, "timebase-frequency", &plat->timebase_freq); /* if not found, then look at the parent /cpus node */ @@ -145,7 +156,6 @@ static int riscv_cpu_probe(struct udevice *dev) return 0; ret = clk_enable(&clk); - clk_free(&clk); if (ret == -ENOSYS || ret == -ENOTSUPP) return 0; else diff --git a/drivers/dma/bcm6348-iudma.c b/drivers/dma/bcm6348-iudma.c index d4cfe0c1868..33c7b981415 100644 --- a/drivers/dma/bcm6348-iudma.c +++ b/drivers/dma/bcm6348-iudma.c @@ -596,8 +596,6 @@ static int bcm6348_iudma_probe(struct udevice *dev) pr_err("error enabling clock %d\n", i); return ret; } - - clk_free(&clk); } /* try to perform resets */ diff --git a/drivers/gpio/at91_gpio.c b/drivers/gpio/at91_gpio.c index 1409db5dc11..f80f4afd24f 100644 --- a/drivers/gpio/at91_gpio.c +++ b/drivers/gpio/at91_gpio.c @@ -603,8 +603,6 @@ static int at91_gpio_probe(struct udevice *dev) if (ret) return ret; - clk_free(&clk); - #if CONFIG_IS_ENABLED(OF_CONTROL) plat->base_addr = dev_read_addr(dev); #endif diff --git a/drivers/gpio/atmel_pio4.c b/drivers/gpio/atmel_pio4.c index 47ed2979814..be1dd752bf7 100644 --- a/drivers/gpio/atmel_pio4.c +++ b/drivers/gpio/atmel_pio4.c @@ -310,8 +310,6 @@ static int atmel_pio4_probe(struct udevice *dev) if (ret) return ret; - clk_free(&clk); - addr_base = dev_read_addr(dev); if (addr_base == FDT_ADDR_T_NONE) return -EINVAL; diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c index d6cfbd231a8..70778501232 100644 --- a/drivers/gpio/gpio-rcar.c +++ b/drivers/gpio/gpio-rcar.c @@ -165,7 +165,6 @@ static int rcar_gpio_probe(struct udevice *dev) } ret = clk_enable(&clk); - clk_free(&clk); if (ret) { dev_err(dev, "Failed to enable GPIO bank clock\n"); return ret; diff --git a/drivers/hwspinlock/stm32_hwspinlock.c b/drivers/hwspinlock/stm32_hwspinlock.c index 46ed64655a8..346b138e98f 100644 --- a/drivers/hwspinlock/stm32_hwspinlock.c +++ b/drivers/hwspinlock/stm32_hwspinlock.c @@ -69,11 +69,7 @@ static int stm32mp1_hwspinlock_probe(struct udevice *dev) if (ret) return ret; - ret = clk_enable(&clk); - if (ret) - clk_free(&clk); - - return ret; + return clk_enable(&clk); } static const struct hwspinlock_ops stm32mp1_hwspinlock_ops = { diff --git a/drivers/i2c/at91_i2c.c b/drivers/i2c/at91_i2c.c index e743d2a849a..b7a25885e66 100644 --- a/drivers/i2c/at91_i2c.c +++ b/drivers/i2c/at91_i2c.c @@ -201,8 +201,6 @@ static int at91_i2c_enable_clk(struct udevice *dev) bus->bus_clk_rate = clk_rate; - clk_free(&clk); - return 0; } diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c index 215ce010cb7..29cf63375c7 100644 --- a/drivers/i2c/designware_i2c.c +++ b/drivers/i2c/designware_i2c.c @@ -770,7 +770,6 @@ int designware_i2c_of_to_plat(struct udevice *bus) ret = clk_enable(&priv->clk); if (ret && ret != -ENOSYS && ret != -ENOTSUPP) { - clk_free(&priv->clk); dev_err(bus, "failed to enable clock\n"); return ret; } @@ -803,7 +802,6 @@ int designware_i2c_remove(struct udevice *dev) #if CONFIG_IS_ENABLED(CLK) clk_disable(&priv->clk); - clk_free(&priv->clk); #endif return reset_release_bulk(&priv->resets); diff --git a/drivers/i2c/i2c-microchip.c b/drivers/i2c/i2c-microchip.c index d82b80f5355..d453e243d6f 100644 --- a/drivers/i2c/i2c-microchip.c +++ b/drivers/i2c/i2c-microchip.c @@ -183,8 +183,6 @@ static int mpfs_i2c_init(struct mpfs_i2c_bus *bus, struct udevice *dev) if (!clk_rate) return -EINVAL; - clk_free(&bus->i2c_clk); - divisor = clk_rate / bus->clk_rate; ctrl = readl(bus->base + MPFS_I2C_CTRL); diff --git a/drivers/i2c/npcm_i2c.c b/drivers/i2c/npcm_i2c.c index b867b6c8e91..c64752e1467 100644 --- a/drivers/i2c/npcm_i2c.c +++ b/drivers/i2c/npcm_i2c.c @@ -570,7 +570,6 @@ static int npcm_i2c_probe(struct udevice *dev) printf("%s: fail to get rate\n", __func__); return -EINVAL; } - clk_free(&clk); bus->num = dev->seq_; bus->reg = dev_read_addr_ptr(dev); diff --git a/drivers/i2c/ocores_i2c.c b/drivers/i2c/ocores_i2c.c index 3b19ba78fa3..fff85118d0d 100644 --- a/drivers/i2c/ocores_i2c.c +++ b/drivers/i2c/ocores_i2c.c @@ -396,8 +396,6 @@ static int ocores_i2c_enable_clk(struct udevice *dev) bus->ip_clk_khz = clk_rate / 1000; - clk_free(&bus->clk); - return 0; } diff --git a/drivers/i2c/stm32f7_i2c.c b/drivers/i2c/stm32f7_i2c.c index eaa1d692898..f42e08a6418 100644 --- a/drivers/i2c/stm32f7_i2c.c +++ b/drivers/i2c/stm32f7_i2c.c @@ -890,7 +890,7 @@ static int stm32_i2c_probe(struct udevice *dev) ret = clk_enable(&i2c_priv->clk); if (ret) - goto clk_free; + return ret; ret = reset_get_by_index(dev, 0, &reset_ctl); if (ret) @@ -904,8 +904,6 @@ static int stm32_i2c_probe(struct udevice *dev) clk_disable: clk_disable(&i2c_priv->clk); -clk_free: - clk_free(&i2c_priv->clk); return ret; } diff --git a/drivers/mailbox/stm32-ipcc.c b/drivers/mailbox/stm32-ipcc.c index 69c86e059f5..046e1a8aca6 100644 --- a/drivers/mailbox/stm32-ipcc.c +++ b/drivers/mailbox/stm32-ipcc.c @@ -134,18 +134,13 @@ static int stm32_ipcc_probe(struct udevice *dev) ret = clk_enable(&clk); if (ret) - goto clk_free; + return ret; /* get channel number */ ipcc->n_chans = readl(ipcc->reg_base + IPCC_HWCFGR); ipcc->n_chans &= IPCFGR_CHAN_MASK; return 0; - -clk_free: - clk_free(&clk); - - return ret; } static const struct udevice_id stm32_ipcc_ids[] = { diff --git a/drivers/misc/ls2_sfp.c b/drivers/misc/ls2_sfp.c index 2a81bc7de5f..5351c7ed34f 100644 --- a/drivers/misc/ls2_sfp.c +++ b/drivers/misc/ls2_sfp.c @@ -249,7 +249,6 @@ static int ls2_sfp_probe(struct udevice *dev) } rate = clk_get_rate(&clk); - clk_free(&clk); if (!rate || IS_ERR_VALUE(rate)) { ret = rate ? rate : -ENOENT; dev_dbg(dev, "could not get clock rate (err %d)\n", diff --git a/drivers/misc/qfw_smbios.c b/drivers/misc/qfw_smbios.c index a898cb4eea4..c3e8c310d00 100644 --- a/drivers/misc/qfw_smbios.c +++ b/drivers/misc/qfw_smbios.c @@ -90,7 +90,7 @@ static int qfw_parse_smbios_anchor(struct udevice *dev, entry->length = sizeof(struct smbios3_entry); entry->major_ver = entry2->major_ver; entry->minor_ver = entry2->minor_ver; - entry->max_struct_size = entry2->struct_table_length; + entry->table_maximum_size = entry2->struct_table_length; } else { ret = -ENOENT; goto out; diff --git a/drivers/mmc/arm_pl180_mmci.c b/drivers/mmc/arm_pl180_mmci.c index 9c5d48e90cd..5cf5502ed54 100644 --- a/drivers/mmc/arm_pl180_mmci.c +++ b/drivers/mmc/arm_pl180_mmci.c @@ -447,7 +447,6 @@ static int arm_pl180_mmc_probe(struct udevice *dev) ret = clk_enable(&clk); if (ret) { - clk_free(&clk); dev_err(dev, "failed to enable clock\n"); return ret; } diff --git a/drivers/mmc/aspeed_sdhci.c b/drivers/mmc/aspeed_sdhci.c index 9d79bf58cc7..c9626c6beb8 100644 --- a/drivers/mmc/aspeed_sdhci.c +++ b/drivers/mmc/aspeed_sdhci.c @@ -35,7 +35,7 @@ static int aspeed_sdhci_probe(struct udevice *dev) ret = clk_enable(&clk); if (ret) { debug("%s: clock enable failed %d\n", __func__, ret); - goto free; + return ret; } host->name = dev->name; @@ -66,8 +66,6 @@ static int aspeed_sdhci_probe(struct udevice *dev) err: clk_disable(&clk); -free: - clk_free(&clk); return ret; } diff --git a/drivers/mmc/atmel_sdhci.c b/drivers/mmc/atmel_sdhci.c index 5347ba90431..d92bad97b71 100644 --- a/drivers/mmc/atmel_sdhci.c +++ b/drivers/mmc/atmel_sdhci.c @@ -147,8 +147,6 @@ static int atmel_sdhci_probe(struct udevice *dev) host->ops = &atmel_sdhci_ops; upriv->mmc = host->mmc; - clk_free(&clk); - ret = sdhci_probe(dev); if (ret) return ret; diff --git a/drivers/mmc/gen_atmel_mci.c b/drivers/mmc/gen_atmel_mci.c index d91819acfd7..3ee99558f6f 100644 --- a/drivers/mmc/gen_atmel_mci.c +++ b/drivers/mmc/gen_atmel_mci.c @@ -559,27 +559,20 @@ static int atmel_mci_enable_clk(struct udevice *dev) int ret = 0; ret = clk_get_by_index(dev, 0, &clk); - if (ret) { - ret = -EINVAL; - goto failed; - } + if (ret) + return -EINVAL; ret = clk_enable(&clk); if (ret) - goto failed; + return ret; clk_rate = clk_get_rate(&clk); - if (!clk_rate) { - ret = -EINVAL; - goto failed; - } + if (!clk_rate) + return -EINVAL; priv->bus_clk_rate = clk_rate; -failed: - clk_free(&clk); - - return ret; + return 0; } static int atmel_mci_probe(struct udevice *dev) diff --git a/drivers/mmc/msm_sdhci.c b/drivers/mmc/msm_sdhci.c index 604f9c3ff99..fe1e754bfde 100644 --- a/drivers/mmc/msm_sdhci.c +++ b/drivers/mmc/msm_sdhci.c @@ -81,7 +81,6 @@ static int msm_sdc_clk_init(struct udevice *dev) return ret; ret = clk_set_rate(&clk, clk_rate); - clk_free(&clk); if (ret < 0) return ret; diff --git a/drivers/mmc/pic32_sdhci.c b/drivers/mmc/pic32_sdhci.c index fe555106a1d..7a8e33dbc7a 100644 --- a/drivers/mmc/pic32_sdhci.c +++ b/drivers/mmc/pic32_sdhci.c @@ -32,7 +32,6 @@ static int pic32_sdhci_probe(struct udevice *dev) return ret; clk_rate = clk_get_rate(&clk); - clk_free(&clk); if (IS_ERR_VALUE(clk_rate)) return clk_rate; diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c index 97aaf1e4ec3..a74559ca686 100644 --- a/drivers/mmc/renesas-sdhi.c +++ b/drivers/mmc/renesas-sdhi.c @@ -979,19 +979,19 @@ static int rzg2l_sdhi_setup(struct udevice *dev) ret = clk_get_by_name(dev, "cd", &imclk2); if (ret < 0) { dev_err(dev, "failed to get imclk2 (chip detect clk)\n"); - goto err_get_imclk2; + return ret; } ret = clk_get_by_name(dev, "aclk", &aclk); if (ret < 0) { dev_err(dev, "failed to get aclk\n"); - goto err_get_aclk; + return ret; } ret = clk_enable(&imclk2); if (ret < 0) { dev_err(dev, "failed to enable imclk2 (chip detect clk)\n"); - goto err_imclk2; + return ret; } ret = clk_enable(&aclk); @@ -1026,11 +1026,6 @@ err_get_reset: clk_disable(&aclk); err_aclk: clk_disable(&imclk2); -err_imclk2: - clk_free(&aclk); -err_get_aclk: - clk_free(&imclk2); -err_get_imclk2: return ret; } @@ -1071,7 +1066,7 @@ static int renesas_sdhi_probe(struct udevice *dev) ret = clk_set_rate(&priv->clkh, 800000000); if (ret < 0) { dev_err(dev, "failed to set rate for SDnH clock (%d)\n", ret); - goto err_clk; + return ret; } } @@ -1079,13 +1074,13 @@ static int renesas_sdhi_probe(struct udevice *dev) ret = clk_set_rate(&priv->clk, 200000000); if (ret < 0) { dev_err(dev, "failed to set rate for SDn clock (%d)\n", ret); - goto err_clkh; + return ret; } ret = clk_enable(&priv->clk); if (ret) { dev_err(dev, "failed to enable SDn clock (%d)\n", ret); - goto err_clkh; + return ret; } if (device_is_compatible(dev, "renesas,sdhi-r9a07g044")) @@ -1107,10 +1102,6 @@ static int renesas_sdhi_probe(struct udevice *dev) err_tmio_probe: clk_disable(&priv->clk); -err_clkh: - clk_free(&priv->clkh); -err_clk: - clk_free(&priv->clk); return ret; } diff --git a/drivers/mmc/snps_dw_mmc.c b/drivers/mmc/snps_dw_mmc.c index 50a8805e736..0134399e393 100644 --- a/drivers/mmc/snps_dw_mmc.c +++ b/drivers/mmc/snps_dw_mmc.c @@ -46,7 +46,7 @@ static int snps_dwmmc_clk_setup(struct udevice *dev) ret = clk_enable(&clk_ciu); if (ret && ret != -ENOSYS && ret != -ENOTSUPP) - goto clk_err_ciu; + goto clk_err; host->bus_hz = clk_get_rate(&clk_ciu); if (host->bus_hz < CLOCK_MIN) { @@ -60,16 +60,12 @@ static int snps_dwmmc_clk_setup(struct udevice *dev) ret = clk_enable(&clk_biu); if (ret && ret != -ENOSYS && ret != -ENOTSUPP) - goto clk_err_biu; + goto clk_err_ciu_dis; return 0; -clk_err_biu: - clk_free(&clk_biu); clk_err_ciu_dis: clk_disable(&clk_ciu); -clk_err_ciu: - clk_free(&clk_ciu); clk_err: dev_err(dev, "failed to setup clocks, ret %d\n", ret); diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c index be3d8bfb3d7..387cb8b6b50 100644 --- a/drivers/mmc/socfpga_dw_mmc.c +++ b/drivers/mmc/socfpga_dw_mmc.c @@ -99,7 +99,6 @@ static int socfpga_dwmmc_get_clk_rate(struct udevice *dev) host->bus_hz = clk_get_rate(&clk); - clk_free(&clk); #else /* Fixed clock divide by 4 which due to the SDMMC wrapper */ host->bus_hz = cm_get_mmc_controller_clk_hz(); diff --git a/drivers/mmc/stm32_sdmmc2.c b/drivers/mmc/stm32_sdmmc2.c index 5ff5e1a4d8b..a2b111a8435 100644 --- a/drivers/mmc/stm32_sdmmc2.c +++ b/drivers/mmc/stm32_sdmmc2.c @@ -766,10 +766,8 @@ static int stm32_sdmmc2_probe(struct udevice *dev) int ret; ret = clk_enable(&plat->clk); - if (ret) { - clk_free(&plat->clk); + if (ret) return ret; - } upriv->mmc = &plat->mmc; diff --git a/drivers/mmc/uniphier-sd.c b/drivers/mmc/uniphier-sd.c index 75003a0113e..8cde4308aae 100644 --- a/drivers/mmc/uniphier-sd.c +++ b/drivers/mmc/uniphier-sd.c @@ -64,7 +64,6 @@ static int uniphier_sd_probe(struct udevice *dev) ret = clk_set_rate(&priv->clk, ULONG_MAX); if (ret < 0) { dev_err(dev, "failed to set rate for host clock\n"); - clk_free(&priv->clk); return ret; } diff --git a/drivers/mtd/nand/raw/atmel/nand-controller.c b/drivers/mtd/nand/raw/atmel/nand-controller.c index a2151f98491..0e0441472b8 100644 --- a/drivers/mtd/nand/raw/atmel/nand-controller.c +++ b/drivers/mtd/nand/raw/atmel/nand-controller.c @@ -1999,10 +1999,8 @@ atmel_hsmc_nand_controller_remove(struct atmel_nand_controller *nc) hsmc_nc = container_of(nc, struct atmel_hsmc_nand_controller, base); - if (hsmc_nc->clk) { + if (hsmc_nc->clk) clk_disable_unprepare(hsmc_nc->clk); - devm_clk_put(nc->dev, hsmc_nc->clk); - } return 0; } diff --git a/drivers/mtd/nand/raw/atmel/pmecc.c b/drivers/mtd/nand/raw/atmel/pmecc.c index e2e3f1ee6b5..51f6bd2e65b 100644 --- a/drivers/mtd/nand/raw/atmel/pmecc.c +++ b/drivers/mtd/nand/raw/atmel/pmecc.c @@ -816,9 +816,6 @@ int atmel_pmecc_wait_rdy(struct atmel_pmecc_user *user) } EXPORT_SYMBOL_GPL(atmel_pmecc_wait_rdy); -#define ATMEL_BASE_PMECC 0xffffe000 -#define ATMEL_BASE_PMERRLOC 0xffffe600 - static struct atmel_pmecc * atmel_pmecc_create(struct udevice *dev, const struct atmel_pmecc_caps *caps, diff --git a/drivers/mtd/renesas_rpc_hf.c b/drivers/mtd/renesas_rpc_hf.c index aca7a6cdd25..979b64d4a2f 100644 --- a/drivers/mtd/renesas_rpc_hf.c +++ b/drivers/mtd/renesas_rpc_hf.c @@ -370,7 +370,6 @@ static int rpc_hf_probe(struct udevice *dev) } ret = clk_enable(&clk); - clk_free(&clk); if (ret) { dev_err(dev, "Failed to enable RPC clock\n"); return ret; diff --git a/drivers/net/bcm6348-eth.c b/drivers/net/bcm6348-eth.c index 72dcd07d30d..15a94f6ce9a 100644 --- a/drivers/net/bcm6348-eth.c +++ b/drivers/net/bcm6348-eth.c @@ -457,8 +457,6 @@ static int bcm6348_eth_probe(struct udevice *dev) pr_err("%s: error enabling clock %d\n", __func__, i); return ret; } - - clk_free(&clk); } /* try to perform resets */ diff --git a/drivers/net/bcm6368-eth.c b/drivers/net/bcm6368-eth.c index fdd938ce0dd..9679a45b075 100644 --- a/drivers/net/bcm6368-eth.c +++ b/drivers/net/bcm6368-eth.c @@ -546,8 +546,6 @@ static int bcm6368_eth_probe(struct udevice *dev) pr_err("%s: error enabling clock %d\n", __func__, i); return ret; } - - clk_free(&clk); } /* try to perform resets */ diff --git a/drivers/net/designware.c b/drivers/net/designware.c index a174344b3ef..c8696358d6f 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -702,7 +702,6 @@ int designware_eth_probe(struct udevice *dev) err = clk_enable(&priv->clocks[i]); if (err && err != -ENOSYS && err != -ENOTSUPP) { pr_err("failed to enable clock %d\n", i); - clk_free(&priv->clocks[i]); goto clk_err; } priv->clock_count++; diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index e40e399c802..9b3bce1dc87 100644 --- a/drivers/net/dwc_eth_qos.c +++ b/drivers/net/dwc_eth_qos.c @@ -1382,38 +1382,30 @@ static int eqos_probe_resources_tegra186(struct udevice *dev) ret = clk_get_by_name(dev, "master_bus", &eqos->clk_master_bus); if (ret) { pr_err("clk_get_by_name(master_bus) failed: %d", ret); - goto err_free_clk_slave_bus; + goto err_free_gpio_phy_reset; } ret = clk_get_by_name(dev, "rx", &eqos->clk_rx); if (ret) { pr_err("clk_get_by_name(rx) failed: %d", ret); - goto err_free_clk_master_bus; + goto err_free_gpio_phy_reset; } ret = clk_get_by_name(dev, "ptp_ref", &eqos->clk_ptp_ref); if (ret) { pr_err("clk_get_by_name(ptp_ref) failed: %d", ret); - goto err_free_clk_rx; + goto err_free_gpio_phy_reset; } ret = clk_get_by_name(dev, "tx", &eqos->clk_tx); if (ret) { pr_err("clk_get_by_name(tx) failed: %d", ret); - goto err_free_clk_ptp_ref; + goto err_free_gpio_phy_reset; } debug("%s: OK\n", __func__); return 0; -err_free_clk_ptp_ref: - clk_free(&eqos->clk_ptp_ref); -err_free_clk_rx: - clk_free(&eqos->clk_rx); -err_free_clk_master_bus: - clk_free(&eqos->clk_master_bus); -err_free_clk_slave_bus: - clk_free(&eqos->clk_slave_bus); err_free_gpio_phy_reset: dm_gpio_free(dev, &eqos->phy_reset_gpio); err_free_reset_eqos: @@ -1451,13 +1443,13 @@ static int eqos_probe_resources_stm32(struct udevice *dev) ret = clk_get_by_name(dev, "mac-clk-rx", &eqos->clk_rx); if (ret) { pr_err("clk_get_by_name(rx) failed: %d", ret); - goto err_free_clk_master_bus; + goto err_probe; } ret = clk_get_by_name(dev, "mac-clk-tx", &eqos->clk_tx); if (ret) { pr_err("clk_get_by_name(tx) failed: %d", ret); - goto err_free_clk_rx; + goto err_probe; } /* Get ETH_CLK clocks (optional) */ @@ -1468,10 +1460,6 @@ static int eqos_probe_resources_stm32(struct udevice *dev) debug("%s: OK\n", __func__); return 0; -err_free_clk_rx: - clk_free(&eqos->clk_rx); -err_free_clk_master_bus: - clk_free(&eqos->clk_master_bus); err_probe: debug("%s: returns %d\n", __func__, ret); @@ -1489,13 +1477,6 @@ static int eqos_remove_resources_tegra186(struct udevice *dev) debug("%s(dev=%p):\n", __func__, dev); -#ifdef CONFIG_CLK - clk_free(&eqos->clk_tx); - clk_free(&eqos->clk_ptp_ref); - clk_free(&eqos->clk_rx); - clk_free(&eqos->clk_slave_bus); - clk_free(&eqos->clk_master_bus); -#endif dm_gpio_free(dev, &eqos->phy_reset_gpio); reset_free(&eqos->reset_ctl); @@ -1505,19 +1486,7 @@ static int eqos_remove_resources_tegra186(struct udevice *dev) static int eqos_remove_resources_stm32(struct udevice *dev) { - struct eqos_priv * __maybe_unused eqos = dev_get_priv(dev); - debug("%s(dev=%p):\n", __func__, dev); - -#ifdef CONFIG_CLK - clk_free(&eqos->clk_tx); - clk_free(&eqos->clk_rx); - clk_free(&eqos->clk_master_bus); - if (clk_valid(&eqos->clk_ck)) - clk_free(&eqos->clk_ck); -#endif - - debug("%s: OK\n", __func__); return 0; } diff --git a/drivers/net/dwc_eth_qos_imx.c b/drivers/net/dwc_eth_qos_imx.c index e3f55dd9817..9c4e3904413 100644 --- a/drivers/net/dwc_eth_qos_imx.c +++ b/drivers/net/dwc_eth_qos_imx.c @@ -70,30 +70,24 @@ static int eqos_probe_resources_imx(struct udevice *dev) ret = clk_get_by_name(dev, "ptp_ref", &eqos->clk_ptp_ref); if (ret) { dev_dbg(dev, "clk_get_by_name(ptp_ref) failed: %d", ret); - goto err_free_clk_master_bus; + goto err_probe; } ret = clk_get_by_name(dev, "tx", &eqos->clk_tx); if (ret) { dev_dbg(dev, "clk_get_by_name(tx) failed: %d", ret); - goto err_free_clk_ptp_ref; + goto err_probe; } ret = clk_get_by_name(dev, "pclk", &eqos->clk_ck); if (ret) { dev_dbg(dev, "clk_get_by_name(pclk) failed: %d", ret); - goto err_free_clk_tx; + goto err_probe; } debug("%s: OK\n", __func__); return 0; -err_free_clk_tx: - clk_free(&eqos->clk_tx); -err_free_clk_ptp_ref: - clk_free(&eqos->clk_ptp_ref); -err_free_clk_master_bus: - clk_free(&eqos->clk_master_bus); err_probe: debug("%s: returns %d\n", __func__, ret); @@ -102,16 +96,7 @@ err_probe: static int eqos_remove_resources_imx(struct udevice *dev) { - struct eqos_priv *eqos = dev_get_priv(dev); - debug("%s(dev=%p):\n", __func__, dev); - - clk_free(&eqos->clk_ck); - clk_free(&eqos->clk_tx); - clk_free(&eqos->clk_ptp_ref); - clk_free(&eqos->clk_master_bus); - - debug("%s: OK\n", __func__); return 0; } diff --git a/drivers/net/dwc_eth_qos_qcom.c b/drivers/net/dwc_eth_qos_qcom.c index df83f1c5f9e..8178138fc65 100644 --- a/drivers/net/dwc_eth_qos_qcom.c +++ b/drivers/net/dwc_eth_qos_qcom.c @@ -575,7 +575,6 @@ static int eqos_remove_resources_qcom(struct udevice *dev) debug("%s(dev=%p):\n", __func__, dev); - clk_free(&eqos->clk_tx); dm_gpio_free(dev, &eqos->phy_reset_gpio); reset_free(&eqos->reset_ctl); diff --git a/drivers/net/dwc_eth_qos_rockchip.c b/drivers/net/dwc_eth_qos_rockchip.c index 834307a4477..fa9e513faea 100644 --- a/drivers/net/dwc_eth_qos_rockchip.c +++ b/drivers/net/dwc_eth_qos_rockchip.c @@ -372,7 +372,7 @@ static int eqos_probe_resources_rk(struct udevice *dev) ret = clk_get_by_name(dev, "clk_mac_speed", &eqos->clk_tx); if (ret) { dev_dbg(dev, "clk_get_by_name(clk_mac_speed) failed: %d", ret); - goto err_free_clk_master_bus; + goto err_release_resets; } } @@ -393,8 +393,6 @@ static int eqos_probe_resources_rk(struct udevice *dev) return 0; -err_free_clk_master_bus: - clk_free(&eqos->clk_master_bus); err_release_resets: reset_release_bulk(&data->resets); err_free: @@ -412,8 +410,6 @@ static int eqos_remove_resources_rk(struct udevice *dev) if (dm_gpio_is_valid(&eqos->phy_reset_gpio)) dm_gpio_free(dev, &eqos->phy_reset_gpio); - clk_free(&eqos->clk_tx); - clk_free(&eqos->clk_master_bus); reset_release_bulk(&data->resets); free(data); diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c index 8635a960d6e..a2c763c8791 100644 --- a/drivers/net/phy/motorcomm.c +++ b/drivers/net/phy/motorcomm.c @@ -23,6 +23,12 @@ #define YTPHY_SYNCE_CFG_REG 0xA012 +#define YT8531_PAD_DRIVE_STRENGTH_CFG_REG 0xA010 +#define YT8531_RGMII_RXC_DS_MASK GENMASK(15, 13) +#define YT8531_RGMII_RXD_DS_HI_MASK BIT(12) /* Bit 2 of rxd_ds */ +#define YT8531_RGMII_RXD_DS_LOW_MASK GENMASK(5, 4) /* Bit 1/0 of rxd_ds */ +#define YT8531_RGMII_RX_DS_DEFAULT 0x3 + #define YTPHY_DTS_OUTPUT_CLK_DIS 0 #define YTPHY_DTS_OUTPUT_CLK_25M 25000000 #define YTPHY_DTS_OUTPUT_CLK_125M 125000000 @@ -114,6 +120,10 @@ #define YT8531_CCR_RXC_DLY_EN BIT(8) #define YT8531_CCR_RXC_DLY_1_900_NS 1900 +#define YT8531_CCR_CFG_LDO_MASK GENMASK(5, 4) +#define YT8531_CCR_CFG_LDO_3V3 0x0 +#define YT8531_CCR_CFG_LDO_1V8 0x2 + /* bits in struct ytphy_plat_priv->flag */ #define TX_CLK_ADJ_ENABLED BIT(0) #define AUTO_SLEEP_DISABLED BIT(1) @@ -224,6 +234,17 @@ static int ytphy_modify_ext(struct phy_device *phydev, u16 regnum, u16 mask, return phy_modify(phydev, MDIO_DEVAD_NONE, YTPHY_PAGE_DATA, mask, set); } +static int ytphy_read_ext(struct phy_device *phydev, u16 regnum) +{ + int ret; + + ret = phy_write(phydev, MDIO_DEVAD_NONE, YTPHY_PAGE_SELECT, regnum); + if (ret < 0) + return ret; + + return phy_read(phydev, MDIO_DEVAD_NONE, YTPHY_PAGE_DATA); +} + static int ytphy_rgmii_clk_delay_config(struct phy_device *phydev) { struct ytphy_plat_priv *priv = phydev->priv; @@ -425,6 +446,111 @@ static int yt8511_config(struct phy_device *phydev) return 0; } +/** + * struct ytphy_ldo_vol_map - map a current value to a register value + * @vol: ldo voltage + * @ds: value in the register + * @cur: value in device configuration + */ +struct ytphy_ldo_vol_map { + u32 vol; + u32 ds; + u32 cur; +}; + +static const struct ytphy_ldo_vol_map yt8531_ldo_vol[] = { + {.vol = YT8531_CCR_CFG_LDO_1V8, .ds = 0, .cur = 1200}, + {.vol = YT8531_CCR_CFG_LDO_1V8, .ds = 1, .cur = 2100}, + {.vol = YT8531_CCR_CFG_LDO_1V8, .ds = 2, .cur = 2700}, + {.vol = YT8531_CCR_CFG_LDO_1V8, .ds = 3, .cur = 2910}, + {.vol = YT8531_CCR_CFG_LDO_1V8, .ds = 4, .cur = 3110}, + {.vol = YT8531_CCR_CFG_LDO_1V8, .ds = 5, .cur = 3600}, + {.vol = YT8531_CCR_CFG_LDO_1V8, .ds = 6, .cur = 3970}, + {.vol = YT8531_CCR_CFG_LDO_1V8, .ds = 7, .cur = 4350}, + {.vol = YT8531_CCR_CFG_LDO_3V3, .ds = 0, .cur = 3070}, + {.vol = YT8531_CCR_CFG_LDO_3V3, .ds = 1, .cur = 4080}, + {.vol = YT8531_CCR_CFG_LDO_3V3, .ds = 2, .cur = 4370}, + {.vol = YT8531_CCR_CFG_LDO_3V3, .ds = 3, .cur = 4680}, + {.vol = YT8531_CCR_CFG_LDO_3V3, .ds = 4, .cur = 5020}, + {.vol = YT8531_CCR_CFG_LDO_3V3, .ds = 5, .cur = 5450}, + {.vol = YT8531_CCR_CFG_LDO_3V3, .ds = 6, .cur = 5740}, + {.vol = YT8531_CCR_CFG_LDO_3V3, .ds = 7, .cur = 6140}, +}; + +static u32 yt8531_get_ldo_vol(struct phy_device *phydev) +{ + u32 val; + + val = ytphy_read_ext(phydev, YT8531_CHIP_CONFIG_REG); + val = FIELD_GET(YT8531_CCR_CFG_LDO_MASK, val); + + return val <= YT8531_CCR_CFG_LDO_1V8 ? val : YT8531_CCR_CFG_LDO_1V8; +} + +static int yt8531_get_ds_map(struct phy_device *phydev, u32 cur) +{ + u32 vol; + int i; + + vol = yt8531_get_ldo_vol(phydev); + for (i = 0; i < ARRAY_SIZE(yt8531_ldo_vol); i++) { + if (yt8531_ldo_vol[i].vol == vol && yt8531_ldo_vol[i].cur == cur) + return yt8531_ldo_vol[i].ds; + } + + return -EINVAL; +} + +static int yt8531_set_ds(struct phy_device *phydev) +{ + u32 ds_field_low, ds_field_hi, val; + int ret, ds; + + /* set rgmii rx clk driver strength */ + if (!ofnode_read_u32(phydev->node, "motorcomm,rx-clk-drv-microamp", &val)) { + ds = yt8531_get_ds_map(phydev, val); + if (ds < 0) { + pr_warn("No matching current value was found."); + return -EINVAL; + } + } else { + ds = YT8531_RGMII_RX_DS_DEFAULT; + } + + ret = ytphy_modify_ext(phydev, + YT8531_PAD_DRIVE_STRENGTH_CFG_REG, + YT8531_RGMII_RXC_DS_MASK, + FIELD_PREP(YT8531_RGMII_RXC_DS_MASK, ds)); + if (ret < 0) + return ret; + + /* set rgmii rx data driver strength */ + if (!ofnode_read_u32(phydev->node, "motorcomm,rx-data-drv-microamp", &val)) { + ds = yt8531_get_ds_map(phydev, val); + if (ds < 0) { + pr_warn("No matching current value was found."); + return -EINVAL; + } + } else { + ds = YT8531_RGMII_RX_DS_DEFAULT; + } + + ds_field_hi = FIELD_GET(BIT(2), ds); + ds_field_hi = FIELD_PREP(YT8531_RGMII_RXD_DS_HI_MASK, ds_field_hi); + + ds_field_low = FIELD_GET(GENMASK(1, 0), ds); + ds_field_low = FIELD_PREP(YT8531_RGMII_RXD_DS_LOW_MASK, ds_field_low); + + ret = ytphy_modify_ext(phydev, + YT8531_PAD_DRIVE_STRENGTH_CFG_REG, + YT8531_RGMII_RXD_DS_LOW_MASK | YT8531_RGMII_RXD_DS_HI_MASK, + ds_field_low | ds_field_hi); + if (ret < 0) + return ret; + + return 0; +} + static int yt8531_config(struct phy_device *phydev) { struct ytphy_plat_priv *priv = phydev->priv; @@ -487,6 +613,10 @@ static int yt8531_config(struct phy_device *phydev) return ret; } + ret = yt8531_set_ds(phydev); + if (ret < 0) + return ret; + return 0; } diff --git a/drivers/net/sni_ave.c b/drivers/net/sni_ave.c index 8eeecbc4cf3..a265ce9df57 100644 --- a/drivers/net/sni_ave.c +++ b/drivers/net/sni_ave.c @@ -777,7 +777,7 @@ static int ave_of_to_plat(struct udevice *dev) if (ret) { dev_err(dev, "Failed to get clocks property: %d\n", ret); - goto out_clk_free; + return ret; } priv->nclks++; } @@ -823,9 +823,6 @@ static int ave_of_to_plat(struct udevice *dev) out_reset_free: while (--nr >= 0) reset_free(&priv->rst[nr]); -out_clk_free: - while (--nc >= 0) - clk_free(&priv->clk[nc]); return ret; } diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c index 18a33c4c0e3..6da018c0f9d 100644 --- a/drivers/net/ti/am65-cpsw-nuss.c +++ b/drivers/net/ti/am65-cpsw-nuss.c @@ -948,7 +948,6 @@ static int am65_cpsw_probe_nuss(struct udevice *dev) cpsw_common->bus_freq); out: - clk_free(&cpsw_common->fclk); power_domain_free(&cpsw_common->pwrdmn); return ret; } diff --git a/drivers/phy/bcm6318-usbh-phy.c b/drivers/phy/bcm6318-usbh-phy.c index 1c10853940a..a2fa446cb1c 100644 --- a/drivers/phy/bcm6318-usbh-phy.c +++ b/drivers/phy/bcm6318-usbh-phy.c @@ -98,8 +98,6 @@ static int bcm6318_usbh_probe(struct udevice *dev) if (ret < 0) return ret; - clk_free(&clk); - /* enable power domain */ ret = power_domain_get(dev, &pwr_dom); if (ret < 0) diff --git a/drivers/phy/bcm6348-usbh-phy.c b/drivers/phy/bcm6348-usbh-phy.c index ce6be3d7dab..857fb575ef1 100644 --- a/drivers/phy/bcm6348-usbh-phy.c +++ b/drivers/phy/bcm6348-usbh-phy.c @@ -62,8 +62,6 @@ static int bcm6348_usbh_probe(struct udevice *dev) if (ret < 0) return ret; - clk_free(&clk); - /* perform reset */ ret = reset_get_by_index(dev, 0, &rst_ctl); if (ret < 0) diff --git a/drivers/phy/bcm6368-usbh-phy.c b/drivers/phy/bcm6368-usbh-phy.c index d057f1f52e8..1a2870d5149 100644 --- a/drivers/phy/bcm6368-usbh-phy.c +++ b/drivers/phy/bcm6368-usbh-phy.c @@ -137,8 +137,6 @@ static int bcm6368_usbh_probe(struct udevice *dev) if (ret < 0) return ret; - clk_free(&clk); - #if defined(CONFIG_POWER_DOMAIN) /* enable power domain */ ret = power_domain_get(dev, &pwr_dom); @@ -173,8 +171,6 @@ static int bcm6368_usbh_probe(struct udevice *dev) ret = clk_enable(&clk); if (ret < 0) return ret; - - clk_free(&clk); } mdelay(100); diff --git a/drivers/phy/meson-axg-mipi-dphy.c b/drivers/phy/meson-axg-mipi-dphy.c index a69b6c97594..faa1d9d6d37 100644 --- a/drivers/phy/meson-axg-mipi-dphy.c +++ b/drivers/phy/meson-axg-mipi-dphy.c @@ -369,7 +369,6 @@ int meson_axg_mipi_dphy_probe(struct udevice *dev) ret = clk_enable(&priv->clk); if (ret && ret != -ENOSYS && ret != -ENOTSUPP) { pr_err("failed to enable PHY clock\n"); - clk_free(&priv->clk); return ret; } #endif diff --git a/drivers/phy/meson-g12a-usb3-pcie.c b/drivers/phy/meson-g12a-usb3-pcie.c index 40a5da948dc..1eaff410efa 100644 --- a/drivers/phy/meson-g12a-usb3-pcie.c +++ b/drivers/phy/meson-g12a-usb3-pcie.c @@ -398,7 +398,6 @@ int meson_g12a_usb3_pcie_phy_probe(struct udevice *dev) ret = clk_enable(&priv->clk); if (ret && ret != -ENOENT && ret != -ENOTSUPP) { pr_err("failed to enable PHY clock\n"); - clk_free(&priv->clk); return ret; } #endif diff --git a/drivers/phy/meson-gxl-usb2.c b/drivers/phy/meson-gxl-usb2.c index 8f5e4a43661..d633effa404 100644 --- a/drivers/phy/meson-gxl-usb2.c +++ b/drivers/phy/meson-gxl-usb2.c @@ -203,7 +203,6 @@ int meson_gxl_usb2_phy_probe(struct udevice *dev) ret = clk_enable(&priv->clk); if (ret && ret != -ENOSYS && ret != -ENOTSUPP) { pr_err("failed to enable PHY clock\n"); - clk_free(&priv->clk); return ret; } #endif diff --git a/drivers/phy/phy-rcar-gen2.c b/drivers/phy/phy-rcar-gen2.c index 17940959246..e528c4ec579 100644 --- a/drivers/phy/phy-rcar-gen2.c +++ b/drivers/phy/phy-rcar-gen2.c @@ -172,7 +172,6 @@ static int rcar_gen2_phy_remove(struct udevice *dev) struct rcar_gen2_phy *priv = dev_get_priv(dev); clk_disable(&priv->clk); - clk_free(&priv->clk); return 0; } diff --git a/drivers/phy/phy-rcar-gen3.c b/drivers/phy/phy-rcar-gen3.c index 7159e7e8716..03c747b373b 100644 --- a/drivers/phy/phy-rcar-gen3.c +++ b/drivers/phy/phy-rcar-gen3.c @@ -142,7 +142,6 @@ static int rcar_gen3_phy_remove(struct udevice *dev) struct rcar_gen3_phy *priv = dev_get_priv(dev); clk_disable(&priv->clk); - clk_free(&priv->clk); return 0; } diff --git a/drivers/pinctrl/pinctrl-k210.c b/drivers/pinctrl/pinctrl-k210.c index 13f0a342686..ee35dfe1420 100644 --- a/drivers/pinctrl/pinctrl-k210.c +++ b/drivers/pinctrl/pinctrl-k210.c @@ -691,23 +691,19 @@ static int k210_pc_probe(struct udevice *dev) ret = clk_enable(&priv->clk); if (ret && ret != -ENOSYS && ret != -ENOTSUPP) - goto err; + return ret; ret = dev_read_phandle_with_args(dev, "canaan,k210-sysctl-power", NULL, 1, 0, &args); if (ret) - goto err; + return ret; - if (args.args_count != 1) { - ret = -EINVAL; - goto err; - } + if (args.args_count != 1) + return -EINVAL; priv->sysctl = syscon_node_to_regmap(args.node); - if (IS_ERR(priv->sysctl)) { - ret = PTR_ERR(priv->sysctl); - goto err; - } + if (IS_ERR(priv->sysctl)) + return PTR_ERR(priv->sysctl); priv->power_offset = args.args[0]; @@ -728,10 +724,6 @@ static int k210_pc_probe(struct udevice *dev) } return 0; - -err: - clk_free(&priv->clk); - return ret; } static const struct udevice_id k210_pc_ids[] = { diff --git a/drivers/power/domain/imx8mp-hsiomix.c b/drivers/power/domain/imx8mp-hsiomix.c index 6a721a934a7..e2d772c5ec7 100644 --- a/drivers/power/domain/imx8mp-hsiomix.c +++ b/drivers/power/domain/imx8mp-hsiomix.c @@ -111,7 +111,7 @@ static int imx8mp_hsiomix_probe(struct udevice *dev) ret = power_domain_get_by_name(dev, &priv->pd_bus, "bus"); if (ret < 0) - goto err_pd_bus; + return ret; ret = power_domain_get_by_name(dev, &priv->pd_usb, "usb"); if (ret < 0) @@ -133,8 +133,6 @@ err_pd_usb_phy1: power_domain_free(&priv->pd_usb); err_pd_usb: power_domain_free(&priv->pd_bus); -err_pd_bus: - clk_free(&priv->clk_usb); return ret; } diff --git a/drivers/rtc/stm32_rtc.c b/drivers/rtc/stm32_rtc.c index 1753283460d..ec7584c3d70 100644 --- a/drivers/rtc/stm32_rtc.c +++ b/drivers/rtc/stm32_rtc.c @@ -223,10 +223,8 @@ static int stm32_rtc_init(struct udevice *dev) return ret; ret = clk_enable(&clk); - if (ret) { - clk_free(&clk); + if (ret) return ret; - } rate = clk_get_rate(&clk); @@ -275,10 +273,8 @@ static int stm32_rtc_init(struct udevice *dev) unlock: stm32_rtc_lock(dev); - if (ret) { + if (ret) clk_disable(&clk); - clk_free(&clk); - } return ret; } @@ -298,17 +294,13 @@ static int stm32_rtc_probe(struct udevice *dev) return ret; ret = clk_enable(&clk); - if (ret) { - clk_free(&clk); + if (ret) return ret; - } ret = stm32_rtc_init(dev); - if (ret) { + if (ret) clk_disable(&clk); - clk_free(&clk); - } return ret; } diff --git a/drivers/serial/atmel_usart.c b/drivers/serial/atmel_usart.c index 9853f49c94f..9827c006fa8 100644 --- a/drivers/serial/atmel_usart.c +++ b/drivers/serial/atmel_usart.c @@ -253,8 +253,6 @@ static int atmel_serial_enable_clk(struct udevice *dev) priv->usart_clk_rate = clk_rate; - clk_free(&clk); - return 0; } #endif diff --git a/drivers/serial/serial_bcm6345.c b/drivers/serial/serial_bcm6345.c index 2359656a239..13bc51725cd 100644 --- a/drivers/serial/serial_bcm6345.c +++ b/drivers/serial/serial_bcm6345.c @@ -239,7 +239,6 @@ static int bcm6345_serial_probe(struct udevice *dev) if (ret < 0) return ret; priv->uartclk = clk_get_rate(&clk); - clk_free(&clk); /* initialize serial */ return bcm6345_serial_init(priv->base, priv->uartclk, CONFIG_BAUDRATE); diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c index a22623c316e..f4d96313b93 100644 --- a/drivers/serial/serial_msm.c +++ b/drivers/serial/serial_msm.c @@ -185,7 +185,6 @@ static int msm_uart_clk_init(struct udevice *dev) return ret; ret = clk_set_rate(&clk, clk_rate); - clk_free(&clk); if (ret < 0) return ret; diff --git a/drivers/serial/serial_pic32.c b/drivers/serial/serial_pic32.c index 3c5d37ce0ab..0a03a9a2549 100644 --- a/drivers/serial/serial_pic32.c +++ b/drivers/serial/serial_pic32.c @@ -155,7 +155,6 @@ static int pic32_uart_probe(struct udevice *dev) if (ret < 0) return ret; priv->uartclk = clk_get_rate(&clk); - clk_free(&clk); /* initialize serial */ return pic32_serial_init(priv->base, priv->uartclk, CONFIG_BAUDRATE); diff --git a/drivers/spi/atcspi200_spi.c b/drivers/spi/atcspi200_spi.c index de9c14837cd..70cb242cd31 100644 --- a/drivers/spi/atcspi200_spi.c +++ b/drivers/spi/atcspi200_spi.c @@ -362,7 +362,6 @@ static int atcspi200_spi_get_clk(struct udevice *bus) return -EINVAL; ns->clock = clk_rate; - clk_free(&clk); return 0; } diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c index cb64119f972..bd73e4fddf1 100644 --- a/drivers/spi/atmel-quadspi.c +++ b/drivers/spi/atmel-quadspi.c @@ -877,7 +877,6 @@ static int atmel_qspi_set_gclk(struct udevice *bus, uint hz) ret = clk_enable(&gclk); if (ret) dev_err(bus, "Failed to enable QSPI generic clock\n"); - clk_free(&gclk); return ret; } @@ -1000,7 +999,7 @@ static int atmel_qspi_enable_clk(struct udevice *dev) ret = clk_enable(&pclk); if (ret) { dev_err(dev, "Failed to enable QSPI peripheral clock\n"); - goto free_pclk; + return ret; } if (aq->caps->has_qspick) { @@ -1008,32 +1007,27 @@ static int atmel_qspi_enable_clk(struct udevice *dev) ret = clk_get_by_name(dev, "qspick", &qspick); if (ret) { dev_err(dev, "Missing QSPI peripheral clock\n"); - goto free_pclk; + return ret; } ret = clk_enable(&qspick); if (ret) dev_err(dev, "Failed to enable QSPI system clock\n"); - clk_free(&qspick); } else if (aq->caps->has_gclk) { ret = clk_get_by_name(dev, "gclk", &gclk); if (ret) { dev_err(dev, "Missing QSPI generic clock\n"); - goto free_pclk; + return ret; } ret = clk_enable(&gclk); if (ret) dev_err(dev, "Failed to enable QSPI system clock\n"); - clk_free(&gclk); } aq->bus_clk_rate = clk_get_rate(&pclk); if (!aq->bus_clk_rate) - ret = -EINVAL; - -free_pclk: - clk_free(&pclk); + return -EINVAL; return ret; } diff --git a/drivers/spi/atmel_spi.c b/drivers/spi/atmel_spi.c index aec6f4eca9a..d4f0c4c4483 100644 --- a/drivers/spi/atmel_spi.c +++ b/drivers/spi/atmel_spi.c @@ -338,8 +338,6 @@ static int atmel_spi_enable_clk(struct udevice *bus) priv->bus_clk_rate = clk_rate; - clk_free(&clk); - return 0; } diff --git a/drivers/spi/bcm63xx_hsspi.c b/drivers/spi/bcm63xx_hsspi.c index 19d9a5ae23c..23ac5bb76c0 100644 --- a/drivers/spi/bcm63xx_hsspi.c +++ b/drivers/spi/bcm63xx_hsspi.c @@ -581,8 +581,6 @@ static int bcm63xx_hsspi_probe(struct udevice *dev) if (ret < 0 && ret != -ENOSYS) return ret; - clk_free(&clk); - /* get clock rate */ ret = clk_get_by_name(dev, "pll", &clk); if (ret < 0 && ret != -ENOSYS) @@ -590,8 +588,6 @@ static int bcm63xx_hsspi_probe(struct udevice *dev) priv->clk_rate = clk_get_rate(&clk); - clk_free(&clk); - /* perform reset */ ret = reset_get_by_index(dev, 0, &rst_ctl); if (ret >= 0) { diff --git a/drivers/spi/bcm63xx_spi.c b/drivers/spi/bcm63xx_spi.c index 0600d56c69e..889ac1f966e 100644 --- a/drivers/spi/bcm63xx_spi.c +++ b/drivers/spi/bcm63xx_spi.c @@ -391,8 +391,6 @@ static int bcm63xx_spi_probe(struct udevice *dev) if (ret < 0) return ret; - clk_free(&clk); - /* perform reset */ ret = reset_get_by_index(dev, 0, &rst_ctl); if (ret < 0) diff --git a/drivers/spi/bcmbca_hsspi.c b/drivers/spi/bcmbca_hsspi.c index fbe315a7d45..af45882db0a 100644 --- a/drivers/spi/bcmbca_hsspi.c +++ b/drivers/spi/bcmbca_hsspi.c @@ -375,8 +375,6 @@ static int bcmbca_hsspi_probe(struct udevice *dev) if (ret < 0 && ret != -ENOSYS) return ret; - clk_free(&clk); - /* get clock rate */ ret = clk_get_by_name(dev, "pll", &clk); if (ret < 0 && ret != -ENOSYS) @@ -384,8 +382,6 @@ static int bcmbca_hsspi_probe(struct udevice *dev) priv->clk_rate = clk_get_rate(&clk); - clk_free(&clk); - /* initialize hardware */ writel(0, priv->regs + SPI_IR_MASK_REG); diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index dfc74c882d2..f4593c47b8c 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -236,7 +236,6 @@ static int cadence_spi_probe(struct udevice *bus) #endif } else { priv->ref_clk_hz = clk_get_rate(&clk); - clk_free(&clk); if (IS_ERR_VALUE(priv->ref_clk_hz)) return priv->ref_clk_hz; } diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c index 98908c5217f..22a79da2333 100644 --- a/drivers/spi/designware_spi.c +++ b/drivers/spi/designware_spi.c @@ -319,7 +319,6 @@ __weak int dw_spi_get_clk(struct udevice *bus, ulong *rate) err_rate: clk_disable(&priv->clk); - clk_free(&priv->clk); return -EINVAL; } @@ -743,10 +742,6 @@ static int dw_spi_remove(struct udevice *bus) ret = clk_disable(&priv->clk); if (ret) return ret; - - clk_free(&priv->clk); - if (ret) - return ret; #endif return 0; } diff --git a/drivers/spi/meson_spifc_a1.c b/drivers/spi/meson_spifc_a1.c index cca4debb412..943bf6986f1 100644 --- a/drivers/spi/meson_spifc_a1.c +++ b/drivers/spi/meson_spifc_a1.c @@ -343,15 +343,6 @@ static int amlogic_spifc_a1_probe(struct udevice *dev) return 0; } -static int amlogic_spifc_a1_remove(struct udevice *dev) -{ - struct amlogic_spifc_a1 *spifc = dev_get_priv(dev); - - clk_free(&spifc->clk); - - return 0; -} - static const struct udevice_id meson_spifc_ids[] = { { .compatible = "amlogic,a1-spifc", }, { } @@ -379,6 +370,5 @@ U_BOOT_DRIVER(meson_spifc_a1) = { .of_match = meson_spifc_ids, .ops = &amlogic_spifc_a1_ops, .probe = amlogic_spifc_a1_probe, - .remove = amlogic_spifc_a1_remove, .priv_auto = sizeof(struct amlogic_spifc_a1), }; diff --git a/drivers/spi/mvebu_a3700_spi.c b/drivers/spi/mvebu_a3700_spi.c index 52882e8b263..bba2383a111 100644 --- a/drivers/spi/mvebu_a3700_spi.c +++ b/drivers/spi/mvebu_a3700_spi.c @@ -296,15 +296,6 @@ static int mvebu_spi_of_to_plat(struct udevice *bus) return 0; } -static int mvebu_spi_remove(struct udevice *bus) -{ - struct mvebu_spi_plat *plat = dev_get_plat(bus); - - clk_free(&plat->clk); - - return 0; -} - static const struct dm_spi_ops mvebu_spi_ops = { .xfer = mvebu_spi_xfer, .set_speed = mvebu_spi_set_speed, @@ -328,5 +319,4 @@ U_BOOT_DRIVER(mvebu_spi) = { .of_to_plat = mvebu_spi_of_to_plat, .plat_auto = sizeof(struct mvebu_spi_plat), .probe = mvebu_spi_probe, - .remove = mvebu_spi_remove, }; diff --git a/drivers/spi/spi-aspeed-smc.c b/drivers/spi/spi-aspeed-smc.c index 39620310218..7d5f101a766 100644 --- a/drivers/spi/spi-aspeed-smc.c +++ b/drivers/spi/spi-aspeed-smc.c @@ -1148,7 +1148,6 @@ static int apseed_spi_of_to_plat(struct udevice *bus) } plat->hclk_rate = clk_get_rate(&hclk); - clk_free(&hclk); dev_dbg(bus, "ctrl_base = 0x%x, ahb_base = 0x%p, size = 0x%llx\n", (u32)priv->regs, plat->ahb_base, (fdt64_t)plat->ahb_sz); diff --git a/drivers/spi/stm32_spi.c b/drivers/spi/stm32_spi.c index 82f6ed783f9..ddb410a94c0 100644 --- a/drivers/spi/stm32_spi.c +++ b/drivers/spi/stm32_spi.c @@ -526,22 +526,16 @@ static int stm32_spi_of_to_plat(struct udevice *dev) ret = reset_get_by_index(dev, 0, &plat->rst_ctl); if (ret < 0) - goto clk_err; + return ret; ret = gpio_request_list_by_name(dev, "cs-gpios", plat->cs_gpios, ARRAY_SIZE(plat->cs_gpios), 0); if (ret < 0) { dev_err(dev, "Can't get %s cs gpios: %d", dev->name, ret); - ret = -ENOENT; - goto clk_err; + return -ENOENT; } return 0; - -clk_err: - clk_free(&plat->clk); - - return ret; } static int stm32_spi_probe(struct udevice *dev) @@ -610,7 +604,6 @@ static int stm32_spi_probe(struct udevice *dev) clk_err: clk_disable(&plat->clk); - clk_free(&plat->clk); return ret; }; @@ -630,13 +623,7 @@ static int stm32_spi_remove(struct udevice *dev) reset_free(&plat->rst_ctl); - ret = clk_disable(&plat->clk); - if (ret < 0) - return ret; - - clk_free(&plat->clk); - - return ret; + return clk_disable(&plat->clk); }; static const struct dm_spi_ops stm32_spi_ops = { diff --git a/drivers/timer/dw-apb-timer.c b/drivers/timer/dw-apb-timer.c index 6cd25251f94..0607f751ca7 100644 --- a/drivers/timer/dw-apb-timer.c +++ b/drivers/timer/dw-apb-timer.c @@ -74,8 +74,6 @@ static int dw_apb_timer_probe(struct udevice *dev) return ret; uc_priv->clock_rate = clk_get_rate(&clk); - - clk_free(&clk); } /* init timer */ diff --git a/drivers/timer/ostm_timer.c b/drivers/timer/ostm_timer.c index 3ec729d2c43..3bf0d4647b5 100644 --- a/drivers/timer/ostm_timer.c +++ b/drivers/timer/ostm_timer.c @@ -49,8 +49,6 @@ static int ostm_probe(struct udevice *dev) return ret; uc_priv->clock_rate = clk_get_rate(&clk); - - clk_free(&clk); #else uc_priv->clock_rate = get_board_sys_clk() / 2; #endif diff --git a/drivers/usb/dwc3/dwc3-meson-g12a.c b/drivers/usb/dwc3/dwc3-meson-g12a.c index 196035215a6..1a3e9350c46 100644 --- a/drivers/usb/dwc3/dwc3-meson-g12a.c +++ b/drivers/usb/dwc3/dwc3-meson-g12a.c @@ -361,10 +361,8 @@ static int dwc3_meson_g12a_clk_init(struct dwc3_meson_g12a *priv) #if CONFIG_IS_ENABLED(CLK) ret = clk_enable(&priv->clk); - if (ret) { - clk_free(&priv->clk); + if (ret) return ret; - } #endif return 0; diff --git a/drivers/usb/dwc3/dwc3-meson-gxl.c b/drivers/usb/dwc3/dwc3-meson-gxl.c index cbe8aaa005b..2ce915701a8 100644 --- a/drivers/usb/dwc3/dwc3-meson-gxl.c +++ b/drivers/usb/dwc3/dwc3-meson-gxl.c @@ -284,10 +284,8 @@ static int dwc3_meson_gxl_clk_init(struct dwc3_meson_gxl *priv) #if CONFIG_IS_ENABLED(CLK) ret = clk_enable(&priv->clk); - if (ret) { - clk_free(&priv->clk); + if (ret) return ret; - } #endif return 0; diff --git a/drivers/usb/host/ehci-atmel.c b/drivers/usb/host/ehci-atmel.c index fba3595e10f..c6d50fd4551 100644 --- a/drivers/usb/host/ehci-atmel.c +++ b/drivers/usb/host/ehci-atmel.c @@ -70,13 +70,7 @@ static int ehci_atmel_enable_clk(struct udevice *dev) if (ret) return -EINVAL; - ret = clk_enable(&clk); - if (ret) - return ret; - - clk_free(&clk); - - return 0; + return clk_enable(&clk); } static int ehci_atmel_probe(struct udevice *dev) diff --git a/drivers/usb/host/ohci-da8xx.c b/drivers/usb/host/ohci-da8xx.c index 33c4a911a09..d3d73d23844 100644 --- a/drivers/usb/host/ohci-da8xx.c +++ b/drivers/usb/host/ohci-da8xx.c @@ -115,7 +115,6 @@ static int ohci_da8xx_probe(struct udevice *dev) err = clk_enable(&priv->clocks[i]); if (err) { dev_err(dev, "failed to enable clock %d\n", i); - clk_free(&priv->clocks[i]); goto clk_err; } priv->clock_count++; diff --git a/drivers/usb/host/xhci-rcar.c b/drivers/usb/host/xhci-rcar.c index 5fc7afb7d21..fedcf786929 100644 --- a/drivers/usb/host/xhci-rcar.c +++ b/drivers/usb/host/xhci-rcar.c @@ -90,7 +90,7 @@ static int xhci_rcar_probe(struct udevice *dev) ret = clk_enable(&plat->clk); if (ret) { dev_err(dev, "Failed to enable USB3 clock\n"); - goto err_clk; + return ret; } ctx->hcd = (struct xhci_hccr *)plat->hcd_base; @@ -114,8 +114,6 @@ static int xhci_rcar_probe(struct udevice *dev) err_fw: clk_disable(&plat->clk); -err_clk: - clk_free(&plat->clk); return ret; } @@ -127,7 +125,6 @@ static int xhci_rcar_deregister(struct udevice *dev) ret = xhci_deregister(dev); clk_disable(&plat->clk); - clk_free(&plat->clk); return ret; } diff --git a/drivers/video/atmel_hlcdfb.c b/drivers/video/atmel_hlcdfb.c index 2bf19a6684b..652ba141801 100644 --- a/drivers/video/atmel_hlcdfb.c +++ b/drivers/video/atmel_hlcdfb.c @@ -62,8 +62,6 @@ static int at91_hlcdc_enable_clk(struct udevice *dev) priv->clk_rate = clk_rate; - clk_free(&clk); - return 0; } diff --git a/drivers/video/mali_dp.c b/drivers/video/mali_dp.c index cbcdb99e1f0..dbb2f538617 100644 --- a/drivers/video/mali_dp.c +++ b/drivers/video/mali_dp.c @@ -360,25 +360,18 @@ static int malidp_probe(struct udevice *dev) err = malidp_setup_mode(priv, &timings); if (err) - goto fail_timings; + return err; malidp_setup_layer(priv, &timings, MALIDP_LAYER_LV1, (phys_addr_t)uc_plat->base); err = malidp_leave_config(priv); if (err) - goto fail_timings; + return err; malidp_set_configvalid(priv); return 0; - -fail_timings: - clk_free(&priv->aclk); -fail_aclk: - clk_free(&priv->pxlclk); - - return err; } static int malidp_bind(struct udevice *dev) diff --git a/drivers/video/rockchip/rk3288_hdmi.c b/drivers/video/rockchip/rk3288_hdmi.c index 327ae787125..8bedee55ad4 100644 --- a/drivers/video/rockchip/rk3288_hdmi.c +++ b/drivers/video/rockchip/rk3288_hdmi.c @@ -67,10 +67,8 @@ static int rk3288_clk_config(struct udevice *dev) * monitor wants */ ret = clk_get_by_index(uc_plat->src_dev, 0, &clk); - if (ret >= 0) { + if (ret >= 0) ret = clk_set_rate(&clk, 384000000); - clk_free(&clk); - } if (ret < 0) { debug("%s: Failed to set clock in source device '%s': ret=%d\n", __func__, uc_plat->src_dev->name, ret); diff --git a/drivers/video/rockchip/rk_edp.c b/drivers/video/rockchip/rk_edp.c index 3697d582510..dbd70ad583a 100644 --- a/drivers/video/rockchip/rk_edp.c +++ b/drivers/video/rockchip/rk_edp.c @@ -1095,20 +1095,16 @@ static int rk_edp_probe(struct udevice *dev) if (edp_data->chip_type == RK3288_DP) { ret = clk_get_by_index(dev, 1, &clk); - if (ret >= 0) { + if (ret >= 0) ret = clk_set_rate(&clk, 0); - clk_free(&clk); - } if (ret) { debug("%s: Failed to set EDP clock: ret=%d\n", __func__, ret); return ret; } } ret = clk_get_by_index(uc_plat->src_dev, 0, &clk); - if (ret >= 0) { + if (ret >= 0) ret = clk_set_rate(&clk, 192000000); - clk_free(&clk); - } if (ret < 0) { debug("%s: Failed to set clock in source device '%s': ret=%d\n", __func__, uc_plat->src_dev->name, ret); diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 569726119ca..8318fd77a32 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -130,6 +130,12 @@ config WDT_AT91 Select this to enable Microchip watchdog timer, which can be found on some AT91 devices. +config WDT_ATCWDT200 + bool "Andes watchdog timer support" + depends on WDT + help + Select this to enable Andes ATCWDT200 watchdog timer + config WDT_BCM6345 bool "BCM6345 watchdog timer support" depends on WDT && (ARCH_BMIPS || BCM6856 || \ diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 5520d3d9ae8..7b39adcf0ff 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -22,6 +22,7 @@ obj-$(CONFIG_WDT_ARM_SMC) += arm_smc_wdt.o obj-$(CONFIG_WDT_ARMADA_37XX) += armada-37xx-wdt.o obj-$(CONFIG_WDT_ASPEED) += ast_wdt.o obj-$(CONFIG_WDT_AST2600) += ast2600_wdt.o +obj-$(CONFIG_WDT_ATCWDT200) += atcwdt200_wdt.o obj-$(CONFIG_WDT_BCM2835) += bcm2835_wdt.o obj-$(CONFIG_WDT_BCM6345) += bcm6345_wdt.o obj-$(CONFIG_WDT_BOOKE) += booke_wdt.o diff --git a/drivers/watchdog/atcwdt200_wdt.c b/drivers/watchdog/atcwdt200_wdt.c new file mode 100644 index 00000000000..a29b42d607e --- /dev/null +++ b/drivers/watchdog/atcwdt200_wdt.c @@ -0,0 +1,220 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023 Andes Technology Corporation. + * + */ + +#include <asm/io.h> +#include <dm.h> +#include <hang.h> +#include <linux/bitops.h> +#include <wdt.h> + +#define NODE_NOT_FOUND 0xFFFFFFFF + +#define WDT_WP_MAGIC 0x5aa5 +#define WDT_RESTART_MAGIC 0xcafe + +/* Control Register */ +#define REG_WDT_ID 0x00 +#define REG_WDT_CFG 0x10 +#define REG_WDT_RS 0x14 +#define REG_WDT_WE 0x18 +#define REG_WDT_STA 0x1C + +#define RST_TIME_OFF 8 +#define RST_TIME_MSK (0x7 << RST_TIME_OFF) +#define RST_CLK_128 (0 << RST_TIME_OFF) +#define RST_CLK_256 (1 << RST_TIME_OFF) +#define RST_CLK_512 (2 << RST_TIME_OFF) +#define RST_CLK_1024 (3 << RST_TIME_OFF) +#define INT_TIME_OFF 4 +#define INT_TIME_MSK (0xf << INT_TIME_OFF) +#define INT_CLK_2_6 (0 << INT_TIME_OFF) /* clk period*2^6 */ +#define INT_CLK_2_8 (1 << INT_TIME_OFF) /* clk period*2^8 */ +#define INT_CLK_2_10 (2 << INT_TIME_OFF) /* clk period*2^10 */ +#define INT_CLK_2_11 (3 << INT_TIME_OFF) /* clk period*2^11 */ +#define INT_CLK_2_12 (4 << INT_TIME_OFF) /* clk period*2^12 */ +#define INT_CLK_2_13 (5 << INT_TIME_OFF) /* clk period*2^13 */ +#define INT_CLK_2_14 (6 << INT_TIME_OFF) /* clk period*2^14 */ +#define INT_CLK_2_15 (7 << INT_TIME_OFF) /* clk period*2^15 */ +#define INT_CLK_2_17 (8 << INT_TIME_OFF) /* clk period*2^17 */ +#define INT_CLK_2_19 (9 << INT_TIME_OFF) /* clk period*2^19 */ +#define INT_CLK_2_21 (10 << INT_TIME_OFF) /* clk period*2^21 */ +#define INT_CLK_2_23 (11 << INT_TIME_OFF) /* clk period*2^23 */ +#define INT_CLK_2_25 (12 << INT_TIME_OFF) /* clk period*2^25 */ +#define INT_CLK_2_27 (13 << INT_TIME_OFF) /* clk period*2^27 */ +#define INT_CLK_2_29 (14 << INT_TIME_OFF) /* clk period*2^29 */ +#define INT_CLK_2_31 (15 << INT_TIME_OFF) /* clk period*2^31 */ +#define INT_CLK_MIN 0x0 +#define INT_CLK_MAX_16B 0x7 +#define INT_CLK_MAX_32B 0xF +#define RST_EN BIT(3) +#define INT_EN BIT(2) +#define CLK_PCLK BIT(1) +#define WDT_EN BIT(0) +#define INT_EXPIRED BIT(0) + +#define INT_TIME_ARRAY 16 +#define RST_TIME_ARRAY 8 + +struct wdt_priv { + void __iomem *base; + u32 wdt_clk_src; + u32 clk_freq; + u8 max_clk; +}; + +static inline u8 atcwdt_get_2_power_of_n(u8 index, u8 type) +{ + const u8 div_int[INT_TIME_ARRAY] = {6, 8, 10, 11, 12, 13, 14, 15, + 17, 19, 21, 23, 25, 27, 29, 31}; + const u8 div_rst[RST_TIME_ARRAY] = {7, 8, 9, 10, 11, 12, 13, 14}; + const u8 *pdiv; + + if (type == RST_TIME_ARRAY) + pdiv = div_rst; + else + pdiv = div_int; + + if (index >= type) + index = type - 1; + + return pdiv[index]; +} + +static u8 atcwdt_search_msb(u64 freq_ms, u8 type) +{ + u64 result; + u64 freq_sec; + u8 index; + + freq_sec = freq_ms / 1000; + for (index = 0; index < type; index++) { + result = freq_sec >> atcwdt_get_2_power_of_n(index, type); + + if (result <= 1) + break; + } + + return index; +} + +static int atcwdt_wdt_start(struct udevice *dev, u64 timeout, ulong flags) +{ + struct wdt_priv *priv = dev_get_priv(dev); + u64 rst_max_count; + u32 rst_max_time_ms; + u64 rst_time_ms; + u64 int_time_ms; + u8 rst_time; + u8 int_time; + + rst_max_count = 1 << atcwdt_get_2_power_of_n(RST_TIME_ARRAY, RST_TIME_ARRAY); + rst_max_time_ms = (rst_max_count * 1000) / priv->clk_freq; + + if (timeout > rst_max_time_ms) { + int_time_ms = timeout - rst_max_time_ms; + rst_time_ms = rst_max_time_ms; + } else { + int_time_ms = 0; + rst_time_ms = timeout; + } + + rst_time = atcwdt_search_msb(rst_time_ms * priv->clk_freq, RST_TIME_ARRAY); + + if (int_time_ms) { + int_time = atcwdt_search_msb(int_time_ms * priv->clk_freq, INT_TIME_ARRAY); + if (int_time > priv->max_clk) + int_time = priv->max_clk; + } else { + int_time = 0; + } + + writel(WDT_WP_MAGIC, priv->base + REG_WDT_WE); + writel(((rst_time << RST_TIME_OFF) & RST_TIME_MSK) | ((int_time << INT_TIME_OFF) & + INT_TIME_MSK) | INT_EN | RST_EN | priv->wdt_clk_src | WDT_EN, + priv->base + REG_WDT_CFG); + + return 0; +} + +static int atcwdt_wdt_stop(struct udevice *dev) +{ + struct wdt_priv *priv = dev_get_priv(dev); + + writel(WDT_WP_MAGIC, priv->base + REG_WDT_WE); + writel(0, priv->base + REG_WDT_CFG); + + return 0; +} + +static int atcwdt_wdt_restart(struct udevice *dev) +{ + struct wdt_priv *priv = dev_get_priv(dev); + + writel(WDT_WP_MAGIC, priv->base + REG_WDT_WE); + writel(WDT_RESTART_MAGIC, priv->base + REG_WDT_RS); + setbits_le32(priv->base + REG_WDT_STA, INT_EXPIRED); + + return 0; +} + +static int atcwdt_wdt_expire_now(struct udevice *dev, ulong flags) +{ + atcwdt_wdt_start(dev, 0, 0); + hang(); + + return 0; +} + +static int atcwdt_wdt_probe(struct udevice *dev) +{ + struct wdt_priv *priv = dev_get_priv(dev); + int timer_16bit; + + priv->base = dev_remap_addr_index(dev, 0); + if (!priv->base) + return -EFAULT; + + priv->wdt_clk_src = dev_read_u32_default(dev, "clock-source", NODE_NOT_FOUND); + if (priv->wdt_clk_src == NODE_NOT_FOUND || priv->wdt_clk_src > 1) + priv->wdt_clk_src = CLK_PCLK; + + timer_16bit = dev_read_u32_default(dev, "16bit_timer", NODE_NOT_FOUND); + if (timer_16bit == 1 || timer_16bit == NODE_NOT_FOUND) + priv->max_clk = INT_CLK_MAX_16B; + else + priv->max_clk = INT_CLK_MAX_32B; + + priv->clk_freq = dev_read_u32_default(dev, "clock-frequency", NODE_NOT_FOUND); + if (priv->clk_freq == NODE_NOT_FOUND) { + printf("atcwdt200: Please provide a valid \"clock-frequency\" in DTB\n"); + return -EINVAL; + } + + atcwdt_wdt_stop(dev); + + return 0; +} + +static const struct wdt_ops atcwdt_wdt_ops = { + .start = atcwdt_wdt_start, + .reset = atcwdt_wdt_restart, + .stop = atcwdt_wdt_stop, + .expire_now = atcwdt_wdt_expire_now, +}; + +static const struct udevice_id atcwdt_wdt_ids[] = { + {.compatible = "andestech,atcwdt200"}, + {} +}; + +U_BOOT_DRIVER(atcwdt) = { + .name = "atcwdt200", + .id = UCLASS_WDT, + .probe = atcwdt_wdt_probe, + .of_match = atcwdt_wdt_ids, + .ops = &atcwdt_wdt_ops, + .priv_auto = sizeof(struct wdt_priv), +}; diff --git a/drivers/watchdog/designware_wdt.c b/drivers/watchdog/designware_wdt.c index 447a22d3b36..b22e0ee06a4 100644 --- a/drivers/watchdog/designware_wdt.c +++ b/drivers/watchdog/designware_wdt.c @@ -124,13 +124,11 @@ static int designware_wdt_probe(struct udevice *dev) ret = clk_enable(&clk); if (ret) - goto err; + return ret; priv->clk_khz = clk_get_rate(&clk) / 1000; - if (!priv->clk_khz) { - ret = -EINVAL; - goto err; - } + if (!priv->clk_khz) + return -EINVAL; #else priv->clk_khz = CFG_DW_WDT_CLOCK_KHZ; #endif @@ -139,21 +137,15 @@ static int designware_wdt_probe(struct udevice *dev) ofnode_read_prop(dev_ofnode(dev), "resets", &ret)) { ret = reset_get_bulk(dev, &priv->resets); if (ret) - goto err; + return ret; ret = reset_deassert_bulk(&priv->resets); if (ret) - goto err; + return ret; } /* reset to disable the watchdog */ return designware_wdt_stop(dev); - -err: -#if CONFIG_IS_ENABLED(CLK) - clk_free(&clk); -#endif - return ret; } static const struct wdt_ops designware_wdt_ops = { diff --git a/drivers/watchdog/meson_gxbb_wdt.c b/drivers/watchdog/meson_gxbb_wdt.c index 6ab005813f9..01a35b3ab30 100644 --- a/drivers/watchdog/meson_gxbb_wdt.c +++ b/drivers/watchdog/meson_gxbb_wdt.c @@ -98,10 +98,8 @@ static int amlogic_wdt_probe(struct udevice *dev) return ret; ret = clk_enable(&clk); - if (ret) { - clk_free(&clk); + if (ret) return ret; - } /* Setup with 1ms timebase */ writel(((clk_get_rate(&clk) / 1000) & GXBB_WDT_CTRL_DIV_MASK) | |