diff options
Diffstat (limited to 'drivers')
86 files changed, 14287 insertions, 259 deletions
diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig index 48529a6982f..5283d8981e0 100644 --- a/drivers/block/Kconfig +++ b/drivers/block/Kconfig @@ -109,7 +109,7 @@ config EFI_MEDIA config SPL_BLK_FS bool "Load images from filesystems on block devices" - depends on SPL_BLK + depends on SPL_BLK && SPL_FS_LOADER help Use generic support to load images from fat/ext filesystems on different types of block devices such as NVMe. diff --git a/drivers/bootcount/Kconfig b/drivers/bootcount/Kconfig index 2105cea3d45..fa6d8e71281 100644 --- a/drivers/bootcount/Kconfig +++ b/drivers/bootcount/Kconfig @@ -6,14 +6,13 @@ menuconfig BOOTCOUNT_LIMIT bool "Enable support for checking boot count limit" help Enable checking for exceeding the boot count limit. - More information: http://www.denx.de/wiki/DULG/UBootBootCountLimit + More information: https://docs.u-boot.org/en/latest/api/bootcount.html if BOOTCOUNT_LIMIT choice prompt "Boot count device" default BOOTCOUNT_AM33XX if AM33XX || SOC_DA8XX - default BOOTCOUNT_AT91 if AT91SAM9XE default BOOTCOUNT_GENERIC config BOOTCOUNT_GENERIC diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 9acbc47fe8e..d9d518d7038 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -257,6 +257,7 @@ source "drivers/clk/mvebu/Kconfig" source "drivers/clk/owl/Kconfig" source "drivers/clk/qcom/Kconfig" source "drivers/clk/renesas/Kconfig" +source "drivers/clk/sophgo/Kconfig" source "drivers/clk/sunxi/Kconfig" source "drivers/clk/sifive/Kconfig" source "drivers/clk/starfive/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 847b9b29110..f9b90a38b00 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -44,6 +44,7 @@ obj-$(CONFIG_CLK_QCOM) += qcom/ obj-$(CONFIG_CLK_RENESAS) += renesas/ obj-$(CONFIG_$(SPL_TPL_)CLK_SCMI) += clk_scmi.o obj-$(CONFIG_CLK_SIFIVE) += sifive/ +obj-$(CONFIG_CLK_SOPHGO) += sophgo/ obj-$(CONFIG_CLK_SUNXI) += sunxi/ obj-$(CONFIG_CLK_UNIPHIER) += uniphier/ obj-$(CONFIG_CLK_VERSACLOCK) += clk_versaclock.o diff --git a/drivers/clk/analogbits/wrpll-cln28hpc.c b/drivers/clk/analogbits/wrpll-cln28hpc.c index a3cb109d357..537c696b727 100644 --- a/drivers/clk/analogbits/wrpll-cln28hpc.c +++ b/drivers/clk/analogbits/wrpll-cln28hpc.c @@ -81,7 +81,7 @@ static int __wrpll_calc_filter_range(unsigned long post_divr_freq) { if (post_divr_freq < MIN_POST_DIVR_FREQ || post_divr_freq > MAX_POST_DIVR_FREQ) { - WARN(1, "%s: post-divider reference freq out of range: %lu", + WARN(1, "%s: post-divider reference freq out of range: %lu\n", __func__, post_divr_freq); return -ERANGE; } @@ -229,7 +229,7 @@ int wrpll_configure_for_rate(struct wrpll_cfg *c, u32 target_rate, int range; if (c->flags == 0) { - WARN(1, "%s called with uninitialized PLL config", __func__); + WARN(1, "%s called with uninitialized PLL config\n", __func__); return -EINVAL; } @@ -335,7 +335,7 @@ unsigned long wrpll_calc_output_rate(const struct wrpll_cfg *c, u64 n; if (c->flags & WRPLL_FLAGS_EXT_FEEDBACK_MASK) { - WARN(1, "external feedback mode not yet supported"); + WARN(1, "external feedback mode not yet supported\n"); return ULONG_MAX; } diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 45d63c6d6db..0d2c0ac225c 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -86,6 +86,14 @@ config CLK_QCOM_SM8650 on the Snapdragon SM8650 SoC. This driver supports the clocks and resets exposed by the GCC hardware block. +config CLK_QCOM_SC7280 + bool "Qualcomm SC7280 GCC" + select CLK_QCOM + help + Say Y here to enable support for the Global Clock Controller + on the Snapdragon SC7280 SoC. This driver supports the clocks + and resets exposed by the GCC hardware block. + endmenu endif diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index dec20e4b594..e223c131ee4 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -9,6 +9,7 @@ obj-$(CONFIG_CLK_QCOM_APQ8096) += clock-apq8096.o obj-$(CONFIG_CLK_QCOM_IPQ4019) += clock-ipq4019.o obj-$(CONFIG_CLK_QCOM_QCM2290) += clock-qcm2290.o obj-$(CONFIG_CLK_QCOM_QCS404) += clock-qcs404.o +obj-$(CONFIG_CLK_QCOM_SC7280) += clock-sc7280.o obj-$(CONFIG_CLK_QCOM_SM6115) += clock-sm6115.o obj-$(CONFIG_CLK_QCOM_SM8250) += clock-sm8250.o obj-$(CONFIG_CLK_QCOM_SM8550) += clock-sm8550.o diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h index f6445c8f566..7aa6ca59aad 100644 --- a/drivers/clk/qcom/clock-qcom.h +++ b/drivers/clk/qcom/clock-qcom.h @@ -11,6 +11,7 @@ #define CFG_CLK_SRC_GPLL0 (1 << 8) #define CFG_CLK_SRC_GPLL0_AUX2 (2 << 8) #define CFG_CLK_SRC_GPLL9 (2 << 8) +#define CFG_CLK_SRC_GPLL0_ODD (3 << 8) #define CFG_CLK_SRC_GPLL6 (4 << 8) #define CFG_CLK_SRC_GPLL7 (3 << 8) #define CFG_CLK_SRC_GPLL4 (5 << 8) diff --git a/drivers/clk/qcom/clock-sc7280.c b/drivers/clk/qcom/clock-sc7280.c new file mode 100644 index 00000000000..5d343f12051 --- /dev/null +++ b/drivers/clk/qcom/clock-sc7280.c @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Clock drivers for Qualcomm sc7280 + * + * (C) Copyright 2024 Linaro Ltd. + */ + +#include <linux/types.h> +#include <clk-uclass.h> +#include <dm.h> +#include <linux/delay.h> +#include <asm/io.h> +#include <linux/bug.h> +#include <linux/bitops.h> +#include <dt-bindings/clock/qcom,gcc-sc7280.h> + +#include "clock-qcom.h" + +#define USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR 0xf038 +#define USB30_PRIM_MASTER_CLK_CMD_RCGR 0xf020 + +static ulong sc7280_set_rate(struct clk *clk, ulong rate) +{ + struct msm_clk_priv *priv = dev_get_priv(clk->dev); + + if (clk->id < priv->data->num_clks) + debug("%s: %s, requested rate=%ld\n", __func__, priv->data->clks[clk->id].name, rate); + + switch (clk->id) { + case GCC_USB30_PRIM_MOCK_UTMI_CLK: + WARN(rate != 19200000, "Unexpected rate for USB30_PRIM_MOCK_UTMI_CLK: %lu\n", rate); + clk_rcg_set_rate(priv->base, USB30_PRIM_MASTER_CLK_CMD_RCGR, 0, CFG_CLK_SRC_CXO); + return rate; + case GCC_USB30_PRIM_MASTER_CLK: + WARN(rate != 200000000, "Unexpected rate for USB30_PRIM_MASTER_CLK: %lu\n", rate); + clk_rcg_set_rate_mnd(priv->base, USB30_PRIM_MASTER_CLK_CMD_RCGR, + 1, 0, 0, CFG_CLK_SRC_GPLL0_ODD, 8); + clk_rcg_set_rate(priv->base, 0xf064, 0, 0); + return rate; + default: + return 0; + } +} + +static const struct gate_clk sc7280_clks[] = { + GATE_CLK(GCC_CFG_NOC_USB3_PRIM_AXI_CLK, 0xf07c, 1), + GATE_CLK(GCC_USB30_PRIM_MASTER_CLK, 0xf010, 1), + GATE_CLK(GCC_AGGRE_USB3_PRIM_AXI_CLK, 0xf080, 1), + GATE_CLK(GCC_USB30_PRIM_SLEEP_CLK, 0xf018, 1), + GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0xf01c, 1), + GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK, 0xf054, 1), + GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0xf058, 1), +}; + +static int sc7280_enable(struct clk *clk) +{ + struct msm_clk_priv *priv = dev_get_priv(clk->dev); + + if (priv->data->num_clks < clk->id) { + debug("%s: unknown clk id %lu\n", __func__, clk->id); + return 0; + } + + debug("%s: clk %ld: %s\n", __func__, clk->id, sc7280_clks[clk->id].name); + + switch (clk->id) { + case GCC_AGGRE_USB3_PRIM_AXI_CLK: + qcom_gate_clk_en(priv, GCC_USB30_PRIM_MASTER_CLK); + fallthrough; + case GCC_USB30_PRIM_MASTER_CLK: + qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_AUX_CLK); + qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_COM_AUX_CLK); + break; + } + + qcom_gate_clk_en(priv, clk->id); + + return 0; +} + +static const struct qcom_reset_map sc7280_gcc_resets[] = { + [GCC_PCIE_0_BCR] = { 0x6b000 }, + [GCC_PCIE_0_PHY_BCR] = { 0x6c01c }, + [GCC_PCIE_1_BCR] = { 0x8d000 }, + [GCC_PCIE_1_PHY_BCR] = { 0x8e01c }, + [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 }, + [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 }, + [GCC_SDCC1_BCR] = { 0x75000 }, + [GCC_SDCC2_BCR] = { 0x14000 }, + [GCC_SDCC4_BCR] = { 0x16000 }, + [GCC_UFS_PHY_BCR] = { 0x77000 }, + [GCC_USB30_PRIM_BCR] = { 0xf000 }, + [GCC_USB30_SEC_BCR] = { 0x9e000 }, + [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 }, + [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 }, + [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 }, + [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, +}; + +static const struct qcom_power_map sc7280_gdscs[] = { + [GCC_UFS_PHY_GDSC] = { 0x77004 }, + [GCC_USB30_PRIM_GDSC] = { 0xf004 }, +}; + +static struct msm_clk_data qcs404_gcc_data = { + .resets = sc7280_gcc_resets, + .num_resets = ARRAY_SIZE(sc7280_gcc_resets), + .clks = sc7280_clks, + .num_clks = ARRAY_SIZE(sc7280_clks), + + .power_domains = sc7280_gdscs, + .num_power_domains = ARRAY_SIZE(sc7280_gdscs), + + .enable = sc7280_enable, + .set_rate = sc7280_set_rate, +}; + +static const struct udevice_id gcc_sc7280_of_match[] = { + { + .compatible = "qcom,gcc-sc7280", + .data = (ulong)&qcs404_gcc_data, + }, + { } +}; + +U_BOOT_DRIVER(gcc_sc7280) = { + .name = "gcc_sc7280", + .id = UCLASS_NOP, + .of_match = gcc_sc7280_of_match, + .bind = qcom_cc_bind, + .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF, +}; diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c index ceb2c6fab0d..e55a26ab8fd 100644 --- a/drivers/clk/sifive/fu540-prci.c +++ b/drivers/clk/sifive/fu540-prci.c @@ -58,7 +58,7 @@ static const struct __prci_clock_ops sifive_fu540_prci_tlclksel_clk_ops = { }; /* List of clock controls provided by the PRCI */ -struct __prci_clock __prci_init_clocks_fu540[] = { +static struct __prci_clock __prci_init_clocks_fu540[] = { [PRCI_CLK_COREPLL] = { .name = "corepll", .parent_name = "hfclk", @@ -83,3 +83,8 @@ struct __prci_clock __prci_init_clocks_fu540[] = { .ops = &sifive_fu540_prci_tlclksel_clk_ops, }, }; + +const struct prci_clk_desc prci_clk_fu540 = { + .clks = __prci_init_clocks_fu540, + .num_clks = ARRAY_SIZE(__prci_init_clocks_fu540), +}; diff --git a/drivers/clk/sifive/fu540-prci.h b/drivers/clk/sifive/fu540-prci.h deleted file mode 100644 index 113301107da..00000000000 --- a/drivers/clk/sifive/fu540-prci.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2020-2021 SiFive, Inc. - * Zong Li - * Pragnesh Patel - */ - -#ifndef __SIFIVE_CLK_FU540_PRCI_H -#define __SIFIVE_CLK_FU540_PRCI_H - -#include "sifive-prci.h" - -#define NUM_CLOCK_FU540 4 - -extern struct __prci_clock __prci_init_clocks_fu540[NUM_CLOCK_FU540]; - -static const struct prci_clk_desc prci_clk_fu540 = { - .clks = __prci_init_clocks_fu540, - .num_clks = ARRAY_SIZE(__prci_init_clocks_fu540), -}; - -#endif /* __SIFIVE_CLK_FU540_PRCI_H */ diff --git a/drivers/clk/sifive/fu740-prci.c b/drivers/clk/sifive/fu740-prci.c index 5edc864e4bd..4274b215d2f 100644 --- a/drivers/clk/sifive/fu740-prci.c +++ b/drivers/clk/sifive/fu740-prci.c @@ -102,7 +102,7 @@ static const struct __prci_clock_ops sifive_fu740_prci_pcieaux_clk_ops = { }; /* List of clock controls provided by the PRCI */ -struct __prci_clock __prci_init_clocks_fu740[] = { +static struct __prci_clock __prci_init_clocks_fu740[] = { [FU740_PRCI_CLK_COREPLL] = { .name = "corepll", .parent_name = "hfclk", @@ -156,3 +156,8 @@ struct __prci_clock __prci_init_clocks_fu740[] = { .pwd = &__prci_pcieaux_data, } }; + +const struct prci_clk_desc prci_clk_fu740 = { + .clks = __prci_init_clocks_fu740, + .num_clks = ARRAY_SIZE(__prci_init_clocks_fu740), +}; diff --git a/drivers/clk/sifive/fu740-prci.h b/drivers/clk/sifive/fu740-prci.h deleted file mode 100644 index b74f0789061..00000000000 --- a/drivers/clk/sifive/fu740-prci.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2020-2021 SiFive, Inc. - * Zong Li - * Pragnesh Patel - */ - -#ifndef __SIFIVE_CLK_FU740_PRCI_H -#define __SIFIVE_CLK_FU740_PRCI_H - -#include "sifive-prci.h" - -#define NUM_CLOCK_FU740 9 - -extern struct __prci_clock __prci_init_clocks_fu740[NUM_CLOCK_FU740]; - -static const struct prci_clk_desc prci_clk_fu740 = { - .clks = __prci_init_clocks_fu740, - .num_clks = ARRAY_SIZE(__prci_init_clocks_fu740), -}; - -#endif /* __SIFIVE_CLK_FU740_PRCI_H */ diff --git a/drivers/clk/sifive/sifive-prci.c b/drivers/clk/sifive/sifive-prci.c index 5ea86062800..aa26d3a109b 100644 --- a/drivers/clk/sifive/sifive-prci.c +++ b/drivers/clk/sifive/sifive-prci.c @@ -33,8 +33,7 @@ #include <linux/math64.h> #include <dt-bindings/clock/sifive-fu740-prci.h> -#include "fu540-prci.h" -#include "fu740-prci.h" +#include "sifive-prci.h" /* * Private functions diff --git a/drivers/clk/sifive/sifive-prci.h b/drivers/clk/sifive/sifive-prci.h index 5ce33d61846..b391698081d 100644 --- a/drivers/clk/sifive/sifive-prci.h +++ b/drivers/clk/sifive/sifive-prci.h @@ -320,4 +320,8 @@ unsigned long sifive_prci_hfpclkplldiv_recalc_rate(struct __prci_clock *pc, int sifive_prci_clock_enable(struct __prci_clock *pc, bool enable); +/* Clock driver data */ +extern const struct prci_clk_desc prci_clk_fu540; +extern const struct prci_clk_desc prci_clk_fu740; + #endif /* __SIFIVE_CLK_SIFIVE_PRCI_H */ diff --git a/drivers/clk/sophgo/Kconfig b/drivers/clk/sophgo/Kconfig new file mode 100644 index 00000000000..59b51608fe6 --- /dev/null +++ b/drivers/clk/sophgo/Kconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com> + +config CLK_SOPHGO + bool + +config CLK_SOPHGO_CV1800B + bool "Sophgo CV1800B clock support" + depends on CLK + select CLK_CCF + select CLK_SOPHGO + help + This enables support clock driver for Sophgo CV1800B SoC. diff --git a/drivers/clk/sophgo/Makefile b/drivers/clk/sophgo/Makefile new file mode 100644 index 00000000000..caec76222be --- /dev/null +++ b/drivers/clk/sophgo/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com> + +obj-y += clk-ip.o clk-pll.o +obj-$(CONFIG_CLK_SOPHGO_CV1800B) += clk-cv1800b.o diff --git a/drivers/clk/sophgo/clk-common.h b/drivers/clk/sophgo/clk-common.h new file mode 100644 index 00000000000..95b82e968d0 --- /dev/null +++ b/drivers/clk/sophgo/clk-common.h @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com> + * + */ + +#ifndef __CLK_SOPHGO_COMMON_H__ +#define __CLK_SOPHGO_COMMON_H__ + +#include <linux/bitops.h> +#include <linux/io.h> + +#define CV1800B_CLK_OSC 1 +#define CV1800B_CLK_BYPASS 2 +#define CV1800B_CLK_ID_TRANSFORM(_id) ((_id) + 3) + +struct cv1800b_clk_regbit { + u32 offset; + u8 shift; +}; + +struct cv1800b_clk_regfield { + u32 offset; + u8 shift; + u8 width; +}; + +#define CV1800B_CLK_REGBIT(_offset, _shift) \ + { \ + .offset = _offset, \ + .shift = _shift, \ + } + +#define CV1800B_CLK_REGFIELD(_offset, _shift, _width) \ + { \ + .offset = _offset, \ + .shift = _shift, \ + .width = _width, \ + } + +static inline u32 cv1800b_clk_getbit(void *base, struct cv1800b_clk_regbit *bit) +{ + return readl(base + bit->offset) & (BIT(bit->shift)); +} + +static inline u32 cv1800b_clk_setbit(void *base, struct cv1800b_clk_regbit *bit) +{ + return setbits_le32(base + bit->offset, BIT(bit->shift)); +} + +static inline u32 cv1800b_clk_clrbit(void *base, struct cv1800b_clk_regbit *bit) +{ + return clrbits_le32(base + bit->offset, BIT(bit->shift)); +} + +static inline u32 cv1800b_clk_getfield(void *base, + struct cv1800b_clk_regfield *field) +{ + u32 mask = GENMASK(field->shift + field->width - 1, field->shift); + + return (readl(base + field->offset) & mask) >> field->shift; +} + +static inline void +cv1800b_clk_setfield(void *base, struct cv1800b_clk_regfield *field, u32 val) +{ + u32 mask = GENMASK(field->shift + field->width - 1, field->shift); + u32 new_val = (readl(base + field->offset) & ~mask) | + ((val << field->shift) & mask); + + return writel(new_val, base + field->offset); +} + +#endif /* __CLK_SOPHGO_COMMON_H__ */ diff --git a/drivers/clk/sophgo/clk-cv1800b.c b/drivers/clk/sophgo/clk-cv1800b.c new file mode 100644 index 00000000000..d946ea57a46 --- /dev/null +++ b/drivers/clk/sophgo/clk-cv1800b.c @@ -0,0 +1,754 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com> + */ + +#include <clk-uclass.h> +#include <dm.h> +#include <linux/clk-provider.h> + +#include "clk-common.h" +#include "clk-cv1800b.h" +#include "clk-ip.h" +#include "clk-pll.h" + +static const char *const clk_cam_parents[] = { + "clk_cam0pll", + "clk_cam0pll_d2", + "clk_cam0pll_d3", + "clk_mipimpll_d3" +}; + +static const char *const clk_tpu_parents[] = { + "clk_tpll", + "clk_a0pll", + "clk_mipimpll", + "clk_fpll" +}; + +static const char *const clk_axi4_parents[] = { "clk_fpll", "clk_disppll" }; +static const char *const clk_aud_parents[] = { "clk_a0pll", "clk_a24m" }; +static const char *const clk_cam0_200_parents[] = { "osc", "clk_disppll" }; + +static const char *const clk_vip_sys_parents[] = { + "clk_mipimpll", + "clk_cam0pll", + "clk_disppll", + "clk_fpll" +}; + +static const char *const clk_axi_video_codec_parents[] = { + "clk_a0pll", + "clk_mipimpll", + "clk_cam1pll", + "clk_fpll" +}; + +static const char *const clk_vc_src0_parents[] = { + "clk_disppll", + "clk_mipimpll", + "clk_cam1pll", + "clk_fpll" +}; + +static const struct cv1800b_mmux_parent_info clk_c906_0_parents[] = { + { "clk_tpll", 0, 0 }, + { "clk_a0pll", 0, 1 }, + { "clk_mipimpll", 0, 2 }, + { "clk_mpll", 0, 3 }, + { "clk_fpll", 1, 0 }, +}; + +static const struct cv1800b_mmux_parent_info clk_c906_1_parents[] = { + { "clk_tpll", 0, 0 }, + { "clk_a0pll", 0, 1 }, + { "clk_disppll", 0, 2 }, + { "clk_mpll", 0, 3 }, + { "clk_fpll", 1, 0 }, +}; + +static const struct cv1800b_mmux_parent_info clk_a53_parents[] = { + { "clk_tpll", 0, 0 }, + { "clk_a0pll", 0, 1 }, + { "clk_mipimpll", 0, 2 }, + { "clk_mpll", 0, 3 }, + { "clk_fpll", 1, 0 }, +}; + +static struct cv1800b_clk_gate cv1800b_gate_info[] = { + CV1800B_GATE(CLK_XTAL_AP, "clk_xtal_ap", "osc", REG_CLK_EN_0, 3, CLK_IS_CRITICAL), + CV1800B_GATE(CLK_RTC_25M, "clk_rtc_25m", "osc", REG_CLK_EN_0, 8, CLK_IS_CRITICAL), + CV1800B_GATE(CLK_TEMPSEN, "clk_tempsen", "osc", REG_CLK_EN_0, 9, 0), + CV1800B_GATE(CLK_SARADC, "clk_saradc", "osc", REG_CLK_EN_0, 10, 0), + CV1800B_GATE(CLK_EFUSE, "clk_efuse", "osc", REG_CLK_EN_0, 11, 0), + CV1800B_GATE(CLK_APB_EFUSE, "clk_apb_efuse", "osc", REG_CLK_EN_0, 12, 0), + CV1800B_GATE(CLK_DEBUG, "clk_debug", "osc", REG_CLK_EN_0, 13, CLK_IS_CRITICAL), + CV1800B_GATE(CLK_XTAL_MISC, "clk_xtal_misc", "osc", REG_CLK_EN_0, 14, CLK_IS_CRITICAL), + CV1800B_GATE(CLK_APB_WDT, "clk_apb_wdt", "osc", REG_CLK_EN_1, 7, CLK_IS_CRITICAL), + CV1800B_GATE(CLK_WGN, "clk_wgn", "osc", REG_CLK_EN_3, 22, 0), + CV1800B_GATE(CLK_WGN0, "clk_wgn0", "osc", REG_CLK_EN_3, 23, 0), + CV1800B_GATE(CLK_WGN1, "clk_wgn1", "osc", REG_CLK_EN_3, 24, 0), + CV1800B_GATE(CLK_WGN2, "clk_wgn2", "osc", REG_CLK_EN_3, 25, 0), + CV1800B_GATE(CLK_KEYSCAN, "clk_keyscan", "osc", REG_CLK_EN_3, 26, 0), + CV1800B_GATE(CLK_TPU_FAB, "clk_tpu_fab", "clk_mipimpll", REG_CLK_EN_0, 5, 0), + CV1800B_GATE(CLK_AHB_ROM, "clk_ahb_rom", "clk_axi4", REG_CLK_EN_0, 6, 0), + CV1800B_GATE(CLK_AXI4_EMMC, "clk_axi4_emmc", "clk_axi4", REG_CLK_EN_0, 15, 0), + CV1800B_GATE(CLK_AXI4_SD0, "clk_axi4_sd0", "clk_axi4", REG_CLK_EN_0, 18, 0), + CV1800B_GATE(CLK_AXI4_SD1, "clk_axi4_sd1", "clk_axi4", REG_CLK_EN_0, 21, 0), + CV1800B_GATE(CLK_AXI4_ETH0, "clk_axi4_eth0", "clk_axi4", REG_CLK_EN_0, 26, 0), + CV1800B_GATE(CLK_AXI4_ETH1, "clk_axi4_eth1", "clk_axi4", REG_CLK_EN_0, 28, 0), + CV1800B_GATE(CLK_AHB_SF, "clk_ahb_sf", "clk_axi4", REG_CLK_EN_1, 0, 0), + CV1800B_GATE(CLK_SDMA_AXI, "clk_sdma_axi", "clk_axi4", REG_CLK_EN_1, 1, 0), + CV1800B_GATE(CLK_APB_I2C, "clk_apb_i2c", "clk_axi4", REG_CLK_EN_1, 6, 0), + CV1800B_GATE(CLK_APB_SPI0, "clk_apb_spi0", "clk_axi4", REG_CLK_EN_1, 9, 0), + CV1800B_GATE(CLK_APB_SPI1, "clk_apb_spi1", "clk_axi4", REG_CLK_EN_1, 10, 0), + CV1800B_GATE(CLK_APB_SPI2, "clk_apb_spi2", "clk_axi4", REG_CLK_EN_1, 11, 0), + CV1800B_GATE(CLK_APB_SPI3, "clk_apb_spi3", "clk_axi4", REG_CLK_EN_1, 12, 0), + CV1800B_GATE(CLK_APB_UART0, "clk_apb_uart0", "clk_axi4", REG_CLK_EN_1, 15, CLK_IS_CRITICAL), + CV1800B_GATE(CLK_APB_UART1, "clk_apb_uart1", "clk_axi4", REG_CLK_EN_1, 17, 0), + CV1800B_GATE(CLK_APB_UART2, "clk_apb_uart2", "clk_axi4", REG_CLK_EN_1, 19, 0), + CV1800B_GATE(CLK_APB_UART3, "clk_apb_uart3", "clk_axi4", REG_CLK_EN_1, 21, 0), + CV1800B_GATE(CLK_APB_UART4, "clk_apb_uart4", "clk_axi4", REG_CLK_EN_1, 23, 0), + CV1800B_GATE(CLK_APB_I2S0, "clk_apb_i2s0", "clk_axi4", REG_CLK_EN_1, 24, 0), + CV1800B_GATE(CLK_APB_I2S1, "clk_apb_i2s1", "clk_axi4", REG_CLK_EN_1, 25, 0), + CV1800B_GATE(CLK_APB_I2S2, "clk_apb_i2s2", "clk_axi4", REG_CLK_EN_1, 26, 0), + CV1800B_GATE(CLK_APB_I2S3, "clk_apb_i2s3", "clk_axi4", REG_CLK_EN_1, 27, 0), + CV1800B_GATE(CLK_AXI4_USB, "clk_axi4_usb", "clk_axi4", REG_CLK_EN_1, 28, 0), + CV1800B_GATE(CLK_APB_USB, "clk_apb_usb", "clk_axi4", REG_CLK_EN_1, 29, 0), + CV1800B_GATE(CLK_APB_I2C0, "clk_apb_i2c0", "clk_axi4", REG_CLK_EN_3, 17, 0), + CV1800B_GATE(CLK_APB_I2C1, "clk_apb_i2c1", "clk_axi4", REG_CLK_EN_3, 18, 0), + CV1800B_GATE(CLK_APB_I2C2, "clk_apb_i2c2", "clk_axi4", REG_CLK_EN_3, 19, 0), + CV1800B_GATE(CLK_APB_I2C3, "clk_apb_i2c3", "clk_axi4", REG_CLK_EN_3, 20, 0), + CV1800B_GATE(CLK_APB_I2C4, "clk_apb_i2c4", "clk_axi4", REG_CLK_EN_3, 21, 0), + CV1800B_GATE(CLK_AHB_SF1, "clk_ahb_sf1", "clk_axi4", REG_CLK_EN_3, 27, 0), + CV1800B_GATE(CLK_APB_AUDSRC, "clk_apb_audsrc", "clk_axi4", REG_CLK_EN_4, 2, 0), + CV1800B_GATE(CLK_DDR_AXI_REG, "clk_ddr_axi_reg", "clk_axi6", REG_CLK_EN_0, 7, + CLK_IS_CRITICAL), + CV1800B_GATE(CLK_APB_GPIO, "clk_apb_gpio", "clk_axi6", REG_CLK_EN_0, 29, CLK_IS_CRITICAL), + CV1800B_GATE(CLK_APB_GPIO_INTR, "clk_apb_gpio_intr", "clk_axi6", REG_CLK_EN_0, 30, + CLK_IS_CRITICAL), + CV1800B_GATE(CLK_APB_JPEG, "clk_apb_jpeg", "clk_axi6", REG_CLK_EN_2, 13, CLK_IGNORE_UNUSED), + CV1800B_GATE(CLK_APB_H264C, "clk_apb_h264c", "clk_axi6", REG_CLK_EN_2, 14, 0), + CV1800B_GATE(CLK_APB_H265C, "clk_apb_h265c", "clk_axi6", REG_CLK_EN_2, 15, 0), + CV1800B_GATE(CLK_PM, "clk_pm", "clk_axi6", REG_CLK_EN_3, 8, CLK_IS_CRITICAL), + CV1800B_GATE(CLK_CFG_REG_VIP, "clk_cfg_reg_vip", "clk_axi6", REG_CLK_EN_3, 31, 0), + CV1800B_GATE(CLK_CFG_REG_VC, "clk_cfg_reg_vc", "clk_axi6", REG_CLK_EN_4, 0, + CLK_IGNORE_UNUSED), + CV1800B_GATE(CLK_PWM, "clk_pwm", "clk_pwm_src", REG_CLK_EN_1, 8, CLK_IS_CRITICAL), + CV1800B_GATE(CLK_UART0, "clk_uart0", "clk_cam0_200", REG_CLK_EN_1, 14, CLK_IS_CRITICAL), + CV1800B_GATE(CLK_UART1, "clk_uart1", "clk_cam0_200", REG_CLK_EN_1, 16, 0), + CV1800B_GATE(CLK_UART2, "clk_uart2", "clk_cam0_200", REG_CLK_EN_1, 18, 0), + CV1800B_GATE(CLK_UART3, "clk_uart3", "clk_cam0_200", REG_CLK_EN_1, 20, 0), + CV1800B_GATE(CLK_UART4, "clk_uart4", "clk_cam0_200", REG_CLK_EN_1, 22, 0), + CV1800B_GATE(CLK_H264C, "clk_h264c", "clk_axi_video_codec", REG_CLK_EN_2, 10, 0), + CV1800B_GATE(CLK_H265C, "clk_h265c", "clk_axi_video_codec", REG_CLK_EN_2, 11, 0), + CV1800B_GATE(CLK_JPEG, "clk_jpeg", "clk_axi_video_codec", REG_CLK_EN_2, 12, + CLK_IGNORE_UNUSED), + CV1800B_GATE(CLK_CSI_MAC0_VIP, "clk_csi_mac0_vip", "clk_axi_vip", REG_CLK_EN_2, 18, 0), + CV1800B_GATE(CLK_CSI_MAC1_VIP, "clk_csi_mac1_vip", "clk_axi_vip", REG_CLK_EN_2, 19, 0), + CV1800B_GATE(CLK_ISP_TOP_VIP, "clk_isp_top_vip", "clk_axi_vip", REG_CLK_EN_2, 20, 0), + CV1800B_GATE(CLK_IMG_D_VIP, "clk_img_d_vip", "clk_axi_vip", REG_CLK_EN_2, 21, 0), + CV1800B_GATE(CLK_IMG_V_VIP, "clk_img_v_vip", "clk_axi_vip", REG_CLK_EN_2, 22, 0), + CV1800B_GATE(CLK_SC_TOP_VIP, "clk_sc_top_vip", "clk_axi_vip", REG_CLK_EN_2, 23, 0), + CV1800B_GATE(CLK_SC_D_VIP, "clk_sc_d_vip", "clk_axi_vip", REG_CLK_EN_2, 24, 0), + CV1800B_GATE(CLK_SC_V1_VIP, "clk_sc_v1_vip", "clk_axi_vip", REG_CLK_EN_2, 25, 0), + CV1800B_GATE(CLK_SC_V2_VIP, "clk_sc_v2_vip", "clk_axi_vip", REG_CLK_EN_2, 26, 0), + CV1800B_GATE(CLK_SC_V3_VIP, "clk_sc_v3_vip", "clk_axi_vip", REG_CLK_EN_2, 27, 0), + CV1800B_GATE(CLK_DWA_VIP, "clk_dwa_vip", "clk_axi_vip", REG_CLK_EN_2, 28, 0), + CV1800B_GATE(CLK_BT_VIP, "clk_bt_vip", "clk_axi_vip", REG_CLK_EN_2, 29, 0), + CV1800B_GATE(CLK_DISP_VIP, "clk_disp_vip", "clk_axi_vip", REG_CLK_EN_2, 30, 0), + CV1800B_GATE(CLK_DSI_MAC_VIP, "clk_dsi_mac_vip", "clk_axi_vip", REG_CLK_EN_2, 31, 0), + CV1800B_GATE(CLK_LVDS0_VIP, "clk_lvds0_vip", "clk_axi_vip", REG_CLK_EN_3, 0, 0), + CV1800B_GATE(CLK_LVDS1_VIP, "clk_lvds1_vip", "clk_axi_vip", REG_CLK_EN_3, 1, 0), + CV1800B_GATE(CLK_CSI0_RX_VIP, "clk_csi0_rx_vip", "clk_axi_vip", REG_CLK_EN_3, 2, 0), + CV1800B_GATE(CLK_CSI1_RX_VIP, "clk_csi1_rx_vip", "clk_axi_vip", REG_CLK_EN_3, 3, 0), + CV1800B_GATE(CLK_PAD_VI_VIP, "clk_pad_vi_vip", "clk_axi_vip", REG_CLK_EN_3, 4, 0), + CV1800B_GATE(CLK_PAD_VI1_VIP, "clk_pad_vi1_vip", "clk_axi_vip", REG_CLK_EN_3, 30, 0), + CV1800B_GATE(CLK_PAD_VI2_VIP, "clk_pad_vi2_vip", "clk_axi_vip", REG_CLK_EN_4, 7, 0), + CV1800B_GATE(CLK_CSI_BE_VIP, "clk_csi_be_vip", "clk_axi_vip", REG_CLK_EN_4, 8, 0), + CV1800B_GATE(CLK_VIP_IP0, "clk_vip_ip0", "clk_axi_vip", REG_CLK_EN_4, 9, 0), + CV1800B_GATE(CLK_VIP_IP1, "clk_vip_ip1", "clk_axi_vip", REG_CLK_EN_4, 10, 0), + CV1800B_GATE(CLK_VIP_IP2, "clk_vip_ip2", "clk_axi_vip", REG_CLK_EN_4, 11, 0), + CV1800B_GATE(CLK_VIP_IP3, "clk_vip_ip3", "clk_axi_vip", REG_CLK_EN_4, 12, 0), + CV1800B_GATE(CLK_IVE_VIP, "clk_ive_vip", "clk_axi_vip", REG_CLK_EN_4, 17, 0), + CV1800B_GATE(CLK_RAW_VIP, "clk_raw_vip", "clk_axi_vip", REG_CLK_EN_4, 18, 0), + CV1800B_GATE(CLK_OSDC_VIP, "clk_osdc_vip", "clk_axi_vip", REG_CLK_EN_4, 19, 0), + CV1800B_GATE(CLK_CSI_MAC2_VIP, "clk_csi_mac2_vip", "clk_axi_vip", REG_CLK_EN_4, 20, 0), + CV1800B_GATE(CLK_CAM0_VIP, "clk_cam0_vip", "clk_axi_vip", REG_CLK_EN_4, 21, 0), + CV1800B_GATE(CLK_TIMER0, "clk_timer0", "clk_xtal_misc", REG_CLK_EN_3, 9, CLK_IS_CRITICAL), + CV1800B_GATE(CLK_TIMER1, "clk_timer1", "clk_xtal_misc", REG_CLK_EN_3, 10, CLK_IS_CRITICAL), + CV1800B_GATE(CLK_TIMER2, "clk_timer2", "clk_xtal_misc", REG_CLK_EN_3, 11, CLK_IS_CRITICAL), + CV1800B_GATE(CLK_TIMER3, "clk_timer3", "clk_xtal_misc", REG_CLK_EN_3, 12, CLK_IS_CRITICAL), + CV1800B_GATE(CLK_TIMER4, "clk_timer4", "clk_xtal_misc", REG_CLK_EN_3, 13, CLK_IS_CRITICAL), + CV1800B_GATE(CLK_TIMER5, "clk_timer5", "clk_xtal_misc", REG_CLK_EN_3, 14, CLK_IS_CRITICAL), + CV1800B_GATE(CLK_TIMER6, "clk_timer6", "clk_xtal_misc", REG_CLK_EN_3, 15, CLK_IS_CRITICAL), + CV1800B_GATE(CLK_TIMER7, "clk_timer7", "clk_xtal_misc", REG_CLK_EN_3, 16, CLK_IS_CRITICAL), +}; + +struct cv1800b_clk_div cv1800b_div_info[] = { + CV1800B_DIV(CLK_1M, "clk_1m", "osc", REG_CLK_EN_3, 5, + REG_DIV_CLK_1M, 16, 6, 25, CLK_IS_CRITICAL), + CV1800B_DIV(CLK_EMMC_100K, "clk_emmc_100k", "clk_1m", REG_CLK_EN_0, 17, + REG_DIV_CLK_EMMC_100K, 16, 8, 10, 0), + CV1800B_DIV(CLK_SD0_100K, "clk_sd0_100k", "clk_1m", REG_CLK_EN_0, 20, + REG_DIV_CLK_SD0_100K, 16, 8, 10, 0), + CV1800B_DIV(CLK_SD1_100K, "clk_sd1_100k", "clk_1m", REG_CLK_EN_0, 23, + REG_DIV_CLK_SD1_100K, 16, 8, 10, 0), + CV1800B_DIV(CLK_GPIO_DB, "clk_gpio_db", "clk_1m", REG_CLK_EN_0, 31, + REG_DIV_CLK_GPIO_DB, 16, 16, 10, CLK_IS_CRITICAL) +}; + +struct cv1800b_clk_bypass_div cv1800b_bypass_div_info[] = { + CV1800B_BYPASS_DIV(CLK_AP_DEBUG, "clk_ap_debug", "clk_fpll", REG_CLK_EN_4, 5, + REG_DIV_CLK_AP_DEBUG, 16, 4, 5, REG_CLK_BYP_1, 4, CLK_IS_CRITICAL), + CV1800B_BYPASS_DIV(CLK_SRC_RTC_SYS_0, "clk_src_rtc_sys_0", "clk_fpll", REG_CLK_EN_4, 6, + REG_DIV_CLK_RTCSYS_SRC_0, 16, 4, 5, REG_CLK_BYP_1, 5, CLK_IS_CRITICAL), + CV1800B_BYPASS_DIV(CLK_CPU_GIC, "clk_cpu_gic", "clk_fpll", REG_CLK_EN_0, 2, + REG_DIV_CLK_CPU_GIC, 16, 4, 5, REG_CLK_BYP_0, 2, CLK_IS_CRITICAL), + CV1800B_BYPASS_DIV(CLK_ETH0_500M, "clk_eth0_500m", "clk_fpll", REG_CLK_EN_0, 25, + REG_DIV_CLK_GPIO_DB, 16, 4, 3, REG_CLK_BYP_0, 9, 0), + CV1800B_BYPASS_DIV(CLK_ETH1_500M, "clk_eth1_500m", "clk_fpll", REG_CLK_EN_0, 27, + REG_DIV_CLK_GPIO_DB, 16, 4, 3, REG_CLK_BYP_0, 10, 0), + CV1800B_BYPASS_DIV(CLK_AXI6, "clk_axi6", "clk_fpll", REG_CLK_EN_2, 2, REG_DIV_CLK_AXI6, 16, + 4, 15, REG_CLK_BYP_0, 20, CLK_IS_CRITICAL), + CV1800B_BYPASS_DIV(CLK_SPI, "clk_spi", "clk_fpll", REG_CLK_EN_3, 6, REG_DIV_CLK_SPI, 16, 6, + 8, REG_CLK_BYP_0, 30, 0), + CV1800B_BYPASS_DIV(CLK_DISP_SRC_VIP, "clk_disp_src_vip", "clk_disppll", REG_CLK_EN_2, 7, + REG_DIV_CLK_DISP_SRC_VIP, 16, 4, 8, REG_CLK_BYP_0, 25, 0), + CV1800B_BYPASS_DIV(CLK_CPU_AXI0, "clk_cpu_axi0", "clk_axi4", REG_CLK_EN_0, 1, + REG_DIV_CLK_CPU_AXI0, 16, 4, 3, REG_CLK_BYP_0, 1, CLK_IS_CRITICAL), + CV1800B_BYPASS_DIV(CLK_DSI_ESC, "clk_dsi_esc", "clk_axi6", REG_CLK_EN_2, 3, + REG_DIV_CLK_DSI_ESC, 16, 4, 5, REG_CLK_BYP_0, 21, 0), + CV1800B_BYPASS_DIV(CLK_I2C, "clk_i2c", "clk_axi6", REG_CLK_EN_3, 7, REG_DIV_CLK_I2C, 16, 4, + 1, REG_CLK_BYP_0, 31, 0), +}; + +struct cv1800b_clk_fixed_div cv1800b_fixed_div_info[] = { + CV1800B_FIXED_DIV(CLK_CAM0PLL_D2, "clk_cam0pll_d2", "clk_cam0pll", + REG_CAM0PLL_CLK_CSR, 1, 2, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), + CV1800B_FIXED_DIV(CLK_CAM0PLL_D3, "clk_cam0pll_d3", "clk_cam0pll", + REG_CAM0PLL_CLK_CSR, 2, 3, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), + CV1800B_FIXED_DIV(CLK_MIPIMPLL_D3, "clk_mipimpll_d3", "clk_mipimpll", + REG_MIPIMPLL_CLK_CSR, 2, 3, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), + CV1800B_FIXED_DIV(CLK_USB_33K, "clk_usb_33k", "clk_1m", + REG_CLK_EN_1, 31, 3, + 0), +}; + +struct cv1800b_clk_bypass_fixed_div cv1800b_bypass_fixed_div_info[] = { + CV1800B_BYPASS_FIXED_DIV(CLK_USB_125M, "clk_usb_125m", "clk_fpll", + REG_CLK_EN_1, 30, 12, + REG_CLK_BYP_0, 17, + CLK_SET_RATE_PARENT), + CV1800B_BYPASS_FIXED_DIV(CLK_USB_12M, "clk_usb_12m", "clk_fpll", + REG_CLK_EN_2, 0, 125, + REG_CLK_BYP_0, 18, + CLK_SET_RATE_PARENT), + CV1800B_BYPASS_FIXED_DIV(CLK_VC_SRC1, "clk_vc_src1", "clk_fpll", + REG_CLK_EN_3, 28, 2, + REG_CLK_BYP_1, 0, + CLK_SET_RATE_PARENT), + CV1800B_BYPASS_FIXED_DIV(CLK_VC_SRC2, "clk_vc_src2", "clk_fpll", + REG_CLK_EN_4, 3, 3, + REG_CLK_BYP_1, 3, + CLK_SET_RATE_PARENT), +}; + +struct cv1800b_clk_mux cv1800b_mux_info[] = { + CV1800B_MUX(CLK_CAM0, "clk_cam0", clk_cam_parents, + REG_CLK_EN_2, 16, + REG_CLK_CAM0_SRC_DIV, 16, 6, 0, + REG_CLK_CAM0_SRC_DIV, 8, 2, + CLK_IGNORE_UNUSED), + CV1800B_MUX(CLK_CAM1, "clk_cam1", clk_cam_parents, + REG_CLK_EN_2, 17, + REG_CLK_CAM1_SRC_DIV, 16, 6, 0, + REG_CLK_CAM1_SRC_DIV, 8, 2, + CLK_IGNORE_UNUSED), +}; + +struct cv1800b_clk_bypass_mux cv1800b_bypass_mux_info[] = { + CV1800B_BYPASS_MUX(CLK_TPU, "clk_tpu", clk_tpu_parents, + REG_CLK_EN_0, 4, + REG_DIV_CLK_TPU, 16, 4, 3, + REG_DIV_CLK_TPU, 8, 2, + REG_CLK_BYP_0, 3, + 0), + CV1800B_BYPASS_MUX(CLK_EMMC, "clk_emmc", clk_axi4_parents, + REG_CLK_EN_0, 16, + REG_DIV_CLK_EMMC, 16, 5, 15, + REG_DIV_CLK_EMMC, 8, 2, + REG_CLK_BYP_0, 5, + 0), + CV1800B_BYPASS_MUX(CLK_SD0, "clk_sd0", clk_axi4_parents, + REG_CLK_EN_0, 19, + REG_DIV_CLK_SD0, 16, 5, 15, + REG_DIV_CLK_SD0, 8, 2, + REG_CLK_BYP_0, 6, + 0), + CV1800B_BYPASS_MUX(CLK_SD1, "clk_sd1", clk_axi4_parents, + REG_CLK_EN_0, 22, + REG_DIV_CLK_SD1, 16, 5, 15, + REG_DIV_CLK_SD1, 8, 2, + REG_CLK_BYP_0, 7, + 0), + CV1800B_BYPASS_MUX(CLK_SPI_NAND, "clk_spi_nand", clk_axi4_parents, + REG_CLK_EN_0, 24, + REG_DIV_CLK_SPI_NAND, 16, 5, 8, + REG_DIV_CLK_SPI_NAND, 8, 2, + REG_CLK_BYP_0, 8, + 0), + CV1800B_BYPASS_MUX(CLK_AXI4, "clk_axi4", clk_axi4_parents, + REG_CLK_EN_2, 1, + REG_DIV_CLK_AXI4, 16, 4, 5, + REG_DIV_CLK_AXI4, 8, 2, + REG_CLK_BYP_0, 19, + CLK_IS_CRITICAL), + CV1800B_BYPASS_MUX(CLK_PWM_SRC, "clk_pwm_src", clk_axi4_parents, + REG_CLK_EN_4, 4, + REG_DIV_CLK_PWM_SRC_0, 16, 6, 10, + REG_DIV_CLK_PWM_SRC_0, 8, 2, + REG_CLK_BYP_0, 15, + CLK_IS_CRITICAL), + CV1800B_BYPASS_MUX(CLK_AUDSRC, "clk_audsrc", clk_aud_parents, + REG_CLK_EN_4, 1, + REG_DIV_CLK_AUDSRC, 16, 8, 18, + REG_DIV_CLK_AUDSRC, 8, 2, + REG_CLK_BYP_1, 2, + 0), + CV1800B_BYPASS_MUX(CLK_SDMA_AUD0, "clk_sdma_aud0", clk_aud_parents, + REG_CLK_EN_1, 2, + REG_DIV_CLK_SDMA_AUD0, 16, 8, 18, + REG_DIV_CLK_SDMA_AUD0, 8, 2, + REG_CLK_BYP_0, 11, + 0), + CV1800B_BYPASS_MUX(CLK_SDMA_AUD1, "clk_sdma_aud1", clk_aud_parents, + REG_CLK_EN_1, 3, + REG_DIV_CLK_SDMA_AUD1, 16, 8, 18, + REG_DIV_CLK_SDMA_AUD1, 8, 2, + REG_CLK_BYP_0, 12, + 0), + CV1800B_BYPASS_MUX(CLK_SDMA_AUD2, "clk_sdma_aud2", clk_aud_parents, + REG_CLK_EN_1, 3, + REG_DIV_CLK_SDMA_AUD2, 16, 8, 18, + REG_DIV_CLK_SDMA_AUD2, 8, 2, + REG_CLK_BYP_0, 13, + 0), + CV1800B_BYPASS_MUX(CLK_SDMA_AUD3, "clk_sdma_aud3", clk_aud_parents, + REG_CLK_EN_1, 3, + REG_DIV_CLK_SDMA_AUD3, 16, 8, 18, + REG_DIV_CLK_SDMA_AUD3, 8, 2, + REG_CLK_BYP_0, 14, + 0), + CV1800B_BYPASS_MUX(CLK_CAM0_200, "clk_cam0_200", clk_cam0_200_parents, + REG_CLK_EN_1, 13, + REG_DIV_CLK_CAM0_200, 16, 4, 1, + REG_DIV_CLK_CAM0_200, 8, 2, + REG_CLK_BYP_0, 16, + CLK_IS_CRITICAL), + CV1800B_BYPASS_MUX(CLK_AXI_VIP, "clk_axi_vip", clk_vip_sys_parents, + REG_CLK_EN_2, 4, + REG_DIV_CLK_AXI_VIP, 16, 4, 3, + REG_DIV_CLK_AXI_VIP, 8, 2, + REG_CLK_BYP_0, 22, + 0), + CV1800B_BYPASS_MUX(CLK_SRC_VIP_SYS_0, "clk_src_vip_sys_0", clk_vip_sys_parents, + REG_CLK_EN_2, 5, + REG_DIV_CLK_SRC_VIP_SYS_0, 16, 4, 6, + REG_DIV_CLK_SRC_VIP_SYS_0, 8, 2, + REG_CLK_BYP_0, 23, + 0), + CV1800B_BYPASS_MUX(CLK_SRC_VIP_SYS_1, "clk_src_vip_sys_1", clk_vip_sys_parents, + REG_CLK_EN_2, 6, + REG_DIV_CLK_SRC_VIP_SYS_1, 16, 4, 6, + REG_DIV_CLK_SRC_VIP_SYS_1, 8, 2, + REG_CLK_BYP_0, 24, + 0), + CV1800B_BYPASS_MUX(CLK_SRC_VIP_SYS_2, "clk_src_vip_sys_2", clk_vip_sys_parents, + REG_CLK_EN_3, 29, + REG_DIV_CLK_SRC_VIP_SYS_2, 16, 4, 2, + REG_DIV_CLK_SRC_VIP_SYS_2, 8, 2, + REG_CLK_BYP_1, 1, + 0), + CV1800B_BYPASS_MUX(CLK_SRC_VIP_SYS_3, "clk_src_vip_sys_3", clk_vip_sys_parents, + REG_CLK_EN_4, 15, + REG_DIV_CLK_SRC_VIP_SYS_3, 16, 4, 2, + REG_DIV_CLK_SRC_VIP_SYS_3, 8, 2, + REG_CLK_BYP_1, 8, + 0), + CV1800B_BYPASS_MUX(CLK_SRC_VIP_SYS_4, "clk_src_vip_sys_4", clk_vip_sys_parents, + REG_CLK_EN_4, 16, + REG_DIV_CLK_SRC_VIP_SYS_4, 16, 4, 3, + REG_DIV_CLK_SRC_VIP_SYS_4, 8, 2, + REG_CLK_BYP_1, 9, + 0), + CV1800B_BYPASS_MUX(CLK_AXI_VIDEO_CODEC, "clk_axi_video_codec", clk_axi_video_codec_parents, + REG_CLK_EN_2, 8, + REG_DIV_CLK_AXI_VIDEO_CODEC, 16, 4, 2, + REG_DIV_CLK_AXI_VIDEO_CODEC, 8, 2, + REG_CLK_BYP_0, 26, + 0), + CV1800B_BYPASS_MUX(CLK_VC_SRC0, "clk_vc_src0", clk_vc_src0_parents, + REG_CLK_EN_2, 9, + REG_DIV_CLK_VC_SRC0, 16, 4, 2, + REG_DIV_CLK_VC_SRC0, 8, 2, + REG_CLK_BYP_0, 27, + 0), +}; + +struct cv1800b_clk_mmux cv1800b_mmux_info[] = { + CV1800B_MMUX(CLK_C906_0, "clk_c906_0", clk_c906_0_parents, + REG_CLK_EN_4, 13, + REG_DIV_CLK_C906_0_0, 16, 4, 1, + REG_DIV_CLK_C906_0_1, 16, 4, 2, + REG_DIV_CLK_C906_0_0, 8, 2, + REG_DIV_CLK_C906_0_1, 8, 2, + REG_CLK_BYP_1, 6, + REG_CLK_SEL_0, 23, + CLK_IS_CRITICAL | CLK_GET_RATE_NOCACHE), + CV1800B_MMUX(CLK_C906_1, "clk_c906_1", clk_c906_1_parents, + REG_CLK_EN_4, 14, + REG_DIV_CLK_C906_1_0, 16, 4, 2, + REG_DIV_CLK_C906_1_1, 16, 4, 3, + REG_DIV_CLK_C906_1_0, 8, 2, + REG_DIV_CLK_C906_1_1, 8, 2, + REG_CLK_BYP_1, 7, + REG_CLK_SEL_0, 24, + CLK_IS_CRITICAL | CLK_GET_RATE_NOCACHE), + CV1800B_MMUX(CLK_A53, "clk_a53", clk_a53_parents, + REG_CLK_EN_0, 0, + REG_DIV_CLK_A53_0, 16, 4, 1, + REG_DIV_CLK_A53_1, 16, 4, 2, + REG_DIV_CLK_A53_0, 8, 2, + REG_DIV_CLK_A53_1, 8, 2, + REG_CLK_BYP_0, 0, + REG_CLK_SEL_0, 0, + CLK_IS_CRITICAL | CLK_GET_RATE_NOCACHE), +}; + +static struct cv1800b_clk_audio cv1800b_audio_info[] = { + CV1800B_AUDIO(CLK_A24M, "clk_a24m", "clk_mipimpll", + REG_APLL_FRAC_DIV_CTRL, 0, + REG_APLL_FRAC_DIV_CTRL, 3, + REG_APLL_FRAC_DIV_CTRL, 1, + REG_APLL_FRAC_DIV_CTRL, 2, + REG_APLL_FRAC_DIV_M, 0, 22, + REG_APLL_FRAC_DIV_N, 0, 22, + 0), +}; + +static struct cv1800b_clk_ipll cv1800b_ipll_info[] = { + CV1800B_IPLL(CLK_FPLL, "clk_fpll", "osc", REG_FPLL_CSR, + REG_PLL_G6_CTRL, 8, + REG_PLL_G6_STATUS, 2, + CLK_IS_CRITICAL), + CV1800B_IPLL(CLK_MIPIMPLL, "clk_mipimpll", "osc", REG_MIPIMPLL_CSR, + REG_PLL_G2_CTRL, 0, + REG_PLL_G2_STATUS, 0, + CLK_IS_CRITICAL), +}; + +static struct cv1800b_clk_fpll cv1800b_fpll_info[] = { + CV1800B_FPLL(CLK_MPLL, "clk_mpll", "osc", REG_MPLL_CSR, + REG_PLL_G6_CTRL, 0, + REG_PLL_G6_STATUS, 0, + REG_PLL_G6_SSC_SYN_CTRL, 2, + REG_PLL_G6_SSC_SYN_CTRL, 0, + REG_MPLL_SSC_SYN_CTRL, REG_MPLL_SSC_SYN_SET, + CLK_IS_CRITICAL), + CV1800B_FPLL(CLK_TPLL, "clk_tpll", "osc", REG_TPLL_CSR, + REG_PLL_G6_CTRL, 4, + REG_PLL_G6_STATUS, 1, + REG_PLL_G6_SSC_SYN_CTRL, 3, + REG_PLL_G6_SSC_SYN_CTRL, 0, + REG_TPLL_SSC_SYN_CTRL, REG_TPLL_SSC_SYN_SET, + CLK_IS_CRITICAL), + CV1800B_FPLL(CLK_A0PLL, "clk_a0pll", "clk_mipimpll", REG_A0PLL_CSR, + REG_PLL_G2_CTRL, 4, + REG_PLL_G2_STATUS, 1, + REG_PLL_G2_SSC_SYN_CTRL, 2, + REG_PLL_G2_SSC_SYN_CTRL, 0, + REG_A0PLL_SSC_SYN_CTRL, REG_A0PLL_SSC_SYN_SET, + CLK_IS_CRITICAL), + CV1800B_FPLL(CLK_DISPPLL, "clk_disppll", "clk_mipimpll", REG_DISPPLL_CSR, + REG_PLL_G2_CTRL, 8, + REG_PLL_G2_STATUS, 2, + REG_PLL_G2_SSC_SYN_CTRL, 3, + REG_PLL_G2_SSC_SYN_CTRL, 0, + REG_DISPPLL_SSC_SYN_CTRL, REG_DISPPLL_SSC_SYN_SET, + CLK_IS_CRITICAL), + CV1800B_FPLL(CLK_CAM0PLL, "clk_cam0pll", "clk_mipimpll", REG_CAM0PLL_CSR, + REG_PLL_G2_CTRL, 12, + REG_PLL_G2_STATUS, 3, + REG_PLL_G2_SSC_SYN_CTRL, 4, + REG_PLL_G2_SSC_SYN_CTRL, 0, + REG_CAM0PLL_SSC_SYN_CTRL, REG_CAM0PLL_SSC_SYN_SET, + CLK_IGNORE_UNUSED), + CV1800B_FPLL(CLK_CAM1PLL, "clk_cam1pll", "clk_mipimpll", REG_CAM1PLL_CSR, + REG_PLL_G2_CTRL, 16, + REG_PLL_G2_STATUS, 4, + REG_PLL_G2_SSC_SYN_CTRL, 5, + REG_PLL_G2_SSC_SYN_CTRL, 0, + REG_CAM1PLL_SSC_SYN_CTRL, REG_CAM1PLL_SSC_SYN_SET, + CLK_IS_CRITICAL), +}; + +static int cv1800b_register_clk(struct udevice *dev) +{ + struct clk osc; + ulong osc_rate; + void *base = devfdt_get_addr_ptr(dev); + int i, ret; + + ret = clk_get_by_index(dev, 0, &osc); + if (ret) { + pr_err("Failed to get clock\n"); + return ret; + } + + osc_rate = clk_get_rate(&osc); + clk_dm(CV1800B_CLK_OSC, clk_register_fixed_rate(NULL, "osc", osc_rate)); + clk_dm(CV1800B_CLK_BYPASS, clk_register_fixed_rate(NULL, "bypass", osc_rate)); + + for (i = 0; i < ARRAY_SIZE(cv1800b_ipll_info); i++) { + struct cv1800b_clk_ipll *ipll = &cv1800b_ipll_info[i]; + + ipll->base = base; + ret = clk_register(&ipll->clk, "cv1800b_clk_ipll", ipll->name, + ipll->parent_name); + if (ret) { + pr_err("Failed to register ipll %s\n", ipll->name); + return ret; + } + } + + for (i = 0; i < ARRAY_SIZE(cv1800b_fpll_info); i++) { + struct cv1800b_clk_fpll *fpll = &cv1800b_fpll_info[i]; + + fpll->ipll.base = base; + ret = clk_register(&fpll->ipll.clk, "cv1800b_clk_fpll", + fpll->ipll.name, fpll->ipll.parent_name); + if (ret) { + pr_err("Failed to register fpll %s\n", fpll->ipll.name); + return ret; + } + } + + for (i = 0; i < ARRAY_SIZE(cv1800b_div_info); i++) { + struct cv1800b_clk_div *div = &cv1800b_div_info[i]; + + div->base = base; + ret = clk_register(&div->clk, "cv1800b_clk_div", div->name, + div->parent_name); + if (ret) { + pr_err("Failed to register div %s\n", div->name); + return ret; + } + } + + for (i = 0; i < ARRAY_SIZE(cv1800b_fixed_div_info); i++) { + struct cv1800b_clk_fixed_div *fixed_div = + &cv1800b_fixed_div_info[i]; + + fixed_div->base = base; + ret = clk_register(&fixed_div->clk, "cv1800b_clk_fixed_div", + fixed_div->name, fixed_div->parent_name); + if (ret) { + pr_err("Failed to register fixed div %s\n", + fixed_div->name); + return ret; + } + } + + for (i = 0; i < ARRAY_SIZE(cv1800b_bypass_fixed_div_info); i++) { + struct cv1800b_clk_bypass_fixed_div *bypass_fixed_div = + &cv1800b_bypass_fixed_div_info[i]; + + bypass_fixed_div->div.base = base; + ret = clk_register(&bypass_fixed_div->div.clk, + "cv1800b_clk_bypass_fixed_div", + bypass_fixed_div->div.name, + bypass_fixed_div->div.parent_name); + if (ret) { + pr_err("Failed to register bypass fixed div %s\n", + bypass_fixed_div->div.name); + return ret; + } + } + + for (i = 0; i < ARRAY_SIZE(cv1800b_mux_info); i++) { + struct cv1800b_clk_mux *mux = &cv1800b_mux_info[i]; + int parent; + + mux->base = base; + parent = cv1800b_clk_getfield(base, &mux->mux); + ret = clk_register(&mux->clk, "cv1800b_clk_mux", mux->name, + mux->parent_names[parent]); + if (ret) { + pr_err("Failed to register mux %s\n", mux->name); + return ret; + } + } + + for (i = 0; i < ARRAY_SIZE(cv1800b_mmux_info); i++) { + struct cv1800b_clk_mmux *mmux = &cv1800b_mmux_info[i]; + int clk_sel, parent, idx; + + mmux->base = base; + clk_sel = cv1800b_clk_getbit(base, &mmux->clk_sel) ? 0 : 1; + parent = cv1800b_clk_getfield(base, &mmux->mux[clk_sel]); + for (idx = 0; idx < mmux->num_parents; idx++) { + if (clk_sel == mmux->parent_infos[idx].clk_sel && + parent == mmux->parent_infos[idx].index) + break; + } + ret = clk_register(&mmux->clk, "cv1800b_clk_mmux", mmux->name, + mmux->parent_infos[idx].name); + if (ret) { + pr_err("Failed to register mmux %s\n", mmux->name); + return ret; + } + } + + for (i = 0; i < ARRAY_SIZE(cv1800b_audio_info); i++) { + struct cv1800b_clk_audio *audio = &cv1800b_audio_info[i]; + + audio->base = base; + ret = clk_register(&audio->clk, "cv1800b_clk_audio", + audio->name, audio->parent_name); + if (ret) { + pr_err("Failed to register audio %s\n", audio->name); + return ret; + } + } + + for (i = 0; i < ARRAY_SIZE(cv1800b_bypass_mux_info); i++) { + struct cv1800b_clk_bypass_mux *bypass_mux = + &cv1800b_bypass_mux_info[i]; + int parent; + + bypass_mux->mux.base = base; + parent = cv1800b_clk_getfield(base, &bypass_mux->mux.mux); + ret = clk_register(&bypass_mux->mux.clk, + "cv1800b_clk_bypass_mux", + bypass_mux->mux.name, + bypass_mux->mux.parent_names[parent]); + if (ret) { + pr_err("Failed to register bypass mux %s\n", + bypass_mux->mux.name); + return ret; + } + } + + for (i = 0; i < ARRAY_SIZE(cv1800b_bypass_div_info); i++) { + struct cv1800b_clk_bypass_div *bypass_div = + &cv1800b_bypass_div_info[i]; + + bypass_div->div.base = base; + ret = clk_register(&bypass_div->div.clk, + "cv1800b_clk_bypass_div", + bypass_div->div.name, + bypass_div->div.parent_name); + if (ret) { + pr_err("Failed to register bypass div %s\n", + bypass_div->div.name); + return ret; + } + } + + for (i = 0; i < ARRAY_SIZE(cv1800b_gate_info); i++) { + struct cv1800b_clk_gate *gate = &cv1800b_gate_info[i]; + + gate->base = base; + ret = clk_register(&gate->clk, "cv1800b_clk_gate", gate->name, + gate->parent_name); + if (ret) { + pr_err("Failed to register gate %s\n", gate->name); + return ret; + } + } + return 0; +} + +static int cv1800b_clk_probe(struct udevice *dev) +{ + return cv1800b_register_clk(dev); +} + +static int cv1800b_clk_enable(struct clk *clk) +{ + struct clk *c; + int err = clk_get_by_id(CV1800B_CLK_ID_TRANSFORM(clk->id), &c); + + if (err) + return err; + return clk_enable(c); +} + +static int cv1800b_clk_disable(struct clk *clk) +{ + struct clk *c; + int err = clk_get_by_id(CV1800B_CLK_ID_TRANSFORM(clk->id), &c); + + if (err) + return err; + return clk_disable(c); +} + +static ulong cv1800b_clk_get_rate(struct clk *clk) +{ + struct clk *c; + int err = clk_get_by_id(CV1800B_CLK_ID_TRANSFORM(clk->id), &c); + + if (err) + return err; + return clk_get_rate(c); +} + +static ulong cv1800b_clk_set_rate(struct clk *clk, ulong rate) +{ + struct clk *c; + int err = clk_get_by_id(CV1800B_CLK_ID_TRANSFORM(clk->id), &c); + + if (err) + return err; + return clk_set_rate(c, rate); +} + +static int cv1800b_clk_set_parent(struct clk *clk, struct clk *parent) +{ + struct clk *c, *p; + int err = clk_get_by_id(CV1800B_CLK_ID_TRANSFORM(clk->id), &c); + + if (err) + return err; + err = clk_get_by_id(CV1800B_CLK_ID_TRANSFORM(parent->id), &p); + if (err) + return err; + return clk_set_parent(c, p); +} + +const struct clk_ops cv1800b_clk_ops = { + .enable = cv1800b_clk_enable, + .disable = cv1800b_clk_disable, + .get_rate = cv1800b_clk_get_rate, + .set_rate = cv1800b_clk_set_rate, + .set_parent = cv1800b_clk_set_parent, +}; + +static const struct udevice_id cv1800b_clk_of_match[] = { + { .compatible = "sophgo,cv1800-clk" }, + { }, +}; + +U_BOOT_DRIVER(sophgo_clk) = { + .name = "cv1800b_clk", + .id = UCLASS_CLK, + .of_match = cv1800b_clk_of_match, + .probe = cv1800b_clk_probe, + .ops = &cv1800b_clk_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/clk/sophgo/clk-cv1800b.h b/drivers/clk/sophgo/clk-cv1800b.h new file mode 100644 index 00000000000..1e7107b5d05 --- /dev/null +++ b/drivers/clk/sophgo/clk-cv1800b.h @@ -0,0 +1,123 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com> + */ + +#ifndef _CLK_SOPHGO_CV1800_H_ +#define _CLK_SOPHGO_CV1800_H_ + +#include <dt-bindings/clock/sophgo,cv1800.h> + +#define CV1800_CLK_MAX (CLK_XTAL_AP + 1) +#define CV1810_CLK_MAX (CLK_DISP_SRC_VIP + 1) + +#define REG_PLL_G2_CTRL 0x800 +#define REG_PLL_G2_STATUS 0x804 +#define REG_MIPIMPLL_CSR 0x808 +#define REG_A0PLL_CSR 0x80C +#define REG_DISPPLL_CSR 0x810 +#define REG_CAM0PLL_CSR 0x814 +#define REG_CAM1PLL_CSR 0x818 +#define REG_PLL_G2_SSC_SYN_CTRL 0x840 +#define REG_A0PLL_SSC_SYN_CTRL 0x850 +#define REG_A0PLL_SSC_SYN_SET 0x854 +#define REG_A0PLL_SSC_SYN_SPAN 0x858 +#define REG_A0PLL_SSC_SYN_STEP 0x85C +#define REG_DISPPLL_SSC_SYN_CTRL 0x860 +#define REG_DISPPLL_SSC_SYN_SET 0x864 +#define REG_DISPPLL_SSC_SYN_SPAN 0x868 +#define REG_DISPPLL_SSC_SYN_STEP 0x86C +#define REG_CAM0PLL_SSC_SYN_CTRL 0x870 +#define REG_CAM0PLL_SSC_SYN_SET 0x874 +#define REG_CAM0PLL_SSC_SYN_SPAN 0x878 +#define REG_CAM0PLL_SSC_SYN_STEP 0x87C +#define REG_CAM1PLL_SSC_SYN_CTRL 0x880 +#define REG_CAM1PLL_SSC_SYN_SET 0x884 +#define REG_CAM1PLL_SSC_SYN_SPAN 0x888 +#define REG_CAM1PLL_SSC_SYN_STEP 0x88C +#define REG_APLL_FRAC_DIV_CTRL 0x890 +#define REG_APLL_FRAC_DIV_M 0x894 +#define REG_APLL_FRAC_DIV_N 0x898 +#define REG_MIPIMPLL_CLK_CSR 0x8A0 +#define REG_A0PLL_CLK_CSR 0x8A4 +#define REG_DISPPLL_CLK_CSR 0x8A8 +#define REG_CAM0PLL_CLK_CSR 0x8AC +#define REG_CAM1PLL_CLK_CSR 0x8B0 +#define REG_CLK_CAM0_SRC_DIV 0x8C0 +#define REG_CLK_CAM1_SRC_DIV 0x8C4 + +/* top_pll_g6 */ +#define REG_PLL_G6_CTRL 0x900 +#define REG_PLL_G6_STATUS 0x904 +#define REG_MPLL_CSR 0x908 +#define REG_TPLL_CSR 0x90C +#define REG_FPLL_CSR 0x910 +#define REG_PLL_G6_SSC_SYN_CTRL 0x940 +#define REG_DPLL_SSC_SYN_CTRL 0x950 +#define REG_DPLL_SSC_SYN_SET 0x954 +#define REG_DPLL_SSC_SYN_SPAN 0x958 +#define REG_DPLL_SSC_SYN_STEP 0x95C +#define REG_MPLL_SSC_SYN_CTRL 0x960 +#define REG_MPLL_SSC_SYN_SET 0x964 +#define REG_MPLL_SSC_SYN_SPAN 0x968 +#define REG_MPLL_SSC_SYN_STEP 0x96C +#define REG_TPLL_SSC_SYN_CTRL 0x970 +#define REG_TPLL_SSC_SYN_SET 0x974 +#define REG_TPLL_SSC_SYN_SPAN 0x978 +#define REG_TPLL_SSC_SYN_STEP 0x97C + +/* clkgen */ +#define REG_CLK_EN_0 0x000 +#define REG_CLK_EN_1 0x004 +#define REG_CLK_EN_2 0x008 +#define REG_CLK_EN_3 0x00C +#define REG_CLK_EN_4 0x010 +#define REG_CLK_SEL_0 0x020 +#define REG_CLK_BYP_0 0x030 +#define REG_CLK_BYP_1 0x034 + +#define REG_DIV_CLK_A53_0 0x040 +#define REG_DIV_CLK_A53_1 0x044 +#define REG_DIV_CLK_CPU_AXI0 0x048 +#define REG_DIV_CLK_CPU_GIC 0x050 +#define REG_DIV_CLK_TPU 0x054 +#define REG_DIV_CLK_EMMC 0x064 +#define REG_DIV_CLK_EMMC_100K 0x06C +#define REG_DIV_CLK_SD0 0x070 +#define REG_DIV_CLK_SD0_100K 0x078 +#define REG_DIV_CLK_SD1 0x07C +#define REG_DIV_CLK_SD1_100K 0x084 +#define REG_DIV_CLK_SPI_NAND 0x088 +#define REG_DIV_CLK_ETH0_500M 0x08C +#define REG_DIV_CLK_ETH1_500M 0x090 +#define REG_DIV_CLK_GPIO_DB 0x094 +#define REG_DIV_CLK_SDMA_AUD0 0x098 +#define REG_DIV_CLK_SDMA_AUD1 0x09C +#define REG_DIV_CLK_SDMA_AUD2 0x0A0 +#define REG_DIV_CLK_SDMA_AUD3 0x0A4 +#define REG_DIV_CLK_CAM0_200 0x0A8 +#define REG_DIV_CLK_AXI4 0x0B8 +#define REG_DIV_CLK_AXI6 0x0BC +#define REG_DIV_CLK_DSI_ESC 0x0C4 +#define REG_DIV_CLK_AXI_VIP 0x0C8 +#define REG_DIV_CLK_SRC_VIP_SYS_0 0x0D0 +#define REG_DIV_CLK_SRC_VIP_SYS_1 0x0D8 +#define REG_DIV_CLK_DISP_SRC_VIP 0x0E0 +#define REG_DIV_CLK_AXI_VIDEO_CODEC 0x0E4 +#define REG_DIV_CLK_VC_SRC0 0x0EC +#define REG_DIV_CLK_1M 0x0FC +#define REG_DIV_CLK_SPI 0x100 +#define REG_DIV_CLK_I2C 0x104 +#define REG_DIV_CLK_SRC_VIP_SYS_2 0x110 +#define REG_DIV_CLK_AUDSRC 0x118 +#define REG_DIV_CLK_PWM_SRC_0 0x120 +#define REG_DIV_CLK_AP_DEBUG 0x128 +#define REG_DIV_CLK_RTCSYS_SRC_0 0x12C +#define REG_DIV_CLK_C906_0_0 0x130 +#define REG_DIV_CLK_C906_0_1 0x134 +#define REG_DIV_CLK_C906_1_0 0x138 +#define REG_DIV_CLK_C906_1_1 0x13C +#define REG_DIV_CLK_SRC_VIP_SYS_3 0x140 +#define REG_DIV_CLK_SRC_VIP_SYS_4 0x144 + +#endif /* _CLK_SOPHGO_CV1800_H_ */ diff --git a/drivers/clk/sophgo/clk-ip.c b/drivers/clk/sophgo/clk-ip.c new file mode 100644 index 00000000000..d571fa671b0 --- /dev/null +++ b/drivers/clk/sophgo/clk-ip.c @@ -0,0 +1,594 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com> + */ + +#include <dm.h> +#include <div64.h> +#include <linux/clk-provider.h> +#include <linux/io.h> + +#include "clk-common.h" +#include "clk-ip.h" + +static int get_parent_index(struct clk *clk, const char *const *parent_name, + u8 num_parents) +{ + const char *name = clk_hw_get_name(clk); + int i; + + for (i = 0; i < num_parents; i++) { + if (!strcmp(name, parent_name[i])) + return i; + } + + return -1; +} + +/* GATE */ +#define to_cv1800b_clk_gate(_clk) \ + container_of(_clk, struct cv1800b_clk_gate, clk) + +static int gate_enable(struct clk *clk) +{ + struct cv1800b_clk_gate *gate = to_cv1800b_clk_gate(clk); + + return cv1800b_clk_setbit(gate->base, &gate->gate); +} + +static int gate_disable(struct clk *clk) +{ + struct cv1800b_clk_gate *gate = to_cv1800b_clk_gate(clk); + + return cv1800b_clk_clrbit(gate->base, &gate->gate); +} + +static ulong gate_get_rate(struct clk *clk) +{ + return clk_get_parent_rate(clk); +} + +const struct clk_ops cv1800b_clk_gate_ops = { + .disable = gate_disable, + .enable = gate_enable, + .get_rate = gate_get_rate, +}; + +U_BOOT_DRIVER(cv1800b_clk_gate) = { + .name = "cv1800b_clk_gate", + .id = UCLASS_CLK, + .ops = &cv1800b_clk_gate_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +/* DIV */ +#define CLK_DIV_EN_FACTOR BIT(3) + +#define to_cv1800b_clk_div(_clk) container_of(_clk, struct cv1800b_clk_div, clk) + +static int div_enable(struct clk *clk) +{ + struct cv1800b_clk_div *div = to_cv1800b_clk_div(clk); + + return cv1800b_clk_setbit(div->base, &div->gate); +} + +static int div_disable(struct clk *clk) +{ + struct cv1800b_clk_div *div = to_cv1800b_clk_div(clk); + + return cv1800b_clk_clrbit(div->base, &div->gate); +} + +static ulong div_get_rate(struct clk *clk) +{ + struct cv1800b_clk_div *div = to_cv1800b_clk_div(clk); + ulong val; + + if (div->div_init == 0 || + readl(div->base + div->div.offset) & CLK_DIV_EN_FACTOR) + val = cv1800b_clk_getfield(div->base, &div->div); + else + val = div->div_init; + + return DIV_ROUND_UP_ULL(clk_get_parent_rate(clk), val); +} + +static ulong div_set_rate(struct clk *clk, ulong rate) +{ + struct cv1800b_clk_div *div = to_cv1800b_clk_div(clk); + ulong parent_rate = clk_get_parent_rate(clk); + u32 val; + + val = DIV_ROUND_UP_ULL(parent_rate, rate); + val = min_t(u32, val, clk_div_mask(div->div.width)); + + cv1800b_clk_setfield(div->base, &div->div, val); + if (div->div_init > 0) + setbits_le32(div->base + div->div.offset, CLK_DIV_EN_FACTOR); + + return DIV_ROUND_UP_ULL(parent_rate, val); +} + +const struct clk_ops cv1800b_clk_div_ops = { + .disable = div_disable, + .enable = div_enable, + .get_rate = div_get_rate, + .set_rate = div_set_rate, +}; + +U_BOOT_DRIVER(cv1800b_clk_div) = { + .name = "cv1800b_clk_div", + .id = UCLASS_CLK, + .ops = &cv1800b_clk_div_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +#define to_cv1800b_clk_bypass_div(_clk) \ + container_of(_clk, struct cv1800b_clk_bypass_div, div.clk) + +static ulong bypass_div_get_rate(struct clk *clk) +{ + struct cv1800b_clk_bypass_div *div = to_cv1800b_clk_bypass_div(clk); + + if (cv1800b_clk_getbit(div->div.base, &div->bypass)) + return 0; + + return div_get_rate(clk); +} + +static ulong bypass_div_set_rate(struct clk *clk, ulong rate) +{ + struct cv1800b_clk_bypass_div *div = to_cv1800b_clk_bypass_div(clk); + + if (cv1800b_clk_getbit(div->div.base, &div->bypass)) + return 0; + + return div_set_rate(clk, rate); +} + +static int bypass_div_set_parent(struct clk *clk, struct clk *pclk) +{ + struct cv1800b_clk_bypass_div *div = to_cv1800b_clk_bypass_div(clk); + + if (pclk->id == CV1800B_CLK_BYPASS) { + cv1800b_clk_setbit(div->div.base, &div->bypass); + return 0; + } + + if (strcmp(clk_hw_get_name(pclk), div->div.parent_name)) + return -EINVAL; + + cv1800b_clk_clrbit(div->div.base, &div->bypass); + return 0; +} + +const struct clk_ops cv1800b_clk_bypass_div_ops = { + .disable = div_disable, + .enable = div_enable, + .get_rate = bypass_div_get_rate, + .set_rate = bypass_div_set_rate, + .set_parent = bypass_div_set_parent, +}; + +U_BOOT_DRIVER(cv1800b_clk_bypass_div) = { + .name = "cv1800b_clk_bypass_div", + .id = UCLASS_CLK, + .ops = &cv1800b_clk_bypass_div_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +/* FIXED DIV */ +#define to_cv1800b_clk_fixed_div(_clk) \ + container_of(_clk, struct cv1800b_clk_fixed_div, clk) + +static int fixed_div_enable(struct clk *clk) +{ + struct cv1800b_clk_fixed_div *div = to_cv1800b_clk_fixed_div(clk); + + return cv1800b_clk_setbit(div->base, &div->gate); +} + +static int fixed_div_disable(struct clk *clk) +{ + struct cv1800b_clk_fixed_div *div = to_cv1800b_clk_fixed_div(clk); + + return cv1800b_clk_clrbit(div->base, &div->gate); +} + +static ulong fixed_div_get_rate(struct clk *clk) +{ + struct cv1800b_clk_fixed_div *div = to_cv1800b_clk_fixed_div(clk); + + return DIV_ROUND_UP_ULL(clk_get_parent_rate(clk), div->div); +} + +const struct clk_ops cv1800b_clk_fixed_div_ops = { + .disable = fixed_div_disable, + .enable = fixed_div_enable, + .get_rate = fixed_div_get_rate, +}; + +U_BOOT_DRIVER(cv1800b_clk_fixed_div) = { + .name = "cv1800b_clk_fixed_div", + .id = UCLASS_CLK, + .ops = &cv1800b_clk_fixed_div_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +#define to_cv1800b_clk_bypass_fixed_div(_clk) \ + container_of(_clk, struct cv1800b_clk_bypass_fixed_div, div.clk) + +static ulong bypass_fixed_div_get_rate(struct clk *clk) +{ + struct cv1800b_clk_bypass_fixed_div *div = + to_cv1800b_clk_bypass_fixed_div(clk); + + if (cv1800b_clk_getbit(div->div.base, &div->bypass)) + return 0; + + return fixed_div_get_rate(clk); +} + +static int bypass_fixed_div_set_parent(struct clk *clk, struct clk *pclk) +{ + struct cv1800b_clk_bypass_fixed_div *div = + to_cv1800b_clk_bypass_fixed_div(clk); + + if (pclk->id == CV1800B_CLK_BYPASS) { + cv1800b_clk_setbit(div->div.base, &div->bypass); + return 0; + } + + if (strcmp(clk_hw_get_name(pclk), div->div.parent_name)) + return -EINVAL; + + cv1800b_clk_clrbit(div->div.base, &div->bypass); + return 0; +} + +const struct clk_ops cv1800b_clk_bypass_fixed_div_ops = { + .disable = fixed_div_disable, + .enable = fixed_div_enable, + .get_rate = bypass_fixed_div_get_rate, + .set_parent = bypass_fixed_div_set_parent, +}; + +U_BOOT_DRIVER(cv1800b_clk_bypass_fixed_div) = { + .name = "cv1800b_clk_bypass_fixed_div", + .id = UCLASS_CLK, + .ops = &cv1800b_clk_bypass_fixed_div_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +/* MUX */ +#define to_cv1800b_clk_mux(_clk) container_of(_clk, struct cv1800b_clk_mux, clk) + +static int mux_enable(struct clk *clk) +{ + struct cv1800b_clk_mux *mux = to_cv1800b_clk_mux(clk); + + return cv1800b_clk_setbit(mux->base, &mux->gate); +} + +static int mux_disable(struct clk *clk) +{ + struct cv1800b_clk_mux *mux = to_cv1800b_clk_mux(clk); + + return cv1800b_clk_clrbit(mux->base, &mux->gate); +} + +static ulong mux_get_rate(struct clk *clk) +{ + struct cv1800b_clk_mux *mux = to_cv1800b_clk_mux(clk); + ulong val; + + if (mux->div_init == 0 || + readl(mux->base + mux->div.offset) & CLK_DIV_EN_FACTOR) + val = cv1800b_clk_getfield(mux->base, &mux->div); + else + val = mux->div_init; + + return DIV_ROUND_UP_ULL(clk_get_parent_rate(clk), val); +} + +static ulong mux_set_rate(struct clk *clk, ulong rate) +{ + struct cv1800b_clk_mux *mux = to_cv1800b_clk_mux(clk); + ulong parent_rate = clk_get_parent_rate(clk); + ulong val; + + val = DIV_ROUND_UP_ULL(parent_rate, rate); + val = min_t(u32, val, clk_div_mask(mux->div.width)); + + cv1800b_clk_setfield(mux->base, &mux->div, val); + if (mux->div_init > 0) + setbits_le32(mux->base + mux->div.offset, CLK_DIV_EN_FACTOR); + + return DIV_ROUND_UP_ULL(parent_rate, val); +} + +static int mux_set_parent(struct clk *clk, struct clk *pclk) +{ + struct cv1800b_clk_mux *mux = to_cv1800b_clk_mux(clk); + int index = get_parent_index(pclk, mux->parent_names, mux->num_parents); + + if (index < 0) + return -EINVAL; + + cv1800b_clk_setfield(mux->base, &mux->mux, index); + return 0; +} + +const struct clk_ops cv1800b_clk_mux_ops = { + .disable = mux_disable, + .enable = mux_enable, + .get_rate = mux_get_rate, + .set_rate = mux_set_rate, + .set_parent = mux_set_parent, +}; + +U_BOOT_DRIVER(cv1800b_clk_mux) = { + .name = "cv1800b_clk_mux", + .id = UCLASS_CLK, + .ops = &cv1800b_clk_mux_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +#define to_cv1800b_clk_bypass_mux(_clk) \ + container_of(_clk, struct cv1800b_clk_bypass_mux, mux.clk) + +static ulong bypass_mux_get_rate(struct clk *clk) +{ + struct cv1800b_clk_bypass_mux *mux = to_cv1800b_clk_bypass_mux(clk); + + if (cv1800b_clk_getbit(mux->mux.base, &mux->bypass)) + return 0; + + return mux_get_rate(clk); +} + +static ulong bypass_mux_set_rate(struct clk *clk, ulong rate) +{ + struct cv1800b_clk_bypass_mux *mux = to_cv1800b_clk_bypass_mux(clk); + + if (cv1800b_clk_getbit(mux->mux.base, &mux->bypass)) + return 0; + + return mux_set_rate(clk, rate); +} + +static int bypass_mux_set_parent(struct clk *clk, struct clk *pclk) +{ + struct cv1800b_clk_bypass_mux *mux = to_cv1800b_clk_bypass_mux(clk); + int index; + + if (pclk->id == CV1800B_CLK_BYPASS) { + cv1800b_clk_setbit(mux->mux.base, &mux->bypass); + return 0; + } + + index = get_parent_index(pclk, mux->mux.parent_names, + mux->mux.num_parents); + if (index < 0) + return -EINVAL; + + cv1800b_clk_clrbit(mux->mux.base, &mux->bypass); + cv1800b_clk_setfield(mux->mux.base, &mux->mux.mux, index); + return 0; +} + +const struct clk_ops cv1800b_clk_bypass_mux_ops = { + .disable = mux_disable, + .enable = mux_enable, + .get_rate = bypass_mux_get_rate, + .set_rate = bypass_mux_set_rate, + .set_parent = bypass_mux_set_parent, +}; + +U_BOOT_DRIVER(cv1800b_clk_bypass_mux) = { + .name = "cv1800b_clk_bypass_mux", + .id = UCLASS_CLK, + .ops = &cv1800b_clk_bypass_mux_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +/* MMUX */ +#define to_cv1800b_clk_mmux(_clk) \ + container_of(_clk, struct cv1800b_clk_mmux, clk) + +static int mmux_enable(struct clk *clk) +{ + struct cv1800b_clk_mmux *mmux = to_cv1800b_clk_mmux(clk); + + return cv1800b_clk_setbit(mmux->base, &mmux->gate); +} + +static int mmux_disable(struct clk *clk) +{ + struct cv1800b_clk_mmux *mmux = to_cv1800b_clk_mmux(clk); + + return cv1800b_clk_clrbit(mmux->base, &mmux->gate); +} + +static ulong mmux_get_rate(struct clk *clk) +{ + struct cv1800b_clk_mmux *mmux = to_cv1800b_clk_mmux(clk); + int clk_sel = 1; + ulong reg, val; + + if (cv1800b_clk_getbit(mmux->base, &mmux->bypass)) + return 0; + + if (cv1800b_clk_getbit(mmux->base, &mmux->clk_sel)) + clk_sel = 0; + + reg = readl(mmux->base + mmux->div[clk_sel].offset); + + if (mmux->div_init[clk_sel] == 0 || reg & CLK_DIV_EN_FACTOR) + val = cv1800b_clk_getfield(mmux->base, &mmux->div[clk_sel]); + else + val = mmux->div_init[clk_sel]; + + return DIV_ROUND_UP_ULL(clk_get_parent_rate(clk), val); +} + +static ulong mmux_set_rate(struct clk *clk, ulong rate) +{ + struct cv1800b_clk_mmux *mmux = to_cv1800b_clk_mmux(clk); + int clk_sel = 1; + ulong parent_rate = clk_get_parent_rate(clk); + ulong val; + + if (cv1800b_clk_getbit(mmux->base, &mmux->bypass)) + return 0; + + if (cv1800b_clk_getbit(mmux->base, &mmux->clk_sel)) + clk_sel = 0; + + val = DIV_ROUND_UP_ULL(parent_rate, rate); + val = min_t(u32, val, clk_div_mask(mmux->div[clk_sel].width)); + + cv1800b_clk_setfield(mmux->base, &mmux->div[clk_sel], val); + if (mmux->div_init[clk_sel] > 0) + setbits_le32(mmux->base + mmux->div[clk_sel].offset, + CLK_DIV_EN_FACTOR); + + return DIV_ROUND_UP_ULL(parent_rate, val); +} + +static int mmux_set_parent(struct clk *clk, struct clk *pclk) +{ + struct cv1800b_clk_mmux *mmux = to_cv1800b_clk_mmux(clk); + const char *pname = clk_hw_get_name(pclk); + int i; + u8 clk_sel, index; + + if (pclk->id == CV1800B_CLK_BYPASS) { + cv1800b_clk_setbit(mmux->base, &mmux->bypass); + return 0; + } + + for (i = 0; i < mmux->num_parents; i++) { + if (!strcmp(pname, mmux->parent_infos[i].name)) + break; + } + + if (i == mmux->num_parents) + return -EINVAL; + + clk_sel = mmux->parent_infos[i].clk_sel; + index = mmux->parent_infos[i].index; + cv1800b_clk_clrbit(mmux->base, &mmux->bypass); + if (clk_sel) + cv1800b_clk_clrbit(mmux->base, &mmux->clk_sel); + else + cv1800b_clk_setbit(mmux->base, &mmux->clk_sel); + + cv1800b_clk_setfield(mmux->base, &mmux->mux[clk_sel], index); + return 0; +} + +const struct clk_ops cv1800b_clk_mmux_ops = { + .disable = mmux_disable, + .enable = mmux_enable, + .get_rate = mmux_get_rate, + .set_rate = mmux_set_rate, + .set_parent = mmux_set_parent, +}; + +U_BOOT_DRIVER(cv1800b_clk_mmux) = { + .name = "cv1800b_clk_mmux", + .id = UCLASS_CLK, + .ops = &cv1800b_clk_mmux_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +/* AUDIO CLK */ +#define to_cv1800b_clk_audio(_clk) \ + container_of(_clk, struct cv1800b_clk_audio, clk) + +static int aclk_enable(struct clk *clk) +{ + struct cv1800b_clk_audio *aclk = to_cv1800b_clk_audio(clk); + + cv1800b_clk_setbit(aclk->base, &aclk->src_en); + cv1800b_clk_setbit(aclk->base, &aclk->output_en); + return 0; +} + +static int aclk_disable(struct clk *clk) +{ + struct cv1800b_clk_audio *aclk = to_cv1800b_clk_audio(clk); + + cv1800b_clk_clrbit(aclk->base, &aclk->src_en); + cv1800b_clk_clrbit(aclk->base, &aclk->output_en); + return 0; +} + +static ulong aclk_get_rate(struct clk *clk) +{ + struct cv1800b_clk_audio *aclk = to_cv1800b_clk_audio(clk); + u64 parent_rate = clk_get_parent_rate(clk); + u32 m, n; + + if (!cv1800b_clk_getbit(aclk->base, &aclk->div_en)) + return 0; + + m = cv1800b_clk_getfield(aclk->base, &aclk->m); + n = cv1800b_clk_getfield(aclk->base, &aclk->n); + + return DIV_ROUND_UP_ULL(n * parent_rate, m * 2); +} + +static u32 gcd(u32 a, u32 b) +{ + u32 t; + + while (b != 0) { + t = a % b; + a = b; + b = t; + } + return a; +} + +static void aclk_determine_mn(ulong parent_rate, ulong rate, u32 *m, u32 *n) +{ + u32 tm = parent_rate / 2; + u32 tn = rate; + u32 tcommon = gcd(tm, tn); + *m = tm / tcommon; + *n = tn / tcommon; +} + +static ulong aclk_set_rate(struct clk *clk, ulong rate) +{ + struct cv1800b_clk_audio *aclk = to_cv1800b_clk_audio(clk); + ulong parent_rate = clk_get_parent_rate(clk); + u32 m, n; + + aclk_determine_mn(parent_rate, rate, &m, &n); + + cv1800b_clk_setfield(aclk->base, &aclk->m, m); + cv1800b_clk_setfield(aclk->base, &aclk->n, n); + + cv1800b_clk_setbit(aclk->base, &aclk->div_en); + cv1800b_clk_setbit(aclk->base, &aclk->div_up); + + return DIV_ROUND_UP_ULL(parent_rate * n, m * 2); +} + +const struct clk_ops cv1800b_clk_audio_ops = { + .disable = aclk_disable, + .enable = aclk_enable, + .get_rate = aclk_get_rate, + .set_rate = aclk_set_rate, +}; + +U_BOOT_DRIVER(cv1800b_clk_audio) = { + .name = "cv1800b_clk_audio", + .id = UCLASS_CLK, + .ops = &cv1800b_clk_audio_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/clk/sophgo/clk-ip.h b/drivers/clk/sophgo/clk-ip.h new file mode 100644 index 00000000000..09d15d86dc9 --- /dev/null +++ b/drivers/clk/sophgo/clk-ip.h @@ -0,0 +1,288 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com> + * + */ + +#ifndef __CLK_SOPHGO_IP_H__ +#define __CLK_SOPHGO_IP_H__ + +#include <clk.h> + +#include "clk-common.h" + +struct cv1800b_mmux_parent_info { + const char *name; + u8 clk_sel; + u8 index; +}; + +struct cv1800b_clk_gate { + struct clk clk; + const char *name; + const char *parent_name; + void __iomem *base; + struct cv1800b_clk_regbit gate; +}; + +struct cv1800b_clk_div { + struct clk clk; + const char *name; + const char *parent_name; + void __iomem *base; + struct cv1800b_clk_regbit gate; + struct cv1800b_clk_regfield div; + int div_init; +}; + +struct cv1800b_clk_bypass_div { + struct cv1800b_clk_div div; + struct cv1800b_clk_regbit bypass; +}; + +struct cv1800b_clk_fixed_div { + struct clk clk; + const char *name; + const char *parent_name; + void __iomem *base; + struct cv1800b_clk_regbit gate; + int div; +}; + +struct cv1800b_clk_bypass_fixed_div { + struct cv1800b_clk_fixed_div div; + struct cv1800b_clk_regbit bypass; +}; + +struct cv1800b_clk_mux { + struct clk clk; + const char *name; + const char * const *parent_names; + u8 num_parents; + void __iomem *base; + struct cv1800b_clk_regbit gate; + struct cv1800b_clk_regfield div; + int div_init; + struct cv1800b_clk_regfield mux; +}; + +struct cv1800b_clk_bypass_mux { + struct cv1800b_clk_mux mux; + struct cv1800b_clk_regbit bypass; +}; + +struct cv1800b_clk_mmux { + struct clk clk; + const char *name; + const struct cv1800b_mmux_parent_info *parent_infos; + u8 num_parents; + void __iomem *base; + struct cv1800b_clk_regbit gate; + struct cv1800b_clk_regfield div[2]; + int div_init[2]; + struct cv1800b_clk_regfield mux[2]; + struct cv1800b_clk_regbit bypass; + struct cv1800b_clk_regbit clk_sel; +}; + +struct cv1800b_clk_audio { + struct clk clk; + const char *name; + const char *parent_name; + void __iomem *base; + struct cv1800b_clk_regbit src_en; + struct cv1800b_clk_regbit output_en; + struct cv1800b_clk_regbit div_en; + struct cv1800b_clk_regbit div_up; + struct cv1800b_clk_regfield m; + struct cv1800b_clk_regfield n; +}; + +#define CV1800B_GATE(_id, _name, _parent, \ + _gate_offset, _gate_shift, \ + _flags) \ + { \ + .clk = { \ + .id = CV1800B_CLK_ID_TRANSFORM(_id), \ + .flags = _flags, \ + }, \ + .name = _name, \ + .parent_name = _parent, \ + .gate = CV1800B_CLK_REGBIT(_gate_offset, _gate_shift), \ + } + +#define CV1800B_DIV(_id, _name, _parent, \ + _gate_offset, _gate_shift, \ + _div_offset, _div_shift, _div_width, \ + _div_init, _flags) \ + { \ + .clk = { \ + .id = CV1800B_CLK_ID_TRANSFORM(_id), \ + .flags = _flags, \ + }, \ + .name = _name, \ + .parent_name = _parent, \ + .gate = CV1800B_CLK_REGBIT(_gate_offset, _gate_shift), \ + .div = CV1800B_CLK_REGFIELD(_div_offset, _div_shift, \ + _div_width), \ + .div_init = _div_init, \ + } + +#define CV1800B_BYPASS_DIV(_id, _name, _parent, \ + _gate_offset, _gate_shift, \ + _div_offset, _div_shift, \ + _div_width, _div_init, \ + _bypass_offset, _bypass_shift, \ + _flags) \ + { \ + .div = CV1800B_DIV(_id, _name, _parent, \ + _gate_offset, _gate_shift, \ + _div_offset, _div_shift, _div_width, \ + _div_init, _flags), \ + .bypass = CV1800B_CLK_REGBIT(_bypass_offset, \ + _bypass_shift), \ + } + +#define CV1800B_FIXED_DIV(_id, _name, _parent, \ + _gate_offset, _gate_shift, \ + _div, _flags) \ + { \ + .clk = { \ + .id = CV1800B_CLK_ID_TRANSFORM(_id), \ + .flags = _flags, \ + }, \ + .name = _name, \ + .parent_name = _parent, \ + .gate = CV1800B_CLK_REGBIT(_gate_offset, _gate_shift), \ + .div = _div, \ + } + +#define CV1800B_BYPASS_FIXED_DIV(_id, _name, _parent, \ + _gate_offset, _gate_shift, \ + _div, \ + _bypass_offset, _bypass_shift, \ + _flags) \ + { \ + .div = CV1800B_FIXED_DIV(_id, _name, _parent, \ + _gate_offset, _gate_shift, \ + _div, _flags), \ + .bypass = CV1800B_CLK_REGBIT(_bypass_offset, \ + _bypass_shift) \ + } + +#define CV1800B_MUX(_id, _name, _parents, \ + _gate_offset, _gate_shift, \ + _div_offset, _div_shift, _div_width, _div_init, \ + _mux_offset, _mux_shift, _mux_width, \ + _flags) \ + { \ + .clk = { \ + .id = CV1800B_CLK_ID_TRANSFORM(_id), \ + .flags = _flags, \ + }, \ + .name = _name, \ + .parent_names = _parents, \ + .num_parents = ARRAY_SIZE(_parents), \ + .gate = CV1800B_CLK_REGBIT(_gate_offset, _gate_shift), \ + .div = CV1800B_CLK_REGFIELD(_div_offset, _div_shift, \ + _div_width), \ + .div_init = _div_init, \ + .mux = CV1800B_CLK_REGFIELD(_mux_offset, _mux_shift, \ + _mux_width), \ + } + +#define CV1800B_BYPASS_MUX(_id, _name, _parents, \ + _gate_offset, _gate_shift, \ + _div_offset, _div_shift, \ + _div_width, _div_init, \ + _mux_offset, _mux_shift, _mux_width, \ + _bypass_offset, _bypass_shift, \ + _flags) \ + { \ + .mux = CV1800B_MUX(_id, _name, _parents, \ + _gate_offset, _gate_shift, \ + _div_offset, _div_shift, \ + _div_width, _div_init, \ + _mux_offset, _mux_shift, _mux_width, \ + _flags), \ + .bypass = CV1800B_CLK_REGBIT(_bypass_offset, \ + _bypass_shift), \ + } + +#define CV1800B_MMUX(_id, _name, _parents, \ + _gate_offset, _gate_shift, \ + _div0_offset, _div0_shift, _div0_width, _div0_init,\ + _div1_offset, _div1_shift, _div1_width, _div1_init,\ + _mux0_offset, _mux0_shift, _mux0_width, \ + _mux1_offset, _mux1_shift, _mux1_width, \ + _bypass_offset, _bypass_shift, \ + _clk_sel_offset, _clk_sel_shift, \ + _flags) \ + { \ + .clk = { \ + .id = CV1800B_CLK_ID_TRANSFORM(_id), \ + .flags = _flags, \ + }, \ + .name = _name, \ + .parent_infos = _parents, \ + .num_parents = ARRAY_SIZE(_parents), \ + .gate = CV1800B_CLK_REGBIT(_gate_offset, _gate_shift), \ + .div = { \ + CV1800B_CLK_REGFIELD(_div0_offset, _div0_shift, \ + _div0_width), \ + CV1800B_CLK_REGFIELD(_div1_offset, _div1_shift, \ + _div1_width), \ + }, \ + .div_init = { _div0_init, _div1_init }, \ + .mux = { \ + CV1800B_CLK_REGFIELD(_mux0_offset, _mux0_shift, \ + _mux0_width), \ + CV1800B_CLK_REGFIELD(_mux1_offset, _mux1_shift, \ + _mux1_width), \ + }, \ + .bypass = CV1800B_CLK_REGBIT(_bypass_offset, \ + _bypass_shift), \ + .clk_sel = CV1800B_CLK_REGBIT(_clk_sel_offset, \ + _clk_sel_shift), \ + } + +#define CV1800B_AUDIO(_id, _name, _parent, \ + _src_en_offset, _src_en_shift, \ + _output_en_offset, _output_en_shift, \ + _div_en_offset, _div_en_shift, \ + _div_up_offset, _div_up_shift, \ + _m_offset, _m_shift, _m_width, \ + _n_offset, _n_shift, _n_width, \ + _flags) \ + { \ + .clk = { \ + .id = CV1800B_CLK_ID_TRANSFORM(_id), \ + .flags = _flags, \ + }, \ + .name = _name, \ + .parent_name = _parent, \ + .src_en = CV1800B_CLK_REGBIT(_src_en_offset, \ + _src_en_shift), \ + .output_en = CV1800B_CLK_REGBIT(_output_en_offset, \ + _output_en_shift), \ + .div_en = CV1800B_CLK_REGBIT(_div_en_offset, \ + _div_en_shift), \ + .div_up = CV1800B_CLK_REGBIT(_div_up_offset, \ + _div_up_shift), \ + .m = CV1800B_CLK_REGFIELD(_m_offset, _m_shift, \ + _m_width), \ + .n = CV1800B_CLK_REGFIELD(_n_offset, _n_shift, \ + _n_width), \ + } + +extern const struct clk_ops cv1800b_clk_gate_ops; +extern const struct clk_ops cv1800b_clk_div_ops; +extern const struct clk_ops cv1800b_clk_bypass_div_ops; +extern const struct clk_ops cv1800b_clk_fixed_div_ops; +extern const struct clk_ops cv1800b_clk_bypass_fixed_div_ops; +extern const struct clk_ops cv1800b_clk_mux_ops; +extern const struct clk_ops cv1800b_clk_bypass_mux_ops; +extern const struct clk_ops cv1800b_clk_mmux_ops; +extern const struct clk_ops cv1800b_clk_audio_ops; + +#endif /* __CLK_SOPHGO_IP_H__ */ diff --git a/drivers/clk/sophgo/clk-pll.c b/drivers/clk/sophgo/clk-pll.c new file mode 100644 index 00000000000..c99aa0b4e44 --- /dev/null +++ b/drivers/clk/sophgo/clk-pll.c @@ -0,0 +1,275 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com> + */ + +#include <clk-uclass.h> +#include <dm.h> +#include <div64.h> +#include <linux/bitfield.h> +#include <linux/clk-provider.h> +#include <linux/kernel.h> + +#include "clk-common.h" +#include "clk-pll.h" + +#define PLL_PRE_DIV_MIN 1 +#define PLL_PRE_DIV_MAX 127 +#define PLL_POST_DIV_MIN 1 +#define PLL_POST_DIV_MAX 127 +#define PLL_DIV_MIN 6 +#define PLL_DIV_MAX 127 +#define PLL_ICTRL_MIN 0 +#define PLL_ICTRL_MAX 7 +#define PLL_MODE_MIN 0 +#define PLL_MODE_MAX 3 +#define FOR_RANGE(x, RANGE) for (x = RANGE##_MIN; x <= RANGE##_MAX; x++) + +#define PLL_ICTRL GENMASK(26, 24) +#define PLL_DIV_SEL GENMASK(23, 17) +#define PLL_SEL_MODE GENMASK(16, 15) +#define PLL_POST_DIV_SEL GENMASK(14, 8) +#define PLL_PRE_DIV_SEL GENMASK(6, 0) +#define PLL_MASK_ALL (PLL_ICTRL | PLL_DIV_SEL | PLL_SEL_MODE | PLL_POST_DIV_SEL | PLL_PRE_DIV_SEL) + +/* IPLL */ +#define to_clk_ipll(dev) container_of(dev, struct cv1800b_clk_ipll, clk) + +static int cv1800b_ipll_enable(struct clk *clk) +{ + struct cv1800b_clk_ipll *pll = to_clk_ipll(clk); + + cv1800b_clk_clrbit(pll->base, &pll->pll_pwd); + return 0; +} + +static int cv1800b_ipll_disable(struct clk *clk) +{ + struct cv1800b_clk_ipll *pll = to_clk_ipll(clk); + + cv1800b_clk_setbit(pll->base, &pll->pll_pwd); + return 0; +} + +static ulong cv1800b_ipll_get_rate(struct clk *clk) +{ + struct cv1800b_clk_ipll *pll = to_clk_ipll(clk); + + ulong parent_rate = clk_get_parent_rate(clk); + u32 reg = readl(pll->base + pll->pll_reg); + u32 pre_div = FIELD_GET(PLL_PRE_DIV_SEL, reg); + u32 post_div = FIELD_GET(PLL_POST_DIV_SEL, reg); + u32 div = FIELD_GET(PLL_DIV_SEL, reg); + + return DIV_ROUND_DOWN_ULL(parent_rate * div, pre_div * post_div); +} + +static ulong cv1800b_ipll_set_rate(struct clk *clk, ulong rate) +{ + struct cv1800b_clk_ipll *pll = to_clk_ipll(clk); + ulong parent_rate = clk_get_parent_rate(clk); + u32 pre_div, post_div, div; + u32 pre_div_sel, post_div_sel, div_sel; + ulong new_rate, best_rate = 0; + u32 mode, ictrl; + u32 test, val; + + FOR_RANGE(pre_div, PLL_PRE_DIV) + { + FOR_RANGE(post_div, PLL_POST_DIV) + { + FOR_RANGE(div, PLL_DIV) + { + new_rate = + DIV_ROUND_DOWN_ULL(parent_rate * div, pre_div * post_div); + if (rate - new_rate < rate - best_rate) { + best_rate = new_rate; + pre_div_sel = pre_div; + post_div_sel = post_div; + div_sel = div; + } + } + } + } + + FOR_RANGE(mode, PLL_MODE) + { + FOR_RANGE(ictrl, PLL_ICTRL) + { + test = 184 * (1 + mode) * (1 + ictrl) / 2; + if (test > 20 * div_sel && test < 35 * div_sel) { + val = FIELD_PREP(PLL_PRE_DIV_SEL, pre_div_sel) | + FIELD_PREP(PLL_POST_DIV_SEL, post_div_sel) | + FIELD_PREP(PLL_DIV_SEL, div_sel) | + FIELD_PREP(PLL_ICTRL, ictrl) | + FIELD_PREP(PLL_SEL_MODE, mode); + clrsetbits_le32(pll->base + pll->pll_reg, PLL_MASK_ALL, val); + return best_rate; + } + } + } + + return -EINVAL; +} + +const struct clk_ops cv1800b_ipll_ops = { + .enable = cv1800b_ipll_enable, + .disable = cv1800b_ipll_disable, + .get_rate = cv1800b_ipll_get_rate, + .set_rate = cv1800b_ipll_set_rate, +}; + +U_BOOT_DRIVER(cv1800b_clk_ipll) = { + .name = "cv1800b_clk_ipll", + .id = UCLASS_CLK, + .ops = &cv1800b_ipll_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +/* FPLL */ +#define to_clk_fpll(dev) container_of(dev, struct cv1800b_clk_fpll, ipll.clk) + +static ulong cv1800b_fpll_get_rate(struct clk *clk) +{ + struct cv1800b_clk_fpll *pll = to_clk_fpll(clk); + u32 val, syn_set; + u32 pre_div, post_div, div; + u8 mult = 1; + ulong divisor, remainder, rate; + + if (!cv1800b_clk_getbit(pll->ipll.base, &pll->syn.en)) + return cv1800b_ipll_get_rate(clk); + + syn_set = readl(pll->ipll.base + pll->syn.set); + if (syn_set == 0) + return 0; + + val = readl(pll->ipll.base + pll->ipll.pll_reg); + pre_div = FIELD_GET(PLL_PRE_DIV_SEL, val); + post_div = FIELD_GET(PLL_POST_DIV_SEL, val); + div = FIELD_GET(PLL_DIV_SEL, val); + + if (cv1800b_clk_getbit(pll->ipll.base, &pll->syn.clk_half)) + mult = 2; + + divisor = (ulong)pre_div * post_div * syn_set; + rate = (clk_get_parent_rate(clk) * div) << 25; + remainder = rate % divisor; + rate /= divisor; + return rate * mult + DIV_ROUND_CLOSEST_ULL(remainder * mult, divisor); +} + +static ulong cv1800b_find_syn(ulong rate, ulong parent_rate, ulong pre_div, ulong post_div, + ulong div, u32 *syn) +{ + u32 syn_min = (4 << 26) + 1; + u32 syn_max = U32_MAX; + u32 mid; + ulong new_rate; + u32 mult = 1; + ulong divisor, remainder; + + while (syn_min < syn_max) { + mid = ((ulong)syn_min + syn_max) / 2; + divisor = pre_div * post_div * mid; + new_rate = (parent_rate * div) << 25; + remainder = do_div(new_rate, divisor); + new_rate = new_rate * mult + DIV_ROUND_CLOSEST_ULL(remainder * mult, divisor); + if (new_rate > rate) { + syn_max = mid + 1; + } else if (new_rate < rate) { + syn_min = mid - 1; + } else { + syn_min = mid; + break; + } + } + *syn = syn_min; + return new_rate; +} + +static ulong cv1800b_fpll_set_rate(struct clk *clk, ulong rate) +{ + struct cv1800b_clk_fpll *pll = to_clk_fpll(clk); + ulong parent_rate = clk_get_parent_rate(clk); + u32 pre_div, post_div, div; + u32 pre_div_sel, post_div_sel, div_sel; + u32 syn, syn_sel; + ulong new_rate, best_rate = 0; + u32 mult = 1; + u32 mode, ictrl; + + if (!cv1800b_clk_getbit(pll->ipll.base, &pll->syn.en)) + return cv1800b_ipll_set_rate(clk, rate); + + if (cv1800b_clk_getbit(pll->ipll.base, &pll->syn.clk_half)) + mult = 2; + + FOR_RANGE(pre_div, PLL_PRE_DIV) + { + FOR_RANGE(post_div, PLL_POST_DIV) + { + FOR_RANGE(div, PLL_DIV) + { + new_rate = cv1800b_find_syn(rate, parent_rate, pre_div, post_div, + div, &syn); + if (rate - new_rate < rate - best_rate) { + best_rate = new_rate; + pre_div_sel = pre_div; + post_div_sel = post_div; + div_sel = div; + syn_sel = syn; + } + } + } + } + + FOR_RANGE(mode, PLL_MODE) + { + FOR_RANGE(ictrl, PLL_ICTRL) + { + u32 test = 184 * (1 + mode) * (1 + ictrl) / 2; + + if (test > 10 * div_sel && test <= 24 * div_sel) { + u32 val = FIELD_PREP(PLL_PRE_DIV_SEL, pre_div_sel) | + FIELD_PREP(PLL_POST_DIV_SEL, post_div_sel) | + FIELD_PREP(PLL_DIV_SEL, div_sel) | + FIELD_PREP(PLL_ICTRL, ictrl) | + FIELD_PREP(PLL_SEL_MODE, mode); + clrsetbits_le32(pll->ipll.base + pll->ipll.pll_reg, PLL_MASK_ALL, + val); + writel(syn_sel, pll->ipll.base + pll->syn.set); + return best_rate; + } + } + } + + return -EINVAL; +} + +static int cv1800b_fpll_set_parent(struct clk *clk, struct clk *parent) +{ + struct cv1800b_clk_fpll *pll = to_clk_fpll(clk); + + if (parent->id == CV1800B_CLK_BYPASS) + cv1800b_clk_setbit(pll->ipll.base, &pll->syn.en); + else + cv1800b_clk_clrbit(pll->ipll.base, &pll->syn.en); + + return 0; +} + +const struct clk_ops cv1800b_fpll_ops = { + .enable = cv1800b_ipll_enable, + .disable = cv1800b_ipll_disable, + .get_rate = cv1800b_fpll_get_rate, + .set_rate = cv1800b_fpll_set_rate, + .set_parent = cv1800b_fpll_set_parent, +}; + +U_BOOT_DRIVER(cv1800b_clk_fpll) = { + .name = "cv1800b_clk_fpll", + .id = UCLASS_CLK, + .ops = &cv1800b_fpll_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/clk/sophgo/clk-pll.h b/drivers/clk/sophgo/clk-pll.h new file mode 100644 index 00000000000..bea9bd8a437 --- /dev/null +++ b/drivers/clk/sophgo/clk-pll.h @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com> + * + */ + +#ifndef __clk_SOPHGO_PLL_H__ +#define __clk_SOPHGO_PLL_H__ + +#include <clk.h> + +#include "clk-common.h" + +struct cv1800b_clk_synthesizer { + struct cv1800b_clk_regbit en; + struct cv1800b_clk_regbit clk_half; + u32 ctrl; + u32 set; +}; + +struct cv1800b_clk_ipll { + struct clk clk; + const char *name; + const char *parent_name; + void __iomem *base; + u32 pll_reg; + struct cv1800b_clk_regbit pll_pwd; + struct cv1800b_clk_regbit pll_status; +}; + +struct cv1800b_clk_fpll { + struct cv1800b_clk_ipll ipll; + struct cv1800b_clk_synthesizer syn; +}; + +#define CV1800B_IPLL(_id, _name, _parent_name, _pll_reg, _pll_pwd_offset, \ + _pll_pwd_shift, _pll_status_offset, _pll_status_shift, \ + _flags) \ + { \ + .clk = { \ + .id = CV1800B_CLK_ID_TRANSFORM(_id), \ + .flags = _flags, \ + }, \ + .name = _name, \ + .parent_name = _parent_name, \ + .pll_reg = _pll_reg, \ + .pll_pwd = CV1800B_CLK_REGBIT(_pll_pwd_offset, _pll_pwd_shift), \ + .pll_status = CV1800B_CLK_REGBIT(_pll_status_offset, \ + _pll_status_shift), \ + } + +#define CV1800B_FPLL(_id, _name, _parent_name, _pll_reg, _pll_pwd_offset, \ + _pll_pwd_shift, _pll_status_offset, _pll_status_shift, \ + _syn_en_offset, _syn_en_shift, _syn_clk_half_offset, \ + _syn_clk_half_shift, _syn_ctrl_offset, _syn_set_offset, \ + _flags) \ + { \ + .ipll = CV1800B_IPLL(_id, _name, _parent_name, _pll_reg, \ + _pll_pwd_offset, _pll_pwd_shift, \ + _pll_status_offset, _pll_status_shift, \ + _flags), \ + .syn = { \ + .en = CV1800B_CLK_REGBIT(_syn_en_offset, _syn_en_shift),\ + .clk_half = CV1800B_CLK_REGBIT(_syn_clk_half_offset, \ + _syn_clk_half_shift), \ + .ctrl = _syn_ctrl_offset, \ + .set = _syn_set_offset, \ + }, \ + } + +extern const struct clk_ops cv1800b_ipll_ops; +extern const struct clk_ops cv1800b_fpll_ops; + +#endif /* __clk_SOPHGO_PLL_H__ */ diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c index 60deca963a6..6c0a8c0cbe4 100644 --- a/drivers/cpu/imx8_cpu.c +++ b/drivers/cpu/imx8_cpu.c @@ -60,6 +60,10 @@ static const char *get_imx_type_str(u32 imxtype) return "93(12)";/* iMX93 9x9 Dual core without NPU */ case MXC_CPU_IMX9311: return "93(11)";/* iMX93 9x9 Single core without NPU */ + case MXC_CPU_IMX9302: + return "93(02)";/* iMX93 900Mhz Low performance Dual core without NPU */ + case MXC_CPU_IMX9301: + return "93(01)";/* iMX93 900Mhz Low performance Single core without NPU */ default: return "??"; } diff --git a/drivers/crypto/aspeed/Kconfig b/drivers/crypto/aspeed/Kconfig index 9bf317177aa..473e3e5a863 100644 --- a/drivers/crypto/aspeed/Kconfig +++ b/drivers/crypto/aspeed/Kconfig @@ -18,3 +18,13 @@ config ASPEED_ACRY Enabling this allows the use of RSA/ECC operations in hardware without requiring the software implementations. It also improves performance and saves code size. + +config ASPEED_CPTRA_SHA + bool "Caliptra SHA ACC for Aspeed AST27xx SoCs" + depends on DM_HASH + help + Select this option to enable a driver for using the SHA accelerator provided + by Caliptra 1.0, which is integrated in AST27xx BMC SoCs. + + Enabling this allows the use of SHA operations in hardware. Note that only + SHA384 and SHA512 are supported by Caliptra 1.0. diff --git a/drivers/crypto/aspeed/Makefile b/drivers/crypto/aspeed/Makefile index 58b55fc46e4..570587e744f 100644 --- a/drivers/crypto/aspeed/Makefile +++ b/drivers/crypto/aspeed/Makefile @@ -1,2 +1,3 @@ obj-$(CONFIG_ASPEED_HACE) += aspeed_hace.o obj-$(CONFIG_ASPEED_ACRY) += aspeed_acry.o +obj-$(CONFIG_ASPEED_CPTRA_SHA) += cptra_sha.o diff --git a/drivers/crypto/aspeed/cptra_sha.c b/drivers/crypto/aspeed/cptra_sha.c new file mode 100644 index 00000000000..26b97bdd92b --- /dev/null +++ b/drivers/crypto/aspeed/cptra_sha.c @@ -0,0 +1,258 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2024 ASPEED Technology Inc. + */ +#include <asm/io.h> +#include <config.h> +#include <dm.h> +#include <linux/bitfield.h> +#include <linux/bitops.h> +#include <linux/iopoll.h> +#include <malloc.h> +#include <u-boot/hash.h> +#include <watchdog.h> + +/* SHA register offsets */ +#define CPTRA_SHA_LOCK 0x00 +#define CPTRA_SHA_USER 0x04 +#define CPTRA_SHA_MODE 0x08 +#define CPTRA_SHA_MODE_ENDIAN BIT(2) +#define CPTRA_SHA_MODE_SEL GENMASK(1, 0) +#define CPTRA_SHA_DLEN 0x10 +#define CPTRA_SHA_DATAIN 0x14 +#define CPTRA_SHA_EXEC 0x18 +#define CPTRA_SHA_STS 0x1c +#define CPTRA_SHA_STS_SOC_LOCK BIT(1) +#define CPTRA_SHA_STS_VLD BIT(0) +#define CPTRA_SHA_DIGEST(n) (0x20 + ((n) << 2)) +#define CPTRA_SHA_CTRL 0x60 +#define CPTRA_SHA_CTRL_ZEROIZE BIT(0) + +enum cptra_sha_modes { + CPTRA_SHA384_STREAM, + CPTRA_SHA512_STREAM, +}; + +struct cptra_sha_ctx { + enum HASH_ALGO algo; + uint32_t dgst_len; +}; + +struct cptra_sha { + void *regs; +}; + +static int cptra_sha_init(struct udevice *dev, enum HASH_ALGO algo, void **ctxp) +{ + struct cptra_sha_ctx *cs_ctx; + struct cptra_sha *cs; + uint32_t mode; + uint32_t reg; + int rc; + + cs_ctx = malloc(sizeof(struct cptra_sha_ctx)); + if (!cs_ctx) + return -ENOMEM; + + memset(cs_ctx, 0, sizeof(struct cptra_sha_ctx)); + + cs_ctx->algo = algo; + + switch (algo) { + case HASH_ALGO_SHA384: + mode = CPTRA_SHA384_STREAM; + cs_ctx->dgst_len = 48; + break; + case HASH_ALGO_SHA512: + mode = CPTRA_SHA512_STREAM; + cs_ctx->dgst_len = 64; + break; + default: + rc = -EINVAL; + goto free_n_out; + }; + + cs = dev_get_priv(dev); + + /* get CPTRA SHA lock */ + if (readl_poll_timeout(cs->regs + CPTRA_SHA_LOCK, reg, reg == 0, 1000000)) + return -EBUSY; + + /* zero clear SHA */ + writel(CPTRA_SHA_CTRL_ZEROIZE, cs->regs + CPTRA_SHA_CTRL); + + /* zero clear length */ + writel(0x0, cs->regs + CPTRA_SHA_DLEN); + + /* set SHA mode */ + reg = readl(cs->regs + CPTRA_SHA_MODE); + reg &= ~(CPTRA_SHA_MODE_SEL); + reg |= FIELD_PREP(CPTRA_SHA_MODE_SEL, mode); + writel(reg, cs->regs + CPTRA_SHA_MODE); + + *ctxp = cs_ctx; + + return 0; + +free_n_out: + free(cs_ctx); + + return rc; +} + +static int cptra_sha_update(struct udevice *dev, void *ctx, const void *ibuf, uint32_t ilen) +{ + struct cptra_sha *cs; + uint32_t din_be; + uint32_t dlen_sum; + uint8_t *p8; + uint32_t i; + + cs = dev_get_priv(dev); + + /* update length */ + dlen_sum = readl(cs->regs + CPTRA_SHA_DLEN) + ilen; + writel(dlen_sum, cs->regs + CPTRA_SHA_DLEN); + + din_be = 0; + for (i = 0, p8 = (uint8_t *)ibuf; i < ilen; ++i) { + if (i && (i % sizeof(din_be) == 0)) { + writel(din_be, cs->regs + CPTRA_SHA_DATAIN); + din_be = 0; + } + + din_be <<= 8; + din_be |= p8[i]; + } + + if (i % sizeof(din_be)) + din_be <<= (8 * (sizeof(din_be) - (i % sizeof(din_be)))); + + writel(din_be, cs->regs + CPTRA_SHA_DATAIN); + + return 0; +} + +static int cptra_sha_finish(struct udevice *dev, void *ctx, void *obuf) +{ + struct cptra_sha_ctx *cs_ctx; + struct cptra_sha *cs; + uint32_t i, *p32; + uint32_t sts; + + cs = dev_get_priv(dev); + cs_ctx = (struct cptra_sha_ctx *)ctx; + + /* trigger SHA calculation */ + writel(0x1, cs->regs + CPTRA_SHA_EXEC); + + /* wait for completion */ + while (1) { + sts = readl(cs->regs + CPTRA_SHA_STS); + if (sts & CPTRA_SHA_STS_VLD) + break; + } + + /* get the SHA digest in big-endian */ + p32 = (uint32_t *)obuf; + for (i = 0; i < (cs_ctx->dgst_len / sizeof(*p32)); ++i, p32++) + *p32 = be32_to_cpu(readl(cs->regs + CPTRA_SHA_DIGEST(i))); + + /* release CPTRA SHA lock */ + writel(0x1, cs->regs + CPTRA_SHA_LOCK); + + free(cs_ctx); + + return 0; +} + +static int cptra_sha_digest_wd(struct udevice *dev, enum HASH_ALGO algo, + const void *ibuf, const uint32_t ilen, + void *obuf, uint32_t chunk_sz) +{ + const void *cur, *end; + uint32_t chunk; + void *ctx; + int rc; + + rc = cptra_sha_init(dev, algo, &ctx); + if (rc) + return rc; + + if (IS_ENABLED(CONFIG_HW_WATCHDOG) || CONFIG_IS_ENABLED(WATCHDOG)) { + cur = ibuf; + end = ibuf + ilen; + + while (cur < end) { + chunk = end - cur; + if (chunk > chunk_sz) + chunk = chunk_sz; + + rc = cptra_sha_update(dev, ctx, cur, chunk); + if (rc) + return rc; + + cur += chunk; + schedule(); + } + } else { + rc = cptra_sha_update(dev, ctx, ibuf, ilen); + if (rc) + return rc; + } + + rc = cptra_sha_finish(dev, ctx, obuf); + if (rc) + return rc; + + return 0; +} + +static int cptra_sha_digest(struct udevice *dev, enum HASH_ALGO algo, + const void *ibuf, const uint32_t ilen, void *obuf) +{ + /* re-use the watchdog version with input length as the chunk_sz */ + return cptra_sha_digest_wd(dev, algo, ibuf, ilen, obuf, ilen); +} + +static int cptra_sha_probe(struct udevice *dev) +{ + struct cptra_sha *cs = dev_get_priv(dev); + + cs->regs = (void *)devfdt_get_addr(dev); + if (cs->regs == (void *)FDT_ADDR_T_NONE) { + debug("cannot map Caliptra SHA ACC registers\n"); + return -ENODEV; + } + + return 0; +} + +static int cptra_sha_remove(struct udevice *dev) +{ + return 0; +} + +static const struct hash_ops cptra_sha_ops = { + .hash_init = cptra_sha_init, + .hash_update = cptra_sha_update, + .hash_finish = cptra_sha_finish, + .hash_digest_wd = cptra_sha_digest_wd, + .hash_digest = cptra_sha_digest, +}; + +static const struct udevice_id cptra_sha_ids[] = { + { .compatible = "aspeed,ast2700-cptra-sha" }, + { } +}; + +U_BOOT_DRIVER(aspeed_cptra_sha) = { + .name = "aspeed_cptra_sha", + .id = UCLASS_HASH, + .of_match = cptra_sha_ids, + .ops = &cptra_sha_ops, + .probe = cptra_sha_probe, + .remove = cptra_sha_remove, + .priv_auto = sizeof(struct cptra_sha), + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/ddr/imx/phy/ddrphy_utils.c b/drivers/ddr/imx/phy/ddrphy_utils.c index cf5bdad7abe..14278f5ad8f 100644 --- a/drivers/ddr/imx/phy/ddrphy_utils.c +++ b/drivers/ddr/imx/phy/ddrphy_utils.c @@ -148,6 +148,10 @@ void ddrphy_init_set_dfi_clk(unsigned int drate) dram_pll_init(MHZ(266)); dram_disable_bypass(); break; + case 933: + dram_pll_init(MHZ(233)); + dram_disable_bypass(); + break; case 667: dram_pll_init(MHZ(167)); dram_disable_bypass(); diff --git a/drivers/dfu/Kconfig b/drivers/dfu/Kconfig index 971204758aa..aadd7e8cf7f 100644 --- a/drivers/dfu/Kconfig +++ b/drivers/dfu/Kconfig @@ -7,7 +7,7 @@ config DFU config DFU_OVER_USB bool select HASH - depends on USB_GADGET + depends on USB_GADGET_DOWNLOAD config DFU_OVER_TFTP bool diff --git a/drivers/firmware/arm-ffa/arm-ffa-uclass.c b/drivers/firmware/arm-ffa/arm-ffa-uclass.c index e0767fc7551..96c64964bb7 100644 --- a/drivers/firmware/arm-ffa/arm-ffa-uclass.c +++ b/drivers/firmware/arm-ffa/arm-ffa-uclass.c @@ -11,7 +11,7 @@ #include <log.h> #include <malloc.h> #include <string.h> -#include <uuid.h> +#include <u-boot/uuid.h> #include <asm/global_data.h> #include <dm/device-internal.h> #include <dm/devres.h> diff --git a/drivers/iommu/qcom-hyp-smmu.c b/drivers/iommu/qcom-hyp-smmu.c index 7b646d840dd..1b5a09bb7b3 100644 --- a/drivers/iommu/qcom-hyp-smmu.c +++ b/drivers/iommu/qcom-hyp-smmu.c @@ -381,6 +381,7 @@ static struct iommu_ops qcom_smmu_ops = { static const struct udevice_id qcom_smmu500_ids[] = { { .compatible = "qcom,sdm845-smmu-500" }, + { .compatible = "qcom,sc7280-smmu-500" }, { .compatible = "qcom,smmu-500", }, { /* sentinel */ } }; diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index e8870e30689..d4f2fd5bf89 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -3039,6 +3039,20 @@ static int mmc_complete_init(struct mmc *mmc) return err; } +static void __maybe_unused mmc_cyclic_cd_poll(struct cyclic_info *c) +{ + struct mmc *m = CONFIG_IS_ENABLED(CYCLIC, (container_of(c, struct mmc, cyclic)), (NULL)); + + if (!m->has_init) + return; + + if (mmc_getcd(m)) + return; + + mmc_deinit(m); + m->has_init = 0; +} + int mmc_init(struct mmc *mmc) { int err = 0; @@ -3061,6 +3075,14 @@ int mmc_init(struct mmc *mmc) if (err) pr_info("%s: %d, time %lu\n", __func__, err, get_timer(start)); + if (CONFIG_IS_ENABLED(CYCLIC, (!mmc->cyclic.func), (NULL))) { + /* Register cyclic function for card detect polling */ + CONFIG_IS_ENABLED(CYCLIC, (cyclic_register(&mmc->cyclic, + mmc_cyclic_cd_poll, + 100 * 1000, + mmc->cfg->name))); + } + return err; } @@ -3068,6 +3090,9 @@ int mmc_deinit(struct mmc *mmc) { u32 caps_filtered; + if (CONFIG_IS_ENABLED(CYCLIC, (mmc->cyclic.func), (NULL))) + CONFIG_IS_ENABLED(CYCLIC, (cyclic_unregister(&mmc->cyclic))); + if (!CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) && !CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) && !CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)) diff --git a/drivers/mmc/msm_sdhci.c b/drivers/mmc/msm_sdhci.c index f5e9930c799..4e5c932c071 100644 --- a/drivers/mmc/msm_sdhci.c +++ b/drivers/mmc/msm_sdhci.c @@ -32,6 +32,8 @@ #define SDCC_MCI_STATUS2_MCI_ACT 0x1 #define SDCC_MCI_HC_MODE 0x78 +#define CORE_VENDOR_SPEC_POR_VAL 0xa9c + struct msm_sdhc_plat { struct mmc_config cfg; struct mmc mmc; @@ -46,6 +48,7 @@ struct msm_sdhc { struct msm_sdhc_variant_info { bool mci_removed; + u32 core_vendor_spec; u32 core_vendor_spec_capabilities0; }; @@ -54,11 +57,14 @@ DECLARE_GLOBAL_DATA_PTR; static int msm_sdc_clk_init(struct udevice *dev) { struct msm_sdhc *prv = dev_get_priv(dev); + const struct msm_sdhc_variant_info *var_info; ofnode node = dev_ofnode(dev); ulong clk_rate; int ret, i = 0, n_clks; const char *clk_name; + var_info = (void *)dev_get_driver_data(dev); + ret = ofnode_read_u32(node, "clock-frequency", (uint *)(&clk_rate)); if (ret) clk_rate = 201500000; @@ -105,6 +111,9 @@ static int msm_sdc_clk_init(struct udevice *dev) return -EINVAL; } + writel_relaxed(CORE_VENDOR_SPEC_POR_VAL, + prv->host.ioaddr + var_info->core_vendor_spec); + return 0; } @@ -254,12 +263,14 @@ static int msm_sdc_bind(struct udevice *dev) static const struct msm_sdhc_variant_info msm_sdhc_mci_var = { .mci_removed = false, + .core_vendor_spec = 0x10c, .core_vendor_spec_capabilities0 = 0x11c, }; static const struct msm_sdhc_variant_info msm_sdhc_v5_var = { .mci_removed = true, + .core_vendor_spec = 0x20c, .core_vendor_spec_capabilities0 = 0x21c, }; diff --git a/drivers/mmc/snps_dw_mmc.c b/drivers/mmc/snps_dw_mmc.c index f30331e51f7..47ab5654bd6 100644 --- a/drivers/mmc/snps_dw_mmc.c +++ b/drivers/mmc/snps_dw_mmc.c @@ -12,6 +12,7 @@ #include <dwmmc.h> #include <errno.h> #include <fdtdec.h> +#include <asm/gpio.h> #include <dm/device_compat.h> #include <linux/libfdt.h> #include <linux/err.h> @@ -29,6 +30,7 @@ struct snps_dwmci_plat { struct snps_dwmci_priv_data { struct dwmci_host host; u32 f_max; + struct gpio_desc cd_gpio; }; static int snps_dwmmc_clk_setup(struct udevice *dev) @@ -104,6 +106,10 @@ static int snps_dwmmc_of_to_plat(struct udevice *dev) if (!ret && priv->f_max < CLOCK_MIN) return -EINVAL; + if (CONFIG_IS_ENABLED(DM_GPIO)) + gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, + GPIOD_IS_IN); + host->fifo_mode = dev_read_bool(dev, "fifo-mode"); host->name = dev->name; host->dev_index = 0; @@ -117,6 +123,9 @@ int snps_dwmmc_getcd(struct udevice *dev) struct snps_dwmci_priv_data *priv = dev_get_priv(dev); struct dwmci_host *host = &priv->host; + if (CONFIG_IS_ENABLED(DM_GPIO) && dm_gpio_is_valid(&priv->cd_gpio)) + return dm_gpio_get_value(&priv->cd_gpio); + return !(dwmci_readl(host, DWMCI_CDETECT) & 1); } diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index 28d2b456fbf..24d0556cd37 100644 --- a/drivers/mmc/zynq_sdhci.c +++ b/drivers/mmc/zynq_sdhci.c @@ -105,6 +105,19 @@ struct arasan_sdhci_priv { struct reset_ctl_bulk resets; }; +enum arasan_sdhci_compatible { + SDHCI_COMPATIBLE_SDHCI_89A, + SDHCI_COMPATIBLE_VERSAL_NET_EMMC, +}; + +static bool arasan_sdhci_is_compatible(struct udevice *dev, + enum arasan_sdhci_compatible family) +{ + enum arasan_sdhci_compatible compat = dev_get_driver_data(dev); + + return compat == family; +} + /* For Versal platforms zynqmp_mmio_write() won't be available */ __weak int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value) { @@ -422,7 +435,7 @@ static int arasan_sdhci_execute_tuning(struct mmc *mmc, u8 opcode) mdelay(1); - if (device_is_compatible(mmc->dev, "xlnx,zynqmp-8.9a")) + if (arasan_sdhci_is_compatible(mmc->dev, SDHCI_COMPATIBLE_SDHCI_89A)) arasan_zynqmp_dll_reset(host, priv->node_id); sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE); @@ -470,7 +483,7 @@ static int arasan_sdhci_execute_tuning(struct mmc *mmc, u8 opcode) udelay(1); - if (device_is_compatible(mmc->dev, "xlnx,zynqmp-8.9a")) + if (arasan_sdhci_is_compatible(mmc->dev, SDHCI_COMPATIBLE_SDHCI_89A)) arasan_zynqmp_dll_reset(host, priv->node_id); /* Enable only interrupts served by the SD controller */ @@ -858,7 +871,7 @@ static int arasan_sdhci_set_tapdelay(struct sdhci_host *host) dev_dbg(dev, "%s, host:%s, mode:%d\n", __func__, host->name, timing); if (IS_ENABLED(CONFIG_ARCH_ZYNQMP) && - device_is_compatible(dev, "xlnx,zynqmp-8.9a")) { + arasan_sdhci_is_compatible(dev, SDHCI_COMPATIBLE_SDHCI_89A)) { ret = sdhci_zynqmp_sampleclk_set_phase(host, iclk_phase); if (ret) return ret; @@ -869,7 +882,7 @@ static int arasan_sdhci_set_tapdelay(struct sdhci_host *host) } else if ((IS_ENABLED(CONFIG_ARCH_VERSAL) || IS_ENABLED(CONFIG_ARCH_VERSAL_NET) || IS_ENABLED(CONFIG_ARCH_VERSAL2)) && - device_is_compatible(dev, "xlnx,versal-8.9a")) { + arasan_sdhci_is_compatible(dev, SDHCI_COMPATIBLE_SDHCI_89A)) { ret = sdhci_versal_sampleclk_set_phase(host, iclk_phase); if (ret) return ret; @@ -879,7 +892,7 @@ static int arasan_sdhci_set_tapdelay(struct sdhci_host *host) return ret; } else if ((IS_ENABLED(CONFIG_ARCH_VERSAL_NET) || IS_ENABLED(CONFIG_ARCH_VERSAL2)) && - device_is_compatible(dev, "xlnx,versal-net-emmc")) { + arasan_sdhci_is_compatible(dev, SDHCI_COMPATIBLE_VERSAL_NET_EMMC)) { if (mmc->clock >= MIN_PHY_CLK_HZ) if (iclk_phase == VERSAL_NET_EMMC_ICLK_PHASE_DDR52_DLY_CHAIN) iclk_phase = VERSAL_NET_EMMC_ICLK_PHASE_DDR52_DLL; @@ -933,7 +946,7 @@ static void arasan_dt_parse_clk_phases(struct udevice *dev) int i; if (IS_ENABLED(CONFIG_ARCH_ZYNQMP) && - device_is_compatible(dev, "xlnx,zynqmp-8.9a")) { + arasan_sdhci_is_compatible(dev, SDHCI_COMPATIBLE_SDHCI_89A)) { for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) { clk_data->clk_phase_in[i] = zynqmp_iclk_phases[i]; clk_data->clk_phase_out[i] = zynqmp_oclk_phases[i]; @@ -948,7 +961,7 @@ static void arasan_dt_parse_clk_phases(struct udevice *dev) if ((IS_ENABLED(CONFIG_ARCH_VERSAL) || IS_ENABLED(CONFIG_ARCH_VERSAL_NET) || IS_ENABLED(CONFIG_ARCH_VERSAL2)) && - device_is_compatible(dev, "xlnx,versal-8.9a")) { + arasan_sdhci_is_compatible(dev, SDHCI_COMPATIBLE_SDHCI_89A)) { for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) { clk_data->clk_phase_in[i] = versal_iclk_phases[i]; clk_data->clk_phase_out[i] = versal_oclk_phases[i]; @@ -957,7 +970,7 @@ static void arasan_dt_parse_clk_phases(struct udevice *dev) if ((IS_ENABLED(CONFIG_ARCH_VERSAL_NET) || IS_ENABLED(CONFIG_ARCH_VERSAL2)) && - device_is_compatible(dev, "xlnx,versal-net-emmc")) { + arasan_sdhci_is_compatible(dev, SDHCI_COMPATIBLE_VERSAL_NET_EMMC)) { for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) { clk_data->clk_phase_in[i] = versal_net_emmc_iclk_phases[i]; clk_data->clk_phase_out[i] = versal_net_emmc_oclk_phases[i]; @@ -1101,7 +1114,7 @@ static int arasan_sdhci_probe(struct udevice *dev) host = priv->host; #if defined(CONFIG_ARCH_ZYNQMP) && defined(CONFIG_ZYNQMP_FIRMWARE) - if (device_is_compatible(dev, "xlnx,zynqmp-8.9a")) { + if (arasan_sdhci_is_compatible(dev, SDHCI_COMPATIBLE_SDHCI_89A)) { ret = zynqmp_pm_is_function_supported(PM_IOCTL, IOCTL_SET_SD_CONFIG); if (!ret) { @@ -1111,7 +1124,7 @@ static int arasan_sdhci_probe(struct udevice *dev) } } #endif - if (device_is_compatible(dev, "xlnx,versal-net-emmc")) + if (arasan_sdhci_is_compatible(dev, SDHCI_COMPATIBLE_VERSAL_NET_EMMC)) priv->internal_phy_reg = true; ret = clk_get_by_index(dev, 0, &clk); @@ -1145,7 +1158,7 @@ static int arasan_sdhci_probe(struct udevice *dev) host->quirks |= SDHCI_QUIRK_NO_1_8_V; if (CONFIG_IS_ENABLED(ARCH_VERSAL_NET) && - device_is_compatible(dev, "xlnx,versal-net-emmc")) + arasan_sdhci_is_compatible(dev, SDHCI_COMPATIBLE_VERSAL_NET_EMMC)) host->quirks |= SDHCI_QUIRK_CAPS_BIT63_FOR_HS400; plat->cfg.f_max = CONFIG_ZYNQ_SDHCI_MAX_FREQ; @@ -1228,8 +1241,8 @@ static int arasan_sdhci_bind(struct udevice *dev) } static const struct udevice_id arasan_sdhci_ids[] = { - { .compatible = "arasan,sdhci-8.9a" }, - { .compatible = "xlnx,versal-net-emmc" }, + { .compatible = "arasan,sdhci-8.9a", .data = SDHCI_COMPATIBLE_SDHCI_89A }, + { .compatible = "xlnx,versal-net-emmc", .data = SDHCI_COMPATIBLE_VERSAL_NET_EMMC }, { } }; diff --git a/drivers/mtd/altera_qspi.c b/drivers/mtd/altera_qspi.c index c26615821c8..e5c8df750b7 100644 --- a/drivers/mtd/altera_qspi.c +++ b/drivers/mtd/altera_qspi.c @@ -96,7 +96,7 @@ int flash_erase(flash_info_t *info, int s_first, int s_last) ret = mtd_erase(mtd, &instr); flash_set_verbose(0); if (ret) - return ERR_PROTECTED; + return FL_ERR_PROTECTED; puts(" done\n"); return 0; @@ -114,7 +114,7 @@ int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) ret = mtd_write(mtd, to, cnt, &retlen, src); if (ret) - return ERR_PROTECTED; + return FL_ERR_PROTECTED; return 0; } diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index a7826e81c17..e50502824ac 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -593,11 +593,11 @@ static int flash_status_check(flash_info_t *info, flash_sect_t sector, flash_read_long(info, sector, 0)); flash_write_cmd(info, sector, 0, info->cmd_reset); udelay(1); - return ERR_TIMEOUT; + return FL_ERR_TIMEOUT; } udelay(1); /* also triggers watchdog */ } - return ERR_OK; + return FL_ERR_OK; } /*----------------------------------------------------------------------- @@ -616,9 +616,9 @@ static int flash_full_status_check(flash_info_t *info, flash_sect_t sector, case CFI_CMDSET_INTEL_PROG_REGIONS: case CFI_CMDSET_INTEL_EXTENDED: case CFI_CMDSET_INTEL_STANDARD: - if (retcode == ERR_OK && + if (retcode == FL_ERR_OK && !flash_isset(info, sector, 0, FLASH_STATUS_DONE)) { - retcode = ERR_INVAL; + retcode = FL_ERR_INVAL; printf("Flash %s error at address %lx\n", prompt, info->start[sector]); if (flash_isset(info, sector, 0, FLASH_STATUS_ECLBS | @@ -627,14 +627,14 @@ static int flash_full_status_check(flash_info_t *info, flash_sect_t sector, } else if (flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)) { puts("Block Erase Error.\n"); - retcode = ERR_NOT_ERASED; + retcode = FL_ERR_NOT_ERASED; } else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) { puts("Locking Error\n"); } if (flash_isset(info, sector, 0, FLASH_STATUS_DPS)) { puts("Block locked.\n"); - retcode = ERR_PROTECTED; + retcode = FL_ERR_PROTECTED; } if (flash_isset(info, sector, 0, FLASH_STATUS_VPENS)) puts("Vpp Low Error.\n"); @@ -702,12 +702,12 @@ static int flash_status_poll(flash_info_t *info, void *src, void *dst, if (get_timer(start) > tout) { printf("Flash %s timeout at address %lx data %lx\n", prompt, (ulong)dst, (ulong)flash_read8(dst)); - return ERR_TIMEOUT; + return FL_ERR_TIMEOUT; } udelay(1); /* also triggers watchdog */ } #endif /* CONFIG_SYS_CFI_FLASH_STATUS_POLL */ - return ERR_OK; + return FL_ERR_OK; } /*----------------------------------------------------------------------- @@ -810,7 +810,7 @@ static int flash_write_cfiword(flash_info_t *info, ulong dest, cfiword_t cword) break; } if (!flag) - return ERR_NOT_ERASED; + return FL_ERR_NOT_ERASED; /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts(); @@ -899,7 +899,7 @@ static int flash_write_cfibuffer(flash_info_t *info, ulong dest, uchar *cp, shift = 3; break; default: - retcode = ERR_INVAL; + retcode = FL_ERR_INVAL; goto out_unmap; } @@ -930,7 +930,7 @@ static int flash_write_cfibuffer(flash_info_t *info, ulong dest, uchar *cp, } } if (!flag) { - retcode = ERR_NOT_ERASED; + retcode = FL_ERR_NOT_ERASED; goto out_unmap; } @@ -950,7 +950,7 @@ static int flash_write_cfibuffer(flash_info_t *info, ulong dest, uchar *cp, retcode = flash_status_check(info, sector, info->buffer_write_tout, "write to buffer"); - if (retcode == ERR_OK) { + if (retcode == FL_ERR_OK) { /* reduce the number of loops by the width of * the port */ @@ -975,7 +975,7 @@ static int flash_write_cfibuffer(flash_info_t *info, ulong dest, uchar *cp, src += 8, dst += 8; break; default: - retcode = ERR_INVAL; + retcode = FL_ERR_INVAL; goto out_unmap; } } @@ -1025,7 +1025,7 @@ static int flash_write_cfibuffer(flash_info_t *info, ulong dest, uchar *cp, } break; default: - retcode = ERR_INVAL; + retcode = FL_ERR_INVAL; goto out_unmap; } @@ -1043,7 +1043,7 @@ static int flash_write_cfibuffer(flash_info_t *info, ulong dest, uchar *cp, default: debug("Unknown Command Set\n"); - retcode = ERR_INVAL; + retcode = FL_ERR_INVAL; break; } @@ -1389,7 +1389,7 @@ int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) if (i > cnt) i = cnt; rc = flash_write_cfibuffer(info, wp, src, i); - if (rc != ERR_OK) + if (rc != FL_ERR_OK) return rc; i -= i & (info->portwidth - 1); wp += i; @@ -1398,7 +1398,7 @@ int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) FLASH_SHOW_PROGRESS(scale, dots, digit, i); /* Only check every once in a while */ if ((cnt & 0xFFFF) < buffered_size && ctrlc()) - return ERR_ABORTED; + return FL_ERR_ABORTED; } #else while (cnt >= info->portwidth) { @@ -1413,7 +1413,7 @@ int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) FLASH_SHOW_PROGRESS(scale, dots, digit, info->portwidth); /* Only check every once in a while */ if ((cnt & 0xFFFF) < info->portwidth && ctrlc()) - return ERR_ABORTED; + return FL_ERR_ABORTED; } #endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ diff --git a/drivers/mtd/nvmxip/nvmxip-uclass.c b/drivers/mtd/nvmxip/nvmxip-uclass.c index 254f04e0b99..d18bd0e3d6b 100644 --- a/drivers/mtd/nvmxip/nvmxip-uclass.c +++ b/drivers/mtd/nvmxip/nvmxip-uclass.c @@ -47,19 +47,13 @@ int nvmxip_probe(struct udevice *udev) return ret; } - log_info("[%s]: the block device %s ready for use\n", udev->name, bdev_name); + log_debug("[%s]: the block device %s ready for use\n", udev->name, + bdev_name); return 0; } -static int nvmxip_post_bind(struct udevice *udev) -{ - dev_or_flags(udev, DM_FLAG_PROBE_AFTER_BIND); - return 0; -} - UCLASS_DRIVER(nvmxip) = { .name = "nvmxip", .id = UCLASS_NVMXIP, - .post_bind = nvmxip_post_bind, }; diff --git a/drivers/mtd/renesas_rpc_hf.c b/drivers/mtd/renesas_rpc_hf.c index 941f2040983..03545822b07 100644 --- a/drivers/mtd/renesas_rpc_hf.c +++ b/drivers/mtd/renesas_rpc_hf.c @@ -387,6 +387,7 @@ static int rpc_hf_probe(struct udevice *dev) static const struct udevice_id rpc_hf_ids[] = { { .compatible = "renesas,r7s72100-rpc-if" }, { .compatible = "renesas,rcar-gen3-rpc-if" }, + { .compatible = "renesas,rcar-gen4-rpc-if" }, {} }; diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index aea611fef52..8f7a77e7169 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -44,6 +44,12 @@ #define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ) +/* + * For full-chip erase, calibrated to a 2MB flash (M25P16); should be scaled up + * for larger flash + */ +#define CHIP_ERASE_2MB_READY_WAIT_JIFFIES (40UL * HZ) + #define ROUND_UP_TO(x, y) (((x) + (y) - 1) / (y) * (y)) struct sfdp_parameter_header { @@ -855,6 +861,20 @@ static int spi_nor_wait_till_ready(struct spi_nor *nor) DEFAULT_READY_WAIT_JIFFIES); } +static int spi_nor_erase_chip_wait_till_ready(struct spi_nor *nor, unsigned long size) +{ + /* + * Scale the timeout linearly with the size of the flash, with + * a minimum calibrated to an old 2MB flash. We could try to + * pull these from CFI/SFDP, but these values should be good + * enough for now. + */ + unsigned long timeout = max(CHIP_ERASE_2MB_READY_WAIT_JIFFIES, + CHIP_ERASE_2MB_READY_WAIT_JIFFIES * + (unsigned long)(size / SZ_2M)); + return spi_nor_wait_till_ready_with_timeout(nor, timeout); +} + #ifdef CONFIG_SPI_FLASH_BAR /* * This "clean_bar" is necessary in a situation when one was accessing @@ -989,7 +1009,7 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) { struct spi_nor *nor = mtd_to_spi_nor(mtd); bool addr_known = false; - u32 addr, len, rem; + u32 addr, len, rem, max_size; int ret, err; dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr, @@ -1003,6 +1023,7 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) addr = instr->addr; len = instr->len; + max_size = instr->len; instr->state = MTD_ERASING; addr_known = true; @@ -1035,7 +1056,13 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) addr += ret; len -= ret; - ret = spi_nor_wait_till_ready(nor); + if (max_size == mtd->size && + !(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) { + ret = spi_nor_erase_chip_wait_till_ready(nor, mtd->size); + } else { + ret = spi_nor_wait_till_ready(nor); + } + if (ret) goto erase_err; } diff --git a/drivers/mux/mmio.c b/drivers/mux/mmio.c index e1125458a62..e06f4462b5a 100644 --- a/drivers/mux/mmio.c +++ b/drivers/mux/mmio.c @@ -31,6 +31,7 @@ static const struct mux_control_ops mux_mmio_ops = { static const struct udevice_id mmio_mux_of_match[] = { { .compatible = "mmio-mux" }, + { .compatible = "reg-mux" }, { /* sentinel */ }, }; @@ -45,7 +46,11 @@ static int mmio_mux_probe(struct udevice *dev) int ret; int i; - regmap = syscon_node_to_regmap(dev_ofnode(dev->parent)); + if (ofnode_device_is_compatible(dev_ofnode(dev), "mmio-mux")) + regmap = syscon_node_to_regmap(dev_ofnode(dev->parent)); + else + regmap_init_mem(dev_ofnode(dev), ®map); + if (IS_ERR(regmap)) { ret = PTR_ERR(regmap); dev_err(dev, "failed to get regmap: %d\n", ret); diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 6ed325517c0..e7d0ddfe25a 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -468,6 +468,7 @@ config FTMAC100 config FTGMAC100 bool "Ftgmac100 Ethernet Support" select PHYLIB + depends on NET help This driver supports the Faraday's FTGMAC100 Gigabit SoC Ethernet controller that can be found on Aspeed SoCs (which diff --git a/drivers/net/aspeed_mdio.c b/drivers/net/aspeed_mdio.c index f2e4392aa9a..2e1f3cdf11a 100644 --- a/drivers/net/aspeed_mdio.c +++ b/drivers/net/aspeed_mdio.c @@ -113,6 +113,7 @@ static int aspeed_mdio_probe(struct udevice *dev) static const struct udevice_id aspeed_mdio_ids[] = { { .compatible = "aspeed,ast2600-mdio" }, + { .compatible = "aspeed,ast2700-mdio" }, { } }; diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 0a0d92bc2cd..d6d5cb52fdd 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -615,8 +615,7 @@ static int fecmxc_init(struct udevice *dev) if (fec->xcv_type != SEVENWIRE) miiphy_restart_aneg(dev); #endif - fec_open(dev); - return 0; + return fec_open(dev); } /** @@ -818,6 +817,9 @@ static int fecmxc_recv(struct udevice *dev, int flags, uchar **packetp) return -ENOMEM; } + if (!(readl(&fec->eth->ecntrl) & FEC_ECNTRL_ETHER_EN)) + return 0; + /* Check if any critical events have happened */ ievent = readl(&fec->eth->ievent); writel(ievent, &fec->eth->ievent); @@ -1210,10 +1212,13 @@ static int fecmxc_set_ref_clk(struct clk *clk_ref, phy_interface_t interface) else if (interface == PHY_INTERFACE_MODE_RGMII || interface == PHY_INTERFACE_MODE_RGMII_ID || interface == PHY_INTERFACE_MODE_RGMII_RXID || - interface == PHY_INTERFACE_MODE_RGMII_TXID) + interface == PHY_INTERFACE_MODE_RGMII_TXID) { freq = 125000000; - else + if (is_imx93()) + freq = freq << 1; + } else { return -EINVAL; + } ret = clk_set_rate(clk_ref, freq); if (ret < 0) diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c index 19f3f0fef07..63fe4b2d33c 100644 --- a/drivers/net/fm/eth.c +++ b/drivers/net/fm/eth.c @@ -26,7 +26,8 @@ #include "fm.h" -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) && !defined(BITBANGMII) +#if ((defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) && \ + !defined(CONFIG_BITBANGMII)) #define TBIANA_SETTINGS (TBIANA_ASYMMETRIC_PAUSE | TBIANA_SYMMETRIC_PAUSE | \ TBIANA_FULL_DUPLEX) @@ -701,8 +702,11 @@ static int init_phy(struct fm_eth *fm_eth) supported |= SUPPORTED_2500baseX_Full; #endif +#if (CONFIG_IS_ENABLED(MII) || CONFIG_IS_ENABLED(CMD_MII)) && \ + !CONFIG_IS_ENABLED(BITBANGMII) if (fm_eth->type == FM_ETH_1G_E) dtsec_init_phy(fm_eth); +#endif #ifdef CONFIG_PHYLIB #ifdef CONFIG_DM_MDIO diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c index 8781e50a48d..f5ea2e72d1b 100644 --- a/drivers/net/ftgmac100.c +++ b/drivers/net/ftgmac100.c @@ -26,6 +26,7 @@ #include <linux/io.h> #include <linux/iopoll.h> #include <linux/printk.h> +#include <linux/bitfield.h> #include "ftgmac100.h" @@ -57,6 +58,15 @@ enum ftgmac100_model { FTGMAC100_MODEL_FARADAY, FTGMAC100_MODEL_ASPEED, + FTGMAC100_MODEL_ASPEED_AST2700, +}; + +union ftgmac100_dma_addr { + dma_addr_t addr; + struct { + u32 lo; + u32 hi; + }; }; /** @@ -96,6 +106,8 @@ struct ftgmac100_data { /* End of RX/TX ring buffer bits. Depend on model */ u32 rxdes0_edorr_mask; u32 txdes0_edotr_mask; + + bool is_ast2700; }; /* @@ -222,7 +234,7 @@ static int ftgmac100_phy_init(struct udevice *dev) struct phy_device *phydev; int ret; - if (IS_ENABLED(CONFIG_DM_MDIO)) + if (IS_ENABLED(CONFIG_DM_MDIO) && priv->phy_mode != PHY_INTERFACE_MODE_NCSI) phydev = dm_eth_phy_connect(dev); else phydev = phy_connect(priv->bus, priv->phy_addr, dev, priv->phy_mode); @@ -320,8 +332,9 @@ static int ftgmac100_start(struct udevice *dev) struct eth_pdata *plat = dev_get_plat(dev); struct ftgmac100_data *priv = dev_get_priv(dev); struct ftgmac100 *ftgmac100 = priv->iobase; + union ftgmac100_dma_addr dma_addr = {.hi = 0, .lo = 0}; struct phy_device *phydev = priv->phydev; - unsigned int maccr; + unsigned int maccr, dblac, desc_size; ulong start, end; int ret; int i; @@ -341,6 +354,7 @@ static int ftgmac100_start(struct udevice *dev) priv->rx_index = 0; for (i = 0; i < PKTBUFSTX; i++) { + priv->txdes[i].txdes2 = 0; priv->txdes[i].txdes3 = 0; priv->txdes[i].txdes0 = 0; } @@ -351,7 +365,14 @@ static int ftgmac100_start(struct udevice *dev) flush_dcache_range(start, end); for (i = 0; i < PKTBUFSRX; i++) { - priv->rxdes[i].rxdes3 = (unsigned int)net_rx_packets[i]; + unsigned int ip_align = 0; + + dma_addr.addr = (dma_addr_t)net_rx_packets[i]; + priv->rxdes[i].rxdes2 = FIELD_PREP(FTGMAC100_RXDES2_RXBUF_BADR_HI, dma_addr.hi); + /* For IP alignment */ + if ((dma_addr.lo & (PKTALIGN - 1)) == 0) + ip_align = 2; + priv->rxdes[i].rxdes3 = dma_addr.lo + ip_align; priv->rxdes[i].rxdes0 = 0; } priv->rxdes[PKTBUFSRX - 1].rxdes0 = priv->rxdes0_edorr_mask; @@ -361,10 +382,25 @@ static int ftgmac100_start(struct udevice *dev) flush_dcache_range(start, end); /* transmit ring */ - writel((u32)priv->txdes, &ftgmac100->txr_badr); + dma_addr.addr = (dma_addr_t)priv->txdes; + writel(dma_addr.lo, &ftgmac100->txr_badr); + writel(dma_addr.hi, &ftgmac100->txr_badr_hi); /* receive ring */ - writel((u32)priv->rxdes, &ftgmac100->rxr_badr); + dma_addr.addr = (dma_addr_t)priv->rxdes; + writel(dma_addr.lo, &ftgmac100->rxr_badr); + writel(dma_addr.hi, &ftgmac100->rxr_badr_hi); + + /* Configure TX/RX decsriptor size + * This size is calculated based on cache line. + */ + desc_size = ARCH_DMA_MINALIGN / FTGMAC100_DESC_UNIT; + /* The descriptor size is at least 2 descriptor units. */ + if (desc_size < 2) + desc_size = 2; + dblac = readl(&ftgmac100->dblac) & ~GENMASK(19, 12); + dblac |= FTGMAC100_DBLAC_RXDES_SIZE(desc_size) | FTGMAC100_DBLAC_TXDES_SIZE(desc_size); + writel(dblac, &ftgmac100->dblac); /* poll receive descriptor automatically */ writel(FTGMAC100_APTC_RXPOLL_CNT(1), &ftgmac100->aptc); @@ -382,6 +418,10 @@ static int ftgmac100_start(struct udevice *dev) FTGMAC100_MACCR_RX_RUNT | FTGMAC100_MACCR_RX_BROADPKT; + if (priv->is_ast2700 && (priv->phydev->interface == PHY_INTERFACE_MODE_RMII || + priv->phydev->interface == PHY_INTERFACE_MODE_NCSI)) + maccr |= FTGMAC100_MACCR_RMII_ENABLE; + writel(maccr, &ftgmac100->maccr); ret = phy_startup(phydev); @@ -410,6 +450,14 @@ static int ftgmac100_free_pkt(struct udevice *dev, uchar *packet, int length) ulong des_end = des_start + roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN); + /* + * Make sure there are no stale data in write-back over this area, which + * might get written into the memory while the ftgmac100 also writes + * into the same memory area. + */ + flush_dcache_range((ulong)net_rx_packets[priv->rx_index], + (ulong)net_rx_packets[priv->rx_index] + PKTSIZE_ALIGN); + /* Release buffer to DMA and flush descriptor */ curr_des->rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY; flush_dcache_range(des_start, des_end); @@ -431,9 +479,11 @@ static int ftgmac100_recv(struct udevice *dev, int flags, uchar **packetp) ulong des_start = ((ulong)curr_des) & ~(ARCH_DMA_MINALIGN - 1); ulong des_end = des_start + roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN); - ulong data_start = curr_des->rxdes3; + union ftgmac100_dma_addr data_start = { .lo = 0, .hi = 0 }; ulong data_end; + data_start.hi = FIELD_GET(FTGMAC100_RXDES2_RXBUF_BADR_HI, curr_des->rxdes2); + data_start.lo = curr_des->rxdes3; invalidate_dcache_range(des_start, des_end); if (!(curr_des->rxdes0 & FTGMAC100_RXDES0_RXPKT_RDY)) @@ -453,9 +503,9 @@ static int ftgmac100_recv(struct udevice *dev, int flags, uchar **packetp) __func__, priv->rx_index, rxlen); /* Invalidate received data */ - data_end = data_start + roundup(rxlen, ARCH_DMA_MINALIGN); - invalidate_dcache_range(data_start, data_end); - *packetp = (uchar *)data_start; + data_end = data_start.addr + roundup(rxlen, ARCH_DMA_MINALIGN); + invalidate_dcache_range(data_start.addr, data_end); + *packetp = (uchar *)data_start.addr; return rxlen; } @@ -481,6 +531,7 @@ static int ftgmac100_send(struct udevice *dev, void *packet, int length) struct ftgmac100_data *priv = dev_get_priv(dev); struct ftgmac100 *ftgmac100 = priv->iobase; struct ftgmac100_txdes *curr_des = &priv->txdes[priv->tx_index]; + union ftgmac100_dma_addr dma_addr; ulong des_start = ((ulong)curr_des) & ~(ARCH_DMA_MINALIGN - 1); ulong des_end = des_start + roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN); @@ -499,10 +550,12 @@ static int ftgmac100_send(struct udevice *dev, void *packet, int length) length = (length < ETH_ZLEN) ? ETH_ZLEN : length; - curr_des->txdes3 = (unsigned int)packet; + dma_addr.addr = (dma_addr_t)packet; + curr_des->txdes2 = FIELD_PREP(FTGMAC100_TXDES2_TXBUF_BADR_HI, dma_addr.hi); + curr_des->txdes3 = dma_addr.lo; /* Flush data to be sent */ - data_start = curr_des->txdes3; + data_start = (ulong)dma_addr.addr; data_end = data_start + roundup(length, ARCH_DMA_MINALIGN); flush_dcache_range(data_start, data_end); @@ -565,6 +618,11 @@ static int ftgmac100_of_to_plat(struct udevice *dev) if (dev_get_driver_data(dev) == FTGMAC100_MODEL_ASPEED) { priv->rxdes0_edorr_mask = BIT(30); priv->txdes0_edotr_mask = BIT(30); + priv->is_ast2700 = false; + } else if (dev_get_driver_data(dev) == FTGMAC100_MODEL_ASPEED_AST2700) { + priv->rxdes0_edorr_mask = BIT(30); + priv->txdes0_edotr_mask = BIT(30); + priv->is_ast2700 = true; } else { priv->rxdes0_edorr_mask = BIT(15); priv->txdes0_edotr_mask = BIT(15); @@ -655,10 +713,11 @@ static const struct eth_ops ftgmac100_ops = { }; static const struct udevice_id ftgmac100_ids[] = { - { .compatible = "faraday,ftgmac100", .data = FTGMAC100_MODEL_FARADAY }, - { .compatible = "aspeed,ast2500-mac", .data = FTGMAC100_MODEL_ASPEED }, - { .compatible = "aspeed,ast2600-mac", .data = FTGMAC100_MODEL_ASPEED }, - { } + { .compatible = "faraday,ftgmac100", .data = FTGMAC100_MODEL_FARADAY }, + { .compatible = "aspeed,ast2500-mac", .data = FTGMAC100_MODEL_ASPEED }, + { .compatible = "aspeed,ast2600-mac", .data = FTGMAC100_MODEL_ASPEED }, + { .compatible = "aspeed,ast2700-mac", .data = FTGMAC100_MODEL_ASPEED_AST2700 }, + {} }; U_BOOT_DRIVER(ftgmac100) = { diff --git a/drivers/net/ftgmac100.h b/drivers/net/ftgmac100.h index f7874ae68b6..c38b57c9541 100644 --- a/drivers/net/ftgmac100.h +++ b/drivers/net/ftgmac100.h @@ -66,6 +66,13 @@ struct ftgmac100 { unsigned int rx_runt; /* 0xc0 */ unsigned int rx_crcer_ftl; /* 0xc4 */ unsigned int rx_col_lost; /* 0xc8 */ + unsigned int reserved[43]; /* 0xcc - 0x174 */ + unsigned int txr_badr_lo; /* 0x178, defined in ast2700 */ + unsigned int txr_badr_hi; /* 0x17c, defined in ast2700 */ + unsigned int hptxr_badr_lo; /* 0x180, defined in ast2700 */ + unsigned int hptxr_badr_hi; /* 0x184, defined in ast2700 */ + unsigned int rxr_badr_lo; /* 0x188, defined in ast2700 */ + unsigned int rxr_badr_hi; /* 0x18c, defined in ast2700 */ }; /* @@ -111,6 +118,7 @@ struct ftgmac100 { #define FTGMAC100_DBLAC_TXBURST_SIZE(x) (((x) & 0x3) << 10) #define FTGMAC100_DBLAC_RXDES_SIZE(x) (((x) & 0xf) << 12) #define FTGMAC100_DBLAC_TXDES_SIZE(x) (((x) & 0xf) << 16) +#define FTGMAC100_DESC_UNIT 8 #define FTGMAC100_DBLAC_IFG_CNT(x) (((x) & 0x7) << 20) #define FTGMAC100_DBLAC_IFG_INC BIT(23) @@ -157,6 +165,7 @@ struct ftgmac100 { #define FTGMAC100_MACCR_RX_BROADPKT BIT(17) #define FTGMAC100_MACCR_DISCARD_CRCERR BIT(18) #define FTGMAC100_MACCR_FAST_MODE BIT(19) +#define FTGMAC100_MACCR_RMII_ENABLE BIT(20) /* defined in ast2700 */ #define FTGMAC100_MACCR_SW_RST BIT(31) /* @@ -183,7 +192,7 @@ struct ftgmac100_txdes { unsigned int txdes1; unsigned int txdes2; /* not used by HW */ unsigned int txdes3; /* TXBUF_BADR */ -} __aligned(16); +} __aligned(ARCH_DMA_MINALIGN); #define FTGMAC100_TXDES0_TXBUF_SIZE(x) ((x) & 0x3fff) #define FTGMAC100_TXDES0_EDOTR BIT(15) @@ -201,6 +210,8 @@ struct ftgmac100_txdes { #define FTGMAC100_TXDES1_TX2FIC BIT(30) #define FTGMAC100_TXDES1_TXIC BIT(31) +#define FTGMAC100_TXDES2_TXBUF_BADR_HI GENMASK(18, 16) + /* * Receive descriptor, aligned to 16 bytes */ @@ -209,7 +220,7 @@ struct ftgmac100_rxdes { unsigned int rxdes1; unsigned int rxdes2; /* not used by HW */ unsigned int rxdes3; /* RXBUF_BADR */ -} __aligned(16); +} __aligned(ARCH_DMA_MINALIGN); #define FTGMAC100_RXDES0_VDBC(x) ((x) & 0x3fff) #define FTGMAC100_RXDES0_EDORR BIT(15) @@ -240,4 +251,6 @@ struct ftgmac100_rxdes { #define FTGMAC100_RXDES1_UDP_CHKSUM_ERR BIT(26) #define FTGMAC100_RXDES1_IP_CHKSUM_ERR BIT(27) +#define FTGMAC100_RXDES2_RXBUF_BADR_HI GENMASK(18, 16) + #endif /* __FTGMAC100_H */ diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 73064b2af68..a9efc509814 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -368,6 +368,7 @@ config PHY_FIXED config PHY_NCSI bool "NC-SI based PHY" + depends on NET endif #PHYLIB diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index fe7d1084450..461805ae53f 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -228,7 +228,6 @@ struct zynq_gem_priv { struct clk tx_clk; struct clk pclk; u32 max_speed; - bool int_pcs; bool dma_64bit; u32 clk_en_info; struct reset_ctl_bulk resets; @@ -504,8 +503,7 @@ static int zynq_gem_init(struct udevice *dev) * Set SGMII enable PCS selection only if internal PCS/PMA * core is used and interface is SGMII. */ - if (priv->interface == PHY_INTERFACE_MODE_SGMII && - priv->int_pcs) { + if (priv->interface == PHY_INTERFACE_MODE_SGMII) { nwconfig |= ZYNQ_GEM_NWCFG_SGMII_ENBL | ZYNQ_GEM_NWCFG_PCS_SEL; } @@ -529,8 +527,7 @@ static int zynq_gem_init(struct udevice *dev) writel(nwcfg, ®s->nwcfg); #ifdef CONFIG_ARM64 - if (priv->interface == PHY_INTERFACE_MODE_SGMII && - priv->int_pcs) { + if (priv->interface == PHY_INTERFACE_MODE_SGMII) { /* * Disable AN for fixed link configuration, enable otherwise. * Must be written after PCS_SEL is set in nwconfig, @@ -992,8 +989,6 @@ static int zynq_gem_of_to_plat(struct udevice *dev) return -EINVAL; priv->interface = pdata->phy_interface; - priv->int_pcs = dev_read_bool(dev, "is-internal-pcspma"); - priv->clk_en_info = dev_get_driver_data(dev); return 0; diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c index f5e23f36c56..2c9d5a12127 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -1126,7 +1126,7 @@ static int cdns_sierra_phy_probe(struct udevice *dev) sp->autoconf = dev_read_bool(dev, "cdns,autoconf"); - dev_info(dev, "sierra probed\n"); + dev_dbg(dev, "sierra probed\n"); return 0; clk_disable: diff --git a/drivers/phy/phy-rcar-gen3.c b/drivers/phy/phy-rcar-gen3.c index 7c292cae0e2..b278f995f37 100644 --- a/drivers/phy/phy-rcar-gen3.c +++ b/drivers/phy/phy-rcar-gen3.c @@ -8,6 +8,7 @@ #include <clk.h> #include <div64.h> #include <dm.h> +#include <dm/device_compat.h> #include <fdtdec.h> #include <generic-phy.h> #include <malloc.h> @@ -31,8 +32,13 @@ #define USB2_LINECTRL1 0x610 #define USB2_ADPCTRL 0x630 +/* INT_ENABLE */ +#define USB2_INT_ENABLE_UCOM_INTEN BIT(3) +#define USB2_INT_ENABLE_USBH_INTB_EN BIT(2) +#define USB2_INT_ENABLE_USBH_INTA_EN BIT(1) + /* USBCTR */ -#define USB2_USBCTR_PLL_RST BIT(1) +#define USB2_USBCTR_PLL_RST BIT(1) /* SPD_RSM_TIMSET */ #define USB2_SPD_RSM_TIMSET_INIT 0x014e029b @@ -43,11 +49,23 @@ /* COMMCTRL */ #define USB2_COMMCTRL_OTG_PERI BIT(31) /* 1 = Peripheral mode */ +/* OBINTSTA and OBINTEN */ +#define USB2_OBINT_SESSVLDCHG BIT(12) +#define USB2_OBINT_IDDIGCHG BIT(11) + +/* VBCTRL */ +#define USB2_VBCTRL_DRVVBUSSEL BIT(8) + /* LINECTRL1 */ +#define USB2_LINECTRL1_DPRPD_EN BIT(19) #define USB2_LINECTRL1_DP_RPD BIT(18) +#define USB2_LINECTRL1_DMRPD_EN BIT(17) #define USB2_LINECTRL1_DM_RPD BIT(16) /* ADPCTRL */ +#define USB2_ADPCTRL_OTGSESSVLD BIT(20) +#define USB2_ADPCTRL_IDDIG BIT(19) +#define USB2_ADPCTRL_IDPULLUP BIT(5) /* 1 = ID sampling is enabled */ #define USB2_ADPCTRL_DRVVBUS BIT(4) struct rcar_gen3_phy { @@ -65,12 +83,14 @@ static int rcar_gen3_phy_phy_init(struct phy *phy) writel(USB2_SPD_RSM_TIMSET_INIT, priv->regs + USB2_SPD_RSM_TIMSET); writel(USB2_OC_TIMSET_INIT, priv->regs + USB2_OC_TIMSET); - setbits_le32(priv->regs + USB2_LINECTRL1, - USB2_LINECTRL1_DP_RPD | USB2_LINECTRL1_DM_RPD); + return 0; +} - clrbits_le32(priv->regs + USB2_COMMCTRL, USB2_COMMCTRL_OTG_PERI); +static int rcar_gen3_phy_phy_exit(struct phy *phy) +{ + struct rcar_gen3_phy *priv = dev_get_priv(phy->dev); - setbits_le32(priv->regs + USB2_ADPCTRL, USB2_ADPCTRL_DRVVBUS); + writel(0, priv->regs + USB2_INT_ENABLE); return 0; } @@ -102,10 +122,70 @@ static int rcar_gen3_phy_phy_power_off(struct phy *phy) return regulator_set_enable(priv->vbus_supply, false); } +static int rcar_gen3_phy_phy_set_mode(struct phy *phy, enum phy_mode mode, + int submode) +{ + const u32 adpdevmask = USB2_ADPCTRL_IDDIG | USB2_ADPCTRL_OTGSESSVLD; + struct rcar_gen3_phy *priv = dev_get_priv(phy->dev); + u32 adpctrl; + + if (mode == PHY_MODE_USB_OTG) { + if (submode) { + /* OTG submode is used as initialization indicator */ + writel(USB2_INT_ENABLE_UCOM_INTEN | + USB2_INT_ENABLE_USBH_INTB_EN | + USB2_INT_ENABLE_USBH_INTA_EN, + priv->regs + USB2_INT_ENABLE); + setbits_le32(priv->regs + USB2_VBCTRL, + USB2_VBCTRL_DRVVBUSSEL); + writel(USB2_OBINT_SESSVLDCHG | USB2_OBINT_IDDIGCHG, + priv->regs + USB2_OBINTSTA); + setbits_le32(priv->regs + USB2_OBINTEN, + USB2_OBINT_SESSVLDCHG | + USB2_OBINT_IDDIGCHG); + setbits_le32(priv->regs + USB2_ADPCTRL, + USB2_ADPCTRL_IDPULLUP); + clrsetbits_le32(priv->regs + USB2_LINECTRL1, + USB2_LINECTRL1_DP_RPD | + USB2_LINECTRL1_DM_RPD | + USB2_LINECTRL1_DPRPD_EN | + USB2_LINECTRL1_DMRPD_EN, + USB2_LINECTRL1_DPRPD_EN | + USB2_LINECTRL1_DMRPD_EN); + } + + adpctrl = readl(priv->regs + USB2_ADPCTRL); + if ((adpctrl & adpdevmask) == adpdevmask) + mode = PHY_MODE_USB_DEVICE; + else + mode = PHY_MODE_USB_HOST; + } + + if (mode == PHY_MODE_USB_HOST) { + clrbits_le32(priv->regs + USB2_COMMCTRL, USB2_COMMCTRL_OTG_PERI); + setbits_le32(priv->regs + USB2_LINECTRL1, + USB2_LINECTRL1_DP_RPD | USB2_LINECTRL1_DM_RPD); + setbits_le32(priv->regs + USB2_ADPCTRL, USB2_ADPCTRL_DRVVBUS); + } else if (mode == PHY_MODE_USB_DEVICE) { + setbits_le32(priv->regs + USB2_COMMCTRL, USB2_COMMCTRL_OTG_PERI); + clrsetbits_le32(priv->regs + USB2_LINECTRL1, + USB2_LINECTRL1_DP_RPD | USB2_LINECTRL1_DM_RPD, + USB2_LINECTRL1_DM_RPD); + clrbits_le32(priv->regs + USB2_ADPCTRL, USB2_ADPCTRL_DRVVBUS); + } else { + dev_err(phy->dev, "Unknown mode %d\n", mode); + return -EINVAL; + } + + return 0; +} + static const struct phy_ops rcar_gen3_phy_phy_ops = { .init = rcar_gen3_phy_phy_init, + .exit = rcar_gen3_phy_phy_exit, .power_on = rcar_gen3_phy_phy_power_on, .power_off = rcar_gen3_phy_phy_power_off, + .set_mode = rcar_gen3_phy_phy_set_mode, }; static int rcar_gen3_phy_probe(struct udevice *dev) diff --git a/drivers/phy/phy-uclass.c b/drivers/phy/phy-uclass.c index acdcda15b5b..777d952b041 100644 --- a/drivers/phy/phy-uclass.c +++ b/drivers/phy/phy-uclass.c @@ -508,7 +508,8 @@ int generic_phy_power_off_bulk(struct phy_bulk *bulk) return ret; } -int generic_setup_phy(struct udevice *dev, struct phy *phy, int index) +int generic_setup_phy(struct udevice *dev, struct phy *phy, int index, + enum phy_mode mode, int submode) { int ret; @@ -520,10 +521,18 @@ int generic_setup_phy(struct udevice *dev, struct phy *phy, int index) if (ret) return ret; + ret = generic_phy_set_mode(phy, mode, submode); + if (ret) + goto phys_mode_err; + ret = generic_phy_power_on(phy); if (ret) - generic_phy_exit(phy); + goto phys_mode_err; + + return 0; +phys_mode_err: + generic_phy_exit(phy); return ret; } diff --git a/drivers/phy/sandbox-phy.c b/drivers/phy/sandbox-phy.c index b159147a765..e70d20432e0 100644 --- a/drivers/phy/sandbox-phy.c +++ b/drivers/phy/sandbox-phy.c @@ -72,6 +72,18 @@ static int sandbox_phy_exit(struct phy *phy) return 0; } +static int +sandbox_phy_set_mode(struct phy *phy, enum phy_mode mode, int submode) +{ + if (submode) + return -EOPNOTSUPP; + + if (mode != PHY_MODE_USB_HOST) + return -EINVAL; + + return 0; +} + static int sandbox_phy_bind(struct udevice *dev) { if (dev_get_driver_data(dev) != DRIVER_DATA) @@ -96,6 +108,7 @@ static struct phy_ops sandbox_phy_ops = { .power_off = sandbox_phy_power_off, .init = sandbox_phy_init, .exit = sandbox_phy_exit, + .set_mode = sandbox_phy_set_mode, }; static const struct udevice_id sandbox_phy_ids[] = { diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c index ff49819b58d..67e564f85c3 100644 --- a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c +++ b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c @@ -48,6 +48,7 @@ #define GPIO_OES 0x70 /* Output Enable Set */ #define GPIO_OEC 0x74 /* Output Enable Clear */ +#define NPCM8XX_NUM_GPIO_BANK 8 #define NPCM8XX_GPIO_PER_BANK 32 #define GPIOX_OFFSET 16 @@ -967,6 +968,18 @@ static int npcm8xx_pinconf_set(struct udevice *dev, unsigned int selector, } #endif +static void npcm8xx_pinctrl_clear_events(struct npcm8xx_pinctrl_priv *priv) +{ + void __iomem *base; + int i; + + for (i = 0; i < NPCM8XX_NUM_GPIO_BANK; i++) { + base = priv->gpio_base + (0x1000 * i); + clrbits_le32(base + GPIO_EVEN, 0xFFFFFFFF); + setbits_le32(base + GPIO_EVST, 0xFFFFFFFF); + } +} + static struct pinctrl_ops npcm8xx_pinctrl_ops = { .set_state = pinctrl_generic_set_state, .get_pins_count = npcm8xx_get_pins_count, @@ -1001,6 +1014,11 @@ static int npcm8xx_pinctrl_probe(struct udevice *dev) if (IS_ERR(priv->rst_regmap)) return -EINVAL; + /* + * Clear all previous gpio events, otherwise it may produce + * unexpected interrupts during kernel booting. + */ + npcm8xx_pinctrl_clear_events(priv); return 0; } diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig index bc061c20d75..958f337c7e7 100644 --- a/drivers/power/regulator/Kconfig +++ b/drivers/power/regulator/Kconfig @@ -383,6 +383,15 @@ config DM_REGULATOR_TPS80031 features for TPS80031/TPS80032 PMICs. The driver implements get/set api for: value and enable. +config DM_REGULATOR_TPS6287X + bool "Enable driver for TPS6287x Power Regulator" + depends on DM_REGULATOR + help + The TPS6287X is a step down converter with a fast transient + response. This driver supports all four variants of the chip + (TPS62870, TPS62871, TPS62872, TPS62873). It implements the + get/set api for value only, as the power line is always on. + config DM_REGULATOR_STPMIC1 bool "Enable driver for STPMIC1 regulators" depends on DM_REGULATOR && PMIC_STPMIC1 @@ -402,6 +411,15 @@ config DM_REGULATOR_ANATOP regulators. It is recommended that this option be enabled on i.MX6 platform. +config SPL_DM_REGULATOR_TPS6287X + bool "Enable driver for TPS6287x Power Regulator" + depends on SPL_DM_REGULATOR + help + The TPS6287X is a step down converter with a fast transient + response. This driver supports all four variants of the chip + (TPS62870, TPS62871, TPS62872, TPS62873). It implements the + get/set api for value only, as the power line is always on. + config SPL_DM_REGULATOR_STPMIC1 bool "Enable driver for STPMIC1 regulators in SPL" depends on SPL_DM_REGULATOR && PMIC_STPMIC1 diff --git a/drivers/power/regulator/Makefile b/drivers/power/regulator/Makefile index 56a527612b7..54db0885657 100644 --- a/drivers/power/regulator/Makefile +++ b/drivers/power/regulator/Makefile @@ -35,6 +35,7 @@ obj-$(CONFIG_$(SPL_)DM_REGULATOR_STM32_VREFBUF) += stm32-vrefbuf.o obj-$(CONFIG_DM_REGULATOR_TPS65910) += tps65910_regulator.o obj-$(CONFIG_$(SPL_)DM_REGULATOR_TPS65911) += tps65911_regulator.o obj-$(CONFIG_DM_REGULATOR_TPS62360) += tps62360_regulator.o +obj-$(CONFIG_$(SPL_)DM_REGULATOR_TPS6287X) += tps6287x_regulator.o obj-$(CONFIG_$(SPL_)DM_REGULATOR_TPS80031) += tps80031_regulator.o obj-$(CONFIG_$(SPL_)DM_REGULATOR_STPMIC1) += stpmic1.o obj-$(CONFIG_DM_REGULATOR_TPS65941) += tps65941_regulator.o diff --git a/drivers/power/regulator/fixed.c b/drivers/power/regulator/fixed.c index 98c89bf2aff..996da41546a 100644 --- a/drivers/power/regulator/fixed.c +++ b/drivers/power/regulator/fixed.c @@ -17,7 +17,7 @@ #include "regulator_common.h" -struct fixed_clock_regulator_plat { +struct fixed_clock_regulator_priv { struct clk *enable_clock; unsigned int clk_enable_counter; }; @@ -83,14 +83,14 @@ static int fixed_regulator_set_enable(struct udevice *dev, bool enable) static int fixed_clock_regulator_get_enable(struct udevice *dev) { - struct fixed_clock_regulator_plat *priv = dev_get_priv(dev); + struct fixed_clock_regulator_priv *priv = dev_get_priv(dev); return priv->clk_enable_counter > 0; } static int fixed_clock_regulator_set_enable(struct udevice *dev, bool enable) { - struct fixed_clock_regulator_plat *priv = dev_get_priv(dev); + struct fixed_clock_regulator_priv *priv = dev_get_priv(dev); struct regulator_common_plat *plat = dev_get_plat(dev); int ret = 0; @@ -113,6 +113,17 @@ static int fixed_clock_regulator_set_enable(struct udevice *dev, bool enable) return ret; } +static int fixed_clock_regulator_probe(struct udevice *dev) +{ + struct fixed_clock_regulator_priv *priv = dev_get_priv(dev); + + priv->enable_clock = devm_clk_get(dev, NULL); + if (IS_ERR(priv->enable_clock)) + return PTR_ERR(priv->enable_clock); + + return 0; +} + static const struct dm_regulator_ops fixed_regulator_ops = { .get_value = fixed_regulator_get_value, .get_current = fixed_regulator_get_current, @@ -149,6 +160,8 @@ U_BOOT_DRIVER(regulator_fixed_clock) = { .id = UCLASS_REGULATOR, .ops = &fixed_clock_regulator_ops, .of_match = fixed_clock_regulator_ids, + .probe = fixed_clock_regulator_probe, .of_to_plat = fixed_regulator_of_to_plat, - .plat_auto = sizeof(struct fixed_clock_regulator_plat), + .plat_auto = sizeof(struct regulator_common_plat), + .priv_auto = sizeof(struct fixed_clock_regulator_priv), }; diff --git a/drivers/power/regulator/qcom-rpmh-regulator.c b/drivers/power/regulator/qcom-rpmh-regulator.c index 06fd3f31956..2dc261d83e3 100644 --- a/drivers/power/regulator/qcom-rpmh-regulator.c +++ b/drivers/power/regulator/qcom-rpmh-regulator.c @@ -357,6 +357,69 @@ static const struct dm_regulator_ops rpmh_regulator_vrm_drms_ops = { .get_mode = rpmh_regulator_vrm_get_mode, }; +static struct dm_regulator_mode pmic_mode_map_pmic5_bob[] = { + { + .id = REGULATOR_MODE_LPM, + .register_value = PMIC5_BOB_MODE_PFM, + .name = "PMIC5_BOB_MODE_PFM" + }, { + .id = REGULATOR_MODE_AUTO, + .register_value = PMIC5_BOB_MODE_AUTO, + .name = "PMIC5_BOB_MODE_AUTO" + }, { + .id = REGULATOR_MODE_HPM, + .register_value = PMIC5_BOB_MODE_PWM, + .name = "PMIC5_BOB_MODE_PWM" + }, +}; + +static struct dm_regulator_mode pmic_mode_map_pmic5_smps[] = { + { + .id = REGULATOR_MODE_RETENTION, + .register_value = PMIC5_SMPS_MODE_RETENTION, + .name = "PMIC5_SMPS_MODE_RETENTION" + }, { + .id = REGULATOR_MODE_LPM, + .register_value = PMIC5_SMPS_MODE_PFM, + .name = "PMIC5_SMPS_MODE_PFM" + }, { + .id = REGULATOR_MODE_AUTO, + .register_value = PMIC5_SMPS_MODE_AUTO, + .name = "PMIC5_SMPS_MODE_AUTO" + }, { + .id = REGULATOR_MODE_HPM, + .register_value = PMIC5_SMPS_MODE_PWM, + .name = "PMIC5_SMPS_MODE_PWM" + }, +}; + +static const struct rpmh_vreg_hw_data pmic5_bob = { + .regulator_type = VRM, + .ops = &rpmh_regulator_vrm_drms_ops, + .voltage_range = REGULATOR_LINEAR_RANGE(3000000, 0, 31, 32000), + .n_voltages = 32, + .pmic_mode_map = pmic_mode_map_pmic5_bob, + .n_modes = ARRAY_SIZE(pmic_mode_map_pmic5_bob), +}; + +static const struct rpmh_vreg_hw_data pmic5_ftsmps525_lv = { + .regulator_type = VRM, + .ops = &rpmh_regulator_vrm_drms_ops, + .voltage_range = REGULATOR_LINEAR_RANGE(300000, 0, 267, 4000), + .n_voltages = 268, + .pmic_mode_map = pmic_mode_map_pmic5_smps, + .n_modes = ARRAY_SIZE(pmic_mode_map_pmic5_smps), +}; + +static const struct rpmh_vreg_hw_data pmic5_ftsmps525_mv = { + .regulator_type = VRM, + .ops = &rpmh_regulator_vrm_drms_ops, + .voltage_range = REGULATOR_LINEAR_RANGE(600000, 0, 267, 8000), + .n_voltages = 268, + .pmic_mode_map = pmic_mode_map_pmic5_smps, + .n_modes = ARRAY_SIZE(pmic_mode_map_pmic5_smps), +}; + static struct dm_regulator_mode pmic_mode_map_pmic5_ldo[] = { { .id = REGULATOR_MODE_RETENTION, @@ -393,6 +456,16 @@ static const struct rpmh_vreg_hw_data pmic5_pldo_lv = { .n_modes = ARRAY_SIZE(pmic_mode_map_pmic5_ldo), }; +static const struct rpmh_vreg_hw_data pmic5_nldo515 = { + .regulator_type = VRM, + .ops = &rpmh_regulator_vrm_drms_ops, + .voltage_range = REGULATOR_LINEAR_RANGE(320000, 0, 210, 8000), + .n_voltages = 211, + .hpm_min_load_uA = 30000, + .pmic_mode_map = pmic_mode_map_pmic5_ldo, + .n_modes = ARRAY_SIZE(pmic_mode_map_pmic5_ldo), +}; + #define RPMH_VREG(_name, _resource_name, _hw_data, _supply_name) \ { \ .name = _name, \ @@ -412,6 +485,57 @@ static const struct rpmh_vreg_init_data pm8150l_vreg_data[] = { {} }; +static const struct rpmh_vreg_init_data pm8550_vreg_data[] = { + RPMH_VREG("ldo1", "ldo%s1", &pmic5_nldo515, "vdd-l1-l4-l10"), + RPMH_VREG("ldo2", "ldo%s2", &pmic5_pldo, "vdd-l2-l13-l14"), + RPMH_VREG("ldo3", "ldo%s3", &pmic5_nldo515, "vdd-l3"), + RPMH_VREG("ldo4", "ldo%s4", &pmic5_nldo515, "vdd-l1-l4-l10"), + RPMH_VREG("ldo5", "ldo%s5", &pmic5_pldo, "vdd-l5-l16"), + RPMH_VREG("ldo6", "ldo%s6", &pmic5_pldo, "vdd-l6-l7"), + RPMH_VREG("ldo7", "ldo%s7", &pmic5_pldo, "vdd-l6-l7"), + RPMH_VREG("ldo8", "ldo%s8", &pmic5_pldo, "vdd-l8-l9"), + RPMH_VREG("ldo9", "ldo%s9", &pmic5_pldo, "vdd-l8-l9"), + RPMH_VREG("ldo10", "ldo%s10", &pmic5_nldo515, "vdd-l1-l4-l10"), + RPMH_VREG("ldo11", "ldo%s11", &pmic5_nldo515, "vdd-l11"), + RPMH_VREG("ldo12", "ldo%s12", &pmic5_nldo515, "vdd-l12"), + RPMH_VREG("ldo13", "ldo%s13", &pmic5_pldo, "vdd-l2-l13-l14"), + RPMH_VREG("ldo14", "ldo%s14", &pmic5_pldo, "vdd-l2-l13-l14"), + RPMH_VREG("ldo15", "ldo%s15", &pmic5_nldo515, "vdd-l15"), + RPMH_VREG("ldo16", "ldo%s16", &pmic5_pldo, "vdd-l5-l16"), + RPMH_VREG("ldo17", "ldo%s17", &pmic5_pldo, "vdd-l17"), + RPMH_VREG("bob1", "bob%s1", &pmic5_bob, "vdd-bob1"), + RPMH_VREG("bob2", "bob%s2", &pmic5_bob, "vdd-bob2"), + {} +}; + +static const struct rpmh_vreg_init_data pm8550vs_vreg_data[] = { + RPMH_VREG("smps1", "smp%s1", &pmic5_ftsmps525_lv, "vdd-s1"), + RPMH_VREG("smps2", "smp%s2", &pmic5_ftsmps525_lv, "vdd-s2"), + RPMH_VREG("smps3", "smp%s3", &pmic5_ftsmps525_lv, "vdd-s3"), + RPMH_VREG("smps4", "smp%s4", &pmic5_ftsmps525_lv, "vdd-s4"), + RPMH_VREG("smps5", "smp%s5", &pmic5_ftsmps525_lv, "vdd-s5"), + RPMH_VREG("smps6", "smp%s6", &pmic5_ftsmps525_mv, "vdd-s6"), + RPMH_VREG("ldo1", "ldo%s1", &pmic5_nldo515, "vdd-l1"), + RPMH_VREG("ldo2", "ldo%s2", &pmic5_nldo515, "vdd-l2"), + RPMH_VREG("ldo3", "ldo%s3", &pmic5_nldo515, "vdd-l3"), + {} +}; + +static const struct rpmh_vreg_init_data pm8550ve_vreg_data[] = { + RPMH_VREG("smps1", "smp%s1", &pmic5_ftsmps525_lv, "vdd-s1"), + RPMH_VREG("smps2", "smp%s2", &pmic5_ftsmps525_lv, "vdd-s2"), + RPMH_VREG("smps3", "smp%s3", &pmic5_ftsmps525_lv, "vdd-s3"), + RPMH_VREG("smps4", "smp%s4", &pmic5_ftsmps525_mv, "vdd-s4"), + RPMH_VREG("smps5", "smp%s5", &pmic5_ftsmps525_lv, "vdd-s5"), + RPMH_VREG("smps6", "smp%s6", &pmic5_ftsmps525_lv, "vdd-s6"), + RPMH_VREG("smps7", "smp%s7", &pmic5_ftsmps525_lv, "vdd-s7"), + RPMH_VREG("smps8", "smp%s8", &pmic5_ftsmps525_lv, "vdd-s8"), + RPMH_VREG("ldo1", "ldo%s1", &pmic5_nldo515, "vdd-l1"), + RPMH_VREG("ldo2", "ldo%s2", &pmic5_nldo515, "vdd-l2"), + RPMH_VREG("ldo3", "ldo%s3", &pmic5_nldo515, "vdd-l3"), + {} +}; + /* probe an individual regulator */ static int rpmh_regulator_probe(struct udevice *dev) { @@ -526,6 +650,18 @@ static const struct udevice_id rpmh_regulator_ids[] = { .compatible = "qcom,pm8150l-rpmh-regulators", .data = (ulong)pm8150l_vreg_data, }, + { + .compatible = "qcom,pm8550-rpmh-regulators", + .data = (ulong)pm8550_vreg_data, + }, + { + .compatible = "qcom,pm8550ve-rpmh-regulators", + .data = (ulong)pm8550ve_vreg_data, + }, + { + .compatible = "qcom,pm8550vs-rpmh-regulators", + .data = (ulong)pm8550vs_vreg_data, + }, { /* sentinal */ }, }; diff --git a/drivers/power/regulator/regulator-uclass.c b/drivers/power/regulator/regulator-uclass.c index 88a8525b3c4..decd0802c84 100644 --- a/drivers/power/regulator/regulator-uclass.c +++ b/drivers/power/regulator/regulator-uclass.c @@ -55,14 +55,16 @@ int regulator_set_value(struct udevice *dev, int uV) struct dm_regulator_uclass_plat *uc_pdata; int ret, old_uV = uV, is_enabled = 0; + if (!ops || !ops->set_value) + return -ENOSYS; + uc_pdata = dev_get_uclass_plat(dev); if (uc_pdata->min_uV != -ENODATA && uV < uc_pdata->min_uV) return -EINVAL; if (uc_pdata->max_uV != -ENODATA && uV > uc_pdata->max_uV) return -EINVAL; - - if (!ops || !ops->set_value) - return -ENOSYS; + if (uV == -ENODATA) + return -EINVAL; if (uc_pdata->ramp_delay) { is_enabled = regulator_get_enable(dev); @@ -85,14 +87,16 @@ int regulator_set_suspend_value(struct udevice *dev, int uV) const struct dm_regulator_ops *ops = dev_get_driver_ops(dev); struct dm_regulator_uclass_plat *uc_pdata; + if (!ops || !ops->set_suspend_value) + return -ENOSYS; + uc_pdata = dev_get_uclass_plat(dev); if (uc_pdata->min_uV != -ENODATA && uV < uc_pdata->min_uV) return -EINVAL; if (uc_pdata->max_uV != -ENODATA && uV > uc_pdata->max_uV) return -EINVAL; - - if (!ops->set_suspend_value) - return -ENOSYS; + if (uV == -ENODATA) + return -EINVAL; return ops->set_suspend_value(dev, uV); } @@ -101,7 +105,7 @@ int regulator_get_suspend_value(struct udevice *dev) { const struct dm_regulator_ops *ops = dev_get_driver_ops(dev); - if (!ops->get_suspend_value) + if (!ops || !ops->get_suspend_value) return -ENOSYS; return ops->get_suspend_value(dev); @@ -136,14 +140,16 @@ int regulator_set_current(struct udevice *dev, int uA) const struct dm_regulator_ops *ops = dev_get_driver_ops(dev); struct dm_regulator_uclass_plat *uc_pdata; + if (!ops || !ops->set_current) + return -ENOSYS; + uc_pdata = dev_get_uclass_plat(dev); if (uc_pdata->min_uA != -ENODATA && uA < uc_pdata->min_uA) return -EINVAL; if (uc_pdata->max_uA != -ENODATA && uA > uc_pdata->max_uA) return -EINVAL; - - if (!ops || !ops->set_current) - return -ENOSYS; + if (uA == -ENODATA) + return -EINVAL; return ops->set_current(dev, uA); } @@ -210,7 +216,7 @@ int regulator_set_suspend_enable(struct udevice *dev, bool enable) { const struct dm_regulator_ops *ops = dev_get_driver_ops(dev); - if (!ops->set_suspend_enable) + if (!ops || !ops->set_suspend_enable) return -ENOSYS; return ops->set_suspend_enable(dev, enable); @@ -220,7 +226,7 @@ int regulator_get_suspend_enable(struct udevice *dev) { const struct dm_regulator_ops *ops = dev_get_driver_ops(dev); - if (!ops->get_suspend_enable) + if (!ops || !ops->get_suspend_enable) return -ENOSYS; return ops->get_suspend_enable(dev); @@ -299,7 +305,7 @@ int regulator_autoset(struct udevice *dev) if (ret == -ENOSYS) ret = 0; - if (!ret && uc_pdata->suspend_on) { + if (!ret && uc_pdata->suspend_on && uc_pdata->suspend_uV != -ENODATA) { ret = regulator_set_suspend_value(dev, uc_pdata->suspend_uV); if (ret == -ENOSYS) ret = 0; @@ -308,6 +314,11 @@ int regulator_autoset(struct udevice *dev) return ret; } + if (uc_pdata->force_off) { + ret = regulator_set_enable(dev, false); + goto out; + } + if (!uc_pdata->always_on && !uc_pdata->boot_on) { ret = -EMEDIUMTYPE; goto out; @@ -334,17 +345,6 @@ out: return ret; } -int regulator_unset(struct udevice *dev) -{ - struct dm_regulator_uclass_plat *uc_pdata; - - uc_pdata = dev_get_uclass_plat(dev); - if (uc_pdata && uc_pdata->force_off) - return regulator_set_enable(dev, false); - - return -EMEDIUMTYPE; -} - static void regulator_show(struct udevice *dev, int ret) { struct dm_regulator_uclass_plat *uc_pdata; @@ -433,6 +433,8 @@ static int regulator_post_bind(struct udevice *dev) const char *property = "regulator-name"; uc_pdata = dev_get_uclass_plat(dev); + uc_pdata->always_on = dev_read_bool(dev, "regulator-always-on"); + uc_pdata->boot_on = dev_read_bool(dev, "regulator-boot-on"); /* Regulator's mandatory constraint */ uc_pdata->name = dev_read_string(dev, property); @@ -444,13 +446,21 @@ static int regulator_post_bind(struct udevice *dev) return -EINVAL; } - if (regulator_name_is_unique(dev, uc_pdata->name)) - return 0; + if (!regulator_name_is_unique(dev, uc_pdata->name)) { + debug("'%s' of dev: '%s', has nonunique value: '%s\n", + property, dev->name, uc_pdata->name); + return -EINVAL; + } - debug("'%s' of dev: '%s', has nonunique value: '%s\n", - property, dev->name, uc_pdata->name); + /* + * In case the regulator has regulator-always-on or + * regulator-boot-on DT property, trigger probe() to + * configure its default state during startup. + */ + if (uc_pdata->always_on || uc_pdata->boot_on) + dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND); - return -EINVAL; + return 0; } static int regulator_pre_probe(struct udevice *dev) @@ -473,8 +483,6 @@ static int regulator_pre_probe(struct udevice *dev) -ENODATA); uc_pdata->max_uA = dev_read_u32_default(dev, "regulator-max-microamp", -ENODATA); - uc_pdata->always_on = dev_read_bool(dev, "regulator-always-on"); - uc_pdata->boot_on = dev_read_bool(dev, "regulator-boot-on"); uc_pdata->ramp_delay = dev_read_u32_default(dev, "regulator-ramp-delay", 0); uc_pdata->force_off = dev_read_bool(dev, "regulator-force-boot-off"); @@ -504,56 +512,18 @@ static int regulator_pre_probe(struct udevice *dev) return 0; } -int regulators_enable_boot_on(bool verbose) +static int regulator_post_probe(struct udevice *dev) { - struct udevice *dev; - struct uclass *uc; int ret; - ret = uclass_get(UCLASS_REGULATOR, &uc); - if (ret) + ret = regulator_autoset(dev); + if (ret && ret != -EMEDIUMTYPE && ret != -EALREADY && ret != ENOSYS) return ret; - for (uclass_first_device(UCLASS_REGULATOR, &dev); - dev; - uclass_next_device(&dev)) { - ret = regulator_autoset(dev); - if (ret == -EMEDIUMTYPE || ret == -EALREADY) { - ret = 0; - continue; - } - if (verbose) - regulator_show(dev, ret); - if (ret == -ENOSYS) - ret = 0; - } - - return ret; -} - -int regulators_enable_boot_off(bool verbose) -{ - struct udevice *dev; - struct uclass *uc; - int ret; - ret = uclass_get(UCLASS_REGULATOR, &uc); - if (ret) - return ret; - for (uclass_first_device(UCLASS_REGULATOR, &dev); - dev; - uclass_next_device(&dev)) { - ret = regulator_unset(dev); - if (ret == -EMEDIUMTYPE) { - ret = 0; - continue; - } - if (verbose) - regulator_show(dev, ret); - if (ret == -ENOSYS) - ret = 0; - } + if (_DEBUG) + regulator_show(dev, ret); - return ret; + return 0; } UCLASS_DRIVER(regulator) = { @@ -561,5 +531,6 @@ UCLASS_DRIVER(regulator) = { .name = "regulator", .post_bind = regulator_post_bind, .pre_probe = regulator_pre_probe, + .post_probe = regulator_post_probe, .per_device_plat_auto = sizeof(struct dm_regulator_uclass_plat), }; diff --git a/drivers/power/regulator/rk8xx.c b/drivers/power/regulator/rk8xx.c index 34e61511d88..375d06e3207 100644 --- a/drivers/power/regulator/rk8xx.c +++ b/drivers/power/regulator/rk8xx.c @@ -381,7 +381,7 @@ static int _buck_set_value(struct udevice *pmic, int buck, int uvolt) val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel; debug("%s: volt=%d, buck=%d, reg=0x%x, mask=0x%x, val=0x%x\n", - __func__, uvolt, buck + 1, info->vsel_reg, mask, val); + __func__, uvolt, buck, info->vsel_reg, mask, val); if (priv->variant == RK816_ID) { pmic_clrsetbits(pmic, info->vsel_reg, mask, val); @@ -415,7 +415,7 @@ static int _buck_set_enable(struct udevice *pmic, int buck, bool enable) break; case RK806_ID: value = RK806_POWER_EN_CLRSETBITS(buck % 4, enable); - en_reg = RK806_POWER_EN((buck + 1) / 4); + en_reg = RK806_POWER_EN(buck / 4); ret = pmic_reg_write(pmic, en_reg, value); break; case RK808_ID: @@ -470,7 +470,7 @@ static int _buck_set_suspend_value(struct udevice *pmic, int buck, int uvolt) val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel; debug("%s: volt=%d, buck=%d, reg=0x%x, mask=0x%x, val=0x%x\n", - __func__, uvolt, buck + 1, info->vsel_sleep_reg, mask, val); + __func__, uvolt, buck, info->vsel_sleep_reg, mask, val); return pmic_clrsetbits(pmic, info->vsel_sleep_reg, mask, val); } @@ -494,7 +494,7 @@ static int _buck_get_enable(struct udevice *pmic, int buck) break; case RK806_ID: mask = BIT(buck % 4); - ret = pmic_reg_read(pmic, RK806_POWER_EN((buck + 1) / 4)); + ret = pmic_reg_read(pmic, RK806_POWER_EN(buck / 4)); break; case RK808_ID: case RK818_ID: @@ -539,12 +539,13 @@ static int _buck_set_suspend_enable(struct udevice *pmic, int buck, bool enable) { u8 reg; - if (buck + 1 >= 9) { + if (buck >= 8) { + /* BUCK9 and BUCK10 */ reg = RK806_POWER_SLP_EN1; - mask = BIT(buck + 1 - 3); + mask = BIT(buck - 2); } else { reg = RK806_POWER_SLP_EN0; - mask = BIT(buck + 1); + mask = BIT(buck); } ret = pmic_clrsetbits(pmic, reg, mask, enable ? mask : 0); } @@ -590,12 +591,13 @@ static int _buck_get_suspend_enable(struct udevice *pmic, int buck) { u8 reg; - if (buck + 1 >= 9) { + if (buck >= 8) { + /* BUCK9 and BUCK10 */ reg = RK806_POWER_SLP_EN1; - mask = BIT(buck + 1 - 3); + mask = BIT(buck - 2); } else { reg = RK806_POWER_SLP_EN0; - mask = BIT(buck + 1); + mask = BIT(buck); } val = pmic_reg_read(pmic, reg); } diff --git a/drivers/power/regulator/tps6287x_regulator.c b/drivers/power/regulator/tps6287x_regulator.c new file mode 100644 index 00000000000..6d185719199 --- /dev/null +++ b/drivers/power/regulator/tps6287x_regulator.c @@ -0,0 +1,172 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/ + * Keerthy <j-keerthy@ti.com> + */ + +#include <dm.h> +#include <i2c.h> +#include <dm/device_compat.h> +#include <power/regulator.h> + +#define TPS6287X_REG_VSET 0x0 +#define TPS6287X_REG_CONTROL1 0x1 +#define TPS6287X_REG_CONTROL2 0x2 +#define TPS6287X_REG_CONTROL3 0x3 +#define TPS6287X_REG_STATUS 0x4 +#define TPS6287X_REG_VSET_VSET_MASK 0xff +#define TPS6287X_REG_CONTROL2_VRANGE_MASK 0xc + +struct tps6287x_regulator_config { + u32 vmin; + u32 vmax; +}; + +struct tps6287x_regulator_pdata { + u8 vsel_offset; + struct udevice *i2c; + struct tps6287x_regulator_config *config; +}; + +static struct tps6287x_regulator_config tps6287x_data = { + .vmin = 400000, + .vmax = 3350000, +}; + +static int tps6287x_regulator_set_value(struct udevice *dev, int uV) +{ + struct tps6287x_regulator_pdata *pdata = dev_get_plat(dev); + u8 regval, vset; + int ret; + + if (uV < pdata->config->vmin || uV > pdata->config->vmax) + return -EINVAL; + /* + * Based on the value of VRANGE bit field of CONTROL2 reg the range + * varies. + */ + ret = dm_i2c_read(pdata->i2c, TPS6287X_REG_CONTROL2, ®val, 1); + if (ret) { + dev_err(dev, "CTRL2 reg read failed: %d\n", ret); + return ret; + } + + regval &= TPS6287X_REG_CONTROL2_VRANGE_MASK; + regval >>= ffs(TPS6287X_REG_CONTROL2_VRANGE_MASK) - 1; + + /* + * VRANGE = 0. Increment step 1250 uV starting with 0 --> 400000 uV + * VRANGE = 1. Increment step 2500 uV starting with 0 --> 400000 uV + * VRANGE = 2. Increment step 5000 uV starting with 0 --> 400000 uV + * VRANGE = 3. Increment step 10000 uV starting with 0 --> 800000 uV + */ + switch (regval) { + case 0: + vset = (uV - 400000) / 1250; + break; + case 1: + vset = (uV - 400000) / 2500; + break; + case 2: + vset = (uV - 400000) / 5000; + break; + case 3: + vset = (uV - 800000) / 10000; + break; + default: + pr_err("%s: invalid regval %d\n", dev->name, regval); + return -EINVAL; + } + + return dm_i2c_write(pdata->i2c, TPS6287X_REG_VSET, &vset, 1); +} + +static int tps6287x_regulator_get_value(struct udevice *dev) +{ + u8 regval, vset; + int uV; + int ret; + struct tps6287x_regulator_pdata *pdata = dev_get_plat(dev); + + /* + * Based on the value of VRANGE bit field of CONTROL2 reg the range + * varies. + */ + ret = dm_i2c_read(pdata->i2c, TPS6287X_REG_CONTROL2, ®val, 1); + if (ret) { + dev_err(dev, "i2c read failed: %d\n", ret); + return ret; + } + + regval &= TPS6287X_REG_CONTROL2_VRANGE_MASK; + regval >>= ffs(TPS6287X_REG_CONTROL2_VRANGE_MASK) - 1; + + ret = dm_i2c_read(pdata->i2c, TPS6287X_REG_VSET, &vset, 1); + if (ret) { + dev_err(dev, "i2c VSET read failed: %d\n", ret); + return ret; + } + + /* + * VRANGE = 0. Increment step 1250 uV starting with 0 --> 400000 uV + * VRANGE = 1. Increment step 2500 uV starting with 0 --> 400000 uV + * VRANGE = 2. Increment step 5000 uV starting with 0 --> 400000 uV + * VRANGE = 3. Increment step 10000 uV starting with 0 --> 800000 uV + */ + switch (regval) { + case 0: + uV = 400000 + vset * 1250; + break; + case 1: + uV = 400000 + vset * 2500; + break; + case 2: + uV = 400000 + vset * 5000; + break; + case 3: + uV = 800000 + vset * 10000; + break; + default: + pr_err("%s: invalid regval %d\n", dev->name, regval); + return -EINVAL; + } + + return uV; +} + +static int tps6287x_regulator_probe(struct udevice *dev) +{ + struct tps6287x_regulator_pdata *pdata = dev_get_plat(dev); + int ret, slave_id; + + pdata->config = (void *)dev_get_driver_data(dev); + + slave_id = devfdt_get_addr_index(dev, 0); + + ret = i2c_get_chip(dev->parent, slave_id, 1, &pdata->i2c); + if (ret) { + dev_err(dev, "i2c dev get failed.\n"); + return ret; + } + + return 0; +} + +static const struct dm_regulator_ops tps6287x_regulator_ops = { + .get_value = tps6287x_regulator_get_value, + .set_value = tps6287x_regulator_set_value, +}; + +static const struct udevice_id tps6287x_regulator_ids[] = { + { .compatible = "ti,tps62873", .data = (ulong)&tps6287x_data }, + { }, +}; + +U_BOOT_DRIVER(tps6287x_regulator) = { + .name = "tps6287x_regulator", + .id = UCLASS_REGULATOR, + .ops = &tps6287x_regulator_ops, + .of_match = tps6287x_regulator_ids, + .plat_auto = sizeof(struct tps6287x_regulator_pdata), + .probe = tps6287x_regulator_probe, +}; diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c index 320ea7c4239..bb37b39fa0e 100644 --- a/drivers/pwm/pwm-imx.c +++ b/drivers/pwm/pwm-imx.c @@ -20,10 +20,11 @@ int pwm_config_internal(struct pwm_regs *pwm, unsigned long period_cycles, u32 cr; writel(0, &pwm->ir); - cr = PWMCR_PRESCALER(prescale) | + + cr = readl(&pwm->cr) & PWMCR_EN; + cr |= PWMCR_PRESCALER(prescale) | PWMCR_DOZEEN | PWMCR_WAITEN | PWMCR_DBGEN | PWMCR_CLKSRC_IPG_HIGH; - writel(cr, &pwm->cr); /* set duty cycles */ writel(duty_cycles, &pwm->sar); diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile index c9c46cc17a8..fdb2e78ec9e 100644 --- a/drivers/ram/Makefile +++ b/drivers/ram/Makefile @@ -14,7 +14,7 @@ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ obj-$(CONFIG_K3_AM654_DDRSS) += k3-am654-ddrss.o obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/ -obj-$(CONFIG_ARCH_ASPEED) += aspeed/ +obj-$(CONFIG_ASPEED_RAM) += aspeed/ obj-$(CONFIG_K3_DDRSS) += k3-ddrss/ obj-$(CONFIG_IMXRT_SDRAM) += imxrt_sdram.o diff --git a/drivers/ram/aspeed/Kconfig b/drivers/ram/aspeed/Kconfig index 0deab8649b6..e4918460de6 100644 --- a/drivers/ram/aspeed/Kconfig +++ b/drivers/ram/aspeed/Kconfig @@ -1,6 +1,7 @@ menuconfig ASPEED_RAM bool "ASPEED SDRAM configuration" - depends on RAM && ARCH_ASPEED + depends on RAM + depends on ARCH_ASPEED || TARGET_ASPEED_AST2700_IBEX default ARCH_ASPEED help Configuration options for DDR SDRAM on ASPEED systems. @@ -8,8 +9,6 @@ menuconfig ASPEED_RAM RAM initialisation is always built in for the platform. This menu allows customisation of the configuration used. -if ASPEED_RAM - config ASPEED_DDR4_DUALX8 bool "Enable Dual X8 DDR4 die" depends on ASPEED_RAM @@ -74,4 +73,24 @@ config ASPEED_DDR4_1600 select DDR4 target data rate at 1600M endchoice -endif # End of ASPEED_RAM +choice + prompt "AST2700 DDR target date rate" + default ASPEED_DDR_3200 + depends on ASPEED_RAM + depends on TARGET_ASPEED_AST2700_IBEX + +config ASPEED_DDR_1600 + bool "1600 Mbps" + help + select DDR target data rate at 1600M + +config ASPEED_DDR_2400 + bool "2400 Mbps" + help + select DDR target data rate at 2400M + +config ASPEED_DDR_3200 + bool "3200 Mbps" + help + select DDR target data rate at 3200M +endchoice diff --git a/drivers/ram/aspeed/Makefile b/drivers/ram/aspeed/Makefile index 7ac10af1c22..1f0b22c8e9f 100644 --- a/drivers/ram/aspeed/Makefile +++ b/drivers/ram/aspeed/Makefile @@ -2,3 +2,4 @@ # obj-$(CONFIG_ASPEED_AST2500) += sdram_ast2500.o obj-$(CONFIG_ASPEED_AST2600) += sdram_ast2600.o +obj-$(CONFIG_TARGET_ASPEED_AST2700_IBEX) += sdram_ast2700.o diff --git a/drivers/ram/aspeed/dwc_ddrphy_phyinit_ddr4-3200-nodimm-train2D.c b/drivers/ram/aspeed/dwc_ddrphy_phyinit_ddr4-3200-nodimm-train2D.c new file mode 100644 index 00000000000..de593c17fad --- /dev/null +++ b/drivers/ram/aspeed/dwc_ddrphy_phyinit_ddr4-3200-nodimm-train2D.c @@ -0,0 +1,2700 @@ +// SPDX-License-Identifier: GPL-2.0+ +// [dwc_ddrphy_phyinit_main] Start of dwc_ddrphy_phyinit_main() +// [dwc_ddrphy_phyinit_sequence] Start of dwc_ddrphy_phyinit_sequence() +// [dwc_ddrphy_phyinit_initStruct] Start of dwc_ddrphy_phyinit_initStruct() +// [dwc_ddrphy_phyinit_initStruct] End of dwc_ddrphy_phyinit_initStruct() +// [dwc_ddrphy_phyinit_setDefault] Start of dwc_ddrphy_phyinit_setDefault() +// [dwc_ddrphy_phyinit_setDefault] End of dwc_ddrphy_phyinit_setDefault() + +////############################################################## +// +//// dwc_ddrphy_phyinit_userCustom_overrideUserInput is a user-editable function. User can edit this function according to their needs. +//// +//// The purpose of dwc_ddrphy_phyinit_userCustom_overrideUserInput() is to override any +//// any field in Phyinit data structure set by dwc_ddrphy_phyinit_setDefault() +//// User should only override values in userInputBasic and userInputAdvanced. +//// IMPORTANT: in this function, user shall not override any values in the +//// messageblock directly on the data structue as the might be overwritten by +//// dwc_ddrphy_phyinit_calcMb(). Use dwc_ddrphy_phyinit_setMb() to set +//// messageblock parameters for override values to remain pervasive if +//// desired +// +////############################################################## + +dwc_ddrphy_phyinit_userCustom_overrideUserInput(); +// +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'DramType' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'DimmType' to 0x4 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'NumDbyte' to 0x2 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'NumActiveDbyteDfi0' to 0x2 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'NumAnib' to 0xa +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'NumRank_dfi0' to 0x1 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'DramDataWidth[0]' to 0x10 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'DramDataWidth[1]' to 0x10 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'DramDataWidth[2]' to 0x10 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'DramDataWidth[3]' to 0x10 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'NumPStates' to 0x1 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'Frequency[0]' to 0x640 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'PllBypass[0]' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'DfiFreqRatio[0]' to 0x1 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'Dfi1Exists' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'D4RxPreambleLength[0]' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'D4TxPreambleLength[0]' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'ExtCalResVal' to 0xf0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'Is2Ttiming[0]' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'ODTImpedance[0]' to 0x78 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'TxImpedance[0]' to 0x3c +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'MemAlertEn' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'MtestPUImp' to 0xf0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'DisDynAdrTri[0]' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'PhyMstrTrainInterval[0]' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'PhyMstrMaxReqToAck[0]' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'PhyMstrCtrlMode[0]' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'WDQSExt' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'CalInterval' to 0x9 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'CalOnce' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'RxEnBackOff' to 0x1 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'TrainSequenceCtrl' to 0x31f +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'SnpsUmctlOpt' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'SnpsUmctlF0RC5x[0]' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'TxSlewRiseDQ[0]' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'TxSlewFallDQ[0]' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'TxSlewRiseAC' to 0x45 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'TxSlewFallAC' to 0xa +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'IsHighVDD' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'TxSlewRiseCK' to 0x52 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'TxSlewFallCK' to 0x12 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'DisablePmuEcc' to 0x1 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'EnableMAlertAsync' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'Apb32BitMode' to 0x1 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'tDQS2DQ' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'tDQSCK' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'tCASL_override' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'tCASL_add[0][0]' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'tCASL_add[0][1]' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'tCASL_add[0][2]' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'tCASL_add[0][3]' to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].MsgMisc to 0x7 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].Pstate to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].PllBypassEn to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].DRAMFreq to 0xc80 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].PhyVref to 0x40 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].DramType to 0x2 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].DisabledDbyte to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].EnabledDQs to 0x10 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].CsPresent to 0x1 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].CsPresentD0 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].CsPresentD1 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].AddrMirror to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].PhyCfg to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].SequenceCtrl to 0x31f +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].HdtCtrl to 0xc8 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].PhyConfigOverride to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].DFIMRLMargin to 0x2 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].MR0 to 0x2150 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].MR1 to 0x101 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].MR2 to 0x228 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].MR3 to 0x400 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].MR4 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].MR5 to 0x500 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].MR6 to 0x104f +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].X16Present to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].CsSetupGDDec to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].AcsmOdtCtrl0 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].AcsmOdtCtrl1 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].AcsmOdtCtrl2 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].AcsmOdtCtrl3 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].AcsmOdtCtrl4 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].AcsmOdtCtrl5 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].AcsmOdtCtrl6 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].AcsmOdtCtrl7 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR0Nib0 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR0Nib1 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR0Nib2 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR0Nib3 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR0Nib4 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR0Nib5 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR0Nib6 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR0Nib7 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR0Nib8 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR0Nib9 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR0Nib10 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR0Nib11 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR0Nib12 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR0Nib13 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR0Nib14 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR0Nib15 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR0Nib16 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR0Nib17 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR0Nib18 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR0Nib19 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR1Nib0 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR1Nib1 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR1Nib2 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR1Nib3 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR1Nib4 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR1Nib5 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR1Nib6 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR1Nib7 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR1Nib8 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR1Nib9 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR1Nib10 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR1Nib11 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR1Nib12 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR1Nib13 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR1Nib14 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR1Nib15 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR1Nib16 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR1Nib17 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR1Nib18 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR1Nib19 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR2Nib0 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR2Nib1 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR2Nib2 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR2Nib3 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR2Nib4 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR2Nib5 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR2Nib6 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR2Nib7 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR2Nib8 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR2Nib9 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR2Nib10 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR2Nib11 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR2Nib12 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR2Nib13 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR2Nib14 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR2Nib15 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR2Nib16 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR2Nib17 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR2Nib18 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR2Nib19 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR3Nib0 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR3Nib1 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR3Nib2 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR3Nib3 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR3Nib4 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR3Nib5 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR3Nib6 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR3Nib7 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR3Nib8 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR3Nib9 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR3Nib10 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR3Nib11 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR3Nib12 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR3Nib13 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR3Nib14 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR3Nib15 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR3Nib16 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR3Nib17 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR3Nib18 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR3Nib19 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].ALT_CAS_L to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].ALT_WCAS_L to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].D4Misc to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].ExtTrainOpt to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].NVDIMM to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].MsgMisc to 0x7 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].Pstate to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].PllBypassEn to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].DRAMFreq to 0xc80 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].PhyVref to 0x40 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].DramType to 0x2 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].DisabledDbyte to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].EnabledDQs to 0x10 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].CsPresent to 0x1 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].CsPresentD0 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].CsPresentD1 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].AddrMirror to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].PhyCfg to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].SequenceCtrl to 0x31f +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].HdtCtrl to 0xc8 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].PhyConfigOverride to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].DFIMRLMargin to 0x2 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].MR0 to 0x2150 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].MR1 to 0x101 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].MR2 to 0x228 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].MR3 to 0x400 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].MR4 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].MR5 to 0x500 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].MR6 to 0x104f +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].X16Present to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].CsSetupGDDec to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].AcsmOdtCtrl0 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].AcsmOdtCtrl1 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].AcsmOdtCtrl2 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].AcsmOdtCtrl3 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].AcsmOdtCtrl4 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].AcsmOdtCtrl5 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].AcsmOdtCtrl6 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].AcsmOdtCtrl7 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR0Nib0 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR0Nib1 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR0Nib2 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR0Nib3 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR0Nib4 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR0Nib5 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR0Nib6 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR0Nib7 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR0Nib8 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR0Nib9 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR0Nib10 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR0Nib11 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR0Nib12 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR0Nib13 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR0Nib14 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR0Nib15 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR0Nib16 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR0Nib17 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR0Nib18 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR0Nib19 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR1Nib0 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR1Nib1 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR1Nib2 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR1Nib3 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR1Nib4 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR1Nib5 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR1Nib6 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR1Nib7 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR1Nib8 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR1Nib9 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR1Nib10 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR1Nib11 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR1Nib12 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR1Nib13 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR1Nib14 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR1Nib15 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR1Nib16 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR1Nib17 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR1Nib18 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR1Nib19 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR2Nib0 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR2Nib1 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR2Nib2 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR2Nib3 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR2Nib4 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR2Nib5 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR2Nib6 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR2Nib7 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR2Nib8 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR2Nib9 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR2Nib10 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR2Nib11 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR2Nib12 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR2Nib13 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR2Nib14 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR2Nib15 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR2Nib16 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR2Nib17 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR2Nib18 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR2Nib19 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR3Nib0 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR3Nib1 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR3Nib2 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR3Nib3 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR3Nib4 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR3Nib5 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR3Nib6 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR3Nib7 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR3Nib8 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR3Nib9 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR3Nib10 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR3Nib11 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR3Nib12 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR3Nib13 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR3Nib14 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR3Nib15 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR3Nib16 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR3Nib17 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR3Nib18 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR3Nib19 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].ALT_CAS_L to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].ALT_WCAS_L to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].D4Misc to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].ExtTrainOpt to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].NVDIMM to 0x0 +// [dwc_ddrphy_phyinit_userCustom_overrideUserInput] End of dwc_ddrphy_phyinit_userCustom_overrideUserInput() +//[dwc_ddrphy_phyinit_calcMb] Start of dwc_ddrphy_phyinit_calcMb() +//// [dwc_ddrphy_phyinit_softSetMb] mb_DDR4U_1D[0].DramType override to 0x2 +//// [dwc_ddrphy_phyinit_softSetMb] mb_DDR4U_1D[0].Pstate override to 0x0 +//// [dwc_ddrphy_phyinit_softSetMb] mb_DDR4U_1D[0].DRAMFreq override to 0xc80 +//// [dwc_ddrphy_phyinit_softSetMb] mb_DDR4U_1D[0].PllBypassEn override to 0x0 +//// [dwc_ddrphy_phyinit_softSetMb] mb_DDR4U_1D[0].EnabledDQs override to 0x10 +//// [dwc_ddrphy_phyinit_softSetMb] mb_DDR4U_1D[0].PhyCfg override to 0x0 +//// [dwc_ddrphy_phyinit_softSetMb] mb_DDR4U_1D[0].DisabledDbyte override to 0x0 +//// [dwc_ddrphy_phyinit_softSetMb] mb_DDR4U_1D[0].X16Present override to 0x0 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR4U_1D[1].DramType to 0x2 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR4U_1D[1].Pstate to 0x1 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR4U_1D[1].DRAMFreq to 0x856 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR4U_1D[1].PllBypassEn to 0x0 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR4U_1D[1].EnabledDQs to 0x10 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR4U_1D[1].PhyCfg to 0x0 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR4U_1D[1].DisabledDbyte to 0x0 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR4U_1D[1].X16Present to 0x1 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR4U_1D[2].DramType to 0x2 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR4U_1D[2].Pstate to 0x2 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR4U_1D[2].DRAMFreq to 0x74a +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR4U_1D[2].PllBypassEn to 0x0 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR4U_1D[2].EnabledDQs to 0x10 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR4U_1D[2].PhyCfg to 0x0 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR4U_1D[2].DisabledDbyte to 0x0 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR4U_1D[2].X16Present to 0x1 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR4U_1D[3].DramType to 0x2 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR4U_1D[3].Pstate to 0x3 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR4U_1D[3].DRAMFreq to 0x640 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR4U_1D[3].PllBypassEn to 0x0 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR4U_1D[3].EnabledDQs to 0x10 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR4U_1D[3].PhyCfg to 0x0 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR4U_1D[3].DisabledDbyte to 0x0 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR4U_1D[3].X16Present to 0x1 +//// [dwc_ddrphy_phyinit_softSetMb] mb_DDR4U_2D[0].DramType override to 0x2 +//// [dwc_ddrphy_phyinit_softSetMb] mb_DDR4U_2D[0].Pstate override to 0x0 +//// [dwc_ddrphy_phyinit_softSetMb] mb_DDR4U_2D[0].DRAMFreq override to 0xc80 +//// [dwc_ddrphy_phyinit_softSetMb] mb_DDR4U_2D[0].PllBypassEn override to 0x0 +//// [dwc_ddrphy_phyinit_softSetMb] mb_DDR4U_2D[0].EnabledDQs override to 0x10 +//// [dwc_ddrphy_phyinit_softSetMb] mb_DDR4U_2D[0].PhyCfg override to 0x0 +//// [dwc_ddrphy_phyinit_softSetMb] mb_DDR4U_2D[0].DisabledDbyte override to 0x0 +//// [dwc_ddrphy_phyinit_softSetMb] mb_DDR4U_2D[0].X16Present override to 0x0 +////[dwc_ddrphy_phyinit_calcMb] TG_active[0] = 1 +////[dwc_ddrphy_phyinit_calcMb] TG_active[1] = 0 +////[dwc_ddrphy_phyinit_calcMb] TG_active[2] = 0 +////[dwc_ddrphy_phyinit_calcMb] TG_active[3] = 0 +////[dwc_ddrphy_phyinit_calcMb] tDIMM_CK [pstate=0][tg=0] = 0 ps +////[dwc_ddrphy_phyinit_calcMb] tDIMM_DQ [pstate=0][tg=0] = 0 ps +////[dwc_ddrphy_phyinit_calcMb] userInputSim.tCASL_add[pstate=0][tg=0] = 0 ps +////[dwc_ddrphy_phyinit_calcMb] tDIMM_CK [pstate=0][tg=1] = 0 ps +////[dwc_ddrphy_phyinit_calcMb] tDIMM_DQ [pstate=0][tg=1] = 0 ps +////[dwc_ddrphy_phyinit_calcMb] userInputSim.tCASL_add[pstate=0][tg=1] = 0 ps +////[dwc_ddrphy_phyinit_calcMb] tDIMM_CK [pstate=0][tg=2] = 0 ps +////[dwc_ddrphy_phyinit_calcMb] tDIMM_DQ [pstate=0][tg=2] = 0 ps +////[dwc_ddrphy_phyinit_calcMb] userInputSim.tCASL_add[pstate=0][tg=2] = 0 ps +////[dwc_ddrphy_phyinit_calcMb] tDIMM_CK [pstate=0][tg=3] = 0 ps +////[dwc_ddrphy_phyinit_calcMb] tDIMM_DQ [pstate=0][tg=3] = 0 ps +////[dwc_ddrphy_phyinit_calcMb] userInputSim.tCASL_add[pstate=0][tg=3] = 0 ps +//[dwc_ddrphy_phyinit_calcMb] End of dwc_ddrphy_phyinit_calcMb() +//// [phyinit_print_dat] // #################################################### +//// [phyinit_print_dat] // +//// [phyinit_print_dat] // Printing values in user input structure +//// [phyinit_print_dat] // +//// [phyinit_print_dat] // #################################################### +//// [phyinit_print_dat] pUserInputBasic->Frequency[0] = 1600 +//// [phyinit_print_dat] pUserInputBasic->Frequency[1] = 1067 +//// [phyinit_print_dat] pUserInputBasic->Frequency[2] = 933 +//// [phyinit_print_dat] pUserInputBasic->Frequency[3] = 800 +//// [phyinit_print_dat] pUserInputBasic->NumAnib = 10 +//// [phyinit_print_dat] pUserInputBasic->DramType = 0 +//// [phyinit_print_dat] pUserInputBasic->ARdPtrInitValOvr = 0 +//// [phyinit_print_dat] pUserInputBasic->ARdPtrInitVal[0] = 3 +//// [phyinit_print_dat] pUserInputBasic->ARdPtrInitVal[1] = 3 +//// [phyinit_print_dat] pUserInputBasic->ARdPtrInitVal[2] = 3 +//// [phyinit_print_dat] pUserInputBasic->ARdPtrInitVal[3] = 3 +//// [phyinit_print_dat] pUserInputBasic->DfiFreqRatio[0] = 1 +//// [phyinit_print_dat] pUserInputBasic->DfiFreqRatio[1] = 1 +//// [phyinit_print_dat] pUserInputBasic->DfiFreqRatio[2] = 1 +//// [phyinit_print_dat] pUserInputBasic->DfiFreqRatio[3] = 1 +//// [phyinit_print_dat] pUserInputBasic->NumActiveDbyteDfi0 = 2 +//// [phyinit_print_dat] pUserInputBasic->DisPtrInitClrTxTracking[0] = 0 +//// [phyinit_print_dat] pUserInputBasic->DisPtrInitClrTxTracking[1] = 0 +//// [phyinit_print_dat] pUserInputBasic->DisPtrInitClrTxTracking[2] = 0 +//// [phyinit_print_dat] pUserInputBasic->DisPtrInitClrTxTracking[3] = 0 +//// [phyinit_print_dat] pUserInputBasic->DramDataWidth[0] = 16 +//// [phyinit_print_dat] pUserInputBasic->DramDataWidth[1] = 16 +//// [phyinit_print_dat] pUserInputBasic->DramDataWidth[2] = 16 +//// [phyinit_print_dat] pUserInputBasic->DramDataWidth[3] = 16 +//// [phyinit_print_dat] pUserInputBasic->PllBypass[0] = 0 +//// [phyinit_print_dat] pUserInputBasic->PllBypass[1] = 0 +//// [phyinit_print_dat] pUserInputBasic->PllBypass[2] = 0 +//// [phyinit_print_dat] pUserInputBasic->PllBypass[3] = 0 +//// [phyinit_print_dat] pUserInputBasic->Dfi1Exists = 0 +//// [phyinit_print_dat] pUserInputBasic->Train2D = 0 +//// [phyinit_print_dat] pUserInputBasic->NumRank_dfi0 = 1 +//// [phyinit_print_dat] pUserInputBasic->DimmType = 4 +//// [phyinit_print_dat] pUserInputBasic->NumPStates = 1 +//// [phyinit_print_dat] pUserInputBasic->NumDbyte = 2 +//// [phyinit_print_dat] pUserInputAdvanced->DisablePmuEcc = 1 +//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvEn[0] = 1 +//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvEn[1] = 1 +//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvEn[2] = 1 +//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvEn[3] = 1 +//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvEn[4] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvEn[5] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvEn[6] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvEn[7] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->SnpsUmctlOpt = 0 +//// [phyinit_print_dat] pUserInputAdvanced->TxImpedanceCtrl1[0] = 25 +//// [phyinit_print_dat] pUserInputAdvanced->TxImpedanceCtrl1[1] = 25 +//// [phyinit_print_dat] pUserInputAdvanced->TxImpedanceCtrl1[2] = 25 +//// [phyinit_print_dat] pUserInputAdvanced->TxImpedanceCtrl1[3] = 25 +//// [phyinit_print_dat] pUserInputAdvanced->TxSlewFallAC = 10 +//// [phyinit_print_dat] pUserInputAdvanced->CalOnce = 0 +//// [phyinit_print_dat] pUserInputAdvanced->ExtCalResVal = 240 +//// [phyinit_print_dat] pUserInputAdvanced->D4TxPreambleLength[0] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->D4TxPreambleLength[1] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->D4TxPreambleLength[2] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->D4TxPreambleLength[3] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->DramByteSwap[0] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->DramByteSwap[1] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->DramByteSwap[2] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->DramByteSwap[3] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->NvAnibRcvSel[0] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->NvAnibRcvSel[1] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->NvAnibRcvSel[2] = 11 +//// [phyinit_print_dat] pUserInputAdvanced->NvAnibRcvSel[3] = 11 +//// [phyinit_print_dat] pUserInputAdvanced->NvAnibRcvSel[4] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->NvAnibRcvSel[5] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->NvAnibRcvSel[6] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->NvAnibRcvSel[7] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->CalInterval = 9 +//// [phyinit_print_dat] pUserInputAdvanced->IsHighVDD = 0 +//// [phyinit_print_dat] pUserInputAdvanced->TxSlewRiseAC = 69 +//// [phyinit_print_dat] pUserInputAdvanced->TxSlewRiseCK = 82 +//// [phyinit_print_dat] pUserInputAdvanced->RedundantCs_en = 0 +//// [phyinit_print_dat] pUserInputAdvanced->TrainSequenceCtrl = 799 +//// [phyinit_print_dat] pUserInputAdvanced->PhyMstrCtrlMode[0] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->PhyMstrCtrlMode[1] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->PhyMstrCtrlMode[2] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->PhyMstrCtrlMode[3] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->TxSlewFallDQ[0] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->TxSlewFallDQ[1] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->TxSlewFallDQ[2] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->TxSlewFallDQ[3] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->MtestPUImp = 240 +//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvLaneSel[0] = 1 +//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvLaneSel[1] = 3 +//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvLaneSel[2] = 1 +//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvLaneSel[3] = 3 +//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvLaneSel[4] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvLaneSel[5] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvLaneSel[6] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvLaneSel[7] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->AlertRecoveryEnable = 0 +//// [phyinit_print_dat] pUserInputAdvanced->DisDynAdrTri[0] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->DisDynAdrTri[1] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->DisDynAdrTri[2] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->DisDynAdrTri[3] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->VREGCtrl_LP2_PwrSavings_En = 0 +//// [phyinit_print_dat] pUserInputAdvanced->SnpsUmctlF0RC5x[0] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->SnpsUmctlF0RC5x[1] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->SnpsUmctlF0RC5x[2] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->SnpsUmctlF0RC5x[3] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->D4RxPreambleLength[0] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->D4RxPreambleLength[1] = 1 +//// [phyinit_print_dat] pUserInputAdvanced->D4RxPreambleLength[2] = 1 +//// [phyinit_print_dat] pUserInputAdvanced->D4RxPreambleLength[3] = 1 +//// [phyinit_print_dat] pUserInputAdvanced->PhyMstrMaxReqToAck[0] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->PhyMstrMaxReqToAck[1] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->PhyMstrMaxReqToAck[2] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->PhyMstrMaxReqToAck[3] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->TxSlewRiseDQ[0] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->TxSlewRiseDQ[1] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->TxSlewRiseDQ[2] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->TxSlewRiseDQ[3] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->TxSlewFallCK = 18 +//// [phyinit_print_dat] pUserInputAdvanced->TxImpedance[0] = 60 +//// [phyinit_print_dat] pUserInputAdvanced->TxImpedance[1] = 25 +//// [phyinit_print_dat] pUserInputAdvanced->TxImpedance[2] = 25 +//// [phyinit_print_dat] pUserInputAdvanced->TxImpedance[3] = 25 +//// [phyinit_print_dat] pUserInputAdvanced->en_16LogicalRanks_3DS = 0 +//// [phyinit_print_dat] pUserInputAdvanced->RstRxTrkState = 0 +//// [phyinit_print_dat] pUserInputAdvanced->Is2Ttiming[0] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->Is2Ttiming[1] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->Is2Ttiming[2] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->Is2Ttiming[3] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->MemAlertEn = 0 +//// [phyinit_print_dat] pUserInputAdvanced->rtt_term_en = 0 +//// [phyinit_print_dat] pUserInputAdvanced->PhyMstrTrainInterval[0] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->PhyMstrTrainInterval[1] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->PhyMstrTrainInterval[2] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->PhyMstrTrainInterval[3] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->WDQSExt = 0 +//// [phyinit_print_dat] pUserInputAdvanced->en_3DS = 0 +//// [phyinit_print_dat] pUserInputAdvanced->TxImpedanceCtrl2[0] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->TxImpedanceCtrl2[1] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->TxImpedanceCtrl2[2] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->TxImpedanceCtrl2[3] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->ODTImpedance[0] = 120 +//// [phyinit_print_dat] pUserInputAdvanced->ODTImpedance[1] = 60 +//// [phyinit_print_dat] pUserInputAdvanced->ODTImpedance[2] = 60 +//// [phyinit_print_dat] pUserInputAdvanced->ODTImpedance[3] = 60 +//// [phyinit_print_dat] pUserInputAdvanced->EnableMAlertAsync = 0 +//// [phyinit_print_dat] pUserInputAdvanced->Apb32BitMode = 1 +//// [phyinit_print_dat] pUserInputAdvanced->Nibble_ECC = 15 +//// [phyinit_print_dat] pUserInputAdvanced->RxEnBackOff = 1 +//// [phyinit_print_dat] pUserInputAdvanced->ATxImpedance = 53247 +//// [phyinit_print_dat] pUserInputSim->tDQS2DQ = 0 +//// [phyinit_print_dat] pUserInputSim->tDQSCK = 0 +//// [phyinit_print_dat] pUserInputSim->tSTAOFF[0] = 0 +//// [phyinit_print_dat] pUserInputSim->tSTAOFF[1] = 0 +//// [phyinit_print_dat] pUserInputSim->tSTAOFF[2] = 0 +//// [phyinit_print_dat] pUserInputSim->tSTAOFF[3] = 0 +//// [phyinit_print_dat] // #################################################### +//// [phyinit_print_dat] // +//// [phyinit_print_dat] // Printing values of 1D message block input/inout fields, PState=0 +//// [phyinit_print_dat] // +//// [phyinit_print_dat] // #################################################### +//// [phyinit_print_dat] mb_DDR4U_1D[0].AdvTrainOpt = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].MsgMisc = 0x7 +//// [phyinit_print_dat] mb_DDR4U_1D[0].Pstate = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].PllBypassEn = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].DRAMFreq = 0xc80 +//// [phyinit_print_dat] mb_DDR4U_1D[0].PhyVref = 0x40 +//// [phyinit_print_dat] mb_DDR4U_1D[0].DramType = 0x2 +//// [phyinit_print_dat] mb_DDR4U_1D[0].DisabledDbyte = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].EnabledDQs = 0x10 +//// [phyinit_print_dat] mb_DDR4U_1D[0].CsPresent = 0x1 +//// [phyinit_print_dat] mb_DDR4U_1D[0].CsPresentD0 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].CsPresentD1 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].AddrMirror = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].PhyCfg = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].SequenceCtrl = 0x31f +//// [phyinit_print_dat] mb_DDR4U_1D[0].HdtCtrl = 0xc8 +//// [phyinit_print_dat] mb_DDR4U_1D[0].Rx2D_CmdSpacing = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].MREP_MIN_PULSE = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].DWL_MIN_PULSE = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].PhyConfigOverride = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].DFIMRLMargin = 0x2 +//// [phyinit_print_dat] mb_DDR4U_1D[0].DDR4_RXEN_OFFSET = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].MR0 = 0x2150 +//// [phyinit_print_dat] mb_DDR4U_1D[0].MR1 = 0x101 +//// [phyinit_print_dat] mb_DDR4U_1D[0].MR2 = 0x228 +//// [phyinit_print_dat] mb_DDR4U_1D[0].MR3 = 0x400 +//// [phyinit_print_dat] mb_DDR4U_1D[0].MR4 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].MR5 = 0x500 +//// [phyinit_print_dat] mb_DDR4U_1D[0].MR6 = 0x104f +//// [phyinit_print_dat] mb_DDR4U_1D[0].X16Present = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].CsSetupGDDec = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].RTT_NOM_WR_PARK0 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].RTT_NOM_WR_PARK1 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].RTT_NOM_WR_PARK2 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].RTT_NOM_WR_PARK3 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].RTT_NOM_WR_PARK4 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].RTT_NOM_WR_PARK5 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].RTT_NOM_WR_PARK6 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].RTT_NOM_WR_PARK7 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].AcsmOdtCtrl0 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].AcsmOdtCtrl1 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].AcsmOdtCtrl2 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].AcsmOdtCtrl3 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].AcsmOdtCtrl4 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].AcsmOdtCtrl5 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].AcsmOdtCtrl6 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].AcsmOdtCtrl7 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib0 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib1 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib2 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib3 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib4 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib5 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib6 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib7 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib8 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib9 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib10 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib11 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib12 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib13 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib14 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib15 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib16 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib17 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib18 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib19 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib0 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib1 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib2 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib3 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib4 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib5 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib6 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib7 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib8 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib9 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib10 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib11 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib12 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib13 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib14 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib15 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib16 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib17 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib18 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib19 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib0 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib1 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib2 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib3 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib4 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib5 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib6 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib7 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib8 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib9 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib10 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib11 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib12 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib13 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib14 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib15 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib16 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib17 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib18 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib19 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib0 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib1 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib2 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib3 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib4 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib5 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib6 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib7 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib8 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib9 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib10 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib11 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib12 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib13 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib14 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib15 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib16 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib17 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib18 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib19 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].ALT_CAS_L = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].ALT_WCAS_L = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].D4Misc = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].ExtTrainOpt = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].NVDIMM = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].AdvTrainOpt = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].MsgMisc = 0x7 +//// [phyinit_print_dat] mb_DDR4U_1D[0].Pstate = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].PllBypassEn = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].DRAMFreq = 0xc80 +//// [phyinit_print_dat] mb_DDR4U_1D[0].PhyVref = 0x40 +//// [phyinit_print_dat] mb_DDR4U_1D[0].DramType = 0x2 +//// [phyinit_print_dat] mb_DDR4U_1D[0].DisabledDbyte = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].EnabledDQs = 0x10 +//// [phyinit_print_dat] mb_DDR4U_1D[0].CsPresent = 0x1 +//// [phyinit_print_dat] mb_DDR4U_1D[0].CsPresentD0 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].CsPresentD1 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].AddrMirror = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].PhyCfg = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].SequenceCtrl = 0x31f +//// [phyinit_print_dat] mb_DDR4U_1D[0].HdtCtrl = 0xc8 +//// [phyinit_print_dat] mb_DDR4U_1D[0].Rx2D_CmdSpacing = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].MREP_MIN_PULSE = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].DWL_MIN_PULSE = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].PhyConfigOverride = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].DFIMRLMargin = 0x2 +//// [phyinit_print_dat] mb_DDR4U_1D[0].DDR4_RXEN_OFFSET = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].MR0 = 0x2150 +//// [phyinit_print_dat] mb_DDR4U_1D[0].MR1 = 0x101 +//// [phyinit_print_dat] mb_DDR4U_1D[0].MR2 = 0x228 +//// [phyinit_print_dat] mb_DDR4U_1D[0].MR3 = 0x400 +//// [phyinit_print_dat] mb_DDR4U_1D[0].MR4 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].MR5 = 0x500 +//// [phyinit_print_dat] mb_DDR4U_1D[0].MR6 = 0x104f +//// [phyinit_print_dat] mb_DDR4U_1D[0].X16Present = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].CsSetupGDDec = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].RTT_NOM_WR_PARK0 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].RTT_NOM_WR_PARK1 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].RTT_NOM_WR_PARK2 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].RTT_NOM_WR_PARK3 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].RTT_NOM_WR_PARK4 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].RTT_NOM_WR_PARK5 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].RTT_NOM_WR_PARK6 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].RTT_NOM_WR_PARK7 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].AcsmOdtCtrl0 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].AcsmOdtCtrl1 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].AcsmOdtCtrl2 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].AcsmOdtCtrl3 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].AcsmOdtCtrl4 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].AcsmOdtCtrl5 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].AcsmOdtCtrl6 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].AcsmOdtCtrl7 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib0 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib1 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib2 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib3 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib4 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib5 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib6 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib7 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib8 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib9 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib10 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib11 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib12 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib13 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib14 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib15 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib16 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib17 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib18 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib19 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib0 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib1 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib2 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib3 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib4 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib5 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib6 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib7 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib8 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib9 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib10 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib11 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib12 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib13 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib14 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib15 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib16 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib17 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib18 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib19 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib0 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib1 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib2 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib3 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib4 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib5 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib6 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib7 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib8 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib9 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib10 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib11 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib12 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib13 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib14 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib15 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib16 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib17 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib18 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib19 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib0 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib1 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib2 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib3 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib4 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib5 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib6 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib7 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib8 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib9 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib10 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib11 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib12 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib13 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib14 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib15 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib16 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib17 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib18 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib19 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].ALT_CAS_L = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].ALT_WCAS_L = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].D4Misc = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].ExtTrainOpt = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].NVDIMM = 0x0 +//// [phyinit_print_dat] // #################################################### +//// [phyinit_print_dat] // +//// [phyinit_print_dat] // Printing values of 2D message block input/inout fields, PState=0 +//// [phyinit_print_dat] // +//// [phyinit_print_dat] // #################################################### +//// [phyinit_print_dat] mb_DDR4U_2D[0].AdvTrainOpt = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].MsgMisc = 0x7 +//// [phyinit_print_dat] mb_DDR4U_2D[0].Pstate = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].PllBypassEn = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].DRAMFreq = 0xc80 +//// [phyinit_print_dat] mb_DDR4U_2D[0].PhyVref = 0x40 +//// [phyinit_print_dat] mb_DDR4U_2D[0].DramType = 0x2 +//// [phyinit_print_dat] mb_DDR4U_2D[0].DisabledDbyte = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].EnabledDQs = 0x10 +//// [phyinit_print_dat] mb_DDR4U_2D[0].CsPresent = 0x1 +//// [phyinit_print_dat] mb_DDR4U_2D[0].CsPresentD0 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].CsPresentD1 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].AddrMirror = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].PhyCfg = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].SequenceCtrl = 0x31f +//// [phyinit_print_dat] mb_DDR4U_2D[0].HdtCtrl = 0xc8 +//// [phyinit_print_dat] mb_DDR4U_2D[0].RX2D_TrainOpt = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].TX2D_TrainOpt = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].Share2DVrefResult = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].Delay_Weight2D = 0x20 +//// [phyinit_print_dat] mb_DDR4U_2D[0].Voltage_Weight2D = 0x80 +//// [phyinit_print_dat] mb_DDR4U_2D[0].Rx2D_CmdSpacing = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].MREP_MIN_PULSE = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].DWL_MIN_PULSE = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].PhyConfigOverride = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].DFIMRLMargin = 0x2 +//// [phyinit_print_dat] mb_DDR4U_2D[0].VoltageRange2D = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].MR1_EQU_TrainOpt = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].advSearch_rd2D = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].advSearch_wr2D = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].moreDebug2D = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].MR6_EQU_TrainOpt = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].TX2D_DB_DFE_TrainOpt = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].CsWriteNoise = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].AdvTrainOpt2D = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].Misc2D = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].MR0 = 0x2150 +//// [phyinit_print_dat] mb_DDR4U_2D[0].MR1 = 0x101 +//// [phyinit_print_dat] mb_DDR4U_2D[0].MR2 = 0x228 +//// [phyinit_print_dat] mb_DDR4U_2D[0].MR3 = 0x400 +//// [phyinit_print_dat] mb_DDR4U_2D[0].MR4 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].MR5 = 0x500 +//// [phyinit_print_dat] mb_DDR4U_2D[0].MR6 = 0x104f +//// [phyinit_print_dat] mb_DDR4U_2D[0].X16Present = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].CsSetupGDDec = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].RTT_NOM_WR_PARK0 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].RTT_NOM_WR_PARK1 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].RTT_NOM_WR_PARK2 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].RTT_NOM_WR_PARK3 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].RTT_NOM_WR_PARK4 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].RTT_NOM_WR_PARK5 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].RTT_NOM_WR_PARK6 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].RTT_NOM_WR_PARK7 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].AcsmOdtCtrl0 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].AcsmOdtCtrl1 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].AcsmOdtCtrl2 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].AcsmOdtCtrl3 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].AcsmOdtCtrl4 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].AcsmOdtCtrl5 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].AcsmOdtCtrl6 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].AcsmOdtCtrl7 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib0 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib1 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib2 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib3 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib4 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib5 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib6 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib7 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib8 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib9 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib10 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib11 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib12 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib13 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib14 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib15 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib16 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib17 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib18 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib19 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib0 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib1 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib2 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib3 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib4 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib5 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib6 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib7 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib8 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib9 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib10 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib11 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib12 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib13 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib14 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib15 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib16 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib17 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib18 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib19 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib0 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib1 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib2 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib3 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib4 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib5 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib6 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib7 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib8 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib9 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib10 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib11 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib12 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib13 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib14 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib15 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib16 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib17 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib18 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib19 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib0 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib1 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib2 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib3 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib4 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib5 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib6 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib7 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib8 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib9 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib10 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib11 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib12 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib13 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib14 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib15 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib16 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib17 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib18 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib19 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].ALT_CAS_L = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].ALT_WCAS_L = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].D4Misc = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].ExtTrainOpt = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].NVDIMM = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].AdvTrainOpt = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].MsgMisc = 0x7 +//// [phyinit_print_dat] mb_DDR4U_2D[0].Pstate = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].PllBypassEn = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].DRAMFreq = 0xc80 +//// [phyinit_print_dat] mb_DDR4U_2D[0].PhyVref = 0x40 +//// [phyinit_print_dat] mb_DDR4U_2D[0].DramType = 0x2 +//// [phyinit_print_dat] mb_DDR4U_2D[0].DisabledDbyte = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].EnabledDQs = 0x10 +//// [phyinit_print_dat] mb_DDR4U_2D[0].CsPresent = 0x1 +//// [phyinit_print_dat] mb_DDR4U_2D[0].CsPresentD0 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].CsPresentD1 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].AddrMirror = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].PhyCfg = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].SequenceCtrl = 0x31f +//// [phyinit_print_dat] mb_DDR4U_2D[0].HdtCtrl = 0xc8 +//// [phyinit_print_dat] mb_DDR4U_2D[0].RX2D_TrainOpt = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].TX2D_TrainOpt = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].Share2DVrefResult = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].Delay_Weight2D = 0x20 +//// [phyinit_print_dat] mb_DDR4U_2D[0].Voltage_Weight2D = 0x80 +//// [phyinit_print_dat] mb_DDR4U_2D[0].Rx2D_CmdSpacing = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].MREP_MIN_PULSE = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].DWL_MIN_PULSE = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].PhyConfigOverride = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].DFIMRLMargin = 0x2 +//// [phyinit_print_dat] mb_DDR4U_2D[0].VoltageRange2D = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].MR1_EQU_TrainOpt = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].advSearch_rd2D = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].advSearch_wr2D = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].moreDebug2D = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].MR6_EQU_TrainOpt = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].TX2D_DB_DFE_TrainOpt = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].CsWriteNoise = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].AdvTrainOpt2D = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].Misc2D = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].MR0 = 0x2150 +//// [phyinit_print_dat] mb_DDR4U_2D[0].MR1 = 0x101 +//// [phyinit_print_dat] mb_DDR4U_2D[0].MR2 = 0x228 +//// [phyinit_print_dat] mb_DDR4U_2D[0].MR3 = 0x400 +//// [phyinit_print_dat] mb_DDR4U_2D[0].MR4 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].MR5 = 0x500 +//// [phyinit_print_dat] mb_DDR4U_2D[0].MR6 = 0x104f +//// [phyinit_print_dat] mb_DDR4U_2D[0].X16Present = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].CsSetupGDDec = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].RTT_NOM_WR_PARK0 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].RTT_NOM_WR_PARK1 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].RTT_NOM_WR_PARK2 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].RTT_NOM_WR_PARK3 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].RTT_NOM_WR_PARK4 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].RTT_NOM_WR_PARK5 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].RTT_NOM_WR_PARK6 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].RTT_NOM_WR_PARK7 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].AcsmOdtCtrl0 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].AcsmOdtCtrl1 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].AcsmOdtCtrl2 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].AcsmOdtCtrl3 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].AcsmOdtCtrl4 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].AcsmOdtCtrl5 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].AcsmOdtCtrl6 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].AcsmOdtCtrl7 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib0 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib1 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib2 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib3 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib4 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib5 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib6 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib7 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib8 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib9 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib10 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib11 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib12 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib13 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib14 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib15 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib16 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib17 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib18 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib19 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib0 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib1 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib2 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib3 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib4 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib5 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib6 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib7 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib8 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib9 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib10 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib11 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib12 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib13 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib14 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib15 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib16 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib17 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib18 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib19 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib0 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib1 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib2 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib3 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib4 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib5 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib6 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib7 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib8 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib9 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib10 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib11 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib12 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib13 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib14 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib15 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib16 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib17 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib18 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib19 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib0 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib1 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib2 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib3 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib4 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib5 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib6 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib7 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib8 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib9 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib10 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib11 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib12 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib13 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib14 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib15 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib16 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib17 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib18 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib19 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].ALT_CAS_L = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].ALT_WCAS_L = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].D4Misc = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].ExtTrainOpt = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].NVDIMM = 0x0 + +////############################################################## +//// +//// Step (A) : Bring up VDD, VDDQ, and VAA +//// +//// The power supplies can come up and stabilize in any order. +//// While the power supplies are coming up, all outputs will be unknown and +//// the values of the inputs are don't cares. +//// +////############################################################## + +dwc_ddrphy_phyinit_userCustom_A_bringupPower(); + +//[dwc_ddrphy_phyinit_userCustom_A_bringupPower] End of dwc_ddrphy_phyinit_userCustom_A_bringupPower() +// +// +////############################################################## +//// +//// 4.3.2(B) Start Clocks and Reset the PHY +//// +//// Following is one possbile sequence to reset the PHY. Other sequences are also possible. +//// See section 5.2.2 of the PUB for other possible reset sequences. +//// +//// 1. Drive PwrOkIn to 0. Note: Reset, DfiClk, and APBCLK can be X. +//// 2. Start DfiClk and APBCLK +//// 3. Drive Reset to 1 and PRESETn_APB to 0. +//// Note: The combination of PwrOkIn=0 and Reset=1 signals a cold reset to the PHY. +//// 4. Wait a minimum of 8 cycles. +//// 5. Drive PwrOkIn to 1. Once the PwrOkIn is asserted (and Reset is still asserted), +//// DfiClk synchronously switches to any legal input frequency. +//// 6. Wait a minimum of 64 cycles. Note: This is the reset period for the PHY. +//// 7. Drive Reset to 0. Note: All DFI and APB inputs must be driven at valid reset states before the deassertion of Reset. +//// 8. Wait a minimum of 1 Cycle. +//// 9. Drive PRESETn_APB to 1 to de-assert reset on the ABP bus. +////10. The PHY is now in the reset state and is ready to accept APB transactions. +//// +////############################################################## +// +// +dwc_ddrphy_phyinit_userCustom_B_startClockResetPhy(sdrammc); + +//// [dwc_ddrphy_phyinit_userCustom_B_startClockResetPhy] End of dwc_ddrphy_phyinit_userCustom_B_startClockResetPhy() +// + +////############################################################## +//// +//// Step (C) Initialize PHY Configuration +//// +//// Load the required PHY configuration registers for the appropriate mode and memory configuration +//// +////############################################################## +// + +//// [phyinit_C_initPhyConfig] Start of dwc_ddrphy_phyinit_C_initPhyConfig() +//// [phyinit_C_initPhyConfig] Programming ForceClkGaterEnables::ForcePubDxClkEnLow to 0x1 +dwc_ddrphy_apb_wr(0x200a6, 0x2); // DWC_DDRPHYA_MASTER0_base0_ForceClkGaterEnables +// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming VREGCtrl3::VshCtrlUpdate to 0x0 for MASTER +dwc_ddrphy_apb_wr(0x20066, 0x0); // DWC_DDRPHYA_MASTER0_base0_VREGCtrl3 +// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming VREGCtrl3::VshCtrlUpdate to 0x0 for all DBYTEs +dwc_ddrphy_apb_wr(0x10066, 0x0); // DWC_DDRPHYA_DBYTE0_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x11066, 0x0); // DWC_DDRPHYA_DBYTE1_base0_VREGCtrl3 +// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming VREGCtrl3::VshCtrlUpdate to 0x0 for all ANIBs +dwc_ddrphy_apb_wr(0x66, 0x0); // DWC_DDRPHYA_ANIB0_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x1066, 0x0); // DWC_DDRPHYA_ANIB1_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x2066, 0x0); // DWC_DDRPHYA_ANIB2_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x3066, 0x0); // DWC_DDRPHYA_ANIB3_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x4066, 0x0); // DWC_DDRPHYA_ANIB4_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x5066, 0x0); // DWC_DDRPHYA_ANIB5_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x6066, 0x0); // DWC_DDRPHYA_ANIB6_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x7066, 0x0); // DWC_DDRPHYA_ANIB7_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x8066, 0x0); // DWC_DDRPHYA_ANIB8_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x9066, 0x0); // DWC_DDRPHYA_ANIB9_base0_VREGCtrl3 +// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming VREGCtrl1::VshDAC to 0x31 for MASTER +dwc_ddrphy_apb_wr(0x20029, 0xc4); // DWC_DDRPHYA_MASTER0_base0_VREGCtrl1_p0 +// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming VREGCtrl1::VshDAC to 0x31 for all DBYTEs +dwc_ddrphy_apb_wr(0x10029, 0xc4); // DWC_DDRPHYA_DBYTE0_base0_VREGCtrl1_p0 +dwc_ddrphy_apb_wr(0x11029, 0xc4); // DWC_DDRPHYA_DBYTE1_base0_VREGCtrl1_p0 +// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming VREGCtrl1::VshDAC to 0x31 for all ANIBs +dwc_ddrphy_apb_wr(0x29, 0xc4); // DWC_DDRPHYA_ANIB0_base0_VREGCtrl1_p0 +dwc_ddrphy_apb_wr(0x1029, 0xc4); // DWC_DDRPHYA_ANIB1_base0_VREGCtrl1_p0 +dwc_ddrphy_apb_wr(0x2029, 0xc4); // DWC_DDRPHYA_ANIB2_base0_VREGCtrl1_p0 +dwc_ddrphy_apb_wr(0x3029, 0xc4); // DWC_DDRPHYA_ANIB3_base0_VREGCtrl1_p0 +dwc_ddrphy_apb_wr(0x4029, 0xc4); // DWC_DDRPHYA_ANIB4_base0_VREGCtrl1_p0 +dwc_ddrphy_apb_wr(0x5029, 0xc4); // DWC_DDRPHYA_ANIB5_base0_VREGCtrl1_p0 +dwc_ddrphy_apb_wr(0x6029, 0xc4); // DWC_DDRPHYA_ANIB6_base0_VREGCtrl1_p0 +dwc_ddrphy_apb_wr(0x7029, 0xc4); // DWC_DDRPHYA_ANIB7_base0_VREGCtrl1_p0 +dwc_ddrphy_apb_wr(0x8029, 0xc4); // DWC_DDRPHYA_ANIB8_base0_VREGCtrl1_p0 +dwc_ddrphy_apb_wr(0x9029, 0xc4); // DWC_DDRPHYA_ANIB9_base0_VREGCtrl1_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TxSlewRate::CsrTxSrc to 0x0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TxSlewRate::TxPreDrvMode to 0x0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TxSlewRate to 0x0 +//// [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for TxSlewRate::CsrTxSrc are technology specific. +//// [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings + +dwc_ddrphy_apb_wr(0x1005f, 0x0); // DWC_DDRPHYA_DBYTE0_base0_TxSlewRate_b0_p0 +dwc_ddrphy_apb_wr(0x1015f, 0x0); // DWC_DDRPHYA_DBYTE0_base0_TxSlewRate_b1_p0 +dwc_ddrphy_apb_wr(0x1105f, 0x0); // DWC_DDRPHYA_DBYTE1_base0_TxSlewRate_b0_p0 +dwc_ddrphy_apb_wr(0x1115f, 0x0); // DWC_DDRPHYA_DBYTE1_base0_TxSlewRate_b1_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate::ATxPreDrvMode to 0x0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate::CsrATxSrc ANIB 0 to 0x11e +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate ANIB 0 to 0x11e +dwc_ddrphy_apb_wr(0x55, 0x11e); // DWC_DDRPHYA_ANIB0_base0_ATxSlewRate_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate::CsrATxSrc ANIB 1 to 0x11e +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate ANIB 1 to 0x11e +dwc_ddrphy_apb_wr(0x1055, 0x11e); // DWC_DDRPHYA_ANIB1_base0_ATxSlewRate_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate::CsrATxSrc ANIB 2 to 0x11e +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate ANIB 2 to 0x11e +dwc_ddrphy_apb_wr(0x2055, 0x11e); // DWC_DDRPHYA_ANIB2_base0_ATxSlewRate_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate::CsrATxSrc ANIB 3 to 0x11e +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate ANIB 3 to 0x11e +dwc_ddrphy_apb_wr(0x3055, 0x11e); // DWC_DDRPHYA_ANIB3_base0_ATxSlewRate_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate::CsrATxSrc ANIB 4 to 0x11e +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate ANIB 4 to 0x11e +dwc_ddrphy_apb_wr(0x4055, 0x11e); // DWC_DDRPHYA_ANIB4_base0_ATxSlewRate_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate::CsrATxSrc ANIB 5 to 0x15a +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate ANIB 5 to 0x15a +dwc_ddrphy_apb_wr(0x5055, 0x15a); // DWC_DDRPHYA_ANIB5_base0_ATxSlewRate_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate::CsrATxSrc ANIB 6 to 0x11e +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate ANIB 6 to 0x11e +dwc_ddrphy_apb_wr(0x6055, 0x11e); // DWC_DDRPHYA_ANIB6_base0_ATxSlewRate_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate::CsrATxSrc ANIB 7 to 0x11e +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate ANIB 7 to 0x11e +dwc_ddrphy_apb_wr(0x7055, 0x11e); // DWC_DDRPHYA_ANIB7_base0_ATxSlewRate_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate::CsrATxSrc ANIB 8 to 0x11e +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate ANIB 8 to 0x11e +dwc_ddrphy_apb_wr(0x8055, 0x11e); // DWC_DDRPHYA_ANIB8_base0_ATxSlewRate_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate::CsrATxSrc ANIB 9 to 0x11e +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate ANIB 9 to 0x11e +dwc_ddrphy_apb_wr(0x9055, 0x11e); // DWC_DDRPHYA_ANIB9_base0_ATxSlewRate_p0 +//// [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for ATxSlewRate::CsrATxSrc are technology specific. +//// [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings + +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming CalPreDriverOverride::CsrTxOvSrc to 0x172 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming CalPreDriverOverride::TxCalBaseN to 0x1 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming CalPreDriverOverride::TxCalBaseP to 0x1 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming CalPreDriverOverride to 0x372 +//// [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for CalPreDriverOverride::CsrTxOvSrc are technology specific. +//// [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings + +dwc_ddrphy_apb_wr(0x2008c, 0x372); // DWC_DDRPHYA_MASTER0_base0_CalPreDriverOverride +//// [phyinit_C_initPhyConfig] PUB revision is 0x0350. +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming PllCtrl2::PllFreqSel to 0x19 based on DfiClk frequency = 800. +dwc_ddrphy_apb_wr(0x200c5, 0x19); // DWC_DDRPHYA_MASTER0_base0_PllCtrl2_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming PllCtrl1::PllCpPropCtrl to 0x3 based on DfiClk frequency = 800. +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming PllCtrl1::PllCpIntCtrl to 0x1 based on DfiClk frequency = 800. +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming PllCtrl1 to 0x61 based on DfiClk frequency = 800. +dwc_ddrphy_apb_wr(0x200c7, 0x61); // DWC_DDRPHYA_MASTER0_base0_PllCtrl1_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming PllTestMode to 0x400f based on DfiClk frequency = 800. +dwc_ddrphy_apb_wr(0x200ca, 0x400f); // DWC_DDRPHYA_MASTER0_base0_PllTestMode_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming PllCtrl4::PllCpPropGsCtrl to 0x6 based on DfiClk frequency = 800. +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming PllCtrl4::PllCpIntGsCtrl to 0x12 based on DfiClk frequency = 800. +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming PllCtrl4 to 0xd2 based on DfiClk frequency = 800. +dwc_ddrphy_apb_wr(0x200cc, 0xd2); // DWC_DDRPHYA_MASTER0_base0_PllCtrl4_p0 +//// [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for PllCtrl1 and PllTestMode are technology specific. +//// [phyinit_C_initPhyConfig] ### NOTE ### Please consult technology specific PHY Databook for recommended settings + +// +////############################################################## +//// +//// Program ARdPtrInitVal based on Frequency and PLL Bypass inputs +//// The values programmed here assume ideal properties of DfiClk +//// and Pclk including: +//// - DfiClk skew +//// - DfiClk jitter +//// - DfiClk PVT variations +//// - Pclk skew +//// - Pclk jitter +//// +//// PLL Bypassed mode: +//// For MemClk frequency > 933MHz, the valid range of ARdPtrInitVal_p0[3:0] is: 2-5 +//// For MemClk frequency < 933MHz, the valid range of ARdPtrInitVal_p0[3:0] is: 1-5 +//// +//// PLL Enabled mode: +//// For MemClk frequency > 933MHz, the valid range of ARdPtrInitVal_p0[3:0] is: 1-5 +//// For MemClk frequency < 933MHz, the valid range of ARdPtrInitVal_p0[3:0] is: 0-5 +//// +////############################################################## +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ARdPtrInitVal to 0x1 +dwc_ddrphy_apb_wr(0x2002e, 0x1); // DWC_DDRPHYA_MASTER0_base0_ARdPtrInitVal_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DisPtrInitClrTxTracking to 0x0 +dwc_ddrphy_apb_wr(0x20051, 0x0); // DWC_DDRPHYA_MASTER0_base0_PtrInitTrackingModeCntrl_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DqsPreambleControl::TwoTckRxDqsPre to 0x0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DqsPreambleControl::TwoTckTxDqsPre to 0x0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DqsPreambleControl::PositionDfeInit to 0x2 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DqsPreambleControl::DDR5RxPreamble to 0x0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DqsPreambleControl::DDR5RxPostamble to 0x0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DqsPreambleControl to 0x8 +dwc_ddrphy_apb_wr(0x20024, 0x8); // DWC_DDRPHYA_MASTER0_base0_DqsPreambleControl_p0 +//// [phyinit_C_initPhyConfig] Programming DbyteDllModeCntrl::DllRxPreambleMode to 0x1 +//// [phyinit_C_initPhyConfig] Programming DbyteDllModeCntrl::DllRxBurstLengthMode to 0x0 +//// [phyinit_C_initPhyConfig] Programming DbyteDllModeCntrl to 0x2 +dwc_ddrphy_apb_wr(0x2003a, 0x2); // DWC_DDRPHYA_MASTER0_base0_DbyteDllModeCntrl +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TxOdtDrvStren::TxOdtStrenPu to 0x4 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TxOdtDrvStren::TxOdtStrenPd to 0x0 +dwc_ddrphy_apb_wr(0x1004d, 0x4); // DWC_DDRPHYA_DBYTE0_base0_TxOdtDrvStren_b0_p0 +dwc_ddrphy_apb_wr(0x1014d, 0x4); // DWC_DDRPHYA_DBYTE0_base0_TxOdtDrvStren_b1_p0 +dwc_ddrphy_apb_wr(0x1104d, 0x4); // DWC_DDRPHYA_DBYTE1_base0_TxOdtDrvStren_b0_p0 +dwc_ddrphy_apb_wr(0x1114d, 0x4); // DWC_DDRPHYA_DBYTE1_base0_TxOdtDrvStren_b1_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxImpedance::ADrvStrenP to 0x3f +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxImpedance::ADrvStrenN to 0x3f +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxImpedance::ATxReserved13x12 to 0x0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxImpedance::ATxCalBaseN to 0x1 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxImpedance::ATxCalBaseP to 0x1 +dwc_ddrphy_apb_wr(0x43, 0xcfff); // DWC_DDRPHYA_ANIB0_base0_ATxImpedance +dwc_ddrphy_apb_wr(0x1043, 0xcfff); // DWC_DDRPHYA_ANIB1_base0_ATxImpedance +dwc_ddrphy_apb_wr(0x2043, 0xcfff); // DWC_DDRPHYA_ANIB2_base0_ATxImpedance +dwc_ddrphy_apb_wr(0x3043, 0xcfff); // DWC_DDRPHYA_ANIB3_base0_ATxImpedance +dwc_ddrphy_apb_wr(0x4043, 0xcfff); // DWC_DDRPHYA_ANIB4_base0_ATxImpedance +dwc_ddrphy_apb_wr(0x5043, 0xcfff); // DWC_DDRPHYA_ANIB5_base0_ATxImpedance +dwc_ddrphy_apb_wr(0x6043, 0xcfff); // DWC_DDRPHYA_ANIB6_base0_ATxImpedance +dwc_ddrphy_apb_wr(0x7043, 0xcfff); // DWC_DDRPHYA_ANIB7_base0_ATxImpedance +dwc_ddrphy_apb_wr(0x8043, 0xcfff); // DWC_DDRPHYA_ANIB8_base0_ATxImpedance +dwc_ddrphy_apb_wr(0x9043, 0xcfff); // DWC_DDRPHYA_ANIB9_base0_ATxImpedance +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TxImpedanceCtrl0::TxStrenEqHiPu to 0xc +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TxImpedanceCtrl0::TxStrenEqLoPd to 0xc +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TxImpedanceCtrl1::TxStrenPu to 0x3f +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TxImpedanceCtrl1::TxStrenPd to 0x3f +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TxImpedanceCtrl2::TxStrenEqLoPu to 0x0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TxImpedanceCtrl2::TxStrenEqHiPd to 0x0 +dwc_ddrphy_apb_wr(0x10041, 0x30c); // DWC_DDRPHYA_DBYTE0_base0_TxImpedanceCtrl0_b0_p0 +dwc_ddrphy_apb_wr(0x10049, 0xfff); // DWC_DDRPHYA_DBYTE0_base0_TxImpedanceCtrl1_b0_p0 +dwc_ddrphy_apb_wr(0x1004b, 0x0); // DWC_DDRPHYA_DBYTE0_base0_TxImpedanceCtrl2_b0_p0 +dwc_ddrphy_apb_wr(0x10141, 0x30c); // DWC_DDRPHYA_DBYTE0_base0_TxImpedanceCtrl0_b1_p0 +dwc_ddrphy_apb_wr(0x10149, 0xfff); // DWC_DDRPHYA_DBYTE0_base0_TxImpedanceCtrl1_b1_p0 +dwc_ddrphy_apb_wr(0x1014b, 0x0); // DWC_DDRPHYA_DBYTE0_base0_TxImpedanceCtrl2_b1_p0 +dwc_ddrphy_apb_wr(0x11041, 0x30c); // DWC_DDRPHYA_DBYTE1_base0_TxImpedanceCtrl0_b0_p0 +dwc_ddrphy_apb_wr(0x11049, 0xfff); // DWC_DDRPHYA_DBYTE1_base0_TxImpedanceCtrl1_b0_p0 +dwc_ddrphy_apb_wr(0x1104b, 0x0); // DWC_DDRPHYA_DBYTE1_base0_TxImpedanceCtrl2_b0_p0 +dwc_ddrphy_apb_wr(0x11141, 0x30c); // DWC_DDRPHYA_DBYTE1_base0_TxImpedanceCtrl0_b1_p0 +dwc_ddrphy_apb_wr(0x11149, 0xfff); // DWC_DDRPHYA_DBYTE1_base0_TxImpedanceCtrl1_b1_p0 +dwc_ddrphy_apb_wr(0x1114b, 0x0); // DWC_DDRPHYA_DBYTE1_base0_TxImpedanceCtrl2_b1_p0 +//// [phyinit_C_initPhyConfig] Programming DfiMode to 0x1 +dwc_ddrphy_apb_wr(0x20018, 0x1); // DWC_DDRPHYA_MASTER0_base0_DfiMode +//// [phyinit_C_initPhyConfig] Programming DfiCAMode to 0x2 +dwc_ddrphy_apb_wr(0x20075, 0x2); // DWC_DDRPHYA_MASTER0_base0_DfiCAMode +//// [phyinit_C_initPhyConfig] Programming CalDrvStr0::CalDrvStrPd50 to 0x2 +//// [phyinit_C_initPhyConfig] Programming CalDrvStr0::CalDrvStrPu50 to 0x2 +dwc_ddrphy_apb_wr(0x20050, 0x82); // DWC_DDRPHYA_MASTER0_base0_CalDrvStr0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming CalUclkInfo::CalUClkTicksPer1uS to 0x320 +dwc_ddrphy_apb_wr(0x20008, 0x320); // DWC_DDRPHYA_MASTER0_base0_CalUclkInfo_p0 +//// [phyinit_C_initPhyConfig] Programming CalRate::CalInterval to 0x9 +//// [phyinit_C_initPhyConfig] Programming CalRate::CalOnce to 0x0 +dwc_ddrphy_apb_wr(0x20088, 0x9); // DWC_DDRPHYA_MASTER0_base0_CalRate +//// [phyinit_C_initPhyConfig] Pstate=0, Programming VrefInGlobal::GlobalVrefInSel to 0x0 +//// [phyinit_C_initPhyConfig] Pstate=0, Programming VrefInGlobal::GlobalVrefInDAC to 0x1f +//// [phyinit_C_initPhyConfig] Pstate=0, Programming VrefInGlobal to 0xf8 +dwc_ddrphy_apb_wr(0x200b2, 0xf8); // DWC_DDRPHYA_MASTER0_base0_VrefInGlobal_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Programming DqDqsRcvCntrl (Byte=0, Upper/Lower=0) to 0x2500 +dwc_ddrphy_apb_wr(0x10043, 0x2500); // DWC_DDRPHYA_DBYTE0_base0_DqDqsRcvCntrl_b0_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Programming DqDqsRcvCntrl (Byte=0, Upper/Lower=1) to 0x2500 +dwc_ddrphy_apb_wr(0x10143, 0x2500); // DWC_DDRPHYA_DBYTE0_base0_DqDqsRcvCntrl_b1_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Programming DqDqsRcvCntrl (Byte=1, Upper/Lower=0) to 0x2500 +dwc_ddrphy_apb_wr(0x11043, 0x2500); // DWC_DDRPHYA_DBYTE1_base0_DqDqsRcvCntrl_b0_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Programming DqDqsRcvCntrl (Byte=1, Upper/Lower=1) to 0x2500 +dwc_ddrphy_apb_wr(0x11143, 0x2500); // DWC_DDRPHYA_DBYTE1_base0_DqDqsRcvCntrl_b1_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Programming DqDqsRcvCntrl2 to 0x1c +dwc_ddrphy_apb_wr(0x1004c, 0x1c); // DWC_DDRPHYA_DBYTE0_base0_DqDqsRcvCntrl2_p0 +dwc_ddrphy_apb_wr(0x1104c, 0x1c); // DWC_DDRPHYA_DBYTE1_base0_DqDqsRcvCntrl2_p0 +//// [phyinit_C_initPhyConfig] Programming ATxOdtDrvStren of ANIB_0 to 0x0 +dwc_ddrphy_apb_wr(0x42, 0x0); // DWC_DDRPHYA_ANIB0_base0_ATxOdtDrvStren +//// [phyinit_C_initPhyConfig] Programming ATxOdtDrvStren of ANIB_0 to 0x0 +dwc_ddrphy_apb_wr(0x42, 0x0); // DWC_DDRPHYA_ANIB0_base0_ATxOdtDrvStren +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TristateModeCA::DisDynAdrTri_p0 to 0x0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TristateModeCA::DDR2TMode_p0 to 0x0 +dwc_ddrphy_apb_wr(0x20019, 0x5); // DWC_DDRPHYA_MASTER0_base0_TristateModeCA_p0 +//// [phyinit_C_initPhyConfig] Programming DfiFreqXlat* +dwc_ddrphy_apb_wr(0x200f0, 0x5555); // DWC_DDRPHYA_MASTER0_base0_DfiFreqXlat0 +dwc_ddrphy_apb_wr(0x200f1, 0x5555); // DWC_DDRPHYA_MASTER0_base0_DfiFreqXlat1 +dwc_ddrphy_apb_wr(0x200f2, 0x5555); // DWC_DDRPHYA_MASTER0_base0_DfiFreqXlat2 +dwc_ddrphy_apb_wr(0x200f3, 0x5555); // DWC_DDRPHYA_MASTER0_base0_DfiFreqXlat3 +dwc_ddrphy_apb_wr(0x200f4, 0x5555); // DWC_DDRPHYA_MASTER0_base0_DfiFreqXlat4 +dwc_ddrphy_apb_wr(0x200f5, 0x5555); // DWC_DDRPHYA_MASTER0_base0_DfiFreqXlat5 +dwc_ddrphy_apb_wr(0x200f6, 0x5555); // DWC_DDRPHYA_MASTER0_base0_DfiFreqXlat6 +dwc_ddrphy_apb_wr(0x200f7, 0xf000); // DWC_DDRPHYA_MASTER0_base0_DfiFreqXlat7 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming Seq0BDLY0 to 0x64 +dwc_ddrphy_apb_wr(0x2000b, 0x64); // DWC_DDRPHYA_MASTER0_base0_Seq0BDLY0_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming Seq0BDLY1 to 0xc8 +dwc_ddrphy_apb_wr(0x2000c, 0xc8); // DWC_DDRPHYA_MASTER0_base0_Seq0BDLY1_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming Seq0BDLY2 to 0x2bc +dwc_ddrphy_apb_wr(0x2000d, 0x2bc); // DWC_DDRPHYA_MASTER0_base0_Seq0BDLY2_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming Seq0BDLY3 to 0x2c +dwc_ddrphy_apb_wr(0x2000e, 0x2c); // DWC_DDRPHYA_MASTER0_base0_Seq0BDLY3_p0 +//// [phyinit_C_initPhyConfig] Disabling DBYTE 0 Lane 8 (DBI) Receiver to save power. +dwc_ddrphy_apb_wr(0x1004a, 0x500); // DWC_DDRPHYA_DBYTE0_base0_DqDqsRcvCntrl1 +//// [phyinit_C_initPhyConfig] Disabling DBYTE 1 Lane 8 (DBI) Receiver to save power. +dwc_ddrphy_apb_wr(0x1104a, 0x500); // DWC_DDRPHYA_DBYTE1_base0_DqDqsRcvCntrl1 +//// [phyinit_C_initPhyConfig] Programming MasterX4Config::X4TG to 0x0 +dwc_ddrphy_apb_wr(0x20025, 0x0); // DWC_DDRPHYA_MASTER0_base0_MasterX4Config +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming GPR7(csrAlertRecovery) to 0x0 +dwc_ddrphy_apb_wr(0x90307, 0x0); // DWC_DDRPHYA_INITENG0_base0_Seq0BGPR7_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DMIPinPresent::RdDbiEnabled to 0x0 +dwc_ddrphy_apb_wr(0x2002d, 0x0); // DWC_DDRPHYA_MASTER0_base0_DMIPinPresent_p0 +// [phyinit_C_initPhyConfig] Programming TimingModeCntrl::Dly64Prec to 0x0 +dwc_ddrphy_apb_wr(0x20040, 0x0); // DWC_DDRPHYA_MASTER0_base0_TimingModeCntrl +// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming VREGCtrl3::VshCtrlUpdate to 0x1 for MASTER +dwc_ddrphy_apb_wr(0x20066, 0x1); // DWC_DDRPHYA_MASTER0_base0_VREGCtrl3 +// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming VREGCtrl3::VshCtrlUpdate to 0x1 for all DBYTEs +dwc_ddrphy_apb_wr(0x10066, 0x1); // DWC_DDRPHYA_DBYTE0_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x11066, 0x1); // DWC_DDRPHYA_DBYTE1_base0_VREGCtrl3 +// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming VREGCtrl3::VshCtrlUpdate to 0x1 for all ANIBs +dwc_ddrphy_apb_wr(0x66, 0x1); // DWC_DDRPHYA_ANIB0_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x1066, 0x1); // DWC_DDRPHYA_ANIB1_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x2066, 0x1); // DWC_DDRPHYA_ANIB2_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x3066, 0x1); // DWC_DDRPHYA_ANIB3_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x4066, 0x1); // DWC_DDRPHYA_ANIB4_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x5066, 0x1); // DWC_DDRPHYA_ANIB5_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x6066, 0x1); // DWC_DDRPHYA_ANIB6_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x7066, 0x1); // DWC_DDRPHYA_ANIB7_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x8066, 0x1); // DWC_DDRPHYA_ANIB8_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x9066, 0x1); // DWC_DDRPHYA_ANIB9_base0_VREGCtrl3 +// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming AcClkDLLControl to 0x1080 +dwc_ddrphy_apb_wr(0x200ea, 0x1080); // DWC_DDRPHYA_MASTER0_base0_AcClkDLLControl_p0 +// [phyinit_C_initPhyConfig] Programming ArcPmuEccCtl to 0x1 +dwc_ddrphy_apb_wr(0xc0086, 0x1); // DWC_DDRPHYA_DRTUB0_ArcPmuEccCtl +// [phyinit_C_initPhyConfig] Programming VREGCtrl2 to 0x9820 for MASTER +dwc_ddrphy_apb_wr(0x2002b, 0x9820); // DWC_DDRPHYA_MASTER0_base0_VREGCtrl2 +// [phyinit_C_initPhyConfig] Programming VREGCtrl2 to 0x8020 for all DBYTEs +dwc_ddrphy_apb_wr(0x1002b, 0x8020); // DWC_DDRPHYA_DBYTE0_base0_VREGCtrl2 +dwc_ddrphy_apb_wr(0x1102b, 0x8020); // DWC_DDRPHYA_DBYTE1_base0_VREGCtrl2 +// [phyinit_C_initPhyConfig] Programming VREGCtrl2 to 0x8020 for all ANIBs +dwc_ddrphy_apb_wr(0x2b, 0x8020); // DWC_DDRPHYA_ANIB0_base0_VREGCtrl2 +dwc_ddrphy_apb_wr(0x102b, 0x8020); // DWC_DDRPHYA_ANIB1_base0_VREGCtrl2 +dwc_ddrphy_apb_wr(0x202b, 0x8020); // DWC_DDRPHYA_ANIB2_base0_VREGCtrl2 +dwc_ddrphy_apb_wr(0x302b, 0x8020); // DWC_DDRPHYA_ANIB3_base0_VREGCtrl2 +dwc_ddrphy_apb_wr(0x402b, 0x8020); // DWC_DDRPHYA_ANIB4_base0_VREGCtrl2 +dwc_ddrphy_apb_wr(0x502b, 0x8020); // DWC_DDRPHYA_ANIB5_base0_VREGCtrl2 +dwc_ddrphy_apb_wr(0x602b, 0x8020); // DWC_DDRPHYA_ANIB6_base0_VREGCtrl2 +dwc_ddrphy_apb_wr(0x702b, 0x8020); // DWC_DDRPHYA_ANIB7_base0_VREGCtrl2 +dwc_ddrphy_apb_wr(0x802b, 0x8020); // DWC_DDRPHYA_ANIB8_base0_VREGCtrl2 +dwc_ddrphy_apb_wr(0x902b, 0x8020); // DWC_DDRPHYA_ANIB9_base0_VREGCtrl2 +// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming VREGCtrl3::VshCtrlUpdate to 0x0 for MASTER +dwc_ddrphy_apb_wr(0x20066, 0x0); // DWC_DDRPHYA_MASTER0_base0_VREGCtrl3 +// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming VREGCtrl3::VshCtrlUpdate to 0x0 for all DBYTEs +dwc_ddrphy_apb_wr(0x10066, 0x0); // DWC_DDRPHYA_DBYTE0_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x11066, 0x0); // DWC_DDRPHYA_DBYTE1_base0_VREGCtrl3 +// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming VREGCtrl3::VshCtrlUpdate to 0x0 for all ANIBs +dwc_ddrphy_apb_wr(0x66, 0x0); // DWC_DDRPHYA_ANIB0_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x1066, 0x0); // DWC_DDRPHYA_ANIB1_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x2066, 0x0); // DWC_DDRPHYA_ANIB2_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x3066, 0x0); // DWC_DDRPHYA_ANIB3_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x4066, 0x0); // DWC_DDRPHYA_ANIB4_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x5066, 0x0); // DWC_DDRPHYA_ANIB5_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x6066, 0x0); // DWC_DDRPHYA_ANIB6_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x7066, 0x0); // DWC_DDRPHYA_ANIB7_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x8066, 0x0); // DWC_DDRPHYA_ANIB8_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x9066, 0x0); // DWC_DDRPHYA_ANIB9_base0_VREGCtrl3 +// [phyinit_C_initPhyConfig] Programming VrefDAC0 to 0x3f for all DBYTEs and lanes +// [phyinit_C_initPhyConfig] Programming VrefDAC1 to 0x3f for all DBYTEs and lanes +// [phyinit_C_initPhyConfig] Programming VrefDAC2 to 0x3f for all DBYTEs and lanes +// [phyinit_C_initPhyConfig] Programming VrefDAC3 to 0x3f for all DBYTEs and lanes +dwc_ddrphy_apb_wr(0x10040, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC0_r0_p0 +dwc_ddrphy_apb_wr(0x10030, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC1_r0 +dwc_ddrphy_apb_wr(0x10050, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC2_r0 +dwc_ddrphy_apb_wr(0x10060, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC3_r0 +dwc_ddrphy_apb_wr(0x10140, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC0_r1_p0 +dwc_ddrphy_apb_wr(0x10130, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC1_r1 +dwc_ddrphy_apb_wr(0x10150, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC2_r1 +dwc_ddrphy_apb_wr(0x10160, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC3_r1 +dwc_ddrphy_apb_wr(0x10240, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC0_r2_p0 +dwc_ddrphy_apb_wr(0x10230, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC1_r2 +dwc_ddrphy_apb_wr(0x10250, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC2_r2 +dwc_ddrphy_apb_wr(0x10260, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC3_r2 +dwc_ddrphy_apb_wr(0x10340, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC0_r3_p0 +dwc_ddrphy_apb_wr(0x10330, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC1_r3 +dwc_ddrphy_apb_wr(0x10350, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC2_r3 +dwc_ddrphy_apb_wr(0x10360, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC3_r3 +dwc_ddrphy_apb_wr(0x10440, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC0_r4_p0 +dwc_ddrphy_apb_wr(0x10430, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC1_r4 +dwc_ddrphy_apb_wr(0x10450, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC2_r4 +dwc_ddrphy_apb_wr(0x10460, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC3_r4 +dwc_ddrphy_apb_wr(0x10540, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC0_r5_p0 +dwc_ddrphy_apb_wr(0x10530, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC1_r5 +dwc_ddrphy_apb_wr(0x10550, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC2_r5 +dwc_ddrphy_apb_wr(0x10560, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC3_r5 +dwc_ddrphy_apb_wr(0x10640, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC0_r6_p0 +dwc_ddrphy_apb_wr(0x10630, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC1_r6 +dwc_ddrphy_apb_wr(0x10650, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC2_r6 +dwc_ddrphy_apb_wr(0x10660, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC3_r6 +dwc_ddrphy_apb_wr(0x10740, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC0_r7_p0 +dwc_ddrphy_apb_wr(0x10730, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC1_r7 +dwc_ddrphy_apb_wr(0x10750, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC2_r7 +dwc_ddrphy_apb_wr(0x10760, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC3_r7 +dwc_ddrphy_apb_wr(0x10840, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC0_r8_p0 +dwc_ddrphy_apb_wr(0x10830, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC1_r8 +dwc_ddrphy_apb_wr(0x10850, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC2_r8 +dwc_ddrphy_apb_wr(0x10860, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC3_r8 +dwc_ddrphy_apb_wr(0x11040, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC0_r0_p0 +dwc_ddrphy_apb_wr(0x11030, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC1_r0 +dwc_ddrphy_apb_wr(0x11050, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC2_r0 +dwc_ddrphy_apb_wr(0x11060, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC3_r0 +dwc_ddrphy_apb_wr(0x11140, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC0_r1_p0 +dwc_ddrphy_apb_wr(0x11130, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC1_r1 +dwc_ddrphy_apb_wr(0x11150, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC2_r1 +dwc_ddrphy_apb_wr(0x11160, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC3_r1 +dwc_ddrphy_apb_wr(0x11240, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC0_r2_p0 +dwc_ddrphy_apb_wr(0x11230, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC1_r2 +dwc_ddrphy_apb_wr(0x11250, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC2_r2 +dwc_ddrphy_apb_wr(0x11260, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC3_r2 +dwc_ddrphy_apb_wr(0x11340, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC0_r3_p0 +dwc_ddrphy_apb_wr(0x11330, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC1_r3 +dwc_ddrphy_apb_wr(0x11350, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC2_r3 +dwc_ddrphy_apb_wr(0x11360, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC3_r3 +dwc_ddrphy_apb_wr(0x11440, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC0_r4_p0 +dwc_ddrphy_apb_wr(0x11430, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC1_r4 +dwc_ddrphy_apb_wr(0x11450, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC2_r4 +dwc_ddrphy_apb_wr(0x11460, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC3_r4 +dwc_ddrphy_apb_wr(0x11540, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC0_r5_p0 +dwc_ddrphy_apb_wr(0x11530, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC1_r5 +dwc_ddrphy_apb_wr(0x11550, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC2_r5 +dwc_ddrphy_apb_wr(0x11560, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC3_r5 +dwc_ddrphy_apb_wr(0x11640, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC0_r6_p0 +dwc_ddrphy_apb_wr(0x11630, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC1_r6 +dwc_ddrphy_apb_wr(0x11650, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC2_r6 +dwc_ddrphy_apb_wr(0x11660, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC3_r6 +dwc_ddrphy_apb_wr(0x11740, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC0_r7_p0 +dwc_ddrphy_apb_wr(0x11730, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC1_r7 +dwc_ddrphy_apb_wr(0x11750, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC2_r7 +dwc_ddrphy_apb_wr(0x11760, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC3_r7 +dwc_ddrphy_apb_wr(0x11840, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC0_r8_p0 +dwc_ddrphy_apb_wr(0x11830, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC1_r8 +dwc_ddrphy_apb_wr(0x11850, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC2_r8 +dwc_ddrphy_apb_wr(0x11860, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC3_r8 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DfiFreqRatio_p0 to 0x1 +dwc_ddrphy_apb_wr(0x200fa, 0x1); // DWC_DDRPHYA_MASTER0_base0_DfiFreqRatio_p0 +//// [phyinit_C_initPhyConfig] Programming ForceClkGaterEnables::ForcePubDxClkEnLow to 0x0 +dwc_ddrphy_apb_wr(0x200a6, 0x0); // DWC_DDRPHYA_MASTER0_base0_ForceClkGaterEnables +//// [phyinit_C_initPhyConfig] Programming AForceTriCont (anib=0) to 0xc +dwc_ddrphy_apb_wr(0x28, 0xc); // DWC_DDRPHYA_ANIB0_base0_AForceTriCont +//// [phyinit_C_initPhyConfig] End of dwc_ddrphy_phyinit_C_initPhyConfig() +// +// +////############################################################## +//// +//// dwc_ddrphy_phyinit_userCustom_customPreTrain is a user-editable function. +//// +//// The purpose of dwc_ddrphy_phyinit_userCustom_customPreTrain() is to override any +//// any message block fields calculated by Phyinit in dwc_ddrphy_phyinit_calcMb() or to +//// override any CSR values programmed by Phyinit in dwc_ddrphy_phyinit_C_initPhyConfig(). +//// This function is executed before training and thus any override here might affect +//// training result. +//// +//// IMPORTANT: in this function, user shall not override any values in userInputBasic and +//// userInputAdvanced data structures. Use dwc_ddrphy_phyinit_userCustom_overrideUserInput() +//// to modify values in those data structures. +//// +////############################################################## +// +//// [phyinit_userCustom_customPreTrain] Start of dwc_ddrphy_phyinit_userCustom_customPreTrain() +//// [phyinit_userCustom_customPreTrain] End of dwc_ddrphy_phyinit_userCustom_customPreTrain() +//// [dwc_ddrphy_phyinit_D_loadIMEM, 1D] Start of dwc_ddrphy_phyinit_D_loadIMEM (Train2D=0) +// +// +////############################################################## +//// +//// (D) Load the 1D IMEM image +//// +//// This function loads the training firmware IMEM image into the SRAM. +//// See PhyInit App Note for detailed description and function usage +//// +////############################################################## +// +// +//// [dwc_ddrphy_phyinit_D_loadIMEM, 1D] Programming MemResetL to 0x2 +dwc_ddrphy_apb_wr(0x20060, 0x2); // DWC_DDRPHYA_MASTER0_base0_MemResetL +// [dwc_ddrphy_phyinit_storeIncvFile] Reading input file: /home/jerry_ku/Project/Development/ast2700dev/ddr45phy_tsmc12/coreConsultant/config3_3.50a/2022-12-12-16-52-55/firmware/Latest/training/ddr4/ddr4_pmu_train_imem.incv + +//// 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. +//// This allows the memory controller unrestricted access to the configuration CSRs. +dwc_ddrphy_apb_wr(0xd0000, 0x0); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel +//// [phyinit_userCustom_wait] Wait 40 DfiClks +//// [dwc_ddrphy_phyinit_WriteOutMem] STARTING 32bit write. offset 0x50000 size 0x8000 +//#ifdef TRAIN_LOADBIN +dwc_ddrphy_phyinit_userCustom_D_loadIMEM(sdrammc, 0); +//// [dwc_ddrphy_phyinit_WriteOutMem] DONE. Index 0x8000 +//// 2. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. +//// This allows the firmware unrestricted access to the configuration CSRs. +dwc_ddrphy_apb_wr(0xd0000, 0x1); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel +//// [phyinit_userCustom_wait] Wait 40 DfiClks +//// [dwc_ddrphy_phyinit_D_loadIMEM, 1D] End of dwc_ddrphy_phyinit_D_loadIMEM() +// +// +////############################################################## +//// +//// 4.3.5(E) Set the PHY input clocks to the desired frequency for pstate 0 +//// +//// Set the PHY input Dfi Clk to the desired operating frequency associated with the given Pstate. Before proceeding to the next step, +//// the clock should be stable at the new frequency. For more information on clocking requirements, see "Clocks" on page <XXX>. +//// +////############################################################## +// +dwc_ddrphy_phyinit_userCustom_E_setDfiClk(sdrammc); + +// +//// [dwc_ddrphy_phyinit_userCustom_E_setDfiClk] End of dwc_ddrphy_phyinit_userCustom_E_setDfiClk() +//// [phyinit_F_loadDMEM, 1D] Start of dwc_ddrphy_phyinit_F_loadDMEM (pstate=0, Train2D=0) +// +// +////############################################################## +//// +//// 4.3.5(F) Load the 1D DMEM image and write the 1D Message Block parameters for the training firmware +//// +//// The procedure is as follows: +//// +////############################################################## +// +// +// +//// 1. Load the firmware DMEM segment to initialize the data structures. +// +//// 2. Write the Firmware Message Block with the required contents detailing the training parameters. +// +// [dwc_ddrphy_phyinit_storeIncvFile] Reading input file: /home/jerry_ku/Project/Development/ast2700dev/ddr45phy_tsmc12/coreConsultant/config3_3.50a/2022-12-12-16-52-55/firmware/Latest/training/ddr4/ddr4_pmu_train_dmem.incv + +//// 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. +//// This allows the memory controller unrestricted access to the configuration CSRs. +dwc_ddrphy_apb_wr(0xd0000, 0x0); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel +//// [phyinit_userCustom_wait] Wait 40 DfiClks +//// [dwc_ddrphy_phyinit_WriteOutMem] STARTING 32bit write. offset 0x58000 size 0x8000 +//#ifdef TRAIN_LOADBIN +dwc_ddrphy_phyinit_userCustom_F_loadDMEM(sdrammc, 0, 0); + +dwc_ddrphy_apb_wr_32b(0x58000, 0x100); +dwc_ddrphy_apb_wr_32b(0x58002, 0xc800000); +dwc_ddrphy_apb_wr_32b(0x58004, 0x0); +dwc_ddrphy_apb_wr_32b(0x58006, 0x10000240); +dwc_ddrphy_apb_wr_32b(0x58008, 0x1); +dwc_ddrphy_apb_wr_32b(0x5800a, 0x31f0000); +dwc_ddrphy_apb_wr_32b(0x5800c, 0xc8); +dwc_ddrphy_apb_wr_32b(0x5800e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58010, 0x0); +dwc_ddrphy_apb_wr_32b(0x58012, 0x2); +dwc_ddrphy_apb_wr_32b(0x58014, 0x0); +dwc_ddrphy_apb_wr_32b(0x58016, 0x0); +dwc_ddrphy_apb_wr_32b(0x58018, 0x0); +dwc_ddrphy_apb_wr_32b(0x5801a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5801c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5801e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58020, 0x0); +dwc_ddrphy_apb_wr_32b(0x58022, 0x0); +dwc_ddrphy_apb_wr_32b(0x58024, 0x0); +dwc_ddrphy_apb_wr_32b(0x58026, 0x0); +dwc_ddrphy_apb_wr_32b(0x58028, 0x0); +dwc_ddrphy_apb_wr_32b(0x5802a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5802c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5802e, 0x21500000); +dwc_ddrphy_apb_wr_32b(0x58030, 0x2280101); +dwc_ddrphy_apb_wr_32b(0x58032, 0x400); +dwc_ddrphy_apb_wr_32b(0x58034, 0x104f0500); +dwc_ddrphy_apb_wr_32b(0x58036, 0x0); +dwc_ddrphy_apb_wr_32b(0x58038, 0x0); +dwc_ddrphy_apb_wr_32b(0x5803a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5803c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5803e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58040, 0x0); +dwc_ddrphy_apb_wr_32b(0x58042, 0xf0f0000); +dwc_ddrphy_apb_wr_32b(0x58044, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x58046, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x58048, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x5804a, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x5804c, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x5804e, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x58050, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x58052, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x58054, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x58056, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x58058, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x5805a, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x5805c, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x5805e, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x58060, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x58062, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x58064, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x58066, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x58068, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x5806a, 0xf0f); +dwc_ddrphy_apb_wr_32b(0x5806c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5806e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58070, 0x0); +dwc_ddrphy_apb_wr_32b(0x58072, 0x0); +dwc_ddrphy_apb_wr_32b(0x58074, 0x0); +dwc_ddrphy_apb_wr_32b(0x58076, 0x0); +dwc_ddrphy_apb_wr_32b(0x58078, 0x0); +dwc_ddrphy_apb_wr_32b(0x5807a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5807c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5807e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58080, 0x0); +dwc_ddrphy_apb_wr_32b(0x58082, 0x0); +dwc_ddrphy_apb_wr_32b(0x58084, 0x0); +dwc_ddrphy_apb_wr_32b(0x58086, 0x0); +dwc_ddrphy_apb_wr_32b(0x58088, 0x0); +dwc_ddrphy_apb_wr_32b(0x5808a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5808c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5808e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58090, 0x0); +dwc_ddrphy_apb_wr_32b(0x58092, 0x0); +dwc_ddrphy_apb_wr_32b(0x58094, 0x0); +dwc_ddrphy_apb_wr_32b(0x58096, 0x0); +dwc_ddrphy_apb_wr_32b(0x58098, 0x0); +dwc_ddrphy_apb_wr_32b(0x5809a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5809c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5809e, 0x0); +dwc_ddrphy_apb_wr_32b(0x580a0, 0x0); +dwc_ddrphy_apb_wr_32b(0x580a2, 0x0); +dwc_ddrphy_apb_wr_32b(0x580a4, 0x0); +dwc_ddrphy_apb_wr_32b(0x580a6, 0x0); +dwc_ddrphy_apb_wr_32b(0x580a8, 0x0); +dwc_ddrphy_apb_wr_32b(0x580aa, 0x0); +dwc_ddrphy_apb_wr_32b(0x580ac, 0x0); +dwc_ddrphy_apb_wr_32b(0x580ae, 0x0); +dwc_ddrphy_apb_wr_32b(0x580b0, 0x0); +dwc_ddrphy_apb_wr_32b(0x580b2, 0x0); +dwc_ddrphy_apb_wr_32b(0x580b4, 0x0); +dwc_ddrphy_apb_wr_32b(0x580b6, 0x0); +dwc_ddrphy_apb_wr_32b(0x580b8, 0x0); +dwc_ddrphy_apb_wr_32b(0x580ba, 0x0); +dwc_ddrphy_apb_wr_32b(0x580bc, 0x0); +dwc_ddrphy_apb_wr_32b(0x580be, 0x0); +dwc_ddrphy_apb_wr_32b(0x580c0, 0x0); +dwc_ddrphy_apb_wr_32b(0x580c2, 0x0); +dwc_ddrphy_apb_wr_32b(0x580c4, 0x0); +dwc_ddrphy_apb_wr_32b(0x580c6, 0x0); +dwc_ddrphy_apb_wr_32b(0x580c8, 0x0); +dwc_ddrphy_apb_wr_32b(0x580ca, 0x0); +dwc_ddrphy_apb_wr_32b(0x580cc, 0x0); +dwc_ddrphy_apb_wr_32b(0x580ce, 0x0); +dwc_ddrphy_apb_wr_32b(0x580d0, 0x0); +dwc_ddrphy_apb_wr_32b(0x580d2, 0x0); +dwc_ddrphy_apb_wr_32b(0x580d4, 0x0); +dwc_ddrphy_apb_wr_32b(0x580d6, 0x0); +dwc_ddrphy_apb_wr_32b(0x580d8, 0x0); +dwc_ddrphy_apb_wr_32b(0x580da, 0x0); +dwc_ddrphy_apb_wr_32b(0x580dc, 0x0); +dwc_ddrphy_apb_wr_32b(0x580de, 0x0); +dwc_ddrphy_apb_wr_32b(0x580e0, 0x0); +dwc_ddrphy_apb_wr_32b(0x580e2, 0x0); +dwc_ddrphy_apb_wr_32b(0x580e4, 0x0); +dwc_ddrphy_apb_wr_32b(0x580e6, 0x0); +dwc_ddrphy_apb_wr_32b(0x580e8, 0x0); +dwc_ddrphy_apb_wr_32b(0x580ea, 0x0); +dwc_ddrphy_apb_wr_32b(0x580ec, 0x0); +dwc_ddrphy_apb_wr_32b(0x580ee, 0x0); +dwc_ddrphy_apb_wr_32b(0x580f0, 0x0); +dwc_ddrphy_apb_wr_32b(0x580f2, 0x0); +dwc_ddrphy_apb_wr_32b(0x580f4, 0x0); +dwc_ddrphy_apb_wr_32b(0x580f6, 0x0); +dwc_ddrphy_apb_wr_32b(0x580f8, 0x0); +dwc_ddrphy_apb_wr_32b(0x580fa, 0x0); +dwc_ddrphy_apb_wr_32b(0x580fc, 0x0); +dwc_ddrphy_apb_wr_32b(0x580fe, 0x0); +dwc_ddrphy_apb_wr_32b(0x58100, 0x0); +dwc_ddrphy_apb_wr_32b(0x58102, 0x0); +dwc_ddrphy_apb_wr_32b(0x58104, 0x0); +dwc_ddrphy_apb_wr_32b(0x58106, 0x0); +dwc_ddrphy_apb_wr_32b(0x58108, 0x0); +dwc_ddrphy_apb_wr_32b(0x5810a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5810c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5810e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58110, 0x0); +dwc_ddrphy_apb_wr_32b(0x58112, 0x0); +dwc_ddrphy_apb_wr_32b(0x58114, 0x0); +dwc_ddrphy_apb_wr_32b(0x58116, 0x0); +dwc_ddrphy_apb_wr_32b(0x58118, 0x0); +dwc_ddrphy_apb_wr_32b(0x5811a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5811c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5811e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58120, 0x0); +dwc_ddrphy_apb_wr_32b(0x58122, 0x0); +dwc_ddrphy_apb_wr_32b(0x58124, 0x0); +dwc_ddrphy_apb_wr_32b(0x58126, 0x0); +dwc_ddrphy_apb_wr_32b(0x58128, 0x0); +dwc_ddrphy_apb_wr_32b(0x5812a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5812c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5812e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58130, 0x0); +dwc_ddrphy_apb_wr_32b(0x58132, 0x0); +dwc_ddrphy_apb_wr_32b(0x58134, 0x0); +dwc_ddrphy_apb_wr_32b(0x58136, 0x0); +dwc_ddrphy_apb_wr_32b(0x58138, 0x0); +dwc_ddrphy_apb_wr_32b(0x5813a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5813c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5813e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58140, 0x0); +dwc_ddrphy_apb_wr_32b(0x58142, 0x0); +dwc_ddrphy_apb_wr_32b(0x58144, 0x0); +dwc_ddrphy_apb_wr_32b(0x58146, 0x0); +dwc_ddrphy_apb_wr_32b(0x58148, 0x0); +dwc_ddrphy_apb_wr_32b(0x5814a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5814c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5814e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58150, 0x0); +dwc_ddrphy_apb_wr_32b(0x58152, 0x0); +dwc_ddrphy_apb_wr_32b(0x58154, 0x0); +dwc_ddrphy_apb_wr_32b(0x58156, 0x0); +dwc_ddrphy_apb_wr_32b(0x58158, 0x0); +dwc_ddrphy_apb_wr_32b(0x5815a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5815c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5815e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58160, 0x0); +dwc_ddrphy_apb_wr_32b(0x58162, 0x0); +dwc_ddrphy_apb_wr_32b(0x58164, 0x0); +dwc_ddrphy_apb_wr_32b(0x58166, 0x0); +dwc_ddrphy_apb_wr_32b(0x58168, 0x0); +dwc_ddrphy_apb_wr_32b(0x5816a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5816c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5816e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58170, 0x0); +dwc_ddrphy_apb_wr_32b(0x58172, 0x0); +dwc_ddrphy_apb_wr_32b(0x58174, 0x0); +dwc_ddrphy_apb_wr_32b(0x58176, 0x0); +dwc_ddrphy_apb_wr_32b(0x58178, 0x0); +dwc_ddrphy_apb_wr_32b(0x5817a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5817c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5817e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58180, 0x0); +dwc_ddrphy_apb_wr_32b(0x58182, 0x0); +dwc_ddrphy_apb_wr_32b(0x58184, 0x0); +dwc_ddrphy_apb_wr_32b(0x58186, 0x0); +dwc_ddrphy_apb_wr_32b(0x58188, 0x0); +dwc_ddrphy_apb_wr_32b(0x5818a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5818c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5818e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58190, 0x0); +dwc_ddrphy_apb_wr_32b(0x58192, 0x0); +dwc_ddrphy_apb_wr_32b(0x58194, 0x0); +dwc_ddrphy_apb_wr_32b(0x58196, 0x0); +dwc_ddrphy_apb_wr_32b(0x58198, 0x0); +dwc_ddrphy_apb_wr_32b(0x5819a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5819c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5819e, 0x0); +dwc_ddrphy_apb_wr_32b(0x581a0, 0x0); +dwc_ddrphy_apb_wr_32b(0x581a2, 0x0); +dwc_ddrphy_apb_wr_32b(0x581a4, 0x0); +dwc_ddrphy_apb_wr_32b(0x581a6, 0x0); +dwc_ddrphy_apb_wr_32b(0x581a8, 0x0); +dwc_ddrphy_apb_wr_32b(0x581aa, 0x0); +dwc_ddrphy_apb_wr_32b(0x581ac, 0x0); +dwc_ddrphy_apb_wr_32b(0x581ae, 0x0); +dwc_ddrphy_apb_wr_32b(0x581b0, 0x0); +dwc_ddrphy_apb_wr_32b(0x581b2, 0x0); +dwc_ddrphy_apb_wr_32b(0x581b4, 0x0); +dwc_ddrphy_apb_wr_32b(0x581b6, 0x0); +dwc_ddrphy_apb_wr_32b(0x581b8, 0x0); +dwc_ddrphy_apb_wr_32b(0x581ba, 0x0); +dwc_ddrphy_apb_wr_32b(0x581bc, 0x0); +dwc_ddrphy_apb_wr_32b(0x581be, 0x0); +dwc_ddrphy_apb_wr_32b(0x581c0, 0x0); +dwc_ddrphy_apb_wr_32b(0x581c2, 0x0); +dwc_ddrphy_apb_wr_32b(0x581c4, 0x0); +dwc_ddrphy_apb_wr_32b(0x581c6, 0x0); +dwc_ddrphy_apb_wr_32b(0x581c8, 0x0); +dwc_ddrphy_apb_wr_32b(0x581ca, 0x0); +dwc_ddrphy_apb_wr_32b(0x581cc, 0x0); +dwc_ddrphy_apb_wr_32b(0x581ce, 0x0); +dwc_ddrphy_apb_wr_32b(0x581d0, 0x0); +dwc_ddrphy_apb_wr_32b(0x581d2, 0x0); +dwc_ddrphy_apb_wr_32b(0x581d4, 0x0); +dwc_ddrphy_apb_wr_32b(0x581d6, 0x0); +dwc_ddrphy_apb_wr_32b(0x581d8, 0x0); +dwc_ddrphy_apb_wr_32b(0x581da, 0x0); +dwc_ddrphy_apb_wr_32b(0x581dc, 0x0); +dwc_ddrphy_apb_wr_32b(0x581de, 0x0); +dwc_ddrphy_apb_wr_32b(0x581e0, 0x0); +dwc_ddrphy_apb_wr_32b(0x581e2, 0x0); +dwc_ddrphy_apb_wr_32b(0x581e4, 0x0); +dwc_ddrphy_apb_wr_32b(0x581e6, 0x0); +dwc_ddrphy_apb_wr_32b(0x581e8, 0x0); +dwc_ddrphy_apb_wr_32b(0x581ea, 0x0); +dwc_ddrphy_apb_wr_32b(0x581ec, 0x0); +dwc_ddrphy_apb_wr_32b(0x581ee, 0x0); +dwc_ddrphy_apb_wr_32b(0x581f0, 0x0); +dwc_ddrphy_apb_wr_32b(0x581f2, 0x0); +dwc_ddrphy_apb_wr_32b(0x581f4, 0x0); +dwc_ddrphy_apb_wr_32b(0x581f6, 0x0); +dwc_ddrphy_apb_wr_32b(0x581f8, 0x0); +dwc_ddrphy_apb_wr_32b(0x581fa, 0x0); +dwc_ddrphy_apb_wr_32b(0x581fc, 0x0); +dwc_ddrphy_apb_wr_32b(0x581fe, 0x0); +//// [dwc_ddrphy_phyinit_WriteOutMem] DONE. Index 0x8000 +//// 2. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. +//// This allows the firmware unrestricted access to the configuration CSRs. +dwc_ddrphy_apb_wr(0xd0000, 0x1); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel +//// [phyinit_userCustom_wait] Wait 40 DfiClks +//// [phyinit_F_loadDMEM, 1D] End of dwc_ddrphy_phyinit_F_loadDMEM() +// +// +////############################################################## +//// +//// 4.3.7(G) Execute the Training Firmware +//// +//// The training firmware is executed with the following procedure: +//// +////############################################################## +// +// +//// 1. Reset the firmware microcontroller by writing the MicroReset CSR to set the StallToMicro and +//// ResetToMicro fields to 1 (all other fields should be zero). +//// Then rewrite the CSR so that only the StallToMicro remains set (all other fields should be zero). +dwc_ddrphy_apb_wr(0xd0000, 0x1); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel +//// [phyinit_userCustom_wait] Wait 40 DfiClks +dwc_ddrphy_apb_wr(0xd0099, 0x9); // DWC_DDRPHYA_APBONLY0_MicroReset +dwc_ddrphy_apb_wr(0xd0099, 0x1); // DWC_DDRPHYA_APBONLY0_MicroReset +// +//// 2. Begin execution of the training firmware by setting the MicroReset CSR to 4'b0000. +dwc_ddrphy_apb_wr(0xd0099, 0x0); // DWC_DDRPHYA_APBONLY0_MicroReset +// +//// 3. Wait for the training firmware to complete by following the procedure in "uCtrl Initialization and Mailbox Messaging" +//// 4.3.7 3. Wait for the training firmware to complete. Implement timeout function or follow the procedure in "3.4 Running the firmware" of the Training Firmware Application Note to poll the Mailbox message. +dwc_ddrphy_phyinit_userCustom_G_waitFwDone(sdrammc); + +//// [dwc_ddrphy_phyinit_userCustom_G_waitFwDone] End of dwc_ddrphy_phyinit_userCustom_G_waitFwDone() +//// 4. Halt the microcontroller." +dwc_ddrphy_apb_wr(0xd0099, 0x1); // DWC_DDRPHYA_APBONLY0_MicroReset +dwc_ddrphy_apb_wr(0x20089, 0x0); // DWC_DDRPHYA_MASTER0_base0_CalZap +//// [dwc_ddrphy_phyinit_G_execFW] End of dwc_ddrphy_phyinit_G_execFW() +// +// +////############################################################## +//// +//// 4.3.8(H) Read the Message Block results +//// +//// The procedure is as follows: +//// +////############################################################## +// +// +//// 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. +dwc_ddrphy_apb_wr(0xd0000, 0x0); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel +//// [phyinit_userCustom_wait] Wait 40 DfiClks +// +//2. Read the Firmware Message Block to obtain the results from the training. +//This can be accomplished by issuing APB read commands to the DMEM addresses. +//Example: +//if (Train2D) +//{ +// _read_2d_message_block_outputs_ +//} +//else +//{ +// _read_1d_message_block_outputs_ +//} +//This can be accomplished by issuing APB read commands to the DMEM addresses. +dwc_ddrphy_phyinit_userCustom_H_readMsgBlock(sdrammc, 0); + +//[dwc_ddrphy_phyinit_userCustom_H_readMsgBlock] End of dwc_ddrphy_phyinit_userCustom_H_readMsgBlock() +//// 3. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. +dwc_ddrphy_apb_wr(0xd0000, 0x1); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel +//// [phyinit_userCustom_wait] Wait 40 DfiClks +//// 4. If training is required at another frequency, repeat the operations starting at step (E). +//// [dwc_ddrphy_phyinit_H_readMsgBlock] End of dwc_ddrphy_phyinit_H_readMsgBlock() +// +// +////############################################################## +//// +//// 4.3.5(E) Set the PHY input clocks to the desired frequency for pstate 0 +//// +//// Set the PHY input Dfi Clk to the desired operating frequency associated with the given Pstate. Before proceeding to the next step, +//// the clock should be stable at the new frequency. For more information on clocking requirements, see "Clocks" on page <XXX>. +//// +////############################################################## +// +dwc_ddrphy_phyinit_userCustom_E_setDfiClk(sdrammc); + +// +//// [dwc_ddrphy_phyinit_userCustom_E_setDfiClk] End of dwc_ddrphy_phyinit_userCustom_E_setDfiClk() +//// [dwc_ddrphy_phyinit_D_loadIMEM, 2D] Start of dwc_ddrphy_phyinit_D_loadIMEM (Train2D=1) +// +// +////############################################################## +//// +//// (D) Load the 2D IMEM image +//// +//// This function loads the training firmware IMEM image into the SRAM. +//// See PhyInit App Note for detailed description and function usage +//// +////############################################################## +// +// +// [dwc_ddrphy_phyinit_storeIncvFile] Reading input file: /home/jerry_ku/Project/Development/ast2700dev/ddr45phy_tsmc12/coreConsultant/config3_3.50a/2022-12-12-16-52-55/firmware/Latest/training/ddr4_2d/ddr4_2d_pmu_train_imem.incv + +//// 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. +//// This allows the memory controller unrestricted access to the configuration CSRs. +dwc_ddrphy_apb_wr(0xd0000, 0x0); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel +//// [phyinit_userCustom_wait] Wait 40 DfiClks +//// [dwc_ddrphy_phyinit_WriteOutMem] STARTING 32bit write. offset 0x50000 size 0x8000 +dwc_ddrphy_phyinit_userCustom_D_loadIMEM(sdrammc, 1); +//// [dwc_ddrphy_phyinit_WriteOutMem] DONE. Index 0x8000 +//// 2. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. +//// This allows the firmware unrestricted access to the configuration CSRs. +dwc_ddrphy_apb_wr(0xd0000, 0x1); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel +//// [phyinit_userCustom_wait] Wait 40 DfiClks +//// [dwc_ddrphy_phyinit_D_loadIMEM, 2D] End of dwc_ddrphy_phyinit_D_loadIMEM() +//// [phyinit_F_loadDMEM, 2D] Start of dwc_ddrphy_phyinit_F_loadDMEM (pstate=0, Train2D=1) +// +// +////############################################################## +//// +//// 4.3.5(F) Load the 2D DMEM image and write the 2D Message Block parameters for the training firmware +//// +//// The procedure is as follows: +//// +////############################################################## +// +// +// +//// 1. Load the firmware DMEM segment to initialize the data structures. +// +//// 2. Write the Firmware Message Block with the required contents detailing the training parameters. +// +// [dwc_ddrphy_phyinit_storeIncvFile] Reading input file: /home/jerry_ku/Project/Development/ast2700dev/ddr45phy_tsmc12/coreConsultant/config3_3.50a/2022-12-12-16-52-55/firmware/Latest/training/ddr4_2d/ddr4_2d_pmu_train_dmem.incv + +//// 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. +//// This allows the memory controller unrestricted access to the configuration CSRs. +dwc_ddrphy_apb_wr(0xd0000, 0x0); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel +//// [phyinit_userCustom_wait] Wait 40 DfiClks +//// [dwc_ddrphy_phyinit_WriteOutMem] STARTING 32bit write. offset 0x58000 size 0x8000 +dwc_ddrphy_phyinit_userCustom_F_loadDMEM(sdrammc, 0, 1); +dwc_ddrphy_apb_wr_32b(0x58000, 0x100); +dwc_ddrphy_apb_wr_32b(0x58002, 0xc800000); +dwc_ddrphy_apb_wr_32b(0x58004, 0x0); +dwc_ddrphy_apb_wr_32b(0x58006, 0x10000240); +dwc_ddrphy_apb_wr_32b(0x58008, 0x1); +//printf("- <DWC_DDRPHY/TRAIN>: Override 2D DMEM image for SequenceCtrl, RX2D_TrainOpt, TX2D_TrainOpt, Delay_Weight2D, and Voltage_Weight2D\n"); +// uint16_t SequenceCtrl; // Byte offset 0x16, CSR Addr 0x5800b, Direction=In + // SequenceCtrl[0] = Run DevInit - Device/PHY initialization. Should always be set + // SequenceCtrl[5] = Run rd2D - 2d read dqs training + // SequenceCtrl[6] = Run wr2D - 2d write dq training +dwc_ddrphy_apb_wr_32b(0x5800a, 0x0610000); + +// Redmine 1392: To speed up data collection, set the voltage and delay step size in Rx2D_TrainOpt and Tx2D_TrainOpt to its maximum value. +// uint8_t HdtCtrl; // Byte offset 0x18, CSR Addr 0x5800c, Direction=In + // 0x04 = Maximal debug messages (e.g., Eye contours) + // 0x05 = Detailed debug messages (e.g. Eye delays) + // 0x0A = Coarse debug messages (e.g. rank information) + // 0xC8 = Stage completion + // 0xC9 = Assertion messages + // 0xFF = Firmware completion messages only +// uint8_t RX2D_TrainOpt; // Byte offset 0x19, CSR Addr 0x5800c, Direction=In +// uint8_t TX2D_TrainOpt; // Byte offset 0x1a, CSR Addr 0x5800d, Direction=In + #ifdef DWC_DEBUG +//dwc_ddrphy_apb_wr_32b(0x5800c, 0x001e1e0a); + #else +//dwc_ddrphy_apb_wr_32b(0x5800c, 0x001e1ec8); +dwc_ddrphy_apb_wr_32b(0x5800c, 0x000000c8); + #endif +// uint8_t Delay_Weight2D; // Byte offset 0x1c, CSR Addr 0x5800e, Direction=In +// uint8_t Voltage_Weight2D; // Byte offset 0x1d, CSR Addr 0x5800e, Direction=In +dwc_ddrphy_apb_wr_32b(0x5800e, 0x8020); + +dwc_ddrphy_apb_wr_32b(0x58010, 0x0); +dwc_ddrphy_apb_wr_32b(0x58012, 0x2); +dwc_ddrphy_apb_wr_32b(0x58014, 0x0); +dwc_ddrphy_apb_wr_32b(0x58016, 0x0); +dwc_ddrphy_apb_wr_32b(0x58018, 0x0); +dwc_ddrphy_apb_wr_32b(0x5801a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5801c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5801e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58020, 0x0); +dwc_ddrphy_apb_wr_32b(0x58022, 0x0); +dwc_ddrphy_apb_wr_32b(0x58024, 0x0); +dwc_ddrphy_apb_wr_32b(0x58026, 0x0); +dwc_ddrphy_apb_wr_32b(0x58028, 0x0); +dwc_ddrphy_apb_wr_32b(0x5802a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5802c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5802e, 0x21500000); +dwc_ddrphy_apb_wr_32b(0x58030, 0x2280101); +dwc_ddrphy_apb_wr_32b(0x58032, 0x400); +dwc_ddrphy_apb_wr_32b(0x58034, 0x104f0500); +dwc_ddrphy_apb_wr_32b(0x58036, 0x0); +dwc_ddrphy_apb_wr_32b(0x58038, 0x0); +dwc_ddrphy_apb_wr_32b(0x5803a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5803c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5803e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58040, 0x0); +dwc_ddrphy_apb_wr_32b(0x58042, 0xf0f0000); +dwc_ddrphy_apb_wr_32b(0x58044, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x58046, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x58048, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x5804a, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x5804c, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x5804e, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x58050, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x58052, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x58054, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x58056, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x58058, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x5805a, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x5805c, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x5805e, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x58060, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x58062, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x58064, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x58066, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x58068, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x5806a, 0xf0f); +dwc_ddrphy_apb_wr_32b(0x5806c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5806e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58070, 0x0); +dwc_ddrphy_apb_wr_32b(0x58072, 0x0); +dwc_ddrphy_apb_wr_32b(0x58074, 0x0); +dwc_ddrphy_apb_wr_32b(0x58076, 0x0); +dwc_ddrphy_apb_wr_32b(0x58078, 0x0); +dwc_ddrphy_apb_wr_32b(0x5807a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5807c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5807e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58080, 0x0); +dwc_ddrphy_apb_wr_32b(0x58082, 0x0); +dwc_ddrphy_apb_wr_32b(0x58084, 0x0); +dwc_ddrphy_apb_wr_32b(0x58086, 0x0); +dwc_ddrphy_apb_wr_32b(0x58088, 0x0); +dwc_ddrphy_apb_wr_32b(0x5808a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5808c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5808e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58090, 0x0); +dwc_ddrphy_apb_wr_32b(0x58092, 0x0); +dwc_ddrphy_apb_wr_32b(0x58094, 0x0); +dwc_ddrphy_apb_wr_32b(0x58096, 0x0); +dwc_ddrphy_apb_wr_32b(0x58098, 0x0); +dwc_ddrphy_apb_wr_32b(0x5809a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5809c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5809e, 0x0); +dwc_ddrphy_apb_wr_32b(0x580a0, 0x0); +dwc_ddrphy_apb_wr_32b(0x580a2, 0x0); +dwc_ddrphy_apb_wr_32b(0x580a4, 0x0); +dwc_ddrphy_apb_wr_32b(0x580a6, 0x0); +dwc_ddrphy_apb_wr_32b(0x580a8, 0x0); +dwc_ddrphy_apb_wr_32b(0x580aa, 0x0); +dwc_ddrphy_apb_wr_32b(0x580ac, 0x0); +dwc_ddrphy_apb_wr_32b(0x580ae, 0x0); +dwc_ddrphy_apb_wr_32b(0x580b0, 0x0); +dwc_ddrphy_apb_wr_32b(0x580b2, 0x0); +dwc_ddrphy_apb_wr_32b(0x580b4, 0x0); +dwc_ddrphy_apb_wr_32b(0x580b6, 0x0); +dwc_ddrphy_apb_wr_32b(0x580b8, 0x0); +dwc_ddrphy_apb_wr_32b(0x580ba, 0x0); +dwc_ddrphy_apb_wr_32b(0x580bc, 0x0); +dwc_ddrphy_apb_wr_32b(0x580be, 0x0); +dwc_ddrphy_apb_wr_32b(0x580c0, 0x0); +dwc_ddrphy_apb_wr_32b(0x580c2, 0x0); +dwc_ddrphy_apb_wr_32b(0x580c4, 0x0); +dwc_ddrphy_apb_wr_32b(0x580c6, 0x0); +dwc_ddrphy_apb_wr_32b(0x580c8, 0x0); +dwc_ddrphy_apb_wr_32b(0x580ca, 0x0); +dwc_ddrphy_apb_wr_32b(0x580cc, 0x0); +dwc_ddrphy_apb_wr_32b(0x580ce, 0x0); +dwc_ddrphy_apb_wr_32b(0x580d0, 0x0); +dwc_ddrphy_apb_wr_32b(0x580d2, 0x0); +dwc_ddrphy_apb_wr_32b(0x580d4, 0x0); +dwc_ddrphy_apb_wr_32b(0x580d6, 0x0); +dwc_ddrphy_apb_wr_32b(0x580d8, 0x0); +dwc_ddrphy_apb_wr_32b(0x580da, 0x0); +dwc_ddrphy_apb_wr_32b(0x580dc, 0x0); +dwc_ddrphy_apb_wr_32b(0x580de, 0x0); +dwc_ddrphy_apb_wr_32b(0x580e0, 0x0); +dwc_ddrphy_apb_wr_32b(0x580e2, 0x0); +dwc_ddrphy_apb_wr_32b(0x580e4, 0x0); +dwc_ddrphy_apb_wr_32b(0x580e6, 0x0); +dwc_ddrphy_apb_wr_32b(0x580e8, 0x0); +dwc_ddrphy_apb_wr_32b(0x580ea, 0x0); +dwc_ddrphy_apb_wr_32b(0x580ec, 0x0); +dwc_ddrphy_apb_wr_32b(0x580ee, 0x0); +dwc_ddrphy_apb_wr_32b(0x580f0, 0x0); +dwc_ddrphy_apb_wr_32b(0x580f2, 0x0); +dwc_ddrphy_apb_wr_32b(0x580f4, 0x0); +dwc_ddrphy_apb_wr_32b(0x580f6, 0x0); +dwc_ddrphy_apb_wr_32b(0x580f8, 0x0); +dwc_ddrphy_apb_wr_32b(0x580fa, 0x0); +dwc_ddrphy_apb_wr_32b(0x580fc, 0x0); +dwc_ddrphy_apb_wr_32b(0x580fe, 0x0); +dwc_ddrphy_apb_wr_32b(0x58100, 0x0); +dwc_ddrphy_apb_wr_32b(0x58102, 0x0); +dwc_ddrphy_apb_wr_32b(0x58104, 0x0); +dwc_ddrphy_apb_wr_32b(0x58106, 0x0); +dwc_ddrphy_apb_wr_32b(0x58108, 0x0); +dwc_ddrphy_apb_wr_32b(0x5810a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5810c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5810e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58110, 0x0); +dwc_ddrphy_apb_wr_32b(0x58112, 0x0); +dwc_ddrphy_apb_wr_32b(0x58114, 0x0); +dwc_ddrphy_apb_wr_32b(0x58116, 0x0); +dwc_ddrphy_apb_wr_32b(0x58118, 0x0); +dwc_ddrphy_apb_wr_32b(0x5811a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5811c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5811e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58120, 0x0); +dwc_ddrphy_apb_wr_32b(0x58122, 0x0); +dwc_ddrphy_apb_wr_32b(0x58124, 0x0); +dwc_ddrphy_apb_wr_32b(0x58126, 0x0); +dwc_ddrphy_apb_wr_32b(0x58128, 0x0); +dwc_ddrphy_apb_wr_32b(0x5812a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5812c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5812e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58130, 0x0); +dwc_ddrphy_apb_wr_32b(0x58132, 0x0); +dwc_ddrphy_apb_wr_32b(0x58134, 0x0); +dwc_ddrphy_apb_wr_32b(0x58136, 0x0); +dwc_ddrphy_apb_wr_32b(0x58138, 0x0); +dwc_ddrphy_apb_wr_32b(0x5813a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5813c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5813e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58140, 0x0); +dwc_ddrphy_apb_wr_32b(0x58142, 0x0); +dwc_ddrphy_apb_wr_32b(0x58144, 0x0); +dwc_ddrphy_apb_wr_32b(0x58146, 0x0); +dwc_ddrphy_apb_wr_32b(0x58148, 0x0); +dwc_ddrphy_apb_wr_32b(0x5814a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5814c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5814e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58150, 0x0); +dwc_ddrphy_apb_wr_32b(0x58152, 0x0); +dwc_ddrphy_apb_wr_32b(0x58154, 0x0); +dwc_ddrphy_apb_wr_32b(0x58156, 0x0); +dwc_ddrphy_apb_wr_32b(0x58158, 0x0); +dwc_ddrphy_apb_wr_32b(0x5815a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5815c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5815e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58160, 0x0); +dwc_ddrphy_apb_wr_32b(0x58162, 0x0); +dwc_ddrphy_apb_wr_32b(0x58164, 0x0); +dwc_ddrphy_apb_wr_32b(0x58166, 0x0); +dwc_ddrphy_apb_wr_32b(0x58168, 0x0); +dwc_ddrphy_apb_wr_32b(0x5816a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5816c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5816e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58170, 0x0); +dwc_ddrphy_apb_wr_32b(0x58172, 0x0); +dwc_ddrphy_apb_wr_32b(0x58174, 0x0); +dwc_ddrphy_apb_wr_32b(0x58176, 0x0); +dwc_ddrphy_apb_wr_32b(0x58178, 0x0); +dwc_ddrphy_apb_wr_32b(0x5817a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5817c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5817e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58180, 0x0); +dwc_ddrphy_apb_wr_32b(0x58182, 0x0); +dwc_ddrphy_apb_wr_32b(0x58184, 0x0); +dwc_ddrphy_apb_wr_32b(0x58186, 0x0); +dwc_ddrphy_apb_wr_32b(0x58188, 0x0); +dwc_ddrphy_apb_wr_32b(0x5818a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5818c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5818e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58190, 0x0); +dwc_ddrphy_apb_wr_32b(0x58192, 0x0); +dwc_ddrphy_apb_wr_32b(0x58194, 0x0); +dwc_ddrphy_apb_wr_32b(0x58196, 0x0); +dwc_ddrphy_apb_wr_32b(0x58198, 0x0); +dwc_ddrphy_apb_wr_32b(0x5819a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5819c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5819e, 0x0); +dwc_ddrphy_apb_wr_32b(0x581a0, 0x0); +dwc_ddrphy_apb_wr_32b(0x581a2, 0x0); +dwc_ddrphy_apb_wr_32b(0x581a4, 0x0); +dwc_ddrphy_apb_wr_32b(0x581a6, 0x0); +dwc_ddrphy_apb_wr_32b(0x581a8, 0x0); +dwc_ddrphy_apb_wr_32b(0x581aa, 0x0); +dwc_ddrphy_apb_wr_32b(0x581ac, 0x0); +dwc_ddrphy_apb_wr_32b(0x581ae, 0x0); +dwc_ddrphy_apb_wr_32b(0x581b0, 0x0); +dwc_ddrphy_apb_wr_32b(0x581b2, 0x0); +dwc_ddrphy_apb_wr_32b(0x581b4, 0x0); +dwc_ddrphy_apb_wr_32b(0x581b6, 0x0); +dwc_ddrphy_apb_wr_32b(0x581b8, 0x0); +dwc_ddrphy_apb_wr_32b(0x581ba, 0x0); +dwc_ddrphy_apb_wr_32b(0x581bc, 0x0); +dwc_ddrphy_apb_wr_32b(0x581be, 0x0); +dwc_ddrphy_apb_wr_32b(0x581c0, 0x0); +dwc_ddrphy_apb_wr_32b(0x581c2, 0x0); +dwc_ddrphy_apb_wr_32b(0x581c4, 0x0); +dwc_ddrphy_apb_wr_32b(0x581c6, 0x0); +dwc_ddrphy_apb_wr_32b(0x581c8, 0x0); +dwc_ddrphy_apb_wr_32b(0x581ca, 0x0); +dwc_ddrphy_apb_wr_32b(0x581cc, 0x0); +dwc_ddrphy_apb_wr_32b(0x581ce, 0x0); +dwc_ddrphy_apb_wr_32b(0x581d0, 0x0); +dwc_ddrphy_apb_wr_32b(0x581d2, 0x0); +dwc_ddrphy_apb_wr_32b(0x581d4, 0x0); +dwc_ddrphy_apb_wr_32b(0x581d6, 0x0); +dwc_ddrphy_apb_wr_32b(0x581d8, 0x0); +dwc_ddrphy_apb_wr_32b(0x581da, 0x0); +dwc_ddrphy_apb_wr_32b(0x581dc, 0x0); +dwc_ddrphy_apb_wr_32b(0x581de, 0x0); +dwc_ddrphy_apb_wr_32b(0x581e0, 0x0); +dwc_ddrphy_apb_wr_32b(0x581e2, 0x0); +dwc_ddrphy_apb_wr_32b(0x581e4, 0x0); +dwc_ddrphy_apb_wr_32b(0x581e6, 0x0); +dwc_ddrphy_apb_wr_32b(0x581e8, 0x0); +dwc_ddrphy_apb_wr_32b(0x581ea, 0x0); +dwc_ddrphy_apb_wr_32b(0x581ec, 0x0); +dwc_ddrphy_apb_wr_32b(0x581ee, 0x0); +dwc_ddrphy_apb_wr_32b(0x581f0, 0x0); +dwc_ddrphy_apb_wr_32b(0x581f2, 0x0); +dwc_ddrphy_apb_wr_32b(0x581f4, 0x0); +dwc_ddrphy_apb_wr_32b(0x581f6, 0x0); +dwc_ddrphy_apb_wr_32b(0x581f8, 0x0); +dwc_ddrphy_apb_wr_32b(0x581fa, 0x0); +dwc_ddrphy_apb_wr_32b(0x581fc, 0x0); +dwc_ddrphy_apb_wr_32b(0x581fe, 0x0); +//// [dwc_ddrphy_phyinit_WriteOutMem] DONE. Index 0x8000 +//// 2. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. +//// This allows the firmware unrestricted access to the configuration CSRs. +dwc_ddrphy_apb_wr(0xd0000, 0x1); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel +//// [phyinit_userCustom_wait] Wait 40 DfiClks +//// [phyinit_F_loadDMEM, 2D] End of dwc_ddrphy_phyinit_F_loadDMEM() +// +// +////############################################################## +//// +//// 4.3.7(G) Execute the Training Firmware +//// +//// The training firmware is executed with the following procedure: +//// +////############################################################## +// +// +//// 1. Reset the firmware microcontroller by writing the MicroReset CSR to set the StallToMicro and +//// ResetToMicro fields to 1 (all other fields should be zero). +//// Then rewrite the CSR so that only the StallToMicro remains set (all other fields should be zero). +dwc_ddrphy_apb_wr(0xd0000, 0x1); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel +//// [phyinit_userCustom_wait] Wait 40 DfiClks +dwc_ddrphy_apb_wr(0xd0099, 0x9); // DWC_DDRPHYA_APBONLY0_MicroReset +dwc_ddrphy_apb_wr(0xd0099, 0x1); // DWC_DDRPHYA_APBONLY0_MicroReset +// +//// 2. Begin execution of the training firmware by setting the MicroReset CSR to 4'b0000. +dwc_ddrphy_apb_wr(0xd0099, 0x0); // DWC_DDRPHYA_APBONLY0_MicroReset +// +//// 3. Wait for the training firmware to complete by following the procedure in "uCtrl Initialization and Mailbox Messaging" +//// 4.3.7 3. Wait for the training firmware to complete. Implement timeout function or follow the procedure in "3.4 Running the firmware" of the Training Firmware Application Note to poll the Mailbox message. +dwc_ddrphy_phyinit_userCustom_G_waitFwDone(sdrammc); + +//// [dwc_ddrphy_phyinit_userCustom_G_waitFwDone] End of dwc_ddrphy_phyinit_userCustom_G_waitFwDone() +//// 4. Halt the microcontroller." +dwc_ddrphy_apb_wr(0xd0099, 0x1); // DWC_DDRPHYA_APBONLY0_MicroReset +dwc_ddrphy_apb_wr(0x20089, 0x0); // DWC_DDRPHYA_MASTER0_base0_CalZap +//// [dwc_ddrphy_phyinit_G_execFW] End of dwc_ddrphy_phyinit_G_execFW() +// +// +////############################################################## +//// +//// 4.3.8(H) Read the Message Block results +//// +//// The procedure is as follows: +//// +////############################################################## +// +// +//// 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. +dwc_ddrphy_apb_wr(0xd0000, 0x0); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel +//// [phyinit_userCustom_wait] Wait 40 DfiClks +// +//2. Read the Firmware Message Block to obtain the results from the training. +//This can be accomplished by issuing APB read commands to the DMEM addresses. +//Example: +//if (Train2D) +//{ +// _read_2d_message_block_outputs_ +//} +//else +//{ +// _read_1d_message_block_outputs_ +//} +//This can be accomplished by issuing APB read commands to the DMEM addresses. +dwc_ddrphy_phyinit_userCustom_H_readMsgBlock(sdrammc, 1); + +//[dwc_ddrphy_phyinit_userCustom_H_readMsgBlock] End of dwc_ddrphy_phyinit_userCustom_H_readMsgBlock() +//// 3. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. +dwc_ddrphy_apb_wr(0xd0000, 0x1); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel +//// [phyinit_userCustom_wait] Wait 40 DfiClks +//// 4. If training is required at another frequency, repeat the operations starting at step (E). +//// [dwc_ddrphy_phyinit_H_readMsgBlock] End of dwc_ddrphy_phyinit_H_readMsgBlock() +//// [initRuntimeConfigEnableBits] Start of initRuntimeConfigEnableBits() +//// [initRuntimeConfigEnableBits] enableBits[0] = 0x00000009 +//// [initRuntimeConfigEnableBits] WR_RD_RTT_PARK_A0 = 0x000000ff, rtt_required = 0x0000000f +//// [initRuntimeConfigEnableBits] WR_RD_RTT_PARK_A1 = 0x000000ff, rtt_required = 0x0000000f +//// [initRuntimeConfigEnableBits] WR_RD_RTT_PARK_A2 = 0x000000ff, rtt_required = 0x0000000f +//// [initRuntimeConfigEnableBits] WR_RD_RTT_PARK_A3 = 0x000000ff, rtt_required = 0x0000000f +//// [initRuntimeConfigEnableBits] enableBits[1] = 0x00000000 +//// [initRuntimeConfigEnableBits] WR_RD_RTT_PARK_B0 = 0x000000ff, rtt_required = 0x0000000f +//// [initRuntimeConfigEnableBits] WR_RD_RTT_PARK_B1 = 0x000000ff, rtt_required = 0x0000000f +//// [initRuntimeConfigEnableBits] WR_RD_RTT_PARK_B2 = 0x000000ff, rtt_required = 0x0000000f +//// [initRuntimeConfigEnableBits] WR_RD_RTT_PARK_B3 = 0x000000ff, rtt_required = 0x0000000f +//// [initRuntimeConfigEnableBits] enableBits[2] = 0x00000000 +//// [initRuntimeConfigEnableBits] End of initRuntimeConfigEnableBits() +//// [phyinit_I_loadPIEImage] Start of dwc_ddrphy_phyinit_I_loadPIEImage() +// +// +////############################################################## +//// +//// 4.3.9(I) Load PHY Init Engine Image +//// +//// Load the PHY Initialization Engine memory with the provided initialization sequence. +//// +////############################################################## +// +// +//// Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. +//// This allows the memory controller unrestricted access to the configuration CSRs. +dwc_ddrphy_apb_wr(0xd0000, 0x0); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel +//// [phyinit_userCustom_wait] Wait 40 DfiClks +//// [phyinit_I_loadPIEImage] Programming ForceClkGaterEnables::ForcePubDxClkEnLow to 0x1 +dwc_ddrphy_apb_wr(0x200a6, 0x2); // DWC_DDRPHYA_MASTER0_base0_ForceClkGaterEnables +//// [phyinit_I_loadPIEImage] Programming PIE Production Code +//// [phyinit_LoadPIECodeSections] Start of dwc_ddrphy_phyinit_LoadPIECodeSections() +//// [phyinit_LoadPIECodeSections] Moving start address from 0 to 90000 +dwc_ddrphy_apb_wr(0x90000, 0x10); // DWC_DDRPHYA_INITENG0_base0_PreSequenceReg0b0s0 +dwc_ddrphy_apb_wr(0x90001, 0x400); // DWC_DDRPHYA_INITENG0_base0_PreSequenceReg0b0s1 +dwc_ddrphy_apb_wr(0x90002, 0x10e); // DWC_DDRPHYA_INITENG0_base0_PreSequenceReg0b0s2 +dwc_ddrphy_apb_wr(0x90003, 0x0); // DWC_DDRPHYA_INITENG0_base0_PreSequenceReg0b1s0 +dwc_ddrphy_apb_wr(0x90004, 0x0); // DWC_DDRPHYA_INITENG0_base0_PreSequenceReg0b1s1 +dwc_ddrphy_apb_wr(0x90005, 0x8); // DWC_DDRPHYA_INITENG0_base0_PreSequenceReg0b1s2 +//// [phyinit_LoadPIECodeSections] Moving start address from 90006 to 90029 +dwc_ddrphy_apb_wr(0x90029, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b0s0 +dwc_ddrphy_apb_wr(0x9002a, 0x4); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b0s1 +dwc_ddrphy_apb_wr(0x9002b, 0x18); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b0s2 +dwc_ddrphy_apb_wr(0x9002c, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b1s0 +dwc_ddrphy_apb_wr(0x9002d, 0x4); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b1s1 +dwc_ddrphy_apb_wr(0x9002e, 0x18); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b1s2 +dwc_ddrphy_apb_wr(0x9002f, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b2s0 +dwc_ddrphy_apb_wr(0x90030, 0x4); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b2s1 +dwc_ddrphy_apb_wr(0x90031, 0x18); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b2s2 +dwc_ddrphy_apb_wr(0x90032, 0xb); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b3s0 +dwc_ddrphy_apb_wr(0x90033, 0x480); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b3s1 +dwc_ddrphy_apb_wr(0x90034, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b3s2 +dwc_ddrphy_apb_wr(0x90035, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b4s0 +dwc_ddrphy_apb_wr(0x90036, 0x448); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b4s1 +dwc_ddrphy_apb_wr(0x90037, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b4s2 +dwc_ddrphy_apb_wr(0x90038, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b5s0 +dwc_ddrphy_apb_wr(0x90039, 0x478); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b5s1 +dwc_ddrphy_apb_wr(0x9003a, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b5s2 +dwc_ddrphy_apb_wr(0x9003b, 0x2); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b6s0 +dwc_ddrphy_apb_wr(0x9003c, 0x10); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b6s1 +dwc_ddrphy_apb_wr(0x9003d, 0x139); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b6s2 +dwc_ddrphy_apb_wr(0x9003e, 0xf); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b7s0 +dwc_ddrphy_apb_wr(0x9003f, 0x7c0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b7s1 +dwc_ddrphy_apb_wr(0x90040, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b7s2 +dwc_ddrphy_apb_wr(0x90041, 0x107); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b8s0 +dwc_ddrphy_apb_wr(0x90042, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b8s1 +dwc_ddrphy_apb_wr(0x90043, 0x159); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b8s2 +dwc_ddrphy_apb_wr(0x90044, 0x18); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b9s0 +dwc_ddrphy_apb_wr(0x90045, 0xe0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b9s1 +dwc_ddrphy_apb_wr(0x90046, 0x139); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b9s2 +dwc_ddrphy_apb_wr(0x90047, 0x147); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b10s0 +dwc_ddrphy_apb_wr(0x90048, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b10s1 +dwc_ddrphy_apb_wr(0x90049, 0x159); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b10s2 +dwc_ddrphy_apb_wr(0x9004a, 0x14f); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b11s0 +dwc_ddrphy_apb_wr(0x9004b, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b11s1 +dwc_ddrphy_apb_wr(0x9004c, 0x159); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b11s2 +dwc_ddrphy_apb_wr(0x9004d, 0x7); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b12s0 +dwc_ddrphy_apb_wr(0x9004e, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b12s1 +dwc_ddrphy_apb_wr(0x9004f, 0x149); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b12s2 +dwc_ddrphy_apb_wr(0x90050, 0x47); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b13s0 +dwc_ddrphy_apb_wr(0x90051, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b13s1 +dwc_ddrphy_apb_wr(0x90052, 0x149); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b13s2 +dwc_ddrphy_apb_wr(0x90053, 0x4f); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b14s0 +dwc_ddrphy_apb_wr(0x90054, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b14s1 +dwc_ddrphy_apb_wr(0x90055, 0x179); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b14s2 +dwc_ddrphy_apb_wr(0x90056, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b15s0 +dwc_ddrphy_apb_wr(0x90057, 0x7c8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b15s1 +dwc_ddrphy_apb_wr(0x90058, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b15s2 +dwc_ddrphy_apb_wr(0x90059, 0x11); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b16s0 +dwc_ddrphy_apb_wr(0x9005a, 0x530); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b16s1 +dwc_ddrphy_apb_wr(0x9005b, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b16s2 +dwc_ddrphy_apb_wr(0x9005c, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b17s0 +dwc_ddrphy_apb_wr(0x9005d, 0x1); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b17s1 +dwc_ddrphy_apb_wr(0x9005e, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b17s2 +dwc_ddrphy_apb_wr(0x9005f, 0x14f); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b18s0 +dwc_ddrphy_apb_wr(0x90060, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b18s1 +dwc_ddrphy_apb_wr(0x90061, 0x159); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b18s2 +dwc_ddrphy_apb_wr(0x90062, 0x2); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b19s0 +dwc_ddrphy_apb_wr(0x90063, 0x45a); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b19s1 +dwc_ddrphy_apb_wr(0x90064, 0x9); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b19s2 +dwc_ddrphy_apb_wr(0x90065, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b20s0 +dwc_ddrphy_apb_wr(0x90066, 0x530); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b20s1 +dwc_ddrphy_apb_wr(0x90067, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b20s2 +dwc_ddrphy_apb_wr(0x90068, 0x18); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b21s0 +dwc_ddrphy_apb_wr(0x90069, 0x65a); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b21s1 +dwc_ddrphy_apb_wr(0x9006a, 0x9); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b21s2 +dwc_ddrphy_apb_wr(0x9006b, 0x41); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b22s0 +dwc_ddrphy_apb_wr(0x9006c, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b22s1 +dwc_ddrphy_apb_wr(0x9006d, 0x179); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b22s2 +dwc_ddrphy_apb_wr(0x9006e, 0x1); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b23s0 +dwc_ddrphy_apb_wr(0x9006f, 0x618); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b23s1 +dwc_ddrphy_apb_wr(0x90070, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b23s2 +dwc_ddrphy_apb_wr(0x90071, 0x40c0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b24s0 +dwc_ddrphy_apb_wr(0x90072, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b24s1 +dwc_ddrphy_apb_wr(0x90073, 0x149); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b24s2 +dwc_ddrphy_apb_wr(0x90074, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b25s0 +dwc_ddrphy_apb_wr(0x90075, 0x4); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b25s1 +dwc_ddrphy_apb_wr(0x90076, 0x48); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b25s2 +dwc_ddrphy_apb_wr(0x90077, 0x4040); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b26s0 +dwc_ddrphy_apb_wr(0x90078, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b26s1 +dwc_ddrphy_apb_wr(0x90079, 0x149); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b26s2 +dwc_ddrphy_apb_wr(0x9007a, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b27s0 +dwc_ddrphy_apb_wr(0x9007b, 0x4); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b27s1 +dwc_ddrphy_apb_wr(0x9007c, 0x48); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b27s2 +dwc_ddrphy_apb_wr(0x9007d, 0x40); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b28s0 +dwc_ddrphy_apb_wr(0x9007e, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b28s1 +dwc_ddrphy_apb_wr(0x9007f, 0x149); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b28s2 +dwc_ddrphy_apb_wr(0x90080, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b29s0 +dwc_ddrphy_apb_wr(0x90081, 0x658); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b29s1 +dwc_ddrphy_apb_wr(0x90082, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b29s2 +dwc_ddrphy_apb_wr(0x90083, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b30s0 +dwc_ddrphy_apb_wr(0x90084, 0x4); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b30s1 +dwc_ddrphy_apb_wr(0x90085, 0x18); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b30s2 +dwc_ddrphy_apb_wr(0x90086, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b31s0 +dwc_ddrphy_apb_wr(0x90087, 0x4); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b31s1 +dwc_ddrphy_apb_wr(0x90088, 0x78); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b31s2 +dwc_ddrphy_apb_wr(0x90089, 0x549); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b32s0 +dwc_ddrphy_apb_wr(0x9008a, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b32s1 +dwc_ddrphy_apb_wr(0x9008b, 0x159); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b32s2 +dwc_ddrphy_apb_wr(0x9008c, 0xd49); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b33s0 +dwc_ddrphy_apb_wr(0x9008d, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b33s1 +dwc_ddrphy_apb_wr(0x9008e, 0x159); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b33s2 +dwc_ddrphy_apb_wr(0x9008f, 0x94c); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b34s0 +dwc_ddrphy_apb_wr(0x90090, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b34s1 +dwc_ddrphy_apb_wr(0x90091, 0x159); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b34s2 +dwc_ddrphy_apb_wr(0x90092, 0x94c); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b35s0 +dwc_ddrphy_apb_wr(0x90093, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b35s1 +dwc_ddrphy_apb_wr(0x90094, 0x159); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b35s2 +dwc_ddrphy_apb_wr(0x90095, 0x442); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b36s0 +dwc_ddrphy_apb_wr(0x90096, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b36s1 +dwc_ddrphy_apb_wr(0x90097, 0x149); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b36s2 +dwc_ddrphy_apb_wr(0x90098, 0x42); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b37s0 +dwc_ddrphy_apb_wr(0x90099, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b37s1 +dwc_ddrphy_apb_wr(0x9009a, 0x149); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b37s2 +dwc_ddrphy_apb_wr(0x9009b, 0x1); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b38s0 +dwc_ddrphy_apb_wr(0x9009c, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b38s1 +dwc_ddrphy_apb_wr(0x9009d, 0x149); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b38s2 +dwc_ddrphy_apb_wr(0x9009e, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b39s0 +dwc_ddrphy_apb_wr(0x9009f, 0xe0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b39s1 +dwc_ddrphy_apb_wr(0x900a0, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b39s2 +dwc_ddrphy_apb_wr(0x900a1, 0xa); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b40s0 +dwc_ddrphy_apb_wr(0x900a2, 0x10); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b40s1 +dwc_ddrphy_apb_wr(0x900a3, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b40s2 +dwc_ddrphy_apb_wr(0x900a4, 0x9); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b41s0 +dwc_ddrphy_apb_wr(0x900a5, 0x3c0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b41s1 +dwc_ddrphy_apb_wr(0x900a6, 0x149); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b41s2 +dwc_ddrphy_apb_wr(0x900a7, 0x9); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b42s0 +dwc_ddrphy_apb_wr(0x900a8, 0x3c0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b42s1 +dwc_ddrphy_apb_wr(0x900a9, 0x159); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b42s2 +dwc_ddrphy_apb_wr(0x900aa, 0x18); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b43s0 +dwc_ddrphy_apb_wr(0x900ab, 0x10); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b43s1 +dwc_ddrphy_apb_wr(0x900ac, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b43s2 +dwc_ddrphy_apb_wr(0x900ad, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b44s0 +dwc_ddrphy_apb_wr(0x900ae, 0x3c0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b44s1 +dwc_ddrphy_apb_wr(0x900af, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b44s2 +dwc_ddrphy_apb_wr(0x900b0, 0x18); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b45s0 +dwc_ddrphy_apb_wr(0x900b1, 0x4); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b45s1 +dwc_ddrphy_apb_wr(0x900b2, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b45s2 +dwc_ddrphy_apb_wr(0x900b3, 0xc); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b46s0 +dwc_ddrphy_apb_wr(0x900b4, 0x10); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b46s1 +dwc_ddrphy_apb_wr(0x900b5, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b46s2 +dwc_ddrphy_apb_wr(0x900b6, 0x3); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b47s0 +dwc_ddrphy_apb_wr(0x900b7, 0x10); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b47s1 +dwc_ddrphy_apb_wr(0x900b8, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b47s2 +dwc_ddrphy_apb_wr(0x900b9, 0x7); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b48s0 +dwc_ddrphy_apb_wr(0x900ba, 0x7c0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b48s1 +dwc_ddrphy_apb_wr(0x900bb, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b48s2 +//// [phyinit_LoadPIECodeSections] Matched ANY enable_bits = 8, type = 0 +dwc_ddrphy_apb_wr(0x900bc, 0x3a); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b49s0 +dwc_ddrphy_apb_wr(0x900bd, 0x1e2); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b49s1 +dwc_ddrphy_apb_wr(0x900be, 0x9); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b49s2 +dwc_ddrphy_apb_wr(0x900bf, 0x10); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b50s0 +dwc_ddrphy_apb_wr(0x900c0, 0x10); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b50s1 +dwc_ddrphy_apb_wr(0x900c1, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b50s2 +dwc_ddrphy_apb_wr(0x900c2, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b51s0 +dwc_ddrphy_apb_wr(0x900c3, 0x8140); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b51s1 +dwc_ddrphy_apb_wr(0x900c4, 0x10c); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b51s2 +dwc_ddrphy_apb_wr(0x900c5, 0x10); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b52s0 +dwc_ddrphy_apb_wr(0x900c6, 0x8138); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b52s1 +dwc_ddrphy_apb_wr(0x900c7, 0x10c); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b52s2 +//// [phyinit_LoadPIECodeSections] Matched ANY enable_bits = 1, type = 0 +dwc_ddrphy_apb_wr(0x900c8, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b53s0 +dwc_ddrphy_apb_wr(0x900c9, 0x400); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b53s1 +dwc_ddrphy_apb_wr(0x900ca, 0x10e); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b53s2 +dwc_ddrphy_apb_wr(0x900cb, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b54s0 +dwc_ddrphy_apb_wr(0x900cc, 0x448); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b54s1 +dwc_ddrphy_apb_wr(0x900cd, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b54s2 +dwc_ddrphy_apb_wr(0x900ce, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b55s0 +dwc_ddrphy_apb_wr(0x900cf, 0x7c8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b55s1 +dwc_ddrphy_apb_wr(0x900d0, 0x101); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b55s2 +dwc_ddrphy_apb_wr(0x900d1, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b56s0 +dwc_ddrphy_apb_wr(0x900d2, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b56s1 +dwc_ddrphy_apb_wr(0x900d3, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b56s2 +dwc_ddrphy_apb_wr(0x900d4, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b57s0 +dwc_ddrphy_apb_wr(0x900d5, 0x448); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b57s1 +dwc_ddrphy_apb_wr(0x900d6, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b57s2 +dwc_ddrphy_apb_wr(0x900d7, 0xf); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b58s0 +dwc_ddrphy_apb_wr(0x900d8, 0x7c0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b58s1 +dwc_ddrphy_apb_wr(0x900d9, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b58s2 +dwc_ddrphy_apb_wr(0x900da, 0x7); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b59s0 +dwc_ddrphy_apb_wr(0x900db, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b59s1 +dwc_ddrphy_apb_wr(0x900dc, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b59s2 +dwc_ddrphy_apb_wr(0x900dd, 0x47); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b60s0 +dwc_ddrphy_apb_wr(0x900de, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b60s1 +dwc_ddrphy_apb_wr(0x900df, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b60s2 +dwc_ddrphy_apb_wr(0x900e0, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b61s0 +dwc_ddrphy_apb_wr(0x900e1, 0x618); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b61s1 +dwc_ddrphy_apb_wr(0x900e2, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b61s2 +dwc_ddrphy_apb_wr(0x900e3, 0x18); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b62s0 +dwc_ddrphy_apb_wr(0x900e4, 0xe0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b62s1 +dwc_ddrphy_apb_wr(0x900e5, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b62s2 +dwc_ddrphy_apb_wr(0x900e6, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b63s0 +dwc_ddrphy_apb_wr(0x900e7, 0x7c8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b63s1 +dwc_ddrphy_apb_wr(0x900e8, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b63s2 +dwc_ddrphy_apb_wr(0x900e9, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b64s0 +dwc_ddrphy_apb_wr(0x900ea, 0x8140); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b64s1 +dwc_ddrphy_apb_wr(0x900eb, 0x10c); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b64s2 +dwc_ddrphy_apb_wr(0x900ec, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b65s0 +dwc_ddrphy_apb_wr(0x900ed, 0x478); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b65s1 +dwc_ddrphy_apb_wr(0x900ee, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b65s2 +dwc_ddrphy_apb_wr(0x900ef, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b66s0 +dwc_ddrphy_apb_wr(0x900f0, 0x1); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b66s1 +dwc_ddrphy_apb_wr(0x900f1, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b66s2 +dwc_ddrphy_apb_wr(0x900f2, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b67s0 +dwc_ddrphy_apb_wr(0x900f3, 0x4); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b67s1 +dwc_ddrphy_apb_wr(0x900f4, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b67s2 +dwc_ddrphy_apb_wr(0x900f5, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b68s0 +dwc_ddrphy_apb_wr(0x900f6, 0x7c8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b68s1 +dwc_ddrphy_apb_wr(0x900f7, 0x101); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b68s2 +//// [phyinit_LoadPIECodeSections] Moving start address from 900f8 to 90006 +dwc_ddrphy_apb_wr(0x90006, 0x0); // DWC_DDRPHYA_INITENG0_base0_PostSequenceReg0b0s0 +dwc_ddrphy_apb_wr(0x90007, 0x0); // DWC_DDRPHYA_INITENG0_base0_PostSequenceReg0b0s1 +dwc_ddrphy_apb_wr(0x90008, 0x8); // DWC_DDRPHYA_INITENG0_base0_PostSequenceReg0b0s2 +dwc_ddrphy_apb_wr(0x90009, 0x0); // DWC_DDRPHYA_INITENG0_base0_PostSequenceReg0b1s0 +dwc_ddrphy_apb_wr(0x9000a, 0x0); // DWC_DDRPHYA_INITENG0_base0_PostSequenceReg0b1s1 +dwc_ddrphy_apb_wr(0x9000b, 0x0); // DWC_DDRPHYA_INITENG0_base0_PostSequenceReg0b1s2 +//// [phyinit_LoadPIECodeSections] Moving start address from 9000c to d00e7 +dwc_ddrphy_apb_wr(0xd00e7, 0x400); // DWC_DDRPHYA_APBONLY0_SequencerOverride +//// [phyinit_LoadPIECodeSections] End of dwc_ddrphy_phyinit_LoadPIECodeSections() +//seq0b_LoadPstateSeqProductionCode(): --------------------------------------------------------------------------------------------------- +//seq0b_LoadPstateSeqProductionCode(): Programming the 0B sequencer 0b0000 start vector registers with 0. +//seq0b_LoadPstateSeqProductionCode(): Programming the 0B sequencer 0b1111 start vector register with 56. +//seq0b_LoadPstateSeqProductionCode(): --------------------------------------------------------------------------------------------------- +dwc_ddrphy_apb_wr(0x90017, 0x0); // DWC_DDRPHYA_INITENG0_base0_StartVector0b0 +dwc_ddrphy_apb_wr(0x90026, 0x38); // DWC_DDRPHYA_INITENG0_base0_StartVector0b15 +dwc_ddrphy_apb_wr(0x9000c, 0x0); // DWC_DDRPHYA_INITENG0_base0_Seq0BDisableFlag0 +dwc_ddrphy_apb_wr(0x9000d, 0x173); // DWC_DDRPHYA_INITENG0_base0_Seq0BDisableFlag1 +dwc_ddrphy_apb_wr(0x9000e, 0x60); // DWC_DDRPHYA_INITENG0_base0_Seq0BDisableFlag2 +dwc_ddrphy_apb_wr(0x9000f, 0x6110); // DWC_DDRPHYA_INITENG0_base0_Seq0BDisableFlag3 +dwc_ddrphy_apb_wr(0x90010, 0x2152); // DWC_DDRPHYA_INITENG0_base0_Seq0BDisableFlag4 +dwc_ddrphy_apb_wr(0x90011, 0xdfbd); // DWC_DDRPHYA_INITENG0_base0_Seq0BDisableFlag5 +dwc_ddrphy_apb_wr(0x90012, 0xffff); // DWC_DDRPHYA_INITENG0_base0_Seq0BDisableFlag6 +dwc_ddrphy_apb_wr(0x90013, 0x6152); // DWC_DDRPHYA_INITENG0_base0_Seq0BDisableFlag7 +//// [phyinit_I_loadPIEImage] Programming D4PowerControl::D4CATxDllLP to 0x1 +//// [phyinit_I_loadPIEImage] Programming AcLcdlMasDis to 0xfff +dwc_ddrphy_apb_wr(0x2006d, 0x1); // DWC_DDRPHYA_MASTER0_base0_D4PowerControl +dwc_ddrphy_apb_wr(0x200e8, 0xfff); // DWC_DDRPHYA_MASTER0_base0_AcLcdlMasDis +//// [phyinit_I_loadPIEImage] Turn on calibration and hold idle until dfi_init_start is asserted sequence is triggered. +//// [phyinit_I_loadPIEImage] Programming CalZap to 0x1 +//// [phyinit_I_loadPIEImage] Programming CalRate::CalRun to 0x1 +//// [phyinit_I_loadPIEImage] Programming CalRate to 0x19 +dwc_ddrphy_apb_wr(0x20089, 0x1); // DWC_DDRPHYA_MASTER0_base0_CalZap +dwc_ddrphy_apb_wr(0x20088, 0x19); // DWC_DDRPHYA_MASTER0_base0_CalRate +//// [phyinit_I_loadPIEImage] Programming ForceClkGaterEnables::ForcePubDxClkEnLow to 0x0 +dwc_ddrphy_apb_wr(0x200a6, 0x0); // DWC_DDRPHYA_MASTER0_base0_ForceClkGaterEnables +//// Disabling Ucclk (PMU) and Hclk (training hardware) +dwc_ddrphy_apb_wr(0xc0080, 0x0); // DWC_DDRPHYA_DRTUB0_UcclkHclkEnables +//// Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. +dwc_ddrphy_apb_wr(0xd0000, 0x1); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel +//// [phyinit_userCustom_wait] Wait 40 DfiClks +//// [phyinit_I_loadPIEImage] End of dwc_ddrphy_phyinit_I_loadPIEImage() +// +// +////############################################################## +//// +//// dwc_ddrphy_phyinit_userCustom_customPostTrain is a user-editable function. +//// +//// The purpose of dwc_ddrphy_phyinit_userCustom_customPostTrain() is to override any +//// CSR values programmed by the training firmware or dwc_ddrphy_phyinit_progCsrSkipTrain() +//// This function is executed after training +//// +//// IMPORTANT: in this function, user shall not override any values in userInputBasic and +//// userInputAdvanced data structures. Only CSR programming should be done in this function. +//// +//// Sequence of Events in this function are: +//// 1. Enable APB access. +//// 2. Issue register writes +//// 3. Isolate APB access. +// +////############################################################## +// +dwc_ddrphy_phyinit_userCustom_customPostTrain(); + +//// [dwc_ddrphy_phyinit_userCustom_customPostTrain] End of dwc_ddrphy_phyinit_userCustom_customPostTrain() +//// [dwc_ddrphy_phyinit_userCustom_J_enterMissionMode] Start of dwc_ddrphy_phyinit_userCustom_J_enterMissionMode() +// +// +////############################################################## +//// +//// 4.3.10(J) Initialize the PHY to Mission Mode through DFI Initialization +//// +//// Initialize the PHY to mission mode as follows: +//// +//// 1. Set the PHY input clocks to the desired frequency. +//// 2. Initialize the PHY to mission mode by performing DFI Initialization. +//// Please see the DFI specification for more information. See the DFI frequency bus encoding in section <XXX>. +//// Note: The PHY training firmware initializes the DRAM state. if skip +//// training is used, the DRAM state is not initialized. +//// +////############################################################## +// +dwc_ddrphy_phyinit_userCustom_J_enterMissionMode(sdrammc); + +// +//// [dwc_ddrphy_phyinit_userCustom_J_enterMissionMode] End of dwc_ddrphy_phyinit_userCustom_J_enterMissionMode() +// [dwc_ddrphy_phyinit_sequence] End of dwc_ddrphy_phyinit_sequence() +// [dwc_ddrphy_phyinit_main] End of dwc_ddrphy_phyinit_main() diff --git a/drivers/ram/aspeed/dwc_ddrphy_phyinit_ddr5-3200-nodimm-train2D.c b/drivers/ram/aspeed/dwc_ddrphy_phyinit_ddr5-3200-nodimm-train2D.c new file mode 100644 index 00000000000..d21bcda6fb8 --- /dev/null +++ b/drivers/ram/aspeed/dwc_ddrphy_phyinit_ddr5-3200-nodimm-train2D.c @@ -0,0 +1,6930 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) ASPEED Technology Inc. + */ +// [dwc_ddrphy_phyinit_main] Start of dwc_ddrphy_phyinit_main() +// [dwc_ddrphy_phyinit_sequence] Start of dwc_ddrphy_phyinit_sequence() +// [dwc_ddrphy_phyinit_initStruct] Start of dwc_ddrphy_phyinit_initStruct() +// [dwc_ddrphy_phyinit_initStruct] End of dwc_ddrphy_phyinit_initStruct() +// [dwc_ddrphy_phyinit_setDefault] Start of dwc_ddrphy_phyinit_setDefault() +// [dwc_ddrphy_phyinit_setDefault] End of dwc_ddrphy_phyinit_setDefault() + +////############################################################## +// +//// dwc_ddrphy_phyinit_userCustom_overrideUserInput is a user-editable function. User can edit this function according to their needs. +//// +//// The purpose of dwc_ddrphy_phyinit_userCustom_overrideUserInput() is to override any +//// any field in Phyinit data structure set by dwc_ddrphy_phyinit_setDefault() +//// User should only override values in userInputBasic and userInputAdvanced. +//// IMPORTANT: in this function, user shall not override any values in the +//// messageblock directly on the data structue as the might be overwritten by +//// dwc_ddrphy_phyinit_calcMb(). Use dwc_ddrphy_phyinit_setMb() to set +//// messageblock parameters for override values to remain pervasive if +//// desired +// +////############################################################## + +dwc_ddrphy_phyinit_userCustom_overrideUserInput(); +// +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'DramType' to 0x1 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'DimmType' to 0x4 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'NumDbyte' to 0x2 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'NumActiveDbyteDfi0' to 0x2 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'NumActiveDbyteDfi1' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'NumAnib' to 0xa +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'NumRank_dfi0' to 0x1 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'NumRank_dfi1' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'DramDataWidth[0]' to 0x10 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'DramDataWidth[1]' to 0x10 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'DramDataWidth[2]' to 0x10 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'DramDataWidth[3]' to 0x10 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'NumPStates' to 0x1 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'Frequency[0]' to 0x640 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'PllBypass[0]' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'DfiFreqRatio[0]' to 0x1 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'Dfi1Exists' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'ExtCalResVal' to 0xf0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'ODTImpedance[0]' to 0x78 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'TxImpedance[0]' to 0x3c +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'MemAlertEn' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'MtestPUImp' to 0xf0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'DisDynAdrTri[0]' to 0x1 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'PhyMstrTrainInterval[0]' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'PhyMstrMaxReqToAck[0]' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'PhyMstrCtrlMode[0]' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'WDQSExt' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'CalInterval' to 0x9 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'CalOnce' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'RxEnBackOff' to 0x1 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'TrainSequenceCtrl' to 0x837f +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'SnpsUmctlOpt' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'SnpsUmctlF0RC5x[0]' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'TxSlewRiseDQ[0]' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'TxSlewFallDQ[0]' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'TxSlewRiseAC' to 0x66 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'TxSlewFallAC' to 0x26 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'IsHighVDD' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'TxSlewRiseCK' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'TxSlewFallCK' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'EnTdqs2dqTrackingTg0[0]' to 0x1 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'EnTdqs2dqTrackingTg1[0]' to 0x1 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'EnTdqs2dqTrackingTg2[0]' to 0x1 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'EnTdqs2dqTrackingTg3[0]' to 0x1 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'DqsOscRunTimeSel[0]' to 0x100 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'EnRxDqsTracking[0]' to 0x1 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'D5TxDqPreambleCtrl[0]' to 0x1 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'D5DisableRetraining' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'DisablePmuEcc' to 0x1 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'EnableMAlertAsync' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'Apb32BitMode' to 0x1 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'tDQS2DQ' to 0x2ee +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'tDQSCK' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'tCASL_override' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'tCASL_add[0][0]' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'tCASL_add[0][1]' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'tCASL_add[0][2]' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'tCASL_add[0][3]' to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MsgMisc to 0x7 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].Pstate to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].PllBypassEn to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].DRAMFreq to 0xc80 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].PhyVref to 0x40 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].D5Misc to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].WL_ADJ to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].SequenceCtrl to 0x837f +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].HdtCtrl to 0xc8 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].PhyCfg to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].DFIMRLMargin to 0x2 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].X16Present to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].UseBroadcastMR to 0x1 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].DisabledDbyte to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].CATrainOpt to 0x8 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].PhyConfigOverride to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].EnabledDQsChA to 0x10 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].CsPresentChA to 0x1 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR0_A0 to 0x8 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR2_A0 to 0x4 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR3_A0 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR4_A0 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR5_A0 to 0x20 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR6_A0 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR8_A0 to 0x8 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR10_A0 to 0x2d +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR11_A0 to 0x2d +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR12_A0 to 0xd6 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR13_A0 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR14_A0 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR15_A0 to 0x3 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR111_A0 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR32_A0 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR33_A0 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR34_A0 to 0x11 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR35_A0 to 0x4 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR37_A0 to 0x2c +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR38_A0 to 0x2c +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR39_A0 to 0x2c +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR50_A0 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR51_A0 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR52_A0 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR0_A1 to 0x8 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR2_A1 to 0x4 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR3_A1 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR4_A1 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR5_A1 to 0x20 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR6_A1 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR8_A1 to 0x8 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR10_A1 to 0x2d +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR11_A1 to 0x2d +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR12_A1 to 0xd6 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR13_A1 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR14_A1 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR15_A1 to 0x3 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR111_A1 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR32_A1 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR33_A1 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR34_A1 to 0x11 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR35_A1 to 0x4 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR37_A1 to 0x2c +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR38_A1 to 0x2c +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR39_A1 to 0x2c +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR50_A1 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR51_A1 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR52_A1 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR0_A2 to 0x8 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR2_A2 to 0x4 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR3_A2 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR4_A2 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR5_A2 to 0x20 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR6_A2 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR8_A2 to 0x8 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR10_A2 to 0x2d +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR11_A2 to 0x2d +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR12_A2 to 0xd6 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR13_A2 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR14_A2 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR15_A2 to 0x3 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR111_A2 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR32_A2 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR33_A2 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR34_A2 to 0x11 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR35_A2 to 0x4 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR37_A2 to 0x2c +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR38_A2 to 0x2c +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR39_A2 to 0x2c +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR50_A2 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR51_A2 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR52_A2 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR0_A3 to 0x8 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR2_A3 to 0x4 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR3_A3 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR4_A3 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR5_A3 to 0x20 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR6_A3 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR8_A3 to 0x8 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR10_A3 to 0x2d +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR11_A3 to 0x2d +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR12_A3 to 0xd6 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR13_A3 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR14_A3 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR15_A3 to 0x3 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR111_A3 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR32_A3 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR33_A3 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR34_A3 to 0x11 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR35_A3 to 0x4 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR37_A3 to 0x2c +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR38_A3 to 0x2c +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR39_A3 to 0x2c +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR50_A3 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR51_A3 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR52_A3 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].EnabledDQsChB to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].CsPresentChB to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR0_B0 to 0x8 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR2_B0 to 0x4 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR3_B0 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR4_B0 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR5_B0 to 0x20 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR6_B0 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR8_B0 to 0x8 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR10_B0 to 0x2d +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR11_B0 to 0x2d +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR12_B0 to 0xd6 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR13_B0 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR14_B0 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR15_B0 to 0x3 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR111_B0 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR32_B0 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR33_B0 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR34_B0 to 0x11 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR35_B0 to 0x4 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR37_B0 to 0x2c +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR38_B0 to 0x2c +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR39_B0 to 0x2c +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR50_B0 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR51_B0 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR52_B0 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR0_B1 to 0x8 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR2_B1 to 0x4 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR3_B1 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR4_B1 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR5_B1 to 0x20 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR6_B1 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR8_B1 to 0x8 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR10_B1 to 0x2d +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR11_B1 to 0x2d +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR12_B1 to 0xd6 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR13_B1 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR14_B1 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR15_B1 to 0x3 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR111_B1 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR32_B1 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR33_B1 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR34_B1 to 0x11 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR35_B1 to 0x4 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR37_B1 to 0x2c +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR38_B1 to 0x2c +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR39_B1 to 0x2c +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR50_B1 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR51_B1 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR52_B1 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR0_B2 to 0x8 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR2_B2 to 0x4 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR3_B2 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR4_B2 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR5_B2 to 0x20 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR6_B2 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR8_B2 to 0x8 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR10_B2 to 0x2d +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR11_B2 to 0x2d +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR12_B2 to 0xd6 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR13_B2 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR14_B2 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR15_B2 to 0x3 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR111_B2 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR32_B2 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR33_B2 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR34_B2 to 0x11 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR35_B2 to 0x4 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR37_B2 to 0x2c +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR38_B2 to 0x2c +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR39_B2 to 0x2c +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR50_B2 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR51_B2 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR52_B2 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR0_B3 to 0x8 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR2_B3 to 0x4 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR3_B3 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR4_B3 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR5_B3 to 0x20 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR6_B3 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR8_B3 to 0x8 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR10_B3 to 0x2d +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR11_B3 to 0x2d +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR12_B3 to 0xd6 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR13_B3 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR14_B3 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR15_B3 to 0x3 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR111_B3 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR32_B3 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR33_B3 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR34_B3 to 0x11 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR35_B3 to 0x4 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR37_B3 to 0x2c +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR38_B3 to 0x2c +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR39_B3 to 0x2c +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR50_B3 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR51_B3 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR52_B3 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].WL_ADJ_START to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].WL_ADJ_END to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].RCW00_ChA_D0 to 0x1 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].RCW00_ChA_D1 to 0x1 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].RCW00_ChB_D0 to 0x1 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].RCW00_ChB_D1 to 0x1 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR0Nib0 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR0Nib1 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR0Nib2 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR0Nib3 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR0Nib4 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR0Nib5 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR0Nib6 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR0Nib7 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR0Nib8 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR0Nib9 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR0Nib10 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR0Nib11 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR0Nib12 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR0Nib13 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR0Nib14 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR0Nib15 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR0Nib16 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR0Nib17 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR0Nib18 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR0Nib19 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR1Nib0 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR1Nib1 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR1Nib2 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR1Nib3 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR1Nib4 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR1Nib5 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR1Nib6 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR1Nib7 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR1Nib8 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR1Nib9 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR1Nib10 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR1Nib11 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR1Nib12 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR1Nib13 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR1Nib14 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR1Nib15 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR1Nib16 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR1Nib17 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR1Nib18 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR1Nib19 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR2Nib0 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR2Nib1 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR2Nib2 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR2Nib3 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR2Nib4 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR2Nib5 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR2Nib6 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR2Nib7 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR2Nib8 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR2Nib9 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR2Nib10 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR2Nib11 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR2Nib12 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR2Nib13 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR2Nib14 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR2Nib15 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR2Nib16 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR2Nib17 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR2Nib18 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR2Nib19 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR3Nib0 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR3Nib1 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR3Nib2 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR3Nib3 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR3Nib4 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR3Nib5 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR3Nib6 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR3Nib7 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR3Nib8 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR3Nib9 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR3Nib10 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR3Nib11 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR3Nib12 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR3Nib13 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR3Nib14 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR3Nib15 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR3Nib16 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR3Nib17 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR3Nib18 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR3Nib19 to 0x17 +// [dwc_ddrphy_phyinit_userCustom_overrideUserInput] End of dwc_ddrphy_phyinit_userCustom_overrideUserInput() +//[dwc_ddrphy_phyinit_calcMb] Start of dwc_ddrphy_phyinit_calcMb() +//// [dwc_ddrphy_phyinit_softSetMb] mb_DDR5U_1D[0].Pstate override to 0x0 +//// [dwc_ddrphy_phyinit_softSetMb] mb_DDR5U_1D[0].DRAMFreq override to 0xc80 +//// [dwc_ddrphy_phyinit_softSetMb] mb_DDR5U_1D[0].PllBypassEn override to 0x0 +//// [dwc_ddrphy_phyinit_softSetMb] mb_DDR5U_1D[0].X16Present override to 0x0 +//// [dwc_ddrphy_phyinit_softSetMb] mb_DDR5U_1D[0].EnabledDQsChA override to 0x10 +//// [dwc_ddrphy_phyinit_softSetMb] mb_DDR5U_1D[0].EnabledDQsChB override to 0x0 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR5U_1D[1].Pstate to 0x1 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR5U_1D[1].DRAMFreq to 0x856 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR5U_1D[1].PllBypassEn to 0x0 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR5U_1D[1].X16Present to 0x1 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR5U_1D[1].EnabledDQsChA to 0x10 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR5U_1D[1].EnabledDQsChB to 0x0 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR5U_1D[2].Pstate to 0x2 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR5U_1D[2].DRAMFreq to 0x74a +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR5U_1D[2].PllBypassEn to 0x0 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR5U_1D[2].X16Present to 0x1 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR5U_1D[2].EnabledDQsChA to 0x10 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR5U_1D[2].EnabledDQsChB to 0x0 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR5U_1D[3].Pstate to 0x3 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR5U_1D[3].DRAMFreq to 0x640 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR5U_1D[3].PllBypassEn to 0x0 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR5U_1D[3].X16Present to 0x1 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR5U_1D[3].EnabledDQsChA to 0x10 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR5U_1D[3].EnabledDQsChB to 0x0 +////[dwc_ddrphy_phyinit_calcMb] TG_active[0] = 1 +////[dwc_ddrphy_phyinit_calcMb] TG_active[1] = 0 +////[dwc_ddrphy_phyinit_calcMb] TG_active[2] = 0 +////[dwc_ddrphy_phyinit_calcMb] TG_active[3] = 0 +////[dwc_ddrphy_phyinit_calcMb] tDIMM_CK [pstate=0][tg=0] = 0 ps +////[dwc_ddrphy_phyinit_calcMb] tDIMM_DQ [pstate=0][tg=0] = 0 ps +////[dwc_ddrphy_phyinit_calcMb] userInputSim.tCASL_add[pstate=0][tg=0] = 0 ps +////[dwc_ddrphy_phyinit_calcMb] tDIMM_CK [pstate=0][tg=1] = 0 ps +////[dwc_ddrphy_phyinit_calcMb] tDIMM_DQ [pstate=0][tg=1] = 0 ps +////[dwc_ddrphy_phyinit_calcMb] userInputSim.tCASL_add[pstate=0][tg=1] = 0 ps +////[dwc_ddrphy_phyinit_calcMb] tDIMM_CK [pstate=0][tg=2] = 0 ps +////[dwc_ddrphy_phyinit_calcMb] tDIMM_DQ [pstate=0][tg=2] = 0 ps +////[dwc_ddrphy_phyinit_calcMb] userInputSim.tCASL_add[pstate=0][tg=2] = 0 ps +////[dwc_ddrphy_phyinit_calcMb] tDIMM_CK [pstate=0][tg=3] = 0 ps +////[dwc_ddrphy_phyinit_calcMb] tDIMM_DQ [pstate=0][tg=3] = 0 ps +////[dwc_ddrphy_phyinit_calcMb] userInputSim.tCASL_add[pstate=0][tg=3] = 0 ps +//[dwc_ddrphy_phyinit_calcMb] End of dwc_ddrphy_phyinit_calcMb() +//// [phyinit_print_dat] // #################################################### +//// [phyinit_print_dat] // +//// [phyinit_print_dat] // Printing values in user input structure +//// [phyinit_print_dat] // +//// [phyinit_print_dat] // #################################################### +//// [phyinit_print_dat] pUserInputBasic->DramDataWidth[0] = 16 +//// [phyinit_print_dat] pUserInputBasic->DramDataWidth[1] = 16 +//// [phyinit_print_dat] pUserInputBasic->DramDataWidth[2] = 16 +//// [phyinit_print_dat] pUserInputBasic->DramDataWidth[3] = 16 +//// [phyinit_print_dat] pUserInputBasic->NumActiveDbyteDfi1 = 0 +//// [phyinit_print_dat] pUserInputBasic->DramType = 1 +//// [phyinit_print_dat] pUserInputBasic->ARdPtrInitValOvr = 0 +//// [phyinit_print_dat] pUserInputBasic->ARdPtrInitVal[0] = 3 +//// [phyinit_print_dat] pUserInputBasic->ARdPtrInitVal[1] = 3 +//// [phyinit_print_dat] pUserInputBasic->ARdPtrInitVal[2] = 3 +//// [phyinit_print_dat] pUserInputBasic->ARdPtrInitVal[3] = 3 +//// [phyinit_print_dat] pUserInputBasic->Dfi1Exists = 0 +//// [phyinit_print_dat] pUserInputBasic->Frequency[0] = 1600 +//// [phyinit_print_dat] pUserInputBasic->Frequency[1] = 1067 +//// [phyinit_print_dat] pUserInputBasic->Frequency[2] = 933 +//// [phyinit_print_dat] pUserInputBasic->Frequency[3] = 800 +//// [phyinit_print_dat] pUserInputBasic->NumActiveDbyteDfi0 = 2 +//// [phyinit_print_dat] pUserInputBasic->DisPtrInitClrTxTracking[0] = 0 +//// [phyinit_print_dat] pUserInputBasic->DisPtrInitClrTxTracking[1] = 0 +//// [phyinit_print_dat] pUserInputBasic->DisPtrInitClrTxTracking[2] = 0 +//// [phyinit_print_dat] pUserInputBasic->DisPtrInitClrTxTracking[3] = 0 +//// [phyinit_print_dat] pUserInputBasic->NumRank_dfi0 = 1 +//// [phyinit_print_dat] pUserInputBasic->NumPStates = 1 +//// [phyinit_print_dat] pUserInputBasic->PllBypass[0] = 0 +//// [phyinit_print_dat] pUserInputBasic->PllBypass[1] = 0 +//// [phyinit_print_dat] pUserInputBasic->PllBypass[2] = 0 +//// [phyinit_print_dat] pUserInputBasic->PllBypass[3] = 0 +//// [phyinit_print_dat] pUserInputBasic->DfiFreqRatio[0] = 1 +//// [phyinit_print_dat] pUserInputBasic->DfiFreqRatio[1] = 1 +//// [phyinit_print_dat] pUserInputBasic->DfiFreqRatio[2] = 1 +//// [phyinit_print_dat] pUserInputBasic->DfiFreqRatio[3] = 1 +//// [phyinit_print_dat] pUserInputBasic->NumAnib = 10 +//// [phyinit_print_dat] pUserInputBasic->DimmType = 4 +//// [phyinit_print_dat] pUserInputBasic->NumRank_dfi1 = 0 +//// [phyinit_print_dat] pUserInputBasic->NumDbyte = 2 +//// [phyinit_print_dat] pUserInputAdvanced->EnTdqs2dqTrackingTg1[0] = 1 +//// [phyinit_print_dat] pUserInputAdvanced->EnTdqs2dqTrackingTg1[1] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->EnTdqs2dqTrackingTg1[2] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->EnTdqs2dqTrackingTg1[3] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->EnTdqs2dqTrackingTg0[0] = 1 +//// [phyinit_print_dat] pUserInputAdvanced->EnTdqs2dqTrackingTg0[1] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->EnTdqs2dqTrackingTg0[2] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->EnTdqs2dqTrackingTg0[3] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->SnpsUmctlF0RC5x[0] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->SnpsUmctlF0RC5x[1] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->SnpsUmctlF0RC5x[2] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->SnpsUmctlF0RC5x[3] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->TxImpedanceCtrl2[0] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->TxImpedanceCtrl2[1] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->TxImpedanceCtrl2[2] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->TxImpedanceCtrl2[3] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->IsHighVDD = 0 +//// [phyinit_print_dat] pUserInputAdvanced->DramByteSwap[0] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->DramByteSwap[1] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->DramByteSwap[2] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->DramByteSwap[3] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->ExtCalResVal = 240 +//// [phyinit_print_dat] pUserInputAdvanced->D4TxPreambleLength[0] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->D4TxPreambleLength[1] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->D4TxPreambleLength[2] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->D4TxPreambleLength[3] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->RxEnBackOff = 1 +//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvLaneSel[0] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvLaneSel[1] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvLaneSel[2] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvLaneSel[3] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvLaneSel[4] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvLaneSel[5] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvLaneSel[6] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvLaneSel[7] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->CalOnce = 0 +//// [phyinit_print_dat] pUserInputAdvanced->Apb32BitMode = 1 +//// [phyinit_print_dat] pUserInputAdvanced->TxSlewRiseCK = 0 +//// [phyinit_print_dat] pUserInputAdvanced->TxSlewFallAC = 38 +//// [phyinit_print_dat] pUserInputAdvanced->TxSlewFallCK = 0 +//// [phyinit_print_dat] pUserInputAdvanced->DisablePmuEcc = 1 +//// [phyinit_print_dat] pUserInputAdvanced->SnpsUmctlOpt = 0 +//// [phyinit_print_dat] pUserInputAdvanced->WDQSExt = 0 +//// [phyinit_print_dat] pUserInputAdvanced->VREGCtrl_LP2_PwrSavings_En = 0 +//// [phyinit_print_dat] pUserInputAdvanced->TxSlewRiseAC = 102 +//// [phyinit_print_dat] pUserInputAdvanced->DisDynAdrTri[0] = 1 +//// [phyinit_print_dat] pUserInputAdvanced->DisDynAdrTri[1] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->DisDynAdrTri[2] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->DisDynAdrTri[3] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvEn[0] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvEn[1] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvEn[2] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvEn[3] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvEn[4] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvEn[5] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvEn[6] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvEn[7] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->EnTdqs2dqTrackingTg3[0] = 1 +//// [phyinit_print_dat] pUserInputAdvanced->EnTdqs2dqTrackingTg3[1] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->EnTdqs2dqTrackingTg3[2] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->EnTdqs2dqTrackingTg3[3] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->PhyMstrTrainInterval[0] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->PhyMstrTrainInterval[1] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->PhyMstrTrainInterval[2] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->PhyMstrTrainInterval[3] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->rtt_term_en = 0 +//// [phyinit_print_dat] pUserInputAdvanced->AlertRecoveryEnable = 0 +//// [phyinit_print_dat] pUserInputAdvanced->TxSlewRiseDQ[0] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->TxSlewRiseDQ[1] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->TxSlewRiseDQ[2] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->TxSlewRiseDQ[3] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->en_16LogicalRanks_3DS = 0 +//// [phyinit_print_dat] pUserInputAdvanced->D4RxPreambleLength[0] = 1 +//// [phyinit_print_dat] pUserInputAdvanced->D4RxPreambleLength[1] = 1 +//// [phyinit_print_dat] pUserInputAdvanced->D4RxPreambleLength[2] = 1 +//// [phyinit_print_dat] pUserInputAdvanced->D4RxPreambleLength[3] = 1 +//// [phyinit_print_dat] pUserInputAdvanced->PhyMstrCtrlMode[0] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->PhyMstrCtrlMode[1] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->PhyMstrCtrlMode[2] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->PhyMstrCtrlMode[3] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->TxSlewFallDQ[0] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->TxSlewFallDQ[1] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->TxSlewFallDQ[2] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->TxSlewFallDQ[3] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->NvAnibRcvSel[0] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->NvAnibRcvSel[1] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->NvAnibRcvSel[2] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->NvAnibRcvSel[3] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->NvAnibRcvSel[4] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->NvAnibRcvSel[5] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->NvAnibRcvSel[6] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->NvAnibRcvSel[7] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->TxImpedanceCtrl1[0] = 25 +//// [phyinit_print_dat] pUserInputAdvanced->TxImpedanceCtrl1[1] = 25 +//// [phyinit_print_dat] pUserInputAdvanced->TxImpedanceCtrl1[2] = 25 +//// [phyinit_print_dat] pUserInputAdvanced->TxImpedanceCtrl1[3] = 25 +//// [phyinit_print_dat] pUserInputAdvanced->Nibble_ECC = 15 +//// [phyinit_print_dat] pUserInputAdvanced->D5DisableRetraining = 0 +//// [phyinit_print_dat] pUserInputAdvanced->DqsOscRunTimeSel[0] = 256 +//// [phyinit_print_dat] pUserInputAdvanced->DqsOscRunTimeSel[1] = 256 +//// [phyinit_print_dat] pUserInputAdvanced->DqsOscRunTimeSel[2] = 256 +//// [phyinit_print_dat] pUserInputAdvanced->DqsOscRunTimeSel[3] = 256 +//// [phyinit_print_dat] pUserInputAdvanced->ODTImpedance[0] = 120 +//// [phyinit_print_dat] pUserInputAdvanced->ODTImpedance[1] = 60 +//// [phyinit_print_dat] pUserInputAdvanced->ODTImpedance[2] = 60 +//// [phyinit_print_dat] pUserInputAdvanced->ODTImpedance[3] = 60 +//// [phyinit_print_dat] pUserInputAdvanced->MtestPUImp = 240 +//// [phyinit_print_dat] pUserInputAdvanced->EnableMAlertAsync = 0 +//// [phyinit_print_dat] pUserInputAdvanced->PhyMstrMaxReqToAck[0] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->PhyMstrMaxReqToAck[1] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->PhyMstrMaxReqToAck[2] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->PhyMstrMaxReqToAck[3] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->RedundantCs_en = 0 +//// [phyinit_print_dat] pUserInputAdvanced->CalInterval = 9 +//// [phyinit_print_dat] pUserInputAdvanced->D5TxDqPreambleCtrl[0] = 1 +//// [phyinit_print_dat] pUserInputAdvanced->D5TxDqPreambleCtrl[1] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->D5TxDqPreambleCtrl[2] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->D5TxDqPreambleCtrl[3] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->MemAlertEn = 0 +//// [phyinit_print_dat] pUserInputAdvanced->ATxImpedance = 53247 +//// [phyinit_print_dat] pUserInputAdvanced->EnTdqs2dqTrackingTg2[0] = 1 +//// [phyinit_print_dat] pUserInputAdvanced->EnTdqs2dqTrackingTg2[1] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->EnTdqs2dqTrackingTg2[2] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->EnTdqs2dqTrackingTg2[3] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->en_3DS = 0 +//// [phyinit_print_dat] pUserInputAdvanced->EnRxDqsTracking[0] = 1 +//// [phyinit_print_dat] pUserInputAdvanced->EnRxDqsTracking[1] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->EnRxDqsTracking[2] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->EnRxDqsTracking[3] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->RstRxTrkState = 0 +//// [phyinit_print_dat] pUserInputAdvanced->TrainSequenceCtrl = 33663 +//// [phyinit_print_dat] pUserInputAdvanced->TxImpedance[0] = 60 +//// [phyinit_print_dat] pUserInputAdvanced->TxImpedance[1] = 25 +//// [phyinit_print_dat] pUserInputAdvanced->TxImpedance[2] = 25 +//// [phyinit_print_dat] pUserInputAdvanced->TxImpedance[3] = 25 +//// [phyinit_print_dat] pUserInputSim->tDQS2DQ = 750 +//// [phyinit_print_dat] pUserInputSim->tDQSCK = 0 +//// [phyinit_print_dat] pUserInputSim->tSTAOFF[0] = 0 +//// [phyinit_print_dat] pUserInputSim->tSTAOFF[1] = 0 +//// [phyinit_print_dat] pUserInputSim->tSTAOFF[2] = 0 +//// [phyinit_print_dat] pUserInputSim->tSTAOFF[3] = 0 +//// [phyinit_print_dat] // #################################################### +//// [phyinit_print_dat] // +//// [phyinit_print_dat] // Printing values of 1D message block input/inout fields, PState=0 +//// [phyinit_print_dat] // +//// [phyinit_print_dat] // #################################################### +//// [phyinit_print_dat] mb_DDR5U_1D[0].AdvTrainOpt = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MsgMisc = 0x7 +//// [phyinit_print_dat] mb_DDR5U_1D[0].Pstate = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].PllBypassEn = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DRAMFreq = 0xc80 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW05_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW06_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RXEN_ADJ = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RX2D_DFE_Misc = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].PhyVref = 0x40 +//// [phyinit_print_dat] mb_DDR5U_1D[0].D5Misc = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].WL_ADJ = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].SequenceCtrl = 0x837f +//// [phyinit_print_dat] mb_DDR5U_1D[0].HdtCtrl = 0xc8 +//// [phyinit_print_dat] mb_DDR5U_1D[0].PhyCfg = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DFIMRLMargin = 0x2 +//// [phyinit_print_dat] mb_DDR5U_1D[0].X16Present = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].UseBroadcastMR = 0x1 +//// [phyinit_print_dat] mb_DDR5U_1D[0].D5Quickboot = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDbyte = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].CATrainOpt = 0x8 +//// [phyinit_print_dat] mb_DDR5U_1D[0].TX2D_DFE_Misc = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RX2D_TrainOpt = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].TX2D_TrainOpt = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].Share2DVrefResult = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MRE_MIN_PULSE = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DWL_MIN_PULSE = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].PhyConfigOverride = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].EnabledDQsChA = 0x10 +//// [phyinit_print_dat] mb_DDR5U_1D[0].CsPresentChA = 0x1 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR0_A0 = 0x8 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR2_A0 = 0x4 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3_A0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR4_A0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR5_A0 = 0x20 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR6_A0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_A0_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR8_A0 = 0x8 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_A0_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR10_A0 = 0x2d +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_A0 = 0x2d +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_A0 = 0xd6 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_A0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR14_A0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR15_A0 = 0x3 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR111_A0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_A0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_A0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR34_A0 = 0x11 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR35_A0 = 0x4 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_A0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR37_A0 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR38_A0 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR39_A0 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_A0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_A0_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_A0_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_A0_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_A0_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_A0_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR50_A0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR51_A0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR52_A0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DFE_GainBias_A0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR0_A1 = 0x8 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR2_A1 = 0x4 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3_A1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR4_A1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR5_A1 = 0x20 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR6_A1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_A1_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR8_A1 = 0x8 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_A1_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR10_A1 = 0x2d +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_A1 = 0x2d +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_A1 = 0xd6 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_A1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR14_A1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR15_A1 = 0x3 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR111_A1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_A1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_A1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR34_A1 = 0x11 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR35_A1 = 0x4 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_A1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR37_A1 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR38_A1 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR39_A1 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_A1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_A1_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_A1_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_A1_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_A1_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_A1_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR50_A1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR51_A1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR52_A1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DFE_GainBias_A1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR0_A2 = 0x8 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR2_A2 = 0x4 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3_A2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR4_A2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR5_A2 = 0x20 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR6_A2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_A2_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR8_A2 = 0x8 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_A2_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR10_A2 = 0x2d +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_A2 = 0x2d +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_A2 = 0xd6 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_A2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR14_A2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR15_A2 = 0x3 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR111_A2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_A2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_A2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR34_A2 = 0x11 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR35_A2 = 0x4 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_A2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR37_A2 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR38_A2 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR39_A2 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_A2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_A2_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_A2_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_A2_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_A2_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_A2_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR50_A2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR51_A2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR52_A2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DFE_GainBias_A2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR0_A3 = 0x8 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR2_A3 = 0x4 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3_A3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR4_A3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR5_A3 = 0x20 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR6_A3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_A3_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR8_A3 = 0x8 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_A3_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR10_A3 = 0x2d +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_A3 = 0x2d +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_A3 = 0xd6 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_A3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR14_A3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR15_A3 = 0x3 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR111_A3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_A3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_A3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR34_A3 = 0x11 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR35_A3 = 0x4 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_A3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR37_A3 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR38_A3 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR39_A3 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_A3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_A3_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_A3_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_A3_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_A3_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_A3_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR50_A3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR51_A3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR52_A3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DFE_GainBias_A3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW04_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW05_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].WR_RD_RTT_PARK_A0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].WR_RD_RTT_PARK_A1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].WR_RD_RTT_PARK_A2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].WR_RD_RTT_PARK_A3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].EnabledDQsChB = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].CsPresentChB = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR0_B0 = 0x8 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR2_B0 = 0x4 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3_B0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR4_B0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR5_B0 = 0x20 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR6_B0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_B0_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR8_B0 = 0x8 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_B0_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR10_B0 = 0x2d +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_B0 = 0x2d +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_B0 = 0xd6 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_B0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR14_B0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR15_B0 = 0x3 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR111_B0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_B0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_B0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR34_B0 = 0x11 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR35_B0 = 0x4 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_B0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR37_B0 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR38_B0 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR39_B0 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_B0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_B0_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_B0_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_B0_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_B0_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_B0_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR50_B0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR51_B0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR52_B0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DFE_GainBias_B0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR0_B1 = 0x8 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR2_B1 = 0x4 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3_B1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR4_B1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR5_B1 = 0x20 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR6_B1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_B1_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR8_B1 = 0x8 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_B1_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR10_B1 = 0x2d +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_B1 = 0x2d +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_B1 = 0xd6 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_B1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR14_B1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR15_B1 = 0x3 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR111_B1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_B1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_B1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR34_B1 = 0x11 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR35_B1 = 0x4 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_B1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR37_B1 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR38_B1 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR39_B1 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_B1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_B1_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_B1_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_B1_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_B1_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_B1_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR50_B1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR51_B1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR52_B1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DFE_GainBias_B1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR0_B2 = 0x8 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR2_B2 = 0x4 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3_B2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR4_B2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR5_B2 = 0x20 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR6_B2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_B2_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR8_B2 = 0x8 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_B2_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR10_B2 = 0x2d +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_B2 = 0x2d +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_B2 = 0xd6 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_B2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR14_B2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR15_B2 = 0x3 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR111_B2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_B2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_B2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR34_B2 = 0x11 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR35_B2 = 0x4 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_B2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR37_B2 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR38_B2 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR39_B2 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_B2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_B2_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_B2_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_B2_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_B2_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_B2_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR50_B2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR51_B2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR52_B2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DFE_GainBias_B2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR0_B3 = 0x8 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR2_B3 = 0x4 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3_B3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR4_B3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR5_B3 = 0x20 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR6_B3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_B3_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR8_B3 = 0x8 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_B3_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR10_B3 = 0x2d +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_B3 = 0x2d +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_B3 = 0xd6 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_B3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR14_B3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR15_B3 = 0x3 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR111_B3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_B3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_B3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR34_B3 = 0x11 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR35_B3 = 0x4 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_B3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR37_B3 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR38_B3 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR39_B3 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_B3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_B3_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_B3_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_B3_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_B3_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_B3_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR50_B3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR51_B3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR52_B3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DFE_GainBias_B3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].WR_RD_RTT_PARK_B0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].WR_RD_RTT_PARK_B1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].WR_RD_RTT_PARK_B2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].WR_RD_RTT_PARK_B3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].WL_ADJ_START = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].WL_ADJ_END = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW00_ChA_D0 = 0x1 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW01_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW02_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW03_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW04_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW05_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW06_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW07_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW08_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW09_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0A_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0B_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0C_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0D_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0E_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0F_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW10_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW11_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW12_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW13_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW14_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW15_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW16_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW17_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW18_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW19_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1A_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1B_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1C_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1D_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1E_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1F_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW20_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW21_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW22_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW23_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW24_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW25_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW26_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW27_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW28_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW29_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2A_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2B_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2C_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2D_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2E_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2F_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW30_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW31_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW32_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW33_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW34_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW35_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW36_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW37_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW38_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW39_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3A_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3B_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3C_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3D_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3E_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3F_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW40_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW41_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW42_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW43_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW44_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW45_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW46_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW47_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW48_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW49_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4A_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4B_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4C_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4D_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4E_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4F_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW50_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW51_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW52_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW53_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW54_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW55_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW56_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW57_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW58_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW59_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5A_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5B_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5C_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5D_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5E_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5F_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW60_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW61_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW62_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW63_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW64_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW65_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW66_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW67_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW68_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW69_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6A_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6B_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6C_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6D_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6E_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6F_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW70_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW71_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW72_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW73_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW74_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW75_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW76_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW77_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW78_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW79_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7A_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7B_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7C_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7D_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7E_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7F_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW00_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW01_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW02_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW03_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW04_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW05_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW06_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW07_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW08_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW09_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0A_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0B_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0C_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0D_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0E_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0F_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW10_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW11_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW12_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW13_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW14_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW15_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW16_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW17_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW18_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW19_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1A_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1B_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1C_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1D_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1E_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1F_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW20_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW21_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW22_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW23_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW24_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW25_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW26_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW27_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW28_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW29_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2A_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2B_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2C_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2D_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2E_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2F_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW30_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW31_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW32_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW33_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW34_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW35_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW36_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW37_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW38_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW39_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3A_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3B_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3C_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3D_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3E_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3F_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW40_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW41_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW42_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW43_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW44_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW45_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW46_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW47_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW48_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW49_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4A_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4B_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4C_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4D_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4E_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4F_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW50_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW51_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW52_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW53_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW54_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW55_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW56_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW57_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW58_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW59_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5A_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5B_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5C_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5D_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5E_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5F_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW60_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW61_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW62_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW63_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW64_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW65_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW66_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW67_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW68_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW69_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6A_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6B_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6C_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6D_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6E_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6F_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW70_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW71_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW72_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW73_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW74_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW75_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW76_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW77_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW78_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW79_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7A_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7B_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7C_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7D_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7E_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7F_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW00_ChA_D1 = 0x1 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW01_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW02_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW03_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW04_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW05_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW06_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW07_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW08_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW09_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0A_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0B_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0C_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0D_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0E_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0F_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW10_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW11_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW12_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW13_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW14_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW15_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW16_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW17_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW18_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW19_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1A_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1B_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1C_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1D_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1E_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1F_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW20_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW21_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW22_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW23_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW24_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW25_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW26_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW27_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW28_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW29_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2A_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2B_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2C_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2D_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2E_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2F_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW30_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW31_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW32_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW33_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW34_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW35_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW36_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW37_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW38_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW39_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3A_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3B_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3C_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3D_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3E_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3F_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW40_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW41_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW42_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW43_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW44_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW45_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW46_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW47_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW48_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW49_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4A_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4B_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4C_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4D_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4E_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4F_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW50_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW51_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW52_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW53_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW54_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW55_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW56_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW57_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW58_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW59_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5A_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5B_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5C_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5D_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5E_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5F_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW60_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW61_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW62_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW63_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW64_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW65_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW66_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW67_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW68_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW69_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6A_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6B_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6C_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6D_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6E_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6F_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW70_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW71_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW72_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW73_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW74_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW75_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW76_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW77_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW78_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW79_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7A_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7B_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7C_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7D_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7E_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7F_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW00_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW01_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW02_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW03_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW04_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW05_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW06_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW07_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW08_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW09_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0A_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0B_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0C_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0D_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0E_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0F_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW10_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW11_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW12_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW13_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW14_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW15_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW16_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW17_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW18_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW19_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1A_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1B_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1C_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1D_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1E_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1F_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW20_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW21_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW22_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW23_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW24_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW25_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW26_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW27_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW28_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW29_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2A_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2B_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2C_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2D_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2E_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2F_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW30_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW31_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW32_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW33_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW34_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW35_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW36_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW37_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW38_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW39_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3A_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3B_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3C_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3D_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3E_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3F_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW40_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW41_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW42_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW43_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW44_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW45_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW46_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW47_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW48_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW49_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4A_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4B_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4C_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4D_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4E_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4F_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW50_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW51_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW52_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW53_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW54_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW55_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW56_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW57_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW58_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW59_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5A_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5B_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5C_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5D_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5E_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5F_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW60_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW61_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW62_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW63_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW64_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW65_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW66_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW67_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW68_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW69_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6A_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6B_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6C_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6D_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6E_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6F_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW70_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW71_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW72_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW73_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW74_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW75_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW76_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW77_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW78_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW79_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7A_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7B_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7C_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7D_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7E_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7F_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW00_ChB_D0 = 0x1 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW01_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW02_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW03_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW04_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW05_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW06_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW07_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW08_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW09_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0A_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0B_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0C_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0D_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0E_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0F_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW10_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW11_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW12_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW13_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW14_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW15_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW16_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW17_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW18_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW19_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1A_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1B_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1C_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1D_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1E_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1F_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW20_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW21_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW22_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW23_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW24_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW25_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW26_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW27_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW28_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW29_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2A_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2B_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2C_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2D_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2E_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2F_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW30_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW31_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW32_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW33_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW34_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW35_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW36_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW37_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW38_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW39_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3A_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3B_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3C_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3D_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3E_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3F_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW40_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW41_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW42_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW43_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW44_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW45_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW46_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW47_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW48_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW49_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4A_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4B_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4C_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4D_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4E_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4F_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW50_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW51_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW52_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW53_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW54_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW55_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW56_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW57_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW58_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW59_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5A_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5B_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5C_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5D_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5E_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5F_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW60_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW61_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW62_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW63_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW64_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW65_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW66_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW67_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW68_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW69_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6A_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6B_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6C_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6D_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6E_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6F_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW70_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW71_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW72_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW73_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW74_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW75_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW76_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW77_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW78_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW79_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7A_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7B_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7C_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7D_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7E_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7F_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW00_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW01_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW02_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW03_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW04_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW05_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW06_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW07_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW08_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW09_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0A_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0B_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0C_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0D_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0E_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0F_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW10_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW11_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW12_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW13_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW14_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW15_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW16_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW17_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW18_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW19_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1A_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1B_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1C_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1D_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1E_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1F_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW20_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW21_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW22_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW23_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW24_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW25_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW26_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW27_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW28_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW29_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2A_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2B_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2C_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2D_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2E_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2F_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW30_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW31_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW32_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW33_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW34_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW35_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW36_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW37_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW38_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW39_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3A_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3B_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3C_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3D_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3E_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3F_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW40_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW41_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW42_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW43_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW44_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW45_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW46_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW47_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW48_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW49_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4A_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4B_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4C_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4D_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4E_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4F_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW50_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW51_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW52_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW53_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW54_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW55_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW56_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW57_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW58_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW59_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5A_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5B_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5C_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5D_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5E_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5F_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW60_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW61_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW62_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW63_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW64_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW65_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW66_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW67_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW68_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW69_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6A_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6B_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6C_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6D_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6E_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6F_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW70_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW71_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW72_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW73_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW74_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW75_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW76_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW77_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW78_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW79_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7A_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7B_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7C_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7D_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7E_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7F_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW00_ChB_D1 = 0x1 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW01_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW02_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW03_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW04_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW05_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW06_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW07_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW08_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW09_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0A_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0B_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0C_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0D_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0E_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0F_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW10_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW11_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW12_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW13_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW14_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW15_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW16_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW17_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW18_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW19_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1A_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1B_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1C_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1D_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1E_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1F_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW20_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW21_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW22_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW23_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW24_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW25_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW26_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW27_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW28_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW29_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2A_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2B_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2C_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2D_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2E_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2F_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW30_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW31_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW32_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW33_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW34_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW35_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW36_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW37_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW38_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW39_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3A_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3B_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3C_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3D_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3E_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3F_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW40_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW41_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW42_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW43_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW44_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW45_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW46_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW47_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW48_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW49_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4A_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4B_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4C_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4D_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4E_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4F_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW50_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW51_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW52_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW53_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW54_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW55_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW56_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW57_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW58_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW59_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5A_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5B_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5C_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5D_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5E_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5F_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW60_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW61_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW62_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW63_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW64_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW65_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW66_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW67_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW68_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW69_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6A_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6B_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6C_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6D_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6E_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6F_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW70_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW71_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW72_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW73_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW74_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW75_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW76_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW77_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW78_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW79_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7A_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7B_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7C_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7D_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7E_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7F_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW00_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW01_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW02_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW03_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW04_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW05_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW06_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW07_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW08_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW09_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0A_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0B_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0C_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0D_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0E_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0F_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW10_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW11_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW12_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW13_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW14_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW15_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW16_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW17_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW18_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW19_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1A_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1B_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1C_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1D_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1E_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1F_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW20_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW21_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW22_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW23_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW24_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW25_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW26_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW27_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW28_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW29_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2A_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2B_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2C_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2D_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2E_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2F_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW30_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW31_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW32_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW33_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW34_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW35_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW36_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW37_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW38_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW39_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3A_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3B_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3C_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3D_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3E_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3F_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW40_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW41_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW42_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW43_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW44_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW45_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW46_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW47_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW48_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW49_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4A_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4B_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4C_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4D_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4E_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4F_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW50_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW51_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW52_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW53_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW54_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW55_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW56_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW57_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW58_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW59_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5A_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5B_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5C_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5D_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5E_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5F_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW60_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW61_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW62_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW63_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW64_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW65_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW66_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW67_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW68_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW69_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6A_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6B_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6C_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6D_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6E_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6F_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW70_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW71_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW72_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW73_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW74_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW75_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW76_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW77_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW78_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW79_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7A_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7B_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7C_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7D_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7E_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7F_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib0 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib1 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib2 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib3 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib4 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib5 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib6 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib7 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib8 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib9 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib10 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib11 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib12 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib13 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib14 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib15 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib16 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib17 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib18 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib19 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib0 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib1 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib2 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib3 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib4 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib5 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib6 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib7 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib8 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib9 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib10 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib11 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib12 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib13 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib14 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib15 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib16 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib17 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib18 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib19 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib0 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib1 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib2 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib3 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib4 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib5 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib6 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib7 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib8 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib9 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib10 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib11 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib12 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib13 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib14 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib15 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib16 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib17 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib18 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib19 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib0 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib1 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib2 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib3 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib4 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib5 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib6 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib7 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib8 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib9 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib10 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib11 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib12 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib13 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib14 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib15 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib16 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib17 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib18 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib19 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib4 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib5 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib6 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib7 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib8 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib9 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib10 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib11 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib12 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib13 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib14 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib15 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib16 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib17 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib18 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib19 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib4 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib5 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib6 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib7 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib8 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib9 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib10 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib11 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib12 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib13 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib14 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib15 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib16 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib17 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib18 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib19 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib4 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib5 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib6 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib7 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib8 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib9 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib10 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib11 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib12 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib13 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib14 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib15 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib16 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib17 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib18 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib19 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib4 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib5 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib6 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib7 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib8 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib9 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib10 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib11 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib12 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib13 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib14 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib15 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib16 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib17 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib18 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib19 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib4 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib5 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib6 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib7 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib8 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib9 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib10 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib11 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib12 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib13 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib14 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib15 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib16 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib17 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib18 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib19 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib4 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib5 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib6 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib7 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib8 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib9 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib10 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib11 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib12 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib13 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib14 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib15 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib16 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib17 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib18 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib19 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib4 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib5 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib6 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib7 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib8 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib9 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib10 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib11 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib12 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib13 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib14 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib15 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib16 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib17 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib18 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib19 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib4 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib5 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib6 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib7 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib8 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib9 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib10 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib11 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib12 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib13 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib14 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib15 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib16 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib17 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib18 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib19 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib4 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib5 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib6 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib7 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib8 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib9 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib10 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib11 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib12 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib13 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib14 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib15 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib16 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib17 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib18 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib19 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib4 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib5 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib6 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib7 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib8 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib9 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib10 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib11 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib12 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib13 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib14 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib15 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib16 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib17 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib18 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib19 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib4 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib5 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib6 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib7 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib8 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib9 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib10 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib11 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib12 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib13 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib14 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib15 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib16 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib17 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib18 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib19 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib4 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib5 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib6 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib7 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib8 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib9 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib10 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib11 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib12 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib13 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib14 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib15 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib16 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib17 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib18 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib19 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB0LaneR0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB1LaneR0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB2LaneR0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB3LaneR0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB4LaneR0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB5LaneR0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB6LaneR0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB7LaneR0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB8LaneR0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB9LaneR0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB0LaneR1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB1LaneR1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB2LaneR1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB3LaneR1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB4LaneR1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB5LaneR1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB6LaneR1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB7LaneR1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB8LaneR1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB9LaneR1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB0LaneR2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB1LaneR2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB2LaneR2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB3LaneR2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB4LaneR2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB5LaneR2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB6LaneR2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB7LaneR2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB8LaneR2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB9LaneR2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB0LaneR3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB1LaneR3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB2LaneR3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB3LaneR3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB4LaneR3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB5LaneR3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB6LaneR3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB7LaneR3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB8LaneR3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB9LaneR3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].AdvTrainOpt = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MsgMisc = 0x7 +//// [phyinit_print_dat] mb_DDR5U_1D[0].Pstate = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].PllBypassEn = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DRAMFreq = 0xc80 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW05_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW06_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RXEN_ADJ = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RX2D_DFE_Misc = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].PhyVref = 0x40 +//// [phyinit_print_dat] mb_DDR5U_1D[0].D5Misc = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].WL_ADJ = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].SequenceCtrl = 0x837f +//// [phyinit_print_dat] mb_DDR5U_1D[0].HdtCtrl = 0xc8 +//// [phyinit_print_dat] mb_DDR5U_1D[0].PhyCfg = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DFIMRLMargin = 0x2 +//// [phyinit_print_dat] mb_DDR5U_1D[0].X16Present = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].UseBroadcastMR = 0x1 +//// [phyinit_print_dat] mb_DDR5U_1D[0].D5Quickboot = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDbyte = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].CATrainOpt = 0x8 +//// [phyinit_print_dat] mb_DDR5U_1D[0].TX2D_DFE_Misc = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RX2D_TrainOpt = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].TX2D_TrainOpt = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].Share2DVrefResult = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MRE_MIN_PULSE = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DWL_MIN_PULSE = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].PhyConfigOverride = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].EnabledDQsChA = 0x10 +//// [phyinit_print_dat] mb_DDR5U_1D[0].CsPresentChA = 0x1 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR0_A0 = 0x8 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR2_A0 = 0x4 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3_A0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR4_A0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR5_A0 = 0x20 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR6_A0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_A0_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR8_A0 = 0x8 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_A0_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR10_A0 = 0x2d +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_A0 = 0x2d +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_A0 = 0xd6 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_A0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR14_A0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR15_A0 = 0x3 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR111_A0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_A0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_A0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR34_A0 = 0x11 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR35_A0 = 0x4 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_A0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR37_A0 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR38_A0 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR39_A0 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_A0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_A0_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_A0_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_A0_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_A0_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_A0_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR50_A0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR51_A0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR52_A0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DFE_GainBias_A0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR0_A1 = 0x8 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR2_A1 = 0x4 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3_A1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR4_A1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR5_A1 = 0x20 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR6_A1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_A1_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR8_A1 = 0x8 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_A1_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR10_A1 = 0x2d +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_A1 = 0x2d +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_A1 = 0xd6 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_A1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR14_A1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR15_A1 = 0x3 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR111_A1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_A1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_A1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR34_A1 = 0x11 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR35_A1 = 0x4 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_A1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR37_A1 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR38_A1 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR39_A1 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_A1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_A1_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_A1_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_A1_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_A1_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_A1_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR50_A1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR51_A1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR52_A1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DFE_GainBias_A1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR0_A2 = 0x8 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR2_A2 = 0x4 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3_A2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR4_A2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR5_A2 = 0x20 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR6_A2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_A2_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR8_A2 = 0x8 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_A2_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR10_A2 = 0x2d +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_A2 = 0x2d +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_A2 = 0xd6 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_A2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR14_A2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR15_A2 = 0x3 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR111_A2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_A2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_A2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR34_A2 = 0x11 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR35_A2 = 0x4 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_A2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR37_A2 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR38_A2 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR39_A2 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_A2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_A2_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_A2_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_A2_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_A2_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_A2_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR50_A2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR51_A2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR52_A2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DFE_GainBias_A2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR0_A3 = 0x8 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR2_A3 = 0x4 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3_A3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR4_A3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR5_A3 = 0x20 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR6_A3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_A3_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR8_A3 = 0x8 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_A3_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR10_A3 = 0x2d +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_A3 = 0x2d +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_A3 = 0xd6 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_A3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR14_A3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR15_A3 = 0x3 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR111_A3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_A3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_A3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR34_A3 = 0x11 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR35_A3 = 0x4 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_A3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR37_A3 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR38_A3 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR39_A3 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_A3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_A3_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_A3_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_A3_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_A3_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_A3_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR50_A3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR51_A3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR52_A3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DFE_GainBias_A3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW04_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW05_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].WR_RD_RTT_PARK_A0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].WR_RD_RTT_PARK_A1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].WR_RD_RTT_PARK_A2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].WR_RD_RTT_PARK_A3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].EnabledDQsChB = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].CsPresentChB = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR0_B0 = 0x8 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR2_B0 = 0x4 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3_B0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR4_B0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR5_B0 = 0x20 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR6_B0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_B0_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR8_B0 = 0x8 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_B0_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR10_B0 = 0x2d +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_B0 = 0x2d +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_B0 = 0xd6 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_B0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR14_B0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR15_B0 = 0x3 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR111_B0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_B0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_B0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR34_B0 = 0x11 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR35_B0 = 0x4 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_B0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR37_B0 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR38_B0 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR39_B0 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_B0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_B0_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_B0_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_B0_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_B0_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_B0_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR50_B0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR51_B0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR52_B0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DFE_GainBias_B0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR0_B1 = 0x8 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR2_B1 = 0x4 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3_B1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR4_B1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR5_B1 = 0x20 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR6_B1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_B1_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR8_B1 = 0x8 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_B1_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR10_B1 = 0x2d +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_B1 = 0x2d +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_B1 = 0xd6 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_B1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR14_B1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR15_B1 = 0x3 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR111_B1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_B1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_B1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR34_B1 = 0x11 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR35_B1 = 0x4 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_B1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR37_B1 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR38_B1 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR39_B1 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_B1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_B1_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_B1_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_B1_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_B1_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_B1_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR50_B1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR51_B1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR52_B1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DFE_GainBias_B1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR0_B2 = 0x8 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR2_B2 = 0x4 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3_B2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR4_B2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR5_B2 = 0x20 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR6_B2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_B2_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR8_B2 = 0x8 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_B2_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR10_B2 = 0x2d +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_B2 = 0x2d +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_B2 = 0xd6 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_B2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR14_B2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR15_B2 = 0x3 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR111_B2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_B2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_B2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR34_B2 = 0x11 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR35_B2 = 0x4 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_B2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR37_B2 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR38_B2 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR39_B2 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_B2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_B2_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_B2_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_B2_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_B2_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_B2_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR50_B2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR51_B2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR52_B2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DFE_GainBias_B2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR0_B3 = 0x8 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR2_B3 = 0x4 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3_B3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR4_B3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR5_B3 = 0x20 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR6_B3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_B3_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR8_B3 = 0x8 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_B3_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR10_B3 = 0x2d +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_B3 = 0x2d +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_B3 = 0xd6 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_B3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR14_B3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR15_B3 = 0x3 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR111_B3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_B3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_B3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR34_B3 = 0x11 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR35_B3 = 0x4 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_B3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR37_B3 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR38_B3 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR39_B3 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_B3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_B3_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_B3_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_B3_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_B3_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_B3_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR50_B3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR51_B3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR52_B3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DFE_GainBias_B3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].WR_RD_RTT_PARK_B0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].WR_RD_RTT_PARK_B1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].WR_RD_RTT_PARK_B2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].WR_RD_RTT_PARK_B3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].WL_ADJ_START = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].WL_ADJ_END = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW00_ChA_D0 = 0x1 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW01_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW02_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW03_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW04_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW05_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW06_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW07_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW08_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW09_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0A_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0B_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0C_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0D_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0E_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0F_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW10_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW11_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW12_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW13_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW14_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW15_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW16_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW17_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW18_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW19_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1A_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1B_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1C_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1D_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1E_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1F_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW20_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW21_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW22_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW23_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW24_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW25_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW26_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW27_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW28_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW29_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2A_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2B_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2C_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2D_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2E_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2F_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW30_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW31_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW32_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW33_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW34_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW35_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW36_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW37_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW38_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW39_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3A_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3B_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3C_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3D_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3E_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3F_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW40_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW41_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW42_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW43_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW44_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW45_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW46_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW47_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW48_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW49_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4A_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4B_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4C_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4D_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4E_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4F_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW50_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW51_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW52_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW53_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW54_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW55_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW56_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW57_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW58_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW59_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5A_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5B_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5C_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5D_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5E_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5F_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW60_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW61_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW62_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW63_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW64_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW65_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW66_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW67_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW68_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW69_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6A_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6B_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6C_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6D_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6E_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6F_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW70_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW71_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW72_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW73_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW74_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW75_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW76_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW77_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW78_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW79_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7A_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7B_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7C_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7D_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7E_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7F_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW00_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW01_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW02_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW03_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW04_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW05_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW06_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW07_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW08_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW09_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0A_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0B_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0C_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0D_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0E_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0F_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW10_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW11_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW12_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW13_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW14_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW15_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW16_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW17_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW18_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW19_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1A_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1B_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1C_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1D_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1E_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1F_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW20_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW21_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW22_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW23_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW24_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW25_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW26_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW27_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW28_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW29_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2A_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2B_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2C_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2D_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2E_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2F_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW30_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW31_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW32_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW33_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW34_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW35_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW36_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW37_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW38_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW39_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3A_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3B_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3C_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3D_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3E_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3F_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW40_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW41_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW42_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW43_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW44_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW45_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW46_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW47_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW48_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW49_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4A_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4B_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4C_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4D_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4E_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4F_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW50_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW51_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW52_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW53_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW54_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW55_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW56_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW57_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW58_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW59_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5A_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5B_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5C_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5D_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5E_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5F_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW60_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW61_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW62_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW63_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW64_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW65_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW66_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW67_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW68_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW69_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6A_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6B_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6C_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6D_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6E_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6F_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW70_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW71_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW72_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW73_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW74_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW75_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW76_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW77_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW78_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW79_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7A_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7B_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7C_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7D_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7E_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7F_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW00_ChA_D1 = 0x1 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW01_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW02_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW03_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW04_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW05_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW06_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW07_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW08_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW09_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0A_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0B_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0C_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0D_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0E_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0F_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW10_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW11_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW12_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW13_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW14_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW15_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW16_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW17_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW18_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW19_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1A_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1B_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1C_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1D_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1E_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1F_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW20_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW21_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW22_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW23_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW24_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW25_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW26_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW27_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW28_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW29_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2A_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2B_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2C_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2D_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2E_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2F_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW30_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW31_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW32_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW33_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW34_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW35_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW36_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW37_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW38_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW39_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3A_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3B_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3C_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3D_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3E_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3F_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW40_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW41_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW42_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW43_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW44_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW45_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW46_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW47_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW48_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW49_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4A_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4B_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4C_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4D_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4E_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4F_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW50_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW51_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW52_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW53_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW54_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW55_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW56_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW57_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW58_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW59_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5A_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5B_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5C_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5D_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5E_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5F_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW60_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW61_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW62_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW63_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW64_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW65_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW66_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW67_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW68_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW69_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6A_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6B_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6C_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6D_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6E_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6F_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW70_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW71_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW72_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW73_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW74_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW75_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW76_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW77_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW78_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW79_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7A_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7B_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7C_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7D_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7E_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7F_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW00_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW01_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW02_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW03_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW04_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW05_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW06_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW07_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW08_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW09_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0A_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0B_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0C_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0D_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0E_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0F_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW10_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW11_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW12_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW13_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW14_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW15_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW16_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW17_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW18_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW19_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1A_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1B_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1C_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1D_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1E_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1F_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW20_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW21_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW22_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW23_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW24_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW25_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW26_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW27_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW28_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW29_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2A_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2B_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2C_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2D_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2E_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2F_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW30_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW31_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW32_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW33_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW34_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW35_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW36_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW37_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW38_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW39_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3A_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3B_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3C_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3D_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3E_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3F_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW40_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW41_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW42_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW43_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW44_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW45_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW46_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW47_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW48_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW49_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4A_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4B_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4C_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4D_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4E_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4F_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW50_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW51_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW52_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW53_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW54_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW55_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW56_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW57_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW58_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW59_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5A_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5B_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5C_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5D_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5E_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5F_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW60_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW61_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW62_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW63_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW64_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW65_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW66_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW67_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW68_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW69_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6A_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6B_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6C_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6D_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6E_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6F_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW70_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW71_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW72_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW73_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW74_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW75_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW76_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW77_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW78_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW79_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7A_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7B_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7C_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7D_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7E_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7F_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW00_ChB_D0 = 0x1 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW01_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW02_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW03_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW04_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW05_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW06_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW07_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW08_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW09_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0A_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0B_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0C_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0D_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0E_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0F_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW10_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW11_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW12_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW13_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW14_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW15_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW16_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW17_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW18_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW19_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1A_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1B_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1C_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1D_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1E_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1F_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW20_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW21_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW22_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW23_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW24_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW25_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW26_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW27_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW28_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW29_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2A_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2B_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2C_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2D_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2E_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2F_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW30_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW31_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW32_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW33_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW34_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW35_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW36_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW37_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW38_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW39_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3A_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3B_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3C_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3D_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3E_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3F_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW40_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW41_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW42_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW43_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW44_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW45_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW46_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW47_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW48_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW49_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4A_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4B_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4C_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4D_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4E_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4F_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW50_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW51_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW52_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW53_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW54_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW55_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW56_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW57_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW58_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW59_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5A_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5B_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5C_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5D_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5E_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5F_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW60_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW61_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW62_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW63_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW64_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW65_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW66_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW67_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW68_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW69_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6A_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6B_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6C_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6D_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6E_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6F_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW70_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW71_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW72_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW73_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW74_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW75_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW76_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW77_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW78_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW79_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7A_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7B_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7C_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7D_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7E_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7F_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW00_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW01_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW02_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW03_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW04_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW05_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW06_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW07_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW08_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW09_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0A_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0B_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0C_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0D_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0E_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0F_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW10_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW11_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW12_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW13_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW14_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW15_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW16_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW17_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW18_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW19_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1A_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1B_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1C_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1D_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1E_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1F_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW20_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW21_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW22_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW23_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW24_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW25_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW26_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW27_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW28_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW29_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2A_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2B_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2C_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2D_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2E_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2F_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW30_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW31_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW32_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW33_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW34_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW35_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW36_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW37_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW38_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW39_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3A_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3B_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3C_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3D_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3E_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3F_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW40_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW41_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW42_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW43_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW44_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW45_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW46_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW47_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW48_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW49_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4A_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4B_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4C_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4D_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4E_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4F_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW50_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW51_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW52_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW53_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW54_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW55_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW56_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW57_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW58_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW59_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5A_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5B_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5C_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5D_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5E_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5F_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW60_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW61_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW62_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW63_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW64_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW65_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW66_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW67_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW68_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW69_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6A_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6B_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6C_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6D_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6E_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6F_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW70_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW71_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW72_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW73_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW74_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW75_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW76_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW77_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW78_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW79_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7A_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7B_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7C_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7D_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7E_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7F_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW00_ChB_D1 = 0x1 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW01_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW02_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW03_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW04_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW05_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW06_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW07_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW08_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW09_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0A_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0B_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0C_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0D_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0E_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0F_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW10_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW11_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW12_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW13_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW14_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW15_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW16_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW17_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW18_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW19_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1A_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1B_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1C_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1D_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1E_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1F_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW20_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW21_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW22_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW23_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW24_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW25_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW26_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW27_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW28_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW29_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2A_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2B_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2C_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2D_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2E_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2F_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW30_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW31_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW32_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW33_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW34_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW35_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW36_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW37_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW38_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW39_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3A_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3B_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3C_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3D_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3E_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3F_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW40_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW41_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW42_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW43_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW44_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW45_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW46_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW47_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW48_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW49_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4A_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4B_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4C_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4D_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4E_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4F_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW50_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW51_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW52_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW53_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW54_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW55_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW56_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW57_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW58_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW59_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5A_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5B_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5C_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5D_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5E_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5F_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW60_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW61_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW62_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW63_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW64_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW65_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW66_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW67_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW68_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW69_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6A_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6B_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6C_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6D_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6E_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6F_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW70_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW71_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW72_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW73_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW74_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW75_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW76_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW77_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW78_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW79_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7A_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7B_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7C_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7D_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7E_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7F_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW00_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW01_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW02_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW03_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW04_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW05_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW06_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW07_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW08_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW09_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0A_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0B_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0C_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0D_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0E_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0F_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW10_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW11_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW12_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW13_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW14_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW15_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW16_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW17_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW18_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW19_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1A_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1B_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1C_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1D_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1E_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1F_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW20_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW21_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW22_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW23_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW24_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW25_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW26_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW27_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW28_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW29_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2A_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2B_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2C_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2D_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2E_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2F_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW30_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW31_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW32_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW33_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW34_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW35_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW36_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW37_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW38_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW39_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3A_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3B_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3C_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3D_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3E_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3F_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW40_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW41_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW42_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW43_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW44_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW45_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW46_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW47_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW48_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW49_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4A_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4B_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4C_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4D_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4E_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4F_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW50_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW51_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW52_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW53_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW54_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW55_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW56_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW57_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW58_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW59_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5A_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5B_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5C_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5D_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5E_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5F_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW60_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW61_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW62_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW63_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW64_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW65_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW66_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW67_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW68_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW69_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6A_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6B_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6C_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6D_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6E_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6F_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW70_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW71_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW72_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW73_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW74_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW75_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW76_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW77_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW78_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW79_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7A_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7B_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7C_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7D_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7E_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7F_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib0 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib1 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib2 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib3 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib4 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib5 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib6 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib7 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib8 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib9 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib10 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib11 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib12 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib13 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib14 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib15 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib16 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib17 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib18 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib19 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib0 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib1 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib2 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib3 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib4 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib5 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib6 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib7 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib8 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib9 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib10 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib11 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib12 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib13 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib14 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib15 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib16 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib17 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib18 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib19 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib0 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib1 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib2 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib3 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib4 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib5 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib6 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib7 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib8 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib9 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib10 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib11 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib12 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib13 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib14 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib15 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib16 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib17 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib18 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib19 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib0 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib1 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib2 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib3 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib4 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib5 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib6 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib7 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib8 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib9 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib10 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib11 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib12 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib13 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib14 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib15 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib16 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib17 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib18 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib19 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib4 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib5 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib6 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib7 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib8 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib9 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib10 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib11 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib12 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib13 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib14 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib15 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib16 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib17 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib18 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib19 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib4 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib5 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib6 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib7 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib8 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib9 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib10 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib11 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib12 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib13 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib14 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib15 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib16 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib17 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib18 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib19 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib4 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib5 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib6 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib7 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib8 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib9 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib10 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib11 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib12 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib13 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib14 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib15 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib16 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib17 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib18 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib19 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib4 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib5 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib6 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib7 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib8 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib9 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib10 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib11 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib12 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib13 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib14 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib15 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib16 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib17 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib18 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib19 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib4 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib5 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib6 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib7 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib8 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib9 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib10 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib11 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib12 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib13 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib14 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib15 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib16 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib17 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib18 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib19 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib4 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib5 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib6 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib7 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib8 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib9 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib10 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib11 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib12 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib13 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib14 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib15 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib16 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib17 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib18 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib19 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib4 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib5 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib6 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib7 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib8 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib9 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib10 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib11 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib12 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib13 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib14 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib15 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib16 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib17 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib18 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib19 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib4 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib5 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib6 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib7 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib8 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib9 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib10 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib11 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib12 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib13 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib14 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib15 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib16 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib17 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib18 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib19 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib4 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib5 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib6 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib7 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib8 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib9 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib10 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib11 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib12 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib13 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib14 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib15 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib16 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib17 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib18 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib19 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib4 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib5 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib6 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib7 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib8 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib9 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib10 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib11 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib12 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib13 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib14 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib15 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib16 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib17 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib18 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib19 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib4 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib5 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib6 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib7 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib8 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib9 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib10 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib11 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib12 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib13 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib14 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib15 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib16 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib17 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib18 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib19 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib4 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib5 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib6 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib7 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib8 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib9 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib10 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib11 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib12 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib13 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib14 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib15 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib16 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib17 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib18 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib19 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB0LaneR0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB1LaneR0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB2LaneR0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB3LaneR0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB4LaneR0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB5LaneR0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB6LaneR0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB7LaneR0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB8LaneR0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB9LaneR0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB0LaneR1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB1LaneR1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB2LaneR1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB3LaneR1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB4LaneR1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB5LaneR1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB6LaneR1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB7LaneR1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB8LaneR1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB9LaneR1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB0LaneR2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB1LaneR2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB2LaneR2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB3LaneR2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB4LaneR2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB5LaneR2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB6LaneR2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB7LaneR2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB8LaneR2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB9LaneR2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB0LaneR3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB1LaneR3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB2LaneR3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB3LaneR3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB4LaneR3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB5LaneR3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB6LaneR3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB7LaneR3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB8LaneR3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB9LaneR3 = 0x0 + +////############################################################## +//// +//// Step (A) : Bring up VDD, VDDQ, and VAA +//// +//// The power supplies can come up and stabilize in any order. +//// While the power supplies are coming up, all outputs will be unknown and +//// the values of the inputs are don't cares. +//// +////############################################################## + +dwc_ddrphy_phyinit_userCustom_A_bringupPower(); + +//[dwc_ddrphy_phyinit_userCustom_A_bringupPower] End of dwc_ddrphy_phyinit_userCustom_A_bringupPower() +// +// +////############################################################## +//// +//// 4.3.2(B) Start Clocks and Reset the PHY +//// +//// Following is one possbile sequence to reset the PHY. Other sequences are also possible. +//// See section 5.2.2 of the PUB for other possible reset sequences. +//// +//// 1. Drive PwrOkIn to 0. Note: Reset, DfiClk, and APBCLK can be X. +//// 2. Start DfiClk and APBCLK +//// 3. Drive Reset to 1 and PRESETn_APB to 0. +//// Note: The combination of PwrOkIn=0 and Reset=1 signals a cold reset to the PHY. +//// 4. Wait a minimum of 8 cycles. +//// 5. Drive PwrOkIn to 1. Once the PwrOkIn is asserted (and Reset is still asserted), +//// DfiClk synchronously switches to any legal input frequency. +//// 6. Wait a minimum of 64 cycles. Note: This is the reset period for the PHY. +//// 7. Drive Reset to 0. Note: All DFI and APB inputs must be driven at valid reset states before the deassertion of Reset. +//// 8. Wait a minimum of 1 Cycle. +//// 9. Drive PRESETn_APB to 1 to de-assert reset on the ABP bus. +////10. The PHY is now in the reset state and is ready to accept APB transactions. +//// +////############################################################## +// +// +dwc_ddrphy_phyinit_userCustom_B_startClockResetPhy(sdrammc); + +//// [dwc_ddrphy_phyinit_userCustom_B_startClockResetPhy] End of dwc_ddrphy_phyinit_userCustom_B_startClockResetPhy() +// + +////############################################################## +//// +//// Step (C) Initialize PHY Configuration +//// +//// Load the required PHY configuration registers for the appropriate mode and memory configuration +//// +////############################################################## +// + +//// [phyinit_C_initPhyConfig] Start of dwc_ddrphy_phyinit_C_initPhyConfig() +//// [phyinit_C_initPhyConfig] Programming ForceClkGaterEnables::ForcePubDxClkEnLow to 0x1 +dwc_ddrphy_apb_wr(0x200a6, 0x2); // DWC_DDRPHYA_MASTER0_base0_ForceClkGaterEnables +// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming VREGCtrl3::VshCtrlUpdate to 0x0 for MASTER +dwc_ddrphy_apb_wr(0x20066, 0x0); // DWC_DDRPHYA_MASTER0_base0_VREGCtrl3 +// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming VREGCtrl3::VshCtrlUpdate to 0x0 for all DBYTEs +dwc_ddrphy_apb_wr(0x10066, 0x0); // DWC_DDRPHYA_DBYTE0_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x11066, 0x0); // DWC_DDRPHYA_DBYTE1_base0_VREGCtrl3 +// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming VREGCtrl3::VshCtrlUpdate to 0x0 for all ANIBs +dwc_ddrphy_apb_wr(0x66, 0x0); // DWC_DDRPHYA_ANIB0_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x1066, 0x0); // DWC_DDRPHYA_ANIB1_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x2066, 0x0); // DWC_DDRPHYA_ANIB2_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x3066, 0x0); // DWC_DDRPHYA_ANIB3_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x4066, 0x0); // DWC_DDRPHYA_ANIB4_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x5066, 0x0); // DWC_DDRPHYA_ANIB5_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x6066, 0x0); // DWC_DDRPHYA_ANIB6_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x7066, 0x0); // DWC_DDRPHYA_ANIB7_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x8066, 0x0); // DWC_DDRPHYA_ANIB8_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x9066, 0x0); // DWC_DDRPHYA_ANIB9_base0_VREGCtrl3 +// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming VREGCtrl1::VshDAC to 0x16 for MASTER +dwc_ddrphy_apb_wr(0x20029, 0x58); // DWC_DDRPHYA_MASTER0_base0_VREGCtrl1_p0 +// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming VREGCtrl1::VshDAC to 0x16 for all DBYTEs +dwc_ddrphy_apb_wr(0x10029, 0x58); // DWC_DDRPHYA_DBYTE0_base0_VREGCtrl1_p0 +dwc_ddrphy_apb_wr(0x11029, 0x58); // DWC_DDRPHYA_DBYTE1_base0_VREGCtrl1_p0 +// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming VREGCtrl1::VshDAC to 0x16 for all ANIBs +dwc_ddrphy_apb_wr(0x29, 0x58); // DWC_DDRPHYA_ANIB0_base0_VREGCtrl1_p0 +dwc_ddrphy_apb_wr(0x1029, 0x58); // DWC_DDRPHYA_ANIB1_base0_VREGCtrl1_p0 +dwc_ddrphy_apb_wr(0x2029, 0x58); // DWC_DDRPHYA_ANIB2_base0_VREGCtrl1_p0 +dwc_ddrphy_apb_wr(0x3029, 0x58); // DWC_DDRPHYA_ANIB3_base0_VREGCtrl1_p0 +dwc_ddrphy_apb_wr(0x4029, 0x58); // DWC_DDRPHYA_ANIB4_base0_VREGCtrl1_p0 +dwc_ddrphy_apb_wr(0x5029, 0x58); // DWC_DDRPHYA_ANIB5_base0_VREGCtrl1_p0 +dwc_ddrphy_apb_wr(0x6029, 0x58); // DWC_DDRPHYA_ANIB6_base0_VREGCtrl1_p0 +dwc_ddrphy_apb_wr(0x7029, 0x58); // DWC_DDRPHYA_ANIB7_base0_VREGCtrl1_p0 +dwc_ddrphy_apb_wr(0x8029, 0x58); // DWC_DDRPHYA_ANIB8_base0_VREGCtrl1_p0 +dwc_ddrphy_apb_wr(0x9029, 0x58); // DWC_DDRPHYA_ANIB9_base0_VREGCtrl1_p0 +dwc_ddrphy_apb_wr(0x90301, 0x59); // DWC_DDRPHYA_INITENG0_base0_Seq0BGPR1_p0 +dwc_ddrphy_apb_wr(0x90302, 0x58); // DWC_DDRPHYA_INITENG0_base0_Seq0BGPR2_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TxSlewRate::CsrTxSrc to 0x0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TxSlewRate::TxPreDrvMode to 0x0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TxSlewRate to 0x0 +//// [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for TxSlewRate::CsrTxSrc are technology specific. +//// [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings + +dwc_ddrphy_apb_wr(0x1005f, 0x0); // DWC_DDRPHYA_DBYTE0_base0_TxSlewRate_b0_p0 +dwc_ddrphy_apb_wr(0x1015f, 0x0); // DWC_DDRPHYA_DBYTE0_base0_TxSlewRate_b1_p0 +dwc_ddrphy_apb_wr(0x1105f, 0x0); // DWC_DDRPHYA_DBYTE1_base0_TxSlewRate_b0_p0 +dwc_ddrphy_apb_wr(0x1115f, 0x0); // DWC_DDRPHYA_DBYTE1_base0_TxSlewRate_b1_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate::ATxPreDrvMode to 0x0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate::CsrATxSrc ANIB 0 to 0x1be +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate ANIB 0 to 0x1be +dwc_ddrphy_apb_wr(0x55, 0x1be); // DWC_DDRPHYA_ANIB0_base0_ATxSlewRate_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate::CsrATxSrc ANIB 1 to 0x1be +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate ANIB 1 to 0x1be +dwc_ddrphy_apb_wr(0x1055, 0x1be); // DWC_DDRPHYA_ANIB1_base0_ATxSlewRate_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate::CsrATxSrc ANIB 2 to 0x1be +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate ANIB 2 to 0x1be +dwc_ddrphy_apb_wr(0x2055, 0x1be); // DWC_DDRPHYA_ANIB2_base0_ATxSlewRate_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate::CsrATxSrc ANIB 3 to 0x1be +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate ANIB 3 to 0x1be +dwc_ddrphy_apb_wr(0x3055, 0x1be); // DWC_DDRPHYA_ANIB3_base0_ATxSlewRate_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate::CsrATxSrc ANIB 4 to 0x1be +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate ANIB 4 to 0x1be +dwc_ddrphy_apb_wr(0x4055, 0x1be); // DWC_DDRPHYA_ANIB4_base0_ATxSlewRate_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate::CsrATxSrc ANIB 5 to 0x0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate ANIB 5 to 0x0 +dwc_ddrphy_apb_wr(0x5055, 0x0); // DWC_DDRPHYA_ANIB5_base0_ATxSlewRate_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate::CsrATxSrc ANIB 6 to 0x1be +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate ANIB 6 to 0x1be +dwc_ddrphy_apb_wr(0x6055, 0x1be); // DWC_DDRPHYA_ANIB6_base0_ATxSlewRate_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate::CsrATxSrc ANIB 7 to 0x1be +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate ANIB 7 to 0x1be +dwc_ddrphy_apb_wr(0x7055, 0x1be); // DWC_DDRPHYA_ANIB7_base0_ATxSlewRate_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate::CsrATxSrc ANIB 8 to 0x1be +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate ANIB 8 to 0x1be +dwc_ddrphy_apb_wr(0x8055, 0x1be); // DWC_DDRPHYA_ANIB8_base0_ATxSlewRate_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate::CsrATxSrc ANIB 9 to 0x1be +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate ANIB 9 to 0x1be +dwc_ddrphy_apb_wr(0x9055, 0x1be); // DWC_DDRPHYA_ANIB9_base0_ATxSlewRate_p0 +//// [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for ATxSlewRate::CsrATxSrc are technology specific. +//// [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings + +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming CalPreDriverOverride::CsrTxOvSrc to 0x0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming CalPreDriverOverride::TxCalBaseN to 0x1 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming CalPreDriverOverride::TxCalBaseP to 0x1 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming CalPreDriverOverride to 0x300 +//// [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for CalPreDriverOverride::CsrTxOvSrc are technology specific. +//// [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings + +dwc_ddrphy_apb_wr(0x2008c, 0x300); // DWC_DDRPHYA_MASTER0_base0_CalPreDriverOverride +//// [phyinit_C_initPhyConfig] PUB revision is 0x0350. +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming PllCtrl2::PllFreqSel to 0x19 based on DfiClk frequency = 800. +dwc_ddrphy_apb_wr(0x200c5, 0x19); // DWC_DDRPHYA_MASTER0_base0_PllCtrl2_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming PllCtrl1::PllCpPropCtrl to 0x3 based on DfiClk frequency = 800. +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming PllCtrl1::PllCpIntCtrl to 0x1 based on DfiClk frequency = 800. +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming PllCtrl1 to 0x61 based on DfiClk frequency = 800. +dwc_ddrphy_apb_wr(0x200c7, 0x21); // DWC_DDRPHYA_MASTER0_base0_PllCtrl1_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming PllTestMode to 0x400f based on DfiClk frequency = 800. +dwc_ddrphy_apb_wr(0x200ca, 0x402f); // DWC_DDRPHYA_MASTER0_base0_PllTestMode_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming PllCtrl4::PllCpPropGsCtrl to 0x6 based on DfiClk frequency = 800. +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming PllCtrl4::PllCpIntGsCtrl to 0x12 based on DfiClk frequency = 800. +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming PllCtrl4 to 0xd2 based on DfiClk frequency = 800. +dwc_ddrphy_apb_wr(0x200cc, 0x17f); // DWC_DDRPHYA_MASTER0_base0_PllCtrl4_p0 +//// [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for PllCtrl1 and PllTestMode are technology specific. +//// [phyinit_C_initPhyConfig] ### NOTE ### Please consult technology specific PHY Databook for recommended settings + +// +////############################################################## +//// +//// Program ARdPtrInitVal based on Frequency and PLL Bypass inputs +//// The values programmed here assume ideal properties of DfiClk +//// and Pclk including: +//// - DfiClk skew +//// - DfiClk jitter +//// - DfiClk PVT variations +//// - Pclk skew +//// - Pclk jitter +//// +//// PLL Bypassed mode: +//// For MemClk frequency > 933MHz, the valid range of ARdPtrInitVal_p0[3:0] is: 2-5 +//// For MemClk frequency < 933MHz, the valid range of ARdPtrInitVal_p0[3:0] is: 1-5 +//// +//// PLL Enabled mode: +//// For MemClk frequency > 933MHz, the valid range of ARdPtrInitVal_p0[3:0] is: 1-5 +//// For MemClk frequency < 933MHz, the valid range of ARdPtrInitVal_p0[3:0] is: 0-5 +//// +////############################################################## +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ARdPtrInitVal to 0x1 +dwc_ddrphy_apb_wr(0x2002e, 0x1); // DWC_DDRPHYA_MASTER0_base0_ARdPtrInitVal_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DisPtrInitClrTxTracking to 0x0 +dwc_ddrphy_apb_wr(0x20051, 0x0); // DWC_DDRPHYA_MASTER0_base0_PtrInitTrackingModeCntrl_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DqsPreambleControl::TwoTckRxDqsPre to 0x0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DqsPreambleControl::TwoTckTxDqsPre to 0x0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DqsPreambleControl::PositionDfeInit to 0x2 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DqsPreambleControl::DDR5RxPreamble to 0x0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DqsPreambleControl::DDR5RxPostamble to 0x0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DqsPreambleControl to 0x88 +dwc_ddrphy_apb_wr(0x20024, 0x88); // DWC_DDRPHYA_MASTER0_base0_DqsPreambleControl_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DqsPreamblePattern::EnTxDqsPreamblePattern to 0x7 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DqsPreamblePattern::TxDqsPreamblePattern to 0x1 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DqsPreamblePattern to 0x701 +dwc_ddrphy_apb_wr(0x200a1, 0x701); // DWC_DDRPHYA_MASTER0_base0_DqsPreamblePattern_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DqsPostamblePattern::EnTxDqsPostamblePattern to 0x0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DqsPostamblePattern::TxDqsPostamblePattern to 0x0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DqsPostamblePattern to 0x0 +dwc_ddrphy_apb_wr(0x200a2, 0x0); // DWC_DDRPHYA_MASTER0_base0_DqsPostamblePattern_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DmPreamblePattern::EnTxDmPreamblePattern to 0xf +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DmPreamblePattern::TxDmPreamblePattern to 0xf +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DmPreamblePattern to 0xf5 +dwc_ddrphy_apb_wr(0x200fe, 0xf5); // DWC_DDRPHYA_MASTER0_base0_DmPreamblePattern_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DqPreamblePatternU0::EnTxDqPreamblePatternU0 to 0xf +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DqPreamblePatternU0::TxDqPreamblePatternU0 to 0xf +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DqPreamblePatternU0 to 0xf5 +dwc_ddrphy_apb_wr(0x200fc, 0xf5); // DWC_DDRPHYA_MASTER0_base0_DqPreamblePatternU0_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DqPreamblePatternU1::EnTxDqPreamblePatternU1 to 0xf +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DqPreamblePatternU1::TxDqPreamblePatternU1 to 0xf +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DqPreamblePatternU1 to 0xf5 +dwc_ddrphy_apb_wr(0x200fd, 0xf5); // DWC_DDRPHYA_MASTER0_base0_DqPreamblePatternU1_p0 +//// [phyinit_C_initPhyConfig] Programming DbyteDllModeCntrl::DllRxPreambleMode to 0x1 +//// [phyinit_C_initPhyConfig] Programming DbyteDllModeCntrl::DllRxBurstLengthMode to 0x0 +//// [phyinit_C_initPhyConfig] Programming DbyteDllModeCntrl to 0x2 +dwc_ddrphy_apb_wr(0x2003a, 0x2); // DWC_DDRPHYA_MASTER0_base0_DbyteDllModeCntrl +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TxOdtDrvStren::TxOdtStrenPu to 0x4 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TxOdtDrvStren::TxOdtStrenPd to 0x0 +dwc_ddrphy_apb_wr(0x1004d, 0x104); // DWC_DDRPHYA_DBYTE0_base0_TxOdtDrvStren_b0_p0 +dwc_ddrphy_apb_wr(0x1014d, 0x104); // DWC_DDRPHYA_DBYTE0_base0_TxOdtDrvStren_b1_p0 +dwc_ddrphy_apb_wr(0x1104d, 0x104); // DWC_DDRPHYA_DBYTE1_base0_TxOdtDrvStren_b0_p0 +dwc_ddrphy_apb_wr(0x1114d, 0x104); // DWC_DDRPHYA_DBYTE1_base0_TxOdtDrvStren_b1_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxImpedance::ADrvStrenP to 0x3f +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxImpedance::ADrvStrenN to 0x3f +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxImpedance::ATxReserved13x12 to 0x0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxImpedance::ATxCalBaseN to 0x1 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxImpedance::ATxCalBaseP to 0x1 +dwc_ddrphy_apb_wr(0x43, 0xcfff); // DWC_DDRPHYA_ANIB0_base0_ATxImpedance +dwc_ddrphy_apb_wr(0x1043, 0xcfff); // DWC_DDRPHYA_ANIB1_base0_ATxImpedance +dwc_ddrphy_apb_wr(0x2043, 0xcfff); // DWC_DDRPHYA_ANIB2_base0_ATxImpedance +dwc_ddrphy_apb_wr(0x3043, 0xcfff); // DWC_DDRPHYA_ANIB3_base0_ATxImpedance +dwc_ddrphy_apb_wr(0x4043, 0xcfff); // DWC_DDRPHYA_ANIB4_base0_ATxImpedance +dwc_ddrphy_apb_wr(0x5043, 0xcfff); // DWC_DDRPHYA_ANIB5_base0_ATxImpedance +dwc_ddrphy_apb_wr(0x6043, 0xcfff); // DWC_DDRPHYA_ANIB6_base0_ATxImpedance +dwc_ddrphy_apb_wr(0x7043, 0xcfff); // DWC_DDRPHYA_ANIB7_base0_ATxImpedance +dwc_ddrphy_apb_wr(0x8043, 0xcfff); // DWC_DDRPHYA_ANIB8_base0_ATxImpedance +dwc_ddrphy_apb_wr(0x9043, 0xcfff); // DWC_DDRPHYA_ANIB9_base0_ATxImpedance +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TxImpedanceCtrl0::TxStrenEqHiPu to 0xc +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TxImpedanceCtrl0::TxStrenEqLoPd to 0xc +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TxImpedanceCtrl1::TxStrenPu to 0x3f +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TxImpedanceCtrl1::TxStrenPd to 0x3f +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TxImpedanceCtrl2::TxStrenEqLoPu to 0x0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TxImpedanceCtrl2::TxStrenEqHiPd to 0x0 +dwc_ddrphy_apb_wr(0x10041, 0x30c); // DWC_DDRPHYA_DBYTE0_base0_TxImpedanceCtrl0_b0_p0 +dwc_ddrphy_apb_wr(0x10049, 0x79e); // DWC_DDRPHYA_DBYTE0_base0_TxImpedanceCtrl1_b0_p0 +dwc_ddrphy_apb_wr(0x1004b, 0x0); // DWC_DDRPHYA_DBYTE0_base0_TxImpedanceCtrl2_b0_p0 +dwc_ddrphy_apb_wr(0x10141, 0x30c); // DWC_DDRPHYA_DBYTE0_base0_TxImpedanceCtrl0_b1_p0 +dwc_ddrphy_apb_wr(0x10149, 0x79e); // DWC_DDRPHYA_DBYTE0_base0_TxImpedanceCtrl1_b1_p0 +dwc_ddrphy_apb_wr(0x1014b, 0x0); // DWC_DDRPHYA_DBYTE0_base0_TxImpedanceCtrl2_b1_p0 +dwc_ddrphy_apb_wr(0x11041, 0x30c); // DWC_DDRPHYA_DBYTE1_base0_TxImpedanceCtrl0_b0_p0 +dwc_ddrphy_apb_wr(0x11049, 0x79e); // DWC_DDRPHYA_DBYTE1_base0_TxImpedanceCtrl1_b0_p0 +dwc_ddrphy_apb_wr(0x1104b, 0x0); // DWC_DDRPHYA_DBYTE1_base0_TxImpedanceCtrl2_b0_p0 +dwc_ddrphy_apb_wr(0x11141, 0x30c); // DWC_DDRPHYA_DBYTE1_base0_TxImpedanceCtrl0_b1_p0 +dwc_ddrphy_apb_wr(0x11149, 0x79e); // DWC_DDRPHYA_DBYTE1_base0_TxImpedanceCtrl1_b1_p0 +dwc_ddrphy_apb_wr(0x1114b, 0x0); // DWC_DDRPHYA_DBYTE1_base0_TxImpedanceCtrl2_b1_p0 +//// [phyinit_C_initPhyConfig] Programming DfiMode to 0x1 +dwc_ddrphy_apb_wr(0x20018, 0x1); // DWC_DDRPHYA_MASTER0_base0_DfiMode +//// [phyinit_C_initPhyConfig] Programming DfiCAMode to 0x10 +dwc_ddrphy_apb_wr(0x20075, 0x10); // DWC_DDRPHYA_MASTER0_base0_DfiCAMode +//// [phyinit_C_initPhyConfig] Programming CalDrvStr0::CalDrvStrPd50 to 0x2 +//// [phyinit_C_initPhyConfig] Programming CalDrvStr0::CalDrvStrPu50 to 0x2 +dwc_ddrphy_apb_wr(0x20050, 0x82); // DWC_DDRPHYA_MASTER0_base0_CalDrvStr0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming CalUclkInfo::CalUClkTicksPer1uS to 0x320 +dwc_ddrphy_apb_wr(0x20008, 0x320); // DWC_DDRPHYA_MASTER0_base0_CalUclkInfo_p0 +//// [phyinit_C_initPhyConfig] Programming CalRate::CalInterval to 0x9 +//// [phyinit_C_initPhyConfig] Programming CalRate::CalOnce to 0x0 +dwc_ddrphy_apb_wr(0x20088, 0x9); // DWC_DDRPHYA_MASTER0_base0_CalRate +//// [phyinit_C_initPhyConfig] Pstate=0, Programming VrefInGlobal::GlobalVrefInSel to 0x0 +//// [phyinit_C_initPhyConfig] Pstate=0, Programming VrefInGlobal::GlobalVrefInDAC to 0x1f +//// [phyinit_C_initPhyConfig] Pstate=0, Programming VrefInGlobal to 0xf8 +dwc_ddrphy_apb_wr(0x200b2, 0xf8); // DWC_DDRPHYA_MASTER0_base0_VrefInGlobal_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Programming DqDqsRcvCntrl (Byte=0, Upper/Lower=0) to 0x2900 +dwc_ddrphy_apb_wr(0x10043, 0x2900); // DWC_DDRPHYA_DBYTE0_base0_DqDqsRcvCntrl_b0_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Programming DqDqsRcvCntrl (Byte=0, Upper/Lower=1) to 0x2900 +dwc_ddrphy_apb_wr(0x10143, 0x2900); // DWC_DDRPHYA_DBYTE0_base0_DqDqsRcvCntrl_b1_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Programming DqDqsRcvCntrl (Byte=1, Upper/Lower=0) to 0x2900 +dwc_ddrphy_apb_wr(0x11043, 0x2900); // DWC_DDRPHYA_DBYTE1_base0_DqDqsRcvCntrl_b0_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Programming DqDqsRcvCntrl (Byte=1, Upper/Lower=1) to 0x2900 +dwc_ddrphy_apb_wr(0x11143, 0x2900); // DWC_DDRPHYA_DBYTE1_base0_DqDqsRcvCntrl_b1_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Programming DqDqsRcvCntrl2 to 0x1c +dwc_ddrphy_apb_wr(0x1004c, 0x1c); // DWC_DDRPHYA_DBYTE0_base0_DqDqsRcvCntrl2_p0 +dwc_ddrphy_apb_wr(0x1104c, 0x1c); // DWC_DDRPHYA_DBYTE1_base0_DqDqsRcvCntrl2_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TristateModeCA::DisDynAdrTri_p0 to 0x1 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TristateModeCA::DDR2TMode_p0 to 0x0 +dwc_ddrphy_apb_wr(0x20019, 0x5); // DWC_DDRPHYA_MASTER0_base0_TristateModeCA_p0 +//// [phyinit_C_initPhyConfig] Programming DfiFreqXlat* +dwc_ddrphy_apb_wr(0x200f0, 0x0); // DWC_DDRPHYA_MASTER0_base0_DfiFreqXlat0 +dwc_ddrphy_apb_wr(0x200f1, 0x0); // DWC_DDRPHYA_MASTER0_base0_DfiFreqXlat1 +dwc_ddrphy_apb_wr(0x200f2, 0x4444); // DWC_DDRPHYA_MASTER0_base0_DfiFreqXlat2 +dwc_ddrphy_apb_wr(0x200f3, 0x8888); // DWC_DDRPHYA_MASTER0_base0_DfiFreqXlat3 +dwc_ddrphy_apb_wr(0x200f4, 0x5555); // DWC_DDRPHYA_MASTER0_base0_DfiFreqXlat4 +dwc_ddrphy_apb_wr(0x200f5, 0x0); // DWC_DDRPHYA_MASTER0_base0_DfiFreqXlat5 +dwc_ddrphy_apb_wr(0x200f6, 0x0); // DWC_DDRPHYA_MASTER0_base0_DfiFreqXlat6 +dwc_ddrphy_apb_wr(0x200f7, 0xf000); // DWC_DDRPHYA_MASTER0_base0_DfiFreqXlat7 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming Seq0BDLY0 to 0x64 +dwc_ddrphy_apb_wr(0x2000b, 0x64); // DWC_DDRPHYA_MASTER0_base0_Seq0BDLY0_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming Seq0BDLY1 to 0xc8 +dwc_ddrphy_apb_wr(0x2000c, 0xc8); // DWC_DDRPHYA_MASTER0_base0_Seq0BDLY1_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming Seq0BDLY2 to 0x2bc +dwc_ddrphy_apb_wr(0x2000d, 0x2bc); // DWC_DDRPHYA_MASTER0_base0_Seq0BDLY2_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming Seq0BDLY3 to 0x2c +dwc_ddrphy_apb_wr(0x2000e, 0x2c); // DWC_DDRPHYA_MASTER0_base0_Seq0BDLY3_p0 +//// [phyinit_C_initPhyConfig] Disabling DBYTE 0 Lane 8 (DBI) Receiver to save power. +dwc_ddrphy_apb_wr(0x1004a, 0x500); // DWC_DDRPHYA_DBYTE0_base0_DqDqsRcvCntrl1 +//// [phyinit_C_initPhyConfig] Disabling DBYTE 1 Lane 8 (DBI) Receiver to save power. +dwc_ddrphy_apb_wr(0x1104a, 0x500); // DWC_DDRPHYA_DBYTE1_base0_DqDqsRcvCntrl1 +//// [phyinit_C_initPhyConfig] Programming MasterX4Config::X4TG to 0x0 +dwc_ddrphy_apb_wr(0x20025, 0x0); // DWC_DDRPHYA_MASTER0_base0_MasterX4Config +// [phyinit_C_initPhyConfig] Programming DfiDataEnLatency::WLm13 and RLm13 +dwc_ddrphy_apb_wr(0x2019a, 0x18); // DWC_DDRPHYA_MASTER0_base0_DfiDataEnLatency +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, rd_Crc = 0 cwl= 24 , cl = 26 mr_cl =2 MR0_A0 = 0x8 +dwc_ddrphy_apb_wr(0x400f5, 0x1200); // DWC_DDRPHYA_ACSM0_base0_AcsmCtrl5_p0 +dwc_ddrphy_apb_wr(0x400f6, 0x10); // DWC_DDRPHYA_ACSM0_base0_AcsmCtrl6_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming D5ACSM0RxEnPulse to 2062 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming D5ACSM0RxValPulse to 2062 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming D5ACSM0RdcsPulse to 2062 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming D5ACSM0TxEnPulse to 2060 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming D5ACSM0WrcsPulse to 2060 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming D5ACSM0SnoopPulse to 2062 +dwc_ddrphy_apb_wr(0x20120, 0x80e); // DWC_DDRPHYA_MASTER0_base0_D5ACSM0RxEnPulse_p0 +dwc_ddrphy_apb_wr(0x20121, 0x80e); // DWC_DDRPHYA_MASTER0_base0_D5ACSM0RxValPulse_p0 +dwc_ddrphy_apb_wr(0x20124, 0x80e); // DWC_DDRPHYA_MASTER0_base0_D5ACSM0RdcsPulse_p0 +dwc_ddrphy_apb_wr(0x20122, 0x80c); // DWC_DDRPHYA_MASTER0_base0_D5ACSM0TxEnPulse_p0 +dwc_ddrphy_apb_wr(0x20123, 0x80c); // DWC_DDRPHYA_MASTER0_base0_D5ACSM0WrcsPulse_p0 +dwc_ddrphy_apb_wr(0x20125, 0x80e); // DWC_DDRPHYA_MASTER0_base0_D5ACSM0SnoopPulse_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming D5ACSM0SnoopVal to 801 +dwc_ddrphy_apb_wr(0x2012e, 0x321); // DWC_DDRPHYA_MASTER0_base0_D5ACSM0SnoopVal +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming D5ACSM1RxEnPulse to 2062 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming D5ACSM1RxValPulse to 2062 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming D5ACSM1RdcsPulse to 2062 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming D5ACSM1TxEnPulse to 2060 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming D5ACSM1WrcsPulse to 2060 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming D5ACSM1SnoopPulse to 2062 +dwc_ddrphy_apb_wr(0x20140, 0x80e); // DWC_DDRPHYA_MASTER0_base0_D5ACSM1RxEnPulse_p0 +dwc_ddrphy_apb_wr(0x20141, 0x80e); // DWC_DDRPHYA_MASTER0_base0_D5ACSM1RxValPulse_p0 +dwc_ddrphy_apb_wr(0x20144, 0x80e); // DWC_DDRPHYA_MASTER0_base0_D5ACSM1RdcsPulse_p0 +dwc_ddrphy_apb_wr(0x20142, 0x80c); // DWC_DDRPHYA_MASTER0_base0_D5ACSM1TxEnPulse_p0 +dwc_ddrphy_apb_wr(0x20143, 0x80c); // DWC_DDRPHYA_MASTER0_base0_D5ACSM1WrcsPulse_p0 +dwc_ddrphy_apb_wr(0x20145, 0x80e); // DWC_DDRPHYA_MASTER0_base0_D5ACSM1SnoopPulse_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming D5ACSM1SnoopVal to 801 +dwc_ddrphy_apb_wr(0x2014e, 0x321); // DWC_DDRPHYA_MASTER0_base0_D5ACSM1SnoopVal +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming GPR7(csrAlertRecovery) to 0x0 +dwc_ddrphy_apb_wr(0x90307, 0x0); // DWC_DDRPHYA_INITENG0_base0_Seq0BGPR7_p0 +// [phyinit_C_initPhyConfig] Programming TimingModeCntrl::Dly64Prec to 0x1 +dwc_ddrphy_apb_wr(0x20040, 0x1); // DWC_DDRPHYA_MASTER0_base0_TimingModeCntrl +// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming VREGCtrl3::VshCtrlUpdate to 0x1 for MASTER +dwc_ddrphy_apb_wr(0x20066, 0x1); // DWC_DDRPHYA_MASTER0_base0_VREGCtrl3 +// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming VREGCtrl3::VshCtrlUpdate to 0x1 for all DBYTEs +dwc_ddrphy_apb_wr(0x10066, 0x1); // DWC_DDRPHYA_DBYTE0_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x11066, 0x1); // DWC_DDRPHYA_DBYTE1_base0_VREGCtrl3 +// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming VREGCtrl3::VshCtrlUpdate to 0x1 for all ANIBs +dwc_ddrphy_apb_wr(0x66, 0x1); // DWC_DDRPHYA_ANIB0_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x1066, 0x1); // DWC_DDRPHYA_ANIB1_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x2066, 0x1); // DWC_DDRPHYA_ANIB2_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x3066, 0x1); // DWC_DDRPHYA_ANIB3_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x4066, 0x1); // DWC_DDRPHYA_ANIB4_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x5066, 0x1); // DWC_DDRPHYA_ANIB5_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x6066, 0x1); // DWC_DDRPHYA_ANIB6_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x7066, 0x1); // DWC_DDRPHYA_ANIB7_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x8066, 0x1); // DWC_DDRPHYA_ANIB8_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x9066, 0x1); // DWC_DDRPHYA_ANIB9_base0_VREGCtrl3 +// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming AcClkDLLControl to 0x1080 +dwc_ddrphy_apb_wr(0x200ea, 0x1080); // DWC_DDRPHYA_MASTER0_base0_AcClkDLLControl_p0 +// [phyinit_C_initPhyConfig] Programming ArcPmuEccCtl to 0x1 +dwc_ddrphy_apb_wr(0xc0086, 0x1); // DWC_DDRPHYA_DRTUB0_ArcPmuEccCtl +// [phyinit_C_initPhyConfig] Programming VREGCtrl2 to 0x9820 for MASTER +dwc_ddrphy_apb_wr(0x2002b, 0x9820); // DWC_DDRPHYA_MASTER0_base0_VREGCtrl2 +// [phyinit_C_initPhyConfig] Programming VREGCtrl2 to 0x8020 for all DBYTEs +dwc_ddrphy_apb_wr(0x1002b, 0x8020); // DWC_DDRPHYA_DBYTE0_base0_VREGCtrl2 +dwc_ddrphy_apb_wr(0x1102b, 0x8020); // DWC_DDRPHYA_DBYTE1_base0_VREGCtrl2 +// [phyinit_C_initPhyConfig] Programming VREGCtrl2 to 0x8020 for all ANIBs +dwc_ddrphy_apb_wr(0x2b, 0x8020); // DWC_DDRPHYA_ANIB0_base0_VREGCtrl2 +dwc_ddrphy_apb_wr(0x102b, 0x8020); // DWC_DDRPHYA_ANIB1_base0_VREGCtrl2 +dwc_ddrphy_apb_wr(0x202b, 0x8020); // DWC_DDRPHYA_ANIB2_base0_VREGCtrl2 +dwc_ddrphy_apb_wr(0x302b, 0x8020); // DWC_DDRPHYA_ANIB3_base0_VREGCtrl2 +dwc_ddrphy_apb_wr(0x402b, 0x8020); // DWC_DDRPHYA_ANIB4_base0_VREGCtrl2 +dwc_ddrphy_apb_wr(0x502b, 0x8020); // DWC_DDRPHYA_ANIB5_base0_VREGCtrl2 +dwc_ddrphy_apb_wr(0x602b, 0x8020); // DWC_DDRPHYA_ANIB6_base0_VREGCtrl2 +dwc_ddrphy_apb_wr(0x702b, 0x8020); // DWC_DDRPHYA_ANIB7_base0_VREGCtrl2 +dwc_ddrphy_apb_wr(0x802b, 0x8020); // DWC_DDRPHYA_ANIB8_base0_VREGCtrl2 +dwc_ddrphy_apb_wr(0x902b, 0x8020); // DWC_DDRPHYA_ANIB9_base0_VREGCtrl2 +// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming VREGCtrl3::VshCtrlUpdate to 0x0 for MASTER +dwc_ddrphy_apb_wr(0x20066, 0x0); // DWC_DDRPHYA_MASTER0_base0_VREGCtrl3 +// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming VREGCtrl3::VshCtrlUpdate to 0x0 for all DBYTEs +dwc_ddrphy_apb_wr(0x10066, 0x0); // DWC_DDRPHYA_DBYTE0_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x11066, 0x0); // DWC_DDRPHYA_DBYTE1_base0_VREGCtrl3 +// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming VREGCtrl3::VshCtrlUpdate to 0x0 for all ANIBs +dwc_ddrphy_apb_wr(0x66, 0x0); // DWC_DDRPHYA_ANIB0_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x1066, 0x0); // DWC_DDRPHYA_ANIB1_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x2066, 0x0); // DWC_DDRPHYA_ANIB2_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x3066, 0x0); // DWC_DDRPHYA_ANIB3_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x4066, 0x0); // DWC_DDRPHYA_ANIB4_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x5066, 0x0); // DWC_DDRPHYA_ANIB5_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x6066, 0x0); // DWC_DDRPHYA_ANIB6_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x7066, 0x0); // DWC_DDRPHYA_ANIB7_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x8066, 0x0); // DWC_DDRPHYA_ANIB8_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x9066, 0x0); // DWC_DDRPHYA_ANIB9_base0_VREGCtrl3 +// [phyinit_C_initPhyConfig] Programming VrefDAC0 to 0x3f for all DBYTEs and lanes +// [phyinit_C_initPhyConfig] Programming VrefDAC1 to 0x3f for all DBYTEs and lanes +// [phyinit_C_initPhyConfig] Programming VrefDAC2 to 0x3f for all DBYTEs and lanes +// [phyinit_C_initPhyConfig] Programming VrefDAC3 to 0x3f for all DBYTEs and lanes +dwc_ddrphy_apb_wr(0x10040, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC0_r0_p0 +dwc_ddrphy_apb_wr(0x10030, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC1_r0 +dwc_ddrphy_apb_wr(0x10050, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC2_r0 +dwc_ddrphy_apb_wr(0x10060, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC3_r0 +dwc_ddrphy_apb_wr(0x10140, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC0_r1_p0 +dwc_ddrphy_apb_wr(0x10130, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC1_r1 +dwc_ddrphy_apb_wr(0x10150, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC2_r1 +dwc_ddrphy_apb_wr(0x10160, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC3_r1 +dwc_ddrphy_apb_wr(0x10240, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC0_r2_p0 +dwc_ddrphy_apb_wr(0x10230, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC1_r2 +dwc_ddrphy_apb_wr(0x10250, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC2_r2 +dwc_ddrphy_apb_wr(0x10260, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC3_r2 +dwc_ddrphy_apb_wr(0x10340, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC0_r3_p0 +dwc_ddrphy_apb_wr(0x10330, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC1_r3 +dwc_ddrphy_apb_wr(0x10350, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC2_r3 +dwc_ddrphy_apb_wr(0x10360, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC3_r3 +dwc_ddrphy_apb_wr(0x10440, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC0_r4_p0 +dwc_ddrphy_apb_wr(0x10430, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC1_r4 +dwc_ddrphy_apb_wr(0x10450, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC2_r4 +dwc_ddrphy_apb_wr(0x10460, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC3_r4 +dwc_ddrphy_apb_wr(0x10540, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC0_r5_p0 +dwc_ddrphy_apb_wr(0x10530, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC1_r5 +dwc_ddrphy_apb_wr(0x10550, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC2_r5 +dwc_ddrphy_apb_wr(0x10560, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC3_r5 +dwc_ddrphy_apb_wr(0x10640, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC0_r6_p0 +dwc_ddrphy_apb_wr(0x10630, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC1_r6 +dwc_ddrphy_apb_wr(0x10650, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC2_r6 +dwc_ddrphy_apb_wr(0x10660, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC3_r6 +dwc_ddrphy_apb_wr(0x10740, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC0_r7_p0 +dwc_ddrphy_apb_wr(0x10730, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC1_r7 +dwc_ddrphy_apb_wr(0x10750, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC2_r7 +dwc_ddrphy_apb_wr(0x10760, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC3_r7 +dwc_ddrphy_apb_wr(0x10840, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC0_r8_p0 +dwc_ddrphy_apb_wr(0x10830, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC1_r8 +dwc_ddrphy_apb_wr(0x10850, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC2_r8 +dwc_ddrphy_apb_wr(0x10860, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC3_r8 +dwc_ddrphy_apb_wr(0x11040, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC0_r0_p0 +dwc_ddrphy_apb_wr(0x11030, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC1_r0 +dwc_ddrphy_apb_wr(0x11050, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC2_r0 +dwc_ddrphy_apb_wr(0x11060, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC3_r0 +dwc_ddrphy_apb_wr(0x11140, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC0_r1_p0 +dwc_ddrphy_apb_wr(0x11130, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC1_r1 +dwc_ddrphy_apb_wr(0x11150, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC2_r1 +dwc_ddrphy_apb_wr(0x11160, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC3_r1 +dwc_ddrphy_apb_wr(0x11240, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC0_r2_p0 +dwc_ddrphy_apb_wr(0x11230, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC1_r2 +dwc_ddrphy_apb_wr(0x11250, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC2_r2 +dwc_ddrphy_apb_wr(0x11260, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC3_r2 +dwc_ddrphy_apb_wr(0x11340, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC0_r3_p0 +dwc_ddrphy_apb_wr(0x11330, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC1_r3 +dwc_ddrphy_apb_wr(0x11350, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC2_r3 +dwc_ddrphy_apb_wr(0x11360, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC3_r3 +dwc_ddrphy_apb_wr(0x11440, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC0_r4_p0 +dwc_ddrphy_apb_wr(0x11430, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC1_r4 +dwc_ddrphy_apb_wr(0x11450, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC2_r4 +dwc_ddrphy_apb_wr(0x11460, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC3_r4 +dwc_ddrphy_apb_wr(0x11540, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC0_r5_p0 +dwc_ddrphy_apb_wr(0x11530, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC1_r5 +dwc_ddrphy_apb_wr(0x11550, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC2_r5 +dwc_ddrphy_apb_wr(0x11560, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC3_r5 +dwc_ddrphy_apb_wr(0x11640, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC0_r6_p0 +dwc_ddrphy_apb_wr(0x11630, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC1_r6 +dwc_ddrphy_apb_wr(0x11650, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC2_r6 +dwc_ddrphy_apb_wr(0x11660, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC3_r6 +dwc_ddrphy_apb_wr(0x11740, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC0_r7_p0 +dwc_ddrphy_apb_wr(0x11730, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC1_r7 +dwc_ddrphy_apb_wr(0x11750, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC2_r7 +dwc_ddrphy_apb_wr(0x11760, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC3_r7 +dwc_ddrphy_apb_wr(0x11840, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC0_r8_p0 +dwc_ddrphy_apb_wr(0x11830, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC1_r8 +dwc_ddrphy_apb_wr(0x11850, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC2_r8 +dwc_ddrphy_apb_wr(0x11860, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC3_r8 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DfiFreqRatio_p0 to 0x1 +dwc_ddrphy_apb_wr(0x200fa, 0x1); // DWC_DDRPHYA_MASTER0_base0_DfiFreqRatio_p0 +//// [phyinit_C_initPhyConfig] Programming PptCtlStatic::DOCByteSelTg0 (dbyte=0) to 0x0 +//// [phyinit_C_initPhyConfig] Programming PptCtlStatic::DOCByteSelTg1 (dbyte=0) to 0x0 +//// [phyinit_C_initPhyConfig] Programming PptCtlStatic::DOCByteSelTg2 (dbyte=0) to 0x0 +//// [phyinit_C_initPhyConfig] Programming PptCtlStatic::DOCByteSelTg3 (dbyte=0) to 0x0 +//// [phyinit_C_initPhyConfig] Programming PptCtlStatic::NoX4onUpperNibbleTg0 (dbyte=0) to 0x0 +//// [phyinit_C_initPhyConfig] Programming PptCtlStatic::NoX4onUpperNibbleTg1 (dbyte=0) to 0x0 +//// [phyinit_C_initPhyConfig] Programming PptCtlStatic::NoX4onUpperNibbleTg2 (dbyte=0) to 0x0 +//// [phyinit_C_initPhyConfig] Programming PptCtlStatic::NoX4onUpperNibbleTg3 (dbyte=0) to 0x0 +dwc_ddrphy_apb_wr(0x100aa, 0x0); // DWC_DDRPHYA_DBYTE0_base0_PptCtlStatic +//// [phyinit_C_initPhyConfig] Programming PptCtlStatic::DOCByteSelTg0 (dbyte=1) to 0x0 +//// [phyinit_C_initPhyConfig] Programming PptCtlStatic::DOCByteSelTg1 (dbyte=1) to 0x0 +//// [phyinit_C_initPhyConfig] Programming PptCtlStatic::DOCByteSelTg2 (dbyte=1) to 0x0 +//// [phyinit_C_initPhyConfig] Programming PptCtlStatic::DOCByteSelTg3 (dbyte=1) to 0x0 +//// [phyinit_C_initPhyConfig] Programming PptCtlStatic::NoX4onUpperNibbleTg0 (dbyte=1) to 0x0 +//// [phyinit_C_initPhyConfig] Programming PptCtlStatic::NoX4onUpperNibbleTg1 (dbyte=1) to 0x0 +//// [phyinit_C_initPhyConfig] Programming PptCtlStatic::NoX4onUpperNibbleTg2 (dbyte=1) to 0x0 +//// [phyinit_C_initPhyConfig] Programming PptCtlStatic::NoX4onUpperNibbleTg3 (dbyte=1) to 0x0 +dwc_ddrphy_apb_wr(0x110aa, 0x0); // DWC_DDRPHYA_DBYTE1_base0_PptCtlStatic +//// [phyinit_C_initPhyConfig] Programming ForceClkGaterEnables::ForcePubDxClkEnLow to 0x0 +dwc_ddrphy_apb_wr(0x200a6, 0x0); // DWC_DDRPHYA_MASTER0_base0_ForceClkGaterEnables +//// [phyinit_C_initPhyConfig] Programming AForceTriCont (anib=0) to 0xc +//// [phyinit_C_initPhyConfig] Programming AForceTriCont (anib=4) to 0x8 +//// [phyinit_C_initPhyConfig] Programming AForceTriCont (anib=6) to 0xf +//// [phyinit_C_initPhyConfig] Programming AForceTriCont (anib=7) to 0xf +//// [phyinit_C_initPhyConfig] Programming AForceTriCont (anib=8) to 0xf +//// [phyinit_C_initPhyConfig] Programming AForceTriCont (anib=9) to 0xf +dwc_ddrphy_apb_wr(0x28, 0xc); // DWC_DDRPHYA_ANIB0_base0_AForceTriCont +dwc_ddrphy_apb_wr(0x4028, 0x8); // DWC_DDRPHYA_ANIB4_base0_AForceTriCont +dwc_ddrphy_apb_wr(0x6028, 0xf); // DWC_DDRPHYA_ANIB6_base0_AForceTriCont +dwc_ddrphy_apb_wr(0x7028, 0xf); // DWC_DDRPHYA_ANIB7_base0_AForceTriCont +dwc_ddrphy_apb_wr(0x8028, 0xf); // DWC_DDRPHYA_ANIB8_base0_AForceTriCont +dwc_ddrphy_apb_wr(0x9028, 0xf); // DWC_DDRPHYA_ANIB9_base0_AForceTriCont +//// [phyinit_C_initPhyConfig] End of dwc_ddrphy_phyinit_C_initPhyConfig() +// +// +////############################################################## +//// +//// dwc_ddrphy_phyinit_userCustom_customPreTrain is a user-editable function. +//// +//// The purpose of dwc_ddrphy_phyinit_userCustom_customPreTrain() is to override any +//// any message block fields calculated by Phyinit in dwc_ddrphy_phyinit_calcMb() or to +//// override any CSR values programmed by Phyinit in dwc_ddrphy_phyinit_C_initPhyConfig(). +//// This function is executed before training and thus any override here might affect +//// training result. +//// +//// IMPORTANT: in this function, user shall not override any values in userInputBasic and +//// userInputAdvanced data structures. Use dwc_ddrphy_phyinit_userCustom_overrideUserInput() +//// to modify values in those data structures. +//// +////############################################################## +// +//// [phyinit_userCustom_customPreTrain] Start of dwc_ddrphy_phyinit_userCustom_customPreTrain() +//// [phyinit_userCustom_customPreTrain] End of dwc_ddrphy_phyinit_userCustom_customPreTrain() +//// [dwc_ddrphy_phyinit_D_loadIMEM, 1D] Start of dwc_ddrphy_phyinit_D_loadIMEM (Train2D=0) +// +// +////############################################################## +//// +//// (D) Load the 1D IMEM image +//// +//// This function loads the training firmware IMEM image into the SRAM. +//// See PhyInit App Note for detailed description and function usage +//// +////############################################################## +// +// +//// [dwc_ddrphy_phyinit_D_loadIMEM, 1D] Programming MemResetL to 0x2 +dwc_ddrphy_apb_wr(0x20060, 0x2); // DWC_DDRPHYA_MASTER0_base0_MemResetL +// [dwc_ddrphy_phyinit_storeIncvFile] Reading input file: /home/jerry_ku/Project/Development/ast2700dev/ddr45phy_tsmc12/coreConsultant/config3_3.50a/2022-12-12-17-01-49/firmware/Latest/training/ddr5/ddr5_pmu_train_imem.incv + +//// 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. +//// This allows the memory controller unrestricted access to the configuration CSRs. +dwc_ddrphy_apb_wr(0xd0000, 0x0); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel +//// [phyinit_userCustom_wait] Wait 40 DfiClks +//// [dwc_ddrphy_phyinit_WriteOutMem] STARTING 32bit write. offset 0x50000 size 0x8000 +dwc_ddrphy_phyinit_userCustom_D_loadIMEM(sdrammc, 0); + +//// [dwc_ddrphy_phyinit_WriteOutMem] DONE. Index 0x8000 +//// 2. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. +//// This allows the firmware unrestricted access to the configuration CSRs. +dwc_ddrphy_apb_wr(0xd0000, 0x1); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel +//// [phyinit_userCustom_wait] Wait 40 DfiClks +//// [dwc_ddrphy_phyinit_D_loadIMEM, 1D] End of dwc_ddrphy_phyinit_D_loadIMEM() +// +// +////############################################################## +//// +//// 4.3.5(E) Set the PHY input clocks to the desired frequency for pstate 0 +//// +//// Set the PHY input Dfi Clk to the desired operating frequency associated with the given Pstate. Before proceeding to the next step, +//// the clock should be stable at the new frequency. For more information on clocking requirements, see "Clocks" on page <XXX>. +//// +////############################################################## +// +dwc_ddrphy_phyinit_userCustom_E_setDfiClk(sdrammc); + +// +//// [dwc_ddrphy_phyinit_userCustom_E_setDfiClk] End of dwc_ddrphy_phyinit_userCustom_E_setDfiClk() +//// [phyinit_F_loadDMEM, 1D] Start of dwc_ddrphy_phyinit_F_loadDMEM (pstate=0, Train2D=0) +// +// +////############################################################## +//// +//// 4.3.5(F) Load the 1D DMEM image and write the 1D Message Block parameters for the training firmware +//// +//// The procedure is as follows: +//// +////############################################################## +// +// +// +//// 1. Load the firmware DMEM segment to initialize the data structures. +// +//// 2. Write the Firmware Message Block with the required contents detailing the training parameters. +// +// [dwc_ddrphy_phyinit_storeIncvFile] Reading input file: /home/jerry_ku/Project/Development/ast2700dev/ddr45phy_tsmc12/coreConsultant/config3_3.50a/2022-12-12-17-01-49/firmware/Latest/training/ddr5/ddr5_pmu_train_dmem.incv + +//// 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. +//// This allows the memory controller unrestricted access to the configuration CSRs. +dwc_ddrphy_apb_wr(0xd0000, 0x0); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel +//// [phyinit_userCustom_wait] Wait 40 DfiClks +//// [dwc_ddrphy_phyinit_WriteOutMem] STARTING 32bit write. offset 0x58000 size 0x8000 + +dwc_ddrphy_phyinit_userCustom_F_loadDMEM(sdrammc, 0, 0); + +dwc_ddrphy_apb_wr_32b(0x58000, 0x100); +dwc_ddrphy_apb_wr_32b(0x58002, 0xc800000); +dwc_ddrphy_apb_wr_32b(0x58004, 0x0); +dwc_ddrphy_apb_wr_32b(0x58006, 0x40); +if (IS_ENABLED(CONFIG_ASPEED_PHY_TRAINING_MESSAGE)) + dwc_ddrphy_apb_wr_32b(0x58008, 0x04827f); +else + dwc_ddrphy_apb_wr_32b(0x58008, 0xc8827f); +// Redmine 1392: Set X16Present=1 by Synopsys's comment +// 0x5800b[7:0]=DFIMRLMargin, 0x5800b[15:8]=X16Present +dwc_ddrphy_apb_wr_32b(0x5800a, 0x01020000); +// Redmine 1456: Skip_CA13_during_CAtraining during DDR5 +dwc_ddrphy_apb_wr_32b(0x5800c, 0x10000001); +// Redmine 1392: To speed up data collection, set the voltage and delay step size in Rx2D_TrainOpt and Tx2D_TrainOpt to its maximum value. +// uint8_t RX2D_TrainOpt; // Byte offset 0x1d, CSR Addr 0x5800e, Direction=In +// uint8_t TX2D_TrainOpt; // Byte offset 0x1e, CSR Addr 0x5800f, Direction=In +//dwc_ddrphy_apb_wr_32b(0x5800e, 0x001e1e00); +//#elif defined(TRAIN_1D) +//printf("- <DWC_DDRPHY TRAIN>: Enable RdDQS1D, WrDQ1D for 1D training"); +// #ifdef DWC_DEBUG +//printf("- <DWC_DDRPHY TRAIN>: Debug level = 0x05: Detailed debug messages (e.g. Eye delays)"); +//dwc_ddrphy_apb_wr_32b(0x58008, 0x05821f); +// #else +//printf("- <DWC_DDRPHY TRAIN>: Debug level = 0xC8: Stage completion"); +//dwc_ddrphy_apb_wr_32b(0x58008, 0xc8821f); +// #endif +//// Redmine 1392: Set X16Present=1 by Synopsys's comment +//dwc_ddrphy_apb_wr_32b(0x5800a, 0x01020000); +//// Redmine 1456: Skip_CA13_during_CAtraining during DDR5 +//dwc_ddrphy_apb_wr_32b(0x5800c, 0x18000001); +//// Redmine 1392: To speed up data collection, set the voltage and delay step size in Rx2D_TrainOpt and Tx2D_TrainOpt to its maximum value. +//// uint8_t RX2D_TrainOpt; // Byte offset 0x1d, CSR Addr 0x5800e, Direction=In +//// uint8_t TX2D_TrainOpt; // Byte offset 0x1e, CSR Addr 0x5800f, Direction=In +//dwc_ddrphy_apb_wr_32b(0x5800e, 0x001e1e00); +//#else +//dwc_ddrphy_apb_wr_32b(0x58008, 0xc8837f); +//dwc_ddrphy_apb_wr_32b(0x5800a, 0x20000); +//dwc_ddrphy_apb_wr_32b(0x5800c, 0x8000001); +//dwc_ddrphy_apb_wr_32b(0x5800e, 0x0); +//#endif +dwc_ddrphy_apb_wr_32b(0x58010, 0x0); +dwc_ddrphy_apb_wr_32b(0x58012, 0x110); +dwc_ddrphy_apb_wr_32b(0x58014, 0x0); +dwc_ddrphy_apb_wr_32b(0x58016, 0x0); +dwc_ddrphy_apb_wr_32b(0x58018, 0x0); +dwc_ddrphy_apb_wr_32b(0x5801a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5801c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5801e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58020, 0x0); +dwc_ddrphy_apb_wr_32b(0x58022, 0x0); +dwc_ddrphy_apb_wr_32b(0x58024, 0x0); +dwc_ddrphy_apb_wr_32b(0x58026, 0x0); +dwc_ddrphy_apb_wr_32b(0x58028, 0x0); +dwc_ddrphy_apb_wr_32b(0x5802a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5802c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5802e, 0x84080000); //MR0 0x5802f=0x8(CL=26), MR2 0x5802f=0x84(OP[2]=1 2N mode, OP[7]=enable internal WL training) +dwc_ddrphy_apb_wr_32b(0x58030, 0x200000); //MR5 0x58031=0x20(OP[5]=1 DM enable, OP[2:1]=0 pu 34ohm, 1=40ohm, 2=48ohm, OP7:6]=pd) +dwc_ddrphy_apb_wr_32b(0x58032, 0x2d000800); //MR8 0x58032=0x08(OP[4:3]=1 Write preamble 2 tCK) MR10 0x58033=0x2d(Vref 75%) +dwc_ddrphy_apb_wr_32b(0x58034, 0xd62d); +dwc_ddrphy_apb_wr_32b(0x58036, 0x04240003); //MR32 0x58037=0x24(OP[2:0]=4 CK ODT 80, OP[5:3]=4 CS ODT 80ohm), MR33 0x58037=0x4(OP[2:0]=4 CA ODTt 80ohm) +dwc_ddrphy_apb_wr_32b(0x58038, 0x2c000499); //MR34 0x58038(OP[5:3]=3 RTT_WR 80) +dwc_ddrphy_apb_wr_32b(0x5803a, 0x2c2c); +dwc_ddrphy_apb_wr_32b(0x5803c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5803e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58040, 0x0); +dwc_ddrphy_apb_wr_32b(0x58042, 0x408); +dwc_ddrphy_apb_wr_32b(0x58044, 0x8000020); +dwc_ddrphy_apb_wr_32b(0x58046, 0xd62d2d00); +dwc_ddrphy_apb_wr_32b(0x58048, 0x30000); +dwc_ddrphy_apb_wr_32b(0x5804a, 0x4110000); +dwc_ddrphy_apb_wr_32b(0x5804c, 0x2c2c2c00); +dwc_ddrphy_apb_wr_32b(0x5804e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58050, 0x0); +dwc_ddrphy_apb_wr_32b(0x58052, 0x0); +dwc_ddrphy_apb_wr_32b(0x58054, 0x4080000); +dwc_ddrphy_apb_wr_32b(0x58056, 0x200000); +dwc_ddrphy_apb_wr_32b(0x58058, 0x2d000800); +dwc_ddrphy_apb_wr_32b(0x5805a, 0xd62d); +dwc_ddrphy_apb_wr_32b(0x5805c, 0x3); +dwc_ddrphy_apb_wr_32b(0x5805e, 0x2c000411); +dwc_ddrphy_apb_wr_32b(0x58060, 0x2c2c); +dwc_ddrphy_apb_wr_32b(0x58062, 0x0); +dwc_ddrphy_apb_wr_32b(0x58064, 0x0); +dwc_ddrphy_apb_wr_32b(0x58066, 0x0); +dwc_ddrphy_apb_wr_32b(0x58068, 0x408); +dwc_ddrphy_apb_wr_32b(0x5806a, 0x8000020); +dwc_ddrphy_apb_wr_32b(0x5806c, 0xd62d2d00); +dwc_ddrphy_apb_wr_32b(0x5806e, 0x30000); +dwc_ddrphy_apb_wr_32b(0x58070, 0x4110000); +dwc_ddrphy_apb_wr_32b(0x58072, 0x2c2c2c00); +dwc_ddrphy_apb_wr_32b(0x58074, 0x0); +dwc_ddrphy_apb_wr_32b(0x58076, 0x0); +dwc_ddrphy_apb_wr_32b(0x58078, 0x0); +dwc_ddrphy_apb_wr_32b(0x5807a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5807c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5807e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58080, 0x0); +dwc_ddrphy_apb_wr_32b(0x58082, 0x0); +dwc_ddrphy_apb_wr_32b(0x58084, 0x0); +dwc_ddrphy_apb_wr_32b(0x58086, 0x0); +dwc_ddrphy_apb_wr_32b(0x58088, 0x0); +dwc_ddrphy_apb_wr_32b(0x5808a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5808c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5808e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58090, 0x0); +dwc_ddrphy_apb_wr_32b(0x58092, 0x0); +dwc_ddrphy_apb_wr_32b(0x58094, 0x0); +dwc_ddrphy_apb_wr_32b(0x58096, 0x0); +dwc_ddrphy_apb_wr_32b(0x58098, 0x0); +dwc_ddrphy_apb_wr_32b(0x5809a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5809c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5809e, 0x0); +dwc_ddrphy_apb_wr_32b(0x580a0, 0x0); +dwc_ddrphy_apb_wr_32b(0x580a2, 0x0); +dwc_ddrphy_apb_wr_32b(0x580a4, 0x4080000); +dwc_ddrphy_apb_wr_32b(0x580a6, 0x200000); +dwc_ddrphy_apb_wr_32b(0x580a8, 0x2d000800); +dwc_ddrphy_apb_wr_32b(0x580aa, 0xd62d); +dwc_ddrphy_apb_wr_32b(0x580ac, 0x3); +dwc_ddrphy_apb_wr_32b(0x580ae, 0x2c000411); +dwc_ddrphy_apb_wr_32b(0x580b0, 0x2c2c); +dwc_ddrphy_apb_wr_32b(0x580b2, 0x0); +dwc_ddrphy_apb_wr_32b(0x580b4, 0x0); +dwc_ddrphy_apb_wr_32b(0x580b6, 0x0); +dwc_ddrphy_apb_wr_32b(0x580b8, 0x408); +dwc_ddrphy_apb_wr_32b(0x580ba, 0x8000020); +dwc_ddrphy_apb_wr_32b(0x580bc, 0xd62d2d00); +dwc_ddrphy_apb_wr_32b(0x580be, 0x30000); +dwc_ddrphy_apb_wr_32b(0x580c0, 0x4110000); +dwc_ddrphy_apb_wr_32b(0x580c2, 0x2c2c2c00); +dwc_ddrphy_apb_wr_32b(0x580c4, 0x0); +dwc_ddrphy_apb_wr_32b(0x580c6, 0x0); +dwc_ddrphy_apb_wr_32b(0x580c8, 0x0); +dwc_ddrphy_apb_wr_32b(0x580ca, 0x4080000); +dwc_ddrphy_apb_wr_32b(0x580cc, 0x200000); +dwc_ddrphy_apb_wr_32b(0x580ce, 0x2d000800); +dwc_ddrphy_apb_wr_32b(0x580d0, 0xd62d); +dwc_ddrphy_apb_wr_32b(0x580d2, 0x3); +dwc_ddrphy_apb_wr_32b(0x580d4, 0x2c000411); +dwc_ddrphy_apb_wr_32b(0x580d6, 0x2c2c); +dwc_ddrphy_apb_wr_32b(0x580d8, 0x0); +dwc_ddrphy_apb_wr_32b(0x580da, 0x0); +dwc_ddrphy_apb_wr_32b(0x580dc, 0x0); +dwc_ddrphy_apb_wr_32b(0x580de, 0x408); +dwc_ddrphy_apb_wr_32b(0x580e0, 0x8000020); +dwc_ddrphy_apb_wr_32b(0x580e2, 0xd62d2d00); +dwc_ddrphy_apb_wr_32b(0x580e4, 0x30000); +dwc_ddrphy_apb_wr_32b(0x580e6, 0x4110000); +dwc_ddrphy_apb_wr_32b(0x580e8, 0x2c2c2c00); +dwc_ddrphy_apb_wr_32b(0x580ea, 0x0); +dwc_ddrphy_apb_wr_32b(0x580ec, 0x0); +dwc_ddrphy_apb_wr_32b(0x580ee, 0x0); +dwc_ddrphy_apb_wr_32b(0x580f0, 0x0); +dwc_ddrphy_apb_wr_32b(0x580f2, 0x0); +dwc_ddrphy_apb_wr_32b(0x580f4, 0x0); +dwc_ddrphy_apb_wr_32b(0x580f6, 0x0); +dwc_ddrphy_apb_wr_32b(0x580f8, 0x0); +dwc_ddrphy_apb_wr_32b(0x580fa, 0x0); +dwc_ddrphy_apb_wr_32b(0x580fc, 0x0); +dwc_ddrphy_apb_wr_32b(0x580fe, 0xa00060); // WL_ADJ_START, WL_ADJ_END +dwc_ddrphy_apb_wr_32b(0x58100, 0x1); +dwc_ddrphy_apb_wr_32b(0x58102, 0x0); +dwc_ddrphy_apb_wr_32b(0x58104, 0x0); +dwc_ddrphy_apb_wr_32b(0x58106, 0x0); +dwc_ddrphy_apb_wr_32b(0x58108, 0x0); +dwc_ddrphy_apb_wr_32b(0x5810a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5810c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5810e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58110, 0x0); +dwc_ddrphy_apb_wr_32b(0x58112, 0x0); +dwc_ddrphy_apb_wr_32b(0x58114, 0x0); +dwc_ddrphy_apb_wr_32b(0x58116, 0x0); +dwc_ddrphy_apb_wr_32b(0x58118, 0x0); +dwc_ddrphy_apb_wr_32b(0x5811a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5811c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5811e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58120, 0x0); +dwc_ddrphy_apb_wr_32b(0x58122, 0x0); +dwc_ddrphy_apb_wr_32b(0x58124, 0x0); +dwc_ddrphy_apb_wr_32b(0x58126, 0x0); +dwc_ddrphy_apb_wr_32b(0x58128, 0x0); +dwc_ddrphy_apb_wr_32b(0x5812a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5812c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5812e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58130, 0x0); +dwc_ddrphy_apb_wr_32b(0x58132, 0x0); +dwc_ddrphy_apb_wr_32b(0x58134, 0x0); +dwc_ddrphy_apb_wr_32b(0x58136, 0x0); +dwc_ddrphy_apb_wr_32b(0x58138, 0x0); +dwc_ddrphy_apb_wr_32b(0x5813a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5813c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5813e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58140, 0x0); +dwc_ddrphy_apb_wr_32b(0x58142, 0x0); +dwc_ddrphy_apb_wr_32b(0x58144, 0x0); +dwc_ddrphy_apb_wr_32b(0x58146, 0x0); +dwc_ddrphy_apb_wr_32b(0x58148, 0x0); +dwc_ddrphy_apb_wr_32b(0x5814a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5814c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5814e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58150, 0x0); +dwc_ddrphy_apb_wr_32b(0x58152, 0x0); +dwc_ddrphy_apb_wr_32b(0x58154, 0x0); +dwc_ddrphy_apb_wr_32b(0x58156, 0x0); +dwc_ddrphy_apb_wr_32b(0x58158, 0x0); +dwc_ddrphy_apb_wr_32b(0x5815a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5815c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5815e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58160, 0x0); +dwc_ddrphy_apb_wr_32b(0x58162, 0x0); +dwc_ddrphy_apb_wr_32b(0x58164, 0x0); +dwc_ddrphy_apb_wr_32b(0x58166, 0x0); +dwc_ddrphy_apb_wr_32b(0x58168, 0x0); +dwc_ddrphy_apb_wr_32b(0x5816a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5816c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5816e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58170, 0x0); +dwc_ddrphy_apb_wr_32b(0x58172, 0x0); +dwc_ddrphy_apb_wr_32b(0x58174, 0x0); +dwc_ddrphy_apb_wr_32b(0x58176, 0x0); +dwc_ddrphy_apb_wr_32b(0x58178, 0x0); +dwc_ddrphy_apb_wr_32b(0x5817a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5817c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5817e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58180, 0x1); +dwc_ddrphy_apb_wr_32b(0x58182, 0x0); +dwc_ddrphy_apb_wr_32b(0x58184, 0x0); +dwc_ddrphy_apb_wr_32b(0x58186, 0x0); +dwc_ddrphy_apb_wr_32b(0x58188, 0x0); +dwc_ddrphy_apb_wr_32b(0x5818a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5818c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5818e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58190, 0x0); +dwc_ddrphy_apb_wr_32b(0x58192, 0x0); +dwc_ddrphy_apb_wr_32b(0x58194, 0x0); +dwc_ddrphy_apb_wr_32b(0x58196, 0x0); +dwc_ddrphy_apb_wr_32b(0x58198, 0x0); +dwc_ddrphy_apb_wr_32b(0x5819a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5819c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5819e, 0x0); +dwc_ddrphy_apb_wr_32b(0x581a0, 0x0); +dwc_ddrphy_apb_wr_32b(0x581a2, 0x0); +dwc_ddrphy_apb_wr_32b(0x581a4, 0x0); +dwc_ddrphy_apb_wr_32b(0x581a6, 0x0); +dwc_ddrphy_apb_wr_32b(0x581a8, 0x0); +dwc_ddrphy_apb_wr_32b(0x581aa, 0x0); +dwc_ddrphy_apb_wr_32b(0x581ac, 0x0); +dwc_ddrphy_apb_wr_32b(0x581ae, 0x0); +dwc_ddrphy_apb_wr_32b(0x581b0, 0x0); +dwc_ddrphy_apb_wr_32b(0x581b2, 0x0); +dwc_ddrphy_apb_wr_32b(0x581b4, 0x0); +dwc_ddrphy_apb_wr_32b(0x581b6, 0x0); +dwc_ddrphy_apb_wr_32b(0x581b8, 0x0); +dwc_ddrphy_apb_wr_32b(0x581ba, 0x0); +dwc_ddrphy_apb_wr_32b(0x581bc, 0x0); +dwc_ddrphy_apb_wr_32b(0x581be, 0x0); +dwc_ddrphy_apb_wr_32b(0x581c0, 0x0); +dwc_ddrphy_apb_wr_32b(0x581c2, 0x0); +dwc_ddrphy_apb_wr_32b(0x581c4, 0x0); +dwc_ddrphy_apb_wr_32b(0x581c6, 0x0); +dwc_ddrphy_apb_wr_32b(0x581c8, 0x0); +dwc_ddrphy_apb_wr_32b(0x581ca, 0x0); +dwc_ddrphy_apb_wr_32b(0x581cc, 0x0); +dwc_ddrphy_apb_wr_32b(0x581ce, 0x0); +dwc_ddrphy_apb_wr_32b(0x581d0, 0x0); +dwc_ddrphy_apb_wr_32b(0x581d2, 0x0); +dwc_ddrphy_apb_wr_32b(0x581d4, 0x0); +dwc_ddrphy_apb_wr_32b(0x581d6, 0x0); +dwc_ddrphy_apb_wr_32b(0x581d8, 0x0); +dwc_ddrphy_apb_wr_32b(0x581da, 0x0); +dwc_ddrphy_apb_wr_32b(0x581dc, 0x0); +dwc_ddrphy_apb_wr_32b(0x581de, 0x0); +dwc_ddrphy_apb_wr_32b(0x581e0, 0x0); +dwc_ddrphy_apb_wr_32b(0x581e2, 0x0); +dwc_ddrphy_apb_wr_32b(0x581e4, 0x0); +dwc_ddrphy_apb_wr_32b(0x581e6, 0x0); +dwc_ddrphy_apb_wr_32b(0x581e8, 0x0); +dwc_ddrphy_apb_wr_32b(0x581ea, 0x0); +dwc_ddrphy_apb_wr_32b(0x581ec, 0x0); +dwc_ddrphy_apb_wr_32b(0x581ee, 0x0); +dwc_ddrphy_apb_wr_32b(0x581f0, 0x0); +dwc_ddrphy_apb_wr_32b(0x581f2, 0x0); +dwc_ddrphy_apb_wr_32b(0x581f4, 0x0); +dwc_ddrphy_apb_wr_32b(0x581f6, 0x0); +dwc_ddrphy_apb_wr_32b(0x581f8, 0x0); +dwc_ddrphy_apb_wr_32b(0x581fa, 0x0); +dwc_ddrphy_apb_wr_32b(0x581fc, 0x0); +dwc_ddrphy_apb_wr_32b(0x581fe, 0x0); +dwc_ddrphy_apb_wr_32b(0x58200, 0x1); +dwc_ddrphy_apb_wr_32b(0x58202, 0x0); +dwc_ddrphy_apb_wr_32b(0x58204, 0x0); +dwc_ddrphy_apb_wr_32b(0x58206, 0x0); +dwc_ddrphy_apb_wr_32b(0x58208, 0x0); +dwc_ddrphy_apb_wr_32b(0x5820a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5820c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5820e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58210, 0x0); +dwc_ddrphy_apb_wr_32b(0x58212, 0x0); +dwc_ddrphy_apb_wr_32b(0x58214, 0x0); +dwc_ddrphy_apb_wr_32b(0x58216, 0x0); +dwc_ddrphy_apb_wr_32b(0x58218, 0x0); +dwc_ddrphy_apb_wr_32b(0x5821a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5821c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5821e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58220, 0x0); +dwc_ddrphy_apb_wr_32b(0x58222, 0x0); +dwc_ddrphy_apb_wr_32b(0x58224, 0x0); +dwc_ddrphy_apb_wr_32b(0x58226, 0x0); +dwc_ddrphy_apb_wr_32b(0x58228, 0x0); +dwc_ddrphy_apb_wr_32b(0x5822a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5822c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5822e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58230, 0x0); +dwc_ddrphy_apb_wr_32b(0x58232, 0x0); +dwc_ddrphy_apb_wr_32b(0x58234, 0x0); +dwc_ddrphy_apb_wr_32b(0x58236, 0x0); +dwc_ddrphy_apb_wr_32b(0x58238, 0x0); +dwc_ddrphy_apb_wr_32b(0x5823a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5823c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5823e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58240, 0x0); +dwc_ddrphy_apb_wr_32b(0x58242, 0x0); +dwc_ddrphy_apb_wr_32b(0x58244, 0x0); +dwc_ddrphy_apb_wr_32b(0x58246, 0x0); +dwc_ddrphy_apb_wr_32b(0x58248, 0x0); +dwc_ddrphy_apb_wr_32b(0x5824a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5824c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5824e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58250, 0x0); +dwc_ddrphy_apb_wr_32b(0x58252, 0x0); +dwc_ddrphy_apb_wr_32b(0x58254, 0x0); +dwc_ddrphy_apb_wr_32b(0x58256, 0x0); +dwc_ddrphy_apb_wr_32b(0x58258, 0x0); +dwc_ddrphy_apb_wr_32b(0x5825a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5825c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5825e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58260, 0x0); +dwc_ddrphy_apb_wr_32b(0x58262, 0x0); +dwc_ddrphy_apb_wr_32b(0x58264, 0x0); +dwc_ddrphy_apb_wr_32b(0x58266, 0x0); +dwc_ddrphy_apb_wr_32b(0x58268, 0x0); +dwc_ddrphy_apb_wr_32b(0x5826a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5826c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5826e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58270, 0x0); +dwc_ddrphy_apb_wr_32b(0x58272, 0x0); +dwc_ddrphy_apb_wr_32b(0x58274, 0x0); +dwc_ddrphy_apb_wr_32b(0x58276, 0x0); +dwc_ddrphy_apb_wr_32b(0x58278, 0x0); +dwc_ddrphy_apb_wr_32b(0x5827a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5827c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5827e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58280, 0x1); +dwc_ddrphy_apb_wr_32b(0x58282, 0x0); +dwc_ddrphy_apb_wr_32b(0x58284, 0x0); +dwc_ddrphy_apb_wr_32b(0x58286, 0x0); +dwc_ddrphy_apb_wr_32b(0x58288, 0x0); +dwc_ddrphy_apb_wr_32b(0x5828a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5828c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5828e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58290, 0x0); +dwc_ddrphy_apb_wr_32b(0x58292, 0x0); +dwc_ddrphy_apb_wr_32b(0x58294, 0x0); +dwc_ddrphy_apb_wr_32b(0x58296, 0x0); +dwc_ddrphy_apb_wr_32b(0x58298, 0x0); +dwc_ddrphy_apb_wr_32b(0x5829a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5829c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5829e, 0x0); +dwc_ddrphy_apb_wr_32b(0x582a0, 0x0); +dwc_ddrphy_apb_wr_32b(0x582a2, 0x0); +dwc_ddrphy_apb_wr_32b(0x582a4, 0x0); +dwc_ddrphy_apb_wr_32b(0x582a6, 0x0); +dwc_ddrphy_apb_wr_32b(0x582a8, 0x0); +dwc_ddrphy_apb_wr_32b(0x582aa, 0x0); +dwc_ddrphy_apb_wr_32b(0x582ac, 0x0); +dwc_ddrphy_apb_wr_32b(0x582ae, 0x0); +dwc_ddrphy_apb_wr_32b(0x582b0, 0x0); +dwc_ddrphy_apb_wr_32b(0x582b2, 0x0); +dwc_ddrphy_apb_wr_32b(0x582b4, 0x0); +dwc_ddrphy_apb_wr_32b(0x582b6, 0x0); +dwc_ddrphy_apb_wr_32b(0x582b8, 0x0); +dwc_ddrphy_apb_wr_32b(0x582ba, 0x0); +dwc_ddrphy_apb_wr_32b(0x582bc, 0x0); +dwc_ddrphy_apb_wr_32b(0x582be, 0x0); +dwc_ddrphy_apb_wr_32b(0x582c0, 0x0); +dwc_ddrphy_apb_wr_32b(0x582c2, 0x0); +dwc_ddrphy_apb_wr_32b(0x582c4, 0x0); +dwc_ddrphy_apb_wr_32b(0x582c6, 0x0); +dwc_ddrphy_apb_wr_32b(0x582c8, 0x0); +dwc_ddrphy_apb_wr_32b(0x582ca, 0x0); +dwc_ddrphy_apb_wr_32b(0x582cc, 0x0); +dwc_ddrphy_apb_wr_32b(0x582ce, 0x0); +dwc_ddrphy_apb_wr_32b(0x582d0, 0x0); +dwc_ddrphy_apb_wr_32b(0x582d2, 0x0); +dwc_ddrphy_apb_wr_32b(0x582d4, 0x0); +dwc_ddrphy_apb_wr_32b(0x582d6, 0x0); +dwc_ddrphy_apb_wr_32b(0x582d8, 0x0); +dwc_ddrphy_apb_wr_32b(0x582da, 0x0); +dwc_ddrphy_apb_wr_32b(0x582dc, 0x0); +dwc_ddrphy_apb_wr_32b(0x582de, 0x0); +dwc_ddrphy_apb_wr_32b(0x582e0, 0x0); +dwc_ddrphy_apb_wr_32b(0x582e2, 0x0); +dwc_ddrphy_apb_wr_32b(0x582e4, 0x0); +dwc_ddrphy_apb_wr_32b(0x582e6, 0x0); +dwc_ddrphy_apb_wr_32b(0x582e8, 0x0); +dwc_ddrphy_apb_wr_32b(0x582ea, 0x0); +dwc_ddrphy_apb_wr_32b(0x582ec, 0x0); +dwc_ddrphy_apb_wr_32b(0x582ee, 0x0); +dwc_ddrphy_apb_wr_32b(0x582f0, 0x0); +dwc_ddrphy_apb_wr_32b(0x582f2, 0x0); +dwc_ddrphy_apb_wr_32b(0x582f4, 0x0); +dwc_ddrphy_apb_wr_32b(0x582f6, 0x0); +dwc_ddrphy_apb_wr_32b(0x582f8, 0x0); +dwc_ddrphy_apb_wr_32b(0x582fa, 0x0); +dwc_ddrphy_apb_wr_32b(0x582fc, 0x0); +dwc_ddrphy_apb_wr_32b(0x582fe, 0x0); +dwc_ddrphy_apb_wr_32b(0x58300, 0x17171717); +dwc_ddrphy_apb_wr_32b(0x58302, 0x17171717); +dwc_ddrphy_apb_wr_32b(0x58304, 0x17171717); +dwc_ddrphy_apb_wr_32b(0x58306, 0x17171717); +dwc_ddrphy_apb_wr_32b(0x58308, 0x17171717); +dwc_ddrphy_apb_wr_32b(0x5830a, 0x17171717); +dwc_ddrphy_apb_wr_32b(0x5830c, 0x17171717); +dwc_ddrphy_apb_wr_32b(0x5830e, 0x17171717); +dwc_ddrphy_apb_wr_32b(0x58310, 0x17171717); +dwc_ddrphy_apb_wr_32b(0x58312, 0x17171717); +dwc_ddrphy_apb_wr_32b(0x58314, 0x17171717); +dwc_ddrphy_apb_wr_32b(0x58316, 0x17171717); +dwc_ddrphy_apb_wr_32b(0x58318, 0x17171717); +dwc_ddrphy_apb_wr_32b(0x5831a, 0x17171717); +dwc_ddrphy_apb_wr_32b(0x5831c, 0x17171717); +dwc_ddrphy_apb_wr_32b(0x5831e, 0x17171717); +dwc_ddrphy_apb_wr_32b(0x58320, 0x17171717); +dwc_ddrphy_apb_wr_32b(0x58322, 0x17171717); +dwc_ddrphy_apb_wr_32b(0x58324, 0x17171717); +dwc_ddrphy_apb_wr_32b(0x58326, 0x17171717); +dwc_ddrphy_apb_wr_32b(0x58328, 0x0); +dwc_ddrphy_apb_wr_32b(0x5832a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5832c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5832e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58330, 0x0); +dwc_ddrphy_apb_wr_32b(0x58332, 0x0); +dwc_ddrphy_apb_wr_32b(0x58334, 0x0); +dwc_ddrphy_apb_wr_32b(0x58336, 0x0); +dwc_ddrphy_apb_wr_32b(0x58338, 0x0); +dwc_ddrphy_apb_wr_32b(0x5833a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5833c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5833e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58340, 0x0); +dwc_ddrphy_apb_wr_32b(0x58342, 0x0); +dwc_ddrphy_apb_wr_32b(0x58344, 0x0); +dwc_ddrphy_apb_wr_32b(0x58346, 0x0); +dwc_ddrphy_apb_wr_32b(0x58348, 0x0); +dwc_ddrphy_apb_wr_32b(0x5834a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5834c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5834e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58350, 0x0); +dwc_ddrphy_apb_wr_32b(0x58352, 0x0); +dwc_ddrphy_apb_wr_32b(0x58354, 0x0); +dwc_ddrphy_apb_wr_32b(0x58356, 0x0); +dwc_ddrphy_apb_wr_32b(0x58358, 0x0); +dwc_ddrphy_apb_wr_32b(0x5835a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5835c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5835e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58360, 0x0); +dwc_ddrphy_apb_wr_32b(0x58362, 0x0); +dwc_ddrphy_apb_wr_32b(0x58364, 0x0); +dwc_ddrphy_apb_wr_32b(0x58366, 0x0); +dwc_ddrphy_apb_wr_32b(0x58368, 0x0); +dwc_ddrphy_apb_wr_32b(0x5836a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5836c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5836e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58370, 0x0); +dwc_ddrphy_apb_wr_32b(0x58372, 0x0); +dwc_ddrphy_apb_wr_32b(0x58374, 0x0); +dwc_ddrphy_apb_wr_32b(0x58376, 0x0); +dwc_ddrphy_apb_wr_32b(0x58378, 0x0); +dwc_ddrphy_apb_wr_32b(0x5837a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5837c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5837e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58380, 0x0); +dwc_ddrphy_apb_wr_32b(0x58382, 0x0); +dwc_ddrphy_apb_wr_32b(0x58384, 0x0); +dwc_ddrphy_apb_wr_32b(0x58386, 0x0); +dwc_ddrphy_apb_wr_32b(0x58388, 0x0); +dwc_ddrphy_apb_wr_32b(0x5838a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5838c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5838e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58390, 0x0); +dwc_ddrphy_apb_wr_32b(0x58392, 0x0); +dwc_ddrphy_apb_wr_32b(0x58394, 0x0); +dwc_ddrphy_apb_wr_32b(0x58396, 0x0); +dwc_ddrphy_apb_wr_32b(0x58398, 0x0); +dwc_ddrphy_apb_wr_32b(0x5839a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5839c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5839e, 0x0); +dwc_ddrphy_apb_wr_32b(0x583a0, 0x0); +dwc_ddrphy_apb_wr_32b(0x583a2, 0x0); +dwc_ddrphy_apb_wr_32b(0x583a4, 0x0); +dwc_ddrphy_apb_wr_32b(0x583a6, 0x0); +dwc_ddrphy_apb_wr_32b(0x583a8, 0x0); +dwc_ddrphy_apb_wr_32b(0x583aa, 0x0); +dwc_ddrphy_apb_wr_32b(0x583ac, 0x0); +dwc_ddrphy_apb_wr_32b(0x583ae, 0x0); +dwc_ddrphy_apb_wr_32b(0x583b0, 0x0); +dwc_ddrphy_apb_wr_32b(0x583b2, 0x0); +dwc_ddrphy_apb_wr_32b(0x583b4, 0x0); +dwc_ddrphy_apb_wr_32b(0x583b6, 0x0); +dwc_ddrphy_apb_wr_32b(0x583b8, 0x0); +dwc_ddrphy_apb_wr_32b(0x583ba, 0x0); +dwc_ddrphy_apb_wr_32b(0x583bc, 0x0); +dwc_ddrphy_apb_wr_32b(0x583be, 0x0); +dwc_ddrphy_apb_wr_32b(0x583c0, 0x0); +dwc_ddrphy_apb_wr_32b(0x583c2, 0x0); +dwc_ddrphy_apb_wr_32b(0x583c4, 0x0); +dwc_ddrphy_apb_wr_32b(0x583c6, 0x0); +dwc_ddrphy_apb_wr_32b(0x583c8, 0x0); +dwc_ddrphy_apb_wr_32b(0x583ca, 0x0); +dwc_ddrphy_apb_wr_32b(0x583cc, 0x0); +dwc_ddrphy_apb_wr_32b(0x583ce, 0x0); +dwc_ddrphy_apb_wr_32b(0x583d0, 0x0); +dwc_ddrphy_apb_wr_32b(0x583d2, 0x0); +dwc_ddrphy_apb_wr_32b(0x583d4, 0x0); +dwc_ddrphy_apb_wr_32b(0x583d6, 0x0); +dwc_ddrphy_apb_wr_32b(0x583d8, 0x0); +dwc_ddrphy_apb_wr_32b(0x583da, 0x0); +dwc_ddrphy_apb_wr_32b(0x583dc, 0x0); +dwc_ddrphy_apb_wr_32b(0x583de, 0x0); +dwc_ddrphy_apb_wr_32b(0x583e0, 0x0); +dwc_ddrphy_apb_wr_32b(0x583e2, 0x0); +dwc_ddrphy_apb_wr_32b(0x583e4, 0x0); +dwc_ddrphy_apb_wr_32b(0x583e6, 0x0); +dwc_ddrphy_apb_wr_32b(0x583e8, 0x0); +dwc_ddrphy_apb_wr_32b(0x583ea, 0x0); +dwc_ddrphy_apb_wr_32b(0x583ec, 0x0); +dwc_ddrphy_apb_wr_32b(0x583ee, 0x0); +dwc_ddrphy_apb_wr_32b(0x583f0, 0x0); +dwc_ddrphy_apb_wr_32b(0x583f2, 0x0); +dwc_ddrphy_apb_wr_32b(0x583f4, 0x0); +dwc_ddrphy_apb_wr_32b(0x583f6, 0x0); +dwc_ddrphy_apb_wr_32b(0x583f8, 0x0); +dwc_ddrphy_apb_wr_32b(0x583fa, 0x0); +dwc_ddrphy_apb_wr_32b(0x583fc, 0x0); +dwc_ddrphy_apb_wr_32b(0x583fe, 0x0); +//// [dwc_ddrphy_phyinit_WriteOutMem] DONE. Index 0x8000 +//// 2. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. +//// This allows the firmware unrestricted access to the configuration CSRs. +dwc_ddrphy_apb_wr(0xd0000, 0x1); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel +//// [phyinit_userCustom_wait] Wait 40 DfiClks +//// [phyinit_F_loadDMEM, 1D] End of dwc_ddrphy_phyinit_F_loadDMEM() +// +// +////############################################################## +//// +//// 4.3.7(G) Execute the Training Firmware +//// +//// The training firmware is executed with the following procedure: +//// +////############################################################## +// +// +//// 1. Reset the firmware microcontroller by writing the MicroReset CSR to set the StallToMicro and +//// ResetToMicro fields to 1 (all other fields should be zero). +//// Then rewrite the CSR so that only the StallToMicro remains set (all other fields should be zero). +dwc_ddrphy_apb_wr(0xd0000, 0x1); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel +//// [phyinit_userCustom_wait] Wait 40 DfiClks +dwc_ddrphy_apb_wr(0xd0099, 0x9); // DWC_DDRPHYA_APBONLY0_MicroReset +dwc_ddrphy_apb_wr(0xd0099, 0x1); // DWC_DDRPHYA_APBONLY0_MicroReset +// +//// 2. Begin execution of the training firmware by setting the MicroReset CSR to 4'b0000. +dwc_ddrphy_apb_wr(0xd0099, 0x0); // DWC_DDRPHYA_APBONLY0_MicroReset +// +//// 3. Wait for the training firmware to complete by following the procedure in "uCtrl Initialization and Mailbox Messaging" +//// 4.3.7 3. Wait for the training firmware to complete. Implement timeout function or follow the procedure in "3.4 Running the firmware" of the Training Firmware Application Note to poll the Mailbox message. +dwc_ddrphy_phyinit_userCustom_G_waitFwDone(sdrammc); + +//// [dwc_ddrphy_phyinit_userCustom_G_waitFwDone] End of dwc_ddrphy_phyinit_userCustom_G_waitFwDone() +//// 4. Halt the microcontroller." +dwc_ddrphy_apb_wr(0xd0099, 0x1); // DWC_DDRPHYA_APBONLY0_MicroReset +dwc_ddrphy_apb_wr(0x20089, 0x0); // DWC_DDRPHYA_MASTER0_base0_CalZap +//// [dwc_ddrphy_phyinit_G_execFW] End of dwc_ddrphy_phyinit_G_execFW() +// +// +////############################################################## +//// +//// 4.3.8(H) Read the Message Block results +//// +//// The procedure is as follows: +//// +////############################################################## +// +// +//// 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. +dwc_ddrphy_apb_wr(0xd0000, 0x0); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel +//// [phyinit_userCustom_wait] Wait 40 DfiClks +// +//2. Read the Firmware Message Block to obtain the results from the training. +//This can be accomplished by issuing APB read commands to the DMEM addresses. +//Example: +//if (Train2D) +//{ +// _read_2d_message_block_outputs_ +//} +//else +//{ +// _read_1d_message_block_outputs_ +//} +//This can be accomplished by issuing APB read commands to the DMEM addresses. +dwc_ddrphy_phyinit_userCustom_H_readMsgBlock(sdrammc, 0); + +//[dwc_ddrphy_phyinit_userCustom_H_readMsgBlock] End of dwc_ddrphy_phyinit_userCustom_H_readMsgBlock() +//// 3. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. +dwc_ddrphy_apb_wr(0xd0000, 0x1); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel +//// [phyinit_userCustom_wait] Wait 40 DfiClks +//// 4. If training is required at another frequency, repeat the operations starting at step (E). +//// [dwc_ddrphy_phyinit_H_readMsgBlock] End of dwc_ddrphy_phyinit_H_readMsgBlock() +//// [initRuntimeConfigEnableBits] Start of initRuntimeConfigEnableBits() +//// [initRuntimeConfigEnableBits] enableBits[0] = 0x00000009 +//// [initRuntimeConfigEnableBits] WR_RD_RTT_PARK_A0 = 0x00000000, rtt_required = 0x00000001 +//// [initRuntimeConfigEnableBits] WR_RD_RTT_PARK_A1 = 0x00000000, rtt_required = 0x00000002 +//// [initRuntimeConfigEnableBits] WR_RD_RTT_PARK_A2 = 0x00000000, rtt_required = 0x00000004 +//// [initRuntimeConfigEnableBits] WR_RD_RTT_PARK_A3 = 0x00000000, rtt_required = 0x00000008 +//// [initRuntimeConfigEnableBits] enableBits[1] = 0x00000000 +//// [initRuntimeConfigEnableBits] WR_RD_RTT_PARK_B0 = 0x00000000, rtt_required = 0x00000001 +//// [initRuntimeConfigEnableBits] WR_RD_RTT_PARK_B1 = 0x00000000, rtt_required = 0x00000002 +//// [initRuntimeConfigEnableBits] WR_RD_RTT_PARK_B2 = 0x00000000, rtt_required = 0x00000004 +//// [initRuntimeConfigEnableBits] WR_RD_RTT_PARK_B3 = 0x00000000, rtt_required = 0x00000008 +//// [initRuntimeConfigEnableBits] enableBits[2] = 0x00000000 +//// [initRuntimeConfigEnableBits] End of initRuntimeConfigEnableBits() +//// [phyinit_I_loadPIEImage] Start of dwc_ddrphy_phyinit_I_loadPIEImage() +// +// +////############################################################## +//// +//// 4.3.9(I) Load PHY Init Engine Image +//// +//// Load the PHY Initialization Engine memory with the provided initialization sequence. +//// +////############################################################## +// +// +//// Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. +//// This allows the memory controller unrestricted access to the configuration CSRs. +dwc_ddrphy_apb_wr(0xd0000, 0x0); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel +//// [phyinit_userCustom_wait] Wait 40 DfiClks +//// [phyinit_I_loadPIEImage] Programming ForceClkGaterEnables::ForcePubDxClkEnLow to 0x1 +dwc_ddrphy_apb_wr(0x200a6, 0x2); // DWC_DDRPHYA_MASTER0_base0_ForceClkGaterEnables +//// [phyinit_I_loadPIEImage] Programming PIE Production Code +//// [phyinit_LoadPIECodeSections] Start of dwc_ddrphy_phyinit_LoadPIECodeSections() +//// [phyinit_LoadPIECodeSections] Moving start address from 0 to 90000 +dwc_ddrphy_apb_wr(0x90000, 0x10); // DWC_DDRPHYA_INITENG0_base0_PreSequenceReg0b0s0 +dwc_ddrphy_apb_wr(0x90001, 0x400); // DWC_DDRPHYA_INITENG0_base0_PreSequenceReg0b0s1 +dwc_ddrphy_apb_wr(0x90002, 0x10e); // DWC_DDRPHYA_INITENG0_base0_PreSequenceReg0b0s2 +dwc_ddrphy_apb_wr(0x90003, 0x0); // DWC_DDRPHYA_INITENG0_base0_PreSequenceReg0b1s0 +dwc_ddrphy_apb_wr(0x90004, 0x0); // DWC_DDRPHYA_INITENG0_base0_PreSequenceReg0b1s1 +dwc_ddrphy_apb_wr(0x90005, 0x8); // DWC_DDRPHYA_INITENG0_base0_PreSequenceReg0b1s2 +//// [phyinit_LoadPIECodeSections] Moving start address from 90006 to 41000 +dwc_ddrphy_apb_wr(0x41000, 0x3fff); +dwc_ddrphy_apb_wr(0x41001, 0xff00); +dwc_ddrphy_apb_wr(0x41002, 0x3f); +dwc_ddrphy_apb_wr(0x41003, 0x2c1); +dwc_ddrphy_apb_wr(0x41004, 0x3fff); +dwc_ddrphy_apb_wr(0x41005, 0xff00); +dwc_ddrphy_apb_wr(0x41006, 0x3f); +dwc_ddrphy_apb_wr(0x41007, 0xa01); +dwc_ddrphy_apb_wr(0x41008, 0x3fff); +dwc_ddrphy_apb_wr(0x41009, 0xff00); +dwc_ddrphy_apb_wr(0x4100a, 0x3f); +dwc_ddrphy_apb_wr(0x4100b, 0x1); +dwc_ddrphy_apb_wr(0x4100c, 0xffff); +dwc_ddrphy_apb_wr(0x4100d, 0xff03); +dwc_ddrphy_apb_wr(0x4100e, 0x3ff); +dwc_ddrphy_apb_wr(0x4100f, 0x0); +dwc_ddrphy_apb_wr(0x41010, 0xffff); +dwc_ddrphy_apb_wr(0x41011, 0xff03); +dwc_ddrphy_apb_wr(0x41012, 0x3ff); +dwc_ddrphy_apb_wr(0x41013, 0x1c1); +dwc_ddrphy_apb_wr(0x41014, 0xffff); +dwc_ddrphy_apb_wr(0x41015, 0xff03); +dwc_ddrphy_apb_wr(0x41016, 0x3ff); +dwc_ddrphy_apb_wr(0x41017, 0x1); +dwc_ddrphy_apb_wr(0x41018, 0xffff); +dwc_ddrphy_apb_wr(0x41019, 0xff03); +dwc_ddrphy_apb_wr(0x4101a, 0x3ff); +dwc_ddrphy_apb_wr(0x4101b, 0x2c1); +dwc_ddrphy_apb_wr(0x4101c, 0xffff); +dwc_ddrphy_apb_wr(0x4101d, 0xff03); +dwc_ddrphy_apb_wr(0x4101e, 0x3ff); +dwc_ddrphy_apb_wr(0x4101f, 0x101); +dwc_ddrphy_apb_wr(0x41020, 0x3fff); +dwc_ddrphy_apb_wr(0x41021, 0xff00); +dwc_ddrphy_apb_wr(0x41022, 0x3f); +dwc_ddrphy_apb_wr(0x41023, 0x1); +dwc_ddrphy_apb_wr(0x41024, 0x3fff); +dwc_ddrphy_apb_wr(0x41025, 0xff00); +dwc_ddrphy_apb_wr(0x41026, 0x3ff); +dwc_ddrphy_apb_wr(0x41027, 0x1); +dwc_ddrphy_apb_wr(0x41028, 0xffff); +dwc_ddrphy_apb_wr(0x41029, 0xff03); +dwc_ddrphy_apb_wr(0x4102a, 0x3ff); +dwc_ddrphy_apb_wr(0x4102b, 0x2c1); +dwc_ddrphy_apb_wr(0x4102c, 0xffff); +dwc_ddrphy_apb_wr(0x4102d, 0xff03); +dwc_ddrphy_apb_wr(0x4102e, 0x3ff); +dwc_ddrphy_apb_wr(0x4102f, 0xf901); +dwc_ddrphy_apb_wr(0x41030, 0xffff); +dwc_ddrphy_apb_wr(0x41031, 0xff03); +dwc_ddrphy_apb_wr(0x41032, 0x3ff); +dwc_ddrphy_apb_wr(0x41033, 0x2c1); +dwc_ddrphy_apb_wr(0x41034, 0xffff); +dwc_ddrphy_apb_wr(0x41035, 0xff03); +dwc_ddrphy_apb_wr(0x41036, 0x3ff); +dwc_ddrphy_apb_wr(0x41037, 0x5901); +dwc_ddrphy_apb_wr(0x41038, 0x5a5); +dwc_ddrphy_apb_wr(0x41039, 0x4000); +dwc_ddrphy_apb_wr(0x4103a, 0x3c0); +dwc_ddrphy_apb_wr(0x4103b, 0x1); +dwc_ddrphy_apb_wr(0x4103c, 0xc000); +dwc_ddrphy_apb_wr(0x4103d, 0x3); +dwc_ddrphy_apb_wr(0x4103e, 0x3c0); +dwc_ddrphy_apb_wr(0x4103f, 0x0); +dwc_ddrphy_apb_wr(0x41040, 0xc000); +dwc_ddrphy_apb_wr(0x41041, 0x3); +dwc_ddrphy_apb_wr(0x41042, 0x3c0); +dwc_ddrphy_apb_wr(0x41043, 0x2c1); +dwc_ddrphy_apb_wr(0x41044, 0xc000); +dwc_ddrphy_apb_wr(0x41045, 0x3); +dwc_ddrphy_apb_wr(0x41046, 0x3c0); +dwc_ddrphy_apb_wr(0x41047, 0xa01); +dwc_ddrphy_apb_wr(0x41048, 0xef); +dwc_ddrphy_apb_wr(0x41049, 0xef00); +dwc_ddrphy_apb_wr(0x4104a, 0x3c0); +dwc_ddrphy_apb_wr(0x4104b, 0x1); +dwc_ddrphy_apb_wr(0x4104c, 0xc000); +dwc_ddrphy_apb_wr(0x4104d, 0x3); +dwc_ddrphy_apb_wr(0x4104e, 0x3c0); +dwc_ddrphy_apb_wr(0x4104f, 0x0); +dwc_ddrphy_apb_wr(0x41050, 0xc000); +dwc_ddrphy_apb_wr(0x41051, 0x3); +dwc_ddrphy_apb_wr(0x41052, 0x3c0); +dwc_ddrphy_apb_wr(0x41053, 0x2c1); +dwc_ddrphy_apb_wr(0x41054, 0xc000); +dwc_ddrphy_apb_wr(0x41055, 0x3); +dwc_ddrphy_apb_wr(0x41056, 0x3c0); +dwc_ddrphy_apb_wr(0x41057, 0xff01); +dwc_ddrphy_apb_wr(0x41058, 0xc000); +dwc_ddrphy_apb_wr(0x41059, 0x3); +dwc_ddrphy_apb_wr(0x4105a, 0x3c0); +dwc_ddrphy_apb_wr(0x4105b, 0x2c1); +dwc_ddrphy_apb_wr(0x4105c, 0xc000); +dwc_ddrphy_apb_wr(0x4105d, 0x3); +dwc_ddrphy_apb_wr(0x4105e, 0x3c0); +dwc_ddrphy_apb_wr(0x4105f, 0xff01); +dwc_ddrphy_apb_wr(0x41060, 0xc000); +dwc_ddrphy_apb_wr(0x41061, 0x3); +dwc_ddrphy_apb_wr(0x41062, 0x3c0); +dwc_ddrphy_apb_wr(0x41063, 0x2c1); +dwc_ddrphy_apb_wr(0x41064, 0xc000); +dwc_ddrphy_apb_wr(0x41065, 0x3); +dwc_ddrphy_apb_wr(0x41066, 0x3c0); +dwc_ddrphy_apb_wr(0x41067, 0xa01); +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 1, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 2, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 4, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 8, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 10, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 20, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 40, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 80, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 100, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 200, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 400, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 800, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 1000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 2000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 4000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 8000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 10000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 20000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 40000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 80000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 100000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 200000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 400000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 800000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 1000000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 2000000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 4000000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 8000000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 10000000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 20000000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 40000000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 80000000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 10, type = 0 +//// [phyinit_LoadPIECodeSections] Matched NO enable_bits = 4, type = 0 +dwc_ddrphy_apb_wr(0x41068, 0x85d5); +dwc_ddrphy_apb_wr(0x41069, 0x63); +dwc_ddrphy_apb_wr(0x4106a, 0x3c0); +dwc_ddrphy_apb_wr(0x4106b, 0x400); +dwc_ddrphy_apb_wr(0x4106c, 0xc000); +dwc_ddrphy_apb_wr(0x4106d, 0x3); +dwc_ddrphy_apb_wr(0x4106e, 0x3c0); +dwc_ddrphy_apb_wr(0x4106f, 0x0); +dwc_ddrphy_apb_wr(0x41070, 0xc000); +dwc_ddrphy_apb_wr(0x41071, 0x3); +dwc_ddrphy_apb_wr(0x41072, 0x3c0); +dwc_ddrphy_apb_wr(0x41073, 0x2c1); +dwc_ddrphy_apb_wr(0x41074, 0xc000); +dwc_ddrphy_apb_wr(0x41075, 0x3); +dwc_ddrphy_apb_wr(0x41076, 0x3c0); +dwc_ddrphy_apb_wr(0x41077, 0x1001); +dwc_ddrphy_apb_wr(0x41078, 0x85f5); +dwc_ddrphy_apb_wr(0x41079, 0x63); +dwc_ddrphy_apb_wr(0x4107a, 0x3c0); +dwc_ddrphy_apb_wr(0x4107b, 0x800); +dwc_ddrphy_apb_wr(0x4107c, 0xc000); +dwc_ddrphy_apb_wr(0x4107d, 0x3); +dwc_ddrphy_apb_wr(0x4107e, 0x3c0); +dwc_ddrphy_apb_wr(0x4107f, 0x0); +dwc_ddrphy_apb_wr(0x41080, 0xc000); +dwc_ddrphy_apb_wr(0x41081, 0x3); +dwc_ddrphy_apb_wr(0x41082, 0x3c0); +dwc_ddrphy_apb_wr(0x41083, 0x2c1); +dwc_ddrphy_apb_wr(0x41084, 0xc000); +dwc_ddrphy_apb_wr(0x41085, 0x3); +dwc_ddrphy_apb_wr(0x41086, 0x3c0); +dwc_ddrphy_apb_wr(0x41087, 0x1001); +dwc_ddrphy_apb_wr(0x41088, 0x45d5); +dwc_ddrphy_apb_wr(0x41089, 0x63); +dwc_ddrphy_apb_wr(0x4108a, 0x3c0); +dwc_ddrphy_apb_wr(0x4108b, 0x401); +dwc_ddrphy_apb_wr(0x4108c, 0xc000); +dwc_ddrphy_apb_wr(0x4108d, 0x3); +dwc_ddrphy_apb_wr(0x4108e, 0x3c0); +dwc_ddrphy_apb_wr(0x4108f, 0x1); +dwc_ddrphy_apb_wr(0x41090, 0xc000); +dwc_ddrphy_apb_wr(0x41091, 0x3); +dwc_ddrphy_apb_wr(0x41092, 0x3c0); +dwc_ddrphy_apb_wr(0x41093, 0x2c1); +dwc_ddrphy_apb_wr(0x41094, 0xc000); +dwc_ddrphy_apb_wr(0x41095, 0x3); +dwc_ddrphy_apb_wr(0x41096, 0x3c0); +dwc_ddrphy_apb_wr(0x41097, 0x1001); +dwc_ddrphy_apb_wr(0x41098, 0x45f5); +dwc_ddrphy_apb_wr(0x41099, 0x63); +dwc_ddrphy_apb_wr(0x4109a, 0x3c0); +dwc_ddrphy_apb_wr(0x4109b, 0x801); +dwc_ddrphy_apb_wr(0x4109c, 0xc000); +dwc_ddrphy_apb_wr(0x4109d, 0x3); +dwc_ddrphy_apb_wr(0x4109e, 0x3c0); +dwc_ddrphy_apb_wr(0x4109f, 0x1); +dwc_ddrphy_apb_wr(0x410a0, 0xc000); +dwc_ddrphy_apb_wr(0x410a1, 0x3); +dwc_ddrphy_apb_wr(0x410a2, 0x3c0); +dwc_ddrphy_apb_wr(0x410a3, 0x2c1); +dwc_ddrphy_apb_wr(0x410a4, 0xc000); +dwc_ddrphy_apb_wr(0x410a5, 0x3); +dwc_ddrphy_apb_wr(0x410a6, 0x3c0); +dwc_ddrphy_apb_wr(0x410a7, 0x1001); +dwc_ddrphy_apb_wr(0x410a8, 0xc5d5); +dwc_ddrphy_apb_wr(0x410a9, 0x62); +dwc_ddrphy_apb_wr(0x410aa, 0x3c0); +dwc_ddrphy_apb_wr(0x410ab, 0x402); +dwc_ddrphy_apb_wr(0x410ac, 0xc000); +dwc_ddrphy_apb_wr(0x410ad, 0x3); +dwc_ddrphy_apb_wr(0x410ae, 0x3c0); +dwc_ddrphy_apb_wr(0x410af, 0x2); +dwc_ddrphy_apb_wr(0x410b0, 0xc000); +dwc_ddrphy_apb_wr(0x410b1, 0x3); +dwc_ddrphy_apb_wr(0x410b2, 0x3c0); +dwc_ddrphy_apb_wr(0x410b3, 0x2c1); +dwc_ddrphy_apb_wr(0x410b4, 0xc000); +dwc_ddrphy_apb_wr(0x410b5, 0x3); +dwc_ddrphy_apb_wr(0x410b6, 0x3c0); +dwc_ddrphy_apb_wr(0x410b7, 0x1001); +dwc_ddrphy_apb_wr(0x410b8, 0xc5f5); +dwc_ddrphy_apb_wr(0x410b9, 0x62); +dwc_ddrphy_apb_wr(0x410ba, 0x3c0); +dwc_ddrphy_apb_wr(0x410bb, 0x802); +dwc_ddrphy_apb_wr(0x410bc, 0xc000); +dwc_ddrphy_apb_wr(0x410bd, 0x3); +dwc_ddrphy_apb_wr(0x410be, 0x3c0); +dwc_ddrphy_apb_wr(0x410bf, 0x2); +dwc_ddrphy_apb_wr(0x410c0, 0xc000); +dwc_ddrphy_apb_wr(0x410c1, 0x3); +dwc_ddrphy_apb_wr(0x410c2, 0x3c0); +dwc_ddrphy_apb_wr(0x410c3, 0x2c1); +dwc_ddrphy_apb_wr(0x410c4, 0xc000); +dwc_ddrphy_apb_wr(0x410c5, 0x3); +dwc_ddrphy_apb_wr(0x410c6, 0x3c0); +dwc_ddrphy_apb_wr(0x410c7, 0x1001); +dwc_ddrphy_apb_wr(0x410c8, 0xc5d5); +dwc_ddrphy_apb_wr(0x410c9, 0x61); +dwc_ddrphy_apb_wr(0x410ca, 0x3c0); +dwc_ddrphy_apb_wr(0x410cb, 0x403); +dwc_ddrphy_apb_wr(0x410cc, 0xc000); +dwc_ddrphy_apb_wr(0x410cd, 0x3); +dwc_ddrphy_apb_wr(0x410ce, 0x3c0); +dwc_ddrphy_apb_wr(0x410cf, 0x3); +dwc_ddrphy_apb_wr(0x410d0, 0xc000); +dwc_ddrphy_apb_wr(0x410d1, 0x3); +dwc_ddrphy_apb_wr(0x410d2, 0x3c0); +dwc_ddrphy_apb_wr(0x410d3, 0x2c1); +dwc_ddrphy_apb_wr(0x410d4, 0xc000); +dwc_ddrphy_apb_wr(0x410d5, 0x3); +dwc_ddrphy_apb_wr(0x410d6, 0x3c0); +dwc_ddrphy_apb_wr(0x410d7, 0x1001); +dwc_ddrphy_apb_wr(0x410d8, 0xc5f5); +dwc_ddrphy_apb_wr(0x410d9, 0x61); +dwc_ddrphy_apb_wr(0x410da, 0x3c0); +dwc_ddrphy_apb_wr(0x410db, 0x803); +dwc_ddrphy_apb_wr(0x410dc, 0xc000); +dwc_ddrphy_apb_wr(0x410dd, 0x3); +dwc_ddrphy_apb_wr(0x410de, 0x3c0); +dwc_ddrphy_apb_wr(0x410df, 0x3); +dwc_ddrphy_apb_wr(0x410e0, 0xc000); +dwc_ddrphy_apb_wr(0x410e1, 0x3); +dwc_ddrphy_apb_wr(0x410e2, 0x3c0); +dwc_ddrphy_apb_wr(0x410e3, 0x2c1); +dwc_ddrphy_apb_wr(0x410e4, 0xc000); +dwc_ddrphy_apb_wr(0x410e5, 0x3); +dwc_ddrphy_apb_wr(0x410e6, 0x3c0); +dwc_ddrphy_apb_wr(0x410e7, 0x1d01); +//// [phyinit_LoadPIECodeSections] Matched NO enable_bits = 2, type = 0 +dwc_ddrphy_apb_wr(0x410e8, 0x213); +dwc_ddrphy_apb_wr(0x410e9, 0x0); +dwc_ddrphy_apb_wr(0x410ea, 0x3c0); +dwc_ddrphy_apb_wr(0x410eb, 0x1); +dwc_ddrphy_apb_wr(0x410ec, 0xc000); +dwc_ddrphy_apb_wr(0x410ed, 0x3); +dwc_ddrphy_apb_wr(0x410ee, 0x3c0); +dwc_ddrphy_apb_wr(0x410ef, 0x0); +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 20, type = 0 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 80, type = 0 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 40, type = 0 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 100, type = 0 +dwc_ddrphy_apb_wr(0x410f0, 0xc000); +dwc_ddrphy_apb_wr(0x410f1, 0x3); +dwc_ddrphy_apb_wr(0x410f2, 0x3c0); +dwc_ddrphy_apb_wr(0x410f3, 0x2c1); +dwc_ddrphy_apb_wr(0x410f4, 0xc000); +dwc_ddrphy_apb_wr(0x410f5, 0x3); +dwc_ddrphy_apb_wr(0x410f6, 0x3c0); +dwc_ddrphy_apb_wr(0x410f7, 0xef00); +dwc_ddrphy_apb_wr(0x410f8, 0xc000); +dwc_ddrphy_apb_wr(0x410f9, 0x3); +dwc_ddrphy_apb_wr(0x410fa, 0x3c0); +dwc_ddrphy_apb_wr(0x410fb, 0x2c1); +dwc_ddrphy_apb_wr(0x410fc, 0xc000); +dwc_ddrphy_apb_wr(0x410fd, 0x3); +dwc_ddrphy_apb_wr(0x410fe, 0x3c0); +dwc_ddrphy_apb_wr(0x410ff, 0x5900); +dwc_ddrphy_apb_wr(0x41100, 0x217); +dwc_ddrphy_apb_wr(0x41101, 0x1700); +dwc_ddrphy_apb_wr(0x41102, 0x3c2); +dwc_ddrphy_apb_wr(0x41103, 0x1); +dwc_ddrphy_apb_wr(0x41104, 0xc000); +dwc_ddrphy_apb_wr(0x41105, 0x3); +dwc_ddrphy_apb_wr(0x41106, 0x3c0); +dwc_ddrphy_apb_wr(0x41107, 0x0); +dwc_ddrphy_apb_wr(0x41108, 0xc000); +dwc_ddrphy_apb_wr(0x41109, 0x3); +dwc_ddrphy_apb_wr(0x4110a, 0x3c0); +dwc_ddrphy_apb_wr(0x4110b, 0x2c1); +dwc_ddrphy_apb_wr(0x4110c, 0xc000); +dwc_ddrphy_apb_wr(0x4110d, 0x3); +dwc_ddrphy_apb_wr(0x4110e, 0x3c0); +dwc_ddrphy_apb_wr(0x4110f, 0x400); +dwc_ddrphy_apb_wr(0x41110, 0x3fff); +dwc_ddrphy_apb_wr(0x41111, 0xff00); +dwc_ddrphy_apb_wr(0x41112, 0x3f); +dwc_ddrphy_apb_wr(0x41113, 0x2e1); +dwc_ddrphy_apb_wr(0x41114, 0x3fff); +dwc_ddrphy_apb_wr(0x41115, 0xff00); +dwc_ddrphy_apb_wr(0x41116, 0x3f); +dwc_ddrphy_apb_wr(0x41117, 0xa21); +dwc_ddrphy_apb_wr(0x41118, 0x3fff); +dwc_ddrphy_apb_wr(0x41119, 0xff00); +dwc_ddrphy_apb_wr(0x4111a, 0x3f); +dwc_ddrphy_apb_wr(0x4111b, 0x21); +dwc_ddrphy_apb_wr(0x4111c, 0xffff); +dwc_ddrphy_apb_wr(0x4111d, 0xff03); +dwc_ddrphy_apb_wr(0x4111e, 0x3ff); +dwc_ddrphy_apb_wr(0x4111f, 0x20); +dwc_ddrphy_apb_wr(0x41120, 0xffff); +dwc_ddrphy_apb_wr(0x41121, 0xff03); +dwc_ddrphy_apb_wr(0x41122, 0x3ff); +dwc_ddrphy_apb_wr(0x41123, 0x1e1); +dwc_ddrphy_apb_wr(0x41124, 0xffff); +dwc_ddrphy_apb_wr(0x41125, 0xff03); +dwc_ddrphy_apb_wr(0x41126, 0x3ff); +dwc_ddrphy_apb_wr(0x41127, 0x21); +dwc_ddrphy_apb_wr(0x41128, 0xffff); +dwc_ddrphy_apb_wr(0x41129, 0xff03); +dwc_ddrphy_apb_wr(0x4112a, 0x3ff); +dwc_ddrphy_apb_wr(0x4112b, 0x2e1); +dwc_ddrphy_apb_wr(0x4112c, 0xffff); +dwc_ddrphy_apb_wr(0x4112d, 0xff03); +dwc_ddrphy_apb_wr(0x4112e, 0x3ff); +dwc_ddrphy_apb_wr(0x4112f, 0x121); +dwc_ddrphy_apb_wr(0x41130, 0x3fff); +dwc_ddrphy_apb_wr(0x41131, 0xff00); +dwc_ddrphy_apb_wr(0x41132, 0x3ff); +dwc_ddrphy_apb_wr(0x41133, 0x21); +dwc_ddrphy_apb_wr(0x41134, 0x3fff); +dwc_ddrphy_apb_wr(0x41135, 0xff00); +dwc_ddrphy_apb_wr(0x41136, 0x3ff); +dwc_ddrphy_apb_wr(0x41137, 0x21); +dwc_ddrphy_apb_wr(0x41138, 0x3fff); +dwc_ddrphy_apb_wr(0x41139, 0xff00); +dwc_ddrphy_apb_wr(0x4113a, 0x3ff); +dwc_ddrphy_apb_wr(0x4113b, 0x21); +dwc_ddrphy_apb_wr(0x4113c, 0xffff); +dwc_ddrphy_apb_wr(0x4113d, 0xff03); +dwc_ddrphy_apb_wr(0x4113e, 0x3ff); +dwc_ddrphy_apb_wr(0x4113f, 0x21); +dwc_ddrphy_apb_wr(0x41140, 0xffff); +dwc_ddrphy_apb_wr(0x41141, 0xff03); +dwc_ddrphy_apb_wr(0x41142, 0x3ff); +dwc_ddrphy_apb_wr(0x41143, 0x2e1); +dwc_ddrphy_apb_wr(0x41144, 0xffff); +dwc_ddrphy_apb_wr(0x41145, 0xff03); +dwc_ddrphy_apb_wr(0x41146, 0x3ff); +dwc_ddrphy_apb_wr(0x41147, 0xf921); +dwc_ddrphy_apb_wr(0x41148, 0xffff); +dwc_ddrphy_apb_wr(0x41149, 0xff03); +dwc_ddrphy_apb_wr(0x4114a, 0x3ff); +dwc_ddrphy_apb_wr(0x4114b, 0x2e1); +dwc_ddrphy_apb_wr(0x4114c, 0xffff); +dwc_ddrphy_apb_wr(0x4114d, 0xff03); +dwc_ddrphy_apb_wr(0x4114e, 0x3ff); +dwc_ddrphy_apb_wr(0x4114f, 0x5921); +dwc_ddrphy_apb_wr(0x41150, 0x5a5); +dwc_ddrphy_apb_wr(0x41151, 0xa500); +dwc_ddrphy_apb_wr(0x41152, 0x3c5); +dwc_ddrphy_apb_wr(0x41153, 0x21); +dwc_ddrphy_apb_wr(0x41154, 0xc040); +dwc_ddrphy_apb_wr(0x41155, 0x4003); +dwc_ddrphy_apb_wr(0x41156, 0x3c0); +dwc_ddrphy_apb_wr(0x41157, 0x20); +dwc_ddrphy_apb_wr(0x41158, 0xc000); +dwc_ddrphy_apb_wr(0x41159, 0x3); +dwc_ddrphy_apb_wr(0x4115a, 0x3c0); +dwc_ddrphy_apb_wr(0x4115b, 0x2e1); +dwc_ddrphy_apb_wr(0x4115c, 0xc000); +dwc_ddrphy_apb_wr(0x4115d, 0x3); +dwc_ddrphy_apb_wr(0x4115e, 0x3c0); +dwc_ddrphy_apb_wr(0x4115f, 0xa21); +dwc_ddrphy_apb_wr(0x41160, 0xef); +dwc_ddrphy_apb_wr(0x41161, 0xef00); +dwc_ddrphy_apb_wr(0x41162, 0x3c0); +dwc_ddrphy_apb_wr(0x41163, 0x21); +dwc_ddrphy_apb_wr(0x41164, 0xc000); +dwc_ddrphy_apb_wr(0x41165, 0x3); +dwc_ddrphy_apb_wr(0x41166, 0x3c0); +dwc_ddrphy_apb_wr(0x41167, 0x20); +dwc_ddrphy_apb_wr(0x41168, 0xc000); +dwc_ddrphy_apb_wr(0x41169, 0x3); +dwc_ddrphy_apb_wr(0x4116a, 0x3c0); +dwc_ddrphy_apb_wr(0x4116b, 0x2e1); +dwc_ddrphy_apb_wr(0x4116c, 0xc000); +dwc_ddrphy_apb_wr(0x4116d, 0x3); +dwc_ddrphy_apb_wr(0x4116e, 0x3c0); +dwc_ddrphy_apb_wr(0x4116f, 0xff21); +dwc_ddrphy_apb_wr(0x41170, 0xc000); +dwc_ddrphy_apb_wr(0x41171, 0x3); +dwc_ddrphy_apb_wr(0x41172, 0x3c0); +dwc_ddrphy_apb_wr(0x41173, 0x2e1); +dwc_ddrphy_apb_wr(0x41174, 0xc000); +dwc_ddrphy_apb_wr(0x41175, 0x3); +dwc_ddrphy_apb_wr(0x41176, 0x3c0); +dwc_ddrphy_apb_wr(0x41177, 0xff21); +dwc_ddrphy_apb_wr(0x41178, 0xc000); +dwc_ddrphy_apb_wr(0x41179, 0x3); +dwc_ddrphy_apb_wr(0x4117a, 0x3c0); +dwc_ddrphy_apb_wr(0x4117b, 0x2e1); +dwc_ddrphy_apb_wr(0x4117c, 0xc000); +dwc_ddrphy_apb_wr(0x4117d, 0x3); +dwc_ddrphy_apb_wr(0x4117e, 0x3c0); +dwc_ddrphy_apb_wr(0x4117f, 0xa21); +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 1, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 2, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 4, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 8, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 10, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 20, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 40, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 80, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 100, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 200, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 400, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 800, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 1000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 2000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 4000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 8000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 10000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 20000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 40000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 80000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 100000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 200000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 400000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 800000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 1000000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 2000000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 4000000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 8000000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 10000000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 20000000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 40000000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 80000000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 10, type = 0 +//// [phyinit_LoadPIECodeSections] Matched NO enable_bits = 4, type = 0 +dwc_ddrphy_apb_wr(0x41180, 0x85d5); +dwc_ddrphy_apb_wr(0x41181, 0xd563); +dwc_ddrphy_apb_wr(0x41182, 0x3c5); +dwc_ddrphy_apb_wr(0x41183, 0x420); +dwc_ddrphy_apb_wr(0x41184, 0xc000); +dwc_ddrphy_apb_wr(0x41185, 0x3); +dwc_ddrphy_apb_wr(0x41186, 0x3c0); +dwc_ddrphy_apb_wr(0x41187, 0x20); +dwc_ddrphy_apb_wr(0x41188, 0xc000); +dwc_ddrphy_apb_wr(0x41189, 0x3); +dwc_ddrphy_apb_wr(0x4118a, 0x3c0); +dwc_ddrphy_apb_wr(0x4118b, 0x2c1); +dwc_ddrphy_apb_wr(0x4118c, 0xc000); +dwc_ddrphy_apb_wr(0x4118d, 0x3); +dwc_ddrphy_apb_wr(0x4118e, 0x3c0); +dwc_ddrphy_apb_wr(0x4118f, 0x1001); +dwc_ddrphy_apb_wr(0x41190, 0x85f5); +dwc_ddrphy_apb_wr(0x41191, 0xf563); +dwc_ddrphy_apb_wr(0x41192, 0x3c5); +dwc_ddrphy_apb_wr(0x41193, 0x820); +dwc_ddrphy_apb_wr(0x41194, 0xc000); +dwc_ddrphy_apb_wr(0x41195, 0x3); +dwc_ddrphy_apb_wr(0x41196, 0x3c0); +dwc_ddrphy_apb_wr(0x41197, 0x20); +dwc_ddrphy_apb_wr(0x41198, 0xc000); +dwc_ddrphy_apb_wr(0x41199, 0x3); +dwc_ddrphy_apb_wr(0x4119a, 0x3c0); +dwc_ddrphy_apb_wr(0x4119b, 0x2c1); +dwc_ddrphy_apb_wr(0x4119c, 0xc000); +dwc_ddrphy_apb_wr(0x4119d, 0x3); +dwc_ddrphy_apb_wr(0x4119e, 0x3c0); +dwc_ddrphy_apb_wr(0x4119f, 0x1001); +dwc_ddrphy_apb_wr(0x411a0, 0x45d5); +dwc_ddrphy_apb_wr(0x411a1, 0xd563); +dwc_ddrphy_apb_wr(0x411a2, 0x3c5); +dwc_ddrphy_apb_wr(0x411a3, 0x421); +dwc_ddrphy_apb_wr(0x411a4, 0xc000); +dwc_ddrphy_apb_wr(0x411a5, 0x3); +dwc_ddrphy_apb_wr(0x411a6, 0x3c0); +dwc_ddrphy_apb_wr(0x411a7, 0x21); +dwc_ddrphy_apb_wr(0x411a8, 0xc000); +dwc_ddrphy_apb_wr(0x411a9, 0x3); +dwc_ddrphy_apb_wr(0x411aa, 0x3c0); +dwc_ddrphy_apb_wr(0x411ab, 0x2c1); +dwc_ddrphy_apb_wr(0x411ac, 0xc000); +dwc_ddrphy_apb_wr(0x411ad, 0x3); +dwc_ddrphy_apb_wr(0x411ae, 0x3c0); +dwc_ddrphy_apb_wr(0x411af, 0x1001); +dwc_ddrphy_apb_wr(0x411b0, 0x45f5); +dwc_ddrphy_apb_wr(0x411b1, 0xf563); +dwc_ddrphy_apb_wr(0x411b2, 0x3c5); +dwc_ddrphy_apb_wr(0x411b3, 0x821); +dwc_ddrphy_apb_wr(0x411b4, 0xc000); +dwc_ddrphy_apb_wr(0x411b5, 0x3); +dwc_ddrphy_apb_wr(0x411b6, 0x3c0); +dwc_ddrphy_apb_wr(0x411b7, 0x21); +dwc_ddrphy_apb_wr(0x411b8, 0xc000); +dwc_ddrphy_apb_wr(0x411b9, 0x3); +dwc_ddrphy_apb_wr(0x411ba, 0x3c0); +dwc_ddrphy_apb_wr(0x411bb, 0x2c1); +dwc_ddrphy_apb_wr(0x411bc, 0xc000); +dwc_ddrphy_apb_wr(0x411bd, 0x3); +dwc_ddrphy_apb_wr(0x411be, 0x3c0); +dwc_ddrphy_apb_wr(0x411bf, 0x1001); +dwc_ddrphy_apb_wr(0x411c0, 0xc5d5); +dwc_ddrphy_apb_wr(0x411c1, 0xd562); +dwc_ddrphy_apb_wr(0x411c2, 0x3c5); +dwc_ddrphy_apb_wr(0x411c3, 0x422); +dwc_ddrphy_apb_wr(0x411c4, 0xc000); +dwc_ddrphy_apb_wr(0x411c5, 0x3); +dwc_ddrphy_apb_wr(0x411c6, 0x3c0); +dwc_ddrphy_apb_wr(0x411c7, 0x22); +dwc_ddrphy_apb_wr(0x411c8, 0xc000); +dwc_ddrphy_apb_wr(0x411c9, 0x3); +dwc_ddrphy_apb_wr(0x411ca, 0x3c0); +dwc_ddrphy_apb_wr(0x411cb, 0x2c1); +dwc_ddrphy_apb_wr(0x411cc, 0xc000); +dwc_ddrphy_apb_wr(0x411cd, 0x3); +dwc_ddrphy_apb_wr(0x411ce, 0x3c0); +dwc_ddrphy_apb_wr(0x411cf, 0x1001); +dwc_ddrphy_apb_wr(0x411d0, 0xc5f5); +dwc_ddrphy_apb_wr(0x411d1, 0xf562); +dwc_ddrphy_apb_wr(0x411d2, 0x3c5); +dwc_ddrphy_apb_wr(0x411d3, 0x822); +dwc_ddrphy_apb_wr(0x411d4, 0xc000); +dwc_ddrphy_apb_wr(0x411d5, 0x3); +dwc_ddrphy_apb_wr(0x411d6, 0x3c0); +dwc_ddrphy_apb_wr(0x411d7, 0x22); +dwc_ddrphy_apb_wr(0x411d8, 0xc000); +dwc_ddrphy_apb_wr(0x411d9, 0x3); +dwc_ddrphy_apb_wr(0x411da, 0x3c0); +dwc_ddrphy_apb_wr(0x411db, 0x2c1); +dwc_ddrphy_apb_wr(0x411dc, 0xc000); +dwc_ddrphy_apb_wr(0x411dd, 0x3); +dwc_ddrphy_apb_wr(0x411de, 0x3c0); +dwc_ddrphy_apb_wr(0x411df, 0x1001); +dwc_ddrphy_apb_wr(0x411e0, 0xc5d5); +dwc_ddrphy_apb_wr(0x411e1, 0xd561); +dwc_ddrphy_apb_wr(0x411e2, 0x3c5); +dwc_ddrphy_apb_wr(0x411e3, 0x423); +dwc_ddrphy_apb_wr(0x411e4, 0xc000); +dwc_ddrphy_apb_wr(0x411e5, 0x3); +dwc_ddrphy_apb_wr(0x411e6, 0x3c0); +dwc_ddrphy_apb_wr(0x411e7, 0x23); +dwc_ddrphy_apb_wr(0x411e8, 0xc000); +dwc_ddrphy_apb_wr(0x411e9, 0x3); +dwc_ddrphy_apb_wr(0x411ea, 0x3c0); +dwc_ddrphy_apb_wr(0x411eb, 0x2c1); +dwc_ddrphy_apb_wr(0x411ec, 0xc000); +dwc_ddrphy_apb_wr(0x411ed, 0x3); +dwc_ddrphy_apb_wr(0x411ee, 0x3c0); +dwc_ddrphy_apb_wr(0x411ef, 0x1001); +dwc_ddrphy_apb_wr(0x411f0, 0xc5f5); +dwc_ddrphy_apb_wr(0x411f1, 0xf561); +dwc_ddrphy_apb_wr(0x411f2, 0x3c5); +dwc_ddrphy_apb_wr(0x411f3, 0x823); +dwc_ddrphy_apb_wr(0x411f4, 0xc000); +dwc_ddrphy_apb_wr(0x411f5, 0x3); +dwc_ddrphy_apb_wr(0x411f6, 0x3c0); +dwc_ddrphy_apb_wr(0x411f7, 0x23); +dwc_ddrphy_apb_wr(0x411f8, 0xc000); +dwc_ddrphy_apb_wr(0x411f9, 0x3); +dwc_ddrphy_apb_wr(0x411fa, 0x3c0); +dwc_ddrphy_apb_wr(0x411fb, 0x2c1); +dwc_ddrphy_apb_wr(0x411fc, 0xc000); +dwc_ddrphy_apb_wr(0x411fd, 0x3); +dwc_ddrphy_apb_wr(0x411fe, 0x3c0); +dwc_ddrphy_apb_wr(0x411ff, 0x1d01); +//// [phyinit_LoadPIECodeSections] Matched NO enable_bits = 2, type = 0 +dwc_ddrphy_apb_wr(0x41200, 0x213); +dwc_ddrphy_apb_wr(0x41201, 0x1300); +dwc_ddrphy_apb_wr(0x41202, 0x3c2); +dwc_ddrphy_apb_wr(0x41203, 0x21); +dwc_ddrphy_apb_wr(0x41204, 0xc000); +dwc_ddrphy_apb_wr(0x41205, 0x3); +dwc_ddrphy_apb_wr(0x41206, 0x3c0); +dwc_ddrphy_apb_wr(0x41207, 0x20); +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 20, type = 0 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 80, type = 0 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 40, type = 0 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 100, type = 0 +dwc_ddrphy_apb_wr(0x41208, 0xc000); +dwc_ddrphy_apb_wr(0x41209, 0x3); +dwc_ddrphy_apb_wr(0x4120a, 0x3c0); +dwc_ddrphy_apb_wr(0x4120b, 0x2e1); +dwc_ddrphy_apb_wr(0x4120c, 0xc000); +dwc_ddrphy_apb_wr(0x4120d, 0x3); +dwc_ddrphy_apb_wr(0x4120e, 0x3c0); +dwc_ddrphy_apb_wr(0x4120f, 0xef20); +dwc_ddrphy_apb_wr(0x41210, 0xc000); +dwc_ddrphy_apb_wr(0x41211, 0x3); +dwc_ddrphy_apb_wr(0x41212, 0x3c0); +dwc_ddrphy_apb_wr(0x41213, 0x2e1); +dwc_ddrphy_apb_wr(0x41214, 0xc000); +dwc_ddrphy_apb_wr(0x41215, 0x3); +dwc_ddrphy_apb_wr(0x41216, 0x3c0); +dwc_ddrphy_apb_wr(0x41217, 0x5920); +dwc_ddrphy_apb_wr(0x41218, 0x217); +dwc_ddrphy_apb_wr(0x41219, 0x1700); +dwc_ddrphy_apb_wr(0x4121a, 0x3c2); +dwc_ddrphy_apb_wr(0x4121b, 0x21); +dwc_ddrphy_apb_wr(0x4121c, 0xc000); +dwc_ddrphy_apb_wr(0x4121d, 0x3); +dwc_ddrphy_apb_wr(0x4121e, 0x3c0); +dwc_ddrphy_apb_wr(0x4121f, 0x20); +dwc_ddrphy_apb_wr(0x41220, 0xc000); +dwc_ddrphy_apb_wr(0x41221, 0x3); +dwc_ddrphy_apb_wr(0x41222, 0x3c0); +dwc_ddrphy_apb_wr(0x41223, 0x2e1); +dwc_ddrphy_apb_wr(0x41224, 0xc000); +dwc_ddrphy_apb_wr(0x41225, 0x3); +dwc_ddrphy_apb_wr(0x41226, 0x3c0); +dwc_ddrphy_apb_wr(0x41227, 0x420); +//// [phyinit_LoadPIECodeSections] Moving start address from 41228 to 42000 +dwc_ddrphy_apb_wr(0x42000, 0x3fff); +dwc_ddrphy_apb_wr(0x42001, 0xff00); +dwc_ddrphy_apb_wr(0x42002, 0x3f); +dwc_ddrphy_apb_wr(0x42003, 0x2c1); +dwc_ddrphy_apb_wr(0x42004, 0x3fff); +dwc_ddrphy_apb_wr(0x42005, 0xff00); +dwc_ddrphy_apb_wr(0x42006, 0x3f); +dwc_ddrphy_apb_wr(0x42007, 0xa01); +dwc_ddrphy_apb_wr(0x42008, 0x3fff); +dwc_ddrphy_apb_wr(0x42009, 0xff00); +dwc_ddrphy_apb_wr(0x4200a, 0x3f); +dwc_ddrphy_apb_wr(0x4200b, 0x1); +dwc_ddrphy_apb_wr(0x4200c, 0xffff); +dwc_ddrphy_apb_wr(0x4200d, 0xff03); +dwc_ddrphy_apb_wr(0x4200e, 0x3ff); +dwc_ddrphy_apb_wr(0x4200f, 0x0); +dwc_ddrphy_apb_wr(0x42010, 0xffff); +dwc_ddrphy_apb_wr(0x42011, 0xff03); +dwc_ddrphy_apb_wr(0x42012, 0x3ff); +dwc_ddrphy_apb_wr(0x42013, 0x1c1); +dwc_ddrphy_apb_wr(0x42014, 0xffff); +dwc_ddrphy_apb_wr(0x42015, 0xff03); +dwc_ddrphy_apb_wr(0x42016, 0x3ff); +dwc_ddrphy_apb_wr(0x42017, 0x1); +dwc_ddrphy_apb_wr(0x42018, 0xffff); +dwc_ddrphy_apb_wr(0x42019, 0xff03); +dwc_ddrphy_apb_wr(0x4201a, 0x3ff); +dwc_ddrphy_apb_wr(0x4201b, 0x2c1); +dwc_ddrphy_apb_wr(0x4201c, 0xffff); +dwc_ddrphy_apb_wr(0x4201d, 0xff03); +dwc_ddrphy_apb_wr(0x4201e, 0x3ff); +dwc_ddrphy_apb_wr(0x4201f, 0x101); +dwc_ddrphy_apb_wr(0x42020, 0x3fff); +dwc_ddrphy_apb_wr(0x42021, 0xff00); +dwc_ddrphy_apb_wr(0x42022, 0x3f); +dwc_ddrphy_apb_wr(0x42023, 0x1); +dwc_ddrphy_apb_wr(0x42024, 0x3fff); +dwc_ddrphy_apb_wr(0x42025, 0xff00); +dwc_ddrphy_apb_wr(0x42026, 0x3ff); +dwc_ddrphy_apb_wr(0x42027, 0x1); +dwc_ddrphy_apb_wr(0x42028, 0xffff); +dwc_ddrphy_apb_wr(0x42029, 0xff03); +dwc_ddrphy_apb_wr(0x4202a, 0x3ff); +dwc_ddrphy_apb_wr(0x4202b, 0x2c1); +dwc_ddrphy_apb_wr(0x4202c, 0xffff); +dwc_ddrphy_apb_wr(0x4202d, 0xff03); +dwc_ddrphy_apb_wr(0x4202e, 0x3ff); +dwc_ddrphy_apb_wr(0x4202f, 0xf901); +dwc_ddrphy_apb_wr(0x42030, 0xffff); +dwc_ddrphy_apb_wr(0x42031, 0xff03); +dwc_ddrphy_apb_wr(0x42032, 0x3ff); +dwc_ddrphy_apb_wr(0x42033, 0x2c1); +dwc_ddrphy_apb_wr(0x42034, 0xffff); +dwc_ddrphy_apb_wr(0x42035, 0xff03); +dwc_ddrphy_apb_wr(0x42036, 0x3ff); +dwc_ddrphy_apb_wr(0x42037, 0x5901); +dwc_ddrphy_apb_wr(0x42038, 0x5a5); +dwc_ddrphy_apb_wr(0x42039, 0x4000); +dwc_ddrphy_apb_wr(0x4203a, 0x3c0); +dwc_ddrphy_apb_wr(0x4203b, 0x1); +dwc_ddrphy_apb_wr(0x4203c, 0xc000); +dwc_ddrphy_apb_wr(0x4203d, 0x3); +dwc_ddrphy_apb_wr(0x4203e, 0x3c0); +dwc_ddrphy_apb_wr(0x4203f, 0x0); +dwc_ddrphy_apb_wr(0x42040, 0xc000); +dwc_ddrphy_apb_wr(0x42041, 0x3); +dwc_ddrphy_apb_wr(0x42042, 0x3c0); +dwc_ddrphy_apb_wr(0x42043, 0x2c1); +dwc_ddrphy_apb_wr(0x42044, 0xc000); +dwc_ddrphy_apb_wr(0x42045, 0x3); +dwc_ddrphy_apb_wr(0x42046, 0x3c0); +dwc_ddrphy_apb_wr(0x42047, 0xa01); +dwc_ddrphy_apb_wr(0x42048, 0xef); +dwc_ddrphy_apb_wr(0x42049, 0xef00); +dwc_ddrphy_apb_wr(0x4204a, 0x3c0); +dwc_ddrphy_apb_wr(0x4204b, 0x1); +dwc_ddrphy_apb_wr(0x4204c, 0xc000); +dwc_ddrphy_apb_wr(0x4204d, 0x3); +dwc_ddrphy_apb_wr(0x4204e, 0x3c0); +dwc_ddrphy_apb_wr(0x4204f, 0x0); +dwc_ddrphy_apb_wr(0x42050, 0xc000); +dwc_ddrphy_apb_wr(0x42051, 0x3); +dwc_ddrphy_apb_wr(0x42052, 0x3c0); +dwc_ddrphy_apb_wr(0x42053, 0x2c1); +dwc_ddrphy_apb_wr(0x42054, 0xc000); +dwc_ddrphy_apb_wr(0x42055, 0x3); +dwc_ddrphy_apb_wr(0x42056, 0x3c0); +dwc_ddrphy_apb_wr(0x42057, 0xff01); +dwc_ddrphy_apb_wr(0x42058, 0xc000); +dwc_ddrphy_apb_wr(0x42059, 0x3); +dwc_ddrphy_apb_wr(0x4205a, 0x3c0); +dwc_ddrphy_apb_wr(0x4205b, 0x2c1); +dwc_ddrphy_apb_wr(0x4205c, 0xc000); +dwc_ddrphy_apb_wr(0x4205d, 0x3); +dwc_ddrphy_apb_wr(0x4205e, 0x3c0); +dwc_ddrphy_apb_wr(0x4205f, 0xff01); +dwc_ddrphy_apb_wr(0x42060, 0xc000); +dwc_ddrphy_apb_wr(0x42061, 0x3); +dwc_ddrphy_apb_wr(0x42062, 0x3c0); +dwc_ddrphy_apb_wr(0x42063, 0x2c1); +dwc_ddrphy_apb_wr(0x42064, 0xc000); +dwc_ddrphy_apb_wr(0x42065, 0x3); +dwc_ddrphy_apb_wr(0x42066, 0x3c0); +dwc_ddrphy_apb_wr(0x42067, 0xa01); +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 1, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 2, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 4, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 8, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 10, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 20, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 40, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 80, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 100, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 200, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 400, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 800, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 1000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 2000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 4000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 8000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 10000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 20000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 40000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 80000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 100000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 200000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 400000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 800000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 1000000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 2000000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 4000000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 8000000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 10000000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 20000000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 40000000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 80000000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 10, type = 0 +//// [phyinit_LoadPIECodeSections] Matched NO enable_bits = 4, type = 0 +dwc_ddrphy_apb_wr(0x42068, 0x85d5); +dwc_ddrphy_apb_wr(0x42069, 0x63); +dwc_ddrphy_apb_wr(0x4206a, 0x3c0); +dwc_ddrphy_apb_wr(0x4206b, 0x400); +dwc_ddrphy_apb_wr(0x4206c, 0xc000); +dwc_ddrphy_apb_wr(0x4206d, 0x3); +dwc_ddrphy_apb_wr(0x4206e, 0x3c0); +dwc_ddrphy_apb_wr(0x4206f, 0x0); +dwc_ddrphy_apb_wr(0x42070, 0xc000); +dwc_ddrphy_apb_wr(0x42071, 0x3); +dwc_ddrphy_apb_wr(0x42072, 0x3c0); +dwc_ddrphy_apb_wr(0x42073, 0x2c1); +dwc_ddrphy_apb_wr(0x42074, 0xc000); +dwc_ddrphy_apb_wr(0x42075, 0x3); +dwc_ddrphy_apb_wr(0x42076, 0x3c0); +dwc_ddrphy_apb_wr(0x42077, 0x1001); +dwc_ddrphy_apb_wr(0x42078, 0x85f5); +dwc_ddrphy_apb_wr(0x42079, 0x63); +dwc_ddrphy_apb_wr(0x4207a, 0x3c0); +dwc_ddrphy_apb_wr(0x4207b, 0x800); +dwc_ddrphy_apb_wr(0x4207c, 0xc000); +dwc_ddrphy_apb_wr(0x4207d, 0x3); +dwc_ddrphy_apb_wr(0x4207e, 0x3c0); +dwc_ddrphy_apb_wr(0x4207f, 0x0); +dwc_ddrphy_apb_wr(0x42080, 0xc000); +dwc_ddrphy_apb_wr(0x42081, 0x3); +dwc_ddrphy_apb_wr(0x42082, 0x3c0); +dwc_ddrphy_apb_wr(0x42083, 0x2c1); +dwc_ddrphy_apb_wr(0x42084, 0xc000); +dwc_ddrphy_apb_wr(0x42085, 0x3); +dwc_ddrphy_apb_wr(0x42086, 0x3c0); +dwc_ddrphy_apb_wr(0x42087, 0x1001); +dwc_ddrphy_apb_wr(0x42088, 0x45d5); +dwc_ddrphy_apb_wr(0x42089, 0x63); +dwc_ddrphy_apb_wr(0x4208a, 0x3c0); +dwc_ddrphy_apb_wr(0x4208b, 0x401); +dwc_ddrphy_apb_wr(0x4208c, 0xc000); +dwc_ddrphy_apb_wr(0x4208d, 0x3); +dwc_ddrphy_apb_wr(0x4208e, 0x3c0); +dwc_ddrphy_apb_wr(0x4208f, 0x1); +dwc_ddrphy_apb_wr(0x42090, 0xc000); +dwc_ddrphy_apb_wr(0x42091, 0x3); +dwc_ddrphy_apb_wr(0x42092, 0x3c0); +dwc_ddrphy_apb_wr(0x42093, 0x2c1); +dwc_ddrphy_apb_wr(0x42094, 0xc000); +dwc_ddrphy_apb_wr(0x42095, 0x3); +dwc_ddrphy_apb_wr(0x42096, 0x3c0); +dwc_ddrphy_apb_wr(0x42097, 0x1001); +dwc_ddrphy_apb_wr(0x42098, 0x45f5); +dwc_ddrphy_apb_wr(0x42099, 0x63); +dwc_ddrphy_apb_wr(0x4209a, 0x3c0); +dwc_ddrphy_apb_wr(0x4209b, 0x801); +dwc_ddrphy_apb_wr(0x4209c, 0xc000); +dwc_ddrphy_apb_wr(0x4209d, 0x3); +dwc_ddrphy_apb_wr(0x4209e, 0x3c0); +dwc_ddrphy_apb_wr(0x4209f, 0x1); +dwc_ddrphy_apb_wr(0x420a0, 0xc000); +dwc_ddrphy_apb_wr(0x420a1, 0x3); +dwc_ddrphy_apb_wr(0x420a2, 0x3c0); +dwc_ddrphy_apb_wr(0x420a3, 0x2c1); +dwc_ddrphy_apb_wr(0x420a4, 0xc000); +dwc_ddrphy_apb_wr(0x420a5, 0x3); +dwc_ddrphy_apb_wr(0x420a6, 0x3c0); +dwc_ddrphy_apb_wr(0x420a7, 0x1001); +dwc_ddrphy_apb_wr(0x420a8, 0xc5d5); +dwc_ddrphy_apb_wr(0x420a9, 0x62); +dwc_ddrphy_apb_wr(0x420aa, 0x3c0); +dwc_ddrphy_apb_wr(0x420ab, 0x402); +dwc_ddrphy_apb_wr(0x420ac, 0xc000); +dwc_ddrphy_apb_wr(0x420ad, 0x3); +dwc_ddrphy_apb_wr(0x420ae, 0x3c0); +dwc_ddrphy_apb_wr(0x420af, 0x2); +dwc_ddrphy_apb_wr(0x420b0, 0xc000); +dwc_ddrphy_apb_wr(0x420b1, 0x3); +dwc_ddrphy_apb_wr(0x420b2, 0x3c0); +dwc_ddrphy_apb_wr(0x420b3, 0x2c1); +dwc_ddrphy_apb_wr(0x420b4, 0xc000); +dwc_ddrphy_apb_wr(0x420b5, 0x3); +dwc_ddrphy_apb_wr(0x420b6, 0x3c0); +dwc_ddrphy_apb_wr(0x420b7, 0x1001); +dwc_ddrphy_apb_wr(0x420b8, 0xc5f5); +dwc_ddrphy_apb_wr(0x420b9, 0x62); +dwc_ddrphy_apb_wr(0x420ba, 0x3c0); +dwc_ddrphy_apb_wr(0x420bb, 0x802); +dwc_ddrphy_apb_wr(0x420bc, 0xc000); +dwc_ddrphy_apb_wr(0x420bd, 0x3); +dwc_ddrphy_apb_wr(0x420be, 0x3c0); +dwc_ddrphy_apb_wr(0x420bf, 0x2); +dwc_ddrphy_apb_wr(0x420c0, 0xc000); +dwc_ddrphy_apb_wr(0x420c1, 0x3); +dwc_ddrphy_apb_wr(0x420c2, 0x3c0); +dwc_ddrphy_apb_wr(0x420c3, 0x2c1); +dwc_ddrphy_apb_wr(0x420c4, 0xc000); +dwc_ddrphy_apb_wr(0x420c5, 0x3); +dwc_ddrphy_apb_wr(0x420c6, 0x3c0); +dwc_ddrphy_apb_wr(0x420c7, 0x1001); +dwc_ddrphy_apb_wr(0x420c8, 0xc5d5); +dwc_ddrphy_apb_wr(0x420c9, 0x61); +dwc_ddrphy_apb_wr(0x420ca, 0x3c0); +dwc_ddrphy_apb_wr(0x420cb, 0x403); +dwc_ddrphy_apb_wr(0x420cc, 0xc000); +dwc_ddrphy_apb_wr(0x420cd, 0x3); +dwc_ddrphy_apb_wr(0x420ce, 0x3c0); +dwc_ddrphy_apb_wr(0x420cf, 0x3); +dwc_ddrphy_apb_wr(0x420d0, 0xc000); +dwc_ddrphy_apb_wr(0x420d1, 0x3); +dwc_ddrphy_apb_wr(0x420d2, 0x3c0); +dwc_ddrphy_apb_wr(0x420d3, 0x2c1); +dwc_ddrphy_apb_wr(0x420d4, 0xc000); +dwc_ddrphy_apb_wr(0x420d5, 0x3); +dwc_ddrphy_apb_wr(0x420d6, 0x3c0); +dwc_ddrphy_apb_wr(0x420d7, 0x1001); +dwc_ddrphy_apb_wr(0x420d8, 0xc5f5); +dwc_ddrphy_apb_wr(0x420d9, 0x61); +dwc_ddrphy_apb_wr(0x420da, 0x3c0); +dwc_ddrphy_apb_wr(0x420db, 0x803); +dwc_ddrphy_apb_wr(0x420dc, 0xc000); +dwc_ddrphy_apb_wr(0x420dd, 0x3); +dwc_ddrphy_apb_wr(0x420de, 0x3c0); +dwc_ddrphy_apb_wr(0x420df, 0x3); +dwc_ddrphy_apb_wr(0x420e0, 0xc000); +dwc_ddrphy_apb_wr(0x420e1, 0x3); +dwc_ddrphy_apb_wr(0x420e2, 0x3c0); +dwc_ddrphy_apb_wr(0x420e3, 0x2c1); +dwc_ddrphy_apb_wr(0x420e4, 0xc000); +dwc_ddrphy_apb_wr(0x420e5, 0x3); +dwc_ddrphy_apb_wr(0x420e6, 0x3c0); +dwc_ddrphy_apb_wr(0x420e7, 0x1d01); +//// [phyinit_LoadPIECodeSections] Matched NO enable_bits = 2, type = 0 +dwc_ddrphy_apb_wr(0x420e8, 0x213); +dwc_ddrphy_apb_wr(0x420e9, 0x0); +dwc_ddrphy_apb_wr(0x420ea, 0x3c0); +dwc_ddrphy_apb_wr(0x420eb, 0x1); +dwc_ddrphy_apb_wr(0x420ec, 0xc000); +dwc_ddrphy_apb_wr(0x420ed, 0x3); +dwc_ddrphy_apb_wr(0x420ee, 0x3c0); +dwc_ddrphy_apb_wr(0x420ef, 0x0); +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 20, type = 0 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 80, type = 0 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 40, type = 0 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 100, type = 0 +dwc_ddrphy_apb_wr(0x420f0, 0xc000); +dwc_ddrphy_apb_wr(0x420f1, 0x3); +dwc_ddrphy_apb_wr(0x420f2, 0x3c0); +dwc_ddrphy_apb_wr(0x420f3, 0x2c1); +dwc_ddrphy_apb_wr(0x420f4, 0xc000); +dwc_ddrphy_apb_wr(0x420f5, 0x3); +dwc_ddrphy_apb_wr(0x420f6, 0x3c0); +dwc_ddrphy_apb_wr(0x420f7, 0xef00); +dwc_ddrphy_apb_wr(0x420f8, 0xc000); +dwc_ddrphy_apb_wr(0x420f9, 0x3); +dwc_ddrphy_apb_wr(0x420fa, 0x3c0); +dwc_ddrphy_apb_wr(0x420fb, 0x2c1); +dwc_ddrphy_apb_wr(0x420fc, 0xc000); +dwc_ddrphy_apb_wr(0x420fd, 0x3); +dwc_ddrphy_apb_wr(0x420fe, 0x3c0); +dwc_ddrphy_apb_wr(0x420ff, 0x5900); +dwc_ddrphy_apb_wr(0x42100, 0x217); +dwc_ddrphy_apb_wr(0x42101, 0x1700); +dwc_ddrphy_apb_wr(0x42102, 0x3c2); +dwc_ddrphy_apb_wr(0x42103, 0x1); +dwc_ddrphy_apb_wr(0x42104, 0xc000); +dwc_ddrphy_apb_wr(0x42105, 0x3); +dwc_ddrphy_apb_wr(0x42106, 0x3c0); +dwc_ddrphy_apb_wr(0x42107, 0x0); +dwc_ddrphy_apb_wr(0x42108, 0xc000); +dwc_ddrphy_apb_wr(0x42109, 0x3); +dwc_ddrphy_apb_wr(0x4210a, 0x3c0); +dwc_ddrphy_apb_wr(0x4210b, 0x2c1); +dwc_ddrphy_apb_wr(0x4210c, 0xc000); +dwc_ddrphy_apb_wr(0x4210d, 0x3); +dwc_ddrphy_apb_wr(0x4210e, 0x3c0); +dwc_ddrphy_apb_wr(0x4210f, 0x400); +dwc_ddrphy_apb_wr(0x42110, 0x3fff); +dwc_ddrphy_apb_wr(0x42111, 0xff00); +dwc_ddrphy_apb_wr(0x42112, 0x3f); +dwc_ddrphy_apb_wr(0x42113, 0x2e1); +dwc_ddrphy_apb_wr(0x42114, 0x3fff); +dwc_ddrphy_apb_wr(0x42115, 0xff00); +dwc_ddrphy_apb_wr(0x42116, 0x3f); +dwc_ddrphy_apb_wr(0x42117, 0xa21); +dwc_ddrphy_apb_wr(0x42118, 0x3fff); +dwc_ddrphy_apb_wr(0x42119, 0xff00); +dwc_ddrphy_apb_wr(0x4211a, 0x3f); +dwc_ddrphy_apb_wr(0x4211b, 0x21); +dwc_ddrphy_apb_wr(0x4211c, 0xffff); +dwc_ddrphy_apb_wr(0x4211d, 0xff03); +dwc_ddrphy_apb_wr(0x4211e, 0x3ff); +dwc_ddrphy_apb_wr(0x4211f, 0x20); +dwc_ddrphy_apb_wr(0x42120, 0xffff); +dwc_ddrphy_apb_wr(0x42121, 0xff03); +dwc_ddrphy_apb_wr(0x42122, 0x3ff); +dwc_ddrphy_apb_wr(0x42123, 0x1e1); +dwc_ddrphy_apb_wr(0x42124, 0xffff); +dwc_ddrphy_apb_wr(0x42125, 0xff03); +dwc_ddrphy_apb_wr(0x42126, 0x3ff); +dwc_ddrphy_apb_wr(0x42127, 0x21); +dwc_ddrphy_apb_wr(0x42128, 0xffff); +dwc_ddrphy_apb_wr(0x42129, 0xff03); +dwc_ddrphy_apb_wr(0x4212a, 0x3ff); +dwc_ddrphy_apb_wr(0x4212b, 0x2e1); +dwc_ddrphy_apb_wr(0x4212c, 0xffff); +dwc_ddrphy_apb_wr(0x4212d, 0xff03); +dwc_ddrphy_apb_wr(0x4212e, 0x3ff); +dwc_ddrphy_apb_wr(0x4212f, 0x121); +dwc_ddrphy_apb_wr(0x42130, 0x3fff); +dwc_ddrphy_apb_wr(0x42131, 0xff00); +dwc_ddrphy_apb_wr(0x42132, 0x3ff); +dwc_ddrphy_apb_wr(0x42133, 0x21); +dwc_ddrphy_apb_wr(0x42134, 0x3fff); +dwc_ddrphy_apb_wr(0x42135, 0xff00); +dwc_ddrphy_apb_wr(0x42136, 0x3ff); +dwc_ddrphy_apb_wr(0x42137, 0x21); +dwc_ddrphy_apb_wr(0x42138, 0x3fff); +dwc_ddrphy_apb_wr(0x42139, 0xff00); +dwc_ddrphy_apb_wr(0x4213a, 0x3ff); +dwc_ddrphy_apb_wr(0x4213b, 0x21); +dwc_ddrphy_apb_wr(0x4213c, 0xffff); +dwc_ddrphy_apb_wr(0x4213d, 0xff03); +dwc_ddrphy_apb_wr(0x4213e, 0x3ff); +dwc_ddrphy_apb_wr(0x4213f, 0x21); +dwc_ddrphy_apb_wr(0x42140, 0xffff); +dwc_ddrphy_apb_wr(0x42141, 0xff03); +dwc_ddrphy_apb_wr(0x42142, 0x3ff); +dwc_ddrphy_apb_wr(0x42143, 0x2e1); +dwc_ddrphy_apb_wr(0x42144, 0xffff); +dwc_ddrphy_apb_wr(0x42145, 0xff03); +dwc_ddrphy_apb_wr(0x42146, 0x3ff); +dwc_ddrphy_apb_wr(0x42147, 0xf921); +dwc_ddrphy_apb_wr(0x42148, 0xffff); +dwc_ddrphy_apb_wr(0x42149, 0xff03); +dwc_ddrphy_apb_wr(0x4214a, 0x3ff); +dwc_ddrphy_apb_wr(0x4214b, 0x2e1); +dwc_ddrphy_apb_wr(0x4214c, 0xffff); +dwc_ddrphy_apb_wr(0x4214d, 0xff03); +dwc_ddrphy_apb_wr(0x4214e, 0x3ff); +dwc_ddrphy_apb_wr(0x4214f, 0x5921); +dwc_ddrphy_apb_wr(0x42150, 0x5a5); +dwc_ddrphy_apb_wr(0x42151, 0xa500); +dwc_ddrphy_apb_wr(0x42152, 0x3c5); +dwc_ddrphy_apb_wr(0x42153, 0x21); +dwc_ddrphy_apb_wr(0x42154, 0xc040); +dwc_ddrphy_apb_wr(0x42155, 0x4003); +dwc_ddrphy_apb_wr(0x42156, 0x3c0); +dwc_ddrphy_apb_wr(0x42157, 0x20); +dwc_ddrphy_apb_wr(0x42158, 0xc000); +dwc_ddrphy_apb_wr(0x42159, 0x3); +dwc_ddrphy_apb_wr(0x4215a, 0x3c0); +dwc_ddrphy_apb_wr(0x4215b, 0x2e1); +dwc_ddrphy_apb_wr(0x4215c, 0xc000); +dwc_ddrphy_apb_wr(0x4215d, 0x3); +dwc_ddrphy_apb_wr(0x4215e, 0x3c0); +dwc_ddrphy_apb_wr(0x4215f, 0xa21); +dwc_ddrphy_apb_wr(0x42160, 0xef); +dwc_ddrphy_apb_wr(0x42161, 0xef00); +dwc_ddrphy_apb_wr(0x42162, 0x3c0); +dwc_ddrphy_apb_wr(0x42163, 0x21); +dwc_ddrphy_apb_wr(0x42164, 0xc000); +dwc_ddrphy_apb_wr(0x42165, 0x3); +dwc_ddrphy_apb_wr(0x42166, 0x3c0); +dwc_ddrphy_apb_wr(0x42167, 0x20); +dwc_ddrphy_apb_wr(0x42168, 0xc000); +dwc_ddrphy_apb_wr(0x42169, 0x3); +dwc_ddrphy_apb_wr(0x4216a, 0x3c0); +dwc_ddrphy_apb_wr(0x4216b, 0x2e1); +dwc_ddrphy_apb_wr(0x4216c, 0xc000); +dwc_ddrphy_apb_wr(0x4216d, 0x3); +dwc_ddrphy_apb_wr(0x4216e, 0x3c0); +dwc_ddrphy_apb_wr(0x4216f, 0xff21); +dwc_ddrphy_apb_wr(0x42170, 0xc000); +dwc_ddrphy_apb_wr(0x42171, 0x3); +dwc_ddrphy_apb_wr(0x42172, 0x3c0); +dwc_ddrphy_apb_wr(0x42173, 0x2e1); +dwc_ddrphy_apb_wr(0x42174, 0xc000); +dwc_ddrphy_apb_wr(0x42175, 0x3); +dwc_ddrphy_apb_wr(0x42176, 0x3c0); +dwc_ddrphy_apb_wr(0x42177, 0xff21); +dwc_ddrphy_apb_wr(0x42178, 0xc000); +dwc_ddrphy_apb_wr(0x42179, 0x3); +dwc_ddrphy_apb_wr(0x4217a, 0x3c0); +dwc_ddrphy_apb_wr(0x4217b, 0x2e1); +dwc_ddrphy_apb_wr(0x4217c, 0xc000); +dwc_ddrphy_apb_wr(0x4217d, 0x3); +dwc_ddrphy_apb_wr(0x4217e, 0x3c0); +dwc_ddrphy_apb_wr(0x4217f, 0xa21); +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 1, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 2, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 4, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 8, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 10, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 20, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 40, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 80, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 100, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 200, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 400, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 800, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 1000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 2000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 4000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 8000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 10000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 20000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 40000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 80000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 100000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 200000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 400000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 800000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 1000000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 2000000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 4000000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 8000000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 10000000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 20000000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 40000000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 80000000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 10, type = 0 +//// [phyinit_LoadPIECodeSections] Matched NO enable_bits = 4, type = 0 +dwc_ddrphy_apb_wr(0x42180, 0x85d5); +dwc_ddrphy_apb_wr(0x42181, 0xd563); +dwc_ddrphy_apb_wr(0x42182, 0x3c5); +dwc_ddrphy_apb_wr(0x42183, 0x420); +dwc_ddrphy_apb_wr(0x42184, 0xc000); +dwc_ddrphy_apb_wr(0x42185, 0x3); +dwc_ddrphy_apb_wr(0x42186, 0x3c0); +dwc_ddrphy_apb_wr(0x42187, 0x20); +dwc_ddrphy_apb_wr(0x42188, 0xc000); +dwc_ddrphy_apb_wr(0x42189, 0x3); +dwc_ddrphy_apb_wr(0x4218a, 0x3c0); +dwc_ddrphy_apb_wr(0x4218b, 0x2c1); +dwc_ddrphy_apb_wr(0x4218c, 0xc000); +dwc_ddrphy_apb_wr(0x4218d, 0x3); +dwc_ddrphy_apb_wr(0x4218e, 0x3c0); +dwc_ddrphy_apb_wr(0x4218f, 0x1001); +dwc_ddrphy_apb_wr(0x42190, 0x85f5); +dwc_ddrphy_apb_wr(0x42191, 0xf563); +dwc_ddrphy_apb_wr(0x42192, 0x3c5); +dwc_ddrphy_apb_wr(0x42193, 0x820); +dwc_ddrphy_apb_wr(0x42194, 0xc000); +dwc_ddrphy_apb_wr(0x42195, 0x3); +dwc_ddrphy_apb_wr(0x42196, 0x3c0); +dwc_ddrphy_apb_wr(0x42197, 0x20); +dwc_ddrphy_apb_wr(0x42198, 0xc000); +dwc_ddrphy_apb_wr(0x42199, 0x3); +dwc_ddrphy_apb_wr(0x4219a, 0x3c0); +dwc_ddrphy_apb_wr(0x4219b, 0x2c1); +dwc_ddrphy_apb_wr(0x4219c, 0xc000); +dwc_ddrphy_apb_wr(0x4219d, 0x3); +dwc_ddrphy_apb_wr(0x4219e, 0x3c0); +dwc_ddrphy_apb_wr(0x4219f, 0x1001); +dwc_ddrphy_apb_wr(0x421a0, 0x45d5); +dwc_ddrphy_apb_wr(0x421a1, 0xd563); +dwc_ddrphy_apb_wr(0x421a2, 0x3c5); +dwc_ddrphy_apb_wr(0x421a3, 0x421); +dwc_ddrphy_apb_wr(0x421a4, 0xc000); +dwc_ddrphy_apb_wr(0x421a5, 0x3); +dwc_ddrphy_apb_wr(0x421a6, 0x3c0); +dwc_ddrphy_apb_wr(0x421a7, 0x21); +dwc_ddrphy_apb_wr(0x421a8, 0xc000); +dwc_ddrphy_apb_wr(0x421a9, 0x3); +dwc_ddrphy_apb_wr(0x421aa, 0x3c0); +dwc_ddrphy_apb_wr(0x421ab, 0x2c1); +dwc_ddrphy_apb_wr(0x421ac, 0xc000); +dwc_ddrphy_apb_wr(0x421ad, 0x3); +dwc_ddrphy_apb_wr(0x421ae, 0x3c0); +dwc_ddrphy_apb_wr(0x421af, 0x1001); +dwc_ddrphy_apb_wr(0x421b0, 0x45f5); +dwc_ddrphy_apb_wr(0x421b1, 0xf563); +dwc_ddrphy_apb_wr(0x421b2, 0x3c5); +dwc_ddrphy_apb_wr(0x421b3, 0x821); +dwc_ddrphy_apb_wr(0x421b4, 0xc000); +dwc_ddrphy_apb_wr(0x421b5, 0x3); +dwc_ddrphy_apb_wr(0x421b6, 0x3c0); +dwc_ddrphy_apb_wr(0x421b7, 0x21); +dwc_ddrphy_apb_wr(0x421b8, 0xc000); +dwc_ddrphy_apb_wr(0x421b9, 0x3); +dwc_ddrphy_apb_wr(0x421ba, 0x3c0); +dwc_ddrphy_apb_wr(0x421bb, 0x2c1); +dwc_ddrphy_apb_wr(0x421bc, 0xc000); +dwc_ddrphy_apb_wr(0x421bd, 0x3); +dwc_ddrphy_apb_wr(0x421be, 0x3c0); +dwc_ddrphy_apb_wr(0x421bf, 0x1001); +dwc_ddrphy_apb_wr(0x421c0, 0xc5d5); +dwc_ddrphy_apb_wr(0x421c1, 0xd562); +dwc_ddrphy_apb_wr(0x421c2, 0x3c5); +dwc_ddrphy_apb_wr(0x421c3, 0x422); +dwc_ddrphy_apb_wr(0x421c4, 0xc000); +dwc_ddrphy_apb_wr(0x421c5, 0x3); +dwc_ddrphy_apb_wr(0x421c6, 0x3c0); +dwc_ddrphy_apb_wr(0x421c7, 0x22); +dwc_ddrphy_apb_wr(0x421c8, 0xc000); +dwc_ddrphy_apb_wr(0x421c9, 0x3); +dwc_ddrphy_apb_wr(0x421ca, 0x3c0); +dwc_ddrphy_apb_wr(0x421cb, 0x2c1); +dwc_ddrphy_apb_wr(0x421cc, 0xc000); +dwc_ddrphy_apb_wr(0x421cd, 0x3); +dwc_ddrphy_apb_wr(0x421ce, 0x3c0); +dwc_ddrphy_apb_wr(0x421cf, 0x1001); +dwc_ddrphy_apb_wr(0x421d0, 0xc5f5); +dwc_ddrphy_apb_wr(0x421d1, 0xf562); +dwc_ddrphy_apb_wr(0x421d2, 0x3c5); +dwc_ddrphy_apb_wr(0x421d3, 0x822); +dwc_ddrphy_apb_wr(0x421d4, 0xc000); +dwc_ddrphy_apb_wr(0x421d5, 0x3); +dwc_ddrphy_apb_wr(0x421d6, 0x3c0); +dwc_ddrphy_apb_wr(0x421d7, 0x22); +dwc_ddrphy_apb_wr(0x421d8, 0xc000); +dwc_ddrphy_apb_wr(0x421d9, 0x3); +dwc_ddrphy_apb_wr(0x421da, 0x3c0); +dwc_ddrphy_apb_wr(0x421db, 0x2c1); +dwc_ddrphy_apb_wr(0x421dc, 0xc000); +dwc_ddrphy_apb_wr(0x421dd, 0x3); +dwc_ddrphy_apb_wr(0x421de, 0x3c0); +dwc_ddrphy_apb_wr(0x421df, 0x1001); +dwc_ddrphy_apb_wr(0x421e0, 0xc5d5); +dwc_ddrphy_apb_wr(0x421e1, 0xd561); +dwc_ddrphy_apb_wr(0x421e2, 0x3c5); +dwc_ddrphy_apb_wr(0x421e3, 0x423); +dwc_ddrphy_apb_wr(0x421e4, 0xc000); +dwc_ddrphy_apb_wr(0x421e5, 0x3); +dwc_ddrphy_apb_wr(0x421e6, 0x3c0); +dwc_ddrphy_apb_wr(0x421e7, 0x23); +dwc_ddrphy_apb_wr(0x421e8, 0xc000); +dwc_ddrphy_apb_wr(0x421e9, 0x3); +dwc_ddrphy_apb_wr(0x421ea, 0x3c0); +dwc_ddrphy_apb_wr(0x421eb, 0x2c1); +dwc_ddrphy_apb_wr(0x421ec, 0xc000); +dwc_ddrphy_apb_wr(0x421ed, 0x3); +dwc_ddrphy_apb_wr(0x421ee, 0x3c0); +dwc_ddrphy_apb_wr(0x421ef, 0x1001); +dwc_ddrphy_apb_wr(0x421f0, 0xc5f5); +dwc_ddrphy_apb_wr(0x421f1, 0xf561); +dwc_ddrphy_apb_wr(0x421f2, 0x3c5); +dwc_ddrphy_apb_wr(0x421f3, 0x823); +dwc_ddrphy_apb_wr(0x421f4, 0xc000); +dwc_ddrphy_apb_wr(0x421f5, 0x3); +dwc_ddrphy_apb_wr(0x421f6, 0x3c0); +dwc_ddrphy_apb_wr(0x421f7, 0x23); +dwc_ddrphy_apb_wr(0x421f8, 0xc000); +dwc_ddrphy_apb_wr(0x421f9, 0x3); +dwc_ddrphy_apb_wr(0x421fa, 0x3c0); +dwc_ddrphy_apb_wr(0x421fb, 0x2c1); +dwc_ddrphy_apb_wr(0x421fc, 0xc000); +dwc_ddrphy_apb_wr(0x421fd, 0x3); +dwc_ddrphy_apb_wr(0x421fe, 0x3c0); +dwc_ddrphy_apb_wr(0x421ff, 0x1d01); +//// [phyinit_LoadPIECodeSections] Matched NO enable_bits = 2, type = 0 +dwc_ddrphy_apb_wr(0x42200, 0x213); +dwc_ddrphy_apb_wr(0x42201, 0x1300); +dwc_ddrphy_apb_wr(0x42202, 0x3c2); +dwc_ddrphy_apb_wr(0x42203, 0x21); +dwc_ddrphy_apb_wr(0x42204, 0xc000); +dwc_ddrphy_apb_wr(0x42205, 0x3); +dwc_ddrphy_apb_wr(0x42206, 0x3c0); +dwc_ddrphy_apb_wr(0x42207, 0x20); +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 20, type = 0 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 80, type = 0 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 40, type = 0 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 100, type = 0 +dwc_ddrphy_apb_wr(0x42208, 0xc000); +dwc_ddrphy_apb_wr(0x42209, 0x3); +dwc_ddrphy_apb_wr(0x4220a, 0x3c0); +dwc_ddrphy_apb_wr(0x4220b, 0x2e1); +dwc_ddrphy_apb_wr(0x4220c, 0xc000); +dwc_ddrphy_apb_wr(0x4220d, 0x3); +dwc_ddrphy_apb_wr(0x4220e, 0x3c0); +dwc_ddrphy_apb_wr(0x4220f, 0xef20); +dwc_ddrphy_apb_wr(0x42210, 0xc000); +dwc_ddrphy_apb_wr(0x42211, 0x3); +dwc_ddrphy_apb_wr(0x42212, 0x3c0); +dwc_ddrphy_apb_wr(0x42213, 0x2e1); +dwc_ddrphy_apb_wr(0x42214, 0xc000); +dwc_ddrphy_apb_wr(0x42215, 0x3); +dwc_ddrphy_apb_wr(0x42216, 0x3c0); +dwc_ddrphy_apb_wr(0x42217, 0x5920); +dwc_ddrphy_apb_wr(0x42218, 0x217); +dwc_ddrphy_apb_wr(0x42219, 0x1700); +dwc_ddrphy_apb_wr(0x4221a, 0x3c2); +dwc_ddrphy_apb_wr(0x4221b, 0x21); +dwc_ddrphy_apb_wr(0x4221c, 0xc000); +dwc_ddrphy_apb_wr(0x4221d, 0x3); +dwc_ddrphy_apb_wr(0x4221e, 0x3c0); +dwc_ddrphy_apb_wr(0x4221f, 0x20); +dwc_ddrphy_apb_wr(0x42220, 0xc000); +dwc_ddrphy_apb_wr(0x42221, 0x3); +dwc_ddrphy_apb_wr(0x42222, 0x3c0); +dwc_ddrphy_apb_wr(0x42223, 0x2e1); +dwc_ddrphy_apb_wr(0x42224, 0xc000); +dwc_ddrphy_apb_wr(0x42225, 0x3); +dwc_ddrphy_apb_wr(0x42226, 0x3c0); +dwc_ddrphy_apb_wr(0x42227, 0x420); +//// [phyinit_LoadPIECodeSections] Moving start address from 42228 to 90029 +dwc_ddrphy_apb_wr(0x90029, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b0s0 +dwc_ddrphy_apb_wr(0x9002a, 0x4); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b0s1 +dwc_ddrphy_apb_wr(0x9002b, 0x18); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b0s2 +dwc_ddrphy_apb_wr(0x9002c, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b1s0 +dwc_ddrphy_apb_wr(0x9002d, 0x4); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b1s1 +dwc_ddrphy_apb_wr(0x9002e, 0x18); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b1s2 +dwc_ddrphy_apb_wr(0x9002f, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b2s0 +dwc_ddrphy_apb_wr(0x90030, 0x4); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b2s1 +dwc_ddrphy_apb_wr(0x90031, 0x18); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b2s2 +dwc_ddrphy_apb_wr(0x90032, 0xb); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b3s0 +dwc_ddrphy_apb_wr(0x90033, 0x480); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b3s1 +dwc_ddrphy_apb_wr(0x90034, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b3s2 +dwc_ddrphy_apb_wr(0x90035, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b4s0 +dwc_ddrphy_apb_wr(0x90036, 0x448); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b4s1 +dwc_ddrphy_apb_wr(0x90037, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b4s2 +dwc_ddrphy_apb_wr(0x90038, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b5s0 +dwc_ddrphy_apb_wr(0x90039, 0x478); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b5s1 +dwc_ddrphy_apb_wr(0x9003a, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b5s2 +dwc_ddrphy_apb_wr(0x9003b, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b6s0 +dwc_ddrphy_apb_wr(0x9003c, 0xe8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b6s1 +dwc_ddrphy_apb_wr(0x9003d, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b6s2 +dwc_ddrphy_apb_wr(0x9003e, 0x2); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b7s0 +dwc_ddrphy_apb_wr(0x9003f, 0x10); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b7s1 +dwc_ddrphy_apb_wr(0x90040, 0x139); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b7s2 +dwc_ddrphy_apb_wr(0x90041, 0xf); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b8s0 +dwc_ddrphy_apb_wr(0x90042, 0x7c0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b8s1 +dwc_ddrphy_apb_wr(0x90043, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b8s2 +dwc_ddrphy_apb_wr(0x90044, 0x107); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b9s0 +dwc_ddrphy_apb_wr(0x90045, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b9s1 +dwc_ddrphy_apb_wr(0x90046, 0x159); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b9s2 +dwc_ddrphy_apb_wr(0x90047, 0x18); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b10s0 +dwc_ddrphy_apb_wr(0x90048, 0xe0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b10s1 +dwc_ddrphy_apb_wr(0x90049, 0x139); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b10s2 +dwc_ddrphy_apb_wr(0x9004a, 0x147); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b11s0 +dwc_ddrphy_apb_wr(0x9004b, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b11s1 +dwc_ddrphy_apb_wr(0x9004c, 0x159); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b11s2 +dwc_ddrphy_apb_wr(0x9004d, 0x14f); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b12s0 +dwc_ddrphy_apb_wr(0x9004e, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b12s1 +dwc_ddrphy_apb_wr(0x9004f, 0x159); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b12s2 +dwc_ddrphy_apb_wr(0x90050, 0x7); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b13s0 +dwc_ddrphy_apb_wr(0x90051, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b13s1 +dwc_ddrphy_apb_wr(0x90052, 0x149); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b13s2 +dwc_ddrphy_apb_wr(0x90053, 0x47); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b14s0 +dwc_ddrphy_apb_wr(0x90054, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b14s1 +dwc_ddrphy_apb_wr(0x90055, 0x149); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b14s2 +dwc_ddrphy_apb_wr(0x90056, 0x4f); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b15s0 +dwc_ddrphy_apb_wr(0x90057, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b15s1 +dwc_ddrphy_apb_wr(0x90058, 0x179); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b15s2 +//// [phyinit_LoadPIECodeSections] Matched NO enable_bits = 800, type = 0 +dwc_ddrphy_apb_wr(0x90059, 0x100); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b16s0 +dwc_ddrphy_apb_wr(0x9005a, 0x15c); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b16s1 +dwc_ddrphy_apb_wr(0x9005b, 0x139); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b16s2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 800, type = 0 +dwc_ddrphy_apb_wr(0x9005c, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b17s0 +dwc_ddrphy_apb_wr(0x9005d, 0x7c8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b17s1 +dwc_ddrphy_apb_wr(0x9005e, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b17s2 +dwc_ddrphy_apb_wr(0x9005f, 0x11); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b18s0 +dwc_ddrphy_apb_wr(0x90060, 0x530); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b18s1 +dwc_ddrphy_apb_wr(0x90061, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b18s2 +dwc_ddrphy_apb_wr(0x90062, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b19s0 +dwc_ddrphy_apb_wr(0x90063, 0x1); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b19s1 +dwc_ddrphy_apb_wr(0x90064, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b19s2 +dwc_ddrphy_apb_wr(0x90065, 0x14f); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b20s0 +dwc_ddrphy_apb_wr(0x90066, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b20s1 +dwc_ddrphy_apb_wr(0x90067, 0x159); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b20s2 +dwc_ddrphy_apb_wr(0x90068, 0x2); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b21s0 +dwc_ddrphy_apb_wr(0x90069, 0x45a); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b21s1 +dwc_ddrphy_apb_wr(0x9006a, 0x9); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b21s2 +dwc_ddrphy_apb_wr(0x9006b, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b22s0 +dwc_ddrphy_apb_wr(0x9006c, 0x530); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b22s1 +dwc_ddrphy_apb_wr(0x9006d, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b22s2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 800, type = 0 +dwc_ddrphy_apb_wr(0x9006e, 0xc100); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b23s0 +dwc_ddrphy_apb_wr(0x9006f, 0x15c); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b23s1 +dwc_ddrphy_apb_wr(0x90070, 0x139); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b23s2 +dwc_ddrphy_apb_wr(0x90071, 0x18); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b24s0 +dwc_ddrphy_apb_wr(0x90072, 0x65a); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b24s1 +dwc_ddrphy_apb_wr(0x90073, 0x9); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b24s2 +dwc_ddrphy_apb_wr(0x90074, 0x41); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b25s0 +dwc_ddrphy_apb_wr(0x90075, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b25s1 +dwc_ddrphy_apb_wr(0x90076, 0x179); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b25s2 +dwc_ddrphy_apb_wr(0x90077, 0x1); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b26s0 +dwc_ddrphy_apb_wr(0x90078, 0x618); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b26s1 +dwc_ddrphy_apb_wr(0x90079, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b26s2 +dwc_ddrphy_apb_wr(0x9007a, 0x40c0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b27s0 +dwc_ddrphy_apb_wr(0x9007b, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b27s1 +dwc_ddrphy_apb_wr(0x9007c, 0x149); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b27s2 +dwc_ddrphy_apb_wr(0x9007d, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b28s0 +dwc_ddrphy_apb_wr(0x9007e, 0x4); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b28s1 +dwc_ddrphy_apb_wr(0x9007f, 0x48); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b28s2 +dwc_ddrphy_apb_wr(0x90080, 0x4040); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b29s0 +dwc_ddrphy_apb_wr(0x90081, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b29s1 +dwc_ddrphy_apb_wr(0x90082, 0x149); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b29s2 +dwc_ddrphy_apb_wr(0x90083, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b30s0 +dwc_ddrphy_apb_wr(0x90084, 0x4); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b30s1 +dwc_ddrphy_apb_wr(0x90085, 0x48); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b30s2 +dwc_ddrphy_apb_wr(0x90086, 0x40); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b31s0 +dwc_ddrphy_apb_wr(0x90087, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b31s1 +dwc_ddrphy_apb_wr(0x90088, 0x149); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b31s2 +dwc_ddrphy_apb_wr(0x90089, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b32s0 +dwc_ddrphy_apb_wr(0x9008a, 0x658); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b32s1 +dwc_ddrphy_apb_wr(0x9008b, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b32s2 +dwc_ddrphy_apb_wr(0x9008c, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b33s0 +dwc_ddrphy_apb_wr(0x9008d, 0x4); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b33s1 +dwc_ddrphy_apb_wr(0x9008e, 0x18); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b33s2 +dwc_ddrphy_apb_wr(0x9008f, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b34s0 +dwc_ddrphy_apb_wr(0x90090, 0x4); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b34s1 +dwc_ddrphy_apb_wr(0x90091, 0x78); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b34s2 +dwc_ddrphy_apb_wr(0x90092, 0x549); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b35s0 +dwc_ddrphy_apb_wr(0x90093, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b35s1 +dwc_ddrphy_apb_wr(0x90094, 0x159); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b35s2 +dwc_ddrphy_apb_wr(0x90095, 0xd49); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b36s0 +dwc_ddrphy_apb_wr(0x90096, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b36s1 +dwc_ddrphy_apb_wr(0x90097, 0x159); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b36s2 +dwc_ddrphy_apb_wr(0x90098, 0x94c); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b37s0 +dwc_ddrphy_apb_wr(0x90099, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b37s1 +dwc_ddrphy_apb_wr(0x9009a, 0x159); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b37s2 +dwc_ddrphy_apb_wr(0x9009b, 0x94c); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b38s0 +dwc_ddrphy_apb_wr(0x9009c, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b38s1 +dwc_ddrphy_apb_wr(0x9009d, 0x159); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b38s2 +dwc_ddrphy_apb_wr(0x9009e, 0x442); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b39s0 +dwc_ddrphy_apb_wr(0x9009f, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b39s1 +dwc_ddrphy_apb_wr(0x900a0, 0x149); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b39s2 +dwc_ddrphy_apb_wr(0x900a1, 0x42); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b40s0 +dwc_ddrphy_apb_wr(0x900a2, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b40s1 +dwc_ddrphy_apb_wr(0x900a3, 0x149); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b40s2 +dwc_ddrphy_apb_wr(0x900a4, 0x1); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b41s0 +dwc_ddrphy_apb_wr(0x900a5, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b41s1 +dwc_ddrphy_apb_wr(0x900a6, 0x149); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b41s2 +dwc_ddrphy_apb_wr(0x900a7, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b42s0 +dwc_ddrphy_apb_wr(0x900a8, 0xe0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b42s1 +dwc_ddrphy_apb_wr(0x900a9, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b42s2 +dwc_ddrphy_apb_wr(0x900aa, 0xa); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b43s0 +dwc_ddrphy_apb_wr(0x900ab, 0x10); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b43s1 +dwc_ddrphy_apb_wr(0x900ac, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b43s2 +dwc_ddrphy_apb_wr(0x900ad, 0x9); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b44s0 +dwc_ddrphy_apb_wr(0x900ae, 0x3c0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b44s1 +dwc_ddrphy_apb_wr(0x900af, 0x149); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b44s2 +dwc_ddrphy_apb_wr(0x900b0, 0x9); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b45s0 +dwc_ddrphy_apb_wr(0x900b1, 0x3c0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b45s1 +dwc_ddrphy_apb_wr(0x900b2, 0x159); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b45s2 +dwc_ddrphy_apb_wr(0x900b3, 0x18); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b46s0 +dwc_ddrphy_apb_wr(0x900b4, 0x10); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b46s1 +dwc_ddrphy_apb_wr(0x900b5, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b46s2 +dwc_ddrphy_apb_wr(0x900b6, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b47s0 +dwc_ddrphy_apb_wr(0x900b7, 0x3c0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b47s1 +dwc_ddrphy_apb_wr(0x900b8, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b47s2 +dwc_ddrphy_apb_wr(0x900b9, 0x18); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b48s0 +dwc_ddrphy_apb_wr(0x900ba, 0x4); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b48s1 +dwc_ddrphy_apb_wr(0x900bb, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b48s2 +dwc_ddrphy_apb_wr(0x900bc, 0xc); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b49s0 +dwc_ddrphy_apb_wr(0x900bd, 0x10); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b49s1 +dwc_ddrphy_apb_wr(0x900be, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b49s2 +dwc_ddrphy_apb_wr(0x900bf, 0x3); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b50s0 +dwc_ddrphy_apb_wr(0x900c0, 0x10); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b50s1 +dwc_ddrphy_apb_wr(0x900c1, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b50s2 +dwc_ddrphy_apb_wr(0x900c2, 0x7); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b51s0 +dwc_ddrphy_apb_wr(0x900c3, 0x7c0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b51s1 +dwc_ddrphy_apb_wr(0x900c4, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b51s2 +//// [phyinit_LoadPIECodeSections] Matched ANY enable_bits = 8, type = 0 +dwc_ddrphy_apb_wr(0x900c5, 0x3a); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b52s0 +dwc_ddrphy_apb_wr(0x900c6, 0x1e2); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b52s1 +dwc_ddrphy_apb_wr(0x900c7, 0x9); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b52s2 +dwc_ddrphy_apb_wr(0x900c8, 0x10); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b53s0 +dwc_ddrphy_apb_wr(0x900c9, 0x10); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b53s1 +dwc_ddrphy_apb_wr(0x900ca, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b53s2 +dwc_ddrphy_apb_wr(0x900cb, 0x10); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b54s0 +dwc_ddrphy_apb_wr(0x900cc, 0x400); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b54s1 +dwc_ddrphy_apb_wr(0x900cd, 0x16e); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b54s2 +dwc_ddrphy_apb_wr(0x900ce, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b55s0 +dwc_ddrphy_apb_wr(0x900cf, 0x7c8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b55s1 +dwc_ddrphy_apb_wr(0x900d0, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b55s2 +dwc_ddrphy_apb_wr(0x900d1, 0x10); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b56s0 +dwc_ddrphy_apb_wr(0x900d2, 0x10); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b56s1 +dwc_ddrphy_apb_wr(0x900d3, 0x169); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b56s2 +dwc_ddrphy_apb_wr(0x900d4, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b57s0 +dwc_ddrphy_apb_wr(0x900d5, 0x978); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b57s1 +dwc_ddrphy_apb_wr(0x900d6, 0x169); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b57s2 +dwc_ddrphy_apb_wr(0x900d7, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b58s0 +dwc_ddrphy_apb_wr(0x900d8, 0xa78); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b58s1 +dwc_ddrphy_apb_wr(0x900d9, 0x169); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b58s2 +dwc_ddrphy_apb_wr(0x900da, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b59s0 +dwc_ddrphy_apb_wr(0x900db, 0x980); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b59s1 +dwc_ddrphy_apb_wr(0x900dc, 0x169); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b59s2 +dwc_ddrphy_apb_wr(0x900dd, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b60s0 +dwc_ddrphy_apb_wr(0x900de, 0xa80); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b60s1 +dwc_ddrphy_apb_wr(0x900df, 0x169); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b60s2 +dwc_ddrphy_apb_wr(0x900e0, 0x32); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b61s0 +dwc_ddrphy_apb_wr(0x900e1, 0x952); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b61s1 +dwc_ddrphy_apb_wr(0x900e2, 0x69); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b61s2 +dwc_ddrphy_apb_wr(0x900e3, 0x32); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b62s0 +dwc_ddrphy_apb_wr(0x900e4, 0xa52); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b62s1 +dwc_ddrphy_apb_wr(0x900e5, 0x69); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b62s2 +dwc_ddrphy_apb_wr(0x900e6, 0x2); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b63s0 +dwc_ddrphy_apb_wr(0x900e7, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b63s1 +dwc_ddrphy_apb_wr(0x900e8, 0x68); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b63s2 +dwc_ddrphy_apb_wr(0x900e9, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b64s0 +dwc_ddrphy_apb_wr(0x900ea, 0x370); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b64s1 +dwc_ddrphy_apb_wr(0x900eb, 0x169); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b64s2 +dwc_ddrphy_apb_wr(0x900ec, 0x1); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b65s0 +dwc_ddrphy_apb_wr(0x900ed, 0x1400); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b65s1 +dwc_ddrphy_apb_wr(0x900ee, 0x169); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b65s2 +dwc_ddrphy_apb_wr(0x900ef, 0x18); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b66s0 +dwc_ddrphy_apb_wr(0x900f0, 0x8e8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b66s1 +dwc_ddrphy_apb_wr(0x900f1, 0x169); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b66s2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 20, type = 0 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 80, type = 0 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 40, type = 0 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 100, type = 0 +//// [phyinit_LoadPIECodeSections] Matched NO enable_bits = 2, type = 0 +dwc_ddrphy_apb_wr(0x900f2, 0x2cd); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b67s0 +dwc_ddrphy_apb_wr(0x900f3, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b67s1 +dwc_ddrphy_apb_wr(0x900f4, 0x68); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b67s2 +dwc_ddrphy_apb_wr(0x900f5, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b68s0 +dwc_ddrphy_apb_wr(0x900f6, 0x8e8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b68s1 +dwc_ddrphy_apb_wr(0x900f7, 0x169); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b68s2 +dwc_ddrphy_apb_wr(0x900f8, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b69s0 +dwc_ddrphy_apb_wr(0x900f9, 0x3c8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b69s1 +dwc_ddrphy_apb_wr(0x900fa, 0x1e9); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b69s2 +dwc_ddrphy_apb_wr(0x900fb, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b70s0 +dwc_ddrphy_apb_wr(0x900fc, 0x370); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b70s1 +dwc_ddrphy_apb_wr(0x900fd, 0x169); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b70s2 +dwc_ddrphy_apb_wr(0x900fe, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b71s0 +dwc_ddrphy_apb_wr(0x900ff, 0xe8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b71s1 +dwc_ddrphy_apb_wr(0x90100, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b71s2 +dwc_ddrphy_apb_wr(0x90101, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b72s0 +dwc_ddrphy_apb_wr(0x90102, 0x8140); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b72s1 +dwc_ddrphy_apb_wr(0x90103, 0x10c); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b72s2 +dwc_ddrphy_apb_wr(0x90104, 0x10); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b73s0 +dwc_ddrphy_apb_wr(0x90105, 0x8138); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b73s1 +dwc_ddrphy_apb_wr(0x90106, 0x10c); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b73s2 +//// [phyinit_LoadPIECodeSections] Matched ANY enable_bits = 1, type = 0 +dwc_ddrphy_apb_wr(0x90107, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b74s0 +dwc_ddrphy_apb_wr(0x90108, 0x400); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b74s1 +dwc_ddrphy_apb_wr(0x90109, 0x10e); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b74s2 +dwc_ddrphy_apb_wr(0x9010a, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b75s0 +dwc_ddrphy_apb_wr(0x9010b, 0x448); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b75s1 +dwc_ddrphy_apb_wr(0x9010c, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b75s2 +dwc_ddrphy_apb_wr(0x9010d, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b76s0 +dwc_ddrphy_apb_wr(0x9010e, 0x7c8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b76s1 +dwc_ddrphy_apb_wr(0x9010f, 0x101); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b76s2 +dwc_ddrphy_apb_wr(0x90110, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b77s0 +dwc_ddrphy_apb_wr(0x90111, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b77s1 +dwc_ddrphy_apb_wr(0x90112, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b77s2 +dwc_ddrphy_apb_wr(0x90113, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b78s0 +dwc_ddrphy_apb_wr(0x90114, 0x448); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b78s1 +dwc_ddrphy_apb_wr(0x90115, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b78s2 +dwc_ddrphy_apb_wr(0x90116, 0xf); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b79s0 +dwc_ddrphy_apb_wr(0x90117, 0x7c0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b79s1 +dwc_ddrphy_apb_wr(0x90118, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b79s2 +dwc_ddrphy_apb_wr(0x90119, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b80s0 +dwc_ddrphy_apb_wr(0x9011a, 0xe8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b80s1 +dwc_ddrphy_apb_wr(0x9011b, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b80s2 +dwc_ddrphy_apb_wr(0x9011c, 0x7); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b81s0 +dwc_ddrphy_apb_wr(0x9011d, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b81s1 +dwc_ddrphy_apb_wr(0x9011e, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b81s2 +dwc_ddrphy_apb_wr(0x9011f, 0x47); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b82s0 +dwc_ddrphy_apb_wr(0x90120, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b82s1 +dwc_ddrphy_apb_wr(0x90121, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b82s2 +dwc_ddrphy_apb_wr(0x90122, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b83s0 +dwc_ddrphy_apb_wr(0x90123, 0x618); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b83s1 +dwc_ddrphy_apb_wr(0x90124, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b83s2 +dwc_ddrphy_apb_wr(0x90125, 0x18); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b84s0 +dwc_ddrphy_apb_wr(0x90126, 0xe0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b84s1 +dwc_ddrphy_apb_wr(0x90127, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b84s2 +dwc_ddrphy_apb_wr(0x90128, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b85s0 +dwc_ddrphy_apb_wr(0x90129, 0x7c8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b85s1 +dwc_ddrphy_apb_wr(0x9012a, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b85s2 +dwc_ddrphy_apb_wr(0x9012b, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b86s0 +dwc_ddrphy_apb_wr(0x9012c, 0x8140); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b86s1 +dwc_ddrphy_apb_wr(0x9012d, 0x10c); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b86s2 +dwc_ddrphy_apb_wr(0x9012e, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b87s0 +dwc_ddrphy_apb_wr(0x9012f, 0x478); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b87s1 +dwc_ddrphy_apb_wr(0x90130, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b87s2 +dwc_ddrphy_apb_wr(0x90131, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b88s0 +dwc_ddrphy_apb_wr(0x90132, 0x1); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b88s1 +dwc_ddrphy_apb_wr(0x90133, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b88s2 +dwc_ddrphy_apb_wr(0x90134, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b89s0 +dwc_ddrphy_apb_wr(0x90135, 0x4); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b89s1 +dwc_ddrphy_apb_wr(0x90136, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b89s2 +dwc_ddrphy_apb_wr(0x90137, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b90s0 +dwc_ddrphy_apb_wr(0x90138, 0x7c8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b90s1 +dwc_ddrphy_apb_wr(0x90139, 0x101); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b90s2 +//// [phyinit_LoadPIECodeSections] Moving start address from 9013a to 90006 +dwc_ddrphy_apb_wr(0x90006, 0x0); // DWC_DDRPHYA_INITENG0_base0_PostSequenceReg0b0s0 +dwc_ddrphy_apb_wr(0x90007, 0x0); // DWC_DDRPHYA_INITENG0_base0_PostSequenceReg0b0s1 +dwc_ddrphy_apb_wr(0x90008, 0x8); // DWC_DDRPHYA_INITENG0_base0_PostSequenceReg0b0s2 +dwc_ddrphy_apb_wr(0x90009, 0x0); // DWC_DDRPHYA_INITENG0_base0_PostSequenceReg0b1s0 +dwc_ddrphy_apb_wr(0x9000a, 0x0); // DWC_DDRPHYA_INITENG0_base0_PostSequenceReg0b1s1 +dwc_ddrphy_apb_wr(0x9000b, 0x0); // DWC_DDRPHYA_INITENG0_base0_PostSequenceReg0b1s2 +//// [phyinit_LoadPIECodeSections] Moving start address from 9000c to d00e7 +dwc_ddrphy_apb_wr(0xd00e7, 0x400); // DWC_DDRPHYA_APBONLY0_SequencerOverride +//// [phyinit_LoadPIECodeSections] End of dwc_ddrphy_phyinit_LoadPIECodeSections() +dwc_ddrphy_apb_wr(0x20240, 0x4300); // DWC_DDRPHYA_MASTER0_base0_D5ACSMPtrXlat0 +dwc_ddrphy_apb_wr(0x20242, 0x8944); // DWC_DDRPHYA_MASTER0_base0_D5ACSMPtrXlat2 +dwc_ddrphy_apb_wr(0x20241, 0x4300); // DWC_DDRPHYA_MASTER0_base0_D5ACSMPtrXlat1 +dwc_ddrphy_apb_wr(0x20243, 0x8944); // DWC_DDRPHYA_MASTER0_base0_D5ACSMPtrXlat3 +//seq0b_LoadPstateSeqProductionCode(): --------------------------------------------------------------------------------------------------- +//seq0b_LoadPstateSeqProductionCode(): Programming the 0B sequencer 0b0000 start vector registers with 0. +//seq0b_LoadPstateSeqProductionCode(): Programming the 0B sequencer 0b1000 start vector register with 54. +//seq0b_LoadPstateSeqProductionCode(): Programming the 0B sequencer 0b1111 start vector register with 77. +//seq0b_LoadPstateSeqProductionCode(): --------------------------------------------------------------------------------------------------- +dwc_ddrphy_apb_wr(0x90017, 0x0); // DWC_DDRPHYA_INITENG0_base0_StartVector0b0 +dwc_ddrphy_apb_wr(0x9001f, 0x36); // DWC_DDRPHYA_INITENG0_base0_StartVector0b8 +dwc_ddrphy_apb_wr(0x90026, 0x4d); // DWC_DDRPHYA_INITENG0_base0_StartVector0b15 +dwc_ddrphy_apb_wr(0x9000c, 0x0); // DWC_DDRPHYA_INITENG0_base0_Seq0BDisableFlag0 +dwc_ddrphy_apb_wr(0x9000d, 0x173); // DWC_DDRPHYA_INITENG0_base0_Seq0BDisableFlag1 +dwc_ddrphy_apb_wr(0x9000e, 0x60); // DWC_DDRPHYA_INITENG0_base0_Seq0BDisableFlag2 +dwc_ddrphy_apb_wr(0x9000f, 0x6110); // DWC_DDRPHYA_INITENG0_base0_Seq0BDisableFlag3 +dwc_ddrphy_apb_wr(0x90010, 0x2152); // DWC_DDRPHYA_INITENG0_base0_Seq0BDisableFlag4 +dwc_ddrphy_apb_wr(0x90011, 0xdfbd); // DWC_DDRPHYA_INITENG0_base0_Seq0BDisableFlag5 +dwc_ddrphy_apb_wr(0x90012, 0x8060); // DWC_DDRPHYA_INITENG0_base0_Seq0BDisableFlag6 +dwc_ddrphy_apb_wr(0x90013, 0x6152); // DWC_DDRPHYA_INITENG0_base0_Seq0BDisableFlag7 +//// [phyinit_I_loadPIEImage] Enabling Phy Master Interface for DRAM drift compensation +//// [phyinit_I_loadPIEImage] Pstate=0, Memclk=1600MHz, Programming PPTTrainSetup::PhyMstrTrainInterval to 0x0 +//// [phyinit_I_loadPIEImage] Pstate=0, Memclk=1600MHz, Programming PPTTrainSetup::PhyMstrMaxReqToAck to 0x0 +dwc_ddrphy_apb_wr(0x20010, 0x0); // DWC_DDRPHYA_MASTER0_base0_PPTTrainSetup_p0 +//// [phyinit_I_loadPIEImage] Pstate=0, Memclk=1600MHz, Programming PPTTrainSetup2::PhyMstrFreqOverride to 0x3 +dwc_ddrphy_apb_wr(0x20011, 0x3); // DWC_DDRPHYA_MASTER0_base0_PPTTrainSetup2_p0 +//// [phyinit_I_loadPIEImage] Programming D5ACSMXlatSelect to 0x1 +dwc_ddrphy_apb_wr(0x20281, 0x1); // DWC_DDRPHYA_MASTER0_base0_D5ACSMXlatSelect +//// [phyinit_I_loadPIEImage] Programming DbyteRxEnTrain::EnDqsSampNegRxEn to 0x1 +dwc_ddrphy_apb_wr(0x2003b, 0x2); // DWC_DDRPHYA_MASTER0_base0_DbyteRxEnTrain +//// [phyinit_I_loadPIEImage] Pstate=0, Memclk=1600MHz, Programming TrackingModeCntrl to 0x131f +dwc_ddrphy_apb_wr(0x20041, 0x131f); // DWC_DDRPHYA_MASTER0_base0_TrackingModeCntrl_p0 +//// [phyinit_I_loadPIEImage] Programming D5ACSM0MaskCs to 0xe +dwc_ddrphy_apb_wr(0x20131, 0xe); // DWC_DDRPHYA_MASTER0_base0_D5ACSM0MaskCs +//// [phyinit_I_loadPIEImage] Programming D5ACSM1MaskCs to 0xf +dwc_ddrphy_apb_wr(0x20151, 0xf); // DWC_DDRPHYA_MASTER0_base0_D5ACSM1MaskCs +//// [phyinit_I_loadPIEImage] Pstate=0, Memclk=1600MHz, Programming Seq0BGPR6[0] with OuterLoopRepeatCnt values to 0x2 +dwc_ddrphy_apb_wr(0x90306, 0x2); // DWC_DDRPHYA_INITENG0_base0_Seq0BGPR6_p0 +//// [phyinit_I_loadPIEImage] Programming D5ACSM<0/1>OuterLoopRepeatCnt=2 +dwc_ddrphy_apb_wr(0x2012a, 0x2); // DWC_DDRPHYA_MASTER0_base0_D5ACSM0OuterLoopRepeatCnt +dwc_ddrphy_apb_wr(0x2014a, 0x2); // DWC_DDRPHYA_MASTER0_base0_D5ACSM1OuterLoopRepeatCnt +//// [phyinit_I_loadPIEImage] Programming D5ACSM<0/1>AddressMask=7ff +dwc_ddrphy_apb_wr(0x20126, 0x7ff); // DWC_DDRPHYA_MASTER0_base0_D5ACSM0AddressMask +dwc_ddrphy_apb_wr(0x20146, 0x7ff); // DWC_DDRPHYA_MASTER0_base0_D5ACSM1AddressMask +//// [phyinit_I_loadPIEImage] Programming D5ACSM<0/1>AlgaIncVal=1 +dwc_ddrphy_apb_wr(0x20127, 0x1); // DWC_DDRPHYA_MASTER0_base0_D5ACSM0AlgaIncVal +dwc_ddrphy_apb_wr(0x20147, 0x1); // DWC_DDRPHYA_MASTER0_base0_D5ACSM1AlgaIncVal +//// [phyinit_I_loadPIEImage] Turn on calibration and hold idle until dfi_init_start is asserted sequence is triggered. +//// [phyinit_I_loadPIEImage] Programming CalZap to 0x1 +//// [phyinit_I_loadPIEImage] Programming CalRate::CalRun to 0x1 +//// [phyinit_I_loadPIEImage] Programming CalRate to 0x19 +dwc_ddrphy_apb_wr(0x20089, 0x1); // DWC_DDRPHYA_MASTER0_base0_CalZap +dwc_ddrphy_apb_wr(0x20088, 0x19); // DWC_DDRPHYA_MASTER0_base0_CalRate +//// [phyinit_I_loadPIEImage] Programming ForceClkGaterEnables::ForcePubDxClkEnLow to 0x0 +dwc_ddrphy_apb_wr(0x200a6, 0x0); // DWC_DDRPHYA_MASTER0_base0_ForceClkGaterEnables +//// Disabling Ucclk (PMU) and Hclk (training hardware) +dwc_ddrphy_apb_wr(0xc0080, 0x0); // DWC_DDRPHYA_DRTUB0_UcclkHclkEnables +//// Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. +dwc_ddrphy_apb_wr(0xd0000, 0x1); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel +//// [phyinit_userCustom_wait] Wait 40 DfiClks +//// [phyinit_I_loadPIEImage] End of dwc_ddrphy_phyinit_I_loadPIEImage() +// +// +////############################################################## +//// +//// dwc_ddrphy_phyinit_userCustom_customPostTrain is a user-editable function. +//// +//// The purpose of dwc_ddrphy_phyinit_userCustom_customPostTrain() is to override any +//// CSR values programmed by the training firmware or dwc_ddrphy_phyinit_progCsrSkipTrain() +//// This function is executed after training +//// +//// IMPORTANT: in this function, user shall not override any values in userInputBasic and +//// userInputAdvanced data structures. Only CSR programming should be done in this function. +//// +//// Sequence of Events in this function are: +//// 1. Enable APB access. +//// 2. Issue register writes +//// 3. Isolate APB access. +// +////############################################################## +// +dwc_ddrphy_phyinit_userCustom_customPostTrain(); + +//// [dwc_ddrphy_phyinit_userCustom_customPostTrain] End of dwc_ddrphy_phyinit_userCustom_customPostTrain() +//// [dwc_ddrphy_phyinit_userCustom_J_enterMissionMode] Start of dwc_ddrphy_phyinit_userCustom_J_enterMissionMode() +// +// +////############################################################## +//// +//// 4.3.10(J) Initialize the PHY to Mission Mode through DFI Initialization +//// +//// Initialize the PHY to mission mode as follows: +//// +//// 1. Set the PHY input clocks to the desired frequency. +//// 2. Initialize the PHY to mission mode by performing DFI Initialization. +//// Please see the DFI specification for more information. See the DFI frequency bus encoding in section <XXX>. +//// Note: The PHY training firmware initializes the DRAM state. if skip +//// training is used, the DRAM state is not initialized. +//// +////############################################################## +// +dwc_ddrphy_phyinit_userCustom_J_enterMissionMode(sdrammc); + +// +//// [dwc_ddrphy_phyinit_userCustom_J_enterMissionMode] End of dwc_ddrphy_phyinit_userCustom_J_enterMissionMode() +// [dwc_ddrphy_phyinit_sequence] End of dwc_ddrphy_phyinit_sequence() +// [dwc_ddrphy_phyinit_main] End of dwc_ddrphy_phyinit_main() diff --git a/drivers/ram/aspeed/sdram_ast2700.c b/drivers/ram/aspeed/sdram_ast2700.c new file mode 100644 index 00000000000..4a019c4edb1 --- /dev/null +++ b/drivers/ram/aspeed/sdram_ast2700.c @@ -0,0 +1,1036 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) ASPEED Technology Inc. + */ +#include <asm/io.h> +#include <asm/arch/fmc_hdr.h> +#include <asm/arch/scu.h> +#include <asm/arch/sdram.h> +#include <config.h> +#include <dm.h> +#include <linux/bitfield.h> +#include <linux/delay.h> +#include <linux/err.h> +#include <linux/sizes.h> +#include <ram.h> + +enum ddr_type { + DDR4_1600 = 0x0, + DDR4_2400, + DDR4_3200, + DDR5_3200, + + DDR_TYPES +}; + +enum ddr_size { + DDR_SIZE_256MB, + DDR_SIZE_512MB, + DDR_SIZE_1GB, + DDR_SIZE_2GB, + + DDR_SIZE_MAX, +}; + +#define IS_DDR4(t) \ + (((t) <= DDR4_3200) ? 1 : 0) + +struct sdrammc_ac_timing { + u32 t_cl; + u32 t_cwl; + u32 t_bl; + u32 t_rcd; /* ACT-to-read/write command delay */ + u32 t_rp; /* PRE command period */ + u32 t_ras; /* ACT-to-PRE command delay */ + u32 t_rrd; /* ACT-to-ACT delay for different BG */ + u32 t_rrd_l; /* ACT-to-ACT delay for same BG */ + u32 t_faw; /* Four active window */ + u32 t_rtp; /* Read-to-PRE command delay */ + u32 t_wtr; /* Minimum write to read command for different BG */ + u32 t_wtr_l; /* Minimum write to read command for same BG */ + u32 t_wtr_a; /* Write to read command for same BG with auto precharge */ + u32 t_wtp; /* Minimum write to precharge command delay */ + u32 t_rtw; /* minimum read to write command */ + u32 t_ccd_l; /* CAS-to-CAS delay for same BG */ + u32 t_dllk; /* DLL locking time */ + u32 t_cksre; /* valid clock before after self-refresh or power-down entry/exit process */ + u32 t_pd; /* power-down entry to exit minimum width */ + u32 t_xp; /* exit power-down to valid command delay */ + u32 t_rfc; /* refresh time period */ + u32 t_mrd; + u32 t_refsbrd; + u32 t_rfcsb; + u32 t_cshsr; + u32 t_zq; +}; + +static const struct sdrammc_ac_timing ac_table[] = { + [DDR4_1600] = { + .t_cl = 10, .t_cwl = 9, .t_bl = 8, .t_rcd = 10, + .t_rp = 10, .t_ras = 28, .t_rrd = 5, .t_rrd_l = 6, + .t_faw = 28, .t_rtp = 6, .t_wtr = 2, .t_wtr_l = 6, + .t_wtr_a = 0, .t_wtp = 12, .t_rtw = 0, .t_ccd_l = 5, + .t_dllk = 597, .t_cksre = 8, .t_pd = 4, .t_xp = 5, + .t_rfc = 880, .t_mrd = 24, .t_refsbrd = 0, .t_rfcsb = 0, + .t_cshsr = 0, .t_zq = 80, + }, + [DDR4_2400] = { + .t_cl = 15, .t_cwl = 12, .t_bl = 8, .t_rcd = 16, + .t_rp = 16, .t_ras = 39, .t_rrd = 7, .t_rrd_l = 8, + .t_faw = 37, .t_rtp = 10, .t_wtr = 4, .t_wtr_l = 10, + .t_wtr_a = 0, .t_wtp = 19, .t_rtw = 0, .t_ccd_l = 7, + .t_dllk = 768, .t_cksre = 13, .t_pd = 7, .t_xp = 8, + .t_rfc = 880, .t_mrd = 24, .t_refsbrd = 0, .t_rfcsb = 0, + .t_cshsr = 0, .t_zq = 80, + }, + [DDR4_3200] = { + .t_cl = 20, .t_cwl = 16, .t_bl = 8, .t_rcd = 20, + .t_rp = 20, .t_ras = 52, .t_rrd = 9, .t_rrd_l = 11, + .t_faw = 48, .t_rtp = 12, .t_wtr = 4, .t_wtr_l = 12, + .t_wtr_a = 0, .t_wtp = 24, .t_rtw = 0, .t_ccd_l = 8, + .t_dllk = 1023, .t_cksre = 16, .t_pd = 8, .t_xp = 10, + .t_rfc = 880, .t_mrd = 24, .t_refsbrd = 0, .t_rfcsb = 0, + .t_cshsr = 0, .t_zq = 80, + }, + [DDR5_3200] = { + .t_cl = 26, .t_cwl = 24, .t_bl = 16, .t_rcd = 26, + .t_rp = 26, .t_ras = 52, .t_rrd = 8, .t_rrd_l = 8, + .t_faw = 40, .t_rtp = 12, .t_wtr = 4, .t_wtr_l = 16, + .t_wtr_a = 36, .t_wtp = 48, .t_rtw = 0, .t_ccd_l = 8, + .t_dllk = 1024, .t_cksre = 9, .t_pd = 13, .t_xp = 13, + .t_rfc = 880, .t_mrd = 23, .t_refsbrd = 48, .t_rfcsb = 208, + .t_cshsr = 30, + .t_zq = 48, + }, +}; + +struct sdrammc { + u32 type; + void __iomem *regs; + void __iomem *phy; + void __iomem *scu0; + void __iomem *scu1; + const struct sdrammc_ac_timing *ac; + struct ram_info info; +}; + +static size_t ast2700_sdrammc_get_vga_mem_size(struct sdrammc *sdrammc) +{ + struct sdrammc_regs *regs = sdrammc->regs; + void *scu0 = sdrammc->scu0; + size_t vga_memsz[] = { + SZ_32M, + SZ_64M, + }; + u32 reg, sel, dual = 0; + + sel = readl(®s->gfmcfg) & 0x1; + + reg = readl(scu0 + SCU0_PCI_MISC70); + if (reg & SCU0_PCI_MISC70_EN_PCIEVGA0) { + debug("VGA0:%dMB\n", vga_memsz[sel] / SZ_1M); + dual++; + } + + reg = readl(scu0 + SCU0_PCI_MISC80); + if (reg & SCU0_PCI_MISC80_EN_PCIEVGA1) { + debug("VGA1:%dMB\n", vga_memsz[sel] / SZ_1M); + dual++; + } + + return vga_memsz[sel] * dual; +} + +static int sdrammc_calc_size(struct sdrammc *sdrammc) +{ + struct sdrammc_regs *regs = sdrammc->regs; + u32 val, test_pattern = 0xdeadbeef; + size_t sz; + + struct { + u32 size; + int rfc[2]; + } ddr_capacity[] = { + { 0x10000000UL, {208, 256} }, /* 256MB */ + { 0x20000000UL, {208, 416} }, /* 512MB */ + { 0x40000000UL, {208, 560} }, /* 1GB */ + { 0x80000000UL, {472, 880} }, /* 2GB */ + }; + + /* Configure ram size to max to enable whole area */ + val = readl(®s->mcfg); + val &= ~(0x7 << 2); + writel(val | (DDR_SIZE_2GB << 2), ®s->mcfg); + + /* Clear basement. */ + writel(0, (void *)CFG_SYS_SDRAM_BASE); + + for (sz = DDR_SIZE_2GB - 1; sz > DDR_SIZE_256MB; sz--) { + test_pattern = (test_pattern << 4) + sz; + writel(test_pattern, (void *)(CFG_SYS_SDRAM_BASE + ddr_capacity[sz].size)); + + if (readl((void *)CFG_SYS_SDRAM_BASE) != test_pattern) + break; + } + + /* re-configure ram size to dramc. */ + val = readl(®s->mcfg); + val &= ~(0x7 << 2); + writel(val | ((sz + 1) << 2), ®s->mcfg); + + /* update rfc in ac_timing5 register. */ + val = readl(®s->actime5); + val &= ~(0x3ff); + val |= (ddr_capacity[sz + 1].rfc[IS_DDR4(sdrammc->type)] >> 1); + writel(val, ®s->actime5); + + /* report actual ram base and size to kernel */ + sdrammc->info.base = CFG_SYS_SDRAM_BASE; + sdrammc->info.size = ddr_capacity[sz + 1].size; + + /* reserve the VGA memory */ + sdrammc->info.size -= ast2700_sdrammc_get_vga_mem_size(sdrammc); + + return 0; +} + +static int sdrammc_bist(struct sdrammc *sdrammc, u32 addr, u32 size, u32 cfg, u32 timeout) +{ + struct sdrammc_regs *regs = sdrammc->regs; + u32 val; + u32 err = 0; + + writel(0, ®s->bistcfg); + writel(cfg, ®s->bistcfg); + writel(addr >> 4, ®s->bist_addr); + writel(size >> 4, ®s->bist_size); + writel(0x89abcdef, ®s->bist_patt); + writel(cfg | DRAMC_BISTCFG_START, ®s->bistcfg); + + while (!(readl(®s->intr_status) & DRAMC_IRQSTA_BIST_DONE)) + ; + + writel(DRAMC_IRQSTA_BIST_DONE, ®s->intr_clear); + + val = readl(®s->bist_res); + + if (val & DRAMC_BISTRES_DONE) { + if (val & DRAMC_BISTRES_FAIL) + err++; + } else { + err++; + } + + return err; +} + +static void sdrammc_enable_refresh(struct sdrammc *sdrammc) +{ + struct sdrammc_regs *regs = sdrammc->regs; + + /* refresh update */ + clrbits_le32(®s->refctl, 0x8000); +} + +static void sdrammc_mr_send(struct sdrammc *sdrammc, u32 ctrl, u32 op) +{ + struct sdrammc_regs *regs = sdrammc->regs; + + writel(op, ®s->mrwr); + writel(ctrl | DRAMC_MRCTL_CMD_START, ®s->mrctl); + + while (!(readl(®s->intr_status) & DRAMC_IRQSTA_MR_DONE)) + ; + + writel(DRAMC_IRQSTA_MR_DONE, ®s->intr_clear); +} + +static void sdrammc_config_mrs(struct sdrammc *sdrammc) +{ + const struct sdrammc_ac_timing *ac = sdrammc->ac; + struct sdrammc_regs *regs = sdrammc->regs; + u32 mr0_cas, mr0_rtp, mr0_val; + u32 mr6_tccd_l, mr6_val; + u32 mr2_cwl, mr2_val; + u32 mr1_val; + u32 mr3_val; + u32 mr4_val; + u32 mr5_val; + + if (!IS_DDR4(sdrammc->type)) + return; + + //------------------------------------------------------------------- + // CAS Latency (Table-15) + //------------------------------------------------------------------- + switch (ac->t_cl) { + case 9: + mr0_cas = 0x00; //5'b00000; + break; + case 10: + mr0_cas = 0x01; //5'b00001; + break; + case 11: + mr0_cas = 0x02; //5'b00010; + break; + case 12: + mr0_cas = 0x03; //5'b00011; + break; + case 13: + mr0_cas = 0x04; //5'b00100; + break; + case 14: + mr0_cas = 0x05; //5'b00101; + break; + case 15: + mr0_cas = 0x06; //5'b00110; + break; + case 16: + mr0_cas = 0x07; //5'b00111; + break; + case 18: + mr0_cas = 0x08; //5'b01000; + break; + case 20: + mr0_cas = 0x09; //5'b01001; + break; + case 22: + mr0_cas = 0x0a; //5'b01010; + break; + case 24: + mr0_cas = 0x0b; //5'b01011; + break; + case 23: + mr0_cas = 0x0c; //5'b01100; + break; + case 17: + mr0_cas = 0x0d; //5'b01101; + break; + case 19: + mr0_cas = 0x0e; //5'b01110; + break; + case 21: + mr0_cas = 0x0f; //5'b01111; + break; + case 25: + mr0_cas = 0x10; //5'b10000; + break; + case 26: + mr0_cas = 0x11; //5'b10001; + break; + case 27: + mr0_cas = 0x12; //5'b10010; + break; + case 28: + mr0_cas = 0x13; //5'b10011; + break; + case 30: + mr0_cas = 0x15; //5'b10101; + break; + case 32: + mr0_cas = 0x17; //5'b10111; + break; + } + + //------------------------------------------------------------------- + // WR and RTP (Table-14) + //------------------------------------------------------------------- + switch (ac->t_rtp) { + case 5: + mr0_rtp = 0x0; //4'b0000; + break; + case 6: + mr0_rtp = 0x1; //4'b0001; + break; + case 7: + mr0_rtp = 0x2; //4'b0010; + break; + case 8: + mr0_rtp = 0x3; //4'b0011; + break; + case 9: + mr0_rtp = 0x4; //4'b0100; + break; + case 10: + mr0_rtp = 0x5; //4'b0101; + break; + case 12: + mr0_rtp = 0x6; //4'b0110; + break; + case 11: + mr0_rtp = 0x7; //4'b0111; + break; + case 13: + mr0_rtp = 0x8; //4'b1000; + break; + } + + //------------------------------------------------------------------- + // CAS Write Latency (Table-21) + //------------------------------------------------------------------- + switch (ac->t_cwl) { + case 9: + mr2_cwl = 0x0; // 3'b000; // 1600 + break; + case 10: + mr2_cwl = 0x1; // 3'b001; // 1866 + break; + case 11: + mr2_cwl = 0x2; // 3'b010; // 2133 + break; + case 12: + mr2_cwl = 0x3; // 3'b011; // 2400 + break; + case 14: + mr2_cwl = 0x4; // 3'b100; // 2666 + break; + case 16: + mr2_cwl = 0x5; // 3'b101; // 2933/3200 + break; + case 18: + mr2_cwl = 0x6; // 3'b110; + break; + case 20: + mr2_cwl = 0x7; // 3'b111; + break; + } + + //------------------------------------------------------------------- + // tCCD_L and tDLLK + //------------------------------------------------------------------- + switch (ac->t_ccd_l) { + case 4: + mr6_tccd_l = 0x0; //3'b000; // rate <= 1333 + break; + case 5: + mr6_tccd_l = 0x1; //3'b001; // 1333 < rate <= 1866 + break; + case 6: + mr6_tccd_l = 0x2; //3'b010; // 1866 < rate <= 2400 + break; + case 7: + mr6_tccd_l = 0x3; //3'b011; // 2400 < rate <= 2666 + break; + case 8: + mr6_tccd_l = 0x4; //3'b100; // 2666 < rate <= 3200 + break; + } + + /* + * mr0_val = + * mr0_rtp[3], // 13 + * mr0_cas[4], // 12 + * mr0_rtp[2:0], // 13,11-9: WR and RTP + * 1'b0, // 8: DLL reset + * 1'b0, // 7: TM + * mr0_cas[3:1], // 6-4,2: CAS latency + * 1'b0, // 3: sequential + * mr0_cas[0], + * 2'b00 // 1-0: burst length + */ + mr0_val = ((mr0_cas & 0x1) << 2) | + (((mr0_cas >> 1) & 0x7) << 4) | + (((mr0_cas >> 4) & 0x1) << 12) | + ((mr0_rtp & 0x7) << 9) | + (((mr0_rtp >> 3) & 0x1) << 13); + + /* + * 3'b2 //[10:8]: rtt_nom, 000:disable,001:rzq/4,010:rzq/2,011:rzq/6,100:rzq/1,101:rzq/5,110:rzq/3,111:rzq/7 + * 1'b0 //[7]: write leveling enable + * 2'b0 //[6:5]: reserved + * 2'b0 //[4:3]: additive latency + * 2'b0 //[2:1]: output driver impedance + * 1'b1 //[0]: enable dll + */ + mr1_val = 0x201; + + /* + * [10:9]: rtt_wr, 00:dynamic odt off, 01:rzq/2, 10:rzq/1, 11: hi-z + * [8]: 0 + */ + mr2_val = ((mr2_cwl & 0x7) << 3) | 0x200; + + mr3_val = 0; + + mr4_val = 0; + + /* + * mr5_val = { + * 1'b0, // 13: RFU + * 1'b0, // 12: read DBI + * 1'b0, // 11: write DBI + * 1'b1, // 10: Data mask + * 1'b0, // 9: C/A parity persistent error + * 3'b000, // 8-6: RTT_PARK (disable) + * 1'b1, // 5: ODT input buffer during power down mode + * 1'b0, // 4: C/A parity status + * 1'b0, // 3: CRC error clear + * 3'b0 // 2-0: C/A parity latency mode + * }; + */ + mr5_val = 0x420; + + /* + * mr6_val = { + * 1'b0, // 13, 9-8: RFU + * mr6_tccd_l[2:0], // 12-10: tCCD_L + * 2'b0, // 13, 9-8: RFU + * 1'b0, // 7: VrefDQ training enable + * 1'b0, // 6: VrefDQ training range + * 6'b0 // 5-0: VrefDQ training value + * }; + */ + mr6_val = ((mr6_tccd_l & 0x7) << 10); + + writel((mr1_val << 16) + mr0_val, ®s->mr01); + writel((mr3_val << 16) + mr2_val, ®s->mr23); + writel((mr5_val << 16) + mr4_val, ®s->mr45); + writel(mr6_val, ®s->mr67); + + /* Power-up initialization sequence */ + sdrammc_mr_send(sdrammc, MR_ADDR(3), 0); + sdrammc_mr_send(sdrammc, MR_ADDR(6), 0); + sdrammc_mr_send(sdrammc, MR_ADDR(5), 0); + sdrammc_mr_send(sdrammc, MR_ADDR(4), 0); + sdrammc_mr_send(sdrammc, MR_ADDR(2), 0); + sdrammc_mr_send(sdrammc, MR_ADDR(1), 0); + sdrammc_mr_send(sdrammc, MR_ADDR(0), 0); +} + +static void sdrammc_exit_self_refresh(struct sdrammc *sdrammc) +{ + struct sdrammc_regs *regs = sdrammc->regs; + + /* exit self-refresh after phy init */ + setbits_le32(®s->mctl, DRAMC_MCTL_SELF_REF_START); + + /* query if self-ref done */ + while (!(readl(®s->intr_status) & DRAMC_IRQSTA_REF_DONE)) + ; + + /* clear status */ + writel(DRAMC_IRQSTA_REF_DONE, ®s->intr_clear); + udelay(1); +} + +/* user-customized functions for the vendor PHY init code */ +#define DWC_PHY_IMEM_OFST 0x50000 +#define DWC_PHY_DMEM_OFST 0x58000 +#define DWC_PHY_MB_START_STREAM_MSG 0x8 +#define DWC_PHY_MB_TRAIN_SUCCESS 0x7 +#define DWC_PHY_MB_TRAIN_FAIL 0xff + +#define dwc_ddrphy_apb_wr(addr, data) \ + writew((data), sdrammc->phy + ((addr) << 1)) + +#define dwc_ddrphy_apb_rd(addr) \ + readw(sdrammc->phy + ((addr) << 1)) + +#define dwc_ddrphy_apb_wr_32b(addr, data) \ + writel((data), sdrammc->phy + ((addr) << 1)) + +#define dwc_ddrphy_apb_rd_32b(addr) \ + readl(sdrammc->phy + ((addr) << 1)) + +void dwc_get_mailbox(struct sdrammc *sdrammc, const int mode, u32 *mbox) +{ + u32 val; + + /* 1. Poll the UctWriteProtShadow, looking for a 0 */ + while (dwc_ddrphy_apb_rd(0xd0004) & BIT(0)) + ; + + /* 2. When a 0 is seen, read the UctWriteOnlyShadow register to get the major message number. */ + *mbox = dwc_ddrphy_apb_rd(0xd0032) & 0xffff; + + /* 3. If reading a streaming or SMBus message, also read the UctDatWriteOnlyShadow register. */ + if (mode) { + val = (dwc_ddrphy_apb_rd(0xd0034)) & 0xffff; + *mbox |= (val << 16); + } + + /* 4. Write the DctWriteProt to 0 to acknowledge the reception of the message */ + dwc_ddrphy_apb_wr(0xd0031, 0); + + /* 5. Poll the UctWriteProtShadow, looking for a 1 */ + while (!(dwc_ddrphy_apb_rd(0xd0004) & BIT(0))) + ; + + /* 6. When a 1 is seen, write the DctWriteProt to 1 to complete the protocol */ + dwc_ddrphy_apb_wr(0xd0031, 1); +} + +uint32_t dwc_readMsgBlock(struct sdrammc *sdrammc, const u32 addr_half) +{ + u32 data_word; + + data_word = dwc_ddrphy_apb_rd_32b((addr_half >> 1) << 1); + + if (addr_half & 0x1) + data_word = data_word >> 16; + else + data_word &= 0xffff; + + return data_word; +} + +int dwc_ddrphy_phyinit_userCustom_H_readMsgBlock(struct sdrammc *sdrammc, int train2D) +{ + u32 msg; + + if (IS_DDR4(sdrammc->type)) { + /* DWC_PHY_DDR4_MB_RESULT */ + msg = dwc_readMsgBlock(sdrammc, 0x5800a); + if (msg & 0xff) + debug("%s: Training Failure index (0x%x)\n", __func__, msg); + else + debug("%s: %dD Training Passed\n", __func__, train2D ? 2 : 1); + } else { + /* DWC_PHY_DDR5_MB_RESULT */ + msg = dwc_readMsgBlock(sdrammc, 0x58007); + if (msg & 0xff00) + debug("%s: Training Failure index (0x%x)\n", __func__, msg); + else + debug("%s: DDR5 1D/2D Training Passed\n", __func__); + + /* DWC_PHY_DDR5_MB_RESULT_ADR */ + msg = dwc_readMsgBlock(sdrammc, 0x5800a); + debug("%s: Result Address Offset (0x%x)\n", __func__, msg); + } + + return 0; +} + +void dwc_ddrphy_phyinit_userCustom_A_bringupPower(void) +{ + /* do nothing */ +} + +void dwc_ddrphy_phyinit_userCustom_B_startClockResetPhy(struct sdrammc *sdrammc) +{ + struct sdrammc_regs *regs = sdrammc->regs; + + /* + * 1. Drive PwrOkIn to 0. Note: Reset, DfiClk, and APBCLK can be X. + * 2. Start DfiClk and APBCLK + * 3. Drive Reset to 1 and PRESETn_APB to 0. + * Note: The combination of PwrOkIn=0 and Reset=1 signals a cold reset to the PHY. + */ + writel(DRAMC_MCTL_PHY_RESET, ®s->mctl); + udelay(2); + + /* + * 5. Drive PwrOkIn to 1. Once the PwrOkIn is asserted (and Reset is still asserted), + * DfiClk synchronously switches to any legal input frequency. + */ + writel(DRAMC_MCTL_PHY_RESET | DRAMC_MCTL_PHY_POWER_ON, ®s->mctl); + udelay(2); + + /* + * 7. Drive Reset to 0. Note: All DFI and APB inputs must be driven at valid reset states + * before the deassertion of Reset. + */ + writel(DRAMC_MCTL_PHY_POWER_ON, ®s->mctl); + udelay(2); + + /* + * 9. Drive PRESETn_APB to 1 to de-assert reset on the ABP bus. + * 10. The PHY is now in the reset state and is ready to accept APB transactions. + */ +} + +void dwc_ddrphy_phyinit_userCustom_overrideUserInput(void) +{ + /* do nothing */ +} + +void dwc_ddrphy_phyinit_userCustom_customPostTrain(void) +{ + /* do nothing */ +} + +void dwc_ddrphy_phyinit_userCustom_E_setDfiClk(struct sdrammc *sdrammc) +{ + dwc_ddrphy_apb_wr(0xd0031, 1); /* DWC_DCTWRITEPROT */ + dwc_ddrphy_apb_wr(0xd0033, 1); /* DWC_UCTWRITEPROT */ +} + +void dwc_ddrphy_phyinit_userCustom_G_waitFwDone(struct sdrammc *sdrammc) +{ + u32 mbox, msg = 0; + + while (msg != DWC_PHY_MB_TRAIN_SUCCESS && msg != DWC_PHY_MB_TRAIN_FAIL) { + dwc_get_mailbox(sdrammc, 0, &mbox); + msg = mbox & 0xffff; + } +} + +void dwc_ddrphy_phyinit_userCustom_J_enterMissionMode(struct sdrammc *sdrammc) +{ + struct sdrammc_regs *regs = sdrammc->regs; + u32 val; + + /* + * 1. Set the PHY input clocks to the desired frequency. + * 2. Initialize the PHY to mission mode by performing DFI Initialization. + * Please see the DFI specification for more information. See the DFI frequency bus encoding in section <XXX>. + * Note: The PHY training firmware initializes the DRAM state. if skip + * training is used, the DRAM state is not initialized. + */ + + writel(0xffffffff, (void *)®s->intr_mask); + + writel(0x0, (void *)®s->dcfg); + + if (!IS_DDR4(sdrammc->type)) { + dwc_ddrphy_apb_wr(0xd0000, 0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + dwc_ddrphy_apb_wr(0x20240, 0x3900); /* DWC_DDRPHYA_MASTER0_base0_D5ACSMPtr0lat0 */ + dwc_ddrphy_apb_wr(0x900da, 8); /* DWC_DDRPHYA_INITENG0_base0_SequenceReg0b59s0 */ + dwc_ddrphy_apb_wr(0xd0000, 1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + } + + /* phy init start */ + val = readl((void *)®s->mctl); + val = val | DRAMC_MCTL_PHY_INIT_START; + writel(val, (void *)®s->mctl); + + /* wait phy complete */ + while (1) { + val = readl(®s->intr_status) & DRAMC_IRQSTA_PHY_INIT_DONE; + if (val == DRAMC_IRQSTA_PHY_INIT_DONE) + break; + } + + writel(0xffff, (void *)®s->intr_clear); + + while (readl((void *)®s->intr_status)) + ; + + if (!IS_DDR4(sdrammc->type)) { + dwc_ddrphy_apb_wr(0xd0000, 0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + dwc_ddrphy_apb_wr(0x20240, 0x4300); /* DWC_DDRPHYA_MASTER0_base0_D5ACSMPtr0lat0 */ + dwc_ddrphy_apb_wr(0x900da, 0); /* DWC_DDRPHYA_INITENG0_base0_SequenceReg0b59s0 */ + dwc_ddrphy_apb_wr(0xd0000, 1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + } +} + +int dwc_ddrphy_phyinit_userCustom_D_loadIMEM(struct sdrammc *sdrammc, const int train2D) +{ + u32 imem_ofst, imem_size; + u32 pb_type; + + if (IS_DDR4(sdrammc->type)) + pb_type = (train2D) ? PBT_DDR4_2D_PMU_TRAIN_IMEM : PBT_DDR4_PMU_TRAIN_IMEM; + else + pb_type = PBT_DDR5_PMU_TRAIN_IMEM; + + fmc_hdr_get_prebuilt(pb_type, &imem_ofst, &imem_size); + + memcpy(sdrammc->phy + (DWC_PHY_IMEM_OFST << 1), + (void *)(0x20000000 + imem_ofst), imem_size); + + return 0; +} + +int dwc_ddrphy_phyinit_userCustom_F_loadDMEM(struct sdrammc *sdrammc, + const int pState, const int train2D) +{ + u32 dmem_ofst, dmem_size; + u32 pb_type; + + if (IS_DDR4(sdrammc->type)) + pb_type = (train2D) ? PBT_DDR4_2D_PMU_TRAIN_DMEM : PBT_DDR4_PMU_TRAIN_DMEM; + else + pb_type = PBT_DDR5_PMU_TRAIN_DMEM; + + fmc_hdr_get_prebuilt(pb_type, &dmem_ofst, &dmem_size); + + memcpy(sdrammc->phy + (DWC_PHY_DMEM_OFST << 1), + (void *)(0x20000000 + dmem_ofst), dmem_size); + + return 0; +} + +static void sdrammc_dwc_phy_init(struct sdrammc *sdrammc) +{ + /* enable ddr phy free-run clock */ + writel(SCU0_CLKGATE1_CLR_DDRPHY, sdrammc->scu0 + SCU0_CLKGATE1_CLR); + + /* include the vendor-provided PHY init code */ + if (IS_DDR4(sdrammc->type)) { + #include "dwc_ddrphy_phyinit_ddr4-3200-nodimm-train2D.c" + } else { + #include "dwc_ddrphy_phyinit_ddr5-3200-nodimm-train2D.c" + } +} + +static void sdrammc_config_ac_timing(struct sdrammc *sdrammc) +{ + const struct sdrammc_ac_timing *ac = sdrammc->ac; + struct sdrammc_regs *regs = sdrammc->regs; + u32 actime; + +#define ACTIME1(ccd, rrd_l, rrd, mrd) \ + (((ccd) << 24) | \ + (((rrd_l) >> 1) << 16) | \ + (((rrd) >> 1) << 8) | \ + ((mrd) >> 1)) + +#define ACTIME2(faw, rp, ras, rcd) \ + ((((faw) >> 1) << 24) | \ + (((rp) >> 1) << 16) | \ + (((ras) >> 1) << 8) | \ + ((rcd) >> 1)) + +#define ACTIME3(wtr, rtw, wtp, rtp) \ + ((((wtr) >> 1) << 24) | \ + (((rtw) >> 1) << 16) | \ + (((wtp) >> 1) << 8) | \ + ((rtp) >> 1)) + +#define ACTIME4(wtr_a, wtr_l) \ + ((((wtr_a) >> 1) << 8) | \ + ((wtr_l) >> 1)) + +#define ACTIME5(refsbrd, rfcsb, rfc) \ + ((((refsbrd) >> 1) << 20) | \ + (((rfcsb) >> 1) << 10) | \ + ((rfc) >> 1)) + +#define ACTIME6(cshsr, pd, xp, cksre) \ + ((((cshsr) >> 1) << 24) | \ + (((pd) >> 1) << 16) | \ + (((xp) >> 1) << 8) | \ + ((cksre) >> 1)) + +#define ACTIME7(zqcs, dllk) \ + ((((zqcs) >> 1) << 10) | \ + ((dllk) >> 1)) + + actime = ACTIME1(ac->t_ccd_l, ac->t_rrd_l, ac->t_rrd, ac->t_mrd); + writel(actime, ®s->actime1); + + actime = ACTIME2(ac->t_faw, ac->t_rp, ac->t_ras, ac->t_rcd); + writel(actime, ®s->actime2); + + actime = ACTIME3(ac->t_cwl + ac->t_bl / 2 + ac->t_wtr, + ac->t_cl - ac->t_cwl + (ac->t_bl / 2) + 2, + ac->t_cwl + ac->t_bl / 2 + ac->t_wtp, + ac->t_rtp); + writel(actime, ®s->actime3); + + actime = ACTIME4(ac->t_cwl + ac->t_bl / 2 + ac->t_wtr_a, + ac->t_cwl + ac->t_bl / 2 + ac->t_wtr_l); + writel(actime, ®s->actime4); + + actime = ACTIME5(ac->t_refsbrd, ac->t_rfcsb, ac->t_rfc); + writel(actime, ®s->actime5); + + actime = ACTIME6(ac->t_cshsr, ac->t_pd, ac->t_xp, ac->t_cksre); + writel(actime, ®s->actime6); + + actime = ACTIME7(ac->t_zq, ac->t_dllk); + writel(actime, ®s->actime7); +} + +static void sdrammc_config_registers(struct sdrammc *sdrammc) +{ + const struct sdrammc_ac_timing *ac = sdrammc->ac; + struct sdrammc_regs *regs = sdrammc->regs; + u32 reg; + + u32 dram_size = 5; + u32 t_phy_wrdata; + u32 t_phy_wrlat; + u32 t_phy_rddata_en; + u32 t_phy_odtlat; + u32 t_phy_odtext; + + if (IS_DDR4(sdrammc->type)) { + t_phy_wrlat = ac->t_cwl - 5 - 4; + t_phy_rddata_en = ac->t_cl - 5 - 4; + t_phy_wrdata = 2; + t_phy_odtlat = ac->t_cwl - 5 - 4; + t_phy_odtext = 0; + } else { + t_phy_wrlat = ac->t_cwl - 13 - 3; + t_phy_rddata_en = ac->t_cl - 13 - 3; + t_phy_wrdata = 6; + t_phy_odtlat = 0; + t_phy_odtext = 0; + } + + writel(0x20 + (dram_size << 2) + !!!IS_DDR4(sdrammc->type), ®s->mcfg); + + reg = (t_phy_odtext << 20) + (t_phy_odtlat << 16) + + (t_phy_rddata_en << 10) + (t_phy_wrdata << 6) + + t_phy_wrlat; + writel(reg, ®s->dfi_timing); + writel(0, ®s->dctl); + + writel(0x40b48200, ®s->refctl); + + writel(0x42aa1800, ®s->zqctl); + + writel(0, ®s->arbctl); + + if (!IS_DDR4(sdrammc->type)) + writel(0, ®s->refmng_ctl); + + writel(0xffffffff, ®s->intr_mask); +} + +static void sdrammc_init(struct sdrammc *sdrammc) +{ + u32 reg; + + reg = readl(sdrammc->scu1 + SCU1_HWSTRAP1); + + if (reg & SCU1_HWSTRAP1_DDR4) { + if (IS_ENABLED(CONFIG_ASPEED_DDR_1600)) + sdrammc->type = DDR4_1600; + else if (IS_ENABLED(CONFIG_ASPEED_DDR_2400)) + sdrammc->type = DDR4_2400; + else if (IS_ENABLED(CONFIG_ASPEED_DDR_3200)) + sdrammc->type = DDR4_3200; + } else { + sdrammc->type = DDR5_3200; + } + + sdrammc->ac = &ac_table[sdrammc->type]; + + sdrammc_config_ac_timing(sdrammc); + sdrammc_config_registers(sdrammc); +} + +static int ast2700_sdrammc_probe(struct udevice *dev) +{ + struct sdrammc *sdrammc = dev_get_priv(dev); + struct sdrammc_regs *regs = sdrammc->regs; + u32 bistcfg; + u32 reg; + int rc; + + /* skip DRAM init if already done */ + reg = readl(sdrammc->scu0 + SCU0_VGA0_SCRATCH); + if (reg & SCU0_VGA0_SCRATCH_DRAM_INIT) + goto out; + + /* unlock DRAM controller */ + writel(DRAMC_UNLK_KEY, ®s->prot_key); + + sdrammc_init(sdrammc); + + sdrammc_dwc_phy_init(sdrammc); + + sdrammc_exit_self_refresh(sdrammc); + + sdrammc_config_mrs(sdrammc); + + sdrammc_enable_refresh(sdrammc); + + bistcfg = FIELD_PREP(DRAMC_BISTCFG_PMODE, BIST_PMODE_CRC) | + FIELD_PREP(DRAMC_BISTCFG_BMODE, BIST_BMODE_RW_SWITCH) | + DRAMC_BISTCFG_ENABLE; + + rc = sdrammc_bist(sdrammc, 0, 0x10000, bistcfg, 0x200000); + if (rc) { + debug("bist test failed, type=%d\n", sdrammc->type); + return rc; + } + + /* set DRAM init flag */ + reg |= SCU0_VGA0_SCRATCH_DRAM_INIT; + writel(reg, sdrammc->scu0 + SCU0_VGA0_SCRATCH); + +out: + sdrammc_calc_size(sdrammc); + + return 0; +} + +static int ast2700_sdrammc_of_to_plat(struct udevice *dev) +{ + struct sdrammc *sdrammc = dev_get_priv(dev); + u32 phandle; + ofnode node; + int rc; + + sdrammc->regs = (struct sdrammc_regs *)devfdt_get_addr_index(dev, 0); + if (sdrammc->regs == (void *)FDT_ADDR_T_NONE) { + debug("cannot map DRAM register\n"); + return -ENODEV; + } + + sdrammc->phy = (void *)devfdt_get_addr_index(dev, 1); + if (sdrammc->phy == (void *)FDT_ADDR_T_NONE) { + debug("cannot map PHY memory\n"); + return -ENODEV; + } + + rc = ofnode_read_u32(dev_ofnode(dev), "aspeed,scu0", &phandle); + if (rc) { + debug("cannot find SCU0 handle\n"); + return -ENODEV; + } + + node = ofnode_get_by_phandle(phandle); + if (!ofnode_valid(node)) { + debug("cannot get SCU0 node\n"); + return -ENODEV; + } + + sdrammc->scu0 = (void *)ofnode_get_addr(node); + if (sdrammc->scu0 == (void *)FDT_ADDR_T_NONE) { + debug("cannot map SCU0 register\n"); + return -ENODEV; + } + + rc = ofnode_read_u32(dev_ofnode(dev), "aspeed,scu1", &phandle); + if (rc) { + debug("cannot find SCU1 handle\n"); + return -ENODEV; + } + + node = ofnode_get_by_phandle(phandle); + if (!ofnode_valid(node)) { + debug("cannot get SCU1 node\n"); + return -ENODEV; + } + + sdrammc->scu1 = (void *)ofnode_get_addr(node); + if (sdrammc->scu1 == (void *)FDT_ADDR_T_NONE) { + debug("cannot map SCU1 register\n"); + return -ENODEV; + } + + return 0; +} + +static int ast2700_sdrammc_get_info(struct udevice *dev, struct ram_info *info) +{ + struct sdrammc *sdrammc = dev_get_priv(dev); + + *info = sdrammc->info; + + return 0; +} + +static struct ram_ops ast2700_sdrammc_ops = { + .get_info = ast2700_sdrammc_get_info, +}; + +static const struct udevice_id ast2700_sdrammc_ids[] = { + { .compatible = "aspeed,ast2700-sdrammc" }, + { } +}; + +U_BOOT_DRIVER(sdrammc_ast2700) = { + .name = "aspeed_ast2700_sdrammc", + .id = UCLASS_RAM, + .of_match = ast2700_sdrammc_ids, + .ops = &ast2700_sdrammc_ops, + .of_to_plat = ast2700_sdrammc_of_to_plat, + .probe = ast2700_sdrammc_probe, + .priv_auto = sizeof(struct sdrammc), +}; diff --git a/drivers/ram/k3-ddrss/lpddr4.c b/drivers/ram/k3-ddrss/lpddr4.c index 11ef242a37b..9f9abfeca48 100644 --- a/drivers/ram/k3-ddrss/lpddr4.c +++ b/drivers/ram/k3-ddrss/lpddr4.c @@ -155,10 +155,11 @@ u32 lpddr4_start(const lpddr4_privatedata *pd) u32 result = 0U; result = lpddr4_startsf(pd); - if (result == (u32)0) { + if (result == (u32)0) result = lpddr4_enablepiinitiator(pd); + if (result == (u32)0) result = lpddr4_startsequencecontroller(pd); - } + return result; } diff --git a/drivers/rtc/rv3028.c b/drivers/rtc/rv3028.c index 9f63afc14a8..b14d2a246ff 100644 --- a/drivers/rtc/rv3028.c +++ b/drivers/rtc/rv3028.c @@ -12,6 +12,9 @@ #include <dm.h> #include <i2c.h> #include <rtc.h> +#include <dm/device_compat.h> +#include <linux/delay.h> +#include <power/regulator.h> #define RV3028_SEC 0x00 #define RV3028_MIN 0x01 @@ -78,6 +81,12 @@ #define RTC_RV3028_LEN 7 +#define VDD_START_TIME_US 200000 + +struct rv3028_priv { + struct udevice *vdd; +}; + static int rv3028_rtc_get(struct udevice *dev, struct rtc_time *tm) { u8 regs[RTC_RV3028_LEN]; @@ -180,6 +189,28 @@ static int rv3028_rtc_write8(struct udevice *dev, unsigned int reg, int val) static int rv3028_probe(struct udevice *dev) { + struct rv3028_priv *priv = dev_get_priv(dev); + int ret; + + if (IS_ENABLED(CONFIG_DM_REGULATOR)) { + ret = device_get_supply_regulator(dev, "vdd-supply", &priv->vdd); + if (ret && ret != -ENOENT) { + dev_err(dev, "Warning: cannot get VDD supply\n"); + return ret; + } + + if (priv->vdd) { + ret = regulator_set_enable_if_allowed(priv->vdd, true); + if (ret) { + dev_err(dev, "failed to enable vdd-supply\n"); + return ret; + } + + /* We must wait Tstart = 0.2s before access to I2C */ + udelay(VDD_START_TIME_US); + } + } + i2c_set_chip_flags(dev, DM_I2C_CHIP_RD_ADDRESS | DM_I2C_CHIP_WR_ADDRESS); @@ -205,4 +236,5 @@ U_BOOT_DRIVER(rtc_rv3028) = { .probe = rv3028_probe, .of_match = rv3028_rtc_ids, .ops = &rv3028_rtc_ops, + .priv_auto = sizeof(struct rv3028_priv), }; diff --git a/drivers/soc/qcom/cmd-db.c b/drivers/soc/qcom/cmd-db.c index 08736ea936a..67be18e89f4 100644 --- a/drivers/soc/qcom/cmd-db.c +++ b/drivers/soc/qcom/cmd-db.c @@ -6,6 +6,7 @@ #define pr_fmt(fmt) "cmd-db: " fmt +#include <asm/system.h> #include <dm.h> #include <dm/ofnode.h> #include <dm/device_compat.h> @@ -141,7 +142,7 @@ static int cmd_db_get_header(const char *id, const struct entry_header **eh, ent = rsc_to_entry_header(rsc_hdr); for (j = 0; j < le16_to_cpu(rsc_hdr->cnt); j++, ent++) { - if (memcmp(ent->id, query, sizeof(ent->id)) == 0) { + if (strncmp(ent->id, query, sizeof(ent->id)) == 0) { if (eh) *eh = ent; if (rh) @@ -182,9 +183,10 @@ u32 cmd_db_read_addr(const char *id) } EXPORT_SYMBOL_GPL(cmd_db_read_addr); -int cmd_db_bind(struct udevice *dev) +static int cmd_db_bind(struct udevice *dev) { void __iomem *base; + fdt_size_t size; ofnode node; if (cmd_db_header) @@ -194,12 +196,15 @@ int cmd_db_bind(struct udevice *dev) debug("%s(%s)\n", __func__, ofnode_get_name(node)); - base = (void __iomem *)ofnode_get_addr(node); + base = (void __iomem *)ofnode_get_addr_size(node, "reg", &size); if ((fdt_addr_t)base == FDT_ADDR_T_NONE) { log_err("%s: Failed to read base address\n", __func__); return -ENOENT; } + /* On SM8550/SM8650 and newer SoCs cmd-db might not be mapped */ + mmu_map_region((phys_addr_t)base, (phys_size_t)size, false); + cmd_db_header = base; if (!cmd_db_magic_matches(cmd_db_header)) { log_err("%s: Invalid Command DB Magic\n", __func__); diff --git a/drivers/soc/qcom/rpmh-rsc.c b/drivers/soc/qcom/rpmh-rsc.c index 61fb2e69558..aee9e55194e 100644 --- a/drivers/soc/qcom/rpmh-rsc.c +++ b/drivers/soc/qcom/rpmh-rsc.c @@ -294,6 +294,48 @@ static void __tcs_buffer_write(struct rsc_drv *drv, int tcs_id, int cmd_id, } /** + * __tcs_set_trigger() - Start xfer on a TCS or unset trigger on a borrowed TCS + * @drv: The controller. + * @tcs_id: The global ID of this TCS. + * @trigger: If true then untrigger/retrigger. If false then just untrigger. + * + * In the normal case we only ever call with "trigger=true" to start a + * transfer. That will un-trigger/disable the TCS from the last transfer + * then trigger/enable for this transfer. + * + * If we borrowed a wake TCS for an active-only transfer we'll also call + * this function with "trigger=false" to just do the un-trigger/disable + * before using the TCS for wake purposes again. + * + * Note that the AP is only in charge of triggering active-only transfers. + * The AP never triggers sleep/wake values using this function. + */ +static void __tcs_set_trigger(struct rsc_drv *drv, int tcs_id, bool trigger) +{ + u32 enable; + u32 reg = drv->regs[RSC_DRV_CONTROL]; + + /* + * HW req: Clear the DRV_CONTROL and enable TCS again + * While clearing ensure that the AMC mode trigger is cleared + * and then the mode enable is cleared. + */ + enable = read_tcs_reg(drv, reg, tcs_id); + enable &= ~TCS_AMC_MODE_TRIGGER; + write_tcs_reg_sync(drv, reg, tcs_id, enable); + enable &= ~TCS_AMC_MODE_ENABLE; + write_tcs_reg_sync(drv, reg, tcs_id, enable); + + if (trigger) { + /* Enable the AMC mode on the TCS and then trigger the TCS */ + enable = TCS_AMC_MODE_ENABLE; + write_tcs_reg_sync(drv, reg, tcs_id, enable); + enable |= TCS_AMC_MODE_TRIGGER; + write_tcs_reg(drv, reg, tcs_id, enable); + } +} + +/** * rpmh_rsc_send_data() - Write / trigger active-only message. * @drv: The controller. * @msg: The data to be sent. @@ -348,6 +390,7 @@ int rpmh_rsc_send_data(struct rsc_drv *drv, const struct tcs_request *msg) * of __tcs_set_trigger() below. */ __tcs_buffer_write(drv, tcs_id, 0, msg); + __tcs_set_trigger(drv, tcs_id, true); /* U-Boot: Now wait for the TCS to be cleared, indicating that we're done */ for (i = 0; i < USEC_PER_SEC; i++) { diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c index 82049872d05..19bd06cf872 100644 --- a/drivers/spi/davinci_spi.c +++ b/drivers/spi/davinci_spi.c @@ -129,9 +129,6 @@ static int davinci_spi_read(struct davinci_spi_slave *ds, unsigned int len, while (readl(&ds->regs->buf) & SPIBUF_TXFULL_MASK) ; - /* preload the TX buffer to avoid clock starvation */ - writel(data1_reg_val, &ds->regs->dat1); - /* keep reading 1 byte until only 1 byte left */ while ((len--) > 1) *rxp++ = davinci_spi_xfer_data(ds, data1_reg_val); @@ -159,12 +156,6 @@ static int davinci_spi_write(struct davinci_spi_slave *ds, unsigned int len, while (readl(&ds->regs->buf) & SPIBUF_TXFULL_MASK) ; - /* preload the TX buffer to avoid clock starvation */ - if (len > 2) { - writel(data1_reg_val | *txp++, &ds->regs->dat1); - len--; - } - /* keep writing 1 byte until only 1 byte left */ while ((len--) > 1) davinci_spi_xfer_data(ds, data1_reg_val | *txp++); diff --git a/drivers/spi/renesas_rpc_spi.c b/drivers/spi/renesas_rpc_spi.c index e6b602cf7b4..f1e6f9f4e01 100644 --- a/drivers/spi/renesas_rpc_spi.c +++ b/drivers/spi/renesas_rpc_spi.c @@ -145,6 +145,12 @@ #define RPC_PHYCNT_WBUF BIT(2) #define RPC_PHYCNT_MEM(v) (((v) & 0x3) << 0) +#define RPCIF_PHYOFFSET1 0x0080 /* R/W */ +#define RPCIF_PHYOFFSET1_DDRTMG(v) (((v) & 0x3) << 28) + +#define RPCIF_PHYOFFSET2 0x0084 /* R/W */ +#define RPCIF_PHYOFFSET2_OCTTMG(v) (((v) & 0x7) << 8) + #define RPC_PHYINT 0x0088 /* R/W */ #define RPC_PHYINT_RSTEN BIT(18) #define RPC_PHYINT_WPEN BIT(17) @@ -227,6 +233,12 @@ static int rpc_spi_claim_bus(struct udevice *dev, bool manual) struct udevice *bus = dev->parent; struct rpc_spi_priv *priv = dev_get_priv(bus); + setbits_le32(priv->regs + RPCIF_PHYOFFSET1, + RPCIF_PHYOFFSET1_DDRTMG(3)); + clrsetbits_le32(priv->regs + RPCIF_PHYOFFSET2, + RPCIF_PHYOFFSET2_OCTTMG(7), + RPCIF_PHYOFFSET2_OCTTMG(4)); + /* NOTE: The 0x260 are undocumented bits, but they must be set. */ writel(RPC_PHYCNT_CAL | rpc_spi_get_strobe_delay() | 0x260, priv->regs + RPC_PHYCNT); @@ -277,24 +289,24 @@ static int rpc_spi_mem_exec_op(struct spi_slave *spi, writel(RPC_DRCMR_CMD(op->cmd.opcode), priv->regs + RPC_DRCMR); smenr |= RPC_DRENR_CDE; - writel(0, priv->regs + RPC_DREAR); if (op->addr.nbytes == 4) { writel(RPC_DREAR_EAV(offset >> 25) | RPC_DREAR_EAC(1), priv->regs + RPC_DREAR); smenr |= RPC_DRENR_ADE(0xF); } else if (op->addr.nbytes == 3) { + writel(0, priv->regs + RPC_DREAR); smenr |= RPC_DRENR_ADE(0x7); } else { + writel(0, priv->regs + RPC_DREAR); smenr |= RPC_DRENR_ADE(0); } - writel(0, priv->regs + RPC_DRDMCR); - if (op->dummy.nbytes) { - writel(8 * op->dummy.nbytes - 1, priv->regs + RPC_DRDMCR); + if (op->dummy.nbytes) smenr |= RPC_DRENR_DME; - } + writel(8 * op->dummy.nbytes - 1, priv->regs + RPC_DRDMCR); writel(0, priv->regs + RPC_DROPR); + writel(0, priv->regs + RPC_DRDRENR); writel(smenr, priv->regs + RPC_DRENR); memcpy_fromio(din, (void *)(priv->extr + offset), op->data.nbytes); @@ -453,6 +465,7 @@ static const struct dm_spi_ops rpc_spi_ops = { static const struct udevice_id rpc_spi_ids[] = { { .compatible = "renesas,r7s72100-rpc-if" }, { .compatible = "renesas,rcar-gen3-rpc-if" }, + { .compatible = "renesas,rcar-gen4-rpc-if" }, { } }; diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index 6b1de82ae38..cb6fc0e7fda 100644 --- a/drivers/timer/Kconfig +++ b/drivers/timer/Kconfig @@ -106,6 +106,12 @@ config AST_TIMER This is mostly because they all share several registers which makes it difficult to completely separate them. +config AST_IBEX_TIMER + bool "Aspeed ast2700 Ibex timer" + depends on TIMER + help + Select this to enable a timer support for the Ibex RV32-based MCUs in AST2700. + config ATCPIT100_TIMER bool "ATCPIT100 timer support" depends on TIMER diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile index fb95c8899e3..fec4af392e6 100644 --- a/drivers/timer/Makefile +++ b/drivers/timer/Makefile @@ -9,6 +9,7 @@ obj-$(CONFIG_$(SPL_)ANDES_PLMT_TIMER) += andes_plmt_timer.o obj-$(CONFIG_ARC_TIMER) += arc_timer.o obj-$(CONFIG_ARM_TWD_TIMER) += arm_twd_timer.o obj-$(CONFIG_AST_TIMER) += ast_timer.o +obj-$(CONFIG_AST_IBEX_TIMER) += ast_ibex_timer.o obj-$(CONFIG_ATCPIT100_TIMER) += atcpit100_timer.o obj-$(CONFIG_$(SPL_)ATMEL_PIT_TIMER) += atmel_pit_timer.o obj-$(CONFIG_$(SPL_)ATMEL_TCB_TIMER) += atmel_tcb_timer.o diff --git a/drivers/timer/ast_ibex_timer.c b/drivers/timer/ast_ibex_timer.c new file mode 100644 index 00000000000..261839661e9 --- /dev/null +++ b/drivers/timer/ast_ibex_timer.c @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2024 Aspeed Technology Inc. + */ + +#include <asm/csr.h> +#include <asm/io.h> +#include <dm.h> +#include <errno.h> +#include <timer.h> + +#define CSR_MCYCLE 0xb00 +#define CSR_MCYCLEH 0xb80 + +static u64 ast_ibex_timer_get_count(struct udevice *dev) +{ + uint32_t cnt_l, cnt_h; + + cnt_l = csr_read(CSR_MCYCLE); + cnt_h = csr_read(CSR_MCYCLEH); + + return ((uint64_t)cnt_h << 32) | cnt_l; +} + +static int ast_ibex_timer_probe(struct udevice *dev) +{ + return 0; +} + +static const struct timer_ops ast_ibex_timer_ops = { + .get_count = ast_ibex_timer_get_count, +}; + +static const struct udevice_id ast_ibex_timer_ids[] = { + { .compatible = "aspeed,ast2700-ibex-timer" }, + { } +}; + +U_BOOT_DRIVER(ast_ibex_timer) = { + .name = "ast_ibex_timer", + .id = UCLASS_TIMER, + .of_match = ast_ibex_timer_ids, + .probe = ast_ibex_timer_probe, + .ops = &ast_ibex_timer_ops, +}; diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig index a972d87c7ad..311aaa7e67f 100644 --- a/drivers/usb/Kconfig +++ b/drivers/usb/Kconfig @@ -99,7 +99,8 @@ config USB_STORAGE config USB_KEYBOARD bool "USB Keyboard support" - select DM_KEYBOARD if DM_USB + depends on DM_USB + select DM_KEYBOARD select SYS_STDIO_DEREGISTER ---help--- Say Y here if you want to use a USB keyboard for U-Boot command line diff --git a/drivers/usb/cdns3/gadget.c b/drivers/usb/cdns3/gadget.c index 32b2c412068..ac7e469469a 100644 --- a/drivers/usb/cdns3/gadget.c +++ b/drivers/usb/cdns3/gadget.c @@ -965,6 +965,12 @@ int cdns3_ep_run_transfer(struct cdns3_endpoint *priv_ep, if (priv_dev->dev_ver <= DEV_VER_V2) cdns3_wa1_tray_restore_cycle_bit(priv_dev, priv_ep); + /* Flush TRBs */ + flush_dcache_range((unsigned long)priv_ep->trb_pool, + (unsigned long)priv_ep->trb_pool + + ROUND(sizeof(struct cdns3_trb) * priv_ep->num_trbs, + CONFIG_SYS_CACHELINE_SIZE)); + trace_cdns3_prepare_trb(priv_ep, priv_req->trb); /* @@ -1153,6 +1159,13 @@ static void cdns3_transfer_completed(struct cdns3_device *priv_dev, priv_ep->endpoint.desc->bEndpointAddress); #endif + /* Invalidate TRBs */ + invalidate_dcache_range((unsigned long)priv_ep->trb_pool, + (unsigned long)priv_ep->trb_pool + + ROUND(sizeof(struct cdns3_trb) * + priv_ep->num_trbs, + CONFIG_SYS_CACHELINE_SIZE)); + if (!cdns3_request_handled(priv_ep, priv_req)) goto prepare_next_td; diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig index 4621a6fd5e6..f20a16e3e7d 100644 --- a/drivers/usb/gadget/Kconfig +++ b/drivers/usb/gadget/Kconfig @@ -323,7 +323,8 @@ config SPL_DFU bool "Support DFU (Device Firmware Upgrade) in SPL" select SPL_HASH select SPL_DFU_NO_RESET - depends on SPL_RAM_SUPPORT + select SPL_RAM_SUPPORT + depends on DFU_OVER_USB help This feature enables the DFU (Device Firmware Upgrade) in SPL with RAM memory device support. The ROM code will load and execute diff --git a/drivers/usb/host/ehci-generic.c b/drivers/usb/host/ehci-generic.c index 23c3ed25554..1ae3619ce25 100644 --- a/drivers/usb/host/ehci-generic.c +++ b/drivers/usb/host/ehci-generic.c @@ -94,7 +94,7 @@ static int ehci_usb_probe(struct udevice *dev) if (err) goto reset_err; - err = generic_setup_phy(dev, &priv->phy, 0); + err = generic_setup_phy(dev, &priv->phy, 0, PHY_MODE_USB_HOST, 0); if (err) goto regulator_err; diff --git a/drivers/usb/host/ehci-msm.c b/drivers/usb/host/ehci-msm.c index ff336082e3a..a759aea9db3 100644 --- a/drivers/usb/host/ehci-msm.c +++ b/drivers/usb/host/ehci-msm.c @@ -80,7 +80,7 @@ static int ehci_usb_probe(struct udevice *dev) hcor = (struct ehci_hcor *)((phys_addr_t)hccr + HC_LENGTH(ehci_readl(&(hccr)->cr_capbase))); - ret = generic_setup_phy(dev, &p->phy, 0); + ret = generic_setup_phy(dev, &p->phy, 0, PHY_MODE_USB_HOST, 0); if (ret) goto cleanup_iface; diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c index 31cd8a50f4a..a93fa5d5455 100644 --- a/drivers/usb/host/ehci-mx6.c +++ b/drivers/usb/host/ehci-mx6.c @@ -703,7 +703,7 @@ static int ehci_usb_probe(struct udevice *dev) usb_phy_enable(ehci, priv->phy_addr); #endif #else - ret = generic_setup_phy(dev, &priv->phy, 0); + ret = generic_setup_phy(dev, &priv->phy, 0, PHY_MODE_USB_HOST, 0); if (ret) goto err_regulator; #endif diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c index 572686580cd..8d05b14e898 100644 --- a/drivers/usb/host/ehci-pci.c +++ b/drivers/usb/host/ehci-pci.c @@ -30,7 +30,7 @@ static int ehci_pci_init(struct udevice *dev, struct ehci_hccr **ret_hccr, int ret; u32 cmd; - ret = generic_setup_phy(dev, &priv->phy, 0); + ret = generic_setup_phy(dev, &priv->phy, 0, PHY_MODE_USB_HOST, 0); if (ret) return ret; diff --git a/drivers/usb/host/ohci-generic.c b/drivers/usb/host/ohci-generic.c index f1325cd4953..cc44226f5e0 100644 --- a/drivers/usb/host/ohci-generic.c +++ b/drivers/usb/host/ohci-generic.c @@ -50,7 +50,7 @@ static int ohci_usb_probe(struct udevice *dev) goto reset_err; } - err = generic_setup_phy(dev, &priv->phy, 0); + err = generic_setup_phy(dev, &priv->phy, 0, PHY_MODE_USB_HOST, 0); if (err) goto reset_err; |