diff options
Diffstat (limited to 'drivers')
36 files changed, 616 insertions, 1197 deletions
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig index ce6907e6900..7715c403656 100644 --- a/drivers/ata/Kconfig +++ b/drivers/ata/Kconfig @@ -113,12 +113,20 @@ config SATA_CEVA config FSL_SATA bool "Enable Freescale SATA controller driver support" + depends on PPC select AHCI select LIBATA + imply LBA48 help Enable this driver to support the SATA controller found in some Freescale PowerPC SoCs. +config FSL_SATA_V2 + bool "Enable support for V2 of the Freescale SATA controller" + depends on FSL_SATA + help + Enable support for V2 of this controller, rather than V1. + config SATA_MV bool "Enable Marvell SATA controller driver support" select AHCI diff --git a/drivers/ata/dwc_ahsata.c b/drivers/ata/dwc_ahsata.c index d9fd850c6fa..1a2c3c2fe70 100644 --- a/drivers/ata/dwc_ahsata.c +++ b/drivers/ata/dwc_ahsata.c @@ -844,138 +844,6 @@ static ulong sata_write_common(struct ahci_uc_priv *uc_priv, return rc; } -#if !CONFIG_IS_ENABLED(AHCI) -static int ahci_init_one(int pdev) -{ - int rc; - struct ahci_uc_priv *uc_priv = NULL; - - uc_priv = malloc(sizeof(struct ahci_uc_priv)); - if (!uc_priv) - return -ENOMEM; - - memset(uc_priv, 0, sizeof(struct ahci_uc_priv)); - uc_priv->dev = pdev; - - uc_priv->host_flags = ATA_FLAG_SATA - | ATA_FLAG_NO_LEGACY - | ATA_FLAG_MMIO - | ATA_FLAG_PIO_DMA - | ATA_FLAG_NO_ATAPI; - - uc_priv->mmio_base = (void __iomem *)CONFIG_DWC_AHSATA_BASE_ADDR; - - /* initialize adapter */ - rc = ahci_host_init(uc_priv); - if (rc) - goto err_out; - - ahci_print_info(uc_priv); - - /* Save the uc_private struct to block device struct */ - sata_dev_desc[pdev].priv = uc_priv; - - return 0; - -err_out: - if (uc_priv) - free(uc_priv); - return rc; -} - -int init_sata(int dev) -{ - struct ahci_uc_priv *uc_priv = NULL; - -#if defined(CONFIG_MX6) - if (!is_mx6dq() && !is_mx6dqp()) - return 1; -#endif - if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) { - printf("The sata index %d is out of ranges\n\r", dev); - return -1; - } - - ahci_init_one(dev); - - uc_priv = sata_dev_desc[dev].priv; - - return dwc_ahci_start_ports(uc_priv) ? 1 : 0; -} - -int reset_sata(int dev) -{ - struct ahci_uc_priv *uc_priv; - struct sata_host_regs *host_mmio; - - if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) { - printf("The sata index %d is out of ranges\n\r", dev); - return -1; - } - - uc_priv = sata_dev_desc[dev].priv; - if (NULL == uc_priv) - /* not initialized, so nothing to reset */ - return 0; - - host_mmio = uc_priv->mmio_base; - setbits_le32(&host_mmio->ghc, SATA_HOST_GHC_HR); - while (readl(&host_mmio->ghc) & SATA_HOST_GHC_HR) - udelay(100); - - free(uc_priv); - memset(&sata_dev_desc[dev], 0, sizeof(struct blk_desc)); - - return 0; -} - -int sata_port_status(int dev, int port) -{ - struct sata_port_regs *port_mmio; - struct ahci_uc_priv *uc_priv = NULL; - - if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) - return -EINVAL; - - if (sata_dev_desc[dev].priv == NULL) - return -ENODEV; - - uc_priv = sata_dev_desc[dev].priv; - port_mmio = uc_priv->port[port].port_mmio; - - return readl(&port_mmio->ssts) & SATA_PORT_SSTS_DET_MASK; -} - -/* - * SATA interface between low level driver and command layer - */ -ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer) -{ - struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv; - - return sata_read_common(uc_priv, &sata_dev_desc[dev], blknr, blkcnt, - buffer); -} - -ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer) -{ - struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv; - - return sata_write_common(uc_priv, &sata_dev_desc[dev], blknr, blkcnt, - buffer); -} - -int scan_sata(int dev) -{ - struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv; - struct blk_desc *pdev = &sata_dev_desc[dev]; - - return dwc_ahsata_scan_common(uc_priv, pdev); -} -#endif /* CONFIG_IS_ENABLED(AHCI) */ - -#if CONFIG_IS_ENABLED(AHCI) - int dwc_ahsata_port_status(struct udevice *dev, int port) { struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev); @@ -1109,4 +977,3 @@ U_BOOT_DRIVER(dwc_ahsata_ahci) = { .probe = dwc_ahsata_probe, }; #endif -#endif diff --git a/drivers/ata/fsl_sata.c b/drivers/ata/fsl_sata.c index d1bab931895..6db4247368e 100644 --- a/drivers/ata/fsl_sata.c +++ b/drivers/ata/fsl_sata.c @@ -6,10 +6,13 @@ */ #include <common.h> +#include <ahci.h> #include <blk.h> #include <command.h> #include <console.h> #include <cpu_func.h> +#include <dm.h> +#include <dm/device-internal.h> #include <log.h> #include <asm/io.h> #include <asm/processor.h> @@ -21,33 +24,6 @@ #include <linux/delay.h> #include "fsl_sata.h" -#if CONFIG_IS_ENABLED(BLK) -#include <dm.h> -#include <ahci.h> -#include <blk.h> -#include <dm/device-internal.h> -#else -#ifndef CONFIG_SYS_SATA1_FLAGS - #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA -#endif -#ifndef CONFIG_SYS_SATA2_FLAGS - #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA -#endif - -static struct fsl_sata_info fsl_sata_info[] = { -#ifdef CONFIG_SATA1 - {CONFIG_SYS_SATA1, CONFIG_SYS_SATA1_FLAGS}, -#else - {0, 0}, -#endif -#ifdef CONFIG_SATA2 - {CONFIG_SYS_SATA2, CONFIG_SYS_SATA2_FLAGS}, -#else - {0, 0}, -#endif -}; -#endif - static inline void sdelay(unsigned long sec) { unsigned long i; @@ -86,11 +62,7 @@ static int ata_wait_register(unsigned __iomem *addr, u32 mask, return (i < timeout_msec) ? 0 : -1; } -#if !CONFIG_IS_ENABLED(BLK) -int init_sata(int dev) -#else static int init_sata(struct fsl_ata_priv *priv, int dev) -#endif { u32 length, align; cmd_hdr_tbl_t *cmd_hdr; @@ -129,15 +101,9 @@ static int init_sata(struct fsl_ata_priv *priv, int dev) snprintf(sata->name, 12, "SATA%d:", dev); /* Set the controller register base address to device struct */ -#if !CONFIG_IS_ENABLED(BLK) - sata_dev_desc[dev].priv = (void *)sata; - reg = (fsl_sata_reg_t *)(fsl_sata_info[dev].sata_reg_base); - sata->dma_flag = fsl_sata_info[dev].flags; -#else reg = (fsl_sata_reg_t *)(priv->base + priv->offset * dev); sata->dma_flag = priv->flag; priv->fsl_sata = sata; -#endif sata->reg_base = reg; /* Allocate the command header table, 4 bytes aligned */ @@ -738,17 +704,11 @@ static u32 ata_low_level_rw_lba28(fsl_sata_t *sata, u32 blknr, u32 blkcnt, /* * SATA interface between low level driver and command layer */ -#if !CONFIG_IS_ENABLED(BLK) -ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer) -{ - fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv; -#else static ulong sata_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt, void *buffer) { struct fsl_ata_priv *priv = dev_get_plat(dev); fsl_sata_t *sata = priv->fsl_sata; -#endif u32 rc; if (sata->lba48) @@ -760,17 +720,11 @@ static ulong sata_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt, return rc; } -#if !CONFIG_IS_ENABLED(BLK) -ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer) -{ - fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv; -#else static ulong sata_write(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt, const void *buffer) { struct fsl_ata_priv *priv = dev_get_plat(dev); fsl_sata_t *sata = priv->fsl_sata; -#endif u32 rc; if (sata->lba48) { @@ -801,17 +755,11 @@ static void fsl_sata_identify(fsl_sata_t *sata, u16 *id) ata_swap_buf_le16(id, ATA_ID_WORDS); } -#if !CONFIG_IS_ENABLED(BLK) -int scan_sata(int dev) -{ - fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv; -#else static int scan_sata(struct udevice *dev) { struct blk_desc *desc = dev_get_uclass_plat(dev); struct fsl_ata_priv *priv = dev_get_plat(dev); fsl_sata_t *sata = priv->fsl_sata; -#endif unsigned char serial[ATA_ID_SERNO_LEN + 1]; unsigned char firmware[ATA_ID_FW_REV_LEN + 1]; @@ -853,15 +801,6 @@ static int scan_sata(struct udevice *dev) debug("Device supports LBA28\n\r"); #endif -#if !CONFIG_IS_ENABLED(BLK) - memcpy(sata_dev_desc[dev].product, serial, sizeof(serial)); - memcpy(sata_dev_desc[dev].revision, firmware, sizeof(firmware)); - memcpy(sata_dev_desc[dev].vendor, product, sizeof(product)); - sata_dev_desc[dev].lba = (u32)n_sectors; -#ifdef CONFIG_LBA48 - sata_dev_desc[dev].lba48 = sata->lba48; -#endif -#else memcpy(desc->product, serial, sizeof(serial)); memcpy(desc->revision, firmware, sizeof(firmware)); memcpy(desc->vendor, product, sizeof(product)); @@ -869,7 +808,6 @@ static int scan_sata(struct udevice *dev) #ifdef CONFIG_LBA48 desc->lba48 = sata->lba48; #endif -#endif /* Get the NCQ queue depth from device */ sata->queue_depth = ata_id_queue_depth(id); @@ -890,7 +828,6 @@ static int scan_sata(struct udevice *dev) return 0; } -#if CONFIG_IS_ENABLED(BLK) static const struct blk_ops sata_fsl_blk_ops = { .read = sata_read, .write = sata_write, @@ -1042,4 +979,3 @@ U_BOOT_DRIVER(fsl_ahci) = { .remove = fsl_ata_remove, .priv_auto = sizeof(struct fsl_ata_priv), }; -#endif diff --git a/drivers/ata/fsl_sata.h b/drivers/ata/fsl_sata.h index 5b9daa79e02..e1ea8eb3a18 100644 --- a/drivers/ata/fsl_sata.h +++ b/drivers/ata/fsl_sata.h @@ -319,7 +319,6 @@ typedef struct fsl_sata { #define READ_CMD 0 #define WRITE_CMD 1 -#if CONFIG_IS_ENABLED(BLK) struct fsl_ata_priv { u32 base; u32 flag; @@ -327,6 +326,5 @@ struct fsl_ata_priv { u32 offset; fsl_sata_t *fsl_sata; }; -#endif #endif /* __FSL_SATA_H__ */ diff --git a/drivers/ata/sata_sil.h b/drivers/ata/sata_sil.h index bea4322c919..9ad09e5461d 100644 --- a/drivers/ata/sata_sil.h +++ b/drivers/ata/sata_sil.h @@ -212,12 +212,10 @@ enum { CMD_ERR = 0x21, }; -#if CONFIG_IS_ENABLED(BLK) #define ATA_MAX_PORTS 32 struct sil_sata_priv { int port_num; struct sil_sata *sil_sata_desc[ATA_MAX_PORTS]; }; -#endif #endif diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig index d6d1c6e32cc..b5b482086af 100644 --- a/drivers/block/Kconfig +++ b/drivers/block/Kconfig @@ -218,3 +218,19 @@ config IDE_RESET must be defined in a board-specific file. endif # IDE + +config LBA48 + bool "Enable LBA support for disks larger than 137GB" + depends on HAVE_BLOCK_DEVICE + help + Set this to enable support for disks larger than 137GB. + Also look at CONFIG_SYS_64BIT_LBA. Without both of these, LBA48 + support uses 32bit variables and will 'only' support disks up to + 2.1TB. + +config SYS_64BIT_LBA + bool "Enable 64bit number of blocks on a block device" + depends on HAVE_BLOCK_DEVICE + help + Make the block subsystem use 64bit sector addresses, rather than the + default of 32bit. diff --git a/drivers/block/ide.c b/drivers/block/ide.c index e8518ff3a11..3270a9f032f 100644 --- a/drivers/block/ide.c +++ b/drivers/block/ide.c @@ -695,15 +695,6 @@ void ide_init(void) unsigned char c; int i, bus; -#ifdef CONFIG_IDE_PREINIT - WATCHDOG_RESET(); - - if (ide_preinit()) { - puts("ide_preinit failed\n"); - return; - } -#endif /* CONFIG_IDE_PREINIT */ - WATCHDOG_RESET(); /* ATAPI Drives seems to need a proper IDE Reset */ diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig index 9b9a7148a1a..d3fe1d4093d 100644 --- a/drivers/core/Kconfig +++ b/drivers/core/Kconfig @@ -224,7 +224,7 @@ config SPL_SYSCON config TPL_SYSCON bool "Support system controllers in TPL" - depends on SPL_REGMAP + depends on TPL_REGMAP help Many SoCs have a number of system controllers which are dealt with as a group by a single driver. Some common functionality is provided diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index dc0b3dd31b7..76719517f54 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -21,6 +21,12 @@ config FPGA_SOCFPGA This provides common functionality for Gen5 and Arria10 devices. +config FPGA_STRATIX_V + bool "Enable Stratix V FPGA drivers" + depends on FPGA_ALTERA + help + Say Y here to enable the Altera Stratix V FPGA specific driver. + config FPGA_CYCLON2 bool "Enable Altera FPGA driver for Cyclone II" depends on FPGA_ALTERA diff --git a/drivers/i2c/exynos_hs_i2c.c b/drivers/i2c/exynos_hs_i2c.c index 39bcacc17a7..a7349e06cfd 100644 --- a/drivers/i2c/exynos_hs_i2c.c +++ b/drivers/i2c/exynos_hs_i2c.c @@ -147,7 +147,7 @@ static int hsi2c_get_clk_details(struct s3c24x0_i2c_bus *i2c_bus) unsigned int i = 0, utemp0 = 0, utemp1 = 0; unsigned int t_ftl_cycle; -#if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) +#if defined(CONFIG_ARCH_EXYNOS4) || defined(CONFIG_ARCH_EXYNOS5) clkin = get_i2c_clk(); #else clkin = get_PCLK(); diff --git a/drivers/i2c/s3c24x0_i2c.c b/drivers/i2c/s3c24x0_i2c.c index aaccb3aa228..505e20bc61c 100644 --- a/drivers/i2c/s3c24x0_i2c.c +++ b/drivers/i2c/s3c24x0_i2c.c @@ -8,7 +8,7 @@ #include <errno.h> #include <dm.h> #include <fdtdec.h> -#if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) +#if defined(CONFIG_ARCH_EXYNOS4) || defined(CONFIG_ARCH_EXYNOS5) #include <log.h> #include <asm/arch/clk.h> #include <asm/arch/cpu.h> @@ -53,7 +53,7 @@ static void read_write_byte(struct s3c24x0_i2c *i2c) static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd) { ulong freq, pres = 16, div; -#if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) +#if defined(CONFIG_ARCH_EXYNOS4) || defined(CONFIG_ARCH_EXYNOS5) freq = get_i2c_clk(); #else freq = get_PCLK(); diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 20cd4d7fc9e..67278c40e35 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -82,6 +82,7 @@ const struct flash_info spi_nor_ids[] = { /* EON -- en25xxx */ { INFO("en25q32b", 0x1c3016, 0, 64 * 1024, 64, 0) }, { INFO("en25q64", 0x1c3017, 0, 64 * 1024, 128, SECT_4K) }, + { INFO("en25q128b", 0x1c3018, 0, 64 * 1024, 256, 0) }, { INFO("en25qh128", 0x1c7018, 0, 64 * 1024, 256, 0) }, { INFO("en25s64", 0x1c3817, 0, 64 * 1024, 128, SECT_4K) }, #endif @@ -127,11 +128,17 @@ const struct flash_info spi_nor_ids[] = { SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, + { + INFO("gd25lx256e", 0xc86819, 0, 64 * 1024, 512, + SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) + }, #endif #ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */ /* ISSI */ { INFO("is25lq040b", 0x9d4013, 0, 64 * 1024, 8, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("is25lp008", 0x9d6014, 0, 64 * 1024, 16, SPI_NOR_QUAD_READ) }, + { INFO("is25lp016", 0x9d6015, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ) }, { INFO("is25lp032", 0x9d6016, 0, 64 * 1024, 64, 0) }, { INFO("is25lp064", 0x9d6017, 0, 64 * 1024, 128, 0) }, { INFO("is25lp128", 0x9d6018, 0, 64 * 1024, 256, @@ -140,6 +147,10 @@ const struct flash_info spi_nor_ids[] = { SECT_4K | SPI_NOR_DUAL_READ) }, { INFO("is25lp512", 0x9d601a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("is25lp01g", 0x9d601b, 0, 64 * 1024, 2048, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("is25wp008", 0x9d7014, 0, 64 * 1024, 16, SPI_NOR_QUAD_READ) }, + { INFO("is25wp016", 0x9d7015, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ) }, { INFO("is25wp032", 0x9d7016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("is25wp064", 0x9d7017, 0, 64 * 1024, 128, @@ -151,6 +162,10 @@ const struct flash_info spi_nor_ids[] = { SPI_NOR_4B_OPCODES) }, { INFO("is25wp512", 0x9d701a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("is25wp01g", 0x9d701b, 0, 64 * 1024, 2048, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("is25wx256", 0x9d5b19, 0, 128 * 1024, 256, + SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) }, #endif #ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */ /* Macronix */ @@ -176,8 +191,11 @@ const struct flash_info spi_nor_ids[] = { { INFO("mx25l25655e", 0xc22619, 0, 64 * 1024, 512, 0) }, { INFO("mx66l51235l", 0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, { INFO("mx66u51235f", 0xc2253a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, + { INFO("mx25u51245f", 0xc2953a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, + { INFO("mx66u1g45g", 0xc2253b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, { INFO("mx66u2g45g", 0xc2253c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, { INFO("mx66l1g45g", 0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("mx66l2g45g", 0xc2201c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, { INFO("mx25l1633e", 0xc22415, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | SECT_4K) }, { INFO("mx25r6435f", 0xc22817, 0, 64 * 1024, 128, SECT_4K) }, { INFO("mx66uw2g345g", 0xc2943c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) }, @@ -208,8 +226,10 @@ const struct flash_info spi_nor_ids[] = { { INFO("mt25qu02g", 0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, { INFO("mt25ql02g", 0x20ba22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE | SPI_NOR_4B_OPCODES) }, #ifdef CONFIG_SPI_FLASH_MT35XU + { INFO("mt35xl512aba", 0x2c5a1a, 0, 128 * 1024, 512, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ) }, { INFO("mt35xu512aba", 0x2c5b1a, 0, 128 * 1024, 512, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ) }, #endif /* CONFIG_SPI_FLASH_MT35XU */ + { INFO6("mt35xu01g", 0x2c5b1b, 0x104100, 128 * 1024, 1024, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) }, { INFO("mt35xu02g", 0x2c5b1c, 0, 128 * 1024, 2048, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) }, #endif #ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */ @@ -225,6 +245,7 @@ const struct flash_info spi_nor_ids[] = { { INFO("s25fl512s_256k", 0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, { INFO("s25fl512s_64k", 0x010220, 0x4d01, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, { INFO("s25fl512s_512k", 0x010220, 0x4f00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, + { INFO("s70fs01gs_256k", 0x010221, 0x4d00, 256 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("s25sl12800", 0x012018, 0x0300, 256 * 1024, 64, 0) }, { INFO("s25sl12801", 0x012018, 0x0301, 64 * 1024, 256, 0) }, { INFO6("s25fl128s", 0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, @@ -275,6 +296,7 @@ const struct flash_info spi_nor_ids[] = { { INFO("sst25wf040", 0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) }, { INFO("sst25wf080", 0xbf2505, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) }, { INFO("sst26vf064b", 0xbf2643, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_HAS_SST26LOCK | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("sst26wf016b", 0xbf2641, 0, 64 * 1024, 32, SECT_4K) }, { INFO("sst26wf016", 0xbf2651, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_HAS_SST26LOCK) }, { INFO("sst26wf032", 0xbf2622, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_HAS_SST26LOCK) }, { INFO("sst26wf064", 0xbf2643, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_HAS_SST26LOCK) }, @@ -312,11 +334,19 @@ const struct flash_info spi_nor_ids[] = { { INFO("w25q20ew", 0xef6012, 0, 64 * 1024, 4, SECT_4K) }, { INFO("w25q32", 0xef4016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { + INFO("w25q16dw", 0xef6015, 0, 64 * 1024, 32, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) + }, + { INFO("w25q32dw", 0xef6016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, { + INFO("w25q16jv", 0xef7015, 0, 64 * 1024, 32, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) + }, + { INFO("w25q32jv", 0xef7016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) @@ -363,6 +393,11 @@ const struct flash_info spi_nor_ids[] = { SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, { + INFO("w25q512jv", 0xef7119, 0, 64 * 1024, 512, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) + }, + { INFO("w25q01jv", 0xef4021, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) @@ -370,6 +405,7 @@ const struct flash_info spi_nor_ids[] = { { INFO("w25q80", 0xef5014, 0, 64 * 1024, 16, SECT_4K) }, { INFO("w25q80bl", 0xef4014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("w25q16cl", 0xef4015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("w25q32bv", 0xef4016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("w25q64cv", 0xef4017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("w25q128", 0xef4018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | @@ -378,6 +414,7 @@ const struct flash_info spi_nor_ids[] = { { INFO("w25q256", 0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("w25m512jw", 0xef6119, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("w25m512jv", 0xef7119, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("w25h02jv", 0xef9022, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, #endif #ifdef CONFIG_SPI_FLASH_XMC /* XMC (Wuhan Xinxin Semiconductor Manufacturing Corp.) */ diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 84d859c21eb..56f9416a48d 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -239,6 +239,10 @@ config E1000 <http://support.intel.com/support/network/adapter/pro100/21397.htm> +config E1000_NO_NVM + bool "Intel PRO/1000 has no NVMEM / EEPROM" + depends on E1000 + config E1000_SPI_GENERIC bool "Allow access to the Intel 8257x SPI bus" depends on E1000 diff --git a/drivers/power/acpi_pmc/Kconfig b/drivers/power/acpi_pmc/Kconfig index fcd50e36cad..355d1618c61 100644 --- a/drivers/power/acpi_pmc/Kconfig +++ b/drivers/power/acpi_pmc/Kconfig @@ -17,6 +17,7 @@ config SPL_ACPI_PMC config TPL_ACPI_PMC bool "Power Manager (x86 PMC) support in TPL" + depends on TPL default y if ACPI_PMC help Enable support for an x86-style power-management controller which diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig index a4f9f1aad2a..7c346180bae 100644 --- a/drivers/ram/Kconfig +++ b/drivers/ram/Kconfig @@ -19,7 +19,7 @@ config SPL_RAM config TPL_RAM bool "Enable RAM support in TPL" - depends on RAM + depends on RAM && TPL help The RAM subsystem adds a small amount of overhead to the image. If this is acceptable and you have a need to use RAM drivers in diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index e48d72d7445..766d5636c09 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -136,6 +136,14 @@ config CQSPI_REF_CLK int "Cadence QSPI reference clock value in Hz" depends on HAS_CQSPI_REF_CLK +config CADENCE_OSPI_VERSAL + bool "Configure Versal OSPI" + depends on ARCH_VERSAL && CADENCE_QSPI + imply DM_GPIO + help + This option is used to enable Versal OSPI DMA operations which + are used for ospi flash read using cadence qspi controller. + config CF_SPI bool "ColdFire SPI driver" help diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 8755408e629..4de77c260ad 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -7,6 +7,7 @@ ifdef CONFIG_$(SPL_TPL_)DM_SPI obj-y += spi-uclass.o obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o cadence_qspi_apb.o +obj-$(CONFIG_CADENCE_OSPI_VERSAL) += cadence_ospi_versal.o obj-$(CONFIG_SANDBOX) += spi-emul-uclass.o obj-$(CONFIG_SOFT_SPI) += soft_spi.o obj-$(CONFIG_SPI_MEM) += spi-mem.o diff --git a/drivers/spi/cadence_ospi_versal.c b/drivers/spi/cadence_ospi_versal.c new file mode 100644 index 00000000000..52bcad053fe --- /dev/null +++ b/drivers/spi/cadence_ospi_versal.c @@ -0,0 +1,237 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * (C) Copyright 2018 Xilinx + * + * Cadence QSPI controller DMA operations + */ + +#include <clk.h> +#include <common.h> +#include <memalign.h> +#include <wait_bit.h> +#include <asm/io.h> +#include <asm/gpio.h> +#include <asm/cache.h> +#include <cpu_func.h> +#include <zynqmp_firmware.h> +#include <asm/arch/hardware.h> +#include "cadence_qspi.h" +#include <dt-bindings/power/xlnx-versal-power.h> + +#define CMD_4BYTE_READ 0x13 +#define CMD_4BYTE_FAST_READ 0x0C + +int cadence_qspi_apb_dma_read(struct cadence_spi_plat *plat, + const struct spi_mem_op *op) +{ + u32 reg, ret, rx_rem, n_rx, bytes_to_dma, data; + u8 opcode, addr_bytes, *rxbuf, dummy_cycles; + + n_rx = op->data.nbytes; + rxbuf = op->data.buf.in; + rx_rem = n_rx % 4; + bytes_to_dma = n_rx - rx_rem; + + if (bytes_to_dma) { + cadence_qspi_apb_enable_linear_mode(false); + reg = readl(plat->regbase + CQSPI_REG_CONFIG); + reg |= CQSPI_REG_CONFIG_ENBL_DMA; + writel(reg, plat->regbase + CQSPI_REG_CONFIG); + + writel(bytes_to_dma, plat->regbase + CQSPI_REG_INDIRECTRDBYTES); + + writel(CQSPI_DFLT_INDIR_TRIG_ADDR_RANGE, + plat->regbase + CQSPI_REG_INDIR_TRIG_ADDR_RANGE); + writel(CQSPI_DFLT_DMA_PERIPH_CFG, + plat->regbase + CQSPI_REG_DMA_PERIPH_CFG); + writel((unsigned long)rxbuf, plat->regbase + + CQSPI_DMA_DST_ADDR_REG); + writel(plat->trigger_address, plat->regbase + + CQSPI_DMA_SRC_RD_ADDR_REG); + writel(bytes_to_dma, plat->regbase + + CQSPI_DMA_DST_SIZE_REG); + flush_dcache_range((unsigned long)rxbuf, + (unsigned long)rxbuf + bytes_to_dma); + writel(CQSPI_DFLT_DST_CTRL_REG_VAL, + plat->regbase + CQSPI_DMA_DST_CTRL_REG); + + /* Start the indirect read transfer */ + writel(CQSPI_REG_INDIRECTRD_START, plat->regbase + + CQSPI_REG_INDIRECTRD); + /* Wait for dma to complete transfer */ + ret = cadence_qspi_apb_wait_for_dma_cmplt(plat); + if (ret) + return ret; + + /* Clear indirect completion status */ + writel(CQSPI_REG_INDIRECTRD_DONE, plat->regbase + + CQSPI_REG_INDIRECTRD); + rxbuf += bytes_to_dma; + } + + if (rx_rem) { + reg = readl(plat->regbase + CQSPI_REG_CONFIG); + reg &= ~CQSPI_REG_CONFIG_ENBL_DMA; + writel(reg, plat->regbase + CQSPI_REG_CONFIG); + + reg = readl(plat->regbase + CQSPI_REG_INDIRECTRDSTARTADDR); + reg += bytes_to_dma; + writel(reg, plat->regbase + CQSPI_REG_CMDADDRESS); + + addr_bytes = readl(plat->regbase + CQSPI_REG_SIZE) & + CQSPI_REG_SIZE_ADDRESS_MASK; + + opcode = CMD_4BYTE_FAST_READ; + dummy_cycles = 8; + writel((dummy_cycles << CQSPI_REG_RD_INSTR_DUMMY_LSB) | opcode, + plat->regbase + CQSPI_REG_RD_INSTR); + + reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB; + reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB); + reg |= (addr_bytes & CQSPI_REG_CMDCTRL_ADD_BYTES_MASK) << + CQSPI_REG_CMDCTRL_ADD_BYTES_LSB; + reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB); + dummy_cycles = (readl(plat->regbase + CQSPI_REG_RD_INSTR) >> + CQSPI_REG_RD_INSTR_DUMMY_LSB) & + CQSPI_REG_RD_INSTR_DUMMY_MASK; + reg |= (dummy_cycles & CQSPI_REG_CMDCTRL_DUMMY_MASK) << + CQSPI_REG_CMDCTRL_DUMMY_LSB; + reg |= (((rx_rem - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK) << + CQSPI_REG_CMDCTRL_RD_BYTES_LSB); + ret = cadence_qspi_apb_exec_flash_cmd(plat->regbase, reg); + if (ret) + return ret; + + data = readl(plat->regbase + CQSPI_REG_CMDREADDATALOWER); + memcpy(rxbuf, &data, rx_rem); + } + + return 0; +} + +int cadence_qspi_apb_wait_for_dma_cmplt(struct cadence_spi_plat *plat) +{ + u32 timeout = CQSPI_DMA_TIMEOUT; + + while (!(readl(plat->regbase + CQSPI_DMA_DST_I_STS_REG) & + CQSPI_DMA_DST_I_STS_DONE) && timeout--) + udelay(1); + + if (!timeout) { + printf("DMA timeout\n"); + return -ETIMEDOUT; + } + + writel(readl(plat->regbase + CQSPI_DMA_DST_I_STS_REG), + plat->regbase + CQSPI_DMA_DST_I_STS_REG); + return 0; +} + +#if defined(CONFIG_DM_GPIO) +int cadence_spi_versal_flash_reset(struct udevice *dev) +{ + struct gpio_desc gpio; + u32 reset_gpio; + int ret; + + /* request gpio and set direction as output set to 1 */ + ret = gpio_request_by_name(dev, "reset-gpios", 0, &gpio, + GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + if (ret) { + printf("%s: unable to reset ospi flash device", __func__); + return ret; + } + + reset_gpio = PMIO_NODE_ID_BASE + gpio.offset; + + /* Request for pin */ + xilinx_pm_request(PM_PINCTRL_REQUEST, reset_gpio, 0, 0, 0, NULL); + + /* Enable hysteresis in cmos receiver */ + xilinx_pm_request(PM_PINCTRL_CONFIG_PARAM_SET, reset_gpio, + PM_PINCTRL_CONFIG_SCHMITT_CMOS, + PM_PINCTRL_INPUT_TYPE_SCHMITT, 0, NULL); + + /* Disable Tri-state */ + xilinx_pm_request(PM_PINCTRL_CONFIG_PARAM_SET, reset_gpio, + PM_PINCTRL_CONFIG_TRI_STATE, + PM_PINCTRL_TRI_STATE_DISABLE, 0, NULL); + udelay(1); + + /* Set value 0 to pin */ + dm_gpio_set_value(&gpio, 0); + udelay(1); + + /* Set value 1 to pin */ + dm_gpio_set_value(&gpio, 1); + udelay(1); + + return 0; +} +#else +int cadence_spi_versal_flash_reset(struct udevice *dev) +{ + /* CRP WPROT */ + writel(0, WPROT_CRP); + /* GPIO Reset */ + writel(0, RST_GPIO); + + /* disable IOU write protection */ + writel(0, WPROT_LPD_MIO); + + /* set direction as output */ + writel((readl(BOOT_MODE_DIR) | BIT(FLASH_RESET_GPIO)), + BOOT_MODE_POR_0); + + /* Data output enable */ + writel((readl(BOOT_MODE_OUT) | BIT(FLASH_RESET_GPIO)), + BOOT_MODE_POR_1); + + /* IOU SLCR write enable */ + writel(0, WPROT_PMC_MIO); + + /* set MIO as GPIO */ + writel(0x60, MIO_PIN_12); + + /* Set value 1 to pin */ + writel((readl(BANK0_OUTPUT) | BIT(FLASH_RESET_GPIO)), BANK0_OUTPUT); + udelay(10); + + /* Disable Tri-state */ + writel((readl(BANK0_TRI) & ~BIT(FLASH_RESET_GPIO)), BANK0_TRI); + udelay(1); + + /* Set value 0 to pin */ + writel((readl(BANK0_OUTPUT) & ~BIT(FLASH_RESET_GPIO)), BANK0_OUTPUT); + udelay(10); + + /* Set value 1 to pin */ + writel((readl(BANK0_OUTPUT) | BIT(FLASH_RESET_GPIO)), BANK0_OUTPUT); + udelay(10); + + return 0; +} +#endif + +void cadence_qspi_apb_enable_linear_mode(bool enable) +{ + if (CONFIG_IS_ENABLED(ZYNQMP_FIRMWARE)) { + if (enable) + /* ahb read mode */ + xilinx_pm_request(PM_IOCTL, PM_DEV_OSPI, + IOCTL_OSPI_MUX_SELECT, + PM_OSPI_MUX_SEL_LINEAR, 0, NULL); + else + /* DMA mode */ + xilinx_pm_request(PM_IOCTL, PM_DEV_OSPI, + IOCTL_OSPI_MUX_SELECT, + PM_OSPI_MUX_SEL_DMA, 0, NULL); + } else { + if (enable) + writel(readl(VERSAL_AXI_MUX_SEL) | + VERSAL_OSPI_LINEAR_MODE, VERSAL_AXI_MUX_SEL); + else + writel(readl(VERSAL_AXI_MUX_SEL) & + ~VERSAL_OSPI_LINEAR_MODE, VERSAL_AXI_MUX_SEL); + } +} diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index 7209bb43a77..907f5dadc4f 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -18,7 +18,9 @@ #include <linux/err.h> #include <linux/errno.h> #include <linux/sizes.h> +#include <zynqmp_firmware.h> #include "cadence_qspi.h" +#include <dt-bindings/power/xlnx-versal-power.h> #define NSEC_PER_SEC 1000000000L @@ -27,6 +29,17 @@ #define CQSPI_READ 2 #define CQSPI_WRITE 3 +__weak int cadence_qspi_apb_dma_read(struct cadence_spi_plat *plat, + const struct spi_mem_op *op) +{ + return 0; +} + +__weak int cadence_qspi_versal_flash_reset(struct udevice *dev) +{ + return 0; +} + static int cadence_spi_write_speed(struct udevice *bus, uint hz) { struct cadence_spi_plat *plat = dev_get_plat(bus); @@ -138,7 +151,7 @@ static int cadence_spi_set_speed(struct udevice *bus, uint hz) struct cadence_spi_priv *priv = dev_get_priv(bus); int err; - if (hz > plat->max_hz) + if (!hz || hz > plat->max_hz) hz = plat->max_hz; /* Disable QSPI */ @@ -185,6 +198,11 @@ static int cadence_spi_probe(struct udevice *bus) priv->regbase = plat->regbase; priv->ahbbase = plat->ahbbase; + if (CONFIG_IS_ENABLED(ZYNQMP_FIRMWARE)) + xilinx_pm_request(PM_REQUEST_NODE, PM_DEV_OSPI, + ZYNQMP_PM_CAPABILITY_ACCESS, ZYNQMP_PM_MAX_QOS, + ZYNQMP_PM_REQUEST_ACK_NO, NULL); + if (plat->ref_clk_hz == 0) { ret = clk_get_by_index(bus, 0, &clk); if (ret) { @@ -214,6 +232,16 @@ static int cadence_spi_probe(struct udevice *bus) plat->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC, plat->ref_clk_hz); + if (CONFIG_IS_ENABLED(ARCH_VERSAL)) { + /* Versal platform uses spi calibration to set read delay */ + if (plat->read_delay >= 0) + plat->read_delay = -1; + /* Reset ospi flash device */ + ret = cadence_qspi_versal_flash_reset(bus); + if (ret) + return ret; + } + return 0; } @@ -288,8 +316,12 @@ static int cadence_spi_mem_exec_op(struct spi_slave *spi, break; case CQSPI_READ: err = cadence_qspi_apb_read_setup(plat, op); - if (!err) - err = cadence_qspi_apb_read_execute(plat, op); + if (!err) { + if (plat->is_dma) + err = cadence_qspi_apb_dma_read(plat, op); + else + err = cadence_qspi_apb_read_execute(plat, op); + } break; case CQSPI_WRITE: err = cadence_qspi_apb_write_setup(plat, op); @@ -342,6 +374,8 @@ static int cadence_spi_of_to_plat(struct udevice *bus) if (plat->ahbsize >= SZ_8M) plat->use_dac_mode = true; + plat->is_dma = dev_read_bool(bus, "cdns,is-dma"); + /* All other paramters are embedded in the child node */ subnode = dev_read_first_subnode(bus); if (!ofnode_valid(subnode)) { diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h index a2b620a5fe2..c8d16bb0e44 100644 --- a/drivers/spi/cadence_qspi.h +++ b/drivers/spi/cadence_qspi.h @@ -8,6 +8,8 @@ #define __CADENCE_QSPI_H__ #include <reset.h> +#include <linux/mtd/spi-nor.h> +#include <spi-mem.h> #define CQSPI_IS_ADDR(cmd_len) (cmd_len > 1 ? 1 : 0) @@ -15,6 +17,186 @@ #define CQSPI_DECODER_MAX_CS 16 #define CQSPI_READ_CAPTURE_MAX_DELAY 16 +#define CQSPI_REG_POLL_US 1 /* 1us */ +#define CQSPI_REG_RETRY 10000 +#define CQSPI_POLL_IDLE_RETRY 3 + +/* Transfer mode */ +#define CQSPI_INST_TYPE_SINGLE 0 +#define CQSPI_INST_TYPE_DUAL 1 +#define CQSPI_INST_TYPE_QUAD 2 +#define CQSPI_INST_TYPE_OCTAL 3 + +#define CQSPI_STIG_DATA_LEN_MAX 8 + +#define CQSPI_DUMMY_CLKS_PER_BYTE 8 +#define CQSPI_DUMMY_BYTES_MAX 4 +#define CQSPI_DUMMY_CLKS_MAX 31 + +/**************************************************************************** + * Controller's configuration and status register (offset from QSPI_BASE) + ****************************************************************************/ +#define CQSPI_REG_CONFIG 0x00 +#define CQSPI_REG_CONFIG_ENABLE BIT(0) +#define CQSPI_REG_CONFIG_CLK_POL BIT(1) +#define CQSPI_REG_CONFIG_CLK_PHA BIT(2) +#define CQSPI_REG_CONFIG_PHY_ENABLE_MASK BIT(3) +#define CQSPI_REG_CONFIG_DIRECT BIT(7) +#define CQSPI_REG_CONFIG_DECODE BIT(9) +#define CQSPI_REG_CONFIG_ENBL_DMA BIT(15) +#define CQSPI_REG_CONFIG_XIP_IMM BIT(18) +#define CQSPI_REG_CONFIG_DTR_PROT_EN_MASK BIT(24) +#define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10 +#define CQSPI_REG_CONFIG_BAUD_LSB 19 +#define CQSPI_REG_CONFIG_DTR_PROTO BIT(24) +#define CQSPI_REG_CONFIG_DUAL_OPCODE BIT(30) +#define CQSPI_REG_CONFIG_IDLE_LSB 31 +#define CQSPI_REG_CONFIG_CHIPSELECT_MASK 0xF +#define CQSPI_REG_CONFIG_BAUD_MASK 0xF + +#define CQSPI_REG_RD_INSTR 0x04 +#define CQSPI_REG_RD_INSTR_OPCODE_LSB 0 +#define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB 8 +#define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB 12 +#define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB 16 +#define CQSPI_REG_RD_INSTR_MODE_EN_LSB 20 +#define CQSPI_REG_RD_INSTR_DUMMY_LSB 24 +#define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK 0x3 +#define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK 0x3 +#define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK 0x3 +#define CQSPI_REG_RD_INSTR_DUMMY_MASK 0x1F + +#define CQSPI_REG_WR_INSTR 0x08 +#define CQSPI_REG_WR_INSTR_OPCODE_LSB 0 +#define CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB 12 +#define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB 16 + +#define CQSPI_REG_DELAY 0x0C +#define CQSPI_REG_DELAY_TSLCH_LSB 0 +#define CQSPI_REG_DELAY_TCHSH_LSB 8 +#define CQSPI_REG_DELAY_TSD2D_LSB 16 +#define CQSPI_REG_DELAY_TSHSL_LSB 24 +#define CQSPI_REG_DELAY_TSLCH_MASK 0xFF +#define CQSPI_REG_DELAY_TCHSH_MASK 0xFF +#define CQSPI_REG_DELAY_TSD2D_MASK 0xFF +#define CQSPI_REG_DELAY_TSHSL_MASK 0xFF + +#define CQSPI_REG_RD_DATA_CAPTURE 0x10 +#define CQSPI_REG_RD_DATA_CAPTURE_BYPASS BIT(0) +#define CQSPI_REG_READCAPTURE_DQS_ENABLE BIT(8) +#define CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB 1 +#define CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK 0xF + +#define CQSPI_REG_SIZE 0x14 +#define CQSPI_REG_SIZE_ADDRESS_LSB 0 +#define CQSPI_REG_SIZE_PAGE_LSB 4 +#define CQSPI_REG_SIZE_BLOCK_LSB 16 +#define CQSPI_REG_SIZE_ADDRESS_MASK 0xF +#define CQSPI_REG_SIZE_PAGE_MASK 0xFFF +#define CQSPI_REG_SIZE_BLOCK_MASK 0x3F + +#define CQSPI_REG_SRAMPARTITION 0x18 +#define CQSPI_REG_INDIRECTTRIGGER 0x1C + +#define CQSPI_REG_REMAP 0x24 +#define CQSPI_REG_MODE_BIT 0x28 + +#define CQSPI_REG_SDRAMLEVEL 0x2C +#define CQSPI_REG_SDRAMLEVEL_RD_LSB 0 +#define CQSPI_REG_SDRAMLEVEL_WR_LSB 16 +#define CQSPI_REG_SDRAMLEVEL_RD_MASK 0xFFFF +#define CQSPI_REG_SDRAMLEVEL_WR_MASK 0xFFFF + +#define CQSPI_REG_WR_COMPLETION_CTRL 0x38 +#define CQSPI_REG_WR_DISABLE_AUTO_POLL BIT(14) + +#define CQSPI_REG_IRQSTATUS 0x40 +#define CQSPI_REG_IRQMASK 0x44 + +#define CQSPI_REG_INDIRECTRD 0x60 +#define CQSPI_REG_INDIRECTRD_START BIT(0) +#define CQSPI_REG_INDIRECTRD_CANCEL BIT(1) +#define CQSPI_REG_INDIRECTRD_INPROGRESS BIT(2) +#define CQSPI_REG_INDIRECTRD_DONE BIT(5) + +#define CQSPI_REG_INDIRECTRDWATERMARK 0x64 +#define CQSPI_REG_INDIRECTRDSTARTADDR 0x68 +#define CQSPI_REG_INDIRECTRDBYTES 0x6C + +#define CQSPI_REG_CMDCTRL 0x90 +#define CQSPI_REG_CMDCTRL_EXECUTE BIT(0) +#define CQSPI_REG_CMDCTRL_INPROGRESS BIT(1) +#define CQSPI_REG_CMDCTRL_DUMMY_LSB 7 +#define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12 +#define CQSPI_REG_CMDCTRL_WR_EN_LSB 15 +#define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB 16 +#define CQSPI_REG_CMDCTRL_ADDR_EN_LSB 19 +#define CQSPI_REG_CMDCTRL_RD_BYTES_LSB 20 +#define CQSPI_REG_CMDCTRL_RD_EN_LSB 23 +#define CQSPI_REG_CMDCTRL_OPCODE_LSB 24 +#define CQSPI_REG_CMDCTRL_DUMMY_MASK 0x1F +#define CQSPI_REG_CMDCTRL_WR_BYTES_MASK 0x7 +#define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK 0x3 +#define CQSPI_REG_CMDCTRL_RD_BYTES_MASK 0x7 +#define CQSPI_REG_CMDCTRL_OPCODE_MASK 0xFF + +#define CQSPI_REG_INDIRECTWR 0x70 +#define CQSPI_REG_INDIRECTWR_START BIT(0) +#define CQSPI_REG_INDIRECTWR_CANCEL BIT(1) +#define CQSPI_REG_INDIRECTWR_INPROGRESS BIT(2) +#define CQSPI_REG_INDIRECTWR_DONE BIT(5) + +#define CQSPI_REG_INDIRECTWRWATERMARK 0x74 +#define CQSPI_REG_INDIRECTWRSTARTADDR 0x78 +#define CQSPI_REG_INDIRECTWRBYTES 0x7C + +#define CQSPI_REG_CMDADDRESS 0x94 +#define CQSPI_REG_CMDREADDATALOWER 0xA0 +#define CQSPI_REG_CMDREADDATAUPPER 0xA4 +#define CQSPI_REG_CMDWRITEDATALOWER 0xA8 +#define CQSPI_REG_CMDWRITEDATAUPPER 0xAC + +#define CQSPI_REG_OP_EXT_LOWER 0xE0 +#define CQSPI_REG_OP_EXT_READ_LSB 24 +#define CQSPI_REG_OP_EXT_WRITE_LSB 16 +#define CQSPI_REG_OP_EXT_STIG_LSB 0 + +#define CQSPI_REG_PHY_CONFIG 0xB4 +#define CQSPI_REG_PHY_CONFIG_RESET_FLD_MASK 0x40000000 + +#define CQSPI_DMA_DST_ADDR_REG 0x1800 +#define CQSPI_DMA_DST_SIZE_REG 0x1804 +#define CQSPI_DMA_DST_STS_REG 0x1808 +#define CQSPI_DMA_DST_CTRL_REG 0x180C +#define CQSPI_DMA_DST_I_STS_REG 0x1814 +#define CQSPI_DMA_DST_I_ENBL_REG 0x1818 +#define CQSPI_DMA_DST_I_DISBL_REG 0x181C +#define CQSPI_DMA_DST_CTRL2_REG 0x1824 +#define CQSPI_DMA_DST_ADDR_MSB_REG 0x1828 + +#define CQSPI_DMA_SRC_RD_ADDR_REG 0x1000 + +#define CQSPI_REG_DMA_PERIPH_CFG 0x20 +#define CQSPI_REG_INDIR_TRIG_ADDR_RANGE 0x80 +#define CQSPI_DFLT_INDIR_TRIG_ADDR_RANGE 6 +#define CQSPI_DFLT_DMA_PERIPH_CFG 0x602 +#define CQSPI_DFLT_DST_CTRL_REG_VAL 0xF43FFA00 + +#define CQSPI_DMA_DST_I_STS_DONE BIT(1) +#define CQSPI_DMA_TIMEOUT 10000000 + +#define CQSPI_REG_IS_IDLE(base) \ + ((readl((base) + CQSPI_REG_CONFIG) >> \ + CQSPI_REG_CONFIG_IDLE_LSB) & 0x1) + +#define CQSPI_GET_RD_SRAM_LEVEL(reg_base) \ + (((readl((reg_base) + CQSPI_REG_SDRAMLEVEL)) >> \ + CQSPI_REG_SDRAMLEVEL_RD_LSB) & CQSPI_REG_SDRAMLEVEL_RD_MASK) + +#define CQSPI_GET_WR_SRAM_LEVEL(reg_base) \ + (((readl((reg_base) + CQSPI_REG_SDRAMLEVEL)) >> \ + CQSPI_REG_SDRAMLEVEL_WR_LSB) & CQSPI_REG_SDRAMLEVEL_WR_MASK) + struct cadence_spi_plat { unsigned int ref_clk_hz; unsigned int max_hz; @@ -42,6 +224,7 @@ struct cadence_spi_plat { u8 addr_width; u8 data_width; bool dtr; + bool is_dma; }; struct cadence_spi_priv { @@ -96,5 +279,11 @@ void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy); void cadence_qspi_apb_readdata_capture(void *reg_base, unsigned int bypass, unsigned int delay); unsigned int cm_get_qspi_controller_clk_hz(void); +int cadence_qspi_apb_dma_read(struct cadence_spi_plat *plat, + const struct spi_mem_op *op); +int cadence_qspi_apb_wait_for_dma_cmplt(struct cadence_spi_plat *plat); +int cadence_qspi_apb_exec_flash_cmd(void *reg_base, unsigned int reg); +int cadence_qspi_versal_flash_reset(struct udevice *dev); +void cadence_qspi_apb_enable_linear_mode(bool enable); #endif /* __CADENCE_QSPI_H__ */ diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index 2cdf4c9c9f8..c00755050e1 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -38,156 +38,10 @@ #include <malloc.h> #include "cadence_qspi.h" -#define CQSPI_REG_POLL_US 1 /* 1us */ -#define CQSPI_REG_RETRY 10000 -#define CQSPI_POLL_IDLE_RETRY 3 - -/* Transfer mode */ -#define CQSPI_INST_TYPE_SINGLE 0 -#define CQSPI_INST_TYPE_DUAL 1 -#define CQSPI_INST_TYPE_QUAD 2 -#define CQSPI_INST_TYPE_OCTAL 3 - -#define CQSPI_STIG_DATA_LEN_MAX 8 - -#define CQSPI_DUMMY_CLKS_PER_BYTE 8 -#define CQSPI_DUMMY_CLKS_MAX 31 - -/**************************************************************************** - * Controller's configuration and status register (offset from QSPI_BASE) - ****************************************************************************/ -#define CQSPI_REG_CONFIG 0x00 -#define CQSPI_REG_CONFIG_ENABLE BIT(0) -#define CQSPI_REG_CONFIG_CLK_POL BIT(1) -#define CQSPI_REG_CONFIG_CLK_PHA BIT(2) -#define CQSPI_REG_CONFIG_DIRECT BIT(7) -#define CQSPI_REG_CONFIG_DECODE BIT(9) -#define CQSPI_REG_CONFIG_XIP_IMM BIT(18) -#define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10 -#define CQSPI_REG_CONFIG_BAUD_LSB 19 -#define CQSPI_REG_CONFIG_DTR_PROTO BIT(24) -#define CQSPI_REG_CONFIG_DUAL_OPCODE BIT(30) -#define CQSPI_REG_CONFIG_IDLE_LSB 31 -#define CQSPI_REG_CONFIG_CHIPSELECT_MASK 0xF -#define CQSPI_REG_CONFIG_BAUD_MASK 0xF - -#define CQSPI_REG_RD_INSTR 0x04 -#define CQSPI_REG_RD_INSTR_OPCODE_LSB 0 -#define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB 8 -#define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB 12 -#define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB 16 -#define CQSPI_REG_RD_INSTR_MODE_EN_LSB 20 -#define CQSPI_REG_RD_INSTR_DUMMY_LSB 24 -#define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK 0x3 -#define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK 0x3 -#define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK 0x3 -#define CQSPI_REG_RD_INSTR_DUMMY_MASK 0x1F - -#define CQSPI_REG_WR_INSTR 0x08 -#define CQSPI_REG_WR_INSTR_OPCODE_LSB 0 -#define CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB 12 -#define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB 16 - -#define CQSPI_REG_DELAY 0x0C -#define CQSPI_REG_DELAY_TSLCH_LSB 0 -#define CQSPI_REG_DELAY_TCHSH_LSB 8 -#define CQSPI_REG_DELAY_TSD2D_LSB 16 -#define CQSPI_REG_DELAY_TSHSL_LSB 24 -#define CQSPI_REG_DELAY_TSLCH_MASK 0xFF -#define CQSPI_REG_DELAY_TCHSH_MASK 0xFF -#define CQSPI_REG_DELAY_TSD2D_MASK 0xFF -#define CQSPI_REG_DELAY_TSHSL_MASK 0xFF - -#define CQSPI_REG_RD_DATA_CAPTURE 0x10 -#define CQSPI_REG_RD_DATA_CAPTURE_BYPASS BIT(0) -#define CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB 1 -#define CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK 0xF - -#define CQSPI_REG_SIZE 0x14 -#define CQSPI_REG_SIZE_ADDRESS_LSB 0 -#define CQSPI_REG_SIZE_PAGE_LSB 4 -#define CQSPI_REG_SIZE_BLOCK_LSB 16 -#define CQSPI_REG_SIZE_ADDRESS_MASK 0xF -#define CQSPI_REG_SIZE_PAGE_MASK 0xFFF -#define CQSPI_REG_SIZE_BLOCK_MASK 0x3F - -#define CQSPI_REG_SRAMPARTITION 0x18 -#define CQSPI_REG_INDIRECTTRIGGER 0x1C - -#define CQSPI_REG_REMAP 0x24 -#define CQSPI_REG_MODE_BIT 0x28 - -#define CQSPI_REG_SDRAMLEVEL 0x2C -#define CQSPI_REG_SDRAMLEVEL_RD_LSB 0 -#define CQSPI_REG_SDRAMLEVEL_WR_LSB 16 -#define CQSPI_REG_SDRAMLEVEL_RD_MASK 0xFFFF -#define CQSPI_REG_SDRAMLEVEL_WR_MASK 0xFFFF - -#define CQSPI_REG_WR_COMPLETION_CTRL 0x38 -#define CQSPI_REG_WR_DISABLE_AUTO_POLL BIT(14) - -#define CQSPI_REG_IRQSTATUS 0x40 -#define CQSPI_REG_IRQMASK 0x44 - -#define CQSPI_REG_INDIRECTRD 0x60 -#define CQSPI_REG_INDIRECTRD_START BIT(0) -#define CQSPI_REG_INDIRECTRD_CANCEL BIT(1) -#define CQSPI_REG_INDIRECTRD_INPROGRESS BIT(2) -#define CQSPI_REG_INDIRECTRD_DONE BIT(5) - -#define CQSPI_REG_INDIRECTRDWATERMARK 0x64 -#define CQSPI_REG_INDIRECTRDSTARTADDR 0x68 -#define CQSPI_REG_INDIRECTRDBYTES 0x6C - -#define CQSPI_REG_CMDCTRL 0x90 -#define CQSPI_REG_CMDCTRL_EXECUTE BIT(0) -#define CQSPI_REG_CMDCTRL_INPROGRESS BIT(1) -#define CQSPI_REG_CMDCTRL_DUMMY_LSB 7 -#define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12 -#define CQSPI_REG_CMDCTRL_WR_EN_LSB 15 -#define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB 16 -#define CQSPI_REG_CMDCTRL_ADDR_EN_LSB 19 -#define CQSPI_REG_CMDCTRL_RD_BYTES_LSB 20 -#define CQSPI_REG_CMDCTRL_RD_EN_LSB 23 -#define CQSPI_REG_CMDCTRL_OPCODE_LSB 24 -#define CQSPI_REG_CMDCTRL_DUMMY_MASK 0x1F -#define CQSPI_REG_CMDCTRL_WR_BYTES_MASK 0x7 -#define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK 0x3 -#define CQSPI_REG_CMDCTRL_RD_BYTES_MASK 0x7 -#define CQSPI_REG_CMDCTRL_OPCODE_MASK 0xFF - -#define CQSPI_REG_INDIRECTWR 0x70 -#define CQSPI_REG_INDIRECTWR_START BIT(0) -#define CQSPI_REG_INDIRECTWR_CANCEL BIT(1) -#define CQSPI_REG_INDIRECTWR_INPROGRESS BIT(2) -#define CQSPI_REG_INDIRECTWR_DONE BIT(5) - -#define CQSPI_REG_INDIRECTWRWATERMARK 0x74 -#define CQSPI_REG_INDIRECTWRSTARTADDR 0x78 -#define CQSPI_REG_INDIRECTWRBYTES 0x7C - -#define CQSPI_REG_CMDADDRESS 0x94 -#define CQSPI_REG_CMDREADDATALOWER 0xA0 -#define CQSPI_REG_CMDREADDATAUPPER 0xA4 -#define CQSPI_REG_CMDWRITEDATALOWER 0xA8 -#define CQSPI_REG_CMDWRITEDATAUPPER 0xAC - -#define CQSPI_REG_OP_EXT_LOWER 0xE0 -#define CQSPI_REG_OP_EXT_READ_LSB 24 -#define CQSPI_REG_OP_EXT_WRITE_LSB 16 -#define CQSPI_REG_OP_EXT_STIG_LSB 0 - -#define CQSPI_REG_IS_IDLE(base) \ - ((readl(base + CQSPI_REG_CONFIG) >> \ - CQSPI_REG_CONFIG_IDLE_LSB) & 0x1) - -#define CQSPI_GET_RD_SRAM_LEVEL(reg_base) \ - (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >> \ - CQSPI_REG_SDRAMLEVEL_RD_LSB) & CQSPI_REG_SDRAMLEVEL_RD_MASK) - -#define CQSPI_GET_WR_SRAM_LEVEL(reg_base) \ - (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >> \ - CQSPI_REG_SDRAMLEVEL_WR_LSB) & CQSPI_REG_SDRAMLEVEL_WR_MASK) +__weak void cadence_qspi_apb_enable_linear_mode(bool enable) +{ + return; +} void cadence_qspi_apb_controller_enable(void *reg_base) { @@ -487,8 +341,7 @@ void cadence_qspi_apb_controller_init(struct cadence_spi_plat *plat) cadence_qspi_apb_controller_enable(plat->regbase); } -static int cadence_qspi_apb_exec_flash_cmd(void *reg_base, - unsigned int reg) +int cadence_qspi_apb_exec_flash_cmd(void *reg_base, unsigned int reg) { unsigned int retry = CQSPI_REG_RETRY; @@ -882,6 +735,9 @@ int cadence_qspi_apb_read_execute(struct cadence_spi_plat *plat, void *buf = op->data.buf.in; size_t len = op->data.nbytes; + if (CONFIG_IS_ENABLED(ARCH_VERSAL)) + cadence_qspi_apb_enable_linear_mode(true); + if (plat->use_dac_mode && (from + len < plat->ahbsize)) { if (len < 256 || dma_memcpy(buf, plat->ahbbase + from, len) < 0) { @@ -1049,6 +905,9 @@ int cadence_qspi_apb_write_execute(struct cadence_spi_plat *plat, const void *buf = op->data.buf.out; size_t len = op->data.nbytes; + if (CONFIG_IS_ENABLED(ARCH_VERSAL)) + cadence_qspi_apb_enable_linear_mode(true); + /* * Some flashes like the Cypress Semper flash expect a dummy 4-byte * address (all 0s) with the read status register command in DTR mode. diff --git a/drivers/usb/common/fsl-dt-fixup.c b/drivers/usb/common/fsl-dt-fixup.c index 4d7a2acd8e5..00b8cd368b1 100644 --- a/drivers/usb/common/fsl-dt-fixup.c +++ b/drivers/usb/common/fsl-dt-fixup.c @@ -16,10 +16,6 @@ #include <fsl_usb.h> #include <fdt_support.h> -#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#endif - /* USB Controllers */ #define FSL_USB2_MPH "fsl-usb2-mph" #define FSL_USB2_DR "fsl-usb2-dr" diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 8f77412cc71..7d5bde53870 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -116,11 +116,19 @@ config USB_XHCI_BRCM endif # USB_XHCI_HCD +config EHCI_DESC_BIG_ENDIAN + bool + +config EHCI_MMIO_BIG_ENDIAN + bool + config USB_EHCI_HCD bool "EHCI HCD (USB 2.0) support" default y if ARCH_MX5 || ARCH_MX6 depends on DM && OF_CONTROL select USB_HOST + select EHCI_DESC_BIG_ENDIAN if SYS_BIG_ENDIAN + select EHCI_MMIO_BIG_ENDIAN if SYS_BIG_ENDIAN ---help--- The Enhanced Host Controller Interface (EHCI) is standard for USB 2.0 "high speed" (480 Mbit/sec, 60 Mbyte/sec) host controller hardware. @@ -166,6 +174,7 @@ config USB_EHCI_MX5 config USB_EHCI_MX6 bool "Support for i.MX6/i.MX7ULP on-chip EHCI USB controller" depends on ARCH_MX6 || ARCH_MX7ULP || ARCH_IMXRT + select EHCI_HCD_INIT_AFTER_RESET default y ---help--- Enables support for the on-chip EHCI controller on i.MX6 SoCs. @@ -173,6 +182,7 @@ config USB_EHCI_MX6 config USB_EHCI_MX7 bool "Support for i.MX7 on-chip EHCI USB controller" depends on ARCH_MX7 || IMX8M + select EHCI_HCD_INIT_AFTER_RESET if ARCH_MX7 select PHY if IMX8M select NOP_PHY if IMX8M default y @@ -250,11 +260,25 @@ config USB_EHCI_GENERIC ---help--- Enables support for generic EHCI controller. +config EHCI_HCD_INIT_AFTER_RESET + bool + config USB_EHCI_FSL bool "Support for FSL on-chip EHCI USB controller" - select CONFIG_EHCI_HCD_INIT_AFTER_RESET + select EHCI_HCD_INIT_AFTER_RESET ---help--- Enables support for the on-chip EHCI controller on FSL chips. + +config USB_EHCI_TXFIFO_THRESH + hex + depends on USB_EHCI_TEGRA + default 0x10 + help + This parameter affects a TXFILLTUNING field that controls how much + data is sent to the latency fifo before it is sent to the wire. + Without this parameter, the default (2) causes occasional Data Buffer + Errors in OUT packets depending on the buffer address and size. + endif # USB_EHCI_HCD config USB_OHCI_HCD @@ -340,3 +364,9 @@ config USB_R8A66597_HCD ---help--- This enables support for the on-chip Renesas R8A66597 USB 2.0 controller, present in various RZ and SH SoCs. + +config USB_MAX_CONTROLLER_COUNT + int "Maximum number of USB host controllers" + depends on USB_EHCI_FSL || USB_XHCI_FSL || \ + (SPL_USB_HOST && !DM_SPL_USB) || (USB_HOST && !DM_USB) + default 1 diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index 7785b3744ef..5fdb8041167 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -30,7 +30,6 @@ obj-$(CONFIG_USB_EHCI_FSL) += ehci-fsl.o obj-$(CONFIG_USB_EHCI_FARADAY) += ehci-faraday.o obj-$(CONFIG_USB_EHCI_GENERIC) += ehci-generic.o obj-$(CONFIG_USB_EHCI_EXYNOS) += ehci-exynos.o -obj-$(CONFIG_USB_EHCI_MXC) += ehci-mxc.o obj-$(CONFIG_USB_EHCI_MXS) += ehci-mxs.o obj-$(CONFIG_USB_EHCI_MX5) += ehci-mx5.o obj-$(CONFIG_USB_EHCI_MX6) += ehci-mx6.o diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c index cf1f882441b..0569dd54fff 100644 --- a/drivers/usb/host/ehci-fsl.c +++ b/drivers/usb/host/ehci-fsl.c @@ -25,26 +25,15 @@ DECLARE_GLOBAL_DATA_PTR; -#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#endif - -#if CONFIG_IS_ENABLED(DM_USB) struct ehci_fsl_priv { struct ehci_ctrl ehci; fdt_addr_t hcd_base; char *phy_type; }; -#endif static void set_txfifothresh(struct usb_ehci *, u32); -#if CONFIG_IS_ENABLED(DM_USB) static int ehci_fsl_init(struct ehci_fsl_priv *priv, struct usb_ehci *ehci, struct ehci_hccr *hccr, struct ehci_hcor *hcor); -#else -static int ehci_fsl_init(int index, struct usb_ehci *ehci, - struct ehci_hccr *hccr, struct ehci_hcor *hcor); -#endif /* Check USB PHY clock valid */ static int usb_phy_clk_valid(struct usb_ehci *ehci) @@ -58,7 +47,6 @@ static int usb_phy_clk_valid(struct usb_ehci *ehci) } } -#if CONFIG_IS_ENABLED(DM_USB) static int ehci_fsl_of_to_plat(struct udevice *dev) { struct ehci_fsl_priv *priv = dev_get_priv(dev); @@ -150,64 +138,11 @@ U_BOOT_DRIVER(ehci_fsl) = { .priv_auto = sizeof(struct ehci_fsl_priv), .flags = DM_FLAG_ALLOC_PRIV_DMA, }; -#else -/* - * Create the appropriate control structures to manage - * a new EHCI host controller. - * - * Excerpts from linux ehci fsl driver. - */ -int ehci_hcd_init(int index, enum usb_init_type init, - struct ehci_hccr **hccr, struct ehci_hcor **hcor) -{ - struct ehci_ctrl *ehci_ctrl = container_of(hccr, - struct ehci_ctrl, hccr); - struct usb_ehci *ehci = NULL; - - switch (index) { - case 0: - ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR; - break; - case 1: - ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB2_ADDR; - break; - default: - printf("ERROR: wrong controller index!!\n"); - return -EINVAL; - }; - - *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); - *hcor = (struct ehci_hcor *)((uint32_t) *hccr + - HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); - ehci_ctrl->has_fsl_erratum_a005275 = has_erratum_a005275(); - - return ehci_fsl_init(index, ehci, *hccr, *hcor); -} - -/* - * Destroy the appropriate control structures corresponding - * the the EHCI host controller. - */ -int ehci_hcd_stop(int index) -{ - return 0; -} -#endif - -#if CONFIG_IS_ENABLED(DM_USB) static int ehci_fsl_init(struct ehci_fsl_priv *priv, struct usb_ehci *ehci, struct ehci_hccr *hccr, struct ehci_hcor *hcor) -#else -static int ehci_fsl_init(int index, struct usb_ehci *ehci, - struct ehci_hccr *hccr, struct ehci_hcor *hcor) -#endif { const char *phy_type = NULL; -#if !CONFIG_IS_ENABLED(DM_USB) - size_t len; - char current_usb_controller[5]; -#endif #ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY char usb_phy[5]; @@ -230,18 +165,8 @@ static int ehci_fsl_init(int index, struct usb_ehci *ehci, out_be32(&ehci->snoop2, 0x80000000 | SNOOP_SIZE_2GB); /* Init phy */ -#if CONFIG_IS_ENABLED(DM_USB) if (priv->phy_type) phy_type = priv->phy_type; -#else - memset(current_usb_controller, '\0', 5); - snprintf(current_usb_controller, sizeof(current_usb_controller), - "usb%d", index+1); - - if (hwconfig_sub(current_usb_controller, "phy_type")) - phy_type = hwconfig_subarg(current_usb_controller, - "phy_type", &len); -#endif else phy_type = env_get("usb_phy_type"); diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index e6355263cb9..f033198a7c1 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -25,10 +25,6 @@ #include "ehci.h" -#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#endif - /* * EHCI spec page 20 says that the HC may take up to 16 uFrames (= 4ms) to halt. * Let's time out after 8 to have a little safety margin on top of that. diff --git a/drivers/usb/host/ehci-mx5.c b/drivers/usb/host/ehci-mx5.c index ab863f41b24..964a53bb7c0 100644 --- a/drivers/usb/host/ehci-mx5.c +++ b/drivers/usb/host/ehci-mx5.c @@ -228,52 +228,6 @@ __weak void mx5_ehci_powerup_fixup(struct ehci_ctrl *ctrl, uint32_t *status_reg, mdelay(50); } -#if !CONFIG_IS_ENABLED(DM_USB) -static const struct ehci_ops mx5_ehci_ops = { - .powerup_fixup = mx5_ehci_powerup_fixup, -}; - -int ehci_hcd_init(int index, enum usb_init_type init, - struct ehci_hccr **hccr, struct ehci_hcor **hcor) -{ - struct usb_ehci *ehci; - - /* The only user for this is efikamx-usb */ - ehci_set_controller_priv(index, NULL, &mx5_ehci_ops); - set_usboh3_clk(); - enable_usboh3_clk(true); - set_usb_phy_clk(); - enable_usb_phy1_clk(true); - enable_usb_phy2_clk(true); - mdelay(1); - - /* Do board specific initialization */ - board_ehci_hcd_init(CONFIG_MXC_USB_PORT); - - ehci = (struct usb_ehci *)(OTG_BASE_ADDR + - (0x200 * CONFIG_MXC_USB_PORT)); - *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); - *hcor = (struct ehci_hcor *)((uint32_t)*hccr + - HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); - setbits_le32(&ehci->usbmode, CM_HOST); - - __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc); - setbits_le32(&ehci->portsc, USB_EN); - - mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS); - mdelay(10); - - /* Do board specific post-initialization */ - board_ehci_hcd_postinit(ehci, CONFIG_MXC_USB_PORT); - - return 0; -} - -int ehci_hcd_stop(int index) -{ - return 0; -} -#else /* CONFIG_IS_ENABLED(DM_USB) */ struct ehci_mx5_priv_data { struct ehci_ctrl ctrl; struct usb_ehci *ehci; @@ -372,4 +326,3 @@ U_BOOT_DRIVER(usb_mx5) = { .priv_auto = sizeof(struct ehci_mx5_priv_data), .flags = DM_FLAG_ALLOC_PRIV_DMA, }; -#endif /* !CONFIG_IS_ENABLED(DM_USB) */ diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c deleted file mode 100644 index 1fb685e58d8..00000000000 --- a/drivers/usb/host/ehci-mxc.c +++ /dev/null @@ -1,148 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de> - */ - - -#include <common.h> -#include <usb.h> -#include <asm/io.h> -#include <asm/arch/imx-regs.h> -#include <linux/delay.h> -#include <usb/ehci-ci.h> -#include <errno.h> - -#include "ehci.h" - -#define USBCTRL_OTGBASE_OFFSET 0x600 - -#define MX25_OTG_SIC_SHIFT 29 -#define MX25_OTG_SIC_MASK (0x3 << MX25_OTG_SIC_SHIFT) -#define MX25_OTG_PM_BIT (1 << 24) -#define MX25_OTG_PP_BIT (1 << 11) -#define MX25_OTG_OCPOL_BIT (1 << 3) - -#define MX25_H1_SIC_SHIFT 21 -#define MX25_H1_SIC_MASK (0x3 << MX25_H1_SIC_SHIFT) -#define MX25_H1_PP_BIT (1 << 18) -#define MX25_H1_PM_BIT (1 << 16) -#define MX25_H1_IPPUE_UP_BIT (1 << 7) -#define MX25_H1_IPPUE_DOWN_BIT (1 << 6) -#define MX25_H1_TLL_BIT (1 << 5) -#define MX25_H1_USBTE_BIT (1 << 4) -#define MX25_H1_OCPOL_BIT (1 << 2) - -#define MX31_OTG_SIC_SHIFT 29 -#define MX31_OTG_SIC_MASK (0x3 << MX31_OTG_SIC_SHIFT) -#define MX31_OTG_PM_BIT (1 << 24) - -#define MX31_H2_SIC_SHIFT 21 -#define MX31_H2_SIC_MASK (0x3 << MX31_H2_SIC_SHIFT) -#define MX31_H2_PM_BIT (1 << 16) -#define MX31_H2_DT_BIT (1 << 5) - -#define MX31_H1_SIC_SHIFT 13 -#define MX31_H1_SIC_MASK (0x3 << MX31_H1_SIC_SHIFT) -#define MX31_H1_PM_BIT (1 << 8) -#define MX31_H1_DT_BIT (1 << 4) - -#define MX35_OTG_SIC_SHIFT 29 -#define MX35_OTG_SIC_MASK (0x3 << MX35_OTG_SIC_SHIFT) -#define MX35_OTG_PM_BIT (1 << 24) -#define MX35_OTG_PP_BIT (1 << 11) -#define MX35_OTG_OCPOL_BIT (1 << 3) - -#define MX35_H1_SIC_SHIFT 21 -#define MX35_H1_SIC_MASK (0x3 << MX35_H1_SIC_SHIFT) -#define MX35_H1_PP_BIT (1 << 18) -#define MX35_H1_PM_BIT (1 << 16) -#define MX35_H1_IPPUE_UP_BIT (1 << 7) -#define MX35_H1_IPPUE_DOWN_BIT (1 << 6) -#define MX35_H1_TLL_BIT (1 << 5) -#define MX35_H1_USBTE_BIT (1 << 4) -#define MX35_H1_OCPOL_BIT (1 << 2) - -static int mxc_set_usbcontrol(int port, unsigned int flags) -{ - unsigned int v; - - v = readl(IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET); -#if defined(CONFIG_MX31) - switch (port) { - case 0: /* OTG port */ - v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT); - v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_OTG_SIC_SHIFT; - - if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) - v |= MX31_OTG_PM_BIT; - - break; - case 1: /* H1 port */ - v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT | MX31_H1_DT_BIT); - v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H1_SIC_SHIFT; - - if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) - v |= MX31_H1_PM_BIT; - - if (!(flags & MXC_EHCI_TTL_ENABLED)) - v |= MX31_H1_DT_BIT; - - break; - case 2: /* H2 port */ - v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT | MX31_H2_DT_BIT); - v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H2_SIC_SHIFT; - - if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) - v |= MX31_H2_PM_BIT; - - if (!(flags & MXC_EHCI_TTL_ENABLED)) - v |= MX31_H2_DT_BIT; - - break; - default: - return -EINVAL; - } -#else -#error MXC EHCI USB driver not supported on this platform -#endif - writel(v, IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET); - - return 0; -} - -int ehci_hcd_init(int index, enum usb_init_type init, - struct ehci_hccr **hccr, struct ehci_hcor **hcor) -{ - struct usb_ehci *ehci; -#ifdef CONFIG_MX31 - struct clock_control_regs *sc_regs = - (struct clock_control_regs *)CCM_BASE; - - __raw_readl(&sc_regs->ccmr); - __raw_writel(__raw_readl(&sc_regs->ccmr) | (1 << 9), &sc_regs->ccmr) ; -#endif - - udelay(80); - - ehci = (struct usb_ehci *)(IMX_USB_BASE + - IMX_USB_PORT_OFFSET * CONFIG_MXC_USB_PORT); - *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); - *hcor = (struct ehci_hcor *)((uint32_t) *hccr + - HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); - setbits_le32(&ehci->usbmode, CM_HOST); - __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc); - mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS); - - udelay(10000); - - return 0; -} - -/* - * Destroy the appropriate control structures corresponding - * the the EHCI host controller. - */ -int ehci_hcd_stop(int index) -{ - return 0; -} diff --git a/drivers/usb/host/ehci-mxs.c b/drivers/usb/host/ehci-mxs.c index 9a614955fc1..147b2fa145d 100644 --- a/drivers/usb/host/ehci-mxs.c +++ b/drivers/usb/host/ehci-mxs.c @@ -112,82 +112,6 @@ static int __ehci_hcd_stop(struct ehci_mxs_port *port) return ehci_mxs_toggle_clock(port, 0); } -#if !CONFIG_IS_ENABLED(DM_USB) -static const struct ehci_mxs_port mxs_port[] = { -#ifdef CONFIG_EHCI_MXS_PORT0 - { - MXS_USBCTRL0_BASE, - (struct mxs_usbphy_regs *)MXS_USBPHY0_BASE, - (struct mxs_register_32 *)(MXS_CLKCTRL_BASE + - offsetof(struct mxs_clkctrl_regs, - hw_clkctrl_pll0ctrl0_reg)), - CLKCTRL_PLL0CTRL0_EN_USB_CLKS | CLKCTRL_PLL0CTRL0_POWER, - CLKCTRL_PLL0CTRL0_EN_USB_CLKS, - HW_DIGCTL_CTRL_USB0_CLKGATE, - }, -#endif -#ifdef CONFIG_EHCI_MXS_PORT1 - { - MXS_USBCTRL1_BASE, - (struct mxs_usbphy_regs *)MXS_USBPHY1_BASE, - (struct mxs_register_32 *)(MXS_CLKCTRL_BASE + - offsetof(struct mxs_clkctrl_regs, - hw_clkctrl_pll1ctrl0_reg)), - CLKCTRL_PLL1CTRL0_EN_USB_CLKS | CLKCTRL_PLL1CTRL0_POWER, - CLKCTRL_PLL1CTRL0_EN_USB_CLKS, - HW_DIGCTL_CTRL_USB1_CLKGATE, - }, -#endif -}; - -int __weak board_ehci_hcd_init(int port) -{ - return 0; -} - -int __weak board_ehci_hcd_exit(int port) -{ - return 0; -} - -int ehci_hcd_init(int index, enum usb_init_type init, - struct ehci_hccr **hccr, struct ehci_hcor **hcor) -{ - - int ret; - const struct ehci_mxs_port *port; - - if ((index < 0) || (index >= ARRAY_SIZE(mxs_port))) { - printf("Invalid port index (index = %d)!\n", index); - return -EINVAL; - } - - ret = board_ehci_hcd_init(index); - if (ret) - return ret; - - port = &mxs_port[index]; - return __ehci_hcd_init(port, init, hccr, hcor); -} - -int ehci_hcd_stop(int index) -{ - int ret; - const struct ehci_mxs_port *port; - - if ((index < 0) || (index >= ARRAY_SIZE(mxs_port))) { - printf("Invalid port index (index = %d)!\n", index); - return -EINVAL; - } - - port = &mxs_port[index]; - - ret = __ehci_hcd_stop(port); - board_ehci_hcd_exit(index); - - return ret; -} -#else /* CONFIG_IS_ENABLED(DM_USB) */ struct ehci_mxs_priv_data { struct ehci_ctrl ctrl; struct usb_ehci *ehci; @@ -367,4 +291,3 @@ U_BOOT_DRIVER(usb_mxs) = { .priv_auto = sizeof(struct ehci_mxs_priv_data), .flags = DM_FLAG_ALLOC_PRIV_DMA, }; -#endif /* !CONFIG_IS_ENABLED(DM_USB) */ diff --git a/drivers/usb/host/xhci-fsl.c b/drivers/usb/host/xhci-fsl.c index 80871908dc1..e67e09e31e4 100644 --- a/drivers/usb/host/xhci-fsl.c +++ b/drivers/usb/host/xhci-fsl.c @@ -20,16 +20,11 @@ #include <dm.h> /* Declare global data pointer */ -#if !CONFIG_IS_ENABLED(DM_USB) -static struct fsl_xhci fsl_xhci; -unsigned long ctr_addr[] = FSL_USB_XHCI_ADDR; -#else struct xhci_fsl_priv { struct xhci_ctrl xhci; fdt_addr_t hcd_base; struct fsl_xhci ctx; }; -#endif __weak int __board_usb_init(int index, enum usb_init_type init) { @@ -108,7 +103,6 @@ static int fsl_xhci_core_exit(struct fsl_xhci *fsl_xhci) return 0; } -#if CONFIG_IS_ENABLED(DM_USB) static int xhci_fsl_probe(struct udevice *dev) { struct xhci_fsl_priv *priv = dev_get_priv(dev); @@ -174,44 +168,3 @@ U_BOOT_DRIVER(xhci_fsl) = { .priv_auto = sizeof(struct xhci_fsl_priv), .flags = DM_FLAG_ALLOC_PRIV_DMA, }; -#else -int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor) -{ - struct fsl_xhci *ctx = &fsl_xhci; - int ret = 0; - - ctx->hcd = (struct xhci_hccr *)ctr_addr[index]; - ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET); - - ret = board_usb_init(index, USB_INIT_HOST); - if (ret != 0) { - puts("Failed to initialize board for USB\n"); - return ret; - } - - fsl_apply_xhci_errata(); - - ret = fsl_xhci_core_init(ctx); - if (ret < 0) { - puts("Failed to initialize xhci\n"); - return ret; - } - - *hccr = (struct xhci_hccr *)ctx->hcd; - *hcor = (struct xhci_hcor *)((uintptr_t) *hccr - + HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase))); - - debug("fsl-xhci: init hccr %lx and hcor %lx hc_length %lx\n", - (uintptr_t)*hccr, (uintptr_t)*hcor, - (uintptr_t)HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase))); - - return ret; -} - -void xhci_hcd_stop(int index) -{ - struct fsl_xhci *ctx = &fsl_xhci; - - fsl_xhci_core_exit(ctx); -} -#endif diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c index ad73ba12e2b..dbeb88afe37 100644 --- a/drivers/usb/host/xhci.c +++ b/drivers/usb/host/xhci.c @@ -37,10 +37,6 @@ #include <linux/errno.h> #include <linux/iopoll.h> -#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#endif - static struct descriptor { struct usb_hub_descriptor hub; struct usb_device_descriptor device; @@ -115,13 +111,8 @@ static struct descriptor { }, }; -#if !CONFIG_IS_ENABLED(DM_USB) -static struct xhci_ctrl xhcic[CONFIG_USB_MAX_CONTROLLER_COUNT]; -#endif - struct xhci_ctrl *xhci_get_ctrl(struct usb_device *udev) { -#if CONFIG_IS_ENABLED(DM_USB) struct udevice *dev; /* Find the USB controller */ @@ -130,9 +121,6 @@ struct xhci_ctrl *xhci_get_ctrl(struct usb_device *udev) dev = dev->parent) ; return dev_get_priv(dev); -#else - return udev->controller; -#endif } /** @@ -752,13 +740,6 @@ static int _xhci_alloc_device(struct usb_device *udev) return 0; } -#if !CONFIG_IS_ENABLED(DM_USB) -int usb_alloc_device(struct usb_device *udev) -{ - return _xhci_alloc_device(udev); -} -#endif - /* * Full speed devices may have a max packet size greater than 8 bytes, but the * USB core doesn't know that until it reads the first 8 bytes of the @@ -1267,95 +1248,6 @@ static int xhci_lowlevel_stop(struct xhci_ctrl *ctrl) return 0; } -#if !CONFIG_IS_ENABLED(DM_USB) -int submit_control_msg(struct usb_device *udev, unsigned long pipe, - void *buffer, int length, struct devrequest *setup) -{ - struct usb_device *hop = udev; - - if (hop->parent) - while (hop->parent->parent) - hop = hop->parent; - - return _xhci_submit_control_msg(udev, pipe, buffer, length, setup, - hop->portnr); -} - -int submit_bulk_msg(struct usb_device *udev, unsigned long pipe, void *buffer, - int length) -{ - return _xhci_submit_bulk_msg(udev, pipe, buffer, length); -} - -int submit_int_msg(struct usb_device *udev, unsigned long pipe, void *buffer, - int length, int interval, bool nonblock) -{ - return _xhci_submit_int_msg(udev, pipe, buffer, length, interval, - nonblock); -} - -/** - * Intialises the XHCI host controller - * and allocates the necessary data structures - * - * @param index index to the host controller data structure - * Return: pointer to the intialised controller - */ -int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) -{ - struct xhci_hccr *hccr; - struct xhci_hcor *hcor; - struct xhci_ctrl *ctrl; - int ret; - - *controller = NULL; - - if (xhci_hcd_init(index, &hccr, (struct xhci_hcor **)&hcor) != 0) - return -ENODEV; - - if (xhci_reset(hcor) != 0) - return -ENODEV; - - ctrl = &xhcic[index]; - - ctrl->hccr = hccr; - ctrl->hcor = hcor; - - ret = xhci_lowlevel_init(ctrl); - - if (ret) { - ctrl->hccr = NULL; - ctrl->hcor = NULL; - } else { - *controller = &xhcic[index]; - } - - return ret; -} - -/** - * Stops the XHCI host controller - * and cleans up all the related data structures - * - * @param index index to the host controller data structure - * Return: none - */ -int usb_lowlevel_stop(int index) -{ - struct xhci_ctrl *ctrl = (xhcic + index); - - if (ctrl->hcor) { - xhci_lowlevel_stop(ctrl); - xhci_hcd_stop(index); - xhci_cleanup(ctrl); - } - - return 0; -} -#endif /* CONFIG_IS_ENABLED(DM_USB) */ - -#if CONFIG_IS_ENABLED(DM_USB) - static int xhci_submit_control_msg(struct udevice *dev, struct usb_device *udev, unsigned long pipe, void *buffer, int length, struct devrequest *setup) @@ -1546,5 +1438,3 @@ struct dm_usb_ops xhci_usb_ops = { .update_hub_device = xhci_update_hub_device, .get_max_xfer_size = xhci_get_max_xfer_size, }; - -#endif diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 965b5879274..4ecc158c460 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -583,6 +583,8 @@ config ATMEL_HLCD source "drivers/video/ti/Kconfig" +source "drivers/video/exynos/Kconfig" + config LOGICORE_DP_TX bool "Enable Logicore DP TX driver" depends on DISPLAY diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 259658074bc..63d8dbe3c85 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -38,7 +38,6 @@ obj-$(CONFIG_NXP_TDA19988) += tda19988.o obj-$(CONFIG_OSD) += video_osd-uclass.o obj-$(CONFIG_PXA_LCD) += pxa_lcd.o obj-$(CONFIG_SANDBOX_OSD) += sandbox_osd.o -obj-$(CONFIG_S6E8AX0) += s6e8ax0.o obj-$(CONFIG_SCF0403_LCD) += scf0403_lcd.o obj-$(CONFIG_VIDEO_ARM_MALIDP) += mali_dp.o obj-$(CONFIG_VIDEO_BCM2835) += bcm2835.o diff --git a/drivers/video/exynos/Kconfig b/drivers/video/exynos/Kconfig new file mode 100644 index 00000000000..37e661b1edd --- /dev/null +++ b/drivers/video/exynos/Kconfig @@ -0,0 +1,20 @@ + +menuconfig VIDEO_EXYNOS + bool "Enable Exynos video support" + depends on DM_VIDEO + help + Enable support for various video output options on Exynos SoCs. + +if VIDEO_EXYNOS + +config EXYNOS_DP + bool "Exynos Display Port support" + +config EXYNOS_FB + bool "Exynos FIMD support" + +config EXYNOS_MIPI_DSIM + bool "Exynos MIPI DSI support" + depends on EXYNOS_FB + +endif diff --git a/drivers/video/exynos/exynos_pwm_bl.c b/drivers/video/exynos/exynos_pwm_bl.c deleted file mode 100644 index a3d467aa23b..00000000000 --- a/drivers/video/exynos/exynos_pwm_bl.c +++ /dev/null @@ -1,44 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * PWM BACKLIGHT driver for Board based on EXYNOS. - * - * Author: Donghwa Lee <dh09.lee@samsung.com> - * - * Derived from linux/drivers/video/backlight/pwm_backlight.c - */ - -#include <common.h> -#include <pwm.h> -#include <linux/types.h> -#include <asm/io.h> -#include <asm/arch/cpu.h> -#include <asm/arch/gpio.h> -#include <asm/arch/pwm.h> -#include <asm/arch/pwm_backlight.h> - -static struct pwm_backlight_data *pwm; - -static int exynos_pwm_backlight_update_status(void) -{ - int brightness = pwm->brightness; - int max = pwm->max_brightness; - - if (brightness == 0) { - pwm_config(pwm->pwm_id, 0, pwm->period); - pwm_disable(pwm->pwm_id); - } else { - pwm_config(pwm->pwm_id, - brightness * pwm->period / max, pwm->period); - pwm_enable(pwm->pwm_id); - } - return 0; -} - -int exynos_pwm_backlight_init(struct pwm_backlight_data *pd) -{ - pwm = pd; - - exynos_pwm_backlight_update_status(); - - return 0; -} diff --git a/drivers/video/s6e8ax0.c b/drivers/video/s6e8ax0.c deleted file mode 100644 index 497258f3de9..00000000000 --- a/drivers/video/s6e8ax0.c +++ /dev/null @@ -1,265 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2012 Samsung Electronics - * - * Author: Donghwa Lee <dh09.lee@samsung.com> - */ - -#include <common.h> -#include <asm/arch/mipi_dsim.h> -#include <linux/delay.h> - -#include "exynos/exynos_mipi_dsi_lowlevel.h" -#include "exynos/exynos_mipi_dsi_common.h" - -static void s6e8ax0_panel_cond(struct mipi_dsim_device *dsim_dev) -{ - struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; - int reverse = dsim_dev->dsim_lcd_dev->reverse_panel; - static const unsigned char data_to_send[] = { - 0xf8, 0x3d, 0x35, 0x00, 0x00, 0x00, 0x8d, 0x00, 0x4c, - 0x6e, 0x10, 0x27, 0x7d, 0x3f, 0x10, 0x00, 0x00, 0x20, - 0x04, 0x08, 0x6e, 0x00, 0x00, 0x00, 0x02, 0x08, 0x08, - 0x23, 0x23, 0xc0, 0xc8, 0x08, 0x48, 0xc1, 0x00, 0xc3, - 0xff, 0xff, 0xc8 - }; - - static const unsigned char data_to_send_reverse[] = { - 0xf8, 0x19, 0x35, 0x00, 0x00, 0x00, 0x93, 0x00, 0x3c, - 0x7d, 0x08, 0x27, 0x7d, 0x3f, 0x00, 0x00, 0x00, 0x20, - 0x04, 0x08, 0x6e, 0x00, 0x00, 0x00, 0x02, 0x08, 0x08, - 0x23, 0x23, 0xc0, 0xc1, 0x01, 0x41, 0xc1, 0x00, 0xc1, - 0xf6, 0xf6, 0xc1 - }; - - if (reverse) { - ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, - data_to_send_reverse, - ARRAY_SIZE(data_to_send_reverse)); - } else { - ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, - data_to_send, ARRAY_SIZE(data_to_send)); - } -} - -static void s6e8ax0_display_cond(struct mipi_dsim_device *dsim_dev) -{ - struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; - static const unsigned char data_to_send[] = { - 0xf2, 0x80, 0x03, 0x0d - }; - - ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, - data_to_send, ARRAY_SIZE(data_to_send)); -} - -static void s6e8ax0_gamma_cond(struct mipi_dsim_device *dsim_dev) -{ - struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; - /* 7500K 2.2 Set : 30cd */ - static const unsigned char data_to_send[] = { - 0xfa, 0x01, 0x60, 0x10, 0x60, 0xf5, 0x00, 0xff, 0xad, - 0xaf, 0xba, 0xc3, 0xd8, 0xc5, 0x9f, 0xc6, 0x9e, 0xc1, - 0xdc, 0xc0, 0x00, 0x61, 0x00, 0x5a, 0x00, 0x74, - }; - - ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, - data_to_send, ARRAY_SIZE(data_to_send)); -} - -static void s6e8ax0_gamma_update(struct mipi_dsim_device *dsim_dev) -{ - struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; - static const unsigned char data_to_send[] = { - 0xf7, 0x03 - }; - - ops->cmd_write(dsim_dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, data_to_send, - ARRAY_SIZE(data_to_send)); -} - -static void s6e8ax0_etc_source_control(struct mipi_dsim_device *dsim_dev) -{ - struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; - static const unsigned char data_to_send[] = { - 0xf6, 0x00, 0x02, 0x00 - }; - - ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, - data_to_send, ARRAY_SIZE(data_to_send)); -} - -static void s6e8ax0_etc_pentile_control(struct mipi_dsim_device *dsim_dev) -{ - struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; - static const unsigned char data_to_send[] = { - 0xb6, 0x0c, 0x02, 0x03, 0x32, 0xff, 0x44, 0x44, 0xc0, - 0x00 - }; - - ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, - data_to_send, ARRAY_SIZE(data_to_send)); -} - -static void s6e8ax0_etc_mipi_control1(struct mipi_dsim_device *dsim_dev) -{ - struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; - static const unsigned char data_to_send[] = { - 0xe1, 0x10, 0x1c, 0x17, 0x08, 0x1d - }; - - ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, - data_to_send, ARRAY_SIZE(data_to_send)); -} - -static void s6e8ax0_etc_mipi_control2(struct mipi_dsim_device *dsim_dev) -{ - struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; - static const unsigned char data_to_send[] = { - 0xe2, 0xed, 0x07, 0xc3, 0x13, 0x0d, 0x03 - }; - - ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, - data_to_send, ARRAY_SIZE(data_to_send)); -} - -static void s6e8ax0_etc_power_control(struct mipi_dsim_device *dsim_dev) -{ - struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; - static const unsigned char data_to_send[] = { - 0xf4, 0xcf, 0x0a, 0x12, 0x10, 0x19, 0x33, 0x02 - }; - - ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, - data_to_send, ARRAY_SIZE(data_to_send)); -} - -static void s6e8ax0_etc_mipi_control3(struct mipi_dsim_device *dsim_dev) -{ - struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; - static const unsigned char data_to_send[] = { - 0xe3, 0x40 - }; - - ops->cmd_write(dsim_dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, data_to_send, - ARRAY_SIZE(data_to_send)); -} - -static void s6e8ax0_etc_mipi_control4(struct mipi_dsim_device *dsim_dev) -{ - struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; - static const unsigned char data_to_send[] = { - 0xe4, 0x00, 0x00, 0x14, 0x80, 0x00, 0x00, 0x00 - }; - - ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, - data_to_send, ARRAY_SIZE(data_to_send)); -} - -static void s6e8ax0_elvss_set(struct mipi_dsim_device *dsim_dev) -{ - struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; - static const unsigned char data_to_send[] = { - 0xb1, 0x04, 0x00 - }; - - ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, - data_to_send, ARRAY_SIZE(data_to_send)); -} - -static void s6e8ax0_display_on(struct mipi_dsim_device *dsim_dev) -{ - struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; - static const unsigned char data_to_send[] = { - 0x29, 0x00 - }; - - ops->cmd_write(dsim_dev, MIPI_DSI_DCS_SHORT_WRITE, data_to_send, - ARRAY_SIZE(data_to_send)); -} - -static void s6e8ax0_sleep_out(struct mipi_dsim_device *dsim_dev) -{ - struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; - static const unsigned char data_to_send[] = { - 0x11, 0x00 - }; - - ops->cmd_write(dsim_dev, MIPI_DSI_DCS_SHORT_WRITE, data_to_send, - ARRAY_SIZE(data_to_send)); -} - -static void s6e8ax0_apply_level1_key(struct mipi_dsim_device *dsim_dev) -{ - struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; - static const unsigned char data_to_send[] = { - 0xf0, 0x5a, 0x5a - }; - - ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, - data_to_send, ARRAY_SIZE(data_to_send)); -} - -static void s6e8ax0_apply_mtp_key(struct mipi_dsim_device *dsim_dev) -{ - struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; - static const unsigned char data_to_send[] = { - 0xf1, 0x5a, 0x5a - }; - - ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, - data_to_send, ARRAY_SIZE(data_to_send)); -} - -static void s6e8ax0_panel_init(struct mipi_dsim_device *dsim_dev) -{ - /* - * in case of setting gamma and panel condition at first, - * it shuold be setting like below. - * set_gamma() -> set_panel_condition() - */ - - s6e8ax0_apply_level1_key(dsim_dev); - s6e8ax0_apply_mtp_key(dsim_dev); - - s6e8ax0_sleep_out(dsim_dev); - mdelay(5); - s6e8ax0_panel_cond(dsim_dev); - s6e8ax0_display_cond(dsim_dev); - s6e8ax0_gamma_cond(dsim_dev); - s6e8ax0_gamma_update(dsim_dev); - - s6e8ax0_etc_source_control(dsim_dev); - s6e8ax0_elvss_set(dsim_dev); - s6e8ax0_etc_pentile_control(dsim_dev); - s6e8ax0_etc_mipi_control1(dsim_dev); - s6e8ax0_etc_mipi_control2(dsim_dev); - s6e8ax0_etc_power_control(dsim_dev); - s6e8ax0_etc_mipi_control3(dsim_dev); - s6e8ax0_etc_mipi_control4(dsim_dev); -} - -static int s6e8ax0_panel_set(struct mipi_dsim_device *dsim_dev) -{ - s6e8ax0_panel_init(dsim_dev); - - return 0; -} - -static void s6e8ax0_display_enable(struct mipi_dsim_device *dsim_dev) -{ - s6e8ax0_display_on(dsim_dev); -} - -static struct mipi_dsim_lcd_driver s6e8ax0_dsim_ddi_driver = { - .name = "s6e8ax0", - .id = -1, - - .mipi_panel_init = s6e8ax0_panel_set, - .mipi_display_on = s6e8ax0_display_enable, -}; - -void s6e8ax0_init(void) -{ - exynos_mipi_dsi_register_lcd_driver(&s6e8ax0_dsim_ddi_driver); -} |