diff options
Diffstat (limited to 'drivers')
96 files changed, 3141 insertions, 1209 deletions
diff --git a/drivers/Makefile b/drivers/Makefile index 15d19d0c8a3..58be410135d 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -18,7 +18,6 @@ obj-$(CONFIG_$(SPL_TPL_)INPUT) += input/ obj-$(CONFIG_$(SPL_TPL_)LED) += led/ obj-$(CONFIG_$(SPL_TPL_)MMC) += mmc/ obj-y += mtd/ -obj-$(CONFIG_$(SPL_)MULTIPLEXER) += mux/ obj-$(CONFIG_$(SPL_TPL_)ETH) += net/ obj-$(CONFIG_$(SPL_TPL_)PCH) += pch/ obj-$(CONFIG_$(SPL_TPL_)PCI) += pci/ @@ -87,6 +86,7 @@ obj-$(CONFIG_FASTBOOT) += fastboot/ obj-$(CONFIG_FWU_MDATA) += fwu-mdata/ obj-y += misc/ obj-$(CONFIG_MMC) += mmc/ +obj-$(CONFIG_MULTIPLEXER) += mux/ obj-$(CONFIG_NVME) += nvme/ obj-$(CONFIG_PCI_ENDPOINT) += pci_endpoint/ obj-y += dfu/ diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 09aa97ee8c0..42280cbf83a 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -185,7 +185,7 @@ config CLK_VERSACLOCK config CLK_VERSAL bool "Enable clock driver support for Versal" depends on (ARCH_VERSAL || ARCH_VERSAL_NET) - select ZYNQMP_FIRMWARE + imply ZYNQMP_FIRMWARE help This clock driver adds support for clock realted settings for Versal platform. @@ -219,7 +219,7 @@ config CLK_ZYNQ config CLK_ZYNQMP bool "Enable clock driver support for ZynqMP" depends on ARCH_ZYNQMP - select ZYNQMP_FIRMWARE + imply ZYNQMP_FIRMWARE help This clock driver adds support for clock realted settings for ZynqMP platform. diff --git a/drivers/clk/aspeed/clk_ast2600.c b/drivers/clk/aspeed/clk_ast2600.c index 0df1dc3718d..e5ada5b6d49 100644 --- a/drivers/clk/aspeed/clk_ast2600.c +++ b/drivers/clk/aspeed/clk_ast2600.c @@ -538,7 +538,7 @@ static uint32_t ast2600_configure_pll(struct ast2600_scu *scu, } p_cfg->reg.b.bypass = 0; - p_cfg->reg.b.off = 1; + p_cfg->reg.b.off = 0; p_cfg->reg.b.reset = 1; reg = readl(addr); @@ -549,7 +549,6 @@ static uint32_t ast2600_configure_pll(struct ast2600_scu *scu, /* write extend parameter */ writel(p_cfg->ext_reg, addr_ext); udelay(100); - p_cfg->reg.b.off = 0; p_cfg->reg.b.reset = 0; reg &= ~GENMASK(25, 0); reg |= p_cfg->reg.w; diff --git a/drivers/clk/at91/Kconfig b/drivers/clk/at91/Kconfig index 4abc8026b4d..4563892647b 100644 --- a/drivers/clk/at91/Kconfig +++ b/drivers/clk/at91/Kconfig @@ -61,3 +61,10 @@ config AT91_SAM9X60_PLL help This option is used to enable the AT91 SAM9X60's PLL clock driver. + +config AT91_SAM9X60_USB + bool "USB Clock support for SAM9X60 SoCs" + depends on CLK_AT91 + help + This option is used to enable the AT91 SAM9X60's USB clock + driver. diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile index 580b406d7bd..e53dcb4ca7a 100644 --- a/drivers/clk/at91/Makefile +++ b/drivers/clk/at91/Makefile @@ -9,6 +9,7 @@ obj-y += clk-peripheral.o obj-$(CONFIG_AT91_GENERIC_CLK) += clk-generic.o obj-$(CONFIG_AT91_UTMI) += clk-utmi.o obj-$(CONFIG_AT91_SAM9X60_PLL) += clk-sam9x60-pll.o +obj-$(CONFIG_AT91_SAM9X60_USB) += clk-sam9x60-usb.o obj-$(CONFIG_SAMA7G5) += sama7g5.o obj-$(CONFIG_SAM9X60) += sam9x60.o else diff --git a/drivers/clk/at91/clk-sam9x60-usb.c b/drivers/clk/at91/clk-sam9x60-usb.c new file mode 100644 index 00000000000..798fa9eb3cc --- /dev/null +++ b/drivers/clk/at91/clk-sam9x60-usb.c @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * SAM9X60's USB Clock support. + * + * Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries + * + * Author: Sergiu Moga <sergiu.moga@microchip.com> + */ + +#include <clk-uclass.h> +#include <dm.h> +#include <linux/clk-provider.h> + +#include "pmc.h" + +#define UBOOT_DM_CLK_AT91_SAM9X60_USB "at91-sam9x60-usb-clk" + +struct sam9x60_usb { + const struct clk_usbck_layout *layout; + void __iomem *base; + struct clk clk; + const u32 *clk_mux_table; + const u32 *mux_table; + const char * const *parent_names; + u32 num_parents; + u8 id; +}; + +#define to_sam9x60_usb(_clk) container_of(_clk, struct sam9x60_usb, clk) +#define USB_MAX_DIV 15 + +static int sam9x60_usb_clk_set_parent(struct clk *clk, struct clk *parent) +{ + struct sam9x60_usb *usb = to_sam9x60_usb(clk); + int index; + u32 val; + + index = at91_clk_mux_val_to_index(usb->clk_mux_table, usb->num_parents, + parent->id); + if (index < 0) + return index; + + index = at91_clk_mux_index_to_val(usb->mux_table, usb->num_parents, + index); + if (index < 0) + return index; + + pmc_read(usb->base, usb->layout->offset, &val); + val &= ~usb->layout->usbs_mask; + val |= index << (ffs(usb->layout->usbs_mask - 1)); + pmc_write(usb->base, usb->layout->offset, val); + + return 0; +} + +static ulong sam9x60_usb_clk_get_rate(struct clk *clk) +{ + struct sam9x60_usb *usb = to_sam9x60_usb(clk); + ulong parent_rate = clk_get_parent_rate(clk); + u32 val, usbdiv; + + if (!parent_rate) + return 0; + + pmc_read(usb->base, usb->layout->offset, &val); + usbdiv = (val & usb->layout->usbdiv_mask) >> + (ffs(usb->layout->usbdiv_mask) - 1); + return parent_rate / (usbdiv + 1); +} + +static ulong sam9x60_usb_clk_set_rate(struct clk *clk, ulong rate) +{ + struct sam9x60_usb *usb = to_sam9x60_usb(clk); + ulong parent_rate = clk_get_parent_rate(clk); + u32 usbdiv, val; + + if (!parent_rate) + return 0; + + usbdiv = DIV_ROUND_CLOSEST(parent_rate, rate); + if (usbdiv > USB_MAX_DIV + 1 || !usbdiv) + return 0; + + pmc_read(usb->base, usb->layout->offset, &val); + val &= usb->layout->usbdiv_mask; + val |= (usbdiv - 1) << (ffs(usb->layout->usbdiv_mask) - 1); + pmc_write(usb->base, usb->layout->offset, val); + + return parent_rate / usbdiv; +} + +static const struct clk_ops sam9x60_usb_ops = { + .set_parent = sam9x60_usb_clk_set_parent, + .set_rate = sam9x60_usb_clk_set_rate, + .get_rate = sam9x60_usb_clk_get_rate, +}; + +struct clk * +sam9x60_clk_register_usb(void __iomem *base, const char *name, + const char * const *parent_names, u8 num_parents, + const struct clk_usbck_layout *usbck_layout, + const u32 *clk_mux_table, const u32 *mux_table, u8 id) +{ + struct sam9x60_usb *usb; + struct clk *clk; + int ret, index; + u32 val; + + if (!base || !name || !parent_names || !num_parents || + !clk_mux_table || !mux_table) + return ERR_PTR(-EINVAL); + + usb = kzalloc(sizeof(*usb), GFP_KERNEL); + if (!usb) + return ERR_PTR(-ENOMEM); + + usb->id = id; + usb->base = base; + usb->layout = usbck_layout; + usb->parent_names = parent_names; + usb->num_parents = num_parents; + usb->clk_mux_table = clk_mux_table; + usb->mux_table = mux_table; + + clk = &usb->clk; + clk->flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | + CLK_SET_RATE_PARENT; + + pmc_read(usb->base, usb->layout->offset, &val); + + val = (val & usb->layout->usbs_mask) >> + (ffs(usb->layout->usbs_mask) - 1); + + index = at91_clk_mux_val_to_index(usb->mux_table, usb->num_parents, + val); + + if (index < 0) { + kfree(usb); + return ERR_PTR(index); + } + + ret = clk_register(clk, UBOOT_DM_CLK_AT91_SAM9X60_USB, name, + parent_names[index]); + if (ret) { + kfree(usb); + clk = ERR_PTR(ret); + } + + return clk; +} + +U_BOOT_DRIVER(at91_sam9x60_usb_clk) = { + .name = UBOOT_DM_CLK_AT91_SAM9X60_USB, + .id = UCLASS_CLK, + .ops = &sam9x60_usb_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/clk/at91/pmc.c b/drivers/clk/at91/pmc.c index 270892517a9..87d2069d89c 100644 --- a/drivers/clk/at91/pmc.c +++ b/drivers/clk/at91/pmc.c @@ -120,3 +120,45 @@ int at91_clk_mux_index_to_val(const u32 *table, u32 num_parents, u32 index) return table[index]; } + +int at91_clk_setup(const struct pmc_clk_setup *setup, int size) +{ + struct clk *c, *parent; + int i, ret; + + if (!size) + return 0; + + if (!setup) + return -EINVAL; + + for (i = 0; i < size; i++) { + ret = clk_get_by_id(setup[i].cid, &c); + if (ret) + return ret; + + if (setup[i].pid) { + ret = clk_get_by_id(setup[i].pid, &parent); + if (ret) + return ret; + + ret = clk_set_parent(c, parent); + if (ret) + return ret; + + if (setup[i].prate) { + ret = clk_set_rate(parent, setup[i].prate); + if (ret < 0) + return ret; + } + } + + if (setup[i].rate) { + ret = clk_set_rate(c, setup[i].rate); + if (ret < 0) + return ret; + } + } + + return 0; +} diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index 2b4dd9a3d96..ff464522aa0 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -71,6 +71,26 @@ struct clk_pcr_layout { u32 pid_mask; }; +struct clk_usbck_layout { + u32 offset; + u32 usbs_mask; + u32 usbdiv_mask; +}; + +/** + * Clock setup description + * @cid: clock id corresponding to clock subsystem + * @pid: parent clock id corresponding to clock subsystem + * @rate: clock rate + * @prate: parent rate + */ +struct pmc_clk_setup { + unsigned int cid; + unsigned int pid; + unsigned long rate; + unsigned long prate; +}; + extern const struct clk_programmable_layout at91rm9200_programmable_layout; extern const struct clk_programmable_layout at91sam9g45_programmable_layout; extern const struct clk_programmable_layout at91sam9x5_programmable_layout; @@ -87,6 +107,11 @@ struct clk *at91_clk_sam9x5_main(void __iomem *reg, const char *name, const char * const *parent_names, int num_parents, const u32 *mux_table, int type); struct clk * +sam9x60_clk_register_usb(void __iomem *base, const char *name, + const char * const *parent_names, u8 num_parents, + const struct clk_usbck_layout *usbck_layout, + const u32 *clk_mux_table, const u32 *mux_table, u8 id); +struct clk * sam9x60_clk_register_div_pll(void __iomem *base, const char *name, const char *parent_name, u8 id, const struct clk_pll_characteristics *characteristics, @@ -149,4 +174,6 @@ void pmc_write(void __iomem *base, unsigned int off, unsigned int val); void pmc_update_bits(void __iomem *base, unsigned int off, unsigned int mask, unsigned int bits); +int at91_clk_setup(const struct pmc_clk_setup *setup, int size); + #endif diff --git a/drivers/clk/at91/sam9x60.c b/drivers/clk/at91/sam9x60.c index 6b5486c6c9e..e2f72446d50 100644 --- a/drivers/clk/at91/sam9x60.c +++ b/drivers/clk/at91/sam9x60.c @@ -76,6 +76,8 @@ enum pmc_clk_ids { ID_QSPI = 18, ID_MCK_PRES = 19, + ID_USBCK = 20, + ID_UHPCK = 21, ID_MAX, }; @@ -99,6 +101,7 @@ static const char *clk_names[] = { [ID_PLL_A_DIV] = "plla_divpmcck", [ID_MCK_PRES] = "mck_pres", [ID_MCK_DIV] = "mck_div", + [ID_USBCK] = "usbck", }; /* Fractional PLL output range. */ @@ -171,6 +174,13 @@ static const struct clk_pcr_layout pcr_layout = { .pid_mask = GENMASK(6, 0), }; +/* USB clock layout */ +static const struct clk_usbck_layout usbck_layout = { + .offset = 0x38, + .usbs_mask = GENMASK(1, 0), + .usbdiv_mask = GENMASK(11, 8), +}; + /** * PLL clocks description * @n: clock name @@ -266,6 +276,7 @@ static const struct { u8 cid; } sam9x60_systemck[] = { { .n = "ddrck", .p = "mck_div", .id = 2, .cid = ID_DDR, }, + { .n = "uhpck", .p = "usbck", .id = 6, .cid = ID_UHPCK }, { .n = "pck0", .p = "prog0", .id = 8, .cid = ID_PCK0, }, { .n = "pck1", .p = "prog1", .id = 9, .cid = ID_PCK1, }, { .n = "qspick", .p = "mck_div", .id = 19, .cid = ID_QSPI, }, @@ -367,6 +378,31 @@ static const struct { { .n = "dbgu_gclk", .id = 47, }, }; +/** + * Clock setup description + * @cid: clock id corresponding to clock subsystem + * @pid: parent clock id corresponding to clock subsystem + * @rate: clock rate + * @prate: parent rate + */ +static const struct pmc_clk_setup sam9x60_clk_setup[] = { + { + .cid = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_U_FRAC), + .rate = 960000000, + }, + + { + .cid = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_U_DIV), + .rate = 480000000, + }, + + { + .cid = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_USBCK), + .pid = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_U_DIV), + .rate = 48000000, + }, +}; + #define prepare_mux_table(_allocs, _index, _dst, _src, _num, _label) \ do { \ int _i; \ @@ -543,6 +579,28 @@ static int sam9x60_clk_probe(struct udevice *dev) } clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK_DIV), c); + /* Register usbck. */ + p[0] = clk_names[ID_PLL_A_DIV]; + p[1] = clk_names[ID_PLL_U_DIV]; + p[2] = clk_names[ID_MAIN_XTAL]; + m[0] = 0; + m[1] = 1; + m[2] = 2; + cm[0] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_A_DIV); + cm[1] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_U_DIV); + cm[2] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAIN_XTAL); + prepare_mux_table(clkmuxallocs, clkmuxallocindex, tmpclkmux, cm, + 3, fail); + prepare_mux_table(muxallocs, muxallocindex, tmpmux, m, 3, fail); + c = sam9x60_clk_register_usb(base, clk_names[ID_USBCK], p, 3, + &usbck_layout, tmpclkmux, tmpmux, + ID_USBCK); + if (IS_ERR(c)) { + ret = PTR_ERR(c); + goto fail; + } + clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_USBCK), c); + /* Register programmable clocks. */ p[0] = clk_names[ID_MD_SLCK]; p[1] = clk_names[ID_TD_SLCK]; @@ -635,6 +693,11 @@ static int sam9x60_clk_probe(struct udevice *dev) clk_dm(AT91_TO_CLK_ID(PMC_TYPE_GCK, sam9x60_gck[i].id), c); } + /* Setup clocks. */ + ret = at91_clk_setup(sam9x60_clk_setup, ARRAY_SIZE(sam9x60_clk_setup)); + if (ret) + goto fail; + return 0; fail: diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c index d1ec3c82b54..8bd9c141566 100644 --- a/drivers/clk/at91/sama7g5.c +++ b/drivers/clk/at91/sama7g5.c @@ -1070,19 +1070,8 @@ static const struct { }, }; -/** - * Clock setup description - * @cid: clock id corresponding to clock subsystem - * @pid: parent clock id corresponding to clock subsystem - * @rate: clock rate - * @prate: parent rate - */ -static const struct pmc_clk_setup { - unsigned int cid; - unsigned int pid; - unsigned long rate; - unsigned long prate; -} sama7g5_clk_setup[] = { +/* Clock setup description */ +static const struct pmc_clk_setup sama7g5_clk_setup[] = { { .cid = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_ETH_FRAC), .rate = 625000000, @@ -1119,7 +1108,7 @@ static int sama7g5_clk_probe(struct udevice *dev) unsigned int *muxallocs[SAMA7G5_MAX_MUX_ALLOCS]; const char *p[10]; unsigned int cm[10], m[10], *tmpclkmux, *tmpmux; - struct clk clk, *c, *parent; + struct clk clk, *c; bool main_osc_bypass; int ret, muxallocindex = 0, clkmuxallocindex = 0, i, j; @@ -1353,34 +1342,9 @@ static int sama7g5_clk_probe(struct udevice *dev) } /* Setup clocks. */ - for (i = 0; i < ARRAY_SIZE(sama7g5_clk_setup); i++) { - ret = clk_get_by_id(sama7g5_clk_setup[i].cid, &c); - if (ret) - goto fail; - - if (sama7g5_clk_setup[i].pid) { - ret = clk_get_by_id(sama7g5_clk_setup[i].pid, &parent); - if (ret) - goto fail; - - ret = clk_set_parent(c, parent); - if (ret) - goto fail; - - if (sama7g5_clk_setup[i].prate) { - ret = clk_set_rate(parent, - sama7g5_clk_setup[i].prate); - if (ret < 0) - goto fail; - } - } - - if (sama7g5_clk_setup[i].rate) { - ret = clk_set_rate(c, sama7g5_clk_setup[i].rate); - if (ret < 0) - goto fail; - } - } + ret = at91_clk_setup(sama7g5_clk_setup, ARRAY_SIZE(sama7g5_clk_setup)); + if (ret) + goto fail; return 0; diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index ffbc1d1ba9f..09bef596f22 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -70,6 +70,14 @@ static const char *imx8mp_i2c6_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_ "sys_pll3_out", "audio_pll1_out", "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", }; +static const char *imx8mp_enet_qos_sels[] = {"clock-osc-24m", "sys_pll2_125m", "sys_pll2_50m", + "sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out", + "video_pll1_out", "clk_ext4", }; + +static const char *imx8mp_enet_qos_timer_sels[] = {"clock-osc-24m", "sys_pll2_100m", "audio_pll1_out", + "clk_ext1", "clk_ext2", "clk_ext3", + "clk_ext4", "video_pll1_out", }; + static const char *imx8mp_usdhc1_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", }; @@ -122,6 +130,22 @@ static const char *imx8mp_gic_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_p "sys_pll2_100m", "sys_pll1_800m", "sys_pll2_500m", "clk_ext4", "audio_pll2_out" }; +static const char *imx8mp_pwm1_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", + "sys_pll1_40m", "sys_pll3_out", "clk_ext1", + "sys_pll1_80m", "video_pll1_out", }; + +static const char *imx8mp_pwm2_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", + "sys_pll1_40m", "sys_pll3_out", "clk_ext1", + "sys_pll1_80m", "video_pll1_out", }; + +static const char *imx8mp_pwm3_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", + "sys_pll1_40m", "sys_pll3_out", "clk_ext2", + "sys_pll1_80m", "video_pll1_out", }; + +static const char *imx8mp_pwm4_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", + "sys_pll1_40m", "sys_pll3_out", "clk_ext2", + "sys_pll1_80m", "video_pll1_out", }; + static const char *imx8mp_ecspi1_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", }; @@ -250,6 +274,8 @@ static int imx8mp_clk_probe(struct udevice *dev) clk_dm(IMX8MP_CLK_DRAM_APB, imx8m_clk_composite_critical("dram_apb", imx8mp_dram_apb_sels, base + 0xa080)); clk_dm(IMX8MP_CLK_I2C5, imx8m_clk_composite("i2c5", imx8mp_i2c5_sels, base + 0xa480)); clk_dm(IMX8MP_CLK_I2C6, imx8m_clk_composite("i2c6", imx8mp_i2c6_sels, base + 0xa500)); + clk_dm(IMX8MP_CLK_ENET_QOS, imx8m_clk_composite("enet_qos", imx8mp_enet_qos_sels, base + 0xa880)); + clk_dm(IMX8MP_CLK_ENET_QOS_TIMER, imx8m_clk_composite("enet_qos_timer", imx8mp_enet_qos_timer_sels, base + 0xa900)); clk_dm(IMX8MP_CLK_ENET_REF, imx8m_clk_composite("enet_ref", imx8mp_enet_ref_sels, base + 0xa980)); clk_dm(IMX8MP_CLK_ENET_TIMER, imx8m_clk_composite("enet_timer", imx8mp_enet_timer_sels, base + 0xaa00)); clk_dm(IMX8MP_CLK_ENET_PHY_REF, imx8m_clk_composite("enet_phy_ref", imx8mp_enet_phy_ref_sels, base + 0xaa80)); @@ -270,6 +296,10 @@ static int imx8mp_clk_probe(struct udevice *dev) clk_dm(IMX8MP_CLK_GIC, imx8m_clk_composite_critical("gic", imx8mp_gic_sels, base + 0xb200)); clk_dm(IMX8MP_CLK_ECSPI1, imx8m_clk_composite("ecspi1", imx8mp_ecspi1_sels, base + 0xb280)); clk_dm(IMX8MP_CLK_ECSPI2, imx8m_clk_composite("ecspi2", imx8mp_ecspi2_sels, base + 0xb300)); + clk_dm(IMX8MP_CLK_PWM1, imx8m_clk_composite_critical("pwm1", imx8mp_pwm1_sels, base + 0xb380)); + clk_dm(IMX8MP_CLK_PWM2, imx8m_clk_composite_critical("pwm2", imx8mp_pwm2_sels, base + 0xb400)); + clk_dm(IMX8MP_CLK_PWM3, imx8m_clk_composite_critical("pwm3", imx8mp_pwm3_sels, base + 0xb480)); + clk_dm(IMX8MP_CLK_PWM4, imx8m_clk_composite_critical("pwm4", imx8mp_pwm4_sels, base + 0xb500)); clk_dm(IMX8MP_CLK_ECSPI3, imx8m_clk_composite("ecspi3", imx8mp_ecspi3_sels, base + 0xc180)); clk_dm(IMX8MP_CLK_WDOG, imx8m_clk_composite("wdog", imx8mp_wdog_sels, base + 0xb900)); @@ -292,10 +322,17 @@ static int imx8mp_clk_probe(struct udevice *dev) clk_dm(IMX8MP_CLK_I2C2_ROOT, imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0)); clk_dm(IMX8MP_CLK_I2C3_ROOT, imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0)); clk_dm(IMX8MP_CLK_I2C4_ROOT, imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0)); + clk_dm(IMX8MP_CLK_PWM1_ROOT, imx_clk_gate4("pwm1_root_clk", "pwm1", base + 0x4280, 0)); + clk_dm(IMX8MP_CLK_PWM2_ROOT, imx_clk_gate4("pwm2_root_clk", "pwm2", base + 0x4290, 0)); + clk_dm(IMX8MP_CLK_PWM3_ROOT, imx_clk_gate4("pwm3_root_clk", "pwm3", base + 0x42a0, 0)); + clk_dm(IMX8MP_CLK_PWM4_ROOT, imx_clk_gate4("pwm4_root_clk", "pwm4", base + 0x42b0, 0)); + clk_dm(IMX8MP_CLK_QOS_ROOT, imx_clk_gate4("qos_root_clk", "ipg_root", base + 0x42c0, 0)); + clk_dm(IMX8MP_CLK_QOS_ENET_ROOT, imx_clk_gate4("qos_enet_root_clk", "ipg_root", base + 0x42e0, 0)); clk_dm(IMX8MP_CLK_QSPI_ROOT, imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0)); clk_dm(IMX8MP_CLK_I2C5_ROOT, imx_clk_gate2("i2c5_root_clk", "i2c5", base + 0x4330, 0)); clk_dm(IMX8MP_CLK_I2C6_ROOT, imx_clk_gate2("i2c6_root_clk", "i2c6", base + 0x4340, 0)); clk_dm(IMX8MP_CLK_SIM_ENET_ROOT, imx_clk_gate4("sim_enet_root_clk", "enet_axi", base + 0x4400, 0)); + clk_dm(IMX8MP_CLK_ENET_QOS_ROOT, imx_clk_gate4("enet_qos_root_clk", "sim_enet_root_clk", base + 0x43b0, 0)); clk_dm(IMX8MP_CLK_UART1_ROOT, imx_clk_gate4("uart1_root_clk", "uart1", base + 0x4490, 0)); clk_dm(IMX8MP_CLK_UART2_ROOT, imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0)); clk_dm(IMX8MP_CLK_UART3_ROOT, imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0)); diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c index c121d82de7e..1697867ff0b 100644 --- a/drivers/clk/renesas/clk-rcar-gen3.c +++ b/drivers/clk/renesas/clk-rcar-gen3.c @@ -55,6 +55,7 @@ static int gen3_clk_get_parent(struct gen3_clk_priv *priv, struct clk *clk, struct cpg_mssr_info *info, struct clk *parent) { const struct cpg_core_clk *core; + u8 shift; int ret; if (!renesas_clk_is_mod(clk)) { @@ -63,8 +64,9 @@ static int gen3_clk_get_parent(struct gen3_clk_priv *priv, struct clk *clk, return ret; if (core->type == CLK_TYPE_GEN3_MDSEL) { + shift = priv->cpg_mode & BIT(core->offset) ? 16 : 0; parent->dev = clk->dev; - parent->id = core->parent >> (priv->sscg ? 16 : 0); + parent->id = core->parent >> shift; parent->id &= 0xffff; return 0; } @@ -183,6 +185,7 @@ static u64 gen3_clk_get_rate64(struct clk *clk) priv->cpg_pll_config; u32 value, div; u64 rate = 0; + u8 shift; int ret; debug("%s[%i] Clock: id=%lu\n", __func__, __LINE__, clk->id); @@ -277,11 +280,11 @@ static u64 gen3_clk_get_rate64(struct clk *clk) "FIXED"); case CLK_TYPE_GEN3_MDSEL: - div = (core->div >> (priv->sscg ? 16 : 0)) & 0xffff; + shift = priv->cpg_mode & BIT(core->offset) ? 16 : 0; + div = (core->div >> shift) & 0xffff; rate = gen3_clk_get_rate64(&parent) / div; debug("%s[%i] PE clk: parent=%i div=%u => rate=%llu\n", - __func__, __LINE__, - (core->parent >> (priv->sscg ? 16 : 0)) & 0xffff, + __func__, __LINE__, (core->parent >> shift) & 0xffff, div, rate); return rate; @@ -407,7 +410,6 @@ static int gen3_clk_probe(struct udevice *dev) struct cpg_mssr_info *info = (struct cpg_mssr_info *)dev_get_driver_data(dev); fdt_addr_t rst_base; - u32 cpg_mode; int ret; priv->base = dev_read_addr_ptr(dev); @@ -423,15 +425,13 @@ static int gen3_clk_probe(struct udevice *dev) if (rst_base == FDT_ADDR_T_NONE) return -EINVAL; - cpg_mode = readl(rst_base + info->reset_modemr_offset); + priv->cpg_mode = readl(rst_base + info->reset_modemr_offset); priv->cpg_pll_config = - (struct rcar_gen3_cpg_pll_config *)info->get_pll_config(cpg_mode); + (struct rcar_gen3_cpg_pll_config *)info->get_pll_config(priv->cpg_mode); if (!priv->cpg_pll_config->extal_div) return -EINVAL; - priv->sscg = !(cpg_mode & BIT(12)); - if (info->reg_layout == CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3) { priv->info->status_regs = mstpsr; priv->info->control_regs = smstpcr; diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h index 200e4adb906..894e3765495 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.h +++ b/drivers/clk/renesas/rcar-gen3-cpg.h @@ -132,7 +132,7 @@ struct gen3_clk_priv { struct cpg_mssr_info *info; struct clk clk_extal; struct clk clk_extalr; - bool sscg; + u32 cpg_mode; const struct rcar_gen3_cpg_pll_config *cpg_pll_config; }; diff --git a/drivers/clk/uniphier/clk-uniphier-sys.c b/drivers/clk/uniphier/clk-uniphier-sys.c index ff5d364f597..3b8595fe610 100644 --- a/drivers/clk/uniphier/clk-uniphier-sys.c +++ b/drivers/clk/uniphier/clk-uniphier-sys.c @@ -28,7 +28,10 @@ const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = { UNIPHIER_CLK_GATE_SIMPLE(14, 0x2104, 16), /* usb30 (Pro4, Pro5, PXs2) */ UNIPHIER_CLK_GATE_SIMPLE(15, 0x2104, 17), /* usb31 (Pro4, Pro5, PXs2) */ UNIPHIER_CLK_GATE_SIMPLE(16, 0x2104, 19), /* usb30-phy (PXs2) */ + UNIPHIER_CLK_RATE(17, 25000000), /* usb30-phy2 (PXs2) */ + UNIPHIER_CLK_RATE(18, 25000000), /* usb30-phy3 (PXs2) */ UNIPHIER_CLK_GATE_SIMPLE(20, 0x2104, 20), /* usb31-phy (PXs2) */ + UNIPHIER_CLK_RATE(21, 25000000), /* usb31-phy2 (PXs2) */ UNIPHIER_CLK_GATE_SIMPLE(24, 0x2108, 2), /* pcie (Pro5) */ { /* sentinel */ } #endif @@ -44,6 +47,8 @@ const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = { UNIPHIER_CLK_GATE_SIMPLE(14, 0x210c, 14), /* usb30 (LD20) */ UNIPHIER_CLK_GATE_SIMPLE(16, 0x210c, 12), /* usb30-phy0 (LD20) */ UNIPHIER_CLK_GATE_SIMPLE(17, 0x210c, 13), /* usb30-phy1 (LD20) */ + UNIPHIER_CLK_RATE(18, 25000000), /* usb30-phy2 (LD20) */ + UNIPHIER_CLK_RATE(19, 25000000), /* usb30-phy3 (LD20) */ UNIPHIER_CLK_GATE_SIMPLE(24, 0x210c, 4), /* pcie */ { /* sentinel */ } #endif diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig index 6fc8854b574..0f755aa702e 100644 --- a/drivers/core/Kconfig +++ b/drivers/core/Kconfig @@ -301,6 +301,13 @@ config SPL_SIMPLE_BUS Supports the 'simple-bus' driver, which is used on some systems in SPL. +config TPL_SIMPLE_BUS + bool "Support simple-bus driver in TPL" + depends on TPL_DM && TPL_OF_CONTROL + help + Supports the 'simple-bus' driver, which is used on some systems + in TPL. + config SIMPLE_BUS_CORRECT_RANGE bool "Decode the 'simple-bus' <range> by honoring the #address-cells and #size-cells" depends on SIMPLE_BUS diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c index d08578e9c4f..f49ee493d3c 100644 --- a/drivers/core/ofnode.c +++ b/drivers/core/ofnode.c @@ -1312,24 +1312,36 @@ bool ofnode_pre_reloc(ofnode node) { #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_TPL_BUILD) /* for SPL and TPL the remaining nodes after the fdtgrep 1st pass - * had property dm-pre-reloc or u-boot,dm-spl/tpl. + * had property bootph-all or bootph-pre-sram/bootph-pre-ram. * They are removed in final dtb (fdtgrep 2nd pass) */ return true; #else - if (ofnode_read_bool(node, "u-boot,dm-pre-reloc")) + if (ofnode_read_bool(node, "bootph-all")) return true; - if (ofnode_read_bool(node, "u-boot,dm-pre-proper")) + if (ofnode_read_bool(node, "bootph-some-ram")) return true; /* * In regular builds individual spl and tpl handling both * count as handled pre-relocation for later second init. */ - if (ofnode_read_bool(node, "u-boot,dm-spl") || - ofnode_read_bool(node, "u-boot,dm-tpl")) + if (ofnode_read_bool(node, "bootph-pre-ram") || + ofnode_read_bool(node, "bootph-pre-sram")) return true; + if (IS_ENABLED(CONFIG_OF_TAG_MIGRATE)) { + /* detect and handle old tags */ + if (ofnode_read_bool(node, "u-boot,dm-pre-reloc") || + ofnode_read_bool(node, "u-boot,dm-pre-proper") || + ofnode_read_bool(node, "u-boot,dm-spl") || + ofnode_read_bool(node, "u-boot,dm-tpl") || + ofnode_read_bool(node, "u-boot,dm-vpl")) { + gd->flags |= GD_FLG_OF_TAG_MIGRATE; + return true; + } + } + return false; #endif } diff --git a/drivers/ddr/imx/imx8ulp/Kconfig b/drivers/ddr/imx/imx8ulp/Kconfig index 42848863aae..5448c33838c 100644 --- a/drivers/ddr/imx/imx8ulp/Kconfig +++ b/drivers/ddr/imx/imx8ulp/Kconfig @@ -13,6 +13,6 @@ config SAVED_DRAM_TIMING_BASE help The DRAM config timing data need to be saved into sram for low power use. - default 0x2006c000 + default 0x20055000 endmenu diff --git a/drivers/ddr/imx/imx8ulp/ddr_init.c b/drivers/ddr/imx/imx8ulp/ddr_init.c index a5a9fd8d7c8..c362a2da338 100644 --- a/drivers/ddr/imx/imx8ulp/ddr_init.c +++ b/drivers/ddr/imx/imx8ulp/ddr_init.c @@ -31,6 +31,7 @@ #define DENALI_CTL_25 (DDR_CTL_BASE_ADDR + 4 * 25) #define DENALI_PHY_1624 (DDR_PHY_BASE_ADDR + 4 * 1624) +#define DENALI_PHY_1625 (DDR_PHY_BASE_ADDR + 4 * 1625) #define DENALI_PHY_1537 (DDR_PHY_BASE_ADDR + 4 * 1537) #define PHY_FREQ_SEL_MULTICAST_EN(X) ((X) << 8) #define PHY_FREQ_SEL_INDEX(X) ((X) << 16) @@ -82,25 +83,39 @@ int ddr_calibration(unsigned int fsp_table[3]) u32 int_status_init, phy_freq_req, phy_freq_type; u32 lock_0, lock_1, lock_2; u32 freq_chg_pt, freq_chg_cnt; + u32 is_lpddr4 = 0; if (IS_ENABLED(CONFIG_IMX8ULP_DRAM_PHY_PLL_BYPASS)) { ddr_enable_pll_bypass(); freq_chg_cnt = 0; freq_chg_pt = 0; } else { - reg_val = readl(DENALI_CTL_250); - if (((reg_val >> 16) & 0x3) == 1) - freq_chg_cnt = 2; - else - freq_chg_cnt = 3; - - reg_val = readl(DENALI_PI_12); - if (reg_val == 0x3) { - freq_chg_pt = 1; - } else if (reg_val == 0x7) { - freq_chg_pt = 2; + reg_val = (readl(DENALI_CTL_00)>>8)&0xf; + if(reg_val == 0x7) { + /* LPDDR3 type */ + set_ddr_clk(fsp_table[1] >> 1); + freq_chg_cnt = 0; + freq_chg_pt = 0; + } else if(reg_val == 0xb) { + /* LPDDR4/4x type */ + is_lpddr4 = 1; + reg_val = readl(DENALI_CTL_250); + if (((reg_val >> 16) & 0x3) == 1) + freq_chg_cnt = 2; + else + freq_chg_cnt = 3; + + reg_val = readl(DENALI_PI_12); + if(reg_val == 0x3) + freq_chg_pt = 1; + else if(reg_val == 0x7) + freq_chg_pt = 2; + else { + printf("frequency map(0x%x) is wrong, please check!\r\n", reg_val); + return -1; + } } else { - printf("frequency map(0x%x) is wrong, please check!\r\n", reg_val); + printf("Incorrect DDR type configured!\r\n"); return -1; } } @@ -179,6 +194,22 @@ int ddr_calibration(unsigned int fsp_table[3]) } debug("De-Skew PLL is locked and ready\n"); + + /* Change LPDDR4 FREQ1 to bypass mode if it is lower than 200MHz */ + if(is_lpddr4 && fsp_table[1] < 400) { + /* Set FREQ1 to bypass mode */ + reg_val = PHY_FREQ_SEL_MULTICAST_EN(0) | PHY_FREQ_SEL_INDEX(0); + writel(reg_val, DENALI_PHY_1537); + + /* PHY_PLL_BYPASS=0x1 (DENALI_PHY_1624) */ + reg_val =readl(DENALI_PHY_1624) | 0x1; + writel(reg_val, DENALI_PHY_1624); + + /* DENALI_PHY_1625: bypass mode in PHY PLL */ + reg_val =readl(DENALI_PHY_1625) & ~0xf; + writel(reg_val, DENALI_PHY_1625); + } + return 0; } diff --git a/drivers/ddr/marvell/a38x/ddr3_init.h b/drivers/ddr/marvell/a38x/ddr3_init.h index ba9f7881d54..6854bb49de1 100644 --- a/drivers/ddr/marvell/a38x/ddr3_init.h +++ b/drivers/ddr/marvell/a38x/ddr3_init.h @@ -9,7 +9,6 @@ #include "ddr_ml_wrapper.h" #include "mv_ddr_plat.h" -#include "seq_exec.h" #include "ddr3_logging_def.h" #include "ddr3_training_hw_algo.h" #include "ddr3_training_ip.h" diff --git a/drivers/ddr/marvell/a38x/seq_exec.h b/drivers/ddr/marvell/a38x/seq_exec.h deleted file mode 100644 index fe0cb8f75df..00000000000 --- a/drivers/ddr/marvell/a38x/seq_exec.h +++ /dev/null @@ -1,64 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) Marvell International Ltd. and its affiliates - */ - -#ifndef _SEQ_EXEC_H -#define _SEQ_EXEC_H - -#define NA 0xff -#define DEFAULT_PARAM 0 -#define MV_BOARD_TCLK_ERROR 0xffffffff - -#define NO_DATA 0xffffffff -#define MAX_DATA_ARRAY 5 -#define FIRST_CELL 0 - -/* Operation types */ -enum mv_op { - WRITE_OP, - DELAY_OP, - POLL_OP, -}; - -/* Operation parameters */ -struct op_params { - u32 unit_base_reg; - u32 unit_offset; - u32 mask; - u32 data[MAX_DATA_ARRAY]; /* data array */ - u8 wait_time; /* msec */ - u16 num_of_loops; /* for polling only */ -}; - -/* - * Sequence parameters. Each sequence contains: - * 1. Sequence id. - * 2. Sequence size (total amount of operations during the sequence) - * 3. a series of operations. operations can be write, poll or delay - * 4. index in the data array (the entry where the relevant data sits) - */ -struct cfg_seq { - struct op_params *op_params_ptr; - u8 cfg_seq_size; - u8 data_arr_idx; -}; - -extern struct cfg_seq serdes_seq_db[]; - -/* - * A generic function type for executing an operation (write, poll or delay) - */ -typedef int (*op_execute_func_ptr)(u32 serdes_num, struct op_params *params, - u32 data_arr_idx); - -/* Specific functions for executing each operation */ -int write_op_execute(u32 serdes_num, struct op_params *params, - u32 data_arr_idx); -int delay_op_execute(u32 serdes_num, struct op_params *params, - u32 data_arr_idx); -int poll_op_execute(u32 serdes_num, struct op_params *params, u32 data_arr_idx); -enum mv_op get_cfg_seq_op(struct op_params *params); -int mv_seq_exec(u32 serdes_num, u32 seq_id); - -#endif /*_SEQ_EXEC_H*/ diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index 61490d6d8de..62cb77b098c 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -75,7 +75,7 @@ config FPGA_XILINX config FPGA_ZYNQMPPL bool "Enable Xilinx FPGA driver for ZynqMP" - depends on FPGA_XILINX + depends on FPGA_XILINX && ZYNQMP_FIRMWARE help Enable FPGA driver for loading bitstream in BIT and BIN format on Xilinx Zynq UltraScale+ (ZynqMP) device. diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c index d1491da02c3..7b5128fe27a 100644 --- a/drivers/fpga/zynqmppl.c +++ b/drivers/fpga/zynqmppl.c @@ -332,10 +332,16 @@ static int zynqmp_loads(xilinx_desc *desc, const void *buf, size_t bsize, buf_lo = lower_32_bits((ulong)buf); buf_hi = upper_32_bits((ulong)buf); - ret = xilinx_pm_request(PM_FPGA_LOAD, buf_lo, + if ((u32)(uintptr_t)fpga_sec_info->userkey_addr) + ret = xilinx_pm_request(PM_FPGA_LOAD, buf_lo, buf_hi, - (u32)(uintptr_t)fpga_sec_info->userkey_addr, - flag, ret_payload); + (u32)(uintptr_t)fpga_sec_info->userkey_addr, + flag, ret_payload); + else + ret = xilinx_pm_request(PM_FPGA_LOAD, buf_lo, + buf_hi, (u32)bsize, + flag, ret_payload); + if (ret) puts("PL FPGA LOAD fail\n"); else diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c index dbebf3a53eb..c8be5a4d668 100644 --- a/drivers/gpio/gpio-uclass.c +++ b/drivers/gpio/gpio-uclass.c @@ -1171,6 +1171,13 @@ int gpio_request_by_line_name(struct udevice *dev, const char *line_name, { int ret; + if (!dev) { + uclass_foreach_dev_probe(UCLASS_GPIO, dev) + if (!gpio_request_by_line_name(dev, line_name, desc, flags)) + return 0; + return -ENOENT; + } + ret = dev_read_stringlist_search(dev, "gpio-line-names", line_name); if (ret < 0) return ret; diff --git a/drivers/gpio/sh_pfc.c b/drivers/gpio/sh_pfc.c index 988f7e9bbad..92522b63bbe 100644 --- a/drivers/gpio/sh_pfc.c +++ b/drivers/gpio/sh_pfc.c @@ -568,10 +568,10 @@ static int sh_gpio_get_value(struct pinmux_info *gpioc, unsigned gpio) if (!gpioc || get_data_reg(gpioc, gpio, &dr, &bit) != 0) return -1; -#if defined(CONFIG_RCAR_GEN3) - if ((gpioc->gpios[gpio].flags & PINMUX_FLAG_TYPE) == PINMUX_TYPE_INPUT) + + if (IS_ENABLED(CONFIG_RCAR_GEN3) && + ((gpioc->gpios[gpio].flags & PINMUX_FLAG_TYPE) == PINMUX_TYPE_INPUT)) offset += 4; -#endif return gpio_read_bit(dr, offset, bit); } diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 3279fef1eb0..2eae33cd54c 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -47,6 +47,16 @@ config SPL_DM_I2C device (bus child) info is kept as parent platdata. The interface is defined in include/i2c.h. +config TPL_DM_I2C + bool "Enable Driver Model for I2C drivers in TPL" + depends on TPL_DM && DM_I2C + help + Enable driver model for I2C. The I2C uclass interface: probe, read, + write and speed, is implemented with the bus drivers operations, + which provide methods for bus setting and data transfer. Each chip + device (bus child) info is kept as parent platdata. The interface + is defined in include/i2c.h. + config VPL_DM_I2C bool "Enable Driver Model for I2C drivers in VPL" depends on VPL_DM && DM_I2C @@ -486,13 +496,13 @@ config SYS_I2C_OMAP24XX config SYS_I2C_RCAR_I2C bool "Renesas RCar I2C driver" - depends on (RCAR_GEN3 || RCAR_GEN2) && DM_I2C + depends on (RCAR_GEN2 || RCAR_GEN3) && DM_I2C help Support for Renesas RCar I2C controller. config SYS_I2C_RCAR_IIC bool "Renesas RCar Gen3 IIC driver" - depends on (RCAR_GEN3 || RCAR_GEN2) && DM_I2C + depends on (RCAR_GEN2 || RCAR_GEN3) && DM_I2C help Support for Renesas RCar Gen3 IIC controller. @@ -508,6 +518,16 @@ config SYS_I2C_ROCKCHIP config SYS_I2C_SANDBOX bool "Sandbox I2C driver" depends on SANDBOX && DM_I2C + default y + help + Enable I2C support for sandbox. This is an emulation of a real I2C + bus. Devices can be attached to the bus using the device tree + which specifies the driver to use. See sandbox.dts as an example. + +config SPL_SYS_I2C_SANDBOX + bool "Sandbox I2C driver (SPL)" + depends on SPL && SANDBOX && DM_I2C + default y help Enable I2C support for sandbox. This is an emulation of a real I2C bus. Devices can be attached to the bus using the device tree diff --git a/drivers/input/Kconfig b/drivers/input/Kconfig index 32360d94c05..c2b365af11d 100644 --- a/drivers/input/Kconfig +++ b/drivers/input/Kconfig @@ -48,8 +48,8 @@ config APPLE_SPI_KEYB config BUTTON_KEYBOARD bool "Buttons as keyboard" - depends on BUTTON_GPIO depends on DM_KEYBOARD + select BUTTON_GPIO help Enable support for mapping buttons to keycode events. Use linux,code button driver dt node to define button-event mapping. diff --git a/drivers/input/Makefile b/drivers/input/Makefile index 14c0ea73254..71f315adf6f 100644 --- a/drivers/input/Makefile +++ b/drivers/input/Makefile @@ -14,5 +14,4 @@ obj-$(CONFIG_APPLE_SPI_KEYB) += apple_spi_kbd.o obj-$(CONFIG_I8042_KEYB) += i8042.o obj-$(CONFIG_TEGRA_KEYBOARD) += input.o tegra-kbc.o obj-$(CONFIG_TWL4030_INPUT) += twl4030.o -obj-$(CONFIG_TWL6030_INPUT) += twl6030.o endif diff --git a/drivers/input/button_kbd.c b/drivers/input/button_kbd.c index 99e65f12f01..74fadfca8bb 100644 --- a/drivers/input/button_kbd.c +++ b/drivers/input/button_kbd.c @@ -111,16 +111,14 @@ static int button_kbd_probe(struct udevice *dev) return 0; } -static const struct udevice_id button_kbd_ids[] = { - { .compatible = "button-kbd" }, - { } -}; - U_BOOT_DRIVER(button_kbd) = { .name = "button_kbd", .id = UCLASS_KEYBOARD, - .of_match = button_kbd_ids, .ops = &button_kbd_ops, .priv_auto = sizeof(struct button_kbd_priv), .probe = button_kbd_probe, }; + +U_BOOT_DRVINFO(button_kbd) = { + .name = "button_kbd" +}; diff --git a/drivers/input/twl6030.c b/drivers/input/twl6030.c deleted file mode 100644 index 76bd3488fc6..00000000000 --- a/drivers/input/twl6030.c +++ /dev/null @@ -1,47 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * TWL6030 input - * - * Copyright (C) 2016 Paul Kocialkowski <contact@paulk.fr> - */ - -#include <twl6030.h> - -int twl6030_input_power_button(void) -{ - u8 value; - - twl6030_i2c_read_u8(TWL6030_CHIP_PM, TWL6030_STS_HW_CONDITIONS, &value); - - /* Power button is active low. */ - if (value & TWL6030_STS_HW_CONDITIONS_PWRON) - return 0; - - return 1; -} - -int twl6030_input_charger(void) -{ - u8 value; - - twl6030_i2c_read_u8(TWL6030_CHIP_CHARGER, TWL6030_CONTROLLER_STAT1, - &value); - - if (value & TWL6030_CONTROLLER_STAT1_VAC_DET) - return 1; - - return 0; -} - -int twl6030_input_usb(void) -{ - u8 value; - - twl6030_i2c_read_u8(TWL6030_CHIP_CHARGER, TWL6030_CONTROLLER_STAT1, - &value); - - if (value & TWL6030_CONTROLLER_STAT1_VBUS_DET) - return 1; - - return 0; -} diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index b5707a15c50..4e1ae03e9fd 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -348,7 +348,7 @@ config NPCM_HOST config SPL_MXC_OCOTP bool "Enable MXC OCOTP driver in SPL" - depends on SPL_MISC && (ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610) + depends on SPL_DRIVERS_MISC && (ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610) default y help If you say Y here, you will get support for the One Time diff --git a/drivers/misc/sentinel/fuse.c b/drivers/misc/sentinel/fuse.c index e2b68757664..99342d33c06 100644 --- a/drivers/misc/sentinel/fuse.c +++ b/drivers/misc/sentinel/fuse.c @@ -60,6 +60,11 @@ struct fsb_map_entry fsb_mapping_table[] = { { 46, 8 }, }; +/* None ECC banks such like Redundancy or Bit protect */ +u32 nonecc_fuse_banks[] = { + 0, 1, 8, 12, 16, 22, 24, 25, 26, 27, 36, 41, 51, 56 +}; + struct s400_map_entry s400_api_mapping_table[] = { { 1, 8 }, /* LOCK */ { 2, 8 }, /* ECID */ @@ -67,6 +72,16 @@ struct s400_map_entry s400_api_mapping_table[] = { { 15, 8 }, /* OEM SRK HASH */ { 23, 1, 4, 2 }, /* OTFAD */ { 25, 8 }, /* Test config2 */ + { 26, 8 }, /* PMU */ + { 27, 8 }, /* Test flow/USB */ + { 32, 8 }, /* GP1 */ + { 33, 8 }, /* GP2 */ + { 34, 8 }, /* GP3 */ + { 35, 8 }, /* GP4 */ + { 36, 8 }, /* GP5 */ + { 49, 8 }, /* GP8 */ + { 50, 8 }, /* GP9 */ + { 51, 8 }, /* GP10 */ }; #elif defined(CONFIG_ARCH_IMX9) #define FSB_OTP_SHADOW 0x8000 @@ -270,11 +285,26 @@ int fuse_prog(u32 bank, u32 word, u32 val) { u32 res; int ret; + bool lock = false; if (bank >= FUSE_BANKS || word >= WORDS_PER_BANKS || !val) return -EINVAL; - ret = ahab_write_fuse((bank * 8 + word), val, false, &res); + /* Lock 8ULP ECC fuse word, so second programming will return failure. + * iMX9 OTP can protect ECC fuse, so not need it + */ +#if defined(CONFIG_IMX8ULP) + u32 i; + for (i = 0; i < ARRAY_SIZE(nonecc_fuse_banks); i++) { + if (nonecc_fuse_banks[i] == bank) + break; + } + + if (i == ARRAY_SIZE(nonecc_fuse_banks)) + lock = true; +#endif + + ret = ahab_write_fuse((bank * 8 + word), val, lock, &res); if (ret) { printf("ahab write fuse failed %d, 0x%x\n", ret, res); return ret; diff --git a/drivers/misc/sentinel/s400_api.c b/drivers/misc/sentinel/s400_api.c index 65032f77362..6c0d0b3f18a 100644 --- a/drivers/misc/sentinel/s400_api.c +++ b/drivers/misc/sentinel/s400_api.c @@ -29,7 +29,7 @@ int ahab_release_rdc(u8 core_id, u8 xrdc, u32 *response) msg.version = AHAB_VERSION; msg.tag = AHAB_CMD_TAG; msg.size = 2; - msg.command = AHAB_RELEASE_RDC_REQ_CID; + msg.command = ELE_RELEASE_RDC_REQ; switch (xrdc) { case 0: msg.data[0] = (0x74 << 8) | core_id; @@ -74,7 +74,7 @@ int ahab_auth_oem_ctnr(ulong ctnr_addr, u32 *response) msg.version = AHAB_VERSION; msg.tag = AHAB_CMD_TAG; msg.size = 3; - msg.command = AHAB_AUTH_OEM_CTNR_CID; + msg.command = ELE_OEM_CNTN_AUTH_REQ; msg.data[0] = upper_32_bits(ctnr_addr); msg.data[1] = lower_32_bits(ctnr_addr); @@ -104,7 +104,7 @@ int ahab_release_container(u32 *response) msg.version = AHAB_VERSION; msg.tag = AHAB_CMD_TAG; msg.size = 1; - msg.command = AHAB_RELEASE_CTNR_CID; + msg.command = ELE_RELEASE_CONTAINER_REQ; ret = misc_call(dev, false, &msg, size, &msg, size); if (ret) @@ -132,7 +132,7 @@ int ahab_verify_image(u32 img_id, u32 *response) msg.version = AHAB_VERSION; msg.tag = AHAB_CMD_TAG; msg.size = 2; - msg.command = AHAB_VERIFY_IMG_CID; + msg.command = ELE_VERIFY_IMAGE_REQ; msg.data[0] = 1 << img_id; ret = misc_call(dev, false, &msg, size, &msg, size); @@ -161,7 +161,7 @@ int ahab_forward_lifecycle(u16 life_cycle, u32 *response) msg.version = AHAB_VERSION; msg.tag = AHAB_CMD_TAG; msg.size = 2; - msg.command = AHAB_FWD_LIFECYCLE_UP_REQ_CID; + msg.command = ELE_FWD_LIFECYCLE_UP_REQ; msg.data[0] = life_cycle; ret = misc_call(dev, false, &msg, size, &msg, size); @@ -201,7 +201,7 @@ int ahab_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32 fuse_num, u32 *respo msg.version = AHAB_VERSION; msg.tag = AHAB_CMD_TAG; msg.size = 2; - msg.command = AHAB_READ_FUSE_REQ_CID; + msg.command = ELE_READ_FUSE_REQ; msg.data[0] = fuse_id; ret = misc_call(dev, false, &msg, size, &msg, size); @@ -238,7 +238,7 @@ int ahab_write_fuse(u16 fuse_id, u32 fuse_val, bool lock, u32 *response) msg.version = AHAB_VERSION; msg.tag = AHAB_CMD_TAG; msg.size = 3; - msg.command = AHAB_WRITE_FUSE_REQ_CID; + msg.command = ELE_WRITE_FUSE_REQ; msg.data[0] = (32 << 16) | (fuse_id << 5); if (lock) msg.data[0] |= (1 << 31); @@ -271,7 +271,7 @@ int ahab_release_caam(u32 core_did, u32 *response) msg.version = AHAB_VERSION; msg.tag = AHAB_CMD_TAG; msg.size = 2; - msg.command = AHAB_CAAM_RELEASE_CID; + msg.command = ELE_RELEASE_CAAM_REQ; msg.data[0] = core_did; ret = misc_call(dev, false, &msg, size, &msg, size); @@ -310,7 +310,7 @@ int ahab_get_fw_version(u32 *fw_version, u32 *sha1, u32 *response) msg.version = AHAB_VERSION; msg.tag = AHAB_CMD_TAG; msg.size = 1; - msg.command = AHAB_GET_FW_VERSION_CID; + msg.command = ELE_GET_FW_VERSION_REQ; ret = misc_call(dev, false, &msg, size, &msg, size); if (ret) @@ -341,7 +341,7 @@ int ahab_dump_buffer(u32 *buffer, u32 buffer_length) msg.version = AHAB_VERSION; msg.tag = AHAB_CMD_TAG; msg.size = 1; - msg.command = AHAB_LOG_CID; + msg.command = ELE_DUMP_DEBUG_BUFFER_REQ; ret = misc_call(dev, false, &msg, size, &msg, size); if (ret) { @@ -375,7 +375,7 @@ int ahab_get_info(struct sentinel_get_info_data *info, u32 *response) msg.version = AHAB_VERSION; msg.tag = AHAB_CMD_TAG; msg.size = 4; - msg.command = AHAB_GET_INFO_CID; + msg.command = ELE_GET_INFO_REQ; msg.data[0] = upper_32_bits((ulong)info); msg.data[1] = lower_32_bits((ulong)info); msg.data[2] = sizeof(struct sentinel_get_info_data); @@ -406,7 +406,7 @@ int ahab_get_fw_status(u32 *status, u32 *response) msg.version = AHAB_VERSION; msg.tag = AHAB_CMD_TAG; msg.size = 1; - msg.command = AHAB_GET_FW_STATUS_CID; + msg.command = ELE_GET_FW_STATUS_REQ; ret = misc_call(dev, false, &msg, size, &msg, size); if (ret) @@ -436,7 +436,7 @@ int ahab_release_m33_trout(void) msg.version = AHAB_VERSION; msg.tag = AHAB_CMD_TAG; msg.size = 1; - msg.command = 0xd3; + msg.command = ELE_ENABLE_RTC_REQ; ret = misc_call(dev, false, &msg, size, &msg, size); if (ret) @@ -445,3 +445,48 @@ int ahab_release_m33_trout(void) return ret; } + +int ahab_get_events(u32 *events, u32 *events_cnt, u32 *response) +{ + struct udevice *dev = gd->arch.s400_dev; + int size = sizeof(struct sentinel_msg); + struct sentinel_msg msg; + int ret, i = 0; + u32 actual_events; + + if (!dev) { + printf("s400 dev is not initialized\n"); + return -ENODEV; + } + + if (!events || !events_cnt || *events_cnt == 0) { + printf("Invalid parameters for %s\n", __func__); + return -EINVAL; + } + + msg.version = AHAB_VERSION; + msg.tag = AHAB_CMD_TAG; + msg.size = 1; + msg.command = ELE_GET_EVENTS_REQ; + + ret = misc_call(dev, false, &msg, size, &msg, size); + if (ret) + printf("Error: %s: ret %d, response 0x%x\n", + __func__, ret, msg.data[0]); + + if (response) + *response = msg.data[0]; + + if (!ret) { + actual_events = msg.data[1] & 0xffff; + if (*events_cnt < actual_events) + actual_events = *events_cnt; + + for (; i < actual_events; i++) + events[i] = msg.data[i + 2]; + + *events_cnt = actual_events; + } + + return ret; +} diff --git a/drivers/misc/swap_case.c b/drivers/misc/swap_case.c index 7093ad1cd4f..ee5c12bd0a4 100644 --- a/drivers/misc/swap_case.c +++ b/drivers/misc/swap_case.c @@ -165,6 +165,9 @@ static int sandbox_swap_case_read_config(const struct udevice *emul, case PCI_CAP_ID_EXP_OFFSET + PCI_CAP_LIST_NEXT: *valuep = PCI_CAP_ID_MSIX_OFFSET; break; + case PCI_CAP_ID_EXP_OFFSET + PCI_EXP_DEVCAP: + *valuep = PCI_EXP_DEVCAP_PAYLOAD_256B; + break; case PCI_CAP_ID_MSIX_OFFSET: if (sandbox_swap_case_use_ea(emul)) *valuep = (PCI_CAP_ID_EA_OFFSET << 8) | PCI_CAP_ID_MSIX; diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 878f867c627..80641e13930 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -667,18 +667,6 @@ config MMC_SDHCI_S5P If unsure, say N. -config MMC_SDHCI_SPEAR - bool "SDHCI support on ST SPEAr platform" - depends on MMC_SDHCI - help - This selects the Secure Digital Host Controller Interface (SDHCI) - often referrered to as the HSMMC block in some of the ST SPEAR range - of SoC - - If you have a controller with this interface, say Y here. - - If unsure, say N. - config MMC_SDHCI_STI bool "SDHCI support for STMicroelectronics SoC" depends on MMC_SDHCI && OF_CONTROL diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index 3dc757108d5..2c65c4765ab 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -70,7 +70,6 @@ obj-$(CONFIG_MMC_SDHCI_NPCM) += npcm_sdhci.o obj-$(CONFIG_MMC_SDHCI_PIC32) += pic32_sdhci.o obj-$(CONFIG_MMC_SDHCI_ROCKCHIP) += rockchip_sdhci.o obj-$(CONFIG_MMC_SDHCI_S5P) += s5p_sdhci.o -obj-$(CONFIG_MMC_SDHCI_SPEAR) += spear_sdhci.o obj-$(CONFIG_MMC_SDHCI_STI) += sti_sdhci.o obj-$(CONFIG_MMC_SDHCI_TANGIER) += tangier_sdhci.o obj-$(CONFIG_MMC_SDHCI_TEGRA) += tegra_mmc.o diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index 91e309d2752..9dc310663f2 100644 --- a/drivers/mmc/zynq_sdhci.c +++ b/drivers/mmc/zynq_sdhci.c @@ -14,6 +14,7 @@ #include "mmc_private.h" #include <log.h> #include <reset.h> +#include <asm/arch/sys_proto.h> #include <dm/device_compat.h> #include <linux/err.h> #include <linux/libfdt.h> @@ -988,7 +989,7 @@ static const struct sdhci_ops arasan_ops = { }; #endif -#if defined(CONFIG_ARCH_ZYNQMP) +#if defined(CONFIG_ARCH_ZYNQMP) && defined(CONFIG_ZYNQMP_FIRMWARE) static int sdhci_zynqmp_set_dynamic_config(struct arasan_sdhci_priv *priv, struct udevice *dev) { @@ -1090,7 +1091,7 @@ static int arasan_sdhci_probe(struct udevice *dev) host = priv->host; -#if defined(CONFIG_ARCH_ZYNQMP) +#if defined(CONFIG_ARCH_ZYNQMP) && defined(CONFIG_ZYNQMP_FIRMWARE) if (device_is_compatible(dev, "xlnx,zynqmp-8.9a")) { ret = zynqmp_pm_is_function_supported(PM_IOCTL, IOCTL_SET_SD_CONFIG); diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index 5b35da45f58..5c7b0d9dcc1 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -628,7 +628,8 @@ comment "Generic NAND options" config SYS_NAND_BLOCK_SIZE hex "NAND chip eraseblock size" - depends on ARCH_SUNXI || SPL_NAND_SUPPORT || TPL_NAND_SUPPORT + depends on ARCH_SUNXI || SPL_NAND_SUPPORT || TPL_NAND_SUPPORT || \ + MVEBU_SPL_BOOT_DEVICE_NAND depends on !NAND_MXS && !NAND_DENALI_DT && !NAND_LPC32XX_MLC && \ !NAND_FSL_IFC && !NAND_MT7621 help @@ -655,6 +656,7 @@ config SYS_NAND_PAGE_SIZE hex "NAND chip page size" depends on ARCH_SUNXI || NAND_OMAP_GPMC || NAND_LPC32XX_SLC || \ SPL_NAND_SIMPLE || (NAND_MXC && SPL_NAND_SUPPORT) || \ + MVEBU_SPL_BOOT_DEVICE_NAND || \ (NAND_ATMEL && SPL_NAND_SUPPORT) || SPL_GENERATE_ATMEL_PMECC_HEADER depends on !NAND_MXS && !NAND_DENALI_DT && !NAND_LPC32XX_MLC && !NAND_MT7621 help diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile index 666323e2219..add2b4cf655 100644 --- a/drivers/mtd/nand/raw/Makefile +++ b/drivers/mtd/nand/raw/Makefile @@ -56,7 +56,6 @@ obj-$(CONFIG_NAND_DENALI) += denali.o obj-$(CONFIG_NAND_DENALI_DT) += denali_dt.o obj-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o obj-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_nand.o -obj-$(CONFIG_NAND_KB9202) += kb9202_nand.o obj-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o obj-$(CONFIG_NAND_KMETER1) += kmeter1_nand.o obj-$(CONFIG_NAND_LPC32XX_MLC) += lpc32xx_nand_mlc.o diff --git a/drivers/mtd/nand/raw/arasan_nfc.c b/drivers/mtd/nand/raw/arasan_nfc.c index 4621bfb03e3..99e2681c14b 100644 --- a/drivers/mtd/nand/raw/arasan_nfc.c +++ b/drivers/mtd/nand/raw/arasan_nfc.c @@ -1230,12 +1230,16 @@ static int arasan_probe(struct udevice *dev) struct nand_drv *info = &arasan->nand_ctrl; struct nand_config *nand = &info->config; struct mtd_info *mtd; + ofnode child; int err = -1; info->reg = (struct nand_regs *)dev_read_addr(dev); mtd = nand_to_mtd(nand_chip); nand_set_controller_data(nand_chip, &arasan->nand_ctrl); + ofnode_for_each_subnode(child, dev_ofnode(dev)) + nand_set_flash_node(nand_chip, child); + #ifdef CONFIG_SYS_NAND_NO_SUBPAGE_WRITE nand_chip->options |= NAND_NO_SUBPAGE_WRITE; #endif @@ -1248,7 +1252,6 @@ static int arasan_probe(struct udevice *dev) /* Buffer read/write routines */ nand_chip->read_buf = arasan_nand_read_buf; nand_chip->write_buf = arasan_nand_write_buf; - nand_chip->bbt_options = NAND_BBT_USE_FLASH; writel(0x0, &info->reg->cmd_reg); writel(0x0, &info->reg->pgm_reg); diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c b/drivers/mtd/nand/raw/brcmnand/brcmnand.c index 74c9348f7fc..efbf9a3120a 100644 --- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c +++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c @@ -86,6 +86,12 @@ struct brcm_nand_dma_desc { #define FLASH_DMA_ECC_ERROR (1 << 8) #define FLASH_DMA_CORR_ERROR (1 << 9) +/* Bitfields for DMA_MODE */ +#define FLASH_DMA_MODE_STOP_ON_ERROR BIT(1) /* stop in Uncorr ECC error */ +#define FLASH_DMA_MODE_MODE BIT(0) /* link list */ +#define FLASH_DMA_MODE_MASK (FLASH_DMA_MODE_STOP_ON_ERROR | \ + FLASH_DMA_MODE_MODE) + /* 512B flash cache in the NAND controller HW */ #define FC_SHIFT 9U #define FC_BYTES 512U @@ -98,6 +104,65 @@ struct brcm_nand_dma_desc { #define NAND_CTRL_RDY (INTFC_CTLR_READY | INTFC_FLASH_READY) #define NAND_POLL_STATUS_TIMEOUT_MS 100 +/* flash_dma registers */ +enum flash_dma_reg { + FLASH_DMA_REVISION = 0, + FLASH_DMA_FIRST_DESC, + FLASH_DMA_FIRST_DESC_EXT, + FLASH_DMA_CTRL, + FLASH_DMA_MODE, + FLASH_DMA_STATUS, + FLASH_DMA_INTERRUPT_DESC, + FLASH_DMA_INTERRUPT_DESC_EXT, + FLASH_DMA_ERROR_STATUS, + FLASH_DMA_CURRENT_DESC, + FLASH_DMA_CURRENT_DESC_EXT, +}; + +#ifndef __UBOOT__ +/* flash_dma registers v0*/ +static const u16 flash_dma_regs_v0[] = { + [FLASH_DMA_REVISION] = 0x00, + [FLASH_DMA_FIRST_DESC] = 0x04, + [FLASH_DMA_CTRL] = 0x08, + [FLASH_DMA_MODE] = 0x0c, + [FLASH_DMA_STATUS] = 0x10, + [FLASH_DMA_INTERRUPT_DESC] = 0x14, + [FLASH_DMA_ERROR_STATUS] = 0x18, + [FLASH_DMA_CURRENT_DESC] = 0x1c, +}; + +/* flash_dma registers v1*/ +static const u16 flash_dma_regs_v1[] = { + [FLASH_DMA_REVISION] = 0x00, + [FLASH_DMA_FIRST_DESC] = 0x04, + [FLASH_DMA_FIRST_DESC_EXT] = 0x08, + [FLASH_DMA_CTRL] = 0x0c, + [FLASH_DMA_MODE] = 0x10, + [FLASH_DMA_STATUS] = 0x14, + [FLASH_DMA_INTERRUPT_DESC] = 0x18, + [FLASH_DMA_INTERRUPT_DESC_EXT] = 0x1c, + [FLASH_DMA_ERROR_STATUS] = 0x20, + [FLASH_DMA_CURRENT_DESC] = 0x24, + [FLASH_DMA_CURRENT_DESC_EXT] = 0x28, +}; + +/* flash_dma registers v4 */ +static const u16 flash_dma_regs_v4[] = { + [FLASH_DMA_REVISION] = 0x00, + [FLASH_DMA_FIRST_DESC] = 0x08, + [FLASH_DMA_FIRST_DESC_EXT] = 0x0c, + [FLASH_DMA_CTRL] = 0x10, + [FLASH_DMA_MODE] = 0x14, + [FLASH_DMA_STATUS] = 0x18, + [FLASH_DMA_INTERRUPT_DESC] = 0x20, + [FLASH_DMA_INTERRUPT_DESC_EXT] = 0x24, + [FLASH_DMA_ERROR_STATUS] = 0x28, + [FLASH_DMA_CURRENT_DESC] = 0x30, + [FLASH_DMA_CURRENT_DESC_EXT] = 0x34, +}; +#endif /* __UBOOT__ */ + /* Controller feature flags */ enum { BRCMNAND_HAS_1K_SECTORS = BIT(0), @@ -135,6 +200,8 @@ struct brcmnand_controller { /* List of NAND hosts (one for each chip-select) */ struct list_head host_list; + /* flash_dma reg */ + const u16 *flash_dma_offsets; struct brcm_nand_dma_desc *dma_desc; dma_addr_t dma_pa; @@ -150,6 +217,7 @@ struct brcmnand_controller { const unsigned int *block_sizes; unsigned int max_page_size; const unsigned int *page_sizes; + unsigned int page_size_shift; unsigned int max_oob; u32 features; @@ -226,8 +294,38 @@ enum brcmnand_reg { BRCMNAND_FC_BASE, }; -/* BRCMNAND v4.0 */ -static const u16 brcmnand_regs_v40[] = { +/* BRCMNAND v2.1-v2.2 */ +static const u16 brcmnand_regs_v21[] = { + [BRCMNAND_CMD_START] = 0x04, + [BRCMNAND_CMD_EXT_ADDRESS] = 0x08, + [BRCMNAND_CMD_ADDRESS] = 0x0c, + [BRCMNAND_INTFC_STATUS] = 0x5c, + [BRCMNAND_CS_SELECT] = 0x14, + [BRCMNAND_CS_XOR] = 0x18, + [BRCMNAND_LL_OP] = 0, + [BRCMNAND_CS0_BASE] = 0x40, + [BRCMNAND_CS1_BASE] = 0, + [BRCMNAND_CORR_THRESHOLD] = 0, + [BRCMNAND_CORR_THRESHOLD_EXT] = 0, + [BRCMNAND_UNCORR_COUNT] = 0, + [BRCMNAND_CORR_COUNT] = 0, + [BRCMNAND_CORR_EXT_ADDR] = 0x60, + [BRCMNAND_CORR_ADDR] = 0x64, + [BRCMNAND_UNCORR_EXT_ADDR] = 0x68, + [BRCMNAND_UNCORR_ADDR] = 0x6c, + [BRCMNAND_SEMAPHORE] = 0x50, + [BRCMNAND_ID] = 0x54, + [BRCMNAND_ID_EXT] = 0, + [BRCMNAND_LL_RDATA] = 0, + [BRCMNAND_OOB_READ_BASE] = 0x20, + [BRCMNAND_OOB_READ_10_BASE] = 0, + [BRCMNAND_OOB_WRITE_BASE] = 0x30, + [BRCMNAND_OOB_WRITE_10_BASE] = 0, + [BRCMNAND_FC_BASE] = 0x200, +}; + +/* BRCMNAND v3.3-v4.0 */ +static const u16 brcmnand_regs_v33[] = { [BRCMNAND_CMD_START] = 0x04, [BRCMNAND_CMD_EXT_ADDRESS] = 0x08, [BRCMNAND_CMD_ADDRESS] = 0x0c, @@ -424,6 +522,9 @@ enum { CFG_BUS_WIDTH = BIT(CFG_BUS_WIDTH_SHIFT), CFG_DEVICE_SIZE_SHIFT = 24, + /* Only for v2.1 */ + CFG_PAGE_SIZE_SHIFT_v2_1 = 30, + /* Only for pre-v7.1 (with no CFG_EXT register) */ CFG_PAGE_SIZE_SHIFT = 20, CFG_BLK_SIZE_SHIFT = 28, @@ -459,12 +560,16 @@ static int brcmnand_revision_init(struct brcmnand_controller *ctrl) { static const unsigned int block_sizes_v6[] = { 8, 16, 128, 256, 512, 1024, 2048, 0 }; static const unsigned int block_sizes_v4[] = { 16, 128, 8, 512, 256, 1024, 2048, 0 }; - static const unsigned int page_sizes[] = { 512, 2048, 4096, 8192, 0 }; + static const unsigned int block_sizes_v2_2[] = { 16, 128, 8, 512, 256, 0 }; + static const unsigned int block_sizes_v2_1[] = { 16, 128, 8, 512, 0 }; + static const unsigned int page_sizes_v3_4[] = { 512, 2048, 4096, 8192, 0 }; + static const unsigned int page_sizes_v2_2[] = { 512, 2048, 4096, 0 }; + static const unsigned int page_sizes_v2_1[] = { 512, 2048, 0 }; ctrl->nand_version = nand_readreg(ctrl, 0) & 0xffff; - /* Only support v4.0+? */ - if (ctrl->nand_version < 0x0400) { + /* Only support v2.1+ */ + if (ctrl->nand_version < 0x0201) { dev_err(ctrl->dev, "version %#x not supported\n", ctrl->nand_version); return -ENODEV; @@ -473,14 +578,16 @@ static int brcmnand_revision_init(struct brcmnand_controller *ctrl) /* Register offsets */ if (ctrl->nand_version >= 0x0702) ctrl->reg_offsets = brcmnand_regs_v72; - else if (ctrl->nand_version >= 0x0701) + else if (ctrl->nand_version == 0x0701) ctrl->reg_offsets = brcmnand_regs_v71; else if (ctrl->nand_version >= 0x0600) ctrl->reg_offsets = brcmnand_regs_v60; else if (ctrl->nand_version >= 0x0500) ctrl->reg_offsets = brcmnand_regs_v50; - else if (ctrl->nand_version >= 0x0400) - ctrl->reg_offsets = brcmnand_regs_v40; + else if (ctrl->nand_version >= 0x0303) + ctrl->reg_offsets = brcmnand_regs_v33; + else if (ctrl->nand_version >= 0x0201) + ctrl->reg_offsets = brcmnand_regs_v21; /* Chip-select stride */ if (ctrl->nand_version >= 0x0701) @@ -494,8 +601,9 @@ static int brcmnand_revision_init(struct brcmnand_controller *ctrl) } else { ctrl->cs_offsets = brcmnand_cs_offsets; - /* v5.0 and earlier has a different CS0 offset layout */ - if (ctrl->nand_version <= 0x0500) + /* v3.3-5.0 have a different CS0 offset layout */ + if (ctrl->nand_version >= 0x0303 && + ctrl->nand_version <= 0x0500) ctrl->cs0_offsets = brcmnand_cs_offsets_cs0; } @@ -505,20 +613,38 @@ static int brcmnand_revision_init(struct brcmnand_controller *ctrl) ctrl->max_page_size = 16 * 1024; ctrl->max_block_size = 2 * 1024 * 1024; } else { - ctrl->page_sizes = page_sizes; + if (ctrl->nand_version >= 0x0304) + ctrl->page_sizes = page_sizes_v3_4; + else if (ctrl->nand_version >= 0x0202) + ctrl->page_sizes = page_sizes_v2_2; + else + ctrl->page_sizes = page_sizes_v2_1; + + if (ctrl->nand_version >= 0x0202) + ctrl->page_size_shift = CFG_PAGE_SIZE_SHIFT; + else + ctrl->page_size_shift = CFG_PAGE_SIZE_SHIFT_v2_1; + if (ctrl->nand_version >= 0x0600) ctrl->block_sizes = block_sizes_v6; - else + else if (ctrl->nand_version >= 0x0400) ctrl->block_sizes = block_sizes_v4; + else if (ctrl->nand_version >= 0x0202) + ctrl->block_sizes = block_sizes_v2_2; + else + ctrl->block_sizes = block_sizes_v2_1; if (ctrl->nand_version < 0x0400) { - ctrl->max_page_size = 4096; + if (ctrl->nand_version < 0x0202) + ctrl->max_page_size = 2048; + else + ctrl->max_page_size = 4096; ctrl->max_block_size = 512 * 1024; } } /* Maximum spare area sector size (per 512B) */ - if (ctrl->nand_version >= 0x0702) + if (ctrl->nand_version == 0x0702) ctrl->max_oob = 128; else if (ctrl->nand_version >= 0x0600) ctrl->max_oob = 64; @@ -553,6 +679,19 @@ static int brcmnand_revision_init(struct brcmnand_controller *ctrl) return 0; } +#ifndef __UBOOT__ +static void brcmnand_flash_dma_revision_init(struct brcmnand_controller *ctrl) +{ + /* flash_dma register offsets */ + if (ctrl->nand_version >= 0x0703) + ctrl->flash_dma_offsets = flash_dma_regs_v4; + else if (ctrl->nand_version == 0x0602) + ctrl->flash_dma_offsets = flash_dma_regs_v0; + else + ctrl->flash_dma_offsets = flash_dma_regs_v1; +} +#endif /* __UBOOT__ */ + static inline u32 brcmnand_read_reg(struct brcmnand_controller *ctrl, enum brcmnand_reg reg) { @@ -595,6 +734,54 @@ static inline void brcmnand_write_fc(struct brcmnand_controller *ctrl, __raw_writel(val, ctrl->nand_fc + word * 4); } +static void brcmnand_clear_ecc_addr(struct brcmnand_controller *ctrl) +{ + + /* Clear error addresses */ + brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_ADDR, 0); + brcmnand_write_reg(ctrl, BRCMNAND_CORR_ADDR, 0); + brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_EXT_ADDR, 0); + brcmnand_write_reg(ctrl, BRCMNAND_CORR_EXT_ADDR, 0); +} + +static u64 brcmnand_get_uncorrecc_addr(struct brcmnand_controller *ctrl) +{ + u64 err_addr; + + err_addr = brcmnand_read_reg(ctrl, BRCMNAND_UNCORR_ADDR); + err_addr |= ((u64)(brcmnand_read_reg(ctrl, + BRCMNAND_UNCORR_EXT_ADDR) + & 0xffff) << 32); + + return err_addr; +} + +static u64 brcmnand_get_correcc_addr(struct brcmnand_controller *ctrl) +{ + u64 err_addr; + + err_addr = brcmnand_read_reg(ctrl, BRCMNAND_CORR_ADDR); + err_addr |= ((u64)(brcmnand_read_reg(ctrl, + BRCMNAND_CORR_EXT_ADDR) + & 0xffff) << 32); + + return err_addr; +} + +static void brcmnand_set_cmd_addr(struct mtd_info *mtd, u64 addr) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + struct brcmnand_host *host = nand_get_controller_data(chip); + struct brcmnand_controller *ctrl = host->ctrl; + + brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS, + (host->cs << 16) | ((addr >> 32) & 0xffff)); + (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS); + brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS, + lower_32_bits(addr)); + (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS); +} + static inline u16 brcmnand_cs_offset(struct brcmnand_controller *ctrl, int cs, enum brcmnand_cs_reg reg) { @@ -627,7 +814,10 @@ static void brcmnand_wr_corr_thresh(struct brcmnand_host *host, u8 val) enum brcmnand_reg reg = BRCMNAND_CORR_THRESHOLD; int cs = host->cs; - if (ctrl->nand_version >= 0x0702) + if (!ctrl->reg_offsets[reg]) + return; + + if (ctrl->nand_version == 0x0702) bits = 7; else if (ctrl->nand_version >= 0x0600) bits = 6; @@ -681,12 +871,14 @@ enum { static inline u32 brcmnand_spare_area_mask(struct brcmnand_controller *ctrl) { - if (ctrl->nand_version >= 0x0702) + if (ctrl->nand_version == 0x0702) return GENMASK(7, 0); else if (ctrl->nand_version >= 0x0600) return GENMASK(6, 0); - else + else if (ctrl->nand_version >= 0x0303) return GENMASK(5, 0); + else + return GENMASK(4, 0); } #define NAND_ACC_CONTROL_ECC_SHIFT 16 @@ -829,20 +1021,6 @@ static inline void brcmnand_set_wp(struct brcmnand_controller *ctrl, bool en) * Flash DMA ***********************************************************************/ -enum flash_dma_reg { - FLASH_DMA_REVISION = 0x00, - FLASH_DMA_FIRST_DESC = 0x04, - FLASH_DMA_FIRST_DESC_EXT = 0x08, - FLASH_DMA_CTRL = 0x0c, - FLASH_DMA_MODE = 0x10, - FLASH_DMA_STATUS = 0x14, - FLASH_DMA_INTERRUPT_DESC = 0x18, - FLASH_DMA_INTERRUPT_DESC_EXT = 0x1c, - FLASH_DMA_ERROR_STATUS = 0x20, - FLASH_DMA_CURRENT_DESC = 0x24, - FLASH_DMA_CURRENT_DESC_EXT = 0x28, -}; - static inline bool has_flash_dma(struct brcmnand_controller *ctrl) { return ctrl->flash_dma_base; @@ -858,14 +1036,19 @@ static inline bool flash_dma_buf_ok(const void *buf) #endif /* __UBOOT__ */ } -static inline void flash_dma_writel(struct brcmnand_controller *ctrl, u8 offs, - u32 val) +static inline void flash_dma_writel(struct brcmnand_controller *ctrl, + enum flash_dma_reg dma_reg, u32 val) { + u16 offs = ctrl->flash_dma_offsets[dma_reg]; + brcmnand_writel(val, ctrl->flash_dma_base + offs); } -static inline u32 flash_dma_readl(struct brcmnand_controller *ctrl, u8 offs) +static inline u32 flash_dma_readl(struct brcmnand_controller *ctrl, + enum flash_dma_reg dma_reg) { + u16 offs = ctrl->flash_dma_offsets[dma_reg]; + return brcmnand_readl(ctrl->flash_dma_base + offs); } @@ -1190,9 +1373,12 @@ static void brcmnand_send_cmd(struct brcmnand_host *host, int cmd) { struct brcmnand_controller *ctrl = host->ctrl; int ret; + u64 cmd_addr; + + cmd_addr = brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS); + + dev_dbg(ctrl->dev, "send native cmd %d addr 0x%llx\n", cmd, cmd_addr); - dev_dbg(ctrl->dev, "send native cmd %d addr_lo 0x%x\n", cmd, - brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS)); BUG_ON(ctrl->cmd_pending != 0); ctrl->cmd_pending = cmd; @@ -1365,12 +1551,7 @@ static void brcmnand_cmdfunc(struct mtd_info *mtd, unsigned command, if (!native_cmd) return; - brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS, - (host->cs << 16) | ((addr >> 32) & 0xffff)); - (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS); - brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS, lower_32_bits(addr)); - (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS); - + brcmnand_set_cmd_addr(mtd, addr); brcmnand_send_cmd(host, native_cmd); brcmnand_waitfunc(mtd, chip); @@ -1542,8 +1723,11 @@ static void brcmnand_dma_run(struct brcmnand_host *host, dma_addr_t desc) flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC, lower_32_bits(desc)); (void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC); - flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC_EXT, upper_32_bits(desc)); - (void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC_EXT); + if (ctrl->nand_version > 0x0602) { + flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC_EXT, + upper_32_bits(desc)); + (void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC_EXT); + } /* Start FLASH_DMA engine */ ctrl->dma_pending = true; @@ -1600,20 +1784,10 @@ static int brcmnand_read_by_pio(struct mtd_info *mtd, struct nand_chip *chip, struct brcmnand_controller *ctrl = host->ctrl; int i, j, ret = 0; - /* Clear error addresses */ - brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_ADDR, 0); - brcmnand_write_reg(ctrl, BRCMNAND_CORR_ADDR, 0); - brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_EXT_ADDR, 0); - brcmnand_write_reg(ctrl, BRCMNAND_CORR_EXT_ADDR, 0); - - brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS, - (host->cs << 16) | ((addr >> 32) & 0xffff)); - (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS); + brcmnand_clear_ecc_addr(ctrl); for (i = 0; i < trans; i++, addr += FC_BYTES) { - brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS, - lower_32_bits(addr)); - (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS); + brcmnand_set_cmd_addr(mtd, addr); /* SPARE_AREA_READ does not use ECC, so just use PAGE_READ */ brcmnand_send_cmd(host, CMD_PAGE_READ); brcmnand_waitfunc(mtd, chip); @@ -1633,21 +1807,15 @@ static int brcmnand_read_by_pio(struct mtd_info *mtd, struct nand_chip *chip, host->hwcfg.sector_size_1k); if (ret != -EBADMSG) { - *err_addr = brcmnand_read_reg(ctrl, - BRCMNAND_UNCORR_ADDR) | - ((u64)(brcmnand_read_reg(ctrl, - BRCMNAND_UNCORR_EXT_ADDR) - & 0xffff) << 32); + *err_addr = brcmnand_get_uncorrecc_addr(ctrl); + if (*err_addr) ret = -EBADMSG; } if (!ret) { - *err_addr = brcmnand_read_reg(ctrl, - BRCMNAND_CORR_ADDR) | - ((u64)(brcmnand_read_reg(ctrl, - BRCMNAND_CORR_EXT_ADDR) - & 0xffff) << 32); + *err_addr = brcmnand_get_correcc_addr(ctrl); + if (*err_addr) ret = -EUCLEAN; } @@ -1673,11 +1841,13 @@ static int brcmnand_read_by_pio(struct mtd_info *mtd, struct nand_chip *chip, static int brcmstb_nand_verify_erased_page(struct mtd_info *mtd, struct nand_chip *chip, void *buf, u64 addr) { - int i, sas; - void *oob = chip->oob_poi; + struct mtd_oob_region ecc; + int i; int bitflips = 0; int page = addr >> chip->page_shift; int ret; + void *ecc_bytes; + void *ecc_chunk; if (!buf) { #ifndef __UBOOT__ @@ -1689,16 +1859,20 @@ static int brcmstb_nand_verify_erased_page(struct mtd_info *mtd, chip->pagebuf = -1; } - sas = mtd->oobsize / chip->ecc.steps; - /* read without ecc for verification */ ret = chip->ecc.read_page_raw(mtd, chip, buf, true, page); if (ret) return ret; - for (i = 0; i < chip->ecc.steps; i++, oob += sas) { - ret = nand_check_erased_ecc_chunk(buf, chip->ecc.size, - oob, sas, NULL, 0, + for (i = 0; i < chip->ecc.steps; i++) { + ecc_chunk = buf + chip->ecc.size * i; + + mtd_ooblayout_ecc(mtd, i, &ecc); + ecc_bytes = chip->oob_poi + ecc.offset; + + ret = nand_check_erased_ecc_chunk(ecc_chunk, chip->ecc.size, + ecc_bytes, ecc.length, + NULL, 0, chip->ecc.strength); if (ret < 0) return ret; @@ -1721,7 +1895,7 @@ static int brcmnand_read(struct mtd_info *mtd, struct nand_chip *chip, dev_dbg(ctrl->dev, "read %llx -> %p\n", (unsigned long long)addr, buf); try_dmaread: - brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_COUNT, 0); + brcmnand_clear_ecc_addr(ctrl); #ifndef __UBOOT__ if (has_flash_dma(ctrl) && !oob && flash_dma_buf_ok(buf)) { @@ -1875,15 +2049,9 @@ static int brcmnand_write(struct mtd_info *mtd, struct nand_chip *chip, } #endif /* __UBOOT__ */ - brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS, - (host->cs << 16) | ((addr >> 32) & 0xffff)); - (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS); - for (i = 0; i < trans; i++, addr += FC_BYTES) { /* full address MUST be set before populating FC */ - brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS, - lower_32_bits(addr)); - (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS); + brcmnand_set_cmd_addr(mtd, addr); if (buf) { brcmnand_soc_data_bus_prepare(ctrl->soc, false); @@ -2044,7 +2212,7 @@ static int brcmnand_set_cfg(struct brcmnand_host *host, (!!(cfg->device_width == 16) << CFG_BUS_WIDTH_SHIFT) | (device_size << CFG_DEVICE_SIZE_SHIFT); if (cfg_offs == cfg_ext_offs) { - tmp |= (page_size << CFG_PAGE_SIZE_SHIFT) | + tmp |= (page_size << ctrl->page_size_shift) | (block_size << CFG_BLK_SIZE_SHIFT); nand_writereg(ctrl, cfg_offs, tmp); } else { @@ -2056,9 +2224,11 @@ static int brcmnand_set_cfg(struct brcmnand_host *host, tmp = nand_readreg(ctrl, acc_control_offs); tmp &= ~brcmnand_ecc_level_mask(ctrl); - tmp |= cfg->ecc_level << NAND_ACC_CONTROL_ECC_SHIFT; tmp &= ~brcmnand_spare_area_mask(ctrl); - tmp |= cfg->spare_area_size; + if (ctrl->nand_version >= 0x0302) { + tmp |= cfg->ecc_level << NAND_ACC_CONTROL_ECC_SHIFT; + tmp |= cfg->spare_area_size; + } nand_writereg(ctrl, acc_control_offs, tmp); brcmnand_set_sector_size_1k(host, cfg->sector_size_1k); @@ -2345,6 +2515,12 @@ static int brcmnand_init_cs(struct brcmnand_host *host, ofnode dn) ret = nand_register(0, mtd); #endif /* __UBOOT__ */ + /* If OOB is written with ECC enabled it will cause ECC errors */ + if (is_hamming_ecc(host->ctrl, &host->hwcfg)) { + chip->ecc.write_oob = brcmnand_write_oob_raw; + chip->ecc.read_oob = brcmnand_read_oob_raw; + } + return ret; } @@ -2438,6 +2614,8 @@ const struct dev_pm_ops brcmnand_pm_ops = { EXPORT_SYMBOL_GPL(brcmnand_pm_ops); static const struct of_device_id brcmnand_of_match[] = { + { .compatible = "brcm,brcmnand-v2.1" }, + { .compatible = "brcm,brcmnand-v2.2" }, { .compatible = "brcm,brcmnand-v4.0" }, { .compatible = "brcm,brcmnand-v5.0" }, { .compatible = "brcm,brcmnand-v6.0" }, @@ -2446,6 +2624,7 @@ static const struct of_device_id brcmnand_of_match[] = { { .compatible = "brcm,brcmnand-v7.0" }, { .compatible = "brcm,brcmnand-v7.1" }, { .compatible = "brcm,brcmnand-v7.2" }, + { .compatible = "brcm,brcmnand-v7.3" }, {}, }; MODULE_DEVICE_TABLE(of, brcmnand_of_match); @@ -2576,7 +2755,11 @@ int brcmnand_probe(struct udevice *dev, struct brcmnand_soc *soc) goto err; } - flash_dma_writel(ctrl, FLASH_DMA_MODE, 1); /* linked-list */ + /* initialize the dma version */ + brcmnand_flash_dma_revision_init(ctrl); + + /* linked-list and stop on error */ + flash_dma_writel(ctrl, FLASH_DMA_MODE, FLASH_DMA_MODE_MASK); flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0); /* Allocate descriptor(s) */ diff --git a/drivers/mtd/nand/raw/kb9202_nand.c b/drivers/mtd/nand/raw/kb9202_nand.c deleted file mode 100644 index 9d26532c780..00000000000 --- a/drivers/mtd/nand/raw/kb9202_nand.c +++ /dev/null @@ -1,134 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2006 - * KwikByte <kb9200_dev@kwikbyte.com> - * - * (C) Copyright 2009 - * Matthias Kaehlcke <matthias@kaehlcke.net> - */ - -#include <common.h> -#include <linux/mtd/rawnand.h> -#include <asm/io.h> -#include <asm/arch/AT91RM9200.h> -#include <asm/arch/hardware.h> - -#include <nand.h> - -/* - * hardware specific access to control-lines - */ - -#define MASK_ALE (1 << 22) /* our ALE is A22 */ -#define MASK_CLE (1 << 21) /* our CLE is A21 */ - -#define KB9202_NAND_NCE (1 << 28) /* EN* on D28 */ -#define KB9202_NAND_BUSY (1 << 29) /* RB* on D29 */ - -#define KB9202_SMC2_NWS (1 << 2) -#define KB9202_SMC2_TDF (1 << 8) -#define KB9202_SMC2_RWSETUP (1 << 24) -#define KB9202_SMC2_RWHOLD (1 << 29) - -/* - * Board-specific function to access device control signals - */ -static void kb9202_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) -{ - struct nand_chip *this = mtd_to_nand(mtd); - - if (ctrl & NAND_CTRL_CHANGE) { - ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; - - /* clear ALE and CLE bits */ - IO_ADDR_W &= ~(MASK_ALE | MASK_CLE); - - if (ctrl & NAND_CLE) - IO_ADDR_W |= MASK_CLE; - - if (ctrl & NAND_ALE) - IO_ADDR_W |= MASK_ALE; - - this->IO_ADDR_W = (void *) IO_ADDR_W; - - if (ctrl & NAND_NCE) - writel(KB9202_NAND_NCE, AT91C_PIOC_CODR); - else - writel(KB9202_NAND_NCE, AT91C_PIOC_SODR); - } - - if (cmd != NAND_CMD_NONE) - writeb(cmd, this->IO_ADDR_W); -} - - -/* - * Board-specific function to access the device ready signal. - */ -static int kb9202_nand_ready(struct mtd_info *mtd) -{ - return readl(AT91C_PIOC_PDSR) & KB9202_NAND_BUSY; -} - - -/* - * Board-specific NAND init. Copied from include/linux/mtd/nand.h for reference. - * - * struct nand_chip - NAND Private Flash Chip Data - * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device - * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device - * @hwcontrol: [BOARDSPECIFIC] hardwarespecific function for accesing control-lines - * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line - * If set to NULL no access to ready/busy is available and the ready/busy information - * is read from the chip status register - * @enable_hwecc: [BOARDSPECIFIC] function to enable (reset) hardware ecc generator. Must only - * be provided if a hardware ECC is available - * @eccmode: [BOARDSPECIFIC] mode of ecc, see defines - * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR) - * @options: [BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about - * special functionality. See the defines for further explanation -*/ -/* - * This routine initializes controller and GPIOs. - */ -int board_nand_init(struct nand_chip *nand) -{ - unsigned int value; - - nand->ecc.mode = NAND_ECC_SOFT; - nand->cmd_ctrl = kb9202_nand_hwcontrol; - nand->dev_ready = kb9202_nand_ready; - - /* in case running outside of bootloader */ - writel(1 << AT91C_ID_PIOC, AT91C_PMC_PCER); - - /* setup nand flash access (allow ample margin) */ - /* 4 wait states, 1 setup, 1 hold, 1 float for 8-bit device */ - writel(AT91C_SMC2_WSEN | KB9202_SMC2_NWS | KB9202_SMC2_TDF | - AT91C_SMC2_DBW_8 | KB9202_SMC2_RWSETUP | KB9202_SMC2_RWHOLD, - AT91C_SMC_CSR3); - - /* enable internal NAND controller */ - value = readl(AT91C_EBI_CSA); - value |= AT91C_EBI_CS3A_SMC_SmartMedia; - writel(value, AT91C_EBI_CSA); - - /* enable SMOE/SMWE */ - writel(AT91C_PC1_BFRDY_SMOE | AT91C_PC3_BFBAA_SMWE, AT91C_PIOC_ASR); - writel(AT91C_PC1_BFRDY_SMOE | AT91C_PC3_BFBAA_SMWE, AT91C_PIOC_PDR); - writel(AT91C_PC1_BFRDY_SMOE | AT91C_PC3_BFBAA_SMWE, AT91C_PIOC_OER); - - /* set NCE to high */ - writel(KB9202_NAND_NCE, AT91C_PIOC_SODR); - - /* disable output on pin connected to the busy line of the NAND */ - writel(KB9202_NAND_BUSY, AT91C_PIOC_ODR); - - /* enable the PIO to control NCE and BUSY */ - writel(KB9202_NAND_NCE | KB9202_NAND_BUSY, AT91C_PIOC_PER); - - /* enable output for NCE */ - writel(KB9202_NAND_NCE, AT91C_PIOC_OER); - - return (0); -} diff --git a/drivers/mtd/nand/raw/nand_bbt.c b/drivers/mtd/nand/raw/nand_bbt.c index 911472e91e1..cd451870a6f 100644 --- a/drivers/mtd/nand/raw/nand_bbt.c +++ b/drivers/mtd/nand/raw/nand_bbt.c @@ -1330,6 +1330,7 @@ int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs) * @mtd: MTD device structure * @offs: offset in the device * @allowbbt: allow access to bad block table region + * Return: 0 - good block, 1- bad block, 2 - reserved block */ int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt) { @@ -1348,7 +1349,7 @@ int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt) case BBT_BLOCK_WORN: return 1; case BBT_BLOCK_RESERVED: - return allowbbt ? 0 : 1; + return allowbbt ? 0 : 2; } return 1; } diff --git a/drivers/mtd/nand/raw/nand_util.c b/drivers/mtd/nand/raw/nand_util.c index b2345dca7f7..72cc24f4037 100644 --- a/drivers/mtd/nand/raw/nand_util.c +++ b/drivers/mtd/nand/raw/nand_util.c @@ -113,9 +113,10 @@ int nand_erase_opts(struct mtd_info *mtd, int ret = mtd_block_isbad(mtd, erase.addr); if (ret > 0) { if (!opts->quiet) - printf("\rSkipping bad block at " + printf("\rSkipping %s at " "0x%08llx " " \n", + ret == 1 ? "bad block" : "bbt reserved", erase.addr); if (!opts->spread) diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index 134bf22c805..70d8ae531ee 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -979,8 +979,9 @@ static int spinand_detect(struct spinand_device *spinand) ret = spinand_manufacturer_detect(spinand); if (ret) { - dev_err(spinand->slave->dev, "unknown raw ID %*phN\n", - SPINAND_MAX_ID_LEN, spinand->id.data); + dev_err(spinand->slave->dev, "unknown raw ID %02x %02x %02x %02x\n", + spinand->id.data[0], spinand->id.data[1], + spinand->id.data[2], spinand->id.data[3]); return ret; } diff --git a/drivers/mux/Makefile b/drivers/mux/Makefile index 78ebf04c7a9..d4e24789d33 100644 --- a/drivers/mux/Makefile +++ b/drivers/mux/Makefile @@ -3,5 +3,5 @@ # (C) Copyright 2019 # Jean-Jacques Hiblot <jjhiblot@ti.com> -obj-$(CONFIG_$(SPL_)MULTIPLEXER) += mux-uclass.o +obj-$(CONFIG_MULTIPLEXER) += mux-uclass.o obj-$(CONFIG_$(SPL_)MUX_MMIO) += mmio.o diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index 112deb546de..ec58697b311 100644 --- a/drivers/net/dwc_eth_qos.c +++ b/drivers/net/dwc_eth_qos.c @@ -108,7 +108,7 @@ void eqos_flush_desc_generic(void *desc) flush_dcache_range(start, end); } -void eqos_inval_buffer_tegra186(void *buf, size_t size) +static void eqos_inval_buffer_tegra186(void *buf, size_t size) { unsigned long start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1); unsigned long end = ALIGN(start + size, ARCH_DMA_MINALIGN); @@ -761,6 +761,12 @@ static int eqos_start(struct udevice *dev) eqos->reg_access_ok = true; + /* + * Assert the SWR first, the actually reset the MAC and to latch in + * e.g. i.MX8M Plus GPR[1] content, which selects interface mode. + */ + setbits_le32(&eqos->dma_regs->mode, EQOS_DMA_MODE_SWR); + ret = wait_for_bit_le32(&eqos->dma_regs->mode, EQOS_DMA_MODE_SWR, false, eqos->config->swr_wait, false); @@ -1383,7 +1389,6 @@ static int eqos_probe_resources_tegra186(struct udevice *dev) if (ret) { pr_err("clk_get_by_name(ptp_ref) failed: %d", ret); goto err_free_clk_rx; - return ret; } ret = clk_get_by_name(dev, "tx", &eqos->clk_tx); @@ -1412,13 +1417,6 @@ err_free_reset_eqos: return ret; } -/* board-specific Ethernet Interface initializations. */ -__weak int board_interface_eth_init(struct udevice *dev, - phy_interface_t interface_type) -{ - return 0; -} - static int eqos_probe_resources_stm32(struct udevice *dev) { struct eqos_priv *eqos = dev_get_priv(dev); @@ -1501,7 +1499,7 @@ static int eqos_remove_resources_tegra186(struct udevice *dev) static int eqos_remove_resources_stm32(struct udevice *dev) { - struct eqos_priv *eqos = dev_get_priv(dev); + struct eqos_priv * __maybe_unused eqos = dev_get_priv(dev); debug("%s(dev=%p):\n", __func__, dev); @@ -1513,9 +1511,6 @@ static int eqos_remove_resources_stm32(struct udevice *dev) clk_free(&eqos->clk_ck); #endif - if (dm_gpio_is_valid(&eqos->phy_reset_gpio)) - dm_gpio_free(dev, &eqos->phy_reset_gpio); - debug("%s: OK\n", __func__); return 0; } diff --git a/drivers/net/dwc_eth_qos_imx.c b/drivers/net/dwc_eth_qos_imx.c index 42cb164ad14..60f3f3f5a10 100644 --- a/drivers/net/dwc_eth_qos_imx.c +++ b/drivers/net/dwc_eth_qos_imx.c @@ -7,6 +7,7 @@ #include <clk.h> #include <cpu_func.h> #include <dm.h> +#include <dm/device_compat.h> #include <errno.h> #include <eth_phy.h> #include <log.h> @@ -32,20 +33,18 @@ __weak u32 imx_get_eqos_csr_clk(void) return 100 * 1000000; } -__weak int imx_eqos_txclk_set_rate(unsigned long rate) -{ - return 0; -} - static ulong eqos_get_tick_clk_rate_imx(struct udevice *dev) { - return imx_get_eqos_csr_clk(); + struct eqos_priv *eqos = dev_get_priv(dev); + + return clk_get_rate(&eqos->clk_master_bus); } static int eqos_probe_resources_imx(struct udevice *dev) { struct eqos_priv *eqos = dev_get_priv(dev); phy_interface_t interface; + int ret; debug("%s(dev=%p):\n", __func__, dev); @@ -56,6 +55,122 @@ static int eqos_probe_resources_imx(struct udevice *dev) return -EINVAL; } + ret = board_interface_eth_init(dev, interface); + if (ret) + return -EINVAL; + + eqos->max_speed = dev_read_u32_default(dev, "max-speed", 0); + + ret = clk_get_by_name(dev, "stmmaceth", &eqos->clk_master_bus); + if (ret) { + dev_dbg(dev, "clk_get_by_name(master_bus) failed: %d", ret); + goto err_probe; + } + + ret = clk_get_by_name(dev, "ptp_ref", &eqos->clk_ptp_ref); + if (ret) { + dev_dbg(dev, "clk_get_by_name(ptp_ref) failed: %d", ret); + goto err_free_clk_master_bus; + } + + ret = clk_get_by_name(dev, "tx", &eqos->clk_tx); + if (ret) { + dev_dbg(dev, "clk_get_by_name(tx) failed: %d", ret); + goto err_free_clk_ptp_ref; + } + + ret = clk_get_by_name(dev, "pclk", &eqos->clk_ck); + if (ret) { + dev_dbg(dev, "clk_get_by_name(pclk) failed: %d", ret); + goto err_free_clk_tx; + } + + debug("%s: OK\n", __func__); + return 0; + +err_free_clk_tx: + clk_free(&eqos->clk_tx); +err_free_clk_ptp_ref: + clk_free(&eqos->clk_ptp_ref); +err_free_clk_master_bus: + clk_free(&eqos->clk_master_bus); +err_probe: + + debug("%s: returns %d\n", __func__, ret); + return ret; +} + +static int eqos_remove_resources_imx(struct udevice *dev) +{ + struct eqos_priv *eqos = dev_get_priv(dev); + + debug("%s(dev=%p):\n", __func__, dev); + + clk_free(&eqos->clk_ck); + clk_free(&eqos->clk_tx); + clk_free(&eqos->clk_ptp_ref); + clk_free(&eqos->clk_master_bus); + + debug("%s: OK\n", __func__); + return 0; +} + +static int eqos_start_clks_imx(struct udevice *dev) +{ + struct eqos_priv *eqos = dev_get_priv(dev); + int ret; + + debug("%s(dev=%p):\n", __func__, dev); + + ret = clk_enable(&eqos->clk_master_bus); + if (ret < 0) { + dev_dbg(dev, "clk_enable(clk_master_bus) failed: %d", ret); + goto err; + } + + ret = clk_enable(&eqos->clk_ptp_ref); + if (ret < 0) { + dev_dbg(dev, "clk_enable(clk_ptp_ref) failed: %d", ret); + goto err_disable_clk_master_bus; + } + + ret = clk_enable(&eqos->clk_tx); + if (ret < 0) { + dev_dbg(dev, "clk_enable(clk_tx) failed: %d", ret); + goto err_disable_clk_ptp_ref; + } + + ret = clk_enable(&eqos->clk_ck); + if (ret < 0) { + dev_dbg(dev, "clk_enable(clk_ck) failed: %d", ret); + goto err_disable_clk_tx; + } + + debug("%s: OK\n", __func__); + return 0; + +err_disable_clk_tx: + clk_disable(&eqos->clk_tx); +err_disable_clk_ptp_ref: + clk_disable(&eqos->clk_ptp_ref); +err_disable_clk_master_bus: + clk_disable(&eqos->clk_master_bus); +err: + debug("%s: FAILED: %d\n", __func__, ret); + return ret; +} + +static int eqos_stop_clks_imx(struct udevice *dev) +{ + struct eqos_priv *eqos = dev_get_priv(dev); + + debug("%s(dev=%p):\n", __func__, dev); + + clk_disable(&eqos->clk_ck); + clk_disable(&eqos->clk_tx); + clk_disable(&eqos->clk_ptp_ref); + clk_disable(&eqos->clk_master_bus); + debug("%s: OK\n", __func__); return 0; } @@ -68,22 +183,29 @@ static int eqos_set_tx_clk_speed_imx(struct udevice *dev) debug("%s(dev=%p):\n", __func__, dev); - switch (eqos->phy->speed) { - case SPEED_1000: - rate = 125 * 1000 * 1000; - break; - case SPEED_100: - rate = 25 * 1000 * 1000; - break; - case SPEED_10: - rate = 2.5 * 1000 * 1000; - break; - default: + if (eqos->phy->interface == PHY_INTERFACE_MODE_RMII) + rate = 5000; /* 5000 kHz = 5 MHz */ + else + rate = 2500; /* 2500 kHz = 2.5 MHz */ + + if (eqos->phy->speed == SPEED_1000 && + (eqos->phy->interface == PHY_INTERFACE_MODE_RGMII || + eqos->phy->interface == PHY_INTERFACE_MODE_RGMII_ID || + eqos->phy->interface == PHY_INTERFACE_MODE_RGMII_RXID || + eqos->phy->interface == PHY_INTERFACE_MODE_RGMII_TXID)) { + rate *= 50; /* Use 50x base rate i.e. 125 MHz */ + } else if (eqos->phy->speed == SPEED_100) { + rate *= 10; /* Use 10x base rate */ + } else if (eqos->phy->speed == SPEED_10) { + rate *= 1; /* Use base rate */ + } else { pr_err("invalid speed %d", eqos->phy->speed); return -EINVAL; } - ret = imx_eqos_txclk_set_rate(rate); + rate *= 1000; /* clk_set_rate() operates in Hz */ + + ret = clk_set_rate(&eqos->clk_tx, rate); if (ret < 0) { pr_err("imx (tx_clk, %lu) failed: %d", rate, ret); return ret; @@ -107,11 +229,11 @@ static struct eqos_ops eqos_imx_ops = { .eqos_inval_buffer = eqos_inval_buffer_generic, .eqos_flush_buffer = eqos_flush_buffer_generic, .eqos_probe_resources = eqos_probe_resources_imx, - .eqos_remove_resources = eqos_null_ops, + .eqos_remove_resources = eqos_remove_resources_imx, .eqos_stop_resets = eqos_null_ops, .eqos_start_resets = eqos_null_ops, - .eqos_stop_clks = eqos_null_ops, - .eqos_start_clks = eqos_null_ops, + .eqos_stop_clks = eqos_stop_clks_imx, + .eqos_start_clks = eqos_start_clks_imx, .eqos_calibrate_pads = eqos_null_ops, .eqos_disable_calibration = eqos_null_ops, .eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_imx, diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 1a6c18a441f..ac937676f9c 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -1196,6 +1196,33 @@ static void fec_gpio_reset(struct fec_priv *priv) } #endif +static int fecmxc_set_ref_clk(struct clk *clk_ref, phy_interface_t interface) +{ + unsigned int freq; + int ret; + + if (!CONFIG_IS_ENABLED(CLK_CCF)) + return 0; + + if (interface == PHY_INTERFACE_MODE_MII) + freq = 25000000; + else if (interface == PHY_INTERFACE_MODE_RMII) + freq = 50000000; + else if (interface == PHY_INTERFACE_MODE_RGMII || + interface == PHY_INTERFACE_MODE_RGMII_ID || + interface == PHY_INTERFACE_MODE_RGMII_RXID || + interface == PHY_INTERFACE_MODE_RGMII_TXID) + freq = 125000000; + else + return -EINVAL; + + ret = clk_set_rate(clk_ref, freq); + if (ret < 0) + return ret; + + return 0; +} + static int fecmxc_probe(struct udevice *dev) { bool dm_mii_bus = true; @@ -1205,6 +1232,10 @@ static int fecmxc_probe(struct udevice *dev) uint32_t start; int ret; + ret = board_interface_eth_init(dev, pdata->phy_interface); + if (ret) + return ret; + if (IS_ENABLED(CONFIG_IMX_MODULE_FUSE)) { if (enet_fused((ulong)priv->eth)) { printf("SoC fuse indicates Ethernet@0x%lx is unavailable.\n", (ulong)priv->eth); @@ -1253,6 +1284,11 @@ static int fecmxc_probe(struct udevice *dev) ret = clk_get_by_name(dev, "enet_clk_ref", &priv->clk_ref); if (!ret) { + ret = fecmxc_set_ref_clk(&priv->clk_ref, + pdata->phy_interface); + if (ret) + return ret; + ret = clk_enable(&priv->clk_ref); if (ret) return ret; diff --git a/drivers/net/mvneta.c b/drivers/net/mvneta.c index 0fbfad11d45..24933473fa0 100644 --- a/drivers/net/mvneta.c +++ b/drivers/net/mvneta.c @@ -815,7 +815,7 @@ static void mvneta_defaults_set(struct mvneta_port *pp) mvreg_write(pp, MVNETA_SDMA_CONFIG, val); /* Enable PHY polling in hardware if not in fixed-link mode */ - if (!CONFIG_IS_ENABLED(PHY_FIXED) || + if (!IS_ENABLED(CONFIG_PHY_FIXED) || pp->phydev->phy_id != PHY_FIXED_ID) { mvreg_write(pp, MVNETA_PHY_ADDR, pp->phydev->addr); @@ -1176,7 +1176,7 @@ static void mvneta_adjust_link(struct udevice *dev) * be added). Also, why is ADVERT_FC enabled if we don't enable * inband AN at all? */ - if (CONFIG_IS_ENABLED(PHY_FIXED) && + if (IS_ENABLED(CONFIG_PHY_FIXED) && pp->phydev->phy_id == PHY_FIXED_ID) val = MVNETA_GMAC_IB_BYPASS_AN_EN | MVNETA_GMAC_SET_FC_EN | diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 5eaff053a09..6806e3c0903 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -106,6 +106,9 @@ config PHY_AQUANTIA_FW_NAME config PHY_ATHEROS bool "Atheros Ethernet PHYs support" +config SPL_PHY_ATHEROS + bool "Atheros Ethernet PHYs support (SPL)" + config PHY_BROADCOM bool "Broadcom Ethernet PHYs support" diff --git a/drivers/net/ravb.c b/drivers/net/ravb.c index 5a835cc06ff..0bc50dc7335 100644 --- a/drivers/net/ravb.c +++ b/drivers/net/ravb.c @@ -310,7 +310,7 @@ static int ravb_phy_config(struct udevice *dev) struct ravb_priv *eth = dev_get_priv(dev); struct eth_pdata *pdata = dev_get_plat(dev); struct phy_device *phydev; - int mask = 0xffffffff, reg; + int reg; if (dm_gpio_is_valid(ð->reset_gpio)) { dm_gpio_set_value(ð->reset_gpio, 1); @@ -319,12 +319,10 @@ static int ravb_phy_config(struct udevice *dev) mdelay(1); } - phydev = phy_find_by_mask(eth->bus, mask); + phydev = phy_connect(eth->bus, -1, dev, pdata->phy_interface); if (!phydev) return -ENODEV; - phy_connect_dev(phydev, dev, pdata->phy_interface); - eth->phydev = phydev; phydev->supported &= SUPPORTED_100baseT_Full | diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index cc49788012f..211b2c6e556 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -738,7 +738,7 @@ static int gem_zynqmp_set_dynamic_config(struct udevice *dev) u32 pm_info[2]; int ret; - if (IS_ENABLED(CONFIG_ARCH_ZYNQMP)) { + if (IS_ENABLED(CONFIG_ARCH_ZYNQMP) && IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE)) { if (!zynqmp_pm_is_function_supported(PM_IOCTL, IOCTL_SET_GEM_CONFIG)) { ret = ofnode_read_u32_array(dev_ofnode(dev), diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c index 47b6e6e5bcf..f0dfe631490 100644 --- a/drivers/pci/pci_rom.c +++ b/drivers/pci/pci_rom.c @@ -325,7 +325,7 @@ err: return ret; } -int vesa_setup_video_priv(struct vesa_mode_info *vesa, +int vesa_setup_video_priv(struct vesa_mode_info *vesa, u64 fb, struct video_priv *uc_priv, struct video_uc_plat *plat) { @@ -348,9 +348,9 @@ int vesa_setup_video_priv(struct vesa_mode_info *vesa, /* Use double buffering if enabled */ if (IS_ENABLED(CONFIG_VIDEO_COPY) && plat->base) - plat->copy_base = vesa->phys_base_ptr; + plat->copy_base = fb; else - plat->base = vesa->phys_base_ptr; + plat->base = fb; log_debug("base = %lx, copy_base = %lx\n", plat->base, plat->copy_base); plat->size = vesa->bytes_per_scanline * vesa->y_resolution; @@ -377,7 +377,9 @@ int vesa_setup_video(struct udevice *dev, int (*int15_handler)(void)) return ret; } - ret = vesa_setup_video_priv(&mode_info.vesa, uc_priv, plat); + ret = vesa_setup_video_priv(&mode_info.vesa, + mode_info.vesa.phys_base_ptr, uc_priv, + plat); if (ret) { if (ret == -ENFILE) { /* diff --git a/drivers/pci/pcie_apple.c b/drivers/pci/pcie_apple.c index 9b08e1e5da8..b934fdbc35c 100644 --- a/drivers/pci/pcie_apple.c +++ b/drivers/pci/pcie_apple.c @@ -315,6 +315,8 @@ static int apple_pcie_probe(struct udevice *dev) for (of_port = ofnode_first_subnode(dev_ofnode(dev)); ofnode_valid(of_port); of_port = ofnode_next_subnode(of_port)) { + if (!ofnode_is_enabled(of_port)) + continue; ret = apple_pcie_setup_port(pcie, of_port); if (ret) { dev_err(pcie->dev, "Port %d setup fail: %d\n", i, ret); diff --git a/drivers/phy/phy-mtk-tphy.c b/drivers/phy/phy-mtk-tphy.c index 2dd964f7b20..1883f9f83e4 100644 --- a/drivers/phy/phy-mtk-tphy.c +++ b/drivers/phy/phy-mtk-tphy.c @@ -14,6 +14,7 @@ #include <asm/io.h> #include <dm/device_compat.h> #include <dm/devres.h> +#include <linux/bitfield.h> #include <linux/bitops.h> #include <linux/delay.h> @@ -43,19 +44,21 @@ #define U3P_USBPHYACR0 0x000 #define PA0_RG_U2PLL_FORCE_ON BIT(15) +#define PA0_USB20_PLL_PREDIV GENMASK(7, 6) #define PA0_RG_USB20_INTR_EN BIT(5) +#define U3P_USBPHYACR2 0x008 +#define PA2_RG_U2PLL_BW GENMASK(21, 19) + #define U3P_USBPHYACR5 0x014 #define PA5_RG_U2_HSTX_SRCAL_EN BIT(15) #define PA5_RG_U2_HSTX_SRCTRL GENMASK(14, 12) -#define PA5_RG_U2_HSTX_SRCTRL_VAL(x) ((0x7 & (x)) << 12) #define PA5_RG_U2_HS_100U_U3_EN BIT(11) #define U3P_USBPHYACR6 0x018 #define PA6_RG_U2_BC11_SW_EN BIT(23) #define PA6_RG_U2_OTG_VBUSCMP_EN BIT(20) #define PA6_RG_U2_SQTH GENMASK(3, 0) -#define PA6_RG_U2_SQTH_VAL(x) (0xf & (x)) #define U3P_U2PHYACR4 0x020 #define P2C_RG_USB20_GPIO_CTL BIT(9) @@ -63,6 +66,14 @@ #define P2C_U2_GPIO_CTR_MSK \ (P2C_RG_USB20_GPIO_CTL | P2C_USB20_GPIO_MODE) +#define U3P_U2PHYA_RESV 0x030 +#define P2R_RG_U2PLL_FBDIV_26M 0x1bb13b +#define P2R_RG_U2PLL_FBDIV_48M 0x3c0000 + +#define U3P_U2PHYA_RESV1 0x044 +#define P2R_RG_U2PLL_REFCLK_SEL BIT(5) +#define P2R_RG_U2PLL_FRA_EN BIT(3) + #define U3P_U2PHYDTM0 0x068 #define P2C_FORCE_UART_EN BIT(26) #define P2C_FORCE_DATAIN BIT(23) @@ -72,11 +83,9 @@ #define P2C_FORCE_SUSPENDM BIT(18) #define P2C_FORCE_TERMSEL BIT(17) #define P2C_RG_DATAIN GENMASK(13, 10) -#define P2C_RG_DATAIN_VAL(x) ((0xf & (x)) << 10) #define P2C_RG_DMPULLDOWN BIT(7) #define P2C_RG_DPPULLDOWN BIT(6) #define P2C_RG_XCVRSEL GENMASK(5, 4) -#define P2C_RG_XCVRSEL_VAL(x) ((0x3 & (x)) << 4) #define P2C_RG_SUSPENDM BIT(3) #define P2C_RG_TERMSEL BIT(2) #define P2C_DTM0_PART_MASK \ @@ -104,72 +113,53 @@ #define U3P_U3_PHYA_REG0 0x000 #define P3A_RG_CLKDRV_OFF GENMASK(3, 2) -#define P3A_RG_CLKDRV_OFF_VAL(x) ((0x3 & (x)) << 2) #define U3P_U3_PHYA_REG1 0x004 #define P3A_RG_CLKDRV_AMP GENMASK(31, 29) -#define P3A_RG_CLKDRV_AMP_VAL(x) ((0x7 & (x)) << 29) #define U3P_U3_PHYA_REG6 0x018 #define P3A_RG_TX_EIDLE_CM GENMASK(31, 28) -#define P3A_RG_TX_EIDLE_CM_VAL(x) ((0xf & (x)) << 28) #define U3P_U3_PHYA_REG9 0x024 #define P3A_RG_RX_DAC_MUX GENMASK(5, 1) -#define P3A_RG_RX_DAC_MUX_VAL(x) ((0x1f & (x)) << 1) #define U3P_U3_PHYA_DA_REG0 0x100 #define P3A_RG_XTAL_EXT_PE2H GENMASK(17, 16) -#define P3A_RG_XTAL_EXT_PE2H_VAL(x) ((0x3 & (x)) << 16) #define P3A_RG_XTAL_EXT_PE1H GENMASK(13, 12) -#define P3A_RG_XTAL_EXT_PE1H_VAL(x) ((0x3 & (x)) << 12) #define P3A_RG_XTAL_EXT_EN_U3 GENMASK(11, 10) -#define P3A_RG_XTAL_EXT_EN_U3_VAL(x) ((0x3 & (x)) << 10) #define U3P_U3_PHYA_DA_REG4 0x108 #define P3A_RG_PLL_DIVEN_PE2H GENMASK(21, 19) #define P3A_RG_PLL_BC_PE2H GENMASK(7, 6) -#define P3A_RG_PLL_BC_PE2H_VAL(x) ((0x3 & (x)) << 6) #define U3P_U3_PHYA_DA_REG5 0x10c #define P3A_RG_PLL_BR_PE2H GENMASK(29, 28) -#define P3A_RG_PLL_BR_PE2H_VAL(x) ((0x3 & (x)) << 28) #define P3A_RG_PLL_IC_PE2H GENMASK(15, 12) -#define P3A_RG_PLL_IC_PE2H_VAL(x) ((0xf & (x)) << 12) #define U3P_U3_PHYA_DA_REG6 0x110 #define P3A_RG_PLL_IR_PE2H GENMASK(19, 16) -#define P3A_RG_PLL_IR_PE2H_VAL(x) ((0xf & (x)) << 16) #define U3P_U3_PHYA_DA_REG7 0x114 #define P3A_RG_PLL_BP_PE2H GENMASK(19, 16) -#define P3A_RG_PLL_BP_PE2H_VAL(x) ((0xf & (x)) << 16) #define U3P_U3_PHYA_DA_REG20 0x13c #define P3A_RG_PLL_DELTA1_PE2H GENMASK(31, 16) -#define P3A_RG_PLL_DELTA1_PE2H_VAL(x) ((0xffff & (x)) << 16) #define U3P_U3_PHYA_DA_REG25 0x148 #define P3A_RG_PLL_DELTA_PE2H GENMASK(15, 0) -#define P3A_RG_PLL_DELTA_PE2H_VAL(x) (0xffff & (x)) #define U3P_U3_PHYD_LFPS1 0x00c #define P3D_RG_FWAKE_TH GENMASK(21, 16) -#define P3D_RG_FWAKE_TH_VAL(x) ((0x3f & (x)) << 16) #define U3P_U3_PHYD_CDR1 0x05c #define P3D_RG_CDR_BIR_LTD1 GENMASK(28, 24) -#define P3D_RG_CDR_BIR_LTD1_VAL(x) ((0x1f & (x)) << 24) #define P3D_RG_CDR_BIR_LTD0 GENMASK(12, 8) -#define P3D_RG_CDR_BIR_LTD0_VAL(x) ((0x1f & (x)) << 8) #define U3P_U3_PHYD_RXDET1 0x128 #define P3D_RG_RXDET_STB2_SET GENMASK(17, 9) -#define P3D_RG_RXDET_STB2_SET_VAL(x) ((0x1ff & (x)) << 9) #define U3P_U3_PHYD_RXDET2 0x12c #define P3D_RG_RXDET_STB2_SET_P3 GENMASK(8, 0) -#define P3D_RG_RXDET_STB2_SET_P3_VAL(x) (0x1ff & (x)) #define U3P_SPLLC_XTALCTL3 0x018 #define XC3_RG_U3_XTAL_RX_PWD BIT(9) @@ -179,66 +169,62 @@ #define PHYD_CTRL_SIGNAL_MODE4 0x1c /* CDR Charge Pump P-path current adjustment */ #define RG_CDR_BICLTD1_GEN1_MSK GENMASK(23, 20) -#define RG_CDR_BICLTD1_GEN1_VAL(x) ((0xf & (x)) << 20) #define RG_CDR_BICLTD0_GEN1_MSK GENMASK(11, 8) -#define RG_CDR_BICLTD0_GEN1_VAL(x) ((0xf & (x)) << 8) #define PHYD_DESIGN_OPTION2 0x24 /* Symbol lock count selection */ #define RG_LOCK_CNT_SEL_MSK GENMASK(5, 4) -#define RG_LOCK_CNT_SEL_VAL(x) ((0x3 & (x)) << 4) #define PHYD_DESIGN_OPTION9 0x40 /* COMWAK GAP width window */ #define RG_TG_MAX_MSK GENMASK(20, 16) -#define RG_TG_MAX_VAL(x) ((0x1f & (x)) << 16) /* COMINIT GAP width window */ #define RG_T2_MAX_MSK GENMASK(13, 8) -#define RG_T2_MAX_VAL(x) ((0x3f & (x)) << 8) /* COMWAK GAP width window */ #define RG_TG_MIN_MSK GENMASK(7, 5) -#define RG_TG_MIN_VAL(x) ((0x7 & (x)) << 5) /* COMINIT GAP width window */ #define RG_T2_MIN_MSK GENMASK(4, 0) -#define RG_T2_MIN_VAL(x) (0x1f & (x)) #define ANA_RG_CTRL_SIGNAL1 0x4c /* TX driver tail current control for 0dB de-empahsis mdoe for Gen1 speed */ #define RG_IDRV_0DB_GEN1_MSK GENMASK(13, 8) -#define RG_IDRV_0DB_GEN1_VAL(x) ((0x3f & (x)) << 8) #define ANA_RG_CTRL_SIGNAL4 0x58 #define RG_CDR_BICLTR_GEN1_MSK GENMASK(23, 20) -#define RG_CDR_BICLTR_GEN1_VAL(x) ((0xf & (x)) << 20) /* Loop filter R1 resistance adjustment for Gen1 speed */ #define RG_CDR_BR_GEN2_MSK GENMASK(10, 8) -#define RG_CDR_BR_GEN2_VAL(x) ((0x7 & (x)) << 8) #define ANA_RG_CTRL_SIGNAL6 0x60 /* I-path capacitance adjustment for Gen1 */ #define RG_CDR_BC_GEN1_MSK GENMASK(28, 24) -#define RG_CDR_BC_GEN1_VAL(x) ((0x1f & (x)) << 24) #define RG_CDR_BIRLTR_GEN1_MSK GENMASK(4, 0) -#define RG_CDR_BIRLTR_GEN1_VAL(x) (0x1f & (x)) #define ANA_EQ_EYE_CTRL_SIGNAL1 0x6c /* RX Gen1 LEQ tuning step */ #define RG_EQ_DLEQ_LFI_GEN1_MSK GENMASK(11, 8) -#define RG_EQ_DLEQ_LFI_GEN1_VAL(x) ((0xf & (x)) << 8) #define ANA_EQ_EYE_CTRL_SIGNAL4 0xd8 #define RG_CDR_BIRLTD0_GEN1_MSK GENMASK(20, 16) -#define RG_CDR_BIRLTD0_GEN1_VAL(x) ((0x1f & (x)) << 16) #define ANA_EQ_EYE_CTRL_SIGNAL5 0xdc #define RG_CDR_BIRLTD0_GEN3_MSK GENMASK(4, 0) -#define RG_CDR_BIRLTD0_GEN3_VAL(x) (0x1f & (x)) enum mtk_phy_version { MTK_TPHY_V1 = 1, MTK_TPHY_V2, }; +struct tphy_pdata { + enum mtk_phy_version version; + + /* + * workaround only for mt8195: + * u2phy should use integer mode instead of fractional mode of + * 48M PLL, fix it by switching PLL to 26M from default 48M + */ + bool sw_pll_48m_to_26m; +}; + struct u2phy_banks { void __iomem *misc; void __iomem *fmreg; @@ -269,11 +255,32 @@ struct mtk_phy_instance { struct mtk_tphy { struct udevice *dev; void __iomem *sif_base; - enum mtk_phy_version version; + const struct tphy_pdata *pdata; struct mtk_phy_instance **phys; int nphys; }; +/* workaround only for mt8195 */ +static void u2_phy_pll_26m_set(struct mtk_tphy *tphy, + struct mtk_phy_instance *instance) +{ + struct u2phy_banks *u2_banks = &instance->u2_banks; + + if (!tphy->pdata->sw_pll_48m_to_26m) + return; + + clrsetbits_le32(u2_banks->com + U3P_USBPHYACR0, PA0_USB20_PLL_PREDIV, + FIELD_PREP(PA0_USB20_PLL_PREDIV, 0)); + + clrsetbits_le32(u2_banks->com + U3P_USBPHYACR2, PA2_RG_U2PLL_BW, + FIELD_PREP(PA2_RG_U2PLL_BW, 3)); + + writel(P2R_RG_U2PLL_FBDIV_26M, u2_banks->com + U3P_U2PHYA_RESV); + + setbits_le32(u2_banks->com + U3P_U2PHYA_RESV1, + P2R_RG_U2PLL_FRA_EN | P2R_RG_U2PLL_REFCLK_SEL); +} + static void u2_phy_instance_init(struct mtk_tphy *tphy, struct mtk_phy_instance *instance) { @@ -282,7 +289,8 @@ static void u2_phy_instance_init(struct mtk_tphy *tphy, /* switch to USB function, and enable usb pll */ clrsetbits_le32(u2_banks->com + U3P_U2PHYDTM0, P2C_FORCE_UART_EN | P2C_FORCE_SUSPENDM, - P2C_RG_XCVRSEL_VAL(1) | P2C_RG_DATAIN_VAL(0)); + FIELD_PREP(P2C_RG_XCVRSEL, 1) | + FIELD_PREP(P2C_RG_DATAIN, 0)); clrbits_le32(u2_banks->com + U3P_U2PHYDTM1, P2C_RG_UART_EN); setbits_le32(u2_banks->com + U3P_USBPHYACR0, PA0_RG_USB20_INTR_EN); @@ -295,11 +303,14 @@ static void u2_phy_instance_init(struct mtk_tphy *tphy, /* DP/DM BC1.1 path Disable */ clrsetbits_le32(u2_banks->com + U3P_USBPHYACR6, PA6_RG_U2_BC11_SW_EN | PA6_RG_U2_SQTH, - PA6_RG_U2_SQTH_VAL(2)); + FIELD_PREP(PA6_RG_U2_SQTH, 2)); /* set HS slew rate */ clrsetbits_le32(u2_banks->com + U3P_USBPHYACR5, - PA5_RG_U2_HSTX_SRCTRL, PA5_RG_U2_HSTX_SRCTRL_VAL(4)); + PA5_RG_U2_HSTX_SRCTRL, + FIELD_PREP(PA5_RG_U2_HSTX_SRCTRL, 4)); + + u2_phy_pll_26m_set(tphy, instance); dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index); } @@ -351,28 +362,31 @@ static void u3_phy_instance_init(struct mtk_tphy *tphy, /* gating XSQ */ clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG0, - P3A_RG_XTAL_EXT_EN_U3, P3A_RG_XTAL_EXT_EN_U3_VAL(2)); + P3A_RG_XTAL_EXT_EN_U3, + FIELD_PREP(P3A_RG_XTAL_EXT_EN_U3, 2)); clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_REG9, - P3A_RG_RX_DAC_MUX, P3A_RG_RX_DAC_MUX_VAL(4)); + P3A_RG_RX_DAC_MUX, FIELD_PREP(P3A_RG_RX_DAC_MUX, 4)); clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_REG6, - P3A_RG_TX_EIDLE_CM, P3A_RG_TX_EIDLE_CM_VAL(0xe)); + P3A_RG_TX_EIDLE_CM, + FIELD_PREP(P3A_RG_TX_EIDLE_CM, 0xe)); clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_CDR1, P3D_RG_CDR_BIR_LTD0 | P3D_RG_CDR_BIR_LTD1, - P3D_RG_CDR_BIR_LTD0_VAL(0xc) | - P3D_RG_CDR_BIR_LTD1_VAL(0x3)); + FIELD_PREP(P3D_RG_CDR_BIR_LTD0, 0xc) | + FIELD_PREP(P3D_RG_CDR_BIR_LTD1, 0x3)); clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_LFPS1, - P3D_RG_FWAKE_TH, P3D_RG_FWAKE_TH_VAL(0x34)); + P3D_RG_FWAKE_TH, FIELD_PREP(P3D_RG_FWAKE_TH, 0x34)); clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_RXDET1, - P3D_RG_RXDET_STB2_SET, P3D_RG_RXDET_STB2_SET_VAL(0x10)); + P3D_RG_RXDET_STB2_SET, + FIELD_PREP(P3D_RG_RXDET_STB2_SET, 0x10)); clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_RXDET2, P3D_RG_RXDET_STB2_SET_P3, - P3D_RG_RXDET_STB2_SET_P3_VAL(0x10)); + FIELD_PREP(P3D_RG_RXDET_STB2_SET_P3, 0x10)); dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index); } @@ -382,50 +396,52 @@ static void pcie_phy_instance_init(struct mtk_tphy *tphy, { struct u3phy_banks *u3_banks = &instance->u3_banks; - if (tphy->version != MTK_TPHY_V1) + if (tphy->pdata->version != MTK_TPHY_V1) return; clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG0, P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H, - P3A_RG_XTAL_EXT_PE1H_VAL(0x2) | - P3A_RG_XTAL_EXT_PE2H_VAL(0x2)); + FIELD_PREP(P3A_RG_XTAL_EXT_PE1H, 0x2) | + FIELD_PREP(P3A_RG_XTAL_EXT_PE2H, 0x2)); /* ref clk drive */ clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_REG1, P3A_RG_CLKDRV_AMP, - P3A_RG_CLKDRV_AMP_VAL(0x4)); + FIELD_PREP(P3A_RG_CLKDRV_AMP, 0x4)); clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_REG0, P3A_RG_CLKDRV_OFF, - P3A_RG_CLKDRV_OFF_VAL(0x1)); + FIELD_PREP(P3A_RG_CLKDRV_OFF, 0x1)); /* SSC delta -5000ppm */ clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG20, P3A_RG_PLL_DELTA1_PE2H, - P3A_RG_PLL_DELTA1_PE2H_VAL(0x3c)); + FIELD_PREP(P3A_RG_PLL_DELTA1_PE2H, 0x3c)); clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG25, P3A_RG_PLL_DELTA_PE2H, - P3A_RG_PLL_DELTA_PE2H_VAL(0x36)); + FIELD_PREP(P3A_RG_PLL_DELTA_PE2H, 0x36)); /* change pll BW 0.6M */ clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG5, P3A_RG_PLL_BR_PE2H | P3A_RG_PLL_IC_PE2H, - P3A_RG_PLL_BR_PE2H_VAL(0x1) | - P3A_RG_PLL_IC_PE2H_VAL(0x1)); + FIELD_PREP(P3A_RG_PLL_BR_PE2H, 0x1) | + FIELD_PREP(P3A_RG_PLL_IC_PE2H, 0x1)); clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG4, P3A_RG_PLL_DIVEN_PE2H | P3A_RG_PLL_BC_PE2H, - P3A_RG_PLL_BC_PE2H_VAL(0x3)); + FIELD_PREP(P3A_RG_PLL_BC_PE2H, 0x3)); clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG6, - P3A_RG_PLL_IR_PE2H, P3A_RG_PLL_IR_PE2H_VAL(0x2)); + P3A_RG_PLL_IR_PE2H, + FIELD_PREP(P3A_RG_PLL_IR_PE2H, 0x2)); clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG7, - P3A_RG_PLL_BP_PE2H, P3A_RG_PLL_BP_PE2H_VAL(0xa)); + P3A_RG_PLL_BP_PE2H, + FIELD_PREP(P3A_RG_PLL_BP_PE2H, 0xa)); /* Tx Detect Rx Timing: 10us -> 5us */ clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_RXDET1, P3D_RG_RXDET_STB2_SET, - P3D_RG_RXDET_STB2_SET_VAL(0x10)); + FIELD_PREP(P3D_RG_RXDET_STB2_SET, 0x10)); clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_RXDET2, P3D_RG_RXDET_STB2_SET_P3, - P3D_RG_RXDET_STB2_SET_P3_VAL(0x10)); + FIELD_PREP(P3D_RG_RXDET_STB2_SET_P3, 0x10)); /* wait for PCIe subsys register to active */ udelay(3000); @@ -438,36 +454,38 @@ static void sata_phy_instance_init(struct mtk_tphy *tphy, clrsetbits_le32(u3_banks->phyd + ANA_RG_CTRL_SIGNAL6, RG_CDR_BIRLTR_GEN1_MSK | RG_CDR_BC_GEN1_MSK, - RG_CDR_BIRLTR_GEN1_VAL(0x6) | - RG_CDR_BC_GEN1_VAL(0x1a)); + FIELD_PREP(RG_CDR_BIRLTR_GEN1_MSK, 0x6) | + FIELD_PREP(RG_CDR_BC_GEN1_MSK, 0x1a)); clrsetbits_le32(u3_banks->phyd + ANA_EQ_EYE_CTRL_SIGNAL4, RG_CDR_BIRLTD0_GEN1_MSK, - RG_CDR_BIRLTD0_GEN1_VAL(0x18)); + FIELD_PREP(RG_CDR_BIRLTD0_GEN1_MSK, 0x18)); clrsetbits_le32(u3_banks->phyd + ANA_EQ_EYE_CTRL_SIGNAL5, RG_CDR_BIRLTD0_GEN3_MSK, - RG_CDR_BIRLTD0_GEN3_VAL(0x06)); + FIELD_PREP(RG_CDR_BIRLTD0_GEN3_MSK, 0x06)); clrsetbits_le32(u3_banks->phyd + ANA_RG_CTRL_SIGNAL4, RG_CDR_BICLTR_GEN1_MSK | RG_CDR_BR_GEN2_MSK, - RG_CDR_BICLTR_GEN1_VAL(0x0c) | - RG_CDR_BR_GEN2_VAL(0x07)); + FIELD_PREP(RG_CDR_BICLTR_GEN1_MSK, 0x0c) | + FIELD_PREP(RG_CDR_BR_GEN2_MSK, 0x07)); clrsetbits_le32(u3_banks->phyd + PHYD_CTRL_SIGNAL_MODE4, RG_CDR_BICLTD0_GEN1_MSK | RG_CDR_BICLTD1_GEN1_MSK, - RG_CDR_BICLTD0_GEN1_VAL(0x08) | - RG_CDR_BICLTD1_GEN1_VAL(0x02)); + FIELD_PREP(RG_CDR_BICLTD0_GEN1_MSK, 0x08) | + FIELD_PREP(RG_CDR_BICLTD1_GEN1_MSK, 0x02)); clrsetbits_le32(u3_banks->phyd + PHYD_DESIGN_OPTION2, RG_LOCK_CNT_SEL_MSK, - RG_LOCK_CNT_SEL_VAL(0x02)); + FIELD_PREP(RG_LOCK_CNT_SEL_MSK, 0x02)); clrsetbits_le32(u3_banks->phyd + PHYD_DESIGN_OPTION9, RG_T2_MIN_MSK | RG_TG_MIN_MSK | RG_T2_MAX_MSK | RG_TG_MAX_MSK, - RG_T2_MIN_VAL(0x12) | RG_TG_MIN_VAL(0x04) | - RG_T2_MAX_VAL(0x31) | RG_TG_MAX_VAL(0x0e)); + FIELD_PREP(RG_T2_MIN_MSK, 0x12) | + FIELD_PREP(RG_TG_MIN_MSK, 0x04) | + FIELD_PREP(RG_T2_MAX_MSK, 0x31) | + FIELD_PREP(RG_TG_MAX_MSK, 0x0e)); clrsetbits_le32(u3_banks->phyd + ANA_RG_CTRL_SIGNAL1, RG_IDRV_0DB_GEN1_MSK, - RG_IDRV_0DB_GEN1_VAL(0x20)); + FIELD_PREP(RG_IDRV_0DB_GEN1_MSK, 0x20)); clrsetbits_le32(u3_banks->phyd + ANA_EQ_EYE_CTRL_SIGNAL1, RG_EQ_DLEQ_LFI_GEN1_MSK, - RG_EQ_DLEQ_LFI_GEN1_VAL(0x03)); + FIELD_PREP(RG_EQ_DLEQ_LFI_GEN1_MSK, 0x03)); } static void pcie_phy_instance_power_on(struct mtk_tphy *tphy, @@ -662,11 +680,14 @@ static int mtk_phy_xlate(struct phy *phy, return -EINVAL; } - if (tphy->version == MTK_TPHY_V1) { + switch (tphy->pdata->version) { + case MTK_TPHY_V1: phy_v1_banks_init(tphy, instance); - } else if (tphy->version == MTK_TPHY_V2) { + break; + case MTK_TPHY_V2: phy_v2_banks_init(tphy, instance); - } else { + break; + default: dev_err(phy->dev, "phy version is not supported\n"); return -EINVAL; } @@ -696,13 +717,12 @@ static int mtk_tphy_probe(struct udevice *dev) return -ENOMEM; tphy->dev = dev; - tphy->version = dev_get_driver_data(dev); + tphy->pdata = (void *)dev_get_driver_data(dev); /* v1 has shared banks for usb/pcie mode, */ /* but not for sata mode */ - if (tphy->version == MTK_TPHY_V1) { + if (tphy->pdata->version == MTK_TPHY_V1) tphy->sif_base = dev_read_addr_ptr(dev); - } dev_for_each_subnode(subnode, dev) { struct mtk_phy_instance *instance; @@ -737,9 +757,32 @@ static int mtk_tphy_probe(struct udevice *dev) return 0; } +static struct tphy_pdata tphy_v1_pdata = { + .version = MTK_TPHY_V1, +}; + +static struct tphy_pdata tphy_v2_pdata = { + .version = MTK_TPHY_V2, +}; + +static struct tphy_pdata mt8195_pdata = { + .version = MTK_TPHY_V2, + .sw_pll_48m_to_26m = true, +}; + static const struct udevice_id mtk_tphy_id_table[] = { - { .compatible = "mediatek,generic-tphy-v1", .data = MTK_TPHY_V1, }, - { .compatible = "mediatek,generic-tphy-v2", .data = MTK_TPHY_V2, }, + { + .compatible = "mediatek,generic-tphy-v1", + .data = (ulong)&tphy_v1_pdata, + }, + { + .compatible = "mediatek,generic-tphy-v2", + .data = (ulong)&tphy_v2_pdata, + }, + { + .compatible = "mediatek,mt8195-tphy", + .data = (ulong)&mt8195_pdata, + }, { } }; diff --git a/drivers/phy/socionext/Kconfig b/drivers/phy/socionext/Kconfig index bcd579e98ec..de87d5b0109 100644 --- a/drivers/phy/socionext/Kconfig +++ b/drivers/phy/socionext/Kconfig @@ -10,3 +10,11 @@ config PHY_UNIPHIER_PCIE help Enable this to support PHY implemented in PCIe controller on UniPhier SoCs. + +config PHY_UNIPHIER_USB3 + bool "UniPhier USB3 PHY driver" + depends on PHY && ARCH_UNIPHIER + imply REGMAP + help + Enable this to support PHY implemented in USB3 controller + on UniPhier SoCs. diff --git a/drivers/phy/socionext/Makefile b/drivers/phy/socionext/Makefile index 5484360b70f..94d3aa68cfa 100644 --- a/drivers/phy/socionext/Makefile +++ b/drivers/phy/socionext/Makefile @@ -4,3 +4,4 @@ # obj-$(CONFIG_PHY_UNIPHIER_PCIE) += phy-uniphier-pcie.o +obj-$(CONFIG_PHY_UNIPHIER_USB3) += phy-uniphier-usb3.o diff --git a/drivers/phy/socionext/phy-uniphier-usb3.c b/drivers/phy/socionext/phy-uniphier-usb3.c new file mode 100644 index 00000000000..1d65b0b08f7 --- /dev/null +++ b/drivers/phy/socionext/phy-uniphier-usb3.c @@ -0,0 +1,168 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * phy_uniphier_usb3.c - Socionext UniPhier Usb3 PHY driver + * Copyright 2019-2023 Socionext, Inc. + */ + +#include <common.h> +#include <dm.h> +#include <generic-phy.h> + +#include <clk.h> +#include <reset.h> + +struct uniphier_usb3phy_priv { + struct clk *clk_link, *clk_phy, *clk_parent, *clk_phyext; + struct reset_ctl *rst_link, *rst_phy, *rst_parent; +}; + +static int uniphier_usb3phy_init(struct phy *phy) +{ + struct uniphier_usb3phy_priv *priv = dev_get_priv(phy->dev); + int ret; + + ret = clk_enable(priv->clk_phy); + if (ret) + return ret; + + ret = reset_deassert(priv->rst_phy); + if (ret) + goto out_clk; + + if (priv->clk_phyext) { + ret = clk_enable(priv->clk_phyext); + if (ret) + goto out_rst; + } + + return 0; + +out_rst: + reset_assert(priv->rst_phy); +out_clk: + clk_disable(priv->clk_phy); + + return ret; +} + +static int uniphier_usb3phy_exit(struct phy *phy) +{ + struct uniphier_usb3phy_priv *priv = dev_get_priv(phy->dev); + + if (priv->clk_phyext) + clk_disable(priv->clk_phyext); + + reset_assert(priv->rst_phy); + clk_disable(priv->clk_phy); + + return 0; +} + +static int uniphier_usb3phy_probe(struct udevice *dev) +{ + struct uniphier_usb3phy_priv *priv = dev_get_priv(dev); + int ret; + + priv->clk_link = devm_clk_get(dev, "link"); + if (IS_ERR(priv->clk_link)) { + printf("Failed to get link clock\n"); + return PTR_ERR(priv->clk_link); + } + + priv->clk_phy = devm_clk_get(dev, "phy"); + if (IS_ERR(priv->clk_link)) { + printf("Failed to get phy clock\n"); + return PTR_ERR(priv->clk_link); + } + + priv->clk_parent = devm_clk_get_optional(dev, "gio"); + if (IS_ERR(priv->clk_parent)) { + printf("Failed to get parent clock\n"); + return PTR_ERR(priv->clk_parent); + } + + priv->clk_phyext = devm_clk_get_optional(dev, "phy-ext"); + if (IS_ERR(priv->clk_phyext)) { + printf("Failed to get external phy clock\n"); + return PTR_ERR(priv->clk_phyext); + } + + priv->rst_link = devm_reset_control_get(dev, "link"); + if (IS_ERR(priv->rst_link)) { + printf("Failed to get link reset\n"); + return PTR_ERR(priv->rst_link); + } + + priv->rst_phy = devm_reset_control_get(dev, "phy"); + if (IS_ERR(priv->rst_phy)) { + printf("Failed to get phy reset\n"); + return PTR_ERR(priv->rst_phy); + } + + priv->rst_parent = devm_reset_control_get_optional(dev, "gio"); + if (IS_ERR(priv->rst_parent)) { + printf("Failed to get parent reset\n"); + return PTR_ERR(priv->rst_parent); + } + + if (priv->clk_parent) { + ret = clk_enable(priv->clk_parent); + if (ret) + return ret; + } + if (priv->rst_parent) { + ret = reset_deassert(priv->rst_parent); + if (ret) + goto out_clk_parent; + } + + ret = clk_enable(priv->clk_link); + if (ret) + goto out_rst_parent; + + ret = reset_deassert(priv->rst_link); + if (ret) + goto out_clk; + + return 0; + +out_clk: + clk_disable(priv->clk_link); +out_rst_parent: + if (priv->rst_parent) + reset_assert(priv->rst_parent); +out_clk_parent: + if (priv->clk_parent) + clk_disable(priv->clk_parent); + + return ret; +} + +static struct phy_ops uniphier_usb3phy_ops = { + .init = uniphier_usb3phy_init, + .exit = uniphier_usb3phy_exit, +}; + +static const struct udevice_id uniphier_usb3phy_ids[] = { + { .compatible = "socionext,uniphier-pro4-usb3-ssphy" }, + { .compatible = "socionext,uniphier-pro5-usb3-hsphy" }, + { .compatible = "socionext,uniphier-pro5-usb3-ssphy" }, + { .compatible = "socionext,uniphier-pxs2-usb3-hsphy" }, + { .compatible = "socionext,uniphier-pxs2-usb3-ssphy" }, + { .compatible = "socionext,uniphier-ld20-usb3-hsphy" }, + { .compatible = "socionext,uniphier-ld20-usb3-ssphy" }, + { .compatible = "socionext,uniphier-pxs3-usb3-hsphy" }, + { .compatible = "socionext,uniphier-pxs3-usb3-ssphy" }, + { .compatible = "socionext,uniphier-nx1-usb3-hsphy" }, + { .compatible = "socionext,uniphier-nx1-usb3-ssphy" }, + { } +}; + +U_BOOT_DRIVER(uniphier_usb3_phy) = { + .name = "uniphier-usb3-phy", + .id = UCLASS_PHY, + .of_match = uniphier_usb3phy_ids, + .ops = &uniphier_usb3phy_ops, + .probe = uniphier_usb3phy_probe, + .priv_auto = sizeof(struct uniphier_usb3phy_priv), +}; diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c index 6646b15d410..23397175d34 100644 --- a/drivers/phy/ti/phy-j721e-wiz.c +++ b/drivers/phy/ti/phy-j721e-wiz.c @@ -39,6 +39,7 @@ #define WIZ_DIV_NUM_CLOCKS_10G 1 #define WIZ_SERDES_TYPEC_LN10_SWAP BIT(30) +#define WIZ_SERDES_TYPEC_LN23_SWAP BIT(31) enum wiz_lane_standard_mode { LANE_MODE_GEN1, @@ -65,6 +66,14 @@ enum wiz_clock_input { WIZ_EXT_REFCLK1, }; +/* + * List of master lanes used for lane swapping + */ +enum wiz_typec_master_lane { + LANE0 = 0, + LANE2 = 2, +}; + static const struct reg_field por_en = REG_FIELD(WIZ_SERDES_CTRL, 31, 31); static const struct reg_field phy_reset_n = REG_FIELD(WIZ_SERDES_RST, 31, 31); static const struct reg_field pll1_refclk_mux_sel = @@ -329,6 +338,7 @@ struct wiz { u32 num_lanes; struct gpio_desc *gpio_typec_dir; u32 lane_phy_type[WIZ_MAX_LANES]; + u32 master_lane_num[WIZ_MAX_LANES]; struct clk *input_clks[WIZ_MAX_INPUT_CLOCKS]; unsigned int id; const struct wiz_data *data; @@ -586,14 +596,42 @@ static int wiz_reset_deassert(struct reset_ctl *reset_ctl) return ret; /* if typec-dir gpio was specified, set LN10 SWAP bit based on that */ - if (id == 0 && wiz->gpio_typec_dir) { - if (dm_gpio_get_value(wiz->gpio_typec_dir)) { - regmap_update_bits(wiz->regmap, WIZ_SERDES_TYPEC, - WIZ_SERDES_TYPEC_LN10_SWAP, - WIZ_SERDES_TYPEC_LN10_SWAP); - } else { - regmap_update_bits(wiz->regmap, WIZ_SERDES_TYPEC, - WIZ_SERDES_TYPEC_LN10_SWAP, 0); + if (id == 0) { + if (wiz->gpio_typec_dir) { + if (dm_gpio_get_value(wiz->gpio_typec_dir)) { + regmap_update_bits(wiz->regmap, WIZ_SERDES_TYPEC, + WIZ_SERDES_TYPEC_LN10_SWAP, + WIZ_SERDES_TYPEC_LN10_SWAP); + } else { + regmap_update_bits(wiz->regmap, WIZ_SERDES_TYPEC, + WIZ_SERDES_TYPEC_LN10_SWAP, 0); + } + } + } else { + /* if no typec-dir gpio was specified and PHY type is + * USB3 with master lane number is '0', set LN10 SWAP + * bit to '1' + */ + u32 num_lanes = wiz->num_lanes; + int i; + + for (i = 0; i < num_lanes; i++) { + if (wiz->lane_phy_type[i] == PHY_TYPE_USB3) { + switch (wiz->master_lane_num[i]) { + case LANE0: + regmap_update_bits(wiz->regmap, WIZ_SERDES_TYPEC, + WIZ_SERDES_TYPEC_LN10_SWAP, + WIZ_SERDES_TYPEC_LN10_SWAP); + break; + case LANE2: + regmap_update_bits(wiz->regmap, WIZ_SERDES_TYPEC, + WIZ_SERDES_TYPEC_LN23_SWAP, + WIZ_SERDES_TYPEC_LN23_SWAP); + break; + default: + break; + } + } } } @@ -1100,8 +1138,10 @@ static int wiz_get_lane_phy_types(struct udevice *dev, struct wiz *wiz) dev_dbg(dev, "%s: Lanes %u-%u have phy-type %u\n", __func__, reg, reg + num_lanes - 1, phy_type); - for (i = reg; i < reg + num_lanes; i++) + for (i = reg; i < reg + num_lanes; i++) { wiz->lane_phy_type[i] = phy_type; + wiz->master_lane_num[i] = reg; + } } return 0; diff --git a/drivers/pinctrl/pinctrl-uclass.c b/drivers/pinctrl/pinctrl-uclass.c index 8837726cc16..73dd7b1038b 100644 --- a/drivers/pinctrl/pinctrl-uclass.c +++ b/drivers/pinctrl/pinctrl-uclass.c @@ -169,34 +169,33 @@ pinctrl_gpio_get_pinctrl_and_offset(struct udevice *dev, unsigned offset, { struct ofnode_phandle_args args; unsigned gpio_offset, pfc_base, pfc_pins; - int ret; + int ret = 0; + int i = 0; - ret = dev_read_phandle_with_args(dev, "gpio-ranges", NULL, 3, - 0, &args); - if (ret) { - dev_dbg(dev, "%s: dev_read_phandle_with_args: err=%d\n", - __func__, ret); - return ret; - } + while (ret == 0) { + ret = dev_read_phandle_with_args(dev, "gpio-ranges", NULL, 3, + i++, &args); + if (ret) { + dev_dbg(dev, "%s: dev_read_phandle_with_args: err=%d\n", + __func__, ret); + return ret; + } - ret = uclass_get_device_by_ofnode(UCLASS_PINCTRL, - args.node, pctldev); - if (ret) { - dev_dbg(dev, - "%s: uclass_get_device_by_of_offset failed: err=%d\n", - __func__, ret); - return ret; - } + ret = uclass_get_device_by_ofnode(UCLASS_PINCTRL, + args.node, pctldev); + if (ret) { + dev_dbg(dev, + "%s: uclass_get_device_by_of_offset failed: err=%d\n", + __func__, ret); + return ret; + } - gpio_offset = args.args[0]; - pfc_base = args.args[1]; - pfc_pins = args.args[2]; + gpio_offset = args.args[0]; + pfc_base = args.args[1]; + pfc_pins = args.args[2]; - if (offset < gpio_offset || offset > gpio_offset + pfc_pins) { - dev_dbg(dev, - "%s: GPIO can not be mapped to pincontrol pin\n", - __func__); - return -EINVAL; + if (offset >= gpio_offset && offset <= gpio_offset + pfc_pins) + break; } offset -= gpio_offset; diff --git a/drivers/power/pmic/pca9450.c b/drivers/power/pmic/pca9450.c index 2427abfb7a5..e99ece8fb08 100644 --- a/drivers/power/pmic/pca9450.c +++ b/drivers/power/pmic/pca9450.c @@ -120,6 +120,7 @@ static const struct udevice_id pca9450_ids[] = { { .compatible = "nxp,pca9450a", .data = NXP_CHIP_TYPE_PCA9450A, }, { .compatible = "nxp,pca9450b", .data = NXP_CHIP_TYPE_PCA9450BC, }, { .compatible = "nxp,pca9450c", .data = NXP_CHIP_TYPE_PCA9450BC, }, + { .compatible = "nxp,pca9451a", .data = NXP_CHIP_TYPE_PCA9451A, }, { } }; diff --git a/drivers/power/regulator/pca9450.c b/drivers/power/regulator/pca9450.c index fe1869397cd..7ca20d1f7f8 100644 --- a/drivers/power/regulator/pca9450.c +++ b/drivers/power/regulator/pca9450.c @@ -276,7 +276,8 @@ static int pca9450_regulator_probe(struct udevice *dev) type = dev_get_driver_data(dev_get_parent(dev)); - if (type != NXP_CHIP_TYPE_PCA9450A && type != NXP_CHIP_TYPE_PCA9450BC) { + if (type != NXP_CHIP_TYPE_PCA9450A && type != NXP_CHIP_TYPE_PCA9450BC && + type != NXP_CHIP_TYPE_PCA9451A) { debug("Unknown PMIC type\n"); return -EINVAL; } @@ -291,6 +292,14 @@ static int pca9450_regulator_probe(struct udevice *dev) continue; } + /* PCA9451A uses BUCK3 in dual-phase and don't have LDO2 and LDO3 */ + if (type == NXP_CHIP_TYPE_PCA9451A && + (!strcmp(pca9450_reg_data[i].name, "BUCK3") || + !strcmp(pca9450_reg_data[i].name, "LDO2") || + !strcmp(pca9450_reg_data[i].name, "LDO3"))) { + continue; + } + *plat = pca9450_reg_data[i]; return 0; diff --git a/drivers/ram/aspeed/sdram_ast2600.c b/drivers/ram/aspeed/sdram_ast2600.c index 18767554123..d463933363e 100644 --- a/drivers/ram/aspeed/sdram_ast2600.c +++ b/drivers/ram/aspeed/sdram_ast2600.c @@ -1089,13 +1089,13 @@ static int ast2600_sdrammc_probe(struct udevice *dev) } reg = readl(&priv->scu->mpll); - reg &= ~(SCU_PLL_BYPASS | SCU_PLL_DIV_MASK | + reg &= ~(SCU_PLL_BYPASS | SCU_PLL_OFF | SCU_PLL_DIV_MASK | SCU_PLL_DENUM_MASK | SCU_PLL_NUM_MASK); - reg |= (SCU_PLL_RST | SCU_PLL_OFF | SCU_MPLL_FREQ_CFG); + reg |= (SCU_PLL_RST | SCU_MPLL_FREQ_CFG); writel(reg, &priv->scu->mpll); writel(SCU_MPLL_EXT_CFG, &priv->scu->mpll_ext); udelay(100); - reg &= ~(SCU_PLL_RST | SCU_PLL_OFF); + reg &= ~SCU_PLL_RST; writel(reg, &priv->scu->mpll); while ((readl(&priv->scu->mpll_ext) & BIT(31)) == 0) diff --git a/drivers/reset/reset-uniphier.c b/drivers/reset/reset-uniphier.c index 7adae51873f..35e3ccebd72 100644 --- a/drivers/reset/reset-uniphier.c +++ b/drivers/reset/reset-uniphier.c @@ -2,6 +2,7 @@ /* * Copyright (C) 2016 Socionext Inc. * Author: Masahiro Yamada <yamada.masahiro@socionext.com> + * Author: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> */ #include <common.h> @@ -9,6 +10,8 @@ #include <log.h> #include <malloc.h> #include <reset-uclass.h> +#include <clk.h> +#include <reset.h> #include <dm/device_compat.h> #include <linux/bitops.h> #include <linux/io.h> @@ -178,10 +181,17 @@ static const struct uniphier_reset_data uniphier_pro4_peri_reset_data[] = { UNIPHIER_RESET_END, }; +/* Glue reset data */ +static const struct uniphier_reset_data uniphier_pro4_usb3_reset_data[] = { + UNIPHIER_RESETX(15, 0, 15) +}; + /* core implementaton */ struct uniphier_reset_priv { void __iomem *base; const struct uniphier_reset_data *data; + struct clk_bulk clks; + struct reset_ctl_bulk rsts; }; static int uniphier_reset_update(struct reset_ctl *reset_ctl, int assert) @@ -233,10 +243,47 @@ static const struct reset_ops uniphier_reset_ops = { .rst_deassert = uniphier_reset_deassert, }; +static int uniphier_reset_rst_init(struct udevice *dev) +{ + struct uniphier_reset_priv *priv = dev_get_priv(dev); + int ret; + + ret = reset_get_bulk(dev, &priv->rsts); + if (ret == -ENOSYS || ret == -ENOENT) + return 0; + else if (ret) + return ret; + + ret = reset_deassert_bulk(&priv->rsts); + if (ret) + reset_release_bulk(&priv->rsts); + + return ret; +} + +static int uniphier_reset_clk_init(struct udevice *dev) +{ + struct uniphier_reset_priv *priv = dev_get_priv(dev); + int ret; + + ret = clk_get_bulk(dev, &priv->clks); + if (ret == -ENOSYS || ret == -ENOENT) + return 0; + if (ret) + return ret; + + ret = clk_enable_bulk(&priv->clks); + if (ret) + clk_release_bulk(&priv->clks); + + return ret; +} + static int uniphier_reset_probe(struct udevice *dev) { struct uniphier_reset_priv *priv = dev_get_priv(dev); fdt_addr_t addr; + int ret; addr = dev_read_addr(dev->parent); if (addr == FDT_ADDR_T_NONE) @@ -248,7 +295,11 @@ static int uniphier_reset_probe(struct udevice *dev) priv->data = (void *)dev_get_driver_data(dev); - return 0; + ret = uniphier_reset_clk_init(dev); + if (ret) + return ret; + + return uniphier_reset_rst_init(dev); } static const struct udevice_id uniphier_reset_match[] = { @@ -355,6 +406,31 @@ static const struct udevice_id uniphier_reset_match[] = { .compatible = "socionext,uniphier-pxs3-peri-reset", .data = (ulong)uniphier_pro4_peri_reset_data, }, + /* USB glue reset */ + { + .compatible = "socionext,uniphier-pro4-usb3-reset", + .data = (ulong)uniphier_pro4_usb3_reset_data, + }, + { + .compatible = "socionext,uniphier-pro5-usb3-reset", + .data = (ulong)uniphier_pro4_usb3_reset_data, + }, + { + .compatible = "socionext,uniphier-pxs2-usb3-reset", + .data = (ulong)uniphier_pro4_usb3_reset_data, + }, + { + .compatible = "socionext,uniphier-ld20-usb3-reset", + .data = (ulong)uniphier_pro4_usb3_reset_data, + }, + { + .compatible = "socionext,uniphier-pxs3-usb3-reset", + .data = (ulong)uniphier_pro4_usb3_reset_data, + }, + { + .compatible = "socionext,uniphier-nx1-usb3-reset", + .data = (ulong)uniphier_pro4_usb3_reset_data, + }, { /* sentinel */ } }; diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 35b6ed4d7c7..23173139e01 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -134,6 +134,19 @@ config RTC_ISL1208 This driver supports reading and writing the RTC/calendar and detects total power failures. +config RTC_MAX313XX + bool "Analog Devices MAX313XX RTC driver" + depends on DM_RTC + depends on DM_I2C + help + If you say yes here you will get support for the + Analog Devices MAX313XX series RTC family. + + Chip features not currently supported: + - Timestamp registers as SRAM + - Temperature sensor + - CLKOUT generation + config RTC_PCF8563 tristate "Philips PCF8563" help @@ -231,6 +244,24 @@ config RTC_M41T62 Enable driver for ST's M41T62 compatible RTC devices (like RV-4162). It is a serial (I2C) real-time clock (RTC) with alarm. +config RTC_SANDBOX + bool "Enable sandbox RTC driver" + depends on SANDBOX && DM_RTC + default y + help + Enable the sandbox RTC driver. This driver connects to the RTC + emulator and is used to test the RTC uclasses and associated code, + as well as the I2C subsystem. + +config SPL_RTC_SANDBOX + bool "Enable sandbox RTC driver (SPL)" + depends on SANDBOX && SPL_DM_RTC + default y + help + Enable the sandbox RTC driver. This driver connects to the RTC + emulator and is used to test the RTC uclasses and associated code, + as well as the I2C subsystem. + config RTC_STM32 bool "Enable STM32 RTC driver" depends on DM_RTC diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 447551e15aa..308fab8da9b 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -16,9 +16,10 @@ obj-$(CONFIG_RTC_DS3231) += ds3231.o obj-$(CONFIG_RTC_DS3232) += ds3232.o obj-$(CONFIG_RTC_EMULATION) += emul_rtc.o obj-$(CONFIG_RTC_HT1380) += ht1380.o -obj-$(CONFIG_SANDBOX) += i2c_rtc_emul.o +obj-$(CONFIG_$(SPL_TPL_)RTC_SANDBOX) += i2c_rtc_emul.o obj-$(CONFIG_RTC_ISL1208) += isl1208.o obj-$(CONFIG_RTC_M41T62) += m41t62.o +obj-$(CONFIG_RTC_MAX313XX) += max313xx.o obj-$(CONFIG_RTC_MC13XXX) += mc13xxx-rtc.o obj-$(CONFIG_RTC_MC146818) += mc146818.o obj-$(CONFIG_MCFRTC) += mcfrtc.o @@ -35,6 +36,6 @@ obj-$(CONFIG_RTC_RX8025) += rx8025.o obj-$(CONFIG_RTC_RX8010SJ) += rx8010sj.o obj-$(CONFIG_RTC_S35392A) += s35392a.o obj-$(CONFIG_RTC_STM32) += stm32_rtc.o -obj-$(CONFIG_SANDBOX) += sandbox_rtc.o +obj-$(CONFIG_$(SPL_TPL_)RTC_SANDBOX) += sandbox_rtc.o obj-$(CONFIG_RTC_ABX80X) += abx80x.o obj-$(CONFIG_RTC_ZYNQMP) += zynqmp_rtc.o diff --git a/drivers/rtc/m41t62.c b/drivers/rtc/m41t62.c index 66a0faa0ecf..891fe09d311 100644 --- a/drivers/rtc/m41t62.c +++ b/drivers/rtc/m41t62.c @@ -283,6 +283,16 @@ static int m41t62_rtc_reset(struct udevice *dev) return m41t62_sqw_enable(dev, true); } +static int m41t62_rtc_read8(struct udevice *dev, unsigned int reg) +{ + return dm_i2c_reg_read(dev, reg); +} + +static int m41t62_rtc_write8(struct udevice *dev, unsigned int reg, int val) +{ + return dm_i2c_reg_write(dev, reg, val); +} + /* * Make sure HT bit is cleared. This bit is set on entering battery backup * mode, so do this before the first read access. @@ -296,6 +306,8 @@ static const struct rtc_ops m41t62_rtc_ops = { .get = m41t62_rtc_get, .set = m41t62_rtc_set, .reset = m41t62_rtc_reset, + .read8 = m41t62_rtc_read8, + .write8 = m41t62_rtc_write8, }; static const struct udevice_id m41t62_rtc_ids[] = { diff --git a/drivers/rtc/max313xx.c b/drivers/rtc/max313xx.c new file mode 100644 index 00000000000..748f3c42c30 --- /dev/null +++ b/drivers/rtc/max313xx.c @@ -0,0 +1,459 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Analog Devices MAX313XX series I2C RTC driver + * + * Copyright 2022 Analog Devices Inc. + */ +#include <bcd.h> +#include <dm.h> +#include <i2c.h> +#include <rtc.h> +#include <dm/device_compat.h> +#include <linux/bitfield.h> +#include <linux/delay.h> +#include <linux/kernel.h> + +/* common registers */ +#define MAX313XX_INT_ALARM1 BIT(0) +#define MAX313XX_INT_ALARM2 BIT(1) +#define MAX313XX_HRS_F_12_24 BIT(6) +#define MAX313XX_HRS_F_AM_PM BIT(5) +#define MAX313XX_MONTH_CENTURY BIT(7) + +#define MAX313XX_TMR_CFG_ENABLE BIT(4) +#define MAX313XX_TMR_CFG_FREQ_MASK GENMASK(1, 0) +#define MAX313XX_TMR_CFG_FREQ_16HZ 0x03 + +#define MAX313XX_REG_MINUTE 0x01 +#define MAX313XX_REG_HOUR 0x02 + +#define MAX313XX_TIME_SIZE 0x07 + +/* device specific registers */ +#define MAX3134X_CFG2_REG 0x01 +#define MAX3134X_CFG2_SET_RTC BIT(1) + +#define MAX31341_TRICKLE_RES_MASK GENMASK(1, 0) +#define MAX31341_TRICKLE_DIODE_EN BIT(2) +#define MAX31341_TRICKLE_ENABLE_BIT BIT(3) +#define MAX31341_POWER_MGMT_REG 0x56 +#define MAX31341_POWER_MGMT_TRICKLE_BIT BIT(0) + +#define MAX3133X_TRICKLE_RES_MASK GENMASK(2, 1) +#define MAX3133X_TRICKLE_DIODE_EN BIT(3) +#define MAX3133X_TRICKLE_ENABLE_BIT BIT(0) + +#define MAX31329_TRICKLE_ENABLE_BIT BIT(7) +#define MAX31343_TRICKLE_ENABLE_MASK GENMASK(7, 4) +#define MAX31343_TRICKLE_ENABLE_CODE 5 +#define MAX31329_43_TRICKLE_RES_MASK GENMASK(1, 0) +#define MAX31329_43_TRICKLE_DIODE_EN BIT(2) + +#define MAX31329_CONFIG2_REG 0x04 +#define MAX31329_CONFIG2_CLKIN_EN BIT(2) +#define MAX31329_CONFIG2_CLKIN_FREQ GENMASK(1, 0) + +#define MAX31341_42_CONFIG1_REG 0x00 +#define MAX31341_42_CONFIG1_CLKIN_EN BIT(7) +#define MAX31341_42_CONFIG1_CLKIN_FREQ GENMASK(5, 4) +#define MAX31341_42_CONFIG1_OSC_DISABLE BIT(3) +#define MAX31341_42_CONFIG1_SWRST BIT(0) + +enum max313xx_ids { + ID_MAX31328, + ID_MAX31329, + ID_MAX31331, + ID_MAX31334, + ID_MAX31341, + ID_MAX31342, + ID_MAX31343, + MAX313XX_ID_NR +}; + +/** + * struct chip_desc - descriptor for MAX313xx variants + * @sec_reg: Offset to seconds register. Used to denote the start of the + * current time registers. + * @alarm1_sec_reg: Offset to Alarm1 seconds register. Used to denote the + * start of the alarm registers. + * @int_en_reg: Offset to the interrupt enable register. + * @int_status_reg: Offset to the interrupt status register. + * @ram_reg: Offset to the timestamp RAM (which can be used as SRAM). + * @ram_size: Size of the timestamp RAM. + * @temp_reg: Offset to the temperature register (or 0 if temperature + * sensor is not supported). + * @trickle_reg: Offset to the trickle charger configuration register (or + * 0 if trickle charger is not supported). + * @rst_reg: Offset to the reset register. + * @rst_bit: Bit within the reset register for the software reset. + */ +struct chip_desc { + u8 sec_reg; + u8 alarm1_sec_reg; + + u8 int_en_reg; + u8 int_status_reg; + + u8 ram_reg; + u8 ram_size; + + u8 temp_reg; + + u8 trickle_reg; + + u8 rst_reg; + u8 rst_bit; +}; + +struct max313xx_priv { + enum max313xx_ids id; + const struct chip_desc *chip; +}; + +static const struct chip_desc chip[MAX313XX_ID_NR] = { + [ID_MAX31328] = { + .int_en_reg = 0x0E, + .int_status_reg = 0x0F, + .sec_reg = 0x00, + .alarm1_sec_reg = 0x07, + .temp_reg = 0x11, + }, + [ID_MAX31329] = { + .int_en_reg = 0x01, + .int_status_reg = 0x00, + .sec_reg = 0x06, + .alarm1_sec_reg = 0x0D, + .ram_reg = 0x22, + .ram_size = 64, + .trickle_reg = 0x19, + .rst_reg = 0x02, + .rst_bit = BIT(0), + }, + [ID_MAX31331] = { + .int_en_reg = 0x01, + .int_status_reg = 0x00, + .sec_reg = 0x08, + .alarm1_sec_reg = 0x0F, + .ram_reg = 0x20, + .ram_size = 32, + .trickle_reg = 0x1B, + .rst_reg = 0x02, + .rst_bit = BIT(0), + }, + [ID_MAX31334] = { + .int_en_reg = 0x01, + .int_status_reg = 0x00, + .sec_reg = 0x09, + .alarm1_sec_reg = 0x10, + .ram_reg = 0x30, + .ram_size = 32, + .trickle_reg = 0x1E, + .rst_reg = 0x02, + .rst_bit = BIT(0), + }, + [ID_MAX31341] = { + .int_en_reg = 0x04, + .int_status_reg = 0x05, + .sec_reg = 0x06, + .alarm1_sec_reg = 0x0D, + .ram_reg = 0x16, + .ram_size = 64, + .trickle_reg = 0x57, + .rst_reg = 0x00, + .rst_bit = BIT(0), + }, + [ID_MAX31342] = { + .int_en_reg = 0x04, + .int_status_reg = 0x05, + .sec_reg = 0x06, + .alarm1_sec_reg = 0x0D, + .rst_reg = 0x00, + .rst_bit = BIT(0), + }, + [ID_MAX31343] = { + .int_en_reg = 0x01, + .int_status_reg = 0x00, + .sec_reg = 0x06, + .alarm1_sec_reg = 0x0D, + .ram_reg = 0x22, + .ram_size = 64, + .temp_reg = 0x1A, + .trickle_reg = 0x19, + .rst_reg = 0x02, + .rst_bit = BIT(0), + }, +}; + +static const u32 max313xx_trickle_ohms[] = { 3000, 6000, 11000 }; + +static int max313xx_set_bits(struct udevice *dev, unsigned int reg, unsigned int bits) +{ + int ret; + + ret = dm_i2c_reg_read(dev, reg); + if (ret < 0) + return ret; + + return dm_i2c_reg_write(dev, reg, ret | bits); +} + +static int max313xx_clear_bits(struct udevice *dev, unsigned int reg, unsigned int bits) +{ + int ret; + + ret = dm_i2c_reg_read(dev, reg); + if (ret < 0) + return ret; + + return dm_i2c_reg_write(dev, reg, ret & ~bits); +} + +static int max313xx_get_hour(u8 hour_reg) +{ + int hour; + + /* 24Hr mode */ + if (!FIELD_GET(MAX313XX_HRS_F_12_24, hour_reg)) + return bcd2bin(hour_reg & 0x3f); + + /* 12Hr mode */ + hour = bcd2bin(hour_reg & 0x1f); + if (hour == 12) + hour = 0; + + if (FIELD_GET(MAX313XX_HRS_F_AM_PM, hour_reg)) + hour += 12; + + return hour; +} + +static int max313xx_read_time(struct udevice *dev, struct rtc_time *t) +{ + struct max313xx_priv *rtc = dev_get_priv(dev); + u8 regs[7]; + int ret; + + ret = dm_i2c_read(dev, rtc->chip->sec_reg, regs, 7); + if (ret) + return ret; + + t->tm_sec = bcd2bin(regs[0] & 0x7f); + t->tm_min = bcd2bin(regs[1] & 0x7f); + t->tm_hour = max313xx_get_hour(regs[2]); + t->tm_wday = bcd2bin(regs[3] & 0x07) - 1; + t->tm_mday = bcd2bin(regs[4] & 0x3f); + t->tm_mon = bcd2bin(regs[5] & 0x1f); + t->tm_year = bcd2bin(regs[6]) + 2000; + + if (FIELD_GET(MAX313XX_MONTH_CENTURY, regs[5])) + t->tm_year += 100; + + dev_dbg(dev, "read %4d-%02d-%02d (wday=%d) %2d:%02d:%02d\n", + t->tm_year, t->tm_mon, t->tm_mday, + t->tm_wday, t->tm_hour, t->tm_min, t->tm_sec); + + return 0; +} + +static int max313xx_set_time(struct udevice *dev, const struct rtc_time *t) +{ + struct max313xx_priv *rtc = dev_get_priv(dev); + u8 regs[7]; + int ret; + + dev_dbg(dev, "set %4d-%02d-%02d (wday=%d) %2d:%02d:%02d\n", + t->tm_year, t->tm_mon, t->tm_mday, + t->tm_wday, t->tm_hour, t->tm_min, t->tm_sec); + + if (t->tm_year < 2000) { + dev_err(dev, "year %d (before 2000) not supported\n", + t->tm_year); + return -EINVAL; + } + + if (rtc->chip->rst_bit) { + ret = max313xx_clear_bits(dev, rtc->chip->rst_reg, rtc->chip->rst_bit); + if (ret) + return ret; + } + + regs[0] = bin2bcd(t->tm_sec); + regs[1] = bin2bcd(t->tm_min); + regs[2] = bin2bcd(t->tm_hour); + regs[3] = bin2bcd(t->tm_wday + 1); + regs[4] = bin2bcd(t->tm_mday); + regs[5] = bin2bcd(t->tm_mon); + regs[6] = bin2bcd((t->tm_year - 2000) % 100); + + if ((t->tm_year - 2000) >= 200) + regs[5] |= FIELD_PREP(MAX313XX_MONTH_CENTURY, 1); + + ret = dm_i2c_write(dev, rtc->chip->sec_reg, regs, 7); + if (ret) + return ret; + + switch (rtc->id) { + case ID_MAX31341: + case ID_MAX31342: + ret = max313xx_set_bits(dev, MAX3134X_CFG2_REG, + MAX3134X_CFG2_SET_RTC); + if (ret) + return ret; + + udelay(10000); + + ret = max313xx_clear_bits(dev, MAX3134X_CFG2_REG, + MAX3134X_CFG2_SET_RTC); + if (ret) + return ret; + + break; + default: + break; + } + + return ret; +} + +static int max313xx_reset(struct udevice *dev) +{ + struct max313xx_priv *rtc = dev_get_priv(dev); + int ret = -EINVAL; + + if (rtc->chip->rst_bit) + ret = max313xx_set_bits(dev, rtc->chip->rst_reg, rtc->chip->rst_bit); + + return ret; +} + +static const struct rtc_ops max3133x_rtc_ops = { + .get = max313xx_read_time, + .set = max313xx_set_time, + .reset = max313xx_reset, +}; + +static int max313xx_init(struct udevice *dev) +{ + struct max313xx_priv *rtc = dev_get_priv(dev); + int ret; + + switch (rtc->id) { + case ID_MAX31341: + case ID_MAX31342: + ret = max313xx_clear_bits(dev, MAX31341_42_CONFIG1_REG, + MAX31341_42_CONFIG1_OSC_DISABLE); + if (ret) + return ret; + + return max313xx_set_bits(dev, MAX31341_42_CONFIG1_REG, + MAX31341_42_CONFIG1_SWRST); + default: + return 0; + } +} + +static int max313xx_trickle_charger_setup(struct udevice *dev) +{ + struct max313xx_priv *rtc = dev_get_priv(dev); + bool diode; + int index, reg; + u32 ohms; + u32 chargeable; + int ret; + + if (dev_read_u32(dev, "trickle-resistor-ohms", &ohms) || + dev_read_u32(dev, "aux-voltage-chargeable", &chargeable)) + return 0; + + switch (chargeable) { + case 0: + diode = false; + break; + case 1: + diode = true; + break; + default: + dev_dbg(dev, "unsupported aux-voltage-chargeable value\n"); + return -EINVAL; + } + + if (!rtc->chip->trickle_reg) { + dev_warn(dev, "device does not have trickle charger\n"); + return -ENOTSUPP; + } + + index = find_closest(ohms, max313xx_trickle_ohms, + ARRAY_SIZE(max313xx_trickle_ohms)) + 1; + + switch (rtc->id) { + case ID_MAX31329: + reg = FIELD_PREP(MAX31329_TRICKLE_ENABLE_BIT, 1) | + FIELD_PREP(MAX31329_43_TRICKLE_RES_MASK, index) | + FIELD_PREP(MAX31329_43_TRICKLE_DIODE_EN, diode); + break; + case ID_MAX31331: + case ID_MAX31334: + reg = FIELD_PREP(MAX3133X_TRICKLE_ENABLE_BIT, 1) | + FIELD_PREP(MAX3133X_TRICKLE_DIODE_EN, diode) | + FIELD_PREP(MAX3133X_TRICKLE_RES_MASK, index); + break; + case ID_MAX31341: + if (index == 1) + index = 0; + reg = FIELD_PREP(MAX31341_TRICKLE_ENABLE_BIT, 1) | + FIELD_PREP(MAX31341_TRICKLE_DIODE_EN, diode) | + FIELD_PREP(MAX31341_TRICKLE_RES_MASK, index); + + ret = max313xx_set_bits(dev, MAX31341_POWER_MGMT_REG, + MAX31341_POWER_MGMT_TRICKLE_BIT); + if (ret) + return ret; + + break; + case ID_MAX31343: + reg = FIELD_PREP(MAX31329_43_TRICKLE_RES_MASK, index) | + FIELD_PREP(MAX31329_43_TRICKLE_DIODE_EN, diode) | + FIELD_PREP(MAX31343_TRICKLE_ENABLE_MASK, + MAX31343_TRICKLE_ENABLE_CODE); + break; + default: + return -EOPNOTSUPP; + } + + return dm_i2c_reg_write(dev, rtc->chip->trickle_reg, reg); +} + +static int max313xx_probe(struct udevice *dev) +{ + struct max313xx_priv *max313xx = dev_get_priv(dev); + int ret; + + max313xx->id = dev_get_driver_data(dev); + max313xx->chip = &chip[max313xx->id]; + + ret = max313xx_init(dev); + if (ret) + return ret; + + return max313xx_trickle_charger_setup(dev); +} + +static const struct udevice_id max313xx_of_id[] = { + { .compatible = "adi,max31328", .data = ID_MAX31328 }, + { .compatible = "adi,max31329", .data = ID_MAX31329 }, + { .compatible = "adi,max31331", .data = ID_MAX31331 }, + { .compatible = "adi,max31334", .data = ID_MAX31334 }, + { .compatible = "adi,max31341", .data = ID_MAX31341 }, + { .compatible = "adi,max31342", .data = ID_MAX31342 }, + { .compatible = "adi,max31343", .data = ID_MAX31343 }, + { } +}; + +U_BOOT_DRIVER(rtc_max313xx) = { + .name = "rtc-max313xx", + .id = UCLASS_RTC, + .probe = max313xx_probe, + .of_match = max313xx_of_id, + .priv_auto = sizeof(struct max313xx_priv), + .ops = &max3133x_rtc_ops, +}; diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index bb5083201b3..10d07daf277 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -415,6 +415,14 @@ config DEBUG_UART_SEMIHOSTING start up driver model. The driver will be available until the real driver model serial is running. +config DEBUG_UART_SCIF + bool "Renesas SCIF UART" + depends on SH || ARCH_RMOBILE + help + Select this to enable a debug UART using the serial_sh driver. You + will need to provide parameters to make this work. The driver will + be available until the real driver-model serial is running. + config DEBUG_UART_SIFIVE bool "SiFive UART" depends on SIFIVE_SERIAL diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c index 4671217b59a..e08bdcadc9c 100644 --- a/drivers/serial/serial_sh.c +++ b/drivers/serial/serial_sh.c @@ -249,9 +249,40 @@ U_BOOT_DRIVER(serial_sh) = { #endif .priv_auto = sizeof(struct uart_port), }; +#endif -#else /* CONFIG_DM_SERIAL */ +#if !CONFIG_IS_ENABLED(DM_SERIAL) || IS_ENABLED(CONFIG_DEBUG_UART_SCIF) +#if defined(CFG_SCIF_A) + #define SCIF_BASE_PORT PORT_SCIFA +#elif defined(CFG_SCI) + #define SCIF_BASE_PORT PORT_SCI +#else + #define SCIF_BASE_PORT PORT_SCIF +#endif + +static void sh_serial_init_nodm(struct uart_port *port) +{ + sh_serial_init_generic(port); + serial_setbrg(); +} + +static void sh_serial_putc_nondm(struct uart_port *port, const char c) +{ + if (c == '\n') { + while (1) { + if (serial_raw_putc(port, '\r') != -EAGAIN) + break; + } + } + while (1) { + if (serial_raw_putc(port, c) != -EAGAIN) + break; + } +} +#endif + +#if !CONFIG_IS_ENABLED(DM_SERIAL) #if defined(CONFIG_CONS_SCIF0) # define SCIF_BASE SCIF0_BASE #elif defined(CONFIG_CONS_SCIF1) @@ -274,19 +305,11 @@ U_BOOT_DRIVER(serial_sh) = { # error "Default SCIF doesn't set....." #endif -#if defined(CFG_SCIF_A) - #define SCIF_BASE_PORT PORT_SCIFA -#elif defined(CONFIG_SCI) - #define SCIF_BASE_PORT PORT_SCI -#else - #define SCIF_BASE_PORT PORT_SCIF -#endif - static struct uart_port sh_sci = { .membase = (unsigned char *)SCIF_BASE, .mapbase = SCIF_BASE, .type = SCIF_BASE_PORT, -#ifdef CONFIG_SCIF_USE_EXT_CLK +#ifdef CFG_SCIF_USE_EXT_CLK .clk_mode = EXT_CLK, #endif }; @@ -301,28 +324,14 @@ static void sh_serial_setbrg(void) static int sh_serial_init(void) { - struct uart_port *port = &sh_sci; - - sh_serial_init_generic(port); - serial_setbrg(); + sh_serial_init_nodm(&sh_sci); return 0; } static void sh_serial_putc(const char c) { - struct uart_port *port = &sh_sci; - - if (c == '\n') { - while (1) { - if (serial_raw_putc(port, '\r') != -EAGAIN) - break; - } - } - while (1) { - if (serial_raw_putc(port, c) != -EAGAIN) - break; - } + sh_serial_putc_nondm(&sh_sci, c); } static int sh_serial_tstc(void) @@ -367,3 +376,29 @@ __weak struct serial_device *default_serial_console(void) return &sh_serial_drv; } #endif /* CONFIG_DM_SERIAL */ + +#ifdef CONFIG_DEBUG_UART_SCIF +#include <debug_uart.h> + +static struct uart_port debug_uart_sci = { + .membase = (unsigned char *)CONFIG_DEBUG_UART_BASE, + .mapbase = CONFIG_DEBUG_UART_BASE, + .type = SCIF_BASE_PORT, +#ifdef CFG_SCIF_USE_EXT_CLK + .clk_mode = EXT_CLK, +#endif +}; + +static inline void _debug_uart_init(void) +{ + sh_serial_init_nodm(&debug_uart_sci); +} + +static inline void _debug_uart_putc(int c) +{ + sh_serial_putc_nondm(&debug_uart_sci, c); +} + +DEBUG_UART_FUNCS + +#endif diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h index 660aaab6638..eb8523dde55 100644 --- a/drivers/serial/serial_sh.h +++ b/drivers/serial/serial_sh.h @@ -406,13 +406,13 @@ SCIF_FNS(SCSPTR, 0, 0, 0x24, 16) SCIF_FNS(SCLSR, 0, 0, 0x28, 16) #else -SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16) +SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16) #if defined(CONFIG_CPU_SH7722) -SCIF_FNS(SCSPTR, 0, 0, 0, 0) +SCIF_FNS(SCSPTR, 0, 0, 0, 0) #else -SCIF_FNS(SCSPTR, 0, 0, 0x20, 16) +SCIF_FNS(SCSPTR, 0, 0, 0x20, 16) #endif -SCIF_FNS(SCLSR, 0, 0, 0x24, 16) +SCIF_FNS(SCLSR, 0, 0, 0x24, 16) #endif SCIF_FNS(DL, 0, 0, 0x0, 0) /* dummy */ #endif diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c index 4e9115dafee..9e6255a172a 100644 --- a/drivers/spi/xilinx_spi.c +++ b/drivers/spi/xilinx_spi.c @@ -112,10 +112,9 @@ struct xilinx_spi_priv { static int xilinx_spi_probe(struct udevice *bus) { struct xilinx_spi_priv *priv = dev_get_priv(bus); - struct xilinx_spi_regs *regs = priv->regs; - - priv->regs = (struct xilinx_spi_regs *)dev_read_addr(bus); + struct xilinx_spi_regs *regs; + regs = priv->regs = (struct xilinx_spi_regs *)dev_read_addr(bus); priv->fifo_depth = dev_read_u32_default(bus, "fifo-size", 0); writel(SPISSR_RESET_VALUE, ®s->srr); diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c index 335b458cb90..c4aee279aa4 100644 --- a/drivers/spi/zynqmp_gqspi.c +++ b/drivers/spi/zynqmp_gqspi.c @@ -183,6 +183,11 @@ struct zynqmp_qspi_priv { const struct spi_mem_op *op; }; +__weak int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value) +{ + return 0; +} + static int zynqmp_qspi_of_to_plat(struct udevice *bus) { struct zynqmp_qspi_plat *plat = dev_get_plat(bus); diff --git a/drivers/sysinfo/gpio.c b/drivers/sysinfo/gpio.c index 1d7f050998a..82f90303bb7 100644 --- a/drivers/sysinfo/gpio.c +++ b/drivers/sysinfo/gpio.c @@ -57,7 +57,7 @@ static int sysinfo_gpio_get_str(struct udevice *dev, int id, size_t size, char * int i, ret; u32 revision; - for (i = 0; i < priv->gpio_num; i++) { + for (i = 0; ; i++) { ret = dev_read_u32_index(dev, "revisions", i, &revision); if (ret) { @@ -80,7 +80,8 @@ static int sysinfo_gpio_get_str(struct udevice *dev, int id, size_t size, char * strncpy(val, name, size); val[size - 1] = '\0'; return 0; - } default: + } + default: return -EINVAL; }; } diff --git a/drivers/sysreset/sysreset_mpc83xx.c b/drivers/sysreset/sysreset_mpc83xx.c index c9a03266595..ca48328f7b5 100644 --- a/drivers/sysreset/sysreset_mpc83xx.c +++ b/drivers/sysreset/sysreset_mpc83xx.c @@ -107,7 +107,7 @@ static int print_83xx_arb_event(bool force, char *buf, int size) if (!force && !gd->arch.arbiter_event_address) return 0; - if (CONFIG_IS_ENABLED(DISPLAY_AER_FULL)) { + if (IS_ENABLED(CONFIG_DISPLAY_AER_FULL)) { res = snprintf(buf, size, "Arbiter Event Status:\n" " %s: 0x%08lX\n" @@ -184,7 +184,7 @@ static int mpc83xx_sysreset_get_status(struct udevice *dev, char *buf, int size) * TODO(mario.six@gdsys.cc): Move this into a dedicated * arbiter driver */ - if (CONFIG_IS_ENABLED(DISPLAY_AER_FULL) || + if (IS_ENABLED(CONFIG_DISPLAY_AER_FULL) || IS_ENABLED(CONFIG_DISPLAY_AER_BRIEF)) { /* * If there was a bus monitor reset event, we force the arbiter diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index f32bd16227e..915b2af160c 100644 --- a/drivers/timer/Kconfig +++ b/drivers/timer/Kconfig @@ -145,6 +145,13 @@ config DESIGNWARE_APB_TIMER Enables support for the Designware APB Timer driver. This timer is present on Altera SoCFPGA SoCs. +config FTTMR010_TIMER + bool "Faraday Technology timer support" + depends on TIMER + help + Select this to enable support for the timer found on + devices using Faraday Technology's IP. + config GXP_TIMER bool "HPE GXP Timer" depends on TIMER diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile index 3c92113fc6f..cdc20f5e946 100644 --- a/drivers/timer/Makefile +++ b/drivers/timer/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_$(SPL_)ATMEL_PIT_TIMER) += atmel_pit_timer.o obj-$(CONFIG_$(SPL_)ATMEL_TCB_TIMER) += atmel_tcb_timer.o obj-$(CONFIG_CADENCE_TTC_TIMER) += cadence-ttc.o obj-$(CONFIG_DESIGNWARE_APB_TIMER) += dw-apb-timer.o +obj-$(CONFIG_FTTMR010_TIMER) += fttmr010_timer.o obj-$(CONFIG_GXP_TIMER) += gxp-timer.o obj-$(CONFIG_MPC83XX_TIMER) += mpc83xx_timer.o obj-$(CONFIG_NOMADIK_MTU_TIMER) += nomadik-mtu-timer.o diff --git a/drivers/timer/fttmr010_timer.c b/drivers/timer/fttmr010_timer.c new file mode 100644 index 00000000000..b6289e64610 --- /dev/null +++ b/drivers/timer/fttmr010_timer.c @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert@faraday-tech.com> + * + * 23/08/2022 Port to DM + */ +#include <common.h> +#include <dm.h> +#include <log.h> +#include <timer.h> +#include <asm/io.h> +#include <dm/ofnode.h> +#include <faraday/fttmr010.h> +#include <asm/global_data.h> + +#define TIMER_LOAD_VAL 0xffffffff + +struct fttmr010_timer_priv { + struct fttmr010 __iomem *regs; +}; + +static u64 fttmr010_timer_get_count(struct udevice *dev) +{ + struct fttmr010_timer_priv *priv = dev_get_priv(dev); + struct fttmr010 *tmr = priv->regs; + u32 now = TIMER_LOAD_VAL - readl(&tmr->timer3_counter); + + /* increment tbu if tbl has rolled over */ + if (now < gd->arch.tbl) + gd->arch.tbu++; + gd->arch.tbl = now; + + return ((u64)gd->arch.tbu << 32) | gd->arch.tbl; +} + +static int fttmr010_timer_probe(struct udevice *dev) +{ + struct fttmr010_timer_priv *priv = dev_get_priv(dev); + struct fttmr010 *tmr; + unsigned int cr; + + priv->regs = dev_read_addr_ptr(dev); + if (!priv->regs) + return -EINVAL; + tmr = priv->regs; + + debug("Faraday FTTMR010 timer revision 0x%08X\n", readl(&tmr->revision)); + + /* disable timers */ + writel(0, &tmr->cr); + + /* setup timer */ + writel(TIMER_LOAD_VAL, &tmr->timer3_load); + writel(TIMER_LOAD_VAL, &tmr->timer3_counter); + writel(0, &tmr->timer3_match1); + writel(0, &tmr->timer3_match2); + + /* we don't want timer to issue interrupts */ + writel(FTTMR010_TM3_MATCH1 | + FTTMR010_TM3_MATCH2 | + FTTMR010_TM3_OVERFLOW, + &tmr->interrupt_mask); + + cr = readl(&tmr->cr); + cr |= FTTMR010_TM3_CLOCK; /* use external clock */ + cr |= FTTMR010_TM3_ENABLE; + writel(cr, &tmr->cr); + + gd->arch.tbl = 0; + gd->arch.tbu = 0; + + return 0; +} + +static const struct timer_ops fttmr010_timer_ops = { + .get_count = fttmr010_timer_get_count, +}; + +static const struct udevice_id fttmr010_timer_ids[] = { + { .compatible = "faraday,fttmr010-timer" }, + {} +}; + +U_BOOT_DRIVER(fttmr010_timer) = { + .name = "fttmr010_timer", + .id = UCLASS_TIMER, + .of_match = fttmr010_timer_ids, + .priv_auto = sizeof(struct fttmr010_timer_priv), + .probe = fttmr010_timer_probe, + .ops = &fttmr010_timer_ops, +}; diff --git a/drivers/timer/tsc_timer.c b/drivers/timer/tsc_timer.c index 192c7b71a5a..f86a0b86921 100644 --- a/drivers/timer/tsc_timer.c +++ b/drivers/timer/tsc_timer.c @@ -404,6 +404,15 @@ static void tsc_timer_ensure_setup(bool early) if (!gd->arch.clock_rate) { unsigned long fast_calibrate; + /** + * There is no obvious way to obtain this information from EFI + * boot services. This value was measured on a Framework Laptop + * which has a 12th Gen Intel Core + */ + if (IS_ENABLED(CONFIG_EFI_APP)) { + fast_calibrate = 2750; + goto done; + } fast_calibrate = native_calibrate_tsc(); if (fast_calibrate) goto done; diff --git a/drivers/tpm/tpm2_tis_sandbox.c b/drivers/tpm/tpm2_tis_sandbox.c index dd94bdc31fb..e4004cfcca3 100644 --- a/drivers/tpm/tpm2_tis_sandbox.c +++ b/drivers/tpm/tpm2_tis_sandbox.c @@ -810,7 +810,7 @@ static int sandbox_tpm2_open(struct udevice *dev) struct sandbox_tpm2 *tpm = dev_get_priv(dev); if (tpm->init_done) - return -EIO; + return -EBUSY; tpm->init_done = true; diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig index f010291d022..c0c8c16fd9c 100644 --- a/drivers/usb/dwc3/Kconfig +++ b/drivers/usb/dwc3/Kconfig @@ -40,7 +40,7 @@ config SPL_USB_DWC3_GENERIC config USB_DWC3_MESON_G12A bool "Amlogic Meson G12A USB wrapper" depends on DM_USB && USB_DWC3 && ARCH_MESON - imply PHY + select PHY help Select this for Amlogic Meson G12A Platforms. This wrapper supports Host and Peripheral operation modes. @@ -48,14 +48,17 @@ config USB_DWC3_MESON_G12A config USB_DWC3_MESON_GXL bool "Amlogic Meson GXL USB wrapper" depends on DM_USB && USB_DWC3 && ARCH_MESON - imply PHY + select PHY help Select this for Amlogic Meson GXL and GXM Platforms. This wrapper supports Host and Peripheral operation modes. config USB_DWC3_UNIPHIER bool "DesignWare USB3 Host Support on UniPhier Platforms" - depends on ARCH_UNIPHIER && USB_XHCI_DWC3 + depends on ARCH_UNIPHIER && USB_DWC3 + select USB_DWC3_GENERIC + select PHY + select PHY_UNIPHIER_USB3 help Support of USB2/3 functionality in Socionext UniPhier platforms. Say 'Y' here if you have one such device. diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c index ed1b9b630eb..66da5a8d6f8 100644 --- a/drivers/usb/dwc3/dwc3-generic.c +++ b/drivers/usb/dwc3/dwc3-generic.c @@ -28,11 +28,7 @@ #include <usb/xhci.h> #include <asm/gpio.h> -struct dwc3_glue_data { - struct clk_bulk clks; - struct reset_ctl_bulk resets; - fdt_addr_t regs; -}; +#include "dwc3-generic.h" struct dwc3_generic_plat { fdt_addr_t base; @@ -68,10 +64,27 @@ static int dwc3_generic_probe(struct udevice *dev, #if CONFIG_IS_ENABLED(OF_CONTROL) dwc3_of_parse(dwc3); + /* + * There are currently four disparate placement possibilities of DWC3 + * reference clock phandle in SoC DTs: + * - in top level glue node, with generic subnode without clock (ZynqMP) + * - in top level generic node, with no subnode (i.MX8MQ) + * - in generic subnode, with other clock in top level node (i.MX8MP) + * - in both top level node and generic subnode (Rockchip) + * Cover all the possibilities here by looking into both nodes, start + * with the top level node as that seems to be used in majority of DTs + * to reference the clock. + */ node = dev_ofnode(dev->parent); index = ofnode_stringlist_search(node, "clock-names", "ref"); if (index < 0) index = ofnode_stringlist_search(node, "clock-names", "ref_clk"); + if (index < 0) { + node = dev_ofnode(dev); + index = ofnode_stringlist_search(node, "clock-names", "ref"); + if (index < 0) + index = ofnode_stringlist_search(node, "clock-names", "ref_clk"); + } if (index >= 0) dwc3->ref_clk = &glue->clks.clks[index]; #endif @@ -258,11 +271,6 @@ U_BOOT_DRIVER(dwc3_generic_host) = { }; #endif -struct dwc3_glue_ops { - void (*glue_configure)(struct udevice *dev, int index, - enum usb_dr_mode mode); -}; - void dwc3_imx8mp_glue_configure(struct udevice *dev, int index, enum usb_dr_mode mode) { @@ -398,54 +406,74 @@ struct dwc3_glue_ops ti_ops = { .glue_configure = dwc3_ti_glue_configure, }; -static int dwc3_glue_bind(struct udevice *parent) +static int dwc3_glue_bind_common(struct udevice *parent, ofnode node) { - ofnode node; - int ret; + const char *name = ofnode_get_name(node); + const char *driver = NULL; enum usb_dr_mode dr_mode; + struct udevice *dev; + int ret; - dr_mode = usb_get_dr_mode(dev_ofnode(parent)); - - ofnode_for_each_subnode(node, dev_ofnode(parent)) { - const char *name = ofnode_get_name(node); - struct udevice *dev; - const char *driver = NULL; - - debug("%s: subnode name: %s\n", __func__, name); + debug("%s: subnode name: %s\n", __func__, name); - /* if the parent node doesn't have a mode check the leaf */ - if (!dr_mode) - dr_mode = usb_get_dr_mode(node); + /* if the parent node doesn't have a mode check the leaf */ + dr_mode = usb_get_dr_mode(dev_ofnode(parent)); + if (!dr_mode) + dr_mode = usb_get_dr_mode(node); - switch (dr_mode) { - case USB_DR_MODE_PERIPHERAL: - case USB_DR_MODE_OTG: + switch (dr_mode) { + case USB_DR_MODE_PERIPHERAL: + case USB_DR_MODE_OTG: #if CONFIG_IS_ENABLED(DM_USB_GADGET) - debug("%s: dr_mode: OTG or Peripheral\n", __func__); - driver = "dwc3-generic-peripheral"; + debug("%s: dr_mode: OTG or Peripheral\n", __func__); + driver = "dwc3-generic-peripheral"; #endif - break; + break; #if defined(CONFIG_SPL_USB_HOST) || !defined(CONFIG_SPL_BUILD) - case USB_DR_MODE_HOST: - debug("%s: dr_mode: HOST\n", __func__); - driver = "dwc3-generic-host"; - break; + case USB_DR_MODE_HOST: + debug("%s: dr_mode: HOST\n", __func__); + driver = "dwc3-generic-host"; + break; #endif - default: - debug("%s: unsupported dr_mode\n", __func__); - return -ENODEV; - }; + default: + debug("%s: unsupported dr_mode\n", __func__); + return -ENODEV; + }; - if (!driver) - continue; + if (!driver) + return -ENXIO; + + ret = device_bind_driver_to_node(parent, driver, name, + node, &dev); + if (ret) { + debug("%s: not able to bind usb device mode\n", + __func__); + return ret; + } + + return 0; +} - ret = device_bind_driver_to_node(parent, driver, name, - node, &dev); - if (ret) { - debug("%s: not able to bind usb device mode\n", - __func__); +int dwc3_glue_bind(struct udevice *parent) +{ + struct dwc3_glue_ops *ops = (struct dwc3_glue_ops *)dev_get_driver_data(parent); + ofnode node; + int ret; + + if (ops && ops->glue_get_ctrl_dev) { + ret = ops->glue_get_ctrl_dev(parent, &node); + if (ret) + return ret; + + return dwc3_glue_bind_common(parent, node); + } + + ofnode_for_each_subnode(node, dev_ofnode(parent)) { + ret = dwc3_glue_bind_common(parent, node); + if (ret == -ENXIO) + continue; + if (ret) return ret; - } } return 0; @@ -493,7 +521,7 @@ static int dwc3_glue_clk_init(struct udevice *dev, return 0; } -static int dwc3_glue_probe(struct udevice *dev) +int dwc3_glue_probe(struct udevice *dev) { struct dwc3_glue_ops *ops = (struct dwc3_glue_ops *)dev_get_driver_data(dev); struct dwc3_glue_data *glue = dev_get_plat(dev); @@ -514,7 +542,7 @@ static int dwc3_glue_probe(struct udevice *dev) phy.dev = NULL; } - glue->regs = dev_read_addr(dev); + glue->regs = dev_read_addr_size_index(dev, 0, &glue->size); ret = dwc3_glue_clk_init(dev, glue); if (ret) @@ -534,6 +562,12 @@ static int dwc3_glue_probe(struct udevice *dev) if (ret) return ret; + if (glue->clks.count == 0) { + ret = dwc3_glue_clk_init(child, glue); + if (ret) + return ret; + } + if (glue->resets.count == 0) { ret = dwc3_glue_reset_init(child, glue); if (ret) @@ -553,7 +587,7 @@ static int dwc3_glue_probe(struct udevice *dev) return 0; } -static int dwc3_glue_remove(struct udevice *dev) +int dwc3_glue_remove(struct udevice *dev) { struct dwc3_glue_data *glue = dev_get_plat(dev); diff --git a/drivers/usb/dwc3/dwc3-generic.h b/drivers/usb/dwc3/dwc3-generic.h new file mode 100644 index 00000000000..40902c8923f --- /dev/null +++ b/drivers/usb/dwc3/dwc3-generic.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * dwc3-generic.h - Generic DWC3 Glue layer header + * + * Copyright (C) 2016 - 2018 Xilinx, Inc. + * Copyright (C) 2023 Socionext Inc. + */ + +#ifndef __DRIVERS_USB_DWC3_GENERIC_H +#define __DRIVERS_USB_DWC3_GENERIC_H + +#include <clk.h> +#include <reset.h> +#include <dwc3-uboot.h> + +struct dwc3_glue_data { + struct clk_bulk clks; + struct reset_ctl_bulk resets; + fdt_addr_t regs; + fdt_size_t size; +}; + +struct dwc3_glue_ops { + int (*glue_get_ctrl_dev)(struct udevice *parent, ofnode *node); + void (*glue_configure)(struct udevice *dev, int index, + enum usb_dr_mode mode); +}; + +int dwc3_glue_bind(struct udevice *parent); +int dwc3_glue_probe(struct udevice *dev); +int dwc3_glue_remove(struct udevice *dev); + +#endif diff --git a/drivers/usb/dwc3/dwc3-uniphier.c b/drivers/usb/dwc3/dwc3-uniphier.c index 54b52dcd66a..ab85428a700 100644 --- a/drivers/usb/dwc3/dwc3-uniphier.c +++ b/drivers/usb/dwc3/dwc3-uniphier.c @@ -4,14 +4,17 @@ * * Copyright (C) 2016-2017 Socionext Inc. * Author: Masahiro Yamada <yamada.masahiro@socionext.com> + * Author: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> */ #include <dm.h> -#include <dm/device_compat.h> +#include <dm/lists.h> #include <linux/bitops.h> -#include <linux/errno.h> -#include <linux/io.h> -#include <linux/sizes.h> +#include <linux/usb/gadget.h> + +#include "core.h" +#include "gadget.h" +#include "dwc3-generic.h" #define UNIPHIER_PRO4_DWC3_RESET 0x40 #define UNIPHIER_PRO4_DWC3_RESET_XIOMMU BIT(5) @@ -27,8 +30,11 @@ #define UNIPHIER_PXS2_DWC3_RESET 0x00 #define UNIPHIER_PXS2_DWC3_RESET_XLINK BIT(15) -static int uniphier_pro4_dwc3_init(void __iomem *regs) +static void uniphier_pro4_dwc3_init(struct udevice *dev, int index, + enum usb_dr_mode mode) { + struct dwc3_glue_data *glue = dev_get_plat(dev); + void *regs = map_physmem(glue->regs, glue->size, MAP_NOCACHE); u32 tmp; tmp = readl(regs + UNIPHIER_PRO4_DWC3_RESET); @@ -36,11 +42,14 @@ static int uniphier_pro4_dwc3_init(void __iomem *regs) tmp |= UNIPHIER_PRO4_DWC3_RESET_XIOMMU | UNIPHIER_PRO4_DWC3_RESET_XLINK; writel(tmp, regs + UNIPHIER_PRO4_DWC3_RESET); - return 0; + unmap_physmem(regs, MAP_NOCACHE); } -static int uniphier_pro5_dwc3_init(void __iomem *regs) +static void uniphier_pro5_dwc3_init(struct udevice *dev, int index, + enum usb_dr_mode mode) { + struct dwc3_glue_data *glue = dev_get_plat(dev); + void *regs = map_physmem(glue->regs, glue->size, MAP_NOCACHE); u32 tmp; tmp = readl(regs + UNIPHIER_PRO5_DWC3_RESET); @@ -49,72 +58,97 @@ static int uniphier_pro5_dwc3_init(void __iomem *regs) tmp |= UNIPHIER_PRO5_DWC3_RESET_XLINK | UNIPHIER_PRO5_DWC3_RESET_XIOMMU; writel(tmp, regs + UNIPHIER_PRO5_DWC3_RESET); - return 0; + unmap_physmem(regs, MAP_NOCACHE); } -static int uniphier_pxs2_dwc3_init(void __iomem *regs) +static void uniphier_pxs2_dwc3_init(struct udevice *dev, int index, + enum usb_dr_mode mode) { + struct dwc3_glue_data *glue = dev_get_plat(dev); + void *regs = map_physmem(glue->regs, glue->size, MAP_NOCACHE); u32 tmp; tmp = readl(regs + UNIPHIER_PXS2_DWC3_RESET); tmp |= UNIPHIER_PXS2_DWC3_RESET_XLINK; writel(tmp, regs + UNIPHIER_PXS2_DWC3_RESET); - return 0; + unmap_physmem(regs, MAP_NOCACHE); } -static int uniphier_dwc3_probe(struct udevice *dev) +static int dwc3_uniphier_glue_get_ctrl_dev(struct udevice *dev, ofnode *node) { - fdt_addr_t base; - void __iomem *regs; - int (*init)(void __iomem *regs); - int ret; + struct udevice *child; + const char *name; + ofnode subnode; + + /* + * "controller reset" belongs to glue logic, and it should be + * accessible in .glue_configure() before access to the controller + * begins. + */ + ofnode_for_each_subnode(subnode, dev_ofnode(dev)) { + name = ofnode_get_name(subnode); + if (!strncmp(name, "reset", 5)) + device_bind_driver_to_node(dev, "uniphier-reset", + name, subnode, &child); + } + + /* Get controller node that is placed separately from the glue node */ + *node = ofnode_by_compatible(dev_ofnode(dev->parent), + "socionext,uniphier-dwc3"); - base = dev_read_addr(dev); - if (base == FDT_ADDR_T_NONE) - return -EINVAL; - - regs = ioremap(base, SZ_32K); - if (!regs) - return -ENOMEM; + return 0; +} - init = (typeof(init))dev_get_driver_data(dev); - ret = init(regs); - if (ret) - dev_err(dev, "failed to init glue layer\n"); +static const struct dwc3_glue_ops uniphier_pro4_dwc3_ops = { + .glue_get_ctrl_dev = dwc3_uniphier_glue_get_ctrl_dev, + .glue_configure = uniphier_pro4_dwc3_init, +}; - iounmap(regs); +static const struct dwc3_glue_ops uniphier_pro5_dwc3_ops = { + .glue_get_ctrl_dev = dwc3_uniphier_glue_get_ctrl_dev, + .glue_configure = uniphier_pro5_dwc3_init, +}; - return ret; -} +static const struct dwc3_glue_ops uniphier_pxs2_dwc3_ops = { + .glue_get_ctrl_dev = dwc3_uniphier_glue_get_ctrl_dev, + .glue_configure = uniphier_pxs2_dwc3_init, +}; static const struct udevice_id uniphier_dwc3_match[] = { { - .compatible = "socionext,uniphier-pro4-dwc3", - .data = (ulong)uniphier_pro4_dwc3_init, + .compatible = "socionext,uniphier-pro4-dwc3-glue", + .data = (ulong)&uniphier_pro4_dwc3_ops, + }, + { + .compatible = "socionext,uniphier-pro5-dwc3-glue", + .data = (ulong)&uniphier_pro5_dwc3_ops, }, { - .compatible = "socionext,uniphier-pro5-dwc3", - .data = (ulong)uniphier_pro5_dwc3_init, + .compatible = "socionext,uniphier-pxs2-dwc3-glue", + .data = (ulong)&uniphier_pxs2_dwc3_ops, }, { - .compatible = "socionext,uniphier-pxs2-dwc3", - .data = (ulong)uniphier_pxs2_dwc3_init, + .compatible = "socionext,uniphier-ld20-dwc3-glue", + .data = (ulong)&uniphier_pxs2_dwc3_ops, }, { - .compatible = "socionext,uniphier-ld20-dwc3", - .data = (ulong)uniphier_pxs2_dwc3_init, + .compatible = "socionext,uniphier-pxs3-dwc3-glue", + .data = (ulong)&uniphier_pxs2_dwc3_ops, }, { - .compatible = "socionext,uniphier-pxs3-dwc3", - .data = (ulong)uniphier_pxs2_dwc3_init, + .compatible = "socionext,uniphier-nx1-dwc3-glue", + .data = (ulong)&uniphier_pxs2_dwc3_ops, }, { /* sentinel */ } }; -U_BOOT_DRIVER(usb_xhci) = { +U_BOOT_DRIVER(dwc3_uniphier_wrapper) = { .name = "uniphier-dwc3", .id = UCLASS_SIMPLE_BUS, .of_match = uniphier_dwc3_match, - .probe = uniphier_dwc3_probe, + .bind = dwc3_glue_bind, + .probe = dwc3_glue_probe, + .remove = dwc3_glue_remove, + .plat_auto = sizeof(struct dwc3_glue_data), }; diff --git a/drivers/usb/host/xhci-mtk.c b/drivers/usb/host/xhci-mtk.c index 3838a990ec3..63dfb793c6b 100644 --- a/drivers/usb/host/xhci-mtk.c +++ b/drivers/usb/host/xhci-mtk.c @@ -14,8 +14,9 @@ #include <power/regulator.h> #include <usb.h> #include <usb/xhci.h> -#include <linux/errno.h> +#include <linux/bitfield.h> #include <linux/compat.h> +#include <linux/errno.h> #include <linux/iopoll.h> /* IPPC (IP Port Control) registers */ @@ -50,6 +51,25 @@ #define IPPC_U3_CTRL(p) (IPPC_U3_CTRL_0P + ((p) * 0x08)) #define IPPC_U2_CTRL(p) (IPPC_U2_CTRL_0P + ((p) * 0x08)) +/* xHCI CSR */ +#define LS_EOF_CFG 0x930 +#define LSEOF_OFFSET 0x89 + +#define FS_EOF_CFG 0x934 +#define FSEOF_OFFSET 0x2e + +#define SS_GEN1_EOF_CFG 0x93c +#define SSG1EOF_OFFSET 0x78 + +#define HFCNTR_CFG 0x944 +#define ITP_DELTA_CLK_MASK GENMASK(5, 1) +#define FRMCNT_LEV1_RANG_MASK GENMASK(19, 8) + +#define SS_GEN2_EOF_CFG 0x990 +#define SSG2EOF_OFFSET 0x3c + +#define XSEOF_OFFSET_MASK GENMASK(11, 0) + struct mtk_xhci { struct xhci_ctrl ctrl; /* Needs to come first in this struct! */ struct xhci_hccr *hcd; @@ -65,6 +85,30 @@ struct mtk_xhci { u32 u2p_dis_msk; }; +/* + * workaround for mt8195: + * MT8195 has 4 controllers, the controller1~3's default SOF/ITP interval + * is calculated from the frame counter clock 24M, but in fact, the clock + * is 48M. + */ +static void xhci_mtk_set_frame_interval(struct mtk_xhci *mtk) +{ + void __iomem *mac = (void __iomem *)mtk->hcd; + + if (!ofnode_device_is_compatible(dev_ofnode(mtk->dev), "mediatek,mt8195-xhci")) + return; + + clrsetbits_le32(mac + HFCNTR_CFG, + ITP_DELTA_CLK_MASK | FRMCNT_LEV1_RANG_MASK, + FIELD_PREP(ITP_DELTA_CLK_MASK, 0xa) | + FIELD_PREP(FRMCNT_LEV1_RANG_MASK, 0x12b)); + + clrsetbits_le32(mac + LS_EOF_CFG, XSEOF_OFFSET_MASK, LSEOF_OFFSET); + clrsetbits_le32(mac + FS_EOF_CFG, XSEOF_OFFSET_MASK, FSEOF_OFFSET); + clrsetbits_le32(mac + SS_GEN1_EOF_CFG, XSEOF_OFFSET_MASK, SSG1EOF_OFFSET); + clrsetbits_le32(mac + SS_GEN2_EOF_CFG, XSEOF_OFFSET_MASK, SSG2EOF_OFFSET); +} + static int xhci_mtk_host_enable(struct mtk_xhci *mtk) { int u3_ports_disabed = 0; @@ -278,6 +322,8 @@ static int xhci_mtk_probe(struct udevice *dev) if (ret) goto ssusb_init_err; + xhci_mtk_set_frame_interval(mtk); + mtk->ctrl.quirks = XHCI_MTK_HOST; hcor = (struct xhci_hcor *)((uintptr_t)mtk->hcd + HC_LENGTH(xhci_readl(&mtk->hcd->cr_capbase))); @@ -308,6 +354,7 @@ static int xhci_mtk_remove(struct udevice *dev) static const struct udevice_id xhci_mtk_ids[] = { { .compatible = "mediatek,mtk-xhci" }, + { .compatible = "mediatek,mt8195-xhci" }, { } }; diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 2a76d19cc8e..60f4a4bf9cc 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -16,6 +16,35 @@ config VIDEO if VIDEO +config VIDEO_FONT_4X6 + bool "4 x 6 font size" + help + Font for video console driver, 4 x 6 pixels. + Provides character bitmap data in header file. + When selecting multiple fonts, you may want to enable CMD_SELECT_FONT too. + +config VIDEO_FONT_8X16 + bool "8 x 16 font size" + default y + help + Font for video console driver, 8 x 16 pixels + Provides character bitmap data in header file. + When selecting multiple fonts, you may want to enable CMD_SELECT_FONT too. + +config VIDEO_FONT_SUN12X22 + bool "12 x 22 font size" + help + Font for video console driver, 12 x 22 pixels + Provides character bitmap data in header file. + When selecting multiple fonts, you may want to enable CMD_SELECT_FONT too. + +config VIDEO_FONT_16X32 + bool "16 x 32 font size" + help + Font for video console driver, 16 x 32 pixels + Provides character bitmap data in header file. + When selecting multiple fonts, you may want to enable CMD_SELECT_FONT too. + config VIDEO_LOGO bool "Show the U-Boot logo on the display" default y if !SPLASH_SCREEN @@ -150,6 +179,7 @@ config CONSOLE_ROTATION config CONSOLE_TRUETYPE bool "Support a console that uses TrueType fonts" + select CMD_SELECT_FONT help TrueTrype fonts can provide outline-drawing capability rather than needing to provide a bitmap for each font and size that is needed. diff --git a/drivers/video/Makefile b/drivers/video/Makefile index cdb7d9a54d4..cb3f3736459 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -9,6 +9,12 @@ obj-$(CONFIG_BACKLIGHT_GPIO) += backlight_gpio.o obj-$(CONFIG_BACKLIGHT_PWM) += pwm_backlight.o obj-$(CONFIG_CONSOLE_NORMAL) += console_normal.o obj-$(CONFIG_CONSOLE_ROTATION) += console_rotate.o +ifdef CONFIG_CONSOLE_NORMAL +obj-y += console_core.o +else ifdef CONFIG_CONSOLE_ROTATION +obj-y += console_core.o +endif +obj-$(CONFIG_CONSOLE_ROTATION) += console_core.o obj-$(CONFIG_CONSOLE_TRUETYPE) += console_truetype.o fonts/ obj-$(CONFIG_DISPLAY) += display-uclass.o obj-$(CONFIG_VIDEO_MIPI_DSI) += dsi-host-uclass.o diff --git a/drivers/video/console_core.c b/drivers/video/console_core.c new file mode 100644 index 00000000000..d4f79c656a9 --- /dev/null +++ b/drivers/video/console_core.c @@ -0,0 +1,212 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2015 Google, Inc + * (C) Copyright 2015 + * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com + * (C) Copyright 2023 Dzmitry Sankouski <dsankouski@gmail.com> + */ + +#include <video.h> +#include <video_console.h> +#include <dm.h> +#include <video_font.h> +#include "vidconsole_internal.h" + +/** + * console_set_font() - prepare vidconsole for chosen font. + * + * @dev vidconsole device + * @fontdata pointer to font data struct + */ +static int console_set_font(struct udevice *dev, struct video_fontdata *fontdata) +{ + struct console_simple_priv *priv = dev_get_priv(dev); + struct vidconsole_priv *vc_priv = dev_get_uclass_priv(dev); + struct video_priv *vid_priv = dev_get_uclass_priv(dev->parent); + + debug("console_simple: setting %s font\n", fontdata->name); + debug("width: %d\n", fontdata->width); + debug("byte width: %d\n", fontdata->byte_width); + debug("height: %d\n", fontdata->height); + + priv->fontdata = fontdata; + vc_priv->x_charsize = fontdata->width; + vc_priv->y_charsize = fontdata->height; + if (vid_priv->rot % 2) { + vc_priv->cols = vid_priv->ysize / fontdata->width; + vc_priv->rows = vid_priv->xsize / fontdata->height; + vc_priv->xsize_frac = VID_TO_POS(vid_priv->ysize); + } else { + vc_priv->cols = vid_priv->xsize / fontdata->width; + vc_priv->rows = vid_priv->ysize / fontdata->height; + } + + return 0; +} + +int check_bpix_support(int bpix) +{ + if (bpix == VIDEO_BPP8 && IS_ENABLED(CONFIG_VIDEO_BPP8)) + return 0; + else if (bpix == VIDEO_BPP16 && IS_ENABLED(CONFIG_VIDEO_BPP16)) + return 0; + else if (bpix == VIDEO_BPP32 && IS_ENABLED(CONFIG_VIDEO_BPP32)) + return 0; + else + return -ENOSYS; +} + +inline void fill_pixel_and_goto_next(void **dstp, u32 value, int pbytes, int step) +{ + u8 *dst_byte = *dstp; + + if (pbytes == 4) { + u32 *dst = *dstp; + *dst = value; + } + if (pbytes == 2) { + u16 *dst = *dstp; + *dst = value; + } + if (pbytes == 1) { + u8 *dst = *dstp; + *dst = value; + } + *dstp = dst_byte + step; +} + +int fill_char_vertically(uchar *pfont, void **line, struct video_priv *vid_priv, + struct video_fontdata *fontdata, bool direction) +{ + int step, line_step, pbytes, bitcount, width_remainder, ret; + void *dst; + + ret = check_bpix_support(vid_priv->bpix); + if (ret) + return ret; + + pbytes = VNBYTES(vid_priv->bpix); + if (direction) { + step = -pbytes; + line_step = -vid_priv->line_length; + } else { + step = pbytes; + line_step = vid_priv->line_length; + } + + width_remainder = fontdata->width % 8; + for (int row = 0; row < fontdata->height; row++) { + uchar bits; + + bitcount = 8; + dst = *line; + for (int col = 0; col < fontdata->byte_width; col++) { + if (width_remainder) { + bool is_last_col = (fontdata->byte_width - col == 1); + + if (is_last_col) + bitcount = width_remainder; + } + bits = pfont[col]; + + for (int bit = 0; bit < bitcount; bit++) { + u32 value = (bits & 0x80) ? + vid_priv->colour_fg : + vid_priv->colour_bg; + + fill_pixel_and_goto_next(&dst, + value, + pbytes, + step + ); + bits <<= 1; + } + } + *line += line_step; + pfont += fontdata->byte_width; + } + return ret; +} + +int fill_char_horizontally(uchar *pfont, void **line, struct video_priv *vid_priv, + struct video_fontdata *fontdata, bool direction) +{ + int step, line_step, pbytes, bitcount = 8, width_remainder, ret; + void *dst; + u8 mask; + + ret = check_bpix_support(vid_priv->bpix); + if (ret) + return ret; + + pbytes = VNBYTES(vid_priv->bpix); + if (direction) { + step = -pbytes; + line_step = vid_priv->line_length; + } else { + step = pbytes; + line_step = -vid_priv->line_length; + } + + width_remainder = fontdata->width % 8; + for (int col = 0; col < fontdata->byte_width; col++) { + mask = 0x80; + if (width_remainder) { + bool is_last_col = (fontdata->byte_width - col == 1); + + if (is_last_col) + bitcount = width_remainder; + } + for (int bit = 0; bit < bitcount; bit++) { + dst = *line; + for (int row = 0; row < fontdata->height; row++) { + u32 value = (pfont[row * fontdata->byte_width + col] + & mask) ? vid_priv->colour_fg : vid_priv->colour_bg; + + fill_pixel_and_goto_next(&dst, + value, + pbytes, + step + ); + } + *line += line_step; + mask >>= 1; + } + } + return ret; +} + +int console_probe(struct udevice *dev) +{ + return console_set_font(dev, fonts); +} + +const char *console_simple_get_font_size(struct udevice *dev, uint *sizep) +{ + struct console_simple_priv *priv = dev_get_priv(dev); + + *sizep = priv->fontdata->width; + + return priv->fontdata->name; +} + +int console_simple_get_font(struct udevice *dev, int seq, struct vidfont_info *info) +{ + info->name = fonts[seq].name; + + return 0; +} + +int console_simple_select_font(struct udevice *dev, const char *name, uint size) +{ + struct video_fontdata *font; + + for (font = fonts; font->name; font++) { + if (!strcmp(name, font->name)) { + console_set_font(dev, font); + return 0; + } + }; + printf("no such font: %s, make sure it's name has <width>x<height> format\n", name); + return -ENOENT; +} diff --git a/drivers/video/console_normal.c b/drivers/video/console_normal.c index 04f022491e5..413c7abee9e 100644 --- a/drivers/video/console_normal.c +++ b/drivers/video/console_normal.c @@ -1,10 +1,9 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (c) 2015 Google, Inc - * (C) Copyright 2001-2015 - * DENX Software Engineering -- wd@denx.de - * Compulab Ltd - http://compulab.co.il/ + * (C) Copyright 2015 * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com + * (C) Copyright 2023 Dzmitry Sankouski <dsankouski@gmail.com> */ #include <common.h> @@ -12,47 +11,30 @@ #include <video.h> #include <video_console.h> #include <video_font.h> /* Get font data, width and height */ +#include "vidconsole_internal.h" -static int console_normal_set_row(struct udevice *dev, uint row, int clr) +static int console_set_row(struct udevice *dev, uint row, int clr) { struct video_priv *vid_priv = dev_get_uclass_priv(dev->parent); - void *line, *end; - int pixels = VIDEO_FONT_HEIGHT * vid_priv->xsize; + struct console_simple_priv *priv = dev_get_priv(dev); + struct video_fontdata *fontdata = priv->fontdata; + void *line, *dst, *end; + int pixels = fontdata->height * vid_priv->xsize; int ret; int i; + int pbytes; + + ret = check_bpix_support(vid_priv->bpix); + if (ret) + return ret; + + line = vid_priv->fb + row * fontdata->height * vid_priv->line_length; + dst = line; + pbytes = VNBYTES(vid_priv->bpix); + for (i = 0; i < pixels; i++) + fill_pixel_and_goto_next(&dst, clr, pbytes, pbytes); + end = dst; - line = vid_priv->fb + row * VIDEO_FONT_HEIGHT * vid_priv->line_length; - switch (vid_priv->bpix) { - case VIDEO_BPP8: - if (IS_ENABLED(CONFIG_VIDEO_BPP8)) { - uint8_t *dst = line; - - for (i = 0; i < pixels; i++) - *dst++ = clr; - end = dst; - break; - } - case VIDEO_BPP16: - if (IS_ENABLED(CONFIG_VIDEO_BPP16)) { - uint16_t *dst = line; - - for (i = 0; i < pixels; i++) - *dst++ = clr; - end = dst; - break; - } - case VIDEO_BPP32: - if (IS_ENABLED(CONFIG_VIDEO_BPP32)) { - uint32_t *dst = line; - - for (i = 0; i < pixels; i++) - *dst++ = clr; - end = dst; - break; - } - default: - return -ENOSYS; - } ret = vidconsole_sync_copy(dev, line, end); if (ret) return ret; @@ -60,18 +42,20 @@ static int console_normal_set_row(struct udevice *dev, uint row, int clr) return 0; } -static int console_normal_move_rows(struct udevice *dev, uint rowdst, - uint rowsrc, uint count) +static int console_move_rows(struct udevice *dev, uint rowdst, + uint rowsrc, uint count) { struct video_priv *vid_priv = dev_get_uclass_priv(dev->parent); + struct console_simple_priv *priv = dev_get_priv(dev); + struct video_fontdata *fontdata = priv->fontdata; void *dst; void *src; int size; int ret; - dst = vid_priv->fb + rowdst * VIDEO_FONT_HEIGHT * vid_priv->line_length; - src = vid_priv->fb + rowsrc * VIDEO_FONT_HEIGHT * vid_priv->line_length; - size = VIDEO_FONT_HEIGHT * vid_priv->line_length * count; + dst = vid_priv->fb + rowdst * fontdata->height * vid_priv->line_length; + src = vid_priv->fb + rowsrc * fontdata->height * vid_priv->line_length; + size = fontdata->height * vid_priv->line_length * count; ret = vidconsole_memmove(dev, dst, src, size); if (ret) return ret; @@ -79,100 +63,53 @@ static int console_normal_move_rows(struct udevice *dev, uint rowdst, return 0; } -static int console_normal_putc_xy(struct udevice *dev, uint x_frac, uint y, - char ch) +static int console_putc_xy(struct udevice *dev, uint x_frac, uint y, char ch) { struct vidconsole_priv *vc_priv = dev_get_uclass_priv(dev); struct udevice *vid = dev->parent; struct video_priv *vid_priv = dev_get_uclass_priv(vid); - int i, row; - void *start; - void *line; - int ret; + struct console_simple_priv *priv = dev_get_priv(dev); + struct video_fontdata *fontdata = priv->fontdata; + int pbytes = VNBYTES(vid_priv->bpix); + int x, linenum, ret; + void *start, *line; + uchar *pfont = fontdata->video_fontdata + + (u8)ch * fontdata->char_pixel_bytes; - start = vid_priv->fb + y * vid_priv->line_length + - VID_TO_PIXEL(x_frac) * VNBYTES(vid_priv->bpix); + if (x_frac + VID_TO_POS(vc_priv->x_charsize) > vc_priv->xsize_frac) + return -EAGAIN; + linenum = y; + x = VID_TO_PIXEL(x_frac); + start = vid_priv->fb + linenum * vid_priv->line_length + x * pbytes; line = start; if (x_frac + VID_TO_POS(vc_priv->x_charsize) > vc_priv->xsize_frac) return -EAGAIN; - for (row = 0; row < VIDEO_FONT_HEIGHT; row++) { - unsigned int idx = (u8)ch * VIDEO_FONT_HEIGHT + row; - uchar bits = video_fontdata[idx]; - - switch (vid_priv->bpix) { - case VIDEO_BPP8: - if (IS_ENABLED(CONFIG_VIDEO_BPP8)) { - uint8_t *dst = line; - - for (i = 0; i < VIDEO_FONT_WIDTH; i++) { - *dst++ = (bits & 0x80) ? - vid_priv->colour_fg : - vid_priv->colour_bg; - bits <<= 1; - } - break; - } - case VIDEO_BPP16: - if (IS_ENABLED(CONFIG_VIDEO_BPP16)) { - uint16_t *dst = line; - - for (i = 0; i < VIDEO_FONT_WIDTH; i++) { - *dst++ = (bits & 0x80) ? - vid_priv->colour_fg : - vid_priv->colour_bg; - bits <<= 1; - } - break; - } - case VIDEO_BPP32: - if (IS_ENABLED(CONFIG_VIDEO_BPP32)) { - uint32_t *dst = line; - - for (i = 0; i < VIDEO_FONT_WIDTH; i++) { - *dst++ = (bits & 0x80) ? - vid_priv->colour_fg : - vid_priv->colour_bg; - bits <<= 1; - } - break; - } - default: - return -ENOSYS; - } - line += vid_priv->line_length; - } - ret = vidconsole_sync_copy(dev, start, line); + ret = fill_char_vertically(pfont, &line, vid_priv, fontdata, NORMAL_DIRECTION); if (ret) return ret; - return VID_TO_POS(VIDEO_FONT_WIDTH); -} - -static int console_normal_probe(struct udevice *dev) -{ - struct vidconsole_priv *vc_priv = dev_get_uclass_priv(dev); - struct udevice *vid_dev = dev->parent; - struct video_priv *vid_priv = dev_get_uclass_priv(vid_dev); - - vc_priv->x_charsize = VIDEO_FONT_WIDTH; - vc_priv->y_charsize = VIDEO_FONT_HEIGHT; - vc_priv->cols = vid_priv->xsize / VIDEO_FONT_WIDTH; - vc_priv->rows = vid_priv->ysize / VIDEO_FONT_HEIGHT; + ret = vidconsole_sync_copy(dev, start, line); + if (ret) + return ret; - return 0; + return VID_TO_POS(fontdata->width); } -struct vidconsole_ops console_normal_ops = { - .putc_xy = console_normal_putc_xy, - .move_rows = console_normal_move_rows, - .set_row = console_normal_set_row, +struct vidconsole_ops console_ops = { + .putc_xy = console_putc_xy, + .move_rows = console_move_rows, + .set_row = console_set_row, + .get_font_size = console_simple_get_font_size, + .get_font = console_simple_get_font, + .select_font = console_simple_select_font, }; U_BOOT_DRIVER(vidconsole_normal) = { - .name = "vidconsole0", - .id = UCLASS_VIDEO_CONSOLE, - .ops = &console_normal_ops, - .probe = console_normal_probe, + .name = "vidconsole0", + .id = UCLASS_VIDEO_CONSOLE, + .ops = &console_ops, + .probe = console_probe, + .priv_auto = sizeof(struct console_simple_priv), }; diff --git a/drivers/video/console_rotate.c b/drivers/video/console_rotate.c index 36c8d0609d8..65358a1c6e7 100644 --- a/drivers/video/console_rotate.c +++ b/drivers/video/console_rotate.c @@ -3,6 +3,7 @@ * Copyright (c) 2015 Google, Inc * (C) Copyright 2015 * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com + * (C) Copyright 2023 Dzmitry Sankouski <dsankouski@gmail.com> */ #include <common.h> @@ -10,47 +11,25 @@ #include <video.h> #include <video_console.h> #include <video_font.h> /* Get font data, width and height */ +#include "vidconsole_internal.h" static int console_set_row_1(struct udevice *dev, uint row, int clr) { struct video_priv *vid_priv = dev_get_uclass_priv(dev->parent); + struct console_simple_priv *priv = dev_get_priv(dev); + struct video_fontdata *fontdata = priv->fontdata; int pbytes = VNBYTES(vid_priv->bpix); - void *start, *line; + void *start, *dst, *line; int i, j; int ret; start = vid_priv->fb + vid_priv->line_length - - (row + 1) * VIDEO_FONT_HEIGHT * pbytes; + (row + 1) * fontdata->height * pbytes; line = start; for (j = 0; j < vid_priv->ysize; j++) { - switch (vid_priv->bpix) { - case VIDEO_BPP8: - if (IS_ENABLED(CONFIG_VIDEO_BPP8)) { - uint8_t *dst = line; - - for (i = 0; i < VIDEO_FONT_HEIGHT; i++) - *dst++ = clr; - break; - } - case VIDEO_BPP16: - if (IS_ENABLED(CONFIG_VIDEO_BPP16)) { - uint16_t *dst = line; - - for (i = 0; i < VIDEO_FONT_HEIGHT; i++) - *dst++ = clr; - break; - } - case VIDEO_BPP32: - if (IS_ENABLED(CONFIG_VIDEO_BPP32)) { - uint32_t *dst = line; - - for (i = 0; i < VIDEO_FONT_HEIGHT; i++) - *dst++ = clr; - break; - } - default: - return -ENOSYS; - } + dst = line; + for (i = 0; i < fontdata->height; i++) + fill_pixel_and_goto_next(&dst, clr, pbytes, pbytes); line += vid_priv->line_length; } ret = vidconsole_sync_copy(dev, start, line); @@ -61,22 +40,24 @@ static int console_set_row_1(struct udevice *dev, uint row, int clr) } static int console_move_rows_1(struct udevice *dev, uint rowdst, uint rowsrc, - uint count) + uint count) { struct video_priv *vid_priv = dev_get_uclass_priv(dev->parent); + struct console_simple_priv *priv = dev_get_priv(dev); + struct video_fontdata *fontdata = priv->fontdata; int pbytes = VNBYTES(vid_priv->bpix); void *dst; void *src; int j, ret; dst = vid_priv->fb + vid_priv->line_length - - (rowdst + count) * VIDEO_FONT_HEIGHT * pbytes; + (rowdst + count) * fontdata->height * pbytes; src = vid_priv->fb + vid_priv->line_length - - (rowsrc + count) * VIDEO_FONT_HEIGHT * pbytes; + (rowsrc + count) * fontdata->height * pbytes; for (j = 0; j < vid_priv->ysize; j++) { ret = vidconsole_memmove(dev, dst, src, - VIDEO_FONT_HEIGHT * pbytes * count); + fontdata->height * pbytes * count); if (ret) return ret; src += vid_priv->line_length; @@ -91,110 +72,51 @@ static int console_putc_xy_1(struct udevice *dev, uint x_frac, uint y, char ch) struct vidconsole_priv *vc_priv = dev_get_uclass_priv(dev); struct udevice *vid = dev->parent; struct video_priv *vid_priv = dev_get_uclass_priv(vid); - uchar *pfont = video_fontdata + (u8)ch * VIDEO_FONT_HEIGHT; + struct console_simple_priv *priv = dev_get_priv(dev); + struct video_fontdata *fontdata = priv->fontdata; int pbytes = VNBYTES(vid_priv->bpix); - int i, col, x, linenum, ret; - int mask = 0x80; + int x, linenum, ret; void *start, *line; + uchar *pfont = fontdata->video_fontdata + + (u8)ch * fontdata->char_pixel_bytes; + if (x_frac + VID_TO_POS(vc_priv->x_charsize) > vc_priv->xsize_frac) + return -EAGAIN; linenum = VID_TO_PIXEL(x_frac) + 1; x = y + 1; start = vid_priv->fb + linenum * vid_priv->line_length - x * pbytes; line = start; - if (x_frac + VID_TO_POS(vc_priv->x_charsize) > vc_priv->xsize_frac) - return -EAGAIN; - for (col = 0; col < VIDEO_FONT_HEIGHT; col++) { - switch (vid_priv->bpix) { - case VIDEO_BPP8: - if (IS_ENABLED(CONFIG_VIDEO_BPP8)) { - uint8_t *dst = line; - - for (i = 0; i < VIDEO_FONT_HEIGHT; i++) { - *dst-- = (pfont[i] & mask) ? - vid_priv->colour_fg : - vid_priv->colour_bg; - } - break; - } - case VIDEO_BPP16: - if (IS_ENABLED(CONFIG_VIDEO_BPP16)) { - uint16_t *dst = line; - - for (i = 0; i < VIDEO_FONT_HEIGHT; i++) { - *dst-- = (pfont[i] & mask) ? - vid_priv->colour_fg : - vid_priv->colour_bg; - } - break; - } - case VIDEO_BPP32: - if (IS_ENABLED(CONFIG_VIDEO_BPP32)) { - uint32_t *dst = line; - - for (i = 0; i < VIDEO_FONT_HEIGHT; i++) { - *dst-- = (pfont[i] & mask) ? - vid_priv->colour_fg : - vid_priv->colour_bg; - } - break; - } - default: - return -ENOSYS; - } - line += vid_priv->line_length; - mask >>= 1; - } + ret = fill_char_horizontally(pfont, &line, vid_priv, fontdata, FLIPPED_DIRECTION); + if (ret) + return ret; + /* We draw backwards from 'start, so account for the first line */ ret = vidconsole_sync_copy(dev, start - vid_priv->line_length, line); if (ret) return ret; - return VID_TO_POS(VIDEO_FONT_WIDTH); + return VID_TO_POS(fontdata->width); } static int console_set_row_2(struct udevice *dev, uint row, int clr) { struct video_priv *vid_priv = dev_get_uclass_priv(dev->parent); - void *start, *line, *end; - int pixels = VIDEO_FONT_HEIGHT * vid_priv->xsize; + struct console_simple_priv *priv = dev_get_priv(dev); + struct video_fontdata *fontdata = priv->fontdata; + void *start, *line, *dst, *end; + int pixels = fontdata->height * vid_priv->xsize; int i, ret; + int pbytes = VNBYTES(vid_priv->bpix); start = vid_priv->fb + vid_priv->ysize * vid_priv->line_length - - (row + 1) * VIDEO_FONT_HEIGHT * vid_priv->line_length; + (row + 1) * fontdata->height * vid_priv->line_length; line = start; - switch (vid_priv->bpix) { - case VIDEO_BPP8: - if (IS_ENABLED(CONFIG_VIDEO_BPP8)) { - uint8_t *dst = line; - - for (i = 0; i < pixels; i++) - *dst++ = clr; - end = dst; - break; - } - case VIDEO_BPP16: - if (IS_ENABLED(CONFIG_VIDEO_BPP16)) { - uint16_t *dst = line; - - for (i = 0; i < pixels; i++) - *dst++ = clr; - end = dst; - break; - } - case VIDEO_BPP32: - if (IS_ENABLED(CONFIG_VIDEO_BPP32)) { - uint32_t *dst = line; - - for (i = 0; i < pixels; i++) - *dst++ = clr; - end = dst; - break; - } - default: - return -ENOSYS; - } + dst = line; + for (i = 0; i < pixels; i++) + fill_pixel_and_goto_next(&dst, clr, pbytes, pbytes); + end = dst; ret = vidconsole_sync_copy(dev, start, end); if (ret) return ret; @@ -206,17 +128,19 @@ static int console_move_rows_2(struct udevice *dev, uint rowdst, uint rowsrc, uint count) { struct video_priv *vid_priv = dev_get_uclass_priv(dev->parent); + struct console_simple_priv *priv = dev_get_priv(dev); + struct video_fontdata *fontdata = priv->fontdata; void *dst; void *src; void *end; end = vid_priv->fb + vid_priv->ysize * vid_priv->line_length; - dst = end - (rowdst + count) * VIDEO_FONT_HEIGHT * + dst = end - (rowdst + count) * fontdata->height * vid_priv->line_length; - src = end - (rowsrc + count) * VIDEO_FONT_HEIGHT * + src = end - (rowsrc + count) * fontdata->height * vid_priv->line_length; vidconsole_memmove(dev, dst, src, - VIDEO_FONT_HEIGHT * vid_priv->line_length * count); + fontdata->height * vid_priv->line_length * count); return 0; } @@ -226,9 +150,13 @@ static int console_putc_xy_2(struct udevice *dev, uint x_frac, uint y, char ch) struct vidconsole_priv *vc_priv = dev_get_uclass_priv(dev); struct udevice *vid = dev->parent; struct video_priv *vid_priv = dev_get_uclass_priv(vid); + struct console_simple_priv *priv = dev_get_priv(dev); + struct video_fontdata *fontdata = priv->fontdata; int pbytes = VNBYTES(vid_priv->bpix); - int i, row, x, linenum, ret; + int linenum, x, ret; void *start, *line; + uchar *pfont = fontdata->video_fontdata + + (u8)ch * fontdata->char_pixel_bytes; if (x_frac + VID_TO_POS(vc_priv->x_charsize) > vc_priv->xsize_frac) return -EAGAIN; @@ -237,98 +165,33 @@ static int console_putc_xy_2(struct udevice *dev, uint x_frac, uint y, char ch) start = vid_priv->fb + linenum * vid_priv->line_length + x * pbytes; line = start; - for (row = 0; row < VIDEO_FONT_HEIGHT; row++) { - unsigned int idx = (u8)ch * VIDEO_FONT_HEIGHT + row; - uchar bits = video_fontdata[idx]; - - switch (vid_priv->bpix) { - case VIDEO_BPP8: - if (IS_ENABLED(CONFIG_VIDEO_BPP8)) { - uint8_t *dst = line; - - for (i = 0; i < VIDEO_FONT_WIDTH; i++) { - *dst-- = (bits & 0x80) ? - vid_priv->colour_fg : - vid_priv->colour_bg; - bits <<= 1; - } - break; - } - case VIDEO_BPP16: - if (IS_ENABLED(CONFIG_VIDEO_BPP16)) { - uint16_t *dst = line; - - for (i = 0; i < VIDEO_FONT_WIDTH; i++) { - *dst-- = (bits & 0x80) ? - vid_priv->colour_fg : - vid_priv->colour_bg; - bits <<= 1; - } - break; - } - case VIDEO_BPP32: - if (IS_ENABLED(CONFIG_VIDEO_BPP32)) { - uint32_t *dst = line; - - for (i = 0; i < VIDEO_FONT_WIDTH; i++) { - *dst-- = (bits & 0x80) ? - vid_priv->colour_fg : - vid_priv->colour_bg; - bits <<= 1; - } - break; - } - default: - return -ENOSYS; - } - line -= vid_priv->line_length; - } + ret = fill_char_vertically(pfont, &line, vid_priv, fontdata, FLIPPED_DIRECTION); + if (ret) + return ret; + /* Add 4 bytes to allow for the first pixel writen */ ret = vidconsole_sync_copy(dev, start + 4, line); if (ret) return ret; - return VID_TO_POS(VIDEO_FONT_WIDTH); + return VID_TO_POS(fontdata->width); } static int console_set_row_3(struct udevice *dev, uint row, int clr) { struct video_priv *vid_priv = dev_get_uclass_priv(dev->parent); + struct console_simple_priv *priv = dev_get_priv(dev); + struct video_fontdata *fontdata = priv->fontdata; int pbytes = VNBYTES(vid_priv->bpix); - void *start, *line; + void *start, *dst, *line; int i, j, ret; - start = vid_priv->fb + row * VIDEO_FONT_HEIGHT * pbytes; + start = vid_priv->fb + row * fontdata->height * pbytes; line = start; for (j = 0; j < vid_priv->ysize; j++) { - switch (vid_priv->bpix) { - case VIDEO_BPP8: - if (IS_ENABLED(CONFIG_VIDEO_BPP8)) { - uint8_t *dst = line; - - for (i = 0; i < VIDEO_FONT_HEIGHT; i++) - *dst++ = clr; - break; - } - case VIDEO_BPP16: - if (IS_ENABLED(CONFIG_VIDEO_BPP16)) { - uint16_t *dst = line; - - for (i = 0; i < VIDEO_FONT_HEIGHT; i++) - *dst++ = clr; - break; - } - case VIDEO_BPP32: - if (IS_ENABLED(CONFIG_VIDEO_BPP32)) { - uint32_t *dst = line; - - for (i = 0; i < VIDEO_FONT_HEIGHT; i++) - *dst++ = clr; - break; - } - default: - return -ENOSYS; - } + dst = line; + for (i = 0; i < fontdata->height; i++) + fill_pixel_and_goto_next(&dst, clr, pbytes, pbytes); line += vid_priv->line_length; } ret = vidconsole_sync_copy(dev, start, line); @@ -342,17 +205,19 @@ static int console_move_rows_3(struct udevice *dev, uint rowdst, uint rowsrc, uint count) { struct video_priv *vid_priv = dev_get_uclass_priv(dev->parent); + struct console_simple_priv *priv = dev_get_priv(dev); + struct video_fontdata *fontdata = priv->fontdata; int pbytes = VNBYTES(vid_priv->bpix); void *dst; void *src; int j, ret; - dst = vid_priv->fb + rowdst * VIDEO_FONT_HEIGHT * pbytes; - src = vid_priv->fb + rowsrc * VIDEO_FONT_HEIGHT * pbytes; + dst = vid_priv->fb + rowdst * fontdata->height * pbytes; + src = vid_priv->fb + rowsrc * fontdata->height * pbytes; for (j = 0; j < vid_priv->ysize; j++) { ret = vidconsole_memmove(dev, dst, src, - VIDEO_FONT_HEIGHT * pbytes * count); + fontdata->height * pbytes * count); if (ret) return ret; src += vid_priv->line_length; @@ -367,131 +232,79 @@ static int console_putc_xy_3(struct udevice *dev, uint x_frac, uint y, char ch) struct vidconsole_priv *vc_priv = dev_get_uclass_priv(dev); struct udevice *vid = dev->parent; struct video_priv *vid_priv = dev_get_uclass_priv(vid); - uchar *pfont = video_fontdata + (u8)ch * VIDEO_FONT_HEIGHT; + struct console_simple_priv *priv = dev_get_priv(dev); + struct video_fontdata *fontdata = priv->fontdata; int pbytes = VNBYTES(vid_priv->bpix); - int i, col, x, ret; - int mask = 0x80; + int linenum, x, ret; void *start, *line; + uchar *pfont = fontdata->video_fontdata + + (u8)ch * fontdata->char_pixel_bytes; if (x_frac + VID_TO_POS(vc_priv->x_charsize) > vc_priv->xsize_frac) return -EAGAIN; - x = vid_priv->ysize - VID_TO_PIXEL(x_frac) - 1; - start = vid_priv->fb + x * vid_priv->line_length + y * pbytes; + x = y; + linenum = vid_priv->ysize - VID_TO_PIXEL(x_frac) - 1; + start = vid_priv->fb + linenum * vid_priv->line_length + y * pbytes; line = start; - for (col = 0; col < VIDEO_FONT_HEIGHT; col++) { - switch (vid_priv->bpix) { - case VIDEO_BPP8: - if (IS_ENABLED(CONFIG_VIDEO_BPP8)) { - uint8_t *dst = line; - - for (i = 0; i < VIDEO_FONT_HEIGHT; i++) { - *dst++ = (pfont[i] & mask) ? - vid_priv->colour_fg : - vid_priv->colour_bg; - } - break; - } - case VIDEO_BPP16: - if (IS_ENABLED(CONFIG_VIDEO_BPP16)) { - uint16_t *dst = line; - - for (i = 0; i < VIDEO_FONT_HEIGHT; i++) { - *dst++ = (pfont[i] & mask) ? - vid_priv->colour_fg : - vid_priv->colour_bg; - } - break; - } - case VIDEO_BPP32: - if (IS_ENABLED(CONFIG_VIDEO_BPP32)) { - uint32_t *dst = line; - - for (i = 0; i < VIDEO_FONT_HEIGHT; i++) { - *dst++ = (pfont[i] & mask) ? - vid_priv->colour_fg : - vid_priv->colour_bg; - } - break; - } - default: - return -ENOSYS; - } - line -= vid_priv->line_length; - mask >>= 1; - } + + ret = fill_char_horizontally(pfont, &line, vid_priv, fontdata, NORMAL_DIRECTION); + if (ret) + return ret; /* Add a line to allow for the first pixels writen */ ret = vidconsole_sync_copy(dev, start + vid_priv->line_length, line); if (ret) return ret; - return VID_TO_POS(VIDEO_FONT_WIDTH); -} - - -static int console_probe_2(struct udevice *dev) -{ - struct vidconsole_priv *vc_priv = dev_get_uclass_priv(dev); - struct udevice *vid_dev = dev->parent; - struct video_priv *vid_priv = dev_get_uclass_priv(vid_dev); - - vc_priv->x_charsize = VIDEO_FONT_WIDTH; - vc_priv->y_charsize = VIDEO_FONT_HEIGHT; - vc_priv->cols = vid_priv->xsize / VIDEO_FONT_WIDTH; - vc_priv->rows = vid_priv->ysize / VIDEO_FONT_HEIGHT; - - return 0; -} - -static int console_probe_1_3(struct udevice *dev) -{ - struct vidconsole_priv *vc_priv = dev_get_uclass_priv(dev); - struct udevice *vid_dev = dev->parent; - struct video_priv *vid_priv = dev_get_uclass_priv(vid_dev); - - vc_priv->x_charsize = VIDEO_FONT_WIDTH; - vc_priv->y_charsize = VIDEO_FONT_HEIGHT; - vc_priv->cols = vid_priv->ysize / VIDEO_FONT_WIDTH; - vc_priv->rows = vid_priv->xsize / VIDEO_FONT_HEIGHT; - vc_priv->xsize_frac = VID_TO_POS(vid_priv->ysize); - - return 0; + return VID_TO_POS(fontdata->width); } struct vidconsole_ops console_ops_1 = { .putc_xy = console_putc_xy_1, .move_rows = console_move_rows_1, .set_row = console_set_row_1, + .get_font_size = console_simple_get_font_size, + .get_font = console_simple_get_font, + .select_font = console_simple_select_font, }; struct vidconsole_ops console_ops_2 = { .putc_xy = console_putc_xy_2, .move_rows = console_move_rows_2, .set_row = console_set_row_2, + .get_font_size = console_simple_get_font_size, + .get_font = console_simple_get_font, + .select_font = console_simple_select_font, }; struct vidconsole_ops console_ops_3 = { .putc_xy = console_putc_xy_3, .move_rows = console_move_rows_3, .set_row = console_set_row_3, + .get_font_size = console_simple_get_font_size, + .get_font = console_simple_get_font, + .select_font = console_simple_select_font, }; U_BOOT_DRIVER(vidconsole_1) = { .name = "vidconsole1", .id = UCLASS_VIDEO_CONSOLE, .ops = &console_ops_1, - .probe = console_probe_1_3, + .probe = console_probe, + .priv_auto = sizeof(struct console_simple_priv), }; U_BOOT_DRIVER(vidconsole_2) = { .name = "vidconsole2", .id = UCLASS_VIDEO_CONSOLE, .ops = &console_ops_2, - .probe = console_probe_2, + .probe = console_probe, + .priv_auto = sizeof(struct console_simple_priv), }; U_BOOT_DRIVER(vidconsole_3) = { .name = "vidconsole3", .id = UCLASS_VIDEO_CONSOLE, .ops = &console_ops_3, - .probe = console_probe_1_3, + .probe = console_probe, + .priv_auto = sizeof(struct console_simple_priv), }; diff --git a/drivers/video/console_truetype.c b/drivers/video/console_truetype.c index 9cac9a6de4d..6b5390136a7 100644 --- a/drivers/video/console_truetype.c +++ b/drivers/video/console_truetype.c @@ -724,7 +724,7 @@ static int truetype_select_font(struct udevice *dev, const char *name, return 0; } -const char *vidconsole_get_font_size(struct udevice *dev, uint *sizep) +const char *console_truetype_get_font_size(struct udevice *dev, uint *sizep) { struct console_tt_priv *priv = dev_get_priv(dev); struct console_tt_metrics *met = priv->cur_met; @@ -773,6 +773,7 @@ struct vidconsole_ops console_truetype_ops = { .backspace = console_truetype_backspace, .entry_start = console_truetype_entry_start, .get_font = console_truetype_get_font, + .get_font_size = console_truetype_get_font_size, .select_font = truetype_select_font, }; diff --git a/drivers/video/coreboot.c b/drivers/video/coreboot.c index d2d87c75c89..c586475e41e 100644 --- a/drivers/video/coreboot.c +++ b/drivers/video/coreboot.c @@ -57,7 +57,7 @@ static int coreboot_video_probe(struct udevice *dev) goto err; } - ret = vesa_setup_video_priv(vesa, uc_priv, plat); + ret = vesa_setup_video_priv(vesa, vesa->phys_base_ptr, uc_priv, plat); if (ret) { ret = log_msg_ret("setup", ret); goto err; diff --git a/drivers/video/efi.c b/drivers/video/efi.c index b11e42c0ebf..28ac15ff61b 100644 --- a/drivers/video/efi.c +++ b/drivers/video/efi.c @@ -5,6 +5,8 @@ * EFI framebuffer driver based on GOP */ +#define LOG_CATEGORY LOGC_EFI + #include <common.h> #include <dm.h> #include <efi_api.h> @@ -50,7 +52,19 @@ static void efi_find_pixel_bits(u32 mask, u8 *pos, u8 *size) *size = len; } -static int get_mode_info(struct vesa_mode_info *vesa) +/** + * get_mode_info() - Ask EFI for the mode information + * + * Gets info from the graphics-output protocol + * + * @vesa: Place to put the mode information + * @fbp: Returns the address of the frame buffer + * @infop: Returns a pointer to the mode info + * Returns: 0 if OK, -ENOSYS if boot services are not available, -ENOTSUPP if + * the protocol is not supported by EFI + */ +static int get_mode_info(struct vesa_mode_info *vesa, u64 *fbp, + struct efi_gop_mode_info **infop) { efi_guid_t efi_gop_guid = EFI_GRAPHICS_OUTPUT_PROTOCOL_GUID; struct efi_boot_services *boot = efi_get_boot(); @@ -63,41 +77,70 @@ static int get_mode_info(struct vesa_mode_info *vesa) ret = boot->locate_protocol(&efi_gop_guid, NULL, (void **)&gop); if (ret) return log_msg_ret("prot", -ENOTSUPP); - mode = gop->mode; + log_debug("maxmode %u, mode %u, info %p, size %lx, fb %lx, fb_size %lx\n", + mode->max_mode, mode->mode, mode->info, mode->info_size, + (ulong)mode->fb_base, (ulong)mode->fb_size); + vesa->phys_base_ptr = mode->fb_base; + *fbp = mode->fb_base; vesa->x_resolution = mode->info->width; vesa->y_resolution = mode->info->height; + *infop = mode->info; return 0; } -static int save_vesa_mode(struct vesa_mode_info *vesa) +/** + * get_mode_from_entry() - Obtain fb info from the EFIET_GOP_MODE payload entry + * + * This gets the mode information provided by the stub to the payload and puts + * it into a vesa structure. It also returns the mode information. + * + * @vesa: Place to put the mode information + * @fbp: Returns the address of the frame buffer + * @infop: Returns a pointer to the mode info + * Returns: 0 if OK, -ve on error + */ +static int get_mode_from_entry(struct vesa_mode_info *vesa, u64 *fbp, + struct efi_gop_mode_info **infop) { - struct efi_entry_gopmode *mode; - const struct efi_framebuffer *fbinfo; + struct efi_gop_mode *mode; int size; int ret; - if (IS_ENABLED(CONFIG_EFI_APP)) { - ret = get_mode_info(vesa); - if (ret) { - printf("EFI graphics output protocol not found\n"); - return -ENXIO; - } - } else { - ret = efi_info_get(EFIET_GOP_MODE, (void **)&mode, &size); - if (ret == -ENOENT) { - printf("EFI graphics output protocol mode not found\n"); - return -ENXIO; - } - vesa->phys_base_ptr = mode->fb_base; - vesa->x_resolution = mode->info->width; - vesa->y_resolution = mode->info->height; + ret = efi_info_get(EFIET_GOP_MODE, (void **)&mode, &size); + if (ret) { + printf("EFI graphics output entry not found\n"); + return ret; } + vesa->phys_base_ptr = mode->fb_base; + *fbp = mode->fb_base; + vesa->x_resolution = mode->info->width; + vesa->y_resolution = mode->info->height; + *infop = mode->info; - if (mode->info->pixel_format < EFI_GOT_BITMASK) { - fbinfo = &efi_framebuffer_format_map[mode->info->pixel_format]; + return 0; +} + +static int save_vesa_mode(struct vesa_mode_info *vesa, u64 *fbp) +{ + const struct efi_framebuffer *fbinfo; + struct efi_gop_mode_info *info; + int ret; + + if (IS_ENABLED(CONFIG_EFI_APP)) + ret = get_mode_info(vesa, fbp, &info); + else + ret = get_mode_from_entry(vesa, fbp, &info); + if (ret) { + printf("EFI graphics output protocol not found (err=%dE)\n", + ret); + return ret; + } + + if (info->pixel_format < EFI_GOT_BITMASK) { + fbinfo = &efi_framebuffer_format_map[info->pixel_format]; vesa->red_mask_size = fbinfo->red.size; vesa->red_mask_pos = fbinfo->red.pos; vesa->green_mask_size = fbinfo->green.size; @@ -108,29 +151,28 @@ static int save_vesa_mode(struct vesa_mode_info *vesa) vesa->reserved_mask_pos = fbinfo->rsvd.pos; vesa->bits_per_pixel = 32; - vesa->bytes_per_scanline = mode->info->pixels_per_scanline * 4; - } else if (mode->info->pixel_format == EFI_GOT_BITMASK) { - efi_find_pixel_bits(mode->info->pixel_bitmask[0], + vesa->bytes_per_scanline = info->pixels_per_scanline * 4; + } else if (info->pixel_format == EFI_GOT_BITMASK) { + efi_find_pixel_bits(info->pixel_bitmask[0], &vesa->red_mask_pos, &vesa->red_mask_size); - efi_find_pixel_bits(mode->info->pixel_bitmask[1], + efi_find_pixel_bits(info->pixel_bitmask[1], &vesa->green_mask_pos, &vesa->green_mask_size); - efi_find_pixel_bits(mode->info->pixel_bitmask[2], + efi_find_pixel_bits(info->pixel_bitmask[2], &vesa->blue_mask_pos, &vesa->blue_mask_size); - efi_find_pixel_bits(mode->info->pixel_bitmask[3], + efi_find_pixel_bits(info->pixel_bitmask[3], &vesa->reserved_mask_pos, &vesa->reserved_mask_size); vesa->bits_per_pixel = vesa->red_mask_size + vesa->green_mask_size + vesa->blue_mask_size + vesa->reserved_mask_size; - vesa->bytes_per_scanline = (mode->info->pixels_per_scanline * + vesa->bytes_per_scanline = (info->pixels_per_scanline * vesa->bits_per_pixel) / 8; } else { - debug("efi set unknown framebuffer format: %d\n", - mode->info->pixel_format); + log_err("Unknown framebuffer format: %d\n", info->pixel_format); return -EINVAL; } @@ -142,19 +184,20 @@ static int efi_video_probe(struct udevice *dev) struct video_uc_plat *plat = dev_get_uclass_plat(dev); struct video_priv *uc_priv = dev_get_uclass_priv(dev); struct vesa_mode_info *vesa = &mode_info.vesa; + u64 fb; int ret; /* Initialize vesa_mode_info structure */ - ret = save_vesa_mode(vesa); + ret = save_vesa_mode(vesa, &fb); if (ret) goto err; - ret = vesa_setup_video_priv(vesa, uc_priv, plat); + ret = vesa_setup_video_priv(vesa, fb, uc_priv, plat); if (ret) goto err; - printf("Video: %dx%dx%d\n", uc_priv->xsize, uc_priv->ysize, - vesa->bits_per_pixel); + printf("Video: %dx%dx%d @ %lx\n", uc_priv->xsize, uc_priv->ysize, + vesa->bits_per_pixel, (ulong)fb); return 0; @@ -163,6 +206,30 @@ err: return ret; } +static int efi_video_bind(struct udevice *dev) +{ + if (IS_ENABLED(CONFIG_VIDEO_COPY)) { + struct video_uc_plat *plat = dev_get_uclass_plat(dev); + struct vesa_mode_info vesa; + int ret; + u64 fb; + + /* + * Initialise vesa_mode_info structure so we can figure out the + * required framebuffer size. If something goes wrong, just do + * without a copy framebuffer + */ + ret = save_vesa_mode(&vesa, &fb); + if (!ret) { + /* this is not reached if the EFI call failed */ + plat->copy_size = vesa.bytes_per_scanline * + vesa.y_resolution; + } + } + + return 0; +} + static const struct udevice_id efi_video_ids[] = { { .compatible = "efi-fb" }, { } @@ -172,5 +239,6 @@ U_BOOT_DRIVER(efi_video) = { .name = "efi_video", .id = UCLASS_VIDEO, .of_match = efi_video_ids, + .bind = efi_video_bind, .probe = efi_video_probe, }; diff --git a/drivers/video/vidconsole-uclass.c b/drivers/video/vidconsole-uclass.c index 72a13d30527..1225de23332 100644 --- a/drivers/video/vidconsole-uclass.c +++ b/drivers/video/vidconsole-uclass.c @@ -575,6 +575,17 @@ int vidconsole_get_font(struct udevice *dev, int seq, return ops->get_font(dev, seq, info); } +int vidconsole_get_font_size(struct udevice *dev, const char **name, uint *sizep) +{ + struct vidconsole_ops *ops = vidconsole_get_ops(dev); + + if (!ops->get_font_size) + return -ENOSYS; + + *name = ops->get_font_size(dev, sizep); + return 0; +} + int vidconsole_select_font(struct udevice *dev, const char *name, uint size) { struct vidconsole_ops *ops = vidconsole_get_ops(dev); @@ -645,6 +656,18 @@ int vidconsole_memmove(struct udevice *dev, void *dst, const void *src, } #endif +int vidconsole_clear_and_reset(struct udevice *dev) +{ + int ret; + + ret = video_clear(dev_get_parent(dev)); + if (ret) + return ret; + vidconsole_position_cursor(dev, 0, 0); + + return 0; +} + void vidconsole_position_cursor(struct udevice *dev, unsigned col, unsigned row) { struct vidconsole_priv *priv = dev_get_uclass_priv(dev); diff --git a/drivers/video/vidconsole_internal.h b/drivers/video/vidconsole_internal.h new file mode 100644 index 00000000000..c41edd45249 --- /dev/null +++ b/drivers/video/vidconsole_internal.h @@ -0,0 +1,120 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2015 Google, Inc + * (C) Copyright 2015 + * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com + * (C) Copyright 2023 Dzmitry Sankouski <dsankouski@gmail.com> + */ + +#define FLIPPED_DIRECTION 1 +#define NORMAL_DIRECTION 0 + +/** + * struct console_simple_priv - Private data for this driver + * + * @video_fontdata font graphical representation data + */ +struct console_simple_priv { + struct video_fontdata *fontdata; +}; + +/** + * Checks if bits per pixel supported. + * + * @param bpix framebuffer bits per pixel. + * + * @returns 0, if supported, or else -ENOSYS. + */ +int check_bpix_support(int bpix); + +/** + * Fill 1 pixel in framebuffer, and go to next one. + * + * @param dstp a pointer to pointer to framebuffer. + * @param value value to write to framebuffer. + * @param pbytes framebuffer bytes per pixel. + * @param step framebuffer pointer increment. Usually is equal to pbytes, + * and may be negative to control filling direction. + */ +void fill_pixel_and_goto_next(void **dstp, u32 value, int pbytes, int step); + +/** + * Fills 1 character in framebuffer vertically. Vertically means we're filling char font data rows + * across the lines. + * + * @param pfont a pointer to character font data. + * @param line a pointer to pointer to framebuffer. It's a point for upper left char corner + * @param vid_priv driver private data. + * @fontdata font graphical representation data + * @param direction controls character orientation. Can be normal or flipped. + * When normal: When flipped: + *|-----------------------------------------------| + *| line stepping | | + *| | | stepping -> | + *| * | | * * * | + *| * * v | * | + *| * | * | + *| * | * * ^ | + *| * * * | * | | + *| | | | + *| stepping -> | line stepping | + *|---!!we're starting from upper left char corner| + *|-----------------------------------------------| + * + * @returns 0, if success, or else error code. + */ +int fill_char_vertically(uchar *pfont, void **line, struct video_priv *vid_priv, + struct video_fontdata *fontdata, bool direction); + +/** + * Fills 1 character in framebuffer horizontally. + * Horizontally means we're filling char font data columns across the lines. + * + * @param pfont a pointer to character font data. + * @param line a pointer to pointer to framebuffer. It's a point for upper left char corner + * @param vid_priv driver private data. + * @fontdata font graphical representation data + * @param direction controls character orientation. Can be normal or flipped. + * When normal: When flipped: + *|-----------------------------------------------| + *| * | line stepping | + *| ^ * * * * * | | | + *| | * * | v * * | + *| | | * * * * * | + *| line stepping | * | + *| | | + *| stepping -> | <- stepping | + *|---!!we're starting from upper left char corner| + *|-----------------------------------------------| + * + * @returns 0, if success, or else error code. + */ +int fill_char_horizontally(uchar *pfont, void **line, struct video_priv *vid_priv, + struct video_fontdata *fontdata, bool direction); + +/** + * console probe function. + * + * @param dev a pointer to device. + * + * @returns 0, if success, or else error code. + */ +int console_probe(struct udevice *dev); + +/** + * Internal function to be used in as ops. + * See details in video_console.h get_font_size function + **/ +const char *console_simple_get_font_size(struct udevice *dev, uint *sizep); + +/** + * Internal function to be used in as ops. + * See details in video_console.h get_font function + **/ +int console_simple_get_font(struct udevice *dev, int seq, struct vidfont_info *info); + +/** + * Internal function to be used in as ops. + * See details in video_console.h select_font function + **/ +int console_simple_select_font(struct udevice *dev, const char *name, uint size); diff --git a/drivers/video/video-uclass.c b/drivers/video/video-uclass.c index 6aaacff10df..da89f431441 100644 --- a/drivers/video/video-uclass.c +++ b/drivers/video/video-uclass.c @@ -78,24 +78,40 @@ void video_set_flush_dcache(struct udevice *dev, bool flush) priv->flush_dcache = flush; } +static ulong alloc_fb_(ulong align, ulong size, ulong *addrp) +{ + ulong base; + + align = align ? align : 1 << 20; + base = *addrp - size; + base &= ~(align - 1); + size = *addrp - base; + *addrp = base; + + return size; +} + static ulong alloc_fb(struct udevice *dev, ulong *addrp) { struct video_uc_plat *plat = dev_get_uclass_plat(dev); - ulong base, align, size; + ulong size; + + if (!plat->size) { + if (IS_ENABLED(CONFIG_VIDEO_COPY) && plat->copy_size) { + size = alloc_fb_(plat->align, plat->copy_size, addrp); + plat->copy_base = *addrp; + return size; + } - if (!plat->size) return 0; + } /* Allow drivers to allocate the frame buffer themselves */ if (plat->base) return 0; - align = plat->align ? plat->align : 1 << 20; - base = *addrp - plat->size; - base &= ~(align - 1); - plat->base = base; - size = *addrp - base; - *addrp = base; + size = alloc_fb_(plat->align, plat->size, addrp); + plat->base = *addrp; return size; } @@ -529,8 +545,8 @@ static int video_post_bind(struct udevice *dev) addr = uc_priv->video_ptr; size = alloc_fb(dev, &addr); if (addr < gd->video_bottom) { - /* Device tree node may need the 'u-boot,dm-pre-reloc' or - * 'u-boot,dm-pre-proper' tag + /* Device tree node may need the 'bootph-all' or + * 'bootph-some-ram' tag */ printf("Video device '%s' cannot allocate frame buffer memory -ensure the device is set up before relocation\n", dev->name); |