diff options
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/clk/rockchip/clk_rk3399.c | 20 | ||||
| -rw-r--r-- | drivers/ram/rockchip/Kconfig | 21 | ||||
| -rw-r--r-- | drivers/ram/rockchip/sdram_px30.c | 8 | ||||
| -rw-r--r-- | drivers/video/rockchip/Kconfig | 4 | ||||
| -rw-r--r-- | drivers/video/rockchip/rk_edp.c | 6 |
5 files changed, 57 insertions, 2 deletions
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 1ea41f3c5b2..478d76d428c 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -233,6 +233,10 @@ enum { DCLK_VOP_DIV_CON_MASK = 0xff, DCLK_VOP_DIV_CON_SHIFT = 0, + /* CLKSEL_CON57 */ + PCLK_ALIVE_DIV_CON_SHIFT = 0, + PCLK_ALIVE_DIV_CON_MASK = 0x1f << PCLK_ALIVE_DIV_CON_SHIFT, + /* CLKSEL_CON58 */ CLK_SPI_PLL_SEL_WIDTH = 1, CLK_SPI_PLL_SEL_MASK = ((1 < CLK_SPI_PLL_SEL_WIDTH) - 1), @@ -867,6 +871,17 @@ static ulong rk3399_ddr_set_clk(struct rockchip_cru *cru, return set_rate; } +static ulong rk3399_alive_get_clk(struct rockchip_cru *cru) +{ + u32 div, val; + + val = readl(&cru->clksel_con[57]); + div = (val & PCLK_ALIVE_DIV_CON_MASK) >> + PCLK_ALIVE_DIV_CON_SHIFT; + + return DIV_TO_RATE(GPLL_HZ, div); +} + static ulong rk3399_saradc_get_clk(struct rockchip_cru *cru) { u32 div, val; @@ -936,6 +951,10 @@ static ulong rk3399_clk_get_rate(struct clk *clk) case ACLK_GIC_PRE: case PCLK_DDR: break; + case PCLK_ALIVE: + case PCLK_WDT: + rate = rk3399_alive_get_clk(priv->cru); + break; default: log_debug("Unknown clock %lu\n", clk->id); return -ENOENT; @@ -1502,6 +1521,7 @@ static ulong rk3399_pmuclk_get_rate(struct clk *clk) case PLL_PPLL: return PPLL_HZ; case PCLK_RKPWM_PMU: + case PCLK_WDT_M0_PMU: rate = rk3399_pwm_get_clk(priv->pmucru); break; case SCLK_I2C0_PMU: diff --git a/drivers/ram/rockchip/Kconfig b/drivers/ram/rockchip/Kconfig index 8e97c2f49e2..c459bbf5e24 100644 --- a/drivers/ram/rockchip/Kconfig +++ b/drivers/ram/rockchip/Kconfig @@ -22,6 +22,27 @@ config RAM_ROCKCHIP_DEBUG This is an option for developers to understand the ram drivers initialization, configurations and etc. +config RAM_PX30_DDR4 + bool "DDR3 support for Rockchip PX30" + depends on RAM_ROCKCHIP && ROCKCHIP_PX30 + help + This enables DDR4 sdram support instead of the default DDR3 support + on Rockchip PC30 SoCs. + +config RAM_PX30_LPDDR2 + bool "LPDDR2 support for Rockchip PX30" + depends on RAM_ROCKCHIP && ROCKCHIP_PX30 + help + This enables LPDDR2 sdram support instead of the default DDR3 support + on Rockchip PC30 SoCs. + +config RAM_PX30_LPDDR3 + bool "LPDDR3 support for Rockchip PX30" + depends on RAM_ROCKCHIP && ROCKCHIP_PX30 + help + This enables LPDDR3 sdram support instead of the default DDR3 support + on Rockchip PC30 SoCs. + config RAM_RK3399_LPDDR4 bool "LPDDR4 support for Rockchip RK3399" depends on RAM_ROCKCHIP && ROCKCHIP_RK3399 diff --git a/drivers/ram/rockchip/sdram_px30.c b/drivers/ram/rockchip/sdram_px30.c index fd5763d0a0d..2f1f6e9c0c4 100644 --- a/drivers/ram/rockchip/sdram_px30.c +++ b/drivers/ram/rockchip/sdram_px30.c @@ -125,7 +125,15 @@ u32 addrmap[][8] = { struct dram_info dram_info; struct px30_sdram_params sdram_configs[] = { +#if defined(CONFIG_RAM_PX30_DDR4) +#include "sdram-px30-ddr4-detect-333.inc" +#elif defined(CONFIG_RAM_PX30_LPDDR2) +#include "sdram-px30-lpddr2-detect-333.inc" +#elif defined(CONFIG_RAM_PX30_LPDDR3) +#include "sdram-px30-lpddr3-detect-333.inc" +#else #include "sdram-px30-ddr3-detect-333.inc" +#endif }; struct ddr_phy_skew skew = { diff --git a/drivers/video/rockchip/Kconfig b/drivers/video/rockchip/Kconfig index 5215a71f99f..0ade631bd5c 100644 --- a/drivers/video/rockchip/Kconfig +++ b/drivers/video/rockchip/Kconfig @@ -22,7 +22,7 @@ menuconfig VIDEO_ROCKCHIP config VIDEO_ROCKCHIP_MAX_XRES int "Maximum horizontal resolution (for memory allocation purposes)" depends on VIDEO_ROCKCHIP - default 3840 if ROCKCHIP_RK3399 && DISPLAY_ROCKCHIP_HDMI + default 3840 if DISPLAY_ROCKCHIP_HDMI default 1920 help The maximum horizontal resolution to support for the framebuffer. @@ -32,7 +32,7 @@ config VIDEO_ROCKCHIP_MAX_XRES config VIDEO_ROCKCHIP_MAX_YRES int "Maximum vertical resolution (for memory allocation purposes)" depends on VIDEO_ROCKCHIP - default 2160 if ROCKCHIP_RK3399 && DISPLAY_ROCKCHIP_HDMI + default 2160 if DISPLAY_ROCKCHIP_HDMI default 1080 help The maximum vertical resolution to support for the framebuffer. diff --git a/drivers/video/rockchip/rk_edp.c b/drivers/video/rockchip/rk_edp.c index 000bd481408..a032eb68895 100644 --- a/drivers/video/rockchip/rk_edp.c +++ b/drivers/video/rockchip/rk_edp.c @@ -559,6 +559,12 @@ static int rk_edp_link_train_ce(struct rk_edp_priv *edp) channel_eq = 0; for (tries = 0; tries < 5; tries++) { rk_edp_set_link_training(edp, edp->train_set); + ret = rk_edp_dpcd_write(regs, DPCD_TRAINING_LANE0_SET, + edp->train_set, + edp->link_train.lane_count); + if (ret) + return ret; + udelay(400); if (rk_edp_dpcd_read_link_status(edp, status) < 0) { |