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-rw-r--r--drivers/ddr/altera/sdram_arria10.c107
-rw-r--r--drivers/i2c/i2c-cdns.c78
-rw-r--r--drivers/i2c/rcar_i2c.c102
-rw-r--r--drivers/i2c/rcar_iic.c6
4 files changed, 165 insertions, 128 deletions
diff --git a/drivers/ddr/altera/sdram_arria10.c b/drivers/ddr/altera/sdram_arria10.c
index 29ea7492f30..1777e7e1a50 100644
--- a/drivers/ddr/altera/sdram_arria10.c
+++ b/drivers/ddr/altera/sdram_arria10.c
@@ -31,7 +31,6 @@ static u64 sdram_size_calc(void);
#define DDR_REG_CORE2SEQ 0xFFD05078
#define DDR_READ_LATENCY_DELAY 40
#define DDR_SIZE_2GB_HEX 0x80000000
-#define DDR_MAX_TRIES 0x00100000
#define IO48_MMR_DRAMSTS 0xFFCFA0EC
#define IO48_MMR_NIOS2_RESERVE0 0xFFCFA110
@@ -103,52 +102,18 @@ static int match_ddr_conf(u32 ddr_conf)
return 0;
}
-/* Check whether SDRAM is successfully Calibrated */
-static int is_sdram_cal_success(void)
-{
- return readl(&socfpga_ecc_hmc_base->ddrcalstat);
-}
-
-static unsigned char ddr_get_bit(u32 ereg, unsigned char bit)
-{
- u32 reg = readl(ereg);
-
- return (reg & BIT(bit)) ? 1 : 0;
-}
-
-static unsigned char ddr_wait_bit(u32 ereg, u32 bit,
- u32 expected, u32 timeout_usec)
-{
- u32 tmr;
-
- for (tmr = 0; tmr < timeout_usec; tmr += 100) {
- udelay(100);
- WATCHDOG_RESET();
- if (ddr_get_bit(ereg, bit) == expected)
- return 0;
- }
-
- return 1;
-}
-
static int emif_clear(void)
{
- u32 i = DDR_MAX_TRIES;
- u8 ret = 0;
-
writel(0, DDR_REG_CORE2SEQ);
- do {
- ret = !wait_for_bit_le32((u32 *)DDR_REG_SEQ2CORE,
- SEQ2CORE_MASK, 1, 50, 0);
- } while (ret && (--i > 0));
-
- return !i;
+ return wait_for_bit_le32((u32 *)DDR_REG_SEQ2CORE,
+ SEQ2CORE_MASK, 0, 1000, 0);
}
static int emif_reset(void)
{
u32 c2s, s2c;
+ int ret;
c2s = readl(DDR_REG_CORE2SEQ);
s2c = readl(DDR_REG_SEQ2CORE);
@@ -159,21 +124,28 @@ static int emif_reset(void)
readl(IO48_MMR_NIOS2_RESERVE2),
readl(IO48_MMR_DRAMSTS));
- if ((s2c & SEQ2CORE_MASK) && emif_clear()) {
- debug("failed emif_clear()\n");
- return -EPERM;
+ if (s2c & SEQ2CORE_MASK) {
+ ret = emif_clear();
+ if (ret) {
+ debug("failed emif_clear()\n");
+ return -EPERM;
+ }
}
writel(CORE2SEQ_INT_REQ, DDR_REG_CORE2SEQ);
- if (ddr_wait_bit(DDR_REG_SEQ2CORE, SEQ2CORE_INT_RESP_BIT, 0, 1000000)) {
+ ret = wait_for_bit_le32((u32 *)DDR_REG_SEQ2CORE,
+ SEQ2CORE_INT_RESP_BIT, false, 1000, false);
+ if (ret) {
debug("emif_reset failed to see interrupt acknowledge\n");
- return -EPERM;
- } else {
- debug("emif_reset interrupt acknowledged\n");
+ emif_clear();
+ return ret;
}
- if (emif_clear()) {
+ mdelay(1);
+
+ ret = emif_clear();
+ if (ret) {
debug("emif_clear() failed\n");
return -EPERM;
}
@@ -189,30 +161,23 @@ static int emif_reset(void)
static int ddr_setup(void)
{
- int i, j, ddr_setup_complete = 0;
-
- /* Try 3 times to do a calibration */
- for (i = 0; (i < 3) && !ddr_setup_complete; i++) {
- WATCHDOG_RESET();
-
- /* A delay to wait for calibration bit to set */
- for (j = 0; (j < 10) && !ddr_setup_complete; j++) {
- mdelay(500);
- ddr_setup_complete = is_sdram_cal_success();
- }
-
- if (!ddr_setup_complete)
- if (emif_reset())
- puts("Error: Failed to reset EMIF\n");
- }
+ int i, ret;
+
+ /* Try 32 times to do a calibration */
+ for (i = 0; i < 32; i++) {
+ mdelay(500);
+ ret = wait_for_bit_le32(&socfpga_ecc_hmc_base->ddrcalstat,
+ BIT(0), true, 500, false);
+ if (!ret)
+ return 0;
- /* After 3 times trying calibration */
- if (!ddr_setup_complete) {
- puts("Error: Could Not Calibrate SDRAM\n");
- return -EPERM;
+ ret = emif_reset();
+ if (ret)
+ puts("Error: Failed to reset EMIF\n");
}
- return 0;
+ puts("Error: Could Not Calibrate SDRAM\n");
+ return -EPERM;
}
static int sdram_is_ecc_enabled(void)
@@ -270,7 +235,7 @@ static u64 sdram_size_calc(void)
size *= (2 << (readl(&socfpga_ecc_hmc_base->ddrioctrl) &
ALT_ECC_HMC_OCP_DDRIOCTRL_IO_SIZE_MSK));
- debug("SDRAM size=%llu", size);
+ debug("SDRAM size=%llu\n", size);
return size;
}
@@ -304,7 +269,7 @@ static void sdram_mmr_init(void)
* bit[9:6] = Minor Release #
* bit[14:10] = Major Release #
*/
- if ((socfpga_io48_mmr_base->niosreserve1 >> 6) & 0x1FF) {
+ if ((readl(&socfpga_io48_mmr_base->niosreserve1) >> 6) & 0x1FF) {
update_value = readl(&socfpga_io48_mmr_base->niosreserve0);
writel(((update_value & 0xFF) >> 5),
&socfpga_ecc_hmc_base->ddrioctrl);
@@ -394,7 +359,7 @@ static void sdram_mmr_init(void)
caltim0_cfg_act_to_rdwr -
(ctrlcfg0_cfg_ctrl_burst_len >> 2));
- io48_value = ((((socfpga_io48_mmr_base->dramtiming0 &
+ io48_value = ((((readl(&socfpga_io48_mmr_base->dramtiming0) &
ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK) + 2 + 15 +
(ctrlcfg0_cfg_ctrl_burst_len >> 1)) >> 1) -
/* Up to here was in memory cycles so divide by 2 */
@@ -424,7 +389,7 @@ static void sdram_mmr_init(void)
&socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_ddrmode);
/* Configure the read latency [0xFFD12414] */
- writel(((socfpga_io48_mmr_base->dramtiming0 &
+ writel(((readl(&socfpga_io48_mmr_base->dramtiming0) &
ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK) >> 1) +
DDR_READ_LATENCY_DELAY,
&socfpga_noc_ddr_scheduler_base->
diff --git a/drivers/i2c/i2c-cdns.c b/drivers/i2c/i2c-cdns.c
index 4330d28c2b0..1af94d17614 100644
--- a/drivers/i2c/i2c-cdns.c
+++ b/drivers/i2c/i2c-cdns.c
@@ -64,12 +64,24 @@ struct cdns_i2c_regs {
#define CDNS_I2C_INTERRUPT_RXUNF 0x00000080
#define CDNS_I2C_INTERRUPT_ARBLOST 0x00000200
+#define CDNS_I2C_INTERRUPTS_MASK (CDNS_I2C_INTERRUPT_COMP | \
+ CDNS_I2C_INTERRUPT_DATA | \
+ CDNS_I2C_INTERRUPT_NACK | \
+ CDNS_I2C_INTERRUPT_TO | \
+ CDNS_I2C_INTERRUPT_SLVRDY | \
+ CDNS_I2C_INTERRUPT_RXOVF | \
+ CDNS_I2C_INTERRUPT_TXOVF | \
+ CDNS_I2C_INTERRUPT_RXUNF | \
+ CDNS_I2C_INTERRUPT_ARBLOST)
+
#define CDNS_I2C_FIFO_DEPTH 16
#define CDNS_I2C_TRANSFER_SIZE_MAX 255 /* Controller transfer limit */
#define CDNS_I2C_TRANSFER_SIZE (CDNS_I2C_TRANSFER_SIZE_MAX - 3)
#define CDNS_I2C_BROKEN_HOLD_BIT BIT(0)
+#define CDNS_I2C_ARB_LOST_MAX_RETRIES 10
+
#ifdef DEBUG
static void cdns_i2c_debug_status(struct cdns_i2c_regs *cdns_i2c)
{
@@ -224,11 +236,17 @@ static int cdns_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
return 0;
}
+static inline u32 is_arbitration_lost(struct cdns_i2c_regs *regs)
+{
+ return (readl(&regs->interrupt_status) & CDNS_I2C_INTERRUPT_ARBLOST);
+}
+
static int cdns_i2c_write_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data,
u32 len)
{
u8 *cur_data = data;
struct cdns_i2c_regs *regs = i2c_bus->regs;
+ u32 ret;
/* Set the controller in Master transmit mode and clear FIFO */
setbits_le32(&regs->control, CDNS_I2C_CONTROL_CLR_FIFO);
@@ -241,29 +259,42 @@ static int cdns_i2c_write_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data,
setbits_le32(&regs->control, CDNS_I2C_CONTROL_HOLD);
/* Clear the interrupts in status register */
- writel(0xFF, &regs->interrupt_status);
+ writel(CDNS_I2C_INTERRUPTS_MASK, &regs->interrupt_status);
writel(addr, &regs->address);
- while (len--) {
+ while (len-- && !is_arbitration_lost(regs)) {
writel(*(cur_data++), &regs->data);
if (readl(&regs->transfer_size) == CDNS_I2C_FIFO_DEPTH) {
- if (!cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP)) {
- /* Release the bus */
- clrbits_le32(&regs->control,
- CDNS_I2C_CONTROL_HOLD);
- return -ETIMEDOUT;
- }
+ ret = cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
+ CDNS_I2C_INTERRUPT_ARBLOST);
+ if (ret & CDNS_I2C_INTERRUPT_ARBLOST)
+ return -EAGAIN;
+ if (ret & CDNS_I2C_INTERRUPT_COMP)
+ continue;
+ /* Release the bus */
+ clrbits_le32(&regs->control,
+ CDNS_I2C_CONTROL_HOLD);
+ return -ETIMEDOUT;
}
}
+ if (len && is_arbitration_lost(regs))
+ return -EAGAIN;
+
/* All done... release the bus */
if (!i2c_bus->hold_flag)
clrbits_le32(&regs->control, CDNS_I2C_CONTROL_HOLD);
/* Wait for the address and data to be sent */
- if (!cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP))
+ ret = cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
+ CDNS_I2C_INTERRUPT_ARBLOST);
+ if (!(ret & (CDNS_I2C_INTERRUPT_ARBLOST |
+ CDNS_I2C_INTERRUPT_COMP)))
return -ETIMEDOUT;
+ if (ret & CDNS_I2C_INTERRUPT_ARBLOST)
+ return -EAGAIN;
+
return 0;
}
@@ -279,6 +310,7 @@ static int cdns_i2c_read_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data,
struct cdns_i2c_regs *regs = i2c_bus->regs;
int curr_recv_count;
int updatetx, hold_quirk;
+ u32 ret;
/* Check the hardware can handle the requested bytes */
if ((recv_count < 0))
@@ -307,7 +339,7 @@ static int cdns_i2c_read_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data,
hold_quirk = (i2c_bus->quirks & CDNS_I2C_BROKEN_HOLD_BIT) && updatetx;
- while (recv_count) {
+ while (recv_count && !is_arbitration_lost(regs)) {
while (readl(&regs->status) & CDNS_I2C_STATUS_RXDV) {
if (recv_count < CDNS_I2C_FIFO_DEPTH &&
!i2c_bus->hold_flag) {
@@ -356,8 +388,13 @@ static int cdns_i2c_read_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data,
}
/* Wait for the address and data to be sent */
- if (!cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP))
+ ret = cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
+ CDNS_I2C_INTERRUPT_ARBLOST);
+ if (!(ret & (CDNS_I2C_INTERRUPT_ARBLOST |
+ CDNS_I2C_INTERRUPT_COMP)))
return -ETIMEDOUT;
+ if (ret & CDNS_I2C_INTERRUPT_ARBLOST)
+ return -EAGAIN;
return 0;
}
@@ -366,8 +403,11 @@ static int cdns_i2c_xfer(struct udevice *dev, struct i2c_msg *msg,
int nmsgs)
{
struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev);
- int ret, count;
+ int ret = 0;
+ int count;
bool hold_quirk;
+ struct i2c_msg *message = msg;
+ int num_msgs = nmsgs;
hold_quirk = !!(i2c_bus->quirks & CDNS_I2C_BROKEN_HOLD_BIT);
@@ -393,7 +433,8 @@ static int cdns_i2c_xfer(struct udevice *dev, struct i2c_msg *msg,
}
debug("i2c_xfer: %d messages\n", nmsgs);
- for (; nmsgs > 0; nmsgs--, msg++) {
+ for (u8 retry = 0; retry < CDNS_I2C_ARB_LOST_MAX_RETRIES &&
+ nmsgs > 0; nmsgs--, msg++) {
debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
if (msg->flags & I2C_M_RD) {
ret = cdns_i2c_read_data(i2c_bus, msg->addr, msg->buf,
@@ -402,13 +443,22 @@ static int cdns_i2c_xfer(struct udevice *dev, struct i2c_msg *msg,
ret = cdns_i2c_write_data(i2c_bus, msg->addr, msg->buf,
msg->len);
}
+ if (ret == -EAGAIN) {
+ msg = message;
+ nmsgs = num_msgs;
+ retry++;
+ printf("%s,arbitration lost, retrying:%d\n", __func__,
+ retry);
+ continue;
+ }
+
if (ret) {
debug("i2c_write: error sending\n");
return -EREMOTEIO;
}
}
- return 0;
+ return ret;
}
static int cdns_i2c_ofdata_to_platdata(struct udevice *dev)
diff --git a/drivers/i2c/rcar_i2c.c b/drivers/i2c/rcar_i2c.c
index 8d87c737136..2ebae349ed3 100644
--- a/drivers/i2c/rcar_i2c.c
+++ b/drivers/i2c/rcar_i2c.c
@@ -18,39 +18,52 @@
#include <asm/io.h>
#include <wait_bit.h>
-#define RCAR_I2C_ICSCR 0x00
-#define RCAR_I2C_ICMCR 0x04
-#define RCAR_I2C_ICMCR_MDBS BIT(7)
-#define RCAR_I2C_ICMCR_FSCL BIT(6)
-#define RCAR_I2C_ICMCR_FSDA BIT(5)
-#define RCAR_I2C_ICMCR_OBPC BIT(4)
-#define RCAR_I2C_ICMCR_MIE BIT(3)
+#define RCAR_I2C_ICSCR 0x00 /* slave ctrl */
+#define RCAR_I2C_ICMCR 0x04 /* master ctrl */
+#define RCAR_I2C_ICMCR_MDBS BIT(7) /* non-fifo mode switch */
+#define RCAR_I2C_ICMCR_FSCL BIT(6) /* override SCL pin */
+#define RCAR_I2C_ICMCR_FSDA BIT(5) /* override SDA pin */
+#define RCAR_I2C_ICMCR_OBPC BIT(4) /* override pins */
+#define RCAR_I2C_ICMCR_MIE BIT(3) /* master if enable */
#define RCAR_I2C_ICMCR_TSBE BIT(2)
-#define RCAR_I2C_ICMCR_FSB BIT(1)
-#define RCAR_I2C_ICMCR_ESG BIT(0)
-#define RCAR_I2C_ICSSR 0x08
-#define RCAR_I2C_ICMSR 0x0c
+#define RCAR_I2C_ICMCR_FSB BIT(1) /* force stop bit */
+#define RCAR_I2C_ICMCR_ESG BIT(0) /* enable start bit gen */
+#define RCAR_I2C_ICSSR 0x08 /* slave status */
+#define RCAR_I2C_ICMSR 0x0c /* master status */
#define RCAR_I2C_ICMSR_MASK 0x7f
-#define RCAR_I2C_ICMSR_MNR BIT(6)
-#define RCAR_I2C_ICMSR_MAL BIT(5)
-#define RCAR_I2C_ICMSR_MST BIT(4)
+#define RCAR_I2C_ICMSR_MNR BIT(6) /* Nack */
+#define RCAR_I2C_ICMSR_MAL BIT(5) /* Arbitration lost */
+#define RCAR_I2C_ICMSR_MST BIT(4) /* Stop */
#define RCAR_I2C_ICMSR_MDE BIT(3)
#define RCAR_I2C_ICMSR_MDT BIT(2)
#define RCAR_I2C_ICMSR_MDR BIT(1)
#define RCAR_I2C_ICMSR_MAT BIT(0)
-#define RCAR_I2C_ICSIER 0x10
-#define RCAR_I2C_ICMIER 0x14
-#define RCAR_I2C_ICCCR 0x18
+#define RCAR_I2C_ICSIER 0x10 /* slave irq enable */
+#define RCAR_I2C_ICMIER 0x14 /* master irq enable */
+#define RCAR_I2C_ICCCR 0x18 /* clock dividers */
#define RCAR_I2C_ICCCR_SCGD_OFF 3
-#define RCAR_I2C_ICSAR 0x1c
-#define RCAR_I2C_ICMAR 0x20
-#define RCAR_I2C_ICRXD_ICTXD 0x24
+#define RCAR_I2C_ICSAR 0x1c /* slave address */
+#define RCAR_I2C_ICMAR 0x20 /* master address */
+#define RCAR_I2C_ICRXD_ICTXD 0x24 /* data port */
+/*
+ * First Bit Setup Cycle (Gen3).
+ * Defines 1st bit delay between SDA and SCL.
+ */
+#define RCAR_I2C_ICFBSCR 0x38
+#define RCAR_I2C_ICFBSCR_TCYC17 0x0f /* 17*Tcyc */
+
+
+enum rcar_i2c_type {
+ RCAR_I2C_TYPE_GEN2,
+ RCAR_I2C_TYPE_GEN3,
+};
struct rcar_i2c_priv {
void __iomem *base;
struct clk clk;
u32 intdelay;
u32 icccr;
+ enum rcar_i2c_type type;
};
static int rcar_i2c_finish(struct udevice *dev)
@@ -68,12 +81,13 @@ static int rcar_i2c_finish(struct udevice *dev)
return ret;
}
-static void rcar_i2c_recover(struct udevice *dev)
+static int rcar_i2c_recover(struct udevice *dev)
{
struct rcar_i2c_priv *priv = dev_get_priv(dev);
u32 mcr = RCAR_I2C_ICMCR_MDBS | RCAR_I2C_ICMCR_OBPC;
u32 mcra = mcr | RCAR_I2C_ICMCR_FSDA;
int i;
+ u32 mstat;
/* Send 9 SCL pulses */
for (i = 0; i < 9; i++) {
@@ -93,6 +107,9 @@ static void rcar_i2c_recover(struct udevice *dev)
udelay(5);
writel(mcra | RCAR_I2C_ICMCR_FSCL, priv->base + RCAR_I2C_ICMCR);
udelay(5);
+
+ mstat = readl(priv->base + RCAR_I2C_ICMSR);
+ return mstat & RCAR_I2C_ICMCR_FSDA ? -EBUSY : 0;
}
static int rcar_i2c_set_addr(struct udevice *dev, u8 chip, u8 read)
@@ -100,7 +117,6 @@ static int rcar_i2c_set_addr(struct udevice *dev, u8 chip, u8 read)
struct rcar_i2c_priv *priv = dev_get_priv(dev);
u32 mask = RCAR_I2C_ICMSR_MAT |
(read ? RCAR_I2C_ICMSR_MDR : RCAR_I2C_ICMSR_MDE);
- u32 val;
int ret;
writel(0, priv->base + RCAR_I2C_ICMIER);
@@ -108,21 +124,22 @@ static int rcar_i2c_set_addr(struct udevice *dev, u8 chip, u8 read)
writel(0, priv->base + RCAR_I2C_ICMSR);
writel(priv->icccr, priv->base + RCAR_I2C_ICCCR);
+ /* Wait for the bus */
ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMCR,
RCAR_I2C_ICMCR_FSDA, false, 2, true);
if (ret) {
- rcar_i2c_recover(dev);
- val = readl(priv->base + RCAR_I2C_ICMSR);
- if (val & RCAR_I2C_ICMCR_FSDA) {
+ if (rcar_i2c_recover(dev)) {
dev_err(dev, "Bus busy, aborting\n");
return ret;
}
}
writel((chip << 1) | read, priv->base + RCAR_I2C_ICMAR);
- writel(0, priv->base + RCAR_I2C_ICMSR);
+ /* Reset */
writel(RCAR_I2C_ICMCR_MDBS | RCAR_I2C_ICMCR_MIE | RCAR_I2C_ICMCR_ESG,
priv->base + RCAR_I2C_ICMCR);
+ /* Clear Status */
+ writel(0, priv->base + RCAR_I2C_ICMSR);
ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMSR, mask,
true, 100, true);
@@ -142,16 +159,12 @@ static int rcar_i2c_read_common(struct udevice *dev, struct i2c_msg *msg)
u32 icmcr = RCAR_I2C_ICMCR_MDBS | RCAR_I2C_ICMCR_MIE;
int i, ret = -EREMOTEIO;
- ret = rcar_i2c_set_addr(dev, msg->addr, 1);
- if (ret)
- return ret;
-
for (i = 0; i < msg->len; i++) {
if (msg->len - 1 == i)
icmcr |= RCAR_I2C_ICMCR_FSB;
writel(icmcr, priv->base + RCAR_I2C_ICMCR);
- writel(~RCAR_I2C_ICMSR_MDR, priv->base + RCAR_I2C_ICMSR);
+ writel((u32)~RCAR_I2C_ICMSR_MDR, priv->base + RCAR_I2C_ICMSR);
ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMSR,
RCAR_I2C_ICMSR_MDR, true, 100, true);
@@ -161,7 +174,7 @@ static int rcar_i2c_read_common(struct udevice *dev, struct i2c_msg *msg)
msg->buf[i] = readl(priv->base + RCAR_I2C_ICRXD_ICTXD) & 0xff;
}
- writel(~RCAR_I2C_ICMSR_MDR, priv->base + RCAR_I2C_ICMSR);
+ writel((u32)~RCAR_I2C_ICMSR_MDR, priv->base + RCAR_I2C_ICMSR);
return rcar_i2c_finish(dev);
}
@@ -172,14 +185,10 @@ static int rcar_i2c_write_common(struct udevice *dev, struct i2c_msg *msg)
u32 icmcr = RCAR_I2C_ICMCR_MDBS | RCAR_I2C_ICMCR_MIE;
int i, ret = -EREMOTEIO;
- ret = rcar_i2c_set_addr(dev, msg->addr, 0);
- if (ret)
- return ret;
-
for (i = 0; i < msg->len; i++) {
writel(msg->buf[i], priv->base + RCAR_I2C_ICRXD_ICTXD);
writel(icmcr, priv->base + RCAR_I2C_ICMCR);
- writel(~RCAR_I2C_ICMSR_MDE, priv->base + RCAR_I2C_ICMSR);
+ writel((u32)~RCAR_I2C_ICMSR_MDE, priv->base + RCAR_I2C_ICMSR);
ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMSR,
RCAR_I2C_ICMSR_MDE, true, 100, true);
@@ -187,7 +196,7 @@ static int rcar_i2c_write_common(struct udevice *dev, struct i2c_msg *msg)
return ret;
}
- writel(~RCAR_I2C_ICMSR_MDE, priv->base + RCAR_I2C_ICMSR);
+ writel((u32)~RCAR_I2C_ICMSR_MDE, priv->base + RCAR_I2C_ICMSR);
icmcr |= RCAR_I2C_ICMCR_FSB;
writel(icmcr, priv->base + RCAR_I2C_ICMCR);
@@ -199,16 +208,20 @@ static int rcar_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs)
int ret;
for (; nmsgs > 0; nmsgs--, msg++) {
+ ret = rcar_i2c_set_addr(dev, msg->addr, 1);
+ if (ret)
+ return ret;
+
if (msg->flags & I2C_M_RD)
ret = rcar_i2c_read_common(dev, msg);
else
ret = rcar_i2c_write_common(dev, msg);
if (ret)
- return -EREMOTEIO;
+ return ret;
}
- return ret;
+ return 0;
}
static int rcar_i2c_probe_chip(struct udevice *dev, uint addr, uint flags)
@@ -293,6 +306,11 @@ scgd_find:
priv->icccr = (scgd << RCAR_I2C_ICCCR_SCGD_OFF) | cdf;
writel(priv->icccr, priv->base + RCAR_I2C_ICCCR);
+ if (priv->type == RCAR_I2C_TYPE_GEN3) {
+ /* Set SCL/SDA delay */
+ writel(RCAR_I2C_ICFBSCR_TCYC17, priv->base + RCAR_I2C_ICFBSCR);
+ }
+
return 0;
}
@@ -304,6 +322,7 @@ static int rcar_i2c_probe(struct udevice *dev)
priv->base = dev_read_addr_ptr(dev);
priv->intdelay = dev_read_u32_default(dev,
"i2c-scl-internal-delay-ns", 5);
+ priv->type = dev_get_driver_data(dev);
ret = clk_get_by_index(dev, 0, &priv->clk);
if (ret)
@@ -339,7 +358,8 @@ static const struct dm_i2c_ops rcar_i2c_ops = {
};
static const struct udevice_id rcar_i2c_ids[] = {
- { .compatible = "renesas,rcar-gen2-i2c" },
+ { .compatible = "renesas,rcar-gen2-i2c", .data = RCAR_I2C_TYPE_GEN2 },
+ { .compatible = "renesas,rcar-gen3-i2c", .data = RCAR_I2C_TYPE_GEN3 },
{ }
};
diff --git a/drivers/i2c/rcar_iic.c b/drivers/i2c/rcar_iic.c
index e91fc86c1ac..9d45f547d15 100644
--- a/drivers/i2c/rcar_iic.c
+++ b/drivers/i2c/rcar_iic.c
@@ -58,12 +58,14 @@ static void sh_irq_dte(struct udevice *dev)
static int sh_irq_dte_with_tack(struct udevice *dev)
{
struct rcar_iic_priv *priv = dev_get_priv(dev);
+ u8 icsr;
int i;
for (i = 0; i < IRQ_WAIT; i++) {
- if (RCAR_IC_DTE & readb(priv->base + RCAR_IIC_ICSR))
+ icsr = readb(priv->base + RCAR_IIC_ICSR);
+ if (RCAR_IC_DTE & icsr)
break;
- if (RCAR_IC_TACK & readb(priv->base + RCAR_IIC_ICSR))
+ if (RCAR_IC_TACK & icsr)
return -ETIMEDOUT;
udelay(10);
}
generated by cgit v1.2.3 (git 2.0.4) at 2025-09-19 05:28:13 +0000