diff options
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/net/dwc_eth_qos_rockchip.c | 14 | ||||
| -rw-r--r-- | drivers/pinctrl/rockchip/pinctrl-rk3328.c | 59 |
2 files changed, 62 insertions, 11 deletions
diff --git a/drivers/net/dwc_eth_qos_rockchip.c b/drivers/net/dwc_eth_qos_rockchip.c index 9fc8c686b88..f3a0f63003e 100644 --- a/drivers/net/dwc_eth_qos_rockchip.c +++ b/drivers/net/dwc_eth_qos_rockchip.c @@ -46,6 +46,10 @@ struct rockchip_platform_data { #define GRF_BIT(nr) (BIT(nr) | BIT((nr) + 16)) #define GRF_CLR_BIT(nr) (BIT((nr) + 16)) +#define DELAY_ENABLE(soc, tx, rx) \ + (((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \ + ((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE)) + #define RK3568_GRF_GMAC0_CON0 0x0380 #define RK3568_GRF_GMAC0_CON1 0x0384 #define RK3568_GRF_GMAC1_CON0 0x0388 @@ -85,8 +89,7 @@ static int rk3568_set_to_rgmii(struct udevice *dev, regmap_write(data->grf, con1, RK3568_GMAC_PHY_INTF_SEL_RGMII | - RK3568_GMAC_RXCLK_DLY_ENABLE | - RK3568_GMAC_TXCLK_DLY_ENABLE); + DELAY_ENABLE(RK3568, tx_delay, rx_delay)); return 0; } @@ -131,6 +134,10 @@ static int rk3568_set_gmac_speed(struct udevice *dev) return 0; } +#define RK3588_DELAY_ENABLE(id, tx, rx) \ + (((tx) ? RK3588_GMAC_TXCLK_DLY_ENABLE(id) : RK3588_GMAC_TXCLK_DLY_DISABLE(id)) | \ + ((rx) ? RK3588_GMAC_RXCLK_DLY_ENABLE(id) : RK3588_GMAC_RXCLK_DLY_DISABLE(id))) + /* sys_grf */ #define RK3588_GRF_GMAC_CON7 0x031c #define RK3588_GRF_GMAC_CON8 0x0320 @@ -189,8 +196,7 @@ static int rk3588_set_to_rgmii(struct udevice *dev, RK3588_GMAC_CLK_RGMII_MODE(id)); regmap_write(data->grf, RK3588_GRF_GMAC_CON7, - RK3588_GMAC_RXCLK_DLY_ENABLE(id) | - RK3588_GMAC_TXCLK_DLY_ENABLE(id)); + RK3588_DELAY_ENABLE(id, tx_delay, rx_delay)); regmap_write(data->grf, offset_con, RK3588_GMAC_CLK_RX_DL_CFG(rx_delay) | diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3328.c b/drivers/pinctrl/rockchip/pinctrl-rk3328.c index 47c2e923a1b..dd0dc2eff27 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3328.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3328.c @@ -14,23 +14,68 @@ static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = { { - .num = 2, - .pin = 12, - .reg = 0x24, - .bit = 8, - .mask = 0x3 - }, { + /* gpio2_b7_sel */ .num = 2, .pin = 15, .reg = 0x28, .bit = 0, .mask = 0x7 }, { + /* gpio2_c7_sel */ .num = 2, .pin = 23, .reg = 0x30, .bit = 14, .mask = 0x3 + }, { + /* gpio3_b1_sel */ + .num = 3, + .pin = 9, + .reg = 0x44, + .bit = 2, + .mask = 0x3 + }, { + /* gpio3_b2_sel */ + .num = 3, + .pin = 10, + .reg = 0x44, + .bit = 4, + .mask = 0x3 + }, { + /* gpio3_b3_sel */ + .num = 3, + .pin = 11, + .reg = 0x44, + .bit = 6, + .mask = 0x3 + }, { + /* gpio3_b4_sel */ + .num = 3, + .pin = 12, + .reg = 0x44, + .bit = 8, + .mask = 0x3 + }, { + /* gpio3_b5_sel */ + .num = 3, + .pin = 13, + .reg = 0x44, + .bit = 10, + .mask = 0x3 + }, { + /* gpio3_b6_sel */ + .num = 3, + .pin = 14, + .reg = 0x44, + .bit = 12, + .mask = 0x3 + }, { + /* gpio3_b7_sel */ + .num = 3, + .pin = 15, + .reg = 0x44, + .bit = 14, + .mask = 0x3 }, }; @@ -275,7 +320,7 @@ static struct rockchip_pin_bank rk3328_pin_banks[] = { PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0), PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, - IOMUX_WIDTH_3BIT, + IOMUX_8WIDTH_2BIT, IOMUX_WIDTH_3BIT, 0), PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", |