diff options
Diffstat (limited to 'drivers')
28 files changed, 312 insertions, 133 deletions
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig index 9bc5283c268..6cca561f974 100644 --- a/drivers/ata/Kconfig +++ b/drivers/ata/Kconfig @@ -61,7 +61,6 @@ config DWC_AHCI config DWC_AHSATA bool "Enable DWC AHSATA driver support" select LIBATA - depends on BLK help Enable this driver to support the DWC AHSATA SATA controller found in i.MX5 and i.MX6 SoCs. diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig index 6ad18889f61..48529a6982f 100644 --- a/drivers/block/Kconfig +++ b/drivers/block/Kconfig @@ -1,8 +1,8 @@ config BLK bool # "Support block devices" depends on DM - default y if MMC || USB || SCSI || NVME || IDE || AHCI || SATA - default y if EFI_MEDIA || VIRTIO_BLK || PVBLOCK + def_bool y if MMC || USB || SCSI || NVME || IDE || AHCI || SATA + def_bool y if EFI_MEDIA || VIRTIO_BLK || PVBLOCK help Enable support for block devices, such as SCSI, MMC and USB flash sticks. These provide a block-level interface which permits diff --git a/drivers/clk/ti/clk-k3.c b/drivers/clk/ti/clk-k3.c index 41e5022ea0c..bf65f573cb8 100644 --- a/drivers/clk/ti/clk-k3.c +++ b/drivers/clk/ti/clk-k3.c @@ -59,6 +59,24 @@ static void clk_add_map(struct ti_clk_data *data, struct clk *clk, } static const struct soc_attr ti_k3_soc_clk_data[] = { +#if IS_ENABLED(CONFIG_SOC_K3_AM625) + { + .family = "AM62X", + .data = &am62x_clk_platdata, + }, +#endif +#if IS_ENABLED(CONFIG_SOC_K3_AM62A7) + { + .family = "AM62AX", + .data = &am62ax_clk_platdata, + }, +#endif +#if IS_ENABLED(CONFIG_SOC_K3_AM62P5) + { + .family = "AM62PX", + .data = &am62px_clk_platdata, + }, +#endif #if IS_ENABLED(CONFIG_SOC_K3_J721E) { .family = "J721E", @@ -68,36 +86,25 @@ static const struct soc_attr ti_k3_soc_clk_data[] = { .family = "J7200", .data = &j7200_clk_platdata, }, -#elif CONFIG_SOC_K3_J721S2 +#endif +#if IS_ENABLED(CONFIG_SOC_K3_J721S2) { .family = "J721S2", .data = &j721s2_clk_platdata, }, #endif -#ifdef CONFIG_SOC_K3_AM625 - { - .family = "AM62X", - .data = &am62x_clk_platdata, - }, -#endif -#ifdef CONFIG_SOC_K3_AM62A7 +#if IS_ENABLED(CONFIG_SOC_K3_J722S) { - .family = "AM62AX", - .data = &am62ax_clk_platdata, + .family = "J722S", + .data = &j722s_clk_platdata, }, #endif -#ifdef CONFIG_SOC_K3_J784S4 +#if IS_ENABLED(CONFIG_SOC_K3_J784S4) { .family = "J784S4", .data = &j784s4_clk_platdata, }, #endif -#ifdef CONFIG_SOC_K3_AM62P5 - { - .family = "AM62PX", - .data = &am62px_clk_platdata, - }, -#endif { /* sentinel */ } }; diff --git a/drivers/firmware/ti_sci_static_data.h b/drivers/firmware/ti_sci_static_data.h index 9662bd95f28..3370f80231d 100644 --- a/drivers/firmware/ti_sci_static_data.h +++ b/drivers/firmware/ti_sci_static_data.h @@ -85,7 +85,7 @@ static struct ti_sci_resource_static_data rm_static_data[] = { #endif /* CONFIG_SOC_K3_J721S2 */ #if IS_ENABLED(CONFIG_SOC_K3_AM625) || IS_ENABLED(CONFIG_SOC_K3_AM62A7) || \ - IS_ENABLED(CONFIG_SOC_K3_AM62P5) + IS_ENABLED(CONFIG_SOC_K3_AM62P5) || IS_ENABLED(CONFIG_SOC_K3_J722S) static struct ti_sci_resource_static_data rm_static_data[] = { /* BC channels */ { diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index b050585389b..fcca6941ebf 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -487,7 +487,7 @@ config MVEBU_GPIO config ZYNQ_GPIO bool "Zynq GPIO driver" depends on DM_GPIO - default y if ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL + default y if ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL || ARCH_VERSAL2 help Supports GPIO access on Zynq SoC. @@ -639,7 +639,7 @@ config NOMADIK_GPIO config ZYNQMP_GPIO_MODEPIN bool "ZynqMP gpio modepin" - depends on DM_GPIO + depends on DM_GPIO && ZYNQMP_FIRMWARE help This config enables the ZynqMP gpio modepin driver. ZynqMP modepin driver will set and get the status of PS_MODE pins. These modepins diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig index 47f24e0a02e..67d5ac1a742 100644 --- a/drivers/mailbox/Kconfig +++ b/drivers/mailbox/Kconfig @@ -54,7 +54,7 @@ config K3_SEC_PROXY config ZYNQMP_IPI bool "Xilinx ZynqMP IPI controller support" - depends on DM_MAILBOX && (ARCH_ZYNQMP || ARCH_VERSAL || ARCH_VERSAL_NET) + depends on DM_MAILBOX && (ARCH_ZYNQMP || ARCH_VERSAL || ARCH_VERSAL_NET || ARCH_VERSAL2) help This enables support for the Xilinx ZynqMP Inter Processor Interrupt communication controller. diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index d0944793c92..8b13a0821ee 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -41,7 +41,6 @@ config MMC_BROKEN_CD config DM_MMC bool "Enable MMC controllers using Driver Model" depends on DM - select BLK help This enables the MultiMediaCard (MMC) uclass which supports MMC and Secure Digital I/O (SDIO) cards. Both removable (SD, micro-SD, etc.) @@ -249,7 +248,6 @@ config MMC_DW_CORTINA bool "Cortina specific extensions for Synopsys DW Memory Card Interface" depends on DM_MMC depends on MMC_DW - depends on BLK help This selects support for Cortina SoC specific extensions to the Synopsys DesignWare Memory Card Interface driver. Select this option @@ -313,7 +311,7 @@ config NEXELL_DWMMC config MMC_MESON_GX bool "Meson GX EMMC controller support" - depends on DM_MMC && BLK && ARCH_MESON + depends on DM_MMC && ARCH_MESON help Support for EMMC host controller on Meson GX ARM SoCs platform (S905) @@ -367,7 +365,7 @@ config MMC_OCTEONTX config MVEBU_MMC bool "Kirkwood MMC controller support" - depends on DM_MMC && BLK && ARCH_KIRKWOOD + depends on DM_MMC && ARCH_KIRKWOOD help Support for MMC host controller on Kirkwood SoCs. If you are on a Kirkwood architecture, say Y here. @@ -420,7 +418,7 @@ config SH_MMCIF config MMC_UNIPHIER bool "UniPhier SD/MMC Host Controller support" depends on ARCH_UNIPHIER - depends on BLK && DM_MMC + depends on DM_MMC depends on OF_CONTROL help This selects support for the Matsushita SD/MMC Host Controller on @@ -429,7 +427,7 @@ config MMC_UNIPHIER config RENESAS_SDHI bool "Renesas R-Car SD/MMC Host Controller support" depends on ARCH_RENESAS - depends on BLK && DM_MMC + depends on DM_MMC depends on OF_CONTROL select BOUNCE_BUFFER help @@ -439,7 +437,7 @@ config RENESAS_SDHI config MMC_BCM2835 bool "BCM2835 family custom SD/MMC Host Controller support" depends on ARCH_BCM283X - depends on BLK && DM_MMC + depends on DM_MMC depends on OF_CONTROL default y help @@ -459,7 +457,7 @@ config JZ47XX_MMC config MMC_SANDBOX bool "Sandbox MMC support" depends on SANDBOX - depends on BLK && DM_MMC && OF_CONTROL + depends on DM_MMC && OF_CONTROL help This select a dummy sandbox MMC driver. At present this does nothing other than allow sandbox to be build with MMC support. This @@ -561,7 +559,7 @@ config MMC_SDHCI_ASPEED config MMC_SDHCI_ATMEL bool "Atmel SDHCI controller support" depends on ARCH_AT91 - depends on DM_MMC && BLK && ARCH_AT91 + depends on DM_MMC && ARCH_AT91 depends on MMC_SDHCI help This enables support for the Atmel SDHCI controller, which supports @@ -596,7 +594,7 @@ config MMC_SDHCI_BCMSTB config MMC_SDHCI_CADENCE bool "SDHCI support for the Cadence SD/SDIO/eMMC controller" - depends on BLK && DM_MMC + depends on DM_MMC depends on MMC_SDHCI depends on OF_CONTROL help @@ -608,7 +606,7 @@ config MMC_SDHCI_CADENCE config MMC_SDHCI_CV1800B bool "SDHCI support for the CV1800B SD/SDIO/eMMC controller" - depends on BLK && DM_MMC + depends on DM_MMC depends on MMC_SDHCI depends on OF_CONTROL help @@ -643,7 +641,7 @@ config MMC_SDHCI_IPROC config MMC_SDHCI_F_SDH30 bool "SDHCI support for Fujitsu Semiconductor/Socionext F_SDH30" - depends on BLK && DM_MMC + depends on DM_MMC depends on MMC_SDHCI help This selects the Secure Digital Host Controller Interface (SDHCI) @@ -663,7 +661,7 @@ config MMC_SDHCI_KONA config MMC_SDHCI_MSM bool "Qualcomm SDHCI controller" - depends on BLK && DM_MMC + depends on DM_MMC depends on MMC_SDHCI help Enables support for SDHCI 2.0 controller present on some Qualcomm @@ -829,7 +827,7 @@ config MMC_PITON config GENERIC_ATMEL_MCI bool "Atmel Multimedia Card Interface support" - depends on DM_MMC && BLK && ARCH_AT91 + depends on DM_MMC && ARCH_AT91 help This enables support for Atmel High Speed Multimedia Card Interface (HSMCI), which supports the MultiMedia Card (MMC) Specification V4.3, @@ -838,7 +836,7 @@ config GENERIC_ATMEL_MCI config STM32_SDMMC2 bool "STMicroelectronics STM32H7 SD/MMC Host Controller support" - depends on DM_MMC && BLK && OF_CONTROL + depends on DM_MMC && OF_CONTROL help This selects support for the SD/MMC controller on STM32H7 SoCs. If you have a board based on such a SoC and with a SD/MMC slot, @@ -858,7 +856,7 @@ config FTSDC010_SDIO config MMC_MTK bool "MediaTek SD/MMC Card Interface support" depends on ARCH_MEDIATEK || ARCH_MTMIPS - depends on BLK && DM_MMC + depends on DM_MMC depends on OF_CONTROL help This selects the MediaTek(R) Secure digital and Multimedia card Interface. diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index 898be5a0913..28d2b456fbf 100644 --- a/drivers/mmc/zynq_sdhci.c +++ b/drivers/mmc/zynq_sdhci.c @@ -122,7 +122,8 @@ __weak int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id) return 1; } -#if defined(CONFIG_ARCH_ZYNQMP) || defined(CONFIG_ARCH_VERSAL) || defined(CONFIG_ARCH_VERSAL_NET) +#if defined(CONFIG_ARCH_ZYNQMP) || defined(CONFIG_ARCH_VERSAL) || \ + defined(CONFIG_ARCH_VERSAL_NET) || defined(CONFIG_ARCH_VERSAL2) /* Default settings for ZynqMP Clock Phases */ static const u32 zynqmp_iclk_phases[] = {0, 63, 63, 0, 63, 0, 0, 183, 54, 0, 0}; @@ -156,7 +157,7 @@ static const u8 mode2timing[] = { [MMC_HS_400] = MMC_TIMING_MMC_HS400, }; -#if defined(CONFIG_ARCH_VERSAL_NET) +#if defined(CONFIG_ARCH_VERSAL_NET) || defined(CONFIG_ARCH_VERSAL2) /** * arasan_phy_set_delaychain - Set eMMC delay chain based Input/Output clock * @@ -865,7 +866,9 @@ static int arasan_sdhci_set_tapdelay(struct sdhci_host *host) ret = sdhci_zynqmp_sdcardclk_set_phase(host, oclk_phase); if (ret) return ret; - } else if (IS_ENABLED(CONFIG_ARCH_VERSAL) && + } else if ((IS_ENABLED(CONFIG_ARCH_VERSAL) || + IS_ENABLED(CONFIG_ARCH_VERSAL_NET) || + IS_ENABLED(CONFIG_ARCH_VERSAL2)) && device_is_compatible(dev, "xlnx,versal-8.9a")) { ret = sdhci_versal_sampleclk_set_phase(host, iclk_phase); if (ret) @@ -874,7 +877,8 @@ static int arasan_sdhci_set_tapdelay(struct sdhci_host *host) ret = sdhci_versal_sdcardclk_set_phase(host, oclk_phase); if (ret) return ret; - } else if (IS_ENABLED(CONFIG_ARCH_VERSAL_NET) && + } else if ((IS_ENABLED(CONFIG_ARCH_VERSAL_NET) || + IS_ENABLED(CONFIG_ARCH_VERSAL2)) && device_is_compatible(dev, "xlnx,versal-net-emmc")) { if (mmc->clock >= MIN_PHY_CLK_HZ) if (iclk_phase == VERSAL_NET_EMMC_ICLK_PHASE_DDR52_DLY_CHAIN) @@ -941,7 +945,9 @@ static void arasan_dt_parse_clk_phases(struct udevice *dev) } } - if (IS_ENABLED(CONFIG_ARCH_VERSAL) && + if ((IS_ENABLED(CONFIG_ARCH_VERSAL) || + IS_ENABLED(CONFIG_ARCH_VERSAL_NET) || + IS_ENABLED(CONFIG_ARCH_VERSAL2)) && device_is_compatible(dev, "xlnx,versal-8.9a")) { for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) { clk_data->clk_phase_in[i] = versal_iclk_phases[i]; @@ -949,7 +955,8 @@ static void arasan_dt_parse_clk_phases(struct udevice *dev) } } - if (IS_ENABLED(CONFIG_ARCH_VERSAL_NET) && + if ((IS_ENABLED(CONFIG_ARCH_VERSAL_NET) || + IS_ENABLED(CONFIG_ARCH_VERSAL2)) && device_is_compatible(dev, "xlnx,versal-net-emmc")) { for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) { clk_data->clk_phase_in[i] = versal_net_emmc_iclk_phases[i]; @@ -985,7 +992,7 @@ static const struct sdhci_ops arasan_ops = { .platform_execute_tuning = &arasan_sdhci_execute_tuning, .set_delay = &arasan_sdhci_set_tapdelay, .set_control_reg = &sdhci_set_control_reg, -#if defined(CONFIG_ARCH_VERSAL_NET) +#if defined(CONFIG_ARCH_VERSAL_NET) || defined(CONFIG_ARCH_VERSAL2) .config_dll = &arasan_sdhci_config_dll, #endif }; @@ -1193,7 +1200,8 @@ static int arasan_sdhci_of_to_plat(struct udevice *dev) priv->host->name = dev->name; -#if defined(CONFIG_ARCH_ZYNQMP) || defined(CONFIG_ARCH_VERSAL) || defined(CONFIG_ARCH_VERSAL_NET) +#if defined(CONFIG_ARCH_ZYNQMP) || defined(CONFIG_ARCH_VERSAL) || defined(CONFIG_ARCH_VERSAL_NET) || \ + defined(CONFIG_ARCH_VERSAL2) priv->host->ops = &arasan_ops; arasan_dt_parse_clk_phases(dev); #endif diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 982dd251150..aea611fef52 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -1804,11 +1804,62 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len, if (ret < 0) return ret; #endif + write_enable(nor); - ret = nor->write(nor, addr, page_remain, buf + i); - if (ret < 0) - goto write_err; - written = ret; + + /* + * On DTR capable flashes like Micron Xcella the writes cannot + * start or end at an odd address in DTR mode. So we need to + * append or prepend extra 0xff bytes to make sure the start + * address and end address are even. + */ + if (spi_nor_protocol_is_dtr(nor->write_proto) && + ((addr | page_remain) & 1)) { + u_char *tmp; + size_t extra_bytes = 0; + + tmp = kmalloc(nor->page_size, 0); + if (!tmp) { + ret = -ENOMEM; + goto write_err; + } + + /* Prepend a 0xff byte if the start address is odd. */ + if (addr & 1) { + tmp[0] = 0xff; + memcpy(tmp + 1, buf + i, page_remain); + addr--; + page_remain++; + extra_bytes++; + } else { + memcpy(tmp, buf + i, page_remain); + } + + /* Append a 0xff byte if the end address is odd. */ + if ((addr + page_remain) & 1) { + tmp[page_remain + extra_bytes] = 0xff; + extra_bytes++; + page_remain++; + } + + ret = nor->write(nor, addr, page_remain, tmp); + + kfree(tmp); + + if (ret < 0) + goto write_err; + + /* + * We write extra bytes but they are not part of the + * original write. + */ + written = ret - extra_bytes; + } else { + ret = nor->write(nor, addr, page_remain, buf + i); + if (ret < 0) + goto write_err; + written = ret; + } ret = spi_nor_wait_till_ready(nor); if (ret) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 684206ea07d..2206d734810 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -274,7 +274,7 @@ const struct flash_info spi_nor_ids[] = { { INFO("mx66l2g45g", 0xc2201c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, { INFO("mx25l1633e", 0xc22415, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | SECT_4K) }, { INFO("mx25r6435f", 0xc22817, 0, 64 * 1024, 128, SECT_4K) }, - { INFO("mx66uw2g345gx0", 0xc2943c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, + { INFO("mx66uw2g345gx0", 0xc2943c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_READ) }, { INFO("mx66lm1g45g", 0xc2853b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, { INFO("mx25lm51245g", 0xc2853a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, { INFO("mx25lw51245g", 0xc2863a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, diff --git a/drivers/net/bcmgenet.c b/drivers/net/bcmgenet.c index 4e1f8ed7a4a..a0264dc386d 100644 --- a/drivers/net/bcmgenet.c +++ b/drivers/net/bcmgenet.c @@ -360,6 +360,10 @@ static int bcmgenet_gmac_free_pkt(struct udevice *dev, uchar *packet, int length) { struct bcmgenet_eth_priv *priv = dev_get_priv(dev); + void *desc_base = priv->rx_desc_base + priv->rx_index * DMA_DESC_SIZE; + u32 addr = readl(desc_base + DMA_DESC_ADDRESS_LO); + + flush_dcache_range(addr, addr + RX_BUF_LENGTH); /* Tell the MAC we have consumed that last receive buffer. */ priv->c_index = (priv->c_index + 1) & 0xFFFF; diff --git a/drivers/net/dwc_eth_qos_stm32.c b/drivers/net/dwc_eth_qos_stm32.c index fbc08bba1d6..cffaa10b705 100644 --- a/drivers/net/dwc_eth_qos_stm32.c +++ b/drivers/net/dwc_eth_qos_stm32.c @@ -266,6 +266,12 @@ static int eqos_probe_resources_stm32(struct udevice *dev) if (ret) dev_warn(dev, "No phy clock provided %d\n", ret); + /* Get reset gpio pin (optional) */ + ret = gpio_request_by_name(dev, "phy-reset-gpios", 0, + &eqos->phy_reset_gpio, GPIOD_IS_OUT); + if (ret) + pr_warn("No phy reset gpio provided: %d\n", ret); + dev_dbg(dev, "%s: OK\n", __func__); return 0; @@ -277,6 +283,21 @@ err_probe: return ret; } +static int eqos_start_resets_stm32(struct udevice *dev) +{ + struct eqos_priv *eqos = dev_get_priv(dev); + + debug("%s(dev=%p):\n", __func__, dev); + + if (dm_gpio_is_valid(&eqos->phy_reset_gpio)) { + dm_gpio_set_value(&eqos->phy_reset_gpio, 1); + udelay(2); + dm_gpio_set_value(&eqos->phy_reset_gpio, 0); + } + + return 0; +} + static int eqos_remove_resources_stm32(struct udevice *dev) { dev_dbg(dev, "%s:\n", __func__); @@ -292,7 +313,7 @@ static struct eqos_ops eqos_stm32_ops = { .eqos_probe_resources = eqos_probe_resources_stm32, .eqos_remove_resources = eqos_remove_resources_stm32, .eqos_stop_resets = eqos_null_ops, - .eqos_start_resets = eqos_null_ops, + .eqos_start_resets = eqos_start_resets_stm32, .eqos_stop_clks = eqos_stop_clks_stm32, .eqos_start_clks = eqos_start_clks_stm32, .eqos_calibrate_pads = eqos_null_ops, diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 3d96938eaba..73064b2af68 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -23,6 +23,12 @@ config PHY_ADDR_ENABLE help Select this if you want to control which phy address is used +config PHY_ANEG_TIMEOUT + int "PHY auto-negotiation timeout" + default 4000 + help + Default PHY auto-negotiation timeout. + if PHY_ADDR_ENABLE config PHY_ADDR int "PHY address" diff --git a/drivers/net/phy/aquantia.c b/drivers/net/phy/aquantia.c index 4517a6b13ba..d2db8d9f792 100644 --- a/drivers/net/phy/aquantia.c +++ b/drivers/net/phy/aquantia.c @@ -566,9 +566,9 @@ int aquantia_startup(struct phy_device *phydev) if ((i++ % 500) == 0) printf("."); } while (!aquantia_link_is_up(phydev) && - i < (4 * PHY_ANEG_TIMEOUT)); + i < (4 * CONFIG_PHY_ANEG_TIMEOUT)); - if (i > PHY_ANEG_TIMEOUT) + if (i > CONFIG_PHY_ANEG_TIMEOUT) printf(" TIMEOUT !\n"); } diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index fbf85d90f54..716a1d46111 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -250,7 +250,7 @@ int genphy_update_link(struct phy_device *phydev) /* * Timeout reached ? */ - if (i > (PHY_ANEG_TIMEOUT / 50)) { + if (i > (CONFIG_PHY_ANEG_TIMEOUT / 50)) { printf(" TIMEOUT !\n"); phydev->link = 0; return -ETIMEDOUT; diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c index a1a39f61488..4d87e2d1f36 100644 --- a/drivers/net/xilinx_axi_emac.c +++ b/drivers/net/xilinx_axi_emac.c @@ -361,7 +361,7 @@ static int pcs_pma_startup(struct axidma_priv *priv) * and the external PHY is not obtained. */ debug("axiemac: waiting for link status of the PCS/PMA PHY"); - while (retry_cnt * 10 < PHY_ANEG_TIMEOUT) { + while (retry_cnt * 10 < CONFIG_PHY_ANEG_TIMEOUT) { rc = phyread(priv, priv->pcsaddr, MII_BMSR, &mii_reg); if ((mii_reg & BMSR_LSTATUS) && mii_reg != 0xffff && !rc) { debug(".Done\n"); diff --git a/drivers/power/domain/ti-power-domain.c b/drivers/power/domain/ti-power-domain.c index b059dd37376..5e7a4c5648d 100644 --- a/drivers/power/domain/ti-power-domain.c +++ b/drivers/power/domain/ti-power-domain.c @@ -71,6 +71,24 @@ static void lpsc_write(u32 val, struct ti_lpsc *lpsc, u32 reg) } static const struct soc_attr ti_k3_soc_pd_data[] = { +#if IS_ENABLED(CONFIG_SOC_K3_AM625) + { + .family = "AM62X", + .data = &am62x_pd_platdata, + }, +#endif +#if IS_ENABLED(CONFIG_SOC_K3_AM62A7) + { + .family = "AM62AX", + .data = &am62ax_pd_platdata, + }, +#endif +#if IS_ENABLED(CONFIG_SOC_K3_AM62P5) + { + .family = "AM62PX", + .data = &am62px_pd_platdata, + }, +#endif #if IS_ENABLED(CONFIG_SOC_K3_J721E) { .family = "J721E", @@ -87,16 +105,10 @@ static const struct soc_attr ti_k3_soc_pd_data[] = { .data = &j721s2_pd_platdata, }, #endif -#if IS_ENABLED(CONFIG_SOC_K3_AM625) - { - .family = "AM62X", - .data = &am62x_pd_platdata, - }, -#endif -#if IS_ENABLED(CONFIG_SOC_K3_AM62A7) +#if IS_ENABLED(CONFIG_SOC_K3_J722S) { - .family = "AM62AX", - .data = &am62ax_pd_platdata, + .family = "J722S", + .data = &j722s_pd_platdata, }, #endif #if IS_ENABLED(CONFIG_SOC_K3_J784S4) @@ -105,12 +117,6 @@ static const struct soc_attr ti_k3_soc_pd_data[] = { .data = &j784s4_pd_platdata, }, #endif -#if IS_ENABLED(CONFIG_SOC_K3_AM62P5) - { - .family = "AM62PX", - .data = &am62px_pd_platdata, - }, -#endif { /* sentinel */ } }; diff --git a/drivers/power/pmic/rk8xx.c b/drivers/power/pmic/rk8xx.c index 12ff26a0855..617bb511e4e 100644 --- a/drivers/power/pmic/rk8xx.c +++ b/drivers/power/pmic/rk8xx.c @@ -6,6 +6,7 @@ #include <dm.h> #include <dm/lists.h> +#include <bitfield.h> #include <errno.h> #include <log.h> #include <linux/bitfield.h> @@ -277,10 +278,9 @@ static int rk8xx_probe(struct udevice *dev) return ret; priv->variant = ((msb << 8) | lsb) & RK8XX_ID_MSK; - show_variant = priv->variant; + show_variant = bitfield_extract_by_mask(priv->variant, RK8XX_ID_MSK); switch (priv->variant) { case RK808_ID: - show_variant = 0x808; /* RK808 hardware ID is 0 */ break; case RK805_ID: case RK816_ID: @@ -311,7 +311,7 @@ static int rk8xx_probe(struct udevice *dev) init_data_num = ARRAY_SIZE(rk806_init_reg); break; default: - printf("Unknown PMIC: RK%x!!\n", priv->variant); + printf("Unknown PMIC: RK%x!!\n", show_variant); return -EINVAL; } diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig index 9838a2798f9..a64d2dff68d 100644 --- a/drivers/ram/Kconfig +++ b/drivers/ram/Kconfig @@ -65,7 +65,7 @@ choice default K3_J721E_DDRSS if SOC_K3_J721E || SOC_K3_J721S2 || SOC_K3_J784S4 default K3_AM64_DDRSS if SOC_K3_AM642 default K3_AM64_DDRSS if SOC_K3_AM625 - default K3_AM62A_DDRSS if SOC_K3_AM62A7 || SOC_K3_AM62P5 + default K3_AM62A_DDRSS if SOC_K3_AM62A7 || SOC_K3_AM62P5 || SOC_K3_J722S config K3_J721E_DDRSS bool "Enable J721E DDRSS support" diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 4963385dc1c..42b69719dd7 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -291,9 +291,9 @@ void ns16550_putc(struct ns16550 *com_port, char c) serial_out(c, &com_port->thr); /* - * Call watchdog_reset() upon newline. This is done here in putc + * Call schedule() upon newline. This is done here in putc * since the environment code uses a single puts() to print the complete - * environment upon "printenv". So we can't put this watchdog call + * environment upon "printenv". So we can't put this schedule call * in puts(). */ if (c == '\n') @@ -390,9 +390,9 @@ static int ns16550_serial_putc(struct udevice *dev, const char ch) serial_out(ch, &com_port->thr); /* - * Call watchdog_reset() upon newline. This is done here in putc + * Call schedule() upon newline. This is done here in putc * since the environment code uses a single puts() to print the complete - * environment upon "printenv". So we can't put this watchdog call + * environment upon "printenv". So we can't put this schedule call * in puts(). */ if (ch == '\n') diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig index 03433bc0e6d..cee506fe474 100644 --- a/drivers/soc/Kconfig +++ b/drivers/soc/Kconfig @@ -9,6 +9,14 @@ config SOC_DEVICE need different parameters or quirks enabled depending on the specific device variant in use. +config SOC_AMD_VERSAL2 + bool "Enable SoC Device ID driver for AMD Versal Gen 2" + depends on SOC_DEVICE && ARCH_VERSAL2 + help + Enable this option to select SoC device id driver for AMD Versal Gen 2. + This allows other drivers to verify the SoC familiy & revision using + matching SoC attributes. + config SOC_DEVICE_TI_K3 depends on SOC_DEVICE && ARCH_K3 bool "Enable SoC Device ID driver for TI K3 SoCs" diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index 610bf816d40..5ec89a05316 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile @@ -2,6 +2,7 @@ # # Makefile for the U-Boot SOC specific device drivers. +obj-$(CONFIG_SOC_AMD_VERSAL2) += soc_amd_versal2.o obj-$(CONFIG_SOC_SAMSUNG) += samsung/ obj-$(CONFIG_SOC_TI) += ti/ obj-$(CONFIG_SOC_DEVICE) += soc-uclass.o diff --git a/drivers/soc/soc_amd_versal2.c b/drivers/soc/soc_amd_versal2.c new file mode 100644 index 00000000000..66bcb22b4fa --- /dev/null +++ b/drivers/soc/soc_amd_versal2.c @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * AMD Versal Gen 2 SOC driver + * + * Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc. + */ + +#include <dm.h> +#include <soc.h> +#include <zynqmp_firmware.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> + +#include <linux/bitfield.h> + +/* + * v1 -> 0x10 - ES1 + * v2 -> 0x20 - Production + */ +static const char versal2_family[] = "Versal Gen 2"; + +struct soc_amd_versal2_priv { + const char *family; + char revision; +}; + +static int soc_amd_versal2_get_family(struct udevice *dev, char *buf, int size) +{ + struct soc_amd_versal2_priv *priv = dev_get_priv(dev); + + return snprintf(buf, size, "%s", priv->family); +} + +static int soc_amd_versal2_get_revision(struct udevice *dev, char *buf, int size) +{ + struct soc_amd_versal2_priv *priv = dev_get_priv(dev); + + return snprintf(buf, size, "v%d", priv->revision); +} + +static const struct soc_ops soc_amd_versal2_ops = { + .get_family = soc_amd_versal2_get_family, + .get_revision = soc_amd_versal2_get_revision, +}; + +static int soc_amd_versal2_probe(struct udevice *dev) +{ + struct soc_amd_versal2_priv *priv = dev_get_priv(dev); + u32 ret_payload[PAYLOAD_ARG_CNT]; + int ret; + + priv->family = versal2_family; + + if (IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE)) { + ret = xilinx_pm_request(PM_GET_CHIPID, 0, 0, 0, 0, + ret_payload); + if (ret) + return ret; + } else { + ret_payload[2] = readl(PMC_TAP_VERSION); + if (!ret_payload[2]) + return -EINVAL; + } + + priv->revision = FIELD_GET(PS_VERSION_MASK, ret_payload[2]); + + return 0; +} + +U_BOOT_DRIVER(soc_amd_versal2) = { + .name = "soc_amd_versal2", + .id = UCLASS_SOC, + .ops = &soc_amd_versal2_ops, + .probe = soc_amd_versal2_probe, + .priv_auto = sizeof(struct soc_amd_versal2_priv), + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/soc/soc_ti_k3.c b/drivers/soc/soc_ti_k3.c index b585e47d46f..f948914d218 100644 --- a/drivers/soc/soc_ti_k3.c +++ b/drivers/soc/soc_ti_k3.c @@ -23,33 +23,36 @@ static const char *get_family_string(u32 idreg) soc = (idreg & JTAG_ID_PARTNO_MASK) >> JTAG_ID_PARTNO_SHIFT; switch (soc) { + case JTAG_ID_PARTNO_AM62X: + family = "AM62X"; + break; + case JTAG_ID_PARTNO_AM62AX: + family = "AM62AX"; + break; + case JTAG_ID_PARTNO_AM62PX: + family = "AM62PX"; + break; + case JTAG_ID_PARTNO_AM64X: + family = "AM64X"; + break; case JTAG_ID_PARTNO_AM65X: family = "AM65X"; break; - case JTAG_ID_PARTNO_J721E: - family = "J721E"; - break; case JTAG_ID_PARTNO_J7200: family = "J7200"; break; - case JTAG_ID_PARTNO_AM64X: - family = "AM64X"; + case JTAG_ID_PARTNO_J721E: + family = "J721E"; break; case JTAG_ID_PARTNO_J721S2: family = "J721S2"; break; - case JTAG_ID_PARTNO_AM62X: - family = "AM62X"; - break; - case JTAG_ID_PARTNO_AM62AX: - family = "AM62AX"; + case JTAG_ID_PARTNO_J722S: + family = "J722S"; break; case JTAG_ID_PARTNO_J784S4: family = "J784S4"; break; - case JTAG_ID_PARTNO_AM62PX: - family = "AM62PX"; - break; default: family = "Unknown Silicon"; }; diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 35030ab3556..cd785aefd56 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -156,7 +156,7 @@ config CQSPI_REF_CLK config CADENCE_OSPI_VERSAL bool "Configure Versal OSPI" - depends on (ARCH_VERSAL || ARCH_VERSAL_NET) && CADENCE_QSPI + depends on (ARCH_VERSAL || ARCH_VERSAL_NET || ARCH_VERSAL2) && CADENCE_QSPI imply DM_GPIO help This option is used to enable Versal OSPI DMA operations which diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index 75e52232010..9c466f8695e 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -253,7 +253,8 @@ static int cadence_spi_probe(struct udevice *bus) /* Versal and Versal-NET use spi calibration to set read delay */ if (CONFIG_IS_ENABLED(ARCH_VERSAL) || - CONFIG_IS_ENABLED(ARCH_VERSAL_NET)) + CONFIG_IS_ENABLED(ARCH_VERSAL_NET) || + CONFIG_IS_ENABLED(ARCH_VERSAL2)) if (priv->read_delay >= 0) priv->read_delay = -1; diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c index 61349a4da53..ae795e50b0a 100644 --- a/drivers/spi/zynqmp_gqspi.c +++ b/drivers/spi/zynqmp_gqspi.c @@ -106,7 +106,8 @@ #define TAP_DLY_BYPASS_LQSPI_RX_SHIFT 2 #define GQSPI_DATA_DLY_ADJ_OFST 0x000001F8 #define IOU_TAPDLY_BYPASS_OFST !(IS_ENABLED(CONFIG_ARCH_VERSAL) || \ - IS_ENABLED(CONFIG_ARCH_VERSAL_NET)) ? \ + IS_ENABLED(CONFIG_ARCH_VERSAL_NET) || \ + IS_ENABLED(CONFIG_ARCH_VERSAL2)) ? \ 0xFF180390 : 0xF103003C #define GQSPI_LPBK_DLY_ADJ_LPBK_MASK 0x00000020 #define GQSPI_FREQ_37_5MHZ 37500000 @@ -316,7 +317,8 @@ static void zynqmp_qspi_set_tapdelay(struct udevice *bus, u32 baudrateval) __func__, clk_rate, baudrateval, reqhz); if (!(IS_ENABLED(CONFIG_ARCH_VERSAL) || - IS_ENABLED(CONFIG_ARCH_VERSAL_NET))) { + IS_ENABLED(CONFIG_ARCH_VERSAL_NET) || + IS_ENABLED(CONFIG_ARCH_VERSAL2))) { if (reqhz <= GQSPI_FREQ_40MHZ) { tapdlybypass = TAP_DLY_BYPASS_LQSPI_RX_VALUE << TAP_DLY_BYPASS_LQSPI_RX_SHIFT; diff --git a/drivers/watchdog/wdt-uclass.c b/drivers/watchdog/wdt-uclass.c index c88312ec721..10be334e9ed 100644 --- a/drivers/watchdog/wdt-uclass.c +++ b/drivers/watchdog/wdt-uclass.c @@ -17,17 +17,20 @@ #include <asm/global_data.h> #include <dm/device-internal.h> #include <dm/lists.h> +#include <linux/kernel.h> DECLARE_GLOBAL_DATA_PTR; #define WATCHDOG_TIMEOUT_SECS (CONFIG_WATCHDOG_TIMEOUT_MSECS / 1000) struct wdt_priv { + /* The udevice owning this wdt_priv. */ + struct udevice *dev; /* Timeout, in seconds, to configure this device to. */ u32 timeout; /* * Time, in milliseconds, between calling the device's ->reset() - * method from watchdog_reset(). + * method from schedule(). */ ulong reset_period; /* @@ -40,18 +43,17 @@ struct wdt_priv { /* autostart */ bool autostart; - struct cyclic_info *cyclic; + struct cyclic_info cyclic; }; -static void wdt_cyclic(void *ctx) +static void wdt_cyclic(struct cyclic_info *c) { - struct udevice *dev = ctx; - struct wdt_priv *priv; + struct wdt_priv *priv = container_of(c, struct wdt_priv, cyclic); + struct udevice *dev = priv->dev; if (!device_active(dev)) return; - priv = dev_get_uclass_priv(dev); if (!priv->running) return; @@ -121,24 +123,20 @@ int wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags) struct wdt_priv *priv = dev_get_uclass_priv(dev); char str[16]; - priv->running = true; - memset(str, 0, 16); if (IS_ENABLED(CONFIG_WATCHDOG)) { + if (priv->running) + cyclic_unregister(&priv->cyclic); + /* Register the watchdog driver as a cyclic function */ - priv->cyclic = cyclic_register(wdt_cyclic, - priv->reset_period * 1000, - dev->name, dev); - if (!priv->cyclic) { - printf("cyclic_register for %s failed\n", - dev->name); - return -ENODEV; - } else { - snprintf(str, 16, "every %ldms", - priv->reset_period); - } + cyclic_register(&priv->cyclic, wdt_cyclic, + priv->reset_period * 1000, + dev->name); + + snprintf(str, 16, "every %ldms", priv->reset_period); } + priv->running = true; printf("WDT: Started %s with%s servicing %s (%ds timeout)\n", dev->name, IS_ENABLED(CONFIG_WATCHDOG) ? "" : "out", str, (u32)lldiv(timeout_ms, 1000)); @@ -159,6 +157,9 @@ int wdt_stop(struct udevice *dev) if (ret == 0) { struct wdt_priv *priv = dev_get_uclass_priv(dev); + if (IS_ENABLED(CONFIG_WATCHDOG) && priv->running) + cyclic_unregister(&priv->cyclic); + priv->running = false; } @@ -221,21 +222,6 @@ int wdt_expire_now(struct udevice *dev, ulong flags) return ret; } -#if defined(CONFIG_WATCHDOG) -/* - * Called by macro WATCHDOG_RESET. This function be called *very* early, - * so we need to make sure, that the watchdog driver is ready before using - * it in this function. - */ -void watchdog_reset(void) -{ - /* - * Empty function for now. The actual WDT handling is now done in - * the cyclic function instead. - */ -} -#endif - static int wdt_pre_probe(struct udevice *dev) { u32 timeout = WATCHDOG_TIMEOUT_SECS; @@ -257,12 +243,13 @@ static int wdt_pre_probe(struct udevice *dev) autostart = true; } priv = dev_get_uclass_priv(dev); + priv->dev = dev; priv->timeout = timeout; priv->reset_period = reset_period; priv->autostart = autostart; /* * Pretend this device was last reset "long" ago so the first - * watchdog_reset will actually call its ->reset method. + * schedule() will actually call its ->reset method. */ priv->next_reset = get_timer(0); |