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-rw-r--r--drivers/phy/Kconfig6
-rw-r--r--drivers/phy/Makefile1
-rw-r--r--drivers/phy/phy-qcom-ipq4019-usb.c145
-rw-r--r--drivers/reset/Kconfig8
-rw-r--r--drivers/reset/Makefile1
-rw-r--r--drivers/reset/reset-ipq4019.c173
-rw-r--r--drivers/smem/Kconfig2
-rw-r--r--drivers/usb/dwc3/dwc3-generic.c1
8 files changed, 336 insertions, 1 deletions
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 9c775107e9c..8da00a259d7 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -125,6 +125,12 @@ config STI_USB_PHY
used by USB2 and USB3 Host controllers available on
STiH407 SoC families.
+config PHY_QCOM_IPQ4019_USB
+ tristate "Qualcomm IPQ4019 USB PHY driver"
+ depends on PHY && ARCH_IPQ40XX
+ help
+ Support for the USB PHY-s on Qualcomm IPQ40xx SoC-s.
+
config PHY_RCAR_GEN2
tristate "Renesas R-Car Gen2 USB PHY"
depends on PHY && RCAR_GEN2
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 74e8d931d38..009f353baf4 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_PHY_SANDBOX) += sandbox-phy.o
obj-$(CONFIG_$(SPL_)PIPE3_PHY) += ti-pipe3-phy.o
obj-$(CONFIG_AM654_PHY) += phy-ti-am654.o
obj-$(CONFIG_STI_USB_PHY) += sti_usb_phy.o
+obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o
obj-$(CONFIG_PHY_RCAR_GEN2) += phy-rcar-gen2.o
obj-$(CONFIG_PHY_RCAR_GEN3) += phy-rcar-gen3.o
obj-$(CONFIG_PHY_STM32_USBPHYC) += phy-stm32-usbphyc.o
diff --git a/drivers/phy/phy-qcom-ipq4019-usb.c b/drivers/phy/phy-qcom-ipq4019-usb.c
new file mode 100644
index 00000000000..465f0d3a01e
--- /dev/null
+++ b/drivers/phy/phy-qcom-ipq4019-usb.c
@@ -0,0 +1,145 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 Sartura Ltd.
+ *
+ * Author: Robert Marko <robert.marko@sartura.hr>
+ *
+ * Based on Linux driver
+ */
+
+#include <clk.h>
+#include <common.h>
+#include <dm.h>
+#include <generic-phy.h>
+#include <log.h>
+#include <reset.h>
+#include <asm/io.h>
+#include <linux/delay.h>
+
+struct ipq4019_usb_phy {
+ phys_addr_t base;
+ struct reset_ctl por_rst;
+ struct reset_ctl srif_rst;
+};
+
+static int ipq4019_ss_phy_power_off(struct phy *_phy)
+{
+ struct ipq4019_usb_phy *phy = dev_get_priv(_phy->dev);
+
+ reset_assert(&phy->por_rst);
+ mdelay(10);
+
+ return 0;
+}
+
+static int ipq4019_ss_phy_power_on(struct phy *_phy)
+{
+ struct ipq4019_usb_phy *phy = dev_get_priv(_phy->dev);
+
+ ipq4019_ss_phy_power_off(_phy);
+
+ reset_deassert(&phy->por_rst);
+
+ return 0;
+}
+
+static struct phy_ops ipq4019_usb_ss_phy_ops = {
+ .power_on = ipq4019_ss_phy_power_on,
+ .power_off = ipq4019_ss_phy_power_off,
+};
+
+static int ipq4019_usb_ss_phy_probe(struct udevice *dev)
+{
+ struct ipq4019_usb_phy *phy = dev_get_priv(dev);
+ int ret;
+
+ phy->base = dev_read_addr(dev);
+ if (phy->base == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ ret = reset_get_by_name(dev, "por_rst", &phy->por_rst);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static const struct udevice_id ipq4019_usb_ss_phy_ids[] = {
+ { .compatible = "qcom,usb-ss-ipq4019-phy" },
+ { }
+};
+
+U_BOOT_DRIVER(ipq4019_usb_ss_phy) = {
+ .name = "ipq4019-usb-ss-phy",
+ .id = UCLASS_PHY,
+ .of_match = ipq4019_usb_ss_phy_ids,
+ .ops = &ipq4019_usb_ss_phy_ops,
+ .probe = ipq4019_usb_ss_phy_probe,
+ .priv_auto_alloc_size = sizeof(struct ipq4019_usb_phy),
+};
+
+static int ipq4019_hs_phy_power_off(struct phy *_phy)
+{
+ struct ipq4019_usb_phy *phy = dev_get_priv(_phy->dev);
+
+ reset_assert(&phy->por_rst);
+ mdelay(10);
+
+ reset_assert(&phy->srif_rst);
+ mdelay(10);
+
+ return 0;
+}
+
+static int ipq4019_hs_phy_power_on(struct phy *_phy)
+{
+ struct ipq4019_usb_phy *phy = dev_get_priv(_phy->dev);
+
+ ipq4019_hs_phy_power_off(_phy);
+
+ reset_deassert(&phy->srif_rst);
+ mdelay(10);
+
+ reset_deassert(&phy->por_rst);
+
+ return 0;
+}
+
+static struct phy_ops ipq4019_usb_hs_phy_ops = {
+ .power_on = ipq4019_hs_phy_power_on,
+ .power_off = ipq4019_hs_phy_power_off,
+};
+
+static int ipq4019_usb_hs_phy_probe(struct udevice *dev)
+{
+ struct ipq4019_usb_phy *phy = dev_get_priv(dev);
+ int ret;
+
+ phy->base = dev_read_addr(dev);
+ if (phy->base == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ ret = reset_get_by_name(dev, "por_rst", &phy->por_rst);
+ if (ret)
+ return ret;
+
+ ret = reset_get_by_name(dev, "srif_rst", &phy->srif_rst);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static const struct udevice_id ipq4019_usb_hs_phy_ids[] = {
+ { .compatible = "qcom,usb-hs-ipq4019-phy" },
+ { }
+};
+
+U_BOOT_DRIVER(ipq4019_usb_hs_phy) = {
+ .name = "ipq4019-usb-hs-phy",
+ .id = UCLASS_PHY,
+ .of_match = ipq4019_usb_hs_phy_ids,
+ .ops = &ipq4019_usb_hs_phy_ops,
+ .probe = ipq4019_usb_hs_phy_probe,
+ .priv_auto_alloc_size = sizeof(struct ipq4019_usb_phy),
+};
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 253902ff574..3fdfe4a6cb0 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -148,6 +148,14 @@ config RESET_IMX7
help
Support for reset controller on i.MX7/8 SoCs.
+config RESET_IPQ419
+ bool "Reset driver for Qualcomm IPQ40xx SoCs"
+ depends on DM_RESET && ARCH_IPQ40XX
+ default y
+ help
+ Support for reset controller on Qualcomm
+ IPQ40xx SoCs.
+
config RESET_SIFIVE
bool "Reset Driver for SiFive SoC's"
depends on DM_RESET && CLK_SIFIVE_FU540_PRCI && TARGET_SIFIVE_FU540
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 3c7f066ae39..5176da58853 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -23,6 +23,7 @@ obj-$(CONFIG_RESET_MTMIPS) += reset-mtmips.o
obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
obj-$(CONFIG_RESET_HISILICON) += reset-hisilicon.o
obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
+obj-$(CONFIG_RESET_IPQ419) += reset-ipq4019.o
obj-$(CONFIG_RESET_SIFIVE) += reset-sifive.o
obj-$(CONFIG_RESET_SYSCON) += reset-syscon.o
obj-$(CONFIG_RESET_RASPBERRYPI) += reset-raspberrypi.o
diff --git a/drivers/reset/reset-ipq4019.c b/drivers/reset/reset-ipq4019.c
new file mode 100644
index 00000000000..f216db4ce5c
--- /dev/null
+++ b/drivers/reset/reset-ipq4019.c
@@ -0,0 +1,173 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2020 Sartura Ltd.
+ *
+ * Author: Robert Marko <robert.marko@sartura.hr>
+ *
+ * Based on Linux driver
+ */
+
+#include <asm/io.h>
+#include <common.h>
+#include <dm.h>
+#include <dt-bindings/reset/qcom,ipq4019-reset.h>
+#include <reset-uclass.h>
+#include <linux/bitops.h>
+#include <malloc.h>
+
+struct ipq4019_reset_priv {
+ phys_addr_t base;
+};
+
+struct qcom_reset_map {
+ unsigned int reg;
+ u8 bit;
+};
+
+static const struct qcom_reset_map gcc_ipq4019_resets[] = {
+ [WIFI0_CPU_INIT_RESET] = { 0x1f008, 5 },
+ [WIFI0_RADIO_SRIF_RESET] = { 0x1f008, 4 },
+ [WIFI0_RADIO_WARM_RESET] = { 0x1f008, 3 },
+ [WIFI0_RADIO_COLD_RESET] = { 0x1f008, 2 },
+ [WIFI0_CORE_WARM_RESET] = { 0x1f008, 1 },
+ [WIFI0_CORE_COLD_RESET] = { 0x1f008, 0 },
+ [WIFI1_CPU_INIT_RESET] = { 0x20008, 5 },
+ [WIFI1_RADIO_SRIF_RESET] = { 0x20008, 4 },
+ [WIFI1_RADIO_WARM_RESET] = { 0x20008, 3 },
+ [WIFI1_RADIO_COLD_RESET] = { 0x20008, 2 },
+ [WIFI1_CORE_WARM_RESET] = { 0x20008, 1 },
+ [WIFI1_CORE_COLD_RESET] = { 0x20008, 0 },
+ [USB3_UNIPHY_PHY_ARES] = { 0x1e038, 5 },
+ [USB3_HSPHY_POR_ARES] = { 0x1e038, 4 },
+ [USB3_HSPHY_S_ARES] = { 0x1e038, 2 },
+ [USB2_HSPHY_POR_ARES] = { 0x1e01c, 4 },
+ [USB2_HSPHY_S_ARES] = { 0x1e01c, 2 },
+ [PCIE_PHY_AHB_ARES] = { 0x1d010, 11 },
+ [PCIE_AHB_ARES] = { 0x1d010, 10 },
+ [PCIE_PWR_ARES] = { 0x1d010, 9 },
+ [PCIE_PIPE_STICKY_ARES] = { 0x1d010, 8 },
+ [PCIE_AXI_M_STICKY_ARES] = { 0x1d010, 7 },
+ [PCIE_PHY_ARES] = { 0x1d010, 6 },
+ [PCIE_PARF_XPU_ARES] = { 0x1d010, 5 },
+ [PCIE_AXI_S_XPU_ARES] = { 0x1d010, 4 },
+ [PCIE_AXI_M_VMIDMT_ARES] = { 0x1d010, 3 },
+ [PCIE_PIPE_ARES] = { 0x1d010, 2 },
+ [PCIE_AXI_S_ARES] = { 0x1d010, 1 },
+ [PCIE_AXI_M_ARES] = { 0x1d010, 0 },
+ [ESS_RESET] = { 0x12008, 0},
+ [GCC_BLSP1_BCR] = {0x01000, 0},
+ [GCC_BLSP1_QUP1_BCR] = {0x02000, 0},
+ [GCC_BLSP1_UART1_BCR] = {0x02038, 0},
+ [GCC_BLSP1_QUP2_BCR] = {0x03008, 0},
+ [GCC_BLSP1_UART2_BCR] = {0x03028, 0},
+ [GCC_BIMC_BCR] = {0x04000, 0},
+ [GCC_TLMM_BCR] = {0x05000, 0},
+ [GCC_IMEM_BCR] = {0x0E000, 0},
+ [GCC_ESS_BCR] = {0x12008, 0},
+ [GCC_PRNG_BCR] = {0x13000, 0},
+ [GCC_BOOT_ROM_BCR] = {0x13008, 0},
+ [GCC_CRYPTO_BCR] = {0x16000, 0},
+ [GCC_SDCC1_BCR] = {0x18000, 0},
+ [GCC_SEC_CTRL_BCR] = {0x1A000, 0},
+ [GCC_AUDIO_BCR] = {0x1B008, 0},
+ [GCC_QPIC_BCR] = {0x1C000, 0},
+ [GCC_PCIE_BCR] = {0x1D000, 0},
+ [GCC_USB2_BCR] = {0x1E008, 0},
+ [GCC_USB2_PHY_BCR] = {0x1E018, 0},
+ [GCC_USB3_BCR] = {0x1E024, 0},
+ [GCC_USB3_PHY_BCR] = {0x1E034, 0},
+ [GCC_SYSTEM_NOC_BCR] = {0x21000, 0},
+ [GCC_PCNOC_BCR] = {0x2102C, 0},
+ [GCC_DCD_BCR] = {0x21038, 0},
+ [GCC_SNOC_BUS_TIMEOUT0_BCR] = {0x21064, 0},
+ [GCC_SNOC_BUS_TIMEOUT1_BCR] = {0x2106C, 0},
+ [GCC_SNOC_BUS_TIMEOUT2_BCR] = {0x21074, 0},
+ [GCC_SNOC_BUS_TIMEOUT3_BCR] = {0x2107C, 0},
+ [GCC_PCNOC_BUS_TIMEOUT0_BCR] = {0x21084, 0},
+ [GCC_PCNOC_BUS_TIMEOUT1_BCR] = {0x2108C, 0},
+ [GCC_PCNOC_BUS_TIMEOUT2_BCR] = {0x21094, 0},
+ [GCC_PCNOC_BUS_TIMEOUT3_BCR] = {0x2109C, 0},
+ [GCC_PCNOC_BUS_TIMEOUT4_BCR] = {0x210A4, 0},
+ [GCC_PCNOC_BUS_TIMEOUT5_BCR] = {0x210AC, 0},
+ [GCC_PCNOC_BUS_TIMEOUT6_BCR] = {0x210B4, 0},
+ [GCC_PCNOC_BUS_TIMEOUT7_BCR] = {0x210BC, 0},
+ [GCC_PCNOC_BUS_TIMEOUT8_BCR] = {0x210C4, 0},
+ [GCC_PCNOC_BUS_TIMEOUT9_BCR] = {0x210CC, 0},
+ [GCC_TCSR_BCR] = {0x22000, 0},
+ [GCC_MPM_BCR] = {0x24000, 0},
+ [GCC_SPDM_BCR] = {0x25000, 0},
+};
+
+static int ipq4019_reset_assert(struct reset_ctl *rst)
+{
+ struct ipq4019_reset_priv *priv = dev_get_priv(rst->dev);
+ const struct qcom_reset_map *reset_map = gcc_ipq4019_resets;
+ const struct qcom_reset_map *map;
+ u32 value;
+
+ map = &reset_map[rst->id];
+
+ value = readl(priv->base + map->reg);
+ value |= BIT(map->bit);
+ writel(value, priv->base + map->reg);
+
+ return 0;
+}
+
+static int ipq4019_reset_deassert(struct reset_ctl *rst)
+{
+ struct ipq4019_reset_priv *priv = dev_get_priv(rst->dev);
+ const struct qcom_reset_map *reset_map = gcc_ipq4019_resets;
+ const struct qcom_reset_map *map;
+ u32 value;
+
+ map = &reset_map[rst->id];
+
+ value = readl(priv->base + map->reg);
+ value &= ~BIT(map->bit);
+ writel(value, priv->base + map->reg);
+
+ return 0;
+}
+
+static int ipq4019_reset_free(struct reset_ctl *rst)
+{
+ return 0;
+}
+
+static int ipq4019_reset_request(struct reset_ctl *rst)
+{
+ return 0;
+}
+
+static const struct reset_ops ipq4019_reset_ops = {
+ .request = ipq4019_reset_request,
+ .rfree = ipq4019_reset_free,
+ .rst_assert = ipq4019_reset_assert,
+ .rst_deassert = ipq4019_reset_deassert,
+};
+
+static const struct udevice_id ipq4019_reset_ids[] = {
+ { .compatible = "qcom,gcc-reset-ipq4019" },
+ { }
+};
+
+static int ipq4019_reset_probe(struct udevice *dev)
+{
+ struct ipq4019_reset_priv *priv = dev_get_priv(dev);
+
+ priv->base = dev_read_addr(dev);
+ if (priv->base == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ return 0;
+}
+
+U_BOOT_DRIVER(ipq4019_reset) = {
+ .name = "ipq4019_reset",
+ .id = UCLASS_RESET,
+ .of_match = ipq4019_reset_ids,
+ .ops = &ipq4019_reset_ops,
+ .probe = ipq4019_reset_probe,
+ .priv_auto_alloc_size = sizeof(struct ipq4019_reset_priv),
+};
diff --git a/drivers/smem/Kconfig b/drivers/smem/Kconfig
index 7169d0f205a..73d51b3a7a4 100644
--- a/drivers/smem/Kconfig
+++ b/drivers/smem/Kconfig
@@ -15,7 +15,7 @@ config SANDBOX_SMEM
config MSM_SMEM
bool "Qualcomm Shared Memory Manager (SMEM)"
depends on DM
- depends on ARCH_SNAPDRAGON
+ depends on ARCH_SNAPDRAGON || ARCH_IPQ40XX
help
Enable support for the Qualcomm Shared Memory Manager.
The driver provides an interface to items in a heap shared among all
diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
index 551f682024c..7fbf2502faa 100644
--- a/drivers/usb/dwc3/dwc3-generic.c
+++ b/drivers/usb/dwc3/dwc3-generic.c
@@ -449,6 +449,7 @@ static const struct udevice_id dwc3_glue_ids[] = {
{ .compatible = "ti,am654-dwc3" },
{ .compatible = "rockchip,rk3328-dwc3" },
{ .compatible = "rockchip,rk3399-dwc3" },
+ { .compatible = "qcom,dwc3" },
{ }
};
generated by cgit v1.2.3 (git 2.0.4) at 2025-07-20 19:54:44 +0000