41 files changed, 1493 insertions, 83 deletions

diff --git a/drivers/input/Kconfig b/drivers/input/Kconfig
index c2b365af11d..c09f0ae795e 100644
--- a/drivers/input/Kconfig
+++ b/drivers/input/Kconfig
@@ -55,6 +55,12 @@ config BUTTON_KEYBOARD
 	  dt node to define button-event mapping.
 	  For example, an arrows and enter may be implemented to navigate boot menu.
 
+config CPCAP_POWER_BUTTON
+	bool "Enable power button of CPCAP PMIC support"
+	depends on DM_KEYBOARD && DM_PMIC_CPCAP
+	help
+	  Enable support for a dedicated power button of the CPCAP PMIC.
+
 config CROS_EC_KEYB
 	bool "Enable Chrome OS EC keyboard support"
 	depends on INPUT
diff --git a/drivers/input/Makefile b/drivers/input/Makefile
index 8d4107b8848..1303fcdb0b7 100644
--- a/drivers/input/Makefile
+++ b/drivers/input/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_$(PHASE_)CROS_EC_KEYB) += cros_ec_keyb.o
 obj-$(CONFIG_$(PHASE_)OF_CONTROL) += key_matrix.o
 obj-$(CONFIG_$(PHASE_)DM_KEYBOARD) += input.o keyboard-uclass.o
 obj-$(CONFIG_BUTTON_KEYBOARD) += button_kbd.o
+obj-$(CONFIG_CPCAP_POWER_BUTTON) += cpcap_pwrbutton.o
 
 ifndef CONFIG_XPL_BUILD
 
diff --git a/drivers/input/cpcap_pwrbutton.c b/drivers/input/cpcap_pwrbutton.c
new file mode 100644
index 00000000000..c8ad39d33ca
--- /dev/null
+++ b/drivers/input/cpcap_pwrbutton.c
@@ -0,0 +1,134 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *  Copyright(C) 2025 Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <stdlib.h>
+#include <dm.h>
+#include <input.h>
+#include <keyboard.h>
+#include <power/pmic.h>
+#include <power/cpcap.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/input.h>
+
+static const unsigned int cpcpap_to_reg[] = {
+	CPCAP_REG_INT1,
+	CPCAP_REG_INT2,
+	CPCAP_REG_INT3,
+	CPCAP_REG_INT4,
+};
+
+/**
+ * struct cpcap_pwrbutton_priv
+ *
+ * @bank: id of interrupt bank co-responding to an IRQ register
+ * @id: id of interrupt pin co-responding to the bit in IRQ register
+ * @keycode: linux key code
+ * @old_state: holder of last button state
+ * @skip: holder of keycode skip state. This is required since both pressing
+ *        and releasing generate same event and cause key send duplication.
+ */
+struct cpcap_pwrbutton_priv {
+	u32 bank;
+	u32 id;
+
+	u32 keycode;
+
+	bool old_state;
+	bool skip;
+};
+
+static int cpcap_pwrbutton_read_keys(struct input_config *input)
+{
+	struct udevice *dev = input->dev;
+	struct cpcap_pwrbutton_priv *priv = dev_get_priv(dev);
+	u32 value, state_changed;
+	bool state;
+
+	value = pmic_reg_read(dev->parent, cpcpap_to_reg[priv->bank]) &
+			      BIT(priv->id);
+
+	/* Interrupt bit is cleared by writing it to interrupt reg */
+	pmic_reg_write(dev->parent, cpcpap_to_reg[priv->bank], BIT(priv->id));
+
+	state = value >> priv->id;
+	state_changed = state != priv->old_state;
+
+	if (state_changed && !priv->skip) {
+		priv->old_state = state;
+		input_add_keycode(input, priv->keycode, state);
+	}
+
+	if (state)
+		priv->skip = !priv->skip;
+
+	return 0;
+}
+
+static int cpcap_pwrbutton_of_to_plat(struct udevice *dev)
+{
+	struct cpcap_pwrbutton_priv *priv = dev_get_priv(dev);
+	ofnode irq_parent;
+	u32 irq_desc;
+	int ret;
+
+	/* Check interrupt parent, driver supports only CPCAP as parent */
+	irq_parent = ofnode_parse_phandle(dev_ofnode(dev), "interrupt-parent", 0);
+	if (!ofnode_device_is_compatible(irq_parent, "motorola,cpcap"))
+		return -EINVAL;
+
+	ret = dev_read_u32(dev, "interrupts", &irq_desc);
+	if (ret)
+		return ret;
+
+	/* IRQ registers are 16 bit wide */
+	priv->bank = irq_desc / 16;
+	priv->id = irq_desc % 16;
+
+	ret = dev_read_u32(dev, "linux,code", &priv->keycode);
+	if (ret)
+		return ret;
+
+	priv->old_state = false;
+	priv->skip = false;
+	return 0;
+}
+
+static int cpcap_pwrbutton_probe(struct udevice *dev)
+{
+	struct keyboard_priv *uc_priv = dev_get_uclass_priv(dev);
+	struct stdio_dev *sdev = &uc_priv->sdev;
+	struct input_config *input = &uc_priv->input;
+	int ret;
+
+	input_init(input, false);
+	input_add_tables(input, false);
+
+	/* Register the device */
+	input->dev = dev;
+	input->read_keys = cpcap_pwrbutton_read_keys;
+	strcpy(sdev->name, "cpcap-pwrbutton");
+	ret = input_stdio_register(sdev);
+	if (ret) {
+		log_debug("%s: input_stdio_register() failed\n", __func__);
+		return ret;
+	}
+
+	return 0;
+}
+
+static const struct udevice_id cpcap_pwrbutton_ids[] = {
+	{ .compatible = "motorola,cpcap-pwrbutton" },
+	{ }
+};
+
+U_BOOT_DRIVER(cpcap_pwrbutton) = {
+	.name		= "cpcap_pwrbutton",
+	.id		= UCLASS_KEYBOARD,
+	.of_match	= cpcap_pwrbutton_ids,
+	.of_to_plat	= cpcap_pwrbutton_of_to_plat,
+	.probe		= cpcap_pwrbutton_probe,
+	.priv_auto	= sizeof(struct cpcap_pwrbutton_priv),
+};
diff --git a/drivers/pinctrl/tegra/funcmux-tegra20.c b/drivers/pinctrl/tegra/funcmux-tegra20.c
index 951ae196161..f60d5aad3a4 100644
--- a/drivers/pinctrl/tegra/funcmux-tegra20.c
+++ b/drivers/pinctrl/tegra/funcmux-tegra20.c
@@ -62,8 +62,15 @@ int funcmux_select(enum periph_id id, int config)
 			pinmux_tristate_disable(PMUX_PINGRP_SDIO1);
 			bad_config = 0;
 			break;
+		case FUNCMUX_UART1_SDB_SDD:
+			pinmux_set_func(PMUX_PINGRP_SDB, PMUX_FUNC_UARTA);
+			pinmux_set_func(PMUX_PINGRP_SDD, PMUX_FUNC_UARTA);
+			pinmux_tristate_disable(PMUX_PINGRP_SDB);
+			pinmux_tristate_disable(PMUX_PINGRP_SDD);
+			bad_config = 0;
+			break;
 		}
-		if (!bad_config) {
+		if (!bad_config && config != FUNCMUX_UART1_SDB_SDD) {
 			/*
 			 * Tegra appears to boot with function UARTA pre-
 			 * selected on mux group SDB. If two mux groups are
diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c
index b04be168bc8..bc02825ee1f 100644
--- a/drivers/pinctrl/tegra/pinctrl-tegra.c
+++ b/drivers/pinctrl/tegra/pinctrl-tegra.c
@@ -14,7 +14,7 @@
 static void tegra_pinctrl_set_drive(struct udevice *config, int drvcnt)
 {
 	struct pmux_drvgrp_config *drive_group;
-	int i, ret, pad_id;
+	int i, ret, pad_id, count = 0;
 	const char **pads;
 
 	drive_group = kmalloc_array(drvcnt, sizeof(*drive_group), GFP_KERNEL);
@@ -46,21 +46,32 @@ static void tegra_pinctrl_set_drive(struct udevice *config, int drvcnt)
 		goto exit;
 	}
 
+	/*
+	 * i goes through all drive instances defined, while
+	 * count is increased only if a valid configuration is found
+	 */
 	for (i = 0; i < drvcnt; i++) {
 		for (pad_id = 0; pad_id < PMUX_DRVGRP_COUNT; pad_id++)
 			if (tegra_pinctrl_to_drvgrp[pad_id])
 				if (!strcmp(pads[i], tegra_pinctrl_to_drvgrp[pad_id])) {
-					drive_group[i].drvgrp = pad_id;
+					drive_group[count].drvgrp = pad_id;
 					break;
 				}
 
-		debug("%s drvmap: %d, %d, %d, %d, %d\n", pads[i],
-		      drive_group[i].drvgrp, drive_group[i].slwf,
-		      drive_group[i].slwr, drive_group[i].drvup,
-		      drive_group[i].drvdn);
+		if (pad_id == PMUX_DRVGRP_COUNT) {
+			log_debug("%s: drive %s is not valid\n", __func__, pads[i]);
+			continue;
+		}
+
+		log_debug("%s(%d) drvmap: %d, %d, %d, %d, %d\n", pads[count], count,
+			  drive_group[count].drvgrp, drive_group[count].slwf,
+			  drive_group[count].slwr, drive_group[count].drvup,
+			  drive_group[count].drvdn);
+
+		count++;
 	}
 
-	pinmux_config_drvgrp_table(drive_group, drvcnt);
+	pinmux_config_drvgrp_table(drive_group, count);
 
 	free(pads);
 exit:
@@ -71,7 +82,7 @@ exit:
 static void tegra_pinctrl_set_mipipad(struct udevice *config, int padcnt)
 {
 	struct pmux_mipipadctrlgrp_config *mipipad_group;
-	int i, ret, pad_id;
+	int i, ret, pad_id, count = 0;
 	const char *function;
 	const char **pads;
 
@@ -89,6 +100,11 @@ static void tegra_pinctrl_set_mipipad(struct udevice *config, int padcnt)
 				if (!strcmp(function, tegra_pinctrl_to_func[i]))
 					break;
 
+	if (!function || i == PMUX_FUNC_COUNT) {
+		log_debug("%s: pin function is not defined or is not valid\n", __func__);
+		goto exit;
+	}
+
 	mipipad_group[0].func = i;
 
 	for (i = 1; i < padcnt; i++)
@@ -100,16 +116,27 @@ static void tegra_pinctrl_set_mipipad(struct udevice *config, int padcnt)
 		goto exit;
 	}
 
+	/*
+	 * i goes through all pin instances defined, while
+	 * count is increased only if a valid configuration is found
+	 */
 	for (i = 0; i < padcnt; i++) {
 		for (pad_id = 0; pad_id < PMUX_MIPIPADCTRLGRP_COUNT; pad_id++)
 			if (tegra_pinctrl_to_mipipadgrp[pad_id])
 				if (!strcmp(pads[i], tegra_pinctrl_to_mipipadgrp[pad_id])) {
-					mipipad_group[i].grp = pad_id;
+					mipipad_group[count].grp = pad_id;
 					break;
 				}
+
+		if (pad_id == PMUX_MIPIPADCTRLGRP_COUNT) {
+			log_debug("%s: drive %s is not valid\n", __func__, pads[i]);
+			continue;
+		}
+
+		count++;
 	}
 
-	pinmux_config_mipipadctrlgrp_table(mipipad_group, padcnt);
+	pinmux_config_mipipadctrlgrp_table(mipipad_group, count);
 
 	free(pads);
 exit:
@@ -122,7 +149,7 @@ static void tegra_pinctrl_set_mipipad(struct udevice *config, int padcnt) { }
 static void tegra_pinctrl_set_pin(struct udevice *config, int pincnt)
 {
 	struct pmux_pingrp_config *pinmux_group;
-	int i, ret, pin_id;
+	int i, ret, pin_id, count = 0;
 	const char *function;
 	const char **pins;
 
@@ -140,6 +167,11 @@ static void tegra_pinctrl_set_pin(struct udevice *config, int pincnt)
 				if (!strcmp(function, tegra_pinctrl_to_func[i]))
 					break;
 
+	if (!function || i == PMUX_FUNC_COUNT) {
+		log_debug("%s: pin function is not defined or is not valid\n", __func__);
+		goto exit;
+	}
+
 	pinmux_group[0].func = i;
 
 	pinmux_group[0].pull = dev_read_u32_default(config, "nvidia,pull", PMUX_PULL_NORMAL);
@@ -178,20 +210,31 @@ static void tegra_pinctrl_set_pin(struct udevice *config, int pincnt)
 		goto exit;
 	}
 
+	/*
+	 * i goes through all pin instances defined, while
+	 * count is increased only if a valid configuration is found
+	 */
 	for (i = 0; i < pincnt; i++) {
 		for (pin_id = 0; pin_id < PMUX_PINGRP_COUNT; pin_id++)
 			if (tegra_pinctrl_to_pingrp[pin_id])
 				if (!strcmp(pins[i], tegra_pinctrl_to_pingrp[pin_id])) {
-					pinmux_group[i].pingrp = pin_id;
+					pinmux_group[count].pingrp = pin_id;
 					break;
 				}
 
-		debug("%s pinmap: %d, %d, %d, %d\n", pins[i],
-		      pinmux_group[i].pingrp, pinmux_group[i].func,
-		      pinmux_group[i].pull, pinmux_group[i].tristate);
+		if (pin_id == PMUX_PINGRP_COUNT) {
+			log_debug("%s: pin %s is not valid\n", __func__, pins[i]);
+			continue;
+		}
+
+		log_debug("%s(%d) pinmap: %d, %d, %d, %d\n", pins[count], count,
+			  pinmux_group[count].pingrp, pinmux_group[count].func,
+			  pinmux_group[count].pull, pinmux_group[count].tristate);
+
+		count++;
 	}
 
-	pinmux_config_pingrp_table(pinmux_group, pincnt);
+	pinmux_config_pingrp_table(pinmux_group, count);
 
 	free(pins);
 exit:
diff --git a/drivers/pinctrl/tegra/pinctrl-tegra20.c b/drivers/pinctrl/tegra/pinctrl-tegra20.c
index d59b3ec7b5d..c32d590a7e0 100644
--- a/drivers/pinctrl/tegra/pinctrl-tegra20.c
+++ b/drivers/pinctrl/tegra/pinctrl-tegra20.c
@@ -37,6 +37,11 @@ static void tegra_pinctrl_set_pin(struct udevice *config)
 				if (!strcmp(pins[i], tegra_pinctrl_to_pingrp[pin_id]))
 					break;
 
+		if (pin_id == PMUX_PINGRP_COUNT) {
+			log_debug("%s: %s(%d) is not valid\n", __func__, pins[i], pin_id);
+			continue;
+		}
+
 		if (pull >= 0)
 			pinmux_set_pullupdown(pin_id, pull);
 
@@ -58,13 +63,16 @@ static void tegra_pinctrl_set_func(struct udevice *config)
 	const char **pins;
 
 	function = dev_read_string(config, "nvidia,function");
-	if (function)
+	if (function) {
 		for (i = 0; i < PMUX_FUNC_COUNT; i++)
 			if (tegra_pinctrl_to_func[i])
 				if (!strcmp(function, tegra_pinctrl_to_func[i]))
 					break;
 
-	func_id = i;
+		func_id = i;
+	} else {
+		func_id = PMUX_FUNC_COUNT;
+	}
 
 	count = dev_read_string_list(config, "nvidia,pins", &pins);
 	if (count < 0) {
@@ -78,6 +86,12 @@ static void tegra_pinctrl_set_func(struct udevice *config)
 				if (!strcmp(pins[i], tegra_pinctrl_to_pingrp[pin_id]))
 					break;
 
+		if (func_id == PMUX_FUNC_COUNT || pin_id == PMUX_PINGRP_COUNT) {
+			log_debug("%s: pin %s(%d) or function %s(%d) is not valid\n",
+				  __func__, pins[i], pin_id, function, func_id);
+			continue;
+		}
+
 		debug("%s(%d) muxed to %s(%d)\n", pins[i], pin_id, function, func_id);
 
 		pinmux_set_func(pin_id, func_id);
diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig
index bbcbcee4c35..5a61cd45b8c 100644
--- a/drivers/power/pmic/Kconfig
+++ b/drivers/power/pmic/Kconfig
@@ -295,6 +295,16 @@ config DM_PMIC_SANDBOX
 
 	Driver binding info: doc/device-tree-bindings/pmic/sandbox.txt
 
+config DM_PMIC_CPCAP
+	bool "Enable Driver Model for Motorola CPCAP"
+	help
+	The CPCAP is a Motorola/ST-Ericsson creation, a multifunctional IC
+	whose main purpose is power control. It was used in a wide variety of
+	Motorola products, both Tegra and OMAP based. The most notable devices
+	using this PMIC are the Motorola Droid 4, Atrix 4G, and Droid X2.
+	Unlike most PMICs, this one is not I2C based; it uses the SPI bus. The
+	core driver provides both read and write access to the device registers.
+
 config PMIC_S5M8767
 	bool "Enable Driver Model for the Samsung S5M8767 PMIC"
 	---help---
diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
index 4232cb4f5f9..2210b1a64ae 100644
--- a/drivers/power/pmic/Makefile
+++ b/drivers/power/pmic/Makefile
@@ -37,6 +37,7 @@ obj-$(CONFIG_PMIC_TPS65219) += tps65219.o
 obj-$(CONFIG_PMIC_TPS65941) += tps65941.o
 obj-$(CONFIG_PMIC_RAA215300) += raa215300.o
 obj-$(CONFIG_POWER_TPS65218) += pmic_tps65218.o
+obj-$(CONFIG_$(PHASE_)DM_PMIC_CPCAP) += cpcap.o
 
 ifeq ($(CONFIG_$(PHASE_)POWER_LEGACY),y)
 obj-$(CONFIG_POWER_LTC3676) += pmic_ltc3676.o
diff --git a/drivers/power/pmic/cpcap.c b/drivers/power/pmic/cpcap.c
new file mode 100644
index 00000000000..f2076afff43
--- /dev/null
+++ b/drivers/power/pmic/cpcap.c
@@ -0,0 +1,125 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2025 Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <dm.h>
+#include <dm/lists.h>
+#include <log.h>
+#include <power/pmic.h>
+#include <power/cpcap.h>
+#include <spi.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+
+static const struct pmic_child_info pmic_children_info[] = {
+	{ .prefix = "sw", .driver = CPCAP_SW_DRIVER },
+	{ .prefix = "v", .driver = CPCAP_LDO_DRIVER },
+	{ },
+};
+
+static int cpcap_write(struct udevice *dev, uint reg, const uint8_t *buff, int len)
+{
+	u8 buf[4];
+	u16 data = *(u16 *)buff;
+	int ret;
+
+	buf[0] = ((reg >> 8) & 0xff) | 0x80;
+	buf[1] = reg & 0xff;
+	buf[2] = data >> 8 & 0xff;
+	buf[3] = data & 0xff;
+
+	ret = dm_spi_xfer(dev, 32, buf, NULL, SPI_XFER_ONCE);
+
+	log_debug("%s: reg 0x%x, data 0x%04x, ret %d\n", __func__, reg, data, ret);
+
+	return ret;
+}
+
+static int cpcap_read(struct udevice *dev, uint reg, uint8_t *buff, int len)
+{
+	u8 buf[4];
+	int ret;
+
+	buf[0] = (reg >> 8) & 0xff;
+	buf[1] = reg & 0xff;
+	buf[2] = 0;
+	buf[3] = 0;
+
+	ret = dm_spi_xfer(dev, 32, buf, buf, SPI_XFER_ONCE);
+	*buff = (buf[2] << 8) | buf[3];
+
+	log_debug("%s: reg 0x%x, data 0x%04x, ret %d\n", __func__, reg, *buff, ret);
+	return ret;
+}
+
+static int cpcap_bind(struct udevice *dev)
+{
+	ofnode regulators_node;
+	int children;
+
+	/* Regulator device node of PMIC */
+	regulators_node = dev_read_subnode(dev, "regulator");
+	if (!ofnode_valid(regulators_node)) {
+		log_err("%s regulator subnode not found!\n", dev->name);
+		return -ENXIO;
+	}
+
+	/* Actual regulators container */
+	regulators_node = ofnode_find_subnode(regulators_node, "regulators");
+	if (!ofnode_valid(regulators_node)) {
+		log_err("%s regulators subnode not found!\n", dev->name);
+		return -ENXIO;
+	}
+
+	debug("%s: '%s' - found regulators subnode\n", __func__, dev->name);
+
+	children = pmic_bind_children(dev, regulators_node, pmic_children_info);
+	if (!children)
+		log_err("%s - no child found\n", dev->name);
+
+	return dm_scan_fdt_dev(dev);
+}
+
+static int cpcap_probe(struct udevice *dev)
+{
+	struct spi_slave *slave = dev_get_parent_priv(dev);
+	int ret;
+
+	ret = spi_claim_bus(slave);
+	if (ret) {
+		log_err("SPI bus allocation failed (%d)\n", ret);
+		return ret;
+	}
+
+	u16 id = pmic_reg_read(dev, CPCAP_REG_VERSC1);
+
+	u16 ven = (id >> 6) & 0x7;
+	u16 rev = ((id >> 3) & 0x7) | ((id << 3) & 0x38);
+
+	log_debug("%s: vendor %s rev: %i.%i (%x)\n", __func__,
+		  ven == CPCAP_VENDOR_ST ? "ST" : "TI",
+		  CPCAP_REVISION_MAJOR(rev), CPCAP_REVISION_MINOR(rev),
+		  rev);
+	return 0;
+}
+
+static struct dm_pmic_ops cpcap_ops = {
+	.read = cpcap_read,
+	.write = cpcap_write,
+};
+
+static const struct udevice_id cpcap_ids[] = {
+	{ .compatible = "motorola,cpcap" },
+	{ .compatible = "st,6556002" },
+	{ }
+};
+
+U_BOOT_DRIVER(pmic_cpcap) = {
+	.name = "cpcap_pmic",
+	.id = UCLASS_PMIC,
+	.of_match = cpcap_ids,
+	.bind = cpcap_bind,
+	.probe = cpcap_probe,
+	.ops = &cpcap_ops,
+};
diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig
index bab68317cfa..bec2d2d7d49 100644
--- a/drivers/power/regulator/Kconfig
+++ b/drivers/power/regulator/Kconfig
@@ -493,3 +493,12 @@ config REGULATOR_RZG2L_USBPHY
 	  Enable this option to support controlling the VBUS supply in
 	  the USB PHY peripheral of the Renesas RZ/G2L SoC. This option
 	  is required in order to use the USB OTG port.
+
+config DM_REGULATOR_CPCAP
+	bool "Enable driver for CPCAP PMIC regulators"
+	depends on DM_REGULATOR && DM_PMIC_CPCAP
+	---help---
+	Enable implementation of driver-model regulator uclass features for
+	REGULATOR CPCAP. The driver supports both DC-to-DC Step-Down Switching
+	(SW) Regulators and Low-Dropout Linear (LDO) Regulators	found in CPCAP
+	PMIC and implements get/set api for voltage and state.
diff --git a/drivers/power/regulator/Makefile b/drivers/power/regulator/Makefile
index cb6d5b29986..99affa235f3 100644
--- a/drivers/power/regulator/Makefile
+++ b/drivers/power/regulator/Makefile
@@ -44,3 +44,4 @@ obj-$(CONFIG_DM_REGULATOR_SCMI) += scmi_regulator.o
 obj-$(CONFIG_$(PHASE_)DM_REGULATOR_ANATOP) += anatop_regulator.o
 obj-$(CONFIG_DM_REGULATOR_TPS65219) += tps65219_regulator.o
 obj-$(CONFIG_REGULATOR_RZG2L_USBPHY) += rzg2l-usbphy-regulator.o
+obj-$(CONFIG_$(PHASE_)DM_REGULATOR_CPCAP) += cpcap_regulator.o
diff --git a/drivers/power/regulator/cpcap_regulator.c b/drivers/power/regulator/cpcap_regulator.c
new file mode 100644
index 00000000000..04cd6651374
--- /dev/null
+++ b/drivers/power/regulator/cpcap_regulator.c
@@ -0,0 +1,275 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *  Copyright(C) 2025 Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <dm.h>
+#include <power/pmic.h>
+#include <power/regulator.h>
+#include <power/cpcap.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+
+/* CPCAP_REG_ASSIGN2 bits - Resource Assignment 2 */
+#define CPCAP_BIT_VSDIO_SEL		BIT(15)
+#define CPCAP_BIT_VDIG_SEL		BIT(14)
+#define CPCAP_BIT_VCAM_SEL		BIT(13)
+#define CPCAP_BIT_SW6_SEL		BIT(12)
+#define CPCAP_BIT_SW5_SEL		BIT(11)
+#define CPCAP_BIT_SW4_SEL		BIT(10)
+#define CPCAP_BIT_SW3_SEL		BIT(9)
+#define CPCAP_BIT_SW2_SEL		BIT(8)
+#define CPCAP_BIT_SW1_SEL		BIT(7)
+
+/* CPCAP_REG_ASSIGN3 bits - Resource Assignment 3 */
+#define CPCAP_BIT_VUSBINT2_SEL		BIT(15)
+#define CPCAP_BIT_VUSBINT1_SEL		BIT(14)
+#define CPCAP_BIT_VVIB_SEL		BIT(13)
+#define CPCAP_BIT_VWLAN1_SEL		BIT(12)
+#define CPCAP_BIT_VRF1_SEL		BIT(11)
+#define CPCAP_BIT_VHVIO_SEL		BIT(10)
+#define CPCAP_BIT_VDAC_SEL		BIT(9)
+#define CPCAP_BIT_VUSB_SEL		BIT(8)
+#define CPCAP_BIT_VSIM_SEL		BIT(7)
+#define CPCAP_BIT_VRFREF_SEL		BIT(6)
+#define CPCAP_BIT_VPLL_SEL		BIT(5)
+#define CPCAP_BIT_VFUSE_SEL		BIT(4)
+#define CPCAP_BIT_VCSI_SEL		BIT(3)
+#define CPCAP_BIT_SPARE_14_2		BIT(2)
+#define CPCAP_BIT_VWLAN2_SEL		BIT(1)
+#define CPCAP_BIT_VRF2_SEL		BIT(0)
+#define CPCAP_BIT_NONE			0
+
+/* CPCAP_REG_ASSIGN4 bits - Resource Assignment 4 */
+#define CPCAP_BIT_VAUDIO_SEL		BIT(0)
+
+/*
+ * Off mode configuration bit. Used currently only by SW5 on omap4. There's
+ * the following comment in Motorola Linux kernel tree for it:
+ *
+ * When set in the regulator mode, the regulator assignment will be changed
+ * to secondary when the regulator is disabled. The mode will be set back to
+ * primary when the regulator is turned on.
+ */
+#define CPCAP_REG_OFF_MODE_SEC		BIT(15)
+
+#define CPCAP_REG(_reg, _assignment_reg, _assignment_mask, _mode_mask,		\
+		  _volt_mask, _volt_shft, _mode_val, _off_mode_val, _val_tbl,	\
+		  _mode_cntr, _volt_trans_time, _turn_on_time, _bit_offset) {	\
+	.reg = CPCAP_REG_##_reg,						\
+	.assignment_reg = CPCAP_REG_##_assignment_reg,				\
+	.assignment_mask = CPCAP_BIT_##_assignment_mask,			\
+	.mode_mask = _mode_mask,						\
+	.volt_mask = _volt_mask,						\
+	.volt_shft = _volt_shft,						\
+	.mode_val = _mode_val,							\
+	.off_mode_val = _off_mode_val,						\
+	.val_tbl_sz = ARRAY_SIZE(_val_tbl),					\
+	.val_tbl = _val_tbl,							\
+	.mode_cntr = _mode_cntr,						\
+	.volt_trans_time = _volt_trans_time,					\
+	.turn_on_time = _turn_on_time,						\
+	.bit_offset_from_cpcap_lowest_voltage = _bit_offset,			\
+}
+
+static const struct cpcap_regulator_data tegra20_regulators[CPCAP_REGULATORS_COUNT] = {
+	/* BUCK */
+	[CPCAP_SW1]      = CPCAP_REG(S1C1, ASSIGN2, SW1_SEL, 0x6f00, 0x007f,
+				     0, 0x6800, 0, sw1_val_tbl, 0, 0, 1500, 0x0c),
+	[CPCAP_SW2]      = CPCAP_REG(S2C1, ASSIGN2, SW2_SEL, 0x6f00, 0x007f,
+				     0, 0x4804, 0, sw2_sw4_val_tbl, 0, 0, 1500, 0x18),
+	[CPCAP_SW3]      = CPCAP_REG(S3C, ASSIGN2, SW3_SEL, 0x0578, 0x0003,
+				     0, 0x043c, 0, sw3_val_tbl, 0, 0, 0, 0),
+	[CPCAP_SW4]      = CPCAP_REG(S4C1, ASSIGN2, SW4_SEL, 0x6f00, 0x007f,
+				     0, 0x4909, 0, sw2_sw4_val_tbl, 0, 0, 1500, 0x18),
+	[CPCAP_SW5]      = CPCAP_REG(S5C, ASSIGN2, SW5_SEL, 0x0028, 0x0000,
+				     0, 0x0020, 0, sw5_val_tbl, 0, 0, 1500, 0),
+	[CPCAP_SW6]      = CPCAP_REG(S6C, ASSIGN2, SW6_SEL, 0x0000, 0x0000,
+				     0, 0, 0, unknown_val_tbl, 0, 0, 0, 0),
+	/* LDO */
+	[CPCAP_VCAM]     = CPCAP_REG(VCAMC, ASSIGN2, VCAM_SEL, 0x0087, 0x0030,
+				     4, 0x7, 0, vcam_val_tbl, 0, 420, 1000, 0),
+	[CPCAP_VCSI]     = CPCAP_REG(VCSIC, ASSIGN3, VCSI_SEL, 0x0047, 0x0010,
+				     4, 0x7, 0, vcsi_val_tbl, 0, 350, 1000, 0),
+	[CPCAP_VDAC]     = CPCAP_REG(VDACC, ASSIGN3, VDAC_SEL, 0x0087, 0x0030,
+				     4, 0x0, 0, vdac_val_tbl, 0, 420, 1000, 0),
+	[CPCAP_VDIG]     = CPCAP_REG(VDIGC, ASSIGN2, VDIG_SEL, 0x0087, 0x0030,
+				     4, 0x0, 0, vdig_val_tbl, 0, 420, 1000, 0),
+	[CPCAP_VFUSE]    = CPCAP_REG(VFUSEC, ASSIGN3, VFUSE_SEL, 0x00a0, 0x000f,
+				     0, 0x0, 0, vfuse_val_tbl, 0, 420, 1000, 0),
+	[CPCAP_VHVIO]    = CPCAP_REG(VHVIOC, ASSIGN3, VHVIO_SEL, 0x0017, 0x0000,
+				     0, 0x2, 0, vhvio_val_tbl, 0, 0, 1000, 0),
+	[CPCAP_VSDIO]    = CPCAP_REG(VSDIOC, ASSIGN2, VSDIO_SEL, 0x0087, 0x0038,
+				     3, 0x2, 0, vsdio_val_tbl, 0, 420, 1000, 0),
+	[CPCAP_VPLL]     = CPCAP_REG(VPLLC, ASSIGN3, VPLL_SEL, 0x0047, 0x0018,
+				     3, 0x1, 0, vpll_val_tbl, 0, 420, 100, 0),
+	[CPCAP_VRF1]     = CPCAP_REG(VRF1C, ASSIGN3, VRF1_SEL, 0x00ac, 0x0002,
+				     1, 0x0, 0, vrf1_val_tbl, 0, 10, 1000, 0),
+	[CPCAP_VRF2]     = CPCAP_REG(VRF2C, ASSIGN3, VRF2_SEL, 0x0023, 0x0008,
+				     3, 0x0, 0, vrf2_val_tbl, 0, 10, 1000, 0),
+	[CPCAP_VRFREF]   = CPCAP_REG(VRFREFC, ASSIGN3, VRFREF_SEL, 0x0023, 0x0008,
+				     3, 0x0, 0, vrfref_val_tbl, 0, 420, 100, 0),
+	[CPCAP_VWLAN1]   = CPCAP_REG(VWLAN1C, ASSIGN3, VWLAN1_SEL, 0x0047, 0x0010,
+				     4, 0x0, 0, vwlan1_val_tbl, 0, 420, 1000, 0),
+	[CPCAP_VWLAN2]   = CPCAP_REG(VWLAN2C, ASSIGN3, VWLAN2_SEL, 0x020c, 0x00c0,
+				     6, 0xd, 0, vwlan2_val_tbl, 0, 420, 1000, 0),
+	[CPCAP_VSIM]     = CPCAP_REG(VSIMC, ASSIGN3, NONE, 0x0023, 0x0008,
+				     3, 0x0, 0, vsim_val_tbl, 0, 420, 1000, 0),
+	[CPCAP_VSIMCARD] = CPCAP_REG(VSIMC, ASSIGN3, NONE, 0x1e80, 0x0008,
+				     3, 0x1E00, 0, vsimcard_val_tbl, 0, 420, 1000, 0),
+	[CPCAP_VVIB]     = CPCAP_REG(VVIBC, ASSIGN3, VVIB_SEL, 0x0001, 0x000c,
+				     2, 0x1, 0, vvib_val_tbl, 0, 500, 500, 0),
+	[CPCAP_VUSB]     = CPCAP_REG(VUSBC, ASSIGN3, VUSB_SEL, 0x011c, 0x0040,
+				     6, 0xc, 0, vusb_val_tbl, 0, 0, 1000, 0),
+	[CPCAP_VAUDIO]   = CPCAP_REG(VAUDIOC, ASSIGN4, VAUDIO_SEL, 0x0016, 0x0001,
+				     0, 0x5, 0, vaudio_val_tbl, 0, 0, 1000, 0),
+};
+
+static int cpcap_regulator_get_value(struct udevice *dev)
+{
+	const struct cpcap_regulator_data *regulator =
+					&tegra20_regulators[dev->driver_data];
+	int value, volt_shift = regulator->volt_shft;
+
+	value = pmic_reg_read(dev->parent, regulator->reg);
+	if (value < 0)
+		return value;
+
+	if (!(value & regulator->mode_mask))
+		return 0;
+
+	value &= regulator->volt_mask;
+	value -= regulator->bit_offset_from_cpcap_lowest_voltage;
+
+	return regulator->val_tbl[value >> volt_shift];
+}
+
+static int cpcap_regulator_set_value(struct udevice *dev, int uV)
+{
+	const struct cpcap_regulator_data *regulator =
+					&tegra20_regulators[dev->driver_data];
+	int value, ret, volt_shift = regulator->volt_shft;
+
+	if (dev->driver_data == CPCAP_VRF1) {
+		if (uV > 2500000)
+			value = 0;
+		else
+			value = regulator->volt_mask;
+	} else {
+		for (value = 0; value < regulator->val_tbl_sz; value++)
+			if (regulator->val_tbl[value] >= uV)
+				break;
+
+		if (value >= regulator->val_tbl_sz)
+			value = regulator->val_tbl_sz;
+
+		value <<= volt_shift;
+		value += regulator->bit_offset_from_cpcap_lowest_voltage;
+	}
+
+	ret = pmic_clrsetbits(dev->parent, regulator->reg, regulator->volt_mask,
+			      value);
+	if (ret)
+		return ret;
+
+	if (regulator->volt_trans_time)
+		udelay(regulator->volt_trans_time);
+
+	return 0;
+}
+
+static int cpcap_regulator_get_enable(struct udevice *dev)
+{
+	const struct cpcap_regulator_data *regulator =
+					&tegra20_regulators[dev->driver_data];
+	int value;
+
+	value = pmic_reg_read(dev->parent, regulator->reg);
+	if (value < 0)
+		return value;
+
+	return (value & regulator->mode_mask) ? 1 : 0;
+}
+
+static int cpcap_regulator_set_enable(struct udevice *dev, bool enable)
+{
+	const struct cpcap_regulator_data *regulator =
+					&tegra20_regulators[dev->driver_data];
+	int ret;
+
+	if (enable) {
+		ret = pmic_clrsetbits(dev->parent, regulator->reg, regulator->mode_mask,
+				      regulator->mode_val);
+		if (ret)
+			return ret;
+	}
+
+	if (regulator->mode_val & CPCAP_REG_OFF_MODE_SEC) {
+		ret = pmic_clrsetbits(dev->parent, regulator->assignment_reg,
+				      regulator->assignment_mask,
+				      enable ? 0 : regulator->assignment_mask);
+		if (ret)
+			return ret;
+	}
+
+	if (!enable) {
+		ret = pmic_clrsetbits(dev->parent, regulator->reg, regulator->mode_mask,
+				      regulator->off_mode_val);
+		if (ret)
+			return ret;
+	}
+
+	if (regulator->turn_on_time)
+		udelay(regulator->turn_on_time);
+
+	return 0;
+}
+
+static int cpcap_regulator_probe(struct udevice *dev)
+{
+	struct dm_regulator_uclass_plat *uc_pdata = dev_get_uclass_plat(dev);
+	int id;
+
+	for (id = 0; id < CPCAP_REGULATORS_COUNT; id++)
+		if (cpcap_regulator_to_name[id])
+			if (!strcmp(dev->name, cpcap_regulator_to_name[id]))
+				break;
+
+	switch (id) {
+	case CPCAP_SW1 ... CPCAP_SW6:
+		uc_pdata->type = REGULATOR_TYPE_BUCK;
+		break;
+
+	case CPCAP_VCAM ... CPCAP_VAUDIO:
+		uc_pdata->type = REGULATOR_TYPE_LDO;
+		break;
+
+	default:
+		log_err("CPCAP: Invalid regulator ID\n");
+		return -ENODEV;
+	}
+
+	dev->driver_data = id;
+	return 0;
+}
+
+static const struct dm_regulator_ops cpcap_regulator_ops = {
+	.get_value  = cpcap_regulator_get_value,
+	.set_value  = cpcap_regulator_set_value,
+	.get_enable = cpcap_regulator_get_enable,
+	.set_enable = cpcap_regulator_set_enable,
+};
+
+U_BOOT_DRIVER(cpcap_sw) = {
+	.name = CPCAP_SW_DRIVER,
+	.id = UCLASS_REGULATOR,
+	.ops = &cpcap_regulator_ops,
+	.probe = cpcap_regulator_probe,
+};
+
+U_BOOT_DRIVER(cpcap_ldo) = {
+	.name = CPCAP_LDO_DRIVER,
+	.id = UCLASS_REGULATOR,
+	.ops = &cpcap_regulator_ops,
+	.probe = cpcap_regulator_probe,
+};
diff --git a/drivers/spi/tegra20_slink.c b/drivers/spi/tegra20_slink.c
index d54a5049205..097d9164175 100644
--- a/drivers/spi/tegra20_slink.c
+++ b/drivers/spi/tegra20_slink.c
@@ -29,7 +29,10 @@ DECLARE_GLOBAL_DATA_PTR;
 #define SLINK_CMD_IDLE_SCLK_PULL_LOW	(2 << 24)
 #define SLINK_CMD_IDLE_SCLK_PULL_HIGH	(3 << 24)
 #define SLINK_CMD_IDLE_SCLK_MASK	(3 << 24)
+#define SLINK_CMD_CS_POL3		BIT(23)
+#define SLINK_CMD_CS_POL2		BIT(22)
 #define SLINK_CMD_CK_SDA		BIT(21)
+#define SLINK_CMD_CS_POL1		BIT(20)
 #define SLINK_CMD_CS_POL		BIT(13)
 #define SLINK_CMD_CS_VAL		BIT(12)
 #define SLINK_CMD_CS_SOFT		BIT(11)
@@ -64,6 +67,13 @@ DECLARE_GLOBAL_DATA_PTR;
 #define SPI_TIMEOUT		1000
 #define TEGRA_SPI_MAX_FREQ	52000000
 
+unsigned int cmd_cs_pol_bit[] = {
+	SLINK_CMD_CS_POL,
+	SLINK_CMD_CS_POL1,
+	SLINK_CMD_CS_POL2,
+	SLINK_CMD_CS_POL3,
+};
+
 struct spi_regs {
 	u32 command;	/* SLINK_COMMAND_0 register  */
 	u32 command2;	/* SLINK_COMMAND2_0 reg */
@@ -155,6 +165,14 @@ static int tegra30_spi_claim_bus(struct udevice *dev)
 	writel(reg, &regs->status);
 	debug("%s: STATUS = %08x\n", __func__, readl(&regs->status));
 
+	/* Update the polarity bits */
+	if (priv->mode & SPI_CS_HIGH)
+		setbits_le32(&priv->regs->command,
+			     cmd_cs_pol_bit[spi_chip_select(dev)]);
+	else
+		clrbits_le32(&priv->regs->command,
+			     cmd_cs_pol_bit[spi_chip_select(dev)]);
+
 	/* Set master mode and sw controlled CS */
 	reg = readl(&regs->command);
 	reg |= SLINK_CMD_M_S | SLINK_CMD_CS_SOFT;
diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig
index 475540ffac7..4972905482a 100644
--- a/drivers/sysreset/Kconfig
+++ b/drivers/sysreset/Kconfig
@@ -71,6 +71,27 @@ config POWEROFF_GPIO
 	  Support for system poweroff using a GPIO pin. This can be used
 	  for systems having a single GPIO to trigger a system poweroff.
 
+config SPL_POWEROFF_GPIO
+	bool "Enable support for GPIO poweroff driver in SPL"
+	depends on DM_GPIO && SPL
+	help
+	  Support for system poweroff using a GPIO pin in SPL. This can be used
+	  for systems having a single GPIO to trigger a system poweroff.
+
+config TPL_POWEROFF_GPIO
+	bool "Enable support for GPIO poweroff driver in TPL"
+	depends on DM_GPIO && TPL
+	help
+	  Support for system poweroff using a GPIO pin in TPL. This can be used
+	  for systems having a single GPIO to trigger a system poweroff.
+
+config VPL_POWEROFF_GPIO
+	bool "Enable support for GPIO poweroff driver in VPL"
+	depends on DM_GPIO && VPL
+	help
+	  Support for system poweroff using a GPIO pin in VPL. This can be used
+	  for systems having a single GPIO to trigger a system poweroff.
+
 config SYSRESET_GPIO
 	bool "Enable support for GPIO reset driver"
 	depends on DM_GPIO
@@ -79,6 +100,30 @@ config SYSRESET_GPIO
 	  example on Microblaze where reset logic can be controlled via GPIO
 	  pin which triggers cpu reset.
 
+config SPL_SYSRESET_GPIO
+	bool "Enable support for GPIO reset driver in SPL"
+	depends on DM_GPIO && SPL
+	help
+	  Reset support via GPIO pin connected reset logic in SPL. This is used
+	  for example on Microblaze where reset logic can be controlled via
+	  GPIO pin which triggers cpu reset.
+
+config TPL_SYSRESET_GPIO
+	bool "Enable support for GPIO reset driver in TPL"
+	depends on DM_GPIO && TPL
+	help
+	  Reset support via GPIO pin connected reset logic in TPL. This is used
+	  for example on Microblaze where reset logic can be controlled via
+	  GPIO pin which triggers cpu reset.
+
+config VPL_SYSRESET_GPIO
+	bool "Enable support for GPIO reset driver in VPL"
+	depends on DM_GPIO && VPL
+	help
+	  Reset support via GPIO pin connected reset logic in VPL. This is used
+	  for example on Microblaze where reset logic can be controlled via
+	  GPIO pin which triggers cpu reset.
+
 config SYSRESET_MAX77663
 	bool "Enable support for MAX77663 PMIC System Reset"
 	depends on DM_PMIC_MAX77663
diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile
index 796fc9effa5..ded91a4d325 100644
--- a/drivers/sysreset/Makefile
+++ b/drivers/sysreset/Makefile
@@ -8,8 +8,8 @@ obj-$(CONFIG_ARCH_ROCKCHIP) += sysreset_rockchip.o
 obj-$(CONFIG_ARCH_STI) += sysreset_sti.o
 obj-$(CONFIG_SANDBOX) += sysreset_sandbox.o
 obj-$(CONFIG_SYSRESET_CV1800B) += sysreset_cv1800b.o
-obj-$(CONFIG_POWEROFF_GPIO) += poweroff_gpio.o
-obj-$(CONFIG_SYSRESET_GPIO) += sysreset_gpio.o
+obj-$(CONFIG_$(PHASE_)POWEROFF_GPIO) += poweroff_gpio.o
+obj-$(CONFIG_$(PHASE_)SYSRESET_GPIO) += sysreset_gpio.o
 obj-$(CONFIG_$(PHASE_)SYSRESET_MAX77663) += sysreset_max77663.o
 obj-$(CONFIG_SYSRESET_MPC83XX) += sysreset_mpc83xx.o
 obj-$(CONFIG_SYSRESET_MICROBLAZE) += sysreset_microblaze.o
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index df607303616..73353944971 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -529,6 +529,16 @@ config VIDEO_LCD_HIMAX_HX8394
 	Say Y here if you want to enable support for Himax HX8394
 	dsi 4dl panel.
 
+config VIDEO_LCD_MOT
+	tristate "Atrix 4G and Droid X2 540x960 DSI video mode panel"
+	depends on PANEL && BACKLIGHT
+	select VIDEO_MIPI_DSI
+	help
+	  Say Y here if you want to enable support for the LCD panel module for
+	  Motorola Atrix 4G or Droid X2. Exact panel vendor and model are
+	  unknown. The panel has a 540x960 resolution and uses 24 bit RGB per
+	  pixel.
+
 config VIDEO_LCD_ORISETECH_OTM8009A
 	bool "OTM8009A DSI LCD panel support"
 	select VIDEO_MIPI_DSI
@@ -728,6 +738,15 @@ config ATMEL_HLCD
 	help
 	   HLCDC supports video output to an attached LCD panel.
 
+config BACKLIGHT_LM3532
+	bool "Backlight Driver for LM3532"
+	depends on BACKLIGHT
+	select DM_I2C
+	help
+	  Say Y to enable the backlight driver for National Semiconductor / TI
+	  LM3532 Lighting Power chip. Only backlight functions is supported as
+	  for now. Supported backlight level range is from 1 to 255.
+
 config BACKLIGHT_LM3533
 	bool "Backlight Driver for LM3533"
 	depends on BACKLIGHT
@@ -809,17 +828,9 @@ source "drivers/video/stm32/Kconfig"
 
 source "drivers/video/tidss/Kconfig"
 
-config VIDEO_TEGRA124
-	bool "Enable video support on Tegra124"
-	help
-	   Tegra124 supports many video output options including eDP and
-	   HDMI. At present only eDP is supported by U-Boot. This option
-	   enables this support which can be used on devices which
-	   have an eDP display connected.
-
 source "drivers/video/bridge/Kconfig"
 
-source "drivers/video/tegra20/Kconfig"
+source "drivers/video/tegra/Kconfig"
 
 source "drivers/video/imx/Kconfig"
 
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index bbd5db46553..fbdb058647a 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -29,12 +29,12 @@ obj-$(CONFIG_$(PHASE_)BMP) += bmp.o
 
 endif
 
+obj-$(CONFIG_BACKLIGHT_LM3532) += lm3532_backlight.o
 obj-$(CONFIG_BACKLIGHT_LM3533) += lm3533_backlight.o
 obj-$(CONFIG_BACKLIGHT_LP855x) += lp855x_backlight.o
 obj-${CONFIG_EXYNOS_FB} += exynos/
 obj-${CONFIG_VIDEO_ROCKCHIP} += rockchip/
 obj-${CONFIG_VIDEO_STM32} += stm32/
-obj-${CONFIG_VIDEO_TEGRA124} += tegra124/
 obj-${CONFIG_$(PHASE_)VIDEO_TIDSS} += tidss/
 obj-y += ti/
 
@@ -60,6 +60,7 @@ obj-$(CONFIG_VIDEO_LCD_ENDEAVORU) += endeavoru-panel.o
 obj-$(CONFIG_VIDEO_LCD_HIMAX_HX8394) += himax-hx8394.o
 obj-$(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM) += hitachi_tx18d42vm_lcd.o
 obj-$(CONFIG_VIDEO_LCD_LG_LD070WX3) += lg-ld070wx3.o
+obj-$(CONFIG_VIDEO_LCD_MOT) += mot-panel.o
 obj-$(CONFIG_VIDEO_LCD_ORISETECH_OTM8009A) += orisetech_otm8009a.o
 obj-$(CONFIG_VIDEO_LCD_RAYDIUM_RM68200) += raydium-rm68200.o
 obj-$(CONFIG_VIDEO_LCD_RENESAS_R61307) += renesas-r61307.o
@@ -85,4 +86,4 @@ obj-$(CONFIG_VIDEO_ZYNQMP_DPSUB) += zynqmp/
 
 obj-y += bridge/
 obj-y += sunxi/
-obj-y += tegra20/
+obj-y += tegra/
diff --git a/drivers/video/lm3532_backlight.c b/drivers/video/lm3532_backlight.c
new file mode 100644
index 00000000000..81b3b910196
--- /dev/null
+++ b/drivers/video/lm3532_backlight.c
@@ -0,0 +1,380 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * TI LM3532 LED driver
+ *
+ * Copyright (c) 2019 Texas Instruments Incorporated
+ * Copyright (c) 2025 Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#define LOG_CATEGORY UCLASS_PANEL_BACKLIGHT
+
+#include <backlight.h>
+#include <dm.h>
+#include <dm/ofnode.h>
+#include <i2c.h>
+#include <log.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <asm/gpio.h>
+#include <power/regulator.h>
+
+#define LM3532_BL_MODE_MANUAL		0x00
+#define LM3532_BL_MODE_ALS		0x01
+
+#define LM3532_REG_OUTPUT_CFG		0x10
+#define LM3532_REG_STARTSHUT_RAMP	0x11
+#define LM3532_REG_RT_RAMP		0x12
+#define LM3532_REG_PWM_A_CFG		0x13
+#define LM3532_REG_PWM_B_CFG		0x14
+#define LM3532_REG_PWM_C_CFG		0x15
+#define LM3532_REG_ZONE_CFG_A		0x16
+#define LM3532_REG_CTRL_A_FS_CURR	0x17
+#define LM3532_REG_ZONE_CFG_B		0x18
+#define LM3532_REG_CTRL_B_FS_CURR	0x19
+#define LM3532_REG_ZONE_CFG_C		0x1a
+#define LM3532_REG_CTRL_C_FS_CURR	0x1b
+#define LM3532_REG_ENABLE		0x1d
+#define LM3532_ALS_CONFIG		0x23
+#define LM3532_REG_ZN_0_HI		0x60
+#define LM3532_REG_ZN_0_LO		0x61
+#define LM3532_REG_ZN_1_HI		0x62
+#define LM3532_REG_ZN_1_LO		0x63
+#define LM3532_REG_ZN_2_HI		0x64
+#define LM3532_REG_ZN_2_LO		0x65
+#define LM3532_REG_ZN_3_HI		0x66
+#define LM3532_REG_ZN_3_LO		0x67
+#define LM3532_REG_ZONE_TRGT_A		0x70
+#define LM3532_REG_ZONE_TRGT_B		0x75
+#define LM3532_REG_ZONE_TRGT_C		0x7a
+#define LM3532_REG_MAX			0x7e
+
+/* Control Enable */
+#define LM3532_CTRL_A_ENABLE		BIT(0)
+#define LM3532_CTRL_B_ENABLE		BIT(1)
+#define LM3532_CTRL_C_ENABLE		BIT(2)
+
+/* PWM Zone Control */
+#define LM3532_PWM_ZONE_MASK		0x7c
+#define LM3532_PWM_ZONE_0_EN		BIT(2)
+#define LM3532_PWM_ZONE_1_EN		BIT(3)
+#define LM3532_PWM_ZONE_2_EN		BIT(4)
+#define LM3532_PWM_ZONE_3_EN		BIT(5)
+#define LM3532_PWM_ZONE_4_EN		BIT(6)
+
+/* Brightness Configuration */
+#define LM3532_I2C_CTRL			BIT(0)
+#define LM3532_ALS_CTRL			0
+#define LM3532_LINEAR_MAP		BIT(1)
+#define LM3532_ZONE_MASK		(BIT(2) | BIT(3) | BIT(4))
+#define LM3532_ZONE_0			0
+#define LM3532_ZONE_1			BIT(2)
+#define LM3532_ZONE_2			BIT(3)
+#define LM3532_ZONE_3			(BIT(2) | BIT(3))
+#define LM3532_ZONE_4			BIT(4)
+
+#define LM3532_ENABLE_ALS		BIT(3)
+#define LM3532_ALS_SEL_SHIFT		6
+
+/* Zone Boundary Register */
+#define LM3532_ALS_WINDOW_mV		2000
+#define LM3532_ALS_ZB_MAX		4
+#define LM3532_ALS_OFFSET_mV		2
+
+#define LM3532_CONTROL_A		0
+#define LM3532_CONTROL_B		1
+#define LM3532_CONTROL_C		2
+#define LM3532_MAX_CONTROL_BANKS	3
+#define LM3532_MAX_LED_STRINGS		3
+
+#define LM3532_OUTPUT_CFG_MASK		0x3
+#define LM3532_BRT_VAL_ADJUST		8
+#define LM3532_RAMP_DOWN_SHIFT		3
+
+#define LM3532_NUM_RAMP_VALS		8
+#define LM3532_NUM_AVG_VALS		8
+#define LM3532_NUM_IMP_VALS		32
+
+#define LM3532_FS_CURR_MIN		5000
+#define LM3532_FS_CURR_MAX		29800
+#define LM3532_FS_CURR_STEP		800
+
+struct lm3532_bank_data {
+	int control_bank;
+	int mode;
+	int ctrl_brt_pointer;
+	int num_leds;
+	int full_scale_current;
+	u32 present:1;
+	u32 led_strings[LM3532_MAX_CONTROL_BANKS];
+};
+
+struct lm3532_backlight_priv {
+	struct gpio_desc enable_gpio;
+	struct udevice *regulator;
+
+	u32 runtime_ramp_up;
+	u32 runtime_ramp_down;
+
+	struct lm3532_bank_data bank[LM3532_MAX_CONTROL_BANKS];
+};
+
+/* This device does not like i2c md so use this instead */
+static void __maybe_unused dump_i2c(struct udevice *dev)
+{
+	int i, c;
+
+	for (i = 0; i < 0x10; i++) {
+		printf("00%02x: %02x", i * 0x10, dm_i2c_reg_read(dev, i * 0x10));
+		for (c = 1; c < 0xf; c++)
+			printf(" %02x", dm_i2c_reg_read(dev, i * 0x10 + c));
+		printf(" %02x\n", dm_i2c_reg_read(dev, i * 0x10 + 0xf));
+	}
+}
+
+static int lm3532_backlight_enable(struct udevice *dev)
+{
+	struct lm3532_backlight_priv *priv = dev_get_priv(dev);
+	int ret, i;
+
+	for (i = 0; i < LM3532_MAX_CONTROL_BANKS; i++) {
+		if (priv->bank[i].present) {
+			u32 ctrl_en_val = BIT(priv->bank[i].control_bank);
+
+			ret = dm_i2c_reg_clrset(dev, LM3532_REG_ENABLE,
+						ctrl_en_val, ctrl_en_val);
+			if (ret) {
+				log_debug("%s: failed to set ctrl: %d\n",
+					  __func__, ret);
+				return ret;
+			}
+		}
+	}
+
+	regulator_set_enable_if_allowed(priv->regulator, 1);
+
+	return 0;
+}
+
+static int lm3532_backlight_set_brightness(struct udevice *dev, int percent)
+{
+	struct lm3532_backlight_priv *priv = dev_get_priv(dev);
+	struct lm3532_bank_data *bank;
+	int ret, i;
+
+	for (i = 0; i < LM3532_MAX_CONTROL_BANKS; i++) {
+		if (priv->bank[i].present) {
+			bank = &priv->bank[i];
+			u32 brightness_reg = LM3532_REG_ZONE_TRGT_A +
+					     bank->control_bank * 5 +
+					     (bank->ctrl_brt_pointer >> 2);
+
+			ret = dm_i2c_reg_write(dev, brightness_reg, percent);
+			if (ret) {
+				log_debug("%s: failed to set brightness: %d\n",
+					  __func__, ret);
+				return ret;
+			}
+		}
+	}
+
+	return 0;
+}
+
+static const int ramp_table[LM3532_NUM_RAMP_VALS] = { 8, 1024, 2048, 4096, 8192,
+						     16384, 32768, 65536 };
+static int lm3532_get_ramp_index(int ramp_time)
+{
+	int i;
+
+	if (ramp_time <= ramp_table[0])
+		return 0;
+
+	if (ramp_time > ramp_table[LM3532_NUM_RAMP_VALS - 1])
+		return LM3532_NUM_RAMP_VALS - 1;
+
+	for (i = 1; i < LM3532_NUM_RAMP_VALS; i++) {
+		if (ramp_time == ramp_table[i])
+			return i;
+
+		/* Find an approximate index by looking up the table */
+		if (ramp_time > ramp_table[i - 1] &&
+		    ramp_time < ramp_table[i]) {
+			if (ramp_time - ramp_table[i - 1] < ramp_table[i] - ramp_time)
+				return i - 1;
+			else
+				return i;
+		}
+	}
+
+	return 0;
+}
+
+static int lm3532_backlight_of_to_plat(struct udevice *dev)
+{
+	struct lm3532_backlight_priv *priv = dev_get_priv(dev);
+	u32 ramp_time, reg;
+	ofnode child;
+	int ret;
+
+	ret = gpio_request_by_name(dev, "enable-gpios", 0,
+				   &priv->enable_gpio, GPIOD_IS_OUT);
+	if (ret) {
+		log_debug("%s: could not decode enable-gpios (%d)\n", __func__, ret);
+		return ret;
+	}
+
+	ret = device_get_supply_regulator(dev, "vin-supply", &priv->regulator);
+	if (ret) {
+		log_debug("%s: vin regulator not defined: %d\n", __func__, ret);
+		if (ret != -ENOENT)
+			return log_ret(ret);
+	}
+
+	ramp_time = dev_read_u32_default(dev, "ramp-up-us", 0);
+	priv->runtime_ramp_up = lm3532_get_ramp_index(ramp_time);
+
+	ramp_time = dev_read_u32_default(dev, "ramp-down-us", 0);
+	priv->runtime_ramp_down = lm3532_get_ramp_index(ramp_time);
+
+	/* Backlight is one of children but has no dedicated driver */
+	ofnode_for_each_subnode(child, dev_ofnode(dev)) {
+		ret = ofnode_read_u32(child, "reg", &reg);
+		if (ret || reg > LM3532_CONTROL_C) {
+			log_debug("%s: control bank invalid %d\n", __func__, reg);
+			continue;
+		}
+
+		struct lm3532_bank_data *bank = &priv->bank[reg];
+
+		bank->control_bank = reg;
+		bank->present = 1;
+		bank->mode = ofnode_read_u32_default(child, "ti,led-mode",
+						     LM3532_BL_MODE_MANUAL);
+		bank->mode = LM3532_BL_MODE_ALS ? LM3532_ALS_CTRL : LM3532_I2C_CTRL;
+
+		if (ofnode_read_bool(child, "ti,linear-mapping-mode"))
+			bank->mode |= LM3532_LINEAR_MAP;
+
+		bank->num_leds = ofnode_read_size(child, "led-sources");
+		bank->num_leds /= sizeof(u32);
+		if (bank->num_leds > LM3532_MAX_LED_STRINGS) {
+			log_debug("%s: too many LED string defined %d\n",
+				  __func__, bank->num_leds);
+			continue;
+		}
+
+		ret = ofnode_read_u32_array(child, "led-sources",
+					    bank->led_strings,
+					    bank->num_leds);
+		if (ret) {
+			log_debug("%s: led-sources property missing %d\n",
+				  __func__, ret);
+			continue;
+		}
+
+		ret = ofnode_read_u32(child, "led-max-microamp",
+				      &bank->full_scale_current);
+		if (ret)
+			log_debug("%s: failed getting led-max-microamp %d\n",
+				  __func__, ret);
+		else
+			bank->full_scale_current = min(bank->full_scale_current,
+						       LM3532_FS_CURR_MAX);
+	}
+
+	return 0;
+}
+
+static int lm3532_backlight_init_registers(struct udevice *dev,
+					   struct lm3532_bank_data *bank)
+{
+	struct lm3532_backlight_priv *priv = dev_get_priv(dev);
+	u32 brightness_config_val, runtime_ramp_val;
+	u32 output_cfg_val = 0, output_cfg_shift = 0, output_cfg_mask = 0;
+	int fs_current_reg, fs_current_val;
+	int ret, i;
+
+	if (!bank->present)
+		return 0;
+
+	u32 brightness_config_reg = LM3532_REG_ZONE_CFG_A + bank->control_bank * 2;
+	/*
+	 * This could be hard coded to the default value but the control
+	 * brightness register may have changed during boot.
+	 */
+	ret = dm_i2c_reg_read(dev, brightness_config_reg);
+	if (ret < 0)
+		return ret;
+
+	bank->ctrl_brt_pointer = ret & ~LM3532_ZONE_MASK;
+	brightness_config_val = bank->ctrl_brt_pointer | bank->mode;
+
+	ret = dm_i2c_reg_write(dev, brightness_config_reg, brightness_config_val);
+	if (ret)
+		return ret;
+
+	if (bank->full_scale_current) {
+		fs_current_reg = LM3532_REG_CTRL_A_FS_CURR + bank->control_bank * 2;
+		fs_current_val = (bank->full_scale_current - LM3532_FS_CURR_MIN) /
+				 LM3532_FS_CURR_STEP;
+
+		ret = dm_i2c_reg_write(dev, fs_current_reg, fs_current_val);
+		if (ret)
+			return ret;
+	}
+
+	for (i = 0; i < bank->num_leds; i++) {
+		output_cfg_shift = bank->led_strings[i] * 2;
+		output_cfg_val |= (bank->control_bank << output_cfg_shift);
+		output_cfg_mask |= LM3532_OUTPUT_CFG_MASK << output_cfg_shift;
+	}
+
+	ret = dm_i2c_reg_clrset(dev, LM3532_REG_OUTPUT_CFG, output_cfg_mask,
+				output_cfg_val);
+	if (ret)
+		return ret;
+
+	runtime_ramp_val = priv->runtime_ramp_up |
+			 (priv->runtime_ramp_down << LM3532_RAMP_DOWN_SHIFT);
+
+	return dm_i2c_reg_write(dev, LM3532_REG_RT_RAMP, runtime_ramp_val);
+}
+
+static int lm3532_backlight_probe(struct udevice *dev)
+{
+	struct lm3532_backlight_priv *priv = dev_get_priv(dev);
+	int ret, i;
+
+	if (device_get_uclass_id(dev->parent) != UCLASS_I2C)
+		return -EPROTONOSUPPORT;
+
+	dm_gpio_set_value(&priv->enable_gpio, 1);
+
+	for (i = 0; i < LM3532_MAX_CONTROL_BANKS; i++) {
+		ret = lm3532_backlight_init_registers(dev, &priv->bank[i]);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+static const struct backlight_ops lm3532_backlight_ops = {
+	.enable = lm3532_backlight_enable,
+	.set_brightness = lm3532_backlight_set_brightness,
+};
+
+static const struct udevice_id lm3532_backlight_ids[] = {
+	{ .compatible = "ti,lm3532" },
+	{ }
+};
+
+U_BOOT_DRIVER(lm3532_backlight) = {
+	.name		= "lm3532_backlight",
+	.id		= UCLASS_PANEL_BACKLIGHT,
+	.of_match	= lm3532_backlight_ids,
+	.of_to_plat	= lm3532_backlight_of_to_plat,
+	.probe		= lm3532_backlight_probe,
+	.ops		= &lm3532_backlight_ops,
+	.priv_auto	= sizeof(struct lm3532_backlight_priv),
+};
diff --git a/drivers/video/mot-panel.c b/drivers/video/mot-panel.c
new file mode 100644
index 00000000000..a9114957867
--- /dev/null
+++ b/drivers/video/mot-panel.c
@@ -0,0 +1,308 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Motorola ATRIX 4G and DROID X2 DSI panel driver
+ * Exact manufacturer and model unknown
+ *
+ * Copyright (c) 2025 Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <backlight.h>
+#include <dm.h>
+#include <panel.h>
+#include <log.h>
+#include <misc.h>
+#include <mipi_display.h>
+#include <mipi_dsi.h>
+#include <asm/gpio.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <power/regulator.h>
+
+struct mot_panel_priv {
+	struct udevice *vdd;
+	struct udevice *vddio;
+
+	struct udevice *backlight;
+
+	struct gpio_desc reset_gpio;
+};
+
+#define dsi_generic_write_seq(dsi, cmd, seq...) do {			\
+		static const u8 b[] = { cmd, seq };			\
+		int ret;						\
+		ret = mipi_dsi_dcs_write_buffer(dsi, b, ARRAY_SIZE(b));	\
+		if (ret < 0)						\
+			return ret;					\
+	} while (0)
+
+static struct display_timing default_timing = {
+	.pixelclock.typ		= 38250000,
+	.hactive.typ		= 540,
+	.hfront_porch.typ	= 32,
+	.hback_porch.typ	= 32,
+	.hsync_len.typ		= 16,
+	.vactive.typ		= 960,
+	.vfront_porch.typ	= 12,
+	.vback_porch.typ	= 12,
+	.vsync_len.typ		= 8,
+};
+
+static int mot_es2(struct mipi_dsi_device *dsi)
+{
+	int ret;
+
+	dsi_generic_write_seq(dsi, 0x55, 0x01);
+
+	ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
+	if (ret < 0) {
+		log_debug("%s: failed to exit sleep mode: %d\n", __func__, ret);
+		return ret;
+	}
+	mdelay(120);
+
+	dsi_generic_write_seq(dsi, 0xf4, 0x00, 0xbb, 0x46, 0x53, 0x0c, 0x49,
+			      0x74, 0x29, 0x12, 0x15, 0x2f, 0x2f, 0x04);
+	dsi_generic_write_seq(dsi, 0xf8, 0x4b, 0x04, 0x10, 0x1a, 0x2c, 0x2c,
+			      0x2c, 0x2c, 0x14, 0x12);
+
+	dsi_generic_write_seq(dsi, 0xb5, 0x03, 0x7f, 0x00, 0x80, 0xc7, 0x00);
+	dsi_generic_write_seq(dsi, 0xb7, 0x66, 0xf6, 0x46, 0x9f, 0x90, 0x99,
+			      0xff, 0x80, 0x6d, 0x01);
+
+	/* Gamma R */
+	dsi_generic_write_seq(dsi, 0xf9, 0x04);
+	dsi_generic_write_seq(dsi, 0xfa, 0x00, 0x2f, 0x30, 0x12, 0x0e, 0x0c,
+			      0x22, 0x27, 0x31, 0x2e, 0x07, 0x0f);
+	dsi_generic_write_seq(dsi, 0xfb, 0x00, 0x2f, 0x30, 0x12, 0x0e, 0x0c,
+			      0x22, 0x27, 0x31, 0x2e, 0x07, 0x0f);
+
+	/* Gamma G */
+	dsi_generic_write_seq(dsi, 0xf9, 0x02);
+	dsi_generic_write_seq(dsi, 0xfa, 0x00, 0x2f, 0x37, 0x15, 0x15, 0x11,
+			      0x1f, 0x25, 0x2d, 0x2a, 0x05, 0x0f);
+	dsi_generic_write_seq(dsi, 0xfb, 0x00, 0x2f, 0x37, 0x15, 0x15, 0x11,
+			      0x1f, 0x25, 0x2d, 0x2a, 0x05, 0x0f);
+
+	/* Gamma B */
+	dsi_generic_write_seq(dsi, 0xf9, 0x01);
+	dsi_generic_write_seq(dsi, 0xfa, 0x00, 0x2f, 0x3f, 0x16, 0x1f, 0x15,
+			      0x1f, 0x25, 0x2d, 0x2b, 0x06, 0x0b);
+	dsi_generic_write_seq(dsi, 0xfb, 0x00, 0x2f, 0x3f, 0x16, 0x1f, 0x15,
+			      0x1f, 0x25, 0x2d, 0x2b, 0x06, 0x0b);
+
+	/* Gamma W */
+	dsi_generic_write_seq(dsi, 0xf9, 0x20);
+	dsi_generic_write_seq(dsi, 0xfa, 0x00, 0x2f, 0x34, 0x15, 0x1a, 0x11,
+			      0x1f, 0x23, 0x2d, 0x29, 0x02, 0x08);
+	dsi_generic_write_seq(dsi, 0xfb, 0x00, 0x2f, 0x34, 0x15, 0x1a, 0x11,
+			      0x1f, 0x23, 0x2d, 0x29, 0x02, 0x08);
+
+	dsi_generic_write_seq(dsi, 0x53, 0x2c);
+	dsi_generic_write_seq(dsi, 0x35, 0x00);
+
+	return 0;
+}
+
+static int __maybe_unused mot_es4(struct mipi_dsi_device *dsi)
+{
+	int ret;
+
+	dsi_generic_write_seq(dsi, 0xd2, 0x04, 0x53);
+	dsi_generic_write_seq(dsi, 0xd2, 0x05, 0x53);
+	dsi_generic_write_seq(dsi, 0x55, 0x01);
+
+	ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
+	if (ret < 0) {
+		log_debug("%s: failed to exit sleep mode: %d\n", __func__, ret);
+		return ret;
+	}
+	mdelay(120);
+
+	dsi_generic_write_seq(dsi, 0xb5, 0x03, 0x7f, 0x0a, 0x80, 0xff, 0x00);
+	dsi_generic_write_seq(dsi, 0xb7, 0x7a, 0xf7, 0x4d, 0x91, 0x90, 0xb3,
+			      0xff, 0x80, 0x6d, 0x01);
+	dsi_generic_write_seq(dsi, 0xf4, 0x00, 0xbb, 0x46, 0x53, 0x0c, 0x49,
+			      0x74, 0x29, 0x12, 0x15, 0x37, 0x37, 0x04);
+	dsi_generic_write_seq(dsi, 0xf8, 0x0a, 0x04, 0x10, 0x2a, 0x35, 0x35,
+			      0x35, 0x35, 0x21, 0x1a);
+
+	/* Gamma R */
+	dsi_generic_write_seq(dsi, 0xf9, 0x04);
+	dsi_generic_write_seq(dsi, 0xfa, 0x08, 0x1c, 0x1b, 0x0f, 0x0f, 0x0a,
+			      0x1e, 0x22, 0x27, 0x26, 0x07, 0x0d);
+	dsi_generic_write_seq(dsi, 0xfb, 0x08, 0x3c, 0x27, 0x0f, 0x0f, 0x0a,
+			      0x1e, 0x26, 0x31, 0x2f, 0x07, 0x0b);
+
+	/* Gamma G */
+	dsi_generic_write_seq(dsi, 0xf9, 0x02);
+	dsi_generic_write_seq(dsi, 0xfa, 0x30, 0x14, 0x0f, 0x00, 0x06, 0x02,
+			      0x1e, 0x22, 0x27, 0x27, 0x08, 0x10);
+	dsi_generic_write_seq(dsi, 0xfb, 0x30, 0x35, 0x0f, 0x00, 0x0a, 0x02,
+			      0x1c, 0x23, 0x31, 0x2f, 0x08, 0x0e);
+
+	/* Gamma B */
+	dsi_generic_write_seq(dsi, 0xf9, 0x01);
+	dsi_generic_write_seq(dsi, 0xfa, 0x12, 0x1b, 0x26, 0x0e, 0x12, 0x0b,
+			      0x1e, 0x22, 0x27, 0x27, 0x06, 0x0c);
+	dsi_generic_write_seq(dsi, 0xfb, 0x12, 0x3b, 0x2c, 0x12, 0x12, 0x0e,
+			      0x1e, 0x26, 0x31, 0x2f, 0x06, 0x0d);
+
+	/* Gamma W */
+	dsi_generic_write_seq(dsi, 0xf9, 0x20);
+	dsi_generic_write_seq(dsi, 0xfa, 0x37, 0x1b, 0x09, 0x01, 0x06, 0x04,
+			      0x19, 0x19, 0x22, 0x24, 0x04, 0x15);
+	dsi_generic_write_seq(dsi, 0xfb, 0x37, 0x3b, 0x17, 0x01, 0x0a, 0x04,
+			      0x19, 0x1d, 0x2c, 0x2c, 0x04, 0x13);
+
+	dsi_generic_write_seq(dsi, 0x53, 0x2c);
+	dsi_generic_write_seq(dsi, 0x35, 0x00);
+	dsi_generic_write_seq(dsi, 0xc3, 0x01, 0x4e);
+
+	return 0;
+}
+
+static int mot_panel_enable_backlight(struct udevice *dev)
+{
+	struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
+	struct mipi_dsi_device *dsi = plat->device;
+	int ret;
+
+	dsi_generic_write_seq(dsi, 0xf0, 0x5a, 0x5a);
+	dsi_generic_write_seq(dsi, 0xf1, 0x5a, 0x5a);
+	dsi_generic_write_seq(dsi, 0xd0, 0x8e);
+
+	ret = mot_es2(dsi);
+	if (ret)
+		return ret;
+
+	ret = mipi_dsi_dcs_set_display_on(dsi);
+	if (ret < 0) {
+		log_debug("%s: failed to set display on: %d\n", __func__, ret);
+		return ret;
+	}
+	mdelay(20);
+
+	return 0;
+}
+
+static int mot_panel_set_backlight(struct udevice *dev, int percent)
+{
+	struct mot_panel_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	ret = backlight_enable(priv->backlight);
+	if (ret)
+		return ret;
+
+	mdelay(5);
+
+	return backlight_set_brightness(priv->backlight, percent);
+}
+
+static int mot_panel_timings(struct udevice *dev, struct display_timing *timing)
+{
+	memcpy(timing, &default_timing, sizeof(*timing));
+	return 0;
+}
+
+static int mot_panel_of_to_plat(struct udevice *dev)
+{
+	struct mot_panel_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	ret = uclass_get_device_by_phandle(UCLASS_PANEL_BACKLIGHT, dev,
+					   "backlight", &priv->backlight);
+	if (ret) {
+		log_debug("%s: cannot get backlight: ret = %d\n", __func__, ret);
+		return ret;
+	}
+
+	ret = device_get_supply_regulator(dev, "vdd-supply", &priv->vdd);
+	if (ret) {
+		log_debug("%s: cannot get vdd-supply: ret = %d\n", __func__, ret);
+		return ret;
+	}
+
+	ret = device_get_supply_regulator(dev, "vddio-supply", &priv->vddio);
+	if (ret) {
+		log_debug("%s: cannot get vddio-supply: ret = %d\n", __func__, ret);
+		return ret;
+	}
+
+	ret = gpio_request_by_name(dev, "reset-gpios", 0,
+				   &priv->reset_gpio, GPIOD_IS_OUT);
+	if (ret) {
+		log_debug("%s: could not decode reser-gpios (%d)\n", __func__, ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int mot_panel_hw_init(struct udevice *dev)
+{
+	struct mot_panel_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	ret = regulator_set_enable_if_allowed(priv->vddio, 1);
+	if (ret) {
+		log_debug("%s: enabling vddio-supply failed (%d)\n", __func__, ret);
+		return ret;
+	}
+
+	ret = regulator_set_enable_if_allowed(priv->vdd, 1);
+	if (ret) {
+		log_debug("%s: enabling vdd-supply failed (%d)\n", __func__, ret);
+		return ret;
+	}
+
+	ret = dm_gpio_set_value(&priv->reset_gpio, 1);
+	if (ret) {
+		log_debug("%s: error entering reset (%d)\n", __func__, ret);
+		return ret;
+	}
+	mdelay(50);
+
+	ret = dm_gpio_set_value(&priv->reset_gpio, 0);
+	if (ret) {
+		log_debug("%s: error exiting reset (%d)\n", __func__, ret);
+		return ret;
+	}
+	mdelay(10);
+
+	return 0;
+}
+
+static int mot_panel_probe(struct udevice *dev)
+{
+	struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
+
+	/* fill characteristics of DSI data link */
+	plat->lanes = 2;
+	plat->format = MIPI_DSI_FMT_RGB888;
+	plat->mode_flags = MIPI_DSI_MODE_LPM;
+
+	return mot_panel_hw_init(dev);
+}
+
+static const struct panel_ops mot_panel_ops = {
+	.enable_backlight	= mot_panel_enable_backlight,
+	.set_backlight		= mot_panel_set_backlight,
+	.get_display_timing	= mot_panel_timings,
+};
+
+static const struct udevice_id mot_panel_ids[] = {
+	{ .compatible = "motorola,mot-panel" },
+	{ }
+};
+
+U_BOOT_DRIVER(mot_panel) = {
+	.name		= "mot_panel",
+	.id		= UCLASS_PANEL,
+	.of_match	= mot_panel_ids,
+	.ops		= &mot_panel_ops,
+	.of_to_plat	= mot_panel_of_to_plat,
+	.probe		= mot_panel_probe,
+	.plat_auto	= sizeof(struct mipi_dsi_panel_plat),
+	.priv_auto	= sizeof(struct mot_panel_priv),
+};
diff --git a/drivers/video/tegra/Kconfig b/drivers/video/tegra/Kconfig
new file mode 100644
index 00000000000..d3b8dbb2826
--- /dev/null
+++ b/drivers/video/tegra/Kconfig
@@ -0,0 +1,51 @@
+config HOST1X_TEGRA
+	bool "NVIDIA Tegra host1x BUS support"
+	depends on SIMPLE_BUS
+
+config VIDEO_TEGRA
+	bool "Enable Display Controller support on Tegra devices"
+	depends on OF_CONTROL
+	select HOST1X_TEGRA
+	help
+	   Enable support for Display Controller found in Tegra SoC. The
+	   Display Controller Complex integrates two independent display
+	   controllers. Each display controller is capable of interfacing
+	   to an external display device, which can be a parallel interface
+	   or SPI LCD, DVI, an HDMI HDTV, RGB monitor or a MIPI DSI LCD.
+	   Direct interface is supported directly to most LCD displays with
+	   TFT or TFT-like interface.
+
+config VIDEO_DSI_TEGRA
+	bool "Enable DSI controller support on Tegra devices"
+	depends on VIDEO_BRIDGE && PANEL && DM_GPIO
+	select VIDEO_TEGRA
+	select VIDEO_MIPI_DSI
+	help
+	   Enable support for the Display Serial Interface (DSI) found in
+	   Tegra SoC. It is a MIPI standard serial bitstream, intended to
+	   provide a low pin count interface to a display panel.
+
+config VIDEO_HDMI_TEGRA
+	bool "Enable HDMI support on Tegra devices"
+	depends on VIDEO_BRIDGE && DM_I2C
+	select I2C_EDID
+	select VIDEO_TEGRA
+	help
+	   Enable support for the High-Definition Multimedia Interface (HDMI)
+	   found in Tegra SoC.
+
+config TEGRA_BACKLIGHT_PWM
+	bool "Enable Tegra DC PWM backlight support"
+	depends on BACKLIGHT
+	select VIDEO_TEGRA
+	help
+	   Enable support for the Display Controller dependent PWM backlight
+	   found in the Tegra SoC and usually used with DSI panels.
+
+config VIDEO_TEGRA124
+	bool "Enable video support on Tegra124"
+	help
+	   Tegra124 supports many video output options including eDP and
+	   HDMI. At present only eDP is supported by U-Boot. This option
+	   enables this support which can be used on devices which
+	   have an eDP display connected.
diff --git a/drivers/video/tegra/Makefile b/drivers/video/tegra/Makefile
new file mode 100644
index 00000000000..3c50a0ba3c3
--- /dev/null
+++ b/drivers/video/tegra/Makefile
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-$(CONFIG_HOST1X_TEGRA) += host1x.o
+obj-$(CONFIG_VIDEO_TEGRA) += dc.o
+obj-$(CONFIG_VIDEO_DSI_TEGRA) += dsi.o mipi.o mipi-phy.o
+obj-$(CONFIG_VIDEO_HDMI_TEGRA) += hdmi.o
+obj-$(CONFIG_TEGRA_BACKLIGHT_PWM) += dc-pwm-backlight.o
+
+obj-${CONFIG_VIDEO_TEGRA124} += tegra124/
diff --git a/drivers/video/tegra/TODO b/drivers/video/tegra/TODO
new file mode 100644
index 00000000000..1c8c2389a18
--- /dev/null
+++ b/drivers/video/tegra/TODO
@@ -0,0 +1,5 @@
+Existence of separate Tegra124 video implementations is not an ideal solution
+since generic video setup for Tegra already has Tegra124 support of some degree.
+It is not possible at the time of this note is written to integrate T124 SOR
+and DP without possible regressions. Tegra124 setup for SOR and DP should be
+incorporated into existing setup once such opportunity occurs.
diff --git a/drivers/video/tegra20/tegra-pwm-backlight.c b/drivers/video/tegra/dc-pwm-backlight.c
index 998f0df1991..eff10b5563e 100644
--- a/drivers/video/tegra20/tegra-pwm-backlight.c
+++ b/drivers/video/tegra/dc-pwm-backlight.c
@@ -15,7 +15,7 @@
 #include <asm/io.h>
 #include <asm/gpio.h>
 
-#include "tegra-dc.h"
+#include "dc.h"
 
 #define TEGRA_PWM_BL_MIN_BRIGHTNESS	0x10
 #define TEGRA_PWM_BL_MAX_BRIGHTNESS	0xFF
diff --git a/drivers/video/tegra20/tegra-dc.c b/drivers/video/tegra/dc.c
index 1f43153ff27..f0e3d2c993f 100644
--- a/drivers/video/tegra20/tegra-dc.c
+++ b/drivers/video/tegra/dc.c
@@ -19,7 +19,7 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/powergate.h>
 
-#include "tegra-dc.h"
+#include "dc.h"
 
 /* Holder of Tegra per-SOC DC differences */
 struct tegra_dc_soc_info {
diff --git a/drivers/video/tegra20/tegra-dc.h b/drivers/video/tegra/dc.h
index 2a4013b3355..2a4013b3355 100644
--- a/drivers/video/tegra20/tegra-dc.h
+++ b/drivers/video/tegra/dc.h
diff --git a/drivers/video/tegra20/tegra-dsi.c b/drivers/video/tegra/dsi.c
index a2a22fa0fe2..bc308869f4e 100644
--- a/drivers/video/tegra20/tegra-dsi.c
+++ b/drivers/video/tegra/dsi.c
@@ -24,8 +24,8 @@
 #include <asm/arch/clock.h>
 #include <asm/arch-tegra/clk_rst.h>
 
-#include "tegra-dc.h"
-#include "tegra-dsi.h"
+#include "dc.h"
+#include "dsi.h"
 #include "mipi-phy.h"
 
 /* List of supported DSI bridges */
@@ -1129,6 +1129,7 @@ static const struct video_bridge_ops tegra_dsi_bridge_ops = {
 };
 
 static const struct udevice_id tegra_dsi_bridge_ids[] = {
+	{ .compatible = "nvidia,tegra20-dsi", .data = DSI_V0 },
 	{ .compatible = "nvidia,tegra30-dsi", .data = DSI_V0 },
 	{ .compatible = "nvidia,tegra114-dsi", .data = DSI_V1 },
 	{ .compatible = "nvidia,tegra124-dsi", .data = DSI_V1 },
diff --git a/drivers/video/tegra20/tegra-dsi.h b/drivers/video/tegra/dsi.h
index 683c5e31a34..683c5e31a34 100644
--- a/drivers/video/tegra20/tegra-dsi.h
+++ b/drivers/video/tegra/dsi.h
diff --git a/drivers/video/tegra20/tegra-hdmi.c b/drivers/video/tegra/hdmi.c
index bda69919d92..bfb48b25187 100644
--- a/drivers/video/tegra20/tegra-hdmi.c
+++ b/drivers/video/tegra/hdmi.c
@@ -22,8 +22,8 @@
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 
-#include "tegra-dc.h"
-#include "tegra-hdmi.h"
+#include "dc.h"
+#include "hdmi.h"
 
 #define DDCCI_ENTRY_ADDR	0x37
 #define DDCCI_SOURSE_ADDR	0x51
diff --git a/drivers/video/tegra20/tegra-hdmi.h b/drivers/video/tegra/hdmi.h
index d17655973e3..d17655973e3 100644
--- a/drivers/video/tegra20/tegra-hdmi.h
+++ b/drivers/video/tegra/hdmi.h
diff --git a/drivers/video/tegra20/tegra-host1x.c b/drivers/video/tegra/host1x.c
index 58ab871a3b4..58ab871a3b4 100644
--- a/drivers/video/tegra20/tegra-host1x.c
+++ b/drivers/video/tegra/host1x.c
diff --git a/drivers/video/tegra20/mipi-phy.c b/drivers/video/tegra/mipi-phy.c
index 576262e405d..576262e405d 100644
--- a/drivers/video/tegra20/mipi-phy.c
+++ b/drivers/video/tegra/mipi-phy.c
diff --git a/drivers/video/tegra20/mipi-phy.h b/drivers/video/tegra/mipi-phy.h
index 41889a75035..41889a75035 100644
--- a/drivers/video/tegra20/mipi-phy.h
+++ b/drivers/video/tegra/mipi-phy.h
diff --git a/drivers/video/tegra20/tegra-mipi.c b/drivers/video/tegra/mipi.c
index a4f4343d008..a4f4343d008 100644
--- a/drivers/video/tegra20/tegra-mipi.c
+++ b/drivers/video/tegra/mipi.c
diff --git a/drivers/video/tegra124/Makefile b/drivers/video/tegra/tegra124/Makefile
index a378382628c..a378382628c 100644
--- a/drivers/video/tegra124/Makefile
+++ b/drivers/video/tegra/tegra124/Makefile
diff --git a/drivers/video/tegra124/display.c b/drivers/video/tegra/tegra124/display.c
index abe31e27d84..abe31e27d84 100644
--- a/drivers/video/tegra124/display.c
+++ b/drivers/video/tegra/tegra124/display.c
diff --git a/drivers/video/tegra124/displayport.h b/drivers/video/tegra/tegra124/displayport.h
index a3044475aeb..a3044475aeb 100644
--- a/drivers/video/tegra124/displayport.h
+++ b/drivers/video/tegra/tegra124/displayport.h
diff --git a/drivers/video/tegra124/dp.c b/drivers/video/tegra/tegra124/dp.c
index b95b14da77d..b95b14da77d 100644
--- a/drivers/video/tegra124/dp.c
+++ b/drivers/video/tegra/tegra124/dp.c
diff --git a/drivers/video/tegra124/sor.c b/drivers/video/tegra/tegra124/sor.c
index 1ce5330c6bc..1ce5330c6bc 100644
--- a/drivers/video/tegra124/sor.c
+++ b/drivers/video/tegra/tegra124/sor.c
diff --git a/drivers/video/tegra124/sor.h b/drivers/video/tegra/tegra124/sor.h
index 2fc9a38267d..2fc9a38267d 100644
--- a/drivers/video/tegra124/sor.h
+++ b/drivers/video/tegra/tegra124/sor.h
diff --git a/drivers/video/tegra20/Kconfig b/drivers/video/tegra20/Kconfig
deleted file mode 100644
index 598f9ea1f21..00000000000
--- a/drivers/video/tegra20/Kconfig
+++ /dev/null
@@ -1,38 +0,0 @@
-config HOST1X_TEGRA
-	bool "NVIDIA Tegra host1x BUS support"
-	depends on SIMPLE_BUS
-
-config VIDEO_TEGRA20
-	bool "Enable Display Controller support on Tegra20 and Tegra 30"
-	depends on OF_CONTROL
-	select HOST1X_TEGRA
-	help
-	   T20/T30 support video output to an attached LCD panel as well as
-	   other options such as HDMI. Only the LCD is supported in U-Boot.
-	   This option enables this support which can be used on devices which
-	   have an LCD display connected.
-
-config VIDEO_DSI_TEGRA30
-	bool "Enable Tegra 30 DSI support"
-	depends on VIDEO_BRIDGE && PANEL && DM_GPIO
-	select VIDEO_TEGRA20
-	select VIDEO_MIPI_DSI
-	help
-	   T30 has native support for DSI panels. This option enables support
-	   for such panels which can be used on endeavoru and tf600t.
-
-config VIDEO_HDMI_TEGRA
-	bool "Enable Tegra HDMI support"
-	depends on VIDEO_BRIDGE && DM_I2C
-	select I2C_EDID
-	select VIDEO_TEGRA20
-	help
-	   Tegra has native support for HDMI. This option enables support
-	   for such connection and can be used for any supported device.
-
-config TEGRA_BACKLIGHT_PWM
-	bool "Enable Tegra DC PWM backlight support"
-	depends on BACKLIGHT
-	select VIDEO_TEGRA20
-	help
-	   Tegra DC dependent backlight.
diff --git a/drivers/video/tegra20/Makefile b/drivers/video/tegra20/Makefile
deleted file mode 100644
index 78521405749..00000000000
--- a/drivers/video/tegra20/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-
-obj-$(CONFIG_HOST1X_TEGRA) += tegra-host1x.o
-obj-$(CONFIG_VIDEO_TEGRA20) += tegra-dc.o
-obj-$(CONFIG_VIDEO_DSI_TEGRA30) += tegra-dsi.o tegra-mipi.o mipi-phy.o
-obj-$(CONFIG_VIDEO_HDMI_TEGRA) += tegra-hdmi.o
-obj-$(CONFIG_TEGRA_BACKLIGHT_PWM) += tegra-pwm-backlight.o