diff options
Diffstat (limited to 'drivers')
50 files changed, 500 insertions, 189 deletions
diff --git a/drivers/Makefile b/drivers/Makefile index 4e7cf284405..67c8af74424 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -38,6 +38,7 @@ obj-$(CONFIG_XEN) += xen/ obj-$(CONFIG_$(SPL_)FPGA) += fpga/ ifndef CONFIG_TPL_BUILD +ifndef CONFIG_VPL_BUILD ifdef CONFIG_SPL_BUILD obj-$(CONFIG_SPL_CPU) += cpu/ @@ -62,6 +63,7 @@ obj-$(CONFIG_SPL_THERMAL) += thermal/ endif endif +endif ifdef CONFIG_TPL_BUILD diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c index 2062197afcd..de6131f1d9b 100644 --- a/drivers/ata/ahci.c +++ b/drivers/ata/ahci.c @@ -416,8 +416,8 @@ static int ahci_init_one(struct ahci_uc_priv *uc_priv, struct udevice *dev) uc_priv->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */ #if !defined(CONFIG_DM_SCSI) - uc_priv->mmio_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_5, - PCI_REGION_MEM); + uc_priv->mmio_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_5, 0, 0, + PCI_REGION_TYPE, PCI_REGION_MEM); /* Take from kernel: * JMicron-specific fixup: @@ -1148,8 +1148,8 @@ int ahci_probe_scsi_pci(struct udevice *ahci_dev) ulong base; u16 vendor, device; - base = (ulong)dm_pci_map_bar(ahci_dev, PCI_BASE_ADDRESS_5, - PCI_REGION_MEM); + base = (ulong)dm_pci_map_bar(ahci_dev, PCI_BASE_ADDRESS_5, 0, 0, + PCI_REGION_TYPE, PCI_REGION_MEM); /* * Note: @@ -1164,6 +1164,7 @@ int ahci_probe_scsi_pci(struct udevice *ahci_dev) if (vendor == PCI_VENDOR_ID_CAVIUM && device == PCI_DEVICE_ID_CAVIUM_SATA) base = (uintptr_t)dm_pci_map_bar(ahci_dev, PCI_BASE_ADDRESS_0, + 0, 0, PCI_REGION_TYPE, PCI_REGION_MEM); return ahci_probe_scsi(ahci_dev, base); } diff --git a/drivers/ata/sata_sil.c b/drivers/ata/sata_sil.c index b213ebac2fb..70651545722 100644 --- a/drivers/ata/sata_sil.c +++ b/drivers/ata/sata_sil.c @@ -699,9 +699,11 @@ static int sil_pci_probe(struct udevice *dev) /* Read out all BARs */ sata_info.iobase[0] = (ulong)dm_pci_map_bar(dev, - PCI_BASE_ADDRESS_0, PCI_REGION_MEM); + PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_TYPE, + PCI_REGION_MEM); sata_info.iobase[1] = (ulong)dm_pci_map_bar(dev, - PCI_BASE_ADDRESS_2, PCI_REGION_MEM); + PCI_BASE_ADDRESS_2, 0, 0, PCI_REGION_TYPE, + PCI_REGION_MEM); /* mask out the unused bits */ sata_info.iobase[0] &= 0xffffff80; diff --git a/drivers/bios_emulator/atibios.c b/drivers/bios_emulator/atibios.c index 9547470a2f7..cdc5ba6ad90 100644 --- a/drivers/bios_emulator/atibios.c +++ b/drivers/bios_emulator/atibios.c @@ -368,8 +368,8 @@ void *PCI_mapBIOSImage(struct udevice *pcidev) return NULL; } - BIOSImage = dm_pci_bus_to_virt(pcidev, BIOSImageBus, - PCI_REGION_MEM, 0, MAP_NOCACHE); + BIOSImage = dm_pci_bus_to_virt(pcidev, BIOSImageBus, 0, PCI_REGION_TYPE, + PCI_REGION_MEM, MAP_NOCACHE); /*Change the PCI BAR registers to map it onto the bus.*/ dm_pci_write_config32(pcidev, BIOSImageBAR, 0); diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig index c54b58110cf..d6d1c6e32cc 100644 --- a/drivers/block/Kconfig +++ b/drivers/block/Kconfig @@ -39,6 +39,18 @@ config TPL_BLK be partitioned into several areas, called 'partitions' in U-Boot. A filesystem can be placed in each partition. +config VPL_BLK + bool "Support block devices in VPL" + depends on VPL_DM && BLK + default y + help + Enable support for block devices, such as SCSI, MMC and USB + flash sticks. These provide a block-level interface which permits + reading, writing and (in some cases) erasing blocks. Block + devices often have a partition table which allows the device to + be partitioned into several areas, called 'partitions' in U-Boot. + A filesystem can be placed in each partition. + config BLOCK_CACHE bool "Use block device cache" depends on BLK diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 6dc271f71b1..a62b81a1232 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -30,6 +30,32 @@ config TPL_CLK setting up clocks within TPL, and allows the same drivers to be used as U-Boot proper. +config VPL_CLK + bool "Enable clock support in VPL" + depends on CLK && VPL_DM + help + The clock subsystem adds a small amount of overhead to the image. + If this is acceptable and you have a need to use clock drivers in + SPL, enable this option. It might provide a cleaner interface to + setting up clocks within TPL, and allows the same drivers to be + used as U-Boot proper. + +config CLK_BCM6345 + bool "Clock controller driver for BCM6345" + depends on CLK && ARCH_BMIPS + default y + help + This clock driver adds support for enabling and disabling peripheral + clocks on BCM6345 SoCs. HW has no rate changing capabilities. + +config CLK_BOSTON + def_bool y if TARGET_BOSTON + depends on CLK + select REGMAP + select SYSCON + help + Enable this to support the clocks + config SPL_CLK_CCF bool "SPL Common Clock Framework [CCF] support " depends on SPL diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig index 5c3400417f9..408a8d8e28b 100644 --- a/drivers/core/Kconfig +++ b/drivers/core/Kconfig @@ -35,6 +35,16 @@ config TPL_DM CONFIG_SPL_SYS_MALLOC_F_LEN for more details on how to enable it. Disable this for very small implementations. +config VPL_DM + bool "Enable Driver Model for VPL" + depends on DM && VPL + default y if SPL_DM + help + Enable driver model in VPL. You will need to provide a + suitable malloc() implementation. If you are not using the + full malloc() enabled by CONFIG_SYS_SPL_MALLOC_START, + consider using CONFIG_SYS_MALLOC_SIMPLE. + config DM_WARN bool "Enable warnings in driver model" depends on DM @@ -121,6 +131,15 @@ config SPL_DM_SEQ_ALIAS numbered devices (e.g. serial0 = &serial0). This feature can be disabled if it is not required, to save code space in SPL. +config VPL_DM_SEQ_ALIAS + bool "Support numbered aliases in device tree in VPL" + depends on VPL_DM + default y + help + Most boards will have a '/aliases' node containing the path to + numbered devices (e.g. serial0 = &serial0). This feature can be + disabled if it is not required, to save code space in VPL. + config SPL_DM_INLINE_OFNODE bool "Inline some ofnode functions which are seldom used in SPL" depends on SPL_DM @@ -176,6 +195,16 @@ config TPL_REGMAP support any bus type (I2C, SPI) but so far this only supports direct memory access. +config VPL_REGMAP + bool "Support register maps in VPL" + depends on VPL_DM + help + Hardware peripherals tend to have one or more sets of registers + which can be accessed to control the hardware. A register map + models this with a simple read/write interface. It can in principle + support any bus type (I2C, SPI) but so far this only supports + direct memory access. + config SYSCON bool "Support system controllers" depends on REGMAP @@ -196,7 +225,16 @@ config SPL_SYSCON config TPL_SYSCON bool "Support system controllers in TPL" - depends on TPL_REGMAP + depends on SPL_REGMAP + help + Many SoCs have a number of system controllers which are dealt with + as a group by a single driver. Some common functionality is provided + by this uclass, including accessing registers via regmap and + assigning a unique number to each. + +config VPL_SYSCON + bool "Support system controllers in VPL" + depends on VPL_REGMAP help Many SoCs have a number of system controllers which are dealt with as a group by a single driver. Some common functionality is provided @@ -292,6 +330,20 @@ config SPL_OF_TRANSLATE used for the address translation. This function is faster and smaller in size than fdt_translate_address(). +config VPL_OF_TRANSLATE + bool "Translate addresses using fdt_translate_address in SPL" + depends on SPL_DM && VPL_OF_CONTROL + help + If this option is enabled, the reg property will be translated + using the fdt_translate_address() function. This is necessary + on some platforms (e.g. MVEBU) using complex "ranges" + properties in many nodes. As this translation is not handled + correctly in the default simple_bus_translate() function. + + If this option is not enabled, simple_bus_translate() will be + used for the address translation. This function is faster and + smaller in size than fdt_translate_address(). + config TRANSLATION_OFFSET bool "Platforms specific translation offset" depends on DM && OF_CONTROL diff --git a/drivers/core/Makefile b/drivers/core/Makefile index 7099073a533..bce0a3f65cb 100644 --- a/drivers/core/Makefile +++ b/drivers/core/Makefile @@ -5,7 +5,7 @@ obj-y += device.o fdtaddr.o lists.o root.o uclass.o util.o tag.o obj-$(CONFIG_$(SPL_TPL_)ACPIGEN) += acpi.o obj-$(CONFIG_$(SPL_TPL_)DEVRES) += devres.o -obj-$(CONFIG_$(SPL_)DM_DEVICE_REMOVE) += device-remove.o +obj-$(CONFIG_$(SPL_TPL_)DM_DEVICE_REMOVE) += device-remove.o obj-$(CONFIG_$(SPL_)SIMPLE_BUS) += simple-bus.o obj-$(CONFIG_SIMPLE_PM_BUS) += simple-pm-bus.o obj-$(CONFIG_DM) += dump.o diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 89068c7800d..886cdbcdbaa 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -48,6 +48,17 @@ config TPL_DM_GPIO particular GPIOs that they provide. The uclass interface is defined in include/asm-generic/gpio.h. +config VPL_DM_GPIO + bool "Enable Driver Model for GPIO drivers in VPL" + depends on DM_GPIO && VPL_DM && VPL_GPIO + default y + help + Enable driver model for GPIO access in VPL. The standard GPIO + interface (gpio_get_value(), etc.) is then implemented by + the GPIO uclass. Drivers provide methods to query the + particular GPIOs that they provide. The uclass interface + is defined in include/asm-generic/gpio.h. + config GPIO_HOG bool "Enable GPIO hog support" depends on DM_GPIO diff --git a/drivers/gpio/octeon_gpio.c b/drivers/gpio/octeon_gpio.c index 42eae79d8c4..2b2465b1bcd 100644 --- a/drivers/gpio/octeon_gpio.c +++ b/drivers/gpio/octeon_gpio.c @@ -183,7 +183,7 @@ static int octeon_gpio_probe(struct udevice *dev) priv->data = (const struct octeon_gpio_data *)dev_get_driver_data(dev); if (priv->data->probe == PROBE_PCI) { - priv->base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, + priv->base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_TYPE, PCI_REGION_MEM); uc_priv->gpio_count = readq(priv->base + priv->data->reg_offs + GPIO_CONST) & diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 5482a4a470b..d25c5736ef0 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -47,6 +47,17 @@ config SPL_DM_I2C device (bus child) info is kept as parent platdata. The interface is defined in include/i2c.h. +config VPL_DM_I2C + bool "Enable Driver Model for I2C drivers in VPL" + depends on VPL_DM && DM_I2C + default y + help + Enable driver model for I2C. The I2C uclass interface: probe, read, + write and speed, is implemented with the bus drivers operations, + which provide methods for bus setting and data transfer. Each chip + device (bus child) info is kept as parent platdata. The interface + is defined in include/i2c.h. + config SYS_I2C_LEGACY bool "Enable legacy I2C subsystem and drivers" depends on !DM_I2C diff --git a/drivers/i2c/designware_i2c_pci.c b/drivers/i2c/designware_i2c_pci.c index 9e387737b6e..1572c2c6bce 100644 --- a/drivers/i2c/designware_i2c_pci.c +++ b/drivers/i2c/designware_i2c_pci.c @@ -59,7 +59,8 @@ static int designware_i2c_pci_of_to_plat(struct udevice *dev) priv->regs = (struct i2c_regs *)dm_pci_read_bar32(dev, 0); } else { priv->regs = (struct i2c_regs *) - dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, PCI_REGION_MEM); + dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0, + PCI_REGION_TYPE, PCI_REGION_MEM); } if (!priv->regs) return -EINVAL; diff --git a/drivers/i2c/intel_i2c.c b/drivers/i2c/intel_i2c.c index 52f7a528efe..dc26fa8c542 100644 --- a/drivers/i2c/intel_i2c.c +++ b/drivers/i2c/intel_i2c.c @@ -251,7 +251,7 @@ static int intel_i2c_probe(struct udevice *dev) ulong base; /* Save base address from PCI BAR */ - priv->base = (ulong)dm_pci_map_bar(dev, PCI_BASE_ADDRESS_4, + priv->base = (ulong)dm_pci_map_bar(dev, PCI_BASE_ADDRESS_4, 0, 0, PCI_REGION_TYPE, PCI_REGION_IO); base = priv->base; diff --git a/drivers/i2c/octeon_i2c.c b/drivers/i2c/octeon_i2c.c index 50199ff46ef..e54ef18e515 100644 --- a/drivers/i2c/octeon_i2c.c +++ b/drivers/i2c/octeon_i2c.c @@ -792,7 +792,7 @@ static int octeon_i2c_probe(struct udevice *dev) debug("TWSI PCI device: %x\n", bdf); - twsi->base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, + twsi->base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_TYPE, PCI_REGION_MEM); } else { twsi->base = dev_remap_addr(dev); diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index dab7a99c68c..9af806a20ae 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -131,6 +131,16 @@ config TPL_CROS_EC control access to the battery and main PMIC depending on the device. You can use the 'crosec' command to access it. +config VPL_CROS_EC + bool "Enable Chrome OS EC in VPL" + depends on VPL + help + Enable access to the Chrome OS EC in VPL. This is a separate + microcontroller typically available on a SPI bus on Chromebooks. It + provides access to the keyboard, some internal storage and may + control access to the battery and main PMIC depending on the + device. You can use the 'crosec' command to access it. + config CROS_EC_I2C bool "Enable Chrome OS EC I2C driver" depends on CROS_EC @@ -167,6 +177,15 @@ config TPL_CROS_EC_LPC through a legacy port interface, so on x86 machines the main function of the EC is power and thermal management. +config VPL_CROS_EC_LPC + bool "Enable Chrome OS EC LPC driver in VPL" + depends on CROS_EC + help + Enable I2C access to the Chrome OS EC. This is used on x86 + Chromebooks such as link and falco. The keyboard is provided + through a legacy port interface, so on x86 machines the main + function of the EC is power and thermal management. + config CROS_EC_SANDBOX bool "Enable Chrome OS EC sandbox driver" depends on CROS_EC && SANDBOX @@ -194,6 +213,15 @@ config TPL_CROS_EC_SANDBOX EC flash read/write/erase support and a few other things. It is enough to perform a Chrome OS verified boot on sandbox. +config VPL_CROS_EC_SANDBOX + bool "Enable Chrome OS EC sandbox driver in VPL" + depends on VPL_CROS_EC && SANDBOX + help + Enable a sandbox emulation of the Chrome OS EC in VPL. This supports + keyboard (use the -l flag to enable the LCD), verified boot context, + EC flash read/write/erase support and a few other things. It is + enough to perform a Chrome OS verified boot on sandbox. + config CROS_EC_SPI bool "Enable Chrome OS EC SPI driver" depends on CROS_EC diff --git a/drivers/mmc/octeontx_hsmmc.c b/drivers/mmc/octeontx_hsmmc.c index f0519f0cf89..6e9acf7310a 100644 --- a/drivers/mmc/octeontx_hsmmc.c +++ b/drivers/mmc/octeontx_hsmmc.c @@ -3822,7 +3822,7 @@ static int octeontx_mmc_host_probe(struct udevice *dev) /* Octeon TX & TX2 use PCI based probing */ if (device_is_compatible(dev, "cavium,thunder-8890-mmc")) { - host->base_addr = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, + host->base_addr = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_TYPE, PCI_REGION_MEM); if (!host->base_addr) { pr_err("%s: Error: MMC base address not found\n", diff --git a/drivers/mmc/pci_mmc.c b/drivers/mmc/pci_mmc.c index b9ab064b60e..cba2ea8cf3a 100644 --- a/drivers/mmc/pci_mmc.c +++ b/drivers/mmc/pci_mmc.c @@ -50,7 +50,7 @@ static int pci_mmc_probe(struct udevice *dev) desc = mmc_get_blk_desc(&plat->mmc); desc->removable = !(plat->cfg.host_caps & MMC_CAP_NONREMOVABLE); - host->ioaddr = (void *)dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, + host->ioaddr = (void *)dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_TYPE, PCI_REGION_MEM); host->name = dev->name; host->cd_gpio = priv->cd_gpio; diff --git a/drivers/mtd/nand/raw/octeontx_bch.c b/drivers/mtd/nand/raw/octeontx_bch.c index 24ffa5105f3..c1d721cabfc 100644 --- a/drivers/mtd/nand/raw/octeontx_bch.c +++ b/drivers/mtd/nand/raw/octeontx_bch.c @@ -176,7 +176,8 @@ static int octeontx_pci_bchpf_probe(struct udevice *dev) if (!bch) return -ENOMEM; - bch->reg_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, PCI_REGION_MEM); + bch->reg_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0, + PCI_REGION_TYPE, PCI_REGION_MEM); bch->dev = dev; debug("%s: base address: %p\n", __func__, bch->reg_base); @@ -361,7 +362,8 @@ static int octeontx_pci_bchvf_probe(struct udevice *dev) vf->dev = dev; /* Map PF's configuration registers */ - vf->reg_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, PCI_REGION_MEM); + vf->reg_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0, + PCI_REGION_TYPE, PCI_REGION_MEM); debug("%s: reg base: %p\n", __func__, vf->reg_base); err = octeontx_cmd_queue_initialize(dev, QID_BCH, QDEPTH - 1, 0, diff --git a/drivers/mtd/nand/raw/octeontx_nand.c b/drivers/mtd/nand/raw/octeontx_nand.c index ff363a56b51..b338b204f34 100644 --- a/drivers/mtd/nand/raw/octeontx_nand.c +++ b/drivers/mtd/nand/raw/octeontx_nand.c @@ -2098,7 +2098,7 @@ static int octeontx_pci_nand_probe(struct udevice *dev) tn->dev = dev; INIT_LIST_HEAD(&tn->chips); - tn->base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, PCI_REGION_MEM); + tn->base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_TYPE, PCI_REGION_MEM); if (!tn->base) { ret = -EINVAL; goto release; diff --git a/drivers/net/bnxt/bnxt.c b/drivers/net/bnxt/bnxt.c index 9844e96072e..1c9a9962408 100644 --- a/drivers/net/bnxt/bnxt.c +++ b/drivers/net/bnxt/bnxt.c @@ -28,9 +28,12 @@ static void bnxt_bring_pci(struct bnxt *bp) dm_pci_read_config16(bp->pdev, PCI_SUBSYSTEM_ID, &bp->subsystem_device); dm_pci_read_config16(bp->pdev, PCI_COMMAND, &bp->cmd_reg); dm_pci_read_config8(bp->pdev, PCI_INTERRUPT_LINE, &bp->irq); - bp->bar0 = dm_pci_map_bar(bp->pdev, PCI_BASE_ADDRESS_0, PCI_REGION_MEM); - bp->bar1 = dm_pci_map_bar(bp->pdev, PCI_BASE_ADDRESS_2, PCI_REGION_MEM); - bp->bar2 = dm_pci_map_bar(bp->pdev, PCI_BASE_ADDRESS_4, PCI_REGION_MEM); + bp->bar0 = dm_pci_map_bar(bp->pdev, PCI_BASE_ADDRESS_0, 0, 0, + PCI_REGION_TYPE, PCI_REGION_MEM); + bp->bar1 = dm_pci_map_bar(bp->pdev, PCI_BASE_ADDRESS_2, 0, 0, + PCI_REGION_TYPE, PCI_REGION_MEM); + bp->bar2 = dm_pci_map_bar(bp->pdev, PCI_BASE_ADDRESS_4, 0, 0, + PCI_REGION_TYPE, PCI_REGION_MEM); cmd_reg = bp->cmd_reg | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; cmd_reg |= PCI_COMMAND_INTX_DISABLE; /* disable intr */ dm_pci_write_config16(bp->pdev, PCI_COMMAND, cmd_reg); diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c index 4e34248ff6f..5fe016ebaf7 100644 --- a/drivers/net/e1000.c +++ b/drivers/net/e1000.c @@ -5549,8 +5549,8 @@ static int e1000_init_one(struct e1000_hw *hw, int cardnum, pci_dev_t devno, hw->eeprom_semaphore_present = true; #endif #ifdef CONFIG_DM_ETH - hw->hw_addr = dm_pci_map_bar(devno, PCI_BASE_ADDRESS_0, - PCI_REGION_MEM); + hw->hw_addr = dm_pci_map_bar(devno, PCI_BASE_ADDRESS_0, 0, 0, + PCI_REGION_TYPE, PCI_REGION_MEM); #else hw->hw_addr = pci_map_bar(devno, PCI_BASE_ADDRESS_0, PCI_REGION_MEM); diff --git a/drivers/net/fsl_enetc.c b/drivers/net/fsl_enetc.c index 1724f948bcd..9b97a03ccb3 100644 --- a/drivers/net/fsl_enetc.c +++ b/drivers/net/fsl_enetc.c @@ -339,7 +339,7 @@ static int enetc_probe(struct udevice *dev) } /* initialize register */ - priv->regs_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0); + priv->regs_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_TYPE, 0); if (!priv->regs_base) { enetc_dbg(dev, "failed to map BAR0\n"); return -EINVAL; diff --git a/drivers/net/fsl_enetc_mdio.c b/drivers/net/fsl_enetc_mdio.c index 3eb6ac9fc8f..50ad76dfeb5 100644 --- a/drivers/net/fsl_enetc_mdio.c +++ b/drivers/net/fsl_enetc_mdio.c @@ -125,7 +125,7 @@ static int enetc_mdio_probe(struct udevice *dev) { struct enetc_mdio_priv *priv = dev_get_priv(dev); - priv->regs_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0); + priv->regs_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_TYPE, 0); if (!priv->regs_base) { enetc_dbg(dev, "failed to map BAR0\n"); return -EINVAL; diff --git a/drivers/net/mscc_eswitch/felix_switch.c b/drivers/net/mscc_eswitch/felix_switch.c index 60b2e8f32d4..709c9e3ef51 100644 --- a/drivers/net/mscc_eswitch/felix_switch.c +++ b/drivers/net/mscc_eswitch/felix_switch.c @@ -292,13 +292,13 @@ static int felix_probe(struct udevice *dev) return -ENODEV; } - priv->imdio_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0); + priv->imdio_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_TYPE, 0); if (!priv->imdio_base) { dev_err(dev, "failed to map BAR0\n"); return -EINVAL; } - priv->regs_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_4, 0); + priv->regs_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_4, 0, 0, PCI_REGION_TYPE, 0); if (!priv->regs_base) { dev_err(dev, "failed to map BAR4\n"); return -EINVAL; diff --git a/drivers/net/mvgbe.c b/drivers/net/mvgbe.c index bf5ed5513ba..a77c0574326 100644 --- a/drivers/net/mvgbe.c +++ b/drivers/net/mvgbe.c @@ -43,6 +43,7 @@ DECLARE_GLOBAL_DATA_PTR; #define MV_PHY_ADR_REQUEST 0xee #define MVGBE_SMI_REG (((struct mvgbe_registers *)MVGBE0_BASE)->smi) +#define MVGBE_PGADR_REG 22 #if defined(CONFIG_PHYLIB) || defined(CONFIG_MII) || defined(CONFIG_CMD_MII) static int smi_wait_ready(struct mvgbe_device *dmvgbe) @@ -745,6 +746,9 @@ static struct phy_device *__mvgbe_phy_init(struct eth_device *dev, miiphy_write(dev->name, MV_PHY_ADR_REQUEST, MV_PHY_ADR_REQUEST, phyid); + /* Make sure the selected PHY page is 0 before connecting */ + miiphy_write(dev->name, phyid, MVGBE_PGADR_REG, 0); + phydev = phy_connect(bus, phyid, dev, phy_interface); if (!phydev) { printf("phy_connect failed\n"); diff --git a/drivers/net/octeontx/bgx.c b/drivers/net/octeontx/bgx.c index a5c0c9fe2b3..b6592ff2ce5 100644 --- a/drivers/net/octeontx/bgx.c +++ b/drivers/net/octeontx/bgx.c @@ -1458,7 +1458,7 @@ int octeontx_bgx_probe(struct udevice *dev) int bgx_idx, node; int inc = 1; - bgx->reg_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, + bgx->reg_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_TYPE, PCI_REGION_MEM); if (!bgx->reg_base) { debug("No PCI region found\n"); diff --git a/drivers/net/octeontx/nic_main.c b/drivers/net/octeontx/nic_main.c index 0f36f2586e6..99886e3afc0 100644 --- a/drivers/net/octeontx/nic_main.c +++ b/drivers/net/octeontx/nic_main.c @@ -713,7 +713,7 @@ int nic_initialize(struct udevice *dev) return -ENOMEM; /* MAP PF's configuration registers */ - nic->reg_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, + nic->reg_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_TYPE, PCI_REGION_MEM); if (!nic->reg_base) { printf("Cannot map config register space, aborting\n"); diff --git a/drivers/net/octeontx/nicvf_main.c b/drivers/net/octeontx/nicvf_main.c index c30ba49c27c..6e4d0a05121 100644 --- a/drivers/net/octeontx/nicvf_main.c +++ b/drivers/net/octeontx/nicvf_main.c @@ -509,7 +509,7 @@ int nicvf_initialize(struct udevice *dev) /* Enable TSO support */ nicvf->hw_tso = true; - nicvf->reg_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, + nicvf->reg_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_TYPE, PCI_REGION_MEM); debug("nicvf->reg_base: %p\n", nicvf->reg_base); diff --git a/drivers/net/octeontx/smi.c b/drivers/net/octeontx/smi.c index d70fa820c7b..233c26f7319 100644 --- a/drivers/net/octeontx/smi.c +++ b/drivers/net/octeontx/smi.c @@ -322,7 +322,7 @@ int octeontx_smi_probe(struct udevice *dev) u64 baseaddr; debug("SMI PCI device: %x\n", bdf); - if (!dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, PCI_REGION_MEM)) { + if (!dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_TYPE, PCI_REGION_MEM)) { printf("Failed to map PCI region for bdf %x\n", bdf); return -1; } diff --git a/drivers/net/octeontx2/cgx.c b/drivers/net/octeontx2/cgx.c index d139029f4e5..c6ec3200c01 100644 --- a/drivers/net/octeontx2/cgx.c +++ b/drivers/net/octeontx2/cgx.c @@ -253,7 +253,7 @@ int cgx_probe(struct udevice *dev) struct cgx *cgx = dev_get_priv(dev); int err; - cgx->reg_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, + cgx->reg_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_TYPE, PCI_REGION_MEM); cgx->dev = dev; cgx->cgx_id = ((u64)(cgx->reg_base) >> 24) & 0x7; diff --git a/drivers/net/octeontx2/rvu_af.c b/drivers/net/octeontx2/rvu_af.c index d2f96548611..0d3a9ffe9ee 100644 --- a/drivers/net/octeontx2/rvu_af.c +++ b/drivers/net/octeontx2/rvu_af.c @@ -127,7 +127,7 @@ int rvu_af_probe(struct udevice *dev) { struct rvu_af *af_ptr = dev_get_priv(dev); - af_ptr->af_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, + af_ptr->af_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_TYPE, PCI_REGION_MEM); debug("%s RVU AF BAR %p\n", __func__, af_ptr->af_base); af_ptr->dev = dev; diff --git a/drivers/net/octeontx2/rvu_pf.c b/drivers/net/octeontx2/rvu_pf.c index 4b00178989c..5f3ea1f8eab 100644 --- a/drivers/net/octeontx2/rvu_pf.c +++ b/drivers/net/octeontx2/rvu_pf.c @@ -58,7 +58,8 @@ int rvu_pf_probe(struct udevice *dev) debug("%s: name: %s\n", __func__, dev->name); - rvu->pf_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_2, PCI_REGION_MEM); + rvu->pf_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_2, 0, 0, + PCI_REGION_TYPE, PCI_REGION_MEM); rvu->pfid = dev_seq(dev) + 1; // RVU PF's start from 1; rvu->dev = dev; if (!rvu_af_dev) { diff --git a/drivers/net/pch_gbe.c b/drivers/net/pch_gbe.c index f1895246b93..ad7b5b8e99b 100644 --- a/drivers/net/pch_gbe.c +++ b/drivers/net/pch_gbe.c @@ -449,7 +449,7 @@ static int pch_gbe_probe(struct udevice *dev) priv->dev = dev; - iobase = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_1, PCI_REGION_MEM); + iobase = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_1, 0, 0, PCI_REGION_TYPE, PCI_REGION_MEM); plat->iobase = (ulong)iobase; priv->mac_regs = (struct pch_gbe_regs *)iobase; diff --git a/drivers/nvme/nvme_pci.c b/drivers/nvme/nvme_pci.c index 5f60fb884fb..36bf9c5ffb7 100644 --- a/drivers/nvme/nvme_pci.c +++ b/drivers/nvme/nvme_pci.c @@ -28,8 +28,8 @@ static int nvme_probe(struct udevice *udev) sprintf(ndev->vendor, "0x%.4x", pplat->vendor); ndev->instance = trailing_strtol(udev->name); - ndev->bar = dm_pci_map_bar(udev, PCI_BASE_ADDRESS_0, - PCI_REGION_MEM); + ndev->bar = dm_pci_map_bar(udev, PCI_BASE_ADDRESS_0, 0, 0, + PCI_REGION_TYPE, PCI_REGION_MEM); return nvme_init(udev); } diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 47cd074aa14..fd2203420c3 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -67,6 +67,13 @@ config PCI_SRIOV if available on a PCI Physical Function device and probe for applicable drivers. +config PCI_ENHANCED_ALLOCATION + bool "Enable support for Enhanced Allocation of resources" + default y + help + Enable support for Enhanced Allocation which can be used by supported + devices in place of traditional BARS for allocation of resources. + config PCI_ARID bool "Enable Alternate Routing-ID support for PCI" help diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index 33dda00002e..970ee1adf1b 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -645,7 +645,11 @@ int dm_pci_hose_probe_bus(struct udevice *bus) return log_msg_ret("probe", -EINVAL); } - ea_pos = dm_pci_find_capability(bus, PCI_CAP_ID_EA); + if (IS_ENABLED(CONFIG_PCI_ENHANCED_ALLOCATION)) + ea_pos = dm_pci_find_capability(bus, PCI_CAP_ID_EA); + else + ea_pos = 0; + if (ea_pos) { dm_pci_read_config8(bus, ea_pos + sizeof(u32) + sizeof(u8), ®); @@ -1013,7 +1017,22 @@ static void decode_regions(struct pci_controller *hose, ofnode parent_node, if (!IS_ENABLED(CONFIG_SYS_PCI_64BIT) && type == PCI_REGION_MEM && upper_32_bits(pci_addr)) { - debug(" - beyond the 32-bit boundary, ignoring\n"); + debug(" - pci_addr beyond the 32-bit boundary, ignoring\n"); + continue; + } + + if (!IS_ENABLED(CONFIG_PHYS_64BIT) && upper_32_bits(addr)) { + debug(" - addr beyond the 32-bit boundary, ignoring\n"); + continue; + } + + if (~((pci_addr_t)0) - pci_addr < size) { + debug(" - PCI range exceeds max address, ignoring\n"); + continue; + } + + if (~((phys_addr_t)0) - addr < size) { + debug(" - phys range exceeds max address, ignoring\n"); continue; } @@ -1375,131 +1394,84 @@ void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr) dm_pci_write_config32(dev, bar, addr); } -static int _dm_pci_bus_to_phys(struct udevice *ctlr, - pci_addr_t bus_addr, unsigned long flags, - unsigned long skip_mask, phys_addr_t *pa) +phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t bus_addr, + size_t len, unsigned long mask, + unsigned long flags) { - struct pci_controller *hose = dev_get_uclass_priv(ctlr); + struct udevice *ctlr; + struct pci_controller *hose; struct pci_region *res; + pci_addr_t offset; int i; - if (hose->region_count == 0) { - *pa = bus_addr; - return 0; - } + /* The root controller has the region information */ + ctlr = pci_get_controller(dev); + hose = dev_get_uclass_priv(ctlr); + + if (hose->region_count == 0) + return bus_addr; for (i = 0; i < hose->region_count; i++) { res = &hose->regions[i]; - if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0) + if ((res->flags & mask) != flags) continue; - if (res->flags & skip_mask) + if (bus_addr < res->bus_start) continue; - if (bus_addr >= res->bus_start && - (bus_addr - res->bus_start) < res->size) { - *pa = (bus_addr - res->bus_start + res->phys_start); - return 0; - } - } - - return 1; -} - -phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t bus_addr, - unsigned long flags) -{ - phys_addr_t phys_addr = 0; - struct udevice *ctlr; - int ret; + offset = bus_addr - res->bus_start; + if (offset >= res->size) + continue; - /* The root controller has the region information */ - ctlr = pci_get_controller(dev); + if (len > res->size - offset) + continue; - /* - * if PCI_REGION_MEM is set we do a two pass search with preference - * on matches that don't have PCI_REGION_SYS_MEMORY set - */ - if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) { - ret = _dm_pci_bus_to_phys(ctlr, bus_addr, - flags, PCI_REGION_SYS_MEMORY, - &phys_addr); - if (!ret) - return phys_addr; + return res->phys_start + offset; } - ret = _dm_pci_bus_to_phys(ctlr, bus_addr, flags, 0, &phys_addr); - - if (ret) - puts("pci_hose_bus_to_phys: invalid physical address\n"); - - return phys_addr; + puts("pci_hose_bus_to_phys: invalid physical address\n"); + return 0; } -static int _dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr, - unsigned long flags, unsigned long skip_mask, - pci_addr_t *ba) +pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr, + size_t len, unsigned long mask, + unsigned long flags) { - struct pci_region *res; struct udevice *ctlr; - pci_addr_t bus_addr; - int i; struct pci_controller *hose; + struct pci_region *res; + phys_addr_t offset; + int i; /* The root controller has the region information */ ctlr = pci_get_controller(dev); hose = dev_get_uclass_priv(ctlr); - if (hose->region_count == 0) { - *ba = phys_addr; - return 0; - } + if (hose->region_count == 0) + return phys_addr; for (i = 0; i < hose->region_count; i++) { res = &hose->regions[i]; - if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0) + if ((res->flags & mask) != flags) continue; - if (res->flags & skip_mask) + if (phys_addr < res->phys_start) continue; - bus_addr = phys_addr - res->phys_start + res->bus_start; - - if (bus_addr >= res->bus_start && - (bus_addr - res->bus_start) < res->size) { - *ba = bus_addr; - return 0; - } - } - - return 1; -} + offset = phys_addr - res->phys_start; + if (offset >= res->size) + continue; -pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr, - unsigned long flags) -{ - pci_addr_t bus_addr = 0; - int ret; + if (len > res->size - offset) + continue; - /* - * if PCI_REGION_MEM is set we do a two pass search with preference - * on matches that don't have PCI_REGION_SYS_MEMORY set - */ - if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) { - ret = _dm_pci_phys_to_bus(dev, phys_addr, flags, - PCI_REGION_SYS_MEMORY, &bus_addr); - if (!ret) - return bus_addr; + return res->bus_start + offset; } - ret = _dm_pci_phys_to_bus(dev, phys_addr, flags, 0, &bus_addr); - - if (ret) - puts("pci_hose_phys_to_bus: invalid physical address\n"); - - return bus_addr; + puts("pci_hose_phys_to_bus: invalid physical address\n"); + return 0; } static phys_addr_t dm_pci_map_ea_virt(struct udevice *dev, int ea_off, @@ -1533,8 +1505,9 @@ static phys_addr_t dm_pci_map_ea_virt(struct udevice *dev, int ea_off, return addr; } -static void *dm_pci_map_ea_bar(struct udevice *dev, int bar, int flags, - int ea_off, struct pci_child_plat *pdata) +static void *dm_pci_map_ea_bar(struct udevice *dev, int bar, size_t offset, + size_t len, int ea_off, + struct pci_child_plat *pdata) { int ea_cnt, i, entry_size; int bar_id = (bar - PCI_BASE_ADDRESS_0) >> 2; @@ -1576,14 +1549,18 @@ static void *dm_pci_map_ea_bar(struct udevice *dev, int bar, int flags, if (IS_ENABLED(CONFIG_PCI_SRIOV)) addr += dm_pci_map_ea_virt(dev, ea_off, pdata); + if (~((phys_addr_t)0) - addr < offset) + return NULL; + /* size ignored for now */ - return map_physmem(addr, 0, flags); + return map_physmem(addr + offset, len, MAP_NOCACHE); } return 0; } -void *dm_pci_map_bar(struct udevice *dev, int bar, int flags) +void *dm_pci_map_bar(struct udevice *dev, int bar, size_t offset, size_t len, + unsigned long mask, unsigned long flags) { struct pci_child_plat *pdata = dev_get_parent_plat(dev); struct udevice *udev = dev; @@ -1606,21 +1583,29 @@ void *dm_pci_map_bar(struct udevice *dev, int bar, int flags) * Incase of virtual functions, pdata will help read VF BEI * and EA entry size. */ - ea_off = dm_pci_find_capability(udev, PCI_CAP_ID_EA); + if (IS_ENABLED(CONFIG_PCI_ENHANCED_ALLOCATION)) + ea_off = dm_pci_find_capability(udev, PCI_CAP_ID_EA); + else + ea_off = 0; + if (ea_off) - return dm_pci_map_ea_bar(udev, bar, flags, ea_off, pdata); + return dm_pci_map_ea_bar(udev, bar, offset, len, ea_off, pdata); /* read BAR address */ dm_pci_read_config32(udev, bar, &bar_response); pci_bus_addr = (pci_addr_t)(bar_response & ~0xf); + if (~((pci_addr_t)0) - pci_bus_addr < offset) + return NULL; + /* - * Pass "0" as the length argument to pci_bus_to_virt. The arg - * isn't actually used on any platform because U-Boot assumes a static - * linear mapping. In the future, this could read the BAR size - * and pass that as the size if needed. + * Forward the length argument to dm_pci_bus_to_virt. The length will + * be used to check that the entire address range has been declared as + * a PCI range, but a better check would be to probe for the size of + * the bar and prevent overflow more locally. */ - return dm_pci_bus_to_virt(udev, pci_bus_addr, flags, 0, MAP_NOCACHE); + return dm_pci_bus_to_virt(udev, pci_bus_addr + offset, len, mask, flags, + MAP_NOCACHE); } static int _dm_pci_find_next_capability(struct udevice *dev, u8 pos, int cap) diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 13033198f96..563d96d4f5d 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -89,20 +89,34 @@ config TPL_PINCTRL This option is an TPL variant of the PINCTRL option. See the help of PINCTRL for details. +config VPL_PINCTRL + bool "Support pin controllers in VPL" + depends on VPL && VPL_DM + help + This option is an VPL variant of the PINCTRL option. + See the help of PINCTRL for details. + config SPL_PINCTRL_FULL bool "Support full pin controllers in SPL" depends on SPL_PINCTRL && SPL_OF_CONTROL default n if TARGET_STM32F746_DISCO default y help - This option is an SPL-variant of the PINCTRL_FULL option. + This option is an SPL variant of the PINCTRL_FULL option. See the help of PINCTRL_FULL for details. config TPL_PINCTRL_FULL bool "Support full pin controllers in TPL" depends on TPL_PINCTRL && TPL_OF_CONTROL help - This option is an TPL-variant of the PINCTRL_FULL option. + This option is a TPL variant of the PINCTRL_FULL option. + See the help of PINCTRL_FULL for details. + +config VPL_PINCTRL_FULL + bool "Support full pin controllers in VPL" + depends on VPL_PINCTRL && VPL_OF_CONTROL + help + This option is a VPL variant of the PINCTRL_FULL option. See the help of PINCTRL_FULL for details. config SPL_PINCTRL_GENERIC diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 7a6c6efb4b0..23963271928 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -32,6 +32,15 @@ config TPL_DM_RTC drivers to perform the actual functions. See rtc.h for a description of the API. +config VPL_DM_RTC + bool "Enable Driver Model for RTC drivers in VPL" + depends on VPL_DM + help + Enable drver model for real-time-clock drivers. The RTC uclass + then provides the rtc_get()/rtc_set() interface, delegating to + drivers to perform the actual functions. See rtc.h for a + description of the API. + config RTC_ENABLE_32KHZ_OUTPUT bool "Enable RTC 32Khz output" help diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 1e595d06004..5dcf5c019da 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -74,6 +74,16 @@ config TPL_SERIAL_PRESENT This option enables the full UART in TPL, so if is it disabled, the full UART driver will be omitted, thus saving space. +config VPL_SERIAL_PRESENT + bool "Provide a serial driver in VPL" + depends on DM_SERIAL && VPL + default y + help + In very space-constrained devices even the full UART driver is too + large. In this case the debug UART can still be used in some cases. + This option enables the full UART in TPL, so if is it disabled, + the full UART driver will be omitted, thus saving space. + # Logic to allow us to use the imply keyword to set what the default port # should be. The default is otherwise 1. config CONS_INDEX_0 @@ -195,6 +205,16 @@ config TPL_DM_SERIAL implements serial_putc() etc. The uclass interface is defined in include/serial.h. +config VPL_DM_SERIAL + bool "Enable Driver Model for serial drivers in VPL" + depends on DM_SERIAL + default y if VPL && DM_SERIAL + help + Enable driver model for serial in VPL. This replaces + drivers/serial/serial.c with the serial uclass, which + implements serial_putc() etc. The uclass interface is + defined in include/serial.h. + config DEBUG_UART bool "Enable an early debug UART for debugging" help diff --git a/drivers/spi/octeon_spi.c b/drivers/spi/octeon_spi.c index fcabc112d20..c2a7ee232b9 100644 --- a/drivers/spi/octeon_spi.c +++ b/drivers/spi/octeon_spi.c @@ -568,7 +568,7 @@ static int octeon_spi_probe(struct udevice *dev) pci_dev_t bdf = dm_pci_get_bdf(dev); debug("SPI PCI device: %x\n", bdf); - priv->base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, + priv->base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_TYPE, PCI_REGION_MEM); /* Add base offset */ priv->base += 0x1000; diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig index 25dd02c7049..a0acffa4b07 100644 --- a/drivers/sysreset/Kconfig +++ b/drivers/sysreset/Kconfig @@ -31,6 +31,16 @@ config TPL_SYSRESET to effect a reset. The uclass will try all available drivers when reset_walk() is called. +config VPL_SYSRESET + bool "Enable support for system reset drivers in VPL mode" + depends on SYSRESET && VPL_DM + default y if TPL_SYSRESET + help + Enable system reset drivers which can be used to reset the CPU or + board. Each driver can provide a reset method which will be called + to effect a reset. The uclass will try all available drivers when + reset_walk() is called. + if SYSRESET config SYSRESET_CMD_RESET diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index 92050179c28..2eda3bcca5b 100644 --- a/drivers/timer/Kconfig +++ b/drivers/timer/Kconfig @@ -27,6 +27,16 @@ config TPL_TIMER function. This enables the drivers in drivers/timer as part of an TPL build. +config VPL_TIMER + bool "Enable driver model for timer drivers in VPL" + depends on TIMER && VPL + default y if TPL_TIMER + help + Enable support for timer drivers in VPL. These can be used to get + a timer value when in VPL, or perhaps for implementing a delay + function. This enables the drivers in drivers/timer as part of an + TPL build. + config TIMER_EARLY bool "Allow timer to be used early in U-Boot" depends on TIMER diff --git a/drivers/tpm/Kconfig b/drivers/tpm/Kconfig index 406ee8716e1..eceff27d5f8 100644 --- a/drivers/tpm/Kconfig +++ b/drivers/tpm/Kconfig @@ -137,6 +137,36 @@ config TPM2_CR50_I2C trust for a device, It operates like a TPM and can be used with verified boot. Cr50 is used on recent Chromebooks (since 2017). +config SPL_TPM2_CR50_I2C + bool "Enable support for Google cr50 TPM" + depends on DM_I2C && SPL_TPM + help + Cr50 is an implementation of a TPM on Google's H1 security chip. + This uses the same open-source firmware as the Chromium OS EC. + While Cr50 has other features, its primary role is as the root of + trust for a device, It operates like a TPM and can be used with + verified boot. Cr50 is used on recent Chromebooks (since 2017). + +config TPL_TPM2_CR50_I2C + bool "Enable support for Google cr50 TPM" + depends on DM_I2C && TPL_TPM + help + Cr50 is an implementation of a TPM on Google's H1 security chip. + This uses the same open-source firmware as the Chromium OS EC. + While Cr50 has other features, its primary role is as the root of + trust for a device, It operates like a TPM and can be used with + verified boot. Cr50 is used on recent Chromebooks (since 2017). + +config VPL_TPM2_CR50_I2C + bool "Enable support for Google cr50 TPM" + depends on DM_I2C && VPL_TPM + help + Cr50 is an implementation of a TPM on Google's H1 security chip. + This uses the same open-source firmware as the Chromium OS EC. + While Cr50 has other features, its primary role is as the root of + trust for a device, It operates like a TPM and can be used with + verified boot. Cr50 is used on recent Chromebooks (since 2017). + config TPM2_TIS_SANDBOX bool "Enable sandbox TPMv2.x driver" depends on TPM_V2 && SANDBOX diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c index 4f711de7d85..1ab306147fa 100644 --- a/drivers/usb/host/ehci-pci.c +++ b/drivers/usb/host/ehci-pci.c @@ -36,7 +36,8 @@ static int ehci_pci_init(struct udevice *dev, struct ehci_hccr **ret_hccr, return ret; hccr = (struct ehci_hccr *)dm_pci_map_bar(dev, - PCI_BASE_ADDRESS_0, PCI_REGION_MEM); + PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_TYPE, + PCI_REGION_MEM); hcor = (struct ehci_hcor *)((uintptr_t) hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase))); diff --git a/drivers/usb/host/ohci-pci.c b/drivers/usb/host/ohci-pci.c index 6ddc9da704f..f061aec2896 100644 --- a/drivers/usb/host/ohci-pci.c +++ b/drivers/usb/host/ohci-pci.c @@ -18,7 +18,7 @@ static int ohci_pci_probe(struct udevice *dev) { struct ohci_regs *regs; - regs = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, PCI_REGION_MEM); + regs = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_TYPE, PCI_REGION_MEM); return ohci_register(dev, regs); } diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c index 630bc20be1e..11f1c02000a 100644 --- a/drivers/usb/host/xhci-pci.c +++ b/drivers/usb/host/xhci-pci.c @@ -27,7 +27,8 @@ static int xhci_pci_init(struct udevice *dev, struct xhci_hccr **ret_hccr, u32 cmd; hccr = (struct xhci_hccr *)dm_pci_map_bar(dev, - PCI_BASE_ADDRESS_0, PCI_REGION_MEM); + PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_TYPE, + PCI_REGION_MEM); if (!hccr) { printf("xhci-pci init cannot map PCI mem bar\n"); return -EIO; diff --git a/drivers/virtio/Kconfig b/drivers/virtio/Kconfig index 863c3fbe029..586263ec884 100644 --- a/drivers/virtio/Kconfig +++ b/drivers/virtio/Kconfig @@ -37,6 +37,15 @@ config VIRTIO_PCI This driver provides support for virtio based paravirtual device drivers over PCI. +config VIRTIO_PCI_LEGACY + bool "PCI driver for legacy virtio devices" + depends on PCI + select VIRTIO + default VIRTIO_PCI + help + This driver provides support for legacy virtio based paravirtual + device drivers over PCI. + config VIRTIO_SANDBOX bool "Sandbox driver for virtio devices" depends on SANDBOX diff --git a/drivers/virtio/Makefile b/drivers/virtio/Makefile index dc8880937a8..4c63a6c6904 100644 --- a/drivers/virtio/Makefile +++ b/drivers/virtio/Makefile @@ -5,7 +5,8 @@ obj-y += virtio-uclass.o virtio_ring.o obj-$(CONFIG_VIRTIO_MMIO) += virtio_mmio.o -obj-$(CONFIG_VIRTIO_PCI) += virtio_pci_legacy.o virtio_pci_modern.o +obj-$(CONFIG_VIRTIO_PCI) += virtio_pci_modern.o +obj-$(CONFIG_VIRTIO_PCI_LEGACY) += virtio_pci_legacy.o obj-$(CONFIG_VIRTIO_SANDBOX) += virtio_sandbox.o obj-$(CONFIG_VIRTIO_NET) += virtio_net.o obj-$(CONFIG_VIRTIO_BLK) += virtio_blk.o diff --git a/drivers/virtio/virtio_pci_legacy.c b/drivers/virtio/virtio_pci_legacy.c index 03fa5cb608c..cf5dfb17a94 100644 --- a/drivers/virtio/virtio_pci_legacy.c +++ b/drivers/virtio/virtio_pci_legacy.c @@ -319,7 +319,8 @@ static int virtio_pci_probe(struct udevice *udev) uc_priv->device = subdevice; uc_priv->vendor = subvendor; - priv->ioaddr = dm_pci_map_bar(udev, PCI_BASE_ADDRESS_0, PCI_REGION_IO); + priv->ioaddr = dm_pci_map_bar(udev, PCI_BASE_ADDRESS_0, 0, 0, + PCI_REGION_TYPE, PCI_REGION_IO); if (!priv->ioaddr) return -ENXIO; debug("(%s): virtio legacy device reg base %04lx\n", diff --git a/drivers/virtio/virtio_pci_modern.c b/drivers/virtio/virtio_pci_modern.c index fd8a1f3fecb..880a12cc283 100644 --- a/drivers/virtio/virtio_pci_modern.c +++ b/drivers/virtio/virtio_pci_modern.c @@ -94,6 +94,7 @@ * * @common: pci transport device common register block base * @notify_base: pci transport device notify register block base + * @notify_len: pci transport device notify register block length * @device: pci transport device device-specific register block base * @device_len: pci transport device device-specific register block length * @notify_offset_multiplier: multiply queue_notify_off by this value @@ -101,6 +102,7 @@ struct virtio_pci_priv { struct virtio_pci_common_cfg __iomem *common; void __iomem *notify_base; + u32 notify_len; void __iomem *device; u32 device_len; u32 notify_offset_multiplier; @@ -114,7 +116,11 @@ static int virtio_pci_get_config(struct udevice *udev, unsigned int offset, __le16 w; __le32 l; - WARN_ON(offset + len > priv->device_len); + if (!priv->device) + return -ENOSYS; + + if (offset + len > priv->device_len) + return -EINVAL; switch (len) { case 1: @@ -136,7 +142,7 @@ static int virtio_pci_get_config(struct udevice *udev, unsigned int offset, memcpy(buf + sizeof(l), &l, sizeof(l)); break; default: - WARN_ON(true); + return -EINVAL; } return 0; @@ -150,7 +156,11 @@ static int virtio_pci_set_config(struct udevice *udev, unsigned int offset, __le16 w; __le32 l; - WARN_ON(offset + len > priv->device_len); + if (!priv->device) + return -ENOSYS; + + if (offset + len > priv->device_len) + return -EINVAL; switch (len) { case 1: @@ -172,7 +182,7 @@ static int virtio_pci_set_config(struct udevice *udev, unsigned int offset, iowrite32(le32_to_cpu(l), priv->device + offset + sizeof(l)); break; default: - WARN_ON(true); + return -EINVAL; } return 0; @@ -365,11 +375,19 @@ static int virtio_pci_notify(struct udevice *udev, struct virtqueue *vq) off = ioread16(&priv->common->queue_notify_off); /* + * Check the effective offset is in bounds and leaves space for the + * notification, which is just a single 16-bit value since + * VIRTIO_F_NOTIFICATION_DATA isn't negotiated by the drivers. + */ + off *= priv->notify_offset_multiplier; + if (off > priv->notify_len - sizeof(u16)) + return -EIO; + + /* * We write the queue's selector into the notification register * to signal the other end */ - iowrite16(vq->index, - priv->notify_base + off * priv->notify_offset_multiplier); + iowrite16(vq->index, priv->notify_base + off); return 0; } @@ -379,28 +397,51 @@ static int virtio_pci_notify(struct udevice *udev, struct virtqueue *vq) * * @udev: the transport device * @cfg_type: the VIRTIO_PCI_CAP_* value we seek + * @cap_size: expected size of the capability + * @cap: capability read from the config space * * Return: offset of the configuration structure */ -static int virtio_pci_find_capability(struct udevice *udev, u8 cfg_type) +static int virtio_pci_find_capability(struct udevice *udev, u8 cfg_type, + size_t cap_size, + struct virtio_pci_cap *cap) { int pos; int offset; - u8 type, bar; + + assert(cap_size >= sizeof(struct virtio_pci_cap)); + assert(cap_size <= PCI_CFG_SPACE_SIZE); + + if (!cap) + return 0; for (pos = dm_pci_find_capability(udev, PCI_CAP_ID_VNDR); pos > 0; pos = dm_pci_find_next_capability(udev, pos, PCI_CAP_ID_VNDR)) { + /* Ensure the capability is within bounds */ + if (PCI_CFG_SPACE_SIZE - cap_size < pos) + return 0; + + offset = pos + offsetof(struct virtio_pci_cap, cap_vndr); + dm_pci_read_config8(udev, offset, &cap->cap_vndr); + offset = pos + offsetof(struct virtio_pci_cap, cap_next); + dm_pci_read_config8(udev, offset, &cap->cap_next); + offset = pos + offsetof(struct virtio_pci_cap, cap_len); + dm_pci_read_config8(udev, offset, &cap->cap_len); offset = pos + offsetof(struct virtio_pci_cap, cfg_type); - dm_pci_read_config8(udev, offset, &type); + dm_pci_read_config8(udev, offset, &cap->cfg_type); offset = pos + offsetof(struct virtio_pci_cap, bar); - dm_pci_read_config8(udev, offset, &bar); + dm_pci_read_config8(udev, offset, &cap->bar); + offset = pos + offsetof(struct virtio_pci_cap, offset); + dm_pci_read_config32(udev, offset, &cap->offset); + offset = pos + offsetof(struct virtio_pci_cap, length); + dm_pci_read_config32(udev, offset, &cap->length); /* Ignore structures with reserved BAR values */ - if (bar > 0x5) + if (cap->bar > 0x5) continue; - if (type == cfg_type) + if (cap->cfg_type == cfg_type) return pos; } @@ -411,35 +452,24 @@ static int virtio_pci_find_capability(struct udevice *udev, u8 cfg_type) * virtio_pci_map_capability - map base address of the capability * * @udev: the transport device - * @off: offset of the configuration structure + * @cap: capability to map * * Return: base address of the capability */ -static void __iomem *virtio_pci_map_capability(struct udevice *udev, int off) +static void __iomem *virtio_pci_map_capability(struct udevice *udev, + const struct virtio_pci_cap *cap) { - u8 bar; - u32 offset; - ulong base; - void __iomem *p; - - if (!off) - return NULL; - - offset = off + offsetof(struct virtio_pci_cap, bar); - dm_pci_read_config8(udev, offset, &bar); - offset = off + offsetof(struct virtio_pci_cap, offset); - dm_pci_read_config32(udev, offset, &offset); - /* - * TODO: adding 64-bit BAR support - * - * Per spec, the BAR is permitted to be either 32-bit or 64-bit. - * For simplicity, only read the BAR address as 32-bit. + * Find the corresponding memory region that isn't system memory but is + * writable. */ - base = dm_pci_read_bar32(udev, bar); - p = (void __iomem *)base + offset; + unsigned long mask = + PCI_REGION_TYPE | PCI_REGION_SYS_MEMORY | PCI_REGION_RO; + unsigned long flags = PCI_REGION_MEM; + u8 *p = dm_pci_map_bar(udev, PCI_BASE_ADDRESS_0 + cap->bar, cap->offset, + cap->length, mask, flags); - return p; + return (void __iomem *)p; } static int virtio_pci_bind(struct udevice *udev) @@ -462,6 +492,7 @@ static int virtio_pci_probe(struct udevice *udev) u16 subvendor; u8 revision; int common, notify, device; + struct virtio_pci_cap common_cap, notify_cap, device_cap; int offset; /* We only own devices >= 0x1040 and <= 0x107f: leave the rest. */ @@ -477,34 +508,60 @@ static int virtio_pci_probe(struct udevice *udev) uc_priv->vendor = subvendor; /* Check for a common config: if not, use legacy mode (bar 0) */ - common = virtio_pci_find_capability(udev, VIRTIO_PCI_CAP_COMMON_CFG); + common = virtio_pci_find_capability(udev, VIRTIO_PCI_CAP_COMMON_CFG, + sizeof(struct virtio_pci_cap), + &common_cap); if (!common) { printf("(%s): leaving for legacy driver\n", udev->name); return -ENODEV; } + if (common_cap.length < sizeof(struct virtio_pci_common_cfg)) { + printf("(%s): virtio common config too small\n", udev->name); + return -EINVAL; + } + /* If common is there, notify should be too */ - notify = virtio_pci_find_capability(udev, VIRTIO_PCI_CAP_NOTIFY_CFG); + notify = virtio_pci_find_capability(udev, VIRTIO_PCI_CAP_NOTIFY_CFG, + sizeof(struct virtio_pci_notify_cap), + ¬ify_cap); if (!notify) { printf("(%s): missing capabilities %i/%i\n", udev->name, common, notify); return -EINVAL; } + /* Map configuration structures */ + priv->common = virtio_pci_map_capability(udev, &common_cap); + if (!priv->common) { + printf("(%s): could not map common config\n", udev->name); + return -EINVAL; + } + + priv->notify_len = notify_cap.length; + priv->notify_base = virtio_pci_map_capability(udev, ¬ify_cap); + if (!priv->notify_base) { + printf("(%s): could not map notify config\n", udev->name); + return -EINVAL; + } + /* * Device capability is only mandatory for devices that have * device-specific configuration. */ - device = virtio_pci_find_capability(udev, VIRTIO_PCI_CAP_DEVICE_CFG); + device = virtio_pci_find_capability(udev, VIRTIO_PCI_CAP_DEVICE_CFG, + sizeof(struct virtio_pci_cap), + &device_cap); if (device) { - offset = notify + offsetof(struct virtio_pci_cap, length); - dm_pci_read_config32(udev, offset, &priv->device_len); + priv->device_len = device_cap.length; + priv->device = virtio_pci_map_capability(udev, &device_cap); + if (!priv->device) { + printf("(%s): could not map device config\n", + udev->name); + return -EINVAL; + } } - /* Map configuration structures */ - priv->common = virtio_pci_map_capability(udev, common); - priv->notify_base = virtio_pci_map_capability(udev, notify); - priv->device = virtio_pci_map_capability(udev, device); debug("(%p): common @ %p, notify base @ %p, device @ %p\n", udev, priv->common, priv->notify_base, priv->device); |