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-rw-r--r--drivers/crypto/Kconfig2
-rw-r--r--drivers/crypto/Makefile1
-rw-r--r--drivers/crypto/tegra/Kconfig7
-rw-r--r--drivers/crypto/tegra/Makefile3
-rw-r--r--drivers/crypto/tegra/tegra_aes.c591
-rw-r--r--drivers/video/Kconfig24
-rw-r--r--drivers/video/Makefile3
-rw-r--r--drivers/video/bridge/Kconfig8
-rw-r--r--drivers/video/bridge/Makefile1
-rw-r--r--drivers/video/bridge/cmc623.c234
-rw-r--r--drivers/video/cmc623_backlight.c124
-rw-r--r--drivers/video/samsung-s6e63m0.c393
-rw-r--r--drivers/video/sony-l4f00430t01.c210
-rw-r--r--drivers/video/tegra/dc.c16
14 files changed, 1617 insertions, 0 deletions
diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index d26f87364f9..0d58e3910fe 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -10,4 +10,6 @@ source "drivers/crypto/aspeed/Kconfig"
source "drivers/crypto/nuvoton/Kconfig"
+source "drivers/crypto/tegra/Kconfig"
+
endmenu
diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
index 2bd99fc2763..e4a4482b7f3 100644
--- a/drivers/crypto/Makefile
+++ b/drivers/crypto/Makefile
@@ -10,3 +10,4 @@ obj-y += fsl/
obj-y += hash/
obj-y += aspeed/
obj-y += nuvoton/
+obj-y += tegra/
diff --git a/drivers/crypto/tegra/Kconfig b/drivers/crypto/tegra/Kconfig
new file mode 100644
index 00000000000..b027609307b
--- /dev/null
+++ b/drivers/crypto/tegra/Kconfig
@@ -0,0 +1,7 @@
+config TEGRA_AES
+ bool "Support the Tegra AES"
+ depends on DM_AES
+ help
+ This provides a means to encrypt and decrypt data using the Tegra
+ Bit Stream Engine for Video/Audio. Also may provide a mean to
+ encrypt/decrypt/sign using already loaded device SBK.
diff --git a/drivers/crypto/tegra/Makefile b/drivers/crypto/tegra/Makefile
new file mode 100644
index 00000000000..a118350fd11
--- /dev/null
+++ b/drivers/crypto/tegra/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-$(CONFIG_$(PHASE_)TEGRA_AES) += tegra_aes.o
diff --git a/drivers/crypto/tegra/tegra_aes.c b/drivers/crypto/tegra/tegra_aes.c
new file mode 100644
index 00000000000..7b374c757ba
--- /dev/null
+++ b/drivers/crypto/tegra/tegra_aes.c
@@ -0,0 +1,591 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Driver for NVIDIA Tegra AES hardware engine residing inside the Bit Stream Engine
+ * for Video (BSEV) hardware block and Bit Stream Engine for Audio (BSEA).
+ *
+ * The programming sequence for this engine is with the help of commands which travel
+ * via a command queue residing between the CPU and the BSEV/BSEA block.
+ *
+ * The hardware key table length is 64 bytes and each key slot divided as follows:
+ * 1. Key - 32 bytes
+ * 2. Original IV - 16 bytes
+ * 3. Updated IV - 16 bytes
+ *
+ * The engine has 4 slots in T20/T30 in which 0th contains SBK loaded by bootrom,
+ * vendor bootloaders tend to clear this slot so that anything booted after can't
+ * use the SBK. This is relevant for U-Boot's chainloaded from these vendor bootloaders.
+ *
+ * Copyright (c) 2010-2011, NVIDIA Corporation
+ * Copyright (c) 2025, Ion Agorria.
+ */
+
+#include <dm.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <time.h>
+#include <linux/delay.h>
+#include <clk.h>
+#include <reset.h>
+#include <uboot_aes.h>
+
+#include <asm/arch-tegra/crypto.h>
+#include <asm/arch-tegra/fuse.h>
+
+/* Make sure pointers will fit register size for AES engine */
+static_assert(sizeof(void *) == sizeof(u32));
+
+#define IRAM_BASE 0x40000000
+
+#define TEGRA_AES_DMA_BUFFER_SIZE (0x4000 / AES_BLOCK_LENGTH)
+#define TEGRA_AES_HW_MAX_KEY_LENGTH AES256_KEY_LENGTH
+#define TEGRA_AES_HW_TABLE_LENGTH (TEGRA_AES_HW_MAX_KEY_LENGTH + AES_BLOCK_LENGTH * 2)
+#define TEGRA_AES_IRAM_MAX_ADDR (IRAM_BASE | TEGRA_AES_KEYTABLEADDR_FIELD)
+
+#define TEGRA_AES_BUSY_TIMEOUT_MS 1000
+
+/* Registers */
+#define TEGRA_AES_ICMDQUE_WR 0x000
+#define TEGRA_AES_CMDQUE_CONTROL 0x008
+#define TEGRA_AES_INTR_STATUS 0x018
+#define TEGRA_AES_INT_ENB 0x040
+#define TEGRA_AES_BSE_CFG 0x044
+#define TEGRA_AES_IRAM_ACCESS_CFG 0x0a0
+#define TEGRA_AES_SECURE_DEST_ADDR 0x100
+#define TEGRA_AES_SECURE_INPUT_SELECT 0x104
+#define TEGRA_AES_SECURE_CONFIG 0x108
+#define TEGRA_AES_SECURE_CONFIG_EXT 0x10c
+
+/* Register field macros */
+#define TEGRA_AES_ENGINE_BUSY_FIELD BIT(0)
+#define TEGRA_AES_ICQ_EMPTY_FIELD BIT(3)
+#define TEGRA_AES_DMA_BUSY_FIELD BIT(23)
+#define TEGRA_AES_SECURE_KEY_SCH_DIS_FIELD BIT(15)
+#define TEGRA_AES_KEYTABLEADDR_FIELD (BIT(17) - 1)
+#define TEGRA_AES_SECURE_KEY_INDEX_SHIFT 20
+#define TEGRA_AES_SECURE_KEY_INDEX_FIELD (0x1f << TEGRA_AES_SECURE_KEY_INDEX_SHIFT)
+#define TEGRA_AES_SECURE_CTR_CNT_SHIFT 16
+#define TEGRA_AES_SECURE_CTR_CNT_FIELD (0xffff << TEGRA_AES_SECURE_CTR_CNT_SHIFT)
+#define TEGRA_AES_BSE_MODE_FIELD 0x1f
+#define TEGRA_AES_BSE_LITTLE_ENDIAN_FIELD BIT(10)
+#define TEGRA_AES_CMDQ_OPCODE_SHIFT 26
+#define TEGRA_AES_CMDQ_CTRL_ICMDQEN_FIELD BIT(1)
+#define TEGRA_AES_CMDQ_CTRL_SRC_STM_SEL_FIELD BIT(4)
+#define TEGRA_AES_CMDQ_CTRL_DST_STM_SEL_FIELD BIT(5)
+#define TEGRA_AES_SECURE_INPUT_ALG_SEL_SHIFT 28
+#define TEGRA_AES_SECURE_INPUT_KEY_LEN_SHIFT 16
+#define TEGRA_AES_SECURE_INPUT_IV_FIELD BIT(10)
+#define TEGRA_AES_SECURE_INPUT_HASH_ENB_FIELD BIT(2)
+#define TEGRA_AES_SECURE_CORE_SEL_SHIFT 9
+#define TEGRA_AES_SECURE_VCTRAM_SEL_SHIFT 7
+#define TEGRA_AES_SECURE_XOR_POS_SHIFT 3
+#define TEGRA_AES_INT_ERROR_MASK 0x6ff000
+
+/* Commands for BSEV/BSEA */
+#define TEGRA_AES_CMD_BLKSTARTENGINE 0x0e
+#define TEGRA_AES_CMD_DMASETUP 0x10
+#define TEGRA_AES_CMD_DMACOMPLETE 0x11
+#define TEGRA_AES_CMD_SETTABLE 0x15
+
+/* Flags for mode */
+#define TEGRA_AES_MODE_ENCRYPT BIT(0)
+#define TEGRA_AES_MODE_CBC BIT(1)
+#define TEGRA_AES_MODE_UPDATE_IV BIT(2)
+#define TEGRA_AES_MODE_HASH BIT(3)
+
+struct tegra_aes_priv {
+ void *regs;
+ void *iram_addr;
+
+ struct reset_ctl reset_ctl;
+ struct reset_ctl reset_ctl_vde;
+
+ struct clk *clk;
+ struct clk *clk_parent;
+
+ u8 current_key_size;
+ bool sbk_available;
+};
+
+static bool tegra_aes_is_busy(struct tegra_aes_priv *priv, bool dma_wait)
+{
+ u32 value = readl(priv->regs + TEGRA_AES_INTR_STATUS);
+ bool engine_busy = value & TEGRA_AES_ENGINE_BUSY_FIELD;
+ bool non_empty_queue = !(value & TEGRA_AES_ICQ_EMPTY_FIELD);
+ bool dma_busy = dma_wait && (value & TEGRA_AES_DMA_BUSY_FIELD);
+
+ log_debug("%s - e:%d q:%d dma:%d\n", __func__, engine_busy, non_empty_queue, dma_busy);
+
+ return engine_busy || non_empty_queue || dma_busy;
+}
+
+static u32 tegra_aes_check_error(struct tegra_aes_priv *priv)
+{
+ u32 value = readl(priv->regs + TEGRA_AES_INTR_STATUS) & TEGRA_AES_INT_ERROR_MASK;
+
+ if (value) {
+ writel(TEGRA_AES_INT_ERROR_MASK, priv->regs + TEGRA_AES_INTR_STATUS);
+ log_debug("%s 0x%x\n", __func__, value);
+ }
+
+ return value;
+}
+
+static int tegra_aes_wait_for_idle_dma(struct tegra_aes_priv *priv, bool dma_wait)
+{
+ ulong start = get_timer(0);
+
+ while (tegra_aes_is_busy(priv, dma_wait)) {
+ if (get_timer(start) > TEGRA_AES_BUSY_TIMEOUT_MS) {
+ log_err("%s: TIMEOUT!!!\n", __func__);
+ break;
+ }
+ mdelay(5);
+ }
+
+ if (tegra_aes_check_error(priv))
+ return -1;
+
+ return 0;
+}
+
+static int tegra_aes_wait_for_idle(struct tegra_aes_priv *priv)
+{
+ return tegra_aes_wait_for_idle_dma(priv, 1);
+}
+
+static int tegra_aes_configure(struct tegra_aes_priv *priv)
+{
+ u32 value;
+
+ if (tegra_aes_wait_for_idle(priv))
+ return -1;
+
+ /* IRAM config */
+ writel(0, priv->regs + TEGRA_AES_IRAM_ACCESS_CFG);
+
+ /* Reset interrupts bits, or engine will hang on next operation */
+ writel(0xFFFFFFFF, priv->regs + TEGRA_AES_INTR_STATUS);
+
+ /* Set interrupts */
+ writel(0, priv->regs + TEGRA_AES_INT_ENB);
+
+ /* Configure CMDQUE */
+ value = readl(priv->regs + TEGRA_AES_CMDQUE_CONTROL);
+ value |= TEGRA_AES_CMDQ_CTRL_SRC_STM_SEL_FIELD |
+ TEGRA_AES_CMDQ_CTRL_DST_STM_SEL_FIELD |
+ TEGRA_AES_CMDQ_CTRL_ICMDQEN_FIELD;
+ writel(value, priv->regs + TEGRA_AES_CMDQUE_CONTROL);
+
+ value = readl(priv->regs + TEGRA_AES_SECURE_CONFIG_EXT);
+ value &= ~TEGRA_AES_SECURE_CTR_CNT_FIELD;
+ writel(value, priv->regs + TEGRA_AES_SECURE_CONFIG_EXT);
+
+ /* Configure BSE */
+ value = readl(priv->regs + TEGRA_AES_BSE_CFG);
+ value &= ~TEGRA_AES_BSE_MODE_FIELD;
+ value |= TEGRA_AES_BSE_LITTLE_ENDIAN_FIELD;
+ writel(value, priv->regs + TEGRA_AES_BSE_CFG);
+
+ return 0;
+}
+
+static int tegra_aes_select_key_slot(struct tegra_aes_priv *priv, u32 key_size, u8 slot)
+{
+ if (tegra_aes_wait_for_idle(priv))
+ return -1;
+
+ if (key_size < (AES128_KEY_LENGTH * 8) ||
+ key_size > (TEGRA_AES_HW_MAX_KEY_LENGTH * 8))
+ return -EINVAL;
+
+ priv->current_key_size = key_size;
+
+ /* Select the key slot */
+ u32 value = readl(priv->regs + TEGRA_AES_SECURE_CONFIG);
+
+ value &= ~TEGRA_AES_SECURE_KEY_INDEX_FIELD;
+ value |= (slot << TEGRA_AES_SECURE_KEY_INDEX_SHIFT);
+ writel(value, priv->regs + TEGRA_AES_SECURE_CONFIG);
+
+ return 0;
+}
+
+static int tegra_aes_call_engine(struct tegra_aes_priv *priv, u8 *src, u8 *dst,
+ u32 nblocks, u32 mode)
+{
+ u32 value;
+ const u32 ICMDQ_LENGTH = 4;
+ u32 cmdq[ICMDQ_LENGTH];
+
+ log_debug("%s: 0x%p -> 0x%p blocks %d mode 0x%x\n", __func__,
+ src, dst, nblocks, mode);
+
+ if (!nblocks) {
+ log_warning("%s: called with 0 blocks!\n", __func__);
+ return -1;
+ }
+
+ if (tegra_aes_configure(priv))
+ return -1;
+
+ /* Configure Secure Input */
+ value = 1 << TEGRA_AES_SECURE_INPUT_ALG_SEL_SHIFT |
+ priv->current_key_size << TEGRA_AES_SECURE_INPUT_KEY_LEN_SHIFT;
+
+ if (mode & TEGRA_AES_MODE_UPDATE_IV)
+ value |= TEGRA_AES_SECURE_INPUT_IV_FIELD;
+ if (mode & TEGRA_AES_MODE_HASH)
+ value |= TEGRA_AES_SECURE_INPUT_HASH_ENB_FIELD;
+ if (mode & TEGRA_AES_MODE_CBC) {
+ value |= ((mode & TEGRA_AES_MODE_ENCRYPT) ? 2 : 3) <<
+ TEGRA_AES_SECURE_XOR_POS_SHIFT;
+ value |= ((mode & TEGRA_AES_MODE_ENCRYPT) ? 2 : 3) <<
+ TEGRA_AES_SECURE_VCTRAM_SEL_SHIFT;
+ value |= ((mode & TEGRA_AES_MODE_ENCRYPT) ? 1 : 0) <<
+ TEGRA_AES_SECURE_CORE_SEL_SHIFT;
+ } else {
+ /* ECB */
+ value |= ((mode & TEGRA_AES_MODE_ENCRYPT) ? 1 : 0) <<
+ TEGRA_AES_SECURE_CORE_SEL_SHIFT;
+ }
+
+ writel(value, priv->regs + TEGRA_AES_SECURE_INPUT_SELECT);
+
+ /* Set destination address (doing in-place at IRAM) */
+ writel((u32)priv->iram_addr, priv->regs + TEGRA_AES_SECURE_DEST_ADDR);
+
+ /* Copy src data to IRAM */
+ if (src != priv->iram_addr)
+ memcpy(priv->iram_addr, src, nblocks * AES_BLOCK_LENGTH);
+
+ /* Run ICMD commands */
+ cmdq[0] = TEGRA_AES_CMD_DMASETUP << TEGRA_AES_CMDQ_OPCODE_SHIFT;
+ cmdq[1] = (u32)priv->iram_addr;
+ cmdq[2] = TEGRA_AES_CMD_BLKSTARTENGINE << TEGRA_AES_CMDQ_OPCODE_SHIFT | (nblocks - 1);
+ cmdq[3] = TEGRA_AES_CMD_DMACOMPLETE << TEGRA_AES_CMDQ_OPCODE_SHIFT;
+
+ for (int i = 0; i < ICMDQ_LENGTH; i++) {
+ tegra_aes_wait_for_idle_dma(priv, (ICMDQ_LENGTH - 1) == i);
+ writel(cmdq[i], priv->regs + TEGRA_AES_ICMDQUE_WR);
+ }
+
+ if (tegra_aes_wait_for_idle(priv))
+ return -1;
+
+ /* Put the result from IRAM to destination if not hashing */
+ if (dst != priv->iram_addr && !(mode & TEGRA_AES_MODE_HASH))
+ memcpy(dst, priv->iram_addr, nblocks * AES_BLOCK_LENGTH);
+
+ return 0;
+}
+
+static int tegra_aes_process_blocks(struct udevice *dev, u8 *iv, u8 *src,
+ u8 *dst, u32 num_aes_blocks, u32 mode)
+{
+ struct tegra_aes_priv *priv = dev_get_priv(dev);
+
+ log_debug("%s: 0x%p -> 0x%p blocks %d mode 0x%x\n",
+ __func__, src, dst, num_aes_blocks, mode);
+
+ if (!num_aes_blocks) {
+ log_warning("%s: called with 0 blocks!\n", __func__);
+ return -1;
+ }
+
+ /* Load initial IV if CBC mode */
+ if (mode & TEGRA_AES_MODE_CBC) {
+ if (tegra_aes_call_engine(priv, iv, priv->iram_addr, 1, TEGRA_AES_MODE_CBC))
+ return -1;
+
+ /* Add update IV flag */
+ mode |= TEGRA_AES_MODE_UPDATE_IV;
+ }
+
+ /* Process blocks by calling engine several times per dma buffer size */
+ while (num_aes_blocks > 0) {
+ u32 blocks = min(num_aes_blocks, (u32)TEGRA_AES_DMA_BUFFER_SIZE);
+
+ if (tegra_aes_call_engine(priv, src, dst, blocks, mode))
+ return -1;
+
+ num_aes_blocks -= blocks;
+ src += blocks * AES_BLOCK_LENGTH;
+ dst += blocks * AES_BLOCK_LENGTH;
+ }
+
+ return 0;
+}
+
+static int tegra_aes_ops_available_key_slots(struct udevice *dev)
+{
+ return 4; /* 4 slots in Tegra20 and Tegra30 */
+}
+
+static int tegra_aes_ops_select_key_slot(struct udevice *dev, u32 key_size, u8 slot)
+{
+ struct tegra_aes_priv *priv = dev_get_priv(dev);
+
+ if (slot == TEGRA_AES_SLOT_SBK && !priv->sbk_available) {
+ log_warning("%s: SBK not available!\n", __func__);
+ return -1;
+ }
+
+ return tegra_aes_select_key_slot(priv, key_size, slot);
+}
+
+static int tegra_aes_ops_set_key_for_key_slot(struct udevice *dev, u32 key_size,
+ u8 *key, u8 slot)
+{
+ struct tegra_aes_priv *priv = dev_get_priv(dev);
+ const u8 SUBCMD_CRYPTO_TABLE_SEL = 0x3;
+ const u8 SUBCMD_KEY_TABLE_SEL = 0x8;
+ const u8 CMDQ_KEYTABLEADDR_SHIFT = 0;
+ const u8 CMDQ_KEYTABLEID_SHIFT = 17;
+ const u8 CMDQ_TABLESEL_SHIFT = 24;
+ u32 value, addr;
+
+ log_debug("%s: slot %d\n", __func__, slot);
+
+ if (tegra_aes_configure(priv))
+ return -1;
+
+ if (key_size < (AES128_KEY_LENGTH * 8) ||
+ key_size > (TEGRA_AES_HW_MAX_KEY_LENGTH * 8))
+ return -EINVAL;
+
+ if (slot == TEGRA_AES_SLOT_SBK)
+ log_debug("%s: SBK slot being set!\n", __func__);
+
+ /* Clear and copy data to IRAM */
+ memset(priv->iram_addr, 0, TEGRA_AES_HW_TABLE_LENGTH);
+ memcpy(priv->iram_addr, key, key_size / 8);
+
+ /* Mask the addr */
+ addr = ((u32)priv->iram_addr) & TEGRA_AES_KEYTABLEADDR_FIELD;
+
+ /* Command for engine to load AES key from IRAM */
+ value = TEGRA_AES_CMD_SETTABLE << TEGRA_AES_CMDQ_OPCODE_SHIFT |
+ SUBCMD_CRYPTO_TABLE_SEL << CMDQ_TABLESEL_SHIFT |
+ (SUBCMD_KEY_TABLE_SEL | slot) << CMDQ_KEYTABLEID_SHIFT |
+ addr << CMDQ_KEYTABLEADDR_SHIFT;
+ writel(value, priv->regs + TEGRA_AES_ICMDQUE_WR);
+
+ return tegra_aes_wait_for_idle(priv);
+}
+
+static int tegra_aes_ops_aes_ecb_encrypt(struct udevice *dev, u8 *src, u8 *dst,
+ u32 num_aes_blocks)
+{
+ return tegra_aes_process_blocks(dev, NULL, src, dst, num_aes_blocks,
+ TEGRA_AES_MODE_ENCRYPT);
+}
+
+static int tegra_aes_ops_aes_ecb_decrypt(struct udevice *dev, u8 *src, u8 *dst,
+ u32 num_aes_blocks)
+{
+ return tegra_aes_process_blocks(dev, NULL, src, dst, num_aes_blocks, 0);
+}
+
+static int tegra_aes_ops_aes_cbc_encrypt(struct udevice *dev, u8 *iv, u8 *src,
+ u8 *dst, u32 num_aes_blocks)
+{
+ return tegra_aes_process_blocks(dev, iv, src, dst, num_aes_blocks,
+ TEGRA_AES_MODE_CBC | TEGRA_AES_MODE_ENCRYPT);
+}
+
+static int tegra_aes_ops_aes_cbc_decrypt(struct udevice *dev, u8 *iv, u8 *src,
+ u8 *dst, u32 num_aes_blocks)
+{
+ return tegra_aes_process_blocks(dev, iv, src, dst, num_aes_blocks,
+ TEGRA_AES_MODE_CBC);
+}
+
+static void tegra_aes_test_loaded_sbk(struct udevice *dev)
+{
+ struct tegra_aes_priv *priv = dev_get_priv(dev);
+ enum fuse_operating_mode opmode = tegra_fuse_get_operation_mode();
+ const u8 ZERO_KEY_CIPHERTEXT[AES_BLOCK_LENGTH] = {
+ 0x66, 0xe9, 0x4b, 0xd4, 0xef, 0x8a, 0x2c, 0x3b,
+ 0x88, 0x4c, 0xfa, 0x59, 0xca, 0x34, 0x2b, 0x2e
+ };
+
+ /* Encrypt a zero block, we use ECB so that we only care about SBK and not the IV */
+ memset(priv->iram_addr, 0, AES_BLOCK_LENGTH);
+ tegra_aes_select_key_slot(priv, 128, TEGRA_AES_SLOT_SBK);
+ tegra_aes_call_engine(priv, priv->iram_addr, priv->iram_addr, 1, TEGRA_AES_MODE_ENCRYPT);
+
+ /* Evaluate the result of engine operation */
+ if (!memcmp(priv->iram_addr, AES_ZERO_BLOCK, AES_BLOCK_LENGTH)) {
+ log_err("%s: engine is not operational! (opmode 0x%x)\n", __func__, opmode);
+ } else if (!memcmp(priv->iram_addr, ZERO_KEY_CIPHERTEXT, AES_BLOCK_LENGTH)) {
+ if (opmode == MODE_ODM_PRODUCTION_SECURE) {
+ log_warning("%s: SBK is zero or is cleared from engine! (opmode 0x%x)\n",
+ __func__, opmode);
+ } else {
+ log_debug("%s - SBK is zero and available! (opmode 0x%x)\n",
+ __func__, opmode);
+ priv->sbk_available = true;
+ }
+ } else {
+ if (opmode == MODE_ODM_PRODUCTION_SECURE) {
+ log_debug("%s: SBK is available! (opmode 0x%x)\n", __func__, opmode);
+ priv->sbk_available = true;
+ } else {
+ log_warning("%s: SBK is not zero and should be! (opmode 0x%x)\n",
+ __func__, opmode);
+ }
+ }
+}
+
+static int tegra_aes_hw_init(struct udevice *dev)
+{
+ struct tegra_aes_priv *priv = dev_get_priv(dev);
+ u32 value;
+ int ret;
+
+ if (priv->clk_parent) {
+ ret = reset_assert(&priv->reset_ctl_vde);
+ if (ret) {
+ log_debug("%s: VDE reset assert failed: %d\n", __func__, ret);
+ return ret;
+ }
+ }
+
+ ret = reset_assert(&priv->reset_ctl);
+ if (ret) {
+ log_debug("%s: BSE reset assert failed: %d\n", __func__, ret);
+ return ret;
+ }
+
+ if (priv->clk_parent) {
+ ret = clk_enable(priv->clk_parent);
+ if (ret) {
+ log_err("%s: VDE clock enable failed: %d\n", __func__, ret);
+ return ret;
+ }
+
+ ret = clk_set_rate(priv->clk_parent, 50 * 1000000);
+ if (IS_ERR_VALUE(ret)) {
+ log_err("%s: VDE clock set rate failed: %d\n", __func__, ret);
+ return ret;
+ }
+ }
+
+ ret = clk_enable(priv->clk);
+ if (ret) {
+ log_err("%s: BSE clock enable failed: %d\n", __func__, ret);
+ return ret;
+ }
+
+ if (priv->clk_parent) {
+ ret = reset_deassert(&priv->reset_ctl_vde);
+ if (ret) {
+ log_err("%s: VDE reset deassert failed: %d\n", __func__, ret);
+ return ret;
+ }
+ }
+
+ ret = reset_deassert(&priv->reset_ctl);
+ if (ret) {
+ log_err("%s: BSE reset deassert failed: %d\n", __func__, ret);
+ return ret;
+ }
+
+ /* Enable key schedule generation in hardware */
+ value = readl(priv->regs + TEGRA_AES_SECURE_CONFIG_EXT);
+ value &= ~TEGRA_AES_SECURE_KEY_SCH_DIS_FIELD;
+ writel(value, priv->regs + TEGRA_AES_SECURE_CONFIG_EXT);
+
+ /* Check if SBK is loaded in SBK slot or was erased */
+ priv->sbk_available = false;
+ tegra_aes_test_loaded_sbk(dev);
+
+ return 0;
+}
+
+static int tegra_aes_probe(struct udevice *dev)
+{
+ struct tegra_aes_priv *priv = dev_get_priv(dev);
+ fdt_size_t iram_size = 0;
+ u32 value;
+ int ret;
+
+ priv->current_key_size = AES128_KEY_LENGTH;
+
+ priv->regs = dev_read_addr_ptr(dev);
+ if (!priv->regs) {
+ log_err("%s: Cannot find aes reg address, binding failed\n", __func__);
+ return -EINVAL;
+ }
+
+ priv->iram_addr = devfdt_get_addr_size_name_ptr(dev, "iram-buffer", &iram_size);
+ if (!priv->iram_addr) {
+ log_debug("%s: Cannot find iram buffer address, binding failed\n", __func__);
+ return -EINVAL;
+ }
+
+ if (iram_size < TEGRA_AES_DMA_BUFFER_SIZE * AES_BLOCK_LENGTH) {
+ log_debug("%s: Unsupported iram buffer size: 0x%x required: 0x%x\n",
+ __func__, iram_size, TEGRA_AES_DMA_BUFFER_SIZE);
+ return -EINVAL;
+ }
+
+ /* Make sure the IRAM address is kept block aligned and accessible for slot loading */
+ value = (uint32_t)priv->iram_addr;
+ if ((value & 0xFFF0000F) != IRAM_BASE || value > TEGRA_AES_IRAM_MAX_ADDR) {
+ log_debug("%s: iram buffer must be located inside iram,", __func__);
+ log_debug("AES block aligned and not above 0x%08x, current addr %p\n",
+ (u32)TEGRA_AES_IRAM_MAX_ADDR, priv->iram_addr);
+ return -EINVAL;
+ }
+
+ ret = reset_get_by_name(dev, NULL, &priv->reset_ctl);
+ if (ret) {
+ log_debug("%s: failed to get BSE reset: %d\n", __func__, ret);
+ return ret;
+ }
+
+ priv->clk = devm_clk_get(dev, NULL);
+ if (IS_ERR(priv->clk)) {
+ log_err("%s: failed to get BSE clock: %d\n", __func__, ret);
+ return ret;
+ }
+
+ /* VDE clock and reset required by BSEV */
+ ret = reset_get_by_name(dev, "vde", &priv->reset_ctl_vde);
+ if (ret)
+ log_debug("%s: failed to get VDE reset: %d\n", __func__, ret);
+
+ priv->clk_parent = devm_clk_get(dev, "vde");
+ if (IS_ERR(priv->clk_parent))
+ log_debug("%s: failed to get BSE clock: %d\n", __func__, ret);
+
+ return tegra_aes_hw_init(dev);
+}
+
+static const struct aes_ops tegra_aes_ops = {
+ .available_key_slots = tegra_aes_ops_available_key_slots,
+ .select_key_slot = tegra_aes_ops_select_key_slot,
+ .set_key_for_key_slot = tegra_aes_ops_set_key_for_key_slot,
+ .aes_ecb_encrypt = tegra_aes_ops_aes_ecb_encrypt,
+ .aes_ecb_decrypt = tegra_aes_ops_aes_ecb_decrypt,
+ .aes_cbc_encrypt = tegra_aes_ops_aes_cbc_encrypt,
+ .aes_cbc_decrypt = tegra_aes_ops_aes_cbc_decrypt,
+};
+
+static const struct udevice_id tegra_aes_ids[] = {
+ { .compatible = "nvidia,tegra20-bsea" },
+ { .compatible = "nvidia,tegra20-bsev" },
+ { .compatible = "nvidia,tegra30-bsea" },
+ { .compatible = "nvidia,tegra30-bsev" },
+ { }
+};
+
+U_BOOT_DRIVER(tegra_aes) = {
+ .name = "tegra_aes",
+ .id = UCLASS_AES,
+ .of_match = tegra_aes_ids,
+ .probe = tegra_aes_probe,
+ .ops = &tegra_aes_ops,
+ .priv_auto = sizeof(struct tegra_aes_priv),
+};
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index dfe4b3b8a02..b5777da5218 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -691,6 +691,23 @@ config VIDEO_LCD_HITACHI_TX18D42VM
lcd controller which needs to be initialized over SPI, once that is
done they work like a regular LVDS panel.
+config VIDEO_LCD_SONY_L4F00430T01
+ tristate "Sony L4F00430T01 480x800 LCD panel support"
+ depends on PANEL
+ help
+ Say Y here if you want to enable support for Sony L4F00430T01
+ LCD module found in Samsung Galaxy R. The panel has a
+ WVGA resolution (480x800) and is setup over SPI, video
+ data comes from RGB.
+
+config VIDEO_LCD_SAMSUNG_S6E63M0
+ tristate "Samsung S6E63M0 controller based panel support"
+ depends on PANEL && BACKLIGHT
+ help
+ Say Y here if you want to enable support for Samsung S6E63M0
+ controller found in some panels like on Samsung Captivate Glide.
+ Currently only DBI C panel is implemented.
+
config VIDEO_LCD_SPI_CS
string "SPI CS pin for LCD related config job"
depends on VIDEO_LCD_SSD2828 || VIDEO_LCD_HITACHI_TX18D42VM
@@ -821,6 +838,13 @@ config BACKLIGHT_LP855x
supported for now, PWM mode can be added if there will be any need in
it. Supported backlight level range is from 0 to 255 with step of 1.
+config BACKLIGHT_SAMSUNG_CMC623
+ bool "Backlight Driver for Samsung CMC623"
+ depends on VIDEO_BRIDGE_SAMSUNG_CMC623
+ help
+ Say Y to enable the backlight driver for Samsung CMC623 image converter
+ chip's PWM output to control backlight brightness.
+
source "drivers/video/ti/Kconfig"
source "drivers/video/exynos/Kconfig"
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index ebe4a3961fc..96c7ce7bb09 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -33,6 +33,7 @@ obj-$(CONFIG_BACKLIGHT_AAT2870) += aat2870_backlight.o
obj-$(CONFIG_BACKLIGHT_LM3532) += lm3532_backlight.o
obj-$(CONFIG_BACKLIGHT_LM3533) += lm3533_backlight.o
obj-$(CONFIG_BACKLIGHT_LP855x) += lp855x_backlight.o
+obj-$(CONFIG_BACKLIGHT_SAMSUNG_CMC623) += cmc623_backlight.o
obj-${CONFIG_EXYNOS_FB} += exynos/
obj-${CONFIG_VIDEO_ROCKCHIP} += rockchip/
obj-${CONFIG_VIDEO_STM32} += stm32/
@@ -74,6 +75,8 @@ obj-$(CONFIG_VIDEO_LCD_SHARP_LQ079L1SX01) += sharp-lq079l1sx01.o
obj-$(CONFIG_VIDEO_LCD_SHARP_LQ101R1SX01) += sharp-lq101r1sx01.o
obj-$(CONFIG_VIDEO_LCD_SSD2828) += ssd2828.o
obj-$(CONFIG_VIDEO_LCD_TDO_TL070WSH30) += tdo-tl070wsh30.o
+obj-$(CONFIG_VIDEO_LCD_SONY_L4F00430T01) += sony-l4f00430t01.o
+obj-$(CONFIG_VIDEO_LCD_SAMSUNG_S6E63M0) += samsung-s6e63m0.o
obj-$(CONFIG_VIDEO_MCDE_SIMPLE) += mcde_simple.o
obj-${CONFIG_VIDEO_MESON} += meson/
obj-${CONFIG_VIDEO_MIPI_DSI} += mipi_dsi.o
diff --git a/drivers/video/bridge/Kconfig b/drivers/video/bridge/Kconfig
index be53034bd3d..a48cec7a138 100644
--- a/drivers/video/bridge/Kconfig
+++ b/drivers/video/bridge/Kconfig
@@ -66,3 +66,11 @@ config VIDEO_BRIDGE_LVDS_CODEC
help
Support for transparent LVDS encoders and decoders that don't
require any configuration.
+
+config VIDEO_BRIDGE_SAMSUNG_CMC623
+ bool "Samsung CMC623 Image Converter driver"
+ depends on VIDEO_BRIDGE && DM_GPIO
+ select DM_I2C
+ help
+ Samsung CMC623 image converter chip driver.
+ Found in several Samsung devices such as N1
diff --git a/drivers/video/bridge/Makefile b/drivers/video/bridge/Makefile
index 63dc6e62c49..520f36a7a6f 100644
--- a/drivers/video/bridge/Makefile
+++ b/drivers/video/bridge/Makefile
@@ -11,3 +11,4 @@ obj-$(CONFIG_VIDEO_BRIDGE_ANALOGIX_ANX6345) += anx6345.o
obj-$(CONFIG_VIDEO_BRIDGE_SOLOMON_SSD2825) += ssd2825.o
obj-$(CONFIG_VIDEO_BRIDGE_TOSHIBA_TC358768) += tc358768.o
obj-$(CONFIG_VIDEO_BRIDGE_LVDS_CODEC) += lvds-codec.o
+obj-$(CONFIG_VIDEO_BRIDGE_SAMSUNG_CMC623) += cmc623.o
diff --git a/drivers/video/bridge/cmc623.c b/drivers/video/bridge/cmc623.c
new file mode 100644
index 00000000000..78dafef8145
--- /dev/null
+++ b/drivers/video/bridge/cmc623.c
@@ -0,0 +1,234 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2025 Ion Agorria <ion@agorria.com>
+ */
+
+#include <clk.h>
+#include <dm.h>
+#include <dm/ofnode_graph.h>
+#include <i2c.h>
+#include <log.h>
+#include <backlight.h>
+#include <panel.h>
+#include <video_bridge.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/kernel.h>
+#include <linux/math64.h>
+#include <power/regulator.h>
+#include <asm/gpio.h>
+
+static const char * const cmc623_supplies[] = {
+ "vdd3v0-supply", "vdd1v2-supply", "vddio1v8-supply"
+};
+
+struct cmc623_priv {
+ struct udevice *panel;
+ struct display_timing timing;
+
+ struct udevice *supplies[ARRAY_SIZE(cmc623_supplies)];
+
+ struct gpio_desc enable_gpio; /* also known as FAILSAFE */
+ struct gpio_desc bypass_gpio;
+};
+
+static int cmc623_attach(struct udevice *dev)
+{
+ struct cmc623_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ /* Perform panel setup */
+ ret = panel_enable_backlight(priv->panel);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int cmc623_set_backlight(struct udevice *dev, int percent)
+{
+ struct cmc623_priv *priv = dev_get_priv(dev);
+
+ return panel_set_backlight(priv->panel, percent);
+}
+
+static int cmc623_panel_timings(struct udevice *dev, struct display_timing *timing)
+{
+ struct cmc623_priv *priv = dev_get_priv(dev);
+
+ memcpy(timing, &priv->timing, sizeof(*timing));
+
+ return 0;
+}
+
+static int cmc623_hw_init(struct udevice *dev)
+{
+ struct cmc623_priv *priv = dev_get_priv(dev);
+ struct video_bridge_priv *uc_priv = dev_get_uclass_priv(dev);
+ int i, ret;
+
+ /* enable supplies */
+ for (i = 0; i < ARRAY_SIZE(cmc623_supplies); i++) {
+ ret = regulator_set_enable_if_allowed(priv->supplies[i], 1);
+ if (ret) {
+ log_debug("%s: cannot enable %s %d\n", __func__,
+ cmc623_supplies[i], ret);
+ return ret;
+ }
+ }
+
+ mdelay(10);
+
+ ret = dm_gpio_set_value(&uc_priv->reset, 1);
+ if (ret) {
+ log_debug("%s: error at reset = 1 (%d)\n", __func__, ret);
+ return ret;
+ }
+
+ ret = dm_gpio_set_value(&priv->enable_gpio, 0);
+ if (ret) {
+ log_debug("%s: error at enable = 0 (%d)\n", __func__, ret);
+ return ret;
+ }
+
+ ret = dm_gpio_set_value(&priv->bypass_gpio, 0);
+ if (ret) {
+ log_debug("%s: error at bypass = 0 (%d)\n", __func__, ret);
+ return ret;
+ }
+
+ ret = dm_gpio_set_value(&uc_priv->sleep, 0);
+ if (ret) {
+ log_debug("%s: error at sleep = 0 (%d)\n", __func__, ret);
+ return ret;
+ }
+
+ udelay(2000);
+
+ ret = dm_gpio_set_value(&priv->enable_gpio, 1);
+ if (ret) {
+ log_debug("%s: error at enable = 1 (%d)\n", __func__, ret);
+ return ret;
+ }
+
+ udelay(2000);
+
+ ret = dm_gpio_set_value(&priv->bypass_gpio, 1);
+ if (ret) {
+ log_debug("%s: error at bypass = 1 (%d)\n", __func__, ret);
+ return ret;
+ }
+
+ udelay(2000);
+
+ ret = dm_gpio_set_value(&uc_priv->sleep, 1);
+ if (ret) {
+ log_debug("%s: error at sleep = 1 (%d)\n", __func__, ret);
+ return ret;
+ }
+
+ udelay(2000);
+
+ ret = dm_gpio_set_value(&uc_priv->reset, 0);
+ if (ret) {
+ log_debug("%s: error at sleep = 0 (%d)\n", __func__, ret);
+ return ret;
+ }
+
+ mdelay(10);
+
+ ret = dm_gpio_set_value(&uc_priv->reset, 1);
+ if (ret) {
+ log_debug("%s: error at sleep = 1 (%d)\n", __func__, ret);
+ return ret;
+ }
+
+ mdelay(10);
+
+ return 0;
+}
+
+static int cmc623_get_panel(struct udevice *dev)
+{
+ struct cmc623_priv *priv = dev_get_priv(dev);
+ int i, ret;
+
+ u32 num = ofnode_graph_get_port_count(dev_ofnode(dev));
+
+ for (i = 0; i < num; i++) {
+ ofnode remote = ofnode_graph_get_remote_node(dev_ofnode(dev), i, -1);
+
+ ret = uclass_get_device_by_ofnode(UCLASS_PANEL, remote, &priv->panel);
+ if (!ret)
+ return 0;
+ }
+
+ /* If this point is reached, no panels were found */
+ return -ENODEV;
+}
+
+static int cmc623_probe(struct udevice *dev)
+{
+ struct cmc623_priv *priv = dev_get_priv(dev);
+ int i, ret;
+
+ /* get supplies */
+ for (i = 0; i < ARRAY_SIZE(cmc623_supplies); i++) {
+ ret = device_get_supply_regulator(dev, cmc623_supplies[i], &priv->supplies[i]);
+ if (ret) {
+ log_debug("%s: cannot get %s %d\n", __func__, cmc623_supplies[i], ret);
+ if (ret != -ENOENT)
+ return log_ret(ret);
+ }
+ }
+
+ /* get control gpios */
+ ret = gpio_request_by_name(dev, "enable-gpios", 0, &priv->enable_gpio, GPIOD_IS_OUT);
+ if (ret) {
+ log_debug("%s: could not get enable-gpios (%d)\n", __func__, ret);
+ return ret;
+ }
+
+ ret = gpio_request_by_name(dev, "bypass-gpios", 0, &priv->bypass_gpio, GPIOD_IS_OUT);
+ if (ret) {
+ log_debug("%s: could not get bypass-gpios (%d)\n", __func__, ret);
+ return ret;
+ }
+
+ ret = cmc623_hw_init(dev);
+ if (ret) {
+ log_debug("%s: error doing hw init, ret %d\n", __func__, ret);
+ return ret;
+ }
+
+ ret = cmc623_get_panel(dev);
+ if (ret) {
+ log_debug("%s: panel not found, ret %d\n", __func__, ret);
+ return ret;
+ }
+
+ panel_get_display_timing(priv->panel, &priv->timing);
+
+ return 0;
+}
+
+static const struct video_bridge_ops cmc623_ops = {
+ .attach = cmc623_attach,
+ .set_backlight = cmc623_set_backlight,
+ .get_display_timing = cmc623_panel_timings,
+};
+
+static const struct udevice_id cmc623_ids[] = {
+ { .compatible = "samsung,cmc623" },
+ { }
+};
+
+U_BOOT_DRIVER(samsung_cmc623) = {
+ .name = "samsung_cmc623",
+ .id = UCLASS_VIDEO_BRIDGE,
+ .of_match = cmc623_ids,
+ .ops = &cmc623_ops,
+ .bind = dm_scan_fdt_dev,
+ .probe = cmc623_probe,
+ .priv_auto = sizeof(struct cmc623_priv),
+};
diff --git a/drivers/video/cmc623_backlight.c b/drivers/video/cmc623_backlight.c
new file mode 100644
index 00000000000..84b01724a07
--- /dev/null
+++ b/drivers/video/cmc623_backlight.c
@@ -0,0 +1,124 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2025 Ion Agorria <ion@agorria.com>
+ */
+
+#define LOG_CATEGORY UCLASS_PANEL_BACKLIGHT
+
+#include <backlight.h>
+#include <dm.h>
+#include <i2c.h>
+#include <log.h>
+#include <linux/err.h>
+#include <asm/gpio.h>
+#include <power/regulator.h>
+
+#define CMC623_I2C_REG_SELBANK 0x00
+#define CMC623_I2C_REG_PWMCTRL 0xb4
+#define CMC623_I2C_REG_REGMASK 0x28
+
+#define CMC623_BL_MIN_BRIGHTNESS 0
+#define CMC623_BL_DEF_BRIGHTNESS 50
+#define CMC623_BL_MAX_BRIGHTNESS 100
+
+struct cmc623_backlight_priv {
+ struct gpio_desc enable_gpio;
+};
+
+static int cmc623_backlight_enable(struct udevice *dev)
+{
+ struct cmc623_backlight_priv *priv = dev_get_priv(dev);
+
+ if (dm_gpio_is_valid(&priv->enable_gpio))
+ dm_gpio_set_value(&priv->enable_gpio, 1);
+
+ return 0;
+}
+
+static int cmc623_i2c_write(struct udevice *dev, u8 reg, u16 value)
+{
+ u8 data[2];
+
+ data[0] = (value >> 8) & 0xff;
+ data[1] = value & 0xff;
+
+ return dm_i2c_write(dev->parent, reg, data, 2);
+}
+
+static int cmc623_backlight_set_brightness(struct udevice *dev, int percent)
+{
+ int ret;
+ u16 brightness;
+
+ if (percent == BACKLIGHT_DEFAULT)
+ percent = CMC623_BL_DEF_BRIGHTNESS;
+
+ if (percent < CMC623_BL_MIN_BRIGHTNESS)
+ percent = CMC623_BL_MIN_BRIGHTNESS;
+
+ if (percent > CMC623_BL_MAX_BRIGHTNESS)
+ percent = CMC623_BL_MAX_BRIGHTNESS;
+
+ brightness = 0x4000 | (percent << 4);
+
+ ret = cmc623_i2c_write(dev, CMC623_I2C_REG_SELBANK, 0x0000);
+ if (ret) {
+ log_debug("%s: error at CMC623_I2C_REG_SELBANK (%d)\n",
+ __func__, ret);
+ return ret;
+ }
+
+ ret = cmc623_i2c_write(dev, CMC623_I2C_REG_PWMCTRL, brightness);
+ if (ret) {
+ log_debug("%s: error at CMC623_I2C_REG_PWMCTRL (%d)\n",
+ __func__, ret);
+ return ret;
+ }
+
+ ret = cmc623_i2c_write(dev, CMC623_I2C_REG_REGMASK, 0x0000);
+ if (ret) {
+ log_debug("%s: error at CMC623_I2C_REG_REGMASK (%d)\n",
+ __func__, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int cmc623_backlight_of_to_plat(struct udevice *dev)
+{
+ struct cmc623_backlight_priv *priv = dev_get_priv(dev);
+
+ gpio_request_by_name(dev, "enable-gpios", 0,
+ &priv->enable_gpio, GPIOD_IS_OUT);
+
+ return 0;
+}
+
+static int cmc623_backlight_probe(struct udevice *dev)
+{
+ if (device_get_uclass_id(dev->parent) != UCLASS_VIDEO_BRIDGE)
+ return -EPROTONOSUPPORT;
+
+ return 0;
+}
+
+static const struct backlight_ops cmc623_backlight_ops = {
+ .enable = cmc623_backlight_enable,
+ .set_brightness = cmc623_backlight_set_brightness,
+};
+
+static const struct udevice_id cmc623_backlight_ids[] = {
+ { .compatible = "samsung,cmc623-backlight" },
+ { }
+};
+
+U_BOOT_DRIVER(cmc623_backlight) = {
+ .name = "cmc623_backlight",
+ .id = UCLASS_PANEL_BACKLIGHT,
+ .of_match = cmc623_backlight_ids,
+ .of_to_plat = cmc623_backlight_of_to_plat,
+ .probe = cmc623_backlight_probe,
+ .ops = &cmc623_backlight_ops,
+ .priv_auto = sizeof(struct cmc623_backlight_priv),
+};
diff --git a/drivers/video/samsung-s6e63m0.c b/drivers/video/samsung-s6e63m0.c
new file mode 100644
index 00000000000..7497fc0f53a
--- /dev/null
+++ b/drivers/video/samsung-s6e63m0.c
@@ -0,0 +1,393 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2025 Ion Agorria <ion@agorria.com>
+ */
+
+#include <backlight.h>
+#include <dm.h>
+#include <panel.h>
+#include <log.h>
+#include <malloc.h>
+#include <spi.h>
+#include <mipi_display.h>
+#include <linux/delay.h>
+#include <power/regulator.h>
+#include <asm/gpio.h>
+
+#define S6E63M0_DCS_CMD 0
+#define S6E63M0_DCS_DATA 1
+
+#define S6E63M0_INFO_FLAG_PGAMMACTL BIT(0)
+#define S6E63M0_INFO_FLAG_GAMMA_DELTA BIT(1)
+
+#define S6E63M0_GTCON_FLAG_FLIP_H BIT(0)
+#define S6E63M0_GTCON_FLAG_FLIP_V BIT(1)
+
+/* Manufacturer Command Set */
+#define MCS_PENTILE_1 0xb3
+#define MCS_GAMMA_DELTA_Y_RED 0xb5
+#define MCS_GAMMA_DELTA_X_RED 0xb6
+#define MCS_GAMMA_DELTA_Y_GREEN 0xb7
+#define MCS_GAMMA_DELTA_X_GREEN 0xb8
+#define MCS_GAMMA_DELTA_Y_BLUE 0xb9
+#define MCS_GAMMA_DELTA_X_BLUE 0xba
+#define MCS_DISCTL 0xf2
+#define MCS_SRCCTL 0xf6
+#define MCS_IFCTL 0xf7
+#define MCS_PANELCTL 0xf8
+#define MCS_PGAMMACTL 0xfa
+
+#define MCS_PANELCTL_LEN 14
+#define MCS_IFCTL_LEN 3
+#define MCS_PGAMMACTL_LEN 22
+#define MCS_GAMMA_DELTA_Y_LEN 32
+#define MCS_GAMMA_DELTA_X_LEN 16
+
+struct s6e63m0_priv {
+ struct udevice *vdd3;
+ struct udevice *vci;
+
+ struct s6e63m0_info *info;
+
+ struct gpio_desc reset_gpio;
+
+ u8 gtcon;
+};
+
+struct s6e63m0_info {
+ const u32 flags;
+ struct display_timing timing;
+ const u8 cmd_mcs_panelctl[MCS_PANELCTL_LEN];
+ const u8 cmd_mcs_pgammactl_1[MCS_PGAMMACTL_LEN];
+ const u8 cmd_mcs_pgammactl_2;
+ const u8 cmd_mcs_gamma_delta_y[MCS_GAMMA_DELTA_Y_LEN];
+ const u8 cmd_mcs_gamma_delta_x[MCS_GAMMA_DELTA_X_LEN];
+};
+
+static const struct s6e63m0_info s6e63m0_generic_info = {
+ .flags = S6E63M0_INFO_FLAG_GAMMA_DELTA,
+ .timing = {
+ .pixelclock.typ = 25628,
+ .hactive.typ = 480,
+ .hfront_porch.typ = 16,
+ .hback_porch.typ = 16,
+ .hsync_len.typ = 2,
+ .vactive.typ = 800,
+ .vfront_porch.typ = 28,
+ .vback_porch.typ = 1,
+ .vsync_len.typ = 2,
+ .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
+ },
+ .cmd_mcs_panelctl = {
+ 0x01, /* DOCT */ 0x27, /* CLWEA */
+ 0x27, /* CLWEB*/ 0x07, /* CLTE */
+ 0x07, /* SHE */ 0x54, /* FLTE */
+ 0x9F, /* FLWE */ 0x63, /* SCTE */
+ 0x8F, /* SCWE */ 0x1A, /* INTE */
+ 0x33, /* INWE */ 0x0D, /* EMPS */
+ 0x00, /* E_INTE */ 0x00 /* E_INWE */
+ },
+ .cmd_mcs_pgammactl_1 = {
+ 0x00, 0x18, 0x08, 0x24, 0x64, 0x56, 0x33, 0xb6,
+ 0xba, 0xa8, 0xac, 0xb1, 0x9d, 0xc1, 0xc1, 0xb7,
+ 0x00, 0x9c, 0x00, 0x9f, 0x00, 0xd6
+ },
+ .cmd_mcs_pgammactl_2 = 0x01,
+ .cmd_mcs_gamma_delta_y = {
+ 0x2c, 0x12, 0x0c, 0x0a, 0x10, 0x0e, 0x17, 0x13,
+ 0x1f, 0x1a, 0x2a, 0x24, 0x1f, 0x1b, 0x1a, 0x17,
+ 0x2b, 0x26, 0x22, 0x20, 0x3a, 0x34, 0x30, 0x2c,
+ 0x29, 0x26, 0x25, 0x23, 0x21, 0x20, 0x1e, 0x1e
+ },
+ .cmd_mcs_gamma_delta_x = {
+ 0x00, 0x00, 0x11, 0x22, 0x33, 0x44, 0x44, 0x44,
+ 0x55, 0x55, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66
+ },
+};
+
+static const struct s6e63m0_info samsung_bose_panel_info = {
+ .flags = S6E63M0_INFO_FLAG_PGAMMACTL | S6E63M0_INFO_FLAG_GAMMA_DELTA,
+ .timing = {
+ .pixelclock.typ = 24000000,
+ .hactive.typ = 480,
+ .hfront_porch.typ = 16,
+ .hback_porch.typ = 14,
+ .hsync_len.typ = 2,
+ .vactive.typ = 800,
+ .vfront_porch.typ = 28,
+ .vback_porch.typ = 1,
+ .vsync_len.typ = 2,
+ .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
+ DISPLAY_FLAGS_DE_LOW | DISPLAY_FLAGS_PIXDATA_NEGEDGE,
+ },
+ .cmd_mcs_panelctl = {
+ 0x01, /* DOCT */ 0x27, /* CLWEA */
+ 0x27, /* CLWEB*/ 0x07, /* CLTE */
+ 0x07, /* SHE */ 0x54, /* FLTE */
+ 0x9F, /* FLWE */ 0x63, /* SCTE */
+ 0x86, /* SCWE */ 0x1A, /* INTE */
+ 0x33, /* INWE */ 0x0D, /* EMPS */
+ 0x00, /* E_INTE */ 0x00 /* E_INWE */
+ },
+ .cmd_mcs_pgammactl_1 = {
+ 0x02, 0x18, 0x08, 0x24, 0x70, 0x6e, 0x4e, 0xbc,
+ 0xc0, 0xaf, 0xb3, 0xb8, 0xa5, 0xc5, 0xc7, 0xbb,
+ 0x00, 0xb9, 0x00, 0xb8, 0x00, 0xfc
+ },
+ .cmd_mcs_pgammactl_2 = 0x03,
+ .cmd_mcs_gamma_delta_y = {
+ 0x2c, 0x12, 0x0c, 0x0a, 0x10, 0x0e, 0x17, 0x13,
+ 0x1f, 0x1a, 0x2a, 0x24, 0x1f, 0x1b, 0x1a, 0x17,
+ 0x2b, 0x26, 0x22, 0x20, 0x3a, 0x34, 0x30, 0x2c,
+ 0x29, 0x26, 0x25, 0x23, 0x21, 0x20, 0x1e, 0x1e
+ },
+ .cmd_mcs_gamma_delta_x = {
+ 0x00, 0x00, 0x11, 0x22, 0x33, 0x44, 0x44, 0x44,
+ 0x55, 0x55, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66
+ },
+};
+
+static int s6e63m0_dcs_write(struct udevice *dev, u8 cmd, const u8 *seq, size_t len)
+{
+ int ret;
+ u8 data[2];
+ int i;
+
+ data[0] = S6E63M0_DCS_CMD;
+ data[1] = cmd;
+
+ ret = dm_spi_xfer(dev, 9, &data, NULL, SPI_XFER_ONCE);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < len; i++) {
+ data[0] = S6E63M0_DCS_DATA;
+ data[1] = seq[i];
+
+ ret = dm_spi_xfer(dev, 9, &data, NULL, SPI_XFER_ONCE);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+#define s6e63m0_dcs_write_seq_static(dev, cmd, seq ...) ({ \
+ static const u8 d[] = { seq }; \
+ ret = s6e63m0_dcs_write(dev, cmd, d, ARRAY_SIZE(d)); \
+ if (ret) \
+ return ret; \
+})
+
+static int s6e63m0_enable_backlight(struct udevice *dev)
+{
+ struct s6e63m0_priv *priv = dev_get_priv(dev);
+ struct s6e63m0_info *info = priv->info;
+ u8 cmd_mcs_ifctl[MCS_IFCTL_LEN];
+ int ret;
+
+ ret = s6e63m0_dcs_write(dev, MCS_PANELCTL, info->cmd_mcs_panelctl, MCS_PANELCTL_LEN);
+ if (ret)
+ return ret;
+
+ s6e63m0_dcs_write_seq_static(dev, MCS_DISCTL,
+ 0x02, /* Number of Line */
+ 0x03, /* VBP */
+ 0x1c, /* VFP */
+ 0x10, /* HBP */
+ 0x10); /* HFP */
+
+ cmd_mcs_ifctl[0] = priv->gtcon; /* GTCON */
+ cmd_mcs_ifctl[1] = 0x00; /* Display Mode */
+ cmd_mcs_ifctl[2] = 0x00; /* Vsync/Hsync, DOCCLK, RGB mode */
+ ret = s6e63m0_dcs_write(dev, MCS_IFCTL, cmd_mcs_ifctl, MCS_IFCTL_LEN);
+ if (ret)
+ return ret;
+
+ if (info->flags & S6E63M0_INFO_FLAG_PGAMMACTL) {
+ ret = s6e63m0_dcs_write(dev, MCS_PGAMMACTL, info->cmd_mcs_pgammactl_1,
+ MCS_PGAMMACTL_LEN);
+ if (ret)
+ return ret;
+
+ s6e63m0_dcs_write(dev, MCS_PGAMMACTL, &info->cmd_mcs_pgammactl_2, 1);
+ }
+
+ s6e63m0_dcs_write_seq_static(dev, MCS_SRCCTL, 0x00, 0x8e, 0x07);
+ s6e63m0_dcs_write_seq_static(dev, MCS_PENTILE_1, 0x6c);
+
+ if (info->flags & S6E63M0_INFO_FLAG_GAMMA_DELTA) {
+ ret = s6e63m0_dcs_write(dev, MCS_GAMMA_DELTA_Y_RED, info->cmd_mcs_gamma_delta_y,
+ MCS_GAMMA_DELTA_Y_LEN);
+ if (ret)
+ return ret;
+
+ ret = s6e63m0_dcs_write(dev, MCS_GAMMA_DELTA_X_RED, info->cmd_mcs_gamma_delta_x,
+ MCS_GAMMA_DELTA_X_LEN);
+ if (ret)
+ return ret;
+
+ ret = s6e63m0_dcs_write(dev, MCS_GAMMA_DELTA_Y_GREEN, info->cmd_mcs_gamma_delta_y,
+ MCS_GAMMA_DELTA_Y_LEN);
+ if (ret)
+ return ret;
+
+ ret = s6e63m0_dcs_write(dev, MCS_GAMMA_DELTA_X_GREEN, info->cmd_mcs_gamma_delta_x,
+ MCS_GAMMA_DELTA_X_LEN);
+ if (ret)
+ return ret;
+
+ ret = s6e63m0_dcs_write(dev, MCS_GAMMA_DELTA_Y_BLUE, info->cmd_mcs_gamma_delta_y,
+ MCS_GAMMA_DELTA_Y_LEN);
+ if (ret)
+ return ret;
+
+ ret = s6e63m0_dcs_write(dev, MCS_GAMMA_DELTA_X_BLUE, info->cmd_mcs_gamma_delta_x,
+ MCS_GAMMA_DELTA_X_LEN);
+ if (ret)
+ return ret;
+ }
+
+ s6e63m0_dcs_write_seq_static(dev, MIPI_DCS_EXIT_SLEEP_MODE);
+ s6e63m0_dcs_write_seq_static(dev, MIPI_DCS_SET_DISPLAY_ON);
+
+ return 0;
+}
+
+static int s6e63m0_set_backlight(struct udevice *dev, int percent)
+{
+ return 0;
+}
+
+static int s6e63m0_get_display_timing(struct udevice *dev, struct display_timing *timing)
+{
+ struct s6e63m0_priv *priv = dev_get_priv(dev);
+
+ memcpy(timing, &priv->info->timing, sizeof(*timing));
+
+ return 0;
+}
+
+static int s6e63m0_of_to_plat(struct udevice *dev)
+{
+ struct s6e63m0_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = device_get_supply_regulator(dev, "vdd3-supply", &priv->vdd3);
+ if (ret) {
+ log_debug("%s: cannot get vdd3-supply: ret = %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ ret = device_get_supply_regulator(dev, "vci-supply", &priv->vci);
+ if (ret) {
+ log_debug("%s: cannot get vci-supply: ret = %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ ret = gpio_request_by_name(dev, "reset-gpios", 0,
+ &priv->reset_gpio, GPIOD_IS_OUT);
+ if (ret) {
+ log_debug("%s: cannot decode reset-gpios (%d)\n",
+ __func__, ret);
+ return ret;
+ }
+
+ if (dev_read_bool(dev, "flip-horizontal"))
+ priv->gtcon |= S6E63M0_GTCON_FLAG_FLIP_H;
+
+ if (dev_read_bool(dev, "flip-vertical"))
+ priv->gtcon |= S6E63M0_GTCON_FLAG_FLIP_V;
+
+ return 0;
+}
+
+static int s6e63m0_hw_init(struct udevice *dev)
+{
+ struct s6e63m0_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = dm_gpio_set_value(&priv->reset_gpio, 1);
+ if (ret) {
+ log_debug("%s: error entering reset (%d)\n", __func__, ret);
+ return ret;
+ }
+
+ ret = regulator_set_enable_if_allowed(priv->vdd3, 1);
+ if (ret) {
+ log_debug("%s: enabling vdd3-supply failed (%d)\n",
+ __func__, ret);
+ return ret;
+ }
+
+ mdelay(1);
+
+ ret = regulator_set_enable_if_allowed(priv->vci, 1);
+ if (ret) {
+ log_debug("%s: enabling vci-supply failed (%d)\n",
+ __func__, ret);
+ return ret;
+ }
+
+ mdelay(26);
+
+ ret = dm_gpio_set_value(&priv->reset_gpio, 0);
+ if (ret) {
+ log_debug("%s: error exiting reset (%d)\n", __func__, ret);
+ return ret;
+ }
+
+ mdelay(10);
+
+ return 0;
+}
+
+static int s6e63m0_probe(struct udevice *dev)
+{
+ struct s6e63m0_priv *priv = dev_get_priv(dev);
+ struct spi_slave *slave = dev_get_parent_priv(dev);
+ int ret;
+
+ if (device_get_uclass_id(dev->parent) != UCLASS_SPI)
+ return -EPROTONOSUPPORT;
+
+ ret = spi_claim_bus(slave);
+ if (ret) {
+ log_err("SPI bus allocation failed (%d)\n", ret);
+ return ret;
+ }
+
+ priv->info = (struct s6e63m0_info *)dev_get_driver_data(dev);
+
+ return s6e63m0_hw_init(dev);
+}
+
+static const struct panel_ops s6e63m0_ops = {
+ .enable_backlight = s6e63m0_enable_backlight,
+ .set_backlight = s6e63m0_set_backlight,
+ .get_display_timing = s6e63m0_get_display_timing,
+};
+
+static const struct udevice_id s6e63m0_ids[] = {
+ {
+ .compatible = "samsung,s6e63m0",
+ .data = (ulong)&s6e63m0_generic_info
+ },
+ {
+ .compatible = "samsung,bose-panel",
+ .data = (ulong)&samsung_bose_panel_info
+ },
+ { }
+};
+
+U_BOOT_DRIVER(samsung_s6e63m0) = {
+ .name = "samsung_s6e63m0",
+ .id = UCLASS_PANEL,
+ .of_match = s6e63m0_ids,
+ .ops = &s6e63m0_ops,
+ .of_to_plat = s6e63m0_of_to_plat,
+ .probe = s6e63m0_probe,
+ .priv_auto = sizeof(struct s6e63m0_priv),
+};
diff --git a/drivers/video/sony-l4f00430t01.c b/drivers/video/sony-l4f00430t01.c
new file mode 100644
index 00000000000..2303eb86143
--- /dev/null
+++ b/drivers/video/sony-l4f00430t01.c
@@ -0,0 +1,210 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2025 Ion Agorria <ion@agorria.com>
+ */
+
+#include <backlight.h>
+#include <dm.h>
+#include <panel.h>
+#include <log.h>
+#include <spi.h>
+#include <mipi_display.h>
+#include <linux/delay.h>
+#include <power/regulator.h>
+#include <asm/gpio.h>
+
+#define SONY_L4F00430T01_DCS_CMD 0
+#define SONY_L4F00430T01_DCS_DATA 1
+
+struct sony_l4f00430t01_priv {
+ struct udevice *vdd1v8;
+ struct udevice *vdd3v0;
+
+ struct udevice *backlight;
+
+ struct gpio_desc reset_gpio;
+};
+
+static struct display_timing default_timing = {
+ .pixelclock.typ = 24000000,
+ .hactive.typ = 480,
+ .hfront_porch.typ = 10,
+ .hback_porch.typ = 20,
+ .hsync_len.typ = 10,
+ .vactive.typ = 800,
+ .vfront_porch.typ = 3,
+ .vback_porch.typ = 4,
+ .vsync_len.typ = 2,
+ .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
+ DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE,
+};
+
+static int sony_l4f00430t01_write(struct udevice *dev, u8 cmd, const u8 *seq, int len)
+{
+ u8 data[2];
+ int i, ret;
+
+ data[0] = SONY_L4F00430T01_DCS_CMD;
+ data[1] = cmd;
+
+ ret = dm_spi_xfer(dev, 9, &data, NULL, SPI_XFER_ONCE);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < len; i++) {
+ data[0] = SONY_L4F00430T01_DCS_DATA;
+ data[1] = seq[i];
+
+ ret = dm_spi_xfer(dev, 9, &data, NULL, SPI_XFER_ONCE);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+#define sony_l4f00430t01_write_seq(dev, cmd, seq...) do { \
+ static const u8 b[] = { seq }; \
+ sony_l4f00430t01_write(dev, cmd, b, ARRAY_SIZE(b)); \
+ } while (0)
+
+static int sony_l4f00430t01_enable_backlight(struct udevice *dev)
+{
+ sony_l4f00430t01_write_seq(dev, MIPI_DCS_SET_ADDRESS_MODE, 0xd4);
+ mdelay(25);
+
+ sony_l4f00430t01_write_seq(dev, MIPI_DCS_EXIT_SLEEP_MODE);
+ mdelay(150);
+
+ sony_l4f00430t01_write_seq(dev, MIPI_DCS_SET_DISPLAY_ON);
+
+ return 0;
+}
+
+static int sony_l4f00430t01_set_backlight(struct udevice *dev, int percent)
+{
+ struct sony_l4f00430t01_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = uclass_get_device_by_phandle(UCLASS_PANEL_BACKLIGHT, dev,
+ "backlight", &priv->backlight);
+ if (ret) {
+ log_debug("%s: cannot get backlight: ret = %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ ret = backlight_enable(priv->backlight);
+ if (ret)
+ return ret;
+
+ return backlight_set_brightness(priv->backlight, percent);
+}
+
+static int sony_l4f00430t01_get_display_timing(struct udevice *dev,
+ struct display_timing *timing)
+{
+ memcpy(timing, &default_timing, sizeof(*timing));
+ return 0;
+}
+
+static int sony_l4f00430t01_of_to_plat(struct udevice *dev)
+{
+ struct sony_l4f00430t01_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = device_get_supply_regulator(dev, "vdd1v8-supply", &priv->vdd1v8);
+ if (ret) {
+ log_debug("%s: cannot get vdd1v8-supply: ret = %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ ret = device_get_supply_regulator(dev, "vdd3v0-supply", &priv->vdd3v0);
+ if (ret) {
+ log_debug("%s: cannot get vdd3v0-supply: ret = %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ ret = gpio_request_by_name(dev, "reset-gpios", 0,
+ &priv->reset_gpio, GPIOD_IS_OUT);
+ if (ret) {
+ log_debug("%s: cannot decode reset-gpios (%d)\n",
+ __func__, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int sony_l4f00430t01_hw_init(struct udevice *dev)
+{
+ struct sony_l4f00430t01_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = dm_gpio_set_value(&priv->reset_gpio, 1);
+ if (ret) {
+ log_debug("%s: error entering reset (%d)\n", __func__, ret);
+ return ret;
+ }
+
+ ret = regulator_set_enable_if_allowed(priv->vdd1v8, 1);
+ if (ret) {
+ log_debug("%s: enabling vdd1v8-supply failed (%d)\n",
+ __func__, ret);
+ return ret;
+ }
+
+ ret = regulator_set_enable_if_allowed(priv->vdd3v0, 1);
+ if (ret) {
+ log_debug("%s: enabling vdd3v0-supply failed (%d)\n",
+ __func__, ret);
+ return ret;
+ }
+ mdelay(15);
+
+ ret = dm_gpio_set_value(&priv->reset_gpio, 0);
+ if (ret) {
+ log_debug("%s: error exiting reset (%d)\n", __func__, ret);
+ return ret;
+ }
+ mdelay(100);
+
+ return 0;
+}
+
+static int sony_l4f00430t01_probe(struct udevice *dev)
+{
+ struct spi_slave *slave = dev_get_parent_priv(dev);
+ int ret;
+
+ ret = spi_claim_bus(slave);
+ if (ret) {
+ log_err("SPI bus allocation failed (%d)\n", ret);
+ return ret;
+ }
+
+ return sony_l4f00430t01_hw_init(dev);
+}
+
+static const struct panel_ops sony_l4f00430t01_ops = {
+ .enable_backlight = sony_l4f00430t01_enable_backlight,
+ .set_backlight = sony_l4f00430t01_set_backlight,
+ .get_display_timing = sony_l4f00430t01_get_display_timing,
+};
+
+static const struct udevice_id sony_l4f00430t01_ids[] = {
+ { .compatible = "sony,l4f00430t01" },
+ { }
+};
+
+U_BOOT_DRIVER(sony_l4f00430t01) = {
+ .name = "sony_l4f00430t01",
+ .id = UCLASS_PANEL,
+ .of_match = sony_l4f00430t01_ids,
+ .ops = &sony_l4f00430t01_ops,
+ .of_to_plat = sony_l4f00430t01_of_to_plat,
+ .probe = sony_l4f00430t01_probe,
+ .priv_auto = sizeof(struct sony_l4f00430t01_priv),
+};
diff --git a/drivers/video/tegra/dc.c b/drivers/video/tegra/dc.c
index f0e3d2c993f..ced49718834 100644
--- a/drivers/video/tegra/dc.c
+++ b/drivers/video/tegra/dc.c
@@ -238,8 +238,24 @@ static void rgb_enable(struct tegra_lcd_priv *priv)
else
value &= ~LVS_OUTPUT_POLARITY_LOW;
+ /* configure pixel data signal polarity */
+ if (dt->flags & DISPLAY_FLAGS_PIXDATA_POSEDGE)
+ value &= ~LSC0_OUTPUT_POLARITY_LOW;
+ else
+ value |= LSC0_OUTPUT_POLARITY_LOW;
+
writel(value, &com->pin_output_polarity[1]);
+ /* configure data enable signal polarity */
+ value = readl(&com->pin_output_polarity[3]);
+
+ if (dt->flags & DISPLAY_FLAGS_DE_LOW)
+ value |= LSPI_OUTPUT_POLARITY_LOW;
+ else
+ value &= ~LSPI_OUTPUT_POLARITY_LOW;
+
+ writel(value, &com->pin_output_polarity[3]);
+
for (i = 0; i < PIN_OUTPUT_SEL_COUNT; i++)
writel(rgb_sel_tab[i], &com->pin_output_sel[i]);
}
generated by cgit v1.2.3 (git 2.0.4) at 2025-09-19 23:49:33 +0000