diff options
Diffstat (limited to 'drivers')
105 files changed, 6927 insertions, 1444 deletions
diff --git a/drivers/block/blkmap.c b/drivers/block/blkmap.c index 34eed1380dc..473c65b5911 100644 --- a/drivers/block/blkmap.c +++ b/drivers/block/blkmap.c @@ -17,6 +17,30 @@ struct blkmap; /** + * define BLKMAP_SLICE_LINEAR - Linear mapping to another block device + * + * This blkmap slice type is used for mapping to other existing block + * devices. + */ +#define BLKMAP_SLICE_LINEAR BIT(0) + +/** + * define BLKMAP_SLICE_MEM - Linear mapping to memory based block device + * + * This blkmap slice type is used for mapping to memory based block + * devices, like ramdisks. + */ +#define BLKMAP_SLICE_MEM BIT(1) + +/** + * define BLKMAP_SLICE_PRESERVE - Preserved blkmap slice + * + * This blkmap slice is intended to be preserved, and it's + * information passed on to a later stage, like OS. + */ +#define BLKMAP_SLICE_PRESERVE BIT(2) + +/** * struct blkmap_slice - Region mapped to a blkmap * * Common data for a region mapped to a blkmap, specialized by each @@ -25,12 +49,14 @@ struct blkmap; * @node: List node used to associate this slice with a blkmap * @blknr: Start block number of the mapping * @blkcnt: Number of blocks covered by this mapping + * @attr: Attributes of blkmap slice */ struct blkmap_slice { struct list_head node; lbaint_t blknr; lbaint_t blkcnt; + uint attr; /** * @read: - Read from slice @@ -169,6 +195,7 @@ int blkmap_map_linear(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt, .slice = { .blknr = blknr, .blkcnt = blkcnt, + .attr = BLKMAP_SLICE_LINEAR, .read = blkmap_linear_read, .write = blkmap_linear_write, @@ -234,7 +261,7 @@ static void blkmap_mem_destroy(struct blkmap *bm, struct blkmap_slice *bms) } int __blkmap_map_mem(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt, - void *addr, bool remapped) + void *addr, bool remapped, bool preserve) { struct blkmap *bm = dev_get_plat(dev); struct blkmap_mem *bmm; @@ -248,6 +275,7 @@ int __blkmap_map_mem(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt, .slice = { .blknr = blknr, .blkcnt = blkcnt, + .attr = BLKMAP_SLICE_MEM, .read = blkmap_mem_read, .write = blkmap_mem_write, @@ -258,6 +286,9 @@ int __blkmap_map_mem(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt, .remapped = remapped, }; + if (preserve) + bmm->slice.attr |= BLKMAP_SLICE_PRESERVE; + err = blkmap_slice_add(bm, &bmm->slice); if (err) free(bmm); @@ -268,11 +299,11 @@ int __blkmap_map_mem(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt, int blkmap_map_mem(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt, void *addr) { - return __blkmap_map_mem(dev, blknr, blkcnt, addr, false); + return __blkmap_map_mem(dev, blknr, blkcnt, addr, false, false); } int blkmap_map_pmem(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt, - phys_addr_t paddr) + phys_addr_t paddr, bool preserve) { struct blkmap *bm = dev_get_plat(dev); struct blk_desc *bd = dev_get_uclass_plat(bm->blk); @@ -283,7 +314,7 @@ int blkmap_map_pmem(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt, if (!addr) return -ENOMEM; - err = __blkmap_map_mem(dev, blknr, blkcnt, addr, true); + err = __blkmap_map_mem(dev, blknr, blkcnt, addr, true, preserve); if (err) unmap_sysmem(addr); @@ -486,6 +517,49 @@ err: return err; } +static bool blkmap_mem_preserve_slice(struct blkmap_slice *bms) +{ + return (bms->attr & (BLKMAP_SLICE_MEM | BLKMAP_SLICE_PRESERVE)) == + (BLKMAP_SLICE_MEM | BLKMAP_SLICE_PRESERVE); +} + +int blkmap_get_preserved_pmem_slices(int (*cb)(void *ctx, u64 addr, + u64 size), void *ctx) +{ + int ret; + u64 addr, size; + struct udevice *dev; + struct uclass *uc; + struct blkmap *bm; + struct blkmap_mem *bmm; + struct blkmap_slice *bms; + struct blk_desc *bd; + + if (!cb) { + log_debug("%s: No callback passed to the function\n", __func__); + return 0; + } + + uclass_id_foreach_dev(UCLASS_BLKMAP, dev, uc) { + bm = dev_get_plat(dev); + bd = dev_get_uclass_plat(bm->blk); + + list_for_each_entry(bms, &bm->slices, node) { + if (!blkmap_mem_preserve_slice(bms)) + continue; + + bmm = container_of(bms, struct blkmap_mem, slice); + addr = (u64)(uintptr_t)bmm->addr; + size = (u64)bms->blkcnt << bd->log2blksz; + ret = cb(ctx, addr, size); + if (ret) + return ret; + } + } + + return 0; +} + int blkmap_destroy(struct udevice *dev) { int err; diff --git a/drivers/block/blkmap_helper.c b/drivers/block/blkmap_helper.c index bfba14110d2..2f1bc28ee5d 100644 --- a/drivers/block/blkmap_helper.c +++ b/drivers/block/blkmap_helper.c @@ -28,7 +28,7 @@ int blkmap_create_ramdisk(const char *label, ulong image_addr, ulong image_size, bm = dev_get_plat(bm_dev); desc = dev_get_uclass_plat(bm->blk); blknum = image_size >> desc->log2blksz; - ret = blkmap_map_pmem(bm_dev, 0, blknum, image_addr); + ret = blkmap_map_pmem(bm_dev, 0, blknum, image_addr, true); if (ret) { log_err("Unable to map %#llx at block %d : %d\n", (unsigned long long)image_addr, 0, ret); diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c index 199ca6eaa37..9e3b5191767 100644 --- a/drivers/clk/clk-composite.c +++ b/drivers/clk/clk-composite.c @@ -97,7 +97,7 @@ static int clk_composite_disable(struct clk *clk) return 0; } -struct clk *clk_register_composite(struct device *dev, const char *name, +struct clk *clk_register_composite(struct udevice *dev, const char *name, const char * const *parent_names, int num_parents, struct clk *mux, const struct clk_ops *mux_ops, @@ -149,7 +149,7 @@ struct clk *clk_register_composite(struct device *dev, const char *name, clk = &composite->clk; clk->flags = flags; ret = clk_register(clk, UBOOT_DM_CLK_COMPOSITE, name, - parent_names[clk_composite_get_parent(clk)]); + clk_resolve_parent_clk(dev, parent_names[clk_composite_get_parent(clk)])); if (ret) { clk = ERR_PTR(ret); goto err; diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c index aa210e3d15f..e692b9c2167 100644 --- a/drivers/clk/clk-divider.c +++ b/drivers/clk/clk-divider.c @@ -183,7 +183,7 @@ const struct clk_ops clk_divider_ops = { .set_rate = clk_divider_set_rate, }; -static struct clk *_register_divider(struct device *dev, const char *name, +static struct clk *_register_divider(struct udevice *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags, const struct clk_div_table *table) @@ -218,7 +218,8 @@ static struct clk *_register_divider(struct device *dev, const char *name, clk = &div->clk; clk->flags = flags; - ret = clk_register(clk, UBOOT_DM_CLK_CCF_DIVIDER, name, parent_name); + ret = clk_register(clk, UBOOT_DM_CLK_CCF_DIVIDER, name, + clk_resolve_parent_clk(dev, parent_name)); if (ret) { kfree(div); return ERR_PTR(ret); @@ -227,7 +228,7 @@ static struct clk *_register_divider(struct device *dev, const char *name, return clk; } -struct clk *clk_register_divider(struct device *dev, const char *name, +struct clk *clk_register_divider(struct udevice *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags) diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c index 068798cf9b0..4eb8be728e6 100644 --- a/drivers/clk/clk-fixed-factor.c +++ b/drivers/clk/clk-fixed-factor.c @@ -37,7 +37,7 @@ const struct clk_ops ccf_clk_fixed_factor_ops = { .get_rate = clk_factor_recalc_rate, }; -struct clk *clk_hw_register_fixed_factor(struct device *dev, +struct clk *clk_hw_register_fixed_factor(struct udevice *dev, const char *name, const char *parent_name, unsigned long flags, unsigned int mult, unsigned int div) { @@ -56,7 +56,7 @@ struct clk *clk_hw_register_fixed_factor(struct device *dev, clk->flags = flags; ret = clk_register(clk, UBOOT_DM_CLK_IMX_FIXED_FACTOR, name, - parent_name); + clk_resolve_parent_clk(dev, parent_name)); if (ret) { kfree(fix); return ERR_PTR(ret); @@ -65,7 +65,7 @@ struct clk *clk_hw_register_fixed_factor(struct device *dev, return clk; } -struct clk *clk_register_fixed_factor(struct device *dev, const char *name, +struct clk *clk_register_fixed_factor(struct udevice *dev, const char *name, const char *parent_name, unsigned long flags, unsigned int mult, unsigned int div) { diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c index bf1c6a93b46..256ff108991 100644 --- a/drivers/clk/clk-gate.c +++ b/drivers/clk/clk-gate.c @@ -117,7 +117,7 @@ const struct clk_ops clk_gate_ops = { .get_rate = clk_generic_get_rate, }; -struct clk *clk_register_gate(struct device *dev, const char *name, +struct clk *clk_register_gate(struct udevice *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 bit_idx, u8 clk_gate_flags, spinlock_t *lock) @@ -149,7 +149,8 @@ struct clk *clk_register_gate(struct device *dev, const char *name, clk = &gate->clk; clk->flags = flags; - ret = clk_register(clk, UBOOT_DM_CLK_GATE, name, parent_name); + ret = clk_register(clk, UBOOT_DM_CLK_GATE, name, + clk_resolve_parent_clk(dev, parent_name)); if (ret) { kfree(gate); return ERR_PTR(ret); diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c index 62477e15d27..d7411f8f282 100644 --- a/drivers/clk/clk-mux.c +++ b/drivers/clk/clk-mux.c @@ -113,6 +113,11 @@ int clk_mux_fetch_parent_index(struct clk *clk, struct clk *parent) for (i = 0; i < mux->num_parents; i++) { if (!strcmp(parent->dev->name, mux->parent_names[i])) return i; + if (!strcmp(parent->dev->name, + clk_resolve_parent_clk(clk->dev, + mux->parent_names[i]))) + return i; + } return -EINVAL; @@ -159,15 +164,15 @@ const struct clk_ops clk_mux_ops = { .set_parent = clk_mux_set_parent, }; -struct clk *clk_hw_register_mux_table(struct device *dev, const char *name, +struct clk *clk_register_mux(struct udevice *dev, const char *name, const char * const *parent_names, u8 num_parents, unsigned long flags, - void __iomem *reg, u8 shift, u32 mask, - u8 clk_mux_flags, u32 *table) + void __iomem *reg, u8 shift, u8 width, + u8 clk_mux_flags) { + u32 mask = BIT(width) - 1; struct clk_mux *mux; struct clk *clk; - u8 width = 0; int ret; if (clk_mux_flags & CLK_MUX_HIWORD_MASK) { @@ -192,7 +197,7 @@ struct clk *clk_hw_register_mux_table(struct device *dev, const char *name, mux->shift = shift; mux->mask = mask; mux->flags = clk_mux_flags; - mux->table = table; + mux->table = NULL; #if IS_ENABLED(CONFIG_SANDBOX_CLK_CCF) mux->io_mux_val = *(u32 *)reg; #endif @@ -207,7 +212,8 @@ struct clk *clk_hw_register_mux_table(struct device *dev, const char *name, * for the corresponding clock (to do that define .set_parent() method). */ ret = clk_register(clk, UBOOT_DM_CLK_CCF_MUX, name, - parent_names[clk_mux_get_parent(clk)]); + clk_resolve_parent_clk(dev, + parent_names[clk_mux_get_parent(clk)])); if (ret) { kfree(mux); return ERR_PTR(ret); @@ -216,35 +222,6 @@ struct clk *clk_hw_register_mux_table(struct device *dev, const char *name, return clk; } -struct clk *clk_register_mux_table(struct device *dev, const char *name, - const char * const *parent_names, u8 num_parents, - unsigned long flags, - void __iomem *reg, u8 shift, u32 mask, - u8 clk_mux_flags, u32 *table) -{ - struct clk *clk; - - clk = clk_hw_register_mux_table(dev, name, parent_names, num_parents, - flags, reg, shift, mask, clk_mux_flags, - table); - if (IS_ERR(clk)) - return ERR_CAST(clk); - return clk; -} - -struct clk *clk_register_mux(struct device *dev, const char *name, - const char * const *parent_names, u8 num_parents, - unsigned long flags, - void __iomem *reg, u8 shift, u8 width, - u8 clk_mux_flags) -{ - u32 mask = BIT(width) - 1; - - return clk_register_mux_table(dev, name, parent_names, num_parents, - flags, reg, shift, mask, clk_mux_flags, - NULL); -} - U_BOOT_DRIVER(ccf_clk_mux) = { .name = UBOOT_DM_CLK_CCF_MUX, .id = UCLASS_CLK, diff --git a/drivers/clk/clk-stub.c b/drivers/clk/clk-stub.c index 5fbbb07b7f7..343fa5cd3fe 100644 --- a/drivers/clk/clk-stub.c +++ b/drivers/clk/clk-stub.c @@ -50,6 +50,7 @@ static struct clk_ops stub_clk_ops = { static const struct udevice_id stub_clk_ids[] = { { .compatible = "qcom,rpmcc" }, + { .compatible = "qcom,sc7280-rpmh-clk" }, { .compatible = "qcom,sm8150-rpmh-clk" }, { .compatible = "qcom,sm8250-rpmh-clk" }, { .compatible = "qcom,sm8550-rpmh-clk" }, diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index 353ae476068..90b70529a47 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -420,6 +420,24 @@ int clk_get_by_name_nodev(ofnode node, const char *name, struct clk *clk) return clk_get_by_index_nodev(node, index, clk); } +const char * +clk_resolve_parent_clk(struct udevice *dev, const char *name) +{ + struct udevice *parent; + struct clk clk; + int ret; + + ret = uclass_get_device_by_name(UCLASS_CLK, name, &parent); + if (!ret) + return name; + + ret = clk_get_by_name(dev, name, &clk); + if (!clk.dev) + return name; + + return clk.dev->name; +} + int clk_release_all(struct clk *clk, unsigned int count) { unsigned int i; diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig index 56d893e0579..d17a54fb9b3 100644 --- a/drivers/clk/imx/Kconfig +++ b/drivers/clk/imx/Kconfig @@ -60,6 +60,7 @@ config SPL_CLK_IMX8MP depends on ARCH_IMX8M && SPL select SPL_CLK select SPL_CLK_CCF + select SPL_CLK_COMPOSITE_CCF help This enables SPL DM/DTS support for clock driver in i.MX8MP diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-composite-8m.c index 64bffa3b181..14c5b92939c 100644 --- a/drivers/clk/imx/clk-composite-8m.c +++ b/drivers/clk/imx/clk-composite-8m.c @@ -151,7 +151,7 @@ const struct clk_ops imx8m_clk_mux_ops = { .set_parent = imx8m_clk_mux_set_parent, }; -struct clk *imx8m_clk_composite_flags(const char *name, +struct clk *imx8m_clk_composite_flags(struct udevice *dev, const char *name, const char * const *parent_names, int num_parents, void __iomem *reg, unsigned long flags) @@ -187,7 +187,7 @@ struct clk *imx8m_clk_composite_flags(const char *name, gate->reg = reg; gate->bit_idx = PCG_CGC_SHIFT; - clk = clk_register_composite(NULL, name, + clk = clk_register_composite(dev, name, parent_names, num_parents, &mux->clk, &imx8m_clk_mux_ops, &div->clk, &imx8m_clk_composite_divider_ops, diff --git a/drivers/clk/imx/clk-gate2.c b/drivers/clk/imx/clk-gate2.c index 65fa6b5b139..fa07b13249b 100644 --- a/drivers/clk/imx/clk-gate2.c +++ b/drivers/clk/imx/clk-gate2.c @@ -90,7 +90,7 @@ static const struct clk_ops clk_gate2_ops = { .get_rate = clk_generic_get_rate, }; -struct clk *clk_register_gate2(struct device *dev, const char *name, +struct clk *clk_register_gate2(struct udevice *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 bit_idx, u8 cgr_val, u8 clk_gate2_flags, unsigned int *share_count) @@ -111,7 +111,8 @@ struct clk *clk_register_gate2(struct device *dev, const char *name, clk = &gate->clk; - ret = clk_register(clk, UBOOT_DM_CLK_IMX_GATE2, name, parent_name); + ret = clk_register(clk, UBOOT_DM_CLK_IMX_GATE2, name, + clk_resolve_parent_clk(dev, parent_name)); if (ret) { kfree(gate); return ERR_PTR(ret); diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c index df9f0285e1e..13239f2f64d 100644 --- a/drivers/clk/imx/clk-imx6q.c +++ b/drivers/clk/imx/clk-imx6q.c @@ -35,6 +35,8 @@ static const char *const usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", }; static const char *const periph_sels[] = { "periph_pre", "periph_clk2", }; static const char *const periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll2_198m", }; +static const char *const uart_sels[] = { "pll3_80m", "osc", }; +static const char *const ecspi_sels[] = { "pll3_60m", "osc", }; static int imx6q_clk_probe(struct udevice *dev) { @@ -44,21 +46,21 @@ static int imx6q_clk_probe(struct udevice *dev) base = (void *)ANATOP_BASE_ADDR; clk_dm(IMX6QDL_CLK_PLL2, - imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc", + imx_clk_pllv3(dev, IMX_PLLV3_GENERIC, "pll2_bus", "osc", base + 0x30, 0x1)); clk_dm(IMX6QDL_CLK_PLL3_USB_OTG, - imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc", + imx_clk_pllv3(dev, IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x3)); clk_dm(IMX6QDL_CLK_PLL3_60M, - imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8)); + imx_clk_fixed_factor(dev, "pll3_60m", "pll3_usb_otg", 1, 8)); clk_dm(IMX6QDL_CLK_PLL2_PFD0_352M, imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0)); clk_dm(IMX6QDL_CLK_PLL2_PFD2_396M, imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2)); clk_dm(IMX6QDL_CLK_PLL6, - imx_clk_pllv3(IMX_PLLV3_ENET, "pll6", "osc", base + 0xe0, 0x3)); + imx_clk_pllv3(dev, IMX_PLLV3_ENET, "pll6", "osc", base + 0xe0, 0x3)); clk_dm(IMX6QDL_CLK_PLL6_ENET, - imx_clk_gate("pll6_enet", "pll6", base + 0xe0, 13)); + imx_clk_gate(dev, "pll6_enet", "pll6", base + 0xe0, 13)); /* CCM clocks */ base = dev_read_addr_ptr(dev); @@ -66,76 +68,98 @@ static int imx6q_clk_probe(struct udevice *dev) return -EINVAL; clk_dm(IMX6QDL_CLK_USDHC1_SEL, - imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1, + imx_clk_mux(dev, "usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels))); clk_dm(IMX6QDL_CLK_USDHC2_SEL, - imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1, + imx_clk_mux(dev, "usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels))); clk_dm(IMX6QDL_CLK_USDHC3_SEL, - imx_clk_mux("usdhc3_sel", base + 0x1c, 18, 1, + imx_clk_mux(dev, "usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels))); clk_dm(IMX6QDL_CLK_USDHC4_SEL, - imx_clk_mux("usdhc4_sel", base + 0x1c, 19, 1, + imx_clk_mux(dev, "usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels))); + if (of_machine_is_compatible("fsl,imx6qp")) { + clk_dm(IMX6QDL_CLK_UART_SEL, + imx_clk_mux(dev, "uart_sel", base + 0x24, 6, 1, uart_sels, + ARRAY_SIZE(uart_sels))); + clk_dm(IMX6QDL_CLK_ECSPI_SEL, + imx_clk_mux(dev, "ecspi_sel", base + 0x38, 18, 1, ecspi_sels, + ARRAY_SIZE(ecspi_sels))); + } + clk_dm(IMX6QDL_CLK_USDHC1_PODF, - imx_clk_divider("usdhc1_podf", "usdhc1_sel", + imx_clk_divider(dev, "usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3)); clk_dm(IMX6QDL_CLK_USDHC2_PODF, - imx_clk_divider("usdhc2_podf", "usdhc2_sel", + imx_clk_divider(dev, "usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3)); clk_dm(IMX6QDL_CLK_USDHC3_PODF, - imx_clk_divider("usdhc3_podf", "usdhc3_sel", + imx_clk_divider(dev, "usdhc3_podf", "usdhc3_sel", base + 0x24, 19, 3)); clk_dm(IMX6QDL_CLK_USDHC4_PODF, - imx_clk_divider("usdhc4_podf", "usdhc4_sel", + imx_clk_divider(dev, "usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3)); - clk_dm(IMX6QDL_CLK_ECSPI_ROOT, - imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6)); + if (of_machine_is_compatible("fsl,imx6qp")) { + clk_dm(IMX6QDL_CLK_UART_SERIAL_PODF, + imx_clk_divider(dev, "uart_serial_podf", "uart_sel", base + 0x24, 0, 6)); + clk_dm(IMX6QDL_CLK_ECSPI_ROOT, + imx_clk_divider(dev, "ecspi_root", "ecspi_sel", base + 0x38, 19, 6)); + } else { + clk_dm(IMX6QDL_CLK_UART_SERIAL_PODF, + imx_clk_divider(dev, "uart_serial_podf", "pll3_80m", base + 0x24, 0, 6)); + clk_dm(IMX6QDL_CLK_ECSPI_ROOT, + imx_clk_divider(dev, "ecspi_root", "pll3_60m", base + 0x38, 19, 6)); + } clk_dm(IMX6QDL_CLK_ECSPI1, - imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0)); + imx_clk_gate2(dev, "ecspi1", "ecspi_root", base + 0x6c, 0)); clk_dm(IMX6QDL_CLK_ECSPI2, - imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2)); + imx_clk_gate2(dev, "ecspi2", "ecspi_root", base + 0x6c, 2)); clk_dm(IMX6QDL_CLK_ECSPI3, - imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4)); + imx_clk_gate2(dev, "ecspi3", "ecspi_root", base + 0x6c, 4)); clk_dm(IMX6QDL_CLK_ECSPI4, - imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6)); + imx_clk_gate2(dev, "ecspi4", "ecspi_root", base + 0x6c, 6)); + clk_dm(IMX6QDL_CLK_UART_IPG, + imx_clk_gate2(dev, "uart_ipg", "ipg", base + 0x7c, 24)); + clk_dm(IMX6QDL_CLK_UART_SERIAL, + imx_clk_gate2(dev, "uart_serial", "uart_serial_podf", base + 0x7c, 26)); clk_dm(IMX6QDL_CLK_USDHC1, - imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2)); + imx_clk_gate2(dev, "usdhc1", "usdhc1_podf", base + 0x80, 2)); clk_dm(IMX6QDL_CLK_USDHC2, - imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4)); + imx_clk_gate2(dev, "usdhc2", "usdhc2_podf", base + 0x80, 4)); clk_dm(IMX6QDL_CLK_USDHC3, - imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6)); + imx_clk_gate2(dev, "usdhc3", "usdhc3_podf", base + 0x80, 6)); clk_dm(IMX6QDL_CLK_USDHC4, - imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8)); + imx_clk_gate2(dev, "usdhc4", "usdhc4_podf", base + 0x80, 8)); clk_dm(IMX6QDL_CLK_PERIPH_PRE, - imx_clk_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels, + imx_clk_mux(dev, "periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels))); clk_dm(IMX6QDL_CLK_PERIPH, - imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, + imx_clk_busy_mux(dev, "periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels))); clk_dm(IMX6QDL_CLK_AHB, - imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, + imx_clk_busy_divider(dev, "ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1)); clk_dm(IMX6QDL_CLK_IPG, - imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2)); + imx_clk_divider(dev, "ipg", "ahb", base + 0x14, 8, 2)); clk_dm(IMX6QDL_CLK_IPG_PER, - imx_clk_divider("ipg_per", "ipg", base + 0x1c, 0, 6)); + imx_clk_divider(dev, "ipg_per", "ipg", base + 0x1c, 0, 6)); clk_dm(IMX6QDL_CLK_I2C1, - imx_clk_gate2("i2c1", "ipg_per", base + 0x70, 6)); + imx_clk_gate2(dev, "i2c1", "ipg_per", base + 0x70, 6)); clk_dm(IMX6QDL_CLK_I2C2, - imx_clk_gate2("i2c2", "ipg_per", base + 0x70, 8)); + imx_clk_gate2(dev, "i2c2", "ipg_per", base + 0x70, 8)); clk_dm(IMX6QDL_CLK_I2C3, - imx_clk_gate2("i2c3", "ipg_per", base + 0x70, 10)); + imx_clk_gate2(dev, "i2c3", "ipg_per", base + 0x70, 10)); clk_dm(IMX6QDL_CLK_PWM1, - imx_clk_gate2("pwm1", "ipg_per", base + 0x78, 16)); + imx_clk_gate2(dev, "pwm1", "ipg_per", base + 0x78, 16)); - clk_dm(IMX6QDL_CLK_ENET, imx_clk_gate2("enet", "ipg", base + 0x6c, 10)); + clk_dm(IMX6QDL_CLK_ENET, imx_clk_gate2(dev, "enet", "ipg", base + 0x6c, 10)); clk_dm(IMX6QDL_CLK_ENET_REF, - imx_clk_fixed_factor("enet_ref", "pll6_enet", 1, 1)); + imx_clk_fixed_factor(dev, "enet_ref", "pll6_enet", 1, 1)); return 0; } diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c index bb6958f0ec2..b81db516a69 100644 --- a/drivers/clk/imx/clk-imx8mm.c +++ b/drivers/clk/imx/clk-imx8mm.c @@ -14,7 +14,7 @@ #include "clk.h" -static const char * const pll_ref_sels[] = { "clock-osc-24m", "dummy", "dummy", "dummy", }; +static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", }; static const char * const dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", }; static const char * const arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", }; static const char * const sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", }; @@ -23,128 +23,144 @@ static const char * const sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_se static const char * const imx8mm_arm_core_sels[] = {"arm_a53_src", "arm_pll_out", }; -static const char * const imx8mm_a53_sels[] = {"clock-osc-24m", "arm_pll_out", "sys_pll2_500m", +static const char * const imx8mm_a53_sels[] = {"osc_24m", "arm_pll_out", "sys_pll2_500m", "sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m", "audio_pll1_out", "sys_pll3_out", }; -static const char * const imx8mm_ahb_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_800m", +static const char * const imx8mm_ahb_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_800m", "sys_pll1_400m", "sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", "video_pll1_out", }; #ifndef CONFIG_XPL_BUILD -static const char * const imx8mm_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", +static const char * const imx8mm_enet_axi_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_250m", "sys_pll2_200m", "audio_pll1_out", "video_pll1_out", "sys_pll3_out", }; -static const char * const imx8mm_enet_ref_sels[] = {"clock-osc-24m", "sys_pll2_125m", "sys_pll2_50m", +static const char * const imx8mm_enet_ref_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_50m", "sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out", "video_pll1_out", "clk_ext4", }; -static const char * const imx8mm_enet_timer_sels[] = {"clock-osc-24m", "sys_pll2_100m", "audio_pll1_out", +static const char * const imx8mm_enet_timer_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_out", "clk_ext1", "clk_ext2", "clk_ext3", "clk_ext4", "video_pll1_out", }; -static const char * const imx8mm_enet_phy_sels[] = {"clock-osc-24m", "sys_pll2_50m", "sys_pll2_125m", +static const char * const imx8mm_enet_phy_sels[] = {"osc_24m", "sys_pll2_50m", "sys_pll2_125m", "sys_pll2_200m", "sys_pll2_500m", "video_pll1_out", "audio_pll2_out", }; #endif -static const char * const imx8mm_nand_usdhc_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", +static const char * const imx8mm_nand_usdhc_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_200m", "sys_pll1_133m", "sys_pll3_out", "sys_pll2_250m", "audio_pll1_out", }; -static const char * const imx8mm_usb_bus_sels[] = {"clock-osc-24m", "sys_pll2_500m", "sys_pll1_800m", +static const char * const imx8mm_usb_bus_sels[] = {"osc_24m", "sys_pll2_500m", "sys_pll1_800m", "sys_pll2_100m", "sys_pll2_200m", "clk_ext2", "clk_ext4", "audio_pll2_out", }; -static const char * const imx8mm_usdhc1_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", +static const char * const imx8mm_usdhc1_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", }; -static const char * const imx8mm_usdhc2_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", +static const char * const imx8mm_usdhc2_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", }; -static const char * const imx8mm_i2c1_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", +static const char * const imx8mm_i2c1_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out", "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", }; -static const char * const imx8mm_i2c2_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", +static const char * const imx8mm_i2c2_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out", "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", }; -static const char * const imx8mm_i2c3_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", +static const char * const imx8mm_i2c3_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out", "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", }; -static const char * const imx8mm_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", +static const char * const imx8mm_i2c4_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out", "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", }; +static const char * const imx8mm_uart1_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m", + "sys_pll2_100m", "sys_pll3_out", "clk_ext2", "clk_ext4", + "audio_pll2_out", }; + +static const char * const imx8mm_uart2_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m", + "sys_pll2_100m", "sys_pll3_out", "clk_ext2", "clk_ext3", + "audio_pll2_out", }; + +static const char * const imx8mm_uart3_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m", + "sys_pll2_100m", "sys_pll3_out", "clk_ext2", "clk_ext4", + "audio_pll2_out", }; + +static const char * const imx8mm_uart4_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m", + "sys_pll2_100m", "sys_pll3_out", "clk_ext2", "clk_ext3", + "audio_pll2_out", }; + #if CONFIG_IS_ENABLED(PCIE_DW_IMX) -static const char * const imx8mm_pcie1_ctrl_sels[] = {"clock-osc-24m", "sys_pll2_250m", "sys_pll2_200m", +static const char * const imx8mm_pcie1_ctrl_sels[] = {"osc_24m", "sys_pll2_250m", "sys_pll2_200m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_500m", "sys_pll2_333m", "sys_pll3_out", }; -static const char * const imx8mm_pcie1_phy_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll2_500m", +static const char * const imx8mm_pcie1_phy_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll2_500m", "clk_ext1", "clk_ext2", "clk_ext3", "clk_ext4", "sys_pll1_400m", }; -static const char * const imx8mm_pcie1_aux_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll2_50m", +static const char * const imx8mm_pcie1_aux_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll2_50m", "sys_pll3_out", "sys_pll2_100m", "sys_pll1_80m", "sys_pll1_160m", "sys_pll1_200m", }; #endif #ifndef CONFIG_XPL_BUILD -static const char * const imx8mm_pwm1_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", +static const char * const imx8mm_pwm1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll1_out", }; -static const char * const imx8mm_pwm2_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", +static const char * const imx8mm_pwm2_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll1_out", }; -static const char * const imx8mm_pwm3_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", +static const char * const imx8mm_pwm3_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll1_out", }; -static const char * const imx8mm_pwm4_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", +static const char * const imx8mm_pwm4_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll1_out", }; #endif -static const char * const imx8mm_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_160m", +static const char * const imx8mm_wdog_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_160m", "vpu_pll_out", "sys_pll2_125m", "sys_pll3_out", "sys_pll1_80m", "sys_pll2_166m", }; -static const char * const imx8mm_usdhc3_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", +static const char * const imx8mm_usdhc3_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m", "audio_pll2_clk", "sys_pll1_100m", }; #if CONFIG_IS_ENABLED(NXP_FSPI) -static const char * const imx8mm_qspi_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll2_333m", +static const char * const imx8mm_qspi_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll2_333m", "sys_pll2_500m", "audio_pll2_out", "sys_pll1_266m", "sys_pll3_out", "sys_pll1_100m", }; #endif -static const char * const imx8mm_usb_core_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m", +static const char * const imx8mm_usb_core_sels[] = {"osc_24m", "sys_pll1_100m", "sys_pll1_40m", "sys_pll2_100m", "sys_pll2_200m", "clk_ext2", "clk_ext3", "audio_pll2_out", }; -static const char * const imx8mm_usb_phy_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m", +static const char * const imx8mm_usb_phy_sels[] = {"osc_24m", "sys_pll1_100m", "sys_pll1_40m", "sys_pll2_100m", "sys_pll2_200m", "clk_ext2", "clk_ext3", "audio_pll2_out", }; #if CONFIG_IS_ENABLED(DM_SPI) -static const char * const imx8mm_ecspi1_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", +static const char * const imx8mm_ecspi1_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", }; -static const char * const imx8mm_ecspi2_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", +static const char * const imx8mm_ecspi2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", }; -static const char * const imx8mm_ecspi3_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", +static const char * const imx8mm_ecspi3_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", }; #endif @@ -156,19 +172,19 @@ static int imx8mm_clk_probe(struct udevice *dev) base = (void *)ANATOP_BASE_ADDR; clk_dm(IMX8MM_DRAM_PLL_REF_SEL, - imx_clk_mux("dram_pll_ref_sel", base + 0x50, 0, 2, + imx_clk_mux(dev, "dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); clk_dm(IMX8MM_ARM_PLL_REF_SEL, - imx_clk_mux("arm_pll_ref_sel", base + 0x84, 0, 2, + imx_clk_mux(dev, "arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); clk_dm(IMX8MM_SYS_PLL1_REF_SEL, - imx_clk_mux("sys_pll1_ref_sel", base + 0x94, 0, 2, + imx_clk_mux(dev, "sys_pll1_ref_sel", base + 0x94, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); clk_dm(IMX8MM_SYS_PLL2_REF_SEL, - imx_clk_mux("sys_pll2_ref_sel", base + 0x104, 0, 2, + imx_clk_mux(dev, "sys_pll2_ref_sel", base + 0x104, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); clk_dm(IMX8MM_SYS_PLL3_REF_SEL, - imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, + imx_clk_mux(dev, "sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); clk_dm(IMX8MM_DRAM_PLL, @@ -189,238 +205,254 @@ static int imx8mm_clk_probe(struct udevice *dev) /* PLL bypass out */ clk_dm(IMX8MM_DRAM_PLL_BYPASS, - imx_clk_mux_flags("dram_pll_bypass", base + 0x50, 4, 1, + imx_clk_mux_flags(dev, "dram_pll_bypass", base + 0x50, 4, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), CLK_SET_RATE_PARENT)); clk_dm(IMX8MM_ARM_PLL_BYPASS, - imx_clk_mux_flags("arm_pll_bypass", base + 0x84, 4, 1, + imx_clk_mux_flags(dev, "arm_pll_bypass", base + 0x84, 4, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT)); clk_dm(IMX8MM_SYS_PLL1_BYPASS, - imx_clk_mux_flags("sys_pll1_bypass", base + 0x94, 4, 1, + imx_clk_mux_flags(dev, "sys_pll1_bypass", base + 0x94, 4, 1, sys_pll1_bypass_sels, ARRAY_SIZE(sys_pll1_bypass_sels), CLK_SET_RATE_PARENT)); clk_dm(IMX8MM_SYS_PLL2_BYPASS, - imx_clk_mux_flags("sys_pll2_bypass", base + 0x104, 4, 1, + imx_clk_mux_flags(dev, "sys_pll2_bypass", base + 0x104, 4, 1, sys_pll2_bypass_sels, ARRAY_SIZE(sys_pll2_bypass_sels), CLK_SET_RATE_PARENT)); clk_dm(IMX8MM_SYS_PLL3_BYPASS, - imx_clk_mux_flags("sys_pll3_bypass", base + 0x114, 4, 1, + imx_clk_mux_flags(dev, "sys_pll3_bypass", base + 0x114, 4, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels), CLK_SET_RATE_PARENT)); /* PLL out gate */ clk_dm(IMX8MM_DRAM_PLL_OUT, - imx_clk_gate("dram_pll_out", "dram_pll_bypass", + imx_clk_gate(dev, "dram_pll_out", "dram_pll_bypass", base + 0x50, 13)); clk_dm(IMX8MM_ARM_PLL_OUT, - imx_clk_gate("arm_pll_out", "arm_pll_bypass", + imx_clk_gate(dev, "arm_pll_out", "arm_pll_bypass", base + 0x84, 11)); clk_dm(IMX8MM_SYS_PLL1_OUT, - imx_clk_gate("sys_pll1_out", "sys_pll1_bypass", + imx_clk_gate(dev, "sys_pll1_out", "sys_pll1_bypass", base + 0x94, 11)); clk_dm(IMX8MM_SYS_PLL2_OUT, - imx_clk_gate("sys_pll2_out", "sys_pll2_bypass", + imx_clk_gate(dev, "sys_pll2_out", "sys_pll2_bypass", base + 0x104, 11)); clk_dm(IMX8MM_SYS_PLL3_OUT, - imx_clk_gate("sys_pll3_out", "sys_pll3_bypass", + imx_clk_gate(dev, "sys_pll3_out", "sys_pll3_bypass", base + 0x114, 11)); /* SYS PLL fixed output */ clk_dm(IMX8MM_SYS_PLL1_40M, - imx_clk_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20)); + imx_clk_fixed_factor(dev, "sys_pll1_40m", "sys_pll1_out", 1, 20)); clk_dm(IMX8MM_SYS_PLL1_80M, - imx_clk_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10)); + imx_clk_fixed_factor(dev, "sys_pll1_80m", "sys_pll1_out", 1, 10)); clk_dm(IMX8MM_SYS_PLL1_100M, - imx_clk_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8)); + imx_clk_fixed_factor(dev, "sys_pll1_100m", "sys_pll1_out", 1, 8)); clk_dm(IMX8MM_SYS_PLL1_133M, - imx_clk_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6)); + imx_clk_fixed_factor(dev, "sys_pll1_133m", "sys_pll1_out", 1, 6)); clk_dm(IMX8MM_SYS_PLL1_160M, - imx_clk_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5)); + imx_clk_fixed_factor(dev, "sys_pll1_160m", "sys_pll1_out", 1, 5)); clk_dm(IMX8MM_SYS_PLL1_200M, - imx_clk_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4)); + imx_clk_fixed_factor(dev, "sys_pll1_200m", "sys_pll1_out", 1, 4)); clk_dm(IMX8MM_SYS_PLL1_266M, - imx_clk_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3)); + imx_clk_fixed_factor(dev, "sys_pll1_266m", "sys_pll1_out", 1, 3)); clk_dm(IMX8MM_SYS_PLL1_400M, - imx_clk_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2)); + imx_clk_fixed_factor(dev, "sys_pll1_400m", "sys_pll1_out", 1, 2)); clk_dm(IMX8MM_SYS_PLL1_800M, - imx_clk_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1)); + imx_clk_fixed_factor(dev, "sys_pll1_800m", "sys_pll1_out", 1, 1)); clk_dm(IMX8MM_SYS_PLL2_50M, - imx_clk_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20)); + imx_clk_fixed_factor(dev, "sys_pll2_50m", "sys_pll2_out", 1, 20)); clk_dm(IMX8MM_SYS_PLL2_100M, - imx_clk_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10)); + imx_clk_fixed_factor(dev, "sys_pll2_100m", "sys_pll2_out", 1, 10)); clk_dm(IMX8MM_SYS_PLL2_125M, - imx_clk_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8)); + imx_clk_fixed_factor(dev, "sys_pll2_125m", "sys_pll2_out", 1, 8)); clk_dm(IMX8MM_SYS_PLL2_166M, - imx_clk_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6)); + imx_clk_fixed_factor(dev, "sys_pll2_166m", "sys_pll2_out", 1, 6)); clk_dm(IMX8MM_SYS_PLL2_200M, - imx_clk_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5)); + imx_clk_fixed_factor(dev, "sys_pll2_200m", "sys_pll2_out", 1, 5)); clk_dm(IMX8MM_SYS_PLL2_250M, - imx_clk_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4)); + imx_clk_fixed_factor(dev, "sys_pll2_250m", "sys_pll2_out", 1, 4)); clk_dm(IMX8MM_SYS_PLL2_333M, - imx_clk_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3)); + imx_clk_fixed_factor(dev, "sys_pll2_333m", "sys_pll2_out", 1, 3)); clk_dm(IMX8MM_SYS_PLL2_500M, - imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2)); + imx_clk_fixed_factor(dev, "sys_pll2_500m", "sys_pll2_out", 1, 2)); clk_dm(IMX8MM_SYS_PLL2_1000M, - imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1)); + imx_clk_fixed_factor(dev, "sys_pll2_1000m", "sys_pll2_out", 1, 1)); base = dev_read_addr_ptr(dev); if (!base) return -EINVAL; clk_dm(IMX8MM_CLK_A53_SRC, - imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3, + imx_clk_mux2(dev, "arm_a53_src", base + 0x8000, 24, 3, imx8mm_a53_sels, ARRAY_SIZE(imx8mm_a53_sels))); clk_dm(IMX8MM_CLK_A53_CG, - imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28)); + imx_clk_gate3(dev, "arm_a53_cg", "arm_a53_src", base + 0x8000, 28)); clk_dm(IMX8MM_CLK_A53_DIV, - imx_clk_divider2("arm_a53_div", "arm_a53_cg", + imx_clk_divider2(dev, "arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3)); clk_dm(IMX8MM_CLK_AHB, - imx8m_clk_composite_critical("ahb", imx8mm_ahb_sels, + imx8m_clk_composite_critical(dev, "ahb", imx8mm_ahb_sels, base + 0x9000)); clk_dm(IMX8MM_CLK_IPG_ROOT, - imx_clk_divider2("ipg_root", "ahb", base + 0x9080, 0, 1)); + imx_clk_divider2(dev, "ipg_root", "ahb", base + 0x9080, 0, 1)); clk_dm(IMX8MM_CLK_NAND_USDHC_BUS, - imx8m_clk_composite_critical("nand_usdhc_bus", + imx8m_clk_composite_critical(dev, "nand_usdhc_bus", imx8mm_nand_usdhc_sels, base + 0x8900)); clk_dm(IMX8MM_CLK_USB_BUS, - imx8m_clk_composite("usb_bus", imx8mm_usb_bus_sels, base + 0x8b80)); + imx8m_clk_composite(dev, "usb_bus", imx8mm_usb_bus_sels, base + 0x8b80)); /* IP */ #if CONFIG_IS_ENABLED(PCIE_DW_IMX) clk_dm(IMX8MM_CLK_PCIE1_CTRL, - imx8m_clk_composite("pcie1_ctrl", imx8mm_pcie1_ctrl_sels, + imx8m_clk_composite(dev, "pcie1_ctrl", imx8mm_pcie1_ctrl_sels, base + 0xa300)); clk_dm(IMX8MM_CLK_PCIE1_PHY, - imx8m_clk_composite("pcie1_phy", imx8mm_pcie1_phy_sels, + imx8m_clk_composite(dev, "pcie1_phy", imx8mm_pcie1_phy_sels, base + 0xa380)); clk_dm(IMX8MM_CLK_PCIE1_AUX, - imx8m_clk_composite("pcie1_aux", imx8mm_pcie1_aux_sels, + imx8m_clk_composite(dev, "pcie1_aux", imx8mm_pcie1_aux_sels, base + 0xa400)); #endif clk_dm(IMX8MM_CLK_USDHC1, - imx8m_clk_composite("usdhc1", imx8mm_usdhc1_sels, + imx8m_clk_composite(dev, "usdhc1", imx8mm_usdhc1_sels, base + 0xac00)); clk_dm(IMX8MM_CLK_USDHC2, - imx8m_clk_composite("usdhc2", imx8mm_usdhc2_sels, + imx8m_clk_composite(dev, "usdhc2", imx8mm_usdhc2_sels, base + 0xac80)); clk_dm(IMX8MM_CLK_I2C1, - imx8m_clk_composite("i2c1", imx8mm_i2c1_sels, base + 0xad00)); + imx8m_clk_composite(dev, "i2c1", imx8mm_i2c1_sels, base + 0xad00)); clk_dm(IMX8MM_CLK_I2C2, - imx8m_clk_composite("i2c2", imx8mm_i2c2_sels, base + 0xad80)); + imx8m_clk_composite(dev, "i2c2", imx8mm_i2c2_sels, base + 0xad80)); clk_dm(IMX8MM_CLK_I2C3, - imx8m_clk_composite("i2c3", imx8mm_i2c3_sels, base + 0xae00)); + imx8m_clk_composite(dev, "i2c3", imx8mm_i2c3_sels, base + 0xae00)); clk_dm(IMX8MM_CLK_I2C4, - imx8m_clk_composite("i2c4", imx8mm_i2c4_sels, base + 0xae80)); + imx8m_clk_composite(dev, "i2c4", imx8mm_i2c4_sels, base + 0xae80)); + clk_dm(IMX8MM_CLK_UART1, + imx8m_clk_composite(dev, "uart1", imx8mm_uart1_sels, base + 0xaf00)); + clk_dm(IMX8MM_CLK_UART2, + imx8m_clk_composite(dev, "uart2", imx8mm_uart2_sels, base + 0xaf80)); + clk_dm(IMX8MM_CLK_UART3, + imx8m_clk_composite(dev, "uart3", imx8mm_uart3_sels, base + 0xb000)); + clk_dm(IMX8MM_CLK_UART4, + imx8m_clk_composite(dev, "uart4", imx8mm_uart4_sels, base + 0xb080)); + clk_dm(IMX8MM_CLK_UART1_ROOT, + imx_clk_gate4(dev, "uart1_root_clk", "uart1", base + 0x4490, 0)); + clk_dm(IMX8MM_CLK_UART2_ROOT, + imx_clk_gate4(dev, "uart2_root_clk", "uart2", base + 0x44a0, 0)); + clk_dm(IMX8MM_CLK_UART3_ROOT, + imx_clk_gate4(dev, "uart3_root_clk", "uart3", base + 0x44b0, 0)); + clk_dm(IMX8MM_CLK_UART4_ROOT, + imx_clk_gate4(dev, "uart4_root_clk", "uart4", base + 0x44c0, 0)); clk_dm(IMX8MM_CLK_WDOG, - imx8m_clk_composite("wdog", imx8mm_wdog_sels, base + 0xb900)); + imx8m_clk_composite(dev, "wdog", imx8mm_wdog_sels, base + 0xb900)); clk_dm(IMX8MM_CLK_USDHC3, - imx8m_clk_composite("usdhc3", imx8mm_usdhc3_sels, + imx8m_clk_composite(dev, "usdhc3", imx8mm_usdhc3_sels, base + 0xbc80)); clk_dm(IMX8MM_CLK_USB_CORE_REF, - imx8m_clk_composite("usb_core_ref", imx8mm_usb_core_sels, base + 0xb100)); + imx8m_clk_composite(dev, "usb_core_ref", imx8mm_usb_core_sels, base + 0xb100)); clk_dm(IMX8MM_CLK_USB_PHY_REF, - imx8m_clk_composite("usb_phy_ref", imx8mm_usb_phy_sels, base + 0xb180)); + imx8m_clk_composite(dev, "usb_phy_ref", imx8mm_usb_phy_sels, base + 0xb180)); clk_dm(IMX8MM_CLK_I2C1_ROOT, - imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0)); + imx_clk_gate4(dev, "i2c1_root_clk", "i2c1", base + 0x4170, 0)); clk_dm(IMX8MM_CLK_I2C2_ROOT, - imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0)); + imx_clk_gate4(dev, "i2c2_root_clk", "i2c2", base + 0x4180, 0)); clk_dm(IMX8MM_CLK_I2C3_ROOT, - imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0)); + imx_clk_gate4(dev, "i2c3_root_clk", "i2c3", base + 0x4190, 0)); clk_dm(IMX8MM_CLK_I2C4_ROOT, - imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0)); + imx_clk_gate4(dev, "i2c4_root_clk", "i2c4", base + 0x41a0, 0)); clk_dm(IMX8MM_CLK_OCOTP_ROOT, - imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0)); + imx_clk_gate4(dev, "ocotp_root_clk", "ipg_root", base + 0x4220, 0)); clk_dm(IMX8MM_CLK_USDHC1_ROOT, - imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0)); + imx_clk_gate4(dev, "usdhc1_root_clk", "usdhc1", base + 0x4510, 0)); clk_dm(IMX8MM_CLK_USDHC2_ROOT, - imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0)); + imx_clk_gate4(dev, "usdhc2_root_clk", "usdhc2", base + 0x4520, 0)); clk_dm(IMX8MM_CLK_WDOG1_ROOT, - imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0)); + imx_clk_gate4(dev, "wdog1_root_clk", "wdog", base + 0x4530, 0)); clk_dm(IMX8MM_CLK_WDOG2_ROOT, - imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0)); + imx_clk_gate4(dev, "wdog2_root_clk", "wdog", base + 0x4540, 0)); clk_dm(IMX8MM_CLK_WDOG3_ROOT, - imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0)); + imx_clk_gate4(dev, "wdog3_root_clk", "wdog", base + 0x4550, 0)); clk_dm(IMX8MM_CLK_USDHC3_ROOT, - imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0)); + imx_clk_gate4(dev, "usdhc3_root_clk", "usdhc3", base + 0x45e0, 0)); clk_dm(IMX8MM_CLK_USB1_CTRL_ROOT, - imx_clk_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0)); + imx_clk_gate4(dev, "usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0)); /* clks not needed in SPL stage */ #ifndef CONFIG_XPL_BUILD clk_dm(IMX8MM_CLK_ENET_AXI, - imx8m_clk_composite("enet_axi", imx8mm_enet_axi_sels, + imx8m_clk_composite(dev, "enet_axi", imx8mm_enet_axi_sels, base + 0x8880)); clk_dm(IMX8MM_CLK_ENET_REF, - imx8m_clk_composite("enet_ref", imx8mm_enet_ref_sels, + imx8m_clk_composite(dev, "enet_ref", imx8mm_enet_ref_sels, base + 0xa980)); clk_dm(IMX8MM_CLK_ENET_TIMER, - imx8m_clk_composite("enet_timer", imx8mm_enet_timer_sels, + imx8m_clk_composite(dev, "enet_timer", imx8mm_enet_timer_sels, base + 0xaa00)); clk_dm(IMX8MM_CLK_ENET_PHY_REF, - imx8m_clk_composite("enet_phy", imx8mm_enet_phy_sels, + imx8m_clk_composite(dev, "enet_phy", imx8mm_enet_phy_sels, base + 0xaa80)); clk_dm(IMX8MM_CLK_ENET1_ROOT, - imx_clk_gate4("enet1_root_clk", "enet_axi", + imx_clk_gate4(dev, "enet1_root_clk", "enet_axi", base + 0x40a0, 0)); clk_dm(IMX8MM_CLK_PWM1, - imx8m_clk_composite("pwm1", imx8mm_pwm1_sels, base + 0xb380)); + imx8m_clk_composite(dev, "pwm1", imx8mm_pwm1_sels, base + 0xb380)); clk_dm(IMX8MM_CLK_PWM2, - imx8m_clk_composite("pwm2", imx8mm_pwm2_sels, base + 0xb400)); + imx8m_clk_composite(dev, "pwm2", imx8mm_pwm2_sels, base + 0xb400)); clk_dm(IMX8MM_CLK_PWM3, - imx8m_clk_composite("pwm3", imx8mm_pwm3_sels, base + 0xb480)); + imx8m_clk_composite(dev, "pwm3", imx8mm_pwm3_sels, base + 0xb480)); clk_dm(IMX8MM_CLK_PWM4, - imx8m_clk_composite("pwm4", imx8mm_pwm4_sels, base + 0xb500)); + imx8m_clk_composite(dev, "pwm4", imx8mm_pwm4_sels, base + 0xb500)); clk_dm(IMX8MM_CLK_PWM1_ROOT, - imx_clk_gate4("pwm1_root_clk", "pwm1", base + 0x4280, 0)); + imx_clk_gate4(dev, "pwm1_root_clk", "pwm1", base + 0x4280, 0)); clk_dm(IMX8MM_CLK_PWM2_ROOT, - imx_clk_gate4("pwm2_root_clk", "pwm2", base + 0x4290, 0)); + imx_clk_gate4(dev, "pwm2_root_clk", "pwm2", base + 0x4290, 0)); clk_dm(IMX8MM_CLK_PWM3_ROOT, - imx_clk_gate4("pwm3_root_clk", "pwm3", base + 0x42a0, 0)); + imx_clk_gate4(dev, "pwm3_root_clk", "pwm3", base + 0x42a0, 0)); clk_dm(IMX8MM_CLK_PWM4_ROOT, - imx_clk_gate4("pwm4_root_clk", "pwm4", base + 0x42b0, 0)); + imx_clk_gate4(dev, "pwm4_root_clk", "pwm4", base + 0x42b0, 0)); #endif #if CONFIG_IS_ENABLED(PCIE_DW_IMX) clk_dm(IMX8MM_CLK_PCIE1_ROOT, - imx_clk_gate4("pcie1_root_clk", "pcie1_ctrl", base + 0x4250, 0)); + imx_clk_gate4(dev, "pcie1_root_clk", "pcie1_ctrl", base + 0x4250, 0)); #endif #if CONFIG_IS_ENABLED(DM_SPI) clk_dm(IMX8MM_CLK_ECSPI1, - imx8m_clk_composite("ecspi1", imx8mm_ecspi1_sels, base + 0xb280)); + imx8m_clk_composite(dev, "ecspi1", imx8mm_ecspi1_sels, base + 0xb280)); clk_dm(IMX8MM_CLK_ECSPI2, - imx8m_clk_composite("ecspi2", imx8mm_ecspi2_sels, base + 0xb300)); + imx8m_clk_composite(dev, "ecspi2", imx8mm_ecspi2_sels, base + 0xb300)); clk_dm(IMX8MM_CLK_ECSPI3, - imx8m_clk_composite("ecspi3", imx8mm_ecspi3_sels, base + 0xc180)); + imx8m_clk_composite(dev, "ecspi3", imx8mm_ecspi3_sels, base + 0xc180)); clk_dm(IMX8MM_CLK_ECSPI1_ROOT, - imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0)); + imx_clk_gate4(dev, "ecspi1_root_clk", "ecspi1", base + 0x4070, 0)); clk_dm(IMX8MM_CLK_ECSPI2_ROOT, - imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0)); + imx_clk_gate4(dev, "ecspi2_root_clk", "ecspi2", base + 0x4080, 0)); clk_dm(IMX8MM_CLK_ECSPI3_ROOT, - imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0)); + imx_clk_gate4(dev, "ecspi3_root_clk", "ecspi3", base + 0x4090, 0)); #endif #if CONFIG_IS_ENABLED(NXP_FSPI) clk_dm(IMX8MM_CLK_QSPI, - imx8m_clk_composite("qspi", imx8mm_qspi_sels, base + 0xab80)); + imx8m_clk_composite(dev, "qspi", imx8mm_qspi_sels, base + 0xab80)); clk_dm(IMX8MM_CLK_QSPI_ROOT, - imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0)); + imx_clk_gate4(dev, "qspi_root_clk", "qspi", base + 0x42f0, 0)); #endif clk_dm(IMX8MM_CLK_ARM, - imx_clk_mux2_flags("arm_core", base + 0x9880, 24, 1, + imx_clk_mux2_flags(dev, "arm_core", base + 0x9880, 24, 1, imx8mm_arm_core_sels, ARRAY_SIZE(imx8mm_arm_core_sels), CLK_IS_CRITICAL)); diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index be15ebd0e25..be5b7933a8d 100644 --- a/drivers/clk/imx/clk-imx8mn.c +++ b/drivers/clk/imx/clk-imx8mn.c @@ -16,7 +16,7 @@ static u32 share_count_nand; -static const char * const pll_ref_sels[] = { "clock-osc-24m", "dummy", "dummy", "dummy", }; +static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", }; static const char * const dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", }; static const char * const arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", }; static const char * const sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", }; @@ -25,117 +25,133 @@ static const char * const sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_se static const char * const imx8mn_arm_core_sels[] = {"arm_a53_src", "arm_pll_out", }; -static const char * const imx8mn_a53_sels[] = {"clock-osc-24m", "arm_pll_out", "sys_pll2_500m", +static const char * const imx8mn_a53_sels[] = {"osc_24m", "arm_pll_out", "sys_pll2_500m", "sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m", "audio_pll1_out", "sys_pll3_out", }; -static const char * const imx8mn_ahb_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_800m", +static const char * const imx8mn_ahb_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_800m", "sys_pll1_400m", "sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", "video_pll_out", }; -static const char * const imx8mn_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", +static const char * const imx8mn_enet_axi_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_250m", "sys_pll2_200m", "audio_pll1_out", "video_pll_out", "sys_pll3_out", }; #ifndef CONFIG_XPL_BUILD -static const char * const imx8mn_enet_ref_sels[] = {"clock-osc-24m", "sys_pll2_125m", "sys_pll2_50m", +static const char * const imx8mn_enet_ref_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_50m", "sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out", "video_pll_out", "clk_ext4", }; -static const char * const imx8mn_enet_timer_sels[] = {"clock-osc-24m", "sys_pll2_100m", "audio_pll1_out", +static const char * const imx8mn_enet_timer_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_out", "clk_ext1", "clk_ext2", "clk_ext3", "clk_ext4", "video_pll_out", }; -static const char * const imx8mn_enet_phy_sels[] = {"clock-osc-24m", "sys_pll2_50m", "sys_pll2_125m", +static const char * const imx8mn_enet_phy_sels[] = {"osc_24m", "sys_pll2_50m", "sys_pll2_125m", "sys_pll2_200m", "sys_pll2_500m", "audio_pll1_out", "video_pll_out", "audio_pll2_out", }; #endif -static const char * const imx8mn_nand_usdhc_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", +static const char * const imx8mn_nand_usdhc_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_200m", "sys_pll1_133m", "sys_pll3_out", "sys_pll2_250m", "audio_pll1_out", }; -static const char * const imx8mn_usb_bus_sels[] = {"clock-osc-24m", "sys_pll2_500m", "sys_pll1_800m", +static const char * const imx8mn_usb_bus_sels[] = {"osc_24m", "sys_pll2_500m", "sys_pll1_800m", "sys_pll2_100m", "sys_pll2_200m", "clk_ext2", "clk_ext4", "audio_pll2_out", }; -static const char * const imx8mn_usdhc1_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", +static const char * const imx8mn_usdhc1_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", }; -static const char * const imx8mn_usdhc2_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", +static const char * const imx8mn_usdhc2_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", }; #if CONFIG_IS_ENABLED(DM_SPI) -static const char * const imx8mn_ecspi1_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", +static const char * const imx8mn_ecspi1_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", }; -static const char * const imx8mn_ecspi2_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", +static const char * const imx8mn_ecspi2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", }; -static const char * const imx8mn_ecspi3_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", +static const char * const imx8mn_ecspi3_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", }; #endif -static const char * const imx8mn_i2c1_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", +static const char * const imx8mn_i2c1_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out", "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; -static const char * const imx8mn_i2c2_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", +static const char * const imx8mn_i2c2_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out", "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; -static const char * const imx8mn_i2c3_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", +static const char * const imx8mn_i2c3_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out", "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; -static const char * const imx8mn_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", +static const char * const imx8mn_i2c4_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out", "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; +static const char * const imx8mn_uart1_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m", + "sys_pll2_100m", "sys_pll3_out", "clk_ext2", + "clk_ext4", "audio_pll2_out", }; + +static const char * const imx8mn_uart2_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m", + "sys_pll2_100m", "sys_pll3_out", "clk_ext2", + "clk_ext3", "audio_pll2_out", }; + +static const char * const imx8mn_uart3_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m", + "sys_pll2_100m", "sys_pll3_out", "clk_ext2", + "clk_ext4", "audio_pll2_out", }; + +static const char * const imx8mn_uart4_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m", + "sys_pll2_100m", "sys_pll3_out", "clk_ext2", + "clk_ext3", "audio_pll2_out", }; + #ifndef CONFIG_XPL_BUILD -static const char * const imx8mn_pwm1_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", +static const char * const imx8mn_pwm1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll_out", }; -static const char * const imx8mn_pwm2_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", +static const char * const imx8mn_pwm2_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll_out", }; -static const char * const imx8mn_pwm3_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", +static const char * const imx8mn_pwm3_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll_out", }; -static const char * const imx8mn_pwm4_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", +static const char * const imx8mn_pwm4_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll_out", }; #endif -static const char * const imx8mn_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_160m", +static const char * const imx8mn_wdog_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_160m", "m7_alt_pll", "sys_pll2_125m", "sys_pll3_out", "sys_pll1_80m", "sys_pll2_166m", }; -static const char * const imx8mn_usdhc3_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", +static const char * const imx8mn_usdhc3_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m", "audio_pll2_clk", "sys_pll1_100m", }; -static const char * const imx8mn_qspi_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll2_333m", +static const char * const imx8mn_qspi_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll2_333m", "sys_pll2_500m", "audio_pll2_out", "sys_pll1_266m", "sys_pll3_out", "sys_pll1_100m", }; -static const char * const imx8mn_nand_sels[] = {"clock-osc-24m", "sys_pll2_500m", "audio_pll1_out", +static const char * const imx8mn_nand_sels[] = {"osc_24m", "sys_pll2_500m", "audio_pll1_out", "sys_pll1_400m", "audio_pll2_out", "sys_pll3_out", "sys_pll2_250m", "video_pll_out", }; -static const char * const imx8mn_usb_core_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m", +static const char * const imx8mn_usb_core_sels[] = {"osc_24m", "sys_pll1_100m", "sys_pll1_40m", "sys_pll2_100m", "sys_pll2_200m", "clk_ext2", "clk_ext3", "audio_pll2_out", }; -static const char * const imx8mn_usb_phy_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m", +static const char * const imx8mn_usb_phy_sels[] = {"osc_24m", "sys_pll1_100m", "sys_pll1_40m", "sys_pll2_100m", "sys_pll2_200m", "clk_ext2", "clk_ext3", "audio_pll2_out", }; @@ -148,19 +164,19 @@ static int imx8mn_clk_probe(struct udevice *dev) base = (void *)ANATOP_BASE_ADDR; clk_dm(IMX8MN_DRAM_PLL_REF_SEL, - imx_clk_mux("dram_pll_ref_sel", base + 0x50, 0, 2, + imx_clk_mux(dev, "dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); clk_dm(IMX8MN_ARM_PLL_REF_SEL, - imx_clk_mux("arm_pll_ref_sel", base + 0x84, 0, 2, + imx_clk_mux(dev, "arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); clk_dm(IMX8MN_SYS_PLL1_REF_SEL, - imx_clk_mux("sys_pll1_ref_sel", base + 0x94, 0, 2, + imx_clk_mux(dev, "sys_pll1_ref_sel", base + 0x94, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); clk_dm(IMX8MN_SYS_PLL2_REF_SEL, - imx_clk_mux("sys_pll2_ref_sel", base + 0x104, 0, 2, + imx_clk_mux(dev, "sys_pll2_ref_sel", base + 0x104, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); clk_dm(IMX8MN_SYS_PLL3_REF_SEL, - imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, + imx_clk_mux(dev, "sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); clk_dm(IMX8MN_DRAM_PLL, @@ -181,86 +197,86 @@ static int imx8mn_clk_probe(struct udevice *dev) /* PLL bypass out */ clk_dm(IMX8MN_DRAM_PLL_BYPASS, - imx_clk_mux_flags("dram_pll_bypass", base + 0x50, 4, 1, + imx_clk_mux_flags(dev, "dram_pll_bypass", base + 0x50, 4, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), CLK_SET_RATE_PARENT)); clk_dm(IMX8MN_ARM_PLL_BYPASS, - imx_clk_mux_flags("arm_pll_bypass", base + 0x84, 4, 1, + imx_clk_mux_flags(dev, "arm_pll_bypass", base + 0x84, 4, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT)); clk_dm(IMX8MN_SYS_PLL1_BYPASS, - imx_clk_mux_flags("sys_pll1_bypass", base + 0x94, 4, 1, + imx_clk_mux_flags(dev, "sys_pll1_bypass", base + 0x94, 4, 1, sys_pll1_bypass_sels, ARRAY_SIZE(sys_pll1_bypass_sels), CLK_SET_RATE_PARENT)); clk_dm(IMX8MN_SYS_PLL2_BYPASS, - imx_clk_mux_flags("sys_pll2_bypass", base + 0x104, 4, 1, + imx_clk_mux_flags(dev, "sys_pll2_bypass", base + 0x104, 4, 1, sys_pll2_bypass_sels, ARRAY_SIZE(sys_pll2_bypass_sels), CLK_SET_RATE_PARENT)); clk_dm(IMX8MN_SYS_PLL3_BYPASS, - imx_clk_mux_flags("sys_pll3_bypass", base + 0x114, 4, 1, + imx_clk_mux_flags(dev, "sys_pll3_bypass", base + 0x114, 4, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels), CLK_SET_RATE_PARENT)); /* PLL out gate */ clk_dm(IMX8MN_DRAM_PLL_OUT, - imx_clk_gate("dram_pll_out", "dram_pll_bypass", + imx_clk_gate(dev, "dram_pll_out", "dram_pll_bypass", base + 0x50, 13)); clk_dm(IMX8MN_ARM_PLL_OUT, - imx_clk_gate("arm_pll_out", "arm_pll_bypass", + imx_clk_gate(dev, "arm_pll_out", "arm_pll_bypass", base + 0x84, 11)); clk_dm(IMX8MN_SYS_PLL1_OUT, - imx_clk_gate("sys_pll1_out", "sys_pll1_bypass", + imx_clk_gate(dev, "sys_pll1_out", "sys_pll1_bypass", base + 0x94, 11)); clk_dm(IMX8MN_SYS_PLL2_OUT, - imx_clk_gate("sys_pll2_out", "sys_pll2_bypass", + imx_clk_gate(dev, "sys_pll2_out", "sys_pll2_bypass", base + 0x104, 11)); clk_dm(IMX8MN_SYS_PLL3_OUT, - imx_clk_gate("sys_pll3_out", "sys_pll3_bypass", + imx_clk_gate(dev, "sys_pll3_out", "sys_pll3_bypass", base + 0x114, 11)); /* SYS PLL fixed output */ clk_dm(IMX8MN_SYS_PLL1_40M, - imx_clk_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20)); + imx_clk_fixed_factor(dev, "sys_pll1_40m", "sys_pll1_out", 1, 20)); clk_dm(IMX8MN_SYS_PLL1_80M, - imx_clk_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10)); + imx_clk_fixed_factor(dev, "sys_pll1_80m", "sys_pll1_out", 1, 10)); clk_dm(IMX8MN_SYS_PLL1_100M, - imx_clk_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8)); + imx_clk_fixed_factor(dev, "sys_pll1_100m", "sys_pll1_out", 1, 8)); clk_dm(IMX8MN_SYS_PLL1_133M, - imx_clk_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6)); + imx_clk_fixed_factor(dev, "sys_pll1_133m", "sys_pll1_out", 1, 6)); clk_dm(IMX8MN_SYS_PLL1_160M, - imx_clk_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5)); + imx_clk_fixed_factor(dev, "sys_pll1_160m", "sys_pll1_out", 1, 5)); clk_dm(IMX8MN_SYS_PLL1_200M, - imx_clk_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4)); + imx_clk_fixed_factor(dev, "sys_pll1_200m", "sys_pll1_out", 1, 4)); clk_dm(IMX8MN_SYS_PLL1_266M, - imx_clk_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3)); + imx_clk_fixed_factor(dev, "sys_pll1_266m", "sys_pll1_out", 1, 3)); clk_dm(IMX8MN_SYS_PLL1_400M, - imx_clk_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2)); + imx_clk_fixed_factor(dev, "sys_pll1_400m", "sys_pll1_out", 1, 2)); clk_dm(IMX8MN_SYS_PLL1_800M, - imx_clk_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1)); + imx_clk_fixed_factor(dev, "sys_pll1_800m", "sys_pll1_out", 1, 1)); clk_dm(IMX8MN_SYS_PLL2_50M, - imx_clk_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20)); + imx_clk_fixed_factor(dev, "sys_pll2_50m", "sys_pll2_out", 1, 20)); clk_dm(IMX8MN_SYS_PLL2_100M, - imx_clk_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10)); + imx_clk_fixed_factor(dev, "sys_pll2_100m", "sys_pll2_out", 1, 10)); clk_dm(IMX8MN_SYS_PLL2_125M, - imx_clk_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8)); + imx_clk_fixed_factor(dev, "sys_pll2_125m", "sys_pll2_out", 1, 8)); clk_dm(IMX8MN_SYS_PLL2_166M, - imx_clk_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6)); + imx_clk_fixed_factor(dev, "sys_pll2_166m", "sys_pll2_out", 1, 6)); clk_dm(IMX8MN_SYS_PLL2_200M, - imx_clk_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5)); + imx_clk_fixed_factor(dev, "sys_pll2_200m", "sys_pll2_out", 1, 5)); clk_dm(IMX8MN_SYS_PLL2_250M, - imx_clk_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4)); + imx_clk_fixed_factor(dev, "sys_pll2_250m", "sys_pll2_out", 1, 4)); clk_dm(IMX8MN_SYS_PLL2_333M, - imx_clk_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3)); + imx_clk_fixed_factor(dev, "sys_pll2_333m", "sys_pll2_out", 1, 3)); clk_dm(IMX8MN_SYS_PLL2_500M, - imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2)); + imx_clk_fixed_factor(dev, "sys_pll2_500m", "sys_pll2_out", 1, 2)); clk_dm(IMX8MN_SYS_PLL2_1000M, - imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1)); + imx_clk_fixed_factor(dev, "sys_pll2_1000m", "sys_pll2_out", 1, 1)); ret = clk_get_by_name(dev, "osc_24m", &osc_24m_clk); if (ret) @@ -272,141 +288,157 @@ static int imx8mn_clk_probe(struct udevice *dev) return -EINVAL; clk_dm(IMX8MN_CLK_A53_SRC, - imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3, + imx_clk_mux2(dev, "arm_a53_src", base + 0x8000, 24, 3, imx8mn_a53_sels, ARRAY_SIZE(imx8mn_a53_sels))); clk_dm(IMX8MN_CLK_A53_CG, - imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28)); + imx_clk_gate3(dev, "arm_a53_cg", "arm_a53_src", base + 0x8000, 28)); clk_dm(IMX8MN_CLK_A53_DIV, - imx_clk_divider2("arm_a53_div", "arm_a53_cg", + imx_clk_divider2(dev, "arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3)); clk_dm(IMX8MN_CLK_AHB, - imx8m_clk_composite_critical("ahb", imx8mn_ahb_sels, + imx8m_clk_composite_critical(dev, "ahb", imx8mn_ahb_sels, base + 0x9000)); clk_dm(IMX8MN_CLK_IPG_ROOT, - imx_clk_divider2("ipg_root", "ahb", base + 0x9080, 0, 1)); + imx_clk_divider2(dev, "ipg_root", "ahb", base + 0x9080, 0, 1)); clk_dm(IMX8MN_CLK_ENET_AXI, - imx8m_clk_composite("enet_axi", imx8mn_enet_axi_sels, + imx8m_clk_composite(dev, "enet_axi", imx8mn_enet_axi_sels, base + 0x8880)); clk_dm(IMX8MN_CLK_NAND_USDHC_BUS, - imx8m_clk_composite_critical("nand_usdhc_bus", + imx8m_clk_composite_critical(dev, "nand_usdhc_bus", imx8mn_nand_usdhc_sels, base + 0x8900)); clk_dm(IMX8MN_CLK_USB_BUS, - imx8m_clk_composite("usb_bus", imx8mn_usb_bus_sels, base + 0x8b80)); + imx8m_clk_composite(dev, "usb_bus", imx8mn_usb_bus_sels, base + 0x8b80)); /* IP */ clk_dm(IMX8MN_CLK_USDHC1, - imx8m_clk_composite("usdhc1", imx8mn_usdhc1_sels, + imx8m_clk_composite(dev, "usdhc1", imx8mn_usdhc1_sels, base + 0xac00)); clk_dm(IMX8MN_CLK_USDHC2, - imx8m_clk_composite("usdhc2", imx8mn_usdhc2_sels, + imx8m_clk_composite(dev, "usdhc2", imx8mn_usdhc2_sels, base + 0xac80)); clk_dm(IMX8MN_CLK_I2C1, - imx8m_clk_composite("i2c1", imx8mn_i2c1_sels, base + 0xad00)); + imx8m_clk_composite(dev, "i2c1", imx8mn_i2c1_sels, base + 0xad00)); clk_dm(IMX8MN_CLK_I2C2, - imx8m_clk_composite("i2c2", imx8mn_i2c2_sels, base + 0xad80)); + imx8m_clk_composite(dev, "i2c2", imx8mn_i2c2_sels, base + 0xad80)); clk_dm(IMX8MN_CLK_I2C3, - imx8m_clk_composite("i2c3", imx8mn_i2c3_sels, base + 0xae00)); + imx8m_clk_composite(dev, "i2c3", imx8mn_i2c3_sels, base + 0xae00)); clk_dm(IMX8MN_CLK_I2C4, - imx8m_clk_composite("i2c4", imx8mn_i2c4_sels, base + 0xae80)); + imx8m_clk_composite(dev, "i2c4", imx8mn_i2c4_sels, base + 0xae80)); + clk_dm(IMX8MN_CLK_UART1, + imx8m_clk_composite(dev, "uart1", imx8mn_uart1_sels, base + 0xaf00)); + clk_dm(IMX8MN_CLK_UART2, + imx8m_clk_composite(dev, "uart2", imx8mn_uart2_sels, base + 0xaf80)); + clk_dm(IMX8MN_CLK_UART3, + imx8m_clk_composite(dev, "uart3", imx8mn_uart3_sels, base + 0xb000)); + clk_dm(IMX8MN_CLK_UART4, + imx8m_clk_composite(dev, "uart4", imx8mn_uart4_sels, base + 0xb080)); clk_dm(IMX8MN_CLK_WDOG, - imx8m_clk_composite("wdog", imx8mn_wdog_sels, base + 0xb900)); + imx8m_clk_composite(dev, "wdog", imx8mn_wdog_sels, base + 0xb900)); clk_dm(IMX8MN_CLK_USDHC3, - imx8m_clk_composite("usdhc3", imx8mn_usdhc3_sels, + imx8m_clk_composite(dev, "usdhc3", imx8mn_usdhc3_sels, base + 0xbc80)); clk_dm(IMX8MN_CLK_NAND, - imx8m_clk_composite("nand", imx8mn_nand_sels, base + 0xab00)); + imx8m_clk_composite(dev, "nand", imx8mn_nand_sels, base + 0xab00)); clk_dm(IMX8MN_CLK_QSPI, - imx8m_clk_composite("qspi", imx8mn_qspi_sels, base + 0xab80)); + imx8m_clk_composite(dev, "qspi", imx8mn_qspi_sels, base + 0xab80)); clk_dm(IMX8MN_CLK_USB_CORE_REF, - imx8m_clk_composite("usb_core_ref", imx8mn_usb_core_sels, base + 0xb100)); + imx8m_clk_composite(dev, "usb_core_ref", imx8mn_usb_core_sels, base + 0xb100)); clk_dm(IMX8MN_CLK_USB_PHY_REF, - imx8m_clk_composite("usb_phy_ref", imx8mn_usb_phy_sels, base + 0xb180)); + imx8m_clk_composite(dev, "usb_phy_ref", imx8mn_usb_phy_sels, base + 0xb180)); clk_dm(IMX8MN_CLK_I2C1_ROOT, - imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0)); + imx_clk_gate4(dev, "i2c1_root_clk", "i2c1", base + 0x4170, 0)); clk_dm(IMX8MN_CLK_I2C2_ROOT, - imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0)); + imx_clk_gate4(dev, "i2c2_root_clk", "i2c2", base + 0x4180, 0)); clk_dm(IMX8MN_CLK_I2C3_ROOT, - imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0)); + imx_clk_gate4(dev, "i2c3_root_clk", "i2c3", base + 0x4190, 0)); clk_dm(IMX8MN_CLK_I2C4_ROOT, - imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0)); + imx_clk_gate4(dev, "i2c4_root_clk", "i2c4", base + 0x41a0, 0)); clk_dm(IMX8MN_CLK_OCOTP_ROOT, - imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0)); + imx_clk_gate4(dev, "ocotp_root_clk", "ipg_root", base + 0x4220, 0)); clk_dm(IMX8MN_CLK_USDHC1_ROOT, - imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0)); + imx_clk_gate4(dev, "usdhc1_root_clk", "usdhc1", base + 0x4510, 0)); clk_dm(IMX8MN_CLK_USDHC2_ROOT, - imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0)); + imx_clk_gate4(dev, "usdhc2_root_clk", "usdhc2", base + 0x4520, 0)); clk_dm(IMX8MN_CLK_WDOG1_ROOT, - imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0)); + imx_clk_gate4(dev, "wdog1_root_clk", "wdog", base + 0x4530, 0)); clk_dm(IMX8MN_CLK_WDOG2_ROOT, - imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0)); + imx_clk_gate4(dev, "wdog2_root_clk", "wdog", base + 0x4540, 0)); clk_dm(IMX8MN_CLK_WDOG3_ROOT, - imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0)); + imx_clk_gate4(dev, "wdog3_root_clk", "wdog", base + 0x4550, 0)); clk_dm(IMX8MN_CLK_USDHC3_ROOT, - imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0)); + imx_clk_gate4(dev, "usdhc3_root_clk", "usdhc3", base + 0x45e0, 0)); clk_dm(IMX8MN_CLK_QSPI_ROOT, - imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0)); + imx_clk_gate4(dev, "qspi_root_clk", "qspi", base + 0x42f0, 0)); clk_dm(IMX8MN_CLK_NAND_ROOT, - imx_clk_gate2_shared2("nand_root_clk", "nand", base + 0x4300, 0, &share_count_nand)); + imx_clk_gate2_shared2(dev, "nand_root_clk", "nand", base + 0x4300, 0, &share_count_nand)); clk_dm(IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK, - imx_clk_gate2_shared2("nand_usdhc_rawnand_clk", + imx_clk_gate2_shared2(dev, "nand_usdhc_rawnand_clk", "nand_usdhc_bus", base + 0x4300, 0, &share_count_nand)); + clk_dm(IMX8MN_CLK_UART1_ROOT, + imx_clk_gate4(dev, "uart1_root_clk", "uart1", base + 0x4490, 0)); + clk_dm(IMX8MN_CLK_UART2_ROOT, + imx_clk_gate4(dev, "uart2_root_clk", "uart2", base + 0x44a0, 0)); + clk_dm(IMX8MN_CLK_UART3_ROOT, + imx_clk_gate4(dev, "uart3_root_clk", "uart3", base + 0x44b0, 0)); + clk_dm(IMX8MN_CLK_UART4_ROOT, + imx_clk_gate4(dev, "uart4_root_clk", "uart4", base + 0x44c0, 0)); clk_dm(IMX8MN_CLK_USB1_CTRL_ROOT, - imx_clk_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0)); + imx_clk_gate4(dev, "usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0)); /* clks not needed in SPL stage */ #ifndef CONFIG_XPL_BUILD clk_dm(IMX8MN_CLK_ENET_REF, - imx8m_clk_composite("enet_ref", imx8mn_enet_ref_sels, + imx8m_clk_composite(dev, "enet_ref", imx8mn_enet_ref_sels, base + 0xa980)); clk_dm(IMX8MN_CLK_ENET_TIMER, - imx8m_clk_composite("enet_timer", imx8mn_enet_timer_sels, + imx8m_clk_composite(dev, "enet_timer", imx8mn_enet_timer_sels, base + 0xaa00)); clk_dm(IMX8MN_CLK_ENET_PHY_REF, - imx8m_clk_composite("enet_phy", imx8mn_enet_phy_sels, + imx8m_clk_composite(dev, "enet_phy", imx8mn_enet_phy_sels, base + 0xaa80)); clk_dm(IMX8MN_CLK_ENET1_ROOT, - imx_clk_gate4("enet1_root_clk", "enet_axi", + imx_clk_gate4(dev, "enet1_root_clk", "enet_axi", base + 0x40a0, 0)); clk_dm(IMX8MN_CLK_PWM1, - imx8m_clk_composite("pwm1", imx8mn_pwm1_sels, base + 0xb380)); + imx8m_clk_composite(dev, "pwm1", imx8mn_pwm1_sels, base + 0xb380)); clk_dm(IMX8MN_CLK_PWM2, - imx8m_clk_composite("pwm2", imx8mn_pwm2_sels, base + 0xb400)); + imx8m_clk_composite(dev, "pwm2", imx8mn_pwm2_sels, base + 0xb400)); clk_dm(IMX8MN_CLK_PWM3, - imx8m_clk_composite("pwm3", imx8mn_pwm3_sels, base + 0xb480)); + imx8m_clk_composite(dev, "pwm3", imx8mn_pwm3_sels, base + 0xb480)); clk_dm(IMX8MN_CLK_PWM4, - imx8m_clk_composite("pwm4", imx8mn_pwm4_sels, base + 0xb500)); + imx8m_clk_composite(dev, "pwm4", imx8mn_pwm4_sels, base + 0xb500)); clk_dm(IMX8MN_CLK_PWM1_ROOT, - imx_clk_gate4("pwm1_root_clk", "pwm1", base + 0x4280, 0)); + imx_clk_gate4(dev, "pwm1_root_clk", "pwm1", base + 0x4280, 0)); clk_dm(IMX8MN_CLK_PWM2_ROOT, - imx_clk_gate4("pwm2_root_clk", "pwm2", base + 0x4290, 0)); + imx_clk_gate4(dev, "pwm2_root_clk", "pwm2", base + 0x4290, 0)); clk_dm(IMX8MN_CLK_PWM3_ROOT, - imx_clk_gate4("pwm3_root_clk", "pwm3", base + 0x42a0, 0)); + imx_clk_gate4(dev, "pwm3_root_clk", "pwm3", base + 0x42a0, 0)); clk_dm(IMX8MN_CLK_PWM4_ROOT, - imx_clk_gate4("pwm4_root_clk", "pwm4", base + 0x42b0, 0)); + imx_clk_gate4(dev, "pwm4_root_clk", "pwm4", base + 0x42b0, 0)); #endif #if CONFIG_IS_ENABLED(DM_SPI) clk_dm(IMX8MN_CLK_ECSPI1, - imx8m_clk_composite("ecspi1", imx8mn_ecspi1_sels, base + 0xb280)); + imx8m_clk_composite(dev, "ecspi1", imx8mn_ecspi1_sels, base + 0xb280)); clk_dm(IMX8MN_CLK_ECSPI2, - imx8m_clk_composite("ecspi2", imx8mn_ecspi2_sels, base + 0xb300)); + imx8m_clk_composite(dev, "ecspi2", imx8mn_ecspi2_sels, base + 0xb300)); clk_dm(IMX8MN_CLK_ECSPI3, - imx8m_clk_composite("ecspi3", imx8mn_ecspi3_sels, base + 0xc180)); + imx8m_clk_composite(dev, "ecspi3", imx8mn_ecspi3_sels, base + 0xc180)); clk_dm(IMX8MN_CLK_ECSPI1_ROOT, - imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0)); + imx_clk_gate4(dev, "ecspi1_root_clk", "ecspi1", base + 0x4070, 0)); clk_dm(IMX8MN_CLK_ECSPI2_ROOT, - imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0)); + imx_clk_gate4(dev, "ecspi2_root_clk", "ecspi2", base + 0x4080, 0)); clk_dm(IMX8MN_CLK_ECSPI3_ROOT, - imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0)); + imx_clk_gate4(dev, "ecspi3_root_clk", "ecspi3", base + 0x4090, 0)); #endif clk_dm(IMX8MN_CLK_ARM, - imx_clk_mux2_flags("arm_core", base + 0x9880, 24, 1, + imx_clk_mux2_flags(dev, "arm_core", base + 0x9880, 24, 1, imx8mn_arm_core_sels, ARRAY_SIZE(imx8mn_arm_core_sels), CLK_IS_CRITICAL)); diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index 1d04090ca00..bad579f8d5e 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -14,7 +14,7 @@ #include "clk.h" -static const char * const pll_ref_sels[] = { "clock-osc-24m", "dummy", "dummy", "dummy", }; +static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", }; static const char * const dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", }; static const char * const arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", }; static const char * const sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", }; @@ -23,167 +23,167 @@ static const char * const sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_se static const char * const imx8mp_arm_core_sels[] = {"arm_a53_src", "arm_pll_out", }; -static const char * const imx8mp_a53_sels[] = {"clock-osc-24m", "arm_pll_out", "sys_pll2_500m", +static const char * const imx8mp_a53_sels[] = {"osc_24m", "arm_pll_out", "sys_pll2_500m", "sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m", "audio_pll1_out", "sys_pll3_out", }; -static const char * const imx8mp_hsio_axi_sels[] = {"clock-osc-24m", "sys_pll2_500m", "sys_pll1_800m", +static const char * const imx8mp_hsio_axi_sels[] = {"osc_24m", "sys_pll2_500m", "sys_pll1_800m", "sys_pll2_100m", "sys_pll2_200m", "clk_ext2", "clk_ext4", "audio_pll2_out", }; -static const char * const imx8mp_main_axi_sels[] = {"clock-osc-24m", "sys_pll2_333m", "sys_pll1_800m", +static const char * const imx8mp_main_axi_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll1_800m", "sys_pll2_250m", "sys_pll2_1000m", "audio_pll1_out", "video_pll1_out", "sys_pll1_100m",}; -static const char * const imx8mp_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", +static const char * const imx8mp_enet_axi_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_250m", "sys_pll2_200m", "audio_pll1_out", "video_pll1_out", "sys_pll3_out", }; -static const char * const imx8mp_nand_usdhc_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", +static const char * const imx8mp_nand_usdhc_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_200m", "sys_pll1_133m", "sys_pll3_out", "sys_pll2_250m", "audio_pll1_out", }; -static const char * const imx8mp_noc_sels[] = {"clock-osc-24m", "sys_pll1_800m", "sys_pll3_out", +static const char * const imx8mp_noc_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_1000m", "sys_pll2_500m", "audio_pll1_out", "video_pll1_out", "audio_pll2_out", }; -static const char * const imx8mp_noc_io_sels[] = {"clock-osc-24m", "sys_pll1_800m", "sys_pll3_out", +static const char * const imx8mp_noc_io_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_1000m", "sys_pll2_500m", "audio_pll1_out", "video_pll1_out", "audio_pll2_out", }; -static const char * const imx8mp_ahb_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_800m", +static const char * const imx8mp_ahb_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_800m", "sys_pll1_400m", "sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", "video_pll1_out", }; -static const char * const imx8mp_dram_alt_sels[] = {"clock-osc-24m", "sys_pll1_800m", "sys_pll1_100m", +static const char * const imx8mp_dram_alt_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll1_100m", "sys_pll2_500m", "sys_pll2_1000m", "sys_pll3_out", "audio_pll1_out", "sys_pll1_266m", }; -static const char * const imx8mp_dram_apb_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", +static const char * const imx8mp_dram_apb_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", }; -static const char * const imx8mp_pcie_aux_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll2_50m", +static const char * const imx8mp_pcie_aux_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll2_50m", "sys_pll3_out", "sys_pll2_100m", "sys_pll1_80m", "sys_pll1_160m", "sys_pll1_200m", }; -static const char * const imx8mp_i2c5_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", +static const char * const imx8mp_i2c5_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out", "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", }; -static const char * const imx8mp_i2c6_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", +static const char * const imx8mp_i2c6_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out", "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", }; -static const char * const imx8mp_enet_qos_sels[] = {"clock-osc-24m", "sys_pll2_125m", "sys_pll2_50m", +static const char * const imx8mp_enet_qos_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_50m", "sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out", "video_pll1_out", "clk_ext4", }; -static const char * const imx8mp_enet_qos_timer_sels[] = {"clock-osc-24m", "sys_pll2_100m", "audio_pll1_out", +static const char * const imx8mp_enet_qos_timer_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_out", "clk_ext1", "clk_ext2", "clk_ext3", "clk_ext4", "video_pll1_out", }; -static const char * const imx8mp_usdhc1_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", +static const char * const imx8mp_usdhc1_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", }; -static const char * const imx8mp_usdhc2_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", +static const char * const imx8mp_usdhc2_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", }; -static const char * const imx8mp_i2c1_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", +static const char * const imx8mp_i2c1_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out", "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", }; -static const char * const imx8mp_i2c2_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", +static const char * const imx8mp_i2c2_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out", "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", }; -static const char * const imx8mp_i2c3_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", +static const char * const imx8mp_i2c3_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out", "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", }; -static const char * const imx8mp_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", +static const char * const imx8mp_i2c4_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out", "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", }; -static const char * const imx8mp_uart1_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m", +static const char * const imx8mp_uart1_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m", "sys_pll2_100m", "sys_pll3_out", "clk_ext2", "clk_ext4", "audio_pll2_out", }; -static const char * const imx8mp_uart2_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m", +static const char * const imx8mp_uart2_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m", "sys_pll2_100m", "sys_pll3_out", "clk_ext2", "clk_ext3", "audio_pll2_out", }; -static const char * const imx8mp_uart3_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m", +static const char * const imx8mp_uart3_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m", "sys_pll2_100m", "sys_pll3_out", "clk_ext2", "clk_ext4", "audio_pll2_out", }; -static const char * const imx8mp_uart4_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m", +static const char * const imx8mp_uart4_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m", "sys_pll2_100m", "sys_pll3_out", "clk_ext2", "clk_ext3", "audio_pll2_out", }; -static const char * const imx8mp_usb_core_ref_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m", +static const char * const imx8mp_usb_core_ref_sels[] = {"osc_24m", "sys_pll1_100m", "sys_pll1_40m", "sys_pll2_100m", "sys_pll2_200m", "clk_ext2", "clk_ext3", "audio_pll2_out", }; -static const char * const imx8mp_usb_phy_ref_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m", +static const char * const imx8mp_usb_phy_ref_sels[] = {"osc_24m", "sys_pll1_100m", "sys_pll1_40m", "sys_pll2_100m", "sys_pll2_200m", "clk_ext2", "clk_ext3", "audio_pll2_out", }; -static const char * const imx8mp_gic_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", +static const char * const imx8mp_gic_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll2_100m", "sys_pll1_800m", "sys_pll2_500m", "clk_ext4", "audio_pll2_out" }; -static const char * const imx8mp_pwm1_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", +static const char * const imx8mp_pwm1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll1_out", }; -static const char * const imx8mp_pwm2_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", +static const char * const imx8mp_pwm2_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll1_out", }; -static const char * const imx8mp_pwm3_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", +static const char * const imx8mp_pwm3_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll1_out", }; -static const char * const imx8mp_pwm4_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", +static const char * const imx8mp_pwm4_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll1_out", }; -static const char * const imx8mp_ecspi1_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", +static const char * const imx8mp_ecspi1_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", }; -static const char * const imx8mp_ecspi2_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", +static const char * const imx8mp_ecspi2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", }; -static const char * const imx8mp_ecspi3_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", +static const char * const imx8mp_ecspi3_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", }; -static const char * const imx8mp_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_160m", +static const char * const imx8mp_wdog_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_160m", "vpu_pll_out", "sys_pll2_125m", "sys_pll3_out", "sys_pll1_80m", "sys_pll2_166m" }; -static const char * const imx8mp_qspi_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll2_333m", +static const char * const imx8mp_qspi_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll2_333m", "sys_pll2_500m", "audio_pll2_out", "sys_pll1_266m", "sys_pll3_out", "sys_pll1_100m", }; -static const char * const imx8mp_usdhc3_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", +static const char * const imx8mp_usdhc3_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", }; -static const char * const imx8mp_enet_ref_sels[] = {"clock-osc-24m", "sys_pll2_125m", "sys_pll2_50m", +static const char * const imx8mp_enet_ref_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_50m", "sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out", "video_pll1_out", "clk_ext4", }; -static const char * const imx8mp_enet_timer_sels[] = {"clock-osc-24m", "sys_pll2_100m", "audio_pll1_out", +static const char * const imx8mp_enet_timer_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_out", "clk_ext1", "clk_ext2", "clk_ext3", "clk_ext4", "video_pll1_out", }; -static const char * const imx8mp_enet_phy_ref_sels[] = {"clock-osc-24m", "sys_pll2_50m", "sys_pll2_125m", +static const char * const imx8mp_enet_phy_ref_sels[] = {"osc_24m", "sys_pll2_50m", "sys_pll2_125m", "sys_pll2_200m", "sys_pll2_500m", "audio_pll1_out", "video_pll1_out", "audio_pll2_out", }; @@ -199,11 +199,11 @@ static int imx8mp_clk_probe(struct udevice *dev) clk_dm(IMX8MP_CLK_DUMMY, clk_register_fixed_rate(NULL, "dummy", 0)); - clk_dm(IMX8MP_DRAM_PLL_REF_SEL, imx_clk_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); - clk_dm(IMX8MP_ARM_PLL_REF_SEL, imx_clk_mux("arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); - clk_dm(IMX8MP_SYS_PLL1_REF_SEL, imx_clk_mux("sys_pll1_ref_sel", base + 0x94, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); - clk_dm(IMX8MP_SYS_PLL2_REF_SEL, imx_clk_mux("sys_pll2_ref_sel", base + 0x104, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); - clk_dm(IMX8MP_SYS_PLL3_REF_SEL, imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); + clk_dm(IMX8MP_DRAM_PLL_REF_SEL, imx_clk_mux(dev, "dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); + clk_dm(IMX8MP_ARM_PLL_REF_SEL, imx_clk_mux(dev, "arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); + clk_dm(IMX8MP_SYS_PLL1_REF_SEL, imx_clk_mux(dev, "sys_pll1_ref_sel", base + 0x94, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); + clk_dm(IMX8MP_SYS_PLL2_REF_SEL, imx_clk_mux(dev, "sys_pll2_ref_sel", base + 0x104, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); + clk_dm(IMX8MP_SYS_PLL3_REF_SEL, imx_clk_mux(dev, "sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); clk_dm(IMX8MP_DRAM_PLL, imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50, &imx_1443x_dram_pll)); @@ -216,37 +216,37 @@ static int imx8mp_clk_probe(struct udevice *dev) clk_dm(IMX8MP_SYS_PLL3, imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel", base + 0x114, &imx_1416x_pll)); - clk_dm(IMX8MP_DRAM_PLL_BYPASS, imx_clk_mux_flags("dram_pll_bypass", base + 0x50, 4, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), CLK_SET_RATE_PARENT)); - clk_dm(IMX8MP_ARM_PLL_BYPASS, imx_clk_mux_flags("arm_pll_bypass", base + 0x84, 4, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT)); - clk_dm(IMX8MP_SYS_PLL1_BYPASS, imx_clk_mux_flags("sys_pll1_bypass", base + 0x94, 4, 1, sys_pll1_bypass_sels, ARRAY_SIZE(sys_pll1_bypass_sels), CLK_SET_RATE_PARENT)); - clk_dm(IMX8MP_SYS_PLL2_BYPASS, imx_clk_mux_flags("sys_pll2_bypass", base + 0x104, 4, 1, sys_pll2_bypass_sels, ARRAY_SIZE(sys_pll2_bypass_sels), CLK_SET_RATE_PARENT)); - clk_dm(IMX8MP_SYS_PLL3_BYPASS, imx_clk_mux_flags("sys_pll3_bypass", base + 0x114, 4, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels), CLK_SET_RATE_PARENT)); - - clk_dm(IMX8MP_DRAM_PLL_OUT, imx_clk_gate("dram_pll_out", "dram_pll_bypass", base + 0x50, 13)); - clk_dm(IMX8MP_ARM_PLL_OUT, imx_clk_gate("arm_pll_out", "arm_pll_bypass", base + 0x84, 11)); - clk_dm(IMX8MP_SYS_PLL1_OUT, imx_clk_gate("sys_pll1_out", "sys_pll1_bypass", base + 0x94, 11)); - clk_dm(IMX8MP_SYS_PLL2_OUT, imx_clk_gate("sys_pll2_out", "sys_pll2_bypass", base + 0x104, 11)); - clk_dm(IMX8MP_SYS_PLL3_OUT, imx_clk_gate("sys_pll3_out", "sys_pll3_bypass", base + 0x114, 11)); - - clk_dm(IMX8MP_SYS_PLL1_40M, imx_clk_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20)); - clk_dm(IMX8MP_SYS_PLL1_80M, imx_clk_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10)); - clk_dm(IMX8MP_SYS_PLL1_100M, imx_clk_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8)); - clk_dm(IMX8MP_SYS_PLL1_133M, imx_clk_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6)); - clk_dm(IMX8MP_SYS_PLL1_160M, imx_clk_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5)); - clk_dm(IMX8MP_SYS_PLL1_200M, imx_clk_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4)); - clk_dm(IMX8MP_SYS_PLL1_266M, imx_clk_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3)); - clk_dm(IMX8MP_SYS_PLL1_400M, imx_clk_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2)); - clk_dm(IMX8MP_SYS_PLL1_800M, imx_clk_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1)); - - clk_dm(IMX8MP_SYS_PLL2_50M, imx_clk_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20)); - clk_dm(IMX8MP_SYS_PLL2_100M, imx_clk_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10)); - clk_dm(IMX8MP_SYS_PLL2_125M, imx_clk_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8)); - clk_dm(IMX8MP_SYS_PLL2_166M, imx_clk_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6)); - clk_dm(IMX8MP_SYS_PLL2_200M, imx_clk_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5)); - clk_dm(IMX8MP_SYS_PLL2_250M, imx_clk_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4)); - clk_dm(IMX8MP_SYS_PLL2_333M, imx_clk_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3)); - clk_dm(IMX8MP_SYS_PLL2_500M, imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2)); - clk_dm(IMX8MP_SYS_PLL2_1000M, imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1)); + clk_dm(IMX8MP_DRAM_PLL_BYPASS, imx_clk_mux_flags(dev, "dram_pll_bypass", base + 0x50, 4, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), CLK_SET_RATE_PARENT)); + clk_dm(IMX8MP_ARM_PLL_BYPASS, imx_clk_mux_flags(dev, "arm_pll_bypass", base + 0x84, 4, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT)); + clk_dm(IMX8MP_SYS_PLL1_BYPASS, imx_clk_mux_flags(dev, "sys_pll1_bypass", base + 0x94, 4, 1, sys_pll1_bypass_sels, ARRAY_SIZE(sys_pll1_bypass_sels), CLK_SET_RATE_PARENT)); + clk_dm(IMX8MP_SYS_PLL2_BYPASS, imx_clk_mux_flags(dev, "sys_pll2_bypass", base + 0x104, 4, 1, sys_pll2_bypass_sels, ARRAY_SIZE(sys_pll2_bypass_sels), CLK_SET_RATE_PARENT)); + clk_dm(IMX8MP_SYS_PLL3_BYPASS, imx_clk_mux_flags(dev, "sys_pll3_bypass", base + 0x114, 4, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels), CLK_SET_RATE_PARENT)); + + clk_dm(IMX8MP_DRAM_PLL_OUT, imx_clk_gate(dev, "dram_pll_out", "dram_pll_bypass", base + 0x50, 13)); + clk_dm(IMX8MP_ARM_PLL_OUT, imx_clk_gate(dev, "arm_pll_out", "arm_pll_bypass", base + 0x84, 11)); + clk_dm(IMX8MP_SYS_PLL1_OUT, imx_clk_gate(dev, "sys_pll1_out", "sys_pll1_bypass", base + 0x94, 11)); + clk_dm(IMX8MP_SYS_PLL2_OUT, imx_clk_gate(dev, "sys_pll2_out", "sys_pll2_bypass", base + 0x104, 11)); + clk_dm(IMX8MP_SYS_PLL3_OUT, imx_clk_gate(dev, "sys_pll3_out", "sys_pll3_bypass", base + 0x114, 11)); + + clk_dm(IMX8MP_SYS_PLL1_40M, imx_clk_fixed_factor(dev, "sys_pll1_40m", "sys_pll1_out", 1, 20)); + clk_dm(IMX8MP_SYS_PLL1_80M, imx_clk_fixed_factor(dev, "sys_pll1_80m", "sys_pll1_out", 1, 10)); + clk_dm(IMX8MP_SYS_PLL1_100M, imx_clk_fixed_factor(dev, "sys_pll1_100m", "sys_pll1_out", 1, 8)); + clk_dm(IMX8MP_SYS_PLL1_133M, imx_clk_fixed_factor(dev, "sys_pll1_133m", "sys_pll1_out", 1, 6)); + clk_dm(IMX8MP_SYS_PLL1_160M, imx_clk_fixed_factor(dev, "sys_pll1_160m", "sys_pll1_out", 1, 5)); + clk_dm(IMX8MP_SYS_PLL1_200M, imx_clk_fixed_factor(dev, "sys_pll1_200m", "sys_pll1_out", 1, 4)); + clk_dm(IMX8MP_SYS_PLL1_266M, imx_clk_fixed_factor(dev, "sys_pll1_266m", "sys_pll1_out", 1, 3)); + clk_dm(IMX8MP_SYS_PLL1_400M, imx_clk_fixed_factor(dev, "sys_pll1_400m", "sys_pll1_out", 1, 2)); + clk_dm(IMX8MP_SYS_PLL1_800M, imx_clk_fixed_factor(dev, "sys_pll1_800m", "sys_pll1_out", 1, 1)); + + clk_dm(IMX8MP_SYS_PLL2_50M, imx_clk_fixed_factor(dev, "sys_pll2_50m", "sys_pll2_out", 1, 20)); + clk_dm(IMX8MP_SYS_PLL2_100M, imx_clk_fixed_factor(dev, "sys_pll2_100m", "sys_pll2_out", 1, 10)); + clk_dm(IMX8MP_SYS_PLL2_125M, imx_clk_fixed_factor(dev, "sys_pll2_125m", "sys_pll2_out", 1, 8)); + clk_dm(IMX8MP_SYS_PLL2_166M, imx_clk_fixed_factor(dev, "sys_pll2_166m", "sys_pll2_out", 1, 6)); + clk_dm(IMX8MP_SYS_PLL2_200M, imx_clk_fixed_factor(dev, "sys_pll2_200m", "sys_pll2_out", 1, 5)); + clk_dm(IMX8MP_SYS_PLL2_250M, imx_clk_fixed_factor(dev, "sys_pll2_250m", "sys_pll2_out", 1, 4)); + clk_dm(IMX8MP_SYS_PLL2_333M, imx_clk_fixed_factor(dev, "sys_pll2_333m", "sys_pll2_out", 1, 3)); + clk_dm(IMX8MP_SYS_PLL2_500M, imx_clk_fixed_factor(dev, "sys_pll2_500m", "sys_pll2_out", 1, 2)); + clk_dm(IMX8MP_SYS_PLL2_1000M, imx_clk_fixed_factor(dev, "sys_pll2_1000m", "sys_pll2_out", 1, 1)); ret = clk_get_by_name(dev, "osc_24m", &osc_24m_clk); if (ret) @@ -262,104 +262,104 @@ static int imx8mp_clk_probe(struct udevice *dev) if (!base) return -EINVAL; - clk_dm(IMX8MP_CLK_A53_SRC, imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3, imx8mp_a53_sels, ARRAY_SIZE(imx8mp_a53_sels))); - clk_dm(IMX8MP_CLK_A53_CG, imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28)); - clk_dm(IMX8MP_CLK_A53_DIV, imx_clk_divider2("arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3)); - - clk_dm(IMX8MP_CLK_HSIO_AXI, imx8m_clk_composite("hsio_axi", imx8mp_hsio_axi_sels, base + 0x8380)); - clk_dm(IMX8MP_CLK_MAIN_AXI, imx8m_clk_composite_critical("main_axi", imx8mp_main_axi_sels, base + 0x8800)); - clk_dm(IMX8MP_CLK_ENET_AXI, imx8m_clk_composite_critical("enet_axi", imx8mp_enet_axi_sels, base + 0x8880)); - clk_dm(IMX8MP_CLK_NAND_USDHC_BUS, imx8m_clk_composite_critical("nand_usdhc_bus", imx8mp_nand_usdhc_sels, base + 0x8900)); - clk_dm(IMX8MP_CLK_NOC, imx8m_clk_composite_critical("noc", imx8mp_noc_sels, base + 0x8d00)); - clk_dm(IMX8MP_CLK_NOC_IO, imx8m_clk_composite_critical("noc_io", imx8mp_noc_io_sels, base + 0x8d80)); - - clk_dm(IMX8MP_CLK_AHB, imx8m_clk_composite_critical("ahb_root", imx8mp_ahb_sels, base + 0x9000)); - - clk_dm(IMX8MP_CLK_IPG_ROOT, imx_clk_divider2("ipg_root", "ahb_root", base + 0x9080, 0, 1)); - - clk_dm(IMX8MP_CLK_DRAM_ALT, imx8m_clk_composite("dram_alt", imx8mp_dram_alt_sels, base + 0xa000)); - clk_dm(IMX8MP_CLK_DRAM_APB, imx8m_clk_composite_critical("dram_apb", imx8mp_dram_apb_sels, base + 0xa080)); - clk_dm(IMX8MP_CLK_PCIE_AUX, imx8m_clk_composite("pcie_aux", imx8mp_pcie_aux_sels, base + 0xa400)); - clk_dm(IMX8MP_CLK_I2C5, imx8m_clk_composite("i2c5", imx8mp_i2c5_sels, base + 0xa480)); - clk_dm(IMX8MP_CLK_I2C6, imx8m_clk_composite("i2c6", imx8mp_i2c6_sels, base + 0xa500)); - clk_dm(IMX8MP_CLK_ENET_QOS, imx8m_clk_composite("enet_qos", imx8mp_enet_qos_sels, base + 0xa880)); - clk_dm(IMX8MP_CLK_ENET_QOS_TIMER, imx8m_clk_composite("enet_qos_timer", imx8mp_enet_qos_timer_sels, base + 0xa900)); - clk_dm(IMX8MP_CLK_ENET_REF, imx8m_clk_composite("enet_ref", imx8mp_enet_ref_sels, base + 0xa980)); - clk_dm(IMX8MP_CLK_ENET_TIMER, imx8m_clk_composite("enet_timer", imx8mp_enet_timer_sels, base + 0xaa00)); - clk_dm(IMX8MP_CLK_ENET_PHY_REF, imx8m_clk_composite("enet_phy_ref", imx8mp_enet_phy_ref_sels, base + 0xaa80)); - clk_dm(IMX8MP_CLK_QSPI, imx8m_clk_composite("qspi", imx8mp_qspi_sels, base + 0xab80)); - clk_dm(IMX8MP_CLK_USDHC1, imx8m_clk_composite("usdhc1", imx8mp_usdhc1_sels, base + 0xac00)); - clk_dm(IMX8MP_CLK_USDHC2, imx8m_clk_composite("usdhc2", imx8mp_usdhc2_sels, base + 0xac80)); - clk_dm(IMX8MP_CLK_I2C1, imx8m_clk_composite("i2c1", imx8mp_i2c1_sels, base + 0xad00)); - clk_dm(IMX8MP_CLK_I2C2, imx8m_clk_composite("i2c2", imx8mp_i2c2_sels, base + 0xad80)); - clk_dm(IMX8MP_CLK_I2C3, imx8m_clk_composite("i2c3", imx8mp_i2c3_sels, base + 0xae00)); - clk_dm(IMX8MP_CLK_I2C4, imx8m_clk_composite("i2c4", imx8mp_i2c4_sels, base + 0xae80)); - - clk_dm(IMX8MP_CLK_UART1, imx8m_clk_composite("uart1", imx8mp_uart1_sels, base + 0xaf00)); - clk_dm(IMX8MP_CLK_UART2, imx8m_clk_composite("uart2", imx8mp_uart2_sels, base + 0xaf80)); - clk_dm(IMX8MP_CLK_UART3, imx8m_clk_composite("uart3", imx8mp_uart3_sels, base + 0xb000)); - clk_dm(IMX8MP_CLK_UART4, imx8m_clk_composite("uart4", imx8mp_uart4_sels, base + 0xb080)); - clk_dm(IMX8MP_CLK_USB_CORE_REF, imx8m_clk_composite("usb_core_ref", imx8mp_usb_core_ref_sels, base + 0xb100)); - clk_dm(IMX8MP_CLK_USB_PHY_REF, imx8m_clk_composite("usb_phy_ref", imx8mp_usb_phy_ref_sels, base + 0xb180)); - clk_dm(IMX8MP_CLK_GIC, imx8m_clk_composite_critical("gic", imx8mp_gic_sels, base + 0xb200)); - clk_dm(IMX8MP_CLK_ECSPI1, imx8m_clk_composite("ecspi1", imx8mp_ecspi1_sels, base + 0xb280)); - clk_dm(IMX8MP_CLK_ECSPI2, imx8m_clk_composite("ecspi2", imx8mp_ecspi2_sels, base + 0xb300)); - clk_dm(IMX8MP_CLK_PWM1, imx8m_clk_composite_critical("pwm1", imx8mp_pwm1_sels, base + 0xb380)); - clk_dm(IMX8MP_CLK_PWM2, imx8m_clk_composite_critical("pwm2", imx8mp_pwm2_sels, base + 0xb400)); - clk_dm(IMX8MP_CLK_PWM3, imx8m_clk_composite_critical("pwm3", imx8mp_pwm3_sels, base + 0xb480)); - clk_dm(IMX8MP_CLK_PWM4, imx8m_clk_composite_critical("pwm4", imx8mp_pwm4_sels, base + 0xb500)); - clk_dm(IMX8MP_CLK_ECSPI3, imx8m_clk_composite("ecspi3", imx8mp_ecspi3_sels, base + 0xc180)); - - clk_dm(IMX8MP_CLK_WDOG, imx8m_clk_composite("wdog", imx8mp_wdog_sels, base + 0xb900)); - clk_dm(IMX8MP_CLK_USDHC3, imx8m_clk_composite("usdhc3", imx8mp_usdhc3_sels, base + 0xbc80)); - - clk_dm(IMX8MP_CLK_DRAM_ALT_ROOT, imx_clk_fixed_factor("dram_alt_root", "dram_alt", 1, 4)); - clk_dm(IMX8MP_CLK_DRAM_CORE, imx_clk_mux2_flags("dram_core_clk", base + 0x9800, 24, 1, imx8mp_dram_core_sels, ARRAY_SIZE(imx8mp_dram_core_sels), CLK_IS_CRITICAL)); - - clk_dm(IMX8MP_CLK_DRAM1_ROOT, imx_clk_gate4_flags("dram1_root_clk", "dram_core_clk", base + 0x4050, 0, CLK_IS_CRITICAL)); - clk_dm(IMX8MP_CLK_ECSPI1_ROOT, imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0)); - clk_dm(IMX8MP_CLK_ECSPI2_ROOT, imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0)); - clk_dm(IMX8MP_CLK_ECSPI3_ROOT, imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0)); - clk_dm(IMX8MP_CLK_ENET1_ROOT, imx_clk_gate4("enet1_root_clk", "enet_axi", base + 0x40a0, 0)); - clk_dm(IMX8MP_CLK_GPIO1_ROOT, imx_clk_gate4("gpio1_root_clk", "ipg_root", base + 0x40b0, 0)); - clk_dm(IMX8MP_CLK_GPIO2_ROOT, imx_clk_gate4("gpio2_root_clk", "ipg_root", base + 0x40c0, 0)); - clk_dm(IMX8MP_CLK_GPIO3_ROOT, imx_clk_gate4("gpio3_root_clk", "ipg_root", base + 0x40d0, 0)); - clk_dm(IMX8MP_CLK_GPIO4_ROOT, imx_clk_gate4("gpio4_root_clk", "ipg_root", base + 0x40e0, 0)); - clk_dm(IMX8MP_CLK_GPIO5_ROOT, imx_clk_gate4("gpio5_root_clk", "ipg_root", base + 0x40f0, 0)); - clk_dm(IMX8MP_CLK_I2C1_ROOT, imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0)); - clk_dm(IMX8MP_CLK_I2C2_ROOT, imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0)); - clk_dm(IMX8MP_CLK_I2C3_ROOT, imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0)); - clk_dm(IMX8MP_CLK_I2C4_ROOT, imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0)); - clk_dm(IMX8MP_CLK_PCIE_ROOT, imx_clk_gate4("pcie_root_clk", "pcie_aux", base + 0x4250, 0)); - clk_dm(IMX8MP_CLK_PWM1_ROOT, imx_clk_gate4("pwm1_root_clk", "pwm1", base + 0x4280, 0)); - clk_dm(IMX8MP_CLK_PWM2_ROOT, imx_clk_gate4("pwm2_root_clk", "pwm2", base + 0x4290, 0)); - clk_dm(IMX8MP_CLK_PWM3_ROOT, imx_clk_gate4("pwm3_root_clk", "pwm3", base + 0x42a0, 0)); - clk_dm(IMX8MP_CLK_PWM4_ROOT, imx_clk_gate4("pwm4_root_clk", "pwm4", base + 0x42b0, 0)); - clk_dm(IMX8MP_CLK_QOS_ROOT, imx_clk_gate4("qos_root_clk", "ipg_root", base + 0x42c0, 0)); - clk_dm(IMX8MP_CLK_QOS_ENET_ROOT, imx_clk_gate4("qos_enet_root_clk", "ipg_root", base + 0x42e0, 0)); - clk_dm(IMX8MP_CLK_QSPI_ROOT, imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0)); - clk_dm(IMX8MP_CLK_I2C5_ROOT, imx_clk_gate2("i2c5_root_clk", "i2c5", base + 0x4330, 0)); - clk_dm(IMX8MP_CLK_I2C6_ROOT, imx_clk_gate2("i2c6_root_clk", "i2c6", base + 0x4340, 0)); - clk_dm(IMX8MP_CLK_SIM_ENET_ROOT, imx_clk_gate4("sim_enet_root_clk", "enet_axi", base + 0x4400, 0)); - clk_dm(IMX8MP_CLK_ENET_QOS_ROOT, imx_clk_gate4("enet_qos_root_clk", "sim_enet_root_clk", base + 0x43b0, 0)); - clk_dm(IMX8MP_CLK_UART1_ROOT, imx_clk_gate4("uart1_root_clk", "uart1", base + 0x4490, 0)); - clk_dm(IMX8MP_CLK_UART2_ROOT, imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0)); - clk_dm(IMX8MP_CLK_UART3_ROOT, imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0)); - clk_dm(IMX8MP_CLK_UART4_ROOT, imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0)); - clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate2("usb_root_clk", "hsio_axi", base + 0x44d0, 0)); - clk_dm(IMX8MP_CLK_USB_SUSP, imx_clk_gate2("usb_suspend_clk", "clock-osc-24m", base + 0x44d0, 0)); - clk_dm(IMX8MP_CLK_USB_PHY_ROOT, imx_clk_gate4("usb_phy_root_clk", "usb_phy_ref", base + 0x44f0, 0)); - clk_dm(IMX8MP_CLK_USDHC1_ROOT, imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0)); - clk_dm(IMX8MP_CLK_USDHC2_ROOT, imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0)); - clk_dm(IMX8MP_CLK_WDOG1_ROOT, imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0)); - clk_dm(IMX8MP_CLK_WDOG2_ROOT, imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0)); - clk_dm(IMX8MP_CLK_WDOG3_ROOT, imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0)); - clk_dm(IMX8MP_CLK_HSIO_ROOT, imx_clk_gate4("hsio_root_clk", "ipg_root", base + 0x45c0, 0)); - - clk_dm(IMX8MP_CLK_USDHC3_ROOT, imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0)); + clk_dm(IMX8MP_CLK_A53_SRC, imx_clk_mux2(dev, "arm_a53_src", base + 0x8000, 24, 3, imx8mp_a53_sels, ARRAY_SIZE(imx8mp_a53_sels))); + clk_dm(IMX8MP_CLK_A53_CG, imx_clk_gate3(dev, "arm_a53_cg", "arm_a53_src", base + 0x8000, 28)); + clk_dm(IMX8MP_CLK_A53_DIV, imx_clk_divider2(dev, "arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3)); + + clk_dm(IMX8MP_CLK_HSIO_AXI, imx8m_clk_composite(dev, "hsio_axi", imx8mp_hsio_axi_sels, base + 0x8380)); + clk_dm(IMX8MP_CLK_MAIN_AXI, imx8m_clk_composite_critical(dev, "main_axi", imx8mp_main_axi_sels, base + 0x8800)); + clk_dm(IMX8MP_CLK_ENET_AXI, imx8m_clk_composite_critical(dev, "enet_axi", imx8mp_enet_axi_sels, base + 0x8880)); + clk_dm(IMX8MP_CLK_NAND_USDHC_BUS, imx8m_clk_composite_critical(dev, "nand_usdhc_bus", imx8mp_nand_usdhc_sels, base + 0x8900)); + clk_dm(IMX8MP_CLK_NOC, imx8m_clk_composite_critical(dev, "noc", imx8mp_noc_sels, base + 0x8d00)); + clk_dm(IMX8MP_CLK_NOC_IO, imx8m_clk_composite_critical(dev, "noc_io", imx8mp_noc_io_sels, base + 0x8d80)); + + clk_dm(IMX8MP_CLK_AHB, imx8m_clk_composite_critical(dev, "ahb_root", imx8mp_ahb_sels, base + 0x9000)); + + clk_dm(IMX8MP_CLK_IPG_ROOT, imx_clk_divider2(dev, "ipg_root", "ahb_root", base + 0x9080, 0, 1)); + + clk_dm(IMX8MP_CLK_DRAM_ALT, imx8m_clk_composite(dev, "dram_alt", imx8mp_dram_alt_sels, base + 0xa000)); + clk_dm(IMX8MP_CLK_DRAM_APB, imx8m_clk_composite_critical(dev, "dram_apb", imx8mp_dram_apb_sels, base + 0xa080)); + clk_dm(IMX8MP_CLK_PCIE_AUX, imx8m_clk_composite(dev, "pcie_aux", imx8mp_pcie_aux_sels, base + 0xa400)); + clk_dm(IMX8MP_CLK_I2C5, imx8m_clk_composite(dev, "i2c5", imx8mp_i2c5_sels, base + 0xa480)); + clk_dm(IMX8MP_CLK_I2C6, imx8m_clk_composite(dev, "i2c6", imx8mp_i2c6_sels, base + 0xa500)); + clk_dm(IMX8MP_CLK_ENET_QOS, imx8m_clk_composite(dev, "enet_qos", imx8mp_enet_qos_sels, base + 0xa880)); + clk_dm(IMX8MP_CLK_ENET_QOS_TIMER, imx8m_clk_composite(dev, "enet_qos_timer", imx8mp_enet_qos_timer_sels, base + 0xa900)); + clk_dm(IMX8MP_CLK_ENET_REF, imx8m_clk_composite(dev, "enet_ref", imx8mp_enet_ref_sels, base + 0xa980)); + clk_dm(IMX8MP_CLK_ENET_TIMER, imx8m_clk_composite(dev, "enet_timer", imx8mp_enet_timer_sels, base + 0xaa00)); + clk_dm(IMX8MP_CLK_ENET_PHY_REF, imx8m_clk_composite(dev, "enet_phy_ref", imx8mp_enet_phy_ref_sels, base + 0xaa80)); + clk_dm(IMX8MP_CLK_QSPI, imx8m_clk_composite(dev, "qspi", imx8mp_qspi_sels, base + 0xab80)); + clk_dm(IMX8MP_CLK_USDHC1, imx8m_clk_composite(dev, "usdhc1", imx8mp_usdhc1_sels, base + 0xac00)); + clk_dm(IMX8MP_CLK_USDHC2, imx8m_clk_composite(dev, "usdhc2", imx8mp_usdhc2_sels, base + 0xac80)); + clk_dm(IMX8MP_CLK_I2C1, imx8m_clk_composite(dev, "i2c1", imx8mp_i2c1_sels, base + 0xad00)); + clk_dm(IMX8MP_CLK_I2C2, imx8m_clk_composite(dev, "i2c2", imx8mp_i2c2_sels, base + 0xad80)); + clk_dm(IMX8MP_CLK_I2C3, imx8m_clk_composite(dev, "i2c3", imx8mp_i2c3_sels, base + 0xae00)); + clk_dm(IMX8MP_CLK_I2C4, imx8m_clk_composite(dev, "i2c4", imx8mp_i2c4_sels, base + 0xae80)); + + clk_dm(IMX8MP_CLK_UART1, imx8m_clk_composite(dev, "uart1", imx8mp_uart1_sels, base + 0xaf00)); + clk_dm(IMX8MP_CLK_UART2, imx8m_clk_composite(dev, "uart2", imx8mp_uart2_sels, base + 0xaf80)); + clk_dm(IMX8MP_CLK_UART3, imx8m_clk_composite(dev, "uart3", imx8mp_uart3_sels, base + 0xb000)); + clk_dm(IMX8MP_CLK_UART4, imx8m_clk_composite(dev, "uart4", imx8mp_uart4_sels, base + 0xb080)); + clk_dm(IMX8MP_CLK_USB_CORE_REF, imx8m_clk_composite(dev, "usb_core_ref", imx8mp_usb_core_ref_sels, base + 0xb100)); + clk_dm(IMX8MP_CLK_USB_PHY_REF, imx8m_clk_composite(dev, "usb_phy_ref", imx8mp_usb_phy_ref_sels, base + 0xb180)); + clk_dm(IMX8MP_CLK_GIC, imx8m_clk_composite_critical(dev, "gic", imx8mp_gic_sels, base + 0xb200)); + clk_dm(IMX8MP_CLK_ECSPI1, imx8m_clk_composite(dev, "ecspi1", imx8mp_ecspi1_sels, base + 0xb280)); + clk_dm(IMX8MP_CLK_ECSPI2, imx8m_clk_composite(dev, "ecspi2", imx8mp_ecspi2_sels, base + 0xb300)); + clk_dm(IMX8MP_CLK_PWM1, imx8m_clk_composite_critical(dev, "pwm1", imx8mp_pwm1_sels, base + 0xb380)); + clk_dm(IMX8MP_CLK_PWM2, imx8m_clk_composite_critical(dev, "pwm2", imx8mp_pwm2_sels, base + 0xb400)); + clk_dm(IMX8MP_CLK_PWM3, imx8m_clk_composite_critical(dev, "pwm3", imx8mp_pwm3_sels, base + 0xb480)); + clk_dm(IMX8MP_CLK_PWM4, imx8m_clk_composite_critical(dev, "pwm4", imx8mp_pwm4_sels, base + 0xb500)); + clk_dm(IMX8MP_CLK_ECSPI3, imx8m_clk_composite(dev, "ecspi3", imx8mp_ecspi3_sels, base + 0xc180)); + + clk_dm(IMX8MP_CLK_WDOG, imx8m_clk_composite(dev, "wdog", imx8mp_wdog_sels, base + 0xb900)); + clk_dm(IMX8MP_CLK_USDHC3, imx8m_clk_composite(dev, "usdhc3", imx8mp_usdhc3_sels, base + 0xbc80)); + + clk_dm(IMX8MP_CLK_DRAM_ALT_ROOT, imx_clk_fixed_factor(dev, "dram_alt_root", "dram_alt", 1, 4)); + clk_dm(IMX8MP_CLK_DRAM_CORE, imx_clk_mux2_flags(dev, "dram_core_clk", base + 0x9800, 24, 1, imx8mp_dram_core_sels, ARRAY_SIZE(imx8mp_dram_core_sels), CLK_IS_CRITICAL)); + + clk_dm(IMX8MP_CLK_DRAM1_ROOT, imx_clk_gate4_flags(dev, "dram1_root_clk", "dram_core_clk", base + 0x4050, 0, CLK_IS_CRITICAL)); + clk_dm(IMX8MP_CLK_ECSPI1_ROOT, imx_clk_gate4(dev, "ecspi1_root_clk", "ecspi1", base + 0x4070, 0)); + clk_dm(IMX8MP_CLK_ECSPI2_ROOT, imx_clk_gate4(dev, "ecspi2_root_clk", "ecspi2", base + 0x4080, 0)); + clk_dm(IMX8MP_CLK_ECSPI3_ROOT, imx_clk_gate4(dev, "ecspi3_root_clk", "ecspi3", base + 0x4090, 0)); + clk_dm(IMX8MP_CLK_ENET1_ROOT, imx_clk_gate4(dev, "enet1_root_clk", "enet_axi", base + 0x40a0, 0)); + clk_dm(IMX8MP_CLK_GPIO1_ROOT, imx_clk_gate4(dev, "gpio1_root_clk", "ipg_root", base + 0x40b0, 0)); + clk_dm(IMX8MP_CLK_GPIO2_ROOT, imx_clk_gate4(dev, "gpio2_root_clk", "ipg_root", base + 0x40c0, 0)); + clk_dm(IMX8MP_CLK_GPIO3_ROOT, imx_clk_gate4(dev, "gpio3_root_clk", "ipg_root", base + 0x40d0, 0)); + clk_dm(IMX8MP_CLK_GPIO4_ROOT, imx_clk_gate4(dev, "gpio4_root_clk", "ipg_root", base + 0x40e0, 0)); + clk_dm(IMX8MP_CLK_GPIO5_ROOT, imx_clk_gate4(dev, "gpio5_root_clk", "ipg_root", base + 0x40f0, 0)); + clk_dm(IMX8MP_CLK_I2C1_ROOT, imx_clk_gate4(dev, "i2c1_root_clk", "i2c1", base + 0x4170, 0)); + clk_dm(IMX8MP_CLK_I2C2_ROOT, imx_clk_gate4(dev, "i2c2_root_clk", "i2c2", base + 0x4180, 0)); + clk_dm(IMX8MP_CLK_I2C3_ROOT, imx_clk_gate4(dev, "i2c3_root_clk", "i2c3", base + 0x4190, 0)); + clk_dm(IMX8MP_CLK_I2C4_ROOT, imx_clk_gate4(dev, "i2c4_root_clk", "i2c4", base + 0x41a0, 0)); + clk_dm(IMX8MP_CLK_PCIE_ROOT, imx_clk_gate4(dev, "pcie_root_clk", "pcie_aux", base + 0x4250, 0)); + clk_dm(IMX8MP_CLK_PWM1_ROOT, imx_clk_gate4(dev, "pwm1_root_clk", "pwm1", base + 0x4280, 0)); + clk_dm(IMX8MP_CLK_PWM2_ROOT, imx_clk_gate4(dev, "pwm2_root_clk", "pwm2", base + 0x4290, 0)); + clk_dm(IMX8MP_CLK_PWM3_ROOT, imx_clk_gate4(dev, "pwm3_root_clk", "pwm3", base + 0x42a0, 0)); + clk_dm(IMX8MP_CLK_PWM4_ROOT, imx_clk_gate4(dev, "pwm4_root_clk", "pwm4", base + 0x42b0, 0)); + clk_dm(IMX8MP_CLK_QOS_ROOT, imx_clk_gate4(dev, "qos_root_clk", "ipg_root", base + 0x42c0, 0)); + clk_dm(IMX8MP_CLK_QOS_ENET_ROOT, imx_clk_gate4(dev, "qos_enet_root_clk", "ipg_root", base + 0x42e0, 0)); + clk_dm(IMX8MP_CLK_QSPI_ROOT, imx_clk_gate4(dev, "qspi_root_clk", "qspi", base + 0x42f0, 0)); + clk_dm(IMX8MP_CLK_I2C5_ROOT, imx_clk_gate2(dev, "i2c5_root_clk", "i2c5", base + 0x4330, 0)); + clk_dm(IMX8MP_CLK_I2C6_ROOT, imx_clk_gate2(dev, "i2c6_root_clk", "i2c6", base + 0x4340, 0)); + clk_dm(IMX8MP_CLK_SIM_ENET_ROOT, imx_clk_gate4(dev, "sim_enet_root_clk", "enet_axi", base + 0x4400, 0)); + clk_dm(IMX8MP_CLK_ENET_QOS_ROOT, imx_clk_gate4(dev, "enet_qos_root_clk", "sim_enet_root_clk", base + 0x43b0, 0)); + clk_dm(IMX8MP_CLK_UART1_ROOT, imx_clk_gate4(dev, "uart1_root_clk", "uart1", base + 0x4490, 0)); + clk_dm(IMX8MP_CLK_UART2_ROOT, imx_clk_gate4(dev, "uart2_root_clk", "uart2", base + 0x44a0, 0)); + clk_dm(IMX8MP_CLK_UART3_ROOT, imx_clk_gate4(dev, "uart3_root_clk", "uart3", base + 0x44b0, 0)); + clk_dm(IMX8MP_CLK_UART4_ROOT, imx_clk_gate4(dev, "uart4_root_clk", "uart4", base + 0x44c0, 0)); + clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate2(dev, "usb_root_clk", "hsio_axi", base + 0x44d0, 0)); + clk_dm(IMX8MP_CLK_USB_SUSP, imx_clk_gate2(dev, "usb_suspend_clk", "osc_24m", base + 0x44d0, 0)); + clk_dm(IMX8MP_CLK_USB_PHY_ROOT, imx_clk_gate4(dev, "usb_phy_root_clk", "usb_phy_ref", base + 0x44f0, 0)); + clk_dm(IMX8MP_CLK_USDHC1_ROOT, imx_clk_gate4(dev, "usdhc1_root_clk", "usdhc1", base + 0x4510, 0)); + clk_dm(IMX8MP_CLK_USDHC2_ROOT, imx_clk_gate4(dev, "usdhc2_root_clk", "usdhc2", base + 0x4520, 0)); + clk_dm(IMX8MP_CLK_WDOG1_ROOT, imx_clk_gate4(dev, "wdog1_root_clk", "wdog", base + 0x4530, 0)); + clk_dm(IMX8MP_CLK_WDOG2_ROOT, imx_clk_gate4(dev, "wdog2_root_clk", "wdog", base + 0x4540, 0)); + clk_dm(IMX8MP_CLK_WDOG3_ROOT, imx_clk_gate4(dev, "wdog3_root_clk", "wdog", base + 0x4550, 0)); + clk_dm(IMX8MP_CLK_HSIO_ROOT, imx_clk_gate4(dev, "hsio_root_clk", "ipg_root", base + 0x45c0, 0)); + + clk_dm(IMX8MP_CLK_USDHC3_ROOT, imx_clk_gate4(dev, "usdhc3_root_clk", "usdhc3", base + 0x45e0, 0)); clk_dm(IMX8MP_CLK_ARM, - imx_clk_mux2_flags("arm_core", base + 0x9880, 24, 1, + imx_clk_mux2_flags(dev, "arm_core", base + 0x9880, 24, 1, imx8mp_arm_core_sels, ARRAY_SIZE(imx8mp_arm_core_sels), CLK_IS_CRITICAL)); diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c index ed4acd79ef7..fe6cba19758 100644 --- a/drivers/clk/imx/clk-imx8mq.c +++ b/drivers/clk/imx/clk-imx8mq.c @@ -152,31 +152,31 @@ static int imx8mq_clk_probe(struct udevice *dev) clk_dm(IMX8MQ_CLK_27M, clk_register_fixed_rate(NULL, "clock-osc-27m", 27000000)); clk_dm(IMX8MQ_DRAM_PLL1_REF_SEL, - imx_clk_mux("dram_pll_ref_sel", base + 0x60, 0, 2, + imx_clk_mux(dev, "dram_pll_ref_sel", base + 0x60, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); clk_dm(IMX8MQ_ARM_PLL_REF_SEL, - imx_clk_mux("arm_pll_ref_sel", base + 0x28, 0, 2, + imx_clk_mux(dev, "arm_pll_ref_sel", base + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); clk_dm(IMX8MQ_GPU_PLL_REF_SEL, - imx_clk_mux("gpu_pll_ref_sel", base + 0x18, 0, 2, + imx_clk_mux(dev, "gpu_pll_ref_sel", base + 0x18, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); clk_dm(IMX8MQ_VPU_PLL_REF_SEL, - imx_clk_mux("vpu_pll_ref_sel", base + 0x20, 0, 2, + imx_clk_mux(dev, "vpu_pll_ref_sel", base + 0x20, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); clk_dm(IMX8MQ_SYS3_PLL1_REF_SEL, - imx_clk_mux("sys3_pll_ref_sel", base + 0x48, 0, 2, + imx_clk_mux(dev, "sys3_pll_ref_sel", base + 0x48, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); clk_dm(IMX8MQ_AUDIO_PLL1_REF_SEL, - imx_clk_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, + imx_clk_mux(dev, "audio_pll1_ref_sel", base + 0x0, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); clk_dm(IMX8MQ_AUDIO_PLL2_REF_SEL, - imx_clk_mux("audio_pll2_ref_sel", base + 0x8, 0, 2, + imx_clk_mux(dev, "audio_pll2_ref_sel", base + 0x8, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); clk_dm(IMX8MQ_VIDEO_PLL1_REF_SEL, - imx_clk_mux("video_pll1_ref_sel", base + 0x10, 0, 2, + imx_clk_mux(dev, "video_pll1_ref_sel", base + 0x10, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); clk_dm(IMX8MQ_VIDEO2_PLL1_REF_SEL, - imx_clk_mux("video_pll2_ref_sel", base + 0x54, 0, 2, + imx_clk_mux(dev, "video_pll2_ref_sel", base + 0x54, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); clk_dm(IMX8MQ_ARM_PLL, @@ -207,140 +207,140 @@ static int imx8mq_clk_probe(struct udevice *dev) /* PLL bypass out */ clk_dm(IMX8MQ_ARM_PLL_BYPASS, - imx_clk_mux_flags("arm_pll_bypass", base + 0x28, 4, 1, + imx_clk_mux_flags(dev, "arm_pll_bypass", base + 0x28, 4, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT)); clk_dm(IMX8MQ_GPU_PLL_BYPASS, - imx_clk_mux_flags("gpu_pll_bypass", base + 0x18, 4, 1, + imx_clk_mux_flags(dev, "gpu_pll_bypass", base + 0x18, 4, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels), CLK_SET_RATE_PARENT)); clk_dm(IMX8MQ_VPU_PLL_BYPASS, - imx_clk_mux_flags("vpu_pll_bypass", base + 0x20, 4, 1, + imx_clk_mux_flags(dev, "vpu_pll_bypass", base + 0x20, 4, 1, vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels), CLK_SET_RATE_PARENT)); clk_dm(IMX8MQ_AUDIO_PLL1_BYPASS, - imx_clk_mux_flags("audio_pll1_bypass", base + 0x0, 4, 1, + imx_clk_mux_flags(dev, "audio_pll1_bypass", base + 0x0, 4, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels), CLK_SET_RATE_PARENT)); clk_dm(IMX8MQ_AUDIO_PLL2_BYPASS, - imx_clk_mux_flags("audio_pll2_bypass", base + 0x8, 4, 1, + imx_clk_mux_flags(dev, "audio_pll2_bypass", base + 0x8, 4, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass_sels), CLK_SET_RATE_PARENT)); clk_dm(IMX8MQ_VIDEO_PLL1_BYPASS, - imx_clk_mux_flags("video_pll1_bypass", base + 0x10, 4, 1, + imx_clk_mux_flags(dev, "video_pll1_bypass", base + 0x10, 4, 1, video_pll1_bypass_sels, ARRAY_SIZE(video_pll1_bypass_sels), CLK_SET_RATE_PARENT)); /* PLL out gate */ clk_dm(IMX8MQ_DRAM_PLL_OUT, - imx_clk_gate("dram_pll_out", "dram_pll_ref_sel", + imx_clk_gate(dev, "dram_pll_out", "dram_pll_ref_sel", base + 0x60, 13)); clk_dm(IMX8MQ_ARM_PLL_OUT, - imx_clk_gate("arm_pll_out", "arm_pll_bypass", + imx_clk_gate(dev, "arm_pll_out", "arm_pll_bypass", base + 0x28, 11)); clk_dm(IMX8MQ_GPU_PLL_OUT, - imx_clk_gate("gpu_pll_out", "gpu_pll_bypass", + imx_clk_gate(dev, "gpu_pll_out", "gpu_pll_bypass", base + 0x18, 11)); clk_dm(IMX8MQ_VPU_PLL_OUT, - imx_clk_gate("vpu_pll_out", "vpu_pll_bypass", + imx_clk_gate(dev, "vpu_pll_out", "vpu_pll_bypass", base + 0x20, 11)); clk_dm(IMX8MQ_AUDIO_PLL1_OUT, - imx_clk_gate("audio_pll1_out", "audio_pll1_bypass", + imx_clk_gate(dev, "audio_pll1_out", "audio_pll1_bypass", base + 0x0, 11)); clk_dm(IMX8MQ_AUDIO_PLL2_OUT, - imx_clk_gate("audio_pll2_out", "audio_pll2_bypass", + imx_clk_gate(dev, "audio_pll2_out", "audio_pll2_bypass", base + 0x8, 11)); clk_dm(IMX8MQ_VIDEO_PLL1_OUT, - imx_clk_gate("video_pll1_out", "video_pll1_bypass", + imx_clk_gate(dev, "video_pll1_out", "video_pll1_bypass", base + 0x10, 11)); clk_dm(IMX8MQ_SYS1_PLL_OUT, - imx_clk_gate("sys_pll1_out", "sys1_pll", + imx_clk_gate(dev, "sys_pll1_out", "sys1_pll", base + 0x30, 11)); clk_dm(IMX8MQ_SYS2_PLL_OUT, - imx_clk_gate("sys_pll2_out", "sys2_pll", + imx_clk_gate(dev, "sys_pll2_out", "sys2_pll", base + 0x3c, 11)); clk_dm(IMX8MQ_SYS3_PLL_OUT, - imx_clk_gate("sys_pll3_out", "sys3_pll", + imx_clk_gate(dev, "sys_pll3_out", "sys3_pll", base + 0x48, 11)); clk_dm(IMX8MQ_VIDEO2_PLL_OUT, - imx_clk_gate("video_pll2_out", "video_pll2_ref_sel", + imx_clk_gate(dev, "video_pll2_out", "video_pll2_ref_sel", base + 0x54, 11)); /* SYS PLL fixed output */ clk_dm(IMX8MQ_SYS1_PLL_40M, - imx_clk_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20)); + imx_clk_fixed_factor(dev, "sys_pll1_40m", "sys_pll1_out", 1, 20)); clk_dm(IMX8MQ_SYS1_PLL_80M, - imx_clk_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10)); + imx_clk_fixed_factor(dev, "sys_pll1_80m", "sys_pll1_out", 1, 10)); clk_dm(IMX8MQ_SYS1_PLL_100M, - imx_clk_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8)); + imx_clk_fixed_factor(dev, "sys_pll1_100m", "sys_pll1_out", 1, 8)); clk_dm(IMX8MQ_SYS1_PLL_133M, - imx_clk_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6)); + imx_clk_fixed_factor(dev, "sys_pll1_133m", "sys_pll1_out", 1, 6)); clk_dm(IMX8MQ_SYS1_PLL_160M, - imx_clk_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5)); + imx_clk_fixed_factor(dev, "sys_pll1_160m", "sys_pll1_out", 1, 5)); clk_dm(IMX8MQ_SYS1_PLL_200M, - imx_clk_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4)); + imx_clk_fixed_factor(dev, "sys_pll1_200m", "sys_pll1_out", 1, 4)); clk_dm(IMX8MQ_SYS1_PLL_266M, - imx_clk_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3)); + imx_clk_fixed_factor(dev, "sys_pll1_266m", "sys_pll1_out", 1, 3)); clk_dm(IMX8MQ_SYS1_PLL_400M, - imx_clk_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2)); + imx_clk_fixed_factor(dev, "sys_pll1_400m", "sys_pll1_out", 1, 2)); clk_dm(IMX8MQ_SYS1_PLL_800M, - imx_clk_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1)); + imx_clk_fixed_factor(dev, "sys_pll1_800m", "sys_pll1_out", 1, 1)); clk_dm(IMX8MQ_SYS2_PLL_50M, - imx_clk_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20)); + imx_clk_fixed_factor(dev, "sys_pll2_50m", "sys_pll2_out", 1, 20)); clk_dm(IMX8MQ_SYS2_PLL_100M, - imx_clk_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10)); + imx_clk_fixed_factor(dev, "sys_pll2_100m", "sys_pll2_out", 1, 10)); clk_dm(IMX8MQ_SYS2_PLL_125M, - imx_clk_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8)); + imx_clk_fixed_factor(dev, "sys_pll2_125m", "sys_pll2_out", 1, 8)); clk_dm(IMX8MQ_SYS2_PLL_166M, - imx_clk_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6)); + imx_clk_fixed_factor(dev, "sys_pll2_166m", "sys_pll2_out", 1, 6)); clk_dm(IMX8MQ_SYS2_PLL_200M, - imx_clk_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5)); + imx_clk_fixed_factor(dev, "sys_pll2_200m", "sys_pll2_out", 1, 5)); clk_dm(IMX8MQ_SYS2_PLL_250M, - imx_clk_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4)); + imx_clk_fixed_factor(dev, "sys_pll2_250m", "sys_pll2_out", 1, 4)); clk_dm(IMX8MQ_SYS2_PLL_333M, - imx_clk_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3)); + imx_clk_fixed_factor(dev, "sys_pll2_333m", "sys_pll2_out", 1, 3)); clk_dm(IMX8MQ_SYS2_PLL_500M, - imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2)); + imx_clk_fixed_factor(dev, "sys_pll2_500m", "sys_pll2_out", 1, 2)); clk_dm(IMX8MQ_SYS2_PLL_1000M, - imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1)); + imx_clk_fixed_factor(dev, "sys_pll2_1000m", "sys_pll2_out", 1, 1)); clk_dm(IMX8MQ_CLK_MON_AUDIO_PLL1_DIV, - imx_clk_divider("audio_pll1_out_monitor", "audio_pll1_bypass", base + 0x78, 0, 3)); + imx_clk_divider(dev, "audio_pll1_out_monitor", "audio_pll1_bypass", base + 0x78, 0, 3)); clk_dm(IMX8MQ_CLK_MON_AUDIO_PLL2_DIV, - imx_clk_divider("audio_pll2_out_monitor", "audio_pll2_bypass", base + 0x78, 4, 3)); + imx_clk_divider(dev, "audio_pll2_out_monitor", "audio_pll2_bypass", base + 0x78, 4, 3)); clk_dm(IMX8MQ_CLK_MON_VIDEO_PLL1_DIV, - imx_clk_divider("video_pll1_out_monitor", "video_pll1_bypass", base + 0x78, 8, 3)); + imx_clk_divider(dev, "video_pll1_out_monitor", "video_pll1_bypass", base + 0x78, 8, 3)); clk_dm(IMX8MQ_CLK_MON_GPU_PLL_DIV, - imx_clk_divider("gpu_pll_out_monitor", "gpu_pll_bypass", base + 0x78, 12, 3)); + imx_clk_divider(dev, "gpu_pll_out_monitor", "gpu_pll_bypass", base + 0x78, 12, 3)); clk_dm(IMX8MQ_CLK_MON_VPU_PLL_DIV, - imx_clk_divider("vpu_pll_out_monitor", "vpu_pll_bypass", base + 0x78, 16, 3)); + imx_clk_divider(dev, "vpu_pll_out_monitor", "vpu_pll_bypass", base + 0x78, 16, 3)); clk_dm(IMX8MQ_CLK_MON_ARM_PLL_DIV, - imx_clk_divider("arm_pll_out_monitor", "arm_pll_bypass", base + 0x78, 20, 3)); + imx_clk_divider(dev, "arm_pll_out_monitor", "arm_pll_bypass", base + 0x78, 20, 3)); clk_dm(IMX8MQ_CLK_MON_SYS_PLL1_DIV, - imx_clk_divider("sys_pll1_out_monitor", "sys_pll1_out", base + 0x7c, 0, 3)); + imx_clk_divider(dev, "sys_pll1_out_monitor", "sys_pll1_out", base + 0x7c, 0, 3)); clk_dm(IMX8MQ_CLK_MON_SYS_PLL2_DIV, - imx_clk_divider("sys_pll2_out_monitor", "sys_pll2_out", base + 0x7c, 4, 3)); + imx_clk_divider(dev, "sys_pll2_out_monitor", "sys_pll2_out", base + 0x7c, 4, 3)); clk_dm(IMX8MQ_CLK_MON_SYS_PLL3_DIV, - imx_clk_divider("sys_pll3_out_monitor", "sys_pll3_out", base + 0x7c, 8, 3)); + imx_clk_divider(dev, "sys_pll3_out_monitor", "sys_pll3_out", base + 0x7c, 8, 3)); clk_dm(IMX8MQ_CLK_MON_DRAM_PLL_DIV, - imx_clk_divider("dram_pll_out_monitor", "dram_pll_out", base + 0x7c, 12, 3)); + imx_clk_divider(dev, "dram_pll_out_monitor", "dram_pll_out", base + 0x7c, 12, 3)); clk_dm(IMX8MQ_CLK_MON_VIDEO_PLL2_DIV, - imx_clk_divider("video_pll2_out_monitor", "video_pll2_out", base + 0x7c, 16, 3)); + imx_clk_divider(dev, "video_pll2_out_monitor", "video_pll2_out", base + 0x7c, 16, 3)); clk_dm(IMX8MQ_CLK_MON_SEL, - imx_clk_mux_flags("pllout_monitor_sel", base + 0x74, 0, 4, + imx_clk_mux_flags(dev, "pllout_monitor_sel", base + 0x74, 0, 4, pllout_monitor_sels, ARRAY_SIZE(pllout_monitor_sels), CLK_SET_RATE_PARENT)); clk_dm(IMX8MQ_CLK_MON_CLK2_OUT, - imx_clk_gate4("pllout_monitor_clk2", "pllout_monitor_sel", base + 0x74, 4)); + imx_clk_gate4(dev, "pllout_monitor_clk2", "pllout_monitor_sel", base + 0x74, 4)); base = dev_read_addr_ptr(dev); if (!base) { @@ -349,140 +349,140 @@ static int imx8mq_clk_probe(struct udevice *dev) } clk_dm(IMX8MQ_CLK_A53_SRC, - imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3, + imx_clk_mux2(dev, "arm_a53_src", base + 0x8000, 24, 3, imx8mq_a53_sels, ARRAY_SIZE(imx8mq_a53_sels))); clk_dm(IMX8MQ_CLK_A53_CG, - imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28)); + imx_clk_gate3(dev, "arm_a53_cg", "arm_a53_src", base + 0x8000, 28)); clk_dm(IMX8MQ_CLK_A53_DIV, - imx_clk_divider2("arm_a53_div", "arm_a53_cg", + imx_clk_divider2(dev, "arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3)); clk_dm(IMX8MQ_CLK_A53_CORE, - imx_clk_mux2("arm_a53_src", base + 0x9880, 24, 1, + imx_clk_mux2(dev, "arm_a53_src", base + 0x9880, 24, 1, imx8mq_a53_core_sels, ARRAY_SIZE(imx8mq_a53_core_sels))); clk_dm(IMX8MQ_CLK_AHB, - imx8m_clk_composite_critical("ahb", imx8mq_ahb_sels, + imx8m_clk_composite_critical(dev, "ahb", imx8mq_ahb_sels, base + 0x9000)); clk_dm(IMX8MQ_CLK_IPG_ROOT, - imx_clk_divider2("ipg_root", "ahb", base + 0x9080, 0, 1)); + imx_clk_divider2(dev, "ipg_root", "ahb", base + 0x9080, 0, 1)); clk_dm(IMX8MQ_CLK_ENET_AXI, - imx8m_clk_composite("enet_axi", imx8mq_enet_axi_sels, + imx8m_clk_composite(dev, "enet_axi", imx8mq_enet_axi_sels, base + 0x8880)); clk_dm(IMX8MQ_CLK_NAND_USDHC_BUS, - imx8m_clk_composite_critical("nand_usdhc_bus", + imx8m_clk_composite_critical(dev, "nand_usdhc_bus", imx8mq_nand_usdhc_sels, base + 0x8900)); clk_dm(IMX8MQ_CLK_USB_BUS, - imx8m_clk_composite("usb_bus", imx8mq_usb_bus_sels, base + 0x8b80)); + imx8m_clk_composite(dev, "usb_bus", imx8mq_usb_bus_sels, base + 0x8b80)); /* DRAM */ clk_dm(IMX8MQ_CLK_DRAM_CORE, - imx_clk_mux2("dram_core_clk", base + 0x9800, 24, 1, + imx_clk_mux2(dev, "dram_core_clk", base + 0x9800, 24, 1, imx8mq_dram_core_sels, ARRAY_SIZE(imx8mq_dram_core_sels))); clk_dm(IMX8MQ_CLK_DRAM_ALT, - imx8m_clk_composite("dram_alt", imx8mq_dram_alt_sels, base + 0xa000)); + imx8m_clk_composite(dev, "dram_alt", imx8mq_dram_alt_sels, base + 0xa000)); clk_dm(IMX8MQ_CLK_DRAM_APB, - imx8m_clk_composite_critical("dram_apb", imx8mq_dram_apb_sels, base + 0xa080)); + imx8m_clk_composite_critical(dev, "dram_apb", imx8mq_dram_apb_sels, base + 0xa080)); /* IP */ clk_dm(IMX8MQ_CLK_USDHC1, - imx8m_clk_composite("usdhc1", imx8mq_usdhc1_sels, + imx8m_clk_composite(dev, "usdhc1", imx8mq_usdhc1_sels, base + 0xac00)); clk_dm(IMX8MQ_CLK_USDHC2, - imx8m_clk_composite("usdhc2", imx8mq_usdhc2_sels, + imx8m_clk_composite(dev, "usdhc2", imx8mq_usdhc2_sels, base + 0xac80)); clk_dm(IMX8MQ_CLK_I2C1, - imx8m_clk_composite("i2c1", imx8mq_i2c1_sels, base + 0xad00)); + imx8m_clk_composite(dev, "i2c1", imx8mq_i2c1_sels, base + 0xad00)); clk_dm(IMX8MQ_CLK_I2C2, - imx8m_clk_composite("i2c2", imx8mq_i2c2_sels, base + 0xad80)); + imx8m_clk_composite(dev, "i2c2", imx8mq_i2c2_sels, base + 0xad80)); clk_dm(IMX8MQ_CLK_I2C3, - imx8m_clk_composite("i2c3", imx8mq_i2c3_sels, base + 0xae00)); + imx8m_clk_composite(dev, "i2c3", imx8mq_i2c3_sels, base + 0xae00)); clk_dm(IMX8MQ_CLK_I2C4, - imx8m_clk_composite("i2c4", imx8mq_i2c4_sels, base + 0xae80)); + imx8m_clk_composite(dev, "i2c4", imx8mq_i2c4_sels, base + 0xae80)); clk_dm(IMX8MQ_CLK_WDOG, - imx8m_clk_composite("wdog", imx8mq_wdog_sels, base + 0xb900)); + imx8m_clk_composite(dev, "wdog", imx8mq_wdog_sels, base + 0xb900)); clk_dm(IMX8MQ_CLK_UART1, - imx8m_clk_composite("uart1", imx8mq_uart1_sels, base + 0xaf00)); + imx8m_clk_composite(dev, "uart1", imx8mq_uart1_sels, base + 0xaf00)); clk_dm(IMX8MQ_CLK_UART2, - imx8m_clk_composite("uart2", imx8mq_uart2_sels, base + 0xaf80)); + imx8m_clk_composite(dev, "uart2", imx8mq_uart2_sels, base + 0xaf80)); clk_dm(IMX8MQ_CLK_UART3, - imx8m_clk_composite("uart3", imx8mq_uart3_sels, base + 0xb000)); + imx8m_clk_composite(dev, "uart3", imx8mq_uart3_sels, base + 0xb000)); clk_dm(IMX8MQ_CLK_UART4, - imx8m_clk_composite("uart4", imx8mq_uart4_sels, base + 0xb080)); + imx8m_clk_composite(dev, "uart4", imx8mq_uart4_sels, base + 0xb080)); clk_dm(IMX8MQ_CLK_QSPI, - imx8m_clk_composite("qspi", imx8mq_qspi_sels, base + 0xab80)); + imx8m_clk_composite(dev, "qspi", imx8mq_qspi_sels, base + 0xab80)); clk_dm(IMX8MQ_CLK_USB_CORE_REF, - imx8m_clk_composite("usb_core_ref", imx8mq_usb_core_sels, base + 0xb100)); + imx8m_clk_composite(dev, "usb_core_ref", imx8mq_usb_core_sels, base + 0xb100)); clk_dm(IMX8MQ_CLK_USB_PHY_REF, - imx8m_clk_composite("usb_phy_ref", imx8mq_usb_phy_sels, base + 0xb180)); + imx8m_clk_composite(dev, "usb_phy_ref", imx8mq_usb_phy_sels, base + 0xb180)); clk_dm(IMX8MQ_CLK_ECSPI1, - imx8m_clk_composite("ecspi1", imx8mq_ecspi1_sels, base + 0xb280)); + imx8m_clk_composite(dev, "ecspi1", imx8mq_ecspi1_sels, base + 0xb280)); clk_dm(IMX8MQ_CLK_ECSPI2, - imx8m_clk_composite("ecspi2", imx8mq_ecspi2_sels, base + 0xb300)); + imx8m_clk_composite(dev, "ecspi2", imx8mq_ecspi2_sels, base + 0xb300)); clk_dm(IMX8MQ_CLK_ECSPI3, - imx8m_clk_composite("ecspi3", imx8mq_ecspi3_sels, base + 0xc180)); + imx8m_clk_composite(dev, "ecspi3", imx8mq_ecspi3_sels, base + 0xc180)); clk_dm(IMX8MQ_CLK_ECSPI1_ROOT, - imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0)); + imx_clk_gate4(dev, "ecspi1_root_clk", "ecspi1", base + 0x4070, 0)); clk_dm(IMX8MQ_CLK_ECSPI2_ROOT, - imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0)); + imx_clk_gate4(dev, "ecspi2_root_clk", "ecspi2", base + 0x4080, 0)); clk_dm(IMX8MQ_CLK_ECSPI3_ROOT, - imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0)); + imx_clk_gate4(dev, "ecspi3_root_clk", "ecspi3", base + 0x4090, 0)); clk_dm(IMX8MQ_CLK_I2C1_ROOT, - imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0)); + imx_clk_gate4(dev, "i2c1_root_clk", "i2c1", base + 0x4170, 0)); clk_dm(IMX8MQ_CLK_I2C2_ROOT, - imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0)); + imx_clk_gate4(dev, "i2c2_root_clk", "i2c2", base + 0x4180, 0)); clk_dm(IMX8MQ_CLK_I2C3_ROOT, - imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0)); + imx_clk_gate4(dev, "i2c3_root_clk", "i2c3", base + 0x4190, 0)); clk_dm(IMX8MQ_CLK_I2C4_ROOT, - imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0)); + imx_clk_gate4(dev, "i2c4_root_clk", "i2c4", base + 0x41a0, 0)); clk_dm(IMX8MQ_CLK_UART1_ROOT, - imx_clk_gate4("uart1_root_clk", "uart1", base + 0x4490, 0)); + imx_clk_gate4(dev, "uart1_root_clk", "uart1", base + 0x4490, 0)); clk_dm(IMX8MQ_CLK_UART2_ROOT, - imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0)); + imx_clk_gate4(dev, "uart2_root_clk", "uart2", base + 0x44a0, 0)); clk_dm(IMX8MQ_CLK_UART3_ROOT, - imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0)); + imx_clk_gate4(dev, "uart3_root_clk", "uart3", base + 0x44b0, 0)); clk_dm(IMX8MQ_CLK_UART4_ROOT, - imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0)); + imx_clk_gate4(dev, "uart4_root_clk", "uart4", base + 0x44c0, 0)); clk_dm(IMX8MQ_CLK_OCOTP_ROOT, - imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0)); + imx_clk_gate4(dev, "ocotp_root_clk", "ipg_root", base + 0x4220, 0)); clk_dm(IMX8MQ_CLK_USDHC1_ROOT, - imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0)); + imx_clk_gate4(dev, "usdhc1_root_clk", "usdhc1", base + 0x4510, 0)); clk_dm(IMX8MQ_CLK_USDHC2_ROOT, - imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0)); + imx_clk_gate4(dev, "usdhc2_root_clk", "usdhc2", base + 0x4520, 0)); clk_dm(IMX8MQ_CLK_WDOG1_ROOT, - imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0)); + imx_clk_gate4(dev, "wdog1_root_clk", "wdog", base + 0x4530, 0)); clk_dm(IMX8MQ_CLK_WDOG2_ROOT, - imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0)); + imx_clk_gate4(dev, "wdog2_root_clk", "wdog", base + 0x4540, 0)); clk_dm(IMX8MQ_CLK_WDOG3_ROOT, - imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0)); + imx_clk_gate4(dev, "wdog3_root_clk", "wdog", base + 0x4550, 0)); clk_dm(IMX8MQ_CLK_QSPI_ROOT, - imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0)); + imx_clk_gate4(dev, "qspi_root_clk", "qspi", base + 0x42f0, 0)); clk_dm(IMX8MQ_CLK_USB1_CTRL_ROOT, - imx_clk_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0)); + imx_clk_gate4(dev, "usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0)); clk_dm(IMX8MQ_CLK_USB2_CTRL_ROOT, - imx_clk_gate4("usb2_ctrl_root_clk", "usb_bus", base + 0x44e0, 0)); + imx_clk_gate4(dev, "usb2_ctrl_root_clk", "usb_bus", base + 0x44e0, 0)); clk_dm(IMX8MQ_CLK_USB1_PHY_ROOT, - imx_clk_gate4("usb1_phy_root_clk", "usb_phy_ref", base + 0x44f0, 0)); + imx_clk_gate4(dev, "usb1_phy_root_clk", "usb_phy_ref", base + 0x44f0, 0)); clk_dm(IMX8MQ_CLK_USB2_PHY_ROOT, - imx_clk_gate4("usb2_phy_root_clk", "usb_phy_ref", base + 0x4500, 0)); + imx_clk_gate4(dev, "usb2_phy_root_clk", "usb_phy_ref", base + 0x4500, 0)); clk_dm(IMX8MQ_CLK_ENET_REF, - imx8m_clk_composite("enet_ref", imx8mq_enet_ref_sels, + imx8m_clk_composite(dev, "enet_ref", imx8mq_enet_ref_sels, base + 0xa980)); clk_dm(IMX8MQ_CLK_ENET_TIMER, - imx8m_clk_composite("enet_timer", imx8mq_enet_timer_sels, + imx8m_clk_composite(dev, "enet_timer", imx8mq_enet_timer_sels, base + 0xaa00)); clk_dm(IMX8MQ_CLK_ENET_PHY_REF, - imx8m_clk_composite("enet_phy", imx8mq_enet_phy_sels, + imx8m_clk_composite(dev, "enet_phy", imx8mq_enet_phy_sels, base + 0xaa80)); clk_dm(IMX8MQ_CLK_ENET1_ROOT, - imx_clk_gate4("enet1_root_clk", "enet_axi", + imx_clk_gate4(dev, "enet1_root_clk", "enet_axi", base + 0x40a0, 0)); clk_dm(IMX8MQ_CLK_DRAM_ALT_ROOT, - imx_clk_fixed_factor("dram_alt_root", "dram_alt", 1, 4)); + imx_clk_fixed_factor(dev, "dram_alt_root", "dram_alt", 1, 4)); return 0; } diff --git a/drivers/clk/imx/clk-imx93.c b/drivers/clk/imx/clk-imx93.c index b31e57a4a01..c3112968c17 100644 --- a/drivers/clk/imx/clk-imx93.c +++ b/drivers/clk/imx/clk-imx93.c @@ -291,15 +291,15 @@ static int imx93_clk_probe(struct udevice *dev) clk_dm(IMX93_CLK_SYS_PLL_PFD0, clk_register_fixed_rate(NULL, "sys_pll_pfd0", 1000000000)); clk_dm(IMX93_CLK_SYS_PLL_PFD0_DIV2, - imx_clk_fixed_factor("sys_pll_pfd0_div2", "sys_pll_pfd0", 1, 2)); + imx_clk_fixed_factor(dev, "sys_pll_pfd0_div2", "sys_pll_pfd0", 1, 2)); clk_dm(IMX93_CLK_SYS_PLL_PFD1, clk_register_fixed_rate(NULL, "sys_pll_pfd1", 800000000)); clk_dm(IMX93_CLK_SYS_PLL_PFD1_DIV2, - imx_clk_fixed_factor("sys_pll_pfd1_div2", "sys_pll_pfd1", 1, 2)); + imx_clk_fixed_factor(dev, "sys_pll_pfd1_div2", "sys_pll_pfd1", 1, 2)); clk_dm(IMX93_CLK_SYS_PLL_PFD2, clk_register_fixed_rate(NULL, "sys_pll_pfd2", 625000000)); clk_dm(IMX93_CLK_SYS_PLL_PFD2_DIV2, - imx_clk_fixed_factor("sys_pll_pfd2_div2", "sys_pll_pfd2", 1, 2)); + imx_clk_fixed_factor(dev, "sys_pll_pfd2_div2", "sys_pll_pfd2", 1, 2)); anatop_base = (void *)ANATOP_BASE_ADDR; @@ -338,7 +338,7 @@ static int imx93_clk_probe(struct udevice *dev) } clk_dm(IMX93_CLK_A55_SEL, - imx_clk_mux2("a55_sel", base + 0x4820, 0, 1, + imx_clk_mux2(dev, "a55_sel", base + 0x4820, 0, 1, a55_core_sels, ARRAY_SIZE(a55_core_sels))); return 0; diff --git a/drivers/clk/imx/clk-imxrt1020.c b/drivers/clk/imx/clk-imxrt1020.c index 752434cb0ad..c14afdaf236 100644 --- a/drivers/clk/imx/clk-imxrt1020.c +++ b/drivers/clk/imx/clk-imxrt1020.c @@ -38,26 +38,26 @@ static int imxrt1020_clk_probe(struct udevice *dev) base = (void *)ofnode_get_addr(ofnode_by_compatible(ofnode_null(), "fsl,imxrt-anatop")); clk_dm(IMXRT1020_CLK_PLL2_SYS, - imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_sys", "osc", + imx_clk_pllv3(dev, IMX_PLLV3_GENERIC, "pll2_sys", "osc", base + 0x30, 0x1)); clk_dm(IMXRT1020_CLK_PLL3_USB_OTG, - imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc", + imx_clk_pllv3(dev, IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x1)); /* PLL bypass out */ clk_dm(IMXRT1020_CLK_PLL2_BYPASS, - imx_clk_mux_flags("pll2_bypass", base + 0x30, 16, 1, + imx_clk_mux_flags(dev, "pll2_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT)); clk_dm(IMXRT1020_CLK_PLL3_BYPASS, - imx_clk_mux_flags("pll3_bypass", base + 0x10, 16, 1, + imx_clk_mux_flags(dev, "pll3_bypass", base + 0x10, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT)); clk_dm(IMXRT1020_CLK_PLL3_80M, - imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6)); + imx_clk_fixed_factor(dev, "pll3_80m", "pll3_usb_otg", 1, 6)); clk_dm(IMXRT1020_CLK_PLL2_PFD0_352M, imx_clk_pfd("pll2_pfd0_352m", "pll2_sys", base + 0x100, 0)); @@ -78,51 +78,51 @@ static int imxrt1020_clk_probe(struct udevice *dev) return -EINVAL; clk_dm(IMXRT1020_CLK_PRE_PERIPH_SEL, - imx_clk_mux("pre_periph_sel", base + 0x18, 18, 2, + imx_clk_mux(dev, "pre_periph_sel", base + 0x18, 18, 2, pre_periph_sels, ARRAY_SIZE(pre_periph_sels))); clk_dm(IMXRT1020_CLK_PERIPH_SEL, - imx_clk_mux("periph_sel", base + 0x14, 25, 1, + imx_clk_mux(dev, "periph_sel", base + 0x14, 25, 1, periph_sels, ARRAY_SIZE(periph_sels))); clk_dm(IMXRT1020_CLK_USDHC1_SEL, - imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1, + imx_clk_mux(dev, "usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels))); clk_dm(IMXRT1020_CLK_USDHC2_SEL, - imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1, + imx_clk_mux(dev, "usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels))); clk_dm(IMXRT1020_CLK_LPUART_SEL, - imx_clk_mux("lpuart_sel", base + 0x24, 6, 1, + imx_clk_mux(dev, "lpuart_sel", base + 0x24, 6, 1, lpuart_sels, ARRAY_SIZE(lpuart_sels))); clk_dm(IMXRT1020_CLK_SEMC_ALT_SEL, - imx_clk_mux("semc_alt_sel", base + 0x14, 7, 1, + imx_clk_mux(dev, "semc_alt_sel", base + 0x14, 7, 1, semc_alt_sels, ARRAY_SIZE(semc_alt_sels))); clk_dm(IMXRT1020_CLK_SEMC_SEL, - imx_clk_mux("semc_sel", base + 0x14, 6, 1, + imx_clk_mux(dev, "semc_sel", base + 0x14, 6, 1, semc_sels, ARRAY_SIZE(semc_sels))); clk_dm(IMXRT1020_CLK_AHB_PODF, - imx_clk_divider("ahb_podf", "periph_sel", + imx_clk_divider(dev, "ahb_podf", "periph_sel", base + 0x14, 10, 3)); clk_dm(IMXRT1020_CLK_USDHC1_PODF, - imx_clk_divider("usdhc1_podf", "usdhc1_sel", + imx_clk_divider(dev, "usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3)); clk_dm(IMXRT1020_CLK_USDHC2_PODF, - imx_clk_divider("usdhc2_podf", "usdhc2_sel", + imx_clk_divider(dev, "usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3)); clk_dm(IMXRT1020_CLK_LPUART_PODF, - imx_clk_divider("lpuart_podf", "lpuart_sel", + imx_clk_divider(dev, "lpuart_podf", "lpuart_sel", base + 0x24, 0, 6)); clk_dm(IMXRT1020_CLK_SEMC_PODF, - imx_clk_divider("semc_podf", "semc_sel", + imx_clk_divider(dev, "semc_podf", "semc_sel", base + 0x14, 16, 3)); clk_dm(IMXRT1020_CLK_USDHC1, - imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2)); + imx_clk_gate2(dev, "usdhc1", "usdhc1_podf", base + 0x80, 2)); clk_dm(IMXRT1020_CLK_USDHC2, - imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4)); + imx_clk_gate2(dev, "usdhc2", "usdhc2_podf", base + 0x80, 4)); clk_dm(IMXRT1020_CLK_LPUART1, - imx_clk_gate2("lpuart1", "lpuart_podf", base + 0x7c, 24)); + imx_clk_gate2(dev, "lpuart1", "lpuart_podf", base + 0x7c, 24)); clk_dm(IMXRT1020_CLK_SEMC, - imx_clk_gate2("semc", "semc_podf", base + 0x74, 4)); + imx_clk_gate2(dev, "semc", "semc_podf", base + 0x74, 4)); #ifdef CONFIG_XPL_BUILD struct clk *clk, *clk1; diff --git a/drivers/clk/imx/clk-imxrt1050.c b/drivers/clk/imx/clk-imxrt1050.c index 2c029ec5a6e..ba5b48748ef 100644 --- a/drivers/clk/imx/clk-imxrt1050.c +++ b/drivers/clk/imx/clk-imxrt1050.c @@ -36,63 +36,63 @@ static int imxrt1050_clk_probe(struct udevice *dev) base = (void *)ofnode_get_addr(ofnode_by_compatible(ofnode_null(), "fsl,imxrt-anatop")); clk_dm(IMXRT1050_CLK_PLL1_REF_SEL, - imx_clk_mux("pll1_arm_ref_sel", base + 0x0, 14, 2, + imx_clk_mux(dev, "pll1_arm_ref_sel", base + 0x0, 14, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); clk_dm(IMXRT1050_CLK_PLL2_REF_SEL, - imx_clk_mux("pll2_sys_ref_sel", base + 0x30, 14, 2, + imx_clk_mux(dev, "pll2_sys_ref_sel", base + 0x30, 14, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); clk_dm(IMXRT1050_CLK_PLL3_REF_SEL, - imx_clk_mux("pll3_usb_otg_ref_sel", base + 0x10, 14, 2, + imx_clk_mux(dev, "pll3_usb_otg_ref_sel", base + 0x10, 14, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); clk_dm(IMXRT1050_CLK_PLL5_REF_SEL, - imx_clk_mux("pll5_video_ref_sel", base + 0xa0, 14, 2, + imx_clk_mux(dev, "pll5_video_ref_sel", base + 0xa0, 14, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); clk_dm(IMXRT1050_CLK_PLL1_ARM, - imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_arm", "pll1_arm_ref_sel", + imx_clk_pllv3(dev, IMX_PLLV3_SYS, "pll1_arm", "pll1_arm_ref_sel", base + 0x0, 0x7f)); clk_dm(IMXRT1050_CLK_PLL2_SYS, - imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_sys", "pll2_sys_ref_sel", + imx_clk_pllv3(dev, IMX_PLLV3_GENERIC, "pll2_sys", "pll2_sys_ref_sel", base + 0x30, 0x1)); clk_dm(IMXRT1050_CLK_PLL3_USB_OTG, - imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", + imx_clk_pllv3(dev, IMX_PLLV3_USB, "pll3_usb_otg", "pll3_usb_otg_ref_sel", base + 0x10, 0x1)); clk_dm(IMXRT1050_CLK_PLL5_VIDEO, - imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "pll5_video_ref_sel", + imx_clk_pllv3(dev, IMX_PLLV3_AV, "pll5_video", "pll5_video_ref_sel", base + 0xa0, 0x7f)); /* PLL bypass out */ clk_dm(IMXRT1050_CLK_PLL1_BYPASS, - imx_clk_mux_flags("pll1_bypass", base + 0x0, 16, 1, + imx_clk_mux_flags(dev, "pll1_bypass", base + 0x0, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT)); clk_dm(IMXRT1050_CLK_PLL2_BYPASS, - imx_clk_mux_flags("pll2_bypass", base + 0x30, 16, 1, + imx_clk_mux_flags(dev, "pll2_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT)); clk_dm(IMXRT1050_CLK_PLL3_BYPASS, - imx_clk_mux_flags("pll3_bypass", base + 0x10, 16, 1, + imx_clk_mux_flags(dev, "pll3_bypass", base + 0x10, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT)); clk_dm(IMXRT1050_CLK_PLL5_BYPASS, - imx_clk_mux_flags("pll5_bypass", base + 0xa0, 16, 1, + imx_clk_mux_flags(dev, "pll5_bypass", base + 0xa0, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT)); clk_dm(IMXRT1050_CLK_VIDEO_POST_DIV_SEL, - imx_clk_divider("video_post_div_sel", "pll5_video", + imx_clk_divider(dev, "video_post_div_sel", "pll5_video", base + 0xa0, 19, 2)); clk_dm(IMXRT1050_CLK_VIDEO_DIV, - imx_clk_divider("video_div", "video_post_div_sel", + imx_clk_divider(dev, "video_div", "video_post_div_sel", base + 0x170, 30, 2)); clk_dm(IMXRT1050_CLK_PLL3_80M, - imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6)); + imx_clk_fixed_factor(dev, "pll3_80m", "pll3_usb_otg", 1, 6)); clk_dm(IMXRT1050_CLK_PLL2_PFD0_352M, imx_clk_pfd("pll2_pfd0_352m", "pll2_sys", base + 0x100, 0)); @@ -113,73 +113,73 @@ static int imxrt1050_clk_probe(struct udevice *dev) return -EINVAL; clk_dm(IMXRT1050_CLK_ARM_PODF, - imx_clk_divider("arm_podf", "pll1_arm", + imx_clk_divider(dev, "arm_podf", "pll1_arm", base + 0x10, 0, 3)); clk_dm(IMXRT1050_CLK_PRE_PERIPH_SEL, - imx_clk_mux("pre_periph_sel", base + 0x18, 18, 2, + imx_clk_mux(dev, "pre_periph_sel", base + 0x18, 18, 2, pre_periph_sels, ARRAY_SIZE(pre_periph_sels))); clk_dm(IMXRT1050_CLK_PERIPH_SEL, - imx_clk_mux("periph_sel", base + 0x14, 25, 1, + imx_clk_mux(dev, "periph_sel", base + 0x14, 25, 1, periph_sels, ARRAY_SIZE(periph_sels))); clk_dm(IMXRT1050_CLK_USDHC1_SEL, - imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1, + imx_clk_mux(dev, "usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels))); clk_dm(IMXRT1050_CLK_USDHC2_SEL, - imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1, + imx_clk_mux(dev, "usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels))); clk_dm(IMXRT1050_CLK_LPUART_SEL, - imx_clk_mux("lpuart_sel", base + 0x24, 6, 1, + imx_clk_mux(dev, "lpuart_sel", base + 0x24, 6, 1, lpuart_sels, ARRAY_SIZE(lpuart_sels))); clk_dm(IMXRT1050_CLK_SEMC_ALT_SEL, - imx_clk_mux("semc_alt_sel", base + 0x14, 7, 1, + imx_clk_mux(dev, "semc_alt_sel", base + 0x14, 7, 1, semc_alt_sels, ARRAY_SIZE(semc_alt_sels))); clk_dm(IMXRT1050_CLK_SEMC_SEL, - imx_clk_mux("semc_sel", base + 0x14, 6, 1, + imx_clk_mux(dev, "semc_sel", base + 0x14, 6, 1, semc_sels, ARRAY_SIZE(semc_sels))); clk_dm(IMXRT1050_CLK_LCDIF_SEL, - imx_clk_mux("lcdif_sel", base + 0x38, 15, 3, + imx_clk_mux(dev, "lcdif_sel", base + 0x38, 15, 3, lcdif_sels, ARRAY_SIZE(lcdif_sels))); clk_dm(IMXRT1050_CLK_AHB_PODF, - imx_clk_divider("ahb_podf", "periph_sel", + imx_clk_divider(dev, "ahb_podf", "periph_sel", base + 0x14, 10, 3)); clk_dm(IMXRT1050_CLK_IPG_PDOF, - imx_clk_divider("ipg_podf", "ahb_podf", + imx_clk_divider(dev, "ipg_podf", "ahb_podf", base + 0x14, 8, 2)); clk_dm(IMXRT1050_CLK_USDHC1_PODF, - imx_clk_divider("usdhc1_podf", "usdhc1_sel", + imx_clk_divider(dev, "usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3)); clk_dm(IMXRT1050_CLK_USDHC2_PODF, - imx_clk_divider("usdhc2_podf", "usdhc2_sel", + imx_clk_divider(dev, "usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3)); clk_dm(IMXRT1050_CLK_LPUART_PODF, - imx_clk_divider("lpuart_podf", "lpuart_sel", + imx_clk_divider(dev, "lpuart_podf", "lpuart_sel", base + 0x24, 0, 6)); clk_dm(IMXRT1050_CLK_SEMC_PODF, - imx_clk_divider("semc_podf", "semc_sel", + imx_clk_divider(dev, "semc_podf", "semc_sel", base + 0x14, 16, 3)); clk_dm(IMXRT1050_CLK_LCDIF_PRED, - imx_clk_divider("lcdif_pred", "lcdif_sel", + imx_clk_divider(dev, "lcdif_pred", "lcdif_sel", base + 0x38, 12, 3)); clk_dm(IMXRT1050_CLK_LCDIF_PODF, - imx_clk_divider("lcdif_podf", "lcdif_pred", + imx_clk_divider(dev, "lcdif_podf", "lcdif_pred", base + 0x18, 23, 3)); clk_dm(IMXRT1050_CLK_USDHC1, - imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2)); + imx_clk_gate2(dev, "usdhc1", "usdhc1_podf", base + 0x80, 2)); clk_dm(IMXRT1050_CLK_USDHC2, - imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4)); + imx_clk_gate2(dev, "usdhc2", "usdhc2_podf", base + 0x80, 4)); clk_dm(IMXRT1050_CLK_LPUART1, - imx_clk_gate2("lpuart1", "lpuart_podf", base + 0x7c, 24)); + imx_clk_gate2(dev, "lpuart1", "lpuart_podf", base + 0x7c, 24)); clk_dm(IMXRT1050_CLK_SEMC, - imx_clk_gate2("semc", "semc_podf", base + 0x74, 4)); + imx_clk_gate2(dev, "semc", "semc_podf", base + 0x74, 4)); clk_dm(IMXRT1050_CLK_LCDIF_APB, - imx_clk_gate2("lcdif", "lcdif_podf", base + 0x70, 28)); + imx_clk_gate2(dev, "lcdif", "lcdif_podf", base + 0x70, 28)); clk_dm(IMXRT1050_CLK_LCDIF_PIX, - imx_clk_gate2("lcdif_pix", "lcdif", base + 0x74, 10)); + imx_clk_gate2(dev, "lcdif_pix", "lcdif", base + 0x74, 10)); clk_dm(IMXRT1050_CLK_USBOH3, - imx_clk_gate2("usboh3", "pll3_usb_otg", base + 0x80, 0)); + imx_clk_gate2(dev, "usboh3", "pll3_usb_otg", base + 0x80, 0)); struct clk *clk, *clk1; diff --git a/drivers/clk/imx/clk-imxrt1170.c b/drivers/clk/imx/clk-imxrt1170.c index 88a294f4165..3f55d0d0127 100644 --- a/drivers/clk/imx/clk-imxrt1170.c +++ b/drivers/clk/imx/clk-imxrt1170.c @@ -114,20 +114,20 @@ static int imxrt1170_clk_probe(struct udevice *dev) base = (void *)ofnode_get_addr(ofnode_by_compatible(ofnode_null(), "fsl,imxrt-anatop")); clk_dm(IMXRT1170_CLK_RCOSC_48M, - imx_clk_fixed_factor("rcosc48M", "rcosc16M", 3, 1)); + imx_clk_fixed_factor(dev, "rcosc48M", "rcosc16M", 3, 1)); clk_dm(IMXRT1170_CLK_RCOSC_400M, - imx_clk_fixed_factor("rcosc400M", "rcosc16M", 25, 1)); + imx_clk_fixed_factor(dev, "rcosc400M", "rcosc16M", 25, 1)); clk_dm(IMXRT1170_CLK_RCOSC_48M_DIV2, - imx_clk_fixed_factor("rcosc48M_div2", "rcosc48M", 1, 2)); + imx_clk_fixed_factor(dev, "rcosc48M_div2", "rcosc48M", 1, 2)); clk_dm(IMXRT1170_CLK_PLL_ARM, - imx_clk_pllv3(IMX_PLLV3_SYS, "pll_arm", "osc", + imx_clk_pllv3(dev, IMX_PLLV3_SYS, "pll_arm", "osc", base + 0x200, 0xff)); clk_dm(IMXRT1170_CLK_PLL3, - imx_clk_pllv3(IMX_PLLV3_GENERICV2, "pll3_sys", "osc", + imx_clk_pllv3(dev, IMX_PLLV3_GENERICV2, "pll3_sys", "osc", base + 0x210, 1)); clk_dm(IMXRT1170_CLK_PLL2, - imx_clk_pllv3(IMX_PLLV3_GENERICV2, "pll2_sys", "osc", + imx_clk_pllv3(dev, IMX_PLLV3_GENERICV2, "pll2_sys", "osc", base + 0x240, 1)); clk_dm(IMXRT1170_CLK_PLL3_PFD0, @@ -149,7 +149,7 @@ static int imxrt1170_clk_probe(struct udevice *dev) imx_clk_pfd("pll2_pfd3", "pll2_sys", base + 0x270, 3)); clk_dm(IMXRT1170_CLK_PLL3_DIV2, - imx_clk_fixed_factor("pll3_div2", "pll3_sys", 1, 2)); + imx_clk_fixed_factor(dev, "pll3_div2", "pll3_sys", 1, 2)); /* CCM clocks */ base = dev_read_addr_ptr(dev); @@ -157,31 +157,31 @@ static int imxrt1170_clk_probe(struct udevice *dev) return -EINVAL; clk_dm(IMXRT1170_CLK_LPUART1_SEL, - imx_clk_mux("lpuart1_sel", base + (25 * 0x80), 8, 3, + imx_clk_mux(dev, "lpuart1_sel", base + (25 * 0x80), 8, 3, lpuart1_sels, ARRAY_SIZE(lpuart1_sels))); clk_dm(IMXRT1170_CLK_LPUART1, - imx_clk_divider("lpuart1", "lpuart1_sel", + imx_clk_divider(dev, "lpuart1", "lpuart1_sel", base + (25 * 0x80), 0, 8)); clk_dm(IMXRT1170_CLK_USDHC1_SEL, - imx_clk_mux("usdhc1_sel", base + (58 * 0x80), 8, 3, + imx_clk_mux(dev, "usdhc1_sel", base + (58 * 0x80), 8, 3, usdhc1_sels, ARRAY_SIZE(usdhc1_sels))); clk_dm(IMXRT1170_CLK_USDHC1, - imx_clk_divider("usdhc1", "usdhc1_sel", + imx_clk_divider(dev, "usdhc1", "usdhc1_sel", base + (58 * 0x80), 0, 8)); clk_dm(IMXRT1170_CLK_GPT1_SEL, - imx_clk_mux("gpt1_sel", base + (14 * 0x80), 8, 3, + imx_clk_mux(dev, "gpt1_sel", base + (14 * 0x80), 8, 3, gpt1_sels, ARRAY_SIZE(gpt1_sels))); clk_dm(IMXRT1170_CLK_GPT1, - imx_clk_divider("gpt1", "gpt1_sel", + imx_clk_divider(dev, "gpt1", "gpt1_sel", base + (14 * 0x80), 0, 8)); clk_dm(IMXRT1170_CLK_SEMC_SEL, - imx_clk_mux("semc_sel", base + (4 * 0x80), 8, 3, + imx_clk_mux(dev, "semc_sel", base + (4 * 0x80), 8, 3, semc_sels, ARRAY_SIZE(semc_sels))); clk_dm(IMXRT1170_CLK_SEMC, - imx_clk_divider("semc", "semc_sel", + imx_clk_divider(dev, "semc", "semc_sel", base + (4 * 0x80), 0, 8)); struct clk *clk, *clk1; diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c index c6692f2f9f5..85b6a9809e8 100644 --- a/drivers/clk/imx/clk-pllv3.c +++ b/drivers/clk/imx/clk-pllv3.c @@ -281,9 +281,9 @@ static const struct clk_ops clk_pllv3_enet_ops = { .get_rate = clk_pllv3_enet_get_rate, }; -struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, - const char *parent_name, void __iomem *base, - u32 div_mask) +struct clk *imx_clk_pllv3(struct udevice *dev, enum imx_pllv3_type type, + const char *name, const char *parent_name, + void __iomem *base, u32 div_mask) { struct clk_pllv3 *pll; struct clk *clk; @@ -339,7 +339,8 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, pll->div_mask = div_mask; clk = &pll->clk; - ret = clk_register(clk, drv_name, name, parent_name); + ret = clk_register(clk, drv_name, name, + clk_resolve_parent_clk(dev, parent_name)); if (ret) { kfree(pll); return ERR_PTR(ret); diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index 27a53ae5583..7d14dbc395f 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -78,84 +78,89 @@ struct clk *imx_clk_pll14xx(const char *name, const char *parent_name, void __iomem *base, const struct imx_pll14xx_clk *pll_clk); -struct clk *clk_register_gate2(struct device *dev, const char *name, +struct clk *clk_register_gate2(struct udevice *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 bit_idx, u8 cgr_val, u8 clk_gate_flags, unsigned int *share_count); -struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, - const char *parent_name, void __iomem *base, - u32 div_mask); +struct clk *imx_clk_pllv3(struct udevice *dev, enum imx_pllv3_type type, + const char *name, const char *parent_name, + void __iomem *base, u32 div_mask); -static inline struct clk *imx_clk_gate2(const char *name, const char *parent, - void __iomem *reg, u8 shift) +static inline struct clk *imx_clk_gate2(struct udevice *dev, const char *name, + const char *parent, void __iomem *reg, + u8 shift) { - return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg, + return clk_register_gate2(dev, name, parent, CLK_SET_RATE_PARENT, reg, shift, 0x3, 0, NULL); } -static inline struct clk *imx_clk_gate2_shared(const char *name, +static inline struct clk *imx_clk_gate2_shared(struct udevice *dev, const char *name, const char *parent, void __iomem *reg, u8 shift, unsigned int *share_count) { - return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg, + return clk_register_gate2(dev, name, parent, CLK_SET_RATE_PARENT, reg, shift, 0x3, 0, share_count); } -static inline struct clk *imx_clk_gate2_shared2(const char *name, +static inline struct clk *imx_clk_gate2_shared2(struct udevice *dev, const char *name, const char *parent, void __iomem *reg, u8 shift, unsigned int *share_count) { - return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT | + return clk_register_gate2(dev, name, parent, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, reg, shift, 0x3, 0, share_count); } -static inline struct clk *imx_clk_gate4(const char *name, const char *parent, +static inline struct clk *imx_clk_gate4(struct udevice *dev, const char *name, const char *parent, void __iomem *reg, u8 shift) { - return clk_register_gate2(NULL, name, parent, + return clk_register_gate2(dev, name, parent, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, reg, shift, 0x3, 0, NULL); } -static inline struct clk *imx_clk_gate4_flags(const char *name, +static inline struct clk *imx_clk_gate4_flags(struct udevice *dev, const char *name, const char *parent, void __iomem *reg, u8 shift, unsigned long flags) { - return clk_register_gate2(NULL, name, parent, + return clk_register_gate2(dev, name, parent, flags | CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, reg, shift, 0x3, 0, NULL); } -static inline struct clk *imx_clk_fixed_factor(const char *name, - const char *parent, unsigned int mult, unsigned int div) +static inline struct clk * +imx_clk_fixed_factor(struct udevice *dev, const char *name, const char *parent, + unsigned int mult, unsigned int div) { - return clk_register_fixed_factor(NULL, name, parent, + return clk_register_fixed_factor(dev, name, parent, CLK_SET_RATE_PARENT, mult, div); } -static inline struct clk *imx_clk_divider(const char *name, const char *parent, - void __iomem *reg, u8 shift, u8 width) +static inline struct clk *imx_clk_divider(struct udevice *dev, const char *name, + const char *parent, void __iomem *reg, + u8 shift, u8 width) { - return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT, + return clk_register_divider(dev, name, parent, CLK_SET_RATE_PARENT, reg, shift, width, 0); } static inline struct clk * -imx_clk_busy_divider(const char *name, const char *parent, void __iomem *reg, - u8 shift, u8 width, void __iomem *busy_reg, u8 busy_shift) +imx_clk_busy_divider(struct udevice *dev, const char *name, + const char *parent, void __iomem *reg, u8 shift, u8 width, + void __iomem *busy_reg, u8 busy_shift) { - return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT, + return clk_register_divider(dev, name, parent, CLK_SET_RATE_PARENT, reg, shift, width, 0); } -static inline struct clk *imx_clk_divider2(const char *name, const char *parent, - void __iomem *reg, u8 shift, u8 width) +static inline struct clk *imx_clk_divider2(struct udevice *dev, const char *name, + const char *parent, void __iomem *reg, + u8 shift, u8 width) { - return clk_register_divider(NULL, name, parent, + return clk_register_divider(dev, name, parent, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, reg, shift, width, 0); } @@ -167,90 +172,93 @@ struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg, u8 shift, u8 width, const char * const *parents, int num_parents, void (*fixup)(u32 *val)); -static inline struct clk *imx_clk_mux_flags(const char *name, +static inline struct clk *imx_clk_mux_flags(struct udevice *dev, const char *name, void __iomem *reg, u8 shift, u8 width, const char * const *parents, int num_parents, unsigned long flags) { - return clk_register_mux(NULL, name, parents, num_parents, + return clk_register_mux(dev, name, parents, num_parents, flags | CLK_SET_RATE_NO_REPARENT, reg, shift, width, 0); } -static inline struct clk *imx_clk_mux2_flags(const char *name, +static inline struct clk *imx_clk_mux2_flags(struct udevice *dev, const char *name, void __iomem *reg, u8 shift, u8 width, const char * const *parents, int num_parents, unsigned long flags) { - return clk_register_mux(NULL, name, parents, num_parents, + return clk_register_mux(dev, name, parents, num_parents, flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE, reg, shift, width, 0); } -static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg, - u8 shift, u8 width, const char * const *parents, +static inline struct clk *imx_clk_mux(struct udevice *dev, const char *name, + void __iomem *reg, u8 shift, u8 width, const char * const *parents, int num_parents) { - return clk_register_mux(NULL, name, parents, num_parents, + return clk_register_mux(dev, name, parents, num_parents, CLK_SET_RATE_NO_REPARENT, reg, shift, width, 0); } static inline struct clk * -imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift, u8 width, +imx_clk_busy_mux(struct udevice *dev, const char *name, void __iomem *reg, u8 shift, u8 width, void __iomem *busy_reg, u8 busy_shift, const char * const *parents, int num_parents) { - return clk_register_mux(NULL, name, parents, num_parents, + return clk_register_mux(dev, name, parents, num_parents, CLK_SET_RATE_NO_REPARENT, reg, shift, width, 0); } -static inline struct clk *imx_clk_mux2(const char *name, void __iomem *reg, +static inline struct clk *imx_clk_mux2(struct udevice *dev, const char *name, void __iomem *reg, u8 shift, u8 width, const char * const *parents, int num_parents) { - return clk_register_mux(NULL, name, parents, num_parents, + return clk_register_mux(dev, name, parents, num_parents, CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE, reg, shift, width, 0); } -static inline struct clk *imx_clk_gate(const char *name, const char *parent, - void __iomem *reg, u8 shift) +static inline struct clk *imx_clk_gate(struct udevice *dev, const char *name, + const char *parent, void __iomem *reg, + u8 shift) { - return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg, + return clk_register_gate(dev, name, parent, CLK_SET_RATE_PARENT, reg, shift, 0, NULL); } -static inline struct clk *imx_clk_gate_flags(const char *name, const char *parent, - void __iomem *reg, u8 shift, unsigned long flags) +static inline struct clk *imx_clk_gate_flags(struct udevice *dev, const char *name, + const char *parent, void __iomem *reg, + u8 shift, unsigned long flags) { - return clk_register_gate(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg, + return clk_register_gate(dev, name, parent, flags | CLK_SET_RATE_PARENT, reg, shift, 0, NULL); } -static inline struct clk *imx_clk_gate3(const char *name, const char *parent, - void __iomem *reg, u8 shift) +static inline struct clk *imx_clk_gate3(struct udevice *dev, const char *name, + const char *parent, void __iomem *reg, + u8 shift) { - return clk_register_gate(NULL, name, parent, + return clk_register_gate(dev, name, parent, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, reg, shift, 0, NULL); } -struct clk *imx8m_clk_composite_flags(const char *name, +struct clk *imx8m_clk_composite_flags(struct udevice *dev, const char *name, const char * const *parent_names, int num_parents, void __iomem *reg, unsigned long flags); -#define __imx8m_clk_composite(name, parent_names, reg, flags) \ - imx8m_clk_composite_flags(name, parent_names, \ +#define __imx8m_clk_composite(dev, name, parent_names, reg, flags) \ + imx8m_clk_composite_flags(dev, name, parent_names, \ ARRAY_SIZE(parent_names), reg, \ flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE) -#define imx8m_clk_composite(name, parent_names, reg) \ - __imx8m_clk_composite(name, parent_names, reg, 0) +#define imx8m_clk_composite(dev, name, parent_names, reg) \ + __imx8m_clk_composite(dev, name, parent_names, reg, 0) -#define imx8m_clk_composite_critical(name, parent_names, reg) \ - __imx8m_clk_composite(name, parent_names, reg, CLK_IS_CRITICAL) +#define imx8m_clk_composite_critical(dev, name, parent_names, reg) \ + __imx8m_clk_composite(dev, name, parent_names, reg, CLK_IS_CRITICAL) struct clk *imx93_clk_composite_flags(const char *name, const char * const *parent_names, diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index cb867acc48c..3ea01f3c969 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -31,6 +31,14 @@ config CLK_QCOM_IPQ4019 on the Snapdragon IPQ4019 SoC. This driver supports the clocks and resets exposed by the GCC hardware block. +config CLK_QCOM_IPQ9574 + bool "Qualcomm IPQ9574 GCC" + select CLK_QCOM + help + Say Y here to enable support for the Global Clock Controller + on the Snapdragon IPQ9574 SoC. This driver supports the clocks + and resets exposed by the GCC hardware block. + config CLK_QCOM_QCM2290 bool "Qualcomm QCM2290 GCC" select CLK_QCOM diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 1bc0f15005b..e13fc8c1071 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_CLK_QCOM_SDM845) += clock-sdm845.o obj-$(CONFIG_CLK_QCOM_APQ8016) += clock-apq8016.o obj-$(CONFIG_CLK_QCOM_APQ8096) += clock-apq8096.o obj-$(CONFIG_CLK_QCOM_IPQ4019) += clock-ipq4019.o +obj-$(CONFIG_CLK_QCOM_IPQ9574) += clock-ipq9574.o obj-$(CONFIG_CLK_QCOM_QCM2290) += clock-qcm2290.o obj-$(CONFIG_CLK_QCOM_QCS404) += clock-qcs404.o obj-$(CONFIG_CLK_QCOM_SA8775P) += clock-sa8775p.o diff --git a/drivers/clk/qcom/clock-apq8016.c b/drivers/clk/qcom/clock-apq8016.c index b5def55dbc2..6a53f900a9e 100644 --- a/drivers/clk/qcom/clock-apq8016.c +++ b/drivers/clk/qcom/clock-apq8016.c @@ -54,8 +54,9 @@ static struct vote_clk gcc_blsp1_ahb_clk = { }; static const struct gate_clk apq8016_clks[] = { - GATE_CLK(GCC_USB_HS_AHB_CLK, 0x41008, 0x00000001), - GATE_CLK(GCC_USB_HS_SYSTEM_CLK, 0x41004, 0x00000001), + GATE_CLK(GCC_PRNG_AHB_CLK, 0x45004, BIT(8)), + GATE_CLK(GCC_USB_HS_AHB_CLK, 0x41008, BIT(0)), + GATE_CLK(GCC_USB_HS_SYSTEM_CLK, 0x41004, BIT(0)), }; /* SDHCI */ @@ -139,15 +140,14 @@ static int apq8016_clk_enable(struct clk *clk) { struct msm_clk_priv *priv = dev_get_priv(clk->dev); - if (priv->data->num_clks < clk->id) { + if (priv->data->num_clks < clk->id || !apq8016_clks[clk->id].reg) { log_warning("%s: unknown clk id %lu\n", __func__, clk->id); return 0; } - debug("%s: clk %s\n", __func__, apq8016_clks[clk->id].name); - qcom_gate_clk_en(priv, clk->id); + debug("%s: enabling clock %s\n", __func__, apq8016_clks[clk->id].name); - return 0; + return qcom_gate_clk_en(priv, clk->id); } static struct msm_clk_data apq8016_clk_data = { diff --git a/drivers/clk/qcom/clock-ipq9574.c b/drivers/clk/qcom/clock-ipq9574.c new file mode 100644 index 00000000000..b0af4036059 --- /dev/null +++ b/drivers/clk/qcom/clock-ipq9574.c @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Clock drivers for Qualcomm ipq9574 + * + * (C) Copyright 2025 Linaro Ltd. + */ + +#include <linux/types.h> +#include <clk-uclass.h> +#include <dm.h> +#include <linux/delay.h> +#include <asm/io.h> +#include <linux/bug.h> +#include <linux/bitops.h> +#include <dt-bindings/clock/qcom,ipq9574-gcc.h> +#include <dt-bindings/reset/qcom,ipq9574-gcc.h> + +#include "clock-qcom.h" + +#define GCC_BLSP1_AHB_CBCR 0x1004 +#define GCC_BLSP1_UART3_APPS_CMD_RCGR 0x402C +#define GCC_BLSP1_UART3_APPS_CBCR 0x4054 + +#define GCC_SDCC1_APPS_CBCR 0x3302C +#define GCC_SDCC1_AHB_CBCR 0x33034 +#define GCC_SDCC1_APPS_CMD_RCGR 0x33004 +#define GCC_SDCC1_ICE_CORE_CBCR 0x33030 + +static ulong ipq9574_set_rate(struct clk *clk, ulong rate) +{ + struct msm_clk_priv *priv = dev_get_priv(clk->dev); + + switch (clk->id) { + case GCC_BLSP1_UART3_APPS_CLK: + clk_rcg_set_rate_mnd(priv->base, GCC_BLSP1_UART3_APPS_CMD_RCGR, + 0, 144, 15625, CFG_CLK_SRC_GPLL0, 16); + return rate; + case GCC_SDCC1_APPS_CLK: + clk_rcg_set_rate_mnd(priv->base, GCC_SDCC1_APPS_CMD_RCGR, + 11, 0, 0, CFG_CLK_SRC_GPLL2, 16); + return rate; + default: + return -EINVAL; + } +} + +static const struct gate_clk ipq9574_clks[] = { + GATE_CLK(GCC_BLSP1_UART3_APPS_CLK, 0x4054, 0x00000001), + GATE_CLK(GCC_BLSP1_AHB_CLK, 0x1004, 0x00000001), + GATE_CLK(GCC_SDCC1_AHB_CLK, 0x33034, 0x00000001), + GATE_CLK(GCC_SDCC1_APPS_CLK, 0x3302C, 0x00000001), + GATE_CLK(GCC_SDCC1_ICE_CORE_CLK, 0x33030, 0x00000001), +}; + +static int ipq9574_enable(struct clk *clk) +{ + struct msm_clk_priv *priv = dev_get_priv(clk->dev); + + debug("%s: clk %s\n", __func__, ipq9574_clks[clk->id].name); + + if (!ipq9574_clks[clk->id].reg) + return -EINVAL; + + qcom_gate_clk_en(priv, clk->id); + + return 0; +} + +static const struct qcom_reset_map ipq9574_gcc_resets[] = { + [GCC_SDCC_BCR] = { 0x33000 }, +}; + +static struct msm_clk_data ipq9574_gcc_data = { + .resets = ipq9574_gcc_resets, + .num_resets = ARRAY_SIZE(ipq9574_gcc_resets), + .enable = ipq9574_enable, + .set_rate = ipq9574_set_rate, +}; + +static const struct udevice_id gcc_ipq9574_of_match[] = { + { + .compatible = "qcom,ipq9574-gcc", + .data = (ulong)&ipq9574_gcc_data, + }, + { } +}; + +U_BOOT_DRIVER(gcc_ipq9574) = { + .name = "gcc_ipq9574", + .id = UCLASS_NOP, + .of_match = gcc_ipq9574_of_match, + .bind = qcom_cc_bind, + .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF, +}; diff --git a/drivers/clk/qcom/clock-qcm2290.c b/drivers/clk/qcom/clock-qcm2290.c index c78705cb8cf..1326b770c3e 100644 --- a/drivers/clk/qcom/clock-qcm2290.c +++ b/drivers/clk/qcom/clock-qcm2290.c @@ -134,9 +134,7 @@ static int qcm2290_enable(struct clk *clk) break; } - qcom_gate_clk_en(priv, clk->id); - - return 0; + return qcom_gate_clk_en(priv, clk->id); } static const struct qcom_reset_map qcm2290_gcc_resets[] = { diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h index ff336dea39c..f43edea2525 100644 --- a/drivers/clk/qcom/clock-qcom.h +++ b/drivers/clk/qcom/clock-qcom.h @@ -7,10 +7,12 @@ #include <asm/io.h> #include <linux/bitfield.h> +#include <errno.h> #define CFG_CLK_SRC_CXO (0 << 8) #define CFG_CLK_SRC_GPLL0 (1 << 8) #define CFG_CLK_SRC_GPLL0_AUX2 (2 << 8) +#define CFG_CLK_SRC_GPLL2 (2 << 8) #define CFG_CLK_SRC_GPLL9 (2 << 8) #define CFG_CLK_SRC_GPLL0_ODD (3 << 8) #define CFG_CLK_SRC_GPLL6 (4 << 8) @@ -105,14 +107,19 @@ void clk_rcg_set_rate(phys_addr_t base, uint32_t cmd_rcgr, int div, int source); void clk_phy_mux_enable(phys_addr_t base, uint32_t cmd_rcgr, bool enabled); -static inline void qcom_gate_clk_en(const struct msm_clk_priv *priv, unsigned long id) +static inline int qcom_gate_clk_en(const struct msm_clk_priv *priv, unsigned long id) { u32 val; - if (id >= priv->data->num_clks || priv->data->clks[id].reg == 0) - return; + if (id >= priv->data->num_clks || priv->data->clks[id].reg == 0) { + log_err("gcc@%#08llx: unknown clock ID %lu!\n", + priv->base, id); + return -ENOENT; + } val = readl(priv->base + priv->data->clks[id].reg); writel(val | priv->data->clks[id].en_val, priv->base + priv->data->clks[id].reg); + + return 0; } #endif diff --git a/drivers/clk/qcom/clock-sa8775p.c b/drivers/clk/qcom/clock-sa8775p.c index e31f24ed4f0..527cecf5c82 100644 --- a/drivers/clk/qcom/clock-sa8775p.c +++ b/drivers/clk/qcom/clock-sa8775p.c @@ -73,9 +73,7 @@ static int sa8775p_enable(struct clk *clk) break; } - qcom_gate_clk_en(priv, clk->id); - - return 0; + return qcom_gate_clk_en(priv, clk->id); } static const struct qcom_reset_map sa8775p_gcc_resets[] = { diff --git a/drivers/clk/qcom/clock-sc7280.c b/drivers/clk/qcom/clock-sc7280.c index 5d343f12051..8691f08109b 100644 --- a/drivers/clk/qcom/clock-sc7280.c +++ b/drivers/clk/qcom/clock-sc7280.c @@ -16,29 +16,64 @@ #include "clock-qcom.h" -#define USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR 0xf038 #define USB30_PRIM_MASTER_CLK_CMD_RCGR 0xf020 +#define USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR 0xf038 +#define USB30_SEC_MASTER_CLK_CMD_RCGR 0x9e020 +#define USB30_SEC_MOCK_UTMI_CLK_CMD_RCGR 0x9e038 +#define PCIE_1_AUX_CLK_CMD_RCGR 0x8d058 +#define PCIE1_PHY_RCHNG_CMD_RCGR 0x8d03c +#define PCIE_1_PIPE_CLK_PHY_MUX 0x8d054 + +static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { + F(66666667, CFG_CLK_SRC_GPLL0_EVEN, 4.5, 0, 0), + F(133333333, CFG_CLK_SRC_GPLL0, 4.5, 0, 0), + F(200000000, CFG_CLK_SRC_GPLL0_ODD, 1, 0, 0), + F(240000000, CFG_CLK_SRC_GPLL0, 2.5, 0, 0), + { } +}; + +static const struct freq_tbl ftbl_gcc_usb30_sec_master_clk_src[] = { + F(60000000, CFG_CLK_SRC_GPLL0_EVEN, 5, 0, 0), + F(120000000, CFG_CLK_SRC_GPLL0_EVEN, 2.5, 0, 0), + { } +}; static ulong sc7280_set_rate(struct clk *clk, ulong rate) { struct msm_clk_priv *priv = dev_get_priv(clk->dev); + const struct freq_tbl *freq; if (clk->id < priv->data->num_clks) debug("%s: %s, requested rate=%ld\n", __func__, priv->data->clks[clk->id].name, rate); switch (clk->id) { - case GCC_USB30_PRIM_MOCK_UTMI_CLK: - WARN(rate != 19200000, "Unexpected rate for USB30_PRIM_MOCK_UTMI_CLK: %lu\n", rate); - clk_rcg_set_rate(priv->base, USB30_PRIM_MASTER_CLK_CMD_RCGR, 0, CFG_CLK_SRC_CXO); - return rate; case GCC_USB30_PRIM_MASTER_CLK: - WARN(rate != 200000000, "Unexpected rate for USB30_PRIM_MASTER_CLK: %lu\n", rate); + freq = qcom_find_freq(ftbl_gcc_usb30_prim_master_clk_src, rate); clk_rcg_set_rate_mnd(priv->base, USB30_PRIM_MASTER_CLK_CMD_RCGR, - 1, 0, 0, CFG_CLK_SRC_GPLL0_ODD, 8); - clk_rcg_set_rate(priv->base, 0xf064, 0, 0); - return rate; + freq->pre_div, freq->m, freq->n, freq->src, 8); + return freq->freq; + case GCC_USB30_PRIM_MOCK_UTMI_CLK: + clk_rcg_set_rate(priv->base, USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR, 1, 0); + return 19200000; + case GCC_USB3_PRIM_PHY_AUX_CLK_SRC: + clk_rcg_set_rate(priv->base, USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR, 1, 0); + return 19200000; + case GCC_USB30_SEC_MASTER_CLK: + freq = qcom_find_freq(ftbl_gcc_usb30_sec_master_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, USB30_SEC_MASTER_CLK_CMD_RCGR, + freq->pre_div, freq->m, freq->n, freq->src, 8); + return freq->freq; + case GCC_USB30_SEC_MOCK_UTMI_CLK: + clk_rcg_set_rate(priv->base, USB30_SEC_MOCK_UTMI_CLK_CMD_RCGR, 1, 0); + return 19200000; + case GCC_USB3_SEC_PHY_AUX_CLK_SRC: + clk_rcg_set_rate(priv->base, USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR, 1, 0); + return 19200000; + case GCC_PCIE1_PHY_RCHNG_CLK: + clk_rcg_set_rate(priv->base, PCIE1_PHY_RCHNG_CMD_RCGR, 5, CFG_CLK_SRC_GPLL0_EVEN); + return 100000000; default: - return 0; + return rate; } } @@ -50,13 +85,35 @@ static const struct gate_clk sc7280_clks[] = { GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0xf01c, 1), GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK, 0xf054, 1), GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0xf058, 1), + GATE_CLK(GCC_CFG_NOC_USB3_SEC_AXI_CLK, 0x9e07c, 1), + GATE_CLK(GCC_USB30_SEC_MASTER_CLK, 0x9e010, 1), + GATE_CLK(GCC_AGGRE_USB3_SEC_AXI_CLK, 0x9e080, 1), + GATE_CLK(GCC_USB30_SEC_SLEEP_CLK, 0x9e018, 1), + GATE_CLK(GCC_USB30_SEC_MOCK_UTMI_CLK, 0x9e01c, 1), + GATE_CLK(GCC_USB3_SEC_PHY_AUX_CLK, 0x9e054, 1), + GATE_CLK(GCC_USB3_SEC_PHY_COM_AUX_CLK, 0x9e058, 1), + GATE_CLK(GCC_PCIE_CLKREF_EN, 0x8c004, 1), + GATE_CLK(GCC_PCIE_1_PIPE_CLK, 0x52000, BIT(30)), + GATE_CLK(GCC_PCIE_1_AUX_CLK, 0x52000, BIT(29)), + GATE_CLK(GCC_PCIE_1_CFG_AHB_CLK, 0x52000, BIT(28)), + GATE_CLK(GCC_PCIE_1_MSTR_AXI_CLK, 0x52000, BIT(27)), + GATE_CLK(GCC_PCIE_1_SLV_AXI_CLK, 0x52000, BIT(26)), + GATE_CLK(GCC_PCIE_1_SLV_Q2A_AXI_CLK, 0x52000, BIT(25)), + GATE_CLK(GCC_PCIE1_PHY_RCHNG_CLK, 0x52000, BIT(23)), + GATE_CLK(GCC_DDRSS_PCIE_SF_CLK, 0x52000, BIT(19)), + GATE_CLK(GCC_AGGRE_NOC_PCIE_TBU_CLK, 0x52000, BIT(18)), + GATE_CLK(GCC_AGGRE_NOC_PCIE_1_AXI_CLK, 0x52000, BIT(11)), + GATE_CLK(GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK, 0x52008, BIT(28)), + GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK, 0x52008, BIT(10)), + GATE_CLK(GCC_QUPV3_WRAP0_S1_CLK, 0x52008, BIT(11)), + GATE_CLK(GCC_QUPV3_WRAP0_S3_CLK, 0x52008, BIT(13)), }; static int sc7280_enable(struct clk *clk) { struct msm_clk_priv *priv = dev_get_priv(clk->dev); - if (priv->data->num_clks < clk->id) { + if (priv->data->num_clks <= clk->id) { debug("%s: unknown clk id %lu\n", __func__, clk->id); return 0; } @@ -71,11 +128,32 @@ static int sc7280_enable(struct clk *clk) qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_AUX_CLK); qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_COM_AUX_CLK); break; + case GCC_AGGRE_USB3_SEC_AXI_CLK: + qcom_gate_clk_en(priv, GCC_USB30_SEC_MASTER_CLK); + fallthrough; + case GCC_USB30_SEC_MASTER_CLK: + qcom_gate_clk_en(priv, GCC_USB3_SEC_PHY_AUX_CLK); + qcom_gate_clk_en(priv, GCC_USB3_SEC_PHY_COM_AUX_CLK); + break; + case GCC_PCIE_1_PIPE_CLK: + clk_phy_mux_enable(priv->base, PCIE_1_PIPE_CLK_PHY_MUX, true); + break; + case GCC_PCIE_1_AUX_CLK: + clk_rcg_set_rate_mnd(priv->base, PCIE_1_AUX_CLK_CMD_RCGR, 1, 0, 0, + CFG_CLK_SRC_CXO, 16); + break; + case GCC_QUPV3_WRAP0_S0_CLK: + clk_rcg_set_rate_mnd(priv->base, 0x17010, 1, 0, 0, CFG_CLK_SRC_CXO, 16); + break; + case GCC_QUPV3_WRAP0_S1_CLK: + clk_rcg_set_rate_mnd(priv->base, 0x17140, 1, 0, 0, CFG_CLK_SRC_CXO, 16); + break; + case GCC_QUPV3_WRAP0_S3_CLK: + clk_rcg_set_rate_mnd(priv->base, 0x173a0, 1, 0, 0, CFG_CLK_SRC_CXO, 16); + break; } - qcom_gate_clk_en(priv, clk->id); - - return 0; + return qcom_gate_clk_en(priv, clk->id); } static const struct qcom_reset_map sc7280_gcc_resets[] = { @@ -100,6 +178,20 @@ static const struct qcom_reset_map sc7280_gcc_resets[] = { static const struct qcom_power_map sc7280_gdscs[] = { [GCC_UFS_PHY_GDSC] = { 0x77004 }, [GCC_USB30_PRIM_GDSC] = { 0xf004 }, + [GCC_USB30_SEC_GDSC] = { 0x9e004 }, + [GCC_PCIE_1_GDSC] = { 0x8d004 }, +}; + +static const phys_addr_t sc7280_rcg_addrs[] = { + 0x10f020, // USB30_PRIM_MASTER_CLK_CMD_RCGR + 0x10f038, // USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR + 0x18d058, // PCIE_1_AUX_CLK_CMD_RCGR +}; + +static const char *const sc7280_rcg_names[] = { + "USB30_PRIM_MASTER_CLK_SRC", + "USB30_PRIM_MOCK_UTMI_CLK_SRC", + "GCC_PCIE_1_AUX_CLK_SRC", }; static struct msm_clk_data qcs404_gcc_data = { @@ -113,6 +205,10 @@ static struct msm_clk_data qcs404_gcc_data = { .enable = sc7280_enable, .set_rate = sc7280_set_rate, + + .dbg_rcg_addrs = sc7280_rcg_addrs, + .num_rcgs = ARRAY_SIZE(sc7280_rcg_addrs), + .dbg_rcg_names = sc7280_rcg_names, }; static const struct udevice_id gcc_sc7280_of_match[] = { diff --git a/drivers/clk/qcom/clock-sdm845.c b/drivers/clk/qcom/clock-sdm845.c index adffb0cb240..6a0bf16ba2d 100644 --- a/drivers/clk/qcom/clock-sdm845.c +++ b/drivers/clk/qcom/clock-sdm845.c @@ -162,9 +162,7 @@ static int sdm845_clk_enable(struct clk *clk) break; } - qcom_gate_clk_en(priv, clk->id); - - return 0; + return qcom_gate_clk_en(priv, clk->id); } static const struct qcom_reset_map sdm845_gcc_resets[] = { diff --git a/drivers/clk/qcom/clock-sm6115.c b/drivers/clk/qcom/clock-sm6115.c index 9057dfe0bb1..17c2e561758 100644 --- a/drivers/clk/qcom/clock-sm6115.c +++ b/drivers/clk/qcom/clock-sm6115.c @@ -146,9 +146,7 @@ static int sm6115_enable(struct clk *clk) break; } - qcom_gate_clk_en(priv, clk->id); - - return 0; + return qcom_gate_clk_en(priv, clk->id); } static const struct qcom_reset_map sm6115_gcc_resets[] = { diff --git a/drivers/clk/qcom/clock-sm8150.c b/drivers/clk/qcom/clock-sm8150.c index 88f2e678f43..7dd0d56eb43 100644 --- a/drivers/clk/qcom/clock-sm8150.c +++ b/drivers/clk/qcom/clock-sm8150.c @@ -243,9 +243,7 @@ static int sm8150_clk_enable(struct clk *clk) break; }; - qcom_gate_clk_en(priv, clk->id); - - return 0; + return qcom_gate_clk_en(priv, clk->id); } static const struct qcom_reset_map sm8150_gcc_resets[] = { diff --git a/drivers/clk/qcom/clock-sm8250.c b/drivers/clk/qcom/clock-sm8250.c index e322a923a5c..26396847d85 100644 --- a/drivers/clk/qcom/clock-sm8250.c +++ b/drivers/clk/qcom/clock-sm8250.c @@ -195,9 +195,7 @@ static int sm8250_enable(struct clk *clk) break; } - qcom_gate_clk_en(priv, clk->id); - - return 0; + return qcom_gate_clk_en(priv, clk->id); } static const struct qcom_reset_map sm8250_gcc_resets[] = { diff --git a/drivers/clk/qcom/clock-sm8550.c b/drivers/clk/qcom/clock-sm8550.c index 62b5a409e8e..7c06489b9c4 100644 --- a/drivers/clk/qcom/clock-sm8550.c +++ b/drivers/clk/qcom/clock-sm8550.c @@ -220,9 +220,7 @@ static int sm8550_enable(struct clk *clk) break; } - qcom_gate_clk_en(priv, clk->id); - - return 0; + return qcom_gate_clk_en(priv, clk->id); } static const struct qcom_reset_map sm8550_gcc_resets[] = { diff --git a/drivers/clk/qcom/clock-sm8650.c b/drivers/clk/qcom/clock-sm8650.c index 9baaecb571f..364454644a6 100644 --- a/drivers/clk/qcom/clock-sm8650.c +++ b/drivers/clk/qcom/clock-sm8650.c @@ -217,9 +217,7 @@ static int sm8650_enable(struct clk *clk) break; } - qcom_gate_clk_en(priv, clk->id); - - return 0; + return qcom_gate_clk_en(priv, clk->id); } static const struct qcom_reset_map sm8650_gcc_resets[] = { diff --git a/drivers/clk/qcom/clock-x1e80100.c b/drivers/clk/qcom/clock-x1e80100.c index bd9c6ed1c8a..542d6248d65 100644 --- a/drivers/clk/qcom/clock-x1e80100.c +++ b/drivers/clk/qcom/clock-x1e80100.c @@ -174,9 +174,7 @@ static int x1e80100_enable(struct clk *clk) break; } - qcom_gate_clk_en(priv, clk->id); - - return 0; + return qcom_gate_clk_en(priv, clk->id); } static const struct qcom_reset_map x1e80100_gcc_resets[] = { diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c index 53d31b3c0bf..4e1eccaa5b0 100644 --- a/drivers/cpu/imx8_cpu.c +++ b/drivers/cpu/imx8_cpu.c @@ -35,11 +35,49 @@ static const char *get_imx_type_str(u32 imxtype) { switch (imxtype) { case MXC_CPU_IMX8MM: - return "8MM"; + return "8MMQ"; /* Quad-core version of the imx8mm */ + case MXC_CPU_IMX8MML: + return "8MMQL"; /* Quad-core Lite version of the imx8mm */ + case MXC_CPU_IMX8MMD: + return "8MMD"; /* Dual-core version of the imx8mm */ + case MXC_CPU_IMX8MMDL: + return "8MMDL"; /* Dual-core Lite version of the imx8mm */ + case MXC_CPU_IMX8MMS: + return "8MMS"; /* Single-core version of the imx8mm */ + case MXC_CPU_IMX8MMSL: + return "8MMSL"; /* Single-core Lite version of the imx8mm */ case MXC_CPU_IMX8MN: - return "8MN"; + return "8MNano Quad"; /* Quad-core version */ + case MXC_CPU_IMX8MND: + return "8MNano Dual"; /* Dual-core version */ + case MXC_CPU_IMX8MNS: + return "8MNano Solo"; /* Single-core version */ + case MXC_CPU_IMX8MNL: + return "8MNano QuadLite"; /* Quad-core Lite version */ + case MXC_CPU_IMX8MNDL: + return "8MNano DualLite"; /* Dual-core Lite version */ + case MXC_CPU_IMX8MNSL: + return "8MNano SoloLite";/* Single-core Lite version of the imx8mn */ + case MXC_CPU_IMX8MNUQ: + return "8MNano UltraLite Quad";/* Quad-core UltraLite version of the imx8mn */ + case MXC_CPU_IMX8MNUD: + return "8MNano UltraLite Dual";/* Dual-core UltraLite version of the imx8mn */ + case MXC_CPU_IMX8MNUS: + return "8MNano UltraLite Solo";/* Single-core UltraLite version of the imx8mn */ case MXC_CPU_IMX8MP: - return "8MP"; + return "8MP[8]"; /* Quad-core version of the imx8mp */ + case MXC_CPU_IMX8MPD: + return "8MP Dual[3]"; /* Dual-core version of the imx8mp */ + case MXC_CPU_IMX8MPL: + return "8MP Lite[4]"; /* Quad-core Lite version of the imx8mp */ + case MXC_CPU_IMX8MP6: + return "8MP[6]"; /* Quad-core version of the imx8mp, NPU fused */ + case MXC_CPU_IMX8MQ: + return "8MQ"; /* Quad-core version of the imx8mq */ + case MXC_CPU_IMX8MQL: + return "8MQLite"; /* Quad-core Lite version of the imx8mq */ + case MXC_CPU_IMX8MD: + return "8MD"; /* Dual-core version of the imx8mq */ case MXC_CPU_IMX8QXP: case MXC_CPU_IMX8QXP_A0: return "8QXP"; @@ -177,19 +215,19 @@ static int cpu_imx_get_desc(const struct udevice *dev, char *buf, int size) ret = snprintf(buf, size, "NXP i.MX%s Rev%s %s at %u MHz", plat->type, plat->rev, plat->name, plat->freq_mhz); - if (IS_ENABLED(CONFIG_IMX9)) { + if (IS_ENABLED(CONFIG_IMX_TMU)) { switch (get_cpu_temp_grade(&minc, &maxc)) { case TEMP_AUTOMOTIVE: - grade = "Automotive temperature grade "; + grade = "Automotive temperature grade"; break; case TEMP_INDUSTRIAL: - grade = "Industrial temperature grade "; + grade = "Industrial temperature grade"; break; case TEMP_EXTCOMMERCIAL: - grade = "Extended Consumer temperature grade "; + grade = "Extended Consumer temperature grade"; break; default: - grade = "Consumer temperature grade "; + grade = "Consumer temperature grade"; break; } diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig index 67d5ac1a742..4d9f004ebad 100644 --- a/drivers/mailbox/Kconfig +++ b/drivers/mailbox/Kconfig @@ -21,6 +21,13 @@ config APPLE_MBOX such as the System Management Controller (SMC) and NVMe and this driver is required to get that functionality up and running. +config IMX_MU_MBOX + bool "Enable i.MX MU MBOX support" + depends on DM_MAILBOX + help + Enable support for i.MX Messaging Unit for communication with other + processors on the SoC using mailbox interface + config SANDBOX_MBOX bool "Enable the sandbox mailbox test driver" depends on DM_MAILBOX && SANDBOX diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile index 6072fa1956b..574add60005 100644 --- a/drivers/mailbox/Makefile +++ b/drivers/mailbox/Makefile @@ -5,6 +5,7 @@ obj-$(CONFIG_$(XPL_)DM_MAILBOX) += mailbox-uclass.o obj-$(CONFIG_APPLE_MBOX) += apple-mbox.o +obj-$(CONFIG_IMX_MU_MBOX) += imx-mailbox.o obj-$(CONFIG_SANDBOX_MBOX) += sandbox-mbox.o obj-$(CONFIG_SANDBOX_MBOX) += sandbox-mbox-test.o obj-$(CONFIG_STM32_IPCC) += stm32-ipcc.o diff --git a/drivers/mailbox/imx-mailbox.c b/drivers/mailbox/imx-mailbox.c new file mode 100644 index 00000000000..b1e0465e7a8 --- /dev/null +++ b/drivers/mailbox/imx-mailbox.c @@ -0,0 +1,443 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025 NXP + */ + +#include <asm/io.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <mailbox-uclass.h> +#include <linux/bitfield.h> +#include <linux/bug.h> +#include <linux/iopoll.h> +#include <linux/compat.h> + +/* This driver only exposes the status bits to keep with the + * polling methodology of u-boot. + */ +DECLARE_GLOBAL_DATA_PTR; + +#define IMX_MU_CHANS 24 + +#define IMX_MU_V2_PAR_OFF 0x4 +#define IMX_MU_V2_TR_MASK GENMASK(7, 0) +#define IMX_MU_V2_RR_MASK GENMASK(15, 8) + +enum imx_mu_chan_type { + IMX_MU_TYPE_TX = 0, /* Tx */ + IMX_MU_TYPE_RX = 1, /* Rx */ + IMX_MU_TYPE_TXDB = 2, /* Tx doorbell */ + IMX_MU_TYPE_RXDB = 3, /* Rx doorbell */ + IMX_MU_TYPE_RST = 4, /* Reset */ + IMX_MU_TYPE_TXDB_V2 = 5, /* Tx doorbell with S/W ACK */ +}; + +enum imx_mu_xcr { + IMX_MU_CR, + IMX_MU_GIER, + IMX_MU_GCR, + IMX_MU_TCR, + IMX_MU_RCR, + IMX_MU_xCR_MAX, +}; + +enum imx_mu_xsr { + IMX_MU_SR, + IMX_MU_GSR, + IMX_MU_TSR, + IMX_MU_RSR, + IMX_MU_xSR_MAX, +}; + +struct imx_mu_con_priv { + unsigned int idx; + enum imx_mu_chan_type type; + struct mbox_chan *chan; +}; + +enum imx_mu_type { + IMX_MU_V1, + IMX_MU_V2 = BIT(1), + IMX_MU_V2_S4 = BIT(15), + IMX_MU_V2_IRQ = BIT(16), +}; + +struct imx_mu { + void __iomem *base; + const struct imx_mu_dcfg *dcfg; + u32 num_tr; + u32 num_rr; + /* use pointers to channel as a way to reserve channels */ + struct mbox_chan *channels[IMX_MU_CHANS]; + struct imx_mu_con_priv con_priv[IMX_MU_CHANS]; +}; + +struct imx_mu_dcfg { + int (*tx)(struct imx_mu *plat, struct imx_mu_con_priv *cp, const void *data); + int (*rx)(struct imx_mu *plat, struct imx_mu_con_priv *cp); + int (*rxdb)(struct imx_mu *plat, struct imx_mu_con_priv *cp); + int (*init)(struct imx_mu *plat); + int (*of_xlate)(struct mbox_chan *chan, struct ofnode_phandle_args *args); + enum imx_mu_type type; + u32 xTR; /* Transmit Register0 */ + u32 xRR; /* Receive Register0 */ + u32 xSR[IMX_MU_xSR_MAX]; /* Status Registers */ + u32 xCR[IMX_MU_xCR_MAX]; /* Control Registers */ +}; + +#define IMX_MU_xSR_GIPn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x)))) +#define IMX_MU_xSR_RFn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x)))) +#define IMX_MU_xSR_TEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x)))) + +/* General Purpose Interrupt Enable */ +#define IMX_MU_xCR_GIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x)))) +/* Receive Interrupt Enable */ +#define IMX_MU_xCR_RIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x)))) +/* Transmit Interrupt Enable */ +#define IMX_MU_xCR_TIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x)))) +/* General Purpose Interrupt Request */ +#define IMX_MU_xCR_GIRn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(16 + (3 - (x)))) +/* MU reset */ +#define IMX_MU_xCR_RST(type) (type & IMX_MU_V2 ? BIT(0) : BIT(5)) +#define IMX_MU_xSR_RST(type) (type & IMX_MU_V2 ? BIT(0) : BIT(7)) + +static void imx_mu_write(struct imx_mu *plat, u32 val, u32 offs) +{ + iowrite32(val, plat->base + offs); +} + +static u32 imx_mu_read(struct imx_mu *plat, u32 offs) +{ + return ioread32(plat->base + offs); +} + +static u32 imx_mu_xcr_rmw(struct imx_mu *plat, enum imx_mu_xcr type, u32 set, u32 clr) +{ + u32 val; + + val = imx_mu_read(plat, plat->dcfg->xCR[type]); + val &= ~clr; + val |= set; + imx_mu_write(plat, val, plat->dcfg->xCR[type]); + + return val; +} + +/* check that the channel is open or owned by caller */ +static int imx_mu_check_channel(struct mbox_chan *chan) +{ + struct imx_mu *plat = dev_get_plat(chan->dev); + + if (plat->channels[chan->id]) { + /* if reserved check that caller owns */ + if (plat->channels[chan->id] == chan) + return 1; /* caller owns the channel */ + + return -EACCES; + } + + return 0; /* channel empty */ +} + +static int imx_mu_chan_request(struct mbox_chan *chan) +{ + struct imx_mu *plat = dev_get_plat(chan->dev); + struct imx_mu_con_priv *cp; + enum imx_mu_chan_type type; + int idx; + + type = chan->id / 4; + idx = chan->id % 4; + + if (imx_mu_check_channel(chan) < 0) /* check if channel already in use */ + return -EPERM; + + plat->channels[chan->id] = chan; + chan->con_priv = kcalloc(1, sizeof(struct imx_mu_con_priv), 0); + if (!chan->con_priv) + return -ENOMEM; + cp = chan->con_priv; + cp->idx = idx; + cp->type = type; + cp->chan = chan; + + switch (type) { + case IMX_MU_TYPE_RX: + imx_mu_xcr_rmw(plat, IMX_MU_RCR, IMX_MU_xCR_RIEn(plat->dcfg->type, idx), 0); + break; + case IMX_MU_TYPE_TXDB_V2: + case IMX_MU_TYPE_TXDB: + case IMX_MU_TYPE_RXDB: + imx_mu_xcr_rmw(plat, IMX_MU_GIER, IMX_MU_xCR_GIEn(plat->dcfg->type, idx), 0); + break; + default: + break; + } + + return 0; +} + +static int imx_mu_chan_free(struct mbox_chan *chan) +{ + struct imx_mu *plat = dev_get_plat(chan->dev); + struct imx_mu_con_priv *cp = chan->con_priv; + + if (imx_mu_check_channel(chan) <= 0) /* check that the channel is also not empty */ + return -EINVAL; + + /* if you own channel and channel is NOT empty */ + plat->channels[chan->id] = NULL; + switch (cp->type) { + case IMX_MU_TYPE_TX: + imx_mu_xcr_rmw(plat, IMX_MU_TCR, 0, IMX_MU_xCR_TIEn(plat->dcfg->type, cp->idx)); + break; + case IMX_MU_TYPE_RX: + imx_mu_xcr_rmw(plat, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(plat->dcfg->type, cp->idx)); + break; + case IMX_MU_TYPE_TXDB_V2: + case IMX_MU_TYPE_TXDB: + case IMX_MU_TYPE_RXDB: + imx_mu_xcr_rmw(plat, IMX_MU_GIER, 0, IMX_MU_xCR_GIEn(plat->dcfg->type, cp->idx)); + break; + default: + break; + } + + kfree(cp); + + return 0; +} + +static int imx_mu_send(struct mbox_chan *chan, const void *data) +{ + struct imx_mu *plat = dev_get_plat(chan->dev); + struct imx_mu_con_priv *cp = chan->con_priv; + + if (imx_mu_check_channel(chan) < 1) /* return if channel isn't owned */ + return -EPERM; + + return plat->dcfg->tx(plat, cp, data); +} + +static int imx_mu_recv(struct mbox_chan *chan, void *data) +{ + struct imx_mu *plat = dev_get_plat(chan->dev); + struct imx_mu_con_priv *cp = chan->con_priv; + u32 ctrl, val; + + if (imx_mu_check_channel(chan) < 1) /* return if channel isn't owned */ + return -EPERM; + + switch (cp->type) { + case IMX_MU_TYPE_TXDB_V2: + case IMX_MU_TYPE_RXDB: + /* check if GSR[GIRn] bit is set */ + if (readx_poll_timeout(ioread32, plat->base + plat->dcfg->xSR[IMX_MU_GSR], + val, val & BIT(cp->idx), 1000000) < 0) + return -EBUSY; + + ctrl = imx_mu_read(plat, plat->dcfg->xCR[IMX_MU_GIER]); + val = imx_mu_read(plat, plat->dcfg->xSR[IMX_MU_GSR]); + val &= IMX_MU_xSR_GIPn(plat->dcfg->type, cp->idx) & + (ctrl & IMX_MU_xCR_GIEn(plat->dcfg->type, cp->idx)); + break; + default: + dev_warn(chan->dev, "Unhandled channel type %d\n", cp->type); + return -EOPNOTSUPP; + }; + + if (val == IMX_MU_xSR_GIPn(plat->dcfg->type, cp->idx)) + plat->dcfg->rxdb(plat, cp); + + return 0; +} + +static int imx_mu_of_to_plat(struct udevice *dev) +{ + struct imx_mu *plat = dev_get_plat(dev); + fdt_addr_t addr; + + addr = dev_read_addr(dev); + if (addr == FDT_ADDR_T_NONE) + return -ENODEV; + + plat->base = (struct mu_type *)addr; + + return 0; +} + +static int imx_mu_init_generic(struct imx_mu *plat) +{ + unsigned int i; + unsigned int val; + + if (plat->num_rr > 4 || plat->num_tr > 4) { + WARN_ONCE(true, "%s not support TR/RR larger than 4\n", __func__); + return -EOPNOTSUPP; + } + + /* Set default MU configuration */ + for (i = 0; i < IMX_MU_xCR_MAX; i++) + imx_mu_write(plat, 0, plat->dcfg->xCR[i]); + + /* Clear any pending GIP */ + val = imx_mu_read(plat, plat->dcfg->xSR[IMX_MU_GSR]); + imx_mu_write(plat, val, plat->dcfg->xSR[IMX_MU_GSR]); + + /* Clear any pending RSR */ + for (i = 0; i < plat->num_rr; i++) + imx_mu_read(plat, plat->dcfg->xRR + i * 4); + + return 0; +} + +static int imx_mu_generic_of_xlate(struct mbox_chan *chan, struct ofnode_phandle_args *args) +{ + enum imx_mu_chan_type type; + int idx, cid; + + if (args->args_count != 2) { + dev_err(chan->dev, "Invalid argument count %d\n", args->args_count); + return -EINVAL; + } + + type = args->args[0]; /* channel type */ + idx = args->args[1]; /* index */ + + cid = type * 4 + idx; + if (cid >= IMX_MU_CHANS) { + dev_err(chan->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", + cid, type, idx); + return -EINVAL; + } + + chan->id = cid; + + return 0; +} + +static int imx_mu_generic_tx(struct imx_mu *plat, struct imx_mu_con_priv *cp, + const void *data) +{ + switch (cp->type) { + case IMX_MU_TYPE_TXDB_V2: + imx_mu_xcr_rmw(plat, IMX_MU_GCR, IMX_MU_xCR_GIRn(plat->dcfg->type, cp->idx), 0); + break; + default: + dev_warn(cp->chan->dev, "Send data on wrong channel type: %d\n", cp->type); + return -EINVAL; + } + + return 0; +} + +static int imx_mu_generic_rxdb(struct imx_mu *plat, struct imx_mu_con_priv *cp) +{ + imx_mu_write(plat, IMX_MU_xSR_GIPn(plat->dcfg->type, cp->idx), + plat->dcfg->xSR[IMX_MU_GSR]); + + return 0; +} + +static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = { + .tx = imx_mu_generic_tx, + .rxdb = imx_mu_generic_rxdb, + .init = imx_mu_init_generic, + .of_xlate = imx_mu_generic_of_xlate, + .type = IMX_MU_V1, + .xTR = 0x0, + .xRR = 0x10, + .xSR = {0x20, 0x20, 0x20, 0x20}, + .xCR = {0x24, 0x24, 0x24, 0x24, 0x24}, +}; + +static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = { + .tx = imx_mu_generic_tx, + .rxdb = imx_mu_generic_rxdb, + .init = imx_mu_init_generic, + .of_xlate = imx_mu_generic_of_xlate, + .type = IMX_MU_V1, + .xTR = 0x20, + .xRR = 0x40, + .xSR = {0x60, 0x60, 0x60, 0x60}, + .xCR = {0x64, 0x64, 0x64, 0x64, 0x64}, +}; + +static const struct imx_mu_dcfg imx_mu_cfg_imx95 = { + .tx = imx_mu_generic_tx, + .rxdb = imx_mu_generic_rxdb, + .init = imx_mu_init_generic, + .of_xlate = imx_mu_generic_of_xlate, + .type = IMX_MU_V2, + .xTR = 0x200, + .xRR = 0x280, + .xSR = {0xC, 0x118, 0x124, 0x12C}, + .xCR = {0x8, 0x110, 0x114, 0x120, 0x128}, +}; + +static const struct udevice_id ids[] = { + { .compatible = "fsl,imx6sx-mu", .data = (ulong)&imx_mu_cfg_imx6sx }, + { .compatible = "fsl,imx7ulp-mu", .data = (ulong)&imx_mu_cfg_imx7ulp }, + { .compatible = "fsl,imx95-mu", .data = (ulong)&imx_mu_cfg_imx95 }, + { } +}; + +int imx_mu_of_xlate(struct mbox_chan *chan, struct ofnode_phandle_args *args) +{ + struct imx_mu *plat = dev_get_plat(chan->dev); + + return plat->dcfg->of_xlate(chan, args); +} + +struct mbox_ops imx_mu_ops = { + .of_xlate = imx_mu_of_xlate, + .request = imx_mu_chan_request, + .rfree = imx_mu_chan_free, + .send = imx_mu_send, + .recv = imx_mu_recv, +}; + +static void imx_mu_get_tr_rr(struct imx_mu *plat) +{ + u32 val; + + if (plat->dcfg->type & IMX_MU_V2) { + val = imx_mu_read(plat, IMX_MU_V2_PAR_OFF); + plat->num_tr = FIELD_GET(IMX_MU_V2_TR_MASK, val); + plat->num_rr = FIELD_GET(IMX_MU_V2_RR_MASK, val); + } else { + plat->num_tr = 4; + plat->num_rr = 4; + } +} + +static int imx_mu_probe(struct udevice *dev) +{ + struct imx_mu *plat = dev_get_plat(dev); + int ret; + + debug("%s(dev=%p)\n", __func__, dev); + + plat->dcfg = (void *)dev_get_driver_data(dev); + + imx_mu_get_tr_rr(plat); + + ret = plat->dcfg->init(plat); + if (ret) { + dev_err(dev, "Failed to init MU\n"); + return ret; + } + + return 0; +} + +U_BOOT_DRIVER(imx_mu) = { + .name = "imx-mu", + .id = UCLASS_MAILBOX, + .of_match = ids, + .of_to_plat = imx_mu_of_to_plat, + .plat_auto = sizeof(struct imx_mu), + .probe = imx_mu_probe, + .ops = &imx_mu_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/memory/ti-gpmc.c b/drivers/memory/ti-gpmc.c index e979c431e33..29e02f12ae0 100644 --- a/drivers/memory/ti-gpmc.c +++ b/drivers/memory/ti-gpmc.c @@ -1242,4 +1242,5 @@ U_BOOT_DRIVER(ti_gpmc) = { .of_match = gpmc_dt_ids, .probe = gpmc_probe, .flags = DM_FLAG_ALLOC_PRIV_DMA, + .priv_auto = sizeof(struct ti_gpmc), }; diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index ab56bd3939f..6740591a653 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -928,6 +928,12 @@ config ESDHC_DETECT_QUIRK bool "QIXIS-based eSDHC quirk detection" depends on FSL_ESDHC && FSL_QIXIS +config ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE + bool + depends on FSL_ESDHC || FSL_ESDHC_IMX + def_bool y if ARCH_T1024 || ARCH_T1040 || ARCH_T1042 || ARCH_T2080 \ + || FSL_ESDHC_IMX + config FSL_ESDHC_IMX bool "Freescale/NXP i.MX eSDHC controller support" help diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c index d7a45ef0ad0..926113f79d3 100644 --- a/drivers/mmc/fsl_esdhc_imx.c +++ b/drivers/mmc/fsl_esdhc_imx.c @@ -40,12 +40,6 @@ #include <linux/iopoll.h> #include <linux/dma-mapping.h> -#ifndef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE -#ifdef CONFIG_FSL_USDHC -#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 1 -#endif -#endif - DECLARE_GLOBAL_DATA_PTR; #define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \ @@ -376,7 +370,7 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc, (timeout == 4 || timeout == 8 || timeout == 12)) timeout++; - if (IS_ENABLED(ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE)) + if (IS_ENABLED(CONFIG_ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE)) timeout = 0xE; esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16); diff --git a/drivers/mmc/msm_sdhci.c b/drivers/mmc/msm_sdhci.c index 27bb7052fca..ac77fb06bf7 100644 --- a/drivers/mmc/msm_sdhci.c +++ b/drivers/mmc/msm_sdhci.c @@ -10,6 +10,7 @@ #include <clk.h> #include <dm.h> #include <malloc.h> +#include <reset.h> #include <sdhci.h> #include <wait_bit.h> #include <asm/global_data.h> @@ -153,9 +154,18 @@ static int msm_sdc_probe(struct udevice *dev) const struct msm_sdhc_variant_info *var_info; struct sdhci_host *host = &prv->host; u32 core_version, core_minor, core_major; + struct reset_ctl bcr_rst; u32 caps; int ret; + ret = reset_get_by_index(dev, 0, &bcr_rst); + if (!ret) { + reset_assert(&bcr_rst); + udelay(200); + reset_deassert(&bcr_rst); + udelay(200); + } + host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_BROKEN_R1B; host->max_clk = 0; diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index 609bdffbf77..adb271dfb8f 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -190,6 +190,21 @@ config SPL_NAND_LOAD def_bool y depends on NAND_DAVINCI && ARCH_DAVINCI && SPL_NAND_SUPPORT +config NAND_CADENCE + bool "Support Cadence NAND controller as a DT device" + depends on OF_CONTROL && DM_MTD + select SYS_NAND_SELF_INIT + select SPL_SYS_NAND_SELF_INIT + select SPL_NAND_BASE + select SPL_NAND_DRIVERS + select SPL_NAND_IDENT + select SPL_NAND_INIT + select SPL_NAND_ECC + imply CMD_NAND + help + Enable the driver for NAND flash on platforms using a Cadence NAND + controller as a DT device. + config NAND_DENALI bool select SYS_NAND_SELF_INIT @@ -673,7 +688,7 @@ config SYS_NAND_PAGE_SIZE SPL_NAND_SIMPLE || (NAND_MXC && SPL_NAND_SUPPORT) || \ MVEBU_SPL_BOOT_DEVICE_NAND || \ (NAND_ATMEL && SPL_NAND_SUPPORT) || \ - SPL_GENERATE_ATMEL_PMECC_HEADER || NAND_SANDBOX + SPL_GENERATE_ATMEL_PMECC_HEADER || NAND_SANDBOX || NAND_CADENCE depends on !NAND_MXS && !NAND_DENALI_DT && !NAND_LPC32XX_MLC && !NAND_MT7621 help Number of data bytes in one page for the NAND chip on the @@ -775,6 +790,13 @@ config SPL_NAND_AM33XX_BCH so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling SPL-NAND driver with software ECC correction support. +config SPL_NAND_CADENCE + bool "Support Cadence NAND controller for SPL" + depends on SPL_NAND_SUPPORT + help + This is a small implementation of the Cadence NAND controller + for use on SPL. + config SPL_NAND_DENALI bool "Support Denali NAND controller for SPL" depends on SPL_NAND_SUPPORT diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile index b47a3d787ce..34cba77046a 100644 --- a/drivers/mtd/nand/raw/Makefile +++ b/drivers/mtd/nand/raw/Makefile @@ -10,6 +10,7 @@ NORMAL_DRIVERS=y endif obj-$(CONFIG_SPL_NAND_AM33XX_BCH) += am335x_spl_bch.o +obj-$(CONFIG_SPL_NAND_CADENCE) += cadence_spl.o obj-$(CONFIG_SPL_NAND_DENALI) += denali_spl.o obj-$(CONFIG_SPL_NAND_SIMPLE) += nand_spl_simple.o obj-$(CONFIG_SPL_NAND_LOAD) += nand_spl_load.o @@ -51,6 +52,7 @@ obj-$(CONFIG_NAND_ATMEL) += atmel_nand.o obj-$(CONFIG_DM_NAND_ATMEL) += atmel/ obj-$(CONFIG_NAND_ARASAN) += arasan_nfc.o obj-$(CONFIG_NAND_BRCMNAND) += brcmnand/ +obj-$(CONFIG_NAND_CADENCE) += cadence_nand.o obj-$(CONFIG_NAND_DAVINCI) += davinci_nand.o obj-$(CONFIG_NAND_DENALI) += denali.o obj-$(CONFIG_NAND_DENALI_DT) += denali_dt.o diff --git a/drivers/mtd/nand/raw/cadence_nand.c b/drivers/mtd/nand/raw/cadence_nand.c new file mode 100644 index 00000000000..27aa7f97a45 --- /dev/null +++ b/drivers/mtd/nand/raw/cadence_nand.c @@ -0,0 +1,2423 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Cadence NAND flash controller driver + * + * Copyright (C) 2019 Cadence + * + * Author: Piotr Sroka <piotrs@cadence.com> + * + */ + +#include <cadence-nand.h> +#include <clk.h> +#include <dm.h> +#include <hang.h> +#include <malloc.h> +#include <memalign.h> +#include <nand.h> +#include <reset.h> +#include <wait_bit.h> +#include <dm/device_compat.h> +#include <dm/devres.h> +#include <linux/bitfield.h> +#include <linux/bug.h> +#include <linux/delay.h> +#include <linux/dma-direction.h> +#include <linux/dma-mapping.h> +#include <linux/io.h> +#include <linux/iopoll.h> +#include <linux/ioport.h> +#include <linux/printk.h> +#include <linux/sizes.h> + +static inline struct +cdns_nand_chip *to_cdns_nand_chip(struct nand_chip *chip) +{ + return container_of(chip, struct cdns_nand_chip, chip); +} + +static inline struct +cadence_nand_info *to_cadence_nand_info(struct nand_hw_control *controller) +{ + return container_of(controller, struct cadence_nand_info, controller); +} + +static bool +cadence_nand_dma_buf_ok(struct cadence_nand_info *cadence, const void *buf, + u32 buf_len) +{ + u8 data_dma_width = cadence->caps2.data_dma_width; + + return buf && + likely(IS_ALIGNED((uintptr_t)buf, data_dma_width)) && + likely(IS_ALIGNED(buf_len, DMA_DATA_SIZE_ALIGN)); +} + +static int cadence_nand_wait_for_value(struct cadence_nand_info *cadence, + u32 reg_offset, u32 timeout_us, + u32 mask, bool is_clear) +{ + u32 val; + int ret; + + ret = readl_poll_sleep_timeout(cadence->reg + reg_offset, + val, !(val & mask) == is_clear, + 10, timeout_us); + + if (ret < 0) { + dev_err(cadence->dev, + "Timeout while waiting for reg %x with mask %x is clear %d\n", + reg_offset, mask, is_clear); + } + + return ret; +} + +static int cadence_nand_set_ecc_enable(struct cadence_nand_info *cadence, + bool enable) +{ + u32 reg; + + if (cadence_nand_wait_for_value(cadence, CTRL_STATUS, + TIMEOUT_US, + CTRL_STATUS_CTRL_BUSY, true)) + return -ETIMEDOUT; + + reg = readl_relaxed(cadence->reg + ECC_CONFIG_0); + + if (enable) + reg |= ECC_CONFIG_0_ECC_EN; + else + reg &= ~ECC_CONFIG_0_ECC_EN; + + writel_relaxed(reg, cadence->reg + ECC_CONFIG_0); + + return 0; +} + +static void cadence_nand_set_ecc_strength(struct cadence_nand_info *cadence, + u8 corr_str_idx) +{ + u32 reg; + + if (cadence->curr_corr_str_idx == corr_str_idx) + return; + + reg = readl_relaxed(cadence->reg + ECC_CONFIG_0); + reg &= ~ECC_CONFIG_0_CORR_STR; + reg |= FIELD_PREP(ECC_CONFIG_0_CORR_STR, corr_str_idx); + writel_relaxed(reg, cadence->reg + ECC_CONFIG_0); + + cadence->curr_corr_str_idx = corr_str_idx; +} + +static int cadence_nand_get_ecc_strength_idx(struct cadence_nand_info *cadence, + u8 strength) +{ + int i, corr_str_idx = -1; + + for (i = 0; i < BCH_MAX_NUM_CORR_CAPS; i++) { + if (cadence->ecc_strengths[i] == strength) { + corr_str_idx = i; + break; + } + } + + return corr_str_idx; +} + +static int cadence_nand_set_skip_marker_val(struct cadence_nand_info *cadence, + u16 marker_value) +{ + u32 reg; + + if (cadence_nand_wait_for_value(cadence, CTRL_STATUS, + TIMEOUT_US, + CTRL_STATUS_CTRL_BUSY, true)) + return -ETIMEDOUT; + + reg = readl_relaxed(cadence->reg + SKIP_BYTES_CONF); + reg &= ~SKIP_BYTES_MARKER_VALUE; + reg |= FIELD_PREP(SKIP_BYTES_MARKER_VALUE, + marker_value); + + writel_relaxed(reg, cadence->reg + SKIP_BYTES_CONF); + + return 0; +} + +static int cadence_nand_set_skip_bytes_conf(struct cadence_nand_info *cadence, + u8 num_of_bytes, + u32 offset_value, + int enable) +{ + u32 reg, skip_bytes_offset; + + if (cadence_nand_wait_for_value(cadence, CTRL_STATUS, + TIMEOUT_US, + CTRL_STATUS_CTRL_BUSY, true)) + return -ETIMEDOUT; + + if (!enable) { + num_of_bytes = 0; + offset_value = 0; + } + + reg = readl_relaxed(cadence->reg + SKIP_BYTES_CONF); + reg &= ~SKIP_BYTES_NUM_OF_BYTES; + reg |= FIELD_PREP(SKIP_BYTES_NUM_OF_BYTES, + num_of_bytes); + skip_bytes_offset = FIELD_PREP(SKIP_BYTES_OFFSET_VALUE, + offset_value); + + writel_relaxed(reg, cadence->reg + SKIP_BYTES_CONF); + writel_relaxed(skip_bytes_offset, cadence->reg + SKIP_BYTES_OFFSET); + + return 0; +} + +/* Functions enables/disables hardware detection of erased data */ +static void cadence_nand_set_erase_detection(struct cadence_nand_info *cadence, + bool enable, + u8 bitflips_threshold) +{ + u32 reg; + + reg = readl_relaxed(cadence->reg + ECC_CONFIG_0); + + if (enable) + reg |= ECC_CONFIG_0_ERASE_DET_EN; + else + reg &= ~ECC_CONFIG_0_ERASE_DET_EN; + + writel_relaxed(reg, cadence->reg + ECC_CONFIG_0); + writel_relaxed(bitflips_threshold, cadence->reg + ECC_CONFIG_1); +} + +static int cadence_nand_set_access_width16(struct cadence_nand_info *cadence, + bool bit_bus16) +{ + u32 reg; + + if (cadence_nand_wait_for_value(cadence, CTRL_STATUS, + TIMEOUT_US, + CTRL_STATUS_CTRL_BUSY, true)) + return -ETIMEDOUT; + + reg = readl_relaxed(cadence->reg + COMMON_SET); + if (!bit_bus16) + reg &= ~COMMON_SET_DEVICE_16BIT; + else + reg |= COMMON_SET_DEVICE_16BIT; + writel_relaxed(reg, cadence->reg + COMMON_SET); + + return 0; +} + +static void +cadence_nand_clear_interrupt(struct cadence_nand_info *cadence, + struct cadence_nand_irq_status *irq_status) +{ + writel_relaxed(irq_status->status, cadence->reg + INTR_STATUS); + writel_relaxed(irq_status->trd_status, + cadence->reg + TRD_COMP_INT_STATUS); + writel_relaxed(irq_status->trd_error, + cadence->reg + TRD_ERR_INT_STATUS); +} + +static void +cadence_nand_read_int_status(struct cadence_nand_info *cadence, + struct cadence_nand_irq_status *irq_status) +{ + irq_status->status = readl_relaxed(cadence->reg + INTR_STATUS); + irq_status->trd_status = readl_relaxed(cadence->reg + + TRD_COMP_INT_STATUS); + irq_status->trd_error = readl_relaxed(cadence->reg + + TRD_ERR_INT_STATUS); +} + +static u32 irq_detected(struct cadence_nand_info *cadence, + struct cadence_nand_irq_status *irq_status) +{ + cadence_nand_read_int_status(cadence, irq_status); + + return irq_status->status || irq_status->trd_status || + irq_status->trd_error; +} + +static void cadence_nand_reset_irq(struct cadence_nand_info *cadence) +{ + memset(&cadence->irq_status, 0, sizeof(cadence->irq_status)); + memset(&cadence->irq_mask, 0, sizeof(cadence->irq_mask)); +} + +/* + * This is the interrupt service routine. It handles all interrupts + * sent to this device. + */ +static irqreturn_t cadence_nand_isr(struct cadence_nand_info *cadence) +{ + struct cadence_nand_irq_status irq_status; + irqreturn_t result = IRQ_NONE; + + if (irq_detected(cadence, &irq_status)) { + /* Handle interrupt. */ + /* First acknowledge it. */ + cadence_nand_clear_interrupt(cadence, &irq_status); + /* Status in the device context for someone to read. */ + cadence->irq_status.status |= irq_status.status; + cadence->irq_status.trd_status |= irq_status.trd_status; + cadence->irq_status.trd_error |= irq_status.trd_error; + /* Tell the OS that we've handled this. */ + result = IRQ_HANDLED; + } + return result; +} + +static void cadence_nand_set_irq_mask(struct cadence_nand_info *cadence, + struct cadence_nand_irq_status *irq_mask) +{ + writel_relaxed(INTR_ENABLE_INTR_EN | irq_mask->status, + cadence->reg + INTR_ENABLE); + + writel_relaxed(irq_mask->trd_error, + cadence->reg + TRD_ERR_INT_STATUS_EN); +} + +static void +cadence_nand_wait_for_irq(struct cadence_nand_info *cadence, + struct cadence_nand_irq_status *irq_mask, + struct cadence_nand_irq_status *irq_status) +{ + irqreturn_t result = IRQ_NONE; + u32 start = get_timer(0); + + while (get_timer(start) < TIMEOUT_US) { + result = cadence_nand_isr(cadence); + + if (result == IRQ_HANDLED) { + *irq_status = cadence->irq_status; + break; + } + udelay(1); + } + + if (!result) { + /* Timeout error. */ + dev_err(cadence->dev, "timeout occurred:\n"); + dev_err(cadence->dev, "\tstatus = 0x%x, mask = 0x%x\n", + irq_status->status, irq_mask->status); + dev_err(cadence->dev, + "\ttrd_status = 0x%x, trd_status mask = 0x%x\n", + irq_status->trd_status, irq_mask->trd_status); + dev_err(cadence->dev, + "\t trd_error = 0x%x, trd_error mask = 0x%x\n", + irq_status->trd_error, irq_mask->trd_error); + } +} + +/* Execute generic command on NAND controller. */ +static int cadence_nand_generic_cmd_send(struct cadence_nand_info *cadence, + u8 chip_nr, + u64 mini_ctrl_cmd) +{ + u32 mini_ctrl_cmd_l, mini_ctrl_cmd_h, reg; + + mini_ctrl_cmd |= FIELD_PREP(GCMD_LAY_CS, chip_nr); + mini_ctrl_cmd_l = mini_ctrl_cmd & 0xFFFFFFFF; + mini_ctrl_cmd_h = mini_ctrl_cmd >> 32; + + if (cadence_nand_wait_for_value(cadence, CTRL_STATUS, + TIMEOUT_US, + CTRL_STATUS_CTRL_BUSY, true)) + return -ETIMEDOUT; + + cadence_nand_reset_irq(cadence); + + writel_relaxed(mini_ctrl_cmd_l, cadence->reg + CMD_REG2); + writel_relaxed(mini_ctrl_cmd_h, cadence->reg + CMD_REG3); + + /* Select generic command. */ + reg = FIELD_PREP(CMD_REG0_CT, CMD_REG0_CT_GEN); + /* Thread number. */ + reg |= FIELD_PREP(CMD_REG0_TN, 0); + + /* Issue command. */ + writel_relaxed(reg, cadence->reg + CMD_REG0); + cadence->buf_index = 0; + + return 0; +} + +/* Wait for data on slave DMA interface. */ +static int cadence_nand_wait_on_sdma(struct cadence_nand_info *cadence, u8 *out_sdma_trd, + u32 *out_sdma_size) +{ + struct cadence_nand_irq_status irq_mask, irq_status; + + irq_mask.trd_status = 0; + irq_mask.trd_error = 0; + irq_mask.status = INTR_STATUS_SDMA_TRIGG + | INTR_STATUS_SDMA_ERR + | INTR_STATUS_UNSUPP_CMD; + + cadence_nand_set_irq_mask(cadence, &irq_mask); + cadence_nand_wait_for_irq(cadence, &irq_mask, &irq_status); + if (irq_status.status == 0) { + dev_err(cadence->dev, "Timeout while waiting for SDMA\n"); + return -ETIMEDOUT; + } + + if (irq_status.status & INTR_STATUS_SDMA_TRIGG) { + *out_sdma_size = readl_relaxed(cadence->reg + SDMA_SIZE); + *out_sdma_trd = readl_relaxed(cadence->reg + SDMA_TRD_NUM); + *out_sdma_trd = + FIELD_GET(SDMA_TRD_NUM_SDMA_TRD, *out_sdma_trd); + } else { + dev_err(cadence->dev, "SDMA error - irq_status %x\n", + irq_status.status); + return -EIO; + } + + return 0; +} + +static void cadence_nand_get_caps(struct cadence_nand_info *cadence) +{ + u32 reg; + + reg = readl_relaxed(cadence->reg + CTRL_FEATURES); + + cadence->caps2.max_banks = 1 << FIELD_GET(CTRL_FEATURES_N_BANKS, reg); + + if (FIELD_GET(CTRL_FEATURES_DMA_DWITH64, reg)) + cadence->caps2.data_dma_width = 8; + else + cadence->caps2.data_dma_width = 4; + + if (reg & CTRL_FEATURES_CONTROL_DATA) + cadence->caps2.data_control_supp = true; + + if (reg & (CTRL_FEATURES_NVDDR_2_3 + | CTRL_FEATURES_NVDDR)) + cadence->caps2.is_phy_type_dll = true; +} + +/* Prepare CDMA descriptor. */ +static void +cadence_nand_cdma_desc_prepare(struct cadence_nand_info *cadence, + char nf_mem, u32 flash_ptr, dma_addr_t mem_ptr, + dma_addr_t ctrl_data_ptr, u16 ctype) +{ + struct cadence_nand_cdma_desc *cdma_desc = cadence->cdma_desc; + + memset(cdma_desc, 0, sizeof(struct cadence_nand_cdma_desc)); + + /* Set fields for one descriptor. */ + cdma_desc->flash_pointer = flash_ptr; + if (cadence->ctrl_rev >= 13) + cdma_desc->bank = nf_mem; + else + cdma_desc->flash_pointer |= (nf_mem << CDMA_CFPTR_MEM_SHIFT); + + cdma_desc->command_flags |= CDMA_CF_DMA_MASTER; + cdma_desc->command_flags |= CDMA_CF_INT; + + cdma_desc->memory_pointer = mem_ptr; + cdma_desc->status = 0; + cdma_desc->sync_flag_pointer = 0; + cdma_desc->sync_arguments = 0; + + cdma_desc->command_type = ctype; + cdma_desc->ctrl_data_ptr = ctrl_data_ptr; + + flush_cache((dma_addr_t)cadence->cdma_desc, + ROUND(sizeof(struct cadence_nand_cdma_desc), + ARCH_DMA_MINALIGN)); +} + +static u8 cadence_nand_check_desc_error(struct cadence_nand_info *cadence, + u32 desc_status) +{ + if (desc_status & CDMA_CS_ERP) + return STAT_ERASED; + + if (desc_status & CDMA_CS_UNCE) + return STAT_ECC_UNCORR; + + if (desc_status & CDMA_CS_ERR) { + dev_err(cadence->dev, ":CDMA desc error flag detected.\n"); + return STAT_FAIL; + } + + if (FIELD_GET(CDMA_CS_MAXERR, desc_status)) + return STAT_ECC_CORR; + + return STAT_FAIL; +} + +static int cadence_nand_cdma_finish(struct cadence_nand_info *cadence) +{ + struct cadence_nand_cdma_desc *desc_ptr = cadence->cdma_desc; + u8 status = STAT_BUSY; + + invalidate_dcache_range((dma_addr_t)cadence->cdma_desc, + (dma_addr_t)cadence->cdma_desc + + ROUND(sizeof(struct cadence_nand_cdma_desc), + ARCH_DMA_MINALIGN)); + + if (desc_ptr->status & CDMA_CS_FAIL) { + status = cadence_nand_check_desc_error(cadence, + desc_ptr->status); + dev_err(cadence->dev, ":CDMA error %x\n", desc_ptr->status); + } else if (desc_ptr->status & CDMA_CS_COMP) { + /* Descriptor finished with no errors. */ + if (desc_ptr->command_flags & CDMA_CF_CONT) { + dev_info(cadence->dev, "DMA unsupported flag is set"); + status = STAT_UNKNOWN; + } else { + /* Last descriptor. */ + status = STAT_OK; + } + } + + return status; +} + +static int cadence_nand_cdma_send(struct cadence_nand_info *cadence, + u8 thread) +{ + u32 reg; + int status; + + /* Wait for thread ready. */ + status = cadence_nand_wait_for_value(cadence, TRD_STATUS, + TIMEOUT_US, + BIT(thread), true); + if (status) + return status; + + cadence_nand_reset_irq(cadence); + + writel_relaxed((u32)cadence->dma_cdma_desc, + cadence->reg + CMD_REG2); + writel_relaxed(0, cadence->reg + CMD_REG3); + + /* Select CDMA mode. */ + reg = FIELD_PREP(CMD_REG0_CT, CMD_REG0_CT_CDMA); + /* Thread number. */ + reg |= FIELD_PREP(CMD_REG0_TN, thread); + /* Issue command. */ + writel_relaxed(reg, cadence->reg + CMD_REG0); + + return 0; +} + +/* Send SDMA command and wait for finish. */ +static u32 +cadence_nand_cdma_send_and_wait(struct cadence_nand_info *cadence, + u8 thread) +{ + struct cadence_nand_irq_status irq_mask, irq_status = {0}; + int status; + u32 val; + + irq_mask.trd_status = BIT(thread); + irq_mask.trd_error = BIT(thread); + irq_mask.status = INTR_STATUS_CDMA_TERR; + + cadence_nand_set_irq_mask(cadence, &irq_mask); + + status = cadence_nand_cdma_send(cadence, thread); + if (status) + return status; + + /* Make sure the descriptor processing is complete */ + status = readl_poll_timeout(cadence->reg + TRD_COMP_INT_STATUS, val, + (val & BIT(thread)), TIMEOUT_US); + if (status) { + pr_err("cmd thread completion timeout!\n"); + return status; + } + + cadence_nand_wait_for_irq(cadence, &irq_mask, &irq_status); + + if (irq_status.status == 0 && irq_status.trd_status == 0 && + irq_status.trd_error == 0) { + dev_err(cadence->dev, "CDMA command timeout\n"); + return -ETIMEDOUT; + } + if (irq_status.status & irq_mask.status) { + dev_err(cadence->dev, "CDMA command failed\n"); + return -EIO; + } + + return 0; +} + +/* + * ECC size depends on configured ECC strength and on maximum supported + * ECC step size. + */ +static int cadence_nand_calc_ecc_bytes(int max_step_size, int strength) +{ + int nbytes = DIV_ROUND_UP(fls(8 * max_step_size) * strength, 8); + + return ALIGN(nbytes, 2); +} + +#define CADENCE_NAND_CALC_ECC_BYTES(max_step_size) \ + static int \ + cadence_nand_calc_ecc_bytes_##max_step_size(int step_size, \ + int strength)\ + {\ + return cadence_nand_calc_ecc_bytes(max_step_size, strength);\ + } + +CADENCE_NAND_CALC_ECC_BYTES(256) +CADENCE_NAND_CALC_ECC_BYTES(512) +CADENCE_NAND_CALC_ECC_BYTES(1024) +CADENCE_NAND_CALC_ECC_BYTES(2048) +CADENCE_NAND_CALC_ECC_BYTES(4096) + +/* Function reads BCH capabilities. */ +static int cadence_nand_read_bch_caps(struct cadence_nand_info *cadence) +{ + struct nand_ecc_caps *ecc_caps = &cadence->ecc_caps; + int max_step_size = 0, nstrengths, i; + u32 reg; + + reg = readl_relaxed(cadence->reg + BCH_CFG_3); + cadence->bch_metadata_size = FIELD_GET(BCH_CFG_3_METADATA_SIZE, reg); + if (cadence->bch_metadata_size < 4) { + dev_err(cadence->dev, + "Driver needs at least 4 bytes of BCH meta data\n"); + return -EIO; + } + + reg = readl_relaxed(cadence->reg + BCH_CFG_0); + cadence->ecc_strengths[0] = FIELD_GET(BCH_CFG_0_CORR_CAP_0, reg); + cadence->ecc_strengths[1] = FIELD_GET(BCH_CFG_0_CORR_CAP_1, reg); + cadence->ecc_strengths[2] = FIELD_GET(BCH_CFG_0_CORR_CAP_2, reg); + cadence->ecc_strengths[3] = FIELD_GET(BCH_CFG_0_CORR_CAP_3, reg); + + reg = readl_relaxed(cadence->reg + BCH_CFG_1); + cadence->ecc_strengths[4] = FIELD_GET(BCH_CFG_1_CORR_CAP_4, reg); + cadence->ecc_strengths[5] = FIELD_GET(BCH_CFG_1_CORR_CAP_5, reg); + cadence->ecc_strengths[6] = FIELD_GET(BCH_CFG_1_CORR_CAP_6, reg); + cadence->ecc_strengths[7] = FIELD_GET(BCH_CFG_1_CORR_CAP_7, reg); + + reg = readl_relaxed(cadence->reg + BCH_CFG_2); + cadence->ecc_stepinfos[0].stepsize = + FIELD_GET(BCH_CFG_2_SECT_0, reg); + + cadence->ecc_stepinfos[1].stepsize = + FIELD_GET(BCH_CFG_2_SECT_1, reg); + + nstrengths = 0; + for (i = 0; i < BCH_MAX_NUM_CORR_CAPS; i++) { + if (cadence->ecc_strengths[i] != 0) + nstrengths++; + } + + ecc_caps->nstepinfos = 0; + for (i = 0; i < BCH_MAX_NUM_SECTOR_SIZES; i++) { + /* ECC strengths are common for all step infos. */ + cadence->ecc_stepinfos[i].nstrengths = nstrengths; + cadence->ecc_stepinfos[i].strengths = + cadence->ecc_strengths; + + if (cadence->ecc_stepinfos[i].stepsize != 0) + ecc_caps->nstepinfos++; + + if (cadence->ecc_stepinfos[i].stepsize > max_step_size) + max_step_size = cadence->ecc_stepinfos[i].stepsize; + } + ecc_caps->stepinfos = &cadence->ecc_stepinfos[0]; + + switch (max_step_size) { + case 256: + ecc_caps->calc_ecc_bytes = &cadence_nand_calc_ecc_bytes_256; + break; + case 512: + ecc_caps->calc_ecc_bytes = &cadence_nand_calc_ecc_bytes_512; + break; + case 1024: + ecc_caps->calc_ecc_bytes = &cadence_nand_calc_ecc_bytes_1024; + break; + case 2048: + ecc_caps->calc_ecc_bytes = &cadence_nand_calc_ecc_bytes_2048; + break; + case 4096: + ecc_caps->calc_ecc_bytes = &cadence_nand_calc_ecc_bytes_4096; + break; + default: + dev_err(cadence->dev, + "Unsupported sector size(ecc step size) %d\n", + max_step_size); + return -EIO; + } + + return 0; +} + +/* Hardware initialization. */ +static int cadence_nand_hw_init(struct cadence_nand_info *cadence) +{ + int status; + u32 reg; + + status = cadence_nand_wait_for_value(cadence, CTRL_STATUS, + TIMEOUT_US, + CTRL_STATUS_INIT_COMP, false); + if (status) + return status; + + reg = readl_relaxed(cadence->reg + CTRL_VERSION); + cadence->ctrl_rev = FIELD_GET(CTRL_VERSION_REV, reg); + + dev_info(cadence->dev, + "%s: cadence nand controller version reg %x\n", + __func__, reg); + + /* Disable cache and multiplane. */ + writel_relaxed(0, cadence->reg + MULTIPLANE_CFG); + writel_relaxed(0, cadence->reg + CACHE_CFG); + + /* Clear all interrupts. */ + writel_relaxed(0xFFFFFFFF, cadence->reg + INTR_STATUS); + + cadence_nand_get_caps(cadence); + if (cadence_nand_read_bch_caps(cadence)) + return -EIO; + + /* + * Set IO width access to 8. + * It is because during SW device discovering width access + * is expected to be 8. + */ + status = cadence_nand_set_access_width16(cadence, false); + + return status; +} + +#define TT_MAIN_OOB_AREAS 2 +#define TT_RAW_PAGE 3 +#define TT_BBM 4 +#define TT_MAIN_OOB_AREA_EXT 5 + +/* Prepare size of data to transfer. */ +static void +cadence_nand_prepare_data_size(struct mtd_info *mtd, + int transfer_type) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + struct cadence_nand_info *cadence = to_cadence_nand_info(chip->controller); + struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip); + u32 sec_size = 0, offset = 0, sec_cnt = 1; + u32 last_sec_size = cdns_chip->sector_size; + u32 data_ctrl_size = 0; + u32 reg = 0; + + if (cadence->curr_trans_type == transfer_type) + return; + + switch (transfer_type) { + case TT_MAIN_OOB_AREA_EXT: + sec_cnt = cdns_chip->sector_count; + sec_size = cdns_chip->sector_size; + data_ctrl_size = cdns_chip->avail_oob_size; + break; + case TT_MAIN_OOB_AREAS: + sec_cnt = cdns_chip->sector_count; + last_sec_size = cdns_chip->sector_size + + cdns_chip->avail_oob_size; + sec_size = cdns_chip->sector_size; + break; + case TT_RAW_PAGE: + last_sec_size = mtd->writesize + mtd->oobsize; + break; + case TT_BBM: + offset = mtd->writesize + cdns_chip->bbm_offs; + last_sec_size = 8; + break; + } + + reg = 0; + reg |= FIELD_PREP(TRAN_CFG_0_OFFSET, offset); + reg |= FIELD_PREP(TRAN_CFG_0_SEC_CNT, sec_cnt); + writel_relaxed(reg, cadence->reg + TRAN_CFG_0); + + reg = 0; + reg |= FIELD_PREP(TRAN_CFG_1_LAST_SEC_SIZE, last_sec_size); + reg |= FIELD_PREP(TRAN_CFG_1_SECTOR_SIZE, sec_size); + writel_relaxed(reg, cadence->reg + TRAN_CFG_1); + + if (cadence->caps2.data_control_supp) { + reg = readl_relaxed(cadence->reg + CONTROL_DATA_CTRL); + reg &= ~CONTROL_DATA_CTRL_SIZE; + reg |= FIELD_PREP(CONTROL_DATA_CTRL_SIZE, data_ctrl_size); + writel_relaxed(reg, cadence->reg + CONTROL_DATA_CTRL); + } + + cadence->curr_trans_type = transfer_type; +} + +static int +cadence_nand_cdma_transfer(struct cadence_nand_info *cadence, u8 chip_nr, + int page, void *buf, void *ctrl_dat, u32 buf_size, + u32 ctrl_dat_size, enum dma_data_direction dir, + bool with_ecc) +{ + dma_addr_t dma_buf, dma_ctrl_dat = 0; + u8 thread_nr = chip_nr; + int status; + u16 ctype; + + if (dir == DMA_FROM_DEVICE) + ctype = CDMA_CT_RD; + else + ctype = CDMA_CT_WR; + + cadence_nand_set_ecc_enable(cadence, with_ecc); + + dma_buf = dma_map_single(buf, buf_size, dir); + if (dma_mapping_error(cadence->dev, dma_buf)) { + dev_err(cadence->dev, "Failed to map DMA buffer\n"); + return -EIO; + } + + if (ctrl_dat && ctrl_dat_size) { + dma_ctrl_dat = dma_map_single(ctrl_dat, + ctrl_dat_size, dir); + if (dma_mapping_error(cadence->dev, dma_ctrl_dat)) { + dma_unmap_single(dma_buf, + buf_size, dir); + dev_err(cadence->dev, "Failed to map DMA buffer\n"); + return -EIO; + } + } + + cadence_nand_cdma_desc_prepare(cadence, chip_nr, page, + dma_buf, dma_ctrl_dat, ctype); + + status = cadence_nand_cdma_send_and_wait(cadence, thread_nr); + + dma_unmap_single(dma_buf, + buf_size, dir); + + if (ctrl_dat && ctrl_dat_size) + dma_unmap_single(dma_ctrl_dat, + ctrl_dat_size, dir); + if (status) + return status; + + return cadence_nand_cdma_finish(cadence); +} + +static void cadence_nand_set_timings(struct cadence_nand_info *cadence, + struct cadence_nand_timings *t) +{ + writel_relaxed(t->async_toggle_timings, + cadence->reg + ASYNC_TOGGLE_TIMINGS); + writel_relaxed(t->timings0, cadence->reg + TIMINGS0); + writel_relaxed(t->timings1, cadence->reg + TIMINGS1); + writel_relaxed(t->timings2, cadence->reg + TIMINGS2); + + if (cadence->caps2.is_phy_type_dll) + writel_relaxed(t->dll_phy_ctrl, cadence->reg + DLL_PHY_CTRL); + + writel_relaxed(t->phy_ctrl, cadence->reg + PHY_CTRL); + + if (cadence->caps2.is_phy_type_dll) { + writel_relaxed(0, cadence->reg + PHY_TSEL); + writel_relaxed(2, cadence->reg + PHY_DQ_TIMING); + writel_relaxed(t->phy_dqs_timing, + cadence->reg + PHY_DQS_TIMING); + writel_relaxed(t->phy_gate_lpbk_ctrl, + cadence->reg + PHY_GATE_LPBK_CTRL); + writel_relaxed(PHY_DLL_MASTER_CTRL_BYPASS_MODE, + cadence->reg + PHY_DLL_MASTER_CTRL); + writel_relaxed(0, cadence->reg + PHY_DLL_SLAVE_CTRL); + } +} + +static int cadence_nand_select_target(struct nand_chip *chip) +{ + struct cadence_nand_info *cadence = to_cadence_nand_info(chip->controller); + struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip); + + if (chip == cadence->selected_chip) + return 0; + + if (cadence_nand_wait_for_value(cadence, CTRL_STATUS, + TIMEOUT_US, + CTRL_STATUS_CTRL_BUSY, true)) + return -ETIMEDOUT; + + cadence_nand_set_timings(cadence, &cdns_chip->timings); + + cadence_nand_set_ecc_strength(cadence, + cdns_chip->corr_str_idx); + + cadence_nand_set_erase_detection(cadence, true, + chip->ecc.strength); + + cadence->curr_trans_type = -1; + cadence->selected_chip = chip; + + return 0; +} + +static int cadence_nand_erase(struct mtd_info *mtd, int page) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + struct cadence_nand_info *cadence = to_cadence_nand_info(chip->controller); + struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip); + int status; + u8 thread_nr = cdns_chip->cs[chip->cur_cs]; + + cadence_nand_cdma_desc_prepare(cadence, + cdns_chip->cs[chip->cur_cs], + page, 0, 0, + CDMA_CT_ERASE); + status = cadence_nand_cdma_send_and_wait(cadence, thread_nr); + if (status) { + dev_err(cadence->dev, "erase operation failed\n"); + return -EIO; + } + + status = cadence_nand_cdma_finish(cadence); + if (status) + return status; + + return 0; +} + +static int cadence_ecc_setup(struct mtd_info *mtd, struct nand_chip *chip, int oobavail) +{ + struct cadence_nand_info *cadence = to_cadence_nand_info(chip->controller); + int ret; + + /* + * If .size and .strength are already set (usually by DT), + * check if they are supported by this controller. + */ + if (chip->ecc.size && chip->ecc.strength) + return nand_check_ecc_caps(chip, &cadence->ecc_caps, oobavail); + + /* + * We want .size and .strength closest to the chip's requirement + * unless NAND_ECC_MAXIMIZE is requested. + */ + if (!(chip->ecc.options & NAND_ECC_MAXIMIZE)) { + ret = nand_match_ecc_req(chip, &cadence->ecc_caps, oobavail); + if (!ret) + return 0; + } + + /* Max ECC strength is the last thing we can do */ + return nand_maximize_ecc(chip, &cadence->ecc_caps, oobavail); +} + +static int cadence_nand_read_bbm(struct mtd_info *mtd, struct nand_chip *chip, int page, u8 *buf) +{ + int status; + struct cadence_nand_info *cadence = to_cadence_nand_info(chip->controller); + struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip); + + cadence_nand_prepare_data_size(mtd, TT_BBM); + + cadence_nand_set_skip_bytes_conf(cadence, 0, 0, 0); + + /* + * Read only bad block marker from offset + * defined by a memory manufacturer. + */ + status = cadence_nand_cdma_transfer(cadence, + cdns_chip->cs[chip->cur_cs], + page, cadence->buf, NULL, + mtd->oobsize, + 0, DMA_FROM_DEVICE, false); + if (status) { + dev_err(cadence->dev, "read BBM failed\n"); + return -EIO; + } + + memcpy(buf + cdns_chip->bbm_offs, cadence->buf, cdns_chip->bbm_len); + + return 0; +} + +static int cadence_nand_write_page(struct mtd_info *mtd, struct nand_chip *chip, + const u8 *buf, int oob_required, int page) +{ + struct cadence_nand_info *cadence = to_cadence_nand_info(chip->controller); + struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip); + int status; + u16 marker_val = 0xFFFF; + + status = cadence_nand_select_target(chip); + if (status) + return status; + + cadence_nand_set_skip_bytes_conf(cadence, cdns_chip->bbm_len, + mtd->writesize + + cdns_chip->bbm_offs, + 1); + + if (oob_required) { + marker_val = *(u16 *)(chip->oob_poi + + cdns_chip->bbm_offs); + } else { + /* Set oob data to 0xFF. */ + memset(cadence->buf + mtd->writesize, 0xFF, + cdns_chip->avail_oob_size); + } + + cadence_nand_set_skip_marker_val(cadence, marker_val); + + cadence_nand_prepare_data_size(mtd, TT_MAIN_OOB_AREA_EXT); + + if (cadence_nand_dma_buf_ok(cadence, buf, mtd->writesize) && + cadence->caps2.data_control_supp && !(chip->options & NAND_USE_BOUNCE_BUFFER)) { + u8 *oob; + + if (oob_required) + oob = chip->oob_poi; + else + oob = cadence->buf + mtd->writesize; + + status = cadence_nand_cdma_transfer(cadence, + cdns_chip->cs[chip->cur_cs], + page, (void *)buf, oob, + mtd->writesize, + cdns_chip->avail_oob_size, + DMA_TO_DEVICE, true); + if (status) { + dev_err(cadence->dev, "write page failed\n"); + return -EIO; + } + + return 0; + } + + if (oob_required) { + /* Transfer the data to the oob area. */ + memcpy(cadence->buf + mtd->writesize, chip->oob_poi, + cdns_chip->avail_oob_size); + } + + memcpy(cadence->buf, buf, mtd->writesize); + + cadence_nand_prepare_data_size(mtd, TT_MAIN_OOB_AREAS); + + return cadence_nand_cdma_transfer(cadence, + cdns_chip->cs[chip->cur_cs], + page, cadence->buf, NULL, + mtd->writesize + + cdns_chip->avail_oob_size, + 0, DMA_TO_DEVICE, true); +} + +static int cadence_nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip, + int page) +{ + struct cadence_nand_info *cadence = to_cadence_nand_info(chip->controller); + + memset(cadence->buf, 0xFF, mtd->writesize); + + return cadence_nand_write_page(mtd, chip, cadence->buf, 1, page); +} + +static int cadence_nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, + const u8 *buf, int oob_required, int page) +{ + struct cadence_nand_info *cadence = to_cadence_nand_info(chip->controller); + struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip); + int writesize = mtd->writesize; + int oobsize = mtd->oobsize; + int ecc_steps = chip->ecc.steps; + int ecc_size = chip->ecc.size; + int ecc_bytes = chip->ecc.bytes; + void *tmp_buf = cadence->buf; + int oob_skip = cdns_chip->bbm_len; + size_t size = writesize + oobsize; + int i, pos, len; + int status; + + status = cadence_nand_select_target(chip); + if (status) + return status; + + /* + * Fill the buffer with 0xff first except the full page transfer. + * This simplifies the logic. + */ + if (!buf || !oob_required) + memset(tmp_buf, 0xff, size); + + cadence_nand_set_skip_bytes_conf(cadence, 0, 0, 0); + + /* Arrange the buffer for syndrome payload/ecc layout. */ + if (buf) { + for (i = 0; i < ecc_steps; i++) { + pos = i * (ecc_size + ecc_bytes); + len = ecc_size; + + if (pos >= writesize) + pos += oob_skip; + else if (pos + len > writesize) + len = writesize - pos; + + memcpy(tmp_buf + pos, buf, len); + buf += len; + if (len < ecc_size) { + len = ecc_size - len; + memcpy(tmp_buf + writesize + oob_skip, buf, + len); + buf += len; + } + } + } + + if (oob_required) { + const u8 *oob = chip->oob_poi; + u32 oob_data_offset = (cdns_chip->sector_count - 1) * + (cdns_chip->sector_size + chip->ecc.bytes) + + cdns_chip->sector_size + oob_skip; + + /* BBM at the beginning of the OOB area. */ + memcpy(tmp_buf + writesize, oob, oob_skip); + + /* OOB free. */ + memcpy(tmp_buf + oob_data_offset, oob, + cdns_chip->avail_oob_size); + oob += cdns_chip->avail_oob_size; + + /* OOB ECC. */ + for (i = 0; i < ecc_steps; i++) { + pos = ecc_size + i * (ecc_size + ecc_bytes); + if (i == (ecc_steps - 1)) + pos += cdns_chip->avail_oob_size; + + len = ecc_bytes; + + if (pos >= writesize) + pos += oob_skip; + else if (pos + len > writesize) + len = writesize - pos; + + memcpy(tmp_buf + pos, oob, len); + oob += len; + if (len < ecc_bytes) { + len = ecc_bytes - len; + memcpy(tmp_buf + writesize + oob_skip, oob, + len); + oob += len; + } + } + } + + cadence_nand_prepare_data_size(mtd, TT_RAW_PAGE); + + return cadence_nand_cdma_transfer(cadence, + cdns_chip->cs[chip->cur_cs], + page, cadence->buf, NULL, + mtd->writesize + + mtd->oobsize, + 0, DMA_TO_DEVICE, false); +} + +static int cadence_nand_write_oob_raw(struct mtd_info *mtd, struct nand_chip *chip, + int page) +{ + return cadence_nand_write_page_raw(mtd, chip, NULL, true, page); +} + +static int cadence_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip, + u8 *buf, int oob_required, int page) +{ + struct cadence_nand_info *cadence = to_cadence_nand_info(chip->controller); + struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip); + int status; + int ecc_err_count = 0; + + status = cadence_nand_select_target(chip); + if (status) + return status; + + cadence_nand_set_skip_bytes_conf(cadence, cdns_chip->bbm_len, + mtd->writesize + + cdns_chip->bbm_offs, 1); + + /* + * If data buffer can be accessed by DMA and data_control feature + * is supported then transfer data and oob directly. + */ + if (cadence_nand_dma_buf_ok(cadence, buf, mtd->writesize) && + cadence->caps2.data_control_supp && !(chip->options & NAND_USE_BOUNCE_BUFFER)) { + u8 *oob; + + if (oob_required) + oob = chip->oob_poi; + else + oob = cadence->buf + mtd->writesize; + + cadence_nand_prepare_data_size(mtd, TT_MAIN_OOB_AREA_EXT); + status = cadence_nand_cdma_transfer(cadence, + cdns_chip->cs[chip->cur_cs], + page, buf, oob, + mtd->writesize, + cdns_chip->avail_oob_size, + DMA_FROM_DEVICE, true); + /* Otherwise use bounce buffer. */ + } else { + cadence_nand_prepare_data_size(mtd, TT_MAIN_OOB_AREAS); + status = cadence_nand_cdma_transfer(cadence, + cdns_chip->cs[chip->cur_cs], + page, cadence->buf, + NULL, mtd->writesize + + cdns_chip->avail_oob_size, + 0, DMA_FROM_DEVICE, true); + + memcpy(buf, cadence->buf, mtd->writesize); + if (oob_required) + memcpy(chip->oob_poi, + cadence->buf + mtd->writesize, + mtd->oobsize); + } + + switch (status) { + case STAT_ECC_UNCORR: + mtd->ecc_stats.failed++; + ecc_err_count++; + break; + case STAT_ECC_CORR: + ecc_err_count = FIELD_GET(CDMA_CS_MAXERR, + cadence->cdma_desc->status); + mtd->ecc_stats.corrected += ecc_err_count; + break; + case STAT_ERASED: + case STAT_OK: + break; + default: + dev_err(cadence->dev, "read page failed\n"); + return -EIO; + } + + if (oob_required) + if (cadence_nand_read_bbm(mtd, chip, page, chip->oob_poi)) + return -EIO; + + return ecc_err_count; +} + +static int cadence_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip, + int page) +{ + struct cadence_nand_info *cadence = to_cadence_nand_info(chip->controller); + + return cadence_nand_read_page(mtd, chip, cadence->buf, 1, page); +} + +static int cadence_nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, + u8 *buf, int oob_required, int page) +{ + struct cadence_nand_info *cadence = to_cadence_nand_info(chip->controller); + struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip); + int oob_skip = cdns_chip->bbm_len; + int writesize = mtd->writesize; + int ecc_steps = chip->ecc.steps; + int ecc_size = chip->ecc.size; + int ecc_bytes = chip->ecc.bytes; + void *tmp_buf = cadence->buf; + int i, pos, len; + int status; + + status = cadence_nand_select_target(chip); + if (status) + return status; + + cadence_nand_set_skip_bytes_conf(cadence, 0, 0, 0); + + cadence_nand_prepare_data_size(mtd, TT_RAW_PAGE); + status = cadence_nand_cdma_transfer(cadence, + cdns_chip->cs[chip->cur_cs], + page, cadence->buf, NULL, + mtd->writesize + + mtd->oobsize, + 0, DMA_FROM_DEVICE, false); + + switch (status) { + case STAT_ERASED: + case STAT_OK: + break; + default: + dev_err(cadence->dev, "read raw page failed\n"); + return -EIO; + } + + /* Arrange the buffer for syndrome payload/ecc layout. */ + if (buf) { + for (i = 0; i < ecc_steps; i++) { + pos = i * (ecc_size + ecc_bytes); + len = ecc_size; + + if (pos >= writesize) + pos += oob_skip; + else if (pos + len > writesize) + len = writesize - pos; + + memcpy(buf, tmp_buf + pos, len); + buf += len; + if (len < ecc_size) { + len = ecc_size - len; + memcpy(buf, tmp_buf + writesize + oob_skip, + len); + buf += len; + } + } + } + + if (oob_required) { + u8 *oob = chip->oob_poi; + u32 oob_data_offset = (cdns_chip->sector_count - 1) * + (cdns_chip->sector_size + chip->ecc.bytes) + + cdns_chip->sector_size + oob_skip; + + /* OOB free. */ + memcpy(oob, tmp_buf + oob_data_offset, + cdns_chip->avail_oob_size); + + /* BBM at the beginning of the OOB area. */ + memcpy(oob, tmp_buf + writesize, oob_skip); + + oob += cdns_chip->avail_oob_size; + + /* OOB ECC */ + for (i = 0; i < ecc_steps; i++) { + pos = ecc_size + i * (ecc_size + ecc_bytes); + len = ecc_bytes; + + if (i == (ecc_steps - 1)) + pos += cdns_chip->avail_oob_size; + + if (pos >= writesize) + pos += oob_skip; + else if (pos + len > writesize) + len = writesize - pos; + + memcpy(oob, tmp_buf + pos, len); + oob += len; + if (len < ecc_bytes) { + len = ecc_bytes - len; + memcpy(oob, tmp_buf + writesize + oob_skip, + len); + oob += len; + } + } + } + return 0; +} + +static int cadence_nand_read_oob_raw(struct mtd_info *mtd, struct nand_chip *chip, + int page) +{ + return cadence_nand_read_page_raw(mtd, chip, NULL, true, page); +} + +static void cadence_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + struct cadence_nand_info *cadence = to_cadence_nand_info(chip->controller); + u8 thread_nr = 0; + u32 sdma_size; + int status; + int len_in_words = len >> 2; + + /* Wait until slave DMA interface is ready to data transfer. */ + status = cadence_nand_wait_on_sdma(cadence, &thread_nr, &sdma_size); + if (status) { + pr_err("Wait on sdma failed:%x\n", status); + hang(); + } + + if (!cadence->caps1->has_dma) { + readsq(cadence->io.virt, buf, len_in_words); + + if (sdma_size > len) { + memcpy(cadence->buf, buf + (len_in_words << 2), + len - (len_in_words << 2)); + readsl(cadence->io.virt, cadence->buf, + sdma_size / 4 - len_in_words); + } + } +} + +static void cadence_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + struct cadence_nand_info *cadence = to_cadence_nand_info(chip->controller); + u8 thread_nr = 0; + u32 sdma_size; + int status; + int len_in_words = len >> 2; + + /* Wait until slave DMA interface is ready to data transfer. */ + status = cadence_nand_wait_on_sdma(cadence, &thread_nr, &sdma_size); + if (status) { + pr_err("Wait on sdma failed:%x\n", status); + hang(); + } + + if (!cadence->caps1->has_dma) { + writesq(cadence->io.virt, buf, len_in_words); + + if (sdma_size > len) { + memcpy(cadence->buf, buf + (len_in_words << 2), + len - (len_in_words << 2)); + writesl(cadence->io.virt, cadence->buf, + sdma_size / 4 - len_in_words); + } + } +} + +static int cadence_nand_cmd_opcode(struct nand_chip *chip, unsigned int op_id) +{ + struct cadence_nand_info *cadence = to_cadence_nand_info(chip->controller); + struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip); + u64 mini_ctrl_cmd = 0; + int ret; + + mini_ctrl_cmd |= GCMD_LAY_TWB; + mini_ctrl_cmd |= FIELD_PREP(GCMD_LAY_INSTR, GCMD_LAY_INSTR_CMD); + mini_ctrl_cmd |= FIELD_PREP(GCMD_LAY_INPUT_CMD, op_id); + + ret = cadence_nand_generic_cmd_send(cadence, + cdns_chip->cs[chip->cur_cs], + mini_ctrl_cmd); + + if (ret) + dev_err(cadence->dev, "send cmd %x failed\n", + op_id); + + return ret; +} + +static int cadence_nand_cmd_address(struct nand_chip *chip, + unsigned int naddrs, const u8 *addrs) +{ + struct cadence_nand_info *cadence = to_cadence_nand_info(chip->controller); + struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip); + u64 address = 0; + u64 mini_ctrl_cmd = 0; + int ret; + int i; + + mini_ctrl_cmd |= GCMD_LAY_TWB; + + mini_ctrl_cmd |= FIELD_PREP(GCMD_LAY_INSTR, + GCMD_LAY_INSTR_ADDR); + + for (i = 0; i < naddrs; i++) + address |= (u64)addrs[i] << (8 * i); + + mini_ctrl_cmd |= FIELD_PREP(GCMD_LAY_INPUT_ADDR, + address); + mini_ctrl_cmd |= FIELD_PREP(GCMD_LAY_INPUT_ADDR_SIZE, + naddrs - 1); + + ret = cadence_nand_generic_cmd_send(cadence, + cdns_chip->cs[chip->cur_cs], + mini_ctrl_cmd); + + if (ret) + pr_err("send address %llx failed\n", address); + + return ret; +} + +static int cadence_nand_cmd_data(struct nand_chip *chip, + unsigned int len, u8 mode) +{ + struct cadence_nand_info *cadence = to_cadence_nand_info(chip->controller); + struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip); + u64 mini_ctrl_cmd = 0; + int ret; + + mini_ctrl_cmd |= GCMD_LAY_TWB; + mini_ctrl_cmd |= FIELD_PREP(GCMD_LAY_INSTR, + GCMD_LAY_INSTR_DATA); + + if (mode) + mini_ctrl_cmd |= FIELD_PREP(GCMD_DIR, GCMD_DIR_WRITE); + + mini_ctrl_cmd |= FIELD_PREP(GCMD_SECT_CNT, 1); + mini_ctrl_cmd |= FIELD_PREP(GCMD_LAST_SIZE, len); + + ret = cadence_nand_generic_cmd_send(cadence, + cdns_chip->cs[chip->cur_cs], + mini_ctrl_cmd); + + if (ret) { + pr_err("send generic data cmd failed\n"); + return ret; + } + + return ret; +} + +static int cadence_nand_waitfunc(struct mtd_info *mtd, struct nand_chip *chip) +{ + struct cadence_nand_info *cadence = to_cadence_nand_info(chip->controller); + struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip); + int status; + + status = cadence_nand_wait_for_value(cadence, RBN_SETINGS, + TIMEOUT_US, + BIT(cdns_chip->cs[chip->cur_cs]), + false); + return status; +} + +static int cadence_nand_ooblayout_free(struct mtd_info *mtd, int section, + struct mtd_oob_region *oobregion) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip); + + if (section) + return -ERANGE; + + oobregion->offset = cdns_chip->bbm_len; + oobregion->length = cdns_chip->avail_oob_size + - cdns_chip->bbm_len; + + return 0; +} + +static int cadence_nand_ooblayout_ecc(struct mtd_info *mtd, int section, + struct mtd_oob_region *oobregion) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip); + + if (section) + return -ERANGE; + + oobregion->offset = cdns_chip->avail_oob_size; + oobregion->length = chip->ecc.total; + + return 0; +} + +static const struct mtd_ooblayout_ops cadence_nand_ooblayout_ops = { + .rfree = cadence_nand_ooblayout_free, + .ecc = cadence_nand_ooblayout_ecc, +}; + +static int calc_cycl(u32 timing, u32 clock) +{ + if (timing == 0 || clock == 0) + return 0; + + if ((timing % clock) > 0) + return timing / clock; + else + return timing / clock - 1; +} + +/* Calculate max data valid window. */ +static inline u32 calc_tdvw_max(u32 trp_cnt, u32 clk_period, u32 trhoh_min, + u32 board_delay_skew_min, u32 ext_mode) +{ + if (ext_mode == 0) + clk_period /= 2; + + return (trp_cnt + 1) * clk_period + trhoh_min + + board_delay_skew_min; +} + +/* Calculate data valid window. */ +static inline u32 calc_tdvw(u32 trp_cnt, u32 clk_period, u32 trhoh_min, + u32 trea_max, u32 ext_mode) +{ + if (ext_mode == 0) + clk_period /= 2; + + return (trp_cnt + 1) * clk_period + trhoh_min - trea_max; +} + +static inline int of_get_child_count(const ofnode node) +{ + return fdtdec_get_child_count(gd->fdt_blob, ofnode_to_offset(node)); +} + +static int cadence_setup_data_interface(struct mtd_info *mtd, int chipnr, + const struct nand_data_interface *conf) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + struct cadence_nand_info *cadence = to_cadence_nand_info(chip->controller); + struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(mtd_to_nand(mtd)); + const struct nand_sdr_timings *sdr; + struct cadence_nand_timings *t = &cdns_chip->timings; + u32 reg; + u32 board_delay = cadence->board_delay; + u32 clk_period = DIV_ROUND_DOWN_ULL(1000000000000ULL, + cadence->nf_clk_rate); + u32 tceh_cnt, tcs_cnt, tadl_cnt, tccs_cnt; + u32 tfeat_cnt, trhz_cnt, tvdly_cnt; + u32 trhw_cnt, twb_cnt, twh_cnt = 0, twhr_cnt; + u32 twp_cnt = 0, trp_cnt = 0, trh_cnt = 0; + u32 if_skew = cadence->caps1->if_skew; + u32 board_delay_skew_min = board_delay - if_skew; + u32 board_delay_skew_max = board_delay + if_skew; + u32 dqs_sampl_res, phony_dqs_mod; + u32 tdvw, tdvw_min, tdvw_max; + u32 ext_rd_mode, ext_wr_mode; + u32 dll_phy_dqs_timing = 0, phony_dqs_timing = 0, rd_del_sel = 0; + u32 sampling_point; + + sdr = nand_get_sdr_timings(conf); + if (IS_ERR(sdr)) + return PTR_ERR(sdr); + + memset(t, 0, sizeof(*t)); + /* Sampling point calculation. */ + if (cadence->caps2.is_phy_type_dll) + phony_dqs_mod = 2; + else + phony_dqs_mod = 1; + + dqs_sampl_res = clk_period / phony_dqs_mod; + + tdvw_min = sdr->tREA_max + board_delay_skew_max; + /* + * The idea of those calculation is to get the optimum value + * for tRP and tRH timings. If it is NOT possible to sample data + * with optimal tRP/tRH settings, the parameters will be extended. + * If clk_period is 50ns (the lowest value) this condition is met + * for SDR timing modes 1, 2, 3, 4 and 5. + * If clk_period is 20ns the condition is met only for SDR timing + * mode 5. + */ + if (sdr->tRC_min <= clk_period && + sdr->tRP_min <= (clk_period / 2) && + sdr->tREH_min <= (clk_period / 2)) { + /* Performance mode. */ + ext_rd_mode = 0; + tdvw = calc_tdvw(trp_cnt, clk_period, sdr->tRHOH_min, + sdr->tREA_max, ext_rd_mode); + tdvw_max = calc_tdvw_max(trp_cnt, clk_period, sdr->tRHOH_min, + board_delay_skew_min, + ext_rd_mode); + /* + * Check if data valid window and sampling point can be found + * and is not on the edge (ie. we have hold margin). + * If not extend the tRP timings. + */ + if (tdvw > 0) { + if (tdvw_max <= tdvw_min || + (tdvw_max % dqs_sampl_res) == 0) { + /* + * No valid sampling point so the RE pulse need + * to be widen widening by half clock cycle. + */ + ext_rd_mode = 1; + } + } else { + /* + * There is no valid window + * to be able to sample data the tRP need to be widen. + * Very safe calculations are performed here. + */ + trp_cnt = (sdr->tREA_max + board_delay_skew_max + + dqs_sampl_res) / clk_period; + ext_rd_mode = 1; + } + + } else { + /* Extended read mode. */ + u32 trh; + + ext_rd_mode = 1; + trp_cnt = calc_cycl(sdr->tRP_min, clk_period); + trh = sdr->tRC_min - ((trp_cnt + 1) * clk_period); + if (sdr->tREH_min >= trh) + trh_cnt = calc_cycl(sdr->tREH_min, clk_period); + else + trh_cnt = calc_cycl(trh, clk_period); + + tdvw = calc_tdvw(trp_cnt, clk_period, sdr->tRHOH_min, + sdr->tREA_max, ext_rd_mode); + /* + * Check if data valid window and sampling point can be found + * or if it is at the edge check if previous is valid + * - if not extend the tRP timings. + */ + if (tdvw > 0) { + tdvw_max = calc_tdvw_max(trp_cnt, clk_period, + sdr->tRHOH_min, + board_delay_skew_min, + ext_rd_mode); + + if ((((tdvw_max / dqs_sampl_res) + * dqs_sampl_res) <= tdvw_min) || + (((tdvw_max % dqs_sampl_res) == 0) && + (((tdvw_max / dqs_sampl_res - 1) + * dqs_sampl_res) <= tdvw_min))) { + /* + * Data valid window width is lower than + * sampling resolution and do not hit any + * sampling point to be sure the sampling point + * will be found the RE low pulse width will be + * extended by one clock cycle. + */ + trp_cnt = trp_cnt + 1; + } + } else { + /* + * There is no valid window to be able to sample data. + * The tRP need to be widen. + * Very safe calculations are performed here. + */ + trp_cnt = (sdr->tREA_max + board_delay_skew_max + + dqs_sampl_res) / clk_period; + } + } + + tdvw_max = calc_tdvw_max(trp_cnt, clk_period, + sdr->tRHOH_min, + board_delay_skew_min, ext_rd_mode); + + if (sdr->tWC_min <= clk_period && + (sdr->tWP_min + if_skew) <= (clk_period / 2) && + (sdr->tWH_min + if_skew) <= (clk_period / 2)) { + ext_wr_mode = 0; + } else { + u32 twh; + + ext_wr_mode = 1; + twp_cnt = calc_cycl(sdr->tWP_min + if_skew, clk_period); + if ((twp_cnt + 1) * clk_period < (sdr->tALS_min + if_skew)) + twp_cnt = calc_cycl(sdr->tALS_min + if_skew, + clk_period); + + twh = (sdr->tWC_min - (twp_cnt + 1) * clk_period); + if (sdr->tWH_min >= twh) + twh = sdr->tWH_min; + + twh_cnt = calc_cycl(twh + if_skew, clk_period); + } + + reg = FIELD_PREP(ASYNC_TOGGLE_TIMINGS_TRH, trh_cnt); + reg |= FIELD_PREP(ASYNC_TOGGLE_TIMINGS_TRP, trp_cnt); + reg |= FIELD_PREP(ASYNC_TOGGLE_TIMINGS_TWH, twh_cnt); + reg |= FIELD_PREP(ASYNC_TOGGLE_TIMINGS_TWP, twp_cnt); + t->async_toggle_timings = reg; + dev_dbg(cadence->dev, "ASYNC_TOGGLE_TIMINGS_SDR\t%x\n", reg); + + tadl_cnt = calc_cycl((sdr->tADL_min + if_skew), clk_period); + tccs_cnt = calc_cycl((sdr->tCCS_min + if_skew), clk_period); + twhr_cnt = calc_cycl((sdr->tWHR_min + if_skew), clk_period); + trhw_cnt = calc_cycl((sdr->tRHW_min + if_skew), clk_period); + reg = FIELD_PREP(TIMINGS0_TADL, tadl_cnt); + + /* + * If timing exceeds delay field in timing register + * then use maximum value. + */ + if (FIELD_FIT(TIMINGS0_TCCS, tccs_cnt)) + reg |= FIELD_PREP(TIMINGS0_TCCS, tccs_cnt); + else + reg |= TIMINGS0_TCCS; + + reg |= FIELD_PREP(TIMINGS0_TWHR, twhr_cnt); + reg |= FIELD_PREP(TIMINGS0_TRHW, trhw_cnt); + t->timings0 = reg; + dev_dbg(cadence->dev, "TIMINGS0_SDR\t%x\n", reg); + + /* The following is related to single signal so skew is not needed. */ + trhz_cnt = calc_cycl(sdr->tRHZ_max, clk_period); + trhz_cnt = trhz_cnt + 1; + twb_cnt = calc_cycl((sdr->tWB_max + board_delay), clk_period); + /* + * Because of the two stage syncflop the value must be increased by 3 + * first value is related with sync, second value is related + * with output if delay. + */ + twb_cnt = twb_cnt + 3 + 5; + /* + * The following is related to the we edge of the random data input + * sequence so skew is not needed. + */ + tvdly_cnt = calc_cycl(500000 + if_skew, clk_period); + reg = FIELD_PREP(TIMINGS1_TRHZ, trhz_cnt); + reg |= FIELD_PREP(TIMINGS1_TWB, twb_cnt); + reg |= FIELD_PREP(TIMINGS1_TVDLY, tvdly_cnt); + t->timings1 = reg; + dev_dbg(cadence->dev, "TIMINGS1_SDR\t%x\n", reg); + + tfeat_cnt = calc_cycl(sdr->tFEAT_max, clk_period); + if (tfeat_cnt < twb_cnt) + tfeat_cnt = twb_cnt; + + tceh_cnt = calc_cycl(sdr->tCEH_min, clk_period); + tcs_cnt = calc_cycl((sdr->tCS_min + if_skew), clk_period); + + reg = FIELD_PREP(TIMINGS2_TFEAT, tfeat_cnt); + reg |= FIELD_PREP(TIMINGS2_CS_HOLD_TIME, tceh_cnt); + reg |= FIELD_PREP(TIMINGS2_CS_SETUP_TIME, tcs_cnt); + t->timings2 = reg; + dev_dbg(cadence->dev, "TIMINGS2_SDR\t%x\n", reg); + + if (cadence->caps2.is_phy_type_dll) { + reg = DLL_PHY_CTRL_DLL_RST_N; + if (ext_wr_mode) + reg |= DLL_PHY_CTRL_EXTENDED_WR_MODE; + if (ext_rd_mode) + reg |= DLL_PHY_CTRL_EXTENDED_RD_MODE; + + reg |= FIELD_PREP(DLL_PHY_CTRL_RS_HIGH_WAIT_CNT, 7); + reg |= FIELD_PREP(DLL_PHY_CTRL_RS_IDLE_CNT, 7); + t->dll_phy_ctrl = reg; + dev_dbg(cadence->dev, "DLL_PHY_CTRL_SDR\t%x\n", reg); + } + + /* Sampling point calculation. */ + if ((tdvw_max % dqs_sampl_res) > 0) + sampling_point = tdvw_max / dqs_sampl_res; + else + sampling_point = (tdvw_max / dqs_sampl_res - 1); + + if (sampling_point * dqs_sampl_res > tdvw_min) { + dll_phy_dqs_timing = + FIELD_PREP(PHY_DQS_TIMING_DQS_SEL_OE_END, 4); + dll_phy_dqs_timing |= PHY_DQS_TIMING_USE_PHONY_DQS; + phony_dqs_timing = sampling_point / phony_dqs_mod; + + if ((sampling_point % 2) > 0) { + dll_phy_dqs_timing |= PHY_DQS_TIMING_PHONY_DQS_SEL; + if ((tdvw_max % dqs_sampl_res) == 0) + /* + * Calculation for sampling point at the edge + * of data and being odd number. + */ + phony_dqs_timing = (tdvw_max / dqs_sampl_res) + / phony_dqs_mod - 1; + + if (!cadence->caps2.is_phy_type_dll) + phony_dqs_timing--; + + } else { + phony_dqs_timing--; + } + rd_del_sel = phony_dqs_timing + 3; + } else { + dev_warn(cadence->dev, + "ERROR : cannot find valid sampling point\n"); + } + + reg = FIELD_PREP(PHY_CTRL_PHONY_DQS, phony_dqs_timing); + if (cadence->caps2.is_phy_type_dll) + reg |= PHY_CTRL_SDR_DQS; + t->phy_ctrl = reg; + dev_dbg(cadence->dev, "PHY_CTRL_REG_SDR\t%x\n", reg); + + if (cadence->caps2.is_phy_type_dll) { + dev_dbg(cadence->dev, "PHY_TSEL_REG_SDR\t%x\n", 0); + dev_dbg(cadence->dev, "PHY_DQ_TIMING_REG_SDR\t%x\n", 2); + dev_dbg(cadence->dev, "PHY_DQS_TIMING_REG_SDR\t%x\n", + dll_phy_dqs_timing); + t->phy_dqs_timing = dll_phy_dqs_timing; + + reg = FIELD_PREP(PHY_GATE_LPBK_CTRL_RDS, rd_del_sel); + dev_dbg(cadence->dev, "PHY_GATE_LPBK_CTRL_REG_SDR\t%x\n", + reg); + t->phy_gate_lpbk_ctrl = reg; + + dev_dbg(cadence->dev, "PHY_DLL_MASTER_CTRL_REG_SDR\t%lx\n", + PHY_DLL_MASTER_CTRL_BYPASS_MODE); + dev_dbg(cadence->dev, "PHY_DLL_SLAVE_CTRL_REG_SDR\t%x\n", 0); + } + return 0; +} + +static int cadence_nand_attach_chip(struct nand_chip *chip) +{ + struct cadence_nand_info *cadence = to_cadence_nand_info(chip->controller); + struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip); + static struct nand_ecclayout nand_oob; + u32 ecc_size; + struct mtd_info *mtd = nand_to_mtd(chip); + int ret; + + if (chip->options & NAND_BUSWIDTH_16) { + ret = cadence_nand_set_access_width16(cadence, true); + if (ret) + return ret; + } + + chip->options |= NAND_USE_BOUNCE_BUFFER; + chip->bbt_options |= NAND_BBT_USE_FLASH; + chip->bbt_options |= NAND_BBT_NO_OOB; + chip->ecc.mode = NAND_ECC_HW_SYNDROME; + + chip->options |= NAND_NO_SUBPAGE_WRITE; + + cdns_chip->bbm_offs = chip->badblockpos; + cdns_chip->bbm_offs &= ~0x01; + /* this value should be even number */ + cdns_chip->bbm_len = 2; + + ret = cadence_ecc_setup(mtd, chip, mtd->oobsize - cdns_chip->bbm_len); + if (ret) { + dev_err(cadence->dev, "ECC configuration failed\n"); + return ret; + } + + dev_dbg(cadence->dev, + "chosen ECC settings: step=%d, strength=%d, bytes=%d\n", + chip->ecc.size, chip->ecc.strength, chip->ecc.bytes); + + /* Error correction configuration. */ + cdns_chip->sector_size = chip->ecc.size; + cdns_chip->sector_count = mtd->writesize / cdns_chip->sector_size; + ecc_size = cdns_chip->sector_count * chip->ecc.bytes; + + cdns_chip->avail_oob_size = mtd->oobsize - ecc_size; + + if (cdns_chip->avail_oob_size > cadence->bch_metadata_size) + cdns_chip->avail_oob_size = cadence->bch_metadata_size; + + if ((cdns_chip->avail_oob_size + cdns_chip->bbm_len + ecc_size) + > mtd->oobsize) + cdns_chip->avail_oob_size -= 4; + + ret = cadence_nand_get_ecc_strength_idx(cadence, chip->ecc.strength); + if (ret < 0) + return -EINVAL; + + cdns_chip->corr_str_idx = (u8)ret; + + if (cadence_nand_wait_for_value(cadence, CTRL_STATUS, + TIMEOUT_US, + CTRL_STATUS_CTRL_BUSY, true)) + return -ETIMEDOUT; + + cadence_nand_set_ecc_strength(cadence, + cdns_chip->corr_str_idx); + + cadence_nand_set_erase_detection(cadence, true, + chip->ecc.strength); + + dev_dbg(cadence->dev, + "chosen ECC settings: step=%d, strength=%d, bytes=%d\n", + chip->ecc.size, chip->ecc.strength, chip->ecc.bytes); + + /* Override the default read operations. */ + chip->ecc.options |= NAND_ECC_CUSTOM_PAGE_ACCESS; + chip->ecc.read_page = cadence_nand_read_page; + chip->ecc.read_page_raw = cadence_nand_read_page_raw; + chip->ecc.write_page = cadence_nand_write_page; + chip->ecc.write_page_raw = cadence_nand_write_page_raw; + chip->ecc.read_oob = cadence_nand_read_oob; + chip->ecc.write_oob = cadence_nand_write_oob; + chip->ecc.read_oob_raw = cadence_nand_read_oob_raw; + chip->ecc.write_oob_raw = cadence_nand_write_oob_raw; + chip->erase = cadence_nand_erase; + + if ((mtd->writesize + mtd->oobsize) > cadence->buf_size) + cadence->buf_size = mtd->writesize + mtd->oobsize; + + mtd_set_ooblayout(mtd, &cadence_nand_ooblayout_ops); + + nand_oob.eccbytes = cdns_chip->chip.ecc.bytes; + cdns_chip->chip.ecc.layout = &nand_oob; + + return 0; +} + +/* Dummy implementation: we don't support multiple chips */ +static void cadence_nand_select_chip(struct mtd_info *mtd, int chipnr) +{ + switch (chipnr) { + case -1: + case 0: + break; + + default: + WARN_ON(chipnr); + } +} + +static int cadence_nand_status(struct mtd_info *mtd, unsigned int command) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + int ret = 0; + + ret = cadence_nand_cmd_opcode(chip, command); + if (ret) + return ret; + + ret = cadence_nand_cmd_data(chip, 1, GCMD_DIR_READ); + if (ret) + return ret; + + return 0; +} + +static int cadence_nand_readid(struct mtd_info *mtd, int offset_in_page, unsigned int command) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + u8 addrs = (u8)offset_in_page; + int ret = 0; + + ret = cadence_nand_cmd_opcode(chip, command); + if (ret) + return ret; + + ret = cadence_nand_cmd_address(chip, ONE_CYCLE, &addrs); + if (ret) + return ret; + + ret = cadence_nand_cmd_data(chip, 8, GCMD_DIR_READ); + if (ret) + return ret; + + return 0; +} + +static int cadence_nand_param(struct mtd_info *mtd, u8 offset_in_page, unsigned int command) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + int ret = 0; + + ret = cadence_nand_cmd_opcode(chip, command); + if (ret) + return ret; + + ret = cadence_nand_cmd_address(chip, ONE_CYCLE, &offset_in_page); + if (ret) + return ret; + + ret = cadence_nand_waitfunc(mtd, chip); + if (ret) + return ret; + + ret = cadence_nand_cmd_data(chip, sizeof(struct nand_jedec_params), GCMD_DIR_READ); + if (ret) + return ret; + + return 0; +} + +static int cadence_nand_reset(struct mtd_info *mtd, unsigned int command) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + int ret = 0; + + ret = cadence_nand_cmd_opcode(chip, command); + if (ret) + return ret; + + ret = cadence_nand_waitfunc(mtd, chip); + if (ret) + return ret; + + return 0; +} + +static int cadence_nand_features(struct mtd_info *mtd, u8 offset_in_page, u32 command) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + int ret = 0; + + ret = cadence_nand_cmd_opcode(chip, command); + if (ret) + return ret; + + ret = cadence_nand_cmd_address(chip, ONE_CYCLE, &offset_in_page); + if (ret) + return ret; + + if (command == NAND_CMD_GET_FEATURES) + ret = cadence_nand_cmd_data(chip, ONFI_SUBFEATURE_PARAM_LEN, + GCMD_DIR_READ); + else + ret = cadence_nand_cmd_data(chip, ONFI_SUBFEATURE_PARAM_LEN, + GCMD_DIR_WRITE); + + return ret; +} + +static void cadence_nand_cmdfunc(struct mtd_info *mtd, unsigned int command, + int offset_in_page, int page) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + struct cadence_nand_info *cadence = to_cadence_nand_info(chip->controller); + int ret = 0; + + cadence->cmd = command; + switch (command) { + case NAND_CMD_STATUS: + ret = cadence_nand_status(mtd, command); + break; + + case NAND_CMD_READID: + ret = cadence_nand_readid(mtd, offset_in_page, command); + break; + + case NAND_CMD_PARAM: + ret = cadence_nand_param(mtd, offset_in_page, command); + break; + + case NAND_CMD_RESET: + ret = cadence_nand_reset(mtd, command); + break; + + case NAND_CMD_SET_FEATURES: + case NAND_CMD_GET_FEATURES: + ret = cadence_nand_features(mtd, offset_in_page, command); + break; + /* + * ecc will override other command for read, write and erase + */ + default: + break; + } + + if (cadence->cmd == NAND_CMD_RESET) { + ret = cadence_nand_select_target(chip); + if (ret) + dev_err(cadence->dev, "Chip select failure after reset\n"); + } + + if (ret != 0) + printf("ERROR:%s:command:0x%x\n", __func__, cadence->cmd); +} + +static int cadence_nand_dev_ready(struct mtd_info *mtd) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + struct cadence_nand_info *cadence = to_cadence_nand_info(chip->controller); + + if (cadence_nand_wait_for_value(cadence, CTRL_STATUS, + TIMEOUT_US, + CTRL_STATUS_CTRL_BUSY, true)) + return -ETIMEDOUT; + + return 0; +} + +static u8 cadence_nand_read_byte(struct mtd_info *mtd) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + struct cadence_nand_info *cadence = to_cadence_nand_info(chip->controller); + u32 size = 1; + u8 val; + + if (cadence->buf_index == 0) { + if (cadence->cmd == NAND_CMD_READID) + size = 8; + else if (cadence->cmd == NAND_CMD_PARAM) + size = sizeof(struct nand_jedec_params); + else if (cadence->cmd == NAND_CMD_GET_FEATURES) + size = ONFI_SUBFEATURE_PARAM_LEN; + + cadence_nand_read_buf(mtd, &cadence->buf[0], size); + } + + val = *(&cadence->buf[0] + cadence->buf_index); + cadence->buf_index++; + + return val; +} + +static void cadence_nand_write_byte(struct mtd_info *mtd, u8 byte) +{ + cadence_nand_write_buf(mtd, &byte, 1); +} + +static int cadence_nand_chip_init(struct cadence_nand_info *cadence, ofnode node) +{ + struct cdns_nand_chip *cdns_chip; + struct nand_chip *chip; + struct mtd_info *mtd; + int ret, i; + int nsels; + u32 cs; + + if (!ofnode_get_property(node, "reg", &nsels)) + return -ENODEV; + + nsels /= sizeof(u32); + if (nsels <= 0) { + dev_err(cadence->dev, "invalid reg property size %d\n", nsels); + return -EINVAL; + } + + cdns_chip = devm_kzalloc(cadence->dev, sizeof(*cdns_chip) + + (nsels * sizeof(u8)), GFP_KERNEL); + if (!cdns_chip) + return -ENODEV; + + cdns_chip->nsels = nsels; + for (i = 0; i < nsels; i++) { + /* Retrieve CS id. */ + ret = ofnode_read_u32_index(node, "reg", i, &cs); + if (ret) { + dev_err(cadence->dev, + "could not retrieve reg property: %d\n", + ret); + goto free_buf; + } + + if (cs >= cadence->caps2.max_banks) { + dev_err(cadence->dev, + "invalid reg value: %u (max CS = %d)\n", + cs, cadence->caps2.max_banks); + ret = -EINVAL; + goto free_buf; + } + + if (test_and_set_bit(cs, &cadence->assigned_cs)) { + dev_err(cadence->dev, + "CS %d already assigned\n", cs); + ret = -EINVAL; + goto free_buf; + } + + cdns_chip->cs[i] = cs; + } + + chip = &cdns_chip->chip; + chip->controller = &cadence->controller; + nand_set_flash_node(chip, node); + mtd = nand_to_mtd(chip); + mtd->dev->parent = cadence->dev; + + chip->options |= NAND_BUSWIDTH_AUTO; + chip->select_chip = cadence_nand_select_chip; + chip->cmdfunc = cadence_nand_cmdfunc; + chip->dev_ready = cadence_nand_dev_ready; + chip->read_byte = cadence_nand_read_byte; + chip->write_byte = cadence_nand_write_byte; + chip->waitfunc = cadence_nand_waitfunc; + chip->read_buf = cadence_nand_read_buf; + chip->write_buf = cadence_nand_write_buf; + chip->setup_data_interface = cadence_setup_data_interface; + + ret = nand_scan_ident(mtd, 1, NULL); + if (ret) { + dev_err(cadence->dev, "Chip identification failure\n"); + goto free_buf; + } + + ret = cadence_nand_attach_chip(chip); + if (ret) { + dev_err(cadence->dev, "Chip not able to attached\n"); + goto free_buf; + } + + ret = nand_scan_tail(mtd); + if (ret) { + dev_err(cadence->dev, "could not scan the nand chip\n"); + goto free_buf; + } + + ret = nand_register(0, mtd); + if (ret) { + dev_err(cadence->dev, "Failed to register MTD: %d\n", ret); + goto free_buf; + } + + return 0; + +free_buf: + devm_kfree(cadence->dev, cdns_chip); + return ret; +} + +static int cadence_nand_chips_init(struct cadence_nand_info *cadence) +{ + struct udevice *dev = cadence->dev; + ofnode node = dev_ofnode(dev); + ofnode nand_node; + int max_cs = cadence->caps2.max_banks; + int nchips, ret; + + nchips = of_get_child_count(node); + + if (nchips > max_cs) { + dev_err(cadence->dev, + "too many NAND chips: %d (max = %d CS)\n", + nchips, max_cs); + return -EINVAL; + } + + ofnode_for_each_subnode(nand_node, node) { + ret = cadence_nand_chip_init(cadence, nand_node); + if (ret) + return ret; + } + + return 0; +} + +static int cadence_nand_init(struct cadence_nand_info *cadence) +{ + int ret; + + cadence->cdma_desc = dma_alloc_coherent(sizeof(*cadence->cdma_desc), + (unsigned long *)&cadence->dma_cdma_desc); + if (!cadence->cdma_desc) + return -ENOMEM; + + cadence->buf_size = SZ_16K; + cadence->buf = kmalloc(cadence->buf_size, GFP_KERNEL); + if (!cadence->buf) { + ret = -ENOMEM; + goto free_buf_desc; + } + + //Hardware initialization + ret = cadence_nand_hw_init(cadence); + if (ret) + goto free_buf; + + cadence->curr_corr_str_idx = 0xFF; + + ret = cadence_nand_chips_init(cadence); + if (ret) { + dev_err(cadence->dev, "Failed to register MTD: %d\n", + ret); + goto free_buf; + } + + kfree(cadence->buf); + cadence->buf = kzalloc(cadence->buf_size, GFP_KERNEL); + if (!cadence->buf) { + ret = -ENOMEM; + goto free_buf_desc; + } + + return 0; + +free_buf: + kfree(cadence->buf); + +free_buf_desc: + dma_free_coherent(cadence->cdma_desc); + + return ret; +} + +static const struct cadence_nand_dt_devdata cadence_nand_default = { + .if_skew = 0, + .has_dma = 0, +}; + +static const struct udevice_id cadence_nand_dt_ids[] = { + { + .compatible = "cdns,nand", + .data = (unsigned long)&cadence_nand_default + }, {} +}; + +static int cadence_nand_dt_probe(struct udevice *dev) +{ + struct cadence_nand_info *cadence = dev_get_priv(dev); + const struct udevice_id *of_id; + const struct cadence_nand_dt_devdata *devdata; + struct resource res; + int ret; + u32 val; + + if (!dev) { + dev_warn(dev, "Device ptr null\n"); + return -EINVAL; + } + + of_id = &cadence_nand_dt_ids[0]; + devdata = (struct cadence_nand_dt_devdata *)of_id->data; + + cadence->caps1 = devdata; + cadence->dev = dev; + + ret = clk_get_by_index(dev, 0, &cadence->clk); + if (ret) + return ret; + + ret = clk_enable(&cadence->clk); + if (ret && ret != -ENOSYS && ret != -ENOMEM) { + dev_err(dev, "failed to enable clock\n"); + return ret; + } + cadence->nf_clk_rate = clk_get_rate(&cadence->clk); + + ret = reset_get_by_index(dev, 1, &cadence->softphy_reset); + if (ret) { + if (ret != -ENOMEM) + dev_warn(dev, "Can't get softphy_reset: %d\n", ret); + } else { + reset_deassert(&cadence->softphy_reset); + } + + ret = reset_get_by_index(dev, 0, &cadence->nand_reset); + if (ret) { + if (ret != -ENOMEM) + dev_warn(dev, "Can't get nand_reset: %d\n", ret); + } else { + reset_deassert(&cadence->nand_reset); + } + + ret = dev_read_resource_byname(dev, "reg", &res); + if (ret) + return ret; + cadence->reg = devm_ioremap(dev, res.start, resource_size(&res)); + + ret = dev_read_resource_byname(dev, "sdma", &res); + if (ret) + return ret; + cadence->io.dma = res.start; + cadence->io.virt = devm_ioremap(dev, res.start, resource_size(&res)); + + ret = ofnode_read_u32(dev_ofnode(dev->parent), + "cdns,board-delay-ps", &val); + if (ret) { + val = 4830; + dev_info(cadence->dev, + "missing cdns,board-delay-ps property, %d was set\n", + val); + } + cadence->board_delay = val; + + ret = cadence_nand_init(cadence); + if (ret) + return ret; + + return 0; +} + +U_BOOT_DRIVER(cadence_nand_dt) = { + .name = "cadence-nand-dt", + .id = UCLASS_MTD, + .of_match = cadence_nand_dt_ids, + .probe = cadence_nand_dt_probe, + .priv_auto = sizeof(struct cadence_nand_info), +}; + +void board_nand_init(void) +{ + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_MTD, + DM_DRIVER_GET(cadence_nand_dt), + &dev); + if (ret && ret != -ENODEV) + pr_err("Failed to initialize Cadence NAND controller. (error %d)\n", + ret); +} diff --git a/drivers/mtd/nand/raw/cadence_spl.c b/drivers/mtd/nand/raw/cadence_spl.c new file mode 100644 index 00000000000..17058e49faa --- /dev/null +++ b/drivers/mtd/nand/raw/cadence_spl.c @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024 Intel Corporation <www.intel.com> + */ + +#include <cadence-nand.h> +#include <dm.h> +#include <hang.h> +#include <nand.h> +#include <system-constants.h> + +/* Unselect after operation */ +void nand_deselect(void) +{ + struct mtd_info *mtd; + struct nand_chip *chip; + + mtd = get_nand_dev_by_index(nand_curr_device); + if (!mtd) + hang(); + chip = mtd_to_nand(mtd); + + if (chip->select_chip) + chip->select_chip(mtd, -1); +} + +static int nand_is_bad_block(int block) +{ + struct mtd_info *mtd; + struct nand_chip *chip; + loff_t ofs = block * CONFIG_SYS_NAND_BLOCK_SIZE; + + mtd = get_nand_dev_by_index(nand_curr_device); + if (!mtd) + hang(); + chip = mtd_to_nand(mtd); + + return chip->block_bad(mtd, ofs); +} + +static int nand_read_page(int block, int page, uchar *dst) +{ + struct mtd_info *mtd; + int page_addr = block * SYS_NAND_BLOCK_PAGES + page; + loff_t ofs = page_addr * CONFIG_SYS_NAND_PAGE_SIZE; + int ret; + size_t len = CONFIG_SYS_NAND_PAGE_SIZE; + + mtd = get_nand_dev_by_index(nand_curr_device); + if (!mtd) + hang(); + + ret = nand_read(mtd, ofs, &len, dst); + if (ret) + printf("nand_read failed %d\n", ret); + + return ret; +} +#include "nand_spl_loaders.c" diff --git a/drivers/mtd/nand/raw/meson_nand.c b/drivers/mtd/nand/raw/meson_nand.c index 28c851f103b..7e683f49c5e 100644 --- a/drivers/mtd/nand/raw/meson_nand.c +++ b/drivers/mtd/nand/raw/meson_nand.c @@ -618,9 +618,7 @@ static int meson_nfc_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *ch memcpy(meson_chip->data_buf, buf, mtd->writesize); memset(meson_chip->info_buf, 0, chip->ecc.steps * PER_INFO_BYTE); - - if (oob_required) - meson_nfc_set_user_byte(chip, chip->oob_poi); + meson_nfc_set_user_byte(chip, chip->oob_poi); return meson_nfc_write_page_sub(chip, page, false); } diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index 1b65c6f6443..bb5460e0068 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -306,6 +306,35 @@ void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len) ioread16_rep(chip->IO_ADDR_R, p, len >> 1); } +/* + * nand_bbm_get_next_page - Get the next page for bad block markers + * @chip: The NAND chip + * @page: First page to start checking for bad block marker usage + * + * Returns an integer that corresponds to the page offset within a block, for + * a page that is used to store bad block markers. If no more pages are + * available, -EINVAL is returned. + */ +int nand_bbm_get_next_page(struct nand_chip *chip, int page) +{ + struct mtd_info *mtd = nand_to_mtd(chip); + int last_page = ((mtd->erasesize - mtd->writesize) >> + chip->page_shift) & chip->pagemask; + unsigned int bbm_flags = NAND_BBM_FIRSTPAGE | NAND_BBM_SECONDPAGE + | NAND_BBM_LASTPAGE; + + if (page == 0 && !(chip->options & bbm_flags)) + return 0; + if (page == 0 && chip->options & NAND_BBM_FIRSTPAGE) + return 0; + if (page <= 1 && chip->options & NAND_BBM_SECONDPAGE) + return 1; + if (page <= last_page && chip->options & NAND_BBM_LASTPAGE) + return last_page; + + return -EINVAL; +} + /** * nand_block_bad - [DEFAULT] Read bad block marker from the chip * @mtd: MTD device structure @@ -315,40 +344,32 @@ void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len) */ static int nand_block_bad(struct mtd_info *mtd, loff_t ofs) { - int page, res = 0, i = 0; struct nand_chip *chip = mtd_to_nand(mtd); - u16 bad; + int first_page, page_offset; + int res; + u8 bad; - if (chip->bbt_options & NAND_BBT_SCANLASTPAGE) - ofs += mtd->erasesize - mtd->writesize; + first_page = (int)(ofs >> chip->page_shift) & chip->pagemask; + page_offset = nand_bbm_get_next_page(chip, 0); - page = (int)(ofs >> chip->page_shift) & chip->pagemask; + while (page_offset >= 0) { + res = chip->ecc.read_oob(mtd, chip, first_page + page_offset); + if (res < 0) + return res; - do { - if (chip->options & NAND_BUSWIDTH_16) { - chip->cmdfunc(mtd, NAND_CMD_READOOB, - chip->badblockpos & 0xFE, page); - bad = cpu_to_le16(chip->read_word(mtd)); - if (chip->badblockpos & 0x1) - bad >>= 8; - else - bad &= 0xFF; - } else { - chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, - page); - bad = chip->read_byte(mtd); - } + bad = chip->oob_poi[chip->badblockpos]; if (likely(chip->badblockbits == 8)) res = bad != 0xFF; else res = hweight8(bad) < chip->badblockbits; - ofs += mtd->writesize; - page = (int)(ofs >> chip->page_shift) & chip->pagemask; - i++; - } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE)); + if (res) + return res; - return res; + page_offset = nand_bbm_get_next_page(chip, page_offset + 1); + } + + return 0; } /** diff --git a/drivers/net/phy/micrel_ksz90x1.c b/drivers/net/phy/micrel_ksz90x1.c index c48ae6e88f3..ee8eae1efd9 100644 --- a/drivers/net/phy/micrel_ksz90x1.c +++ b/drivers/net/phy/micrel_ksz90x1.c @@ -389,10 +389,126 @@ U_BOOT_PHY_DRIVER(ksz9031) = { #define KSZ9131RN_DLL_ENABLE_DELAY 0 #define KSZ9131RN_DLL_DISABLE_DELAY BIT(12) +#define KSZ9131RN_COMMON_CTRL 0 +#define KSZ9131RN_COMMON_CTRL_INDIVIDUAL_LED_MODE BIT(4) + +#define KSZ9131RN_LED_ERRATA_REG 0x1e +#define KSZ9131RN_LED_ERRATA_BIT BIT(9) + +#define KSZ9131RN_CONTROL_PAD_SKEW 4 +#define KSZ9131RN_RX_DATA_PAD_SKEW 5 +#define KSZ9131RN_TX_DATA_PAD_SKEW 6 +#define KSZ9131RN_CLK_PAD_SKEW 8 + +#define KSZ9131RN_SKEW_5BIT_MAX 2400 +#define KSZ9131RN_SKEW_4BIT_MAX 800 +#define KSZ9131RN_OFFSET 700 +#define KSZ9131RN_STEP 100 + +static int ksz9131_of_load_skew_values(struct phy_device *phydev, + ofnode of_node, + u16 reg, size_t field_sz, + const char *field[], u8 numfields) +{ + int val[4] = {-(1 + KSZ9131RN_OFFSET), -(2 + KSZ9131RN_OFFSET), + -(3 + KSZ9131RN_OFFSET), -(4 + KSZ9131RN_OFFSET)}; + int skewval, skewmax = 0; + int matches = 0; + u16 maxval; + u16 newval; + u16 mask; + int i; + + /* psec properties in dts should mean x pico seconds */ + if (field_sz == 5) + skewmax = KSZ9131RN_SKEW_5BIT_MAX; + else + skewmax = KSZ9131RN_SKEW_4BIT_MAX; + + for (i = 0; i < numfields; i++) + if (!ofnode_read_s32(of_node, field[i], &skewval)) { + if (skewval < -KSZ9131RN_OFFSET) + skewval = -KSZ9131RN_OFFSET; + else if (skewval > skewmax) + skewval = skewmax; + + val[i] = skewval + KSZ9131RN_OFFSET; + matches++; + } + + if (!matches) + return 0; + + if (matches < numfields) + newval = phy_read_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG, reg); + else + newval = 0; + + maxval = (field_sz == 4) ? 0xf : 0x1f; + for (i = 0; i < numfields; i++) + if (val[i] != -(i + 1 + KSZ9131RN_OFFSET)) { + mask = 0xffff; + mask ^= maxval << (field_sz * i); + newval = (newval & mask) | + (((val[i] / KSZ9131RN_STEP) & maxval) + << (field_sz * i)); + } + + return phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG, reg, newval); +} + +static int ksz9131_of_load_all_skew_values(struct phy_device *phydev) +{ + const char *control_skews[2] = { "txen-skew-psec", "rxdv-skew-psec" }; + const char *clk_skews[2] = { "rxc-skew-psec", "txc-skew-psec" }; + const char *rx_data_skews[4] = { + "rxd0-skew-psec", "rxd1-skew-psec", + "rxd2-skew-psec", "rxd3-skew-psec" + }; + const char *tx_data_skews[4] = { + "txd0-skew-psec", "txd1-skew-psec", + "txd2-skew-psec", "txd3-skew-psec" + }; + struct ofnode_phandle_args phandle_args; + int ret; + + /* + * Silently ignore failure here as the device tree is not required to + * contain a phy node. + */ + if (dev_read_phandle_with_args(phydev->dev, "phy-handle", NULL, 0, 0, + &phandle_args)) + return 0; + + if (!ofnode_valid(phandle_args.node)) + return 0; + + ret = ksz9131_of_load_skew_values(phydev, phandle_args.node, + KSZ9131RN_CLK_PAD_SKEW, 5, + clk_skews, 2); + if (ret < 0) + return ret; + + ret = ksz9131_of_load_skew_values(phydev, phandle_args.node, + KSZ9131RN_CONTROL_PAD_SKEW, 4, + control_skews, 2); + if (ret < 0) + return ret; + + ret = ksz9131_of_load_skew_values(phydev, phandle_args.node, + KSZ9131RN_RX_DATA_PAD_SKEW, 4, + rx_data_skews, 4); + if (ret < 0) + return ret; + + return ksz9131_of_load_skew_values(phydev, phandle_args.node, + KSZ9131RN_TX_DATA_PAD_SKEW, 4, + tx_data_skews, 4); +} + static int ksz9131_config_rgmii_delay(struct phy_device *phydev) { - struct phy_driver *drv = phydev->drv; - u16 rxcdll_val, txcdll_val, val; + u16 rxcdll_val, txcdll_val; int ret; switch (phydev->interface) { @@ -416,24 +532,37 @@ static int ksz9131_config_rgmii_delay(struct phy_device *phydev) return 0; } - val = drv->readext(phydev, 0, KSZ9131RN_MMD_COMMON_CTRL_REG, - KSZ9131RN_RXC_DLL_CTRL); - val &= ~KSZ9131RN_DLL_CTRL_BYPASS; - val |= rxcdll_val; - ret = drv->writeext(phydev, 0, KSZ9131RN_MMD_COMMON_CTRL_REG, - KSZ9131RN_RXC_DLL_CTRL, val); - if (ret) + ret = phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG, + KSZ9131RN_RXC_DLL_CTRL, KSZ9131RN_DLL_CTRL_BYPASS, + rxcdll_val); + if (ret < 0) return ret; - val = drv->readext(phydev, 0, KSZ9131RN_MMD_COMMON_CTRL_REG, - KSZ9131RN_TXC_DLL_CTRL); + return phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG, + KSZ9131RN_TXC_DLL_CTRL, KSZ9131RN_DLL_CTRL_BYPASS, + txcdll_val); +} + +/* Silicon Errata DS80000693B + * + * When LEDs are configured in Individual Mode, LED1 is ON in a no-link + * condition. Workaround is to set register 0x1e, bit 9, this way LED1 behaves + * according to the datasheet (off if there is no link). + */ +static int ksz9131_led_errata(struct phy_device *phydev) +{ + int reg; - val &= ~KSZ9131RN_DLL_CTRL_BYPASS; - val |= txcdll_val; - ret = drv->writeext(phydev, 0, KSZ9131RN_MMD_COMMON_CTRL_REG, - KSZ9131RN_TXC_DLL_CTRL, val); + reg = phy_read_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG, + KSZ9131RN_COMMON_CTRL); + if (reg < 0) + return reg; - return ret; + if (!(reg & KSZ9131RN_COMMON_CTRL_INDIVIDUAL_LED_MODE)) + return 0; + + return phy_set_bits(phydev, MDIO_DEVAD_NONE, KSZ9131RN_LED_ERRATA_REG, + KSZ9131RN_LED_ERRATA_BIT); } static int ksz9131_config(struct phy_device *phydev) @@ -446,6 +575,14 @@ static int ksz9131_config(struct phy_device *phydev) return ret; } + ret = ksz9131_of_load_all_skew_values(phydev); + if (ret < 0) + return ret; + + ret = ksz9131_led_errata(phydev); + if (ret < 0) + return ret; + /* add an option to disable the gigabit feature of this PHY */ if (env_get("disable_giga")) { unsigned features; diff --git a/drivers/net/ravb.c b/drivers/net/ravb.c index c39bef17b79..539fd37ee59 100644 --- a/drivers/net/ravb.c +++ b/drivers/net/ravb.c @@ -592,7 +592,7 @@ static int ravb_probe(struct udevice *dev) ret = clk_get_bulk(dev, ð->clks); if (ret < 0) - goto err_mdio_alloc; + goto err_clk_get; mdiodev = mdio_alloc(); if (!mdiodev) { @@ -614,23 +614,25 @@ static int ravb_probe(struct udevice *dev) /* Bring up PHY */ ret = clk_enable_bulk(ð->clks); if (ret) - goto err_mdio_register; + goto err_clk_enable; ret = ravb_reset(dev); if (ret) - goto err_mdio_reset; + goto err_clk_enable; ret = ravb_phy_config(dev); if (ret) - goto err_mdio_reset; + goto err_clk_enable; return 0; -err_mdio_reset: - clk_release_bulk(ð->clks); +err_clk_enable: + mdio_unregister(mdiodev); err_mdio_register: mdio_free(mdiodev); err_mdio_alloc: + clk_release_bulk(ð->clks); +err_clk_get: unmap_physmem(eth->iobase, MAP_NOCACHE); return ret; } diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index e12347e8a03..d3fe90d939e 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -163,8 +163,8 @@ config PHY_RCAR_GEN2 config PHY_RCAR_GEN3 tristate "Renesas R-Car Gen3 USB PHY" - depends on PHY && RCAR_GEN3 && CLK && DM_REGULATOR - default y if RCAR_GEN3 + depends on PHY && CLK && DM_REGULATOR && (RCAR_GEN3 || RZG2L) + default y if (RCAR_GEN3 || RZG2L) help Support for the Renesas R-Car Gen3 USB PHY. This driver operates the PHY connected to EHCI USB module and controls USB OTG operation. @@ -309,5 +309,6 @@ source "drivers/phy/cadence/Kconfig" source "drivers/phy/ti/Kconfig" source "drivers/phy/qcom/Kconfig" source "drivers/phy/renesas/Kconfig" +source "drivers/phy/starfive/Kconfig" endmenu diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index c35f9294dd9..ce4ea28b299 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -44,3 +44,4 @@ obj-y += cadence/ obj-y += ti/ obj-y += qcom/ obj-y += renesas/ +obj-y += starfive/ diff --git a/drivers/phy/phy-rcar-gen3.c b/drivers/phy/phy-rcar-gen3.c index 8c004eaf4c6..d06861c4f79 100644 --- a/drivers/phy/phy-rcar-gen3.c +++ b/drivers/phy/phy-rcar-gen3.c @@ -55,6 +55,7 @@ /* VBCTRL */ #define USB2_VBCTRL_DRVVBUSSEL BIT(8) +#define USB2_VBCTRL_VBOUT BIT(0) /* LINECTRL1 */ #define USB2_LINECTRL1_DPRPD_EN BIT(19) @@ -68,6 +69,13 @@ #define USB2_ADPCTRL_IDPULLUP BIT(5) /* 1 = ID sampling is enabled */ #define USB2_ADPCTRL_DRVVBUS BIT(4) +/* RZ/G2L specific */ +#define USB2_OBINT_IDCHG_EN BIT(0) +#define USB2_LINECTRL1_USB2_IDMON BIT(0) + +/* Device flags */ +#define RCAR_GEN3_PHY_NO_ADPCTRL BIT(0) + struct rcar_gen3_phy { fdt_addr_t regs; struct clk clk; @@ -122,15 +130,50 @@ static int rcar_gen3_phy_phy_power_off(struct phy *phy) return regulator_set_enable(priv->vbus_supply, false); } +static bool rcar_gen3_phy_check_id(struct phy *phy) +{ + const u32 adpdevmask = USB2_ADPCTRL_IDDIG | USB2_ADPCTRL_OTGSESSVLD; + struct rcar_gen3_phy *priv = dev_get_priv(phy->dev); + ulong flags = dev_get_driver_data(phy->dev); + u32 val; + + if (flags & RCAR_GEN3_PHY_NO_ADPCTRL) { + val = readl(priv->regs + USB2_LINECTRL1); + return !!(val & USB2_LINECTRL1_USB2_IDMON); + } + + val = readl(priv->regs + USB2_ADPCTRL); + return (val & adpdevmask) == adpdevmask; +} + +static void rcar_gen3_phy_set_vbus(struct phy *phy, bool enable) +{ + struct rcar_gen3_phy *priv = dev_get_priv(phy->dev); + ulong flags = dev_get_driver_data(phy->dev); + u32 bits = USB2_ADPCTRL_DRVVBUS; + u64 reg = USB2_ADPCTRL; + + if (flags & RCAR_GEN3_PHY_NO_ADPCTRL) { + bits = USB2_VBCTRL_VBOUT; + reg = USB2_VBCTRL; + } + + if (enable) + setbits_le32(priv->regs + reg, bits); + else + clrbits_le32(priv->regs + reg, bits); +} + static int rcar_gen3_phy_phy_set_mode(struct phy *phy, enum phy_mode mode, int submode) { - const u32 adpdevmask = USB2_ADPCTRL_IDDIG | USB2_ADPCTRL_OTGSESSVLD; struct rcar_gen3_phy *priv = dev_get_priv(phy->dev); - u32 adpctrl; + ulong flags = dev_get_driver_data(phy->dev); if (mode == PHY_MODE_USB_OTG) { if (submode) { + u32 obint_enable_bits; + /* OTG submode is used as initialization indicator */ writel(USB2_INT_ENABLE_UCOM_INTEN | USB2_INT_ENABLE_USBH_INTB_EN | @@ -138,13 +181,16 @@ static int rcar_gen3_phy_phy_set_mode(struct phy *phy, enum phy_mode mode, priv->regs + USB2_INT_ENABLE); setbits_le32(priv->regs + USB2_VBCTRL, USB2_VBCTRL_DRVVBUSSEL); - writel(USB2_OBINT_SESSVLDCHG | USB2_OBINT_IDDIGCHG, - priv->regs + USB2_OBINTSTA); - setbits_le32(priv->regs + USB2_OBINTEN, - USB2_OBINT_SESSVLDCHG | - USB2_OBINT_IDDIGCHG); - setbits_le32(priv->regs + USB2_ADPCTRL, - USB2_ADPCTRL_IDPULLUP); + if (flags & RCAR_GEN3_PHY_NO_ADPCTRL) { + obint_enable_bits = USB2_OBINT_IDCHG_EN; + } else { + obint_enable_bits = USB2_OBINT_SESSVLDCHG | + USB2_OBINT_IDDIGCHG; + setbits_le32(priv->regs + USB2_ADPCTRL, + USB2_ADPCTRL_IDPULLUP); + } + writel(obint_enable_bits, priv->regs + USB2_OBINTSTA); + setbits_le32(priv->regs + USB2_OBINTEN, obint_enable_bits); clrsetbits_le32(priv->regs + USB2_LINECTRL1, USB2_LINECTRL1_DP_RPD | USB2_LINECTRL1_DM_RPD | @@ -154,8 +200,7 @@ static int rcar_gen3_phy_phy_set_mode(struct phy *phy, enum phy_mode mode, USB2_LINECTRL1_DMRPD_EN); } - adpctrl = readl(priv->regs + USB2_ADPCTRL); - if ((adpctrl & adpdevmask) == adpdevmask) + if (rcar_gen3_phy_check_id(phy)) mode = PHY_MODE_USB_DEVICE; else mode = PHY_MODE_USB_HOST; @@ -165,13 +210,13 @@ static int rcar_gen3_phy_phy_set_mode(struct phy *phy, enum phy_mode mode, clrbits_le32(priv->regs + USB2_COMMCTRL, USB2_COMMCTRL_OTG_PERI); setbits_le32(priv->regs + USB2_LINECTRL1, USB2_LINECTRL1_DP_RPD | USB2_LINECTRL1_DM_RPD); - setbits_le32(priv->regs + USB2_ADPCTRL, USB2_ADPCTRL_DRVVBUS); + rcar_gen3_phy_set_vbus(phy, true); } else if (mode == PHY_MODE_USB_DEVICE) { setbits_le32(priv->regs + USB2_COMMCTRL, USB2_COMMCTRL_OTG_PERI); clrsetbits_le32(priv->regs + USB2_LINECTRL1, USB2_LINECTRL1_DP_RPD | USB2_LINECTRL1_DM_RPD, USB2_LINECTRL1_DM_RPD); - clrbits_le32(priv->regs + USB2_ADPCTRL, USB2_ADPCTRL_DRVVBUS); + rcar_gen3_phy_set_vbus(phy, false); } else { dev_err(phy->dev, "Unknown mode %d\n", mode); return -EINVAL; @@ -226,7 +271,13 @@ static int rcar_gen3_phy_remove(struct udevice *dev) } static const struct udevice_id rcar_gen3_phy_of_match[] = { - { .compatible = "renesas,rcar-gen3-usb2-phy", }, + { + .compatible = "renesas,rcar-gen3-usb2-phy", + }, + { + .compatible = "renesas,rzg2l-usb2-phy", + .data = RCAR_GEN3_PHY_NO_ADPCTRL, + }, { }, }; diff --git a/drivers/phy/starfive/Kconfig b/drivers/phy/starfive/Kconfig new file mode 100644 index 00000000000..d11338ed484 --- /dev/null +++ b/drivers/phy/starfive/Kconfig @@ -0,0 +1,21 @@ +# +# PHY drivers for Starfive platforms +# + +menu "Starfive PHY driver" + +config PHY_STARFIVE_JH7110_PCIE + bool "Starfive JH7110 PCIe 2.0 PHY driver" + depends on PHY + help + Enable this to support the Starfive JH7110 PCIE 2.0/USB 3.0 PHY. + Generic PHY driver JH7110 USB 3.0/ PCIe 2.0. + +config PHY_STARFIVE_JH7110_USB2 + bool "Starfive JH7110 USB 2.0 PHY driver" + depends on PHY + help + Enable this to support the Starfive JH7110 USB 2.0 PHY. + Generic PHY driver JH7110 USB 2.0. + +endmenu diff --git a/drivers/phy/starfive/Makefile b/drivers/phy/starfive/Makefile new file mode 100644 index 00000000000..82f25aa21b7 --- /dev/null +++ b/drivers/phy/starfive/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2023 Starfive +# + +obj-$(CONFIG_PHY_STARFIVE_JH7110_PCIE) += phy-jh7110-pcie.o +obj-$(CONFIG_PHY_STARFIVE_JH7110_USB2) += phy-jh7110-usb2.o diff --git a/drivers/phy/starfive/phy-jh7110-pcie.c b/drivers/phy/starfive/phy-jh7110-pcie.c new file mode 100644 index 00000000000..a30582821d9 --- /dev/null +++ b/drivers/phy/starfive/phy-jh7110-pcie.c @@ -0,0 +1,239 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * StarFive JH7110 PCIe 2.0 PHY driver + * + * Copyright (C) 2024 StarFive Technology Co., Ltd. + * Author: Minda Chen <minda.chen@starfivetech.com> + */ +#include <asm/io.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <errno.h> +#include <generic-phy.h> +#include <regmap.h> +#include <soc.h> +#include <syscon.h> +#include <linux/bitops.h> +#include <linux/err.h> + +#include "phy-jh7110-usb-syscon.h" + +#define PCIE_KVCO_LEVEL_OFF 0x28 +#define PCIE_USB3_PHY_PLL_CTL_OFF 0x7c +#define PCIE_USB3_PHY_SS_MODE BIT(4) +#define PCIE_KVCO_TUNE_SIGNAL_OFF 0x80 +#define PHY_KVCO_FINE_TUNE_LEVEL 0x91 +#define PHY_KVCO_FINE_TUNE_SIGNALS 0xc + +#define PCIE_USB3_PHY_MODE 0x1 +#define PCIE_BUS_WIDTH 0x2 +#define PCIE_USB3_PHY_ENABLE 0x1 +#define PCIE_USB3_PHY_SPLIT 0x1 + +struct jh7110_pcie_phy { + struct phy *phy; + struct regmap *stg_syscon; + struct regmap *sys_syscon; + void __iomem *regs; + struct regmap_field *phy_mode; + struct regmap_field *bus_width; + struct regmap_field *usb3_phy_en; + struct regmap_field *usb_split; + enum phy_mode mode; +}; + +static int phy_pcie_mode_set(struct jh7110_pcie_phy *data, bool usb_mode) +{ + unsigned int phy_mode, width, usb3_phy, ss_mode, split; + + /* default is PCIe mode */ + if (!data->stg_syscon || !data->sys_syscon) { + if (usb_mode) { + dev_err(data->phy->dev, "doesn't support USB3 mode\n"); + return -EINVAL; + } + return 0; + } + + if (usb_mode) { + phy_mode = PCIE_USB3_PHY_MODE; + width = 0; + usb3_phy = PCIE_USB3_PHY_ENABLE; + ss_mode = PCIE_USB3_PHY_SS_MODE; + split = 0; + } else { + phy_mode = 0; + width = PCIE_BUS_WIDTH; + usb3_phy = 0; + ss_mode = 0; + split = PCIE_USB3_PHY_SPLIT; + } + + regmap_field_write(data->phy_mode, phy_mode); + regmap_field_write(data->bus_width, width); + regmap_field_write(data->usb3_phy_en, usb3_phy); + clrsetbits_le32(data->regs + PCIE_USB3_PHY_PLL_CTL_OFF, + PCIE_USB3_PHY_SS_MODE, ss_mode); + regmap_field_write(data->usb_split, split); + + return 0; +} + +static void phy_kvco_gain_set(struct jh7110_pcie_phy *phy) +{ + /* PCIe Multi-PHY PLL KVCO Gain fine tune settings: */ + writel(PHY_KVCO_FINE_TUNE_LEVEL, phy->regs + PCIE_KVCO_LEVEL_OFF); + writel(PHY_KVCO_FINE_TUNE_SIGNALS, phy->regs + PCIE_KVCO_TUNE_SIGNAL_OFF); +} + +static int jh7110_pcie_phy_set_mode(struct phy *phy, + enum phy_mode mode, int submode) +{ + struct udevice *dev = phy->dev; + struct jh7110_pcie_phy *pcie_phy = dev_get_priv(dev); + int ret; + + if (mode == pcie_phy->mode) + return 0; + + switch (mode) { + case PHY_MODE_USB_HOST: + case PHY_MODE_USB_DEVICE: + case PHY_MODE_USB_OTG: + ret = phy_pcie_mode_set(pcie_phy, 1); + if (ret) + return ret; + break; + case PHY_MODE_PCIE: + phy_pcie_mode_set(pcie_phy, 0); + break; + default: + return -EINVAL; + } + + dev_dbg(phy->dev, "Changing PHY mode to %d\n", mode); + pcie_phy->mode = mode; + + return 0; +} + +static const struct phy_ops jh7110_pcie_phy_ops = { + .set_mode = jh7110_pcie_phy_set_mode, +}; + +static int phy_stg_regfield_init(struct udevice *dev, int mode, int usb3) +{ + struct jh7110_pcie_phy *phy = dev_get_priv(dev); + struct reg_field phy_mode = REG_FIELD(mode, 20, 21); + struct reg_field bus_width = REG_FIELD(usb3, 2, 3); + struct reg_field usb3_phy_en = REG_FIELD(usb3, 4, 4); + + phy->phy_mode = devm_regmap_field_alloc(dev, phy->stg_syscon, phy_mode); + if (IS_ERR(phy->phy_mode)) { + dev_err(dev, "PHY mode reg field init failed\n"); + return PTR_ERR(phy->phy_mode); + } + + phy->bus_width = devm_regmap_field_alloc(dev, phy->stg_syscon, bus_width); + if (IS_ERR(phy->bus_width)) { + dev_err(dev, "PHY bus width reg field init failed\n"); + return PTR_ERR(phy->bus_width); + } + + phy->usb3_phy_en = devm_regmap_field_alloc(dev, phy->stg_syscon, usb3_phy_en); + if (IS_ERR(phy->usb3_phy_en)) { + dev_err(dev, "USB3 PHY enable field init failed\n"); + return PTR_ERR(phy->bus_width); + } + + return 0; +} + +static int phy_sys_regfield_init(struct udevice *dev, int split) +{ + struct jh7110_pcie_phy *phy = dev_get_priv(dev); + struct reg_field usb_split = REG_FIELD(split, USB_PDRSTN_SPLIT_BIT, USB_PDRSTN_SPLIT_BIT); + + phy->usb_split = devm_regmap_field_alloc(dev, phy->sys_syscon, usb_split); + if (IS_ERR(phy->usb_split)) { + dev_err(dev, "USB split field init failed\n"); + return PTR_ERR(phy->usb_split); + } + + return 0; +} + +static int starfive_pcie_phy_get_syscon(struct udevice *dev) +{ + struct jh7110_pcie_phy *phy = dev_get_priv(dev); + struct ofnode_phandle_args sys_phandle, stg_phandle; + int ret; + + /* get corresponding syscon phandle */ + ret = dev_read_phandle_with_args(dev, "starfive,sys-syscon", NULL, 1, 0, + &sys_phandle); + + if (ret < 0) { + dev_err(dev, "Can't get sys cfg phandle: %d\n", ret); + return ret; + } + + ret = dev_read_phandle_with_args(dev, "starfive,stg-syscon", NULL, 2, 0, + &stg_phandle); + + if (ret < 0) { + dev_err(dev, "Can't get stg cfg phandle: %d\n", ret); + return ret; + } + + phy->sys_syscon = syscon_node_to_regmap(sys_phandle.node); + /* get syscon register offset */ + if (!IS_ERR(phy->sys_syscon)) { + ret = phy_sys_regfield_init(dev, SYSCON_USB_PDRSTN_REG_OFFSET); + if (ret) + return ret; + } else { + phy->sys_syscon = NULL; + } + + phy->stg_syscon = syscon_node_to_regmap(stg_phandle.node); + if (!IS_ERR(phy->stg_syscon)) + return phy_stg_regfield_init(dev, stg_phandle.args[0], + stg_phandle.args[1]); + else + phy->stg_syscon = NULL; + + return 0; +} + +int jh7110_pcie_phy_probe(struct udevice *dev) +{ + struct jh7110_pcie_phy *phy = dev_get_priv(dev); + int rc; + + phy->regs = dev_read_addr_ptr(dev); + if (!phy->regs) + return -EINVAL; + + rc = starfive_pcie_phy_get_syscon(dev); + if (rc) + return rc; + + phy_kvco_gain_set(phy); + + return 0; +} + +static const struct udevice_id jh7110_pcie_phy[] = { + { .compatible = "starfive,jh7110-pcie-phy"}, + {}, +}; + +U_BOOT_DRIVER(jh7110_pcie_phy) = { + .name = "jh7110_pcie_phy", + .id = UCLASS_PHY, + .of_match = jh7110_pcie_phy, + .probe = jh7110_pcie_phy_probe, + .ops = &jh7110_pcie_phy_ops, + .priv_auto = sizeof(struct jh7110_pcie_phy), +}; diff --git a/drivers/phy/starfive/phy-jh7110-usb-syscon.h b/drivers/phy/starfive/phy-jh7110-usb-syscon.h new file mode 100644 index 00000000000..0eb66f0d859 --- /dev/null +++ b/drivers/phy/starfive/phy-jh7110-usb-syscon.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef PHY_JH7110_USB_SYSCON_H_ +#define PHY_JH7110_USB_SYSCON_H_ + +#define SYSCON_USB_PDRSTN_REG_OFFSET 0x18 +#define USB_PDRSTN_SPLIT_BIT 17 + +#endif diff --git a/drivers/phy/starfive/phy-jh7110-usb2.c b/drivers/phy/starfive/phy-jh7110-usb2.c new file mode 100644 index 00000000000..1a28381e0df --- /dev/null +++ b/drivers/phy/starfive/phy-jh7110-usb2.c @@ -0,0 +1,162 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * StarFive JH7110 USB 2.0 PHY driver + * + * Copyright (C) 2024 StarFive Technology Co., Ltd. + * Author: Minda Chen <minda.chen@starfivetech.com> + */ + +#include <asm/io.h> +#include <clk.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <errno.h> +#include <generic-phy.h> +#include <regmap.h> +#include <soc.h> +#include <syscon.h> +#include <linux/bitops.h> +#include <linux/err.h> + +#include "phy-jh7110-usb-syscon.h" + +#define USB_LS_KEEPALIVE_OFF 0x4 +#define USB_LS_KEEPALIVE_ENABLE BIT(4) +#define USB_PHY_CLK_RATE 125000000 + +struct jh7110_usb2_phy { + struct phy *phy; + struct regmap *sys_syscon; + void __iomem *regs; + struct clk *usb_125m_clk; + struct clk *app_125m; + struct regmap_field *usb_split; + enum phy_mode mode; +}; + +static void usb2_set_ls_keepalive(struct jh7110_usb2_phy *phy, bool set) +{ + /* Host mode enable the LS speed keep-alive signal */ + clrsetbits_le32(phy->regs + USB_LS_KEEPALIVE_OFF, + USB_LS_KEEPALIVE_ENABLE, + set ? USB_LS_KEEPALIVE_ENABLE : 0); +} + +static int usb2_phy_set_mode(struct phy *phy, + enum phy_mode mode, int submode) +{ + struct udevice *dev = phy->dev; + struct jh7110_usb2_phy *usb2_phy = dev_get_priv(dev); + + if (mode == usb2_phy->mode) + return 0; + + switch (mode) { + case PHY_MODE_USB_HOST: + case PHY_MODE_USB_DEVICE: + case PHY_MODE_USB_OTG: + dev_dbg(dev, "Changing PHY to %d\n", mode); + usb2_phy->mode = mode; + usb2_set_ls_keepalive(usb2_phy, (mode != PHY_MODE_USB_DEVICE)); + break; + default: + return -EINVAL; + } + + /* set default split usb 2.0 only mode */ + regmap_field_write(usb2_phy->usb_split, true); + + return 0; +} + +static int jh7110_usb2_phy_init(struct phy *phy) +{ + struct udevice *dev = phy->dev; + struct jh7110_usb2_phy *usb2_phy = dev_get_priv(dev); + int ret; + + ret = clk_set_rate(usb2_phy->usb_125m_clk, USB_PHY_CLK_RATE); + if (ret < 0) { + dev_err(dev, "Failed to set 125m clock\n"); + return ret; + } + + return clk_prepare_enable(usb2_phy->app_125m); +} + +static int jh7110_usb2_phy_exit(struct phy *phy) +{ + struct udevice *dev = phy->dev; + struct jh7110_usb2_phy *usb2_phy = dev_get_priv(dev); + + clk_disable_unprepare(usb2_phy->app_125m); + + return 0; +} + +struct phy_ops jh7110_usb2_phy_ops = { + .init = jh7110_usb2_phy_init, + .exit = jh7110_usb2_phy_exit, + .set_mode = usb2_phy_set_mode, +}; + +int jh7110_usb2_phy_probe(struct udevice *dev) +{ + struct jh7110_usb2_phy *phy = dev_get_priv(dev); + ofnode node; + struct reg_field usb_split; + int ret; + + phy->regs = dev_read_addr_ptr(dev); + if (!phy->regs) + return -EINVAL; + + node = ofnode_by_compatible(ofnode_null(), "starfive,jh7110-sys-syscon"); + if (!ofnode_valid(node)) { + dev_err(dev, "Can't get syscon dev node\n"); + return -ENODEV; + } + + phy->sys_syscon = syscon_node_to_regmap(node); + if (IS_ERR(phy->sys_syscon)) { + dev_err(dev, "Can't get syscon regmap: %d\n", ret); + return PTR_ERR(phy->sys_syscon); + } + + usb_split.reg = SYSCON_USB_PDRSTN_REG_OFFSET; + usb_split.lsb = USB_PDRSTN_SPLIT_BIT; + usb_split.msb = USB_PDRSTN_SPLIT_BIT; + phy->usb_split = devm_regmap_field_alloc(dev, phy->sys_syscon, usb_split); + if (IS_ERR(phy->usb_split)) { + dev_err(dev, "USB split field init failed\n"); + return PTR_ERR(phy->usb_split); + } + + phy->usb_125m_clk = devm_clk_get(dev, "125m"); + if (IS_ERR(phy->usb_125m_clk)) { + dev_err(dev, "Failed to get 125m clock\n"); + return PTR_ERR(phy->usb_125m_clk); + } + + phy->app_125m = devm_clk_get(dev, "app_125m"); + if (IS_ERR(phy->app_125m)) { + dev_err(dev, "Failed to get app 125m clock\n"); + return PTR_ERR(phy->app_125m); + } + + return 0; +} + +static const struct udevice_id jh7110_usb2_phy[] = { + { .compatible = "starfive,jh7110-usb-phy"}, + {}, +}; + +U_BOOT_DRIVER(jh7110_usb2_phy) = { + .name = "jh7110_usb2_phy", + .id = UCLASS_PHY, + .of_match = jh7110_usb2_phy, + .probe = jh7110_usb2_phy_probe, + .ops = &jh7110_usb2_phy_ops, + .priv_auto = sizeof(struct jh7110_usb2_phy), +}; diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index d3eb6998551..f4a3942ee2f 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -7,84 +7,98 @@ config PINCTRL_QCOM menu "Qualcomm pinctrl drivers" config PINCTRL_QCOM_APQ8016 - bool "Qualcomm APQ8016 GCC" + bool "Qualcomm APQ8016 Pinctrl" select PINCTRL_QCOM help Say Y here to enable support for pinctrl on the MSM8916 / APQ8016 Snapdragon 410 SoC, as well as the associated GPIO driver. config PINCTRL_QCOM_APQ8096 - bool "Qualcomm APQ8096 GCC" + bool "Qualcomm APQ8096 Pinctrl" select PINCTRL_QCOM help Say Y here to enable support for pinctrl on the MSM8996 / APQ8096 Snapdragon 820 SoC, as well as the associated GPIO driver. config PINCTRL_QCOM_IPQ4019 - bool "Qualcomm IPQ4019 GCC" + bool "Qualcomm IPQ4019 Pinctrl" select PINCTRL_QCOM help Say Y here to enable support for pinctrl on the IPQ4019 SoC, as well as the associated GPIO driver. +config PINCTRL_QCOM_IPQ9574 + bool "Qualcomm IPQ9574 Pinctrl" + select PINCTRL_QCOM + help + Say Y here to enable support for pinctrl on the IPQ9574 SoC, + as well as the associated GPIO driver. + config PINCTRL_QCOM_QCM2290 - bool "Qualcomm QCM2290 GCC" + bool "Qualcomm QCM2290 Pinctrl" select PINCTRL_QCOM help Say Y here to enable support for pinctrl on the Snapdragon QCM2290 SoC, as well as the associated GPIO driver. config PINCTRL_QCOM_QCS404 - bool "Qualcomm QCS404 GCC" + bool "Qualcomm QCS404 Pinctrl" select PINCTRL_QCOM help Say Y here to enable support for pinctrl on the Snapdragon QCS404 SoC, as well as the associated GPIO driver. +config PINCTRL_QCOM_SC7280 + bool "Qualcomm SC7280/QCM6490 Pinctrl" + select PINCTRL_QCOM + help + Say Y here to enable support for pinctrl on the Snapdragon SC7280 SoC, + as well as the associated GPIO driver. + config PINCTRL_QCOM_SDM845 - bool "Qualcomm SDM845 GCC" + bool "Qualcomm SDM845 Pinctrl" select PINCTRL_QCOM help Say Y here to enable support for pinctrl on the Snapdragon 845 SoC, as well as the associated GPIO driver. config PINCTRL_QCOM_SM6115 - bool "Qualcomm SM6115 GCC" + bool "Qualcomm SM6115 Pinctrl" select PINCTRL_QCOM help Say Y here to enable support for pinctrl on the Snapdragon SM6115 SoC, as well as the associated GPIO driver. config PINCTRL_QCOM_SM8150 - bool "Qualcomm SM8150 GCC" + bool "Qualcomm SM8150 Pinctrl" select PINCTRL_QCOM help Say Y here to enable support for pinctrl on the Snapdragon SM8150 SoC, as well as the associated GPIO driver. config PINCTRL_QCOM_SM8250 - bool "Qualcomm SM8250 GCC" + bool "Qualcomm SM8250 Pinctrl" select PINCTRL_QCOM help Say Y here to enable support for pinctrl on the Snapdragon SM8250 SoC, as well as the associated GPIO driver. config PINCTRL_QCOM_SM8550 - bool "Qualcomm SM8550 GCC" + bool "Qualcomm SM8550 Pinctrl" select PINCTRL_QCOM help Say Y here to enable support for pinctrl on the Snapdragon SM8550 SoC, as well as the associated GPIO driver. config PINCTRL_QCOM_SM8650 - bool "Qualcomm SM8650 GCC" + bool "Qualcomm SM8650 Pinctrl" select PINCTRL_QCOM help Say Y here to enable support for pinctrl on the Snapdragon SM8650 SoC, as well as the associated GPIO driver. config PINCTRL_QCOM_X1E80100 - bool "Qualcomm X1E80100 GCC" + bool "Qualcomm X1E80100 Pinctrl" select PINCTRL_QCOM help Say Y here to enable support for pinctrl on the Snapdragon X1E80100 SoC, diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 06d3c95f93a..94cdc6e4a62 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -5,9 +5,11 @@ obj-$(CONFIG_PINCTRL_QCOM) += pinctrl-qcom.o obj-$(CONFIG_PINCTRL_QCOM_APQ8016) += pinctrl-apq8016.o obj-$(CONFIG_PINCTRL_QCOM_IPQ4019) += pinctrl-ipq4019.o +obj-$(CONFIG_PINCTRL_QCOM_IPQ9574) += pinctrl-ipq9574.o obj-$(CONFIG_PINCTRL_QCOM_APQ8096) += pinctrl-apq8096.o obj-$(CONFIG_PINCTRL_QCOM_QCM2290) += pinctrl-qcm2290.o obj-$(CONFIG_PINCTRL_QCOM_QCS404) += pinctrl-qcs404.o +obj-$(CONFIG_PINCTRL_QCOM_SC7280) += pinctrl-sc7280.o obj-$(CONFIG_PINCTRL_QCOM_SDM845) += pinctrl-sdm845.o obj-$(CONFIG_PINCTRL_QCOM_SM6115) += pinctrl-sm6115.o obj-$(CONFIG_PINCTRL_QCOM_SM8150) += pinctrl-sm8150.o diff --git a/drivers/pinctrl/qcom/pinctrl-apq8016.c b/drivers/pinctrl/qcom/pinctrl-apq8016.c index 0c7437822ff..9ae07d43d93 100644 --- a/drivers/pinctrl/qcom/pinctrl-apq8016.c +++ b/drivers/pinctrl/qcom/pinctrl-apq8016.c @@ -50,8 +50,8 @@ static const char *apq8016_get_pin_name(struct udevice *dev, } } -static unsigned int apq8016_get_function_mux(__maybe_unused unsigned int pin, - unsigned int selector) +static int apq8016_get_function_mux(__maybe_unused unsigned int pin, + unsigned int selector) { return msm_pinctrl_functions[selector].val; } diff --git a/drivers/pinctrl/qcom/pinctrl-apq8096.c b/drivers/pinctrl/qcom/pinctrl-apq8096.c index 132ece868bf..eaa927c6e22 100644 --- a/drivers/pinctrl/qcom/pinctrl-apq8096.c +++ b/drivers/pinctrl/qcom/pinctrl-apq8096.c @@ -43,8 +43,8 @@ static const char *apq8096_get_pin_name(struct udevice *dev, } } -static unsigned int apq8096_get_function_mux(__maybe_unused unsigned int pin, - unsigned int selector) +static int apq8096_get_function_mux(__maybe_unused unsigned int pin, + unsigned int selector) { return msm_pinctrl_functions[selector].val; } diff --git a/drivers/pinctrl/qcom/pinctrl-ipq4019.c b/drivers/pinctrl/qcom/pinctrl-ipq4019.c index 3215c677b26..dafcd494df4 100644 --- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c +++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c @@ -311,8 +311,7 @@ static const char *ipq4019_get_pin_name(struct udevice *dev, return pin_name; } -static unsigned int ipq4019_get_function_mux(unsigned int pin, - unsigned int selector) +static int ipq4019_get_function_mux(unsigned int pin, unsigned int selector) { unsigned int i; const msm_pin_function *func = ipq4019_pin_functions + pin; diff --git a/drivers/pinctrl/qcom/pinctrl-ipq9574.c b/drivers/pinctrl/qcom/pinctrl-ipq9574.c new file mode 100644 index 00000000000..ce09072ae3c --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-ipq9574.c @@ -0,0 +1,226 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * pinctrl driver for Qualcomm ipq9574 + * + * (C) Copyright 2025 Linaro Ltd. + */ + +#include <dm.h> + +#include "pinctrl-qcom.h" + +#define MAX_PIN_NAME_LEN 32 +static char pin_name[MAX_PIN_NAME_LEN] __section(".data"); + +enum ipq9574_functions { + msm_mux_blsp0_spi, + msm_mux_blsp0_uart, + msm_mux_blsp1_i2c, + msm_mux_blsp1_spi, + msm_mux_blsp1_uart, + msm_mux_blsp2_i2c, + msm_mux_blsp2_spi, + msm_mux_blsp2_uart, + msm_mux_blsp3_i2c, + msm_mux_blsp3_spi, + msm_mux_blsp3_uart, + msm_mux_blsp4_i2c, + msm_mux_blsp4_spi, + msm_mux_blsp4_uart, + msm_mux_blsp5_i2c, + msm_mux_blsp5_uart, + msm_mux_gpio, + msm_mux_mdc, + msm_mux_mdio, + msm_mux_pcie0_clk, + msm_mux_pcie0_wake, + msm_mux_pcie1_clk, + msm_mux_pcie1_wake, + msm_mux_pcie2_clk, + msm_mux_pcie2_wake, + msm_mux_pcie3_clk, + msm_mux_pcie3_wake, + msm_mux_qspi_data, + msm_mux_qspi_clk, + msm_mux_qspi_cs, + msm_mux_sdc_data, + msm_mux_sdc_clk, + msm_mux_sdc_cmd, + msm_mux_sdc_rclk, + msm_mux_NA, +}; + +#define MSM_PIN_FUNCTION(fname) \ + [msm_mux_##fname] = {#fname, msm_mux_##fname} + +static const struct pinctrl_function msm_pinctrl_functions[] = { + MSM_PIN_FUNCTION(blsp0_spi), + MSM_PIN_FUNCTION(blsp0_uart), + MSM_PIN_FUNCTION(blsp1_i2c), + MSM_PIN_FUNCTION(blsp1_spi), + MSM_PIN_FUNCTION(blsp1_uart), + MSM_PIN_FUNCTION(blsp2_i2c), + MSM_PIN_FUNCTION(blsp2_spi), + MSM_PIN_FUNCTION(blsp2_uart), + MSM_PIN_FUNCTION(blsp3_i2c), + MSM_PIN_FUNCTION(blsp3_spi), + MSM_PIN_FUNCTION(blsp3_uart), + MSM_PIN_FUNCTION(blsp4_i2c), + MSM_PIN_FUNCTION(blsp4_spi), + MSM_PIN_FUNCTION(blsp4_uart), + MSM_PIN_FUNCTION(blsp5_i2c), + MSM_PIN_FUNCTION(blsp5_uart), + MSM_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(mdc), + MSM_PIN_FUNCTION(mdio), + MSM_PIN_FUNCTION(pcie0_clk), + MSM_PIN_FUNCTION(pcie0_wake), + MSM_PIN_FUNCTION(pcie1_clk), + MSM_PIN_FUNCTION(pcie1_wake), + MSM_PIN_FUNCTION(pcie2_clk), + MSM_PIN_FUNCTION(pcie2_wake), + MSM_PIN_FUNCTION(pcie3_clk), + MSM_PIN_FUNCTION(pcie3_wake), + MSM_PIN_FUNCTION(qspi_data), + MSM_PIN_FUNCTION(qspi_clk), + MSM_PIN_FUNCTION(qspi_cs), + MSM_PIN_FUNCTION(sdc_data), + MSM_PIN_FUNCTION(sdc_clk), + MSM_PIN_FUNCTION(sdc_cmd), + MSM_PIN_FUNCTION(sdc_rclk), +}; + +typedef unsigned int msm_pin_function[10]; + +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + [id] = { msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9, \ + } + +static const msm_pin_function ipq9574_pin_functions[] = { + PINGROUP(0, sdc_data, qspi_data, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(1, sdc_data, qspi_data, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(2, sdc_data, qspi_data, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(3, sdc_data, qspi_data, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(4, sdc_cmd, qspi_cs, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(5, sdc_clk, qspi_clk, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(6, sdc_data, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(7, sdc_data, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(8, sdc_data, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(9, sdc_data, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(10, sdc_rclk, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(11, blsp0_spi, blsp0_uart, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(12, blsp0_spi, blsp0_uart, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(13, blsp0_spi, blsp0_uart, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(14, blsp0_spi, blsp0_uart, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(15, blsp3_spi, blsp3_i2c, blsp3_uart, NA, NA, NA, NA, NA, NA), + PINGROUP(16, blsp3_spi, blsp3_i2c, blsp3_uart, NA, NA, NA, NA, NA, NA), + PINGROUP(17, blsp3_spi, blsp3_uart, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(18, blsp3_spi, blsp3_uart, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(19, blsp3_spi, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(20, blsp3_spi, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(21, blsp3_spi, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(22, pcie0_clk, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(23, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(24, pcie0_wake, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(25, pcie1_clk, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(26, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(27, pcie1_wake, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(28, pcie2_clk, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(29, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(30, pcie2_wake, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(31, pcie3_clk, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(32, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(33, pcie3_wake, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(34, blsp2_uart, blsp2_i2c, blsp2_spi, blsp1_uart, NA, NA, NA, NA, NA), + PINGROUP(35, blsp2_uart, blsp2_i2c, blsp2_spi, blsp1_uart, NA, NA, NA, NA, NA), + PINGROUP(36, blsp1_uart, blsp1_i2c, blsp2_spi, NA, NA, NA, NA, NA, NA), + PINGROUP(37, blsp1_uart, blsp1_i2c, blsp2_spi, NA, NA, NA, NA, NA, NA), + PINGROUP(38, mdc, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(39, mdio, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(40, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(41, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(42, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(43, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(44, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(45, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(46, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(47, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(48, blsp5_i2c, blsp5_uart, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(49, blsp5_i2c, blsp5_uart, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(50, blsp4_uart, blsp4_i2c, blsp4_spi, NA, NA, NA, NA, NA, NA), + PINGROUP(51, blsp4_uart, blsp4_i2c, blsp4_spi, NA, NA, NA, NA, NA, NA), + PINGROUP(52, blsp4_uart, blsp4_spi, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(53, blsp4_uart, blsp4_spi, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(54, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(55, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(56, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(57, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(58, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(59, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(60, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(61, blsp1_spi, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(62, blsp1_spi, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(63, blsp1_spi, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(64, blsp1_spi, NA, NA, NA, NA, NA, NA, NA, NA), +}; + +static const char *ipq9574_get_function_name(struct udevice *dev, + unsigned int selector) +{ + return msm_pinctrl_functions[selector].name; +} + +static const char *ipq9574_get_pin_name(struct udevice *dev, + unsigned int selector) +{ + snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector); + return pin_name; +} + +static int ipq9574_get_function_mux(unsigned int pin, unsigned int selector) +{ + unsigned int i; + const msm_pin_function *func = ipq9574_pin_functions + pin; + + for (i = 0; i < 10; i++) + if ((*func)[i] == selector) + return i; + + debug("Can't find requested function for pin:selector %u:%u\n", + pin, selector); + + return -EINVAL; +} + +static const struct msm_pinctrl_data ipq9574_data = { + .pin_data = { + .pin_count = 65, + }, + .functions_count = ARRAY_SIZE(msm_pinctrl_functions), + .get_function_name = ipq9574_get_function_name, + .get_function_mux = ipq9574_get_function_mux, + .get_pin_name = ipq9574_get_pin_name, +}; + +static const struct udevice_id msm_pinctrl_ids[] = { + { .compatible = "qcom,ipq9574-tlmm", .data = (ulong)&ipq9574_data }, + { /* Sentinal */ } +}; + +U_BOOT_DRIVER(pinctrl_ipq9574) = { + .name = "pinctrl_ipq9574", + .id = UCLASS_NOP, + .of_match = msm_pinctrl_ids, + .ops = &msm_pinctrl_ops, + .bind = msm_pinctrl_bind, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/pinctrl/qcom/pinctrl-qcm2290.c b/drivers/pinctrl/qcom/pinctrl-qcm2290.c index af969e177d7..0c2222ce663 100644 --- a/drivers/pinctrl/qcom/pinctrl-qcm2290.c +++ b/drivers/pinctrl/qcom/pinctrl-qcm2290.c @@ -38,7 +38,7 @@ static const char *qcm2290_get_pin_name(struct udevice *dev, unsigned int select return pin_name; } -static unsigned int qcm2290_get_function_mux(__maybe_unused unsigned int pin, unsigned int selector) +static int qcm2290_get_function_mux(__maybe_unused unsigned int pin, unsigned int selector) { return msm_pinctrl_functions[selector].val; } diff --git a/drivers/pinctrl/qcom/pinctrl-qcom.c b/drivers/pinctrl/qcom/pinctrl-qcom.c index 26a3fba194a..24d031947a3 100644 --- a/drivers/pinctrl/qcom/pinctrl-qcom.c +++ b/drivers/pinctrl/qcom/pinctrl-qcom.c @@ -92,7 +92,10 @@ static int msm_pinmux_set(struct udevice *dev, unsigned int pin_selector, unsigned int func_selector) { struct msm_pinctrl_priv *priv = dev_get_priv(dev); - u32 func = priv->data->get_function_mux(pin_selector, func_selector); + int func = priv->data->get_function_mux(pin_selector, func_selector); + + if (func < 0) + return func; /* Always NOP for special pins, assume they're in the correct state */ if (qcom_is_special_pin(&priv->data->pin_data, pin_selector)) diff --git a/drivers/pinctrl/qcom/pinctrl-qcom.h b/drivers/pinctrl/qcom/pinctrl-qcom.h index 49b7bfbc001..cd167e63868 100644 --- a/drivers/pinctrl/qcom/pinctrl-qcom.h +++ b/drivers/pinctrl/qcom/pinctrl-qcom.h @@ -18,8 +18,7 @@ struct msm_pinctrl_data { int functions_count; const char *(*get_function_name)(struct udevice *dev, unsigned int selector); - unsigned int (*get_function_mux)(unsigned int pin, - unsigned int selector); + int (*get_function_mux)(unsigned int pin, unsigned int selector); const char *(*get_pin_name)(struct udevice *dev, unsigned int selector); }; diff --git a/drivers/pinctrl/qcom/pinctrl-qcs404.c b/drivers/pinctrl/qcom/pinctrl-qcs404.c index fb6defaeddf..c272595aa2a 100644 --- a/drivers/pinctrl/qcom/pinctrl-qcs404.c +++ b/drivers/pinctrl/qcom/pinctrl-qcs404.c @@ -93,8 +93,8 @@ static const char *qcs404_get_pin_name(struct udevice *dev, } } -static unsigned int qcs404_get_function_mux(__maybe_unused unsigned int pin, - unsigned int selector) +static int qcs404_get_function_mux(__maybe_unused unsigned int pin, + unsigned int selector) { return msm_pinctrl_functions[selector].val; } diff --git a/drivers/pinctrl/qcom/pinctrl-sc7280.c b/drivers/pinctrl/qcom/pinctrl-sc7280.c new file mode 100644 index 00000000000..fe87947fbbf --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sc7280.c @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Qualcomm sc7280 pinctrl + * + * (C) Copyright 2024 Linaro Ltd. + * + */ + +#include <dm.h> + +#include "pinctrl-qcom.h" + +#define WEST 0x00000000 +#define SOUTH 0x00400000 +#define NORTH 0x00800000 + +#define MAX_PIN_NAME_LEN 32 +static char pin_name[MAX_PIN_NAME_LEN] __section(".data"); + +static const struct pinctrl_function msm_pinctrl_functions[] = { + { "qup05", 1 }, + { "gpio", 0 }, + { "pcie1_clkreqn", 3}, +}; +#define SDC_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .name = pg_name, \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + } + +#define UFS_RESET(pg_name, offset) \ + { \ + .name = pg_name, \ + .ctl_reg = offset, \ + .io_reg = offset + 0x4, \ + .pull_bit = 3, \ + .drv_bit = 0, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = 0, \ + } + +static const struct msm_special_pin_data sc7280_special_pins_data[] = { + [0] = UFS_RESET("ufs_reset", SOUTH + 0xbe000), + [1] = SDC_PINGROUP("sdc1_rclk", 0xb3004, 0, 6), + [2] = SDC_PINGROUP("sdc1_clk", 0xb3000, 13, 6), + [3] = SDC_PINGROUP("sdc1_cmd", 0xb3000, 11, 3), + [4] = SDC_PINGROUP("sdc1_data", 0xb3000, 9, 0), + [5] = SDC_PINGROUP("sdc2_clk", 0xb4000, 14, 6), + [6] = SDC_PINGROUP("sdc2_cmd", 0xb4000, 11, 3), + [7] = SDC_PINGROUP("sdc2_data", 0xb4000, 9, 0), +}; + +static const char *sc7280_get_function_name(struct udevice *dev, unsigned int selector) +{ + return msm_pinctrl_functions[selector].name; +} + +static const char *sc7280_get_pin_name(struct udevice *dev, unsigned int selector) +{ + if (selector >= 175 && selector <= 182) + snprintf(pin_name, MAX_PIN_NAME_LEN, + sc7280_special_pins_data[selector - 175].name); + else + snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector); + + return pin_name; +} + +static int sc7280_get_function_mux(__maybe_unused unsigned int pin, unsigned int selector) +{ + return msm_pinctrl_functions[selector].val; +} + +static struct msm_pinctrl_data sc7280_data = { + .pin_data = { + .pin_count = 183, + .special_pins_start = 175, + .special_pins_data = sc7280_special_pins_data, + }, + .functions_count = ARRAY_SIZE(msm_pinctrl_functions), + .get_function_name = sc7280_get_function_name, + .get_function_mux = sc7280_get_function_mux, + .get_pin_name = sc7280_get_pin_name, +}; + +static const struct udevice_id msm_pinctrl_ids[] = { + { + .compatible = "qcom,sc7280-pinctrl", + .data = (ulong)&sc7280_data + }, + { /* Sentinel */ } }; + +U_BOOT_DRIVER(pinctrl_sc7280) = { + .name = "pinctrl_sc7280", + .id = UCLASS_NOP, + .of_match = msm_pinctrl_ids, + .ops = &msm_pinctrl_ops, + .bind = msm_pinctrl_bind, +}; diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845.c b/drivers/pinctrl/qcom/pinctrl-sdm845.c index f1a23f51099..3f55fc81c8e 100644 --- a/drivers/pinctrl/qcom/pinctrl-sdm845.c +++ b/drivers/pinctrl/qcom/pinctrl-sdm845.c @@ -80,8 +80,8 @@ static const char *sdm845_get_pin_name(struct udevice *dev, return pin_name; } -static unsigned int sdm845_get_function_mux(__maybe_unused unsigned int pin, - unsigned int selector) +static int sdm845_get_function_mux(__maybe_unused unsigned int pin, + unsigned int selector) { return msm_pinctrl_functions[selector].val; } diff --git a/drivers/pinctrl/qcom/pinctrl-sm6115.c b/drivers/pinctrl/qcom/pinctrl-sm6115.c index f07f39f4ac3..7e80ea39a12 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm6115.c +++ b/drivers/pinctrl/qcom/pinctrl-sm6115.c @@ -167,7 +167,7 @@ static const char *sm6115_get_pin_name(struct udevice *dev, unsigned int selecto return pin_name; } -static unsigned int sm6115_get_function_mux(__maybe_unused unsigned int pin, unsigned int selector) +static int sm6115_get_function_mux(__maybe_unused unsigned int pin, unsigned int selector) { return msm_pinctrl_functions[selector].val; } diff --git a/drivers/pinctrl/qcom/pinctrl-sm8150.c b/drivers/pinctrl/qcom/pinctrl-sm8150.c index 1fb2ffb9597..fe789e8639b 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8150.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8150.c @@ -123,8 +123,8 @@ static const char *sm8150_get_pin_name(struct udevice *dev, return pin_name; } -static unsigned int sm8150_get_function_mux(__maybe_unused unsigned int pin, - unsigned int selector) +static int sm8150_get_function_mux(__maybe_unused unsigned int pin, + unsigned int selector) { return msm_pinctrl_functions[selector].val; } diff --git a/drivers/pinctrl/qcom/pinctrl-sm8250.c b/drivers/pinctrl/qcom/pinctrl-sm8250.c index b21cdc4d24b..d5447651695 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8250.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8250.c @@ -99,7 +99,7 @@ static const char *sm8250_get_pin_name(struct udevice *dev, unsigned int selecto return pin_name; } -static unsigned int sm8250_get_function_mux(__maybe_unused unsigned int pin, unsigned int selector) +static int sm8250_get_function_mux(__maybe_unused unsigned int pin, unsigned int selector) { return msm_pinctrl_functions[selector].val; } diff --git a/drivers/pinctrl/qcom/pinctrl-sm8550.c b/drivers/pinctrl/qcom/pinctrl-sm8550.c index 25b972a6d82..f7fcad0e4aa 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8550.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8550.c @@ -68,8 +68,8 @@ static const char *sm8550_get_pin_name(struct udevice *dev, return pin_name; } -static unsigned int sm8550_get_function_mux(__maybe_unused unsigned int pin, - unsigned int selector) +static int sm8550_get_function_mux(__maybe_unused unsigned int pin, + unsigned int selector) { return msm_pinctrl_functions[selector].val; } diff --git a/drivers/pinctrl/qcom/pinctrl-sm8650.c b/drivers/pinctrl/qcom/pinctrl-sm8650.c index 9146d6abd9a..6b9d56b1058 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8650.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8650.c @@ -69,8 +69,8 @@ static const char *sm8650_get_pin_name(struct udevice *dev, return pin_name; } -static unsigned int sm8650_get_function_mux(__maybe_unused unsigned int pin, - unsigned int selector) +static int sm8650_get_function_mux(__maybe_unused unsigned int pin, + unsigned int selector) { return msm_pinctrl_functions[selector].val; } diff --git a/drivers/pinctrl/qcom/pinctrl-x1e80100.c b/drivers/pinctrl/qcom/pinctrl-x1e80100.c index f39dc426d68..319667bfc16 100644 --- a/drivers/pinctrl/qcom/pinctrl-x1e80100.c +++ b/drivers/pinctrl/qcom/pinctrl-x1e80100.c @@ -72,8 +72,8 @@ static const char *x1e80100_get_pin_name(struct udevice *dev, return pin_name; } -static unsigned int x1e80100_get_function_mux(__maybe_unused unsigned int pin, - unsigned int selector) +static int x1e80100_get_function_mux(__maybe_unused unsigned int pin, + unsigned int selector) { return msm_pinctrl_functions[selector].val; } diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig index 958f337c7e7..8f102a92c23 100644 --- a/drivers/power/regulator/Kconfig +++ b/drivers/power/regulator/Kconfig @@ -478,3 +478,11 @@ config DM_REGULATOR_TPS65219 features for REGULATOR TPS65219 and the family of TPS65219 PMICs. TPS65219 series of PMICs have 3 single phase BUCKs & 4 LDOs. The driver implements get/set api for value and enable. + +config REGULATOR_RZG2L_USBPHY + bool "Enable driver for RZ/G2L USB PHY VBUS supply" + depends on DM_REGULATOR + help + Enable this option to support controlling the VBUS supply in + the USB PHY peripheral of the Renesas RZ/G2L SoC. This option + is required in order to use the USB OTG port. diff --git a/drivers/power/regulator/Makefile b/drivers/power/regulator/Makefile index ca6c89d13b5..4382d4b3ab9 100644 --- a/drivers/power/regulator/Makefile +++ b/drivers/power/regulator/Makefile @@ -42,3 +42,4 @@ obj-$(CONFIG_DM_REGULATOR_TPS65941) += tps65941_regulator.o obj-$(CONFIG_DM_REGULATOR_SCMI) += scmi_regulator.o obj-$(CONFIG_$(XPL_)DM_REGULATOR_ANATOP) += anatop_regulator.o obj-$(CONFIG_DM_REGULATOR_TPS65219) += tps65219_regulator.o +obj-$(CONFIG_REGULATOR_RZG2L_USBPHY) += rzg2l-usbphy-regulator.o diff --git a/drivers/power/regulator/rzg2l-usbphy-regulator.c b/drivers/power/regulator/rzg2l-usbphy-regulator.c new file mode 100644 index 00000000000..451f04c140e --- /dev/null +++ b/drivers/power/regulator/rzg2l-usbphy-regulator.c @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2024 Renesas Electronics Corporation + */ + +#include <asm/io.h> +#include <dm.h> +#include <power/regulator.h> +#include <renesas/rzg2l-usbphy.h> + +#define VBENCTL 0x03c +#define VBENCTL_VBUS_SEL BIT(0) + +static int rzg2l_usbphy_regulator_set_enable(struct udevice *dev, bool enable) +{ + struct rzg2l_usbphy_ctrl_priv *priv = dev_get_priv(dev->parent); + + if (enable) + clrbits_le32(priv->regs + VBENCTL, VBENCTL_VBUS_SEL); + else + setbits_le32(priv->regs + VBENCTL, VBENCTL_VBUS_SEL); + + return 0; +} + +static int rzg2l_usbphy_regulator_get_enable(struct udevice *dev) +{ + struct rzg2l_usbphy_ctrl_priv *priv = dev_get_priv(dev->parent); + + return !!readl(priv->regs + VBENCTL) & VBENCTL_VBUS_SEL; +} + +static const struct dm_regulator_ops rzg2l_usbphy_regulator_ops = { + .get_enable = rzg2l_usbphy_regulator_get_enable, + .set_enable = rzg2l_usbphy_regulator_set_enable, +}; + +U_BOOT_DRIVER(rzg2l_usbphy_regulator) = { + .name = "rzg2l_usbphy_regulator", + .id = UCLASS_REGULATOR, + .ops = &rzg2l_usbphy_regulator_ops, +}; diff --git a/drivers/ram/renesas/dbsc5/dbsc5.c b/drivers/ram/renesas/dbsc5/dbsc5.c index d24b7c5c30a..4cbc6aeda43 100644 --- a/drivers/ram/renesas/dbsc5/dbsc5.c +++ b/drivers/ram/renesas/dbsc5/dbsc5.c @@ -59,7 +59,8 @@ int renesas_dbsc5_bind(struct udevice *dev) struct renesas_dbsc5_data r8a779g0_dbsc5_data = { .clock_node = "renesas,r8a779g0-cpg-mssr", - .reset_node = "renesas,r8a779g0-rst" + .reset_node = "renesas,r8a779g0-rst", + .otp_node = "renesas,r8a779g0-otp", }; static const struct udevice_id renesas_dbsc5_ids[] = { diff --git a/drivers/ram/renesas/dbsc5/dbsc5.h b/drivers/ram/renesas/dbsc5/dbsc5.h index c410eb0c5ed..bf22fcb8c11 100644 --- a/drivers/ram/renesas/dbsc5/dbsc5.h +++ b/drivers/ram/renesas/dbsc5/dbsc5.h @@ -23,6 +23,7 @@ struct renesas_dbsc5_data { const char *clock_node; const char *reset_node; + const char *otp_node; }; #endif /* __DRIVERS_RAM_RENESAS_DBSC5_DBSC5_H__ */ diff --git a/drivers/ram/renesas/dbsc5/dram.c b/drivers/ram/renesas/dbsc5/dram.c index 210a68f6496..6f78afb0ab5 100644 --- a/drivers/ram/renesas/dbsc5/dram.c +++ b/drivers/ram/renesas/dbsc5/dram.c @@ -4,6 +4,7 @@ */ #include <asm/io.h> +#include <dbsc5.h> #include <dm.h> #include <errno.h> #include <hang.h> @@ -12,13 +13,6 @@ #include <linux/sizes.h> #include "dbsc5.h" -/* The number of channels V4H has */ -#define DRAM_CH_CNT 4 -/* The number of slices V4H has */ -#define SLICE_CNT 2 -/* The number of chip select V4H has */ -#define CS_CNT 2 - /* Number of array elements in Data Slice */ #define DDR_PHY_SLICE_REGSET_SIZE_V4H 0x100 /* Number of array elements in Data Slice */ @@ -220,6 +214,7 @@ static const u16 jedec_spec2_tRFC_ab[] = { #define PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS DDR_REGDEF(0x00, 0x09, 0x103F) #define PHY_WDQLVL_STATUS_OBS DDR_REGDEF(0x00, 0x20, 0x1043) #define PHY_DATA_DC_CAL_START DDR_REGDEF(0x18, 0x01, 0x104D) +#define PHY_SLV_DLY_CTRL_GATE_DISABLE DDR_REGDEF(0x10, 0x01, 0x104E) #define PHY_REGULATOR_EN_CNT DDR_REGDEF(0x18, 0x06, 0x1050) #define PHY_VREF_INITIAL_START_POINT DDR_REGDEF(0x00, 0x09, 0x1055) #define PHY_VREF_INITIAL_STOP_POINT DDR_REGDEF(0x10, 0x09, 0x1055) @@ -469,7 +464,7 @@ static const u32 DDR_PHY_SLICE_REGSET_V4H[DDR_PHY_SLICE_REGSET_NUM_V4H] = { 0x00000000, 0x00500050, 0x00500050, 0x00500050, 0x00500050, 0x0D000050, 0x10100004, 0x06102010, 0x61619041, 0x07097000, 0x00644180, 0x00803280, - 0x00808001, 0x13010100, 0x02000016, 0x10001003, + 0x00808001, 0x13010101, 0x02000016, 0x10001003, 0x06093E42, 0x0F063D01, 0x011700C8, 0x04100140, 0x00000100, 0x000001D1, 0x05000068, 0x00030402, 0x01400000, 0x80800300, 0x00160010, 0x76543210, @@ -512,8 +507,8 @@ static const u32 DDR_PHY_ADR_G_REGSET_V4H[DDR_PHY_ADR_G_REGSET_NUM_V4H] = { 0x00040101, 0x00000000, 0x00000000, 0x00000064, 0x00000000, 0x00000000, 0x39421B42, 0x00010124, 0x00520052, 0x00000052, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x07030102, + 0x00010001, 0x00000000, 0x00000000, 0x00010001, + 0x00000000, 0x00000000, 0x00010001, 0x07030102, 0x01030307, 0x00000054, 0x00004096, 0x08200820, 0x08200820, 0x08200820, 0x08200820, 0x00000820, 0x004103B8, 0x0000003F, 0x000C0006, 0x00000000, @@ -1294,7 +1289,7 @@ static const struct dbsc5_table_patch dbsc5_table_patch_slice_mbpsdiv_572 = { }; static const struct dbsc5_table_patch dbsc5_table_patch_adr_g_mbpsdiv_572 = { - PHY_PAD_ACS_RX_PCLK_CLK_SEL, 0x03 + PHY_PAD_ACS_RX_PCLK_CLK_SEL, 0x02 }; static const struct dbsc5_table_patch dbsc5_table_patch_adr_g_mbpsdiv_400[] = { @@ -1374,46 +1369,6 @@ static const u32 PI_DARRAY3_1_CSx_Fx[CS_CNT][3] = { #define CLK_DIV(a, diva, b, divb) (((a) * (divb)) / ((b) * (diva))) -struct renesas_dbsc5_board_config { - /* Channels in use */ - u8 bdcfg_phyvalid; - /* Read vref (SoC) training range */ - u32 bdcfg_vref_r; - /* Write vref (MR14, MR15) training range */ - u16 bdcfg_vref_w; - /* CA vref (MR12) training range */ - u16 bdcfg_vref_ca; - /* RFM required check */ - bool bdcfg_rfm_chk; - - /* Board parameter about channels */ - struct { - /* - * 0x00: 4Gb dual channel die / 2Gb single channel die - * 0x01: 6Gb dual channel die / 3Gb single channel die - * 0x02: 8Gb dual channel die / 4Gb single channel die - * 0x03: 12Gb dual channel die / 6Gb single channel die - * 0x04: 16Gb dual channel die / 8Gb single channel die - * 0x05: 24Gb dual channel die / 12Gb single channel die - * 0x06: 32Gb dual channel die / 16Gb single channel die - * 0x07: 24Gb single channel die - * 0x08: 32Gb single channel die - * 0xFF: NO_MEMORY - */ - u8 bdcfg_ddr_density[CS_CNT]; - /* SoC caX([6][5][4][3][2][1][0]) -> MEM caY: */ - u32 bdcfg_ca_swap; - /* SoC dqsX([1][0]) -> MEM dqsY: */ - u8 bdcfg_dqs_swap; - /* SoC dq([7][6][5][4][3][2][1][0]) -> MEM dqY/dm: (8 means DM) */ - u32 bdcfg_dq_swap[SLICE_CNT]; - /* SoC dm -> MEM dqY/dm: (8 means DM) */ - u8 bdcfg_dm_swap[SLICE_CNT]; - /* SoC ckeX([1][0]) -> MEM csY */ - u8 bdcfg_cs_swap; - } ch[4]; -}; - struct renesas_dbsc5_dram_priv { void __iomem *regs; void __iomem *cpg_regs; @@ -1713,14 +1668,17 @@ static void dbsc5_clk_wait_dbpdstat1(struct udevice *dev, u32 status) { struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET; - u32 i, ch, reg; + u32 i, ch, chk, reg; for (i = 0; i < 2; i++) { do { reg = status; - r_foreach_vch(dev, ch) + chk = 0; + r_foreach_vch(dev, ch) { reg &= readl(regs_dbsc_d + DBSC_DBPDSTAT1(ch)); - } while (reg != status); + chk |= readl(regs_dbsc_d + DBSC_DBPDSTAT0(ch)); + } + } while (reg != status && !(chk & BIT(0))); } } @@ -2192,7 +2150,7 @@ static void dbsc5_ddrtbl_calc(struct renesas_dbsc5_dram_priv *priv) if (js1[i].fx3 * 2 * priv->ddr_mbpsdiv >= priv->ddr_mbps * 3) break; - priv->js1_ind = max(i, JS1_USABLEC_SPEC_HI); + priv->js1_ind = clamp(i, 0, JS1_USABLEC_SPEC_HI); priv->RL = js1[priv->js1_ind].RLset1; priv->WL = js1[priv->js1_ind].WLsetA; @@ -2635,7 +2593,7 @@ static void dbsc5_dbsc_regset(struct udevice *dev) */ dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(11), priv->RL + 4 + priv->js2[JS2_tWCK2DQO_HF] - - js1[priv->js1_ind].ODTLon - priv->js2[JS2_tODTon_min]); + js1[priv->js1_ind].ODTLon - priv->js2[JS2_tODTon_min] + 2); /* DBTR12.TWRRD_S : WL + BL/2 + tWTR_S, TWRRD_L : WL + BL + tWTR_L */ dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(12), @@ -3491,13 +3449,10 @@ static void dbsc5_manual_write_dca(struct udevice *dev) { struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); const u32 rank = priv->ch_have_this_cs[1] ? 0x2 : 0x1; - u32 slv_dly_center[DRAM_CH_CNT][CS_CNT][SLICE_CNT]; - u32 slv_dly_center_cyc; - u32 slv_dly_center_dly; + u32 phy_slv_dly[DRAM_CH_CNT][CS_CNT][SLICE_CNT]; + u32 phy_slv_dly_avg[DRAM_CH_CNT][SLICE_CNT]; u32 slv_dly_min[DRAM_CH_CNT][SLICE_CNT]; u32 slv_dly_max[DRAM_CH_CNT][SLICE_CNT]; - u32 slv_dly_min_tmp[DRAM_CH_CNT][CS_CNT][SLICE_CNT]; - u32 slv_dly_max_tmp[DRAM_CH_CNT][CS_CNT][SLICE_CNT]; u32 phy_dcc_code_min[DRAM_CH_CNT][SLICE_CNT]; u32 phy_dcc_code_max[DRAM_CH_CNT][SLICE_CNT]; u32 phy_dcc_code_mid; @@ -3521,18 +3476,9 @@ static void dbsc5_manual_write_dca(struct udevice *dev) dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_PER_CS_TRAINING_INDEX, cs); r_foreach_vch(dev, ch) { for (slice = 0; slice < SLICE_CNT; slice++) { - slv_dly_center[ch][cs][slice] = - dbsc5_ddr_getval_slice(dev, ch, slice, PHY_CLK_WRDQS_SLAVE_DELAY); - slv_dly_center_cyc = slv_dly_center[ch][cs][slice] & 0x180; - slv_dly_center_dly = slv_dly_center[ch][cs][slice] & 0x7F; - slv_dly_min_tmp[ch][cs][slice] = - slv_dly_center_cyc | - (slv_dly_center_dly * ratio_min / ratio_min_div); - slv_dly_max_tmp[ch][cs][slice] = slv_dly_center_cyc; - if ((slv_dly_center_dly * ratio_max) > (0x7F * ratio_max_div)) - slv_dly_max_tmp[ch][cs][slice] |= 0x7F; - else - slv_dly_max_tmp[ch][cs][slice] |= slv_dly_center_dly * ratio_max / ratio_max_div; + phy_slv_dly[ch][cs][slice] = + dbsc5_ddr_getval_slice(dev, ch, slice, + PHY_CLK_WRDQS_SLAVE_DELAY); } } } @@ -3540,22 +3486,22 @@ static void dbsc5_manual_write_dca(struct udevice *dev) r_foreach_vch(dev, ch) { for (slice = 0; slice < SLICE_CNT; slice++) { if (rank == 0x2) { - if (slv_dly_max_tmp[ch][0][slice] < slv_dly_max_tmp[ch][1][slice]) - slv_dly_max[ch][slice] = slv_dly_max_tmp[ch][1][slice]; - else - slv_dly_max[ch][slice] = slv_dly_max_tmp[ch][0][slice]; - - if (slv_dly_min_tmp[ch][0][slice] < slv_dly_min_tmp[ch][1][slice]) - slv_dly_min[ch][slice] = slv_dly_min_tmp[ch][0][slice]; - else - slv_dly_min[ch][slice] = slv_dly_min_tmp[ch][1][slice]; + /* Calculate average between ranks */ + phy_slv_dly_avg[ch][slice] = (phy_slv_dly[ch][0][slice] + + phy_slv_dly[ch][1][slice]) / 2; } else { - slv_dly_max[ch][slice] = slv_dly_max_tmp[ch][0][slice]; - slv_dly_min[ch][slice] = slv_dly_min_tmp[ch][0][slice]; + phy_slv_dly_avg[ch][slice] = phy_slv_dly[ch][0][slice]; } + /* Determine the search range */ + slv_dly_min[ch][slice] = (phy_slv_dly_avg[ch][slice] & 0x07F) * ratio_min / ratio_min_div; + slv_dly_max[ch][slice] = (phy_slv_dly_avg[ch][slice] & 0x07F) * ratio_max / ratio_max_div; + if (slv_dly_max[ch][slice] > 0x7F) + slv_dly_max[ch][slice] = 0x7F; } } + dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_SLV_DLY_CTRL_GATE_DISABLE, 0x1); + for (i = 0; i <= 0x7F; i++) { r_foreach_vch(dev, ch) { for (slice = 0; slice < SLICE_CNT; slice++) { @@ -3621,13 +3567,16 @@ static void dbsc5_manual_write_dca(struct udevice *dev) for (slice = 0; slice < SLICE_CNT; slice++) { dbsc5_ddr_setval_slice(dev, ch, slice, PHY_CLK_WRDQS_SLAVE_DELAY, - slv_dly_center[ch][cs][slice]); + phy_slv_dly[ch][cs][slice]); dbsc5_ddr_setval_slice(dev, ch, slice, SC_PHY_WCK_CALC, 0x1); dbsc5_ddr_setval(dev, ch, SC_PHY_MANUAL_UPDATE, 0x1); } } } + + dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_SLV_DLY_CTRL_GATE_DISABLE, 0x0); + dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_PER_CS_TRAINING_MULTICAST_EN, 0x1); r_foreach_vch(dev, ch) { @@ -4369,16 +4318,20 @@ static int renesas_dbsc5_dram_probe(struct udevice *dev) { #define RST_MODEMR0 0x0 #define RST_MODEMR1 0x4 +#define OTP_MONITOR17 0x1144 struct renesas_dbsc5_data *data = (struct renesas_dbsc5_data *)dev_get_driver_data(dev); ofnode cnode = ofnode_by_compatible(ofnode_null(), data->clock_node); ofnode rnode = ofnode_by_compatible(ofnode_null(), data->reset_node); + ofnode onode = ofnode_by_compatible(ofnode_null(), data->otp_node); struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); void __iomem *regs_dbsc_a = priv->regs + DBSC5_DBSC_A_OFFSET; void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET; phys_addr_t rregs = ofnode_get_addr(rnode); const u32 modemr0 = readl(rregs + RST_MODEMR0); const u32 modemr1 = readl(rregs + RST_MODEMR1); - u32 breg, reg, md, sscg; + phys_addr_t oregs = ofnode_get_addr(onode); + const u32 otpmon17 = readl(oregs + OTP_MONITOR17); + u32 breg, reg, md, sscg, product; u32 ch, cs; /* Get board data */ @@ -4433,29 +4386,41 @@ static int renesas_dbsc5_dram_probe(struct udevice *dev) /* Decode DDR operating frequency from MD[37:36,19,17] pins */ md = ((modemr0 & BIT(19)) >> 18) | ((modemr0 & BIT(17)) >> 17); + product = otpmon17 & 0xff; sscg = (modemr1 >> 4) & 0x03; if (sscg == 2) { printf("MD[37:36] setting 0x%x not supported!", sscg); hang(); } - if (md == 0) { - if (sscg == 0) { - priv->ddr_mbps = 6400; - priv->ddr_mbpsdiv = 1; - } else { - priv->ddr_mbps = 19000; - priv->ddr_mbpsdiv = 3; - } - } else if (md == 1) { - priv->ddr_mbps = 6000; - priv->ddr_mbpsdiv = 1; - } else if (md == 1) { - priv->ddr_mbps = 5500; - priv->ddr_mbpsdiv = 1; - } else if (md == 1) { + if (product == 0x2) { /* V4H-3 */ priv->ddr_mbps = 4800; priv->ddr_mbpsdiv = 1; + } else if (product == 0x1) { /* V4H-5 */ + if (md == 3) + priv->ddr_mbps = 4800; + else + priv->ddr_mbps = 5000; + priv->ddr_mbpsdiv = 1; + } else { /* V4H-7 */ + if (md == 0) { + if (sscg == 0) { + priv->ddr_mbps = 6400; + priv->ddr_mbpsdiv = 1; + } else { + priv->ddr_mbps = 19000; + priv->ddr_mbpsdiv = 3; + } + } else if (md == 1) { + priv->ddr_mbps = 6000; + priv->ddr_mbpsdiv = 1; + } else if (md == 2) { + priv->ddr_mbps = 5500; + priv->ddr_mbpsdiv = 1; + } else if (md == 3) { + priv->ddr_mbps = 4800; + priv->ddr_mbpsdiv = 1; + } } priv->ddr_mul = CLK_DIV(priv->ddr_mbps, priv->ddr_mbpsdiv * 2, diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index fe5c1214f57..b408f19a20b 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -235,4 +235,20 @@ config RESET_AT91 This enables the Reset Controller driver support for Microchip/Atmel SoCs. Mainly used to expose assert/deassert methods to other drivers that require it. + +config RESET_RZG2L_USBPHY_CTRL + bool "Enable support for Renesas RZ/G2L USB 2.0 PHY control" + depends on DM_RESET + select REGULATOR_RZG2L_USBPHY + help + Enable support for controlling USB 2.0 PHY resets on the Renesas + RZ/G2L SoC. This is required for USB 2.0 functionality to work on this + SoC. + +config RESET_SPACEMIT_K1 + bool "Support for SPACEMIT's K1 Reset driver" + depends on DM_RESET + help + Support for SPACEMIT's K1 Reset system. Basic Assert/Deassert + is supported. endmenu diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index d99a78c9828..8cab734bdab 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -33,3 +33,5 @@ obj-$(CONFIG_RESET_ZYNQMP) += reset-zynqmp.o obj-$(CONFIG_RESET_DRA7) += reset-dra7.o obj-$(CONFIG_RESET_AT91) += reset-at91.o obj-$(CONFIG_$(PHASE_)RESET_JH7110) += reset-jh7110.o +obj-$(CONFIG_RESET_RZG2L_USBPHY_CTRL) += reset-rzg2l-usbphy-ctrl.o +obj-$(CONFIG_RESET_SPACEMIT_K1) += reset-spacemit-k1.o diff --git a/drivers/reset/reset-rzg2l-usbphy-ctrl.c b/drivers/reset/reset-rzg2l-usbphy-ctrl.c new file mode 100644 index 00000000000..622d7b9cf4f --- /dev/null +++ b/drivers/reset/reset-rzg2l-usbphy-ctrl.c @@ -0,0 +1,142 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2024 Renesas Electronics Corporation + */ + +#include <asm/io.h> +#include <dm.h> +#include <dm/device-internal.h> +#include <dm/device_compat.h> +#include <dm/lists.h> +#include <renesas/rzg2l-usbphy.h> +#include <reset-uclass.h> +#include <reset.h> + +#define RESET 0x000 + +#define RESET_SEL_PLLRESET BIT(12) +#define RESET_PLLRESET BIT(8) + +#define RESET_SEL_P2RESET BIT(5) +#define RESET_SEL_P1RESET BIT(4) +#define RESET_PHYRST_2 BIT(1) +#define RESET_PHYRST_1 BIT(0) + +#define PHY_RESET_MASK (RESET_PHYRST_1 | RESET_PHYRST_2) + +#define NUM_PORTS 2 + +static int rzg2l_usbphy_ctrl_assert(struct reset_ctl *reset_ctl) +{ + struct rzg2l_usbphy_ctrl_priv *priv = dev_get_priv(reset_ctl->dev); + u32 val; + + val = readl(priv->regs + RESET); + val |= reset_ctl->id ? RESET_PHYRST_2 : RESET_PHYRST_1; + + /* If both ports are in reset, we can also place the PLL into reset. */ + if ((val & PHY_RESET_MASK) == PHY_RESET_MASK) + val |= RESET_PLLRESET; + + writel(val, priv->regs + RESET); + return 0; +} + +static int rzg2l_usbphy_ctrl_deassert(struct reset_ctl *reset_ctl) +{ + struct rzg2l_usbphy_ctrl_priv *priv = dev_get_priv(reset_ctl->dev); + u32 val = reset_ctl->id ? RESET_PHYRST_2 : RESET_PHYRST_1; + + /* If either port is out of reset, the PLL must also be out of reset. */ + val |= RESET_PLLRESET; + + clrbits_le32(priv->regs + RESET, val); + return 0; +} + +static int rzg2l_usbphy_ctrl_of_xlate(struct reset_ctl *reset_ctl, + struct ofnode_phandle_args *args) +{ + if (args->args[0] >= NUM_PORTS) + return -EINVAL; + + reset_ctl->id = args->args[0]; + return 0; +} + +struct reset_ops rzg2l_usbphy_ctrl_ops = { + .rst_assert = rzg2l_usbphy_ctrl_assert, + .rst_deassert = rzg2l_usbphy_ctrl_deassert, + .of_xlate = rzg2l_usbphy_ctrl_of_xlate, +}; + +static int rzg2l_usbphy_ctrl_probe(struct udevice *dev) +{ + struct rzg2l_usbphy_ctrl_priv *priv = dev_get_priv(dev); + struct reset_ctl rst; + int ret; + + priv->regs = dev_read_addr(dev); + + ret = reset_get_by_index(dev, 0, &rst); + if (ret < 0) { + dev_err(dev, "failed to get reset line: %d\n", ret); + return ret; + } + + ret = reset_deassert(&rst); + if (ret < 0) { + dev_err(dev, "failed to de-assert reset line: %d\n", ret); + return ret; + } + + /* put pll and phy into reset state */ + setbits_le32(priv->regs + RESET, + RESET_SEL_PLLRESET | RESET_PLLRESET | + RESET_SEL_P1RESET | RESET_PHYRST_1 | + RESET_SEL_P2RESET | RESET_PHYRST_2); + + return 0; +} + +static const struct udevice_id rzg2l_usbphy_ctrl_ids[] = { + { .compatible = "renesas,rzg2l-usbphy-ctrl", }, + { /* sentinel */ } +}; + +static int rzg2l_usbphy_ctrl_bind(struct udevice *dev) +{ + struct driver *drv; + ofnode node; + int ret; + + node = ofnode_find_subnode(dev_ofnode(dev), "regulator-vbus"); + if (!ofnode_valid(node)) { + dev_err(dev, "Failed to find vbus regulator devicetree node\n"); + return -ENOENT; + } + + drv = lists_driver_lookup_name("rzg2l_usbphy_regulator"); + if (!drv) { + dev_err(dev, "Failed to find vbus regulator driver\n"); + return -ENOENT; + } + + ret = device_bind(dev, drv, dev->name, NULL, node, NULL); + if (ret) { + dev_err(dev, "Failed to bind vbus regulator: %d\n", ret); + return ret; + } + + return 0; +} + +U_BOOT_DRIVER(rzg2l_usbphy_ctrl) = { + .name = "rzg2l_usbphy_ctrl", + .id = UCLASS_RESET, + .of_match = rzg2l_usbphy_ctrl_ids, + .bind = rzg2l_usbphy_ctrl_bind, + .probe = rzg2l_usbphy_ctrl_probe, + .ops = &rzg2l_usbphy_ctrl_ops, + .priv_auto = sizeof(struct rzg2l_usbphy_ctrl_priv), +}; diff --git a/drivers/reset/reset-spacemit-k1.c b/drivers/reset/reset-spacemit-k1.c new file mode 100644 index 00000000000..613e002fc4f --- /dev/null +++ b/drivers/reset/reset-spacemit-k1.c @@ -0,0 +1,548 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 Spacemit Inc. + * Copyright (C) 2025 Huan Zhou <pericycle.cc@gmail.com> + */ + +#include <asm/io.h> +#include <config.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <dm/device-internal.h> +#include <dm/lists.h> +#include <dt-bindings/reset/spacemit-k1-reset.h> +#include <linux/bitops.h> +#include <reset-uclass.h> + +/* APBC register offset */ +#define APBC_UART1_CLK_RST 0x0 +#define APBC_UART2_CLK_RST 0x4 +#define APBC_GPIO_CLK_RST 0x8 +#define APBC_PWM0_CLK_RST 0xc +#define APBC_PWM1_CLK_RST 0x10 +#define APBC_PWM2_CLK_RST 0x14 +#define APBC_PWM3_CLK_RST 0x18 +#define APBC_TWSI8_CLK_RST 0x20 +#define APBC_UART3_CLK_RST 0x24 +#define APBC_RTC_CLK_RST 0x28 +#define APBC_TWSI0_CLK_RST 0x2c +#define APBC_TWSI1_CLK_RST 0x30 +#define APBC_TIMERS1_CLK_RST 0x34 +#define APBC_TWSI2_CLK_RST 0x38 +#define APBC_AIB_CLK_RST 0x3c +#define APBC_TWSI4_CLK_RST 0x40 +#define APBC_TIMERS2_CLK_RST 0x44 +#define APBC_ONEWIRE_CLK_RST 0x48 +#define APBC_TWSI5_CLK_RST 0x4c +#define APBC_DRO_CLK_RST 0x58 +#define APBC_IR_CLK_RST 0x5c +#define APBC_TWSI6_CLK_RST 0x60 +#define APBC_TWSI7_CLK_RST 0x68 +#define APBC_TSEN_CLK_RST 0x6c + +#define APBC_UART4_CLK_RST 0x70 +#define APBC_UART5_CLK_RST 0x74 +#define APBC_UART6_CLK_RST 0x78 +#define APBC_SSP3_CLK_RST 0x7c + +#define APBC_SSPA0_CLK_RST 0x80 +#define APBC_SSPA1_CLK_RST 0x84 + +#define APBC_IPC_AP2AUD_CLK_RST 0x90 +#define APBC_UART7_CLK_RST 0x94 +#define APBC_UART8_CLK_RST 0x98 +#define APBC_UART9_CLK_RST 0x9c + +#define APBC_CAN0_CLK_RST 0xa0 +#define APBC_PWM4_CLK_RST 0xa8 +#define APBC_PWM5_CLK_RST 0xac +#define APBC_PWM6_CLK_RST 0xb0 +#define APBC_PWM7_CLK_RST 0xb4 +#define APBC_PWM8_CLK_RST 0xb8 +#define APBC_PWM9_CLK_RST 0xbc +#define APBC_PWM10_CLK_RST 0xc0 +#define APBC_PWM11_CLK_RST 0xc4 +#define APBC_PWM12_CLK_RST 0xc8 +#define APBC_PWM13_CLK_RST 0xcc +#define APBC_PWM14_CLK_RST 0xd0 +#define APBC_PWM15_CLK_RST 0xd4 +#define APBC_PWM16_CLK_RST 0xd8 +#define APBC_PWM17_CLK_RST 0xdc +#define APBC_PWM18_CLK_RST 0xe0 +#define APBC_PWM19_CLK_RST 0xe4 +/* end of APBC register offset */ + +/* MPMU register offset */ +#define MPMU_WDTPCR 0x200 +/* end of MPMU register offset */ + +/* APMU register offset */ +#define APMU_JPG_CLK_RES_CTRL 0x20 +#define APMU_CSI_CCIC2_CLK_RES_CTRL 0x24 +#define APMU_ISP_CLK_RES_CTRL 0x38 +#define APMU_LCD_CLK_RES_CTRL1 0x44 +#define APMU_LCD_SPI_CLK_RES_CTRL 0x48 +#define APMU_LCD_CLK_RES_CTRL2 0x4c +#define APMU_CCIC_CLK_RES_CTRL 0x50 +#define APMU_SDH0_CLK_RES_CTRL 0x54 +#define APMU_SDH1_CLK_RES_CTRL 0x58 +#define APMU_USB_CLK_RES_CTRL 0x5c +#define APMU_QSPI_CLK_RES_CTRL 0x60 +#define APMU_USB_CLK_RES_CTRL 0x5c +#define APMU_DMA_CLK_RES_CTRL 0x64 +#define APMU_AES_CLK_RES_CTRL 0x68 +#define APMU_VPU_CLK_RES_CTRL 0xa4 +#define APMU_GPU_CLK_RES_CTRL 0xcc +#define APMU_SDH2_CLK_RES_CTRL 0xe0 +#define APMU_PMUA_MC_CTRL 0xe8 +#define APMU_PMU_CC2_AP 0x100 +#define APMU_PMUA_EM_CLK_RES_CTRL 0x104 + +#define APMU_AUDIO_CLK_RES_CTRL 0x14c +#define APMU_HDMI_CLK_RES_CTRL 0x1B8 + +#define APMU_PCIE_CLK_RES_CTRL_0 0x3cc +#define APMU_PCIE_CLK_RES_CTRL_1 0x3d4 +#define APMU_PCIE_CLK_RES_CTRL_2 0x3dc + +#define APMU_EMAC0_CLK_RES_CTRL 0x3e4 +#define APMU_EMAC1_CLK_RES_CTRL 0x3ec +/* end of APMU register offset */ + +/* APBC2 register offset */ +#define APBC2_UART1_CLK_RST 0x00 +#define APBC2_SSP2_CLK_RST 0x04 +#define APBC2_TWSI3_CLK_RST 0x08 +#define APBC2_RTC_CLK_RST 0x0c +#define APBC2_TIMERS0_CLK_RST 0x10 +#define APBC2_KPC_CLK_RST 0x14 +#define APBC2_GPIO_CLK_RST 0x1c +/* end of APBC2 register offset */ + +enum spacemit_reset_base_type { + RST_BASE_TYPE_MPMU = 0, + RST_BASE_TYPE_APMU = 1, + RST_BASE_TYPE_APBC = 2, + RST_BASE_TYPE_APBS = 3, + RST_BASE_TYPE_CIU = 4, + RST_BASE_TYPE_DCIU = 5, + RST_BASE_TYPE_DDRC = 6, + RST_BASE_TYPE_AUDC = 7, + RST_BASE_TYPE_APBC2 = 8, +}; + +struct spacemit_reset_signal { + u32 offset; + u32 mask; + u32 deassert_val; + u32 assert_val; + enum spacemit_reset_base_type type; +}; + +struct spacemit_reset_base { + void __iomem *mpmu_base; + void __iomem *apmu_base; + void __iomem *apbc_base; + void __iomem *apbs_base; + void __iomem *ciu_base; + void __iomem *dciu_base; + void __iomem *ddrc_base; + void __iomem *audio_ctrl_base; + void __iomem *apbc2_base; +}; + +struct spacemit_reset { + struct spacemit_reset_base io_base; + const struct spacemit_reset_signal *signals; +}; + +enum { + RESET_TWSI6_SPL = 0, + RESET_TWSI8_SPL, + RESET_SDH_AXI_SPL, + RESET_SDH0_SPL, + RESET_USB_AXI_SPL, + RESET_USBP1_AXI_SPL, + RESET_USB3_0_SPL, + RESET_QSPI_SPL, + RESET_QSPI_BUS_SPL, + RESET_AES_SPL, + RESET_SDH2_SPL, + RESET_NUMBER_SPL +}; + +static const struct spacemit_reset_signal + k1_reset_signals[RESET_NUMBER] = { + [RESET_UART1] = { APBC_UART1_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC }, + [RESET_UART2] = { APBC_UART2_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC }, + [RESET_GPIO] = { APBC_GPIO_CLK_RST, BIT(2), 0, + BIT(2), + RST_BASE_TYPE_APBC }, + [RESET_PWM0] = { APBC_PWM0_CLK_RST, + BIT(2) | BIT(0), + BIT(0), + BIT(2), + RST_BASE_TYPE_APBC }, + [RESET_PWM1] = { APBC_PWM1_CLK_RST, + BIT(2) | BIT(0), + BIT(0), + BIT(2), + RST_BASE_TYPE_APBC }, + [RESET_PWM2] = { APBC_PWM2_CLK_RST, + BIT(2) | BIT(0), + BIT(0), + BIT(2), + RST_BASE_TYPE_APBC }, + [RESET_PWM3] = { APBC_PWM3_CLK_RST, + BIT(2) | BIT(0), + BIT(0), + BIT(2), + RST_BASE_TYPE_APBC }, + [RESET_PWM4] = { APBC_PWM4_CLK_RST, + BIT(2) | BIT(0), + BIT(0), + BIT(2), + RST_BASE_TYPE_APBC }, + [RESET_PWM5] = { APBC_PWM5_CLK_RST, + BIT(2) | BIT(0), + BIT(0), + BIT(2), + RST_BASE_TYPE_APBC }, + [RESET_PWM6] = { APBC_PWM6_CLK_RST, + BIT(2) | BIT(0), + BIT(0), + BIT(2), + RST_BASE_TYPE_APBC }, + [RESET_PWM7] = { APBC_PWM7_CLK_RST, + BIT(2) | BIT(0), + BIT(0), + BIT(2), + RST_BASE_TYPE_APBC }, + [RESET_PWM8] = { APBC_PWM8_CLK_RST, + BIT(2) | BIT(0), + BIT(0), + BIT(2), + RST_BASE_TYPE_APBC }, + [RESET_PWM9] = { APBC_PWM9_CLK_RST, + BIT(2) | BIT(0), + BIT(0), + BIT(2), + RST_BASE_TYPE_APBC }, + [RESET_PWM10] = { APBC_PWM10_CLK_RST, + BIT(2) | BIT(0), + BIT(0), + BIT(2), + RST_BASE_TYPE_APBC }, + [RESET_PWM11] = { APBC_PWM11_CLK_RST, + BIT(2) | BIT(0), + BIT(0), + BIT(2), + RST_BASE_TYPE_APBC }, + [RESET_PWM12] = { APBC_PWM12_CLK_RST, + BIT(2) | BIT(0), + BIT(0), + BIT(2), + RST_BASE_TYPE_APBC }, + [RESET_PWM13] = { APBC_PWM13_CLK_RST, + BIT(2) | BIT(0), + BIT(0), + BIT(2), + RST_BASE_TYPE_APBC }, + [RESET_PWM14] = { APBC_PWM14_CLK_RST, + BIT(2) | BIT(0), + BIT(0), + BIT(2), + RST_BASE_TYPE_APBC }, + [RESET_PWM15] = { APBC_PWM15_CLK_RST, + BIT(2) | BIT(0), + BIT(0), + BIT(2), + RST_BASE_TYPE_APBC }, + [RESET_PWM16] = { APBC_PWM16_CLK_RST, + BIT(2) | BIT(0), + BIT(0), + BIT(2), + RST_BASE_TYPE_APBC }, + [RESET_PWM17] = { APBC_PWM17_CLK_RST, + BIT(2) | BIT(0), + BIT(0), + BIT(2), + RST_BASE_TYPE_APBC }, + [RESET_PWM18] = { APBC_PWM18_CLK_RST, + BIT(2) | BIT(0), + BIT(0), + BIT(2), + RST_BASE_TYPE_APBC }, + [RESET_PWM19] = { APBC_PWM19_CLK_RST, + BIT(2) | BIT(0), + BIT(0), + BIT(2), + RST_BASE_TYPE_APBC }, + [RESET_SSP3] = { APBC_SSP3_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC }, + [RESET_UART3] = { APBC_UART3_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC }, + [RESET_RTC] = { APBC_RTC_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC }, + [RESET_TWSI0] = { APBC_TWSI0_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC }, + [RESET_TIMERS1] = { APBC_TIMERS1_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC }, + [RESET_AIB] = { APBC_AIB_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC }, + [RESET_TIMERS2] = { APBC_TIMERS2_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC }, + [RESET_ONEWIRE] = { APBC_ONEWIRE_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC }, + [RESET_SSPA0] = { APBC_SSPA0_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC }, + [RESET_SSPA1] = { APBC_SSPA1_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC }, + [RESET_DRO] = { APBC_DRO_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC }, + [RESET_IR] = { APBC_IR_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC }, + [RESET_TWSI1] = { APBC_TWSI1_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC }, + [RESET_TSEN] = { APBC_TSEN_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC }, + [RESET_TWSI2] = { APBC_TWSI2_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC }, + [RESET_TWSI4] = { APBC_TWSI4_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC }, + [RESET_TWSI5] = { APBC_TWSI5_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC }, + [RESET_TWSI6] = { APBC_TWSI6_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC }, + [RESET_TWSI7] = { APBC_TWSI7_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC }, + [RESET_TWSI8] = { APBC_TWSI8_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC }, + [RESET_IPC_AP2AUD] = { APBC_IPC_AP2AUD_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC }, + [RESET_UART4] = { APBC_UART4_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC }, + [RESET_UART5] = { APBC_UART5_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC }, + [RESET_UART6] = { APBC_UART6_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC }, + [RESET_UART7] = { APBC_UART7_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC }, + [RESET_UART8] = { APBC_UART8_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC }, + [RESET_UART9] = { APBC_UART9_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC }, + [RESET_CAN0] = { APBC_CAN0_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC }, + /* MPMU */ + [RESET_WDT] = { MPMU_WDTPCR, BIT(2), 0, BIT(2), RST_BASE_TYPE_MPMU }, + /* APMU */ + [RESET_JPG] = { APMU_JPG_CLK_RES_CTRL, BIT(0), BIT(0), 0, RST_BASE_TYPE_APMU }, + [RESET_CSI] = { APMU_CSI_CCIC2_CLK_RES_CTRL, BIT(1), BIT(1), 0, RST_BASE_TYPE_APMU }, + [RESET_CCIC2_PHY] = { APMU_CSI_CCIC2_CLK_RES_CTRL, + BIT(2), + BIT(2), + 0, + RST_BASE_TYPE_APMU }, + [RESET_CCIC3_PHY] = { APMU_CSI_CCIC2_CLK_RES_CTRL, + BIT(29), + BIT(29), + 0, + RST_BASE_TYPE_APMU }, + [RESET_ISP] = { APMU_ISP_CLK_RES_CTRL, BIT(0), BIT(0), 0, RST_BASE_TYPE_APMU }, + [RESET_ISP_AHB] = { APMU_ISP_CLK_RES_CTRL, BIT(3), BIT(3), 0, RST_BASE_TYPE_APMU }, + [RESET_ISP_CI] = { APMU_ISP_CLK_RES_CTRL, BIT(16), BIT(16), 0, RST_BASE_TYPE_APMU }, + [RESET_ISP_CPP] = { APMU_ISP_CLK_RES_CTRL, BIT(27), BIT(27), 0, RST_BASE_TYPE_APMU }, + [RESET_LCD] = { APMU_LCD_CLK_RES_CTRL1, BIT(4), BIT(4), 0, RST_BASE_TYPE_APMU }, + [RESET_DSI_ESC] = { APMU_LCD_CLK_RES_CTRL1, BIT(3), BIT(3), 0, RST_BASE_TYPE_APMU }, + [RESET_V2D] = { APMU_LCD_CLK_RES_CTRL1, BIT(27), BIT(27), 0, RST_BASE_TYPE_APMU }, + [RESET_MIPI] = { APMU_LCD_CLK_RES_CTRL1, BIT(15), BIT(15), 0, RST_BASE_TYPE_APMU }, + [RESET_LCD_SPI] = { APMU_LCD_SPI_CLK_RES_CTRL, BIT(0), BIT(0), 0, RST_BASE_TYPE_APMU }, + [RESET_LCD_SPI_BUS] = { APMU_LCD_SPI_CLK_RES_CTRL, + BIT(4), + BIT(4), + 0, + RST_BASE_TYPE_APMU }, + [RESET_LCD_SPI_HBUS] = { APMU_LCD_SPI_CLK_RES_CTRL, + BIT(2), + BIT(2), + 0, + RST_BASE_TYPE_APMU }, + [RESET_LCD_MCLK] = { APMU_LCD_CLK_RES_CTRL2, BIT(9), BIT(9), 0, RST_BASE_TYPE_APMU }, + [RESET_CCIC_4X] = { APMU_CCIC_CLK_RES_CTRL, BIT(1), BIT(1), 0, RST_BASE_TYPE_APMU }, + [RESET_CCIC1_PHY] = { APMU_CCIC_CLK_RES_CTRL, BIT(2), BIT(2), 0, RST_BASE_TYPE_APMU }, + [RESET_SDH_AXI] = { APMU_SDH0_CLK_RES_CTRL, BIT(0), BIT(0), 0, RST_BASE_TYPE_APMU }, + [RESET_SDH0] = { APMU_SDH0_CLK_RES_CTRL, BIT(1), BIT(1), 0, RST_BASE_TYPE_APMU }, + [RESET_SDH1] = { APMU_SDH1_CLK_RES_CTRL, BIT(1), BIT(1), 0, RST_BASE_TYPE_APMU }, + [RESET_USB_AXI] = { APMU_USB_CLK_RES_CTRL, BIT(0), BIT(0), 0, RST_BASE_TYPE_APMU }, + [RESET_USBP1_AXI] = { APMU_USB_CLK_RES_CTRL, BIT(4), BIT(4), 0, RST_BASE_TYPE_APMU }, + [RESET_USB3_0] = { APMU_USB_CLK_RES_CTRL, + BIT(9) | BIT(10) | BIT(11), + BIT(9) | BIT(10) | BIT(11), + 0, + RST_BASE_TYPE_APMU }, + [RESET_QSPI] = { APMU_QSPI_CLK_RES_CTRL, BIT(1), BIT(1), 0, RST_BASE_TYPE_APMU }, + [RESET_QSPI_BUS] = { APMU_QSPI_CLK_RES_CTRL, BIT(0), BIT(0), 0, RST_BASE_TYPE_APMU }, + [RESET_DMA] = { APMU_DMA_CLK_RES_CTRL, BIT(0), BIT(0), 0, RST_BASE_TYPE_APMU }, + [RESET_AES] = { APMU_AES_CLK_RES_CTRL, BIT(4), BIT(4), 0, RST_BASE_TYPE_APMU }, + [RESET_VPU] = { APMU_VPU_CLK_RES_CTRL, BIT(0), BIT(0), 0, RST_BASE_TYPE_APMU }, + [RESET_GPU] = { APMU_GPU_CLK_RES_CTRL, BIT(1), BIT(1), 0, RST_BASE_TYPE_APMU }, + [RESET_SDH2] = { APMU_SDH2_CLK_RES_CTRL, BIT(1), BIT(1), 0, RST_BASE_TYPE_APMU }, + [RESET_MC] = { APMU_PMUA_MC_CTRL, BIT(0), BIT(0), 0, RST_BASE_TYPE_APMU }, + [RESET_EM_AXI] = { APMU_PMUA_EM_CLK_RES_CTRL, BIT(0), BIT(0), 0, RST_BASE_TYPE_APMU }, + [RESET_EM] = { APMU_PMUA_EM_CLK_RES_CTRL, BIT(1), BIT(1), 0, RST_BASE_TYPE_APMU }, + [RESET_AUDIO_SYS] = { APMU_AUDIO_CLK_RES_CTRL, + BIT(0) | BIT(2) | BIT(3), + BIT(0) | BIT(2) | BIT(3), + 0, + RST_BASE_TYPE_APMU }, + [RESET_HDMI] = { APMU_HDMI_CLK_RES_CTRL, BIT(9), BIT(9), 0, RST_BASE_TYPE_APMU }, + [RESET_PCIE0] = { APMU_PCIE_CLK_RES_CTRL_0, + BIT(3) | BIT(4) | BIT(5) | BIT(8), + BIT(3) | BIT(4) | BIT(5), + BIT(8), + RST_BASE_TYPE_APMU }, + [RESET_PCIE1] = { APMU_PCIE_CLK_RES_CTRL_1, + BIT(3) | BIT(4) | BIT(5) | BIT(8), + BIT(3) | BIT(4) | BIT(5), + BIT(8), + RST_BASE_TYPE_APMU }, + [RESET_PCIE2] = { APMU_PCIE_CLK_RES_CTRL_2, 0x138, 0x38, 0x100, RST_BASE_TYPE_APMU }, + [RESET_EMAC0] = { APMU_EMAC0_CLK_RES_CTRL, BIT(1), BIT(1), 0, RST_BASE_TYPE_APMU }, + [RESET_EMAC1] = { APMU_EMAC1_CLK_RES_CTRL, BIT(1), BIT(1), 0, RST_BASE_TYPE_APMU }, + [RESET_SEC_UART1] = { APBC2_UART1_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC2 }, + [RESET_SEC_SSP2] = { APBC2_SSP2_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC2 }, + [RESET_SEC_TWSI3] = { APBC2_TWSI3_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC2 }, + [RESET_SEC_RTC] = { APBC2_RTC_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC2 }, + [RESET_SEC_TIMERS0] = { APBC2_TIMERS0_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC2 }, + [RESET_SEC_KPC] = { APBC2_KPC_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC2 }, + [RESET_SEC_GPIO] = { APBC2_GPIO_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC2 }, + }; + +static u32 spacemit_reset_read(struct spacemit_reset *reset, u32 id) +{ + void __iomem *base; + + switch (reset->signals[id].type) { + case RST_BASE_TYPE_APMU: + base = reset->io_base.apmu_base; + break; + case RST_BASE_TYPE_APBC: + base = reset->io_base.apbc_base; + break; + default: + base = reset->io_base.apbc_base; + break; + } + + return readl(base + reset->signals[id].offset); +} + +static void spacemit_reset_write(struct spacemit_reset *reset, u32 value, u32 id) +{ + void __iomem *base; + + switch (reset->signals[id].type) { + case RST_BASE_TYPE_APMU: + base = reset->io_base.apmu_base; + break; + case RST_BASE_TYPE_APBC: + base = reset->io_base.apbc_base; + break; + default: + base = reset->io_base.apbc_base; + break; + } + + writel(value, base + reset->signals[id].offset); +} + +static void spacemit_reset_set(struct reset_ctl *rst, u32 id, bool assert) +{ + u32 value; + struct spacemit_reset *reset = dev_get_priv(rst->dev); + + value = spacemit_reset_read(reset, id); + + if (assert) { + value &= ~reset->signals[id].mask; + value |= reset->signals[id].assert_val; + } else { + value &= ~reset->signals[id].mask; + value |= reset->signals[id].deassert_val; + } + + spacemit_reset_write(reset, value, id); +} + +static int spacemit_reset_update(struct reset_ctl *rst, bool assert) +{ + if (rst->id < RESET_UART1 || rst->id >= RESET_NUMBER) + return 0; + + /* can not write to twsi8 */ + if (rst->id == RESET_TWSI8) + return 0; + + spacemit_reset_set(rst, rst->id, assert); + return 0; +} + +static int spacemit_reset_assert(struct reset_ctl *rst) +{ + return spacemit_reset_update(rst, true); +} + +static int spacemit_reset_deassert(struct reset_ctl *rst) +{ + return spacemit_reset_update(rst, false); +} + +static int spacemit_k1_reset_probe(struct udevice *dev) +{ + struct spacemit_reset *reset = dev_get_priv(dev); + + reset->io_base.mpmu_base = (void *)dev_remap_addr_index(dev, 0); + if (!reset->io_base.mpmu_base) { + pr_err("failed to map mpmu registers\n"); + goto out; + } + + reset->io_base.apmu_base = (void *)dev_remap_addr_index(dev, 1); + if (!reset->io_base.apmu_base) { + pr_err("failed to map apmu registers\n"); + goto out; + } + + reset->io_base.apbc_base = (void *)dev_remap_addr_index(dev, 2); + if (!reset->io_base.apbc_base) { + pr_err("failed to map apbc registers\n"); + goto out; + } + + reset->io_base.apbs_base = (void *)dev_remap_addr_index(dev, 3); + if (!reset->io_base.apbs_base) { + pr_err("failed to map apbs registers\n"); + goto out; + } + + reset->io_base.ciu_base = (void *)dev_remap_addr_index(dev, 4); + if (!reset->io_base.ciu_base) { + pr_err("failed to map ciu registers\n"); + goto out; + } + + reset->io_base.dciu_base = (void *)dev_remap_addr_index(dev, 5); + if (!reset->io_base.dciu_base) { + pr_err("failed to map dragon ciu registers\n"); + goto out; + } + + reset->io_base.ddrc_base = (void *)dev_remap_addr_index(dev, 6); + if (!reset->io_base.ddrc_base) { + pr_err("failed to map ddrc registers\n"); + goto out; + } + + reset->io_base.apbc2_base = (void *)dev_remap_addr_index(dev, 7); + if (!reset->io_base.apbc2_base) { + pr_err("failed to map apbc2 registers\n"); + goto out; + } + + reset->signals = k1_reset_signals; + +out: + return 0; +} + +const struct reset_ops k1_reset_ops = { + .rst_assert = spacemit_reset_assert, + .rst_deassert = spacemit_reset_deassert, +}; + +static const struct udevice_id k1_reset_ids[] = { + { .compatible = "spacemit,k1-reset", }, + {}, +}; + +U_BOOT_DRIVER(k1_reset) = { + .name = "spacemit,k1-reset", + .id = UCLASS_RESET, + .ops = &k1_reset_ops, + .of_match = k1_reset_ids, + .probe = spacemit_k1_reset_probe, + .priv_auto = sizeof(struct spacemit_reset), +}; diff --git a/drivers/rng/msm_rng.c b/drivers/rng/msm_rng.c index f790d3b60f9..aab602c5ed0 100644 --- a/drivers/rng/msm_rng.c +++ b/drivers/rng/msm_rng.c @@ -44,6 +44,11 @@ static int msm_rng_read(struct udevice *dev, void *data, size_t len) u32 *retdata = data; size_t maxsize; u32 val; + int ret; + + ret = clk_enable(&priv->clk); + if (ret < 0) + return ret; /* calculate max size bytes to transfer back to caller */ maxsize = min_t(size_t, MAX_HW_FIFO_SIZE, len); @@ -66,6 +71,8 @@ static int msm_rng_read(struct udevice *dev, void *data, size_t len) break; } while (currsize < maxsize); + clk_disable(&priv->clk); + return 0; } @@ -76,7 +83,7 @@ static int msm_rng_enable(struct msm_rng_priv *priv, int enable) if (enable) { /* Enable PRNG only if it is not already enabled */ val = readl_relaxed(priv->base + PRNG_CONFIG); - if (val & PRNG_CONFIG_HW_ENABLE) { + if (!(val & PRNG_CONFIG_HW_ENABLE)) { val = readl_relaxed(priv->base + PRNG_LFSR_CFG); val &= ~PRNG_LFSR_CFG_MASK; val |= PRNG_LFSR_CFG_CLOCKS; @@ -118,7 +125,9 @@ static int msm_rng_probe(struct udevice *dev) if (ret < 0) return ret; - return msm_rng_enable(priv, 1); + ret = msm_rng_enable(priv, 1); + clk_disable(&priv->clk); + return ret; } static int msm_rng_remove(struct udevice *dev) diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index c4f4a8d78df..84130524c2d 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -789,6 +789,12 @@ config SPL_SYS_NS16550_SERIAL default y if SYS_NS16550_SERIAL || ARCH_SUNXI || ARCH_OMAP2PLUS select SYS_NS16550 +config TPL_SYS_NS16550_SERIAL + bool "NS16550 UART or compatible legacy driver in TPL" + depends on TPL && !TPL_DM_SERIAL + default y if SPL_SYS_NS16550_SERIAL + select SYS_NS16550 + config SYS_NS16550 bool "NS16550 UART or compatible" help diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c index c5fd740be4d..28f4435d01d 100644 --- a/drivers/serial/serial_mxc.c +++ b/drivers/serial/serial_mxc.c @@ -3,6 +3,7 @@ * (c) 2007 Sascha Hauer <s.hauer@pengutronix.de> */ +#include <clk.h> #include <dm.h> #include <errno.h> #include <watchdog.h> @@ -312,7 +313,17 @@ int mxc_serial_setbrg(struct udevice *dev, int baudrate) static int mxc_serial_probe(struct udevice *dev) { struct mxc_serial_plat *plat = dev_get_plat(dev); +#if CONFIG_IS_ENABLED(CLK_CCF) + int ret; + ret = clk_get_bulk(dev, &plat->clks); + if (ret) + return ret; + + ret = clk_enable_bulk(&plat->clks); + if (ret) + return ret; +#endif _mxc_serial_init(plat->reg, plat->use_dte); return 0; diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig index 121194e4418..475540ffac7 100644 --- a/drivers/sysreset/Kconfig +++ b/drivers/sysreset/Kconfig @@ -242,7 +242,6 @@ config SYSRESET_RAA215300 config SYSRESET_QCOM_PSHOLD bool "Support sysreset for Qualcomm SoCs via PSHOLD" - depends on ARCH_IPQ40XX help Add support for the system reboot on Qualcomm SoCs via PSHOLD. diff --git a/drivers/ufs/ufs.c b/drivers/ufs/ufs.c index f7d8c40c448..91f6ad3bfef 100644 --- a/drivers/ufs/ufs.c +++ b/drivers/ufs/ufs.c @@ -19,6 +19,7 @@ #include <malloc.h> #include <hexdump.h> #include <scsi.h> +#include <ufs.h> #include <asm/io.h> #include <asm/dma-mapping.h> #include <linux/bitops.h> @@ -313,16 +314,12 @@ static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer) ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), &tx_lanes); for (i = 0; i < tx_lanes; i++) { + unsigned int val = UIC_ARG_MIB_SEL(TX_LCC_ENABLE, + UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)); if (!peer) - err = ufshcd_dme_set(hba, - UIC_ARG_MIB_SEL(TX_LCC_ENABLE, - UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)), - 0); + err = ufshcd_dme_set(hba, val, 0); else - err = ufshcd_dme_peer_set(hba, - UIC_ARG_MIB_SEL(TX_LCC_ENABLE, - UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)), - 0); + err = ufshcd_dme_peer_set(hba, val, 0); if (err) { dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d\n", __func__, peer, i, err); @@ -1034,8 +1031,8 @@ static inline void ufshcd_init_query(struct ufs_hba *hba, /** * ufshcd_query_flag() - API function for sending flag query requests */ -int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode, - enum flag_idn idn, bool *flag_res) +static int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode, + enum flag_idn idn, bool *flag_res) { struct ufs_query_req *request = NULL; struct ufs_query_res *response = NULL; @@ -1170,9 +1167,9 @@ out: /** * ufshcd_query_descriptor_retry - API function for sending descriptor requests */ -int ufshcd_query_descriptor_retry(struct ufs_hba *hba, enum query_opcode opcode, - enum desc_idn idn, u8 index, u8 selector, - u8 *desc_buf, int *buf_len) +static int ufshcd_query_descriptor_retry(struct ufs_hba *hba, enum query_opcode opcode, + enum desc_idn idn, u8 index, u8 selector, + u8 *desc_buf, int *buf_len) { int err; int retries; @@ -1264,8 +1261,8 @@ static void ufshcd_init_desc_sizes(struct ufs_hba *hba) * ufshcd_map_desc_id_to_length - map descriptor IDN to its length * */ -int ufshcd_map_desc_id_to_length(struct ufs_hba *hba, enum desc_idn desc_id, - int *desc_len) +static int ufshcd_map_desc_id_to_length(struct ufs_hba *hba, enum desc_idn desc_id, + int *desc_len) { switch (desc_id) { case QUERY_DESC_IDN_DEVICE: @@ -1302,15 +1299,14 @@ int ufshcd_map_desc_id_to_length(struct ufs_hba *hba, enum desc_idn desc_id, } return 0; } -EXPORT_SYMBOL(ufshcd_map_desc_id_to_length); /** * ufshcd_read_desc_param - read the specified descriptor parameter * */ -int ufshcd_read_desc_param(struct ufs_hba *hba, enum desc_idn desc_id, - int desc_index, u8 param_offset, u8 *param_read_buf, - u8 param_size) +static int ufshcd_read_desc_param(struct ufs_hba *hba, enum desc_idn desc_id, + int desc_index, u8 param_offset, + u8 *param_read_buf, u8 param_size) { int ret; u8 *desc_buf; @@ -1569,8 +1565,8 @@ static int ufshcd_read_device_desc(struct ufs_hba *hba, u8 *buf, u32 size) * ufshcd_read_string_desc - read string descriptor * */ -int ufshcd_read_string_desc(struct ufs_hba *hba, int desc_index, - u8 *buf, u32 size, bool ascii) +static int ufshcd_read_string_desc(struct ufs_hba *hba, int desc_index, + u8 *buf, u32 size, bool ascii) { int err = 0; @@ -1881,7 +1877,7 @@ static void ufshcd_def_desc_sizes(struct ufs_hba *hba) hba->desc_size.hlth_desc = QUERY_DESC_HEALTH_DEF_SIZE; } -int ufs_start(struct ufs_hba *hba) +static int ufs_start(struct ufs_hba *hba) { struct ufs_dev_desc card = {0}; int ret; @@ -1962,7 +1958,7 @@ int ufshcd_probe(struct udevice *ufs_dev, struct ufs_hba_ops *hba_ops) ufshcd_ops_init(hba); - /* Read capabilties registers */ + /* Read capabilities registers */ hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES); if (hba->quirks & UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS) hba->capabilities &= ~MASK_64_ADDRESSING_SUPPORT; @@ -2001,7 +1997,7 @@ int ufshcd_probe(struct udevice *ufs_dev, struct ufs_hba_ops *hba_ops) REG_INTERRUPT_STATUS); ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE); - mb(); + mb(); /* flush previous writes */ /* Reset the attached device */ ufshcd_device_reset(hba); diff --git a/drivers/ufs/ufs.h b/drivers/ufs/ufs.h index 00ecca350c3..53137fae3a8 100644 --- a/drivers/ufs/ufs.h +++ b/drivers/ufs/ufs.h @@ -4,6 +4,7 @@ #include <linux/types.h> #include <asm/io.h> +#include "ufshci.h" #include "unipro.h" struct udevice; @@ -14,11 +15,6 @@ struct udevice; #define RESPONSE_UPIU_SENSE_DATA_LENGTH 18 #define UFS_MAX_LUNS 0x7F -enum { - TASK_REQ_UPIU_SIZE_DWORDS = 8, - TASK_RSP_UPIU_SIZE_DWORDS = 8, - ALIGNED_UPIU_SIZE = 512, -}; /* UFS device power modes */ enum ufs_dev_pwr_mode { @@ -84,44 +80,6 @@ enum { /* Offset of the response code in the UPIU header */ #define UPIU_RSP_CODE_OFFSET 8 -/* To accommodate UFS2.0 required Command type */ -enum { - UTP_CMD_TYPE_UFS_STORAGE = 0x1, -}; - -enum { - UTP_SCSI_COMMAND = 0x00000000, - UTP_NATIVE_UFS_COMMAND = 0x10000000, - UTP_DEVICE_MANAGEMENT_FUNCTION = 0x20000000, - UTP_REQ_DESC_INT_CMD = 0x01000000, -}; - -/* UTP Transfer Request Data Direction (DD) */ -enum { - UTP_NO_DATA_TRANSFER = 0x00000000, - UTP_HOST_TO_DEVICE = 0x02000000, - UTP_DEVICE_TO_HOST = 0x04000000, -}; - -/* Overall command status values */ -enum { - OCS_SUCCESS = 0x0, - OCS_INVALID_CMD_TABLE_ATTR = 0x1, - OCS_INVALID_PRDT_ATTR = 0x2, - OCS_MISMATCH_DATA_BUF_SIZE = 0x3, - OCS_MISMATCH_RESP_UPIU_SIZE = 0x4, - OCS_PEER_COMM_FAILURE = 0x5, - OCS_ABORTED = 0x6, - OCS_FATAL_ERROR = 0x7, - OCS_INVALID_COMMAND_STATUS = 0x0F, - MASK_OCS = 0x0F, -}; - -/* The maximum length of the data byte count field in the PRDT is 256KB */ -#define PRDT_DATA_BYTE_COUNT_MAX (256 * 1024) -/* The granularity of the data byte count field in the PRDT is 32-bit */ -#define PRDT_DATA_BYTE_COUNT_PAD 4 - #define GENERAL_UPIU_REQUEST_SIZE (sizeof(struct utp_upiu_req)) #define QUERY_DESC_MAX_SIZE 255 #define QUERY_DESC_MIN_SIZE 2 @@ -130,8 +88,8 @@ enum { (sizeof(struct utp_upiu_header))) #define RESPONSE_UPIU_SENSE_DATA_LENGTH 18 #define UPIU_HEADER_DWORD(byte3, byte2, byte1, byte0)\ - cpu_to_be32((byte3 << 24) | (byte2 << 16) |\ - (byte1 << 8) | (byte0)) + cpu_to_be32(((byte3) << 24) | ((byte2) << 16) |\ + ((byte1) << 8) | (byte0)) /* * UFS Protocol Information Unit related definitions */ @@ -297,79 +255,6 @@ enum desc_header_offset { QUERY_DESC_DESC_TYPE_OFFSET = 0x01, }; -struct ufshcd_sg_entry { - __le32 base_addr; - __le32 upper_addr; - __le32 reserved; - __le32 size; -}; - -#define MAX_BUFF 128 -/** - * struct utp_transfer_cmd_desc - UFS Command Descriptor structure - * @command_upiu: Command UPIU Frame address - * @response_upiu: Response UPIU Frame address - * @prd_table: Physical Region Descriptor - */ -struct utp_transfer_cmd_desc { - u8 command_upiu[ALIGNED_UPIU_SIZE]; - u8 response_upiu[ALIGNED_UPIU_SIZE]; - struct ufshcd_sg_entry prd_table[MAX_BUFF]; -}; - -/** - * struct request_desc_header - Descriptor Header common to both UTRD and UTMRD - * @dword0: Descriptor Header DW0 - * @dword1: Descriptor Header DW1 - * @dword2: Descriptor Header DW2 - * @dword3: Descriptor Header DW3 - */ -struct request_desc_header { - __le32 dword_0; - __le32 dword_1; - __le32 dword_2; - __le32 dword_3; -}; - -/** - * struct utp_transfer_req_desc - UTRD structure - * @header: UTRD header DW-0 to DW-3 - * @command_desc_base_addr_lo: UCD base address low DW-4 - * @command_desc_base_addr_hi: UCD base address high DW-5 - * @response_upiu_length: response UPIU length DW-6 - * @response_upiu_offset: response UPIU offset DW-6 - * @prd_table_length: Physical region descriptor length DW-7 - * @prd_table_offset: Physical region descriptor offset DW-7 - */ -struct utp_transfer_req_desc { - /* DW 0-3 */ - struct request_desc_header header; - - /* DW 4-5*/ - __le32 command_desc_base_addr_lo; - __le32 command_desc_base_addr_hi; - - /* DW 6 */ - __le16 response_upiu_length; - __le16 response_upiu_offset; - - /* DW 7 */ - __le16 prd_table_length; - __le16 prd_table_offset; -}; - -/** - * struct utp_upiu_header - UPIU header structure - * @dword_0: UPIU header DW-0 - * @dword_1: UPIU header DW-1 - * @dword_2: UPIU header DW-2 - */ -struct utp_upiu_header { - __be32 dword_0; - __be32 dword_1; - __be32 dword_2; -}; - /** * struct utp_upiu_query - upiu request buffer structure for * query request. @@ -403,27 +288,6 @@ struct utp_upiu_cmd { u8 cdb[UFS_CDB_SIZE]; }; -/* - * UTMRD structure. - */ -struct utp_task_req_desc { - /* DW 0-3 */ - struct request_desc_header header; - - /* DW 4-11 - Task request UPIU structure */ - struct utp_upiu_header req_header; - __be32 input_param1; - __be32 input_param2; - __be32 input_param3; - __be32 __reserved1[2]; - - /* DW 12-19 - Task Management Response UPIU structure */ - struct utp_upiu_header rsp_header; - __be32 output_param1; - __be32 output_param2; - __be32 __reserved2[3]; -}; - /** * struct utp_upiu_req - general upiu request structure * @header:UPIU header structure DW-0 to DW-2 @@ -551,63 +415,6 @@ struct uic_command { int result; }; -/* GenSelectorIndex calculation macros for M-PHY attributes */ -#define UIC_ARG_MPHY_TX_GEN_SEL_INDEX(lane) (lane) -#define UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane) (PA_MAXDATALANES + (lane)) - -#define UIC_ARG_MIB_SEL(attr, sel) ((((attr) & 0xFFFF) << 16) |\ - ((sel) & 0xFFFF)) -#define UIC_ARG_MIB(attr) UIC_ARG_MIB_SEL(attr, 0) -#define UIC_ARG_ATTR_TYPE(t) (((t) & 0xFF) << 16) -#define UIC_GET_ATTR_ID(v) (((v) >> 16) & 0xFFFF) - -/* Link Status*/ -enum link_status { - UFSHCD_LINK_IS_DOWN = 1, - UFSHCD_LINK_IS_UP = 2, -}; - -#define UIC_ARG_MIB_SEL(attr, sel) ((((attr) & 0xFFFF) << 16) |\ - ((sel) & 0xFFFF)) -#define UIC_ARG_MIB(attr) UIC_ARG_MIB_SEL(attr, 0) -#define UIC_ARG_ATTR_TYPE(t) (((t) & 0xFF) << 16) -#define UIC_GET_ATTR_ID(v) (((v) >> 16) & 0xFFFF) - -/* UIC Commands */ -enum uic_cmd_dme { - UIC_CMD_DME_GET = 0x01, - UIC_CMD_DME_SET = 0x02, - UIC_CMD_DME_PEER_GET = 0x03, - UIC_CMD_DME_PEER_SET = 0x04, - UIC_CMD_DME_POWERON = 0x10, - UIC_CMD_DME_POWEROFF = 0x11, - UIC_CMD_DME_ENABLE = 0x12, - UIC_CMD_DME_RESET = 0x14, - UIC_CMD_DME_END_PT_RST = 0x15, - UIC_CMD_DME_LINK_STARTUP = 0x16, - UIC_CMD_DME_HIBER_ENTER = 0x17, - UIC_CMD_DME_HIBER_EXIT = 0x18, - UIC_CMD_DME_TEST_MODE = 0x1A, -}; - -/* UIC Config result code / Generic error code */ -enum { - UIC_CMD_RESULT_SUCCESS = 0x00, - UIC_CMD_RESULT_INVALID_ATTR = 0x01, - UIC_CMD_RESULT_FAILURE = 0x01, - UIC_CMD_RESULT_INVALID_ATTR_VALUE = 0x02, - UIC_CMD_RESULT_READ_ONLY_ATTR = 0x03, - UIC_CMD_RESULT_WRITE_ONLY_ATTR = 0x04, - UIC_CMD_RESULT_BAD_INDEX = 0x05, - UIC_CMD_RESULT_LOCKED_ATTR = 0x06, - UIC_CMD_RESULT_BAD_TEST_FEATURE_INDEX = 0x07, - UIC_CMD_RESULT_PEER_COMM_FAILURE = 0x08, - UIC_CMD_RESULT_BUSY = 0x09, - UIC_CMD_RESULT_DME_FAILURE = 0x0A, -}; - -#define MASK_UIC_COMMAND_RESULT 0xFF - /* Host <-> Device UniPro Link state */ enum uic_link_state { UIC_LINK_OFF_STATE = 0, /* Link powered down or disabled */ @@ -915,7 +722,7 @@ static inline int ufshcd_ops_get_max_pwr_mode(struct ufs_hba *hba, } static inline int ufshcd_ops_hce_enable_notify(struct ufs_hba *hba, - bool status) + bool status) { if (hba->ops && hba->ops->hce_enable_notify) return hba->ops->hce_enable_notify(hba, status); @@ -940,17 +747,6 @@ static inline int ufshcd_vops_device_reset(struct ufs_hba *hba) return 0; } -/* Controller UFSHCI version */ -enum { - UFSHCI_VERSION_10 = 0x00010000, /* 1.0 */ - UFSHCI_VERSION_11 = 0x00010100, /* 1.1 */ - UFSHCI_VERSION_20 = 0x00000200, /* 2.0 */ - UFSHCI_VERSION_21 = 0x00000210, /* 2.1 */ - UFSHCI_VERSION_30 = 0x00000300, /* 3.0 */ - UFSHCI_VERSION_31 = 0x00000310, /* 3.1 */ - UFSHCI_VERSION_40 = 0x00000400, /* 4.0 */ -}; - /* Interrupt disable masks */ enum { /* Interrupt disable mask for UFSHCI v1.0 */ @@ -964,123 +760,6 @@ enum { INTERRUPT_MASK_ALL_VER_21 = 0x71FFF, }; -/* UFSHCI Registers */ -enum { - REG_CONTROLLER_CAPABILITIES = 0x00, - REG_UFS_VERSION = 0x08, - REG_CONTROLLER_DEV_ID = 0x10, - REG_CONTROLLER_PROD_ID = 0x14, - REG_AUTO_HIBERNATE_IDLE_TIMER = 0x18, - REG_INTERRUPT_STATUS = 0x20, - REG_INTERRUPT_ENABLE = 0x24, - REG_CONTROLLER_STATUS = 0x30, - REG_CONTROLLER_ENABLE = 0x34, - REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER = 0x38, - REG_UIC_ERROR_CODE_DATA_LINK_LAYER = 0x3C, - REG_UIC_ERROR_CODE_NETWORK_LAYER = 0x40, - REG_UIC_ERROR_CODE_TRANSPORT_LAYER = 0x44, - REG_UIC_ERROR_CODE_DME = 0x48, - REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL = 0x4C, - REG_UTP_TRANSFER_REQ_LIST_BASE_L = 0x50, - REG_UTP_TRANSFER_REQ_LIST_BASE_H = 0x54, - REG_UTP_TRANSFER_REQ_DOOR_BELL = 0x58, - REG_UTP_TRANSFER_REQ_LIST_CLEAR = 0x5C, - REG_UTP_TRANSFER_REQ_LIST_RUN_STOP = 0x60, - REG_UTP_TASK_REQ_LIST_BASE_L = 0x70, - REG_UTP_TASK_REQ_LIST_BASE_H = 0x74, - REG_UTP_TASK_REQ_DOOR_BELL = 0x78, - REG_UTP_TASK_REQ_LIST_CLEAR = 0x7C, - REG_UTP_TASK_REQ_LIST_RUN_STOP = 0x80, - REG_UIC_COMMAND = 0x90, - REG_UIC_COMMAND_ARG_1 = 0x94, - REG_UIC_COMMAND_ARG_2 = 0x98, - REG_UIC_COMMAND_ARG_3 = 0x9C, - - UFSHCI_REG_SPACE_SIZE = 0xA0, - - REG_UFS_CCAP = 0x100, - REG_UFS_CRYPTOCAP = 0x104, - - UFSHCI_CRYPTO_REG_SPACE_SIZE = 0x400, -}; - -/* Controller capability masks */ -enum { - MASK_TRANSFER_REQUESTS_SLOTS = 0x0000001F, - MASK_TASK_MANAGEMENT_REQUEST_SLOTS = 0x00070000, - MASK_AUTO_HIBERN8_SUPPORT = 0x00800000, - MASK_64_ADDRESSING_SUPPORT = 0x01000000, - MASK_OUT_OF_ORDER_DATA_DELIVERY_SUPPORT = 0x02000000, - MASK_UIC_DME_TEST_MODE_SUPPORT = 0x04000000, -}; - -/* Interrupt Status 20h */ -#define UTP_TRANSFER_REQ_COMPL 0x1 -#define UIC_DME_END_PT_RESET 0x2 -#define UIC_ERROR 0x4 -#define UIC_TEST_MODE 0x8 -#define UIC_POWER_MODE 0x10 -#define UIC_HIBERNATE_EXIT 0x20 -#define UIC_HIBERNATE_ENTER 0x40 -#define UIC_LINK_LOST 0x80 -#define UIC_LINK_STARTUP 0x100 -#define UTP_TASK_REQ_COMPL 0x200 -#define UIC_COMMAND_COMPL 0x400 -#define DEVICE_FATAL_ERROR 0x800 -#define CONTROLLER_FATAL_ERROR 0x10000 -#define SYSTEM_BUS_FATAL_ERROR 0x20000 - -#define UFSHCD_UIC_PWR_MASK (UIC_HIBERNATE_ENTER |\ - UIC_HIBERNATE_EXIT |\ - UIC_POWER_MODE) - -#define UFSHCD_UIC_MASK (UIC_COMMAND_COMPL | UIC_POWER_MODE) - -#define UFSHCD_ERROR_MASK (UIC_ERROR |\ - DEVICE_FATAL_ERROR |\ - CONTROLLER_FATAL_ERROR |\ - SYSTEM_BUS_FATAL_ERROR) - -#define INT_FATAL_ERRORS (DEVICE_FATAL_ERROR |\ - CONTROLLER_FATAL_ERROR |\ - SYSTEM_BUS_FATAL_ERROR) - -/* Host Controller Enable 0x34h */ -#define CONTROLLER_ENABLE 0x1 -#define CONTROLLER_DISABLE 0x0 -/* HCS - Host Controller Status 30h */ -#define DEVICE_PRESENT 0x1 -#define UTP_TRANSFER_REQ_LIST_READY 0x2 -#define UTP_TASK_REQ_LIST_READY 0x4 -#define UIC_COMMAND_READY 0x8 -#define HOST_ERROR_INDICATOR 0x10 -#define DEVICE_ERROR_INDICATOR 0x20 -#define UIC_POWER_MODE_CHANGE_REQ_STATUS_MASK UFS_MASK(0x7, 8) - -#define UFSHCD_STATUS_READY (UTP_TRANSFER_REQ_LIST_READY |\ - UTP_TASK_REQ_LIST_READY |\ - UIC_COMMAND_READY) - -enum { - PWR_OK = 0x0, - PWR_LOCAL = 0x01, - PWR_REMOTE = 0x02, - PWR_BUSY = 0x03, - PWR_ERROR_CAP = 0x04, - PWR_FATAL_ERROR = 0x05, -}; - -/* UICCMD - UIC Command */ -#define COMMAND_OPCODE_MASK 0xFF -#define GEN_SELECTOR_INDEX_MASK 0xFFFF - -#define MIB_ATTRIBUTE_MASK UFS_MASK(0xFFFF, 16) -#define RESET_LEVEL 0xFF - -#define ATTR_SET_TYPE_MASK UFS_MASK(0xFF, 16) -#define CFG_RESULT_CODE_MASK 0xFF -#define GENERIC_ERROR_CODE_MASK 0xFF - #define ufshcd_writel(hba, val, reg) \ writel((val), (hba)->mmio_base + (reg)) #define ufshcd_readl(hba, reg) \ @@ -1103,12 +782,6 @@ static inline void ufshcd_rmwl(struct ufs_hba *hba, u32 mask, u32 val, u32 reg) ufshcd_writel(hba, tmp, reg); } -/* UTRLRSR - UTP Transfer Request Run-Stop Register 60h */ -#define UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT 0x1 - -/* UTMRLRSR - UTP Task Management Request Run-Stop Register 80h */ -#define UTP_TASK_REQ_LIST_RUN_STOP_BIT 0x1 - int ufshcd_probe(struct udevice *dev, struct ufs_hba_ops *hba_ops); #endif diff --git a/drivers/ufs/ufshci.h b/drivers/ufs/ufshci.h new file mode 100644 index 00000000000..90cbf87a3a4 --- /dev/null +++ b/drivers/ufs/ufshci.h @@ -0,0 +1,469 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +#ifndef __UFSHCI_H +#define __UFSHCI_H + +enum { + TASK_REQ_UPIU_SIZE_DWORDS = 8, + TASK_RSP_UPIU_SIZE_DWORDS = 8, + ALIGNED_UPIU_SIZE = 512, +}; + +/* UFSHCI Registers */ +enum { + REG_CONTROLLER_CAPABILITIES = 0x00, + REG_MCQCAP = 0x04, + REG_UFS_VERSION = 0x08, + REG_EXT_CONTROLLER_CAPABILITIES = 0x0C, + REG_CONTROLLER_PID = 0x10, + REG_CONTROLLER_MID = 0x14, + REG_AUTO_HIBERNATE_IDLE_TIMER = 0x18, + REG_INTERRUPT_STATUS = 0x20, + REG_INTERRUPT_ENABLE = 0x24, + REG_CONTROLLER_STATUS = 0x30, + REG_CONTROLLER_ENABLE = 0x34, + REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER = 0x38, + REG_UIC_ERROR_CODE_DATA_LINK_LAYER = 0x3C, + REG_UIC_ERROR_CODE_NETWORK_LAYER = 0x40, + REG_UIC_ERROR_CODE_TRANSPORT_LAYER = 0x44, + REG_UIC_ERROR_CODE_DME = 0x48, + REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL = 0x4C, + REG_UTP_TRANSFER_REQ_LIST_BASE_L = 0x50, + REG_UTP_TRANSFER_REQ_LIST_BASE_H = 0x54, + REG_UTP_TRANSFER_REQ_DOOR_BELL = 0x58, + REG_UTP_TRANSFER_REQ_LIST_CLEAR = 0x5C, + REG_UTP_TRANSFER_REQ_LIST_RUN_STOP = 0x60, + REG_UTP_TASK_REQ_LIST_BASE_L = 0x70, + REG_UTP_TASK_REQ_LIST_BASE_H = 0x74, + REG_UTP_TASK_REQ_DOOR_BELL = 0x78, + REG_UTP_TASK_REQ_LIST_CLEAR = 0x7C, + REG_UTP_TASK_REQ_LIST_RUN_STOP = 0x80, + REG_UIC_COMMAND = 0x90, + REG_UIC_COMMAND_ARG_1 = 0x94, + REG_UIC_COMMAND_ARG_2 = 0x98, + REG_UIC_COMMAND_ARG_3 = 0x9C, + + UFSHCI_REG_SPACE_SIZE = 0xA0, + + REG_UFS_CCAP = 0x100, + REG_UFS_CRYPTOCAP = 0x104, + + REG_UFS_MEM_CFG = 0x300, + REG_UFS_MCQ_CFG = 0x380, + REG_UFS_ESILBA = 0x384, + REG_UFS_ESIUBA = 0x388, + UFSHCI_CRYPTO_REG_SPACE_SIZE = 0x400, +}; + +/* Controller capability masks */ +enum { + MASK_TRANSFER_REQUESTS_SLOTS_SDB = 0x0000001F, + MASK_TRANSFER_REQUESTS_SLOTS_MCQ = 0x000000FF, + MASK_NUMBER_OUTSTANDING_RTT = 0x0000FF00, + MASK_TASK_MANAGEMENT_REQUEST_SLOTS = 0x00070000, + MASK_EHSLUTRD_SUPPORTED = 0x00400000, + MASK_AUTO_HIBERN8_SUPPORT = 0x00800000, + MASK_64_ADDRESSING_SUPPORT = 0x01000000, + MASK_OUT_OF_ORDER_DATA_DELIVERY_SUPPORT = 0x02000000, + MASK_UIC_DME_TEST_MODE_SUPPORT = 0x04000000, + MASK_CRYPTO_SUPPORT = 0x10000000, + MASK_LSDB_SUPPORT = 0x20000000, + MASK_MCQ_SUPPORT = 0x40000000, +}; + +/* MCQ capability mask */ +enum { + MASK_EXT_IID_SUPPORT = 0x00000400, +}; + +enum { + REG_SQATTR = 0x0, + REG_SQLBA = 0x4, + REG_SQUBA = 0x8, + REG_SQDAO = 0xC, + REG_SQISAO = 0x10, + + REG_CQATTR = 0x20, + REG_CQLBA = 0x24, + REG_CQUBA = 0x28, + REG_CQDAO = 0x2C, + REG_CQISAO = 0x30, +}; + +enum { + REG_SQHP = 0x0, + REG_SQTP = 0x4, + REG_SQRTC = 0x8, + REG_SQCTI = 0xC, + REG_SQRTS = 0x10, +}; + +enum { + REG_CQHP = 0x0, + REG_CQTP = 0x4, +}; + +enum { + REG_CQIS = 0x0, + REG_CQIE = 0x4, +}; + +enum { + SQ_START = 0x0, + SQ_STOP = 0x1, + SQ_ICU = 0x2, +}; + +enum { + SQ_STS = 0x1, + SQ_CUS = 0x2, +}; + +#define SQ_ICU_ERR_CODE_MASK GENMASK(7, 4) +#define UFS_MASK(mask, offset) ((mask) << (offset)) + +/* UFS Version 08h */ +#define MINOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 0) +#define MAJOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 16) + +/* Controller UFSHCI version */ +enum { + UFSHCI_VERSION_10 = 0x00010000, /* 1.0 */ + UFSHCI_VERSION_11 = 0x00010100, /* 1.1 */ + UFSHCI_VERSION_20 = 0x00000200, /* 2.0 */ + UFSHCI_VERSION_21 = 0x00000210, /* 2.1 */ + UFSHCI_VERSION_30 = 0x00000300, /* 3.0 */ + UFSHCI_VERSION_31 = 0x00000310, /* 3.1 */ + UFSHCI_VERSION_40 = 0x00000400, /* 4.0 */ +}; + +/* + * IS - Interrupt Status - 20h + */ +#define UTP_TRANSFER_REQ_COMPL 0x1 +#define UIC_DME_END_PT_RESET 0x2 +#define UIC_ERROR 0x4 +#define UIC_TEST_MODE 0x8 +#define UIC_POWER_MODE 0x10 +#define UIC_HIBERNATE_EXIT 0x20 +#define UIC_HIBERNATE_ENTER 0x40 +#define UIC_LINK_LOST 0x80 +#define UIC_LINK_STARTUP 0x100 +#define UTP_TASK_REQ_COMPL 0x200 +#define UIC_COMMAND_COMPL 0x400 +#define DEVICE_FATAL_ERROR 0x800 +#define CONTROLLER_FATAL_ERROR 0x10000 +#define SYSTEM_BUS_FATAL_ERROR 0x20000 +#define CRYPTO_ENGINE_FATAL_ERROR 0x40000 +#define MCQ_CQ_EVENT_STATUS 0x100000 + +#define UFSHCD_UIC_HIBERN8_MASK (UIC_HIBERNATE_ENTER |\ + UIC_HIBERNATE_EXIT) + +#define UFSHCD_UIC_PWR_MASK (UFSHCD_UIC_HIBERN8_MASK |\ + UIC_POWER_MODE) + +#define UFSHCD_UIC_MASK (UIC_COMMAND_COMPL | UFSHCD_UIC_PWR_MASK) + +#define UFSHCD_ERROR_MASK (UIC_ERROR | INT_FATAL_ERRORS) + +#define INT_FATAL_ERRORS (DEVICE_FATAL_ERROR |\ + CONTROLLER_FATAL_ERROR |\ + SYSTEM_BUS_FATAL_ERROR |\ + CRYPTO_ENGINE_FATAL_ERROR |\ + UIC_LINK_LOST) + +/* HCS - Host Controller Status 30h */ +#define DEVICE_PRESENT 0x1 +#define UTP_TRANSFER_REQ_LIST_READY 0x2 +#define UTP_TASK_REQ_LIST_READY 0x4 +#define UIC_COMMAND_READY 0x8 +#define HOST_ERROR_INDICATOR 0x10 +#define DEVICE_ERROR_INDICATOR 0x20 +#define UIC_POWER_MODE_CHANGE_REQ_STATUS_MASK UFS_MASK(0x7, 8) + +#define UFSHCD_STATUS_READY (UTP_TRANSFER_REQ_LIST_READY |\ + UTP_TASK_REQ_LIST_READY |\ + UIC_COMMAND_READY) + +enum { + PWR_OK = 0x0, + PWR_LOCAL = 0x01, + PWR_REMOTE = 0x02, + PWR_BUSY = 0x03, + PWR_ERROR_CAP = 0x04, + PWR_FATAL_ERROR = 0x05, +}; + +/* HCE - Host Controller Enable 34h */ +#define CONTROLLER_ENABLE 0x1 +#define CONTROLLER_DISABLE 0x0 +#define CRYPTO_GENERAL_ENABLE 0x2 + +/* UECPA - Host UIC Error Code PHY Adapter Layer 38h */ +#define UIC_PHY_ADAPTER_LAYER_ERROR 0x80000000 +#define UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK 0x1F +#define UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK 0xF +#define UIC_PHY_ADAPTER_LAYER_GENERIC_ERROR 0x10 + +/* UECDL - Host UIC Error Code Data Link Layer 3Ch */ +#define UIC_DATA_LINK_LAYER_ERROR 0x80000000 +#define UIC_DATA_LINK_LAYER_ERROR_CODE_MASK 0xFFFF +#define UIC_DATA_LINK_LAYER_ERROR_TCX_REP_TIMER_EXP 0x2 +#define UIC_DATA_LINK_LAYER_ERROR_AFCX_REQ_TIMER_EXP 0x4 +#define UIC_DATA_LINK_LAYER_ERROR_FCX_PRO_TIMER_EXP 0x8 +#define UIC_DATA_LINK_LAYER_ERROR_RX_BUF_OF 0x20 +#define UIC_DATA_LINK_LAYER_ERROR_PA_INIT 0x2000 +#define UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED 0x0001 +#define UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT 0x0002 + +/* UECN - Host UIC Error Code Network Layer 40h */ +#define UIC_NETWORK_LAYER_ERROR 0x80000000 +#define UIC_NETWORK_LAYER_ERROR_CODE_MASK 0x7 +#define UIC_NETWORK_UNSUPPORTED_HEADER_TYPE 0x1 +#define UIC_NETWORK_BAD_DEVICEID_ENC 0x2 +#define UIC_NETWORK_LHDR_TRAP_PACKET_DROPPING 0x4 + +/* UECT - Host UIC Error Code Transport Layer 44h */ +#define UIC_TRANSPORT_LAYER_ERROR 0x80000000 +#define UIC_TRANSPORT_LAYER_ERROR_CODE_MASK 0x7F +#define UIC_TRANSPORT_UNSUPPORTED_HEADER_TYPE 0x1 +#define UIC_TRANSPORT_UNKNOWN_CPORTID 0x2 +#define UIC_TRANSPORT_NO_CONNECTION_RX 0x4 +#define UIC_TRANSPORT_CONTROLLED_SEGMENT_DROPPING 0x8 +#define UIC_TRANSPORT_BAD_TC 0x10 +#define UIC_TRANSPORT_E2E_CREDIT_OVERFOW 0x20 +#define UIC_TRANSPORT_SAFETY_VALUE_DROPPING 0x40 + +/* UECDME - Host UIC Error Code DME 48h */ +#define UIC_DME_ERROR 0x80000000 +#define UIC_DME_ERROR_CODE_MASK 0x1 + +/* UTRIACR - Interrupt Aggregation control register - 0x4Ch */ +#define INT_AGGR_TIMEOUT_VAL_MASK 0xFF +#define INT_AGGR_COUNTER_THRESHOLD_MASK UFS_MASK(0x1F, 8) +#define INT_AGGR_COUNTER_AND_TIMER_RESET 0x10000 +#define INT_AGGR_STATUS_BIT 0x100000 +#define INT_AGGR_PARAM_WRITE 0x1000000 +#define INT_AGGR_ENABLE 0x80000000 + +/* UTRLRSR - UTP Transfer Request Run-Stop Register 60h */ +#define UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT 0x1 + +/* UTMRLRSR - UTP Task Management Request Run-Stop Register 80h */ +#define UTP_TASK_REQ_LIST_RUN_STOP_BIT 0x1 + +/* REG_UFS_MEM_CFG - Global Config Registers 300h */ +#define MCQ_MODE_SELECT BIT(0) + +/* CQISy - CQ y Interrupt Status Register */ +#define UFSHCD_MCQ_CQIS_TAIL_ENT_PUSH_STS 0x1 + +/* UICCMD - UIC Command */ +#define COMMAND_OPCODE_MASK 0xFF +#define GEN_SELECTOR_INDEX_MASK 0xFFFF + +#define MIB_ATTRIBUTE_MASK UFS_MASK(0xFFFF, 16) +#define RESET_LEVEL 0xFF + +#define ATTR_SET_TYPE_MASK UFS_MASK(0xFF, 16) +#define CFG_RESULT_CODE_MASK 0xFF +#define GENERIC_ERROR_CODE_MASK 0xFF + +/* GenSelectorIndex calculation macros for M-PHY attributes */ +#define UIC_ARG_MPHY_TX_GEN_SEL_INDEX(lane) (lane) +#define UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane) (PA_MAXDATALANES + (lane)) + +#define UIC_ARG_MIB_SEL(attr, sel) ((((attr) & 0xFFFF) << 16) |\ + ((sel) & 0xFFFF)) +#define UIC_ARG_MIB(attr) UIC_ARG_MIB_SEL(attr, 0) +#define UIC_ARG_ATTR_TYPE(t) (((t) & 0xFF) << 16) +#define UIC_GET_ATTR_ID(v) (((v) >> 16) & 0xFFFF) + +/* Link Status*/ +enum link_status { + UFSHCD_LINK_IS_DOWN = 1, + UFSHCD_LINK_IS_UP = 2, +}; + +/* UIC Commands */ +enum uic_cmd_dme { + UIC_CMD_DME_GET = 0x01, + UIC_CMD_DME_SET = 0x02, + UIC_CMD_DME_PEER_GET = 0x03, + UIC_CMD_DME_PEER_SET = 0x04, + UIC_CMD_DME_POWERON = 0x10, + UIC_CMD_DME_POWEROFF = 0x11, + UIC_CMD_DME_ENABLE = 0x12, + UIC_CMD_DME_RESET = 0x14, + UIC_CMD_DME_END_PT_RST = 0x15, + UIC_CMD_DME_LINK_STARTUP = 0x16, + UIC_CMD_DME_HIBER_ENTER = 0x17, + UIC_CMD_DME_HIBER_EXIT = 0x18, + UIC_CMD_DME_TEST_MODE = 0x1A, +}; + +/* UIC Config result code / Generic error code */ +enum { + UIC_CMD_RESULT_SUCCESS = 0x00, + UIC_CMD_RESULT_INVALID_ATTR = 0x01, + UIC_CMD_RESULT_FAILURE = 0x01, + UIC_CMD_RESULT_INVALID_ATTR_VALUE = 0x02, + UIC_CMD_RESULT_READ_ONLY_ATTR = 0x03, + UIC_CMD_RESULT_WRITE_ONLY_ATTR = 0x04, + UIC_CMD_RESULT_BAD_INDEX = 0x05, + UIC_CMD_RESULT_LOCKED_ATTR = 0x06, + UIC_CMD_RESULT_BAD_TEST_FEATURE_INDEX = 0x07, + UIC_CMD_RESULT_PEER_COMM_FAILURE = 0x08, + UIC_CMD_RESULT_BUSY = 0x09, + UIC_CMD_RESULT_DME_FAILURE = 0x0A, +}; + +#define MASK_UIC_COMMAND_RESULT 0xFF + +#define INT_AGGR_COUNTER_THLD_VAL(c) (((c) & 0x1F) << 8) +#define INT_AGGR_TIMEOUT_VAL(t) (((t) & 0xFF) << 0) + +/* + * Request Descriptor Definitions + */ + +/* To accommodate UFS2.0 required Command type */ +enum { + UTP_CMD_TYPE_UFS_STORAGE = 0x1, +}; + +enum { + UTP_SCSI_COMMAND = 0x00000000, + UTP_REQ_DESC_INT_CMD = 0x01000000, + UTP_NATIVE_UFS_COMMAND = 0x10000000, + UTP_DEVICE_MANAGEMENT_FUNCTION = 0x20000000, +}; + +/* UTP Transfer Request Data Direction (DD) */ +enum utp_data_direction { + UTP_NO_DATA_TRANSFER = 0, + UTP_HOST_TO_DEVICE = 1, + UTP_DEVICE_TO_HOST = 2, +}; + +/* Overall command status values */ +enum utp_ocs { + OCS_SUCCESS = 0x0, + OCS_INVALID_CMD_TABLE_ATTR = 0x1, + OCS_INVALID_PRDT_ATTR = 0x2, + OCS_MISMATCH_DATA_BUF_SIZE = 0x3, + OCS_MISMATCH_RESP_UPIU_SIZE = 0x4, + OCS_PEER_COMM_FAILURE = 0x5, + OCS_ABORTED = 0x6, + OCS_FATAL_ERROR = 0x7, + OCS_DEVICE_FATAL_ERROR = 0x8, + OCS_INVALID_CRYPTO_CONFIG = 0x9, + OCS_GENERAL_CRYPTO_ERROR = 0xA, + OCS_INVALID_COMMAND_STATUS = 0x0F, +}; + +enum { + MASK_OCS = 0x0F, +}; + +/* The maximum length of the data byte count field in the PRDT is 256KB */ +#define PRDT_DATA_BYTE_COUNT_MAX SZ_256K +/* The granularity of the data byte count field in the PRDT is 32-bit */ +#define PRDT_DATA_BYTE_COUNT_PAD 4 + + +struct ufshcd_sg_entry { + __le32 base_addr; + __le32 upper_addr; + __le32 reserved; + __le32 size; +}; + +#define MAX_BUFF 128 +/** + * struct utp_transfer_cmd_desc - UFS Command Descriptor structure + * @command_upiu: Command UPIU Frame address + * @response_upiu: Response UPIU Frame address + * @prd_table: Physical Region Descriptor + */ +struct utp_transfer_cmd_desc { + u8 command_upiu[ALIGNED_UPIU_SIZE]; + u8 response_upiu[ALIGNED_UPIU_SIZE]; + struct ufshcd_sg_entry prd_table[MAX_BUFF]; +}; + +/** + * struct request_desc_header - Descriptor Header common to both UTRD and UTMRD + * @dword0: Descriptor Header DW0 + * @dword1: Descriptor Header DW1 + * @dword2: Descriptor Header DW2 + * @dword3: Descriptor Header DW3 + */ +struct request_desc_header { + __le32 dword_0; + __le32 dword_1; + __le32 dword_2; + __le32 dword_3; +}; + +/** + * struct utp_transfer_req_desc - UTRD structure + * @header: UTRD header DW-0 to DW-3 + * @command_desc_base_addr_lo: UCD base address low DW-4 + * @command_desc_base_addr_hi: UCD base address high DW-5 + * @response_upiu_length: response UPIU length DW-6 + * @response_upiu_offset: response UPIU offset DW-6 + * @prd_table_length: Physical region descriptor length DW-7 + * @prd_table_offset: Physical region descriptor offset DW-7 + */ +struct utp_transfer_req_desc { + /* DW 0-3 */ + struct request_desc_header header; + + /* DW 4-5*/ + __le32 command_desc_base_addr_lo; + __le32 command_desc_base_addr_hi; + + /* DW 6 */ + __le16 response_upiu_length; + __le16 response_upiu_offset; + + /* DW 7 */ + __le16 prd_table_length; + __le16 prd_table_offset; +}; + +/** + * struct utp_upiu_header - UPIU header structure + * @dword_0: UPIU header DW-0 + * @dword_1: UPIU header DW-1 + * @dword_2: UPIU header DW-2 + */ +struct utp_upiu_header { + __be32 dword_0; + __be32 dword_1; + __be32 dword_2; +}; + +/* + * UTMRD structure. + */ +struct utp_task_req_desc { + /* DW 0-3 */ + struct request_desc_header header; + + /* DW 4-11 - Task request UPIU structure */ + struct utp_upiu_header req_header; + __be32 input_param1; + __be32 input_param2; + __be32 input_param3; + __be32 __reserved1[2]; + + /* DW 12-19 - Task Management Response UPIU structure */ + struct utp_upiu_header rsp_header; + __be32 output_param1; + __be32 output_param2; + __be32 __reserved2[3]; +}; + +#endif diff --git a/drivers/ufs/unipro.h b/drivers/ufs/unipro.h index 6df953e6e60..56833602b77 100644 --- a/drivers/ufs/unipro.h +++ b/drivers/ufs/unipro.h @@ -34,6 +34,18 @@ /* * M-RX Configuration Attributes */ +#define RX_HS_G1_SYNC_LENGTH_CAP 0x008B +#define RX_HS_G1_PREP_LENGTH_CAP 0x008C +#define RX_MIN_ACTIVATETIME_CAPABILITY 0x008F +#define RX_HIBERN8TIME_CAPABILITY 0x0092 +#define RX_HS_G2_SYNC_LENGTH_CAP 0x0094 +#define RX_HS_G3_SYNC_LENGTH_CAP 0x0095 +#define RX_HS_G2_PREP_LENGTH_CAP 0x0096 +#define RX_HS_G3_PREP_LENGTH_CAP 0x0097 +#define RX_ADV_GRANULARITY_CAP 0x0098 +#define RX_HIBERN8TIME_CAP 0x0092 +#define RX_ADV_HIBERN8TIME_CAP 0x0099 +#define RX_ADV_MIN_ACTIVATETIME_CAP 0x009A #define RX_MODE 0x00A1 #define RX_HSRATE_SERIES 0x00A2 #define RX_HSGEAR 0x00A3 @@ -42,24 +54,27 @@ #define RX_HS_UNTERMINATED_ENABLE 0x00A6 #define RX_ENTER_HIBERN8 0x00A7 #define RX_BYPASS_8B10B_ENABLE 0x00A8 -#define RX_TERMINATION_FORCE_ENABLE 0x0089 -#define RX_MIN_ACTIVATETIME_CAPABILITY 0x008F -#define RX_HIBERN8TIME_CAPABILITY 0x0092 +#define RX_TERMINATION_FORCE_ENABLE 0x00A9 +#define RXCALCTRL 0x00B4 +#define RXSQCTRL 0x00B5 +#define CFGRXCDR8 0x00BA +#define CFGRXOVR8 0x00BD +#define CFGRXOVR6 0x00BF +#define RXDIRECTCTRL2 0x00C7 +#define CFGRXOVR4 0x00E9 #define RX_REFCLKFREQ 0x00EB #define RX_CFGCLKFREQVAL 0x00EC #define CFGWIDEINLN 0x00F0 -#define CFGRXCDR8 0x00BA #define ENARXDIRECTCFG4 0x00F2 -#define CFGRXOVR8 0x00BD -#define RXDIRECTCTRL2 0x00C7 #define ENARXDIRECTCFG3 0x00F3 -#define RXCALCTRL 0x00B4 #define ENARXDIRECTCFG2 0x00F4 -#define CFGRXOVR4 0x00E9 -#define RXSQCTRL 0x00B5 -#define CFGRXOVR6 0x00BF -#define is_mphy_tx_attr(attr) (attr < RX_MODE) +#define is_mphy_tx_attr(attr) ((attr) < RX_MODE) +#define RX_ADV_FINE_GRAN_STEP(x) ((((x) & 0x3) << 1) | 0x1) +#define SYNC_LEN_FINE(x) ((x) & 0x3F) +#define SYNC_LEN_COARSE(x) ((1 << 6) | ((x) & 0x3F)) +#define PREP_LEN(x) ((x) & 0xF) + #define RX_MIN_ACTIVATETIME_UNIT_US 100 #define HIBERN8TIME_UNIT_US 100 @@ -77,51 +92,54 @@ #define CBPRGPLL2 UNIPRO_CB_OFFSET(0x00F8) #define CBPRGTUNING UNIPRO_CB_OFFSET(0x00FB) -#define UNIPRO_CB_OFFSET(x) (0x8000 | x) +#define UNIPRO_CB_OFFSET(x) (0x8000 | (x)) /* - * PHY Adpater attributes + * PHY Adapter attributes */ -#define PA_ACTIVETXDATALANES 0x1560 -#define PA_ACTIVERXDATALANES 0x1580 -#define PA_TXTRAILINGCLOCKS 0x1564 #define PA_PHY_TYPE 0x1500 #define PA_AVAILTXDATALANES 0x1520 -#define PA_AVAILRXDATALANES 0x1540 -#define PA_MINRXTRAILINGCLOCKS 0x1543 -#define PA_TXPWRSTATUS 0x1567 -#define PA_RXPWRSTATUS 0x1582 -#define PA_TXFORCECLOCK 0x1562 -#define PA_TXPWRMODE 0x1563 -#define PA_LEGACYDPHYESCDL 0x1570 #define PA_MAXTXSPEEDFAST 0x1521 #define PA_MAXTXSPEEDSLOW 0x1522 #define PA_MAXRXSPEEDFAST 0x1541 #define PA_MAXRXSPEEDSLOW 0x1542 #define PA_TXLINKSTARTUPHS 0x1544 +#define PA_AVAILRXDATALANES 0x1540 +#define PA_MINRXTRAILINGCLOCKS 0x1543 #define PA_LOCAL_TX_LCC_ENABLE 0x155E +#define PA_ACTIVETXDATALANES 0x1560 +#define PA_CONNECTEDTXDATALANES 0x1561 +#define PA_TXFORCECLOCK 0x1562 +#define PA_TXPWRMODE 0x1563 +#define PA_TXTRAILINGCLOCKS 0x1564 #define PA_TXSPEEDFAST 0x1565 #define PA_TXSPEEDSLOW 0x1566 -#define PA_REMOTEVERINFO 0x15A0 +#define PA_TXPWRSTATUS 0x1567 #define PA_TXGEAR 0x1568 #define PA_TXTERMINATION 0x1569 #define PA_HSSERIES 0x156A +#define PA_LEGACYDPHYESCDL 0x1570 #define PA_PWRMODE 0x1571 +#define PA_ACTIVERXDATALANES 0x1580 +#define PA_CONNECTEDRXDATALANES 0x1581 +#define PA_RXPWRSTATUS 0x1582 #define PA_RXGEAR 0x1583 #define PA_RXTERMINATION 0x1584 #define PA_MAXRXPWMGEAR 0x1586 #define PA_MAXRXHSGEAR 0x1587 -#define PA_RXHSUNTERMCAP 0x15A5 -#define PA_RXLSTERMCAP 0x15A6 -#define PA_GRANULARITY 0x15AA #define PA_PACPREQTIMEOUT 0x1590 #define PA_PACPREQEOBTIMEOUT 0x1591 +#define PA_REMOTEVERINFO 0x15A0 +#define PA_LOGICALLANEMAP 0x15A1 +#define PA_SLEEPNOCONFIGTIME 0x15A2 +#define PA_STALLNOCONFIGTIME 0x15A3 +#define PA_SAVECONFIGTIME 0x15A4 +#define PA_RXHSUNTERMCAP 0x15A5 +#define PA_RXLSTERMCAP 0x15A6 #define PA_HIBERN8TIME 0x15A7 #define PA_LOCALVERINFO 0x15A9 +#define PA_GRANULARITY 0x15AA #define PA_TACTIVATE 0x15A8 -#define PA_PACPFRAMECOUNT 0x15C0 -#define PA_PACPERRORCOUNT 0x15C1 -#define PA_PHYTESTCONTROL 0x15C2 #define PA_PWRMODEUSERDATA0 0x15B0 #define PA_PWRMODEUSERDATA1 0x15B1 #define PA_PWRMODEUSERDATA2 0x15B2 @@ -134,12 +152,9 @@ #define PA_PWRMODEUSERDATA9 0x15B9 #define PA_PWRMODEUSERDATA10 0x15BA #define PA_PWRMODEUSERDATA11 0x15BB -#define PA_CONNECTEDTXDATALANES 0x1561 -#define PA_CONNECTEDRXDATALANES 0x1581 -#define PA_LOGICALLANEMAP 0x15A1 -#define PA_SLEEPNOCONFIGTIME 0x15A2 -#define PA_STALLNOCONFIGTIME 0x15A3 -#define PA_SAVECONFIGTIME 0x15A4 +#define PA_PACPFRAMECOUNT 0x15C0 +#define PA_PACPERRORCOUNT 0x15C1 +#define PA_PHYTESTCONTROL 0x15C2 #define PA_TXHSADAPTTYPE 0x15D4 /* Adapt type for PA_TXHSADAPTTYPE attribute */ @@ -151,9 +166,9 @@ #define PA_HIBERN8_TIME_UNIT_US 100 /*Other attributes*/ +#define VS_POWERSTATE 0xD083 #define VS_MPHYCFGUPDT 0xD085 #define VS_DEBUGOMC 0xD09E -#define VS_POWERSTATE 0xD083 #define VS_MPHYDISABLE 0xD0C1 #define PA_GRANULARITY_MIN_VAL 1 @@ -163,7 +178,7 @@ #define PA_MAXDATALANES 4 /* PA power modes */ -enum { +enum ufs_pa_pwr_mode { FAST_MODE = 1, SLOW_MODE = 2, FASTAUTO_MODE = 4, @@ -171,8 +186,11 @@ enum { UNCHANGED = 7, }; +#define PWRMODE_MASK 0xF +#define PWRMODE_RX_OFFSET 4 + /* PA TX/RX Frequency Series */ -enum { +enum ufs_hs_gear_rate { PA_HS_MODE_A = 1, PA_HS_MODE_B = 2, }; @@ -193,14 +211,24 @@ enum ufs_hs_gear_tag { UFS_HS_G1, /* HS Gear 1 (default for reset) */ UFS_HS_G2, /* HS Gear 2 */ UFS_HS_G3, /* HS Gear 3 */ + UFS_HS_G4, /* HS Gear 4 */ + UFS_HS_G5 /* HS Gear 5 */ +}; + +enum ufs_lanes { + UFS_LANE_DONT_CHANGE, /* Don't change Lane */ + UFS_LANE_1, /* Lane 1 (default for reset) */ + UFS_LANE_2, /* Lane 2 */ }; enum ufs_unipro_ver { UFS_UNIPRO_VER_RESERVED = 0, UFS_UNIPRO_VER_1_40 = 1, /* UniPro version 1.40 */ UFS_UNIPRO_VER_1_41 = 2, /* UniPro version 1.41 */ - UFS_UNIPRO_VER_1_6 = 3, /* UniPro version 1.6 */ - UFS_UNIPRO_VER_MAX = 4, /* UniPro unsupported version */ + UFS_UNIPRO_VER_1_6 = 3, /* UniPro version 1.6 */ + UFS_UNIPRO_VER_1_61 = 4, /* UniPro version 1.61 */ + UFS_UNIPRO_VER_1_8 = 5, /* UniPro version 1.8 */ + UFS_UNIPRO_VER_MAX = 6, /* UniPro unsupported version */ /* UniPro version field mask in PA_LOCALVERINFO */ UFS_UNIPRO_VER_MASK = 0xF, }; @@ -208,27 +236,27 @@ enum ufs_unipro_ver { /* * Data Link Layer Attributes */ +#define DL_TXPREEMPTIONCAP 0x2000 +#define DL_TC0TXMAXSDUSIZE 0x2001 +#define DL_TC0RXINITCREDITVAL 0x2002 +#define DL_TC1TXMAXSDUSIZE 0x2003 +#define DL_TC1RXINITCREDITVAL 0x2004 +#define DL_TC0TXBUFFERSIZE 0x2005 +#define DL_TC1TXBUFFERSIZE 0x2006 #define DL_TC0TXFCTHRESHOLD 0x2040 #define DL_FC0PROTTIMEOUTVAL 0x2041 #define DL_TC0REPLAYTIMEOUTVAL 0x2042 #define DL_AFC0REQTIMEOUTVAL 0x2043 #define DL_AFC0CREDITTHRESHOLD 0x2044 #define DL_TC0OUTACKTHRESHOLD 0x2045 +#define DL_PEERTC0PRESENT 0x2046 +#define DL_PEERTC0RXINITCREVAL 0x2047 #define DL_TC1TXFCTHRESHOLD 0x2060 #define DL_FC1PROTTIMEOUTVAL 0x2061 #define DL_TC1REPLAYTIMEOUTVAL 0x2062 #define DL_AFC1REQTIMEOUTVAL 0x2063 #define DL_AFC1CREDITTHRESHOLD 0x2064 #define DL_TC1OUTACKTHRESHOLD 0x2065 -#define DL_TXPREEMPTIONCAP 0x2000 -#define DL_TC0TXMAXSDUSIZE 0x2001 -#define DL_TC0RXINITCREDITVAL 0x2002 -#define DL_TC0TXBUFFERSIZE 0x2005 -#define DL_PEERTC0PRESENT 0x2046 -#define DL_PEERTC0RXINITCREVAL 0x2047 -#define DL_TC1TXMAXSDUSIZE 0x2003 -#define DL_TC1RXINITCREDITVAL 0x2004 -#define DL_TC1TXBUFFERSIZE 0x2006 #define DL_PEERTC1PRESENT 0x2066 #define DL_PEERTC1RXINITCREVAL 0x2067 diff --git a/drivers/usb/cdns3/Kconfig b/drivers/usb/cdns3/Kconfig index 35b61497d9c..1d5e4afac6c 100644 --- a/drivers/usb/cdns3/Kconfig +++ b/drivers/usb/cdns3/Kconfig @@ -49,6 +49,13 @@ config SPL_USB_CDNS3_HOST Host controller is compliant with XHCI so it will use standard XHCI driver. +config USB_CDNS3_STARFIVE + tristate "Cadence USB3 support on Starfive platforms" + default y if STARFIVE_JH7110 + help + Say 'Y' here if you are building for Starfive platforms + that contain Cadence USB3 controller core. E.g.: JH7110. + config USB_CDNS3_TI tristate "Cadence USB3 support on TI platforms" default USB_CDNS3 diff --git a/drivers/usb/cdns3/Makefile b/drivers/usb/cdns3/Makefile index d6047856091..1f00f23f704 100644 --- a/drivers/usb/cdns3/Makefile +++ b/drivers/usb/cdns3/Makefile @@ -8,4 +8,5 @@ cdns3-$(CONFIG_$(XPL_)USB_CDNS3_GADGET) += gadget.o ep0.o cdns3-$(CONFIG_$(XPL_)USB_CDNS3_HOST) += host.o +obj-$(CONFIG_USB_CDNS3_STARFIVE) += cdns3-starfive.o obj-$(CONFIG_USB_CDNS3_TI) += cdns3-ti.o diff --git a/drivers/usb/cdns3/cdns3-starfive.c b/drivers/usb/cdns3/cdns3-starfive.c new file mode 100644 index 00000000000..78ceb831b19 --- /dev/null +++ b/drivers/usb/cdns3/cdns3-starfive.c @@ -0,0 +1,182 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * cdns3-starfive.c - StarFive specific Glue layer for Cadence USB Controller + * + * Copyright (C) 2024 StarFive Technology Co., Ltd. + * + * Author: Minda Chen <minda.chen@starfivetech.com> + */ + +#include <asm/io.h> +#include <clk.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <linux/bitops.h> +#include <linux/usb/otg.h> +#include <malloc.h> +#include <reset.h> +#include <regmap.h> +#include <syscon.h> + +#include "core.h" + +#define USB_STRAP_HOST BIT(17) +#define USB_STRAP_DEVICE BIT(18) +#define USB_STRAP_MASK GENMASK(18, 16) + +#define USB_SUSPENDM_HOST BIT(19) +#define USB_SUSPENDM_MASK BIT(19) + +#define USB_MISC_CFG_MASK GENMASK(23, 20) +#define USB_SUSPENDM_BYPS BIT(20) +#define USB_PLL_EN BIT(22) +#define USB_REFCLK_MODE BIT(23) + +struct cdns_starfive { + struct udevice *dev; + struct regmap *stg_syscon; + struct reset_ctl_bulk resets; + struct clk_bulk clks; + u32 stg_usb_mode; + enum usb_dr_mode mode; +}; + +static void cdns_mode_init(struct cdns_starfive *data, enum usb_dr_mode mode) +{ + unsigned int strap, suspendm; + + regmap_update_bits(data->stg_syscon, data->stg_usb_mode, + USB_MISC_CFG_MASK, + USB_SUSPENDM_BYPS | USB_PLL_EN | USB_REFCLK_MODE); + + switch (mode) { + case USB_DR_MODE_HOST: + strap = USB_STRAP_HOST; + suspendm = USB_SUSPENDM_HOST; + break; + case USB_DR_MODE_PERIPHERAL: + strap = USB_STRAP_DEVICE; + suspendm = 0; + break; + default: + return; + } + + regmap_update_bits(data->stg_syscon, data->stg_usb_mode, + USB_SUSPENDM_MASK | USB_STRAP_MASK, + strap | suspendm); +} + +static void cdns_clk_rst_deinit(struct cdns_starfive *data) +{ + reset_assert_bulk(&data->resets); + clk_disable_bulk(&data->clks); +} + +static int cdns_clk_rst_init(struct cdns_starfive *data) +{ + int ret; + + ret = clk_get_bulk(data->dev, &data->clks); + if (ret) + return ret; + + ret = reset_get_bulk(data->dev, &data->resets); + if (ret) + goto err_clk; + + ret = clk_enable_bulk(&data->clks); + if (ret) { + dev_err(data->dev, "clk enable failed: %d\n", ret); + goto err_en_clk; + } + + ret = reset_deassert_bulk(&data->resets); + if (ret) { + dev_err(data->dev, "reset deassert failed: %d\n", ret); + goto err_reset; + } + + return 0; + +err_reset: + clk_disable_bulk(&data->clks); +err_en_clk: + reset_release_bulk(&data->resets); +err_clk: + clk_release_bulk(&data->clks); + + return ret; +} + +static int cdns_starfive_get_syscon(struct cdns_starfive *data) +{ + struct ofnode_phandle_args phandle; + int ret; + + ret = dev_read_phandle_with_args(data->dev, "starfive,stg-syscon", NULL, 1, 0, + &phandle); + if (ret < 0) { + dev_err(data->dev, "Can't get stg cfg phandle: %d\n", ret); + return ret; + } + + data->stg_syscon = syscon_node_to_regmap(phandle.node); + if (IS_ERR(data->stg_syscon)) { + dev_err(data->dev, "fail to get regmap: %d\n", (int)PTR_ERR(data->stg_syscon)); + return PTR_ERR(data->stg_syscon); + } + + data->stg_usb_mode = phandle.args[0]; + + return 0; +} + +static int cdns_starfive_probe(struct udevice *dev) +{ + struct cdns_starfive *data = dev_get_plat(dev); + enum usb_dr_mode dr_mode; + int ret; + + data->dev = dev; + + ret = cdns_starfive_get_syscon(data); + if (ret) + return ret; + + dr_mode = usb_get_dr_mode(dev_ofnode(dev)); + + data->mode = dr_mode; + ret = cdns_clk_rst_init(data); + if (ret) { + dev_err(data->dev, "clk reset failed: %d\n", ret); + return ret; + } + cdns_mode_init(data, dr_mode); + + return 0; +} + +static int cdns_starfive_remove(struct udevice *dev) +{ + struct cdns_starfive *data = dev_get_plat(dev); + + cdns_clk_rst_deinit(data); + return 0; +} + +static const struct udevice_id cdns_starfive_of_match[] = { + { .compatible = "starfive,jh7110-usb", }, + {}, +}; + +U_BOOT_DRIVER(cdns_starfive) = { + .name = "cdns-starfive", + .id = UCLASS_NOP, + .of_match = cdns_starfive_of_match, + .bind = cdns3_bind, + .probe = cdns_starfive_probe, + .remove = cdns_starfive_remove, + .plat_auto = sizeof(struct cdns_starfive), + .flags = DM_FLAG_OS_PREPARE, +}; diff --git a/drivers/usb/cdns3/core.c b/drivers/usb/cdns3/core.c index 4cfd38ec245..4434dc15bec 100644 --- a/drivers/usb/cdns3/core.c +++ b/drivers/usb/cdns3/core.c @@ -410,6 +410,9 @@ int cdns3_bind(struct udevice *parent) name = ofnode_get_name(node); dr_mode = usb_get_dr_mode(node); + if (dr_mode == USB_DR_MODE_UNKNOWN) + dr_mode = usb_get_dr_mode(dev_ofnode(parent)); + switch (dr_mode) { #if defined(CONFIG_SPL_USB_HOST) || \ (!defined(CONFIG_XPL_BUILD) && defined(CONFIG_USB_HOST)) diff --git a/drivers/usb/cdns3/drd.c b/drivers/usb/cdns3/drd.c index 47874fec29e..cbb13342343 100644 --- a/drivers/usb/cdns3/drd.c +++ b/drivers/usb/cdns3/drd.c @@ -217,15 +217,19 @@ static int cdns3_init_otg_mode(struct cdns3 *cdns) int cdns3_drd_update_mode(struct cdns3 *cdns) { int ret = 0; + int mode; switch (cdns->dr_mode) { case USB_DR_MODE_PERIPHERAL: + mode = PHY_MODE_USB_DEVICE; ret = cdns3_set_mode(cdns, USB_DR_MODE_PERIPHERAL); break; case USB_DR_MODE_HOST: + mode = PHY_MODE_USB_HOST; ret = cdns3_set_mode(cdns, USB_DR_MODE_HOST); break; case USB_DR_MODE_OTG: + mode = PHY_MODE_USB_OTG; ret = cdns3_init_otg_mode(cdns); break; default: @@ -234,6 +238,16 @@ int cdns3_drd_update_mode(struct cdns3 *cdns) return -EINVAL; } + ret = generic_phy_set_mode(&cdns->usb2_phy, mode, 0); + if (ret) { + dev_err(cdns->dev, "Set usb 2.0 PHY mode failed %d\n", ret); + return ret; + } + + ret = generic_phy_set_mode(&cdns->usb3_phy, mode, 0); + if (ret) + dev_err(cdns->dev, "Set usb 3.0 PHY mode failed %d\n", ret); + return ret; } diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c index e5a383407a2..477ecd02098 100644 --- a/drivers/usb/dwc3/gadget.c +++ b/drivers/usb/dwc3/gadget.c @@ -1631,8 +1631,25 @@ usb_ep *dwc3_gadget_match_ep(struct usb_gadget *gadget, return dwc3_find_ep(gadget, "ep1in"); if (usb_endpoint_is_bulk_out(desc)) return dwc3_find_ep(gadget, "ep2out"); - if (usb_endpoint_is_int_in(desc)) + if (usb_endpoint_is_int_in(desc)) { + /* + * Special workaround for NXP UUU tool in SPL. + * + * The tool excepts the interrupt-in endpoint to be ep1in, + * otherwise it crashes. This is a result of the previous + * hard-coded EP setup in drivers/usb/gadget/epautoconf.c + * which did special-case EP allocation for SPL builds, + * and which was since converted to this callback, but + * without the special-case EP allocation in SPL part. + * + * This reinstates the SPL part in an isolated manner, + * only for NXP iMX SoCs, only for SPL builds, and only + * for the ep1in interrupt-in endpoint. + */ + if (IS_ENABLED(CONFIG_MACH_IMX) && IS_ENABLED(CONFIG_XPL_BUILD)) + return dwc3_find_ep(gadget, "ep1in"); return dwc3_find_ep(gadget, "ep3in"); + } return NULL; } diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 11d17076a96..df607303616 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -293,27 +293,6 @@ config PANEL_HX8238D source "drivers/video/fonts/Kconfig" -config VIDCONSOLE_AS_LCD - bool "Use 'vidconsole' when CONFIG_VIDCONSOLE_AS_NAME string is seen in stdout" - help - This is a work-around for boards which have 'lcd' or 'vga' in their - stdout environment variable, but have moved to use driver model for - video. In this case the console will no-longer work. While it is - possible to update the environment, the breakage may be confusing for - users. This option will be removed around the end of 2020. - -config VIDCONSOLE_AS_NAME - string "Use 'vidconsole' when string defined here is seen in stdout" - depends on VIDCONSOLE_AS_LCD - default "lcd" if LCD || TEGRA_COMMON - default "vga" if !LCD - help - This is a work-around for boards which have 'lcd' or 'vga' in their - stdout environment variable, but have moved to use driver model for - video. In this case the console will no-longer work. While it is - possible to update the environment, the breakage may be confusing for - users. This option will be removed around the end of 2020. - config VIDEO_BOCHS bool "Enable Bochs video emulation for QEMU" help |