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-rw-r--r--drivers/i2c/Makefile2
-rw-r--r--drivers/i2c/fti2c010.c352
-rw-r--r--drivers/i2c/omap24xx_i2c.c6
-rw-r--r--drivers/i2c/s3c24x0_i2c.c284
-rw-r--r--drivers/misc/cros_ec_spi.c3
-rw-r--r--drivers/mmc/Makefile1
-rw-r--r--drivers/mmc/dw_mmc.c23
-rw-r--r--drivers/mmc/exynos_dw_mmc.c14
-rw-r--r--drivers/mmc/fsl_esdhc_spl.c5
-rw-r--r--drivers/mmc/ftsdc021_sdhci.c33
-rw-r--r--drivers/mtd/spi/Makefile1
-rw-r--r--drivers/mtd/spi/fsl_espi_spl.c5
-rw-r--r--drivers/mtd/spi/sandbox.c483
-rw-r--r--drivers/mtd/spi/sf_internal.h1
-rw-r--r--drivers/mtd/spi/sf_probe.c28
-rw-r--r--drivers/spi/Makefile1
-rw-r--r--drivers/spi/bfin_spi.c17
-rw-r--r--drivers/spi/bfin_spi6xx.c5
-rw-r--r--drivers/spi/exynos_spi.c10
-rw-r--r--drivers/spi/sandbox_spi.c204
-rw-r--r--drivers/spi/spi.c19
21 files changed, 1204 insertions, 293 deletions
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 553b519cca3..fa3a875705b 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -12,7 +12,6 @@ obj-$(CONFIG_I2C_MVTWSI) += mvtwsi.o
obj-$(CONFIG_I2C_MV) += mv_i2c.o
obj-$(CONFIG_I2C_MXS) += mxs_i2c.o
obj-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o
-obj-$(CONFIG_DRIVER_S3C24X0_I2C) += s3c24x0_i2c.o
obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
obj-$(CONFIG_U8500_I2C) += u8500_i2c.o
obj-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o
@@ -24,6 +23,7 @@ obj-$(CONFIG_SYS_I2C_OMAP24XX) += omap24xx_i2c.o
obj-$(CONFIG_SYS_I2C_OMAP34XX) += omap24xx_i2c.o
obj-$(CONFIG_SYS_I2C_PPC4XX) += ppc4xx_i2c.o
obj-$(CONFIG_SYS_I2C_RCAR) += rcar_i2c.o
+obj-$(CONFIG_SYS_I2C_S3C24X0) += s3c24x0_i2c.o
obj-$(CONFIG_SYS_I2C_SH) += sh_i2c.o
obj-$(CONFIG_SYS_I2C_SOFT) += soft_i2c.o
obj-$(CONFIG_SYS_I2C_TEGRA) += tegra_i2c.o
diff --git a/drivers/i2c/fti2c010.c b/drivers/i2c/fti2c010.c
index ddeb941fafb..fb9fa353d10 100644
--- a/drivers/i2c/fti2c010.c
+++ b/drivers/i2c/fti2c010.c
@@ -13,67 +13,78 @@
#include "fti2c010.h"
-#ifndef CONFIG_HARD_I2C
-#error "fti2c010: CONFIG_HARD_I2C is not defined"
+#ifndef CONFIG_SYS_I2C_SPEED
+#define CONFIG_SYS_I2C_SPEED 5000
#endif
-#ifndef CONFIG_SYS_I2C_SPEED
-#define CONFIG_SYS_I2C_SPEED 50000
+#ifndef CONFIG_SYS_I2C_SLAVE
+#define CONFIG_SYS_I2C_SLAVE 0
#endif
-#ifndef CONFIG_FTI2C010_FREQ
-#define CONFIG_FTI2C010_FREQ clk_get_rate("I2C")
+#ifndef CONFIG_FTI2C010_CLOCK
+#define CONFIG_FTI2C010_CLOCK clk_get_rate("I2C")
#endif
-/* command timeout */
-#define CFG_CMD_TIMEOUT 10 /* ms */
+#ifndef CONFIG_FTI2C010_TIMEOUT
+#define CONFIG_FTI2C010_TIMEOUT 10 /* ms */
+#endif
-/* 7-bit chip address + 1-bit read/write */
-#define I2C_RD(chip) ((((chip) << 1) & 0xff) | 1)
-#define I2C_WR(chip) (((chip) << 1) & 0xff)
+/* 7-bit dev address + 1-bit read/write */
+#define I2C_RD(dev) ((((dev) << 1) & 0xfe) | 1)
+#define I2C_WR(dev) (((dev) << 1) & 0xfe)
struct fti2c010_chip {
- void __iomem *regs;
- uint bus;
- uint speed;
+ struct fti2c010_regs *regs;
};
static struct fti2c010_chip chip_list[] = {
{
- .bus = 0,
- .regs = (void __iomem *)CONFIG_FTI2C010_BASE,
+ .regs = (struct fti2c010_regs *)CONFIG_FTI2C010_BASE,
},
-#ifdef CONFIG_I2C_MULTI_BUS
-# ifdef CONFIG_FTI2C010_BASE1
+#ifdef CONFIG_FTI2C010_BASE1
{
- .bus = 1,
- .regs = (void __iomem *)CONFIG_FTI2C010_BASE1,
+ .regs = (struct fti2c010_regs *)CONFIG_FTI2C010_BASE1,
},
-# endif
-# ifdef CONFIG_FTI2C010_BASE2
+#endif
+#ifdef CONFIG_FTI2C010_BASE2
{
- .bus = 2,
- .regs = (void __iomem *)CONFIG_FTI2C010_BASE2,
+ .regs = (struct fti2c010_regs *)CONFIG_FTI2C010_BASE2,
},
-# endif
-# ifdef CONFIG_FTI2C010_BASE3
+#endif
+#ifdef CONFIG_FTI2C010_BASE3
{
- .bus = 3,
- .regs = (void __iomem *)CONFIG_FTI2C010_BASE3,
+ .regs = (struct fti2c010_regs *)CONFIG_FTI2C010_BASE3,
},
-# endif
-#endif /* #ifdef CONFIG_I2C_MULTI_BUS */
+#endif
};
-static struct fti2c010_chip *curr = chip_list;
+static int fti2c010_reset(struct fti2c010_chip *chip)
+{
+ ulong ts;
+ int ret = -1;
+ struct fti2c010_regs *regs = chip->regs;
+
+ writel(CR_I2CRST, &regs->cr);
+ for (ts = get_timer(0); get_timer(ts) < CONFIG_FTI2C010_TIMEOUT; ) {
+ if (!(readl(&regs->cr) & CR_I2CRST)) {
+ ret = 0;
+ break;
+ }
+ }
-static int fti2c010_wait(uint32_t mask)
+ if (ret)
+ printf("fti2c010: reset timeout\n");
+
+ return ret;
+}
+
+static int fti2c010_wait(struct fti2c010_chip *chip, uint32_t mask)
{
int ret = -1;
uint32_t stat, ts;
- struct fti2c010_regs *regs = curr->regs;
+ struct fti2c010_regs *regs = chip->regs;
- for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) {
+ for (ts = get_timer(0); get_timer(ts) < CONFIG_FTI2C010_TIMEOUT; ) {
stat = readl(&regs->sr);
if ((stat & mask) == mask) {
ret = 0;
@@ -84,88 +95,124 @@ static int fti2c010_wait(uint32_t mask)
return ret;
}
-/*
- * u-boot I2C API
- */
+static unsigned int set_i2c_bus_speed(struct fti2c010_chip *chip,
+ unsigned int speed)
+{
+ struct fti2c010_regs *regs = chip->regs;
+ unsigned int clk = CONFIG_FTI2C010_CLOCK;
+ unsigned int gsr = 0;
+ unsigned int tsr = 32;
+ unsigned int div, rate;
+
+ for (div = 0; div < 0x3ffff; ++div) {
+ /* SCLout = PCLK/(2*(COUNT + 2) + GSR) */
+ rate = clk / (2 * (div + 2) + gsr);
+ if (rate <= speed)
+ break;
+ }
+
+ writel(TGSR_GSR(gsr) | TGSR_TSR(tsr), &regs->tgsr);
+ writel(CDR_DIV(div), &regs->cdr);
+
+ return rate;
+}
/*
* Initialization, must be called once on start up, may be called
* repeatedly to change the speed and slave addresses.
*/
-void i2c_init(int speed, int slaveaddr)
+static void fti2c010_init(struct i2c_adapter *adap, int speed, int slaveaddr)
{
- if (speed || !curr->speed)
- i2c_set_bus_speed(speed);
+ struct fti2c010_chip *chip = chip_list + adap->hwadapnr;
- /* if slave mode disabled */
- if (!slaveaddr)
+ if (adap->init_done)
return;
- /*
- * TODO:
- * Implement slave mode, but is it really necessary?
- */
+#ifdef CONFIG_SYS_I2C_INIT_BOARD
+ /* Call board specific i2c bus reset routine before accessing the
+ * environment, which might be in a chip on that bus. For details
+ * about this problem see doc/I2C_Edge_Conditions.
+ */
+ i2c_init_board();
+#endif
+
+ /* master init */
+
+ fti2c010_reset(chip);
+
+ set_i2c_bus_speed(chip, speed);
+
+ /* slave init, don't care */
+
+#ifdef CONFIG_SYS_I2C_BOARD_LATE_INIT
+ /* Call board specific i2c bus reset routine AFTER the bus has been
+ * initialized. Use either this callpoint or i2c_init_board;
+ * which is called before fti2c010_init operations.
+ * For details about this problem see doc/I2C_Edge_Conditions.
+ */
+ i2c_board_late_init();
+#endif
}
/*
* Probe the given I2C chip address. Returns 0 if a chip responded,
* not 0 on failure.
*/
-int i2c_probe(uchar chip)
+static int fti2c010_probe(struct i2c_adapter *adap, u8 dev)
{
+ struct fti2c010_chip *chip = chip_list + adap->hwadapnr;
+ struct fti2c010_regs *regs = chip->regs;
int ret;
- struct fti2c010_regs *regs = curr->regs;
-
- i2c_init(0, 0);
/* 1. Select slave device (7bits Address + 1bit R/W) */
- writel(I2C_WR(chip), &regs->dr);
+ writel(I2C_WR(dev), &regs->dr);
writel(CR_ENABLE | CR_TBEN | CR_START, &regs->cr);
- ret = fti2c010_wait(SR_DT);
+ ret = fti2c010_wait(chip, SR_DT);
if (ret)
return ret;
/* 2. Select device register */
writel(0, &regs->dr);
writel(CR_ENABLE | CR_TBEN, &regs->cr);
- ret = fti2c010_wait(SR_DT);
+ ret = fti2c010_wait(chip, SR_DT);
return ret;
}
-/*
- * Read/Write interface:
- * chip: I2C chip address, range 0..127
- * addr: Memory (register) address within the chip
- * alen: Number of bytes to use for addr (typically 1, 2 for larger
- * memories, 0 for register type devices with only one
- * register)
- * buffer: Where to read/write the data
- * len: How many bytes to read/write
- *
- * Returns: 0 on success, not 0 on failure
- */
-int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
+static void to_i2c_addr(u8 *buf, uint32_t addr, int alen)
+{
+ int i, shift;
+
+ if (!buf || alen <= 0)
+ return;
+
+ /* MSB first */
+ i = 0;
+ shift = (alen - 1) * 8;
+ while (alen-- > 0) {
+ buf[i] = (u8)(addr >> shift);
+ shift -= 8;
+ }
+}
+
+static int fti2c010_read(struct i2c_adapter *adap,
+ u8 dev, uint addr, int alen, uchar *buf, int len)
{
+ struct fti2c010_chip *chip = chip_list + adap->hwadapnr;
+ struct fti2c010_regs *regs = chip->regs;
int ret, pos;
uchar paddr[4];
- struct fti2c010_regs *regs = curr->regs;
- i2c_init(0, 0);
-
- paddr[0] = (addr >> 0) & 0xFF;
- paddr[1] = (addr >> 8) & 0xFF;
- paddr[2] = (addr >> 16) & 0xFF;
- paddr[3] = (addr >> 24) & 0xFF;
+ to_i2c_addr(paddr, addr, alen);
/*
* Phase A. Set register address
*/
/* A.1 Select slave device (7bits Address + 1bit R/W) */
- writel(I2C_WR(chip), &regs->dr);
+ writel(I2C_WR(dev), &regs->dr);
writel(CR_ENABLE | CR_TBEN | CR_START, &regs->cr);
- ret = fti2c010_wait(SR_DT);
+ ret = fti2c010_wait(chip, SR_DT);
if (ret)
return ret;
@@ -175,7 +222,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
writel(paddr[pos], &regs->dr);
writel(ctrl, &regs->cr);
- ret = fti2c010_wait(SR_DT);
+ ret = fti2c010_wait(chip, SR_DT);
if (ret)
return ret;
}
@@ -185,9 +232,9 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
*/
/* B.1 Select slave device (7bits Address + 1bit R/W) */
- writel(I2C_RD(chip), &regs->dr);
+ writel(I2C_RD(dev), &regs->dr);
writel(CR_ENABLE | CR_TBEN | CR_START, &regs->cr);
- ret = fti2c010_wait(SR_DT);
+ ret = fti2c010_wait(chip, SR_DT);
if (ret)
return ret;
@@ -201,7 +248,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
stat |= SR_ACK;
}
writel(ctrl, &regs->cr);
- ret = fti2c010_wait(stat);
+ ret = fti2c010_wait(chip, stat);
if (ret)
break;
buf[pos] = (uchar)(readl(&regs->dr) & 0xFF);
@@ -210,39 +257,24 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
return ret;
}
-/*
- * Read/Write interface:
- * chip: I2C chip address, range 0..127
- * addr: Memory (register) address within the chip
- * alen: Number of bytes to use for addr (typically 1, 2 for larger
- * memories, 0 for register type devices with only one
- * register)
- * buffer: Where to read/write the data
- * len: How many bytes to read/write
- *
- * Returns: 0 on success, not 0 on failure
- */
-int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
+static int fti2c010_write(struct i2c_adapter *adap,
+ u8 dev, uint addr, int alen, u8 *buf, int len)
{
+ struct fti2c010_chip *chip = chip_list + adap->hwadapnr;
+ struct fti2c010_regs *regs = chip->regs;
int ret, pos;
uchar paddr[4];
- struct fti2c010_regs *regs = curr->regs;
- i2c_init(0, 0);
-
- paddr[0] = (addr >> 0) & 0xFF;
- paddr[1] = (addr >> 8) & 0xFF;
- paddr[2] = (addr >> 16) & 0xFF;
- paddr[3] = (addr >> 24) & 0xFF;
+ to_i2c_addr(paddr, addr, alen);
/*
* Phase A. Set register address
*
* A.1 Select slave device (7bits Address + 1bit R/W)
*/
- writel(I2C_WR(chip), &regs->dr);
+ writel(I2C_WR(dev), &regs->dr);
writel(CR_ENABLE | CR_TBEN | CR_START, &regs->cr);
- ret = fti2c010_wait(SR_DT);
+ ret = fti2c010_wait(chip, SR_DT);
if (ret)
return ret;
@@ -252,7 +284,7 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
writel(paddr[pos], &regs->dr);
writel(ctrl, &regs->cr);
- ret = fti2c010_wait(SR_DT);
+ ret = fti2c010_wait(chip, SR_DT);
if (ret)
return ret;
}
@@ -267,7 +299,7 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
ctrl |= CR_STOP;
writel(buf[pos], &regs->dr);
writel(ctrl, &regs->cr);
- ret = fti2c010_wait(SR_DT);
+ ret = fti2c010_wait(chip, SR_DT);
if (ret)
break;
}
@@ -275,94 +307,40 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
return ret;
}
-/*
- * Functions for setting the current I2C bus and its speed
- */
-#ifdef CONFIG_I2C_MULTI_BUS
-
-/*
- * i2c_set_bus_num:
- *
- * Change the active I2C bus. Subsequent read/write calls will
- * go to this one.
- *
- * bus - bus index, zero based
- *
- * Returns: 0 on success, not 0 on failure
- */
-int i2c_set_bus_num(uint bus)
-{
- if (bus >= ARRAY_SIZE(chip_list))
- return -1;
- curr = chip_list + bus;
- i2c_init(0, 0);
- return 0;
-}
-
-/*
- * i2c_get_bus_num:
- *
- * Returns index of currently active I2C bus. Zero-based.
- */
-
-uint i2c_get_bus_num(void)
-{
- return curr->bus;
-}
-
-#endif /* #ifdef CONFIG_I2C_MULTI_BUS */
-
-/*
- * i2c_set_bus_speed:
- *
- * Change the speed of the active I2C bus
- *
- * speed - bus speed in Hz
- *
- * Returns: 0 on success, not 0 on failure
- */
-int i2c_set_bus_speed(uint speed)
+static unsigned int fti2c010_set_bus_speed(struct i2c_adapter *adap,
+ unsigned int speed)
{
- struct fti2c010_regs *regs = curr->regs;
- uint clk = CONFIG_FTI2C010_FREQ;
- uint gsr = 0, tsr = 32;
- uint spd, div;
-
- if (!speed)
- speed = CONFIG_SYS_I2C_SPEED;
-
- for (div = 0; div < 0x3ffff; ++div) {
- /* SCLout = PCLK/(2*(COUNT + 2) + GSR) */
- spd = clk / (2 * (div + 2) + gsr);
- if (spd <= speed)
- break;
- }
-
- if (curr->speed == spd)
- return 0;
-
- writel(CR_I2CRST, &regs->cr);
- mdelay(100);
- if (readl(&regs->cr) & CR_I2CRST) {
- printf("fti2c010: reset timeout\n");
- return -1;
- }
+ struct fti2c010_chip *chip = chip_list + adap->hwadapnr;
+ int ret;
- curr->speed = spd;
+ fti2c010_reset(chip);
+ ret = set_i2c_bus_speed(chip, speed);
- writel(TGSR_GSR(gsr) | TGSR_TSR(tsr), &regs->tgsr);
- writel(CDR_DIV(div), &regs->cdr);
-
- return 0;
+ return ret;
}
/*
- * i2c_get_bus_speed:
- *
- * Returns speed of currently active I2C bus in Hz
+ * Register i2c adapters
*/
-
-uint i2c_get_bus_speed(void)
-{
- return curr->speed;
-}
+U_BOOT_I2C_ADAP_COMPLETE(i2c_0, fti2c010_init, fti2c010_probe, fti2c010_read,
+ fti2c010_write, fti2c010_set_bus_speed,
+ CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
+ 0)
+#ifdef CONFIG_FTI2C010_BASE1
+U_BOOT_I2C_ADAP_COMPLETE(i2c_1, fti2c010_init, fti2c010_probe, fti2c010_read,
+ fti2c010_write, fti2c010_set_bus_speed,
+ CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
+ 1)
+#endif
+#ifdef CONFIG_FTI2C010_BASE2
+U_BOOT_I2C_ADAP_COMPLETE(i2c_2, fti2c010_init, fti2c010_probe, fti2c010_read,
+ fti2c010_write, fti2c010_set_bus_speed,
+ CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
+ 2)
+#endif
+#ifdef CONFIG_FTI2C010_BASE3
+U_BOOT_I2C_ADAP_COMPLETE(i2c_3, fti2c010_init, fti2c010_probe, fti2c010_read,
+ fti2c010_write, fti2c010_set_bus_speed,
+ CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
+ 3)
+#endif
diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c
index 3d38c035b67..c7840049b11 100644
--- a/drivers/i2c/omap24xx_i2c.c
+++ b/drivers/i2c/omap24xx_i2c.c
@@ -158,7 +158,6 @@ static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
udelay(1000);
flush_fifo(adap);
writew(0xFFFF, &i2c_base->stat);
- writew(0, &i2c_base->cnt);
}
static void flush_fifo(struct i2c_adapter *adap)
@@ -198,8 +197,6 @@ static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip)
return res;
/* No data transfer, slave addr only */
- writew(0, &i2c_base->cnt);
- /* Set slave address */
writew(chip, &i2c_base->sa);
/* Stop bit needed here */
writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
@@ -234,7 +231,6 @@ static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip)
pr_exit:
flush_fifo(adap);
writew(0xFFFF, &i2c_base->stat);
- writew(0, &i2c_base->cnt);
return res;
}
@@ -372,7 +368,6 @@ static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
rd_exit:
flush_fifo(adap);
writew(0xFFFF, &i2c_base->stat);
- writew(0, &i2c_base->cnt);
return i2c_error;
}
@@ -473,7 +468,6 @@ static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
wr_exit:
flush_fifo(adap);
writew(0xFFFF, &i2c_base->stat);
- writew(0, &i2c_base->cnt);
return i2c_error;
}
diff --git a/drivers/i2c/s3c24x0_i2c.c b/drivers/i2c/s3c24x0_i2c.c
index f77a9d1a1ff..fd328f05494 100644
--- a/drivers/i2c/s3c24x0_i2c.c
+++ b/drivers/i2c/s3c24x0_i2c.c
@@ -23,8 +23,6 @@
#include <i2c.h>
#include "s3c24x0_i2c.h"
-#ifdef CONFIG_HARD_I2C
-
#define I2C_WRITE 0
#define I2C_READ 1
@@ -127,7 +125,6 @@
* For SPL boot some boards need i2c before SDRAM is initialised so force
* variables to live in SRAM
*/
-static unsigned int g_current_bus __attribute__((section(".data")));
static struct s3c24x0_i2c_bus i2c_bus[CONFIG_MAX_I2C_NUM]
__attribute__((section(".data")));
@@ -254,17 +251,17 @@ static void ReadWriteByte(struct s3c24x0_i2c *i2c)
writel(readl(&i2c->iiccon) & ~I2CCON_IRPND, &i2c->iiccon);
}
-static struct s3c24x0_i2c *get_base_i2c(void)
+static struct s3c24x0_i2c *get_base_i2c(int bus)
{
#ifdef CONFIG_EXYNOS4
struct s3c24x0_i2c *i2c = (struct s3c24x0_i2c *)(samsung_get_base_i2c()
+ (EXYNOS4_I2C_SPACING
- * g_current_bus));
+ * bus));
return i2c;
#elif defined CONFIG_EXYNOS5
struct s3c24x0_i2c *i2c = (struct s3c24x0_i2c *)(samsung_get_base_i2c()
+ (EXYNOS5_I2C_SPACING
- * g_current_bus));
+ * bus));
return i2c;
#else
return s3c24x0_get_base_i2c();
@@ -298,7 +295,6 @@ static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd)
writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat);
}
-#ifdef CONFIG_I2C_MULTI_BUS
static int hsi2c_get_clk_details(struct s3c24x0_i2c_bus *i2c_bus)
{
struct exynos5_hsi2c *hsregs = i2c_bus->hsregs;
@@ -307,8 +303,10 @@ static int hsi2c_get_clk_details(struct s3c24x0_i2c_bus *i2c_bus)
unsigned int i = 0, utemp0 = 0, utemp1 = 0;
unsigned int t_ftl_cycle;
-#if defined CONFIG_EXYNOS5
+#if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
clkin = get_i2c_clk();
+#else
+ clkin = get_PCLK();
#endif
/* FPCLK / FI2C =
* (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + 2 * FLT_CYCLE
@@ -330,7 +328,6 @@ static int hsi2c_get_clk_details(struct s3c24x0_i2c_bus *i2c_bus)
}
return -1;
}
-#endif
static void hsi2c_ch_init(struct s3c24x0_i2c_bus *i2c_bus)
{
@@ -401,49 +398,18 @@ static void exynos5_i2c_reset(struct s3c24x0_i2c_bus *i2c_bus)
hsi2c_ch_init(i2c_bus);
}
-/*
- * MULTI BUS I2C support
- */
-
-#ifdef CONFIG_I2C_MULTI_BUS
-int i2c_set_bus_num(unsigned int bus)
-{
- struct s3c24x0_i2c_bus *i2c_bus;
-
- i2c_bus = get_bus(bus);
- if (!i2c_bus)
- return -1;
- g_current_bus = bus;
-
- if (i2c_bus->is_highspeed) {
- if (hsi2c_get_clk_details(i2c_bus))
- return -1;
- hsi2c_ch_init(i2c_bus);
- } else {
- i2c_ch_init(i2c_bus->regs, i2c_bus->clock_frequency,
- CONFIG_SYS_I2C_SLAVE);
- }
-
- return 0;
-}
-
-unsigned int i2c_get_bus_num(void)
-{
- return g_current_bus;
-}
-#endif
-
-void i2c_init(int speed, int slaveadd)
+static void s3c24x0_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
{
struct s3c24x0_i2c *i2c;
+ struct s3c24x0_i2c_bus *bus;
+
#if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
#endif
ulong start_time = get_timer(0);
/* By default i2c channel 0 is the current bus */
- g_current_bus = 0;
- i2c = get_base_i2c();
+ i2c = get_base_i2c(adap->hwadapnr);
/*
* In case the previous transfer is still going, wait to give it a
@@ -505,6 +471,10 @@ void i2c_init(int speed, int slaveadd)
}
#endif /* #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) */
i2c_ch_init(i2c, speed, slaveadd);
+
+ bus = &i2c_bus[adap->hwadapnr];
+ bus->active = true;
+ bus->regs = i2c;
}
/*
@@ -728,6 +698,40 @@ static int hsi2c_read(struct exynos5_hsi2c *i2c,
return rv;
}
+static unsigned int s3c24x0_i2c_set_bus_speed(struct i2c_adapter *adap,
+ unsigned int speed)
+{
+ struct s3c24x0_i2c_bus *i2c_bus;
+
+ i2c_bus = get_bus(adap->hwadapnr);
+ if (!i2c_bus)
+ return -1;
+
+ i2c_bus->clock_frequency = speed;
+
+ if (i2c_bus->is_highspeed) {
+ if (hsi2c_get_clk_details(i2c_bus))
+ return -1;
+ hsi2c_ch_init(i2c_bus);
+ } else {
+ i2c_ch_init(i2c_bus->regs, i2c_bus->clock_frequency,
+ CONFIG_SYS_I2C_S3C24X0_SLAVE);
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_EXYNOS5
+static void exynos_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
+{
+ /* This will override the speed selected in the fdt for that port */
+ debug("i2c_init(speed=%u, slaveaddr=0x%x)\n", speed, slaveaddr);
+ if (i2c_set_bus_speed(speed))
+ printf("i2c_init: failed to init bus %d for speed = %d\n",
+ adap->hwadapnr, speed);
+}
+#endif
+
/*
* cmd_type is 0 for write, 1 for read.
*
@@ -840,13 +844,13 @@ bailout:
return result;
}
-int i2c_probe(uchar chip)
+static int s3c24x0_i2c_probe(struct i2c_adapter *adap, uchar chip)
{
struct s3c24x0_i2c_bus *i2c_bus;
uchar buf[1];
int ret;
- i2c_bus = get_bus(g_current_bus);
+ i2c_bus = get_bus(adap->hwadapnr);
if (!i2c_bus)
return -1;
buf[0] = 0;
@@ -864,11 +868,11 @@ int i2c_probe(uchar chip)
I2C_READ, chip << 1, 0, 0, buf, 1);
}
-
return ret != I2C_OK;
}
-int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
+static int s3c24x0_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
+ int alen, uchar *buffer, int len)
{
struct s3c24x0_i2c_bus *i2c_bus;
uchar xaddr[4];
@@ -902,7 +906,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
chip |= ((addr >> (alen * 8)) &
CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
#endif
- i2c_bus = get_bus(g_current_bus);
+ i2c_bus = get_bus(adap->hwadapnr);
if (!i2c_bus)
return -1;
@@ -922,7 +926,8 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
return 0;
}
-int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
+static int s3c24x0_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
+ int alen, uchar *buffer, int len)
{
struct s3c24x0_i2c_bus *i2c_bus;
uchar xaddr[4];
@@ -955,7 +960,7 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
chip |= ((addr >> (alen * 8)) &
CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
#endif
- i2c_bus = get_bus(g_current_bus);
+ i2c_bus = get_bus(adap->hwadapnr);
if (!i2c_bus)
return -1;
@@ -1001,8 +1006,8 @@ static void process_nodes(const void *blob, int node_list[], int count,
bus->id = pinmux_decode_periph_id(blob, node);
bus->clock_frequency = fdtdec_get_int(blob, node,
- "clock-frequency",
- CONFIG_SYS_I2C_SPEED);
+ "clock-frequency",
+ CONFIG_SYS_I2C_S3C24X0_SPEED);
bus->node = node;
bus->bus_num = i;
exynos_pinmux_config(bus->id, 0);
@@ -1044,7 +1049,6 @@ int i2c_get_bus_num_fdt(int node)
return -1;
}
-#ifdef CONFIG_I2C_MULTI_BUS
int i2c_reset_port_fdt(const void *blob, int node)
{
struct s3c24x0_i2c_bus *i2c_bus;
@@ -1068,12 +1072,178 @@ int i2c_reset_port_fdt(const void *blob, int node)
hsi2c_ch_init(i2c_bus);
} else {
i2c_ch_init(i2c_bus->regs, i2c_bus->clock_frequency,
- CONFIG_SYS_I2C_SLAVE);
+ CONFIG_SYS_I2C_S3C24X0_SLAVE);
}
return 0;
}
#endif
-#endif
-#endif /* CONFIG_HARD_I2C */
+/*
+ * Register s3c24x0 i2c adapters
+ */
+#if defined(CONFIG_EXYNOS5420)
+U_BOOT_I2C_ADAP_COMPLETE(i2c00, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+ s3c24x0_i2c_read, s3c24x0_i2c_write,
+ s3c24x0_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_S3C24X0_SPEED,
+ CONFIG_SYS_I2C_S3C24X0_SLAVE, 0)
+U_BOOT_I2C_ADAP_COMPLETE(i2c01, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+ s3c24x0_i2c_read, s3c24x0_i2c_write,
+ s3c24x0_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_S3C24X0_SPEED,
+ CONFIG_SYS_I2C_S3C24X0_SLAVE, 1)
+U_BOOT_I2C_ADAP_COMPLETE(i2c02, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+ s3c24x0_i2c_read, s3c24x0_i2c_write,
+ s3c24x0_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_S3C24X0_SPEED,
+ CONFIG_SYS_I2C_S3C24X0_SLAVE, 2)
+U_BOOT_I2C_ADAP_COMPLETE(i2c03, exynos_i2c_init, s3c24x0_i2c_probe,
+ s3c24x0_i2c_read, s3c24x0_i2c_write,
+ s3c24x0_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_S3C24X0_SPEED,
+ CONFIG_SYS_I2C_S3C24X0_SLAVE, 3)
+U_BOOT_I2C_ADAP_COMPLETE(i2c04, exynos_i2c_init, s3c24x0_i2c_probe,
+ s3c24x0_i2c_read, s3c24x0_i2c_write,
+ s3c24x0_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_S3C24X0_SPEED,
+ CONFIG_SYS_I2C_S3C24X0_SLAVE, 4)
+U_BOOT_I2C_ADAP_COMPLETE(i2c05, exynos_i2c_init, s3c24x0_i2c_probe,
+ s3c24x0_i2c_read, s3c24x0_i2c_write,
+ s3c24x0_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_S3C24X0_SPEED,
+ CONFIG_SYS_I2C_S3C24X0_SLAVE, 5)
+U_BOOT_I2C_ADAP_COMPLETE(i2c06, exynos_i2c_init, s3c24x0_i2c_probe,
+ s3c24x0_i2c_read, s3c24x0_i2c_write,
+ s3c24x0_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_S3C24X0_SPEED,
+ CONFIG_SYS_I2C_S3C24X0_SLAVE, 6)
+U_BOOT_I2C_ADAP_COMPLETE(i2c07, exynos_i2c_init, s3c24x0_i2c_probe,
+ s3c24x0_i2c_read, s3c24x0_i2c_write,
+ s3c24x0_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_S3C24X0_SPEED,
+ CONFIG_SYS_I2C_S3C24X0_SLAVE, 7)
+U_BOOT_I2C_ADAP_COMPLETE(i2c08, exynos_i2c_init, s3c24x0_i2c_probe,
+ s3c24x0_i2c_read, s3c24x0_i2c_write,
+ s3c24x0_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_S3C24X0_SPEED,
+ CONFIG_SYS_I2C_S3C24X0_SLAVE, 8)
+U_BOOT_I2C_ADAP_COMPLETE(i2c09, exynos_i2c_init, s3c24x0_i2c_probe,
+ s3c24x0_i2c_read, s3c24x0_i2c_write,
+ s3c24x0_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_S3C24X0_SPEED,
+ CONFIG_SYS_I2C_S3C24X0_SLAVE, 9)
+U_BOOT_I2C_ADAP_COMPLETE(i2c10, exynos_i2c_init, s3c24x0_i2c_probe,
+ s3c24x0_i2c_read, s3c24x0_i2c_write,
+ s3c24x0_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_S3C24X0_SPEED,
+ CONFIG_SYS_I2C_S3C24X0_SLAVE, 10)
+#elif defined(CONFIG_EXYNOS5250)
+U_BOOT_I2C_ADAP_COMPLETE(i2c00, exynos_i2c_init, s3c24x0_i2c_probe,
+ s3c24x0_i2c_read, s3c24x0_i2c_write,
+ s3c24x0_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_S3C24X0_SPEED,
+ CONFIG_SYS_I2C_S3C24X0_SLAVE, 0)
+U_BOOT_I2C_ADAP_COMPLETE(i2c01, exynos_i2c_init, s3c24x0_i2c_probe,
+ s3c24x0_i2c_read, s3c24x0_i2c_write,
+ s3c24x0_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_S3C24X0_SPEED,
+ CONFIG_SYS_I2C_S3C24X0_SLAVE, 1)
+U_BOOT_I2C_ADAP_COMPLETE(i2c02, exynos_i2c_init, s3c24x0_i2c_probe,
+ s3c24x0_i2c_read, s3c24x0_i2c_write,
+ s3c24x0_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_S3C24X0_SPEED,
+ CONFIG_SYS_I2C_S3C24X0_SLAVE, 2)
+U_BOOT_I2C_ADAP_COMPLETE(i2c03, exynos_i2c_init, s3c24x0_i2c_probe,
+ s3c24x0_i2c_read, s3c24x0_i2c_write,
+ s3c24x0_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_S3C24X0_SPEED,
+ CONFIG_SYS_I2C_S3C24X0_SLAVE, 3)
+U_BOOT_I2C_ADAP_COMPLETE(i2c04, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+ s3c24x0_i2c_read, s3c24x0_i2c_write,
+ s3c24x0_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_S3C24X0_SPEED,
+ CONFIG_SYS_I2C_S3C24X0_SLAVE, 4)
+U_BOOT_I2C_ADAP_COMPLETE(i2c05, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+ s3c24x0_i2c_read, s3c24x0_i2c_write,
+ s3c24x0_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_S3C24X0_SPEED,
+ CONFIG_SYS_I2C_S3C24X0_SLAVE, 5)
+U_BOOT_I2C_ADAP_COMPLETE(i2c06, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+ s3c24x0_i2c_read, s3c24x0_i2c_write,
+ s3c24x0_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_S3C24X0_SPEED,
+ CONFIG_SYS_I2C_S3C24X0_SLAVE, 6)
+U_BOOT_I2C_ADAP_COMPLETE(i2c07, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+ s3c24x0_i2c_read, s3c24x0_i2c_write,
+ s3c24x0_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_S3C24X0_SPEED,
+ CONFIG_SYS_I2C_S3C24X0_SLAVE, 7)
+U_BOOT_I2C_ADAP_COMPLETE(i2c08, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+ s3c24x0_i2c_read, s3c24x0_i2c_write,
+ s3c24x0_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_S3C24X0_SPEED,
+ CONFIG_SYS_I2C_S3C24X0_SLAVE, 8)
+U_BOOT_I2C_ADAP_COMPLETE(i2c09, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+ s3c24x0_i2c_read, s3c24x0_i2c_write,
+ s3c24x0_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_S3C24X0_SPEED,
+ CONFIG_SYS_I2C_S3C24X0_SLAVE, 9)
+U_BOOT_I2C_ADAP_COMPLETE(s3c10, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+ s3c24x0_i2c_read, s3c24x0_i2c_write,
+ s3c24x0_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_S3C24X0_SPEED,
+ CONFIG_SYS_I2C_S3C24X0_SLAVE, 10)
+#elif defined(CONFIG_EXYNOS4)
+U_BOOT_I2C_ADAP_COMPLETE(i2c00, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+ s3c24x0_i2c_read, s3c24x0_i2c_write,
+ s3c24x0_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_S3C24X0_SPEED,
+ CONFIG_SYS_I2C_S3C24X0_SLAVE, 0)
+U_BOOT_I2C_ADAP_COMPLETE(i2c01, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+ s3c24x0_i2c_read, s3c24x0_i2c_write,
+ s3c24x0_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_S3C24X0_SPEED,
+ CONFIG_SYS_I2C_S3C24X0_SLAVE, 1)
+U_BOOT_I2C_ADAP_COMPLETE(i2c02, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+ s3c24x0_i2c_read, s3c24x0_i2c_write,
+ s3c24x0_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_S3C24X0_SPEED,
+ CONFIG_SYS_I2C_S3C24X0_SLAVE, 2)
+U_BOOT_I2C_ADAP_COMPLETE(i2c03, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+ s3c24x0_i2c_read, s3c24x0_i2c_write,
+ s3c24x0_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_S3C24X0_SPEED,
+ CONFIG_SYS_I2C_S3C24X0_SLAVE, 3)
+U_BOOT_I2C_ADAP_COMPLETE(i2c04, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+ s3c24x0_i2c_read, s3c24x0_i2c_write,
+ s3c24x0_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_S3C24X0_SPEED,
+ CONFIG_SYS_I2C_S3C24X0_SLAVE, 4)
+U_BOOT_I2C_ADAP_COMPLETE(i2c05, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+ s3c24x0_i2c_read, s3c24x0_i2c_write,
+ s3c24x0_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_S3C24X0_SPEED,
+ CONFIG_SYS_I2C_S3C24X0_SLAVE, 5)
+U_BOOT_I2C_ADAP_COMPLETE(i2c06, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+ s3c24x0_i2c_read, s3c24x0_i2c_write,
+ s3c24x0_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_S3C24X0_SPEED,
+ CONFIG_SYS_I2C_S3C24X0_SLAVE, 6)
+U_BOOT_I2C_ADAP_COMPLETE(i2c07, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+ s3c24x0_i2c_read, s3c24x0_i2c_write,
+ s3c24x0_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_S3C24X0_SPEED,
+ CONFIG_SYS_I2C_S3C24X0_SLAVE, 7)
+U_BOOT_I2C_ADAP_COMPLETE(i2c08, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+ s3c24x0_i2c_read, s3c24x0_i2c_write,
+ s3c24x0_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_S3C24X0_SPEED,
+ CONFIG_SYS_I2C_S3C24X0_SLAVE, 8)
+#else
+U_BOOT_I2C_ADAP_COMPLETE(s3c0, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+ s3c24x0_i2c_read, s3c24x0_i2c_write,
+ s3c24x0_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_S3C24X0_SPEED,
+ CONFIG_SYS_I2C_S3C24X0_SLAVE, 0)
+#endif
diff --git a/drivers/misc/cros_ec_spi.c b/drivers/misc/cros_ec_spi.c
index 202acf258b8..2fc911025ee 100644
--- a/drivers/misc/cros_ec_spi.c
+++ b/drivers/misc/cros_ec_spi.c
@@ -135,8 +135,7 @@ int cros_ec_spi_decode_fdt(struct cros_ec_dev *dev, const void *blob)
*/
int cros_ec_spi_init(struct cros_ec_dev *dev, const void *blob)
{
- dev->spi = spi_setup_slave_fdt(blob, dev->parent_node,
- dev->cs, dev->max_frequency, 0);
+ dev->spi = spi_setup_slave_fdt(blob, dev->parent_node, dev->node);
if (!dev->spi) {
debug("%s: Could not setup SPI slave\n", __func__);
return -1;
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index a7ae38dadcb..1ed26cab34f 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_BFIN_SDH) += bfin_sdh.o
obj-$(CONFIG_DAVINCI_MMC) += davinci_mmc.o
obj-$(CONFIG_FSL_ESDHC) += fsl_esdhc.o
obj-$(CONFIG_FTSDC010) += ftsdc010_mci.o
+obj-$(CONFIG_FTSDC021) += ftsdc021_sdhci.o
obj-$(CONFIG_GENERIC_MMC) += mmc.o
obj-$(CONFIG_GENERIC_ATMEL_MCI) += gen_atmel_mci.o
obj-$(CONFIG_MMC_SPI) += mmc_spi.o
diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
index 1e0f72bbe7d..19d9b0b899c 100644
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -11,7 +11,6 @@
#include <mmc.h>
#include <dwmmc.h>
#include <asm-generic/errno.h>
-#include <asm/arch/dwmmc.h>
#define PAGE_SIZE 4096
@@ -300,17 +299,9 @@ static void dwmci_set_ios(struct mmc *mmc)
static int dwmci_init(struct mmc *mmc)
{
struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
- u32 fifo_size;
-
- if (host->quirks & DWMCI_QUIRK_DISABLE_SMU) {
- dwmci_writel(host, EMMCP_MPSBEGIN0, 0);
- dwmci_writel(host, EMMCP_SEND0, 0);
- dwmci_writel(host, EMMCP_CTRL0,
- MPSCTRL_SECURE_READ_BIT |
- MPSCTRL_SECURE_WRITE_BIT |
- MPSCTRL_NON_SECURE_READ_BIT |
- MPSCTRL_NON_SECURE_WRITE_BIT | MPSCTRL_VALID);
- }
+
+ if (host->board_init)
+ host->board_init(host);
dwmci_writel(host, DWMCI_PWREN, 1);
@@ -330,13 +321,9 @@ static int dwmci_init(struct mmc *mmc)
dwmci_writel(host, DWMCI_IDINTEN, 0);
dwmci_writel(host, DWMCI_BMOD, 1);
- if (!host->fifoth_val) {
- fifo_size = dwmci_readl(host, DWMCI_FIFOTH);
- fifo_size = ((fifo_size & RX_WMARK_MASK) >> RX_WMARK_SHIFT) + 1;
- host->fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size / 2 - 1) |
- TX_WMARK(fifo_size / 2);
+ if (host->fifoth_val) {
+ dwmci_writel(host, DWMCI_FIFOTH, host->fifoth_val);
}
- dwmci_writel(host, DWMCI_FIFOTH, host->fifoth_val);
dwmci_writel(host, DWMCI_CLKENA, 0);
dwmci_writel(host, DWMCI_CLKSRC, 0);
diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c
index a0f1511cb6f..b3e5c5e5e09 100644
--- a/drivers/mmc/exynos_dw_mmc.c
+++ b/drivers/mmc/exynos_dw_mmc.c
@@ -34,6 +34,19 @@ unsigned int exynos_dwmci_get_clk(int dev_index)
return get_mmc_clk(dev_index);
}
+static void exynos_dwmci_board_init(struct dwmci_host *host)
+{
+ if (host->quirks & DWMCI_QUIRK_DISABLE_SMU) {
+ dwmci_writel(host, EMMCP_MPSBEGIN0, 0);
+ dwmci_writel(host, EMMCP_SEND0, 0);
+ dwmci_writel(host, EMMCP_CTRL0,
+ MPSCTRL_SECURE_READ_BIT |
+ MPSCTRL_SECURE_WRITE_BIT |
+ MPSCTRL_NON_SECURE_READ_BIT |
+ MPSCTRL_NON_SECURE_WRITE_BIT | MPSCTRL_VALID);
+ }
+}
+
/*
* This function adds the mmc channel to be registered with mmc core.
* index - mmc channel number.
@@ -65,6 +78,7 @@ int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel)
#ifdef CONFIG_EXYNOS5420
host->quirks = DWMCI_QUIRK_DISABLE_SMU;
#endif
+ host->board_init = exynos_dwmci_board_init;
if (clksel) {
host->clksel_val = clksel;
diff --git a/drivers/mmc/fsl_esdhc_spl.c b/drivers/mmc/fsl_esdhc_spl.c
index 65c52a22db7..8fc263f4f40 100644
--- a/drivers/mmc/fsl_esdhc_spl.c
+++ b/drivers/mmc/fsl_esdhc_spl.c
@@ -42,6 +42,10 @@ void __noreturn mmc_boot(void)
hang();
}
+#ifdef CONFIG_FSL_CORENET
+ offset = CONFIG_SYS_MMC_U_BOOT_OFFS;
+ code_len = CONFIG_SYS_MMC_U_BOOT_SIZE;
+#else
blklen = mmc->read_bl_len;
tmp_buf = malloc(blklen);
if (!tmp_buf) {
@@ -91,6 +95,7 @@ void __noreturn mmc_boot(void)
/*
* Load U-Boot image from mmc into RAM
*/
+#endif
blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len;
blk_cnt = ALIGN(code_len, mmc->read_bl_len) / mmc->read_bl_len;
err = mmc->block_dev.block_read(0, blk_start, blk_cnt,
diff --git a/drivers/mmc/ftsdc021_sdhci.c b/drivers/mmc/ftsdc021_sdhci.c
new file mode 100644
index 00000000000..1f6cdba1734
--- /dev/null
+++ b/drivers/mmc/ftsdc021_sdhci.c
@@ -0,0 +1,33 @@
+/*
+ * (C) Copyright 2013 Faraday Technology
+ * Kuo-Jung Su <dantesu@faraday-tech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <sdhci.h>
+
+#ifndef CONFIG_FTSDC021_CLOCK
+#define CONFIG_FTSDC021_CLOCK clk_get_rate("MMC")
+#endif
+
+int ftsdc021_sdhci_init(u32 regbase)
+{
+ struct sdhci_host *host = NULL;
+ uint32_t freq = CONFIG_FTSDC021_CLOCK;
+
+ host = calloc(1, sizeof(struct sdhci_host));
+ if (!host) {
+ puts("sdh_host malloc fail!\n");
+ return 1;
+ }
+
+ host->name = "FTSDC021";
+ host->ioaddr = (void __iomem *)regbase;
+ host->quirks = 0;
+ add_sdhci(host, freq, 0);
+
+ return 0;
+}
diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile
index 1bbeb7da3b8..26483a23f79 100644
--- a/drivers/mtd/spi/Makefile
+++ b/drivers/mtd/spi/Makefile
@@ -13,4 +13,5 @@ endif
obj-$(CONFIG_CMD_SF) += sf.o
obj-$(CONFIG_SPI_FLASH) += sf_probe.o sf_ops.o
obj-$(CONFIG_SPI_FRAM_RAMTRON) += ramtron.o
+obj-$(CONFIG_SPI_FLASH_SANDBOX) += sandbox.o
obj-$(CONFIG_SPI_M95XXX) += eeprom_m95xxx.o
diff --git a/drivers/mtd/spi/fsl_espi_spl.c b/drivers/mtd/spi/fsl_espi_spl.c
index 6263d8c2217..e5ac79b9520 100644
--- a/drivers/mtd/spi/fsl_espi_spl.c
+++ b/drivers/mtd/spi/fsl_espi_spl.c
@@ -31,6 +31,10 @@ void spi_boot(void)
hang();
}
+#ifdef CONFIG_FSL_CORENET
+ offset = CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS;
+ code_len = CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE;
+#else
/*
* Load U-Boot image from SPI flash into RAM
*/
@@ -50,6 +54,7 @@ void spi_boot(void)
code_len = *(u32 *)(buf + ESPI_BOOT_IMAGE_SIZE);
/* Skip spl code */
code_len = code_len - CONFIG_SPL_MAX_SIZE;
+#endif
/* copy code to DDR */
spi_flash_read(flash, offset, code_len,
(void *)CONFIG_SYS_SPI_FLASH_U_BOOT_DST);
diff --git a/drivers/mtd/spi/sandbox.c b/drivers/mtd/spi/sandbox.c
new file mode 100644
index 00000000000..a62ef4cbbd3
--- /dev/null
+++ b/drivers/mtd/spi/sandbox.c
@@ -0,0 +1,483 @@
+/*
+ * Simulate a SPI flash
+ *
+ * Copyright (c) 2011-2013 The Chromium OS Authors.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <spi.h>
+#include <os.h>
+
+#include <spi_flash.h>
+#include "sf_internal.h"
+
+#include <asm/getopt.h>
+#include <asm/spi.h>
+#include <asm/state.h>
+
+/*
+ * The different states that our SPI flash transitions between.
+ * We need to keep track of this across multiple xfer calls since
+ * the SPI bus could possibly call down into us multiple times.
+ */
+enum sandbox_sf_state {
+ SF_CMD, /* default state -- we're awaiting a command */
+ SF_ID, /* read the flash's (jedec) ID code */
+ SF_ADDR, /* processing the offset in the flash to read/etc... */
+ SF_READ, /* reading data from the flash */
+ SF_WRITE, /* writing data to the flash, i.e. page programming */
+ SF_ERASE, /* erase the flash */
+ SF_READ_STATUS, /* read the flash's status register */
+ SF_READ_STATUS1, /* read the flash's status register upper 8 bits*/
+};
+
+static const char *sandbox_sf_state_name(enum sandbox_sf_state state)
+{
+ static const char * const states[] = {
+ "CMD", "ID", "ADDR", "READ", "WRITE", "ERASE", "READ_STATUS",
+ };
+ return states[state];
+}
+
+/* Bits for the status register */
+#define STAT_WIP (1 << 0)
+#define STAT_WEL (1 << 1)
+
+/* Assume all SPI flashes have 3 byte addresses since they do atm */
+#define SF_ADDR_LEN 3
+
+struct sandbox_spi_flash_erase_commands {
+ u8 cmd;
+ u32 size;
+};
+#define IDCODE_LEN 5
+#define MAX_ERASE_CMDS 3
+struct sandbox_spi_flash_data {
+ const char *name;
+ u8 idcode[IDCODE_LEN];
+ u32 size;
+ const struct sandbox_spi_flash_erase_commands
+ erase_cmds[MAX_ERASE_CMDS];
+};
+
+/* Structure describing all the flashes we know how to emulate */
+static const struct sandbox_spi_flash_data sandbox_sf_flashes[] = {
+ {
+ "M25P16", { 0x20, 0x20, 0x15 }, (2 << 20),
+ { /* erase commands */
+ { 0xd8, (64 << 10), }, /* sector */
+ { 0xc7, (2 << 20), }, /* bulk */
+ },
+ },
+ {
+ "W25Q32", { 0xef, 0x40, 0x16 }, (4 << 20),
+ { /* erase commands */
+ { 0x20, (4 << 10), }, /* 4KB */
+ { 0xd8, (64 << 10), }, /* sector */
+ { 0xc7, (4 << 20), }, /* bulk */
+ },
+ },
+ {
+ "W25Q128", { 0xef, 0x40, 0x18 }, (16 << 20),
+ { /* erase commands */
+ { 0x20, (4 << 10), }, /* 4KB */
+ { 0xd8, (64 << 10), }, /* sector */
+ { 0xc7, (16 << 20), }, /* bulk */
+ },
+ },
+};
+
+/* Used to quickly bulk erase backing store */
+static u8 sandbox_sf_0xff[0x1000];
+
+/* Internal state data for each SPI flash */
+struct sandbox_spi_flash {
+ /*
+ * As we receive data over the SPI bus, our flash transitions
+ * between states. For example, we start off in the SF_CMD
+ * state where the first byte tells us what operation to perform
+ * (such as read or write the flash). But the operation itself
+ * can go through a few states such as first reading in the
+ * offset in the flash to perform the requested operation.
+ * Thus "state" stores the exact state that our machine is in
+ * while "cmd" stores the overall command we're processing.
+ */
+ enum sandbox_sf_state state;
+ uint cmd;
+ const void *cmd_data;
+ /* Current position in the flash; used when reading/writing/etc... */
+ uint off;
+ /* How many address bytes we've consumed */
+ uint addr_bytes, pad_addr_bytes;
+ /* The current flash status (see STAT_XXX defines above) */
+ u16 status;
+ /* Data describing the flash we're emulating */
+ const struct sandbox_spi_flash_data *data;
+ /* The file on disk to serv up data from */
+ int fd;
+};
+
+static int sandbox_sf_setup(void **priv, const char *spec)
+{
+ /* spec = idcode:file */
+ struct sandbox_spi_flash *sbsf;
+ const char *file;
+ size_t i, len, idname_len;
+ const struct sandbox_spi_flash_data *data;
+
+ file = strchr(spec, ':');
+ if (!file) {
+ printf("sandbox_sf: unable to parse file\n");
+ goto error;
+ }
+ idname_len = file - spec;
+ ++file;
+
+ for (i = 0; i < ARRAY_SIZE(sandbox_sf_flashes); ++i) {
+ data = &sandbox_sf_flashes[i];
+ len = strlen(data->name);
+ if (idname_len != len)
+ continue;
+ if (!memcmp(spec, data->name, len))
+ break;
+ }
+ if (i == ARRAY_SIZE(sandbox_sf_flashes)) {
+ printf("sandbox_sf: unknown flash '%*s'\n", (int)idname_len,
+ spec);
+ goto error;
+ }
+
+ if (sandbox_sf_0xff[0] == 0x00)
+ memset(sandbox_sf_0xff, 0xff, sizeof(sandbox_sf_0xff));
+
+ sbsf = calloc(sizeof(*sbsf), 1);
+ if (!sbsf) {
+ printf("sandbox_sf: out of memory\n");
+ goto error;
+ }
+
+ sbsf->fd = os_open(file, 02);
+ if (sbsf->fd == -1) {
+ free(sbsf);
+ printf("sandbox_sf: unable to open file '%s'\n", file);
+ goto error;
+ }
+
+ sbsf->data = data;
+
+ *priv = sbsf;
+ return 0;
+
+ error:
+ return 1;
+}
+
+static void sandbox_sf_free(void *priv)
+{
+ struct sandbox_spi_flash *sbsf = priv;
+
+ os_close(sbsf->fd);
+ free(sbsf);
+}
+
+static void sandbox_sf_cs_activate(void *priv)
+{
+ struct sandbox_spi_flash *sbsf = priv;
+
+ debug("sandbox_sf: CS activated; state is fresh!\n");
+
+ /* CS is asserted, so reset state */
+ sbsf->off = 0;
+ sbsf->addr_bytes = 0;
+ sbsf->pad_addr_bytes = 0;
+ sbsf->state = SF_CMD;
+ sbsf->cmd = SF_CMD;
+}
+
+static void sandbox_sf_cs_deactivate(void *priv)
+{
+ debug("sandbox_sf: CS deactivated; cmd done processing!\n");
+}
+
+/* Figure out what command this stream is telling us to do */
+static int sandbox_sf_process_cmd(struct sandbox_spi_flash *sbsf, const u8 *rx,
+ u8 *tx)
+{
+ enum sandbox_sf_state oldstate = sbsf->state;
+
+ /* We need to output a byte for the cmd byte we just ate */
+ sandbox_spi_tristate(tx, 1);
+
+ sbsf->cmd = rx[0];
+ switch (sbsf->cmd) {
+ case CMD_READ_ID:
+ sbsf->state = SF_ID;
+ sbsf->cmd = SF_ID;
+ break;
+ case CMD_READ_ARRAY_FAST:
+ sbsf->pad_addr_bytes = 1;
+ case CMD_READ_ARRAY_SLOW:
+ case CMD_PAGE_PROGRAM:
+ state_addr:
+ sbsf->state = SF_ADDR;
+ break;
+ case CMD_WRITE_DISABLE:
+ debug(" write disabled\n");
+ sbsf->status &= ~STAT_WEL;
+ break;
+ case CMD_READ_STATUS:
+ sbsf->state = SF_READ_STATUS;
+ break;
+ case CMD_READ_STATUS1:
+ sbsf->state = SF_READ_STATUS1;
+ break;
+ case CMD_WRITE_ENABLE:
+ debug(" write enabled\n");
+ sbsf->status |= STAT_WEL;
+ break;
+ default: {
+ size_t i;
+
+ /* handle erase commands first */
+ for (i = 0; i < MAX_ERASE_CMDS; ++i) {
+ const struct sandbox_spi_flash_erase_commands *
+ erase_cmd = &sbsf->data->erase_cmds[i];
+
+ if (erase_cmd->cmd == 0x00)
+ continue;
+ if (sbsf->cmd != erase_cmd->cmd)
+ continue;
+
+ sbsf->cmd_data = erase_cmd;
+ goto state_addr;
+ }
+
+ debug(" cmd unknown: %#x\n", sbsf->cmd);
+ return 1;
+ }
+ }
+
+ if (oldstate != sbsf->state)
+ debug(" cmd: transition to %s state\n",
+ sandbox_sf_state_name(sbsf->state));
+
+ return 0;
+}
+
+int sandbox_erase_part(struct sandbox_spi_flash *sbsf, int size)
+{
+ int todo;
+ int ret;
+
+ while (size > 0) {
+ todo = min(size, sizeof(sandbox_sf_0xff));
+ ret = os_write(sbsf->fd, sandbox_sf_0xff, todo);
+ if (ret != todo)
+ return ret;
+ size -= todo;
+ }
+
+ return 0;
+}
+
+static int sandbox_sf_xfer(void *priv, const u8 *rx, u8 *tx,
+ uint bytes)
+{
+ struct sandbox_spi_flash *sbsf = priv;
+ uint cnt, pos = 0;
+ int ret;
+
+ debug("sandbox_sf: state:%x(%s) bytes:%u\n", sbsf->state,
+ sandbox_sf_state_name(sbsf->state), bytes);
+
+ if (sbsf->state == SF_CMD) {
+ /* Figure out the initial state */
+ if (sandbox_sf_process_cmd(sbsf, rx, tx))
+ return 1;
+ ++pos;
+ }
+
+ /* Process the remaining data */
+ while (pos < bytes) {
+ switch (sbsf->state) {
+ case SF_ID: {
+ u8 id;
+
+ debug(" id: off:%u tx:", sbsf->off);
+ if (sbsf->off < IDCODE_LEN)
+ id = sbsf->data->idcode[sbsf->off];
+ else
+ id = 0;
+ debug("%02x\n", id);
+ tx[pos++] = id;
+ ++sbsf->off;
+ break;
+ }
+ case SF_ADDR:
+ debug(" addr: bytes:%u rx:%02x ", sbsf->addr_bytes,
+ rx[pos]);
+
+ if (sbsf->addr_bytes++ < SF_ADDR_LEN)
+ sbsf->off = (sbsf->off << 8) | rx[pos];
+ debug("addr:%06x\n", sbsf->off);
+
+ sandbox_spi_tristate(&tx[pos++], 1);
+
+ /* See if we're done processing */
+ if (sbsf->addr_bytes <
+ SF_ADDR_LEN + sbsf->pad_addr_bytes)
+ break;
+
+ /* Next state! */
+ if (os_lseek(sbsf->fd, sbsf->off, OS_SEEK_SET) < 0) {
+ puts("sandbox_sf: os_lseek() failed");
+ return 1;
+ }
+ switch (sbsf->cmd) {
+ case CMD_READ_ARRAY_FAST:
+ case CMD_READ_ARRAY_SLOW:
+ sbsf->state = SF_READ;
+ break;
+ case CMD_PAGE_PROGRAM:
+ sbsf->state = SF_WRITE;
+ break;
+ default:
+ /* assume erase state ... */
+ sbsf->state = SF_ERASE;
+ goto case_sf_erase;
+ }
+ debug(" cmd: transition to %s state\n",
+ sandbox_sf_state_name(sbsf->state));
+ break;
+ case SF_READ:
+ /*
+ * XXX: need to handle exotic behavior:
+ * - reading past end of device
+ */
+
+ cnt = bytes - pos;
+ debug(" tx: read(%u)\n", cnt);
+ ret = os_read(sbsf->fd, tx + pos, cnt);
+ if (ret < 0) {
+ puts("sandbox_spi: os_read() failed\n");
+ return 1;
+ }
+ pos += ret;
+ break;
+ case SF_READ_STATUS:
+ debug(" read status: %#x\n", sbsf->status);
+ cnt = bytes - pos;
+ memset(tx + pos, sbsf->status, cnt);
+ pos += cnt;
+ break;
+ case SF_READ_STATUS1:
+ debug(" read status: %#x\n", sbsf->status);
+ cnt = bytes - pos;
+ memset(tx + pos, sbsf->status >> 8, cnt);
+ pos += cnt;
+ break;
+ case SF_WRITE:
+ /*
+ * XXX: need to handle exotic behavior:
+ * - unaligned addresses
+ * - more than a page (256) worth of data
+ * - reading past end of device
+ */
+ if (!(sbsf->status & STAT_WEL)) {
+ puts("sandbox_sf: write enable not set before write\n");
+ goto done;
+ }
+
+ cnt = bytes - pos;
+ debug(" rx: write(%u)\n", cnt);
+ sandbox_spi_tristate(&tx[pos], cnt);
+ ret = os_write(sbsf->fd, rx + pos, cnt);
+ if (ret < 0) {
+ puts("sandbox_spi: os_write() failed\n");
+ return 1;
+ }
+ pos += ret;
+ sbsf->status &= ~STAT_WEL;
+ break;
+ case SF_ERASE:
+ case_sf_erase: {
+ const struct sandbox_spi_flash_erase_commands *
+ erase_cmd = sbsf->cmd_data;
+
+ if (!(sbsf->status & STAT_WEL)) {
+ puts("sandbox_sf: write enable not set before erase\n");
+ goto done;
+ }
+
+ /* verify address is aligned */
+ if (sbsf->off & (erase_cmd->size - 1)) {
+ debug(" sector erase: cmd:%#x needs align:%#x, but we got %#x\n",
+ erase_cmd->cmd, erase_cmd->size,
+ sbsf->off);
+ sbsf->status &= ~STAT_WEL;
+ goto done;
+ }
+
+ debug(" sector erase addr: %u\n", sbsf->off);
+
+ cnt = bytes - pos;
+ sandbox_spi_tristate(&tx[pos], cnt);
+ pos += cnt;
+
+ /*
+ * TODO(vapier@gentoo.org): latch WIP in status, and
+ * delay before clearing it ?
+ */
+ ret = sandbox_erase_part(sbsf, erase_cmd->size);
+ sbsf->status &= ~STAT_WEL;
+ if (ret) {
+ debug("sandbox_sf: Erase failed\n");
+ goto done;
+ }
+ goto done;
+ }
+ default:
+ debug(" ??? no idea what to do ???\n");
+ goto done;
+ }
+ }
+
+ done:
+ return pos == bytes ? 0 : 1;
+}
+
+static const struct sandbox_spi_emu_ops sandbox_sf_ops = {
+ .setup = sandbox_sf_setup,
+ .free = sandbox_sf_free,
+ .cs_activate = sandbox_sf_cs_activate,
+ .cs_deactivate = sandbox_sf_cs_deactivate,
+ .xfer = sandbox_sf_xfer,
+};
+
+static int sandbox_cmdline_cb_spi_sf(struct sandbox_state *state,
+ const char *arg)
+{
+ unsigned long bus, cs;
+ const char *spec = sandbox_spi_parse_spec(arg, &bus, &cs);
+
+ if (!spec)
+ return 1;
+
+ /*
+ * It is safe to not make a copy of 'spec' because it comes from the
+ * command line.
+ *
+ * TODO(sjg@chromium.org): It would be nice if we could parse the
+ * spec here, but the problem is that no U-Boot init has been done
+ * yet. Perhaps we can figure something out.
+ */
+ state->spi[bus][cs].ops = &sandbox_sf_ops;
+ state->spi[bus][cs].spec = spec;
+ return 0;
+}
+SANDBOX_CMDLINE_OPT(spi_sf, 1, "connect a SPI flash: <bus>:<cs>:<id>:<file>");
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 732ddf836df..d291746ed4a 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -28,6 +28,7 @@
#define CMD_PAGE_PROGRAM 0x02
#define CMD_WRITE_DISABLE 0x04
#define CMD_READ_STATUS 0x05
+#define CMD_READ_STATUS1 0x35
#define CMD_WRITE_ENABLE 0x06
#define CMD_READ_CONFIG 0x35
#define CMD_FLAG_STATUS 0x70
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index 5eb8ffe843e..c1eb7548983 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -13,6 +13,7 @@
#include <malloc.h>
#include <spi.h>
#include <spi_flash.h>
+#include <asm/io.h>
#include "sf_internal.h"
@@ -279,22 +280,19 @@ int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash)
debug("%s: Memory map must cover entire device\n", __func__);
return -1;
}
- flash->memory_map = (void *)addr;
+ flash->memory_map = map_sysmem(addr, size);
return 0;
}
#endif /* CONFIG_OF_CONTROL */
-struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int spi_mode)
+static struct spi_flash *spi_flash_probe_slave(struct spi_slave *spi)
{
- struct spi_slave *spi;
struct spi_flash *flash = NULL;
u8 idcode[5];
int ret;
/* Setup spi_slave */
- spi = spi_setup_slave(bus, cs, max_hz, spi_mode);
if (!spi) {
printf("SF: Failed to set up slave\n");
return NULL;
@@ -358,6 +356,26 @@ err_claim_bus:
return NULL;
}
+struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int spi_mode)
+{
+ struct spi_slave *spi;
+
+ spi = spi_setup_slave(bus, cs, max_hz, spi_mode);
+ return spi_flash_probe_slave(spi);
+}
+
+#ifdef CONFIG_OF_SPI_FLASH
+struct spi_flash *spi_flash_probe_fdt(const void *blob, int slave_node,
+ int spi_node)
+{
+ struct spi_slave *spi;
+
+ spi = spi_setup_slave_fdt(blob, slave_node, spi_node);
+ return spi_flash_probe_slave(spi);
+}
+#endif
+
void spi_flash_free(struct spi_flash *flash)
{
spi_free_slave(flash->spi);
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 27902fe394e..ed4ecd754b4 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_MXC_SPI) += mxc_spi.o
obj-$(CONFIG_MXS_SPI) += mxs_spi.o
obj-$(CONFIG_OC_TINY_SPI) += oc_tiny_spi.o
obj-$(CONFIG_OMAP3_SPI) += omap3_spi.o
+obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o
obj-$(CONFIG_SOFT_SPI) += soft_spi.o
obj-$(CONFIG_SH_SPI) += sh_spi.o
obj-$(CONFIG_FSL_ESPI) += fsl_espi.o
diff --git a/drivers/spi/bfin_spi.c b/drivers/spi/bfin_spi.c
index bb88f3008a8..aa89d89a32a 100644
--- a/drivers/spi/bfin_spi.c
+++ b/drivers/spi/bfin_spi.c
@@ -162,21 +162,22 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
if (!spi_cs_is_valid(bus, cs))
return NULL;
- if (bus >= ARRAY_SIZE(pins) || pins[bus] == NULL) {
- debug("%s: invalid bus %u\n", __func__, bus);
- return NULL;
- }
switch (bus) {
#ifdef SPI0_CTL
- case 0: mmr_base = SPI0_CTL; break;
+ case 0:
+ mmr_base = SPI0_CTL; break;
#endif
#ifdef SPI1_CTL
- case 1: mmr_base = SPI1_CTL; break;
+ case 1:
+ mmr_base = SPI1_CTL; break;
#endif
#ifdef SPI2_CTL
- case 2: mmr_base = SPI2_CTL; break;
+ case 2:
+ mmr_base = SPI2_CTL; break;
#endif
- default: return NULL;
+ default:
+ debug("%s: invalid bus %u\n", __func__, bus);
+ return NULL;
}
bss = spi_alloc_slave(struct bfin_spi_slave, bus, cs);
diff --git a/drivers/spi/bfin_spi6xx.c b/drivers/spi/bfin_spi6xx.c
index c25c4a9aeab..07b833d3a3d 100644
--- a/drivers/spi/bfin_spi6xx.c
+++ b/drivers/spi/bfin_spi6xx.c
@@ -154,10 +154,6 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
if (!spi_cs_is_valid(bus, cs))
return NULL;
- if (bus >= ARRAY_SIZE(pins) || pins[bus] == NULL) {
- debug("%s: invalid bus %u\n", __func__, bus);
- return NULL;
- }
switch (bus) {
#ifdef SPI0_REGBASE
case 0:
@@ -175,6 +171,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
break;
#endif
default:
+ debug("%s: invalid bus %u\n", __func__, bus);
return NULL;
}
diff --git a/drivers/spi/exynos_spi.c b/drivers/spi/exynos_spi.c
index 699c57eb6d9..4d5def2d319 100644
--- a/drivers/spi/exynos_spi.c
+++ b/drivers/spi/exynos_spi.c
@@ -529,18 +529,18 @@ static int process_nodes(const void *blob, int node_list[], int count)
* @param node SPI peripheral node to use
* @return 0 if ok, -1 on error
*/
-struct spi_slave *spi_setup_slave_fdt(const void *blob, int node,
- unsigned int cs, unsigned int max_hz, unsigned int mode)
+struct spi_slave *spi_setup_slave_fdt(const void *blob, int slave_node,
+ int spi_node)
{
struct spi_bus *bus;
unsigned int i;
for (i = 0, bus = spi_bus; i < bus_count; i++, bus++) {
- if (bus->node == node)
- return spi_setup_slave(i, cs, max_hz, mode);
+ if (bus->node == spi_node)
+ return spi_base_setup_slave_fdt(blob, i, slave_node);
}
- debug("%s: Failed to find bus node %d\n", __func__, node);
+ debug("%s: Failed to find bus node %d\n", __func__, spi_node);
return NULL;
}
diff --git a/drivers/spi/sandbox_spi.c b/drivers/spi/sandbox_spi.c
new file mode 100644
index 00000000000..7895305a053
--- /dev/null
+++ b/drivers/spi/sandbox_spi.c
@@ -0,0 +1,204 @@
+/*
+ * Simulate a SPI port
+ *
+ * Copyright (c) 2011-2013 The Chromium OS Authors.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <spi.h>
+#include <os.h>
+
+#include <asm/errno.h>
+#include <asm/spi.h>
+#include <asm/state.h>
+
+#ifndef CONFIG_SPI_IDLE_VAL
+# define CONFIG_SPI_IDLE_VAL 0xFF
+#endif
+
+struct sandbox_spi_slave {
+ struct spi_slave slave;
+ const struct sandbox_spi_emu_ops *ops;
+ void *priv;
+};
+
+#define to_sandbox_spi_slave(s) container_of(s, struct sandbox_spi_slave, slave)
+
+const char *sandbox_spi_parse_spec(const char *arg, unsigned long *bus,
+ unsigned long *cs)
+{
+ char *endp;
+
+ *bus = simple_strtoul(arg, &endp, 0);
+ if (*endp != ':' || *bus >= CONFIG_SANDBOX_SPI_MAX_BUS)
+ return NULL;
+
+ *cs = simple_strtoul(endp + 1, &endp, 0);
+ if (*endp != ':' || *cs >= CONFIG_SANDBOX_SPI_MAX_CS)
+ return NULL;
+
+ return endp + 1;
+}
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return bus < CONFIG_SANDBOX_SPI_MAX_BUS &&
+ cs < CONFIG_SANDBOX_SPI_MAX_CS;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ struct sandbox_spi_slave *sss = to_sandbox_spi_slave(slave);
+
+ debug("sandbox_spi: activating CS\n");
+ if (sss->ops->cs_activate)
+ sss->ops->cs_activate(sss->priv);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ struct sandbox_spi_slave *sss = to_sandbox_spi_slave(slave);
+
+ debug("sandbox_spi: deactivating CS\n");
+ if (sss->ops->cs_deactivate)
+ sss->ops->cs_deactivate(sss->priv);
+}
+
+void spi_init(void)
+{
+}
+
+void spi_set_speed(struct spi_slave *slave, uint hz)
+{
+}
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int mode)
+{
+ struct sandbox_spi_slave *sss;
+ struct sandbox_state *state = state_get_current();
+ const char *spec;
+
+ if (!spi_cs_is_valid(bus, cs)) {
+ debug("sandbox_spi: Invalid SPI bus/cs\n");
+ return NULL;
+ }
+
+ sss = spi_alloc_slave(struct sandbox_spi_slave, bus, cs);
+ if (!sss) {
+ debug("sandbox_spi: Out of memory\n");
+ return NULL;
+ }
+
+ spec = state->spi[bus][cs].spec;
+ sss->ops = state->spi[bus][cs].ops;
+ if (!spec || !sss->ops || sss->ops->setup(&sss->priv, spec)) {
+ free(sss);
+ printf("sandbox_spi: unable to locate a slave client\n");
+ return NULL;
+ }
+
+ return &sss->slave;
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+ struct sandbox_spi_slave *sss = to_sandbox_spi_slave(slave);
+
+ debug("sandbox_spi: releasing slave\n");
+
+ if (sss->ops->free)
+ sss->ops->free(sss->priv);
+
+ free(sss);
+}
+
+static int spi_bus_claim_cnt[CONFIG_SANDBOX_SPI_MAX_BUS];
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+ if (spi_bus_claim_cnt[slave->bus]++) {
+ printf("sandbox_spi: error: bus already claimed: %d!\n",
+ spi_bus_claim_cnt[slave->bus]);
+ }
+
+ return 0;
+}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+ if (--spi_bus_claim_cnt[slave->bus]) {
+ printf("sandbox_spi: error: bus freed too often: %d!\n",
+ spi_bus_claim_cnt[slave->bus]);
+ }
+}
+
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
+ void *din, unsigned long flags)
+{
+ struct sandbox_spi_slave *sss = to_sandbox_spi_slave(slave);
+ uint bytes = bitlen / 8, i;
+ int ret = 0;
+ u8 *tx = (void *)dout, *rx = din;
+
+ if (bitlen == 0)
+ goto done;
+
+ /* we can only do 8 bit transfers */
+ if (bitlen % 8) {
+ printf("sandbox_spi: xfer: invalid bitlen size %u; needs to be 8bit\n",
+ bitlen);
+ flags |= SPI_XFER_END;
+ goto done;
+ }
+
+ if (flags & SPI_XFER_BEGIN)
+ spi_cs_activate(slave);
+
+ /* make sure rx/tx buffers are full so clients can assume */
+ if (!tx) {
+ debug("sandbox_spi: xfer: auto-allocating tx scratch buffer\n");
+ tx = malloc(bytes);
+ if (!tx) {
+ debug("sandbox_spi: Out of memory\n");
+ return -ENOMEM;
+ }
+ }
+ if (!rx) {
+ debug("sandbox_spi: xfer: auto-allocating rx scratch buffer\n");
+ rx = malloc(bytes);
+ if (!rx) {
+ debug("sandbox_spi: Out of memory\n");
+ return -ENOMEM;
+ }
+ }
+
+ debug("sandbox_spi: xfer: bytes = %u\n tx:", bytes);
+ for (i = 0; i < bytes; ++i)
+ debug(" %u:%02x", i, tx[i]);
+ debug("\n");
+
+ ret = sss->ops->xfer(sss->priv, tx, rx, bytes);
+
+ debug("sandbox_spi: xfer: got back %i (that's %s)\n rx:",
+ ret, ret ? "bad" : "good");
+ for (i = 0; i < bytes; ++i)
+ debug(" %u:%02x", i, rx[i]);
+ debug("\n");
+
+ if (tx != dout)
+ free(tx);
+ if (rx != din)
+ free(rx);
+
+ done:
+ if (flags & SPI_XFER_END)
+ spi_cs_deactivate(slave);
+
+ return ret;
+}
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index b76a26cef05..7ddea9b026a 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -5,6 +5,7 @@
*/
#include <common.h>
+#include <fdtdec.h>
#include <malloc.h>
#include <spi.h>
@@ -37,3 +38,21 @@ void *spi_do_alloc_slave(int offset, int size, unsigned int bus,
return ptr;
}
+
+#ifdef CONFIG_OF_SPI
+struct spi_slave *spi_base_setup_slave_fdt(const void *blob, int busnum,
+ int node)
+{
+ int cs, max_hz, mode = 0;
+
+ cs = fdtdec_get_int(blob, node, "reg", -1);
+ max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", 100000);
+ if (fdtdec_get_bool(blob, node, "spi-cpol"))
+ mode |= SPI_CPOL;
+ if (fdtdec_get_bool(blob, node, "spi-cpha"))
+ mode |= SPI_CPHA;
+ if (fdtdec_get_bool(blob, node, "spi-cs-high"))
+ mode |= SPI_CS_HIGH;
+ return spi_setup_slave(busnum, cs, max_hz, mode);
+}
+#endif
generated by cgit v1.2.3 (git 2.0.4) at 2025-10-25 16:02:46 +0000