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-rw-r--r--drivers/ddr/imx/imx8m/ddr_init.c6
-rw-r--r--drivers/mmc/davinci_mmc.c16
-rw-r--r--drivers/mtd/spi/spi-nor-core.c6
-rw-r--r--drivers/mtd/spi/spi-nor-ids.c5
-rw-r--r--drivers/net/bcm-sf2-eth.c2
-rw-r--r--drivers/net/dwc_eth_qos.c2
-rw-r--r--drivers/phy/ti-pipe3-phy.c281
-rw-r--r--drivers/rtc/rx8010sj.c3
-rw-r--r--drivers/rtc/s35392a.c2
-rw-r--r--drivers/spi/rk_spi.c10
-rw-r--r--drivers/sysreset/Kconfig2
-rw-r--r--drivers/sysreset/Makefile2
-rw-r--r--drivers/usb/cdns3/ep0.c1
-rw-r--r--drivers/usb/dwc3/core.c12
-rw-r--r--drivers/usb/dwc3/core.h20
-rw-r--r--drivers/video/Kconfig5
-rw-r--r--drivers/video/console_normal.c125
-rw-r--r--drivers/video/console_rotate.c325
-rw-r--r--drivers/video/fonts/.gitignore1
-rw-r--r--drivers/video/vidconsole-uclass.c22
-rw-r--r--drivers/video/video-uclass.c54
21 files changed, 564 insertions, 338 deletions
diff --git a/drivers/ddr/imx/imx8m/ddr_init.c b/drivers/ddr/imx/imx8m/ddr_init.c
index d6e915c9b9c..21af66e4e7f 100644
--- a/drivers/ddr/imx/imx8m/ddr_init.c
+++ b/drivers/ddr/imx/imx8m/ddr_init.c
@@ -24,7 +24,7 @@ void ddr_init(struct dram_timing_info *dram_timing)
{
unsigned int tmp, initial_drate, target_freq;
- printf("DDRINFO: start DRAM init\n");
+ debug("DDRINFO: start DRAM init\n");
/* Step1: Follow the power up procedure */
if (is_imx8mq()) {
@@ -109,7 +109,7 @@ void ddr_init(struct dram_timing_info *dram_timing)
tmp = reg32_read(DDRPHY_CalBusy(0));
} while ((tmp & 0x1));
- printf("DDRINFO:ddrphy calibration done\n");
+ debug("DDRINFO:ddrphy calibration done\n");
/* Step15: Set SWCTL.sw_done to 0 */
reg32_write(DDRC_SWCTL(0), 0x00000000);
@@ -161,7 +161,7 @@ void ddr_init(struct dram_timing_info *dram_timing)
/* enable port 0 */
reg32_write(DDRC_PCTRL_0(0), 0x00000001);
- printf("DDRINFO: ddrmix config done\n");
+ debug("DDRINFO: ddrmix config done\n");
/* save the dram timing config into memory */
dram_config_save(dram_timing, CONFIG_SAVED_DRAM_TIMING_BASE);
diff --git a/drivers/mmc/davinci_mmc.c b/drivers/mmc/davinci_mmc.c
index c3f7b57665d..ef5cd4e7234 100644
--- a/drivers/mmc/davinci_mmc.c
+++ b/drivers/mmc/davinci_mmc.c
@@ -32,6 +32,10 @@ struct davinci_mmc_priv {
uint input_clk; /* Input clock to MMC controller */
struct gpio_desc cd_gpio; /* Card Detect GPIO */
struct gpio_desc wp_gpio; /* Write Protect GPIO */
+};
+
+struct davinci_mmc_plat
+{
struct mmc_config cfg;
struct mmc mmc;
};
@@ -480,8 +484,9 @@ int davinci_mmc_init(bd_t *bis, struct davinci_mmc *host)
static int davinci_mmc_probe(struct udevice *dev)
{
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+ struct davinci_mmc_plat *plat = dev_get_platdata(dev);
struct davinci_mmc_priv *priv = dev_get_priv(dev);
- struct mmc_config *cfg = &priv->cfg;
+ struct mmc_config *cfg = &plat->cfg;
#ifdef CONFIG_SPL_BUILD
int ret;
#endif
@@ -502,7 +507,7 @@ static int davinci_mmc_probe(struct udevice *dev)
gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
#endif
- upriv->mmc = &priv->mmc;
+ upriv->mmc = &plat->mmc;
#ifdef CONFIG_SPL_BUILD
/*
@@ -513,7 +518,7 @@ static int davinci_mmc_probe(struct udevice *dev)
* support in SPL, hence the hard-coded base register address.
*/
priv->reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE;
- ret = mmc_bind(dev, &priv->mmc, &priv->cfg);
+ ret = mmc_bind(dev, &plat->mmc, &plat->cfg);
if (ret)
return ret;
#endif
@@ -523,9 +528,9 @@ static int davinci_mmc_probe(struct udevice *dev)
static int davinci_mmc_bind(struct udevice *dev)
{
- struct davinci_mmc_priv *priv = dev_get_priv(dev);
+ struct davinci_mmc_plat *plat = dev_get_platdata(dev);
- return mmc_bind(dev, &priv->mmc, &priv->cfg);
+ return mmc_bind(dev, &plat->mmc, &plat->cfg);
}
static const struct udevice_id davinci_mmc_ids[] = {
@@ -542,6 +547,7 @@ U_BOOT_DRIVER(davinci_mmc_drv) = {
#endif
.probe = davinci_mmc_probe,
.ops = &davinci_mmc_ops,
+ .platdata_auto_alloc_size = sizeof(struct davinci_mmc_plat),
.priv_auto_alloc_size = sizeof(struct davinci_mmc_priv),
};
#endif
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 5a8c0842556..eb49a6c11c4 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -546,6 +546,9 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr,
(long long)instr->len);
+ if (!instr->len)
+ return 0;
+
div_u64_rem(instr->len, mtd->erasesize, &rem);
if (rem)
return -EINVAL;
@@ -1226,6 +1229,9 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
+ if (!len)
+ return 0;
+
for (i = 0; i < len; ) {
ssize_t written;
loff_t addr = to + i;
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index d3b84574ac4..973b6f86c94 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -108,6 +108,11 @@ const struct flash_info spi_nor_ids[] = {
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
},
{
+ INFO("gd25q128", 0xc84018, 0, 64 * 1024, 256,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
+ },
+ {
INFO("gd25lq128", 0xc86018, 0, 64 * 1024, 256,
SECT_4K | SPI_NOR_DUAL_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
diff --git a/drivers/net/bcm-sf2-eth.c b/drivers/net/bcm-sf2-eth.c
index 615037f1a3f..11f937032f3 100644
--- a/drivers/net/bcm-sf2-eth.c
+++ b/drivers/net/bcm-sf2-eth.c
@@ -50,7 +50,7 @@ static int bcm_sf2_eth_init(struct eth_device *dev)
eth->port_num = 0;
debug("Connecting PHY 0...\n");
phydev = phy_connect(miiphy_get_dev_by_name(dev->name),
- 0, dev, eth->phy_interface);
+ -1, dev, eth->phy_interface);
if (phydev != NULL) {
eth->port[0] = phydev;
eth->port_num += 1;
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index da5b696c9d8..46321116352 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -1045,7 +1045,7 @@ static int eqos_start(struct udevice *dev)
* don't need to reconnect/reconfigure again
*/
if (!eqos->phy) {
- eqos->phy = phy_connect(eqos->mii, 0, dev,
+ eqos->phy = phy_connect(eqos->mii, -1, dev,
eqos->config->interface(dev));
if (!eqos->phy) {
pr_err("phy_connect() failed");
diff --git a/drivers/phy/ti-pipe3-phy.c b/drivers/phy/ti-pipe3-phy.c
index e7e78e3c56d..0c59552bb86 100644
--- a/drivers/phy/ti-pipe3-phy.c
+++ b/drivers/phy/ti-pipe3-phy.c
@@ -41,27 +41,110 @@
#define SATA_PLL_SOFT_RESET (1<<18)
/* PHY POWER CONTROL Register */
-#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK 0x003FC000
-#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT 0xE
-
-#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK 0xFFC00000
-#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT 0x16
-
-#define OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON 0x3
-#define OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF 0x0
-
+#define PIPE3_PHY_PWRCTL_CLK_CMD_MASK GENMASK(21, 14)
+#define PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT 14
+
+#define PIPE3_PHY_PWRCTL_CLK_FREQ_MASK GENMASK(31, 22)
+#define PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT 22
+
+#define PIPE3_PHY_RX_POWERON (0x1 << PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT)
+#define PIPE3_PHY_TX_POWERON (0x2 << PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT)
+
+/* PHY RX Registers */
+#define PIPE3_PHY_RX_ANA_PROGRAMMABILITY 0x0000000C
+#define INTERFACE_MASK GENMASK(31, 27)
+#define INTERFACE_SHIFT 27
+#define INTERFACE_MODE_USBSS BIT(4)
+#define INTERFACE_MODE_SATA_1P5 BIT(3)
+#define INTERFACE_MODE_SATA_3P0 BIT(2)
+#define INTERFACE_MODE_PCIE BIT(0)
+
+#define LOSD_MASK GENMASK(17, 14)
+#define LOSD_SHIFT 14
+#define MEM_PLLDIV GENMASK(6, 5)
+
+#define PIPE3_PHY_RX_TRIM 0x0000001C
+#define MEM_DLL_TRIM_SEL_MASK GENMASK(31, 30)
+#define MEM_DLL_TRIM_SHIFT 30
+
+#define PIPE3_PHY_RX_DLL 0x00000024
+#define MEM_DLL_PHINT_RATE_MASK GENMASK(31, 30)
+#define MEM_DLL_PHINT_RATE_SHIFT 30
+
+#define PIPE3_PHY_RX_DIGITAL_MODES 0x00000028
+#define MEM_HS_RATE_MASK GENMASK(28, 27)
+#define MEM_HS_RATE_SHIFT 27
+#define MEM_OVRD_HS_RATE BIT(26)
+#define MEM_OVRD_HS_RATE_SHIFT 26
+#define MEM_CDR_FASTLOCK BIT(23)
+#define MEM_CDR_FASTLOCK_SHIFT 23
+#define MEM_CDR_LBW_MASK GENMASK(22, 21)
+#define MEM_CDR_LBW_SHIFT 21
+#define MEM_CDR_STEPCNT_MASK GENMASK(20, 19)
+#define MEM_CDR_STEPCNT_SHIFT 19
+#define MEM_CDR_STL_MASK GENMASK(18, 16)
+#define MEM_CDR_STL_SHIFT 16
+#define MEM_CDR_THR_MASK GENMASK(15, 13)
+#define MEM_CDR_THR_SHIFT 13
+#define MEM_CDR_THR_MODE BIT(12)
+#define MEM_CDR_THR_MODE_SHIFT 12
+#define MEM_CDR_2NDO_SDM_MODE BIT(11)
+#define MEM_CDR_2NDO_SDM_MODE_SHIFT 11
+
+#define PIPE3_PHY_RX_EQUALIZER 0x00000038
+#define MEM_EQLEV_MASK GENMASK(31, 16)
+#define MEM_EQLEV_SHIFT 16
+#define MEM_EQFTC_MASK GENMASK(15, 11)
+#define MEM_EQFTC_SHIFT 11
+#define MEM_EQCTL_MASK GENMASK(10, 7)
+#define MEM_EQCTL_SHIFT 7
+#define MEM_OVRD_EQLEV BIT(2)
+#define MEM_OVRD_EQLEV_SHIFT 2
+#define MEM_OVRD_EQFTC BIT(1)
+#define MEM_OVRD_EQFTC_SHIFT 1
+
+#define SATA_PHY_RX_IO_AND_A2D_OVERRIDES 0x44
+#define MEM_CDR_LOS_SOURCE_MASK GENMASK(10, 9)
+#define MEM_CDR_LOS_SOURCE_SHIFT 9
#define PLL_IDLE_TIME 100 /* in milliseconds */
#define PLL_LOCK_TIME 100 /* in milliseconds */
+enum pipe3_mode { PIPE3_MODE_PCIE = 1,
+ PIPE3_MODE_SATA,
+ PIPE3_MODE_USBSS };
+
+struct pipe3_settings {
+ u8 ana_interface;
+ u8 ana_losd;
+ u8 dig_fastlock;
+ u8 dig_lbw;
+ u8 dig_stepcnt;
+ u8 dig_stl;
+ u8 dig_thr;
+ u8 dig_thr_mode;
+ u8 dig_2ndo_sdm_mode;
+ u8 dig_hs_rate;
+ u8 dig_ovrd_hs_rate;
+ u8 dll_trim_sel;
+ u8 dll_phint_rate;
+ u8 eq_lev;
+ u8 eq_ftc;
+ u8 eq_ctl;
+ u8 eq_ovrd_lev;
+ u8 eq_ovrd_ftc;
+};
+
struct omap_pipe3 {
void __iomem *pll_ctrl_base;
+ void __iomem *phy_rx;
void __iomem *power_reg;
void __iomem *pll_reset_reg;
struct pipe3_dpll_map *dpll_map;
+ enum pipe3_mode mode;
+ struct pipe3_settings settings;
};
-
struct pipe3_dpll_params {
u16 m;
u8 n;
@@ -75,6 +158,12 @@ struct pipe3_dpll_map {
struct pipe3_dpll_params params;
};
+struct pipe3_data {
+ enum pipe3_mode mode;
+ struct pipe3_dpll_map *dpll_map;
+ struct pipe3_settings settings;
+};
+
static inline u32 omap_pipe3_readl(void __iomem *addr, unsigned offset)
{
return readl(addr + offset);
@@ -175,19 +264,75 @@ static void omap_control_pipe3_power(struct omap_pipe3 *pipe3, int on)
rate = rate/1000000;
if (on) {
- val &= ~(OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK |
- OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK);
- val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON <<
- OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
- val |= rate <<
- OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT;
+ val &= ~(PIPE3_PHY_PWRCTL_CLK_CMD_MASK |
+ PIPE3_PHY_PWRCTL_CLK_FREQ_MASK);
+ val |= rate << PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT;
+ writel(val, pipe3->power_reg);
+
+ /* Power up TX before RX for SATA & USB */
+ val |= PIPE3_PHY_TX_POWERON;
+ writel(val, pipe3->power_reg);
+
+ val |= PIPE3_PHY_RX_POWERON;
+ writel(val, pipe3->power_reg);
} else {
- val &= ~OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK;
- val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF <<
- OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
+ val &= ~PIPE3_PHY_PWRCTL_CLK_CMD_MASK;
+ writel(val, pipe3->power_reg);
}
+}
- writel(val, pipe3->power_reg);
+static void ti_pipe3_calibrate(struct omap_pipe3 *phy)
+{
+ u32 val;
+ struct pipe3_settings *s = &phy->settings;
+
+ val = omap_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_ANA_PROGRAMMABILITY);
+ val &= ~(INTERFACE_MASK | LOSD_MASK | MEM_PLLDIV);
+ val = (s->ana_interface << INTERFACE_SHIFT | s->ana_losd << LOSD_SHIFT);
+ omap_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_ANA_PROGRAMMABILITY, val);
+
+ val = omap_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_DIGITAL_MODES);
+ val &= ~(MEM_HS_RATE_MASK | MEM_OVRD_HS_RATE | MEM_CDR_FASTLOCK |
+ MEM_CDR_LBW_MASK | MEM_CDR_STEPCNT_MASK | MEM_CDR_STL_MASK |
+ MEM_CDR_THR_MASK | MEM_CDR_THR_MODE | MEM_CDR_2NDO_SDM_MODE);
+ val |= s->dig_hs_rate << MEM_HS_RATE_SHIFT |
+ s->dig_ovrd_hs_rate << MEM_OVRD_HS_RATE_SHIFT |
+ s->dig_fastlock << MEM_CDR_FASTLOCK_SHIFT |
+ s->dig_lbw << MEM_CDR_LBW_SHIFT |
+ s->dig_stepcnt << MEM_CDR_STEPCNT_SHIFT |
+ s->dig_stl << MEM_CDR_STL_SHIFT |
+ s->dig_thr << MEM_CDR_THR_SHIFT |
+ s->dig_thr_mode << MEM_CDR_THR_MODE_SHIFT |
+ s->dig_2ndo_sdm_mode << MEM_CDR_2NDO_SDM_MODE_SHIFT;
+ omap_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_DIGITAL_MODES, val);
+
+ val = omap_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_TRIM);
+ val &= ~MEM_DLL_TRIM_SEL_MASK;
+ val |= s->dll_trim_sel << MEM_DLL_TRIM_SHIFT;
+ omap_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_TRIM, val);
+
+ val = omap_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_DLL);
+ val &= ~MEM_DLL_PHINT_RATE_MASK;
+ val |= s->dll_phint_rate << MEM_DLL_PHINT_RATE_SHIFT;
+ omap_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_DLL, val);
+
+ val = omap_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_EQUALIZER);
+ val &= ~(MEM_EQLEV_MASK | MEM_EQFTC_MASK | MEM_EQCTL_MASK |
+ MEM_OVRD_EQLEV | MEM_OVRD_EQFTC);
+ val |= s->eq_lev << MEM_EQLEV_SHIFT |
+ s->eq_ftc << MEM_EQFTC_SHIFT |
+ s->eq_ctl << MEM_EQCTL_SHIFT |
+ s->eq_ovrd_lev << MEM_OVRD_EQLEV_SHIFT |
+ s->eq_ovrd_ftc << MEM_OVRD_EQFTC_SHIFT;
+ omap_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_EQUALIZER, val);
+
+ if (phy->mode == PIPE3_MODE_SATA) {
+ val = omap_pipe3_readl(phy->phy_rx,
+ SATA_PHY_RX_IO_AND_A2D_OVERRIDES);
+ val &= ~MEM_CDR_LOS_SOURCE_MASK;
+ omap_pipe3_writel(phy->phy_rx, SATA_PHY_RX_IO_AND_A2D_OVERRIDES,
+ val);
+ }
}
static int pipe3_init(struct phy *phy)
@@ -202,6 +347,8 @@ static int pipe3_init(struct phy *phy)
ret = omap_pipe3_dpll_program(pipe3);
if (ret)
return ret;
+
+ ti_pipe3_calibrate(pipe3);
} else {
/* else just bring it out of IDLE mode */
val = omap_pipe3_readl(pipe3->pll_ctrl_base,
@@ -317,7 +464,22 @@ static int pipe3_phy_probe(struct udevice *dev)
fdt_addr_t addr;
fdt_size_t sz;
struct omap_pipe3 *pipe3 = dev_get_priv(dev);
+ struct pipe3_data *data;
+ /* PHY_RX */
+ addr = devfdt_get_addr_size_index(dev, 0, &sz);
+ if (addr == FDT_ADDR_T_NONE) {
+ pr_err("missing phy_rx address\n");
+ return -EINVAL;
+ }
+
+ pipe3->phy_rx = map_physmem(addr, sz, MAP_NOCACHE);
+ if (!pipe3->phy_rx) {
+ pr_err("unable to remap phy_rx\n");
+ return -EINVAL;
+ }
+
+ /* PLLCTRL */
addr = devfdt_get_addr_size_index(dev, 2, &sz);
if (addr == FDT_ADDR_T_NONE) {
pr_err("missing pll ctrl address\n");
@@ -334,25 +496,28 @@ static int pipe3_phy_probe(struct udevice *dev)
if (!pipe3->power_reg)
return -EINVAL;
- if (device_is_compatible(dev, "ti,phy-pipe3-sata")) {
+ data = (struct pipe3_data *)dev_get_driver_data(dev);
+ pipe3->mode = data->mode;
+ pipe3->dpll_map = data->dpll_map;
+ pipe3->settings = data->settings;
+
+ if (pipe3->mode == PIPE3_MODE_SATA) {
pipe3->pll_reset_reg = get_reg(dev, "syscon-pllreset");
if (!pipe3->pll_reset_reg)
return -EINVAL;
}
- pipe3->dpll_map = (struct pipe3_dpll_map *)dev_get_driver_data(dev);
-
return 0;
}
static struct pipe3_dpll_map dpll_map_sata[] = {
- {12000000, {1000, 7, 4, 6, 0} }, /* 12 MHz */
- {16800000, {714, 7, 4, 6, 0} }, /* 16.8 MHz */
- {19200000, {625, 7, 4, 6, 0} }, /* 19.2 MHz */
- {20000000, {600, 7, 4, 6, 0} }, /* 20 MHz */
- {26000000, {461, 7, 4, 6, 0} }, /* 26 MHz */
- {38400000, {312, 7, 4, 6, 0} }, /* 38.4 MHz */
- { }, /* Terminator */
+ {12000000, {625, 4, 4, 6, 0} }, /* 12 MHz */
+ {16800000, {625, 6, 4, 7, 0} }, /* 16.8 MHz */
+ {19200000, {625, 7, 4, 6, 0} }, /* 19.2 MHz */
+ {20000000, {750, 9, 4, 6, 0} }, /* 20 MHz */
+ {26000000, {750, 12, 4, 6, 0} }, /* 26 MHz */
+ {38400000, {625, 15, 4, 6, 0} }, /* 38.4 MHz */
+ { }, /* Terminator */
};
static struct pipe3_dpll_map dpll_map_usb[] = {
@@ -365,9 +530,61 @@ static struct pipe3_dpll_map dpll_map_usb[] = {
{ }, /* Terminator */
};
+static struct pipe3_data data_usb = {
+ .mode = PIPE3_MODE_USBSS,
+ .dpll_map = dpll_map_usb,
+ .settings = {
+ /* DRA75x TRM Table 26-17. Preferred USB3_PHY_RX SCP Register Settings */
+ .ana_interface = INTERFACE_MODE_USBSS,
+ .ana_losd = 0xa,
+ .dig_fastlock = 1,
+ .dig_lbw = 3,
+ .dig_stepcnt = 0,
+ .dig_stl = 0x3,
+ .dig_thr = 1,
+ .dig_thr_mode = 1,
+ .dig_2ndo_sdm_mode = 0,
+ .dig_hs_rate = 0,
+ .dig_ovrd_hs_rate = 1,
+ .dll_trim_sel = 0x2,
+ .dll_phint_rate = 0x3,
+ .eq_lev = 0,
+ .eq_ftc = 0,
+ .eq_ctl = 0x9,
+ .eq_ovrd_lev = 0,
+ .eq_ovrd_ftc = 0,
+ },
+};
+
+static struct pipe3_data data_sata = {
+ .mode = PIPE3_MODE_SATA,
+ .dpll_map = dpll_map_sata,
+ .settings = {
+ /* DRA75x TRM Table 26-9. Preferred SATA_PHY_RX SCP Register Settings */
+ .ana_interface = INTERFACE_MODE_SATA_3P0,
+ .ana_losd = 0x5,
+ .dig_fastlock = 1,
+ .dig_lbw = 3,
+ .dig_stepcnt = 0,
+ .dig_stl = 0x3,
+ .dig_thr = 1,
+ .dig_thr_mode = 1,
+ .dig_2ndo_sdm_mode = 0,
+ .dig_hs_rate = 0, /* Not in TRM preferred settings */
+ .dig_ovrd_hs_rate = 0, /* Not in TRM preferred settings */
+ .dll_trim_sel = 0x1,
+ .dll_phint_rate = 0x2, /* for 1.5 GHz DPLL clock */
+ .eq_lev = 0,
+ .eq_ftc = 0x1f,
+ .eq_ctl = 0,
+ .eq_ovrd_lev = 1,
+ .eq_ovrd_ftc = 1,
+ },
+};
+
static const struct udevice_id pipe3_phy_ids[] = {
- { .compatible = "ti,phy-pipe3-sata", .data = (ulong)&dpll_map_sata },
- { .compatible = "ti,omap-usb3", .data = (ulong)&dpll_map_usb},
+ { .compatible = "ti,phy-pipe3-sata", .data = (ulong)&data_sata },
+ { .compatible = "ti,omap-usb3", .data = (ulong)&data_usb},
{ }
};
diff --git a/drivers/rtc/rx8010sj.c b/drivers/rtc/rx8010sj.c
index 81560e16cef..82c5185e2e5 100644
--- a/drivers/rtc/rx8010sj.c
+++ b/drivers/rtc/rx8010sj.c
@@ -349,7 +349,7 @@ void rtc_init(void)
static int rx8010sj_probe(struct udevice *dev)
{
- rx8010sj_rtc_init(&dev);
+ rx8010sj_rtc_init(dev);
return 0;
}
@@ -364,6 +364,7 @@ static const struct rtc_ops rx8010sj_rtc_ops = {
static const struct udevice_id rx8010sj_rtc_ids[] = {
{ .compatible = "epson,rx8010sj-rtc" },
+ { .compatible = "epson,rx8010" },
{ }
};
diff --git a/drivers/rtc/s35392a.c b/drivers/rtc/s35392a.c
index 844f1b72c7a..4f478ccfd72 100644
--- a/drivers/rtc/s35392a.c
+++ b/drivers/rtc/s35392a.c
@@ -350,6 +350,8 @@ static const struct rtc_ops s35392a_rtc_ops = {
static const struct udevice_id s35392a_rtc_ids[] = {
{ .compatible = "sii,s35392a-rtc" },
+ { .compatible = "sii,s35392a" },
+ { .compatible = "s35392a" },
{ }
};
diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c
index c04535ac445..95eeb8307ad 100644
--- a/drivers/spi/rk_spi.c
+++ b/drivers/spi/rk_spi.c
@@ -27,6 +27,12 @@
/* Change to 1 to output registers at the start of each transaction */
#define DEBUG_RK_SPI 0
+/*
+ * ctrlr1 is 16-bits, so we should support lengths of 0xffff + 1. However,
+ * the controller seems to hang when given 0x10000, so stick with this for now.
+ */
+#define ROCKCHIP_SPI_MAX_TRANLEN 0xffff
+
struct rockchip_spi_params {
/* RXFIFO overruns and TXFIFO underruns stop the master clock */
bool master_manages_fifo;
@@ -367,7 +373,7 @@ static inline int rockchip_spi_16bit_reader(struct udevice *dev,
* represented in CTRLR1.
*/
if (data && data->master_manages_fifo)
- max_chunk_size = 0x10000;
+ max_chunk_size = ROCKCHIP_SPI_MAX_TRANLEN;
// rockchip_spi_configure(dev, mode, size)
rkspi_enable_chip(regs, false);
@@ -451,7 +457,7 @@ static int rockchip_spi_xfer(struct udevice *dev, unsigned int bitlen,
/* This is the original 8bit reader/writer code */
while (len > 0) {
- int todo = min(len, 0x10000);
+ int todo = min(len, ROCKCHIP_SPI_MAX_TRANLEN);
rkspi_enable_chip(regs, false);
writel(todo - 1, &regs->ctrlr1);
diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig
index 5e6293ae69b..f09e138bb8c 100644
--- a/drivers/sysreset/Kconfig
+++ b/drivers/sysreset/Kconfig
@@ -119,7 +119,7 @@ config SYSRESET_TPL_X86
help
Reboot support for generic x86 processor reset in TPL.
-config SYSRESET_MCP83XX
+config SYSRESET_MPC83XX
bool "Enable support MPC83xx SoC family reboot driver"
help
Reboot support for NXP MPC83xx SoCs.
diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile
index fff4a184a02..51af68fad3b 100644
--- a/drivers/sysreset/Makefile
+++ b/drivers/sysreset/Makefile
@@ -8,7 +8,7 @@ obj-$(CONFIG_ARCH_ROCKCHIP) += sysreset_rockchip.o
obj-$(CONFIG_ARCH_STI) += sysreset_sti.o
obj-$(CONFIG_SANDBOX) += sysreset_sandbox.o
obj-$(CONFIG_SYSRESET_GPIO) += sysreset_gpio.o
-obj-$(CONFIG_SYSRESET_MCP83XX) += sysreset_mpc83xx.o
+obj-$(CONFIG_SYSRESET_MPC83XX) += sysreset_mpc83xx.o
obj-$(CONFIG_SYSRESET_MICROBLAZE) += sysreset_microblaze.o
obj-$(CONFIG_SYSRESET_PSCI) += sysreset_psci.o
obj-$(CONFIG_SYSRESET_SOCFPGA) += sysreset_socfpga.o
diff --git a/drivers/usb/cdns3/ep0.c b/drivers/usb/cdns3/ep0.c
index 1903f611038..0b6d9cf7274 100644
--- a/drivers/usb/cdns3/ep0.c
+++ b/drivers/usb/cdns3/ep0.c
@@ -10,6 +10,7 @@
* Peter Chen <peter.chen@nxp.com>
*/
+#include <cpu_func.h>
#include <linux/usb/composite.h>
#include <linux/iopoll.h>
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 0f9a6328161..77c555e7692 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -622,15 +622,19 @@ static void dwc3_uboot_hsphy_mode(struct dwc3_device *dwc3_dev,
/* Set dwc3 usb2 phy config */
reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
- reg |= DWC3_GUSB2PHYCFG_PHYIF;
- reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK;
switch (hsphy_mode) {
case USBPHY_INTERFACE_MODE_UTMI:
- reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_8BIT;
+ reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
+ DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
+ reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
+ DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
break;
case USBPHY_INTERFACE_MODE_UTMIW:
- reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT;
+ reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
+ DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
+ reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
+ DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
break;
default:
break;
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index bff53e072b9..1c08a2c5b6e 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -162,18 +162,14 @@
/* Global USB2 PHY Configuration Register */
#define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31)
#define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6)
-#define DWC3_GUSB2PHYCFG_PHYIF BIT(3)
-
-/* Global USB2 PHY Configuration Mask */
-#define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK (0xf << 10)
-
-/* Global USB2 PHY Configuration Offset */
-#define DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET 10
-
-#define DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT (0x5 << \
- DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET)
-#define DWC3_GUSB2PHYCFG_USBTRDTIM_8BIT (0x9 << \
- DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET)
+#define DWC3_GUSB2PHYCFG_PHYIF(n) ((n) << 3)
+#define DWC3_GUSB2PHYCFG_PHYIF_MASK DWC3_GUSB2PHYCFG_PHYIF(1)
+#define DWC3_GUSB2PHYCFG_USBTRDTIM(n) ((n) << 10)
+#define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK DWC3_GUSB2PHYCFG_USBTRDTIM(0xf)
+#define USBTRDTIM_UTMI_8_BIT 9
+#define USBTRDTIM_UTMI_16_BIT 5
+#define UTMI_PHYIF_16_BIT 1
+#define UTMI_PHYIF_8_BIT 0
/* Global USB3 PIPE Control Register */
#define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31)
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 4cde0acbf63..50ab3650ee9 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -38,7 +38,6 @@ config BACKLIGHT_GPIO
config VIDEO_BPP8
bool "Support 8-bit-per-pixel displays"
depends on DM_VIDEO
- default n
help
Support drawing text and bitmaps onto a 8-bit-per-pixel display.
Enabling this will include code to support this display. Without
@@ -48,7 +47,6 @@ config VIDEO_BPP8
config VIDEO_BPP16
bool "Support 16-bit-per-pixel displays"
depends on DM_VIDEO
- default n
help
Support drawing text and bitmaps onto a 16-bit-per-pixel display.
Enabling this will include code to support this display. Without
@@ -58,7 +56,7 @@ config VIDEO_BPP16
config VIDEO_BPP32
bool "Support 32-bit-per-pixel displays"
depends on DM_VIDEO
- default n
+ default y if X86
help
Support drawing text and bitmaps onto a 32-bit-per-pixel display.
Enabling this will include code to support this display. Without
@@ -68,7 +66,6 @@ config VIDEO_BPP32
config VIDEO_ANSI
bool "Support ANSI escape sequences in video console"
depends on DM_VIDEO
- default n
help
Enable ANSI escape sequence decoding for a more fully functional
console.
diff --git a/drivers/video/console_normal.c b/drivers/video/console_normal.c
index 2f25af73325..c3f7ef8addc 100644
--- a/drivers/video/console_normal.c
+++ b/drivers/video/console_normal.c
@@ -16,39 +16,36 @@
static int console_normal_set_row(struct udevice *dev, uint row, int clr)
{
struct video_priv *vid_priv = dev_get_uclass_priv(dev->parent);
- void * __maybe_unused line;
- int __maybe_unused pixels = VIDEO_FONT_HEIGHT * vid_priv->xsize;
- int __maybe_unused i;
+ void *line;
+ int pixels = VIDEO_FONT_HEIGHT * vid_priv->xsize;
+ int i;
line = vid_priv->fb + row * VIDEO_FONT_HEIGHT * vid_priv->line_length;
switch (vid_priv->bpix) {
-#ifdef CONFIG_VIDEO_BPP8
- case VIDEO_BPP8: {
- uint8_t *dst = line;
+ case VIDEO_BPP8:
+ if (IS_ENABLED(CONFIG_VIDEO_BPP8)) {
+ uint8_t *dst = line;
- for (i = 0; i < pixels; i++)
- *dst++ = clr;
- break;
- }
-#endif
-#ifdef CONFIG_VIDEO_BPP16
- case VIDEO_BPP16: {
- uint16_t *dst = line;
-
- for (i = 0; i < pixels; i++)
- *dst++ = clr;
- break;
- }
-#endif
-#ifdef CONFIG_VIDEO_BPP32
- case VIDEO_BPP32: {
- uint32_t *dst = line;
-
- for (i = 0; i < pixels; i++)
- *dst++ = clr;
- break;
- }
-#endif
+ for (i = 0; i < pixels; i++)
+ *dst++ = clr;
+ break;
+ }
+ case VIDEO_BPP16:
+ if (IS_ENABLED(CONFIG_VIDEO_BPP16)) {
+ uint16_t *dst = line;
+
+ for (i = 0; i < pixels; i++)
+ *dst++ = clr;
+ break;
+ }
+ case VIDEO_BPP32:
+ if (IS_ENABLED(CONFIG_VIDEO_BPP32)) {
+ uint32_t *dst = line;
+
+ for (i = 0; i < pixels; i++)
+ *dst++ = clr;
+ break;
+ }
default:
return -ENOSYS;
}
@@ -76,7 +73,7 @@ static int console_normal_putc_xy(struct udevice *dev, uint x_frac, uint y,
struct vidconsole_priv *vc_priv = dev_get_uclass_priv(dev);
struct udevice *vid = dev->parent;
struct video_priv *vid_priv = dev_get_uclass_priv(vid);
- int __maybe_unused i, row;
+ int i, row;
void *line = vid_priv->fb + y * vid_priv->line_length +
VID_TO_PIXEL(x_frac) * VNBYTES(vid_priv->bpix);
@@ -85,45 +82,45 @@ static int console_normal_putc_xy(struct udevice *dev, uint x_frac, uint y,
for (row = 0; row < VIDEO_FONT_HEIGHT; row++) {
unsigned int idx = (u8)ch * VIDEO_FONT_HEIGHT + row;
- uchar __maybe_unused bits = video_fontdata[idx];
+ uchar bits = video_fontdata[idx];
switch (vid_priv->bpix) {
-#ifdef CONFIG_VIDEO_BPP8
- case VIDEO_BPP8: {
- uint8_t *dst = line;
-
- for (i = 0; i < VIDEO_FONT_WIDTH; i++) {
- *dst++ = (bits & 0x80) ? vid_priv->colour_fg
- : vid_priv->colour_bg;
- bits <<= 1;
+ case VIDEO_BPP8:
+ if (IS_ENABLED(CONFIG_VIDEO_BPP8)) {
+ uint8_t *dst = line;
+
+ for (i = 0; i < VIDEO_FONT_WIDTH; i++) {
+ *dst++ = (bits & 0x80) ?
+ vid_priv->colour_fg :
+ vid_priv->colour_bg;
+ bits <<= 1;
+ }
+ break;
}
- break;
- }
-#endif
-#ifdef CONFIG_VIDEO_BPP16
- case VIDEO_BPP16: {
- uint16_t *dst = line;
-
- for (i = 0; i < VIDEO_FONT_WIDTH; i++) {
- *dst++ = (bits & 0x80) ? vid_priv->colour_fg
- : vid_priv->colour_bg;
- bits <<= 1;
+ case VIDEO_BPP16:
+ if (IS_ENABLED(CONFIG_VIDEO_BPP16)) {
+ uint16_t *dst = line;
+
+ for (i = 0; i < VIDEO_FONT_WIDTH; i++) {
+ *dst++ = (bits & 0x80) ?
+ vid_priv->colour_fg :
+ vid_priv->colour_bg;
+ bits <<= 1;
+ }
+ break;
}
- break;
- }
-#endif
-#ifdef CONFIG_VIDEO_BPP32
- case VIDEO_BPP32: {
- uint32_t *dst = line;
-
- for (i = 0; i < VIDEO_FONT_WIDTH; i++) {
- *dst++ = (bits & 0x80) ? vid_priv->colour_fg
- : vid_priv->colour_bg;
- bits <<= 1;
+ case VIDEO_BPP32:
+ if (IS_ENABLED(CONFIG_VIDEO_BPP32)) {
+ uint32_t *dst = line;
+
+ for (i = 0; i < VIDEO_FONT_WIDTH; i++) {
+ *dst++ = (bits & 0x80) ?
+ vid_priv->colour_fg :
+ vid_priv->colour_bg;
+ bits <<= 1;
+ }
+ break;
}
- break;
- }
-#endif
default:
return -ENOSYS;
}
diff --git a/drivers/video/console_rotate.c b/drivers/video/console_rotate.c
index 71a5c5efba3..b4852555989 100644
--- a/drivers/video/console_rotate.c
+++ b/drivers/video/console_rotate.c
@@ -22,33 +22,30 @@ static int console_set_row_1(struct udevice *dev, uint row, int clr)
(row + 1) * VIDEO_FONT_HEIGHT * pbytes;
for (j = 0; j < vid_priv->ysize; j++) {
switch (vid_priv->bpix) {
-#ifdef CONFIG_VIDEO_BPP8
- case VIDEO_BPP8: {
- uint8_t *dst = line;
+ case VIDEO_BPP8:
+ if (IS_ENABLED(CONFIG_VIDEO_BPP8)) {
+ uint8_t *dst = line;
- for (i = 0; i < VIDEO_FONT_HEIGHT; i++)
- *dst++ = clr;
- break;
- }
-#endif
-#ifdef CONFIG_VIDEO_BPP16
- case VIDEO_BPP16: {
- uint16_t *dst = line;
+ for (i = 0; i < VIDEO_FONT_HEIGHT; i++)
+ *dst++ = clr;
+ break;
+ }
+ case VIDEO_BPP16:
+ if (IS_ENABLED(CONFIG_VIDEO_BPP16)) {
+ uint16_t *dst = line;
- for (i = 0; i < VIDEO_FONT_HEIGHT; i++)
- *dst++ = clr;
- break;
- }
-#endif
-#ifdef CONFIG_VIDEO_BPP32
- case VIDEO_BPP32: {
- uint32_t *dst = line;
+ for (i = 0; i < VIDEO_FONT_HEIGHT; i++)
+ *dst++ = clr;
+ break;
+ }
+ case VIDEO_BPP32:
+ if (IS_ENABLED(CONFIG_VIDEO_BPP32)) {
+ uint32_t *dst = line;
- for (i = 0; i < VIDEO_FONT_HEIGHT; i++)
- *dst++ = clr;
- break;
- }
-#endif
+ for (i = 0; i < VIDEO_FONT_HEIGHT; i++)
+ *dst++ = clr;
+ break;
+ }
default:
return -ENOSYS;
}
@@ -99,39 +96,39 @@ static int console_putc_xy_1(struct udevice *dev, uint x_frac, uint y, char ch)
for (col = 0; col < VIDEO_FONT_HEIGHT; col++) {
switch (vid_priv->bpix) {
-#ifdef CONFIG_VIDEO_BPP8
- case VIDEO_BPP8: {
- uint8_t *dst = line;
-
- for (i = 0; i < VIDEO_FONT_HEIGHT; i++) {
- *dst-- = (pfont[i] & mask) ? vid_priv->colour_fg
- : vid_priv->colour_bg;
+ case VIDEO_BPP8:
+ if (IS_ENABLED(CONFIG_VIDEO_BPP8)) {
+ uint8_t *dst = line;
+
+ for (i = 0; i < VIDEO_FONT_HEIGHT; i++) {
+ *dst-- = (pfont[i] & mask) ?
+ vid_priv->colour_fg :
+ vid_priv->colour_bg;
+ }
+ break;
}
- break;
- }
-#endif
-#ifdef CONFIG_VIDEO_BPP16
- case VIDEO_BPP16: {
- uint16_t *dst = line;
-
- for (i = 0; i < VIDEO_FONT_HEIGHT; i++) {
- *dst-- = (pfont[i] & mask) ? vid_priv->colour_fg
- : vid_priv->colour_bg;
+ case VIDEO_BPP16:
+ if (IS_ENABLED(CONFIG_VIDEO_BPP16)) {
+ uint16_t *dst = line;
+
+ for (i = 0; i < VIDEO_FONT_HEIGHT; i++) {
+ *dst-- = (pfont[i] & mask) ?
+ vid_priv->colour_fg :
+ vid_priv->colour_bg;
+ }
+ break;
}
- break;
- }
-#endif
-#ifdef CONFIG_VIDEO_BPP32
- case VIDEO_BPP32: {
- uint32_t *dst = line;
-
- for (i = 0; i < VIDEO_FONT_HEIGHT; i++) {
- *dst-- = (pfont[i] & mask) ? vid_priv->colour_fg
- : vid_priv->colour_bg;
+ case VIDEO_BPP32:
+ if (IS_ENABLED(CONFIG_VIDEO_BPP32)) {
+ uint32_t *dst = line;
+
+ for (i = 0; i < VIDEO_FONT_HEIGHT; i++) {
+ *dst-- = (pfont[i] & mask) ?
+ vid_priv->colour_fg :
+ vid_priv->colour_bg;
+ }
+ break;
}
- break;
- }
-#endif
default:
return -ENOSYS;
}
@@ -153,33 +150,30 @@ static int console_set_row_2(struct udevice *dev, uint row, int clr)
line = vid_priv->fb + vid_priv->ysize * vid_priv->line_length -
(row + 1) * VIDEO_FONT_HEIGHT * vid_priv->line_length;
switch (vid_priv->bpix) {
-#ifdef CONFIG_VIDEO_BPP8
- case VIDEO_BPP8: {
- uint8_t *dst = line;
+ case VIDEO_BPP8:
+ if (IS_ENABLED(CONFIG_VIDEO_BPP8)) {
+ uint8_t *dst = line;
- for (i = 0; i < pixels; i++)
- *dst++ = clr;
- break;
- }
-#endif
-#ifdef CONFIG_VIDEO_BPP16
- case VIDEO_BPP16: {
- uint16_t *dst = line;
-
- for (i = 0; i < pixels; i++)
- *dst++ = clr;
- break;
- }
-#endif
-#ifdef CONFIG_VIDEO_BPP32
- case VIDEO_BPP32: {
- uint32_t *dst = line;
-
- for (i = 0; i < pixels; i++)
- *dst++ = clr;
- break;
- }
-#endif
+ for (i = 0; i < pixels; i++)
+ *dst++ = clr;
+ break;
+ }
+ case VIDEO_BPP16:
+ if (IS_ENABLED(CONFIG_VIDEO_BPP16)) {
+ uint16_t *dst = line;
+
+ for (i = 0; i < pixels; i++)
+ *dst++ = clr;
+ break;
+ }
+ case VIDEO_BPP32:
+ if (IS_ENABLED(CONFIG_VIDEO_BPP32)) {
+ uint32_t *dst = line;
+
+ for (i = 0; i < pixels; i++)
+ *dst++ = clr;
+ break;
+ }
default:
return -ENOSYS;
}
@@ -226,42 +220,42 @@ static int console_putc_xy_2(struct udevice *dev, uint x_frac, uint y, char ch)
uchar bits = video_fontdata[idx];
switch (vid_priv->bpix) {
-#ifdef CONFIG_VIDEO_BPP8
- case VIDEO_BPP8: {
- uint8_t *dst = line;
-
- for (i = 0; i < VIDEO_FONT_WIDTH; i++) {
- *dst-- = (bits & 0x80) ? vid_priv->colour_fg
- : vid_priv->colour_bg;
- bits <<= 1;
+ case VIDEO_BPP8:
+ if (IS_ENABLED(CONFIG_VIDEO_BPP8)) {
+ uint8_t *dst = line;
+
+ for (i = 0; i < VIDEO_FONT_WIDTH; i++) {
+ *dst-- = (bits & 0x80) ?
+ vid_priv->colour_fg :
+ vid_priv->colour_bg;
+ bits <<= 1;
+ }
+ break;
}
- break;
- }
-#endif
-#ifdef CONFIG_VIDEO_BPP16
- case VIDEO_BPP16: {
- uint16_t *dst = line;
-
- for (i = 0; i < VIDEO_FONT_WIDTH; i++) {
- *dst-- = (bits & 0x80) ? vid_priv->colour_fg
- : vid_priv->colour_bg;
- bits <<= 1;
+ case VIDEO_BPP16:
+ if (IS_ENABLED(CONFIG_VIDEO_BPP16)) {
+ uint16_t *dst = line;
+
+ for (i = 0; i < VIDEO_FONT_WIDTH; i++) {
+ *dst-- = (bits & 0x80) ?
+ vid_priv->colour_fg :
+ vid_priv->colour_bg;
+ bits <<= 1;
+ }
+ break;
}
- break;
- }
-#endif
-#ifdef CONFIG_VIDEO_BPP32
- case VIDEO_BPP32: {
- uint32_t *dst = line;
-
- for (i = 0; i < VIDEO_FONT_WIDTH; i++) {
- *dst-- = (bits & 0x80) ? vid_priv->colour_fg
- : vid_priv->colour_bg;
- bits <<= 1;
+ case VIDEO_BPP32:
+ if (IS_ENABLED(CONFIG_VIDEO_BPP32)) {
+ uint32_t *dst = line;
+
+ for (i = 0; i < VIDEO_FONT_WIDTH; i++) {
+ *dst-- = (bits & 0x80) ?
+ vid_priv->colour_fg :
+ vid_priv->colour_bg;
+ bits <<= 1;
+ }
+ break;
}
- break;
- }
-#endif
default:
return -ENOSYS;
}
@@ -281,33 +275,30 @@ static int console_set_row_3(struct udevice *dev, uint row, int clr)
line = vid_priv->fb + row * VIDEO_FONT_HEIGHT * pbytes;
for (j = 0; j < vid_priv->ysize; j++) {
switch (vid_priv->bpix) {
-#ifdef CONFIG_VIDEO_BPP8
- case VIDEO_BPP8: {
- uint8_t *dst = line;
+ case VIDEO_BPP8:
+ if (IS_ENABLED(CONFIG_VIDEO_BPP8)) {
+ uint8_t *dst = line;
- for (i = 0; i < VIDEO_FONT_HEIGHT; i++)
- *dst++ = clr;
- break;
- }
-#endif
-#ifdef CONFIG_VIDEO_BPP16
- case VIDEO_BPP16: {
- uint16_t *dst = line;
+ for (i = 0; i < VIDEO_FONT_HEIGHT; i++)
+ *dst++ = clr;
+ break;
+ }
+ case VIDEO_BPP16:
+ if (IS_ENABLED(CONFIG_VIDEO_BPP16)) {
+ uint16_t *dst = line;
- for (i = 0; i < VIDEO_FONT_HEIGHT; i++)
- *dst++ = clr;
- break;
- }
-#endif
-#ifdef CONFIG_VIDEO_BPP32
- case VIDEO_BPP32: {
- uint32_t *dst = line;
+ for (i = 0; i < VIDEO_FONT_HEIGHT; i++)
+ *dst++ = clr;
+ break;
+ }
+ case VIDEO_BPP32:
+ if (IS_ENABLED(CONFIG_VIDEO_BPP32)) {
+ uint32_t *dst = line;
- for (i = 0; i < VIDEO_FONT_HEIGHT; i++)
- *dst++ = clr;
- break;
- }
-#endif
+ for (i = 0; i < VIDEO_FONT_HEIGHT; i++)
+ *dst++ = clr;
+ break;
+ }
default:
return -ENOSYS;
}
@@ -356,39 +347,39 @@ static int console_putc_xy_3(struct udevice *dev, uint x_frac, uint y, char ch)
for (col = 0; col < VIDEO_FONT_HEIGHT; col++) {
switch (vid_priv->bpix) {
-#ifdef CONFIG_VIDEO_BPP8
- case VIDEO_BPP8: {
- uint8_t *dst = line;
-
- for (i = 0; i < VIDEO_FONT_HEIGHT; i++) {
- *dst++ = (pfont[i] & mask) ? vid_priv->colour_fg
- : vid_priv->colour_bg;
+ case VIDEO_BPP8:
+ if (IS_ENABLED(CONFIG_VIDEO_BPP8)) {
+ uint8_t *dst = line;
+
+ for (i = 0; i < VIDEO_FONT_HEIGHT; i++) {
+ *dst++ = (pfont[i] & mask) ?
+ vid_priv->colour_fg :
+ vid_priv->colour_bg;
+ }
+ break;
}
- break;
- }
-#endif
-#ifdef CONFIG_VIDEO_BPP16
- case VIDEO_BPP16: {
- uint16_t *dst = line;
-
- for (i = 0; i < VIDEO_FONT_HEIGHT; i++) {
- *dst++ = (pfont[i] & mask) ? vid_priv->colour_fg
- : vid_priv->colour_bg;
+ case VIDEO_BPP16:
+ if (IS_ENABLED(CONFIG_VIDEO_BPP16)) {
+ uint16_t *dst = line;
+
+ for (i = 0; i < VIDEO_FONT_HEIGHT; i++) {
+ *dst++ = (pfont[i] & mask) ?
+ vid_priv->colour_fg :
+ vid_priv->colour_bg;
+ }
+ break;
}
- break;
- }
-#endif
-#ifdef CONFIG_VIDEO_BPP32
- case VIDEO_BPP32: {
- uint32_t *dst = line;
-
- for (i = 0; i < VIDEO_FONT_HEIGHT; i++) {
- *dst++ = (pfont[i] & mask) ? vid_priv->colour_fg
- : vid_priv->colour_bg;
+ case VIDEO_BPP32:
+ if (IS_ENABLED(CONFIG_VIDEO_BPP32)) {
+ uint32_t *dst = line;
+
+ for (i = 0; i < VIDEO_FONT_HEIGHT; i++) {
+ *dst++ = (pfont[i] & mask) ?
+ vid_priv->colour_fg :
+ vid_priv->colour_bg;
+ }
+ break;
}
- break;
- }
-#endif
default:
return -ENOSYS;
}
diff --git a/drivers/video/fonts/.gitignore b/drivers/video/fonts/.gitignore
new file mode 100644
index 00000000000..86ec950f649
--- /dev/null
+++ b/drivers/video/fonts/.gitignore
@@ -0,0 +1 @@
+*.S
diff --git a/drivers/video/vidconsole-uclass.c b/drivers/video/vidconsole-uclass.c
index c690eceeaa7..75c7e25095d 100644
--- a/drivers/video/vidconsole-uclass.c
+++ b/drivers/video/vidconsole-uclass.c
@@ -116,7 +116,6 @@ static void vidconsole_newline(struct udevice *dev)
video_sync(dev->parent, false);
}
-#if CONFIG_IS_ENABLED(VIDEO_BPP16) || CONFIG_IS_ENABLED(VIDEO_BPP32)
static const struct vid_rgb colors[VID_COLOR_COUNT] = {
{ 0x00, 0x00, 0x00 }, /* black */
{ 0xc0, 0x00, 0x00 }, /* red */
@@ -135,23 +134,22 @@ static const struct vid_rgb colors[VID_COLOR_COUNT] = {
{ 0x00, 0xff, 0xff }, /* bright cyan */
{ 0xff, 0xff, 0xff }, /* white */
};
-#endif
u32 vid_console_color(struct video_priv *priv, unsigned int idx)
{
switch (priv->bpix) {
-#if CONFIG_IS_ENABLED(VIDEO_BPP16)
case VIDEO_BPP16:
- return ((colors[idx].r >> 3) << 11) |
- ((colors[idx].g >> 2) << 5) |
- ((colors[idx].b >> 3) << 0);
-#endif
-#if CONFIG_IS_ENABLED(VIDEO_BPP32)
+ if (CONFIG_IS_ENABLED(VIDEO_BPP16)) {
+ return ((colors[idx].r >> 3) << 11) |
+ ((colors[idx].g >> 2) << 5) |
+ ((colors[idx].b >> 3) << 0);
+ }
case VIDEO_BPP32:
- return (colors[idx].r << 16) |
- (colors[idx].g << 8) |
- (colors[idx].b << 0);
-#endif
+ if (CONFIG_IS_ENABLED(VIDEO_BPP32)) {
+ return (colors[idx].r << 16) |
+ (colors[idx].g << 8) |
+ (colors[idx].b << 0);
+ }
default:
/*
* For unknown bit arrangements just support
diff --git a/drivers/video/video-uclass.c b/drivers/video/video-uclass.c
index 5ea7568fa4c..12057c8a5be 100644
--- a/drivers/video/video-uclass.c
+++ b/drivers/video/video-uclass.c
@@ -92,26 +92,24 @@ int video_clear(struct udevice *dev)
struct video_priv *priv = dev_get_uclass_priv(dev);
switch (priv->bpix) {
-#ifdef CONFIG_VIDEO_BPP16
- case VIDEO_BPP16: {
- u16 *ppix = priv->fb;
- u16 *end = priv->fb + priv->fb_size;
-
- while (ppix < end)
- *ppix++ = priv->colour_bg;
- break;
- }
-#endif
-#ifdef CONFIG_VIDEO_BPP32
- case VIDEO_BPP32: {
- u32 *ppix = priv->fb;
- u32 *end = priv->fb + priv->fb_size;
-
- while (ppix < end)
- *ppix++ = priv->colour_bg;
- break;
- }
-#endif
+ case VIDEO_BPP16:
+ if (IS_ENABLED(CONFIG_VIDEO_BPP16)) {
+ u16 *ppix = priv->fb;
+ u16 *end = priv->fb + priv->fb_size;
+
+ while (ppix < end)
+ *ppix++ = priv->colour_bg;
+ break;
+ }
+ case VIDEO_BPP32:
+ if (IS_ENABLED(CONFIG_VIDEO_BPP32)) {
+ u32 *ppix = priv->fb;
+ u32 *end = priv->fb + priv->fb_size;
+
+ while (ppix < end)
+ *ppix++ = priv->colour_bg;
+ break;
+ }
default:
memset(priv->fb, priv->colour_bg, priv->fb_size);
break;
@@ -125,14 +123,14 @@ void video_set_default_colors(struct udevice *dev, bool invert)
struct video_priv *priv = dev_get_uclass_priv(dev);
int fore, back;
-#ifdef CONFIG_SYS_WHITE_ON_BLACK
- /* White is used when switching to bold, use light gray here */
- fore = VID_LIGHT_GRAY;
- back = VID_BLACK;
-#else
- fore = VID_BLACK;
- back = VID_WHITE;
-#endif
+ if (CONFIG_IS_ENABLED(SYS_WHITE_ON_BLACK)) {
+ /* White is used when switching to bold, use light gray here */
+ fore = VID_LIGHT_GRAY;
+ back = VID_BLACK;
+ } else {
+ fore = VID_BLACK;
+ back = VID_WHITE;
+ }
if (invert) {
int temp;
generated by cgit v1.2.3 (git 2.0.4) at 2025-09-19 23:15:11 +0000