diff options
Diffstat (limited to 'drivers')
39 files changed, 7237 insertions, 112 deletions
diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile index a72d8fe58a6..f719f4e3791 100644 --- a/drivers/clk/rockchip/Makefile +++ b/drivers/clk/rockchip/Makefile @@ -17,3 +17,4 @@ obj-$(CONFIG_ROCKCHIP_RK3368) += clk_rk3368.o obj-$(CONFIG_ROCKCHIP_RK3399) += clk_rk3399.o obj-$(CONFIG_ROCKCHIP_RK3568) += clk_rk3568.o obj-$(CONFIG_ROCKCHIP_RV1108) += clk_rv1108.o +obj-$(CONFIG_ROCKCHIP_RV1126) += clk_rv1126.o diff --git a/drivers/clk/rockchip/clk_px30.c b/drivers/clk/rockchip/clk_px30.c index 5d467447a17..33a7348b9fc 100644 --- a/drivers/clk/rockchip/clk_px30.c +++ b/drivers/clk/rockchip/clk_px30.c @@ -1415,6 +1415,9 @@ static int px30_clk_enable(struct clk *clk) case SCLK_GMAC_RMII: /* Required to successfully probe the Designware GMAC driver */ return 0; + case PCLK_WDT_NS: + /* Required to successfully probe the Designware watchdog driver */ + return 0; } debug("%s: unsupported clk %ld\n", __func__, clk->id); diff --git a/drivers/clk/rockchip/clk_rv1126.c b/drivers/clk/rockchip/clk_rv1126.c new file mode 100644 index 00000000000..3ed29364deb --- /dev/null +++ b/drivers/clk/rockchip/clk_rv1126.c @@ -0,0 +1,1889 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd + * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. + * Author: Finley Xiao <finley.xiao@rock-chips.com> + */ + +#include <common.h> +#include <bitfield.h> +#include <clk-uclass.h> +#include <dm.h> +#include <errno.h> +#include <syscon.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rv1126.h> +#include <asm/arch-rockchip/grf_rv1126.h> +#include <asm/arch-rockchip/hardware.h> +#include <dm/device-internal.h> +#include <asm/io.h> +#include <dm/lists.h> +#include <dt-bindings/clock/rockchip,rv1126-cru.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define RV1126_CPUCLK_RATE(_rate, _aclk_div, _pclk_div) \ +{ \ + .rate = _rate##U, \ + .aclk_div = _aclk_div, \ + .pclk_div = _pclk_div, \ +} + +#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) + +static struct rockchip_cpu_rate_table rv1126_cpu_rates[] = { + RV1126_CPUCLK_RATE(1200000000, 1, 5), + RV1126_CPUCLK_RATE(1008000000, 1, 5), + RV1126_CPUCLK_RATE(816000000, 1, 3), + RV1126_CPUCLK_RATE(600000000, 1, 3), + RV1126_CPUCLK_RATE(408000000, 1, 1), +}; + +static struct rockchip_pll_rate_table rv1126_pll_rates[] = { + /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ + RK3036_PLL_RATE(1600000000, 3, 200, 1, 1, 1, 0), + RK3036_PLL_RATE(1400000000, 3, 350, 2, 1, 1, 0), + RK3036_PLL_RATE(1200000000, 1, 100, 2, 1, 1, 0), + RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0), + RK3036_PLL_RATE(1100000000, 3, 275, 2, 1, 1, 0), + RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), + RK3036_PLL_RATE(1000000000, 3, 250, 2, 1, 1, 0), + RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0), + RK3036_PLL_RATE(800000000, 3, 200, 2, 1, 1, 0), + RK3036_PLL_RATE(600000000, 1, 100, 4, 1, 1, 0), + RK3036_PLL_RATE(594000000, 1, 99, 4, 1, 1, 0), + RK3036_PLL_RATE(500000000, 1, 125, 6, 1, 1, 0), + RK3036_PLL_RATE(200000000, 1, 100, 6, 2, 1, 0), + RK3036_PLL_RATE(100000000, 1, 100, 6, 4, 1, 0), + { /* sentinel */ }, +}; + +static struct rockchip_pll_clock rv1126_pll_clks[] = { + [APLL] = PLL(pll_rk3328, PLL_APLL, RV1126_PLL_CON(0), + RV1126_MODE_CON, 0, 10, 0, rv1126_pll_rates), + [DPLL] = PLL(pll_rk3328, PLL_DPLL, RV1126_PLL_CON(8), + RV1126_MODE_CON, 2, 10, 0, NULL), + [CPLL] = PLL(pll_rk3328, PLL_CPLL, RV1126_PLL_CON(16), + RV1126_MODE_CON, 4, 10, 0, rv1126_pll_rates), + [HPLL] = PLL(pll_rk3328, PLL_HPLL, RV1126_PLL_CON(24), + RV1126_MODE_CON, 6, 10, 0, rv1126_pll_rates), + [GPLL] = PLL(pll_rk3328, PLL_GPLL, RV1126_PMU_PLL_CON(0), + RV1126_PMU_MODE, 0, 10, 0, rv1126_pll_rates), +}; + +static ulong rv1126_gpll_set_rate(struct rv1126_clk_priv *priv, + struct rv1126_pmuclk_priv *pmu_priv, + ulong rate); +/* + * + * rational_best_approximation(31415, 10000, + * (1 << 8) - 1, (1 << 5) - 1, &n, &d); + * + * you may look at given_numerator as a fixed point number, + * with the fractional part size described in given_denominator. + * + * for theoretical background, see: + * http://en.wikipedia.org/wiki/Continued_fraction + */ +static void rational_best_approximation(unsigned long given_numerator, + unsigned long given_denominator, + unsigned long max_numerator, + unsigned long max_denominator, + unsigned long *best_numerator, + unsigned long *best_denominator) +{ + unsigned long n, d, n0, d0, n1, d1; + + n = given_numerator; + d = given_denominator; + n0 = 0; + d1 = 0; + n1 = 1; + d0 = 1; + for (;;) { + unsigned long t, a; + + if (n1 > max_numerator || d1 > max_denominator) { + n1 = n0; + d1 = d0; + break; + } + if (d == 0) + break; + t = d; + a = n / d; + d = n % d; + n = t; + t = n0 + a * n1; + n0 = n1; + n1 = t; + t = d0 + a * d1; + d0 = d1; + d1 = t; + } + *best_numerator = n1; + *best_denominator = d1; +} + +static ulong rv1126_gpll_get_pmuclk(struct rv1126_pmuclk_priv *priv) +{ + return rockchip_pll_get_rate(&rv1126_pll_clks[GPLL], + priv->pmucru, GPLL); +} + +static ulong rv1126_gpll_set_pmuclk(struct rv1126_pmuclk_priv *pmu_priv, ulong rate) +{ + struct udevice *cru_dev; + struct rv1126_clk_priv *priv; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_CLK, + DM_DRIVER_GET(rockchip_rv1126_cru), + &cru_dev); + if (ret) { + printf("%s: could not find cru device\n", __func__); + return ret; + } + priv = dev_get_priv(cru_dev); + + if (rv1126_gpll_set_rate(priv, pmu_priv, rate)) { + printf("%s: failed to set gpll rate %lu\n", __func__, rate); + return -EINVAL; + } + return 0; +} + +static ulong rv1126_rtc32k_get_pmuclk(struct rv1126_pmuclk_priv *priv) +{ + struct rv1126_pmucru *pmucru = priv->pmucru; + unsigned long m, n; + u32 fracdiv; + + fracdiv = readl(&pmucru->pmu_clksel_con[13]); + m = fracdiv & CLK_RTC32K_FRAC_NUMERATOR_MASK; + m >>= CLK_RTC32K_FRAC_NUMERATOR_SHIFT; + n = fracdiv & CLK_RTC32K_FRAC_DENOMINATOR_MASK; + n >>= CLK_RTC32K_FRAC_DENOMINATOR_SHIFT; + + return OSC_HZ * m / n; +} + +static ulong rv1126_rtc32k_set_pmuclk(struct rv1126_pmuclk_priv *priv, + ulong rate) +{ + struct rv1126_pmucru *pmucru = priv->pmucru; + unsigned long m, n, val; + + rk_clrsetreg(&pmucru->pmu_clksel_con[0], RTC32K_SEL_MASK, + RTC32K_SEL_OSC0_DIV32K << RTC32K_SEL_SHIFT); + + rational_best_approximation(rate, OSC_HZ, + GENMASK(16 - 1, 0), + GENMASK(16 - 1, 0), + &m, &n); + val = m << CLK_RTC32K_FRAC_NUMERATOR_SHIFT | n; + writel(val, &pmucru->pmu_clksel_con[13]); + + return rv1126_rtc32k_get_pmuclk(priv); +} + +static ulong rv1126_i2c_get_pmuclk(struct rv1126_pmuclk_priv *priv, + ulong clk_id) +{ + struct rv1126_pmucru *pmucru = priv->pmucru; + u32 div, con; + + switch (clk_id) { + case CLK_I2C0: + con = readl(&pmucru->pmu_clksel_con[2]); + div = (con & CLK_I2C0_DIV_MASK) >> CLK_I2C0_DIV_SHIFT; + break; + case CLK_I2C2: + con = readl(&pmucru->pmu_clksel_con[3]); + div = (con & CLK_I2C1_DIV_MASK) >> CLK_I2C1_DIV_SHIFT; + break; + default: + return -ENOENT; + } + + return DIV_TO_RATE(priv->gpll_hz, div); +} + +static ulong rv1126_i2c_set_pmuclk(struct rv1126_pmuclk_priv *priv, + ulong clk_id, ulong rate) +{ + struct rv1126_pmucru *pmucru = priv->pmucru; + int src_clk_div; + + src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); + assert(src_clk_div - 1 <= 127); + + switch (clk_id) { + case CLK_I2C0: + rk_clrsetreg(&pmucru->pmu_clksel_con[2], CLK_I2C0_DIV_MASK, + (src_clk_div - 1) << CLK_I2C0_DIV_SHIFT); + break; + case CLK_I2C2: + rk_clrsetreg(&pmucru->pmu_clksel_con[3], CLK_I2C2_DIV_MASK, + (src_clk_div - 1) << CLK_I2C2_DIV_SHIFT); + break; + default: + return -ENOENT; + } + + return rv1126_i2c_get_pmuclk(priv, clk_id); +} + +static ulong rv1126_pwm_get_pmuclk(struct rv1126_pmuclk_priv *priv, + ulong clk_id) +{ + struct rv1126_pmucru *pmucru = priv->pmucru; + u32 div, sel, con; + + switch (clk_id) { + case CLK_PWM0: + con = readl(&pmucru->pmu_clksel_con[6]); + sel = (con & CLK_PWM0_SEL_MASK) >> CLK_PWM0_SEL_SHIFT; + div = (con & CLK_PWM0_DIV_MASK) >> CLK_PWM0_DIV_SHIFT; + if (sel == CLK_PWM0_SEL_XIN24M) + return OSC_HZ; + break; + case CLK_PWM1: + con = readl(&pmucru->pmu_clksel_con[6]); + sel = (con & CLK_PWM1_SEL_MASK) >> CLK_PWM1_SEL_SHIFT; + div = (con & CLK_PWM1_DIV_MASK) >> CLK_PWM1_DIV_SHIFT; + if (sel == CLK_PWM1_SEL_XIN24M) + return OSC_HZ; + break; + default: + return -ENOENT; + } + + return DIV_TO_RATE(priv->gpll_hz, div); +} + +static ulong rv1126_pwm_set_pmuclk(struct rv1126_pmuclk_priv *priv, + ulong clk_id, ulong rate) +{ + struct rv1126_pmucru *pmucru = priv->pmucru; + int src_clk_div; + + switch (clk_id) { + case CLK_PWM0: + if (rate == OSC_HZ) { + rk_clrsetreg(&pmucru->pmu_clksel_con[6], + CLK_PWM0_SEL_MASK, + CLK_PWM0_SEL_XIN24M << CLK_PWM0_SEL_SHIFT); + rk_clrsetreg(&pmucru->pmu_clksel_con[6], + CLK_PWM0_DIV_MASK, 0); + } else { + src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); + assert(src_clk_div - 1 <= 127); + rk_clrsetreg(&pmucru->pmu_clksel_con[6], + CLK_PWM0_DIV_MASK, + (src_clk_div - 1) << CLK_PWM0_DIV_SHIFT); + rk_clrsetreg(&pmucru->pmu_clksel_con[6], + CLK_PWM0_SEL_MASK, + CLK_PWM0_SEL_GPLL << CLK_PWM0_SEL_SHIFT); + } + break; + case CLK_PWM1: + if (rate == OSC_HZ) { + rk_clrsetreg(&pmucru->pmu_clksel_con[6], + CLK_PWM1_SEL_MASK, + CLK_PWM1_SEL_XIN24M << CLK_PWM1_SEL_SHIFT); + rk_clrsetreg(&pmucru->pmu_clksel_con[6], + CLK_PWM1_DIV_MASK, 0); + } else { + src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); + assert(src_clk_div - 1 <= 127); + rk_clrsetreg(&pmucru->pmu_clksel_con[6], + CLK_PWM1_DIV_MASK, + (src_clk_div - 1) << CLK_PWM1_DIV_SHIFT); + rk_clrsetreg(&pmucru->pmu_clksel_con[6], + CLK_PWM1_SEL_MASK, + CLK_PWM1_SEL_GPLL << CLK_PWM1_SEL_SHIFT); + } + break; + default: + return -ENOENT; + } + + return rv1126_pwm_get_pmuclk(priv, clk_id); +} + +static ulong rv1126_spi_get_pmuclk(struct rv1126_pmuclk_priv *priv) +{ + struct rv1126_pmucru *pmucru = priv->pmucru; + u32 div, con; + + con = readl(&pmucru->pmu_clksel_con[9]); + div = (con & CLK_SPI0_DIV_MASK) >> CLK_SPI0_DIV_SHIFT; + + return DIV_TO_RATE(priv->gpll_hz, div); +} + +static ulong rv1126_spi_set_pmuclk(struct rv1126_pmuclk_priv *priv, + ulong rate) +{ + struct rv1126_pmucru *pmucru = priv->pmucru; + int src_clk_div; + + src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); + assert(src_clk_div - 1 <= 127); + + rk_clrsetreg(&pmucru->pmu_clksel_con[9], + CLK_SPI0_SEL_MASK | CLK_SPI0_DIV_MASK, + CLK_SPI0_SEL_GPLL << CLK_SPI0_SEL_SHIFT | + (src_clk_div - 1) << CLK_SPI0_DIV_SHIFT); + + return rv1126_spi_get_pmuclk(priv); +} + +static ulong rv1126_pdpmu_get_pmuclk(struct rv1126_pmuclk_priv *priv) +{ + struct rv1126_pmucru *pmucru = priv->pmucru; + u32 div, con; + + con = readl(&pmucru->pmu_clksel_con[1]); + div = (con & PCLK_PDPMU_DIV_MASK) >> PCLK_PDPMU_DIV_SHIFT; + + return DIV_TO_RATE(priv->gpll_hz, div); +} + +static ulong rv1126_pdpmu_set_pmuclk(struct rv1126_pmuclk_priv *priv, + ulong rate) +{ + struct rv1126_pmucru *pmucru = priv->pmucru; + int src_clk_div; + + src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); + assert(src_clk_div - 1 <= 31); + + rk_clrsetreg(&pmucru->pmu_clksel_con[1], + PCLK_PDPMU_DIV_MASK, + (src_clk_div - 1) << PCLK_PDPMU_DIV_SHIFT); + + return rv1126_pdpmu_get_pmuclk(priv); +} + +static ulong rv1126_pmuclk_get_rate(struct clk *clk) +{ + struct rv1126_pmuclk_priv *priv = dev_get_priv(clk->dev); + ulong rate = 0; + + if (!priv->gpll_hz) { + printf("%s gpll=%lu\n", __func__, priv->gpll_hz); + return -ENOENT; + } + + debug("%s %ld\n", __func__, clk->id); + switch (clk->id) { + case PLL_GPLL: + rate = rv1126_gpll_get_pmuclk(priv); + break; + case CLK_RTC32K: + rate = rv1126_rtc32k_get_pmuclk(priv); + break; + case CLK_I2C0: + case CLK_I2C2: + rate = rv1126_i2c_get_pmuclk(priv, clk->id); + break; + case CLK_PWM0: + case CLK_PWM1: + rate = rv1126_pwm_get_pmuclk(priv, clk->id); + break; + case CLK_SPI0: + rate = rv1126_spi_get_pmuclk(priv); + break; + case PCLK_PDPMU: + rate = rv1126_pdpmu_get_pmuclk(priv); + break; + default: + debug("%s: Unsupported CLK#%ld\n", __func__, clk->id); + return -ENOENT; + } + + return rate; +} + +static ulong rv1126_pmuclk_set_rate(struct clk *clk, ulong rate) +{ + struct rv1126_pmuclk_priv *priv = dev_get_priv(clk->dev); + ulong ret = 0; + + if (!priv->gpll_hz) { + printf("%s gpll=%lu\n", __func__, priv->gpll_hz); + return -ENOENT; + } + + debug("%s %ld %ld\n", __func__, clk->id, rate); + switch (clk->id) { + case PLL_GPLL: + ret = rv1126_gpll_set_pmuclk(priv, rate); + break; + case CLK_RTC32K: + ret = rv1126_rtc32k_set_pmuclk(priv, rate); + break; + case CLK_I2C0: + case CLK_I2C2: + ret = rv1126_i2c_set_pmuclk(priv, clk->id, rate); + break; + case CLK_PWM0: + case CLK_PWM1: + ret = rv1126_pwm_set_pmuclk(priv, clk->id, rate); + break; + case CLK_SPI0: + ret = rv1126_spi_set_pmuclk(priv, rate); + break; + case PCLK_PDPMU: + ret = rv1126_pdpmu_set_pmuclk(priv, rate); + break; + default: + debug("%s: Unsupported CLK#%ld\n", __func__, clk->id); + return -ENOENT; + } + + return ret; +} + +static int rv1126_rtc32k_set_parent(struct clk *clk, struct clk *parent) +{ + struct rv1126_pmuclk_priv *priv = dev_get_priv(clk->dev); + struct rv1126_pmucru *pmucru = priv->pmucru; + + if (parent->id == CLK_OSC0_DIV32K) + rk_clrsetreg(&pmucru->pmu_clksel_con[0], RTC32K_SEL_MASK, + RTC32K_SEL_OSC0_DIV32K << RTC32K_SEL_SHIFT); + else + rk_clrsetreg(&pmucru->pmu_clksel_con[0], RTC32K_SEL_MASK, + RTC32K_SEL_OSC1_32K << RTC32K_SEL_SHIFT); + + return 0; +} + +static int rv1126_pmuclk_set_parent(struct clk *clk, struct clk *parent) +{ + switch (clk->id) { + case CLK_RTC32K: + return rv1126_rtc32k_set_parent(clk, parent); + default: + debug("%s: Unsupported CLK#%ld\n", __func__, clk->id); + return -ENOENT; + } +} + +static struct clk_ops rv1126_pmuclk_ops = { + .get_rate = rv1126_pmuclk_get_rate, + .set_rate = rv1126_pmuclk_set_rate, + .set_parent = rv1126_pmuclk_set_parent, +}; + +static int rv1126_pmuclk_probe(struct udevice *dev) +{ + struct rv1126_pmuclk_priv *priv = dev_get_priv(dev); + + priv->gpll_hz = rv1126_gpll_get_pmuclk(priv); + + return 0; +} + +static int rv1126_pmuclk_of_to_plat(struct udevice *dev) +{ + struct rv1126_pmuclk_priv *priv = dev_get_priv(dev); + + priv->pmucru = dev_read_addr_ptr(dev); + + return 0; +} + +static int rv1126_pmuclk_bind(struct udevice *dev) +{ +#if CONFIG_IS_ENABLED(RESET_ROCKCHIP) + int ret; + + ret = offsetof(struct rv1126_pmucru, pmu_softrst_con[0]); + ret = rockchip_reset_bind(dev, ret, 2); + if (ret) + debug("Warning: software reset driver bind faile\n"); +#endif + return 0; +} + +static const struct udevice_id rv1126_pmuclk_ids[] = { + { .compatible = "rockchip,rv1126-pmucru" }, + { } +}; + +U_BOOT_DRIVER(rockchip_rv1126_pmucru) = { + .name = "rockchip_rv1126_pmucru", + .id = UCLASS_CLK, + .of_match = rv1126_pmuclk_ids, + .priv_auto = sizeof(struct rv1126_pmuclk_priv), + .of_to_plat = rv1126_pmuclk_of_to_plat, + .ops = &rv1126_pmuclk_ops, + .bind = rv1126_pmuclk_bind, + .probe = rv1126_pmuclk_probe, +}; + +static int rv1126_armclk_set_clk(struct rv1126_clk_priv *priv, ulong hz) +{ + struct rv1126_cru *cru = priv->cru; + const struct rockchip_cpu_rate_table *rate; + ulong old_rate; + + rate = rockchip_get_cpu_settings(rv1126_cpu_rates, hz); + if (!rate) { + printf("%s unsupported rate\n", __func__); + return -EINVAL; + } + + /* + * set up dependent divisors for DBG and ACLK clocks. + */ + old_rate = rockchip_pll_get_rate(&rv1126_pll_clks[APLL], + priv->cru, APLL); + if (old_rate > hz) { + if (rockchip_pll_set_rate(&rv1126_pll_clks[APLL], + priv->cru, APLL, hz)) + return -EINVAL; + rk_clrsetreg(&cru->clksel_con[1], + CORE_DBG_DIV_MASK | CORE_ACLK_DIV_MASK, + rate->pclk_div << CORE_DBG_DIV_SHIFT | + rate->aclk_div << CORE_ACLK_DIV_SHIFT); + } else if (old_rate < hz) { + rk_clrsetreg(&cru->clksel_con[1], + CORE_DBG_DIV_MASK | CORE_ACLK_DIV_MASK, + rate->pclk_div << CORE_DBG_DIV_SHIFT | + rate->aclk_div << CORE_ACLK_DIV_SHIFT); + if (rockchip_pll_set_rate(&rv1126_pll_clks[APLL], + priv->cru, APLL, hz)) + return -EINVAL; + } + + return 0; +} + +static ulong rv1126_pdcore_get_clk(struct rv1126_clk_priv *priv) +{ + struct rv1126_cru *cru = priv->cru; + u32 con, div; + + con = readl(&cru->clksel_con[0]); + div = (con & CORE_HCLK_DIV_MASK) >> CORE_HCLK_DIV_SHIFT; + + return DIV_TO_RATE(priv->gpll_hz, div); +} + +static ulong rv1126_pdcore_set_clk(struct rv1126_clk_priv *priv, ulong rate) +{ + struct rv1126_cru *cru = priv->cru; + int src_clk_div; + + src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); + assert(src_clk_div - 1 <= 31); + + rk_clrsetreg(&cru->clksel_con[0], CORE_HCLK_DIV_MASK, + (src_clk_div - 1) << CORE_HCLK_DIV_SHIFT); + + return rv1126_pdcore_get_clk(priv); +} + +static ulong rv1126_pdbus_get_clk(struct rv1126_clk_priv *priv, ulong clk_id) +{ + struct rv1126_cru *cru = priv->cru; + u32 con, div, sel, parent; + + switch (clk_id) { + case ACLK_PDBUS: + con = readl(&cru->clksel_con[2]); + div = (con & ACLK_PDBUS_DIV_MASK) >> ACLK_PDBUS_DIV_SHIFT; + sel = (con & ACLK_PDBUS_SEL_MASK) >> ACLK_PDBUS_SEL_SHIFT; + if (sel == ACLK_PDBUS_SEL_GPLL) + parent = priv->gpll_hz; + else if (sel == ACLK_PDBUS_SEL_CPLL) + parent = priv->cpll_hz; + else + return -ENOENT; + break; + case HCLK_PDBUS: + con = readl(&cru->clksel_con[2]); + div = (con & HCLK_PDBUS_DIV_MASK) >> HCLK_PDBUS_DIV_SHIFT; + sel = (con & HCLK_PDBUS_SEL_MASK) >> HCLK_PDBUS_SEL_SHIFT; + if (sel == HCLK_PDBUS_SEL_GPLL) + parent = priv->gpll_hz; + else if (sel == HCLK_PDBUS_SEL_CPLL) + parent = priv->cpll_hz; + else + return -ENOENT; + break; + case PCLK_PDBUS: + case PCLK_WDT: + con = readl(&cru->clksel_con[3]); + div = (con & PCLK_PDBUS_DIV_MASK) >> PCLK_PDBUS_DIV_SHIFT; + sel = (con & PCLK_PDBUS_SEL_MASK) >> PCLK_PDBUS_SEL_SHIFT; + if (sel == PCLK_PDBUS_SEL_GPLL) + parent = priv->gpll_hz; + else if (sel == PCLK_PDBUS_SEL_CPLL) + parent = priv->cpll_hz; + else + return -ENOENT; + break; + default: + return -ENOENT; + } + + return DIV_TO_RATE(parent, div); +} + +static ulong rv1126_pdbus_set_clk(struct rv1126_clk_priv *priv, ulong clk_id, + ulong rate) +{ + struct rv1126_cru *cru = priv->cru; + int src_clk_div, clk_sel; + + switch (clk_id) { + case ACLK_PDBUS: + if (CPLL_HZ % rate) { + src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); + clk_sel = ACLK_PDBUS_SEL_GPLL; + } else { + src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate); + clk_sel = ACLK_PDBUS_SEL_CPLL; + } + assert(src_clk_div - 1 <= 31); + rk_clrsetreg(&cru->clksel_con[2], + ACLK_PDBUS_SEL_MASK | ACLK_PDBUS_DIV_MASK, + clk_sel << ACLK_PDBUS_SEL_SHIFT | + (src_clk_div - 1) << ACLK_PDBUS_DIV_SHIFT); + break; + case HCLK_PDBUS: + src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); + assert(src_clk_div - 1 <= 31); + rk_clrsetreg(&cru->clksel_con[2], + HCLK_PDBUS_SEL_MASK | HCLK_PDBUS_DIV_MASK, + HCLK_PDBUS_SEL_GPLL << HCLK_PDBUS_SEL_SHIFT | + (src_clk_div - 1) << HCLK_PDBUS_DIV_SHIFT); + break; + case PCLK_PDBUS: + case PCLK_WDT: + src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); + assert(src_clk_div - 1 <= 31); + rk_clrsetreg(&cru->clksel_con[3], + PCLK_PDBUS_SEL_MASK | PCLK_PDBUS_DIV_MASK, + PCLK_PDBUS_SEL_GPLL << PCLK_PDBUS_SEL_SHIFT | + (src_clk_div - 1) << PCLK_PDBUS_DIV_SHIFT); + break; + + default: + printf("do not support this pdbus freq\n"); + return -EINVAL; + } + + return rv1126_pdbus_get_clk(priv, clk_id); +} + +static ulong rv1126_pdphp_get_clk(struct rv1126_clk_priv *priv, ulong clk_id) +{ + struct rv1126_cru *cru = priv->cru; + u32 con, div, parent; + + switch (clk_id) { + case ACLK_PDPHP: + con = readl(&cru->clksel_con[53]); + div = (con & ACLK_PDPHP_DIV_MASK) >> ACLK_PDPHP_DIV_SHIFT; + parent = priv->gpll_hz; + break; + case HCLK_PDPHP: + con = readl(&cru->clksel_con[53]); + div = (con & HCLK_PDPHP_DIV_MASK) >> HCLK_PDPHP_DIV_SHIFT; + parent = priv->gpll_hz; + break; + default: + return -ENOENT; + } + + return DIV_TO_RATE(parent, div); +} + +static ulong rv1126_pdphp_set_clk(struct rv1126_clk_priv *priv, ulong clk_id, + ulong rate) +{ + struct rv1126_cru *cru = priv->cru; + int src_clk_div; + + src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); + assert(src_clk_div - 1 <= 31); + + switch (clk_id) { + case ACLK_PDPHP: + rk_clrsetreg(&cru->clksel_con[53], + ACLK_PDPHP_SEL_MASK | ACLK_PDPHP_DIV_MASK, + ACLK_PDPHP_SEL_GPLL << ACLK_PDPHP_SEL_SHIFT | + (src_clk_div - 1) << ACLK_PDPHP_DIV_SHIFT); + break; + case HCLK_PDPHP: + rk_clrsetreg(&cru->clksel_con[53], + HCLK_PDPHP_DIV_MASK, + (src_clk_div - 1) << HCLK_PDPHP_DIV_SHIFT); + break; + default: + printf("do not support this pdphp freq\n"); + return -EINVAL; + } + + return rv1126_pdphp_get_clk(priv, clk_id); +} + +static ulong rv1126_pdaudio_get_clk(struct rv1126_clk_priv *priv) +{ + struct rv1126_cru *cru = priv->cru; + u32 con, div; + + con = readl(&cru->clksel_con[26]); + div = (con & HCLK_PDAUDIO_DIV_MASK) >> HCLK_PDAUDIO_DIV_SHIFT; + + return DIV_TO_RATE(priv->gpll_hz, div); +} + +static ulong rv1126_pdaudio_set_clk(struct rv1126_clk_priv *priv, ulong rate) +{ + struct rv1126_cru *cru = priv->cru; + int src_clk_div; + + src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); + assert(src_clk_div - 1 <= 31); + + rk_clrsetreg(&cru->clksel_con[26], HCLK_PDAUDIO_DIV_MASK, + (src_clk_div - 1) << HCLK_PDAUDIO_DIV_SHIFT); + + return rv1126_pdaudio_get_clk(priv); +} + +static ulong rv1126_i2c_get_clk(struct rv1126_clk_priv *priv, ulong clk_id) +{ + struct rv1126_cru *cru = priv->cru; + u32 div, con; + + switch (clk_id) { + case CLK_I2C1: + con = readl(&cru->clksel_con[5]); + div = (con & CLK_I2C1_DIV_MASK) >> CLK_I2C1_DIV_SHIFT; + break; + case CLK_I2C3: + con = readl(&cru->clksel_con[5]); + div = (con & CLK_I2C3_DIV_MASK) >> CLK_I2C3_DIV_SHIFT; + break; + case CLK_I2C4: + con = readl(&cru->clksel_con[6]); + div = (con & CLK_I2C4_DIV_MASK) >> CLK_I2C4_DIV_SHIFT; + break; + case CLK_I2C5: + con = readl(&cru->clksel_con[6]); + div = (con & CLK_I2C5_DIV_MASK) >> CLK_I2C5_DIV_SHIFT; + break; + default: + return -ENOENT; + } + + return DIV_TO_RATE(priv->gpll_hz, div); +} + +static ulong rv1126_i2c_set_clk(struct rv1126_clk_priv *priv, ulong clk_id, + ulong rate) +{ + struct rv1126_cru *cru = priv->cru; + int src_clk_div; + + src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); + assert(src_clk_div - 1 <= 127); + + switch (clk_id) { + case CLK_I2C1: + rk_clrsetreg(&cru->clksel_con[5], CLK_I2C1_DIV_MASK, + (src_clk_div - 1) << CLK_I2C1_DIV_SHIFT); + break; + case CLK_I2C3: + rk_clrsetreg(&cru->clksel_con[5], CLK_I2C3_DIV_MASK, + (src_clk_div - 1) << CLK_I2C3_DIV_SHIFT); + break; + case CLK_I2C4: + rk_clrsetreg(&cru->clksel_con[6], CLK_I2C4_DIV_MASK, + (src_clk_div - 1) << CLK_I2C4_DIV_SHIFT); + break; + case CLK_I2C5: + rk_clrsetreg(&cru->clksel_con[6], CLK_I2C5_DIV_MASK, + (src_clk_div - 1) << CLK_I2C5_DIV_SHIFT); + break; + default: + return -ENOENT; + } + + return rv1126_i2c_get_clk(priv, clk_id); +} + +static ulong rv1126_spi_get_clk(struct rv1126_clk_priv *priv) +{ + struct rv1126_cru *cru = priv->cru; + u32 div, con; + + con = readl(&cru->clksel_con[8]); + div = (con & CLK_SPI1_DIV_MASK) >> CLK_SPI1_DIV_SHIFT; + + return DIV_TO_RATE(priv->gpll_hz, div); +} + +static ulong rv1126_spi_set_clk(struct rv1126_clk_priv *priv, ulong rate) +{ + struct rv1126_cru *cru = priv->cru; + int src_clk_div; + + src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); + assert(src_clk_div - 1 <= 127); + + rk_clrsetreg(&cru->clksel_con[8], + CLK_SPI1_SEL_MASK | CLK_SPI1_DIV_MASK, + CLK_SPI1_SEL_GPLL << CLK_SPI1_SEL_SHIFT | + (src_clk_div - 1) << CLK_SPI1_DIV_SHIFT); + + return rv1126_spi_get_clk(priv); +} + +static ulong rv1126_pwm_get_clk(struct rv1126_clk_priv *priv) +{ + struct rv1126_cru *cru = priv->cru; + u32 div, sel, con; + + con = readl(&cru->clksel_con[9]); + sel = (con & CLK_PWM2_SEL_MASK) >> CLK_PWM2_SEL_SHIFT; + div = (con & CLK_PWM2_DIV_MASK) >> CLK_PWM2_DIV_SHIFT; + if (sel == CLK_PWM2_SEL_XIN24M) + return OSC_HZ; + + return DIV_TO_RATE(priv->gpll_hz, div); +} + +static ulong rv1126_pwm_set_clk(struct rv1126_clk_priv *priv, ulong rate) +{ + struct rv1126_cru *cru = priv->cru; + int src_clk_div; + + if (rate == OSC_HZ) { + rk_clrsetreg(&cru->clksel_con[9], CLK_PWM2_SEL_MASK, + CLK_PWM2_SEL_XIN24M << CLK_PWM2_SEL_SHIFT); + rk_clrsetreg(&cru->clksel_con[9], CLK_PWM2_DIV_MASK, 0); + } else { + src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); + assert(src_clk_div - 1 <= 127); + rk_clrsetreg(&cru->clksel_con[9], CLK_PWM2_DIV_MASK, + (src_clk_div - 1) << CLK_PWM2_DIV_SHIFT); + rk_clrsetreg(&cru->clksel_con[9], CLK_PWM2_SEL_MASK, + CLK_PWM2_SEL_GPLL << CLK_PWM2_SEL_SHIFT); + } + + return rv1126_pwm_get_clk(priv); +} + +static ulong rv1126_saradc_get_clk(struct rv1126_clk_priv *priv) +{ + struct rv1126_cru *cru = priv->cru; + u32 div, con; + + con = readl(&cru->clksel_con[20]); + div = (con & CLK_SARADC_DIV_MASK) >> CLK_SARADC_DIV_SHIFT; + + return DIV_TO_RATE(OSC_HZ, div); +} + +static ulong rv1126_saradc_set_clk(struct rv1126_clk_priv *priv, ulong rate) +{ + struct rv1126_cru *cru = priv->cru; + int src_clk_div; + + src_clk_div = DIV_ROUND_UP(OSC_HZ, rate); + assert(src_clk_div - 1 <= 2047); + rk_clrsetreg(&cru->clksel_con[20], CLK_SARADC_DIV_MASK, + (src_clk_div - 1) << CLK_SARADC_DIV_SHIFT); + + return rv1126_saradc_get_clk(priv); +} + +static ulong rv1126_crypto_get_clk(struct rv1126_clk_priv *priv, ulong clk_id) +{ + struct rv1126_cru *cru = priv->cru; + u32 div, sel, con, parent; + + switch (clk_id) { + case CLK_CRYPTO_CORE: + con = readl(&cru->clksel_con[7]); + div = (con & CLK_CRYPTO_CORE_DIV_MASK) >> CLK_CRYPTO_CORE_DIV_SHIFT; + sel = (con & CLK_CRYPTO_CORE_SEL_MASK) >> CLK_CRYPTO_CORE_SEL_SHIFT; + if (sel == CLK_CRYPTO_CORE_SEL_GPLL) + parent = priv->gpll_hz; + else if (sel == CLK_CRYPTO_CORE_SEL_CPLL) + parent = priv->cpll_hz; + else + return -ENOENT; + break; + case CLK_CRYPTO_PKA: + con = readl(&cru->clksel_con[7]); + div = (con & CLK_CRYPTO_PKA_DIV_MASK) >> CLK_CRYPTO_PKA_DIV_SHIFT; + sel = (con & CLK_CRYPTO_PKA_SEL_MASK) >> CLK_CRYPTO_PKA_SEL_SHIFT; + if (sel == CLK_CRYPTO_PKA_SEL_GPLL) + parent = priv->gpll_hz; + else if (sel == CLK_CRYPTO_PKA_SEL_CPLL) + parent = priv->cpll_hz; + else + return -ENOENT; + break; + case ACLK_CRYPTO: + con = readl(&cru->clksel_con[4]); + div = (con & ACLK_CRYPTO_DIV_MASK) >> ACLK_CRYPTO_DIV_SHIFT; + sel = (con & ACLK_CRYPTO_SEL_MASK) >> ACLK_CRYPTO_SEL_SHIFT; + if (sel == ACLK_CRYPTO_SEL_GPLL) + parent = priv->gpll_hz; + else if (sel == ACLK_CRYPTO_SEL_CPLL) + parent = priv->cpll_hz; + else + return -ENOENT; + break; + default: + return -ENOENT; + } + + return DIV_TO_RATE(parent, div); +} + +static ulong rv1126_crypto_set_clk(struct rv1126_clk_priv *priv, ulong clk_id, + ulong rate) +{ + struct rv1126_cru *cru = priv->cru; + int src_clk_div; + + src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); + assert(src_clk_div - 1 <= 31); + + switch (clk_id) { + case CLK_CRYPTO_CORE: + rk_clrsetreg(&cru->clksel_con[7], + CLK_CRYPTO_CORE_SEL_MASK | + CLK_CRYPTO_CORE_DIV_MASK, + CLK_CRYPTO_CORE_SEL_GPLL << + CLK_CRYPTO_CORE_SEL_SHIFT | + (src_clk_div - 1) << CLK_CRYPTO_CORE_DIV_SHIFT); + break; + case CLK_CRYPTO_PKA: + rk_clrsetreg(&cru->clksel_con[7], + CLK_CRYPTO_PKA_SEL_MASK | + CLK_CRYPTO_PKA_DIV_MASK, + CLK_CRYPTO_PKA_SEL_GPLL << + CLK_CRYPTO_PKA_SEL_SHIFT | + (src_clk_div - 1) << CLK_CRYPTO_PKA_DIV_SHIFT); + break; + case ACLK_CRYPTO: + rk_clrsetreg(&cru->clksel_con[4], + ACLK_CRYPTO_SEL_MASK | ACLK_CRYPTO_DIV_MASK, + ACLK_CRYPTO_SEL_GPLL << ACLK_CRYPTO_SEL_SHIFT | + (src_clk_div - 1) << ACLK_CRYPTO_DIV_SHIFT); + break; + default: + return -ENOENT; + } + + return rv1126_crypto_get_clk(priv, clk_id); +} + +static ulong rv1126_mmc_get_clk(struct rv1126_clk_priv *priv, ulong clk_id) +{ + struct rv1126_cru *cru = priv->cru; + u32 div, sel, con, con_id; + + switch (clk_id) { + case HCLK_SDMMC: + case CLK_SDMMC: + con_id = 55; + break; + case HCLK_SDIO: + case CLK_SDIO: + con_id = 56; + break; + case HCLK_EMMC: + case CLK_EMMC: + case SCLK_EMMC_SAMPLE: + con_id = 57; + break; + default: + return -ENOENT; + } + + con = readl(&cru->clksel_con[con_id]); + div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT; + sel = (con & EMMC_SEL_MASK) >> EMMC_SEL_SHIFT; + if (sel == EMMC_SEL_GPLL) + return DIV_TO_RATE(priv->gpll_hz, div) / 2; + else if (sel == EMMC_SEL_CPLL) + return DIV_TO_RATE(priv->cpll_hz, div) / 2; + else if (sel == EMMC_SEL_XIN24M) + return DIV_TO_RATE(OSC_HZ, div) / 2; + + return -ENOENT; +} + +static ulong rv1126_mmc_set_clk(struct rv1126_clk_priv *priv, ulong clk_id, + ulong rate) +{ + struct rv1126_cru *cru = priv->cru; + int src_clk_div; + u32 con_id; + + switch (clk_id) { + case HCLK_SDMMC: + case CLK_SDMMC: + con_id = 55; + break; + case HCLK_SDIO: + case CLK_SDIO: + con_id = 56; + break; + case HCLK_EMMC: + case CLK_EMMC: + con_id = 57; + break; + default: + return -ENOENT; + } + + /* Select clk_sdmmc/emmc source from GPLL by default */ + /* mmc clock defaulg div 2 internal, need provide double in cru */ + src_clk_div = DIV_ROUND_UP(priv->gpll_hz / 2, rate); + + if (src_clk_div > 127) { + /* use 24MHz source for 400KHz clock */ + src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, rate); + rk_clrsetreg(&cru->clksel_con[con_id], + EMMC_SEL_MASK | EMMC_DIV_MASK, + EMMC_SEL_XIN24M << EMMC_SEL_SHIFT | + (src_clk_div - 1) << EMMC_DIV_SHIFT); + } else { + rk_clrsetreg(&cru->clksel_con[con_id], + EMMC_SEL_MASK | EMMC_DIV_MASK, + EMMC_SEL_GPLL << EMMC_SEL_SHIFT | + (src_clk_div - 1) << EMMC_DIV_SHIFT); + } + + return rv1126_mmc_get_clk(priv, clk_id); +} + +static ulong rv1126_sfc_get_clk(struct rv1126_clk_priv *priv) +{ + struct rv1126_cru *cru = priv->cru; + u32 div, sel, con, parent; + + con = readl(&cru->clksel_con[58]); + div = (con & SCLK_SFC_DIV_MASK) >> SCLK_SFC_DIV_SHIFT; + sel = (con & SCLK_SFC_SEL_MASK) >> SCLK_SFC_SEL_SHIFT; + if (sel == SCLK_SFC_SEL_GPLL) + parent = priv->gpll_hz; + else if (sel == SCLK_SFC_SEL_CPLL) + parent = priv->cpll_hz; + else + return -ENOENT; + + return DIV_TO_RATE(parent, div); +} + +static ulong rv1126_sfc_set_clk(struct rv1126_clk_priv *priv, ulong rate) +{ + struct rv1126_cru *cru = priv->cru; + int src_clk_div; + + src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); + rk_clrsetreg(&cru->clksel_con[58], + SCLK_SFC_SEL_MASK | SCLK_SFC_DIV_MASK, + SCLK_SFC_SEL_GPLL << SCLK_SFC_SEL_SHIFT | + (src_clk_div - 1) << SCLK_SFC_DIV_SHIFT); + + return rv1126_sfc_get_clk(priv); +} + +static ulong rv1126_nand_get_clk(struct rv1126_clk_priv *priv) +{ + struct rv1126_cru *cru = priv->cru; + u32 div, sel, con, parent; + + con = readl(&cru->clksel_con[59]); + div = (con & CLK_NANDC_DIV_MASK) >> CLK_NANDC_DIV_SHIFT; + sel = (con & CLK_NANDC_SEL_MASK) >> CLK_NANDC_SEL_SHIFT; + if (sel == CLK_NANDC_SEL_GPLL) + parent = priv->gpll_hz; + else if (sel == CLK_NANDC_SEL_CPLL) + parent = priv->cpll_hz; + else + return -ENOENT; + + return DIV_TO_RATE(parent, div); +} + +static ulong rv1126_nand_set_clk(struct rv1126_clk_priv *priv, ulong rate) +{ + struct rv1126_cru *cru = priv->cru; + int src_clk_div; + + src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); + rk_clrsetreg(&cru->clksel_con[59], + CLK_NANDC_SEL_MASK | CLK_NANDC_DIV_MASK, + CLK_NANDC_SEL_GPLL << CLK_NANDC_SEL_SHIFT | + (src_clk_div - 1) << CLK_NANDC_DIV_SHIFT); + + return rv1126_nand_get_clk(priv); +} + +static ulong rv1126_aclk_vop_get_clk(struct rv1126_clk_priv *priv) +{ + struct rv1126_cru *cru = priv->cru; + u32 div, sel, con, parent; + + con = readl(&cru->clksel_con[45]); + div = (con & ACLK_PDVO_DIV_MASK) >> ACLK_PDVO_DIV_SHIFT; + sel = (con & ACLK_PDVO_SEL_MASK) >> ACLK_PDVO_SEL_SHIFT; + if (sel == ACLK_PDVO_SEL_GPLL) + parent = priv->gpll_hz; + else if (sel == ACLK_PDVO_SEL_CPLL) + parent = priv->cpll_hz; + else + return -ENOENT; + + return DIV_TO_RATE(parent, div); +} + +static ulong rv1126_aclk_vop_set_clk(struct rv1126_clk_priv *priv, ulong rate) +{ + struct rv1126_cru *cru = priv->cru; + int src_clk_div; + + src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); + assert(src_clk_div - 1 <= 31); + rk_clrsetreg(&cru->clksel_con[45], + ACLK_PDVO_SEL_MASK | ACLK_PDVO_DIV_MASK, + ACLK_PDVO_SEL_GPLL << ACLK_PDVO_SEL_SHIFT | + (src_clk_div - 1) << ACLK_PDVO_DIV_SHIFT); + + return rv1126_aclk_vop_get_clk(priv); +} + +static ulong rv1126_dclk_vop_get_clk(struct rv1126_clk_priv *priv) +{ + struct rv1126_cru *cru = priv->cru; + u32 div, sel, con, parent; + + con = readl(&cru->clksel_con[47]); + div = (con & DCLK_VOP_DIV_MASK) >> DCLK_VOP_DIV_SHIFT; + sel = (con & DCLK_VOP_SEL_MASK) >> DCLK_VOP_SEL_SHIFT; + if (sel == DCLK_VOP_SEL_GPLL) + parent = priv->gpll_hz; + else if (sel == DCLK_VOP_SEL_CPLL) + parent = priv->cpll_hz; + else + return -ENOENT; + + return DIV_TO_RATE(parent, div); +} + +static ulong rv1126_dclk_vop_set_clk(struct rv1126_clk_priv *priv, ulong rate) +{ + struct rv1126_cru *cru = priv->cru; + ulong pll_rate, now, best_rate = 0; + u32 i, div, best_div = 0, best_sel = 0; + + for (i = 0; i <= DCLK_VOP_SEL_CPLL; i++) { + switch (i) { + case DCLK_VOP_SEL_GPLL: + pll_rate = priv->gpll_hz; + break; + case DCLK_VOP_SEL_CPLL: + pll_rate = priv->cpll_hz; + break; + default: + printf("do not support this vop pll sel\n"); + return -EINVAL; + } + + div = DIV_ROUND_UP(pll_rate, rate); + if (div > 255) + continue; + now = pll_rate / div; + if (abs(rate - now) < abs(rate - best_rate)) { + best_rate = now; + best_div = div; + best_sel = i; + } + debug("pll_rate=%lu, best_rate=%lu, best_div=%u, best_sel=%u\n", + pll_rate, best_rate, best_div, best_sel); + } + + if (best_rate) { + rk_clrsetreg(&cru->clksel_con[47], + DCLK_VOP_SEL_MASK | DCLK_VOP_DIV_MASK, + best_sel << DCLK_VOP_SEL_SHIFT | + (best_div - 1) << DCLK_VOP_DIV_SHIFT); + } else { + printf("do not support this vop freq %lu\n", rate); + return -EINVAL; + } + + return rv1126_dclk_vop_get_clk(priv); +} + +static ulong rv1126_scr1_get_clk(struct rv1126_clk_priv *priv) +{ + struct rv1126_cru *cru = priv->cru; + u32 div, sel, con, parent; + + con = readl(&cru->clksel_con[3]); + div = (con & CLK_SCR1_DIV_MASK) >> CLK_SCR1_DIV_SHIFT; + sel = (con & CLK_SCR1_SEL_MASK) >> CLK_SCR1_SEL_SHIFT; + if (sel == CLK_SCR1_SEL_GPLL) + parent = priv->gpll_hz; + else if (sel == CLK_SCR1_SEL_CPLL) + parent = priv->cpll_hz; + else + return -ENOENT; + + return DIV_TO_RATE(parent, div); +} + +static ulong rv1126_scr1_set_clk(struct rv1126_clk_priv *priv, ulong rate) +{ + struct rv1126_cru *cru = priv->cru; + int src_clk_div; + + src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); + assert(src_clk_div - 1 <= 31); + rk_clrsetreg(&cru->clksel_con[3], + CLK_SCR1_SEL_MASK | CLK_SCR1_DIV_MASK, + CLK_SCR1_SEL_GPLL << CLK_SCR1_SEL_SHIFT | + (src_clk_div - 1) << CLK_SCR1_DIV_SHIFT); + + return rv1126_scr1_get_clk(priv); +} + +static ulong rv1126_gmac_src_get_clk(struct rv1126_clk_priv *priv) +{ + struct rv1126_cru *cru = priv->cru; + u32 div, sel, con, parent; + + con = readl(&cru->clksel_con[63]); + div = (con & CLK_GMAC_SRC_DIV_MASK) >> CLK_GMAC_SRC_DIV_SHIFT; + sel = (con & CLK_GMAC_SRC_SEL_MASK) >> CLK_GMAC_SRC_SEL_SHIFT; + if (sel == CLK_GMAC_SRC_SEL_CPLL) + parent = priv->cpll_hz; + else if (sel == CLK_GMAC_SRC_SEL_GPLL) + parent = priv->gpll_hz; + else + return -ENOENT; + + return DIV_TO_RATE(parent, div); +} + +static ulong rv1126_gmac_src_set_clk(struct rv1126_clk_priv *priv, ulong rate) +{ + struct rv1126_cru *cru = priv->cru; + int src_clk_div; + + src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate); + assert(src_clk_div - 1 <= 31); + rk_clrsetreg(&cru->clksel_con[63], + CLK_GMAC_SRC_SEL_MASK | CLK_GMAC_SRC_DIV_MASK, + CLK_GMAC_SRC_SEL_CPLL << CLK_GMAC_SRC_SEL_SHIFT | + (src_clk_div - 1) << CLK_GMAC_SRC_DIV_SHIFT); + + return rv1126_gmac_src_get_clk(priv); +} + +static ulong rv1126_gmac_out_get_clk(struct rv1126_clk_priv *priv) +{ + struct rv1126_cru *cru = priv->cru; + u32 div, sel, con, parent; + + con = readl(&cru->clksel_con[61]); + div = (con & CLK_GMAC_OUT_DIV_MASK) >> CLK_GMAC_OUT_DIV_SHIFT; + sel = (con & CLK_GMAC_OUT_SEL_MASK) >> CLK_GMAC_OUT_SEL_SHIFT; + if (sel == CLK_GMAC_OUT_SEL_CPLL) + parent = priv->cpll_hz; + else if (sel == CLK_GMAC_OUT_SEL_GPLL) + parent = priv->gpll_hz; + else + return -ENOENT; + + return DIV_TO_RATE(parent, div); +} + +static ulong rv1126_gmac_out_set_clk(struct rv1126_clk_priv *priv, ulong rate) +{ + struct rv1126_cru *cru = priv->cru; + int src_clk_div; + + src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate); + assert(src_clk_div - 1 <= 31); + rk_clrsetreg(&cru->clksel_con[61], + CLK_GMAC_OUT_SEL_MASK | CLK_GMAC_OUT_DIV_MASK, + CLK_GMAC_OUT_SEL_CPLL << CLK_GMAC_OUT_SEL_SHIFT | + (src_clk_div - 1) << CLK_GMAC_OUT_DIV_SHIFT); + + return rv1126_gmac_out_get_clk(priv); +} + +static ulong rv1126_gmac_tx_rx_set_clk(struct rv1126_clk_priv *priv, ulong rate) +{ + struct rv1126_cru *cru = priv->cru; + u32 con, sel, div_sel; + + con = readl(&cru->gmac_con); + sel = (con & GMAC_MODE_SEL_MASK) >> GMAC_MODE_SEL_SHIFT; + + if (sel == GMAC_RGMII_MODE) { + if (rate == 2500000) + div_sel = RGMII_CLK_DIV50; + else if (rate == 25000000) + div_sel = RGMII_CLK_DIV5; + else + div_sel = RGMII_CLK_DIV0; + rk_clrsetreg(&cru->gmac_con, RGMII_CLK_SEL_MASK, + div_sel << RGMII_CLK_SEL_SHIFT); + } else if (sel == GMAC_RMII_MODE) { + if (rate == 2500000) + div_sel = RMII_CLK_DIV20; + else + div_sel = RMII_CLK_DIV2; + rk_clrsetreg(&cru->gmac_con, RMII_CLK_SEL_MASK, + div_sel << RMII_CLK_SEL_SHIFT); + } + + return 0; +} + +static ulong rv1126_pclk_gmac_get_clk(struct rv1126_clk_priv *priv) +{ + struct rv1126_cru *cru = priv->cru; + u32 div, con, parent; + + parent = rv1126_pdphp_get_clk(priv, ACLK_PDPHP); + + con = readl(&cru->clksel_con[63]); + div = (con & PCLK_GMAC_DIV_MASK) >> PCLK_GMAC_DIV_SHIFT; + + return DIV_TO_RATE(parent, div); +} + +static ulong rv1126_dclk_decom_get_clk(struct rv1126_clk_priv *priv) +{ + struct rv1126_cru *cru = priv->cru; + u32 div, sel, con, parent; + + con = readl(&cru->clksel_con[25]); + div = (con & DCLK_DECOM_DIV_MASK) >> DCLK_DECOM_DIV_SHIFT; + sel = (con & DCLK_DECOM_SEL_MASK) >> DCLK_DECOM_SEL_SHIFT; + if (sel == DCLK_DECOM_SEL_GPLL) + parent = priv->gpll_hz; + else if (sel == DCLK_DECOM_SEL_CPLL) + parent = priv->cpll_hz; + else + return -ENOENT; + + return DIV_TO_RATE(parent, div); +} + +static ulong rv1126_dclk_decom_set_clk(struct rv1126_clk_priv *priv, ulong rate) +{ + struct rv1126_cru *cru = priv->cru; + u32 src_clk_div; + + src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); + assert(src_clk_div - 1 <= 127); + rk_clrsetreg(&cru->clksel_con[25], + DCLK_DECOM_SEL_MASK | DCLK_DECOM_DIV_MASK, + DCLK_DECOM_SEL_GPLL << DCLK_DECOM_SEL_SHIFT | + (src_clk_div - 1) << DCLK_DECOM_DIV_SHIFT); + + return rv1126_dclk_decom_get_clk(priv); +} + +static ulong rv1126_clk_get_rate(struct clk *clk) +{ + struct rv1126_clk_priv *priv = dev_get_priv(clk->dev); + ulong rate = 0; + + if (!priv->gpll_hz) { + printf("%s gpll=%lu\n", __func__, priv->gpll_hz); + return -ENOENT; + } + + switch (clk->id) { + case PLL_APLL: + case ARMCLK: + rate = rockchip_pll_get_rate(&rv1126_pll_clks[APLL], priv->cru, + APLL); + break; + case PLL_CPLL: + rate = rockchip_pll_get_rate(&rv1126_pll_clks[CPLL], priv->cru, + CPLL); + break; + case PLL_HPLL: + rate = rockchip_pll_get_rate(&rv1126_pll_clks[HPLL], priv->cru, + HPLL); + break; + case PLL_DPLL: + rate = rockchip_pll_get_rate(&rv1126_pll_clks[DPLL], priv->cru, + DPLL); + break; + case HCLK_PDCORE_NIU: + rate = rv1126_pdcore_get_clk(priv); + break; + case ACLK_PDBUS: + case HCLK_PDBUS: + case PCLK_PDBUS: + case PCLK_WDT: + rate = rv1126_pdbus_get_clk(priv, clk->id); + break; + case ACLK_PDPHP: + case HCLK_PDPHP: + rate = rv1126_pdphp_get_clk(priv, clk->id); + break; + case HCLK_PDAUDIO: + rate = rv1126_pdaudio_get_clk(priv); + break; + case CLK_I2C1: + case CLK_I2C3: + case CLK_I2C4: + case CLK_I2C5: + rate = rv1126_i2c_get_clk(priv, clk->id); + break; + case CLK_SPI1: + rate = rv1126_spi_get_clk(priv); + break; + case CLK_PWM2: + rate = rv1126_pwm_get_clk(priv); + break; + case CLK_SARADC: + rate = rv1126_saradc_get_clk(priv); + break; + case CLK_CRYPTO_CORE: + case CLK_CRYPTO_PKA: + case ACLK_CRYPTO: + rate = rv1126_crypto_get_clk(priv, clk->id); + break; + case CLK_SDMMC: + case HCLK_SDMMC: + case CLK_SDIO: + case HCLK_SDIO: + case CLK_EMMC: + case HCLK_EMMC: + case SCLK_EMMC_SAMPLE: + rate = rv1126_mmc_get_clk(priv, clk->id); + break; + case SCLK_SFC: + rate = rv1126_sfc_get_clk(priv); + break; + case CLK_NANDC: + rate = rv1126_nand_get_clk(priv); + break; + case ACLK_PDVO: + case ACLK_VOP: + rate = rv1126_aclk_vop_get_clk(priv); + break; + case DCLK_VOP: + rate = rv1126_dclk_vop_get_clk(priv); + break; + case CLK_SCR1_CORE: + rate = rv1126_scr1_get_clk(priv); + break; + case CLK_GMAC_SRC: + rate = rv1126_gmac_src_get_clk(priv); + break; + case CLK_GMAC_ETHERNET_OUT: + rate = rv1126_gmac_out_get_clk(priv); + break; + case PCLK_GMAC: + rate = rv1126_pclk_gmac_get_clk(priv); + break; + case DCLK_DECOM: + rate = rv1126_dclk_decom_get_clk(priv); + break; + default: + debug("%s: Unsupported CLK#%ld\n", __func__, clk->id); + return -ENOENT; + } + + return rate; +}; + +static ulong rv1126_clk_set_rate(struct clk *clk, ulong rate) +{ + struct rv1126_clk_priv *priv = dev_get_priv(clk->dev); + ulong ret = 0; + + if (!priv->gpll_hz) { + printf("%s gpll=%lu\n", __func__, priv->gpll_hz); + return -ENOENT; + } + + switch (clk->id) { + case PLL_APLL: + case ARMCLK: + if (priv->armclk_hz) + rv1126_armclk_set_clk(priv, rate); + priv->armclk_hz = rate; + break; + case PLL_CPLL: + ret = rockchip_pll_set_rate(&rv1126_pll_clks[CPLL], priv->cru, + CPLL, rate); + break; + case PLL_HPLL: + ret = rockchip_pll_set_rate(&rv1126_pll_clks[HPLL], priv->cru, + HPLL, rate); + break; + case ACLK_PDBUS: + case HCLK_PDBUS: + case PCLK_PDBUS: + case PCLK_WDT: + ret = rv1126_pdbus_set_clk(priv, clk->id, rate); + break; + case ACLK_PDPHP: + case HCLK_PDPHP: + ret = rv1126_pdphp_set_clk(priv, clk->id, rate); + break; + case HCLK_PDCORE_NIU: + ret = rv1126_pdcore_set_clk(priv, rate); + break; + case HCLK_PDAUDIO: + ret = rv1126_pdaudio_set_clk(priv, rate); + break; + case CLK_I2C1: + case CLK_I2C3: + case CLK_I2C4: + case CLK_I2C5: + ret = rv1126_i2c_set_clk(priv, clk->id, rate); + break; + case CLK_SPI1: + ret = rv1126_spi_set_clk(priv, rate); + break; + case CLK_PWM2: + ret = rv1126_pwm_set_clk(priv, rate); + break; + case CLK_SARADC: + ret = rv1126_saradc_set_clk(priv, rate); + break; + case CLK_CRYPTO_CORE: + case CLK_CRYPTO_PKA: + case ACLK_CRYPTO: + ret = rv1126_crypto_set_clk(priv, clk->id, rate); + break; + case CLK_SDMMC: + case HCLK_SDMMC: + case CLK_SDIO: + case HCLK_SDIO: + case CLK_EMMC: + case HCLK_EMMC: + ret = rv1126_mmc_set_clk(priv, clk->id, rate); + break; + case SCLK_SFC: + ret = rv1126_sfc_set_clk(priv, rate); + break; + case CLK_NANDC: + ret = rv1126_nand_set_clk(priv, rate); + break; + case ACLK_PDVO: + case ACLK_VOP: + ret = rv1126_aclk_vop_set_clk(priv, rate); + break; + case DCLK_VOP: + ret = rv1126_dclk_vop_set_clk(priv, rate); + break; + case CLK_SCR1_CORE: + ret = rv1126_scr1_set_clk(priv, rate); + break; + case CLK_GMAC_SRC: + ret = rv1126_gmac_src_set_clk(priv, rate); + break; + case CLK_GMAC_ETHERNET_OUT: + ret = rv1126_gmac_out_set_clk(priv, rate); + break; + case CLK_GMAC_TX_RX: + ret = rv1126_gmac_tx_rx_set_clk(priv, rate); + break; + case DCLK_DECOM: + ret = rv1126_dclk_decom_set_clk(priv, rate); + break; + default: + debug("%s: Unsupported CLK#%ld\n", __func__, clk->id); + return -ENOENT; + } + + return ret; +}; + +#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +static int rv1126_gmac_src_set_parent(struct clk *clk, struct clk *parent) +{ + struct rv1126_clk_priv *priv = dev_get_priv(clk->dev); + struct rv1126_grf *grf = priv->grf; + + if (parent->id == CLK_GMAC_SRC_M0) + rk_clrsetreg(&grf->iofunc_con1, GMAC_SRC_SEL_MASK, + GMAC_SRC_SEL_M0 << GMAC_SRC_SEL_SHIFT); + else if (parent->id == CLK_GMAC_SRC_M1) + rk_clrsetreg(&grf->iofunc_con1, GMAC_SRC_SEL_MASK, + GMAC_SRC_SEL_M1 << GMAC_SRC_SEL_SHIFT); + + return 0; +} + +static int rv1126_gmac_src_m0_set_parent(struct clk *clk, struct clk *parent) +{ + struct rv1126_clk_priv *priv = dev_get_priv(clk->dev); + struct rv1126_cru *cru = priv->cru; + + if (parent->id == CLK_GMAC_DIV) + rk_clrsetreg(&cru->gmac_con, GMAC_SRC_M0_SEL_MASK, + GMAC_SRC_M0_SEL_INT << GMAC_SRC_M0_SEL_SHIFT); + else + rk_clrsetreg(&cru->gmac_con, GMAC_SRC_M0_SEL_MASK, + GMAC_SRC_M0_SEL_EXT << GMAC_SRC_M0_SEL_SHIFT); + + return 0; +} + +static int rv1126_gmac_src_m1_set_parent(struct clk *clk, struct clk *parent) +{ + struct rv1126_clk_priv *priv = dev_get_priv(clk->dev); + struct rv1126_cru *cru = priv->cru; + + if (parent->id == CLK_GMAC_DIV) + rk_clrsetreg(&cru->gmac_con, GMAC_SRC_M1_SEL_MASK, + GMAC_SRC_M1_SEL_INT << GMAC_SRC_M1_SEL_SHIFT); + else + rk_clrsetreg(&cru->gmac_con, GMAC_SRC_M1_SEL_MASK, + GMAC_SRC_M1_SEL_EXT << GMAC_SRC_M1_SEL_SHIFT); + + return 0; +} + +static int rv1126_gmac_tx_rx_set_parent(struct clk *clk, struct clk *parent) +{ + struct rv1126_clk_priv *priv = dev_get_priv(clk->dev); + struct rv1126_cru *cru = priv->cru; + + if (parent->id == RGMII_MODE_CLK) + rk_clrsetreg(&cru->gmac_con, GMAC_MODE_SEL_MASK, + GMAC_RGMII_MODE << GMAC_MODE_SEL_SHIFT); + else + rk_clrsetreg(&cru->gmac_con, GMAC_MODE_SEL_MASK, + GMAC_RMII_MODE << GMAC_MODE_SEL_SHIFT); + + return 0; +} + +static int rv1126_clk_set_parent(struct clk *clk, struct clk *parent) +{ + switch (clk->id) { + case CLK_GMAC_SRC: + return rv1126_gmac_src_set_parent(clk, parent); + case CLK_GMAC_SRC_M0: + return rv1126_gmac_src_m0_set_parent(clk, parent); + case CLK_GMAC_SRC_M1: + return rv1126_gmac_src_m1_set_parent(clk, parent); + case CLK_GMAC_TX_RX: + return rv1126_gmac_tx_rx_set_parent(clk, parent); + default: + return -ENOENT; + } + + return 0; +} +#endif + +static struct clk_ops rv1126_clk_ops = { + .get_rate = rv1126_clk_get_rate, + .set_rate = rv1126_clk_set_rate, +#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) + .set_parent = rv1126_clk_set_parent, +#endif +}; + +static ulong rv1126_gpll_set_rate(struct rv1126_clk_priv *priv, + struct rv1126_pmuclk_priv *pmu_priv, + ulong rate) +{ + ulong emmc_rate, sfc_rate, nandc_rate; + bool restore = false; + + if (priv->gpll_hz != OSC_HZ) { + emmc_rate = rv1126_mmc_get_clk(priv, CLK_EMMC); + sfc_rate = rv1126_sfc_get_clk(priv); + nandc_rate = rv1126_nand_get_clk(priv); + debug("%s emmc=%lu, sfc=%lu, nandc=%lu\n", __func__, + emmc_rate, sfc_rate, nandc_rate); + restore = true; + } + + /* + * the child div is big enough for gpll 1188MHz, + * even maskrom has change some clocks. + */ + if (rockchip_pll_set_rate(&rv1126_pll_clks[GPLL], + pmu_priv->pmucru, GPLL, rate)) + return -EINVAL; + pmu_priv->gpll_hz = rate; + priv->gpll_hz = rate; + + if (restore) { + rv1126_mmc_set_clk(priv, CLK_EMMC, emmc_rate); + rv1126_sfc_set_clk(priv, sfc_rate); + rv1126_nand_set_clk(priv, nandc_rate); + } + + return 0; +} + +static int rv1126_gpll_set_clk(struct rv1126_clk_priv *priv, ulong rate) +{ + struct udevice *pmucru_dev; + struct rv1126_pmuclk_priv *pmu_priv; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_CLK, + DM_DRIVER_GET(rockchip_rv1126_pmucru), + &pmucru_dev); + if (ret) { + printf("%s: could not find pmucru device\n", __func__); + return ret; + } + pmu_priv = dev_get_priv(pmucru_dev); + priv->gpll_hz = pmu_priv->gpll_hz; + + if (rv1126_gpll_set_rate(priv, pmu_priv, rate)) { + printf("%s: failed to set gpll rate %lu\n", __func__, rate); + return -EINVAL; + } + + rv1126_pdpmu_set_pmuclk(pmu_priv, PCLK_PDPMU_HZ); + rv1126_rtc32k_set_pmuclk(pmu_priv, CLK_OSC0_DIV_HZ); + + return 0; +} + +static void rv1126_clk_init(struct rv1126_clk_priv *priv) +{ + int ret; + + priv->sync_kernel = false; + if (!priv->armclk_enter_hz) { + priv->armclk_enter_hz = + rockchip_pll_get_rate(&rv1126_pll_clks[APLL], + priv->cru, APLL); + priv->armclk_init_hz = priv->armclk_enter_hz; + } + + if (priv->armclk_init_hz != APLL_HZ) { + ret = rv1126_armclk_set_clk(priv, APLL_HZ); + if (!ret) + priv->armclk_init_hz = APLL_HZ; + } + if (priv->cpll_hz != CPLL_HZ) { + ret = rockchip_pll_set_rate(&rv1126_pll_clks[CPLL], priv->cru, + CPLL, CPLL_HZ); + if (!ret) + priv->cpll_hz = CPLL_HZ; + } + if (priv->hpll_hz != HPLL_HZ) { + ret = rockchip_pll_set_rate(&rv1126_pll_clks[HPLL], priv->cru, + HPLL, HPLL_HZ); + if (!ret) + priv->hpll_hz = HPLL_HZ; + } + if (priv->gpll_hz != GPLL_HZ) + rv1126_gpll_set_clk(priv, GPLL_HZ); + + rv1126_pdbus_set_clk(priv, ACLK_PDBUS, ACLK_PDBUS_HZ); + rv1126_pdbus_set_clk(priv, HCLK_PDBUS, HCLK_PDBUS_HZ); + rv1126_pdbus_set_clk(priv, PCLK_PDBUS, PCLK_PDBUS_HZ); + rv1126_pdphp_set_clk(priv, ACLK_PDPHP, ACLK_PDPHP_HZ); + rv1126_pdphp_set_clk(priv, HCLK_PDPHP, HCLK_PDPHP_HZ); + rv1126_pdcore_set_clk(priv, HCLK_PDCORE_HZ); + rv1126_pdaudio_set_clk(priv, HCLK_PDAUDIO_HZ); +} + +static int rv1126_clk_probe(struct udevice *dev) +{ + struct rv1126_clk_priv *priv = dev_get_priv(dev); + int ret; + + priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + if (IS_ERR(priv->grf)) + return PTR_ERR(priv->grf); + + rv1126_clk_init(priv); + + /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ + ret = clk_set_defaults(dev, 1); + if (ret) + debug("%s clk_set_defaults failed %d\n", __func__, ret); + else + priv->sync_kernel = true; + + return 0; +} + +static int rv1126_clk_of_to_plat(struct udevice *dev) +{ + struct rv1126_clk_priv *priv = dev_get_priv(dev); + + priv->cru = dev_read_addr_ptr(dev); + + return 0; +} + +static int rv1126_clk_bind(struct udevice *dev) +{ + int ret; + struct udevice *sys_child; + struct sysreset_reg *priv; + + /* The reset driver does not have a device node, so bind it here */ + ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset", + &sys_child); + if (ret) { + debug("Warning: No sysreset driver: ret=%d\n", ret); + } else { + priv = malloc(sizeof(struct sysreset_reg)); + priv->glb_srst_fst_value = offsetof(struct rv1126_cru, + glb_srst_fst); + priv->glb_srst_snd_value = offsetof(struct rv1126_cru, + glb_srst_snd); + dev_set_priv(sys_child, priv); + } + +#if CONFIG_IS_ENABLED(RESET_ROCKCHIP) + ret = offsetof(struct rv1126_cru, softrst_con[0]); + ret = rockchip_reset_bind(dev, ret, 15); + if (ret) + debug("Warning: software reset driver bind faile\n"); +#endif + return 0; +} + +static const struct udevice_id rv1126_clk_ids[] = { + { .compatible = "rockchip,rv1126-cru" }, + { } +}; + +U_BOOT_DRIVER(rockchip_rv1126_cru) = { + .name = "rockchip_rv1126_cru", + .id = UCLASS_CLK, + .of_match = rv1126_clk_ids, + .priv_auto = sizeof(struct rv1126_clk_priv), + .of_to_plat = rv1126_clk_of_to_plat, + .ops = &rv1126_clk_ops, + .bind = rv1126_clk_bind, + .probe = rv1126_clk_probe, +}; diff --git a/drivers/pinctrl/rockchip/Makefile b/drivers/pinctrl/rockchip/Makefile index 7d03f8101df..98843554733 100644 --- a/drivers/pinctrl/rockchip/Makefile +++ b/drivers/pinctrl/rockchip/Makefile @@ -15,3 +15,4 @@ obj-$(CONFIG_ROCKCHIP_RK3328) += pinctrl-rk3328.o obj-$(CONFIG_ROCKCHIP_RK3368) += pinctrl-rk3368.o obj-$(CONFIG_ROCKCHIP_RK3399) += pinctrl-rk3399.o obj-$(CONFIG_ROCKCHIP_RV1108) += pinctrl-rv1108.o +obj-$(CONFIG_ROCKCHIP_RV1126) += pinctrl-rv1126.o diff --git a/drivers/pinctrl/rockchip/pinctrl-px30.c b/drivers/pinctrl/rockchip/pinctrl-px30.c index 9de29c0b8b4..2c35491b24d 100644 --- a/drivers/pinctrl/rockchip/pinctrl-px30.c +++ b/drivers/pinctrl/rockchip/pinctrl-px30.c @@ -80,7 +80,7 @@ static int px30_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) struct regmap *regmap; int reg, ret, mask, mux_type; u8 bit; - u32 data, route_reg, route_val; + u32 data; regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) ? priv->regmap_pmu : priv->regmap_base; @@ -90,15 +90,6 @@ static int px30_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) reg = bank->iomux[iomux_num].offset; reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask); - if (bank->route_mask & BIT(pin)) { - if (rockchip_get_mux_route(bank, pin, mux, &route_reg, - &route_val)) { - ret = regmap_write(regmap, route_reg, route_val); - if (ret) - return ret; - } - } - data = (mask << (bit + 16)); data |= (mux & mask) << bit; ret = regmap_write(regmap, reg, data); diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3128.c b/drivers/pinctrl/rockchip/pinctrl-rk3128.c index e6dc1af86e9..355c45eb7f8 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3128.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3128.c @@ -106,7 +106,7 @@ static int rk3128_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) struct regmap *regmap; int reg, ret, mask, mux_type; u8 bit; - u32 data, route_reg, route_val; + u32 data; regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) ? priv->regmap_pmu : priv->regmap_base; @@ -119,15 +119,6 @@ static int rk3128_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) if (bank->recalced_mask & BIT(pin)) rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); - if (bank->route_mask & BIT(pin)) { - if (rockchip_get_mux_route(bank, pin, mux, &route_reg, - &route_val)) { - ret = regmap_write(regmap, route_reg, route_val); - if (ret) - return ret; - } - } - data = (mask << (bit + 16)); data |= (mux & mask) << bit; ret = regmap_write(regmap, reg, data); diff --git a/drivers/pinctrl/rockchip/pinctrl-rk322x.c b/drivers/pinctrl/rockchip/pinctrl-rk322x.c index 7c58f40d93d..351406da2d4 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk322x.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk322x.c @@ -150,7 +150,7 @@ static int rk3228_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) struct regmap *regmap; int reg, ret, mask, mux_type; u8 bit; - u32 data, route_reg, route_val; + u32 data; regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) ? priv->regmap_pmu : priv->regmap_base; @@ -160,15 +160,6 @@ static int rk3228_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) reg = bank->iomux[iomux_num].offset; reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask); - if (bank->route_mask & BIT(pin)) { - if (rockchip_get_mux_route(bank, pin, mux, &route_reg, - &route_val)) { - ret = regmap_write(regmap, route_reg, route_val); - if (ret) - return ret; - } - } - data = (mask << (bit + 16)); data |= (mux & mask) << bit; ret = regmap_write(regmap, reg, data); diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3288.c b/drivers/pinctrl/rockchip/pinctrl-rk3288.c index 5894f47f534..a976b7aeeb2 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3288.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3288.c @@ -37,7 +37,7 @@ static int rk3288_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) struct regmap *regmap; int reg, ret, mask, mux_type; u8 bit; - u32 data, route_reg, route_val; + u32 data; regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) ? priv->regmap_pmu : priv->regmap_base; @@ -47,15 +47,6 @@ static int rk3288_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) reg = bank->iomux[iomux_num].offset; reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask); - if (bank->route_mask & BIT(pin)) { - if (rockchip_get_mux_route(bank, pin, mux, &route_reg, - &route_val)) { - ret = regmap_write(regmap, route_reg, route_val); - if (ret) - return ret; - } - } - /* bank0 is special, there are no higher 16 bit writing bits. */ if (bank->bank_num == 0) { regmap_read(regmap, reg, &data); diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3308.c b/drivers/pinctrl/rockchip/pinctrl-rk3308.c index 83186f40f6f..f9ac6347eaf 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3308.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3308.c @@ -258,7 +258,7 @@ static int rk3308_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) struct regmap *regmap; int reg, ret, mask, mux_type; u8 bit; - u32 data, route_reg, route_val; + u32 data; regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) ? priv->regmap_pmu : priv->regmap_base; @@ -271,15 +271,6 @@ static int rk3308_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) if (bank->recalced_mask & BIT(pin)) rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); - if (bank->route_mask & BIT(pin)) { - if (rockchip_get_mux_route(bank, pin, mux, &route_reg, - &route_val)) { - ret = regmap_write(regmap, route_reg, route_val); - if (ret) - return ret; - } - } - data = (mask << (bit + 16)); data |= (mux & mask) << bit; ret = regmap_write(regmap, reg, data); diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3328.c b/drivers/pinctrl/rockchip/pinctrl-rk3328.c index 1c3c5986a50..65a75007677 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3328.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3328.c @@ -130,7 +130,7 @@ static int rk3328_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) struct regmap *regmap; int reg, ret, mask, mux_type; u8 bit; - u32 data, route_reg, route_val; + u32 data; regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) ? priv->regmap_pmu : priv->regmap_base; @@ -143,15 +143,6 @@ static int rk3328_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) if (bank->recalced_mask & BIT(pin)) rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); - if (bank->route_mask & BIT(pin)) { - if (rockchip_get_mux_route(bank, pin, mux, &route_reg, - &route_val)) { - ret = regmap_write(regmap, route_reg, route_val); - if (ret) - return ret; - } - } - data = (mask << (bit + 16)); data |= (mux & mask) << bit; ret = regmap_write(regmap, reg, data); diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3399.c b/drivers/pinctrl/rockchip/pinctrl-rk3399.c index caa92200c6e..ae785573baf 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3399.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3399.c @@ -59,7 +59,7 @@ static int rk3399_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) struct regmap *regmap; int reg, ret, mask, mux_type; u8 bit; - u32 data, route_reg, route_val; + u32 data; regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) ? priv->regmap_pmu : priv->regmap_base; @@ -69,15 +69,6 @@ static int rk3399_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) reg = bank->iomux[iomux_num].offset; reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask); - if (bank->route_mask & BIT(pin)) { - if (rockchip_get_mux_route(bank, pin, mux, &route_reg, - &route_val)) { - ret = regmap_write(regmap, route_reg, route_val); - if (ret) - return ret; - } - } - data = (mask << (bit + 16)); data |= (mux & mask) << bit; ret = regmap_write(regmap, reg, data); diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c index 630513ba3a2..d9d61fdb726 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c +++ b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c @@ -62,8 +62,9 @@ void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, *bit = data->bit; } -bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, - int mux, u32 *reg, u32 *value) +static enum rockchip_pin_route_type +rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, + int mux, u32 *reg, u32 *value) { struct rockchip_pinctrl_priv *priv = bank->priv; struct rockchip_pin_ctrl *ctrl = priv->ctrl; @@ -78,12 +79,12 @@ bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, } if (i >= ctrl->niomux_routes) - return false; + return ROUTE_TYPE_INVALID; *reg = data->route_offset; *value = data->route_val; - return true; + return data->route_type; } int rockchip_get_mux_data(int mux_type, int pin, u8 *bit, int *mask) @@ -214,8 +215,40 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) return -ENOTSUPP; ret = ctrl->set_mux(bank, pin, mux); + if (ret) + return ret; - return ret; + if (bank->route_mask & BIT(pin)) { + struct regmap *regmap; + u32 route_reg = 0, route_val = 0; + + ret = rockchip_get_mux_route(bank, pin, mux, + &route_reg, &route_val); + switch (ret) { + case ROUTE_TYPE_DEFAULT: + if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) + regmap = priv->regmap_pmu; + else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU) + regmap = (pin % 8 < 4) ? priv->regmap_pmu : priv->regmap_base; + else + regmap = priv->regmap_base; + + regmap_write(regmap, route_reg, route_val); + break; + case ROUTE_TYPE_TOPGRF: + regmap_write(priv->regmap_base, route_reg, route_val); + break; + case ROUTE_TYPE_PMUGRF: + regmap_write(priv->regmap_pmu, route_reg, route_val); + break; + case ROUTE_TYPE_INVALID: + fallthrough; + default: + break; + } + } + + return 0; } static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = { @@ -545,7 +578,7 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(struct udevice *d inc = (iom->type & (IOMUX_WIDTH_4BIT | IOMUX_WIDTH_3BIT | IOMUX_8WIDTH_2BIT)) ? 8 : 4; - if (iom->type & IOMUX_SOURCE_PMU) + if ((iom->type & IOMUX_SOURCE_PMU) || (iom->type & IOMUX_L_SOURCE_PMU)) pmu_offs += inc; else grf_offs += inc; diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip.h b/drivers/pinctrl/rockchip/pinctrl-rockchip.h index d969c200826..8dfaba5c74d 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rockchip.h +++ b/drivers/pinctrl/rockchip/pinctrl-rockchip.h @@ -9,6 +9,9 @@ #include <linux/bitops.h> #include <linux/types.h> +#define RK_GENMASK_VAL(h, l, v) \ + (GENMASK(((h) + 16), ((l) + 16)) | (((v) << (l)) & GENMASK((h), (l)))) + /** * Encode variants of iomux registers into a type variable */ @@ -18,6 +21,7 @@ #define IOMUX_UNROUTED BIT(3) #define IOMUX_WIDTH_3BIT BIT(4) #define IOMUX_8WIDTH_2BIT BIT(5) +#define IOMUX_L_SOURCE_PMU BIT(6) /** * Defined some common pins constants @@ -63,6 +67,22 @@ enum rockchip_pin_pull_type { }; /** + * Rockchip pinctrl route type + * + * DEFAULT : Same regmap as pin iomux + * TOPGRF : Mux route setting in topgrf + * PMUGRF : Mux route setting in pmugrf + * INVALID : Nnot need to set mux route + */ +enum rockchip_pin_route_type { + ROUTE_TYPE_DEFAULT = 0, + ROUTE_TYPE_TOPGRF = 1, + ROUTE_TYPE_PMUGRF = 2, + + ROUTE_TYPE_INVALID = -1, +}; + +/** * @drv_type: drive strength variant using rockchip_perpin_drv_type * @offset: if initialized to -1 it will be autocalculated, by specifying * an initial offset value the relevant source offset can be reset @@ -126,6 +146,21 @@ struct rockchip_pin_bank { }, \ } +#define PIN_BANK_IOMUX_FLAGS_OFFSET(id, pins, label, iom0, iom1, iom2, \ + iom3, offset0, offset1, offset2, \ + offset3) \ + { \ + .bank_num = id, \ + .nr_pins = pins, \ + .name = label, \ + .iomux = { \ + { .type = iom0, .offset = offset0 }, \ + { .type = iom1, .offset = offset1 }, \ + { .type = iom2, .offset = offset2 }, \ + { .type = iom3, .offset = offset3 }, \ + }, \ + } + #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \ { \ .bank_num = id, \ @@ -220,6 +255,25 @@ struct rockchip_pin_bank { .pull_type[3] = pull3, \ } +#define PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, FLAG) \ + { \ + .bank_num = ID, \ + .pin = PIN, \ + .func = FUNC, \ + .route_offset = REG, \ + .route_val = VAL, \ + .route_type = FLAG, \ + } + +#define MR_DEFAULT(ID, PIN, FUNC, REG, VAL) \ + PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROUTE_TYPE_DEFAULT) + +#define MR_TOPGRF(ID, PIN, FUNC, REG, VAL) \ + PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROUTE_TYPE_TOPGRF) + +#define MR_PMUGRF(ID, PIN, FUNC, REG, VAL) \ + PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROUTE_TYPE_PMUGRF) + /** * struct rockchip_mux_recalced_data: recalculate a pin iomux data. * @num: bank number. @@ -241,6 +295,7 @@ struct rockchip_mux_recalced_data { * @bank_num: bank number. * @pin: index at register or used to calc index. * @func: the min pin. + * @route_type: the register type. * @route_offset: the max pin. * @route_val: the register offset. */ @@ -248,6 +303,7 @@ struct rockchip_mux_route_data { u8 bank_num; u8 pin; u8 func; + enum rockchip_pin_route_type route_type : 8; u32 route_offset; u32 route_val; }; @@ -289,8 +345,6 @@ extern const struct pinctrl_ops rockchip_pinctrl_ops; int rockchip_pinctrl_probe(struct udevice *dev); void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, int *reg, u8 *bit, int *mask); -bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, - int mux, u32 *reg, u32 *value); int rockchip_get_mux_data(int mux_type, int pin, u8 *bit, int *mask); int rockchip_translate_drive_value(int type, int strength); int rockchip_translate_pull_value(int type, int pull); diff --git a/drivers/pinctrl/rockchip/pinctrl-rv1126.c b/drivers/pinctrl/rockchip/pinctrl-rv1126.c new file mode 100644 index 00000000000..eefb8b17768 --- /dev/null +++ b/drivers/pinctrl/rockchip/pinctrl-rv1126.c @@ -0,0 +1,416 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2020 Rockchip Electronics Co., Ltd + */ + +#include <common.h> +#include <dm.h> +#include <log.h> +#include <dm/pinctrl.h> +#include <regmap.h> +#include <syscon.h> +#include <linux/bitops.h> +#include <dt-bindings/pinctrl/rockchip.h> + +#include "pinctrl-rockchip.h" + +static struct rockchip_mux_recalced_data rv1126_mux_recalced_data[] = { + { + .num = 0, + .pin = 20, + .reg = 0x10000, + .bit = 0, + .mask = 0xf + }, + { + .num = 0, + .pin = 21, + .reg = 0x10000, + .bit = 4, + .mask = 0xf + }, + { + .num = 0, + .pin = 22, + .reg = 0x10000, + .bit = 8, + .mask = 0xf + }, + { + .num = 0, + .pin = 23, + .reg = 0x10000, + .bit = 12, + .mask = 0xf + }, +}; + +static struct rockchip_mux_route_data rv1126_mux_route_data[] = { + MR_TOPGRF(RK_GPIO3, RK_PD2, 1, 0x10260, RK_GENMASK_VAL(0, 0, 0)), /* I2S0_MCLK_M0 */ + MR_TOPGRF(RK_GPIO3, RK_PB0, 3, 0x10260, RK_GENMASK_VAL(0, 0, 1)), /* I2S0_MCLK_M1 */ + + MR_TOPGRF(RK_GPIO0, RK_PD4, 4, 0x10260, RK_GENMASK_VAL(3, 2, 0)), /* I2S1_MCLK_M0 */ + MR_TOPGRF(RK_GPIO1, RK_PD5, 2, 0x10260, RK_GENMASK_VAL(3, 2, 1)), /* I2S1_MCLK_M1 */ + MR_TOPGRF(RK_GPIO2, RK_PC7, 6, 0x10260, RK_GENMASK_VAL(3, 2, 2)), /* I2S1_MCLK_M2 */ + + MR_TOPGRF(RK_GPIO1, RK_PD0, 1, 0x10260, RK_GENMASK_VAL(4, 4, 0)), /* I2S2_MCLK_M0 */ + MR_TOPGRF(RK_GPIO2, RK_PB3, 2, 0x10260, RK_GENMASK_VAL(4, 4, 1)), /* I2S2_MCLK_M1 */ + + MR_TOPGRF(RK_GPIO3, RK_PD4, 2, 0x10260, RK_GENMASK_VAL(12, 12, 0)), /* PDM_CLK0_M0 */ + MR_TOPGRF(RK_GPIO3, RK_PC0, 3, 0x10260, RK_GENMASK_VAL(12, 12, 1)), /* PDM_CLK0_M1 */ + + MR_TOPGRF(RK_GPIO3, RK_PC6, 1, 0x10264, RK_GENMASK_VAL(0, 0, 0)), /* CIF_CLKOUT_M0 */ + MR_TOPGRF(RK_GPIO2, RK_PD1, 3, 0x10264, RK_GENMASK_VAL(0, 0, 1)), /* CIF_CLKOUT_M1 */ + + MR_TOPGRF(RK_GPIO3, RK_PA4, 5, 0x10264, RK_GENMASK_VAL(5, 4, 0)), /* I2C3_SCL_M0 */ + MR_TOPGRF(RK_GPIO2, RK_PD4, 7, 0x10264, RK_GENMASK_VAL(5, 4, 1)), /* I2C3_SCL_M1 */ + MR_TOPGRF(RK_GPIO1, RK_PD6, 3, 0x10264, RK_GENMASK_VAL(5, 4, 2)), /* I2C3_SCL_M2 */ + + MR_TOPGRF(RK_GPIO3, RK_PA0, 7, 0x10264, RK_GENMASK_VAL(6, 6, 0)), /* I2C4_SCL_M0 */ + MR_TOPGRF(RK_GPIO4, RK_PA0, 4, 0x10264, RK_GENMASK_VAL(6, 6, 1)), /* I2C4_SCL_M1 */ + + MR_TOPGRF(RK_GPIO2, RK_PA5, 7, 0x10264, RK_GENMASK_VAL(9, 8, 0)), /* I2C5_SCL_M0 */ + MR_TOPGRF(RK_GPIO3, RK_PB0, 5, 0x10264, RK_GENMASK_VAL(9, 8, 1)), /* I2C5_SCL_M1 */ + MR_TOPGRF(RK_GPIO1, RK_PD0, 4, 0x10264, RK_GENMASK_VAL(9, 8, 2)), /* I2C5_SCL_M2 */ + + MR_TOPGRF(RK_GPIO3, RK_PC0, 5, 0x10264, RK_GENMASK_VAL(11, 10, 0)), /* SPI1_CLK_M0 */ + MR_TOPGRF(RK_GPIO1, RK_PC6, 3, 0x10264, RK_GENMASK_VAL(11, 10, 1)), /* SPI1_CLK_M1 */ + MR_TOPGRF(RK_GPIO2, RK_PD5, 6, 0x10264, RK_GENMASK_VAL(11, 10, 2)), /* SPI1_CLK_M2 */ + + MR_TOPGRF(RK_GPIO3, RK_PC0, 2, 0x10264, RK_GENMASK_VAL(12, 12, 0)), /* RGMII_CLK_M0 */ + MR_TOPGRF(RK_GPIO2, RK_PB7, 2, 0x10264, RK_GENMASK_VAL(12, 12, 1)), /* RGMII_CLK_M1 */ + + MR_TOPGRF(RK_GPIO3, RK_PA1, 3, 0x10264, RK_GENMASK_VAL(13, 13, 0)), /* CAN_TXD_M0 */ + MR_TOPGRF(RK_GPIO3, RK_PA7, 5, 0x10264, RK_GENMASK_VAL(13, 13, 1)), /* CAN_TXD_M1 */ + + MR_TOPGRF(RK_GPIO3, RK_PA4, 6, 0x10268, RK_GENMASK_VAL(0, 0, 0)), /* PWM8_M0 */ + MR_TOPGRF(RK_GPIO2, RK_PD7, 5, 0x10268, RK_GENMASK_VAL(0, 0, 1)), /* PWM8_M1 */ + + MR_TOPGRF(RK_GPIO3, RK_PA5, 6, 0x10268, RK_GENMASK_VAL(2, 2, 0)), /* PWM9_M0 */ + MR_TOPGRF(RK_GPIO2, RK_PD6, 5, 0x10268, RK_GENMASK_VAL(2, 2, 1)), /* PWM9_M1 */ + + MR_TOPGRF(RK_GPIO3, RK_PA6, 6, 0x10268, RK_GENMASK_VAL(4, 4, 0)), /* PWM10_M0 */ + MR_TOPGRF(RK_GPIO2, RK_PD5, 5, 0x10268, RK_GENMASK_VAL(4, 4, 1)), /* PWM10_M1 */ + + MR_TOPGRF(RK_GPIO3, RK_PA7, 6, 0x10268, RK_GENMASK_VAL(6, 6, 0)), /* PWM11_IR_M0 */ + MR_TOPGRF(RK_GPIO3, RK_PA1, 5, 0x10268, RK_GENMASK_VAL(6, 6, 1)), /* PWM11_IR_M1 */ + + MR_TOPGRF(RK_GPIO1, RK_PA5, 3, 0x10268, RK_GENMASK_VAL(8, 8, 0)), /* UART2_TX_M0 */ + MR_TOPGRF(RK_GPIO3, RK_PA2, 1, 0x10268, RK_GENMASK_VAL(8, 8, 1)), /* UART2_TX_M1 */ + + MR_TOPGRF(RK_GPIO3, RK_PC6, 3, 0x10268, RK_GENMASK_VAL(11, 10, 0)), /* UART3_TX_M0 */ + MR_TOPGRF(RK_GPIO1, RK_PA7, 2, 0x10268, RK_GENMASK_VAL(11, 10, 1)), /* UART3_TX_M1 */ + MR_TOPGRF(RK_GPIO3, RK_PA0, 4, 0x10268, RK_GENMASK_VAL(11, 10, 2)), /* UART3_TX_M2 */ + + MR_TOPGRF(RK_GPIO3, RK_PA4, 4, 0x10268, RK_GENMASK_VAL(13, 12, 0)), /* UART4_TX_M0 */ + MR_TOPGRF(RK_GPIO2, RK_PA6, 4, 0x10268, RK_GENMASK_VAL(13, 12, 1)), /* UART4_TX_M1 */ + MR_TOPGRF(RK_GPIO1, RK_PD5, 3, 0x10268, RK_GENMASK_VAL(13, 12, 2)), /* UART4_TX_M2 */ + + MR_TOPGRF(RK_GPIO3, RK_PA6, 4, 0x10268, RK_GENMASK_VAL(15, 14, 0)), /* UART5_TX_M0 */ + MR_TOPGRF(RK_GPIO2, RK_PB0, 4, 0x10268, RK_GENMASK_VAL(15, 14, 1)), /* UART5_TX_M1 */ + MR_TOPGRF(RK_GPIO2, RK_PA0, 3, 0x10268, RK_GENMASK_VAL(15, 14, 2)), /* UART5_TX_M2 */ + + MR_PMUGRF(RK_GPIO0, RK_PB6, 3, 0x0114, RK_GENMASK_VAL(0, 0, 0)), /* PWM0_M0 */ + MR_PMUGRF(RK_GPIO2, RK_PB3, 5, 0x0114, RK_GENMASK_VAL(0, 0, 1)), /* PWM0_M1 */ + + MR_PMUGRF(RK_GPIO0, RK_PB7, 3, 0x0114, RK_GENMASK_VAL(2, 2, 0)), /* PWM1_M0 */ + MR_PMUGRF(RK_GPIO2, RK_PB2, 5, 0x0114, RK_GENMASK_VAL(2, 2, 1)), /* PWM1_M1 */ + + MR_PMUGRF(RK_GPIO0, RK_PC0, 3, 0x0114, RK_GENMASK_VAL(4, 4, 0)), /* PWM2_M0 */ + MR_PMUGRF(RK_GPIO2, RK_PB1, 5, 0x0114, RK_GENMASK_VAL(4, 4, 1)), /* PWM2_M1 */ + + MR_PMUGRF(RK_GPIO0, RK_PC1, 3, 0x0114, RK_GENMASK_VAL(6, 6, 0)), /* PWM3_IR_M0 */ + MR_PMUGRF(RK_GPIO2, RK_PB0, 5, 0x0114, RK_GENMASK_VAL(6, 6, 1)), /* PWM3_IR_M1 */ + + MR_PMUGRF(RK_GPIO0, RK_PC2, 3, 0x0114, RK_GENMASK_VAL(8, 8, 0)), /* PWM4_M0 */ + MR_PMUGRF(RK_GPIO2, RK_PA7, 5, 0x0114, RK_GENMASK_VAL(8, 8, 1)), /* PWM4_M1 */ + + MR_PMUGRF(RK_GPIO0, RK_PC3, 3, 0x0114, RK_GENMASK_VAL(10, 10, 0)), /* PWM5_M0 */ + MR_PMUGRF(RK_GPIO2, RK_PA6, 5, 0x0114, RK_GENMASK_VAL(10, 10, 1)), /* PWM5_M1 */ + + MR_PMUGRF(RK_GPIO0, RK_PB2, 3, 0x0114, RK_GENMASK_VAL(12, 12, 0)), /* PWM6_M0 */ + MR_PMUGRF(RK_GPIO2, RK_PD4, 5, 0x0114, RK_GENMASK_VAL(12, 12, 1)), /* PWM6_M1 */ + + MR_PMUGRF(RK_GPIO0, RK_PB1, 3, 0x0114, RK_GENMASK_VAL(14, 14, 0)), /* PWM7_IR_M0 */ + MR_PMUGRF(RK_GPIO3, RK_PA0, 5, 0x0114, RK_GENMASK_VAL(14, 14, 1)), /* PWM7_IR_M1 */ + + MR_PMUGRF(RK_GPIO0, RK_PB0, 1, 0x0118, RK_GENMASK_VAL(1, 0, 0)), /* SPI0_CLK_M0 */ + MR_PMUGRF(RK_GPIO2, RK_PA1, 1, 0x0118, RK_GENMASK_VAL(1, 0, 1)), /* SPI0_CLK_M1 */ + MR_PMUGRF(RK_GPIO2, RK_PB2, 6, 0x0118, RK_GENMASK_VAL(1, 0, 2)), /* SPI0_CLK_M2 */ + + MR_PMUGRF(RK_GPIO0, RK_PB6, 2, 0x0118, RK_GENMASK_VAL(2, 2, 0)), /* UART1_TX_M0 */ + MR_PMUGRF(RK_GPIO1, RK_PD0, 5, 0x0118, RK_GENMASK_VAL(2, 2, 1)), /* UART1_TX_M1 */ + MR_PMUGRF(RK_GPIO0, RK_PC3, 1, 0x0118, RK_GENMASK_VAL(4, 4, 1)), /* I2C2 */ +}; + +static int rv1126_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + int iomux_num = (pin / 8); + struct regmap *regmap; + int reg, ret, mask, mux_type; + u8 bit; + u32 data; + + debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux); + + if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) + regmap = priv->regmap_pmu; + else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU) + regmap = (pin % 8 < 4) ? priv->regmap_pmu : priv->regmap_base; + else + regmap = priv->regmap_base; + + /* get basic quadrupel of mux registers and the correct reg inside */ + mux_type = bank->iomux[iomux_num].type; + reg = bank->iomux[iomux_num].offset; + if (mux_type & IOMUX_WIDTH_4BIT) { + if ((pin % 8) >= 4) + reg += 0x4; + bit = (pin % 4) * 4; + mask = 0xf; + } else { + bit = (pin % 8) * 2; + mask = 0x3; + } + + if (bank->recalced_mask & BIT(pin)) + rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); + + data = (mask << (bit + 16)); + data |= (mux & mask) << bit; + ret = regmap_write(regmap, reg, data); + + return ret; +} + +#define RV1126_PULL_PMU_OFFSET 0x40 +#define RV1126_PULL_GRF_GPIO1A0_OFFSET 0x10108 +#define RV1126_PULL_PINS_PER_REG 8 +#define RV1126_PULL_BITS_PER_PIN 2 +#define RV1126_PULL_BANK_STRIDE 16 +#define RV1126_GPIO_C4_D7(p) (p >= 20 && p <= 31) /* GPIO0_C4 ~ GPIO0_D7 */ + +static void rv1126_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + + /* The first 24 pins of the first bank are located in PMU */ + if (bank->bank_num == 0) { + if (RV1126_GPIO_C4_D7(pin_num)) { + *regmap = priv->regmap_base; + *reg = RV1126_PULL_GRF_GPIO1A0_OFFSET; + *reg -= (((31 - pin_num) / RV1126_PULL_PINS_PER_REG + 1) * 4); + *bit = pin_num % RV1126_PULL_PINS_PER_REG; + *bit *= RV1126_PULL_BITS_PER_PIN; + return; + } + *regmap = priv->regmap_pmu; + *reg = RV1126_PULL_PMU_OFFSET; + } else { + *reg = RV1126_PULL_GRF_GPIO1A0_OFFSET; + *regmap = priv->regmap_base; + *reg += (bank->bank_num - 1) * RV1126_PULL_BANK_STRIDE; + } + + *reg += ((pin_num / RV1126_PULL_PINS_PER_REG) * 4); + *bit = (pin_num % RV1126_PULL_PINS_PER_REG); + *bit *= RV1126_PULL_BITS_PER_PIN; +} + +static int rv1126_set_pull(struct rockchip_pin_bank *bank, + int pin_num, int pull) +{ + struct regmap *regmap; + int reg, ret; + u8 bit, type; + u32 data; + + if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT) + return -EOPNOTSUPP; + + rv1126_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit); + type = bank->pull_type[pin_num / 8]; + ret = rockchip_translate_pull_value(type, pull); + if (ret < 0) { + debug("unsupported pull setting %d\n", pull); + return ret; + } + + /* enable the write to the equivalent lower bits */ + data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16); + + data |= (ret << bit); + ret = regmap_write(regmap, reg, data); + + return ret; +} + +#define RV1126_DRV_PMU_OFFSET 0x20 +#define RV1126_DRV_GRF_GPIO1A0_OFFSET 0x10090 +#define RV1126_DRV_BITS_PER_PIN 4 +#define RV1126_DRV_PINS_PER_REG 4 +#define RV1126_DRV_BANK_STRIDE 32 + +static void rv1126_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + + /* The first 24 pins of the first bank are located in PMU */ + if (bank->bank_num == 0) { + if (RV1126_GPIO_C4_D7(pin_num)) { + *regmap = priv->regmap_base; + *reg = RV1126_DRV_GRF_GPIO1A0_OFFSET; + *reg -= (((31 - pin_num) / RV1126_DRV_PINS_PER_REG + 1) * 4); + *reg -= 0x4; + *bit = pin_num % RV1126_DRV_PINS_PER_REG; + *bit *= RV1126_DRV_BITS_PER_PIN; + return; + } + *regmap = priv->regmap_pmu; + *reg = RV1126_DRV_PMU_OFFSET; + } else { + *regmap = priv->regmap_base; + *reg = RV1126_DRV_GRF_GPIO1A0_OFFSET; + *reg += (bank->bank_num - 1) * RV1126_DRV_BANK_STRIDE; + } + + *reg += ((pin_num / RV1126_DRV_PINS_PER_REG) * 4); + *bit = pin_num % RV1126_DRV_PINS_PER_REG; + *bit *= RV1126_DRV_BITS_PER_PIN; +} + +static int rv1126_set_drive(struct rockchip_pin_bank *bank, + int pin_num, int strength) +{ + struct regmap *regmap; + int reg; + u32 data; + u8 bit; + + rv1126_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit); + + /* enable the write to the equivalent lower bits */ + data = ((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << (bit + 16); + data |= (strength << bit); + + return regmap_write(regmap, reg, data); +} + +#define RV1126_SCHMITT_PMU_OFFSET 0x60 +#define RV1126_SCHMITT_GRF_GPIO1A0_OFFSET 0x10188 +#define RV1126_SCHMITT_BANK_STRIDE 16 +#define RV1126_SCHMITT_PINS_PER_GRF_REG 8 +#define RV1126_SCHMITT_PINS_PER_PMU_REG 8 + +static int rv1126_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, + struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + int pins_per_reg; + + if (bank->bank_num == 0) { + if (RV1126_GPIO_C4_D7(pin_num)) { + *regmap = priv->regmap_base; + *reg = RV1126_SCHMITT_GRF_GPIO1A0_OFFSET; + *reg -= (((31 - pin_num) / RV1126_SCHMITT_PINS_PER_GRF_REG + 1) * 4); + *bit = pin_num % RV1126_SCHMITT_PINS_PER_GRF_REG; + return 0; + } + *regmap = priv->regmap_pmu; + *reg = RV1126_SCHMITT_PMU_OFFSET; + pins_per_reg = RV1126_SCHMITT_PINS_PER_PMU_REG; + } else { + *regmap = priv->regmap_base; + *reg = RV1126_SCHMITT_GRF_GPIO1A0_OFFSET; + pins_per_reg = RV1126_SCHMITT_PINS_PER_GRF_REG; + *reg += (bank->bank_num - 1) * RV1126_SCHMITT_BANK_STRIDE; + } + *reg += ((pin_num / pins_per_reg) * 4); + *bit = pin_num % pins_per_reg; + + return 0; +} + +static int rv1126_set_schmitt(struct rockchip_pin_bank *bank, + int pin_num, int enable) +{ + struct regmap *regmap; + int reg; + u8 bit; + u32 data; + + rv1126_calc_schmitt_reg_and_bit(bank, pin_num, ®map, ®, &bit); + /* enable the write to the equivalent lower bits */ + data = BIT(bit + 16) | (enable << bit); + + return regmap_write(regmap, reg, data); +} + +static struct rockchip_pin_bank rv1126_pin_banks[] = { + PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", + IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU, + IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU, + IOMUX_WIDTH_4BIT | IOMUX_L_SOURCE_PMU, + IOMUX_WIDTH_4BIT), + PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0x10010, 0x10018, 0x10020, 0x10028), + PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT), + PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT), + PIN_BANK_IOMUX_FLAGS(4, 2, "gpio4", + IOMUX_WIDTH_4BIT, 0, 0, 0), +}; + +static const struct rockchip_pin_ctrl rv1126_pin_ctrl = { + .pin_banks = rv1126_pin_banks, + .nr_banks = ARRAY_SIZE(rv1126_pin_banks), + .nr_pins = 130, + .grf_mux_offset = 0x10004, /* mux offset from GPIO0_D0 */ + .pmu_mux_offset = 0x0, + .iomux_routes = rv1126_mux_route_data, + .niomux_routes = ARRAY_SIZE(rv1126_mux_route_data), + .iomux_recalced = rv1126_mux_recalced_data, + .niomux_recalced = ARRAY_SIZE(rv1126_mux_recalced_data), + .set_mux = rv1126_set_mux, + .set_pull = rv1126_set_pull, + .set_drive = rv1126_set_drive, + .set_schmitt = rv1126_set_schmitt, +}; + +static const struct udevice_id rv1126_pinctrl_ids[] = { + { + .compatible = "rockchip,rv1126-pinctrl", + .data = (ulong)&rv1126_pin_ctrl + }, + { } +}; + +U_BOOT_DRIVER(pinctrl_rv1126) = { + .name = "rockchip_rv1126_pinctrl", + .id = UCLASS_PINCTRL, + .of_match = rv1126_pinctrl_ids, + .priv_auto = sizeof(struct rockchip_pinctrl_priv), + .ops = &rockchip_pinctrl_ops, +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + .bind = dm_scan_fdt_dev, +#endif + .probe = rockchip_pinctrl_probe, +}; diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile index 5a39611349d..83948e2c43e 100644 --- a/drivers/ram/Makefile +++ b/drivers/ram/Makefile @@ -3,7 +3,7 @@ # Copyright (c) 2015 Google, Inc # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # -obj-$(CONFIG_RAM) += ram-uclass.o +obj-$(CONFIG_$(SPL_TPL_)DM) += ram-uclass.o obj-$(CONFIG_MPC83XX_SDRAM) += mpc83xx_sdram.o obj-$(CONFIG_SANDBOX) += sandbox_ram.o obj-$(CONFIG_STM32MP1_DDR) += stm32mp1/ diff --git a/drivers/ram/rockchip/Kconfig b/drivers/ram/rockchip/Kconfig index c29d5e8b38c..67c63ecba04 100644 --- a/drivers/ram/rockchip/Kconfig +++ b/drivers/ram/rockchip/Kconfig @@ -11,9 +11,10 @@ config ROCKCHIP_SDRAM_COMMON help This enable sdram common driver +if RAM_ROCKCHIP + config RAM_ROCKCHIP_DEBUG bool "Rockchip ram drivers debugging" - depends on RAM_ROCKCHIP default y help This enables debugging ram driver API's for the platforms @@ -22,31 +23,28 @@ config RAM_ROCKCHIP_DEBUG This is an option for developers to understand the ram drivers initialization, configurations and etc. -config RAM_PX30_DDR4 - bool "DDR4 support for Rockchip PX30" - depends on RAM_ROCKCHIP && ROCKCHIP_PX30 +config RAM_ROCKCHIP_DDR4 + bool "DDR4 support for Rockchip SoCs" help This enables DDR4 sdram support instead of the default DDR3 support - on Rockchip PC30 SoCs. + on Rockchip SoCs. -config RAM_PX30_LPDDR2 - bool "LPDDR2 support for Rockchip PX30" - depends on RAM_ROCKCHIP && ROCKCHIP_PX30 +config RAM_ROCKCHIP_LPDDR2 + bool "LPDDR2 support for Rockchip SoCs" help This enables LPDDR2 sdram support instead of the default DDR3 support - on Rockchip PC30 SoCs. + on Rockchip SoCs. -config RAM_PX30_LPDDR3 - bool "LPDDR3 support for Rockchip PX30" - depends on RAM_ROCKCHIP && ROCKCHIP_PX30 +config RAM_ROCKCHIP_LPDDR3 + bool "LPDDR3 support for Rockchip SoCs" help This enables LPDDR3 sdram support instead of the default DDR3 support - on Rockchip PC30 SoCs. + on Rockchip SoCs. -config RAM_RK3399_LPDDR4 - bool "LPDDR4 support for Rockchip RK3399" - depends on RAM_ROCKCHIP && ROCKCHIP_RK3399 +config RAM_ROCKCHIP_LPDDR4 + bool "LPDDR4 support for Rockchip SoCs" help This enables LPDDR4 sdram code support for the platforms based - on Rockchip RK3399 SoC. + on Rockchip SoCs. +endif # RAM_ROCKCHIP diff --git a/drivers/ram/rockchip/Makefile b/drivers/ram/rockchip/Makefile index 6d530c29afd..98839ad6a6c 100644 --- a/drivers/ram/rockchip/Makefile +++ b/drivers/ram/rockchip/Makefile @@ -14,4 +14,5 @@ obj-$(CONFIG_ROCKCHIP_RK3308) = sdram_rk3308.o obj-$(CONFIG_ROCKCHIP_RK3328) = sdram_rk3328.o sdram_pctl_px30.o sdram_phy_px30.o obj-$(CONFIG_ROCKCHIP_RK3399) += sdram_rk3399.o obj-$(CONFIG_ROCKCHIP_RK3568) += sdram_rk3568.o +obj-$(CONFIG_ROCKCHIP_RV1126) += sdram_rv1126.o sdram_pctl_px30.o obj-$(CONFIG_ROCKCHIP_SDRAM_COMMON) += sdram_common.o diff --git a/drivers/ram/rockchip/sdram-rv1126-ddr3-detect-1056.inc b/drivers/ram/rockchip/sdram-rv1126-ddr3-detect-1056.inc new file mode 100644 index 00000000000..4cde21565b0 --- /dev/null +++ b/drivers/ram/rockchip/sdram-rv1126-ddr3-detect-1056.inc @@ -0,0 +1,72 @@ +{ + { + { + .rank = 0x1, + .col = 0xC, + .bk = 0x3, + .bw = 0x0, + .dbw = 0x0, + .row_3_4 = 0x0, + .cs0_row = 0x10, + .cs1_row = 0x10, + .cs0_high16bit_row = 0x10, + .cs1_high16bit_row = 0x10, + .ddrconfig = 0 + }, + { + {0x351b1019}, + {0x12030903}, + {0x00000002}, + {0x00001111}, + {0x0000000c}, + {0x00000000}, + 0x000000ff + } + }, + { + .ddr_freq = 1056, /* clock rate(MHz) */ + .dramtype = DDR3, + .num_channels = 1, + .stride = 0, + .odt = 1 + }, + { + { + {0x00000000, 0x43042001}, /* MSTR */ + {0x00000064, 0x008000b9}, /* RFSHTMG */ + {0x000000d0, 0x00020103}, /* INIT0 */ + {0x000000d4, 0x00690000}, /* INIT1 */ + {0x000000d8, 0x00000100}, /* INIT2 */ + {0x000000dc, 0x01240040}, /* INIT3 */ + {0x000000e0, 0x00280000}, /* INIT4 */ + {0x000000e4, 0x000c0000}, /* INIT5 */ + {0x000000f4, 0x000f011f}, /* RANKCTL */ + {0x00000100, 0x0f132414}, /* DRAMTMG0 */ + {0x00000104, 0x000d0419}, /* DRAMTMG1 */ + {0x00000108, 0x0507050b}, /* DRAMTMG2 */ + {0x0000010c, 0x00202008}, /* DRAMTMG3 */ + {0x00000110, 0x07020408}, /* DRAMTMG4 */ + {0x00000114, 0x06060404}, /* DRAMTMG5 */ + {0x00000120, 0x00000907}, /* DRAMTMG8 */ + {0x00000180, 0x00a9002b}, /* ZQCTL0 */ + {0x00000184, 0x00000000}, /* ZQCTL1 */ + {0x00000190, 0x07050003}, /* DFITMG0 */ + {0x00000198, 0x07000101}, /* DFILPCFG0 */ + {0x000001a0, 0xc0400003}, /* DFIUPD0 */ + {0x00000240, 0x06000610}, /* ODTCFG */ + {0x00000244, 0x00000201}, /* ODTMAP */ + {0x00000250, 0x00001f00}, /* SCHED */ + {0x00000490, 0x00000001}, /* PCTRL_0 */ + {0xffffffff, 0xffffffff} + } + }, + { + { + {0x00000004, 0x0000008a}, /* PHYREG01 */ + {0x00000014, 0x0000000e}, /* PHYREG05 */ + {0x00000018, 0x00000000}, /* PHYREG06 */ + {0x0000001c, 0x0000000a}, /* PHYREG07 */ + {0xffffffff, 0xffffffff} + } + } +}, diff --git a/drivers/ram/rockchip/sdram-rv1126-ddr3-detect-328.inc b/drivers/ram/rockchip/sdram-rv1126-ddr3-detect-328.inc new file mode 100644 index 00000000000..eef61ab500f --- /dev/null +++ b/drivers/ram/rockchip/sdram-rv1126-ddr3-detect-328.inc @@ -0,0 +1,72 @@ +{ + { + { + .rank = 0x1, + .col = 0xC, + .bk = 0x3, + .bw = 0x0, + .dbw = 0x0, + .row_3_4 = 0x0, + .cs0_row = 0x10, + .cs1_row = 0x10, + .cs0_high16bit_row = 0x10, + .cs1_high16bit_row = 0x10, + .ddrconfig = 0 + }, + { + {0x270a0509}, + {0x08020401}, + {0x00000002}, + {0x00001111}, + {0x0000000c}, + {0x00000000}, + 0x000000ff + } + }, + { + .ddr_freq = 328, /* clock rate(MHz) */ + .dramtype = DDR3, + .num_channels = 1, + .stride = 0, + .odt = 0 + }, + { + { + {0x00000000, 0x43042001}, /* MSTR */ + {0x00000064, 0x0027003a}, /* RFSHTMG */ + {0x000000d0, 0x00020052}, /* INIT0 */ + {0x000000d4, 0x00220000}, /* INIT1 */ + {0x000000d8, 0x00000100}, /* INIT2 */ + {0x000000dc, 0x03100000}, /* INIT3 */ + {0x000000e0, 0x00000000}, /* INIT4 */ + {0x000000e4, 0x00090000}, /* INIT5 */ + {0x000000f4, 0x000f011f}, /* RANKCTL */ + {0x00000100, 0x07090b06}, /* DRAMTMG0 */ + {0x00000104, 0x00050209}, /* DRAMTMG1 */ + {0x00000108, 0x03030307}, /* DRAMTMG2 */ + {0x0000010c, 0x00202006}, /* DRAMTMG3 */ + {0x00000110, 0x03020203}, /* DRAMTMG4 */ + {0x00000114, 0x03030202}, /* DRAMTMG5 */ + {0x00000120, 0x00000903}, /* DRAMTMG8 */ + {0x00000180, 0x00800020}, /* ZQCTL0 */ + {0x00000184, 0x00000000}, /* ZQCTL1 */ + {0x00000190, 0x07010001}, /* DFITMG0 */ + {0x00000198, 0x07000101}, /* DFILPCFG0 */ + {0x000001a0, 0xc0400003}, /* DFIUPD0 */ + {0x00000240, 0x06000600}, /* ODTCFG */ + {0x00000244, 0x00000201}, /* ODTMAP */ + {0x00000250, 0x00001f00}, /* SCHED */ + {0x00000490, 0x00000001}, /* PCTRL_0 */ + {0xffffffff, 0xffffffff} + } + }, + { + { + {0x00000004, 0x0000008a}, /* PHYREG01 */ + {0x00000014, 0x00000005}, /* PHYREG05 */ + {0x00000018, 0x00000000}, /* PHYREG06 */ + {0x0000001c, 0x00000005}, /* PHYREG07 */ + {0xffffffff, 0xffffffff} + } + } +}, diff --git a/drivers/ram/rockchip/sdram-rv1126-ddr3-detect-396.inc b/drivers/ram/rockchip/sdram-rv1126-ddr3-detect-396.inc new file mode 100644 index 00000000000..39a82718152 --- /dev/null +++ b/drivers/ram/rockchip/sdram-rv1126-ddr3-detect-396.inc @@ -0,0 +1,72 @@ +{ + { + { + .rank = 0x1, + .col = 0xC, + .bk = 0x3, + .bw = 0x0, + .dbw = 0x0, + .row_3_4 = 0x0, + .cs0_row = 0x10, + .cs1_row = 0x10, + .cs0_high16bit_row = 0x10, + .cs1_high16bit_row = 0x10, + .ddrconfig = 0 + }, + { + {0x290b060a}, + {0x0a020401}, + {0x00000002}, + {0x00001111}, + {0x0000000c}, + {0x00000000}, + 0x000000ff + } + }, + { + .ddr_freq = 396, /* clock rate(MHz) */ + .dramtype = DDR3, + .num_channels = 1, + .stride = 0, + .odt = 0 + }, + { + { + {0x00000000, 0x43042001}, /* MSTR */ + {0x00000064, 0x00300046}, /* RFSHTMG */ + {0x000000d0, 0x00020062}, /* INIT0 */ + {0x000000d4, 0x00280000}, /* INIT1 */ + {0x000000d8, 0x00000100}, /* INIT2 */ + {0x000000dc, 0x05200000}, /* INIT3 */ + {0x000000e0, 0x00000000}, /* INIT4 */ + {0x000000e4, 0x00090000}, /* INIT5 */ + {0x000000f4, 0x000f011f}, /* RANKCTL */ + {0x00000100, 0x070a0d07}, /* DRAMTMG0 */ + {0x00000104, 0x0005020b}, /* DRAMTMG1 */ + {0x00000108, 0x03030407}, /* DRAMTMG2 */ + {0x0000010c, 0x00202006}, /* DRAMTMG3 */ + {0x00000110, 0x03020204}, /* DRAMTMG4 */ + {0x00000114, 0x03030202}, /* DRAMTMG5 */ + {0x00000120, 0x00000904}, /* DRAMTMG8 */ + {0x00000180, 0x00800020}, /* ZQCTL0 */ + {0x00000184, 0x00000000}, /* ZQCTL1 */ + {0x00000190, 0x07010001}, /* DFITMG0 */ + {0x00000198, 0x07000101}, /* DFILPCFG0 */ + {0x000001a0, 0xc0400003}, /* DFIUPD0 */ + {0x00000240, 0x06000604}, /* ODTCFG */ + {0x00000244, 0x00000201}, /* ODTMAP */ + {0x00000250, 0x00001f00}, /* SCHED */ + {0x00000490, 0x00000001}, /* PCTRL_0 */ + {0xffffffff, 0xffffffff} + } + }, + { + { + {0x00000004, 0x0000008a}, /* PHYREG01 */ + {0x00000014, 0x00000006}, /* PHYREG05 */ + {0x00000018, 0x00000000}, /* PHYREG06 */ + {0x0000001c, 0x00000005}, /* PHYREG07 */ + {0xffffffff, 0xffffffff} + } + } +}, diff --git a/drivers/ram/rockchip/sdram-rv1126-ddr3-detect-528.inc b/drivers/ram/rockchip/sdram-rv1126-ddr3-detect-528.inc new file mode 100644 index 00000000000..9dbbb1aa9e2 --- /dev/null +++ b/drivers/ram/rockchip/sdram-rv1126-ddr3-detect-528.inc @@ -0,0 +1,72 @@ +{ + { + { + .rank = 0x1, + .col = 0xC, + .bk = 0x3, + .bw = 0x0, + .dbw = 0x0, + .row_3_4 = 0x0, + .cs0_row = 0x10, + .cs1_row = 0x10, + .cs0_high16bit_row = 0x10, + .cs1_high16bit_row = 0x10, + .ddrconfig = 0 + }, + { + {0x2c0f080e}, + {0x0d030502}, + {0x00000002}, + {0x00001111}, + {0x0000000c}, + {0x00000000}, + 0x000000ff + } + }, + { + .ddr_freq = 528, /* clock rate(MHz) */ + .dramtype = DDR3, + .num_channels = 1, + .stride = 0, + .odt = 0 + }, + { + { + {0x00000000, 0x43042001}, /* MSTR */ + {0x00000064, 0x0040005d}, /* RFSHTMG */ + {0x000000d0, 0x00020082}, /* INIT0 */ + {0x000000d4, 0x00350000}, /* INIT1 */ + {0x000000d8, 0x00000100}, /* INIT2 */ + {0x000000dc, 0x09400000}, /* INIT3 */ + {0x000000e0, 0x00080000}, /* INIT4 */ + {0x000000e4, 0x00090000}, /* INIT5 */ + {0x000000f4, 0x000f011f}, /* RANKCTL */ + {0x00000100, 0x090e120a}, /* DRAMTMG0 */ + {0x00000104, 0x0007020e}, /* DRAMTMG1 */ + {0x00000108, 0x03040407}, /* DRAMTMG2 */ + {0x0000010c, 0x00202006}, /* DRAMTMG3 */ + {0x00000110, 0x04020305}, /* DRAMTMG4 */ + {0x00000114, 0x03030302}, /* DRAMTMG5 */ + {0x00000120, 0x00000904}, /* DRAMTMG8 */ + {0x00000180, 0x00800020}, /* ZQCTL0 */ + {0x00000184, 0x00000000}, /* ZQCTL1 */ + {0x00000190, 0x07020001}, /* DFITMG0 */ + {0x00000198, 0x07000101}, /* DFILPCFG0 */ + {0x000001a0, 0xc0400003}, /* DFIUPD0 */ + {0x00000240, 0x06000608}, /* ODTCFG */ + {0x00000244, 0x00000201}, /* ODTMAP */ + {0x00000250, 0x00001f00}, /* SCHED */ + {0x00000490, 0x00000001}, /* PCTRL_0 */ + {0xffffffff, 0xffffffff} + } + }, + { + { + {0x00000004, 0x0000008a}, /* PHYREG01 */ + {0x00000014, 0x00000008}, /* PHYREG05 */ + {0x00000018, 0x00000000}, /* PHYREG06 */ + {0x0000001c, 0x00000006}, /* PHYREG07 */ + {0xffffffff, 0xffffffff} + } + } +}, diff --git a/drivers/ram/rockchip/sdram-rv1126-ddr3-detect-664.inc b/drivers/ram/rockchip/sdram-rv1126-ddr3-detect-664.inc new file mode 100644 index 00000000000..2b571327949 --- /dev/null +++ b/drivers/ram/rockchip/sdram-rv1126-ddr3-detect-664.inc @@ -0,0 +1,72 @@ +{ + { + { + .rank = 0x1, + .col = 0xC, + .bk = 0x3, + .bw = 0x0, + .dbw = 0x0, + .row_3_4 = 0x0, + .cs0_row = 0x10, + .cs1_row = 0x10, + .cs0_high16bit_row = 0x10, + .cs1_high16bit_row = 0x10, + .ddrconfig = 0 + }, + { + {0x2f120a11}, + {0x0f020602}, + {0x00000002}, + {0x00001111}, + {0x0000000c}, + {0x00000000}, + 0x000000ff + } + }, + { + .ddr_freq = 664, /* clock rate(MHz) */ + .dramtype = DDR3, + .num_channels = 1, + .stride = 0, + .odt = 1 + }, + { + { + {0x00000000, 0x43042001}, /* MSTR */ + {0x00000064, 0x00500075}, /* RFSHTMG */ + {0x000000d0, 0x000200a4}, /* INIT0 */ + {0x000000d4, 0x00420000}, /* INIT1 */ + {0x000000d8, 0x00000100}, /* INIT2 */ + {0x000000dc, 0x0b600040}, /* INIT3 */ + {0x000000e0, 0x00100000}, /* INIT4 */ + {0x000000e4, 0x00090000}, /* INIT5 */ + {0x000000f4, 0x000f011f}, /* RANKCTL */ + {0x00000100, 0x0a0f160c}, /* DRAMTMG0 */ + {0x00000104, 0x00080211}, /* DRAMTMG1 */ + {0x00000108, 0x04050508}, /* DRAMTMG2 */ + {0x0000010c, 0x00202006}, /* DRAMTMG3 */ + {0x00000110, 0x05020306}, /* DRAMTMG4 */ + {0x00000114, 0x04040302}, /* DRAMTMG5 */ + {0x00000120, 0x00000905}, /* DRAMTMG8 */ + {0x00000180, 0x00800020}, /* ZQCTL0 */ + {0x00000184, 0x00000000}, /* ZQCTL1 */ + {0x00000190, 0x07030002}, /* DFITMG0 */ + {0x00000198, 0x07000101}, /* DFILPCFG0 */ + {0x000001a0, 0xc0400003}, /* DFIUPD0 */ + {0x00000240, 0x0600060c}, /* ODTCFG */ + {0x00000244, 0x00000201}, /* ODTMAP */ + {0x00000250, 0x00001f00}, /* SCHED */ + {0x00000490, 0x00000001}, /* PCTRL_0 */ + {0xffffffff, 0xffffffff} + } + }, + { + { + {0x00000004, 0x0000008a}, /* PHYREG01 */ + {0x00000014, 0x0000000a}, /* PHYREG05 */ + {0x00000018, 0x00000000}, /* PHYREG06 */ + {0x0000001c, 0x00000007}, /* PHYREG07 */ + {0xffffffff, 0xffffffff} + } + } +}, diff --git a/drivers/ram/rockchip/sdram-rv1126-ddr3-detect-784.inc b/drivers/ram/rockchip/sdram-rv1126-ddr3-detect-784.inc new file mode 100644 index 00000000000..8ad22727fcb --- /dev/null +++ b/drivers/ram/rockchip/sdram-rv1126-ddr3-detect-784.inc @@ -0,0 +1,72 @@ +{ + { + { + .rank = 0x1, + .col = 0xC, + .bk = 0x3, + .bw = 0x0, + .dbw = 0x0, + .row_3_4 = 0x0, + .cs0_row = 0x10, + .cs1_row = 0x10, + .cs0_high16bit_row = 0x10, + .cs1_high16bit_row = 0x10, + .ddrconfig = 0 + }, + { + {0x30150c13}, + {0x10030702}, + {0x00000002}, + {0x00001111}, + {0x0000000c}, + {0x00000000}, + 0x000000ff + } + }, + { + .ddr_freq = 784, /* clock rate(MHz) */ + .dramtype = DDR3, + .num_channels = 1, + .stride = 0, + .odt = 1 + }, + { + { + {0x00000000, 0x43042001}, /* MSTR */ + {0x00000064, 0x005f008a}, /* RFSHTMG */ + {0x000000d0, 0x000200c1}, /* INIT0 */ + {0x000000d4, 0x004e0000}, /* INIT1 */ + {0x000000d8, 0x00000100}, /* INIT2 */ + {0x000000dc, 0x0d700040}, /* INIT3 */ + {0x000000e0, 0x00180000}, /* INIT4 */ + {0x000000e4, 0x00090000}, /* INIT5 */ + {0x000000f4, 0x000f011f}, /* RANKCTL */ + {0x00000100, 0x0c101a0f}, /* DRAMTMG0 */ + {0x00000104, 0x000a0314}, /* DRAMTMG1 */ + {0x00000108, 0x04060509}, /* DRAMTMG2 */ + {0x0000010c, 0x00202006}, /* DRAMTMG3 */ + {0x00000110, 0x06020306}, /* DRAMTMG4 */ + {0x00000114, 0x04040303}, /* DRAMTMG5 */ + {0x00000120, 0x00000906}, /* DRAMTMG8 */ + {0x00000180, 0x00800020}, /* ZQCTL0 */ + {0x00000184, 0x00000000}, /* ZQCTL1 */ + {0x00000190, 0x07040002}, /* DFITMG0 */ + {0x00000198, 0x07000101}, /* DFILPCFG0 */ + {0x000001a0, 0xc0400003}, /* DFIUPD0 */ + {0x00000240, 0x0600060c}, /* ODTCFG */ + {0x00000244, 0x00000201}, /* ODTMAP */ + {0x00000250, 0x00001f00}, /* SCHED */ + {0x00000490, 0x00000001}, /* PCTRL_0 */ + {0xffffffff, 0xffffffff} + } + }, + { + { + {0x00000004, 0x0000008a}, /* PHYREG01 */ + {0x00000014, 0x0000000b}, /* PHYREG05 */ + {0x00000018, 0x00000000}, /* PHYREG06 */ + {0x0000001c, 0x00000008}, /* PHYREG07 */ + {0xffffffff, 0xffffffff} + } + } +}, diff --git a/drivers/ram/rockchip/sdram-rv1126-ddr3-detect-924.inc b/drivers/ram/rockchip/sdram-rv1126-ddr3-detect-924.inc new file mode 100644 index 00000000000..4cc36b05d25 --- /dev/null +++ b/drivers/ram/rockchip/sdram-rv1126-ddr3-detect-924.inc @@ -0,0 +1,72 @@ +{ + { + { + .rank = 0x1, + .col = 0xC, + .bk = 0x3, + .bw = 0x0, + .dbw = 0x0, + .row_3_4 = 0x0, + .cs0_row = 0x10, + .cs1_row = 0x10, + .cs0_high16bit_row = 0x10, + .cs1_high16bit_row = 0x10, + .ddrconfig = 0 + }, + { + {0x33180e16}, + {0x10030803}, + {0x00000002}, + {0x00001111}, + {0x0000000c}, + {0x00000000}, + 0x000000ff + } + }, + { + .ddr_freq = 924, /* clock rate(MHz) */ + .dramtype = DDR3, + .num_channels = 1, + .stride = 0, + .odt = 1 + }, + { + { + {0x00000000, 0x43042001}, /* MSTR */ + {0x00000064, 0x007000a2}, /* RFSHTMG */ + {0x000000d0, 0x000200e3}, /* INIT0 */ + {0x000000d4, 0x005c0000}, /* INIT1 */ + {0x000000d8, 0x00000100}, /* INIT2 */ + {0x000000dc, 0x0f140040}, /* INIT3 */ + {0x000000e0, 0x00200000}, /* INIT4 */ + {0x000000e4, 0x000b0000}, /* INIT5 */ + {0x000000f4, 0x000f011f}, /* RANKCTL */ + {0x00000100, 0x0d111f11}, /* DRAMTMG0 */ + {0x00000104, 0x000c0317}, /* DRAMTMG1 */ + {0x00000108, 0x0507050a}, /* DRAMTMG2 */ + {0x0000010c, 0x00202007}, /* DRAMTMG3 */ + {0x00000110, 0x07020307}, /* DRAMTMG4 */ + {0x00000114, 0x05050403}, /* DRAMTMG5 */ + {0x00000120, 0x00000907}, /* DRAMTMG8 */ + {0x00000180, 0x00940025}, /* ZQCTL0 */ + {0x00000184, 0x00000000}, /* ZQCTL1 */ + {0x00000190, 0x07050003}, /* DFITMG0 */ + {0x00000198, 0x07000101}, /* DFILPCFG0 */ + {0x000001a0, 0xc0400003}, /* DFIUPD0 */ + {0x00000240, 0x06000610}, /* ODTCFG */ + {0x00000244, 0x00000201}, /* ODTMAP */ + {0x00000250, 0x00001f00}, /* SCHED */ + {0x00000490, 0x00000001}, /* PCTRL_0 */ + {0xffffffff, 0xffffffff} + } + }, + { + { + {0x00000004, 0x0000008a}, /* PHYREG01 */ + {0x00000014, 0x0000000d}, /* PHYREG05 */ + {0x00000018, 0x00000000}, /* PHYREG06 */ + {0x0000001c, 0x00000009}, /* PHYREG07 */ + {0xffffffff, 0xffffffff} + } + } +}, diff --git a/drivers/ram/rockchip/sdram-rv1126-loader_params.inc b/drivers/ram/rockchip/sdram-rv1126-loader_params.inc new file mode 100644 index 00000000000..a4c9e7f3287 --- /dev/null +++ b/drivers/ram/rockchip/sdram-rv1126-loader_params.inc @@ -0,0 +1,197 @@ +0x12345678, +2,/* version */ +(0 << 0) | (1 << 8) | (9 << 16) | (8 << 24),/* cpu_gen,global index */ +(0 << 0) | (9 << 8) | (17 << 16) | (9 << 24),/* d2,d3 index */ +(26 << 0) | (9 << 8) | (0 << 16) | (0 << 24),/* d4,d5 index */ +(0 << 0) | (9 << 8) | (35 << 16) | (9 << 24),/* lp2,lp3 index */ +(44 << 0) | (13 << 8) | (0 << 16) | (0 << 24),/* lp4,lp5 index */ +(0 << 0) | (0 << 8) | (57 << 16) | (8 << 24),/* skew index, dq_map index */ +(65 << 0) | (13 << 8) | (0 << 16) | (0 << 24), /*lp4x index*/ +/* global info */ +0, +(93 << 16) | 13,/* sr_idle << 16 | pd_idle */ +0,/* channel info */ +1,/* 2t info */ +0, 0, 0, 0,/* reserved */ + +/* ddr3 */ +(924 << DDR_FREQ_F0_SHIFT) | (328 << DDR_FREQ_F1_SHIFT), +(528 << DDR_FREQ_F2_SHIFT) | (784 << DDR_FREQ_F3_SHIFT), +(0 << DDR_FREQ_F4_SHIFT) | (0 << DDR_FREQ_F5_SHIFT), +/* drv when odt on */ +(30 << PHY_DQ_DRV_SHIFT) | (41 << PHY_CA_DRV_SHIFT) | + (38 << PHY_CLK_DRV_SHIFT) | (34 << DRAM_DQ_DRV_SHIFT), +/* drv when odt off */ +(30 << PHY_DQ_DRV_SHIFT) | (30 << PHY_CA_DRV_SHIFT) | + (38 << PHY_CLK_DRV_SHIFT) | (34 << DRAM_DQ_DRV_SHIFT), +/* odt info */ +(120 << DRAM_ODT_SHIFT) | (141 << PHY_ODT_SHIFT) | + (1 << PHY_ODT_PUUP_EN_SHIFT) | + (0 << PHY_ODT_PUDN_EN_SHIFT), +/* odt enable freq */ +(333 << DRAM_ODT_EN_FREQ_SHIFT) | (333 << PHY_ODT_EN_FREQ_SHIFT), +/* slew rate when odt enable */ +(0x1f << PHY_DQ_SR_SHIFT) | (0x1f << PHY_CA_SR_SHIFT) | + (0x1f << PHY_CLK_SR_SHIFT), +/* slew ratee when odt disable */ +(0x1f << PHY_DQ_SR_SHIFT) | (0x1f << PHY_CA_SR_SHIFT) | + (0x1f << PHY_CLK_SR_SHIFT), + +/* ddr4 */ +(924 << DDR_FREQ_F0_SHIFT) | (328 << DDR_FREQ_F1_SHIFT), +(528 << DDR_FREQ_F2_SHIFT) | (784 << DDR_FREQ_F3_SHIFT), +(0 << DDR_FREQ_F4_SHIFT) | (0 << DDR_FREQ_F5_SHIFT), +/* drv when odt on */ +(37 << PHY_DQ_DRV_SHIFT) | (44 << PHY_CA_DRV_SHIFT) | + (37 << PHY_CLK_DRV_SHIFT) | (34 << DRAM_DQ_DRV_SHIFT), +/* drv when odt off */ +(37 << PHY_DQ_DRV_SHIFT) | (44 << PHY_CA_DRV_SHIFT) | + (37 << PHY_CLK_DRV_SHIFT) | (34 << DRAM_DQ_DRV_SHIFT), +/* odt info */ +(120 << DRAM_ODT_SHIFT) | (148 << PHY_ODT_SHIFT) | + (1 << PHY_ODT_PUUP_EN_SHIFT) | (1 << PHY_ODT_PUDN_EN_SHIFT), +/* odt enable freq */ +(625 << DRAM_ODT_EN_FREQ_SHIFT) | (625 << PHY_ODT_EN_FREQ_SHIFT), +/* slew rate when odt enable */ +(0xe << PHY_DQ_SR_SHIFT) | (0x3 << PHY_CA_SR_SHIFT) | + (0x3 << PHY_CLK_SR_SHIFT), +/* slew ratee when odt disable */ +(0xe << PHY_DQ_SR_SHIFT) | (0x3 << PHY_CA_SR_SHIFT) | + (0x3 << PHY_CLK_SR_SHIFT), + +/* lpddr3 */ +(924 << DDR_FREQ_F0_SHIFT) | (328 << DDR_FREQ_F1_SHIFT), +(528 << DDR_FREQ_F2_SHIFT) | (784 << DDR_FREQ_F3_SHIFT), +(0 << DDR_FREQ_F4_SHIFT) | (0 << DDR_FREQ_F5_SHIFT), +/* drv when odt on */ +(28 << PHY_DQ_DRV_SHIFT) | (37 << PHY_CA_DRV_SHIFT) | + (34 << PHY_CLK_DRV_SHIFT) | (34 << DRAM_DQ_DRV_SHIFT), +/* drv when odt off */ +(28 << PHY_DQ_DRV_SHIFT) | (37 << PHY_CA_DRV_SHIFT) | + (34 << PHY_CLK_DRV_SHIFT) | (34 << DRAM_DQ_DRV_SHIFT), +/* odt info */ +(120 << DRAM_ODT_SHIFT) | (148 << PHY_ODT_SHIFT) | + (1 << PHY_ODT_PUUP_EN_SHIFT) | (1 << PHY_ODT_PUDN_EN_SHIFT), +/* odt enable freq */ +(333 << DRAM_ODT_EN_FREQ_SHIFT) | (333 << PHY_ODT_EN_FREQ_SHIFT), + +/* slew rate when odt enable */ +(0xe << PHY_DQ_SR_SHIFT) | (0x0 << PHY_CA_SR_SHIFT) | + (0x0 << PHY_CLK_SR_SHIFT), +/* slew ratee when odt disable */ +(0xe << PHY_DQ_SR_SHIFT) | (0x0 << PHY_CA_SR_SHIFT) | + (0x0 << PHY_CLK_SR_SHIFT), + +/* lpddr4 */ +(924 << DDR_FREQ_F0_SHIFT) | (328 << DDR_FREQ_F1_SHIFT), +(528 << DDR_FREQ_F2_SHIFT) | (784 << DDR_FREQ_F3_SHIFT), +(0 << DDR_FREQ_F4_SHIFT) | (0 << DDR_FREQ_F5_SHIFT), + +/* drv when odt on */ +(38 << PHY_DQ_DRV_SHIFT) | (46 << PHY_CA_DRV_SHIFT) | + (38 << PHY_CLK_DRV_SHIFT) | (40 << DRAM_DQ_DRV_SHIFT), +/* drv when odt off */ +(38 << PHY_DQ_DRV_SHIFT) | (46 << PHY_CA_DRV_SHIFT) | + (38 << PHY_CLK_DRV_SHIFT) | (40 << DRAM_DQ_DRV_SHIFT), +/* odt info and PU-cal info */ +(240 << DRAM_ODT_SHIFT) | (80 << PHY_ODT_SHIFT) | + (0 << LP4_CA_ODT_SHIFT) | + (LPDDR4_VDDQ_2_5 << LP4_DRV_PU_CAL_ODTEN_SHIFT) | + (LPDDR4_VDDQ_2_5 << LP4_DRV_PU_CAL_ODTOFF_SHIFT) | + (0 << PHY_LP4_DRV_PULLDOWN_EN_ODTEN_SHIFT) | + (0 << PHY_LP4_DRV_PULLDOWN_EN_ODTOFF_SHIFT), +/* odt enable freq */ +(333 << PHY_LP4_ODT_EN_FREQ_SHIFT) | (333 << LP4_DQ_ODT_EN_FREQ_SHIFT), +/* slew rate when odt enable */ +(0xf << PHY_DQ_SR_SHIFT) | (0xf << PHY_CA_SR_SHIFT) | + (0xf << PHY_CLK_SR_SHIFT), +/* slew ratee when odt disable */ +(0xf << PHY_DQ_SR_SHIFT) | (0xf << PHY_CA_SR_SHIFT) | + (0xf << PHY_CLK_SR_SHIFT), +/* ca odt en freq */ +(333 << LP4_CA_ODT_EN_FREQ_SHIFT), +/* cs drv info and ca odt info */ +(0 << PHY_LP4_CS_DRV_ODTEN_SHIFT) | + (0 << PHY_LP4_CS_DRV_ODTOFF_SHIFT) | + (0 << LP4_ODTE_CK_SHIFT) | (0 << LP4_ODTE_CS_EN_SHIFT) | + (0 << LP4_ODTD_CA_EN_SHIFT), +/* vref info when odt enable */ +(200 << PHY_LP4_DQ_VREF_SHIFT) | (420 << LP4_DQ_VREF_SHIFT) | + (420 << LP4_CA_VREF_SHIFT), +/* vref info when odt disable */ +(420 << PHY_LP4_DQ_VREF_SHIFT) | (420 << LP4_DQ_VREF_SHIFT) | + (420 << LP4_CA_VREF_SHIFT), +/* ddr4 map << 0 | ddr3 map << 24 */ +((0x2 << 6) | (0x1 << 4) | (0x3 << 2) | (0x0 << 0)) | + (0 << 8) | (0 << 16) | + (((0x2 << 6) | (0x1 << 4) | (0x3 << 2) | (0x0 << 0)) << 24), +/* lp3 map << 16 | lp4 map << 24 */ +/* lp4 should equal to 0xc9 */ +(((0x3 << 6) | (0x2 << 4) | (0x1 << 2) | (0x0 << 0)) << 16) | + (((0x3 << 6) | (0x0 << 4) | (0x2 << 2) | (0x1 << 0)) << 24), +/* lp3 dq0-7 map */ +(2 << 0) | (6 << 4) | (4 << 8) | (0 << 12) | (3 << 16) | (7 << 20) | + ( 5 << 24) | (1 << 28), +/* lp2 dq0-7 map */ +0, +/* ddr4 dq map */ +/* cs0 dq0-15 */ + ((2 << 0 | 0 << 2 | 3 << 4 | 1 << 6) << 0) | + ((0 << 0 | 2 << 2 | 3 << 4 | 1 << 6) << 8) | + ((2 << 0 | 2 << 2 | 1 << 4 | 3 << 6) << 16) | + ((1 << 0 | 3 << 2 | 0 << 4 | 0 << 6) << 24), +/* cs0 dq16-31 */ + ((2 << 0 | 0 << 2 | 2 << 4 | 0 << 6) << 0) | + ((1 << 0 | 3 << 2 | 3 << 4 | 1 << 6) << 8) | + ((0 << 0 | 0 << 2 | 1 << 4 | 3 << 6) << 16) | + ((1 << 0 | 3 << 2 | 2 << 4 | 2 << 6) << 24), +/* cs1 dq0-15 */ + ((2 << 0 | 0 << 2 | 3 << 4 | 1 << 6) << 0) | + ((0 << 0 | 2 << 2 | 3 << 4 | 1 << 6) << 8) | + ((2 << 0 | 2 << 2 | 1 << 4 | 3 << 6) << 16) | + ((1 << 0 | 3 << 2 | 0 << 4 | 0 << 6) << 24), +/* cs1 dq16-31 */ + ((2 << 0 | 0 << 2 | 2 << 4 | 0 << 6) << 0) | + ((1 << 0 | 3 << 2 | 3 << 4 | 1 << 6) << 8) | + ((0 << 0 | 0 << 2 | 1 << 4 | 3 << 6) << 16) | + ((1 << 0 | 3 << 2 | 2 << 4 | 2 << 6) << 24), + +/* lpddr4x */ +(1056 << DDR_FREQ_F0_SHIFT) | (328 << DDR_FREQ_F1_SHIFT), +(528 << DDR_FREQ_F2_SHIFT) | (784 << DDR_FREQ_F3_SHIFT), +(0 << DDR_FREQ_F4_SHIFT) | (0 << DDR_FREQ_F5_SHIFT), + +/* drv when odt on */ +(38 << PHY_DQ_DRV_SHIFT) | (38 << PHY_CA_DRV_SHIFT) | + (38 << PHY_CLK_DRV_SHIFT) | (40 << DRAM_DQ_DRV_SHIFT), +/* drv when odt off */ +(38 << PHY_DQ_DRV_SHIFT) | (38 << PHY_CA_DRV_SHIFT) | + (38 << PHY_CLK_DRV_SHIFT) | (40 << DRAM_DQ_DRV_SHIFT), +/* odt info and PU-cal info */ +(48 << DRAM_ODT_SHIFT) | (60 << PHY_ODT_SHIFT) | + (120 << LP4_CA_ODT_SHIFT) | + (LPDDR4X_VDDQ_0_6 << LP4_DRV_PU_CAL_ODTEN_SHIFT) | + (LPDDR4X_VDDQ_0_6 << LP4_DRV_PU_CAL_ODTOFF_SHIFT) | + (0 << PHY_LP4_DRV_PULLDOWN_EN_ODTEN_SHIFT) | + (0 << PHY_LP4_DRV_PULLDOWN_EN_ODTOFF_SHIFT), +/* odt enable freq */ +(0 << PHY_LP4_ODT_EN_FREQ_SHIFT) | (0 << LP4_DQ_ODT_EN_FREQ_SHIFT), +/* slew rate when odt enable */ +(0xf << PHY_DQ_SR_SHIFT) | (0xf << PHY_CA_SR_SHIFT) | + (0xf << PHY_CLK_SR_SHIFT), +/* slew ratee when odt disable */ +(0xf << PHY_DQ_SR_SHIFT) | (0xf << PHY_CA_SR_SHIFT) | + (0xf << PHY_CLK_SR_SHIFT), +/* ca odt en freq */ +(333 << LP4_CA_ODT_EN_FREQ_SHIFT), +/* cs drv info and ca odt info */ +(0 << PHY_LP4_CS_DRV_ODTEN_SHIFT) | + (0 << PHY_LP4_CS_DRV_ODTOFF_SHIFT) | + (0 << LP4_ODTE_CK_SHIFT) | (0 << LP4_ODTE_CS_EN_SHIFT) | + (0 << LP4_ODTD_CA_EN_SHIFT), +/* vref info when odt enable, phy vddq=1.1V, lp4x vddq=0.6V */ +(153 << PHY_LP4_DQ_VREF_SHIFT) | (515 << LP4_DQ_VREF_SHIFT) | + (629 << LP4_CA_VREF_SHIFT), +/* vref info when odt disable */ +(153 << PHY_LP4_DQ_VREF_SHIFT) | (629 << LP4_DQ_VREF_SHIFT) | + (629 << LP4_CA_VREF_SHIFT), diff --git a/drivers/ram/rockchip/sdram-rv1126-lpddr4-detect-1056.inc b/drivers/ram/rockchip/sdram-rv1126-lpddr4-detect-1056.inc new file mode 100644 index 00000000000..705cbfb5cb0 --- /dev/null +++ b/drivers/ram/rockchip/sdram-rv1126-lpddr4-detect-1056.inc @@ -0,0 +1,78 @@ +{ + { + { + .rank = 0x1, + .col = 0xB, + .bk = 0x3, + .bw = 0x1, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0x11, + .cs1_row = 0x11, + .cs0_high16bit_row = 0x0, + .cs1_high16bit_row = 0x0, + .ddrconfig = 0 + }, + { + {0x41241522}, + {0x15050b07}, + {0x00000602}, + {0x00001111}, + {0x00000054}, + {0x00000000}, + 0x000000ff + } + }, + { + .ddr_freq = 1056, /* clock rate(MHz) */ + .dramtype = LPDDR4, + .num_channels = 1, + .stride = 0, + .odt = 1 + }, + { + { + {0x00000000, 0x81081020}, /* MSTR */ + {0x00000064, 0x00400094}, /* RFSHTMG */ + {0x000000d0, 0x00030409}, /* INIT0 */ + {0x000000d4, 0x00690000}, /* INIT1 */ + {0x000000d8, 0x00000206}, /* INIT2 */ + {0x000000dc, 0x0034001b}, /* INIT3 */ + {0x000000e0, 0x00310000}, /* INIT4 */ + {0x000000e8, 0x00110000}, /* INIT6 */ + {0x000000ec, 0x00000000}, /* INIT7 */ + {0x000000f4, 0x000f033f}, /* RANKCTL */ + {0x00000100, 0x14161217}, /* DRAMTMG0 */ + {0x00000104, 0x00040422}, /* DRAMTMG1 */ + {0x00000108, 0x050a0e0f}, /* DRAMTMG2 */ + {0x0000010c, 0x00808000}, /* DRAMTMG3 */ + {0x00000110, 0x0a04060c}, /* DRAMTMG4 */ + {0x00000114, 0x02040808}, /* DRAMTMG5 */ + {0x00000118, 0x01010005}, /* DRAMTMG6 */ + {0x0000011c, 0x00000401}, /* DRAMTMG7 */ + {0x00000120, 0x00000606}, /* DRAMTMG8 */ + {0x00000130, 0x00020000}, /* DRAMTMG12 */ + {0x00000134, 0x0a100002}, /* DRAMTMG13 */ + {0x00000138, 0x00000098}, /* DRAMTMG14 */ + {0x00000180, 0x02100010}, /* ZQCTL0 */ + {0x00000184, 0x01b00000}, /* ZQCTL1 */ + {0x00000190, 0x07070001}, /* DFITMG0 */ + {0x00000198, 0x07000101}, /* DFILPCFG0 */ + {0x000001a0, 0xc0400003}, /* DFIUPD0 */ + {0x00000240, 0x0b050d3c}, /* ODTCFG */ + {0x00000244, 0x00000101}, /* ODTMAP */ + {0x00000250, 0x00001f00}, /* SCHED */ + {0x00000490, 0x00000001}, /* PCTRL_0 */ + {0xffffffff, 0xffffffff} + } + }, + { + { + {0x00000004, 0x0000008d}, /* PHYREG01 */ + {0x00000014, 0x00000014}, /* PHYREG05 */ + {0x00000018, 0x00000000}, /* PHYREG06 */ + {0x0000001c, 0x0000000a}, /* PHYREG07 */ + {0xffffffff, 0xffffffff} + } + } +}, diff --git a/drivers/ram/rockchip/sdram-rv1126-lpddr4-detect-328.inc b/drivers/ram/rockchip/sdram-rv1126-lpddr4-detect-328.inc new file mode 100644 index 00000000000..3864b0097fe --- /dev/null +++ b/drivers/ram/rockchip/sdram-rv1126-lpddr4-detect-328.inc @@ -0,0 +1,78 @@ +{ + { + { + .rank = 0x1, + .col = 0xB, + .bk = 0x3, + .bw = 0x1, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0x11, + .cs1_row = 0x11, + .cs0_high16bit_row = 0x0, + .cs1_high16bit_row = 0x0, + .ddrconfig = 0 + }, + { + {0x2f0d060a}, + {0x07020804}, + {0x00000602}, + {0x00001111}, + {0x00000054}, + {0x00000000}, + 0x000000ff + } + }, + { + .ddr_freq = 328, /* clock rate(MHz) */ + .dramtype = LPDDR4, + .num_channels = 1, + .stride = 0, + .odt = 0 + }, + { + { + {0x00000000, 0x81081020}, /* MSTR */ + {0x00000064, 0x0014002e}, /* RFSHTMG */ + {0x000000d0, 0x00020142}, /* INIT0 */ + {0x000000d4, 0x00220000}, /* INIT1 */ + {0x000000d8, 0x00000202}, /* INIT2 */ + {0x000000dc, 0x00240012}, /* INIT3 */ + {0x000000e0, 0x00310000}, /* INIT4 */ + {0x000000e8, 0x00100000}, /* INIT6 */ + {0x000000ec, 0x00000000}, /* INIT7 */ + {0x000000f4, 0x000f033f}, /* RANKCTL */ + {0x00000100, 0x0c070507}, /* DRAMTMG0 */ + {0x00000104, 0x0003040b}, /* DRAMTMG1 */ + {0x00000108, 0x04070c0d}, /* DRAMTMG2 */ + {0x0000010c, 0x00505000}, /* DRAMTMG3 */ + {0x00000110, 0x03040204}, /* DRAMTMG4 */ + {0x00000114, 0x02030303}, /* DRAMTMG5 */ + {0x00000118, 0x01010004}, /* DRAMTMG6 */ + {0x0000011c, 0x00000301}, /* DRAMTMG7 */ + {0x00000120, 0x00000303}, /* DRAMTMG8 */ + {0x00000130, 0x00020000}, /* DRAMTMG12 */ + {0x00000134, 0x00100002}, /* DRAMTMG13 */ + {0x00000138, 0x00000030}, /* DRAMTMG14 */ + {0x00000180, 0x00a40005}, /* ZQCTL0 */ + {0x00000184, 0x00900000}, /* ZQCTL1 */ + {0x00000190, 0x07040000}, /* DFITMG0 */ + {0x00000198, 0x07000101}, /* DFILPCFG0 */ + {0x000001a0, 0xc0400003}, /* DFIUPD0 */ + {0x00000240, 0x0905092c}, /* ODTCFG */ + {0x00000244, 0x00000101}, /* ODTMAP */ + {0x00000250, 0x00001f00}, /* SCHED */ + {0x00000490, 0x00000001}, /* PCTRL_0 */ + {0xffffffff, 0xffffffff} + } + }, + { + { + {0x00000004, 0x0000008d}, /* PHYREG01 */ + {0x00000014, 0x0000000e}, /* PHYREG05 */ + {0x00000018, 0x00000000}, /* PHYREG06 */ + {0x0000001c, 0x00000008}, /* PHYREG07 */ + {0xffffffff, 0xffffffff} + } + } +}, diff --git a/drivers/ram/rockchip/sdram-rv1126-lpddr4-detect-396.inc b/drivers/ram/rockchip/sdram-rv1126-lpddr4-detect-396.inc new file mode 100644 index 00000000000..9018c3a7635 --- /dev/null +++ b/drivers/ram/rockchip/sdram-rv1126-lpddr4-detect-396.inc @@ -0,0 +1,78 @@ +{ + { + { + .rank = 0x1, + .col = 0xB, + .bk = 0x3, + .bw = 0x1, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0x11, + .cs1_row = 0x11, + .cs0_high16bit_row = 0x0, + .cs1_high16bit_row = 0x0, + .ddrconfig = 0 + }, + { + {0x3110080d}, + {0x08020804}, + {0x00000602}, + {0x00001111}, + {0x00000054}, + {0x00000000}, + 0x000000ff + } + }, + { + .ddr_freq = 396, /* clock rate(MHz) */ + .dramtype = LPDDR4, + .num_channels = 1, + .stride = 0, + .odt = 0 + }, + { + { + {0x00000000, 0x81081020}, /* MSTR */ + {0x00000064, 0x00180038}, /* RFSHTMG */ + {0x000000d0, 0x00020184}, /* INIT0 */ + {0x000000d4, 0x00280000}, /* INIT1 */ + {0x000000d8, 0x00000202}, /* INIT2 */ + {0x000000dc, 0x00240012}, /* INIT3 */ + {0x000000e0, 0x00310000}, /* INIT4 */ + {0x000000e8, 0x00100000}, /* INIT6 */ + {0x000000ec, 0x00000000}, /* INIT7 */ + {0x000000f4, 0x000f033f}, /* RANKCTL */ + {0x00000100, 0x0d080609}, /* DRAMTMG0 */ + {0x00000104, 0x0003040d}, /* DRAMTMG1 */ + {0x00000108, 0x04070c0d}, /* DRAMTMG2 */ + {0x0000010c, 0x00505000}, /* DRAMTMG3 */ + {0x00000110, 0x04040205}, /* DRAMTMG4 */ + {0x00000114, 0x02030303}, /* DRAMTMG5 */ + {0x00000118, 0x01010004}, /* DRAMTMG6 */ + {0x0000011c, 0x00000301}, /* DRAMTMG7 */ + {0x00000120, 0x00000303}, /* DRAMTMG8 */ + {0x00000130, 0x00020000}, /* DRAMTMG12 */ + {0x00000134, 0x00100002}, /* DRAMTMG13 */ + {0x00000138, 0x00000039}, /* DRAMTMG14 */ + {0x00000180, 0x00c60006}, /* ZQCTL0 */ + {0x00000184, 0x00a00000}, /* ZQCTL1 */ + {0x00000190, 0x07040000}, /* DFITMG0 */ + {0x00000198, 0x07000101}, /* DFILPCFG0 */ + {0x000001a0, 0xc0400003}, /* DFIUPD0 */ + {0x00000240, 0x0905092c}, /* ODTCFG */ + {0x00000244, 0x00000101}, /* ODTMAP */ + {0x00000250, 0x00001f00}, /* SCHED */ + {0x00000490, 0x00000001}, /* PCTRL_0 */ + {0xffffffff, 0xffffffff} + } + }, + { + { + {0x00000004, 0x0000008d}, /* PHYREG01 */ + {0x00000014, 0x0000000e}, /* PHYREG05 */ + {0x00000018, 0x00000000}, /* PHYREG06 */ + {0x0000001c, 0x00000008}, /* PHYREG07 */ + {0xffffffff, 0xffffffff} + } + } +}, diff --git a/drivers/ram/rockchip/sdram-rv1126-lpddr4-detect-528.inc b/drivers/ram/rockchip/sdram-rv1126-lpddr4-detect-528.inc new file mode 100644 index 00000000000..8c8e14c3764 --- /dev/null +++ b/drivers/ram/rockchip/sdram-rv1126-lpddr4-detect-528.inc @@ -0,0 +1,78 @@ +{ + { + { + .rank = 0x1, + .col = 0xB, + .bk = 0x3, + .bw = 0x1, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0x11, + .cs1_row = 0x11, + .cs0_high16bit_row = 0x0, + .cs1_high16bit_row = 0x0, + .ddrconfig = 0 + }, + { + {0x34140b11}, + {0x0b030804}, + {0x00000602}, + {0x00001111}, + {0x00000054}, + {0x00000000}, + 0x000000ff + } + }, + { + .ddr_freq = 528, /* clock rate(MHz) */ + .dramtype = LPDDR4, + .num_channels = 1, + .stride = 0, + .odt = 0 + }, + { + { + {0x00000000, 0x81081020}, /* MSTR */ + {0x00000064, 0x0020004a}, /* RFSHTMG */ + {0x000000d0, 0x00020205}, /* INIT0 */ + {0x000000d4, 0x00350000}, /* INIT1 */ + {0x000000d8, 0x00000203}, /* INIT2 */ + {0x000000dc, 0x00240012}, /* INIT3 */ + {0x000000e0, 0x00310000}, /* INIT4 */ + {0x000000e8, 0x00100000}, /* INIT6 */ + {0x000000ec, 0x00000000}, /* INIT7 */ + {0x000000f4, 0x000f033f}, /* RANKCTL */ + {0x00000100, 0x0e0b090c}, /* DRAMTMG0 */ + {0x00000104, 0x00030412}, /* DRAMTMG1 */ + {0x00000108, 0x04070c0d}, /* DRAMTMG2 */ + {0x0000010c, 0x00505000}, /* DRAMTMG3 */ + {0x00000110, 0x05040306}, /* DRAMTMG4 */ + {0x00000114, 0x02030404}, /* DRAMTMG5 */ + {0x00000118, 0x01010004}, /* DRAMTMG6 */ + {0x0000011c, 0x00000301}, /* DRAMTMG7 */ + {0x00000120, 0x00000404}, /* DRAMTMG8 */ + {0x00000130, 0x00020000}, /* DRAMTMG12 */ + {0x00000134, 0x00100002}, /* DRAMTMG13 */ + {0x00000138, 0x0000004c}, /* DRAMTMG14 */ + {0x00000180, 0x01080008}, /* ZQCTL0 */ + {0x00000184, 0x00e00000}, /* ZQCTL1 */ + {0x00000190, 0x07040000}, /* DFITMG0 */ + {0x00000198, 0x07000101}, /* DFILPCFG0 */ + {0x000001a0, 0xc0400003}, /* DFIUPD0 */ + {0x00000240, 0x0905092c}, /* ODTCFG */ + {0x00000244, 0x00000101}, /* ODTMAP */ + {0x00000250, 0x00001f00}, /* SCHED */ + {0x00000490, 0x00000001}, /* PCTRL_0 */ + {0xffffffff, 0xffffffff} + } + }, + { + { + {0x00000004, 0x0000008d}, /* PHYREG01 */ + {0x00000014, 0x0000000e}, /* PHYREG05 */ + {0x00000018, 0x00000000}, /* PHYREG06 */ + {0x0000001c, 0x00000008}, /* PHYREG07 */ + {0xffffffff, 0xffffffff} + } + } +}, diff --git a/drivers/ram/rockchip/sdram-rv1126-lpddr4-detect-664.inc b/drivers/ram/rockchip/sdram-rv1126-lpddr4-detect-664.inc new file mode 100644 index 00000000000..f601fe5cb6a --- /dev/null +++ b/drivers/ram/rockchip/sdram-rv1126-lpddr4-detect-664.inc @@ -0,0 +1,78 @@ +{ + { + { + .rank = 0x1, + .col = 0xB, + .bk = 0x3, + .bw = 0x1, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0x11, + .cs1_row = 0x11, + .cs0_high16bit_row = 0x0, + .cs1_high16bit_row = 0x0, + .ddrconfig = 0 + }, + { + {0x36170d15}, + {0x0d030805}, + {0x00000602}, + {0x00001111}, + {0x00000054}, + {0x00000000}, + 0x000000ff + } + }, + { + .ddr_freq = 664, /* clock rate(MHz) */ + .dramtype = LPDDR4, + .num_channels = 1, + .stride = 0, + .odt = 1 + }, + { + { + {0x00000000, 0x81081020}, /* MSTR */ + {0x00000064, 0x0028005d}, /* RFSHTMG */ + {0x000000d0, 0x0002028a}, /* INIT0 */ + {0x000000d4, 0x00420000}, /* INIT1 */ + {0x000000d8, 0x00000204}, /* INIT2 */ + {0x000000dc, 0x00240012}, /* INIT3 */ + {0x000000e0, 0x00310000}, /* INIT4 */ + {0x000000e8, 0x00110000}, /* INIT6 */ + {0x000000ec, 0x00000000}, /* INIT7 */ + {0x000000f4, 0x000f033f}, /* RANKCTL */ + {0x00000100, 0x0f0e0b0e}, /* DRAMTMG0 */ + {0x00000104, 0x00030415}, /* DRAMTMG1 */ + {0x00000108, 0x04070d0d}, /* DRAMTMG2 */ + {0x0000010c, 0x00505000}, /* DRAMTMG3 */ + {0x00000110, 0x06040407}, /* DRAMTMG4 */ + {0x00000114, 0x02030505}, /* DRAMTMG5 */ + {0x00000118, 0x01010004}, /* DRAMTMG6 */ + {0x0000011c, 0x00000301}, /* DRAMTMG7 */ + {0x00000120, 0x00000404}, /* DRAMTMG8 */ + {0x00000130, 0x00020000}, /* DRAMTMG12 */ + {0x00000134, 0x00100002}, /* DRAMTMG13 */ + {0x00000138, 0x00000060}, /* DRAMTMG14 */ + {0x00000180, 0x014c000a}, /* ZQCTL0 */ + {0x00000184, 0x01100000}, /* ZQCTL1 */ + {0x00000190, 0x07040000}, /* DFITMG0 */ + {0x00000198, 0x07000101}, /* DFILPCFG0 */ + {0x000001a0, 0xc0400003}, /* DFIUPD0 */ + {0x00000240, 0x0a040b28}, /* ODTCFG */ + {0x00000244, 0x00000101}, /* ODTMAP */ + {0x00000250, 0x00001f00}, /* SCHED */ + {0x00000490, 0x00000001}, /* PCTRL_0 */ + {0xffffffff, 0xffffffff} + } + }, + { + { + {0x00000004, 0x0000008d}, /* PHYREG01 */ + {0x00000014, 0x0000000e}, /* PHYREG05 */ + {0x00000018, 0x00000000}, /* PHYREG06 */ + {0x0000001c, 0x00000008}, /* PHYREG07 */ + {0xffffffff, 0xffffffff} + } + } +}, diff --git a/drivers/ram/rockchip/sdram-rv1126-lpddr4-detect-784.inc b/drivers/ram/rockchip/sdram-rv1126-lpddr4-detect-784.inc new file mode 100644 index 00000000000..b8d9d5f1ce7 --- /dev/null +++ b/drivers/ram/rockchip/sdram-rv1126-lpddr4-detect-784.inc @@ -0,0 +1,78 @@ +{ + { + { + .rank = 0x1, + .col = 0xB, + .bk = 0x3, + .bw = 0x1, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0x11, + .cs1_row = 0x11, + .cs0_high16bit_row = 0x0, + .cs1_high16bit_row = 0x0, + .ddrconfig = 0 + }, + { + {0x391b1019}, + {0x10040805}, + {0x00000602}, + {0x00001111}, + {0x00000054}, + {0x00000000}, + 0x000000ff + } + }, + { + .ddr_freq = 784, /* clock rate(MHz) */ + .dramtype = LPDDR4, + .num_channels = 1, + .stride = 0, + .odt = 1 + }, + { + { + {0x00000000, 0x81081020}, /* MSTR */ + {0x00000064, 0x002f006e}, /* RFSHTMG */ + {0x000000d0, 0x000202ff}, /* INIT0 */ + {0x000000d4, 0x004e0000}, /* INIT1 */ + {0x000000d8, 0x00000204}, /* INIT2 */ + {0x000000dc, 0x00240012}, /* INIT3 */ + {0x000000e0, 0x00310000}, /* INIT4 */ + {0x000000e8, 0x00110000}, /* INIT6 */ + {0x000000ec, 0x00000000}, /* INIT7 */ + {0x000000f4, 0x000f033f}, /* RANKCTL */ + {0x00000100, 0x10100d11}, /* DRAMTMG0 */ + {0x00000104, 0x00030419}, /* DRAMTMG1 */ + {0x00000108, 0x04070c0d}, /* DRAMTMG2 */ + {0x0000010c, 0x00606000}, /* DRAMTMG3 */ + {0x00000110, 0x08040409}, /* DRAMTMG4 */ + {0x00000114, 0x02030606}, /* DRAMTMG5 */ + {0x00000118, 0x01010004}, /* DRAMTMG6 */ + {0x0000011c, 0x00000301}, /* DRAMTMG7 */ + {0x00000120, 0x00000505}, /* DRAMTMG8 */ + {0x00000130, 0x00020000}, /* DRAMTMG12 */ + {0x00000134, 0x00100002}, /* DRAMTMG13 */ + {0x00000138, 0x00000071}, /* DRAMTMG14 */ + {0x00000180, 0x0188000c}, /* ZQCTL0 */ + {0x00000184, 0x01400000}, /* ZQCTL1 */ + {0x00000190, 0x07040000}, /* DFITMG0 */ + {0x00000198, 0x07000101}, /* DFILPCFG0 */ + {0x000001a0, 0xc0400003}, /* DFIUPD0 */ + {0x00000240, 0x0a040b28}, /* ODTCFG */ + {0x00000244, 0x00000101}, /* ODTMAP */ + {0x00000250, 0x00001f00}, /* SCHED */ + {0x00000490, 0x00000001}, /* PCTRL_0 */ + {0xffffffff, 0xffffffff} + } + }, + { + { + {0x00000004, 0x0000008d}, /* PHYREG01 */ + {0x00000014, 0x0000000e}, /* PHYREG05 */ + {0x00000018, 0x00000000}, /* PHYREG06 */ + {0x0000001c, 0x00000008}, /* PHYREG07 */ + {0xffffffff, 0xffffffff} + } + } +}, diff --git a/drivers/ram/rockchip/sdram-rv1126-lpddr4-detect-924.inc b/drivers/ram/rockchip/sdram-rv1126-lpddr4-detect-924.inc new file mode 100644 index 00000000000..a2050f61534 --- /dev/null +++ b/drivers/ram/rockchip/sdram-rv1126-lpddr4-detect-924.inc @@ -0,0 +1,78 @@ +{ + { + { + .rank = 0x1, + .col = 0xB, + .bk = 0x3, + .bw = 0x1, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0x11, + .cs1_row = 0x11, + .cs0_high16bit_row = 0x0, + .cs1_high16bit_row = 0x0, + .ddrconfig = 0 + }, + { + {0x3e20121d}, + {0x12050a07}, + {0x00000602}, + {0x00001111}, + {0x00000054}, + {0x00000000}, + 0x000000ff + } + }, + { + .ddr_freq = 924, /* clock rate(MHz) */ + .dramtype = LPDDR4, + .num_channels = 1, + .stride = 0, + .odt = 1 + }, + { + { + {0x00000000, 0x81081020}, /* MSTR */ + {0x00000064, 0x00380082}, /* RFSHTMG */ + {0x000000d0, 0x00020388}, /* INIT0 */ + {0x000000d4, 0x005c0000}, /* INIT1 */ + {0x000000d8, 0x00000205}, /* INIT2 */ + {0x000000dc, 0x0034001b}, /* INIT3 */ + {0x000000e0, 0x00310000}, /* INIT4 */ + {0x000000e8, 0x00110000}, /* INIT6 */ + {0x000000ec, 0x00000000}, /* INIT7 */ + {0x000000f4, 0x000f033f}, /* RANKCTL */ + {0x00000100, 0x12130f14}, /* DRAMTMG0 */ + {0x00000104, 0x0004041e}, /* DRAMTMG1 */ + {0x00000108, 0x050a0e0f}, /* DRAMTMG2 */ + {0x0000010c, 0x00707000}, /* DRAMTMG3 */ + {0x00000110, 0x0904050a}, /* DRAMTMG4 */ + {0x00000114, 0x02040707}, /* DRAMTMG5 */ + {0x00000118, 0x01010005}, /* DRAMTMG6 */ + {0x0000011c, 0x00000401}, /* DRAMTMG7 */ + {0x00000120, 0x00000606}, /* DRAMTMG8 */ + {0x00000130, 0x00020000}, /* DRAMTMG12 */ + {0x00000134, 0x0a100002}, /* DRAMTMG13 */ + {0x00000138, 0x00000085}, /* DRAMTMG14 */ + {0x00000180, 0x01ce000e}, /* ZQCTL0 */ + {0x00000184, 0x01800000}, /* ZQCTL1 */ + {0x00000190, 0x07070001}, /* DFITMG0 */ + {0x00000198, 0x07000101}, /* DFILPCFG0 */ + {0x000001a0, 0xc0400003}, /* DFIUPD0 */ + {0x00000240, 0x0b050d3c}, /* ODTCFG */ + {0x00000244, 0x00000101}, /* ODTMAP */ + {0x00000250, 0x00001f00}, /* SCHED */ + {0x00000490, 0x00000001}, /* PCTRL_0 */ + {0xffffffff, 0xffffffff} + } + }, + { + { + {0x00000004, 0x0000008d}, /* PHYREG01 */ + {0x00000014, 0x00000014}, /* PHYREG05 */ + {0x00000018, 0x00000000}, /* PHYREG06 */ + {0x0000001c, 0x0000000a}, /* PHYREG07 */ + {0xffffffff, 0xffffffff} + } + } +}, diff --git a/drivers/ram/rockchip/sdram_common.c b/drivers/ram/rockchip/sdram_common.c index ec46ba54575..60fc90d0a5c 100644 --- a/drivers/ram/rockchip/sdram_common.c +++ b/drivers/ram/rockchip/sdram_common.c @@ -36,7 +36,7 @@ void sdram_print_dram_type(unsigned char dramtype) } void sdram_print_ddr_info(struct sdram_cap_info *cap_info, - struct sdram_base_params *base) + struct sdram_base_params *base, u32 split) { u64 cap; u32 bg; @@ -83,6 +83,8 @@ void sdram_print_ddr_info(struct sdram_cap_info *cap_info, cap = sdram_get_cs_cap(cap_info, 3, base->dramtype); if (cap_info->row_3_4) cap = cap * 3 / 4; + else if (split) + cap = cap / 2 + (split << 24) / 2; printascii(" Size="); printdec(cap >> 20); @@ -123,7 +125,7 @@ inline void sdram_print_dram_type(unsigned char dramtype) } inline void sdram_print_ddr_info(struct sdram_cap_info *cap_info, - struct sdram_base_params *base) + struct sdram_base_params *base, u32 split) { } diff --git a/drivers/ram/rockchip/sdram_pctl_px30.c b/drivers/ram/rockchip/sdram_pctl_px30.c index 331d85fba26..e5c80fb83b3 100644 --- a/drivers/ram/rockchip/sdram_pctl_px30.c +++ b/drivers/ram/rockchip/sdram_pctl_px30.c @@ -21,7 +21,7 @@ void pctl_read_mr(void __iomem *pctl_base, u32 rank, u32 mr_num) setbits_le32(pctl_base + DDR_PCTL2_MRCTRL0, 1u << 31); while (readl(pctl_base + DDR_PCTL2_MRCTRL0) & (1u << 31)) continue; - while (readl(pctl_base + DDR_PCTL2_MRSTAT) & MR_WR_BUSY) + while (readl(pctl_base + DDR_PCTL2_MRSTAT) & PCTL2_MR_WR_BUSY) continue; } @@ -33,7 +33,7 @@ void pctl_read_mr(void __iomem *pctl_base, u32 rank, u32 mr_num) int pctl_write_mr(void __iomem *pctl_base, u32 rank, u32 mr_num, u32 arg, u32 dramtype) { - while (readl(pctl_base + DDR_PCTL2_MRSTAT) & MR_WR_BUSY) + while (readl(pctl_base + DDR_PCTL2_MRSTAT) & PCTL2_MR_WR_BUSY) continue; if (dramtype == DDR3 || dramtype == DDR4) { writel((mr_num << 12) | (rank << 4) | (0 << 0), @@ -49,7 +49,7 @@ int pctl_write_mr(void __iomem *pctl_base, u32 rank, u32 mr_num, u32 arg, setbits_le32(pctl_base + DDR_PCTL2_MRCTRL0, 1u << 31); while (readl(pctl_base + DDR_PCTL2_MRCTRL0) & (1u << 31)) continue; - while (readl(pctl_base + DDR_PCTL2_MRSTAT) & MR_WR_BUSY) + while (readl(pctl_base + DDR_PCTL2_MRSTAT) & PCTL2_MR_WR_BUSY) continue; return 0; diff --git a/drivers/ram/rockchip/sdram_px30.c b/drivers/ram/rockchip/sdram_px30.c index 98b2593ac49..2728d93be32 100644 --- a/drivers/ram/rockchip/sdram_px30.c +++ b/drivers/ram/rockchip/sdram_px30.c @@ -125,11 +125,11 @@ u32 addrmap[][8] = { struct dram_info dram_info; struct px30_sdram_params sdram_configs[] = { -#if defined(CONFIG_RAM_PX30_DDR4) +#if defined(CONFIG_RAM_ROCKCHIP_DDR4) #include "sdram-px30-ddr4-detect-333.inc" -#elif defined(CONFIG_RAM_PX30_LPDDR2) +#elif defined(CONFIG_RAM_ROCKCHIP_LPDDR2) #include "sdram-px30-lpddr2-detect-333.inc" -#elif defined(CONFIG_RAM_PX30_LPDDR3) +#elif defined(CONFIG_RAM_ROCKCHIP_LPDDR3) #include "sdram-px30-lpddr3-detect-333.inc" #else #include "sdram-px30-ddr3-detect-333.inc" @@ -711,7 +711,7 @@ int sdram_init(void) if (ret) goto error; - sdram_print_ddr_info(&sdram_params->ch.cap_info, &sdram_params->base); + sdram_print_ddr_info(&sdram_params->ch.cap_info, &sdram_params->base, 0); printascii("out\n"); return ret; diff --git a/drivers/ram/rockchip/sdram_rk3328.c b/drivers/ram/rockchip/sdram_rk3328.c index b511c6bf6fe..184c93f7763 100644 --- a/drivers/ram/rockchip/sdram_rk3328.c +++ b/drivers/ram/rockchip/sdram_rk3328.c @@ -506,7 +506,7 @@ static int sdram_init_detect(struct dram_info *dram, writel(sys_reg3, &dram->grf->os_reg[3]); } - sdram_print_ddr_info(&sdram_params->ch.cap_info, &sdram_params->base); + sdram_print_ddr_info(&sdram_params->ch.cap_info, &sdram_params->base, 0); return 0; } diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 136e4ede712..b1fea04e84a 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -1625,7 +1625,7 @@ static void set_ddr_stride(struct rk3399_pmusgrf_regs *pmusgrf, u32 stride) rk_clrsetreg(&pmusgrf->soc_con4, 0x1f << 10, stride << 10); } -#if !defined(CONFIG_RAM_RK3399_LPDDR4) +#if !defined(CONFIG_RAM_ROCKCHIP_LPDDR4) static int data_training_first(struct dram_info *dram, u32 channel, u8 rank, struct rk3399_sdram_params *params) { @@ -2558,8 +2558,7 @@ static int lpddr4_set_rate(struct dram_info *dram, return 0; } - -#endif /* CONFIG_RAM_RK3399_LPDDR4 */ +#endif /* CONFIG_RAM_ROCKCHIP_LPDDR4 */ /* CS0,n=1 * CS1,n=2 @@ -2987,7 +2986,7 @@ static int sdram_init(struct dram_info *dram, continue; } - sdram_print_ddr_info(cap_info, ¶ms->base); + sdram_print_ddr_info(cap_info, ¶ms->base, 0); set_memory_map(chan, channel, params); cap_info->ddrconfig = calculate_ddrconfig(params, channel); @@ -3059,7 +3058,7 @@ static int conv_of_plat(struct udevice *dev) #endif static const struct sdram_rk3399_ops rk3399_ops = { -#if !defined(CONFIG_RAM_RK3399_LPDDR4) +#if !defined(CONFIG_RAM_ROCKCHIP_LPDDR4) .data_training_first = data_training_first, .set_rate_index = switch_to_phy_index1, .modify_param = modify_param, diff --git a/drivers/ram/rockchip/sdram_rv1126.c b/drivers/ram/rockchip/sdram_rv1126.c new file mode 100644 index 00000000000..9e1376a940f --- /dev/null +++ b/drivers/ram/rockchip/sdram_rv1126.c @@ -0,0 +1,3543 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * (C) Copyright 2020 Rockchip Electronics Co., Ltd. + * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. + */ + +#include <common.h> +#include <debug_uart.h> +#include <dm.h> +#include <ram.h> +#include <syscon.h> +#include <asm/io.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/hardware.h> +#include <asm/arch-rockchip/cru_rv1126.h> +#include <asm/arch-rockchip/grf_rv1126.h> +#include <asm/arch-rockchip/sdram_common.h> +#include <asm/arch-rockchip/sdram_rv1126.h> +#include <linux/delay.h> + +/* define training flag */ +#define CA_TRAINING (0x1 << 0) +#define READ_GATE_TRAINING (0x1 << 1) +#define WRITE_LEVELING (0x1 << 2) +#define WRITE_TRAINING (0x1 << 3) +#define READ_TRAINING (0x1 << 4) +#define FULL_TRAINING (0xff) + +#define SKEW_RX_SIGNAL (0) +#define SKEW_TX_SIGNAL (1) +#define SKEW_CA_SIGNAL (2) + +#define DESKEW_MDF_ABS_VAL (0) +#define DESKEW_MDF_DIFF_VAL (1) + +struct dram_info { +#if defined(CONFIG_TPL_BUILD) || \ + (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD)) + void __iomem *pctl; + void __iomem *phy; + struct rv1126_cru *cru; + struct msch_regs *msch; + struct rv1126_ddrgrf *ddrgrf; + struct rv1126_grf *grf; + u32 sr_idle; + u32 pd_idle; +#endif + struct ram_info info; + struct rv1126_pmugrf *pmugrf; +}; + +#if defined(CONFIG_TPL_BUILD) || \ + (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD)) + +#define GRF_BASE_ADDR 0xfe000000 +#define PMU_GRF_BASE_ADDR 0xfe020000 +#define DDR_GRF_BASE_ADDR 0xfe030000 +#define BUS_SGRF_BASE_ADDR 0xfe0a0000 +#define SERVER_MSCH_BASE_ADDR 0xfe800000 +#define CRU_BASE_ADDR 0xff490000 +#define DDR_PHY_BASE_ADDR 0xff4a0000 +#define UPCTL2_BASE_ADDR 0xffa50000 + +#define SGRF_SOC_CON2 0x8 +#define SGRF_SOC_CON12 0x30 +#define SGRF_SOC_CON13 0x34 + +struct dram_info dram_info; + +struct rv1126_sdram_params sdram_configs[] = { +#if defined(CONFIG_RAM_ROCKCHIP_LPDDR4) +# include "sdram-rv1126-lpddr4-detect-328.inc" +# include "sdram-rv1126-lpddr4-detect-396.inc" +# include "sdram-rv1126-lpddr4-detect-528.inc" +# include "sdram-rv1126-lpddr4-detect-664.inc" +# include "sdram-rv1126-lpddr4-detect-784.inc" +# include "sdram-rv1126-lpddr4-detect-924.inc" +# include "sdram-rv1126-lpddr4-detect-1056.inc" +#else +# include "sdram-rv1126-ddr3-detect-328.inc" +# include "sdram-rv1126-ddr3-detect-396.inc" +# include "sdram-rv1126-ddr3-detect-528.inc" +# include "sdram-rv1126-ddr3-detect-664.inc" +# include "sdram-rv1126-ddr3-detect-784.inc" +# include "sdram-rv1126-ddr3-detect-924.inc" +# include "sdram-rv1126-ddr3-detect-1056.inc" +#endif +}; + +u32 common_info[] = { +#include "sdram-rv1126-loader_params.inc" +}; + +#if defined(CONFIG_CMD_DDR_TEST_TOOL) +static struct rw_trn_result rw_trn_result; +#endif + +static struct rv1126_fsp_param fsp_param[MAX_IDX]; + +static u8 lp3_odt_value; + +static s8 wrlvl_result[2][4]; + +/* DDR configuration 0-9 */ +u16 ddr_cfg_2_rbc[] = { + ((0 << 8) | (3 << 5) | (0 << 4) | (1 << 3) | 3), /* 0 */ + ((1 << 8) | (3 << 5) | (0 << 4) | (1 << 3) | 2), /* 1 */ + ((1 << 8) | (2 << 5) | (0 << 4) | (1 << 3) | 3), /* 2 */ + ((1 << 8) | (3 << 5) | (0 << 4) | (1 << 3) | 1), /* 3 */ + ((0 << 8) | (2 << 5) | (0 << 4) | (1 << 3) | 4), /* 4 */ + ((0 << 8) | (3 << 5) | (1 << 4) | (1 << 3) | 1), /* 5 */ + ((0 << 8) | (3 << 5) | (1 << 4) | (1 << 3) | 2), /* 6 */ + ((0 << 8) | (2 << 5) | (1 << 4) | (1 << 3) | 3), /* 7 */ + ((1 << 8) | (3 << 5) | (0 << 4) | (0 << 3) | 2), /* 8 */ + ((1 << 8) | (2 << 5) | (0 << 4) | (1 << 3) | 2) /* 9 */ +}; + +/* DDR configuration 10-21 */ +u8 ddr4_cfg_2_rbc[] = { + ((0 << 7) | (3 << 4) | (0 << 3) | (2 << 1) | 0), /* 10 */ + ((1 << 7) | (2 << 4) | (0 << 3) | (2 << 1) | 0), /* 11 */ + ((0 << 7) | (4 << 4) | (0 << 3) | (1 << 1) | 0), /* 12 */ + ((1 << 7) | (3 << 4) | (0 << 3) | (1 << 1) | 0), /* 13 */ + ((0 << 7) | (4 << 4) | (0 << 3) | (2 << 1) | 1), /* 14 */ + ((1 << 7) | (3 << 4) | (0 << 3) | (2 << 1) | 1), /* 15 */ + ((1 << 7) | (4 << 4) | (0 << 3) | (1 << 1) | 1), /* 16 */ + ((0 << 7) | (2 << 4) | (1 << 3) | (2 << 1) | 0), /* 17 */ + ((0 << 7) | (3 << 4) | (1 << 3) | (1 << 1) | 0), /* 18 */ + ((0 << 7) | (3 << 4) | (1 << 3) | (2 << 1) | 1), /* 19 */ + ((0 << 7) | (4 << 4) | (1 << 3) | (1 << 1) | 1), /* 20 */ + ((1 << 7) | (4 << 4) | (0 << 3) | (0 << 1) | 0) /* 21 */ +}; + +/* DDR configuration 22-28 */ +u16 ddr_cfg_2_rbc_p2[] = { + ((1 << 8) | (3 << 5) | (0 << 4) | (1 << 3) | 0), /* 22 */ + ((0 << 8) | (4 << 5) | (0 << 4) | (1 << 3) | 2), /* 23 */ + ((1 << 8) | (3 << 5) | (0 << 4) | (0 << 3) | 3), /* 24 */ + ((0 << 8) | (3 << 5) | (1 << 4) | (0 << 3) | 3), /* 25 */ + ((0 << 8) | (4 << 5) | (1 << 4) | (0 << 3) | 2), /* 26 */ + ((1 << 8) | (4 << 5) | (0 << 4) | (0 << 3) | 2), /* 27 */ + ((0 << 8) | (4 << 5) | (0 << 4) | (0 << 3) | 3) /* 28 */ +}; + +u8 d4_rbc_2_d3_rbc[][2] = { + {10, 0}, + {11, 2}, + {12, 23}, + {13, 1}, + {14, 28}, + {15, 24}, + {16, 27}, + {17, 7}, + {18, 6}, + {19, 25}, + {20, 26}, + {21, 3} +}; + +u32 addrmap[29][9] = { + {24, 0x00090909, 0x00000000, 0x00000000, 0x00001f00, 0x08080808, + 0x08080808, 0x00000f0f, 0x3f3f}, /* 0 */ + {23, 0x00080808, 0x00000000, 0x00000000, 0x00001f1f, 0x07070707, + 0x07070707, 0x00000f0f, 0x3f3f}, /* 1 */ + {23, 0x00090909, 0x00000000, 0x00000000, 0x00001f00, 0x08080808, + 0x0f080808, 0x00000f0f, 0x3f3f}, /* 2 */ + {22, 0x00070707, 0x00000000, 0x1f000000, 0x00001f1f, 0x06060606, + 0x06060606, 0x00000f0f, 0x3f3f}, /* 3 */ + {24, 0x000a0a0a, 0x00000000, 0x00000000, 0x00000000, 0x09090909, + 0x0f090909, 0x00000f0f, 0x3f3f}, /* 4 */ + {6, 0x00070707, 0x00000000, 0x1f000000, 0x00001f1f, 0x07070707, + 0x07070707, 0x00000f0f, 0x3f3f}, /* 5 */ + {7, 0x00080808, 0x00000000, 0x00000000, 0x00001f1f, 0x08080808, + 0x08080808, 0x00000f0f, 0x3f3f}, /* 6 */ + {8, 0x00090909, 0x00000000, 0x00000000, 0x00001f00, 0x09090909, + 0x0f090909, 0x00000f0f, 0x3f3f}, /* 7 */ + {22, 0x001f0808, 0x00000000, 0x00000000, 0x00001f1f, 0x06060606, + 0x06060606, 0x00000f0f, 0x3f3f}, /* 8 */ + {23, 0x00080808, 0x00000000, 0x00000000, 0x00001f1f, 0x07070707, + 0x0f070707, 0x00000f0f, 0x3f3f}, /* 9 */ + + {24, 0x003f0a0a, 0x01010100, 0x01010101, 0x00001f1f, 0x08080808, + 0x08080808, 0x00000f0f, 0x0801}, /* 10 */ + {23, 0x003f0a0a, 0x01010100, 0x01010101, 0x00001f1f, 0x08080808, + 0x0f080808, 0x00000f0f, 0x0801}, /* 11 */ + {24, 0x003f0909, 0x00000007, 0x1f000000, 0x00001f1f, 0x07070707, + 0x07070707, 0x00000f07, 0x0700}, /* 12 */ + {23, 0x003f0909, 0x00000007, 0x1f000000, 0x00001f1f, 0x07070707, + 0x07070707, 0x00000f0f, 0x0700}, /* 13 */ + {24, 0x003f0909, 0x01010100, 0x01010101, 0x00001f1f, 0x07070707, + 0x07070707, 0x00000f07, 0x3f01}, /* 14 */ + {23, 0x003f0909, 0x01010100, 0x01010101, 0x00001f1f, 0x07070707, + 0x07070707, 0x00000f0f, 0x3f01}, /* 15 */ + {23, 0x003f0808, 0x00000007, 0x1f000000, 0x00001f1f, 0x06060606, + 0x06060606, 0x00000f06, 0x3f00}, /* 16 */ + {8, 0x003f0a0a, 0x01010100, 0x01010101, 0x00001f1f, 0x09090909, + 0x0f090909, 0x00000f0f, 0x0801}, /* 17 */ + {7, 0x003f0909, 0x00000007, 0x1f000000, 0x00001f1f, 0x08080808, + 0x08080808, 0x00000f0f, 0x0700}, /* 18 */ + {7, 0x003f0909, 0x01010100, 0x01010101, 0x00001f1f, 0x08080808, + 0x08080808, 0x00000f0f, 0x3f01}, /* 19 */ + + {6, 0x003f0808, 0x00000007, 0x1f000000, 0x00001f1f, 0x07070707, + 0x07070707, 0x00000f07, 0x3f00}, /* 20 */ + {23, 0x003f0909, 0x00000006, 0x1f1f0000, 0x00001f1f, 0x06060606, + 0x06060606, 0x00000f06, 0x0600}, /* 21 */ + {21, 0x00060606, 0x00000000, 0x1f1f0000, 0x00001f1f, 0x05050505, + 0x05050505, 0x00000f0f, 0x3f3f}, /* 22 */ + + {24, 0x00080808, 0x00000000, 0x00000000, 0x00001f1f, 0x07070707, + 0x07070707, 0x00000f07, 0x3f3f}, /* 23 */ + {23, 0x003f0909, 0x00000000, 0x00000000, 0x00001f00, 0x07070707, + 0x07070707, 0x00000f0f, 0x3f3f}, /* 24 */ + {7, 0x003f0909, 0x00000000, 0x00000000, 0x00001f00, 0x08080808, + 0x08080808, 0x00000f0f, 0x3f3f}, /* 25 */ + {6, 0x003f0808, 0x00000000, 0x00000000, 0x00001f1f, 0x07070707, + 0x07070707, 0x00000f07, 0x3f3f}, /* 26 */ + {23, 0x003f0808, 0x00000000, 0x00000000, 0x00001f1f, 0x06060606, + 0x06060606, 0x00000f06, 0x3f3f}, /* 27 */ + {24, 0x003f0909, 0x00000000, 0x00000000, 0x00001f00, 0x07070707, + 0x07070707, 0x00000f07, 0x3f3f} /* 28 */ +}; + +static u8 dq_sel[22][3] = { + {0x0, 0x17, 0x22}, + {0x1, 0x18, 0x23}, + {0x2, 0x19, 0x24}, + {0x3, 0x1a, 0x25}, + {0x4, 0x1b, 0x26}, + {0x5, 0x1c, 0x27}, + {0x6, 0x1d, 0x28}, + {0x7, 0x1e, 0x29}, + {0x8, 0x16, 0x21}, + {0x9, 0x1f, 0x2a}, + {0xa, 0x20, 0x2b}, + {0x10, 0x1, 0xc}, + {0x11, 0x2, 0xd}, + {0x12, 0x3, 0xe}, + {0x13, 0x4, 0xf}, + {0x14, 0x5, 0x10}, + {0x15, 0x6, 0x11}, + {0x16, 0x7, 0x12}, + {0x17, 0x8, 0x13}, + {0x18, 0x0, 0xb}, + {0x19, 0x9, 0x14}, + {0x1a, 0xa, 0x15} +}; + +static u16 grp_addr[4] = { + ADD_GROUP_CS0_A, + ADD_GROUP_CS0_B, + ADD_GROUP_CS1_A, + ADD_GROUP_CS1_B +}; + +static u8 wrlvl_result_offset[2][4] = { + {0xa0 + 0x26, 0xa0 + 0x27, 0xd0 + 0x26, 0xd0 + 0x27}, + {0xa0 + 0x28, 0xa0 + 0x29, 0xd0 + 0x28, 0xd0 + 0x29}, +}; + +static u16 dqs_dq_skew_adr[16] = { + 0x170 + 0, /* SKEW_UPDATE_RX_CS0_DQS0 */ + 0x170 + 0xb, /* SKEW_UPDATE_RX_CS0_DQS1 */ + 0x1d0 + 0, /* SKEW_UPDATE_RX_CS0_DQS2 */ + 0x1d0 + 0xb, /* SKEW_UPDATE_RX_CS0_DQS3 */ + 0x1a0 + 0, /* SKEW_UPDATE_RX_CS1_DQS0 */ + 0x1a0 + 0xb, /* SKEW_UPDATE_RX_CS1_DQS1 */ + 0x200 + 0, /* SKEW_UPDATE_RX_CS1_DQS2 */ + 0x200 + 0xb, /* SKEW_UPDATE_RX_CS1_DQS3 */ + 0x170 + 0x16, /* SKEW_UPDATE_TX_CS0_DQS0 */ + 0x170 + 0x21, /* SKEW_UPDATE_TX_CS0_DQS1 */ + 0x1d0 + 0x16, /* SKEW_UPDATE_TX_CS0_DQS2 */ + 0x1d0 + 0x21, /* SKEW_UPDATE_TX_CS0_DQS3 */ + 0x1a0 + 0x16, /* SKEW_UPDATE_TX_CS1_DQS0 */ + 0x1a0 + 0x21, /* SKEW_UPDATE_TX_CS1_DQS1 */ + 0x200 + 0x16, /* SKEW_UPDATE_TX_CS1_DQS2 */ + 0x200 + 0x21, /* SKEW_UPDATE_TX_CS1_DQS3 */ +}; + +static void rkclk_ddr_reset(struct dram_info *dram, + u32 ctl_srstn, u32 ctl_psrstn, + u32 phy_srstn, u32 phy_psrstn) +{ + writel(UPCTL2_SRSTN_REQ(ctl_srstn) | UPCTL2_PSRSTN_REQ(ctl_psrstn) | + UPCTL2_ASRSTN_REQ(ctl_srstn), + BUS_SGRF_BASE_ADDR + SGRF_SOC_CON13); + + writel(DDRPHY_SRSTN_REQ(phy_srstn) | DDRPHY_PSRSTN_REQ(phy_psrstn), + &dram->cru->softrst_con[12]); +} + +static void rkclk_set_dpll(struct dram_info *dram, unsigned int hz) +{ + unsigned int refdiv, postdiv1, postdiv2, fbdiv; + int delay = 1000; + u32 mhz = hz / MHz; + struct global_info *gbl_info; + struct sdram_head_info_index_v2 *index = + (struct sdram_head_info_index_v2 *)common_info; + u32 ssmod_info; + u32 dsmpd = 1; + + gbl_info = (struct global_info *)((void *)common_info + + index->global_index.offset * 4); + ssmod_info = gbl_info->info_2t; + refdiv = 1; + if (mhz <= 100) { + postdiv1 = 6; + postdiv2 = 4; + } else if (mhz <= 150) { + postdiv1 = 4; + postdiv2 = 4; + } else if (mhz <= 200) { + postdiv1 = 6; + postdiv2 = 2; + } else if (mhz <= 300) { + postdiv1 = 4; + postdiv2 = 2; + } else if (mhz <= 400) { + postdiv1 = 6; + postdiv2 = 1; + } else { + postdiv1 = 4; + postdiv2 = 1; + } + fbdiv = (mhz * refdiv * postdiv1 * postdiv2) / 24; + + writel(DPLL_MODE(CLOCK_FROM_XIN_OSC), &dram->cru->mode); + + writel(0x1f000000, &dram->cru->clksel_con[64]); + writel(POSTDIV1(postdiv1) | FBDIV(fbdiv), &dram->cru->pll[1].con0); + /* enable ssmod */ + if (PLL_SSMOD_SPREAD(ssmod_info)) { + dsmpd = 0; + clrsetbits_le32(&dram->cru->pll[1].con2, + 0xffffff << 0, 0x0 << 0); + writel(SSMOD_SPREAD(PLL_SSMOD_SPREAD(ssmod_info)) | + SSMOD_DIVVAL(PLL_SSMOD_DIV(ssmod_info)) | + SSMOD_DOWNSPREAD(PLL_SSMOD_DOWNSPREAD(ssmod_info)) | + SSMOD_RESET(0) | + SSMOD_DIS_SSCG(0) | + SSMOD_BP(0), + &dram->cru->pll[1].con3); + } + writel(DSMPD(dsmpd) | POSTDIV2(postdiv2) | REFDIV(refdiv), + &dram->cru->pll[1].con1); + + while (delay > 0) { + udelay(1); + if (LOCK(readl(&dram->cru->pll[1].con1))) + break; + delay--; + } + + writel(DPLL_MODE(CLOCK_FROM_PLL), &dram->cru->mode); +} + +static void rkclk_configure_ddr(struct dram_info *dram, + struct rv1126_sdram_params *sdram_params) +{ + /* for inno ddr phy need freq / 2 */ + rkclk_set_dpll(dram, sdram_params->base.ddr_freq * MHZ / 2); +} + +static unsigned int + calculate_ddrconfig(struct rv1126_sdram_params *sdram_params) +{ + struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; + u32 cs, bw, die_bw, col, row, bank; + u32 cs1_row; + u32 i, tmp; + u32 ddrconf = -1; + u32 row_3_4; + + cs = cap_info->rank; + bw = cap_info->bw; + die_bw = cap_info->dbw; + col = cap_info->col; + row = cap_info->cs0_row; + cs1_row = cap_info->cs1_row; + bank = cap_info->bk; + row_3_4 = cap_info->row_3_4; + + if (sdram_params->base.dramtype == DDR4) { + if (cs == 2 && row == cs1_row && !row_3_4) { + tmp = ((row - 13) << 4) | (1 << 3) | (bw << 1) | + die_bw; + for (i = 17; i < 21; i++) { + if (((tmp & 0xf) == + (ddr4_cfg_2_rbc[i - 10] & 0xf)) && + ((tmp & 0x70) <= + (ddr4_cfg_2_rbc[i - 10] & 0x70))) { + ddrconf = i; + goto out; + } + } + } + + tmp = ((cs - 1) << 7) | ((row - 13) << 4) | (bw << 1) | die_bw; + for (i = 10; i < 21; i++) { + if (((tmp & 0xf) == (ddr4_cfg_2_rbc[i - 10] & 0xf)) && + ((tmp & 0x70) <= (ddr4_cfg_2_rbc[i - 10] & 0x70)) && + ((tmp & 0x80) <= (ddr4_cfg_2_rbc[i - 10] & 0x80))) { + ddrconf = i; + goto out; + } + } + } else { + if (cs == 2 && row == cs1_row && bank == 3) { + for (i = 5; i < 8; i++) { + if (((bw + col - 10) == (ddr_cfg_2_rbc[i] & + 0x7)) && + ((row - 13) << 5) <= (ddr_cfg_2_rbc[i] & + (0x7 << 5))) { + ddrconf = i; + goto out; + } + } + } + + tmp = ((cs - 1) << 8) | ((row - 13) << 5) | + ((bw + col - 10) << 0); + if (bank == 3) + tmp |= (1 << 3); + + for (i = 0; i < 9; i++) + if (((tmp & 0x1f) == (ddr_cfg_2_rbc[i] & 0x1f)) && + ((tmp & (7 << 5)) <= + (ddr_cfg_2_rbc[i] & (7 << 5))) && + ((tmp & (1 << 8)) <= + (ddr_cfg_2_rbc[i] & (1 << 8)))) { + ddrconf = i; + goto out; + } + + for (i = 0; i < 7; i++) + if (((tmp & 0x1f) == (ddr_cfg_2_rbc_p2[i] & 0x1f)) && + ((tmp & (7 << 5)) <= + (ddr_cfg_2_rbc_p2[i] & (7 << 5))) && + ((tmp & (1 << 8)) <= + (ddr_cfg_2_rbc_p2[i] & (1 << 8)))) { + ddrconf = i + 22; + goto out; + } + + if (cs == 1 && bank == 3 && row <= 17 && + (col + bw) == 12) + ddrconf = 23; + } + +out: + if (ddrconf > 28) + printascii("calculate ddrconfig error\n"); + + if (sdram_params->base.dramtype == DDR4) { + for (i = 0; i < ARRAY_SIZE(d4_rbc_2_d3_rbc) ; i++) { + if (ddrconf == d4_rbc_2_d3_rbc[i][0]) { + if (ddrconf == 21 && row > 16) + printascii("warn:ddrconf21 row > 16\n"); + else + ddrconf = d4_rbc_2_d3_rbc[i][1]; + break; + } + } + } + + return ddrconf; +} + +static void sw_set_req(struct dram_info *dram) +{ + void __iomem *pctl_base = dram->pctl; + + /* clear sw_done=0 */ + writel(PCTL2_SW_DONE_CLEAR, pctl_base + DDR_PCTL2_SWCTL); +} + +static void sw_set_ack(struct dram_info *dram) +{ + void __iomem *pctl_base = dram->pctl; + + /* set sw_done=1 */ + writel(PCTL2_SW_DONE, pctl_base + DDR_PCTL2_SWCTL); + while (1) { + /* wait programming done */ + if (readl(pctl_base + DDR_PCTL2_SWSTAT) & + PCTL2_SW_DONE_ACK) + break; + } +} + +static void set_ctl_address_map(struct dram_info *dram, + struct rv1126_sdram_params *sdram_params) +{ + struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; + void __iomem *pctl_base = dram->pctl; + u32 ddrconf = cap_info->ddrconfig; + u32 i, row; + + row = cap_info->cs0_row; + if (sdram_params->base.dramtype == DDR4) { + for (i = 0; i < ARRAY_SIZE(d4_rbc_2_d3_rbc) ; i++) { + if (ddrconf == d4_rbc_2_d3_rbc[i][1]) { + ddrconf = d4_rbc_2_d3_rbc[i][0]; + break; + } + } + } + + if (ddrconf >= ARRAY_SIZE(addrmap)) { + printascii("set ctl address map fail\n"); + return; + } + + sdram_copy_to_reg((u32 *)(pctl_base + DDR_PCTL2_ADDRMAP0), + &addrmap[ddrconf][0], ARRAY_SIZE(addrmap[ddrconf]) * 4); + + /* unused row set to 0xf */ + for (i = 17; i >= row; i--) + setbits_le32(pctl_base + DDR_PCTL2_ADDRMAP6 + + ((i - 12) * 8 / 32) * 4, + 0xf << ((i - 12) * 8 % 32)); + + if (sdram_params->base.dramtype == LPDDR3 && cap_info->row_3_4) + setbits_le32(pctl_base + DDR_PCTL2_ADDRMAP6, 1 << 31); + if (sdram_params->base.dramtype == DDR4 && cap_info->bw == 0x1) + setbits_le32(pctl_base + DDR_PCTL2_PCCFG, 1 << 8); + + if (cap_info->rank == 1) + clrsetbits_le32(pctl_base + DDR_PCTL2_ADDRMAP0, 0x1f, 0x1f); +} + +static void phy_pll_set(struct dram_info *dram, u32 freq, u32 wait) +{ + void __iomem *phy_base = dram->phy; + u32 fbdiv, prediv, postdiv, postdiv_en; + + if (wait) { + clrbits_le32(PHY_REG(phy_base, 0x53), PHY_PD_DISB); + while (!(readl(PHY_REG(phy_base, 0x90)) & PHY_PLL_LOCK)) + continue; + } else { + freq /= MHz; + prediv = 1; + if (freq <= 200) { + fbdiv = 16; + postdiv = 2; + postdiv_en = 1; + } else if (freq <= 456) { + fbdiv = 8; + postdiv = 1; + postdiv_en = 1; + } else { + fbdiv = 4; + postdiv = 0; + postdiv_en = 0; + } + writel(fbdiv & 0xff, PHY_REG(phy_base, 0x50)); + clrsetbits_le32(PHY_REG(phy_base, 0x51), PHY_PBDIV_BIT9_MASK, + (fbdiv >> 8) & 1); + clrsetbits_le32(PHY_REG(phy_base, 0x51), PHY_POSTDIV_EN_MASK, + postdiv_en << PHY_POSTDIV_EN_SHIFT); + + clrsetbits_le32(PHY_REG(phy_base, 0x52), + PHY_PREDIV_MASK << PHY_PREDIV_SHIFT, prediv); + clrsetbits_le32(PHY_REG(phy_base, 0x53), + PHY_POSTDIV_MASK << PHY_POSTDIV_SHIFT, + postdiv << PHY_POSTDIV_SHIFT); + } +} + +static const u16 d3_phy_drv_2_ohm[][2] = { + {PHY_DDR3_RON_455ohm, 455}, + {PHY_DDR3_RON_230ohm, 230}, + {PHY_DDR3_RON_153ohm, 153}, + {PHY_DDR3_RON_115ohm, 115}, + {PHY_DDR3_RON_91ohm, 91}, + {PHY_DDR3_RON_76ohm, 76}, + {PHY_DDR3_RON_65ohm, 65}, + {PHY_DDR3_RON_57ohm, 57}, + {PHY_DDR3_RON_51ohm, 51}, + {PHY_DDR3_RON_46ohm, 46}, + {PHY_DDR3_RON_41ohm, 41}, + {PHY_DDR3_RON_38ohm, 38}, + {PHY_DDR3_RON_35ohm, 35}, + {PHY_DDR3_RON_32ohm, 32}, + {PHY_DDR3_RON_30ohm, 30}, + {PHY_DDR3_RON_28ohm, 28}, + {PHY_DDR3_RON_27ohm, 27}, + {PHY_DDR3_RON_25ohm, 25}, + {PHY_DDR3_RON_24ohm, 24}, + {PHY_DDR3_RON_23ohm, 23}, + {PHY_DDR3_RON_22ohm, 22}, + {PHY_DDR3_RON_21ohm, 21}, + {PHY_DDR3_RON_20ohm, 20} +}; + +static u16 d3_phy_odt_2_ohm[][2] = { + {PHY_DDR3_RTT_DISABLE, 0}, + {PHY_DDR3_RTT_561ohm, 561}, + {PHY_DDR3_RTT_282ohm, 282}, + {PHY_DDR3_RTT_188ohm, 188}, + {PHY_DDR3_RTT_141ohm, 141}, + {PHY_DDR3_RTT_113ohm, 113}, + {PHY_DDR3_RTT_94ohm, 94}, + {PHY_DDR3_RTT_81ohm, 81}, + {PHY_DDR3_RTT_72ohm, 72}, + {PHY_DDR3_RTT_64ohm, 64}, + {PHY_DDR3_RTT_58ohm, 58}, + {PHY_DDR3_RTT_52ohm, 52}, + {PHY_DDR3_RTT_48ohm, 48}, + {PHY_DDR3_RTT_44ohm, 44}, + {PHY_DDR3_RTT_41ohm, 41}, + {PHY_DDR3_RTT_38ohm, 38}, + {PHY_DDR3_RTT_37ohm, 37}, + {PHY_DDR3_RTT_34ohm, 34}, + {PHY_DDR3_RTT_32ohm, 32}, + {PHY_DDR3_RTT_31ohm, 31}, + {PHY_DDR3_RTT_29ohm, 29}, + {PHY_DDR3_RTT_28ohm, 28}, + {PHY_DDR3_RTT_27ohm, 27}, + {PHY_DDR3_RTT_25ohm, 25} +}; + +static u16 d4lp3_phy_drv_2_ohm[][2] = { + {PHY_DDR4_LPDDR3_RON_482ohm, 482}, + {PHY_DDR4_LPDDR3_RON_244ohm, 244}, + {PHY_DDR4_LPDDR3_RON_162ohm, 162}, + {PHY_DDR4_LPDDR3_RON_122ohm, 122}, + {PHY_DDR4_LPDDR3_RON_97ohm, 97}, + {PHY_DDR4_LPDDR3_RON_81ohm, 81}, + {PHY_DDR4_LPDDR3_RON_69ohm, 69}, + {PHY_DDR4_LPDDR3_RON_61ohm, 61}, + {PHY_DDR4_LPDDR3_RON_54ohm, 54}, + {PHY_DDR4_LPDDR3_RON_48ohm, 48}, + {PHY_DDR4_LPDDR3_RON_44ohm, 44}, + {PHY_DDR4_LPDDR3_RON_40ohm, 40}, + {PHY_DDR4_LPDDR3_RON_37ohm, 37}, + {PHY_DDR4_LPDDR3_RON_34ohm, 34}, + {PHY_DDR4_LPDDR3_RON_32ohm, 32}, + {PHY_DDR4_LPDDR3_RON_30ohm, 30}, + {PHY_DDR4_LPDDR3_RON_28ohm, 28}, + {PHY_DDR4_LPDDR3_RON_27ohm, 27}, + {PHY_DDR4_LPDDR3_RON_25ohm, 25}, + {PHY_DDR4_LPDDR3_RON_24ohm, 24}, + {PHY_DDR4_LPDDR3_RON_23ohm, 23}, + {PHY_DDR4_LPDDR3_RON_22ohm, 22}, + {PHY_DDR4_LPDDR3_RON_21ohm, 21} +}; + +static u16 d4lp3_phy_odt_2_ohm[][2] = { + {PHY_DDR4_LPDDR3_RTT_DISABLE, 0}, + {PHY_DDR4_LPDDR3_RTT_586ohm, 586}, + {PHY_DDR4_LPDDR3_RTT_294ohm, 294}, + {PHY_DDR4_LPDDR3_RTT_196ohm, 196}, + {PHY_DDR4_LPDDR3_RTT_148ohm, 148}, + {PHY_DDR4_LPDDR3_RTT_118ohm, 118}, + {PHY_DDR4_LPDDR3_RTT_99ohm, 99}, + {PHY_DDR4_LPDDR3_RTT_85ohm, 58}, + {PHY_DDR4_LPDDR3_RTT_76ohm, 76}, + {PHY_DDR4_LPDDR3_RTT_67ohm, 67}, + {PHY_DDR4_LPDDR3_RTT_60ohm, 60}, + {PHY_DDR4_LPDDR3_RTT_55ohm, 55}, + {PHY_DDR4_LPDDR3_RTT_50ohm, 50}, + {PHY_DDR4_LPDDR3_RTT_46ohm, 46}, + {PHY_DDR4_LPDDR3_RTT_43ohm, 43}, + {PHY_DDR4_LPDDR3_RTT_40ohm, 40}, + {PHY_DDR4_LPDDR3_RTT_38ohm, 38}, + {PHY_DDR4_LPDDR3_RTT_36ohm, 36}, + {PHY_DDR4_LPDDR3_RTT_34ohm, 34}, + {PHY_DDR4_LPDDR3_RTT_32ohm, 32}, + {PHY_DDR4_LPDDR3_RTT_31ohm, 31}, + {PHY_DDR4_LPDDR3_RTT_29ohm, 29}, + {PHY_DDR4_LPDDR3_RTT_28ohm, 28}, + {PHY_DDR4_LPDDR3_RTT_27ohm, 27} +}; + +static u16 lp4_phy_drv_2_ohm[][2] = { + {PHY_LPDDR4_RON_501ohm, 501}, + {PHY_LPDDR4_RON_253ohm, 253}, + {PHY_LPDDR4_RON_168ohm, 168}, + {PHY_LPDDR4_RON_126ohm, 126}, + {PHY_LPDDR4_RON_101ohm, 101}, + {PHY_LPDDR4_RON_84ohm, 84}, + {PHY_LPDDR4_RON_72ohm, 72}, + {PHY_LPDDR4_RON_63ohm, 63}, + {PHY_LPDDR4_RON_56ohm, 56}, + {PHY_LPDDR4_RON_50ohm, 50}, + {PHY_LPDDR4_RON_46ohm, 46}, + {PHY_LPDDR4_RON_42ohm, 42}, + {PHY_LPDDR4_RON_38ohm, 38}, + {PHY_LPDDR4_RON_36ohm, 36}, + {PHY_LPDDR4_RON_33ohm, 33}, + {PHY_LPDDR4_RON_31ohm, 31}, + {PHY_LPDDR4_RON_29ohm, 29}, + {PHY_LPDDR4_RON_28ohm, 28}, + {PHY_LPDDR4_RON_26ohm, 26}, + {PHY_LPDDR4_RON_25ohm, 25}, + {PHY_LPDDR4_RON_24ohm, 24}, + {PHY_LPDDR4_RON_23ohm, 23}, + {PHY_LPDDR4_RON_22ohm, 22} +}; + +static u16 lp4_phy_odt_2_ohm[][2] = { + {PHY_LPDDR4_RTT_DISABLE, 0}, + {PHY_LPDDR4_RTT_604ohm, 604}, + {PHY_LPDDR4_RTT_303ohm, 303}, + {PHY_LPDDR4_RTT_202ohm, 202}, + {PHY_LPDDR4_RTT_152ohm, 152}, + {PHY_LPDDR4_RTT_122ohm, 122}, + {PHY_LPDDR4_RTT_101ohm, 101}, + {PHY_LPDDR4_RTT_87ohm, 87}, + {PHY_LPDDR4_RTT_78ohm, 78}, + {PHY_LPDDR4_RTT_69ohm, 69}, + {PHY_LPDDR4_RTT_62ohm, 62}, + {PHY_LPDDR4_RTT_56ohm, 56}, + {PHY_LPDDR4_RTT_52ohm, 52}, + {PHY_LPDDR4_RTT_48ohm, 48}, + {PHY_LPDDR4_RTT_44ohm, 44}, + {PHY_LPDDR4_RTT_41ohm, 41}, + {PHY_LPDDR4_RTT_39ohm, 39}, + {PHY_LPDDR4_RTT_37ohm, 37}, + {PHY_LPDDR4_RTT_35ohm, 35}, + {PHY_LPDDR4_RTT_33ohm, 33}, + {PHY_LPDDR4_RTT_32ohm, 32}, + {PHY_LPDDR4_RTT_30ohm, 30}, + {PHY_LPDDR4_RTT_29ohm, 29}, + {PHY_LPDDR4_RTT_27ohm, 27} +}; + +static u32 lp4_odt_calc(u32 odt_ohm) +{ + u32 odt; + + if (odt_ohm == 0) + odt = LPDDR4_DQODT_DIS; + else if (odt_ohm <= 40) + odt = LPDDR4_DQODT_40; + else if (odt_ohm <= 48) + odt = LPDDR4_DQODT_48; + else if (odt_ohm <= 60) + odt = LPDDR4_DQODT_60; + else if (odt_ohm <= 80) + odt = LPDDR4_DQODT_80; + else if (odt_ohm <= 120) + odt = LPDDR4_DQODT_120; + else + odt = LPDDR4_DQODT_240; + + return odt; +} + +static void *get_ddr_drv_odt_info(u32 dramtype) +{ + struct sdram_head_info_index_v2 *index = + (struct sdram_head_info_index_v2 *)common_info; + void *ddr_info = 0; + + if (dramtype == DDR4) + ddr_info = (void *)common_info + index->ddr4_index.offset * 4; + else if (dramtype == DDR3) + ddr_info = (void *)common_info + index->ddr3_index.offset * 4; + else if (dramtype == LPDDR3) + ddr_info = (void *)common_info + index->lp3_index.offset * 4; + else if (dramtype == LPDDR4) + ddr_info = (void *)common_info + index->lp4_index.offset * 4; + else + printascii("unsupported dram type\n"); + return ddr_info; +} + +static void set_lp4_vref(struct dram_info *dram, struct lp4_info *lp4_info, + u32 freq_mhz, u32 dst_fsp, u32 dramtype) +{ + void __iomem *pctl_base = dram->pctl; + u32 ca_vref, dq_vref; + + if (freq_mhz <= LP4_CA_ODT_EN_FREQ(lp4_info->ca_odten_freq)) + ca_vref = LP4_CA_VREF(lp4_info->vref_when_odtoff); + else + ca_vref = LP4_CA_VREF(lp4_info->vref_when_odten); + + if (freq_mhz <= LP4_DQ_ODT_EN_FREQ(lp4_info->dq_odten_freq)) + dq_vref = LP4_DQ_VREF(lp4_info->vref_when_odtoff); + else + dq_vref = LP4_DQ_VREF(lp4_info->vref_when_odten); + + if (dramtype == LPDDR4) { + if (ca_vref < 100) + ca_vref = 100; + if (ca_vref > 420) + ca_vref = 420; + + if (ca_vref <= 300) + ca_vref = (0 << 6) | (ca_vref - 100) / 4; + else + ca_vref = (1 << 6) | (ca_vref - 220) / 4; + + if (dq_vref < 100) + dq_vref = 100; + if (dq_vref > 420) + dq_vref = 420; + + if (dq_vref <= 300) + dq_vref = (0 << 6) | (dq_vref - 100) / 4; + else + dq_vref = (1 << 6) | (dq_vref - 220) / 4; + } else { + ca_vref = ca_vref * 11 / 6; + if (ca_vref < 150) + ca_vref = 150; + if (ca_vref > 629) + ca_vref = 629; + + if (ca_vref <= 449) + ca_vref = (0 << 6) | (ca_vref - 150) / 4; + else + ca_vref = (1 << 6) | (ca_vref - 329) / 4; + + if (dq_vref < 150) + dq_vref = 150; + if (dq_vref > 629) + dq_vref = 629; + + if (dq_vref <= 449) + dq_vref = (0 << 6) | (dq_vref - 150) / 6; + else + dq_vref = (1 << 6) | (dq_vref - 329) / 6; + } + sw_set_req(dram); + clrsetbits_le32(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + + DDR_PCTL2_INIT6, + PCTL2_MR_MASK << PCTL2_LPDDR4_MR12_SHIFT, + ca_vref << PCTL2_LPDDR4_MR12_SHIFT); + + clrsetbits_le32(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + + DDR_PCTL2_INIT7, + PCTL2_MR_MASK << PCTL2_LPDDR4_MR14_SHIFT, + dq_vref << PCTL2_LPDDR4_MR14_SHIFT); + sw_set_ack(dram); +} + +static void set_ds_odt(struct dram_info *dram, + struct rv1126_sdram_params *sdram_params, u32 dst_fsp) +{ + void __iomem *phy_base = dram->phy; + void __iomem *pctl_base = dram->pctl; + u32 dramtype = sdram_params->base.dramtype; + struct ddr2_3_4_lp2_3_info *ddr_info; + struct lp4_info *lp4_info; + u32 i, j, tmp; + const u16 (*p_drv)[2]; + const u16 (*p_odt)[2]; + u32 drv_info, sr_info; + u32 phy_dq_drv_ohm, phy_clk_drv_ohm, phy_ca_drv_ohm, dram_drv_ohm; + u32 phy_odt_ohm, dram_odt_ohm; + u32 lp4_pu_cal, phy_lp4_drv_pd_en; + u32 phy_odt_up_en, phy_odt_dn_en; + u32 sr_dq, sr_clk; + u32 freq = sdram_params->base.ddr_freq; + u32 mr1_mr3, mr11, mr22, vref_out, vref_inner; + u32 phy_clk_drv = 0, phy_odt = 0, phy_ca_drv = 0, dram_caodt_ohm = 0; + u32 phy_dq_drv = 0; + u32 phy_odt_up = 0, phy_odt_dn = 0; + + ddr_info = get_ddr_drv_odt_info(dramtype); + lp4_info = (void *)ddr_info; + + if (!ddr_info) + return; + + /* dram odt en freq control phy drv, dram odt and phy sr */ + if (freq <= DRAMODT_EN_FREQ(ddr_info->odten_freq)) { + drv_info = ddr_info->drv_when_odtoff; + dram_odt_ohm = 0; + sr_info = ddr_info->sr_when_odtoff; + phy_lp4_drv_pd_en = + PHY_LP4_DRV_PULLDOWN_EN_ODTOFF(lp4_info->odt_info); + } else { + drv_info = ddr_info->drv_when_odten; + dram_odt_ohm = ODT_INFO_DRAM_ODT(ddr_info->odt_info); + sr_info = ddr_info->sr_when_odten; + phy_lp4_drv_pd_en = + PHY_LP4_DRV_PULLDOWN_EN_ODTEN(lp4_info->odt_info); + } + phy_dq_drv_ohm = + DRV_INFO_PHY_DQ_DRV(drv_info); + phy_clk_drv_ohm = + DRV_INFO_PHY_CLK_DRV(drv_info); + phy_ca_drv_ohm = + DRV_INFO_PHY_CA_DRV(drv_info); + + sr_dq = DQ_SR_INFO(sr_info); + sr_clk = CLK_SR_INFO(sr_info); + + /* phy odt en freq control dram drv and phy odt */ + if (freq <= PHYODT_EN_FREQ(ddr_info->odten_freq)) { + dram_drv_ohm = DRV_INFO_DRAM_DQ_DRV(ddr_info->drv_when_odtoff); + lp4_pu_cal = LP4_DRV_PU_CAL_ODTOFF(lp4_info->odt_info); + phy_odt_ohm = 0; + phy_odt_up_en = 0; + phy_odt_dn_en = 0; + } else { + dram_drv_ohm = + DRV_INFO_DRAM_DQ_DRV(ddr_info->drv_when_odten); + phy_odt_ohm = ODT_INFO_PHY_ODT(ddr_info->odt_info); + phy_odt_up_en = + ODT_INFO_PULLUP_EN(ddr_info->odt_info); + phy_odt_dn_en = + ODT_INFO_PULLDOWN_EN(ddr_info->odt_info); + lp4_pu_cal = LP4_DRV_PU_CAL_ODTEN(lp4_info->odt_info); + } + + if (dramtype == LPDDR4) { + if (phy_odt_ohm) { + phy_odt_up_en = 0; + phy_odt_dn_en = 1; + } + if (freq <= LP4_CA_ODT_EN_FREQ(lp4_info->ca_odten_freq)) + dram_caodt_ohm = 0; + else + dram_caodt_ohm = + ODT_INFO_LP4_CA_ODT(lp4_info->odt_info); + } + + if (dramtype == DDR3) { + p_drv = d3_phy_drv_2_ohm; + p_odt = d3_phy_odt_2_ohm; + } else if (dramtype == LPDDR4) { + p_drv = lp4_phy_drv_2_ohm; + p_odt = lp4_phy_odt_2_ohm; + } else { + p_drv = d4lp3_phy_drv_2_ohm; + p_odt = d4lp3_phy_odt_2_ohm; + } + + for (i = ARRAY_SIZE(d3_phy_drv_2_ohm) - 1; ; i--) { + if (phy_dq_drv_ohm <= *(*(p_drv + i) + 1)) { + phy_dq_drv = **(p_drv + i); + break; + } + if (i == 0) + break; + } + for (i = ARRAY_SIZE(d3_phy_drv_2_ohm) - 1; ; i--) { + if (phy_clk_drv_ohm <= *(*(p_drv + i) + 1)) { + phy_clk_drv = **(p_drv + i); + break; + } + if (i == 0) + break; + } + for (i = ARRAY_SIZE(d3_phy_drv_2_ohm) - 1; ; i--) { + if (phy_ca_drv_ohm <= *(*(p_drv + i) + 1)) { + phy_ca_drv = **(p_drv + i); + break; + } + if (i == 0) + break; + } + if (!phy_odt_ohm) + phy_odt = 0; + else + for (i = ARRAY_SIZE(d4lp3_phy_odt_2_ohm) - 1; ; i--) { + if (phy_odt_ohm <= *(*(p_odt + i) + 1)) { + phy_odt = **(p_odt + i); + break; + } + if (i == 0) + break; + } + + if (dramtype != LPDDR4) { + if (!phy_odt_ohm || (phy_odt_up_en && phy_odt_dn_en)) + vref_inner = 0x80; + else if (phy_odt_up_en) + vref_inner = (2 * dram_drv_ohm + phy_odt_ohm) * 128 / + (dram_drv_ohm + phy_odt_ohm); + else + vref_inner = phy_odt_ohm * 128 / + (phy_odt_ohm + dram_drv_ohm); + + if (dramtype != DDR3 && dram_odt_ohm) + vref_out = (2 * phy_dq_drv_ohm + dram_odt_ohm) * 128 / + (phy_dq_drv_ohm + dram_odt_ohm); + else + vref_out = 0x80; + } else { + /* for lp4 and lp4x*/ + if (phy_odt_ohm) + vref_inner = + (PHY_LP4_DQ_VREF(lp4_info->vref_when_odten) * + 256) / 1000; + else + vref_inner = + (PHY_LP4_DQ_VREF(lp4_info->vref_when_odtoff) * + 256) / 1000; + + vref_out = 0x80; + } + + /* default ZQCALIB bypass mode */ + clrsetbits_le32(PHY_REG(phy_base, 0x100), 0x1f, phy_ca_drv); + clrsetbits_le32(PHY_REG(phy_base, 0x101), 0x1f, phy_ca_drv); + clrsetbits_le32(PHY_REG(phy_base, 0x102), 0x1f, phy_clk_drv); + clrsetbits_le32(PHY_REG(phy_base, 0x103), 0x1f, phy_clk_drv); + if (dramtype == LPDDR4) { + clrsetbits_le32(PHY_REG(phy_base, 0x107), 0x1f, phy_clk_drv); + clrsetbits_le32(PHY_REG(phy_base, 0x108), 0x1f, phy_clk_drv); + } else { + clrsetbits_le32(PHY_REG(phy_base, 0x107), 0x1f, phy_ca_drv); + clrsetbits_le32(PHY_REG(phy_base, 0x108), 0x1f, phy_ca_drv); + } + /* clk / cmd slew rate */ + clrsetbits_le32(PHY_REG(phy_base, 0x106), 0x1f, sr_clk); + + phy_lp4_drv_pd_en = (~phy_lp4_drv_pd_en) & 1; + if (phy_odt_up_en) + phy_odt_up = phy_odt; + if (phy_odt_dn_en) + phy_odt_dn = phy_odt; + + for (i = 0; i < 4; i++) { + j = 0x110 + i * 0x10; + clrsetbits_le32(PHY_REG(phy_base, j + 1), 0x1f, phy_odt_up); + clrsetbits_le32(PHY_REG(phy_base, j), 0x1f, phy_odt_dn); + clrsetbits_le32(PHY_REG(phy_base, j + 2), 0x1f, phy_dq_drv); + clrsetbits_le32(PHY_REG(phy_base, j + 3), 0x1f, phy_dq_drv); + writel(vref_inner, PHY_REG(phy_base, 0x118 + i * 0x10)); + + clrsetbits_le32(PHY_REG(phy_base, 0x114 + i * 0x10), + 1 << 3, phy_lp4_drv_pd_en << 3); + if (dramtype == LPDDR4) + clrbits_le32(PHY_REG(phy_base, 0x114 + i * 0x10), BIT(5)); + /* dq slew rate */ + clrsetbits_le32(PHY_REG(phy_base, 0x117 + i * 0x10), + 0x1f, sr_dq); + } + + /* reg_rx_vref_value_update */ + setbits_le32(PHY_REG(phy_base, 0x71), 1 << 5); + clrbits_le32(PHY_REG(phy_base, 0x71), 1 << 5); + + /* RAM VREF */ + writel(vref_out, PHY_REG(phy_base, 0x105)); + if (dramtype == LPDDR3) + udelay(100); + + if (dramtype == LPDDR4) + set_lp4_vref(dram, lp4_info, freq, dst_fsp, dramtype); + + if (dramtype == DDR3 || dramtype == DDR4) { + mr1_mr3 = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + + DDR_PCTL2_INIT3); + mr1_mr3 = mr1_mr3 >> PCTL2_DDR34_MR1_SHIFT & PCTL2_MR_MASK; + } else { + mr1_mr3 = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + + DDR_PCTL2_INIT4); + mr1_mr3 = mr1_mr3 >> PCTL2_LPDDR234_MR3_SHIFT & PCTL2_MR_MASK; + } + + if (dramtype == DDR3) { + mr1_mr3 &= ~(DDR3_DS_MASK | DDR3_RTT_NOM_MASK); + if (dram_drv_ohm == 34) + mr1_mr3 |= DDR3_DS_34; + + if (dram_odt_ohm == 0) + mr1_mr3 |= DDR3_RTT_NOM_DIS; + else if (dram_odt_ohm <= 40) + mr1_mr3 |= DDR3_RTT_NOM_40; + else if (dram_odt_ohm <= 60) + mr1_mr3 |= DDR3_RTT_NOM_60; + else + mr1_mr3 |= DDR3_RTT_NOM_120; + + } else if (dramtype == DDR4) { + mr1_mr3 &= ~(DDR4_DS_MASK | DDR4_RTT_NOM_MASK); + if (dram_drv_ohm == 48) + mr1_mr3 |= DDR4_DS_48; + + if (dram_odt_ohm == 0) + mr1_mr3 |= DDR4_RTT_NOM_DIS; + else if (dram_odt_ohm <= 34) + mr1_mr3 |= DDR4_RTT_NOM_34; + else if (dram_odt_ohm <= 40) + mr1_mr3 |= DDR4_RTT_NOM_40; + else if (dram_odt_ohm <= 48) + mr1_mr3 |= DDR4_RTT_NOM_48; + else if (dram_odt_ohm <= 60) + mr1_mr3 |= DDR4_RTT_NOM_60; + else + mr1_mr3 |= DDR4_RTT_NOM_120; + + } else if (dramtype == LPDDR3) { + if (dram_drv_ohm <= 34) + mr1_mr3 |= LPDDR3_DS_34; + else if (dram_drv_ohm <= 40) + mr1_mr3 |= LPDDR3_DS_40; + else if (dram_drv_ohm <= 48) + mr1_mr3 |= LPDDR3_DS_48; + else if (dram_drv_ohm <= 60) + mr1_mr3 |= LPDDR3_DS_60; + else if (dram_drv_ohm <= 80) + mr1_mr3 |= LPDDR3_DS_80; + + if (dram_odt_ohm == 0) + lp3_odt_value = LPDDR3_ODT_DIS; + else if (dram_odt_ohm <= 60) + lp3_odt_value = LPDDR3_ODT_60; + else if (dram_odt_ohm <= 120) + lp3_odt_value = LPDDR3_ODT_120; + else + lp3_odt_value = LPDDR3_ODT_240; + } else {/* for lpddr4 and lpddr4x */ + /* MR3 for lp4 PU-CAL and PDDS */ + mr1_mr3 &= ~(LPDDR4_PDDS_MASK | LPDDR4_PU_CAL_MASK); + mr1_mr3 |= lp4_pu_cal; + + tmp = lp4_odt_calc(dram_drv_ohm); + if (!tmp) + tmp = LPDDR4_PDDS_240; + mr1_mr3 |= (tmp << LPDDR4_PDDS_SHIFT); + + /* MR11 for lp4 ca odt, dq odt set */ + mr11 = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + + DDR_PCTL2_INIT6); + mr11 = mr11 >> PCTL2_LPDDR4_MR11_SHIFT & PCTL2_MR_MASK; + + mr11 &= ~(LPDDR4_DQODT_MASK | LPDDR4_CAODT_MASK); + + tmp = lp4_odt_calc(dram_odt_ohm); + mr11 |= (tmp << LPDDR4_DQODT_SHIFT); + + tmp = lp4_odt_calc(dram_caodt_ohm); + mr11 |= (tmp << LPDDR4_CAODT_SHIFT); + sw_set_req(dram); + clrsetbits_le32(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + + DDR_PCTL2_INIT6, + PCTL2_MR_MASK << PCTL2_LPDDR4_MR11_SHIFT, + mr11 << PCTL2_LPDDR4_MR11_SHIFT); + sw_set_ack(dram); + + /* MR22 for soc odt/odt-ck/odt-cs/odt-ca */ + mr22 = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + + DDR_PCTL2_INIT7); + mr22 = mr22 >> PCTL2_LPDDR4_MR22_SHIFT & PCTL2_MR_MASK; + mr22 &= ~LPDDR4_SOC_ODT_MASK; + + tmp = lp4_odt_calc(phy_odt_ohm); + mr22 |= tmp; + mr22 = mr22 | + (LP4_ODTE_CK_EN(lp4_info->cs_drv_ca_odt_info) << + LPDDR4_ODTE_CK_SHIFT) | + (LP4_ODTE_CS_EN(lp4_info->cs_drv_ca_odt_info) << + LPDDR4_ODTE_CS_SHIFT) | + (LP4_ODTD_CA_EN(lp4_info->cs_drv_ca_odt_info) << + LPDDR4_ODTD_CA_SHIFT); + + sw_set_req(dram); + clrsetbits_le32(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + + DDR_PCTL2_INIT7, + PCTL2_MR_MASK << PCTL2_LPDDR4_MR22_SHIFT, + mr22 << PCTL2_LPDDR4_MR22_SHIFT); + sw_set_ack(dram); + } + + if (dramtype == DDR4 || dramtype == DDR3) { + sw_set_req(dram); + clrsetbits_le32(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + + DDR_PCTL2_INIT3, + PCTL2_MR_MASK << PCTL2_DDR34_MR1_SHIFT, + mr1_mr3 << PCTL2_DDR34_MR1_SHIFT); + sw_set_ack(dram); + } else { + sw_set_req(dram); + clrsetbits_le32(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + + DDR_PCTL2_INIT4, + PCTL2_MR_MASK << PCTL2_LPDDR234_MR3_SHIFT, + mr1_mr3 << PCTL2_LPDDR234_MR3_SHIFT); + sw_set_ack(dram); + } +} + +static int sdram_cmd_dq_path_remap(struct dram_info *dram, + struct rv1126_sdram_params *sdram_params) +{ + void __iomem *phy_base = dram->phy; + u32 dramtype = sdram_params->base.dramtype; + struct sdram_head_info_index_v2 *index = + (struct sdram_head_info_index_v2 *)common_info; + struct dq_map_info *map_info; + + map_info = (struct dq_map_info *)((void *)common_info + + index->dq_map_index.offset * 4); + + if (dramtype <= LPDDR4) + writel((map_info->byte_map[dramtype / 4] >> + ((dramtype % 4) * 8)) & 0xff, + PHY_REG(phy_base, 0x4f)); + + return 0; +} + +static void phy_cfg(struct dram_info *dram, + struct rv1126_sdram_params *sdram_params) +{ + struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; + void __iomem *phy_base = dram->phy; + u32 i, dq_map, tmp; + u32 byte1 = 0, byte0 = 0; + + sdram_cmd_dq_path_remap(dram, sdram_params); + + phy_pll_set(dram, sdram_params->base.ddr_freq * MHZ, 0); + for (i = 0; sdram_params->phy_regs.phy[i][0] != 0xFFFFFFFF; i++) { + writel(sdram_params->phy_regs.phy[i][1], + phy_base + sdram_params->phy_regs.phy[i][0]); + } + + clrbits_le32(PHY_REG(phy_base, 0x62), BIT(5)); + dq_map = readl(PHY_REG(phy_base, 0x4f)); + for (i = 0; i < 4; i++) { + if (((dq_map >> (i * 2)) & 0x3) == 0) + byte0 = i; + if (((dq_map >> (i * 2)) & 0x3) == 1) + byte1 = i; + } + + tmp = readl(PHY_REG(phy_base, 0xf)) & (~PHY_DQ_WIDTH_MASK); + if (cap_info->bw == 2) + tmp |= 0xf; + else if (cap_info->bw == 1) + tmp |= ((1 << byte0) | (1 << byte1)); + else + tmp |= (1 << byte0); + + writel(tmp, PHY_REG(phy_base, 0xf)); + + /* lpddr4 odt control by phy, enable cs0 odt */ + if (sdram_params->base.dramtype == LPDDR4) + clrsetbits_le32(PHY_REG(phy_base, 0x20), 0x7 << 4, + (1 << 6) | (1 << 4)); + /* for ca training ca vref choose range1 */ + setbits_le32(PHY_REG(phy_base, 0x1e), BIT(6)); + setbits_le32(PHY_REG(phy_base, 0x1f), BIT(6)); + /* for wr training PHY_0x7c[5], choose range0 */ + clrbits_le32(PHY_REG(phy_base, 0x7c), BIT(5)); +} + +static int update_refresh_reg(struct dram_info *dram) +{ + void __iomem *pctl_base = dram->pctl; + u32 ret; + + ret = readl(pctl_base + DDR_PCTL2_RFSHCTL3) ^ (1 << 1); + writel(ret, pctl_base + DDR_PCTL2_RFSHCTL3); + + return 0; +} + +/* + * rank = 1: cs0 + * rank = 2: cs1 + */ +int read_mr(struct dram_info *dram, u32 rank, u32 mr_num, u32 dramtype) +{ + u32 ret; + u32 i, temp; + u32 dqmap; + + void __iomem *pctl_base = dram->pctl; + struct sdram_head_info_index_v2 *index = + (struct sdram_head_info_index_v2 *)common_info; + struct dq_map_info *map_info; + + map_info = (struct dq_map_info *)((void *)common_info + + index->dq_map_index.offset * 4); + + if (dramtype == LPDDR2) + dqmap = map_info->lp2_dq0_7_map; + else + dqmap = map_info->lp3_dq0_7_map; + + pctl_read_mr(pctl_base, rank, mr_num); + + ret = (readl(&dram->ddrgrf->ddr_grf_status[0]) & 0xff); + + if (dramtype != LPDDR4) { + temp = 0; + for (i = 0; i < 8; i++) { + temp = temp | (((ret >> i) & 0x1) << + ((dqmap >> (i * 4)) & 0xf)); + } + } else { + temp = (readl(&dram->ddrgrf->ddr_grf_status[1]) & 0xff); + } + + return temp; +} + +/* before call this function autorefresh should be disabled */ +void send_a_refresh(struct dram_info *dram) +{ + void __iomem *pctl_base = dram->pctl; + + while (readl(pctl_base + DDR_PCTL2_DBGSTAT) & 0x3) + continue; + writel(0x3, pctl_base + DDR_PCTL2_DBGCMD); +} + +static void enter_sr(struct dram_info *dram, u32 en) +{ + void __iomem *pctl_base = dram->pctl; + + if (en) { + setbits_le32(pctl_base + DDR_PCTL2_PWRCTL, PCTL2_SELFREF_SW); + while (1) { + if (((readl(pctl_base + DDR_PCTL2_STAT) & + PCTL2_SELFREF_TYPE_MASK) == + PCTL2_SELFREF_TYPE_SR_NOT_AUTO) && + ((readl(pctl_base + DDR_PCTL2_STAT) & + PCTL2_OPERATING_MODE_MASK) == + PCTL2_OPERATING_MODE_SR)) + break; + } + } else { + clrbits_le32(pctl_base + DDR_PCTL2_PWRCTL, PCTL2_SELFREF_SW); + while ((readl(pctl_base + DDR_PCTL2_STAT) & + PCTL2_OPERATING_MODE_MASK) == PCTL2_OPERATING_MODE_SR) + continue; + } +} + +void record_dq_prebit(struct dram_info *dram) +{ + u32 group, i, tmp; + void __iomem *phy_base = dram->phy; + + for (group = 0; group < 4; group++) { + for (i = 0; i < ARRAY_SIZE(dq_sel); i++) { + /* l_loop_invdelaysel */ + writel(dq_sel[i][0], PHY_REG(phy_base, + grp_addr[group] + 0x2c)); + tmp = readl(PHY_REG(phy_base, grp_addr[group] + 0x2e)); + writel(tmp, PHY_REG(phy_base, + grp_addr[group] + dq_sel[i][1])); + + /* r_loop_invdelaysel */ + writel(dq_sel[i][0], PHY_REG(phy_base, + grp_addr[group] + 0x2d)); + tmp = readl(PHY_REG(phy_base, grp_addr[group] + 0x2f)); + writel(tmp, PHY_REG(phy_base, + grp_addr[group] + dq_sel[i][2])); + } + } +} + +static void update_dq_rx_prebit(struct dram_info *dram) +{ + void __iomem *phy_base = dram->phy; + + clrsetbits_le32(PHY_REG(phy_base, 0x70), BIT(1) | BIT(6) | BIT(4), + BIT(4)); + udelay(1); + clrbits_le32(PHY_REG(phy_base, 0x70), BIT(4)); +} + +static void update_dq_tx_prebit(struct dram_info *dram) +{ + void __iomem *phy_base = dram->phy; + + clrbits_le32(PHY_REG(phy_base, 0x7a), BIT(1)); + setbits_le32(PHY_REG(phy_base, 0x2), BIT(3)); + setbits_le32(PHY_REG(phy_base, 0xc), BIT(6)); + udelay(1); + clrbits_le32(PHY_REG(phy_base, 0xc), BIT(6)); +} + +static void update_ca_prebit(struct dram_info *dram) +{ + void __iomem *phy_base = dram->phy; + + clrbits_le32(PHY_REG(phy_base, 0x25), BIT(2)); + setbits_le32(PHY_REG(phy_base, 0x22), BIT(6)); + udelay(1); + clrbits_le32(PHY_REG(phy_base, 0x22), BIT(6)); +} + +/* + * dir: 0: de-skew = delta_* + * 1: de-skew = reg val - delta_* + * delta_dir: value for differential signal: clk/ + * delta_sig: value for single signal: ca/cmd + */ +static void modify_ca_deskew(struct dram_info *dram, u32 dir, int delta_dif, + int delta_sig, u32 cs, u32 dramtype) +{ + void __iomem *phy_base = dram->phy; + u32 i, cs_en, tmp; + u32 dfi_lp_stat = 0; + + if (cs == 0) + cs_en = 1; + else if (cs == 2) + cs_en = 2; + else + cs_en = 3; + + if (dramtype == LPDDR4 && + ((readl(PHY_REG(phy_base, 0x60)) & BIT(5)) == 0)) { + dfi_lp_stat = 1; + setbits_le32(PHY_REG(phy_base, 0x60), BIT(5)); + } + enter_sr(dram, 1); + + for (i = 0; i < 0x20; i++) { + if (dir == DESKEW_MDF_ABS_VAL) + tmp = delta_sig; + else + tmp = readl(PHY_REG(phy_base, 0x150 + i)) + + delta_sig; + writel(tmp, PHY_REG(phy_base, 0x150 + i)); + } + + if (dir == DESKEW_MDF_ABS_VAL) + tmp = delta_dif; + else + tmp = readl(PHY_REG(phy_base, 0x150 + 0x17)) - + delta_sig + delta_dif; + writel(tmp, PHY_REG(phy_base, 0x150 + 0x17)); + writel(tmp, PHY_REG(phy_base, 0x150 + 0x18)); + if (dramtype == LPDDR4) { + writel(tmp, PHY_REG(phy_base, 0x150 + 0x4)); + writel(tmp, PHY_REG(phy_base, 0x150 + 0xa)); + + clrbits_le32(PHY_REG(phy_base, 0x10), cs_en << 6); + update_ca_prebit(dram); + } + enter_sr(dram, 0); + + if (dfi_lp_stat) + clrbits_le32(PHY_REG(phy_base, 0x60), BIT(5)); +} + +static u32 get_min_value(struct dram_info *dram, u32 signal, u32 rank) +{ + u32 i, j, offset = 0; + u32 min = 0x3f; + void __iomem *phy_base = dram->phy; + u32 byte_en; + + if (signal == SKEW_TX_SIGNAL) + offset = 8; + + if (signal == SKEW_CA_SIGNAL) { + for (i = 0; i < 0x20; i++) + min = MIN(min, readl(PHY_REG(phy_base, 0x150 + i))); + } else { + byte_en = readl(PHY_REG(phy_base, 0xf)) & 0xf; + for (j = offset; j < offset + rank * 4; j++) { + if (!((byte_en >> (j % 4)) & 1)) + continue; + for (i = 0; i < 11; i++) + min = MIN(min, + readl(PHY_REG(phy_base, + dqs_dq_skew_adr[j] + + i))); + } + } + + return min; +} + +static u32 low_power_update(struct dram_info *dram, u32 en) +{ + void __iomem *pctl_base = dram->pctl; + u32 lp_stat = 0; + + if (en) { + setbits_le32(pctl_base + DDR_PCTL2_PWRCTL, en & 0xf); + } else { + lp_stat = readl(pctl_base + DDR_PCTL2_PWRCTL) & 0xf; + clrbits_le32(pctl_base + DDR_PCTL2_PWRCTL, 0xf); + } + + return lp_stat; +} + +/* + * signal: + * dir: 0: de-skew = delta_* + * 1: de-skew = reg val - delta_* + * delta_dir: value for differential signal: dqs + * delta_sig: value for single signal: dq/dm + */ +static void modify_dq_deskew(struct dram_info *dram, u32 signal, u32 dir, + int delta_dif, int delta_sig, u32 rank) +{ + void __iomem *phy_base = dram->phy; + u32 i, j, tmp, offset; + u32 byte_en; + + byte_en = readl(PHY_REG(phy_base, 0xf)) & 0xf; + + if (signal == SKEW_RX_SIGNAL) + offset = 0; + else + offset = 8; + + for (j = offset; j < (offset + rank * 4); j++) { + if (!((byte_en >> (j % 4)) & 1)) + continue; + for (i = 0; i < 0x9; i++) { + if (dir == DESKEW_MDF_ABS_VAL) + tmp = delta_sig; + else + tmp = delta_sig + readl(PHY_REG(phy_base, + dqs_dq_skew_adr[j] + + i)); + writel(tmp, PHY_REG(phy_base, dqs_dq_skew_adr[j] + i)); + } + if (dir == DESKEW_MDF_ABS_VAL) + tmp = delta_dif; + else + tmp = delta_dif + readl(PHY_REG(phy_base, + dqs_dq_skew_adr[j] + 9)); + writel(tmp, PHY_REG(phy_base, dqs_dq_skew_adr[j] + 9)); + writel(tmp, PHY_REG(phy_base, dqs_dq_skew_adr[j] + 0xa)); + } + if (signal == SKEW_RX_SIGNAL) + update_dq_rx_prebit(dram); + else + update_dq_tx_prebit(dram); +} + +static int data_training_rg(struct dram_info *dram, u32 cs, u32 dramtype) +{ + void __iomem *phy_base = dram->phy; + u32 ret; + u32 dis_auto_zq = 0; + u32 odt_val_up, odt_val_dn; + u32 i, j; + + odt_val_dn = readl(PHY_REG(phy_base, 0x110)); + odt_val_up = readl(PHY_REG(phy_base, 0x111)); + + if (dramtype != LPDDR4) { + for (i = 0; i < 4; i++) { + j = 0x110 + i * 0x10; + writel(PHY_DDR4_LPDDR3_RTT_294ohm, + PHY_REG(phy_base, j)); + writel(PHY_DDR4_LPDDR3_RTT_DISABLE, + PHY_REG(phy_base, j + 0x1)); + } + } + dis_auto_zq = pctl_dis_zqcs_aref(dram->pctl); + /* use normal read mode for data training */ + clrbits_le32(PHY_REG(phy_base, 0xc), BIT(1)); + + if (dramtype == DDR4) + setbits_le32(PHY_REG(phy_base, 0xc), BIT(1)); + + /* choose training cs */ + clrsetbits_le32(PHY_REG(phy_base, 2), 0x33, (0x20 >> cs)); + /* enable gate training */ + clrsetbits_le32(PHY_REG(phy_base, 2), 0x33, (0x20 >> cs) | 1); + udelay(50); + ret = readl(PHY_REG(phy_base, 0x91)); + /* disable gate training */ + clrsetbits_le32(PHY_REG(phy_base, 2), 0x33, (0x20 >> cs) | 0); + clrbits_le32(PHY_REG(phy_base, 2), 0x30); + pctl_rest_zqcs_aref(dram->pctl, dis_auto_zq); + + ret = (ret & 0x2f) ^ (readl(PHY_REG(phy_base, 0xf)) & 0xf); + + if (dramtype != LPDDR4) { + for (i = 0; i < 4; i++) { + j = 0x110 + i * 0x10; + writel(odt_val_dn, PHY_REG(phy_base, j)); + writel(odt_val_up, PHY_REG(phy_base, j + 0x1)); + } + } + return ret; +} + +static int data_training_wl(struct dram_info *dram, u32 cs, u32 dramtype, + u32 rank) +{ + void __iomem *pctl_base = dram->pctl; + void __iomem *phy_base = dram->phy; + u32 dis_auto_zq = 0; + u32 tmp; + u32 cur_fsp; + u32 timeout_us = 1000; + + dis_auto_zq = pctl_dis_zqcs_aref(dram->pctl); + + clrbits_le32(PHY_REG(phy_base, 0x7a), 0x1); + + cur_fsp = readl(pctl_base + DDR_PCTL2_MSTR2) & 0x3; + tmp = readl(pctl_base + UMCTL2_REGS_FREQ(cur_fsp) + DDR_PCTL2_INIT3) & + 0xffff; + writel(tmp & 0xff, PHY_REG(phy_base, 0x3)); + + /* disable another cs's output */ + if ((dramtype == DDR3 || dramtype == DDR4) && rank == 2) + pctl_write_mr(dram->pctl, (cs + 1) & 1, 1, tmp | (1 << 12), + dramtype); + if (dramtype == DDR3 || dramtype == DDR4) + writel(0x40 | ((tmp >> 8) & 0x3f), PHY_REG(phy_base, 0x4)); + else + writel(0x80 | ((tmp >> 8) & 0x3f), PHY_REG(phy_base, 0x4)); + + /* choose cs */ + clrsetbits_le32(PHY_REG(phy_base, 2), (0x3 << 6) | (0x3 << 2), + ((0x2 >> cs) << 6) | (0 << 2)); + /* enable write leveling */ + clrsetbits_le32(PHY_REG(phy_base, 2), (0x3 << 6) | (0x3 << 2), + ((0x2 >> cs) << 6) | (1 << 2)); + + while (1) { + if ((readl(PHY_REG(phy_base, 0x92)) & 0xf) == + (readl(PHY_REG(phy_base, 0xf)) & 0xf)) + break; + + udelay(1); + if (timeout_us-- == 0) { + printascii("error: write leveling timeout\n"); + while (1) + ; + } + } + + /* disable write leveling */ + clrsetbits_le32(PHY_REG(phy_base, 2), (0x3 << 6) | (0x3 << 2), + ((0x2 >> cs) << 6) | (0 << 2)); + clrsetbits_le32(PHY_REG(phy_base, 2), 0x3 << 6, 0 << 6); + + /* enable another cs's output */ + if ((dramtype == DDR3 || dramtype == DDR4) && rank == 2) + pctl_write_mr(dram->pctl, (cs + 1) & 1, 1, tmp & ~(1 << 12), + dramtype); + + pctl_rest_zqcs_aref(dram->pctl, dis_auto_zq); + + return 0; +} + +char pattern[32] = { + 0xaa, 0x55, 0xaa, 0x55, 0x55, 0xaa, 0x55, 0xaa, + 0x55, 0xaa, 0x55, 0xaa, 0xaa, 0x55, 0xaa, 0x55, + 0x55, 0x55, 0xaa, 0xaa, 0xaa, 0xaa, 0x55, 0x55, + 0xaa, 0xaa, 0x55, 0x55, 0x55, 0x55, 0xaa, 0xaa +}; + +static int data_training_rd(struct dram_info *dram, u32 cs, u32 dramtype, + u32 mhz) +{ + void __iomem *pctl_base = dram->pctl; + void __iomem *phy_base = dram->phy; + u32 trefi_1x, trfc_1x; + u32 dis_auto_zq = 0; + u32 timeout_us = 1000; + u32 dqs_default; + u32 cur_fsp; + u32 vref_inner; + u32 i; + struct sdram_head_info_index_v2 *index = + (struct sdram_head_info_index_v2 *)common_info; + struct dq_map_info *map_info; + + vref_inner = readl(PHY_REG(phy_base, 0x128)) & 0xff; + if (dramtype == DDR3 && vref_inner == 0x80) { + for (i = 0; i < 4; i++) + writel(vref_inner - 0xa, + PHY_REG(phy_base, 0x118 + i * 0x10)); + + /* reg_rx_vref_value_update */ + setbits_le32(PHY_REG(phy_base, 0x71), 1 << 5); + clrbits_le32(PHY_REG(phy_base, 0x71), 1 << 5); + } + + map_info = (struct dq_map_info *)((void *)common_info + + index->dq_map_index.offset * 4); + /* only 1cs a time, 0:cs0 1 cs1 */ + if (cs > 1) + return -1; + + dqs_default = 0xf; + dis_auto_zq = pctl_dis_zqcs_aref(dram->pctl); + + cur_fsp = readl(pctl_base + DDR_PCTL2_MSTR2) & 0x3; + /* config refresh timing */ + trefi_1x = ((readl(pctl_base + UMCTL2_REGS_FREQ(cur_fsp) + + DDR_PCTL2_RFSHTMG) >> 16) & 0xfff) * 32; + trfc_1x = readl(pctl_base + UMCTL2_REGS_FREQ(cur_fsp) + + DDR_PCTL2_RFSHTMG) & 0x3ff; + /* reg_phy_trefi[7:0] and reg_phy_trefi[13:8] */ + clrsetbits_le32(PHY_REG(phy_base, 0x6e), 0xff, trefi_1x & 0xff); + clrsetbits_le32(PHY_REG(phy_base, 0x6f), 0x3f, (trefi_1x >> 8) & 0x3f); + /* reg_phy_trfc */ + clrsetbits_le32(PHY_REG(phy_base, 0x57), 0xff, trfc_1x); + /* reg_max_refi_cnt */ + clrsetbits_le32(PHY_REG(phy_base, 0x61), 0xf << 4, 0x8 << 4); + + /* choose training cs */ + clrsetbits_le32(PHY_REG(phy_base, 0x71), 0x3 << 6, (0x2 >> cs) << 6); + + /* set dq map for ddr4 */ + if (dramtype == DDR4) { + setbits_le32(PHY_REG(phy_base, 0x70), BIT(7)); + for (i = 0; i < 4; i++) { + writel((map_info->ddr4_dq_map[cs * 2] >> + ((i % 4) * 8)) & 0xff, + PHY_REG(phy_base, 0x238 + i)); + writel((map_info->ddr4_dq_map[cs * 2 + 1] >> + ((i % 4) * 8)) & 0xff, + PHY_REG(phy_base, 0x2b8 + i)); + } + } + + /* cha_l reg_l_rd_train_dqs_default[5:0] */ + clrsetbits_le32(PHY_REG(phy_base, 0x230), 0x3f, dqs_default); + /* cha_h reg_h_rd_train_dqs_default[5:0] */ + clrsetbits_le32(PHY_REG(phy_base, 0x234), 0x3f, dqs_default); + /* chb_l reg_l_rd_train_dqs_default[5:0] */ + clrsetbits_le32(PHY_REG(phy_base, 0x2b0), 0x3f, dqs_default); + /* chb_h reg_h_rd_train_dqs_default[5:0] */ + clrsetbits_le32(PHY_REG(phy_base, 0x2b4), 0x3f, dqs_default); + + /* Choose the read train auto mode */ + clrsetbits_le32(PHY_REG(phy_base, 0x70), 0x3, 0x1); + /* Enable the auto train of the read train */ + clrsetbits_le32(PHY_REG(phy_base, 0x70), 0x3, 0x3); + + /* Wait the train done. */ + while (1) { + if ((readl(PHY_REG(phy_base, 0x93)) >> 7) & 0x1) + break; + + udelay(1); + if (timeout_us-- == 0) { + printascii("error: read training timeout\n"); + return -1; + } + } + + /* Check the read train state */ + if ((readl(PHY_REG(phy_base, 0x240)) & 0x3) || + (readl(PHY_REG(phy_base, 0x2c0)) & 0x3)) { + printascii("error: read training error\n"); + return -1; + } + + /* Exit the Read Training by setting */ + clrbits_le32(PHY_REG(phy_base, 0x70), BIT(1)); + + pctl_rest_zqcs_aref(dram->pctl, dis_auto_zq); + + if (dramtype == DDR3 && vref_inner == 0x80) { + for (i = 0; i < 4; i++) + writel(vref_inner, + PHY_REG(phy_base, 0x118 + i * 0x10)); + + /* reg_rx_vref_value_update */ + setbits_le32(PHY_REG(phy_base, 0x71), 1 << 5); + clrbits_le32(PHY_REG(phy_base, 0x71), 1 << 5); + } + + return 0; +} + +static int data_training_wr(struct dram_info *dram, u32 cs, u32 dramtype, + u32 mhz, u32 dst_fsp) +{ + void __iomem *pctl_base = dram->pctl; + void __iomem *phy_base = dram->phy; + u32 trefi_1x, trfc_1x; + u32 dis_auto_zq = 0; + u32 timeout_us = 1000; + u32 cur_fsp; + u32 mr_tmp, cl, cwl, phy_fsp, offset = 0; + + if (dramtype == LPDDR3 && mhz <= 400) { + phy_fsp = (readl(PHY_REG(phy_base, 0xc)) >> 0x2) & 0x3; + offset = (phy_fsp == 0) ? 0x5 : 0x387 + (phy_fsp - 1) * 3; + cl = readl(PHY_REG(phy_base, offset)); + cwl = readl(PHY_REG(phy_base, offset + 2)); + + clrsetbits_le32(PHY_REG(phy_base, offset), 0x1f, 0x8); + clrsetbits_le32(PHY_REG(phy_base, offset + 2), 0x1f, 0x4); + pctl_write_mr(dram->pctl, 3, 2, 0x6, dramtype); + } + + dis_auto_zq = pctl_dis_zqcs_aref(dram->pctl); + + /* PHY_0x7b[7:0] reg_train_col_addr[7:0] */ + clrsetbits_le32(PHY_REG(phy_base, 0x7b), 0xff, 0x0); + /* PHY_0x7c[4:2] reg_train_ba_addr[2:0] */ + clrsetbits_le32(PHY_REG(phy_base, 0x7c), 0x7 << 2, 0x0 << 2); + /* PHY_0x7c[1:0] reg_train_col_addr[9:8] */ + clrsetbits_le32(PHY_REG(phy_base, 0x7c), 0x3, 0x0); + /* PHY_0x7d[7:0] reg_train_row_addr[7:0] */ + clrsetbits_le32(PHY_REG(phy_base, 0x7d), 0xff, 0x0); + /* PHY_0x7e[7:0] reg_train_row_addr[15:8] */ + clrsetbits_le32(PHY_REG(phy_base, 0x7e), 0xff, 0x0); + + /* PHY_0x71[3] wrtrain_check_data_value_random_gen */ + clrbits_le32(PHY_REG(phy_base, 0x71), BIT(3)); + + /* config refresh timing */ + cur_fsp = readl(pctl_base + DDR_PCTL2_MSTR2) & 0x3; + trefi_1x = ((readl(pctl_base + UMCTL2_REGS_FREQ(cur_fsp) + + DDR_PCTL2_RFSHTMG) >> 16) & 0xfff) * 32; + trfc_1x = readl(pctl_base + UMCTL2_REGS_FREQ(cur_fsp) + + DDR_PCTL2_RFSHTMG) & 0x3ff; + /* reg_phy_trefi[7:0] and reg_phy_trefi[13:8] */ + clrsetbits_le32(PHY_REG(phy_base, 0x6e), 0xff, trefi_1x & 0xff); + clrsetbits_le32(PHY_REG(phy_base, 0x6f), 0x3f, (trefi_1x >> 8) & 0x3f); + /* reg_phy_trfc */ + clrsetbits_le32(PHY_REG(phy_base, 0x57), 0xff, trfc_1x); + /* reg_max_refi_cnt */ + clrsetbits_le32(PHY_REG(phy_base, 0x61), 0xf << 4, 0x8 << 4); + + /* choose training cs */ + clrsetbits_le32(PHY_REG(phy_base, 0x7c), 0x3 << 6, (0x2 >> cs) << 6); + + /* PHY_0x7a [4] reg_wr_train_dqs_default_bypass */ + /* 0: Use the write-leveling value. */ + /* 1: use reg0x233 0x237 0x2b3 0x2b7 */ + setbits_le32(PHY_REG(phy_base, 0x7a), BIT(4)); + + /* PHY_0x7a [0] reg_dq_wr_train_auto */ + setbits_le32(PHY_REG(phy_base, 0x7a), 0x1); + + /* PHY_0x7a [1] reg_dq_wr_train_en */ + setbits_le32(PHY_REG(phy_base, 0x7a), BIT(1)); + + send_a_refresh(dram); + + while (1) { + if ((readl(PHY_REG(phy_base, 0x92)) >> 7) & 0x1) + break; + + udelay(1); + if (timeout_us-- == 0) { + printascii("error: write training timeout\n"); + while (1) + ; + } + } + + /* Check the write train state */ + if ((readl(PHY_REG(phy_base, 0x90)) >> 5) & 0x7) { + printascii("error: write training error\n"); + return -1; + } + + /* PHY_0x7a [1] reg_dq_wr_train_en */ + clrbits_le32(PHY_REG(phy_base, 0x7a), BIT(1)); + + pctl_rest_zqcs_aref(dram->pctl, dis_auto_zq); + + /* save LPDDR4 write vref to fsp_param for dfs */ + if (dramtype == LPDDR4) { + fsp_param[dst_fsp].vref_dq[cs] = + ((readl(PHY_REG(phy_base, 0x384)) & 0x3f) + + (readl(PHY_REG(phy_base, 0x385)) & 0x3f)) / 2; + /* add range info */ + fsp_param[dst_fsp].vref_dq[cs] |= + ((readl(PHY_REG(phy_base, 0x7c)) & BIT(5)) << 1); + } + + if (dramtype == LPDDR3 && mhz <= 400) { + clrsetbits_le32(PHY_REG(phy_base, offset), 0x1f, cl); + clrsetbits_le32(PHY_REG(phy_base, offset + 2), 0x1f, cwl); + mr_tmp = readl(pctl_base + UMCTL2_REGS_FREQ(cur_fsp) + + DDR_PCTL2_INIT3); + pctl_write_mr(dram->pctl, 3, 2, mr_tmp & PCTL2_MR_MASK, + dramtype); + } + + return 0; +} + +static int data_training(struct dram_info *dram, u32 cs, + struct rv1126_sdram_params *sdram_params, u32 dst_fsp, + u32 training_flag) +{ + u32 ret = 0; + + if (training_flag == FULL_TRAINING) + training_flag = READ_GATE_TRAINING | WRITE_LEVELING | + WRITE_TRAINING | READ_TRAINING; + + if ((training_flag & WRITE_LEVELING) == WRITE_LEVELING) { + ret = data_training_wl(dram, cs, + sdram_params->base.dramtype, + sdram_params->ch.cap_info.rank); + if (ret != 0) + goto out; + } + + if ((training_flag & READ_GATE_TRAINING) == READ_GATE_TRAINING) { + ret = data_training_rg(dram, cs, + sdram_params->base.dramtype); + if (ret != 0) + goto out; + } + + if ((training_flag & READ_TRAINING) == READ_TRAINING) { + ret = data_training_rd(dram, cs, + sdram_params->base.dramtype, + sdram_params->base.ddr_freq); + if (ret != 0) + goto out; + } + + if ((training_flag & WRITE_TRAINING) == WRITE_TRAINING) { + ret = data_training_wr(dram, cs, + sdram_params->base.dramtype, + sdram_params->base.ddr_freq, dst_fsp); + if (ret != 0) + goto out; + } + +out: + return ret; +} + +static int get_wrlvl_val(struct dram_info *dram, + struct rv1126_sdram_params *sdram_params) +{ + int i, j, clk_skew; + void __iomem *phy_base = dram->phy; + u32 lp_stat; + int ret; + + lp_stat = low_power_update(dram, 0); + + clk_skew = 0x1f; + modify_ca_deskew(dram, DESKEW_MDF_ABS_VAL, clk_skew, clk_skew, 3, + sdram_params->base.dramtype); + + ret = data_training(dram, 0, sdram_params, 0, WRITE_LEVELING); + if (sdram_params->ch.cap_info.rank == 2) + ret |= data_training(dram, 1, sdram_params, 0, WRITE_LEVELING); + + for (j = 0; j < 2; j++) + for (i = 0; i < 4; i++) + wrlvl_result[j][i] = + (readl(PHY_REG(phy_base, wrlvl_result_offset[j][i])) & 0x3f) - + clk_skew; + + low_power_update(dram, lp_stat); + + return ret; +} + +#if defined(CONFIG_CMD_DDR_TEST_TOOL) +static void init_rw_trn_result_struct(struct rw_trn_result *result, + void __iomem *phy_base, u8 cs_num) +{ + int i; + + result->cs_num = cs_num; + result->byte_en = readb(PHY_REG(dram_info.phy, 0xf)) & + PHY_DQ_WIDTH_MASK; + for (i = 0; i < FSP_NUM; i++) + result->fsp_mhz[i] = 0; +} + +static void save_rw_trn_min_max(void __iomem *phy_base, + struct cs_rw_trn_result *rd_result, + struct cs_rw_trn_result *wr_result, + u8 byte_en) +{ + u16 phy_ofs; + u8 dqs; + u8 dq; + + for (dqs = 0; dqs < BYTE_NUM; dqs++) { + if ((byte_en & BIT(dqs)) == 0) + continue; + + /* Channel A or B (low or high 16 bit) */ + phy_ofs = dqs < 2 ? 0x230 : 0x2b0; + /* low or high 8 bit */ + phy_ofs += (dqs & 0x1) == 0 ? 0 : 0x9; + for (dq = 0; dq < 8; dq++) { + rd_result->dqs[dqs].dq_min[dq] = + readb(PHY_REG(phy_base, phy_ofs + 0x15 + dq)); + rd_result->dqs[dqs].dq_max[dq] = + readb(PHY_REG(phy_base, phy_ofs + 0x27 + dq)); + wr_result->dqs[dqs].dq_min[dq] = + readb(PHY_REG(phy_base, phy_ofs + 0x3d + dq)); + wr_result->dqs[dqs].dq_max[dq] = + readb(PHY_REG(phy_base, phy_ofs + 0x4f + dq)); + } + } +} + +static void save_rw_trn_deskew(void __iomem *phy_base, + struct fsp_rw_trn_result *result, u8 cs_num, + int min_val, bool rw) +{ + u16 phy_ofs; + u8 cs; + u8 dq; + + result->min_val = min_val; + + for (cs = 0; cs < cs_num; cs++) { + phy_ofs = cs == 0 ? 0x170 : 0x1a0; + phy_ofs += rw == SKEW_RX_SIGNAL ? 0x1 : 0x17; + for (dq = 0; dq < 8; dq++) { + result->cs[cs].dqs[0].dq_deskew[dq] = + readb(PHY_REG(phy_base, phy_ofs + dq)); + result->cs[cs].dqs[1].dq_deskew[dq] = + readb(PHY_REG(phy_base, phy_ofs + 0xb + dq)); + result->cs[cs].dqs[2].dq_deskew[dq] = + readb(PHY_REG(phy_base, phy_ofs + 0x60 + dq)); + result->cs[cs].dqs[3].dq_deskew[dq] = + readb(PHY_REG(phy_base, phy_ofs + 0x60 + 0xb + dq)); + } + + result->cs[cs].dqs[0].dqs_deskew = + readb(PHY_REG(phy_base, phy_ofs + 0x8)); + result->cs[cs].dqs[1].dqs_deskew = + readb(PHY_REG(phy_base, phy_ofs + 0xb + 0x8)); + result->cs[cs].dqs[2].dqs_deskew = + readb(PHY_REG(phy_base, phy_ofs + 0x60 + 0x8)); + result->cs[cs].dqs[3].dqs_deskew = + readb(PHY_REG(phy_base, phy_ofs + 0x60 + 0xb + 0x8)); + } +} + +static void save_rw_trn_result_to_ddr(struct rw_trn_result *result) +{ + result->flag = DDR_DQ_EYE_FLAG; + memcpy((void *)(RW_TRN_RESULT_ADDR), result, sizeof(*result)); +} +#endif + +static int high_freq_training(struct dram_info *dram, + struct rv1126_sdram_params *sdram_params, + u32 fsp) +{ + u32 i, j; + void __iomem *phy_base = dram->phy; + u32 dramtype = sdram_params->base.dramtype; + int min_val; + int dqs_skew, clk_skew, ca_skew; + u8 byte_en; + int ret; + + byte_en = readl(PHY_REG(phy_base, 0xf)) & PHY_DQ_WIDTH_MASK; + dqs_skew = 0; + for (j = 0; j < sdram_params->ch.cap_info.rank; j++) { + for (i = 0; i < ARRAY_SIZE(wrlvl_result[0]); i++) { + if ((byte_en & BIT(i)) != 0) + dqs_skew += wrlvl_result[j][i]; + } + } + dqs_skew = dqs_skew / + (int)(sdram_params->ch.cap_info.rank * (1 << sdram_params->ch.cap_info.bw)); + + clk_skew = 0x20 - dqs_skew; + dqs_skew = 0x20; + + if (dramtype == LPDDR4) { + min_val = 0xff; + for (j = 0; j < sdram_params->ch.cap_info.rank; j++) + for (i = 0; i < sdram_params->ch.cap_info.bw; i++) + min_val = MIN(wrlvl_result[j][i], min_val); + + if (min_val < 0) { + clk_skew = -min_val; + ca_skew = -min_val; + } else { + clk_skew = 0; + ca_skew = 0; + } + } else if (dramtype == LPDDR3) { + ca_skew = clk_skew - 4; + } else { + ca_skew = clk_skew; + } + modify_ca_deskew(dram, DESKEW_MDF_ABS_VAL, clk_skew, ca_skew, 3, + dramtype); + + writel(wrlvl_result[0][0] + clk_skew, PHY_REG(phy_base, 0x233)); + writel(wrlvl_result[0][1] + clk_skew, PHY_REG(phy_base, 0x237)); + writel(wrlvl_result[0][2] + clk_skew, PHY_REG(phy_base, 0x2b3)); + writel(wrlvl_result[0][3] + clk_skew, PHY_REG(phy_base, 0x2b7)); + ret = data_training(dram, 0, sdram_params, fsp, READ_GATE_TRAINING | + READ_TRAINING | WRITE_TRAINING); +#if defined(CONFIG_CMD_DDR_TEST_TOOL) + rw_trn_result.fsp_mhz[fsp] = (u16)sdram_params->base.ddr_freq; + save_rw_trn_min_max(phy_base, &rw_trn_result.rd_fsp[fsp].cs[0], + &rw_trn_result.wr_fsp[fsp].cs[0], + rw_trn_result.byte_en); +#endif + if (sdram_params->ch.cap_info.rank == 2) { + writel(wrlvl_result[1][0] + clk_skew, PHY_REG(phy_base, 0x233)); + writel(wrlvl_result[1][1] + clk_skew, PHY_REG(phy_base, 0x237)); + writel(wrlvl_result[1][2] + clk_skew, PHY_REG(phy_base, 0x2b3)); + writel(wrlvl_result[1][3] + clk_skew, PHY_REG(phy_base, 0x2b7)); + ret |= data_training(dram, 1, sdram_params, fsp, + READ_GATE_TRAINING | READ_TRAINING | + WRITE_TRAINING); +#if defined(CONFIG_CMD_DDR_TEST_TOOL) + save_rw_trn_min_max(phy_base, &rw_trn_result.rd_fsp[fsp].cs[1], + &rw_trn_result.wr_fsp[fsp].cs[1], + rw_trn_result.byte_en); +#endif + } + if (ret) + goto out; + + record_dq_prebit(dram); + + min_val = get_min_value(dram, SKEW_RX_SIGNAL, + sdram_params->ch.cap_info.rank) * -1; + modify_dq_deskew(dram, SKEW_RX_SIGNAL, DESKEW_MDF_DIFF_VAL, + min_val, min_val, sdram_params->ch.cap_info.rank); +#if defined(CONFIG_CMD_DDR_TEST_TOOL) + save_rw_trn_deskew(phy_base, &rw_trn_result.rd_fsp[fsp], + rw_trn_result.cs_num, (u8)(min_val * (-1)), + SKEW_RX_SIGNAL); +#endif + + min_val = MIN(get_min_value(dram, SKEW_TX_SIGNAL, + sdram_params->ch.cap_info.rank), + get_min_value(dram, SKEW_CA_SIGNAL, + sdram_params->ch.cap_info.rank)) * -1; + + /* clk = 0, rx all skew -7, tx - min_value */ + modify_ca_deskew(dram, DESKEW_MDF_DIFF_VAL, min_val, min_val, 3, + dramtype); + + modify_dq_deskew(dram, SKEW_TX_SIGNAL, DESKEW_MDF_DIFF_VAL, + min_val, min_val, sdram_params->ch.cap_info.rank); +#if defined(CONFIG_CMD_DDR_TEST_TOOL) + save_rw_trn_deskew(phy_base, &rw_trn_result.wr_fsp[fsp], + rw_trn_result.cs_num, (u8)(min_val * (-1)), + SKEW_TX_SIGNAL); +#endif + + ret = data_training(dram, 0, sdram_params, 0, READ_GATE_TRAINING); + if (sdram_params->ch.cap_info.rank == 2) + ret |= data_training(dram, 1, sdram_params, 0, + READ_GATE_TRAINING); +out: + return ret; +} + +static void set_ddrconfig(struct dram_info *dram, u32 ddrconfig) +{ + writel(ddrconfig, &dram->msch->deviceconf); + clrsetbits_le32(&dram->grf->noc_con0, 0x3 << 0, 0 << 0); +} + +static void update_noc_timing(struct dram_info *dram, + struct rv1126_sdram_params *sdram_params) +{ + void __iomem *pctl_base = dram->pctl; + u32 bw, bl; + + bw = 8 << sdram_params->ch.cap_info.bw; + bl = ((readl(pctl_base + DDR_PCTL2_MSTR) >> 16) & 0xf) * 2; + + /* update the noc timing related to data bus width */ + if ((bw / 8 * bl) <= 16) + sdram_params->ch.noc_timings.ddrmode.b.burstsize = 0; + else if ((bw / 8 * bl) == 32) + sdram_params->ch.noc_timings.ddrmode.b.burstsize = 1; + else if ((bw / 8 * bl) == 64) + sdram_params->ch.noc_timings.ddrmode.b.burstsize = 2; + else + sdram_params->ch.noc_timings.ddrmode.b.burstsize = 3; + + sdram_params->ch.noc_timings.ddrtimingc0.b.burstpenalty = + (bl * bw / 8) > 16 ? (bl / 4) : (16 / (bl * bw / 8)) * bl / 4; + + if (sdram_params->base.dramtype == LPDDR4) { + sdram_params->ch.noc_timings.ddrmode.b.mwrsize = + (bw == 16) ? 0x1 : 0x2; + sdram_params->ch.noc_timings.ddrtimingc0.b.wrtomwr = + 3 * sdram_params->ch.noc_timings.ddrtimingc0.b.burstpenalty; + } + + writel(sdram_params->ch.noc_timings.ddrtiminga0.d32, + &dram->msch->ddrtiminga0); + writel(sdram_params->ch.noc_timings.ddrtimingb0.d32, + &dram->msch->ddrtimingb0); + writel(sdram_params->ch.noc_timings.ddrtimingc0.d32, + &dram->msch->ddrtimingc0); + writel(sdram_params->ch.noc_timings.devtodev0.d32, + &dram->msch->devtodev0); + writel(sdram_params->ch.noc_timings.ddrmode.d32, &dram->msch->ddrmode); + writel(sdram_params->ch.noc_timings.ddr4timing.d32, + &dram->msch->ddr4timing); +} + +static int split_setup(struct dram_info *dram, + struct rv1126_sdram_params *sdram_params) +{ + struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; + u32 dramtype = sdram_params->base.dramtype; + u32 split_size, split_mode; + u64 cs_cap[2], cap; + + cs_cap[0] = sdram_get_cs_cap(cap_info, 0, dramtype); + cs_cap[1] = sdram_get_cs_cap(cap_info, 1, dramtype); + /* only support the larger cap is in low 16bit */ + if (cap_info->cs0_high16bit_row < cap_info->cs0_row) { + cap = cs_cap[0] / (1 << (cap_info->cs0_row - + cap_info->cs0_high16bit_row)); + } else if ((cap_info->cs1_high16bit_row < cap_info->cs1_row) && + (cap_info->rank == 2)) { + if (!cap_info->cs1_high16bit_row) + cap = cs_cap[0]; + else + cap = cs_cap[0] + cs_cap[1] / (1 << (cap_info->cs1_row - + cap_info->cs1_high16bit_row)); + } else { + goto out; + } + split_size = (u32)(cap >> 24) & SPLIT_SIZE_MASK; + if (cap_info->bw == 2) + split_mode = SPLIT_MODE_32_L16_VALID; + else + split_mode = SPLIT_MODE_16_L8_VALID; + + rk_clrsetreg(&dram->ddrgrf->grf_ddrsplit_con, + (SPLIT_MODE_MASK << SPLIT_MODE_OFFSET) | + (SPLIT_BYPASS_MASK << SPLIT_BYPASS_OFFSET) | + (SPLIT_SIZE_MASK << SPLIT_SIZE_OFFSET), + (split_mode << SPLIT_MODE_OFFSET) | + (0x0 << SPLIT_BYPASS_OFFSET) | + (split_size << SPLIT_SIZE_OFFSET)); + + rk_clrsetreg(BUS_SGRF_BASE_ADDR + SGRF_SOC_CON2, + MSCH_AXI_BYPASS_ALL_MASK << MSCH_AXI_BYPASS_ALL_SHIFT, + 0x0 << MSCH_AXI_BYPASS_ALL_SHIFT); + +out: + return 0; +} + +static void split_bypass(struct dram_info *dram) +{ + if ((readl(&dram->ddrgrf->grf_ddrsplit_con) & + (1 << SPLIT_BYPASS_OFFSET)) != 0) + return; + + /* bypass split */ + rk_clrsetreg(&dram->ddrgrf->grf_ddrsplit_con, + (SPLIT_BYPASS_MASK << SPLIT_BYPASS_OFFSET) | + (SPLIT_SIZE_MASK << SPLIT_SIZE_OFFSET), + (0x1 << SPLIT_BYPASS_OFFSET) | + (0x0 << SPLIT_SIZE_OFFSET)); +} + +static void dram_all_config(struct dram_info *dram, + struct rv1126_sdram_params *sdram_params) +{ + struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; + u32 dram_type = sdram_params->base.dramtype; + void __iomem *pctl_base = dram->pctl; + u32 sys_reg2 = 0; + u32 sys_reg3 = 0; + u64 cs_cap[2]; + u32 cs_pst; + + set_ddrconfig(dram, cap_info->ddrconfig); + sdram_org_config(cap_info, &sdram_params->base, &sys_reg2, + &sys_reg3, 0); + writel(sys_reg2, &dram->pmugrf->os_reg[2]); + writel(sys_reg3, &dram->pmugrf->os_reg[3]); + + cs_cap[0] = sdram_get_cs_cap(cap_info, 0, dram_type); + cs_cap[1] = sdram_get_cs_cap(cap_info, 1, dram_type); + + if (cap_info->rank == 2) { + cs_pst = (readl(pctl_base + DDR_PCTL2_ADDRMAP0) & 0x1f) + + 6 + 2; + if (cs_pst > 28) + cs_cap[0] = 1llu << cs_pst; + } + + writel(((((cs_cap[1] >> 20) / 64) & 0xff) << 8) | + (((cs_cap[0] >> 20) / 64) & 0xff), + &dram->msch->devicesize); + update_noc_timing(dram, sdram_params); +} + +static void enable_low_power(struct dram_info *dram, + struct rv1126_sdram_params *sdram_params) +{ + void __iomem *pctl_base = dram->pctl; + u32 grf_lp_con; + + writel(0x1f1f0617, &dram->ddrgrf->ddr_grf_con[1]); + + if (sdram_params->base.dramtype == DDR4) + grf_lp_con = (0x7 << 16) | (1 << 1); + else if (sdram_params->base.dramtype == DDR3) + grf_lp_con = (0x7 << 16) | (1 << 0); + else + grf_lp_con = (0x7 << 16) | (1 << 2); + + /* en lpckdis_en */ + grf_lp_con = grf_lp_con | (0x1 << (9 + 16)) | (0x1 << 9); + writel(grf_lp_con, &dram->ddrgrf->ddr_grf_lp_con); + + /* enable sr, pd */ + if (dram->pd_idle == 0) + clrbits_le32(pctl_base + DDR_PCTL2_PWRCTL, (1 << 1)); + else + setbits_le32(pctl_base + DDR_PCTL2_PWRCTL, (1 << 1)); + if (dram->sr_idle == 0) + clrbits_le32(pctl_base + DDR_PCTL2_PWRCTL, 1); + else + setbits_le32(pctl_base + DDR_PCTL2_PWRCTL, 1); + setbits_le32(pctl_base + DDR_PCTL2_PWRCTL, (1 << 3)); +} + +static void print_ddr_info(struct rv1126_sdram_params *sdram_params) +{ + u32 split; + + if ((readl(DDR_GRF_BASE_ADDR + DDR_GRF_SPLIT_CON) & + (1 << SPLIT_BYPASS_OFFSET)) != 0) + split = 0; + else + split = readl(DDR_GRF_BASE_ADDR + DDR_GRF_SPLIT_CON) & + SPLIT_SIZE_MASK; + + sdram_print_ddr_info(&sdram_params->ch.cap_info, + &sdram_params->base, split); +} + +static int sdram_init_(struct dram_info *dram, + struct rv1126_sdram_params *sdram_params, u32 post_init) +{ + void __iomem *pctl_base = dram->pctl; + void __iomem *phy_base = dram->phy; + u32 ddr4_vref; + u32 mr_tmp; + + rkclk_configure_ddr(dram, sdram_params); + + rkclk_ddr_reset(dram, 1, 1, 1, 1); + udelay(10); + + rkclk_ddr_reset(dram, 1, 1, 1, 0); + phy_cfg(dram, sdram_params); + + rkclk_ddr_reset(dram, 1, 1, 0, 0); + phy_pll_set(dram, sdram_params->base.ddr_freq * MHZ, 1); + + rkclk_ddr_reset(dram, 1, 0, 0, 0); + pctl_cfg(dram->pctl, &sdram_params->pctl_regs, + dram->sr_idle, dram->pd_idle); + + if (sdram_params->ch.cap_info.bw == 2) { + /* 32bit interface use pageclose */ + setbits_le32(pctl_base + DDR_PCTL2_SCHED, 1 << 2); + /* pageclose = 1, pageclose_timer = 0 will err in lp4 328MHz */ + clrsetbits_le32(pctl_base + DDR_PCTL2_SCHED1, 0xff, 0x1 << 0); + } else { + clrbits_le32(pctl_base + DDR_PCTL2_SCHED, 1 << 2); + } + +#ifdef CONFIG_ROCKCHIP_DRAM_EXTENDED_TEMP_SUPPORT + u32 tmp, trefi; + + tmp = readl(pctl_base + DDR_PCTL2_RFSHTMG); + trefi = (tmp >> 16) & 0xfff; + writel((tmp & 0xf000ffff) | (trefi / 2) << 16, + pctl_base + DDR_PCTL2_RFSHTMG); +#endif + + /* set frequency_mode */ + setbits_le32(pctl_base + DDR_PCTL2_MSTR, 0x1 << 29); + /* set target_frequency to Frequency 0 */ + clrsetbits_le32(pctl_base + DDR_PCTL2_MSTR2, 0x3, 0); + + set_ds_odt(dram, sdram_params, 0); + sdram_params->ch.cap_info.ddrconfig = calculate_ddrconfig(sdram_params); + set_ctl_address_map(dram, sdram_params); + + setbits_le32(pctl_base + DDR_PCTL2_DFIMISC, (1 << 5) | (1 << 4)); + + rkclk_ddr_reset(dram, 0, 0, 0, 0); + + while ((readl(pctl_base + DDR_PCTL2_STAT) & 0x7) == 0) + continue; + + if (sdram_params->base.dramtype == LPDDR3) { + pctl_write_mr(dram->pctl, 3, 11, lp3_odt_value, LPDDR3); + } else if (sdram_params->base.dramtype == LPDDR4) { + mr_tmp = readl(pctl_base + DDR_PCTL2_INIT6); + /* MR11 */ + pctl_write_mr(dram->pctl, 3, 11, + mr_tmp >> PCTL2_LPDDR4_MR11_SHIFT & PCTL2_MR_MASK, + LPDDR4); + /* MR12 */ + pctl_write_mr(dram->pctl, 3, 12, + mr_tmp >> PCTL2_LPDDR4_MR12_SHIFT & PCTL2_MR_MASK, + LPDDR4); + + mr_tmp = readl(pctl_base + DDR_PCTL2_INIT7); + /* MR22 */ + pctl_write_mr(dram->pctl, 3, 22, + mr_tmp >> PCTL2_LPDDR4_MR22_SHIFT & PCTL2_MR_MASK, + LPDDR4); + } + + if (data_training(dram, 0, sdram_params, 0, READ_GATE_TRAINING) != 0) { + if (post_init != 0) + printascii("DTT cs0 error\n"); + return -1; + } + + if (sdram_params->base.dramtype == LPDDR4) { + mr_tmp = read_mr(dram, 1, 14, LPDDR4); + + if (mr_tmp != 0x4d) + return -1; + } + + if (sdram_params->base.dramtype == LPDDR4) { + mr_tmp = readl(pctl_base + DDR_PCTL2_INIT7); + /* MR14 */ + pctl_write_mr(dram->pctl, 3, 14, + mr_tmp >> PCTL2_LPDDR4_MR14_SHIFT & PCTL2_MR_MASK, + LPDDR4); + } + if (post_init != 0 && sdram_params->ch.cap_info.rank == 2) { + if (data_training(dram, 1, sdram_params, 0, + READ_GATE_TRAINING) != 0) { + printascii("DTT cs1 error\n"); + return -1; + } + } + + if (sdram_params->base.dramtype == DDR4) { + ddr4_vref = readl(PHY_REG(phy_base, 0x105)) * 39; + pctl_write_vrefdq(dram->pctl, 0x3, ddr4_vref, + sdram_params->base.dramtype); + } + + dram_all_config(dram, sdram_params); + enable_low_power(dram, sdram_params); + + return 0; +} + +static u64 dram_detect_cap(struct dram_info *dram, + struct rv1126_sdram_params *sdram_params, + unsigned char channel) +{ + struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; + void __iomem *pctl_base = dram->pctl; + void __iomem *phy_base = dram->phy; + u32 mr8; + + u32 bktmp; + u32 coltmp; + u32 rowtmp; + u32 cs; + u32 dram_type = sdram_params->base.dramtype; + u32 pwrctl; + u32 i, dq_map; + u32 byte1 = 0, byte0 = 0; + u32 tmp, byte; + struct sdram_head_info_index_v2 *index = (struct sdram_head_info_index_v2 *)common_info; + struct dq_map_info *map_info = (struct dq_map_info *) + ((void *)common_info + index->dq_map_index.offset * 4); + + cap_info->bw = dram_type == DDR3 ? 0 : 1; + if (dram_type != LPDDR4) { + if (dram_type != DDR4) { + coltmp = 12; + bktmp = 3; + if (dram_type == LPDDR2) + rowtmp = 15; + else + rowtmp = 16; + + if (sdram_detect_col(cap_info, coltmp) != 0) + goto cap_err; + + sdram_detect_bank(cap_info, coltmp, bktmp); + if (dram_type != LPDDR3) + sdram_detect_dbw(cap_info, dram_type); + } else { + coltmp = 10; + bktmp = 4; + rowtmp = 17; + + cap_info->col = 10; + cap_info->bk = 2; + sdram_detect_bg(cap_info, coltmp); + } + + if (sdram_detect_row(cap_info, coltmp, bktmp, rowtmp) != 0) + goto cap_err; + + sdram_detect_row_3_4(cap_info, coltmp, bktmp); + } else { + cap_info->col = 10; + cap_info->bk = 3; + mr8 = read_mr(dram, 1, 8, dram_type); + cap_info->dbw = ((mr8 >> 6) & 0x3) == 0 ? 1 : 0; + mr8 = (mr8 >> 2) & 0xf; + if (mr8 >= 0 && mr8 <= 6) { + cap_info->cs0_row = 14 + (mr8 + 1) / 2; + } else if (mr8 == 0xc) { + cap_info->cs0_row = 13; + } else { + printascii("Cap ERR: Fail to get cap of LPDDR4/X from MR8\n"); + goto cap_err; + } + if (cap_info->dbw == 0) + cap_info->cs0_row++; + cap_info->row_3_4 = mr8 % 2 == 1 ? 1 : 0; + if (cap_info->cs0_row >= 17) { + printascii("Cap ERR: "); + printascii("RV1126 LPDDR4/X cannot support row >= 17\n"); + goto cap_err; + // cap_info->cs0_row = 16; + // cap_info->row_3_4 = 0; + } + } + + pwrctl = readl(pctl_base + DDR_PCTL2_PWRCTL); + writel(0, pctl_base + DDR_PCTL2_PWRCTL); + + if (data_training(dram, 1, sdram_params, 0, READ_GATE_TRAINING) == 0) + cs = 1; + else + cs = 0; + cap_info->rank = cs + 1; + + setbits_le32(PHY_REG(phy_base, 0xf), 0xf); + + tmp = data_training_rg(dram, 0, dram_type) & 0xf; + + if (tmp == 0) { + cap_info->bw = 2; + } else { + if (dram_type == DDR3 || dram_type == DDR4) { + dq_map = 0; + byte = 0; + for (i = 0; i < 4; i++) { + if ((tmp & BIT(i)) == 0) { + dq_map |= byte << (i * 2); + byte++; + } + } + cap_info->bw = byte / 2; + for (i = 0; i < 4; i++) { + if ((tmp & BIT(i)) != 0) { + dq_map |= byte << (i * 2); + byte++; + } + } + clrsetbits_le32(&map_info->byte_map[0], 0xff << 24, dq_map << 24); + } else { + dq_map = readl(PHY_REG(phy_base, 0x4f)); + for (i = 0; i < 4; i++) { + if (((dq_map >> (i * 2)) & 0x3) == 0) + byte0 = i; + if (((dq_map >> (i * 2)) & 0x3) == 1) + byte1 = i; + } + clrsetbits_le32(PHY_REG(phy_base, 0xf), PHY_DQ_WIDTH_MASK, + BIT(byte0) | BIT(byte1)); + if (data_training(dram, 0, sdram_params, 0, READ_GATE_TRAINING) == 0) + cap_info->bw = 1; + else + cap_info->bw = 0; + } + } + if (cap_info->bw > 0) + cap_info->dbw = 1; + + writel(pwrctl, pctl_base + DDR_PCTL2_PWRCTL); + + cap_info->cs0_high16bit_row = cap_info->cs0_row; + if (cs) { + cap_info->cs1_row = cap_info->cs0_row; + cap_info->cs1_high16bit_row = cap_info->cs0_row; + } else { + cap_info->cs1_row = 0; + cap_info->cs1_high16bit_row = 0; + } + + if (dram_type == LPDDR3) + sdram_detect_dbw(cap_info, dram_type); + + return 0; +cap_err: + return -1; +} + +static int dram_detect_cs1_row(struct dram_info *dram, + struct rv1126_sdram_params *sdram_params, + unsigned char channel) +{ + struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; + void __iomem *pctl_base = dram->pctl; + u32 ret = 0; + void __iomem *test_addr; + u32 row, bktmp, coltmp, bw; + u64 cs0_cap; + u32 byte_mask; + u32 cs_pst; + u32 cs_add = 0; + u32 max_row; + + if (cap_info->rank == 2) { + cs_pst = (readl(pctl_base + DDR_PCTL2_ADDRMAP0) & 0x1f) + + 6 + 2; + if (cs_pst < 28) + cs_add = 1; + + cs0_cap = 1 << cs_pst; + + if (sdram_params->base.dramtype == DDR4) { + if (cap_info->dbw == 0) + bktmp = cap_info->bk + 2; + else + bktmp = cap_info->bk + 1; + } else { + bktmp = cap_info->bk; + } + bw = cap_info->bw; + coltmp = cap_info->col; + + if (bw == 2) + byte_mask = 0xFFFF; + else + byte_mask = 0xFF; + + max_row = (cs_pst == 31) ? 30 : 31; + + max_row = max_row - bktmp - coltmp - bw - cs_add + 1; + + row = (cap_info->cs0_row > max_row) ? max_row : + cap_info->cs0_row; + + for (; row > 12; row--) { + test_addr = (void __iomem *)(CFG_SYS_SDRAM_BASE + + (u32)cs0_cap + + (1ul << (row + bktmp + coltmp + + cs_add + bw - 1ul))); + + writel(0, CFG_SYS_SDRAM_BASE + (u32)cs0_cap); + writel(PATTERN, test_addr); + + if (((readl(test_addr) & byte_mask) == + (PATTERN & byte_mask)) && + ((readl(CFG_SYS_SDRAM_BASE + (u32)cs0_cap) & + byte_mask) == 0)) { + ret = row; + break; + } + } + } + + return ret; +} + +/* return: 0 = success, other = fail */ +static int sdram_init_detect(struct dram_info *dram, + struct rv1126_sdram_params *sdram_params) +{ + struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; + u32 ret; + u32 sys_reg = 0; + u32 sys_reg3 = 0; + struct sdram_head_info_index_v2 *index = + (struct sdram_head_info_index_v2 *)common_info; + struct dq_map_info *map_info; + + map_info = (struct dq_map_info *)((void *)common_info + + index->dq_map_index.offset * 4); + + if (sdram_init_(dram, sdram_params, 0)) { + if (sdram_params->base.dramtype == DDR3) { + clrsetbits_le32(&map_info->byte_map[0], 0xff << 24, + ((0x1 << 6) | (0x3 << 4) | (0x2 << 2) | + (0x0 << 0)) << 24); + if (sdram_init_(dram, sdram_params, 0)) + return -1; + } else { + return -1; + } + } + + if (sdram_params->base.dramtype == DDR3) { + writel(PATTERN, CFG_SYS_SDRAM_BASE); + if (readl(CFG_SYS_SDRAM_BASE) != PATTERN) + return -1; + } + + split_bypass(dram); + if (dram_detect_cap(dram, sdram_params, 0) != 0) + return -1; + + pctl_remodify_sdram_params(&sdram_params->pctl_regs, cap_info, + sdram_params->base.dramtype); + ret = sdram_init_(dram, sdram_params, 1); + if (ret != 0) + goto out; + + cap_info->cs1_row = + dram_detect_cs1_row(dram, sdram_params, 0); + if (cap_info->cs1_row) { + sys_reg = readl(&dram->pmugrf->os_reg[2]); + sys_reg3 = readl(&dram->pmugrf->os_reg[3]); + SYS_REG_ENC_CS1_ROW(cap_info->cs1_row, + sys_reg, sys_reg3, 0); + writel(sys_reg, &dram->pmugrf->os_reg[2]); + writel(sys_reg3, &dram->pmugrf->os_reg[3]); + } + + sdram_detect_high_row(cap_info); + split_setup(dram, sdram_params); +out: + return ret; +} + +struct rv1126_sdram_params *get_default_sdram_config(u32 freq_mhz) +{ + u32 i; + u32 offset = 0; + struct ddr2_3_4_lp2_3_info *ddr_info; + + if (!freq_mhz) { + ddr_info = get_ddr_drv_odt_info(sdram_configs[0].base.dramtype); + if (ddr_info) + freq_mhz = + (ddr_info->ddr_freq0_1 >> DDR_FREQ_F0_SHIFT) & + DDR_FREQ_MASK; + else + freq_mhz = 0; + } + + for (i = 0; i < ARRAY_SIZE(sdram_configs); i++) { + if (sdram_configs[i].base.ddr_freq == 0 || + freq_mhz < sdram_configs[i].base.ddr_freq) + break; + } + offset = i == 0 ? 0 : i - 1; + + return &sdram_configs[offset]; +} + +static const u16 pctl_need_update_reg[] = { + DDR_PCTL2_RFSHTMG, + DDR_PCTL2_INIT3, + DDR_PCTL2_INIT4, + DDR_PCTL2_INIT6, + DDR_PCTL2_INIT7, + DDR_PCTL2_DRAMTMG0, + DDR_PCTL2_DRAMTMG1, + DDR_PCTL2_DRAMTMG2, + DDR_PCTL2_DRAMTMG3, + DDR_PCTL2_DRAMTMG4, + DDR_PCTL2_DRAMTMG5, + DDR_PCTL2_DRAMTMG6, + DDR_PCTL2_DRAMTMG7, + DDR_PCTL2_DRAMTMG8, + DDR_PCTL2_DRAMTMG9, + DDR_PCTL2_DRAMTMG12, + DDR_PCTL2_DRAMTMG13, + DDR_PCTL2_DRAMTMG14, + DDR_PCTL2_ZQCTL0, + DDR_PCTL2_DFITMG0, + DDR_PCTL2_ODTCFG +}; + +static const u16 phy_need_update_reg[] = { + 0x14, + 0x18, + 0x1c +}; + +static void pre_set_rate(struct dram_info *dram, + struct rv1126_sdram_params *sdram_params, + u32 dst_fsp, u32 dst_fsp_lp4) +{ + u32 i, j, find; + void __iomem *pctl_base = dram->pctl; + void __iomem *phy_base = dram->phy; + u32 phy_offset; + u32 mr_tmp; + u32 dramtype = sdram_params->base.dramtype; + + sw_set_req(dram); + /* pctl timing update */ + for (i = 0, find = 0; i < ARRAY_SIZE(pctl_need_update_reg); i++) { + for (j = find; sdram_params->pctl_regs.pctl[j][0] != 0xFFFFFFFF; + j++) { + if (sdram_params->pctl_regs.pctl[j][0] == + pctl_need_update_reg[i]) { + writel(sdram_params->pctl_regs.pctl[j][1], + pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + + pctl_need_update_reg[i]); + find = j; + break; + } + } + } + +#ifdef CONFIG_ROCKCHIP_DRAM_EXTENDED_TEMP_SUPPORT + u32 tmp, trefi; + + tmp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + DDR_PCTL2_RFSHTMG); + trefi = (tmp >> 16) & 0xfff; + writel((tmp & 0xf000ffff) | (trefi / 2) << 16, + pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + DDR_PCTL2_RFSHTMG); +#endif + + sw_set_ack(dram); + + /* phy timing update */ + if (dst_fsp == 0) + phy_offset = 0; + else + phy_offset = PHY_REG(0, 0x387 - 5 + (dst_fsp - 1) * 3); + /* cl cwl al update */ + for (i = 0, find = 0; i < ARRAY_SIZE(phy_need_update_reg); i++) { + for (j = find; sdram_params->phy_regs.phy[j][0] != 0xFFFFFFFF; + j++) { + if (sdram_params->phy_regs.phy[j][0] == + phy_need_update_reg[i]) { + writel(sdram_params->phy_regs.phy[j][1], + phy_base + phy_offset + + phy_need_update_reg[i]); + find = j; + break; + } + } + } + + set_ds_odt(dram, sdram_params, dst_fsp); + if (dramtype == LPDDR4) { + mr_tmp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + + DDR_PCTL2_INIT4); + /* MR13 */ + pctl_write_mr(dram->pctl, 3, 13, + ((mr_tmp >> PCTL2_LPDDR4_MR13_SHIFT & + PCTL2_MR_MASK) & (~(BIT(7) | BIT(6)))) | + ((0x2 << 6) >> dst_fsp_lp4), dramtype); + writel(((mr_tmp >> PCTL2_LPDDR4_MR13_SHIFT & + PCTL2_MR_MASK) & (~(BIT(7) | BIT(6)))) | + ((0x2 << 6) >> dst_fsp_lp4), + PHY_REG(phy_base, 0x1b)); + /* MR3 */ + pctl_write_mr(dram->pctl, 3, 3, + mr_tmp >> PCTL2_LPDDR234_MR3_SHIFT & + PCTL2_MR_MASK, + dramtype); + writel(mr_tmp >> PCTL2_LPDDR234_MR3_SHIFT & PCTL2_MR_MASK, + PHY_REG(phy_base, 0x19)); + + mr_tmp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + + DDR_PCTL2_INIT3); + /* MR1 */ + pctl_write_mr(dram->pctl, 3, 1, + mr_tmp >> PCTL2_LPDDR234_MR1_SHIFT & + PCTL2_MR_MASK, + dramtype); + writel(mr_tmp >> PCTL2_LPDDR234_MR1_SHIFT & PCTL2_MR_MASK, + PHY_REG(phy_base, 0x17)); + /* MR2 */ + pctl_write_mr(dram->pctl, 3, 2, mr_tmp & PCTL2_MR_MASK, + dramtype); + writel(mr_tmp & PCTL2_MR_MASK, + PHY_REG(phy_base, 0x18)); + + mr_tmp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + + DDR_PCTL2_INIT6); + /* MR11 */ + pctl_write_mr(dram->pctl, 3, 11, + mr_tmp >> PCTL2_LPDDR4_MR11_SHIFT & PCTL2_MR_MASK, + dramtype); + writel(mr_tmp >> PCTL2_LPDDR4_MR11_SHIFT & PCTL2_MR_MASK, + PHY_REG(phy_base, 0x1a)); + /* MR12 */ + pctl_write_mr(dram->pctl, 3, 12, + mr_tmp >> PCTL2_LPDDR4_MR12_SHIFT & PCTL2_MR_MASK, + dramtype); + + mr_tmp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + + DDR_PCTL2_INIT7); + /* MR22 */ + pctl_write_mr(dram->pctl, 3, 22, + mr_tmp >> PCTL2_LPDDR4_MR22_SHIFT & PCTL2_MR_MASK, + dramtype); + writel(mr_tmp >> PCTL2_LPDDR4_MR22_SHIFT & PCTL2_MR_MASK, + PHY_REG(phy_base, 0x1d)); + /* MR14 */ + pctl_write_mr(dram->pctl, 3, 14, + mr_tmp >> PCTL2_LPDDR4_MR14_SHIFT & PCTL2_MR_MASK, + dramtype); + writel(mr_tmp >> PCTL2_LPDDR4_MR14_SHIFT & PCTL2_MR_MASK, + PHY_REG(phy_base, 0x1c)); + } + + update_noc_timing(dram, sdram_params); +} + +static void save_fsp_param(struct dram_info *dram, u32 dst_fsp, + struct rv1126_sdram_params *sdram_params) +{ + void __iomem *pctl_base = dram->pctl; + void __iomem *phy_base = dram->phy; + struct rv1126_fsp_param *p_fsp_param = &fsp_param[dst_fsp]; + u32 temp, temp1; + struct ddr2_3_4_lp2_3_info *ddr_info; + + ddr_info = get_ddr_drv_odt_info(sdram_params->base.dramtype); + + p_fsp_param->freq_mhz = sdram_params->base.ddr_freq; + + if (sdram_params->base.dramtype == LPDDR4) { + p_fsp_param->rd_odt_up_en = 0; + p_fsp_param->rd_odt_down_en = 1; + } else { + p_fsp_param->rd_odt_up_en = + ODT_INFO_PULLUP_EN(ddr_info->odt_info); + p_fsp_param->rd_odt_down_en = + ODT_INFO_PULLDOWN_EN(ddr_info->odt_info); + } + + if (p_fsp_param->rd_odt_up_en) + p_fsp_param->rd_odt = readl(PHY_REG(phy_base, 0x111)); + else if (p_fsp_param->rd_odt_down_en) + p_fsp_param->rd_odt = readl(PHY_REG(phy_base, 0x110)); + else + p_fsp_param->rd_odt = 0; + p_fsp_param->wr_dq_drv = readl(PHY_REG(phy_base, 0x112)); + p_fsp_param->wr_ca_drv = readl(PHY_REG(phy_base, 0x100)); + p_fsp_param->wr_ckcs_drv = readl(PHY_REG(phy_base, 0x102)); + p_fsp_param->vref_inner = readl(PHY_REG(phy_base, 0x128)); + p_fsp_param->vref_out = readl(PHY_REG(phy_base, 0x105)); + + if (sdram_params->base.dramtype == DDR3) { + temp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + + DDR_PCTL2_INIT3); + temp = (temp >> PCTL2_DDR34_MR1_SHIFT) & PCTL2_MR_MASK; + p_fsp_param->ds_pdds = temp & DDR3_DS_MASK; + p_fsp_param->dq_odt = temp & DDR3_RTT_NOM_MASK; + p_fsp_param->ca_odt = p_fsp_param->dq_odt; + } else if (sdram_params->base.dramtype == DDR4) { + temp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + + DDR_PCTL2_INIT3); + temp = (temp >> PCTL2_DDR34_MR1_SHIFT) & PCTL2_MR_MASK; + p_fsp_param->ds_pdds = temp & DDR4_DS_MASK; + p_fsp_param->dq_odt = temp & DDR4_RTT_NOM_MASK; + p_fsp_param->ca_odt = p_fsp_param->dq_odt; + } else if (sdram_params->base.dramtype == LPDDR3) { + temp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + + DDR_PCTL2_INIT4); + temp = (temp >> PCTL2_LPDDR234_MR3_SHIFT) & PCTL2_MR_MASK; + p_fsp_param->ds_pdds = temp & 0xf; + + p_fsp_param->dq_odt = lp3_odt_value; + p_fsp_param->ca_odt = p_fsp_param->dq_odt; + } else if (sdram_params->base.dramtype == LPDDR4) { + temp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + + DDR_PCTL2_INIT4); + temp = (temp >> PCTL2_LPDDR234_MR3_SHIFT) & PCTL2_MR_MASK; + p_fsp_param->ds_pdds = temp & LPDDR4_PDDS_MASK; + + temp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + + DDR_PCTL2_INIT6); + temp = (temp >> PCTL2_LPDDR4_MR11_SHIFT) & PCTL2_MR_MASK; + p_fsp_param->dq_odt = temp & LPDDR4_DQODT_MASK; + p_fsp_param->ca_odt = temp & LPDDR4_CAODT_MASK; + + temp = MAX(readl(PHY_REG(phy_base, 0x3ae)), + readl(PHY_REG(phy_base, 0x3ce))); + temp1 = MIN(readl(PHY_REG(phy_base, 0x3be)), + readl(PHY_REG(phy_base, 0x3de))); + p_fsp_param->vref_ca[0] = (temp + temp1) / 2; + temp = MAX(readl(PHY_REG(phy_base, 0x3af)), + readl(PHY_REG(phy_base, 0x3cf))); + temp1 = MIN(readl(PHY_REG(phy_base, 0x3bf)), + readl(PHY_REG(phy_base, 0x3df))); + p_fsp_param->vref_ca[1] = (temp + temp1) / 2; + p_fsp_param->vref_ca[0] |= + (readl(PHY_REG(phy_base, 0x1e)) & BIT(6)); + p_fsp_param->vref_ca[1] |= + (readl(PHY_REG(phy_base, 0x1e)) & BIT(6)); + + p_fsp_param->lp4_drv_pd_en = (readl(PHY_REG(phy_base, 0x114)) >> + 3) & 0x1; + } + + p_fsp_param->noc_timings.ddrtiminga0 = + sdram_params->ch.noc_timings.ddrtiminga0; + p_fsp_param->noc_timings.ddrtimingb0 = + sdram_params->ch.noc_timings.ddrtimingb0; + p_fsp_param->noc_timings.ddrtimingc0 = + sdram_params->ch.noc_timings.ddrtimingc0; + p_fsp_param->noc_timings.devtodev0 = + sdram_params->ch.noc_timings.devtodev0; + p_fsp_param->noc_timings.ddrmode = + sdram_params->ch.noc_timings.ddrmode; + p_fsp_param->noc_timings.ddr4timing = + sdram_params->ch.noc_timings.ddr4timing; + p_fsp_param->noc_timings.agingx0 = + sdram_params->ch.noc_timings.agingx0; + p_fsp_param->noc_timings.aging0 = + sdram_params->ch.noc_timings.aging0; + p_fsp_param->noc_timings.aging1 = + sdram_params->ch.noc_timings.aging1; + p_fsp_param->noc_timings.aging2 = + sdram_params->ch.noc_timings.aging2; + p_fsp_param->noc_timings.aging3 = + sdram_params->ch.noc_timings.aging3; + + p_fsp_param->flag = FSP_FLAG; +} + +static void copy_fsp_param_to_ddr(void) +{ + memcpy((void *)FSP_PARAM_STORE_ADDR, (void *)&fsp_param, + sizeof(fsp_param)); +} + +static void pctl_modify_trfc(struct ddr_pctl_regs *pctl_regs, + struct sdram_cap_info *cap_info, u32 dram_type, + u32 freq) +{ + u64 cs0_cap; + u32 die_cap; + u32 trfc_ns, trfc4_ns; + u32 trfc, txsnr; + u32 txs_abort_fast = 0; + u32 tmp; + + cs0_cap = sdram_get_cs_cap(cap_info, 0, dram_type); + die_cap = (u32)(cs0_cap >> (20 + (cap_info->bw - cap_info->dbw))); + + switch (dram_type) { + case DDR3: + if (die_cap <= DIE_CAP_512MBIT) + trfc_ns = 90; + else if (die_cap <= DIE_CAP_1GBIT) + trfc_ns = 110; + else if (die_cap <= DIE_CAP_2GBIT) + trfc_ns = 160; + else if (die_cap <= DIE_CAP_4GBIT) + trfc_ns = 260; + else + trfc_ns = 350; + txsnr = MAX(5, ((trfc_ns + 10) * freq + 999) / 1000); + break; + + case DDR4: + if (die_cap <= DIE_CAP_2GBIT) { + trfc_ns = 160; + trfc4_ns = 90; + } else if (die_cap <= DIE_CAP_4GBIT) { + trfc_ns = 260; + trfc4_ns = 110; + } else if (die_cap <= DIE_CAP_8GBIT) { + trfc_ns = 350; + trfc4_ns = 160; + } else { + trfc_ns = 550; + trfc4_ns = 260; + } + txsnr = ((trfc_ns + 10) * freq + 999) / 1000; + txs_abort_fast = ((trfc4_ns + 10) * freq + 999) / 1000; + break; + + case LPDDR3: + if (die_cap <= DIE_CAP_4GBIT) + trfc_ns = 130; + else + trfc_ns = 210; + txsnr = MAX(2, ((trfc_ns + 10) * freq + 999) / 1000); + break; + + case LPDDR4: + if (die_cap <= DIE_CAP_2GBIT) + trfc_ns = 130; + else if (die_cap <= DIE_CAP_4GBIT) + trfc_ns = 180; + else if (die_cap <= DIE_CAP_8GBIT) + trfc_ns = 280; + else + trfc_ns = 380; + txsnr = MAX(2, ((trfc_ns + 10) * freq + 999) / 1000); + break; + + default: + return; + } + trfc = (trfc_ns * freq + 999) / 1000; + + for (int i = 0; pctl_regs->pctl[i][0] != 0xffffffff; i++) { + switch (pctl_regs->pctl[i][0]) { + case DDR_PCTL2_RFSHTMG: + tmp = pctl_regs->pctl[i][1]; + /* t_rfc_min */ + tmp &= ~((u32)0x3ff); + tmp |= ((trfc + 1) / 2) & 0x3ff; + pctl_regs->pctl[i][1] = tmp; + break; + + case DDR_PCTL2_DRAMTMG8: + if (dram_type == DDR3 || dram_type == DDR4) { + tmp = pctl_regs->pctl[i][1]; + /* t_xs_x32 */ + tmp &= ~((u32)0x7f); + tmp |= ((txsnr + 63) / 64) & 0x7f; + + if (dram_type == DDR4) { + /* t_xs_abort_x32 */ + tmp &= ~((u32)(0x7f << 16)); + tmp |= (((txs_abort_fast + 63) / 64) & 0x7f) << 16; + /* t_xs_fast_x32 */ + tmp &= ~((u32)(0x7f << 24)); + tmp |= (((txs_abort_fast + 63) / 64) & 0x7f) << 24; + } + + pctl_regs->pctl[i][1] = tmp; + } + break; + + case DDR_PCTL2_DRAMTMG14: + if (dram_type == LPDDR3 || + dram_type == LPDDR4) { + tmp = pctl_regs->pctl[i][1]; + /* t_xsr */ + tmp &= ~((u32)0xfff); + tmp |= ((txsnr + 1) / 2) & 0xfff; + pctl_regs->pctl[i][1] = tmp; + } + break; + + default: + break; + } + } +} + +void ddr_set_rate(struct dram_info *dram, + struct rv1126_sdram_params *sdram_params, + u32 freq, u32 cur_freq, u32 dst_fsp, + u32 dst_fsp_lp4, u32 training_en) +{ + u32 dest_dll_off, cur_init3, dst_init3, cur_fsp, cur_dll_off; + u32 mr_tmp; + u32 lp_stat; + u32 dramtype = sdram_params->base.dramtype; + struct rv1126_sdram_params *sdram_params_new; + void __iomem *pctl_base = dram->pctl; + void __iomem *phy_base = dram->phy; + + lp_stat = low_power_update(dram, 0); + sdram_params_new = get_default_sdram_config(freq); + sdram_params_new->ch.cap_info.rank = sdram_params->ch.cap_info.rank; + sdram_params_new->ch.cap_info.bw = sdram_params->ch.cap_info.bw; + + pctl_modify_trfc(&sdram_params_new->pctl_regs, + &sdram_params->ch.cap_info, dramtype, freq); + pre_set_rate(dram, sdram_params_new, dst_fsp, dst_fsp_lp4); + + while ((readl(pctl_base + DDR_PCTL2_STAT) & + PCTL2_OPERATING_MODE_MASK) == + PCTL2_OPERATING_MODE_SR) + continue; + + dest_dll_off = 0; + dst_init3 = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + + DDR_PCTL2_INIT3); + if ((dramtype == DDR3 && (dst_init3 & 1)) || + (dramtype == DDR4 && !(dst_init3 & 1))) + dest_dll_off = 1; + + cur_fsp = readl(pctl_base + DDR_PCTL2_MSTR2) & 0x3; + cur_init3 = readl(pctl_base + UMCTL2_REGS_FREQ(cur_fsp) + + DDR_PCTL2_INIT3); + cur_init3 &= PCTL2_MR_MASK; + cur_dll_off = 1; + if ((dramtype == DDR3 && !(cur_init3 & 1)) || + (dramtype == DDR4 && (cur_init3 & 1))) + cur_dll_off = 0; + + if (!cur_dll_off) { + if (dramtype == DDR3) + cur_init3 |= 1; + else + cur_init3 &= ~1; + pctl_write_mr(dram->pctl, 2, 1, cur_init3, dramtype); + } + + setbits_le32(pctl_base + DDR_PCTL2_RFSHCTL3, + PCTL2_DIS_AUTO_REFRESH); + update_refresh_reg(dram); + + enter_sr(dram, 1); + + writel(PMUGRF_CON_DDRPHY_BUFFEREN_MASK | + PMUGRF_CON_DDRPHY_BUFFEREN_EN, + &dram->pmugrf->soc_con[0]); + sw_set_req(dram); + clrbits_le32(pctl_base + DDR_PCTL2_DFIMISC, + PCTL2_DFI_INIT_COMPLETE_EN); + sw_set_ack(dram); + + sw_set_req(dram); + if ((dramtype == DDR3 || dramtype == DDR4) && dest_dll_off) + setbits_le32(pctl_base + DDR_PCTL2_MSTR, PCTL2_DLL_OFF_MODE); + else + clrbits_le32(pctl_base + DDR_PCTL2_MSTR, PCTL2_DLL_OFF_MODE); + + setbits_le32(pctl_base + UMCTL2_REGS_FREQ(cur_fsp) + DDR_PCTL2_ZQCTL0, + PCTL2_DIS_SRX_ZQCL); + setbits_le32(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + DDR_PCTL2_ZQCTL0, + PCTL2_DIS_SRX_ZQCL); + sw_set_ack(dram); + + writel(DDR_MSCH_EN_MASK | (0x1 << DDR_MSCH_EN_SHIFT), + &dram->cru->clkgate_con[21]); + writel(CLK_DDR_UPCTL_EN_MASK | ACLK_DDR_UPCTL_EN_MASK | + (0x1 << CLK_DDR_UPCTL_EN_SHIFT) | + (0x1 << ACLK_DDR_UPCTL_EN_SHIFT), + BUS_SGRF_BASE_ADDR + SGRF_SOC_CON12); + + clrbits_le32(PHY_REG(phy_base, 0), ANALOG_DERESET | DIGITAL_DERESET); + rkclk_set_dpll(dram, freq * MHz / 2); + phy_pll_set(dram, freq * MHz, 0); + phy_pll_set(dram, freq * MHz, 1); + setbits_le32(PHY_REG(phy_base, 0), ANALOG_DERESET | DIGITAL_DERESET); + + writel(PMUGRF_CON_DDRPHY_BUFFEREN_MASK | + PMUGRF_CON_DDRPHY_BUFFEREN_DIS, + &dram->pmugrf->soc_con[0]); + writel(DDR_MSCH_EN_MASK | (0x0 << DDR_MSCH_EN_SHIFT), + &dram->cru->clkgate_con[21]); + writel(CLK_DDR_UPCTL_EN_MASK | ACLK_DDR_UPCTL_EN_MASK | + (0x0 << CLK_DDR_UPCTL_EN_SHIFT) | + (0x0 << ACLK_DDR_UPCTL_EN_SHIFT), + BUS_SGRF_BASE_ADDR + SGRF_SOC_CON12); + while ((readl(pctl_base + DDR_PCTL2_DFISTAT) & + PCTL2_DFI_INIT_COMPLETE) != PCTL2_DFI_INIT_COMPLETE) + continue; + + sw_set_req(dram); + setbits_le32(pctl_base + DDR_PCTL2_MSTR, 0x1 << 29); + clrsetbits_le32(pctl_base + DDR_PCTL2_MSTR2, 0x3, dst_fsp); + sw_set_ack(dram); + update_refresh_reg(dram); + clrsetbits_le32(PHY_REG(phy_base, 0xc), 0x3 << 2, dst_fsp << 2); + + enter_sr(dram, 0); + + setbits_le32(PHY_REG(phy_base, 0x71), 1 << 5); + clrbits_le32(PHY_REG(phy_base, 0x71), 1 << 5); + + mr_tmp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + DDR_PCTL2_INIT4); + if (dramtype == LPDDR3) { + pctl_write_mr(dram->pctl, 3, 1, + (dst_init3 >> PCTL2_LPDDR234_MR1_SHIFT) & + PCTL2_MR_MASK, + dramtype); + pctl_write_mr(dram->pctl, 3, 2, dst_init3 & PCTL2_MR_MASK, + dramtype); + pctl_write_mr(dram->pctl, 3, 3, + (mr_tmp >> PCTL2_LPDDR234_MR3_SHIFT) & + PCTL2_MR_MASK, + dramtype); + pctl_write_mr(dram->pctl, 3, 11, lp3_odt_value, dramtype); + } else if ((dramtype == DDR3) || (dramtype == DDR4)) { + pctl_write_mr(dram->pctl, 3, 1, dst_init3 & PCTL2_MR_MASK, + dramtype); + if (!dest_dll_off) { + pctl_write_mr(dram->pctl, 3, 0, + ((dst_init3 >> PCTL2_DDR34_MR0_SHIFT) & + PCTL2_MR_MASK) | DDR3_DLL_RESET, + dramtype); + udelay(2); + } + pctl_write_mr(dram->pctl, 3, 0, + (dst_init3 >> PCTL2_DDR34_MR0_SHIFT & + PCTL2_MR_MASK) & (~DDR3_DLL_RESET), + dramtype); + pctl_write_mr(dram->pctl, 3, 2, + ((mr_tmp >> PCTL2_DDR34_MR2_SHIFT) & + PCTL2_MR_MASK), dramtype); + if (dramtype == DDR4) { + pctl_write_mr(dram->pctl, 3, 3, mr_tmp & PCTL2_MR_MASK, + dramtype); + mr_tmp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + + DDR_PCTL2_INIT6); + pctl_write_mr(dram->pctl, 3, 4, + (mr_tmp >> PCTL2_DDR4_MR4_SHIFT) & + PCTL2_MR_MASK, + dramtype); + pctl_write_mr(dram->pctl, 3, 5, + mr_tmp >> PCTL2_DDR4_MR5_SHIFT & + PCTL2_MR_MASK, + dramtype); + + mr_tmp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + + DDR_PCTL2_INIT7); + pctl_write_mr(dram->pctl, 3, 6, + mr_tmp >> PCTL2_DDR4_MR6_SHIFT & + PCTL2_MR_MASK, + dramtype); + } + } else if (dramtype == LPDDR4) { + pctl_write_mr(dram->pctl, 3, 13, + ((mr_tmp >> PCTL2_LPDDR4_MR13_SHIFT & + PCTL2_MR_MASK) & (~(BIT(7)))) | + dst_fsp_lp4 << 7, dramtype); + } + clrbits_le32(pctl_base + DDR_PCTL2_RFSHCTL3, + PCTL2_DIS_AUTO_REFRESH); + update_refresh_reg(dram); + + /* training */ + high_freq_training(dram, sdram_params_new, dst_fsp); + low_power_update(dram, lp_stat); + + save_fsp_param(dram, dst_fsp, sdram_params_new); +} + +static void ddr_set_rate_for_fsp(struct dram_info *dram, + struct rv1126_sdram_params *sdram_params) +{ + struct ddr2_3_4_lp2_3_info *ddr_info; + u32 f0; + u32 dramtype = sdram_params->base.dramtype; + u32 f1, f2, f3; + + ddr_info = get_ddr_drv_odt_info(dramtype); + if (!ddr_info) + return; + + f0 = (ddr_info->ddr_freq0_1 >> DDR_FREQ_F0_SHIFT) & + DDR_FREQ_MASK; + + memset((void *)FSP_PARAM_STORE_ADDR, 0, sizeof(fsp_param)); + memset((void *)&fsp_param, 0, sizeof(fsp_param)); + + f1 = (ddr_info->ddr_freq0_1 >> DDR_FREQ_F1_SHIFT) & + DDR_FREQ_MASK; + f2 = (ddr_info->ddr_freq2_3 >> DDR_FREQ_F2_SHIFT) & + DDR_FREQ_MASK; + f3 = (ddr_info->ddr_freq2_3 >> DDR_FREQ_F3_SHIFT) & + DDR_FREQ_MASK; + + if (get_wrlvl_val(dram, sdram_params)) + printascii("get wrlvl value fail\n"); + + if (IS_ENABLED(CONFIG_RAM_ROCKCHIP_DEBUG)) { + printascii("change to: "); + printdec(f1); + printascii("MHz\n"); + } + ddr_set_rate(&dram_info, sdram_params, f1, + sdram_params->base.ddr_freq, 1, 1, 1); + + if (IS_ENABLED(CONFIG_RAM_ROCKCHIP_DEBUG)) { + printascii("change to: "); + printdec(f2); + printascii("MHz\n"); + } + ddr_set_rate(&dram_info, sdram_params, f2, f1, 2, 0, 1); + + if (IS_ENABLED(CONFIG_RAM_ROCKCHIP_DEBUG)) { + printascii("change to: "); + printdec(f3); + printascii("MHz\n"); + } + ddr_set_rate(&dram_info, sdram_params, f3, f2, 3, 1, 1); + + if (IS_ENABLED(CONFIG_RAM_ROCKCHIP_DEBUG)) { + printascii("change to: "); + printdec(f0); + printascii("MHz(final freq)\n"); + } + ddr_set_rate(&dram_info, sdram_params, f0, f3, 0, 0, 1); +} + +int get_uart_config(void) +{ + struct sdram_head_info_index_v2 *index = + (struct sdram_head_info_index_v2 *)common_info; + struct global_info *gbl_info; + + gbl_info = (struct global_info *)((void *)common_info + + index->global_index.offset * 4); + + return gbl_info->uart_info; +} + +/* return: 0 = success, other = fail */ +static int rv1126_dmc_init(struct udevice *dev) +{ + struct rv1126_sdram_params *sdram_params; + int ret = 0; + struct sdram_head_info_index_v2 *index = + (struct sdram_head_info_index_v2 *)common_info; + struct global_info *gbl_info; + + dram_info.phy = (void *)DDR_PHY_BASE_ADDR; + dram_info.pctl = (void *)UPCTL2_BASE_ADDR; + dram_info.grf = (void *)GRF_BASE_ADDR; + dram_info.cru = (void *)CRU_BASE_ADDR; + dram_info.msch = (void *)SERVER_MSCH_BASE_ADDR; + dram_info.ddrgrf = (void *)DDR_GRF_BASE_ADDR; + dram_info.pmugrf = (void *)PMU_GRF_BASE_ADDR; + +#ifdef CONFIG_ROCKCHIP_DRAM_EXTENDED_TEMP_SUPPORT + printascii("extended temp support\n"); +#endif + if (index->version_info != 2 || + (index->global_index.size != sizeof(struct global_info) / 4) || + (index->ddr3_index.size != + sizeof(struct ddr2_3_4_lp2_3_info) / 4) || + (index->ddr4_index.size != + sizeof(struct ddr2_3_4_lp2_3_info) / 4) || + (index->lp3_index.size != + sizeof(struct ddr2_3_4_lp2_3_info) / 4) || + (index->lp4_index.size != (sizeof(struct lp4_info) / 4)) || + (index->lp4x_index.size != (sizeof(struct lp4_info) / 4)) || + index->global_index.offset == 0 || + index->ddr3_index.offset == 0 || + index->ddr4_index.offset == 0 || + index->lp3_index.offset == 0 || + index->lp4_index.offset == 0 || + index->lp4x_index.offset == 0) { + printascii("common info error\n"); + goto error; + } + + gbl_info = (struct global_info *)((void *)common_info + + index->global_index.offset * 4); + + dram_info.sr_idle = SR_INFO(gbl_info->sr_pd_info); + dram_info.pd_idle = PD_INFO(gbl_info->sr_pd_info); + + sdram_params = &sdram_configs[0]; + if (sdram_params->base.dramtype == DDR3 || + sdram_params->base.dramtype == DDR4) { + if (DDR_2T_INFO(gbl_info->info_2t)) + sdram_params->pctl_regs.pctl[0][1] |= 0x1 << 10; + else + sdram_params->pctl_regs.pctl[0][1] &= + ~(0x1 << 10); + } + ret = sdram_init_detect(&dram_info, sdram_params); + if (ret) { + sdram_print_dram_type(sdram_params->base.dramtype); + printascii(", "); + printdec(sdram_params->base.ddr_freq); + printascii("MHz\n"); + goto error; + } + print_ddr_info(sdram_params); +#if defined(CONFIG_CMD_DDR_TEST_TOOL) + init_rw_trn_result_struct(&rw_trn_result, dram_info.phy, + (u8)sdram_params->ch.cap_info.rank); +#endif + + ddr_set_rate_for_fsp(&dram_info, sdram_params); + copy_fsp_param_to_ddr(); + +#if defined(CONFIG_CMD_DDR_TEST_TOOL) + save_rw_trn_result_to_ddr(&rw_trn_result); +#endif + + if (IS_ENABLED(CONFIG_RAM_ROCKCHIP_DEBUG)) + printascii("out\n"); + + return ret; +error: + printascii("error\n"); + return (-1); +} + +#endif + +static int rv1126_dmc_probe(struct udevice *dev) +{ +#if defined(CONFIG_TPL_BUILD) || \ + (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD)) + if (rv1126_dmc_init(dev)) + return 0; +#else + struct dram_info *priv = dev_get_priv(dev); + + priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); + debug("%s: grf=%p\n", __func__, priv->pmugrf); + priv->info.base = CFG_SYS_SDRAM_BASE; + priv->info.size = + rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg[2]); +#endif + return 0; +} + +static int rv1126_dmc_get_info(struct udevice *dev, struct ram_info *info) +{ + struct dram_info *priv = dev_get_priv(dev); + + *info = priv->info; + + return 0; +} + +static struct ram_ops rv1126_dmc_ops = { + .get_info = rv1126_dmc_get_info, +}; + +static const struct udevice_id rv1126_dmc_ids[] = { + { .compatible = "rockchip,rv1126-dmc" }, + { } +}; + +U_BOOT_DRIVER(dmc_rv1126) = { + .name = "rockchip_rv1126_dmc", + .id = UCLASS_RAM, + .of_match = rv1126_dmc_ids, + .ops = &rv1126_dmc_ops, + .probe = rv1126_dmc_probe, + .priv_auto = sizeof(struct dram_info), +}; diff --git a/drivers/timer/orion-timer.c b/drivers/timer/orion-timer.c index 810a03d5496..9cab27f2e48 100644 --- a/drivers/timer/orion-timer.c +++ b/drivers/timer/orion-timer.c @@ -25,7 +25,8 @@ struct orion_timer_priv { static bool early_init_done(void *base) { - if (readl(base + TIMER_CTRL) & TIMER0_EN) + if ((readl(base + TIMER_CTRL) & TIMER0_EN) && + (readl(base + TIMER0_RELOAD) == ~0)) return true; return false; } |