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-rw-r--r--drivers/Makefile2
-rw-r--r--drivers/clk/rockchip/clk_rk3328.c4
-rw-r--r--drivers/clk/rockchip/clk_rk3399.c67
-rw-r--r--drivers/crypto/fsl/Kconfig11
-rw-r--r--drivers/crypto/fsl/Makefile2
-rw-r--r--drivers/crypto/fsl/jr.c4
-rw-r--r--drivers/phy/rockchip/phy-rockchip-usbdp.c126
-rw-r--r--drivers/rng/Kconfig7
-rw-r--r--drivers/rng/Makefile2
-rw-r--r--drivers/spi/npcm_pspi.c10
10 files changed, 149 insertions, 86 deletions
diff --git a/drivers/Makefile b/drivers/Makefile
index bf73b7718ce..9195dafd37e 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -126,7 +126,7 @@ obj-$(CONFIG_W1_EEPROM) += w1-eeprom/
obj-$(CONFIG_MACH_PIC32) += ddr/microchip/
obj-$(CONFIG_FUZZ) += fuzz/
obj-$(CONFIG_DM_HWSPINLOCK) += hwspinlock/
-obj-$(CONFIG_DM_RNG) += rng/
+obj-$(CONFIG_$(SPL_TPL_)DM_RNG) += rng/
endif
obj-y += soc/
diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c
index 87075ec7134..314b903eaa0 100644
--- a/drivers/clk/rockchip/clk_rk3328.c
+++ b/drivers/clk/rockchip/clk_rk3328.c
@@ -706,6 +706,9 @@ static ulong rk3328_clk_get_rate(struct clk *clk)
case PCLK_HDMIPHY:
rate = rk3328_hdmiphy_get_clk(priv->cru);
break;
+ case SCLK_USB3OTG_REF:
+ rate = OSC_HZ;
+ break;
default:
return -ENOENT;
}
@@ -780,6 +783,7 @@ static ulong rk3328_clk_set_rate(struct clk *clk, ulong rate)
case PCLK_DDR:
case ACLK_GMAC:
case PCLK_GMAC:
+ case SCLK_USB3OTG_REF:
case SCLK_USB3OTG_SUSPEND:
case USB480M:
return 0;
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index 80f65a237e8..67b2c05ec9e 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -926,6 +926,26 @@ static ulong rk3399_saradc_set_clk(struct rockchip_cru *cru, uint hz)
return rk3399_saradc_get_clk(cru);
}
+static ulong rk3399_pciephy_get_clk(struct rockchip_cru *cru)
+{
+ if (readl(&cru->clksel_con[18]) & BIT(10))
+ return 100 * MHz;
+ else
+ return OSC_HZ;
+}
+
+static ulong rk3399_pciephy_set_clk(struct rockchip_cru *cru, uint hz)
+{
+ if (hz == 100 * MHz)
+ rk_setreg(&cru->clksel_con[18], BIT(10));
+ else if (hz == OSC_HZ)
+ rk_clrreg(&cru->clksel_con[18], BIT(10));
+ else
+ return -EINVAL;
+
+ return rk3399_pciephy_get_clk(cru);
+}
+
static ulong rk3399_clk_get_rate(struct clk *clk)
{
struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
@@ -956,7 +976,9 @@ static ulong rk3399_clk_get_rate(struct clk *clk)
case SCLK_UART1:
case SCLK_UART2:
case SCLK_UART3:
- return 24000000;
+ case SCLK_USB3OTG0_REF:
+ case SCLK_USB3OTG1_REF:
+ return OSC_HZ;
case PCLK_HDMI_CTRL:
break;
case DCLK_VOP0:
@@ -967,10 +989,14 @@ static ulong rk3399_clk_get_rate(struct clk *clk)
case SCLK_SARADC:
rate = rk3399_saradc_get_clk(priv->cru);
break;
+ case SCLK_PCIEPHY_REF:
+ rate = rk3399_pciephy_get_clk(priv->cru);
+ break;
case ACLK_VIO:
case ACLK_HDCP:
case ACLK_GIC_PRE:
case PCLK_DDR:
+ case ACLK_VDU:
break;
case PCLK_ALIVE:
case PCLK_WDT:
@@ -1049,7 +1075,7 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate)
* return 0 to satisfy clk_set_defaults during device probe.
*/
return 0;
- case SCLK_DDRCLK:
+ case SCLK_DDRC:
ret = rk3399_ddr_set_clk(priv->cru, rate);
break;
case PCLK_EFUSE1024NS:
@@ -1057,10 +1083,14 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate)
case SCLK_SARADC:
ret = rk3399_saradc_set_clk(priv->cru, rate);
break;
+ case SCLK_PCIEPHY_REF:
+ ret = rk3399_pciephy_set_clk(priv->cru, rate);
+ break;
case ACLK_VIO:
case ACLK_HDCP:
case ACLK_GIC_PRE:
case PCLK_DDR:
+ case ACLK_VDU:
return 0;
default:
log_debug("Unknown clock %lu\n", clk->id);
@@ -1106,12 +1136,39 @@ static int __maybe_unused rk3399_gmac_set_parent(struct clk *clk,
return -EINVAL;
}
+static int __maybe_unused rk3399_pciephy_set_parent(struct clk *clk,
+ struct clk *parent)
+{
+ struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
+ const char *clock_output_name;
+ int ret;
+
+ if (parent->dev == clk->dev && parent->id == SCLK_PCIEPHY_REF100M) {
+ rk_setreg(&priv->cru->clksel_con[18], BIT(10));
+ return 0;
+ }
+
+ ret = dev_read_string_index(parent->dev, "clock-output-names",
+ parent->id, &clock_output_name);
+ if (ret < 0)
+ return -ENODATA;
+
+ if (!strcmp(clock_output_name, "xin24m")) {
+ rk_clrreg(&priv->cru->clksel_con[18], BIT(10));
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
static int __maybe_unused rk3399_clk_set_parent(struct clk *clk,
struct clk *parent)
{
switch (clk->id) {
case SCLK_RMII_SRC:
return rk3399_gmac_set_parent(clk, parent);
+ case SCLK_PCIEPHY_REF:
+ return rk3399_pciephy_set_parent(clk, parent);
}
debug("%s: unsupported clk %ld\n", __func__, clk->id);
@@ -1202,7 +1259,8 @@ static int rk3399_clk_enable(struct clk *clk)
rk_clrreg(&priv->cru->clkgate_con[13], BIT(7));
break;
case SCLK_PCIEPHY_REF:
- rk_clrreg(&priv->cru->clksel_con[18], BIT(10));
+ if (readl(&priv->cru->clksel_con[18]) & BIT(10))
+ rk_clrreg(&priv->cru->clkgate_con[12], BIT(6));
break;
default:
debug("%s: unsupported clk %ld\n", __func__, clk->id);
@@ -1296,7 +1354,8 @@ static int rk3399_clk_disable(struct clk *clk)
rk_setreg(&priv->cru->clkgate_con[13], BIT(7));
break;
case SCLK_PCIEPHY_REF:
- rk_clrreg(&priv->cru->clksel_con[18], BIT(10));
+ if (readl(&priv->cru->clksel_con[18]) & BIT(10))
+ rk_setreg(&priv->cru->clkgate_con[12], BIT(6));
break;
default:
debug("%s: unsupported clk %ld\n", __func__, clk->id);
diff --git a/drivers/crypto/fsl/Kconfig b/drivers/crypto/fsl/Kconfig
index 294e1c8a44e..9ed56632fcd 100644
--- a/drivers/crypto/fsl/Kconfig
+++ b/drivers/crypto/fsl/Kconfig
@@ -69,7 +69,7 @@ config FSL_CAAM_JR_NTZ_ACCESS
driver is used.
config FSL_CAAM_RNG
- bool "Enable Random Number Generator support"
+ bool "Enable CAAM Random Number Generator support"
depends on DM_RNG
default y
help
@@ -78,10 +78,17 @@ config FSL_CAAM_RNG
using the prediction resistance flag which means the DRGB is
reseeded from the TRNG every time random data is generated.
+config SPL_FSL_CAAM_RNG
+ bool "Enable CAAM Random Number Generator support in SPL"
+ depends on SPL_DM_RNG
+ help
+ This option is an SPL-variant of the FSL_CAAM_RNG option.
+ See the help of FSL_CAAM_RNG for details.
+
endif
config FSL_DCP_RNG
- bool "Enable Random Number Generator support"
+ bool "Enable DCP Random Number Generator support"
depends on DM_RNG
help
Enable support for the hardware based random number generator
diff --git a/drivers/crypto/fsl/Makefile b/drivers/crypto/fsl/Makefile
index 7a2543e16cc..4fbce519a0b 100644
--- a/drivers/crypto/fsl/Makefile
+++ b/drivers/crypto/fsl/Makefile
@@ -6,6 +6,6 @@ obj-y += sec.o
obj-$(CONFIG_FSL_CAAM) += jr.o fsl_hash.o jobdesc.o error.o
obj-$(CONFIG_CMD_BLOB)$(CONFIG_IMX_CAAM_DEK_ENCAP) += fsl_blob.o
obj-$(CONFIG_RSA_FREESCALE_EXP) += fsl_rsa.o
-obj-$(CONFIG_FSL_CAAM_RNG) += rng.o
+obj-$(CONFIG_$(SPL_TPL_)FSL_CAAM_RNG) += rng.o
obj-$(CONFIG_FSL_DCP_RNG) += dcp_rng.o
obj-$(CONFIG_FSL_MFGPROT) += fsl_mfgprot.o
diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c
index 203f1625215..8ae5c434bdb 100644
--- a/drivers/crypto/fsl/jr.c
+++ b/drivers/crypto/fsl/jr.c
@@ -787,7 +787,7 @@ init:
}
#if CONFIG_IS_ENABLED(OF_CONTROL)
if (ofnode_valid(scu_node)) {
- if (IS_ENABLED(CONFIG_DM_RNG)) {
+ if (CONFIG_IS_ENABLED(DM_RNG)) {
ret = device_bind_driver(NULL, "caam-rng", "caam-rng", NULL);
if (ret)
printf("Couldn't bind rng driver (%d)\n", ret);
@@ -810,7 +810,7 @@ init:
return -1;
}
- if (IS_ENABLED(CONFIG_DM_RNG)) {
+ if (CONFIG_IS_ENABLED(DM_RNG)) {
ret = device_bind_driver(NULL, "caam-rng", "caam-rng",
NULL);
if (ret)
diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c b/drivers/phy/rockchip/phy-rockchip-usbdp.c
index baf92529348..18e76402799 100644
--- a/drivers/phy/rockchip/phy-rockchip-usbdp.c
+++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c
@@ -21,7 +21,7 @@
#include <reset.h>
#include <syscon.h>
#include <asm/arch-rockchip/clock.h>
-
+#include <dt-bindings/phy/phy.h>
#include <linux/usb/phy-rockchip-usbdp.h>
#define BIT_WRITEABLE_SHIFT 16
@@ -74,6 +74,8 @@ struct udphy_grf_cfg {
struct rockchip_udphy;
struct rockchip_udphy_cfg {
+ unsigned int num_phys;
+ unsigned int phy_ids[2];
/* resets to be requested */
const char * const *rst_list;
int num_rsts;
@@ -583,10 +585,21 @@ static int udphy_power_off(struct rockchip_udphy *udphy, u8 mode)
return 0;
}
+static int rockchip_u3phy_of_xlate(struct phy *phy,
+ struct ofnode_phandle_args *args)
+{
+ if (args->args_count == 0)
+ return -EINVAL;
+
+ if (args->args[0] != PHY_TYPE_USB3)
+ return -EINVAL;
+
+ return 0;
+}
+
static int rockchip_u3phy_init(struct phy *phy)
{
- struct udevice *parent = phy->dev->parent;
- struct rockchip_udphy *udphy = dev_get_priv(parent);
+ struct rockchip_udphy *udphy = dev_get_priv(phy->dev);
/* DP only or high-speed, disable U3 port */
if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) {
@@ -599,8 +612,7 @@ static int rockchip_u3phy_init(struct phy *phy)
static int rockchip_u3phy_exit(struct phy *phy)
{
- struct udevice *parent = phy->dev->parent;
- struct rockchip_udphy *udphy = dev_get_priv(parent);
+ struct rockchip_udphy *udphy = dev_get_priv(phy->dev);
/* DP only or high-speed */
if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs)
@@ -610,47 +622,32 @@ static int rockchip_u3phy_exit(struct phy *phy)
}
static const struct phy_ops rockchip_u3phy_ops = {
+ .of_xlate = rockchip_u3phy_of_xlate,
.init = rockchip_u3phy_init,
.exit = rockchip_u3phy_exit,
};
-int rockchip_u3phy_uboot_init(void)
-{
- struct udevice *udev;
- struct rockchip_udphy *udphy;
- int ret;
-
- ret = uclass_get_device_by_driver(UCLASS_PHY,
- DM_DRIVER_GET(rockchip_udphy_u3_port),
- &udev);
- if (ret) {
- pr_err("%s: get u3-port failed: %d\n", __func__, ret);
- return ret;
- }
-
- /* DP only or high-speed, disable U3 port */
- udphy = dev_get_priv(udev->parent);
- if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) {
- udphy_u3_port_disable(udphy, true);
- return 0;
- }
-
- return udphy_power_on(udphy, UDPHY_MODE_USB);
-}
-
static int rockchip_udphy_probe(struct udevice *dev)
{
- const struct device_node *np = ofnode_to_np(dev_ofnode(dev));
struct rockchip_udphy *udphy = dev_get_priv(dev);
const struct rockchip_udphy_cfg *phy_cfgs;
+ unsigned int reg;
int id, ret;
udphy->dev = dev;
- id = of_alias_get_id(np, "usbdp");
- if (id < 0)
- id = 0;
- udphy->id = id;
+ ret = ofnode_read_u32_index(dev_ofnode(dev), "reg", 0, &reg);
+ if (ret) {
+ dev_err(dev, "failed to read reg[0] property\n");
+ return ret;
+ }
+ if (reg == 0 && dev_read_addr_cells(dev) == 2) {
+ ret = ofnode_read_u32_index(dev_ofnode(dev), "reg", 1, &reg);
+ if (ret) {
+ dev_err(dev, "failed to read reg[1] property\n");
+ return ret;
+ }
+ }
phy_cfgs = (const struct rockchip_udphy_cfg *)dev_get_driver_data(dev);
if (!phy_cfgs) {
@@ -659,6 +656,20 @@ static int rockchip_udphy_probe(struct udevice *dev)
}
udphy->cfgs = phy_cfgs;
+ /* find the phy-id from the io address */
+ udphy->id = -ENODEV;
+ for (id = 0; id < udphy->cfgs->num_phys; id++) {
+ if (reg == udphy->cfgs->phy_ids[id]) {
+ udphy->id = id;
+ break;
+ }
+ }
+
+ if (udphy->id < 0) {
+ dev_err(dev, "no matching device found\n");
+ return -ENODEV;
+ }
+
ret = regmap_init_mem(dev_ofnode(dev), &udphy->pma_regmap);
if (ret)
return ret;
@@ -671,40 +682,6 @@ static int rockchip_udphy_probe(struct udevice *dev)
return 0;
}
-static int rockchip_udphy_bind(struct udevice *parent)
-{
- struct udevice *child;
- ofnode subnode;
- const char *node_name;
- int ret;
-
- dev_for_each_subnode(subnode, parent) {
- if (!ofnode_valid(subnode)) {
- printf("%s: no subnode for %s", __func__, parent->name);
- return -ENXIO;
- }
-
- node_name = ofnode_get_name(subnode);
- debug("%s: subnode %s\n", __func__, node_name);
-
- /* if there is no match, continue */
- if (strcasecmp(node_name, "usb3-port"))
- continue;
-
- /* node name is usb3-port */
- ret = device_bind_driver_to_node(parent,
- "rockchip_udphy_u3_port",
- node_name, subnode, &child);
- if (ret) {
- printf("%s: '%s' cannot bind its driver\n",
- __func__, node_name);
- return ret;
- }
- }
-
- return 0;
-}
-
static int rk3588_udphy_refclk_set(struct rockchip_udphy *udphy)
{
/* configure phy reference clock */
@@ -838,6 +815,11 @@ static const char * const rk3588_udphy_rst_l[] = {
};
static const struct rockchip_udphy_cfg rk3588_udphy_cfgs = {
+ .num_phys = 2,
+ .phy_ids = {
+ 0xfed80000,
+ 0xfed90000,
+ },
.num_rsts = ARRAY_SIZE(rk3588_udphy_rst_l),
.rst_list = rk3588_udphy_rst_l,
.grfcfg = {
@@ -864,17 +846,11 @@ static const struct udevice_id rockchip_udphy_dt_match[] = {
{ /* sentinel */ }
};
-U_BOOT_DRIVER(rockchip_udphy_u3_port) = {
- .name = "rockchip_udphy_u3_port",
- .id = UCLASS_PHY,
- .ops = &rockchip_u3phy_ops,
-};
-
U_BOOT_DRIVER(rockchip_udphy) = {
.name = "rockchip_udphy",
.id = UCLASS_PHY,
.of_match = rockchip_udphy_dt_match,
.probe = rockchip_udphy_probe,
- .bind = rockchip_udphy_bind,
+ .ops = &rockchip_u3phy_ops,
.priv_auto = sizeof(struct rockchip_udphy),
};
diff --git a/drivers/rng/Kconfig b/drivers/rng/Kconfig
index cd72852a479..5758ae192a6 100644
--- a/drivers/rng/Kconfig
+++ b/drivers/rng/Kconfig
@@ -6,6 +6,13 @@ config DM_RNG
This interface is used to initialise the rng device and to
read the random seed from the device.
+config SPL_DM_RNG
+ bool "Driver support for Random Number Generator devices in SPL"
+ depends on SPL_DM
+ help
+ This option is an SPL-variant of the DM_RNG option.
+ See the help of DM_RNG for details.
+
if DM_RNG
config RNG_MESON
diff --git a/drivers/rng/Makefile b/drivers/rng/Makefile
index ecae1a3da33..c1f1c616e00 100644
--- a/drivers/rng/Makefile
+++ b/drivers/rng/Makefile
@@ -3,7 +3,7 @@
# Copyright (c) 2019, Linaro Limited
#
-obj-$(CONFIG_DM_RNG) += rng-uclass.o
+obj-$(CONFIG_$(SPL_TPL_)DM_RNG) += rng-uclass.o
obj-$(CONFIG_RNG_MESON) += meson-rng.o
obj-$(CONFIG_RNG_SANDBOX) += sandbox_rng.o
obj-$(CONFIG_RNG_MSM) += msm_rng.o
diff --git a/drivers/spi/npcm_pspi.c b/drivers/spi/npcm_pspi.c
index eb14185273e..c9441304f5a 100644
--- a/drivers/spi/npcm_pspi.c
+++ b/drivers/spi/npcm_pspi.c
@@ -7,6 +7,7 @@
#include <dm.h>
#include <spi.h>
#include <clk.h>
+#include <reset.h>
#include <asm/gpio.h>
#include <linux/iopoll.h>
@@ -194,6 +195,7 @@ static int npcm_pspi_probe(struct udevice *bus)
{
struct npcm_pspi_priv *priv = dev_get_priv(bus);
int node = dev_of_offset(bus);
+ struct reset_ctl reset;
int ret;
ret = clk_get_by_index(bus, 0, &priv->clk);
@@ -205,6 +207,14 @@ static int npcm_pspi_probe(struct udevice *bus)
gpio_request_by_name_nodev(offset_to_ofnode(node), "cs-gpios", 0,
&priv->cs_gpio, GPIOD_IS_OUT| GPIOD_ACTIVE_LOW);
+ /* Reset HW */
+ ret = reset_get_by_index(bus, 0, &reset);
+ if (!ret) {
+ reset_assert(&reset);
+ udelay(5);
+ reset_deassert(&reset);
+ }
+
return 0;
}
generated by cgit v1.2.3 (git 2.0.4) at 2025-10-24 22:15:52 +0000