diff options
Diffstat (limited to 'drivers')
32 files changed, 137 insertions, 96 deletions
diff --git a/drivers/clk/mpc83xx_clk.h b/drivers/clk/mpc83xx_clk.h index c06a51ecd43..6b74fc5f16b 100644 --- a/drivers/clk/mpc83xx_clk.h +++ b/drivers/clk/mpc83xx_clk.h @@ -321,7 +321,7 @@ static inline u32 get_pci_sync_in(immap_t *im) } /** - * get_csb_clk() - Read the CSB (Coheren System Bus) clock speed + * get_csb_clk() - Read the CSB (Coherent System Bus) clock speed * @im: Pointer to the MPC83xx main register map in question * * Return: The CSB clock speed value as a 32-bit number. diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index a093027eb0e..12966d02a22 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -5,20 +5,20 @@ config CLK_RENESAS Enable support for clock present on Renesas SoCs. config CLK_RCAR - bool "Renesas RCar clock driver support" + bool "Renesas R-Car clock driver support" help - Enable common code for clocks on Renesas RCar SoCs. + Enable common code for clocks on Renesas R-Car SoCs. config CLK_RCAR_CPG_LIB bool "CPG/MSSR library functions" config CLK_RCAR_GEN2 - bool "Renesas RCar Gen2 clock driver" + bool "Renesas R-Car Gen2 clock driver" def_bool y if RCAR_32 depends on CLK_RENESAS select CLK_RCAR help - Enable this to support the clocks on Renesas RCar Gen2 SoC. + Enable this to support the clocks on Renesas R-Car Gen2 SoC. config CLK_R8A7790 bool "Renesas R8A7790 clock driver" @@ -51,14 +51,14 @@ config CLK_R8A7794 Enable this to support the clocks on Renesas R8A7794 SoC. config CLK_RCAR_GEN3 - bool "Renesas RCar Gen3 and Gen4 clock driver" + bool "Renesas R-Car Gen3 and Gen4 clock driver" def_bool y if RCAR_64 depends on CLK_RENESAS select CLK_RCAR select CLK_RCAR_CPG_LIB select DM_RESET help - Enable this to support the clocks on Renesas RCar Gen3 and Gen4 SoCs. + Enable this to support the clocks on Renesas R-Car Gen3 and Gen4 SoCs. config CLK_R8A774A1 bool "Renesas R8A774A1 clock driver" diff --git a/drivers/clk/renesas/clk-rcar-gen2.c b/drivers/clk/renesas/clk-rcar-gen2.c index 89f2d966746..9b6fce4675c 100644 --- a/drivers/clk/renesas/clk-rcar-gen2.c +++ b/drivers/clk/renesas/clk-rcar-gen2.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Renesas RCar Gen2 CPG MSSR driver + * Renesas R-Car Gen2 CPG MSSR driver * * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com> * diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c index aa38c0f7dd0..375cc4a4930 100644 --- a/drivers/clk/renesas/clk-rcar-gen3.c +++ b/drivers/clk/renesas/clk-rcar-gen3.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Renesas RCar Gen3 CPG MSSR driver + * Renesas R-Car Gen3 CPG MSSR driver * * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com> * diff --git a/drivers/clk/renesas/r8a779h0-cpg-mssr.c b/drivers/clk/renesas/r8a779h0-cpg-mssr.c index 2e98e262fb0..70fa8ff2871 100644 --- a/drivers/clk/renesas/r8a779h0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779h0-cpg-mssr.c @@ -39,7 +39,6 @@ enum clk_ids { CLK_PLL6, CLK_PLL7, CLK_PLL1_DIV2, - CLK_PLL2_DIV2, CLK_PLL3_DIV2, CLK_PLL4_DIV2, CLK_PLL4_DIV5, @@ -82,7 +81,6 @@ static const struct cpg_core_clk r8a779h0_core_clks[] = { DEF_BASE(".pll7", CLK_PLL7, CLK_TYPE_GEN4_PLL7, CLK_MAIN), DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), - DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 2, 1), DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 2, 1), DEF_FIXED(".pll4_div2", CLK_PLL4_DIV2, CLK_PLL4, 2, 1), DEF_FIXED(".pll4_div5", CLK_PLL4_DIV5, CLK_PLL4, 5, 1), @@ -106,10 +104,10 @@ static const struct cpg_core_clk r8a779h0_core_clks[] = { DEF_RATE(".oco", CLK_OCO, 32768), /* Core Clock Outputs */ - DEF_GEN4_Z("zc0", R8A779H0_CLK_ZC0, CLK_TYPE_GEN4_Z, CLK_PLL2_DIV2, 2, 0), - DEF_GEN4_Z("zc1", R8A779H0_CLK_ZC1, CLK_TYPE_GEN4_Z, CLK_PLL2_DIV2, 2, 8), - DEF_GEN4_Z("zc2", R8A779H0_CLK_ZC2, CLK_TYPE_GEN4_Z, CLK_PLL2_DIV2, 2, 32), - DEF_GEN4_Z("zc3", R8A779H0_CLK_ZC3, CLK_TYPE_GEN4_Z, CLK_PLL2_DIV2, 2, 40), + DEF_GEN4_Z("zc0", R8A779H0_CLK_ZC0, CLK_TYPE_GEN4_Z, CLK_PLL2, 4, 0), + DEF_GEN4_Z("zc1", R8A779H0_CLK_ZC1, CLK_TYPE_GEN4_Z, CLK_PLL2, 4, 8), + DEF_GEN4_Z("zc2", R8A779H0_CLK_ZC2, CLK_TYPE_GEN4_Z, CLK_PLL2, 4, 32), + DEF_GEN4_Z("zc3", R8A779H0_CLK_ZC3, CLK_TYPE_GEN4_Z, CLK_PLL2, 4, 40), DEF_FIXED("s0d2", R8A779H0_CLK_S0D2, CLK_S0, 2, 1), DEF_FIXED("s0d3", R8A779H0_CLK_S0D3, CLK_S0, 3, 1), DEF_FIXED("s0d4", R8A779H0_CLK_S0D4, CLK_S0, 4, 1), diff --git a/drivers/clk/renesas/rcar-cpg-lib.c b/drivers/clk/renesas/rcar-cpg-lib.c index 8862fbc7579..ea33bfd3239 100644 --- a/drivers/clk/renesas/rcar-cpg-lib.c +++ b/drivers/clk/renesas/rcar-cpg-lib.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Renesas RCar Gen3 CPG MSSR driver + * Renesas R-Car Gen3 CPG MSSR driver * * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com> * diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c index 35bad7f5f73..39ff4541c1e 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.c +++ b/drivers/clk/renesas/renesas-cpg-mssr.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Renesas RCar Gen3 CPG MSSR driver + * Renesas R-Car Gen3 CPG MSSR driver * * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> * diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h index 71e409f3eb0..d5db14baf06 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.h +++ b/drivers/clk/renesas/renesas-cpg-mssr.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Renesas RCar Gen3 CPG MSSR driver + * Renesas R-Car Gen3 CPG MSSR driver * * Copyright (C) 2017-2018 Marek Vasut <marek.vasut@gmail.com> * diff --git a/drivers/clk/tegra/tegra-car-clk.c b/drivers/clk/tegra/tegra-car-clk.c index 1d61f8dc378..880dd4f6ece 100644 --- a/drivers/clk/tegra/tegra-car-clk.c +++ b/drivers/clk/tegra/tegra-car-clk.c @@ -10,6 +10,9 @@ #include <asm/arch/clock.h> #include <asm/arch-tegra/clk_rst.h> +#define TEGRA_CAR_CLK_PLL BIT(0) +#define TEGRA_CAR_CLK_PERIPH BIT(1) + static int tegra_car_clk_request(struct clk *clk) { debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev, @@ -20,24 +23,41 @@ static int tegra_car_clk_request(struct clk *clk) * varies per SoC) are the peripheral clocks, which use a numbering * scheme that matches HW registers 1:1. There are other clock IDs * beyond this that are assigned arbitrarily by the Tegra CAR DT - * binding. Due to the implementation of this driver, it currently - * only supports the peripheral IDs. + * binding. */ - if (clk->id >= PERIPH_ID_COUNT) - return -EINVAL; + if (clk->id < PERIPH_ID_COUNT) { + clk->data |= TEGRA_CAR_CLK_PERIPH; + return 0; + } - return 0; + /* If check for periph failed, then check for PLL clock id */ + int id = clk_id_to_pll_id(clk->id); + + if (clock_id_is_pll(id)) { + clk->id = id; + clk->data |= TEGRA_CAR_CLK_PLL; + return 0; + } + + return -EINVAL; } static ulong tegra_car_clk_get_rate(struct clk *clk) { - enum clock_id parent; - debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev, clk->id); - parent = clock_get_periph_parent(clk->id); - return clock_get_periph_rate(clk->id, parent); + if (clk->data & TEGRA_CAR_CLK_PLL) + return clock_get_rate(clk->id); + + if (clk->data & TEGRA_CAR_CLK_PERIPH) { + enum clock_id parent; + + parent = clock_get_periph_parent(clk->id); + return clock_get_periph_rate(clk->id, parent); + } + + return -1U; } static ulong tegra_car_clk_set_rate(struct clk *clk, ulong rate) @@ -47,6 +67,9 @@ static ulong tegra_car_clk_set_rate(struct clk *clk, ulong rate) debug("%s(clk=%p, rate=%lu) (dev=%p, id=%lu)\n", __func__, clk, rate, clk->dev, clk->id); + if (clk->data & TEGRA_CAR_CLK_PLL) + return 0; + parent = clock_get_periph_parent(clk->id); return clock_adjust_periph_pll_div(clk->id, parent, rate, NULL); } @@ -56,6 +79,9 @@ static int tegra_car_clk_enable(struct clk *clk) debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev, clk->id); + if (clk->data & TEGRA_CAR_CLK_PLL) + return 0; + clock_enable(clk->id); return 0; @@ -66,6 +92,9 @@ static int tegra_car_clk_disable(struct clk *clk) debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev, clk->id); + if (clk->data & TEGRA_CAR_CLK_PLL) + return 0; + clock_disable(clk->id); return 0; @@ -83,6 +112,9 @@ static int tegra_car_clk_probe(struct udevice *dev) { debug("%s(dev=%p)\n", __func__, dev); + clock_init(); + clock_verify(); + return 0; } diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 92a8597420a..f4a453e1cdd 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -358,10 +358,10 @@ config PCF8575_GPIO chips are from NXP and TI. config RCAR_GPIO - bool "Renesas RCar GPIO driver" + bool "Renesas R-Car GPIO driver" depends on DM_GPIO && ARCH_RENESAS help - This driver supports the GPIO banks on Renesas RCar SoCs. + This driver supports the GPIO banks on Renesas R-Car SoCs. config RZA1_GPIO bool "Renesas RZ/A1 GPIO driver" diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 52067fa7c1f..cdae6825736 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -504,16 +504,16 @@ config SYS_I2C_OMAP24XX Add support for the OMAP2+ I2C driver. config SYS_I2C_RCAR_I2C - bool "Renesas RCar I2C driver" + bool "Renesas R-Car I2C driver" depends on (RCAR_GEN2 || RCAR_64) && DM_I2C help - Support for Renesas RCar I2C controller. + Support for Renesas R-Car I2C controller. config SYS_I2C_RCAR_IIC - bool "Renesas RCar Gen3 IIC driver" + bool "Renesas R-Car Gen3 IIC driver" depends on (RCAR_GEN2 || RCAR_GEN3) && DM_I2C help - Support for Renesas RCar Gen3 IIC controller. + Support for Renesas R-Car Gen3 IIC controller. config SYS_I2C_ROCKCHIP bool "Rockchip I2C driver" diff --git a/drivers/i2c/rcar_iic.c b/drivers/i2c/rcar_iic.c index 2aa0f5fbfae..e019d06be41 100644 --- a/drivers/i2c/rcar_iic.c +++ b/drivers/i2c/rcar_iic.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Renesas RCar IIC driver + * Renesas R-Car IIC driver * * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com> * diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index efe98354a0f..799586891af 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -750,7 +750,7 @@ static int mmc_send_op_cond(struct mmc *mmc) { int err, i; int timeout = 1000; - uint start; + ulong start; /* Some cards seem to need this */ mmc_go_idle(mmc); @@ -844,7 +844,8 @@ int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd) static int __mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value, bool send_status) { - unsigned int status, start; + ulong start; + unsigned int status; struct mmc_cmd cmd; int timeout_ms = DEFAULT_CMD6_TIMEOUT_MS; bool is_part_switch = (set == EXT_CSD_CMD_SET_NORMAL) && diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c index 92afa6adcda..556f07eaf8f 100644 --- a/drivers/mmc/renesas-sdhi.c +++ b/drivers/mmc/renesas-sdhi.c @@ -571,7 +571,7 @@ int renesas_sdhi_execute_tuning(struct udevice *dev, uint opcode) int i, ret = 0, sret; u32 caps, reg; - /* Only supported on Renesas RCar */ + /* Only supported on Renesas R-Car */ if (!(priv->caps & TMIO_SD_CAP_RCAR_UHS)) return -EINVAL; diff --git a/drivers/mmc/tmio-common.h b/drivers/mmc/tmio-common.h index f489fb70766..657aba75148 100644 --- a/drivers/mmc/tmio-common.h +++ b/drivers/mmc/tmio-common.h @@ -64,7 +64,7 @@ #define TMIO_SD_CLKCTL_DIV4 BIT(0) /* SDCLK = CLK / 4 */ #define TMIO_SD_CLKCTL_DIV2 0 /* SDCLK = CLK / 2 */ #define TMIO_SD_CLKCTL_DIV1 BIT(10) /* SDCLK = CLK */ -#define TMIO_SD_CLKCTL_RCAR_DIV1 0xff /* SDCLK = CLK (RCar ver.) */ +#define TMIO_SD_CLKCTL_RCAR_DIV1 0xff /* SDCLK = CLK (R-Car ver.) */ #define TMIO_SD_CLKCTL_OFFEN BIT(9) /* stop SDCLK when unused */ #define TMIO_SD_CLKCTL_SCLKEN BIT(8) /* SDCLK output enable */ #define TMIO_SD_SIZE 0x04c /* block size */ @@ -90,7 +90,7 @@ #define TMIO_SD_VOLT_180 (2 << 0)/* 1.8V signal */ #define TMIO_SD_DMA_MODE 0x410 #define TMIO_SD_DMA_MODE_DIR_RD BIT(16) /* 1: from device, 0: to dev */ -#define TMIO_SD_DMA_MODE_BUS_WIDTH (BIT(5) | BIT(4)) /* RCar, 64bit */ +#define TMIO_SD_DMA_MODE_BUS_WIDTH (BIT(5) | BIT(4)) /* R-Car, 64bit */ #define TMIO_SD_DMA_MODE_ADDR_INC BIT(0) /* 1: address inc, 0: fixed */ #define TMIO_SD_DMA_CTL 0x414 #define TMIO_SD_DMA_CTL_START BIT(0) /* start DMA (auto cleared) */ @@ -128,9 +128,9 @@ struct tmio_sd_priv { #define TMIO_SD_CAP_DIV1024 BIT(2) /* divisor 1024 is available */ #define TMIO_SD_CAP_64BIT BIT(3) /* Controller is 64bit */ #define TMIO_SD_CAP_16BIT BIT(4) /* Controller is 16bit */ -#define TMIO_SD_CAP_RCAR_GEN2 BIT(5) /* Renesas RCar version of IP */ -#define TMIO_SD_CAP_RCAR_GEN3 BIT(6) /* Renesas RCar version of IP */ -#define TMIO_SD_CAP_RCAR_UHS BIT(7) /* Renesas RCar UHS/SDR modes */ +#define TMIO_SD_CAP_RCAR_GEN2 BIT(5) /* Renesas R-Car version of IP */ +#define TMIO_SD_CAP_RCAR_GEN3 BIT(6) /* Renesas R-Car version of IP */ +#define TMIO_SD_CAP_RCAR_UHS BIT(7) /* Renesas R-Car UHS/SDR modes */ #define TMIO_SD_CAP_RCAR \ (TMIO_SD_CAP_RCAR_GEN2 | TMIO_SD_CAP_RCAR_GEN3) struct udevice *vqmmc_dev; diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig index 678bbde89e6..c71c1e5547c 100644 --- a/drivers/mtd/Kconfig +++ b/drivers/mtd/Kconfig @@ -194,11 +194,11 @@ config ALTERA_QSPI "Embedded Peripherals IP User Guide" of Altera. config RENESAS_RPC_HF - bool "Renesas RCar Gen3 RPC HyperFlash driver" + bool "Renesas R-Car Gen3 RPC HyperFlash driver" depends on RCAR_GEN3 && DM_MTD help This enables access to HyperFlash memory through the Renesas - RCar Gen3 RPC controller. + R-Car Gen3 RPC controller. config HBMC_AM654 bool "HyperBus controller driver for AM65x SoC" diff --git a/drivers/mtd/renesas_rpc_hf.c b/drivers/mtd/renesas_rpc_hf.c index 03545822b07..50a6191d9c2 100644 --- a/drivers/mtd/renesas_rpc_hf.c +++ b/drivers/mtd/renesas_rpc_hf.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Renesas RCar Gen3 RPC HyperFlash driver + * Renesas R-Car Gen3 RPC HyperFlash driver * * Copyright (C) 2016 Renesas Electronics Corporation * Copyright (C) 2016 Cogent Embedded, Inc. diff --git a/drivers/net/rswitch.c b/drivers/net/rswitch.c index 8e1b6e2f6f6..57eff748c90 100644 --- a/drivers/net/rswitch.c +++ b/drivers/net/rswitch.c @@ -837,6 +837,7 @@ static int rswitch_send(struct udevice *dev, void *packet, int len) /* Update TX descriptor */ rswitch_flush_dcache((uintptr_t)packet, len); + rswitch_invalidate_dcache((uintptr_t)desc, sizeof(*desc)); memset(desc, 0x0, sizeof(*desc)); desc->die_dt = DT_FSINGLE; desc->info_ds = len; @@ -1112,6 +1113,9 @@ static int rswitch_bind(struct udevice *parent) return -ENOENT; ofnode_for_each_subnode(node, ports_np) { + if (!ofnode_is_enabled(node)) + continue; + ret = device_bind_with_driver_data(parent, drv, ofnode_get_name(node), (ulong)priv, node, &dev); diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 876a5fa57ee..41901433e8c 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -189,19 +189,19 @@ config PCI_MSC01 depends on TARGET_MALTA config PCI_RCAR_GEN2 - bool "Renesas RCar Gen2 PCIe driver" + bool "Renesas R-Car Gen2 PCIe driver" depends on RCAR_32 help Say Y here if you want to enable PCIe controller support on - Renesas RCar Gen2 SoCs. The PCIe controller on RCar Gen2 is + Renesas R-Car Gen2 SoCs. The PCIe controller on R-Car Gen2 is also used to access EHCI USB controller on the SoC. config PCI_RCAR_GEN3 - bool "Renesas RCar Gen3 PCIe driver" + bool "Renesas R-Car Gen3 PCIe driver" depends on RCAR_GEN3 help Say Y here if you want to enable PCIe controller support on - Renesas RCar Gen3 SoCs. + Renesas R-Car Gen3 SoCs. config PCI_SANDBOX bool "Sandbox PCI support" diff --git a/drivers/pci/pci-rcar-gen2.c b/drivers/pci/pci-rcar-gen2.c index 12c31e74087..08d5c4fbb8b 100644 --- a/drivers/pci/pci-rcar-gen2.c +++ b/drivers/pci/pci-rcar-gen2.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Renesas RCar Gen2 PCIEC driver + * Renesas R-Car Gen2 PCIEC driver * * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> */ diff --git a/drivers/pci/pci-rcar-gen3.c b/drivers/pci/pci-rcar-gen3.c index 76878246f1e..d4b4037ce19 100644 --- a/drivers/pci/pci-rcar-gen3.c +++ b/drivers/pci/pci-rcar-gen3.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Renesas RCar Gen3 PCIEC driver + * Renesas R-Car Gen3 PCIEC driver * * Copyright (C) 2018-2019 Marek Vasut <marek.vasut@gmail.com> * diff --git a/drivers/phy/phy-rcar-gen2.c b/drivers/phy/phy-rcar-gen2.c index f9428c7ad12..be736629d51 100644 --- a/drivers/phy/phy-rcar-gen2.c +++ b/drivers/phy/phy-rcar-gen2.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Renesas RCar Gen2 USB PHY driver + * Renesas R-Car Gen2 USB PHY driver * * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> */ diff --git a/drivers/phy/phy-rcar-gen3.c b/drivers/phy/phy-rcar-gen3.c index b278f995f37..8c004eaf4c6 100644 --- a/drivers/phy/phy-rcar-gen3.c +++ b/drivers/phy/phy-rcar-gen3.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Renesas RCar Gen3 USB PHY driver + * Renesas R-Car Gen3 USB PHY driver * * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> */ diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig index 7ced7d784b3..560f7275454 100644 --- a/drivers/pinctrl/renesas/Kconfig +++ b/drivers/pinctrl/renesas/Kconfig @@ -23,34 +23,34 @@ config PINCTRL_PFC_FULL U-Boot driver. config PINCTRL_PFC_R8A7790 - bool "Renesas RCar Gen2 R8A7790 pin control driver" + bool "Renesas R-Car Gen2 R8A7790 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen2 R8A7790 SoCs. + Support pin multiplexing control on Renesas R-Car Gen2 R8A7790 SoCs. config PINCTRL_PFC_R8A7791 - bool "Renesas RCar Gen2 R8A7791 pin control driver" + bool "Renesas R-Car Gen2 R8A7791 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen2 R8A7791 SoCs. + Support pin multiplexing control on Renesas R-Car Gen2 R8A7791 SoCs. config PINCTRL_PFC_R8A7792 - bool "Renesas RCar Gen2 R8A7792 pin control driver" + bool "Renesas R-Car Gen2 R8A7792 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen2 R8A7792 SoCs. + Support pin multiplexing control on Renesas R-Car Gen2 R8A7792 SoCs. config PINCTRL_PFC_R8A7793 - bool "Renesas RCar Gen2 R8A7793 pin control driver" + bool "Renesas R-Car Gen2 R8A7793 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen2 R8A7793 SoCs. + Support pin multiplexing control on Renesas R-Car Gen2 R8A7793 SoCs. config PINCTRL_PFC_R8A7794 - bool "Renesas RCar Gen2 R8A7794 pin control driver" + bool "Renesas R-Car Gen2 R8A7794 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen2 R8A7794 SoCs. + Support pin multiplexing control on Renesas R-Car Gen2 R8A7794 SoCs. config PINCTRL_PFC_R8A774A1 bool "Renesas RZ/G2 R8A774A1 pin control driver" @@ -77,76 +77,76 @@ config PINCTRL_PFC_R8A774E1 Support pin multiplexing control on Renesas RZ/G2H R8A774E1 SoCs. config PINCTRL_PFC_R8A77951 - bool "Renesas RCar Gen3 R8A7795 pin control driver" + bool "Renesas R-Car Gen3 R8A7795 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen3 R8A7795 SoCs. + Support pin multiplexing control on Renesas R-Car Gen3 R8A7795 SoCs. config PINCTRL_PFC_R8A77960 - bool "Renesas RCar Gen3 R8A77960 pin control driver" + bool "Renesas R-Car Gen3 R8A77960 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen3 R8A77960 SoCs. + Support pin multiplexing control on Renesas R-Car Gen3 R8A77960 SoCs. config PINCTRL_PFC_R8A77961 - bool "Renesas RCar Gen3 R8A77961 pin control driver" + bool "Renesas R-Car Gen3 R8A77961 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen3 R8A77961 SoCs. + Support pin multiplexing control on Renesas R-Car Gen3 R8A77961 SoCs. config PINCTRL_PFC_R8A77965 - bool "Renesas RCar Gen3 R8A77965 pin control driver" + bool "Renesas R-Car Gen3 R8A77965 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen3 R8A77965 SoCs. + Support pin multiplexing control on Renesas R-Car Gen3 R8A77965 SoCs. config PINCTRL_PFC_R8A77970 - bool "Renesas RCar Gen3 R8A77970 pin control driver" + bool "Renesas R-Car Gen3 R8A77970 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen3 R8A77970 SoCs. + Support pin multiplexing control on Renesas R-Car Gen3 R8A77970 SoCs. config PINCTRL_PFC_R8A77980 - bool "Renesas RCar Gen3 R8A77980 pin control driver" + bool "Renesas R-Car Gen3 R8A77980 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen3 R8A77980 SoCs. + Support pin multiplexing control on Renesas R-Car Gen3 R8A77980 SoCs. config PINCTRL_PFC_R8A77990 - bool "Renesas RCar Gen3 R8A77990 pin control driver" + bool "Renesas R-Car Gen3 R8A77990 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen3 R8A77990 SoCs. + Support pin multiplexing control on Renesas R-Car Gen3 R8A77990 SoCs. config PINCTRL_PFC_R8A77995 - bool "Renesas RCar Gen3 R8A77995 pin control driver" + bool "Renesas R-Car Gen3 R8A77995 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen3 R8A77995 SoCs. + Support pin multiplexing control on Renesas R-Car Gen3 R8A77995 SoCs. config PINCTRL_PFC_R8A779A0 - bool "Renesas RCar Gen3 R8A779A0 pin control driver" + bool "Renesas R-Car Gen3 R8A779A0 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen3 R8A779A0 SoCs. + Support pin multiplexing control on Renesas R-Car Gen3 R8A779A0 SoCs. config PINCTRL_PFC_R8A779F0 - bool "Renesas RCar Gen4 R8A779F0 pin control driver" + bool "Renesas R-Car Gen4 R8A779F0 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen4 R8A779F0 SoCs. + Support pin multiplexing control on Renesas R-Car Gen4 R8A779F0 SoCs. config PINCTRL_PFC_R8A779G0 - bool "Renesas RCar Gen4 R8A779G0 pin control driver" + bool "Renesas R-Car Gen4 R8A779G0 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen4 R8A779G0 SoCs. + Support pin multiplexing control on Renesas R-Car Gen4 R8A779G0 SoCs. config PINCTRL_PFC_R8A779H0 - bool "Renesas RCar Gen4 R8A779H0 pin control driver" + bool "Renesas R-Car Gen4 R8A779H0 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen4 R8A779H0 SoCs. + Support pin multiplexing control on Renesas R-Car Gen4 R8A779H0 SoCs. config PINCTRL_RZA1 bool "Renesas RZ/A1 R7S72100 pin control driver" diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 8b27ad9a77e..c4f4a8d78df 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -920,7 +920,7 @@ config SCIF_CONSOLE depends on SH || ARCH_RENESAS help Select this to enable Renesas SCIF UART. To operate serial ports - on systems with RCar or SH SoCs, say Y to this option. If unsure, + on systems with R-Car or SH SoCs, say Y to this option. If unsure, say N. choice diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index fd5cb3694f6..96ea033082b 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -420,7 +420,7 @@ config RENESAS_RPC_SPI imply SPI_FLASH_SFDP_SUPPORT help Enable the Renesas RPC SPI driver, used to access SPI NOR flash - on Renesas RCar Gen3 SoCs. This uses driver model and requires a + on Renesas R-Car Gen3 SoCs. This uses driver model and requires a device tree binding to operate. config ROCKCHIP_SFC diff --git a/drivers/spi/renesas_rpc_spi.c b/drivers/spi/renesas_rpc_spi.c index f1e6f9f4e01..7103d786c7e 100644 --- a/drivers/spi/renesas_rpc_spi.c +++ b/drivers/spi/renesas_rpc_spi.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Renesas RCar Gen3 RPC QSPI driver + * Renesas R-Car Gen3 RPC QSPI driver * * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> */ diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig index 010084ef7f3..c815764c2bc 100644 --- a/drivers/usb/gadget/Kconfig +++ b/drivers/usb/gadget/Kconfig @@ -115,10 +115,10 @@ config USB_GADGET_DWC2_OTG USB_GADGET to be enabled. config USB_RENESAS_USBHS - bool "Renesas RCar USB2.0 HS controller (gadget mode)" + bool "Renesas R-Car USB2.0 HS controller (gadget mode)" select USB_GADGET_DUALSPEED help - The Renesas Rcar USB 2.0 high-speed gadget controller + The Renesas R-Car USB 2.0 high-speed gadget controller integrated into Salvator and Kingfisher boards. Select this option if you want the driver to operate in Peripheral mode. This option requires USB_GADGET to be enabled. diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index bb5893d56db..24786a2bc91 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -103,12 +103,12 @@ config USB_XHCI_PCI Enables support for the PCI-based xHCI controller. config USB_XHCI_RCAR - bool "Renesas RCar USB 3.0 support" + bool "Renesas R-Car USB 3.0 support" default y depends on ARCH_RENESAS help Choose this option to add support for USB 3.0 driver on Renesas - RCar Gen3 SoCs. + R-Car Gen3 SoCs. config USB_XHCI_STI bool "Support for STMicroelectronics STiH407 family on-chip xHCI USB controller" diff --git a/drivers/usb/host/xhci-rcar-r8a779x_usb3_v3.h b/drivers/usb/host/xhci-rcar-r8a779x_usb3_v3.h index 8db88f0dcfa..7c909b4697a 100644 --- a/drivers/usb/host/xhci-rcar-r8a779x_usb3_v3.h +++ b/drivers/usb/host/xhci-rcar-r8a779x_usb3_v3.h @@ -1,5 +1,5 @@ /* - * Renesas RCar xHCI controller firmware version 3 + * Renesas R-Car xHCI controller firmware version 3 * * Copyright (c) 2014, Renesas Electronics Corporation * All rights reserved. diff --git a/drivers/usb/host/xhci-rcar.c b/drivers/usb/host/xhci-rcar.c index 38c5928faed..b72807053c4 100644 --- a/drivers/usb/host/xhci-rcar.c +++ b/drivers/usb/host/xhci-rcar.c @@ -2,7 +2,7 @@ /* * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com> * - * Renesas RCar USB HOST xHCI Controller + * Renesas R-Car USB HOST xHCI Controller */ #include <clk.h> diff --git a/drivers/video/zynqmp/zynqmp_dpsub.c b/drivers/video/zynqmp/zynqmp_dpsub.c index 76abfeac443..52af23c3c83 100644 --- a/drivers/video/zynqmp/zynqmp_dpsub.c +++ b/drivers/video/zynqmp/zynqmp_dpsub.c @@ -11,6 +11,7 @@ #include <dm.h> #include <errno.h> #include <generic-phy.h> +#include <reset.h> #include <stdlib.h> #include <video.h> #include <wait_bit.h> @@ -2093,10 +2094,15 @@ static int zynqmp_dpsub_probe(struct udevice *dev) { struct video_priv *uc_priv = dev_get_uclass_priv(dev); struct zynqmp_dpsub_priv *priv = dev_get_priv(dev); + struct reset_ctl_bulk resets; struct clk clk; int ret; int mode = RGBA8888; + ret = reset_get_bulk(dev, &resets); + if (!ret) + reset_deassert_bulk(&resets); + ret = clk_get_by_name(dev, "dp_apb_clk", &clk); if (ret < 0) { dev_err(dev, "failed to get clock\n"); |