summaryrefslogtreecommitdiff
path: root/drivers
diff options
context:
space:
mode:
Diffstat (limited to 'drivers')
-rw-r--r--drivers/clk/Kconfig8
-rw-r--r--drivers/clk/Makefile2
-rw-r--r--drivers/clk/at91/Kconfig6
-rw-r--r--drivers/clk/at91/clk-generated.c18
-rw-r--r--drivers/clk/clk_stm32f.c (renamed from drivers/clk/clk_stm32f7.c)272
-rw-r--r--drivers/misc/stm32_rcc.c42
-rw-r--r--drivers/mmc/Kconfig12
-rw-r--r--drivers/mmc/Makefile1
-rw-r--r--drivers/mmc/atmel_sdhci.c12
-rw-r--r--drivers/mmc/ftsdc010_mci.c143
-rw-r--r--drivers/mmc/ftsdc010_mci.h53
-rw-r--r--drivers/mmc/nds32_mmc.c136
-rw-r--r--drivers/spi/Kconfig10
-rw-r--r--drivers/spi/Makefile2
-rw-r--r--drivers/spi/atcspi200_spi.c (renamed from drivers/spi/nds_ae3xx_spi.c)96
-rw-r--r--drivers/timer/Kconfig9
-rw-r--r--drivers/timer/Makefile2
-rw-r--r--drivers/timer/atcpit100_timer.c (renamed from drivers/timer/ae3xx_timer.c)38
18 files changed, 646 insertions, 216 deletions
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index baa60a52e68..f6644ee6d16 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -46,6 +46,14 @@ config CLK_BOSTON
help
Enable this to support the clocks
+config CLK_STM32F
+ bool "Enable clock driver support for STM32F family"
+ depends on CLK && (STM32F7 || STM32F4)
+ default y
+ help
+ This clock driver adds support for RCC clock management
+ for STM32F4 and STM32F7 SoCs.
+
config CLK_ZYNQ
bool "Enable clock driver support for Zynq"
depends on CLK && ARCH_ZYNQ
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 83fe88ce9f5..bcc8f82fb65 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -21,5 +21,5 @@ obj-$(CONFIG_CLK_AT91) += at91/
obj-$(CONFIG_CLK_BCM6345) += clk_bcm6345.o
obj-$(CONFIG_CLK_BOSTON) += clk_boston.o
obj-$(CONFIG_ARCH_ASPEED) += aspeed/
-obj-$(CONFIG_STM32F7) += clk_stm32f7.o
+obj-$(CONFIG_CLK_STM32F) += clk_stm32f.o
obj-$(CONFIG_STM32H7) += clk_stm32h7.o
diff --git a/drivers/clk/at91/Kconfig b/drivers/clk/at91/Kconfig
index c6c57618c14..fd56f200b9f 100644
--- a/drivers/clk/at91/Kconfig
+++ b/drivers/clk/at91/Kconfig
@@ -14,11 +14,11 @@ config CLK_AT91
config AT91_UTMI
bool "Support UTMI PLL Clock"
- depends on CLK_AT91 && SPL_DM
+ depends on CLK_AT91
select REGMAP
- select SPL_REGMAP
+ select SPL_REGMAP if SPL_DM
select SYSCON
- select SPL_SYSCON
+ select SPL_SYSCON if SPL_DM
help
This option is used to enable the AT91 UTMI PLL clock
driver. It is the clock provider of USB, and UPLLCK is the
diff --git a/drivers/clk/at91/clk-generated.c b/drivers/clk/at91/clk-generated.c
index 8c9a3cb053a..2aacbaef0c0 100644
--- a/drivers/clk/at91/clk-generated.c
+++ b/drivers/clk/at91/clk-generated.c
@@ -53,16 +53,17 @@ static ulong generic_clk_get_rate(struct clk *clk)
struct clk parent;
ulong clk_rate;
u32 tmp, gckdiv;
- u8 parent_id;
+ u8 clock_source, parent_index;
int ret;
writel(clk->id & AT91_PMC_PCR_PID_MASK, &pmc->pcr);
tmp = readl(&pmc->pcr);
- parent_id = (tmp >> AT91_PMC_PCR_GCKCSS_OFFSET) &
+ clock_source = (tmp >> AT91_PMC_PCR_GCKCSS_OFFSET) &
AT91_PMC_PCR_GCKCSS_MASK;
gckdiv = (tmp >> AT91_PMC_PCR_GCKDIV_OFFSET) & AT91_PMC_PCR_GCKDIV_MASK;
- ret = clk_get_by_index(dev_get_parent(clk->dev), parent_id, &parent);
+ parent_index = clock_source - 1;
+ ret = clk_get_by_index(dev_get_parent(clk->dev), parent_index, &parent);
if (ret)
return 0;
@@ -82,7 +83,7 @@ static ulong generic_clk_set_rate(struct clk *clk, ulong rate)
ulong tmp_rate, best_rate = rate, parent_rate;
int tmp_diff, best_diff = -1;
u32 div, best_div = 0;
- u8 best_parent_id = 0;
+ u8 best_parent_index, best_clock_source = 0;
u8 i;
u32 tmp;
int ret;
@@ -98,9 +99,7 @@ static ulong generic_clk_set_rate(struct clk *clk, ulong rate)
for (div = 1; div < GENERATED_MAX_DIV + 2; div++) {
tmp_rate = DIV_ROUND_CLOSEST(parent_rate, div);
- if (rate < tmp_rate)
- continue;
- tmp_diff = rate - tmp_rate;
+ tmp_diff = abs(rate - tmp_rate);
if (best_diff < 0 || best_diff > tmp_diff) {
best_rate = tmp_rate;
@@ -108,7 +107,8 @@ static ulong generic_clk_set_rate(struct clk *clk, ulong rate)
best_div = div - 1;
best_parent = parent;
- best_parent_id = i;
+ best_parent_index = i;
+ best_clock_source = best_parent_index + 1;
}
if (!best_diff || tmp_rate < rate)
@@ -129,7 +129,7 @@ static ulong generic_clk_set_rate(struct clk *clk, ulong rate)
writel(clk->id & AT91_PMC_PCR_PID_MASK, &pmc->pcr);
tmp = readl(&pmc->pcr);
tmp &= ~(AT91_PMC_PCR_GCKDIV | AT91_PMC_PCR_GCKCSS);
- tmp |= AT91_PMC_PCR_GCKCSS_(best_parent_id) |
+ tmp |= AT91_PMC_PCR_GCKCSS_(best_clock_source) |
AT91_PMC_PCR_CMD_WRITE |
AT91_PMC_PCR_GCKDIV_(best_div) |
AT91_PMC_PCR_GCKEN;
diff --git a/drivers/clk/clk_stm32f7.c b/drivers/clk/clk_stm32f.c
index f1a9e9ca44e..634f0717c68 100644
--- a/drivers/clk/clk_stm32f7.c
+++ b/drivers/clk/clk_stm32f.c
@@ -8,10 +8,12 @@
#include <common.h>
#include <clk-uclass.h>
#include <dm.h>
+#include <stm32_rcc.h>
+
#include <asm/io.h>
-#include <asm/arch/rcc.h>
#include <asm/arch/stm32.h>
#include <asm/arch/stm32_periph.h>
+#include <asm/arch/stm32_pwr.h>
#include <dt-bindings/mfd/stm32f7-rcc.h>
@@ -22,6 +24,8 @@
#define RCC_CR_CSSON BIT(19)
#define RCC_CR_PLLON BIT(24)
#define RCC_CR_PLLRDY BIT(25)
+#define RCC_CR_PLLSAION BIT(28)
+#define RCC_CR_PLLSAIRDY BIT(29)
#define RCC_PLLCFGR_PLLM_MASK GENMASK(5, 0)
#define RCC_PLLCFGR_PLLN_MASK GENMASK(14, 6)
@@ -52,75 +56,87 @@
#define RCC_CFGR_PPRE1_SHIFT 10
#define RCC_CFGR_PPRE2_SHIFT 13
+#define RCC_PLLCFGR_PLLSAIN_MASK GENMASK(14, 6)
+#define RCC_PLLCFGR_PLLSAIP_MASK GENMASK(17, 16)
+#define RCC_PLLSAICFGR_PLLSAIN_SHIFT 6
+#define RCC_PLLSAICFGR_PLLSAIP_SHIFT 16
+#define RCC_PLLSAICFGR_PLLSAIP_4 BIT(17)
+#define RCC_PLLSAICFGR_PLLSAIQ_4 BIT(26)
+#define RCC_PLLSAICFGR_PLLSAIR_2 BIT(29)
+
+#define RCC_DCKCFGRX_CK48MSEL BIT(27)
+#define RCC_DCKCFGRX_SDMMC1SEL BIT(28)
+#define RCC_DCKCFGR2_SDMMC2SEL BIT(29)
+
+#define RCC_APB2ENR_SAI1EN BIT(22)
+
+/*
+ * RCC AHB1ENR specific definitions
+ */
+#define RCC_AHB1ENR_ETHMAC_EN BIT(25)
+#define RCC_AHB1ENR_ETHMAC_TX_EN BIT(26)
+#define RCC_AHB1ENR_ETHMAC_RX_EN BIT(27)
+
/*
- * Offsets of some PWR registers
+ * RCC APB1ENR specific definitions
*/
-#define PWR_CR1_ODEN BIT(16)
-#define PWR_CR1_ODSWEN BIT(17)
-#define PWR_CSR1_ODRDY BIT(16)
-#define PWR_CSR1_ODSWRDY BIT(17)
-
-struct pll_psc {
- u8 pll_m;
- u16 pll_n;
- u8 pll_p;
- u8 pll_q;
- u8 ahb_psc;
- u8 apb1_psc;
- u8 apb2_psc;
+#define RCC_APB1ENR_TIM2EN BIT(0)
+#define RCC_APB1ENR_PWREN BIT(28)
+
+/*
+ * RCC APB2ENR specific definitions
+ */
+#define RCC_APB2ENR_SYSCFGEN BIT(14)
+
+struct stm32_clk_info stm32f4_clk_info = {
+ /* 180 MHz */
+ .sys_pll_psc = {
+ .pll_m = 8,
+ .pll_n = 360,
+ .pll_p = 2,
+ .pll_q = 8,
+ .ahb_psc = AHB_PSC_1,
+ .apb1_psc = APB_PSC_4,
+ .apb2_psc = APB_PSC_2,
+ },
+ .has_overdrive = false,
+ .v2 = false,
};
-#define AHB_PSC_1 0
-#define AHB_PSC_2 0x8
-#define AHB_PSC_4 0x9
-#define AHB_PSC_8 0xA
-#define AHB_PSC_16 0xB
-#define AHB_PSC_64 0xC
-#define AHB_PSC_128 0xD
-#define AHB_PSC_256 0xE
-#define AHB_PSC_512 0xF
-
-#define APB_PSC_1 0
-#define APB_PSC_2 0x4
-#define APB_PSC_4 0x5
-#define APB_PSC_8 0x6
-#define APB_PSC_16 0x7
+struct stm32_clk_info stm32f7_clk_info = {
+ /* 200 MHz */
+ .sys_pll_psc = {
+ .pll_m = 25,
+ .pll_n = 400,
+ .pll_p = 2,
+ .pll_q = 8,
+ .ahb_psc = AHB_PSC_1,
+ .apb1_psc = APB_PSC_4,
+ .apb2_psc = APB_PSC_2,
+ },
+ .has_overdrive = true,
+ .v2 = true,
+};
struct stm32_clk {
struct stm32_rcc_regs *base;
+ struct stm32_pwr_regs *pwr_regs;
+ struct stm32_clk_info *info;
};
-#if !defined(CONFIG_STM32_HSE_HZ)
-#error "CONFIG_STM32_HSE_HZ not defined!"
-#else
-#if (CONFIG_STM32_HSE_HZ == 25000000)
-#if (CONFIG_SYS_CLK_FREQ == 200000000)
-/* 200 MHz */
-struct pll_psc sys_pll_psc = {
- .pll_m = 25,
- .pll_n = 400,
- .pll_p = 2,
- .pll_q = 8,
- .ahb_psc = AHB_PSC_1,
- .apb1_psc = APB_PSC_4,
- .apb2_psc = APB_PSC_2
-};
-#endif
-#else
-#error "No PLL/Prescaler configuration for given CONFIG_STM32_HSE_HZ exists"
-#endif
-#endif
-
static int configure_clocks(struct udevice *dev)
{
struct stm32_clk *priv = dev_get_priv(dev);
struct stm32_rcc_regs *regs = priv->base;
+ struct stm32_pwr_regs *pwr = priv->pwr_regs;
+ struct pll_psc sys_pll_psc = priv->info->sys_pll_psc;
+ u32 pllsaicfgr = 0;
/* Reset RCC configuration */
setbits_le32(&regs->cr, RCC_CR_HSION);
writel(0, &regs->cfgr); /* Reset CFGR */
clrbits_le32(&regs->cr, (RCC_CR_HSEON | RCC_CR_CSSON
- | RCC_CR_PLLON));
+ | RCC_CR_PLLON | RCC_CR_PLLSAION));
writel(0x24003010, &regs->pllcfgr); /* Reset value from RM */
clrbits_le32(&regs->cr, RCC_CR_HSEBYP);
writel(0, &regs->cir); /* Disable all interrupts */
@@ -146,23 +162,57 @@ static int configure_clocks(struct udevice *dev)
clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLQ_MASK,
sys_pll_psc.pll_q << RCC_PLLCFGR_PLLQ_SHIFT);
+ /* Configure the SAI PLL to get a 48 MHz source */
+ pllsaicfgr = RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIQ_4 |
+ RCC_PLLSAICFGR_PLLSAIP_4;
+ pllsaicfgr |= 192 << RCC_PLLSAICFGR_PLLSAIN_SHIFT;
+ writel(pllsaicfgr, &regs->pllsaicfgr);
+
/* Enable the main PLL */
setbits_le32(&regs->cr, RCC_CR_PLLON);
while (!(readl(&regs->cr) & RCC_CR_PLLRDY))
;
- /* Enable high performance mode, System frequency up to 200 MHz */
- setbits_le32(&regs->apb1enr, RCC_APB1ENR_PWREN);
- setbits_le32(&STM32_PWR->cr1, PWR_CR1_ODEN);
- /* Infinite wait! */
- while (!(readl(&STM32_PWR->csr1) & PWR_CSR1_ODRDY))
- ;
- /* Enable the Over-drive switch */
- setbits_le32(&STM32_PWR->cr1, PWR_CR1_ODSWEN);
- /* Infinite wait! */
- while (!(readl(&STM32_PWR->csr1) & PWR_CSR1_ODSWRDY))
+ if (priv->info->v2) { /*stm32f7 case */
+ /* select PLLSAI as 48MHz clock source */
+ setbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_CK48MSEL);
+
+ /* select 48MHz as SDMMC1 clock source */
+ clrbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_SDMMC1SEL);
+
+ /* select 48MHz as SDMMC2 clock source */
+ clrbits_le32(&regs->dckcfgr2, RCC_DCKCFGR2_SDMMC2SEL);
+ } else { /* stm32f4 case */
+ /* select PLLSAI as 48MHz clock source */
+ setbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_CK48MSEL);
+
+ /* select 48MHz as SDMMC1 clock source */
+ clrbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_SDMMC1SEL);
+ }
+
+ /* Enable the SAI PLL */
+ setbits_le32(&regs->cr, RCC_CR_PLLSAION);
+ while (!(readl(&regs->cr) & RCC_CR_PLLSAIRDY))
;
+ setbits_le32(&regs->apb1enr, RCC_APB1ENR_PWREN);
+
+ if (priv->info->has_overdrive) {
+ /*
+ * Enable high performance mode
+ * System frequency up to 200 MHz
+ */
+ setbits_le32(&pwr->cr1, PWR_CR1_ODEN);
+ /* Infinite wait! */
+ while (!(readl(&pwr->csr1) & PWR_CSR1_ODRDY))
+ ;
+ /* Enable the Over-drive switch */
+ setbits_le32(&pwr->cr1, PWR_CR1_ODSWEN);
+ /* Infinite wait! */
+ while (!(readl(&pwr->csr1) & PWR_CSR1_ODSWRDY))
+ ;
+ }
+
stm32_flash_latency_cfg(5);
clrbits_le32(&regs->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1));
setbits_le32(&regs->cfgr, RCC_CFGR_SW_PLL);
@@ -170,16 +220,47 @@ static int configure_clocks(struct udevice *dev)
while ((readl(&regs->cfgr) & RCC_CFGR_SWS_MASK) !=
RCC_CFGR_SWS_PLL)
;
+ /* gate the SAI clock, needed for MMC 1&2 clocks */
+ setbits_le32(&regs->apb2enr, RCC_APB2ENR_SAI1EN);
return 0;
}
+static unsigned long stm32_clk_pll48clk_rate(struct stm32_clk *priv,
+ u32 sysclk)
+{
+ struct stm32_rcc_regs *regs = priv->base;
+ u16 pllq, pllm, pllsain, pllsaip;
+ bool pllsai;
+
+ pllq = (readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLQ_MASK)
+ >> RCC_PLLCFGR_PLLQ_SHIFT;
+
+ if (priv->info->v2) /*stm32f7 case */
+ pllsai = readl(&regs->dckcfgr2) & RCC_DCKCFGRX_CK48MSEL;
+ else
+ pllsai = readl(&regs->dckcfgr) & RCC_DCKCFGRX_CK48MSEL;
+
+ if (pllsai) {
+ /* PLL48CLK is selected from PLLSAI, get PLLSAI value */
+ pllm = (readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
+ pllsain = ((readl(&regs->pllsaicfgr) & RCC_PLLCFGR_PLLSAIN_MASK)
+ >> RCC_PLLSAICFGR_PLLSAIN_SHIFT);
+ pllsaip = ((((readl(&regs->pllsaicfgr) & RCC_PLLCFGR_PLLSAIP_MASK)
+ >> RCC_PLLSAICFGR_PLLSAIP_SHIFT) + 1) << 1);
+ return ((CONFIG_STM32_HSE_HZ / pllm) * pllsain) / pllsaip;
+ }
+ /* PLL48CLK is selected from PLLQ */
+ return sysclk / pllq;
+}
+
static unsigned long stm32_clk_get_rate(struct clk *clk)
{
struct stm32_clk *priv = dev_get_priv(clk->dev);
struct stm32_rcc_regs *regs = priv->base;
u32 sysclk = 0;
u32 shift = 0;
+ u16 pllm, plln, pllp;
/* Prescaler table lookups for clock computation */
u8 ahb_psc_table[16] = {
0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9
@@ -190,7 +271,6 @@ static unsigned long stm32_clk_get_rate(struct clk *clk)
if ((readl(&regs->cfgr) & RCC_CFGR_SWS_MASK) ==
RCC_CFGR_SWS_PLL) {
- u16 pllm, plln, pllp;
pllm = (readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
plln = ((readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLN_MASK)
>> RCC_PLLCFGR_PLLN_SHIFT);
@@ -211,25 +291,43 @@ static unsigned long stm32_clk_get_rate(struct clk *clk)
(readl(&regs->cfgr) & RCC_CFGR_AHB_PSC_MASK)
>> RCC_CFGR_HPRE_SHIFT)];
return sysclk >>= shift;
- break;
/* APB1 CLOCK */
case STM32F7_APB1_CLOCK(TIM2) ... STM32F7_APB1_CLOCK(UART8):
shift = apb_psc_table[(
(readl(&regs->cfgr) & RCC_CFGR_APB1_PSC_MASK)
>> RCC_CFGR_PPRE1_SHIFT)];
return sysclk >>= shift;
- break;
/* APB2 CLOCK */
case STM32F7_APB2_CLOCK(TIM1) ... STM32F7_APB2_CLOCK(LTDC):
+ /*
+ * particular case for SDMMC1 and SDMMC2 :
+ * 48Mhz source clock can be from main PLL or from
+ * SAI PLL
+ */
+ switch (clk->id) {
+ case STM32F7_APB2_CLOCK(SDMMC1):
+ if (readl(&regs->dckcfgr2) & RCC_DCKCFGRX_SDMMC1SEL)
+ /* System clock is selected as SDMMC1 clock */
+ return sysclk;
+ else
+ return stm32_clk_pll48clk_rate(priv, sysclk);
+ break;
+ case STM32F7_APB2_CLOCK(SDMMC2):
+ if (readl(&regs->dckcfgr2) & RCC_DCKCFGR2_SDMMC2SEL)
+ /* System clock is selected as SDMMC2 clock */
+ return sysclk;
+ else
+ return stm32_clk_pll48clk_rate(priv, sysclk);
+ break;
+ }
+
shift = apb_psc_table[(
(readl(&regs->cfgr) & RCC_CFGR_APB2_PSC_MASK)
>> RCC_CFGR_PPRE2_SHIFT)];
return sysclk >>= shift;
- break;
default:
pr_err("clock index %ld out of range\n", clk->id);
return -EINVAL;
- break;
}
}
@@ -268,17 +366,43 @@ void clock_setup(int peripheral)
static int stm32_clk_probe(struct udevice *dev)
{
- debug("%s: stm32_clk_probe\n", __func__);
+ struct ofnode_phandle_args args;
+ int err;
+
+ debug("%s\n", __func__);
struct stm32_clk *priv = dev_get_priv(dev);
fdt_addr_t addr;
- addr = devfdt_get_addr(dev);
+ addr = dev_read_addr(dev);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
priv->base = (struct stm32_rcc_regs *)addr;
+ switch (dev_get_driver_data(dev)) {
+ case STM32F4:
+ priv->info = &stm32f4_clk_info;
+ break;
+ case STM32F7:
+ priv->info = &stm32f7_clk_info;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ if (priv->info->has_overdrive) {
+ err = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0,
+ &args);
+ if (err) {
+ debug("%s: can't find syscon device (%d)\n", __func__,
+ err);
+ return err;
+ }
+
+ priv->pwr_regs = (struct stm32_pwr_regs *)ofnode_get_addr(args.node);
+ }
+
configure_clocks(dev);
return 0;
@@ -307,15 +431,9 @@ static struct clk_ops stm32_clk_ops = {
.get_rate = stm32_clk_get_rate,
};
-static const struct udevice_id stm32_clk_ids[] = {
- { .compatible = "st,stm32f42xx-rcc"},
- {}
-};
-
-U_BOOT_DRIVER(stm32f7_clk) = {
- .name = "stm32f7_clk",
+U_BOOT_DRIVER(stm32fx_clk) = {
+ .name = "stm32fx_rcc_clock",
.id = UCLASS_CLK,
- .of_match = stm32_clk_ids,
.ops = &stm32_clk_ops,
.probe = stm32_clk_probe,
.priv_auto_alloc_size = sizeof(struct stm32_clk),
diff --git a/drivers/misc/stm32_rcc.c b/drivers/misc/stm32_rcc.c
index 32d39719d81..87d9928362b 100644
--- a/drivers/misc/stm32_rcc.c
+++ b/drivers/misc/stm32_rcc.c
@@ -8,31 +8,63 @@
#include <common.h>
#include <dm.h>
#include <misc.h>
+#include <stm32_rcc.h>
+#include <dm/device-internal.h>
#include <dm/lists.h>
+struct stm32_rcc_clk stm32_rcc_clk_f4 = {
+ .drv_name = "stm32fx_rcc_clock",
+ .soc = STM32F4,
+};
+
+struct stm32_rcc_clk stm32_rcc_clk_f7 = {
+ .drv_name = "stm32fx_rcc_clock",
+ .soc = STM32F7,
+};
+
+struct stm32_rcc_clk stm32_rcc_clk_h7 = {
+ .drv_name = "stm32h7_rcc_clock",
+};
+
static int stm32_rcc_bind(struct udevice *dev)
{
- int ret;
struct udevice *child;
+ struct driver *drv;
+ struct stm32_rcc_clk *rcc_clk =
+ (struct stm32_rcc_clk *)dev_get_driver_data(dev);
+ int ret;
debug("%s(dev=%p)\n", __func__, dev);
- ret = device_bind_driver_to_node(dev, "stm32h7_rcc_clock",
- "stm32h7_rcc_clock",
- dev_ofnode(dev), &child);
+ drv = lists_driver_lookup_name(rcc_clk->drv_name);
+ if (!drv) {
+ debug("Cannot find driver '%s'\n", rcc_clk->drv_name);
+ return -ENOENT;
+ }
+
+ ret = device_bind_with_driver_data(dev, drv, rcc_clk->drv_name,
+ rcc_clk->soc,
+ dev_ofnode(dev), &child);
+
if (ret)
return ret;
+#ifdef CONFIG_SPL_BUILD
+ return 0;
+#else
return device_bind_driver_to_node(dev, "stm32_rcc_reset",
"stm32_rcc_reset",
dev_ofnode(dev), &child);
+#endif
}
static const struct misc_ops stm32_rcc_ops = {
};
static const struct udevice_id stm32_rcc_ids[] = {
- {.compatible = "st,stm32h743-rcc"},
+ {.compatible = "st,stm32f42xx-rcc", .data = (ulong)&stm32_rcc_clk_f4 },
+ {.compatible = "st,stm32f746-rcc", .data = (ulong)&stm32_rcc_clk_f7 },
+ {.compatible = "st,stm32h743-rcc", .data = (ulong)&stm32_rcc_clk_h7 },
{ }
};
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 62ce0af7d3c..8fbeaa740d6 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -401,6 +401,18 @@ config STM32_SDMMC2
If you have a board based on such a SoC and with a SD/MMC slot,
say Y or M here.
+config MMC_NDS32
+ bool "Andestech SD/MMC controller support"
+ depends on DM_MMC && OF_CONTROL && BLK && FTSDC010
+ help
+ This enables support for the Andestech SD/MMM controller, which is
+ based on Faraday IP.
+
+config FTSDC010
+ bool "Ftsdc010 SD/MMC controller Support"
+ help
+ This SD/MMC controller is present in Andestech SoCs which is based on Faraday IP.
+
endif
config TEGRA124_MMC_DISABLE_EXT_LOOPBACK
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index d505f37f019..9af375b044a 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -44,6 +44,7 @@ obj-$(CONFIG_MMC_SANDBOX) += sandbox_mmc.o
obj-$(CONFIG_SH_MMCIF) += sh_mmcif.o
obj-$(CONFIG_SH_SDHI) += sh_sdhi.o
obj-$(CONFIG_STM32_SDMMC2) += stm32_sdmmc2.o
+obj-$(CONFIG_MMC_NDS32) += nds32_mmc.o
# SDHCI
obj-$(CONFIG_MMC_SDHCI) += sdhci.o
diff --git a/drivers/mmc/atmel_sdhci.c b/drivers/mmc/atmel_sdhci.c
index c19a1f36b69..9b37e32c8db 100644
--- a/drivers/mmc/atmel_sdhci.c
+++ b/drivers/mmc/atmel_sdhci.c
@@ -13,6 +13,7 @@
#include <asm/arch/clk.h>
#define ATMEL_SDHC_MIN_FREQ 400000
+#define ATMEL_SDHC_GCK_RATE 240000000
#ifndef CONFIG_DM_MMC
int atmel_sdhci_init(void *regbase, u32 id)
@@ -57,9 +58,6 @@ static int atmel_sdhci_probe(struct udevice *dev)
struct atmel_sdhci_plat *plat = dev_get_platdata(dev);
struct sdhci_host *host = dev_get_priv(dev);
u32 max_clk;
- u32 caps, caps_1;
- u32 clk_base, clk_mul;
- ulong gck_rate;
struct clk clk;
int ret;
@@ -78,17 +76,11 @@ static int atmel_sdhci_probe(struct udevice *dev)
host->bus_width = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"bus-width", 4);
- caps = sdhci_readl(host, SDHCI_CAPABILITIES);
- clk_base = (caps & SDHCI_CLOCK_V3_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
- caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
- clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >> SDHCI_CLOCK_MUL_SHIFT;
- gck_rate = clk_base * 1000000 * (clk_mul + 1);
-
ret = clk_get_by_index(dev, 1, &clk);
if (ret)
return ret;
- ret = clk_set_rate(&clk, gck_rate);
+ ret = clk_set_rate(&clk, ATMEL_SDHC_GCK_RATE);
if (ret)
return ret;
diff --git a/drivers/mmc/ftsdc010_mci.c b/drivers/mmc/ftsdc010_mci.c
index 652a718467a..6ac4f83bd1c 100644
--- a/drivers/mmc/ftsdc010_mci.c
+++ b/drivers/mmc/ftsdc010_mci.c
@@ -12,24 +12,15 @@
#include <part.h>
#include <mmc.h>
-#include <asm/io.h>
+#include <linux/io.h>
#include <linux/errno.h>
#include <asm/byteorder.h>
#include <faraday/ftsdc010.h>
+#include "ftsdc010_mci.h"
#define CFG_CMD_TIMEOUT (CONFIG_SYS_HZ >> 4) /* 250 ms */
#define CFG_RST_TIMEOUT CONFIG_SYS_HZ /* 1 sec reset timeout */
-struct ftsdc010_chip {
- void __iomem *regs;
- uint32_t wprot; /* write protected (locked) */
- uint32_t rate; /* actual SD clock in Hz */
- uint32_t sclk; /* FTSDC010 source clock in Hz */
- uint32_t fifo; /* fifo depth in bytes */
- uint32_t acmd;
- struct mmc_config cfg; /* mmc configuration */
-};
-
static inline int ftsdc010_send_cmd(struct mmc *mmc, struct mmc_cmd *mmc_cmd)
{
struct ftsdc010_chip *chip = mmc->priv;
@@ -127,9 +118,8 @@ static void ftsdc010_clkset(struct mmc *mmc, uint32_t rate)
static int ftsdc010_wait(struct ftsdc010_mmc __iomem *regs, uint32_t mask)
{
int ret = -ETIMEDOUT;
- uint32_t st, ts;
-
- for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) {
+ uint32_t st, timeout = 10000000;
+ while (timeout--) {
st = readl(&regs->status);
if (!(st & mask))
continue;
@@ -138,8 +128,9 @@ static int ftsdc010_wait(struct ftsdc010_mmc __iomem *regs, uint32_t mask)
break;
}
- if (ret)
+ if (ret){
debug("ftsdc010: wait st(0x%x) timeout\n", mask);
+ }
return ret;
}
@@ -147,10 +138,16 @@ static int ftsdc010_wait(struct ftsdc010_mmc __iomem *regs, uint32_t mask)
/*
* u-boot mmc api
*/
-
+#ifdef CONFIG_DM_MMC
+static int ftsdc010_request(struct udevice *dev, struct mmc_cmd *cmd,
+ struct mmc_data *data)
+{
+ struct mmc *mmc = mmc_get_mmc_dev(dev);
+#else
static int ftsdc010_request(struct mmc *mmc, struct mmc_cmd *cmd,
struct mmc_data *data)
{
+#endif
int ret = -EOPNOTSUPP;
uint32_t len = 0;
struct ftsdc010_chip *chip = mmc->priv;
@@ -245,14 +242,20 @@ static int ftsdc010_request(struct mmc *mmc, struct mmc_cmd *cmd,
if (!ret) {
ret = ftsdc010_wait(regs,
- FTSDC010_STATUS_DATA_END | FTSDC010_STATUS_DATA_ERROR);
+ FTSDC010_STATUS_DATA_END | FTSDC010_STATUS_DATA_CRC_OK);
}
return ret;
}
+#ifdef CONFIG_DM_MMC
+static int ftsdc010_set_ios(struct udevice *dev)
+{
+ struct mmc *mmc = mmc_get_mmc_dev(dev);
+#else
static int ftsdc010_set_ios(struct mmc *mmc)
{
+#endif
struct ftsdc010_chip *chip = mmc->priv;
struct ftsdc010_mmc __iomem *regs = chip->regs;
@@ -274,20 +277,43 @@ static int ftsdc010_set_ios(struct mmc *mmc)
return 0;
}
-static int ftsdc010_init(struct mmc *mmc)
+#ifdef CONFIG_DM_MMC
+static int ftsdc010_get_cd(struct udevice *dev)
+{
+ struct mmc *mmc = mmc_get_mmc_dev(dev);
+#else
+static int ftsdc010_get_cd(struct mmc *mmc)
{
+#endif
struct ftsdc010_chip *chip = mmc->priv;
struct ftsdc010_mmc __iomem *regs = chip->regs;
- uint32_t ts;
-
- if (readl(&regs->status) & FTSDC010_STATUS_CARD_DETECT)
- return -ENOMEDIUM;
+ return !(readl(&regs->status) & FTSDC010_STATUS_CARD_DETECT);
+}
+#ifdef CONFIG_DM_MMC
+static int ftsdc010_get_wp(struct udevice *dev)
+{
+ struct mmc *mmc = mmc_get_mmc_dev(dev);
+#else
+static int ftsdc010_get_wp(struct mmc *mmc)
+{
+#endif
+ struct ftsdc010_chip *chip = mmc->priv;
+ struct ftsdc010_mmc __iomem *regs = chip->regs;
if (readl(&regs->status) & FTSDC010_STATUS_WRITE_PROT) {
printf("ftsdc010: write protected\n");
chip->wprot = 1;
}
+ return 0;
+}
+
+static int ftsdc010_init(struct mmc *mmc)
+{
+ struct ftsdc010_chip *chip = mmc->priv;
+ struct ftsdc010_mmc __iomem *regs = chip->regs;
+ uint32_t ts;
+
chip->fifo = (readl(&regs->feature) & 0xff) << 2;
/* 1. chip reset */
@@ -311,11 +337,69 @@ static int ftsdc010_init(struct mmc *mmc)
return 0;
}
+#ifdef CONFIG_DM_MMC
+int ftsdc010_probe(struct udevice *dev)
+{
+ struct mmc *mmc = mmc_get_mmc_dev(dev);
+ return ftsdc010_init(mmc);
+}
+
+const struct dm_mmc_ops dm_ftsdc010_ops = {
+ .send_cmd = ftsdc010_request,
+ .set_ios = ftsdc010_set_ios,
+ .get_cd = ftsdc010_get_cd,
+ .get_wp = ftsdc010_get_wp,
+};
+
+#else
static const struct mmc_ops ftsdc010_ops = {
.send_cmd = ftsdc010_request,
.set_ios = ftsdc010_set_ios,
+ .getcd = ftsdc010_get_cd,
+ .getwp = ftsdc010_get_wp,
.init = ftsdc010_init,
};
+#endif
+
+void ftsdc_setup_cfg(struct mmc_config *cfg, const char *name, int buswidth,
+ uint caps, u32 max_clk, u32 min_clk)
+{
+ cfg->name = name;
+ cfg->f_min = min_clk;
+ cfg->f_max = max_clk;
+ cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
+ cfg->host_caps = caps;
+ if (buswidth == 8) {
+ cfg->host_caps |= MMC_MODE_8BIT;
+ cfg->host_caps &= ~MMC_MODE_4BIT;
+ } else {
+ cfg->host_caps |= MMC_MODE_4BIT;
+ cfg->host_caps &= ~MMC_MODE_8BIT;
+ }
+ cfg->part_type = PART_TYPE_DOS;
+ cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
+}
+
+void set_bus_width(struct ftsdc010_mmc __iomem *regs, struct mmc_config *cfg)
+{
+ switch (readl(&regs->bwr) & FTSDC010_BWR_CAPS_MASK) {
+ case FTSDC010_BWR_CAPS_4BIT:
+ cfg->host_caps |= MMC_MODE_4BIT;
+ break;
+ case FTSDC010_BWR_CAPS_8BIT:
+ cfg->host_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
+ break;
+ default:
+ break;
+ }
+}
+
+#ifdef CONFIG_BLK
+int ftsdc010_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
+{
+ return mmc_bind(dev, mmc, cfg);
+}
+#else
int ftsdc010_mmc_init(int devid)
{
@@ -345,19 +429,11 @@ int ftsdc010_mmc_init(int devid)
#endif
chip->cfg.name = "ftsdc010";
+#ifndef CONFIG_DM_MMC
chip->cfg.ops = &ftsdc010_ops;
+#endif
chip->cfg.host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz;
- switch (readl(&regs->bwr) & FTSDC010_BWR_CAPS_MASK) {
- case FTSDC010_BWR_CAPS_4BIT:
- chip->cfg.host_caps |= MMC_MODE_4BIT;
- break;
- case FTSDC010_BWR_CAPS_8BIT:
- chip->cfg.host_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
- break;
- default:
- break;
- }
-
+ set_bus_width(regs , &chip->cfg);
chip->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
chip->cfg.f_max = chip->sclk / 2;
chip->cfg.f_min = chip->sclk / 0x100;
@@ -373,3 +449,4 @@ int ftsdc010_mmc_init(int devid)
return 0;
}
+#endif
diff --git a/drivers/mmc/ftsdc010_mci.h b/drivers/mmc/ftsdc010_mci.h
new file mode 100644
index 00000000000..31a27fd7728
--- /dev/null
+++ b/drivers/mmc/ftsdc010_mci.h
@@ -0,0 +1,53 @@
+/*
+ * Faraday FTSDC010 Secure Digital Memory Card Host Controller
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <mmc.h>
+
+#ifndef __FTSDC010_MCI_H
+#define __FTSDC010_MCI_H
+
+struct ftsdc010_chip {
+ void __iomem *regs;
+ uint32_t wprot; /* write protected (locked) */
+ uint32_t rate; /* actual SD clock in Hz */
+ uint32_t sclk; /* FTSDC010 source clock in Hz */
+ uint32_t fifo; /* fifo depth in bytes */
+ uint32_t acmd;
+ struct mmc_config cfg; /* mmc configuration */
+ const char *name;
+ void *ioaddr;
+ unsigned int caps;
+ unsigned int version;
+ unsigned int clock;
+ unsigned int bus_hz;
+ unsigned int div;
+ int dev_index;
+ int dev_id;
+ int buswidth;
+ u32 fifoth_val;
+ struct mmc *mmc;
+ void *priv;
+ bool fifo_mode;
+};
+
+
+#ifdef CONFIG_DM_MMC
+/* Export the operations to drivers */
+int ftsdc010_probe(struct udevice *dev);
+extern const struct dm_mmc_ops dm_ftsdc010_ops;
+#endif
+void ftsdc_setup_cfg(struct mmc_config *cfg, const char *name, int buswidth,
+ uint caps, u32 max_clk, u32 min_clk);
+void set_bus_width(struct ftsdc010_mmc __iomem *regs, struct mmc_config *cfg);
+
+#ifdef CONFIG_BLK
+int ftsdc010_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg);
+#endif
+
+
+#endif /* __FTSDC010_MCI_H */
diff --git a/drivers/mmc/nds32_mmc.c b/drivers/mmc/nds32_mmc.c
new file mode 100644
index 00000000000..6d3c8572e50
--- /dev/null
+++ b/drivers/mmc/nds32_mmc.c
@@ -0,0 +1,136 @@
+/*
+ * Andestech ATFSDC010 SD/MMC driver
+ *
+ * (C) Copyright 2017
+ * Rick Chen, NDS32 Software Engineering, rick@andestech.com
+
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <dt-structs.h>
+#include <errno.h>
+#include <mapmem.h>
+#include <mmc.h>
+#include <pwrseq.h>
+#include <syscon.h>
+#include <linux/err.h>
+#include <faraday/ftsdc010.h>
+#include "ftsdc010_mci.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+struct nds_mmc {
+ fdt32_t bus_width;
+ bool cap_mmc_highspeed;
+ bool cap_sd_highspeed;
+ fdt32_t clock_freq_min_max[2];
+ struct phandle_2_cell clocks[4];
+ fdt32_t fifo_depth;
+ fdt32_t reg[2];
+};
+#endif
+
+struct nds_mmc_plat {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+ struct nds_mmc dtplat;
+#endif
+ struct mmc_config cfg;
+ struct mmc mmc;
+};
+
+struct ftsdc_priv {
+ struct clk clk;
+ struct ftsdc010_chip chip;
+ int fifo_depth;
+ bool fifo_mode;
+ u32 minmax[2];
+};
+
+static int nds32_mmc_ofdata_to_platdata(struct udevice *dev)
+{
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+ struct ftsdc_priv *priv = dev_get_priv(dev);
+ struct ftsdc010_chip *chip = &priv->chip;
+ chip->name = dev->name;
+ chip->ioaddr = (void *)devfdt_get_addr(dev);
+ chip->buswidth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
+ "bus-width", 4);
+ chip->priv = dev;
+ priv->fifo_depth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
+ "fifo-depth", 0);
+ priv->fifo_mode = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
+ "fifo-mode");
+ if (fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev),
+ "clock-freq-min-max", priv->minmax, 2)) {
+ int val = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
+ "max-frequency", -EINVAL);
+ if (val < 0)
+ return val;
+
+ priv->minmax[0] = 400000; /* 400 kHz */
+ priv->minmax[1] = val;
+ } else {
+ debug("%s: 'clock-freq-min-max' property was deprecated.\n",
+ __func__);
+ }
+#endif
+ chip->sclk = priv->minmax[1];
+ chip->regs = chip->ioaddr;
+ return 0;
+}
+
+static int nds32_mmc_probe(struct udevice *dev)
+{
+ struct nds_mmc_plat *plat = dev_get_platdata(dev);
+ struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+ struct ftsdc_priv *priv = dev_get_priv(dev);
+ struct ftsdc010_chip *chip = &priv->chip;
+ struct udevice *pwr_dev __maybe_unused;
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+ int ret;
+ struct nds_mmc *dtplat = &plat->dtplat;
+ chip->name = dev->name;
+ chip->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
+ chip->buswidth = dtplat->bus_width;
+ chip->priv = dev;
+ chip->dev_index = 1;
+ memcpy(priv->minmax, dtplat->clock_freq_min_max, sizeof(priv->minmax));
+ ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->clk);
+ if (ret < 0)
+ return ret;
+#endif
+ ftsdc_setup_cfg(&plat->cfg, dev->name, chip->buswidth, chip->caps,
+ priv->minmax[1] , priv->minmax[0]);
+ chip->mmc = &plat->mmc;
+ chip->mmc->priv = &priv->chip;
+ chip->mmc->dev = dev;
+ upriv->mmc = chip->mmc;
+ return ftsdc010_probe(dev);
+}
+
+static int nds32_mmc_bind(struct udevice *dev)
+{
+ struct nds_mmc_plat *plat = dev_get_platdata(dev);
+ return ftsdc010_bind(dev, &plat->mmc, &plat->cfg);
+}
+
+static const struct udevice_id nds32_mmc_ids[] = {
+ { .compatible = "andestech,atsdc010" },
+ { }
+};
+
+U_BOOT_DRIVER(nds32_mmc_drv) = {
+ .name = "nds32_mmc",
+ .id = UCLASS_MMC,
+ .of_match = nds32_mmc_ids,
+ .ofdata_to_platdata = nds32_mmc_ofdata_to_platdata,
+ .ops = &dm_ftsdc010_ops,
+ .bind = nds32_mmc_bind,
+ .probe = nds32_mmc_probe,
+ .priv_auto_alloc_size = sizeof(struct ftsdc_priv),
+ .platdata_auto_alloc_size = sizeof(struct nds_mmc_plat),
+};
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 88da9a4c8e7..494639fb019 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -210,12 +210,12 @@ config FSL_QSPI
used to access the SPI NOR flash on platforms embedding this
Freescale IP core.
-config NDS_AE3XX_SPI
- bool "Andestech AE3XX SPI driver"
+config ATCSPI200_SPI
+ bool "Andestech ATCSPI200 SPI driver"
help
- Enable the Andestech AE3XX SPI driver. This driver can be
- used to access the SPI flash on platforms embedding this
- Andestech IP core.
+ Enable the Andestech ATCSPI200 SPI driver. This driver can be
+ used to access the SPI flash on AE3XX and AE250 platforms embedding
+ this Andestech IP core.
config TI_QSPI
bool "TI QSPI driver"
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index ad56203cd6f..e3184db67f5 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -34,7 +34,7 @@ obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o
obj-$(CONFIG_MXC_SPI) += mxc_spi.o
obj-$(CONFIG_MXS_SPI) += mxs_spi.o
-obj-$(CONFIG_NDS_AE3XX_SPI) += nds_ae3xx_spi.o
+obj-$(CONFIG_ATCSPI200_SPI) += atcspi200_spi.o
obj-$(CONFIG_OMAP3_SPI) += omap3_spi.o
obj-$(CONFIG_PIC32_SPI) += pic32_spi.o
obj-$(CONFIG_ROCKCHIP_SPI) += rk_spi.o
diff --git a/drivers/spi/nds_ae3xx_spi.c b/drivers/spi/atcspi200_spi.c
index f5bd99a605b..3e29df03a4d 100644
--- a/drivers/spi/nds_ae3xx_spi.c
+++ b/drivers/spi/atcspi200_spi.c
@@ -1,5 +1,5 @@
/*
- * NDS SPI controller driver.
+ * Andestech ATCSPI200 SPI controller driver.
*
* Copyright 2017 Andes Technology, Inc.
* Author: Rick Chen (rick@andestech.com)
@@ -25,7 +25,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define SPI1_BASE 0xf0f00000
#define NSPI_MAX_CS_NUM 1
-struct ae3xx_spi_regs {
+struct atcspi200_spi_regs {
u32 rev;
u32 reserve1[3];
u32 format; /* 0x10 */
@@ -78,7 +78,7 @@ struct nds_spi_slave {
#ifndef CONFIG_DM_SPI
struct spi_slave slave;
#endif
- volatile struct ae3xx_spi_regs *regs;
+ volatile struct atcspi200_spi_regs *regs;
int to;
unsigned int freq;
ulong clock;
@@ -94,7 +94,7 @@ struct nds_spi_slave {
unsigned int max_transfer_length;
};
-static int __ae3xx_spi_set_speed(struct nds_spi_slave *ns)
+static int __atcspi200_spi_set_speed(struct nds_spi_slave *ns)
{
u32 tm;
u8 div;
@@ -117,7 +117,7 @@ static int __ae3xx_spi_set_speed(struct nds_spi_slave *ns)
}
-static int __ae3xx_spi_claim_bus(struct nds_spi_slave *ns)
+static int __atcspi200_spi_claim_bus(struct nds_spi_slave *ns)
{
unsigned int format=0;
ns->regs->ctrl |= (TXFRST|RXFRST|SPIRST);
@@ -128,18 +128,18 @@ static int __ae3xx_spi_claim_bus(struct nds_spi_slave *ns)
ns->cmd_len = 0;
format = ns->mode|DATA_LENGTH(8);
ns->regs->format = format;
- __ae3xx_spi_set_speed(ns);
+ __atcspi200_spi_set_speed(ns);
return 0;
}
-static int __ae3xx_spi_release_bus(struct nds_spi_slave *ns)
+static int __atcspi200_spi_release_bus(struct nds_spi_slave *ns)
{
/* do nothing */
return 0;
}
-static int __ae3xx_spi_start(struct nds_spi_slave *ns)
+static int __atcspi200_spi_start(struct nds_spi_slave *ns)
{
int i,olen=0;
int tc = ns->regs->tctrl;
@@ -168,7 +168,7 @@ static int __ae3xx_spi_start(struct nds_spi_slave *ns)
return 0;
}
-static int __ae3xx_spi_stop(struct nds_spi_slave *ns)
+static int __atcspi200_spi_stop(struct nds_spi_slave *ns)
{
ns->regs->timing = ns->mtiming;
while ((ns->regs->status & SPIBSY)&&(ns->to--))
@@ -190,7 +190,7 @@ static int __nspi_espi_rx(struct nds_spi_slave *ns, void *din, unsigned int byte
}
-static int __ae3xx_spi_xfer(struct nds_spi_slave *ns,
+static int __atcspi200_spi_xfer(struct nds_spi_slave *ns,
unsigned int bitlen, const void *data_out, void *data_in,
unsigned long flags)
{
@@ -230,7 +230,7 @@ static int __ae3xx_spi_xfer(struct nds_spi_slave *ns,
memcpy(cmd_buf, data_out, cmd_len);
data_out = 0;
data_len = 0;
- __ae3xx_spi_start(ns);
+ __atcspi200_spi_start(ns);
break;
}
debug("spi_xfer: data_out %08X(%p) data_in %08X(%p) data_len %u\n",
@@ -245,7 +245,7 @@ static int __ae3xx_spi_xfer(struct nds_spi_slave *ns,
num_bytes = (tran_len) % CHUNK_SIZE;
if(num_bytes == 0)
num_bytes = CHUNK_SIZE;
- __ae3xx_spi_start(ns);
+ __atcspi200_spi_start(ns);
while (num_blks) {
event = in_le32(&ns->regs->status);
@@ -279,9 +279,9 @@ static int __ae3xx_spi_xfer(struct nds_spi_slave *ns,
ns->cmd_buf[3] += ((tran_len)&0xff);
ns->data_len = data_len;
}
- ret = __ae3xx_spi_stop(ns);
+ ret = __atcspi200_spi_stop(ns);
}
- ret = __ae3xx_spi_stop(ns);
+ ret = __atcspi200_spi_stop(ns);
return ret;
}
@@ -300,11 +300,11 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
switch (bus) {
case SPI0_BUS:
- ns->regs = (struct ae3xx_spi_regs *)SPI0_BASE;
+ ns->regs = (struct atcspi200_spi_regs *)SPI0_BASE;
break;
case SPI1_BUS:
- ns->regs = (struct ae3xx_spi_regs *)SPI1_BASE;
+ ns->regs = (struct atcspi200_spi_regs *)SPI1_BASE;
break;
default:
@@ -336,20 +336,20 @@ void spi_init(void)
int spi_claim_bus(struct spi_slave *slave)
{
struct nds_spi_slave *ns = to_nds_spi_slave(slave);
- return __ae3xx_spi_claim_bus(ns);
+ return __atcspi200_spi_claim_bus(ns);
}
void spi_release_bus(struct spi_slave *slave)
{
struct nds_spi_slave *ns = to_nds_spi_slave(slave);
- __ae3xx_spi_release_bus(ns);
+ __atcspi200_spi_release_bus(ns);
}
int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out,
void *data_in, unsigned long flags)
{
struct nds_spi_slave *ns = to_nds_spi_slave(slave);
- return __ae3xx_spi_xfer(ns, bitlen, data_out, data_in, flags);
+ return __atcspi200_spi_xfer(ns, bitlen, data_out, data_in, flags);
}
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
@@ -360,28 +360,28 @@ int spi_cs_is_valid(unsigned int bus, unsigned int cs)
void spi_cs_activate(struct spi_slave *slave)
{
struct nds_spi_slave *ns = to_nds_spi_slave(slave);
- __ae3xx_spi_start(ns);
+ __atcspi200_spi_start(ns);
}
void spi_cs_deactivate(struct spi_slave *slave)
{
struct nds_spi_slave *ns = to_nds_spi_slave(slave);
- __ae3xx_spi_stop(ns);
+ __atcspi200_spi_stop(ns);
}
#else
-static int ae3xx_spi_set_speed(struct udevice *bus, uint max_hz)
+static int atcspi200_spi_set_speed(struct udevice *bus, uint max_hz)
{
struct nds_spi_slave *ns = dev_get_priv(bus);
debug("%s speed %u\n", __func__, max_hz);
ns->freq = max_hz;
- __ae3xx_spi_set_speed(ns);
+ __atcspi200_spi_set_speed(ns);
return 0;
}
-static int ae3xx_spi_set_mode(struct udevice *bus, uint mode)
+static int atcspi200_spi_set_mode(struct udevice *bus, uint mode)
{
struct nds_spi_slave *ns = dev_get_priv(bus);
@@ -391,7 +391,7 @@ static int ae3xx_spi_set_mode(struct udevice *bus, uint mode)
return 0;
}
-static int ae3xx_spi_claim_bus(struct udevice *dev)
+static int atcspi200_spi_claim_bus(struct udevice *dev)
{
struct dm_spi_slave_platdata *slave_plat =
dev_get_parent_platdata(dev);
@@ -403,27 +403,27 @@ static int ae3xx_spi_claim_bus(struct udevice *dev)
return -EINVAL;
}
- return __ae3xx_spi_claim_bus(ns);
+ return __atcspi200_spi_claim_bus(ns);
}
-static int ae3xx_spi_release_bus(struct udevice *dev)
+static int atcspi200_spi_release_bus(struct udevice *dev)
{
struct nds_spi_slave *ns = dev_get_priv(dev->parent);
- return __ae3xx_spi_release_bus(ns);
+ return __atcspi200_spi_release_bus(ns);
}
-static int ae3xx_spi_xfer(struct udevice *dev, unsigned int bitlen,
+static int atcspi200_spi_xfer(struct udevice *dev, unsigned int bitlen,
const void *dout, void *din,
unsigned long flags)
{
struct udevice *bus = dev->parent;
struct nds_spi_slave *ns = dev_get_priv(bus);
- return __ae3xx_spi_xfer(ns, bitlen, dout, din, flags);
+ return __atcspi200_spi_xfer(ns, bitlen, dout, din, flags);
}
-static int ae3xx_spi_get_clk(struct udevice *bus)
+static int atcspi200_spi_get_clk(struct udevice *bus)
{
struct nds_spi_slave *ns = dev_get_priv(bus);
struct clk clk;
@@ -444,26 +444,26 @@ static int ae3xx_spi_get_clk(struct udevice *bus)
return 0;
}
-static int ae3xx_spi_probe(struct udevice *bus)
+static int atcspi200_spi_probe(struct udevice *bus)
{
struct nds_spi_slave *ns = dev_get_priv(bus);
ns->to = SPI_TIMEOUT;
ns->max_transfer_length = MAX_TRANSFER_LEN;
ns->mtiming = ns->regs->timing;
- ae3xx_spi_get_clk(bus);
+ atcspi200_spi_get_clk(bus);
return 0;
}
-static int ae3xx_ofdata_to_platadata(struct udevice *bus)
+static int atcspi200_ofdata_to_platadata(struct udevice *bus)
{
struct nds_spi_slave *ns = dev_get_priv(bus);
const void *blob = gd->fdt_blob;
int node = dev_of_offset(bus);
ns->regs = map_physmem(devfdt_get_addr(bus),
- sizeof(struct ae3xx_spi_regs),
+ sizeof(struct atcspi200_spi_regs),
MAP_NOCACHE);
if (!ns->regs) {
printf("%s: could not map device address\n", __func__);
@@ -474,26 +474,26 @@ static int ae3xx_ofdata_to_platadata(struct udevice *bus)
return 0;
}
-static const struct dm_spi_ops ae3xx_spi_ops = {
- .claim_bus = ae3xx_spi_claim_bus,
- .release_bus = ae3xx_spi_release_bus,
- .xfer = ae3xx_spi_xfer,
- .set_speed = ae3xx_spi_set_speed,
- .set_mode = ae3xx_spi_set_mode,
+static const struct dm_spi_ops atcspi200_spi_ops = {
+ .claim_bus = atcspi200_spi_claim_bus,
+ .release_bus = atcspi200_spi_release_bus,
+ .xfer = atcspi200_spi_xfer,
+ .set_speed = atcspi200_spi_set_speed,
+ .set_mode = atcspi200_spi_set_mode,
};
-static const struct udevice_id ae3xx_spi_ids[] = {
+static const struct udevice_id atcspi200_spi_ids[] = {
{ .compatible = "andestech,atcspi200" },
{ }
};
-U_BOOT_DRIVER(ae3xx_spi) = {
- .name = "ae3xx_spi",
+U_BOOT_DRIVER(atcspi200_spi) = {
+ .name = "atcspi200_spi",
.id = UCLASS_SPI,
- .of_match = ae3xx_spi_ids,
- .ops = &ae3xx_spi_ops,
- .ofdata_to_platdata = ae3xx_ofdata_to_platadata,
+ .of_match = atcspi200_spi_ids,
+ .ops = &atcspi200_spi_ops,
+ .ofdata_to_platdata = atcspi200_ofdata_to_platadata,
.priv_auto_alloc_size = sizeof(struct nds_spi_slave),
- .probe = ae3xx_spi_probe,
+ .probe = atcspi200_spi_probe,
};
#endif
diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index 6305bbf01cd..3a1f8311c12 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -105,11 +105,12 @@ config AG101P_TIMER
help
Select this to enable a timer for AG01P devices.
-config AE3XX_TIMER
- bool "AE3XX timer support"
- depends on TIMER && NDS32
+config ATCPIT100_TIMER
+ bool "ATCPIT100 timer support"
+ depends on TIMER
help
- Select this to enable a timer for AE3XX devices.
+ Select this to enable a ATCPIT100 timer which will be embeded
+ in AE3XX, AE250 boards.
config ROCKCHIP_TIMER
bool "Rockchip timer support"
diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
index 69e8961a7ba..15e515407e3 100644
--- a/drivers/timer/Makefile
+++ b/drivers/timer/Makefile
@@ -13,6 +13,6 @@ obj-$(CONFIG_AST_TIMER) += ast_timer.o
obj-$(CONFIG_STI_TIMER) += sti-timer.o
obj-$(CONFIG_ARC_TIMER) += arc_timer.o
obj-$(CONFIG_AG101P_TIMER) += ag101p_timer.o
-obj-$(CONFIG_AE3XX_TIMER) += ae3xx_timer.o
+obj-$(CONFIG_ATCPIT100_TIMER) += atcpit100_timer.o
obj-$(CONFIG_ROCKCHIP_TIMER) += rockchip_timer.o
obj-$(CONFIG_ATMEL_PIT_TIMER) += atmel_pit_timer.o
diff --git a/drivers/timer/ae3xx_timer.c b/drivers/timer/atcpit100_timer.c
index bcc07a0c864..963f978d206 100644
--- a/drivers/timer/ae3xx_timer.c
+++ b/drivers/timer/atcpit100_timer.c
@@ -14,7 +14,7 @@
DECLARE_GLOBAL_DATA_PTR;
-#define REG32_TMR(x) (*(unsigned long *) ((plat->regs) + (x>>2)))
+#define REG32_TMR(x) (*(u32 *) ((plat->regs) + (x>>2)))
/*
* Definition of register offsets
@@ -67,51 +67,51 @@ struct atctmr_timer_regs {
u32 int_mask; /* 0x38 */
};
-struct atftmr_timer_platdata {
- unsigned long *regs;
+struct atcpit_timer_platdata {
+ u32 *regs;
};
-static int atftmr_timer_get_count(struct udevice *dev, u64 *count)
+static int atcpit_timer_get_count(struct udevice *dev, u64 *count)
{
- struct atftmr_timer_platdata *plat = dev->platdata;
+ struct atcpit_timer_platdata *plat = dev_get_platdata(dev);
u32 val;
val = ~(REG32_TMR(CH_CNT(1))+0xffffffff);
*count = timer_conv_64(val);
return 0;
}
-static int atctmr_timer_probe(struct udevice *dev)
+static int atcpit_timer_probe(struct udevice *dev)
{
- struct atftmr_timer_platdata *plat = dev->platdata;
+ struct atcpit_timer_platdata *plat = dev_get_platdata(dev);
REG32_TMR(CH_REL(1)) = 0xffffffff;
REG32_TMR(CH_CTL(1)) = APB_CLK|TMR_32;
REG32_TMR(CH_EN) |= CH_TMR_EN(1 , 0);
return 0;
}
-static int atctme_timer_ofdata_to_platdata(struct udevice *dev)
+static int atcpit_timer_ofdata_to_platdata(struct udevice *dev)
{
- struct atftmr_timer_platdata *plat = dev_get_platdata(dev);
+ struct atcpit_timer_platdata *plat = dev_get_platdata(dev);
plat->regs = map_physmem(devfdt_get_addr(dev) , 0x100 , MAP_NOCACHE);
return 0;
}
-static const struct timer_ops ag101p_timer_ops = {
- .get_count = atftmr_timer_get_count,
+static const struct timer_ops atcpit_timer_ops = {
+ .get_count = atcpit_timer_get_count,
};
-static const struct udevice_id ag101p_timer_ids[] = {
+static const struct udevice_id atcpit_timer_ids[] = {
{ .compatible = "andestech,atcpit100" },
{}
};
-U_BOOT_DRIVER(altera_timer) = {
- .name = "ae3xx_timer",
+U_BOOT_DRIVER(atcpit100_timer) = {
+ .name = "atcpit100_timer",
.id = UCLASS_TIMER,
- .of_match = ag101p_timer_ids,
- .ofdata_to_platdata = atctme_timer_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct atftmr_timer_platdata),
- .probe = atctmr_timer_probe,
- .ops = &ag101p_timer_ops,
+ .of_match = atcpit_timer_ids,
+ .ofdata_to_platdata = atcpit_timer_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct atcpit_timer_platdata),
+ .probe = atcpit_timer_probe,
+ .ops = &atcpit_timer_ops,
.flags = DM_FLAG_PRE_RELOC,
};
generated by cgit v1.2.3 (git 2.0.4) at 2025-09-23 04:02:54 +0000