diff options
Diffstat (limited to 'drivers')
83 files changed, 6247 insertions, 61 deletions
diff --git a/drivers/Makefile b/drivers/Makefile index 5e3b1227692..8c53e05d2f5 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -34,6 +34,7 @@ obj-$(CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT) += ddr/fsl/ obj-$(CONFIG_ARMADA_38X) += ddr/marvell/a38x/ obj-$(CONFIG_ARMADA_XP) += ddr/marvell/axp/ obj-$(CONFIG_ALTERA_SDRAM) += ddr/altera/ +obj-$(CONFIG_ARCH_IMX8M) += ddr/imx/imx8m/ obj-$(CONFIG_SPL_POWER_SUPPORT) += power/ power/pmic/ obj-$(CONFIG_SPL_POWER_SUPPORT) += power/regulator/ obj-$(CONFIG_SPL_POWER_DOMAIN) += power/domain/ diff --git a/drivers/clk/uniphier/clk-uniphier-sys.c b/drivers/clk/uniphier/clk-uniphier-sys.c index 9e087b6bd28..487b43ebdab 100644 --- a/drivers/clk/uniphier/clk-uniphier-sys.c +++ b/drivers/clk/uniphier/clk-uniphier-sys.c @@ -6,13 +6,12 @@ #include "clk-uniphier.h" -/* Denali driver requires clk_x rate (clk: 50MHz, clk_x & ecc_clk: 200MHz) */ #define UNIPHIER_LD4_SYS_CLK_NAND(_id) \ - UNIPHIER_CLK_RATE(128, 200000000), \ + UNIPHIER_CLK_RATE(128, 50000000), \ UNIPHIER_CLK_GATE((_id), 128, 0x2104, 2) #define UNIPHIER_LD11_SYS_CLK_NAND(_id) \ - UNIPHIER_CLK_RATE(128, 200000000), \ + UNIPHIER_CLK_RATE(128, 50000000), \ UNIPHIER_CLK_GATE((_id), 128, 0x210c, 0) const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = { @@ -20,6 +19,7 @@ const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = { defined(CONFIG_ARCH_UNIPHIER_PRO4) || defined(CONFIG_ARCH_UNIPHIER_PRO5) ||\ defined(CONFIG_ARCH_UNIPHIER_PXS2) || defined(CONFIG_ARCH_UNIPHIER_LD6B) UNIPHIER_LD4_SYS_CLK_NAND(2), + UNIPHIER_CLK_RATE(3, 200000000), UNIPHIER_CLK_GATE_SIMPLE(6, 0x2104, 12), /* ether (Pro4, PXs2) */ UNIPHIER_CLK_GATE_SIMPLE(7, 0x2104, 5), /* ether-gb (Pro4) */ UNIPHIER_CLK_GATE_SIMPLE(8, 0x2104, 10), /* stdmac */ @@ -36,6 +36,7 @@ const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = { const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = { #if defined(CONFIG_ARCH_UNIPHIER_LD11) || defined(CONFIG_ARCH_UNIPHIER_LD20) UNIPHIER_LD11_SYS_CLK_NAND(2), + UNIPHIER_CLK_RATE(3, 200000000), UNIPHIER_CLK_GATE_SIMPLE(6, 0x210c, 6), /* ether */ UNIPHIER_CLK_GATE_SIMPLE(8, 0x210c, 8), /* stdmac */ UNIPHIER_CLK_GATE_SIMPLE(14, 0x210c, 14), /* usb30 (LD20) */ @@ -48,6 +49,7 @@ const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = { const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[] = { #if defined(CONFIG_ARCH_UNIPHIER_PXS3) UNIPHIER_LD11_SYS_CLK_NAND(2), + UNIPHIER_CLK_RATE(3, 200000000), UNIPHIER_CLK_GATE_SIMPLE(6, 0x210c, 9), /* ether0 */ UNIPHIER_CLK_GATE_SIMPLE(7, 0x210c, 10), /* ether1 */ UNIPHIER_CLK_GATE_SIMPLE(12, 0x210c, 4), /* usb30 (gio0) */ diff --git a/drivers/cpu/Kconfig b/drivers/cpu/Kconfig index d4052005e24..3d5729f6dca 100644 --- a/drivers/cpu/Kconfig +++ b/drivers/cpu/Kconfig @@ -13,3 +13,9 @@ config CPU_MPC83XX select CLK_MPC83XX help Support CPU cores for SoCs of the MPC83xx series. + +config CPU_RISCV + bool "Enable RISC-V CPU driver" + depends on CPU && RISCV + help + Support CPU cores for RISC-V architecture. diff --git a/drivers/cpu/Makefile b/drivers/cpu/Makefile index 858b03755f5..be0300cd4a8 100644 --- a/drivers/cpu/Makefile +++ b/drivers/cpu/Makefile @@ -8,4 +8,5 @@ obj-$(CONFIG_CPU) += cpu-uclass.o obj-$(CONFIG_ARCH_BMIPS) += bmips_cpu.o obj-$(CONFIG_CPU_MPC83XX) += mpc83xx_cpu.o +obj-$(CONFIG_CPU_RISCV) += riscv_cpu.o obj-$(CONFIG_SANDBOX) += cpu_sandbox.o diff --git a/drivers/cpu/riscv_cpu.c b/drivers/cpu/riscv_cpu.c new file mode 100644 index 00000000000..5e15df590e4 --- /dev/null +++ b/drivers/cpu/riscv_cpu.c @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com> + */ + +#include <common.h> +#include <cpu.h> +#include <dm.h> +#include <errno.h> +#include <dm/device-internal.h> +#include <dm/lists.h> + +static int riscv_cpu_get_desc(struct udevice *dev, char *buf, int size) +{ + const char *isa; + + isa = dev_read_string(dev, "riscv,isa"); + if (size < (strlen(isa) + 1)) + return -ENOSPC; + + strcpy(buf, isa); + + return 0; +} + +static int riscv_cpu_get_info(struct udevice *dev, struct cpu_info *info) +{ + const char *mmu; + + dev_read_u32(dev, "clock-frequency", (u32 *)&info->cpu_freq); + + mmu = dev_read_string(dev, "mmu-type"); + if (!mmu) + info->features |= BIT(CPU_FEAT_MMU); + + return 0; +} + +static int riscv_cpu_get_count(struct udevice *dev) +{ + ofnode node; + int num = 0; + + ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) { + const char *device_type; + + device_type = ofnode_read_string(node, "device_type"); + if (!device_type) + continue; + if (strcmp(device_type, "cpu") == 0) + num++; + } + + return num; +} + +static int riscv_cpu_bind(struct udevice *dev) +{ + struct cpu_platdata *plat = dev_get_parent_platdata(dev); + struct driver *drv; + int ret; + + /* save the hart id */ + plat->cpu_id = dev_read_addr(dev); + + /* first examine the property in current cpu node */ + ret = dev_read_u32(dev, "timebase-frequency", &plat->timebase_freq); + /* if not found, then look at the parent /cpus node */ + if (ret) + dev_read_u32(dev->parent, "timebase-frequency", + &plat->timebase_freq); + + /* + * Bind riscv-timer driver on hart 0 + * + * We only instantiate one timer device which is enough for U-Boot. + * Pass the "timebase-frequency" value as the driver data for the + * timer device. + * + * Return value is not checked since it's possible that the timer + * driver is not included. + */ + if (!plat->cpu_id && plat->timebase_freq) { + drv = lists_driver_lookup_name("riscv_timer"); + if (!drv) { + debug("Cannot find the timer driver, not included?\n"); + return 0; + } + + device_bind_with_driver_data(dev, drv, "riscv_timer", + plat->timebase_freq, ofnode_null(), + NULL); + } + + return 0; +} + +static const struct cpu_ops riscv_cpu_ops = { + .get_desc = riscv_cpu_get_desc, + .get_info = riscv_cpu_get_info, + .get_count = riscv_cpu_get_count, +}; + +static const struct udevice_id riscv_cpu_ids[] = { + { .compatible = "riscv" }, + { } +}; + +U_BOOT_DRIVER(riscv_cpu) = { + .name = "riscv_cpu", + .id = UCLASS_CPU, + .of_match = riscv_cpu_ids, + .bind = riscv_cpu_bind, + .ops = &riscv_cpu_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/ddr/Kconfig b/drivers/ddr/Kconfig index b764add060e..d4b393d25e0 100644 --- a/drivers/ddr/Kconfig +++ b/drivers/ddr/Kconfig @@ -1 +1,2 @@ source "drivers/ddr/altera/Kconfig" +source "drivers/ddr/imx/Kconfig" diff --git a/drivers/ddr/imx/Kconfig b/drivers/ddr/imx/Kconfig new file mode 100644 index 00000000000..7e06fb2f7d2 --- /dev/null +++ b/drivers/ddr/imx/Kconfig @@ -0,0 +1 @@ +source "drivers/ddr/imx/imx8m/Kconfig" diff --git a/drivers/ddr/imx/imx8m/Kconfig b/drivers/ddr/imx/imx8m/Kconfig new file mode 100644 index 00000000000..71f466f5ec3 --- /dev/null +++ b/drivers/ddr/imx/imx8m/Kconfig @@ -0,0 +1,22 @@ +config IMX8M_DRAM + bool "imx8m dram" + +config IMX8M_LPDDR4 + bool "imx8m lpddr4" + select IMX8M_DRAM + help + Select the i.MX8M LPDDR4 driver support on i.MX8M SOC. + +config IMX8M_DDR4 + bool "imx8m ddr4" + select IMX8M_DRAM + help + Select the i.MX8M DDR4 driver support on i.MX8M SOC. + +config SAVED_DRAM_TIMING_BASE + hex "Define the base address for saved dram timing" + help + after DRAM is trained, need to save the dram related timming + info into memory for low power use. OCRAM_S is used for this + purpose on i.MX8MM. + default 0x180000 diff --git a/drivers/ddr/imx/imx8m/Makefile b/drivers/ddr/imx/imx8m/Makefile new file mode 100644 index 00000000000..64f9ab20e6d --- /dev/null +++ b/drivers/ddr/imx/imx8m/Makefile @@ -0,0 +1,11 @@ +# +# Copyright 2018 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifdef CONFIG_SPL_BUILD +obj-$(CONFIG_IMX8M_DRAM) += helper.o ddrphy_utils.o ddrphy_train.o ddrphy_csr.o +obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_init.o +obj-$(CONFIG_IMX8M_DDR4) += ddr4_init.o +endif diff --git a/drivers/ddr/imx/imx8m/ddr4_init.c b/drivers/ddr/imx/imx8m/ddr4_init.c new file mode 100644 index 00000000000..031cdc57e16 --- /dev/null +++ b/drivers/ddr/imx/imx8m/ddr4_init.c @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include <common.h> +#include <errno.h> +#include <asm/io.h> +#include <asm/arch/ddr.h> +#include <asm/arch/clock.h> +#include <asm/arch/imx8m_ddr.h> +#include <asm/arch/sys_proto.h> + +void ddr4_cfg_umctl2(struct dram_cfg_param *ddrc_cfg, int num) +{ + int i = 0; + + for (i = 0; i < num; i++) { + reg32_write(ddrc_cfg->reg, ddrc_cfg->val); + ddrc_cfg++; + } +} + +void ddr_init(struct dram_timing_info *dram_timing) +{ + volatile unsigned int tmp_t; + /* + * assert [0]ddr1_preset_n, [1]ddr1_core_reset_n, + * [2]ddr1_phy_reset, [3]ddr1_phy_pwrokin_n, + * [4]src_system_rst_b! + */ + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00003F); + /* deassert [4]src_system_rst_b! */ + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00000F); + + /* + * change the clock source of dram_apb_clk_root + * to source 4 --800MHz/4 + */ + clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | + CLK_ROOT_SOURCE_SEL(4) | + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV4)); + + dram_pll_init(DRAM_PLL_OUT_600M); + + reg32_write(0x303A00EC, 0x0000ffff); /* PGC_CPU_MAPPING */ + reg32setbit(0x303A00F8, 5); /* PU_PGC_SW_PUP_REQ */ + + /* release [0]ddr1_preset_n, [3]ddr1_phy_pwrokin_n */ + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000006); + + reg32_write(DDRC_DBG1(0), 0x00000001); + reg32_write(DDRC_PWRCTL(0), 0x00000001); + + while (0 != (0x7 & reg32_read(DDRC_STAT(0)))) + ; + + /* config the uMCTL2's registers */ + ddr4_cfg_umctl2(dram_timing->ddrc_cfg, dram_timing->ddrc_cfg_num); + + reg32_write(DDRC_RFSHCTL3(0), 0x00000001); + /* RESET: <ctn> DEASSERTED */ + /* RESET: <a Port 0 DEASSERTED(0) */ + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000004); + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000000); + + reg32_write(DDRC_DBG1(0), 0x00000000); + reg32_write(DDRC_PWRCTL(0), 0x00000aa); + reg32_write(DDRC_SWCTL(0), 0x00000000); + + reg32_write(DDRC_DFIMISC(0), 0x00000000); + + /* config the DDR PHY's registers */ + ddr_cfg_phy(dram_timing); + + do { + tmp_t = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + + 4 * 0x00020097); + } while (tmp_t != 0); + + reg32_write(DDRC_DFIMISC(0), 0x00000020); + + /* wait DFISTAT.dfi_init_complete to 1 */ + while (0 == (0x1 & reg32_read(DDRC_DFISTAT(0)))) + ; + + /* clear DFIMISC.dfi_init_complete_en */ + reg32_write(DDRC_DFIMISC(0), 0x00000000); + /* set DFIMISC.dfi_init_complete_en again */ + reg32_write(DDRC_DFIMISC(0), 0x00000001); + reg32_write(DDRC_PWRCTL(0), 0x0000088); + + /* + * set SWCTL.sw_done to enable quasi-dynamic register + * programming outside reset. + */ + reg32_write(DDRC_SWCTL(0), 0x00000001); + /* wait SWSTAT.sw_done_ack to 1 */ + while (0 == (0x1 & reg32_read(DDRC_SWSTAT(0)))) + ; + + /* wait STAT to normal state */ + while (0x1 != (0x7 & reg32_read(DDRC_STAT(0)))) + ; + + reg32_write(DDRC_PWRCTL(0), 0x0000088); + reg32_write(DDRC_PCTRL_0(0), 0x00000001); + /* dis_auto-refresh is set to 0 */ + reg32_write(DDRC_RFSHCTL3(0), 0x00000000); + + /* save the dram timing config into memory */ + dram_config_save(dram_timing, CONFIG_SAVED_DRAM_TIMING_BASE); +} diff --git a/drivers/ddr/imx/imx8m/ddrphy_csr.c b/drivers/ddr/imx/imx8m/ddrphy_csr.c new file mode 100644 index 00000000000..67dd4e7059f --- /dev/null +++ b/drivers/ddr/imx/imx8m/ddrphy_csr.c @@ -0,0 +1,732 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include <linux/kernel.h> +#include <asm/arch/ddr.h> + +/* ddr phy trained csr */ +struct dram_cfg_param ddrphy_trained_csr[] = { + { 0x200b2, 0x0 }, + { 0x1200b2, 0x0 }, + { 0x2200b2, 0x0 }, + { 0x200cb, 0x0 }, + { 0x10043, 0x0 }, + { 0x110043, 0x0 }, + { 0x210043, 0x0 }, + { 0x10143, 0x0 }, + { 0x110143, 0x0 }, + { 0x210143, 0x0 }, + { 0x11043, 0x0 }, + { 0x111043, 0x0 }, + { 0x211043, 0x0 }, + { 0x11143, 0x0 }, + { 0x111143, 0x0 }, + { 0x211143, 0x0 }, + { 0x12043, 0x0 }, + { 0x112043, 0x0 }, + { 0x212043, 0x0 }, + { 0x12143, 0x0 }, + { 0x112143, 0x0 }, + { 0x212143, 0x0 }, + { 0x13043, 0x0 }, + { 0x113043, 0x0 }, + { 0x213043, 0x0 }, + { 0x13143, 0x0 }, + { 0x113143, 0x0 }, + { 0x213143, 0x0 }, + { 0x80, 0x0 }, + { 0x100080, 0x0 }, + { 0x200080, 0x0 }, + { 0x1080, 0x0 }, + { 0x101080, 0x0 }, + { 0x201080, 0x0 }, + { 0x2080, 0x0 }, + { 0x102080, 0x0 }, + { 0x202080, 0x0 }, + { 0x3080, 0x0 }, + { 0x103080, 0x0 }, + { 0x203080, 0x0 }, + { 0x4080, 0x0 }, + { 0x104080, 0x0 }, + { 0x204080, 0x0 }, + { 0x5080, 0x0 }, + { 0x105080, 0x0 }, + { 0x205080, 0x0 }, + { 0x6080, 0x0 }, + { 0x106080, 0x0 }, + { 0x206080, 0x0 }, + { 0x7080, 0x0 }, + { 0x107080, 0x0 }, + { 0x207080, 0x0 }, + { 0x8080, 0x0 }, + { 0x108080, 0x0 }, + { 0x208080, 0x0 }, + { 0x9080, 0x0 }, + { 0x109080, 0x0 }, + { 0x209080, 0x0 }, + { 0x10080, 0x0 }, + { 0x110080, 0x0 }, + { 0x210080, 0x0 }, + { 0x10180, 0x0 }, + { 0x110180, 0x0 }, + { 0x210180, 0x0 }, + { 0x11080, 0x0 }, + { 0x111080, 0x0 }, + { 0x211080, 0x0 }, + { 0x11180, 0x0 }, + { 0x111180, 0x0 }, + { 0x211180, 0x0 }, + { 0x12080, 0x0 }, + { 0x112080, 0x0 }, + { 0x212080, 0x0 }, + { 0x12180, 0x0 }, + { 0x112180, 0x0 }, + { 0x212180, 0x0 }, + { 0x13080, 0x0 }, + { 0x113080, 0x0 }, + { 0x213080, 0x0 }, + { 0x13180, 0x0 }, + { 0x113180, 0x0 }, + { 0x213180, 0x0 }, + { 0x10081, 0x0 }, + { 0x110081, 0x0 }, + { 0x210081, 0x0 }, + { 0x10181, 0x0 }, + { 0x110181, 0x0 }, + { 0x210181, 0x0 }, + { 0x11081, 0x0 }, + { 0x111081, 0x0 }, + { 0x211081, 0x0 }, + { 0x11181, 0x0 }, + { 0x111181, 0x0 }, + { 0x211181, 0x0 }, + { 0x12081, 0x0 }, + { 0x112081, 0x0 }, + { 0x212081, 0x0 }, + { 0x12181, 0x0 }, + { 0x112181, 0x0 }, + { 0x212181, 0x0 }, + { 0x13081, 0x0 }, + { 0x113081, 0x0 }, + { 0x213081, 0x0 }, + { 0x13181, 0x0 }, + { 0x113181, 0x0 }, + { 0x213181, 0x0 }, + { 0x100d0, 0x0 }, + { 0x1100d0, 0x0 }, + { 0x2100d0, 0x0 }, + { 0x101d0, 0x0 }, + { 0x1101d0, 0x0 }, + { 0x2101d0, 0x0 }, + { 0x110d0, 0x0 }, + { 0x1110d0, 0x0 }, + { 0x2110d0, 0x0 }, + { 0x111d0, 0x0 }, + { 0x1111d0, 0x0 }, + { 0x2111d0, 0x0 }, + { 0x120d0, 0x0 }, + { 0x1120d0, 0x0 }, + { 0x2120d0, 0x0 }, + { 0x121d0, 0x0 }, + { 0x1121d0, 0x0 }, + { 0x2121d0, 0x0 }, + { 0x130d0, 0x0 }, + { 0x1130d0, 0x0 }, + { 0x2130d0, 0x0 }, + { 0x131d0, 0x0 }, + { 0x1131d0, 0x0 }, + { 0x2131d0, 0x0 }, + { 0x100d1, 0x0 }, + { 0x1100d1, 0x0 }, + { 0x2100d1, 0x0 }, + { 0x101d1, 0x0 }, + { 0x1101d1, 0x0 }, + { 0x2101d1, 0x0 }, + { 0x110d1, 0x0 }, + { 0x1110d1, 0x0 }, + { 0x2110d1, 0x0 }, + { 0x111d1, 0x0 }, + { 0x1111d1, 0x0 }, + { 0x2111d1, 0x0 }, + { 0x120d1, 0x0 }, + { 0x1120d1, 0x0 }, + { 0x2120d1, 0x0 }, + { 0x121d1, 0x0 }, + { 0x1121d1, 0x0 }, + { 0x2121d1, 0x0 }, + { 0x130d1, 0x0 }, + { 0x1130d1, 0x0 }, + { 0x2130d1, 0x0 }, + { 0x131d1, 0x0 }, + { 0x1131d1, 0x0 }, + { 0x2131d1, 0x0 }, + { 0x10068, 0x0 }, + { 0x10168, 0x0 }, + { 0x10268, 0x0 }, + { 0x10368, 0x0 }, + { 0x10468, 0x0 }, + { 0x10568, 0x0 }, + { 0x10668, 0x0 }, + { 0x10768, 0x0 }, + { 0x10868, 0x0 }, + { 0x11068, 0x0 }, + { 0x11168, 0x0 }, + { 0x11268, 0x0 }, + { 0x11368, 0x0 }, + { 0x11468, 0x0 }, + { 0x11568, 0x0 }, + { 0x11668, 0x0 }, + { 0x11768, 0x0 }, + { 0x11868, 0x0 }, + { 0x12068, 0x0 }, + { 0x12168, 0x0 }, + { 0x12268, 0x0 }, + { 0x12368, 0x0 }, + { 0x12468, 0x0 }, + { 0x12568, 0x0 }, + { 0x12668, 0x0 }, + { 0x12768, 0x0 }, + { 0x12868, 0x0 }, + { 0x13068, 0x0 }, + { 0x13168, 0x0 }, + { 0x13268, 0x0 }, + { 0x13368, 0x0 }, + { 0x13468, 0x0 }, + { 0x13568, 0x0 }, + { 0x13668, 0x0 }, + { 0x13768, 0x0 }, + { 0x13868, 0x0 }, + { 0x10069, 0x0 }, + { 0x10169, 0x0 }, + { 0x10269, 0x0 }, + { 0x10369, 0x0 }, + { 0x10469, 0x0 }, + { 0x10569, 0x0 }, + { 0x10669, 0x0 }, + { 0x10769, 0x0 }, + { 0x10869, 0x0 }, + { 0x11069, 0x0 }, + { 0x11169, 0x0 }, + { 0x11269, 0x0 }, + { 0x11369, 0x0 }, + { 0x11469, 0x0 }, + { 0x11569, 0x0 }, + { 0x11669, 0x0 }, + { 0x11769, 0x0 }, + { 0x11869, 0x0 }, + { 0x12069, 0x0 }, + { 0x12169, 0x0 }, + { 0x12269, 0x0 }, + { 0x12369, 0x0 }, + { 0x12469, 0x0 }, + { 0x12569, 0x0 }, + { 0x12669, 0x0 }, + { 0x12769, 0x0 }, + { 0x12869, 0x0 }, + { 0x13069, 0x0 }, + { 0x13169, 0x0 }, + { 0x13269, 0x0 }, + { 0x13369, 0x0 }, + { 0x13469, 0x0 }, + { 0x13569, 0x0 }, + { 0x13669, 0x0 }, + { 0x13769, 0x0 }, + { 0x13869, 0x0 }, + { 0x1008c, 0x0 }, + { 0x11008c, 0x0 }, + { 0x21008c, 0x0 }, + { 0x1018c, 0x0 }, + { 0x11018c, 0x0 }, + { 0x21018c, 0x0 }, + { 0x1108c, 0x0 }, + { 0x11108c, 0x0 }, + { 0x21108c, 0x0 }, + { 0x1118c, 0x0 }, + { 0x11118c, 0x0 }, + { 0x21118c, 0x0 }, + { 0x1208c, 0x0 }, + { 0x11208c, 0x0 }, + { 0x21208c, 0x0 }, + { 0x1218c, 0x0 }, + { 0x11218c, 0x0 }, + { 0x21218c, 0x0 }, + { 0x1308c, 0x0 }, + { 0x11308c, 0x0 }, + { 0x21308c, 0x0 }, + { 0x1318c, 0x0 }, + { 0x11318c, 0x0 }, + { 0x21318c, 0x0 }, + { 0x1008d, 0x0 }, + { 0x11008d, 0x0 }, + { 0x21008d, 0x0 }, + { 0x1018d, 0x0 }, + { 0x11018d, 0x0 }, + { 0x21018d, 0x0 }, + { 0x1108d, 0x0 }, + { 0x11108d, 0x0 }, + { 0x21108d, 0x0 }, + { 0x1118d, 0x0 }, + { 0x11118d, 0x0 }, + { 0x21118d, 0x0 }, + { 0x1208d, 0x0 }, + { 0x11208d, 0x0 }, + { 0x21208d, 0x0 }, + { 0x1218d, 0x0 }, + { 0x11218d, 0x0 }, + { 0x21218d, 0x0 }, + { 0x1308d, 0x0 }, + { 0x11308d, 0x0 }, + { 0x21308d, 0x0 }, + { 0x1318d, 0x0 }, + { 0x11318d, 0x0 }, + { 0x21318d, 0x0 }, + { 0x100c0, 0x0 }, + { 0x1100c0, 0x0 }, + { 0x2100c0, 0x0 }, + { 0x101c0, 0x0 }, + { 0x1101c0, 0x0 }, + { 0x2101c0, 0x0 }, + { 0x102c0, 0x0 }, + { 0x1102c0, 0x0 }, + { 0x2102c0, 0x0 }, + { 0x103c0, 0x0 }, + { 0x1103c0, 0x0 }, + { 0x2103c0, 0x0 }, + { 0x104c0, 0x0 }, + { 0x1104c0, 0x0 }, + { 0x2104c0, 0x0 }, + { 0x105c0, 0x0 }, + { 0x1105c0, 0x0 }, + { 0x2105c0, 0x0 }, + { 0x106c0, 0x0 }, + { 0x1106c0, 0x0 }, + { 0x2106c0, 0x0 }, + { 0x107c0, 0x0 }, + { 0x1107c0, 0x0 }, + { 0x2107c0, 0x0 }, + { 0x108c0, 0x0 }, + { 0x1108c0, 0x0 }, + { 0x2108c0, 0x0 }, + { 0x110c0, 0x0 }, + { 0x1110c0, 0x0 }, + { 0x2110c0, 0x0 }, + { 0x111c0, 0x0 }, + { 0x1111c0, 0x0 }, + { 0x2111c0, 0x0 }, + { 0x112c0, 0x0 }, + { 0x1112c0, 0x0 }, + { 0x2112c0, 0x0 }, + { 0x113c0, 0x0 }, + { 0x1113c0, 0x0 }, + { 0x2113c0, 0x0 }, + { 0x114c0, 0x0 }, + { 0x1114c0, 0x0 }, + { 0x2114c0, 0x0 }, + { 0x115c0, 0x0 }, + { 0x1115c0, 0x0 }, + { 0x2115c0, 0x0 }, + { 0x116c0, 0x0 }, + { 0x1116c0, 0x0 }, + { 0x2116c0, 0x0 }, + { 0x117c0, 0x0 }, + { 0x1117c0, 0x0 }, + { 0x2117c0, 0x0 }, + { 0x118c0, 0x0 }, + { 0x1118c0, 0x0 }, + { 0x2118c0, 0x0 }, + { 0x120c0, 0x0 }, + { 0x1120c0, 0x0 }, + { 0x2120c0, 0x0 }, + { 0x121c0, 0x0 }, + { 0x1121c0, 0x0 }, + { 0x2121c0, 0x0 }, + { 0x122c0, 0x0 }, + { 0x1122c0, 0x0 }, + { 0x2122c0, 0x0 }, + { 0x123c0, 0x0 }, + { 0x1123c0, 0x0 }, + { 0x2123c0, 0x0 }, + { 0x124c0, 0x0 }, + { 0x1124c0, 0x0 }, + { 0x2124c0, 0x0 }, + { 0x125c0, 0x0 }, + { 0x1125c0, 0x0 }, + { 0x2125c0, 0x0 }, + { 0x126c0, 0x0 }, + { 0x1126c0, 0x0 }, + { 0x2126c0, 0x0 }, + { 0x127c0, 0x0 }, + { 0x1127c0, 0x0 }, + { 0x2127c0, 0x0 }, + { 0x128c0, 0x0 }, + { 0x1128c0, 0x0 }, + { 0x2128c0, 0x0 }, + { 0x130c0, 0x0 }, + { 0x1130c0, 0x0 }, + { 0x2130c0, 0x0 }, + { 0x131c0, 0x0 }, + { 0x1131c0, 0x0 }, + { 0x2131c0, 0x0 }, + { 0x132c0, 0x0 }, + { 0x1132c0, 0x0 }, + { 0x2132c0, 0x0 }, + { 0x133c0, 0x0 }, + { 0x1133c0, 0x0 }, + { 0x2133c0, 0x0 }, + { 0x134c0, 0x0 }, + { 0x1134c0, 0x0 }, + { 0x2134c0, 0x0 }, + { 0x135c0, 0x0 }, + { 0x1135c0, 0x0 }, + { 0x2135c0, 0x0 }, + { 0x136c0, 0x0 }, + { 0x1136c0, 0x0 }, + { 0x2136c0, 0x0 }, + { 0x137c0, 0x0 }, + { 0x1137c0, 0x0 }, + { 0x2137c0, 0x0 }, + { 0x138c0, 0x0 }, + { 0x1138c0, 0x0 }, + { 0x2138c0, 0x0 }, + { 0x100c1, 0x0 }, + { 0x1100c1, 0x0 }, + { 0x2100c1, 0x0 }, + { 0x101c1, 0x0 }, + { 0x1101c1, 0x0 }, + { 0x2101c1, 0x0 }, + { 0x102c1, 0x0 }, + { 0x1102c1, 0x0 }, + { 0x2102c1, 0x0 }, + { 0x103c1, 0x0 }, + { 0x1103c1, 0x0 }, + { 0x2103c1, 0x0 }, + { 0x104c1, 0x0 }, + { 0x1104c1, 0x0 }, + { 0x2104c1, 0x0 }, + { 0x105c1, 0x0 }, + { 0x1105c1, 0x0 }, + { 0x2105c1, 0x0 }, + { 0x106c1, 0x0 }, + { 0x1106c1, 0x0 }, + { 0x2106c1, 0x0 }, + { 0x107c1, 0x0 }, + { 0x1107c1, 0x0 }, + { 0x2107c1, 0x0 }, + { 0x108c1, 0x0 }, + { 0x1108c1, 0x0 }, + { 0x2108c1, 0x0 }, + { 0x110c1, 0x0 }, + { 0x1110c1, 0x0 }, + { 0x2110c1, 0x0 }, + { 0x111c1, 0x0 }, + { 0x1111c1, 0x0 }, + { 0x2111c1, 0x0 }, + { 0x112c1, 0x0 }, + { 0x1112c1, 0x0 }, + { 0x2112c1, 0x0 }, + { 0x113c1, 0x0 }, + { 0x1113c1, 0x0 }, + { 0x2113c1, 0x0 }, + { 0x114c1, 0x0 }, + { 0x1114c1, 0x0 }, + { 0x2114c1, 0x0 }, + { 0x115c1, 0x0 }, + { 0x1115c1, 0x0 }, + { 0x2115c1, 0x0 }, + { 0x116c1, 0x0 }, + { 0x1116c1, 0x0 }, + { 0x2116c1, 0x0 }, + { 0x117c1, 0x0 }, + { 0x1117c1, 0x0 }, + { 0x2117c1, 0x0 }, + { 0x118c1, 0x0 }, + { 0x1118c1, 0x0 }, + { 0x2118c1, 0x0 }, + { 0x120c1, 0x0 }, + { 0x1120c1, 0x0 }, + { 0x2120c1, 0x0 }, + { 0x121c1, 0x0 }, + { 0x1121c1, 0x0 }, + { 0x2121c1, 0x0 }, + { 0x122c1, 0x0 }, + { 0x1122c1, 0x0 }, + { 0x2122c1, 0x0 }, + { 0x123c1, 0x0 }, + { 0x1123c1, 0x0 }, + { 0x2123c1, 0x0 }, + { 0x124c1, 0x0 }, + { 0x1124c1, 0x0 }, + { 0x2124c1, 0x0 }, + { 0x125c1, 0x0 }, + { 0x1125c1, 0x0 }, + { 0x2125c1, 0x0 }, + { 0x126c1, 0x0 }, + { 0x1126c1, 0x0 }, + { 0x2126c1, 0x0 }, + { 0x127c1, 0x0 }, + { 0x1127c1, 0x0 }, + { 0x2127c1, 0x0 }, + { 0x128c1, 0x0 }, + { 0x1128c1, 0x0 }, + { 0x2128c1, 0x0 }, + { 0x130c1, 0x0 }, + { 0x1130c1, 0x0 }, + { 0x2130c1, 0x0 }, + { 0x131c1, 0x0 }, + { 0x1131c1, 0x0 }, + { 0x2131c1, 0x0 }, + { 0x132c1, 0x0 }, + { 0x1132c1, 0x0 }, + { 0x2132c1, 0x0 }, + { 0x133c1, 0x0 }, + { 0x1133c1, 0x0 }, + { 0x2133c1, 0x0 }, + { 0x134c1, 0x0 }, + { 0x1134c1, 0x0 }, + { 0x2134c1, 0x0 }, + { 0x135c1, 0x0 }, + { 0x1135c1, 0x0 }, + { 0x2135c1, 0x0 }, + { 0x136c1, 0x0 }, + { 0x1136c1, 0x0 }, + { 0x2136c1, 0x0 }, + { 0x137c1, 0x0 }, + { 0x1137c1, 0x0 }, + { 0x2137c1, 0x0 }, + { 0x138c1, 0x0 }, + { 0x1138c1, 0x0 }, + { 0x2138c1, 0x0 }, + { 0x10020, 0x0 }, + { 0x110020, 0x0 }, + { 0x210020, 0x0 }, + { 0x11020, 0x0 }, + { 0x111020, 0x0 }, + { 0x211020, 0x0 }, + { 0x12020, 0x0 }, + { 0x112020, 0x0 }, + { 0x212020, 0x0 }, + { 0x13020, 0x0 }, + { 0x113020, 0x0 }, + { 0x213020, 0x0 }, + { 0x20072, 0x0 }, + { 0x20073, 0x0 }, + { 0x20074, 0x0 }, + { 0x100aa, 0x0 }, + { 0x110aa, 0x0 }, + { 0x120aa, 0x0 }, + { 0x130aa, 0x0 }, + { 0x20010, 0x0 }, + { 0x120010, 0x0 }, + { 0x220010, 0x0 }, + { 0x20011, 0x0 }, + { 0x120011, 0x0 }, + { 0x220011, 0x0 }, + { 0x100ae, 0x0 }, + { 0x1100ae, 0x0 }, + { 0x2100ae, 0x0 }, + { 0x100af, 0x0 }, + { 0x1100af, 0x0 }, + { 0x2100af, 0x0 }, + { 0x110ae, 0x0 }, + { 0x1110ae, 0x0 }, + { 0x2110ae, 0x0 }, + { 0x110af, 0x0 }, + { 0x1110af, 0x0 }, + { 0x2110af, 0x0 }, + { 0x120ae, 0x0 }, + { 0x1120ae, 0x0 }, + { 0x2120ae, 0x0 }, + { 0x120af, 0x0 }, + { 0x1120af, 0x0 }, + { 0x2120af, 0x0 }, + { 0x130ae, 0x0 }, + { 0x1130ae, 0x0 }, + { 0x2130ae, 0x0 }, + { 0x130af, 0x0 }, + { 0x1130af, 0x0 }, + { 0x2130af, 0x0 }, + { 0x20020, 0x0 }, + { 0x120020, 0x0 }, + { 0x220020, 0x0 }, + { 0x100a0, 0x0 }, + { 0x100a1, 0x0 }, + { 0x100a2, 0x0 }, + { 0x100a3, 0x0 }, + { 0x100a4, 0x0 }, + { 0x100a5, 0x0 }, + { 0x100a6, 0x0 }, + { 0x100a7, 0x0 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x0 }, + { 0x110a2, 0x0 }, + { 0x110a3, 0x0 }, + { 0x110a4, 0x0 }, + { 0x110a5, 0x0 }, + { 0x110a6, 0x0 }, + { 0x110a7, 0x0 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x0 }, + { 0x120a2, 0x0 }, + { 0x120a3, 0x0 }, + { 0x120a4, 0x0 }, + { 0x120a5, 0x0 }, + { 0x120a6, 0x0 }, + { 0x120a7, 0x0 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x0 }, + { 0x130a2, 0x0 }, + { 0x130a3, 0x0 }, + { 0x130a4, 0x0 }, + { 0x130a5, 0x0 }, + { 0x130a6, 0x0 }, + { 0x130a7, 0x0 }, + { 0x2007c, 0x0 }, + { 0x12007c, 0x0 }, + { 0x22007c, 0x0 }, + { 0x2007d, 0x0 }, + { 0x12007d, 0x0 }, + { 0x22007d, 0x0 }, + { 0x400fd, 0x0 }, + { 0x400c0, 0x0 }, + { 0x90201, 0x0 }, + { 0x190201, 0x0 }, + { 0x290201, 0x0 }, + { 0x90202, 0x0 }, + { 0x190202, 0x0 }, + { 0x290202, 0x0 }, + { 0x90203, 0x0 }, + { 0x190203, 0x0 }, + { 0x290203, 0x0 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x90205, 0x0 }, + { 0x190205, 0x0 }, + { 0x290205, 0x0 }, + { 0x90206, 0x0 }, + { 0x190206, 0x0 }, + { 0x290206, 0x0 }, + { 0x90207, 0x0 }, + { 0x190207, 0x0 }, + { 0x290207, 0x0 }, + { 0x90208, 0x0 }, + { 0x190208, 0x0 }, + { 0x290208, 0x0 }, + { 0x10062, 0x0 }, + { 0x10162, 0x0 }, + { 0x10262, 0x0 }, + { 0x10362, 0x0 }, + { 0x10462, 0x0 }, + { 0x10562, 0x0 }, + { 0x10662, 0x0 }, + { 0x10762, 0x0 }, + { 0x10862, 0x0 }, + { 0x11062, 0x0 }, + { 0x11162, 0x0 }, + { 0x11262, 0x0 }, + { 0x11362, 0x0 }, + { 0x11462, 0x0 }, + { 0x11562, 0x0 }, + { 0x11662, 0x0 }, + { 0x11762, 0x0 }, + { 0x11862, 0x0 }, + { 0x12062, 0x0 }, + { 0x12162, 0x0 }, + { 0x12262, 0x0 }, + { 0x12362, 0x0 }, + { 0x12462, 0x0 }, + { 0x12562, 0x0 }, + { 0x12662, 0x0 }, + { 0x12762, 0x0 }, + { 0x12862, 0x0 }, + { 0x13062, 0x0 }, + { 0x13162, 0x0 }, + { 0x13262, 0x0 }, + { 0x13362, 0x0 }, + { 0x13462, 0x0 }, + { 0x13562, 0x0 }, + { 0x13662, 0x0 }, + { 0x13762, 0x0 }, + { 0x13862, 0x0 }, + { 0x20077, 0x0 }, + { 0x10001, 0x0 }, + { 0x11001, 0x0 }, + { 0x12001, 0x0 }, + { 0x13001, 0x0 }, + { 0x10040, 0x0 }, + { 0x10140, 0x0 }, + { 0x10240, 0x0 }, + { 0x10340, 0x0 }, + { 0x10440, 0x0 }, + { 0x10540, 0x0 }, + { 0x10640, 0x0 }, + { 0x10740, 0x0 }, + { 0x10840, 0x0 }, + { 0x10030, 0x0 }, + { 0x10130, 0x0 }, + { 0x10230, 0x0 }, + { 0x10330, 0x0 }, + { 0x10430, 0x0 }, + { 0x10530, 0x0 }, + { 0x10630, 0x0 }, + { 0x10730, 0x0 }, + { 0x10830, 0x0 }, + { 0x11040, 0x0 }, + { 0x11140, 0x0 }, + { 0x11240, 0x0 }, + { 0x11340, 0x0 }, + { 0x11440, 0x0 }, + { 0x11540, 0x0 }, + { 0x11640, 0x0 }, + { 0x11740, 0x0 }, + { 0x11840, 0x0 }, + { 0x11030, 0x0 }, + { 0x11130, 0x0 }, + { 0x11230, 0x0 }, + { 0x11330, 0x0 }, + { 0x11430, 0x0 }, + { 0x11530, 0x0 }, + { 0x11630, 0x0 }, + { 0x11730, 0x0 }, + { 0x11830, 0x0 }, + { 0x12040, 0x0 }, + { 0x12140, 0x0 }, + { 0x12240, 0x0 }, + { 0x12340, 0x0 }, + { 0x12440, 0x0 }, + { 0x12540, 0x0 }, + { 0x12640, 0x0 }, + { 0x12740, 0x0 }, + { 0x12840, 0x0 }, + { 0x12030, 0x0 }, + { 0x12130, 0x0 }, + { 0x12230, 0x0 }, + { 0x12330, 0x0 }, + { 0x12430, 0x0 }, + { 0x12530, 0x0 }, + { 0x12630, 0x0 }, + { 0x12730, 0x0 }, + { 0x12830, 0x0 }, + { 0x13040, 0x0 }, + { 0x13140, 0x0 }, + { 0x13240, 0x0 }, + { 0x13340, 0x0 }, + { 0x13440, 0x0 }, + { 0x13540, 0x0 }, + { 0x13640, 0x0 }, + { 0x13740, 0x0 }, + { 0x13840, 0x0 }, + { 0x13030, 0x0 }, + { 0x13130, 0x0 }, + { 0x13230, 0x0 }, + { 0x13330, 0x0 }, + { 0x13430, 0x0 }, + { 0x13530, 0x0 }, + { 0x13630, 0x0 }, + { 0x13730, 0x0 }, + { 0x13830, 0x0 }, +}; + +uint32_t ddrphy_trained_csr_num = ARRAY_SIZE(ddrphy_trained_csr); diff --git a/drivers/ddr/imx/imx8m/ddrphy_train.c b/drivers/ddr/imx/imx8m/ddrphy_train.c new file mode 100644 index 00000000000..18f7ed7fea9 --- /dev/null +++ b/drivers/ddr/imx/imx8m/ddrphy_train.c @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include <common.h> +#include <linux/kernel.h> +#include <asm/arch/ddr.h> +#include <asm/arch/lpddr4_define.h> + +void ddr_cfg_phy(struct dram_timing_info *dram_timing) +{ + struct dram_cfg_param *dram_cfg; + struct dram_fsp_msg *fsp_msg; + unsigned int num; + int i = 0; + int j = 0; + + /* initialize PHY configuration */ + dram_cfg = dram_timing->ddrphy_cfg; + num = dram_timing->ddrphy_cfg_num; + for (i = 0; i < num; i++) { + /* config phy reg */ + dwc_ddrphy_apb_wr(dram_cfg->reg, dram_cfg->val); + dram_cfg++; + } + + /* load the frequency setpoint message block config */ + fsp_msg = dram_timing->fsp_msg; + for (i = 0; i < dram_timing->fsp_msg_num; i++) { + debug("DRAM PHY training for %dMTS\n", fsp_msg->drate); + /* set dram PHY input clocks to desired frequency */ + ddrphy_init_set_dfi_clk(fsp_msg->drate); + + /* load the dram training firmware image */ + dwc_ddrphy_apb_wr(0xd0000, 0x0); + ddr_load_train_firmware(fsp_msg->fw_type); + + /* load the frequency set point message block parameter */ + dram_cfg = fsp_msg->fsp_cfg; + num = fsp_msg->fsp_cfg_num; + for (j = 0; j < num; j++) { + dwc_ddrphy_apb_wr(dram_cfg->reg, dram_cfg->val); + dram_cfg++; + } + + /* + * -------------------- excute the firmware -------------------- + * Running the firmware is a simply process to taking the + * PMU out of reset and stall, then the firwmare will be run + * 1. reset the PMU; + * 2. begin the excution; + * 3. wait for the training done; + * 4. read the message block result. + * ------------------------------------------------------------- + */ + dwc_ddrphy_apb_wr(0xd0000, 0x1); + dwc_ddrphy_apb_wr(0xd0099, 0x9); + dwc_ddrphy_apb_wr(0xd0099, 0x1); + dwc_ddrphy_apb_wr(0xd0099, 0x0); + + /* Wait for the training firmware to complete */ + wait_ddrphy_training_complete(); + + /* Halt the microcontroller. */ + dwc_ddrphy_apb_wr(0xd0099, 0x1); + + /* Read the Message Block results */ + dwc_ddrphy_apb_wr(0xd0000, 0x0); + ddrphy_init_read_msg_block(fsp_msg->fw_type); + dwc_ddrphy_apb_wr(0xd0000, 0x1); + + fsp_msg++; + } + + /* Load PHY Init Engine Image */ + dram_cfg = dram_timing->ddrphy_pie; + num = dram_timing->ddrphy_pie_num; + for (i = 0; i < num; i++) { + dwc_ddrphy_apb_wr(dram_cfg->reg, dram_cfg->val); + dram_cfg++; + } + + /* save the ddr PHY trained CSR in memory for low power use */ + ddrphy_trained_csr_save(ddrphy_trained_csr, ddrphy_trained_csr_num); +} diff --git a/drivers/ddr/imx/imx8m/ddrphy_utils.c b/drivers/ddr/imx/imx8m/ddrphy_utils.c new file mode 100644 index 00000000000..47325397647 --- /dev/null +++ b/drivers/ddr/imx/imx8m/ddrphy_utils.c @@ -0,0 +1,186 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* +* Copyright 2018 NXP +*/ + +#include <common.h> +#include <errno.h> +#include <asm/io.h> +#include <asm/arch/ddr.h> +#include <asm/arch/clock.h> +#include <asm/arch/ddr.h> +#include <asm/arch/lpddr4_define.h> + +static inline void poll_pmu_message_ready(void) +{ + unsigned int reg; + + do { + reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0004); + } while (reg & 0x1); +} + +static inline void ack_pmu_message_receive(void) +{ + unsigned int reg; + + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0031, 0x0); + + do { + reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0004); + } while (!(reg & 0x1)); + + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0031, 0x1); +} + +static inline unsigned int get_mail(void) +{ + unsigned int reg; + + poll_pmu_message_ready(); + + reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0032); + + ack_pmu_message_receive(); + + return reg; +} + +static inline unsigned int get_stream_message(void) +{ + unsigned int reg, reg2; + + poll_pmu_message_ready(); + + reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0032); + + reg2 = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0034); + + reg2 = (reg2 << 16) | reg; + + ack_pmu_message_receive(); + + return reg2; +} + +static inline void decode_major_message(unsigned int mail) +{ + debug("[PMU Major message = 0x%08x]\n", mail); +} + +static inline void decode_streaming_message(void) +{ + unsigned int string_index, arg __maybe_unused; + int i = 0; + + string_index = get_stream_message(); + debug("PMU String index = 0x%08x\n", string_index); + while (i < (string_index & 0xffff)) { + arg = get_stream_message(); + debug("arg[%d] = 0x%08x\n", i, arg); + i++; + } + + debug("\n"); +} + +void wait_ddrphy_training_complete(void) +{ + unsigned int mail; + + while (1) { + mail = get_mail(); + decode_major_message(mail); + if (mail == 0x08) { + decode_streaming_message(); + } else if (mail == 0x07) { + debug("Training PASS\n"); + break; + } else if (mail == 0xff) { + printf("Training FAILED\n"); + break; + } + } +} + +void ddrphy_init_set_dfi_clk(unsigned int drate) +{ + switch (drate) { + case 3200: + dram_pll_init(MHZ(800)); + dram_disable_bypass(); + break; + case 3000: + dram_pll_init(MHZ(750)); + dram_disable_bypass(); + break; + case 2400: + dram_pll_init(MHZ(600)); + dram_disable_bypass(); + break; + case 1600: + dram_pll_init(MHZ(400)); + dram_disable_bypass(); + break; + case 667: + dram_pll_init(MHZ(167)); + dram_disable_bypass(); + break; + case 400: + dram_enable_bypass(MHZ(400)); + break; + case 100: + dram_enable_bypass(MHZ(100)); + break; + default: + return; + } +} + +void ddrphy_init_read_msg_block(enum fw_type type) +{ +} + +void lpddr4_mr_write(unsigned int mr_rank, unsigned int mr_addr, + unsigned int mr_data) +{ + unsigned int tmp; + /* + * 1. Poll MRSTAT.mr_wr_busy until it is 0. + * This checks that there is no outstanding MR transaction. + * No writes should be performed to MRCTRL0 and MRCTRL1 if + * MRSTAT.mr_wr_busy = 1. + */ + do { + tmp = reg32_read(DDRC_MRSTAT(0)); + } while (tmp & 0x1); + /* + * 2. Write the MRCTRL0.mr_type, MRCTRL0.mr_addr, MRCTRL0.mr_rank and + * (for MRWs) MRCTRL1.mr_data to define the MR transaction. + */ + reg32_write(DDRC_MRCTRL0(0), (mr_rank << 4)); + reg32_write(DDRC_MRCTRL1(0), (mr_addr << 8) | mr_data); + reg32setbit(DDRC_MRCTRL0(0), 31); +} + +unsigned int lpddr4_mr_read(unsigned int mr_rank, unsigned int mr_addr) +{ + unsigned int tmp; + + reg32_write(DRC_PERF_MON_MRR0_DAT(0), 0x1); + do { + tmp = reg32_read(DDRC_MRSTAT(0)); + } while (tmp & 0x1); + + reg32_write(DDRC_MRCTRL0(0), (mr_rank << 4) | 0x1); + reg32_write(DDRC_MRCTRL1(0), (mr_addr << 8)); + reg32setbit(DDRC_MRCTRL0(0), 31); + do { + tmp = reg32_read(DRC_PERF_MON_MRR0_DAT(0)); + } while ((tmp & 0x8) == 0); + tmp = reg32_read(DRC_PERF_MON_MRR1_DAT(0)); + tmp = tmp & 0xff; + reg32_write(DRC_PERF_MON_MRR0_DAT(0), 0x4); + + return tmp; +} diff --git a/drivers/ddr/imx/imx8m/helper.c b/drivers/ddr/imx/imx8m/helper.c new file mode 100644 index 00000000000..61cd4f6db12 --- /dev/null +++ b/drivers/ddr/imx/imx8m/helper.c @@ -0,0 +1,170 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include <common.h> +#include <spl.h> +#include <asm/io.h> +#include <errno.h> +#include <asm/io.h> +#include <asm/arch/ddr.h> +#include <asm/arch/ddr.h> +#include <asm/arch/lpddr4_define.h> +#include <asm/sections.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define IMEM_LEN 32768 /* byte */ +#define DMEM_LEN 16384 /* byte */ +#define IMEM_2D_OFFSET 49152 + +#define IMEM_OFFSET_ADDR 0x00050000 +#define DMEM_OFFSET_ADDR 0x00054000 +#define DDR_TRAIN_CODE_BASE_ADDR IP2APB_DDRPHY_IPS_BASE_ADDR(0) + +/* We need PHY iMEM PHY is 32KB padded */ +void ddr_load_train_firmware(enum fw_type type) +{ + u32 tmp32, i; + u32 error = 0; + unsigned long pr_to32, pr_from32; + unsigned long fw_offset = type ? IMEM_2D_OFFSET : 0; + unsigned long imem_start = (unsigned long)&_end + fw_offset; + unsigned long dmem_start = imem_start + IMEM_LEN; + + pr_from32 = imem_start; + pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR; + for (i = 0x0; i < IMEM_LEN; ) { + tmp32 = readl(pr_from32); + writew(tmp32 & 0x0000ffff, pr_to32); + pr_to32 += 4; + writew((tmp32 >> 16) & 0x0000ffff, pr_to32); + pr_to32 += 4; + pr_from32 += 4; + i += 4; + } + + pr_from32 = dmem_start; + pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR; + for (i = 0x0; i < DMEM_LEN; ) { + tmp32 = readl(pr_from32); + writew(tmp32 & 0x0000ffff, pr_to32); + pr_to32 += 4; + writew((tmp32 >> 16) & 0x0000ffff, pr_to32); + pr_to32 += 4; + pr_from32 += 4; + i += 4; + } + + debug("check ddr4_pmu_train_imem code\n"); + pr_from32 = imem_start; + pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR; + for (i = 0x0; i < IMEM_LEN; ) { + tmp32 = (readw(pr_to32) & 0x0000ffff); + pr_to32 += 4; + tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16); + + if (tmp32 != readl(pr_from32)) { + debug("%lx %lx\n", pr_from32, pr_to32); + error++; + } + pr_from32 += 4; + pr_to32 += 4; + i += 4; + } + if (error) + printf("check ddr4_pmu_train_imem code fail=%d\n", error); + else + debug("check ddr4_pmu_train_imem code pass\n"); + + debug("check ddr4_pmu_train_dmem code\n"); + pr_from32 = dmem_start; + pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR; + for (i = 0x0; i < DMEM_LEN;) { + tmp32 = (readw(pr_to32) & 0x0000ffff); + pr_to32 += 4; + tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16); + if (tmp32 != readl(pr_from32)) { + debug("%lx %lx\n", pr_from32, pr_to32); + error++; + } + pr_from32 += 4; + pr_to32 += 4; + i += 4; + } + + if (error) + printf("check ddr4_pmu_train_dmem code fail=%d", error); + else + debug("check ddr4_pmu_train_dmem code pass\n"); +} + +void ddrphy_trained_csr_save(struct dram_cfg_param *ddrphy_csr, + unsigned int num) +{ + int i = 0; + + /* enable the ddrphy apb */ + dwc_ddrphy_apb_wr(0xd0000, 0x0); + dwc_ddrphy_apb_wr(0xc0080, 0x3); + for (i = 0; i < num; i++) { + ddrphy_csr->val = dwc_ddrphy_apb_rd(ddrphy_csr->reg); + ddrphy_csr++; + } + /* disable the ddrphy apb */ + dwc_ddrphy_apb_wr(0xc0080, 0x2); + dwc_ddrphy_apb_wr(0xd0000, 0x1); +} + +void dram_config_save(struct dram_timing_info *timing_info, + unsigned long saved_timing_base) +{ + int i = 0; + struct dram_timing_info *saved_timing = (struct dram_timing_info *)saved_timing_base; + struct dram_cfg_param *cfg; + + saved_timing->ddrc_cfg_num = timing_info->ddrc_cfg_num; + saved_timing->ddrphy_cfg_num = timing_info->ddrphy_cfg_num; + saved_timing->ddrphy_trained_csr_num = ddrphy_trained_csr_num; + saved_timing->ddrphy_pie_num = timing_info->ddrphy_pie_num; + + /* save the fsp table */ + for (i = 0; i < 4; i++) + saved_timing->fsp_table[i] = timing_info->fsp_table[i]; + + cfg = (struct dram_cfg_param *)(saved_timing_base + + sizeof(*timing_info)); + + /* save ddrc config */ + saved_timing->ddrc_cfg = cfg; + for (i = 0; i < timing_info->ddrc_cfg_num; i++) { + cfg->reg = timing_info->ddrc_cfg[i].reg; + cfg->val = timing_info->ddrc_cfg[i].val; + cfg++; + } + + /* save ddrphy config */ + saved_timing->ddrphy_cfg = cfg; + for (i = 0; i < timing_info->ddrphy_cfg_num; i++) { + cfg->reg = timing_info->ddrphy_cfg[i].reg; + cfg->val = timing_info->ddrphy_cfg[i].val; + cfg++; + } + + /* save the ddrphy csr */ + saved_timing->ddrphy_trained_csr = cfg; + for (i = 0; i < ddrphy_trained_csr_num; i++) { + cfg->reg = ddrphy_trained_csr[i].reg; + cfg->val = ddrphy_trained_csr[i].val; + cfg++; + } + + /* save the ddrphy pie */ + saved_timing->ddrphy_pie = cfg; + for (i = 0; i < timing_info->ddrphy_pie_num; i++) { + cfg->reg = timing_info->ddrphy_pie[i].reg; + cfg->val = timing_info->ddrphy_pie[i].val; + cfg++; + } +} diff --git a/drivers/ddr/imx/imx8m/lpddr4_init.c b/drivers/ddr/imx/imx8m/lpddr4_init.c new file mode 100644 index 00000000000..a4bc1de8eb6 --- /dev/null +++ b/drivers/ddr/imx/imx8m/lpddr4_init.c @@ -0,0 +1,188 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* +* Copyright 2018 NXP +* +*/ + +#include <common.h> +#include <errno.h> +#include <asm/io.h> +#include <asm/arch/ddr.h> +#include <asm/arch/clock.h> +#include <asm/arch/ddr.h> +#include <asm/arch/lpddr4_define.h> +#include <asm/arch/sys_proto.h> + +void lpddr4_cfg_umctl2(struct dram_cfg_param *ddrc_cfg, int num) +{ + int i = 0; + + for (i = 0; i < num; i++) { + reg32_write(ddrc_cfg->reg, ddrc_cfg->val); + ddrc_cfg++; + } +} + +void ddr_init(struct dram_timing_info *dram_timing) +{ + unsigned int tmp; + + debug("DDRINFO: start lpddr4 ddr init\n"); + /* step 1: reset */ + if (is_imx8mq()) { + reg32_write(SRC_DDRC_RCR_ADDR + 0x04, 0x8F00000F); + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00000F); + reg32_write(SRC_DDRC_RCR_ADDR + 0x04, 0x8F000000); + } else { + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00001F); + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00000F); + } + + mdelay(100); + + debug("DDRINFO: reset done\n"); + /* + * change the clock source of dram_apb_clk_root: + * source 4 800MHz /4 = 200MHz + */ + clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | + CLK_ROOT_SOURCE_SEL(4) | + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV4)); + + /* disable iso */ + reg32_write(0x303A00EC, 0x0000ffff); /* PGC_CPU_MAPPING */ + reg32setbit(0x303A00F8, 5); /* PU_PGC_SW_PUP_REQ */ + + debug("DDRINFO: cfg clk\n"); + dram_pll_init(MHZ(750)); + + /* + * release [0]ddr1_preset_n, [1]ddr1_core_reset_n, + * [2]ddr1_phy_reset, [3]ddr1_phy_pwrokin_n + */ + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000006); + + /*step2 Configure uMCTL2's registers */ + debug("DDRINFO: ddrc config start\n"); + lpddr4_cfg_umctl2(dram_timing->ddrc_cfg, dram_timing->ddrc_cfg_num); + debug("DDRINFO: ddrc config done\n"); + + /* + * step3 de-assert all reset + * RESET: <core_ddrc_rstn> DEASSERTED + * RESET: <aresetn> for Port 0 DEASSERT(0)ED + */ + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000004); + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000000); + + reg32_write(DDRC_DBG1(0), 0x00000000); + /* step4 */ + /* [0]dis_auto_refresh=1 */ + reg32_write(DDRC_RFSHCTL3(0), 0x00000011); + + /* [8]--1: lpddr4_sr allowed; [5]--1: software entry to SR */ + reg32_write(DDRC_PWRCTL(0), 0x000000a8); + + do { + tmp = reg32_read(DDRC_STAT(0)); + } while ((tmp & 0x33f) != 0x223); + + reg32_write(DDRC_DDR_SS_GPR0, 0x01); /* LPDDR4 mode */ + + /* step5 */ + reg32_write(DDRC_SWCTL(0), 0x00000000); + + /* step6 */ + tmp = reg32_read(DDRC_MSTR2(0)); + if (tmp == 0x2) + reg32_write(DDRC_DFIMISC(0), 0x00000210); + else if (tmp == 0x1) + reg32_write(DDRC_DFIMISC(0), 0x00000110); + else + reg32_write(DDRC_DFIMISC(0), 0x00000010); + + /* step7 [0]--1: disable quasi-dynamic programming */ + reg32_write(DDRC_SWCTL(0), 0x00000001); + + /* step8 Configure LPDDR4 PHY's registers */ + debug("DDRINFO:ddrphy config start\n"); + ddr_cfg_phy(dram_timing); + debug("DDRINFO: ddrphy config done\n"); + + /* + * step14 CalBusy.0 =1, indicates the calibrator is actively + * calibrating. Wait Calibrating done. + */ + do { + tmp = reg32_read(DDRPHY_CalBusy(0)); + } while ((tmp & 0x1)); + + debug("DDRINFO:ddrphy calibration done\n"); + + /* step15 [0]--0: to enable quasi-dynamic programming */ + reg32_write(DDRC_SWCTL(0), 0x00000000); + + /* step16 */ + tmp = reg32_read(DDRC_MSTR2(0)); + if (tmp == 0x2) + reg32_write(DDRC_DFIMISC(0), 0x00000230); + else if (tmp == 0x1) + reg32_write(DDRC_DFIMISC(0), 0x00000130); + else + reg32_write(DDRC_DFIMISC(0), 0x00000030); + + /* step17 [0]--1: disable quasi-dynamic programming */ + reg32_write(DDRC_SWCTL(0), 0x00000001); + /* step18 wait DFISTAT.dfi_init_complete to 1 */ + do { + tmp = reg32_read(DDRC_DFISTAT(0)); + } while ((tmp & 0x1) == 0x0); + + /* step19 */ + reg32_write(DDRC_SWCTL(0), 0x00000000); + + /* step20~22 */ + tmp = reg32_read(DDRC_MSTR2(0)); + if (tmp == 0x2) { + reg32_write(DDRC_DFIMISC(0), 0x00000210); + /* set DFIMISC.dfi_init_complete_en again */ + reg32_write(DDRC_DFIMISC(0), 0x00000211); + } else if (tmp == 0x1) { + reg32_write(DDRC_DFIMISC(0), 0x00000110); + /* set DFIMISC.dfi_init_complete_en again */ + reg32_write(DDRC_DFIMISC(0), 0x00000111); + } else { + /* clear DFIMISC.dfi_init_complete_en */ + reg32_write(DDRC_DFIMISC(0), 0x00000010); + /* set DFIMISC.dfi_init_complete_en again */ + reg32_write(DDRC_DFIMISC(0), 0x00000011); + } + + /* step23 [5]selfref_sw=0; */ + reg32_write(DDRC_PWRCTL(0), 0x00000008); + /* step24 sw_done=1 */ + reg32_write(DDRC_SWCTL(0), 0x00000001); + + /* step25 wait SWSTAT.sw_done_ack to 1 */ + do { + tmp = reg32_read(DDRC_SWSTAT(0)); + } while ((tmp & 0x1) == 0x0); + +#ifdef DFI_BUG_WR + reg32_write(DDRC_DFIPHYMSTR(0), 0x00000001); +#endif + /* wait STAT.operating_mode([1:0] for ddr3) to normal state */ + do { + tmp = reg32_read(DDRC_STAT(0)); + } while ((tmp & 0x3) != 0x1); + + /* step26 */ + reg32_write(DDRC_RFSHCTL3(0), 0x00000010); + + /* enable port 0 */ + reg32_write(DDRC_PCTRL_0(0), 0x00000001); + debug("DDRINFO: ddrmix config done\n"); + + /* save the dram timing config into memory */ + dram_config_save(dram_timing, CONFIG_SAVED_DRAM_TIMING_BASE); +} diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index 8a4162eccdb..1820676d7a1 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -26,6 +26,15 @@ config SANDBOX_DMA Enable support for a test DMA uclass implementation. It stimulates DMA transfer by simple copying data between channels. +config BCM6348_IUDMA + bool "BCM6348 IUDMA driver" + depends on ARCH_BMIPS + select DMA_CHANNELS + help + Enable the BCM6348 IUDMA driver. + This driver support data transfer from devices to + memory and from memory to devices. + config TI_EDMA3 bool "TI EDMA3 driver" help diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile index aff31f986a1..b5f9147e0a5 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_DMA) += dma-uclass.o obj-$(CONFIG_FSLDMAFEC) += MCD_tasksInit.o MCD_dmaApi.o MCD_tasks.o obj-$(CONFIG_APBH_DMA) += apbh_dma.o +obj-$(CONFIG_BCM6348_IUDMA) += bcm6348-iudma.o obj-$(CONFIG_FSL_DMA) += fsl_dma.o obj-$(CONFIG_SANDBOX_DMA) += sandbox-dma-test.o obj-$(CONFIG_TI_KSNAV) += keystone_nav.o keystone_nav_cfg.o diff --git a/drivers/dma/bcm6348-iudma.c b/drivers/dma/bcm6348-iudma.c new file mode 100644 index 00000000000..1d3c192cfe5 --- /dev/null +++ b/drivers/dma/bcm6348-iudma.c @@ -0,0 +1,642 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com> + * + * Derived from linux/drivers/dma/bcm63xx-iudma.c: + * Copyright (C) 2015 Simon Arlott <simon@fire.lp0.eu> + * + * Derived from linux/drivers/net/ethernet/broadcom/bcm63xx_enet.c: + * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr> + * + * Derived from bcm963xx_4.12L.06B_consumer/shared/opensource/include/bcm963xx/63268_map_part.h: + * Copyright (C) 2000-2010 Broadcom Corporation + * + * Derived from bcm963xx_4.12L.06B_consumer/bcmdrivers/opensource/net/enet/impl4/bcmenet.c: + * Copyright (C) 2010 Broadcom Corporation + */ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <dma-uclass.h> +#include <memalign.h> +#include <reset.h> +#include <asm/io.h> + +#define DMA_RX_DESC 6 +#define DMA_TX_DESC 1 + +/* DMA Channels */ +#define DMA_CHAN_FLOWC(x) ((x) >> 1) +#define DMA_CHAN_MAX 16 +#define DMA_CHAN_SIZE 0x10 +#define DMA_CHAN_TOUT 500 + +/* DMA Global Configuration register */ +#define DMA_CFG_REG 0x00 +#define DMA_CFG_ENABLE_SHIFT 0 +#define DMA_CFG_ENABLE_MASK (1 << DMA_CFG_ENABLE_SHIFT) +#define DMA_CFG_FLOWC_ENABLE(x) BIT(DMA_CHAN_FLOWC(x) + 1) +#define DMA_CFG_NCHANS_SHIFT 24 +#define DMA_CFG_NCHANS_MASK (0xf << DMA_CFG_NCHANS_SHIFT) + +/* DMA Global Flow Control registers */ +#define DMA_FLOWC_THR_LO_REG(x) (0x04 + DMA_CHAN_FLOWC(x) * 0x0c) +#define DMA_FLOWC_THR_HI_REG(x) (0x08 + DMA_CHAN_FLOWC(x) * 0x0c) +#define DMA_FLOWC_ALLOC_REG(x) (0x0c + DMA_CHAN_FLOWC(x) * 0x0c) +#define DMA_FLOWC_ALLOC_FORCE_SHIFT 31 +#define DMA_FLOWC_ALLOC_FORCE_MASK (1 << DMA_FLOWC_ALLOC_FORCE_SHIFT) + +/* DMA Global Reset register */ +#define DMA_RST_REG 0x34 +#define DMA_RST_CHAN_SHIFT 0 +#define DMA_RST_CHAN_MASK(x) (1 << x) + +/* DMA Channel Configuration register */ +#define DMAC_CFG_REG(x) (DMA_CHAN_SIZE * (x) + 0x00) +#define DMAC_CFG_ENABLE_SHIFT 0 +#define DMAC_CFG_ENABLE_MASK (1 << DMAC_CFG_ENABLE_SHIFT) +#define DMAC_CFG_PKT_HALT_SHIFT 1 +#define DMAC_CFG_PKT_HALT_MASK (1 << DMAC_CFG_PKT_HALT_SHIFT) +#define DMAC_CFG_BRST_HALT_SHIFT 2 +#define DMAC_CFG_BRST_HALT_MASK (1 << DMAC_CFG_BRST_HALT_SHIFT) + +/* DMA Channel Max Burst Length register */ +#define DMAC_BURST_REG(x) (DMA_CHAN_SIZE * (x) + 0x0c) + +/* DMA SRAM Descriptor Ring Start register */ +#define DMAS_RSTART_REG(x) (DMA_CHAN_SIZE * (x) + 0x00) + +/* DMA SRAM State/Bytes done/ring offset register */ +#define DMAS_STATE_DATA_REG(x) (DMA_CHAN_SIZE * (x) + 0x04) + +/* DMA SRAM Buffer Descriptor status and length register */ +#define DMAS_DESC_LEN_STATUS_REG(x) (DMA_CHAN_SIZE * (x) + 0x08) + +/* DMA SRAM Buffer Descriptor status and length register */ +#define DMAS_DESC_BASE_BUFPTR_REG(x) (DMA_CHAN_SIZE * (x) + 0x0c) + +/* DMA Descriptor Status */ +#define DMAD_ST_CRC_SHIFT 8 +#define DMAD_ST_CRC_MASK (1 << DMAD_ST_CRC_SHIFT) +#define DMAD_ST_WRAP_SHIFT 12 +#define DMAD_ST_WRAP_MASK (1 << DMAD_ST_WRAP_SHIFT) +#define DMAD_ST_SOP_SHIFT 13 +#define DMAD_ST_SOP_MASK (1 << DMAD_ST_SOP_SHIFT) +#define DMAD_ST_EOP_SHIFT 14 +#define DMAD_ST_EOP_MASK (1 << DMAD_ST_EOP_SHIFT) +#define DMAD_ST_OWN_SHIFT 15 +#define DMAD_ST_OWN_MASK (1 << DMAD_ST_OWN_SHIFT) + +#define DMAD6348_ST_OV_ERR_SHIFT 0 +#define DMAD6348_ST_OV_ERR_MASK (1 << DMAD6348_ST_OV_ERR_SHIFT) +#define DMAD6348_ST_CRC_ERR_SHIFT 1 +#define DMAD6348_ST_CRC_ERR_MASK (1 << DMAD6348_ST_CRC_ERR_SHIFT) +#define DMAD6348_ST_RX_ERR_SHIFT 2 +#define DMAD6348_ST_RX_ERR_MASK (1 << DMAD6348_ST_RX_ERR_SHIFT) +#define DMAD6348_ST_OS_ERR_SHIFT 4 +#define DMAD6348_ST_OS_ERR_MASK (1 << DMAD6348_ST_OS_ERR_SHIFT) +#define DMAD6348_ST_UN_ERR_SHIFT 9 +#define DMAD6348_ST_UN_ERR_MASK (1 << DMAD6348_ST_UN_ERR_SHIFT) + +struct bcm6348_dma_desc { + uint16_t length; + uint16_t status; + uint32_t address; +}; + +struct bcm6348_chan_priv { + void __iomem *dma_ring; + uint8_t dma_ring_size; + uint8_t desc_id; + uint8_t desc_cnt; + bool *busy_desc; + bool running; +}; + +struct bcm6348_iudma_hw { + uint16_t err_mask; +}; + +struct bcm6348_iudma_priv { + const struct bcm6348_iudma_hw *hw; + void __iomem *base; + void __iomem *chan; + void __iomem *sram; + struct bcm6348_chan_priv **ch_priv; + uint8_t n_channels; +}; + +static inline bool bcm6348_iudma_chan_is_rx(uint8_t ch) +{ + return !(ch & 1); +} + +static inline void bcm6348_iudma_fdc(void *ptr, ulong size) +{ + ulong start = (ulong) ptr; + + flush_dcache_range(start, start + size); +} + +static inline void bcm6348_iudma_idc(void *ptr, ulong size) +{ + ulong start = (ulong) ptr; + + invalidate_dcache_range(start, start + size); +} + +static void bcm6348_iudma_chan_stop(struct bcm6348_iudma_priv *priv, + uint8_t ch) +{ + unsigned int timeout = DMA_CHAN_TOUT; + + do { + uint32_t cfg, halt; + + if (timeout > DMA_CHAN_TOUT / 2) + halt = DMAC_CFG_PKT_HALT_MASK; + else + halt = DMAC_CFG_BRST_HALT_MASK; + + /* try to stop dma channel */ + writel_be(halt, priv->chan + DMAC_CFG_REG(ch)); + mb(); + + /* check if channel was stopped */ + cfg = readl_be(priv->chan + DMAC_CFG_REG(ch)); + if (!(cfg & DMAC_CFG_ENABLE_MASK)) + break; + + udelay(1); + } while (--timeout); + + if (!timeout) + pr_err("unable to stop channel %u\n", ch); + + /* reset dma channel */ + setbits_be32(priv->base + DMA_RST_REG, DMA_RST_CHAN_MASK(ch)); + mb(); + clrbits_be32(priv->base + DMA_RST_REG, DMA_RST_CHAN_MASK(ch)); +} + +static int bcm6348_iudma_disable(struct dma *dma) +{ + struct bcm6348_iudma_priv *priv = dev_get_priv(dma->dev); + struct bcm6348_chan_priv *ch_priv = priv->ch_priv[dma->id]; + + /* stop dma channel */ + bcm6348_iudma_chan_stop(priv, dma->id); + + /* dma flow control */ + if (bcm6348_iudma_chan_is_rx(dma->id)) + writel_be(DMA_FLOWC_ALLOC_FORCE_MASK, + DMA_FLOWC_ALLOC_REG(dma->id)); + + /* init channel config */ + ch_priv->running = false; + ch_priv->desc_id = 0; + if (bcm6348_iudma_chan_is_rx(dma->id)) + ch_priv->desc_cnt = 0; + else + ch_priv->desc_cnt = ch_priv->dma_ring_size; + + return 0; +} + +static int bcm6348_iudma_enable(struct dma *dma) +{ + const struct bcm6348_iudma_priv *priv = dev_get_priv(dma->dev); + struct bcm6348_chan_priv *ch_priv = priv->ch_priv[dma->id]; + struct bcm6348_dma_desc *dma_desc = ch_priv->dma_ring; + uint8_t i; + + /* dma ring init */ + for (i = 0; i < ch_priv->desc_cnt; i++) { + if (bcm6348_iudma_chan_is_rx(dma->id)) { + ch_priv->busy_desc[i] = false; + dma_desc->status |= DMAD_ST_OWN_MASK; + } else { + dma_desc->status = 0; + dma_desc->length = 0; + dma_desc->address = 0; + } + + if (i == ch_priv->desc_cnt - 1) + dma_desc->status |= DMAD_ST_WRAP_MASK; + + dma_desc++; + } + + /* init to first descriptor */ + ch_priv->desc_id = 0; + + /* force cache writeback */ + bcm6348_iudma_fdc(ch_priv->dma_ring, + sizeof(*dma_desc) * ch_priv->desc_cnt); + + /* clear sram */ + writel_be(0, priv->sram + DMAS_STATE_DATA_REG(dma->id)); + writel_be(0, priv->sram + DMAS_DESC_LEN_STATUS_REG(dma->id)); + writel_be(0, priv->sram + DMAS_DESC_BASE_BUFPTR_REG(dma->id)); + + /* set dma ring start */ + writel_be(virt_to_phys(ch_priv->dma_ring), + priv->sram + DMAS_RSTART_REG(dma->id)); + + /* set flow control */ + if (bcm6348_iudma_chan_is_rx(dma->id)) { + u32 val; + + setbits_be32(priv->base + DMA_CFG_REG, + DMA_CFG_FLOWC_ENABLE(dma->id)); + + val = ch_priv->desc_cnt / 3; + writel_be(val, priv->base + DMA_FLOWC_THR_LO_REG(dma->id)); + + val = (ch_priv->desc_cnt * 2) / 3; + writel_be(val, priv->base + DMA_FLOWC_THR_HI_REG(dma->id)); + + writel_be(0, priv->base + DMA_FLOWC_ALLOC_REG(dma->id)); + } + + /* set dma max burst */ + writel_be(ch_priv->desc_cnt, + priv->chan + DMAC_BURST_REG(dma->id)); + + /* kick rx dma channel */ + if (bcm6348_iudma_chan_is_rx(dma->id)) + setbits_be32(priv->chan + DMAC_CFG_REG(dma->id), + DMAC_CFG_ENABLE_MASK); + + /* channel is now enabled */ + ch_priv->running = true; + + return 0; +} + +static int bcm6348_iudma_request(struct dma *dma) +{ + const struct bcm6348_iudma_priv *priv = dev_get_priv(dma->dev); + struct bcm6348_chan_priv *ch_priv; + + /* check if channel is valid */ + if (dma->id >= priv->n_channels) + return -ENODEV; + + /* alloc channel private data */ + priv->ch_priv[dma->id] = calloc(1, sizeof(struct bcm6348_chan_priv)); + if (!priv->ch_priv[dma->id]) + return -ENOMEM; + ch_priv = priv->ch_priv[dma->id]; + + /* alloc dma ring */ + if (bcm6348_iudma_chan_is_rx(dma->id)) + ch_priv->dma_ring_size = DMA_RX_DESC; + else + ch_priv->dma_ring_size = DMA_TX_DESC; + + ch_priv->dma_ring = + malloc_cache_aligned(sizeof(struct bcm6348_dma_desc) * + ch_priv->dma_ring_size); + if (!ch_priv->dma_ring) + return -ENOMEM; + + /* init channel config */ + ch_priv->running = false; + ch_priv->desc_id = 0; + if (bcm6348_iudma_chan_is_rx(dma->id)) { + ch_priv->desc_cnt = 0; + ch_priv->busy_desc = calloc(ch_priv->desc_cnt, sizeof(bool)); + } else { + ch_priv->desc_cnt = ch_priv->dma_ring_size; + ch_priv->busy_desc = NULL; + } + + return 0; +} + +static int bcm6348_iudma_receive(struct dma *dma, void **dst, void *metadata) +{ + const struct bcm6348_iudma_priv *priv = dev_get_priv(dma->dev); + const struct bcm6348_iudma_hw *hw = priv->hw; + struct bcm6348_chan_priv *ch_priv = priv->ch_priv[dma->id]; + struct bcm6348_dma_desc *dma_desc = dma_desc = ch_priv->dma_ring; + int ret; + + /* get dma ring descriptor address */ + dma_desc += ch_priv->desc_id; + + /* invalidate cache data */ + bcm6348_iudma_idc(dma_desc, sizeof(*dma_desc)); + + /* check dma own */ + if (dma_desc->status & DMAD_ST_OWN_MASK) + return -EAGAIN; + + /* check pkt */ + if (!(dma_desc->status & DMAD_ST_EOP_MASK) || + !(dma_desc->status & DMAD_ST_SOP_MASK) || + (dma_desc->status & hw->err_mask)) { + pr_err("invalid pkt received (ch=%ld desc=%u) (st=%04x)\n", + dma->id, ch_priv->desc_id, dma_desc->status); + ret = -EAGAIN; + } else { + /* set dma buffer address */ + *dst = phys_to_virt(dma_desc->address); + + /* invalidate cache data */ + bcm6348_iudma_idc(*dst, dma_desc->length); + + /* return packet length */ + ret = dma_desc->length; + } + + /* busy dma descriptor */ + ch_priv->busy_desc[ch_priv->desc_id] = true; + + /* increment dma descriptor */ + ch_priv->desc_id = (ch_priv->desc_id + 1) % ch_priv->desc_cnt; + + return ret; +} + +static int bcm6348_iudma_send(struct dma *dma, void *src, size_t len, + void *metadata) +{ + const struct bcm6348_iudma_priv *priv = dev_get_priv(dma->dev); + struct bcm6348_chan_priv *ch_priv = priv->ch_priv[dma->id]; + struct bcm6348_dma_desc *dma_desc; + uint16_t status; + + /* flush cache */ + bcm6348_iudma_fdc(src, len); + + /* get dma ring descriptor address */ + dma_desc = ch_priv->dma_ring; + dma_desc += ch_priv->desc_id; + + /* config dma descriptor */ + status = (DMAD_ST_OWN_MASK | + DMAD_ST_EOP_MASK | + DMAD_ST_CRC_MASK | + DMAD_ST_SOP_MASK); + if (ch_priv->desc_id == ch_priv->desc_cnt - 1) + status |= DMAD_ST_WRAP_MASK; + + /* set dma descriptor */ + dma_desc->address = virt_to_phys(src); + dma_desc->length = len; + dma_desc->status = status; + + /* flush cache */ + bcm6348_iudma_fdc(dma_desc, sizeof(*dma_desc)); + + /* kick tx dma channel */ + setbits_be32(priv->chan + DMAC_CFG_REG(dma->id), DMAC_CFG_ENABLE_MASK); + + /* poll dma status */ + do { + /* invalidate cache */ + bcm6348_iudma_idc(dma_desc, sizeof(*dma_desc)); + + if (!(dma_desc->status & DMAD_ST_OWN_MASK)) + break; + } while(1); + + /* increment dma descriptor */ + ch_priv->desc_id = (ch_priv->desc_id + 1) % ch_priv->desc_cnt; + + return 0; +} + +static int bcm6348_iudma_free_rcv_buf(struct dma *dma, void *dst, size_t size) +{ + const struct bcm6348_iudma_priv *priv = dev_get_priv(dma->dev); + struct bcm6348_chan_priv *ch_priv = priv->ch_priv[dma->id]; + struct bcm6348_dma_desc *dma_desc = ch_priv->dma_ring; + uint16_t status; + uint8_t i; + u32 cfg; + + /* get dirty dma descriptor */ + for (i = 0; i < ch_priv->desc_cnt; i++) { + if (phys_to_virt(dma_desc->address) == dst) + break; + + dma_desc++; + } + + /* dma descriptor not found */ + if (i == ch_priv->desc_cnt) { + pr_err("dirty dma descriptor not found\n"); + return -ENOENT; + } + + /* invalidate cache */ + bcm6348_iudma_idc(ch_priv->dma_ring, + sizeof(*dma_desc) * ch_priv->desc_cnt); + + /* free dma descriptor */ + ch_priv->busy_desc[i] = false; + + status = DMAD_ST_OWN_MASK; + if (i == ch_priv->desc_cnt - 1) + status |= DMAD_ST_WRAP_MASK; + + dma_desc->status |= status; + dma_desc->length = PKTSIZE_ALIGN; + + /* tell dma we allocated one buffer */ + writel_be(1, DMA_FLOWC_ALLOC_REG(dma->id)); + + /* flush cache */ + bcm6348_iudma_fdc(ch_priv->dma_ring, + sizeof(*dma_desc) * ch_priv->desc_cnt); + + /* kick rx dma channel if disabled */ + cfg = readl_be(priv->chan + DMAC_CFG_REG(dma->id)); + if (!(cfg & DMAC_CFG_ENABLE_MASK)) + setbits_be32(priv->chan + DMAC_CFG_REG(dma->id), + DMAC_CFG_ENABLE_MASK); + + return 0; +} + +static int bcm6348_iudma_add_rcv_buf(struct dma *dma, void *dst, size_t size) +{ + const struct bcm6348_iudma_priv *priv = dev_get_priv(dma->dev); + struct bcm6348_chan_priv *ch_priv = priv->ch_priv[dma->id]; + struct bcm6348_dma_desc *dma_desc = ch_priv->dma_ring; + + /* no more dma descriptors available */ + if (ch_priv->desc_cnt == ch_priv->dma_ring_size) { + pr_err("max number of buffers reached\n"); + return -EINVAL; + } + + /* get next dma descriptor */ + dma_desc += ch_priv->desc_cnt; + + /* init dma descriptor */ + dma_desc->address = virt_to_phys(dst); + dma_desc->length = size; + dma_desc->status = 0; + + /* flush cache */ + bcm6348_iudma_fdc(dma_desc, sizeof(*dma_desc)); + + /* increment dma descriptors */ + ch_priv->desc_cnt++; + + return 0; +} + +static int bcm6348_iudma_prepare_rcv_buf(struct dma *dma, void *dst, + size_t size) +{ + const struct bcm6348_iudma_priv *priv = dev_get_priv(dma->dev); + struct bcm6348_chan_priv *ch_priv = priv->ch_priv[dma->id]; + + /* only add new rx buffers if channel isn't running */ + if (ch_priv->running) + return bcm6348_iudma_free_rcv_buf(dma, dst, size); + else + return bcm6348_iudma_add_rcv_buf(dma, dst, size); +} + +static const struct dma_ops bcm6348_iudma_ops = { + .disable = bcm6348_iudma_disable, + .enable = bcm6348_iudma_enable, + .prepare_rcv_buf = bcm6348_iudma_prepare_rcv_buf, + .request = bcm6348_iudma_request, + .receive = bcm6348_iudma_receive, + .send = bcm6348_iudma_send, +}; + +static const struct bcm6348_iudma_hw bcm6348_hw = { + .err_mask = (DMAD6348_ST_OV_ERR_MASK | + DMAD6348_ST_CRC_ERR_MASK | + DMAD6348_ST_RX_ERR_MASK | + DMAD6348_ST_OS_ERR_MASK | + DMAD6348_ST_UN_ERR_MASK), +}; + +static const struct bcm6348_iudma_hw bcm6368_hw = { + .err_mask = 0, +}; + +static const struct udevice_id bcm6348_iudma_ids[] = { + { + .compatible = "brcm,bcm6348-iudma", + .data = (ulong)&bcm6348_hw, + }, { + .compatible = "brcm,bcm6368-iudma", + .data = (ulong)&bcm6368_hw, + }, { /* sentinel */ } +}; + +static int bcm6348_iudma_probe(struct udevice *dev) +{ + struct dma_dev_priv *uc_priv = dev_get_uclass_priv(dev); + struct bcm6348_iudma_priv *priv = dev_get_priv(dev); + const struct bcm6348_iudma_hw *hw = + (const struct bcm6348_iudma_hw *)dev_get_driver_data(dev); + uint8_t ch; + int i; + + uc_priv->supported = (DMA_SUPPORTS_DEV_TO_MEM | + DMA_SUPPORTS_MEM_TO_DEV); + priv->hw = hw; + + /* dma global base address */ + priv->base = dev_remap_addr_name(dev, "dma"); + if (!priv->base) + return -EINVAL; + + /* dma channels base address */ + priv->chan = dev_remap_addr_name(dev, "dma-channels"); + if (!priv->chan) + return -EINVAL; + + /* dma sram base address */ + priv->sram = dev_remap_addr_name(dev, "dma-sram"); + if (!priv->sram) + return -EINVAL; + + /* get number of channels */ + priv->n_channels = dev_read_u32_default(dev, "dma-channels", 8); + if (priv->n_channels > DMA_CHAN_MAX) + return -EINVAL; + + /* try to enable clocks */ + for (i = 0; ; i++) { + struct clk clk; + int ret; + + ret = clk_get_by_index(dev, i, &clk); + if (ret < 0) + break; + + ret = clk_enable(&clk); + if (ret < 0) { + pr_err("error enabling clock %d\n", i); + return ret; + } + + ret = clk_free(&clk); + if (ret < 0) { + pr_err("error freeing clock %d\n", i); + return ret; + } + } + + /* try to perform resets */ + for (i = 0; ; i++) { + struct reset_ctl reset; + int ret; + + ret = reset_get_by_index(dev, i, &reset); + if (ret < 0) + break; + + ret = reset_deassert(&reset); + if (ret < 0) { + pr_err("error deasserting reset %d\n", i); + return ret; + } + + ret = reset_free(&reset); + if (ret < 0) { + pr_err("error freeing reset %d\n", i); + return ret; + } + } + + /* disable dma controller */ + clrbits_be32(priv->base + DMA_CFG_REG, DMA_CFG_ENABLE_MASK); + + /* alloc channel private data pointers */ + priv->ch_priv = calloc(priv->n_channels, + sizeof(struct bcm6348_chan_priv*)); + if (!priv->ch_priv) + return -ENOMEM; + + /* stop dma channels */ + for (ch = 0; ch < priv->n_channels; ch++) + bcm6348_iudma_chan_stop(priv, ch); + + /* enable dma controller */ + setbits_be32(priv->base + DMA_CFG_REG, DMA_CFG_ENABLE_MASK); + + return 0; +} + +U_BOOT_DRIVER(bcm6348_iudma) = { + .name = "bcm6348_iudma", + .id = UCLASS_DMA, + .of_match = bcm6348_iudma_ids, + .ops = &bcm6348_iudma_ops, + .priv_auto_alloc_size = sizeof(struct bcm6348_iudma_priv), + .probe = bcm6348_iudma_probe, +}; diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index 50e901973d1..8f59193e3c2 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -31,6 +31,17 @@ config FPGA_CYCLON2 Enable FPGA driver for loading bitstream in BIT and BIN format on Altera Cyclone II device. +config FPGA_STRATIX10 + bool "Enable Altera FPGA driver for Stratix 10" + depends on TARGET_SOCFPGA_STRATIX10 + select FPGA_ALTERA + help + Say Y here to enable the Altera Stratix 10 FPGA specific driver + + This provides common functionality for Altera Stratix 10 devices. + Enable FPGA driver for writing bitstream into Altera Stratix10 + device. + config FPGA_XILINX bool "Enable Xilinx FPGA drivers" select FPGA diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index 97d7d5d9be3..5a778c10e80 100644 --- a/drivers/fpga/Makefile +++ b/drivers/fpga/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_FPGA_ACEX1K) += ACEX1K.o obj-$(CONFIG_FPGA_CYCLON2) += cyclon2.o obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o obj-$(CONFIG_FPGA_STRATIX_V) += stratixv.o +obj-$(CONFIG_FPGA_STRATIX10) += stratix10.o obj-$(CONFIG_FPGA_SOCFPGA) += socfpga.o obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += socfpga_gen5.o obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += socfpga_arria10.o diff --git a/drivers/fpga/altera.c b/drivers/fpga/altera.c index 9605554c6aa..7c8f5185095 100644 --- a/drivers/fpga/altera.c +++ b/drivers/fpga/altera.c @@ -39,6 +39,9 @@ static const struct altera_fpga { #if defined(CONFIG_FPGA_STRATIX_V) { Altera_StratixV, "StratixV", stratixv_load, NULL, NULL }, #endif +#if defined(CONFIG_FPGA_STRATIX10) + { Intel_FPGA_Stratix10, "Stratix10", stratix10_load, NULL, NULL }, +#endif #if defined(CONFIG_FPGA_SOCFPGA) { Altera_SoCFPGA, "SoC FPGA", socfpga_load, NULL, NULL }, #endif @@ -154,6 +157,9 @@ int altera_info(Altera_desc *desc) case fast_passive_parallel_security: printf("Fast Passive Parallel with Security (FPPS)\n"); break; + case secure_device_manager_mailbox: + puts("Secure Device Manager (SDM) Mailbox\n"); + break; /* Add new interface types here */ default: printf("Unsupported interface type, %d\n", desc->iface); diff --git a/drivers/fpga/stratix10.c b/drivers/fpga/stratix10.c new file mode 100644 index 00000000000..aae052130e0 --- /dev/null +++ b/drivers/fpga/stratix10.c @@ -0,0 +1,288 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Intel Corporation <www.intel.com> + */ + +#include <common.h> +#include <altera.h> +#include <asm/arch/mailbox_s10.h> + +#define RECONFIG_STATUS_POLL_RESP_TIMEOUT_MS 60000 +#define RECONFIG_STATUS_INTERVAL_DELAY_US 1000000 + +static const struct mbox_cfgstat_state { + int err_no; + const char *error_name; +} mbox_cfgstat_state[] = { + {MBOX_CFGSTAT_STATE_IDLE, "FPGA in idle mode."}, + {MBOX_CFGSTAT_STATE_CONFIG, "FPGA in config mode."}, + {MBOX_CFGSTAT_STATE_FAILACK, "Acknowledgment failed!"}, + {MBOX_CFGSTAT_STATE_ERROR_INVALID, "Invalid bitstream!"}, + {MBOX_CFGSTAT_STATE_ERROR_CORRUPT, "Corrupted bitstream!"}, + {MBOX_CFGSTAT_STATE_ERROR_AUTH, "Authentication failed!"}, + {MBOX_CFGSTAT_STATE_ERROR_CORE_IO, "I/O error!"}, + {MBOX_CFGSTAT_STATE_ERROR_HARDWARE, "Hardware error!"}, + {MBOX_CFGSTAT_STATE_ERROR_FAKE, "Fake error!"}, + {MBOX_CFGSTAT_STATE_ERROR_BOOT_INFO, "Error in boot info!"}, + {MBOX_CFGSTAT_STATE_ERROR_QSPI_ERROR, "Error in QSPI!"}, + {MBOX_RESP_ERROR, "Mailbox general error!"}, + {-ETIMEDOUT, "I/O timeout error"}, + {-1, "Unknown error!"} +}; + +#define MBOX_CFGSTAT_MAX ARRAY_SIZE(mbox_cfgstat_state) + +static const char *mbox_cfgstat_to_str(int err) +{ + int i; + + for (i = 0; i < MBOX_CFGSTAT_MAX - 1; i++) { + if (mbox_cfgstat_state[i].err_no == err) + return mbox_cfgstat_state[i].error_name; + } + + return mbox_cfgstat_state[MBOX_CFGSTAT_MAX - 1].error_name; +} + +/* + * Add the ongoing transaction's command ID into pending list and return + * the command ID for next transfer. + */ +static u8 add_transfer(u32 *xfer_pending_list, size_t list_size, u8 id) +{ + int i; + + for (i = 0; i < list_size; i++) { + if (xfer_pending_list[i]) + continue; + xfer_pending_list[i] = id; + debug("ID(%d) added to transaction pending list\n", id); + /* + * Increment command ID for next transaction. + * Valid command ID (4 bits) is from 1 to 15. + */ + id = (id % 15) + 1; + break; + } + + return id; +} + +/* + * Check whether response ID match the command ID in the transfer + * pending list. If a match is found in the transfer pending list, + * it clears the transfer pending list and return the matched + * command ID. + */ +static int get_and_clr_transfer(u32 *xfer_pending_list, size_t list_size, + u8 id) +{ + int i; + + for (i = 0; i < list_size; i++) { + if (id != xfer_pending_list[i]) + continue; + xfer_pending_list[i] = 0; + return id; + } + + return 0; +} + +/* + * Polling the FPGA configuration status. + * Return 0 for success, non-zero for error. + */ +static int reconfig_status_polling_resp(void) +{ + int ret; + unsigned long start = get_timer(0); + + while (1) { + ret = mbox_get_fpga_config_status(MBOX_RECONFIG_STATUS); + if (!ret) + return 0; /* configuration success */ + + if (ret != MBOX_CFGSTAT_STATE_CONFIG) + return ret; + + if (get_timer(start) > RECONFIG_STATUS_POLL_RESP_TIMEOUT_MS) + break; /* time out */ + + puts("."); + udelay(RECONFIG_STATUS_INTERVAL_DELAY_US); + } + + return -ETIMEDOUT; +} + +static u32 get_resp_hdr(u32 *r_index, u32 *w_index, u32 *resp_count, + u32 *resp_buf, u32 buf_size, u32 client_id) +{ + u32 buf[MBOX_RESP_BUFFER_SIZE]; + u32 mbox_hdr; + u32 resp_len; + u32 hdr_len; + u32 i; + + if (*resp_count < buf_size) { + u32 rcv_len_max = buf_size - *resp_count; + + if (rcv_len_max > MBOX_RESP_BUFFER_SIZE) + rcv_len_max = MBOX_RESP_BUFFER_SIZE; + resp_len = mbox_rcv_resp(buf, rcv_len_max); + + for (i = 0; i < resp_len; i++) { + resp_buf[(*w_index)++] = buf[i]; + *w_index %= buf_size; + (*resp_count)++; + } + } + + /* No response in buffer */ + if (*resp_count == 0) + return 0; + + mbox_hdr = resp_buf[*r_index]; + + hdr_len = MBOX_RESP_LEN_GET(mbox_hdr); + + /* Insufficient header length to return a mailbox header */ + if ((*resp_count - 1) < hdr_len) + return 0; + + *r_index += (hdr_len + 1); + *r_index %= buf_size; + *resp_count -= (hdr_len + 1); + + /* Make sure response belongs to us */ + if (MBOX_RESP_CLIENT_GET(mbox_hdr) != client_id) + return 0; + + return mbox_hdr; +} + +/* Send bit stream data to SDM via RECONFIG_DATA mailbox command */ +static int send_reconfig_data(const void *rbf_data, size_t rbf_size, + u32 xfer_max, u32 buf_size_max) +{ + u32 response_buffer[MBOX_RESP_BUFFER_SIZE]; + u32 xfer_pending[MBOX_RESP_BUFFER_SIZE]; + u32 resp_rindex = 0; + u32 resp_windex = 0; + u32 resp_count = 0; + u32 xfer_count = 0; + u8 resp_err = 0; + u8 cmd_id = 1; + u32 args[3]; + int ret; + + debug("SDM xfer_max = %d\n", xfer_max); + debug("SDM buf_size_max = %x\n\n", buf_size_max); + + memset(xfer_pending, 0, sizeof(xfer_pending)); + + while (rbf_size || xfer_count) { + if (!resp_err && rbf_size && xfer_count < xfer_max) { + args[0] = MBOX_ARG_DESC_COUNT(1); + args[1] = (u64)rbf_data; + if (rbf_size >= buf_size_max) { + args[2] = buf_size_max; + rbf_size -= buf_size_max; + rbf_data += buf_size_max; + } else { + args[2] = (u64)rbf_size; + rbf_size = 0; + } + + ret = mbox_send_cmd_only(cmd_id, MBOX_RECONFIG_DATA, + MBOX_CMD_INDIRECT, 3, args); + if (ret) { + resp_err = 1; + } else { + xfer_count++; + cmd_id = add_transfer(xfer_pending, + MBOX_RESP_BUFFER_SIZE, + cmd_id); + } + puts("."); + } else { + u32 resp_hdr = get_resp_hdr(&resp_rindex, &resp_windex, + &resp_count, + response_buffer, + MBOX_RESP_BUFFER_SIZE, + MBOX_CLIENT_ID_UBOOT); + + /* + * If no valid response header found or + * non-zero length from RECONFIG_DATA + */ + if (!resp_hdr || MBOX_RESP_LEN_GET(resp_hdr)) + continue; + + /* Check for response's status */ + if (!resp_err) { + ret = MBOX_RESP_ERR_GET(resp_hdr); + debug("Response error code: %08x\n", ret); + /* Error in response */ + if (ret) + resp_err = 1; + } + + ret = get_and_clr_transfer(xfer_pending, + MBOX_RESP_BUFFER_SIZE, + MBOX_RESP_ID_GET(resp_hdr)); + if (ret) { + /* Claim and reuse the ID */ + cmd_id = (u8)ret; + xfer_count--; + } + + if (resp_err && !xfer_count) + return ret; + } + } + + return 0; +} + +/* + * This is the interface used by FPGA driver. + * Return 0 for success, non-zero for error. + */ +int stratix10_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size) +{ + int ret; + u32 resp_len = 2; + u32 resp_buf[2]; + + debug("Sending MBOX_RECONFIG...\n"); + ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_RECONFIG, MBOX_CMD_DIRECT, 0, + NULL, 0, &resp_len, resp_buf); + if (ret) { + puts("Failure in RECONFIG mailbox command!\n"); + return ret; + } + + ret = send_reconfig_data(rbf_data, rbf_size, resp_buf[0], resp_buf[1]); + if (ret) { + printf("RECONFIG_DATA error: %08x, %s\n", ret, + mbox_cfgstat_to_str(ret)); + return ret; + } + + /* Make sure we don't send MBOX_RECONFIG_STATUS too fast */ + udelay(RECONFIG_STATUS_INTERVAL_DELAY_US); + + debug("Polling with MBOX_RECONFIG_STATUS...\n"); + ret = reconfig_status_polling_resp(); + if (ret) { + printf("RECONFIG_STATUS Error: %08x, %s\n", ret, + mbox_cfgstat_to_str(ret)); + return ret; + } + + puts("FPGA reconfiguration OK!\n"); + + return ret; +} diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 35344e57c6c..c8c6c60623e 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -99,6 +99,13 @@ config LPC32XX_GPIO help Support for the LPC32XX GPIO driver. +config MSCC_BITBANG_SPI_GPIO + bool "Microsemi bitbang spi GPIO driver" + depends on DM_GPIO && SOC_VCOREIII + help + Support controlling the GPIO used for SPI bitbang by software. Can + be used by the VCoreIII SoCs, but it was mainly useful for Luton. + config MSM_GPIO bool "Qualcomm GPIO driver" depends on DM_GPIO diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 7ed9a4ec422..61feda15372 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -59,3 +59,4 @@ obj-$(CONFIG_MSM_GPIO) += msm_gpio.o obj-$(CONFIG_$(SPL_)PCF8575_GPIO) += pcf8575_gpio.o obj-$(CONFIG_PM8916_GPIO) += pm8916_gpio.o obj-$(CONFIG_MT7621_GPIO) += mt7621_gpio.o +obj-$(CONFIG_MSCC_BITBANG_SPI_GPIO) += gpio-mscc-bitbang-spi.o diff --git a/drivers/gpio/gpio-mscc-bitbang-spi.c b/drivers/gpio/gpio-mscc-bitbang-spi.c new file mode 100644 index 00000000000..b675f9052c1 --- /dev/null +++ b/drivers/gpio/gpio-mscc-bitbang-spi.c @@ -0,0 +1,122 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Microsemi SoCs pinctrl driver + * + * Author: <gregory.clement@bootlin.com> + * License: Dual MIT/GPL + * Copyright (c) 2018 Microsemi Corporation + */ + +#include <common.h> +#include <asm-generic/gpio.h> +#include <asm/io.h> +#include <dm.h> +#include <errno.h> + +enum { + SDI, + CS0, + CS1, + CS2, + CS3, + SDO, + SCK +}; + +static const int pinmap[] = { 0, 5, 6, 7, 8, 10, 12 }; + +#define SW_SPI_CSn_OE 0x1E /* bits 1 to 4 */ +#define SW_SPI_CS0_OE BIT(1) +#define SW_SPI_SDO_OE BIT(9) +#define SW_SPI_SCK_OE BIT(11) +#define SW_PIN_CTRL_MODE BIT(13) + +struct mscc_bb_spi_gpio { + void __iomem *regs; + u32 cache_val; +}; + +static int mscc_bb_spi_gpio_set(struct udevice *dev, unsigned oft, int val) +{ + struct mscc_bb_spi_gpio *gpio = dev_get_priv(dev); + + if (val) + gpio->cache_val |= BIT(pinmap[oft]); + else + gpio->cache_val &= ~BIT(pinmap[oft]); + + writel(gpio->cache_val, gpio->regs); + + return 0; +} + +static int mscc_bb_spi_gpio_direction_output(struct udevice *dev, unsigned oft, + int val) +{ + if (oft == 0) { + pr_err("SW_SPI_DSI can't be used as output\n"); + return -ENOTSUPP; + } + + mscc_bb_spi_gpio_set(dev, oft, val); + + return 0; +} + +static int mscc_bb_spi_gpio_direction_input(struct udevice *dev, unsigned oft) +{ + return 0; +} + +static int mscc_bb_spi_gpio_get(struct udevice *dev, unsigned int oft) +{ + struct mscc_bb_spi_gpio *gpio = dev_get_priv(dev); + u32 val = readl(gpio->regs); + + return !!(val & BIT(pinmap[oft])); +} + +static const struct dm_gpio_ops mscc_bb_spi_gpio_ops = { + .direction_output = mscc_bb_spi_gpio_direction_output, + .direction_input = mscc_bb_spi_gpio_direction_input, + .set_value = mscc_bb_spi_gpio_set, + .get_value = mscc_bb_spi_gpio_get, +}; + +static int mscc_bb_spi_gpio_probe(struct udevice *dev) +{ + struct mscc_bb_spi_gpio *gpio = dev_get_priv(dev); + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + + gpio->regs = dev_remap_addr(dev); + if (!gpio->regs) + return -EINVAL; + + uc_priv->bank_name = dev->name; + uc_priv->gpio_count = ARRAY_SIZE(pinmap); + /* + * Enable software mode to control the SPI pin, enables the + * output mode for most of the pin and initialize the cache + * value in the same time + */ + + gpio->cache_val = SW_PIN_CTRL_MODE | SW_SPI_SCK_OE | SW_SPI_SDO_OE | + SW_SPI_CS0_OE; + writel(gpio->cache_val, gpio->regs); + + return 0; +} + +static const struct udevice_id mscc_bb_spi_gpio_ids[] = { + {.compatible = "mscc,spi-bitbang-gpio"}, + {} +}; + +U_BOOT_DRIVER(gpio_mscc_bb_spi) = { + .name = "gpio-mscc-spi-bitbang", + .id = UCLASS_GPIO, + .ops = &mscc_bb_spi_gpio_ops, + .probe = mscc_bb_spi_gpio_probe, + .of_match = of_match_ptr(mscc_bb_spi_gpio_ids), + .priv_auto_alloc_size = sizeof(struct mscc_bb_spi_gpio), +}; diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c index b820160ae79..8bd30c75b2f 100644 --- a/drivers/gpio/mxc_gpio.c +++ b/drivers/gpio/mxc_gpio.c @@ -40,15 +40,15 @@ static unsigned long gpio_ports[] = { [2] = GPIO3_BASE_ADDR, #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \ defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ - defined(CONFIG_MX7) || defined(CONFIG_MX8M) || \ + defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || \ defined(CONFIG_ARCH_IMX8) [3] = GPIO4_BASE_ADDR, #endif #if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ - defined(CONFIG_MX7) || defined(CONFIG_MX8M) || \ + defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || \ defined(CONFIG_ARCH_IMX8) [4] = GPIO5_BASE_ADDR, -#if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || defined(CONFIG_MX8M)) +#if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || defined(CONFIG_IMX8M)) [5] = GPIO6_BASE_ADDR, #endif #endif @@ -353,13 +353,13 @@ static const struct mxc_gpio_plat mxc_plat[] = { { 2, (struct gpio_regs *)GPIO3_BASE_ADDR }, #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \ defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ - defined(CONFIG_MX8M) || defined(CONFIG_ARCH_IMX8) + defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8) { 3, (struct gpio_regs *)GPIO4_BASE_ADDR }, #endif #if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ - defined(CONFIG_MX8M) || defined(CONFIG_ARCH_IMX8) + defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8) { 4, (struct gpio_regs *)GPIO5_BASE_ADDR }, -#ifndef CONFIG_MX8M +#ifndef CONFIG_IMX8M { 5, (struct gpio_regs *)GPIO6_BASE_ADDR }, #endif #endif @@ -377,13 +377,13 @@ U_BOOT_DEVICES(mxc_gpios) = { { "gpio_mxc", &mxc_plat[2] }, #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \ defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ - defined(CONFIG_MX8M) || defined(CONFIG_ARCH_IMX8) + defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8) { "gpio_mxc", &mxc_plat[3] }, #endif #if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ - defined(CONFIG_MX8M) || defined(CONFIG_ARCH_IMX8) + defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8) { "gpio_mxc", &mxc_plat[4] }, -#ifndef CONFIG_MX8M +#ifndef CONFIG_IMX8M { "gpio_mxc", &mxc_plat[5] }, #endif #endif diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 48febc47d26..704c8dd1955 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -120,6 +120,12 @@ config FSL_SEC_MON Security Monitor can be transitioned on any security failures, like software violations or hardware security violations. +config JZ4780_EFUSE + bool "Ingenic JZ4780 eFUSE support" + depends on ARCH_JZ47XX + help + This selects support for the eFUSE on Ingenic JZ4780 SoCs. + config MXC_OCOTP bool "Enable MXC OCOTP Driver" help diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 302d4415927..6bdf5054f47 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -62,3 +62,4 @@ obj-$(CONFIG_TEGRA_CAR) += tegra_car.o obj-$(CONFIG_TWL4030_LED) += twl4030_led.o obj-$(CONFIG_VEXPRESS_CONFIG) += vexpress_config.o obj-$(CONFIG_WINBOND_W83627) += winbond_w83627.o +obj-$(CONFIG_JZ4780_EFUSE) += jz4780_efuse.o diff --git a/drivers/misc/jz4780_efuse.c b/drivers/misc/jz4780_efuse.c new file mode 100644 index 00000000000..bc3dc93af2d --- /dev/null +++ b/drivers/misc/jz4780_efuse.c @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * JZ4780 EFUSE driver + * + * Copyright (c) 2014 Imagination Technologies + * Author: Alex Smith <alex.smith@imgtec.com> + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/unaligned.h> +#include <errno.h> +#include <mach/jz4780.h> +#include <wait_bit.h> + +#define EFUSE_EFUCTRL 0xd0 +#define EFUSE_EFUCFG 0xd4 +#define EFUSE_EFUSTATE 0xd8 +#define EFUSE_EFUDATA(n) (0xdc + ((n) * 4)) + +#define EFUSE_EFUCTRL_RD_EN BIT(0) +#define EFUSE_EFUCTRL_LEN_BIT 16 +#define EFUSE_EFUCTRL_LEN_MASK 0x1f +#define EFUSE_EFUCTRL_ADDR_BIT 21 +#define EFUSE_EFUCTRL_ADDR_MASK 0x1ff +#define EFUSE_EFUCTRL_CS BIT(30) + +#define EFUSE_EFUCFG_RD_STROBE_BIT 16 +#define EFUSE_EFUCFG_RD_STROBE_MASK 0xf +#define EFUSE_EFUCFG_RD_ADJ_BIT 20 +#define EFUSE_EFUCFG_RD_ADJ_MASK 0xf + +#define EFUSE_EFUSTATE_RD_DONE BIT(0) + +static void jz4780_efuse_read_chunk(size_t addr, size_t count, u8 *buf) +{ + void __iomem *regs = (void __iomem *)NEMC_BASE; + size_t i; + u32 val; + int ret; + + val = EFUSE_EFUCTRL_RD_EN | + ((count - 1) << EFUSE_EFUCTRL_LEN_BIT) | + (addr << EFUSE_EFUCTRL_ADDR_BIT) | + ((addr > 0x200) ? EFUSE_EFUCTRL_CS : 0); + writel(val, regs + EFUSE_EFUCTRL); + + ret = wait_for_bit_le32(regs + EFUSE_EFUSTATE, + EFUSE_EFUSTATE_RD_DONE, true, 10000, false); + if (ret) + return; + + if ((count % 4) == 0) { + for (i = 0; i < count / 4; i++) { + val = readl(regs + EFUSE_EFUDATA(i)); + put_unaligned(val, (u32 *)(buf + (i * 4))); + } + } else { + val = readl(regs + EFUSE_EFUDATA(0)); + if (count > 2) + buf[2] = (val >> 16) & 0xff; + if (count > 1) + buf[1] = (val >> 8) & 0xff; + buf[0] = val & 0xff; + } +} + +static inline int jz4780_efuse_chunk_size(size_t count) +{ + if (count >= 32) + return 32; + else if ((count / 4) > 0) + return (count / 4) * 4; + else + return count % 4; +} + +void jz4780_efuse_read(size_t addr, size_t count, u8 *buf) +{ + size_t chunk; + + while (count > 0) { + chunk = jz4780_efuse_chunk_size(count); + jz4780_efuse_read_chunk(addr, chunk, buf); + addr += chunk; + buf += chunk; + count -= chunk; + } +} + +void jz4780_efuse_init(u32 ahb2_rate) +{ + void __iomem *regs = (void __iomem *)NEMC_BASE; + u32 rd_adj, rd_strobe, tmp; + + rd_adj = (((6500 * (ahb2_rate / 1000000)) / 1000000) + 0xf) / 2; + tmp = (((35000 * (ahb2_rate / 1000000)) / 1000000) - 4) - rd_adj; + rd_strobe = ((tmp + 0xf) / 2 < 7) ? 7 : (tmp + 0xf) / 2; + + tmp = (rd_adj << EFUSE_EFUCFG_RD_ADJ_BIT) | + (rd_strobe << EFUSE_EFUCFG_RD_STROBE_BIT); + writel(tmp, regs + EFUSE_EFUCFG); +} diff --git a/drivers/misc/mxc_ocotp.c b/drivers/misc/mxc_ocotp.c index 9ff475d9255..f84fe88db19 100644 --- a/drivers/misc/mxc_ocotp.c +++ b/drivers/misc/mxc_ocotp.c @@ -34,7 +34,7 @@ #define BM_OUT_STATUS_DED 0x00000400 #define BM_OUT_STATUS_LOCKED 0x00000800 #define BM_OUT_STATUS_PROGFAIL 0x00001000 -#elif defined(CONFIG_MX8M) +#elif defined(CONFIG_IMX8M) #define BM_CTRL_ADDR 0x000000ff #else #define BM_CTRL_ADDR 0x0000007f @@ -80,7 +80,7 @@ #elif defined(CONFIG_MX7ULP) #define FUSE_BANK_SIZE 0x80 #define FUSE_BANKS 31 -#elif defined(CONFIG_MX8M) +#elif defined(CONFIG_IMX8M) #define FUSE_BANK_SIZE 0x40 #define FUSE_BANKS 64 #else @@ -298,7 +298,7 @@ static void setup_direct_access(struct ocotp_regs *regs, u32 bank, u32 word, u32 wr_unlock = write ? BV_CTRL_WR_UNLOCK_KEY : 0; #ifdef CONFIG_MX7 u32 addr = bank; -#elif defined CONFIG_MX8M +#elif defined CONFIG_IMX8M u32 addr = bank << 2 | word; #else u32 addr; diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index fbd13964a08..496b2cba640 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -332,6 +332,12 @@ config MMC_BCM2835 If unsure, say N. +config JZ47XX_MMC + bool "Ingenic JZ47xx SD/MMC Host Controller support" + depends on ARCH_JZ47XX + help + This selects support for the SD Card Controller on Ingenic JZ47xx SoCs. + config MMC_SANDBOX bool "Sandbox MMC support" depends on SANDBOX diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index 801a26d8219..7892c468f05 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -40,6 +40,7 @@ obj-$(CONFIG_MMC_SANDBOX) += sandbox_mmc.o obj-$(CONFIG_SH_MMCIF) += sh_mmcif.o obj-$(CONFIG_SH_SDHI) += sh_sdhi.o obj-$(CONFIG_STM32_SDMMC2) += stm32_sdmmc2.o +obj-$(CONFIG_JZ47XX_MMC) += jz_mmc.o # SDHCI obj-$(CONFIG_MMC_SDHCI) += sdhci.o diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 3cdfa7f5a68..74007e2ad43 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -259,7 +259,7 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc, int timeout; struct fsl_esdhc *regs = priv->esdhc_regs; #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \ - defined(CONFIG_IMX8) || defined(CONFIG_MX8M) + defined(CONFIG_IMX8) || defined(CONFIG_IMX8M) dma_addr_t addr; #endif uint wml_value; @@ -273,7 +273,7 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc, esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value); #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \ - defined(CONFIG_IMX8) || defined(CONFIG_MX8M) + defined(CONFIG_IMX8) || defined(CONFIG_IMX8M) addr = virt_to_phys((void *)(data->dest)); if (upper_32_bits(addr)) printf("Error found for upper 32 bits\n"); @@ -303,7 +303,7 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc, wml_value << 16); #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \ - defined(CONFIG_IMX8) || defined(CONFIG_MX8M) + defined(CONFIG_IMX8) || defined(CONFIG_IMX8M) addr = virt_to_phys((void *)(data->src)); if (upper_32_bits(addr)) printf("Error found for upper 32 bits\n"); @@ -369,7 +369,7 @@ static void check_and_invalidate_dcache_range unsigned size = roundup(ARCH_DMA_MINALIGN, data->blocks*data->blocksize); #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \ - defined(CONFIG_IMX8) || defined(CONFIG_MX8M) + defined(CONFIG_IMX8) || defined(CONFIG_IMX8M) dma_addr_t addr; addr = virt_to_phys((void *)(data->dest)); diff --git a/drivers/mmc/jz_mmc.c b/drivers/mmc/jz_mmc.c new file mode 100644 index 00000000000..3132c3e191a --- /dev/null +++ b/drivers/mmc/jz_mmc.c @@ -0,0 +1,488 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Ingenic JZ MMC driver + * + * Copyright (c) 2013 Imagination Technologies + * Author: Paul Burton <paul.burton@imgtec.com> + */ + +#include <common.h> +#include <malloc.h> +#include <mmc.h> +#include <asm/io.h> +#include <asm/unaligned.h> +#include <errno.h> +#include <mach/jz4780.h> +#include <wait_bit.h> + +/* Registers */ +#define MSC_STRPCL 0x000 +#define MSC_STAT 0x004 +#define MSC_CLKRT 0x008 +#define MSC_CMDAT 0x00c +#define MSC_RESTO 0x010 +#define MSC_RDTO 0x014 +#define MSC_BLKLEN 0x018 +#define MSC_NOB 0x01c +#define MSC_SNOB 0x020 +#define MSC_IMASK 0x024 +#define MSC_IREG 0x028 +#define MSC_CMD 0x02c +#define MSC_ARG 0x030 +#define MSC_RES 0x034 +#define MSC_RXFIFO 0x038 +#define MSC_TXFIFO 0x03c +#define MSC_LPM 0x040 +#define MSC_DMAC 0x044 +#define MSC_DMANDA 0x048 +#define MSC_DMADA 0x04c +#define MSC_DMALEN 0x050 +#define MSC_DMACMD 0x054 +#define MSC_CTRL2 0x058 +#define MSC_RTCNT 0x05c +#define MSC_DBG 0x0fc + +/* MSC Clock and Control Register (MSC_STRPCL) */ +#define MSC_STRPCL_EXIT_MULTIPLE BIT(7) +#define MSC_STRPCL_EXIT_TRANSFER BIT(6) +#define MSC_STRPCL_START_READWAIT BIT(5) +#define MSC_STRPCL_STOP_READWAIT BIT(4) +#define MSC_STRPCL_RESET BIT(3) +#define MSC_STRPCL_START_OP BIT(2) +#define MSC_STRPCL_CLOCK_CONTROL_STOP BIT(0) +#define MSC_STRPCL_CLOCK_CONTROL_START BIT(1) + +/* MSC Status Register (MSC_STAT) */ +#define MSC_STAT_AUTO_CMD_DONE BIT(31) +#define MSC_STAT_IS_RESETTING BIT(15) +#define MSC_STAT_SDIO_INT_ACTIVE BIT(14) +#define MSC_STAT_PRG_DONE BIT(13) +#define MSC_STAT_DATA_TRAN_DONE BIT(12) +#define MSC_STAT_END_CMD_RES BIT(11) +#define MSC_STAT_DATA_FIFO_AFULL BIT(10) +#define MSC_STAT_IS_READWAIT BIT(9) +#define MSC_STAT_CLK_EN BIT(8) +#define MSC_STAT_DATA_FIFO_FULL BIT(7) +#define MSC_STAT_DATA_FIFO_EMPTY BIT(6) +#define MSC_STAT_CRC_RES_ERR BIT(5) +#define MSC_STAT_CRC_READ_ERROR BIT(4) +#define MSC_STAT_CRC_WRITE_ERROR BIT(2) +#define MSC_STAT_CRC_WRITE_ERROR_NOSTS BIT(4) +#define MSC_STAT_TIME_OUT_RES BIT(1) +#define MSC_STAT_TIME_OUT_READ BIT(0) + +/* MSC Bus Clock Control Register (MSC_CLKRT) */ +#define MSC_CLKRT_CLK_RATE_MASK 0x7 + +/* MSC Command Sequence Control Register (MSC_CMDAT) */ +#define MSC_CMDAT_IO_ABORT BIT(11) +#define MSC_CMDAT_BUS_WIDTH_1BIT (0x0 << 9) +#define MSC_CMDAT_BUS_WIDTH_4BIT (0x2 << 9) +#define MSC_CMDAT_DMA_EN BIT(8) +#define MSC_CMDAT_INIT BIT(7) +#define MSC_CMDAT_BUSY BIT(6) +#define MSC_CMDAT_STREAM_BLOCK BIT(5) +#define MSC_CMDAT_WRITE BIT(4) +#define MSC_CMDAT_DATA_EN BIT(3) +#define MSC_CMDAT_RESPONSE_MASK (0x7 << 0) +#define MSC_CMDAT_RESPONSE_NONE (0x0 << 0) /* No response */ +#define MSC_CMDAT_RESPONSE_R1 (0x1 << 0) /* Format R1 and R1b */ +#define MSC_CMDAT_RESPONSE_R2 (0x2 << 0) /* Format R2 */ +#define MSC_CMDAT_RESPONSE_R3 (0x3 << 0) /* Format R3 */ +#define MSC_CMDAT_RESPONSE_R4 (0x4 << 0) /* Format R4 */ +#define MSC_CMDAT_RESPONSE_R5 (0x5 << 0) /* Format R5 */ +#define MSC_CMDAT_RESPONSE_R6 (0x6 << 0) /* Format R6 */ + +/* MSC Interrupts Mask Register (MSC_IMASK) */ +#define MSC_IMASK_TIME_OUT_RES BIT(9) +#define MSC_IMASK_TIME_OUT_READ BIT(8) +#define MSC_IMASK_SDIO BIT(7) +#define MSC_IMASK_TXFIFO_WR_REQ BIT(6) +#define MSC_IMASK_RXFIFO_RD_REQ BIT(5) +#define MSC_IMASK_END_CMD_RES BIT(2) +#define MSC_IMASK_PRG_DONE BIT(1) +#define MSC_IMASK_DATA_TRAN_DONE BIT(0) + +/* MSC Interrupts Status Register (MSC_IREG) */ +#define MSC_IREG_TIME_OUT_RES BIT(9) +#define MSC_IREG_TIME_OUT_READ BIT(8) +#define MSC_IREG_SDIO BIT(7) +#define MSC_IREG_TXFIFO_WR_REQ BIT(6) +#define MSC_IREG_RXFIFO_RD_REQ BIT(5) +#define MSC_IREG_END_CMD_RES BIT(2) +#define MSC_IREG_PRG_DONE BIT(1) +#define MSC_IREG_DATA_TRAN_DONE BIT(0) + +struct jz_mmc_plat { + struct mmc_config cfg; + struct mmc mmc; +}; + +struct jz_mmc_priv { + void __iomem *regs; + u32 flags; +/* priv flags */ +#define JZ_MMC_BUS_WIDTH_MASK 0x3 +#define JZ_MMC_BUS_WIDTH_1 0x0 +#define JZ_MMC_BUS_WIDTH_4 0x2 +#define JZ_MMC_BUS_WIDTH_8 0x3 +#define JZ_MMC_SENT_INIT BIT(2) +}; + +static int jz_mmc_clock_rate(void) +{ + return 24000000; +} + +static int jz_mmc_send_cmd(struct mmc *mmc, struct jz_mmc_priv *priv, + struct mmc_cmd *cmd, struct mmc_data *data) +{ + u32 stat, mask, cmdat = 0; + int i, ret; + + /* stop the clock */ + writel(MSC_STRPCL_CLOCK_CONTROL_STOP, priv->regs + MSC_STRPCL); + ret = wait_for_bit_le32(priv->regs + MSC_STAT, + MSC_STAT_CLK_EN, false, 10000, false); + if (ret) + return ret; + + writel(0, priv->regs + MSC_DMAC); + + /* setup command */ + writel(cmd->cmdidx, priv->regs + MSC_CMD); + writel(cmd->cmdarg, priv->regs + MSC_ARG); + + if (data) { + /* setup data */ + cmdat |= MSC_CMDAT_DATA_EN; + if (data->flags & MMC_DATA_WRITE) + cmdat |= MSC_CMDAT_WRITE; + + writel(data->blocks, priv->regs + MSC_NOB); + writel(data->blocksize, priv->regs + MSC_BLKLEN); + } else { + writel(0, priv->regs + MSC_NOB); + writel(0, priv->regs + MSC_BLKLEN); + } + + /* setup response */ + switch (cmd->resp_type) { + case MMC_RSP_NONE: + break; + case MMC_RSP_R1: + case MMC_RSP_R1b: + cmdat |= MSC_CMDAT_RESPONSE_R1; + break; + case MMC_RSP_R2: + cmdat |= MSC_CMDAT_RESPONSE_R2; + break; + case MMC_RSP_R3: + cmdat |= MSC_CMDAT_RESPONSE_R3; + break; + default: + break; + } + + if (cmd->resp_type & MMC_RSP_BUSY) + cmdat |= MSC_CMDAT_BUSY; + + /* set init for the first command only */ + if (!(priv->flags & JZ_MMC_SENT_INIT)) { + cmdat |= MSC_CMDAT_INIT; + priv->flags |= JZ_MMC_SENT_INIT; + } + + cmdat |= (priv->flags & JZ_MMC_BUS_WIDTH_MASK) << 9; + + /* write the data setup */ + writel(cmdat, priv->regs + MSC_CMDAT); + + /* unmask interrupts */ + mask = 0xffffffff & ~(MSC_IMASK_END_CMD_RES | MSC_IMASK_TIME_OUT_RES); + if (data) { + mask &= ~MSC_IMASK_DATA_TRAN_DONE; + if (data->flags & MMC_DATA_WRITE) { + mask &= ~MSC_IMASK_TXFIFO_WR_REQ; + } else { + mask &= ~(MSC_IMASK_RXFIFO_RD_REQ | + MSC_IMASK_TIME_OUT_READ); + } + } + writel(mask, priv->regs + MSC_IMASK); + + /* clear interrupts */ + writel(0xffffffff, priv->regs + MSC_IREG); + + /* start the command (& the clock) */ + writel(MSC_STRPCL_START_OP | MSC_STRPCL_CLOCK_CONTROL_START, + priv->regs + MSC_STRPCL); + + /* wait for completion */ + for (i = 0; i < 100; i++) { + stat = readl(priv->regs + MSC_IREG); + stat &= MSC_IREG_END_CMD_RES | MSC_IREG_TIME_OUT_RES; + if (stat) + break; + mdelay(1); + } + writel(stat, priv->regs + MSC_IREG); + if (stat & MSC_IREG_TIME_OUT_RES) + return -ETIMEDOUT; + + if (cmd->resp_type & MMC_RSP_PRESENT) { + /* read the response */ + if (cmd->resp_type & MMC_RSP_136) { + u16 a, b, c, i; + + a = readw(priv->regs + MSC_RES); + for (i = 0; i < 4; i++) { + b = readw(priv->regs + MSC_RES); + c = readw(priv->regs + MSC_RES); + cmd->response[i] = + (a << 24) | (b << 8) | (c >> 8); + a = c; + } + } else { + cmd->response[0] = readw(priv->regs + MSC_RES) << 24; + cmd->response[0] |= readw(priv->regs + MSC_RES) << 8; + cmd->response[0] |= readw(priv->regs + MSC_RES) & 0xff; + } + } + + if (data && (data->flags & MMC_DATA_WRITE)) { + /* write the data */ + int sz = DIV_ROUND_UP(data->blocks * data->blocksize, 4); + const void *buf = data->src; + + while (sz--) { + u32 val = get_unaligned_le32(buf); + + wait_for_bit_le32(priv->regs + MSC_IREG, + MSC_IREG_TXFIFO_WR_REQ, + true, 10000, false); + writel(val, priv->regs + MSC_TXFIFO); + buf += 4; + } + } else if (data && (data->flags & MMC_DATA_READ)) { + /* read the data */ + int sz = data->blocks * data->blocksize; + void *buf = data->dest; + + do { + stat = readl(priv->regs + MSC_STAT); + + if (stat & MSC_STAT_TIME_OUT_READ) + return -ETIMEDOUT; + if (stat & MSC_STAT_CRC_READ_ERROR) + return -EINVAL; + if (stat & MSC_STAT_DATA_FIFO_EMPTY) { + udelay(10); + continue; + } + do { + u32 val = readl(priv->regs + MSC_RXFIFO); + + if (sz == 1) + *(u8 *)buf = (u8)val; + else if (sz == 2) + put_unaligned_le16(val, buf); + else if (sz >= 4) + put_unaligned_le32(val, buf); + buf += 4; + sz -= 4; + stat = readl(priv->regs + MSC_STAT); + } while (!(stat & MSC_STAT_DATA_FIFO_EMPTY)); + } while (!(stat & MSC_STAT_DATA_TRAN_DONE)); + } + + return 0; +} + +static int jz_mmc_set_ios(struct mmc *mmc, struct jz_mmc_priv *priv) +{ + u32 real_rate = jz_mmc_clock_rate(); + u8 clk_div = 0; + + /* calculate clock divide */ + while ((real_rate > mmc->clock) && (clk_div < 7)) { + real_rate >>= 1; + clk_div++; + } + writel(clk_div & MSC_CLKRT_CLK_RATE_MASK, priv->regs + MSC_CLKRT); + + /* set the bus width for the next command */ + priv->flags &= ~JZ_MMC_BUS_WIDTH_MASK; + if (mmc->bus_width == 8) + priv->flags |= JZ_MMC_BUS_WIDTH_8; + else if (mmc->bus_width == 4) + priv->flags |= JZ_MMC_BUS_WIDTH_4; + else + priv->flags |= JZ_MMC_BUS_WIDTH_1; + + return 0; +} + +static int jz_mmc_core_init(struct mmc *mmc) +{ + struct jz_mmc_priv *priv = mmc->priv; + int ret; + + /* Reset */ + writel(MSC_STRPCL_RESET, priv->regs + MSC_STRPCL); + ret = wait_for_bit_le32(priv->regs + MSC_STAT, + MSC_STAT_IS_RESETTING, false, 10000, false); + if (ret) + return ret; + + /* Maximum timeouts */ + writel(0xffff, priv->regs + MSC_RESTO); + writel(0xffffffff, priv->regs + MSC_RDTO); + + /* Enable low power mode */ + writel(0x1, priv->regs + MSC_LPM); + + return 0; +} + +#if !CONFIG_IS_ENABLED(DM_MMC) + +static int jz_mmc_legacy_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, + struct mmc_data *data) +{ + struct jz_mmc_priv *priv = mmc->priv; + + return jz_mmc_send_cmd(mmc, priv, cmd, data); +} + +static int jz_mmc_legacy_set_ios(struct mmc *mmc) +{ + struct jz_mmc_priv *priv = mmc->priv; + + return jz_mmc_set_ios(mmc, priv); +}; + +static const struct mmc_ops jz_msc_ops = { + .send_cmd = jz_mmc_legacy_send_cmd, + .set_ios = jz_mmc_legacy_set_ios, + .init = jz_mmc_core_init, +}; + +static struct jz_mmc_priv jz_mmc_priv_static; +static struct jz_mmc_plat jz_mmc_plat_static = { + .cfg = { + .name = "MSC", + .ops = &jz_msc_ops, + + .voltages = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 | + MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 | + MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36, + .host_caps = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS, + + .f_min = 375000, + .f_max = 48000000, + .b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT, + }, +}; + +int jz_mmc_init(void __iomem *base) +{ + struct mmc *mmc; + + jz_mmc_priv_static.regs = base; + + mmc = mmc_create(&jz_mmc_plat_static.cfg, &jz_mmc_priv_static); + + return mmc ? 0 : -ENODEV; +} + +#else /* CONFIG_DM_MMC */ + +#include <dm.h> +DECLARE_GLOBAL_DATA_PTR; + +static int jz_mmc_dm_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, + struct mmc_data *data) +{ + struct jz_mmc_priv *priv = dev_get_priv(dev); + struct mmc *mmc = mmc_get_mmc_dev(dev); + + return jz_mmc_send_cmd(mmc, priv, cmd, data); +} + +static int jz_mmc_dm_set_ios(struct udevice *dev) +{ + struct jz_mmc_priv *priv = dev_get_priv(dev); + struct mmc *mmc = mmc_get_mmc_dev(dev); + + return jz_mmc_set_ios(mmc, priv); +}; + +static const struct dm_mmc_ops jz_msc_ops = { + .send_cmd = jz_mmc_dm_send_cmd, + .set_ios = jz_mmc_dm_set_ios, +}; + +static int jz_mmc_ofdata_to_platdata(struct udevice *dev) +{ + struct jz_mmc_priv *priv = dev_get_priv(dev); + struct jz_mmc_plat *plat = dev_get_platdata(dev); + struct mmc_config *cfg; + int ret; + + priv->regs = map_physmem(devfdt_get_addr(dev), 0x100, MAP_NOCACHE); + cfg = &plat->cfg; + + cfg->name = "MSC"; + cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS; + + ret = mmc_of_parse(dev, cfg); + if (ret < 0) { + dev_err(dev, "failed to parse host caps\n"); + return ret; + } + + cfg->f_min = 400000; + cfg->f_max = 52000000; + + cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; + cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; + + return 0; +} + +static int jz_mmc_bind(struct udevice *dev) +{ + struct jz_mmc_plat *plat = dev_get_platdata(dev); + + return mmc_bind(dev, &plat->mmc, &plat->cfg); +} + +static int jz_mmc_probe(struct udevice *dev) +{ + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); + struct jz_mmc_priv *priv = dev_get_priv(dev); + struct jz_mmc_plat *plat = dev_get_platdata(dev); + + plat->mmc.priv = priv; + upriv->mmc = &plat->mmc; + return jz_mmc_core_init(&plat->mmc); +} + +static const struct udevice_id jz_mmc_ids[] = { + { .compatible = "ingenic,jz4780-mmc" }, + { } +}; + +U_BOOT_DRIVER(jz_mmc_drv) = { + .name = "jz_mmc", + .id = UCLASS_MMC, + .of_match = jz_mmc_ids, + .ofdata_to_platdata = jz_mmc_ofdata_to_platdata, + .bind = jz_mmc_bind, + .probe = jz_mmc_probe, + .priv_auto_alloc_size = sizeof(struct jz_mmc_priv), + .platdata_auto_alloc_size = sizeof(struct jz_mmc_plat), + .ops = &jz_msc_ops, +}; +#endif /* CONFIG_DM_MMC */ diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index 008f7b4b4ba..fd1723fedad 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -88,6 +88,15 @@ config NAND_VF610_NFC The driver supports a maximum 2k page size. The driver currently does not support hardware ECC. +if NAND_VF610_NFC + +config NAND_VF610_NFC_DT + bool "Support Vybrid's vf610 NAND controller as a DT device" + depends on OF_CONTROL && MTD + help + Enable the driver for Vybrid's vf610 NAND flash on platforms + using device tree. + choice prompt "Hardware ECC strength" depends on NAND_VF610_NFC @@ -103,6 +112,8 @@ config SYS_NAND_VF610_NFC_60_ECC_BYTES endchoice +endif + config NAND_PXA3XX bool "Support for NAND on PXA3xx and Armada 370/XP/38x" select SYS_NAND_SELF_INIT diff --git a/drivers/mtd/nand/raw/denali.c b/drivers/mtd/nand/raw/denali.c index d1cac063f46..e0eb1339ecd 100644 --- a/drivers/mtd/nand/raw/denali.c +++ b/drivers/mtd/nand/raw/denali.c @@ -69,14 +69,6 @@ static int dma_mapping_error(void *dev, dma_addr_t addr) #define DENALI_INVALID_BANK -1 #define DENALI_NR_BANKS 4 -/* - * The bus interface clock, clk_x, is phase aligned with the core clock. The - * clk_x is an integral multiple N of the core clk. The value N is configured - * at IP delivery time, and its available value is 4, 5, or 6. We need to align - * to the largest value to make it work with any possible configuration. - */ -#define DENALI_CLK_X_MULT 6 - static inline struct denali_nand_info *mtd_to_denali(struct mtd_info *mtd) { return container_of(mtd_to_nand(mtd), struct denali_nand_info, nand); @@ -595,6 +587,12 @@ static int denali_dma_xfer(struct denali_nand_info *denali, void *buf, } iowrite32(DMA_ENABLE__FLAG, denali->reg + DMA_ENABLE); + /* + * The ->setup_dma() hook kicks DMA by using the data/command + * interface, which belongs to a different AXI port from the + * register interface. Read back the register to avoid a race. + */ + ioread32(denali->reg + DMA_ENABLE); denali_reset_irq(denali); denali->setup_dma(denali, dma_addr, page, write); @@ -946,7 +944,7 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr, { struct denali_nand_info *denali = mtd_to_denali(mtd); const struct nand_sdr_timings *timings; - unsigned long t_clk; + unsigned long t_x, mult_x; int acc_clks, re_2_we, re_2_re, we_2_re, addr_2_data; int rdwr_en_lo, rdwr_en_hi, rdwr_en_lo_hi, cs_setup; int addr_2_data_mask; @@ -957,15 +955,24 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr, return PTR_ERR(timings); /* clk_x period in picoseconds */ - t_clk = DIV_ROUND_DOWN_ULL(1000000000000ULL, denali->clk_x_rate); - if (!t_clk) + t_x = DIV_ROUND_DOWN_ULL(1000000000000ULL, denali->clk_x_rate); + if (!t_x) + return -EINVAL; + + /* + * The bus interface clock, clk_x, is phase aligned with the core clock. + * The clk_x is an integral multiple N of the core clk. The value N is + * configured at IP delivery time, and its available value is 4, 5, 6. + */ + mult_x = DIV_ROUND_CLOSEST_ULL(denali->clk_x_rate, denali->clk_rate); + if (mult_x < 4 || mult_x > 6) return -EINVAL; if (chipnr == NAND_DATA_IFACE_CHECK_ONLY) return 0; /* tREA -> ACC_CLKS */ - acc_clks = DIV_ROUND_UP(timings->tREA_max, t_clk); + acc_clks = DIV_ROUND_UP(timings->tREA_max, t_x); acc_clks = min_t(int, acc_clks, ACC_CLKS__VALUE); tmp = ioread32(denali->reg + ACC_CLKS); @@ -974,7 +981,7 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr, iowrite32(tmp, denali->reg + ACC_CLKS); /* tRWH -> RE_2_WE */ - re_2_we = DIV_ROUND_UP(timings->tRHW_min, t_clk); + re_2_we = DIV_ROUND_UP(timings->tRHW_min, t_x); re_2_we = min_t(int, re_2_we, RE_2_WE__VALUE); tmp = ioread32(denali->reg + RE_2_WE); @@ -983,7 +990,7 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr, iowrite32(tmp, denali->reg + RE_2_WE); /* tRHZ -> RE_2_RE */ - re_2_re = DIV_ROUND_UP(timings->tRHZ_max, t_clk); + re_2_re = DIV_ROUND_UP(timings->tRHZ_max, t_x); re_2_re = min_t(int, re_2_re, RE_2_RE__VALUE); tmp = ioread32(denali->reg + RE_2_RE); @@ -997,8 +1004,7 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr, * With WE_2_RE properly set, the Denali controller automatically takes * care of the delay; the driver need not set NAND_WAIT_TCCS. */ - we_2_re = DIV_ROUND_UP(max(timings->tCCS_min, timings->tWHR_min), - t_clk); + we_2_re = DIV_ROUND_UP(max(timings->tCCS_min, timings->tWHR_min), t_x); we_2_re = min_t(int, we_2_re, TWHR2_AND_WE_2_RE__WE_2_RE); tmp = ioread32(denali->reg + TWHR2_AND_WE_2_RE); @@ -1013,7 +1019,7 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr, if (denali->revision < 0x0501) addr_2_data_mask >>= 1; - addr_2_data = DIV_ROUND_UP(timings->tADL_min, t_clk); + addr_2_data = DIV_ROUND_UP(timings->tADL_min, t_x); addr_2_data = min_t(int, addr_2_data, addr_2_data_mask); tmp = ioread32(denali->reg + TCWAW_AND_ADDR_2_DATA); @@ -1023,7 +1029,7 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr, /* tREH, tWH -> RDWR_EN_HI_CNT */ rdwr_en_hi = DIV_ROUND_UP(max(timings->tREH_min, timings->tWH_min), - t_clk); + t_x); rdwr_en_hi = min_t(int, rdwr_en_hi, RDWR_EN_HI_CNT__VALUE); tmp = ioread32(denali->reg + RDWR_EN_HI_CNT); @@ -1032,11 +1038,10 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr, iowrite32(tmp, denali->reg + RDWR_EN_HI_CNT); /* tRP, tWP -> RDWR_EN_LO_CNT */ - rdwr_en_lo = DIV_ROUND_UP(max(timings->tRP_min, timings->tWP_min), - t_clk); + rdwr_en_lo = DIV_ROUND_UP(max(timings->tRP_min, timings->tWP_min), t_x); rdwr_en_lo_hi = DIV_ROUND_UP(max(timings->tRC_min, timings->tWC_min), - t_clk); - rdwr_en_lo_hi = max(rdwr_en_lo_hi, DENALI_CLK_X_MULT); + t_x); + rdwr_en_lo_hi = max_t(int, rdwr_en_lo_hi, mult_x); rdwr_en_lo = max(rdwr_en_lo, rdwr_en_lo_hi - rdwr_en_hi); rdwr_en_lo = min_t(int, rdwr_en_lo, RDWR_EN_LO_CNT__VALUE); @@ -1046,8 +1051,8 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr, iowrite32(tmp, denali->reg + RDWR_EN_LO_CNT); /* tCS, tCEA -> CS_SETUP_CNT */ - cs_setup = max3((int)DIV_ROUND_UP(timings->tCS_min, t_clk) - rdwr_en_lo, - (int)DIV_ROUND_UP(timings->tCEA_max, t_clk) - acc_clks, + cs_setup = max3((int)DIV_ROUND_UP(timings->tCS_min, t_x) - rdwr_en_lo, + (int)DIV_ROUND_UP(timings->tCEA_max, t_x) - acc_clks, 0); cs_setup = min_t(int, cs_setup, CS_SETUP_CNT__VALUE); diff --git a/drivers/mtd/nand/raw/denali.h b/drivers/mtd/nand/raw/denali.h index 9b797beffa7..019deda094e 100644 --- a/drivers/mtd/nand/raw/denali.h +++ b/drivers/mtd/nand/raw/denali.h @@ -292,6 +292,7 @@ struct udevice; struct denali_nand_info { struct nand_chip nand; + unsigned long clk_rate; /* core clock rate */ unsigned long clk_x_rate; /* bus interface clock rate */ int active_bank; /* currently selected bank */ struct udevice *dev; diff --git a/drivers/mtd/nand/raw/denali_dt.c b/drivers/mtd/nand/raw/denali_dt.c index 65a7797f0f3..d384b974df1 100644 --- a/drivers/mtd/nand/raw/denali_dt.c +++ b/drivers/mtd/nand/raw/denali_dt.c @@ -62,7 +62,7 @@ static int denali_dt_probe(struct udevice *dev) { struct denali_nand_info *denali = dev_get_priv(dev); const struct denali_dt_data *data; - struct clk clk; + struct clk clk, clk_x, clk_ecc; struct resource res; int ret; @@ -87,15 +87,49 @@ static int denali_dt_probe(struct udevice *dev) denali->host = devm_ioremap(dev, res.start, resource_size(&res)); - ret = clk_get_by_index(dev, 0, &clk); + ret = clk_get_by_name(dev, "nand", &clk); + if (ret) + ret = clk_get_by_index(dev, 0, &clk); if (ret) return ret; + ret = clk_get_by_name(dev, "nand_x", &clk_x); + if (ret) + clk_x.dev = NULL; + + ret = clk_get_by_name(dev, "ecc", &clk_ecc); + if (ret) + clk_ecc.dev = NULL; + ret = clk_enable(&clk); if (ret) return ret; - denali->clk_x_rate = clk_get_rate(&clk); + if (clk_x.dev) { + ret = clk_enable(&clk_x); + if (ret) + return ret; + } + + if (clk_ecc.dev) { + ret = clk_enable(&clk_ecc); + if (ret) + return ret; + } + + if (clk_x.dev) { + denali->clk_rate = clk_get_rate(&clk); + denali->clk_x_rate = clk_get_rate(&clk_x); + } else { + /* + * Hardcode the clock rates for the backward compatibility. + * This works for both SOCFPGA and UniPhier. + */ + dev_notice(dev, + "necessary clock is missing. default clock rates are used.\n"); + denali->clk_rate = 50000000; + denali->clk_x_rate = 200000000; + } return denali_init(denali); } diff --git a/drivers/mtd/nand/raw/nand_ids.c b/drivers/mtd/nand/raw/nand_ids.c index 4009d641235..3104f879f66 100644 --- a/drivers/mtd/nand/raw/nand_ids.c +++ b/drivers/mtd/nand/raw/nand_ids.c @@ -61,6 +61,10 @@ struct nand_flash_dev nand_flash_ids[] = { {"SDTNRGAMA 64G 3.3V 8-bit", { .id = {0x45, 0xde, 0x94, 0x93, 0x76, 0x50} }, SZ_16K, SZ_8K, SZ_4M, 0, 6, 1280, NAND_ECC_INFO(40, SZ_1K) }, + {"H27UBG8T2BTR-BC 32G 3.3V 8-bit", + { .id = {0xad, 0xd7, 0x94, 0xda, 0x74, 0xc3} }, + SZ_8K, SZ_4K, SZ_2M, NAND_NEED_SCRAMBLING, 6, 640, + NAND_ECC_INFO(40, SZ_1K), 0 }, {"H27UCG8T2ATR-BC 64G 3.3V 8-bit", { .id = {0xad, 0xde, 0x94, 0xda, 0x74, 0xc4} }, SZ_8K, SZ_8K, SZ_2M, NAND_NEED_SCRAMBLING, 6, 640, diff --git a/drivers/mtd/nand/raw/vf610_nfc.c b/drivers/mtd/nand/raw/vf610_nfc.c index 619d0403e92..3326c2b096b 100644 --- a/drivers/mtd/nand/raw/vf610_nfc.c +++ b/drivers/mtd/nand/raw/vf610_nfc.c @@ -31,6 +31,11 @@ #include <nand.h> #include <errno.h> #include <asm/io.h> +#if CONFIG_NAND_VF610_NFC_DT +#include <dm.h> +#include <linux/io.h> +#include <linux/ioport.h> +#endif /* Register Offsets */ #define NFC_FLASH_CMD1 0x3F00 @@ -641,7 +646,7 @@ static int vf610_nfc_nand_init(int devnum, void __iomem *addr) .flash_bbt = 1, }; - nfc = malloc(sizeof(*nfc)); + nfc = calloc(1, sizeof(*nfc)); if (!nfc) { printf(KERN_ERR "%s: Memory exhausted!\n", __func__); return -ENOMEM; @@ -760,9 +765,51 @@ error: return err; } +#if CONFIG_NAND_VF610_NFC_DT +static const struct udevice_id vf610_nfc_dt_ids[] = { + { + .compatible = "fsl,vf610-nfc", + }, + { /* sentinel */ } +}; + +static int vf610_nfc_dt_probe(struct udevice *dev) +{ + struct resource res; + int ret; + + ret = dev_read_resource(dev, 0, &res); + if (ret) + return ret; + + return vf610_nfc_nand_init(0, devm_ioremap(dev, res.start, + resource_size(&res))); +} + +U_BOOT_DRIVER(vf610_nfc_dt) = { + .name = "vf610-nfc-dt", + .id = UCLASS_MTD, + .of_match = vf610_nfc_dt_ids, + .probe = vf610_nfc_dt_probe, +}; + +void board_nand_init(void) +{ + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_MTD, + DM_GET_DRIVER(vf610_nfc_dt), + &dev); + if (ret && ret != -ENODEV) + pr_err("Failed to initialize NAND controller. (error %d)\n", + ret); +} +#else void board_nand_init(void) { int err = vf610_nfc_nand_init(0, (void __iomem *)CONFIG_SYS_NAND_BASE); if (err) printf("VF610 NAND init failed (err %d)\n", err); } +#endif /* CONFIG_NAND_VF610_NFC_DT */ diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 8fb365fc5d2..7044c6adf32 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -72,6 +72,24 @@ config BCM_SF2_ETH_GMAC by the BCM_SF2_ETH driver. Say Y to any bcmcygnus based platforms. +config BCM6348_ETH + bool "BCM6348 EMAC support" + depends on DM_ETH && ARCH_BMIPS + select DMA + select DMA_CHANNELS + select MII + select PHYLIB + help + This driver supports the BCM6348 Ethernet MAC. + +config BCM6368_ETH + bool "BCM6368 EMAC support" + depends on DM_ETH && ARCH_BMIPS + select DMA + select MII + help + This driver supports the BCM6368 Ethernet MAC. + config DWC_ETH_QOS bool "Synopsys DWC Ethernet QOS device support" depends on DM_ETH diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 99056aa041d..0dbfa033068 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -6,6 +6,8 @@ obj-$(CONFIG_ALTERA_TSE) += altera_tse.o obj-$(CONFIG_AG7XXX) += ag7xxx.o obj-$(CONFIG_ARMADA100_FEC) += armada100_fec.o +obj-$(CONFIG_BCM6348_ETH) += bcm6348-eth.o +obj-$(CONFIG_BCM6368_ETH) += bcm6368-eth.o obj-$(CONFIG_DRIVER_AT91EMAC) += at91_emac.o obj-$(CONFIG_DRIVER_AX88180) += ax88180.o obj-$(CONFIG_BCM_SF2_ETH) += bcm-sf2-eth.o diff --git a/drivers/net/bcm6348-eth.c b/drivers/net/bcm6348-eth.c new file mode 100644 index 00000000000..7100e68bd20 --- /dev/null +++ b/drivers/net/bcm6348-eth.c @@ -0,0 +1,537 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com> + * + * Derived from linux/drivers/net/ethernet/broadcom/bcm63xx_enet.c: + * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr> + */ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <dma.h> +#include <miiphy.h> +#include <net.h> +#include <phy.h> +#include <reset.h> +#include <wait_bit.h> +#include <asm/io.h> + +#define ETH_RX_DESC PKTBUFSRX +#define ETH_MAX_MTU_SIZE 1518 +#define ETH_TIMEOUT 100 +#define ETH_TX_WATERMARK 32 + +/* ETH Receiver Configuration register */ +#define ETH_RXCFG_REG 0x00 +#define ETH_RXCFG_ENFLOW_SHIFT 5 +#define ETH_RXCFG_ENFLOW_MASK (1 << ETH_RXCFG_ENFLOW_SHIFT) + +/* ETH Receive Maximum Length register */ +#define ETH_RXMAXLEN_REG 0x04 +#define ETH_RXMAXLEN_SHIFT 0 +#define ETH_RXMAXLEN_MASK (0x7ff << ETH_RXMAXLEN_SHIFT) + +/* ETH Transmit Maximum Length register */ +#define ETH_TXMAXLEN_REG 0x08 +#define ETH_TXMAXLEN_SHIFT 0 +#define ETH_TXMAXLEN_MASK (0x7ff << ETH_TXMAXLEN_SHIFT) + +/* MII Status/Control register */ +#define MII_SC_REG 0x10 +#define MII_SC_MDCFREQDIV_SHIFT 0 +#define MII_SC_MDCFREQDIV_MASK (0x7f << MII_SC_MDCFREQDIV_SHIFT) +#define MII_SC_PREAMBLE_EN_SHIFT 7 +#define MII_SC_PREAMBLE_EN_MASK (1 << MII_SC_PREAMBLE_EN_SHIFT) + +/* MII Data register */ +#define MII_DAT_REG 0x14 +#define MII_DAT_DATA_SHIFT 0 +#define MII_DAT_DATA_MASK (0xffff << MII_DAT_DATA_SHIFT) +#define MII_DAT_TA_SHIFT 16 +#define MII_DAT_TA_MASK (0x3 << MII_DAT_TA_SHIFT) +#define MII_DAT_REG_SHIFT 18 +#define MII_DAT_REG_MASK (0x1f << MII_DAT_REG_SHIFT) +#define MII_DAT_PHY_SHIFT 23 +#define MII_DAT_PHY_MASK (0x1f << MII_DAT_PHY_SHIFT) +#define MII_DAT_OP_SHIFT 28 +#define MII_DAT_OP_WRITE (0x5 << MII_DAT_OP_SHIFT) +#define MII_DAT_OP_READ (0x6 << MII_DAT_OP_SHIFT) + +/* ETH Interrupts Mask register */ +#define ETH_IRMASK_REG 0x18 + +/* ETH Interrupts register */ +#define ETH_IR_REG 0x1c +#define ETH_IR_MII_SHIFT 0 +#define ETH_IR_MII_MASK (1 << ETH_IR_MII_SHIFT) + +/* ETH Control register */ +#define ETH_CTL_REG 0x2c +#define ETH_CTL_ENABLE_SHIFT 0 +#define ETH_CTL_ENABLE_MASK (1 << ETH_CTL_ENABLE_SHIFT) +#define ETH_CTL_DISABLE_SHIFT 1 +#define ETH_CTL_DISABLE_MASK (1 << ETH_CTL_DISABLE_SHIFT) +#define ETH_CTL_RESET_SHIFT 2 +#define ETH_CTL_RESET_MASK (1 << ETH_CTL_RESET_SHIFT) +#define ETH_CTL_EPHY_SHIFT 3 +#define ETH_CTL_EPHY_MASK (1 << ETH_CTL_EPHY_SHIFT) + +/* ETH Transmit Control register */ +#define ETH_TXCTL_REG 0x30 +#define ETH_TXCTL_FD_SHIFT 0 +#define ETH_TXCTL_FD_MASK (1 << ETH_TXCTL_FD_SHIFT) + +/* ETH Transmit Watermask register */ +#define ETH_TXWMARK_REG 0x34 +#define ETH_TXWMARK_WM_SHIFT 0 +#define ETH_TXWMARK_WM_MASK (0x3f << ETH_TXWMARK_WM_SHIFT) + +/* MIB Control register */ +#define MIB_CTL_REG 0x38 +#define MIB_CTL_RDCLEAR_SHIFT 0 +#define MIB_CTL_RDCLEAR_MASK (1 << MIB_CTL_RDCLEAR_SHIFT) + +/* ETH Perfect Match registers */ +#define ETH_PM_CNT 4 +#define ETH_PML_REG(x) (0x58 + (x) * 0x8) +#define ETH_PMH_REG(x) (0x5c + (x) * 0x8) +#define ETH_PMH_VALID_SHIFT 16 +#define ETH_PMH_VALID_MASK (1 << ETH_PMH_VALID_SHIFT) + +/* MIB Counters registers */ +#define MIB_REG_CNT 55 +#define MIB_REG(x) (0x200 + (x) * 4) + +/* ETH data */ +struct bcm6348_eth_priv { + void __iomem *base; + /* DMA */ + struct dma rx_dma; + struct dma tx_dma; + /* PHY */ + int phy_id; + struct phy_device *phy_dev; +}; + +static void bcm6348_eth_mac_disable(struct bcm6348_eth_priv *priv) +{ + /* disable emac */ + clrsetbits_be32(priv->base + ETH_CTL_REG, ETH_CTL_ENABLE_MASK, + ETH_CTL_DISABLE_MASK); + + /* wait until emac is disabled */ + if (wait_for_bit_be32(priv->base + ETH_CTL_REG, + ETH_CTL_DISABLE_MASK, false, + ETH_TIMEOUT, false)) + pr_err("%s: error disabling emac\n", __func__); +} + +static void bcm6348_eth_mac_enable(struct bcm6348_eth_priv *priv) +{ + setbits_be32(priv->base + ETH_CTL_REG, ETH_CTL_ENABLE_MASK); +} + +static void bcm6348_eth_mac_reset(struct bcm6348_eth_priv *priv) +{ + /* reset emac */ + writel_be(ETH_CTL_RESET_MASK, priv->base + ETH_CTL_REG); + wmb(); + + /* wait until emac is reset */ + if (wait_for_bit_be32(priv->base + ETH_CTL_REG, + ETH_CTL_RESET_MASK, false, + ETH_TIMEOUT, false)) + pr_err("%s: error resetting emac\n", __func__); +} + +static int bcm6348_eth_free_pkt(struct udevice *dev, uchar *packet, int len) +{ + struct bcm6348_eth_priv *priv = dev_get_priv(dev); + + return dma_prepare_rcv_buf(&priv->rx_dma, packet, len); +} + +static int bcm6348_eth_recv(struct udevice *dev, int flags, uchar **packetp) +{ + struct bcm6348_eth_priv *priv = dev_get_priv(dev); + + return dma_receive(&priv->rx_dma, (void**)packetp, NULL); +} + +static int bcm6348_eth_send(struct udevice *dev, void *packet, int length) +{ + struct bcm6348_eth_priv *priv = dev_get_priv(dev); + + return dma_send(&priv->tx_dma, packet, length, NULL); +} + +static int bcm6348_eth_adjust_link(struct udevice *dev, + struct phy_device *phydev) +{ + struct bcm6348_eth_priv *priv = dev_get_priv(dev); + + /* mac duplex parameters */ + if (phydev->duplex) + setbits_be32(priv->base + ETH_TXCTL_REG, ETH_TXCTL_FD_MASK); + else + clrbits_be32(priv->base + ETH_TXCTL_REG, ETH_TXCTL_FD_MASK); + + /* rx flow control (pause frame handling) */ + if (phydev->pause) + setbits_be32(priv->base + ETH_RXCFG_REG, + ETH_RXCFG_ENFLOW_MASK); + else + clrbits_be32(priv->base + ETH_RXCFG_REG, + ETH_RXCFG_ENFLOW_MASK); + + return 0; +} + +static int bcm6348_eth_start(struct udevice *dev) +{ + struct bcm6348_eth_priv *priv = dev_get_priv(dev); + int ret, i; + + /* prepare rx dma buffers */ + for (i = 0; i < ETH_RX_DESC; i++) { + ret = dma_prepare_rcv_buf(&priv->rx_dma, net_rx_packets[i], + PKTSIZE_ALIGN); + if (ret < 0) + break; + } + + /* enable dma rx channel */ + dma_enable(&priv->rx_dma); + + /* enable dma tx channel */ + dma_enable(&priv->tx_dma); + + ret = phy_startup(priv->phy_dev); + if (ret) { + pr_err("%s: could not initialize phy\n", __func__); + return ret; + } + + if (!priv->phy_dev->link) { + pr_err("%s: no phy link\n", __func__); + return -EIO; + } + + bcm6348_eth_adjust_link(dev, priv->phy_dev); + + /* zero mib counters */ + for (i = 0; i < MIB_REG_CNT; i++) + writel_be(0, MIB_REG(i)); + + /* enable rx flow control */ + setbits_be32(priv->base + ETH_RXCFG_REG, ETH_RXCFG_ENFLOW_MASK); + + /* set max rx/tx length */ + writel_be((ETH_MAX_MTU_SIZE << ETH_RXMAXLEN_SHIFT) & + ETH_RXMAXLEN_MASK, priv->base + ETH_RXMAXLEN_REG); + writel_be((ETH_MAX_MTU_SIZE << ETH_TXMAXLEN_SHIFT) & + ETH_TXMAXLEN_MASK, priv->base + ETH_TXMAXLEN_REG); + + /* set correct transmit fifo watermark */ + writel_be((ETH_TX_WATERMARK << ETH_TXWMARK_WM_SHIFT) & + ETH_TXWMARK_WM_MASK, priv->base + ETH_TXWMARK_REG); + + /* enable emac */ + bcm6348_eth_mac_enable(priv); + + /* clear interrupts */ + writel_be(0, priv->base + ETH_IRMASK_REG); + + return 0; +} + +static void bcm6348_eth_stop(struct udevice *dev) +{ + struct bcm6348_eth_priv *priv = dev_get_priv(dev); + + /* disable dma rx channel */ + dma_disable(&priv->rx_dma); + + /* disable dma tx channel */ + dma_disable(&priv->tx_dma); + + /* disable emac */ + bcm6348_eth_mac_disable(priv); +} + +static int bcm6348_eth_write_hwaddr(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + struct bcm6348_eth_priv *priv = dev_get_priv(dev); + bool running = false; + + /* check if emac is running */ + if (readl_be(priv->base + ETH_CTL_REG) & ETH_CTL_ENABLE_MASK) + running = true; + + /* disable emac */ + if (running) + bcm6348_eth_mac_disable(priv); + + /* set mac address */ + writel_be((pdata->enetaddr[2] << 24) | (pdata->enetaddr[3]) << 16 | + (pdata->enetaddr[4]) << 8 | (pdata->enetaddr[5]), + priv->base + ETH_PML_REG(0)); + writel_be((pdata->enetaddr[1]) | (pdata->enetaddr[0] << 8) | + ETH_PMH_VALID_MASK, priv->base + ETH_PMH_REG(0)); + + /* enable emac */ + if (running) + bcm6348_eth_mac_enable(priv); + + return 0; +} + +static const struct eth_ops bcm6348_eth_ops = { + .free_pkt = bcm6348_eth_free_pkt, + .recv = bcm6348_eth_recv, + .send = bcm6348_eth_send, + .start = bcm6348_eth_start, + .stop = bcm6348_eth_stop, + .write_hwaddr = bcm6348_eth_write_hwaddr, +}; + +static const struct udevice_id bcm6348_eth_ids[] = { + { .compatible = "brcm,bcm6348-enet", }, + { /* sentinel */ } +}; + +static int bcm6348_mdio_op(void __iomem *base, uint32_t data) +{ + /* make sure mii interrupt status is cleared */ + writel_be(ETH_IR_MII_MASK, base + ETH_IR_REG); + + /* issue mii op */ + writel_be(data, base + MII_DAT_REG); + + /* wait until emac is disabled */ + return wait_for_bit_be32(base + ETH_IR_REG, + ETH_IR_MII_MASK, true, + ETH_TIMEOUT, false); +} + +static int bcm6348_mdio_read(struct mii_dev *bus, int addr, int devaddr, + int reg) +{ + void __iomem *base = bus->priv; + uint32_t val; + + val = MII_DAT_OP_READ; + val |= (reg << MII_DAT_REG_SHIFT) & MII_DAT_REG_MASK; + val |= (0x2 << MII_DAT_TA_SHIFT) & MII_DAT_TA_MASK; + val |= (addr << MII_DAT_PHY_SHIFT) & MII_DAT_PHY_MASK; + + if (bcm6348_mdio_op(base, val)) { + pr_err("%s: timeout\n", __func__); + return -EINVAL; + } + + val = readl_be(base + MII_DAT_REG) & MII_DAT_DATA_MASK; + val >>= MII_DAT_DATA_SHIFT; + + return val; +} + +static int bcm6348_mdio_write(struct mii_dev *bus, int addr, int dev_addr, + int reg, u16 value) +{ + void __iomem *base = bus->priv; + uint32_t val; + + val = MII_DAT_OP_WRITE; + val |= (reg << MII_DAT_REG_SHIFT) & MII_DAT_REG_MASK; + val |= (0x2 << MII_DAT_TA_SHIFT) & MII_DAT_TA_MASK; + val |= (addr << MII_DAT_PHY_SHIFT) & MII_DAT_PHY_MASK; + val |= (value << MII_DAT_DATA_SHIFT) & MII_DAT_DATA_MASK; + + if (bcm6348_mdio_op(base, val)) { + pr_err("%s: timeout\n", __func__); + return -EINVAL; + } + + return 0; +} + +static int bcm6348_mdio_init(const char *name, void __iomem *base) +{ + struct mii_dev *bus; + + bus = mdio_alloc(); + if (!bus) { + pr_err("%s: failed to allocate MDIO bus\n", __func__); + return -ENOMEM; + } + + bus->read = bcm6348_mdio_read; + bus->write = bcm6348_mdio_write; + bus->priv = base; + snprintf(bus->name, sizeof(bus->name), "%s", name); + + return mdio_register(bus); +} + +static int bcm6348_phy_init(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + struct bcm6348_eth_priv *priv = dev_get_priv(dev); + struct mii_dev *bus; + + /* get mii bus */ + bus = miiphy_get_dev_by_name(dev->name); + + /* phy connect */ + priv->phy_dev = phy_connect(bus, priv->phy_id, dev, + pdata->phy_interface); + if (!priv->phy_dev) { + pr_err("%s: no phy device\n", __func__); + return -ENODEV; + } + + priv->phy_dev->supported = (SUPPORTED_10baseT_Half | + SUPPORTED_10baseT_Full | + SUPPORTED_100baseT_Half | + SUPPORTED_100baseT_Full | + SUPPORTED_Autoneg | + SUPPORTED_Pause | + SUPPORTED_MII); + priv->phy_dev->advertising = priv->phy_dev->supported; + + /* phy config */ + phy_config(priv->phy_dev); + + return 0; +} + +static int bcm6348_eth_probe(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + struct bcm6348_eth_priv *priv = dev_get_priv(dev); + struct ofnode_phandle_args phy; + const char *phy_mode; + int ret, i; + + /* get base address */ + priv->base = dev_remap_addr(dev); + if (!priv->base) + return -EINVAL; + pdata->iobase = (phys_addr_t) priv->base; + + /* get phy mode */ + pdata->phy_interface = PHY_INTERFACE_MODE_NONE; + phy_mode = dev_read_string(dev, "phy-mode"); + if (phy_mode) + pdata->phy_interface = phy_get_interface_by_name(phy_mode); + if (pdata->phy_interface == PHY_INTERFACE_MODE_NONE) + return -ENODEV; + + /* get phy */ + if (dev_read_phandle_with_args(dev, "phy", NULL, 0, 0, &phy)) + return -ENOENT; + priv->phy_id = ofnode_read_u32_default(phy.node, "reg", -1); + + /* get dma channels */ + ret = dma_get_by_name(dev, "tx", &priv->tx_dma); + if (ret) + return -EINVAL; + + ret = dma_get_by_name(dev, "rx", &priv->rx_dma); + if (ret) + return -EINVAL; + + /* try to enable clocks */ + for (i = 0; ; i++) { + struct clk clk; + int ret; + + ret = clk_get_by_index(dev, i, &clk); + if (ret < 0) + break; + + ret = clk_enable(&clk); + if (ret < 0) { + pr_err("%s: error enabling clock %d\n", __func__, i); + return ret; + } + + ret = clk_free(&clk); + if (ret < 0) { + pr_err("%s: error freeing clock %d\n", __func__, i); + return ret; + } + } + + /* try to perform resets */ + for (i = 0; ; i++) { + struct reset_ctl reset; + int ret; + + ret = reset_get_by_index(dev, i, &reset); + if (ret < 0) + break; + + ret = reset_deassert(&reset); + if (ret < 0) { + pr_err("%s: error deasserting reset %d\n", __func__, i); + return ret; + } + + ret = reset_free(&reset); + if (ret < 0) { + pr_err("%s: error freeing reset %d\n", __func__, i); + return ret; + } + } + + /* disable emac */ + bcm6348_eth_mac_disable(priv); + + /* reset emac */ + bcm6348_eth_mac_reset(priv); + + /* select correct mii interface */ + if (pdata->phy_interface == PHY_INTERFACE_MODE_INTERNAL) + clrbits_be32(priv->base + ETH_CTL_REG, ETH_CTL_EPHY_MASK); + else + setbits_be32(priv->base + ETH_CTL_REG, ETH_CTL_EPHY_MASK); + + /* turn on mdc clock */ + writel_be((0x1f << MII_SC_MDCFREQDIV_SHIFT) | + MII_SC_PREAMBLE_EN_MASK, priv->base + MII_SC_REG); + + /* set mib counters to not clear when read */ + clrbits_be32(priv->base + MIB_CTL_REG, MIB_CTL_RDCLEAR_MASK); + + /* initialize perfect match registers */ + for (i = 0; i < ETH_PM_CNT; i++) { + writel_be(0, priv->base + ETH_PML_REG(i)); + writel_be(0, priv->base + ETH_PMH_REG(i)); + } + + /* init mii bus */ + ret = bcm6348_mdio_init(dev->name, priv->base); + if (ret) + return ret; + + /* init phy */ + ret = bcm6348_phy_init(dev); + if (ret) + return ret; + + return 0; +} + +U_BOOT_DRIVER(bcm6348_eth) = { + .name = "bcm6348_eth", + .id = UCLASS_ETH, + .of_match = bcm6348_eth_ids, + .ops = &bcm6348_eth_ops, + .platdata_auto_alloc_size = sizeof(struct eth_pdata), + .priv_auto_alloc_size = sizeof(struct bcm6348_eth_priv), + .probe = bcm6348_eth_probe, +}; diff --git a/drivers/net/bcm6368-eth.c b/drivers/net/bcm6368-eth.c new file mode 100644 index 00000000000..a31efba9d19 --- /dev/null +++ b/drivers/net/bcm6368-eth.c @@ -0,0 +1,625 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com> + * + * Derived from linux/drivers/net/ethernet/broadcom/bcm63xx_enet.c: + * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr> + */ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <dma.h> +#include <miiphy.h> +#include <net.h> +#include <reset.h> +#include <wait_bit.h> +#include <asm/io.h> + +#define ETH_PORT_STR "brcm,enetsw-port" + +#define ETH_RX_DESC PKTBUFSRX +#define ETH_ZLEN 60 +#define ETH_TIMEOUT 100 + +#define ETH_MAX_PORT 8 +#define ETH_RGMII_PORT0 4 + +/* Port traffic control */ +#define ETH_PTCTRL_REG(x) (0x0 + (x)) +#define ETH_PTCTRL_RXDIS_SHIFT 0 +#define ETH_PTCTRL_RXDIS_MASK (1 << ETH_PTCTRL_RXDIS_SHIFT) +#define ETH_PTCTRL_TXDIS_SHIFT 1 +#define ETH_PTCTRL_TXDIS_MASK (1 << ETH_PTCTRL_TXDIS_SHIFT) + +/* Switch mode register */ +#define ETH_SWMODE_REG 0xb +#define ETH_SWMODE_FWD_EN_SHIFT 1 +#define ETH_SWMODE_FWD_EN_MASK (1 << ETH_SWMODE_FWD_EN_SHIFT) + +/* IMP override Register */ +#define ETH_IMPOV_REG 0xe +#define ETH_IMPOV_LINKUP_SHIFT 0 +#define ETH_IMPOV_LINKUP_MASK (1 << ETH_IMPOV_LINKUP_SHIFT) +#define ETH_IMPOV_FDX_SHIFT 1 +#define ETH_IMPOV_FDX_MASK (1 << ETH_IMPOV_FDX_SHIFT) +#define ETH_IMPOV_100_SHIFT 2 +#define ETH_IMPOV_100_MASK (1 << ETH_IMPOV_100_SHIFT) +#define ETH_IMPOV_1000_SHIFT 3 +#define ETH_IMPOV_1000_MASK (1 << ETH_IMPOV_1000_SHIFT) +#define ETH_IMPOV_RXFLOW_SHIFT 4 +#define ETH_IMPOV_RXFLOW_MASK (1 << ETH_IMPOV_RXFLOW_SHIFT) +#define ETH_IMPOV_TXFLOW_SHIFT 5 +#define ETH_IMPOV_TXFLOW_MASK (1 << ETH_IMPOV_TXFLOW_SHIFT) +#define ETH_IMPOV_FORCE_SHIFT 7 +#define ETH_IMPOV_FORCE_MASK (1 << ETH_IMPOV_FORCE_SHIFT) + +/* Port override Register */ +#define ETH_PORTOV_REG(x) (0x58 + (x)) +#define ETH_PORTOV_LINKUP_SHIFT 0 +#define ETH_PORTOV_LINKUP_MASK (1 << ETH_PORTOV_LINKUP_SHIFT) +#define ETH_PORTOV_FDX_SHIFT 1 +#define ETH_PORTOV_FDX_MASK (1 << ETH_PORTOV_FDX_SHIFT) +#define ETH_PORTOV_100_SHIFT 2 +#define ETH_PORTOV_100_MASK (1 << ETH_PORTOV_100_SHIFT) +#define ETH_PORTOV_1000_SHIFT 3 +#define ETH_PORTOV_1000_MASK (1 << ETH_PORTOV_1000_SHIFT) +#define ETH_PORTOV_RXFLOW_SHIFT 4 +#define ETH_PORTOV_RXFLOW_MASK (1 << ETH_PORTOV_RXFLOW_SHIFT) +#define ETH_PORTOV_TXFLOW_SHIFT 5 +#define ETH_PORTOV_TXFLOW_MASK (1 << ETH_PORTOV_TXFLOW_SHIFT) +#define ETH_PORTOV_ENABLE_SHIFT 6 +#define ETH_PORTOV_ENABLE_MASK (1 << ETH_PORTOV_ENABLE_SHIFT) + +/* Port RGMII control register */ +#define ETH_RGMII_CTRL_REG(x) (0x60 + (x)) +#define ETH_RGMII_CTRL_GMII_CLK_EN (1 << 7) +#define ETH_RGMII_CTRL_MII_OVERRIDE_EN (1 << 6) +#define ETH_RGMII_CTRL_MII_MODE_MASK (3 << 4) +#define ETH_RGMII_CTRL_RGMII_MODE (0 << 4) +#define ETH_RGMII_CTRL_MII_MODE (1 << 4) +#define ETH_RGMII_CTRL_RVMII_MODE (2 << 4) +#define ETH_RGMII_CTRL_TIMING_SEL_EN (1 << 0) + +/* Port RGMII timing register */ +#define ENETSW_RGMII_TIMING_REG(x) (0x68 + (x)) + +/* MDIO control register */ +#define MII_SC_REG 0xb0 +#define MII_SC_EXT_SHIFT 16 +#define MII_SC_EXT_MASK (1 << MII_SC_EXT_SHIFT) +#define MII_SC_REG_SHIFT 20 +#define MII_SC_PHYID_SHIFT 25 +#define MII_SC_RD_SHIFT 30 +#define MII_SC_RD_MASK (1 << MII_SC_RD_SHIFT) +#define MII_SC_WR_SHIFT 31 +#define MII_SC_WR_MASK (1 << MII_SC_WR_SHIFT) + +/* MDIO data register */ +#define MII_DAT_REG 0xb4 + +/* Global Management Configuration Register */ +#define ETH_GMCR_REG 0x200 +#define ETH_GMCR_RST_MIB_SHIFT 0 +#define ETH_GMCR_RST_MIB_MASK (1 << ETH_GMCR_RST_MIB_SHIFT) + +/* Jumbo control register port mask register */ +#define ETH_JMBCTL_PORT_REG 0x4004 + +/* Jumbo control mib good frame register */ +#define ETH_JMBCTL_MAXSIZE_REG 0x4008 + +/* ETH port data */ +struct bcm_enetsw_port { + bool used; + const char *name; + /* Config */ + bool bypass_link; + int force_speed; + bool force_duplex_full; + /* PHY */ + int phy_id; +}; + +/* ETH data */ +struct bcm6368_eth_priv { + void __iomem *base; + /* DMA */ + struct dma rx_dma; + struct dma tx_dma; + /* Ports */ + uint8_t num_ports; + struct bcm_enetsw_port used_ports[ETH_MAX_PORT]; + int sw_port_link[ETH_MAX_PORT]; + bool rgmii_override; + bool rgmii_timing; + /* PHY */ + int phy_id; +}; + +static inline bool bcm_enet_port_is_rgmii(int portid) +{ + return portid >= ETH_RGMII_PORT0; +} + +static int bcm6368_mdio_read(struct bcm6368_eth_priv *priv, uint8_t ext, + int phy_id, int reg) +{ + uint32_t val; + + writel_be(0, priv->base + MII_SC_REG); + + val = MII_SC_RD_MASK | + (phy_id << MII_SC_PHYID_SHIFT) | + (reg << MII_SC_REG_SHIFT); + + if (ext) + val |= MII_SC_EXT_MASK; + + writel_be(val, priv->base + MII_SC_REG); + udelay(50); + + return readw_be(priv->base + MII_DAT_REG); +} + +static int bcm6368_mdio_write(struct bcm6368_eth_priv *priv, uint8_t ext, + int phy_id, int reg, u16 data) +{ + uint32_t val; + + writel_be(0, priv->base + MII_SC_REG); + + val = MII_SC_WR_MASK | + (phy_id << MII_SC_PHYID_SHIFT) | + (reg << MII_SC_REG_SHIFT); + + if (ext) + val |= MII_SC_EXT_MASK; + + val |= data; + + writel_be(val, priv->base + MII_SC_REG); + udelay(50); + + return 0; +} + +static int bcm6368_eth_free_pkt(struct udevice *dev, uchar *packet, int len) +{ + struct bcm6368_eth_priv *priv = dev_get_priv(dev); + + return dma_prepare_rcv_buf(&priv->rx_dma, packet, len); +} + +static int bcm6368_eth_recv(struct udevice *dev, int flags, uchar **packetp) +{ + struct bcm6368_eth_priv *priv = dev_get_priv(dev); + + return dma_receive(&priv->rx_dma, (void**)packetp, NULL); +} + +static int bcm6368_eth_send(struct udevice *dev, void *packet, int length) +{ + struct bcm6368_eth_priv *priv = dev_get_priv(dev); + + /* pad packets smaller than ETH_ZLEN */ + if (length < ETH_ZLEN) { + memset(packet + length, 0, ETH_ZLEN - length); + length = ETH_ZLEN; + } + + return dma_send(&priv->tx_dma, packet, length, NULL); +} + +static int bcm6368_eth_adjust_link(struct udevice *dev) +{ + struct bcm6368_eth_priv *priv = dev_get_priv(dev); + unsigned int i; + + for (i = 0; i < priv->num_ports; i++) { + struct bcm_enetsw_port *port; + int val, j, up, adv, lpa, speed, duplex, media; + int external_phy = bcm_enet_port_is_rgmii(i); + u8 override; + + port = &priv->used_ports[i]; + if (!port->used) + continue; + + if (port->bypass_link) + continue; + + /* dummy read to clear */ + for (j = 0; j < 2; j++) + val = bcm6368_mdio_read(priv, external_phy, + port->phy_id, MII_BMSR); + + if (val == 0xffff) + continue; + + up = (val & BMSR_LSTATUS) ? 1 : 0; + if (!(up ^ priv->sw_port_link[i])) + continue; + + priv->sw_port_link[i] = up; + + /* link changed */ + if (!up) { + dev_info(&priv->pdev->dev, "link DOWN on %s\n", + port->name); + writeb_be(ETH_PORTOV_ENABLE_MASK, + priv->base + ETH_PORTOV_REG(i)); + writeb_be(ETH_PTCTRL_RXDIS_MASK | + ETH_PTCTRL_TXDIS_MASK, + priv->base + ETH_PTCTRL_REG(i)); + continue; + } + + adv = bcm6368_mdio_read(priv, external_phy, + port->phy_id, MII_ADVERTISE); + + lpa = bcm6368_mdio_read(priv, external_phy, port->phy_id, + MII_LPA); + + /* figure out media and duplex from advertise and LPA values */ + media = mii_nway_result(lpa & adv); + duplex = (media & ADVERTISE_FULL) ? 1 : 0; + + if (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)) + speed = 100; + else + speed = 10; + + if (val & BMSR_ESTATEN) { + adv = bcm6368_mdio_read(priv, external_phy, + port->phy_id, MII_CTRL1000); + + lpa = bcm6368_mdio_read(priv, external_phy, + port->phy_id, MII_STAT1000); + + if ((adv & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) && + (lpa & (LPA_1000FULL | LPA_1000HALF))) { + speed = 1000; + duplex = (lpa & LPA_1000FULL); + } + } + + pr_alert("link UP on %s, %dMbps, %s-duplex\n", + port->name, speed, duplex ? "full" : "half"); + + override = ETH_PORTOV_ENABLE_MASK | + ETH_PORTOV_LINKUP_MASK; + + if (speed == 1000) + override |= ETH_PORTOV_1000_MASK; + else if (speed == 100) + override |= ETH_PORTOV_100_MASK; + if (duplex) + override |= ETH_PORTOV_FDX_MASK; + + writeb_be(override, priv->base + ETH_PORTOV_REG(i)); + writeb_be(0, priv->base + ETH_PTCTRL_REG(i)); + } + + return 0; +} + +static int bcm6368_eth_start(struct udevice *dev) +{ + struct bcm6368_eth_priv *priv = dev_get_priv(dev); + uint8_t i; + + /* prepare rx dma buffers */ + for (i = 0; i < ETH_RX_DESC; i++) { + int ret = dma_prepare_rcv_buf(&priv->rx_dma, net_rx_packets[i], + PKTSIZE_ALIGN); + if (ret < 0) + break; + } + + /* enable dma rx channel */ + dma_enable(&priv->rx_dma); + + /* enable dma tx channel */ + dma_enable(&priv->tx_dma); + + /* apply override config for bypass_link ports here. */ + for (i = 0; i < priv->num_ports; i++) { + struct bcm_enetsw_port *port; + u8 override; + + port = &priv->used_ports[i]; + if (!port->used) + continue; + + if (!port->bypass_link) + continue; + + override = ETH_PORTOV_ENABLE_MASK | + ETH_PORTOV_LINKUP_MASK; + + switch (port->force_speed) { + case 1000: + override |= ETH_PORTOV_1000_MASK; + break; + case 100: + override |= ETH_PORTOV_100_MASK; + break; + case 10: + break; + default: + pr_warn("%s: invalid forced speed on port %s\n", + __func__, port->name); + break; + } + + if (port->force_duplex_full) + override |= ETH_PORTOV_FDX_MASK; + + writeb_be(override, priv->base + ETH_PORTOV_REG(i)); + writeb_be(0, priv->base + ETH_PTCTRL_REG(i)); + } + + bcm6368_eth_adjust_link(dev); + + return 0; +} + +static void bcm6368_eth_stop(struct udevice *dev) +{ + struct bcm6368_eth_priv *priv = dev_get_priv(dev); + + /* disable dma rx channel */ + dma_disable(&priv->rx_dma); + + /* disable dma tx channel */ + dma_disable(&priv->tx_dma); +} + +static const struct eth_ops bcm6368_eth_ops = { + .free_pkt = bcm6368_eth_free_pkt, + .recv = bcm6368_eth_recv, + .send = bcm6368_eth_send, + .start = bcm6368_eth_start, + .stop = bcm6368_eth_stop, +}; + +static const struct udevice_id bcm6368_eth_ids[] = { + { .compatible = "brcm,bcm6368-enet", }, + { /* sentinel */ } +}; + +static bool bcm6368_phy_is_external(struct bcm6368_eth_priv *priv, int phy_id) +{ + uint8_t i; + + for (i = 0; i < priv->num_ports; ++i) { + if (!priv->used_ports[i].used) + continue; + if (priv->used_ports[i].phy_id == phy_id) + return bcm_enet_port_is_rgmii(i); + } + + return true; +} + +static int bcm6368_mii_mdio_read(struct mii_dev *bus, int addr, int devaddr, + int reg) +{ + struct bcm6368_eth_priv *priv = bus->priv; + bool ext = bcm6368_phy_is_external(priv, addr); + + return bcm6368_mdio_read(priv, ext, addr, reg); +} + +static int bcm6368_mii_mdio_write(struct mii_dev *bus, int addr, int devaddr, + int reg, u16 data) +{ + struct bcm6368_eth_priv *priv = bus->priv; + bool ext = bcm6368_phy_is_external(priv, addr); + + return bcm6368_mdio_write(priv, ext, addr, reg, data); +} + +static int bcm6368_mdio_init(const char *name, struct bcm6368_eth_priv *priv) +{ + struct mii_dev *bus; + + bus = mdio_alloc(); + if (!bus) { + pr_err("%s: failed to allocate MDIO bus\n", __func__); + return -ENOMEM; + } + + bus->read = bcm6368_mii_mdio_read; + bus->write = bcm6368_mii_mdio_write; + bus->priv = priv; + snprintf(bus->name, sizeof(bus->name), "%s", name); + + return mdio_register(bus); +} + +static int bcm6368_eth_probe(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + struct bcm6368_eth_priv *priv = dev_get_priv(dev); + int num_ports, ret, i; + uint32_t val; + ofnode node; + + /* get base address */ + priv->base = dev_remap_addr(dev); + if (!priv->base) + return -EINVAL; + pdata->iobase = (phys_addr_t) priv->base; + + /* get number of ports */ + num_ports = dev_read_u32_default(dev, "brcm,num-ports", ETH_MAX_PORT); + if (!num_ports || num_ports > ETH_MAX_PORT) + return -EINVAL; + + /* get dma channels */ + ret = dma_get_by_name(dev, "tx", &priv->tx_dma); + if (ret) + return -EINVAL; + + ret = dma_get_by_name(dev, "rx", &priv->rx_dma); + if (ret) + return -EINVAL; + + /* try to enable clocks */ + for (i = 0; ; i++) { + struct clk clk; + int ret; + + ret = clk_get_by_index(dev, i, &clk); + if (ret < 0) + break; + + ret = clk_enable(&clk); + if (ret < 0) { + pr_err("%s: error enabling clock %d\n", __func__, i); + return ret; + } + + ret = clk_free(&clk); + if (ret < 0) { + pr_err("%s: error freeing clock %d\n", __func__, i); + return ret; + } + } + + /* try to perform resets */ + for (i = 0; ; i++) { + struct reset_ctl reset; + int ret; + + ret = reset_get_by_index(dev, i, &reset); + if (ret < 0) + break; + + ret = reset_deassert(&reset); + if (ret < 0) { + pr_err("%s: error deasserting reset %d\n", __func__, i); + return ret; + } + + ret = reset_free(&reset); + if (ret < 0) { + pr_err("%s: error freeing reset %d\n", __func__, i); + return ret; + } + } + + /* set priv data */ + priv->num_ports = num_ports; + if (dev_read_bool(dev, "brcm,rgmii-override")) + priv->rgmii_override = true; + if (dev_read_bool(dev, "brcm,rgmii-timing")) + priv->rgmii_timing = true; + + /* get ports */ + dev_for_each_subnode(node, dev) { + const char *comp; + const char *label; + unsigned int p; + int phy_id; + int speed; + + comp = ofnode_read_string(node, "compatible"); + if (!comp || memcmp(comp, ETH_PORT_STR, sizeof(ETH_PORT_STR))) + continue; + + p = ofnode_read_u32_default(node, "reg", ETH_MAX_PORT); + if (p >= num_ports) + return -EINVAL; + + label = ofnode_read_string(node, "label"); + if (!label) { + debug("%s: node %s has no label\n", __func__, + ofnode_get_name(node)); + return -EINVAL; + } + + phy_id = ofnode_read_u32_default(node, "brcm,phy-id", -1); + + priv->used_ports[p].used = true; + priv->used_ports[p].name = label; + priv->used_ports[p].phy_id = phy_id; + + if (ofnode_read_bool(node, "full-duplex")) + priv->used_ports[p].force_duplex_full = true; + if (ofnode_read_bool(node, "bypass-link")) + priv->used_ports[p].bypass_link = true; + speed = ofnode_read_u32_default(node, "speed", 0); + if (speed) + priv->used_ports[p].force_speed = speed; + } + + /* init mii bus */ + ret = bcm6368_mdio_init(dev->name, priv); + if (ret) + return ret; + + /* disable all ports */ + for (i = 0; i < priv->num_ports; i++) { + writeb_be(ETH_PORTOV_ENABLE_MASK, + priv->base + ETH_PORTOV_REG(i)); + writeb_be(ETH_PTCTRL_RXDIS_MASK | + ETH_PTCTRL_TXDIS_MASK, + priv->base + ETH_PTCTRL_REG(i)); + + priv->sw_port_link[i] = 0; + } + + /* enable external ports */ + for (i = ETH_RGMII_PORT0; i < priv->num_ports; i++) { + u8 rgmii_ctrl; + + if (!priv->used_ports[i].used) + continue; + + rgmii_ctrl = readb_be(priv->base + ETH_RGMII_CTRL_REG(i)); + rgmii_ctrl |= ETH_RGMII_CTRL_GMII_CLK_EN; + if (priv->rgmii_override) + rgmii_ctrl |= ETH_RGMII_CTRL_MII_OVERRIDE_EN; + if (priv->rgmii_timing) + rgmii_ctrl |= ETH_RGMII_CTRL_TIMING_SEL_EN; + writeb_be(rgmii_ctrl, priv->base + ETH_RGMII_CTRL_REG(i)); + } + + /* reset mib */ + val = readb_be(priv->base + ETH_GMCR_REG); + val |= ETH_GMCR_RST_MIB_MASK; + writeb_be(val, priv->base + ETH_GMCR_REG); + mdelay(1); + val &= ~ETH_GMCR_RST_MIB_MASK; + writeb_be(val, priv->base + ETH_GMCR_REG); + mdelay(1); + + /* force CPU port state */ + val = readb_be(priv->base + ETH_IMPOV_REG); + val |= ETH_IMPOV_FORCE_MASK | ETH_IMPOV_LINKUP_MASK; + writeb_be(val, priv->base + ETH_IMPOV_REG); + + /* enable switch forward engine */ + val = readb_be(priv->base + ETH_SWMODE_REG); + val |= ETH_SWMODE_FWD_EN_MASK; + writeb_be(val, priv->base + ETH_SWMODE_REG); + + /* enable jumbo on all ports */ + writel_be(0x1ff, priv->base + ETH_JMBCTL_PORT_REG); + writew_be(9728, priv->base + ETH_JMBCTL_MAXSIZE_REG); + + return 0; +} + +U_BOOT_DRIVER(bcm6368_eth) = { + .name = "bcm6368_eth", + .id = UCLASS_ETH, + .of_match = bcm6368_eth_ids, + .ops = &bcm6368_eth_ops, + .platdata_auto_alloc_size = sizeof(struct eth_pdata), + .priv_auto_alloc_size = sizeof(struct bcm6368_eth_priv), + .probe = bcm6368_eth_probe, +}; diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 99c5c649a0a..32fb34b7932 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -604,7 +604,7 @@ static int fec_init(struct eth_device *dev, bd_t *bd) writel(0x00000000, &fec->eth->gaddr2); /* Do not access reserved register */ - if (!is_mx6ul() && !is_mx6ull() && !is_mx8m()) { + if (!is_mx6ul() && !is_mx6ull() && !is_imx8m()) { /* clear MIB RAM */ for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4) writel(0, i); diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index e837eb7688c..cda4caa8034 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -656,7 +656,8 @@ static struct phy_device *phy_device_create(struct mii_dev *bus, int addr, phy_probe(dev); - bus->phymap[addr] = dev; + if (addr >= 0 && addr < PHY_MAX_ADDR) + bus->phymap[addr] = dev; return dev; } diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 7e6fad305ae..30a6aa6ee8e 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -238,6 +238,16 @@ config PINCTRL_ROCKCHIP_RK3399 the GPIO definitions and pin control functions for each available multiplex function. +config PINCTRL_ROCKCHIP_RK3399_FULL + bool "Rockchip rk3399 pin control driver (full)" + depends on PINCTRL_FULL && PINCTRL_ROCKCHIP_RK3399 + help + Support full pin multiplexing control on Rockchip rk3399 SoCs. + + This enables the full pinctrl driver for the RK3399. + Contrary to the non-full pinctrl driver, this will evaluate + the board DTB to get the pinctrl settings. + config PINCTRL_ROCKCHIP_RV1108 bool "Rockchip rv1108 pin control driver" depends on DM @@ -306,6 +316,7 @@ source "drivers/pinctrl/nxp/Kconfig" source "drivers/pinctrl/renesas/Kconfig" source "drivers/pinctrl/uniphier/Kconfig" source "drivers/pinctrl/exynos/Kconfig" +source "drivers/pinctrl/mscc/Kconfig" source "drivers/pinctrl/mvebu/Kconfig" source "drivers/pinctrl/broadcom/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 293bad3a950..66d36b99d1e 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_PINCTRL_PIC32) += pinctrl_pic32.o obj-$(CONFIG_PINCTRL_EXYNOS) += exynos/ obj-$(CONFIG_PINCTRL_MESON) += meson/ obj-$(CONFIG_PINCTRL_MTK) += mediatek/ +obj-$(CONFIG_PINCTRL_MSCC) += mscc/ obj-$(CONFIG_ARCH_MVEBU) += mvebu/ obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o obj-$(CONFIG_PINCTRL_STI) += pinctrl-sti.o diff --git a/drivers/pinctrl/mscc/Kconfig b/drivers/pinctrl/mscc/Kconfig new file mode 100644 index 00000000000..cfc6c060767 --- /dev/null +++ b/drivers/pinctrl/mscc/Kconfig @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +config PINCTRL_MSCC + bool + +config PINCTRL_MSCC_OCELOT + depends on SOC_OCELOT && PINCTRL_FULL && OF_CONTROL + select PINCTRL_MSCC + default y + bool "Microsemi ocelot family pin control driver" + help + Support pin multiplexing and pin configuration control on + Microsemi ocelot SoCs. + +config PINCTRL_MSCC_LUTON + depends on SOC_LUTON && PINCTRL_FULL && OF_CONTROL + select PINCTRL_MSCC + default y + bool "Microsemi luton family pin control driver" + help + Support pin multiplexing and pin configuration control on + Microsemi luton SoCs. diff --git a/drivers/pinctrl/mscc/Makefile b/drivers/pinctrl/mscc/Makefile new file mode 100644 index 00000000000..69106717282 --- /dev/null +++ b/drivers/pinctrl/mscc/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +obj-y += mscc-common.o +obj-$(CONFIG_PINCTRL_MSCC_OCELOT) += pinctrl-ocelot.o +obj-$(CONFIG_PINCTRL_MSCC_LUTON) += pinctrl-luton.o diff --git a/drivers/pinctrl/mscc/mscc-common.c b/drivers/pinctrl/mscc/mscc-common.c new file mode 100644 index 00000000000..d74b8a66492 --- /dev/null +++ b/drivers/pinctrl/mscc/mscc-common.c @@ -0,0 +1,236 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Microsemi SoCs pinctrl driver + * + * Author: <alexandre.belloni@free-electrons.com> + * Author: <gregory.clement@bootlin.com> + * License: Dual MIT/GPL + * Copyright (c) 2017 Microsemi Corporation + */ + +#include <asm/gpio.h> +#include <asm/system.h> +#include <common.h> +#include <config.h> +#include <dm.h> +#include <dm/device-internal.h> +#include <dm/lists.h> +#include <dm/pinctrl.h> +#include <dm/root.h> +#include <errno.h> +#include <fdtdec.h> +#include <linux/io.h> +#include "mscc-common.h" + +#define MSCC_GPIO_OUT_SET 0x0 +#define MSCC_GPIO_OUT_CLR 0x4 +#define MSCC_GPIO_OUT 0x8 +#define MSCC_GPIO_IN 0xc +#define MSCC_GPIO_OE 0x10 +#define MSCC_GPIO_INTR 0x14 +#define MSCC_GPIO_INTR_ENA 0x18 +#define MSCC_GPIO_INTR_IDENT 0x1c +#define MSCC_GPIO_ALT0 0x20 +#define MSCC_GPIO_ALT1 0x24 + +static int mscc_get_functions_count(struct udevice *dev) +{ + struct mscc_pinctrl *info = dev_get_priv(dev); + + return info->num_func; +} + +static const char *mscc_get_function_name(struct udevice *dev, + unsigned int function) +{ + struct mscc_pinctrl *info = dev_get_priv(dev); + + return info->function_names[function]; +} + +static int mscc_pin_function_idx(unsigned int pin, unsigned int function, + const struct mscc_pin_data *mscc_pins) +{ + struct mscc_pin_caps *p = mscc_pins[pin].drv_data; + int i; + + for (i = 0; i < MSCC_FUNC_PER_PIN; i++) { + if (function == p->functions[i]) + return i; + } + + return -1; +} + +static int mscc_pinmux_set_mux(struct udevice *dev, + unsigned int pin_selector, unsigned int selector) +{ + struct mscc_pinctrl *info = dev_get_priv(dev); + struct mscc_pin_caps *pin = info->mscc_pins[pin_selector].drv_data; + int f; + + f = mscc_pin_function_idx(pin_selector, selector, info->mscc_pins); + if (f < 0) + return -EINVAL; + /* + * f is encoded on two bits. + * bit 0 of f goes in BIT(pin) of ALT0, bit 1 of f goes in BIT(pin) of + * ALT1 + * This is racy because both registers can't be updated at the same time + * but it doesn't matter much for now. + */ + if (f & BIT(0)) + setbits_le32(info->regs + MSCC_GPIO_ALT0, BIT(pin->pin)); + else + clrbits_le32(info->regs + MSCC_GPIO_ALT0, BIT(pin->pin)); + + if (f & BIT(1)) + setbits_le32(info->regs + MSCC_GPIO_ALT1, BIT(pin->pin - 1)); + else + clrbits_le32(info->regs + MSCC_GPIO_ALT1, BIT(pin->pin - 1)); + + return 0; +} + +static int mscc_pctl_get_groups_count(struct udevice *dev) +{ + struct mscc_pinctrl *info = dev_get_priv(dev); + + return info->num_pins; +} + +static const char *mscc_pctl_get_group_name(struct udevice *dev, + unsigned int group) +{ + struct mscc_pinctrl *info = dev_get_priv(dev); + + return info->mscc_pins[group].name; +} + +static int mscc_create_group_func_map(struct udevice *dev, + struct mscc_pinctrl *info) +{ + u16 pins[info->num_pins]; + int f, npins, i; + + for (f = 0; f < info->num_func; f++) { + for (npins = 0, i = 0; i < info->num_pins; i++) { + if (mscc_pin_function_idx(i, f, info->mscc_pins) >= 0) + pins[npins++] = i; + } + + info->func[f].ngroups = npins; + info->func[f].groups = devm_kzalloc(dev, npins * + sizeof(char *), GFP_KERNEL); + if (!info->func[f].groups) + return -ENOMEM; + + for (i = 0; i < npins; i++) + info->func[f].groups[i] = info->mscc_pins[pins[i]].name; + } + + return 0; +} + +static int mscc_pinctrl_register(struct udevice *dev, struct mscc_pinctrl *info) +{ + int ret; + + ret = mscc_create_group_func_map(dev, info); + if (ret) { + dev_err(dev, "Unable to create group func map.\n"); + return ret; + } + + return 0; +} + +static int mscc_gpio_get(struct udevice *dev, unsigned int offset) +{ + struct mscc_pinctrl *info = dev_get_priv(dev->parent); + unsigned int val; + + val = readl(info->regs + MSCC_GPIO_IN); + + return !!(val & BIT(offset)); +} + +static int mscc_gpio_set(struct udevice *dev, unsigned int offset, int value) +{ + struct mscc_pinctrl *info = dev_get_priv(dev->parent); + + if (value) + writel(BIT(offset), info->regs + MSCC_GPIO_OUT_SET); + else + writel(BIT(offset), info->regs + MSCC_GPIO_OUT_CLR); + + return 0; +} + +static int mscc_gpio_get_direction(struct udevice *dev, unsigned int offset) +{ + struct mscc_pinctrl *info = dev_get_priv(dev->parent); + unsigned int val; + + val = readl(info->regs + MSCC_GPIO_OE); + + return (val & BIT(offset)) ? GPIOF_OUTPUT : GPIOF_INPUT; +} + +static int mscc_gpio_direction_input(struct udevice *dev, unsigned int offset) +{ + struct mscc_pinctrl *info = dev_get_priv(dev->parent); + + clrbits_le32(info->regs + MSCC_GPIO_OE, BIT(offset)); + + return 0; +} + +static int mscc_gpio_direction_output(struct udevice *dev, + unsigned int offset, int value) +{ + struct mscc_pinctrl *info = dev_get_priv(dev->parent); + + setbits_le32(info->regs + MSCC_GPIO_OE, BIT(offset)); + + return mscc_gpio_set(dev, offset, value); +} + +const struct dm_gpio_ops mscc_gpio_ops = { + .set_value = mscc_gpio_set, + .get_value = mscc_gpio_get, + .get_function = mscc_gpio_get_direction, + .direction_input = mscc_gpio_direction_input, + .direction_output = mscc_gpio_direction_output, +}; + +const struct pinctrl_ops mscc_pinctrl_ops = { + .get_pins_count = mscc_pctl_get_groups_count, + .get_pin_name = mscc_pctl_get_group_name, + .get_functions_count = mscc_get_functions_count, + .get_function_name = mscc_get_function_name, + .pinmux_set = mscc_pinmux_set_mux, + .set_state = pinctrl_generic_set_state, +}; + +int mscc_pinctrl_probe(struct udevice *dev, int num_func, + const struct mscc_pin_data *mscc_pins, int num_pins, + char *const *function_names) +{ + struct mscc_pinctrl *priv = dev_get_priv(dev); + int ret; + + priv->regs = dev_remap_addr(dev); + if (!priv->regs) + return -EINVAL; + + priv->func = devm_kzalloc(dev, num_func * sizeof(struct mscc_pmx_func), + GFP_KERNEL); + priv->num_func = num_func; + priv->mscc_pins = mscc_pins; + priv->num_pins = num_pins; + priv->function_names = function_names; + ret = mscc_pinctrl_register(dev, priv); + + return ret; +} diff --git a/drivers/pinctrl/mscc/mscc-common.h b/drivers/pinctrl/mscc/mscc-common.h new file mode 100644 index 00000000000..b0001db44c9 --- /dev/null +++ b/drivers/pinctrl/mscc/mscc-common.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Microsemi SoCs pinctrl driver + * + * Author: <alexandre.belloni@free-electrons.com> + * License: Dual MIT/GPL + * Copyright (c) 2017 Microsemi Corporation + */ + +#define MSCC_FUNC_PER_PIN 4 + +struct mscc_pin_caps { + unsigned int pin; + unsigned char functions[MSCC_FUNC_PER_PIN]; +}; + +struct mscc_pin_data { + const char *name; + struct mscc_pin_caps *drv_data; +}; + +#define MSCC_P(p, f0, f1, f2) \ +static struct mscc_pin_caps mscc_pin_##p = { \ + .pin = p, \ + .functions = { \ + FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2, \ + }, \ +} + +struct mscc_pmx_func { + const char **groups; + unsigned int ngroups; +}; + +struct mscc_pinctrl { + struct udevice *dev; + struct pinctrl_dev *pctl; + void __iomem *regs; + struct mscc_pmx_func *func; + int num_func; + const struct mscc_pin_data *mscc_pins; + int num_pins; + char * const *function_names; +}; + +int mscc_pinctrl_probe(struct udevice *dev, int num_func, + const struct mscc_pin_data *mscc_pins, int num_pins, + char * const *function_names); +const struct pinctrl_ops mscc_pinctrl_ops; + +const struct dm_gpio_ops mscc_gpio_ops; diff --git a/drivers/pinctrl/mscc/pinctrl-luton.c b/drivers/pinctrl/mscc/pinctrl-luton.c new file mode 100644 index 00000000000..7166588e3cd --- /dev/null +++ b/drivers/pinctrl/mscc/pinctrl-luton.c @@ -0,0 +1,172 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Microsemi SoCs pinctrl driver + * + * Author: <gregory.clement@bootlin.com> + * License: Dual MIT/GPL + * Copyright (c) 2018 Microsemi Corporation + */ + +#include <common.h> +#include <config.h> +#include <dm.h> +#include <dm/device-internal.h> +#include <dm/lists.h> +#include <dm/pinctrl.h> +#include <dm/root.h> +#include <errno.h> +#include <fdtdec.h> +#include <linux/io.h> +#include <asm/gpio.h> +#include <asm/system.h> +#include "mscc-common.h" + +enum { + FUNC_NONE, + FUNC_GPIO, + FUNC_SIO, + FUNC_TACHO, + FUNC_TWI, + FUNC_PHY_LED, + FUNC_EXT_IRQ, + FUNC_SFP, + FUNC_SI, + FUNC_PWM, + FUNC_UART, + FUNC_MAX +}; + +static char * const luton_function_names[] = { + [FUNC_NONE] = "none", + [FUNC_GPIO] = "gpio", + [FUNC_SIO] = "sio", + [FUNC_TACHO] = "tacho", + [FUNC_TWI] = "twi", + [FUNC_PHY_LED] = "phy_led", + [FUNC_EXT_IRQ] = "ext_irq", + [FUNC_SFP] = "sfp", + [FUNC_SI] = "si", + [FUNC_PWM] = "pwm", + [FUNC_UART] = "uart", +}; + +MSCC_P(0, SIO, NONE, NONE); +MSCC_P(1, SIO, NONE, NONE); +MSCC_P(2, SIO, NONE, NONE); +MSCC_P(3, SIO, NONE, NONE); +MSCC_P(4, TACHO, NONE, NONE); +MSCC_P(5, TWI, PHY_LED, NONE); +MSCC_P(6, TWI, PHY_LED, NONE); +MSCC_P(7, NONE, PHY_LED, NONE); +MSCC_P(8, EXT_IRQ, PHY_LED, NONE); +MSCC_P(9, EXT_IRQ, PHY_LED, NONE); +MSCC_P(10, SFP, PHY_LED, NONE); +MSCC_P(11, SFP, PHY_LED, NONE); +MSCC_P(12, SFP, PHY_LED, NONE); +MSCC_P(13, SFP, PHY_LED, NONE); +MSCC_P(14, SI, PHY_LED, NONE); +MSCC_P(15, SI, PHY_LED, NONE); +MSCC_P(16, SI, PHY_LED, NONE); +MSCC_P(17, SFP, PHY_LED, NONE); +MSCC_P(18, SFP, PHY_LED, NONE); +MSCC_P(19, SFP, PHY_LED, NONE); +MSCC_P(20, SFP, PHY_LED, NONE); +MSCC_P(21, SFP, PHY_LED, NONE); +MSCC_P(22, SFP, PHY_LED, NONE); +MSCC_P(23, SFP, PHY_LED, NONE); +MSCC_P(24, SFP, PHY_LED, NONE); +MSCC_P(25, SFP, PHY_LED, NONE); +MSCC_P(26, SFP, PHY_LED, NONE); +MSCC_P(27, SFP, PHY_LED, NONE); +MSCC_P(28, SFP, PHY_LED, NONE); +MSCC_P(29, PWM, NONE, NONE); +MSCC_P(30, UART, NONE, NONE); +MSCC_P(31, UART, NONE, NONE); + +#define LUTON_PIN(n) { \ + .name = "GPIO_"#n, \ + .drv_data = &mscc_pin_##n \ +} + +static const struct mscc_pin_data luton_pins[] = { + LUTON_PIN(0), + LUTON_PIN(1), + LUTON_PIN(2), + LUTON_PIN(3), + LUTON_PIN(4), + LUTON_PIN(5), + LUTON_PIN(6), + LUTON_PIN(7), + LUTON_PIN(8), + LUTON_PIN(9), + LUTON_PIN(10), + LUTON_PIN(11), + LUTON_PIN(12), + LUTON_PIN(13), + LUTON_PIN(14), + LUTON_PIN(15), + LUTON_PIN(16), + LUTON_PIN(17), + LUTON_PIN(18), + LUTON_PIN(19), + LUTON_PIN(20), + LUTON_PIN(21), + LUTON_PIN(22), + LUTON_PIN(23), + LUTON_PIN(24), + LUTON_PIN(25), + LUTON_PIN(26), + LUTON_PIN(27), + LUTON_PIN(28), + LUTON_PIN(29), + LUTON_PIN(30), + LUTON_PIN(31), +}; + +static int luton_gpio_probe(struct udevice *dev) +{ + struct gpio_dev_priv *uc_priv; + + uc_priv = dev_get_uclass_priv(dev); + uc_priv->bank_name = "luton-gpio"; + uc_priv->gpio_count = ARRAY_SIZE(luton_pins); + + return 0; +} + +static struct driver luton_gpio_driver = { + .name = "luton-gpio", + .id = UCLASS_GPIO, + .probe = luton_gpio_probe, + .ops = &mscc_gpio_ops, +}; + +int luton_pinctrl_probe(struct udevice *dev) +{ + int ret; + + ret = mscc_pinctrl_probe(dev, FUNC_MAX, luton_pins, + ARRAY_SIZE(luton_pins), luton_function_names); + + if (ret) + return ret; + + ret = device_bind(dev, &luton_gpio_driver, "luton-gpio", NULL, + dev_of_offset(dev), NULL); + + return 0; +} + +static const struct udevice_id luton_pinctrl_of_match[] = { + {.compatible = "mscc,luton-pinctrl"}, + {}, +}; + +U_BOOT_DRIVER(luton_pinctrl) = { + .name = "luton-pinctrl", + .id = UCLASS_PINCTRL, + .of_match = of_match_ptr(luton_pinctrl_of_match), + .probe = luton_pinctrl_probe, + .priv_auto_alloc_size = sizeof(struct mscc_pinctrl), + .ops = &mscc_pinctrl_ops, +}; diff --git a/drivers/pinctrl/mscc/pinctrl-ocelot.c b/drivers/pinctrl/mscc/pinctrl-ocelot.c new file mode 100644 index 00000000000..10f9b90aadc --- /dev/null +++ b/drivers/pinctrl/mscc/pinctrl-ocelot.c @@ -0,0 +1,188 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Microsemi SoCs pinctrl driver + * + * Author: <alexandre.belloni@free-electrons.com> + * Author: <gregory.clement@bootlin.com> + * License: Dual MIT/GPL + * Copyright (c) 2017 Microsemi Corporation + */ + +#include <asm/gpio.h> +#include <asm/system.h> +#include <common.h> +#include <config.h> +#include <dm.h> +#include <dm/device-internal.h> +#include <dm/lists.h> +#include <dm/pinctrl.h> +#include <dm/root.h> +#include <errno.h> +#include <fdtdec.h> +#include <linux/io.h> +#include "mscc-common.h" + +enum { + FUNC_NONE, + FUNC_GPIO, + FUNC_IRQ0_IN, + FUNC_IRQ0_OUT, + FUNC_IRQ1_IN, + FUNC_IRQ1_OUT, + FUNC_MIIM1, + FUNC_PCI_WAKE, + FUNC_PTP0, + FUNC_PTP1, + FUNC_PTP2, + FUNC_PTP3, + FUNC_PWM, + FUNC_RECO_CLK0, + FUNC_RECO_CLK1, + FUNC_SFP0, + FUNC_SFP1, + FUNC_SFP2, + FUNC_SFP3, + FUNC_SFP4, + FUNC_SFP5, + FUNC_SG0, + FUNC_SI, + FUNC_TACHO, + FUNC_TWI, + FUNC_TWI_SCL_M, + FUNC_UART, + FUNC_UART2, + FUNC_MAX +}; + +static char * const ocelot_function_names[] = { + [FUNC_NONE] = "none", + [FUNC_GPIO] = "gpio", + [FUNC_IRQ0_IN] = "irq0_in", + [FUNC_IRQ0_OUT] = "irq0_out", + [FUNC_IRQ1_IN] = "irq1_in", + [FUNC_IRQ1_OUT] = "irq1_out", + [FUNC_MIIM1] = "miim1", + [FUNC_PCI_WAKE] = "pci_wake", + [FUNC_PTP0] = "ptp0", + [FUNC_PTP1] = "ptp1", + [FUNC_PTP2] = "ptp2", + [FUNC_PTP3] = "ptp3", + [FUNC_PWM] = "pwm", + [FUNC_RECO_CLK0] = "reco_clk0", + [FUNC_RECO_CLK1] = "reco_clk1", + [FUNC_SFP0] = "sfp0", + [FUNC_SFP1] = "sfp1", + [FUNC_SFP2] = "sfp2", + [FUNC_SFP3] = "sfp3", + [FUNC_SFP4] = "sfp4", + [FUNC_SFP5] = "sfp5", + [FUNC_SG0] = "sg0", + [FUNC_SI] = "si", + [FUNC_TACHO] = "tacho", + [FUNC_TWI] = "twi", + [FUNC_TWI_SCL_M] = "twi_scl_m", + [FUNC_UART] = "uart", + [FUNC_UART2] = "uart2", +}; + +MSCC_P(0, SG0, NONE, NONE); +MSCC_P(1, SG0, NONE, NONE); +MSCC_P(2, SG0, NONE, NONE); +MSCC_P(3, SG0, NONE, NONE); +MSCC_P(4, IRQ0_IN, IRQ0_OUT, TWI); +MSCC_P(5, IRQ1_IN, IRQ1_OUT, PCI_WAKE); +MSCC_P(6, UART, TWI_SCL_M, NONE); +MSCC_P(7, UART, TWI_SCL_M, NONE); +MSCC_P(8, SI, TWI_SCL_M, IRQ0_OUT); +MSCC_P(9, SI, TWI_SCL_M, IRQ1_OUT); +MSCC_P(10, PTP2, TWI_SCL_M, SFP0); +MSCC_P(11, PTP3, TWI_SCL_M, SFP1); +MSCC_P(12, UART2, TWI_SCL_M, SFP2); +MSCC_P(13, UART2, TWI_SCL_M, SFP3); +MSCC_P(14, MIIM1, TWI_SCL_M, SFP4); +MSCC_P(15, MIIM1, TWI_SCL_M, SFP5); +MSCC_P(16, TWI, NONE, SI); +MSCC_P(17, TWI, TWI_SCL_M, SI); +MSCC_P(18, PTP0, TWI_SCL_M, NONE); +MSCC_P(19, PTP1, TWI_SCL_M, NONE); +MSCC_P(20, RECO_CLK0, TACHO, NONE); +MSCC_P(21, RECO_CLK1, PWM, NONE); + +#define OCELOT_PIN(n) { \ + .name = "GPIO_"#n, \ + .drv_data = &mscc_pin_##n \ +} + +static const struct mscc_pin_data ocelot_pins[] = { + OCELOT_PIN(0), + OCELOT_PIN(1), + OCELOT_PIN(2), + OCELOT_PIN(3), + OCELOT_PIN(4), + OCELOT_PIN(5), + OCELOT_PIN(6), + OCELOT_PIN(7), + OCELOT_PIN(8), + OCELOT_PIN(9), + OCELOT_PIN(10), + OCELOT_PIN(11), + OCELOT_PIN(12), + OCELOT_PIN(13), + OCELOT_PIN(14), + OCELOT_PIN(15), + OCELOT_PIN(16), + OCELOT_PIN(17), + OCELOT_PIN(18), + OCELOT_PIN(19), + OCELOT_PIN(20), + OCELOT_PIN(21), +}; + +static int ocelot_gpio_probe(struct udevice *dev) +{ + struct gpio_dev_priv *uc_priv; + + uc_priv = dev_get_uclass_priv(dev); + uc_priv->bank_name = "ocelot-gpio"; + uc_priv->gpio_count = ARRAY_SIZE(ocelot_pins); + + return 0; +} + +static struct driver ocelot_gpio_driver = { + .name = "ocelot-gpio", + .id = UCLASS_GPIO, + .probe = ocelot_gpio_probe, + .ops = &mscc_gpio_ops, +}; + +int ocelot_pinctrl_probe(struct udevice *dev) +{ + int ret; + + ret = mscc_pinctrl_probe(dev, FUNC_MAX, ocelot_pins, + ARRAY_SIZE(ocelot_pins), + ocelot_function_names); + + if (ret) + return ret; + + ret = device_bind(dev, &ocelot_gpio_driver, "ocelot-gpio", NULL, + dev_of_offset(dev), NULL); + + return ret; +} + +static const struct udevice_id ocelot_pinctrl_of_match[] = { + {.compatible = "mscc,ocelot-pinctrl"}, + {}, +}; + +U_BOOT_DRIVER(ocelot_pinctrl) = { + .name = "ocelot-pinctrl", + .id = UCLASS_PINCTRL, + .of_match = of_match_ptr(ocelot_pinctrl_of_match), + .probe = ocelot_pinctrl_probe, + .priv_auto_alloc_size = sizeof(struct mscc_pinctrl), + .ops = &mscc_pinctrl_ops, +}; diff --git a/drivers/pinctrl/nxp/Kconfig b/drivers/pinctrl/nxp/Kconfig index 799d1d2465b..f1d5a5c50d3 100644 --- a/drivers/pinctrl/nxp/Kconfig +++ b/drivers/pinctrl/nxp/Kconfig @@ -74,3 +74,17 @@ config PINCTRL_IMX8 is different from the linux one, this is a simple implementation, only parses the 'fsl,pins' property and configures related registers. + +config PINCTRL_VYBRID + bool "Vybrid (vf610) pinctrl driver" + depends on ARCH_VF610 && PINCTRL_FULL + select DEVRES + select PINCTRL_IMX + help + Say Y here to enable the Vybrid (vf610) pinctrl driver + + This provides a simple pinctrl driver for Vybrid SoC familiy, + vf610. This feature depends on device tree + configuration. This driver is different from the linux one, + this is a simple implementation, only parses the 'fsl,pins' + property and configure related registers. diff --git a/drivers/pinctrl/nxp/Makefile b/drivers/pinctrl/nxp/Makefile index 310b3b3a2e1..891ee6e4774 100644 --- a/drivers/pinctrl/nxp/Makefile +++ b/drivers/pinctrl/nxp/Makefile @@ -5,3 +5,4 @@ obj-$(CONFIG_PINCTRL_IMX7) += pinctrl-imx7.o obj-$(CONFIG_PINCTRL_IMX7ULP) += pinctrl-imx7ulp.o obj-$(CONFIG_PINCTRL_IMX_SCU) += pinctrl-scu.o obj-$(CONFIG_PINCTRL_IMX8) += pinctrl-imx8.o +obj-$(CONFIG_PINCTRL_VYBRID) += pinctrl-vf610.o diff --git a/drivers/pinctrl/nxp/pinctrl-vf610.c b/drivers/pinctrl/nxp/pinctrl-vf610.c new file mode 100644 index 00000000000..e795b5fd8ac --- /dev/null +++ b/drivers/pinctrl/nxp/pinctrl-vf610.c @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 DENX Software Engineering + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + */ + +#include <common.h> +#include <dm.h> +#include <dm/pinctrl.h> + +#include "pinctrl-imx.h" + +static struct imx_pinctrl_soc_info vf610_pinctrl_soc_info = { + .flags = SHARE_MUX_CONF_REG | ZERO_OFFSET_VALID, +}; + +static int vf610_pinctrl_probe(struct udevice *dev) +{ + struct imx_pinctrl_soc_info *info = + (struct imx_pinctrl_soc_info *)dev_get_driver_data(dev); + + return imx_pinctrl_probe(dev, info); +} + +static const struct udevice_id vf610_pinctrl_match[] = { + { .compatible = "fsl,vf610-iomuxc", + .data = (ulong)&vf610_pinctrl_soc_info }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(vf610_pinctrl) = { + .name = "vf610-pinctrl", + .id = UCLASS_PINCTRL, + .of_match = of_match_ptr(vf610_pinctrl_match), + .probe = vf610_pinctrl_probe, + .remove = imx_pinctrl_remove, + .priv_auto_alloc_size = sizeof(struct imx_pinctrl_priv), + .ops = &imx_pinctrl_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/pinctrl/pinctrl-uclass.c b/drivers/pinctrl/pinctrl-uclass.c index 6db04450670..c8b38d78f6b 100644 --- a/drivers/pinctrl/pinctrl-uclass.c +++ b/drivers/pinctrl/pinctrl-uclass.c @@ -27,6 +27,28 @@ int pinctrl_decode_pin_config(const void *blob, int node) return flags; } +/* + * TODO: this function is temporary for v2019.01. + * It should be renamed to pinctrl_decode_pin_config(), + * the original pinctrl_decode_pin_config() function should + * be removed and all callers of the original function should + * be migrated to use the new one. + */ +int pinctrl_decode_pin_config_dm(struct udevice *dev) +{ + int pinconfig = 0; + + if (dev->uclass->uc_drv->id != UCLASS_PINCONFIG) + return -EINVAL; + + if (dev_read_bool(dev, "bias-pull-up")) + pinconfig |= 1 << PIN_CONFIG_BIAS_PULL_UP; + else if (dev_read_bool(dev, "bias-pull-down")) + pinconfig |= 1 << PIN_CONFIG_BIAS_PULL_DOWN; + + return pinconfig; +} + #if CONFIG_IS_ENABLED(PINCTRL_FULL) /** * pinctrl_config_one() - apply pinctrl settings for a single node @@ -117,9 +139,9 @@ static int pinconfig_post_bind(struct udevice *dev) int ret; dev_for_each_subnode(node, dev) { - if (pre_reloc_only && - !ofnode_pre_reloc(node)) + if (pre_reloc_only ^ ofnode_pre_reloc(node)) continue; + /* * If this node has "compatible" property, this is not * a pin configuration node, but a normal device. skip. diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3399.c b/drivers/pinctrl/rockchip/pinctrl_rk3399.c index bc92dd7c062..5c5af3a0bd4 100644 --- a/drivers/pinctrl/rockchip/pinctrl_rk3399.c +++ b/drivers/pinctrl/rockchip/pinctrl_rk3399.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * (C) 2018 Theobroma Systems Design und Consulting GmbH */ #include <common.h> @@ -14,11 +15,241 @@ #include <asm/arch/clock.h> #include <dm/pinctrl.h> +#if CONFIG_IS_ENABLED(PINCTRL_ROCKCHIP_RK3399_FULL) +static const u32 RK_GRF_P_PULLUP = 1; +static const u32 RK_GRF_P_PULLDOWN = 2; +#endif /* PINCTRL_ROCKCHIP_RK3399_FULL */ + struct rk3399_pinctrl_priv { struct rk3399_grf_regs *grf; struct rk3399_pmugrf_regs *pmugrf; + struct rockchip_pin_bank *banks; +}; + +#if CONFIG_IS_ENABLED(PINCTRL_ROCKCHIP_RK3399_FULL) +/* Location of pinctrl/pinconf registers. */ +enum rk_grf_location { + RK_GRF, + RK_PMUGRF, +}; + +/** + * @nr_pins: number of pins in this bank + * @grf_location: location of pinctrl/pinconf registers + * @bank_num: number of the bank, to account for holes + * @iomux: array describing the 4 iomux sources of the bank + */ +struct rockchip_pin_bank { + u8 nr_pins; + enum rk_grf_location grf_location; + size_t iomux_offset; + size_t pupd_offset; }; +#define PIN_BANK(pins, grf, iomux, pupd) \ + { \ + .nr_pins = pins, \ + .grf_location = grf, \ + .iomux_offset = iomux, \ + .pupd_offset = pupd, \ + } + +static struct rockchip_pin_bank rk3399_pin_banks[] = { + PIN_BANK(16, RK_PMUGRF, + offsetof(struct rk3399_pmugrf_regs, gpio0a_iomux), + offsetof(struct rk3399_pmugrf_regs, gpio0_p)), + PIN_BANK(32, RK_PMUGRF, + offsetof(struct rk3399_pmugrf_regs, gpio1a_iomux), + offsetof(struct rk3399_pmugrf_regs, gpio1_p)), + PIN_BANK(32, RK_GRF, + offsetof(struct rk3399_grf_regs, gpio2a_iomux), + offsetof(struct rk3399_grf_regs, gpio2_p)), + PIN_BANK(32, RK_GRF, + offsetof(struct rk3399_grf_regs, gpio3a_iomux), + offsetof(struct rk3399_grf_regs, gpio3_p)), + PIN_BANK(32, RK_GRF, + offsetof(struct rk3399_grf_regs, gpio4a_iomux), + offsetof(struct rk3399_grf_regs, gpio4_p)), +}; + +static void rk_pinctrl_get_info(uintptr_t base, u32 index, uintptr_t *addr, + u32 *shift, u32 *mask) +{ + /* + * In general we four subsequent 32-bit configuration registers + * per bank (e.g. GPIO2A_P, GPIO2B_P, GPIO2C_P, GPIO2D_P). + * The configuration for each pin has two bits. + * + * @base...contains the address to the first register. + * @index...defines the pin within the bank (0..31). + * @addr...will be the address of the actual register to use + * @shift...will be the bit position in the configuration register + * @mask...will be the (unshifted) mask + */ + + const u32 pins_per_register = 8; + const u32 config_bits_per_pin = 2; + + /* Get the address of the configuration register. */ + *addr = base + (index / pins_per_register) * sizeof(u32); + + /* Get the bit offset within the configuration register. */ + *shift = (index & (pins_per_register - 1)) * config_bits_per_pin; + + /* Get the (unshifted) mask for the configuration pins. */ + *mask = ((1 << config_bits_per_pin) - 1); + + pr_debug("%s: addr=0x%lx, mask=0x%x, shift=0x%x\n", + __func__, *addr, *mask, *shift); +} + +static void rk3399_pinctrl_set_pin_iomux(uintptr_t grf_addr, + struct rockchip_pin_bank *bank, + u32 index, u32 muxval) +{ + uintptr_t iomux_base, addr; + u32 shift, mask; + + iomux_base = grf_addr + bank->iomux_offset; + rk_pinctrl_get_info(iomux_base, index, &addr, &shift, &mask); + + /* Set pinmux register */ + rk_clrsetreg(addr, mask << shift, muxval << shift); +} + +static void rk3399_pinctrl_set_pin_pupd(uintptr_t grf_addr, + struct rockchip_pin_bank *bank, + u32 index, int pinconfig) +{ + uintptr_t pupd_base, addr; + u32 shift, mask, pupdval; + + /* Fast path in case there's nothing to do. */ + if (!pinconfig) + return; + + if (pinconfig & (1 << PIN_CONFIG_BIAS_PULL_UP)) + pupdval = RK_GRF_P_PULLUP; + else if (pinconfig & (1 << PIN_CONFIG_BIAS_PULL_DOWN)) { + pupdval = RK_GRF_P_PULLDOWN; + } else { + /* Flag not supported. */ + pr_warn("%s: Unsupported pinconfig flag: 0x%x\n", __func__, + pinconfig); + return; + } + + pupd_base = grf_addr + (uintptr_t)bank->pupd_offset; + rk_pinctrl_get_info(pupd_base, index, &addr, &shift, &mask); + + /* Set pull-up/pull-down regisrer */ + rk_clrsetreg(addr, mask << shift, pupdval << shift); +} + +static int rk3399_pinctrl_set_pin(struct udevice *dev, u32 banknum, u32 index, + u32 muxval, int pinconfig) +{ + struct rk3399_pinctrl_priv *priv = dev_get_priv(dev); + struct rockchip_pin_bank *bank = &priv->banks[banknum]; + uintptr_t grf_addr; + + pr_debug("%s: 0x%x 0x%x 0x%x 0x%x\n", __func__, banknum, index, muxval, + pinconfig); + + if (bank->grf_location == RK_GRF) + grf_addr = (uintptr_t)priv->grf; + else if (bank->grf_location == RK_PMUGRF) + grf_addr = (uintptr_t)priv->pmugrf; + else + return -EINVAL; + + rk3399_pinctrl_set_pin_iomux(grf_addr, bank, index, muxval); + + rk3399_pinctrl_set_pin_pupd(grf_addr, bank, index, pinconfig); + return 0; +} + +static int rk3399_pinctrl_set_state(struct udevice *dev, struct udevice *config) +{ + /* + * The order of the fields in this struct must match the order of + * the fields in the "rockchip,pins" property. + */ + struct rk_pin { + u32 banknum; + u32 index; + u32 muxval; + u32 phandle; + } __packed; + + u32 *fields = NULL; + const int fields_per_pin = 4; + int num_fields, num_pins; + int ret; + int size; + int i; + struct rk_pin *pin; + + pr_debug("%s: %s\n", __func__, config->name); + + size = dev_read_size(config, "rockchip,pins"); + if (size < 0) + return -EINVAL; + + num_fields = size / sizeof(u32); + num_pins = num_fields / fields_per_pin; + + if (num_fields * sizeof(u32) != size || + num_pins * fields_per_pin != num_fields) { + pr_warn("Invalid number of rockchip,pins fields.\n"); + return -EINVAL; + } + + fields = calloc(num_fields, sizeof(u32)); + if (!fields) + return -ENOMEM; + + ret = dev_read_u32_array(config, "rockchip,pins", fields, num_fields); + if (ret) { + pr_warn("%s: Failed to read rockchip,pins fields.\n", + config->name); + goto end; + } + + pin = (struct rk_pin *)fields; + for (i = 0; i < num_pins; i++, pin++) { + struct udevice *dev_pinconfig; + int pinconfig; + + ret = uclass_get_device_by_phandle_id(UCLASS_PINCONFIG, + pin->phandle, + &dev_pinconfig); + if (ret) { + pr_debug("Could not get pinconfig device\n"); + goto end; + } + + pinconfig = pinctrl_decode_pin_config_dm(dev_pinconfig); + if (pinconfig < 0) { + pr_warn("Could not parse pinconfig\n"); + goto end; + } + + ret = rk3399_pinctrl_set_pin(dev, pin->banknum, pin->index, + pin->muxval, pinconfig); + if (ret) { + pr_warn("Could not set pinctrl settings\n"); + goto end; + } + } + +end: + free(fields); + return ret; +} + +#endif /* PINCTRL_ROCKCHIP_RK3399_FULL */ + static void pinctrl_rk3399_pwm_config(struct rk3399_grf_regs *grf, struct rk3399_pmugrf_regs *pmugrf, int pwm_id) { @@ -468,6 +699,9 @@ static int rk3399_pinctrl_set_state_simple(struct udevice *dev, } static struct pinctrl_ops rk3399_pinctrl_ops = { +#if CONFIG_IS_ENABLED(PINCTRL_ROCKCHIP_RK3399_FULL) + .set_state = rk3399_pinctrl_set_state, +#endif .set_state_simple = rk3399_pinctrl_set_state_simple, .request = rk3399_pinctrl_request, .get_periph_id = rk3399_pinctrl_get_periph_id, @@ -481,6 +715,9 @@ static int rk3399_pinctrl_probe(struct udevice *dev) priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); debug("%s: grf=%p, pmugrf=%p\n", __func__, priv->grf, priv->pmugrf); +#if CONFIG_IS_ENABLED(PINCTRL_ROCKCHIP_RK3399_FULL) + priv->banks = rk3399_pin_banks; +#endif /* PINCTRL_ROCKCHIP_RK3399_FULL */ return ret; } diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig index 09b311de8bb..3ed0dd2264a 100644 --- a/drivers/power/regulator/Kconfig +++ b/drivers/power/regulator/Kconfig @@ -61,6 +61,13 @@ config REGULATOR_PWM This driver is controlled by a device tree node which includes voltage limits. +config SPL_REGULATOR_PWM + bool "Enable Driver for PWM regulators in SPL" + depends on REGULATOR_PWM + help + This config enables implementation of driver-model regulator uclass + features for PWM regulators in SPL. + config DM_REGULATOR_MAX77686 bool "Enable Driver Model for REGULATOR MAX77686" depends on DM_REGULATOR && DM_PMIC_MAX77686 diff --git a/drivers/power/regulator/Makefile b/drivers/power/regulator/Makefile index 8017045d542..f617ce723a9 100644 --- a/drivers/power/regulator/Makefile +++ b/drivers/power/regulator/Makefile @@ -9,7 +9,7 @@ obj-$(CONFIG_REGULATOR_ACT8846) += act8846.o obj-$(CONFIG_REGULATOR_AS3722) += as3722_regulator.o obj-$(CONFIG_DM_REGULATOR_MAX77686) += max77686.o obj-$(CONFIG_$(SPL_)DM_PMIC_PFUZE100) += pfuze100.o -obj-$(CONFIG_REGULATOR_PWM) += pwm_regulator.o +obj-$(CONFIG_$(SPL_)REGULATOR_PWM) += pwm_regulator.o obj-$(CONFIG_$(SPL_)DM_REGULATOR_FAN53555) += fan53555.o obj-$(CONFIG_$(SPL_)DM_REGULATOR_FIXED) += fixed.o obj-$(CONFIG_$(SPL_)DM_REGULATOR_GPIO) += gpio-regulator.o diff --git a/drivers/power/regulator/regulator-uclass.c b/drivers/power/regulator/regulator-uclass.c index 4511625ff25..39e46279d53 100644 --- a/drivers/power/regulator/regulator-uclass.c +++ b/drivers/power/regulator/regulator-uclass.c @@ -113,7 +113,7 @@ int regulator_set_enable(struct udevice *dev, bool enable) uc_pdata = dev_get_uclass_platdata(dev); if (!enable && uc_pdata->always_on) - return -EACCES; + return 0; return ops->set_enable(dev, enable); } diff --git a/drivers/ram/rockchip/sdram_rk3128.c b/drivers/ram/rockchip/sdram_rk3128.c index 49689002114..df7b9887033 100644 --- a/drivers/ram/rockchip/sdram_rk3128.c +++ b/drivers/ram/rockchip/sdram_rk3128.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause /* * (C) Copyright 2017 Rockchip Electronics Co., Ltd. */ diff --git a/drivers/ram/rockchip/sdram_rk3188.c b/drivers/ram/rockchip/sdram_rk3188.c index 3774abfa98a..fdd500aa472 100644 --- a/drivers/ram/rockchip/sdram_rk3188.c +++ b/drivers/ram/rockchip/sdram_rk3188.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause /* * (C) Copyright 2015 Google, Inc * Copyright 2014 Rockchip Inc. diff --git a/drivers/ram/rockchip/sdram_rk322x.c b/drivers/ram/rockchip/sdram_rk322x.c index e079ef7a70c..53835a9cd08 100644 --- a/drivers/ram/rockchip/sdram_rk322x.c +++ b/drivers/ram/rockchip/sdram_rk322x.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause /* * (C) Copyright 2017 Rockchip Electronics Co., Ltd */ diff --git a/drivers/ram/rockchip/sdram_rk3288.c b/drivers/ram/rockchip/sdram_rk3288.c index bb3cf48788c..d1e52d84e7a 100644 --- a/drivers/ram/rockchip/sdram_rk3288.c +++ b/drivers/ram/rockchip/sdram_rk3288.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause /* * (C) Copyright 2015 Google, Inc * Copyright 2014 Rockchip Inc. diff --git a/drivers/ram/rockchip/sdram_rk3328.c b/drivers/ram/rockchip/sdram_rk3328.c index 89d95b4f897..e8b234d8665 100644 --- a/drivers/ram/rockchip/sdram_rk3328.c +++ b/drivers/ram/rockchip/sdram_rk3328.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause /* * (C) Copyright 2017 Rockchip Electronics Co., Ltd. */ diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 49ebd8809f0..94dd01156a7 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause /* * (C) Copyright 2016-2017 Rockchip Inc. * diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 6252dd8c4b5..b7ff2960abf 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -343,6 +343,13 @@ config DEBUG_UART_SANDBOX start up driver model. The driver will be available until the real driver model serial is running. +config DEBUG_UART_SIFIVE + bool "SiFive UART" + help + Select this to enable a debug UART using the serial_sifive driver. You + will need to provide parameters to make this work. The driver will + be available until the real driver-model serial is running. + config DEBUG_UART_STM32 bool "STMicroelectronics STM32" depends on STM32_SERIAL @@ -679,6 +686,12 @@ config PXA_SERIAL If you have a machine based on a Marvell XScale PXA2xx CPU you can enable its onboard serial ports by enabling this option. +config SIFIVE_SERIAL + bool "SiFive UART support" + depends on DM_SERIAL + help + This driver supports the SiFive UART. If unsure say N. + config STI_ASC_SERIAL bool "STMicroelectronics on-chip UART" depends on DM_SERIAL && ARCH_STI diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 2f8d065a4c2..06ee30697de 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -67,6 +67,7 @@ obj-$(CONFIG_NULLDEV_SERIAL) += serial_nulldev.o obj-$(CONFIG_OWL_SERIAL) += serial_owl.o obj-$(CONFIG_OMAP_SERIAL) += serial_omap.o obj-$(CONFIG_MTK_SERIAL) += serial_mtk.o +obj-$(CONFIG_SIFIVE_SERIAL) += serial_sifive.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_USB_TTY) += usbtty.o diff --git a/drivers/serial/serial_sifive.c b/drivers/serial/serial_sifive.c new file mode 100644 index 00000000000..341728a690f --- /dev/null +++ b/drivers/serial/serial_sifive.c @@ -0,0 +1,215 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Anup Patel <anup@brainfault.org> + */ + +#include <clk.h> +#include <common.h> +#include <debug_uart.h> +#include <dm.h> +#include <errno.h> +#include <fdtdec.h> +#include <watchdog.h> +#include <asm/io.h> +#include <linux/compiler.h> +#include <serial.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_TXFIFO_FULL 0x80000000 +#define UART_RXFIFO_EMPTY 0x80000000 +#define UART_RXFIFO_DATA 0x000000ff +#define UART_TXCTRL_TXEN 0x1 +#define UART_RXCTRL_RXEN 0x1 + +struct uart_sifive { + u32 txfifo; + u32 rxfifo; + u32 txctrl; + u32 rxctrl; + u32 ie; + u32 ip; + u32 div; +}; + +struct sifive_uart_platdata { + unsigned int clock; + int saved_input_char; + struct uart_sifive *regs; +}; + +/* Set up the baud rate in gd struct */ +static void _sifive_serial_setbrg(struct uart_sifive *regs, + unsigned long clock, unsigned long baud) +{ + writel((u32)((clock / baud) - 1), ®s->div); +} + +static void _sifive_serial_init(struct uart_sifive *regs) +{ + writel(UART_TXCTRL_TXEN, ®s->txctrl); + writel(UART_RXCTRL_RXEN, ®s->rxctrl); + writel(0, ®s->ie); +} + +static int _sifive_serial_putc(struct uart_sifive *regs, const char c) +{ + if (readl(®s->txfifo) & UART_TXFIFO_FULL) + return -EAGAIN; + + writel(c, ®s->txfifo); + + return 0; +} + +static int _sifive_serial_getc(struct uart_sifive *regs) +{ + int ch = readl(®s->rxfifo); + + if (ch & UART_RXFIFO_EMPTY) + return -EAGAIN; + ch &= UART_RXFIFO_DATA; + + return (!ch) ? -EAGAIN : ch; +} + +static int sifive_serial_setbrg(struct udevice *dev, int baudrate) +{ + int err; + struct clk clk; + struct sifive_uart_platdata *platdata = dev_get_platdata(dev); + + err = clk_get_by_index(dev, 0, &clk); + if (!err) { + err = clk_get_rate(&clk); + if (!IS_ERR_VALUE(err)) + platdata->clock = err; + } else if (err != -ENOENT && err != -ENODEV && err != -ENOSYS) { + debug("SiFive UART failed to get clock\n"); + return err; + } + + if (!platdata->clock) + platdata->clock = dev_read_u32_default(dev, "clock-frequency", 0); + if (!platdata->clock) { + debug("SiFive UART clock not defined\n"); + return -EINVAL; + } + + _sifive_serial_setbrg(platdata->regs, platdata->clock, baudrate); + + return 0; +} + +static int sifive_serial_probe(struct udevice *dev) +{ + struct sifive_uart_platdata *platdata = dev_get_platdata(dev); + + /* No need to reinitialize the UART after relocation */ + if (gd->flags & GD_FLG_RELOC) + return 0; + + platdata->saved_input_char = 0; + _sifive_serial_init(platdata->regs); + + return 0; +} + +static int sifive_serial_getc(struct udevice *dev) +{ + int c; + struct sifive_uart_platdata *platdata = dev_get_platdata(dev); + struct uart_sifive *regs = platdata->regs; + + if (platdata->saved_input_char > 0) { + c = platdata->saved_input_char; + platdata->saved_input_char = 0; + return c; + } + + while ((c = _sifive_serial_getc(regs)) == -EAGAIN) ; + + return c; +} + +static int sifive_serial_putc(struct udevice *dev, const char ch) +{ + int rc; + struct sifive_uart_platdata *platdata = dev_get_platdata(dev); + + while ((rc = _sifive_serial_putc(platdata->regs, ch)) == -EAGAIN) ; + + return rc; +} + +static int sifive_serial_pending(struct udevice *dev, bool input) +{ + struct sifive_uart_platdata *platdata = dev_get_platdata(dev); + struct uart_sifive *regs = platdata->regs; + + if (input) { + if (platdata->saved_input_char > 0) + return 1; + platdata->saved_input_char = _sifive_serial_getc(regs); + return (platdata->saved_input_char > 0) ? 1 : 0; + } else { + return !!(readl(®s->txfifo) & UART_TXFIFO_FULL); + } +} + +static int sifive_serial_ofdata_to_platdata(struct udevice *dev) +{ + struct sifive_uart_platdata *platdata = dev_get_platdata(dev); + + platdata->regs = (struct uart_sifive *)dev_read_addr(dev); + if (IS_ERR(platdata->regs)) + return PTR_ERR(platdata->regs); + + return 0; +} + +static const struct dm_serial_ops sifive_serial_ops = { + .putc = sifive_serial_putc, + .getc = sifive_serial_getc, + .pending = sifive_serial_pending, + .setbrg = sifive_serial_setbrg, +}; + +static const struct udevice_id sifive_serial_ids[] = { + { .compatible = "sifive,uart0" }, + { } +}; + +U_BOOT_DRIVER(serial_sifive) = { + .name = "serial_sifive", + .id = UCLASS_SERIAL, + .of_match = sifive_serial_ids, + .ofdata_to_platdata = sifive_serial_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct sifive_uart_platdata), + .probe = sifive_serial_probe, + .ops = &sifive_serial_ops, +}; + +#ifdef CONFIG_DEBUG_UART_SIFIVE +static inline void _debug_uart_init(void) +{ + struct uart_sifive *regs = + (struct uart_sifive *)CONFIG_DEBUG_UART_BASE; + + _sifive_serial_setbrg(regs, CONFIG_DEBUG_UART_CLOCK, + CONFIG_BAUDRATE); + _sifive_serial_init(regs); +} + +static inline void _debug_uart_putc(int ch) +{ + struct uart_sifive *regs = + (struct uart_sifive *)CONFIG_DEBUG_UART_BASE; + + while (_sifive_serial_putc(regs, ch) == -EAGAIN) + WATCHDOG_RESET(); +} + +DEBUG_UART_FUNCS + +#endif diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c index 5cca4144867..02d93763d42 100644 --- a/drivers/spi/designware_spi.c +++ b/drivers/spi/designware_spi.c @@ -369,7 +369,13 @@ static int poll_transfer(struct dw_spi_priv *priv) return 0; } -static void external_cs_manage(struct udevice *dev, bool on) +/* + * We define external_cs_manage function as 'weak' as some targets + * (like MSCC Ocelot) don't control the external CS pin using a GPIO + * controller. These SoCs use specific registers to control by + * software the SPI pins (and especially the CS). + */ +__weak void external_cs_manage(struct udevice *dev, bool on) { #if defined(CONFIG_DM_GPIO) && !defined(CONFIG_SPL_BUILD) struct dw_spi_priv *priv = dev_get_priv(dev->parent); diff --git a/drivers/spi/sun4i_spi.c b/drivers/spi/sun4i_spi.c index b86b5a00adb..38cc743c614 100644 --- a/drivers/spi/sun4i_spi.c +++ b/drivers/spi/sun4i_spi.c @@ -129,7 +129,8 @@ static inline void sun4i_spi_drain_fifo(struct sun4i_spi_priv *priv, int len) while (len--) { byte = readb(&priv->regs->rxdata); - *priv->rx_buf++ = byte; + if (priv->rx_buf) + *priv->rx_buf++ = byte; } } diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index b0e6f32f0bc..df37a798bdc 100644 --- a/drivers/timer/Kconfig +++ b/drivers/timer/Kconfig @@ -126,6 +126,13 @@ config OMAP_TIMER help Select this to enable an timer for Omap devices. +config RISCV_TIMER + bool "RISC-V timer support" + depends on TIMER && RISCV + help + Select this to enable support for the timer as defined + by the RISC-V privileged architecture spec. + config ROCKCHIP_TIMER bool "Rockchip timer support" depends on TIMER diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile index c4fbab2aaca..d0bf218b114 100644 --- a/drivers/timer/Makefile +++ b/drivers/timer/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_CADENCE_TTC_TIMER) += cadence-ttc.o obj-$(CONFIG_DESIGNWARE_APB_TIMER) += dw-apb-timer.o obj-$(CONFIG_MPC83XX_TIMER) += mpc83xx_timer.o obj-$(CONFIG_OMAP_TIMER) += omap-timer.o +obj-$(CONFIG_RISCV_TIMER) += riscv_timer.o obj-$(CONFIG_ROCKCHIP_TIMER) += rockchip_timer.o obj-$(CONFIG_SANDBOX_TIMER) += sandbox_timer.o obj-$(CONFIG_STI_TIMER) += sti-timer.o diff --git a/drivers/timer/riscv_timer.c b/drivers/timer/riscv_timer.c new file mode 100644 index 00000000000..9f9f070e0b3 --- /dev/null +++ b/drivers/timer/riscv_timer.c @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com> + * + * RISC-V privileged architecture defined generic timer driver + * + * This driver relies on RISC-V platform codes to provide the essential API + * riscv_get_time() which is supposed to return the timer counter as defined + * by the RISC-V privileged architecture spec. + * + * This driver can be used in both M-mode and S-mode U-Boot. + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <timer.h> +#include <asm/io.h> + +/** + * riscv_get_time() - get the timer counter + * + * Platform codes should provide this API in order to make this driver function. + * + * @time: the 64-bit timer count as defined by the RISC-V privileged + * architecture spec. + * @return: 0 on success, -ve on error. + */ +extern int riscv_get_time(u64 *time); + +static int riscv_timer_get_count(struct udevice *dev, u64 *count) +{ + return riscv_get_time(count); +} + +static int riscv_timer_probe(struct udevice *dev) +{ + struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); + + /* clock frequency was passed from the cpu driver as driver data */ + uc_priv->clock_rate = dev->driver_data; + + return 0; +} + +static const struct timer_ops riscv_timer_ops = { + .get_count = riscv_timer_get_count, +}; + +U_BOOT_DRIVER(riscv_timer) = { + .name = "riscv_timer", + .id = UCLASS_TIMER, + .probe = riscv_timer_probe, + .ops = &riscv_timer_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/video/fonts/Kconfig b/drivers/video/fonts/Kconfig index 3f1398db50c..c692fa9602f 100644 --- a/drivers/video/fonts/Kconfig +++ b/drivers/video/fonts/Kconfig @@ -7,6 +7,7 @@ menu "TrueType Fonts" config CONSOLE_TRUETYPE_NIMBUS bool "Nimbus Sans Regular" depends on CONSOLE_TRUETYPE + default y help Nimbus Sans L is a version of Nimbus Sans using Adobe font sources. It was designed in 1987. A subset of Nimbus Sans L were released diff --git a/drivers/w1/Kconfig b/drivers/w1/Kconfig index d6e045739d0..031bab25aea 100644 --- a/drivers/w1/Kconfig +++ b/drivers/w1/Kconfig @@ -20,6 +20,20 @@ config W1_GPIO help Emulate a 1-wire bus using a GPIO. +config W1_MXC + bool "Enable 1-wire controller on i.MX processors" + default no + depends on ARCH_MX25 || ARCH_MX31 || ARCH_MX5 + help + Support the one wire controller found in some members of the NXP + i.MX SoC family. + There are currently two silicon variants: + V1: i.MX21, i.MX27, i.MX31, i.MX51 + V2: i.MX25, i.MX35, i.MX50, i.MX53 + Newer i.MX SoCs such as the i.MX6 do not have one wire controllers. + + The driver supports both silicon variants. + endif endmenu diff --git a/drivers/w1/Makefile b/drivers/w1/Makefile index 7fd8697f841..9825187b65d 100644 --- a/drivers/w1/Makefile +++ b/drivers/w1/Makefile @@ -1,3 +1,4 @@ obj-$(CONFIG_W1) += w1-uclass.o obj-$(CONFIG_W1_GPIO) += w1-gpio.o +obj-$(CONFIG_W1_MXC) += mxc_w1.o diff --git a/drivers/w1/mxc_w1.c b/drivers/w1/mxc_w1.c new file mode 100644 index 00000000000..9279ba32b85 --- /dev/null +++ b/drivers/w1/mxc_w1.c @@ -0,0 +1,232 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Driver for one wire controller in some i.MX Socs + * + * There are currently two silicon variants: + * V1: i.MX21, i.MX27, i.MX31, i.MX51 + * V2: i.MX25, i.MX35, i.MX50, i.MX53 + * Newer i.MX SoCs such as the i.MX6 do not have one wire controllers. + * + * The V1 controller only supports single bit operations. + * The V2 controller is backwards compatible on the register level but adds + * byte size operations and a "search ROM accelerator mode" + * + * This driver does not currently support the search ROM accelerator + * + * Copyright (c) 2018 Flowbird + * Martin Fuzzey <martin.fuzzey@flowbird.group> + */ + +#include <asm/arch/clock.h> +#include <common.h> +#include <dm.h> +#include <linux/io.h> +#include <w1.h> + +struct mxc_w1_regs { + u16 control; +#define MXC_W1_CONTROL_RPP BIT(7) +#define MXC_W1_CONTROL_PST BIT(6) +#define MXC_W1_CONTROL_WR(x) BIT(5 - (x)) +#define MXC_W1_CONTROL_RDST BIT(3) + + u16 time_divider; + u16 reset; + + /* Registers below on V2 silicon only */ + u16 command; + u16 tx_rx; + u16 interrupt; +#define MXC_W1_INTERRUPT_TBE BIT(2) +#define MXC_W1_INTERRUPT_TSRE BIT(3) +#define MXC_W1_INTERRUPT_RBF BIT(4) +#define MXC_W1_INTERRUPT_RSRF BIT(5) + + u16 interrupt_en; +}; + +struct mxc_w1_pdata { + struct mxc_w1_regs *regs; +}; + +/* + * this is the low level routine to read/write a bit on the One Wire + * interface on the hardware. It does write 0 if parameter bit is set + * to 0, otherwise a write 1/read. + */ +static u8 mxc_w1_touch_bit(struct mxc_w1_pdata *pdata, u8 bit) +{ + u16 *ctrl_addr = &pdata->regs->control; + u16 mask = MXC_W1_CONTROL_WR(bit); + unsigned int timeout_cnt = 400; /* Takes max. 120us according to + * datasheet. + */ + + writew(mask, ctrl_addr); + + while (timeout_cnt--) { + if (!(readw(ctrl_addr) & mask)) + break; + + udelay(1); + } + + return (readw(ctrl_addr) & MXC_W1_CONTROL_RDST) ? 1 : 0; +} + +static u8 mxc_w1_read_byte(struct udevice *dev) +{ + struct mxc_w1_pdata *pdata = dev_get_platdata(dev); + struct mxc_w1_regs *regs = pdata->regs; + u16 status; + + if (dev_get_driver_data(dev) < 2) { + int i; + u8 ret = 0; + + for (i = 0; i < 8; i++) + ret |= (mxc_w1_touch_bit(pdata, 1) << i); + + return ret; + } + + readw(®s->tx_rx); + writew(0xFF, ®s->tx_rx); + + do { + udelay(1); /* Without this bytes are sometimes duplicated... */ + status = readw(®s->interrupt); + } while (!(status & MXC_W1_INTERRUPT_RBF)); + + return (u8)readw(®s->tx_rx); +} + +static void mxc_w1_write_byte(struct udevice *dev, u8 byte) +{ + struct mxc_w1_pdata *pdata = dev_get_platdata(dev); + struct mxc_w1_regs *regs = pdata->regs; + u16 status; + + if (dev_get_driver_data(dev) < 2) { + int i; + + for (i = 0; i < 8; i++) + mxc_w1_touch_bit(pdata, (byte >> i) & 0x1); + + return; + } + + readw(®s->tx_rx); + writew(byte, ®s->tx_rx); + + do { + udelay(1); + status = readw(®s->interrupt); + } while (!(status & MXC_W1_INTERRUPT_TSRE)); +} + +static bool mxc_w1_reset(struct udevice *dev) +{ + struct mxc_w1_pdata *pdata = dev_get_platdata(dev); + u16 reg_val; + + writew(MXC_W1_CONTROL_RPP, &pdata->regs->control); + + do { + reg_val = readw(&pdata->regs->control); + } while (reg_val & MXC_W1_CONTROL_RPP); + + return !(reg_val & MXC_W1_CONTROL_PST); +} + +static u8 mxc_w1_triplet(struct udevice *dev, bool bdir) +{ + struct mxc_w1_pdata *pdata = dev_get_platdata(dev); + u8 id_bit = mxc_w1_touch_bit(pdata, 1); + u8 comp_bit = mxc_w1_touch_bit(pdata, 1); + u8 retval; + + if (id_bit && comp_bit) + return 0x03; /* error */ + + if (!id_bit && !comp_bit) { + /* Both bits are valid, take the direction given */ + retval = bdir ? 0x04 : 0; + } else { + /* Only one bit is valid, take that direction */ + bdir = id_bit; + retval = id_bit ? 0x05 : 0x02; + } + + mxc_w1_touch_bit(pdata, bdir); + + return retval; +} + +static int mxc_w1_ofdata_to_platdata(struct udevice *dev) +{ + struct mxc_w1_pdata *pdata = dev_get_platdata(dev); + fdt_addr_t addr; + + addr = devfdt_get_addr(dev); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + pdata->regs = (struct mxc_w1_regs *)addr; + + return 0; +}; + +static int mxc_w1_probe(struct udevice *dev) +{ + struct mxc_w1_pdata *pdata = dev_get_platdata(dev); + unsigned int clkrate = mxc_get_clock(MXC_IPG_PERCLK); + unsigned int clkdiv; + + if (clkrate < 10000000) { + dev_err(dev, "input clock frequency (%u Hz) too low\n", + clkrate); + return -EINVAL; + } + + clkdiv = clkrate / 1000000; + clkrate /= clkdiv; + if (clkrate < 980000 || clkrate > 1020000) { + dev_err(dev, "Incorrect time base frequency %u Hz\n", clkrate); + return -EINVAL; + } + + writew(clkdiv - 1, &pdata->regs->time_divider); + + return 0; +} + +static const struct w1_ops mxc_w1_ops = { + .read_byte = mxc_w1_read_byte, + .reset = mxc_w1_reset, + .triplet = mxc_w1_triplet, + .write_byte = mxc_w1_write_byte, +}; + +static const struct udevice_id mxc_w1_id[] = { + { .compatible = "fsl,imx21-owire", .data = 1 }, + { .compatible = "fsl,imx27-owire", .data = 1 }, + { .compatible = "fsl,imx31-owire", .data = 1 }, + { .compatible = "fsl,imx51-owire", .data = 1 }, + + { .compatible = "fsl,imx25-owire", .data = 2 }, + { .compatible = "fsl,imx35-owire", .data = 2 }, + { .compatible = "fsl,imx50-owire", .data = 2 }, + { .compatible = "fsl,imx53-owire", .data = 2 }, + { }, +}; + +U_BOOT_DRIVER(mxc_w1_drv) = { + .id = UCLASS_W1, + .name = "mxc_w1_drv", + .of_match = mxc_w1_id, + .ofdata_to_platdata = mxc_w1_ofdata_to_platdata, + .ops = &mxc_w1_ops, + .platdata_auto_alloc_size = sizeof(struct mxc_w1_pdata), + .probe = mxc_w1_probe, +}; diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index b6974ad619a..10fd3039aa2 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -11,6 +11,12 @@ config WATCHDOG config HW_WATCHDOG bool +config WATCHDOG_RESET_DISABLE + bool "Disable reset watchdog" + help + Disable reset watchdog, which can let WATCHDOG_RESET invalid, so + that the watchdog will not be fed in u-boot. + config BCM2835_WDT bool "Enable BCM2835/2836 watchdog driver" select HW_WATCHDOG diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 74738eeaf7a..d901240ad1b 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -7,6 +7,8 @@ obj-$(CONFIG_WDT_AT91) += at91sam9_wdt.o obj-$(CONFIG_FTWDT010_WATCHDOG) += ftwdt010_wdt.o ifneq (,$(filter $(SOC), mx25 mx31 mx35 mx5 mx6 mx7 vf610)) obj-y += imx_watchdog.o +else +obj-$(CONFIG_IMX_WATCHDOG) += imx_watchdog.o endif obj-$(CONFIG_S5P) += s5p_wdt.o obj-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o diff --git a/drivers/watchdog/imx_watchdog.c b/drivers/watchdog/imx_watchdog.c index 3f826d10eb9..14cc618074b 100644 --- a/drivers/watchdog/imx_watchdog.c +++ b/drivers/watchdog/imx_watchdog.c @@ -8,15 +8,20 @@ #include <asm/io.h> #include <watchdog.h> #include <asm/arch/imx-regs.h> +#ifdef CONFIG_FSL_LSCH2 +#include <asm/arch/immap_lsch2.h> +#endif #include <fsl_wdog.h> #ifdef CONFIG_IMX_WATCHDOG void hw_watchdog_reset(void) { +#ifndef CONFIG_WATCHDOG_RESET_DISABLE struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR; writew(0x5555, &wdog->wsr); writew(0xaaaa, &wdog->wsr); +#endif /* CONFIG_WATCHDOG_RESET_DISABLE*/ } void hw_watchdog_init(void) @@ -33,8 +38,12 @@ void hw_watchdog_init(void) #define CONFIG_WATCHDOG_TIMEOUT_MSECS 128000 #endif timeout = (CONFIG_WATCHDOG_TIMEOUT_MSECS / 500) - 1; +#ifdef CONFIG_FSL_LSCH2 + writew((WCR_WDA | WCR_SRS | WCR_WDE) << 8 | timeout, &wdog->wcr); +#else writew(WCR_WDZST | WCR_WDBG | WCR_WDE | WCR_WDT | WCR_SRS | WCR_WDA | SET_WCR_WT(timeout), &wdog->wcr); +#endif /* CONFIG_FSL_LSCH2*/ hw_watchdog_reset(); } #endif |