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-rw-r--r--drivers/clk/imx/clk-imx8mp.c2
-rw-r--r--drivers/gpio/tegra_gpio.c50
-rw-r--r--drivers/misc/imx_ele/ele_api.c79
-rw-r--r--drivers/misc/imx_ele/ele_mu.c36
-rw-r--r--drivers/misc/imx_ele/fuse.c111
-rw-r--r--drivers/pinctrl/tegra/funcmux-tegra30.c16
-rw-r--r--drivers/usb/host/ehci-tegra.c136
-rw-r--r--drivers/video/Kconfig9
-rw-r--r--drivers/video/Makefile1
-rw-r--r--drivers/video/sharp-lq101r1sx01.c282
-rw-r--r--drivers/video/tegra20/tegra-dc.c2
-rw-r--r--drivers/video/tegra20/tegra-dsi.c95
-rw-r--r--drivers/video/tegra20/tegra-dsi.h15
13 files changed, 758 insertions, 76 deletions
diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
index 34d91cd6880..1d04090ca00 100644
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
@@ -197,6 +197,8 @@ static int imx8mp_clk_probe(struct udevice *dev)
base = (void *)ANATOP_BASE_ADDR;
+ clk_dm(IMX8MP_CLK_DUMMY, clk_register_fixed_rate(NULL, "dummy", 0));
+
clk_dm(IMX8MP_DRAM_PLL_REF_SEL, imx_clk_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
clk_dm(IMX8MP_ARM_PLL_REF_SEL, imx_clk_mux("arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
clk_dm(IMX8MP_SYS_PLL1_REF_SEL, imx_clk_mux("sys_pll1_ref_sel", base + 0x94, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
diff --git a/drivers/gpio/tegra_gpio.c b/drivers/gpio/tegra_gpio.c
index 6cafffaad92..b83df351e74 100644
--- a/drivers/gpio/tegra_gpio.c
+++ b/drivers/gpio/tegra_gpio.c
@@ -257,6 +257,56 @@ static const struct dm_gpio_ops gpio_tegra_ops = {
.xlate = tegra_gpio_xlate,
};
+/*
+ * SPL GPIO functions.
+ */
+int spl_gpio_output(void *regs, uint gpio, int value)
+{
+ /* Configure GPIO output value. */
+ set_level(gpio, value);
+
+ /* Configure GPIO direction as output. */
+ set_direction(gpio, DIRECTION_OUTPUT);
+
+ /* Enable the pin as a GPIO */
+ set_config(gpio, 1);
+
+ return 0;
+}
+
+int spl_gpio_input(void *regs, uint gpio)
+{
+ /* Configure GPIO direction as input. */
+ set_direction(gpio, DIRECTION_INPUT);
+
+ /* Enable the pin as a GPIO */
+ set_config(gpio, 1);
+
+ return 0;
+}
+
+int spl_gpio_get_value(void *regs, uint gpio)
+{
+ struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
+ struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
+ int val;
+
+ if (get_direction(gpio) == DIRECTION_INPUT)
+ val = readl(&bank->gpio_in[GPIO_PORT(gpio)]);
+ else
+ val = readl(&bank->gpio_out[GPIO_PORT(gpio)]);
+
+ return (val >> GPIO_BIT(gpio)) & 1;
+}
+
+int spl_gpio_set_value(void *regs, uint gpio, int value)
+{
+ /* Configure GPIO output value. */
+ set_level(gpio, value);
+
+ return 0;
+}
+
/**
* Returns the name of a GPIO port
*
diff --git a/drivers/misc/imx_ele/ele_api.c b/drivers/misc/imx_ele/ele_api.c
index b753419f01b..661f70cf870 100644
--- a/drivers/misc/imx_ele/ele_api.c
+++ b/drivers/misc/imx_ele/ele_api.c
@@ -5,12 +5,12 @@
*
*/
-#include <hang.h>
-#include <malloc.h>
-#include <memalign.h>
#include <asm/io.h>
-#include <dm.h>
+#include <asm/mach-imx/sys_proto.h>
#include <asm/mach-imx/ele_api.h>
+#include <dm.h>
+#include <malloc.h>
+#include <memalign.h>
#include <misc.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -205,8 +205,7 @@ int ele_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32 fuse_num, u32 *respon
return -EINVAL;
}
- if ((fuse_id != 1 && fuse_num != 1) ||
- (fuse_id == 1 && fuse_num != 4)) {
+ if (is_imx8ulp() && ((fuse_id != 1 && fuse_num != 1) || (fuse_id == 1 && fuse_num != 4))) {
printf("Invalid fuse number parameter\n");
return -EINVAL;
}
@@ -226,7 +225,7 @@ int ele_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32 fuse_num, u32 *respon
*response = msg.data[0];
fuse_words[0] = msg.data[1];
- if (fuse_id == 1) {
+ if (fuse_id == 1 && is_imx8ulp()) {
/* OTP_UNIQ_ID */
fuse_words[1] = msg.data[2];
fuse_words[2] = msg.data[3];
@@ -269,6 +268,72 @@ int ele_write_fuse(u16 fuse_id, u32 fuse_val, bool lock, u32 *response)
return ret;
}
+int ele_write_shadow_fuse(u32 fuse_id, u32 fuse_val, u32 *response)
+{
+ struct udevice *dev = gd->arch.ele_dev;
+ int size = sizeof(struct ele_msg);
+ struct ele_msg msg;
+ int ret;
+
+ if (!dev) {
+ printf("ele dev is not initialized\n");
+ return -ENODEV;
+ }
+
+ msg.version = ELE_VERSION;
+ msg.tag = ELE_CMD_TAG;
+ msg.size = 3;
+ msg.command = ELE_WRITE_SHADOW_REQ;
+ msg.data[0] = fuse_id;
+ msg.data[1] = fuse_val;
+
+ ret = misc_call(dev, false, &msg, size, &msg, size);
+ if (ret)
+ printf("Error: %s: ret %d, fuse_id 0x%x, response 0x%x\n",
+ __func__, ret, fuse_id, msg.data[0]);
+
+ if (response)
+ *response = msg.data[0];
+
+ return ret;
+}
+
+int ele_read_shadow_fuse(u32 fuse_id, u32 *fuse_val, u32 *response)
+{
+ struct udevice *dev = gd->arch.ele_dev;
+ int size = sizeof(struct ele_msg);
+ struct ele_msg msg = {};
+ int ret;
+
+ if (!dev) {
+ printf("ele dev is not initialized\n");
+ return -ENODEV;
+ }
+
+ if (!fuse_val) {
+ printf("Invalid parameters for shadow read\n");
+ return -EINVAL;
+ }
+
+ msg.version = ELE_VERSION;
+ msg.tag = ELE_CMD_TAG;
+ msg.size = 2;
+ msg.command = ELE_READ_SHADOW_REQ;
+ msg.data[0] = fuse_id;
+
+ ret = misc_call(dev, false, &msg, size, &msg, size);
+ if (ret)
+ printf("Error: %s: ret %d, fuse_id 0x%x, response 0x%x\n",
+ __func__, ret, fuse_id, msg.data[0]);
+
+ if (response)
+ *response = msg.data[0];
+
+ *fuse_val = msg.data[1];
+
+ return ret;
+}
+
int ele_release_caam(u32 core_did, u32 *response)
{
struct udevice *dev = gd->arch.ele_dev;
diff --git a/drivers/misc/imx_ele/ele_mu.c b/drivers/misc/imx_ele/ele_mu.c
index 0cf81f33ba5..cdb85b999db 100644
--- a/drivers/misc/imx_ele/ele_mu.c
+++ b/drivers/misc/imx_ele/ele_mu.c
@@ -21,25 +21,35 @@ struct imx8ulp_mu {
#define MU_SR_TE0_MASK BIT(0)
#define MU_SR_RF0_MASK BIT(0)
-#define MU_TR_COUNT 8
-#define MU_RR_COUNT 4
void mu_hal_init(ulong base)
{
struct mu_type *mu_base = (struct mu_type *)base;
+ u32 rr_num = (readl(&mu_base->par) & 0xFF00) >> 8;
+ int i;
writel(0, &mu_base->tcr);
writel(0, &mu_base->rcr);
+
+ while (true) {
+ /* If there is pending RX data, clear them by read them out */
+ if (!(readl(&mu_base->sr) & BIT(6)))
+ return;
+
+ for (i = 0; i < rr_num; i++)
+ readl(&mu_base->rr[i]);
+ }
}
int mu_hal_sendmsg(ulong base, u32 reg_index, u32 msg)
{
struct mu_type *mu_base = (struct mu_type *)base;
u32 mask = MU_SR_TE0_MASK << reg_index;
- u32 val;
+ u32 val, tr_num;
int ret;
- assert(reg_index < MU_TR_COUNT);
+ tr_num = readl(&mu_base->par) & 0xFF;
+ assert(reg_index < tr_num);
debug("sendmsg tsr 0x%x\n", readl(&mu_base->tsr));
@@ -61,11 +71,12 @@ int mu_hal_receivemsg(ulong base, u32 reg_index, u32 *msg)
{
struct mu_type *mu_base = (struct mu_type *)base;
u32 mask = MU_SR_RF0_MASK << reg_index;
- u32 val;
+ u32 val, rr_num;
int ret;
u32 count = 10;
- assert(reg_index < MU_RR_COUNT);
+ rr_num = (readl(&mu_base->par) & 0xFF00) >> 8;
+ assert(reg_index < rr_num);
debug("receivemsg rsr 0x%x\n", readl(&mu_base->rsr));
@@ -96,7 +107,7 @@ static int imx8ulp_mu_read(struct mu_type *base, void *data)
{
struct ele_msg *msg = (struct ele_msg *)data;
int ret;
- u8 count = 0;
+ u8 count = 0, rr_num;
if (!msg)
return -EINVAL;
@@ -113,9 +124,11 @@ static int imx8ulp_mu_read(struct mu_type *base, void *data)
return -EINVAL;
}
+ rr_num = (readl(&base->par) & 0xFF00) >> 8;
+
/* Read remaining words */
while (count < msg->size) {
- ret = mu_hal_receivemsg((ulong)base, count % MU_RR_COUNT,
+ ret = mu_hal_receivemsg((ulong)base, count % rr_num,
&msg->data[count - 1]);
if (ret)
return ret;
@@ -129,7 +142,7 @@ static int imx8ulp_mu_write(struct mu_type *base, void *data)
{
struct ele_msg *msg = (struct ele_msg *)data;
int ret;
- u8 count = 0;
+ u8 count = 0, tr_num;
if (!msg)
return -EINVAL;
@@ -144,9 +157,11 @@ static int imx8ulp_mu_write(struct mu_type *base, void *data)
return ret;
count++;
+ tr_num = readl(&base->par) & 0xFF;
+
/* Write remaining words */
while (count < msg->size) {
- ret = mu_hal_sendmsg((ulong)base, count % MU_TR_COUNT,
+ ret = mu_hal_sendmsg((ulong)base, count % tr_num,
msg->data[count - 1]);
if (ret)
return ret;
@@ -229,6 +244,7 @@ static struct misc_ops imx8ulp_mu_ops = {
static const struct udevice_id imx8ulp_mu_ids[] = {
{ .compatible = "fsl,imx8ulp-mu" },
{ .compatible = "fsl,imx93-mu-s4" },
+ { .compatible = "fsl,imx95-mu-ele" },
{ }
};
diff --git a/drivers/misc/imx_ele/fuse.c b/drivers/misc/imx_ele/fuse.c
index d12539c8aac..c1e7434dbf3 100644
--- a/drivers/misc/imx_ele/fuse.c
+++ b/drivers/misc/imx_ele/fuse.c
@@ -11,10 +11,10 @@
#include <env.h>
#include <asm/mach-imx/ele_api.h>
#include <asm/global_data.h>
+#include <env.h>
DECLARE_GLOBAL_DATA_PTR;
-#define FUSE_BANKS 64
#define WORDS_PER_BANKS 8
struct fsb_map_entry {
@@ -32,6 +32,7 @@ struct ele_map_entry {
#if defined(CONFIG_IMX8ULP)
#define FSB_OTP_SHADOW 0x800
+#define IS_FSB_ALLOWED (true)
struct fsb_map_entry fsb_mapping_table[] = {
{ 3, 8 },
@@ -84,6 +85,8 @@ struct ele_map_entry ele_api_mapping_table[] = {
};
#elif defined(CONFIG_ARCH_IMX9)
#define FSB_OTP_SHADOW 0x8000
+#define IS_FSB_ALLOWED (!IS_ENABLED(CONFIG_SCMI_FIRMWARE) && \
+ !(readl(BLK_CTRL_NS_ANOMIX_BASE_ADDR + 0x28) & BIT(0)))
struct fsb_map_entry fsb_mapping_table[] = {
{ 0, 8 },
@@ -138,8 +141,7 @@ static s32 map_fsb_fuse_index(u32 bank, u32 word, bool *redundancy)
/* map the fuse from ocotp fuse map to FSB*/
for (i = 0; i < size; i++) {
if (fsb_mapping_table[i].fuse_bank != -1 &&
- fsb_mapping_table[i].fuse_bank == bank &&
- fsb_mapping_table[i].fuse_words > word) {
+ fsb_mapping_table[i].fuse_bank == bank) {
break;
}
@@ -150,8 +152,13 @@ static s32 map_fsb_fuse_index(u32 bank, u32 word, bool *redundancy)
return -1; /* Failed to find */
if (fsb_mapping_table[i].redundancy) {
+ if ((fsb_mapping_table[i].fuse_words << 1) <= word)
+ return -2; /* Not valid word */
+
*redundancy = true;
return (word >> 1) + word_pos;
+ } else if (fsb_mapping_table[i].fuse_words <= word) {
+ return -2; /* Not valid word */
}
*redundancy = false;
@@ -187,24 +194,14 @@ static s32 map_ele_fuse_index(u32 bank, u32 word)
int fuse_sense(u32 bank, u32 word, u32 *val)
{
s32 word_index;
- bool redundancy;
- if (bank >= FUSE_BANKS || word >= WORDS_PER_BANKS || !val)
+ if (word >= WORDS_PER_BANKS || !val)
return -EINVAL;
- word_index = map_fsb_fuse_index(bank, word, &redundancy);
- if (word_index >= 0) {
- *val = readl((ulong)FSB_BASE_ADDR + FSB_OTP_SHADOW + (word_index << 2));
- if (redundancy)
- *val = (*val >> ((word % 2) * 16)) & 0xFFFF;
-
- return 0;
- }
-
word_index = map_ele_fuse_index(bank, word);
if (word_index >= 0) {
u32 data[4];
- u32 res, size = 4;
+ u32 res = 0, size = 4;
int ret;
/* Only UID return 4 words */
@@ -236,28 +233,29 @@ int fuse_sense(u32 bank, u32 word, u32 *val)
return -ENOENT;
}
+
#elif defined(CONFIG_ARCH_IMX9)
int fuse_sense(u32 bank, u32 word, u32 *val)
{
s32 word_index;
bool redundancy;
- if (bank >= FUSE_BANKS || word >= WORDS_PER_BANKS || !val)
+ if (word >= WORDS_PER_BANKS || !val)
return -EINVAL;
- word_index = map_fsb_fuse_index(bank, word, &redundancy);
- if (word_index >= 0) {
- *val = readl((ulong)FSB_BASE_ADDR + FSB_OTP_SHADOW + (word_index << 2));
- if (redundancy)
- *val = (*val >> ((word % 2) * 16)) & 0xFFFF;
+ if (!IS_ENABLED(CONFIG_SCMI_FIRMWARE)) {
+ word_index = map_fsb_fuse_index(bank, word, &redundancy);
- return 0;
+ /* ELE read common fuse API supports all FSB fuse. */
+ if (word_index < 0)
+ word_index = map_ele_fuse_index(bank, word);
+ } else {
+ word_index = bank * 8 + word;
}
- word_index = map_ele_fuse_index(bank, word);
if (word_index >= 0) {
u32 data;
- u32 res, size = 1;
+ u32 res = 0, size = 1;
int ret;
ret = ele_read_common_fuse(word_index, &data, size, &res);
@@ -275,18 +273,62 @@ int fuse_sense(u32 bank, u32 word, u32 *val)
}
#endif
-int fuse_read(u32 bank, u32 word, u32 *val)
+static int fuse_read_default(u32 bank, u32 word, u32 *val)
{
+ s32 word_index;
+ bool redundancy;
+
+ if (IS_FSB_ALLOWED) {
+ word_index = map_fsb_fuse_index(bank, word, &redundancy);
+ if (word_index >= 0) {
+ *val = readl((ulong)FSB_BASE_ADDR + FSB_OTP_SHADOW + (word_index << 2));
+ if (redundancy)
+ *val = (*val >> ((word % 2) * 16)) & 0xFFFF;
+
+ return 0;
+ }
+ }
+
return fuse_sense(bank, word, val);
}
+static int fuse_read_ele_shd(u32 bank, u32 word, u32 *val)
+{
+ u32 res = 0;
+ int ret;
+ struct udevice *dev = gd->arch.ele_dev;
+
+ if (!dev)
+ return -ENODEV;
+
+ ret = ele_read_shadow_fuse((bank * 8 + word), val, &res);
+ if (ret) {
+ printf("ele read shadow fuse failed %d, 0x%x\n", ret, res);
+ return ret;
+ }
+
+ return 0;
+}
+
+int fuse_read(u32 bank, u32 word, u32 *val)
+{
+ if (word >= WORDS_PER_BANKS || !val)
+ return -EINVAL;
+
+ if (!IS_ENABLED(CONFIG_SPL_BUILD) &&
+ env_get_yesno("enable_ele_shd") == 1)
+ return fuse_read_ele_shd(bank, word, val);
+ else
+ return fuse_read_default(bank, word, val);
+}
+
int fuse_prog(u32 bank, u32 word, u32 val)
{
- u32 res;
+ u32 res = 0;
int ret;
bool lock = false;
- if (bank >= FUSE_BANKS || word >= WORDS_PER_BANKS || !val)
+ if (word >= WORDS_PER_BANKS || !val)
return -EINVAL;
/* Lock 8ULP ECC fuse word, so second programming will return failure.
@@ -314,6 +356,17 @@ int fuse_prog(u32 bank, u32 word, u32 val)
int fuse_override(u32 bank, u32 word, u32 val)
{
- printf("Override fuse to i.MX8ULP in u-boot is forbidden\n");
- return -EPERM;
+ u32 res = 0;
+ int ret;
+
+ if (word >= WORDS_PER_BANKS || !val)
+ return -EINVAL;
+
+ ret = ele_write_shadow_fuse((bank * 8 + word), val, &res);
+ if (ret) {
+ printf("ahab write shadow fuse failed %d, 0x%x\n", ret, res);
+ return ret;
+ }
+
+ return 0;
}
diff --git a/drivers/pinctrl/tegra/funcmux-tegra30.c b/drivers/pinctrl/tegra/funcmux-tegra30.c
index e31b859beb8..5d3403ae441 100644
--- a/drivers/pinctrl/tegra/funcmux-tegra30.c
+++ b/drivers/pinctrl/tegra/funcmux-tegra30.c
@@ -33,6 +33,22 @@ int funcmux_select(enum periph_id id, int config)
break;
}
break;
+ case PERIPH_ID_UART5:
+ switch (config) {
+ case FUNCMUX_UART5_SDMMC1:
+ pinmux_set_func(PMUX_PINGRP_SDMMC1_DAT3_PY4,
+ PMUX_FUNC_UARTE);
+ pinmux_set_func(PMUX_PINGRP_SDMMC1_DAT2_PY5,
+ PMUX_FUNC_UARTE);
+
+ pinmux_set_io(PMUX_PINGRP_SDMMC1_DAT3_PY4, PMUX_PIN_OUTPUT);
+ pinmux_set_io(PMUX_PINGRP_SDMMC1_DAT2_PY5, PMUX_PIN_INPUT);
+
+ pinmux_tristate_disable(PMUX_PINGRP_SDMMC1_DAT3_PY4);
+ pinmux_tristate_disable(PMUX_PINGRP_SDMMC1_DAT2_PY5);
+ break;
+ }
+ break;
/* Add other periph IDs here as needed */
diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c
index 343893b9f19..7c73eb66b60 100644
--- a/drivers/usb/host/ehci-tegra.c
+++ b/drivers/usb/host/ehci-tegra.c
@@ -66,9 +66,24 @@ enum usb_ctlr_type {
USB_CTRL_COUNT,
};
+struct tegra_utmip_config {
+ u32 hssync_start_delay;
+ u32 elastic_limit;
+ u32 idle_wait_delay;
+ u32 term_range_adj;
+ bool xcvr_setup_use_fuses;
+ u32 xcvr_setup;
+ u32 xcvr_lsfslew;
+ u32 xcvr_lsrslew;
+ u32 xcvr_hsslew;
+ u32 hssquelch_level;
+ u32 hsdiscon_level;
+};
+
/* Information about a USB port */
struct fdt_usb {
struct ehci_ctrl ehci;
+ struct tegra_utmip_config utmip_config;
struct usb_ctlr *reg; /* address of registers in physical memory */
unsigned utmi:1; /* 1 if port has external tranceiver, else 0 */
unsigned ulpi:1; /* 1 if port has external ULPI transceiver */
@@ -192,15 +207,6 @@ static const unsigned T210_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = {
{ 0x028, 0x01, 0x01, 0x0, 0, 0x02, 0x2F, 0x08, 0x76, 65000, 5 }
};
-/* UTMIP Idle Wait Delay */
-static const u8 utmip_idle_wait_delay = 17;
-
-/* UTMIP Elastic limit */
-static const u8 utmip_elastic_limit = 16;
-
-/* UTMIP High Speed Sync Start Delay */
-static const u8 utmip_hs_sync_start_delay = 9;
-
struct fdt_usb_controller {
/* flag to determine whether controller supports hostpc register */
u32 has_hostpc:1;
@@ -377,6 +383,7 @@ static int init_utmi_usb_controller(struct fdt_usb *config,
u32 b_sess_valid_mask, val;
int loop_count;
const unsigned *timing;
+ struct tegra_utmip_config *utmip_config = &config->utmip_config;
struct usb_ctlr *usbctlr = config->reg;
struct clk_rst_ctlr *clkrst;
struct usb_ctlr *usb1ctlr;
@@ -463,16 +470,29 @@ static int init_utmi_usb_controller(struct fdt_usb *config,
/* Recommended PHY settings for EYE diagram */
val = readl(&usbctlr->utmip_xcvr_cfg0);
- clrsetbits_le32(&val, UTMIP_XCVR_SETUP_MASK,
- 0x4 << UTMIP_XCVR_SETUP_SHIFT);
- clrsetbits_le32(&val, UTMIP_XCVR_SETUP_MSB_MASK,
- 0x3 << UTMIP_XCVR_SETUP_MSB_SHIFT);
- clrsetbits_le32(&val, UTMIP_XCVR_HSSLEW_MSB_MASK,
- 0x8 << UTMIP_XCVR_HSSLEW_MSB_SHIFT);
+
+ if (!utmip_config->xcvr_setup_use_fuses) {
+ clrsetbits_le32(&val, UTMIP_XCVR_SETUP(~0),
+ UTMIP_XCVR_SETUP(utmip_config->xcvr_setup));
+ clrsetbits_le32(&val, UTMIP_XCVR_SETUP_MSB(~0),
+ UTMIP_XCVR_SETUP_MSB(utmip_config->xcvr_setup));
+ }
+
+ clrsetbits_le32(&val, UTMIP_XCVR_LSFSLEW(~0),
+ UTMIP_XCVR_LSFSLEW(utmip_config->xcvr_lsfslew));
+ clrsetbits_le32(&val, UTMIP_XCVR_LSRSLEW(~0),
+ UTMIP_XCVR_LSRSLEW(utmip_config->xcvr_lsrslew));
+
+ clrsetbits_le32(&val, UTMIP_XCVR_HSSLEW(~0),
+ UTMIP_XCVR_HSSLEW(utmip_config->xcvr_hsslew));
+ clrsetbits_le32(&val, UTMIP_XCVR_HSSLEW_MSB(~0),
+ UTMIP_XCVR_HSSLEW_MSB(utmip_config->xcvr_hsslew));
writel(val, &usbctlr->utmip_xcvr_cfg0);
+
clrsetbits_le32(&usbctlr->utmip_xcvr_cfg1,
UTMIP_XCVR_TERM_RANGE_ADJ_MASK,
- 0x7 << UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT);
+ utmip_config->term_range_adj <<
+ UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT);
/* Some registers can be controlled from USB1 only. */
if (config->periph_id != PERIPH_ID_USBD) {
@@ -485,9 +505,11 @@ static int init_utmi_usb_controller(struct fdt_usb *config,
val = readl(&usb1ctlr->utmip_bias_cfg0);
setbits_le32(&val, UTMIP_HSDISCON_LEVEL_MSB);
clrsetbits_le32(&val, UTMIP_HSDISCON_LEVEL_MASK,
- 0x1 << UTMIP_HSDISCON_LEVEL_SHIFT);
+ utmip_config->hsdiscon_level <<
+ UTMIP_HSDISCON_LEVEL_SHIFT);
clrsetbits_le32(&val, UTMIP_HSSQUELCH_LEVEL_MASK,
- 0x2 << UTMIP_HSSQUELCH_LEVEL_SHIFT);
+ utmip_config->hssquelch_level <<
+ UTMIP_HSSQUELCH_LEVEL_SHIFT);
writel(val, &usb1ctlr->utmip_bias_cfg0);
/* Miscellaneous setting mentioned in Programming Guide */
@@ -521,7 +543,11 @@ static int init_utmi_usb_controller(struct fdt_usb *config,
setbits_le32(&usbctlr->utmip_bat_chrg_cfg0, UTMIP_PD_CHRG);
clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_XCVR_LSBIAS_SE);
- setbits_le32(&usbctlr->utmip_spare_cfg0, FUSE_SETUP_SEL);
+
+ if (utmip_config->xcvr_setup_use_fuses)
+ setbits_le32(&usbctlr->utmip_spare_cfg0, FUSE_SETUP_SEL);
+ else
+ clrbits_le32(&usbctlr->utmip_spare_cfg0, FUSE_SETUP_SEL);
/*
* Configure the UTMIP_IDLE_WAIT and UTMIP_ELASTIC_LIMIT
@@ -535,15 +561,16 @@ static int init_utmi_usb_controller(struct fdt_usb *config,
/* Set PLL enable delay count and Crystal frequency count */
val = readl(&usbctlr->utmip_hsrx_cfg0);
clrsetbits_le32(&val, UTMIP_IDLE_WAIT_MASK,
- utmip_idle_wait_delay << UTMIP_IDLE_WAIT_SHIFT);
+ utmip_config->idle_wait_delay << UTMIP_IDLE_WAIT_SHIFT);
clrsetbits_le32(&val, UTMIP_ELASTIC_LIMIT_MASK,
- utmip_elastic_limit << UTMIP_ELASTIC_LIMIT_SHIFT);
+ utmip_config->elastic_limit << UTMIP_ELASTIC_LIMIT_SHIFT);
writel(val, &usbctlr->utmip_hsrx_cfg0);
/* Configure the UTMIP_HS_SYNC_START_DLY */
clrsetbits_le32(&usbctlr->utmip_hsrx_cfg1,
UTMIP_HS_SYNC_START_DLY_MASK,
- utmip_hs_sync_start_delay << UTMIP_HS_SYNC_START_DLY_SHIFT);
+ utmip_config->hssync_start_delay <<
+ UTMIP_HS_SYNC_START_DLY_SHIFT);
/* Preceed the crystal clock disable by >100ns delay. */
udelay(1);
@@ -763,6 +790,69 @@ static int fdt_decode_usb(struct udevice *dev, struct fdt_usb *config)
return 0;
}
+static void fdt_decode_usb_phy(struct udevice *dev)
+{
+ struct fdt_usb *priv = dev_get_priv(dev);
+ struct tegra_utmip_config *utmip_config = &priv->utmip_config;
+ u32 usb_phy_phandle;
+ ofnode usb_phy_node;
+ int ret;
+
+ ret = ofnode_read_u32(dev_ofnode(dev), "nvidia,phy", &usb_phy_phandle);
+ if (ret)
+ log_debug("%s: required usb phy node isn't provided\n", __func__);
+
+ usb_phy_node = ofnode_get_by_phandle(usb_phy_phandle);
+ if (!ofnode_valid(usb_phy_node) || !ofnode_is_enabled(usb_phy_node)) {
+ log_debug("%s: failed to find usb phy node or it is disabled\n", __func__);
+ utmip_config->xcvr_setup_use_fuses = true;
+ } else {
+ utmip_config->xcvr_setup_use_fuses =
+ ofnode_read_bool(usb_phy_node, "nvidia,xcvr-setup-use-fuses");
+ }
+
+ utmip_config->hssync_start_delay =
+ ofnode_read_u32_default(usb_phy_node,
+ "nvidia,hssync-start-delay", 0x9);
+
+ utmip_config->elastic_limit =
+ ofnode_read_u32_default(usb_phy_node,
+ "nvidia,elastic-limit", 0x10);
+
+ utmip_config->idle_wait_delay =
+ ofnode_read_u32_default(usb_phy_node,
+ "nvidia,idle-wait-delay", 0x11);
+
+ utmip_config->term_range_adj =
+ ofnode_read_u32_default(usb_phy_node,
+ "nvidia,term-range-adj", 0x7);
+
+ utmip_config->xcvr_lsfslew =
+ ofnode_read_u32_default(usb_phy_node,
+ "nvidia,xcvr-lsfslew", 0x0);
+
+ utmip_config->xcvr_lsrslew =
+ ofnode_read_u32_default(usb_phy_node,
+ "nvidia,xcvr-lsrslew", 0x3);
+
+ utmip_config->xcvr_hsslew =
+ ofnode_read_u32_default(usb_phy_node,
+ "nvidia,xcvr-hsslew", 0x8);
+
+ utmip_config->hssquelch_level =
+ ofnode_read_u32_default(usb_phy_node,
+ "nvidia,hssquelch-level", 0x2);
+
+ utmip_config->hsdiscon_level =
+ ofnode_read_u32_default(usb_phy_node,
+ "nvidia,hsdiscon-level", 0x1);
+
+ if (!utmip_config->xcvr_setup_use_fuses) {
+ ofnode_read_u32(usb_phy_node, "nvidia,xcvr-setup",
+ &utmip_config->xcvr_setup);
+ }
+}
+
int usb_common_init(struct fdt_usb *config, enum usb_init_type init)
{
int ret = 0;
@@ -850,6 +940,8 @@ static int ehci_usb_of_to_plat(struct udevice *dev)
priv->type = dev_get_driver_data(dev);
+ fdt_decode_usb_phy(dev);
+
return 0;
}
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 6e79694fd19..3c3cebaacd0 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -599,6 +599,15 @@ config VIDEO_LCD_SAMSUNG_LTL106HL02
LCD module found in Microsoft Surface 2. The panel has a FullHD
resolution (1920x1080).
+config VIDEO_LCD_SHARP_LQ101R1SX01
+ tristate "Sharp LQ101R1SX01 2560x1600 DSI video mode panel"
+ depends on PANEL && BACKLIGHT
+ select VIDEO_MIPI_DSI
+ help
+ Say Y here if you want to enable support for Sharp LQ101R1SX01
+ LCD module found in ASUS Transformer TF701T. The panel has a
+ WQXGA resolution (2560x1600).
+
config VIDEO_LCD_SSD2828
bool "SSD2828 bridge chip"
---help---
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index af8b2b266e2..5a00438ce06 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -64,6 +64,7 @@ obj-$(CONFIG_VIDEO_LCD_RAYDIUM_RM68200) += raydium-rm68200.o
obj-$(CONFIG_VIDEO_LCD_RENESAS_R61307) += renesas-r61307.o
obj-$(CONFIG_VIDEO_LCD_RENESAS_R69328) += renesas-r69328.o
obj-$(CONFIG_VIDEO_LCD_SAMSUNG_LTL106HL02) += samsung-ltl106hl02.o
+obj-$(CONFIG_VIDEO_LCD_SHARP_LQ101R1SX01) += sharp-lq101r1sx01.o
obj-$(CONFIG_VIDEO_LCD_SSD2828) += ssd2828.o
obj-$(CONFIG_VIDEO_LCD_TDO_TL070WSH30) += tdo-tl070wsh30.o
obj-$(CONFIG_VIDEO_MCDE_SIMPLE) += mcde_simple.o
diff --git a/drivers/video/sharp-lq101r1sx01.c b/drivers/video/sharp-lq101r1sx01.c
new file mode 100644
index 00000000000..5d8453fd796
--- /dev/null
+++ b/drivers/video/sharp-lq101r1sx01.c
@@ -0,0 +1,282 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Sharp LQ101R1SX01 DSI panel driver
+ *
+ * Copyright (C) 2014 NVIDIA Corporation
+ * Copyright (c) 2023 Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <backlight.h>
+#include <dm.h>
+#include <panel.h>
+#include <log.h>
+#include <mipi_dsi.h>
+#include <linux/delay.h>
+#include <power/regulator.h>
+
+struct sharp_lq101r1sx01_priv {
+ struct udevice *backlight;
+ struct udevice *panel_sec;
+ struct udevice *vcc;
+};
+
+static struct display_timing default_timing = {
+ .pixelclock.typ = 278000000,
+ .hactive.typ = 2560,
+ .hfront_porch.typ = 128,
+ .hback_porch.typ = 64,
+ .hsync_len.typ = 64,
+ .vactive.typ = 1600,
+ .vfront_porch.typ = 4,
+ .vback_porch.typ = 8,
+ .vsync_len.typ = 32,
+};
+
+static int sharp_lq101r1sx01_write(struct mipi_dsi_device *dsi,
+ u16 offset, u8 value)
+{
+ u8 payload[3] = { offset >> 8, offset & 0xff, value };
+ int ret;
+
+ ret = mipi_dsi_generic_write(dsi, payload, sizeof(payload));
+ if (ret < 0) {
+ log_debug("%s: failed to write %02x to %04x: %zd\n",
+ __func__, value, offset, ret);
+ return ret;
+ }
+
+ ret = mipi_dsi_dcs_nop(dsi);
+ if (ret < 0) {
+ log_debug("%s: failed to send DCS nop: %zd\n",
+ __func__, ret);
+ return ret;
+ }
+
+ udelay(20);
+
+ return 0;
+}
+
+static int sharp_setup_symmetrical_split(struct mipi_dsi_device *left,
+ struct mipi_dsi_device *right,
+ struct display_timing *timing)
+{
+ int ret;
+
+ ret = mipi_dsi_dcs_set_column_address(left, 0,
+ timing->hactive.typ / 2 - 1);
+ if (ret < 0) {
+ log_debug("%s: failed to set column address: %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ ret = mipi_dsi_dcs_set_page_address(left, 0, timing->vactive.typ - 1);
+ if (ret < 0) {
+ log_debug("%s: failed to set page address: %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ ret = mipi_dsi_dcs_set_column_address(right, timing->hactive.typ / 2,
+ timing->hactive.typ - 1);
+ if (ret < 0) {
+ log_debug("%s: failed to set column address: %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ ret = mipi_dsi_dcs_set_page_address(right, 0, timing->vactive.typ - 1);
+ if (ret < 0) {
+ log_debug("%s: failed to set page address: %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int sharp_lq101r1sx01_enable_backlight(struct udevice *dev)
+{
+ struct sharp_lq101r1sx01_priv *priv = dev_get_priv(dev);
+
+ if (!priv->panel_sec)
+ return 0;
+
+ struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
+ struct mipi_dsi_panel_plat *plat_sec = dev_get_plat(priv->panel_sec);
+ struct mipi_dsi_device *link1 = plat->device;
+ struct mipi_dsi_device *link2 = plat_sec->device;
+ int ret;
+
+ ret = mipi_dsi_dcs_exit_sleep_mode(link1);
+ if (ret < 0) {
+ log_debug("%s: failed to exit sleep mode: %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ /* set left-right mode */
+ ret = sharp_lq101r1sx01_write(link1, 0x1000, 0x2a);
+ if (ret < 0) {
+ log_debug("%s: failed to set left-right mode: %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ /* enable command mode */
+ ret = sharp_lq101r1sx01_write(link1, 0x1001, 0x01);
+ if (ret < 0) {
+ log_debug("%s: failed to enable command mode: %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ ret = mipi_dsi_dcs_set_pixel_format(link1, MIPI_DCS_PIXEL_FMT_24BIT);
+ if (ret < 0) {
+ log_debug("%s: failed to set pixel format: %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ /*
+ * TODO: The device supports both left-right and even-odd split
+ * configurations, but this driver currently supports only the left-
+ * right split. To support a different mode a mechanism needs to be
+ * put in place to communicate the configuration back to the DSI host
+ * controller.
+ */
+ ret = sharp_setup_symmetrical_split(link1, link2, &default_timing);
+ if (ret < 0) {
+ log_debug("%s: failed to set up symmetrical split: %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ ret = mipi_dsi_dcs_set_display_on(link1);
+ if (ret < 0) {
+ log_debug("%s: failed to set panel on: %d\n",
+ __func__, ret);
+ return ret;
+ }
+ mdelay(20);
+
+ return 0;
+}
+
+static int sharp_lq101r1sx01_set_backlight(struct udevice *dev, int percent)
+{
+ struct sharp_lq101r1sx01_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ if (!priv->panel_sec)
+ return 0;
+
+ ret = backlight_enable(priv->backlight);
+ if (ret)
+ return ret;
+
+ return backlight_set_brightness(priv->backlight, percent);
+}
+
+static int sharp_lq101r1sx01_timings(struct udevice *dev,
+ struct display_timing *timing)
+{
+ memcpy(timing, &default_timing, sizeof(*timing));
+ return 0;
+}
+
+static int sharp_lq101r1sx01_of_to_plat(struct udevice *dev)
+{
+ struct sharp_lq101r1sx01_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ /* If node has no link2 it is secondary panel */
+ if (!dev_read_bool(dev, "link2"))
+ return 0;
+
+ ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev,
+ "link2", &priv->panel_sec);
+ if (ret) {
+ log_debug("%s: cannot get secondary panel: ret = %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ ret = uclass_get_device_by_phandle(UCLASS_PANEL_BACKLIGHT, dev,
+ "backlight", &priv->backlight);
+ if (ret) {
+ log_debug("%s: cannot get backlight: ret = %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ ret = uclass_get_device_by_phandle(UCLASS_REGULATOR, dev,
+ "power-supply", &priv->vcc);
+ if (ret) {
+ log_debug("%s: cannot get power-supply: ret = %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int sharp_lq101r1sx01_hw_init(struct udevice *dev)
+{
+ struct sharp_lq101r1sx01_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ if (!priv->panel_sec)
+ return 0;
+
+ ret = regulator_set_enable_if_allowed(priv->vcc, 1);
+ if (ret) {
+ log_debug("%s: enabling power-supply failed (%d)\n",
+ __func__, ret);
+ return ret;
+ }
+
+ /*
+ * According to the datasheet, the panel needs around 10 ms to fully
+ * power up. At least another 120 ms is required before exiting sleep
+ * mode to make sure the panel is ready. Throw in another 20 ms for
+ * good measure.
+ */
+ mdelay(150);
+
+ return 0;
+}
+
+static int sharp_lq101r1sx01_probe(struct udevice *dev)
+{
+ struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
+
+ /* fill characteristics of DSI data link */
+ plat->lanes = 4;
+ plat->format = MIPI_DSI_FMT_RGB888;
+
+ return sharp_lq101r1sx01_hw_init(dev);
+}
+
+static const struct panel_ops sharp_lq101r1sx01_ops = {
+ .enable_backlight = sharp_lq101r1sx01_enable_backlight,
+ .set_backlight = sharp_lq101r1sx01_set_backlight,
+ .get_display_timing = sharp_lq101r1sx01_timings,
+};
+
+static const struct udevice_id sharp_lq101r1sx01_ids[] = {
+ { .compatible = "sharp,lq101r1sx01" },
+ { }
+};
+
+U_BOOT_DRIVER(sharp_lq101r1sx01) = {
+ .name = "sharp_lq101r1sx01",
+ .id = UCLASS_PANEL,
+ .of_match = sharp_lq101r1sx01_ids,
+ .ops = &sharp_lq101r1sx01_ops,
+ .of_to_plat = sharp_lq101r1sx01_of_to_plat,
+ .probe = sharp_lq101r1sx01_probe,
+ .plat_auto = sizeof(struct mipi_dsi_panel_plat),
+ .priv_auto = sizeof(struct sharp_lq101r1sx01_priv),
+};
diff --git a/drivers/video/tegra20/tegra-dc.c b/drivers/video/tegra20/tegra-dc.c
index accabbf4dbb..d24aa375b39 100644
--- a/drivers/video/tegra20/tegra-dc.c
+++ b/drivers/video/tegra20/tegra-dc.c
@@ -26,8 +26,6 @@
#include "tegra-dc.h"
-DECLARE_GLOBAL_DATA_PTR;
-
/* Holder of Tegra per-SOC DC differences */
struct tegra_dc_soc_info {
bool has_timer;
diff --git a/drivers/video/tegra20/tegra-dsi.c b/drivers/video/tegra20/tegra-dsi.c
index 35a8e6c176b..6327266dd22 100644
--- a/drivers/video/tegra20/tegra-dsi.c
+++ b/drivers/video/tegra20/tegra-dsi.c
@@ -20,6 +20,7 @@
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
+#include <asm/arch-tegra/clk_rst.h>
#include "tegra-dc.h"
#include "tegra-dsi.h"
@@ -50,6 +51,10 @@ struct tegra_dsi_priv {
int host_fifo_depth;
u32 version;
+
+ /* for ganged-mode support */
+ struct udevice *master;
+ struct udevice *slave;
};
static void tegra_dc_enable_controller(struct udevice *dev)
@@ -595,6 +600,17 @@ static void tegra_dsi_set_phy_timing(struct dsi_timing_reg *ptiming,
writel(value, &ptiming->dsi_bta_timing);
}
+static void tegra_dsi_ganged_enable(struct udevice *dev, unsigned int start,
+ unsigned int size)
+{
+ struct tegra_dsi_priv *priv = dev_get_priv(dev);
+ struct dsi_ganged_mode_reg *ganged = &priv->dsi->ganged;
+
+ writel(start, &ganged->ganged_mode_start);
+ writel(size << 16 | size, &ganged->ganged_mode_size);
+ writel(DSI_GANGED_MODE_CONTROL_ENABLE, &ganged->ganged_mode_ctrl);
+}
+
static void tegra_dsi_configure(struct udevice *dev,
unsigned long mode_flags)
{
@@ -679,9 +695,19 @@ static void tegra_dsi_configure(struct udevice *dev,
writel(hact << 16 | hbp, &len->dsi_pkt_len_2_3);
writel(hfp, &len->dsi_pkt_len_4_5);
writel(0x0f0f << 16, &len->dsi_pkt_len_6_7);
+
+ /* set SOL delay (for non-burst mode only) */
+ writel(8 * mul / div, &misc->dsi_sol_delay);
} else {
- /* 1 byte (DCS command) + pixel data */
- value = 1 + timing->hactive.typ * mul / div;
+ if (priv->master || priv->slave) {
+ /*
+ * For ganged mode, assume symmetric left-right mode.
+ */
+ value = 1 + (timing->hactive.typ / 2) * mul / div;
+ } else {
+ /* 1 byte (DCS command) + pixel data */
+ value = 1 + timing->hactive.typ * mul / div;
+ }
writel(0, &len->dsi_pkt_len_0_1);
writel(value << 16, &len->dsi_pkt_len_2_3);
@@ -691,10 +717,40 @@ static void tegra_dsi_configure(struct udevice *dev,
value = MIPI_DCS_WRITE_MEMORY_START << 8 |
MIPI_DCS_WRITE_MEMORY_CONTINUE;
writel(value, &len->dsi_dcs_cmds);
+
+ /* set SOL delay */
+ if (priv->master || priv->slave) {
+ unsigned long delay, bclk, bclk_ganged;
+ unsigned int lanes = device->lanes;
+ unsigned long htotal = timing->hactive.typ + timing->hfront_porch.typ +
+ timing->hback_porch.typ + timing->hsync_len.typ;
+
+ /* SOL to valid, valid to FIFO and FIFO write delay */
+ delay = 4 + 4 + 2;
+ delay = DIV_ROUND_UP(delay * mul, div * lanes);
+ /* FIFO read delay */
+ delay = delay + 6;
+
+ bclk = DIV_ROUND_UP(htotal * mul, div * lanes);
+ bclk_ganged = DIV_ROUND_UP(bclk * lanes / 2, lanes);
+ value = bclk - bclk_ganged + delay + 20;
+ } else {
+ /* TODO: revisit for non-ganged mode */
+ value = 8 * mul / div;
+ }
+
+ writel(value, &misc->dsi_sol_delay);
}
- /* set SOL delay (for non-burst mode only) */
- writel(8 * mul / div, &misc->dsi_sol_delay);
+ if (priv->slave) {
+ /*
+ * TODO: Support modes other than symmetrical left-right
+ * split.
+ */
+ tegra_dsi_ganged_enable(dev, 0, timing->hactive.typ / 2);
+ tegra_dsi_ganged_enable(priv->slave, timing->hactive.typ / 2,
+ timing->hactive.typ / 2);
+ }
}
static int tegra_dsi_encoder_enable(struct udevice *dev)
@@ -774,6 +830,9 @@ static int tegra_dsi_encoder_enable(struct udevice *dev)
value |= DSI_POWER_CONTROL_ENABLE;
writel(value, &misc->dsi_pwr_ctrl);
+ if (priv->slave)
+ tegra_dsi_encoder_enable(priv->slave);
+
return 0;
}
@@ -803,6 +862,14 @@ static void tegra_dsi_init_clocks(struct udevice *dev)
unsigned int mul, div;
unsigned long bclk, plld;
+ if (!priv->slave) {
+ /* Change DSIB clock parent to match DSIA */
+ struct clk_rst_ctlr *clkrst =
+ (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+
+ clrbits_le32(&clkrst->plld2.pll_base, BIT(25)); /* DSIB_CLK_SRC */
+ }
+
tegra_dsi_get_muldiv(device->format, &mul, &div);
bclk = (priv->timing.pixelclock.typ * mul) /
@@ -854,6 +921,24 @@ static void tegra_dsi_init_clocks(struct udevice *dev)
reset_set_enable(priv->dsi_clk, 0);
}
+static int tegra_dsi_ganged_probe(struct udevice *dev)
+{
+ struct tegra_dsi_priv *mpriv = dev_get_priv(dev);
+ struct udevice *gangster;
+
+ uclass_get_device_by_phandle(UCLASS_PANEL, dev,
+ "nvidia,ganged-mode", &gangster);
+ if (gangster) {
+ /* Ganged mode is set */
+ struct tegra_dsi_priv *spriv = dev_get_priv(gangster);
+
+ mpriv->slave = gangster;
+ spriv->master = dev;
+ }
+
+ return 0;
+}
+
static int tegra_dsi_bridge_probe(struct udevice *dev)
{
struct tegra_dsi_priv *priv = dev_get_priv(dev);
@@ -873,6 +958,8 @@ static int tegra_dsi_bridge_probe(struct udevice *dev)
priv->video_fifo_depth = 1920;
priv->host_fifo_depth = 64;
+ tegra_dsi_ganged_probe(dev);
+
ret = reset_get_by_name(dev, "dsi", &reset_ctl);
if (ret) {
log_debug("%s: reset_get_by_name() failed: %d\n",
diff --git a/drivers/video/tegra20/tegra-dsi.h b/drivers/video/tegra20/tegra-dsi.h
index 69dac4bd1b8..683c5e31a34 100644
--- a/drivers/video/tegra20/tegra-dsi.h
+++ b/drivers/video/tegra20/tegra-dsi.h
@@ -98,9 +98,9 @@ struct dsi_timeout_reg {
uint dsi_to_tally; /* _DSI_TO_TALLY_0 */
};
-/* DSI PAD control register 0x04b ~ 0x04e */
+/* DSI PAD control register 0x04b ~ 0x052 */
struct dsi_pad_ctrl_reg {
- /* Address 0x04b ~ 0x04e */
+ /* Address 0x04b ~ 0x052 */
uint pad_ctrl; /* _PAD_CONTROL_0 */
uint pad_ctrl_cd; /* _PAD_CONTROL_CD_0 */
uint pad_cd_status; /* _PAD_CD_STATUS_0 */
@@ -111,6 +111,14 @@ struct dsi_pad_ctrl_reg {
uint pad_ctrl_4; /* _PAD_CONTROL_4 */
};
+/* DSI ganged mode register 0x053 ~ 0x04e */
+struct dsi_ganged_mode_reg {
+ /* Address 0x053 ~ 0x055 */
+ uint ganged_mode_ctrl; /* _DSI_GANGED_MODE_CONTROL_0 */
+ uint ganged_mode_start; /* _DSI_GANGED_MODE_START_0 */
+ uint ganged_mode_size; /* _DSI_GANGED_MODE_SIZE_0 */
+};
+
/* Display Serial Interface (DSI_) regs */
struct dsi_ctlr {
struct dsi_syncpt_reg syncpt; /* SYNCPT register 0x000 ~ 0x002 */
@@ -133,6 +141,7 @@ struct dsi_ctlr {
uint reserved5[4]; /* reserved_5[4] */
struct dsi_pad_ctrl_reg pad; /* PAD registers 0x04b ~ 0x04e */
+ struct dsi_ganged_mode_reg ganged; /* GANGED registers 0x053 ~ 0x055 */
};
#define DSI_POWER_CONTROL_ENABLE BIT(0)
@@ -202,6 +211,8 @@ struct dsi_ctlr {
#define DSI_PAD_PREEMP_PD(x) (((x) & 0x3) << 4)
#define DSI_PAD_PREEMP_PU(x) (((x) & 0x3) << 0)
+#define DSI_GANGED_MODE_CONTROL_ENABLE BIT(0)
+
/*
* pixel format as used in the DSI_CONTROL_FORMAT field
*/
generated by cgit v1.2.3 (git 2.0.4) at 2025-07-19 07:10:04 +0000