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-rw-r--r--drivers/clk/rockchip/clk_rk3399.c154
-rw-r--r--drivers/cpu/imx8_cpu.c50
-rw-r--r--drivers/mtd/nand/raw/Kconfig18
-rw-r--r--drivers/mtd/nand/raw/denali.c1
-rw-r--r--drivers/net/Kconfig14
-rw-r--r--drivers/net/ks8851_mll.c570
-rw-r--r--drivers/pci/Kconfig8
-rw-r--r--drivers/pci/Makefile1
-rw-r--r--drivers/pci/pcie_rockchip.c491
-rw-r--r--drivers/pci/pcie_rockchip.h142
-rw-r--r--drivers/pci/pcie_rockchip_phy.c205
-rw-r--r--drivers/thermal/imx_scu_thermal.c4
12 files changed, 1359 insertions, 299 deletions
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index e009f1cf6c1..6a78837619e 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -1074,12 +1074,166 @@ static int __maybe_unused rk3399_clk_set_parent(struct clk *clk,
return -ENOENT;
}
+static int rk3399_clk_enable(struct clk *clk)
+{
+ struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
+
+ switch (clk->id) {
+ case SCLK_MAC:
+ rk_clrreg(&priv->cru->clkgate_con[5], BIT(5));
+ break;
+ case SCLK_MAC_RX:
+ rk_clrreg(&priv->cru->clkgate_con[5], BIT(8));
+ break;
+ case SCLK_MAC_TX:
+ rk_clrreg(&priv->cru->clkgate_con[5], BIT(9));
+ break;
+ case SCLK_MACREF:
+ rk_clrreg(&priv->cru->clkgate_con[5], BIT(7));
+ break;
+ case SCLK_MACREF_OUT:
+ rk_clrreg(&priv->cru->clkgate_con[5], BIT(6));
+ break;
+ case ACLK_GMAC:
+ rk_clrreg(&priv->cru->clkgate_con[32], BIT(0));
+ break;
+ case PCLK_GMAC:
+ rk_clrreg(&priv->cru->clkgate_con[32], BIT(2));
+ break;
+ case SCLK_USB3OTG0_REF:
+ rk_clrreg(&priv->cru->clkgate_con[12], BIT(1));
+ break;
+ case SCLK_USB3OTG1_REF:
+ rk_clrreg(&priv->cru->clkgate_con[12], BIT(2));
+ break;
+ case SCLK_USB3OTG0_SUSPEND:
+ rk_clrreg(&priv->cru->clkgate_con[12], BIT(3));
+ break;
+ case SCLK_USB3OTG1_SUSPEND:
+ rk_clrreg(&priv->cru->clkgate_con[12], BIT(4));
+ break;
+ case ACLK_USB3OTG0:
+ rk_clrreg(&priv->cru->clkgate_con[30], BIT(1));
+ break;
+ case ACLK_USB3OTG1:
+ rk_clrreg(&priv->cru->clkgate_con[30], BIT(2));
+ break;
+ case ACLK_USB3_RKSOC_AXI_PERF:
+ rk_clrreg(&priv->cru->clkgate_con[30], BIT(3));
+ break;
+ case ACLK_USB3:
+ rk_clrreg(&priv->cru->clkgate_con[12], BIT(0));
+ break;
+ case ACLK_USB3_GRF:
+ rk_clrreg(&priv->cru->clkgate_con[30], BIT(4));
+ break;
+ case HCLK_HOST0:
+ rk_clrreg(&priv->cru->clksel_con[20], BIT(5));
+ break;
+ case HCLK_HOST0_ARB:
+ rk_clrreg(&priv->cru->clksel_con[20], BIT(6));
+ break;
+ case HCLK_HOST1:
+ rk_clrreg(&priv->cru->clksel_con[20], BIT(7));
+ break;
+ case HCLK_HOST1_ARB:
+ rk_clrreg(&priv->cru->clksel_con[20], BIT(8));
+ break;
+ case SCLK_PCIEPHY_REF:
+ rk_clrreg(&priv->cru->clksel_con[18], BIT(10));
+ break;
+ default:
+ debug("%s: unsupported clk %ld\n", __func__, clk->id);
+ return -ENOENT;
+ }
+
+ return 0;
+}
+
+static int rk3399_clk_disable(struct clk *clk)
+{
+ struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
+
+ switch (clk->id) {
+ case SCLK_MAC:
+ rk_setreg(&priv->cru->clkgate_con[5], BIT(5));
+ break;
+ case SCLK_MAC_RX:
+ rk_setreg(&priv->cru->clkgate_con[5], BIT(8));
+ break;
+ case SCLK_MAC_TX:
+ rk_setreg(&priv->cru->clkgate_con[5], BIT(9));
+ break;
+ case SCLK_MACREF:
+ rk_setreg(&priv->cru->clkgate_con[5], BIT(7));
+ break;
+ case SCLK_MACREF_OUT:
+ rk_setreg(&priv->cru->clkgate_con[5], BIT(6));
+ break;
+ case ACLK_GMAC:
+ rk_setreg(&priv->cru->clkgate_con[32], BIT(0));
+ break;
+ case PCLK_GMAC:
+ rk_setreg(&priv->cru->clkgate_con[32], BIT(2));
+ break;
+ case SCLK_USB3OTG0_REF:
+ rk_setreg(&priv->cru->clkgate_con[12], BIT(1));
+ break;
+ case SCLK_USB3OTG1_REF:
+ rk_setreg(&priv->cru->clkgate_con[12], BIT(2));
+ break;
+ case SCLK_USB3OTG0_SUSPEND:
+ rk_setreg(&priv->cru->clkgate_con[12], BIT(3));
+ break;
+ case SCLK_USB3OTG1_SUSPEND:
+ rk_setreg(&priv->cru->clkgate_con[12], BIT(4));
+ break;
+ case ACLK_USB3OTG0:
+ rk_setreg(&priv->cru->clkgate_con[30], BIT(1));
+ break;
+ case ACLK_USB3OTG1:
+ rk_setreg(&priv->cru->clkgate_con[30], BIT(2));
+ break;
+ case ACLK_USB3_RKSOC_AXI_PERF:
+ rk_setreg(&priv->cru->clkgate_con[30], BIT(3));
+ break;
+ case ACLK_USB3:
+ rk_setreg(&priv->cru->clkgate_con[12], BIT(0));
+ break;
+ case ACLK_USB3_GRF:
+ rk_setreg(&priv->cru->clkgate_con[30], BIT(4));
+ break;
+ case HCLK_HOST0:
+ rk_setreg(&priv->cru->clksel_con[20], BIT(5));
+ break;
+ case HCLK_HOST0_ARB:
+ rk_setreg(&priv->cru->clksel_con[20], BIT(6));
+ break;
+ case HCLK_HOST1:
+ rk_setreg(&priv->cru->clksel_con[20], BIT(7));
+ break;
+ case HCLK_HOST1_ARB:
+ rk_setreg(&priv->cru->clksel_con[20], BIT(8));
+ break;
+ case SCLK_PCIEPHY_REF:
+ rk_clrreg(&priv->cru->clksel_con[18], BIT(10));
+ break;
+ default:
+ debug("%s: unsupported clk %ld\n", __func__, clk->id);
+ return -ENOENT;
+ }
+
+ return 0;
+}
+
static struct clk_ops rk3399_clk_ops = {
.get_rate = rk3399_clk_get_rate,
.set_rate = rk3399_clk_set_rate,
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
.set_parent = rk3399_clk_set_parent,
#endif
+ .enable = rk3399_clk_enable,
+ .disable = rk3399_clk_disable,
};
#ifdef CONFIG_SPL_BUILD
diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c
index dddd12d1e40..6345cd0815a 100644
--- a/drivers/cpu/imx8_cpu.c
+++ b/drivers/cpu/imx8_cpu.c
@@ -20,6 +20,7 @@ struct cpu_imx_platdata {
const char *name;
const char *rev;
const char *type;
+ u32 cpu_rsrc;
u32 cpurev;
u32 freq_mhz;
u32 mpidr;
@@ -52,16 +53,23 @@ const char *get_imx8_rev(u32 rev)
}
}
-const char *get_core_name(struct udevice *dev)
+static void set_core_data(struct udevice *dev)
{
- if (!device_is_compatible(dev, "arm,cortex-a35"))
- return "A35";
- else if (!device_is_compatible(dev, "arm,cortex-a53"))
- return "A53";
- else if (!device_is_compatible(dev, "arm,cortex-a72"))
- return "A72";
- else
- return "?";
+ struct cpu_imx_platdata *plat = dev_get_platdata(dev);
+
+ if (device_is_compatible(dev, "arm,cortex-a35")) {
+ plat->cpu_rsrc = SC_R_A35;
+ plat->name = "A35";
+ } else if (device_is_compatible(dev, "arm,cortex-a53")) {
+ plat->cpu_rsrc = SC_R_A53;
+ plat->name = "A53";
+ } else if (device_is_compatible(dev, "arm,cortex-a72")) {
+ plat->cpu_rsrc = SC_R_A72;
+ plat->name = "A72";
+ } else {
+ plat->cpu_rsrc = SC_R_A53;
+ plat->name = "?";
+ }
}
#if IS_ENABLED(CONFIG_IMX_SCU_THERMAL)
@@ -69,12 +77,12 @@ static int cpu_imx_get_temp(struct cpu_imx_platdata *plat)
{
struct udevice *thermal_dev;
int cpu_tmp, ret;
+ int idx = 1; /* use "cpu-thermal0" device */
- if (!strcmp(plat->name, "A72"))
- ret = uclass_get_device(UCLASS_THERMAL, 1, &thermal_dev);
- else
- ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
+ if (plat->cpu_rsrc == SC_R_A72)
+ idx = 2; /* use "cpu-thermal1" device */
+ ret = uclass_get_device(UCLASS_THERMAL, idx, &thermal_dev);
if (!ret) {
ret = thermal_get_temp(thermal_dev, &cpu_tmp);
if (ret)
@@ -182,19 +190,11 @@ static const struct udevice_id cpu_imx8_ids[] = {
static ulong imx8_get_cpu_rate(struct udevice *dev)
{
+ struct cpu_imx_platdata *plat = dev_get_platdata(dev);
ulong rate;
- int ret, type;
-
- if (!device_is_compatible(dev, "arm,cortex-a35"))
- type = SC_R_A35;
- else if (!device_is_compatible(dev, "arm,cortex-a53"))
- type = SC_R_A53;
- else if (!device_is_compatible(dev, "arm,cortex-a72"))
- type = SC_R_A72;
- else
- return 0;
+ int ret;
- ret = sc_pm_get_clock_rate(-1, type, SC_PM_CLK_CPU,
+ ret = sc_pm_get_clock_rate(-1, plat->cpu_rsrc, SC_PM_CLK_CPU,
(sc_pm_clock_rate_t *)&rate);
if (ret) {
printf("Could not read CPU frequency: %d\n", ret);
@@ -209,9 +209,9 @@ static int imx8_cpu_probe(struct udevice *dev)
struct cpu_imx_platdata *plat = dev_get_platdata(dev);
u32 cpurev;
+ set_core_data(dev);
cpurev = get_cpu_rev();
plat->cpurev = cpurev;
- plat->name = get_core_name(dev);
plat->rev = get_imx8_rev(cpurev & 0xFFF);
plat->type = get_imx8_type((cpurev & 0xFF000) >> 12);
plat->freq_mhz = imx8_get_cpu_rate(dev) / 1000000;
diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
index c4d9d313883..06b2ff972ca 100644
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig
@@ -121,15 +121,6 @@ config NAND_DENALI_DT
Enable the driver for NAND flash on platforms using a Denali NAND
controller as a DT device.
-config NAND_DENALI_SPARE_AREA_SKIP_BYTES
- int "Number of bytes skipped in OOB area"
- depends on NAND_DENALI
- range 0 63
- help
- This option specifies the number of bytes to skip from the beginning
- of OOB area before last ECC sector data starts. This is potentially
- used to preserve the bad block marker in the OOB area.
-
config NAND_LPC32XX_SLC
bool "Support LPC32XX_SLC controller"
help
@@ -404,6 +395,15 @@ config SPL_NAND_DENALI
This is a small implementation of the Denali NAND controller
for use on SPL.
+config NAND_DENALI_SPARE_AREA_SKIP_BYTES
+ int "Number of bytes skipped in OOB area"
+ depends on SPL_NAND_DENALI
+ range 0 63
+ help
+ This option specifies the number of bytes to skip from the beginning
+ of OOB area before last ECC sector data starts. This is potentially
+ used to preserve the bad block marker in the OOB area.
+
config SPL_NAND_SIMPLE
bool "Use simple SPL NAND driver"
depends on !SPL_NAND_AM33XX_BCH
diff --git a/drivers/mtd/nand/raw/denali.c b/drivers/mtd/nand/raw/denali.c
index 5bae7f1197e..15e90291de0 100644
--- a/drivers/mtd/nand/raw/denali.c
+++ b/drivers/mtd/nand/raw/denali.c
@@ -1095,6 +1095,7 @@ static void denali_hw_init(struct denali_nand_info *denali)
iowrite32(CHIP_EN_DONT_CARE__FLAG, denali->reg + CHIP_ENABLE_DONT_CARE);
iowrite32(0xffff, denali->reg + SPARE_AREA_MARKER);
+ iowrite32(WRITE_PROTECT__FLAG, denali->reg + WRITE_PROTECT);
}
int denali_calc_ecc_bytes(int step_size, int strength)
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index f7855c92d38..0b08de0ef45 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -307,6 +307,20 @@ config FSLDMAFEC
This driver supports the network interface units in the
ColdFire family.
+config KS8851_MLL
+ bool "Microchip KS8851-MLL controller driver"
+ help
+ The Microchip KS8851 parallel bus external ethernet interface chip.
+
+if KS8851_MLL
+if !DM_ETH
+config KS8851_MLL_BASEADDR
+ hex "Microchip KS8851-MLL Base Address"
+ help
+ Define this to hold the physical address of the device (I/O space)
+endif #DM_ETH
+endif #KS8851_MLL
+
config MVGBE
bool "Marvell Orion5x/Kirkwood network interface support"
depends on ARCH_KIRKWOOD || ARCH_ORION5X
diff --git a/drivers/net/ks8851_mll.c b/drivers/net/ks8851_mll.c
index 6643d1e9c13..3ff173ad339 100644
--- a/drivers/net/ks8851_mll.c
+++ b/drivers/net/ks8851_mll.c
@@ -17,123 +17,53 @@
#define DRIVERNAME "ks8851_mll"
-#define MAX_RECV_FRAMES 32
-#define MAX_BUF_SIZE 2048
-#define TX_BUF_SIZE 2000
#define RX_BUF_SIZE 2000
-static const struct chip_id chip_ids[] = {
- {CIDER_ID, "KSZ8851"},
- {0, NULL},
-};
-
-/*
- * union ks_tx_hdr - tx header data
- * @txb: The header as bytes
- * @txw: The header as 16bit, little-endian words
- *
- * A dual representation of the tx header data to allow
- * access to individual bytes, and to allow 16bit accesses
- * with 16bit alignment.
- */
-union ks_tx_hdr {
- u8 txb[4];
- __le16 txw[2];
-};
-
/*
* struct ks_net - KS8851 driver private data
- * @net_device : The network device we're bound to
- * @txh : temporaly buffer to save status/length.
- * @frame_head_info : frame header information for multi-pkt rx.
- * @statelock : Lock on this structure for tx list.
- * @msg_enable : The message flags controlling driver output (see ethtool).
- * @frame_cnt : number of frames received.
+ * @dev : legacy non-DM ethernet device structure
+ * @iobase : register base
* @bus_width : i/o bus width.
- * @irq : irq number assigned to this device.
- * @rc_rxqcr : Cached copy of KS_RXQCR.
- * @rc_txcr : Cached copy of KS_TXCR.
- * @rc_ier : Cached copy of KS_IER.
* @sharedbus : Multipex(addr and data bus) mode indicator.
- * @cmd_reg_cache : command register cached.
- * @cmd_reg_cache_int : command register cached. Used in the irq handler.
- * @promiscuous : promiscuous mode indicator.
- * @all_mcast : mutlicast indicator.
- * @mcast_lst_size : size of multicast list.
- * @mcast_lst : multicast list.
- * @mcast_bits : multicast enabed.
- * @mac_addr : MAC address assigned to this device.
- * @fid : frame id.
- * @extra_byte : number of extra byte prepended rx pkt.
- * @enabled : indicator this device works.
+ * @extra_byte : number of extra byte prepended rx pkt.
*/
-
-/* Receive multiplex framer header info */
-struct type_frame_head {
- u16 sts; /* Frame status */
- u16 len; /* Byte count */
-} fr_h_i[MAX_RECV_FRAMES];
-
struct ks_net {
- struct net_device *netdev;
- union ks_tx_hdr txh;
- struct type_frame_head *frame_head_info;
- u32 msg_enable;
- u32 frame_cnt;
+#ifndef CONFIG_DM_ETH
+ struct eth_device dev;
+#endif
+ phys_addr_t iobase;
int bus_width;
- int irq;
- u16 rc_rxqcr;
- u16 rc_txcr;
- u16 rc_ier;
u16 sharedbus;
- u16 cmd_reg_cache;
- u16 cmd_reg_cache_int;
- u16 promiscuous;
- u16 all_mcast;
- u16 mcast_lst_size;
- u8 mcast_lst[MAX_MCAST_LST][MAC_ADDR_LEN];
- u8 mcast_bits[HW_MCAST_SIZE];
- u8 mac_addr[6];
- u8 fid;
+ u16 rxfc;
u8 extra_byte;
- u8 enabled;
-} ks_str, *ks;
+};
#define BE3 0x8000 /* Byte Enable 3 */
#define BE2 0x4000 /* Byte Enable 2 */
#define BE1 0x2000 /* Byte Enable 1 */
#define BE0 0x1000 /* Byte Enable 0 */
-static u8 ks_rdreg8(struct eth_device *dev, u16 offset)
+static u8 ks_rdreg8(struct ks_net *ks, u16 offset)
{
u8 shift_bit = offset & 0x03;
u8 shift_data = (offset & 1) << 3;
- writew(offset | (BE0 << shift_bit), dev->iobase + 2);
-
- return (u8)(readw(dev->iobase) >> shift_data);
-}
-
-static u16 ks_rdreg16(struct eth_device *dev, u16 offset)
-{
- writew(offset | ((BE1 | BE0) << (offset & 0x02)), dev->iobase + 2);
+ writew(offset | (BE0 << shift_bit), ks->iobase + 2);
- return readw(dev->iobase);
+ return (u8)(readw(ks->iobase) >> shift_data);
}
-static void ks_wrreg8(struct eth_device *dev, u16 offset, u8 val)
+static u16 ks_rdreg16(struct ks_net *ks, u16 offset)
{
- u8 shift_bit = (offset & 0x03);
- u16 value_write = (u16)(val << ((offset & 1) << 3));
+ writew(offset | ((BE1 | BE0) << (offset & 0x02)), ks->iobase + 2);
- writew(offset | (BE0 << shift_bit), dev->iobase + 2);
- writew(value_write, dev->iobase);
+ return readw(ks->iobase);
}
-static void ks_wrreg16(struct eth_device *dev, u16 offset, u16 val)
+static void ks_wrreg16(struct ks_net *ks, u16 offset, u16 val)
{
- writew(offset | ((BE1 | BE0) << (offset & 0x02)), dev->iobase + 2);
- writew(val, dev->iobase);
+ writew(offset | ((BE1 | BE0) << (offset & 0x02)), ks->iobase + 2);
+ writew(val, ks->iobase);
}
/*
@@ -143,12 +73,12 @@ static void ks_wrreg16(struct eth_device *dev, u16 offset, u16 val)
* @wptr: buffer address to save data
* @len: length in byte to read
*/
-static inline void ks_inblk(struct eth_device *dev, u16 *wptr, u32 len)
+static inline void ks_inblk(struct ks_net *ks, u16 *wptr, u32 len)
{
len >>= 1;
while (len--)
- *wptr++ = readw(dev->iobase);
+ *wptr++ = readw(ks->iobase);
}
/*
@@ -157,42 +87,42 @@ static inline void ks_inblk(struct eth_device *dev, u16 *wptr, u32 len)
* @wptr: buffer address
* @len: length in byte to write
*/
-static inline void ks_outblk(struct eth_device *dev, u16 *wptr, u32 len)
+static inline void ks_outblk(struct ks_net *ks, u16 *wptr, u32 len)
{
len >>= 1;
while (len--)
- writew(*wptr++, dev->iobase);
+ writew(*wptr++, ks->iobase);
}
-static void ks_enable_int(struct eth_device *dev)
+static void ks_enable_int(struct ks_net *ks)
{
- ks_wrreg16(dev, KS_IER, ks->rc_ier);
+ ks_wrreg16(ks, KS_IER, IRQ_LCI | IRQ_TXI | IRQ_RXI);
}
-static void ks_set_powermode(struct eth_device *dev, unsigned pwrmode)
+static void ks_set_powermode(struct ks_net *ks, unsigned int pwrmode)
{
- unsigned pmecr;
+ unsigned int pmecr;
- ks_rdreg16(dev, KS_GRR);
- pmecr = ks_rdreg16(dev, KS_PMECR);
+ ks_rdreg16(ks, KS_GRR);
+ pmecr = ks_rdreg16(ks, KS_PMECR);
pmecr &= ~PMECR_PM_MASK;
pmecr |= pwrmode;
- ks_wrreg16(dev, KS_PMECR, pmecr);
+ ks_wrreg16(ks, KS_PMECR, pmecr);
}
/*
* ks_read_config - read chip configuration of bus width.
* @ks: The chip information
*/
-static void ks_read_config(struct eth_device *dev)
+static void ks_read_config(struct ks_net *ks)
{
u16 reg_data = 0;
/* Regardless of bus width, 8 bit read should always work. */
- reg_data = ks_rdreg8(dev, KS_CCR) & 0x00FF;
- reg_data |= ks_rdreg8(dev, KS_CCR + 1) << 8;
+ reg_data = ks_rdreg8(ks, KS_CCR) & 0x00FF;
+ reg_data |= ks_rdreg8(ks, KS_CCR + 1) << 8;
/* addr/data bus are multiplexed */
ks->sharedbus = (reg_data & CCR_SHARED) == CCR_SHARED;
@@ -226,58 +156,58 @@ static void ks_read_config(struct eth_device *dev)
* not currently specify the exact sequence, we have chosen something
* that seems to work with our device.
*/
-static void ks_soft_reset(struct eth_device *dev, unsigned op)
+static void ks_soft_reset(struct ks_net *ks, unsigned int op)
{
/* Disable interrupt first */
- ks_wrreg16(dev, KS_IER, 0x0000);
- ks_wrreg16(dev, KS_GRR, op);
+ ks_wrreg16(ks, KS_IER, 0x0000);
+ ks_wrreg16(ks, KS_GRR, op);
mdelay(10); /* wait a short time to effect reset */
- ks_wrreg16(dev, KS_GRR, 0);
+ ks_wrreg16(ks, KS_GRR, 0);
mdelay(1); /* wait for condition to clear */
}
-void ks_enable_qmu(struct eth_device *dev)
+void ks_enable_qmu(struct ks_net *ks)
{
u16 w;
- w = ks_rdreg16(dev, KS_TXCR);
+ w = ks_rdreg16(ks, KS_TXCR);
/* Enables QMU Transmit (TXCR). */
- ks_wrreg16(dev, KS_TXCR, w | TXCR_TXE);
+ ks_wrreg16(ks, KS_TXCR, w | TXCR_TXE);
/* Enable RX Frame Count Threshold and Auto-Dequeue RXQ Frame */
- w = ks_rdreg16(dev, KS_RXQCR);
- ks_wrreg16(dev, KS_RXQCR, w | RXQCR_RXFCTE);
+ w = ks_rdreg16(ks, KS_RXQCR);
+ ks_wrreg16(ks, KS_RXQCR, w | RXQCR_RXFCTE);
/* Enables QMU Receive (RXCR1). */
- w = ks_rdreg16(dev, KS_RXCR1);
- ks_wrreg16(dev, KS_RXCR1, w | RXCR1_RXE);
+ w = ks_rdreg16(ks, KS_RXCR1);
+ ks_wrreg16(ks, KS_RXCR1, w | RXCR1_RXE);
}
-static void ks_disable_qmu(struct eth_device *dev)
+static void ks_disable_qmu(struct ks_net *ks)
{
u16 w;
- w = ks_rdreg16(dev, KS_TXCR);
+ w = ks_rdreg16(ks, KS_TXCR);
/* Disables QMU Transmit (TXCR). */
w &= ~TXCR_TXE;
- ks_wrreg16(dev, KS_TXCR, w);
+ ks_wrreg16(ks, KS_TXCR, w);
/* Disables QMU Receive (RXCR1). */
- w = ks_rdreg16(dev, KS_RXCR1);
+ w = ks_rdreg16(ks, KS_RXCR1);
w &= ~RXCR1_RXE;
- ks_wrreg16(dev, KS_RXCR1, w);
+ ks_wrreg16(ks, KS_RXCR1, w);
}
-static inline void ks_read_qmu(struct eth_device *dev, u16 *buf, u32 len)
+static inline void ks_read_qmu(struct ks_net *ks, u16 *buf, u32 len)
{
u32 r = ks->extra_byte & 0x1;
u32 w = ks->extra_byte - r;
/* 1. set sudo DMA mode */
- ks_wrreg16(dev, KS_RXFDPR, RXFDPR_RXFPAI);
- ks_wrreg8(dev, KS_RXQCR, (ks->rc_rxqcr | RXQCR_SDA) & 0xff);
+ ks_wrreg16(ks, KS_RXFDPR, RXFDPR_RXFPAI);
+ ks_wrreg16(ks, KS_RXQCR, RXQCR_CMD_CNTL | RXQCR_SDA);
/*
* 2. read prepend data
@@ -287,50 +217,42 @@ static inline void ks_read_qmu(struct eth_device *dev, u16 *buf, u32 len)
*/
if (r)
- ks_rdreg8(dev, 0);
+ ks_rdreg8(ks, 0);
- ks_inblk(dev, buf, w + 2 + 2);
+ ks_inblk(ks, buf, w + 2 + 2);
/* 3. read pkt data */
- ks_inblk(dev, buf, ALIGN(len, 4));
+ ks_inblk(ks, buf, ALIGN(len, 4));
/* 4. reset sudo DMA Mode */
- ks_wrreg8(dev, KS_RXQCR, (ks->rc_rxqcr & ~RXQCR_SDA) & 0xff);
+ ks_wrreg16(ks, KS_RXQCR, RXQCR_CMD_CNTL);
}
-static void ks_rcv(struct eth_device *dev, uchar **pv_data)
+static int ks_rcv(struct ks_net *ks, uchar *data)
{
- struct type_frame_head *frame_hdr = ks->frame_head_info;
- int i;
+ u16 sts, len;
- ks->frame_cnt = ks_rdreg16(dev, KS_RXFCTR) >> 8;
+ if (!ks->rxfc)
+ ks->rxfc = ks_rdreg16(ks, KS_RXFCTR) >> 8;
- /* read all header information */
- for (i = 0; i < ks->frame_cnt; i++) {
- /* Checking Received packet status */
- frame_hdr->sts = ks_rdreg16(dev, KS_RXFHSR);
- /* Get packet len from hardware */
- frame_hdr->len = ks_rdreg16(dev, KS_RXFHBCR);
- frame_hdr++;
- }
+ if (!ks->rxfc)
+ return 0;
- frame_hdr = ks->frame_head_info;
- while (ks->frame_cnt--) {
- if ((frame_hdr->sts & RXFSHR_RXFV) &&
- (frame_hdr->len < RX_BUF_SIZE) &&
- frame_hdr->len) {
- /* read data block including CRC 4 bytes */
- ks_read_qmu(dev, (u16 *)(*pv_data), frame_hdr->len);
-
- /* net_rx_packets buffer size is ok (*pv_data) */
- net_process_received_packet(*pv_data, frame_hdr->len);
- pv_data++;
- } else {
- ks_wrreg16(dev, KS_RXQCR, (ks->rc_rxqcr | RXQCR_RRXEF));
- printf(DRIVERNAME ": bad packet\n");
- }
- frame_hdr++;
+ /* Checking Received packet status */
+ sts = ks_rdreg16(ks, KS_RXFHSR);
+ /* Get packet len from hardware */
+ len = ks_rdreg16(ks, KS_RXFHBCR);
+
+ if ((sts & RXFSHR_RXFV) && len && (len < RX_BUF_SIZE)) {
+ /* read data block including CRC 4 bytes */
+ ks_read_qmu(ks, (u16 *)data, len);
+ ks->rxfc--;
+ return len - 4;
}
+
+ ks_wrreg16(ks, KS_RXQCR, RXQCR_CMD_CNTL | RXQCR_RRXEF);
+ printf(DRIVERNAME ": bad packet\n");
+ return 0;
}
/*
@@ -339,13 +261,13 @@ static void ks_rcv(struct eth_device *dev, uchar **pv_data)
*
* Read and check the TX/RX memory selftest information.
*/
-static int ks_read_selftest(struct eth_device *dev)
+static int ks_read_selftest(struct ks_net *ks)
{
u16 both_done = MBIR_TXMBF | MBIR_RXMBF;
u16 mbir;
int ret = 0;
- mbir = ks_rdreg16(dev, KS_MBIR);
+ mbir = ks_rdreg16(ks, KS_MBIR);
if ((mbir & both_done) != both_done) {
printf(DRIVERNAME ": Memory selftest not finished\n");
@@ -367,61 +289,55 @@ static int ks_read_selftest(struct eth_device *dev)
return ret;
}
-static void ks_setup(struct eth_device *dev)
+static void ks_setup(struct ks_net *ks)
{
u16 w;
/* Setup Transmit Frame Data Pointer Auto-Increment (TXFDPR) */
- ks_wrreg16(dev, KS_TXFDPR, TXFDPR_TXFPAI);
+ ks_wrreg16(ks, KS_TXFDPR, TXFDPR_TXFPAI);
/* Setup Receive Frame Data Pointer Auto-Increment */
- ks_wrreg16(dev, KS_RXFDPR, RXFDPR_RXFPAI);
+ ks_wrreg16(ks, KS_RXFDPR, RXFDPR_RXFPAI);
/* Setup Receive Frame Threshold - 1 frame (RXFCTFC) */
- ks_wrreg16(dev, KS_RXFCTR, 1 & RXFCTR_THRESHOLD_MASK);
+ ks_wrreg16(ks, KS_RXFCTR, 1 & RXFCTR_THRESHOLD_MASK);
/* Setup RxQ Command Control (RXQCR) */
- ks->rc_rxqcr = RXQCR_CMD_CNTL;
- ks_wrreg16(dev, KS_RXQCR, ks->rc_rxqcr);
+ ks_wrreg16(ks, KS_RXQCR, RXQCR_CMD_CNTL);
/*
* set the force mode to half duplex, default is full duplex
* because if the auto-negotiation fails, most switch uses
* half-duplex.
*/
- w = ks_rdreg16(dev, KS_P1MBCR);
+ w = ks_rdreg16(ks, KS_P1MBCR);
w &= ~P1MBCR_FORCE_FDX;
- ks_wrreg16(dev, KS_P1MBCR, w);
+ ks_wrreg16(ks, KS_P1MBCR, w);
w = TXCR_TXFCE | TXCR_TXPE | TXCR_TXCRC | TXCR_TCGIP;
- ks_wrreg16(dev, KS_TXCR, w);
+ ks_wrreg16(ks, KS_TXCR, w);
w = RXCR1_RXFCE | RXCR1_RXBE | RXCR1_RXUE | RXCR1_RXME | RXCR1_RXIPFCC;
/* Normal mode */
w |= RXCR1_RXPAFMA;
- ks_wrreg16(dev, KS_RXCR1, w);
+ ks_wrreg16(ks, KS_RXCR1, w);
}
-static void ks_setup_int(struct eth_device *dev)
+static void ks_setup_int(struct ks_net *ks)
{
- ks->rc_ier = 0x00;
-
/* Clear the interrupts status of the hardware. */
- ks_wrreg16(dev, KS_ISR, 0xffff);
-
- /* Enables the interrupts of the hardware. */
- ks->rc_ier = (IRQ_LCI | IRQ_TXI | IRQ_RXI);
+ ks_wrreg16(ks, KS_ISR, 0xffff);
}
-static int ks8851_mll_detect_chip(struct eth_device *dev)
+static int ks8851_mll_detect_chip(struct ks_net *ks)
{
- unsigned short val, i;
+ unsigned short val;
- ks_read_config(dev);
+ ks_read_config(ks);
- val = ks_rdreg16(dev, KS_CIDER);
+ val = ks_rdreg16(ks, KS_CIDER);
if (val == 0xffff) {
/* Special case -- no chip present */
@@ -434,107 +350,95 @@ static int ks8851_mll_detect_chip(struct eth_device *dev)
debug("Read back KS8851 id 0x%x\n", val);
- /* only one entry in the table */
- val &= 0xfff0;
- for (i = 0; chip_ids[i].id != 0; i++) {
- if (chip_ids[i].id == val)
- break;
- }
- if (!chip_ids[i].id) {
+ if ((val & 0xfff0) != CIDER_ID) {
printf(DRIVERNAME ": Unknown chip ID %04x\n", val);
return -1;
}
- dev->priv = (void *)&chip_ids[i];
-
return 0;
}
-static void ks8851_mll_reset(struct eth_device *dev)
+static void ks8851_mll_reset(struct ks_net *ks)
{
/* wake up powermode to normal mode */
- ks_set_powermode(dev, PMECR_PM_NORMAL);
+ ks_set_powermode(ks, PMECR_PM_NORMAL);
mdelay(1); /* wait for normal mode to take effect */
/* Disable interrupt and reset */
- ks_soft_reset(dev, GRR_GSR);
+ ks_soft_reset(ks, GRR_GSR);
/* turn off the IRQs and ack any outstanding */
- ks_wrreg16(dev, KS_IER, 0x0000);
- ks_wrreg16(dev, KS_ISR, 0xffff);
+ ks_wrreg16(ks, KS_IER, 0x0000);
+ ks_wrreg16(ks, KS_ISR, 0xffff);
/* shutdown RX/TX QMU */
- ks_disable_qmu(dev);
+ ks_disable_qmu(ks);
}
-static void ks8851_mll_phy_configure(struct eth_device *dev)
+static void ks8851_mll_phy_configure(struct ks_net *ks)
{
u16 data;
- ks_setup(dev);
- ks_setup_int(dev);
+ ks_setup(ks);
+ ks_setup_int(ks);
/* Probing the phy */
- data = ks_rdreg16(dev, KS_OBCR);
- ks_wrreg16(dev, KS_OBCR, data | OBCR_ODS_16MA);
+ data = ks_rdreg16(ks, KS_OBCR);
+ ks_wrreg16(ks, KS_OBCR, data | OBCR_ODS_16MA);
debug(DRIVERNAME ": phy initialized\n");
}
-static void ks8851_mll_enable(struct eth_device *dev)
+static void ks8851_mll_enable(struct ks_net *ks)
{
- ks_wrreg16(dev, KS_ISR, 0xffff);
- ks_enable_int(dev);
- ks_enable_qmu(dev);
+ ks_wrreg16(ks, KS_ISR, 0xffff);
+ ks_enable_int(ks);
+ ks_enable_qmu(ks);
}
-static int ks8851_mll_init(struct eth_device *dev, bd_t *bd)
+static int ks8851_mll_init_common(struct ks_net *ks)
{
- struct chip_id *id = dev->priv;
-
- debug(DRIVERNAME ": detected %s controller\n", id->name);
-
- if (ks_read_selftest(dev)) {
+ if (ks_read_selftest(ks)) {
printf(DRIVERNAME ": Selftest failed\n");
return -1;
}
- ks8851_mll_reset(dev);
+ ks8851_mll_reset(ks);
/* Configure the PHY, initialize the link state */
- ks8851_mll_phy_configure(dev);
+ ks8851_mll_phy_configure(ks);
- /* static allocation of private informations */
- ks->frame_head_info = fr_h_i;
+ ks->rxfc = 0;
/* Turn on Tx + Rx */
- ks8851_mll_enable(dev);
+ ks8851_mll_enable(ks);
return 0;
}
-static void ks_write_qmu(struct eth_device *dev, u8 *pdata, u16 len)
+static void ks_write_qmu(struct ks_net *ks, u8 *pdata, u16 len)
{
+ __le16 txw[2];
/* start header at txb[0] to align txw entries */
- ks->txh.txw[0] = 0;
- ks->txh.txw[1] = cpu_to_le16(len);
+ txw[0] = 0;
+ txw[1] = cpu_to_le16(len);
/* 1. set sudo-DMA mode */
- ks_wrreg16(dev, KS_TXFDPR, TXFDPR_TXFPAI);
- ks_wrreg8(dev, KS_RXQCR, (ks->rc_rxqcr | RXQCR_SDA) & 0xff);
- /* 2. write status/lenth info */
- ks_outblk(dev, ks->txh.txw, 4);
+ ks_wrreg16(ks, KS_TXFDPR, TXFDPR_TXFPAI);
+ ks_wrreg16(ks, KS_RXQCR, RXQCR_CMD_CNTL | RXQCR_SDA);
+ /* 2. write status/length info */
+ ks_outblk(ks, txw, 4);
/* 3. write pkt data */
- ks_outblk(dev, (u16 *)pdata, ALIGN(len, 4));
+ ks_outblk(ks, (u16 *)pdata, ALIGN(len, 4));
/* 4. reset sudo-DMA mode */
- ks_wrreg8(dev, KS_RXQCR, (ks->rc_rxqcr & ~RXQCR_SDA) & 0xff);
+ ks_wrreg16(ks, KS_RXQCR, RXQCR_CMD_CNTL);
/* 5. Enqueue Tx(move the pkt from TX buffer into TXQ) */
- ks_wrreg16(dev, KS_TXQCR, TXQCR_METFE);
+ ks_wrreg16(ks, KS_TXQCR, TXQCR_METFE);
/* 6. wait until TXQCR_METFE is auto-cleared */
- do { } while (ks_rdreg16(dev, KS_TXQCR) & TXQCR_METFE);
+ do { } while (ks_rdreg16(ks, KS_TXQCR) & TXQCR_METFE);
}
-static int ks8851_mll_send(struct eth_device *dev, void *packet, int length)
+static int ks8851_mll_send_common(struct ks_net *ks, void *packet, int length)
{
u8 *data = (u8 *)packet;
u16 tmplen = (u16)length;
@@ -544,19 +448,19 @@ static int ks8851_mll_send(struct eth_device *dev, void *packet, int length)
* Extra space are required:
* 4 byte for alignment, 4 for status/length, 4 for CRC
*/
- retv = ks_rdreg16(dev, KS_TXMIR) & 0x1fff;
+ retv = ks_rdreg16(ks, KS_TXMIR) & 0x1fff;
if (retv >= tmplen + 12) {
- ks_write_qmu(dev, data, tmplen);
+ ks_write_qmu(ks, data, tmplen);
return 0;
- } else {
- printf(DRIVERNAME ": failed to send packet: No buffer\n");
- return -1;
}
+
+ printf(DRIVERNAME ": failed to send packet: No buffer\n");
+ return -1;
}
-static void ks8851_mll_halt(struct eth_device *dev)
+static void ks8851_mll_halt_common(struct ks_net *ks)
{
- ks8851_mll_reset(dev);
+ ks8851_mll_reset(ks);
}
/*
@@ -565,70 +469,208 @@ static void ks8851_mll_halt(struct eth_device *dev)
* needs to be enough to prevent a packet being discarded while
* we are processing the previous one.
*/
-static int ks8851_mll_recv(struct eth_device *dev)
+static int ks8851_mll_recv_common(struct ks_net *ks, uchar *data)
{
u16 status;
+ int ret = 0;
+
+ status = ks_rdreg16(ks, KS_ISR);
- status = ks_rdreg16(dev, KS_ISR);
+ ks_wrreg16(ks, KS_ISR, status);
- ks_wrreg16(dev, KS_ISR, status);
+ if (ks->rxfc || (status & IRQ_RXI))
+ ret = ks_rcv(ks, data);
- if ((status & IRQ_RXI))
- ks_rcv(dev, (uchar **)net_rx_packets);
+ if (status & IRQ_LDI) {
+ u16 pmecr = ks_rdreg16(ks, KS_PMECR);
- if ((status & IRQ_LDI)) {
- u16 pmecr = ks_rdreg16(dev, KS_PMECR);
pmecr &= ~PMECR_WKEVT_MASK;
- ks_wrreg16(dev, KS_PMECR, pmecr | PMECR_WKEVT_LINK);
+ ks_wrreg16(ks, KS_PMECR, pmecr | PMECR_WKEVT_LINK);
}
- return 0;
+ return ret;
}
-static int ks8851_mll_write_hwaddr(struct eth_device *dev)
+static void ks8851_mll_write_hwaddr_common(struct ks_net *ks, u8 enetaddr[6])
{
u16 addrl, addrm, addrh;
- addrh = (dev->enetaddr[0] << 8) | dev->enetaddr[1];
- addrm = (dev->enetaddr[2] << 8) | dev->enetaddr[3];
- addrl = (dev->enetaddr[4] << 8) | dev->enetaddr[5];
+ addrh = (enetaddr[0] << 8) | enetaddr[1];
+ addrm = (enetaddr[2] << 8) | enetaddr[3];
+ addrl = (enetaddr[4] << 8) | enetaddr[5];
+
+ ks_wrreg16(ks, KS_MARH, addrh);
+ ks_wrreg16(ks, KS_MARM, addrm);
+ ks_wrreg16(ks, KS_MARL, addrl);
+}
+
+#ifndef CONFIG_DM_ETH
+static int ks8851_mll_init(struct eth_device *dev, bd_t *bd)
+{
+ struct ks_net *ks = container_of(dev, struct ks_net, dev);
+
+ return ks8851_mll_init_common(ks);
+}
+
+static void ks8851_mll_halt(struct eth_device *dev)
+{
+ struct ks_net *ks = container_of(dev, struct ks_net, dev);
+
+ ks8851_mll_halt_common(ks);
+}
+
+static int ks8851_mll_send(struct eth_device *dev, void *packet, int length)
+{
+ struct ks_net *ks = container_of(dev, struct ks_net, dev);
+
+ return ks8851_mll_send_common(ks, packet, length);
+}
+
+static int ks8851_mll_recv(struct eth_device *dev)
+{
+ struct ks_net *ks = container_of(dev, struct ks_net, dev);
+ int ret;
+
+ ret = ks8851_mll_recv_common(ks, net_rx_packets[0]);
+ if (ret)
+ net_process_received_packet(net_rx_packets[0], ret);
+
+ return ret;
+}
+
+static int ks8851_mll_write_hwaddr(struct eth_device *dev)
+{
+ struct ks_net *ks = container_of(dev, struct ks_net, dev);
- ks_wrreg16(dev, KS_MARH, addrh);
- ks_wrreg16(dev, KS_MARM, addrm);
- ks_wrreg16(dev, KS_MARL, addrl);
+ ks8851_mll_write_hwaddr_common(ks, ks->dev.enetaddr);
return 0;
}
int ks8851_mll_initialize(u8 dev_num, int base_addr)
{
- struct eth_device *dev;
+ struct ks_net *ks;
+
+ ks = calloc(1, sizeof(*ks));
+ if (!ks)
+ return -ENOMEM;
+
+ ks->iobase = base_addr;
- dev = malloc(sizeof(*dev));
- if (!dev) {
- printf("Error: Failed to allocate memory\n");
+ /* Try to detect chip. Will fail if not present. */
+ if (ks8851_mll_detect_chip(ks)) {
+ free(ks);
return -1;
}
- memset(dev, 0, sizeof(*dev));
- dev->iobase = base_addr;
+ ks->dev.init = ks8851_mll_init;
+ ks->dev.halt = ks8851_mll_halt;
+ ks->dev.send = ks8851_mll_send;
+ ks->dev.recv = ks8851_mll_recv;
+ ks->dev.write_hwaddr = ks8851_mll_write_hwaddr;
+ sprintf(ks->dev.name, "%s-%hu", DRIVERNAME, dev_num);
+
+ eth_register(&ks->dev);
+
+ return 0;
+}
+#else /* ifdef CONFIG_DM_ETH */
+static int ks8851_start(struct udevice *dev)
+{
+ struct ks_net *ks = dev_get_priv(dev);
+
+ return ks8851_mll_init_common(ks);
+}
+
+static void ks8851_stop(struct udevice *dev)
+{
+ struct ks_net *ks = dev_get_priv(dev);
- ks = &ks_str;
+ ks8851_mll_halt_common(ks);
+}
+
+static int ks8851_send(struct udevice *dev, void *packet, int length)
+{
+ struct ks_net *ks = dev_get_priv(dev);
+ int ret;
+
+ ret = ks8851_mll_send_common(ks, packet, length);
+
+ return ret ? 0 : -ETIMEDOUT;
+}
+
+static int ks8851_recv(struct udevice *dev, int flags, uchar **packetp)
+{
+ struct ks_net *ks = dev_get_priv(dev);
+ uchar *data = net_rx_packets[0];
+ int ret;
+
+ ret = ks8851_mll_recv_common(ks, data);
+ if (ret)
+ *packetp = (void *)data;
+
+ return ret ? ret : -EAGAIN;
+}
+
+static int ks8851_write_hwaddr(struct udevice *dev)
+{
+ struct ks_net *ks = dev_get_priv(dev);
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+
+ ks8851_mll_write_hwaddr_common(ks, pdata->enetaddr);
+
+ return 0;
+}
+
+static int ks8851_bind(struct udevice *dev)
+{
+ return device_set_name(dev, dev->name);
+}
+
+static int ks8851_probe(struct udevice *dev)
+{
+ struct ks_net *ks = dev_get_priv(dev);
/* Try to detect chip. Will fail if not present. */
- if (ks8851_mll_detect_chip(dev)) {
- free(dev);
- return -1;
- }
+ ks8851_mll_detect_chip(ks);
- dev->init = ks8851_mll_init;
- dev->halt = ks8851_mll_halt;
- dev->send = ks8851_mll_send;
- dev->recv = ks8851_mll_recv;
- dev->write_hwaddr = ks8851_mll_write_hwaddr;
- sprintf(dev->name, "%s-%hu", DRIVERNAME, dev_num);
+ return 0;
+}
+
+static int ks8851_ofdata_to_platdata(struct udevice *dev)
+{
+ struct ks_net *ks = dev_get_priv(dev);
+ struct eth_pdata *pdata = dev_get_platdata(dev);
- eth_register(dev);
+ pdata->iobase = devfdt_get_addr(dev);
+ ks->iobase = pdata->iobase;
return 0;
}
+
+static const struct eth_ops ks8851_ops = {
+ .start = ks8851_start,
+ .stop = ks8851_stop,
+ .send = ks8851_send,
+ .recv = ks8851_recv,
+ .write_hwaddr = ks8851_write_hwaddr,
+};
+
+static const struct udevice_id ks8851_ids[] = {
+ { .compatible = "micrel,ks8851-mll" },
+ { }
+};
+
+U_BOOT_DRIVER(ks8851) = {
+ .name = "eth_ks8851",
+ .id = UCLASS_ETH,
+ .of_match = ks8851_ids,
+ .bind = ks8851_bind,
+ .ofdata_to_platdata = ks8851_ofdata_to_platdata,
+ .probe = ks8851_probe,
+ .ops = &ks8851_ops,
+ .priv_auto_alloc_size = sizeof(struct ks_net),
+ .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .flags = DM_FLAG_ALLOC_PRIV_DMA,
+};
+#endif
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index 6fc26884e24..6d8c22aacf2 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -197,4 +197,12 @@ config PCIE_MEDIATEK
Say Y here if you want to enable Gen2 PCIe controller,
which could be found on MT7623 SoC family.
+config PCIE_ROCKCHIP
+ bool "Enable Rockchip PCIe driver"
+ select DM_PCI
+ default y if ROCKCHIP_RK3399
+ help
+ Say Y here if you want to enable PCIe controller support on
+ Rockchip SoCs.
+
endif
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index c051ecc9f39..955351c5c2c 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -43,3 +43,4 @@ obj-$(CONFIG_PCI_PHYTIUM) += pcie_phytium.o
obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o
obj-$(CONFIG_PCI_KEYSTONE) += pcie_dw_ti.o
obj-$(CONFIG_PCIE_MEDIATEK) += pcie_mediatek.o
+obj-$(CONFIG_PCIE_ROCKCHIP) += pcie_rockchip.o pcie_rockchip_phy.o
diff --git a/drivers/pci/pcie_rockchip.c b/drivers/pci/pcie_rockchip.c
new file mode 100644
index 00000000000..82a8396e42c
--- /dev/null
+++ b/drivers/pci/pcie_rockchip.c
@@ -0,0 +1,491 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Rockchip AXI PCIe host controller driver
+ *
+ * Copyright (c) 2016 Rockchip, Inc.
+ * Copyright (c) 2020 Amarula Solutions(India)
+ * Copyright (c) 2020 Jagan Teki <jagan@amarulasolutions.com>
+ * Copyright (c) 2019 Patrick Wildt <patrick@blueri.se>
+ * Copyright (c) 2018 Mark Kettenis <kettenis@openbsd.org>
+ *
+ * Bits taken from Linux Rockchip PCIe host controller.
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <pci.h>
+#include <power-domain.h>
+#include <power/regulator.h>
+#include <reset.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <asm-generic/gpio.h>
+#include <asm/arch-rockchip/clock.h>
+#include <linux/iopoll.h>
+
+#include "pcie_rockchip.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int rockchip_pcie_off_conf(pci_dev_t bdf, uint offset)
+{
+ unsigned int bus = PCI_BUS(bdf);
+ unsigned int dev = PCI_DEV(bdf);
+ unsigned int func = PCI_FUNC(bdf);
+
+ return (bus << 20) | (dev << 15) | (func << 12) | (offset & ~0x3);
+}
+
+static int rockchip_pcie_rd_conf(const struct udevice *udev, pci_dev_t bdf,
+ uint offset, ulong *valuep,
+ enum pci_size_t size)
+{
+ struct rockchip_pcie *priv = dev_get_priv(udev);
+ unsigned int bus = PCI_BUS(bdf);
+ unsigned int dev = PCI_DEV(bdf);
+ int where = rockchip_pcie_off_conf(bdf, offset);
+ ulong value;
+
+ if (bus == priv->first_busno && dev == 0) {
+ value = readl(priv->apb_base + PCIE_RC_NORMAL_BASE + where);
+ *valuep = pci_conv_32_to_size(value, offset, size);
+ return 0;
+ }
+
+ if ((bus == priv->first_busno + 1) && dev == 0) {
+ value = readl(priv->axi_base + where);
+ *valuep = pci_conv_32_to_size(value, offset, size);
+ return 0;
+ }
+
+ *valuep = pci_get_ff(size);
+
+ return 0;
+}
+
+static int rockchip_pcie_wr_conf(struct udevice *udev, pci_dev_t bdf,
+ uint offset, ulong value,
+ enum pci_size_t size)
+{
+ struct rockchip_pcie *priv = dev_get_priv(udev);
+ unsigned int bus = PCI_BUS(bdf);
+ unsigned int dev = PCI_DEV(bdf);
+ int where = rockchip_pcie_off_conf(bdf, offset);
+ ulong old;
+
+ if (bus == priv->first_busno && dev == 0) {
+ old = readl(priv->apb_base + PCIE_RC_NORMAL_BASE + where);
+ value = pci_conv_size_to_32(old, value, offset, size);
+ writel(value, priv->apb_base + PCIE_RC_NORMAL_BASE + where);
+ return 0;
+ }
+
+ if ((bus == priv->first_busno + 1) && dev == 0) {
+ old = readl(priv->axi_base + where);
+ value = pci_conv_size_to_32(old, value, offset, size);
+ writel(value, priv->axi_base + where);
+ return 0;
+ }
+
+ return 0;
+}
+
+static int rockchip_pcie_atr_init(struct rockchip_pcie *priv)
+{
+ struct udevice *ctlr = pci_get_controller(priv->dev);
+ struct pci_controller *hose = dev_get_uclass_priv(ctlr);
+ u64 addr, size, offset;
+ u32 type;
+ int i, region;
+
+ /* Use region 0 to map PCI configuration space. */
+ writel(25 - 1, priv->apb_base + PCIE_ATR_OB_ADDR0(0));
+ writel(0, priv->apb_base + PCIE_ATR_OB_ADDR1(0));
+ writel(PCIE_ATR_HDR_CFG_TYPE0 | PCIE_ATR_HDR_RID,
+ priv->apb_base + PCIE_ATR_OB_DESC0(0));
+ writel(0, priv->apb_base + PCIE_ATR_OB_DESC1(0));
+
+ for (i = 0; i < hose->region_count; i++) {
+ if (hose->regions[i].flags == PCI_REGION_SYS_MEMORY)
+ continue;
+
+ if (hose->regions[i].flags == PCI_REGION_IO)
+ type = PCIE_ATR_HDR_IO;
+ else
+ type = PCIE_ATR_HDR_MEM;
+
+ /* Only support identity mappings. */
+ if (hose->regions[i].bus_start !=
+ hose->regions[i].phys_start)
+ return -EINVAL;
+
+ /* Only support mappings aligned on a region boundary. */
+ addr = hose->regions[i].bus_start;
+ if (addr & (PCIE_ATR_OB_REGION_SIZE - 1))
+ return -EINVAL;
+
+ /* Mappings should lie between AXI and APB regions. */
+ size = hose->regions[i].size;
+ if (addr < (u64)priv->axi_base + PCIE_ATR_OB_REGION0_SIZE)
+ return -EINVAL;
+ if (addr + size > (u64)priv->apb_base)
+ return -EINVAL;
+
+ offset = addr - (u64)priv->axi_base - PCIE_ATR_OB_REGION0_SIZE;
+ region = 1 + (offset / PCIE_ATR_OB_REGION_SIZE);
+ while (size > 0) {
+ writel(32 - 1,
+ priv->apb_base + PCIE_ATR_OB_ADDR0(region));
+ writel(0, priv->apb_base + PCIE_ATR_OB_ADDR1(region));
+ writel(type | PCIE_ATR_HDR_RID,
+ priv->apb_base + PCIE_ATR_OB_DESC0(region));
+ writel(0, priv->apb_base + PCIE_ATR_OB_DESC1(region));
+
+ addr += PCIE_ATR_OB_REGION_SIZE;
+ size -= PCIE_ATR_OB_REGION_SIZE;
+ region++;
+ }
+ }
+
+ /* Passthrough inbound translations unmodified. */
+ writel(32 - 1, priv->apb_base + PCIE_ATR_IB_ADDR0(2));
+ writel(0, priv->apb_base + PCIE_ATR_IB_ADDR1(2));
+
+ return 0;
+}
+
+static int rockchip_pcie_init_port(struct udevice *dev)
+{
+ struct rockchip_pcie *priv = dev_get_priv(dev);
+ struct rockchip_pcie_phy *phy = pcie_get_phy(priv);
+ struct rockchip_pcie_phy_ops *ops = phy_get_ops(phy);
+ u32 cr, val, status;
+ int ret;
+
+ if (dm_gpio_is_valid(&priv->ep_gpio))
+ dm_gpio_set_value(&priv->ep_gpio, 0);
+
+ ret = reset_assert(&priv->aclk_rst);
+ if (ret) {
+ dev_err(dev, "failed to assert aclk reset (ret=%d)\n", ret);
+ return ret;
+ }
+
+ ret = reset_assert(&priv->pclk_rst);
+ if (ret) {
+ dev_err(dev, "failed to assert pclk reset (ret=%d)\n", ret);
+ return ret;
+ }
+
+ ret = reset_assert(&priv->pm_rst);
+ if (ret) {
+ dev_err(dev, "failed to assert pm reset (ret=%d)\n", ret);
+ return ret;
+ }
+
+ ret = ops->init(phy);
+ if (ret) {
+ dev_err(dev, "failed to init phy (ret=%d)\n", ret);
+ goto err_exit_phy;
+ }
+
+ ret = reset_assert(&priv->core_rst);
+ if (ret) {
+ dev_err(dev, "failed to assert core reset (ret=%d)\n", ret);
+ goto err_exit_phy;
+ }
+
+ ret = reset_assert(&priv->mgmt_rst);
+ if (ret) {
+ dev_err(dev, "failed to assert mgmt reset (ret=%d)\n", ret);
+ goto err_exit_phy;
+ }
+
+ ret = reset_assert(&priv->mgmt_sticky_rst);
+ if (ret) {
+ dev_err(dev, "failed to assert mgmt-sticky reset (ret=%d)\n",
+ ret);
+ goto err_exit_phy;
+ }
+
+ ret = reset_assert(&priv->pipe_rst);
+ if (ret) {
+ dev_err(dev, "failed to assert pipe reset (ret=%d)\n", ret);
+ goto err_exit_phy;
+ }
+
+ udelay(10);
+
+ ret = reset_deassert(&priv->pm_rst);
+ if (ret) {
+ dev_err(dev, "failed to deassert pm reset (ret=%d)\n", ret);
+ goto err_exit_phy;
+ }
+
+ ret = reset_deassert(&priv->aclk_rst);
+ if (ret) {
+ dev_err(dev, "failed to deassert aclk reset (ret=%d)\n", ret);
+ goto err_exit_phy;
+ }
+
+ ret = reset_deassert(&priv->pclk_rst);
+ if (ret) {
+ dev_err(dev, "failed to deassert pclk reset (ret=%d)\n", ret);
+ goto err_exit_phy;
+ }
+
+ /* Select GEN1 for now */
+ cr = PCIE_CLIENT_GEN_SEL_1;
+ /* Set Root complex mode */
+ cr |= PCIE_CLIENT_CONF_ENABLE | PCIE_CLIENT_MODE_RC;
+ writel(cr, priv->apb_base + PCIE_CLIENT_CONFIG);
+
+ ret = ops->power_on(phy);
+ if (ret) {
+ dev_err(dev, "failed to power on phy (ret=%d)\n", ret);
+ goto err_power_off_phy;
+ }
+
+ ret = reset_deassert(&priv->mgmt_sticky_rst);
+ if (ret) {
+ dev_err(dev, "failed to deassert mgmt-sticky reset (ret=%d)\n",
+ ret);
+ goto err_power_off_phy;
+ }
+
+ ret = reset_deassert(&priv->core_rst);
+ if (ret) {
+ dev_err(dev, "failed to deassert core reset (ret=%d)\n", ret);
+ goto err_power_off_phy;
+ }
+
+ ret = reset_deassert(&priv->mgmt_rst);
+ if (ret) {
+ dev_err(dev, "failed to deassert mgmt reset (ret=%d)\n", ret);
+ goto err_power_off_phy;
+ }
+
+ ret = reset_deassert(&priv->pipe_rst);
+ if (ret) {
+ dev_err(dev, "failed to deassert pipe reset (ret=%d)\n", ret);
+ goto err_power_off_phy;
+ }
+
+ /* Enable Gen1 training */
+ writel(PCIE_CLIENT_LINK_TRAIN_ENABLE,
+ priv->apb_base + PCIE_CLIENT_CONFIG);
+
+ if (dm_gpio_is_valid(&priv->ep_gpio))
+ dm_gpio_set_value(&priv->ep_gpio, 1);
+
+ ret = readl_poll_sleep_timeout
+ (priv->apb_base + PCIE_CLIENT_BASIC_STATUS1,
+ status, PCIE_LINK_UP(status), 20, 500 * 1000);
+ if (ret) {
+ dev_err(dev, "PCIe link training gen1 timeout!\n");
+ goto err_power_off_phy;
+ }
+
+ /* Initialize Root Complex registers. */
+ writel(PCIE_LM_VENDOR_ROCKCHIP, priv->apb_base + PCIE_LM_VENDOR_ID);
+ writel(PCI_CLASS_BRIDGE_PCI << 16,
+ priv->apb_base + PCIE_RC_BASE + PCI_CLASS_REVISION);
+ writel(PCIE_LM_RCBARPIE | PCIE_LM_RCBARPIS,
+ priv->apb_base + PCIE_LM_RCBAR);
+
+ if (dev_read_bool(dev, "aspm-no-l0s")) {
+ val = readl(priv->apb_base + PCIE_RC_PCIE_LCAP);
+ val &= ~PCIE_RC_PCIE_LCAP_APMS_L0S;
+ writel(val, priv->apb_base + PCIE_RC_PCIE_LCAP);
+ }
+
+ /* Configure Address Translation. */
+ ret = rockchip_pcie_atr_init(priv);
+ if (ret) {
+ dev_err(dev, "PCIE-%d: ATR init failed\n", dev->seq);
+ goto err_power_off_phy;
+ }
+
+ return 0;
+
+err_power_off_phy:
+ ops->power_off(phy);
+err_exit_phy:
+ ops->exit(phy);
+ return ret;
+}
+
+static int rockchip_pcie_set_vpcie(struct udevice *dev)
+{
+ struct rockchip_pcie *priv = dev_get_priv(dev);
+ int ret;
+
+ if (!IS_ERR(priv->vpcie3v3)) {
+ ret = regulator_set_enable(priv->vpcie3v3, true);
+ if (ret) {
+ dev_err(dev, "failed to enable vpcie3v3 (ret=%d)\n",
+ ret);
+ return ret;
+ }
+ }
+
+ ret = regulator_set_enable(priv->vpcie1v8, true);
+ if (ret) {
+ dev_err(dev, "failed to enable vpcie1v8 (ret=%d)\n", ret);
+ goto err_disable_3v3;
+ }
+
+ ret = regulator_set_enable(priv->vpcie0v9, true);
+ if (ret) {
+ dev_err(dev, "failed to enable vpcie0v9 (ret=%d)\n", ret);
+ goto err_disable_1v8;
+ }
+
+ return 0;
+
+err_disable_1v8:
+ regulator_set_enable(priv->vpcie1v8, false);
+err_disable_3v3:
+ if (!IS_ERR(priv->vpcie3v3))
+ regulator_set_enable(priv->vpcie3v3, false);
+ return ret;
+}
+
+static int rockchip_pcie_parse_dt(struct udevice *dev)
+{
+ struct rockchip_pcie *priv = dev_get_priv(dev);
+ int ret;
+
+ priv->axi_base = dev_read_addr_name(dev, "axi-base");
+ if (!priv->axi_base)
+ return -ENODEV;
+
+ priv->apb_base = dev_read_addr_name(dev, "apb-base");
+ if (!priv->axi_base)
+ return -ENODEV;
+
+ ret = gpio_request_by_name(dev, "ep-gpios", 0,
+ &priv->ep_gpio, GPIOD_IS_OUT);
+ if (ret) {
+ dev_err(dev, "failed to find ep-gpios property\n");
+ return ret;
+ }
+
+ ret = reset_get_by_name(dev, "core", &priv->core_rst);
+ if (ret) {
+ dev_err(dev, "failed to get core reset (ret=%d)\n", ret);
+ return ret;
+ }
+
+ ret = reset_get_by_name(dev, "mgmt", &priv->mgmt_rst);
+ if (ret) {
+ dev_err(dev, "failed to get mgmt reset (ret=%d)\n", ret);
+ return ret;
+ }
+
+ ret = reset_get_by_name(dev, "mgmt-sticky", &priv->mgmt_sticky_rst);
+ if (ret) {
+ dev_err(dev, "failed to get mgmt-sticky reset (ret=%d)\n", ret);
+ return ret;
+ }
+
+ ret = reset_get_by_name(dev, "pipe", &priv->pipe_rst);
+ if (ret) {
+ dev_err(dev, "failed to get pipe reset (ret=%d)\n", ret);
+ return ret;
+ }
+
+ ret = reset_get_by_name(dev, "pm", &priv->pm_rst);
+ if (ret) {
+ dev_err(dev, "failed to get pm reset (ret=%d)\n", ret);
+ return ret;
+ }
+
+ ret = reset_get_by_name(dev, "pclk", &priv->pclk_rst);
+ if (ret) {
+ dev_err(dev, "failed to get pclk reset (ret=%d)\n", ret);
+ return ret;
+ }
+
+ ret = reset_get_by_name(dev, "aclk", &priv->aclk_rst);
+ if (ret) {
+ dev_err(dev, "failed to get aclk reset (ret=%d)\n", ret);
+ return ret;
+ }
+
+ ret = device_get_supply_regulator(dev, "vpcie3v3-supply",
+ &priv->vpcie3v3);
+ if (ret && ret != -ENOENT) {
+ dev_err(dev, "failed to get vpcie3v3 supply (ret=%d)\n", ret);
+ return ret;
+ }
+
+ ret = device_get_supply_regulator(dev, "vpcie1v8-supply",
+ &priv->vpcie1v8);
+ if (ret) {
+ dev_err(dev, "failed to get vpcie1v8 supply (ret=%d)\n", ret);
+ return ret;
+ }
+
+ ret = device_get_supply_regulator(dev, "vpcie0v9-supply",
+ &priv->vpcie0v9);
+ if (ret) {
+ dev_err(dev, "failed to get vpcie0v9 supply (ret=%d)\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int rockchip_pcie_probe(struct udevice *dev)
+{
+ struct rockchip_pcie *priv = dev_get_priv(dev);
+ struct udevice *ctlr = pci_get_controller(dev);
+ struct pci_controller *hose = dev_get_uclass_priv(ctlr);
+ int ret;
+
+ priv->first_busno = dev->seq;
+ priv->dev = dev;
+
+ ret = rockchip_pcie_parse_dt(dev);
+ if (ret)
+ return ret;
+
+ ret = rockchip_pcie_phy_get(dev);
+ if (ret)
+ return ret;
+
+ ret = rockchip_pcie_set_vpcie(dev);
+ if (ret)
+ return ret;
+
+ ret = rockchip_pcie_init_port(dev);
+ if (ret)
+ return ret;
+
+ dev_info(dev, "PCIE-%d: Link up (Bus%d)\n",
+ dev->seq, hose->first_busno);
+
+ return 0;
+}
+
+static const struct dm_pci_ops rockchip_pcie_ops = {
+ .read_config = rockchip_pcie_rd_conf,
+ .write_config = rockchip_pcie_wr_conf,
+};
+
+static const struct udevice_id rockchip_pcie_ids[] = {
+ { .compatible = "rockchip,rk3399-pcie" },
+ { }
+};
+
+U_BOOT_DRIVER(rockchip_pcie) = {
+ .name = "rockchip_pcie",
+ .id = UCLASS_PCI,
+ .of_match = rockchip_pcie_ids,
+ .ops = &rockchip_pcie_ops,
+ .probe = rockchip_pcie_probe,
+ .priv_auto_alloc_size = sizeof(struct rockchip_pcie),
+};
diff --git a/drivers/pci/pcie_rockchip.h b/drivers/pci/pcie_rockchip.h
new file mode 100644
index 00000000000..c3a0a2846d4
--- /dev/null
+++ b/drivers/pci/pcie_rockchip.h
@@ -0,0 +1,142 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Rockchip PCIe Headers
+ *
+ * Copyright (c) 2016 Rockchip, Inc.
+ * Copyright (c) 2020 Amarula Solutions(India)
+ * Copyright (c) 2020 Jagan Teki <jagan@amarulasolutions.com>
+ * Copyright (c) 2019 Patrick Wildt <patrick@blueri.se>
+ *
+ */
+
+#define HIWORD_UPDATE(mask, val) (((mask) << 16) | (val))
+#define HIWORD_UPDATE_BIT(val) HIWORD_UPDATE(val, val)
+
+#define ENCODE_LANES(x) ((((x) >> 1) & 3) << 4)
+#define PCIE_CLIENT_BASE 0x0
+#define PCIE_CLIENT_CONFIG (PCIE_CLIENT_BASE + 0x00)
+#define PCIE_CLIENT_CONF_ENABLE HIWORD_UPDATE_BIT(0x0001)
+#define PCIE_CLIENT_LINK_TRAIN_ENABLE HIWORD_UPDATE_BIT(0x0002)
+#define PCIE_CLIENT_MODE_RC HIWORD_UPDATE_BIT(0x0040)
+#define PCIE_CLIENT_GEN_SEL_1 HIWORD_UPDATE(0x0080, 0)
+#define PCIE_CLIENT_BASIC_STATUS1 0x0048
+#define PCIE_CLIENT_LINK_STATUS_UP GENMASK(21, 20)
+#define PCIE_CLIENT_LINK_STATUS_MASK GENMASK(21, 20)
+#define PCIE_LINK_UP(x) \
+ (((x) & PCIE_CLIENT_LINK_STATUS_MASK) == PCIE_CLIENT_LINK_STATUS_UP)
+#define PCIE_RC_NORMAL_BASE 0x800000
+#define PCIE_LM_BASE 0x900000
+#define PCIE_LM_VENDOR_ID (PCIE_LM_BASE + 0x44)
+#define PCIE_LM_VENDOR_ROCKCHIP 0x1d87
+#define PCIE_LM_RCBAR (PCIE_LM_BASE + 0x300)
+#define PCIE_LM_RCBARPIE BIT(19)
+#define PCIE_LM_RCBARPIS BIT(20)
+#define PCIE_RC_BASE 0xa00000
+#define PCIE_RC_CONFIG_DCR (PCIE_RC_BASE + 0x0c4)
+#define PCIE_RC_CONFIG_DCR_CSPL_SHIFT 18
+#define PCIE_RC_CONFIG_DCR_CPLS_SHIFT 26
+#define PCIE_RC_PCIE_LCAP (PCIE_RC_BASE + 0x0cc)
+#define PCIE_RC_PCIE_LCAP_APMS_L0S BIT(10)
+#define PCIE_ATR_BASE 0xc00000
+#define PCIE_ATR_OB_ADDR0(i) (PCIE_ATR_BASE + 0x000 + (i) * 0x20)
+#define PCIE_ATR_OB_ADDR1(i) (PCIE_ATR_BASE + 0x004 + (i) * 0x20)
+#define PCIE_ATR_OB_DESC0(i) (PCIE_ATR_BASE + 0x008 + (i) * 0x20)
+#define PCIE_ATR_OB_DESC1(i) (PCIE_ATR_BASE + 0x00c + (i) * 0x20)
+#define PCIE_ATR_IB_ADDR0(i) (PCIE_ATR_BASE + 0x800 + (i) * 0x8)
+#define PCIE_ATR_IB_ADDR1(i) (PCIE_ATR_BASE + 0x804 + (i) * 0x8)
+#define PCIE_ATR_HDR_MEM 0x2
+#define PCIE_ATR_HDR_IO 0x6
+#define PCIE_ATR_HDR_CFG_TYPE0 0xa
+#define PCIE_ATR_HDR_CFG_TYPE1 0xb
+#define PCIE_ATR_HDR_RID BIT(23)
+
+#define PCIE_ATR_OB_REGION0_SIZE (32 * 1024 * 1024)
+#define PCIE_ATR_OB_REGION_SIZE (1 * 1024 * 1024)
+
+/*
+ * The higher 16-bit of this register is used for write protection
+ * only if BIT(x + 16) set to 1 the BIT(x) can be written.
+ */
+#define HIWORD_UPDATE_MASK(val, mask, shift) \
+ ((val) << (shift) | (mask) << ((shift) + 16))
+
+#define PHY_CFG_DATA_SHIFT 7
+#define PHY_CFG_ADDR_SHIFT 1
+#define PHY_CFG_DATA_MASK 0xf
+#define PHY_CFG_ADDR_MASK 0x3f
+#define PHY_CFG_RD_MASK 0x3ff
+#define PHY_CFG_WR_ENABLE 1
+#define PHY_CFG_WR_DISABLE 1
+#define PHY_CFG_WR_SHIFT 0
+#define PHY_CFG_WR_MASK 1
+#define PHY_CFG_PLL_LOCK 0x10
+#define PHY_CFG_CLK_TEST 0x10
+#define PHY_CFG_CLK_SCC 0x12
+#define PHY_CFG_SEPE_RATE BIT(3)
+#define PHY_CFG_PLL_100M BIT(3)
+#define PHY_PLL_LOCKED BIT(9)
+#define PHY_PLL_OUTPUT BIT(10)
+#define PHY_LANE_IDLE_OFF 0x1
+#define PHY_LANE_IDLE_MASK 0x1
+#define PHY_LANE_IDLE_A_SHIFT 3
+#define PHY_LANE_IDLE_B_SHIFT 4
+#define PHY_LANE_IDLE_C_SHIFT 5
+#define PHY_LANE_IDLE_D_SHIFT 6
+
+#define PCIE_PHY_CONF 0xe220
+#define PCIE_PHY_STATUS 0xe2a4
+#define PCIE_PHY_LANEOFF 0xe214
+
+struct rockchip_pcie_phy {
+ void *reg_base;
+ struct clk refclk;
+ struct reset_ctl phy_rst;
+ struct rockchip_pcie_phy_ops *ops;
+};
+
+struct rockchip_pcie_phy_ops {
+ int (*init)(struct rockchip_pcie_phy *phy);
+ int (*exit)(struct rockchip_pcie_phy *phy);
+ int (*power_on)(struct rockchip_pcie_phy *phy);
+ int (*power_off)(struct rockchip_pcie_phy *phy);
+};
+
+struct rockchip_pcie {
+ fdt_addr_t axi_base;
+ fdt_addr_t apb_base;
+ int first_busno;
+ struct udevice *dev;
+ struct rockchip_pcie_phy rk_phy;
+ struct rockchip_pcie_phy *phy;
+
+ /* resets */
+ struct reset_ctl core_rst;
+ struct reset_ctl mgmt_rst;
+ struct reset_ctl mgmt_sticky_rst;
+ struct reset_ctl pipe_rst;
+ struct reset_ctl pm_rst;
+ struct reset_ctl pclk_rst;
+ struct reset_ctl aclk_rst;
+
+ /* gpio */
+ struct gpio_desc ep_gpio;
+
+ /* vpcie regulators */
+ struct udevice *vpcie12v;
+ struct udevice *vpcie3v3;
+ struct udevice *vpcie1v8;
+ struct udevice *vpcie0v9;
+};
+
+int rockchip_pcie_phy_get(struct udevice *dev);
+
+inline struct rockchip_pcie_phy *pcie_get_phy(struct rockchip_pcie *pcie)
+{
+ return pcie->phy;
+}
+
+inline
+struct rockchip_pcie_phy_ops *phy_get_ops(struct rockchip_pcie_phy *phy)
+{
+ return (struct rockchip_pcie_phy_ops *)phy->ops;
+}
diff --git a/drivers/pci/pcie_rockchip_phy.c b/drivers/pci/pcie_rockchip_phy.c
new file mode 100644
index 00000000000..47f5d6c7e32
--- /dev/null
+++ b/drivers/pci/pcie_rockchip_phy.c
@@ -0,0 +1,205 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Rockchip PCIe PHY driver
+ *
+ * Copyright (c) 2016 Rockchip, Inc.
+ * Copyright (c) 2020 Amarula Solutions(India)
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <reset.h>
+#include <syscon.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <linux/iopoll.h>
+#include <asm/arch-rockchip/clock.h>
+
+#include "pcie_rockchip.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void phy_wr_cfg(struct rockchip_pcie_phy *phy, u32 addr, u32 data)
+{
+ u32 reg;
+
+ reg = HIWORD_UPDATE_MASK(data, PHY_CFG_DATA_MASK, PHY_CFG_DATA_SHIFT);
+ reg |= HIWORD_UPDATE_MASK(addr, PHY_CFG_ADDR_MASK, PHY_CFG_ADDR_SHIFT);
+ writel(reg, phy->reg_base + PCIE_PHY_CONF);
+
+ udelay(1);
+
+ reg = HIWORD_UPDATE_MASK(PHY_CFG_WR_ENABLE,
+ PHY_CFG_WR_MASK,
+ PHY_CFG_WR_SHIFT);
+ writel(reg, phy->reg_base + PCIE_PHY_CONF);
+
+ udelay(1);
+
+ reg = HIWORD_UPDATE_MASK(PHY_CFG_WR_DISABLE,
+ PHY_CFG_WR_MASK,
+ PHY_CFG_WR_SHIFT);
+ writel(reg, phy->reg_base + PCIE_PHY_CONF);
+}
+
+static int rockchip_pcie_phy_power_on(struct rockchip_pcie_phy *phy)
+{
+ int ret = 0;
+ u32 reg, status;
+
+ ret = reset_deassert(&phy->phy_rst);
+ if (ret) {
+ dev_err(dev, "failed to assert phy reset\n");
+ return ret;
+ }
+
+ reg = HIWORD_UPDATE_MASK(PHY_CFG_PLL_LOCK,
+ PHY_CFG_ADDR_MASK,
+ PHY_CFG_ADDR_SHIFT);
+ writel(reg, phy->reg_base + PCIE_PHY_CONF);
+
+ reg = HIWORD_UPDATE_MASK(!PHY_LANE_IDLE_OFF,
+ PHY_LANE_IDLE_MASK,
+ PHY_LANE_IDLE_A_SHIFT);
+ writel(reg, phy->reg_base + PCIE_PHY_LANEOFF);
+
+ ret = -EINVAL;
+ ret = readl_poll_sleep_timeout(phy->reg_base + PCIE_PHY_STATUS,
+ status,
+ status & PHY_PLL_LOCKED,
+ 20 * 1000,
+ 50);
+ if (ret) {
+ dev_err(&phy->dev, "pll lock timeout!\n");
+ goto err_pll_lock;
+ }
+
+ phy_wr_cfg(phy, PHY_CFG_CLK_TEST, PHY_CFG_SEPE_RATE);
+ phy_wr_cfg(phy, PHY_CFG_CLK_SCC, PHY_CFG_PLL_100M);
+
+ ret = -ETIMEDOUT;
+ ret = readl_poll_sleep_timeout(phy->reg_base + PCIE_PHY_STATUS,
+ status,
+ !(status & PHY_PLL_OUTPUT),
+ 20 * 1000,
+ 50);
+ if (ret) {
+ dev_err(&phy->dev, "pll output enable timeout!\n");
+ goto err_pll_lock;
+ }
+
+ reg = HIWORD_UPDATE_MASK(PHY_CFG_PLL_LOCK,
+ PHY_CFG_ADDR_MASK,
+ PHY_CFG_ADDR_SHIFT);
+ writel(reg, phy->reg_base + PCIE_PHY_CONF);
+
+ ret = -EINVAL;
+ ret = readl_poll_sleep_timeout(phy->reg_base + PCIE_PHY_STATUS,
+ status,
+ status & PHY_PLL_LOCKED,
+ 20 * 1000,
+ 50);
+ if (ret) {
+ dev_err(&phy->dev, "pll relock timeout!\n");
+ goto err_pll_lock;
+ }
+
+ return 0;
+
+err_pll_lock:
+ reset_assert(&phy->phy_rst);
+ return ret;
+}
+
+static int rockchip_pcie_phy_power_off(struct rockchip_pcie_phy *phy)
+{
+ int ret;
+ u32 reg;
+
+ reg = HIWORD_UPDATE_MASK(PHY_LANE_IDLE_OFF,
+ PHY_LANE_IDLE_MASK,
+ PHY_LANE_IDLE_A_SHIFT);
+ writel(reg, phy->reg_base + PCIE_PHY_LANEOFF);
+
+ ret = reset_assert(&phy->phy_rst);
+ if (ret) {
+ dev_err(dev, "failed to assert phy reset\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int rockchip_pcie_phy_init(struct rockchip_pcie_phy *phy)
+{
+ int ret;
+
+ ret = clk_enable(&phy->refclk);
+ if (ret) {
+ dev_err(dev, "failed to enable refclk clock\n");
+ return ret;
+ }
+
+ ret = reset_assert(&phy->phy_rst);
+ if (ret) {
+ dev_err(dev, "failed to assert phy reset\n");
+ goto err_reset;
+ }
+
+ return 0;
+
+err_reset:
+ clk_disable(&phy->refclk);
+ return ret;
+}
+
+static int rockchip_pcie_phy_exit(struct rockchip_pcie_phy *phy)
+{
+ clk_disable(&phy->refclk);
+
+ return 0;
+}
+
+static struct rockchip_pcie_phy_ops pcie_phy_ops = {
+ .init = rockchip_pcie_phy_init,
+ .power_on = rockchip_pcie_phy_power_on,
+ .power_off = rockchip_pcie_phy_power_off,
+ .exit = rockchip_pcie_phy_exit,
+};
+
+int rockchip_pcie_phy_get(struct udevice *dev)
+{
+ struct rockchip_pcie *priv = dev_get_priv(dev);
+ struct rockchip_pcie_phy *phy_priv = &priv->rk_phy;
+ ofnode phy_node;
+ u32 phandle;
+ int ret;
+
+ phandle = dev_read_u32_default(dev, "phys", 0);
+ phy_node = ofnode_get_by_phandle(phandle);
+ if (!ofnode_valid(phy_node)) {
+ dev_err(dev, "failed to found pcie-phy\n");
+ return -ENODEV;
+ }
+
+ phy_priv->reg_base = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+
+ ret = clk_get_by_index_nodev(phy_node, 0, &phy_priv->refclk);
+ if (ret) {
+ dev_err(dev, "failed to get refclk clock phandle\n");
+ return ret;
+ }
+
+ ret = reset_get_by_index_nodev(phy_node, 0, &phy_priv->phy_rst);
+ if (ret) {
+ dev_err(dev, "failed to get phy reset phandle\n");
+ return ret;
+ }
+
+ phy_priv->ops = &pcie_phy_ops;
+ priv->phy = phy_priv;
+
+ return 0;
+}
diff --git a/drivers/thermal/imx_scu_thermal.c b/drivers/thermal/imx_scu_thermal.c
index 321f905e3ac..83ec753802a 100644
--- a/drivers/thermal/imx_scu_thermal.c
+++ b/drivers/thermal/imx_scu_thermal.c
@@ -61,13 +61,15 @@ int imx_sc_thermal_get_temp(struct udevice *dev, int *temp)
return ret;
while (cpu_temp >= pdata->alert) {
- printf("CPU Temperature (%dC) has beyond alert (%dC), close to critical (%dC)",
+ printf("CPU Temperature (%dC) beyond alert (%dC), close to critical (%dC)",
cpu_temp, pdata->alert, pdata->critical);
puts(" waiting...\n");
mdelay(pdata->polling_delay);
ret = read_temperature(dev, &cpu_temp);
if (ret)
return ret;
+ if (cpu_temp >= pdata->alert && !pdata->alert)
+ break;
}
*temp = cpu_temp / 1000;
generated by cgit v1.2.3 (git 2.0.4) at 2025-08-03 20:22:48 +0000