diff options
Diffstat (limited to 'drivers')
31 files changed, 1731 insertions, 630 deletions
diff --git a/drivers/clk/exynos/clk-exynos850.c b/drivers/clk/exynos/clk-exynos850.c index cf94a3e1b64..0c09ba02de4 100644 --- a/drivers/clk/exynos/clk-exynos850.c +++ b/drivers/clk/exynos/clk-exynos850.c @@ -10,6 +10,13 @@ #include <dt-bindings/clock/exynos850.h> #include "clk.h" +enum exynos850_cmu_id { + CMU_TOP, + CMU_PERI, + CMU_CORE, + CMU_HSI, +}; + /* ---- CMU_TOP ------------------------------------------------------------- */ /* Register Offset definitions for CMU_TOP (0x120e0000) */ @@ -19,9 +26,23 @@ #define PLL_CON3_PLL_SHARED0 0x014c #define PLL_CON0_PLL_SHARED1 0x0180 #define PLL_CON3_PLL_SHARED1 0x018c +#define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1014 +#define CLK_CON_MUX_MUX_CLKCMU_CORE_CCI 0x1018 +#define CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD 0x101c +#define CLK_CON_MUX_MUX_CLKCMU_CORE_SSS 0x1020 +#define CLK_CON_MUX_MUX_CLKCMU_HSI_BUS 0x103c +#define CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD 0x1040 +#define CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD 0x1044 #define CLK_CON_MUX_MUX_CLKCMU_PERI_BUS 0x1070 #define CLK_CON_MUX_MUX_CLKCMU_PERI_IP 0x1074 #define CLK_CON_MUX_MUX_CLKCMU_PERI_UART 0x1078 +#define CLK_CON_DIV_CLKCMU_CORE_BUS 0x1820 +#define CLK_CON_DIV_CLKCMU_CORE_CCI 0x1824 +#define CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD 0x1828 +#define CLK_CON_DIV_CLKCMU_CORE_SSS 0x182c +#define CLK_CON_DIV_CLKCMU_HSI_BUS 0x1848 +#define CLK_CON_DIV_CLKCMU_HSI_MMC_CARD 0x184c +#define CLK_CON_DIV_CLKCMU_HSI_USB20DRD 0x1850 #define CLK_CON_DIV_CLKCMU_PERI_BUS 0x187c #define CLK_CON_DIV_CLKCMU_PERI_IP 0x1880 #define CLK_CON_DIV_CLKCMU_PERI_UART 0x1884 @@ -31,23 +52,40 @@ #define CLK_CON_DIV_PLL_SHARED1_DIV2 0x1898 #define CLK_CON_DIV_PLL_SHARED1_DIV3 0x189c #define CLK_CON_DIV_PLL_SHARED1_DIV4 0x18a0 +#define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x201c +#define CLK_CON_GAT_GATE_CLKCMU_CORE_CCI 0x2020 +#define CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD 0x2024 +#define CLK_CON_GAT_GATE_CLKCMU_CORE_SSS 0x2028 +#define CLK_CON_GAT_GATE_CLKCMU_HSI_BUS 0x2044 +#define CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD 0x2048 +#define CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD 0x204c #define CLK_CON_GAT_GATE_CLKCMU_PERI_BUS 0x2080 #define CLK_CON_GAT_GATE_CLKCMU_PERI_IP 0x2084 #define CLK_CON_GAT_GATE_CLKCMU_PERI_UART 0x2088 -static const struct samsung_pll_clock top_pure_pll_clks[] = { - PLL(pll_0822x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "clock-oscclk", - PLL_CON3_PLL_SHARED0), - PLL(pll_0822x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "clock-oscclk", - PLL_CON3_PLL_SHARED1), - PLL(pll_0831x, CLK_FOUT_MMC_PLL, "fout_mmc_pll", "clock-oscclk", - PLL_CON3_PLL_MMC), -}; - -/* List of parent clocks for Muxes in CMU_TOP */ +/* List of parent clocks for Muxes in CMU_TOP: for PURECLKCOMP */ PNAME(mout_shared0_pll_p) = { "clock-oscclk", "fout_shared0_pll" }; PNAME(mout_shared1_pll_p) = { "clock-oscclk", "fout_shared1_pll" }; PNAME(mout_mmc_pll_p) = { "clock-oscclk", "fout_mmc_pll" }; +/* List of parent clocks for Muxes in CMU_TOP: for CMU_CORE */ +PNAME(mout_core_bus_p) = { "dout_shared1_div2", "dout_shared0_div3", + "dout_shared1_div3", "dout_shared0_div4" }; +PNAME(mout_core_cci_p) = { "dout_shared0_div2", "dout_shared1_div2", + "dout_shared0_div3", "dout_shared1_div3" }; +PNAME(mout_core_mmc_embd_p) = { "clock-oscclk", "dout_shared0_div2", + "dout_shared1_div2", "dout_shared0_div3", + "dout_shared1_div3", "mout_mmc_pll", + "clock-oscclk", "clock-oscclk" }; +PNAME(mout_core_sss_p) = { "dout_shared0_div3", "dout_shared1_div3", + "dout_shared0_div4", "dout_shared1_div4" }; +/* List of parent clocks for Muxes in CMU_TOP: for CMU_HSI */ +PNAME(mout_hsi_bus_p) = { "dout_shared0_div2", "dout_shared1_div2" }; +PNAME(mout_hsi_mmc_card_p) = { "clock-oscclk", "dout_shared0_div2", + "dout_shared1_div2", "dout_shared0_div3", + "dout_shared1_div3", "mout_mmc_pll", + "clock-oscclk", "clock-oscclk" }; +PNAME(mout_hsi_usb20drd_p) = { "clock-oscclk", "dout_shared0_div4", + "dout_shared1_div4", "clock-oscclk" }; /* List of parent clocks for Muxes in CMU_TOP: for CMU_PERI */ PNAME(mout_peri_bus_p) = { "dout_shared0_div4", "dout_shared1_div4" }; PNAME(mout_peri_uart_p) = { "clock-oscclk", "dout_shared0_div4", @@ -55,6 +93,17 @@ PNAME(mout_peri_uart_p) = { "clock-oscclk", "dout_shared0_div4", PNAME(mout_peri_ip_p) = { "clock-oscclk", "dout_shared0_div4", "dout_shared1_div4", "clock-oscclk" }; +/* PURECLKCOMP */ + +static const struct samsung_pll_clock top_pure_pll_clks[] = { + PLL(pll_0822x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "clock-oscclk", + PLL_CON3_PLL_SHARED0), + PLL(pll_0822x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "clock-oscclk", + PLL_CON3_PLL_SHARED1), + PLL(pll_0831x, CLK_FOUT_MMC_PLL, "fout_mmc_pll", "clock-oscclk", + PLL_CON3_PLL_MMC), +}; + static const struct samsung_mux_clock top_pure_mux_clks[] = { MUX(CLK_MOUT_SHARED0_PLL, "mout_shared0_pll", mout_shared0_pll_p, PLL_CON0_PLL_SHARED0, 4, 1), @@ -64,15 +113,6 @@ static const struct samsung_mux_clock top_pure_mux_clks[] = { PLL_CON0_PLL_MMC, 4, 1), }; -static const struct samsung_mux_clock top_peri_mux_clks[] = { - MUX(CLK_MOUT_PERI_BUS, "mout_peri_bus", mout_peri_bus_p, - CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, 0, 1), - MUX(CLK_MOUT_PERI_UART, "mout_peri_uart", mout_peri_uart_p, - CLK_CON_MUX_MUX_CLKCMU_PERI_UART, 0, 2), - MUX(CLK_MOUT_PERI_IP, "mout_peri_ip", mout_peri_ip_p, - CLK_CON_MUX_MUX_CLKCMU_PERI_IP, 0, 2), -}; - static const struct samsung_div_clock top_pure_div_clks[] = { DIV(CLK_DOUT_SHARED0_DIV3, "dout_shared0_div3", "mout_shared0_pll", CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2), @@ -88,13 +128,79 @@ static const struct samsung_div_clock top_pure_div_clks[] = { CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1), }; -static const struct samsung_div_clock top_peri_div_clks[] = { - DIV(CLK_DOUT_PERI_BUS, "dout_peri_bus", "gout_peri_bus", - CLK_CON_DIV_CLKCMU_PERI_BUS, 0, 4), - DIV(CLK_DOUT_PERI_UART, "dout_peri_uart", "gout_peri_uart", - CLK_CON_DIV_CLKCMU_PERI_UART, 0, 4), - DIV(CLK_DOUT_PERI_IP, "dout_peri_ip", "gout_peri_ip", - CLK_CON_DIV_CLKCMU_PERI_IP, 0, 4), +/* CORE */ + +static const struct samsung_mux_clock top_core_mux_clks[] = { + MUX(CLK_MOUT_CORE_BUS, "mout_core_bus", mout_core_bus_p, + CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2), + MUX(CLK_MOUT_CORE_CCI, "mout_core_cci", mout_core_cci_p, + CLK_CON_MUX_MUX_CLKCMU_CORE_CCI, 0, 2), + MUX(CLK_MOUT_CORE_MMC_EMBD, "mout_core_mmc_embd", mout_core_mmc_embd_p, + CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD, 0, 3), + MUX(CLK_MOUT_CORE_SSS, "mout_core_sss", mout_core_sss_p, + CLK_CON_MUX_MUX_CLKCMU_CORE_SSS, 0, 2), +}; + +static const struct samsung_gate_clock top_core_gate_clks[] = { + GATE(CLK_GOUT_CORE_BUS, "gout_core_bus", "mout_core_bus", + CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 21, 0, 0), + GATE(CLK_GOUT_CORE_CCI, "gout_core_cci", "mout_core_cci", + CLK_CON_GAT_GATE_CLKCMU_CORE_CCI, 21, 0, 0), + GATE(CLK_GOUT_CORE_MMC_EMBD, "gout_core_mmc_embd", "mout_core_mmc_embd", + CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD, 21, 0, 0), + GATE(CLK_GOUT_CORE_SSS, "gout_core_sss", "mout_core_sss", + CLK_CON_GAT_GATE_CLKCMU_CORE_SSS, 21, 0, 0), +}; + +static const struct samsung_div_clock top_core_div_clks[] = { + DIV(CLK_DOUT_CORE_BUS, "dout_core_bus", "gout_core_bus", + CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4), + DIV(CLK_DOUT_CORE_CCI, "dout_core_cci", "gout_core_cci", + CLK_CON_DIV_CLKCMU_CORE_CCI, 0, 4), + DIV(CLK_DOUT_CORE_MMC_EMBD, "dout_core_mmc_embd", "gout_core_mmc_embd", + CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD, 0, 9), + DIV(CLK_DOUT_CORE_SSS, "dout_core_sss", "gout_core_sss", + CLK_CON_DIV_CLKCMU_CORE_SSS, 0, 4), +}; + +/* HSI */ + +static const struct samsung_mux_clock top_hsi_mux_clks[] = { + MUX(CLK_MOUT_HSI_BUS, "mout_hsi_bus", mout_hsi_bus_p, + CLK_CON_MUX_MUX_CLKCMU_HSI_BUS, 0, 1), + MUX(CLK_MOUT_HSI_MMC_CARD, "mout_hsi_mmc_card", mout_hsi_mmc_card_p, + CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD, 0, 3), + MUX(CLK_MOUT_HSI_USB20DRD, "mout_hsi_usb20drd", mout_hsi_usb20drd_p, + CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD, 0, 2), +}; + +static const struct samsung_gate_clock top_hsi_gate_clks[] = { + GATE(CLK_GOUT_HSI_BUS, "gout_hsi_bus", "mout_hsi_bus", + CLK_CON_GAT_GATE_CLKCMU_HSI_BUS, 21, 0, 0), + GATE(CLK_GOUT_HSI_MMC_CARD, "gout_hsi_mmc_card", "mout_hsi_mmc_card", + CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD, 21, 0, 0), + GATE(CLK_GOUT_HSI_USB20DRD, "gout_hsi_usb20drd", "mout_hsi_usb20drd", + CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD, 21, 0, 0), +}; + +static const struct samsung_div_clock top_hsi_div_clks[] = { + DIV(CLK_DOUT_HSI_BUS, "dout_hsi_bus", "gout_hsi_bus", + CLK_CON_DIV_CLKCMU_HSI_BUS, 0, 4), + DIV(CLK_DOUT_HSI_MMC_CARD, "dout_hsi_mmc_card", "gout_hsi_mmc_card", + CLK_CON_DIV_CLKCMU_HSI_MMC_CARD, 0, 9), + DIV(CLK_DOUT_HSI_USB20DRD, "dout_hsi_usb20drd", "gout_hsi_usb20drd", + CLK_CON_DIV_CLKCMU_HSI_USB20DRD, 0, 4), +}; + +/* PERI */ + +static const struct samsung_mux_clock top_peri_mux_clks[] = { + MUX(CLK_MOUT_PERI_BUS, "mout_peri_bus", mout_peri_bus_p, + CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, 0, 1), + MUX(CLK_MOUT_PERI_UART, "mout_peri_uart", mout_peri_uart_p, + CLK_CON_MUX_MUX_CLKCMU_PERI_UART, 0, 2), + MUX(CLK_MOUT_PERI_IP, "mout_peri_ip", mout_peri_ip_p, + CLK_CON_MUX_MUX_CLKCMU_PERI_IP, 0, 2), }; static const struct samsung_gate_clock top_peri_gate_clks[] = { @@ -106,12 +212,31 @@ static const struct samsung_gate_clock top_peri_gate_clks[] = { CLK_CON_GAT_GATE_CLKCMU_PERI_IP, 21, 0, 0), }; +static const struct samsung_div_clock top_peri_div_clks[] = { + DIV(CLK_DOUT_PERI_BUS, "dout_peri_bus", "gout_peri_bus", + CLK_CON_DIV_CLKCMU_PERI_BUS, 0, 4), + DIV(CLK_DOUT_PERI_UART, "dout_peri_uart", "gout_peri_uart", + CLK_CON_DIV_CLKCMU_PERI_UART, 0, 4), + DIV(CLK_DOUT_PERI_IP, "dout_peri_ip", "gout_peri_ip", + CLK_CON_DIV_CLKCMU_PERI_IP, 0, 4), +}; + static const struct samsung_clk_group top_cmu_clks[] = { /* CMU_TOP_PURECLKCOMP */ { S_CLK_PLL, top_pure_pll_clks, ARRAY_SIZE(top_pure_pll_clks) }, { S_CLK_MUX, top_pure_mux_clks, ARRAY_SIZE(top_pure_mux_clks) }, { S_CLK_DIV, top_pure_div_clks, ARRAY_SIZE(top_pure_div_clks) }, + /* CMU_TOP clocks for CMU_CORE */ + { S_CLK_MUX, top_core_mux_clks, ARRAY_SIZE(top_core_mux_clks) }, + { S_CLK_GATE, top_core_gate_clks, ARRAY_SIZE(top_core_gate_clks) }, + { S_CLK_DIV, top_core_div_clks, ARRAY_SIZE(top_core_div_clks) }, + + /* CMU_TOP clocks for CMU_HSI */ + { S_CLK_MUX, top_hsi_mux_clks, ARRAY_SIZE(top_hsi_mux_clks) }, + { S_CLK_GATE, top_hsi_gate_clks, ARRAY_SIZE(top_hsi_gate_clks) }, + { S_CLK_DIV, top_hsi_div_clks, ARRAY_SIZE(top_hsi_div_clks) }, + /* CMU_TOP clocks for CMU_PERI */ { S_CLK_MUX, top_peri_mux_clks, ARRAY_SIZE(top_peri_mux_clks) }, { S_CLK_GATE, top_peri_gate_clks, ARRAY_SIZE(top_peri_gate_clks) }, @@ -120,7 +245,7 @@ static const struct samsung_clk_group top_cmu_clks[] = { static int exynos850_cmu_top_probe(struct udevice *dev) { - return samsung_cmu_register_one(dev, top_cmu_clks, + return samsung_cmu_register_one(dev, CMU_TOP, top_cmu_clks, ARRAY_SIZE(top_cmu_clks)); } @@ -129,11 +254,13 @@ static const struct udevice_id exynos850_cmu_top_ids[] = { { } }; +SAMSUNG_CLK_OPS(exynos850_cmu_top, CMU_TOP); + U_BOOT_DRIVER(exynos850_cmu_top) = { .name = "exynos850-cmu-top", .id = UCLASS_CLK, .of_match = exynos850_cmu_top_ids, - .ops = &ccf_clk_ops, + .ops = &exynos850_cmu_top_clk_ops, .probe = exynos850_cmu_top_probe, .flags = DM_FLAG_PRE_RELOC, }; @@ -171,7 +298,8 @@ static const struct samsung_clk_group peri_cmu_clks[] = { static int exynos850_cmu_peri_probe(struct udevice *dev) { - return samsung_register_cmu(dev, peri_cmu_clks, exynos850_cmu_top); + return samsung_register_cmu(dev, CMU_PERI, peri_cmu_clks, + exynos850_cmu_top); } static const struct udevice_id exynos850_cmu_peri_ids[] = { @@ -179,11 +307,149 @@ static const struct udevice_id exynos850_cmu_peri_ids[] = { { } }; +SAMSUNG_CLK_OPS(exynos850_cmu_peri, CMU_PERI); + U_BOOT_DRIVER(exynos850_cmu_peri) = { .name = "exynos850-cmu-peri", .id = UCLASS_CLK, .of_match = exynos850_cmu_peri_ids, - .ops = &ccf_clk_ops, + .ops = &exynos850_cmu_peri_clk_ops, .probe = exynos850_cmu_peri_probe, .flags = DM_FLAG_PRE_RELOC, }; + +/* ---- CMU_CORE ------------------------------------------------------------ */ + +/* Register Offset definitions for CMU_CORE (0x12000000) */ +#define PLL_CON0_MUX_CLKCMU_CORE_BUS_USER 0x0600 +#define PLL_CON0_MUX_CLKCMU_CORE_MMC_EMBD_USER 0x0620 +#define CLK_CON_DIV_DIV_CLK_CORE_BUSP 0x1800 +#define CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK 0x20e8 +#define CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN 0x20ec + +/* List of parent clocks for Muxes in CMU_CORE */ +PNAME(mout_core_bus_user_p) = { "clock-oscclk", "dout_core_bus" }; +PNAME(mout_core_mmc_embd_user_p) = { "clock-oscclk", + "dout_core_mmc_embd" }; + +static const struct samsung_mux_clock core_mux_clks[] = { + MUX(CLK_MOUT_CORE_BUS_USER, "mout_core_bus_user", mout_core_bus_user_p, + PLL_CON0_MUX_CLKCMU_CORE_BUS_USER, 4, 1), + MUX_F(CLK_MOUT_CORE_MMC_EMBD_USER, "mout_core_mmc_embd_user", + mout_core_mmc_embd_user_p, PLL_CON0_MUX_CLKCMU_CORE_MMC_EMBD_USER, + 4, 1, CLK_SET_RATE_PARENT, 0), +}; + +static const struct samsung_div_clock core_div_clks[] = { + DIV(CLK_DOUT_CORE_BUSP, "dout_core_busp", "mout_core_bus_user", + CLK_CON_DIV_DIV_CLK_CORE_BUSP, 0, 2), +}; + +static const struct samsung_gate_clock core_gate_clks[] = { + GATE(CLK_GOUT_MMC_EMBD_ACLK, "gout_mmc_embd_aclk", "dout_core_busp", + CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK, 21, 0, 0), + GATE(CLK_GOUT_MMC_EMBD_SDCLKIN, "gout_mmc_embd_sdclkin", + "mout_core_mmc_embd_user", CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN, + 21, CLK_SET_RATE_PARENT, 0), +}; + +static const struct samsung_clk_group core_cmu_clks[] = { + { S_CLK_MUX, core_mux_clks, ARRAY_SIZE(core_mux_clks) }, + { S_CLK_DIV, core_div_clks, ARRAY_SIZE(core_div_clks) }, + { S_CLK_GATE, core_gate_clks, ARRAY_SIZE(core_gate_clks) }, +}; + +static int exynos850_cmu_core_probe(struct udevice *dev) +{ + return samsung_register_cmu(dev, CMU_CORE, core_cmu_clks, + exynos850_cmu_top); +} + +static const struct udevice_id exynos850_cmu_core_ids[] = { + { .compatible = "samsung,exynos850-cmu-core" }, + { } +}; + +SAMSUNG_CLK_OPS(exynos850_cmu_core, CMU_CORE); + +U_BOOT_DRIVER(exynos850_cmu_core) = { + .name = "exynos850-cmu-core", + .id = UCLASS_CLK, + .of_match = exynos850_cmu_core_ids, + .ops = &exynos850_cmu_core_clk_ops, + .probe = exynos850_cmu_core_probe, + .flags = DM_FLAG_PRE_RELOC, +}; + +/* ---- CMU_HSI ------------------------------------------------------------- */ + +/* Register Offset definitions for CMU_HSI (0x13400000) */ +#define PLL_CON0_MUX_CLKCMU_HSI_BUS_USER 0x0600 +#define PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER 0x0610 +#define PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER 0x0620 +#define CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50 0x200c +#define CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26 0x2010 +#define CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK 0x2024 +#define CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN 0x2028 +#define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20 0x203c +#define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY 0x2040 + +/* List of parent clocks for Muxes in CMU_HSI */ +PNAME(mout_hsi_bus_user_p) = { "clock-oscclk", "dout_hsi_bus" }; +PNAME(mout_hsi_mmc_card_user_p) = { "clock-oscclk", "dout_hsi_mmc_card" }; +PNAME(mout_hsi_usb20drd_user_p) = { "clock-oscclk", "dout_hsi_usb20drd" }; + +static const struct samsung_mux_clock hsi_mux_clks[] __initconst = { + MUX(CLK_MOUT_HSI_BUS_USER, "mout_hsi_bus_user", mout_hsi_bus_user_p, + PLL_CON0_MUX_CLKCMU_HSI_BUS_USER, 4, 1), + MUX_F(CLK_MOUT_HSI_MMC_CARD_USER, "mout_hsi_mmc_card_user", + mout_hsi_mmc_card_user_p, PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER, + 4, 1, CLK_SET_RATE_PARENT, 0), + MUX(CLK_MOUT_HSI_USB20DRD_USER, "mout_hsi_usb20drd_user", + mout_hsi_usb20drd_user_p, PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER, + 4, 1), +}; + +static const struct samsung_gate_clock hsi_gate_clks[] __initconst = { + GATE(CLK_GOUT_USB_REF_CLK, "gout_usb_ref", "mout_hsi_usb20drd_user", + CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50, 21, 0, 0), + GATE(CLK_GOUT_USB_PHY_REF_CLK, "gout_usb_phy_ref", "clock-oscclk", + CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26, 21, 0, 0), + GATE(CLK_GOUT_MMC_CARD_ACLK, "gout_mmc_card_aclk", "mout_hsi_bus_user", + CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK, 21, 0, 0), + GATE(CLK_GOUT_MMC_CARD_SDCLKIN, "gout_mmc_card_sdclkin", + "mout_hsi_mmc_card_user", + CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN, 21, CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_USB_PHY_ACLK, "gout_usb_phy_aclk", "mout_hsi_bus_user", + CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20, 21, 0, 0), + GATE(CLK_GOUT_USB_BUS_EARLY_CLK, "gout_usb_bus_early", + "mout_hsi_bus_user", + CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY, 21, 0, 0), +}; + +static const struct samsung_clk_group hsi_cmu_clks[] = { + { S_CLK_MUX, hsi_mux_clks, ARRAY_SIZE(hsi_mux_clks) }, + { S_CLK_GATE, hsi_gate_clks, ARRAY_SIZE(hsi_gate_clks) }, +}; + +static int exynos850_cmu_hsi_probe(struct udevice *dev) +{ + return samsung_register_cmu(dev, CMU_HSI, hsi_cmu_clks, + exynos850_cmu_hsi); +} + +static const struct udevice_id exynos850_cmu_hsi_ids[] = { + { .compatible = "samsung,exynos850-cmu-hsi" }, + { } +}; + +SAMSUNG_CLK_OPS(exynos850_cmu_hsi, CMU_HSI); + +U_BOOT_DRIVER(exynos850_cmu_hsi) = { + .name = "exynos850-cmu-hsi", + .id = UCLASS_CLK, + .of_match = exynos850_cmu_hsi_ids, + .ops = &exynos850_cmu_hsi_clk_ops, + .probe = exynos850_cmu_hsi_probe, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/clk/exynos/clk-pll.c b/drivers/clk/exynos/clk-pll.c index 4aacbc26b25..542d577eaa6 100644 --- a/drivers/clk/exynos/clk-pll.c +++ b/drivers/clk/exynos/clk-pll.c @@ -136,7 +136,7 @@ static struct clk *_samsung_clk_register_pll(void __iomem *base, return clk; } -void samsung_clk_register_pll(void __iomem *base, +void samsung_clk_register_pll(void __iomem *base, unsigned int cmu_id, const struct samsung_pll_clock *clk_list, unsigned int nr_clk) { @@ -145,10 +145,12 @@ void samsung_clk_register_pll(void __iomem *base, for (cnt = 0; cnt < nr_clk; cnt++) { struct clk *clk; const struct samsung_pll_clock *pll_clk; + unsigned long clk_id; pll_clk = &clk_list[cnt]; clk = _samsung_clk_register_pll(base, pll_clk); - clk_dm(pll_clk->id, clk); + clk_id = SAMSUNG_TO_CLK_ID(cmu_id, pll_clk->id); + clk_dm(clk_id, clk); } } diff --git a/drivers/clk/exynos/clk-pll.h b/drivers/clk/exynos/clk-pll.h index bd79309fa1c..bdc94e7624d 100644 --- a/drivers/clk/exynos/clk-pll.h +++ b/drivers/clk/exynos/clk-pll.h @@ -15,9 +15,15 @@ #include <linux/clk-provider.h> +struct samsung_pll_clock; + enum samsung_pll_type { pll_0822x, pll_0831x, }; +void samsung_clk_register_pll(void __iomem *base, unsigned int cmu_id, + const struct samsung_pll_clock *clk_list, + unsigned int nr_clk); + #endif /* __EXYNOS_CLK_PLL_H */ diff --git a/drivers/clk/exynos/clk.c b/drivers/clk/exynos/clk.c index 430767f072d..943e8bd0189 100644 --- a/drivers/clk/exynos/clk.c +++ b/drivers/clk/exynos/clk.c @@ -10,61 +10,67 @@ #include <dm.h> #include "clk.h" -void samsung_clk_register_mux(void __iomem *base, - const struct samsung_mux_clock *clk_list, - unsigned int nr_clk) +static void samsung_clk_register_mux(void __iomem *base, unsigned int cmu_id, + const struct samsung_mux_clock *clk_list, + unsigned int nr_clk) { unsigned int cnt; for (cnt = 0; cnt < nr_clk; cnt++) { struct clk *clk; const struct samsung_mux_clock *m; + unsigned long clk_id; m = &clk_list[cnt]; clk = clk_register_mux(NULL, m->name, m->parent_names, m->num_parents, m->flags, base + m->offset, m->shift, m->width, m->mux_flags); - clk_dm(m->id, clk); + clk_id = SAMSUNG_TO_CLK_ID(cmu_id, m->id); + clk_dm(clk_id, clk); } } -void samsung_clk_register_div(void __iomem *base, - const struct samsung_div_clock *clk_list, - unsigned int nr_clk) +static void samsung_clk_register_div(void __iomem *base, unsigned int cmu_id, + const struct samsung_div_clock *clk_list, + unsigned int nr_clk) { unsigned int cnt; for (cnt = 0; cnt < nr_clk; cnt++) { struct clk *clk; const struct samsung_div_clock *d; + unsigned long clk_id; d = &clk_list[cnt]; clk = clk_register_divider(NULL, d->name, d->parent_name, d->flags, base + d->offset, d->shift, d->width, d->div_flags); - clk_dm(d->id, clk); + clk_id = SAMSUNG_TO_CLK_ID(cmu_id, d->id); + clk_dm(clk_id, clk); } } -void samsung_clk_register_gate(void __iomem *base, - const struct samsung_gate_clock *clk_list, - unsigned int nr_clk) +static void samsung_clk_register_gate(void __iomem *base, unsigned int cmu_id, + const struct samsung_gate_clock *clk_list, + unsigned int nr_clk) { unsigned int cnt; for (cnt = 0; cnt < nr_clk; cnt++) { struct clk *clk; const struct samsung_gate_clock *g; + unsigned long clk_id; g = &clk_list[cnt]; clk = clk_register_gate(NULL, g->name, g->parent_name, g->flags, base + g->offset, g->bit_idx, g->gate_flags, NULL); - clk_dm(g->id, clk); + clk_id = SAMSUNG_TO_CLK_ID(cmu_id, g->id); + clk_dm(clk_id, clk); } } -typedef void (*samsung_clk_register_fn)(void __iomem *base, +typedef void (*samsung_clk_register_fn)(void __iomem *base, unsigned int cmu_id, const void *clk_list, unsigned int nr_clk); @@ -78,34 +84,37 @@ static const samsung_clk_register_fn samsung_clk_register_fns[] = { /** * samsung_cmu_register_clocks() - Register provided clock groups * @base: Base address of CMU registers + * @cmu_id: CMU index number * @clk_groups: list of clock groups * @nr_groups: count of clock groups in @clk_groups * * Having the array of clock groups @clk_groups makes it possible to keep a * correct clocks registration order. */ -void samsung_cmu_register_clocks(void __iomem *base, - const struct samsung_clk_group *clk_groups, - unsigned int nr_groups) +static void samsung_cmu_register_clocks(void __iomem *base, unsigned int cmu_id, + const struct samsung_clk_group *clk_groups, + unsigned int nr_groups) { unsigned int i; for (i = 0; i < nr_groups; i++) { const struct samsung_clk_group *g = &clk_groups[i]; - samsung_clk_register_fns[g->type](base, g->clk_list, g->nr_clk); + samsung_clk_register_fns[g->type](base, cmu_id, + g->clk_list, g->nr_clk); } } /** * samsung_cmu_register_one - Register all CMU clocks * @dev: CMU device + * @cmu_id: CMU index number * @clk_groups: list of CMU clock groups * @nr_groups: count of CMU clock groups in @clk_groups * * Return: 0 on success or negative value on error. */ -int samsung_cmu_register_one(struct udevice *dev, +int samsung_cmu_register_one(struct udevice *dev, unsigned int cmu_id, const struct samsung_clk_group *clk_groups, unsigned int nr_groups) { @@ -115,7 +124,7 @@ int samsung_cmu_register_one(struct udevice *dev, if (!base) return -EINVAL; - samsung_cmu_register_clocks(base, clk_groups, nr_groups); + samsung_cmu_register_clocks(base, cmu_id, clk_groups, nr_groups); return 0; } diff --git a/drivers/clk/exynos/clk.h b/drivers/clk/exynos/clk.h index 91a51b877a6..ed0a395f0f6 100644 --- a/drivers/clk/exynos/clk.h +++ b/drivers/clk/exynos/clk.h @@ -13,6 +13,51 @@ #include <linux/clk-provider.h> #include "clk-pll.h" +#define _SAMSUNG_CLK_OPS(_name, _cmu) \ +static int _name##_of_xlate(struct clk *clk, \ + struct ofnode_phandle_args *args) \ +{ \ + if (args->args_count > 1) { \ + debug("Invalid args_count: %d\n", args->args_count); \ + return -EINVAL; \ + } \ + \ + if (args->args_count) \ + clk->id = SAMSUNG_TO_CLK_ID(_cmu, args->args[0]); \ + else \ + clk->id = 0; \ + \ + return 0; \ +} \ + \ +static const struct clk_ops _name##_clk_ops = { \ + .set_rate = ccf_clk_set_rate, \ + .get_rate = ccf_clk_get_rate, \ + .set_parent = ccf_clk_set_parent, \ + .enable = ccf_clk_enable, \ + .disable = ccf_clk_disable, \ + .of_xlate = _name##_of_xlate, \ +} + +/** + * SAMSUNG_CLK_OPS - Define clock operations structure for specified CMU. + * @name: name of generated structure + * @cmu: CMU index + * + * Like ccf_clk_ops, but with custom .of_xlate callback. + */ +#define SAMSUNG_CLK_OPS(name, cmu) _SAMSUNG_CLK_OPS(name, cmu) + +/** + * SAMSUNG_TO_CLK_ID - Calculate a global clock index. + * @_cmu: CMU index + * @_id: local clock index (unique across @_cmu) + * + * Return: A global clock index unique across all CMUs. + * Keeps a range of 256 available clocks for every CMU. + */ +#define SAMSUNG_TO_CLK_ID(_cmu, _id) (((_cmu) << 8) | ((_id) & 0xff)) + /** * struct samsung_mux_clock - information about mux clock * @id: platform specific id of the clock @@ -179,29 +224,14 @@ struct samsung_clk_group { unsigned int nr_clk; }; -void samsung_clk_register_mux(void __iomem *base, - const struct samsung_mux_clock *clk_list, - unsigned int nr_clk); -void samsung_clk_register_div(void __iomem *base, - const struct samsung_div_clock *clk_list, - unsigned int nr_clk); -void samsung_clk_register_gate(void __iomem *base, - const struct samsung_gate_clock *clk_list, - unsigned int nr_clk); -void samsung_clk_register_pll(void __iomem *base, - const struct samsung_pll_clock *clk_list, - unsigned int nr_clk); - -void samsung_cmu_register_clocks(void __iomem *base, - const struct samsung_clk_group *clk_groups, - unsigned int nr_groups); -int samsung_cmu_register_one(struct udevice *dev, +int samsung_cmu_register_one(struct udevice *dev, unsigned int cmu_id, const struct samsung_clk_group *clk_groups, unsigned int nr_groups); /** * samsung_register_cmu - Register CMU clocks ensuring parent CMU is present * @dev: CMU device + * @cmu_id: CMU index number * @clk_groups: list of CMU clock groups * @parent_drv: name of parent CMU driver * @@ -210,7 +240,7 @@ int samsung_cmu_register_one(struct udevice *dev, * * Return: 0 on success or negative value on error. */ -#define samsung_register_cmu(dev, clk_groups, parent_drv) \ +#define samsung_register_cmu(dev, cmu_id, clk_groups, parent_drv) \ ({ \ struct udevice *__parent; \ int __ret; \ @@ -220,8 +250,8 @@ int samsung_cmu_register_one(struct udevice *dev, if (__ret || !__parent) \ __ret = -ENOENT; \ else \ - __ret = samsung_cmu_register_one(dev, clk_groups, \ - ARRAY_SIZE(clk_groups)); \ + __ret = samsung_cmu_register_one(dev, cmu_id, \ + clk_groups, ARRAY_SIZE(clk_groups)); \ __ret; \ }) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 0df0d1881a4..8dae635ac2c 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -2,7 +2,7 @@ if ARCH_SNAPDRAGON || ARCH_IPQ40XX config CLK_QCOM bool - depends on CLK && DM_RESET + depends on CLK && DM_RESET && POWER_DOMAIN def_bool n menu "Qualcomm clock drivers" diff --git a/drivers/clk/qcom/clock-apq8016.c b/drivers/clk/qcom/clock-apq8016.c index e6647f7c41d..5a5868169c8 100644 --- a/drivers/clk/qcom/clock-apq8016.c +++ b/drivers/clk/qcom/clock-apq8016.c @@ -23,11 +23,7 @@ #define APCS_CLOCK_BRANCH_ENA_VOTE (0x45004) #define SDCC_BCR(n) ((n * 0x1000) + 0x41000) -#define SDCC_CMD_RCGR(n) ((n * 0x1000) + 0x41004) -#define SDCC_CFG_RCGR(n) ((n * 0x1000) + 0x41008) -#define SDCC_M(n) ((n * 0x1000) + 0x4100C) -#define SDCC_N(n) ((n * 0x1000) + 0x41010) -#define SDCC_D(n) ((n * 0x1000) + 0x41014) +#define SDCC_CMD_RCGR(n) (((n + 1) * 0x1000) + 0x41004) #define SDCC_APPS_CBCR(n) ((n * 0x1000) + 0x41018) #define SDCC_AHB_CBCR(n) ((n * 0x1000) + 0x4101C) @@ -38,31 +34,10 @@ #define BLSP1_UART2_BCR (0x3028) #define BLSP1_UART2_APPS_CBCR (0x302C) #define BLSP1_UART2_APPS_CMD_RCGR (0x3034) -#define BLSP1_UART2_APPS_CFG_RCGR (0x3038) -#define BLSP1_UART2_APPS_M (0x303C) -#define BLSP1_UART2_APPS_N (0x3040) -#define BLSP1_UART2_APPS_D (0x3044) /* GPLL0 clock control registers */ #define GPLL0_STATUS_ACTIVE BIT(17) -static const struct bcr_regs sdc_regs[] = { - { - .cfg_rcgr = SDCC_CFG_RCGR(1), - .cmd_rcgr = SDCC_CMD_RCGR(1), - .M = SDCC_M(1), - .N = SDCC_N(1), - .D = SDCC_D(1), - }, - { - .cfg_rcgr = SDCC_CFG_RCGR(2), - .cmd_rcgr = SDCC_CMD_RCGR(2), - .M = SDCC_M(2), - .N = SDCC_N(2), - .D = SDCC_D(2), - } -}; - static struct pll_vote_clk gpll0_vote_clk = { .status = GPLL0_STATUS, .status_bit = GPLL0_STATUS_ACTIVE, @@ -86,7 +61,7 @@ static int clk_init_sdc(struct msm_clk_priv *priv, int slot, uint rate) clk_enable_cbc(priv->base + SDCC_AHB_CBCR(slot)); /* 800Mhz/div, gpll0 */ - clk_rcg_set_rate_mnd(priv->base, &sdc_regs[slot], div, 0, 0, + clk_rcg_set_rate_mnd(priv->base, SDCC_CMD_RCGR(slot), div, 0, 0, CFG_CLK_SRC_GPLL0, 8); clk_enable_gpll0(priv->base, &gpll0_vote_clk); clk_enable_cbc(priv->base + SDCC_APPS_CBCR(slot)); @@ -94,14 +69,6 @@ static int clk_init_sdc(struct msm_clk_priv *priv, int slot, uint rate) return rate; } -static const struct bcr_regs uart2_regs = { - .cfg_rcgr = BLSP1_UART2_APPS_CFG_RCGR, - .cmd_rcgr = BLSP1_UART2_APPS_CMD_RCGR, - .M = BLSP1_UART2_APPS_M, - .N = BLSP1_UART2_APPS_N, - .D = BLSP1_UART2_APPS_D, -}; - /* UART: 115200 */ int apq8016_clk_init_uart(phys_addr_t base) { @@ -109,7 +76,7 @@ int apq8016_clk_init_uart(phys_addr_t base) clk_enable_vote_clk(base, &gcc_blsp1_ahb_clk); /* 7372800 uart block clock @ GPLL0 */ - clk_rcg_set_rate_mnd(base, &uart2_regs, 1, 144, 15625, + clk_rcg_set_rate_mnd(base, BLSP1_UART2_APPS_CMD_RCGR, 1, 144, 15625, CFG_CLK_SRC_GPLL0, 16); /* Vote for gpll0 clock */ diff --git a/drivers/clk/qcom/clock-apq8096.c b/drivers/clk/qcom/clock-apq8096.c index a4731613c5e..479f9771a46 100644 --- a/drivers/clk/qcom/clock-apq8096.c +++ b/drivers/clk/qcom/clock-apq8096.c @@ -26,31 +26,15 @@ #define SDCC2_APPS_CBCR (0x14004) /* branch control */ #define SDCC2_AHB_CBCR (0x14008) #define SDCC2_CMD_RCGR (0x14010) -#define SDCC2_CFG_RCGR (0x14014) -#define SDCC2_M (0x14018) -#define SDCC2_N (0x1401C) -#define SDCC2_D (0x14020) #define BLSP2_AHB_CBCR (0x25004) #define BLSP2_UART2_APPS_CBCR (0x29004) #define BLSP2_UART2_APPS_CMD_RCGR (0x2900C) -#define BLSP2_UART2_APPS_CFG_RCGR (0x29010) -#define BLSP2_UART2_APPS_M (0x29014) -#define BLSP2_UART2_APPS_N (0x29018) -#define BLSP2_UART2_APPS_D (0x2901C) /* GPLL0 clock control registers */ #define GPLL0_STATUS_ACTIVE BIT(30) #define APCS_GPLL_ENA_VOTE_GPLL0 BIT(0) -static const struct bcr_regs sdc_regs = { - .cfg_rcgr = SDCC2_CFG_RCGR, - .cmd_rcgr = SDCC2_CMD_RCGR, - .M = SDCC2_M, - .N = SDCC2_N, - .D = SDCC2_D, -}; - static const struct pll_vote_clk gpll0_vote_clk = { .status = GPLL0_STATUS, .status_bit = GPLL0_STATUS_ACTIVE, @@ -69,7 +53,7 @@ static int clk_init_sdc(struct msm_clk_priv *priv, uint rate) int div = 5; clk_enable_cbc(priv->base + SDCC2_AHB_CBCR); - clk_rcg_set_rate_mnd(priv->base, &sdc_regs, div, 0, 0, + clk_rcg_set_rate_mnd(priv->base, SDCC2_CMD_RCGR, div, 0, 0, CFG_CLK_SRC_GPLL0, 8); clk_enable_gpll0(priv->base, &gpll0_vote_clk); clk_enable_cbc(priv->base + SDCC2_APPS_CBCR); @@ -77,21 +61,13 @@ static int clk_init_sdc(struct msm_clk_priv *priv, uint rate) return rate; } -static const struct bcr_regs uart2_regs = { - .cfg_rcgr = BLSP2_UART2_APPS_CFG_RCGR, - .cmd_rcgr = BLSP2_UART2_APPS_CMD_RCGR, - .M = BLSP2_UART2_APPS_M, - .N = BLSP2_UART2_APPS_N, - .D = BLSP2_UART2_APPS_D, -}; - static int clk_init_uart(struct msm_clk_priv *priv) { /* Enable AHB clock */ clk_enable_vote_clk(priv->base, &gcc_blsp2_ahb_clk); /* 7372800 uart block clock @ GPLL0 */ - clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 1, 192, 15625, + clk_rcg_set_rate_mnd(priv->base, BLSP2_UART2_APPS_CMD_RCGR, 1, 192, 15625, CFG_CLK_SRC_GPLL0, 16); /* Vote for gpll0 clock */ diff --git a/drivers/clk/qcom/clock-qcom.c b/drivers/clk/qcom/clock-qcom.c index 7c683e51922..05e5ab7d094 100644 --- a/drivers/clk/qcom/clock-qcom.c +++ b/drivers/clk/qcom/clock-qcom.c @@ -22,7 +22,9 @@ #include <linux/bug.h> #include <linux/delay.h> #include <linux/bitops.h> +#include <linux/iopoll.h> #include <reset-uclass.h> +#include <power-domain-uclass.h> #include "clock-qcom.h" @@ -30,6 +32,13 @@ #define CBCR_BRANCH_ENABLE_BIT BIT(0) #define CBCR_BRANCH_OFF_BIT BIT(31) +#define GDSC_SW_COLLAPSE_MASK BIT(0) +#define GDSC_POWER_DOWN_COMPLETE BIT(15) +#define GDSC_POWER_UP_COMPLETE BIT(16) +#define GDSC_PWR_ON_MASK BIT(31) +#define CFG_GDSCR_OFFSET 0x4 +#define GDSC_STATUS_POLL_TIMEOUT_US 1500 + /* Enable clock controlled by CBC soft macro */ void clk_enable_cbc(phys_addr_t cbcr) { @@ -95,7 +104,7 @@ void clk_bcr_update(phys_addr_t apps_cmd_rcgr) * root set rate for clocks with half integer and MND divider * div should be pre-calculated ((div * 2) - 1) */ -void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs, +void clk_rcg_set_rate_mnd(phys_addr_t base, uint32_t cmd_rcgr, int div, int m, int n, int source, u8 mnd_width) { u32 cfg; @@ -111,13 +120,14 @@ void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs, debug("m %#x n %#x d %#x div %#x mask %#x\n", m_val, n_val, d_val, div, mask); /* Program MND values */ - writel(m_val & mask, base + regs->M); - writel(n_val & mask, base + regs->N); - writel(d_val & mask, base + regs->D); + writel(m_val & mask, base + cmd_rcgr + RCG_M_REG); + writel(n_val & mask, base + cmd_rcgr + RCG_N_REG); + writel(d_val & mask, base + cmd_rcgr + RCG_D_REG); /* setup src select and divider */ - cfg = readl(base + regs->cfg_rcgr); - cfg &= ~(CFG_SRC_SEL_MASK | CFG_MODE_MASK | CFG_HW_CLK_CTRL_MASK); + cfg = readl(base + cmd_rcgr + RCG_CFG_REG); + cfg &= ~(CFG_SRC_SEL_MASK | CFG_MODE_MASK | CFG_HW_CLK_CTRL_MASK | + CFG_SRC_DIV_MASK); cfg |= source & CFG_SRC_SEL_MASK; /* Select clock source */ if (div) @@ -126,20 +136,20 @@ void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs, if (n && n != m) cfg |= CFG_MODE_DUAL_EDGE; - writel(cfg, base + regs->cfg_rcgr); /* Write new clock configuration */ + writel(cfg, base + cmd_rcgr + RCG_CFG_REG); /* Write new clock configuration */ /* Inform h/w to start using the new config. */ - clk_bcr_update(base + regs->cmd_rcgr); + clk_bcr_update(base + cmd_rcgr); } /* root set rate for clocks with half integer and mnd_width=0 */ -void clk_rcg_set_rate(phys_addr_t base, const struct bcr_regs *regs, int div, +void clk_rcg_set_rate(phys_addr_t base, uint32_t cmd_rcgr, int div, int source) { u32 cfg; /* setup src select and divider */ - cfg = readl(base + regs->cfg_rcgr); + cfg = readl(base + cmd_rcgr + RCG_CFG_REG); cfg &= ~(CFG_SRC_SEL_MASK | CFG_MODE_MASK | CFG_HW_CLK_CTRL_MASK); cfg |= source & CFG_CLK_SRC_MASK; /* Select clock source */ @@ -150,10 +160,10 @@ void clk_rcg_set_rate(phys_addr_t base, const struct bcr_regs *regs, int div, if (div) cfg |= (2 * div - 1) & CFG_SRC_DIV_MASK; - writel(cfg, base + regs->cfg_rcgr); /* Write new clock configuration */ + writel(cfg, base + cmd_rcgr + RCG_CFG_REG); /* Write new clock configuration */ /* Inform h/w to start using the new config. */ - clk_bcr_update(base + regs->cmd_rcgr); + clk_bcr_update(base + cmd_rcgr); } const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, uint rate) @@ -217,12 +227,13 @@ U_BOOT_DRIVER(qcom_clk) = { .ops = &msm_clk_ops, .priv_auto = sizeof(struct msm_clk_priv), .probe = msm_clk_probe, + .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF, }; int qcom_cc_bind(struct udevice *parent) { struct msm_clk_data *data = (struct msm_clk_data *)dev_get_driver_data(parent); - struct udevice *clkdev, *rstdev; + struct udevice *clkdev = NULL, *rstdev = NULL, *pwrdev; struct driver *drv; int ret; @@ -237,20 +248,41 @@ int qcom_cc_bind(struct udevice *parent) if (ret) return ret; - /* Bail out early if resets are not specified for this platform */ - if (!data->resets) - return ret; + if (data->resets) { + /* Get a handle to the common reset handler */ + drv = lists_driver_lookup_name("qcom_reset"); + if (!drv) { + ret = -ENOENT; + goto unbind_clkdev; + } + + /* Register the reset controller */ + ret = device_bind_with_driver_data(parent, drv, "qcom_reset", (ulong)data, + dev_ofnode(parent), &rstdev); + if (ret) + goto unbind_clkdev; + } - /* Get a handle to the common reset handler */ - drv = lists_driver_lookup_name("qcom_reset"); - if (!drv) - return -ENOENT; + if (data->power_domains) { + /* Get a handle to the common power domain handler */ + drv = lists_driver_lookup_name("qcom_power"); + if (!drv) { + ret = -ENOENT; + goto unbind_rstdev; + } + /* Register the power domain controller */ + ret = device_bind_with_driver_data(parent, drv, "qcom_power", (ulong)data, + dev_ofnode(parent), &pwrdev); + if (ret) + goto unbind_rstdev; + } - /* Register the reset controller */ - ret = device_bind_with_driver_data(parent, drv, "qcom_reset", (ulong)data, - dev_ofnode(parent), &rstdev); - if (ret) - device_unbind(clkdev); + return 0; + +unbind_rstdev: + device_unbind(rstdev); +unbind_clkdev: + device_unbind(clkdev); return ret; } @@ -305,3 +337,80 @@ U_BOOT_DRIVER(qcom_reset) = { .ops = &qcom_reset_ops, .probe = qcom_reset_probe, }; + +static int qcom_power_set(struct power_domain *pwr, bool on) +{ + struct msm_clk_data *data = (struct msm_clk_data *)dev_get_driver_data(pwr->dev); + void __iomem *base = dev_get_priv(pwr->dev); + const struct qcom_power_map *map; + u32 value; + int ret; + + if (pwr->id >= data->num_power_domains) + return -ENODEV; + + map = &data->power_domains[pwr->id]; + + if (!map->reg) + return -ENODEV; + + value = readl(base + map->reg); + + if (on) + value &= ~GDSC_SW_COLLAPSE_MASK; + else + value |= GDSC_SW_COLLAPSE_MASK; + + writel(value, base + map->reg); + + if (on) + ret = readl_poll_timeout(base + map->reg + CFG_GDSCR_OFFSET, + value, + (value & GDSC_POWER_UP_COMPLETE) || + (value & GDSC_PWR_ON_MASK), + GDSC_STATUS_POLL_TIMEOUT_US); + + else + ret = readl_poll_timeout(base + map->reg + CFG_GDSCR_OFFSET, + value, + (value & GDSC_POWER_DOWN_COMPLETE) || + !(value & GDSC_PWR_ON_MASK), + GDSC_STATUS_POLL_TIMEOUT_US); + + + if (ret == -ETIMEDOUT) + printf("WARNING: GDSC %lu is stuck during power on/off\n", + pwr->id); + return ret; +} + +static int qcom_power_on(struct power_domain *pwr) +{ + return qcom_power_set(pwr, true); +} + +static int qcom_power_off(struct power_domain *pwr) +{ + return qcom_power_set(pwr, false); +} + +static const struct power_domain_ops qcom_power_ops = { + .on = qcom_power_on, + .off = qcom_power_off, +}; + +static int qcom_power_probe(struct udevice *dev) +{ + /* Set our priv pointer to the base address */ + dev_set_priv(dev, (void *)dev_read_addr(dev)); + + return 0; +} + +U_BOOT_DRIVER(qcom_power) = { + .name = "qcom_power", + .id = UCLASS_POWER_DOMAIN, + .ops = &qcom_power_ops, + .probe = qcom_power_probe, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h index 01088c19015..a7f833a4b6d 100644 --- a/drivers/clk/qcom/clock-qcom.h +++ b/drivers/clk/qcom/clock-qcom.h @@ -12,6 +12,11 @@ #define CFG_CLK_SRC_GPLL0_EVEN (6 << 8) #define CFG_CLK_SRC_MASK (7 << 8) +#define RCG_CFG_REG 0x4 +#define RCG_M_REG 0x8 +#define RCG_N_REG 0xc +#define RCG_D_REG 0x10 + struct pll_vote_clk { uintptr_t status; int status_bit; @@ -24,13 +29,6 @@ struct vote_clk { uintptr_t ena_vote; int vote_bit; }; -struct bcr_regs { - uintptr_t cfg_rcgr; - uintptr_t cmd_rcgr; - uintptr_t M; - uintptr_t N; - uintptr_t D; -}; struct freq_tbl { uint freq; @@ -59,9 +57,15 @@ struct qcom_reset_map { u8 bit; }; +struct qcom_power_map { + unsigned int reg; +}; + struct clk; struct msm_clk_data { + const struct qcom_power_map *power_domains; + unsigned long num_power_domains; const struct qcom_reset_map *resets; unsigned long num_resets; const struct gate_clk *clks; @@ -82,9 +86,9 @@ void clk_bcr_update(phys_addr_t apps_cmd_rgcr); void clk_enable_cbc(phys_addr_t cbcr); void clk_enable_vote_clk(phys_addr_t base, const struct vote_clk *vclk); const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, uint rate); -void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs, +void clk_rcg_set_rate_mnd(phys_addr_t base, uint32_t cmd_rcgr, int div, int m, int n, int source, u8 mnd_width); -void clk_rcg_set_rate(phys_addr_t base, const struct bcr_regs *regs, int div, +void clk_rcg_set_rate(phys_addr_t base, uint32_t cmd_rcgr, int div, int source); static inline void qcom_gate_clk_en(const struct msm_clk_priv *priv, unsigned long id) diff --git a/drivers/clk/qcom/clock-qcs404.c b/drivers/clk/qcom/clock-qcs404.c index 958312b8884..8a897a52bc0 100644 --- a/drivers/clk/qcom/clock-qcs404.c +++ b/drivers/clk/qcom/clock-qcs404.c @@ -28,35 +28,22 @@ #define BLSP1_UART2_BCR (0x3028) #define BLSP1_UART2_APPS_CBCR (0x302C) #define BLSP1_UART2_APPS_CMD_RCGR (0x3034) -#define BLSP1_UART2_APPS_CFG_RCGR (0x3038) -#define BLSP1_UART2_APPS_M (0x303C) -#define BLSP1_UART2_APPS_N (0x3040) -#define BLSP1_UART2_APPS_D (0x3044) /* I2C controller clock control registerss */ #define BLSP1_QUP0_I2C_APPS_CBCR (0x6028) #define BLSP1_QUP0_I2C_APPS_CMD_RCGR (0x602C) -#define BLSP1_QUP0_I2C_APPS_CFG_RCGR (0x6030) #define BLSP1_QUP1_I2C_APPS_CBCR (0x2008) #define BLSP1_QUP1_I2C_APPS_CMD_RCGR (0x200C) -#define BLSP1_QUP1_I2C_APPS_CFG_RCGR (0x2010) #define BLSP1_QUP2_I2C_APPS_CBCR (0x3010) #define BLSP1_QUP2_I2C_APPS_CMD_RCGR (0x3000) -#define BLSP1_QUP2_I2C_APPS_CFG_RCGR (0x3004) #define BLSP1_QUP3_I2C_APPS_CBCR (0x4020) #define BLSP1_QUP3_I2C_APPS_CMD_RCGR (0x4000) -#define BLSP1_QUP3_I2C_APPS_CFG_RCGR (0x4004) #define BLSP1_QUP4_I2C_APPS_CBCR (0x5020) #define BLSP1_QUP4_I2C_APPS_CMD_RCGR (0x5000) -#define BLSP1_QUP4_I2C_APPS_CFG_RCGR (0x5004) /* SD controller clock control registers */ #define SDCC_BCR(n) (((n) * 0x1000) + 0x41000) -#define SDCC_CMD_RCGR(n) (((n) * 0x1000) + 0x41004) -#define SDCC_CFG_RCGR(n) (((n) * 0x1000) + 0x41008) -#define SDCC_M(n) (((n) * 0x1000) + 0x4100C) -#define SDCC_N(n) (((n) * 0x1000) + 0x41010) -#define SDCC_D(n) (((n) * 0x1000) + 0x41014) +#define SDCC_CMD_RCGR(n) (((n + 1) * 0x1000) + 0x41004) #define SDCC_APPS_CBCR(n) (((n) * 0x1000) + 0x41018) #define SDCC_AHB_CBCR(n) (((n) * 0x1000) + 0x4101C) @@ -70,10 +57,6 @@ #define USB30_MOCK_UTMI_CMD_RCGR (0x3901C) #define USB30_MOCK_UTMI_CFG_RCGR (0x39020) #define USB30_MASTER_CMD_RCGR (0x39028) -#define USB30_MASTER_CFG_RCGR (0x3902C) -#define USB30_MASTER_M (0x39030) -#define USB30_MASTER_N (0x39034) -#define USB30_MASTER_D (0x39038) #define USB2A_PHY_SLEEP_CBCR (0x4102C) #define USB_HS_PHY_CFG_AHB_CBCR (0x41030) @@ -83,12 +66,7 @@ #define ETH_SLAVE_AHB_CBCR (0x4e00c) #define ETH_AXI_CBCR (0x4e010) #define EMAC_PTP_CMD_RCGR (0x4e014) -#define EMAC_PTP_CFG_RCGR (0x4e018) #define EMAC_CMD_RCGR (0x4e01c) -#define EMAC_CFG_RCGR (0x4e020) -#define EMAC_M (0x4e024) -#define EMAC_N (0x4e028) -#define EMAC_D (0x4e02c) /* GPLL0 clock control registers */ @@ -103,22 +81,6 @@ static struct vote_clk gcc_blsp1_ahb_clk = { .vote_bit = BIT(10) | BIT(5) | BIT(4), }; -static const struct bcr_regs uart2_regs = { - .cfg_rcgr = BLSP1_UART2_APPS_CFG_RCGR, - .cmd_rcgr = BLSP1_UART2_APPS_CMD_RCGR, - .M = BLSP1_UART2_APPS_M, - .N = BLSP1_UART2_APPS_N, - .D = BLSP1_UART2_APPS_D, -}; - -static const struct bcr_regs sdc_regs = { - .cfg_rcgr = SDCC_CFG_RCGR(1), - .cmd_rcgr = SDCC_CMD_RCGR(1), - .M = SDCC_M(1), - .N = SDCC_N(1), - .D = SDCC_D(1), -}; - static struct pll_vote_clk gpll0_vote_clk = { .status = GPLL0_STATUS, .status_bit = GPLL0_STATUS_ACTIVE, @@ -133,60 +95,6 @@ static struct pll_vote_clk gpll1_vote_clk = { .vote_bit = BIT(1), }; -static const struct bcr_regs usb30_master_regs = { - .cfg_rcgr = USB30_MASTER_CFG_RCGR, - .cmd_rcgr = USB30_MASTER_CMD_RCGR, - .M = USB30_MASTER_M, - .N = USB30_MASTER_N, - .D = USB30_MASTER_D, -}; - -static const struct bcr_regs emac_regs = { - .cfg_rcgr = EMAC_CFG_RCGR, - .cmd_rcgr = EMAC_CMD_RCGR, - .M = EMAC_M, - .N = EMAC_N, - .D = EMAC_D, -}; - -static const struct bcr_regs emac_ptp_regs = { - .cfg_rcgr = EMAC_PTP_CFG_RCGR, - .cmd_rcgr = EMAC_PTP_CMD_RCGR, - .M = EMAC_M, - .N = EMAC_N, - .D = EMAC_D, -}; - -static const struct bcr_regs blsp1_qup0_i2c_apps_regs = { - .cmd_rcgr = BLSP1_QUP0_I2C_APPS_CMD_RCGR, - .cfg_rcgr = BLSP1_QUP0_I2C_APPS_CFG_RCGR, - /* mnd_width = 0 */ -}; - -static const struct bcr_regs blsp1_qup1_i2c_apps_regs = { - .cmd_rcgr = BLSP1_QUP1_I2C_APPS_CMD_RCGR, - .cfg_rcgr = BLSP1_QUP1_I2C_APPS_CFG_RCGR, - /* mnd_width = 0 */ -}; - -static const struct bcr_regs blsp1_qup2_i2c_apps_regs = { - .cmd_rcgr = BLSP1_QUP2_I2C_APPS_CMD_RCGR, - .cfg_rcgr = BLSP1_QUP2_I2C_APPS_CFG_RCGR, - /* mnd_width = 0 */ -}; - -static const struct bcr_regs blsp1_qup3_i2c_apps_regs = { - .cmd_rcgr = BLSP1_QUP3_I2C_APPS_CMD_RCGR, - .cfg_rcgr = BLSP1_QUP3_I2C_APPS_CFG_RCGR, - /* mnd_width = 0 */ -}; - -static const struct bcr_regs blsp1_qup4_i2c_apps_regs = { - .cmd_rcgr = BLSP1_QUP4_I2C_APPS_CMD_RCGR, - .cfg_rcgr = BLSP1_QUP4_I2C_APPS_CFG_RCGR, - /* mnd_width = 0 */ -}; - static ulong qcs404_clk_set_rate(struct clk *clk, ulong rate) { struct msm_clk_priv *priv = dev_get_priv(clk->dev); @@ -194,29 +102,29 @@ static ulong qcs404_clk_set_rate(struct clk *clk, ulong rate) switch (clk->id) { case GCC_BLSP1_UART2_APPS_CLK: /* UART: 1843200Hz for a fixed 115200 baudrate (19200000 * (12/125)) */ - clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 0, 12, 125, + clk_rcg_set_rate_mnd(priv->base, BLSP1_UART2_APPS_CMD_RCGR, 0, 12, 125, CFG_CLK_SRC_CXO, 16); clk_enable_cbc(priv->base + BLSP1_UART2_APPS_CBCR); return 1843200; case GCC_SDCC1_APPS_CLK: /* SDCC1: 200MHz */ - clk_rcg_set_rate_mnd(priv->base, &sdc_regs, 7, 0, 0, + clk_rcg_set_rate_mnd(priv->base, SDCC_CMD_RCGR(0), 7, 0, 0, CFG_CLK_SRC_GPLL0, 8); clk_enable_gpll0(priv->base, &gpll0_vote_clk); clk_enable_cbc(priv->base + SDCC_APPS_CBCR(1)); return rate; case GCC_ETH_RGMII_CLK: if (rate == 250000000) - clk_rcg_set_rate_mnd(priv->base, &emac_regs, 3, 0, 0, + clk_rcg_set_rate_mnd(priv->base, EMAC_CMD_RCGR, 3, 0, 0, CFG_CLK_SRC_GPLL1, 8); else if (rate == 125000000) - clk_rcg_set_rate_mnd(priv->base, &emac_regs, 7, 0, 0, + clk_rcg_set_rate_mnd(priv->base, EMAC_CMD_RCGR, 7, 0, 0, CFG_CLK_SRC_GPLL1, 8); else if (rate == 50000000) - clk_rcg_set_rate_mnd(priv->base, &emac_regs, 19, 0, 0, + clk_rcg_set_rate_mnd(priv->base, EMAC_CMD_RCGR, 19, 0, 0, CFG_CLK_SRC_GPLL1, 8); else if (rate == 5000000) - clk_rcg_set_rate_mnd(priv->base, &emac_regs, 3, 1, 50, + clk_rcg_set_rate_mnd(priv->base, EMAC_CMD_RCGR, 3, 1, 50, CFG_CLK_SRC_GPLL1, 8); return rate; } @@ -237,7 +145,7 @@ static int qcs404_clk_enable(struct clk *clk) switch (clk->id) { case GCC_USB30_MASTER_CLK: clk_enable_cbc(priv->base + USB30_MASTER_CBCR); - clk_rcg_set_rate_mnd(priv->base, &usb30_master_regs, 7, 0, 0, + clk_rcg_set_rate_mnd(priv->base, USB30_MASTER_CMD_RCGR, 7, 0, 0, CFG_CLK_SRC_GPLL0, 8); break; case GCC_SYS_NOC_USB3_CLK: @@ -259,14 +167,14 @@ static int qcs404_clk_enable(struct clk *clk) /* SPEED_1000: freq -> 250MHz */ clk_enable_cbc(priv->base + ETH_PTP_CBCR); clk_enable_gpll0(priv->base, &gpll1_vote_clk); - clk_rcg_set_rate_mnd(priv->base, &emac_ptp_regs, 3, 0, 0, + clk_rcg_set_rate_mnd(priv->base, EMAC_PTP_CMD_RCGR, 3, 0, 0, CFG_CLK_SRC_GPLL1, 8); break; case GCC_ETH_RGMII_CLK: /* SPEED_1000: freq -> 250MHz */ clk_enable_cbc(priv->base + ETH_RGMII_CBCR); clk_enable_gpll0(priv->base, &gpll1_vote_clk); - clk_rcg_set_rate_mnd(priv->base, &emac_regs, 3, 0, 0, + clk_rcg_set_rate_mnd(priv->base, EMAC_CMD_RCGR, 3, 0, 0, CFG_CLK_SRC_GPLL1, 8); break; case GCC_ETH_SLAVE_AHB_CLK: @@ -280,27 +188,27 @@ static int qcs404_clk_enable(struct clk *clk) break; case GCC_BLSP1_QUP0_I2C_APPS_CLK: clk_enable_cbc(priv->base + BLSP1_QUP0_I2C_APPS_CBCR); - clk_rcg_set_rate(priv->base, &blsp1_qup0_i2c_apps_regs, 0, + clk_rcg_set_rate(priv->base, BLSP1_QUP0_I2C_APPS_CMD_RCGR, 0, CFG_CLK_SRC_CXO); break; case GCC_BLSP1_QUP1_I2C_APPS_CLK: clk_enable_cbc(priv->base + BLSP1_QUP1_I2C_APPS_CBCR); - clk_rcg_set_rate(priv->base, &blsp1_qup1_i2c_apps_regs, 0, + clk_rcg_set_rate(priv->base, BLSP1_QUP1_I2C_APPS_CMD_RCGR, 0, CFG_CLK_SRC_CXO); break; case GCC_BLSP1_QUP2_I2C_APPS_CLK: clk_enable_cbc(priv->base + BLSP1_QUP2_I2C_APPS_CBCR); - clk_rcg_set_rate(priv->base, &blsp1_qup2_i2c_apps_regs, 0, + clk_rcg_set_rate(priv->base, BLSP1_QUP2_I2C_APPS_CMD_RCGR, 0, CFG_CLK_SRC_CXO); break; case GCC_BLSP1_QUP3_I2C_APPS_CLK: clk_enable_cbc(priv->base + BLSP1_QUP3_I2C_APPS_CBCR); - clk_rcg_set_rate(priv->base, &blsp1_qup3_i2c_apps_regs, 0, + clk_rcg_set_rate(priv->base, BLSP1_QUP3_I2C_APPS_CMD_RCGR, 0, CFG_CLK_SRC_CXO); break; case GCC_BLSP1_QUP4_I2C_APPS_CLK: clk_enable_cbc(priv->base + BLSP1_QUP4_I2C_APPS_CBCR); - clk_rcg_set_rate(priv->base, &blsp1_qup4_i2c_apps_regs, 0, + clk_rcg_set_rate(priv->base, BLSP1_QUP4_I2C_APPS_CMD_RCGR, 0, CFG_CLK_SRC_CXO); break; case GCC_SDCC1_AHB_CLK: diff --git a/drivers/clk/qcom/clock-sdm845.c b/drivers/clk/qcom/clock-sdm845.c index 36ffee79d96..e9c61eb480d 100644 --- a/drivers/clk/qcom/clock-sdm845.c +++ b/drivers/clk/qcom/clock-sdm845.c @@ -19,13 +19,11 @@ #include "clock-qcom.h" -#define SE9_AHB_CBCR 0x25004 -#define SE9_UART_APPS_CBCR 0x29004 #define SE9_UART_APPS_CMD_RCGR 0x18148 -#define SE9_UART_APPS_CFG_RCGR 0x1814C -#define SE9_UART_APPS_M 0x18150 -#define SE9_UART_APPS_N 0x18154 -#define SE9_UART_APPS_D 0x18158 + +#define USB30_PRIM_MASTER_CLK_CMD_RCGR 0xf018 +#define USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR 0xf030 +#define USB3_PRIM_PHY_AUX_CMD_RCGR 0xf05c static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { F(7372800, CFG_CLK_SRC_GPLL0_EVEN, 1, 384, 15625), @@ -46,14 +44,6 @@ static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { { } }; -static const struct bcr_regs uart2_regs = { - .cfg_rcgr = SE9_UART_APPS_CFG_RCGR, - .cmd_rcgr = SE9_UART_APPS_CMD_RCGR, - .M = SE9_UART_APPS_M, - .N = SE9_UART_APPS_N, - .D = SE9_UART_APPS_D, -}; - static ulong sdm845_clk_set_rate(struct clk *clk, ulong rate) { struct msm_clk_priv *priv = dev_get_priv(clk->dev); @@ -62,7 +52,7 @@ static ulong sdm845_clk_set_rate(struct clk *clk, ulong rate) switch (clk->id) { case GCC_QUPV3_WRAP1_S1_CLK: /* UART9 */ freq = qcom_find_freq(ftbl_gcc_qupv3_wrap0_s0_clk_src, rate); - clk_rcg_set_rate_mnd(priv->base, &uart2_regs, + clk_rcg_set_rate_mnd(priv->base, SE9_UART_APPS_CMD_RCGR, freq->pre_div, freq->m, freq->n, freq->src, 16); return freq->freq; default: @@ -71,6 +61,8 @@ static ulong sdm845_clk_set_rate(struct clk *clk, ulong rate) } static const struct gate_clk sdm845_clks[] = { + GATE_CLK(GCC_AGGRE_USB3_SEC_AXI_CLK, 0x82020, 0x00000001), + GATE_CLK(GCC_CFG_NOC_USB3_SEC_AXI_CLK, 0x05030, 0x00000001), GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK, 0x5200c, 0x00000400), GATE_CLK(GCC_QUPV3_WRAP0_S1_CLK, 0x5200c, 0x00000800), GATE_CLK(GCC_QUPV3_WRAP0_S2_CLK, 0x5200c, 0x00001000), @@ -135,6 +127,25 @@ static int sdm845_clk_enable(struct clk *clk) debug("%s: clk %s\n", __func__, sdm845_clks[clk->id].name); + switch (clk->id) { + case GCC_USB30_PRIM_MASTER_CLK: + qcom_gate_clk_en(priv, GCC_USB_PHY_CFG_AHB2PHY_CLK); + /* These numbers are just pulled from the frequency tables in the Linux driver */ + clk_rcg_set_rate_mnd(priv->base, USB30_PRIM_MASTER_CLK_CMD_RCGR, + (4.5 * 2) - 1, 0, 0, 1 << 8, 8); + clk_rcg_set_rate_mnd(priv->base, USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR, + 1, 0, 0, 0, 8); + clk_rcg_set_rate_mnd(priv->base, USB3_PRIM_PHY_AUX_CMD_RCGR, + 1, 0, 0, 0, 8); + break; + case GCC_USB30_SEC_MASTER_CLK: + qcom_gate_clk_en(priv, GCC_USB3_SEC_PHY_AUX_CLK); + + qcom_gate_clk_en(priv, GCC_USB3_SEC_CLKREF_CLK); + qcom_gate_clk_en(priv, GCC_USB3_SEC_PHY_COM_AUX_CLK); + break; + } + qcom_gate_clk_en(priv, clk->id); return 0; @@ -160,11 +171,29 @@ static const struct qcom_reset_map sdm845_gcc_resets[] = { [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, }; +static const struct qcom_power_map sdm845_gdscs[] = { + [PCIE_0_GDSC] = { 0x6b004 }, + [PCIE_1_GDSC] = { 0x8d004 }, + [UFS_CARD_GDSC] = { 0x75004 }, + [UFS_PHY_GDSC] = { 0x77004 }, + [USB30_PRIM_GDSC] = { 0xf004 }, + [USB30_SEC_GDSC] = { 0x10004 }, + [HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC] = { 0x7d030 }, + [HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC] = { 0x7d03c }, + [HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC] = { 0x7d034 }, + [HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC] = { 0x7d038 }, + [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] = { 0x7d040 }, + [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] = { 0x7d048 }, + [HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC] = { 0x7d044 }, +}; + static struct msm_clk_data sdm845_clk_data = { .resets = sdm845_gcc_resets, .num_resets = ARRAY_SIZE(sdm845_gcc_resets), .clks = sdm845_clks, .num_clks = ARRAY_SIZE(sdm845_clks), + .power_domains = sdm845_gdscs, + .num_power_domains = ARRAY_SIZE(sdm845_gdscs), .enable = sdm845_clk_enable, .set_rate = sdm845_clk_set_rate, @@ -183,5 +212,5 @@ U_BOOT_DRIVER(gcc_sdm845) = { .id = UCLASS_NOP, .of_match = gcc_sdm845_of_match, .bind = qcom_cc_bind, - .flags = DM_FLAG_PRE_RELOC, + .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF, }; diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index a7fb1eb3f4c..b050585389b 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -665,13 +665,6 @@ config SLG7XL45106_I2C_GPO 8-bit gpo expander, all gpo lines are controlled by writing value into data register. -config TURRIS_OMNIA_MCU - bool "Turris Omnia MCU GPIO driver" - depends on DM_GPIO - default y if TARGET_TURRIS_OMNIA - help - Support for GPIOs on MCU connected to Turris Omnia via i2c. - config FTGPIO010 bool "Faraday Technology FTGPIO010 driver" depends on DM_GPIO diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 90711702a69..4a293154350 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -73,7 +73,6 @@ obj-$(CONFIG_$(SPL_)MAX77663_GPIO) += max77663_gpio.o obj-$(CONFIG_SL28CPLD_GPIO) += sl28cpld-gpio.o obj-$(CONFIG_ZYNQMP_GPIO_MODEPIN) += zynqmp_gpio_modepin.o obj-$(CONFIG_SLG7XL45106_I2C_GPO) += gpio_slg7xl45106.o -obj-$(CONFIG_$(SPL_TPL_)TURRIS_OMNIA_MCU) += turris_omnia_mcu.o obj-$(CONFIG_FTGPIO010) += ftgpio010.o obj-$(CONFIG_ADP5585_GPIO) += adp5585_gpio.o obj-$(CONFIG_RZG2L_GPIO) += rzg2l-gpio.o diff --git a/drivers/gpio/msm_gpio.c b/drivers/gpio/msm_gpio.c index 5e57b0cbde7..f5d9ab54e81 100644 --- a/drivers/gpio/msm_gpio.c +++ b/drivers/gpio/msm_gpio.c @@ -35,19 +35,19 @@ struct msm_gpio_bank { #define GPIO_IN_OUT_REG(dev, x) \ (GPIO_CONFIG_REG(dev, x) + 0x4) -static int msm_gpio_direction_input(struct udevice *dev, unsigned int gpio) +static void msm_gpio_direction_input(struct udevice *dev, unsigned int gpio) { struct msm_gpio_bank *priv = dev_get_priv(dev); /* Always NOP for special pins, assume they're in the correct state */ if (qcom_is_special_pin(priv->pin_data, gpio)) - return 0; + return; /* Disable OE bit */ clrsetbits_le32(priv->base + GPIO_CONFIG_REG(dev, gpio), GPIO_OE_MASK, GPIO_OE_DISABLE); - return 0; + return; } static int msm_gpio_set_value(struct udevice *dev, unsigned int gpio, int value) @@ -84,6 +84,23 @@ static int msm_gpio_direction_output(struct udevice *dev, unsigned int gpio, return 0; } +static int msm_gpio_set_flags(struct udevice *dev, unsigned int gpio, ulong flags) +{ + if (flags & GPIOD_IS_OUT_ACTIVE) { + return msm_gpio_direction_output(dev, gpio, 1); + } else if (flags & GPIOD_IS_OUT) { + return msm_gpio_direction_output(dev, gpio, 0); + } else if (flags & GPIOD_IS_IN) { + msm_gpio_direction_input(dev, gpio); + if (flags & GPIOD_PULL_UP) + return msm_gpio_set_value(dev, gpio, 1); + else if (flags & GPIOD_PULL_DOWN) + return msm_gpio_set_value(dev, gpio, 0); + } + + return 0; +} + static int msm_gpio_get_value(struct udevice *dev, unsigned int gpio) { struct msm_gpio_bank *priv = dev_get_priv(dev); @@ -110,10 +127,8 @@ static int msm_gpio_get_function(struct udevice *dev, unsigned int gpio) } static const struct dm_gpio_ops gpio_msm_ops = { - .direction_input = msm_gpio_direction_input, - .direction_output = msm_gpio_direction_output, + .set_flags = msm_gpio_set_flags, .get_value = msm_gpio_get_value, - .set_value = msm_gpio_set_value, .get_function = msm_gpio_get_function, }; diff --git a/drivers/gpio/turris_omnia_mcu.c b/drivers/gpio/turris_omnia_mcu.c deleted file mode 100644 index 2d2bf2d1dd6..00000000000 --- a/drivers/gpio/turris_omnia_mcu.c +++ /dev/null @@ -1,316 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// (C) 2022 Pali Rohár <pali@kernel.org> - -#include <common.h> -#include <dm.h> -#include <i2c.h> -#include <asm/gpio.h> -#include <linux/log2.h> - -enum commands_e { - CMD_GET_STATUS_WORD = 0x01, - CMD_GENERAL_CONTROL = 0x02, - - /* available if STS_FEATURES_SUPPORTED bit set in status word */ - CMD_GET_FEATURES = 0x10, - - /* available if FEAT_EXT_CMDS bit is set in features */ - CMD_GET_EXT_STATUS_DWORD = 0x11, - - /* available if FEAT_EXT_CMDS and FEAT_PERIPH_MCU bits are set in featurs */ - CMD_EXT_CONTROL = 0x12, - CMD_GET_EXT_CONTROL_STATUS = 0x13, -}; - -/* CMD_GET_STATUS_WORD */ -enum sts_word_e { - STS_MCU_TYPE_MASK = GENMASK(1, 0), - STS_MCU_TYPE_STM32 = 0, - STS_MCU_TYPE_GD32 = 1, - STS_MCU_TYPE_MKL = 2, - STS_FEATURES_SUPPORTED = BIT(2), - STS_USER_REGULATOR_NOT_SUPPORTED = BIT(3), - STS_CARD_DET = BIT(4), - STS_MSATA_IND = BIT(5), - STS_USB30_OVC = BIT(6), - STS_USB31_OVC = BIT(7), - STS_USB30_PWRON = BIT(8), - STS_USB31_PWRON = BIT(9), - STS_ENABLE_4V5 = BIT(10), - STS_BUTTON_MODE = BIT(11), - STS_BUTTON_PRESSED = BIT(12), - STS_BUTTON_COUNTER_MASK = GENMASK(15, 13) -}; - -/* CMD_GENERAL_CONTROL */ -enum ctl_byte_e { - CTL_LIGHT_RST = BIT(0), - CTL_HARD_RST = BIT(1), - /*CTL_RESERVED = BIT(2),*/ - CTL_USB30_PWRON = BIT(3), - CTL_USB31_PWRON = BIT(4), - CTL_ENABLE_4V5 = BIT(5), - CTL_BUTTON_MODE = BIT(6), - CTL_BOOTLOADER = BIT(7) -}; - -/* CMD_GET_FEATURES */ -enum features_e { - FEAT_PERIPH_MCU = BIT(0), - FEAT_EXT_CMDS = BIT(1), -}; - -struct turris_omnia_mcu_info { - u16 features; -}; - -static int turris_omnia_mcu_get_function(struct udevice *dev, uint offset) -{ - struct turris_omnia_mcu_info *info = dev_get_plat(dev); - - switch (offset) { - /* bank 0 */ - case 0 ... 15: - switch (offset) { - case ilog2(STS_USB30_PWRON): - case ilog2(STS_USB31_PWRON): - case ilog2(STS_ENABLE_4V5): - case ilog2(STS_BUTTON_MODE): - return GPIOF_OUTPUT; - default: - return GPIOF_INPUT; - } - - /* bank 1 - supported only when FEAT_EXT_CMDS is set */ - case (16 + 0) ... (16 + 31): - if (!(info->features & FEAT_EXT_CMDS)) - return -EINVAL; - return GPIOF_INPUT; - - /* bank 2 - supported only when FEAT_EXT_CMDS and FEAT_PERIPH_MCU is set */ - case (16 + 32 + 0) ... (16 + 32 + 15): - if (!(info->features & FEAT_EXT_CMDS)) - return -EINVAL; - if (!(info->features & FEAT_PERIPH_MCU)) - return -EINVAL; - return GPIOF_OUTPUT; - - default: - return -EINVAL; - } -} - -static int turris_omnia_mcu_get_value(struct udevice *dev, uint offset) -{ - struct turris_omnia_mcu_info *info = dev_get_plat(dev); - u8 val16[2]; - u8 val32[4]; - int ret; - - switch (offset) { - /* bank 0 */ - case 0 ... 15: - ret = dm_i2c_read(dev, CMD_GET_STATUS_WORD, val16, 2); - if (ret) - return ret; - return ((((u16)val16[1] << 8) | val16[0]) >> offset) & 0x1; - - /* bank 1 - supported only when FEAT_EXT_CMDS is set */ - case (16 + 0) ... (16 + 31): - if (!(info->features & FEAT_EXT_CMDS)) - return -EINVAL; - ret = dm_i2c_read(dev, CMD_GET_EXT_STATUS_DWORD, val32, 4); - if (ret) - return ret; - return ((((u32)val32[3] << 24) | ((u32)val32[2] << 16) | - ((u32)val32[1] << 8) | val32[0]) >> (offset - 16)) & 0x1; - - /* bank 2 - supported only when FEAT_EXT_CMDS and FEAT_PERIPH_MCU is set */ - case (16 + 32 + 0) ... (16 + 32 + 15): - if (!(info->features & FEAT_EXT_CMDS)) - return -EINVAL; - if (!(info->features & FEAT_PERIPH_MCU)) - return -EINVAL; - ret = dm_i2c_read(dev, CMD_GET_EXT_CONTROL_STATUS, val16, 2); - if (ret) - return ret; - return ((((u16)val16[1] << 8) | val16[0]) >> (offset - 16 - 32)) & 0x1; - - default: - return -EINVAL; - } -} - -static int turris_omnia_mcu_set_value(struct udevice *dev, uint offset, int value) -{ - struct turris_omnia_mcu_info *info = dev_get_plat(dev); - u8 val16[2]; - u8 val32[4]; - - switch (offset) { - /* bank 0 */ - case 0 ... 15: - switch (offset) { - case ilog2(STS_USB30_PWRON): - val16[1] = CTL_USB30_PWRON; - break; - case ilog2(STS_USB31_PWRON): - val16[1] = CTL_USB31_PWRON; - break; - case ilog2(STS_ENABLE_4V5): - val16[1] = CTL_ENABLE_4V5; - break; - case ilog2(STS_BUTTON_MODE): - val16[1] = CTL_BUTTON_MODE; - break; - default: - return -EINVAL; - } - val16[0] = value ? val16[1] : 0; - return dm_i2c_write(dev, CMD_GENERAL_CONTROL, val16, sizeof(val16)); - - /* bank 2 - supported only when FEAT_EXT_CMDS and FEAT_PERIPH_MCU is set */ - case (16 + 32 + 0) ... (16 + 32 + 15): - if (!(info->features & FEAT_EXT_CMDS)) - return -EINVAL; - if (!(info->features & FEAT_PERIPH_MCU)) - return -EINVAL; - val32[3] = BIT(offset - 16 - 32) >> 8; - val32[2] = BIT(offset - 16 - 32) & 0xff; - val32[1] = value ? val32[3] : 0; - val32[0] = value ? val32[2] : 0; - return dm_i2c_write(dev, CMD_EXT_CONTROL, val32, sizeof(val32)); - - default: - return -EINVAL; - } -} - -static int turris_omnia_mcu_direction_input(struct udevice *dev, uint offset) -{ - int ret; - - ret = turris_omnia_mcu_get_function(dev, offset); - if (ret < 0) - return ret; - else if (ret != GPIOF_INPUT) - return -EOPNOTSUPP; - - return 0; -} - -static int turris_omnia_mcu_direction_output(struct udevice *dev, uint offset, int value) -{ - int ret; - - ret = turris_omnia_mcu_get_function(dev, offset); - if (ret < 0) - return ret; - else if (ret != GPIOF_OUTPUT) - return -EOPNOTSUPP; - - return turris_omnia_mcu_set_value(dev, offset, value); -} - -static int turris_omnia_mcu_xlate(struct udevice *dev, struct gpio_desc *desc, - struct ofnode_phandle_args *args) -{ - uint bank, gpio, flags, offset; - int ret; - - if (args->args_count != 3) - return -EINVAL; - - bank = args->args[0]; - gpio = args->args[1]; - flags = args->args[2]; - - switch (bank) { - case 0: - if (gpio >= 16) - return -EINVAL; - offset = gpio; - break; - case 1: - if (gpio >= 32) - return -EINVAL; - offset = 16 + gpio; - break; - case 2: - if (gpio >= 16) - return -EINVAL; - offset = 16 + 32 + gpio; - break; - default: - return -EINVAL; - } - - ret = turris_omnia_mcu_get_function(dev, offset); - if (ret < 0) - return ret; - - desc->offset = offset; - desc->flags = gpio_flags_xlate(flags); - - return 0; -} - -static const struct dm_gpio_ops turris_omnia_mcu_ops = { - .direction_input = turris_omnia_mcu_direction_input, - .direction_output = turris_omnia_mcu_direction_output, - .get_value = turris_omnia_mcu_get_value, - .set_value = turris_omnia_mcu_set_value, - .get_function = turris_omnia_mcu_get_function, - .xlate = turris_omnia_mcu_xlate, -}; - -static int turris_omnia_mcu_probe(struct udevice *dev) -{ - struct turris_omnia_mcu_info *info = dev_get_plat(dev); - struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); - u16 status; - u8 val[2]; - int ret; - - ret = dm_i2c_read(dev, CMD_GET_STATUS_WORD, val, 2); - if (ret) { - printf("Error: turris_omnia_mcu CMD_GET_STATUS_WORD failed: %d\n", ret); - return ret; - } - - status = ((u16)val[1] << 8) | val[0]; - - if (status & STS_FEATURES_SUPPORTED) { - ret = dm_i2c_read(dev, CMD_GET_FEATURES, val, 2); - if (ret) { - printf("Error: turris_omnia_mcu CMD_GET_FEATURES failed: %d\n", ret); - return ret; - } - info->features = ((u16)val[1] << 8) | val[0]; - } - - uc_priv->bank_name = "mcu_"; - - if ((info->features & FEAT_EXT_CMDS) && (info->features & FEAT_PERIPH_MCU)) - uc_priv->gpio_count = 16 + 32 + 16; - else if (info->features & FEAT_EXT_CMDS) - uc_priv->gpio_count = 16 + 32; - else - uc_priv->gpio_count = 16; - - return 0; -} - -static const struct udevice_id turris_omnia_mcu_ids[] = { - { .compatible = "cznic,turris-omnia-mcu" }, - { } -}; - -U_BOOT_DRIVER(turris_omnia_mcu) = { - .name = "turris-omnia-mcu", - .id = UCLASS_GPIO, - .ops = &turris_omnia_mcu_ops, - .probe = turris_omnia_mcu_probe, - .plat_auto = sizeof(struct turris_omnia_mcu_info), - .of_match = turris_omnia_mcu_ids, -}; diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 98043fc2ff3..6b06888454f 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -505,6 +505,17 @@ config TEST_DRV model. This should only be enabled for testing as it is not useful for anything else. +config TURRIS_OMNIA_MCU + bool "Enable Turris Omnia MCU driver" + depends on DM_I2C + depends on DM_GPIO + depends on DM_RNG + depends on SYSRESET + default y if TARGET_TURRIS_OMNIA + help + This enables support for Turris Omnia MCU connected GPIOs and + board power off. + config USB_HUB_USB251XB tristate "USB251XB Hub Controller Configuration Driver" depends on I2C diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 1522f6c3b7d..9e829905f12 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -81,6 +81,7 @@ obj-$(CONFIG_SYS_DPAA_QBMAN) += fsl_portals.o obj-$(CONFIG_TEGRA186_BPMP) += tegra186_bpmp.o obj-$(CONFIG_TEGRA_CAR) += tegra_car.o obj-$(CONFIG_TEST_DRV) += test_drv.o +obj-$(CONFIG_$(SPL_TPL_)TURRIS_OMNIA_MCU) += turris_omnia_mcu.o obj-$(CONFIG_TWL4030_LED) += twl4030_led.o obj-$(CONFIG_VEXPRESS_CONFIG) += vexpress_config.o obj-$(CONFIG_WINBOND_W83627) += winbond_w83627.o diff --git a/drivers/misc/turris_omnia_mcu.c b/drivers/misc/turris_omnia_mcu.c new file mode 100644 index 00000000000..6b2f17c0002 --- /dev/null +++ b/drivers/misc/turris_omnia_mcu.c @@ -0,0 +1,411 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 Pali Rohár <pali@kernel.org> + * Copyright (C) 2024 Marek Behún <kabel@kernel.org> + */ + +#include <common.h> +#include <console.h> +#include <dm.h> +#include <dm/lists.h> +#include <i2c.h> +#include <rng.h> +#include <sysreset.h> +#include <turris-omnia-mcu-interface.h> +#include <asm/byteorder.h> +#include <asm/gpio.h> +#include <linux/delay.h> +#include <linux/log2.h> + +#define CMD_TRNG_MAX_ENTROPY_LEN 64 + +struct turris_omnia_mcu_info { + u32 features; +}; + +static int omnia_gpio_get_function(struct udevice *dev, uint offset) +{ + struct turris_omnia_mcu_info *info = dev_get_priv(dev->parent); + + switch (offset) { + /* bank 0 */ + case 0 ... 15: + switch (offset) { + case ilog2(STS_USB30_PWRON): + case ilog2(STS_USB31_PWRON): + case ilog2(STS_ENABLE_4V5): + case ilog2(STS_BUTTON_MODE): + return GPIOF_OUTPUT; + default: + return GPIOF_INPUT; + } + + /* bank 1 - supported only when FEAT_EXT_CMDS is set */ + case (16 + 0) ... (16 + 31): + if (!(info->features & FEAT_EXT_CMDS)) + return -EINVAL; + return GPIOF_INPUT; + + /* bank 2 - supported only when FEAT_EXT_CMDS and FEAT_PERIPH_MCU is set */ + case (16 + 32 + 0) ... (16 + 32 + 15): + if (!(info->features & FEAT_EXT_CMDS)) + return -EINVAL; + if (!(info->features & FEAT_PERIPH_MCU)) + return -EINVAL; + return GPIOF_OUTPUT; + + default: + return -EINVAL; + } +} + +static int omnia_gpio_get_value(struct udevice *dev, uint offset) +{ + struct turris_omnia_mcu_info *info = dev_get_priv(dev->parent); + u32 val32; + u16 val16; + int ret; + + switch (offset) { + /* bank 0 */ + case 0 ... 15: + ret = dm_i2c_read(dev->parent, CMD_GET_STATUS_WORD, + (void *)&val16, sizeof(val16)); + if (ret) + return ret; + + return !!(le16_to_cpu(val16) & BIT(offset)); + + /* bank 1 - supported only when FEAT_EXT_CMDS is set */ + case (16 + 0) ... (16 + 31): + if (!(info->features & FEAT_EXT_CMDS)) + return -EINVAL; + + ret = dm_i2c_read(dev->parent, CMD_GET_EXT_STATUS_DWORD, + (void *)&val32, sizeof(val32)); + if (ret) + return ret; + + return !!(le32_to_cpu(val32) & BIT(offset - 16)); + + /* bank 2 - supported only when FEAT_EXT_CMDS and FEAT_PERIPH_MCU is set */ + case (16 + 32 + 0) ... (16 + 32 + 15): + if (!(info->features & FEAT_EXT_CMDS)) + return -EINVAL; + if (!(info->features & FEAT_PERIPH_MCU)) + return -EINVAL; + + ret = dm_i2c_read(dev->parent, CMD_GET_EXT_CONTROL_STATUS, + (void *)&val16, sizeof(val16)); + if (ret) + return ret; + + return !!(le16_to_cpu(val16) & BIT(offset - 16 - 32)); + + default: + return -EINVAL; + } +} + +static int omnia_gpio_set_value(struct udevice *dev, uint offset, int value) +{ + struct turris_omnia_mcu_info *info = dev_get_priv(dev->parent); + u16 valmask16[2]; + u8 valmask8[2]; + + switch (offset) { + /* bank 0 */ + case 0 ... 15: + switch (offset) { + case ilog2(STS_USB30_PWRON): + valmask8[1] = CTL_USB30_PWRON; + break; + case ilog2(STS_USB31_PWRON): + valmask8[1] = CTL_USB31_PWRON; + break; + case ilog2(STS_ENABLE_4V5): + valmask8[1] = CTL_ENABLE_4V5; + break; + case ilog2(STS_BUTTON_MODE): + valmask8[1] = CTL_BUTTON_MODE; + break; + default: + return -EINVAL; + } + + valmask8[0] = value ? valmask8[1] : 0; + + return dm_i2c_write(dev->parent, CMD_GENERAL_CONTROL, valmask8, + sizeof(valmask8)); + + /* bank 2 - supported only when FEAT_EXT_CMDS and FEAT_PERIPH_MCU is set */ + case (16 + 32 + 0) ... (16 + 32 + 15): + if (!(info->features & FEAT_EXT_CMDS)) + return -EINVAL; + if (!(info->features & FEAT_PERIPH_MCU)) + return -EINVAL; + + valmask16[1] = cpu_to_le16(BIT(offset - 16 - 32)); + valmask16[0] = value ? valmask16[1] : 0; + + return dm_i2c_write(dev->parent, CMD_EXT_CONTROL, + (void *)valmask16, sizeof(valmask16)); + + default: + return -EINVAL; + } +} + +static int omnia_gpio_direction_input(struct udevice *dev, uint offset) +{ + int ret; + + ret = omnia_gpio_get_function(dev, offset); + if (ret < 0) + return ret; + else if (ret != GPIOF_INPUT) + return -EOPNOTSUPP; + + return 0; +} + +static int omnia_gpio_direction_output(struct udevice *dev, uint offset, int value) +{ + int ret; + + ret = omnia_gpio_get_function(dev, offset); + if (ret < 0) + return ret; + else if (ret != GPIOF_OUTPUT) + return -EOPNOTSUPP; + + return omnia_gpio_set_value(dev, offset, value); +} + +static int omnia_gpio_xlate(struct udevice *dev, struct gpio_desc *desc, + struct ofnode_phandle_args *args) +{ + uint bank, gpio, flags, offset; + int ret; + + if (args->args_count != 3) + return -EINVAL; + + bank = args->args[0]; + gpio = args->args[1]; + flags = args->args[2]; + + switch (bank) { + case 0: + if (gpio >= 16) + return -EINVAL; + offset = gpio; + break; + case 1: + if (gpio >= 32) + return -EINVAL; + offset = 16 + gpio; + break; + case 2: + if (gpio >= 16) + return -EINVAL; + offset = 16 + 32 + gpio; + break; + default: + return -EINVAL; + } + + ret = omnia_gpio_get_function(dev, offset); + if (ret < 0) + return ret; + + desc->offset = offset; + desc->flags = gpio_flags_xlate(flags); + + return 0; +} + +static const struct dm_gpio_ops omnia_gpio_ops = { + .direction_input = omnia_gpio_direction_input, + .direction_output = omnia_gpio_direction_output, + .get_value = omnia_gpio_get_value, + .set_value = omnia_gpio_set_value, + .get_function = omnia_gpio_get_function, + .xlate = omnia_gpio_xlate, +}; + +static int omnia_gpio_probe(struct udevice *dev) +{ + struct turris_omnia_mcu_info *info = dev_get_priv(dev->parent); + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + + uc_priv->bank_name = "mcu_"; + + if ((info->features & FEAT_EXT_CMDS) && (info->features & FEAT_PERIPH_MCU)) + uc_priv->gpio_count = 16 + 32 + 16; + else if (info->features & FEAT_EXT_CMDS) + uc_priv->gpio_count = 16 + 32; + else + uc_priv->gpio_count = 16; + + return 0; +} + +U_BOOT_DRIVER(turris_omnia_mcu_gpio) = { + .name = "turris-omnia-mcu-gpio", + .id = UCLASS_GPIO, + .ops = &omnia_gpio_ops, + .probe = omnia_gpio_probe, +}; + +static int omnia_sysreset_request(struct udevice *dev, enum sysreset_t type) +{ + struct { + u16 magic; + u16 arg; + u32 csum; + } __packed args; + + if (type != SYSRESET_POWER_OFF) + return -EPROTONOSUPPORT; + + args.magic = CMD_POWER_OFF_MAGIC; + args.arg = CMD_POWER_OFF_POWERON_BUTTON; + args.csum = 0xba3b7212; + + return dm_i2c_write(dev->parent, CMD_POWER_OFF, (void *)&args, + sizeof(args)); +} + +static const struct sysreset_ops omnia_sysreset_ops = { + .request = omnia_sysreset_request, +}; + +U_BOOT_DRIVER(turris_omnia_mcu_sysreset) = { + .name = "turris-omnia-mcu-sysreset", + .id = UCLASS_SYSRESET, + .ops = &omnia_sysreset_ops, +}; + +static int omnia_rng_read(struct udevice *dev, void *data, size_t count) +{ + u8 buf[1 + CMD_TRNG_MAX_ENTROPY_LEN]; + size_t len; + int ret; + + while (count) { + ret = dm_i2c_read(dev->parent, CMD_TRNG_COLLECT_ENTROPY, buf, + sizeof(buf)); + if (ret) + return ret; + + len = min_t(size_t, buf[0], + min_t(size_t, CMD_TRNG_MAX_ENTROPY_LEN, count)); + + if (!len) { + /* wait 500ms (fail if interrupted), then try again */ + for (int i = 0; i < 5; ++i) { + mdelay(100); + if (ctrlc()) + return -EINTR; + } + continue; + } + + memcpy(data, &buf[1], len); + data += len; + count -= len; + } + + return 0; +} + +static const struct dm_rng_ops omnia_rng_ops = { + .read = omnia_rng_read, +}; + +U_BOOT_DRIVER(turris_omnia_mcu_trng) = { + .name = "turris-omnia-mcu-trng", + .id = UCLASS_RNG, + .ops = &omnia_rng_ops, +}; + +static int turris_omnia_mcu_bind(struct udevice *dev) +{ + /* bind MCU GPIOs as a child device */ + return device_bind_driver_to_node(dev, "turris-omnia-mcu-gpio", + "turris-omnia-mcu-gpio", + dev_ofnode(dev), NULL); +} + +static int turris_omnia_mcu_probe(struct udevice *dev) +{ + struct turris_omnia_mcu_info *info = dev_get_priv(dev); + u32 dword; + u16 word; + int ret; + + ret = dm_i2c_read(dev, CMD_GET_STATUS_WORD, (void *)&word, sizeof(word)); + if (ret < 0) { + printf("Error: turris_omnia_mcu CMD_GET_STATUS_WORD failed: %d\n", + ret); + return ret; + } + + if (le16_to_cpu(word) & STS_FEATURES_SUPPORTED) { + /* try read 32-bit features */ + ret = dm_i2c_read(dev, CMD_GET_FEATURES, (void *)&dword, + sizeof(dword)); + if (ret < 0) { + /* try read 16-bit features */ + ret = dm_i2c_read(dev, CMD_GET_FEATURES, (void *)&word, + sizeof(word)); + if (ret < 0) { + printf("Error: turris_omnia_mcu CMD_GET_FEATURES failed: %d\n", + ret); + return ret; + } + + info->features = le16_to_cpu(word); + } else { + info->features = le32_to_cpu(dword); + if (info->features & FEAT_FROM_BIT_16_INVALID) + info->features &= GENMASK(15, 0); + } + } + + /* bind sysreset if poweroff is supported */ + if (info->features & FEAT_POWEROFF_WAKEUP) { + ret = device_bind_driver_to_node(dev, + "turris-omnia-mcu-sysreset", + "turris-omnia-mcu-sysreset", + dev_ofnode(dev), NULL); + if (ret < 0) + return ret; + } + + /* bind rng if trng is supported */ + if (info->features & FEAT_TRNG) { + ret = device_bind_driver_to_node(dev, "turris-omnia-mcu-trng", + "turris-omnia-mcu-trng", + dev_ofnode(dev), NULL); + if (ret < 0) + return ret; + } + + return 0; +} + +static const struct udevice_id turris_omnia_mcu_ids[] = { + { .compatible = "cznic,turris-omnia-mcu" }, + { } +}; + +U_BOOT_DRIVER(turris_omnia_mcu) = { + .name = "turris-omnia-mcu", + .id = UCLASS_MISC, + .bind = turris_omnia_mcu_bind, + .probe = turris_omnia_mcu_probe, + .priv_auto = sizeof(struct turris_omnia_mcu_info), + .of_match = turris_omnia_mcu_ids, +}; diff --git a/drivers/phy/qcom/Kconfig b/drivers/phy/qcom/Kconfig index f4ca174805a..b9fe608c279 100644 --- a/drivers/phy/qcom/Kconfig +++ b/drivers/phy/qcom/Kconfig @@ -12,6 +12,21 @@ config PHY_QCOM_IPQ4019_USB help Support for the USB PHY-s on Qualcomm IPQ40xx SoC-s. +config PHY_QCOM_QUSB2 + tristate "Qualcomm USB QUSB2 PHY driver" + depends on PHY && ARCH_SNAPDRAGON + help + Enable this to support the Super-Speed USB transceiver on various + Qualcomm chipsets. + +config PHY_QCOM_USB_SNPS_FEMTO_V2 + tristate "Qualcomm SNPS FEMTO USB HS PHY v2" + depends on PHY && ARCH_SNAPDRAGON + help + Enable this to support the Qualcomm Synopsys DesignWare Core 7nm + High-Speed PHY driver. This driver supports the Hi-Speed PHY which + is usually paired with Synopsys DWC3 USB IPs on MSM SOCs. + config PHY_QCOM_USB_HS_28NM tristate "Qualcomm 28nm High-Speed PHY" depends on PHY && ARCH_SNAPDRAGON diff --git a/drivers/phy/qcom/Makefile b/drivers/phy/qcom/Makefile index 2113f178c0c..5f4db4a5378 100644 --- a/drivers/phy/qcom/Makefile +++ b/drivers/phy/qcom/Makefile @@ -1,4 +1,6 @@ obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o obj-$(CONFIG_MSM8916_USB_PHY) += msm8916-usbh-phy.o +obj-$(CONFIG_PHY_QCOM_QUSB2) += phy-qcom-qusb2.o +obj-$(CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2) += phy-qcom-snps-femto-v2.o obj-$(CONFIG_PHY_QCOM_USB_HS_28NM) += phy-qcom-usb-hs-28nm.o obj-$(CONFIG_PHY_QCOM_USB_SS) += phy-qcom-usb-ss.o diff --git a/drivers/phy/qcom/phy-qcom-qusb2.c b/drivers/phy/qcom/phy-qcom-qusb2.c new file mode 100644 index 00000000000..c91ba18c4ab --- /dev/null +++ b/drivers/phy/qcom/phy-qcom-qusb2.c @@ -0,0 +1,429 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023 Bhupesh Sharma <bhupesh.sharma@linaro.org> + * + * Based on Linux driver + */ + +#include <dm.h> +#include <generic-phy.h> +#include <linux/bitops.h> +#include <asm/io.h> +#include <reset.h> +#include <clk.h> +#include <linux/delay.h> + +#include <dt-bindings/phy/phy-qcom-qusb2.h> + +#define QUSB2PHY_PLL 0x0 +#define QUSB2PHY_PLL_TEST 0x04 +#define CLK_REF_SEL BIT(7) + +#define QUSB2PHY_PLL_TUNE 0x08 +#define QUSB2PHY_PLL_USER_CTL1 0x0c +#define QUSB2PHY_PLL_USER_CTL2 0x10 +#define QUSB2PHY_PLL_AUTOPGM_CTL1 0x1c +#define QUSB2PHY_PLL_PWR_CTRL 0x18 + +/* QUSB2PHY_PLL_STATUS register bits */ +#define PLL_LOCKED BIT(5) + +/* QUSB2PHY_PLL_COMMON_STATUS_ONE register bits */ +#define CORE_READY_STATUS BIT(0) + +/* QUSB2PHY_PORT_POWERDOWN register bits */ +#define CLAMP_N_EN BIT(5) +#define FREEZIO_N BIT(1) +#define POWER_DOWN BIT(0) + +/* QUSB2PHY_PWR_CTRL1 register bits */ +#define PWR_CTRL1_VREF_SUPPLY_TRIM BIT(5) +#define PWR_CTRL1_CLAMP_N_EN BIT(1) + +#define QUSB2PHY_REFCLK_ENABLE BIT(0) + +#define PHY_CLK_SCHEME_SEL BIT(0) + +/* QUSB2PHY_INTR_CTRL register bits */ +#define DMSE_INTR_HIGH_SEL BIT(4) +#define DPSE_INTR_HIGH_SEL BIT(3) +#define CHG_DET_INTR_EN BIT(2) +#define DMSE_INTR_EN BIT(1) +#define DPSE_INTR_EN BIT(0) + +/* QUSB2PHY_PLL_CORE_INPUT_OVERRIDE register bits */ +#define CORE_PLL_EN_FROM_RESET BIT(4) +#define CORE_RESET BIT(5) +#define CORE_RESET_MUX BIT(6) + +/* QUSB2PHY_IMP_CTRL1 register bits */ +#define IMP_RES_OFFSET_MASK GENMASK(5, 0) +#define IMP_RES_OFFSET_SHIFT 0x0 + +/* QUSB2PHY_PLL_BIAS_CONTROL_2 register bits */ +#define BIAS_CTRL2_RES_OFFSET_MASK GENMASK(5, 0) +#define BIAS_CTRL2_RES_OFFSET_SHIFT 0x0 + +/* QUSB2PHY_CHG_CONTROL_2 register bits */ +#define CHG_CTRL2_OFFSET_MASK GENMASK(5, 4) +#define CHG_CTRL2_OFFSET_SHIFT 0x4 + +/* QUSB2PHY_PORT_TUNE1 register bits */ +#define HSTX_TRIM_MASK GENMASK(7, 4) +#define HSTX_TRIM_SHIFT 0x4 +#define PREEMPH_WIDTH_HALF_BIT BIT(2) +#define PREEMPHASIS_EN_MASK GENMASK(1, 0) +#define PREEMPHASIS_EN_SHIFT 0x0 + +/* QUSB2PHY_PORT_TUNE2 register bits */ +#define HSDISC_TRIM_MASK GENMASK(1, 0) +#define HSDISC_TRIM_SHIFT 0x0 + +#define QUSB2PHY_PLL_ANALOG_CONTROLS_TWO 0x04 +#define QUSB2PHY_PLL_CLOCK_INVERTERS 0x18c +#define QUSB2PHY_PLL_CMODE 0x2c +#define QUSB2PHY_PLL_LOCK_DELAY 0x184 +#define QUSB2PHY_PLL_DIGITAL_TIMERS_TWO 0xb4 +#define QUSB2PHY_PLL_BIAS_CONTROL_1 0x194 +#define QUSB2PHY_PLL_BIAS_CONTROL_2 0x198 +#define QUSB2PHY_PWR_CTRL2 0x214 +#define QUSB2PHY_IMP_CTRL1 0x220 +#define QUSB2PHY_IMP_CTRL2 0x224 +#define QUSB2PHY_CHG_CTRL2 0x23c + +struct qusb2_phy_init_tbl { + unsigned int offset; + unsigned int val; + /* + * register part of layout ? + * if yes, then offset gives index in the reg-layout + */ + int in_layout; +}; + +struct qusb2_phy_cfg { + const struct qusb2_phy_init_tbl *tbl; + /* number of entries in the table */ + unsigned int tbl_num; + /* offset to PHY_CLK_SCHEME register in TCSR map */ + unsigned int clk_scheme_offset; + + /* array of registers with different offsets */ + const unsigned int *regs; + unsigned int mask_core_ready; + unsigned int disable_ctrl; + unsigned int autoresume_en; + + /* true if PHY has PLL_TEST register to select clk_scheme */ + bool has_pll_test; + + /* true if TUNE1 register must be updated by fused value, else TUNE2 */ + bool update_tune1_with_efuse; + + /* true if PHY has PLL_CORE_INPUT_OVERRIDE register to reset PLL */ + bool has_pll_override; +}; + +/* set of registers with offsets different per-PHY */ +enum qusb2phy_reg_layout { + QUSB2PHY_PLL_CORE_INPUT_OVERRIDE, + QUSB2PHY_PLL_STATUS, + QUSB2PHY_PORT_TUNE1, + QUSB2PHY_PORT_TUNE2, + QUSB2PHY_PORT_TUNE3, + QUSB2PHY_PORT_TUNE4, + QUSB2PHY_PORT_TUNE5, + QUSB2PHY_PORT_TEST1, + QUSB2PHY_PORT_TEST2, + QUSB2PHY_PORT_POWERDOWN, + QUSB2PHY_INTR_CTRL, +}; + +#define QUSB2_PHY_INIT_CFG(o, v) \ + { \ + .offset = o, .val = v, \ + } + +#define QUSB2_PHY_INIT_CFG_L(o, v) \ + { \ + .offset = o, .val = v, .in_layout = 1, \ + } + +static const struct qusb2_phy_init_tbl sm6115_init_tbl[] = { + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xf8), + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0x53), + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0x81), + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0x17), + + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TUNE, 0x30), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL1, 0x79), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL2, 0x21), + + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TEST2, 0x14), + + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_AUTOPGM_CTL1, 0x9f), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00), +}; + +static const unsigned int sm6115_regs_layout[] = { + [QUSB2PHY_PLL_STATUS] = 0x38, [QUSB2PHY_PORT_TUNE1] = 0x80, + [QUSB2PHY_PORT_TUNE2] = 0x84, [QUSB2PHY_PORT_TUNE3] = 0x88, + [QUSB2PHY_PORT_TUNE4] = 0x8c, [QUSB2PHY_PORT_TUNE5] = 0x90, + [QUSB2PHY_PORT_TEST1] = 0xb8, [QUSB2PHY_PORT_TEST2] = 0x9c, + [QUSB2PHY_PORT_POWERDOWN] = 0xb4, [QUSB2PHY_INTR_CTRL] = 0xbc, +}; + +static const struct qusb2_phy_init_tbl qusb2_v2_init_tbl[] = { + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_ANALOG_CONTROLS_TWO, 0x03), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CLOCK_INVERTERS, 0x7c), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CMODE, 0x80), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_LOCK_DELAY, 0x0a), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_DIGITAL_TIMERS_TWO, 0x19), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_BIAS_CONTROL_1, 0x40), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_BIAS_CONTROL_2, 0x20), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PWR_CTRL2, 0x21), + QUSB2_PHY_INIT_CFG(QUSB2PHY_IMP_CTRL1, 0x0), + QUSB2_PHY_INIT_CFG(QUSB2PHY_IMP_CTRL2, 0x58), + + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0x30), + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0x29), + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0xca), + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0x04), + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE5, 0x03), + + QUSB2_PHY_INIT_CFG(QUSB2PHY_CHG_CTRL2, 0x0), +}; + +static const unsigned int qusb2_v2_regs_layout[] = { + [QUSB2PHY_PLL_CORE_INPUT_OVERRIDE] = 0xa8, + [QUSB2PHY_PLL_STATUS] = 0x1a0, + [QUSB2PHY_PORT_TUNE1] = 0x240, + [QUSB2PHY_PORT_TUNE2] = 0x244, + [QUSB2PHY_PORT_TUNE3] = 0x248, + [QUSB2PHY_PORT_TUNE4] = 0x24c, + [QUSB2PHY_PORT_TUNE5] = 0x250, + [QUSB2PHY_PORT_TEST1] = 0x254, + [QUSB2PHY_PORT_TEST2] = 0x258, + [QUSB2PHY_PORT_POWERDOWN] = 0x210, + [QUSB2PHY_INTR_CTRL] = 0x230, +}; + +static const struct qusb2_phy_cfg sm6115_phy_cfg = { + .tbl = sm6115_init_tbl, + .tbl_num = ARRAY_SIZE(sm6115_init_tbl), + .regs = sm6115_regs_layout, + + .has_pll_test = true, + .disable_ctrl = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN), + .mask_core_ready = PLL_LOCKED, + .autoresume_en = BIT(3), +}; + +static const struct qusb2_phy_cfg qusb2_v2_phy_cfg = { + .tbl = qusb2_v2_init_tbl, + .tbl_num = ARRAY_SIZE(qusb2_v2_init_tbl), + .regs = qusb2_v2_regs_layout, + + .disable_ctrl = (PWR_CTRL1_VREF_SUPPLY_TRIM | PWR_CTRL1_CLAMP_N_EN | + POWER_DOWN), + .mask_core_ready = CORE_READY_STATUS, + .has_pll_override = true, + .autoresume_en = BIT(0), + .update_tune1_with_efuse = true, +}; + +/** + * struct qusb2_phy - structure holding qusb2 phy attributes + * + * @phy: generic phy + * @base: iomapped memory space for qubs2 phy + * + * @cfg_ahb_clk: AHB2PHY interface clock + * @phy_rst: phy reset control + * + * @cfg: phy config data + * @has_se_clk_scheme: indicate if PHY has single-ended ref clock scheme + */ +struct qusb2_phy { + struct phy *phy; + void __iomem *base; + + struct clk cfg_ahb_clk; + struct reset_ctl phy_rst; + + const struct qusb2_phy_cfg *cfg; + bool has_se_clk_scheme; +}; + +static inline void qusb2_phy_configure(void __iomem *base, + const unsigned int *regs, + const struct qusb2_phy_init_tbl tbl[], + int num) +{ + int i; + + for (i = 0; i < num; i++) { + if (tbl[i].in_layout) + writel(tbl[i].val, base + regs[tbl[i].offset]); + else + writel(tbl[i].val, base + tbl[i].offset); + } +} + +static int qusb2phy_do_reset(struct qusb2_phy *qphy) +{ + int ret; + + ret = reset_assert(&qphy->phy_rst); + if (ret) + return ret; + + udelay(500); + + ret = reset_deassert(&qphy->phy_rst); + if (ret) + return ret; + + return 0; +} + +static int qusb2phy_power_on(struct phy *phy) +{ + struct qusb2_phy *qphy = dev_get_priv(phy->dev); + const struct qusb2_phy_cfg *cfg = qphy->cfg; + int ret; + u32 val; + + ret = qusb2phy_do_reset(qphy); + if (ret) + return ret; + + /* Disable the PHY */ + setbits_le32(qphy->base + cfg->regs[QUSB2PHY_PORT_POWERDOWN], + qphy->cfg->disable_ctrl); + + if (cfg->has_pll_test) { + /* save reset value to override reference clock scheme later */ + val = readl(qphy->base + QUSB2PHY_PLL_TEST); + } + + qusb2_phy_configure(qphy->base, cfg->regs, cfg->tbl, cfg->tbl_num); + + /* Enable the PHY */ + clrbits_le32(qphy->base + cfg->regs[QUSB2PHY_PORT_POWERDOWN], + POWER_DOWN); + + /* Required to get phy pll lock successfully */ + udelay(150); + + if (cfg->has_pll_test) { + val |= CLK_REF_SEL; + + writel(val, qphy->base + QUSB2PHY_PLL_TEST); + + /* ensure above write is through */ + readl(qphy->base + QUSB2PHY_PLL_TEST); + } + + /* Required to get phy pll lock successfully */ + udelay(100); + + val = readb(qphy->base + cfg->regs[QUSB2PHY_PLL_STATUS]); + if (!(val & cfg->mask_core_ready)) { + pr_err("QUSB2PHY pll lock failed: status reg = %x\n", val); + ret = -EBUSY; + return ret; + } + + return 0; +} + +static int qusb2phy_power_off(struct phy *phy) +{ + struct qusb2_phy *qphy = dev_get_priv(phy->dev); + + /* Disable the PHY */ + setbits_le32(qphy->base + qphy->cfg->regs[QUSB2PHY_PORT_POWERDOWN], + qphy->cfg->disable_ctrl); + + reset_assert(&qphy->phy_rst); + + clk_disable(&qphy->cfg_ahb_clk); + + return 0; +} + +static int qusb2phy_clk_init(struct udevice *dev, struct qusb2_phy *qphy) +{ + int ret; + + /* We ignore the ref clock as we currently lack a driver for rpmcc/rpmhcc where + * it usually comes from - we assume it's always on. + */ + ret = clk_get_by_name(dev, "cfg_ahb", &qphy->cfg_ahb_clk); + if (ret == -ENOSYS || ret == -ENOENT) + return 0; + if (ret) + return ret; + + ret = clk_enable(&qphy->cfg_ahb_clk); + if (ret) + return ret; + + return 0; +} + +static int qusb2phy_probe(struct udevice *dev) +{ + struct qusb2_phy *qphy = dev_get_priv(dev); + int ret; + + qphy->base = (void __iomem *)dev_read_addr(dev); + if (IS_ERR(qphy->base)) + return PTR_ERR(qphy->base); + + ret = qusb2phy_clk_init(dev, qphy); + if (ret) { + printf("%s: Couldn't get clocks: %d\n", __func__, ret); + return ret; + } + + ret = reset_get_by_index(dev, 0, &qphy->phy_rst); + if (ret) { + printf("%s: Couldn't get resets: %d\n", __func__, ret); + return ret; + } + + qphy->cfg = (const struct qusb2_phy_cfg *)dev_get_driver_data(dev); + if (!qphy->cfg) { + printf("%s: Couldn't get driver data\n", __func__); + return -EINVAL; + } + + debug("%s success qusb phy cfg %p\n", __func__, qphy->cfg); + return 0; +} + +static struct phy_ops qusb2phy_ops = { + .power_on = qusb2phy_power_on, + .power_off = qusb2phy_power_off, +}; + +static const struct udevice_id qusb2phy_ids[] = { + { .compatible = "qcom,qusb2-phy" }, + { .compatible = "qcom,qcm2290-qusb2-phy", + .data = (ulong)&sm6115_phy_cfg }, + { .compatible = "qcom,sm6115-qusb2-phy", + .data = (ulong)&sm6115_phy_cfg }, + { .compatible = "qcom,qusb2-v2-phy", .data = (ulong)&qusb2_v2_phy_cfg }, + {} +}; + +U_BOOT_DRIVER(qcom_qusb2_phy) = { + .name = "qcom-qusb2-phy", + .id = UCLASS_PHY, + .of_match = qusb2phy_ids, + .ops = &qusb2phy_ops, + .probe = qusb2phy_probe, + .priv_auto = sizeof(struct qusb2_phy), +}; diff --git a/drivers/phy/qcom/phy-qcom-snps-femto-v2.c b/drivers/phy/qcom/phy-qcom-snps-femto-v2.c new file mode 100644 index 00000000000..a1675b664e4 --- /dev/null +++ b/drivers/phy/qcom/phy-qcom-snps-femto-v2.c @@ -0,0 +1,216 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + * Copyright (C) 2023 Bhupesh Sharma <bhupesh.sharma@linaro.org> + * + * Based on Linux driver + */ + +#include <clk.h> +#include <clk-uclass.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <dm/devres.h> +#include <generic-phy.h> +#include <malloc.h> +#include <reset.h> + +#include <asm/io.h> +#include <linux/bitops.h> +#include <linux/clk-provider.h> +#include <linux/delay.h> +#include <linux/iopoll.h> + +#define USB2_PHY_USB_PHY_UTMI_CTRL0 (0x3c) +#define SLEEPM BIT(0) +#define OPMODE_MASK GENMASK(4, 3) +#define OPMODE_NORMAL (0x00) +#define OPMODE_NONDRIVING BIT(3) +#define TERMSEL BIT(5) + +#define USB2_PHY_USB_PHY_UTMI_CTRL5 (0x50) +#define POR BIT(1) + +#define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0 (0x54) +#define SIDDQ BIT(2) +#define RETENABLEN BIT(3) +#define FSEL_MASK GENMASK(6, 4) +#define FSEL_DEFAULT (0x3 << 4) + +#define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1 (0x58) +#define VBUSVLDEXTSEL0 BIT(4) +#define PLLBTUNE BIT(5) + +#define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON2 (0x5c) +#define VREGBYPASS BIT(0) + +#define USB2_PHY_USB_PHY_HS_PHY_CTRL1 (0x60) +#define VBUSVLDEXT0 BIT(0) + +#define USB2_PHY_USB_PHY_HS_PHY_CTRL2 (0x64) +#define USB2_AUTO_RESUME BIT(0) +#define USB2_SUSPEND_N BIT(2) +#define USB2_SUSPEND_N_SEL BIT(3) + +#define USB2_PHY_USB_PHY_CFG0 (0x94) +#define UTMI_PHY_DATAPATH_CTRL_OVERRIDE_EN BIT(0) +#define UTMI_PHY_CMN_CTRL_OVERRIDE_EN BIT(1) + +#define USB2_PHY_USB_PHY_REFCLK_CTRL (0xa0) +#define REFCLK_SEL_MASK GENMASK(1, 0) +#define REFCLK_SEL_DEFAULT (0x2 << 0) + +struct qcom_snps_hsphy { + void __iomem *base; + struct clk_bulk clks; + struct reset_ctl_bulk resets; +}; + +/* + * We should just be able to use clrsetbits_le32() here, but this results + * in crashes on some boards. This is suspected to be because of some bus + * arbitration quirks with the PHY (i.e. it takes several bus clock cycles + * for the write to actually go through). The readl_relaxed() at the end will + * block until the write is completed (and all registers updated), and thus + * ensure that we don't access the PHY registers when they're in an + * undetermined state. + */ +static inline void qcom_snps_hsphy_write_mask(void __iomem *base, u32 offset, + u32 mask, u32 val) +{ + u32 reg; + + reg = readl_relaxed(base + offset); + + reg &= ~mask; + reg |= val & mask; + writel_relaxed(reg, base + offset); + + /* Ensure above write is completed */ + readl_relaxed(base + offset); +} + +static int qcom_snps_hsphy_usb_init(struct phy *phy) +{ + struct qcom_snps_hsphy *priv = dev_get_priv(phy->dev); + + qcom_snps_hsphy_write_mask(priv->base, USB2_PHY_USB_PHY_CFG0, + UTMI_PHY_CMN_CTRL_OVERRIDE_EN, + UTMI_PHY_CMN_CTRL_OVERRIDE_EN); + qcom_snps_hsphy_write_mask(priv->base, USB2_PHY_USB_PHY_UTMI_CTRL5, POR, + POR); + qcom_snps_hsphy_write_mask(priv->base, + USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0, FSEL_MASK, 0); + qcom_snps_hsphy_write_mask(priv->base, + USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1, + PLLBTUNE, PLLBTUNE); + qcom_snps_hsphy_write_mask(priv->base, USB2_PHY_USB_PHY_REFCLK_CTRL, + REFCLK_SEL_DEFAULT, REFCLK_SEL_MASK); + qcom_snps_hsphy_write_mask(priv->base, + USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1, + VBUSVLDEXTSEL0, VBUSVLDEXTSEL0); + qcom_snps_hsphy_write_mask(priv->base, USB2_PHY_USB_PHY_HS_PHY_CTRL1, + VBUSVLDEXT0, VBUSVLDEXT0); + + qcom_snps_hsphy_write_mask(priv->base, + USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON2, + VREGBYPASS, VREGBYPASS); + + qcom_snps_hsphy_write_mask(priv->base, USB2_PHY_USB_PHY_HS_PHY_CTRL2, + USB2_SUSPEND_N_SEL | USB2_SUSPEND_N, + USB2_SUSPEND_N_SEL | USB2_SUSPEND_N); + + qcom_snps_hsphy_write_mask(priv->base, USB2_PHY_USB_PHY_UTMI_CTRL0, + SLEEPM, SLEEPM); + + qcom_snps_hsphy_write_mask( + priv->base, USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0, SIDDQ, 0); + + qcom_snps_hsphy_write_mask(priv->base, USB2_PHY_USB_PHY_UTMI_CTRL5, POR, + 0); + + qcom_snps_hsphy_write_mask(priv->base, USB2_PHY_USB_PHY_HS_PHY_CTRL2, + USB2_SUSPEND_N_SEL, 0); + + qcom_snps_hsphy_write_mask(priv->base, USB2_PHY_USB_PHY_CFG0, + UTMI_PHY_CMN_CTRL_OVERRIDE_EN, 0); + + return 0; +} + +static int qcom_snps_hsphy_power_on(struct phy *phy) +{ + struct qcom_snps_hsphy *priv = dev_get_priv(phy->dev); + int ret; + + clk_enable_bulk(&priv->clks); + + ret = reset_deassert_bulk(&priv->resets); + if (ret) + return ret; + + ret = qcom_snps_hsphy_usb_init(phy); + if (ret) + return ret; + + return 0; +} + +static int qcom_snps_hsphy_power_off(struct phy *phy) +{ + struct qcom_snps_hsphy *priv = dev_get_priv(phy->dev); + + reset_assert_bulk(&priv->resets); + clk_disable_bulk(&priv->clks); + + return 0; +} + +static int qcom_snps_hsphy_phy_probe(struct udevice *dev) +{ + struct qcom_snps_hsphy *priv = dev_get_priv(dev); + int ret; + + priv->base = dev_read_addr_ptr(dev); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + ret = clk_get_bulk(dev, &priv->clks); + if (ret < 0 && ret != -ENOENT) { + printf("%s: Failed to get clocks %d\n", __func__, ret); + return ret; + } + + ret = reset_get_bulk(dev, &priv->resets); + if (ret < 0) { + printf("failed to get resets, ret = %d\n", ret); + return ret; + } + + clk_enable_bulk(&priv->clks); + reset_deassert_bulk(&priv->resets); + + return 0; +} + +static struct phy_ops qcom_snps_hsphy_phy_ops = { + .power_on = qcom_snps_hsphy_power_on, + .power_off = qcom_snps_hsphy_power_off, +}; + +static const struct udevice_id qcom_snps_hsphy_phy_ids[] = { + { .compatible = "qcom,sm8150-usb-hs-phy" }, + { .compatible = "qcom,usb-snps-hs-5nm-phy" }, + { .compatible = "qcom,usb-snps-hs-7nm-phy" }, + { .compatible = "qcom,usb-snps-femto-v2-phy" }, + {} +}; + +U_BOOT_DRIVER(qcom_usb_qcom_snps_hsphy) = { + .name = "qcom-snps-hsphy", + .id = UCLASS_PHY, + .of_match = qcom_snps_hsphy_phy_ids, + .ops = &qcom_snps_hsphy_phy_ops, + .probe = qcom_snps_hsphy_phy_probe, + .priv_auto = sizeof(struct qcom_snps_hsphy), +}; diff --git a/drivers/pinctrl/qcom/pinctrl-apq8016.c b/drivers/pinctrl/qcom/pinctrl-apq8016.c index db0e2124684..a9a00f4b081 100644 --- a/drivers/pinctrl/qcom/pinctrl-apq8016.c +++ b/drivers/pinctrl/qcom/pinctrl-apq8016.c @@ -49,7 +49,8 @@ static const char *apq8016_get_pin_name(struct udevice *dev, } } -static unsigned int apq8016_get_function_mux(unsigned int selector) +static unsigned int apq8016_get_function_mux(__maybe_unused unsigned int pin, + unsigned int selector) { return msm_pinctrl_functions[selector].val; } diff --git a/drivers/pinctrl/qcom/pinctrl-apq8096.c b/drivers/pinctrl/qcom/pinctrl-apq8096.c index 880df8fe3c7..9697cb5beb7 100644 --- a/drivers/pinctrl/qcom/pinctrl-apq8096.c +++ b/drivers/pinctrl/qcom/pinctrl-apq8096.c @@ -44,7 +44,8 @@ static const char *apq8096_get_pin_name(struct udevice *dev, } } -static unsigned int apq8096_get_function_mux(unsigned int selector) +static unsigned int apq8096_get_function_mux(__maybe_unused unsigned int pin, + unsigned int selector) { return msm_pinctrl_functions[selector].val; } diff --git a/drivers/pinctrl/qcom/pinctrl-ipq4019.c b/drivers/pinctrl/qcom/pinctrl-ipq4019.c index 74c04ab87cd..44792303133 100644 --- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c +++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c @@ -40,7 +40,8 @@ static const char *ipq4019_get_pin_name(struct udevice *dev, return pin_name; } -static unsigned int ipq4019_get_function_mux(unsigned int selector) +static unsigned int ipq4019_get_function_mux(__maybe_unused unsigned int pin, + unsigned int selector) { return msm_pinctrl_functions[selector].val; } diff --git a/drivers/pinctrl/qcom/pinctrl-qcom.c b/drivers/pinctrl/qcom/pinctrl-qcom.c index ee0624df296..909e566acf5 100644 --- a/drivers/pinctrl/qcom/pinctrl-qcom.c +++ b/drivers/pinctrl/qcom/pinctrl-qcom.c @@ -83,14 +83,14 @@ static int msm_pinmux_set(struct udevice *dev, unsigned int pin_selector, unsigned int func_selector) { struct msm_pinctrl_priv *priv = dev_get_priv(dev); + u32 func = priv->data->get_function_mux(pin_selector, func_selector); /* Always NOP for special pins, assume they're in the correct state */ if (qcom_is_special_pin(&priv->data->pin_data, pin_selector)) return 0; clrsetbits_le32(priv->base + GPIO_CONFIG_REG(priv, pin_selector), - TLMM_FUNC_SEL_MASK | TLMM_GPIO_DISABLE, - priv->data->get_function_mux(func_selector) << 2); + TLMM_FUNC_SEL_MASK | TLMM_GPIO_DISABLE, func << 2); return 0; } diff --git a/drivers/pinctrl/qcom/pinctrl-qcom.h b/drivers/pinctrl/qcom/pinctrl-qcom.h index 07f2eae9bae..49b7bfbc001 100644 --- a/drivers/pinctrl/qcom/pinctrl-qcom.h +++ b/drivers/pinctrl/qcom/pinctrl-qcom.h @@ -18,7 +18,8 @@ struct msm_pinctrl_data { int functions_count; const char *(*get_function_name)(struct udevice *dev, unsigned int selector); - unsigned int (*get_function_mux)(unsigned int selector); + unsigned int (*get_function_mux)(unsigned int pin, + unsigned int selector); const char *(*get_pin_name)(struct udevice *dev, unsigned int selector); }; diff --git a/drivers/pinctrl/qcom/pinctrl-qcs404.c b/drivers/pinctrl/qcom/pinctrl-qcs404.c index 3a2d4685997..4b7c670c90b 100644 --- a/drivers/pinctrl/qcom/pinctrl-qcs404.c +++ b/drivers/pinctrl/qcom/pinctrl-qcs404.c @@ -94,7 +94,8 @@ static const char *qcs404_get_pin_name(struct udevice *dev, } } -static unsigned int qcs404_get_function_mux(unsigned int selector) +static unsigned int qcs404_get_function_mux(__maybe_unused unsigned int pin, + unsigned int selector) { return msm_pinctrl_functions[selector].val; } diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845.c b/drivers/pinctrl/qcom/pinctrl-sdm845.c index 76bd8c4ef41..459a4329ec8 100644 --- a/drivers/pinctrl/qcom/pinctrl-sdm845.c +++ b/drivers/pinctrl/qcom/pinctrl-sdm845.c @@ -70,7 +70,8 @@ static const char *sdm845_get_pin_name(struct udevice *dev, return pin_name; } -static unsigned int sdm845_get_function_mux(unsigned int selector) +static unsigned int sdm845_get_function_mux(__maybe_unused unsigned int pin, + unsigned int selector) { return msm_pinctrl_functions[selector].val; } diff --git a/drivers/serial/serial_msm_geni.c b/drivers/serial/serial_msm_geni.c index e5c3dcffc1c..5260474fb9a 100644 --- a/drivers/serial/serial_msm_geni.c +++ b/drivers/serial/serial_msm_geni.c @@ -603,7 +603,20 @@ U_BOOT_DRIVER(serial_msm_geni) = { .priv_auto = sizeof(struct msm_serial_data), .probe = msm_serial_probe, .ops = &msm_serial_ops, - .flags = DM_FLAG_PRE_RELOC, + .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF, +}; + +static const struct udevice_id geniqup_ids[] = { + { .compatible = "qcom,geni-se-qup" }, + { } +}; + +U_BOOT_DRIVER(geni_se_qup) = { + .name = "geni-se-qup", + .id = UCLASS_NOP, + .of_match = geniqup_ids, + .bind = dm_scan_fdt_dev, + .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF, }; #ifdef CONFIG_DEBUG_UART_MSM_GENI |