diff options
Diffstat (limited to 'drivers')
95 files changed, 8213 insertions, 1288 deletions
diff --git a/drivers/Makefile b/drivers/Makefile index 9440af1b09b..0e1f58c515b 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -21,6 +21,7 @@ obj-$(CONFIG_$(PHASE_)INPUT) += input/ obj-$(CONFIG_$(PHASE_)LED) += led/ obj-$(CONFIG_$(PHASE_)MMC) += mmc/ obj-y += mtd/ +obj-$(CONFIG_MULTIPLEXER) += mux/ obj-$(CONFIG_$(PHASE_)ETH) += net/ obj-$(CONFIG_$(PHASE_)PCH) += pch/ obj-$(CONFIG_$(PHASE_)PCI) += pci/ diff --git a/drivers/bios_emulator/biosemui.h b/drivers/bios_emulator/biosemui.h index 954cd883158..739a17cae5f 100644 --- a/drivers/bios_emulator/biosemui.h +++ b/drivers/bios_emulator/biosemui.h @@ -128,6 +128,7 @@ typedef struct { u32 finalVal; } BE_portInfo; +#if defined(X86EMU_RAW_IO) #define PM_inpb(port) inb(port) #define PM_inpw(port) inw(port) #define PM_inpd(port) inl(port) @@ -135,6 +136,46 @@ typedef struct { #define PM_outpw(port, val) outw(val, port) #define PM_outpd(port, val) outl(val, port) +#else + +/* + * Until the emulator code is fixed, at least print warnings. + */ + +static inline u8 PM_inpb(u16 port) +{ + printf("x86 port 0x%x read attempt, returning 0\n", port); + return 0; +} + +static inline u16 PM_inpw(u16 port) +{ + printf("x86 port 0x%x read attempt, returning 0\n", port); + return 0; +} + +static inline u32 PM_inpd(u16 port) +{ + printf("x86 port 0x%x read attempt, returning 0\n", port); + return 0; +} + +static inline void PM_outpb(u16 port, u8 val) +{ + printf("x86 port 0x%x write attempt, ignoring\n", port); +} + +static inline void PM_outpw(u16 port, u16 val) +{ + printf("x86 port 0x%x write attempt, ignoring\n", port); +} + +static inline void PM_outpd(u16 port, u32 val) +{ + printf("x86 port 0x%x write attempt, ignoring\n", port); +} +#endif + #define LOG_inpb(port) PM_inpb(port) #define LOG_inpw(port) PM_inpw(port) #define LOG_inpd(port) PM_inpd(port) diff --git a/drivers/bios_emulator/x86emu/debug.c b/drivers/bios_emulator/x86emu/debug.c index b426dc3bc45..c63cf3d26b5 100644 --- a/drivers/bios_emulator/x86emu/debug.c +++ b/drivers/bios_emulator/x86emu/debug.c @@ -38,6 +38,8 @@ ****************************************************************************/ #include <stdarg.h> +#include <string.h> +#include <vsprintf.h> #include <linux/ctype.h> #include <linux/printk.h> #include "x86emu/x86emui.h" diff --git a/drivers/bios_emulator/x86emu/ops.c b/drivers/bios_emulator/x86emu/ops.c index 57422ec3d47..f332be5a6f5 100644 --- a/drivers/bios_emulator/x86emu/ops.c +++ b/drivers/bios_emulator/x86emu/ops.c @@ -4200,7 +4200,7 @@ void x86emuOp_call_near_IMM(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("CALL\t"); ip = (s16) fetch_word_imm(); ip += (s16) M.x86.R_IP; /* CHECK SIGN */ - DECODE_PRINTF2("%04x\n", ip); + DECODE_PRINTF2("%04x\n", (u16)ip); CALL_TRACE(M.x86.saved_cs, M.x86.saved_ip, M.x86.R_CS, ip, ""); TRACE_AND_STEP(); push_word(M.x86.R_IP); @@ -4221,7 +4221,7 @@ void x86emuOp_jump_near_IMM(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("JMP\t"); ip = (s16)fetch_word_imm(); ip += (s16)M.x86.R_IP; - DECODE_PRINTF2("%04x\n", ip); + DECODE_PRINTF2("%04x\n", (u16)ip); TRACE_AND_STEP(); M.x86.R_IP = (u16)ip; DECODE_CLEAR_SEGOVR(); diff --git a/drivers/bios_emulator/x86emu/ops2.c b/drivers/bios_emulator/x86emu/ops2.c index 32fecb34791..1ff27b2af95 100644 --- a/drivers/bios_emulator/x86emu/ops2.c +++ b/drivers/bios_emulator/x86emu/ops2.c @@ -245,10 +245,12 @@ void x86emuOp2_set_byte(u8 op2) FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF("\n"); TRACE_AND_STEP(); store_data_byte(destoffset, cond ? 0x01 : 0x00); } else { /* register to register */ destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); TRACE_AND_STEP(); *destreg = cond ? 0x01 : 0x00; } @@ -1280,7 +1282,7 @@ void x86emuOp2_bsf(u8 X86EMU_UNUSED(op2)) uint srcoffset; START_OF_INSTR(); - DECODE_PRINTF("BSF\n"); + DECODE_PRINTF("BSF\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { srcoffset = decode_rmXX_address(mod, rl); @@ -1341,7 +1343,7 @@ void x86emuOp2_bsr(u8 X86EMU_UNUSED(op2)) uint srcoffset; START_OF_INSTR(); - DECODE_PRINTF("BSF\n"); + DECODE_PRINTF("BSF\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { srcoffset = decode_rmXX_address(mod, rl); diff --git a/drivers/button/Kconfig b/drivers/button/Kconfig index 3918b05ae03..6cae16fcc8b 100644 --- a/drivers/button/Kconfig +++ b/drivers/button/Kconfig @@ -9,6 +9,17 @@ config BUTTON can provide access to board-specific buttons. Use of the device tree for configuration is encouraged. +config BUTTON_REMAP_PHONE_KEYS + bool "Remap phone keys for navigation" + depends on BUTTON + help + Enable remapping of phone keys to navigation keys. This is useful for + devices with phone keys that are not used in U-Boot. The phone keys + are remapped to the following navigation keys: + - Volume up: Up + - Volume down: Down + - Power: Enter + config BUTTON_ADC bool "Button adc" depends on BUTTON diff --git a/drivers/button/button-gpio.c b/drivers/button/button-gpio.c index 43b82d98aeb..31b85c8150e 100644 --- a/drivers/button/button-gpio.c +++ b/drivers/button/button-gpio.c @@ -20,6 +20,9 @@ static enum button_state_t button_gpio_get_state(struct udevice *dev) struct button_gpio_priv *priv = dev_get_priv(dev); int ret; + if (!priv) + return -ENODATA; + if (!dm_gpio_is_valid(&priv->gpio)) return -EREMOTEIO; ret = dm_gpio_get_value(&priv->gpio); @@ -32,6 +35,8 @@ static enum button_state_t button_gpio_get_state(struct udevice *dev) static int button_gpio_get_code(struct udevice *dev) { struct button_gpio_priv *priv = dev_get_priv(dev); + if (!priv) + return -ENODATA; int code = priv->linux_code; if (!code) @@ -51,7 +56,7 @@ static int button_gpio_probe(struct udevice *dev) return 0; ret = gpio_request_by_name(dev, "gpios", 0, &priv->gpio, GPIOD_IS_IN); - if (ret) + if (ret || !dm_gpio_is_valid(&priv->gpio)) return ret; ret = dev_read_u32(dev, "linux,code", &priv->linux_code); @@ -98,6 +103,8 @@ static int button_gpio_bind(struct udevice *parent) return ret; uc_plat = dev_get_uclass_plat(dev); uc_plat->label = label; + debug("Button '%s' bound to driver '%s'\n", label, + dev->driver->name); } return 0; diff --git a/drivers/button/button-uclass.c b/drivers/button/button-uclass.c index cda243389df..729983d5870 100644 --- a/drivers/button/button-uclass.c +++ b/drivers/button/button-uclass.c @@ -10,6 +10,7 @@ #include <button.h> #include <dm.h> #include <dm/uclass-internal.h> +#include <dt-bindings/input/linux-event-codes.h> int button_get_by_label(const char *label, struct udevice **devp) { @@ -37,14 +38,33 @@ enum button_state_t button_get_state(struct udevice *dev) return ops->get_state(dev); } +static int button_remap_phone_keys(int code) +{ + switch (code) { + case KEY_VOLUMEUP: + return KEY_UP; + case KEY_VOLUMEDOWN: + return KEY_DOWN; + case KEY_POWER: + return KEY_ENTER; + default: + return code; + } +} + int button_get_code(struct udevice *dev) { struct button_ops *ops = button_get_ops(dev); + int code; if (!ops->get_code) return -ENOSYS; - return ops->get_code(dev); + code = ops->get_code(dev); + if (CONFIG_IS_ENABLED(BUTTON_REMAP_PHONE_KEYS)) + return button_remap_phone_keys(code); + else + return code; } UCLASS_DRIVER(button) = { diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index a9937c22dcb..353ae476068 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -569,8 +569,20 @@ ulong clk_set_rate(struct clk *clk, ulong rate) return 0; ops = clk_dev_ops(clk->dev); - if (!ops->set_rate) - return -ENOSYS; + /* Try to find parents which can set rate */ + while (!ops->set_rate) { + struct clk *parent; + + if (!(clk->flags & CLK_SET_RATE_PARENT)) + return -ENOSYS; + + parent = clk_get_parent(clk); + if (IS_ERR_OR_NULL(parent) || !clk_valid(parent)) + return -ENODEV; + + clk = parent; + ops = clk_dev_ops(clk->dev); + } /* get private clock struct used for cache */ clk_get_priv(clk, &clkp); diff --git a/drivers/clk/imx/clk-fracn-gppll.c b/drivers/clk/imx/clk-fracn-gppll.c index 8f42a5cb1b7..81e19d393cf 100644 --- a/drivers/clk/imx/clk-fracn-gppll.c +++ b/drivers/clk/imx/clk-fracn-gppll.c @@ -86,6 +86,7 @@ struct clk_fracn_gppll { */ static const struct imx_fracn_gppll_rate_table fracn_tbl[] = { PLL_FRACN_GP(650000000U, 162, 50, 100, 0, 6), + PLL_FRACN_GP(600000000U, 200, 0, 1, 0, 8), PLL_FRACN_GP(594000000U, 198, 0, 1, 0, 8), PLL_FRACN_GP(560000000U, 140, 0, 1, 0, 6), PLL_FRACN_GP(498000000U, 166, 0, 1, 0, 8), @@ -93,7 +94,8 @@ static const struct imx_fracn_gppll_rate_table fracn_tbl[] = { PLL_FRACN_GP(445333333U, 167, 0, 1, 0, 9), PLL_FRACN_GP(400000000U, 200, 0, 1, 0, 12), PLL_FRACN_GP(393216000U, 163, 84, 100, 0, 10), - PLL_FRACN_GP(300000000U, 150, 0, 1, 0, 12) + PLL_FRACN_GP(300000000U, 150, 0, 1, 0, 12), + PLL_FRACN_GP(200000000U, 200, 0, 1, 0, 24) }; struct imx_fracn_gppll_clk imx_fracn_gppll = { @@ -111,6 +113,7 @@ static const struct imx_fracn_gppll_rate_table int_tbl[] = { PLL_FRACN_GP_INTEGER(1700000000U, 141, 1, 2), PLL_FRACN_GP_INTEGER(1400000000U, 175, 1, 3), PLL_FRACN_GP_INTEGER(900000000U, 150, 1, 4), + PLL_FRACN_GP_INTEGER(800000000U, 200, 1, 6), }; struct imx_fracn_gppll_clk imx_fracn_gppll_integer = { diff --git a/drivers/clk/imx/clk-imx93.c b/drivers/clk/imx/clk-imx93.c index ede36c412bf..b31e57a4a01 100644 --- a/drivers/clk/imx/clk-imx93.c +++ b/drivers/clk/imx/clk-imx93.c @@ -13,6 +13,11 @@ #include "clk.h" +#define IMX93_CLK_END 207 + +#define PLAT_IMX93 BIT(0) +#define PLAT_IMX91 BIT(1) + enum clk_sel { LOW_SPEED_IO_SEL, NON_IO_SEL, @@ -50,6 +55,7 @@ static const struct imx93_clk_root { u32 off; enum clk_sel sel; unsigned long flags; + unsigned long plat; } root_array[] = { /* a55/m33/bus critical clk for system run */ { IMX93_CLK_A55_PERIPH, "a55_periph_root", 0x0000, FAST_SEL, CLK_IS_CRITICAL }, @@ -60,7 +66,7 @@ static const struct imx93_clk_root { { IMX93_CLK_BUS_AON, "bus_aon_root", 0x0300, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL }, { IMX93_CLK_WAKEUP_AXI, "wakeup_axi_root", 0x0380, FAST_SEL, CLK_IS_CRITICAL }, { IMX93_CLK_SWO_TRACE, "swo_trace_root", 0x0400, LOW_SPEED_IO_SEL, }, - { IMX93_CLK_M33_SYSTICK, "m33_systick_root", 0x0480, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_M33_SYSTICK, "m33_systick_root", 0x0480, LOW_SPEED_IO_SEL, 0, PLAT_IMX93, }, { IMX93_CLK_FLEXIO1, "flexio1_root", 0x0500, LOW_SPEED_IO_SEL, }, { IMX93_CLK_FLEXIO2, "flexio2_root", 0x0580, LOW_SPEED_IO_SEL, }, { IMX93_CLK_LPTMR1, "lptmr1_root", 0x0700, LOW_SPEED_IO_SEL, }, @@ -117,15 +123,15 @@ static const struct imx93_clk_root { { IMX93_CLK_HSIO_ACSCAN_80M, "hsio_acscan_80m_root", 0x1f80, LOW_SPEED_IO_SEL, }, { IMX93_CLK_HSIO_ACSCAN_480M, "hsio_acscan_480m_root", 0x2000, MISC_SEL, }, { IMX93_CLK_NIC_AXI, "nic_axi_root", 0x2080, FAST_SEL, CLK_IS_CRITICAL, }, - { IMX93_CLK_ML_APB, "ml_apb_root", 0x2180, LOW_SPEED_IO_SEL, }, - { IMX93_CLK_ML, "ml_root", 0x2200, FAST_SEL, }, + { IMX93_CLK_ML_APB, "ml_apb_root", 0x2180, LOW_SPEED_IO_SEL, 0, PLAT_IMX93, }, + { IMX93_CLK_ML, "ml_root", 0x2200, FAST_SEL, 0, PLAT_IMX93, }, { IMX93_CLK_MEDIA_AXI, "media_axi_root", 0x2280, FAST_SEL, }, { IMX93_CLK_MEDIA_APB, "media_apb_root", 0x2300, LOW_SPEED_IO_SEL, }, - { IMX93_CLK_MEDIA_LDB, "media_ldb_root", 0x2380, VIDEO_SEL, }, + { IMX93_CLK_MEDIA_LDB, "media_ldb_root", 0x2380, VIDEO_SEL, 0, PLAT_IMX93, }, { IMX93_CLK_MEDIA_DISP_PIX, "media_disp_pix_root", 0x2400, VIDEO_SEL, }, { IMX93_CLK_CAM_PIX, "cam_pix_root", 0x2480, VIDEO_SEL, }, - { IMX93_CLK_MIPI_TEST_BYTE, "mipi_test_byte_root", 0x2500, VIDEO_SEL, }, - { IMX93_CLK_MIPI_PHY_CFG, "mipi_phy_cfg_root", 0x2580, VIDEO_SEL, }, + { IMX93_CLK_MIPI_TEST_BYTE, "mipi_test_byte_root", 0x2500, VIDEO_SEL, 0, PLAT_IMX93, }, + { IMX93_CLK_MIPI_PHY_CFG, "mipi_phy_cfg_root", 0x2580, VIDEO_SEL, 0, PLAT_IMX93, }, { IMX93_CLK_ADC, "adc_root", 0x2700, LOW_SPEED_IO_SEL, }, { IMX93_CLK_PDM, "pdm_root", 0x2780, AUDIO_SEL, }, { IMX93_CLK_TSTMR1, "tstmr1_root", 0x2800, LOW_SPEED_IO_SEL, }, @@ -134,13 +140,16 @@ static const struct imx93_clk_root { { IMX93_CLK_MQS2, "mqs2_root", 0x2980, AUDIO_SEL, }, { IMX93_CLK_AUDIO_XCVR, "audio_xcvr_root", 0x2a00, NON_IO_SEL, }, { IMX93_CLK_SPDIF, "spdif_root", 0x2a80, AUDIO_SEL, }, - { IMX93_CLK_ENET, "enet_root", 0x2b00, NON_IO_SEL, }, - { IMX93_CLK_ENET_TIMER1, "enet_timer1_root", 0x2b80, LOW_SPEED_IO_SEL, }, - { IMX93_CLK_ENET_TIMER2, "enet_timer2_root", 0x2c00, LOW_SPEED_IO_SEL, }, - { IMX93_CLK_ENET_REF, "enet_ref_root", 0x2c80, NON_IO_SEL, }, - { IMX93_CLK_ENET_REF_PHY, "enet_ref_phy_root", 0x2d00, LOW_SPEED_IO_SEL, }, - { IMX93_CLK_I3C1_SLOW, "i3c1_slow_root", 0x2d80, LOW_SPEED_IO_SEL, }, - { IMX93_CLK_I3C2_SLOW, "i3c2_slow_root", 0x2e00, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_ENET, "enet_root", 0x2b00, NON_IO_SEL, 0, PLAT_IMX93, }, + { IMX93_CLK_ENET_TIMER1, "enet_timer1_root", 0x2b80, LOW_SPEED_IO_SEL, 0, PLAT_IMX93, }, + { IMX93_CLK_ENET_TIMER2, "enet_timer2_root", 0x2c00, LOW_SPEED_IO_SEL, 0, PLAT_IMX93, }, + { IMX93_CLK_ENET_REF, "enet_ref_root", 0x2c80, NON_IO_SEL, 0, PLAT_IMX93, }, + { IMX93_CLK_ENET_REF_PHY, "enet_ref_phy_root", 0x2d00, LOW_SPEED_IO_SEL, 0, PLAT_IMX93, }, + { IMX91_CLK_ENET1_QOS_TSN, "enet1_qos_tsn_root", 0x2b00, NON_IO_SEL, 0, PLAT_IMX91, }, + { IMX91_CLK_ENET_TIMER, "enet_timer_root", 0x2b80, LOW_SPEED_IO_SEL, 0, PLAT_IMX91, }, + { IMX91_CLK_ENET2_REGULAR, "enet2_regular_root", 0x2c80, NON_IO_SEL, 0, PLAT_IMX91, }, + { IMX93_CLK_I3C1_SLOW, "i3c1_slow_root", 0x2d80, LOW_SPEED_IO_SEL, 0, PLAT_IMX93, }, + { IMX93_CLK_I3C2_SLOW, "i3c2_slow_root", 0x2e00, LOW_SPEED_IO_SEL, 0, PLAT_IMX93, }, { IMX93_CLK_USB_PHY_BURUNIN, "usb_phy_root", 0x2e80, LOW_SPEED_IO_SEL, }, { IMX93_CLK_PAL_CAME_SCAN, "pal_came_scan_root", 0x2f00, MISC_SEL, } }; @@ -152,6 +161,7 @@ static const struct imx93_clk_ccgr { u32 off; unsigned long flags; u32 *shared_count; + unsigned long plat; } ccgr_array[] = { { IMX93_CLK_A55_GATE, "a55_alt", "a55_alt_root", 0x8000, }, /* M33 critical clk for system run */ @@ -226,7 +236,7 @@ static const struct imx93_clk_ccgr { { IMX93_CLK_SAI3_IPG, "sai3_ipg_clk", "bus_wakeup_root", 0x94c0, 0, &share_count_sai3}, { IMX93_CLK_MIPI_CSI_GATE, "mipi_csi", "media_apb_root", 0x9580, }, { IMX93_CLK_MIPI_DSI_GATE, "mipi_dsi", "media_apb_root", 0x95c0, }, - { IMX93_CLK_LVDS_GATE, "lvds", "media_ldb_root", 0x9600, }, + { IMX93_CLK_LVDS_GATE, "lvds", "media_ldb_root", 0x9600, 0, NULL, PLAT_IMX93, }, { IMX93_CLK_LCDIF_GATE, "lcdif", "media_apb_root", 0x9640, }, { IMX93_CLK_PXP_GATE, "pxp", "media_apb_root", 0x9680, }, { IMX93_CLK_ISI_GATE, "isi", "media_apb_root", 0x96c0, }, @@ -240,8 +250,10 @@ static const struct imx93_clk_ccgr { { IMX93_CLK_AUD_XCVR_GATE, "aud_xcvr", "audio_xcvr_root", 0x9b80, }, { IMX93_CLK_SPDIF_GATE, "spdif", "spdif_root", 0x9c00, }, { IMX93_CLK_HSIO_32K_GATE, "hsio_32k", "clock-osc-24m", 0x9dc0, }, - { IMX93_CLK_ENET1_GATE, "enet1", "wakeup_axi_root", 0x9e00, }, - { IMX93_CLK_ENET_QOS_GATE, "enet_qos", "wakeup_axi_root", 0x9e40, }, + { IMX93_CLK_ENET1_GATE, "enet1", "wakeup_axi_root", 0x9e00, 0, NULL, PLAT_IMX93, }, + { IMX93_CLK_ENET_QOS_GATE, "enet_qos", "wakeup_axi_root", 0x9e40, 0, NULL, PLAT_IMX93, }, + { IMX91_CLK_ENET2_REGULAR_GATE, "enet2_regular", "wakeup_axi_root", 0x9e00, 0, NULL, PLAT_IMX91, }, + { IMX91_CLK_ENET1_QOS_TSN_GATE, "enet1_qos_tsn", "wakeup_axi_root", 0x9e40, 0, NULL, PLAT_IMX91, }, /* Critical because clk accessed during CPU idle */ { IMX93_CLK_SYS_CNT_GATE, "sys_cnt", "clock-osc-24m", 0x9e80, CLK_IS_CRITICAL}, { IMX93_CLK_TSTMR1_GATE, "tstmr1", "bus_aon_root", 0x9ec0, }, @@ -257,6 +269,7 @@ static int imx93_clk_probe(struct udevice *dev) struct clk osc_24m_clk, osc_32k_clk, ext1_clk; void __iomem *base, *anatop_base; int i, ret; + const unsigned long plat = (unsigned long)dev_get_driver_data(dev); clk_dm(IMX93_CLK_DUMMY, clk_register_fixed_rate(NULL, "dummy", 0UL)); @@ -307,6 +320,8 @@ static int imx93_clk_probe(struct udevice *dev) for (i = 0; i < ARRAY_SIZE(root_array); i++) { root = &root_array[i]; + if (root->plat && !(root->plat & plat)) + continue; clk_dm(root->clk, imx93_clk_composite_flags(root->name, parent_names[root->sel], 4, base + root->off, 3, @@ -315,6 +330,8 @@ static int imx93_clk_probe(struct udevice *dev) for (i = 0; i < ARRAY_SIZE(ccgr_array); i++) { ccgr = &ccgr_array[i]; + if (ccgr->plat && !(ccgr->plat & plat)) + continue; clk_dm(ccgr->clk, imx93_clk_gate(NULL, ccgr->name, ccgr->parent_name, ccgr->flags, base + ccgr->off, 0, 1, 1, 3, ccgr->shared_count)); @@ -328,7 +345,8 @@ static int imx93_clk_probe(struct udevice *dev) } static const struct udevice_id imx93_clk_ids[] = { - { .compatible = "fsl,imx93-ccm" }, + { .compatible = "fsl,imx93-ccm", .data = (unsigned long)PLAT_IMX93 }, + { .compatible = "fsl,imx91-ccm", .data = (unsigned long)PLAT_IMX91 }, { /* Sentinel */ }, }; diff --git a/drivers/clk/renesas/r8a779h0-cpg-mssr.c b/drivers/clk/renesas/r8a779h0-cpg-mssr.c index 2e98e262fb0..70fa8ff2871 100644 --- a/drivers/clk/renesas/r8a779h0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779h0-cpg-mssr.c @@ -39,7 +39,6 @@ enum clk_ids { CLK_PLL6, CLK_PLL7, CLK_PLL1_DIV2, - CLK_PLL2_DIV2, CLK_PLL3_DIV2, CLK_PLL4_DIV2, CLK_PLL4_DIV5, @@ -82,7 +81,6 @@ static const struct cpg_core_clk r8a779h0_core_clks[] = { DEF_BASE(".pll7", CLK_PLL7, CLK_TYPE_GEN4_PLL7, CLK_MAIN), DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), - DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 2, 1), DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 2, 1), DEF_FIXED(".pll4_div2", CLK_PLL4_DIV2, CLK_PLL4, 2, 1), DEF_FIXED(".pll4_div5", CLK_PLL4_DIV5, CLK_PLL4, 5, 1), @@ -106,10 +104,10 @@ static const struct cpg_core_clk r8a779h0_core_clks[] = { DEF_RATE(".oco", CLK_OCO, 32768), /* Core Clock Outputs */ - DEF_GEN4_Z("zc0", R8A779H0_CLK_ZC0, CLK_TYPE_GEN4_Z, CLK_PLL2_DIV2, 2, 0), - DEF_GEN4_Z("zc1", R8A779H0_CLK_ZC1, CLK_TYPE_GEN4_Z, CLK_PLL2_DIV2, 2, 8), - DEF_GEN4_Z("zc2", R8A779H0_CLK_ZC2, CLK_TYPE_GEN4_Z, CLK_PLL2_DIV2, 2, 32), - DEF_GEN4_Z("zc3", R8A779H0_CLK_ZC3, CLK_TYPE_GEN4_Z, CLK_PLL2_DIV2, 2, 40), + DEF_GEN4_Z("zc0", R8A779H0_CLK_ZC0, CLK_TYPE_GEN4_Z, CLK_PLL2, 4, 0), + DEF_GEN4_Z("zc1", R8A779H0_CLK_ZC1, CLK_TYPE_GEN4_Z, CLK_PLL2, 4, 8), + DEF_GEN4_Z("zc2", R8A779H0_CLK_ZC2, CLK_TYPE_GEN4_Z, CLK_PLL2, 4, 32), + DEF_GEN4_Z("zc3", R8A779H0_CLK_ZC3, CLK_TYPE_GEN4_Z, CLK_PLL2, 4, 40), DEF_FIXED("s0d2", R8A779H0_CLK_S0D2, CLK_S0, 2, 1), DEF_FIXED("s0d3", R8A779H0_CLK_S0D3, CLK_S0, 3, 1), DEF_FIXED("s0d4", R8A779H0_CLK_S0D4, CLK_S0, 4, 1), diff --git a/drivers/clk/starfive/clk-jh7110-pll.c b/drivers/clk/starfive/clk-jh7110-pll.c index 6d2bfb3ecb7..f8af17227c5 100644 --- a/drivers/clk/starfive/clk-jh7110-pll.c +++ b/drivers/clk/starfive/clk-jh7110-pll.c @@ -374,13 +374,13 @@ static int jh7110_pll_clk_probe(struct udevice *dev) if (sysreg == FDT_ADDR_T_NONE) return -EINVAL; - clk_dm(JH7110_PLL_ID_TRANS(JH7110_SYSCLK_PLL0_OUT), + clk_dm(JH7110_PLL_ID_TRANS(JH7110_PLLCLK_PLL0_OUT), starfive_jh7110_pll("pll0_out", "oscillator", reg, (void __iomem *)sysreg, &starfive_jh7110_pll0)); - clk_dm(JH7110_PLL_ID_TRANS(JH7110_SYSCLK_PLL1_OUT), + clk_dm(JH7110_PLL_ID_TRANS(JH7110_PLLCLK_PLL1_OUT), starfive_jh7110_pll("pll1_out", "oscillator", reg, (void __iomem *)sysreg, &starfive_jh7110_pll1)); - clk_dm(JH7110_PLL_ID_TRANS(JH7110_SYSCLK_PLL2_OUT), + clk_dm(JH7110_PLL_ID_TRANS(JH7110_PLLCLK_PLL2_OUT), starfive_jh7110_pll("pll2_out", "oscillator", reg, (void __iomem *)sysreg, &starfive_jh7110_pll2)); diff --git a/drivers/clk/starfive/clk-jh7110.c b/drivers/clk/starfive/clk-jh7110.c index 191da75d7ba..6387e949d50 100644 --- a/drivers/clk/starfive/clk-jh7110.c +++ b/drivers/clk/starfive/clk-jh7110.c @@ -495,37 +495,37 @@ static int jh7110_stgcrg_init(struct udevice *dev) { struct jh7110_clk_priv *priv = dev_get_priv(dev); - clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB_APB), + clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB0_APB), starfive_clk_gate(priv->reg, "usb_apb", "apb_bus", - OFFSET(JH7110_STGCLK_USB_APB))); - clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB_UTMI_APB), + OFFSET(JH7110_STGCLK_USB0_APB))); + clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB0_UTMI_APB), starfive_clk_gate(priv->reg, "usb_utmi_apb", "apb_bus", - OFFSET(JH7110_STGCLK_USB_UTMI_APB))); - clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB_AXI), + OFFSET(JH7110_STGCLK_USB0_UTMI_APB))); + clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB0_AXI), starfive_clk_gate(priv->reg, "usb_axi", "stg_axiahb", - OFFSET(JH7110_STGCLK_USB_AXI))); - clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB_LPM), + OFFSET(JH7110_STGCLK_USB0_AXI))); + clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB0_LPM), starfive_clk_gate_divider(priv->reg, "usb_lpm", "oscillator", - OFFSET(JH7110_STGCLK_USB_LPM), 2)); - clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB_STB), + OFFSET(JH7110_STGCLK_USB0_LPM), 2)); + clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB0_STB), starfive_clk_gate_divider(priv->reg, "usb_stb", "oscillator", - OFFSET(JH7110_STGCLK_USB_STB), 3)); - clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB_APP_125), + OFFSET(JH7110_STGCLK_USB0_STB), 3)); + clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB0_APP_125), starfive_clk_gate(priv->reg, "usb_app_125", "usb_125m", - OFFSET(JH7110_STGCLK_USB_APP_125))); - clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB_REFCLK), + OFFSET(JH7110_STGCLK_USB0_APP_125))); + clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB0_REFCLK), starfive_clk_divider(priv->reg, "usb_refclk", "oscillator", - OFFSET(JH7110_STGCLK_USB_REFCLK), 2)); - clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_PCIE0_AXI), + OFFSET(JH7110_STGCLK_USB0_REFCLK), 2)); + clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_PCIE0_AXI_MST0), starfive_clk_gate(priv->reg, "pcie0_axi", "stg_axiahb", - OFFSET(JH7110_STGCLK_PCIE0_AXI))); + OFFSET(JH7110_STGCLK_PCIE0_AXI_MST0))); clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_PCIE0_APB), starfive_clk_gate(priv->reg, "pcie0_apb", "apb_bus", @@ -534,10 +534,10 @@ static int jh7110_stgcrg_init(struct udevice *dev) starfive_clk_gate(priv->reg, "pcie0_tl", "stg_axiahb", OFFSET(JH7110_STGCLK_PCIE0_TL))); - clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_PCIE1_AXI), + clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_PCIE1_AXI_MST0), starfive_clk_gate(priv->reg, "pcie1_axi", "stg_axiahb", - OFFSET(JH7110_STGCLK_PCIE1_AXI))); + OFFSET(JH7110_STGCLK_PCIE1_AXI_MST0))); clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_PCIE1_APB), starfive_clk_gate(priv->reg, "pcie1_apb", "apb_bus", @@ -548,14 +548,14 @@ static int jh7110_stgcrg_init(struct udevice *dev) OFFSET(JH7110_STGCLK_PCIE1_TL))); /* Security clocks */ - clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_SEC_HCLK), + clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_SEC_AHB), starfive_clk_gate(priv->reg, "sec_ahb", "stg_axiahb", - OFFSET(JH7110_STGCLK_SEC_HCLK))); - clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_SEC_MISCAHB), + OFFSET(JH7110_STGCLK_SEC_AHB))); + clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_SEC_MISC_AHB), starfive_clk_gate(priv->reg, "sec_misc_ahb", "stg_axiahb", - OFFSET(JH7110_STGCLK_SEC_MISCAHB))); + OFFSET(JH7110_STGCLK_SEC_MISC_AHB))); return 0; } diff --git a/drivers/clk/ti/clk-k3-pll.c b/drivers/clk/ti/clk-k3-pll.c index b3a1b4cedb7..b775bd55faa 100644 --- a/drivers/clk/ti/clk-k3-pll.c +++ b/drivers/clk/ti/clk-k3-pll.c @@ -14,6 +14,7 @@ #include <linux/clk-provider.h> #include "k3-clk.h" #include <linux/rational.h> +#include <linux/delay.h> /* 16FFT register offsets */ #define PLL_16FFT_CFG 0x08 @@ -29,10 +30,12 @@ /* CAL STAT register bits */ #define PLL_16FFT_CAL_STAT_CAL_LOCK BIT(31) +#define PLL_16FFT_CAL_STAT_CAL_LOCK_TIMEOUT (4350U * 100U) /* CFG register bits */ #define PLL_16FFT_CFG_PLL_TYPE_SHIFT (0) #define PLL_16FFT_CFG_PLL_TYPE_MASK (0x3 << 0) +#define PLL_16FFT_CFG_PLL_TYPE_FRAC2 0 #define PLL_16FFT_CFG_PLL_TYPE_FRACF 1 /* CAL CTRL register bits */ @@ -41,14 +44,21 @@ #define PLL_16FFT_CAL_CTRL_CAL_BYP BIT(15) #define PLL_16FFT_CAL_CTRL_CAL_CNT_SHIFT 16 #define PLL_16FFT_CAL_CTRL_CAL_CNT_MASK (0x7 << 16) +#define PLL_16FFT_CAL_CTRL_CAL_IN_MASK (0xFFFU) /* CTRL register bits */ #define PLL_16FFT_CTRL_BYPASS_EN BIT(31) +#define PLL_16FFT_CTRL_BYP_ON_LOCKLOSS BIT(16) #define PLL_16FFT_CTRL_PLL_EN BIT(15) +#define PLL_16FFT_CTRL_INTL_BYP_EN BIT(8) +#define PLL_16FFT_CTRL_CLK_4PH_EN BIT(5) +#define PLL_16FFT_CTRL_CLK_POSTDIV_EN BIT(4) #define PLL_16FFT_CTRL_DSM_EN BIT(1) +#define PLL_16FFT_CTRL_DAC_EN BIT(0) /* STAT register bits */ #define PLL_16FFT_STAT_LOCK BIT(0) +#define PLL_16FFT_STAT_LOCK_TIMEOUT (150U * 100U) /* FREQ_CTRL0 bits */ #define PLL_16FFT_FREQ_CTRL0_FB_DIV_INT_MASK 0xfff @@ -62,7 +72,6 @@ /* FREQ_CTRL1 bits */ #define PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_BITS 24 #define PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_MASK 0xffffff -#define PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_SHIFT 0 /* KICK register magic values */ #define PLL_KICK0_VALUE 0x68ef3490 @@ -75,68 +84,199 @@ */ struct ti_pll_clk { struct clk clk; - void __iomem *reg; + void __iomem *base; }; #define to_clk_pll(_clk) container_of(_clk, struct ti_pll_clk, clk) -static int ti_pll_wait_for_lock(struct clk *clk) +static int ti_pll_clk_disable(struct clk *clk) { struct ti_pll_clk *pll = to_clk_pll(clk); + u32 ctrl; + + ctrl = readl(pll->base + PLL_16FFT_CTRL); + + if ((ctrl & PLL_16FFT_CTRL_PLL_EN)) { + ctrl &= ~PLL_16FFT_CTRL_PLL_EN; + writel(ctrl, pll->base + PLL_16FFT_CTRL); + + /* wait 1us */ + udelay(1); + } + + return 0; +} + +static int ti_pll_clk_enable(struct clk *clk) +{ + struct ti_pll_clk *pll = to_clk_pll(clk); + u32 ctrl; + + ctrl = readl(pll->base + PLL_16FFT_CTRL); + ctrl |= PLL_16FFT_CTRL_PLL_EN; + writel(ctrl, pll->base + PLL_16FFT_CTRL); + + /* Wait 1us */ + udelay(1); + + return 0; +} + +static bool clk_pll_16fft_check_lock(const struct ti_pll_clk *pll) +{ u32 stat; + + stat = readl(pll->base + PLL_16FFT_STAT); + return (stat & PLL_16FFT_STAT_LOCK); +} + +static bool clk_pll_16fft_check_cal_lock(const struct ti_pll_clk *pll) +{ + u32 stat; + + stat = readl(pll->base + PLL_16FFT_CAL_STAT); + return (stat & PLL_16FFT_CAL_STAT_CAL_LOCK); +} + +static void clk_pll_16fft_cal_int(const struct ti_pll_clk *pll) +{ + u32 cal; + + cal = readl(pll->base + PLL_16FFT_CAL_CTRL); + + /* Enable fast cal mode */ + cal |= PLL_16FFT_CAL_CTRL_FAST_CAL; + + /* Disable calibration bypass */ + cal &= ~PLL_16FFT_CAL_CTRL_CAL_BYP; + + /* Set CALCNT to 2 */ + cal &= ~PLL_16FFT_CAL_CTRL_CAL_CNT_MASK; + cal |= 2 << PLL_16FFT_CAL_CTRL_CAL_CNT_SHIFT; + + /* Set CAL_IN to 0 */ + cal &= ~PLL_16FFT_CAL_CTRL_CAL_IN_MASK; + + /* Note this register does not readback the written value. */ + writel(cal, pll->base + PLL_16FFT_CAL_CTRL); + + /* Wait 1us before enabling the CAL_EN field */ + udelay(1); + + cal = readl(pll->base + PLL_16FFT_CAL_CTRL); + + /* Enable calibration for FRACF */ + cal |= PLL_16FFT_CAL_CTRL_CAL_EN; + + /* Note this register does not readback the written value. */ + writel(cal, pll->base + PLL_16FFT_CAL_CTRL); +} + +static void clk_pll_16fft_disable_cal(const struct ti_pll_clk *pll) +{ + u32 cal, stat; + + cal = readl(pll->base + PLL_16FFT_CAL_CTRL); + cal &= ~PLL_16FFT_CAL_CTRL_CAL_EN; + /* Note this register does not readback the written value. */ + writel(cal, pll->base + PLL_16FFT_CAL_CTRL); + do { + stat = readl(pll->base + PLL_16FFT_CAL_STAT); + } while (stat & PLL_16FFT_CAL_STAT_CAL_LOCK); +} + +static int ti_pll_wait_for_lock(struct clk *clk) +{ + struct ti_pll_clk *pll = to_clk_pll(clk); u32 cfg; u32 cal; u32 freq_ctrl1; - int i; + unsigned int i; u32 pllfm; u32 pll_type; - int success; + u32 cal_en = 0; + bool success; - for (i = 0; i < 100000; i++) { - stat = readl(pll->reg + PLL_16FFT_STAT); - if (stat & PLL_16FFT_STAT_LOCK) { - success = 1; + /* + * Minimum VCO input freq is 5MHz, and the longest a lock should + * be consider to be timed out after 750 cycles. Be conservative + * and assume each loop takes 10 cycles and we run at a + * max of 1GHz. That gives 15000 loop cycles. We may end up waiting + * longer than necessary for timeout, but that should be ok. + */ + success = false; + for (i = 0; i < PLL_16FFT_STAT_LOCK_TIMEOUT; i++) { + if (clk_pll_16fft_check_lock(pll)) { + success = true; break; } } - /* Enable calibration if not in fractional mode of the FRACF PLL */ - freq_ctrl1 = readl(pll->reg + PLL_16FFT_FREQ_CTRL1); + /* Disable calibration in the fractional mode of the FRACF PLL based on data + * from silicon and simulation data. + */ + freq_ctrl1 = readl(pll->base + PLL_16FFT_FREQ_CTRL1); pllfm = freq_ctrl1 & PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_MASK; - pllfm >>= PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_SHIFT; - cfg = readl(pll->reg + PLL_16FFT_CFG); + + cfg = readl(pll->base + PLL_16FFT_CFG); pll_type = (cfg & PLL_16FFT_CFG_PLL_TYPE_MASK) >> PLL_16FFT_CFG_PLL_TYPE_SHIFT; - if (success && pll_type == PLL_16FFT_CFG_PLL_TYPE_FRACF && pllfm == 0) { - cal = readl(pll->reg + PLL_16FFT_CAL_CTRL); + if (success && pll_type == PLL_16FFT_CFG_PLL_TYPE_FRACF) { + cal = readl(pll->base + PLL_16FFT_CAL_CTRL); + cal_en = (cal & PLL_16FFT_CAL_CTRL_CAL_EN); + } - /* Enable calibration for FRACF */ - cal |= PLL_16FFT_CAL_CTRL_CAL_EN; + if (success && pll_type == PLL_16FFT_CFG_PLL_TYPE_FRACF && + pllfm == 0 && cal_en == 1) { + /* + * Wait for calibration lock. + * + * Lock should occur within: + * + * 170 * 2^(5+CALCNT) / PFD + * 21760 / PFD + * + * CALCNT = 2, PFD = 5-50MHz. This gives a range of 0.435mS to + * 4.35mS depending on PFD frequency. + * + * Be conservative and assume each loop takes 10 cycles and we run at a + * max of 1GHz. That gives 435000 loop cycles. We may end up waiting + * longer than necessary for timeout, but that should be ok. + * + * The recommend timeout for CALLOCK to go high is 4.35 ms + */ + success = false; + for (i = 0; i < PLL_16FFT_CAL_STAT_CAL_LOCK_TIMEOUT; i++) { + if (clk_pll_16fft_check_cal_lock(pll)) { + success = true; + break; + } + } - /* Enable fast cal mode */ - cal |= PLL_16FFT_CAL_CTRL_FAST_CAL; + /* In case of cal lock failure, operate without calibration */ + if (!success) { + debug("Failure for calibration, falling back without calibration\n"); - /* Disable calibration bypass */ - cal &= ~PLL_16FFT_CAL_CTRL_CAL_BYP; + /* Disable PLL */ + ti_pll_clk_disable(clk); - /* Set CALCNT to 2 */ - cal &= ~PLL_16FFT_CAL_CTRL_CAL_CNT_MASK; - cal |= 2 << PLL_16FFT_CAL_CTRL_CAL_CNT_SHIFT; + /* Disable Calibration */ + clk_pll_16fft_disable_cal(pll); - /* Note this register does not readback the written value. */ - writel(cal, pll->reg + PLL_16FFT_CAL_CTRL); + /* Enable PLL */ + ti_pll_clk_enable(clk); - success = 0; - for (i = 0; i < 100000; i++) { - stat = readl(pll->reg + PLL_16FFT_CAL_STAT); - if (stat & PLL_16FFT_CAL_STAT_CAL_LOCK) { - success = 1; - break; + /* Wait for PLL Lock */ + for (i = 0; i < PLL_16FFT_STAT_LOCK_TIMEOUT; i++) { + if (clk_pll_16fft_check_lock(pll)) { + success = true; + break; + } } } } - if (success == 0) { + if (!success) { printf("%s: pll (%s) failed to lock\n", __func__, clk->dev->name); return -EBUSY; @@ -156,14 +296,14 @@ static ulong ti_pll_clk_get_rate(struct clk *clk) u32 ctrl; /* Check if we are in bypass */ - ctrl = readl(pll->reg + PLL_16FFT_CTRL); + ctrl = readl(pll->base + PLL_16FFT_CTRL); if (ctrl & PLL_16FFT_CTRL_BYPASS_EN) return parent_freq; - pllm = readl(pll->reg + PLL_16FFT_FREQ_CTRL0); - pllfm = readl(pll->reg + PLL_16FFT_FREQ_CTRL1); + pllm = readl(pll->base + PLL_16FFT_FREQ_CTRL0); + pllfm = readl(pll->base + PLL_16FFT_FREQ_CTRL1); - plld = readl(pll->reg + PLL_16FFT_DIV_CTRL) & + plld = readl(pll->base + PLL_16FFT_DIV_CTRL) & PLL_16FFT_DIV_CTRL_REF_DIV_MASK; current_freq = parent_freq * pllm / plld; @@ -180,6 +320,30 @@ static ulong ti_pll_clk_get_rate(struct clk *clk) return current_freq; } +static bool ti_pll_clk_is_bypass(struct ti_pll_clk *pll) +{ + u32 ctrl; + bool ret; + + ctrl = readl(pll->base + PLL_16FFT_CTRL); + ret = (ctrl & PLL_16FFT_CTRL_BYPASS_EN) != 0; + + return ret; +} + +static void ti_pll_clk_bypass(struct ti_pll_clk *pll, bool bypass) +{ + u32 ctrl; + + ctrl = readl(pll->base + PLL_16FFT_CTRL); + if (bypass) + ctrl |= PLL_16FFT_CTRL_BYPASS_EN; + else + ctrl &= ~PLL_16FFT_CTRL_BYPASS_EN; + + writel(ctrl, pll->base + PLL_16FFT_CTRL); +} + static ulong ti_pll_clk_set_rate(struct clk *clk, ulong rate) { struct ti_pll_clk *pll = to_clk_pll(clk); @@ -187,9 +351,13 @@ static ulong ti_pll_clk_set_rate(struct clk *clk, ulong rate) u64 parent_freq = clk_get_parent_rate(clk); int ret; u32 ctrl; + u32 cfg; + u32 pll_type; unsigned long pllm; u32 pllfm = 0; unsigned long plld; + u32 freq_ctrl0; + u32 freq_ctrl1; u32 div_ctrl; u32 rem; int shift; @@ -212,16 +380,22 @@ static ulong ti_pll_clk_set_rate(struct clk *clk, ulong rate) break; } - /* Put PLL to bypass mode */ - ctrl = readl(pll->reg + PLL_16FFT_CTRL); - ctrl |= PLL_16FFT_CTRL_BYPASS_EN; - writel(ctrl, pll->reg + PLL_16FFT_CTRL); + if (!ti_pll_clk_is_bypass(pll)) { + /* Put the PLL into bypass */ + ti_pll_clk_bypass(pll, true); + } + + /* Disable the PLL */ + ti_pll_clk_disable(clk); if (rate == parent_freq) { debug("%s: put %s to bypass\n", __func__, clk->dev->name); return rate; } + cfg = readl(pll->base + PLL_16FFT_CFG); + pll_type = (cfg & PLL_16FFT_CFG_PLL_TYPE_MASK) >> PLL_16FFT_CFG_PLL_TYPE_SHIFT; + debug("%s: pre-frac-calc: rate=%u, parent_freq=%u, plld=%u, pllm=%u\n", __func__, (u32)rate, (u32)parent_freq, (u32)plld, (u32)pllm); @@ -237,31 +411,75 @@ static ulong ti_pll_clk_set_rate(struct clk *clk, ulong rate) plld = 1; } - if (pllfm) - ctrl |= PLL_16FFT_CTRL_DSM_EN; - else - ctrl &= ~PLL_16FFT_CTRL_DSM_EN; + /* Program the new rate */ + freq_ctrl0 = readl(pll->base + PLL_16FFT_FREQ_CTRL0); + freq_ctrl1 = readl(pll->base + PLL_16FFT_FREQ_CTRL1); + div_ctrl = readl(pll->base + PLL_16FFT_DIV_CTRL); + + freq_ctrl0 &= ~PLL_16FFT_FREQ_CTRL0_FB_DIV_INT_MASK; + freq_ctrl0 |= pllm; - writel(pllm, pll->reg + PLL_16FFT_FREQ_CTRL0); - writel(pllfm, pll->reg + PLL_16FFT_FREQ_CTRL1); + freq_ctrl1 &= ~PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_MASK; + freq_ctrl1 |= pllfm; /* * div_ctrl register contains other divider values, so rmw * only plld and leave existing values alone */ - div_ctrl = readl(pll->reg + PLL_16FFT_DIV_CTRL); div_ctrl &= ~PLL_16FFT_DIV_CTRL_REF_DIV_MASK; div_ctrl |= plld; - writel(div_ctrl, pll->reg + PLL_16FFT_DIV_CTRL); - ctrl &= ~PLL_16FFT_CTRL_BYPASS_EN; - ctrl |= PLL_16FFT_CTRL_PLL_EN; - writel(ctrl, pll->reg + PLL_16FFT_CTRL); + /* Make sure we have fractional support if required */ + ctrl = readl(pll->base + PLL_16FFT_CTRL); + + /* Don't use internal bypass,it is not glitch free. Always prefer glitchless bypass */ + ctrl &= ~(PLL_16FFT_CTRL_INTL_BYP_EN | PLL_16FFT_CTRL_CLK_4PH_EN); + + /* Always enable output if PLL, Always bypass if we lose lock */ + ctrl |= (PLL_16FFT_CTRL_CLK_POSTDIV_EN | PLL_16FFT_CTRL_BYP_ON_LOCKLOSS); + + /* Enable fractional support if required */ + if (pll_type == PLL_16FFT_CFG_PLL_TYPE_FRACF) { + if (pllfm != 0) + ctrl |= (PLL_16FFT_CTRL_DSM_EN | PLL_16FFT_CTRL_DAC_EN); + else + ctrl &= ~(PLL_16FFT_CTRL_DSM_EN | PLL_16FFT_CTRL_DAC_EN); + } + + /* Enable Fractional by default for PLL_16FFT_CFG_PLL_TYPE_FRAC2 */ + if (pll_type == PLL_16FFT_CFG_PLL_TYPE_FRAC2) + ctrl |= (PLL_16FFT_CTRL_DSM_EN | PLL_16FFT_CTRL_DAC_EN); + + writel(freq_ctrl0, pll->base + PLL_16FFT_FREQ_CTRL0); + writel(freq_ctrl1, pll->base + PLL_16FFT_FREQ_CTRL1); + writel(div_ctrl, pll->base + PLL_16FFT_DIV_CTRL); + writel(ctrl, pll->base + PLL_16FFT_CTRL); + + /* Configure PLL calibration*/ + if (pll_type == PLL_16FFT_CFG_PLL_TYPE_FRACF) { + if (pllfm != 0) { + /* Disable Calibration in Fractional mode */ + clk_pll_16fft_disable_cal(pll); + } else { + /* Enable Calibration in Integer mode */ + clk_pll_16fft_cal_int(pll); + } + } + + /* + * Wait at least 1 ref cycle before enabling PLL. + * Minimum VCO input frequency is 5MHz, therefore maximum + * wait time for 1 ref clock is 0.2us. + */ + udelay(1); + ti_pll_clk_enable(clk); ret = ti_pll_wait_for_lock(clk); if (ret) return ret; + ti_pll_clk_bypass(pll, false); + debug("%s: pllm=%u, plld=%u, pllfm=%u, parent_freq=%u\n", __func__, (u32)pllm, (u32)plld, (u32)pllfm, (u32)parent_freq); @@ -279,30 +497,7 @@ static ulong ti_pll_clk_set_rate(struct clk *clk, ulong rate) return current_freq; } -static int ti_pll_clk_enable(struct clk *clk) -{ - struct ti_pll_clk *pll = to_clk_pll(clk); - u32 ctrl; - - ctrl = readl(pll->reg + PLL_16FFT_CTRL); - ctrl &= ~PLL_16FFT_CTRL_BYPASS_EN; - ctrl |= PLL_16FFT_CTRL_PLL_EN; - writel(ctrl, pll->reg + PLL_16FFT_CTRL); - - return ti_pll_wait_for_lock(clk); -} - -static int ti_pll_clk_disable(struct clk *clk) -{ - struct ti_pll_clk *pll = to_clk_pll(clk); - u32 ctrl; - ctrl = readl(pll->reg + PLL_16FFT_CTRL); - ctrl |= PLL_16FFT_CTRL_BYPASS_EN; - writel(ctrl, pll->reg + PLL_16FFT_CTRL); - - return 0; -} static const struct clk_ops ti_pll_clk_ops = { .get_rate = ti_pll_clk_get_rate, @@ -323,7 +518,7 @@ struct clk *clk_register_ti_pll(const char *name, const char *parent_name, if (!pll) return ERR_PTR(-ENOMEM); - pll->reg = reg; + pll->base = reg; ret = clk_register(&pll->clk, "ti-pll-clk", name, parent_name); if (ret) { @@ -333,19 +528,19 @@ struct clk *clk_register_ti_pll(const char *name, const char *parent_name, } /* Unlock the PLL registers */ - writel(PLL_KICK0_VALUE, pll->reg + PLL_KICK0); - writel(PLL_KICK1_VALUE, pll->reg + PLL_KICK1); + writel(PLL_KICK0_VALUE, pll->base + PLL_KICK0); + writel(PLL_KICK1_VALUE, pll->base + PLL_KICK1); /* Enable all HSDIV outputs */ - cfg = readl(pll->reg + PLL_16FFT_CFG); + cfg = readl(pll->base + PLL_16FFT_CFG); for (i = 0; i < 16; i++) { hsdiv_presence_bit = BIT(16 + i); hsdiv_ctrl_offs = 0x80 + (i * 4); /* Enable HSDIV output if present */ if ((hsdiv_presence_bit & cfg) != 0UL) { - ctrl = readl(pll->reg + hsdiv_ctrl_offs); + ctrl = readl(pll->base + hsdiv_ctrl_offs); ctrl |= PLL_16FFT_HSDIV_CTRL_CLKOUT_EN; - writel(ctrl, pll->reg + hsdiv_ctrl_offs); + writel(ctrl, pll->base + hsdiv_ctrl_offs); } } diff --git a/drivers/core/of_access.c b/drivers/core/of_access.c index 77acd766262..b11e36202c1 100644 --- a/drivers/core/of_access.c +++ b/drivers/core/of_access.c @@ -666,11 +666,12 @@ int of_property_read_string_helper(const struct device_node *np, return i <= 0 ? -ENODATA : i; } -static int __of_parse_phandle_with_args(const struct device_node *np, - const char *list_name, - const char *cells_name, - int cell_count, int index, - struct of_phandle_args *out_args) +static int __of_root_parse_phandle_with_args(struct device_node *root, + const struct device_node *np, + const char *list_name, + const char *cells_name, + int cell_count, int index, + struct of_phandle_args *out_args) { const __be32 *list, *list_end; int rc = 0, cur_index = 0; @@ -706,7 +707,7 @@ static int __of_parse_phandle_with_args(const struct device_node *np, * below. */ if (cells_name || cur_index == index) { - node = of_find_node_by_phandle(NULL, phandle); + node = of_find_node_by_phandle(root, phandle); if (!node) { dm_warn("%s: could not find phandle\n", np->full_name); @@ -783,39 +784,65 @@ static int __of_parse_phandle_with_args(const struct device_node *np, return rc; } -struct device_node *of_parse_phandle(const struct device_node *np, - const char *phandle_name, int index) +struct device_node *of_root_parse_phandle(struct device_node *root, + const struct device_node *np, + const char *phandle_name, int index) { struct of_phandle_args args; if (index < 0) return NULL; - if (__of_parse_phandle_with_args(np, phandle_name, NULL, 0, index, - &args)) + if (__of_root_parse_phandle_with_args(root, np, phandle_name, NULL, 0, + index, &args)) return NULL; return args.np; } +int of_root_parse_phandle_with_args(struct device_node *root, + const struct device_node *np, + const char *list_name, const char *cells_name, + int cell_count, int index, + struct of_phandle_args *out_args) +{ + if (index < 0) + return -EINVAL; + + return __of_root_parse_phandle_with_args(root, np, list_name, cells_name, + cell_count, index, out_args); +} + +int of_root_count_phandle_with_args(struct device_node *root, + const struct device_node *np, + const char *list_name, const char *cells_name, + int cell_count) +{ + return __of_root_parse_phandle_with_args(root, np, list_name, cells_name, + cell_count, -1, NULL); +} + +struct device_node *of_parse_phandle(const struct device_node *np, + const char *phandle_name, int index) +{ + return of_root_parse_phandle(NULL, np, phandle_name, index); +} + int of_parse_phandle_with_args(const struct device_node *np, const char *list_name, const char *cells_name, int cell_count, int index, struct of_phandle_args *out_args) { - if (index < 0) - return -EINVAL; - - return __of_parse_phandle_with_args(np, list_name, cells_name, - cell_count, index, out_args); + return of_root_parse_phandle_with_args(NULL, np, list_name, cells_name, + cell_count, index, out_args); } int of_count_phandle_with_args(const struct device_node *np, const char *list_name, const char *cells_name, int cell_count) { - return __of_parse_phandle_with_args(np, list_name, cells_name, - cell_count, -1, NULL); + return of_root_count_phandle_with_args(NULL, np, list_name, cells_name, + cell_count); } static void of_alias_add(struct alias_prop *ap, struct device_node *np, diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c index 950895e72a9..c8161827d1c 100644 --- a/drivers/core/ofnode.c +++ b/drivers/core/ofnode.c @@ -879,11 +879,69 @@ int ofnode_read_string_list(ofnode node, const char *property, return count; } -static void ofnode_from_fdtdec_phandle_args(struct fdtdec_phandle_args *in, +ofnode ofnode_parse_phandle(ofnode node, const char *phandle_name, + int index) +{ + ofnode phandle; + + if (ofnode_is_np(node)) { + struct device_node *np; + + np = of_parse_phandle(ofnode_to_np(node), phandle_name, + index); + if (!np) + return ofnode_null(); + + phandle = np_to_ofnode(np); + } else { + struct fdtdec_phandle_args args; + + if (fdtdec_parse_phandle_with_args(ofnode_to_fdt(node), + ofnode_to_offset(node), + phandle_name, NULL, + 0, index, &args)) + return ofnode_null(); + + phandle = offset_to_ofnode(args.node); + } + + return phandle; +} + +ofnode oftree_parse_phandle(oftree tree, ofnode node, const char *phandle_name, + int index) +{ + ofnode phandle; + + if (ofnode_is_np(node)) { + struct device_node *np; + + np = of_root_parse_phandle(tree.np, ofnode_to_np(node), + phandle_name, index); + if (!np) + return ofnode_null(); + + phandle = np_to_ofnode(np); + } else { + struct fdtdec_phandle_args args; + + if (fdtdec_parse_phandle_with_args(tree.fdt, + ofnode_to_offset(node), + phandle_name, NULL, + 0, index, &args)) + return ofnode_null(); + + phandle = noffset_to_ofnode(node, args.node); + } + + return phandle; +} + +static void ofnode_from_fdtdec_phandle_args(ofnode node, struct fdtdec_phandle_args *in, struct ofnode_phandle_args *out) { assert(OF_MAX_PHANDLE_ARGS == MAX_PHANDLE_ARGS); - out->node = offset_to_ofnode(in->node); + out->node = noffset_to_ofnode(node, in->node); out->args_count = in->args_count; memcpy(out->args, in->args, sizeof(out->args)); } @@ -923,7 +981,40 @@ int ofnode_parse_phandle_with_args(ofnode node, const char *list_name, cell_count, index, &args); if (ret) return ret; - ofnode_from_fdtdec_phandle_args(&args, out_args); + ofnode_from_fdtdec_phandle_args(node, &args, out_args); + } + + return 0; +} + +int oftree_parse_phandle_with_args(oftree tree, ofnode node, const char *list_name, + const char *cells_name, int cell_count, + int index, + struct ofnode_phandle_args *out_args) +{ + if (ofnode_is_np(node)) { + struct of_phandle_args args; + int ret; + + ret = of_root_parse_phandle_with_args(tree.np, + ofnode_to_np(node), + list_name, cells_name, + cell_count, index, + &args); + if (ret) + return ret; + ofnode_from_of_phandle_args(&args, out_args); + } else { + struct fdtdec_phandle_args args; + int ret; + + ret = fdtdec_parse_phandle_with_args(tree.fdt, + ofnode_to_offset(node), + list_name, cells_name, + cell_count, index, &args); + if (ret) + return ret; + ofnode_from_fdtdec_phandle_args(node, &args, out_args); } return 0; @@ -941,6 +1032,18 @@ int ofnode_count_phandle_with_args(ofnode node, const char *list_name, cell_count, -1, NULL); } +int oftree_count_phandle_with_args(oftree tree, ofnode node, const char *list_name, + const char *cells_name, int cell_count) +{ + if (ofnode_is_np(node)) + return of_root_count_phandle_with_args(tree.np, ofnode_to_np(node), + list_name, cells_name, cell_count); + else + return fdtdec_parse_phandle_with_args(tree.fdt, + ofnode_to_offset(node), list_name, cells_name, + cell_count, -1, NULL); +} + ofnode ofnode_path(const char *path) { if (of_live_active()) @@ -1768,6 +1871,21 @@ const char *ofnode_options_read_str(const char *prop_name) return ofnode_read_string(uboot, prop_name); } +int ofnode_options_get_by_phandle(const char *prop_name, ofnode *nodep) +{ + ofnode uboot; + + uboot = ofnode_path("/options/u-boot"); + if (!ofnode_valid(uboot)) + return -EINVAL; + + *nodep = ofnode_parse_phandle(uboot, prop_name, 0); + if (!ofnode_valid(*nodep)) + return -EINVAL; + + return 0; +} + int ofnode_read_bootscript_address(u64 *bootscr_address, u64 *bootscr_offset) { int ret; diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c index 51262befaff..53d31b3c0bf 100644 --- a/drivers/cpu/imx8_cpu.c +++ b/drivers/cpu/imx8_cpu.c @@ -65,6 +65,14 @@ static const char *get_imx_type_str(u32 imxtype) return "93(02)";/* iMX93 900Mhz Low performance Dual core without NPU */ case MXC_CPU_IMX9301: return "93(01)";/* iMX93 900Mhz Low performance Single core without NPU */ + case MXC_CPU_IMX91: + return "91(31)";/* iMX91 11x11 Full feature */ + case MXC_CPU_IMX9121: + return "91(21)";/* iMX91 11x11 Low drive mode */ + case MXC_CPU_IMX9111: + return "91(11)";/* iMX91 9x9 Reduced feature */ + case MXC_CPU_IMX9101: + return "91(01)";/* iMX91 9x9 Specific feature */ default: return "??"; } @@ -127,6 +135,8 @@ static int cpu_imx_get_temp(struct cpu_imx_plat *plat) if (IS_ENABLED(CONFIG_IMX8)) { if (plat->cpu_rsrc == SC_R_A72) idx = 2; /* use "cpu-thermal1" device */ + } else if (IS_ENABLED(CONFIG_IMX91)) { + idx = 0; } else { idx = 1; } diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index c45481bef0b..8f7a821ebf3 100644 --- a/drivers/crypto/fsl/jr.c +++ b/drivers/crypto/fsl/jr.c @@ -654,7 +654,7 @@ static int rng_init(uint8_t sec_idx, ccsr_sec_t *sec) ret = instantiate_rng(sec_idx, sec, gen_sk); /* * entropy delay is calculated via self-test method. - * self-test are run across different volatge, temp. + * self-test are run across different voltage, temp. * if worst case value for ent_dly is identified, * loop can be skipped for that platform. */ diff --git a/drivers/ddr/imx/phy/Makefile b/drivers/ddr/imx/phy/Makefile index 592d0c6ebad..95c93ba16d5 100644 --- a/drivers/ddr/imx/phy/Makefile +++ b/drivers/ddr/imx/phy/Makefile @@ -5,5 +5,5 @@ # ifdef CONFIG_XPL_BUILD -obj-$(CONFIG_IMX_SNPS_DDR_PHY) += helper.o ddrphy_utils.o ddrphy_train.o ddrphy_csr.o +obj-$(CONFIG_IMX_SNPS_DDR_PHY) += helper.o ddrphy_utils.o ddrphy_train.o endif diff --git a/drivers/ddr/imx/phy/ddrphy_csr.c b/drivers/ddr/imx/phy/ddrphy_csr.c deleted file mode 100644 index 67dd4e7059f..00000000000 --- a/drivers/ddr/imx/phy/ddrphy_csr.c +++ /dev/null @@ -1,732 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2018 NXP - */ - -#include <linux/kernel.h> -#include <asm/arch/ddr.h> - -/* ddr phy trained csr */ -struct dram_cfg_param ddrphy_trained_csr[] = { - { 0x200b2, 0x0 }, - { 0x1200b2, 0x0 }, - { 0x2200b2, 0x0 }, - { 0x200cb, 0x0 }, - { 0x10043, 0x0 }, - { 0x110043, 0x0 }, - { 0x210043, 0x0 }, - { 0x10143, 0x0 }, - { 0x110143, 0x0 }, - { 0x210143, 0x0 }, - { 0x11043, 0x0 }, - { 0x111043, 0x0 }, - { 0x211043, 0x0 }, - { 0x11143, 0x0 }, - { 0x111143, 0x0 }, - { 0x211143, 0x0 }, - { 0x12043, 0x0 }, - { 0x112043, 0x0 }, - { 0x212043, 0x0 }, - { 0x12143, 0x0 }, - { 0x112143, 0x0 }, - { 0x212143, 0x0 }, - { 0x13043, 0x0 }, - { 0x113043, 0x0 }, - { 0x213043, 0x0 }, - { 0x13143, 0x0 }, - { 0x113143, 0x0 }, - { 0x213143, 0x0 }, - { 0x80, 0x0 }, - { 0x100080, 0x0 }, - { 0x200080, 0x0 }, - { 0x1080, 0x0 }, - { 0x101080, 0x0 }, - { 0x201080, 0x0 }, - { 0x2080, 0x0 }, - { 0x102080, 0x0 }, - { 0x202080, 0x0 }, - { 0x3080, 0x0 }, - { 0x103080, 0x0 }, - { 0x203080, 0x0 }, - { 0x4080, 0x0 }, - { 0x104080, 0x0 }, - { 0x204080, 0x0 }, - { 0x5080, 0x0 }, - { 0x105080, 0x0 }, - { 0x205080, 0x0 }, - { 0x6080, 0x0 }, - { 0x106080, 0x0 }, - { 0x206080, 0x0 }, - { 0x7080, 0x0 }, - { 0x107080, 0x0 }, - { 0x207080, 0x0 }, - { 0x8080, 0x0 }, - { 0x108080, 0x0 }, - { 0x208080, 0x0 }, - { 0x9080, 0x0 }, - { 0x109080, 0x0 }, - { 0x209080, 0x0 }, - { 0x10080, 0x0 }, - { 0x110080, 0x0 }, - { 0x210080, 0x0 }, - { 0x10180, 0x0 }, - { 0x110180, 0x0 }, - { 0x210180, 0x0 }, - { 0x11080, 0x0 }, - { 0x111080, 0x0 }, - { 0x211080, 0x0 }, - { 0x11180, 0x0 }, - { 0x111180, 0x0 }, - { 0x211180, 0x0 }, - { 0x12080, 0x0 }, - { 0x112080, 0x0 }, - { 0x212080, 0x0 }, - { 0x12180, 0x0 }, - { 0x112180, 0x0 }, - { 0x212180, 0x0 }, - { 0x13080, 0x0 }, - { 0x113080, 0x0 }, - { 0x213080, 0x0 }, - { 0x13180, 0x0 }, - { 0x113180, 0x0 }, - { 0x213180, 0x0 }, - { 0x10081, 0x0 }, - { 0x110081, 0x0 }, - { 0x210081, 0x0 }, - { 0x10181, 0x0 }, - { 0x110181, 0x0 }, - { 0x210181, 0x0 }, - { 0x11081, 0x0 }, - { 0x111081, 0x0 }, - { 0x211081, 0x0 }, - { 0x11181, 0x0 }, - { 0x111181, 0x0 }, - { 0x211181, 0x0 }, - { 0x12081, 0x0 }, - { 0x112081, 0x0 }, - { 0x212081, 0x0 }, - { 0x12181, 0x0 }, - { 0x112181, 0x0 }, - { 0x212181, 0x0 }, - { 0x13081, 0x0 }, - { 0x113081, 0x0 }, - { 0x213081, 0x0 }, - { 0x13181, 0x0 }, - { 0x113181, 0x0 }, - { 0x213181, 0x0 }, - { 0x100d0, 0x0 }, - { 0x1100d0, 0x0 }, - { 0x2100d0, 0x0 }, - { 0x101d0, 0x0 }, - { 0x1101d0, 0x0 }, - { 0x2101d0, 0x0 }, - { 0x110d0, 0x0 }, - { 0x1110d0, 0x0 }, - { 0x2110d0, 0x0 }, - { 0x111d0, 0x0 }, - { 0x1111d0, 0x0 }, - { 0x2111d0, 0x0 }, - { 0x120d0, 0x0 }, - { 0x1120d0, 0x0 }, - { 0x2120d0, 0x0 }, - { 0x121d0, 0x0 }, - { 0x1121d0, 0x0 }, - { 0x2121d0, 0x0 }, - { 0x130d0, 0x0 }, - { 0x1130d0, 0x0 }, - { 0x2130d0, 0x0 }, - { 0x131d0, 0x0 }, - { 0x1131d0, 0x0 }, - { 0x2131d0, 0x0 }, - { 0x100d1, 0x0 }, - { 0x1100d1, 0x0 }, - { 0x2100d1, 0x0 }, - { 0x101d1, 0x0 }, - { 0x1101d1, 0x0 }, - { 0x2101d1, 0x0 }, - { 0x110d1, 0x0 }, - { 0x1110d1, 0x0 }, - { 0x2110d1, 0x0 }, - { 0x111d1, 0x0 }, - { 0x1111d1, 0x0 }, - { 0x2111d1, 0x0 }, - { 0x120d1, 0x0 }, - { 0x1120d1, 0x0 }, - { 0x2120d1, 0x0 }, - { 0x121d1, 0x0 }, - { 0x1121d1, 0x0 }, - { 0x2121d1, 0x0 }, - { 0x130d1, 0x0 }, - { 0x1130d1, 0x0 }, - { 0x2130d1, 0x0 }, - { 0x131d1, 0x0 }, - { 0x1131d1, 0x0 }, - { 0x2131d1, 0x0 }, - { 0x10068, 0x0 }, - { 0x10168, 0x0 }, - { 0x10268, 0x0 }, - { 0x10368, 0x0 }, - { 0x10468, 0x0 }, - { 0x10568, 0x0 }, - { 0x10668, 0x0 }, - { 0x10768, 0x0 }, - { 0x10868, 0x0 }, - { 0x11068, 0x0 }, - { 0x11168, 0x0 }, - { 0x11268, 0x0 }, - { 0x11368, 0x0 }, - { 0x11468, 0x0 }, - { 0x11568, 0x0 }, - { 0x11668, 0x0 }, - { 0x11768, 0x0 }, - { 0x11868, 0x0 }, - { 0x12068, 0x0 }, - { 0x12168, 0x0 }, - { 0x12268, 0x0 }, - { 0x12368, 0x0 }, - { 0x12468, 0x0 }, - { 0x12568, 0x0 }, - { 0x12668, 0x0 }, - { 0x12768, 0x0 }, - { 0x12868, 0x0 }, - { 0x13068, 0x0 }, - { 0x13168, 0x0 }, - { 0x13268, 0x0 }, - { 0x13368, 0x0 }, - { 0x13468, 0x0 }, - { 0x13568, 0x0 }, - { 0x13668, 0x0 }, - { 0x13768, 0x0 }, - { 0x13868, 0x0 }, - { 0x10069, 0x0 }, - { 0x10169, 0x0 }, - { 0x10269, 0x0 }, - { 0x10369, 0x0 }, - { 0x10469, 0x0 }, - { 0x10569, 0x0 }, - { 0x10669, 0x0 }, - { 0x10769, 0x0 }, - { 0x10869, 0x0 }, - { 0x11069, 0x0 }, - { 0x11169, 0x0 }, - { 0x11269, 0x0 }, - { 0x11369, 0x0 }, - { 0x11469, 0x0 }, - { 0x11569, 0x0 }, - { 0x11669, 0x0 }, - { 0x11769, 0x0 }, - { 0x11869, 0x0 }, - { 0x12069, 0x0 }, - { 0x12169, 0x0 }, - { 0x12269, 0x0 }, - { 0x12369, 0x0 }, - { 0x12469, 0x0 }, - { 0x12569, 0x0 }, - { 0x12669, 0x0 }, - { 0x12769, 0x0 }, - { 0x12869, 0x0 }, - { 0x13069, 0x0 }, - { 0x13169, 0x0 }, - { 0x13269, 0x0 }, - { 0x13369, 0x0 }, - { 0x13469, 0x0 }, - { 0x13569, 0x0 }, - { 0x13669, 0x0 }, - { 0x13769, 0x0 }, - { 0x13869, 0x0 }, - { 0x1008c, 0x0 }, - { 0x11008c, 0x0 }, - { 0x21008c, 0x0 }, - { 0x1018c, 0x0 }, - { 0x11018c, 0x0 }, - { 0x21018c, 0x0 }, - { 0x1108c, 0x0 }, - { 0x11108c, 0x0 }, - { 0x21108c, 0x0 }, - { 0x1118c, 0x0 }, - { 0x11118c, 0x0 }, - { 0x21118c, 0x0 }, - { 0x1208c, 0x0 }, - { 0x11208c, 0x0 }, - { 0x21208c, 0x0 }, - { 0x1218c, 0x0 }, - { 0x11218c, 0x0 }, - { 0x21218c, 0x0 }, - { 0x1308c, 0x0 }, - { 0x11308c, 0x0 }, - { 0x21308c, 0x0 }, - { 0x1318c, 0x0 }, - { 0x11318c, 0x0 }, - { 0x21318c, 0x0 }, - { 0x1008d, 0x0 }, - { 0x11008d, 0x0 }, - { 0x21008d, 0x0 }, - { 0x1018d, 0x0 }, - { 0x11018d, 0x0 }, - { 0x21018d, 0x0 }, - { 0x1108d, 0x0 }, - { 0x11108d, 0x0 }, - { 0x21108d, 0x0 }, - { 0x1118d, 0x0 }, - { 0x11118d, 0x0 }, - { 0x21118d, 0x0 }, - { 0x1208d, 0x0 }, - { 0x11208d, 0x0 }, - { 0x21208d, 0x0 }, - { 0x1218d, 0x0 }, - { 0x11218d, 0x0 }, - { 0x21218d, 0x0 }, - { 0x1308d, 0x0 }, - { 0x11308d, 0x0 }, - { 0x21308d, 0x0 }, - { 0x1318d, 0x0 }, - { 0x11318d, 0x0 }, - { 0x21318d, 0x0 }, - { 0x100c0, 0x0 }, - { 0x1100c0, 0x0 }, - { 0x2100c0, 0x0 }, - { 0x101c0, 0x0 }, - { 0x1101c0, 0x0 }, - { 0x2101c0, 0x0 }, - { 0x102c0, 0x0 }, - { 0x1102c0, 0x0 }, - { 0x2102c0, 0x0 }, - { 0x103c0, 0x0 }, - { 0x1103c0, 0x0 }, - { 0x2103c0, 0x0 }, - { 0x104c0, 0x0 }, - { 0x1104c0, 0x0 }, - { 0x2104c0, 0x0 }, - { 0x105c0, 0x0 }, - { 0x1105c0, 0x0 }, - { 0x2105c0, 0x0 }, - { 0x106c0, 0x0 }, - { 0x1106c0, 0x0 }, - { 0x2106c0, 0x0 }, - { 0x107c0, 0x0 }, - { 0x1107c0, 0x0 }, - { 0x2107c0, 0x0 }, - { 0x108c0, 0x0 }, - { 0x1108c0, 0x0 }, - { 0x2108c0, 0x0 }, - { 0x110c0, 0x0 }, - { 0x1110c0, 0x0 }, - { 0x2110c0, 0x0 }, - { 0x111c0, 0x0 }, - { 0x1111c0, 0x0 }, - { 0x2111c0, 0x0 }, - { 0x112c0, 0x0 }, - { 0x1112c0, 0x0 }, - { 0x2112c0, 0x0 }, - { 0x113c0, 0x0 }, - { 0x1113c0, 0x0 }, - { 0x2113c0, 0x0 }, - { 0x114c0, 0x0 }, - { 0x1114c0, 0x0 }, - { 0x2114c0, 0x0 }, - { 0x115c0, 0x0 }, - { 0x1115c0, 0x0 }, - { 0x2115c0, 0x0 }, - { 0x116c0, 0x0 }, - { 0x1116c0, 0x0 }, - { 0x2116c0, 0x0 }, - { 0x117c0, 0x0 }, - { 0x1117c0, 0x0 }, - { 0x2117c0, 0x0 }, - { 0x118c0, 0x0 }, - { 0x1118c0, 0x0 }, - { 0x2118c0, 0x0 }, - { 0x120c0, 0x0 }, - { 0x1120c0, 0x0 }, - { 0x2120c0, 0x0 }, - { 0x121c0, 0x0 }, - { 0x1121c0, 0x0 }, - { 0x2121c0, 0x0 }, - { 0x122c0, 0x0 }, - { 0x1122c0, 0x0 }, - { 0x2122c0, 0x0 }, - { 0x123c0, 0x0 }, - { 0x1123c0, 0x0 }, - { 0x2123c0, 0x0 }, - { 0x124c0, 0x0 }, - { 0x1124c0, 0x0 }, - { 0x2124c0, 0x0 }, - { 0x125c0, 0x0 }, - { 0x1125c0, 0x0 }, - { 0x2125c0, 0x0 }, - { 0x126c0, 0x0 }, - { 0x1126c0, 0x0 }, - { 0x2126c0, 0x0 }, - { 0x127c0, 0x0 }, - { 0x1127c0, 0x0 }, - { 0x2127c0, 0x0 }, - { 0x128c0, 0x0 }, - { 0x1128c0, 0x0 }, - { 0x2128c0, 0x0 }, - { 0x130c0, 0x0 }, - { 0x1130c0, 0x0 }, - { 0x2130c0, 0x0 }, - { 0x131c0, 0x0 }, - { 0x1131c0, 0x0 }, - { 0x2131c0, 0x0 }, - { 0x132c0, 0x0 }, - { 0x1132c0, 0x0 }, - { 0x2132c0, 0x0 }, - { 0x133c0, 0x0 }, - { 0x1133c0, 0x0 }, - { 0x2133c0, 0x0 }, - { 0x134c0, 0x0 }, - { 0x1134c0, 0x0 }, - { 0x2134c0, 0x0 }, - { 0x135c0, 0x0 }, - { 0x1135c0, 0x0 }, - { 0x2135c0, 0x0 }, - { 0x136c0, 0x0 }, - { 0x1136c0, 0x0 }, - { 0x2136c0, 0x0 }, - { 0x137c0, 0x0 }, - { 0x1137c0, 0x0 }, - { 0x2137c0, 0x0 }, - { 0x138c0, 0x0 }, - { 0x1138c0, 0x0 }, - { 0x2138c0, 0x0 }, - { 0x100c1, 0x0 }, - { 0x1100c1, 0x0 }, - { 0x2100c1, 0x0 }, - { 0x101c1, 0x0 }, - { 0x1101c1, 0x0 }, - { 0x2101c1, 0x0 }, - { 0x102c1, 0x0 }, - { 0x1102c1, 0x0 }, - { 0x2102c1, 0x0 }, - { 0x103c1, 0x0 }, - { 0x1103c1, 0x0 }, - { 0x2103c1, 0x0 }, - { 0x104c1, 0x0 }, - { 0x1104c1, 0x0 }, - { 0x2104c1, 0x0 }, - { 0x105c1, 0x0 }, - { 0x1105c1, 0x0 }, - { 0x2105c1, 0x0 }, - { 0x106c1, 0x0 }, - { 0x1106c1, 0x0 }, - { 0x2106c1, 0x0 }, - { 0x107c1, 0x0 }, - { 0x1107c1, 0x0 }, - { 0x2107c1, 0x0 }, - { 0x108c1, 0x0 }, - { 0x1108c1, 0x0 }, - { 0x2108c1, 0x0 }, - { 0x110c1, 0x0 }, - { 0x1110c1, 0x0 }, - { 0x2110c1, 0x0 }, - { 0x111c1, 0x0 }, - { 0x1111c1, 0x0 }, - { 0x2111c1, 0x0 }, - { 0x112c1, 0x0 }, - { 0x1112c1, 0x0 }, - { 0x2112c1, 0x0 }, - { 0x113c1, 0x0 }, - { 0x1113c1, 0x0 }, - { 0x2113c1, 0x0 }, - { 0x114c1, 0x0 }, - { 0x1114c1, 0x0 }, - { 0x2114c1, 0x0 }, - { 0x115c1, 0x0 }, - { 0x1115c1, 0x0 }, - { 0x2115c1, 0x0 }, - { 0x116c1, 0x0 }, - { 0x1116c1, 0x0 }, - { 0x2116c1, 0x0 }, - { 0x117c1, 0x0 }, - { 0x1117c1, 0x0 }, - { 0x2117c1, 0x0 }, - { 0x118c1, 0x0 }, - { 0x1118c1, 0x0 }, - { 0x2118c1, 0x0 }, - { 0x120c1, 0x0 }, - { 0x1120c1, 0x0 }, - { 0x2120c1, 0x0 }, - { 0x121c1, 0x0 }, - { 0x1121c1, 0x0 }, - { 0x2121c1, 0x0 }, - { 0x122c1, 0x0 }, - { 0x1122c1, 0x0 }, - { 0x2122c1, 0x0 }, - { 0x123c1, 0x0 }, - { 0x1123c1, 0x0 }, - { 0x2123c1, 0x0 }, - { 0x124c1, 0x0 }, - { 0x1124c1, 0x0 }, - { 0x2124c1, 0x0 }, - { 0x125c1, 0x0 }, - { 0x1125c1, 0x0 }, - { 0x2125c1, 0x0 }, - { 0x126c1, 0x0 }, - { 0x1126c1, 0x0 }, - { 0x2126c1, 0x0 }, - { 0x127c1, 0x0 }, - { 0x1127c1, 0x0 }, - { 0x2127c1, 0x0 }, - { 0x128c1, 0x0 }, - { 0x1128c1, 0x0 }, - { 0x2128c1, 0x0 }, - { 0x130c1, 0x0 }, - { 0x1130c1, 0x0 }, - { 0x2130c1, 0x0 }, - { 0x131c1, 0x0 }, - { 0x1131c1, 0x0 }, - { 0x2131c1, 0x0 }, - { 0x132c1, 0x0 }, - { 0x1132c1, 0x0 }, - { 0x2132c1, 0x0 }, - { 0x133c1, 0x0 }, - { 0x1133c1, 0x0 }, - { 0x2133c1, 0x0 }, - { 0x134c1, 0x0 }, - { 0x1134c1, 0x0 }, - { 0x2134c1, 0x0 }, - { 0x135c1, 0x0 }, - { 0x1135c1, 0x0 }, - { 0x2135c1, 0x0 }, - { 0x136c1, 0x0 }, - { 0x1136c1, 0x0 }, - { 0x2136c1, 0x0 }, - { 0x137c1, 0x0 }, - { 0x1137c1, 0x0 }, - { 0x2137c1, 0x0 }, - { 0x138c1, 0x0 }, - { 0x1138c1, 0x0 }, - { 0x2138c1, 0x0 }, - { 0x10020, 0x0 }, - { 0x110020, 0x0 }, - { 0x210020, 0x0 }, - { 0x11020, 0x0 }, - { 0x111020, 0x0 }, - { 0x211020, 0x0 }, - { 0x12020, 0x0 }, - { 0x112020, 0x0 }, - { 0x212020, 0x0 }, - { 0x13020, 0x0 }, - { 0x113020, 0x0 }, - { 0x213020, 0x0 }, - { 0x20072, 0x0 }, - { 0x20073, 0x0 }, - { 0x20074, 0x0 }, - { 0x100aa, 0x0 }, - { 0x110aa, 0x0 }, - { 0x120aa, 0x0 }, - { 0x130aa, 0x0 }, - { 0x20010, 0x0 }, - { 0x120010, 0x0 }, - { 0x220010, 0x0 }, - { 0x20011, 0x0 }, - { 0x120011, 0x0 }, - { 0x220011, 0x0 }, - { 0x100ae, 0x0 }, - { 0x1100ae, 0x0 }, - { 0x2100ae, 0x0 }, - { 0x100af, 0x0 }, - { 0x1100af, 0x0 }, - { 0x2100af, 0x0 }, - { 0x110ae, 0x0 }, - { 0x1110ae, 0x0 }, - { 0x2110ae, 0x0 }, - { 0x110af, 0x0 }, - { 0x1110af, 0x0 }, - { 0x2110af, 0x0 }, - { 0x120ae, 0x0 }, - { 0x1120ae, 0x0 }, - { 0x2120ae, 0x0 }, - { 0x120af, 0x0 }, - { 0x1120af, 0x0 }, - { 0x2120af, 0x0 }, - { 0x130ae, 0x0 }, - { 0x1130ae, 0x0 }, - { 0x2130ae, 0x0 }, - { 0x130af, 0x0 }, - { 0x1130af, 0x0 }, - { 0x2130af, 0x0 }, - { 0x20020, 0x0 }, - { 0x120020, 0x0 }, - { 0x220020, 0x0 }, - { 0x100a0, 0x0 }, - { 0x100a1, 0x0 }, - { 0x100a2, 0x0 }, - { 0x100a3, 0x0 }, - { 0x100a4, 0x0 }, - { 0x100a5, 0x0 }, - { 0x100a6, 0x0 }, - { 0x100a7, 0x0 }, - { 0x110a0, 0x0 }, - { 0x110a1, 0x0 }, - { 0x110a2, 0x0 }, - { 0x110a3, 0x0 }, - { 0x110a4, 0x0 }, - { 0x110a5, 0x0 }, - { 0x110a6, 0x0 }, - { 0x110a7, 0x0 }, - { 0x120a0, 0x0 }, - { 0x120a1, 0x0 }, - { 0x120a2, 0x0 }, - { 0x120a3, 0x0 }, - { 0x120a4, 0x0 }, - { 0x120a5, 0x0 }, - { 0x120a6, 0x0 }, - { 0x120a7, 0x0 }, - { 0x130a0, 0x0 }, - { 0x130a1, 0x0 }, - { 0x130a2, 0x0 }, - { 0x130a3, 0x0 }, - { 0x130a4, 0x0 }, - { 0x130a5, 0x0 }, - { 0x130a6, 0x0 }, - { 0x130a7, 0x0 }, - { 0x2007c, 0x0 }, - { 0x12007c, 0x0 }, - { 0x22007c, 0x0 }, - { 0x2007d, 0x0 }, - { 0x12007d, 0x0 }, - { 0x22007d, 0x0 }, - { 0x400fd, 0x0 }, - { 0x400c0, 0x0 }, - { 0x90201, 0x0 }, - { 0x190201, 0x0 }, - { 0x290201, 0x0 }, - { 0x90202, 0x0 }, - { 0x190202, 0x0 }, - { 0x290202, 0x0 }, - { 0x90203, 0x0 }, - { 0x190203, 0x0 }, - { 0x290203, 0x0 }, - { 0x90204, 0x0 }, - { 0x190204, 0x0 }, - { 0x290204, 0x0 }, - { 0x90205, 0x0 }, - { 0x190205, 0x0 }, - { 0x290205, 0x0 }, - { 0x90206, 0x0 }, - { 0x190206, 0x0 }, - { 0x290206, 0x0 }, - { 0x90207, 0x0 }, - { 0x190207, 0x0 }, - { 0x290207, 0x0 }, - { 0x90208, 0x0 }, - { 0x190208, 0x0 }, - { 0x290208, 0x0 }, - { 0x10062, 0x0 }, - { 0x10162, 0x0 }, - { 0x10262, 0x0 }, - { 0x10362, 0x0 }, - { 0x10462, 0x0 }, - { 0x10562, 0x0 }, - { 0x10662, 0x0 }, - { 0x10762, 0x0 }, - { 0x10862, 0x0 }, - { 0x11062, 0x0 }, - { 0x11162, 0x0 }, - { 0x11262, 0x0 }, - { 0x11362, 0x0 }, - { 0x11462, 0x0 }, - { 0x11562, 0x0 }, - { 0x11662, 0x0 }, - { 0x11762, 0x0 }, - { 0x11862, 0x0 }, - { 0x12062, 0x0 }, - { 0x12162, 0x0 }, - { 0x12262, 0x0 }, - { 0x12362, 0x0 }, - { 0x12462, 0x0 }, - { 0x12562, 0x0 }, - { 0x12662, 0x0 }, - { 0x12762, 0x0 }, - { 0x12862, 0x0 }, - { 0x13062, 0x0 }, - { 0x13162, 0x0 }, - { 0x13262, 0x0 }, - { 0x13362, 0x0 }, - { 0x13462, 0x0 }, - { 0x13562, 0x0 }, - { 0x13662, 0x0 }, - { 0x13762, 0x0 }, - { 0x13862, 0x0 }, - { 0x20077, 0x0 }, - { 0x10001, 0x0 }, - { 0x11001, 0x0 }, - { 0x12001, 0x0 }, - { 0x13001, 0x0 }, - { 0x10040, 0x0 }, - { 0x10140, 0x0 }, - { 0x10240, 0x0 }, - { 0x10340, 0x0 }, - { 0x10440, 0x0 }, - { 0x10540, 0x0 }, - { 0x10640, 0x0 }, - { 0x10740, 0x0 }, - { 0x10840, 0x0 }, - { 0x10030, 0x0 }, - { 0x10130, 0x0 }, - { 0x10230, 0x0 }, - { 0x10330, 0x0 }, - { 0x10430, 0x0 }, - { 0x10530, 0x0 }, - { 0x10630, 0x0 }, - { 0x10730, 0x0 }, - { 0x10830, 0x0 }, - { 0x11040, 0x0 }, - { 0x11140, 0x0 }, - { 0x11240, 0x0 }, - { 0x11340, 0x0 }, - { 0x11440, 0x0 }, - { 0x11540, 0x0 }, - { 0x11640, 0x0 }, - { 0x11740, 0x0 }, - { 0x11840, 0x0 }, - { 0x11030, 0x0 }, - { 0x11130, 0x0 }, - { 0x11230, 0x0 }, - { 0x11330, 0x0 }, - { 0x11430, 0x0 }, - { 0x11530, 0x0 }, - { 0x11630, 0x0 }, - { 0x11730, 0x0 }, - { 0x11830, 0x0 }, - { 0x12040, 0x0 }, - { 0x12140, 0x0 }, - { 0x12240, 0x0 }, - { 0x12340, 0x0 }, - { 0x12440, 0x0 }, - { 0x12540, 0x0 }, - { 0x12640, 0x0 }, - { 0x12740, 0x0 }, - { 0x12840, 0x0 }, - { 0x12030, 0x0 }, - { 0x12130, 0x0 }, - { 0x12230, 0x0 }, - { 0x12330, 0x0 }, - { 0x12430, 0x0 }, - { 0x12530, 0x0 }, - { 0x12630, 0x0 }, - { 0x12730, 0x0 }, - { 0x12830, 0x0 }, - { 0x13040, 0x0 }, - { 0x13140, 0x0 }, - { 0x13240, 0x0 }, - { 0x13340, 0x0 }, - { 0x13440, 0x0 }, - { 0x13540, 0x0 }, - { 0x13640, 0x0 }, - { 0x13740, 0x0 }, - { 0x13840, 0x0 }, - { 0x13030, 0x0 }, - { 0x13130, 0x0 }, - { 0x13230, 0x0 }, - { 0x13330, 0x0 }, - { 0x13430, 0x0 }, - { 0x13530, 0x0 }, - { 0x13630, 0x0 }, - { 0x13730, 0x0 }, - { 0x13830, 0x0 }, -}; - -uint32_t ddrphy_trained_csr_num = ARRAY_SIZE(ddrphy_trained_csr); diff --git a/drivers/ddr/imx/phy/ddrphy_train.c b/drivers/ddr/imx/phy/ddrphy_train.c index 2a2161dec33..1a2d071d6f1 100644 --- a/drivers/ddr/imx/phy/ddrphy_train.c +++ b/drivers/ddr/imx/phy/ddrphy_train.c @@ -90,7 +90,8 @@ int ddr_cfg_phy(struct dram_timing_info *dram_timing) } /* save the ddr PHY trained CSR in memory for low power use */ - ddrphy_trained_csr_save(ddrphy_trained_csr, ddrphy_trained_csr_num); + ddrphy_trained_csr_save(dram_timing->ddrphy_trained_csr, + dram_timing->ddrphy_trained_csr_num); return 0; } diff --git a/drivers/ddr/imx/phy/ddrphy_utils.c b/drivers/ddr/imx/phy/ddrphy_utils.c index 14278f5ad8f..8e350de8315 100644 --- a/drivers/ddr/imx/phy/ddrphy_utils.c +++ b/drivers/ddr/imx/phy/ddrphy_utils.c @@ -144,6 +144,10 @@ void ddrphy_init_set_dfi_clk(unsigned int drate) dram_pll_init(MHZ(400)); dram_disable_bypass(); break; + case 1200: + dram_pll_init(MHZ(300)); + dram_disable_bypass(); + break; case 1066: dram_pll_init(MHZ(266)); dram_disable_bypass(); @@ -152,6 +156,10 @@ void ddrphy_init_set_dfi_clk(unsigned int drate) dram_pll_init(MHZ(233)); dram_disable_bypass(); break; + case 800: + dram_pll_init(MHZ(200)); + dram_disable_bypass(); + break; case 667: dram_pll_init(MHZ(167)); dram_disable_bypass(); diff --git a/drivers/ddr/imx/phy/helper.c b/drivers/ddr/imx/phy/helper.c index c1fc800f191..b0dfc3a0b4f 100644 --- a/drivers/ddr/imx/phy/helper.c +++ b/drivers/ddr/imx/phy/helper.c @@ -181,7 +181,7 @@ void *dram_config_save(struct dram_timing_info *timing_info, unsigned long saved saved_timing->ddrc_cfg_num = timing_info->ddrc_cfg_num; saved_timing->ddrphy_cfg_num = timing_info->ddrphy_cfg_num; - saved_timing->ddrphy_trained_csr_num = ddrphy_trained_csr_num; + saved_timing->ddrphy_trained_csr_num = timing_info->ddrphy_trained_csr_num; saved_timing->ddrphy_pie_num = timing_info->ddrphy_pie_num; /* save the fsp table */ @@ -209,9 +209,9 @@ void *dram_config_save(struct dram_timing_info *timing_info, unsigned long saved /* save the ddrphy csr */ saved_timing->ddrphy_trained_csr = cfg; - for (i = 0; i < ddrphy_trained_csr_num; i++) { - cfg->reg = ddrphy_trained_csr[i].reg; - cfg->val = ddrphy_trained_csr[i].val; + for (i = 0; i < timing_info->ddrphy_trained_csr_num; i++) { + cfg->reg = timing_info->ddrphy_trained_csr[i].reg; + cfg->val = timing_info->ddrphy_trained_csr[i].val; cfg++; } diff --git a/drivers/gpio/at91_gpio.c b/drivers/gpio/at91_gpio.c index 50a69815907..76fcd3fb930 100644 --- a/drivers/gpio/at91_gpio.c +++ b/drivers/gpio/at91_gpio.c @@ -219,6 +219,44 @@ static bool at91_get_port_output(struct at91_port *at91_port, int offset) val = readl(&at91_port->osr); return val & mask; } + +static bool at91_is_port_gpio(struct at91_port *at91_port, int offset) +{ + u32 mask, val; + + mask = 1 << offset; + val = readl(&at91_port->psr); + return !!(val & mask); +} + +static void at91_set_port_multi_drive(struct at91_port *at91_port, int offset, int is_on) +{ + u32 mask; + + mask = 1 << offset; + if (is_on) + writel(mask, &at91_port->mder); + else + writel(mask, &at91_port->mddr); +} + +static bool at91_get_port_multi_drive(struct at91_port *at91_port, int offset) +{ + u32 mask, val; + + mask = 1 << offset; + val = readl(&at91_port->mdsr); + return !!(val & mask); +} + +static bool at91_get_port_pullup(struct at91_port *at91_port, int offset) +{ + u32 mask, val; + + mask = 1 << offset; + val = readl(&at91_port->pusr); + return !(val & mask); +} #endif static void at91_set_port_input(struct at91_port *at91_port, int offset, @@ -549,13 +587,68 @@ static int at91_gpio_get_function(struct udevice *dev, unsigned offset) { struct at91_port_priv *port = dev_get_priv(dev); - /* GPIOF_FUNC is not implemented yet */ + if (!at91_is_port_gpio(port->regs, offset)) + return GPIOF_FUNC; + if (at91_get_port_output(port->regs, offset)) return GPIOF_OUTPUT; else return GPIOF_INPUT; } +static int at91_gpio_set_flags(struct udevice *dev, unsigned int offset, + ulong flags) +{ + struct at91_port_priv *port = dev_get_priv(dev); + ulong supported_mask; + + supported_mask = GPIOD_OPEN_DRAIN | GPIOD_MASK_DIR | GPIOD_PULL_UP; + if (flags & ~supported_mask) + return -ENOTSUPP; + + if (flags & GPIOD_IS_OUT) { + if (flags & GPIOD_OPEN_DRAIN) + at91_set_port_multi_drive(port->regs, offset, true); + else + at91_set_port_multi_drive(port->regs, offset, false); + + at91_set_port_output(port->regs, offset, flags & GPIOD_IS_OUT_ACTIVE); + + } else if (flags & GPIOD_IS_IN) { + at91_set_port_input(port->regs, offset, false); + } + if (flags & GPIOD_PULL_UP) + at91_set_port_pullup(port->regs, offset, true); + + return 0; +} + +static int at91_gpio_get_flags(struct udevice *dev, unsigned int offset, + ulong *flagsp) +{ + struct at91_port_priv *port = dev_get_priv(dev); + ulong dir_flags = 0; + + if (at91_get_port_output(port->regs, offset)) { + dir_flags |= GPIOD_IS_OUT; + + if (at91_get_port_multi_drive(port->regs, offset)) + dir_flags |= GPIOD_OPEN_DRAIN; + + if (at91_get_port_value(port->regs, offset)) + dir_flags |= GPIOD_IS_OUT_ACTIVE; + } else { + dir_flags |= GPIOD_IS_IN; + } + + if (at91_get_port_pullup(port->regs, offset)) + dir_flags |= GPIOD_PULL_UP; + + *flagsp = dir_flags; + + return 0; +} + static const char *at91_get_bank_name(uint32_t base_addr) { switch (base_addr) { @@ -584,6 +677,8 @@ static const struct dm_gpio_ops gpio_at91_ops = { .get_value = at91_gpio_get_value, .set_value = at91_gpio_set_value, .get_function = at91_gpio_get_function, + .set_flags = at91_gpio_set_flags, + .get_flags = at91_gpio_get_flags, }; static int at91_gpio_probe(struct udevice *dev) diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c index 0213271e3a6..da929c33447 100644 --- a/drivers/gpio/gpio-uclass.c +++ b/drivers/gpio/gpio-uclass.c @@ -705,6 +705,9 @@ static int _dm_gpio_set_flags(struct gpio_desc *desc, ulong flags) if (ops->set_flags) { ret = ops->set_flags(dev, desc->offset, flags); } else { + if (flags & GPIOD_MASK_PULL) + return -EINVAL; + if (flags & GPIOD_IS_OUT) { bool value = flags & GPIOD_IS_OUT_ACTIVE; diff --git a/drivers/gpio/imx_rgpio2p.c b/drivers/gpio/imx_rgpio2p.c index fc1d418315c..7cf178f8a48 100644 --- a/drivers/gpio/imx_rgpio2p.c +++ b/drivers/gpio/imx_rgpio2p.c @@ -231,7 +231,7 @@ static struct imx_rgpio2p_soc_data imx7ulp_data = { .have_dual_base = true, }; -static struct imx_rgpio2p_soc_data imx8ulp_data = { +static struct imx_rgpio2p_soc_data imx8ulp_data __section(".data") = { .have_dual_base = false, }; diff --git a/drivers/gpio/mpc8xxx_gpio.c b/drivers/gpio/mpc8xxx_gpio.c index e9bd38f162c..709d04017d1 100644 --- a/drivers/gpio/mpc8xxx_gpio.c +++ b/drivers/gpio/mpc8xxx_gpio.c @@ -204,7 +204,17 @@ static int mpc8xxx_gpio_plat_to_priv(struct udevice *dev) return -ENOMEM; priv->gpio_count = plat->ngpios; - priv->dat_shadow = 0; + + /* + * On platforms that do support reading back output values, we want to + * try preserving them, so that we don't accidentally set unrelated + * GPIOs to zero in mpc8xxx_gpio_set_value. + */ + if (priv->little_endian) + priv->dat_shadow = in_le32(&priv->base->gpdat) & in_le32(&priv->base->gpdir); + else + priv->dat_shadow = in_be32(&priv->base->gpdat) & in_be32(&priv->base->gpdir); + priv->type = driver_data; diff --git a/drivers/gpio/npcm_sgpio.c b/drivers/gpio/npcm_sgpio.c index 6d73287c0a2..fcc42087d57 100644 --- a/drivers/gpio/npcm_sgpio.c +++ b/drivers/gpio/npcm_sgpio.c @@ -4,31 +4,47 @@ */ #include <dm.h> +#include <regmap.h> +#include <syscon.h> #include <asm/gpio.h> +#include <linux/err.h> #include <linux/io.h> +#include <asm/arch/rst.h> #define MAX_NR_HW_SGPIO 64 -#define NPCM_CLK_MHZ 8000000 +#define NPCM_SIOX1 24 +#define NPCM_SIOX2 25 -#define NPCM_IOXCFG1 0x2A - -#define NPCM_IOXCTS 0x28 -#define NPCM_IOXCTS_IOXIF_EN BIT(7) -#define NPCM_IOXCTS_RD_MODE GENMASK(2, 1) +#define NPCM_IOXCTS 0x28 +#define NPCM_IOXCTS_IOXIF_EN BIT(7) +#define NPCM_IOXCTS_RD_MODE GENMASK(2, 1) #define NPCM_IOXCTS_RD_MODE_PERIODIC BIT(2) +#define NPCM_IOXCFG1 0x2A #define NPCM_IOXCFG2 0x2B #define NPCM_IOXCFG2_PORT GENMASK(3, 0) #define GPIO_BANK(x) ((x) / 8) #define GPIO_BIT(x) ((x) % 8) +#define WD0RCR 0x38 +#define WD1RCR 0x3c +#define WD2RCR 0x40 +#define SWRSTC1 0x44 +#define SWRSTC2 0x48 +#define SWRSTC3 0x4c +#define TIPRSTC 0x50 +#define CORSTC 0x5c + struct npcm_sgpio_priv { void __iomem *base; + struct regmap *rst_regmap; u32 nin_sgpio; u32 nout_sgpio; u32 in_port; u32 out_port; + u8 persist[8]; + u8 siox_num; }; struct npcm_sgpio_bank { @@ -185,7 +201,13 @@ static int npcm_sgpio_get_value(struct udevice *dev, unsigned int offset) static int npcm_sgpio_set_value(struct udevice *dev, unsigned int offset, int value) { - return npcm_sgpio_direction_output(dev, offset, value); + struct npcm_sgpio_priv *priv = dev_get_priv(dev); + u8 check = priv->persist[GPIO_BANK(offset)]; + + if (!!(check & BIT(GPIO_BIT(offset))) == 0) + return npcm_sgpio_direction_output(dev, offset, value); + else + return -EINVAL; } static int npcm_sgpio_get_function(struct udevice *dev, unsigned int offset) @@ -213,12 +235,10 @@ static void npcm_sgpio_setup_enable(struct npcm_sgpio_priv *gpio, bool enable) iowrite8(reg, gpio->base + NPCM_IOXCTS); } -static int npcm_sgpio_init_port(struct udevice *dev) +static void npcm_sgpio_set_port(struct udevice *dev) { struct npcm_sgpio_priv *priv = dev_get_priv(dev); - u8 in_port, out_port, set_port, reg, set_clk; - - npcm_sgpio_setup_enable(priv, false); + u8 in_port, out_port; in_port = GPIO_BANK(priv->nin_sgpio); if (GPIO_BIT(priv->nin_sgpio) > 0) @@ -230,8 +250,16 @@ static int npcm_sgpio_init_port(struct udevice *dev) priv->in_port = in_port; priv->out_port = out_port; +} - set_port = (out_port & NPCM_IOXCFG2_PORT) << 4 | (in_port & NPCM_IOXCFG2_PORT); +static int npcm_sgpio_init_port(struct udevice *dev) +{ + struct npcm_sgpio_priv *priv = dev_get_priv(dev); + u8 set_port, reg, set_clk; + + npcm_sgpio_setup_enable(priv, false); + + set_port = (priv->out_port & NPCM_IOXCFG2_PORT) << 4 | (priv->in_port & NPCM_IOXCFG2_PORT); set_clk = 0x07; iowrite8(set_port, priv->base + NPCM_IOXCFG2); @@ -242,6 +270,61 @@ static int npcm_sgpio_init_port(struct udevice *dev) return reg == set_port ? 0 : -EINVAL; } +static void npcm_sgpio_reset_persist(struct udevice *dev, uint enable) +{ + struct npcm_sgpio_priv *priv = dev_get_priv(dev); + u8 num; + + if (priv->siox_num == 1) + num = NPCM_SIOX2; + else + num = NPCM_SIOX1; + + if (enable) { + regmap_update_bits(priv->rst_regmap, WD0RCR, BIT(num), 0); + regmap_update_bits(priv->rst_regmap, WD1RCR, BIT(num), 0); + regmap_update_bits(priv->rst_regmap, WD2RCR, BIT(num), 0); + regmap_update_bits(priv->rst_regmap, CORSTC, BIT(num), 0); + regmap_update_bits(priv->rst_regmap, SWRSTC1, BIT(num), 0); + regmap_update_bits(priv->rst_regmap, SWRSTC2, BIT(num), 0); + regmap_update_bits(priv->rst_regmap, SWRSTC3, BIT(num), 0); + regmap_update_bits(priv->rst_regmap, TIPRSTC, BIT(num), 0); + } +} + +static bool is_gpio_persist(struct udevice *dev) +{ + struct npcm_sgpio_priv *priv = dev_get_priv(dev); + u32 val; + int status; + + status = npcm_get_reset_status(); + + if (status & PORST) + return false; + if (status & CORST) + regmap_read(priv->rst_regmap, CORSTC, &val); + else if (status & WD0RST) + regmap_read(priv->rst_regmap, WD0RCR, &val); + else if (status & WD1RST) + regmap_read(priv->rst_regmap, WD1RCR, &val); + else if (status & WD2RST) + regmap_read(priv->rst_regmap, WD2RCR, &val); + else if (status & SW1RST) + regmap_read(priv->rst_regmap, SWRSTC1, &val); + else if (status & SW2RST) + regmap_read(priv->rst_regmap, SWRSTC2, &val); + else if (status & SW3RST) + regmap_read(priv->rst_regmap, SWRSTC3, &val); + else if (status & TIPRST) + regmap_read(priv->rst_regmap, TIPRSTC, &val); + + if (priv->siox_num == 1) + return (val && BIT(NPCM_SIOX2)); + else + return (val && BIT(NPCM_SIOX1)); +} + static const struct dm_gpio_ops npcm_sgpio_ops = { .direction_input = npcm_sgpio_direction_input, .direction_output = npcm_sgpio_direction_output, @@ -254,23 +337,57 @@ static int npcm_sgpio_probe(struct udevice *dev) { struct npcm_sgpio_priv *priv = dev_get_priv(dev); struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); - int rc; + int rc, i; + ofnode node; + u32 val[2]; priv->base = dev_read_addr_ptr(dev); + priv->rst_regmap = syscon_regmap_lookup_by_phandle(dev, "syscon-rst"); + if (IS_ERR(priv->rst_regmap)) + return -EINVAL; + ofnode_read_u32(dev_ofnode(dev), "nuvoton,input-ngpios", &priv->nin_sgpio); ofnode_read_u32(dev_ofnode(dev), "nuvoton,output-ngpios", &priv->nout_sgpio); if (priv->nin_sgpio > MAX_NR_HW_SGPIO || priv->nout_sgpio > MAX_NR_HW_SGPIO) return -EINVAL; - rc = npcm_sgpio_init_port(dev); - if (rc < 0) - return rc; + if (!strcmp(ofnode_get_name(dev_ofnode(dev)), "sgpio2@102000")) + priv->siox_num = 1; + else if (!strcmp(ofnode_get_name(dev_ofnode(dev)), "sgpio1@101000")) + priv->siox_num = 0; + else + return -EINVAL; + npcm_sgpio_set_port(dev); uc_priv->gpio_count = priv->nin_sgpio + priv->nout_sgpio; uc_priv->bank_name = dev->name; - npcm_sgpio_setup_enable(priv, true); + if (is_gpio_persist(dev)) { + ofnode_for_each_subnode(node, dev_ofnode(dev)) { + if (ofnode_read_bool(node, "persist-enable")) { + rc = ofnode_read_u32_array(node, "gpios", val, 2); + if (rc == 0) + priv->persist[GPIO_BANK(val[0])] = priv->persist[GPIO_BANK(val[0])] | BIT(GPIO_BIT(val[0])); + } + } + for (i = 0; i < priv->nout_sgpio; i++) + npcm_sgpio_set_value(dev, i, 0); + } else { + rc = npcm_sgpio_init_port(dev); + if (rc < 0) + return rc; + + ofnode_for_each_subnode(node, dev_ofnode(dev)) { + if (ofnode_read_bool(node, "persist-enable")) + npcm_sgpio_reset_persist(dev, 1); + } + + for (i = 0; i < priv->nout_sgpio; i++) + npcm_sgpio_set_value(dev, i, 0); + + npcm_sgpio_setup_enable(priv, true); + } return 0; } diff --git a/drivers/led/led-uclass.c b/drivers/led/led-uclass.c index 05e09909b7d..760750568c0 100644 --- a/drivers/led/led-uclass.c +++ b/drivers/led/led-uclass.c @@ -232,16 +232,24 @@ int led_activity_blink(void) #endif #endif +static const char *led_get_label(ofnode node) +{ + const char *label; + + label = ofnode_read_string(node, "label"); + if (!label && !ofnode_read_string(node, "compatible")) + label = ofnode_get_name(node); + + return label; +} + static int led_post_bind(struct udevice *dev) { struct led_uc_plat *uc_plat = dev_get_uclass_plat(dev); const char *default_state; if (!uc_plat->label) - uc_plat->label = dev_read_string(dev, "label"); - - if (!uc_plat->label && !dev_read_string(dev, "compatible")) - uc_plat->label = ofnode_get_name(dev_ofnode(dev)); + uc_plat->label = led_get_label(dev_ofnode(dev)); uc_plat->default_state = LEDST_COUNT; @@ -300,15 +308,21 @@ static int led_post_probe(struct udevice *dev) static int led_init(struct uclass *uc) { struct led_uc_priv *priv = uclass_get_priv(uc); + ofnode led_node; + int ret; #ifdef CONFIG_LED_BOOT - priv->boot_led_label = ofnode_options_read_str("boot-led"); - priv->boot_led_period = ofnode_options_read_int("boot-led-period", 250); + ret = ofnode_options_get_by_phandle("boot-led", &led_node); + if (!ret) + priv->boot_led_label = led_get_label(led_node); + priv->boot_led_period = ofnode_options_read_int("boot-led-period-ms", 250); #endif #ifdef CONFIG_LED_ACTIVITY - priv->activity_led_label = ofnode_options_read_str("activity-led"); - priv->activity_led_period = ofnode_options_read_int("activity-led-period", + ret = ofnode_options_get_by_phandle("activity-led", &led_node); + if (!ret) + priv->activity_led_label = led_get_label(led_node); + priv->activity_led_period = ofnode_options_read_int("activity-led-period-ms", 250); #endif diff --git a/drivers/misc/gsc.c b/drivers/misc/gsc.c index dee0bdd9663..72a13abaaee 100644 --- a/drivers/misc/gsc.c +++ b/drivers/misc/gsc.c @@ -310,6 +310,7 @@ static int gsc_hwmon(struct udevice *dev) printf("%-8s: %d.%ldC\n", label, val / 10, abs(val % 10)); break; case 1: /* prescaled voltage */ + case 3: if (val != 0xffff) printf("%-8s: %d.%03dV\n", label, val / 1000, val % 1000); break; @@ -330,6 +331,9 @@ static int gsc_hwmon(struct udevice *dev) printf("%-8s: %d.%03dV\n", label, val / 1000, val % 1000); break; + case 4: /* revolutions per minute */ + printf("%-8s: %drpm\n", label, val * 30); + break; } } diff --git a/drivers/misc/i2c_eeprom.c b/drivers/misc/i2c_eeprom.c index 10f0173d805..3cb38aa28ad 100644 --- a/drivers/misc/i2c_eeprom.c +++ b/drivers/misc/i2c_eeprom.c @@ -264,6 +264,13 @@ static const struct i2c_eeprom_drv_data atmel24c256_data = { .offset_len = 2, }; +static const struct i2c_eeprom_drv_data st24256e_wlp_data = { + .size = 64, + .pagesize = 64, + .addr_offset_mask = 0, + .offset_len = 2, +}; + static const struct i2c_eeprom_drv_data atmel24c512_data = { .size = 65536, .pagesize = 64, @@ -287,6 +294,7 @@ static const struct udevice_id i2c_eeprom_std_ids[] = { { .compatible = "atmel,24c128", (ulong)&atmel24c128_data }, { .compatible = "atmel,24c256", (ulong)&atmel24c256_data }, { .compatible = "atmel,24c512", (ulong)&atmel24c512_data }, + { .compatible = "st,24256e-wl", (ulong)&st24256e_wlp_data }, { } }; diff --git a/drivers/misc/imx8/scu_api.c b/drivers/misc/imx8/scu_api.c index 591d71b096a..a40c8badf9a 100644 --- a/drivers/misc/imx8/scu_api.c +++ b/drivers/misc/imx8/scu_api.c @@ -951,6 +951,26 @@ int sc_timer_set_wdog_window(sc_ipc_t ipc, sc_timer_wdog_time_t window) return ret; } +int sc_timer_control_siemens_pmic_wdog(sc_ipc_t ipc, u8 cmd) +{ + struct udevice *dev = gd->arch.scu_dev; + struct sc_rpc_msg_s msg; + int size = sizeof(struct sc_rpc_msg_s); + int ret; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (u8)SC_RPC_SVC_TIMER; + RPC_FUNC(&msg) = (u8)TIMER_FUNC_CTRL_SIEMENS_PMIC_WDOG; + RPC_U8(&msg, 0U) = (u8)cmd; + RPC_SIZE(&msg) = 2U; + + ret = misc_call(dev, SC_FALSE, &msg, size, &msg, size); + if (ret) + printf("%s: res:%d\n", __func__, RPC_R8(&msg)); + + return ret; +} + int sc_seco_authenticate(sc_ipc_t ipc, sc_seco_auth_cmd_t cmd, sc_faddr_t addr) { diff --git a/drivers/misc/k3_avs.c b/drivers/misc/k3_avs.c index 99a18a109b7..0774e0a4c9e 100644 --- a/drivers/misc/k3_avs.c +++ b/drivers/misc/k3_avs.c @@ -121,6 +121,11 @@ static int k3_avs_program_voltage(struct k3_avs_privdata *priv, if (!vd->supply) return -ENODEV; + if (!volt) { + dev_err(priv->dev, "No efuse found for opp_%d\n", opp_id); + return -EINVAL; + } + vd->opp = opp_id; vd->flags |= VD_FLAG_INIT_DONE; @@ -193,6 +198,33 @@ static int match_opp(struct vd_data *vd, u32 freq) } /** + * k3_check_opp: Check for presence of opp efuse + * @dev: AVS device + * @vdd_id: voltage domain ID + * @opp_id: opp id to check if voltage is present + * + * Checks to see if an opp has voltage. k3_avs probe will populate + * voltage data if efuse is present. Returns 0 if data is valid. + */ +int k3_avs_check_opp(struct udevice *dev, int vdd_id, int opp_id) +{ + struct k3_avs_privdata *priv = dev_get_priv(dev); + struct vd_data *vd; + int volt; + + vd = get_vd(priv, vdd_id); + if (!vd) + return -EINVAL; + + volt = vd->opps[opp_id].volt; + if (volt) + return 0; + + printf("No efuse found for opp_%d\n", opp_id); + return -EINVAL; +} + +/** * k3_avs_notify_freq: Notify clock rate change towards AVS subsystem * @dev_id: Device ID for the clock to be changed * @clk_id: Clock ID for the clock to be changed @@ -501,6 +533,10 @@ static struct vd_data j721e_vd_data[] = { .dev_id = 202, /* J721E_DEV_A72SS0_CORE0 */ .clk_id = 2, /* ARM clock */ .opps = { + [AM6_OPP_LOW] = { + .volt = 0, /* voltage TBD after OPP fuse reading */ + .freq = 1000000000, + }, [AM6_OPP_NOM] = { .volt = 880000, /* TBD in DM */ .freq = 2000000000, diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 38817622fca..f4fdf15242c 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -732,6 +732,18 @@ config MMC_SDHCI_S5P If unsure, say N. +config MMC_SDHCI_SNPS + bool "Synopsys DesignWare SDHCI controller" + depends on MMC_SDHCI + depends on DM_MMC + help + Support for DesignWare SDHCI host controller on Alibaba TH1520 SoC. + This is a highly configurable and programmable, high performance + Mobile Storage Host Controller (MSHC) with AXI as the bus interface + for data transfer. + + If unsure, say N. + config MMC_SDHCI_STI bool "SDHCI support for STMicroelectronics SoC" depends on MMC_SDHCI && OF_CONTROL diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index 868f3090ff2..90e76f90769 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -71,6 +71,7 @@ obj-$(CONFIG_MMC_SDHCI_NPCM) += npcm_sdhci.o obj-$(CONFIG_MMC_SDHCI_PIC32) += pic32_sdhci.o obj-$(CONFIG_MMC_SDHCI_ROCKCHIP) += rockchip_sdhci.o obj-$(CONFIG_MMC_SDHCI_S5P) += s5p_sdhci.o +obj-$(CONFIG_MMC_SDHCI_SNPS) += snps_sdhci.o obj-$(CONFIG_MMC_SDHCI_STI) += sti_sdhci.o obj-$(CONFIG_MMC_SDHCI_TANGIER) += tangier_sdhci.o obj-$(CONFIG_MMC_SDHCI_TEGRA) += tegra_mmc.o diff --git a/drivers/mmc/snps_dw_mmc.c b/drivers/mmc/snps_dw_mmc.c index 47ab5654bd6..92880e0ed87 100644 --- a/drivers/mmc/snps_dw_mmc.c +++ b/drivers/mmc/snps_dw_mmc.c @@ -186,6 +186,7 @@ static int snps_dwmmc_bind(struct udevice *dev) static const struct udevice_id snps_dwmmc_ids[] = { { .compatible = "snps,dw-mshc" }, + { .compatible = "starfive,jh7110-mmc" }, { } }; diff --git a/drivers/mmc/snps_sdhci.c b/drivers/mmc/snps_sdhci.c new file mode 100644 index 00000000000..f5ede38c3c1 --- /dev/null +++ b/drivers/mmc/snps_sdhci.c @@ -0,0 +1,444 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2024 Maksim Kiselev <bigunclemax@gmail.com> + */ + +#include <clk.h> +#include <dm.h> +#include <linux/bitfield.h> +#include <sdhci.h> + +/* DWCMSHC specific Mode Select value */ +#define DWCMSHC_CTRL_HS400 0x7 +/* 400KHz is max freq for card ID etc. Use that as min */ +#define EMMC_MIN_FREQ 400000 +#define SDHCI_TUNING_LOOP_COUNT 128 + +/* PHY register area pointer */ +#define DWC_MSHC_PTR_PHY_R 0x300 + +/* PHY general configuration */ +#define PHY_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x00) +#define PHY_CNFG_RSTN_DEASSERT 0x1 /* Deassert PHY reset */ +#define PHY_CNFG_PAD_SP_MASK GENMASK(19, 16) /* bits [19:16] */ +#define PHY_CNFG_PAD_SP 0x0c /* PMOS TX drive strength */ +#define PHY_CNFG_PAD_SN_MASK GENMASK(23, 20) /* bits [23:20] */ +#define PHY_CNFG_PAD_SN 0x0c /* NMOS TX drive strength */ + +/* PHY command/response pad settings */ +#define PHY_CMDPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x04) + +/* PHY data pad settings */ +#define PHY_DATAPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x06) + +/* PHY clock pad settings */ +#define PHY_CLKPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x08) + +/* PHY strobe pad settings */ +#define PHY_STBPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x0a) + +/* PHY reset pad settings */ +#define PHY_RSTNPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x0c) + +/* Bitfields are common for all pad settings */ +#define PHY_PAD_RXSEL_1V8 0x1 /* Receiver type select for 1.8V */ +#define PHY_PAD_RXSEL_3V3 0x2 /* Receiver type select for 3.3V */ + +#define PHY_PAD_WEAKPULL_MASK GENMASK(4, 3) /* bits [4:3] */ +#define PHY_PAD_WEAKPULL_PULLUP 0x1 /* Weak pull up enabled */ +#define PHY_PAD_WEAKPULL_PULLDOWN 0x2 /* Weak pull down enabled */ + +#define PHY_PAD_TXSLEW_CTRL_P_MASK GENMASK(8, 5) /* bits [8:5] */ +#define PHY_PAD_TXSLEW_CTRL_P 0x3 /* Slew control for P-Type pad TX */ +#define PHY_PAD_TXSLEW_CTRL_N_MASK GENMASK(12, 9) /* bits [12:9] */ +#define PHY_PAD_TXSLEW_CTRL_N 0x3 /* Slew control for N-Type pad TX */ + +/* PHY CLK delay line settings */ +#define PHY_SDCLKDL_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x1d) +#define PHY_SDCLKDL_CNFG_UPDATE BIT(4) /* set before writing to SDCLKDL_DC */ + +/* PHY CLK delay line delay code */ +#define PHY_SDCLKDL_DC_R (DWC_MSHC_PTR_PHY_R + 0x1e) +#define PHY_SDCLKDL_DC_INITIAL 0x40 /* initial delay code */ +#define PHY_SDCLKDL_DC_DEFAULT 0x32 /* default delay code */ +#define PHY_SDCLKDL_DC_HS400 0x18 /* delay code for HS400 mode */ + +/* PHY drift_cclk_rx delay line configuration setting */ +#define PHY_ATDL_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x21) +#define PHY_ATDL_CNFG_INPSEL_MASK GENMASK(3, 2) /* bits [3:2] */ +#define PHY_ATDL_CNFG_INPSEL 0x3 /* delay line input source */ + +/* PHY DLL control settings */ +#define PHY_DLL_CTRL_R (DWC_MSHC_PTR_PHY_R + 0x24) +#define PHY_DLL_CTRL_DISABLE 0x0 /* PHY DLL is enabled */ +#define PHY_DLL_CTRL_ENABLE 0x1 /* PHY DLL is disabled */ + +/* PHY DLL configuration register 1 */ +#define PHY_DLL_CNFG1_R (DWC_MSHC_PTR_PHY_R + 0x25) +#define PHY_DLL_CNFG1_SLVDLY_MASK GENMASK(5, 4) /* bits [5:4] */ +#define PHY_DLL_CNFG1_SLVDLY 0x2 /* DLL slave update delay input */ +#define PHY_DLL_CNFG1_WAITCYCLE 0x5 /* DLL wait cycle input */ + +/* PHY DLL configuration register 2 */ +#define PHY_DLL_CNFG2_R (DWC_MSHC_PTR_PHY_R + 0x26) +#define PHY_DLL_CNFG2_JUMPSTEP 0xa /* DLL jump step input */ + +/* PHY DLL master and slave delay line configuration settings */ +#define PHY_DLLDL_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x28) +#define PHY_DLLDL_CNFG_SLV_INPSEL_MASK GENMASK(6, 5) /* bits [6:5] */ +#define PHY_DLLDL_CNFG_SLV_INPSEL 0x3 /* clock source select for slave DL */ + +/* Vendor specific Registers */ +#define P_VENDOR_SPECIFIC_AREA 0x500 + +#define DWCMSHC_EMMC_CONTROL 0x2c +#define DWCMSHC_CARD_IS_EMMC BIT(0) +#define DWCMSHC_ENHANCED_STROBE BIT(8) +#define DWCMSHC_EMMC_ATCTRL 0x40 +/* Tuning and auto-tuning fields in AT_CTRL_R control register */ +#define AT_CTRL_AT_EN BIT(0) /* autotuning is enabled */ +#define AT_CTRL_CI_SEL BIT(1) /* interval to drive center phase select */ +#define AT_CTRL_SWIN_TH_EN BIT(2) /* sampling window threshold enable */ +#define AT_CTRL_RPT_TUNE_ERR BIT(3) /* enable reporting framing errors */ +#define AT_CTRL_SW_TUNE_EN BIT(4) /* enable software managed tuning */ +#define AT_CTRL_WIN_EDGE_SEL_MASK GENMASK(11, 8) /* bits [11:8] */ +#define AT_CTRL_WIN_EDGE_SEL 0xf /* sampling window edge select */ +#define AT_CTRL_TUNE_CLK_STOP_EN BIT(16) /* clocks stopped during phase code change */ +#define AT_CTRL_PRE_CHANGE_DLY_MASK GENMASK(18, 17) /* bits [18:17] */ +#define AT_CTRL_PRE_CHANGE_DLY 0x1 /* 2-cycle latency */ +#define AT_CTRL_POST_CHANGE_DLY_MASK GENMASK(20, 19) /* bits [20:19] */ +#define AT_CTRL_POST_CHANGE_DLY 0x3 /* 4-cycle latency */ +#define AT_CTRL_SWIN_TH_VAL_MASK GENMASK(31, 24) /* bits [31:24] */ +#define AT_CTRL_SWIN_TH_VAL 0x9 /* sampling window threshold */ + +#define FLAG_IO_FIXED_1V8 BIT(0) + +#define BOUNDARY_OK(addr, len) \ + (((addr) | (SZ_128M - 1)) == (((addr) + (len) - 1) | (SZ_128M - 1))) + +struct snps_sdhci_plat { + struct mmc_config cfg; + struct mmc mmc; + u16 delay_line; + u16 flags; +}; + +/* + * If DMA addr spans 128MB boundary, we split the DMA transfer into two + * so that each DMA transfer doesn't exceed the boundary. + */ +void snps_sdhci_adma_write_desc(struct sdhci_host *host, void **desc, + dma_addr_t addr, int len, bool end) +{ + int tmplen, offset; + + if (likely(!len || BOUNDARY_OK(addr, len))) { + sdhci_adma_write_desc(host, desc, addr, len, end); + return; + } + + offset = addr & (SZ_128M - 1); + tmplen = SZ_128M - offset; + sdhci_adma_write_desc(host, desc, addr, tmplen, false); + + addr += tmplen; + len -= tmplen; + sdhci_adma_write_desc(host, desc, addr, len, end); +} + +static void snps_sdhci_set_phy(struct sdhci_host *host) +{ + struct snps_sdhci_plat *plat = dev_get_plat(host->mmc->dev); + u32 rxsel = PHY_PAD_RXSEL_3V3; + u32 val; + + if (plat->flags & FLAG_IO_FIXED_1V8 || + host->mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) + rxsel = PHY_PAD_RXSEL_1V8; + + /* deassert phy reset & set tx drive strength */ + val = PHY_CNFG_RSTN_DEASSERT; + val |= FIELD_PREP(PHY_CNFG_PAD_SP_MASK, PHY_CNFG_PAD_SP); + val |= FIELD_PREP(PHY_CNFG_PAD_SN_MASK, PHY_CNFG_PAD_SN); + sdhci_writel(host, val, PHY_CNFG_R); + + /* disable delay line */ + sdhci_writeb(host, PHY_SDCLKDL_CNFG_UPDATE, PHY_SDCLKDL_CNFG_R); + + /* set delay line */ + sdhci_writeb(host, plat->delay_line, PHY_SDCLKDL_DC_R); + sdhci_writeb(host, PHY_DLL_CNFG2_JUMPSTEP, PHY_DLL_CNFG2_R); + + /* enable delay lane */ + val = sdhci_readb(host, PHY_SDCLKDL_CNFG_R); + val &= ~(PHY_SDCLKDL_CNFG_UPDATE); + sdhci_writeb(host, val, PHY_SDCLKDL_CNFG_R); + + /* configure phy pads */ + val = rxsel; + val |= FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLUP); + val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P); + val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N); + sdhci_writew(host, val, PHY_CMDPAD_CNFG_R); + sdhci_writew(host, val, PHY_DATAPAD_CNFG_R); + sdhci_writew(host, val, PHY_RSTNPAD_CNFG_R); + + val = FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P); + val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N); + sdhci_writew(host, val, PHY_CLKPAD_CNFG_R); + + val = rxsel; + val |= FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLDOWN); + val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P); + val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N); + sdhci_writew(host, val, PHY_STBPAD_CNFG_R); + + /* enable data strobe mode */ + if (plat->flags & FLAG_IO_FIXED_1V8 || + host->mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) { + u8 sel = FIELD_PREP(PHY_DLLDL_CNFG_SLV_INPSEL_MASK, PHY_DLLDL_CNFG_SLV_INPSEL); + + sdhci_writeb(host, sel, PHY_DLLDL_CNFG_R); + } + + /* enable phy dll */ + sdhci_writeb(host, PHY_DLL_CTRL_ENABLE, PHY_DLL_CTRL_R); + + sdhci_writeb(host, FIELD_PREP(PHY_DLL_CNFG1_SLVDLY_MASK, PHY_DLL_CNFG1_SLVDLY) | + PHY_DLL_CNFG1_WAITCYCLE, PHY_DLL_CNFG1_R); +} + +static int snps_sdhci_set_ios_post(struct sdhci_host *host) +{ + struct snps_sdhci_plat *plat = dev_get_plat(host->mmc->dev); + struct mmc *mmc = host->mmc; + u32 reg; + + reg = sdhci_readw(host, SDHCI_HOST_CONTROL2); + reg &= ~SDHCI_CTRL_UHS_MASK; + + switch (mmc->selected_mode) { + case UHS_SDR50: + case MMC_HS_52: + reg |= SDHCI_CTRL_UHS_SDR50; + break; + case UHS_DDR50: + case MMC_DDR_52: + reg |= SDHCI_CTRL_UHS_DDR50; + break; + case UHS_SDR104: + case MMC_HS_200: + reg |= SDHCI_CTRL_UHS_SDR104; + break; + case MMC_HS_400: + case MMC_HS_400_ES: + reg |= DWCMSHC_CTRL_HS400; + break; + default: + reg |= SDHCI_CTRL_UHS_SDR12; + } + + if ((plat->flags & FLAG_IO_FIXED_1V8) || + mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) + reg |= SDHCI_CTRL_VDD_180; + else + reg &= ~SDHCI_CTRL_VDD_180; + + sdhci_writew(host, reg, SDHCI_HOST_CONTROL2); + + reg = sdhci_readw(host, P_VENDOR_SPECIFIC_AREA + DWCMSHC_EMMC_CONTROL); + + if (IS_MMC(mmc)) + reg |= DWCMSHC_CARD_IS_EMMC; + else + reg &= ~DWCMSHC_CARD_IS_EMMC; + + if (mmc->selected_mode == MMC_HS_400_ES) + reg |= DWCMSHC_ENHANCED_STROBE; + else + reg &= ~DWCMSHC_ENHANCED_STROBE; + + sdhci_writeb(host, reg, P_VENDOR_SPECIFIC_AREA + DWCMSHC_EMMC_CONTROL); + + if (mmc->selected_mode == MMC_HS_400 || + mmc->selected_mode == MMC_HS_400_ES) + plat->delay_line = PHY_SDCLKDL_DC_HS400; + else + sdhci_writeb(host, 0, PHY_DLLDL_CNFG_R); + + snps_sdhci_set_phy(host); + + return 0; +} + +static int snps_sdhci_execute_tuning(struct mmc *mmc, u8 opcode) +{ + struct sdhci_host *host = dev_get_priv(mmc->dev); + char tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT; + struct mmc_cmd cmd; + u32 ctrl, blk_size, val; + int ret; + + sdhci_writeb(host, FIELD_PREP(PHY_ATDL_CNFG_INPSEL_MASK, PHY_ATDL_CNFG_INPSEL), + PHY_ATDL_CNFG_R); + val = sdhci_readl(host, P_VENDOR_SPECIFIC_AREA + DWCMSHC_EMMC_ATCTRL); + + /* + * configure tuning settings: + * - center phase select code driven in block gap interval + * - disable reporting of framing errors + * - disable software managed tuning + * - disable user selection of sampling window edges, + * instead tuning calculated edges are used + */ + val &= ~(AT_CTRL_CI_SEL | AT_CTRL_RPT_TUNE_ERR | AT_CTRL_SW_TUNE_EN | + FIELD_PREP(AT_CTRL_WIN_EDGE_SEL_MASK, AT_CTRL_WIN_EDGE_SEL)); + + /* + * configure tuning settings: + * - enable auto-tuning + * - enable sampling window threshold + * - stop clocks during phase code change + * - set max latency in cycles between tx and rx clocks + * - set max latency in cycles to switch output phase + * - set max sampling window threshold value + */ + val |= AT_CTRL_AT_EN | AT_CTRL_SWIN_TH_EN | AT_CTRL_TUNE_CLK_STOP_EN; + val |= FIELD_PREP(AT_CTRL_PRE_CHANGE_DLY_MASK, AT_CTRL_PRE_CHANGE_DLY); + val |= FIELD_PREP(AT_CTRL_POST_CHANGE_DLY_MASK, AT_CTRL_POST_CHANGE_DLY); + val |= FIELD_PREP(AT_CTRL_SWIN_TH_VAL_MASK, AT_CTRL_SWIN_TH_VAL); + + sdhci_writel(host, val, P_VENDOR_SPECIFIC_AREA + DWCMSHC_EMMC_ATCTRL); + val = sdhci_readl(host, P_VENDOR_SPECIFIC_AREA + DWCMSHC_EMMC_ATCTRL); + + /* perform tuning */ + ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); + ctrl |= SDHCI_CTRL_EXEC_TUNING; + sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); + + blk_size = SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 64); + if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200 && mmc->bus_width == 8) + blk_size = SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 128); + sdhci_writew(host, blk_size, SDHCI_BLOCK_SIZE); + sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); + + cmd.cmdidx = opcode; + cmd.resp_type = MMC_RSP_R1; + cmd.cmdarg = 0; + + do { + ret = mmc_send_cmd(mmc, &cmd, NULL); + ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); + if (ret || tuning_loop_counter-- == 0) + break; + + } while (ctrl & SDHCI_CTRL_EXEC_TUNING); + + if (ret || tuning_loop_counter < 0 || !(ctrl & SDHCI_CTRL_TUNED_CLK)) { + if (!ret) + ret = -EIO; + printf("%s: Tuning failed: %d\n", __func__, ret); + + ctrl &= ~SDHCI_CTRL_TUNED_CLK; + ctrl &= ~SDHCI_CTRL_EXEC_TUNING; + sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); + } + + return ret; +} + +static int snps_sdhci_set_enhanced_strobe(struct sdhci_host *host) +{ + return 0; +} + +static const struct sdhci_ops snps_sdhci_ops = { + .set_ios_post = snps_sdhci_set_ios_post, + .platform_execute_tuning = snps_sdhci_execute_tuning, + .set_enhanced_strobe = snps_sdhci_set_enhanced_strobe, +#if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA_HELPERS) + .adma_write_desc = snps_sdhci_adma_write_desc, +#endif +}; + +static int snps_sdhci_probe(struct udevice *dev) +{ + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); + struct snps_sdhci_plat *plat = dev_get_plat(dev); + struct mmc_config *cfg = &plat->cfg; + struct sdhci_host *host = dev_get_priv(dev); + struct clk clk; + int ret; + + plat->delay_line = PHY_SDCLKDL_DC_DEFAULT; + + ret = clk_get_by_name(dev, "core", &clk); + if (ret) + return ret; + + ret = clk_prepare_enable(&clk); + if (ret) + return ret; + + host->max_clk = clk_get_rate(&clk); + + host->ops = &snps_sdhci_ops; + + host->mmc = &plat->mmc; + host->mmc->priv = host; + host->mmc->dev = dev; + upriv->mmc = host->mmc; + + ret = sdhci_setup_cfg(cfg, host, cfg->f_max, EMMC_MIN_FREQ); + if (ret) + return ret; + + if ((dev_read_bool(dev, "mmc-ddr-1_8v")) || + (dev_read_bool(dev, "mmc-hs200-1_8v")) || + (dev_read_bool(dev, "mmc-hs400-1_8v"))) + plat->flags |= FLAG_IO_FIXED_1V8; + else + plat->flags &= ~FLAG_IO_FIXED_1V8; + + return sdhci_probe(dev); +} + +static int snps_sdhci_of_to_plat(struct udevice *dev) +{ + struct snps_sdhci_plat *plat = dev_get_plat(dev); + struct mmc_config *cfg = &plat->cfg; + struct sdhci_host *host = dev_get_priv(dev); + int ret; + + host->name = dev->name; + host->ioaddr = dev_read_addr_ptr(dev); + + ret = mmc_of_parse(dev, cfg); + if (ret) + return ret; + + return 0; +} + +static int snps_sdhci_bind(struct udevice *dev) +{ + struct snps_sdhci_plat *plat = dev_get_plat(dev); + + return sdhci_bind(dev, &plat->mmc, &plat->cfg); +} + +static const struct udevice_id snps_sdhci_ids[] = { + { .compatible = "thead,th1520-dwcmshc" } +}; + +U_BOOT_DRIVER(snps_sdhci_drv) = { + .name = "snps_sdhci", + .id = UCLASS_MMC, + .of_match = snps_sdhci_ids, + .of_to_plat = snps_sdhci_of_to_plat, + .ops = &sdhci_ops, + .bind = snps_sdhci_bind, + .probe = snps_sdhci_probe, + .priv_auto = sizeof(struct sdhci_host), + .plat_auto = sizeof(struct snps_sdhci_plat), +}; diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig index e7ce8b9577b..c71c1e5547c 100644 --- a/drivers/mtd/Kconfig +++ b/drivers/mtd/Kconfig @@ -202,7 +202,7 @@ config RENESAS_RPC_HF config HBMC_AM654 bool "HyperBus controller driver for AM65x SoC" - depends on SYSCON + depends on MULTIPLEXER && MUX_MMIO help This is the driver for HyperBus controller on TI's AM65x and other SoCs diff --git a/drivers/mtd/hbmc-am654.c b/drivers/mtd/hbmc-am654.c index 599beda30d5..98988a8e24d 100644 --- a/drivers/mtd/hbmc-am654.c +++ b/drivers/mtd/hbmc-am654.c @@ -5,8 +5,8 @@ #include <asm/io.h> #include <dm.h> +#include <mux.h> #include <regmap.h> -#include <syscon.h> #include <dm/device_compat.h> #define FSS_SYSC_REG 0x4 @@ -52,9 +52,13 @@ static int am654_hyperbus_calibrate(struct udevice *dev) static int am654_select_hbmc(struct udevice *dev) { - struct regmap *regmap = syscon_get_regmap(dev_get_parent(dev)); + struct mux_control *mux_ctl; + int ret; - return regmap_update_bits(regmap, FSS_SYSC_REG, 0x2, 0x2); + ret = mux_get_by_index(dev, 0, &mux_ctl); + if (!ret) + ret = mux_control_select(mux_ctl, 1); + return ret; } static int am654_hbmc_bind(struct udevice *dev) diff --git a/drivers/mtd/mtdcore.c b/drivers/mtd/mtdcore.c index 5bd64bd6ad4..3bfa5aebbc6 100644 --- a/drivers/mtd/mtdcore.c +++ b/drivers/mtd/mtdcore.c @@ -1124,6 +1124,28 @@ int mtd_read_oob(struct mtd_info *mtd, loff_t from, struct mtd_oob_ops *ops) } EXPORT_SYMBOL_GPL(mtd_read_oob); +/* This is a bare copy of mtd_read_oob returning the actual number of bitflips */ +int mtd_read_oob_bf(struct mtd_info *mtd, loff_t from, struct mtd_oob_ops *ops) +{ + int ret_code; + ops->retlen = ops->oobretlen = 0; + if (!mtd->_read_oob) + return -EOPNOTSUPP; + /* + * In cases where ops->datbuf != NULL, mtd->_read_oob() has semantics + * similar to mtd->_read(), returning a non-negative integer + * representing max bitflips. In other cases, mtd->_read_oob() may + * return -EUCLEAN. In all cases, perform similar logic to mtd_read(). + */ + ret_code = mtd->_read_oob(mtd, from, ops); + if (unlikely(ret_code < 0)) + return ret_code; + if (mtd->ecc_strength == 0) + return 0; /* device lacks ecc */ + return ret_code; +} +EXPORT_SYMBOL_GPL(mtd_read_oob_bf); + int mtd_write_oob(struct mtd_info *mtd, loff_t to, struct mtd_oob_ops *ops) { diff --git a/drivers/mtd/nand/raw/atmel/nand-controller.c b/drivers/mtd/nand/raw/atmel/nand-controller.c index 817fab4ca36..56fbd64ef68 100644 --- a/drivers/mtd/nand/raw/atmel/nand-controller.c +++ b/drivers/mtd/nand/raw/atmel/nand-controller.c @@ -568,12 +568,9 @@ static void atmel_nfc_copy_to_sram(struct nand_chip *chip, const u8 *buf, struct mtd_info *mtd = nand_to_mtd(chip); struct atmel_nand *nand = to_atmel_nand(chip); struct atmel_hsmc_nand_controller *nc; - int ret = -EIO; nc = to_hsmc_nand_controller(nand->controller); - - if (ret) - memcpy_toio(nc->sram.virt, buf, mtd->writesize); + memcpy_toio(nc->sram.virt, buf, mtd->writesize); if (oob_required) memcpy_toio(nc->sram.virt + mtd->writesize, chip->oob_poi, @@ -586,12 +583,9 @@ static void atmel_nfc_copy_from_sram(struct nand_chip *chip, u8 *buf, struct mtd_info *mtd = nand_to_mtd(chip); struct atmel_nand *nand = to_atmel_nand(chip); struct atmel_hsmc_nand_controller *nc; - int ret = -EIO; nc = to_hsmc_nand_controller(nand->controller); - - if (ret) - memcpy_fromio(buf, nc->sram.virt, mtd->writesize); + memcpy_fromio(buf, nc->sram.virt, mtd->writesize); if (oob_required) memcpy_fromio(chip->oob_poi, nc->sram.virt + mtd->writesize, @@ -2205,7 +2199,6 @@ static const struct udevice_id atmel_nand_controller_of_ids[] = { static int atmel_nand_controller_probe(struct udevice *dev) { const struct atmel_nand_controller_caps *caps; - struct udevice *pmecc_dev; caps = (struct atmel_nand_controller_caps *)dev_get_driver_data(dev); if (!caps) { @@ -2213,12 +2206,6 @@ static int atmel_nand_controller_probe(struct udevice *dev) return -EINVAL; } - /* Probe pmecc driver */ - if (uclass_get_device(UCLASS_MTD, 1, &pmecc_dev)) { - printf("%s: get device fail\n", __func__); - return -EINVAL; - } - return caps->ops->probe(dev, caps); } diff --git a/drivers/mtd/nand/raw/atmel/pmecc.c b/drivers/mtd/nand/raw/atmel/pmecc.c index 51f6bd2e65b..e500a0fe3f8 100644 --- a/drivers/mtd/nand/raw/atmel/pmecc.c +++ b/drivers/mtd/nand/raw/atmel/pmecc.c @@ -913,6 +913,7 @@ struct atmel_pmecc *devm_atmel_pmecc_get(struct udevice *userdev) ret = ofnode_parse_phandle_with_args(userdev->node_, "ecc-engine", NULL, 0, 0, &args); + /* Probe pmecc driver */ ret = uclass_get_device_by_ofnode(UCLASS_MTD, args.node, &pdev); if (ret) return NULL; diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index ec841fb13bd..6f352c5c0e2 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -1130,17 +1130,19 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) goto erase_err; } offset = addr; - if (nor->flags & SNOR_F_HAS_PARALLEL) - offset /= 2; - - if (nor->flags & SNOR_F_HAS_STACKED) { - if (offset >= (mtd->size / 2)) - nor->spi->flags |= SPI_XFER_U_PAGE; - else - nor->spi->flags &= ~SPI_XFER_U_PAGE; + if (CONFIG_IS_ENABLED(SPI_STACKED_PARALLEL)) { + if (nor->flags & SNOR_F_HAS_PARALLEL) + offset /= 2; + + if (nor->flags & SNOR_F_HAS_STACKED) { + if (offset >= (mtd->size / 2)) + nor->spi->flags |= SPI_XFER_U_PAGE; + else + nor->spi->flags &= ~SPI_XFER_U_PAGE; + } } #ifdef CONFIG_SPI_FLASH_BAR - ret = write_bar(nor, addr); + ret = write_bar(nor, offset); if (ret < 0) goto erase_err; #endif @@ -1152,7 +1154,7 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) !(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) { ret = spi_nor_erase_chip(nor); } else { - ret = spi_nor_erase_sector(nor, addr); + ret = spi_nor_erase_sector(nor, offset); } if (ret < 0) goto erase_err; @@ -1576,11 +1578,12 @@ static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf) { struct spi_nor *nor = mtd_to_spi_nor(mtd); - int ret; loff_t offset = from; - u32 read_len = 0; u32 rem_bank_len = 0; + u32 stack_shift = 0; + size_t read_len; u8 bank; + int ret; bool is_ofst_odd = false; dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len); @@ -1593,39 +1596,49 @@ static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len, } while (len) { - bank = (u32)from / SZ_16M; - if (nor->flags & SNOR_F_HAS_PARALLEL) - bank /= 2; - - rem_bank_len = SZ_16M * (bank + 1); - if (nor->flags & SNOR_F_HAS_PARALLEL) - rem_bank_len *= 2; - rem_bank_len -= from; - + read_len = len; offset = from; - if (nor->flags & SNOR_F_HAS_STACKED) { - if (offset >= (mtd->size / 2)) { - offset = offset - (mtd->size / 2); - nor->spi->flags |= SPI_XFER_U_PAGE; - } else { - nor->spi->flags &= ~SPI_XFER_U_PAGE; + if (CONFIG_IS_ENABLED(SPI_FLASH_BAR)) { + bank = (u32)from / SZ_16M; + if (CONFIG_IS_ENABLED(SPI_STACKED_PARALLEL)) { + if (nor->flags & SNOR_F_HAS_PARALLEL) + bank /= 2; + } + rem_bank_len = SZ_16M * (bank + 1); + if (CONFIG_IS_ENABLED(SPI_STACKED_PARALLEL)) { + if (nor->flags & SNOR_F_HAS_PARALLEL) + rem_bank_len *= 2; } + rem_bank_len -= from; } - if (nor->flags & SNOR_F_HAS_PARALLEL) - offset /= 2; + if (CONFIG_IS_ENABLED(SPI_STACKED_PARALLEL)) { + if (nor->flags & SNOR_F_HAS_STACKED) { + stack_shift = 1; + if (offset >= (mtd->size / 2)) { + offset = offset - (mtd->size / 2); + nor->spi->flags |= SPI_XFER_U_PAGE; + } else { + nor->spi->flags &= ~SPI_XFER_U_PAGE; + } + } + } + + if (CONFIG_IS_ENABLED(SPI_STACKED_PARALLEL)) { + if (nor->flags & SNOR_F_HAS_PARALLEL) + offset /= 2; + } #ifdef CONFIG_SPI_FLASH_BAR ret = write_bar(nor, offset); if (ret < 0) return log_ret(ret); -#endif - if (len < rem_bank_len) read_len = len; else read_len = rem_bank_len; +#endif if (read_len == 0) return -EIO; diff --git a/drivers/mtd/ubispl/ubispl.c b/drivers/mtd/ubispl/ubispl.c index 90a7c4c6f9e..9face5fae15 100644 --- a/drivers/mtd/ubispl/ubispl.c +++ b/drivers/mtd/ubispl/ubispl.c @@ -113,7 +113,7 @@ static int vtbl_check(struct ubi_scan_info *ubi, crc = crc32(UBI_CRC32_INIT, &vtbl[i], UBI_VTBL_RECORD_SIZE_CRC); if (be32_to_cpu(vtbl[i].crc) != crc) { - ubi_err("bad CRC at record %u: %#08x, not %#08x", + ubi_err("bad CRC at record %u: #%08x, not #%08x", i, crc, be32_to_cpu(vtbl[i].crc)); ubi_dump_vtbl_record(&vtbl[i], i); return 1; diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index d6d5cb52fdd..54b08482b91 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -160,7 +160,7 @@ static int fec_get_clk_rate(void *udev, int idx) } } -static void fec_mii_setspeed(struct ethernet_regs *eth) +static void fec_mii_setspeed(struct udevice *dev, struct ethernet_regs *eth) { /* * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock @@ -182,7 +182,7 @@ static void fec_mii_setspeed(struct ethernet_regs *eth) u32 hold; int ret; - ret = fec_get_clk_rate(NULL, 0); + ret = fec_get_clk_rate(dev, 0); if (ret < 0) { printf("Can't find FEC0 clk rate: %d\n", ret); return; @@ -581,7 +581,7 @@ static int fecmxc_init(struct udevice *dev) fec_reg_setup(fec); if (fec->xcv_type != SEVENWIRE) - fec_mii_setspeed(fec->bus->priv); + fec_mii_setspeed(dev, fec->bus->priv); /* Set Opcode/Pause Duration Register */ writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */ @@ -996,7 +996,7 @@ static void fec_free_descs(struct fec_priv *fec) free(fec->tbd_base); } -struct mii_dev *fec_get_miibus(ulong base_addr, int dev_id) +struct mii_dev *fec_get_miibus(struct udevice *dev, ulong base_addr, int dev_id) { struct ethernet_regs *eth = (struct ethernet_regs *)base_addr; struct mii_dev *bus; @@ -1018,7 +1018,7 @@ struct mii_dev *fec_get_miibus(ulong base_addr, int dev_id) free(bus); return NULL; } - fec_mii_setspeed(eth); + fec_mii_setspeed(dev, eth); return bus; } @@ -1162,6 +1162,7 @@ static int fec_phy_init(struct fec_priv *priv, struct udevice *dev) { struct phy_device *phydev = NULL; int addr; + int ret; addr = device_get_phy_addr(priv, dev); #ifdef CFG_FEC_MXC_PHYADDR @@ -1175,6 +1176,17 @@ static int fec_phy_init(struct fec_priv *priv, struct udevice *dev) if (!phydev) return -ENODEV; + switch (priv->interface) { + case PHY_INTERFACE_MODE_MII: + case PHY_INTERFACE_MODE_RMII: + ret = phy_set_supported(phydev, SPEED_100); + if (ret) + return ret; + break; + default: + break; + } + priv->phydev = phydev; priv->phydev->node = priv->phy_of_node; phy_config(phydev); @@ -1354,10 +1366,10 @@ static int fecmxc_probe(struct udevice *dev) if (!bus) { dm_mii_bus = false; #ifdef CONFIG_FEC_MXC_MDIO_BASE - bus = fec_get_miibus((ulong)CONFIG_FEC_MXC_MDIO_BASE, + bus = fec_get_miibus(dev, (ulong)CONFIG_FEC_MXC_MDIO_BASE, dev_seq(dev)); #else - bus = fec_get_miibus((ulong)priv->eth, dev_seq(dev)); + bus = fec_get_miibus(dev, (ulong)priv->eth, dev_seq(dev)); #endif } if (!bus) { @@ -1491,4 +1503,5 @@ U_BOOT_DRIVER(fecmxc_gem) = { .ops = &fecmxc_ops, .priv_auto = sizeof(struct fec_priv), .plat_auto = sizeof(struct eth_pdata), + .flags = DM_FLAG_ACTIVE_DMA, }; diff --git a/drivers/net/rswitch.c b/drivers/net/rswitch.c index 8e1b6e2f6f6..62d3f39f071 100644 --- a/drivers/net/rswitch.c +++ b/drivers/net/rswitch.c @@ -36,95 +36,94 @@ #define RSWITCH_MAX_CTAG_PCP 7 /* Registers */ -#define RSWITCH_COMA_OFFSET 0x00009000 -#define RSWITCH_ETHA_OFFSET 0x0000a000 /* with RMAC */ -#define RSWITCH_ETHA_SIZE 0x00002000 /* with RMAC */ +#define RSWITCH_COMA_OFFSET 0x00009000 +#define RSWITCH_ETHA_OFFSET 0x0000a000 /* with RMAC */ +#define RSWITCH_ETHA_SIZE 0x00002000 /* with RMAC */ #define RSWITCH_GWCA_OFFSET 0x00010000 #define RSWITCH_GWCA_SIZE 0x00002000 -#define FWRO 0 -#define CARO RSWITCH_COMA_OFFSET -#define GWRO 0 -#define TARO 0 -#define RMRO 0x1000 - -enum rswitch_reg { - EAMC = TARO + 0x0000, - EAMS = TARO + 0x0004, - EATDQDC = TARO + 0x0060, - EATTFC = TARO + 0x0138, - EATASRIRM = TARO + 0x03E4, - - GWMC = GWRO + 0x0000, - GWMS = GWRO + 0x0004, - GWMTIRM = GWRO + 0x0100, - GWVCC = GWRO + 0x0130, - GWTTFC = GWRO + 0x0138, - GWDCBAC0 = GWRO + 0x0194, - GWDCBAC1 = GWRO + 0x0198, - GWTRC = GWRO + 0x0200, - GWARIRM = GWRO + 0x0380, - GWDCC = GWRO + 0x0400, - - RRC = CARO + 0x0004, - RCEC = CARO + 0x0008, - RCDC = CARO + 0x000C, - CABPIRM = CARO + 0x0140, - - FWPC0 = FWRO + 0x0100, - FWPBFC = FWRO + 0x4A00, - FWPBFCSDC = FWRO + 0x4A04, - - MPSM = RMRO + 0x0000, - MPIC = RMRO + 0x0004, - MRMAC0 = RMRO + 0x0084, - MRMAC1 = RMRO + 0x0088, - MRAFC = RMRO + 0x008C, - MRSCE = RMRO + 0x0090, - MRSCP = RMRO + 0x0094, - MLVC = RMRO + 0x0180, - MLBC = RMRO + 0x0188, - MXGMIIC = RMRO + 0x0190, - MPCH = RMRO + 0x0194, - MANM = RMRO + 0x019C, - MMIS0 = RMRO + 0x0210, - MMIS1 = RMRO + 0x0220, -}; +#define FWRO 0 +#define CARO RSWITCH_COMA_OFFSET +#define GWRO 0 +#define TARO 0 +#define RMRO 0x1000 + +/* List of TSNA registers (ETHA) */ +#define EAMC (TARO + 0x0000) +#define EAMS (TARO + 0x0004) +#define EATDQDCR (TARO + 0x0060) +#define EATTFC (TARO + 0x0138) +#define EATASRIRM (TARO + 0x03e4) +/* Gateway CPU agent block (GWCA) */ +#define GWMC (GWRO + 0x0000) +#define GWMS (GWRO + 0x0004) +#define GWMTIRM (GWRO + 0x0100) +#define GWVCC (GWRO + 0x0130) +#define GWTTFC (GWRO + 0x0138) +#define GWDCBAC0 (GWRO + 0x0194) +#define GWDCBAC1 (GWRO + 0x0198) +#define GWTRCR (GWRO + 0x0200) +#define GWARIRM (GWRO + 0x0380) +#define GWDCCR (GWRO + 0x0400) +/* List of Common Agent registers (COMA) */ +#define RRC (CARO + 0x0004) +#define RCEC (CARO + 0x0008) +#define RCDC (CARO + 0x000c) +#define CABPIRM (CARO + 0x0140) +/* List of MFWD registers */ +#define FWPC (FWRO + 0x0100) +#define FWPBFCR (FWRO + 0x4a00) +#define FWPBFCSDCR (FWRO + 0x4a04) +/* List of RMAC registers (RMAC) */ +#define MPSM (RMRO + 0x0000) +#define MPIC (RMRO + 0x0004) +#define MRMAC0 (RMRO + 0x0084) +#define MRMAC1 (RMRO + 0x0088) +#define MRAFC (RMRO + 0x008c) +#define MRSCE (RMRO + 0x0090) +#define MRSCP (RMRO + 0x0094) +#define MLVC (RMRO + 0x0180) +#define MLBC (RMRO + 0x0188) +#define MXGMIIC (RMRO + 0x0190) +#define MPCH (RMRO + 0x0194) +#define MANM (RMRO + 0x019c) +#define MMIS0 (RMRO + 0x0210) +#define MMIS1 (RMRO + 0x0220) /* COMA */ -#define RRC_RR BIT(0) -#define RCEC_RCE BIT(16) +#define RRC_RR BIT(0) +#define RCEC_RCE BIT(16) -#define CABPIRM_BPIOG BIT(0) -#define CABPIRM_BPR BIT(1) +#define CABPIRM_BPIOG BIT(0) +#define CABPIRM_BPR BIT(1) /* MFWD */ -#define FWPC0(i) (FWPC0 + (i) * 0x10) -#define FWPC0_LTHTA BIT(0) -#define FWPC0_IP4UE BIT(3) -#define FWPC0_IP4TE BIT(4) -#define FWPC0_IP4OE BIT(5) -#define FWPC0_L2SE BIT(9) -#define FWPC0_IP4EA BIT(10) -#define FWPC0_IPDSA BIT(12) -#define FWPC0_IPHLA BIT(18) -#define FWPC0_MACSDA BIT(20) -#define FWPC0_MACHLA BIT(26) -#define FWPC0_MACHMA BIT(27) -#define FWPC0_VLANSA BIT(28) - -#define FWPC0_DEFAULT (FWPC0_LTHTA | FWPC0_IP4UE | FWPC0_IP4TE | \ - FWPC0_IP4OE | FWPC0_L2SE | FWPC0_IP4EA | \ - FWPC0_IPDSA | FWPC0_IPHLA | FWPC0_MACSDA | \ - FWPC0_MACHLA | FWPC0_MACHMA | FWPC0_VLANSA) - -#define FWPBFC(i) (FWPBFC + (i) * 0x10) -#define FWPBFCSDC(j, i) (FWPBFCSDC + (i) * 0x10 + (j) * 0x04) +#define FWPC0(i) (FWPC + (i) * 0x10) +#define FWPC0_LTHTA BIT(0) +#define FWPC0_IP4UE BIT(3) +#define FWPC0_IP4TE BIT(4) +#define FWPC0_IP4OE BIT(5) +#define FWPC0_L2SE BIT(9) +#define FWPC0_IP4EA BIT(10) +#define FWPC0_IPDSA BIT(12) +#define FWPC0_IPHLA BIT(18) +#define FWPC0_MACSDA BIT(20) +#define FWPC0_MACHLA BIT(26) +#define FWPC0_MACHMA BIT(27) +#define FWPC0_VLANSA BIT(28) + +#define FWPC0_DEFAULT (FWPC0_LTHTA | FWPC0_IP4UE | FWPC0_IP4TE | \ + FWPC0_IP4OE | FWPC0_L2SE | FWPC0_IP4EA | \ + FWPC0_IPDSA | FWPC0_IPHLA | FWPC0_MACSDA | \ + FWPC0_MACHLA | FWPC0_MACHMA | FWPC0_VLANSA) + +#define FWPBFC(i) (FWPBFCR + (i) * 0x10) +#define FWPBFCSDC(j, i) (FWPBFCSDCR + (i) * 0x10 + (j) * 0x04) /* ETHA */ #define EATASRIRM_TASRIOG BIT(0) #define EATASRIRM_TASRR BIT(1) -#define EATDQDC(q) (EATDQDC + (q) * 0x04) +#define EATDQDC(q) (EATDQDCR + (q) * 0x04) #define EATDQDC_DQD (0xff) /* RMAC */ @@ -149,8 +148,8 @@ enum rswitch_reg { #define MDIO_WRITE_C45 0x01 #define MDIO_ADDR_C45 0x00 -#define MDIO_READ_C22 0x02 -#define MDIO_WRITE_C22 0x01 +#define MDIO_READ_C22 0x02 +#define MDIO_WRITE_C22 0x01 #define MPSM_POP_MASK (0x03 << 13) #define MPSM_PRA_MASK (0x1f << 8) @@ -189,8 +188,8 @@ enum rswitch_gwca_mode { #define GWARIRM_ARR BIT(1) #define GWVCC_VEM_SC_TAG (0x3 << 16) #define GWDCBAC0_DCBAUP (0xff) -#define GWTRC(i) (GWTRC + (i) * 0x04) -#define GWDCC(i) (GWDCC + (i) * 0x04) +#define GWTRC(i) (GWTRCR + (i) * 0x04) +#define GWDCC(i) (GWDCCR + (i) * 0x04) #define GWDCC_DQT BIT(11) #define GWDCC_BALR BIT(24) @@ -356,15 +355,52 @@ static int rswitch_gwca_change_mode(struct rswitch_port_priv *priv, return ret; } +static int rswitch_mii_access_c22(struct rswitch_etha *etha, bool read, + int phyad, int regad, int data) +{ + const u32 pop = read ? MDIO_READ_C22 : MDIO_WRITE_C22; + u32 val, pval; + int ret; + + /* Clear Station Management Mode : Clause 22 */ + clrbits_le32(etha->addr + MPSM, MPSM_MFF_C45); + + /* Clear completion flags */ + writel(MMIS1_CLEAR_FLAGS, etha->addr + MMIS1); + + /* Submit C22 access to PHY */ + val = MPSM_PSME | (pop << 13) | (regad << 8) | (phyad << 3); + if (!read) + val |= data << 16; + writel(val, etha->addr + MPSM); + + ret = readl_poll_sleep_timeout(etha->addr + MPSM, pval, + !(pval & MPSM_PSME), + RSWITCH_SLEEP_US, + RSWITCH_TIMEOUT_US); + if (ret) + return ret; + + if (!read) + return 0; + + /* Read data */ + ret = (readl(etha->addr + MPSM) & MPSM_PRD_MASK) >> 16; + + /* Clear read completion flag */ + setbits_le32(etha->addr + MMIS1, MMIS1_PRACS); + + return ret; +} + static int rswitch_mii_access_c45(struct rswitch_etha *etha, bool read, int phyad, int devad, int regad, int data) { u32 pval, val; int ret; - /* No match device */ - if (devad == 0xffffffff) - return 0; + /* Set Station Management Mode : Clause 45 */ + setbits_le32(etha->addr + MPSM, MPSM_MFF_C45); /* Clear completion flags */ writel(MMIS1_CLEAR_FLAGS, etha->addr + MMIS1); @@ -418,7 +454,6 @@ static int rswitch_mii_read_c45(struct mii_dev *miidev, int phyad, int devad, in struct rswitch_port_priv *priv = miidev->priv; struct rswitch_etha *etha = &priv->etha; int val; - int reg; /* Change to disable mode */ rswitch_etha_change_mode(priv, EAMC_OPC_DISABLE); @@ -427,15 +462,17 @@ static int rswitch_mii_read_c45(struct mii_dev *miidev, int phyad, int devad, in rswitch_etha_change_mode(priv, EAMC_OPC_CONFIG); /* Enable Station Management clock */ - reg = readl(etha->addr + MPIC); - reg &= ~MPIC_PSMCS_MASK & ~MPIC_PSMHT_MASK; - writel(reg | MPIC_MDC_CLK_SET, etha->addr + MPIC); - - /* Set Station Management Mode : Clause 45 */ - setbits_le32(etha->addr + MPSM, MPSM_MFF_C45); + clrsetbits_le32(etha->addr + MPIC, + MPIC_PSMCS_MASK | MPIC_PSMHT_MASK, + MPIC_MDC_CLK_SET); /* Access PHY register */ - val = rswitch_mii_access_c45(etha, true, phyad, devad, regad, 0); + if (devad != MDIO_DEVAD_NONE) /* Definitelly C45 */ + val = rswitch_mii_access_c45(etha, true, phyad, devad, regad, 0); + else if (etha->phydev->is_c45) /* C22 access to C45 PHY */ + val = rswitch_mii_access_c45(etha, true, phyad, 1, regad, 0); + else + val = rswitch_mii_access_c22(etha, true, phyad, regad, 0); /* Disable Station Management Clock */ clrbits_le32(etha->addr + MPIC, MPIC_PSMCS_MASK); @@ -450,7 +487,6 @@ int rswitch_mii_write_c45(struct mii_dev *miidev, int phyad, int devad, int rega { struct rswitch_port_priv *priv = miidev->priv; struct rswitch_etha *etha = &priv->etha; - int reg; /* Change to disable mode */ rswitch_etha_change_mode(priv, EAMC_OPC_DISABLE); @@ -459,15 +495,17 @@ int rswitch_mii_write_c45(struct mii_dev *miidev, int phyad, int devad, int rega rswitch_etha_change_mode(priv, EAMC_OPC_CONFIG); /* Enable Station Management clock */ - reg = readl(etha->addr + MPIC); - reg &= ~MPIC_PSMCS_MASK & ~MPIC_PSMHT_MASK; - writel(reg | MPIC_MDC_CLK_SET, etha->addr + MPIC); - - /* Set Station Management Mode : Clause 45 */ - setbits_le32(etha->addr + MPSM, MPSM_MFF_C45); + clrsetbits_le32(etha->addr + MPIC, + MPIC_PSMCS_MASK | MPIC_PSMHT_MASK, + MPIC_MDC_CLK_SET); /* Access PHY register */ - rswitch_mii_access_c45(etha, false, phyad, devad, regad, data); + if (devad != MDIO_DEVAD_NONE) /* Definitelly C45 */ + rswitch_mii_access_c45(etha, false, phyad, devad, regad, data); + else if (etha->phydev->is_c45) /* C22 access to C45 PHY */ + rswitch_mii_access_c45(etha, false, phyad, 1, regad, data); + else + rswitch_mii_access_c22(etha, false, phyad, regad, data); /* Disable Station Management Clock */ clrbits_le32(etha->addr + MPIC, MPIC_PSMCS_MASK); @@ -837,6 +875,7 @@ static int rswitch_send(struct udevice *dev, void *packet, int len) /* Update TX descriptor */ rswitch_flush_dcache((uintptr_t)packet, len); + rswitch_invalidate_dcache((uintptr_t)desc, sizeof(*desc)); memset(desc, 0x0, sizeof(*desc)); desc->die_dt = DT_FSINGLE; desc->info_ds = len; @@ -1112,6 +1151,9 @@ static int rswitch_bind(struct udevice *parent) return -ENOENT; ofnode_for_each_subnode(node, ports_np) { + if (!ofnode_is_enabled(node)) + continue; + ret = device_bind_with_driver_data(parent, drv, ofnode_get_name(node), (ulong)priv, node, &dev); diff --git a/drivers/pci/pcie_starfive_jh7110.c b/drivers/pci/pcie_starfive_jh7110.c index 569fbfd35c8..51aca7359ff 100644 --- a/drivers/pci/pcie_starfive_jh7110.c +++ b/drivers/pci/pcie_starfive_jh7110.c @@ -25,13 +25,19 @@ #include "pcie_plda_common.h" /* system control */ -#define STG_SYSCON_K_RP_NEP_MASK BIT(8) +#define STG_SYSCON_PCIE0_BASE 0x48 +#define STG_SYSCON_PCIE1_BASE 0x1f8 + +#define STG_SYSCON_AR_OFFSET 0x78 #define STG_SYSCON_AXI4_SLVL_ARFUNC_MASK GENMASK(22, 8) #define STG_SYSCON_AXI4_SLVL_ARFUNC_SHIFT 8 +#define STG_SYSCON_AW_OFFSET 0x7c #define STG_SYSCON_AXI4_SLVL_AWFUNC_MASK GENMASK(14, 0) #define STG_SYSCON_CLKREQ_MASK BIT(22) #define STG_SYSCON_CKREF_SRC_SHIFT 18 #define STG_SYSCON_CKREF_SRC_MASK GENMASK(19, 18) +#define STG_SYSCON_RP_NEP_OFFSET 0xe8 +#define STG_SYSCON_K_RP_NEP_MASK BIT(8) DECLARE_GLOBAL_DATA_PTR; @@ -41,9 +47,7 @@ struct starfive_pcie { struct reset_ctl_bulk rsts; struct gpio_desc reset_gpio; struct regmap *regmap; - u32 stg_arfun; - u32 stg_awfun; - u32 stg_rp_nep; + unsigned int stg_pcie_base; }; static int starfive_pcie_atr_init(struct starfive_pcie *priv) @@ -92,7 +96,6 @@ static int starfive_pcie_get_syscon(struct udevice *dev) struct starfive_pcie *priv = dev_get_priv(dev); struct udevice *syscon; struct ofnode_phandle_args syscfg_phandle; - u32 cells[4]; int ret; /* get corresponding syscon phandle */ @@ -117,20 +120,6 @@ static int starfive_pcie_get_syscon(struct udevice *dev) return -ENODEV; } - /* get syscon register offset */ - ret = dev_read_u32_array(dev, "starfive,stg-syscon", - cells, ARRAY_SIZE(cells)); - if (ret) { - dev_err(dev, "Get syscon register err %d\n", ret); - return -EINVAL; - } - - dev_dbg(dev, "Get syscon values: %x, %x, %x\n", - cells[1], cells[2], cells[3]); - priv->stg_arfun = cells[1]; - priv->stg_awfun = cells[2]; - priv->stg_rp_nep = cells[3]; - return 0; } @@ -138,8 +127,9 @@ static int starfive_pcie_parse_dt(struct udevice *dev) { struct starfive_pcie *priv = dev_get_priv(dev); int ret; + u32 domain_nr; - priv->plda.reg_base = (void *)dev_read_addr_name(dev, "reg"); + priv->plda.reg_base = (void *)dev_read_addr_name(dev, "apb"); if (priv->plda.reg_base == (void __iomem *)FDT_ADDR_T_NONE) { dev_err(dev, "Missing required reg address range\n"); return -EINVAL; @@ -147,7 +137,7 @@ static int starfive_pcie_parse_dt(struct udevice *dev) priv->plda.cfg_base = (void *)dev_read_addr_size_name(dev, - "config", + "cfg", &priv->plda.cfg_size); if (priv->plda.cfg_base == (void __iomem *)FDT_ADDR_T_NONE) { dev_err(dev, "Missing required config address range"); @@ -172,7 +162,18 @@ static int starfive_pcie_parse_dt(struct udevice *dev) return ret; } - ret = gpio_request_by_name(dev, "reset-gpios", 0, &priv->reset_gpio, + ret = dev_read_u32(dev, "linux,pci-domain", &domain_nr); + if (ret) { + dev_err(dev, "Can't get pci domain: %d\n", ret); + return ret; + } + + if (domain_nr == 0) + priv->stg_pcie_base = STG_SYSCON_PCIE0_BASE; + else + priv->stg_pcie_base = STG_SYSCON_PCIE1_BASE; + + ret = gpio_request_by_name(dev, "perst-gpios", 0, &priv->reset_gpio, GPIOD_IS_OUT); if (ret) { dev_err(dev, "Can't get reset-gpio: %d\n", ret); @@ -208,12 +209,12 @@ static int starfive_pcie_init_port(struct udevice *dev) /* Disable physical functions except #0 */ for (i = 1; i < PLDA_FUNC_NUM; i++) { regmap_update_bits(priv->regmap, - priv->stg_arfun, + priv->stg_pcie_base + STG_SYSCON_AR_OFFSET, STG_SYSCON_AXI4_SLVL_ARFUNC_MASK, (i << PLDA_PHY_FUNC_SHIFT) << STG_SYSCON_AXI4_SLVL_ARFUNC_SHIFT); regmap_update_bits(priv->regmap, - priv->stg_awfun, + priv->stg_pcie_base + STG_SYSCON_AW_OFFSET, STG_SYSCON_AXI4_SLVL_AWFUNC_MASK, i << PLDA_PHY_FUNC_SHIFT); @@ -222,11 +223,11 @@ static int starfive_pcie_init_port(struct udevice *dev) /* Disable physical functions */ regmap_update_bits(priv->regmap, - priv->stg_arfun, + priv->stg_pcie_base + STG_SYSCON_AR_OFFSET, STG_SYSCON_AXI4_SLVL_ARFUNC_MASK, 0); regmap_update_bits(priv->regmap, - priv->stg_awfun, + priv->stg_pcie_base + STG_SYSCON_AW_OFFSET, STG_SYSCON_AXI4_SLVL_AWFUNC_MASK, 0); @@ -273,17 +274,17 @@ static int starfive_pcie_probe(struct udevice *dev) return ret; regmap_update_bits(priv->regmap, - priv->stg_rp_nep, + priv->stg_pcie_base + STG_SYSCON_RP_NEP_OFFSET, STG_SYSCON_K_RP_NEP_MASK, STG_SYSCON_K_RP_NEP_MASK); regmap_update_bits(priv->regmap, - priv->stg_awfun, + priv->stg_pcie_base + STG_SYSCON_AW_OFFSET, STG_SYSCON_CKREF_SRC_MASK, 2 << STG_SYSCON_CKREF_SRC_SHIFT); regmap_update_bits(priv->regmap, - priv->stg_awfun, + priv->stg_pcie_base + STG_SYSCON_AW_OFFSET, STG_SYSCON_CLKREQ_MASK, STG_SYSCON_CLKREQ_MASK); diff --git a/drivers/phy/phy-uclass.c b/drivers/phy/phy-uclass.c index 777d952b041..714be123856 100644 --- a/drivers/phy/phy-uclass.c +++ b/drivers/phy/phy-uclass.c @@ -415,7 +415,7 @@ int generic_phy_get_bulk(struct udevice *dev, struct phy_bulk *bulk) if (!dev_read_prop(dev, "phys", NULL)) { phydev = dev->parent; if (!dev_read_prop(phydev, "phys", NULL)) { - pr_err("%s : no phys property\n", __func__); + pr_debug("%s : no phys property\n", __func__); return 0; } } diff --git a/drivers/pinctrl/nxp/pinctrl-imx93.c b/drivers/pinctrl/nxp/pinctrl-imx93.c index 9a5b9de6d75..8d8ffec6d9a 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx93.c +++ b/drivers/pinctrl/nxp/pinctrl-imx93.c @@ -22,6 +22,7 @@ static int imx93_pinctrl_probe(struct udevice *dev) static const struct udevice_id imx93_pinctrl_match[] = { { .compatible = "fsl,imx93-iomuxc", .data = (ulong)&imx93_pinctrl_soc_info }, + { .compatible = "fsl,imx91-iomuxc", .data = (ulong)&imx93_pinctrl_soc_info }, { /* sentinel */ } }; diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig index a209193b332..560f7275454 100644 --- a/drivers/pinctrl/renesas/Kconfig +++ b/drivers/pinctrl/renesas/Kconfig @@ -11,6 +11,17 @@ config PINCTRL_PFC both the GPIO definitions and pin control functions for each available multiplex function. +config PINCTRL_PFC_FULL + bool "Renesas pin control drivers (full size)" + depends on PINCTRL_PFC + help + By default the pin multiplexing tables used by U-Boot are reduced + to keep the size of the bootloader low. Enable this option to use + full pin multiplexing tables the same way they are included in the + Linux kernel. This includes pin multiplexing options for Audio, CAN, + CANFD, DU, INTC, INTC-EX, MSIOF, PWM, SSI, for which there is no + U-Boot driver. + config PINCTRL_PFC_R8A7790 bool "Renesas R-Car Gen2 R8A7790 pin control driver" depends on PINCTRL_PFC diff --git a/drivers/pinctrl/renesas/pfc-r8a7790.c b/drivers/pinctrl/renesas/pfc-r8a7790.c index acd6b01f497..4d6ce06cf16 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7790.c +++ b/drivers/pinctrl/renesas/pfc-r8a7790.c @@ -1745,6 +1745,7 @@ static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_NOGP_ALL(), }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - AUDIO CLOCK ------------------------------------------------------------ */ static const unsigned int audio_clk_a_pins[] = { /* CLK A */ @@ -1795,6 +1796,8 @@ static const unsigned int audio_clkout_d_pins[] = { static const unsigned int audio_clkout_d_mux[] = { AUDIO_CLKOUT_D_MARK, }; +#endif + /* - AVB -------------------------------------------------------------------- */ static const unsigned int avb_link_pins[] = { RCAR_GP_PIN(3, 11), @@ -1870,6 +1873,8 @@ static const unsigned int avb_gmii_mux[] = { AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK, AVB_COL_MARK, }; + +#ifdef CONFIG_PINCTRL_PFC_FULL /* - CAN0 ----------------------------------------------------------------- */ static const unsigned int can0_data_pins[] = { /* CAN0 RX */ @@ -2048,6 +2053,8 @@ static const unsigned int du2_clk_in_pins[] = { static const unsigned int du2_clk_in_mux[] = { DU_DOTCLKIN2_MARK, }; +#endif + /* - ETH -------------------------------------------------------------------- */ static const unsigned int eth_link_pins[] = { /* LINK */ @@ -2363,6 +2370,8 @@ static const unsigned int iic3_pins[] = { static const unsigned int iic3_mux[] = { IIC3_SCL_MARK, IIC3_SDA_MARK, }; + +#ifdef CONFIG_PINCTRL_PFC_FULL /* - INTC ------------------------------------------------------------------- */ static const unsigned int intc_irq0_pins[] = { /* IRQ */ @@ -2392,6 +2401,7 @@ static const unsigned int intc_irq3_pins[] = { static const unsigned int intc_irq3_mux[] = { IRQ3_MARK, }; +#endif #ifdef CONFIG_PINCTRL_PFC_R8A7790 /* - MLB+ ------------------------------------------------------------------- */ @@ -2441,6 +2451,8 @@ static const unsigned int mmc1_ctrl_pins[] = { static const unsigned int mmc1_ctrl_mux[] = { MMC1_CLK_MARK, MMC1_CMD_MARK, }; + +#ifdef CONFIG_PINCTRL_PFC_FULL /* - MSIOF0 ----------------------------------------------------------------- */ static const unsigned int msiof0_clk_pins[] = { /* SCK */ @@ -2769,6 +2781,8 @@ static const unsigned int pwm6_pins[] = { static const unsigned int pwm6_mux[] = { PWM6_MARK, }; +#endif + /* - QSPI ------------------------------------------------------------------- */ static const unsigned int qspi_ctrl_pins[] = { /* SPCLK, SSL */ @@ -3394,6 +3408,8 @@ static const unsigned int sdhi3_wp_pins[] = { static const unsigned int sdhi3_wp_mux[] = { SD3_WP_MARK, }; + +#ifdef CONFIG_PINCTRL_PFC_FULL /* - SSI -------------------------------------------------------------------- */ static const unsigned int ssi0_data_pins[] = { /* SDATA0 */ @@ -3577,6 +3593,8 @@ static const unsigned int ssi9_ctrl_pins[] = { static const unsigned int ssi9_ctrl_mux[] = { SSI_SCK9_MARK, SSI_WS9_MARK, }; +#endif + /* - TPU0 ------------------------------------------------------------------- */ static const unsigned int tpu0_to0_pins[] = { /* TO */ @@ -3630,6 +3648,8 @@ static const unsigned int usb2_pins[] = { static const unsigned int usb2_mux[] = { USB2_PWEN_MARK, USB2_OVC_MARK, }; + +#ifdef CONFIG_PINCTRL_PFC_FULL /* - VIN0 ------------------------------------------------------------------- */ static const unsigned int vin0_data_pins[] = { /* B */ @@ -4024,6 +4044,7 @@ static const unsigned int vin3_clk_pins[] = { static const unsigned int vin3_clk_mux[] = { VI3_CLK_MARK, }; +#endif static const struct { struct sh_pfc_pin_group common[311]; @@ -4032,6 +4053,7 @@ static const struct { #endif } pinmux_groups = { .common = { +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(audio_clk_a), SH_PFC_PIN_GROUP(audio_clk_b), SH_PFC_PIN_GROUP(audio_clk_c), @@ -4039,12 +4061,14 @@ static const struct { SH_PFC_PIN_GROUP(audio_clkout_b), SH_PFC_PIN_GROUP(audio_clkout_c), SH_PFC_PIN_GROUP(audio_clkout_d), +#endif SH_PFC_PIN_GROUP(avb_link), SH_PFC_PIN_GROUP(avb_magic), SH_PFC_PIN_GROUP(avb_phy_int), SH_PFC_PIN_GROUP(avb_mdio), SH_PFC_PIN_GROUP(avb_mii), SH_PFC_PIN_GROUP(avb_gmii), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(can0_data), SH_PFC_PIN_GROUP(can0_data_b), SH_PFC_PIN_GROUP(can0_data_c), @@ -4063,6 +4087,7 @@ static const struct { SH_PFC_PIN_GROUP(du0_clk_in), SH_PFC_PIN_GROUP(du1_clk_in), SH_PFC_PIN_GROUP(du2_clk_in), +#endif SH_PFC_PIN_GROUP(eth_link), SH_PFC_PIN_GROUP(eth_magic), SH_PFC_PIN_GROUP(eth_mdio), @@ -4106,10 +4131,12 @@ static const struct { SH_PFC_PIN_GROUP(iic2_d), SH_PFC_PIN_GROUP(iic2_e), SH_PFC_PIN_GROUP(iic3), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(intc_irq0), SH_PFC_PIN_GROUP(intc_irq1), SH_PFC_PIN_GROUP(intc_irq2), SH_PFC_PIN_GROUP(intc_irq3), +#endif BUS_DATA_PIN_GROUP(mmc0_data, 1), BUS_DATA_PIN_GROUP(mmc0_data, 4), BUS_DATA_PIN_GROUP(mmc0_data, 8), @@ -4118,6 +4145,7 @@ static const struct { BUS_DATA_PIN_GROUP(mmc1_data, 4), BUS_DATA_PIN_GROUP(mmc1_data, 8), SH_PFC_PIN_GROUP(mmc1_ctrl), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(msiof0_clk), SH_PFC_PIN_GROUP(msiof0_sync), SH_PFC_PIN_GROUP(msiof0_ss1), @@ -4165,6 +4193,7 @@ static const struct { SH_PFC_PIN_GROUP(pwm4), SH_PFC_PIN_GROUP(pwm5), SH_PFC_PIN_GROUP(pwm6), +#endif SH_PFC_PIN_GROUP(qspi_ctrl), BUS_DATA_PIN_GROUP(qspi_data, 2), BUS_DATA_PIN_GROUP(qspi_data, 4), @@ -4257,6 +4286,7 @@ static const struct { SH_PFC_PIN_GROUP(sdhi3_ctrl), SH_PFC_PIN_GROUP(sdhi3_cd), SH_PFC_PIN_GROUP(sdhi3_wp), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(ssi0_data), SH_PFC_PIN_GROUP(ssi0129_ctrl), SH_PFC_PIN_GROUP(ssi1_data), @@ -4283,6 +4313,7 @@ static const struct { SH_PFC_PIN_GROUP(ssi8_c_data), SH_PFC_PIN_GROUP(ssi9_data), SH_PFC_PIN_GROUP(ssi9_ctrl), +#endif SH_PFC_PIN_GROUP(tpu0_to0), SH_PFC_PIN_GROUP(tpu0_to1), SH_PFC_PIN_GROUP(tpu0_to2), @@ -4292,6 +4323,7 @@ static const struct { SH_PFC_PIN_GROUP(usb1), SH_PFC_PIN_GROUP_SUBSET(usb1_pwen, usb1, 0, 1), SH_PFC_PIN_GROUP(usb2), +#ifdef CONFIG_PINCTRL_PFC_FULL BUS_DATA_PIN_GROUP(vin0_data, 24), BUS_DATA_PIN_GROUP(vin0_data, 20), SH_PFC_PIN_GROUP(vin0_data18), @@ -4343,6 +4375,7 @@ static const struct { SH_PFC_PIN_GROUP(vin3_field), SH_PFC_PIN_GROUP(vin3_clkenb), SH_PFC_PIN_GROUP(vin3_clk), +#endif }, #ifdef CONFIG_PINCTRL_PFC_R8A7790 .automotive = { @@ -4351,6 +4384,7 @@ static const struct { #endif /* CONFIG_PINCTRL_PFC_R8A7790 */ }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const audio_clk_groups[] = { "audio_clk_a", "audio_clk_b", @@ -4360,6 +4394,7 @@ static const char * const audio_clk_groups[] = { "audio_clkout_c", "audio_clkout_d", }; +#endif static const char * const avb_groups[] = { "avb_link", @@ -4370,6 +4405,7 @@ static const char * const avb_groups[] = { "avb_gmii", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const can0_groups[] = { "can0_data", "can0_data_b", @@ -4408,6 +4444,7 @@ static const char * const du1_groups[] = { static const char * const du2_groups[] = { "du2_clk_in", }; +#endif static const char * const eth_groups[] = { "eth_link", @@ -4485,12 +4522,14 @@ static const char * const iic3_groups[] = { "iic3", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const intc_groups[] = { "intc_irq0", "intc_irq1", "intc_irq2", "intc_irq3", }; +#endif #ifdef CONFIG_PINCTRL_PFC_R8A7790 static const char * const mlb_groups[] = { @@ -4512,6 +4551,7 @@ static const char * const mmc1_groups[] = { "mmc1_ctrl", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const msiof0_groups[] = { "msiof0_clk", "msiof0_sync", @@ -4591,6 +4631,7 @@ static const char * const pwm5_groups[] = { static const char * const pwm6_groups[] = { "pwm6", }; +#endif static const char * const qspi_groups[] = { "qspi_ctrl", @@ -4729,6 +4770,7 @@ static const char * const sdhi3_groups[] = { "sdhi3_wp", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const ssi_groups[] = { "ssi0_data", "ssi0129_ctrl", @@ -4757,6 +4799,7 @@ static const char * const ssi_groups[] = { "ssi9_data", "ssi9_ctrl", }; +#endif static const char * const tpu0_groups[] = { "tpu0_to0", @@ -4779,6 +4822,7 @@ static const char * const usb2_groups[] = { "usb2", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const vin0_groups[] = { "vin0_data24", "vin0_data20", @@ -4841,6 +4885,7 @@ static const char * const vin3_groups[] = { "vin3_clkenb", "vin3_clk", }; +#endif static const struct { struct sh_pfc_function common[58]; @@ -4849,8 +4894,11 @@ static const struct { #endif } pinmux_functions = { .common = { +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(audio_clk), +#endif SH_PFC_FUNCTION(avb), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(can0), SH_PFC_FUNCTION(can1), SH_PFC_FUNCTION(can_clk), @@ -4858,6 +4906,7 @@ static const struct { SH_PFC_FUNCTION(du0), SH_PFC_FUNCTION(du1), SH_PFC_FUNCTION(du2), +#endif SH_PFC_FUNCTION(eth), SH_PFC_FUNCTION(hscif0), SH_PFC_FUNCTION(hscif1), @@ -4869,9 +4918,12 @@ static const struct { SH_PFC_FUNCTION(iic1), SH_PFC_FUNCTION(iic2), SH_PFC_FUNCTION(iic3), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(intc), +#endif SH_PFC_FUNCTION(mmc0), SH_PFC_FUNCTION(mmc1), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(msiof0), SH_PFC_FUNCTION(msiof1), SH_PFC_FUNCTION(msiof2), @@ -4883,6 +4935,7 @@ static const struct { SH_PFC_FUNCTION(pwm4), SH_PFC_FUNCTION(pwm5), SH_PFC_FUNCTION(pwm6), +#endif SH_PFC_FUNCTION(qspi), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1), @@ -4898,15 +4951,19 @@ static const struct { SH_PFC_FUNCTION(sdhi1), SH_PFC_FUNCTION(sdhi2), SH_PFC_FUNCTION(sdhi3), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(ssi), +#endif SH_PFC_FUNCTION(tpu0), SH_PFC_FUNCTION(usb0), SH_PFC_FUNCTION(usb1), SH_PFC_FUNCTION(usb2), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(vin0), SH_PFC_FUNCTION(vin1), SH_PFC_FUNCTION(vin2), SH_PFC_FUNCTION(vin3), +#endif }, #ifdef CONFIG_PINCTRL_PFC_R8A7790 .automotive = { diff --git a/drivers/pinctrl/renesas/pfc-r8a7791.c b/drivers/pinctrl/renesas/pfc-r8a7791.c index fa94a51e5e7..c6d761bb378 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7791.c +++ b/drivers/pinctrl/renesas/pfc-r8a7791.c @@ -1802,6 +1802,7 @@ static const unsigned int adi_chsel2_b_mux[] = { }; #endif /* CONFIG_PINCTRL_PFC_R8A7791 || CONFIG_PINCTRL_PFC_R8A7793 */ +#ifdef CONFIG_PINCTRL_PFC_FULL /* - Audio Clock ------------------------------------------------------------ */ static const unsigned int audio_clk_a_pins[] = { /* CLK */ @@ -1847,6 +1848,7 @@ static const unsigned int audio_clkout_pins[] = { static const unsigned int audio_clkout_mux[] = { AUDIO_CLKOUT_MARK, }; +#endif /* - AVB -------------------------------------------------------------------- */ static const unsigned int avb_link_pins[] = { @@ -1924,6 +1926,7 @@ static const unsigned int avb_gmii_mux[] = { AVB_COL_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - CAN -------------------------------------------------------------------- */ static const unsigned int can0_data_pins[] = { @@ -2160,6 +2163,8 @@ static const unsigned int du1_clk_in_c_pins[] = { static const unsigned int du1_clk_in_c_mux[] = { DU1_DOTCLKIN_C_MARK, }; +#endif + /* - ETH -------------------------------------------------------------------- */ static const unsigned int eth_link_pins[] = { /* LINK */ @@ -2553,6 +2558,8 @@ static const unsigned int i2c8_c_pins[] = { static const unsigned int i2c8_c_mux[] = { IIC1_SCL_C_MARK, IIC1_SDA_C_MARK, }; + +#ifdef CONFIG_PINCTRL_PFC_FULL /* - INTC ------------------------------------------------------------------- */ static const unsigned int intc_irq0_pins[] = { /* IRQ */ @@ -2582,6 +2589,7 @@ static const unsigned int intc_irq3_pins[] = { static const unsigned int intc_irq3_mux[] = { IRQ3_MARK, }; +#endif #if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793) /* - MLB+ ------------------------------------------------------------------- */ @@ -2623,6 +2631,8 @@ static const unsigned int mmc_ctrl_pins[] = { static const unsigned int mmc_ctrl_mux[] = { MMC_CLK_MARK, MMC_CMD_MARK, }; + +#ifdef CONFIG_PINCTRL_PFC_FULL /* - MSIOF0 ----------------------------------------------------------------- */ static const unsigned int msiof0_clk_pins[] = { /* SCK */ @@ -3192,6 +3202,8 @@ static const unsigned int pwm6_pins[] = { static const unsigned int pwm6_mux[] = { PWM6_MARK, }; +#endif + /* - QSPI ------------------------------------------------------------------- */ static const unsigned int qspi_ctrl_pins[] = { /* SPCLK, SSL */ @@ -3872,6 +3884,7 @@ static const unsigned int sdhi2_wp_mux[] = { SD2_WP_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - SSI -------------------------------------------------------------------- */ static const unsigned int ssi0_data_pins[] = { /* SDATA */ @@ -4124,6 +4137,7 @@ static const unsigned int ssi9_ctrl_b_pins[] = { static const unsigned int ssi9_ctrl_b_mux[] = { SSI_SCK9_B_MARK, SSI_WS9_B_MARK, }; +#endif /* - TPU -------------------------------------------------------------------- */ static const unsigned int tpu_to0_pins[] = { @@ -4169,6 +4183,8 @@ static const unsigned int usb1_mux[] = { USB1_PWEN_MARK, USB1_OVC_MARK, }; + +#ifdef CONFIG_PINCTRL_PFC_FULL /* - VIN0 ------------------------------------------------------------------- */ static const unsigned int vin0_data_pins[] = { /* B */ @@ -4424,6 +4440,7 @@ static const unsigned int vin2_clk_pins[] = { static const unsigned int vin2_clk_mux[] = { VI2_CLK_MARK, }; +#endif static const struct { struct sh_pfc_pin_group common[346]; @@ -4432,17 +4449,20 @@ static const struct { #endif } pinmux_groups = { .common = { +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(audio_clk_a), SH_PFC_PIN_GROUP(audio_clk_b), SH_PFC_PIN_GROUP(audio_clk_b_b), SH_PFC_PIN_GROUP(audio_clk_c), SH_PFC_PIN_GROUP(audio_clkout), +#endif SH_PFC_PIN_GROUP(avb_link), SH_PFC_PIN_GROUP(avb_magic), SH_PFC_PIN_GROUP(avb_phy_int), SH_PFC_PIN_GROUP(avb_mdio), SH_PFC_PIN_GROUP(avb_mii), SH_PFC_PIN_GROUP(avb_gmii), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(can0_data), SH_PFC_PIN_GROUP(can0_data_b), SH_PFC_PIN_GROUP(can0_data_c), @@ -4469,6 +4489,7 @@ static const struct { SH_PFC_PIN_GROUP(du1_clk_in), SH_PFC_PIN_GROUP(du1_clk_in_b), SH_PFC_PIN_GROUP(du1_clk_in_c), +#endif SH_PFC_PIN_GROUP(eth_link), SH_PFC_PIN_GROUP(eth_magic), SH_PFC_PIN_GROUP(eth_mdio), @@ -4524,15 +4545,18 @@ static const struct { SH_PFC_PIN_GROUP(i2c8), SH_PFC_PIN_GROUP(i2c8_b), SH_PFC_PIN_GROUP(i2c8_c), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(intc_irq0), SH_PFC_PIN_GROUP(intc_irq1), SH_PFC_PIN_GROUP(intc_irq2), SH_PFC_PIN_GROUP(intc_irq3), +#endif BUS_DATA_PIN_GROUP(mmc_data, 1), BUS_DATA_PIN_GROUP(mmc_data, 4), BUS_DATA_PIN_GROUP(mmc_data, 8), BUS_DATA_PIN_GROUP(mmc_data, 8, _b), SH_PFC_PIN_GROUP(mmc_ctrl), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(msiof0_clk), SH_PFC_PIN_GROUP(msiof0_sync), SH_PFC_PIN_GROUP(msiof0_ss1), @@ -4614,6 +4638,7 @@ static const struct { SH_PFC_PIN_GROUP(pwm5), SH_PFC_PIN_GROUP(pwm5_b), SH_PFC_PIN_GROUP(pwm6), +#endif SH_PFC_PIN_GROUP(qspi_ctrl), BUS_DATA_PIN_GROUP(qspi_data, 2), BUS_DATA_PIN_GROUP(qspi_data, 4), @@ -4712,6 +4737,7 @@ static const struct { SH_PFC_PIN_GROUP(sdhi2_ctrl), SH_PFC_PIN_GROUP(sdhi2_cd), SH_PFC_PIN_GROUP(sdhi2_wp), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(ssi0_data), SH_PFC_PIN_GROUP(ssi0_data_b), SH_PFC_PIN_GROUP(ssi0129_ctrl), @@ -4740,12 +4766,14 @@ static const struct { SH_PFC_PIN_GROUP(ssi9_data_b), SH_PFC_PIN_GROUP(ssi9_ctrl), SH_PFC_PIN_GROUP(ssi9_ctrl_b), +#endif SH_PFC_PIN_GROUP(tpu_to0), SH_PFC_PIN_GROUP(tpu_to1), SH_PFC_PIN_GROUP(tpu_to2), SH_PFC_PIN_GROUP(tpu_to3), SH_PFC_PIN_GROUP(usb0), SH_PFC_PIN_GROUP(usb1), +#ifdef CONFIG_PINCTRL_PFC_FULL BUS_DATA_PIN_GROUP(vin0_data, 24), BUS_DATA_PIN_GROUP(vin0_data, 20), SH_PFC_PIN_GROUP(vin0_data18), @@ -4778,6 +4806,7 @@ static const struct { SH_PFC_PIN_GROUP(vin2_field), SH_PFC_PIN_GROUP(vin2_clkenb), SH_PFC_PIN_GROUP(vin2_clk), +#endif }, #if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793) .automotive = { @@ -4807,6 +4836,7 @@ static const char * const adi_groups[] = { }; #endif /* CONFIG_PINCTRL_PFC_R8A7791 || CONFIG_PINCTRL_PFC_R8A7793 */ +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const audio_clk_groups[] = { "audio_clk_a", "audio_clk_b", @@ -4814,6 +4844,7 @@ static const char * const audio_clk_groups[] = { "audio_clk_c", "audio_clkout", }; +#endif static const char * const avb_groups[] = { "avb_link", @@ -4824,6 +4855,7 @@ static const char * const avb_groups[] = { "avb_gmii", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const can0_groups[] = { "can0_data", "can0_data_b", @@ -4887,6 +4919,7 @@ static const char * const du1_groups[] = { "du1_clk_in_b", "du1_clk_in_c", }; +#endif static const char * const eth_groups[] = { "eth_link", @@ -4976,12 +5009,14 @@ static const char * const i2c8_groups[] = { "i2c8_c", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const intc_groups[] = { "intc_irq0", "intc_irq1", "intc_irq2", "intc_irq3", }; +#endif #if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793) static const char * const mlb_groups[] = { @@ -4997,6 +5032,7 @@ static const char * const mmc_groups[] = { "mmc_ctrl", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const msiof0_groups[] = { "msiof0_clk", "msiof0_sync", @@ -5107,6 +5143,7 @@ static const char * const pwm5_groups[] = { static const char * const pwm6_groups[] = { "pwm6", }; +#endif static const char * const qspi_groups[] = { "qspi_ctrl", @@ -5254,6 +5291,7 @@ static const char * const sdhi2_groups[] = { "sdhi2_wp", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const ssi_groups[] = { "ssi0_data", "ssi0_data_b", @@ -5284,6 +5322,7 @@ static const char * const ssi_groups[] = { "ssi9_ctrl", "ssi9_ctrl_b", }; +#endif static const char * const tpu_groups[] = { "tpu_to0", @@ -5299,6 +5338,7 @@ static const char * const usb1_groups[] = { "usb1", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const vin0_groups[] = { "vin0_data24", "vin0_data20", @@ -5339,6 +5379,7 @@ static const char * const vin2_groups[] = { "vin2_clkenb", "vin2_clk", }; +#endif static const struct { struct sh_pfc_function common[58]; @@ -5347,14 +5388,18 @@ static const struct { #endif } pinmux_functions = { .common = { +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(audio_clk), +#endif SH_PFC_FUNCTION(avb), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(can0), SH_PFC_FUNCTION(can1), SH_PFC_FUNCTION(can_clk), SH_PFC_FUNCTION(du), SH_PFC_FUNCTION(du0), SH_PFC_FUNCTION(du1), +#endif SH_PFC_FUNCTION(eth), SH_PFC_FUNCTION(hscif0), SH_PFC_FUNCTION(hscif1), @@ -5366,8 +5411,11 @@ static const struct { SH_PFC_FUNCTION(i2c4), SH_PFC_FUNCTION(i2c7), SH_PFC_FUNCTION(i2c8), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(intc), +#endif SH_PFC_FUNCTION(mmc), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(msiof0), SH_PFC_FUNCTION(msiof1), SH_PFC_FUNCTION(msiof2), @@ -5378,6 +5426,7 @@ static const struct { SH_PFC_FUNCTION(pwm4), SH_PFC_FUNCTION(pwm5), SH_PFC_FUNCTION(pwm6), +#endif SH_PFC_FUNCTION(qspi), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1), @@ -5398,13 +5447,17 @@ static const struct { SH_PFC_FUNCTION(sdhi0), SH_PFC_FUNCTION(sdhi1), SH_PFC_FUNCTION(sdhi2), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(ssi), +#endif SH_PFC_FUNCTION(tpu), SH_PFC_FUNCTION(usb0), SH_PFC_FUNCTION(usb1), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(vin0), SH_PFC_FUNCTION(vin1), SH_PFC_FUNCTION(vin2), +#endif }, #if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793) .automotive = { diff --git a/drivers/pinctrl/renesas/pfc-r8a7792.c b/drivers/pinctrl/renesas/pfc-r8a7792.c index 7c1e6d40749..d2ff1d9d1a6 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7792.c +++ b/drivers/pinctrl/renesas/pfc-r8a7792.c @@ -831,6 +831,8 @@ static const unsigned int avb_avtp_match_pins[] = { static const unsigned int avb_avtp_match_mux[] = { AVB_AVTP_MATCH_MARK, }; + +#ifdef CONFIG_PINCTRL_PFC_FULL /* - CAN -------------------------------------------------------------------- */ static const unsigned int can0_data_pins[] = { /* TX, RX */ @@ -996,6 +998,8 @@ static const unsigned int intc_irq3_pins[] = { static const unsigned int intc_irq3_mux[] = { IRQ3_MARK, }; +#endif + /* - LBSC ------------------------------------------------------------------- */ static const unsigned int lbsc_cs0_pins[] = { /* CS0# */ @@ -1053,6 +1057,8 @@ static const unsigned int lbsc_ex_cs5_pins[] = { static const unsigned int lbsc_ex_cs5_mux[] = { EX_CS5_N_MARK, }; + +#ifdef CONFIG_PINCTRL_PFC_FULL /* - MSIOF0 ----------------------------------------------------------------- */ static const unsigned int msiof0_clk_pins[] = { /* SCK */ @@ -1111,6 +1117,8 @@ static const unsigned int msiof1_tx_pins[] = { static const unsigned int msiof1_tx_mux[] = { MSIOF1_TXD_MARK, }; +#endif + /* - QSPI ------------------------------------------------------------------- */ static const unsigned int qspi_ctrl_pins[] = { /* SPCLK, SSL */ @@ -1231,6 +1239,8 @@ static const unsigned int sdhi0_wp_pins[] = { static const unsigned int sdhi0_wp_mux[] = { SD0_WP_MARK, }; + +#ifdef CONFIG_PINCTRL_PFC_FULL /* - VIN0 ------------------------------------------------------------------- */ static const unsigned int vin0_data_pins[] = { /* B */ @@ -1645,6 +1655,7 @@ static const unsigned int vin5_clk_pins[] = { static const unsigned int vin5_clk_mux[] = { VI5_CLK_MARK, }; +#endif static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(avb_link), @@ -1654,6 +1665,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(avb_mii), SH_PFC_PIN_GROUP(avb_gmii), SH_PFC_PIN_GROUP(avb_avtp_match), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(can0_data), SH_PFC_PIN_GROUP(can1_data), SH_PFC_PIN_GROUP(can_clk), @@ -1672,6 +1684,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(intc_irq1), SH_PFC_PIN_GROUP(intc_irq2), SH_PFC_PIN_GROUP(intc_irq3), +#endif SH_PFC_PIN_GROUP(lbsc_cs0), SH_PFC_PIN_GROUP(lbsc_cs1), SH_PFC_PIN_GROUP(lbsc_ex_cs0), @@ -1680,6 +1693,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(lbsc_ex_cs3), SH_PFC_PIN_GROUP(lbsc_ex_cs4), SH_PFC_PIN_GROUP(lbsc_ex_cs5), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(msiof0_clk), SH_PFC_PIN_GROUP(msiof0_sync), SH_PFC_PIN_GROUP(msiof0_rx), @@ -1688,6 +1702,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(msiof1_sync), SH_PFC_PIN_GROUP(msiof1_rx), SH_PFC_PIN_GROUP(msiof1_tx), +#endif SH_PFC_PIN_GROUP(qspi_ctrl), BUS_DATA_PIN_GROUP(qspi_data, 2), BUS_DATA_PIN_GROUP(qspi_data, 4), @@ -1706,6 +1721,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(sdhi0_ctrl), SH_PFC_PIN_GROUP(sdhi0_cd), SH_PFC_PIN_GROUP(sdhi0_wp), +#ifdef CONFIG_PINCTRL_PFC_FULL BUS_DATA_PIN_GROUP(vin0_data, 24), BUS_DATA_PIN_GROUP(vin0_data, 20), SH_PFC_PIN_GROUP(vin0_data18), @@ -1762,6 +1778,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(vin5_field), SH_PFC_PIN_GROUP(vin5_clkenb), SH_PFC_PIN_GROUP(vin5_clk), +#endif }; static const char * const avb_groups[] = { @@ -1774,6 +1791,7 @@ static const char * const avb_groups[] = { "avb_avtp_match", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const can0_groups[] = { "can0_data", "can_clk", @@ -1807,6 +1825,7 @@ static const char * const intc_groups[] = { "intc_irq2", "intc_irq3", }; +#endif static const char * const lbsc_groups[] = { "lbsc_cs0", @@ -1819,6 +1838,7 @@ static const char * const lbsc_groups[] = { "lbsc_ex_cs5", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const msiof0_groups[] = { "msiof0_clk", "msiof0_sync", @@ -1832,6 +1852,7 @@ static const char * const msiof1_groups[] = { "msiof1_rx", "msiof1_tx", }; +#endif static const char * const qspi_groups[] = { "qspi_ctrl", @@ -1869,6 +1890,7 @@ static const char * const sdhi0_groups[] = { "sdhi0_wp", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const vin0_groups[] = { "vin0_data24", "vin0_data20", @@ -1942,29 +1964,36 @@ static const char * const vin5_groups[] = { "vin5_clkenb", "vin5_clk", }; +#endif static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(avb), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(can0), SH_PFC_FUNCTION(can1), SH_PFC_FUNCTION(du0), SH_PFC_FUNCTION(du1), SH_PFC_FUNCTION(intc), +#endif SH_PFC_FUNCTION(lbsc), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(msiof0), SH_PFC_FUNCTION(msiof1), +#endif SH_PFC_FUNCTION(qspi), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1), SH_PFC_FUNCTION(scif2), SH_PFC_FUNCTION(scif3), SH_PFC_FUNCTION(sdhi0), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(vin0), SH_PFC_FUNCTION(vin1), SH_PFC_FUNCTION(vin2), SH_PFC_FUNCTION(vin3), SH_PFC_FUNCTION(vin4), SH_PFC_FUNCTION(vin5), +#endif }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { diff --git a/drivers/pinctrl/renesas/pfc-r8a7794.c b/drivers/pinctrl/renesas/pfc-r8a7794.c index 2f550218182..a1fa1776bae 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7794.c +++ b/drivers/pinctrl/renesas/pfc-r8a7794.c @@ -1500,6 +1500,7 @@ static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_NOGP_ALL(), }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - Audio Clock ------------------------------------------------------------ */ static const unsigned int audio_clka_pins[] = { /* CLKA */ @@ -1592,6 +1593,8 @@ static const unsigned int audio_clkout_c_pins[] = { static const unsigned int audio_clkout_c_mux[] = { AUDIO_CLKOUT_C_MARK, }; +#endif + /* - AVB -------------------------------------------------------------------- */ static const unsigned int avb_link_pins[] = { RCAR_GP_PIN(3, 26), @@ -1668,6 +1671,7 @@ static const unsigned int avb_gmii_mux[] = { AVB_COL_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - CAN -------------------------------------------------------------------- */ static const unsigned int can0_data_pins[] = { /* TX, RX */ @@ -1950,6 +1954,8 @@ static const unsigned int du1_disp_pins[] = { static const unsigned int du1_disp_mux[] = { DU1_DISP_MARK }; +#endif + /* - ETH -------------------------------------------------------------------- */ static const unsigned int eth_link_pins[] = { /* LINK */ @@ -2316,6 +2322,8 @@ static const unsigned int i2c5_d_pins[] = { static const unsigned int i2c5_d_mux[] = { I2C5_SCL_D_MARK, I2C5_SDA_D_MARK, }; + +#ifdef CONFIG_PINCTRL_PFC_FULL /* - INTC ------------------------------------------------------------------- */ static const unsigned int intc_irq0_pins[] = { /* IRQ0 */ @@ -2387,6 +2395,8 @@ static const unsigned int intc_irq9_pins[] = { static const unsigned int intc_irq9_mux[] = { IRQ9_MARK, }; +#endif + /* - MMCIF ------------------------------------------------------------------ */ static const unsigned int mmc_data_pins[] = { /* D[0:7] */ @@ -2406,6 +2416,8 @@ static const unsigned int mmc_ctrl_pins[] = { static const unsigned int mmc_ctrl_mux[] = { MMC_CLK_MARK, MMC_CMD_MARK, }; + +#ifdef CONFIG_PINCTRL_PFC_FULL /* - MSIOF0 ----------------------------------------------------------------- */ static const unsigned int msiof0_clk_pins[] = { /* SCK */ @@ -2722,6 +2734,8 @@ static const unsigned int pwm6_b_pins[] = { static const unsigned int pwm6_b_mux[] = { PWM6_B_MARK, }; +#endif + /* - QSPI ------------------------------------------------------------------- */ static const unsigned int qspi_ctrl_pins[] = { /* SPCLK, SSL */ @@ -3299,6 +3313,8 @@ static const unsigned int sdhi2_wp_pins[] = { static const unsigned int sdhi2_wp_mux[] = { SD2_WP_MARK, }; + +#ifdef CONFIG_PINCTRL_PFC_FULL /* - SSI -------------------------------------------------------------------- */ static const unsigned int ssi0_data_pins[] = { /* SDATA0 */ @@ -3538,6 +3554,8 @@ static const unsigned int ssi9_ctrl_b_pins[] = { static const unsigned int ssi9_ctrl_b_mux[] = { SSI_SCK9_B_MARK, SSI_WS9_B_MARK, }; +#endif + /* - TPU -------------------------------------------------------------------- */ static const unsigned int tpu_to0_pins[] = { RCAR_GP_PIN(3, 31), @@ -3629,6 +3647,8 @@ static const unsigned int usb1_mux[] = { USB1_PWEN_MARK, USB1_OVC_MARK, }; + +#ifdef CONFIG_PINCTRL_PFC_FULL /* - VIN0 ------------------------------------------------------------------- */ static const unsigned int vin0_data_pins[] = { /* B */ @@ -3761,8 +3781,10 @@ static const unsigned int vin1_clk_pins[] = { static const unsigned int vin1_clk_mux[] = { VI1_CLK_MARK, }; +#endif static const struct sh_pfc_pin_group pinmux_groups[] = { +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(audio_clka), SH_PFC_PIN_GROUP(audio_clka_b), SH_PFC_PIN_GROUP(audio_clka_c), @@ -3776,12 +3798,14 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(audio_clkout), SH_PFC_PIN_GROUP(audio_clkout_b), SH_PFC_PIN_GROUP(audio_clkout_c), +#endif SH_PFC_PIN_GROUP(avb_link), SH_PFC_PIN_GROUP(avb_magic), SH_PFC_PIN_GROUP(avb_phy_int), SH_PFC_PIN_GROUP(avb_mdio), SH_PFC_PIN_GROUP(avb_mii), SH_PFC_PIN_GROUP(avb_gmii), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(can0_data), SH_PFC_PIN_GROUP(can0_data_b), SH_PFC_PIN_GROUP(can0_data_c), @@ -3812,6 +3836,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(du1_oddf), SH_PFC_PIN_GROUP(du1_cde), SH_PFC_PIN_GROUP(du1_disp), +#endif SH_PFC_PIN_GROUP(eth_link), SH_PFC_PIN_GROUP(eth_magic), SH_PFC_PIN_GROUP(eth_mdio), @@ -3862,6 +3887,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(i2c5_b), SH_PFC_PIN_GROUP(i2c5_c), SH_PFC_PIN_GROUP(i2c5_d), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(intc_irq0), SH_PFC_PIN_GROUP(intc_irq1), SH_PFC_PIN_GROUP(intc_irq2), @@ -3872,10 +3898,12 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(intc_irq7), SH_PFC_PIN_GROUP(intc_irq8), SH_PFC_PIN_GROUP(intc_irq9), +#endif BUS_DATA_PIN_GROUP(mmc_data, 1), BUS_DATA_PIN_GROUP(mmc_data, 4), BUS_DATA_PIN_GROUP(mmc_data, 8), SH_PFC_PIN_GROUP(mmc_ctrl), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(msiof0_clk), SH_PFC_PIN_GROUP(msiof0_sync), SH_PFC_PIN_GROUP(msiof0_ss1), @@ -3923,6 +3951,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(pwm5_c), SH_PFC_PIN_GROUP(pwm6), SH_PFC_PIN_GROUP(pwm6_b), +#endif SH_PFC_PIN_GROUP(qspi_ctrl), BUS_DATA_PIN_GROUP(qspi_data, 2), BUS_DATA_PIN_GROUP(qspi_data, 4), @@ -4006,6 +4035,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(sdhi2_ctrl), SH_PFC_PIN_GROUP(sdhi2_cd), SH_PFC_PIN_GROUP(sdhi2_wp), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(ssi0_data), SH_PFC_PIN_GROUP(ssi0129_ctrl), SH_PFC_PIN_GROUP(ssi1_data), @@ -4040,6 +4070,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(ssi9_ctrl), SH_PFC_PIN_GROUP(ssi9_data_b), SH_PFC_PIN_GROUP(ssi9_ctrl_b), +#endif SH_PFC_PIN_GROUP(tpu_to0), SH_PFC_PIN_GROUP(tpu_to0_b), SH_PFC_PIN_GROUP(tpu_to0_c), @@ -4054,6 +4085,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(tpu_to3_c), SH_PFC_PIN_GROUP(usb0), SH_PFC_PIN_GROUP(usb1), +#ifdef CONFIG_PINCTRL_PFC_FULL BUS_DATA_PIN_GROUP(vin0_data, 24), BUS_DATA_PIN_GROUP(vin0_data, 20), SH_PFC_PIN_GROUP(vin0_data18), @@ -4072,8 +4104,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(vin1_field), SH_PFC_PIN_GROUP(vin1_clkenb), SH_PFC_PIN_GROUP(vin1_clk), +#endif }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const audio_clk_groups[] = { "audio_clka", "audio_clka_b", @@ -4089,6 +4123,7 @@ static const char * const audio_clk_groups[] = { "audio_clkout_b", "audio_clkout_c", }; +#endif static const char * const avb_groups[] = { "avb_link", @@ -4099,6 +4134,7 @@ static const char * const avb_groups[] = { "avb_gmii", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const can0_groups[] = { "can0_data", "can0_data_b", @@ -4163,6 +4199,7 @@ static const char * const du1_groups[] = { "du1_cde", "du1_disp", }; +#endif static const char * const eth_groups[] = { "eth_link", @@ -4244,6 +4281,7 @@ static const char * const i2c5_groups[] = { "i2c5_d", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const intc_groups[] = { "intc_irq0", "intc_irq1", @@ -4256,6 +4294,7 @@ static const char * const intc_groups[] = { "intc_irq8", "intc_irq9", }; +#endif static const char * const mmc_groups[] = { "mmc_data1", @@ -4264,6 +4303,7 @@ static const char * const mmc_groups[] = { "mmc_ctrl", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const msiof0_groups[] = { "msiof0_clk", "msiof0_sync", @@ -4340,6 +4380,7 @@ static const char * const pwm6_groups[] = { "pwm6", "pwm6_b", }; +#endif static const char * const qspi_groups[] = { "qspi_ctrl", @@ -4484,6 +4525,7 @@ static const char * const sdhi2_groups[] = { "sdhi2_wp", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const ssi_groups[] = { "ssi0_data", "ssi0129_ctrl", @@ -4520,6 +4562,7 @@ static const char * const ssi_groups[] = { "ssi9_data_b", "ssi9_ctrl_b", }; +#endif static const char * const tpu_groups[] = { "tpu_to0", @@ -4544,6 +4587,7 @@ static const char * const usb1_groups[] = { "usb1", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const vin0_groups[] = { "vin0_data24", "vin0_data20", @@ -4567,15 +4611,20 @@ static const char * const vin1_groups[] = { "vin1_clkenb", "vin1_clk", }; +#endif static const struct sh_pfc_function pinmux_functions[] = { +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(audio_clk), +#endif SH_PFC_FUNCTION(avb), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(can0), SH_PFC_FUNCTION(can1), SH_PFC_FUNCTION(can_clk), SH_PFC_FUNCTION(du0), SH_PFC_FUNCTION(du1), +#endif SH_PFC_FUNCTION(eth), SH_PFC_FUNCTION(hscif0), SH_PFC_FUNCTION(hscif1), @@ -4586,8 +4635,11 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(i2c3), SH_PFC_FUNCTION(i2c4), SH_PFC_FUNCTION(i2c5), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(intc), +#endif SH_PFC_FUNCTION(mmc), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(msiof0), SH_PFC_FUNCTION(msiof1), SH_PFC_FUNCTION(msiof2), @@ -4598,6 +4650,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(pwm4), SH_PFC_FUNCTION(pwm5), SH_PFC_FUNCTION(pwm6), +#endif SH_PFC_FUNCTION(qspi), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1), @@ -4618,12 +4671,16 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(sdhi0), SH_PFC_FUNCTION(sdhi1), SH_PFC_FUNCTION(sdhi2), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(ssi), +#endif SH_PFC_FUNCTION(tpu), SH_PFC_FUNCTION(usb0), SH_PFC_FUNCTION(usb1), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(vin0), SH_PFC_FUNCTION(vin1), +#endif }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { diff --git a/drivers/pinctrl/renesas/pfc-r8a77951.c b/drivers/pinctrl/renesas/pfc-r8a77951.c index 1cfdc335041..8ddcbfbbd64 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77951.c +++ b/drivers/pinctrl/renesas/pfc-r8a77951.c @@ -1563,6 +1563,7 @@ static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_NOGP_ALL(), }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - AUDIO CLOCK ------------------------------------------------------------ */ static const unsigned int audio_clk_a_a_pins[] = { /* CLK A */ @@ -1683,6 +1684,7 @@ static const unsigned int audio_clkout3_b_pins[] = { static const unsigned int audio_clkout3_b_mux[] = { AUDIO_CLKOUT3_B_MARK, }; +#endif /* - EtherAVB --------------------------------------------------------------- */ static const unsigned int avb_link_pins[] = { @@ -1770,6 +1772,7 @@ static const unsigned int avb_avtp_capture_b_mux[] = { AVB_AVTP_CAPTURE_B_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - CAN ------------------------------------------------------------------ */ static const unsigned int can0_data_a_pins[] = { /* TX, RX */ @@ -1824,6 +1827,7 @@ static const unsigned int canfd1_data_pins[] = { static const unsigned int canfd1_data_mux[] = { CANFD1_TX_MARK, CANFD1_RX_MARK, }; +#endif #ifdef CONFIG_PINCTRL_PFC_R8A77951 /* - DRIF0 --------------------------------------------------------------- */ @@ -2042,6 +2046,7 @@ static const unsigned int drif3_data1_b_mux[] = { }; #endif /* CONFIG_PINCTRL_PFC_R8A77951 */ +#ifdef CONFIG_PINCTRL_PFC_FULL /* - DU --------------------------------------------------------------------- */ static const unsigned int du_rgb666_pins[] = { /* R[7:2], G[7:2], B[7:2] */ @@ -2122,6 +2127,7 @@ static const unsigned int du_disp_pins[] = { static const unsigned int du_disp_mux[] = { DU_DISP_MARK, }; +#endif /* - HSCIF0 ----------------------------------------------------------------- */ static const unsigned int hscif0_data_pins[] = { @@ -2409,6 +2415,7 @@ static const unsigned int i2c6_c_mux[] = { SDA6_C_MARK, SCL6_C_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - INTC-EX ---------------------------------------------------------------- */ static const unsigned int intc_ex_irq0_pins[] = { /* IRQ0 */ @@ -2452,6 +2459,7 @@ static const unsigned int intc_ex_irq5_pins[] = { static const unsigned int intc_ex_irq5_mux[] = { IRQ5_MARK, }; +#endif #ifdef CONFIG_PINCTRL_PFC_R8A77951 /* - MLB+ ------------------------------------------------------------------- */ @@ -2463,6 +2471,7 @@ static const unsigned int mlb_3pin_mux[] = { }; #endif /* CONFIG_PINCTRL_PFC_R8A77951 */ +#ifdef CONFIG_PINCTRL_PFC_FULL /* - MSIOF0 ----------------------------------------------------------------- */ static const unsigned int msiof0_clk_pins[] = { /* SCK */ @@ -3259,6 +3268,7 @@ static const unsigned int pwm6_b_pins[] = { static const unsigned int pwm6_b_mux[] = { PWM6_B_MARK, }; +#endif /* - QSPI0 ------------------------------------------------------------------ */ static const unsigned int qspi0_ctrl_pins[] = { @@ -3687,6 +3697,7 @@ static const unsigned int sdhi3_ds_mux[] = { SD3_DS_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - SSI -------------------------------------------------------------------- */ static const unsigned int ssi0_data_pins[] = { /* SDATA */ @@ -3863,6 +3874,7 @@ static const unsigned int ssi9_ctrl_b_pins[] = { static const unsigned int ssi9_ctrl_b_mux[] = { SSI_SCK9_B_MARK, SSI_WS9_B_MARK, }; +#endif /* - TMU -------------------------------------------------------------------- */ static const unsigned int tmu_tclk1_a_pins[] = { @@ -3966,6 +3978,7 @@ static const unsigned int usb30_mux[] = { USB30_PWEN_MARK, USB30_OVC_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - VIN4 ------------------------------------------------------------------- */ static const unsigned int vin4_data18_a_pins[] = { RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), @@ -4145,6 +4158,7 @@ static const unsigned int vin5_clk_mux[] = { /* CLK */ VI5_CLK_MARK, }; +#endif static const struct { struct sh_pfc_pin_group common[328]; @@ -4153,6 +4167,7 @@ static const struct { #endif } pinmux_groups = { .common = { +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(audio_clk_a_a), SH_PFC_PIN_GROUP(audio_clk_a_b), SH_PFC_PIN_GROUP(audio_clk_a_c), @@ -4170,6 +4185,7 @@ static const struct { SH_PFC_PIN_GROUP(audio_clkout2_b), SH_PFC_PIN_GROUP(audio_clkout3_a), SH_PFC_PIN_GROUP(audio_clkout3_b), +#endif SH_PFC_PIN_GROUP(avb_link), SH_PFC_PIN_GROUP(avb_magic), SH_PFC_PIN_GROUP(avb_phy_int), @@ -4181,6 +4197,7 @@ static const struct { SH_PFC_PIN_GROUP(avb_avtp_capture_a), SH_PFC_PIN_GROUP(avb_avtp_match_b), SH_PFC_PIN_GROUP(avb_avtp_capture_b), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(can0_data_a), SH_PFC_PIN_GROUP(can0_data_b), SH_PFC_PIN_GROUP(can1_data), @@ -4196,6 +4213,7 @@ static const struct { SH_PFC_PIN_GROUP(du_oddf), SH_PFC_PIN_GROUP(du_cde), SH_PFC_PIN_GROUP(du_disp), +#endif SH_PFC_PIN_GROUP(hscif0_data), SH_PFC_PIN_GROUP(hscif0_clk), SH_PFC_PIN_GROUP(hscif0_ctrl), @@ -4234,6 +4252,7 @@ static const struct { SH_PFC_PIN_GROUP(i2c6_a), SH_PFC_PIN_GROUP(i2c6_b), SH_PFC_PIN_GROUP(i2c6_c), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(intc_ex_irq0), SH_PFC_PIN_GROUP(intc_ex_irq1), SH_PFC_PIN_GROUP(intc_ex_irq2), @@ -4352,6 +4371,7 @@ static const struct { SH_PFC_PIN_GROUP(pwm5_b), SH_PFC_PIN_GROUP(pwm6_a), SH_PFC_PIN_GROUP(pwm6_b), +#endif SH_PFC_PIN_GROUP(qspi0_ctrl), BUS_DATA_PIN_GROUP(qspi0_data, 2), BUS_DATA_PIN_GROUP(qspi0_data, 4), @@ -4415,6 +4435,7 @@ static const struct { SH_PFC_PIN_GROUP(sdhi3_cd), SH_PFC_PIN_GROUP(sdhi3_wp), SH_PFC_PIN_GROUP(sdhi3_ds), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(ssi0_data), SH_PFC_PIN_GROUP(ssi01239_ctrl), SH_PFC_PIN_GROUP(ssi1_data_a), @@ -4440,6 +4461,7 @@ static const struct { SH_PFC_PIN_GROUP(ssi9_data_b), SH_PFC_PIN_GROUP(ssi9_ctrl_a), SH_PFC_PIN_GROUP(ssi9_ctrl_b), +#endif SH_PFC_PIN_GROUP(tmu_tclk1_a), SH_PFC_PIN_GROUP(tmu_tclk1_b), SH_PFC_PIN_GROUP(tmu_tclk2_a), @@ -4453,6 +4475,7 @@ static const struct { SH_PFC_PIN_GROUP(usb2), SH_PFC_PIN_GROUP(usb2_ch3), SH_PFC_PIN_GROUP(usb30), +#ifdef CONFIG_PINCTRL_PFC_FULL BUS_DATA_PIN_GROUP(vin4_data, 8, _a), BUS_DATA_PIN_GROUP(vin4_data, 10, _a), BUS_DATA_PIN_GROUP(vin4_data, 12, _a), @@ -4481,6 +4504,7 @@ static const struct { SH_PFC_PIN_GROUP(vin5_field), SH_PFC_PIN_GROUP(vin5_clkenb), SH_PFC_PIN_GROUP(vin5_clk), +#endif }, #ifdef CONFIG_PINCTRL_PFC_R8A77951 .automotive = { @@ -4519,6 +4543,7 @@ static const struct { #endif /* CONFIG_PINCTRL_PFC_R8A77951 */ }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const audio_clk_groups[] = { "audio_clk_a_a", "audio_clk_a_b", @@ -4538,6 +4563,7 @@ static const char * const audio_clk_groups[] = { "audio_clkout3_a", "audio_clkout3_b", }; +#endif static const char * const avb_groups[] = { "avb_link", @@ -4553,6 +4579,7 @@ static const char * const avb_groups[] = { "avb_avtp_capture_b", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const can0_groups[] = { "can0_data_a", "can0_data_b", @@ -4574,6 +4601,7 @@ static const char * const canfd0_groups[] = { static const char * const canfd1_groups[] = { "canfd1_data", }; +#endif #ifdef CONFIG_PINCTRL_PFC_R8A77951 static const char * const drif0_groups[] = { @@ -4619,6 +4647,7 @@ static const char * const drif3_groups[] = { }; #endif /* CONFIG_PINCTRL_PFC_R8A77951 */ +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const du_groups[] = { "du_rgb666", "du_rgb888", @@ -4629,6 +4658,7 @@ static const char * const du_groups[] = { "du_cde", "du_disp", }; +#endif static const char * const hscif0_groups[] = { "hscif0_data", @@ -4701,6 +4731,7 @@ static const char * const i2c6_groups[] = { "i2c6_c", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const intc_ex_groups[] = { "intc_ex_irq0", "intc_ex_irq1", @@ -4709,6 +4740,7 @@ static const char * const intc_ex_groups[] = { "intc_ex_irq4", "intc_ex_irq5", }; +#endif #ifdef CONFIG_PINCTRL_PFC_R8A77951 static const char * const mlb_3pin_groups[] = { @@ -4716,6 +4748,7 @@ static const char * const mlb_3pin_groups[] = { }; #endif /* CONFIG_PINCTRL_PFC_R8A77951 */ +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const msiof0_groups[] = { "msiof0_clk", "msiof0_sync", @@ -4860,6 +4893,7 @@ static const char * const pwm6_groups[] = { "pwm6_a", "pwm6_b", }; +#endif static const char * const qspi0_groups[] = { "qspi0_ctrl", @@ -4966,6 +5000,7 @@ static const char * const sdhi3_groups[] = { "sdhi3_ds", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const ssi_groups[] = { "ssi0_data", "ssi01239_ctrl", @@ -4993,6 +5028,7 @@ static const char * const ssi_groups[] = { "ssi9_ctrl_a", "ssi9_ctrl_b", }; +#endif static const char * const tmu_groups[] = { "tmu_tclk1_a", @@ -5028,6 +5064,7 @@ static const char * const usb30_groups[] = { "usb30", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const vin4_groups[] = { "vin4_data8_a", "vin4_data10_a", @@ -5061,6 +5098,7 @@ static const char * const vin5_groups[] = { "vin5_clkenb", "vin5_clk", }; +#endif static const struct { struct sh_pfc_function common[55]; @@ -5069,14 +5107,18 @@ static const struct { #endif } pinmux_functions = { .common = { +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(audio_clk), +#endif SH_PFC_FUNCTION(avb), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(can0), SH_PFC_FUNCTION(can1), SH_PFC_FUNCTION(can_clk), SH_PFC_FUNCTION(canfd0), SH_PFC_FUNCTION(canfd1), SH_PFC_FUNCTION(du), +#endif SH_PFC_FUNCTION(hscif0), SH_PFC_FUNCTION(hscif1), SH_PFC_FUNCTION(hscif2), @@ -5088,6 +5130,7 @@ static const struct { SH_PFC_FUNCTION(i2c3), SH_PFC_FUNCTION(i2c5), SH_PFC_FUNCTION(i2c6), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(intc_ex), SH_PFC_FUNCTION(msiof0), SH_PFC_FUNCTION(msiof1), @@ -5100,6 +5143,7 @@ static const struct { SH_PFC_FUNCTION(pwm4), SH_PFC_FUNCTION(pwm5), SH_PFC_FUNCTION(pwm6), +#endif SH_PFC_FUNCTION(qspi0), SH_PFC_FUNCTION(qspi1), SH_PFC_FUNCTION(sata0), @@ -5114,7 +5158,9 @@ static const struct { SH_PFC_FUNCTION(sdhi1), SH_PFC_FUNCTION(sdhi2), SH_PFC_FUNCTION(sdhi3), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(ssi), +#endif SH_PFC_FUNCTION(tmu), SH_PFC_FUNCTION(tpu), SH_PFC_FUNCTION(usb0), @@ -5122,8 +5168,10 @@ static const struct { SH_PFC_FUNCTION(usb2), SH_PFC_FUNCTION(usb2_ch3), SH_PFC_FUNCTION(usb30), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(vin4), SH_PFC_FUNCTION(vin5), +#endif }, #ifdef CONFIG_PINCTRL_PFC_R8A77951 .automotive = { diff --git a/drivers/pinctrl/renesas/pfc-r8a7796.c b/drivers/pinctrl/renesas/pfc-r8a7796.c index a289397fb8f..7bc9fb709ea 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7796.c +++ b/drivers/pinctrl/renesas/pfc-r8a7796.c @@ -1568,6 +1568,7 @@ static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_NOGP_ALL(), }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - AUDIO CLOCK ------------------------------------------------------------ */ static const unsigned int audio_clk_a_a_pins[] = { /* CLK A */ @@ -1689,6 +1690,7 @@ static const unsigned int audio_clkout3_b_pins[] = { static const unsigned int audio_clkout3_b_mux[] = { AUDIO_CLKOUT3_B_MARK, }; +#endif /* - EtherAVB --------------------------------------------------------------- */ static const unsigned int avb_link_pins[] = { @@ -1776,6 +1778,7 @@ static const unsigned int avb_avtp_capture_b_mux[] = { AVB_AVTP_CAPTURE_B_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - CAN ------------------------------------------------------------------ */ static const unsigned int can0_data_a_pins[] = { /* TX, RX */ @@ -1830,6 +1833,7 @@ static const unsigned int canfd1_data_pins[] = { static const unsigned int canfd1_data_mux[] = { CANFD1_TX_MARK, CANFD1_RX_MARK, }; +#endif #if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961) /* - DRIF0 --------------------------------------------------------------- */ @@ -2048,6 +2052,7 @@ static const unsigned int drif3_data1_b_mux[] = { }; #endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */ +#ifdef CONFIG_PINCTRL_PFC_FULL /* - DU --------------------------------------------------------------------- */ static const unsigned int du_rgb666_pins[] = { /* R[7:2], G[7:2], B[7:2] */ @@ -2128,6 +2133,7 @@ static const unsigned int du_disp_pins[] = { static const unsigned int du_disp_mux[] = { DU_DISP_MARK, }; +#endif /* - HSCIF0 ----------------------------------------------------------------- */ static const unsigned int hscif0_data_pins[] = { @@ -2415,6 +2421,7 @@ static const unsigned int i2c6_c_mux[] = { SDA6_C_MARK, SCL6_C_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - INTC-EX ---------------------------------------------------------------- */ static const unsigned int intc_ex_irq0_pins[] = { /* IRQ0 */ @@ -2458,6 +2465,7 @@ static const unsigned int intc_ex_irq5_pins[] = { static const unsigned int intc_ex_irq5_mux[] = { IRQ5_MARK, }; +#endif #if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961) /* - MLB+ ------------------------------------------------------------------- */ @@ -2469,6 +2477,7 @@ static const unsigned int mlb_3pin_mux[] = { }; #endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */ +#ifdef CONFIG_PINCTRL_PFC_FULL /* - MSIOF0 ----------------------------------------------------------------- */ static const unsigned int msiof0_clk_pins[] = { /* SCK */ @@ -3266,6 +3275,7 @@ static const unsigned int pwm6_b_pins[] = { static const unsigned int pwm6_b_mux[] = { PWM6_B_MARK, }; +#endif /* - QSPI0 ------------------------------------------------------------------ */ static const unsigned int qspi0_ctrl_pins[] = { @@ -3679,6 +3689,7 @@ static const unsigned int sdhi3_ds_mux[] = { SD3_DS_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - SSI -------------------------------------------------------------------- */ static const unsigned int ssi0_data_pins[] = { /* SDATA */ @@ -3855,6 +3866,7 @@ static const unsigned int ssi9_ctrl_b_pins[] = { static const unsigned int ssi9_ctrl_b_mux[] = { SSI_SCK9_B_MARK, SSI_WS9_B_MARK, }; +#endif /* - TMU -------------------------------------------------------------------- */ static const unsigned int tmu_tclk1_a_pins[] = { @@ -3942,6 +3954,7 @@ static const unsigned int usb30_mux[] = { USB30_PWEN_MARK, USB30_OVC_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - VIN4 ------------------------------------------------------------------- */ static const unsigned int vin4_data18_a_pins[] = { RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), @@ -4121,6 +4134,7 @@ static const unsigned int vin5_clk_mux[] = { /* CLK */ VI5_CLK_MARK, }; +#endif static const struct { struct sh_pfc_pin_group common[324]; @@ -4129,6 +4143,7 @@ static const struct { #endif } pinmux_groups = { .common = { +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(audio_clk_a_a), SH_PFC_PIN_GROUP(audio_clk_a_b), SH_PFC_PIN_GROUP(audio_clk_a_c), @@ -4146,6 +4161,7 @@ static const struct { SH_PFC_PIN_GROUP(audio_clkout2_b), SH_PFC_PIN_GROUP(audio_clkout3_a), SH_PFC_PIN_GROUP(audio_clkout3_b), +#endif SH_PFC_PIN_GROUP(avb_link), SH_PFC_PIN_GROUP(avb_magic), SH_PFC_PIN_GROUP(avb_phy_int), @@ -4157,6 +4173,7 @@ static const struct { SH_PFC_PIN_GROUP(avb_avtp_capture_a), SH_PFC_PIN_GROUP(avb_avtp_match_b), SH_PFC_PIN_GROUP(avb_avtp_capture_b), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(can0_data_a), SH_PFC_PIN_GROUP(can0_data_b), SH_PFC_PIN_GROUP(can1_data), @@ -4172,6 +4189,7 @@ static const struct { SH_PFC_PIN_GROUP(du_oddf), SH_PFC_PIN_GROUP(du_cde), SH_PFC_PIN_GROUP(du_disp), +#endif SH_PFC_PIN_GROUP(hscif0_data), SH_PFC_PIN_GROUP(hscif0_clk), SH_PFC_PIN_GROUP(hscif0_ctrl), @@ -4210,6 +4228,7 @@ static const struct { SH_PFC_PIN_GROUP(i2c6_a), SH_PFC_PIN_GROUP(i2c6_b), SH_PFC_PIN_GROUP(i2c6_c), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(intc_ex_irq0), SH_PFC_PIN_GROUP(intc_ex_irq1), SH_PFC_PIN_GROUP(intc_ex_irq2), @@ -4328,6 +4347,7 @@ static const struct { SH_PFC_PIN_GROUP(pwm5_b), SH_PFC_PIN_GROUP(pwm6_a), SH_PFC_PIN_GROUP(pwm6_b), +#endif SH_PFC_PIN_GROUP(qspi0_ctrl), BUS_DATA_PIN_GROUP(qspi0_data, 2), BUS_DATA_PIN_GROUP(qspi0_data, 4), @@ -4389,6 +4409,7 @@ static const struct { SH_PFC_PIN_GROUP(sdhi3_cd), SH_PFC_PIN_GROUP(sdhi3_wp), SH_PFC_PIN_GROUP(sdhi3_ds), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(ssi0_data), SH_PFC_PIN_GROUP(ssi01239_ctrl), SH_PFC_PIN_GROUP(ssi1_data_a), @@ -4414,6 +4435,7 @@ static const struct { SH_PFC_PIN_GROUP(ssi9_data_b), SH_PFC_PIN_GROUP(ssi9_ctrl_a), SH_PFC_PIN_GROUP(ssi9_ctrl_b), +#endif SH_PFC_PIN_GROUP(tmu_tclk1_a), SH_PFC_PIN_GROUP(tmu_tclk1_b), SH_PFC_PIN_GROUP(tmu_tclk2_a), @@ -4425,6 +4447,7 @@ static const struct { SH_PFC_PIN_GROUP(usb0), SH_PFC_PIN_GROUP(usb1), SH_PFC_PIN_GROUP(usb30), +#ifdef CONFIG_PINCTRL_PFC_FULL BUS_DATA_PIN_GROUP(vin4_data, 8, _a), BUS_DATA_PIN_GROUP(vin4_data, 10, _a), BUS_DATA_PIN_GROUP(vin4_data, 12, _a), @@ -4453,6 +4476,7 @@ static const struct { SH_PFC_PIN_GROUP(vin5_field), SH_PFC_PIN_GROUP(vin5_clkenb), SH_PFC_PIN_GROUP(vin5_clk), +#endif }, #if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961) .automotive = { @@ -4491,6 +4515,7 @@ static const struct { #endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */ }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const audio_clk_groups[] = { "audio_clk_a_a", "audio_clk_a_b", @@ -4510,6 +4535,7 @@ static const char * const audio_clk_groups[] = { "audio_clkout3_a", "audio_clkout3_b", }; +#endif static const char * const avb_groups[] = { "avb_link", @@ -4525,6 +4551,7 @@ static const char * const avb_groups[] = { "avb_avtp_capture_b", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const can0_groups[] = { "can0_data_a", "can0_data_b", @@ -4546,6 +4573,7 @@ static const char * const canfd0_groups[] = { static const char * const canfd1_groups[] = { "canfd1_data", }; +#endif #if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961) static const char * const drif0_groups[] = { @@ -4591,6 +4619,7 @@ static const char * const drif3_groups[] = { }; #endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */ +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const du_groups[] = { "du_rgb666", "du_rgb888", @@ -4601,6 +4630,7 @@ static const char * const du_groups[] = { "du_cde", "du_disp", }; +#endif static const char * const hscif0_groups[] = { "hscif0_data", @@ -4673,6 +4703,7 @@ static const char * const i2c6_groups[] = { "i2c6_c", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const intc_ex_groups[] = { "intc_ex_irq0", "intc_ex_irq1", @@ -4681,6 +4712,7 @@ static const char * const intc_ex_groups[] = { "intc_ex_irq4", "intc_ex_irq5", }; +#endif #if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961) static const char * const mlb_3pin_groups[] = { @@ -4688,6 +4720,7 @@ static const char * const mlb_3pin_groups[] = { }; #endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */ +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const msiof0_groups[] = { "msiof0_clk", "msiof0_sync", @@ -4832,6 +4865,7 @@ static const char * const pwm6_groups[] = { "pwm6_a", "pwm6_b", }; +#endif static const char * const qspi0_groups[] = { "qspi0_ctrl", @@ -4933,6 +4967,7 @@ static const char * const sdhi3_groups[] = { "sdhi3_ds", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const ssi_groups[] = { "ssi0_data", "ssi01239_ctrl", @@ -4960,6 +4995,7 @@ static const char * const ssi_groups[] = { "ssi9_ctrl_a", "ssi9_ctrl_b", }; +#endif static const char * const tmu_groups[] = { "tmu_tclk1_a", @@ -4987,6 +5023,7 @@ static const char * const usb30_groups[] = { "usb30", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const vin4_groups[] = { "vin4_data8_a", "vin4_data10_a", @@ -5020,6 +5057,7 @@ static const char * const vin5_groups[] = { "vin5_clkenb", "vin5_clk", }; +#endif static const struct { struct sh_pfc_function common[52]; @@ -5028,14 +5066,18 @@ static const struct { #endif } pinmux_functions = { .common = { +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(audio_clk), +#endif SH_PFC_FUNCTION(avb), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(can0), SH_PFC_FUNCTION(can1), SH_PFC_FUNCTION(can_clk), SH_PFC_FUNCTION(canfd0), SH_PFC_FUNCTION(canfd1), SH_PFC_FUNCTION(du), +#endif SH_PFC_FUNCTION(hscif0), SH_PFC_FUNCTION(hscif1), SH_PFC_FUNCTION(hscif2), @@ -5047,6 +5089,7 @@ static const struct { SH_PFC_FUNCTION(i2c3), SH_PFC_FUNCTION(i2c5), SH_PFC_FUNCTION(i2c6), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(intc_ex), SH_PFC_FUNCTION(msiof0), SH_PFC_FUNCTION(msiof1), @@ -5059,6 +5102,7 @@ static const struct { SH_PFC_FUNCTION(pwm4), SH_PFC_FUNCTION(pwm5), SH_PFC_FUNCTION(pwm6), +#endif SH_PFC_FUNCTION(qspi0), SH_PFC_FUNCTION(qspi1), SH_PFC_FUNCTION(scif0), @@ -5072,14 +5116,18 @@ static const struct { SH_PFC_FUNCTION(sdhi1), SH_PFC_FUNCTION(sdhi2), SH_PFC_FUNCTION(sdhi3), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(ssi), +#endif SH_PFC_FUNCTION(tmu), SH_PFC_FUNCTION(tpu), SH_PFC_FUNCTION(usb0), SH_PFC_FUNCTION(usb1), SH_PFC_FUNCTION(usb30), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(vin4), SH_PFC_FUNCTION(vin5), +#endif }, #if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961) .automotive = { diff --git a/drivers/pinctrl/renesas/pfc-r8a77965.c b/drivers/pinctrl/renesas/pfc-r8a77965.c index 2852ae64ec0..97fde005de6 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77965.c +++ b/drivers/pinctrl/renesas/pfc-r8a77965.c @@ -1572,6 +1572,7 @@ static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_NOGP_ALL(), }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - AUDIO CLOCK ------------------------------------------------------------ */ static const unsigned int audio_clk_a_a_pins[] = { /* CLK A */ @@ -1693,6 +1694,7 @@ static const unsigned int audio_clkout3_b_pins[] = { static const unsigned int audio_clkout3_b_mux[] = { AUDIO_CLKOUT3_B_MARK, }; +#endif /* - EtherAVB --------------------------------------------------------------- */ static const unsigned int avb_link_pins[] = { @@ -1780,6 +1782,7 @@ static const unsigned int avb_avtp_capture_b_mux[] = { AVB_AVTP_CAPTURE_B_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - CAN ------------------------------------------------------------------ */ static const unsigned int can0_data_a_pins[] = { /* TX, RX */ @@ -1845,6 +1848,7 @@ static const unsigned int canfd1_data_pins[] = { static const unsigned int canfd1_data_mux[] = { CANFD1_TX_MARK, CANFD1_RX_MARK, }; +#endif #ifdef CONFIG_PINCTRL_PFC_R8A77965 /* - DRIF0 --------------------------------------------------------------- */ @@ -2122,6 +2126,7 @@ static const unsigned int drif3_data1_b_mux[] = { }; #endif /* CONFIG_PINCTRL_PFC_R8A77965 */ +#ifdef CONFIG_PINCTRL_PFC_FULL /* - DU --------------------------------------------------------------------- */ static const unsigned int du_rgb666_pins[] = { /* R[7:2], G[7:2], B[7:2] */ @@ -2217,6 +2222,7 @@ static const unsigned int du_disp_pins[] = { static const unsigned int du_disp_mux[] = { DU_DISP_MARK, }; +#endif /* - HSCIF0 ----------------------------------------------------------------- */ static const unsigned int hscif0_data_pins[] = { @@ -2566,6 +2572,7 @@ static const unsigned int i2c6_c_mux[] = { SDA6_C_MARK, SCL6_C_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - INTC-EX ---------------------------------------------------------------- */ static const unsigned int intc_ex_irq0_pins[] = { /* IRQ0 */ @@ -2609,6 +2616,7 @@ static const unsigned int intc_ex_irq5_pins[] = { static const unsigned int intc_ex_irq5_mux[] = { IRQ5_MARK, }; +#endif #ifdef CONFIG_PINCTRL_PFC_R8A77965 /* - MLB+ ------------------------------------------------------------------- */ @@ -2620,6 +2628,7 @@ static const unsigned int mlb_3pin_mux[] = { }; #endif /* CONFIG_PINCTRL_PFC_R8A77965 */ +#ifdef CONFIG_PINCTRL_PFC_FULL /* - MSIOF0 ----------------------------------------------------------------- */ static const unsigned int msiof0_clk_pins[] = { /* SCK */ @@ -3416,6 +3425,7 @@ static const unsigned int pwm6_b_pins[] = { static const unsigned int pwm6_b_mux[] = { PWM6_B_MARK, }; +#endif /* - QSPI0 ------------------------------------------------------------------ */ static const unsigned int qspi0_ctrl_pins[] = { @@ -3884,6 +3894,7 @@ static const unsigned int sdhi3_ds_mux[] = { SD3_DS_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - SSI -------------------------------------------------------------------- */ static const unsigned int ssi0_data_pins[] = { /* SDATA */ @@ -4060,6 +4071,7 @@ static const unsigned int ssi9_ctrl_b_pins[] = { static const unsigned int ssi9_ctrl_b_mux[] = { SSI_SCK9_B_MARK, SSI_WS9_B_MARK, }; +#endif /* - TMU -------------------------------------------------------------------- */ static const unsigned int tmu_tclk1_a_pins[] = { @@ -4158,6 +4170,7 @@ static const unsigned int usb30_mux[] = { USB30_PWEN_MARK, USB30_OVC_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - VIN4 ------------------------------------------------------------------- */ static const unsigned int vin4_data18_a_pins[] = { RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), @@ -4355,6 +4368,7 @@ static const unsigned int vin5_clk_pins[] = { static const unsigned int vin5_clk_mux[] = { VI5_CLK_MARK, }; +#endif static const struct { struct sh_pfc_pin_group common[326]; @@ -4363,6 +4377,7 @@ static const struct { #endif } pinmux_groups = { .common = { +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(audio_clk_a_a), SH_PFC_PIN_GROUP(audio_clk_a_b), SH_PFC_PIN_GROUP(audio_clk_a_c), @@ -4380,6 +4395,7 @@ static const struct { SH_PFC_PIN_GROUP(audio_clkout2_b), SH_PFC_PIN_GROUP(audio_clkout3_a), SH_PFC_PIN_GROUP(audio_clkout3_b), +#endif SH_PFC_PIN_GROUP(avb_link), SH_PFC_PIN_GROUP(avb_magic), SH_PFC_PIN_GROUP(avb_phy_int), @@ -4391,6 +4407,7 @@ static const struct { SH_PFC_PIN_GROUP(avb_avtp_capture_a), SH_PFC_PIN_GROUP(avb_avtp_match_b), SH_PFC_PIN_GROUP(avb_avtp_capture_b), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(can0_data_a), SH_PFC_PIN_GROUP(can0_data_b), SH_PFC_PIN_GROUP(can1_data), @@ -4406,6 +4423,7 @@ static const struct { SH_PFC_PIN_GROUP(du_oddf), SH_PFC_PIN_GROUP(du_cde), SH_PFC_PIN_GROUP(du_disp), +#endif SH_PFC_PIN_GROUP(hscif0_data), SH_PFC_PIN_GROUP(hscif0_clk), SH_PFC_PIN_GROUP(hscif0_ctrl), @@ -4444,6 +4462,7 @@ static const struct { SH_PFC_PIN_GROUP(i2c6_a), SH_PFC_PIN_GROUP(i2c6_b), SH_PFC_PIN_GROUP(i2c6_c), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(intc_ex_irq0), SH_PFC_PIN_GROUP(intc_ex_irq1), SH_PFC_PIN_GROUP(intc_ex_irq2), @@ -4562,6 +4581,7 @@ static const struct { SH_PFC_PIN_GROUP(pwm5_b), SH_PFC_PIN_GROUP(pwm6_a), SH_PFC_PIN_GROUP(pwm6_b), +#endif SH_PFC_PIN_GROUP(qspi0_ctrl), BUS_DATA_PIN_GROUP(qspi0_data, 2), BUS_DATA_PIN_GROUP(qspi0_data, 4), @@ -4625,6 +4645,7 @@ static const struct { SH_PFC_PIN_GROUP(sdhi3_cd), SH_PFC_PIN_GROUP(sdhi3_wp), SH_PFC_PIN_GROUP(sdhi3_ds), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(ssi0_data), SH_PFC_PIN_GROUP(ssi01239_ctrl), SH_PFC_PIN_GROUP(ssi1_data_a), @@ -4650,6 +4671,7 @@ static const struct { SH_PFC_PIN_GROUP(ssi9_data_b), SH_PFC_PIN_GROUP(ssi9_ctrl_a), SH_PFC_PIN_GROUP(ssi9_ctrl_b), +#endif SH_PFC_PIN_GROUP(tmu_tclk1_a), SH_PFC_PIN_GROUP(tmu_tclk1_b), SH_PFC_PIN_GROUP(tmu_tclk2_a), @@ -4661,6 +4683,7 @@ static const struct { SH_PFC_PIN_GROUP(usb0), SH_PFC_PIN_GROUP(usb1), SH_PFC_PIN_GROUP(usb30), +#ifdef CONFIG_PINCTRL_PFC_FULL BUS_DATA_PIN_GROUP(vin4_data, 8, _a), BUS_DATA_PIN_GROUP(vin4_data, 10, _a), BUS_DATA_PIN_GROUP(vin4_data, 12, _a), @@ -4689,6 +4712,7 @@ static const struct { SH_PFC_PIN_GROUP(vin5_field), SH_PFC_PIN_GROUP(vin5_clkenb), SH_PFC_PIN_GROUP(vin5_clk), +#endif }, #ifdef CONFIG_PINCTRL_PFC_R8A77965 .automotive = { @@ -4727,6 +4751,7 @@ static const struct { #endif /* CONFIG_PINCTRL_PFC_R8A77965 */ }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const audio_clk_groups[] = { "audio_clk_a_a", "audio_clk_a_b", @@ -4746,6 +4771,7 @@ static const char * const audio_clk_groups[] = { "audio_clkout3_a", "audio_clkout3_b", }; +#endif static const char * const avb_groups[] = { "avb_link", @@ -4761,6 +4787,7 @@ static const char * const avb_groups[] = { "avb_avtp_capture_b", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const can0_groups[] = { "can0_data_a", "can0_data_b", @@ -4782,6 +4809,7 @@ static const char * const canfd0_groups[] = { static const char * const canfd1_groups[] = { "canfd1_data", }; +#endif #ifdef CONFIG_PINCTRL_PFC_R8A77965 static const char * const drif0_groups[] = { @@ -4827,6 +4855,7 @@ static const char * const drif3_groups[] = { }; #endif /* CONFIG_PINCTRL_PFC_R8A77965 */ +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const du_groups[] = { "du_rgb666", "du_rgb888", @@ -4837,6 +4866,7 @@ static const char * const du_groups[] = { "du_cde", "du_disp", }; +#endif static const char * const hscif0_groups[] = { "hscif0_data", @@ -4909,6 +4939,7 @@ static const char * const i2c6_groups[] = { "i2c6_c", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const intc_ex_groups[] = { "intc_ex_irq0", "intc_ex_irq1", @@ -4917,6 +4948,7 @@ static const char * const intc_ex_groups[] = { "intc_ex_irq4", "intc_ex_irq5", }; +#endif #ifdef CONFIG_PINCTRL_PFC_R8A77965 static const char * const mlb_3pin_groups[] = { @@ -4924,6 +4956,7 @@ static const char * const mlb_3pin_groups[] = { }; #endif /* CONFIG_PINCTRL_PFC_R8A77965 */ +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const msiof0_groups[] = { "msiof0_clk", "msiof0_sync", @@ -5068,6 +5101,7 @@ static const char * const pwm6_groups[] = { "pwm6_a", "pwm6_b", }; +#endif static const char * const qspi0_groups[] = { "qspi0_ctrl", @@ -5173,6 +5207,7 @@ static const char * const sdhi3_groups[] = { "sdhi3_ds", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const ssi_groups[] = { "ssi0_data", "ssi01239_ctrl", @@ -5200,6 +5235,7 @@ static const char * const ssi_groups[] = { "ssi9_ctrl_a", "ssi9_ctrl_b", }; +#endif static const char * const tmu_groups[] = { "tmu_tclk1_a", @@ -5227,6 +5263,7 @@ static const char * const usb30_groups[] = { "usb30", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const vin4_groups[] = { "vin4_data8_a", "vin4_data10_a", @@ -5260,6 +5297,7 @@ static const char * const vin5_groups[] = { "vin5_clkenb", "vin5_clk", }; +#endif static const struct { struct sh_pfc_function common[53]; @@ -5268,14 +5306,18 @@ static const struct { #endif } pinmux_functions = { .common = { +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(audio_clk), +#endif SH_PFC_FUNCTION(avb), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(can0), SH_PFC_FUNCTION(can1), SH_PFC_FUNCTION(can_clk), SH_PFC_FUNCTION(canfd0), SH_PFC_FUNCTION(canfd1), SH_PFC_FUNCTION(du), +#endif SH_PFC_FUNCTION(hscif0), SH_PFC_FUNCTION(hscif1), SH_PFC_FUNCTION(hscif2), @@ -5287,6 +5329,7 @@ static const struct { SH_PFC_FUNCTION(i2c3), SH_PFC_FUNCTION(i2c5), SH_PFC_FUNCTION(i2c6), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(intc_ex), SH_PFC_FUNCTION(msiof0), SH_PFC_FUNCTION(msiof1), @@ -5299,6 +5342,7 @@ static const struct { SH_PFC_FUNCTION(pwm4), SH_PFC_FUNCTION(pwm5), SH_PFC_FUNCTION(pwm6), +#endif SH_PFC_FUNCTION(qspi0), SH_PFC_FUNCTION(qspi1), SH_PFC_FUNCTION(sata0), @@ -5313,14 +5357,18 @@ static const struct { SH_PFC_FUNCTION(sdhi1), SH_PFC_FUNCTION(sdhi2), SH_PFC_FUNCTION(sdhi3), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(ssi), +#endif SH_PFC_FUNCTION(tmu), SH_PFC_FUNCTION(tpu), SH_PFC_FUNCTION(usb0), SH_PFC_FUNCTION(usb1), SH_PFC_FUNCTION(usb30), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(vin4), SH_PFC_FUNCTION(vin5), +#endif }, #ifdef CONFIG_PINCTRL_PFC_R8A77965 .automotive = { diff --git a/drivers/pinctrl/renesas/pfc-r8a77970.c b/drivers/pinctrl/renesas/pfc-r8a77970.c index 00ebbbc7120..3a0a310c5fe 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77970.c +++ b/drivers/pinctrl/renesas/pfc-r8a77970.c @@ -817,6 +817,7 @@ static const unsigned int avb0_avtp_match_mux[] = { AVB0_AVTP_MATCH_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - CANFD Clock ------------------------------------------------------------ */ static const unsigned int canfd_clk_a_pins[] = { /* CANFD_CLK */ @@ -911,6 +912,7 @@ static const unsigned int du_disp_pins[] = { static const unsigned int du_disp_mux[] = { DU_DISP_MARK, }; +#endif /* - HSCIF0 ----------------------------------------------------------------- */ static const unsigned int hscif0_data_pins[] = { @@ -1056,6 +1058,7 @@ static const unsigned int i2c4_mux[] = { SDA4_MARK, SCL4_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - INTC-EX ---------------------------------------------------------------- */ static const unsigned int intc_ex_irq0_pins[] = { /* IRQ0 */ @@ -1099,6 +1102,7 @@ static const unsigned int intc_ex_irq5_pins[] = { static const unsigned int intc_ex_irq5_mux[] = { IRQ5_MARK, }; +#endif /* - MMC -------------------------------------------------------------------- */ static const unsigned int mmc_data_pins[] = { @@ -1122,6 +1126,7 @@ static const unsigned int mmc_ctrl_mux[] = { MMC_CLK_MARK, MMC_CMD_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - MSIOF0 ----------------------------------------------------------------- */ static const unsigned int msiof0_clk_pins[] = { /* SCK */ @@ -1367,6 +1372,7 @@ static const unsigned int pwm4_b_pins[] = { static const unsigned int pwm4_b_mux[] = { PWM4_B_MARK, }; +#endif /* - QSPI0 ------------------------------------------------------------------ */ static const unsigned int qspi0_ctrl_pins[] = { @@ -1583,6 +1589,7 @@ static const unsigned int tmu_tclk2_b_mux[] = { TCLK2_B_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - VIN0 ------------------------------------------------------------------- */ static const unsigned int vin0_data_pins[] = { RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), @@ -1674,6 +1681,7 @@ static const unsigned int vin1_clk_mux[] = { /* CLK */ VI1_CLK_MARK, }; +#endif static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(avb0_link), @@ -1685,6 +1693,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(avb0_avtp_pps), SH_PFC_PIN_GROUP(avb0_avtp_capture), SH_PFC_PIN_GROUP(avb0_avtp_match), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(canfd_clk_a), SH_PFC_PIN_GROUP(canfd_clk_b), SH_PFC_PIN_GROUP(canfd0_data_a), @@ -1696,6 +1705,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(du_oddf), SH_PFC_PIN_GROUP(du_cde), SH_PFC_PIN_GROUP(du_disp), +#endif SH_PFC_PIN_GROUP(hscif0_data), SH_PFC_PIN_GROUP(hscif0_clk), SH_PFC_PIN_GROUP(hscif0_ctrl), @@ -1714,16 +1724,19 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(i2c3_a), SH_PFC_PIN_GROUP(i2c3_b), SH_PFC_PIN_GROUP(i2c4), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(intc_ex_irq0), SH_PFC_PIN_GROUP(intc_ex_irq1), SH_PFC_PIN_GROUP(intc_ex_irq2), SH_PFC_PIN_GROUP(intc_ex_irq3), SH_PFC_PIN_GROUP(intc_ex_irq4), SH_PFC_PIN_GROUP(intc_ex_irq5), +#endif BUS_DATA_PIN_GROUP(mmc_data, 1), BUS_DATA_PIN_GROUP(mmc_data, 4), BUS_DATA_PIN_GROUP(mmc_data, 8), SH_PFC_PIN_GROUP(mmc_ctrl), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(msiof0_clk), SH_PFC_PIN_GROUP(msiof0_sync), SH_PFC_PIN_GROUP(msiof0_ss1), @@ -1758,6 +1771,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(pwm3_b), SH_PFC_PIN_GROUP(pwm4_a), SH_PFC_PIN_GROUP(pwm4_b), +#endif SH_PFC_PIN_GROUP(qspi0_ctrl), SH_PFC_PIN_GROUP_SUBSET(qspi0_data2, rpc_data, 0, 2), SH_PFC_PIN_GROUP_SUBSET(qspi0_data4, rpc_data, 0, 4), @@ -1790,6 +1804,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(tmu_tclk1_b), SH_PFC_PIN_GROUP(tmu_tclk2_a), SH_PFC_PIN_GROUP(tmu_tclk2_b), +#ifdef CONFIG_PINCTRL_PFC_FULL BUS_DATA_PIN_GROUP(vin0_data, 8), BUS_DATA_PIN_GROUP(vin0_data, 10), BUS_DATA_PIN_GROUP(vin0_data, 12), @@ -1804,6 +1819,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(vin1_field), SH_PFC_PIN_GROUP(vin1_clkenb), SH_PFC_PIN_GROUP(vin1_clk), +#endif }; static const char * const avb0_groups[] = { @@ -1818,6 +1834,7 @@ static const char * const avb0_groups[] = { "avb0_avtp_match", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const canfd_clk_groups[] = { "canfd_clk_a", "canfd_clk_b", @@ -1840,6 +1857,7 @@ static const char * const du_groups[] = { "du_cde", "du_disp", }; +#endif static const char * const hscif0_groups[] = { "hscif0_data", @@ -1886,6 +1904,7 @@ static const char * const i2c4_groups[] = { "i2c4", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const intc_ex_groups[] = { "intc_ex_irq0", "intc_ex_irq1", @@ -1894,6 +1913,7 @@ static const char * const intc_ex_groups[] = { "intc_ex_irq4", "intc_ex_irq5", }; +#endif static const char * const mmc_groups[] = { "mmc_data1", @@ -1902,6 +1922,7 @@ static const char * const mmc_groups[] = { "mmc_ctrl", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const msiof0_groups[] = { "msiof0_clk", "msiof0_sync", @@ -1962,6 +1983,7 @@ static const char * const pwm4_groups[] = { "pwm4_a", "pwm4_b", }; +#endif static const char * const qspi0_groups[] = { "qspi0_ctrl", @@ -2022,6 +2044,7 @@ static const char * const tmu_groups[] = { "tmu_tclk2_b", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const vin0_groups[] = { "vin0_data8", "vin0_data10", @@ -2041,13 +2064,16 @@ static const char * const vin1_groups[] = { "vin1_clkenb", "vin1_clk", }; +#endif static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(avb0), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(canfd_clk), SH_PFC_FUNCTION(canfd0), SH_PFC_FUNCTION(canfd1), SH_PFC_FUNCTION(du), +#endif SH_PFC_FUNCTION(hscif0), SH_PFC_FUNCTION(hscif1), SH_PFC_FUNCTION(hscif2), @@ -2057,8 +2083,11 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(i2c2), SH_PFC_FUNCTION(i2c3), SH_PFC_FUNCTION(i2c4), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(intc_ex), +#endif SH_PFC_FUNCTION(mmc), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(msiof0), SH_PFC_FUNCTION(msiof1), SH_PFC_FUNCTION(msiof2), @@ -2068,6 +2097,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(pwm2), SH_PFC_FUNCTION(pwm3), SH_PFC_FUNCTION(pwm4), +#endif SH_PFC_FUNCTION(qspi0), SH_PFC_FUNCTION(qspi1), SH_PFC_FUNCTION(rpc), @@ -2077,8 +2107,10 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(scif3), SH_PFC_FUNCTION(scif4), SH_PFC_FUNCTION(tmu), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(vin0), SH_PFC_FUNCTION(vin1), +#endif }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { diff --git a/drivers/pinctrl/renesas/pfc-r8a77980.c b/drivers/pinctrl/renesas/pfc-r8a77980.c index e3fc4045741..59f4bdde202 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77980.c +++ b/drivers/pinctrl/renesas/pfc-r8a77980.c @@ -929,6 +929,7 @@ static const unsigned int avb_avtp_match_mux[] = { AVB_AVTP_MATCH_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - CANFD0 ----------------------------------------------------------------- */ static const unsigned int canfd0_data_a_pins[] = { /* CANFD0_TX, CANFD0_RX */ @@ -1046,6 +1047,7 @@ static const unsigned int du_disp_pins[] = { static const unsigned int du_disp_mux[] = { DU_DISP_MARK, }; +#endif /* - GETHER ----------------------------------------------------------------- */ static const unsigned int gether_link_a_pins[] = { @@ -1319,6 +1321,7 @@ static const unsigned int i2c5_mux[] = { SDA5_MARK, SCL5_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - INTC-EX ---------------------------------------------------------------- */ static const unsigned int intc_ex_irq0_pins[] = { /* IRQ0 */ @@ -1362,6 +1365,7 @@ static const unsigned int intc_ex_irq5_pins[] = { static const unsigned int intc_ex_irq5_mux[] = { IRQ5_MARK, }; +#endif /* - MMC -------------------------------------------------------------------- */ static const unsigned int mmc_data_pins[] = { @@ -1406,6 +1410,7 @@ static const unsigned int mmc_ds_mux[] = { MMC_DS_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - MSIOF0 ----------------------------------------------------------------- */ static const unsigned int msiof0_clk_pins[] = { /* MSIOF0_SCK */ @@ -1661,6 +1666,7 @@ static const unsigned int pwm4_b_pins[] = { static const unsigned int pwm4_b_mux[] = { PWM4_B_MARK, }; +#endif /* - QSPI0 ------------------------------------------------------------------ */ static const unsigned int qspi0_ctrl_pins[] = { @@ -1907,6 +1913,7 @@ static const unsigned int tpu_to3_mux[] = { TPU0TO3_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - VIN0 ------------------------------------------------------------------- */ static const unsigned int vin0_data_pins[] = { RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), @@ -2032,6 +2039,7 @@ static const unsigned int vin1_clk_pins[] = { static const unsigned int vin1_clk_mux[] = { VI1_CLK_MARK, }; +#endif static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(avb_link), @@ -2043,6 +2051,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(avb_avtp_pps), SH_PFC_PIN_GROUP(avb_avtp_capture), SH_PFC_PIN_GROUP(avb_avtp_match), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(canfd0_data_a), SH_PFC_PIN_GROUP(canfd0_data_b), SH_PFC_PIN_GROUP(canfd1_data), @@ -2055,6 +2064,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(du_oddf), SH_PFC_PIN_GROUP(du_cde), SH_PFC_PIN_GROUP(du_disp), +#endif SH_PFC_PIN_GROUP(gether_link_a), SH_PFC_PIN_GROUP(gether_phy_int_a), SH_PFC_PIN_GROUP(gether_mdio_a), @@ -2087,12 +2097,14 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(i2c3), SH_PFC_PIN_GROUP(i2c4), SH_PFC_PIN_GROUP(i2c5), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(intc_ex_irq0), SH_PFC_PIN_GROUP(intc_ex_irq1), SH_PFC_PIN_GROUP(intc_ex_irq2), SH_PFC_PIN_GROUP(intc_ex_irq3), SH_PFC_PIN_GROUP(intc_ex_irq4), SH_PFC_PIN_GROUP(intc_ex_irq5), +#endif BUS_DATA_PIN_GROUP(mmc_data, 1), BUS_DATA_PIN_GROUP(mmc_data, 4), BUS_DATA_PIN_GROUP(mmc_data, 8), @@ -2100,6 +2112,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(mmc_cd), SH_PFC_PIN_GROUP(mmc_wp), SH_PFC_PIN_GROUP(mmc_ds), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(msiof0_clk), SH_PFC_PIN_GROUP(msiof0_sync), SH_PFC_PIN_GROUP(msiof0_ss1), @@ -2134,6 +2147,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(pwm3_b), SH_PFC_PIN_GROUP(pwm4_a), SH_PFC_PIN_GROUP(pwm4_b), +#endif SH_PFC_PIN_GROUP(qspi0_ctrl), SH_PFC_PIN_GROUP_SUBSET(qspi0_data2, rpc_data, 0, 2), SH_PFC_PIN_GROUP_SUBSET(qspi0_data4, rpc_data, 0, 4), @@ -2170,6 +2184,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(tpu_to1), SH_PFC_PIN_GROUP(tpu_to2), SH_PFC_PIN_GROUP(tpu_to3), +#ifdef CONFIG_PINCTRL_PFC_FULL BUS_DATA_PIN_GROUP(vin0_data, 8), BUS_DATA_PIN_GROUP(vin0_data, 10), BUS_DATA_PIN_GROUP(vin0_data, 12), @@ -2188,6 +2203,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(vin1_field), SH_PFC_PIN_GROUP(vin1_clkenb), SH_PFC_PIN_GROUP(vin1_clk), +#endif }; static const char * const avb_groups[] = { @@ -2202,6 +2218,7 @@ static const char * const avb_groups[] = { "avb_avtp_match", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const canfd0_groups[] = { "canfd0_data_a", "canfd0_data_b", @@ -2225,6 +2242,7 @@ static const char * const du_groups[] = { "du_cde", "du_disp", }; +#endif static const char * const gether_groups[] = { "gether_link_a", @@ -2291,6 +2309,7 @@ static const char * const i2c5_groups[] = { "i2c5", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const intc_ex_groups[] = { "intc_ex_irq0", "intc_ex_irq1", @@ -2299,6 +2318,7 @@ static const char * const intc_ex_groups[] = { "intc_ex_irq4", "intc_ex_irq5", }; +#endif static const char * const mmc_groups[] = { "mmc_data1", @@ -2310,6 +2330,7 @@ static const char * const mmc_groups[] = { "mmc_ds", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const msiof0_groups[] = { "msiof0_clk", "msiof0_sync", @@ -2370,6 +2391,7 @@ static const char * const pwm4_groups[] = { "pwm4_a", "pwm4_b", }; +#endif static const char * const qspi0_groups[] = { "qspi0_ctrl", @@ -2437,6 +2459,7 @@ static const char * const tpu_groups[] = { "tpu_to3", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const vin0_groups[] = { "vin0_data8", "vin0_data10", @@ -2460,13 +2483,16 @@ static const char * const vin1_groups[] = { "vin1_clkenb", "vin1_clk", }; +#endif static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(avb), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(canfd0), SH_PFC_FUNCTION(canfd1), SH_PFC_FUNCTION(canfd_clk), SH_PFC_FUNCTION(du), +#endif SH_PFC_FUNCTION(gether), SH_PFC_FUNCTION(hscif0), SH_PFC_FUNCTION(hscif1), @@ -2478,8 +2504,11 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(i2c3), SH_PFC_FUNCTION(i2c4), SH_PFC_FUNCTION(i2c5), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(intc_ex), +#endif SH_PFC_FUNCTION(mmc), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(msiof0), SH_PFC_FUNCTION(msiof1), SH_PFC_FUNCTION(msiof2), @@ -2489,6 +2518,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(pwm2), SH_PFC_FUNCTION(pwm3), SH_PFC_FUNCTION(pwm4), +#endif SH_PFC_FUNCTION(qspi0), SH_PFC_FUNCTION(qspi1), SH_PFC_FUNCTION(rpc), @@ -2499,8 +2529,10 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(scif_clk), SH_PFC_FUNCTION(tmu), SH_PFC_FUNCTION(tpu), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(vin0), SH_PFC_FUNCTION(vin1), +#endif }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { diff --git a/drivers/pinctrl/renesas/pfc-r8a77990.c b/drivers/pinctrl/renesas/pfc-r8a77990.c index e3a9c5e053d..75b7429bc0d 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77990.c +++ b/drivers/pinctrl/renesas/pfc-r8a77990.c @@ -1314,6 +1314,7 @@ static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_NOGP_ALL(), }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - AUDIO CLOCK ------------------------------------------------------------ */ static const unsigned int audio_clk_a_pins[] = { /* CLK A */ @@ -1476,6 +1477,7 @@ static const unsigned int audio_clkout3_c_pins[] = { static const unsigned int audio_clkout3_c_mux[] = { AUDIO_CLKOUT3_C_MARK, }; +#endif /* - EtherAVB --------------------------------------------------------------- */ static const unsigned int avb_link_pins[] = { @@ -1549,6 +1551,7 @@ static const unsigned int avb_avtp_capture_mux[] = { AVB_AVTP_CAPTURE_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - CAN ------------------------------------------------------------------ */ static const unsigned int can0_data_pins[] = { /* TX, RX */ @@ -1596,6 +1599,7 @@ static const unsigned int canfd1_data_pins[] = { static const unsigned int canfd1_data_mux[] = { CANFD1_TX_MARK, CANFD1_RX_MARK, }; +#endif #ifdef CONFIG_PINCTRL_PFC_R8A77990 /* - DRIF0 --------------------------------------------------------------- */ @@ -1792,6 +1796,7 @@ static const unsigned int drif3_data1_b_mux[] = { }; #endif /* CONFIG_PINCTRL_PFC_R8A77990 */ +#ifdef CONFIG_PINCTRL_PFC_FULL /* - DU --------------------------------------------------------------------- */ static const unsigned int du_rgb666_pins[] = { /* R[7:2], G[7:2], B[7:2] */ @@ -1879,6 +1884,7 @@ static const unsigned int du_disp_pins[] = { static const unsigned int du_disp_mux[] = { DU_DISP_MARK, }; +#endif /* - HSCIF0 --------------------------------------------------*/ static const unsigned int hscif0_data_a_pins[] = { @@ -2300,6 +2306,7 @@ static const unsigned int i2c7_b_mux[] = { SCL7_B_MARK, SDA7_B_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - INTC-EX ---------------------------------------------------------------- */ static const unsigned int intc_ex_irq0_pins[] = { /* IRQ0 */ @@ -2343,6 +2350,7 @@ static const unsigned int intc_ex_irq5_pins[] = { static const unsigned int intc_ex_irq5_mux[] = { IRQ5_MARK, }; +#endif #ifdef CONFIG_PINCTRL_PFC_R8A77990 /* - MLB+ ------------------------------------------------------------------- */ @@ -2354,6 +2362,7 @@ static const unsigned int mlb_3pin_mux[] = { }; #endif /* CONFIG_PINCTRL_PFC_R8A77990 */ +#ifdef CONFIG_PINCTRL_PFC_FULL /* - MSIOF0 ----------------------------------------------------------------- */ static const unsigned int msiof0_clk_pins[] = { /* SCK */ @@ -2823,6 +2832,7 @@ static const unsigned int pwm6_b_pins[] = { static const unsigned int pwm6_b_mux[] = { PWM6_B_MARK, }; +#endif /* - QSPI0 ------------------------------------------------------------------ */ static const unsigned int qspi0_ctrl_pins[] = { @@ -3293,6 +3303,7 @@ static const unsigned int sdhi3_ds_mux[] = { SD3_DS_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - SSI -------------------------------------------------------------------- */ static const unsigned int ssi0_data_pins[] = { /* SDATA */ @@ -3482,6 +3493,7 @@ static const unsigned int ssi9_ctrl_b_pins[] = { static const unsigned int ssi9_ctrl_b_mux[] = { SSI_SCK9_B_MARK, SSI_WS9_B_MARK, }; +#endif /* - TMU -------------------------------------------------------------------- */ static const unsigned int tmu_tclk1_a_pins[] = { @@ -3567,6 +3579,7 @@ static const unsigned int usb30_id_mux[] = { USB3HS0_ID_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - VIN4 ------------------------------------------------------------------- */ static const unsigned int vin4_data18_a_pins[] = { RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), @@ -3786,6 +3799,7 @@ static const unsigned int vin5_clk_b_pins[] = { static const unsigned int vin5_clk_b_mux[] = { VI5_CLK_B_MARK, }; +#endif static const struct { struct sh_pfc_pin_group common[261]; @@ -3794,6 +3808,7 @@ static const struct { #endif } pinmux_groups = { .common = { +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(audio_clk_a), SH_PFC_PIN_GROUP(audio_clk_b_a), SH_PFC_PIN_GROUP(audio_clk_b_b), @@ -3812,6 +3827,7 @@ static const struct { SH_PFC_PIN_GROUP(audio_clkout3_a), SH_PFC_PIN_GROUP(audio_clkout3_b), SH_PFC_PIN_GROUP(audio_clkout3_c), +#endif SH_PFC_PIN_GROUP(avb_link), SH_PFC_PIN_GROUP(avb_magic), SH_PFC_PIN_GROUP(avb_phy_int), @@ -3819,6 +3835,7 @@ static const struct { SH_PFC_PIN_GROUP(avb_avtp_pps), SH_PFC_PIN_GROUP(avb_avtp_match), SH_PFC_PIN_GROUP(avb_avtp_capture), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(can0_data), SH_PFC_PIN_GROUP(can1_data), SH_PFC_PIN_GROUP(can_clk), @@ -3833,6 +3850,7 @@ static const struct { SH_PFC_PIN_GROUP(du_disp_cde), SH_PFC_PIN_GROUP(du_cde), SH_PFC_PIN_GROUP(du_disp), +#endif SH_PFC_PIN_GROUP(hscif0_data_a), SH_PFC_PIN_GROUP(hscif0_clk_a), SH_PFC_PIN_GROUP(hscif0_ctrl_a), @@ -3879,6 +3897,7 @@ static const struct { SH_PFC_PIN_GROUP(i2c6_b), SH_PFC_PIN_GROUP(i2c7_a), SH_PFC_PIN_GROUP(i2c7_b), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(intc_ex_irq0), SH_PFC_PIN_GROUP(intc_ex_irq1), SH_PFC_PIN_GROUP(intc_ex_irq2), @@ -3936,6 +3955,7 @@ static const struct { SH_PFC_PIN_GROUP(pwm5_b), SH_PFC_PIN_GROUP(pwm6_a), SH_PFC_PIN_GROUP(pwm6_b), +#endif SH_PFC_PIN_GROUP(qspi0_ctrl), SH_PFC_PIN_GROUP_SUBSET(qspi0_data2, rpc_data, 0, 2), SH_PFC_PIN_GROUP_SUBSET(qspi0_data4, rpc_data, 0, 4), @@ -3995,6 +4015,7 @@ static const struct { SH_PFC_PIN_GROUP(sdhi3_cd), SH_PFC_PIN_GROUP(sdhi3_wp), SH_PFC_PIN_GROUP(sdhi3_ds), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(ssi0_data), SH_PFC_PIN_GROUP(ssi01239_ctrl), SH_PFC_PIN_GROUP(ssi1_data), @@ -4016,6 +4037,7 @@ static const struct { SH_PFC_PIN_GROUP(ssi9_data), SH_PFC_PIN_GROUP(ssi9_ctrl_a), SH_PFC_PIN_GROUP(ssi9_ctrl_b), +#endif SH_PFC_PIN_GROUP(tmu_tclk1_a), SH_PFC_PIN_GROUP(tmu_tclk1_b), SH_PFC_PIN_GROUP(tmu_tclk2_a), @@ -4025,6 +4047,7 @@ static const struct { SH_PFC_PIN_GROUP(usb0_id), SH_PFC_PIN_GROUP(usb30), SH_PFC_PIN_GROUP(usb30_id), +#ifdef CONFIG_PINCTRL_PFC_FULL BUS_DATA_PIN_GROUP(vin4_data, 8, _a), BUS_DATA_PIN_GROUP(vin4_data, 10, _a), BUS_DATA_PIN_GROUP(vin4_data, 12, _a), @@ -4055,6 +4078,7 @@ static const struct { SH_PFC_PIN_GROUP(vin5_clkenb_a), SH_PFC_PIN_GROUP(vin5_clk_a), SH_PFC_PIN_GROUP(vin5_clk_b), +#endif }, #ifdef CONFIG_PINCTRL_PFC_R8A77990 .automotive = { @@ -4084,6 +4108,7 @@ static const struct { #endif /* CONFIG_PINCTRL_PFC_R8A77990 */ }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const audio_clk_groups[] = { "audio_clk_a", "audio_clk_b_a", @@ -4104,6 +4129,7 @@ static const char * const audio_clk_groups[] = { "audio_clkout3_b", "audio_clkout3_c", }; +#endif static const char * const avb_groups[] = { "avb_link", @@ -4115,6 +4141,7 @@ static const char * const avb_groups[] = { "avb_avtp_capture", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const can0_groups[] = { "can0_data", }; @@ -4134,6 +4161,7 @@ static const char * const canfd0_groups[] = { static const char * const canfd1_groups[] = { "canfd1_data", }; +#endif #ifdef CONFIG_PINCTRL_PFC_R8A77990 static const char * const drif0_groups[] = { @@ -4170,6 +4198,7 @@ static const char * const drif3_groups[] = { }; #endif /* CONFIG_PINCTRL_PFC_R8A77990 */ +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const du_groups[] = { "du_rgb666", "du_rgb888", @@ -4181,6 +4210,7 @@ static const char * const du_groups[] = { "du_cde", "du_disp", }; +#endif static const char * const hscif0_groups[] = { "hscif0_data_a", @@ -4261,6 +4291,7 @@ static const char * const i2c7_groups[] = { "i2c7_b", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const intc_ex_groups[] = { "intc_ex_irq0", "intc_ex_irq1", @@ -4269,6 +4300,7 @@ static const char * const intc_ex_groups[] = { "intc_ex_irq4", "intc_ex_irq5", }; +#endif #ifdef CONFIG_PINCTRL_PFC_R8A77990 static const char * const mlb_3pin_groups[] = { @@ -4276,6 +4308,7 @@ static const char * const mlb_3pin_groups[] = { }; #endif /* CONFIG_PINCTRL_PFC_R8A77990 */ +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const msiof0_groups[] = { "msiof0_clk", "msiof0_sync", @@ -4359,6 +4392,7 @@ static const char * const pwm6_groups[] = { "pwm6_a", "pwm6_b", }; +#endif static const char * const qspi0_groups[] = { "qspi0_ctrl", @@ -4458,6 +4492,7 @@ static const char * const sdhi3_groups[] = { "sdhi3_ds", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const ssi_groups[] = { "ssi0_data", "ssi01239_ctrl", @@ -4481,6 +4516,7 @@ static const char * const ssi_groups[] = { "ssi9_ctrl_a", "ssi9_ctrl_b", }; +#endif static const char * const tmu_groups[] = { "tmu_tclk1_a", @@ -4500,6 +4536,7 @@ static const char * const usb30_groups[] = { "usb30_id", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const vin4_groups[] = { "vin4_data8_a", "vin4_data10_a", @@ -4535,6 +4572,7 @@ static const char * const vin5_groups[] = { "vin5_clk_a", "vin5_clk_b", }; +#endif static const struct { struct sh_pfc_function common[50]; @@ -4543,14 +4581,18 @@ static const struct { #endif } pinmux_functions = { .common = { +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(audio_clk), +#endif SH_PFC_FUNCTION(avb), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(can0), SH_PFC_FUNCTION(can1), SH_PFC_FUNCTION(can_clk), SH_PFC_FUNCTION(canfd0), SH_PFC_FUNCTION(canfd1), SH_PFC_FUNCTION(du), +#endif SH_PFC_FUNCTION(hscif0), SH_PFC_FUNCTION(hscif1), SH_PFC_FUNCTION(hscif2), @@ -4562,6 +4604,7 @@ static const struct { SH_PFC_FUNCTION(i2c5), SH_PFC_FUNCTION(i2c6), SH_PFC_FUNCTION(i2c7), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(intc_ex), SH_PFC_FUNCTION(msiof0), SH_PFC_FUNCTION(msiof1), @@ -4574,6 +4617,7 @@ static const struct { SH_PFC_FUNCTION(pwm4), SH_PFC_FUNCTION(pwm5), SH_PFC_FUNCTION(pwm6), +#endif SH_PFC_FUNCTION(qspi0), SH_PFC_FUNCTION(qspi1), SH_PFC_FUNCTION(rpc), @@ -4587,12 +4631,16 @@ static const struct { SH_PFC_FUNCTION(sdhi0), SH_PFC_FUNCTION(sdhi1), SH_PFC_FUNCTION(sdhi3), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(ssi), +#endif SH_PFC_FUNCTION(tmu), SH_PFC_FUNCTION(usb0), SH_PFC_FUNCTION(usb30), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(vin4), SH_PFC_FUNCTION(vin5), +#endif }, #ifdef CONFIG_PINCTRL_PFC_R8A77990 .automotive = { diff --git a/drivers/pinctrl/renesas/pfc-r8a77995.c b/drivers/pinctrl/renesas/pfc-r8a77995.c index d3e2d842fa5..6fe2d743418 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77995.c +++ b/drivers/pinctrl/renesas/pfc-r8a77995.c @@ -955,6 +955,7 @@ static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_NOGP_ALL(), }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - AUDIO CLOCK ------------------------------------------------------------- */ static const unsigned int audio_clk_a_pins[] = { /* CLK A */ @@ -984,6 +985,7 @@ static const unsigned int audio_clkout1_pins[] = { static const unsigned int audio_clkout1_mux[] = { AUDIO_CLKOUT1_MARK, }; +#endif /* - EtherAVB --------------------------------------------------------------- */ static const unsigned int avb0_link_pins[] = { @@ -1078,6 +1080,7 @@ static const unsigned int avb0_avtp_capture_b_mux[] = { AVB0_AVTP_CAPTURE_B_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - CAN ------------------------------------------------------------------ */ static const unsigned int can0_data_a_pins[] = { /* TX, RX */ @@ -1213,6 +1216,7 @@ static const unsigned int du_disp_pins[] = { static const unsigned int du_disp_mux[] = { DU_DISP_MARK, }; +#endif /* - I2C -------------------------------------------------------------------- */ static const unsigned int i2c0_pins[] = { @@ -1288,6 +1292,7 @@ static const unsigned int mmc_ctrl_mux[] = { MMC_CLK_MARK, MMC_CMD_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - MSIOF0 ----------------------------------------------------------------- */ static const unsigned int msiof0_clk_pins[] = { /* SCK */ @@ -1682,6 +1687,7 @@ static const unsigned int pwm3_c_pins[] = { static const unsigned int pwm3_c_mux[] = { PWM3_C_MARK, }; +#endif /* - QSPI0 ------------------------------------------------------------------ */ static const unsigned int qspi0_ctrl_pins[] = { @@ -1929,6 +1935,7 @@ static const unsigned int scif_clk_mux[] = { SCIF_CLK_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - SSI ---------------------------------------------------------------*/ static const unsigned int ssi3_data_pins[] = { /* SDATA */ @@ -1972,6 +1979,7 @@ static const unsigned int ssi4_data_b_pins[] = { static const unsigned int ssi4_data_b_mux[] = { SSI_SDATA4_B_MARK, }; +#endif /* - USB0 ------------------------------------------------------------------- */ static const unsigned int usb0_pins[] = { @@ -1982,6 +1990,7 @@ static const unsigned int usb0_mux[] = { USB0_PWEN_MARK, USB0_OVC_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - VIN4 ------------------------------------------------------------------- */ static const unsigned int vin4_data18_pins[] = { RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4), @@ -2061,12 +2070,15 @@ static const unsigned int vin4_clk_pins[] = { static const unsigned int vin4_clk_mux[] = { VI4_CLK_MARK, }; +#endif static const struct sh_pfc_pin_group pinmux_groups[] = { +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(audio_clk_a), SH_PFC_PIN_GROUP(audio_clk_b), SH_PFC_PIN_GROUP(audio_clkout), SH_PFC_PIN_GROUP(audio_clkout1), +#endif SH_PFC_PIN_GROUP(avb0_link), SH_PFC_PIN_GROUP(avb0_magic), SH_PFC_PIN_GROUP(avb0_phy_int), @@ -2079,6 +2091,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(avb0_avtp_pps_b), SH_PFC_PIN_GROUP(avb0_avtp_match_b), SH_PFC_PIN_GROUP(avb0_avtp_capture_b), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(can0_data_a), SH_PFC_PIN_GROUP(can0_data_b), SH_PFC_PIN_GROUP(can1_data_a), @@ -2094,6 +2107,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(du_disp_cde), SH_PFC_PIN_GROUP(du_cde), SH_PFC_PIN_GROUP(du_disp), +#endif SH_PFC_PIN_GROUP(i2c0), SH_PFC_PIN_GROUP(i2c1), SH_PFC_PIN_GROUP(i2c2_a), @@ -2105,6 +2119,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { BUS_DATA_PIN_GROUP(mmc_data, 4), BUS_DATA_PIN_GROUP(mmc_data, 8), SH_PFC_PIN_GROUP(mmc_ctrl), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(msiof0_clk), SH_PFC_PIN_GROUP(msiof0_sync), SH_PFC_PIN_GROUP(msiof0_ss1), @@ -2148,6 +2163,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(pwm3_a), SH_PFC_PIN_GROUP(pwm3_b), SH_PFC_PIN_GROUP(pwm3_c), +#endif SH_PFC_PIN_GROUP(qspi0_ctrl), SH_PFC_PIN_GROUP_SUBSET(qspi0_data2, rpc_data, 0, 2), SH_PFC_PIN_GROUP_SUBSET(qspi0_data4, rpc_data, 0, 4), @@ -2185,13 +2201,16 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(scif5_data_b), SH_PFC_PIN_GROUP(scif5_clk_b), SH_PFC_PIN_GROUP(scif_clk), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(ssi3_data), SH_PFC_PIN_GROUP(ssi34_ctrl), SH_PFC_PIN_GROUP(ssi4_ctrl_a), SH_PFC_PIN_GROUP(ssi4_data_a), SH_PFC_PIN_GROUP(ssi4_ctrl_b), SH_PFC_PIN_GROUP(ssi4_data_b), +#endif SH_PFC_PIN_GROUP(usb0), +#ifdef CONFIG_PINCTRL_PFC_FULL BUS_DATA_PIN_GROUP(vin4_data, 8), BUS_DATA_PIN_GROUP(vin4_data, 10), BUS_DATA_PIN_GROUP(vin4_data, 12), @@ -2203,14 +2222,17 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(vin4_field), SH_PFC_PIN_GROUP(vin4_clkenb), SH_PFC_PIN_GROUP(vin4_clk), +#endif }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const audio_clk_groups[] = { "audio_clk_a", "audio_clk_b", "audio_clkout", "audio_clkout1", }; +#endif static const char * const avb0_groups[] = { "avb0_link", @@ -2227,6 +2249,7 @@ static const char * const avb0_groups[] = { "avb0_avtp_capture_b", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const can0_groups[] = { "can0_data_a", "can0_data_b", @@ -2256,6 +2279,7 @@ static const char * const du_groups[] = { "du_cde", "du_disp", }; +#endif static const char * const i2c0_groups[] = { "i2c0", @@ -2285,6 +2309,7 @@ static const char * const mmc_groups[] = { "mmc_ctrl", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const msiof0_groups[] = { "msiof0_clk", "msiof0_sync", @@ -2351,6 +2376,7 @@ static const char * const pwm3_groups[] = { "pwm3_b", "pwm3_c", }; +#endif static const char * const qspi0_groups[] = { "qspi0_ctrl", @@ -2419,6 +2445,7 @@ static const char * const scif_clk_groups[] = { "scif_clk", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const ssi_groups[] = { "ssi3_data", "ssi34_ctrl", @@ -2427,11 +2454,13 @@ static const char * const ssi_groups[] = { "ssi4_ctrl_b", "ssi4_data_b", }; +#endif static const char * const usb0_groups[] = { "usb0", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const vin4_groups[] = { "vin4_data8", "vin4_data10", @@ -2445,22 +2474,28 @@ static const char * const vin4_groups[] = { "vin4_clkenb", "vin4_clk", }; +#endif static const struct sh_pfc_function pinmux_functions[] = { +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(audio_clk), +#endif SH_PFC_FUNCTION(avb0), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(can0), SH_PFC_FUNCTION(can1), SH_PFC_FUNCTION(can_clk), SH_PFC_FUNCTION(canfd0), SH_PFC_FUNCTION(canfd1), SH_PFC_FUNCTION(du), +#endif SH_PFC_FUNCTION(i2c0), SH_PFC_FUNCTION(i2c1), SH_PFC_FUNCTION(i2c2), SH_PFC_FUNCTION(i2c3), SH_PFC_FUNCTION(mlb_3pin), SH_PFC_FUNCTION(mmc), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(msiof0), SH_PFC_FUNCTION(msiof1), SH_PFC_FUNCTION(msiof2), @@ -2469,6 +2504,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(pwm1), SH_PFC_FUNCTION(pwm2), SH_PFC_FUNCTION(pwm3), +#endif SH_PFC_FUNCTION(qspi0), SH_PFC_FUNCTION(qspi1), SH_PFC_FUNCTION(rpc), @@ -2479,9 +2515,13 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(scif4), SH_PFC_FUNCTION(scif5), SH_PFC_FUNCTION(scif_clk), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(ssi), +#endif SH_PFC_FUNCTION(usb0), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(vin4), +#endif }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { diff --git a/drivers/pinctrl/renesas/pfc-r8a779a0.c b/drivers/pinctrl/renesas/pfc-r8a779a0.c index 6f898385027..39690bd5d07 100644 --- a/drivers/pinctrl/renesas/pfc-r8a779a0.c +++ b/drivers/pinctrl/renesas/pfc-r8a779a0.c @@ -1697,6 +1697,7 @@ static const unsigned int avb5_avtp_match_mux[] = { AVB5_AVTP_MATCH_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - CANFD0 ----------------------------------------------------------------- */ static const unsigned int canfd0_data_pins[] = { /* CANFD0_TX, CANFD0_RX */ @@ -1817,6 +1818,7 @@ static const unsigned int du_oddf_pins[] = { static const unsigned int du_oddf_mux[] = { DU_ODDF_DISP_CDE_MARK, }; +#endif /* - HSCIF0 ----------------------------------------------------------------- */ static const unsigned int hscif0_data_pins[] = { @@ -1973,6 +1975,7 @@ static const unsigned int i2c6_mux[] = { SDA6_MARK, SCL6_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - INTC-EX ---------------------------------------------------------------- */ static const unsigned int intc_ex_irq0_pins[] = { /* IRQ0 */ @@ -2016,6 +2019,7 @@ static const unsigned int intc_ex_irq5_pins[] = { static const unsigned int intc_ex_irq5_mux[] = { IRQ5_MARK, }; +#endif /* - MMC -------------------------------------------------------------------- */ static const unsigned int mmc_data_pins[] = { @@ -2060,6 +2064,7 @@ static const unsigned int mmc_ds_mux[] = { MMC_DS_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - MSIOF0 ----------------------------------------------------------------- */ static const unsigned int msiof0_clk_pins[] = { /* MSIOF0_SCK */ @@ -2368,6 +2373,7 @@ static const unsigned int pwm4_pins[] = { static const unsigned int pwm4_mux[] = { PWM4_MARK, }; +#endif /* - QSPI0 ------------------------------------------------------------------ */ static const unsigned int qspi0_ctrl_pins[] = { @@ -2651,6 +2657,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(avb5_avtp_capture), SH_PFC_PIN_GROUP(avb5_avtp_match), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(canfd0_data), SH_PFC_PIN_GROUP(canfd1_data), SH_PFC_PIN_GROUP(canfd2_data), @@ -2665,6 +2672,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(du_clk_out), SH_PFC_PIN_GROUP(du_sync), SH_PFC_PIN_GROUP(du_oddf), +#endif SH_PFC_PIN_GROUP(hscif0_data), SH_PFC_PIN_GROUP(hscif0_clk), @@ -2687,12 +2695,14 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(i2c5), SH_PFC_PIN_GROUP(i2c6), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(intc_ex_irq0), SH_PFC_PIN_GROUP(intc_ex_irq1), SH_PFC_PIN_GROUP(intc_ex_irq2), SH_PFC_PIN_GROUP(intc_ex_irq3), SH_PFC_PIN_GROUP(intc_ex_irq4), SH_PFC_PIN_GROUP(intc_ex_irq5), +#endif BUS_DATA_PIN_GROUP(mmc_data, 1), BUS_DATA_PIN_GROUP(mmc_data, 4), @@ -2702,6 +2712,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(mmc_wp), SH_PFC_PIN_GROUP(mmc_ds), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(msiof0_clk), SH_PFC_PIN_GROUP(msiof0_sync), SH_PFC_PIN_GROUP(msiof0_ss1), @@ -2744,6 +2755,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(pwm2), SH_PFC_PIN_GROUP(pwm3), SH_PFC_PIN_GROUP(pwm4), +#endif SH_PFC_PIN_GROUP(qspi0_ctrl), BUS_DATA_PIN_GROUP(qspi0_data, 2), @@ -2852,6 +2864,7 @@ static const char * const avb5_groups[] = { "avb5_avtp_match", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const canfd0_groups[] = { "canfd0_data", }; @@ -2894,6 +2907,7 @@ static const char * const du_groups[] = { "du_sync", "du_oddf", }; +#endif static const char * const hscif0_groups[] = { "hscif0_data", @@ -2947,6 +2961,7 @@ static const char * const i2c6_groups[] = { "i2c6", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const intc_ex_groups[] = { "intc_ex_irq0", "intc_ex_irq1", @@ -2955,6 +2970,7 @@ static const char * const intc_ex_groups[] = { "intc_ex_irq4", "intc_ex_irq5", }; +#endif static const char * const mmc_groups[] = { "mmc_data1", @@ -2966,6 +2982,7 @@ static const char * const mmc_groups[] = { "mmc_ds", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const msiof0_groups[] = { "msiof0_clk", "msiof0_sync", @@ -3039,6 +3056,7 @@ static const char * const pwm3_groups[] = { static const char * const pwm4_groups[] = { "pwm4", }; +#endif static const char * const qspi0_groups[] = { "qspi0_ctrl", @@ -3105,6 +3123,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(avb4), SH_PFC_FUNCTION(avb5), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(canfd0), SH_PFC_FUNCTION(canfd1), SH_PFC_FUNCTION(canfd2), @@ -3116,6 +3135,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(can_clk), SH_PFC_FUNCTION(du), +#endif SH_PFC_FUNCTION(hscif0), SH_PFC_FUNCTION(hscif1), @@ -3130,10 +3150,13 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(i2c5), SH_PFC_FUNCTION(i2c6), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(intc_ex), +#endif SH_PFC_FUNCTION(mmc), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(msiof0), SH_PFC_FUNCTION(msiof1), SH_PFC_FUNCTION(msiof2), @@ -3146,6 +3169,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(pwm2), SH_PFC_FUNCTION(pwm3), SH_PFC_FUNCTION(pwm4), +#endif SH_PFC_FUNCTION(qspi0), SH_PFC_FUNCTION(qspi1), diff --git a/drivers/pinctrl/renesas/pfc-r8a779f0.c b/drivers/pinctrl/renesas/pfc-r8a779f0.c index eec50210d92..2b629135f69 100644 --- a/drivers/pinctrl/renesas/pfc-r8a779f0.c +++ b/drivers/pinctrl/renesas/pfc-r8a779f0.c @@ -654,6 +654,7 @@ static const unsigned int i2c5_mux[] = { SDA5_MARK, SCL5_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - INTC-EX ---------------------------------------------------------------- */ static const unsigned int intc_ex_irq0_pins[] = { /* IRQ0 */ @@ -697,6 +698,7 @@ static const unsigned int intc_ex_irq5_pins[] = { static const unsigned int intc_ex_irq5_mux[] = { IRQ5_MARK, }; +#endif /* - MMC -------------------------------------------------------------------- */ static const unsigned int mmc_data_pins[] = { @@ -741,6 +743,7 @@ static const unsigned int mmc_ds_mux[] = { MMC_DS_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - MSIOF0 ----------------------------------------------------------------- */ static const unsigned int msiof0_clk_pins[] = { /* MSIOF0_SCK */ @@ -916,6 +919,7 @@ static const unsigned int msiof3_rxd_pins[] = { static const unsigned int msiof3_rxd_mux[] = { MSIOF3_RXD_MARK, }; +#endif /* - PCIE ------------------------------------------------------------------- */ static const unsigned int pcie0_clkreq_n_pins[] = { @@ -1308,12 +1312,14 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(i2c3), SH_PFC_PIN_GROUP(i2c4), SH_PFC_PIN_GROUP(i2c5), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(intc_ex_irq0), SH_PFC_PIN_GROUP(intc_ex_irq1), SH_PFC_PIN_GROUP(intc_ex_irq2), SH_PFC_PIN_GROUP(intc_ex_irq3), SH_PFC_PIN_GROUP(intc_ex_irq4), SH_PFC_PIN_GROUP(intc_ex_irq5), +#endif BUS_DATA_PIN_GROUP(mmc_data, 1), BUS_DATA_PIN_GROUP(mmc_data, 4), BUS_DATA_PIN_GROUP(mmc_data, 8), @@ -1321,6 +1327,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(mmc_cd), SH_PFC_PIN_GROUP(mmc_wp), SH_PFC_PIN_GROUP(mmc_ds), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(msiof0_clk), SH_PFC_PIN_GROUP(msiof0_sync), SH_PFC_PIN_GROUP(msiof0_ss1), @@ -1345,6 +1352,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(msiof3_ss2), SH_PFC_PIN_GROUP(msiof3_txd), SH_PFC_PIN_GROUP(msiof3_rxd), +#endif SH_PFC_PIN_GROUP(pcie0_clkreq_n), SH_PFC_PIN_GROUP(pcie1_clkreq_n), SH_PFC_PIN_GROUP(qspi0_ctrl), @@ -1446,6 +1454,7 @@ static const char * const i2c5_groups[] = { "i2c5", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const intc_ex_groups[] = { "intc_ex_irq0", "intc_ex_irq1", @@ -1454,6 +1463,7 @@ static const char * const intc_ex_groups[] = { "intc_ex_irq4", "intc_ex_irq5", }; +#endif static const char * const mmc_groups[] = { "mmc_data1", @@ -1465,6 +1475,7 @@ static const char * const mmc_groups[] = { "mmc_ds", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const msiof0_groups[] = { "msiof0_clk", "msiof0_sync", @@ -1500,6 +1511,7 @@ static const char * const msiof3_groups[] = { "msiof3_txd", "msiof3_rxd", }; +#endif static const char * const pcie_groups[] = { "pcie0_clkreq_n", @@ -1596,12 +1608,16 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(i2c3), SH_PFC_FUNCTION(i2c4), SH_PFC_FUNCTION(i2c5), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(intc_ex), +#endif SH_PFC_FUNCTION(mmc), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(msiof0), SH_PFC_FUNCTION(msiof1), SH_PFC_FUNCTION(msiof2), SH_PFC_FUNCTION(msiof3), +#endif SH_PFC_FUNCTION(pcie), SH_PFC_FUNCTION(qspi0), SH_PFC_FUNCTION(qspi1), diff --git a/drivers/pinctrl/renesas/pfc-r8a779g0.c b/drivers/pinctrl/renesas/pfc-r8a779g0.c index 2a39d1c8884..f411be8b879 100644 --- a/drivers/pinctrl/renesas/pfc-r8a779g0.c +++ b/drivers/pinctrl/renesas/pfc-r8a779g0.c @@ -1237,6 +1237,7 @@ static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_NOGP_ALL(), }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - AUDIO CLOCK ----------------------------------------- */ static const unsigned int audio_clkin_pins[] = { /* CLK IN */ @@ -1252,6 +1253,7 @@ static const unsigned int audio_clkout_pins[] = { static const unsigned int audio_clkout_mux[] = { AUDIO_CLKOUT_MARK, }; +#endif /* - AVB0 ------------------------------------------------ */ static const unsigned int avb0_link_pins[] = { @@ -1487,6 +1489,7 @@ static const unsigned int avb2_avtp_match_mux[] = { AVB2_AVTP_MATCH_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - CANFD0 ----------------------------------------------------------------- */ static const unsigned int canfd0_data_pins[] = { /* CANFD0_TX, CANFD0_RX */ @@ -1575,6 +1578,7 @@ static const unsigned int can_clk_pins[] = { static const unsigned int can_clk_mux[] = { CAN_CLK_MARK, }; +#endif /* - HSCIF0 ----------------------------------------------------------------- */ static const unsigned int hscif0_data_pins[] = { @@ -1766,6 +1770,7 @@ static const unsigned int i2c5_mux[] = { SDA5_MARK, SCL5_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - INTC-EX ---------------------------------------------------------------- */ static const unsigned int intc_ex_irq0_a_pins[] = { /* IRQ0_A */ @@ -1849,6 +1854,7 @@ static const unsigned int intc_ex_irq5_pins[] = { static const unsigned int intc_ex_irq5_mux[] = { IRQ5_MARK, }; +#endif /* - MMC -------------------------------------------------------------------- */ static const unsigned int mmc_data_pins[] = { @@ -1893,6 +1899,7 @@ static const unsigned int mmc_ds_mux[] = { MMC_DS_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - MSIOF0 ----------------------------------------------------------------- */ static const unsigned int msiof0_clk_pins[] = { /* MSIOF0_SCK */ @@ -2156,6 +2163,7 @@ static const unsigned int msiof5_rxd_pins[] = { static const unsigned int msiof5_rxd_mux[] = { MSIOF5_RXD_MARK, }; +#endif /* - PCIE ------------------------------------------------------------------- */ static const unsigned int pcie0_clkreq_n_pins[] = { @@ -2176,6 +2184,7 @@ static const unsigned int pcie1_clkreq_n_mux[] = { PCIE1_CLKREQ_N_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - PWM0 ------------------------------------------------------------------- */ static const unsigned int pwm0_pins[] = { /* PWM0 */ @@ -2281,6 +2290,7 @@ static const unsigned int pwm9_pins[] = { static const unsigned int pwm9_mux[] = { PWM9_MARK, }; +#endif /* - QSPI0 ------------------------------------------------------------------ */ static const unsigned int qspi0_ctrl_pins[] = { @@ -2471,6 +2481,7 @@ static const unsigned int scif_clk2_mux[] = { SCIF_CLK2_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - SSI ------------------------------------------------- */ static const unsigned int ssi_data_pins[] = { /* SSI_SD */ @@ -2486,6 +2497,7 @@ static const unsigned int ssi_ctrl_pins[] = { static const unsigned int ssi_ctrl_mux[] = { SSI_SCK_MARK, SSI_WS_MARK, }; +#endif /* - TPU -------------------------------------------------------------------- */ static const unsigned int tpu_to0_a_pins[] = { @@ -2618,9 +2630,10 @@ static const unsigned int tsn0_avtp_match_mux[] = { }; static const struct sh_pfc_pin_group pinmux_groups[] = { +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(audio_clkin), SH_PFC_PIN_GROUP(audio_clkout), - +#endif SH_PFC_PIN_GROUP(avb0_link), SH_PFC_PIN_GROUP(avb0_magic), SH_PFC_PIN_GROUP(avb0_phy_int), @@ -2651,6 +2664,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(avb2_avtp_capture), SH_PFC_PIN_GROUP(avb2_avtp_match), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(canfd0_data), SH_PFC_PIN_GROUP(canfd1_data), SH_PFC_PIN_GROUP(canfd2_data), @@ -2661,6 +2675,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(canfd6_data), SH_PFC_PIN_GROUP(canfd7_data), SH_PFC_PIN_GROUP(can_clk), +#endif SH_PFC_PIN_GROUP(hscif0_data), SH_PFC_PIN_GROUP(hscif0_clk), @@ -2688,6 +2703,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(i2c4), SH_PFC_PIN_GROUP(i2c5), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(intc_ex_irq0_a), SH_PFC_PIN_GROUP(intc_ex_irq0_b), SH_PFC_PIN_GROUP(intc_ex_irq1_a), @@ -2699,6 +2715,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(intc_ex_irq4_a), SH_PFC_PIN_GROUP(intc_ex_irq4_b), SH_PFC_PIN_GROUP(intc_ex_irq5), +#endif BUS_DATA_PIN_GROUP(mmc_data, 1), BUS_DATA_PIN_GROUP(mmc_data, 4), @@ -2708,6 +2725,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(mmc_wp), SH_PFC_PIN_GROUP(mmc_ds), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(msiof0_clk), SH_PFC_PIN_GROUP(msiof0_sync), SH_PFC_PIN_GROUP(msiof0_ss1), @@ -2749,10 +2767,12 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(msiof5_ss2), SH_PFC_PIN_GROUP(msiof5_txd), SH_PFC_PIN_GROUP(msiof5_rxd), +#endif SH_PFC_PIN_GROUP(pcie0_clkreq_n), SH_PFC_PIN_GROUP(pcie1_clkreq_n), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(pwm0), SH_PFC_PIN_GROUP(pwm1_a), SH_PFC_PIN_GROUP(pwm1_b), @@ -2765,6 +2785,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(pwm7), SH_PFC_PIN_GROUP(pwm8), SH_PFC_PIN_GROUP(pwm9), +#endif SH_PFC_PIN_GROUP(qspi0_ctrl), BUS_DATA_PIN_GROUP(qspi0_data, 2), @@ -2794,8 +2815,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(scif_clk), SH_PFC_PIN_GROUP(scif_clk2), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(ssi_data), SH_PFC_PIN_GROUP(ssi_ctrl), +#endif SH_PFC_PIN_GROUP(tpu_to0_a), SH_PFC_PIN_GROUP(tpu_to0_b), @@ -2816,10 +2839,12 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(tsn0_avtp_match), }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const audio_clk_groups[] = { "audio_clkin", "audio_clkout", }; +#endif static const char * const avb0_groups[] = { "avb0_link", @@ -2857,6 +2882,7 @@ static const char * const avb2_groups[] = { "avb2_avtp_match", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const canfd0_groups[] = { "canfd0_data", }; @@ -2893,6 +2919,7 @@ static const char * const canfd7_groups[] = { static const char * const can_clk_groups[] = { "can_clk", }; +#endif static const char * const hscif0_groups[] = { "hscif0_data", @@ -2948,6 +2975,7 @@ static const char * const i2c5_groups[] = { "i2c5", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const intc_ex_groups[] = { "intc_ex_irq0_a", "intc_ex_irq0_b", @@ -2961,6 +2989,7 @@ static const char * const intc_ex_groups[] = { "intc_ex_irq4_b", "intc_ex_irq5", }; +#endif static const char * const mmc_groups[] = { "mmc_data1", @@ -2972,6 +3001,7 @@ static const char * const mmc_groups[] = { "mmc_ds", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const msiof0_groups[] = { "msiof0_clk", "msiof0_sync", @@ -3025,12 +3055,14 @@ static const char * const msiof5_groups[] = { "msiof5_txd", "msiof5_rxd", }; +#endif static const char * const pcie_groups[] = { "pcie0_clkreq_n", "pcie1_clkreq_n", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const pwm0_groups[] = { "pwm0", }; @@ -3072,6 +3104,7 @@ static const char * const pwm8_groups[] = { static const char * const pwm9_groups[] = { "pwm9", }; +#endif static const char * const qspi0_groups[] = { "qspi0_ctrl", @@ -3123,10 +3156,12 @@ static const char * const scif_clk2_groups[] = { "scif_clk2", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const ssi_groups[] = { "ssi_data", "ssi_ctrl", }; +#endif static const char * const tpu_groups[] = { "tpu_to0_a", @@ -3151,12 +3186,15 @@ static const char * const tsn0_groups[] = { }; static const struct sh_pfc_function pinmux_functions[] = { +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(audio_clk), +#endif SH_PFC_FUNCTION(avb0), SH_PFC_FUNCTION(avb1), SH_PFC_FUNCTION(avb2), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(canfd0), SH_PFC_FUNCTION(canfd1), SH_PFC_FUNCTION(canfd2), @@ -3166,6 +3204,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(canfd6), SH_PFC_FUNCTION(canfd7), SH_PFC_FUNCTION(can_clk), +#endif SH_PFC_FUNCTION(hscif0), SH_PFC_FUNCTION(hscif1), @@ -3179,19 +3218,24 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(i2c4), SH_PFC_FUNCTION(i2c5), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(intc_ex), +#endif SH_PFC_FUNCTION(mmc), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(msiof0), SH_PFC_FUNCTION(msiof1), SH_PFC_FUNCTION(msiof2), SH_PFC_FUNCTION(msiof3), SH_PFC_FUNCTION(msiof4), SH_PFC_FUNCTION(msiof5), +#endif SH_PFC_FUNCTION(pcie), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(pwm0), SH_PFC_FUNCTION(pwm1), SH_PFC_FUNCTION(pwm2), @@ -3202,6 +3246,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(pwm7), SH_PFC_FUNCTION(pwm8), SH_PFC_FUNCTION(pwm9), +#endif SH_PFC_FUNCTION(qspi0), SH_PFC_FUNCTION(qspi1), @@ -3213,7 +3258,9 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(scif_clk), SH_PFC_FUNCTION(scif_clk2), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(ssi), +#endif SH_PFC_FUNCTION(tpu), diff --git a/drivers/pinctrl/renesas/pfc-r8a779h0.c b/drivers/pinctrl/renesas/pfc-r8a779h0.c index bfabf0c379a..87af037a8d3 100644 --- a/drivers/pinctrl/renesas/pfc-r8a779h0.c +++ b/drivers/pinctrl/renesas/pfc-r8a779h0.c @@ -1193,6 +1193,7 @@ static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_NOGP_ALL(), }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - AUDIO CLOCK ----------------------------------------- */ static const unsigned int audio_clkin_pins[] = { /* CLK IN */ @@ -1208,6 +1209,7 @@ static const unsigned int audio_clkout_pins[] = { static const unsigned int audio_clkout_mux[] = { AUDIO_CLKOUT_MARK, }; +#endif /* - AVB0 ------------------------------------------------ */ static const unsigned int avb0_link_pins[] = { @@ -1491,6 +1493,7 @@ static const unsigned int avb2_avtp_match_mux[] = { AVB2_AVTP_MATCH_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - CANFD0 ----------------------------------------------------------------- */ static const unsigned int canfd0_data_pins[] = { /* CANFD0_TX, CANFD0_RX */ @@ -1535,6 +1538,7 @@ static const unsigned int can_clk_pins[] = { static const unsigned int can_clk_mux[] = { CAN_CLK_MARK, }; +#endif /* - HSCIF0 ----------------------------------------------------------------- */ static const unsigned int hscif0_data_pins[] = { @@ -1708,6 +1712,7 @@ static const unsigned int i2c3_mux[] = { SDA3_MARK, SCL3_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - INTC-EX ---------------------------------------------------------------- */ static const unsigned int intc_ex_irq0_a_pins[] = { /* IRQ0_A */ @@ -1791,6 +1796,7 @@ static const unsigned int intc_ex_irq5_pins[] = { static const unsigned int intc_ex_irq5_mux[] = { IRQ5_MARK, }; +#endif /* - MMC -------------------------------------------------------------------- */ static const unsigned int mmc_data_pins[] = { @@ -1835,6 +1841,7 @@ static const unsigned int mmc_ds_mux[] = { MMC_DS_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - MSIOF0 ----------------------------------------------------------------- */ static const unsigned int msiof0_clk_pins[] = { /* MSIOF0_SCK */ @@ -2098,6 +2105,7 @@ static const unsigned int msiof5_rxd_pins[] = { static const unsigned int msiof5_rxd_mux[] = { MSIOF5_RXD_MARK, }; +#endif /* - PCIE ------------------------------------------------------------------- */ static const unsigned int pcie0_clkreq_n_pins[] = { @@ -2109,6 +2117,7 @@ static const unsigned int pcie0_clkreq_n_mux[] = { PCIE0_CLKREQ_N_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - PWM0 --------------------------------------------------------------------- */ static const unsigned int pwm0_a_pins[] = { /* PWM0_A */ @@ -2209,6 +2218,7 @@ static const unsigned int pwm4_pins[] = { static const unsigned int pwm4_mux[] = { PWM4_MARK, }; +#endif /* - QSPI0 ------------------------------------------------------------------ */ static const unsigned int qspi0_ctrl_pins[] = { @@ -2399,6 +2409,7 @@ static const unsigned int scif_clk2_mux[] = { SCIF_CLK2_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - SSI ------------------------------------------------- */ static const unsigned int ssi_data_pins[] = { /* SSI_SD */ @@ -2414,6 +2425,7 @@ static const unsigned int ssi_ctrl_pins[] = { static const unsigned int ssi_ctrl_mux[] = { SSI_SCK_MARK, SSI_WS_MARK, }; +#endif /* - TPU --------------------------------------------------------------------- */ static const unsigned int tpu_to0_a_pins[] = { @@ -2475,8 +2487,10 @@ static const unsigned int tpu_to3_b_mux[] = { }; static const struct sh_pfc_pin_group pinmux_groups[] = { +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(audio_clkin), SH_PFC_PIN_GROUP(audio_clkout), +#endif SH_PFC_PIN_GROUP(avb0_link), SH_PFC_PIN_GROUP(avb0_magic), @@ -2510,11 +2524,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(avb2_avtp_capture), SH_PFC_PIN_GROUP(avb2_avtp_match), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(canfd0_data), SH_PFC_PIN_GROUP(canfd1_data), SH_PFC_PIN_GROUP(canfd2_data), SH_PFC_PIN_GROUP(canfd3_data), SH_PFC_PIN_GROUP(can_clk), +#endif SH_PFC_PIN_GROUP(hscif0_data), SH_PFC_PIN_GROUP(hscif0_clk), @@ -2540,6 +2556,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(i2c2), SH_PFC_PIN_GROUP(i2c3), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(intc_ex_irq0_a), SH_PFC_PIN_GROUP(intc_ex_irq0_b), SH_PFC_PIN_GROUP(intc_ex_irq1_a), @@ -2551,6 +2568,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(intc_ex_irq4_a), SH_PFC_PIN_GROUP(intc_ex_irq4_b), SH_PFC_PIN_GROUP(intc_ex_irq5), +#endif BUS_DATA_PIN_GROUP(mmc_data, 1), BUS_DATA_PIN_GROUP(mmc_data, 4), @@ -2560,6 +2578,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(mmc_wp), SH_PFC_PIN_GROUP(mmc_ds), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(msiof0_clk), SH_PFC_PIN_GROUP(msiof0_sync), SH_PFC_PIN_GROUP(msiof0_ss1), @@ -2601,9 +2620,11 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(msiof5_ss2), SH_PFC_PIN_GROUP(msiof5_txd), SH_PFC_PIN_GROUP(msiof5_rxd), +#endif SH_PFC_PIN_GROUP(pcie0_clkreq_n), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(pwm0_a), SH_PFC_PIN_GROUP(pwm0_b), SH_PFC_PIN_GROUP(pwm1_a), @@ -2616,6 +2637,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(pwm3_b), SH_PFC_PIN_GROUP(pwm3_c), SH_PFC_PIN_GROUP(pwm4), +#endif SH_PFC_PIN_GROUP(qspi0_ctrl), BUS_DATA_PIN_GROUP(qspi0_data, 2), @@ -2645,8 +2667,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(scif_clk), SH_PFC_PIN_GROUP(scif_clk2), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(ssi_data), SH_PFC_PIN_GROUP(ssi_ctrl), +#endif SH_PFC_PIN_GROUP(tpu_to0_a), SH_PFC_PIN_GROUP(tpu_to0_b), @@ -2658,10 +2682,12 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(tpu_to3_b), }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const audio_clk_groups[] = { "audio_clkin", "audio_clkout", }; +#endif static const char * const avb0_groups[] = { "avb0_link", @@ -2701,6 +2727,7 @@ static const char * const avb2_groups[] = { "avb2_avtp_match", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const canfd0_groups[] = { "canfd0_data", }; @@ -2720,6 +2747,7 @@ static const char * const canfd3_groups[] = { static const char * const can_clk_groups[] = { "can_clk", }; +#endif static const char * const hscif0_groups[] = { "hscif0_data", @@ -2767,6 +2795,7 @@ static const char * const i2c3_groups[] = { "i2c3", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const intc_ex_groups[] = { "intc_ex_irq0_a", "intc_ex_irq0_b", @@ -2780,6 +2809,7 @@ static const char * const intc_ex_groups[] = { "intc_ex_irq4_b", "intc_ex_irq5", }; +#endif static const char * const mmc_groups[] = { "mmc_data1", @@ -2791,6 +2821,7 @@ static const char * const mmc_groups[] = { "mmc_ds", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const msiof0_groups[] = { "msiof0_clk", "msiof0_sync", @@ -2844,11 +2875,13 @@ static const char * const msiof5_groups[] = { "msiof5_txd", "msiof5_rxd", }; +#endif static const char * const pcie_groups[] = { "pcie0_clkreq_n", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const pwm0_groups[] = { "pwm0_a", "pwm0_b", @@ -2875,6 +2908,7 @@ static const char * const pwm3_groups[] = { static const char * const pwm4_groups[] = { "pwm4", }; +#endif static const char * const qspi0_groups[] = { "qspi0_ctrl", @@ -2926,10 +2960,12 @@ static const char * const scif_clk2_groups[] = { "scif_clk2", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const ssi_groups[] = { "ssi_data", "ssi_ctrl", }; +#endif static const char * const tpu_groups[] = { "tpu_to0_a", @@ -2943,17 +2979,21 @@ static const char * const tpu_groups[] = { }; static const struct sh_pfc_function pinmux_functions[] = { +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(audio_clk), +#endif SH_PFC_FUNCTION(avb0), SH_PFC_FUNCTION(avb1), SH_PFC_FUNCTION(avb2), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(canfd0), SH_PFC_FUNCTION(canfd1), SH_PFC_FUNCTION(canfd2), SH_PFC_FUNCTION(canfd3), SH_PFC_FUNCTION(can_clk), +#endif SH_PFC_FUNCTION(hscif0), SH_PFC_FUNCTION(hscif1), @@ -2965,24 +3005,30 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(i2c2), SH_PFC_FUNCTION(i2c3), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(intc_ex), +#endif SH_PFC_FUNCTION(mmc), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(msiof0), SH_PFC_FUNCTION(msiof1), SH_PFC_FUNCTION(msiof2), SH_PFC_FUNCTION(msiof3), SH_PFC_FUNCTION(msiof4), SH_PFC_FUNCTION(msiof5), +#endif SH_PFC_FUNCTION(pcie), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(pwm0), SH_PFC_FUNCTION(pwm1), SH_PFC_FUNCTION(pwm2), SH_PFC_FUNCTION(pwm3), SH_PFC_FUNCTION(pwm4), +#endif SH_PFC_FUNCTION(qspi0), SH_PFC_FUNCTION(qspi1), @@ -2994,7 +3040,9 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(scif_clk), SH_PFC_FUNCTION(scif_clk2), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(ssi), +#endif SH_PFC_FUNCTION(tpu), }; diff --git a/drivers/pinctrl/renesas/pfc.c b/drivers/pinctrl/renesas/pfc.c index 2f6c3b3d1c7..db6be39a528 100644 --- a/drivers/pinctrl/renesas/pfc.c +++ b/drivers/pinctrl/renesas/pfc.c @@ -961,90 +961,50 @@ static int sh_pfc_pinctrl_probe(struct udevice *dev) if (!priv->pfc.regs) return -ENOMEM; -#ifdef CONFIG_PINCTRL_PFC_R8A7790 - if (model == SH_PFC_R8A7790) + if (IS_ENABLED(CONFIG_PINCTRL_PFC_R8A7790) && model == SH_PFC_R8A7790) priv->pfc.info = &r8a7790_pinmux_info; -#endif -#ifdef CONFIG_PINCTRL_PFC_R8A7791 - if (model == SH_PFC_R8A7791) + else if (IS_ENABLED(CONFIG_PINCTRL_PFC_R8A7791) && model == SH_PFC_R8A7791) priv->pfc.info = &r8a7791_pinmux_info; -#endif -#ifdef CONFIG_PINCTRL_PFC_R8A7792 - if (model == SH_PFC_R8A7792) + else if (IS_ENABLED(CONFIG_PINCTRL_PFC_R8A7792) && model == SH_PFC_R8A7792) priv->pfc.info = &r8a7792_pinmux_info; -#endif -#ifdef CONFIG_PINCTRL_PFC_R8A7793 - if (model == SH_PFC_R8A7793) + else if (IS_ENABLED(CONFIG_PINCTRL_PFC_R8A7793) && model == SH_PFC_R8A7793) priv->pfc.info = &r8a7793_pinmux_info; -#endif -#ifdef CONFIG_PINCTRL_PFC_R8A7794 - if (model == SH_PFC_R8A7794) + else if (IS_ENABLED(CONFIG_PINCTRL_PFC_R8A7794) && model == SH_PFC_R8A7794) priv->pfc.info = &r8a7794_pinmux_info; -#endif -#ifdef CONFIG_PINCTRL_PFC_R8A77951 - if (model == SH_PFC_R8A7795) + else if (IS_ENABLED(CONFIG_PINCTRL_PFC_R8A77951) && model == SH_PFC_R8A7795) priv->pfc.info = &r8a77951_pinmux_info; -#endif -#ifdef CONFIG_PINCTRL_PFC_R8A77960 - if (model == SH_PFC_R8A77960) + else if (IS_ENABLED(CONFIG_PINCTRL_PFC_R8A77960) && model == SH_PFC_R8A77960) priv->pfc.info = &r8a77960_pinmux_info; -#endif -#ifdef CONFIG_PINCTRL_PFC_R8A77961 - if (model == SH_PFC_R8A77961) + else if (IS_ENABLED(CONFIG_PINCTRL_PFC_R8A77961) && model == SH_PFC_R8A77961) priv->pfc.info = &r8a77961_pinmux_info; -#endif -#ifdef CONFIG_PINCTRL_PFC_R8A774A1 - if (model == SH_PFC_R8A774A1) + else if (IS_ENABLED(CONFIG_PINCTRL_PFC_R8A774A1) && model == SH_PFC_R8A774A1) priv->pfc.info = &r8a774a1_pinmux_info; -#endif -#ifdef CONFIG_PINCTRL_PFC_R8A774B1 - if (model == SH_PFC_R8A774B1) + else if (IS_ENABLED(CONFIG_PINCTRL_PFC_R8A774B1) && model == SH_PFC_R8A774B1) priv->pfc.info = &r8a774b1_pinmux_info; -#endif -#ifdef CONFIG_PINCTRL_PFC_R8A774C0 - if (model == SH_PFC_R8A774C0) + else if (IS_ENABLED(CONFIG_PINCTRL_PFC_R8A774C0) && model == SH_PFC_R8A774C0) priv->pfc.info = &r8a774c0_pinmux_info; -#endif -#ifdef CONFIG_PINCTRL_PFC_R8A774E1 - if (model == SH_PFC_R8A774E1) + else if (IS_ENABLED(CONFIG_PINCTRL_PFC_R8A774E1) && model == SH_PFC_R8A774E1) priv->pfc.info = &r8a774e1_pinmux_info; -#endif -#ifdef CONFIG_PINCTRL_PFC_R8A77965 - if (model == SH_PFC_R8A77965) + else if (IS_ENABLED(CONFIG_PINCTRL_PFC_R8A77965) && model == SH_PFC_R8A77965) priv->pfc.info = &r8a77965_pinmux_info; -#endif -#ifdef CONFIG_PINCTRL_PFC_R8A77970 - if (model == SH_PFC_R8A77970) + else if (IS_ENABLED(CONFIG_PINCTRL_PFC_R8A77970) && model == SH_PFC_R8A77970) priv->pfc.info = &r8a77970_pinmux_info; -#endif -#ifdef CONFIG_PINCTRL_PFC_R8A77980 - if (model == SH_PFC_R8A77980) + else if (IS_ENABLED(CONFIG_PINCTRL_PFC_R8A77980) && model == SH_PFC_R8A77980) priv->pfc.info = &r8a77980_pinmux_info; -#endif -#ifdef CONFIG_PINCTRL_PFC_R8A77990 - if (model == SH_PFC_R8A77990) + else if (IS_ENABLED(CONFIG_PINCTRL_PFC_R8A77990) && model == SH_PFC_R8A77990) priv->pfc.info = &r8a77990_pinmux_info; -#endif -#ifdef CONFIG_PINCTRL_PFC_R8A77995 - if (model == SH_PFC_R8A77995) + else if (IS_ENABLED(CONFIG_PINCTRL_PFC_R8A77995) && model == SH_PFC_R8A77995) priv->pfc.info = &r8a77995_pinmux_info; -#endif -#ifdef CONFIG_PINCTRL_PFC_R8A779A0 - if (model == SH_PFC_R8A779A0) + else if (IS_ENABLED(CONFIG_PINCTRL_PFC_R8A779A0) && model == SH_PFC_R8A779A0) priv->pfc.info = &r8a779a0_pinmux_info; -#endif -#ifdef CONFIG_PINCTRL_PFC_R8A779F0 - if (model == SH_PFC_R8A779F0) + else if (IS_ENABLED(CONFIG_PINCTRL_PFC_R8A779F0) && model == SH_PFC_R8A779F0) priv->pfc.info = &r8a779f0_pinmux_info; -#endif -#ifdef CONFIG_PINCTRL_PFC_R8A779G0 - if (model == SH_PFC_R8A779G0) + else if (IS_ENABLED(CONFIG_PINCTRL_PFC_R8A779G0) && model == SH_PFC_R8A779G0) priv->pfc.info = &r8a779g0_pinmux_info; -#endif -#ifdef CONFIG_PINCTRL_PFC_R8A779H0 - if (model == SH_PFC_R8A779H0) + else if (IS_ENABLED(CONFIG_PINCTRL_PFC_R8A779H0) && model == SH_PFC_R8A779H0) priv->pfc.info = &r8a779h0_pinmux_info; -#endif + else + return -ENODEV; priv->pmx.pfc = &priv->pfc; sh_pfc_init_ranges(&priv->pfc); @@ -1054,127 +1014,127 @@ static int sh_pfc_pinctrl_probe(struct udevice *dev) } static const struct udevice_id sh_pfc_pinctrl_ids[] = { -#ifdef CONFIG_PINCTRL_PFC_R8A7790 +#if IS_ENABLED(CONFIG_PINCTRL_PFC_R8A7790) { .compatible = "renesas,pfc-r8a7790", .data = SH_PFC_R8A7790, }, #endif -#ifdef CONFIG_PINCTRL_PFC_R8A7791 +#if IS_ENABLED(CONFIG_PINCTRL_PFC_R8A7791) { .compatible = "renesas,pfc-r8a7791", .data = SH_PFC_R8A7791, }, #endif -#ifdef CONFIG_PINCTRL_PFC_R8A7792 +#if IS_ENABLED(CONFIG_PINCTRL_PFC_R8A7792) { .compatible = "renesas,pfc-r8a7792", .data = SH_PFC_R8A7792, }, #endif -#ifdef CONFIG_PINCTRL_PFC_R8A7793 +#if IS_ENABLED(CONFIG_PINCTRL_PFC_R8A7793) { .compatible = "renesas,pfc-r8a7793", .data = SH_PFC_R8A7793, }, #endif -#ifdef CONFIG_PINCTRL_PFC_R8A7794 +#if IS_ENABLED(CONFIG_PINCTRL_PFC_R8A7794) { .compatible = "renesas,pfc-r8a7794", .data = SH_PFC_R8A7794, }, #endif -#ifdef CONFIG_PINCTRL_PFC_R8A77951 +#if IS_ENABLED(CONFIG_PINCTRL_PFC_R8A77951) { .compatible = "renesas,pfc-r8a7795", .data = SH_PFC_R8A7795, }, #endif -#ifdef CONFIG_PINCTRL_PFC_R8A77960 +#if IS_ENABLED(CONFIG_PINCTRL_PFC_R8A77960) { .compatible = "renesas,pfc-r8a7796", .data = SH_PFC_R8A77960, }, #endif -#ifdef CONFIG_PINCTRL_PFC_R8A77961 +#if IS_ENABLED(CONFIG_PINCTRL_PFC_R8A77961) { .compatible = "renesas,pfc-r8a77961", .data = SH_PFC_R8A77961, }, #endif -#ifdef CONFIG_PINCTRL_PFC_R8A774A1 +#if IS_ENABLED(CONFIG_PINCTRL_PFC_R8A774A1) { .compatible = "renesas,pfc-r8a774a1", .data = SH_PFC_R8A774A1, }, #endif -#ifdef CONFIG_PINCTRL_PFC_R8A774B1 +#if IS_ENABLED(CONFIG_PINCTRL_PFC_R8A774B1) { .compatible = "renesas,pfc-r8a774b1", .data = SH_PFC_R8A774B1, }, #endif -#ifdef CONFIG_PINCTRL_PFC_R8A774C0 +#if IS_ENABLED(CONFIG_PINCTRL_PFC_R8A774C0) { .compatible = "renesas,pfc-r8a774c0", .data = SH_PFC_R8A774C0, }, #endif -#ifdef CONFIG_PINCTRL_PFC_R8A774E1 +#if IS_ENABLED(CONFIG_PINCTRL_PFC_R8A774E1) { .compatible = "renesas,pfc-r8a774e1", .data = SH_PFC_R8A774E1, }, #endif -#ifdef CONFIG_PINCTRL_PFC_R8A77965 +#if IS_ENABLED(CONFIG_PINCTRL_PFC_R8A77965) { .compatible = "renesas,pfc-r8a77965", .data = SH_PFC_R8A77965, }, #endif -#ifdef CONFIG_PINCTRL_PFC_R8A77970 +#if IS_ENABLED(CONFIG_PINCTRL_PFC_R8A77970) { .compatible = "renesas,pfc-r8a77970", .data = SH_PFC_R8A77970, }, #endif -#ifdef CONFIG_PINCTRL_PFC_R8A77980 +#if IS_ENABLED(CONFIG_PINCTRL_PFC_R8A77980) { .compatible = "renesas,pfc-r8a77980", .data = SH_PFC_R8A77980, }, #endif -#ifdef CONFIG_PINCTRL_PFC_R8A77990 +#if IS_ENABLED(CONFIG_PINCTRL_PFC_R8A77990) { .compatible = "renesas,pfc-r8a77990", .data = SH_PFC_R8A77990, }, #endif -#ifdef CONFIG_PINCTRL_PFC_R8A77995 +#if IS_ENABLED(CONFIG_PINCTRL_PFC_R8A77995) { .compatible = "renesas,pfc-r8a77995", .data = SH_PFC_R8A77995, }, #endif -#ifdef CONFIG_PINCTRL_PFC_R8A779A0 +#if IS_ENABLED(CONFIG_PINCTRL_PFC_R8A779A0) { .compatible = "renesas,pfc-r8a779a0", .data = SH_PFC_R8A779A0, }, #endif -#ifdef CONFIG_PINCTRL_PFC_R8A779F0 +#if IS_ENABLED(CONFIG_PINCTRL_PFC_R8A779F0) { .compatible = "renesas,pfc-r8a779f0", .data = SH_PFC_R8A779F0, }, #endif -#ifdef CONFIG_PINCTRL_PFC_R8A779G0 +#if IS_ENABLED(CONFIG_PINCTRL_PFC_R8A779G0) { .compatible = "renesas,pfc-r8a779g0", .data = SH_PFC_R8A779G0, }, #endif -#ifdef CONFIG_PINCTRL_PFC_R8A779H0 +#if IS_ENABLED(CONFIG_PINCTRL_PFC_R8A779H0) { .compatible = "renesas,pfc-r8a779h0", .data = SH_PFC_R8A779H0, diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig index f7e357f24da..2b0cd312883 100644 --- a/drivers/ram/Kconfig +++ b/drivers/ram/Kconfig @@ -119,6 +119,7 @@ config IMXRT_SDRAM source "drivers/ram/aspeed/Kconfig" source "drivers/ram/cadence/Kconfig" source "drivers/ram/octeon/Kconfig" +source "drivers/ram/renesas/Kconfig" source "drivers/ram/rockchip/Kconfig" source "drivers/ram/sifive/Kconfig" source "drivers/ram/stm32mp1/Kconfig" diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c b/drivers/ram/k3-ddrss/k3-ddrss.c index 525b6d5b79f..6e9202b9579 100644 --- a/drivers/ram/k3-ddrss/k3-ddrss.c +++ b/drivers/ram/k3-ddrss/k3-ddrss.c @@ -216,9 +216,6 @@ static void k3_lpddr4_freq_update(struct k3_ddrss_desc *ddrss) req_type = readl(ddrss->ddrss_ctrl_mmr + CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS + ddrss->instance * 0x10) & 0x03; - debug("%s: received freq change req: req type = %d, req no. = %d, instance = %d\n", - __func__, req_type, counter, ddrss->instance); - if (req_type == 1) clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq1); else if (req_type == 2) @@ -245,8 +242,6 @@ static void k3_lpddr4_ack_freq_upd_req(const lpddr4_privatedata *pd) { struct k3_ddrss_desc *ddrss = (struct k3_ddrss_desc *)pd->ddr_instance; - debug("--->>> LPDDR4 Initialization is in progress ... <<<---\n"); - switch (ddrss->dram_class) { case DENALI_CTL_0_DRAM_CLASS_DDR4: break; diff --git a/drivers/ram/renesas/Kconfig b/drivers/ram/renesas/Kconfig new file mode 100644 index 00000000000..6a1ef2a0c63 --- /dev/null +++ b/drivers/ram/renesas/Kconfig @@ -0,0 +1,7 @@ +config RAM_RENESAS_DBSC5 + bool "Renesas R-Car V4H/V4M DBSC5 controller driver" + depends on SPL && RAM && (R8A779G0 || R8A779H0) + default n + help + Enable this to support the DBSC5 DRAM controller initialization + on Renesas R8A779G0/R8A779H0 SoCs. diff --git a/drivers/ram/renesas/Makefile b/drivers/ram/renesas/Makefile index 705cc4b6fa5..578d05622d7 100644 --- a/drivers/ram/renesas/Makefile +++ b/drivers/ram/renesas/Makefile @@ -1,3 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ +ifdef CONFIG_XPL_BUILD +obj-$(CONFIG_RAM_RENESAS_DBSC5) += dbsc5/ +endif obj-$(CONFIG_RZN1) += rzn1/ diff --git a/drivers/ram/renesas/dbsc5/Makefile b/drivers/ram/renesas/dbsc5/Makefile new file mode 100644 index 00000000000..177be893e10 --- /dev/null +++ b/drivers/ram/renesas/dbsc5/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y += dbsc5.o dram.o qos.o rtvram.o diff --git a/drivers/ram/renesas/dbsc5/dbsc5.c b/drivers/ram/renesas/dbsc5/dbsc5.c new file mode 100644 index 00000000000..d24b7c5c30a --- /dev/null +++ b/drivers/ram/renesas/dbsc5/dbsc5.c @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +#include <asm/io.h> +#include <dm.h> +#include <dm/device-internal.h> +#include <dm/lists.h> +#include <errno.h> +#include <linux/sizes.h> +#include <ram.h> +#include "dbsc5.h" + +static int renesas_dbsc5_probe(struct udevice *dev) +{ + struct udevice *pdev; + int ret; + + ret = uclass_get_device_by_name(UCLASS_RAM, "dbsc5_dram", &pdev); + if (ret) + return ret; + + ret = uclass_get_device_by_name(UCLASS_NOP, "dbsc5_qos", &pdev); + if (ret) + return ret; + + return 0; +} + +int renesas_dbsc5_bind(struct udevice *dev) +{ + struct udevice *ramdev, *qosdev; + struct driver *ramdrv, *qosdrv; + int ret; + + ramdrv = lists_driver_lookup_name("dbsc5_dram"); + if (!ramdrv) + return -ENOENT; + + + qosdrv = lists_driver_lookup_name("dbsc5_qos"); + if (!qosdrv) + return -ENOENT; + + ret = device_bind_with_driver_data(dev, ramdrv, "dbsc5_dram", + dev_get_driver_data(dev), + dev_ofnode(dev), &ramdev); + if (ret) + return ret; + + ret = device_bind_with_driver_data(dev, qosdrv, "dbsc5_qos", 0, + dev_ofnode(dev), &qosdev); + if (ret) + device_unbind(ramdev); + + return ret; +} + +struct renesas_dbsc5_data r8a779g0_dbsc5_data = { + .clock_node = "renesas,r8a779g0-cpg-mssr", + .reset_node = "renesas,r8a779g0-rst" +}; + +static const struct udevice_id renesas_dbsc5_ids[] = { + { + .compatible = "renesas,r8a779g0-dbsc", + .data = (ulong)&r8a779g0_dbsc5_data + }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(renesas_dbsc5) = { + .name = "dbsc5", + .id = UCLASS_NOP, + .of_match = renesas_dbsc5_ids, + .bind = renesas_dbsc5_bind, + .probe = renesas_dbsc5_probe, +}; diff --git a/drivers/ram/renesas/dbsc5/dbsc5.h b/drivers/ram/renesas/dbsc5/dbsc5.h new file mode 100644 index 00000000000..c410eb0c5ed --- /dev/null +++ b/drivers/ram/renesas/dbsc5/dbsc5.h @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +#ifndef __DRIVERS_RAM_RENESAS_DBSC5_DBSC5_H__ +#define __DRIVERS_RAM_RENESAS_DBSC5_DBSC5_H__ + +/* + * DBSC5 ... 0xe678_0000..0xe67fffff + * - AXMM_BASE 0xe6780000 MM (DDR Hier) MM AXI Router - Region 0 + * - DBSC_A_BASE 0xe6790000 MM (DDR Hier) DBSC0A - Region 0 + * - CCI_BASE 0xe67A0000 MM (DDR Hier) FBA for MM + * - DBSC_D_BASE 0xE67A4000 MM (DDR Hier) DBSC0D - Region 0 + * - QOS_BASE 0xe67E0000 MM (DDR Hier) M-STATQ (64kiB) + */ +#define DBSC5_AXMM_OFFSET 0x00000 +#define DBSC5_DBSC_A_OFFSET 0x10000 +#define DBSC5_CCI_OFFSET 0x20000 +#define DBSC5_DBSC_D_OFFSET 0x24000 +#define DBSC5_QOS_OFFSET 0x60000 + +struct renesas_dbsc5_data { + const char *clock_node; + const char *reset_node; +}; + +#endif /* __DRIVERS_RAM_RENESAS_DBSC5_DBSC5_H__ */ diff --git a/drivers/ram/renesas/dbsc5/dram.c b/drivers/ram/renesas/dbsc5/dram.c new file mode 100644 index 00000000000..210a68f6496 --- /dev/null +++ b/drivers/ram/renesas/dbsc5/dram.c @@ -0,0 +1,4532 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +#include <asm/io.h> +#include <dm.h> +#include <errno.h> +#include <hang.h> +#include <ram.h> +#include <linux/iopoll.h> +#include <linux/sizes.h> +#include "dbsc5.h" + +/* The number of channels V4H has */ +#define DRAM_CH_CNT 4 +/* The number of slices V4H has */ +#define SLICE_CNT 2 +/* The number of chip select V4H has */ +#define CS_CNT 2 + +/* Number of array elements in Data Slice */ +#define DDR_PHY_SLICE_REGSET_SIZE_V4H 0x100 +/* Number of array elements in Data Slice */ +#define DDR_PHY_SLICE_REGSET_NUM_V4H 153 +/* Number of array elements in Address Slice */ +#define DDR_PHY_ADR_V_REGSET_NUM_V4H 61 +/* Number of array elements in Address Control Slice */ +#define DDR_PHY_ADR_G_REGSET_NUM_V4H 97 +/* Number of array elements in PI Register */ +#define DDR_PI_REGSET_NUM_V4H 1381 + +/* Minimum value table for JS1 configuration table that can be taken */ +#define JS1_USABLEC_SPEC_LO 5 +/* Maximum value table for JS1 configuration table that can be taken */ +#define JS1_USABLEC_SPEC_HI 11 +/* The number of JS1 setting table */ +#define JS1_FREQ_TBL_NUM 12 +/* Macro to set the value of MR1 */ +#define JS1_MR1(f) (((f) << 4) | 0x00) /* CK mode = 0B */ +/* Macro to set the value of MR2 */ +#define JS1_MR2(f) (((f) << 4) | (f)) + +#define JS2_tSR 0 /* Element for self refresh */ +#define JS2_tXP 1 /* Exit power-down mode to first valid command */ +#define JS2_tRCD 2 /* Active to read or write delay */ +#define JS2_tRPpb 3 /* Minimum Row Precharge Delay Time */ +#define JS2_tRPab 4 /* Minimum Row Precharge Delay Time */ +#define JS2_tRAS 5 /* ACTIVE-to-PRECHARGE command */ +#define JS2_tWTR_S 6 /* Internal WRITE-to-READ command delay */ +#define JS2_tWTR_L 7 /* Internal WRITE-to-READ command delay */ +#define JS2_tRRD 8 /* Active bank a to active bank b command */ +#define JS2_tPPD 9 /* Precharge Power Down */ +#define JS2_tFAW 10 /* Four bank ACT window */ +#define JS2_tMRR 11 /* Mode Register Read */ +#define JS2_tMRW 12 /* Mode Register Write */ +#define JS2_tMRD 13 /* LOAD MODE REGISTER command cycle time */ +#define JS2_tZQCALns 14 /* ZQ Calibration */ +#define JS2_tZQLAT 15 /* ZQ Latency */ +#define JS2_tODTon_min 16 /* Minimum time on die termination */ +#define JS2_tPDN_DSM 17 /* Recommended minimum time for Deep Sleep Mode duration */ +#define JS2_tXSR_DSM 18 /* Required time to be fully re-powered up from Deep Sleep Mode */ +#define JS2_tXDSM_XP 19 /* Delay from Deep Sleep Mode Exit to Power-Down Exit */ +#define JS2_tWCK2DQI_HF 20 /* Setting value of DQ to WCK input offset */ +#define JS2_tWCK2DQO_HF 21 /* Setting value of WCK to DQ output offset */ +#define JS2_tWCK2DQI_LF 22 /* Setting value of DQ to WCK input offset */ +#define JS2_tWCK2DQO_LF 23 /* Setting value of WCK to DQ output offset */ +#define JS2_tOSCODQI 24 /* Delay time from Stop WCK2DQI Interval Oscillator command to Mode Register Readout */ +#define JS2_tDQ72DQns 25 /* Reception time to change the value fof REF(CA) for Command Bus Training Mode2 */ +#define JS2_tCAENTns 26 /* Reception time to change the value fof REF(CA) for Command Bus Training Mode1 */ +#define JS2_tCSCAL 27 /* Minimum CA Low Duration time */ +#define JS2_TBLCNT 28 /* The number of table */ + +#define JS2_tRCpb JS2_TBLCNT /* ACTIVATE-to-ACTIVATE command period with per bank precharge */ +#define JS2_tRCab (JS2_TBLCNT + 1) /* ACTIVATE-to-ACTIVATE command period with all bank precharge */ +#define JS2_tRFCab (JS2_TBLCNT + 2) /* Refresh Cycle Time with All Banks */ +#define JS2_tRBTP (JS2_TBLCNT + 3) /* READ Burst end to PRECHARGE command delay */ +#define JS2_tXSR (JS2_TBLCNT + 4) /* Exit Self Refresh to Valid commands */ +#define JS2_tPDN (JS2_TBLCNT + 5) +#define JS2_tWLWCKOFF (JS2_TBLCNT + 6) +#define JS2_CNT (JS2_TBLCNT + 7) + +struct jedec_spec1 { + u32 fx3; /* Frequency */ + u8 RLset1; /* setting value of Read Latency */ + u8 RLset2; /* setting value of Read Latency */ + u8 WLsetA; /* setting value of Write Latency */ + u8 WLsetB; /* setting value of Write Latency */ + u32 nWR; /* Write-Recovery for Auto-Precharge commands */ + u32 nRBTP; /* the minimum interval from a READ command to a PRE command */ + u32 ODTLon; /* On Die Termination */ + u8 MR1; /* Mode Register 1 */ + u8 MR2; /* Mode Register 2 */ + u32 WCKENLR; /* The setting time from CAS command to the Start-up of WCK in READ operation */ + u32 WCKENLW; /* The setting time from CAS command to the Start-up of WCK in WRITE operation */ + u32 WCKENLF; /* The setting time from CAS command to the Start-up of WCK in FAST-sync operation */ + u32 WCKPRESTA; /* The setting time from the Start-up of WCK to WCK Clocling Start */ + u32 WCKPRETGLR; /* The setting time from WCK Clocling Start to Reflecting frequency of WCK */ +}; + +static const struct jedec_spec1 js1[JS1_FREQ_TBL_NUM] = { + /* fx3, RL1, RL2, WLA.WLB.nWR.nRBTP, ODTLon */ + { 800, 3, 3, 2, 2, 3, 0, 1, JS1_MR1(0), JS1_MR2(0), 0, 0, 0, 1, 3 }, /* 533.333Mbps*/ + { 1600, 4, 4, 2, 3, 5, 0, 1, JS1_MR1(1), JS1_MR2(1), 0, 0, 0, 1, 4 }, /* 1066.666Mbps*/ + { 2400, 5, 6, 3, 4, 7, 0, 2, JS1_MR1(2), JS1_MR2(2), 1, 1, 1, 1, 4 }, /* 1600.000Mbps*/ + { 3200, 7, 7, 4, 5, 10, 0, 2, JS1_MR1(3), JS1_MR2(3), 2, 1, 1, 2, 4 }, /* 2133.333Mbps*/ + { 4000, 8, 9, 4, 7, 12, 1, 2, JS1_MR1(4), JS1_MR2(4), 2, 1, 1, 2, 5 }, /* 2666.666Mbps*/ + { 4800, 10, 10, 5, 8, 14, 1, 3, JS1_MR1(5), JS1_MR2(5), 4, 2, 1, 2, 5 }, /* 3200.000Mbps*/ + { 5600, 11, 12, 6, 9, 16, 2, 4, JS1_MR1(6), JS1_MR2(6), 4, 2, 1, 3, 5 }, /* 3733.333Mbps*/ + { 6400, 13, 14, 6, 11, 19, 2, 3, JS1_MR1(7), JS1_MR2(7), 5, 2, 1, 3, 6 }, /* 4266.666Mbps*/ + { 7200, 14, 15, 7, 12, 21, 3, 4, JS1_MR1(8), JS1_MR2(8), 6, 3, 2, 3, 6 }, /* 4800.000Mbps*/ + { 8250, 16, 17, 8, 14, 24, 4, 5, JS1_MR1(9), JS1_MR2(9), 7, 3, 2, 4, 6 }, /* 5500.000Mbps*/ + { 9000, 17, 19, 9, 15, 26, 4, 6, JS1_MR1(10), JS1_MR2(10), 7, 4, 2, 4, 7 }, /* 6000.000Mbps*/ + { 9600, 18, 20, 9, 16, 28, 4, 6, JS1_MR1(11), JS1_MR2(11), 8, 4, 2, 4, 7 } /* 6400.000Mbps*/ +}; + +struct jedec_spec2 { + u16 ps; /* Value in pico seconds */ + u16 cyc; /* Value in cycle count */ +}; + +static const struct jedec_spec2 jedec_spec2[2][JS2_TBLCNT] = { + { + { 15000, 2 }, /* tSR */ + { 7000, 3 }, /* tXP */ + { 18000, 2 }, /* tRCD */ + { 18000, 2 }, /* tRPpb */ + { 21000, 2 }, /* tRPab */ + { 42000, 3 }, /* tRAS */ + { 6250, 4 }, /* tWTR_S */ + { 12000, 4 }, /* tWTR_L */ + { 5000, 2 }, /* tRRD */ + { 0, 2 }, /* tPPD */ + { 20000, 0 }, /* tFAW */ + { 0, 4 }, /* tMRR */ + { 10000, 5 }, /* tMRW */ + { 14000, 5 }, /* tMRD */ + { 1500, 0 }, /* tZQCALns */ + { 30000, 4 }, /* tZQLAT */ + { 1500, 0 }, /* tODTon_min */ + { 4000, 0 }, /* tPDN_DSMus */ + { 200, 0 }, /* tXSR_DSMus */ + { 190, 0 }, /* tXDSM_XPus */ + { 700, 0 }, /* tWCK2DQI_HF */ + { 1600, 0 }, /* tWCK2DQO_HF */ + { 900, 0 }, /* tWCK2DQI_LF */ + { 1900, 0 }, /* tWCK2DQO_LF */ + { 40000, 8 }, /* tOSCODQI */ + { 125, 0 }, /* tDQ72DQns */ + { 250, 0 }, /* tCAENTns */ + { 1750, 0 } /* tCSCAL */ + }, { + { 15000, 2 }, /* tSR */ + { 7000, 3 }, /* tXP */ + { 19875, 2 }, /* tRCD */ + { 19875, 2 }, /* tRPpb */ + { 22875, 2 }, /* tRPab */ + { 43875, 3 }, /* tRAS */ + { 6250, 4 }, /* tWTR_S */ + { 12000, 4 }, /* tWTR_L */ + { 5000, 2 }, /* tRRD */ + { 0, 2 }, /* tPPD */ + { 20000, 0 }, /* tFAW */ + { 0, 4 }, /* tMRR */ + { 10000, 5 }, /* tMRW */ + { 14000, 5 }, /* tMRD */ + { 1500, 0 }, /* tZQCALns */ + { 30000, 4 }, /* tZQLAT */ + { 1500, 0 }, /* tODTon_min */ + { 4000, 0 }, /* tPDN_DSMus */ + { 200, 0 }, /* tXSR_DSMus */ + { 190, 0 }, /* tXDSM_XPus */ + { 715, 0 }, /* tWCK2DQI_HF */ + { 1635, 0 }, /* tWCK2DQO_HF */ + { 920, 0 }, /* tWCK2DQI_LF */ + { 1940, 0 }, /* tWCK2DQO_LF */ + { 40000, 8 }, /* tOSCODQI */ + { 125, 0 }, /* tDQ72DQns */ + { 250, 0 }, /* tCAENTns */ + { 1750, 0 } /* tCSCAL */ + } +}; + +static const u16 jedec_spec2_tRFC_ab[] = { + /* 2Gb, 3Gb, 4Gb, 6Gb, 8Gb, 12Gb, 16Gb, 24Gb, 32Gb */ + 130, 180, 180, 210, 210, 280, 280, 380, 380 +}; + +/* The address offsets of PI Register */ +#define DDR_PI_REGSET_OFS_V4H 0x0800 +/* The address offsets of Data Slice */ +#define DDR_PHY_SLICE_REGSET_OFS_V4H 0x1000 +/* The address offsets of Address Slice */ +#define DDR_PHY_ADR_V_REGSET_OFS_V4H 0x1200 +/* The address offsets of Address Control Slice */ +#define DDR_PHY_ADR_G_REGSET_OFS_V4H 0x1300 + +#define DDR_REGDEF_ADR(regdef) ((regdef) & 0xFFFF) +#define DDR_REGDEF_LEN(regdef) (((regdef) >> 16) & 0xFF) +#define DDR_REGDEF_LSB(regdef) (((regdef) >> 24) & 0xFF) + +#define DDR_REGDEF(lsb, len, adr) \ + (((lsb) << 24) | ((len) << 16) | (adr)) + +#define PHY_LP4_BOOT_RX_PCLK_CLK_SEL DDR_REGDEF(0x10, 0x03, 0x1000) +#define PHY_PER_CS_TRAINING_MULTICAST_EN DDR_REGDEF(0x10, 0x01, 0x1006) +#define PHY_PER_CS_TRAINING_INDEX DDR_REGDEF(0x18, 0x01, 0x1006) +#define PHY_VREF_INITIAL_STEPSIZE DDR_REGDEF(0x18, 0x08, 0x100D) +#define PHY_RDLVL_BEST_THRSHLD DDR_REGDEF(0x00, 0x04, 0x100E) +#define PHY_RDLVL_VREF_OUTLIER DDR_REGDEF(0x10, 0x03, 0x100E) +#define SC_PHY_WCK_CALC DDR_REGDEF(0x18, 0x01, 0x101A) +#define PHY_RDLVL_RDDQS_DQ_OBS_SELECT DDR_REGDEF(0x10, 0x05, 0x102C) +#define PHY_CALVL_VREF_DRIVING_SLICE DDR_REGDEF(0x18, 0x01, 0x1030) +#define PHY_WRLVL_HARD0_DELAY_OBS DDR_REGDEF(0x00, 0x0A, 0x1038) +#define PHY_WRLVL_HARD1_DELAY_OBS DDR_REGDEF(0x10, 0x0A, 0x1038) +#define PHY_WRLVL_STATUS_OBS DDR_REGDEF(0x00, 0x1C, 0x1039) +#define PHY_WRLVL_ERROR_OBS DDR_REGDEF(0x00, 0x10, 0x103B) +#define PHY_GTLVL_STATUS_OBS DDR_REGDEF(0x00, 0x12, 0x103D) +#define PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS DDR_REGDEF(0x10, 0x09, 0x103E) +#define PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS DDR_REGDEF(0x00, 0x09, 0x103F) +#define PHY_WDQLVL_STATUS_OBS DDR_REGDEF(0x00, 0x20, 0x1043) +#define PHY_DATA_DC_CAL_START DDR_REGDEF(0x18, 0x01, 0x104D) +#define PHY_REGULATOR_EN_CNT DDR_REGDEF(0x18, 0x06, 0x1050) +#define PHY_VREF_INITIAL_START_POINT DDR_REGDEF(0x00, 0x09, 0x1055) +#define PHY_VREF_INITIAL_STOP_POINT DDR_REGDEF(0x10, 0x09, 0x1055) +#define PHY_VREF_TRAINING_CTRL DDR_REGDEF(0x00, 0x02, 0x1056) +#define PHY_RDDQ0_SLAVE_DELAY DDR_REGDEF(0x00, 0x09, 0x105D) +#define PHY_RDDQ1_SLAVE_DELAY DDR_REGDEF(0x10, 0x09, 0x105D) +#define PHY_RDDQ2_SLAVE_DELAY DDR_REGDEF(0x00, 0x09, 0x105E) +#define PHY_RDDQ3_SLAVE_DELAY DDR_REGDEF(0x10, 0x09, 0x105E) +#define PHY_RDDQ4_SLAVE_DELAY DDR_REGDEF(0x00, 0x09, 0x105F) +#define PHY_RDDQ5_SLAVE_DELAY DDR_REGDEF(0x10, 0x09, 0x105F) +#define PHY_RDDQ6_SLAVE_DELAY DDR_REGDEF(0x00, 0x09, 0x1060) +#define PHY_RDDQ7_SLAVE_DELAY DDR_REGDEF(0x10, 0x09, 0x1060) +#define PHY_RDDM_SLAVE_DELAY DDR_REGDEF(0x00, 0x09, 0x1061) +#define PHY_RX_CAL_ALL_DLY DDR_REGDEF(0x18, 0x06, 0x1061) +#define PHY_RX_PCLK_CLK_SEL DDR_REGDEF(0x00, 0x03, 0x1062) +#define PHY_DATA_DC_CAL_CLK_SEL DDR_REGDEF(0x18, 0x03, 0x1063) +#define PHY_PAD_VREF_CTRL_DQ DDR_REGDEF(0x00, 0x0E, 0x1067) +#define PHY_PER_CS_TRAINING_EN DDR_REGDEF(0x00, 0x01, 0x1068) +#define PHY_RDDATA_EN_TSEL_DLY DDR_REGDEF(0x18, 0x05, 0x1069) +#define PHY_RDDATA_EN_OE_DLY DDR_REGDEF(0x00, 0x05, 0x106A) +#define PHY_RPTR_UPDATE DDR_REGDEF(0x10, 0x04, 0x106C) +#define PHY_WRLVL_RESP_WAIT_CNT DDR_REGDEF(0x08, 0x06, 0x106D) +#define PHY_RDLVL_DLY_STEP DDR_REGDEF(0x08, 0x04, 0x1070) +#define PHY_RDLVL_MAX_EDGE DDR_REGDEF(0x00, 0x09, 0x1071) +#define PHY_DATA_DC_WDQLVL_ENABLE DDR_REGDEF(0x08, 0x02, 0x1075) +#define PHY_RDDATA_EN_DLY DDR_REGDEF(0x10, 0x05, 0x1076) +#define PHY_MEAS_DLY_STEP_ENABLE DDR_REGDEF(0x08, 0x06, 0x1076) +#define PHY_DQ_DM_SWIZZLE0 DDR_REGDEF(0x00, 0x20, 0x1077) +#define PHY_DQ_DM_SWIZZLE1 DDR_REGDEF(0x00, 0x04, 0x1078) +#define PHY_CLK_WRDQS_SLAVE_DELAY DDR_REGDEF(0x00, 0x09, 0x107E) +#define PHY_WRITE_PATH_LAT_DEC DDR_REGDEF(0x10, 0x01, 0x107E) +#define PHY_RDDQS_GATE_SLAVE_DELAY DDR_REGDEF(0x00, 0x09, 0x1088) +#define PHY_RDDQS_LATENCY_ADJUST DDR_REGDEF(0x10, 0x05, 0x1088) +#define PHY_WRITE_PATH_LAT_ADD DDR_REGDEF(0x18, 0x03, 0x1088) +#define PHY_WRITE_PATH_LAT_FRAC DDR_REGDEF(0x00, 0x08, 0x1089) +#define PHY_GTLVL_LAT_ADJ_START DDR_REGDEF(0x00, 0x05, 0x108A) +#define PHY_DATA_DC_DQS_CLK_ADJUST DDR_REGDEF(0x00, 0x08, 0x108C) +#define PHY_ADR_CALVL_SWIZZLE0 DDR_REGDEF(0x00, 0x20, 0x1202) +#define PHY_ADR_MEAS_DLY_STEP_ENABLE DDR_REGDEF(0x10, 0x01, 0x1203) +#define PHY_ADR_CALVL_RANK_CTRL DDR_REGDEF(0x18, 0x02, 0x1205) +#define PHY_ADR_CALVL_OBS1 DDR_REGDEF(0x00, 0x20, 0x120A) +#define PHY_ADR_CALVL_OBS2 DDR_REGDEF(0x00, 0x20, 0x120B) +#define PHY_ADR_CALVL_DLY_STEP DDR_REGDEF(0x00, 0x04, 0x1210) +#define PHY_CS_ACS_ALLOCATION_BIT2_2 DDR_REGDEF(0x08, 0x02, 0x1215) +#define PHY_CS_ACS_ALLOCATION_BIT3_2 DDR_REGDEF(0x10, 0x02, 0x1215) +#define PHY_CSLVL_OBS1 DDR_REGDEF(0x00, 0x20, 0x1221) +#define PHY_CLK_DC_CAL_CLK_SEL DDR_REGDEF(0x08, 0x03, 0x123A) +#define PHY_FREQ_SEL_MULTICAST_EN DDR_REGDEF(0x08, 0x01, 0x1301) +#define PHY_FREQ_SEL_INDEX DDR_REGDEF(0x10, 0x02, 0x1301) +#define SC_PHY_MANUAL_UPDATE DDR_REGDEF(0x18, 0x01, 0x1304) +#define PHY_SET_DFI_INPUT_RST_PAD DDR_REGDEF(0x18, 0x01, 0x1311) +#define PHY_CAL_MODE_0 DDR_REGDEF(0x00, 0x0D, 0x132C) +#define PHY_CAL_INTERVAL_COUNT_0 DDR_REGDEF(0x00, 0x20, 0x132D) +#define PHY_DATA_BYTE_ORDER_SEL DDR_REGDEF(0x00, 0x20, 0x133E) +#define PHY_PAD_ACS_RX_PCLK_CLK_SEL DDR_REGDEF(0x10, 0x03, 0x1348) +#define PHY_PLL_CTRL DDR_REGDEF(0x00, 0x0E, 0x134B) +#define PHY_PLL_CTRL_8X DDR_REGDEF(0x10, 0x0E, 0x134B) +#define PHY_CAL_CLK_SELECT_0 DDR_REGDEF(0x00, 0x03, 0x1360) + +#define PI_START DDR_REGDEF(0x00, 0x01, 0x0800) +#define PI_TRAIN_ALL_FREQ_REQ DDR_REGDEF(0x18, 0x01, 0x0802) +#define PI_CS_MAP DDR_REGDEF(0x08, 0x02, 0x0813) +#define PI_WRLVL_REQ DDR_REGDEF(0x10, 0x01, 0x081C) +#define PI_WRLVL_CS_SW DDR_REGDEF(0x18, 0x02, 0x081C) +#define PI_RDLVL_REQ DDR_REGDEF(0x18, 0x01, 0x0824) +#define PI_RDLVL_GATE_REQ DDR_REGDEF(0x00, 0x01, 0x0825) +#define PI_RDLVL_CS_SW DDR_REGDEF(0x08, 0x02, 0x0825) +#define PI_RDLVL_PERIODIC DDR_REGDEF(0x08, 0x01, 0x082E) +#define PI_RDLVL_INTERVAL DDR_REGDEF(0x08, 0x10, 0x0835) +#define PI_DRAMDCA_FLIP_MASK DDR_REGDEF(0x08, 0x02, 0x083B) +#define PI_DRAMDCA_LVL_REQ DDR_REGDEF(0x10, 0x01, 0x083D) +#define PI_DCMLVL_CS_SW DDR_REGDEF(0x18, 0x02, 0x083D) +#define PI_WRDCM_LVL_EN_F1 DDR_REGDEF(0x00, 0x02, 0x083F) +#define PI_DRAMDCA_LVL_EN_F1 DDR_REGDEF(0x08, 0x02, 0x083F) +#define PI_WRDCM_LVL_EN_F2 DDR_REGDEF(0x18, 0x02, 0x083F) +#define PI_DRAMDCA_LVL_EN_F2 DDR_REGDEF(0x00, 0x02, 0x0840) +#define PI_DRAMDCA_LVL_ACTIVE_SEQ_2 DDR_REGDEF(0x00, 0x1B, 0x0868) +#define PI_DRAMDCA_LVL_ACTIVE_SEQ_3 DDR_REGDEF(0x00, 0x1B, 0x0869) +#define PI_DRAMDCA_LVL_ACTIVE_SEQ_4 DDR_REGDEF(0x00, 0x1B, 0x086A) +#define PI_TCKCKEL_F2 DDR_REGDEF(0x18, 0x04, 0x089D) +#define PI_WDQLVL_VREF_EN DDR_REGDEF(0x08, 0x04, 0x089E) +#define PI_WDQLVL_PERIODIC DDR_REGDEF(0x00, 0x01, 0x08A0) +#define PI_WDQLVL_INTERVAL DDR_REGDEF(0x00, 0x10, 0x08A4) +#define PI_INT_STATUS DDR_REGDEF(0x00, 0x20, 0x0900) +#define PI_INT_ACK_0 DDR_REGDEF(0x00, 0x20, 0x0902) +#define PI_INT_ACK_1 DDR_REGDEF(0x00, 0x03, 0x0903) +#define PI_LONG_COUNT_MASK DDR_REGDEF(0x10, 0x05, 0x090F) +#define PI_ADDR_MUX_0 DDR_REGDEF(0x00, 0x03, 0x0910) +#define PI_ADDR_MUX_1 DDR_REGDEF(0x08, 0x03, 0x0910) +#define PI_ADDR_MUX_2 DDR_REGDEF(0x10, 0x03, 0x0910) +#define PI_ADDR_MUX_3 DDR_REGDEF(0x18, 0x03, 0x0910) +#define PI_ADDR_MUX_4 DDR_REGDEF(0x00, 0x03, 0x0911) +#define PI_ADDR_MUX_5 DDR_REGDEF(0x08, 0x03, 0x0911) +#define PI_ADDR_MUX_6 DDR_REGDEF(0x10, 0x03, 0x0911) +#define PI_DATA_BYTE_SWAP_EN DDR_REGDEF(0x18, 0x01, 0x0911) +#define PI_DATA_BYTE_SWAP_SLICE0 DDR_REGDEF(0x00, 0x01, 0x0912) +#define PI_DATA_BYTE_SWAP_SLICE1 DDR_REGDEF(0x08, 0x01, 0x0912) +#define PI_PWRUP_SREFRESH_EXIT DDR_REGDEF(0x18, 0x01, 0x093D) +#define PI_PWRUP_SREFRESH_EXIT DDR_REGDEF(0x18, 0x01, 0x093D) +#define PI_DLL_RST DDR_REGDEF(0x00, 0x01, 0x0941) +#define PI_TDELAY_RDWR_2_BUS_IDLE_F2 DDR_REGDEF(0x00, 0x08, 0x0964) +#define PI_WRLAT_F2 DDR_REGDEF(0x10, 0x07, 0x096A) +#define PI_TWCKENL_WR_ADJ_F2 DDR_REGDEF(0x18, 0x06, 0x096A) +#define PI_TWCKENL_RD_ADJ_F2 DDR_REGDEF(0x00, 0x06, 0x096B) +#define PI_TWCKPRE_STATIC_F2 DDR_REGDEF(0x08, 0x06, 0x096B) +#define PI_TWCKPRE_TOGGLE_RD_F2 DDR_REGDEF(0x18, 0x06, 0x096B) +#define PI_TWCKENL_FS_ADJ_F2 DDR_REGDEF(0x00, 0x06, 0x096C) +#define PI_CASLAT_F2 DDR_REGDEF(0x08, 0x07, 0x096C) +#define PI_TRFC_F2 DDR_REGDEF(0x00, 0x0A, 0x0971) +#define PI_TREF_F2 DDR_REGDEF(0x00, 0x14, 0x0972) +#define PI_TDFI_WRLVL_WW_F0 DDR_REGDEF(0x00, 0x0A, 0x0974) +#define PI_TDFI_WRLVL_WW_F1 DDR_REGDEF(0x00, 0x0A, 0x0975) +#define PI_WRLVL_EN_F2 DDR_REGDEF(0x18, 0x02, 0x0975) +#define PI_TDFI_WRLVL_WW_F2 DDR_REGDEF(0x00, 0x0A, 0x0976) +#define PI_WRLVL_WCKOFF_F2 DDR_REGDEF(0x10, 0x08, 0x0976) +#define PI_RDLVL_EN_F2 DDR_REGDEF(0x18, 0x02, 0x097A) +#define PI_RDLVL_GATE_EN_F2 DDR_REGDEF(0x00, 0x02, 0x097B) +#define PI_RDLVL_VREF_EN_F0 DDR_REGDEF(0x10, 0x04, 0x097B) +#define PI_RDLVL_VREF_EN_F1 DDR_REGDEF(0x00, 0x04, 0x097D) +#define PI_RDLVL_VREF_EN_F2 DDR_REGDEF(0x10, 0x04, 0x097E) +#define PI_RDLAT_ADJ_F2 DDR_REGDEF(0x00, 0x09, 0x0981) +#define PI_WRLAT_ADJ_F2 DDR_REGDEF(0x00, 0x07, 0x0982) +#define PI_TDFI_CALVL_CC_F2 DDR_REGDEF(0x00, 0x0A, 0x0985) +#define PI_TDFI_CALVL_CAPTURE_F2 DDR_REGDEF(0x10, 0x0A, 0x0985) +#define PI_CALVL_EN_F2 DDR_REGDEF(0x10, 0x02, 0x0986) +#define PI_TCAENT_F2 DDR_REGDEF(0x00, 0x0E, 0x0989) +#define PI_TVREF_SHORT_F2 DDR_REGDEF(0x00, 0x0A, 0x098F) +#define PI_TVREF_LONG_F2 DDR_REGDEF(0x10, 0x0A, 0x098F) +#define PI_TVRCG_ENABLE_F2 DDR_REGDEF(0x00, 0x0A, 0x0990) +#define PI_TVRCG_DISABLE_F2 DDR_REGDEF(0x10, 0x0A, 0x0990) +#define PI_CALVL_VREF_INITIAL_START_POINT_F0 DDR_REGDEF(0x00, 0x07, 0x0991) +#define PI_CALVL_VREF_INITIAL_STOP_POINT_F0 DDR_REGDEF(0x08, 0x07, 0x0991) +#define PI_CALVL_VREF_INITIAL_START_POINT_F1 DDR_REGDEF(0x18, 0x07, 0x0991) +#define PI_CALVL_VREF_INITIAL_STOP_POINT_F1 DDR_REGDEF(0x00, 0x07, 0x0992) +#define PI_CALVL_VREF_INITIAL_START_POINT_F2 DDR_REGDEF(0x10, 0x07, 0x0992) +#define PI_CALVL_VREF_INITIAL_STOP_POINT_F2 DDR_REGDEF(0x18, 0x07, 0x0992) +#define PI_TDFI_CALVL_STROBE_F2 DDR_REGDEF(0x08, 0x04, 0x0995) +#define PI_TXP_F2 DDR_REGDEF(0x10, 0x05, 0x0995) +#define PI_TMRWCKEL_F2 DDR_REGDEF(0x18, 0x08, 0x0995) +#define PI_TCKEHDQS_F2 DDR_REGDEF(0x10, 0x06, 0x099D) +#define PI_TFC_F2 DDR_REGDEF(0x00, 0x0A, 0x099E) +#define PI_WDQLVL_VREF_INITIAL_START_POINT_F0 DDR_REGDEF(0x10, 0x07, 0x09A0) +#define PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0 DDR_REGDEF(0x18, 0x07, 0x09A0) +#define PI_WDQLVL_VREF_INITIAL_START_POINT_F1 DDR_REGDEF(0x00, 0x07, 0x09A4) +#define PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1 DDR_REGDEF(0x08, 0x07, 0x09A4) +#define PI_TDFI_WDQLVL_WR_F2 DDR_REGDEF(0x00, 0x0A, 0x09A6) +#define PI_TDFI_WDQLVL_RW_F2 DDR_REGDEF(0x10, 0x0A, 0x09A6) +#define PI_WDQLVL_VREF_INITIAL_START_POINT_F2 DDR_REGDEF(0x00, 0x07, 0x09A7) +#define PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2 DDR_REGDEF(0x08, 0x07, 0x09A7) +#define PI_WDQLVL_EN_F2 DDR_REGDEF(0x18, 0x02, 0x09A7) +#define PI_MBIST_RDLAT_ADJ_F2 DDR_REGDEF(0x08, 0x09, 0x09A8) +#define PI_MBIST_TWCKENL_RD_ADJ_F2 DDR_REGDEF(0x18, 0x06, 0x09A8) +#define PI_TRTP_F2 DDR_REGDEF(0x18, 0x08, 0x09B3) +#define PI_TRP_F2 DDR_REGDEF(0x00, 0x08, 0x09B4) +#define PI_TRCD_F2 DDR_REGDEF(0x08, 0x08, 0x09B4) +#define PI_TWTR_S_F2 DDR_REGDEF(0x18, 0x06, 0x09B4) +#define PI_TWTR_L_F2 DDR_REGDEF(0x00, 0x06, 0x09B5) +#define PI_TWTR_F2 DDR_REGDEF(0x10, 0x06, 0x09B5) +#define PI_TWR_F2 DDR_REGDEF(0x18, 0x08, 0x09B5) +#define PI_TRAS_MIN_F2 DDR_REGDEF(0x10, 0x09, 0x09B6) +#define PI_TDQSCK_MAX_F2 DDR_REGDEF(0x00, 0x04, 0x09B7) +#define PI_TSR_F2 DDR_REGDEF(0x10, 0x08, 0x09B7) +#define PI_TMRD_F2 DDR_REGDEF(0x18, 0x08, 0x09B7) +#define PI_TDFI_CTRLUPD_MAX_F2 DDR_REGDEF(0x00, 0x15, 0x09BC) +#define PI_TDFI_CTRLUPD_INTERVAL_F2 DDR_REGDEF(0x00, 0x20, 0x09BD) +#define PI_TINIT_F2 DDR_REGDEF(0x00, 0x18, 0x09CC) +#define PI_TINIT1_F2 DDR_REGDEF(0x00, 0x18, 0x09CD) +#define PI_TINIT3_F2 DDR_REGDEF(0x00, 0x18, 0x09CE) +#define PI_TINIT4_F2 DDR_REGDEF(0x00, 0x18, 0x09CF) +#define PI_TINIT5_F2 DDR_REGDEF(0x00, 0x18, 0x09D0) +#define PI_TXSNR_F2 DDR_REGDEF(0x00, 0x10, 0x09D1) +#define PI_TZQCAL_F2 DDR_REGDEF(0x10, 0x0C, 0x09D6) +#define PI_TZQLAT_F2 DDR_REGDEF(0x00, 0x07, 0x09D7) +#define PI_ZQRESET_F2 DDR_REGDEF(0x10, 0x0C, 0x09D8) +#define PI_TDQ72DQ_F2 DDR_REGDEF(0x10, 0x0A, 0x09DD) +#define PI_TCBTRTW_F2 DDR_REGDEF(0x00, 0x06, 0x09DE) +#define PI_MC_TRFC_F2 DDR_REGDEF(0x00, 0x0A, 0x09E1) +#define PI_CKE_MUX_0 DDR_REGDEF(0x00, 0x03, 0x09E6) +#define PI_CKE_MUX_1 DDR_REGDEF(0x08, 0x03, 0x09E6) +#define PI_SEQ_DEC_SW_CS DDR_REGDEF(0x00, 0x02, 0x0A4E) +#define PI_SW_SEQ_START DDR_REGDEF(0x10, 0x01, 0x0A4E) +#define PI_SW_SEQ_0 DDR_REGDEF(0x00, 0x1B, 0x0BF1) +#define PI_SW_SEQ_1 DDR_REGDEF(0x00, 0x1B, 0x0BF2) +#define PI_DFS_ENTRY_SEQ_0 DDR_REGDEF(0x00, 0x1D, 0x0BFB) +#define PI_DFS_INITIALIZATION_SEQ_1 DDR_REGDEF(0x00, 0x1D, 0x0C24) +#define PI_DFS_INITIALIZATION_SEQ_9 DDR_REGDEF(0x00, 0x1D, 0x0C2C) +#define PI_DFS_INITIALIZATION_SEQ_10 DDR_REGDEF(0x00, 0x1D, 0x0C2D) +#define PI_RDLVL_TRAIN_SEQ_1 DDR_REGDEF(0x00, 0x1B, 0x0C42) +#define PI_RDLVL_TRAIN_SEQ_2 DDR_REGDEF(0x00, 0x1B, 0x0C43) +#define PI_RDLVL_TRAIN_SEQ_3 DDR_REGDEF(0x00, 0x1B, 0x0C44) +#define PI_RDLVL_TRAIN_SEQ_4 DDR_REGDEF(0x00, 0x1B, 0x0C45) +#define PI_RDLVL_TRAIN_SEQ_5 DDR_REGDEF(0x00, 0x1B, 0x0C46) +#define PI_SEQ_WAIT_16_F2 DDR_REGDEF(0x00, 0x18, 0x0C77) +#define PI_SEQ_WAIT_17_F2 DDR_REGDEF(0x00, 0x18, 0x0C7A) +#define PI_SEQ_WAIT_18_F2 DDR_REGDEF(0x00, 0x18, 0x0C7D) +#define PI_SEQ_WAIT_19_F2 DDR_REGDEF(0x00, 0x18, 0x0C80) +#define PI_SEQ_WAIT_20_F2 DDR_REGDEF(0x00, 0x18, 0x0C83) +#define PI_SEQ_WAIT_21_F2 DDR_REGDEF(0x00, 0x18, 0x0C86) +#define PI_SEQ_WAIT_22_F2 DDR_REGDEF(0x00, 0x18, 0x0C89) +#define PI_SEQ_WAIT_23_F2 DDR_REGDEF(0x00, 0x18, 0x0C8C) +#define PI_SEQ_WAIT_24_F2 DDR_REGDEF(0x00, 0x18, 0x0C8F) +#define PI_SEQ_WAIT_25_F2 DDR_REGDEF(0x00, 0x18, 0x0C92) +#define PI_SEQ_WAIT_26_F2 DDR_REGDEF(0x00, 0x18, 0x0C95) +#define PI_SEQ_WAIT_30_F2 DDR_REGDEF(0x00, 0x18, 0x0CA1) +#define PI_DARRAY3_0_CS0_F0 DDR_REGDEF(0x00, 0x08, 0x0D0B) +#define PI_DARRAY3_1_CS0_F0 DDR_REGDEF(0x08, 0x08, 0x0D0B) +#define PI_DARRAY3_0_CS0_F1 DDR_REGDEF(0x00, 0x08, 0x0D15) +#define PI_DARRAY3_1_CS0_F1 DDR_REGDEF(0x08, 0x08, 0x0D15) +#define PI_DARRAY3_0_CS0_F2 DDR_REGDEF(0x00, 0x08, 0x0D1F) +#define PI_DARRAY3_1_CS0_F2 DDR_REGDEF(0x08, 0x08, 0x0D1F) +#define PI_DARRAY3_4_CS0_F2 DDR_REGDEF(0x00, 0x08, 0x0D20) +#define PI_DARRAY3_20_CS0_F2 DDR_REGDEF(0x00, 0x08, 0x0D24) +#define PI_DARRAY3_0_CS1_F0 DDR_REGDEF(0x00, 0x08, 0x0D29) +#define PI_DARRAY3_1_CS1_F0 DDR_REGDEF(0x08, 0x08, 0x0D29) +#define PI_DARRAY3_0_CS1_F1 DDR_REGDEF(0x00, 0x08, 0x0D33) +#define PI_DARRAY3_1_CS1_F1 DDR_REGDEF(0x08, 0x08, 0x0D33) +#define PI_DARRAY3_0_CS1_F2 DDR_REGDEF(0x00, 0x08, 0x0D3D) +#define PI_DARRAY3_1_CS1_F2 DDR_REGDEF(0x08, 0x08, 0x0D3D) +#define PI_DARRAY3_4_CS1_F2 DDR_REGDEF(0x00, 0x08, 0x0D3E) +#define PI_DARRAY3_20_CS1_F2 DDR_REGDEF(0x00, 0x08, 0x0D42) + +/* The setting table of Data Slice for V4H */ +static const u32 DDR_PHY_SLICE_REGSET_V4H[DDR_PHY_SLICE_REGSET_NUM_V4H] = { + 0x30020370, 0x00000000, 0x01000002, 0x00000000, + 0x00000000, 0x00000000, 0x00010300, 0x04000100, + 0x00010000, 0x01000000, 0x00000000, 0x00000000, + 0x00010000, 0x08010000, 0x00022003, 0x00000000, + 0x040F0100, 0x1404034F, 0x04040102, 0x04040404, + 0x00000100, 0x00000000, 0x00000000, 0x000800C0, + 0x000F18FF, 0x00000000, 0x00000001, 0x00070000, + 0x0000AAAA, 0x00005555, 0x0000B5B5, 0x00004A4A, + 0x00005656, 0x0000A9A9, 0x0000A9A9, 0x0000B5B5, + 0x00000000, 0xBFBF0000, 0xCCCCF7F7, 0x00000000, + 0x00000000, 0x00000000, 0x00080815, 0x08040000, + 0x00000004, 0x00103000, 0x000C0040, 0x00200200, + 0x01010000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000020, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000004, 0x001F07FF, 0x08000303, + 0x10200080, 0x00000006, 0x00000401, 0x00000000, + 0x20CEC201, 0x00000001, 0x00017706, 0x01007706, + 0x00000000, 0x008D006D, 0x00100001, 0x03FF0100, + 0x00006E01, 0x00000301, 0x00000000, 0x00000000, + 0x00000000, 0x00500050, 0x00500050, 0x00500050, + 0x00500050, 0x0D000050, 0x10100004, 0x06102010, + 0x61619041, 0x07097000, 0x00644180, 0x00803280, + 0x00808001, 0x13010100, 0x02000016, 0x10001003, + 0x06093E42, 0x0F063D01, 0x011700C8, 0x04100140, + 0x00000100, 0x000001D1, 0x05000068, 0x00030402, + 0x01400000, 0x80800300, 0x00160010, 0x76543210, + 0x00000008, 0x03010301, 0x03010301, 0x03010301, + 0x03010301, 0x03010301, 0x00000000, 0x00500050, + 0x00500050, 0x00500050, 0x00500050, 0x00500050, + 0x00500050, 0x00500050, 0x00500050, 0x00500050, + 0x00070087, 0x00000000, 0x08010007, 0x00000000, + 0x20202020, 0x20202020, 0x20202020, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000 +}; + +/* The setting table of Address Slice for V4H */ +static const u32 DDR_PHY_ADR_V_REGSET_V4H[DDR_PHY_ADR_V_REGSET_NUM_V4H] = { + 0x00200030, 0x00200002, 0x76543210, 0x00010001, + 0x06543210, 0x03070000, 0x00001000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x0000807F, + 0x00000001, 0x00000003, 0x00000000, 0x000F0000, + 0x030C000F, 0x00020103, 0x0000000F, 0x00000100, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x02000400, 0x0000002A, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00200101, + 0x10002C03, 0x00000003, 0x00030240, 0x00008008, + 0x00081020, 0x01200000, 0x00010001, 0x00000000, + 0x00100302, 0x003E4208, 0x01400140, 0x01400140, + 0x01400140, 0x01400140, 0x00000100, 0x00000100, + 0x00000100, 0x00000100, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00020580, 0x03000040, + 0x00000000 +}; + +/* The setting table of Address Control Slice for V4H */ +static const u32 DDR_PHY_ADR_G_REGSET_V4H[DDR_PHY_ADR_G_REGSET_NUM_V4H] = { + 0x00000000, 0x00000100, 0x00000001, 0x23800000, + 0x00000000, 0x01000101, 0x00000000, 0x00000001, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00040101, 0x00000000, 0x00000000, 0x00000064, + 0x00000000, 0x00000000, 0x39421B42, 0x00010124, + 0x00520052, 0x00000052, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x07030102, + 0x01030307, 0x00000054, 0x00004096, 0x08200820, + 0x08200820, 0x08200820, 0x08200820, 0x00000820, + 0x004103B8, 0x0000003F, 0x000C0006, 0x00000000, + 0x000004C0, 0x00007A12, 0x00000208, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x03000000, 0x00000000, 0x00000000, 0x04102002, + 0x00041020, 0x01C98C98, 0x3F400000, 0x003F3F3F, + 0x00000000, 0x00000000, 0x76543210, 0x00010198, + 0x00000007, 0x00000000, 0x00000000, 0x00000000, + 0x00000002, 0x00000000, 0x00000000, 0x00000000, + 0x01032380, 0x00000100, 0x00000000, 0x31421342, + 0x00308000, 0x00000080, 0x00063F77, 0x00000006, + 0x0000033F, 0x00000000, 0x0000033F, 0x00000000, + 0x0000033F, 0x00000000, 0x00033F00, 0x00CC0000, + 0x00033F77, 0x00000000, 0x00033F00, 0x00EE0000, + 0x00033F00, 0x00EE0000, 0x00033F00, 0x00EE0000, + 0x00200106 +}; + +/* The setting table of PI Register for V4H */ +static const u32 DDR_PI_REGSET_V4H[DDR_PI_REGSET_NUM_V4H] = { + 0x00000D00, 0x00010100, 0x00640004, 0x00000001, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0xFFFFFFFF, 0x02010000, 0x00000003, 0x00000005, + 0x00000002, 0x00000000, 0x00000101, 0x0012080E, + 0x00000000, 0x001E2C0E, 0x00000000, 0x00030300, + 0x01010700, 0x00000001, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x01000000, 0x00002807, 0x00000000, 0x32000300, + 0x00000000, 0x00000000, 0x04022004, 0x01040100, + 0x00010000, 0x00000100, 0x000000AA, 0x00000055, + 0x000000B5, 0x0000004A, 0x00000056, 0x000000A9, + 0x000000A9, 0x000000B5, 0x00000000, 0x01000000, + 0x00030300, 0x0000001A, 0x000007D0, 0x00000300, + 0x00000000, 0x00000000, 0x01000000, 0x00000101, + 0x00000000, 0x00000000, 0x00000000, 0x00000200, + 0x03030300, 0x01000000, 0x00000000, 0x00000100, + 0x00000003, 0x001100EF, 0x01A1120B, 0x00051400, + 0x001A0700, 0x001101FC, 0x00011A00, 0x00000000, + 0x001F0000, 0x00000000, 0x00000000, 0x00051500, + 0x001103FC, 0x00011A00, 0x00051500, 0x001102FC, + 0x00011A00, 0x00001A00, 0x00000000, 0x001F0000, + 0x001100FC, 0x00011A00, 0x01A1120B, 0x001A0701, + 0x00000000, 0x001F0000, 0x00000000, 0x00000000, + 0x001100EF, 0x01A1120B, 0x00051400, 0x01910480, + 0x01821009, 0x001F0000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x001A0700, 0x01A11E14, + 0x001101FC, 0x00211A00, 0x00051500, 0x001103FC, + 0x00011A00, 0x00051500, 0x001102FC, 0x00011A00, + 0x00031A00, 0x001A0701, 0x00000000, 0x001F0000, + 0x00000000, 0x00000000, 0x01A11E14, 0x01A1120B, + 0x00000000, 0x001F0000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x001100FD, 0x00012E00, + 0x00051700, 0x01A1120B, 0x001A0701, 0x001F0000, + 0x00000000, 0x00000000, 0x001100EF, 0x01A1120B, + 0x00051400, 0x001A0700, 0x001102FD, 0x00012E00, + 0x00000000, 0x001F0000, 0x00000000, 0x00000000, + 0x00070700, 0x00000000, 0x01000000, 0x00000300, + 0x17030000, 0x00000000, 0x00000000, 0x00000000, + 0x0A0A140A, 0x10020201, 0x332A0002, 0x01010000, + 0x0B000404, 0x04030308, 0x00010100, 0x02020301, + 0x01001000, 0x00000034, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x55AA55AA, 0x33CC33CC, + 0x0FF00FF0, 0x0F0FF0F0, 0x00008E38, 0x00000001, + 0x00000002, 0x00020001, 0x00020001, 0x02010201, + 0x0000000F, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0xAAAAA593, + 0xA5939999, 0x00000000, 0x00005555, 0x00003333, + 0x0000CCCC, 0x00000000, 0x0003FFFF, 0x00003333, + 0x0000CCCC, 0x00000000, 0x036DB6DB, 0x00249249, + 0x05B6DB6D, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x036DB6DB, 0x00249249, + 0x05B6DB6D, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x01000000, 0x00000100, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00010000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00010000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00080000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x01180400, + 0x03020100, 0x00060504, 0x00010100, 0x00000008, + 0x00080000, 0x00000001, 0x00000000, 0x0001AA00, + 0x00000100, 0x00000000, 0x00010000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00020000, 0x00000100, 0x00010000, 0x0000000B, + 0x0000001C, 0x00000100, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x03010000, 0x01000100, + 0x01020001, 0x00010300, 0x05000104, 0x01060001, + 0x00010700, 0x00000000, 0x00000000, 0x00010000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000301, 0x00000000, 0x00000000, 0x01010000, + 0x00000000, 0x00000200, 0x00000000, 0xB8000000, + 0x010000FF, 0x0000FFE8, 0x00FFA801, 0xFFD80100, + 0x00007F10, 0x00000000, 0x00000034, 0x0000003D, + 0x00020079, 0x02000200, 0x02000204, 0x06000C06, + 0x04040200, 0x04100804, 0x14090004, 0x1C081024, + 0x0000120C, 0x00000015, 0x000000CF, 0x00000026, + 0x0000017F, 0x00000130, 0x04000C2E, 0x00000404, + 0x01080032, 0x01080032, 0x000F0032, 0x00000000, + 0x00000000, 0x00000000, 0x00010300, 0x00010301, + 0x03030000, 0x00000001, 0x00010303, 0x00030000, + 0x0013000C, 0x0A060037, 0x03030526, 0x000C0032, + 0x0017003D, 0x0025004B, 0x00010101, 0x0000000E, + 0x00000019, 0x010000C8, 0x000F000F, 0x0007000C, + 0x001A0100, 0x0015001A, 0x0100000B, 0x00C900C9, + 0x005100A1, 0x29003329, 0x33290033, 0x0A070600, + 0x0A07060D, 0x0D09070D, 0x000C000D, 0x00001000, + 0x00000C00, 0x00001000, 0x00000C00, 0x02001000, + 0x0002000E, 0x00160019, 0x1E1A00C8, 0x00100004, + 0x361C0008, 0x00000000, 0x0000000C, 0x0006000C, + 0x0300361C, 0x04001300, 0x000D0019, 0x0000361C, + 0x20003300, 0x00000000, 0x02000000, 0x04040802, + 0x00060404, 0x0003C34F, 0x05022001, 0x0203000A, + 0x04040408, 0xC34F0604, 0x10010005, 0x040A0502, + 0x0A080F11, 0x1C0A040A, 0x0022C34F, 0x0C0C1002, + 0x00019E0A, 0x0000102C, 0x000002FE, 0x00001DEC, + 0x0000185C, 0x0000F398, 0x04000400, 0x03030400, + 0x002AF803, 0x00002AF8, 0x0000D6D7, 0x00000003, + 0x0000006E, 0x00000016, 0x00004E20, 0x00004E20, + 0x00030D40, 0x00000005, 0x000000C8, 0x00000027, + 0x00027100, 0x00027100, 0x00186A00, 0x00000028, + 0x00000640, 0x01000136, 0x00530040, 0x00010004, + 0x00960040, 0x00010004, 0x04B00040, 0x00000318, + 0x00280005, 0x05040404, 0x00070603, 0x06030503, + 0x0503000D, 0x00640603, 0x06040608, 0x00040604, + 0x00260015, 0x01050130, 0x01000100, 0x00020201, + 0x04040000, 0x01010104, 0x03020302, 0x00000100, + 0x02020101, 0x00000000, 0x09910260, 0x11911600, + 0x19A21009, 0x19A10100, 0x19A10201, 0x19A10302, + 0x19A10A03, 0x19A10B04, 0x19A10C05, 0x19A10E07, + 0x19A10F08, 0x19A1110A, 0x19A1120B, 0x19A1130C, + 0x19A1140D, 0x19A00C00, 0x199F0000, 0x199F0000, + 0x199F0000, 0x199F0000, 0x01910300, 0x01A21009, + 0x019F0000, 0x019F0000, 0x019F0000, 0x019F0000, + 0x001140BF, 0x01811009, 0x01850400, 0x01A10C05, + 0x01850300, 0x01A10C11, 0x01850300, 0x001100BF, + 0x01811009, 0x01850500, 0x019F0000, 0x019F0000, + 0x01510001, 0x01D102A0, 0x01E21009, 0x00051900, + 0x019F0000, 0x019F0000, 0x019F0000, 0x019F0000, + 0x019F0000, 0x019F0000, 0x019F0000, 0x019F0000, + 0x019F0000, 0x019F0000, 0x019F0000, 0x01510001, + 0x01D10290, 0x01E21009, 0x01510001, 0x01D10000, + 0x01E21009, 0x00051800, 0x019F0000, 0x019F0000, + 0x019F0000, 0x019F0000, 0x019F0000, 0x019F0000, + 0x019F0000, 0x019F0000, 0x0011008F, 0x00910000, + 0x01811009, 0x01910040, 0x01A21009, 0x019F0000, + 0x01911000, 0x01A21009, 0x01A10100, 0x01A10201, + 0x01A10302, 0x01A10A03, 0x01A10B04, 0x01A10C05, + 0x01A10E07, 0x01A10F08, 0x01A1110A, 0x01A1120B, + 0x01A1130C, 0x01A1140D, 0x01A00C00, 0x01910800, + 0x01A21009, 0x019F0000, 0x019F0000, 0x019F0000, + 0x0101017F, 0x00010101, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x01000000, 0x01000101, + 0x00000000, 0x00000000, 0x00050000, 0x00070100, + 0x000F0200, 0x00000000, 0x01A10100, 0x01A10201, + 0x01A10302, 0x01A00B04, 0x00210D06, 0x01A1110A, + 0x01A1140D, 0x00098000, 0x019F0000, 0x019F0000, + 0x019F0000, 0x019F0000, 0x019F0000, 0x019F0000, + 0x019F0000, 0x019F0000, 0x019F0000, 0x019F0000, + 0x019F0000, 0x019F0000, 0x019F0000, 0x019F0000, + 0x019F0000, 0x019F0000, 0x019F0000, 0x019F0000, + 0x019F0000, 0x019F0000, 0x019F0000, 0x019F0000, + 0x019F0000, 0x019F0000, 0x019F0000, 0x019F0000, + 0x019F0000, 0x019F0000, 0x019F0000, 0x019F0000, + 0x019F0000, 0x019F0000, 0x019F0000, 0x019F0000, + 0x019F0000, 0x019F0000, 0x019F0000, 0x019F0000, + 0x019F0000, 0x019F0000, 0x019F0000, 0x019F0000, + 0x019F0000, 0x019F0000, 0x019F0000, 0x019F0000, + 0x019F0000, 0x019F0000, 0x019F0000, 0x019F0000, + 0x019F0000, 0x019F0000, 0x01A10100, 0x01A10201, + 0x01A10302, 0x01A10A03, 0x01A10B04, 0x00210D06, + 0x01A1110A, 0x00000000, 0x01A1140D, 0x00000000, + 0x00000000, 0x00000000, 0x01A1120B, 0x000A0000, + 0x001F0000, 0x001F0000, 0x001F0000, 0x001F0000, + 0x001F0000, 0x001F0000, 0x000A0000, 0x01061300, + 0x00000000, 0x00000000, 0x00061180, 0x000612C0, + 0x00000000, 0x00000000, 0x001F0000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x01811009, 0x0011EFAF, + 0x01A1120B, 0x001F0000, 0x001F0000, 0x001F0000, + 0x001F0000, 0x001F0000, 0x001F0000, 0x001100BF, + 0x01A1120B, 0x080D0000, 0x001F0000, 0x001F0000, + 0x001F0000, 0x080C0000, 0x001F0000, 0x001F0000, + 0x001F0000, 0x001F0000, 0x001F0000, 0x001F0000, + 0x001F0000, 0x001F0000, 0x001F0200, 0x001F0200, + 0x001F0200, 0x001F0200, 0x001F0200, 0x001F0200, + 0x001F0200, 0x001F0200, 0x001F0200, 0x001F0200, + 0x001F0200, 0x001F0200, 0x001100EF, 0x01A1120B, + 0x001F0000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x01A1120B, 0x001F0000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x001100EF, 0x01A1120B, + 0x001F0000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00211F14, 0x00212014, + 0x00212116, 0x00212217, 0x001F0000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x001A85FF, 0x00051E00, 0x001F0000, 0x00000000, + 0x00211F14, 0x00212015, 0x00212116, 0x00212217, + 0x01A1120B, 0x001F0000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x0031FFBF, 0x01A11009, + 0x01A10E07, 0x01A10F08, 0x003100BF, 0x01A11009, + 0x00051800, 0x003F0000, 0x003F0000, 0x003F0000, + 0x003F0000, 0x003F0000, 0x003F0000, 0x003F0000, + 0x003F0000, 0x003F0000, 0x0031FFBF, 0x01A11009, + 0x01A10E07, 0x01A10F08, 0x003100BF, 0x01A11009, + 0x00051800, 0x003F0000, 0x003F0000, 0x003F0000, + 0x003F0000, 0x003F0000, 0x003F0000, 0x003F0000, + 0x003F0000, 0x003F0000, 0x08084340, 0x0011FFFF, + 0x2011FFFB, 0x00012E00, 0x001100EF, 0x01A1120B, + 0x001F0000, 0x001F0000, 0x001F0000, 0x001F0000, + 0x001F0000, 0x001F0000, 0x001F0000, 0x001F0000, + 0x001F0000, 0x001F0000, 0x001F0000, 0x001F0000, + 0x001F0000, 0x001F0000, 0x001F0000, 0x001F0000, + 0x001F0000, 0x001F0000, 0x083E4340, 0x00212E00, + 0x01A1120B, 0x003F0000, 0x003F0000, 0x003F0000, + 0x003F0000, 0x003F0000, 0x003F0000, 0x08201020, + 0x28100020, 0x08083020, 0x08400020, 0x08402020, + 0x08483020, 0x10083020, 0x20180020, 0x30480020, + 0x78880020, 0x488010E0, 0x494B0000, 0x49089080, + 0x49080000, 0x490011C0, 0x0A000020, 0x08000020, + 0x08000020, 0x08000020, 0x08000020, 0x08000020, + 0x08000020, 0x08000020, 0x08000020, 0x08000020, + 0x08000020, 0x08000020, 0x08000020, 0x08000020, + 0x08000020, 0x08000020, 0x08000020, 0x08000020, + 0x08000020, 0x08000020, 0x08000020, 0x08000020, + 0x08000020, 0x08000020, 0x08000020, 0x08000020, + 0x08000020, 0x08000020, 0x08000020, 0x08000020, + 0x001100FF, 0x01810302, 0x001100DF, 0x00010D06, + 0x001100EF, 0x01A1120B, 0x001F0000, 0x001F0000, + 0x001F0000, 0x001F0000, 0x001F0000, 0x001F0000, + 0x001F0000, 0x001F0000, 0x001F0000, 0x001F0000, + 0x00010D06, 0x01810302, 0x0181160E, 0x001F0000, + 0x001F0000, 0x001F0000, 0x001F0000, 0x001F0000, + 0x081A52FD, 0x001A12FF, 0x00051A00, 0x001A13FF, + 0x00051B00, 0x001F13FF, 0x081A52FD, 0x001A12FF, + 0x00051A00, 0x001A13FF, 0x00051B00, 0x001F13FF, + 0x081A52FD, 0x001A12FF, 0x00051A00, 0x001A13FF, + 0x00051B00, 0x001F13FF, 0x00032300, 0x00032400, + 0x001F0000, 0x001F0000, 0x00800000, 0x0031FFBF, + 0x01A11009, 0x01A10E07, 0x01A10F08, 0x003100BF, + 0x01A11009, 0x00051800, 0x003F0000, 0x003F0000, + 0x003F0000, 0x003F0000, 0x003F0000, 0x003F0000, + 0x003F0000, 0x003F0000, 0x00800000, 0x0031FFBF, + 0x01A11009, 0x01A10E07, 0x01A10F08, 0x003100BF, + 0x01A11009, 0x00051800, 0x003F0000, 0x003F0000, + 0x003F0000, 0x003F0000, 0x003F0000, 0x003F0000, + 0x003F0000, 0x003F0000, 0x081100DF, 0x08010D06, + 0x0011000F, 0x0181160E, 0x001100EF, 0x01A1120B, + 0x001F0000, 0x001F0000, 0x001F0000, 0x009C0000, + 0x08010D06, 0x0181160E, 0x01A1120B, 0x001F0000, + 0x001F0000, 0x001F0000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x11910048, + 0x09910060, 0x19A21009, 0x19A10100, 0x19A10201, + 0x19A10302, 0x19A10A03, 0x19A10B04, 0x18051C00, + 0x19A1110A, 0x19A1120B, 0x19A1130C, 0x19A1140D, + 0x19A1160E, 0x181140BF, 0x19A11009, 0x19A10C05, + 0x19A00C00, 0x19A10E07, 0x19A10F08, 0x19910280, + 0x19A21009, 0x18051000, 0x18861101, 0x181F0000, + 0x18000000, 0x18000000, 0x18000000, 0x18000000, + 0x18000000, 0x18000000, 0x18000000, 0x18000000, + 0x18000000, 0x18000000, 0x18000000, 0x18000000, + 0x18000000, 0x18000000, 0x18000000, 0x18861100, + 0x19A11009, 0x101B0001, 0x181B0100, 0x18000500, + 0x181B0200, 0x00000000, 0x181B0600, 0x181B0C00, + 0x181B0100, 0x181B0200, 0x181B0300, 0x181B0400, + 0x181F0000, 0x18000000, 0x18000000, 0x18000000, + 0x18000000, 0x18000000, 0x18000000, 0x18000000, + 0x18000000, 0x18000000, 0x18000000, 0x18000000, + 0x18000000, 0x18000000, 0x18000000, 0x18000000, + 0x18000000, 0x004B1040, 0x001011C0, 0x00089080, + 0x000811C0, 0x040811C0, 0x02000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x5F407FAA, + 0x007B776F, 0x4AB555AA, 0xB5A9A956, 0x9F80BFAA, + 0x00BBB7AF, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00002AF8, 0x0000D6D7, 0x0000006E, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x0000000E, 0x00000019, 0x000000C8, + 0x00000001, 0x00000001, 0x00000003, 0x00000007, + 0x00000007, 0x00000009, 0x00000001, 0x00000001, + 0x00000003, 0x00000001, 0x00000001, 0x00000003, + 0x0000006E, 0x000000C8, 0x00000640, 0x00000001, + 0x00000001, 0x00000003, 0x00000002, 0x00000004, + 0x0000001C, 0x00000007, 0x0000000B, 0x00000051, + 0x0000000C, 0x00000015, 0x000000A1, 0x00000003, + 0x00000000, 0x0000000C, 0x00000000, 0x00000000, + 0x00000000, 0x0000000F, 0x0000000F, 0x0000000F, + 0x00002AF9, 0x00002AF9, 0x00002AF9, 0x00000034, + 0x0000001E, 0x0000003C, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x000000C0, 0x00000000, 0x00000000, 0x55550000, + 0x00003C5A, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00D60000, + 0x50005000, 0x803E0050, 0x00000200, 0x00000000, + 0x00000000, 0x00007800, 0x00000000, 0x00000000, + 0x00000000, 0x00C61110, 0x2C002834, 0x0C06002C, + 0x00000200, 0x00000000, 0x00000000, 0x00007800, + 0x00000000, 0x00000000, 0x00000000, 0x00C6BBB0, + 0x2C002834, 0x0C06002C, 0x00000200, 0x00000000, + 0x00000000, 0x00007800, 0x00000000, 0x00000000, + 0x00000000, 0x00D60000, 0x50005000, 0x803E0050, + 0x00000200, 0x00000000, 0x00000000, 0x00007800, + 0x00000000, 0x00000000, 0x00000000, 0x00C61110, + 0x2C002834, 0x082E002C, 0x00000200, 0x00000000, + 0x00000000, 0x00007800, 0x00000000, 0x00000000, + 0x00000000, 0x00C6BBB0, 0x2C002834, 0x082E002C, + 0x00000200, 0x00000000, 0x00000000, 0x00007800, + 0x00000000, 0x00000000, 0x00000000, 0x80808080, + 0x800D8080, 0x80808080, 0x17808080, 0x80808025, + 0x2221201F, 0x80808080, 0x80808080, 0x80808080, + 0x80808080, 0x80808080, 0x80808080, 0x80808080, + 0x80808080, 0x80808080, 0x80808080, 0x80808080, + 0x80808080, 0x80808080, 0x80808080, 0x0A030201, + 0x0E800C0B, 0x1211100F, 0x80161413, 0x08004C80, + 0x8080801E, 0x80804E80, 0x80808080, 0x80808080, + 0x80808080 +}; + +struct dbsc5_table_patch { + const u32 reg; + const u32 val; +}; + +static const struct dbsc5_table_patch dbsc5_table_patch_slice_3200[] = { + { PHY_REGULATOR_EN_CNT, 0x10 }, + { PHY_RX_CAL_ALL_DLY, 0x07 }, + { PHY_RDDATA_EN_TSEL_DLY, 0x08 }, + { PHY_RDDATA_EN_OE_DLY, 0x0B }, + { PHY_RPTR_UPDATE, 0x07 }, + { PHY_WRLVL_RESP_WAIT_CNT, 0x25 }, + { PHY_RDLVL_MAX_EDGE, 0x012D }, + { PHY_RDDATA_EN_DLY, 0x0B }, + { PHY_RDDQS_LATENCY_ADJUST, 0x04 }, + { PHY_RDDQS_GATE_SLAVE_DELAY, 0x05 }, + { PHY_GTLVL_LAT_ADJ_START, 0x03 }, + { PHY_LP4_BOOT_RX_PCLK_CLK_SEL, 0x00 } +}; + +static const struct dbsc5_table_patch dbsc5_table_patch_adr_v_3200[] = { + { PHY_ADR_MEAS_DLY_STEP_ENABLE, 0x00 }, + { PHY_ADR_CALVL_DLY_STEP, 0x02 } +}; + +static const struct dbsc5_table_patch dbsc5_table_patch_pi_3200[] = { + { PI_TCKCKEL_F2, 0x03 }, + { PI_TDELAY_RDWR_2_BUS_IDLE_F2, 0x57 }, + { PI_TREF_F2, 0x613 }, + { PI_TDFI_WRLVL_WW_F0, 0x2B }, + { PI_TDFI_WRLVL_WW_F1, 0x2B }, + { PI_TDFI_WRLVL_WW_F2, 0x2B }, + { PI_RDLAT_ADJ_F2, 0x22 }, + { PI_TDFI_CALVL_CAPTURE_F2, 0x1D }, + { PI_TDFI_CALVL_CC_F2, 0x43 }, + { PI_TVRCG_ENABLE_F2, 0x51 }, + { PI_TVRCG_DISABLE_F2, 0x29 }, + { PI_TXP_F2, 0x07 }, + { PI_TMRWCKEL_F2, 0x0A }, + { PI_TDFI_CALVL_STROBE_F2, 0x06 }, + { PI_TFC_F2, 0x64 }, + { PI_TCKEHDQS_F2, 0x12 }, + { PI_TDFI_WDQLVL_RW_F2, 0x09 }, + { PI_TDFI_WDQLVL_WR_F2, 0x10 }, + { PI_MBIST_TWCKENL_RD_ADJ_F2, 0x10 }, + { PI_MBIST_RDLAT_ADJ_F2, 0x1E }, + { PI_TWTR_S_F2, 0x05 }, + { PI_TWTR_L_F2, 0x05 }, + { PI_TWTR_F2, 0x05 }, + { PI_TWR_F2, 0x0E }, + { PI_TDQSCK_MAX_F2, 0x01 }, + { PI_TDFI_CTRLUPD_MAX_F2, 0x0C26 }, + { PI_TDFI_CTRLUPD_INTERVAL_F2, 0x797C }, + { PI_TXSNR_F2, 0x9B }, + { PI_ZQRESET_F2, 0x0014 }, + { PI_TCBTRTW_F2, 0x04 }, + { PI_SEQ_WAIT_16_F2, 0x000064 }, + { PI_SEQ_WAIT_17_F2, 0x000002 }, + { PI_SEQ_WAIT_18_F2, 0x000007 }, + { PI_SEQ_WAIT_19_F2, 0x000002 }, + { PI_SEQ_WAIT_20_F2, 0x000002 }, + { PI_SEQ_WAIT_21_F2, 0x000320 }, + { PI_SEQ_WAIT_22_F2, 0x000002 }, + { PI_SEQ_WAIT_23_F2, 0x00000E }, + { PI_SEQ_WAIT_24_F2, 0x000029 }, + { PI_SEQ_WAIT_25_F2, 0x000051 }, + { PI_SEQ_WAIT_26_F2, 0x000003 }, + { PI_SEQ_WAIT_30_F2, 0x00002B }, + { PI_WRDCM_LVL_EN_F1, 0x00 }, + { PI_WRDCM_LVL_EN_F2, 0x00 }, + { PI_DRAMDCA_LVL_EN_F1, 0x00 }, + { PI_DRAMDCA_LVL_EN_F2, 0x00 }, + { PI_TINIT_F2, 0x013880 }, + { PI_TINIT1_F2, 0x013880 }, + { PI_TINIT3_F2, 0x0C3500 }, + { PI_TINIT4_F2, 0x000014 }, + { PI_TINIT5_F2, 0x000320 } +}; + +static const struct dbsc5_table_patch dbsc5_table_patch_slice_3733[] = { + { PHY_REGULATOR_EN_CNT, 0x13 }, + { PHY_RX_CAL_ALL_DLY, 0x08 }, + { PHY_RDDATA_EN_TSEL_DLY, 0x0A }, + { PHY_RDDATA_EN_OE_DLY, 0x0D }, + { PHY_RPTR_UPDATE, 0x08 }, + { PHY_WRLVL_RESP_WAIT_CNT, 0x2A }, + { PHY_RDLVL_MAX_EDGE, 0x0149 }, + { PHY_RDDATA_EN_DLY, 0x0D }, + { PHY_RDDQS_LATENCY_ADJUST, 0x04 }, + { PHY_RDDQS_GATE_SLAVE_DELAY, 0x9C }, + { PHY_GTLVL_LAT_ADJ_START, 0x04 }, + { PHY_LP4_BOOT_RX_PCLK_CLK_SEL, 0x00 } +}; + +static const struct dbsc5_table_patch dbsc5_table_patch_adr_v_3733[] = { + { PHY_ADR_MEAS_DLY_STEP_ENABLE, 0x00 }, + { PHY_ADR_CALVL_DLY_STEP, 0x02 } +}; + +static const struct dbsc5_table_patch dbsc5_table_patch_pi_3733[] = { + { PI_TCKCKEL_F2, 0x03 }, + { PI_TDELAY_RDWR_2_BUS_IDLE_F2, 0x5B }, + { PI_TREF_F2, 0x717 }, + { PI_TDFI_WRLVL_WW_F0, 0x2C }, + { PI_TDFI_WRLVL_WW_F1, 0x2C }, + { PI_TDFI_WRLVL_WW_F2, 0x2C }, + { PI_RDLAT_ADJ_F2, 0x24 }, + { PI_TDFI_CALVL_CAPTURE_F2, 0x1F }, + { PI_TDFI_CALVL_CC_F2, 0x45 }, + { PI_TVRCG_ENABLE_F2, 0x5F }, + { PI_TVRCG_DISABLE_F2, 0x30 }, + { PI_TXP_F2, 0x07 }, + { PI_TMRWCKEL_F2, 0x0A }, + { PI_TDFI_CALVL_STROBE_F2, 0x06 }, + { PI_TFC_F2, 0x75 }, + { PI_TCKEHDQS_F2, 0x13 }, + { PI_TDFI_WDQLVL_RW_F2, 0x09 }, + { PI_TDFI_WDQLVL_WR_F2, 0x12 }, + { PI_MBIST_TWCKENL_RD_ADJ_F2, 0x10 }, + { PI_MBIST_RDLAT_ADJ_F2, 0x20 }, + { PI_TWTR_S_F2, 0x06 }, + { PI_TWTR_L_F2, 0x06 }, + { PI_TWTR_F2, 0x06 }, + { PI_TWR_F2, 0x10 }, + { PI_TDFI_CTRLUPD_MAX_F2, 0x0E2E }, + { PI_TDFI_CTRLUPD_INTERVAL_F2, 0x8DCC }, + { PI_TXSNR_F2, 0xB5 }, + { PI_ZQRESET_F2, 0x0018 }, + { PI_TCBTRTW_F2, 0x05 }, + { PI_SEQ_WAIT_16_F2, 0x000075 }, + { PI_SEQ_WAIT_17_F2, 0x000002 }, + { PI_SEQ_WAIT_18_F2, 0x000007 }, + { PI_SEQ_WAIT_19_F2, 0x000002 }, + { PI_SEQ_WAIT_20_F2, 0x000002 }, + { PI_SEQ_WAIT_21_F2, 0x0003A6 }, + { PI_SEQ_WAIT_22_F2, 0x000002 }, + { PI_SEQ_WAIT_23_F2, 0x000011 }, + { PI_SEQ_WAIT_24_F2, 0x000030 }, + { PI_SEQ_WAIT_25_F2, 0x00005F }, + { PI_SEQ_WAIT_26_F2, 0x000005 }, + { PI_SEQ_WAIT_30_F2, 0x00002D }, + { PI_TINIT_F2, 0x016C90 }, + { PI_TINIT1_F2, 0x016C90 }, + { PI_TINIT3_F2, 0x0E3D98 }, + { PI_TINIT4_F2, 0x000018 }, + { PI_TINIT5_F2, 0x0003A6 } +}; + +static const struct dbsc5_table_patch dbsc5_table_patch_slice_4266[] = { + { PHY_REGULATOR_EN_CNT, 0x16 }, + { PHY_RX_CAL_ALL_DLY, 0x09 }, + { PHY_RDDATA_EN_TSEL_DLY, 0x0B }, + { PHY_RDDATA_EN_OE_DLY, 0x0E }, + { PHY_RPTR_UPDATE, 0x08 }, + { PHY_WRLVL_RESP_WAIT_CNT, 0x2E }, + { PHY_RDLVL_MAX_EDGE, 0x0164 }, + { PHY_RDDATA_EN_DLY, 0x0E }, + { PHY_RDDQS_LATENCY_ADJUST, 0x05 }, + { PHY_RDDQS_GATE_SLAVE_DELAY, 0x30 }, + { PHY_GTLVL_LAT_ADJ_START, 0x04 }, + { PHY_LP4_BOOT_RX_PCLK_CLK_SEL, 0x00 } +}; + +static const struct dbsc5_table_patch dbsc5_table_patch_adr_v_4266[] = { + { PHY_ADR_MEAS_DLY_STEP_ENABLE, 0x00 }, + { PHY_ADR_CALVL_DLY_STEP, 0x02 } +}; + +static const struct dbsc5_table_patch dbsc5_table_patch_pi_4266[] = { + { PI_TCKCKEL_F2, 0x03 }, + { PI_TDELAY_RDWR_2_BUS_IDLE_F2, 0x64 }, + { PI_TREF_F2, 0x81C }, + { PI_TDFI_WRLVL_WW_F0, 0x2D }, + { PI_TDFI_WRLVL_WW_F1, 0x2D }, + { PI_TDFI_WRLVL_WW_F2, 0x2D }, + { PI_RDLAT_ADJ_F2, 0x2B }, + { PI_TDFI_CALVL_CAPTURE_F2, 0x20 }, + { PI_TDFI_CALVL_CC_F2, 0x46 }, + { PI_TVRCG_ENABLE_F2, 0x6C }, + { PI_TVRCG_DISABLE_F2, 0x37 }, + { PI_TXP_F2, 0x07 }, + { PI_TMRWCKEL_F2, 0x0A }, + { PI_TFC_F2, 0x86 }, + { PI_TCKEHDQS_F2, 0x14 }, + { PI_TDFI_WDQLVL_RW_F2, 0x0B }, + { PI_TDFI_WDQLVL_WR_F2, 0x13 }, + { PI_MBIST_TWCKENL_RD_ADJ_F2, 0x14 }, + { PI_MBIST_RDLAT_ADJ_F2, 0x27 }, + { PI_TWTR_S_F2, 0x07 }, + { PI_TWTR_L_F2, 0x07 }, + { PI_TWTR_F2, 0x07 }, + { PI_TWR_F2, 0x13 }, + { PI_TDFI_CTRLUPD_MAX_F2, 0x1038 }, + { PI_TDFI_CTRLUPD_INTERVAL_F2, 0xA230 }, + { PI_TXSNR_F2, 0xCF }, + { PI_ZQRESET_F2, 0x001B }, + { PI_TCBTRTW_F2, 0x06 }, + { PI_SEQ_WAIT_16_F2, 0x000086 }, + { PI_SEQ_WAIT_17_F2, 0x000002 }, + { PI_SEQ_WAIT_18_F2, 0x000007 }, + { PI_SEQ_WAIT_19_F2, 0x000002 }, + { PI_SEQ_WAIT_20_F2, 0x000002 }, + { PI_SEQ_WAIT_21_F2, 0x00042B }, + { PI_SEQ_WAIT_22_F2, 0x000002 }, + { PI_SEQ_WAIT_23_F2, 0x000013 }, + { PI_SEQ_WAIT_24_F2, 0x000037 }, + { PI_SEQ_WAIT_25_F2, 0x00006C }, + { PI_SEQ_WAIT_26_F2, 0x000006 }, + { PI_SEQ_WAIT_30_F2, 0x000032 }, + { PI_TINIT_F2, 0x01A0AB }, + { PI_TINIT1_F2, 0x01A0AB }, + { PI_TINIT3_F2, 0x1046AB }, + { PI_TINIT4_F2, 0x00001B }, + { PI_TINIT5_F2, 0x00042B } +}; + +static const struct dbsc5_table_patch dbsc5_table_patch_slice_4800[] = { + { PHY_REGULATOR_EN_CNT, 0x18 }, + { PHY_RX_CAL_ALL_DLY, 0x0A }, + { PHY_RDDATA_EN_TSEL_DLY, 0x0D }, + { PHY_RDDATA_EN_OE_DLY, 0x10 }, + { PHY_RPTR_UPDATE, 0x08 }, + { PHY_WRLVL_RESP_WAIT_CNT, 0x31 }, + { PHY_RDLVL_MAX_EDGE, 0x017F }, + { PHY_RDDATA_EN_DLY, 0x10 }, + { PHY_RDDQS_LATENCY_ADJUST, 0x05 }, + { PHY_RDDQS_GATE_SLAVE_DELAY, 0xC6 }, + { PHY_GTLVL_LAT_ADJ_START, 0x05 }, + { PHY_LP4_BOOT_RX_PCLK_CLK_SEL, 0x00 } +}; + +static const struct dbsc5_table_patch dbsc5_table_patch_adr_v_4800[] = { + { PHY_ADR_MEAS_DLY_STEP_ENABLE, 0x00 }, + { PHY_ADR_CALVL_DLY_STEP, 0x02 } +}; + +static const struct dbsc5_table_patch dbsc5_table_patch_pi_4800[] = { + { PI_TCKCKEL_F2, 0x03 }, + { PI_TDELAY_RDWR_2_BUS_IDLE_F2, 0x68 }, + { PI_RDLAT_ADJ_F2, 0x2D }, + { PI_TREF_F2, 0x920 }, + { PI_TDFI_WRLVL_WW_F0, 0x2E }, + { PI_TDFI_WRLVL_WW_F1, 0x2E }, + { PI_TDFI_WRLVL_WW_F2, 0x2E }, + { PI_TDFI_CALVL_CAPTURE_F2, 0x21 }, + { PI_TDFI_CALVL_CC_F2, 0x47 }, + { PI_TVRCG_DISABLE_F2, 0x3D }, + { PI_TVRCG_ENABLE_F2, 0x79 }, + { PI_TXP_F2, 0x08 }, + { PI_TMRWCKEL_F2, 0x0A }, + { PI_TCKEHDQS_F2, 0x14 }, + { PI_TFC_F2, 0x96 }, + { PI_TDFI_WDQLVL_RW_F2, 0x0B }, + { PI_TDFI_WDQLVL_WR_F2, 0x15 }, + { PI_MBIST_TWCKENL_RD_ADJ_F2, 0x18 }, + { PI_MBIST_RDLAT_ADJ_F2, 0x29 }, + { PI_TWTR_S_F2, 0x08 }, + { PI_TWR_F2, 0x15 }, + { PI_TWTR_F2, 0x08 }, + { PI_TWTR_L_F2, 0x08 }, + { PI_TDFI_CTRLUPD_MAX_F2, 0x1240 }, + { PI_TDFI_CTRLUPD_INTERVAL_F2, 0xB680 }, + { PI_TXSNR_F2, 0x0E9 }, + { PI_ZQRESET_F2, 0x001E }, + { PI_TCBTRTW_F2, 0x06 }, + { PI_SEQ_WAIT_16_F2, 0x000096 }, + { PI_SEQ_WAIT_17_F2, 0x000002 }, + { PI_SEQ_WAIT_18_F2, 0x000008 }, + { PI_SEQ_WAIT_19_F2, 0x000002 }, + { PI_SEQ_WAIT_20_F2, 0x000002 }, + { PI_SEQ_WAIT_21_F2, 0x0004B0 }, + { PI_SEQ_WAIT_22_F2, 0x000002 }, + { PI_SEQ_WAIT_23_F2, 0x000015 }, + { PI_SEQ_WAIT_24_F2, 0x00003D }, + { PI_SEQ_WAIT_25_F2, 0x000079 }, + { PI_SEQ_WAIT_26_F2, 0x000008 }, + { PI_SEQ_WAIT_30_F2, 0x000034 }, + { PI_TINIT_F2, 0x01D4A9 }, + { PI_TINIT1_F2, 0x01D4A9 }, + { PI_TINIT3_F2, 0x124E91 }, + { PI_TINIT4_F2, 0x00001E }, + { PI_TINIT5_F2, 0x0004B0 } +}; + +static const struct dbsc5_table_patch dbsc5_table_patch_slice_5500[] = { + { PHY_REGULATOR_EN_CNT, 0x1C }, + { PHY_RX_CAL_ALL_DLY, 0x0C }, + { PHY_RDDATA_EN_TSEL_DLY, 0x10 }, + { PHY_RDDATA_EN_OE_DLY, 0x13 }, + { PHY_WRLVL_RESP_WAIT_CNT, 0x37 }, + { PHY_RDLVL_MAX_EDGE, 0x01A3 }, + { PHY_RDDATA_EN_DLY, 0x13 }, + { PHY_RDDQS_LATENCY_ADJUST, 0x06 }, + { PHY_RDDQS_GATE_SLAVE_DELAY, 0x8F }, + { PHY_GTLVL_LAT_ADJ_START, 0x06 }, + { PHY_LP4_BOOT_RX_PCLK_CLK_SEL, 0x00 } +}; + +static const struct dbsc5_table_patch dbsc5_table_patch_adr_v_5500[] = { + { PHY_ADR_MEAS_DLY_STEP_ENABLE, 0x00 }, + { PHY_ADR_CALVL_DLY_STEP, 0x02 } +}; + +static const struct dbsc5_table_patch dbsc5_table_patch_pi_5500[] = { + { PI_TDELAY_RDWR_2_BUS_IDLE_F2, 0x71 }, + { PI_RDLAT_ADJ_F2, 0x32 }, + { PI_TREF_F2, 0xA79 }, + { PI_TDFI_WRLVL_WW_F0, 0x30 }, + { PI_TDFI_WRLVL_WW_F1, 0x30 }, + { PI_TDFI_WRLVL_WW_F2, 0x30 }, + { PI_TDFI_CALVL_CAPTURE_F2, 0x23 }, + { PI_TDFI_CALVL_CC_F2, 0x49 }, + { PI_TVRCG_DISABLE_F2, 0x46 }, + { PI_TVRCG_ENABLE_F2, 0x8B }, + { PI_TMRWCKEL_F2, 0x0B }, + { PI_TCKEHDQS_F2, 0x15 }, + { PI_TFC_F2, 0xAD }, + { PI_TDFI_WDQLVL_RW_F2, 0x0C }, + { PI_TDFI_WDQLVL_WR_F2, 0x17 }, + { PI_MBIST_TWCKENL_RD_ADJ_F2, 0x1C }, + { PI_MBIST_RDLAT_ADJ_F2, 0x2E }, + { PI_TWTR_S_F2, 0x09 }, + { PI_TWR_F2, 0x18 }, + { PI_TWTR_F2, 0x09 }, + { PI_TWTR_L_F2, 0x09 }, + { PI_TDFI_CTRLUPD_MAX_F2, 0x14F2 }, + { PI_TDFI_CTRLUPD_INTERVAL_F2, 0xD174 }, + { PI_TXSNR_F2, 0x10B }, + { PI_ZQRESET_F2, 0x0023 }, + { PI_TCBTRTW_F2, 0x07 }, + { PI_SEQ_WAIT_16_F2, 0x0000AD }, + { PI_SEQ_WAIT_21_F2, 0x000561 }, + { PI_SEQ_WAIT_23_F2, 0x000019 }, + { PI_SEQ_WAIT_24_F2, 0x000046 }, + { PI_SEQ_WAIT_25_F2, 0x00008B }, + { PI_SEQ_WAIT_26_F2, 0x00000A }, + { PI_SEQ_WAIT_30_F2, 0x000038 }, + { PI_TINIT_F2, 0x0219AF }, + { PI_TINIT1_F2, 0x0219AF }, + { PI_TINIT3_F2, 0x1500CF }, + { PI_TINIT4_F2, 0x000023 }, + { PI_TINIT5_F2, 0x000561 } +}; + +static const struct dbsc5_table_patch dbsc5_table_patch_slice_6000[] = { + { PHY_REGULATOR_EN_CNT, 0x1F }, + { PHY_RDDATA_EN_TSEL_DLY, 0x12 }, + { PHY_RDDATA_EN_OE_DLY, 0x15 }, + { PHY_WRLVL_RESP_WAIT_CNT, 0x3A }, + { PHY_RDLVL_MAX_EDGE, 0x01BD }, + { PHY_RDDATA_EN_DLY, 0x15 }, + { PHY_RDDQS_LATENCY_ADJUST, 0x07 }, + { PHY_RDDQS_GATE_SLAVE_DELAY, 0x1B }, + { PHY_GTLVL_LAT_ADJ_START, 0x06 }, + { PHY_LP4_BOOT_RX_PCLK_CLK_SEL, 0x00 } +}; + +static const struct dbsc5_table_patch dbsc5_table_patch_adr_v_6000[] = { + { PHY_ADR_MEAS_DLY_STEP_ENABLE, 0x00 }, + { PHY_ADR_CALVL_DLY_STEP, 0x02 } +}; + +static const struct dbsc5_table_patch dbsc5_table_patch_pi_6000[] = { + { PI_TDELAY_RDWR_2_BUS_IDLE_F2, 0x75 }, + { PI_RDLAT_ADJ_F2, 0x34 }, + { PI_TREF_F2, 0xB6B }, + { PI_TDFI_WRLVL_WW_F0, 0x31 }, + { PI_TDFI_WRLVL_WW_F1, 0x31 }, + { PI_TDFI_WRLVL_WW_F2, 0x31 }, + { PI_TVRCG_DISABLE_F2, 0x4D }, + { PI_TVRCG_ENABLE_F2, 0x98 }, + { PI_TMRWCKEL_F2, 0x0C }, + { PI_TFC_F2, 0xBC }, + { PI_TDFI_WDQLVL_RW_F2, 0x0C }, + { PI_MBIST_TWCKENL_RD_ADJ_F2, 0x1C }, + { PI_MBIST_RDLAT_ADJ_F2, 0x30 }, + { PI_TWR_F2, 0x1A }, + { PI_TDFI_CTRLUPD_MAX_F2, 0x16D6 }, + { PI_TDFI_CTRLUPD_INTERVAL_F2, 0xE45C }, + { PI_TXSNR_F2, 0x123 }, + { PI_ZQRESET_F2, 0x0026 }, + { PI_SEQ_WAIT_16_F2, 0x0000BC }, + { PI_SEQ_WAIT_21_F2, 0x0005DD }, + { PI_SEQ_WAIT_23_F2, 0x00001B }, + { PI_SEQ_WAIT_24_F2, 0x00004D }, + { PI_SEQ_WAIT_25_F2, 0x000098 }, + { PI_SEQ_WAIT_30_F2, 0x00003A }, + { PI_TINIT_F2, 0x024A16 }, + { PI_TINIT1_F2, 0x024A16 }, + { PI_TINIT3_F2, 0x16E4D8 }, + { PI_TINIT4_F2, 0x000026 }, + { PI_TINIT5_F2, 0x0005DD } +}; + +static const struct dbsc5_table_patch dbsc5_table_patch_slice_mbpsdiv_640 = { + PHY_DATA_DC_CAL_CLK_SEL, 0x05 +}; + +static const struct dbsc5_table_patch dbsc5_table_patch_adr_v_mbpsdiv_640 = { + PHY_CLK_DC_CAL_CLK_SEL, 0x04 +}; + +static const struct dbsc5_table_patch dbsc5_table_patch_adr_g_mbpsdiv_640 = { + PHY_CAL_CLK_SELECT_0, 0x05 +}; + +static const struct dbsc5_table_patch dbsc5_table_patch_slice_mbpsdiv_572 = { + PHY_RX_PCLK_CLK_SEL, 0x3 +}; + +static const struct dbsc5_table_patch dbsc5_table_patch_adr_g_mbpsdiv_572 = { + PHY_PAD_ACS_RX_PCLK_CLK_SEL, 0x03 +}; + +static const struct dbsc5_table_patch dbsc5_table_patch_adr_g_mbpsdiv_400[] = { + { PHY_PLL_CTRL, 0x1542 }, + { PHY_PLL_CTRL_8X, 0x3342 } +}; + +/* Array of addresses for setting PI_DARRAY3_0 in each CS and frequency-set */ +static const u32 PI_DARRAY3_0_CSx_Fx[CS_CNT][3] = { + { PI_DARRAY3_0_CS0_F0, PI_DARRAY3_0_CS0_F1, PI_DARRAY3_0_CS0_F2 }, + { PI_DARRAY3_0_CS1_F0, PI_DARRAY3_0_CS1_F1, PI_DARRAY3_0_CS1_F2 } +}; + +/* Array of addresses for setting PI_DARRAY3_1 in each CS and frequency-set */ +static const u32 PI_DARRAY3_1_CSx_Fx[CS_CNT][3] = { + { PI_DARRAY3_1_CS0_F0, PI_DARRAY3_1_CS0_F1, PI_DARRAY3_1_CS0_F2 }, + { PI_DARRAY3_1_CS1_F0, PI_DARRAY3_1_CS1_F1, PI_DARRAY3_1_CS1_F2 } +}; + +/* DBSC registers */ +#define DBSC_DBSYSCONF0 0x0 +#define DBSC_DBSYSCONF1 0x0 +#define DBSC_DBSYSCONF1A 0x4 +#define DBSC_DBSYSCONF2 0x4 +#define DBSC_DBPHYCONF0 0x8 +#define DBSC_DBSYSCONF2A 0x8 +#define DBSC_DBMEMKIND 0x20 +#define DBSC_DBMEMKINDA 0x20 +#define DBSC_DBMEMCONF(ch, cs) (0x30 + (0x2000 * ((ch) & 0x2)) + (0x10 * ((ch) & 0x1)) + (0x4 * (cs))) +#define DBSC_DBMEMCONFA(ch, cs) (0x30 + (0x4000 * ((ch) & 0x2)) + (0x10 * ((ch) & 0x1)) + (0x4 * (cs))) +#define DBSC_DBSYSCNT0 0x100 +#define DBSC_DBSYSCNT0A 0x100 +#define DBSC_DBACEN 0x200 +#define DBSC_DBRFEN 0x204 +#define DBSC_DBCMD 0x208 +#define DBSC_DBWAIT 0x210 +#define DBSC_DBBL 0x400 +#define DBSC_DBBLA 0x400 +#define DBSC_DBRFCNF1 0x414 +#define DBSC_DBRFCNF2 0x418 +#define DBSC_DBCALCNF 0x424 +#define DBSC_DBDBICNT 0x518 +#define DBSC_DBDFIPMSTRCNF 0x520 +#define DBSC_DBDFICUPDCNF 0x540 +#define DBSC_DBBCAMDIS 0x9FC +#define DBSC_DBSCHRW1 0x1024 +#define DBSC_DBSCHTR0 0x1030 +#define DBSC_DBTR(x) (0x300 + (0x4 * (x))) +#define DBSC_DBRNK(x) (0x430 + (0x4 * (x))) +#define DBSC_DBDFISTAT(ch) (0x600 + (0x2000 * ((ch) & 0x2)) + (0x40 * ((ch) & 0x1))) +#define DBSC_DBDFICNT(ch) (0x604 + (0x2000 * ((ch) & 0x2)) + (0x40 * ((ch) & 0x1))) +#define DBSC_DBPDCNT2(ch) (0x618 + (0x2000 * ((ch) & 0x2)) + (0x40 * ((ch) & 0x1))) +#define DBSC_DBPDLK(ch) (0x620 + (0x2000 * ((ch) & 0x2)) + (0x40 * ((ch) & 0x1))) +#define DBSC_DBPDRGA(ch) (0x624 + (0x2000 * ((ch) & 0x2)) + (0x40 * ((ch) & 0x1))) +#define DBSC_DBPDRGD(ch) (0x628 + (0x2000 * ((ch) & 0x2)) + (0x40 * ((ch) & 0x1))) +#define DBSC_DBPDRGM(ch) (0x62C + (0x2000 * ((ch) & 0x2)) + (0x40 * ((ch) & 0x1))) +#define DBSC_DBPDSTAT0(ch) (0x630 + (0x2000 * ((ch) & 0x2)) + (0x40 * ((ch) & 0x1))) +#define DBSC_DBPDSTAT1(ch) (0x634 + (0x2000 * ((ch) & 0x2)) + (0x40 * ((ch) & 0x1))) +#define DBSC_DBSCHFCTST0 0x1040 +#define DBSC_DBSCHFCTST1 0x1044 + +/* CPG PLL3 registers */ +#define CPG_CPGWPR 0x0 +#define CPG_FRQCRD0 0x80C +#define CPG_PLLECR 0x820 +#define CPG_PLL3CR0 0x83C +#define CPG_PLL3CR1 0x8C0 +#define CPG_FSRCHKCLRR4 0x590 +#define CPG_FSRCHKSETR4 0x510 +#define CPG_FSRCHKRA4 0x410 +#define CPG_SRCR4 0x2C10 +#define CPG_SRSTCLR4 0x2C90 + +#define CPG_FRQCRD_KICK_BIT BIT(31) +#define CPG_PLL3CR0_KICK_BIT BIT(31) +#define CPG_PLLECR_PLL3ST_BIT BIT(11) + +#define CLK_DIV(a, diva, b, divb) (((a) * (divb)) / ((b) * (diva))) + +struct renesas_dbsc5_board_config { + /* Channels in use */ + u8 bdcfg_phyvalid; + /* Read vref (SoC) training range */ + u32 bdcfg_vref_r; + /* Write vref (MR14, MR15) training range */ + u16 bdcfg_vref_w; + /* CA vref (MR12) training range */ + u16 bdcfg_vref_ca; + /* RFM required check */ + bool bdcfg_rfm_chk; + + /* Board parameter about channels */ + struct { + /* + * 0x00: 4Gb dual channel die / 2Gb single channel die + * 0x01: 6Gb dual channel die / 3Gb single channel die + * 0x02: 8Gb dual channel die / 4Gb single channel die + * 0x03: 12Gb dual channel die / 6Gb single channel die + * 0x04: 16Gb dual channel die / 8Gb single channel die + * 0x05: 24Gb dual channel die / 12Gb single channel die + * 0x06: 32Gb dual channel die / 16Gb single channel die + * 0x07: 24Gb single channel die + * 0x08: 32Gb single channel die + * 0xFF: NO_MEMORY + */ + u8 bdcfg_ddr_density[CS_CNT]; + /* SoC caX([6][5][4][3][2][1][0]) -> MEM caY: */ + u32 bdcfg_ca_swap; + /* SoC dqsX([1][0]) -> MEM dqsY: */ + u8 bdcfg_dqs_swap; + /* SoC dq([7][6][5][4][3][2][1][0]) -> MEM dqY/dm: (8 means DM) */ + u32 bdcfg_dq_swap[SLICE_CNT]; + /* SoC dm -> MEM dqY/dm: (8 means DM) */ + u8 bdcfg_dm_swap[SLICE_CNT]; + /* SoC ckeX([1][0]) -> MEM csY */ + u8 bdcfg_cs_swap; + } ch[4]; +}; + +struct renesas_dbsc5_dram_priv { + void __iomem *regs; + void __iomem *cpg_regs; + + /* The board parameter structure of the board */ + const struct renesas_dbsc5_board_config *dbsc5_board_config; + + /* The board clock frequency */ + u32 brd_clk; + u32 brd_clkdiv; + u32 brd_clkdiva; + + /* The Mbps of Bus */ + u32 bus_clk; + u32 bus_clkdiv; + + /* The Mbps of DDR */ + u32 ddr_mbps; + u32 ddr_mbpsdiv; + + /* DDR memory multiplier setting value */ + u32 ddr_mul; + u32 ddr_mul_nf; + u32 ddr_mul_low; + u32 ddr_mul_reg; + + /* Value indicating the enabled channel */ + u32 ddr_phyvalid; + + /* The tccd value of DDR */ + u32 ddr_tccd; + + /* Memory capacity in each channel and each CS */ + u8 ddr_density[DRAM_CH_CNT][CS_CNT]; + /* Channels used for each memory rank */ + u32 ch_have_this_cs[CS_CNT]; + /* The maximum memory capacity */ + u32 max_density; + + /* Index of jedec spec1 setting table you use */ + u32 js1_ind; + /* Array of jedec spec2 setting table */ + u32 js2[JS2_CNT]; + /* Read latency */ + u32 RL; + /* Write latency */ + u32 WL; + + /* Array for DDR PI Slice settings */ + u32 DDR_PI_REGSET[DDR_PI_REGSET_NUM_V4H]; + /* Array for DDRPHY Slice settings */ + u32 DDR_PHY_SLICE_REGSET[DDR_PHY_SLICE_REGSET_NUM_V4H]; + /* Array for DDRPHY ADRRESS VALUE Slice settings */ + u32 DDR_PHY_ADR_V_REGSET[DDR_PHY_SLICE_REGSET_NUM_V4H]; + /* Array for DDRPHY ADRRESS CONTROL Slice settings */ + u32 DDR_PHY_ADR_G_REGSET[DDR_PHY_SLICE_REGSET_NUM_V4H]; +}; + +static const struct renesas_dbsc5_board_config renesas_v4h_dbsc5_board_config = { + /* RENESAS V4H White Hawk (64Gbit 1rank) */ + .bdcfg_phyvalid = 0xF, + .bdcfg_vref_r = 0x0, + .bdcfg_vref_w = 0x0, + .bdcfg_vref_ca = 0x0, + .bdcfg_rfm_chk = true, + .ch = { + [0] = { + .bdcfg_ddr_density = { 0x06, 0xFF }, + .bdcfg_ca_swap = 0x04506132, + .bdcfg_dqs_swap = 0x01, + .bdcfg_dq_swap = { 0x26147085, 0x12306845 }, + .bdcfg_dm_swap = { 0x03, 0x07 }, + .bdcfg_cs_swap = 0x10 + }, + [1] = { + .bdcfg_ddr_density = { 0x06, 0xFF }, + .bdcfg_ca_swap = 0x02341065, + .bdcfg_dqs_swap = 0x10, + .bdcfg_dq_swap = { 0x56782314, 0x71048365 }, + .bdcfg_dm_swap = { 0x00, 0x02 }, + .bdcfg_cs_swap = 0x10 + }, + [2] = { + .bdcfg_ddr_density = { 0x06, 0xFF }, + .bdcfg_ca_swap = 0x02150643, + .bdcfg_dqs_swap = 0x10, + .bdcfg_dq_swap = { 0x58264071, 0x41207536 }, + .bdcfg_dm_swap = { 0x03, 0x08 }, + .bdcfg_cs_swap = 0x10 + }, + [3] = { + .bdcfg_ddr_density = { 0x06, 0xFF }, + .bdcfg_ca_swap = 0x01546230, + .bdcfg_dqs_swap = 0x01, + .bdcfg_dq_swap = { 0x45761328, 0x62801745 }, + .bdcfg_dm_swap = { 0x00, 0x03 }, + .bdcfg_cs_swap = 0x10 + } + } +}; + +/** + * r_vch_nxt() - Macro for channel selection loop + * + * Return the ID of the channel to be used. Check for valid channels + * between the value of posn and the maximum number of CHs. If a valid + * channel is found, returns the value of that channel. + */ +static u32 r_vch_nxt(struct udevice *dev, u32 pos) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + int posn; + + for (posn = pos; posn < DRAM_CH_CNT; posn++) + if (priv->ddr_phyvalid & BIT(posn)) + break; + + return posn; +} + +/* Select only valid channels in all channels from CH0. */ +#define r_foreach_vch(dev, ch) \ +for ((ch) = r_vch_nxt((dev), 0); (ch) < DRAM_CH_CNT; (ch) = r_vch_nxt((dev), (ch) + 1)) + +/* All channels are selected. */ +#define r_foreach_ech(ch) \ +for (ch = 0; ch < DRAM_CH_CNT; ch++) + +/** + * dbsc5_clk_cpg_write_32() - Write clock control register + * + * Write the complement value of setting value to the CPG_CPGWPR register + * for releaseing the protect. Write setting value to destination address. + */ +static void dbsc5_clk_cpg_write_32(struct udevice *dev, void __iomem *a, u32 v) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + + writel(~v, priv->cpg_regs + CPG_CPGWPR); + writel(v, a); +} + +enum dbsc5_clk_pll3_mode { + PLL3_LOW_FREQUENCY_MODE = 0, + PLL3_HIGH_FREQUENCY_MODE, + PLL3_HIGH_FREQUENCY_MODE_LOAD_REGISTER +}; + +/** + * dbsc5_clk_pll3_control() - Set PLL3 + * @dev: DBSC5 device + * @mode: PLL3 frequency mode + * + * Determine the set value according to the frequency mode of the argument. + * Write the set value to CPG_FRQCRD0 register and CPG_FRQCRD0 one. + * Reflect settings + */ +static void dbsc5_clk_pll3_control(struct udevice *dev, u32 mode) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + u32 data_div, data_mul, data_nf, ssmode, val; + int ret; + + /* + * PLL3VCO = EXTAL * priv->ddr_mul * 1/2 + * clk_ctlr_sync = PLL3VCO * pll3_div + * priv->ddr_mul = (NI[7:0] + 1) * 2 + NF[24:0] / 2^24 + */ + + switch (mode) { + case PLL3_LOW_FREQUENCY_MODE: + /* Low frequency mode (50MHz) */ + data_mul = (priv->ddr_mul_low / 2) - 1; /* PLL3VCO = 1600MHz */ + data_div = 0x9; /* div = 32 */ + data_nf = 0x0; + ssmode = 0x0; + break; + case PLL3_HIGH_FREQUENCY_MODE: + /* High frequency mode */ + data_mul = (priv->ddr_mul / 2) - 1; + data_div = 0x0; /* div = 2 */ + data_nf = priv->ddr_mul_nf; + ssmode = 0x4; + break; + case PLL3_HIGH_FREQUENCY_MODE_LOAD_REGISTER: + /* High frequency mode for loading to DDRPHY registers */ + data_mul = (priv->ddr_mul_reg / 2) - 1; + data_div = 0x0; /* div = 2 */ + data_nf = 0x0; + ssmode = 0x4; + break; + default: + printf("%s Mode %d not supported\n", __func__, mode); + hang(); + } + + data_mul = (data_mul << 20) | (ssmode << 16); + data_nf = data_nf << 21; + + if (((readl(priv->cpg_regs + CPG_PLL3CR0) & 0x3FFFFF7F) != data_mul) || + (readl(priv->cpg_regs + CPG_PLL3CR1) != data_nf)) { + /* PLL3CR0 multiplie set */ + dbsc5_clk_cpg_write_32(dev, priv->cpg_regs + CPG_PLL3CR0, data_mul); + /* PLL3CR1 multiplie set */ + dbsc5_clk_cpg_write_32(dev, priv->cpg_regs + CPG_PLL3CR1, data_nf); + dbsc5_clk_cpg_write_32(dev, priv->cpg_regs + CPG_PLL3CR0, + readl(priv->cpg_regs + CPG_PLL3CR0) | + CPG_PLL3CR0_KICK_BIT); + + ret = readl_poll_timeout(priv->cpg_regs + CPG_PLLECR, val, + (val & CPG_PLLECR_PLL3ST_BIT), + 1000000); + if (ret < 0) { + printf("%s CPG_PLLECR bit CPG_PLLECR_PLL3ST_BIT timeout\n", __func__); + hang(); + } + } + + /* PLL3 DIV set(Target value) */ + ret = readl_poll_timeout(priv->cpg_regs + CPG_FRQCRD0, val, + ((val & CPG_FRQCRD_KICK_BIT) == 0), + 1000000); + if (ret < 0) { + printf("%s CPG_FRQCRD0 bit CPG_FRQCRD_KICK_BIT div set timeout\n", __func__); + hang(); + } + + dbsc5_clk_cpg_write_32(dev, priv->cpg_regs + CPG_FRQCRD0, + (readl(priv->cpg_regs + CPG_FRQCRD0) & 0xFFFFFFF0) | + data_div); + dbsc5_clk_cpg_write_32(dev, priv->cpg_regs + CPG_FRQCRD0, + readl(priv->cpg_regs + CPG_FRQCRD0) | + CPG_FRQCRD_KICK_BIT); + ret = readl_poll_timeout(priv->cpg_regs + CPG_FRQCRD0, val, + ((val & CPG_FRQCRD_KICK_BIT) == 0), + 1000000); + if (ret < 0) { + printf("%s CPG_FRQCRD0 bit CPG_FRQCRD_KICK_BIT timeout\n", __func__); + hang(); + } +} + +/** + * dbsc5_clk_wait_freqchgreq() - Training handshake functions + * + * Check the value of the argument req_assert. If req_assert is 1, wait until + * FREQCHGREQ of all channels is 1 before time expires. If req_assert is 0, + * wait until FREQCHGREQ of all channels is 0 before time expires. Return the + * result of whether time has expired or not as a return value. + */ +static u32 dbsc5_clk_wait_freqchgreq(struct udevice *dev, u32 req_assert) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET; + u32 count = 0xFFFFFF; + u32 ch, reg; + + do { + reg = !!req_assert; + r_foreach_vch(dev, ch) + reg &= readl(regs_dbsc_d + DBSC_DBPDSTAT0(ch)); + count = count - 1; + } while (((reg & 0x1) != !!req_assert) && (count != 0)); + + return count == 0x0; +} + +/** + * dbsc5_clk_set_freqchgack() - Training handshake functions + * @dev: DBSC5 device + * @ack_assert: Select DBSC_DBPDCNT2 content + * + * Check the value of the argument ackassert. If the value of ackassert + * is greater than or equal to 0, write 0xCF01 to DBSC_DBPDCNT2. + * If the value of ackassert is 0, write 0x0 to DBSC_DBPDCNT2. + */ +static void dbsc5_clk_set_freqchgack(struct udevice *dev, u32 ack_assert) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET; + const u32 reg = ack_assert ? 0xcf01 : 0x0; + u32 ch; + + r_foreach_vch(dev, ch) + writel(reg, regs_dbsc_d + DBSC_DBPDCNT2(ch)); +} + +/** + * dbsc5_clk_wait_dbpdstat1() - Wait for status register update + * @dev: DBSC5 device + * @status: Expected status + * + * Read value the DBSC_DBPDSTAT1(ch) register. Wait until the contents + * of the status register are the same as status. + */ +static void dbsc5_clk_wait_dbpdstat1(struct udevice *dev, u32 status) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET; + u32 i, ch, reg; + + for (i = 0; i < 2; i++) { + do { + reg = status; + r_foreach_vch(dev, ch) + reg &= readl(regs_dbsc_d + DBSC_DBPDSTAT1(ch)); + } while (reg != status); + } +} + +/** + * dbsc5_clk_pll3_freq() - Set up the pll3 frequency + * @dev: DBSC5 device + * + * Wait for frequency change request. DBSC_DBPDSTAT0 value determines whether + * dbsc5_clk_pll3_control is called in low frequency mode or high frequency + * mode. Call dbsc5_clk_set_freqchgack(1) function. Check update completion until + * timeout. Call dbsc5_clk_set_freqchgack(0) function. If timed out, return with + * error log Wait for status register update. + */ +static int dbsc5_clk_pll3_freq(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET; + u32 fsel, timeout; + + dbsc5_clk_wait_freqchgreq(dev, 1); + + fsel = (readl(regs_dbsc_d + DBSC_DBPDSTAT0(0)) & 0x300) >> 8; + dbsc5_clk_pll3_control(dev, fsel ? PLL3_HIGH_FREQUENCY_MODE : + PLL3_LOW_FREQUENCY_MODE); + + dbsc5_clk_set_freqchgack(dev, 1); + timeout = dbsc5_clk_wait_freqchgreq(dev, 0); + dbsc5_clk_set_freqchgack(dev, 0); + + if (timeout) { + printf("Time out\n"); + return -ETIMEDOUT; + } + + dbsc5_clk_wait_dbpdstat1(dev, 0x7); + + return 0; +} + +/** + * dbsc5_reg_write() - Write DBSC register + * @addr: Destination address + * @data: Setting value to be written + * + * Write 32bit value @data to register at @addr . + */ +static void dbsc5_reg_write(void __iomem *addr, u32 data) +{ + writel(data, addr); + + if (((uintptr_t)addr & 0x000A0000) == 0x000A0000) + writel(data, addr + 0x4000); + else + writel(data, addr + 0x8000); +} + +/** + * dbsc5_reg_write() - DRAM Command Write Access + * @dev: DBSC5 device + * @cmd DRAM command. + * + * First, execute the dummy read to DBSC_DBCMD. + * Confirm that no DBSC command operation is in progress 0. + * Write the contents of the command to be sent to DRAM. + */ +static void dbsc5_send_dbcmd2(struct udevice *dev, u32 cmd) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET; + u32 val; + int ret; + + /* dummy read */ + readl(regs_dbsc_d + DBSC_DBCMD); + + ret = readl_poll_timeout(regs_dbsc_d + DBSC_DBWAIT, val, ((val & BIT(0)) == 0), 1000000); + if (ret < 0) { + printf("%s DBWAIT bit 0 timeout\n", __func__); + hang(); + } + + ret = readl_poll_timeout(regs_dbsc_d + DBSC_DBWAIT + 0x4000, val, ((val & BIT(0)) == 0), 1000000); + if (ret < 0) { + printf("%s DBWAIT + 0x4000 bit 0 timeout\n", __func__); + hang(); + } + + dbsc5_reg_write(regs_dbsc_d + DBSC_DBCMD, cmd); +} + +/** + * dbsc5_reg_ddrphy_read() - Read setting from DDR PHY register + * @dev: DBSC5 device + * @ch: Target channel + * @regadd: Destination address + * + * Write matching values to DBPDRGA register and read value out of DBSC_DBPDRGD. + * Wait until the write process completed in each step. + */ +static u32 dbsc5_reg_ddrphy_read(struct udevice *dev, u32 ch, u32 regadd) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET; + u32 val; + int ret; + + writel(regadd | BIT(14), regs_dbsc_d + DBSC_DBPDRGA(ch)); + ret = readl_poll_timeout(regs_dbsc_d + DBSC_DBPDRGA(ch), val, (val == (regadd | BIT(15) | BIT(14))), 1000000); + if (ret < 0) { + printf("%s regs_dbsc_d + DBSC_DBPDRGA timeout\n", __func__); + hang(); + } + + val = readl(regs_dbsc_d + DBSC_DBPDRGA(ch)); + + writel(regadd | BIT(15), regs_dbsc_d + DBSC_DBPDRGA(ch)); + ret = readl_poll_timeout(regs_dbsc_d + DBSC_DBPDRGA(ch), val, (val == regadd), 1000000); + if (ret < 0) { + printf("%s regs_dbsc_d + DBSC_DBPDRGA | BIT(15) timeout\n", __func__); + hang(); + } + + writel(regadd | BIT(15), regs_dbsc_d + DBSC_DBPDRGA(ch)); + ret = readl_poll_timeout(regs_dbsc_d + DBSC_DBPDRGA(ch), val, (val == regadd), 1000000); + if (ret < 0) { + printf("%s regs_dbsc_d + DBSC_DBPDRGA | BIT(15) again timeout\n", __func__); + hang(); + } + + return readl(regs_dbsc_d + DBSC_DBPDRGD(ch)); +} + +/** + * dbsc5_reg_ddrphy_write(dev, ) - Write setting to DDR PHY register + * @dev: DBSC5 device + * @ch: Target channel + * @regadd: Destination address + * @regdata: Value to be written + * + * Write matching values to DBPDRGA, DBPDRGD, DBPDRGA, DBPDRGA registers. + * Wait until the write process completed in each step. + */ +static void dbsc5_reg_ddrphy_write(struct udevice *dev, u32 ch, u32 regadd, u32 regdata) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET; + u32 val; + int ret; + + writel(regadd, regs_dbsc_d + DBSC_DBPDRGA(ch)); + ret = readl_poll_timeout(regs_dbsc_d + DBSC_DBPDRGA(ch), val, (val == regadd), 1000000); + if (ret < 0) { + printf("%s regs_dbsc_d + DBSC_DBPDRGA timeout\n", __func__); + hang(); + } + + writel(regdata, regs_dbsc_d + DBSC_DBPDRGD(ch)); + ret = readl_poll_timeout(regs_dbsc_d + DBSC_DBPDRGA(ch), val, (val == (regadd | BIT(15))), 1000000); + if (ret < 0) { + printf("%s regs_dbsc_d + DBSC_DBPDRGD timeout\n", __func__); + hang(); + } + + writel(regadd | BIT(15), regs_dbsc_d + DBSC_DBPDRGA(ch)); + ret = readl_poll_timeout(regs_dbsc_d + DBSC_DBPDRGA(ch), val, (val == regadd), 1000000); + if (ret < 0) { + printf("%s regs_dbsc_d + DBSC_DBPDRGA | BIT(15) timeout\n", __func__); + hang(); + } + + writel(regadd, regs_dbsc_d + DBSC_DBPDRGA(ch)); +} + +/* + * dbsc5_reg_ddrphy_write_all() - Write setting from DDR PHY register for all channels + * @dev: DBSC5 device + * @regadd: Destination address + * @regdata: Value to be written + * + * Wrapper around dbsc5_reg_ddrphy_write() for all channels. + */ +static void dbsc5_reg_ddrphy_write_all(struct udevice *dev, u32 regadd, u32 regdata) +{ + u32 ch; + + r_foreach_vch(dev, ch) + dbsc5_reg_ddrphy_write(dev, ch, regadd, regdata); +} + +/** + * dbsc5_reg_ddrphy_masked_write() - Write setting to DDR PHY register with mask + * @dev: DBSC5 device + * @ch: Target channel + * @regadd: Destination address + * @regdata: Value to be written + * @msk: Register mask + * + * Wrapper around dbsc5_reg_ddrphy_write() with DBPDRGM set. + */ +static void dbsc5_reg_ddrphy_masked_write(struct udevice *dev, u32 ch, u32 regadd, u32 regdata, u32 msk) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET; + u32 val; + int ret; + + writel(msk, regs_dbsc_d + DBSC_DBPDRGM(ch)); + ret = readl_poll_timeout(regs_dbsc_d + DBSC_DBPDRGM(ch), val, (val == msk), 1000000); + if (ret < 0) { + printf("%s regs_dbsc_d + DBSC_DBPDRGM timeout\n", __func__); + hang(); + } + + dbsc5_reg_ddrphy_write(dev, ch, regadd, regdata); + + writel(0, regs_dbsc_d + DBSC_DBPDRGM(ch)); + ret = readl_poll_timeout(regs_dbsc_d + DBSC_DBPDRGM(ch), val, (val == 0), 1000000); + if (ret < 0) { + printf("%s regs_dbsc_d + DBSC_DBPDRGM != 0 timeout\n", __func__); + hang(); + } +} + +/** + * dbsc5_ddr_setval_slice() - Write setting to DDR PHY hardware + * @dev: DBSC5 device + * @ch: Target channel + * @slice: Target slice + * @regdef: Encoded PHY/PI register and bitfield + * @val: Value to be written + * + * Calculate the bit field in which to write the setting value + * from encoded register and bitfield @regdef parameter. Call + * dbsc5_reg_ddrphy_masked_write() to write the value to hardware. + */ +static void dbsc5_ddr_setval_slice(struct udevice *dev, u32 ch, u32 slice, u32 regdef, u32 val) +{ + const u32 adr = DDR_REGDEF_ADR(regdef) + (0x100 * slice); + const u32 len = DDR_REGDEF_LEN(regdef); + const u32 lsb = DDR_REGDEF_LSB(regdef); + const u32 msk = (len == 32) ? 0xffffffff : ((BIT(len) - 1) << lsb); + const u32 dms = ~((!!(msk & BIT(24)) << 3) | (!!(msk & BIT(16)) << 2) | + (!!(msk & BIT(8)) << 1) | !!(msk & BIT(0))) & 0xf; + + dbsc5_reg_ddrphy_masked_write(dev, ch, adr, val << lsb, dms); +} + +/* + * dbsc5_ddr_setval() - Write setting from DDR PHY hardware slice 0 + * @dev: DBSC5 device + * @ch: Target channel + * @regdef: Encoded PHY/PI register and bitfield + * @val: Value to be written + * + * Wrapper around dbsc5_ddr_setval_slice() for slice 0. + */ +static void dbsc5_ddr_setval(struct udevice *dev, u32 ch, u32 regdef, u32 val) +{ + dbsc5_ddr_setval_slice(dev, ch, 0, regdef, val); +} + +/* + * dbsc5_ddr_setval_all_ch_slice() - Write setting from DDR PHY hardware for all channels and one slice + * @dev: DBSC5 device + * @slice: Target slice + * @regdef: Encoded PHY/PI register and bitfield + * @val: Value to be written + * + * Wrapper around dbsc5_ddr_setval_slice() for slice 0. + */ +static void dbsc5_ddr_setval_all_ch_slice(struct udevice *dev, u32 slice, u32 regdef, u32 val) +{ + u32 ch; + + r_foreach_vch(dev, ch) + dbsc5_ddr_setval_slice(dev, ch, slice, regdef, val); +} + +/* + * dbsc5_ddr_setval_all_ch() - Write setting from DDR PHY hardware for all channels and slice 0 + * @dev: DBSC5 device + * @regdef: Encoded PHY/PI register and bitfield + * @val: Value to be written + * + * Wrapper around dbsc5_ddr_setval_all_ch_slice() for slice 0. + */ +static void dbsc5_ddr_setval_all_ch(struct udevice *dev, u32 regdef, u32 val) +{ + dbsc5_ddr_setval_all_ch_slice(dev, 0, regdef, val); +} + +/* + * dbsc5_ddr_setval_all_ch_all_slice() - Write setting from DDR PHY hardware for all channels and all slices + * @dev: DBSC5 device + * @regdef: Encoded PHY/PI register and bitfield + * @val: Value to be written + * + * Wrapper around dbsc5_ddr_setval_all_ch_slice() for slice 0. + */ +static void dbsc5_ddr_setval_all_ch_all_slice(struct udevice *dev, u32 regdef, u32 val) +{ + u32 slice; + + for (slice = 0; slice < SLICE_CNT; slice++) + dbsc5_ddr_setval_all_ch_slice(dev, slice, regdef, val); +} + +/** + * dbsc5_ddr_getval_slice() - Read setting from DDR PHY/PI hardware + * @dev: DBSC5 device + * @ch: Target channel + * @slice: Target slice + * @regdef: Encoded PHY/PI register and bitfield + * + * Calculate the address and the bit-field from "regdef" value. + * Call dbsc5_reg_ddrphy_read() to read value from the target address. + */ +static u32 dbsc5_ddr_getval_slice(struct udevice *dev, u32 ch, u32 slice, u32 regdef) +{ + const u32 adr = DDR_REGDEF_ADR(regdef) + (0x100 * slice); + const u32 len = DDR_REGDEF_LEN(regdef); + const u32 lsb = DDR_REGDEF_LSB(regdef); + const u32 msk = (len == 32) ? 0xffffffff : (BIT(len) - 1); + + return (dbsc5_reg_ddrphy_read(dev, ch, adr) >> lsb) & msk; +} + +/** + * dbsc5_ddr_getval() - Read setting from DDR PHY/PI hardware slice 0 + * @dev: DBSC5 device + * @ch: Target channel + * @regdef: Encoded PHY/PI register and bitfield + * + * Wrapper around dbsc5_ddr_getval_slice() for slice 0. + */ +static u32 dbsc5_ddr_getval(struct udevice *dev, u32 ch, u32 regdef) +{ + return dbsc5_ddr_getval_slice(dev, ch, 0, regdef); +} + +/** + * dbsc5_table_patch_set() - Modify DDR PHY/PI settings table + * @tbl: DDR PHY/PI setting table pointer + * @adrmsk_pi: Use wider address mask for PI register + * @patch: List of modifications to the settings table + * @patchlen: Length of the list of modifications to the settings table + * + * Calculate the target index of settings table, calculate the bit-field + * to write the setting value, and write the setting value to the target + * bit-field in the index. + */ +static void dbsc5_table_patch_set(u32 *tbl, const bool adrmsk_pi, + const struct dbsc5_table_patch *patch, + int patchlen) +{ + const u32 adrmsk = adrmsk_pi ? 0x7FF : 0xFF; + u32 adr, len, lsb, msk; + int i; + + for (i = 0; i < patchlen; i++) { + adr = DDR_REGDEF_ADR(patch[i].reg); + len = DDR_REGDEF_LEN(patch[i].reg); + lsb = DDR_REGDEF_LSB(patch[i].reg); + msk = (len == 32) ? 0xffffffff : ((BIT(len) - 1) << lsb); + + tbl[adr & adrmsk] &= ~msk; + tbl[adr & adrmsk] |= (patch[i].val << lsb) & msk; + } +} + +/** + * dbsc5_ddrtbl_getval() - Read setting from DDR PHY/PI settings table + * @tbl: DDR PHY/PI setting table pointer + * @regdef: Encoded PHY/PI register and bitfield + * @adrmsk_pi: Use wider address mask for PI register + * + * Calculate the target index of *tbl and the bit-field to read the + * setting value and read and return the setting value from the target + * bit-field in the index. + */ +static u32 dbsc5_ddrtbl_getval(const u32 *tbl, u32 regdef, bool adrmsk_pi) +{ + const u32 adrmsk = adrmsk_pi ? 0x7FF : 0xFF; + const u32 adr = DDR_REGDEF_ADR(regdef); + const u32 len = DDR_REGDEF_LEN(regdef); + const u32 lsb = DDR_REGDEF_LSB(regdef); + const u32 msk = (len == 32) ? 0xffffffff : (BIT(len) - 1); + + return (tbl[adr & adrmsk] >> lsb) & msk; +} + +/** + * dbsc5_f_scale() - Calculate the best value for DBSC timing setting + * @priv: Driver private data + * @frac: Perform fractional rounding + * @ps Optimal setting value in pico second + * @cyc Optimal setting value in cycle count + * + * Convert the optimal value in pico second to in cycle count. Optionally, if @frac is true, + * perform fractional rounding. Compare the value of the result of the conversion with the + * value of the argument @cyc and return the larger value. + */ +static u32 dbsc5_f_scale(struct renesas_dbsc5_dram_priv *priv, const bool frac, u32 ps, u32 cyc) +{ + const u32 mul = frac ? 8 : 800000; + const u32 tmp = DIV_ROUND_UP(ps, 10UL) * priv->ddr_mbps; + const u32 f_scale_div = DIV_ROUND_UP(tmp, mul * priv->ddr_mbpsdiv); + + return (f_scale_div > cyc) ? f_scale_div : cyc; +} + +/** + * dbsc5_f_scale_js2() - Select optimal settings based on jedec_spec2 + * @priv: Driver private data + * + * Calculate and assign each setting value of jedec_spec2 by "dbsc5_f_scale" function. + * Only the following array elements are calculated using different formulas from those + * described above -- JS2_tRRD/JS2_tFAW/JS2_tZQCALns/JS2_tRCpb/JS2_tRCab. + */ +static void dbsc5_f_scale_js2(struct renesas_dbsc5_dram_priv *priv) +{ + const int derate = 0; + int i; + + for (i = 0; i < JS2_TBLCNT; i++) { + priv->js2[i] = dbsc5_f_scale(priv, false, + jedec_spec2[derate][i].ps, + jedec_spec2[derate][i].cyc); + } + + priv->js2[JS2_tZQCALns] = dbsc5_f_scale(priv, false, + jedec_spec2[derate][JS2_tZQCALns].ps * 1000UL, 0); + priv->js2[JS2_tDQ72DQns] = dbsc5_f_scale(priv, false, + jedec_spec2[derate][JS2_tDQ72DQns].ps * 1000UL, 0); + priv->js2[JS2_tCAENTns] = dbsc5_f_scale(priv, false, + jedec_spec2[derate][JS2_tCAENTns].ps * 1000UL, 0); + priv->js2[JS2_tRCpb] = priv->js2[JS2_tRAS] + priv->js2[JS2_tRPpb]; + priv->js2[JS2_tRCab] = priv->js2[JS2_tRAS] + priv->js2[JS2_tRPab]; + priv->js2[JS2_tRFCab] = dbsc5_f_scale(priv, false, + jedec_spec2_tRFC_ab[priv->max_density] * 1000UL, 0); + + priv->js2[JS2_tRBTP] = dbsc5_f_scale(priv, false, 7500, 2) - 2; + priv->js2[JS2_tXSR] = priv->js2[JS2_tRFCab] + + dbsc5_f_scale(priv, false, 7500, 2); + priv->js2[JS2_tPDN] = dbsc5_f_scale(priv, false, 10000, 0) + 1; + priv->js2[JS2_tPDN_DSM] = dbsc5_f_scale(priv, true, + jedec_spec2[derate][JS2_tPDN_DSM].ps * 10UL, 0); + priv->js2[JS2_tXSR_DSM] = dbsc5_f_scale(priv, true, + jedec_spec2[derate][JS2_tXSR_DSM].ps * 10UL, 0); + priv->js2[JS2_tXDSM_XP] = dbsc5_f_scale(priv, true, + jedec_spec2[derate][JS2_tXDSM_XP].ps * 10UL, 0); + priv->js2[JS2_tWLWCKOFF] = dbsc5_f_scale(priv, false, 14000, 5); +} + +/** + * dbsc5_ddrtbl_calc() - Calculate JS1/JS2 + * @priv: Driver private data + * + * Determine jedec_spec1 configuration table based on priv->ddr_mbps + * and priv->ddr_mbpsdiv. Calculate the value of the jedec_spec2 + * configuration table from priv->ddr_mbps and priv->ddr_mbpsdiv. + */ +static void dbsc5_ddrtbl_calc(struct renesas_dbsc5_dram_priv *priv) +{ + int i; + + /* Search jedec_spec1 index */ + for (i = JS1_USABLEC_SPEC_LO; i < JS1_FREQ_TBL_NUM - 1; i++) + if (js1[i].fx3 * 2 * priv->ddr_mbpsdiv >= priv->ddr_mbps * 3) + break; + + priv->js1_ind = max(i, JS1_USABLEC_SPEC_HI); + + priv->RL = js1[priv->js1_ind].RLset1; + priv->WL = js1[priv->js1_ind].WLsetA; + + /* Calculate jedec_spec2 */ + dbsc5_f_scale_js2(priv); +}; + +/** + * dbsc5_ddrtbl_load() Load table data into DDR registers + * @dev: DBSC5 device + * + * Copy the base configuration table to a local array. Change PI register table + * settings to match priv->ddr_mbps and priv->ddr_mbpsdiv. + * + * If the set value vref_r is not 0, change the "Read Vref (SoC side) Training range" + * setting in the configuration table. + * + * If the set value vref_w is not 0, change the "Write Vref (MR14, MR15) Training range" + * setting in the configuration table. + * + * If the set value vref_ca is not 0, change the "CA Vref (MR12) Training range" + * setting in the configuration table. + * + * If priv->ddr_mbps/priv->ddr_mbpsdiv is less than 5120, + * change the contents of the PHY register setting table. + * If priv->ddr_mbps/priv->ddr_mbpsdiv is less than 4576, + * change the contents of the PHY register setting table. + * + * Reflect the contents of the configuration table in the register. + */ +static void dbsc5_ddrtbl_load(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + const struct dbsc5_table_patch dbsc5_table_patch_adr_g_mbps = { + PHY_CAL_INTERVAL_COUNT_0, 10000 * priv->ddr_mbps / priv->ddr_mbpsdiv / 8 / 256, + }; + + const struct dbsc5_table_patch dbsc5_table_patch_pi_js[] = { + { PI_WRLAT_F2, priv->WL }, + { PI_TWCKENL_WR_ADJ_F2, (js1[priv->js1_ind].WCKENLW * 4) + 4 }, + { PI_TWCKENL_RD_ADJ_F2, (js1[priv->js1_ind].WCKENLR * 4) + 4 }, + { PI_TWCKPRE_STATIC_F2, (js1[priv->js1_ind].WCKPRESTA * 4) }, + { PI_TWCKPRE_TOGGLE_RD_F2, (js1[priv->js1_ind].WCKPRETGLR) * 4 }, + { PI_CASLAT_F2, priv->RL }, + { PI_TWCKENL_FS_ADJ_F2, (js1[priv->js1_ind].WCKENLF * 4) + 4 }, + { PI_TRFC_F2, priv->js2[JS2_tRFCab] }, + { PI_WRLVL_WCKOFF_F2, (priv->js2[JS2_tWLWCKOFF]) + 3 }, + { PI_WRLAT_ADJ_F2, (priv->WL * 4) + 2 }, + { PI_TCAENT_F2, priv->js2[JS2_tCAENTns] }, + { PI_TVREF_LONG_F2, (priv->js2[JS2_tCAENTns]) + 1 }, + { PI_TVREF_SHORT_F2, (priv->js2[JS2_tCAENTns]) + 1 }, + { PI_TRCD_F2, priv->js2[JS2_tRCD] }, + { PI_TRP_F2, priv->js2[JS2_tRPab] }, + { PI_TRTP_F2, js1[priv->js1_ind].nRBTP }, + { PI_TRAS_MIN_F2, priv->js2[JS2_tRAS] }, + { PI_TMRD_F2, (priv->js2[JS2_tMRD]) + 1 }, + { PI_TSR_F2, priv->js2[JS2_tSR] }, + { PI_TZQCAL_F2, priv->js2[JS2_tZQCALns] }, + { PI_TZQLAT_F2, priv->js2[JS2_tZQLAT] }, + { PI_TDQ72DQ_F2, priv->js2[JS2_tDQ72DQns] }, + { PI_MC_TRFC_F2, priv->js2[JS2_tRFCab] }, + }; + + const u32 vref_r = priv->dbsc5_board_config->bdcfg_vref_r; + const struct dbsc5_table_patch dbsc5_table_patch_slice_vref_r[] = { + { PHY_VREF_INITIAL_START_POINT, vref_r & 0xFF }, + { PHY_VREF_INITIAL_STOP_POINT, (vref_r & 0xFF00) >> 8 }, + { PHY_VREF_INITIAL_STEPSIZE, (vref_r & 0xFF0000) >> 16 } + }; + + const u32 vref_w = priv->dbsc5_board_config->bdcfg_vref_w; + const struct dbsc5_table_patch dbsc5_table_patch_pi_vref_w[] = { + { PI_WDQLVL_VREF_INITIAL_START_POINT_F0, vref_w & 0xff }, + { PI_WDQLVL_VREF_INITIAL_START_POINT_F1, vref_w & 0xff }, + { PI_WDQLVL_VREF_INITIAL_START_POINT_F2, vref_w & 0xff }, + { PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0, (vref_w & 0xff00) >> 8 }, + { PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1, (vref_w & 0xff00) >> 8 }, + { PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2, (vref_w & 0xff00) >> 8 } + }; + + const u32 vref_ca = priv->dbsc5_board_config->bdcfg_vref_ca; + const struct dbsc5_table_patch dbsc5_table_patch_pi_vref_ca[] = { + { PI_CALVL_VREF_INITIAL_START_POINT_F0, vref_ca & 0xff }, + { PI_CALVL_VREF_INITIAL_START_POINT_F1, vref_ca & 0xff }, + { PI_CALVL_VREF_INITIAL_START_POINT_F2, vref_ca & 0xff }, + { PI_CALVL_VREF_INITIAL_STOP_POINT_F0, (vref_ca & 0xff00) >> 8 }, + { PI_CALVL_VREF_INITIAL_STOP_POINT_F1, (vref_ca & 0xff00) >> 8 }, + { PI_CALVL_VREF_INITIAL_STOP_POINT_F2, (vref_ca & 0xff00) >> 8 } + }; + + int i, cs, slice; + u32 adr; + + /* Prepare register tables */ + memcpy(priv->DDR_PHY_SLICE_REGSET, DDR_PHY_SLICE_REGSET_V4H, sizeof(DDR_PHY_SLICE_REGSET_V4H)); + memcpy(priv->DDR_PHY_ADR_V_REGSET, DDR_PHY_ADR_V_REGSET_V4H, sizeof(DDR_PHY_ADR_V_REGSET_V4H)); + memcpy(priv->DDR_PHY_ADR_G_REGSET, DDR_PHY_ADR_G_REGSET_V4H, sizeof(DDR_PHY_ADR_G_REGSET_V4H)); + memcpy(priv->DDR_PI_REGSET, DDR_PI_REGSET_V4H, sizeof(DDR_PI_REGSET_V4H)); + + /* Adjust PI parameters */ + dbsc5_table_patch_set(priv->DDR_PHY_ADR_G_REGSET, false, + &dbsc5_table_patch_adr_g_mbps, 1); + dbsc5_table_patch_set(priv->DDR_PI_REGSET, true, + dbsc5_table_patch_pi_js, + ARRAY_SIZE(dbsc5_table_patch_pi_js)); + + if (priv->ddr_mbps < (3201 * priv->ddr_mbpsdiv)) { + /* 2751-3200 */ + dbsc5_table_patch_set(priv->DDR_PHY_SLICE_REGSET, false, + dbsc5_table_patch_slice_3200, + ARRAY_SIZE(dbsc5_table_patch_slice_3200)); + dbsc5_table_patch_set(priv->DDR_PHY_ADR_V_REGSET, false, + dbsc5_table_patch_adr_v_3200, + ARRAY_SIZE(dbsc5_table_patch_adr_v_3200)); + dbsc5_table_patch_set(priv->DDR_PI_REGSET, true, + dbsc5_table_patch_pi_3200, + ARRAY_SIZE(dbsc5_table_patch_pi_3200)); + } else if (priv->ddr_mbps < (3734 * priv->ddr_mbpsdiv)) { + /* 3201-3733 */ + dbsc5_table_patch_set(priv->DDR_PHY_SLICE_REGSET, false, + dbsc5_table_patch_slice_3733, + ARRAY_SIZE(dbsc5_table_patch_slice_3733)); + dbsc5_table_patch_set(priv->DDR_PHY_ADR_V_REGSET, false, + dbsc5_table_patch_adr_v_3733, + ARRAY_SIZE(dbsc5_table_patch_adr_v_3733)); + dbsc5_table_patch_set(priv->DDR_PI_REGSET, true, + dbsc5_table_patch_pi_3733, + ARRAY_SIZE(dbsc5_table_patch_pi_3733)); + } else if (priv->ddr_mbps < (4268 * priv->ddr_mbpsdiv)) { + /* 3734-4267 */ + dbsc5_table_patch_set(priv->DDR_PHY_SLICE_REGSET, false, + dbsc5_table_patch_slice_4266, + ARRAY_SIZE(dbsc5_table_patch_slice_4266)); + dbsc5_table_patch_set(priv->DDR_PHY_ADR_V_REGSET, false, + dbsc5_table_patch_adr_v_4266, + ARRAY_SIZE(dbsc5_table_patch_adr_v_4266)); + dbsc5_table_patch_set(priv->DDR_PI_REGSET, true, + dbsc5_table_patch_pi_4266, + ARRAY_SIZE(dbsc5_table_patch_pi_4266)); + } else if (priv->ddr_mbps < (4801 * priv->ddr_mbpsdiv)) { + /* 4269-4800 */ + dbsc5_table_patch_set(priv->DDR_PHY_SLICE_REGSET, false, + dbsc5_table_patch_slice_4800, + ARRAY_SIZE(dbsc5_table_patch_slice_4800)); + dbsc5_table_patch_set(priv->DDR_PHY_ADR_V_REGSET, false, + dbsc5_table_patch_adr_v_4800, + ARRAY_SIZE(dbsc5_table_patch_adr_v_4800)); + dbsc5_table_patch_set(priv->DDR_PI_REGSET, true, + dbsc5_table_patch_pi_4800, + ARRAY_SIZE(dbsc5_table_patch_pi_4800)); + } else if (priv->ddr_mbps < (5501 * priv->ddr_mbpsdiv)) { + /* 4801 - 5500 */ + dbsc5_table_patch_set(priv->DDR_PHY_SLICE_REGSET, false, + dbsc5_table_patch_slice_5500, + ARRAY_SIZE(dbsc5_table_patch_slice_5500)); + dbsc5_table_patch_set(priv->DDR_PHY_ADR_V_REGSET, false, + dbsc5_table_patch_adr_v_5500, + ARRAY_SIZE(dbsc5_table_patch_adr_v_5500)); + dbsc5_table_patch_set(priv->DDR_PI_REGSET, true, + dbsc5_table_patch_pi_5500, + ARRAY_SIZE(dbsc5_table_patch_pi_5500)); + } else if (priv->ddr_mbps < (6001 * priv->ddr_mbpsdiv)) { + /* 5501 - 6000 */ + dbsc5_table_patch_set(priv->DDR_PHY_SLICE_REGSET, false, + dbsc5_table_patch_slice_6000, + ARRAY_SIZE(dbsc5_table_patch_slice_6000)); + dbsc5_table_patch_set(priv->DDR_PHY_ADR_V_REGSET, false, + dbsc5_table_patch_adr_v_6000, + ARRAY_SIZE(dbsc5_table_patch_adr_v_6000)); + dbsc5_table_patch_set(priv->DDR_PI_REGSET, true, + dbsc5_table_patch_pi_6000, + ARRAY_SIZE(dbsc5_table_patch_pi_6000)); + } + + for (cs = 0; cs < CS_CNT; cs++) { + struct dbsc5_table_patch dbsc5_table_patch_pi_mr12[] = { + { PI_DARRAY3_0_CSx_Fx[cs][2], js1[priv->js1_ind].MR1 }, + { PI_DARRAY3_1_CSx_Fx[cs][2], js1[priv->js1_ind].MR2 }, + }; + + dbsc5_table_patch_set(priv->DDR_PI_REGSET, true, + dbsc5_table_patch_pi_mr12, + ARRAY_SIZE(dbsc5_table_patch_pi_mr12)); + } + + /* Read Vref (SoC side) Training range */ + if (priv->dbsc5_board_config->bdcfg_vref_r) { + dbsc5_table_patch_set(priv->DDR_PHY_SLICE_REGSET, false, + dbsc5_table_patch_slice_vref_r, + ARRAY_SIZE(dbsc5_table_patch_slice_vref_r)); + } + + /* Write Vref (MR14, MR15) Training range */ + if (priv->dbsc5_board_config->bdcfg_vref_w) { + dbsc5_table_patch_set(priv->DDR_PI_REGSET, true, + dbsc5_table_patch_pi_vref_w, + ARRAY_SIZE(dbsc5_table_patch_pi_vref_w)); + } + + /* CA Vref (MR12) Training range */ + if (priv->dbsc5_board_config->bdcfg_vref_ca) { + dbsc5_table_patch_set(priv->DDR_PI_REGSET, true, + dbsc5_table_patch_pi_vref_ca, + ARRAY_SIZE(dbsc5_table_patch_pi_vref_ca)); + } + + /* Low Freq setting */ + if (priv->ddr_mbps < (8 * 640 * priv->ddr_mbpsdiv)) { + /* CAL_CLK(10-20MHz) */ + dbsc5_table_patch_set(priv->DDR_PHY_SLICE_REGSET, false, + &dbsc5_table_patch_slice_mbpsdiv_640, 1); + dbsc5_table_patch_set(priv->DDR_PHY_ADR_V_REGSET, false, + &dbsc5_table_patch_adr_v_mbpsdiv_640, 1); + dbsc5_table_patch_set(priv->DDR_PHY_ADR_G_REGSET, false, + &dbsc5_table_patch_adr_g_mbpsdiv_640, 1); + } + + if (priv->ddr_mbps < (8 * 572 * priv->ddr_mbpsdiv)) { + /* CAL_CLK(10-20MHz) */ + dbsc5_table_patch_set(priv->DDR_PHY_SLICE_REGSET, false, + &dbsc5_table_patch_slice_mbpsdiv_572, 1); + dbsc5_table_patch_set(priv->DDR_PHY_ADR_G_REGSET, false, + &dbsc5_table_patch_adr_g_mbpsdiv_572, 1); + } + + if (priv->ddr_mbps < (8 * 401 * priv->ddr_mbpsdiv)) { + dbsc5_table_patch_set(priv->DDR_PHY_ADR_G_REGSET, false, + dbsc5_table_patch_adr_g_mbpsdiv_400, + ARRAY_SIZE(dbsc5_table_patch_adr_g_mbpsdiv_400)); + } + + /* SET DATA SLICE TABLE */ + for (slice = 0; slice < SLICE_CNT; slice++) { + adr = DDR_PHY_SLICE_REGSET_OFS_V4H + (DDR_PHY_SLICE_REGSET_SIZE_V4H * slice); + for (i = 0; i < DDR_PHY_SLICE_REGSET_NUM_V4H; i++) + dbsc5_reg_ddrphy_write_all(dev, adr + i, priv->DDR_PHY_SLICE_REGSET[i]); + } + + /* SET ADR SLICE TABLE */ + for (i = 0; i < DDR_PHY_ADR_V_REGSET_NUM_V4H; i++) + dbsc5_reg_ddrphy_write_all(dev, DDR_PHY_ADR_V_REGSET_OFS_V4H + i, priv->DDR_PHY_ADR_V_REGSET[i]); + + /* SET ADRCTRL SLICE TABLE */ + for (i = 0; i < DDR_PHY_ADR_G_REGSET_NUM_V4H; i++) + dbsc5_reg_ddrphy_write_all(dev, DDR_PHY_ADR_G_REGSET_OFS_V4H + i, priv->DDR_PHY_ADR_G_REGSET[i]); + + /* SET PI REGISTERS */ + for (i = 0; i < DDR_PI_REGSET_NUM_V4H; i++) + dbsc5_reg_ddrphy_write_all(dev, DDR_PI_REGSET_OFS_V4H + i, priv->DDR_PI_REGSET[i]); +} + +/** + * dbsc5_ddr_config() - Configure DDR registers + * @dev: DBSC5 device + * + * Set up wiring for DQ and DM pins and VREF_DRIVING. Set the CA pin wiring + * and ADR_CALVL_SWIZZLE settings. Make wiring settings for the CS pin. When + * memory rank is 1, set RANK setting to 1 to disable CS training. Configure + * the DATA_BYTE_SWAP setting. + */ +static void dbsc5_ddr_config(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + u32 ca_swap, cs_swap, dqs_swap; + u32 ch, slice; + + r_foreach_vch(dev, ch) { + /* Board settings (DQ, DM, VREF_DRIVING) */ + dqs_swap = priv->dbsc5_board_config->ch[ch].bdcfg_dqs_swap; + for (slice = 0; slice < SLICE_CNT; slice++) { + dbsc5_ddr_setval_slice(dev, ch, slice, PHY_DQ_DM_SWIZZLE0, + priv->dbsc5_board_config->ch[ch].bdcfg_dq_swap[slice]); + dbsc5_ddr_setval_slice(dev, ch, slice, PHY_DQ_DM_SWIZZLE1, + priv->dbsc5_board_config->ch[ch].bdcfg_dm_swap[slice]); + dbsc5_ddr_setval_slice(dev, ch, slice, PHY_CALVL_VREF_DRIVING_SLICE, + !((dqs_swap >> (4 * slice)) & 1)); + } + dbsc5_ddr_setval(dev, ch, PHY_DATA_BYTE_ORDER_SEL, + priv->dbsc5_board_config->ch[ch].bdcfg_dqs_swap | 0x76543200); + + /* Board settings (CA, ADDR_MUX) */ + ca_swap = priv->dbsc5_board_config->ch[ch].bdcfg_ca_swap; + + /* ADDR_MUX */ + dbsc5_ddr_setval(dev, ch, PI_ADDR_MUX_0, ca_swap & 0xf); + ca_swap >>= 4; + dbsc5_ddr_setval(dev, ch, PI_ADDR_MUX_1, ca_swap & 0xf); + ca_swap >>= 4; + dbsc5_ddr_setval(dev, ch, PI_ADDR_MUX_2, ca_swap & 0xf); + ca_swap >>= 4; + dbsc5_ddr_setval(dev, ch, PI_ADDR_MUX_3, ca_swap & 0xf); + ca_swap >>= 4; + dbsc5_ddr_setval(dev, ch, PI_ADDR_MUX_4, ca_swap & 0xf); + ca_swap >>= 4; + dbsc5_ddr_setval(dev, ch, PI_ADDR_MUX_5, ca_swap & 0xf); + ca_swap >>= 4; + dbsc5_ddr_setval(dev, ch, PI_ADDR_MUX_6, ca_swap & 0xf); + ca_swap >>= 4; + + /* ADR_CALVL_SWIZZLE */ + ca_swap = priv->dbsc5_board_config->ch[ch].bdcfg_ca_swap; + dbsc5_ddr_setval(dev, ch, PHY_ADR_CALVL_SWIZZLE0, ca_swap & 0x0fffffff); + + /* Board settings (CS) */ + /* CKE_MUX */ + /* SoC CKE -> DRAM CS */ + cs_swap = priv->dbsc5_board_config->ch[ch].bdcfg_cs_swap; + dbsc5_ddr_setval(dev, ch, PI_CKE_MUX_0, (cs_swap & 0xf) + 2); + dbsc5_ddr_setval(dev, ch, PI_CKE_MUX_1, ((cs_swap >> 4) & 0xf) + 2); + dbsc5_ddr_setval(dev, ch, PHY_CS_ACS_ALLOCATION_BIT2_2, (cs_swap & 0xf) + 1); + dbsc5_ddr_setval(dev, ch, PHY_CS_ACS_ALLOCATION_BIT3_2, ((cs_swap >> 4) & 0xf) + 1); + + /* Mask CS_MAP if RANK1 is not found */ + if (!(priv->ch_have_this_cs[1] & BIT(ch))) { + dbsc5_ddr_setval(dev, ch, PHY_ADR_CALVL_RANK_CTRL, 0x0); + for (slice = 0; slice < SLICE_CNT; slice++) + dbsc5_ddr_setval_slice(dev, ch, slice, PHY_PER_CS_TRAINING_EN, 0x0); + } + } + + r_foreach_vch(dev, ch) { + /* DATA_BYTE_SWAP */ + dqs_swap = priv->dbsc5_board_config->ch[ch].bdcfg_dqs_swap; + + dbsc5_ddr_setval(dev, ch, PI_DATA_BYTE_SWAP_EN, 0x1); + dbsc5_ddr_setval(dev, ch, PI_DATA_BYTE_SWAP_SLICE0, dqs_swap & 0xf); + dbsc5_ddr_setval(dev, ch, PI_DATA_BYTE_SWAP_SLICE1, (dqs_swap >> 4) & 0xf); + + if (!(priv->ch_have_this_cs[1] & BIT(ch))) + dbsc5_ddr_setval(dev, ch, PI_CS_MAP, 0x1); + } +} + +/** + * dbsc5_dbsc_regset_pre() - Configure primary DDR registers + * @dev: DBSC5 device + * + * Set SDRAM type, Burst length, and PHY type. Frequency mode setting. + * Write SDRAM configuration contents to registers. + */ +static void dbsc5_dbsc_regset_pre(struct udevice *dev) +{ +#define DBMEMCONF_REG(d3, row, bg, bank, col, dw) \ + (((d3) << 30) | ((row) << 24) | ((bg) << 20) | ((bank) << 16) | ((col) << 8) | (dw)) +#define DBMEMCONF_REGD(density) /* 16bit */ \ + DBMEMCONF_REG(((density) % 2), ((((density) + 1) / 2) + (28 - 2 - 2 - 10 - 1)), 2, 2, 10, 1) + + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + void __iomem *regs_dbsc_a = priv->regs + DBSC5_DBSC_A_OFFSET; + void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET; + u32 density; + u32 ch, cs; + + /* Primary settings */ + /* LPDDR5, BL=16, DFI interface */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBMEMKIND, 0xC); + dbsc5_reg_write(regs_dbsc_a + DBSC_DBMEMKINDA, 0xC); + dbsc5_reg_write(regs_dbsc_d + DBSC_DBBL, 0x2); + dbsc5_reg_write(regs_dbsc_a + DBSC_DBBLA, 0x2); + dbsc5_reg_write(regs_dbsc_d + DBSC_DBPHYCONF0, 0x1); + + dbsc5_reg_write(regs_dbsc_a + DBSC_DBSYSCONF0, 0x1); + + /* FREQRATIO=2 */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBSYSCONF1, 0x20000); + dbsc5_reg_write(regs_dbsc_a + DBSC_DBSYSCONF1A, 0x0); + + dbsc5_reg_write(regs_dbsc_d + DBSC_DBSYSCONF2, 0x1); + dbsc5_reg_write(regs_dbsc_a + DBSC_DBSYSCONF2A, 0x241); + + r_foreach_ech(ch) { + for (cs = 0; cs < CS_CNT; cs++) { + if (priv->ddr_density[ch][cs] == 0xFF) { + writel(0x00, regs_dbsc_d + DBSC_DBMEMCONF(ch, cs)); + writel(0x00, regs_dbsc_a + DBSC_DBMEMCONFA(ch, cs)); + } else { + density = priv->ddr_density[ch][cs]; + writel(DBMEMCONF_REGD(density), + regs_dbsc_d + DBSC_DBMEMCONF(ch, cs)); + writel(DBMEMCONF_REGD(density), + regs_dbsc_a + DBSC_DBMEMCONFA(ch, cs)); + } + } + } +} + +/** + * dbsc5_dbsc_regset() - Set DBSC timing parameters + * @dev: DBSC5 device + * + * Set the timing registers of the DBSC. + * Configure Scheduler settings. + */ +static void dbsc5_dbsc_regset(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + void __iomem *regs_dbsc_a = priv->regs + DBSC5_DBSC_A_OFFSET; + void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET; + u32 tmp[4]; + + /* DBTR0.CL : RL */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(0), priv->RL); + + /* DBTR1.CWL : WL */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(1), priv->WL); + + /* DBTR2.AL = 0 */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(2), 0x0); + + /* DBTR3.TRCD: tRCD */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(3), priv->js2[JS2_tRCD]); + + /* DBTR4.TRPA,TRP: tRPab,tRPpb */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(4), (priv->js2[JS2_tRPab] << 16) | + priv->js2[JS2_tRPpb]); + + /* DBTR5.TRC : tRCpb */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(5), priv->js2[JS2_tRCpb]); + + /* DBTR6.TRAS : tRAS */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(6), priv->js2[JS2_tRAS]); + + /* DBTR7.TRRD : tRRD */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(7), ((priv->js2[JS2_tRRD] - 1) << 16) | + (priv->js2[JS2_tRRD] - 1)); + + /* DBTR8.TFAW : tFAW */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(8), priv->js2[JS2_tFAW] - 1); + + /* DBTR9.TRDPR: nRBTP */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(9), js1[priv->js1_ind].nRBTP); + + /* DBTR10.TWR : nWR */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(10), js1[priv->js1_ind].nWR); + + /* + * DBTR11.TRDWR : RL + BL/n_max + RU(tWCK2DQO(max)/tCK) + + * RD(tRPST/tCK) - ODTLon - RD(tODTon(min)/tCK) + 1 + feature + */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(11), + priv->RL + 4 + priv->js2[JS2_tWCK2DQO_HF] - + js1[priv->js1_ind].ODTLon - priv->js2[JS2_tODTon_min]); + + /* DBTR12.TWRRD_S : WL + BL/2 + tWTR_S, TWRRD_L : WL + BL + tWTR_L */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(12), + ((priv->WL + 2 + priv->js2[JS2_tWTR_S]) << 16) | + (priv->WL + 4 + priv->js2[JS2_tWTR_L])); + + /* DBTR13.TRFCAB : tRFCab */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(13), priv->js2[JS2_tRFCab]); + + /* DBTR14.TCSCAL,TCKEHDLL,tCKEH : tCSCAL,tXP,tXP */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(14), (priv->js2[JS2_tCSCAL] << 24) | + (priv->js2[JS2_tXP] << 16) | + priv->js2[JS2_tXP]); + + /* DBTR15.TESPD,TCKESR,TCKEL : tESPD = 2,tSR,tSR */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(15), (0x02 << 24) | + (priv->js2[JS2_tSR] << 16) | + priv->js2[JS2_tSR]); + + /* DBTR16 */ + /* wdql(tphy_wrlat + tphy_wrdata) */ + tmp[0] = (priv->WL * 4) - 1 + 5; + /* dqenltcy(tphy_wrlat) */ + tmp[1] = (priv->WL * 4) - 2 - 2 + 5; + /* dql(tphy_rdlat + trddata_en) RL * 4 + phy_rptr_update + phy_rddqs_latency_adjust + 39 */ + tmp[2] = (priv->RL * 4) + + dbsc5_ddrtbl_getval(priv->DDR_PHY_SLICE_REGSET, PHY_RPTR_UPDATE, false) + + dbsc5_ddrtbl_getval(priv->DDR_PHY_SLICE_REGSET, PHY_RDDQS_LATENCY_ADJUST, false) + + 39; + /* dqienltncy(trddata_en) RL * 4 - phy_rddata_en_dly_X + 4 * phy_wck_freq_ratio_X */ + tmp[3] = (priv->RL * 4) + 4 - + dbsc5_ddrtbl_getval(priv->DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_DLY, false); + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(16), (tmp[3] << 24) | (tmp[2] << 16) | + (tmp[1] << 8) | tmp[0]); + + /* DBTR17.TMODRD,TMOD: tMRR,tMRW */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(17), (priv->js2[JS2_tMRR] << 24) | + (priv->js2[JS2_tMRW] << 16)); + + /* DBTR18. RODTL, RODTA = 0 */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(18), 0x0); + + /* DBTR19. TZQCL, TZQCS = 0 */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(19), 0x0); + + /* DBTR20.TXSDLL, TXS : tXSR,tXSR */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(20), ((priv->js2[JS2_tXSR]) << 16) | + priv->js2[JS2_tXSR]); + + /* DBTR21.TCCD */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(21), (priv->ddr_tccd << 16) | + (priv->ddr_tccd * 2)); + + /* DBTR22.TZQCAL,TZQLAT : tZQCAL,tZQLAT */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(22), (priv->js2[JS2_tZQCALns] << 16) | priv->js2[JS2_tZQLAT]); + + /* DBTR23. RRSPC = 0 */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(23), 0x0); + + /* DBTR24 */ + /* WRCSLAT(tphy_wrcslat) */ + tmp[0] = (priv->WL * 4) - 2; + /* WRCSGAP(tphy_wrcsgap) */ + tmp[1] = 0x0C; + /* RDCSLAT(tphy_rdcslat) */ + tmp[2] = priv->RL * 4; + /* RDCSGAP(tphy_rdcsgap) */ + tmp[3] = 0x0C; + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(24), (tmp[3] << 24) | (tmp[2] << 16) | + (tmp[1] << 8) | tmp[0]); + + /* DBTR25. TWDQLVLDIS = 0 */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(25), 0x0); + + /* DBTR26. TWCK2DQOOSC,TDQSOSC : WCK2DQI interval timer run time, WCK2DQO interval timer run time */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(26), 0x0); + + /* DBTR27.TPDN : tPDN */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(27), priv->js2[JS2_tPDN]); + + /* DBTR28.txsrdsm : tXSR_DSM */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(28), priv->js2[JS2_tXSR_DSM]); + + /* DBTR29.tdsmxp : tXDSM_XP */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(29), priv->js2[JS2_tXDSM_XP]); + + /* DBTR30.TCMDPD : tCMDPD = 3 */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(30), 0x3); + + /* DBTR31.TWCK2DQOMAX,TWCK2DQIMAX : tWCK2DQI/O_HF/LF */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(31), (priv->js2[JS2_tWCK2DQO_HF] << 4) | + priv->js2[JS2_tWCK2DQI_HF]); + + /* DBTR32 */ + /* twckenr */ + tmp[0] = (js1[priv->js1_ind].WCKENLR * 4) + 4 - 1; + /* twckenw */ + tmp[1] = (js1[priv->js1_ind].WCKENLW * 4) + 4 - 1; + /* twckenlf */ + tmp[2] = (js1[priv->js1_ind].WCKENLF * 4) + 4; + /* twckpresta */ + tmp[3] = js1[priv->js1_ind].WCKPRESTA * 4; + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(32), (tmp[3] << 24) | (tmp[2] << 16) | + (tmp[1] << 8) | tmp[0]); + + /* DBTR33 */ + /* TWCKTGL */ + tmp[0] = 4; + /* TWCKDIS (RL+ bl/n_max) * 4 + RU(tWCKPST/tWCK) : tWCKPST = 2.5(MR10[3:2]) */ + tmp[1] = ((priv->RL + 4) * 4) + 3; + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(33), (tmp[1] << 8) | tmp[0]); + + /* DBTR34 */ + /* TWCKSUS = 4 */ + tmp[0] = 4; + /* TWCKPST RU(tWCKPST/tCK) : tWCKPST=2.5(MR10[3:2]) */ + tmp[1] = 1; + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(34), (tmp[1] << 8) | tmp[0]); + + /* DBTR35 */ + /* TRD2WCKOFF RL + BL/n_max + RD(tWCKPST/tCK) + 1 */ + tmp[0] = priv->RL + 4 + 0 + 1; + /* TWR2WCKOFF WL + BL/n_max + RD(tWCKPST/tCK) + 1 */ + tmp[1] = priv->WL + 4 + 0 + 1; + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(35), (tmp[1] << 16) | tmp[0]); + + /* DBTR36 */ + /* TWSSUSWRX : CAS(WCKSUS)WRX */ + tmp[0] = 3; + /* TWSOFFWRX : CAS(WS_OFF)WRX */ + tmp[1] = 3; + /* TWSFSWRX : CAS(WS_FS)WRX */ + tmp[2] = 2; + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(36), (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]); + + /* DBTR37 */ + /* tOSCO */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(37), priv->js2[JS2_tOSCODQI]); + + /* DBRNK2 */ + /* RNKRR = 12 */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBRNK(2), 0xCC); + + /* DBRNK3 */ + /* RNKRW = 6 */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBRNK(3), 0x66); + + /* DBRNK4 */ + /* RNKWR = 6 */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBRNK(4), 0x66); + + /* DBRNK5 */ + /* RNKWW = 14 */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBRNK(5), 0xEE); + + /* Timing registers for Scheduler */ + /* SCFCTST0 */ + /* SCPREACT */ + tmp[0] = priv->js2[JS2_tRPpb] * priv->bus_clk * priv->ddr_mbpsdiv * 8UL / + priv->ddr_mbps / priv->bus_clkdiv; + /* SCACTRDWR */ + tmp[1] = (priv->WL + 2 + 1 + js1[priv->js1_ind].nWR + priv->js2[JS2_tRPpb]) * + priv->bus_clk * priv->ddr_mbpsdiv * 8UL / + priv->ddr_mbps / priv->bus_clkdiv; + /* SCRDACRT */ + tmp[2] = ((js1[priv->js1_ind].nRBTP + 2) + priv->js2[JS2_tRPpb]) * + priv->bus_clk * priv->ddr_mbpsdiv * 8UL / + priv->ddr_mbps / priv->bus_clkdiv; + /* SCACTACT */ + tmp[3] = priv->js2[JS2_tRCpb] * priv->bus_clk * priv->ddr_mbpsdiv * 8UL / + priv->ddr_mbps / priv->bus_clkdiv; + dbsc5_reg_write(regs_dbsc_a + DBSC_DBSCHFCTST0, (tmp[3] << 24) | (tmp[2] << 16) | + (tmp[1] << 8) | tmp[0]); + + /* SCFCTST1 */ + /* SCASYNCOFS */ + tmp[0] = 12; + /* SCACTRDWR */ + tmp[1] = priv->js2[JS2_tRCD] * priv->bus_clk * priv->ddr_mbpsdiv * 8UL / + priv->ddr_mbps / priv->bus_clkdiv; + /* SCWRRD */ + tmp[2] = (readl(regs_dbsc_d + DBSC_DBTR(12)) & 0xFF) * priv->bus_clk * priv->ddr_mbpsdiv * 8UL / + priv->ddr_mbps / priv->bus_clkdiv; + /* SCRDWR */ + tmp[3] = (readl(regs_dbsc_d + DBSC_DBTR(11)) & 0xFF) * priv->bus_clk * priv->ddr_mbpsdiv * 8UL / + priv->ddr_mbps / priv->bus_clkdiv; + dbsc5_reg_write(regs_dbsc_a + DBSC_DBSCHFCTST1, (tmp[3] << 24) | (tmp[2] << 16) | + (tmp[1] << 8) | tmp[0]); + + /* DBSCHRW1 */ + /* SCTRFCAB */ + tmp[0] = (priv->js2[JS2_tRFCab] + priv->js2[JS2_tZQLAT]) * + priv->bus_clk * priv->ddr_mbpsdiv * 8UL / + priv->ddr_mbps / priv->bus_clkdiv; + dbsc5_reg_write(regs_dbsc_a + DBSC_DBSCHRW1, tmp[0]); + + /* DBSCHTR0 */ + /* SCDT0 */ + tmp[0] = (4 * priv->bus_clk * priv->ddr_mbpsdiv * 8UL / + priv->ddr_mbps / priv->bus_clkdiv) - 1; + /* SCDT1 */ + tmp[1] = (8 * priv->bus_clk * priv->ddr_mbpsdiv * 8UL / + priv->ddr_mbps / priv->bus_clkdiv) - 1; + /* SCDT2 */ + tmp[2] = (12 * priv->bus_clk * priv->ddr_mbpsdiv * 8UL / + priv->ddr_mbps / priv->bus_clkdiv) - 1; + /* SCDT3 */ + tmp[3] = (16 * priv->bus_clk * priv->ddr_mbpsdiv * 8UL / + priv->ddr_mbps / priv->bus_clkdiv) - 1; + dbsc5_reg_write(regs_dbsc_a + DBSC_DBSCHTR0, (tmp[3] << 24) | (tmp[2] << 16) | + (tmp[1] << 8) | tmp[0]); + + /* QOS and CAM */ + dbsc5_reg_write(regs_dbsc_a + DBSC_DBBCAMDIS, 0x1); +} + +/** + * dbsc5_dbsc_regset_post() - Set DBSC registers + * @dev: DBSC5 device + * + * If memory rank is 2, CS_TRAINING_EN is set to the other side. + * Configure DBI read/write settings. Execute DRAM refresh settings. + * Set WTmode of DFI PHY to OFF. Set up PHY Periodic Write DQ training. + * Set WTmode of DFI PHY to ON. Calibration settings for PHY PAD. + * Set SDRAM calibration. Make DFI Control Update Setting settings. + * In the case of WARM_BOOT, cancel the self-refresh setting. + * Enable SDRAM auto refresh. Set up PHY Periodic Write DQ training. + * Enable access to SDRAM. + */ +static void dbsc5_dbsc_regset_post(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + void __iomem *regs_dbsc_a = priv->regs + DBSC5_DBSC_A_OFFSET; + void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET; + /* Average periodic refresh interval/Average Refresh Interval [ns] */ + const u32 dbsc_refint = 1920; + /* 0: Average interval is REFINT, 1: Average interval is 1/2 REFINT */ + const u32 dbsc_refints = 0; + /* Periodic-WriteDQ/ReadDQ Training Interval [us] */ + const u32 periodic_training_interval = 20000; + u32 phymster_req_interval; + u32 ch, slice; + u32 clk_count; + u32 refcycle; + u32 ctrl_clk; + u32 reg; + + if ((renesas_get_cpu_rev_integer() < 3) && priv->ch_have_this_cs[1]) { + r_foreach_vch(dev, ch) { + for (slice = 0; slice < SLICE_CNT; slice++) { + dbsc5_ddr_setval_slice(dev, ch, slice, + PHY_PER_CS_TRAINING_EN, + 0x0); + } + } + } + + dbsc5_reg_write(regs_dbsc_d + DBSC_DBDBICNT, 0x3); + + /* set REFCYCLE */ + refcycle = dbsc_refint * priv->ddr_mbps / 8000 / priv->ddr_mbpsdiv; + /* refpmax=8 */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBRFCNF1, (refcycle & 0xFFFF) | BIT(19)); + /* refpmin=1 */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBRFCNF2, dbsc_refints | BIT(16)); + + dbsc5_reg_write(regs_dbsc_d + DBSC_DBDFIPMSTRCNF, 0x0); + + /* Periodic-WriteDQ Training setting */ + dbsc5_ddr_setval_all_ch(dev, PI_WDQLVL_EN_F2, 0x3); + dbsc5_ddr_setval_all_ch(dev, PI_WDQLVL_VREF_EN, 0x0); + dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_DATA_DC_WDQLVL_ENABLE, 0x0); + dbsc5_ddr_setval_all_ch(dev, PI_WDQLVL_PERIODIC, 0x1); + + /* Periodic-ReadDQ Training setting */ + dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_EN_F2, 0x3); + dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_VREF_EN_F2, 0x0); + dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_RDLVL_DLY_STEP, 0x4); + dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_PERIODIC, 0x1); + + /* DFI_PHYMSTR_ACK , WTmode = b'01 */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBDFIPMSTRCNF, 0x11); + + /* periodic SoC zqcal enable */ + reg = dbsc5_ddrtbl_getval(priv->DDR_PHY_ADR_G_REGSET, PHY_CAL_MODE_0, false); + dbsc5_ddr_setval_all_ch(dev, PHY_CAL_MODE_0, reg | BIT(1)); + + /* Periodic dram zqcal enable */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBCALCNF, 0x1000010); + + /* Periodic phy ctrl update enable */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBDFICUPDCNF, 0x504C0001); + + /* Set Auto Refresh */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBRFEN, 0x1); + + /* Periodic-WriteDQ/ReadDQ Training Interval setting */ + phymster_req_interval = periodic_training_interval - 3000; + clk_count = 1024 - (dbsc5_ddrtbl_getval(priv->DDR_PI_REGSET, PI_LONG_COUNT_MASK, true) * 32); + ctrl_clk = priv->ddr_mbps / priv->ddr_mbpsdiv / 8; + reg = phymster_req_interval * ctrl_clk / clk_count; + + dbsc5_ddr_setval_all_ch(dev, PI_WDQLVL_INTERVAL, reg); + + /* DRAM access enable */ + dbsc5_reg_write(regs_dbsc_a + DBSC_DBACEN, 0x1); +} + +/** + * dbsc5_pi_training() - Training by PI + * @dev: DBSC5 device + * + * Enable WCK signal training and read gate training. Start PI training. + * After DFI initialization for all channels is once turned off, turned + * on all chennels of it. Power down the DRAM device once and then release + * the power down mode. Perform training in low frequency mode and training + * in high frequency mode. Wait for the DFI training completion status + * bit to stand until the time limit. Turn off DFI initialization for all + * channels. Turn off WTMODE of DFI PHY. Check if CA/CS Training has failed. + * Check if Wrlvl training is in error. If an error can be confirmed from + * the check result, the result is returned as a return value. Clear the + * status register for PI training. + */ +static u32 dbsc5_pi_training(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET; + const int retry_max = 0x10000; + u32 ca_training_ng = 0; + u32 wr_training_ng = 0; + u32 phytrainingok = 0; + u32 complete_ng = 0; + bool frqchg_req; + u32 ch, reg; + int retry; + int ret; + + /* Init start */ + dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_GATE_EN_F2, 0x0); + dbsc5_ddr_setval_all_ch(dev, PI_WRDCM_LVL_EN_F2, 0x0); + dbsc5_ddr_setval_all_ch(dev, PI_DRAMDCA_LVL_EN_F2, 0x0); + dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_EN_F2, 0x0); + dbsc5_ddr_setval_all_ch(dev, PI_WDQLVL_EN_F2, 0x0); + dbsc5_ddr_setval_all_ch(dev, PI_DFS_INITIALIZATION_SEQ_9, 0x0); + dbsc5_ddr_setval_all_ch(dev, PI_DFS_INITIALIZATION_SEQ_10, 0x0); + + /* PI_START */ + dbsc5_ddr_setval_all_ch(dev, PI_START, 0x1); + + r_foreach_vch(dev, ch) + writel(0x20, regs_dbsc_d + DBSC_DBDFICNT(ch)); + + r_foreach_vch(dev, ch) + writel(0x21, regs_dbsc_d + DBSC_DBDFICNT(ch)); + + /* Dummy PDE */ + dbsc5_send_dbcmd2(dev, 0x8840000); + + /* PDX */ + dbsc5_send_dbcmd2(dev, 0x8840001); + + /* Wait init_complete */ + for (retry = 0; retry < retry_max; retry++) { + frqchg_req = false; + for (ch = 0; ch < DRAM_CH_CNT; ch++) { + if (!((~phytrainingok & priv->ddr_phyvalid) & BIT(ch))) + continue; + + if (!(readl(regs_dbsc_d + DBSC_DBPDSTAT0(ch)) & BIT(0))) + continue; + + frqchg_req = true; + break; + } + + if (frqchg_req) { + ret = dbsc5_clk_pll3_freq(dev); + if (ret) + break; + } else { + r_foreach_vch(dev, ch) { + if (readl(regs_dbsc_d + DBSC_DBDFISTAT(ch)) & BIT(0)) + phytrainingok |= BIT(ch); + } + + if (phytrainingok == priv->ddr_phyvalid) + break; + } + } + + /* + * dbdficnt0: + * dfi_dram_clk_disable=0 + * dfi_frequency = 0 + * freq_ratio = 10 (4:1) + * init_start =0 + */ + r_foreach_vch(dev, ch) + writel(0x20, regs_dbsc_d + DBSC_DBDFICNT(ch)); + + /* DFI_PHYMSTR_ACK */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBDFIPMSTRCNF, 0x1); + + /* Error check */ + r_foreach_vch(dev, ch) { + /* CA/CS Training Error Check */ + /* PI_CALVL_ERROR_BIT */ + reg = dbsc5_ddr_getval(dev, ch, PI_INT_STATUS) & BIT(4); + /* Error on decrement/increment pass */ + reg |= dbsc5_ddr_getval(dev, ch, PHY_ADR_CALVL_OBS1) & (0x3 << 30); + /* Start outside of initial search range */ + reg |= dbsc5_ddr_getval(dev, ch, PHY_ADR_CALVL_OBS2) & (0x3 << 24); + /* CSlvl error */ + reg |= dbsc5_ddr_getval(dev, ch, PHY_CSLVL_OBS1) & (0xF << 28); + if (reg) { + ca_training_ng |= BIT(ch); + printf("%s pi_training_error:1\n", __func__); + } + + /* Wrlvl Error Check */ + /* PI_WRLVL_ERROR_BIT */ + reg = dbsc5_ddr_getval(dev, ch, PI_INT_STATUS) & BIT(3); + /* SLICE0 wrlvl error */ + reg |= dbsc5_ddr_getval_slice(dev, ch, 0, PHY_WRLVL_STATUS_OBS) & BIT(12); + /* SLICE1 wrlvl error */ + reg |= dbsc5_ddr_getval_slice(dev, ch, 1, PHY_WRLVL_STATUS_OBS) & BIT(12); + /* SLICE0 wrlvl error */ + reg |= dbsc5_ddr_getval_slice(dev, ch, 0, PHY_WRLVL_ERROR_OBS); + /* SLICE1 wrlvl error */ + reg |= dbsc5_ddr_getval_slice(dev, ch, 1, PHY_WRLVL_ERROR_OBS); + if (reg) { + wr_training_ng |= BIT(ch); + printf("%s pi_training_error:2\n", __func__); + } + } + + complete_ng = (wr_training_ng | ca_training_ng); + if (complete_ng) + return ~complete_ng; + + /* PI_INT_ACK assert */ + r_foreach_vch(dev, ch) { + dbsc5_ddr_setval(dev, ch, PI_INT_ACK_0, 0xFFFFFFFF); + dbsc5_ddr_setval(dev, ch, PI_INT_ACK_1, 0x7); + } + + return phytrainingok; +} + +/** + * dbsc5_write_leveling_adjust() - Write Leveling Cycle Adjust + * @dev: DBSC5 device + * + * Get delay value from the result write leveling of slice 0 and 1. + * Calculate latency of dfi_wrdata_en / dfi_wrdata / dfi_wrdata_mask + * signals based on delay values. + */ +static void dbsc5_write_leveling_adjust(struct udevice *dev) +{ + u32 result_hard0, result_hard1; + u32 avg, avg_frac, avg_cycle; + u32 ch; + + r_foreach_vch(dev, ch) { + /* SLICE0 */ + result_hard0 = dbsc5_ddr_getval_slice(dev, ch, 0, PHY_WRLVL_HARD0_DELAY_OBS); + result_hard1 = dbsc5_ddr_getval_slice(dev, ch, 0, PHY_WRLVL_HARD1_DELAY_OBS); + + avg = result_hard0 + result_hard1; + if (result_hard0 > result_hard1) + avg += 0x400; + avg /= 2; + + avg_frac = avg & 0xFF; + avg_cycle = (avg >> 8) & 0x3; + + if (avg_cycle == 0x3) { + dbsc5_ddr_setval_slice(dev, ch, 0, PHY_WRITE_PATH_LAT_DEC, 0x1); + dbsc5_ddr_setval_slice(dev, ch, 0, PHY_WRITE_PATH_LAT_ADD, 0x0); + } else { + dbsc5_ddr_setval_slice(dev, ch, 0, PHY_WRITE_PATH_LAT_DEC, 0x0); + dbsc5_ddr_setval_slice(dev, ch, 0, PHY_WRITE_PATH_LAT_ADD, avg_cycle); + } + dbsc5_ddr_setval_slice(dev, ch, 0, PHY_WRITE_PATH_LAT_FRAC, avg_frac); + + /* SLICE1 */ + result_hard0 = dbsc5_ddr_getval_slice(dev, ch, 1, PHY_WRLVL_HARD0_DELAY_OBS); + result_hard1 = dbsc5_ddr_getval_slice(dev, ch, 1, PHY_WRLVL_HARD1_DELAY_OBS); + + avg = result_hard0 + result_hard1; + if (result_hard0 >= result_hard1) + avg += 0x400; + avg /= 2; + avg_frac = avg & 0xFF; + avg_cycle = (avg >> 8) & 0x3; + + if (avg_cycle == 0x3) { + dbsc5_ddr_setval_slice(dev, ch, 1, PHY_WRITE_PATH_LAT_DEC, 0x1); + dbsc5_ddr_setval_slice(dev, ch, 1, PHY_WRITE_PATH_LAT_ADD, 0x0); + } else { + dbsc5_ddr_setval_slice(dev, ch, 1, PHY_WRITE_PATH_LAT_DEC, 0x0); + dbsc5_ddr_setval_slice(dev, ch, 1, PHY_WRITE_PATH_LAT_ADD, avg_cycle); + } + dbsc5_ddr_setval_slice(dev, ch, 1, PHY_WRITE_PATH_LAT_FRAC, avg_frac); + } + + dbsc5_ddr_setval_all_ch_all_slice(dev, SC_PHY_WCK_CALC, 0x1); +} + +/** + * dbsc5_wl_gt_training() - Re-run Write Leveling & Read Gate Training + * @dev: DBSC5 device + * + * Set CA leveling OFF, read gate leveling ON, write gate leveling ON, + * PI dram wck training ON. Perform PI_DFS configuration. Start PI + * frequency training in manual mode. Perform training in high-frequency + * mode. Check for Write leveling Error and Gate leveling Error. If an + * error is identified, the resulting value is inverted and returned. + * Clear the PI status register. + */ +static u32 dbsc5_wl_gt_training(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + const int retry_max = 0x10000; + u32 gt_training_ng = 0; + u32 wr_training_ng = 0; + u32 phytrainingok = 0; + u32 complete_ng = 0; + int retry, ret; + u32 ch, reg; + + dbsc5_ddr_setval_all_ch(dev, PI_CALVL_EN_F2, 0x0); + dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_GATE_EN_F2, 0x1); + + dbsc5_ddr_setval_all_ch(dev, PI_DFS_ENTRY_SEQ_0, 0x181F0000); + dbsc5_ddr_setval_all_ch(dev, PI_DFS_INITIALIZATION_SEQ_1, 0x0); + dbsc5_ddr_setval_all_ch(dev, PI_TRAIN_ALL_FREQ_REQ, 0x1); + + /* Freq Change High to High*/ + ret = dbsc5_clk_pll3_freq(dev); + if (ret) + return ret; + + for (retry = 0; retry < retry_max; retry++) { + r_foreach_vch(dev, ch) + if (dbsc5_ddr_getval(dev, ch, PI_INT_STATUS) & BIT(0)) + phytrainingok |= BIT(ch); + + if (phytrainingok == priv->ddr_phyvalid) + break; + } + + /* Error Check */ + r_foreach_vch(dev, ch) { + /* Wrlvl Error Check */ + /* PI_WRLVL_ERROR_BIT */ + reg = dbsc5_ddr_getval(dev, ch, PI_INT_STATUS) & BIT(3); + /* SLICE0 wrlvl error */ + reg |= dbsc5_ddr_getval_slice(dev, ch, 0, PHY_WRLVL_STATUS_OBS) & BIT(12); + /* SLICE1 wrlvl error */ + reg |= dbsc5_ddr_getval_slice(dev, ch, 1, PHY_WRLVL_STATUS_OBS) & BIT(12); + /* SLICE0 wrlvl error */ + reg |= dbsc5_ddr_getval_slice(dev, ch, 0, PHY_WRLVL_ERROR_OBS); + /* SLICE1 wrlvl error */ + reg |= dbsc5_ddr_getval_slice(dev, ch, 1, PHY_WRLVL_ERROR_OBS); + if (reg) { + wr_training_ng |= BIT(ch); + printf("%s wl_gt_training_error:1\n", __func__); + } + + /* Gtlvl Error Check */ + /* PI_RDLVL_GATE_ERROR_BIT */ + reg = dbsc5_ddr_getval(dev, ch, PI_INT_STATUS) & BIT(2); + /* SLICE0 delay setup error */ + reg |= dbsc5_ddr_getval_slice(dev, ch, 0, PHY_GTLVL_STATUS_OBS) & (0x3 << 7); + /* SLICE1 delay setup error */ + reg |= dbsc5_ddr_getval_slice(dev, ch, 1, PHY_GTLVL_STATUS_OBS) & (0x3 << 7); + if (reg) { + gt_training_ng |= BIT(ch); + printf("%s wl_gt_training_error:2\n", __func__); + } + } + + complete_ng = (wr_training_ng | gt_training_ng); + if (complete_ng) + return ~complete_ng; + + /* PI_INT_ACK assert */ + r_foreach_vch(dev, ch) { + dbsc5_ddr_setval(dev, ch, PI_INT_ACK_0, 0xFFFFFFFF); + dbsc5_ddr_setval(dev, ch, PI_INT_ACK_1, 0x7); + } + + return phytrainingok; +} + +/** + * dbsc5_pi_int_ack_0_assert() - Training handshake functions + * @dev: DBSC5 device + * @bit: Status bit to poll + * + * Wait for the status bit specified in the argument to become 1 until the + * time limit. After checking status bits on all channels, clear the target + * status bits and returns the result of the check as the return value. + */ +static u32 dbsc5_pi_int_ack_0_assert(struct udevice *dev, u32 bit) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + const int retry_max = 0x10000; + u32 ch, phytrainingok = 0; + int retry; + + for (retry = 0; retry < retry_max; retry++) { + r_foreach_vch(dev, ch) + if (dbsc5_ddr_getval(dev, ch, PI_INT_STATUS) & BIT(bit)) + phytrainingok |= BIT(ch); + + if (phytrainingok == priv->ddr_phyvalid) + break; + } + + if (phytrainingok != priv->ddr_phyvalid) + return phytrainingok; + + r_foreach_vch(dev, ch) + dbsc5_ddr_setval(dev, ch, PI_INT_ACK_0, BIT(bit)); + + return phytrainingok; +} + +/** + * dbsc5_write_dca() - Write DCA Training + * @dev: DBSC5 device + * + * Get DCA Training CS0 Flip-0 training results for RANK0. + * Get DCA Training CS1 Flip-0 training results for RANK0. + * Calculate DRAMDCA settings from training results and write + * them to registers. Set DRAM DCA in MR30. Ensure that the + * training has been successfully completed. Clear CA status + * to 0. + */ +static void dbsc5_write_dca(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + const int retry_max = 0x10000; + u32 phytrainingok = 0; + u32 ch, reg; + int retry; + + dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_DATA_DC_CAL_START, 0x1); + + for (retry = 0; retry < retry_max; retry++) { + r_foreach_vch(dev, ch) { + reg = dbsc5_ddr_getval_slice(dev, ch, 0, PHY_DATA_DC_CAL_START) | + dbsc5_ddr_getval_slice(dev, ch, 1, PHY_DATA_DC_CAL_START); + if (!reg) + phytrainingok |= BIT(ch); + } + + if (phytrainingok == priv->ddr_phyvalid) + break; + } +} + +/** + * dbsc5_dramdca_training() - DRAM DCA Training and Calculations + * @dev: DBSC5 device + * + * Get DCA Training CS0 Flip-0 training results for RANK0. + * Get DCA Training CS1 Flip-0 training results for RANK0. + * Calculate DRAMDCA settings from training results and write + * them to registers. Set DRAM DCA in MR30. Ensure that the + * training has been successfully completed. Clear CA status + * to 0. + */ +static u32 dbsc5_dramdca_training(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + const u32 rank = priv->ch_have_this_cs[1] ? 0x3 : 0x1; + const u32 mr30_conv[16] = { + 0x8, 0x7, 0x6, 0x5, 0x4, 0x3, 0x2, 0x1, + 0x0, 0x9, 0xA, 0xB, 0xC, 0xD, 0xE, 0xF + }; + u32 dca_result_l_0[DRAM_CH_CNT][CS_CNT]; + u32 dca_result_u_0[DRAM_CH_CNT][CS_CNT]; + u32 dca_result_l_1[DRAM_CH_CNT][CS_CNT]; + u32 dca_result_u_1[DRAM_CH_CNT][CS_CNT]; + u32 ch, phytrainingok, reg; + u32 tempu, templ; + + /* Run DRAM DCA Training for Flip-0 */ + dbsc5_ddr_setval_all_ch(dev, PI_DCMLVL_CS_SW, rank); + + /* DRAMDCA go */ + dbsc5_ddr_setval_all_ch(dev, PI_DRAMDCA_LVL_REQ, 0x1); + + /* PI_INT_ACK assert */ + phytrainingok = dbsc5_pi_int_ack_0_assert(dev, 28); + if (phytrainingok != priv->ddr_phyvalid) + return phytrainingok; + + /* Result for DRAMDCA flip-0 */ + r_foreach_vch(dev, ch) { + reg = dbsc5_ddr_getval(dev, ch, PI_DARRAY3_20_CS0_F2); + dca_result_u_0[ch][0] = mr30_conv[reg >> 4]; + dca_result_l_0[ch][0] = mr30_conv[reg & 0xF]; + if (!(rank & 0x2)) + continue; + + reg = dbsc5_ddr_getval(dev, ch, PI_DARRAY3_20_CS1_F2); + dca_result_u_0[ch][1] = mr30_conv[reg >> 4]; + dca_result_l_0[ch][1] = mr30_conv[reg & 0xF]; + } + + /* Run DRAM DCA Training for Flip-1 */ + dbsc5_ddr_setval_all_ch(dev, PI_DRAMDCA_FLIP_MASK, 0x1); + dbsc5_ddr_setval_all_ch(dev, PI_DRAMDCA_LVL_ACTIVE_SEQ_2, 0x0); + dbsc5_ddr_setval_all_ch(dev, PI_DRAMDCA_LVL_ACTIVE_SEQ_3, 0x0); + dbsc5_ddr_setval_all_ch(dev, PI_DRAMDCA_LVL_ACTIVE_SEQ_4, 0x0); + + /* DRAMDCA go */ + dbsc5_ddr_setval_all_ch(dev, PI_DRAMDCA_LVL_REQ, 0x1); + + /* PI_INT_ACK assert */ + phytrainingok = dbsc5_pi_int_ack_0_assert(dev, 28); + if (phytrainingok != priv->ddr_phyvalid) + return phytrainingok; + + /* Result for DRAMDCA flip-1 */ + r_foreach_vch(dev, ch) { + reg = dbsc5_ddr_getval(dev, ch, PI_DARRAY3_20_CS0_F2); + dca_result_u_1[ch][0] = mr30_conv[reg >> 4]; + dca_result_l_1[ch][0] = mr30_conv[reg & 0xF]; + if (!(rank & 0x2)) + continue; + + reg = dbsc5_ddr_getval(dev, ch, PI_DARRAY3_20_CS1_F2); + dca_result_u_1[ch][1] = mr30_conv[reg >> 4]; + dca_result_l_1[ch][1] = mr30_conv[reg & 0xF]; + } + + /* Calculate and set DRAMDCA value */ + r_foreach_vch(dev, ch) { + /* CS0 */ + tempu = (dca_result_u_0[ch][0] + dca_result_u_1[ch][0]) / 2; + templ = (dca_result_l_0[ch][0] + dca_result_l_1[ch][0]) / 2; + reg = (mr30_conv[tempu] << 4) | mr30_conv[templ]; + dbsc5_ddr_setval(dev, ch, PI_DARRAY3_20_CS0_F2, reg); + if (!(rank & 0x2)) + continue; + + /* CS1 */ + tempu = (dca_result_u_0[ch][1] + dca_result_u_1[ch][1]) / 2; + templ = (dca_result_l_0[ch][1] + dca_result_l_1[ch][1]) / 2; + reg = (mr30_conv[tempu] << 4) | mr30_conv[templ]; + dbsc5_ddr_setval(dev, ch, PI_DARRAY3_20_CS1_F2, reg); + } + + /* Set DRAMDCA value in MR30 */ + dbsc5_ddr_setval_all_ch(dev, PI_SW_SEQ_0, 0x1A11E14); + dbsc5_ddr_setval_all_ch(dev, PI_SW_SEQ_1, 0x1F0000); + dbsc5_ddr_setval_all_ch(dev, PI_SEQ_DEC_SW_CS, rank); + dbsc5_ddr_setval_all_ch(dev, PI_SW_SEQ_START, 0x1); + + /* PI_INT_ACK assert */ + phytrainingok = dbsc5_pi_int_ack_0_assert(dev, 19); + if (phytrainingok != priv->ddr_phyvalid) + return phytrainingok; + + dbsc5_ddr_setval_all_ch(dev, PI_SEQ_DEC_SW_CS, 0x0); + dbsc5_ddr_setval_all_ch(dev, PI_DRAMDCA_FLIP_MASK, 0x2); + dbsc5_ddr_setval_all_ch(dev, PI_DRAMDCA_LVL_ACTIVE_SEQ_2, 0x1101FC); + dbsc5_ddr_setval_all_ch(dev, PI_DRAMDCA_LVL_ACTIVE_SEQ_3, 0x211A00); + dbsc5_ddr_setval_all_ch(dev, PI_DRAMDCA_LVL_ACTIVE_SEQ_4, 0x51500); + + return phytrainingok; +} + +/** + * dbsc5_write_leveling() - Re-run Write Leveling + * @dev: DBSC5 device + * + * CALVL training is set to OFF, WRDCM training is set to OFF, and DRAMDCA + * training is set to OFF. Set the memory rank for the Write leveling target + * and start leveling. Wait until leveling is complete. + * + * Check for Write leveling errors. If an error is confirmed to have occurred, + * the result is returned as a return value. Clear the PI status bit. + */ +static u32 dbsc5_write_leveling(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + const u32 rank = priv->ch_have_this_cs[1] ? 0x3 : 0x1; + const int retry_max = 0x10000; + u32 wr_training_ng = 0; + u32 phytrainingok = 0; + u32 ch, reg; + int retry; + + dbsc5_ddr_setval_all_ch(dev, PI_CALVL_EN_F2, 0x0); + dbsc5_ddr_setval_all_ch(dev, PI_WRDCM_LVL_EN_F2, 0x0); + dbsc5_ddr_setval_all_ch(dev, PI_DRAMDCA_LVL_EN_F2, 0x0); + dbsc5_ddr_setval_all_ch(dev, PI_WRLVL_CS_SW, rank); + dbsc5_ddr_setval_all_ch(dev, PI_WRLVL_REQ, 0x1); + + for (retry = 0; retry < retry_max; retry++) { + r_foreach_vch(dev, ch) + if (dbsc5_ddr_getval(dev, ch, PI_INT_STATUS) & BIT(29)) + phytrainingok |= BIT(ch); + + if (phytrainingok == priv->ddr_phyvalid) + break; + } + + /* Error check */ + r_foreach_vch(dev, ch) { + /* Wrlvl Error Check */ + /* PI_WRLVL_ERROR_BIT */ + reg = dbsc5_ddr_getval(dev, ch, PI_INT_STATUS) & BIT(3); + /* SLICE0 wrlvl error */ + reg |= dbsc5_ddr_getval_slice(dev, ch, 0, PHY_WRLVL_STATUS_OBS) & BIT(12); + /* SLICE1 wrlvl error */ + reg |= dbsc5_ddr_getval_slice(dev, ch, 1, PHY_WRLVL_STATUS_OBS) & BIT(12); + /* SLICE0 wrlvl error */ + reg |= dbsc5_ddr_getval_slice(dev, ch, 0, PHY_WRLVL_ERROR_OBS); + /* SLICE1 wrlvl error */ + reg |= dbsc5_ddr_getval_slice(dev, ch, 1, PHY_WRLVL_ERROR_OBS); + if (reg) { + wr_training_ng |= BIT(ch); + printf("%s write_leveling_error:1\n", __func__); + } + } + + if (wr_training_ng) + return ~wr_training_ng; + + /* PI_INT_ACK assert */ + r_foreach_vch(dev, ch) { + dbsc5_ddr_setval(dev, ch, PI_INT_ACK_0, 0xFFFFFFFF); + dbsc5_ddr_setval(dev, ch, PI_INT_ACK_1, 0x7); + } + + return phytrainingok; +} + +/** + * dbsc5_manual_write_dca() - Manual Write DCA Training + * @dev: DBSC5 device + * + * Write DCA training according to memory rank. + */ +static void dbsc5_manual_write_dca(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + const u32 rank = priv->ch_have_this_cs[1] ? 0x2 : 0x1; + u32 slv_dly_center[DRAM_CH_CNT][CS_CNT][SLICE_CNT]; + u32 slv_dly_center_cyc; + u32 slv_dly_center_dly; + u32 slv_dly_min[DRAM_CH_CNT][SLICE_CNT]; + u32 slv_dly_max[DRAM_CH_CNT][SLICE_CNT]; + u32 slv_dly_min_tmp[DRAM_CH_CNT][CS_CNT][SLICE_CNT]; + u32 slv_dly_max_tmp[DRAM_CH_CNT][CS_CNT][SLICE_CNT]; + u32 phy_dcc_code_min[DRAM_CH_CNT][SLICE_CNT]; + u32 phy_dcc_code_max[DRAM_CH_CNT][SLICE_CNT]; + u32 phy_dcc_code_mid; + const int retry_max = 0x10000; + const u8 ratio_min_div = 0xA; + const u8 ratio_max_div = 0x2; + const u8 ratio_min = 0x6; + const u8 ratio_max = 0x3; + u32 ch, cs, slice, tmp; + u32 complete = 0; + int i, retry; + + r_foreach_vch(dev, ch) { + for (slice = 0; slice < SLICE_CNT; slice++) { + phy_dcc_code_min[ch][slice] = 0x7F; + phy_dcc_code_max[ch][slice] = 0x0; + } + } + + for (cs = 0; cs < rank; cs++) { + dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_PER_CS_TRAINING_INDEX, cs); + r_foreach_vch(dev, ch) { + for (slice = 0; slice < SLICE_CNT; slice++) { + slv_dly_center[ch][cs][slice] = + dbsc5_ddr_getval_slice(dev, ch, slice, PHY_CLK_WRDQS_SLAVE_DELAY); + slv_dly_center_cyc = slv_dly_center[ch][cs][slice] & 0x180; + slv_dly_center_dly = slv_dly_center[ch][cs][slice] & 0x7F; + slv_dly_min_tmp[ch][cs][slice] = + slv_dly_center_cyc | + (slv_dly_center_dly * ratio_min / ratio_min_div); + slv_dly_max_tmp[ch][cs][slice] = slv_dly_center_cyc; + if ((slv_dly_center_dly * ratio_max) > (0x7F * ratio_max_div)) + slv_dly_max_tmp[ch][cs][slice] |= 0x7F; + else + slv_dly_max_tmp[ch][cs][slice] |= slv_dly_center_dly * ratio_max / ratio_max_div; + } + } + } + + r_foreach_vch(dev, ch) { + for (slice = 0; slice < SLICE_CNT; slice++) { + if (rank == 0x2) { + if (slv_dly_max_tmp[ch][0][slice] < slv_dly_max_tmp[ch][1][slice]) + slv_dly_max[ch][slice] = slv_dly_max_tmp[ch][1][slice]; + else + slv_dly_max[ch][slice] = slv_dly_max_tmp[ch][0][slice]; + + if (slv_dly_min_tmp[ch][0][slice] < slv_dly_min_tmp[ch][1][slice]) + slv_dly_min[ch][slice] = slv_dly_min_tmp[ch][0][slice]; + else + slv_dly_min[ch][slice] = slv_dly_min_tmp[ch][1][slice]; + } else { + slv_dly_max[ch][slice] = slv_dly_max_tmp[ch][0][slice]; + slv_dly_min[ch][slice] = slv_dly_min_tmp[ch][0][slice]; + } + } + } + + for (i = 0; i <= 0x7F; i++) { + r_foreach_vch(dev, ch) { + for (slice = 0; slice < SLICE_CNT; slice++) { + if (slv_dly_max[ch][slice] < (slv_dly_min[ch][slice] + i)) { + complete |= BIT(ch) << (8 * slice); + } else { + /* CS0/1 same setting, Need masked write */ + dbsc5_ddr_setval_slice(dev, ch, slice, + PHY_CLK_WRDQS_SLAVE_DELAY, + slv_dly_min[ch][slice] + i); + dbsc5_ddr_setval_slice(dev, ch, slice, SC_PHY_WCK_CALC, 0x1); + dbsc5_ddr_setval(dev, ch, SC_PHY_MANUAL_UPDATE, 0x1); + } + } + } + + if (complete == (priv->ddr_phyvalid | (priv->ddr_phyvalid << 8))) + break; + + /* Execute write dca */ + r_foreach_vch(dev, ch) + for (slice = 0; slice < SLICE_CNT; slice++) + if (!(((complete >> (8 * slice)) >> ch) & 0x1)) + dbsc5_ddr_setval_slice(dev, ch, slice, PHY_DATA_DC_CAL_START, 0x1); + + r_foreach_vch(dev, ch) { + for (slice = 0; slice < SLICE_CNT; slice++) { + if (!(((complete >> (8 * slice)) >> ch) & 0x1)) { + for (retry = 0; retry < retry_max; retry++) { + tmp = dbsc5_ddr_getval_slice(dev, ch, slice, + PHY_DATA_DC_CAL_START); + if (!tmp) + break; + } + } + } + } + + r_foreach_vch(dev, ch) { + for (slice = 0; slice < SLICE_CNT; slice++) { + if ((slv_dly_min[ch][slice] + i) > slv_dly_max[ch][slice]) + continue; + + tmp = (dbsc5_ddr_getval_slice(dev, ch, slice, PHY_DATA_DC_DQS_CLK_ADJUST)); + if ((tmp >> 6) == 0x1) + tmp = 0x0; + else if ((tmp >> 6) == 0x2) + tmp = 0x3F; + + if (tmp < phy_dcc_code_min[ch][slice]) + phy_dcc_code_min[ch][slice] = tmp; + + if (phy_dcc_code_max[ch][slice] < tmp) + phy_dcc_code_max[ch][slice] = tmp; + } + } + } + + dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_PER_CS_TRAINING_MULTICAST_EN, 0x0); + for (cs = 0; cs < rank; cs++) { + dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_PER_CS_TRAINING_INDEX, cs); + r_foreach_vch(dev, ch) { + for (slice = 0; slice < SLICE_CNT; slice++) { + dbsc5_ddr_setval_slice(dev, ch, slice, + PHY_CLK_WRDQS_SLAVE_DELAY, + slv_dly_center[ch][cs][slice]); + dbsc5_ddr_setval_slice(dev, ch, slice, + SC_PHY_WCK_CALC, 0x1); + dbsc5_ddr_setval(dev, ch, SC_PHY_MANUAL_UPDATE, 0x1); + } + } + } + dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_PER_CS_TRAINING_MULTICAST_EN, 0x1); + + r_foreach_vch(dev, ch) { + for (slice = 0; slice < SLICE_CNT; slice++) { + phy_dcc_code_mid = (phy_dcc_code_min[ch][slice] + + phy_dcc_code_max[ch][slice]) / 2; + dbsc5_ddr_setval_slice(dev, ch, slice, + PHY_DATA_DC_DQS_CLK_ADJUST, + phy_dcc_code_mid); + } + } +} + +/** + * dbsc5_read_gate_training() - Re-run read gate training by PI + * @dev: DBSC5 device + * + * Write leveling set to OFF, read gate leveling set to ON. Set memory rank + * for leveling target, turn on read gate leveling. Wait for leveling to be + * completed until the time limit. Check for errors during gate leveling. + * + * If an error is confirmed to have occurred, the result is returned as a + * return value. Clear the PI status register. + */ +static u32 dbsc5_read_gate_training(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + const u32 rank = priv->ch_have_this_cs[1] ? 0x3 : 0x1; + const int retry_max = 0x10000; + u32 gt_training_ng = 0; + u32 phytrainingok = 0; + u32 ch, reg; + int retry; + + dbsc5_ddr_setval_all_ch(dev, PI_WRLVL_EN_F2, 0x0); + dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_GATE_EN_F2, 0x1); + dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_CS_SW, rank); + dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_GATE_REQ, 0x1); + + for (retry = 0; retry < retry_max; retry++) { + r_foreach_vch(dev, ch) + if (dbsc5_ddr_getval(dev, ch, PI_INT_STATUS) & BIT(24)) + phytrainingok |= BIT(ch); + + if (phytrainingok == priv->ddr_phyvalid) + break; + } + + /* Error Check */ + r_foreach_vch(dev, ch) { + /* Gtlvl Error Check */ + /* PI_RDLVL_GATE_ERROR_BIT */ + reg = (dbsc5_ddr_getval(dev, ch, PI_INT_STATUS) & BIT(2)); + /* SLICE0 delay setup error */ + reg |= dbsc5_ddr_getval_slice(dev, ch, 0, PHY_GTLVL_STATUS_OBS) & (0x3 << 7); + /* SLICE1 delay setup error */ + reg |= dbsc5_ddr_getval_slice(dev, ch, 1, PHY_GTLVL_STATUS_OBS) & (0x3 << 7); + if (reg) { + gt_training_ng |= BIT(ch); + printf("%s read_gate_training_error\n", __func__); + } + } + + if (gt_training_ng) + return ~gt_training_ng; + + /* PI_INT_ACK assert */ + r_foreach_vch(dev, ch) { + dbsc5_ddr_setval(dev, ch, PI_INT_ACK_0, 0xFFFFFFFF); + dbsc5_ddr_setval(dev, ch, PI_INT_ACK_1, 0x7); + } + + return phytrainingok; +} + +/** + * dbsc5_read_vref_training() - Read Data Training with VREF Training + * @dev: DBSC5 device + * + * Set reading leveling to ON and Vref leveling of reading to OFF. + * Set Vref reading training to OFF. Get start value, end value and + * number of steps for Vref training. Determine the optimal VREFSEL + * value while increasing the Vref training setpoint by the starting + * value+step value. + */ +static u32 dbsc5_read_vref_training(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + const u32 rank = priv->ch_have_this_cs[1] ? 0x3 : 0x1; + u32 best_dvw_min_byte0, best_dvw_min_byte1; + u32 dvw_min_byte0_table[DRAM_CH_CNT][128]; + u32 dvw_min_byte1_table[DRAM_CH_CNT][128]; + u32 dvw_min_byte0[DRAM_CH_CNT] = { 0 }; + u32 dvw_min_byte1[DRAM_CH_CNT] = { 0 }; + u32 best_lower_vref, best_upper_vref; + u32 best_vref_byte0, best_vref_byte1; + u32 vref_start, vref_stop, vref_step; + u32 best_vref_byte0_index = 0; + u32 best_vref_byte1_index = 0; + const int retry_max = 0x10000; + u32 win_byte0, win_byte1; + u32 phytrainingok = 0; + u32 vref_stop_index; + u32 temple, tempte; + u32 best_thrshld; + u32 vref_outlier; + u32 outlier_cnt; + u32 curr_rank; + int i, retry; + u32 obs_sel; + u32 ch, reg; + + dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_EN_F2, 0x3); + dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_VREF_EN_F0, 0x0); + dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_VREF_EN_F1, 0x0); + dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_VREF_EN_F2, 0x0); + dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_VREF_TRAINING_CTRL, 0x0); + + /* ch0 vref_point */ + vref_start = dbsc5_ddr_getval(dev, 0, PHY_VREF_INITIAL_START_POINT); + vref_stop = dbsc5_ddr_getval(dev, 0, PHY_VREF_INITIAL_STOP_POINT); + vref_step = dbsc5_ddr_getval(dev, 0, PHY_VREF_INITIAL_STEPSIZE); + vref_stop_index = (vref_stop - vref_start) / vref_step; + + if (vref_stop_index > 0x80) + return 0; + + for (i = 0; i <= vref_stop_index; i++) { + r_foreach_vch(dev, ch) { + reg = dbsc5_ddr_getval_slice(dev, ch, 0, PHY_PAD_VREF_CTRL_DQ); + reg &= 0xF << 10; + dbsc5_ddr_setval_slice(dev, ch, 0, PHY_PAD_VREF_CTRL_DQ, + reg | BIT(9) | (vref_start + (vref_step * i))); + reg = dbsc5_ddr_getval_slice(dev, ch, 1, PHY_PAD_VREF_CTRL_DQ); + reg &= 0xF << 10; + dbsc5_ddr_setval_slice(dev, ch, 1, PHY_PAD_VREF_CTRL_DQ, + reg | BIT(9) | (vref_start + (vref_step * i))); + } + + for (curr_rank = 0; curr_rank < rank; curr_rank++) { + /* All ch Read Training Start */ + dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_CS_SW, BIT(curr_rank)); + dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_REQ, 0x1); + + phytrainingok = 0; + for (retry = 0; retry < retry_max; retry++) { + r_foreach_vch(dev, ch) + if (dbsc5_ddr_getval(dev, ch, PI_INT_STATUS) & BIT(25)) + phytrainingok |= BIT(ch); + + if (phytrainingok == priv->ddr_phyvalid) + break; + } + + /* Read Training End */ + dbsc5_ddr_setval_all_ch(dev, PI_INT_ACK_0, BIT(25)); + + r_foreach_vch(dev, ch) { + /* minimum Data Valid Window for each VREF */ + dvw_min_byte0[ch] = 0xFFFFFFFF; + dvw_min_byte1[ch] = 0xFFFFFFFF; + for (obs_sel = 0x0; obs_sel < 0x19; obs_sel++) { + if (!((obs_sel < 0x11) || (obs_sel == 0x18))) + continue; + + dbsc5_ddr_setval_slice(dev, ch, 0, + PHY_RDLVL_RDDQS_DQ_OBS_SELECT, + obs_sel); + dbsc5_ddr_setval_slice(dev, ch, 1, + PHY_RDLVL_RDDQS_DQ_OBS_SELECT, + obs_sel); + + temple = dbsc5_ddr_getval_slice(dev, ch, 0, + PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS); + tempte = dbsc5_ddr_getval_slice(dev, ch, 0, + PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS); + if (tempte > temple) + win_byte0 = tempte - temple; + else + win_byte0 = 0; + + temple = dbsc5_ddr_getval_slice(dev, ch, 1, + PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS); + tempte = dbsc5_ddr_getval_slice(dev, ch, 1, + PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS); + if (tempte > temple) + win_byte1 = tempte - temple; + else + win_byte1 = 0; + + if (dvw_min_byte0[ch] > win_byte0) + dvw_min_byte0[ch] = win_byte0; + + if (dvw_min_byte1[ch] > win_byte1) + dvw_min_byte1[ch] = win_byte1; + } + } + } + + r_foreach_vch(dev, ch) { + dvw_min_byte0_table[ch][i] = dvw_min_byte0[ch]; + dvw_min_byte1_table[ch][i] = dvw_min_byte1[ch]; + } + } + + r_foreach_vch(dev, ch) { + /* Search best VREF byte0 */ + best_vref_byte0 = vref_start; + best_vref_byte0_index = 0; + best_dvw_min_byte0 = dvw_min_byte0_table[ch][0]; + + for (i = 0; i <= vref_stop_index; i++) { + if (best_dvw_min_byte0 >= dvw_min_byte0_table[ch][i]) + continue; + + best_vref_byte0 = vref_start + (vref_step * i); + best_vref_byte0_index = i; + best_dvw_min_byte0 = dvw_min_byte0_table[ch][i]; + } + + /* Search best_lower VREF byte0 */ + reg = dbsc5_ddr_getval_slice(dev, ch, 0, PHY_RDLVL_DLY_STEP); + if (reg == 0) + reg = 1; + best_thrshld = dbsc5_ddr_getval_slice(dev, ch, 0, PHY_RDLVL_BEST_THRSHLD) * reg; + + vref_outlier = dbsc5_ddr_getval_slice(dev, ch, 0, PHY_RDLVL_VREF_OUTLIER); + best_lower_vref = best_vref_byte0; + outlier_cnt = vref_outlier; + for (i = best_vref_byte0_index; i >= 0; i--) { + if (dvw_min_byte0_table[ch][i] <= 0) + break; + + if (dvw_min_byte0_table[ch][i] >= (best_dvw_min_byte0 - best_thrshld)) { + best_lower_vref = vref_start + (vref_step * i); + } else { + if (outlier_cnt > 0) + outlier_cnt--; + else + break; + } + + if (i == 0) + break; + } + + /* Search best_upper VREF byte0 */ + vref_outlier = dbsc5_ddr_getval_slice(dev, ch, 0, PHY_RDLVL_VREF_OUTLIER); + best_upper_vref = best_vref_byte0; + outlier_cnt = vref_outlier; + for (i = best_vref_byte0_index; i <= vref_stop_index; i++) { + if (dvw_min_byte0_table[ch][i] <= 0) + break; + + if (dvw_min_byte0_table[ch][i] >= (best_dvw_min_byte0 - best_thrshld)) { + best_upper_vref = vref_start + (vref_step * i); + } else { + if (outlier_cnt > 0) + outlier_cnt--; + else + break; + } + } + + /* Calculate center of best vref range byte0 */ + best_vref_byte0 = (best_lower_vref + best_upper_vref) / 2; + + /* Search best VREF byte1 */ + best_vref_byte1 = vref_start; + best_vref_byte1_index = 0; + best_dvw_min_byte1 = dvw_min_byte1_table[ch][0]; + for (i = 0; i <= vref_stop_index; i++) { + if (best_dvw_min_byte1 >= dvw_min_byte1_table[ch][i]) + continue; + + best_vref_byte1 = vref_start + (vref_step * i); + best_vref_byte1_index = i; + best_dvw_min_byte1 = dvw_min_byte1_table[ch][i]; + } + + /* Search best_lower VREF byte1 */ + reg = dbsc5_ddr_getval_slice(dev, ch, 1, PHY_RDLVL_DLY_STEP); + if (reg == 0) + reg = 1; + best_thrshld = dbsc5_ddr_getval_slice(dev, ch, 1, PHY_RDLVL_BEST_THRSHLD) * reg; + + vref_outlier = dbsc5_ddr_getval_slice(dev, ch, 1, PHY_RDLVL_VREF_OUTLIER); + best_lower_vref = best_vref_byte1; + outlier_cnt = vref_outlier; + for (i = best_vref_byte1_index; i >= 0; i--) { + if (dvw_min_byte1_table[ch][i] <= 0) + break; + + if (dvw_min_byte1_table[ch][i] >= (best_dvw_min_byte1 - best_thrshld)) { + best_lower_vref = vref_start + (vref_step * i); + } else { + if (outlier_cnt > 0) + outlier_cnt--; + else + break; + } + + if (i == 0) + break; + } + + /* Search best_upper VREF byte1 */ + vref_outlier = dbsc5_ddr_getval_slice(dev, ch, 1, PHY_RDLVL_VREF_OUTLIER); + best_upper_vref = best_vref_byte1; + outlier_cnt = vref_outlier; + for (i = best_vref_byte1_index; i <= vref_stop_index; i++) { + if (dvw_min_byte1_table[ch][i] <= 0) + break; + + if (dvw_min_byte1_table[ch][i] >= (best_dvw_min_byte1 - best_thrshld)) { + best_upper_vref = vref_start + (vref_step * i); + } else { + if (outlier_cnt > 0) + outlier_cnt--; + else + break; + } + } + + /* Calculate center of best vref range byte1 */ + best_vref_byte1 = (best_lower_vref + best_upper_vref) / 2; + + reg = dbsc5_ddr_getval_slice(dev, ch, 0, PHY_PAD_VREF_CTRL_DQ); + reg &= 0xF << 10; + dbsc5_ddr_setval_slice(dev, ch, 0, PHY_PAD_VREF_CTRL_DQ, + reg | BIT(9) | best_vref_byte0); + reg = dbsc5_ddr_getval_slice(dev, ch, 1, PHY_PAD_VREF_CTRL_DQ); + reg &= 0xF << 10; + dbsc5_ddr_setval_slice(dev, ch, 1, PHY_PAD_VREF_CTRL_DQ, + reg | BIT(9) | best_vref_byte1); + } + + return phytrainingok; +} + +/** + * dbsc5_read_write_training() - Read Data & RDDQ Training with best VREF & Write DQ VREF Training + * @dev: DBSC5 device + * + * Set read DQS/RDQS slave delay setting to 0. Write leveling set to OFF, + * read gate leveling set to OFF. Turn on read and write leveling. Start + * frequency training. Training in high-frequency mode. Wait until training + * is complete. Check for errors in write dq leveling and read leveling. + + * If an error is confirmed to have occurred, return the inverted result + * value. Clear the PI status register. + */ +static u32 dbsc5_read_write_training(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + const int retry_max = 0x10000; + u32 wdq_training_ng = 0; + u32 rd_training_ng = 0; + u32 phytrainingok = 0; + u32 complete_ng = 0; + int retry, ret; + u32 ch, reg; + + /* RDDQ_SLAVE_DELAY Set 0x0050 -> 0x0000 */ + dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_RDDQ0_SLAVE_DELAY, 0x0); + dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_RDDQ1_SLAVE_DELAY, 0x0); + dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_RDDQ2_SLAVE_DELAY, 0x0); + dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_RDDQ3_SLAVE_DELAY, 0x0); + dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_RDDQ4_SLAVE_DELAY, 0x0); + dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_RDDQ5_SLAVE_DELAY, 0x0); + dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_RDDQ6_SLAVE_DELAY, 0x0); + dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_RDDQ7_SLAVE_DELAY, 0x0); + dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_RDDM_SLAVE_DELAY, 0x0); + + dbsc5_ddr_setval_all_ch(dev, PI_WRLVL_EN_F2, 0x0); + dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_GATE_EN_F2, 0x0); + dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_EN_F2, 0x3); + dbsc5_ddr_setval_all_ch(dev, PI_WDQLVL_EN_F2, 0x3); + + dbsc5_ddr_setval_all_ch(dev, PI_TRAIN_ALL_FREQ_REQ, 0x1); + + /* Freq Change High to High*/ + ret = dbsc5_clk_pll3_freq(dev); + if (ret) + return ret; + + for (retry = 0; retry < retry_max; retry++) { + r_foreach_vch(dev, ch) + if (dbsc5_ddr_getval(dev, ch, PI_INT_STATUS) & BIT(0)) + phytrainingok |= BIT(ch); + + if (phytrainingok == priv->ddr_phyvalid) + break; + } + + /* Error Check */ + r_foreach_vch(dev, ch) { + /* Rdlvl Error Check */ + /* PI_RDLVL_ERROR_BIT */ + reg = dbsc5_ddr_getval(dev, ch, PI_INT_STATUS) & BIT(1); + if (reg) { + rd_training_ng |= BIT(ch); + printf("%s read_write_training_error:1\n", __func__); + } + + /* Wdqlvl Error Check */ + /* PI_WDQLVL_ERROR_BIT */ + reg = dbsc5_ddr_getval(dev, ch, PI_INT_STATUS) & BIT(5); + /* SLICE0 wdqlvl_fail_dqZ */ + reg |= dbsc5_ddr_getval_slice(dev, ch, 0, PHY_WDQLVL_STATUS_OBS) & (0x1FF << 18); + /* SLICE1 wdqlvl_fail_dqZ */ + reg |= dbsc5_ddr_getval_slice(dev, ch, 1, PHY_WDQLVL_STATUS_OBS) & (0x1FF << 18); + if (reg) { + wdq_training_ng |= BIT(ch); + printf("%s read_write_training_error:2\n", __func__); + } + } + + complete_ng = wdq_training_ng | rd_training_ng; + if (complete_ng) + return ~complete_ng; + + /* PI_INT_ACK assert */ + r_foreach_vch(dev, ch) { + dbsc5_ddr_setval(dev, ch, PI_INT_ACK_0, 0xFFFFFFFF); + dbsc5_ddr_setval(dev, ch, PI_INT_ACK_1, 0x7); + } + + return phytrainingok; +} + +/** + * dbsc5_read_training() - Correct RDDQ Training result & Re-Run Read Data Training + * @dev: DBSC5 device + * + * Set the Read DQ correction value and its upper limit from the board + * settings. Check DDR memory ranks. Add the offset value to the current + * Read DQ value and write it to the register. Write the setting value + * to PI_RDLVL_TRAIN_SEQ_x. Start the Read training. PI_INT_ACK assert. + * Execute the Rdlvl Error Check. Confirm that training has been successfully + * completed. Return the result of the confirmation as the return value. + */ +static u32 dbsc5_read_training(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + const u32 rank = priv->ch_have_this_cs[1] ? 0x3 : 0x1; + const u32 rddq_delay_offset_ps = 0x19; + const u32 rddq_delay_max_ps = 0x67; + const u32 rddq_delay_addr[] = { + PHY_RDDQ0_SLAVE_DELAY, PHY_RDDQ1_SLAVE_DELAY, PHY_RDDQ2_SLAVE_DELAY, + PHY_RDDQ3_SLAVE_DELAY, PHY_RDDQ4_SLAVE_DELAY, PHY_RDDQ5_SLAVE_DELAY, + PHY_RDDQ6_SLAVE_DELAY, PHY_RDDQ7_SLAVE_DELAY, PHY_RDDM_SLAVE_DELAY + }; + const u32 rddq_delay_offset = rddq_delay_offset_ps * priv->ddr_mbps * 256 / + (priv->ddr_mbpsdiv * 2 * 1000000); + const u32 rddq_delay_max = rddq_delay_max_ps * priv->ddr_mbps * 256 / + (priv->ddr_mbpsdiv * 2 * 1000000); + u32 rd_training_ng = 0; + u32 ch, reg, slice; + u32 phytrainingok; + int i; + + r_foreach_vch(dev, ch) { + for (slice = 0; slice < SLICE_CNT; slice++) { + for (i = 0; i < 9; i++) { + reg = dbsc5_ddr_getval_slice(dev, ch, slice, + rddq_delay_addr[i]) + + rddq_delay_offset; + if (reg > rddq_delay_max) + reg = rddq_delay_max; + dbsc5_ddr_setval_slice(dev, ch, slice, rddq_delay_addr[i], reg); + } + } + } + + dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_TRAIN_SEQ_1, 0x89080); + dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_TRAIN_SEQ_2, 0x811C0); + dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_TRAIN_SEQ_3, 0x40811C0); + dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_TRAIN_SEQ_4, 0x2000000); + dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_TRAIN_SEQ_5, 0x0); + dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_CS_SW, rank); + + /* Read training go */ + dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_REQ, 0x1); + + /* PI_INT_ACK assert */ + phytrainingok = dbsc5_pi_int_ack_0_assert(dev, 25); + if (phytrainingok != priv->ddr_phyvalid) + return phytrainingok; + + /* Error Check */ + r_foreach_vch(dev, ch) { + /* Rdlvl Error Check */ + /* PI_RDLVL_ERROR_BIT */ + reg = dbsc5_ddr_getval(dev, ch, PI_INT_STATUS) & BIT(1); + if (reg) { + rd_training_ng |= BIT(ch); + printf("%s read_training_error\n", __func__); + } + } + + if (rd_training_ng) + return ~rd_training_ng; + + return phytrainingok; +} + +/** + * dbsc5_ddr_register_set() - DDR mode register setting + * @dev: DBSC5 device + * + * Set the mode register 28 of the SDRAM. + * ZQ Mode: Command-Based ZQ Calibration + * ZQ interval: Background Cal Interval < 64ms + */ +static void dbsc5_ddr_register_set(struct udevice *dev) +{ + dbsc5_send_dbcmd2(dev, 0xE841C24); +} + +/** + * dbsc5_ddr_register_read() - DDR mode register read + * @dev: DBSC5 device + * + * Set the mode register 27 and 57 of the SDRAM. + */ +static void dbsc5_ddr_register_read(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + + if (!priv->dbsc5_board_config->bdcfg_rfm_chk) + return; + + /* MR27 rank0 */ + dbsc5_send_dbcmd2(dev, 0xF801B00); + /* MR57 rank0 */ + dbsc5_send_dbcmd2(dev, 0xF803900); + + if (!priv->ch_have_this_cs[1]) + return; + + /* MR27 rank1 */ + dbsc5_send_dbcmd2(dev, 0xF811B00); + /* MR57 rank1 */ + dbsc5_send_dbcmd2(dev, 0xF813900); +} + +/** + * dbsc5_init_ddr() - Initialize DDR + * @dev: DBSC5 device + * + * Status monitor and perform reset and software reset for DDR. + * Disable DDRPHY software reset. Unprotect the DDRPHY register. + * Perform pre-setting of DBSC registers. Configure the ddrphy + * registers. Process ddr backup. Set DBSC registers. + * + * Initialize DFI and perform PI training. Setup DDR mode registers + * pre-traning. Adjust number of write leveling cycles. Perform PI + * training in manual mode. Perform DRAM DCA training. Perform write + * leveling. Execute phydca training. Execute read gate training. + * + * Perform Vref training on read gate. Read DQ Write DQ Execute. + * Frequency selection change (F1->F2). Disable the FREQ_SEL_MULTICAST & + * PER_CS_TRAINING_MULTICAST. Start setting DDR mode registers. Set DBSC + * registers after training is completed. Set write protection for PHY + * registers. + */ +static u32 dbsc5_init_ddr(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET; + u32 phytrainingok; + u32 ch, val; + int ret; + + /* PLL3 initialization setting */ + /* Reset Status Monitor clear */ + dbsc5_clk_cpg_write_32(dev, priv->cpg_regs + CPG_FSRCHKCLRR4, 0x600); + /* Reset Status Monitor set */ + dbsc5_clk_cpg_write_32(dev, priv->cpg_regs + CPG_FSRCHKSETR4, 0x600); + /* ddrphy soft reset assert */ + dbsc5_clk_cpg_write_32(dev, priv->cpg_regs + CPG_SRCR4, readl(priv->cpg_regs + CPG_SRCR4) | 0x600); + /* Wait reset FB */ + ret = readl_poll_timeout(priv->cpg_regs + CPG_FSRCHKRA4, val, ((val & 0x600) == 0), 1000000); + if (ret < 0) { + printf("%s CPG_FSRCHKRA4 Wait reset FB timeout\n", __func__); + hang(); + } + /* Reset Status Monitor clear */ + dbsc5_clk_cpg_write_32(dev, priv->cpg_regs + CPG_FSRCHKCLRR4, 0x600); + + /* Initialize PLL3 setting */ + dbsc5_clk_pll3_control(dev, PLL3_HIGH_FREQUENCY_MODE_LOAD_REGISTER); + + /* DDRPHY soft reset negate */ + dbsc5_clk_cpg_write_32(dev, priv->cpg_regs + CPG_SRSTCLR4, 0x600); + ret = readl_poll_timeout(priv->cpg_regs + CPG_SRCR4, val, ((val & 0x600) == 0), 1000000); + if (ret < 0) { + printf("%s CPG_SRCR4 DDRPHY soft reset negate timeout\n", __func__); + hang(); + } + + /* Unlock PHY */ + /* Unlock DDRPHY register */ + r_foreach_vch(dev, ch) + writel(0xA55A, regs_dbsc_d + DBSC_DBPDLK(ch)); + + /* DBSC register pre-setting */ + dbsc5_dbsc_regset_pre(dev); + + /* Load DDRPHY registers */ + dbsc5_ddrtbl_calc(priv); + dbsc5_ddrtbl_load(dev); + + /* Configure ddrphy registers */ + dbsc5_ddr_config(dev); + + /* DDR backupmode end */ + + /* DBSC register set */ + dbsc5_dbsc_regset(dev); + + /* Frequency selection change (F1->F2) */ + dbsc5_ddr_setval_all_ch(dev, PHY_FREQ_SEL_INDEX, 0x1); + dbsc5_ddr_setval_all_ch(dev, PHY_FREQ_SEL_MULTICAST_EN, 0x0); + + /* dfi_init_start (start ddrphy) & execute pi_training */ + phytrainingok = dbsc5_pi_training(dev); + if (priv->ddr_phyvalid != phytrainingok) { + printf("%s init_ddr_error:1\n", __func__); + return phytrainingok; + } + + /* Write leveling cycle adjust */ + dbsc5_write_leveling_adjust(dev); + + /* Execute write leveling & read gate training */ + phytrainingok = dbsc5_wl_gt_training(dev); + if (priv->ddr_phyvalid != phytrainingok) { + printf("%s init_ddr_error:2\n", __func__); + return phytrainingok; + } + + /* Execute write dca training */ + dbsc5_write_dca(dev); + + /* Execute dram dca training */ + phytrainingok = dbsc5_dramdca_training(dev); + + if (priv->ddr_phyvalid != phytrainingok) { + printf("%s init_ddr_error:3\n", __func__); + return phytrainingok; + } + + /* Execute write leveling */ + phytrainingok = dbsc5_write_leveling(dev); + + if (priv->ddr_phyvalid != phytrainingok) { + printf("%s init_ddr_error:4\n", __func__); + return phytrainingok; + } + + /* Execute manual write dca training */ + dbsc5_manual_write_dca(dev); + + /* Execute read gate training */ + phytrainingok = dbsc5_read_gate_training(dev); + + if (priv->ddr_phyvalid != phytrainingok) { + printf("%s init_ddr_error:5\n", __func__); + return phytrainingok; + } + + /* Execute read vref training */ + phytrainingok = dbsc5_read_vref_training(dev); + + if (priv->ddr_phyvalid != phytrainingok) { + printf("%s init_ddr_error:6\n", __func__); + return phytrainingok; + } + + /* Execute read dq & write dq training with best vref */ + phytrainingok = dbsc5_read_write_training(dev); + if (priv->ddr_phyvalid != phytrainingok) { + printf("%s init_ddr_error:7\n", __func__); + return phytrainingok; + } + + /* correct rddq training result & Execute read dq training */ + phytrainingok = dbsc5_read_training(dev); + + if (priv->ddr_phyvalid != phytrainingok) { + printf("%s init_ddr_error:8\n", __func__); + return phytrainingok; + } + + /* PER_CS_TRAINING_MULTICAST SET (disable) */ + dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_PER_CS_TRAINING_MULTICAST_EN, 0x0); + + /* setup DDR mode registers */ + /* MRS */ + dbsc5_ddr_register_set(dev); + + /* MRR */ + dbsc5_ddr_register_read(dev); + + /* training complete, setup DBSC */ + dbsc5_dbsc_regset_post(dev); + + /* Lock PHY */ + /* Lock DDRPHY register */ + r_foreach_vch(dev, ch) + writel(0x0, regs_dbsc_d + DBSC_DBPDLK(ch)); + + return phytrainingok; +} + +/** + * dbsc5_get_board_data() - Obtain board specific DRAM configuration + * + * Return board specific DRAM configuration structure pointer. + */ +__weak const struct renesas_dbsc5_board_config *dbsc5_get_board_data(void) +{ + return &renesas_v4h_dbsc5_board_config; +} + +/** + * renesas_dbsc5_dram_probe() - DDR Initialize entry + * @dev: DBSC5 device + * + * Remove write protection on DBSC register. Read DDR configuration + * information from driver data. Calculate board clock frequency and + * operating frequency from DDR configuration information. Call the + * main function of DDR initialization. Perform DBSC write protection + * after initialization is complete. + */ +static int renesas_dbsc5_dram_probe(struct udevice *dev) +{ +#define RST_MODEMR0 0x0 +#define RST_MODEMR1 0x4 + struct renesas_dbsc5_data *data = (struct renesas_dbsc5_data *)dev_get_driver_data(dev); + ofnode cnode = ofnode_by_compatible(ofnode_null(), data->clock_node); + ofnode rnode = ofnode_by_compatible(ofnode_null(), data->reset_node); + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + void __iomem *regs_dbsc_a = priv->regs + DBSC5_DBSC_A_OFFSET; + void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET; + phys_addr_t rregs = ofnode_get_addr(rnode); + const u32 modemr0 = readl(rregs + RST_MODEMR0); + const u32 modemr1 = readl(rregs + RST_MODEMR1); + u32 breg, reg, md, sscg; + u32 ch, cs; + + /* Get board data */ + priv->dbsc5_board_config = dbsc5_get_board_data(); + priv->ddr_phyvalid = (u32)(priv->dbsc5_board_config->bdcfg_phyvalid); + priv->max_density = 0; + priv->cpg_regs = (void __iomem *)ofnode_get_addr(cnode); + + for (cs = 0; cs < CS_CNT; cs++) + priv->ch_have_this_cs[cs] = 0; + + r_foreach_ech(ch) + for (cs = 0; cs < CS_CNT; cs++) + priv->ddr_density[ch][cs] = 0xFF; + + r_foreach_vch(dev, ch) { + for (cs = 0; cs < CS_CNT; cs++) { + priv->ddr_density[ch][cs] = priv->dbsc5_board_config->ch[ch].bdcfg_ddr_density[cs]; + + if (priv->ddr_density[ch][cs] == 0xFF) + continue; + + if (priv->ddr_density[ch][cs] > priv->max_density) + priv->max_density = priv->ddr_density[ch][cs]; + + priv->ch_have_this_cs[cs] |= BIT(ch); + } + } + + /* Decode board clock frequency from MD[14:13] pins */ + priv->brd_clkdiv = 3; + + breg = (modemr0 >> 13) & 0x3; + if (breg == 0) { + priv->brd_clk = 50; /* 16.66 MHz */ + priv->bus_clk = priv->brd_clk * 0x18; + priv->bus_clkdiv = priv->brd_clkdiv; + } else if (breg == 1) { + priv->brd_clk = 60; /* 20 MHz */ + priv->bus_clk = priv->brd_clk * 0x14; + priv->bus_clkdiv = priv->brd_clkdiv; + } else if (breg == 3) { + priv->brd_clk = 100; /* 33.33 MHz */ + priv->bus_clk = priv->brd_clk * 0x18; + priv->bus_clkdiv = priv->brd_clkdiv * 2; + } else { + printf("MD[14:13] setting 0x%x not supported!", breg); + hang(); + } + + priv->brd_clkdiva = !!(modemr0 & BIT(14)); /* MD14 */ + + /* Decode DDR operating frequency from MD[37:36,19,17] pins */ + md = ((modemr0 & BIT(19)) >> 18) | ((modemr0 & BIT(17)) >> 17); + sscg = (modemr1 >> 4) & 0x03; + if (sscg == 2) { + printf("MD[37:36] setting 0x%x not supported!", sscg); + hang(); + } + + if (md == 0) { + if (sscg == 0) { + priv->ddr_mbps = 6400; + priv->ddr_mbpsdiv = 1; + } else { + priv->ddr_mbps = 19000; + priv->ddr_mbpsdiv = 3; + } + } else if (md == 1) { + priv->ddr_mbps = 6000; + priv->ddr_mbpsdiv = 1; + } else if (md == 1) { + priv->ddr_mbps = 5500; + priv->ddr_mbpsdiv = 1; + } else if (md == 1) { + priv->ddr_mbps = 4800; + priv->ddr_mbpsdiv = 1; + } + + priv->ddr_mul = CLK_DIV(priv->ddr_mbps, priv->ddr_mbpsdiv * 2, + priv->brd_clk, priv->brd_clkdiv * (priv->brd_clkdiva + 1)); + priv->ddr_mul_low = CLK_DIV(6400, 2, priv->brd_clk, + priv->brd_clkdiv * (priv->brd_clkdiva + 1)); + + priv->ddr_mul_reg = priv->ddr_mul_low; + if (sscg != 0) + priv->ddr_mul_reg -= 2; + + priv->ddr_mul_nf = ((8 * priv->ddr_mbps * priv->brd_clkdiv * (priv->brd_clkdiva + 1)) / + (priv->ddr_mbpsdiv * priv->brd_clk * 2)) - (8 * (priv->ddr_mul / 2) * 2); + + /* Adjust tccd */ + priv->ddr_tccd = 2; + + /* Initialize DDR */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBSYSCNT0, 0x1234); + dbsc5_reg_write(regs_dbsc_a + DBSC_DBSYSCNT0A, 0x1234); + + reg = dbsc5_init_ddr(dev); + + dbsc5_reg_write(regs_dbsc_d + DBSC_DBSYSCNT0, 0x0); + dbsc5_reg_write(regs_dbsc_a + DBSC_DBSYSCNT0A, 0x0); + + return reg != priv->ddr_phyvalid; +} + +/** + * renesas_dbsc5_dram_of_to_plat() - Convert OF data to plat data + * @dev: DBSC5 device + * + * Extract DBSC5 address from DT and store it in driver data. + */ +static int renesas_dbsc5_dram_of_to_plat(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + + priv->regs = dev_read_addr_ptr(dev); + if (!priv->regs) + return -EINVAL; + + return 0; +} + +/** + * renesas_dbsc5_dram_get_info() - Return RAM size + * @dev: DBSC5 device + * @info: Output RAM info + * + * Return size of the RAM managed by this RAM driver. + */ +static int renesas_dbsc5_dram_get_info(struct udevice *dev, + struct ram_info *info) +{ + info->base = 0x40000000; + info->size = 0; + + return 0; +} + +static const struct ram_ops renesas_dbsc5_dram_ops = { + .get_info = renesas_dbsc5_dram_get_info, +}; + +U_BOOT_DRIVER(renesas_dbsc5_dram) = { + .name = "dbsc5_dram", + .id = UCLASS_RAM, + .of_to_plat = renesas_dbsc5_dram_of_to_plat, + .ops = &renesas_dbsc5_dram_ops, + .probe = renesas_dbsc5_dram_probe, + .priv_auto = sizeof(struct renesas_dbsc5_dram_priv), +}; diff --git a/drivers/ram/renesas/dbsc5/qos.c b/drivers/ram/renesas/dbsc5/qos.c new file mode 100644 index 00000000000..56a60b987af --- /dev/null +++ b/drivers/ram/renesas/dbsc5/qos.c @@ -0,0 +1,636 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +#include <asm/io.h> +#include <dm.h> +#include <errno.h> +#include <hang.h> +#include <linux/sizes.h> +#include <ram.h> +#include "dbsc5.h" + +/* AXMM */ +#define AXMM_ADSPLCR0 0x4008 +#define AXMM_ADSPLCR1 0x400C +#define AXMM_ADSPLCR2 0x4010 +#define AXMM_ADSPLCR3 0x4014 +#define AXMM_MMCR 0x4300 +#define AXMM_TR0CR0 0x51000 +#define AXMM_TR1CR0 0x51004 +#define AXMM_TR2CR0 0x51008 +#define AXMM_TR3CR 0x5100C +#define AXMM_TR3CR0 0x5100C +#define AXMM_TR0CR1 0x51100 +#define AXMM_TR1CR1 0x51104 +#define AXMM_TR2CR1 0x51108 +#define AXMM_TR3CR1 0x5110C +#define AXMM_TR0CR2 0x51200 +#define AXMM_TR1CR2 0x51204 +#define AXMM_TR2CR2 0x51208 +#define AXMM_TR3CR2 0x5120C + +#define ACTEXT_RT0_R 0xFFC50800 +#define ACTEXT_RT0_W 0xFFC51800 +#define ACTEXT_IR0_R 0xFF890800 +#define ACTEXT_IR0_W 0xFF891800 +#define ACTEXT_IR1_R 0xFF892800 +#define ACTEXT_IR1_W 0xFF893800 +#define SI0_RW_MAX 0xF1201110 +#define SI1_RW_MAX 0xF1202110 + +/* DBSC */ +#define DBSC_A_CH_OFFSET 0x8000 +#define DBSC_D_CH_OFFSET 0x4000 + +#define DBSC_SYSCNT0 0x0100 +#define DBSC_SYSCNT1 0x0104 +#define DBSC_FCPRSCTRL 0x0110 +#define DBSC_DBBUS0CNF2 0x0808 +#define DBSC_DBCAM0CNF1 0x0904 +#define DBSC_DBCAM0CNF2 0x0908 +#define DBSC_DBCAM0CNF3 0x090C +#define DBSC_DBCAMDIS 0x09FC +#define DBSC_DBSCHCNT0 0x1000 +#define DBSC_DBSCHSZ0 0x1010 +#define DBSC_DBSCHRW0 0x1020 +#define DBSC_SCFCTST2 0x1048 +#define DBSC_DBSCHQOS_0_0 0x1100 +#define DBSC_DBSCHQOS_0_1 0x1104 +#define DBSC_DBSCHQOS_0_2 0x1108 +#define DBSC_DBSCHQOS_0_3 0x110C +#define DBSC_DBSCHQOS_4_0 0x1140 +#define DBSC_DBSCHQOS_4_1 0x1144 +#define DBSC_DBSCHQOS_4_2 0x1148 +#define DBSC_DBSCHQOS_4_3 0x114C +#define DBSC_DBSCHQOS_9_0 0x1190 +#define DBSC_DBSCHQOS_9_1 0x1194 +#define DBSC_DBSCHQOS_9_2 0x1198 +#define DBSC_DBSCHQOS_9_3 0x119C +#define DBSC_DBSCHQOS_12_0 0x11C0 +#define DBSC_DBSCHQOS_12_1 0x11C4 +#define DBSC_DBSCHQOS_12_2 0x11C8 +#define DBSC_DBSCHQOS_12_3 0x11CC +#define DBSC_DBSCHQOS_13_0 0x11D0 +#define DBSC_DBSCHQOS_13_1 0x11D4 +#define DBSC_DBSCHQOS_13_2 0x11D8 +#define DBSC_DBSCHQOS_13_3 0x11DC +#define DBSC_DBSCHQOS_14_0 0x11E0 +#define DBSC_DBSCHQOS_14_1 0x11E4 +#define DBSC_DBSCHQOS_14_2 0x11E8 +#define DBSC_DBSCHQOS_14_3 0x11EC +#define DBSC_DBSCHQOS_15_0 0x11F0 +#define DBSC_DBSCHQOS_15_1 0x11F4 +#define DBSC_DBSCHQOS_15_2 0x11F8 +#define DBSC_DBSCHQOS_15_3 0x11FC + +/* CCI */ +#define CCIQOS00 0xC020 +#define CCIQOS01 0xC024 +#define CCIQOS10 0xD000 +#define CCIQOS11 0xD004 + +/* QOS */ +#define QOS_FIX_QOS_BANK0 0x0 +#define QOS_FIX_QOS_BANK1 0x1000 +#define QOS_BE_QOS_BANK0 0x2000 +#define QOS_BE_QOS_BANK1 0x3000 +#define QOS_SL_INIT 0x8000 +#define QOS_REF_ARS 0x8004 +#define QOS_STATQC 0x8008 +#define QOS_REF_ENBL 0x8044 +#define QOS_BWG 0x804C +#define QOS_RAS 0x10000 +#define QOS_FSS 0x10048 +#define QOS_RAEN 0x10018 +#define QOS_DANN_LOW 0x10030 +#define QOS_DANN_HIGH 0x10034 +#define QOS_DANT 0x10038 +#define QOS_EMS_LOW 0x10040 +#define QOS_EMS_HIGH 0x10044 +#define QOS_INSFC 0x10050 +#define QOS_EARLYR 0x10060 +#define QOS_RACNT0 0x10080 +#define QOS_STATGEN0 0x10088 + +#define QOSWT_FIX_QOS_BANK0 0x800 +#define QOSWT_FIX_QOS_BANK1 0x1800 +#define QOSWT_BE_QOS_BANK0 0x2800 +#define QOSWT_BE_QOS_BANK1 0x3800 +#define QOSWT_WTEN 0x8030 +#define QOSWT_WTREF 0x8034 +#define QOSWT_WTSET0 0x8038 +#define QOSWT_WTSET1 0x803C + +static const struct { + u64 fix; + u64 be; +} g_qosbw_tbl[] = { + { 0x000C04010000FFFF, 0x00200030004FFC01 }, + { 0x000C04010000FFFF, 0x00100030004FFC01 }, + { 0x000C04010000FFFF, 0x00100030004FFC01 }, + { 0x000C04010000FFFF, 0x00200030004FFC01 }, + { 0x000C04010000FFFF, 0x00100030004FFC01 }, + { 0x000C04010000FFFF, 0x00100030004FFC01 }, + { 0x000C04010000FFFF, 0x00100030004FFC01 }, + { 0x000C04010000FFFF, 0x00100030004FFC01 }, + { 0x000C04010000FFFF, 0x00100030004FFC01 }, + { 0x000C04010000FFFF, 0x00200030004FFC01 }, + { 0x000C04010000FFFF, 0x0000000000000000 }, + { 0x000C04080000FFFF, 0x00200030004FFC01 }, + { 0x000C04080000FFFF, 0x00100030004FFC01 }, + { 0x000C04080000FFFF, 0x00100030004FFC01 }, + { 0x000C04080000FFFF, 0x00100030004FFC01 }, + { 0x000C04010000FFFF, 0x00200030004FFC01 }, + { 0x000C04080000FFFF, 0x00100030004FFC01 }, + { 0x000C04080000FFFF, 0x00100030004FFC01 }, + { 0x000C04080000FFFF, 0x00100030004FFC01 }, + { 0x000C04080000FFFF, 0x00100030004FFC01 }, + { 0x000C04100000FFFF, 0x00100030004FFC01 }, + { 0x000C04100000FFFF, 0x00100030004FFC01 }, + { 0x000C04100000FFFF, 0x0000000000000000 }, + { 0x000C08140000FFFF, 0x00100030004FFC01 }, + { 0x000C08140000FFFF, 0x00100030004FFC01 }, + { 0x000000000000FFF0, 0x0000000000000000 }, + { 0x000C04100000FFFF, 0x00100030004FFC01 }, + { 0x000C04100000FFFF, 0x00100030004FFC01 }, + { 0x000C04100000FFFF, 0x0000000000000000 }, + { 0x000C04080000FFFF, 0x00100030004FFC01 }, + { 0x000C08140000FFFF, 0x00100030004FFC01 }, + { 0x000000000000FFFF, 0x0000000000000000 }, + { 0x000C04080000FFFF, 0x00100030004FFC01 }, + { 0x000C04080000FFFF, 0x00100030004FFC01 }, + { 0x000C04080000FFFF, 0x00100030004FFC01 }, + { 0x000C04080000FFFF, 0x00100030004FFC01 }, + { 0x000C04080000FFFF, 0x00100030004FFC01 }, + { 0x000C04080000FFFF, 0x00100030004FFC01 }, + { 0x001404080000FFFF, 0x00100030004FFC01 }, + { 0x001404080000FFFF, 0x00100030004FFC01 }, + { 0x000C04010000FFFF, 0x001000F0004FFC01 }, + { 0x000C04010000FFFF, 0x001000F0004FFC01 }, + { 0x000C04010000FFFF, 0x002000F0004FFC01 }, + { 0x000C04010000FFFF, 0x002000F0004FFC01 }, + { 0x000000000000FFFF, 0x0000000000000000 }, + { 0x000000000000FFFF, 0x0000000000000000 }, + { 0x000000000000FFFF, 0x0000000000000000 }, + { 0x000000000000FFFF, 0x0000000000000000 }, + { 0x000C144F0000FFFF, 0x00100030004FFC01 }, + { 0x000C144F0000FFFF, 0x00100030004FFC01 }, + { 0x000C144F0000FFFF, 0x00100030004FFC01 }, + { 0x000C144F0000FFFF, 0x00100030004FFC01 }, + { 0x000C144F0000FFFF, 0x00100030004FFC01 }, + { 0x000C144F0000FFFF, 0x00100030004FFC01 }, + { 0x000000000000FFFF, 0x0000000000000000 }, + { 0x000C144F0000FFFF, 0x00100030004FFC01 }, + { 0x000000000000FFFF, 0x0000000000000000 }, + { 0x000C144F0000FFFF, 0x00100030004FFC01 }, + { 0x000000000000FFFF, 0x0000000000000000 }, + { 0x000C144F0000FFFF, 0x00100030004FFC01 }, + { 0x000000000000FFFF, 0x0000000000000000 }, + { 0x000000000000FFFF, 0x0000000000000000 }, + { 0x000C144F0000FFFF, 0x00100030004FFC01 }, + { 0x000C144F0000FFFF, 0x00100030004FFC01 }, + { 0x000C04200000FFFF, 0x00100030004FFC01 }, + { 0x000C04100000FFFF, 0x00100030004FFC01 }, + { 0x000C144F0000FFFF, 0x00100030004FFC01 }, + { 0x000C144F0000FFFF, 0x00100030004FFC01 }, + { 0x000C0C4F0000FFFF, 0x00100030004FFC01 }, + { 0x000C0C4F0000FFFF, 0x00100030004FFC01 }, + { 0x001404080000FFFF, 0x00100030004FFC01 }, + { 0x000C04080000FFFF, 0x00100030004FFC01 }, + { 0x000C04080000FFFF, 0x00100030004FFC01 }, + { 0x000C04010000FFFF, 0x00100030004FFC01 }, + { 0x001424870000FFFF, 0x00100030004FFC01 }, + { 0x001424870000FFFF, 0x00100030004FFC01 }, + { 0x000C149E0000FFFF, 0x00100030004FFC01 }, + { 0x000C149E0000FFFF, 0x00100030004FFC01 }, + { 0x000000000000FFFF, 0x0000000000000000 }, + { 0x000000000000FFFF, 0x0000000000000000 }, + { 0x00140C050000FFFF, 0x00100030004FFC01 }, + { 0x0014450E0000FFFF, 0x00100030004FFC01 }, + { 0x001424870000FFFF, 0x00100030004FFC01 }, + { 0x0014289E0000FFFF, 0x00000000000FFC00 }, + { 0x0014289E0000FFFF, 0x00000000000FFC00 }, + { 0x0014149E0000FFFF, 0x0000000000000000 }, + { 0x000000000000FFFF, 0x0000000000000000 }, + { 0x000000000000FFFF, 0x0000000000000000 }, + { 0x001004080000FFFF, 0x0000000000000000 }, + { 0x001004080000FFFF, 0x0000000000000000 }, + { 0x001004080000FFFF, 0x0000000000000000 }, + { 0x000C00000000FFFF, 0x001000F0004FFC01 }, + { 0x000C00000000FFFF, 0x001000F0004FFC01 }, + { 0x000C04080000FFFF, 0x00100030004FFC01 }, + { 0x000C04080000FFFF, 0x00100030004FFC01 }, + { 0x000000000000FFFF, 0x0000000000000000 }, + { 0x000C04080000FFFF, 0x00100030004FFC01 }, + { 0x000C04080000FFFF, 0x00100030004FFC01 }, + { 0x000C04080000FFFF, 0x00100030004FFC01 }, + { 0x000000000000FFFF, 0x0000000000000000 }, + { 0x000C04080000FFFF, 0x00100030004FFC01 }, + { 0x001404080000FFFF, 0x00100030004FFC01 }, + { 0x000C04080000FFFF, 0x00100030004FFC01 }, + { 0x000C04080000FFFF, 0x00100030004FFC01 }, + { 0x000000000000FFFF, 0x0000000000000000 }, + { 0x000000000000FFFF, 0x0000000000000000 }, + { 0x000000000000FFFF, 0x0000000000000000 }, + { 0x000000000000FFFF, 0x0000000000000000 }, + { 0x000000000000FFFF, 0x0000000000000000 }, + { 0x000000000000FFFF, 0x0000000000000000 }, + { 0x000000000000FFFF, 0x0000000000000000 }, + { 0x000000000000FFFF, 0x0000000000000000 }, + { 0x000000000000FFFF, 0x0000000000000000 }, + { 0x000000000000FFFF, 0x0000000000000000 }, + { 0x000C04010000FFFF, 0x001001D0004FFC01 }, + { 0x000000000000FFFF, 0x0000000000000000 }, + { 0x000C04010000FFFF, 0x001001D0004FFC01 }, + { 0x000000000000FFFF, 0x0000000000000000 }, + { 0x000C04010000FFFF, 0x001001D0004FFC01 }, + { 0x000C04010000FFFF, 0x00100030004FFC01 }, + { 0x000C04010000FFFF, 0x00100030004FFC01 }, + { 0x000C04010000FFFF, 0x001001D0004FFC01 }, + { 0x000C04010000FFFF, 0x00100030004FFC01 }, + { 0x000C04010000FFFF, 0x00100030004FFC01 }, + { 0x001404010000FFFF, 0x00100030004FFC01 } +}; + +static const struct { + u64 fix; + u64 be; +} g_qoswt_tbl[] = { + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x000C04050000FFFF, 0x0000000000000000 }, + { 0x000C080C0000FFFF, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x000C04050000C001, 0x0000000000000000 }, + { 0x000C080C0000C001, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x001424870000C001, 0x0000000000000000 }, + { 0x001424870000C001, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x001424870000FFFF, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 } +}; + +struct renesas_dbsc5_qos_priv { + void __iomem *regs; +}; + +static int dbsc5_qos_dbsc_setting(struct udevice *dev) +{ + struct renesas_dbsc5_qos_priv *priv = dev_get_priv(dev); + void __iomem *regs_dbsc_a, *regs_dbsc_d; + unsigned int ch, nch; + + if (IS_ENABLED(CONFIG_R8A779G0) && + renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A779G0) + nch = 2; + else if (IS_ENABLED(CONFIG_R8A779H0) && + renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A779H0) + nch = 1; + else + return -EINVAL; + + for (ch = 0; ch < nch; ch++) { + regs_dbsc_a = priv->regs + DBSC5_DBSC_A_OFFSET + ch * DBSC_A_CH_OFFSET; + regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET + ch * DBSC_D_CH_OFFSET; + + /* DBSC CAM, Scheduling Setting */ + writel(0x1234, regs_dbsc_d + DBSC_SYSCNT0); + writel(0x1234, regs_dbsc_a + DBSC_SYSCNT0); + writel(0x48218, regs_dbsc_a + DBSC_DBCAM0CNF1); + writel(0x1C4, regs_dbsc_a + DBSC_DBCAM0CNF2); + writel(0x3, regs_dbsc_a + DBSC_DBCAM0CNF3); + + if (IS_ENABLED(CONFIG_R8A779G0) && + renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A779G0 && + (renesas_get_cpu_rev_integer() < 2 || + (renesas_get_cpu_rev_integer() == 2 && + renesas_get_cpu_rev_fraction() <= 1))) { + /* OTLINT-5579: V4H <= rev2.1 DBSC W/A-3 */ + writel(0x11, regs_dbsc_a + DBSC_DBCAMDIS); + } else { + writel(0x10, regs_dbsc_a + DBSC_DBCAMDIS); + } + + writel(0xF0037, regs_dbsc_a + DBSC_DBSCHCNT0); + writel(0x1, regs_dbsc_a + DBSC_DBSCHSZ0); + writel(0xF7311111, regs_dbsc_a + DBSC_DBSCHRW0); + writel(0x111F1FFF, regs_dbsc_a + DBSC_SCFCTST2); + + /* OTLINT-5579: V4H DBSC WA3 */ + writel(0x7, regs_dbsc_a + DBSC_DBBUS0CNF2); + + /* DBSC QoS Setting */ + writel(0xFFFF, regs_dbsc_a + DBSC_DBSCHQOS_0_0); + writel(0x480, regs_dbsc_a + DBSC_DBSCHQOS_0_1); + writel(0x300, regs_dbsc_a + DBSC_DBSCHQOS_0_2); + writel(0x180, regs_dbsc_a + DBSC_DBSCHQOS_0_3); + writel(0x400, regs_dbsc_a + DBSC_DBSCHQOS_4_0); + writel(0x300, regs_dbsc_a + DBSC_DBSCHQOS_4_1); + writel(0x200, regs_dbsc_a + DBSC_DBSCHQOS_4_2); + writel(0x100, regs_dbsc_a + DBSC_DBSCHQOS_4_3); + writel(0x300, regs_dbsc_a + DBSC_DBSCHQOS_9_0); + writel(0x240, regs_dbsc_a + DBSC_DBSCHQOS_9_1); + writel(0x180, regs_dbsc_a + DBSC_DBSCHQOS_9_2); + writel(0xC0, regs_dbsc_a + DBSC_DBSCHQOS_9_3); + writel(0x40, regs_dbsc_a + DBSC_DBSCHQOS_12_0); + writel(0x30, regs_dbsc_a + DBSC_DBSCHQOS_12_1); + writel(0x20, regs_dbsc_a + DBSC_DBSCHQOS_12_2); + writel(0x10, regs_dbsc_a + DBSC_DBSCHQOS_12_3); + writel(0x300, regs_dbsc_a + DBSC_DBSCHQOS_13_0); + writel(0x240, regs_dbsc_a + DBSC_DBSCHQOS_13_1); + writel(0x180, regs_dbsc_a + DBSC_DBSCHQOS_13_2); + writel(0xC0, regs_dbsc_a + DBSC_DBSCHQOS_13_3); + writel(0x200, regs_dbsc_a + DBSC_DBSCHQOS_14_0); + writel(0x180, regs_dbsc_a + DBSC_DBSCHQOS_14_1); + writel(0x100, regs_dbsc_a + DBSC_DBSCHQOS_14_2); + writel(0x80, regs_dbsc_a + DBSC_DBSCHQOS_14_3); + writel(0x100, regs_dbsc_a + DBSC_DBSCHQOS_15_0); + writel(0xC0, regs_dbsc_a + DBSC_DBSCHQOS_15_1); + writel(0x80, regs_dbsc_a + DBSC_DBSCHQOS_15_2); + writel(0x40, regs_dbsc_a + DBSC_DBSCHQOS_15_3); + + /* Target register is only DBSC0 side. */ + if (ch == 0) + writel(0x1, regs_dbsc_a + DBSC_FCPRSCTRL); + + writel(0x1, regs_dbsc_a + DBSC_SYSCNT1); + writel(0x0, regs_dbsc_d + DBSC_SYSCNT0); + writel(0x0, regs_dbsc_a + DBSC_SYSCNT0); + } + + return 0; +} + +static int dbsc5_qos_settings_init(struct udevice *dev) +{ + struct renesas_dbsc5_qos_priv *priv = dev_get_priv(dev); + void __iomem *regs_axmm = priv->regs + DBSC5_AXMM_OFFSET; + void __iomem *regs_cci = priv->regs + DBSC5_CCI_OFFSET; + void __iomem *regs_qos = priv->regs + DBSC5_QOS_OFFSET; + int i; + + if (IS_ENABLED(CONFIG_R8A779G0) && + renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A779G0) { + /* Address Split 2ch */ + writel(0x0, regs_axmm + AXMM_ADSPLCR0); + writel(0xFF1B0C, regs_axmm + AXMM_ADSPLCR1); + writel(0x0, regs_axmm + AXMM_ADSPLCR2); + writel(0x0, regs_axmm + AXMM_ADSPLCR3); + + writel(0x8000000, regs_cci + CCIQOS00); + writel(0x8000000, regs_cci + CCIQOS01); + + if (renesas_get_cpu_rev_integer() >= 2) { + writel(0x1, regs_cci + CCIQOS10); + writel(0x1, regs_cci + CCIQOS11); + } else { + writel(0x0, regs_cci + CCIQOS10); + writel(0x0, regs_cci + CCIQOS11); + } + + /* Resource Alloc setting */ + writel(0x48, regs_qos + QOS_RAS); + } else if (IS_ENABLED(CONFIG_R8A779H0) && + renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A779H0) { + /* Resource Alloc setting */ + writel(0x30, regs_qos + QOS_RAS); + } else { + return -EINVAL; + } + + writel(0x2020201, regs_qos + QOS_DANN_LOW); + writel(0x4040200, regs_qos + QOS_DANN_HIGH); + writel(0x181008, regs_qos + QOS_DANT); + writel(0x0, regs_qos + QOS_EMS_LOW); + writel(0x0, regs_qos + QOS_EMS_HIGH); + writel(0xA, regs_qos + QOS_FSS); + writel(0x30F0001, regs_qos + QOS_INSFC); + writel(0x0, regs_qos + QOS_EARLYR); + writel(0x50003, regs_qos + QOS_RACNT0); + writel(0x0, regs_qos + QOS_STATGEN0); + + /* QoS MSTAT setting */ + writel(0x70120, regs_qos + QOS_SL_INIT); + writel(0x11B0000, regs_qos + QOS_REF_ARS); + writel(0x12, regs_qos + QOS_REF_ENBL); + writel(0x4, regs_qos + QOS_BWG); + + if (IS_ENABLED(CONFIG_R8A779G0) && + renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A779G0 && + (renesas_get_cpu_rev_integer() < 2 || + (renesas_get_cpu_rev_integer() == 2 && + renesas_get_cpu_rev_fraction() <= 1))) { + /* OTLINT-5579: V4H <= rev2.1 DBSC W/A-3 */ + writel(0x0, regs_axmm + AXMM_MMCR); + } else { + writel(0x10000, regs_axmm + AXMM_MMCR); + } + + writel(0x3, ACTEXT_RT0_R); + writel(0x3, ACTEXT_RT0_W); + + /* + * This may be necessary, but this IP is powered off at this point: + * writel(0x3, ACTEXT_IR0_R); + * writel(0x3, ACTEXT_IR0_W); + * writel(0x3, ACTEXT_IR1_R); + * writel(0x3, ACTEXT_IR1_W); + */ + + if (IS_ENABLED(CONFIG_R8A779G0) && + renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A779G0) { + writel(0x10000, regs_axmm + AXMM_TR3CR); + + if (renesas_get_cpu_rev_integer() >= 2) { + /* WA1 patch for IPL CA76 hang-up issue, REL_TRI_DN-7592 */ + writel(0x38, SI0_RW_MAX); + writel(0x38, SI1_RW_MAX); + } + } + + if (IS_ENABLED(CONFIG_R8A779H0) && + renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A779H0) { + writel(0x0, regs_axmm + AXMM_TR0CR0); + writel(0x0, regs_axmm + AXMM_TR1CR0); + writel(0x0, regs_axmm + AXMM_TR2CR0); + writel(0x0, regs_axmm + AXMM_TR3CR0); + writel(0x70707070, regs_axmm + AXMM_TR0CR1); + writel(0x70707070, regs_axmm + AXMM_TR1CR1); + writel(0x70707070, regs_axmm + AXMM_TR2CR1); + writel(0x70707070, regs_axmm + AXMM_TR3CR1); + writel(0x70707070, regs_axmm + AXMM_TR0CR2); + writel(0x70707070, regs_axmm + AXMM_TR1CR2); + writel(0x70707070, regs_axmm + AXMM_TR2CR2); + writel(0x70707070, regs_axmm + AXMM_TR3CR2); + } + + for (i = 0U; i < ARRAY_SIZE(g_qosbw_tbl); i++) { + writeq(g_qosbw_tbl[i].fix, regs_qos + QOS_FIX_QOS_BANK0 + (i * 8)); + writeq(g_qosbw_tbl[i].fix, regs_qos + QOS_FIX_QOS_BANK1 + (i * 8)); + writeq(g_qosbw_tbl[i].be, regs_qos + QOS_BE_QOS_BANK0 + (i * 8)); + writeq(g_qosbw_tbl[i].be, regs_qos + QOS_BE_QOS_BANK1 + (i * 8)); + } + + for (i = 0U; i < ARRAY_SIZE(g_qoswt_tbl); i++) { + writeq(g_qoswt_tbl[i].fix, regs_qos + QOSWT_FIX_QOS_BANK0 + (i * 8)); + writeq(g_qoswt_tbl[i].fix, regs_qos + QOSWT_FIX_QOS_BANK1 + (i * 8)); + writeq(g_qoswt_tbl[i].be, regs_qos + QOSWT_BE_QOS_BANK0 + (i * 8)); + writeq(g_qoswt_tbl[i].be, regs_qos + QOSWT_BE_QOS_BANK1 + (i * 8)); + } + + /* QoS SRAM setting */ + writel(0x1, regs_qos + QOS_RAEN); + writel(0x2080208, regs_qos + QOSWT_WTREF); + writel(0xD90050F, regs_qos + QOSWT_WTSET0); + writel(0xD90050F, regs_qos + QOSWT_WTSET1); + writel(0x1, regs_qos + QOSWT_WTEN); + writel(0x101, regs_qos + QOS_STATQC); + + return 0; +} + +static int renesas_dbsc5_qos_probe(struct udevice *dev) +{ + int ret; + + /* Setting the register of DBSC4 for QoS initialize */ + ret = dbsc5_qos_dbsc_setting(dev); + if (ret) + return ret; + + return dbsc5_qos_settings_init(dev); +} + +static int renesas_dbsc5_qos_of_to_plat(struct udevice *dev) +{ + struct renesas_dbsc5_qos_priv *priv = dev_get_priv(dev); + + priv->regs = dev_read_addr_ptr(dev); + if (!priv->regs) + return -EINVAL; + + return 0; +} + +U_BOOT_DRIVER(renesas_dbsc5_qos) = { + .name = "dbsc5_qos", + .id = UCLASS_NOP, + .of_to_plat = renesas_dbsc5_qos_of_to_plat, + .probe = renesas_dbsc5_qos_probe, + .priv_auto = sizeof(struct renesas_dbsc5_qos_priv), +}; diff --git a/drivers/ram/renesas/dbsc5/rtvram.c b/drivers/ram/renesas/dbsc5/rtvram.c new file mode 100644 index 00000000000..6c149284bc6 --- /dev/null +++ b/drivers/ram/renesas/dbsc5/rtvram.c @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +#include <asm/io.h> +#include <dm.h> +#include <errno.h> +#include <ram.h> +#include <linux/sizes.h> + +/* RT-VRAM register base address */ +#define RTVRAM_VBUF_CFG 0x6504 +#define RTVRAM_VBUF_CFG_CACHE_MODE_8WAY (1 << 8) +#define RTVRAM_VBUF_CFG_VBUF_SIZE_28M (6 << 0) +#define RTVRAM_EXT_MODE 0x8500 +#define RTVRAM_EXT_MODE_EXT BIT(0) +#define RTVRAM_VBUF_BADDR 0xC580 + +#define RTVRAM_VBUF_NUM 7 + +#define SDRAM_40BIT_ADDR_TOP 0x0400000000ULL +#define RTVRAM_VBUF_AREA_SIZE SZ_4M + +struct renesas_dbsc5_rtvram_priv { + void __iomem *regs; +}; + +static int renesas_dbsc5_rtvram_probe(struct udevice *dev) +{ + struct renesas_dbsc5_rtvram_priv *priv = dev_get_priv(dev); + u64 addr; + int i; + + /* Set each 4MB from the top of SDRAM as the buffer area of RT-VRAM. */ + for (i = 0; i < RTVRAM_VBUF_NUM; i++) { + addr = (SDRAM_40BIT_ADDR_TOP + (RTVRAM_VBUF_AREA_SIZE * i)) >> 16; + writel(lower_32_bits(addr), priv->regs + (RTVRAM_VBUF_BADDR + (4 * i))); + } + + /* Cache Mode: 8-way, VBF size: 28M */ + setbits_le32(priv->regs + RTVRAM_VBUF_CFG, + RTVRAM_VBUF_CFG_CACHE_MODE_8WAY | RTVRAM_VBUF_CFG_VBUF_SIZE_28M); + + /* Change from Compatible Mode to Extended Mode */ + writel(RTVRAM_EXT_MODE_EXT, priv->regs + RTVRAM_EXT_MODE); + + dsb(); + + return 0; +} + +static int renesas_dbsc5_rtvram_of_to_plat(struct udevice *dev) +{ + struct renesas_dbsc5_rtvram_priv *priv = dev_get_priv(dev); + + priv->regs = dev_read_addr_ptr(dev); + if (!priv->regs) + return -EINVAL; + + return 0; +} + +static int renesas_dbsc5_rtvram_get_info(struct udevice *dev, + struct ram_info *info) +{ + struct renesas_dbsc5_rtvram_priv *priv = dev_get_priv(dev); + + info->base = (phys_addr_t)priv->regs; + info->size = 28 * SZ_1M; + + return 0; +} + +static const struct ram_ops renesas_dbsc5_rtvram_ops = { + .get_info = renesas_dbsc5_rtvram_get_info, +}; + +static const struct udevice_id renesas_dbsc5_rtvram_ids[] = { + { .compatible = "renesas,r8a779g0-rtvram" }, + { .compatible = "renesas,r8a779h0-rtvram" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(renesas_dbsc5_rtvram) = { + .name = "rtvram", + .id = UCLASS_RAM, + .of_match = renesas_dbsc5_rtvram_ids, + .of_to_plat = renesas_dbsc5_rtvram_of_to_plat, + .ops = &renesas_dbsc5_rtvram_ops, + .probe = renesas_dbsc5_rtvram_probe, + .priv_auto = sizeof(struct renesas_dbsc5_rtvram_priv), +}; diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig index a49802c1323..2790b168b19 100644 --- a/drivers/remoteproc/Kconfig +++ b/drivers/remoteproc/Kconfig @@ -22,6 +22,14 @@ config K3_SYSTEM_CONTROLLER help Say 'y' here to add support for TI' K3 System Controller. +config REMOTEPROC_RENESAS_APMU + bool "Support for Renesas R-Car Gen4 APMU start of CR52 processor" + select REMOTEPROC + depends on ARCH_RENESAS && RCAR_GEN4 && DM && OF_CONTROL + help + Say 'y' here to add support for Renesas R-Car Gen4 Cortex-A52 + processor via the remoteproc framework. + config REMOTEPROC_SANDBOX bool "Support for Test processor for Sandbox" select REMOTEPROC diff --git a/drivers/remoteproc/Makefile b/drivers/remoteproc/Makefile index 801b0965e4f..3a092b7660e 100644 --- a/drivers/remoteproc/Makefile +++ b/drivers/remoteproc/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_$(XPL_)REMOTEPROC) += rproc-uclass.o rproc-elf-loader.o # Remote proc drivers - Please keep this list alphabetically sorted. obj-$(CONFIG_K3_SYSTEM_CONTROLLER) += k3_system_controller.o +obj-$(CONFIG_REMOTEPROC_RENESAS_APMU) += renesas_apmu.o obj-$(CONFIG_REMOTEPROC_SANDBOX) += sandbox_testproc.o obj-$(CONFIG_REMOTEPROC_STM32_COPRO) += stm32_copro.o obj-$(CONFIG_REMOTEPROC_TI_K3_ARM64) += ti_k3_arm64_rproc.o diff --git a/drivers/remoteproc/renesas_apmu.c b/drivers/remoteproc/renesas_apmu.c new file mode 100644 index 00000000000..32d138e6487 --- /dev/null +++ b/drivers/remoteproc/renesas_apmu.c @@ -0,0 +1,266 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +#include <asm/io.h> +#include <dm.h> +#include <dm/device-internal.h> +#include <dm/lists.h> +#include <errno.h> +#include <hang.h> +#include <linux/iopoll.h> +#include <linux/sizes.h> +#include <malloc.h> +#include <remoteproc.h> + +/* R-Car V4H/V4M contain 3 clusters / 3 cores */ +#define RCAR4_CR52_CORES 3 + +/* Reset Control Register for Cortex-R52 #n */ +#define APMU_CRRSTCTRL(n) (0x304 + ((n) * 0x40)) +#define APMU_CRRSTCTRL_CR52RST BIT(0) + +/* Base Address Register for Cortex-R52 #n */ +#define APMU_CRBARP(n) (0x33c + ((n) * 0x40)) +#define APMU_CRBARP_CR_VLD_BARP BIT(0) +#define APMU_CRBARP_CR_BAREN_VALID BIT(4) +#define APMU_CRBARP_CR_RBAR_MASK 0xfffc0000 +#define APMU_CRBARP_CR_RBAR_ALIGN 0x40000 + +/** + * struct renesas_apmu_rproc_privdata - remote processor private data + * @regs: controller registers + * @core_id: CPU core id + * @trampoline: jump trampoline code + */ +struct renesas_apmu_rproc_privdata { + void __iomem *regs; + ulong core_id; + u32 *trampoline; +}; + +/* + * CRBARP address is aligned to 0x40000 / 256 kiB , this trampoline + * allows arbitrary address alignment at instruction granularity. + */ +static const u32 renesas_apmu_rproc_trampoline[4] = { + 0xe59f0004, /* ldr r0, [pc, #4] */ + 0xe1a0f000, /* mov pc, r0 */ + 0xeafffffe, /* 1: b 1b */ + 0xabcd1234 /* jump target (rewritten on load) */ +}; + +/** + * renesas_apmu_rproc_load() - Load the remote processor + * @dev: corresponding remote processor device + * @addr: Address in memory where image is stored + * @size: Size in bytes of the image + * + * Return: 0 if all went ok, else corresponding -ve error + */ +static int renesas_apmu_rproc_load(struct udevice *dev, ulong addr, ulong size) +{ + struct renesas_apmu_rproc_privdata *priv = dev_get_priv(dev); + u32 trampolineaddr = (u32)(uintptr_t)(priv->trampoline); + + priv->trampoline[3] = addr; + flush_dcache_range(trampolineaddr, + trampolineaddr + + sizeof(renesas_apmu_rproc_trampoline)); + + /* CR52 boot address set */ + writel(trampolineaddr | APMU_CRBARP_CR_VLD_BARP, + priv->regs + APMU_CRBARP(priv->core_id)); + writel(trampolineaddr | APMU_CRBARP_CR_VLD_BARP | APMU_CRBARP_CR_BAREN_VALID, + priv->regs + APMU_CRBARP(priv->core_id)); + + return 0; +} + +/** + * renesas_apmu_rproc_start() - Start the remote processor + * @dev: corresponding remote processor device + * + * Return: 0 if all went ok, else corresponding -ve error + */ +static int renesas_apmu_rproc_start(struct udevice *dev) +{ + struct renesas_apmu_rproc_privdata *priv = dev_get_priv(dev); + + /* Clear APMU_CRRSTCTRL_CR52RST, the only bit in this register */ + writel(0, priv->regs + APMU_CRRSTCTRL(priv->core_id)); + + return 0; +} + +/** + * renesas_apmu_rproc_stop() - Stop the remote processor + * @dev: corresponding remote processor device + * + * Return: 0 if all went ok, else corresponding -ve error + */ +static int renesas_apmu_rproc_stop(struct udevice *dev) +{ + struct renesas_apmu_rproc_privdata *priv = dev_get_priv(dev); + + /* Set APMU_CRRSTCTRL_CR52RST, the only bit in this register */ + writel(APMU_CRRSTCTRL_CR52RST, + priv->regs + APMU_CRRSTCTRL(priv->core_id)); + + return 0; +} + +/** + * renesas_apmu_rproc_reset() - Reset the remote processor + * @dev: corresponding remote processor device + * + * Return: 0 if all went ok, else corresponding -ve error + */ +static int renesas_apmu_rproc_reset(struct udevice *dev) +{ + renesas_apmu_rproc_stop(dev); + renesas_apmu_rproc_start(dev); + return 0; +} + +/** + * renesas_apmu_rproc_is_running() - Is the remote processor running + * @dev: corresponding remote processor device + * + * Return: 0 if the remote processor is running, 1 otherwise + */ +static int renesas_apmu_rproc_is_running(struct udevice *dev) +{ + struct renesas_apmu_rproc_privdata *priv = dev_get_priv(dev); + + return readl(priv->regs + APMU_CRRSTCTRL(priv->core_id)) & + APMU_CRRSTCTRL_CR52RST; +} + +/** + * renesas_apmu_rproc_init() - Initialize the remote processor CRBAR registers + * @dev: corresponding remote processor device + * + * Return: 0 if all went ok, else corresponding -ve error + */ +static int renesas_apmu_rproc_init(struct udevice *dev) +{ + struct renesas_apmu_rproc_privdata *priv = dev_get_priv(dev); + + /* If the core is running already, do nothing. */ + if (renesas_apmu_rproc_is_running(dev)) + return 0; + + /* Clear and invalidate CRBARP content */ + writel(0, priv->regs + APMU_CRBARP(priv->core_id)); + + return 0; +} + +/** + * renesas_apmu_rproc_device_to_virt() - Convert device address to virtual address + * @dev: corresponding remote processor device + * @da: device address + * @size: Size of the memory region @da is pointing to + * + * Return: converted virtual address + */ +static void *renesas_apmu_rproc_device_to_virt(struct udevice *dev, ulong da, + ulong size) +{ + /* + * The Cortex R52 and A76 share the same address space, + * this operation is a no-op. + */ + return (void *)da; +} + +static const struct dm_rproc_ops renesas_apmu_rproc_ops = { + .init = renesas_apmu_rproc_init, + .load = renesas_apmu_rproc_load, + .start = renesas_apmu_rproc_start, + .stop = renesas_apmu_rproc_stop, + .reset = renesas_apmu_rproc_reset, + .is_running = renesas_apmu_rproc_is_running, + .device_to_virt = renesas_apmu_rproc_device_to_virt, +}; + +/** + * renesas_apmu_rproc_of_to_plat() - Convert OF data to platform data + * @dev: corresponding remote processor device + * + * Return: 0 if all went ok, else corresponding -ve error + */ +static int renesas_apmu_rproc_of_to_plat(struct udevice *dev) +{ + struct renesas_apmu_rproc_privdata *priv = dev_get_priv(dev); + + priv->core_id = dev_get_driver_data(dev); + + priv->regs = dev_read_addr_ptr(dev); + if (!priv->regs) + return -EINVAL; + + priv->trampoline = memalign(APMU_CRBARP_CR_RBAR_ALIGN, + sizeof(renesas_apmu_rproc_trampoline)); + if (!priv->trampoline) + return -ENOMEM; + + memcpy(priv->trampoline, renesas_apmu_rproc_trampoline, + sizeof(renesas_apmu_rproc_trampoline)); + + return 0; +} + +U_BOOT_DRIVER(renesas_apmu_cr52) = { + .name = "rcar-apmu-cr52", + .id = UCLASS_REMOTEPROC, + .ops = &renesas_apmu_rproc_ops, + .of_to_plat = renesas_apmu_rproc_of_to_plat, + .priv_auto = sizeof(struct renesas_apmu_rproc_privdata), +}; + +/** + * renesas_apmu_rproc_bind() - Bind rproc driver to each core control + * @dev: corresponding remote processor parent device + * + * Return: 0 if all went ok, else corresponding -ve error + */ +static int renesas_apmu_rproc_bind(struct udevice *parent) +{ + const ulong cr52cores = RCAR4_CR52_CORES; + ofnode pnode = dev_ofnode(parent); + struct udevice *cdev; + struct driver *cdrv; + char name[32]; + ulong i; + int ret; + + cdrv = lists_driver_lookup_name("rcar-apmu-cr52"); + if (!cdrv) + return -ENOENT; + + for (i = 0; i < cr52cores; i++) { + snprintf(name, sizeof(name), "rcar-apmu-cr52.%ld", i); + ret = device_bind_with_driver_data(parent, cdrv, strdup(name), + i, pnode, &cdev); + if (ret) + return ret; + } + + return 0; +} + +static const struct udevice_id renesas_apmu_rproc_ids[] = { + { .compatible = "renesas,r8a779g0-cr52" }, + { .compatible = "renesas,r8a779h0-cr52" }, + { } +}; + +U_BOOT_DRIVER(renesas_apmu_rproc) = { + .name = "rcar-apmu-rproc", + .of_match = renesas_apmu_rproc_ids, + .id = UCLASS_NOP, + .bind = renesas_apmu_rproc_bind, +}; diff --git a/drivers/remoteproc/rproc-elf-loader.c b/drivers/remoteproc/rproc-elf-loader.c index ab1836b3f07..0b3941b7798 100644 --- a/drivers/remoteproc/rproc-elf-loader.c +++ b/drivers/remoteproc/rproc-elf-loader.c @@ -6,6 +6,7 @@ #include <dm.h> #include <elf.h> #include <log.h> +#include <mapmem.h> #include <remoteproc.h> #include <asm/cache.h> #include <dm/device_compat.h> @@ -180,6 +181,7 @@ int rproc_elf32_load_image(struct udevice *dev, unsigned long addr, ulong size) for (i = 0; i < ehdr->e_phnum; i++, phdr++) { void *dst = (void *)(uintptr_t)phdr->p_paddr; void *src = (void *)addr + phdr->p_offset; + ulong dst_addr; if (phdr->p_type != PT_LOAD) continue; @@ -195,10 +197,11 @@ int rproc_elf32_load_image(struct udevice *dev, unsigned long addr, ulong size) if (phdr->p_filesz != phdr->p_memsz) memset(dst + phdr->p_filesz, 0x00, phdr->p_memsz - phdr->p_filesz); - flush_cache(rounddown((unsigned long)dst, ARCH_DMA_MINALIGN), - roundup((unsigned long)dst + phdr->p_filesz, + dst_addr = map_to_sysmem(dst); + flush_cache(rounddown(dst_addr, ARCH_DMA_MINALIGN), + roundup(dst_addr + phdr->p_filesz, ARCH_DMA_MINALIGN) - - rounddown((unsigned long)dst, ARCH_DMA_MINALIGN)); + rounddown(dst_addr, ARCH_DMA_MINALIGN)); } return 0; @@ -377,6 +380,7 @@ int rproc_elf32_load_rsc_table(struct udevice *dev, ulong fw_addr, const struct dm_rproc_ops *ops; Elf32_Shdr *shdr; void *src, *dst; + ulong dst_addr; shdr = rproc_elf32_find_rsc_table(dev, fw_addr, fw_size); if (!shdr) @@ -398,10 +402,10 @@ int rproc_elf32_load_rsc_table(struct udevice *dev, ulong fw_addr, (ulong)dst, *rsc_size); memcpy(dst, src, *rsc_size); - flush_cache(rounddown((unsigned long)dst, ARCH_DMA_MINALIGN), - roundup((unsigned long)dst + *rsc_size, - ARCH_DMA_MINALIGN) - - rounddown((unsigned long)dst, ARCH_DMA_MINALIGN)); + dst_addr = map_to_sysmem(dst); + flush_cache(rounddown(dst_addr, ARCH_DMA_MINALIGN), + roundup(dst_addr + *rsc_size, ARCH_DMA_MINALIGN) - + rounddown(dst_addr, ARCH_DMA_MINALIGN)); return 0; } diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 3f6860f3916..c3b884b6d00 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -12,7 +12,6 @@ #include <log.h> #include <ns16550.h> #include <reset.h> -#include <serial.h> #include <spl.h> #include <watchdog.h> #include <asm/global_data.h> @@ -158,7 +157,7 @@ static inline int serial_in_dynamic(struct ns16550_plat *plat, u8 *addr) #endif /* CONFIG_NS16550_DYNAMIC */ -static void ns16550_writeb(struct ns16550 *port, int offset, int value) +void ns16550_writeb(struct ns16550 *port, int offset, int value) { struct ns16550_plat *plat = port->plat; unsigned char *addr; @@ -193,13 +192,6 @@ static u32 ns16550_getfcr(struct ns16550 *port) return plat->fcr; } -/* We can clean these up once everything is moved to driver model */ -#define serial_out(value, addr) \ - ns16550_writeb(com_port, \ - (unsigned char *)addr - (unsigned char *)com_port, value) -#define serial_in(addr) \ - ns16550_readb(com_port, \ - (unsigned char *)addr - (unsigned char *)com_port) #else static u32 ns16550_getfcr(struct ns16550 *port) { @@ -214,7 +206,7 @@ int ns16550_calc_divisor(struct ns16550 *port, int clock, int baudrate) return DIV_ROUND_CLOSEST(clock, mode_x_div * baudrate); } -static void ns16550_setbrg(struct ns16550 *com_port, int baud_divisor) +void ns16550_setbrg(struct ns16550 *com_port, int baud_divisor) { /* to keep serial format, read lcr before writing BKSE */ int lcr_val = serial_in(&com_port->lcr) & ~UART_LCR_BKSE; @@ -380,7 +372,7 @@ DEBUG_UART_FUNCS #endif #if CONFIG_IS_ENABLED(DM_SERIAL) -static int ns16550_serial_putc(struct udevice *dev, const char ch) +int ns16550_serial_putc(struct udevice *dev, const char ch) { struct ns16550 *const com_port = dev_get_priv(dev); @@ -400,7 +392,7 @@ static int ns16550_serial_putc(struct udevice *dev, const char ch) return 0; } -static int ns16550_serial_pending(struct udevice *dev, bool input) +int ns16550_serial_pending(struct udevice *dev, bool input) { struct ns16550 *const com_port = dev_get_priv(dev); @@ -410,7 +402,7 @@ static int ns16550_serial_pending(struct udevice *dev, bool input) return (serial_in(&com_port->lsr) & UART_LSR_THRE) ? 0 : 1; } -static int ns16550_serial_getc(struct udevice *dev) +int ns16550_serial_getc(struct udevice *dev) { struct ns16550 *const com_port = dev_get_priv(dev); @@ -420,7 +412,7 @@ static int ns16550_serial_getc(struct udevice *dev) return serial_in(&com_port->rbr); } -static int ns16550_serial_setbrg(struct udevice *dev, int baudrate) +int ns16550_serial_setbrg(struct udevice *dev, int baudrate) { struct ns16550 *const com_port = dev_get_priv(dev); struct ns16550_plat *plat = com_port->plat; @@ -433,7 +425,7 @@ static int ns16550_serial_setbrg(struct udevice *dev, int baudrate) return 0; } -static int ns16550_serial_setconfig(struct udevice *dev, uint serial_config) +int ns16550_serial_setconfig(struct udevice *dev, uint serial_config) { struct ns16550 *const com_port = dev_get_priv(dev); int lcr_val = UART_LCR_WLS_8; @@ -466,8 +458,7 @@ static int ns16550_serial_setconfig(struct udevice *dev, uint serial_config) return 0; } -static int ns16550_serial_getinfo(struct udevice *dev, - struct serial_device_info *info) +int ns16550_serial_getinfo(struct udevice *dev, struct serial_device_info *info) { struct ns16550 *const com_port = dev_get_priv(dev); struct ns16550_plat *plat = com_port->plat; diff --git a/drivers/serial/serial_omap.c b/drivers/serial/serial_omap.c index 94672655c28..224d9cbf29d 100644 --- a/drivers/serial/serial_omap.c +++ b/drivers/serial/serial_omap.c @@ -15,6 +15,12 @@ #include <clk.h> #include <linux/err.h> +/* + * These are the definitions for the MDR1 register + */ +#define UART_OMAP_MDR1_16X_MODE 0x00 /* UART 16x mode */ +#define UART_OMAP_MDR1_13X_MODE 0x03 /* UART 13x mode */ + #ifndef CFG_SYS_NS16550_CLK #define CFG_SYS_NS16550_CLK 0 #endif @@ -151,6 +157,54 @@ static const struct udevice_id omap_serial_ids[] = { }; #endif /* OF_REAL */ +static int omap_serial_calc_divisor(struct ns16550 *com_port, int clock, int baudrate) +{ + unsigned int div_13, div_16; + unsigned int abs_d13, abs_d16; + /* + * The below logic sets the MDR1 register based on clock and baudrate. + */ + div_13 = DIV_ROUND_CLOSEST(clock, 13 * baudrate); + div_16 = DIV_ROUND_CLOSEST(clock, 16 * baudrate); + + if (!div_13) + div_13 = 1; + if (!div_16) + div_16 = 1; + + abs_d13 = abs(baudrate - clock / 13 / div_13); + abs_d16 = abs(baudrate - clock / 16 / div_16); + + if (abs_d13 >= abs_d16) + serial_out(UART_OMAP_MDR1_16X_MODE, &com_port->mdr1); + else + serial_out(UART_OMAP_MDR1_13X_MODE, &com_port->mdr1); + + return abs_d13 >= abs_d16 ? div_16 : div_13; +} + +static int omap_serial_setbrg(struct udevice *dev, int baudrate) +{ + struct ns16550 *const com_port = dev_get_priv(dev); + struct ns16550_plat *plat = com_port->plat; + int clock_divisor; + + clock_divisor = omap_serial_calc_divisor(com_port, plat->clock, baudrate); + + ns16550_setbrg(com_port, clock_divisor); + + return 0; +} + +const struct dm_serial_ops omap_serial_ops = { + .putc = ns16550_serial_putc, + .pending = ns16550_serial_pending, + .getc = ns16550_serial_getc, + .setbrg = omap_serial_setbrg, + .setconfig = ns16550_serial_setconfig, + .getinfo = ns16550_serial_getinfo, +}; + #if CONFIG_IS_ENABLED(SERIAL_PRESENT) U_BOOT_DRIVER(omap_serial) = { .name = "omap_serial", @@ -162,7 +216,7 @@ U_BOOT_DRIVER(omap_serial) = { #endif .priv_auto = sizeof(struct ns16550), .probe = ns16550_serial_probe, - .ops = &ns16550_serial_ops, + .ops = &omap_serial_ops, #if !CONFIG_IS_ENABLED(OF_CONTROL) .flags = DM_FLAG_PRE_RELOC, #endif diff --git a/drivers/spi/cadence_ospi_versal.c b/drivers/spi/cadence_ospi_versal.c index 222f828f54e..dcf28c75596 100644 --- a/drivers/spi/cadence_ospi_versal.c +++ b/drivers/spi/cadence_ospi_versal.c @@ -125,49 +125,8 @@ int cadence_qspi_apb_wait_for_dma_cmplt(struct cadence_spi_priv *priv) return 0; } -#if defined(CONFIG_DM_GPIO) -int cadence_qspi_versal_flash_reset(struct udevice *dev) -{ - struct gpio_desc gpio; - u32 reset_gpio; - int ret; - - /* request gpio and set direction as output set to 1 */ - ret = gpio_request_by_name(dev, "reset-gpios", 0, &gpio, - GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); - if (ret) { - printf("%s: unable to reset ospi flash device", __func__); - return ret; - } - - reset_gpio = PMIO_NODE_ID_BASE + gpio.offset; - - /* Request for pin */ - xilinx_pm_request(PM_PINCTRL_REQUEST, reset_gpio, 0, 0, 0, NULL); - - /* Enable hysteresis in cmos receiver */ - xilinx_pm_request(PM_PINCTRL_CONFIG_PARAM_SET, reset_gpio, - PM_PINCTRL_CONFIG_SCHMITT_CMOS, - PM_PINCTRL_INPUT_TYPE_SCHMITT, 0, NULL); - - /* Disable Tri-state */ - xilinx_pm_request(PM_PINCTRL_CONFIG_PARAM_SET, reset_gpio, - PM_PINCTRL_CONFIG_TRI_STATE, - PM_PINCTRL_TRI_STATE_DISABLE, 0, NULL); - udelay(1); - - /* Set value 0 to pin */ - dm_gpio_set_value(&gpio, 0); - udelay(1); - - /* Set value 1 to pin */ - dm_gpio_set_value(&gpio, 1); - udelay(1); - - return 0; -} -#else -int cadence_qspi_versal_flash_reset(struct udevice *dev) +#if !CONFIG_IS_ENABLED(DM_GPIO) +int cadence_qspi_flash_reset(struct udevice *dev) { /* CRP WPROT */ writel(0, WPROT_CRP); diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index 331a46d88f7..623904ecdad 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -33,7 +33,7 @@ __weak int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv, return 0; } -__weak int cadence_qspi_versal_flash_reset(struct udevice *dev) +__weak int cadence_qspi_flash_reset(struct udevice *dev) { return 0; } @@ -252,7 +252,9 @@ static int cadence_spi_probe(struct udevice *bus) priv->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC, priv->ref_clk_hz); /* Reset ospi flash device */ - return cadence_qspi_versal_flash_reset(bus); + return cadence_qspi_flash_reset(bus); + + return 0; } static int cadence_spi_remove(struct udevice *dev) diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c index 9ab39a188b2..2c9b0ada87b 100644 --- a/drivers/spi/mxc_spi.c +++ b/drivers/spi/mxc_spi.c @@ -115,6 +115,9 @@ struct mxc_spi_slave { #if defined(MXC_ECSPI) u32 cfg_reg; #endif +#if CONFIG_IS_ENABLED(CLK) + struct clk clk; +#endif int gpio; int ss_pol; unsigned int max_hz; @@ -214,7 +217,11 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs) #ifdef MXC_ECSPI static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs) { +#if CONFIG_IS_ENABLED(CLK) + u32 clk_src = clk_get_rate(&mxcs->clk); +#else u32 clk_src = mxc_get_clock(MXC_CSPI_CLK); +#endif s32 reg_ctrl, reg_config; u32 ss_pol = 0, sclkpol = 0, sclkpha = 0, sclkctl = 0; u32 pre_div = 0, post_div = 0; @@ -599,14 +606,13 @@ static int mxc_spi_probe(struct udevice *bus) return -ENODEV; #if CONFIG_IS_ENABLED(CLK) - struct clk clk; - ret = clk_get_by_index(bus, 0, &clk); + ret = clk_get_by_index(bus, 0, &mxcs->clk); if (ret) return ret; - clk_enable(&clk); + clk_enable(&mxcs->clk); - mxcs->max_hz = clk_get_rate(&clk); + mxcs->max_hz = clk_get_rate(&mxcs->clk); #else int node = dev_of_offset(bus); const void *blob = gd->fdt_blob; diff --git a/drivers/sysinfo/gazerbeam.h b/drivers/sysinfo/gazerbeam.h index 6bf3c0098d1..047f365436f 100644 --- a/drivers/sysinfo/gazerbeam.h +++ b/drivers/sysinfo/gazerbeam.h @@ -8,8 +8,8 @@ #include <sysinfo.h> enum { - BOARD_HWVERSION = SYSINFO_ID_BOARD_MODEL, - BOARD_MULTICHANNEL = SYSINFO_ID_USER, + BOARD_HWVERSION = SYSID_BOARD_MODEL, + BOARD_MULTICHANNEL = SYSID_USER, BOARD_VARIANT }; diff --git a/drivers/sysinfo/gpio.c b/drivers/sysinfo/gpio.c index aaca318419b..66d2a913087 100644 --- a/drivers/sysinfo/gpio.c +++ b/drivers/sysinfo/gpio.c @@ -38,7 +38,7 @@ static int sysinfo_gpio_get_int(struct udevice *dev, int id, int *val) struct sysinfo_gpio_priv *priv = dev_get_priv(dev); switch (id) { - case SYSINFO_ID_BOARD_MODEL: + case SYSID_BOARD_MODEL: *val = priv->revision; return 0; default: @@ -51,7 +51,7 @@ static int sysinfo_gpio_get_str(struct udevice *dev, int id, size_t size, char * struct sysinfo_gpio_priv *priv = dev_get_priv(dev); switch (id) { - case SYSINFO_ID_BOARD_MODEL: { + case SYSID_BOARD_MODEL: { const char *name = NULL; int i, ret; u32 revision; diff --git a/drivers/sysinfo/rcar3.c b/drivers/sysinfo/rcar3.c index 37e2cccd9af..2994df9ab1c 100644 --- a/drivers/sysinfo/rcar3.c +++ b/drivers/sysinfo/rcar3.c @@ -46,7 +46,7 @@ static int sysinfo_rcar_get_str(struct udevice *dev, int id, size_t size, char * struct sysinfo_rcar_priv *priv = dev_get_priv(dev); switch (id) { - case SYSINFO_ID_BOARD_MODEL: + case SYSID_BOARD_MODEL: strncpy(val, priv->boardmodel, size); val[size - 1] = '\0'; return 0; diff --git a/drivers/sysinfo/sandbox.h b/drivers/sysinfo/sandbox.h index d9c5804c26a..a7cbac0ce18 100644 --- a/drivers/sysinfo/sandbox.h +++ b/drivers/sysinfo/sandbox.h @@ -5,7 +5,7 @@ */ enum { - BOOL_CALLED_DETECT = SYSINFO_ID_USER, + BOOL_CALLED_DETECT = SYSID_USER, INT_TEST1, INT_TEST2, STR_VACATIONSPOT, diff --git a/drivers/timer/mpc83xx_timer.c b/drivers/timer/mpc83xx_timer.c index 9da74479aaa..f92009e4ccc 100644 --- a/drivers/timer/mpc83xx_timer.c +++ b/drivers/timer/mpc83xx_timer.c @@ -206,7 +206,7 @@ static u64 mpc83xx_timer_get_count(struct udevice *dev) tbl = mftb(); } while (tbu != mftbu()); - return (tbu * 0x10000ULL) + tbl; + return (uint64_t)tbu << 32 | tbl; } static int mpc83xx_timer_probe(struct udevice *dev) diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c index 2ab41cbae45..55e62b35c61 100644 --- a/drivers/usb/dwc3/dwc3-generic.c +++ b/drivers/usb/dwc3/dwc3-generic.c @@ -51,7 +51,8 @@ struct dwc3_generic_host_priv { }; static int dwc3_generic_probe(struct udevice *dev, - struct dwc3_generic_priv *priv) + struct dwc3_generic_priv *priv, + enum usb_dr_mode mode) { int rc; struct dwc3_generic_plat *plat = dev_get_plat(dev); @@ -62,7 +63,7 @@ static int dwc3_generic_probe(struct udevice *dev, dwc3->dev = dev; dwc3->maximum_speed = plat->maximum_speed; - dwc3->dr_mode = plat->dr_mode; + dwc3->dr_mode = mode; #if CONFIG_IS_ENABLED(OF_CONTROL) dwc3_of_parse(dwc3); @@ -197,7 +198,7 @@ static int dwc3_generic_peripheral_probe(struct udevice *dev) { struct dwc3_generic_priv *priv = dev_get_priv(dev); - return dwc3_generic_probe(dev, priv); + return dwc3_generic_probe(dev, priv, USB_DR_MODE_PERIPHERAL); } static int dwc3_generic_peripheral_remove(struct udevice *dev) @@ -241,7 +242,7 @@ static int dwc3_generic_host_probe(struct udevice *dev) struct dwc3_generic_host_priv *priv = dev_get_priv(dev); int rc; - rc = dwc3_generic_probe(dev, &priv->gen_priv); + rc = dwc3_generic_probe(dev, &priv->gen_priv, USB_DR_MODE_HOST); if (rc) return rc; diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 0e45f0a0922..b39b2546e5c 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -351,6 +351,13 @@ config WDT_SBSA In the single stage mode, when the timeout is reached, your system will be reset by WS1. The first signal (WS0) is ignored. +config WDT_SIEMENS_PMIC + bool "Enable PMIC Watchdog Timer support for Siemens platforms" + depends on ARCH_IMX8 && WDT + help + Select this to enable the PMIC watchdog driver controlled via + IMX8 SCU API found on Siemens platforms. + config WDT_SL28CPLD bool "sl28cpld watchdog timer support" depends on WDT && SL28CPLD diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 0b107c008f7..9b6b1a8e8ad 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -45,6 +45,7 @@ obj-$(CONFIG_WDT_OCTEONTX) += octeontx_wdt.o obj-$(CONFIG_WDT_OMAP3) += omap_wdt.o obj-$(CONFIG_WDT_SBSA) += sbsa_gwdt.o obj-$(CONFIG_WDT_K3_RTI) += rti_wdt.o +obj-$(CONFIG_WDT_SIEMENS_PMIC) += siemens_pmic_wdt.o obj-$(CONFIG_WDT_SL28CPLD) += sl28cpld-wdt.o obj-$(CONFIG_WDT_SP805) += sp805_wdt.o obj-$(CONFIG_WDT_STARFIVE) += starfive_wdt.o diff --git a/drivers/watchdog/siemens_pmic_wdt.c b/drivers/watchdog/siemens_pmic_wdt.c new file mode 100644 index 00000000000..87e817bb5b2 --- /dev/null +++ b/drivers/watchdog/siemens_pmic_wdt.c @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Driver for a PMIC watchdog timer controlled via Siemens SCU firmware + * extensions. Only useful on some Siemens i.MX8-based platforms as + * special NXP SCFW is needed which provides the needed SCU API. + * + * Copyright (C) 2024 Siemens AG + */ + +#include <dm.h> +#include <wdt.h> +#include <firmware/imx/sci/sci.h> + +/* watchdog commands */ +#define CMD_START_WDT 0x55 +#define CMD_STOP_WDT 0x45 +#define CMD_PING_WDT 0x35 + +static int scu_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags) +{ + /* start external watchdog via Timer API */ + return sc_timer_control_siemens_pmic_wdog(-1, CMD_START_WDT); +} + +static int scu_wdt_stop(struct udevice *dev) +{ + /* stop external watchdog via Timer API */ + return sc_timer_control_siemens_pmic_wdog(-1, CMD_STOP_WDT); +} + +static int scu_wdt_reset(struct udevice *dev) +{ + return sc_timer_control_siemens_pmic_wdog(-1, CMD_PING_WDT); +} + +static int scu_wdt_probe(struct udevice *dev) +{ + debug("%s(dev=%p)\n", __func__, dev); + return 0; +} + +static const struct wdt_ops scu_wdt_ops = { + .reset = scu_wdt_reset, + .start = scu_wdt_start, + .stop = scu_wdt_stop, +}; + +static const struct udevice_id scu_wdt_ids[] = { + { .compatible = "siemens,scu-wdt" }, + { } +}; + +U_BOOT_DRIVER(scu_wdt) = { + .name = "scu_wdt", + .id = UCLASS_WDT, + .of_match = scu_wdt_ids, + .probe = scu_wdt_probe, + .ops = &scu_wdt_ops, +}; |