diff options
Diffstat (limited to 'drivers')
43 files changed, 5692 insertions, 304 deletions
diff --git a/drivers/clk/imx/clk-imx8qm.c b/drivers/clk/imx/clk-imx8qm.c index 62fed7e3e32..466d71786cf 100644 --- a/drivers/clk/imx/clk-imx8qm.c +++ b/drivers/clk/imx/clk-imx8qm.c @@ -48,6 +48,8 @@ ulong imx8_clk_get_rate(struct clk *clk) debug("%s(#%lu)\n", __func__, clk->id); switch (clk->id) { + case IMX8QM_CLK_DUMMY: + return 0; case IMX8QM_A53_DIV: resource = SC_R_A53; pm_clk = SC_PM_CLK_CPU; @@ -264,6 +266,8 @@ int __imx8_clk_enable(struct clk *clk, bool enable) debug("%s(#%lu)\n", __func__, clk->id); switch (clk->id) { + case IMX8QM_CLK_DUMMY: + return 0; case IMX8QM_I2C0_IPG_CLK: case IMX8QM_I2C0_CLK: case IMX8QM_I2C0_DIV: diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c index 18bdc08971b..79098623bc8 100644 --- a/drivers/clk/imx/clk-imx8qxp.c +++ b/drivers/clk/imx/clk-imx8qxp.c @@ -51,6 +51,8 @@ ulong imx8_clk_get_rate(struct clk *clk) debug("%s(#%lu)\n", __func__, clk->id); switch (clk->id) { + case IMX8QXP_CLK_DUMMY: + return 0; case IMX8QXP_A35_DIV: resource = SC_R_A35; pm_clk = SC_PM_CLK_CPU; @@ -248,6 +250,8 @@ int __imx8_clk_enable(struct clk *clk, bool enable) debug("%s(#%lu)\n", __func__, clk->id); switch (clk->id) { + case IMX8QXP_CLK_DUMMY: + return 0; case IMX8QXP_I2C0_CLK: case IMX8QXP_I2C0_IPG_CLK: resource = SC_R_I2C_0; diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c index 6c0a8c0cbe4..51262befaff 100644 --- a/drivers/cpu/imx8_cpu.c +++ b/drivers/cpu/imx8_cpu.c @@ -20,10 +20,11 @@ DECLARE_GLOBAL_DATA_PTR; +#define IMX_REV_LEN 4 struct cpu_imx_plat { const char *name; - const char *rev; const char *type; + char rev[IMX_REV_LEN]; u32 cpu_rsrc; u32 cpurev; u32 freq_mhz; @@ -69,28 +70,29 @@ static const char *get_imx_type_str(u32 imxtype) } } -static const char *get_imx_rev_str(u32 rev) +static void get_imx_rev_str(struct cpu_imx_plat *plat, u32 rev) { - static char revision[4]; - if (IS_ENABLED(CONFIG_IMX8)) { switch (rev) { case CHIP_REV_A: - return "A"; + plat->rev[0] = 'A'; + break; case CHIP_REV_B: - return "B"; + plat->rev[0] = 'B'; + break; case CHIP_REV_C: - return "C"; + plat->rev[0] = 'C'; + break; default: - return "?"; + plat->rev[0] = '?'; + break; } + plat->rev[1] = '\0'; } else { - revision[0] = '1' + (((rev & 0xf0) - CHIP_REV_1_0) >> 4); - revision[1] = '.'; - revision[2] = '0' + (rev & 0xf); - revision[3] = '\0'; - - return revision; + plat->rev[0] = '1' + (((rev & 0xf0) - CHIP_REV_1_0) >> 4); + plat->rev[1] = '.'; + plat->rev[2] = '0' + (rev & 0xf); + plat->rev[3] = '\0'; } } @@ -318,7 +320,7 @@ static int imx_cpu_probe(struct udevice *dev) set_core_data(dev); cpurev = get_cpu_rev(); plat->cpurev = cpurev; - plat->rev = get_imx_rev_str(cpurev & 0xFFF); + get_imx_rev_str(plat, cpurev & 0xFFF); plat->type = get_imx_type_str((cpurev & 0x1FF000) >> 12); plat->freq_mhz = imx_get_cpu_rate(dev) / 1000000; plat->mpidr = dev_read_addr(dev); diff --git a/drivers/dfu/Kconfig b/drivers/dfu/Kconfig index aadd7e8cf7f..604386bb734 100644 --- a/drivers/dfu/Kconfig +++ b/drivers/dfu/Kconfig @@ -20,6 +20,7 @@ config DFU_WRITE_ALT config DFU_TFTP bool "DFU via TFTP" depends on NETDEVICES + depends on !NET_LWIP select UPDATE_COMMON select DFU_OVER_TFTP help diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c index e23d09e6b81..dac4023ccfd 100644 --- a/drivers/dma/ti/k3-udma.c +++ b/drivers/dma/ti/k3-udma.c @@ -1700,141 +1700,6 @@ static int setup_resources(struct udma_dev *ud) return ch_count; } -static int udma_probe(struct udevice *dev) -{ - struct dma_dev_priv *uc_priv = dev_get_uclass_priv(dev); - struct udma_dev *ud = dev_get_priv(dev); - int i, ret; - struct udevice *tmp; - struct udevice *tisci_dev = NULL; - struct udma_tisci_rm *tisci_rm = &ud->tisci_rm; - ofnode navss_ofnode = ofnode_get_parent(dev_ofnode(dev)); - - ud->match_data = (void *)dev_get_driver_data(dev); - ret = udma_get_mmrs(dev); - if (ret) - return ret; - - ud->psil_base = ud->match_data->psil_base; - - ret = uclass_get_device_by_phandle(UCLASS_FIRMWARE, dev, - "ti,sci", &tisci_dev); - if (ret) { - debug("Failed to get TISCI phandle (%d)\n", ret); - tisci_rm->tisci = NULL; - return -EINVAL; - } - tisci_rm->tisci = (struct ti_sci_handle *) - (ti_sci_get_handle_from_sysfw(tisci_dev)); - - tisci_rm->tisci_dev_id = -1; - ret = dev_read_u32(dev, "ti,sci-dev-id", &tisci_rm->tisci_dev_id); - if (ret) { - dev_err(dev, "ti,sci-dev-id read failure %d\n", ret); - return ret; - } - - tisci_rm->tisci_navss_dev_id = -1; - ret = ofnode_read_u32(navss_ofnode, "ti,sci-dev-id", - &tisci_rm->tisci_navss_dev_id); - if (ret) { - dev_err(dev, "navss sci-dev-id read failure %d\n", ret); - return ret; - } - - tisci_rm->tisci_udmap_ops = &tisci_rm->tisci->ops.rm_udmap_ops; - tisci_rm->tisci_psil_ops = &tisci_rm->tisci->ops.rm_psil_ops; - - if (ud->match_data->type == DMA_TYPE_UDMA) { - ret = uclass_get_device_by_phandle(UCLASS_MISC, dev, - "ti,ringacc", &tmp); - ud->ringacc = dev_get_priv(tmp); - } else { - struct k3_ringacc_init_data ring_init_data; - - ring_init_data.tisci = ud->tisci_rm.tisci; - ring_init_data.tisci_dev_id = ud->tisci_rm.tisci_dev_id; - if (ud->match_data->type == DMA_TYPE_BCDMA) { - ring_init_data.num_rings = ud->bchan_cnt + - ud->tchan_cnt + - ud->rchan_cnt; - } else { - ring_init_data.num_rings = ud->rflow_cnt + - ud->tflow_cnt; - } - - ud->ringacc = k3_ringacc_dmarings_init(dev, &ring_init_data); - } - if (IS_ERR(ud->ringacc)) - return PTR_ERR(ud->ringacc); - - ud->dev = dev; - ret = setup_resources(ud); - if (ret < 0) - return ret; - - ud->ch_count = ret; - - for (i = 0; i < ud->bchan_cnt; i++) { - struct udma_bchan *bchan = &ud->bchans[i]; - - bchan->id = i; - bchan->reg_rt = ud->mmrs[MMR_BCHANRT] + i * 0x1000; - } - - for (i = 0; i < ud->tchan_cnt; i++) { - struct udma_tchan *tchan = &ud->tchans[i]; - - tchan->id = i; - tchan->reg_chan = ud->mmrs[MMR_TCHAN] + UDMA_CH_100(i); - tchan->reg_rt = ud->mmrs[MMR_TCHANRT] + UDMA_CH_1000(i); - } - - for (i = 0; i < ud->rchan_cnt; i++) { - struct udma_rchan *rchan = &ud->rchans[i]; - - rchan->id = i; - rchan->reg_chan = ud->mmrs[MMR_RCHAN] + UDMA_CH_100(i); - rchan->reg_rt = ud->mmrs[MMR_RCHANRT] + UDMA_CH_1000(i); - } - - for (i = 0; i < ud->rflow_cnt; i++) { - struct udma_rflow *rflow = &ud->rflows[i]; - - rflow->id = i; - rflow->reg_rflow = ud->mmrs[MMR_RFLOW] + UDMA_CH_40(i); - } - - for (i = 0; i < ud->ch_count; i++) { - struct udma_chan *uc = &ud->channels[i]; - - uc->ud = ud; - uc->id = i; - uc->config.remote_thread_id = -1; - uc->bchan = NULL; - uc->tchan = NULL; - uc->rchan = NULL; - uc->config.mapped_channel_id = -1; - uc->config.default_flow_id = -1; - uc->config.dir = DMA_MEM_TO_MEM; - sprintf(uc->name, "UDMA chan%d\n", i); - if (!i) - uc->in_use = true; - } - - pr_debug("%s(rev: 0x%08x) CAP0-3: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n", - dev->name, - udma_read(ud->mmrs[MMR_GCFG], 0), - udma_read(ud->mmrs[MMR_GCFG], 0x20), - udma_read(ud->mmrs[MMR_GCFG], 0x24), - udma_read(ud->mmrs[MMR_GCFG], 0x28), - udma_read(ud->mmrs[MMR_GCFG], 0x2c)); - - uc_priv->supported = DMA_SUPPORTS_MEM_TO_MEM | DMA_SUPPORTS_MEM_TO_DEV; - - return 0; -} - static int udma_push_to_ring(struct k3_nav_ring *ring, void *elem) { u64 addr = 0; @@ -2325,37 +2190,12 @@ static int udma_transfer(struct udevice *dev, int direction, /* Channel0 is reserved for memcpy */ struct udma_chan *uc = &ud->channels[0]; dma_addr_t paddr = 0; - int ret; - - switch (ud->match_data->type) { - case DMA_TYPE_UDMA: - ret = udma_alloc_chan_resources(uc); - break; - case DMA_TYPE_BCDMA: - ret = bcdma_alloc_chan_resources(uc); - break; - default: - return -EINVAL; - }; - if (ret) - return ret; udma_prep_dma_memcpy(uc, dst, src, len); udma_start(uc); udma_poll_completion(uc, &paddr); udma_stop(uc); - switch (ud->match_data->type) { - case DMA_TYPE_UDMA: - udma_free_chan_resources(uc); - break; - case DMA_TYPE_BCDMA: - bcdma_free_bchan_resources(uc); - break; - default: - return -EINVAL; - }; - return 0; } @@ -2717,6 +2557,177 @@ static int udma_get_cfg(struct dma *dma, u32 id, void **data) return -EINVAL; } +static int udma_probe(struct udevice *dev) +{ + struct dma_dev_priv *uc_priv = dev_get_uclass_priv(dev); + struct udma_dev *ud = dev_get_priv(dev); + int i, ret; + struct udevice *tmp; + struct udevice *tisci_dev = NULL; + struct udma_tisci_rm *tisci_rm = &ud->tisci_rm; + struct udma_chan *uc; + ofnode navss_ofnode = ofnode_get_parent(dev_ofnode(dev)); + + ud->match_data = (void *)dev_get_driver_data(dev); + ret = udma_get_mmrs(dev); + if (ret) + return ret; + + ud->psil_base = ud->match_data->psil_base; + + ret = uclass_get_device_by_phandle(UCLASS_FIRMWARE, dev, + "ti,sci", &tisci_dev); + if (ret) { + debug("Failed to get TISCI phandle (%d)\n", ret); + tisci_rm->tisci = NULL; + return -EINVAL; + } + tisci_rm->tisci = (struct ti_sci_handle *) + (ti_sci_get_handle_from_sysfw(tisci_dev)); + + tisci_rm->tisci_dev_id = -1; + ret = dev_read_u32(dev, "ti,sci-dev-id", &tisci_rm->tisci_dev_id); + if (ret) { + dev_err(dev, "ti,sci-dev-id read failure %d\n", ret); + return ret; + } + + tisci_rm->tisci_navss_dev_id = -1; + ret = ofnode_read_u32(navss_ofnode, "ti,sci-dev-id", + &tisci_rm->tisci_navss_dev_id); + if (ret) { + dev_err(dev, "navss sci-dev-id read failure %d\n", ret); + return ret; + } + + tisci_rm->tisci_udmap_ops = &tisci_rm->tisci->ops.rm_udmap_ops; + tisci_rm->tisci_psil_ops = &tisci_rm->tisci->ops.rm_psil_ops; + + if (ud->match_data->type == DMA_TYPE_UDMA) { + ret = uclass_get_device_by_phandle(UCLASS_MISC, dev, + "ti,ringacc", &tmp); + ud->ringacc = dev_get_priv(tmp); + } else { + struct k3_ringacc_init_data ring_init_data; + + ring_init_data.tisci = ud->tisci_rm.tisci; + ring_init_data.tisci_dev_id = ud->tisci_rm.tisci_dev_id; + if (ud->match_data->type == DMA_TYPE_BCDMA) { + ring_init_data.num_rings = ud->bchan_cnt + + ud->tchan_cnt + + ud->rchan_cnt; + } else { + ring_init_data.num_rings = ud->rflow_cnt + + ud->tflow_cnt; + } + + ud->ringacc = k3_ringacc_dmarings_init(dev, &ring_init_data); + } + if (IS_ERR(ud->ringacc)) + return PTR_ERR(ud->ringacc); + + ud->dev = dev; + ret = setup_resources(ud); + if (ret < 0) + return ret; + + ud->ch_count = ret; + + for (i = 0; i < ud->bchan_cnt; i++) { + struct udma_bchan *bchan = &ud->bchans[i]; + + bchan->id = i; + bchan->reg_rt = ud->mmrs[MMR_BCHANRT] + i * 0x1000; + } + + for (i = 0; i < ud->tchan_cnt; i++) { + struct udma_tchan *tchan = &ud->tchans[i]; + + tchan->id = i; + tchan->reg_chan = ud->mmrs[MMR_TCHAN] + UDMA_CH_100(i); + tchan->reg_rt = ud->mmrs[MMR_TCHANRT] + UDMA_CH_1000(i); + } + + for (i = 0; i < ud->rchan_cnt; i++) { + struct udma_rchan *rchan = &ud->rchans[i]; + + rchan->id = i; + rchan->reg_chan = ud->mmrs[MMR_RCHAN] + UDMA_CH_100(i); + rchan->reg_rt = ud->mmrs[MMR_RCHANRT] + UDMA_CH_1000(i); + } + + for (i = 0; i < ud->rflow_cnt; i++) { + struct udma_rflow *rflow = &ud->rflows[i]; + + rflow->id = i; + rflow->reg_rflow = ud->mmrs[MMR_RFLOW] + UDMA_CH_40(i); + } + + for (i = 0; i < ud->ch_count; i++) { + struct udma_chan *uc = &ud->channels[i]; + + uc->ud = ud; + uc->id = i; + uc->config.remote_thread_id = -1; + uc->bchan = NULL; + uc->tchan = NULL; + uc->rchan = NULL; + uc->config.mapped_channel_id = -1; + uc->config.default_flow_id = -1; + uc->config.dir = DMA_MEM_TO_MEM; + sprintf(uc->name, "UDMA chan%d\n", i); + if (!i) + uc->in_use = true; + } + + pr_debug("%s(rev: 0x%08x) CAP0-3: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n", + dev->name, + udma_read(ud->mmrs[MMR_GCFG], 0), + udma_read(ud->mmrs[MMR_GCFG], 0x20), + udma_read(ud->mmrs[MMR_GCFG], 0x24), + udma_read(ud->mmrs[MMR_GCFG], 0x28), + udma_read(ud->mmrs[MMR_GCFG], 0x2c)); + + uc_priv->supported = DMA_SUPPORTS_MEM_TO_MEM | DMA_SUPPORTS_MEM_TO_DEV; + + uc = &ud->channels[0]; + ret = 0; + switch (ud->match_data->type) { + case DMA_TYPE_UDMA: + ret = udma_alloc_chan_resources(uc); + break; + case DMA_TYPE_BCDMA: + ret = bcdma_alloc_chan_resources(uc); + break; + default: + break; /* Do nothing in any other case */ + }; + + if (ret) + dev_err(dev, " Channel 0 allocation failure %d\n", ret); + + return ret; +} + +static int udma_remove(struct udevice *dev) +{ + struct udma_dev *ud = dev_get_priv(dev); + struct udma_chan *uc = &ud->channels[0]; + + switch (ud->match_data->type) { + case DMA_TYPE_UDMA: + udma_free_chan_resources(uc); + break; + case DMA_TYPE_BCDMA: + bcdma_free_bchan_resources(uc); + break; + default: + break; + }; + + return 0; +} + static const struct dma_ops udma_ops = { .transfer = udma_transfer, .of_xlate = udma_of_xlate, @@ -2855,5 +2866,7 @@ U_BOOT_DRIVER(ti_edma3) = { .of_match = udma_ids, .ops = &udma_ops, .probe = udma_probe, + .remove = udma_remove, .priv_auto = sizeof(struct udma_dev), + .flags = DM_FLAG_OS_PREPARE, }; diff --git a/drivers/fastboot/Kconfig b/drivers/fastboot/Kconfig index 70207573de2..1eb460f5a02 100644 --- a/drivers/fastboot/Kconfig +++ b/drivers/fastboot/Kconfig @@ -1,5 +1,6 @@ menu "Fastboot support" depends on CMDLINE + depends on !NET_LWIP config FASTBOOT bool diff --git a/drivers/i2c/i2c-gpio.c b/drivers/i2c/i2c-gpio.c index e0a575fb4a4..00aef40e341 100644 --- a/drivers/i2c/i2c-gpio.c +++ b/drivers/i2c/i2c-gpio.c @@ -101,7 +101,7 @@ static int i2c_gpio_read_bit(struct i2c_gpio_bus *bus, int delay) bus->set_scl(bus, 1); udelay(delay); - value = bus->get_sda(bus); + value = bus->get_sda ? bus->get_sda(bus) : 0; udelay(delay); bus->set_scl(bus, 0); udelay(2 * delay); @@ -256,6 +256,9 @@ static int i2c_gpio_read_data(struct i2c_gpio_bus *bus, uchar chip, { unsigned int delay = bus->udelay; + if (!bus->get_sda) + return -EOPNOTSUPP; + debug("%s: chip %x buffer: %p len %d\n", __func__, chip, buffer, len); while (len-- > 0) @@ -353,7 +356,10 @@ static int i2c_gpio_of_to_plat(struct udevice *dev) bus->udelay = dev_read_u32_default(dev, "i2c-gpio,delay-us", DEFAULT_UDELAY); - bus->get_sda = i2c_gpio_sda_get; + if (dev_read_bool(dev, "i2c-gpio,sda-output-only")) + bus->get_sda = NULL; + else + bus->get_sda = i2c_gpio_sda_get; bus->set_sda = i2c_gpio_sda_set; if (dev_read_bool(dev, "i2c-gpio,scl-output-only")) bus->set_scl = i2c_gpio_scl_set_output_only; diff --git a/drivers/i2c/muxes/Kconfig b/drivers/i2c/muxes/Kconfig index 323c4fbe9cc..cd5579aa55a 100644 --- a/drivers/i2c/muxes/Kconfig +++ b/drivers/i2c/muxes/Kconfig @@ -36,6 +36,11 @@ config I2C_MUX_PCA954x device. Supported chips are PCA9543, PCA9544, PCA9546, PCA9547, PCA9548 and PCA9646. + It's also compatible to Maxims MAX735x I2C switch chips, which are controlled + as the NXP PCA9548 and the MAX736x chips that act like the PCA9544. + This includes the: + MAX7356, MAX7357, MAX7358, MAX7367, MAX7368 and MAX7369 + config I2C_MUX_GPIO tristate "GPIO-based I2C multiplexer" depends on I2C_MUX && DM_GPIO diff --git a/drivers/i2c/muxes/pca954x.c b/drivers/i2c/muxes/pca954x.c index 795288fe2e9..9dd26972703 100644 --- a/drivers/i2c/muxes/pca954x.c +++ b/drivers/i2c/muxes/pca954x.c @@ -14,6 +14,12 @@ #include <asm-generic/gpio.h> enum pca_type { + MAX7356, + MAX7357, + MAX7358, + MAX7367, + MAX7368, + MAX7369, PCA9543, PCA9544, PCA9546, @@ -39,6 +45,31 @@ struct pca954x_priv { }; static const struct chip_desc chips[] = { + [MAX7356] = { + .muxtype = pca954x_isswi, + .width = 8, + }, + [MAX7357] = { + .muxtype = pca954x_isswi, + .width = 8, + }, + [MAX7358] = { + .muxtype = pca954x_isswi, + .width = 8, + }, + [MAX7367] = { + .muxtype = pca954x_isswi, + .width = 4, + }, + [MAX7368] = { + .muxtype = pca954x_isswi, + .width = 4, + }, + [MAX7369] = { + .enable = 0x4, + .muxtype = pca954x_ismux, + .width = 4, + }, [PCA9543] = { .muxtype = pca954x_isswi, .width = 2, @@ -102,6 +133,12 @@ static const struct i2c_mux_ops pca954x_ops = { }; static const struct udevice_id pca954x_ids[] = { + { .compatible = "maxim,max7356", .data = MAX7356 }, + { .compatible = "maxim,max7357", .data = MAX7357 }, + { .compatible = "maxim,max7358", .data = MAX7358 }, + { .compatible = "maxim,max7367", .data = MAX7367 }, + { .compatible = "maxim,max7368", .data = MAX7368 }, + { .compatible = "maxim,max7369", .data = MAX7369 }, { .compatible = "nxp,pca9543", .data = PCA9543 }, { .compatible = "nxp,pca9544", .data = PCA9544 }, { .compatible = "nxp,pca9546", .data = PCA9546 }, diff --git a/drivers/misc/k3_avs.c b/drivers/misc/k3_avs.c index 87471cc3b16..99a18a109b7 100644 --- a/drivers/misc/k3_avs.c +++ b/drivers/misc/k3_avs.c @@ -352,6 +352,9 @@ static int k3_avs_probe(struct udevice *dev) struct k3_avs_privdata *priv; struct vd_data *vd; int ret; + ofnode node; + struct ofnode_phandle_args phandle_args; + int i = 0; priv = dev_get_priv(dev); priv->dev = dev; @@ -367,6 +370,32 @@ static int k3_avs_probe(struct udevice *dev) return -ENODEV; for (vd = priv->vd_config->vds; vd->id >= 0; vd++) { + /* Get the clock and dev id for Jacinto platforms */ + if (vd->id == J721E_VDD_MPU) { + node = ofnode_by_compatible(ofnode_null(), "ti,am654-rproc"); + if (!ofnode_valid(node)) + return -ENODEV; + + i = ofnode_stringlist_search(node, "clock-names", "core"); + if (i < 0) + return -ENODEV; + + ret = ofnode_parse_phandle_with_args(node, "clocks", + "#clock-cells", + 0, i, + &phandle_args); + if (ret) { + printf("Couldn't get the clock node, ret = %d\n", ret); + return ret; + } + + vd->dev_id = phandle_args.args[0]; + vd->clk_id = phandle_args.args[1]; + + debug("%s: MPU dev_id: %d, clk_id: %d", __func__, + vd->dev_id, vd->clk_id); + } + if (!(readl(AM6_VTM_DEVINFO(vd->id)) & AM6_VTM_AVS0_SUPPORTED)) { dev_warn(dev, "AVS-class 0 not supported for VD%d\n", @@ -391,7 +420,10 @@ static int k3_avs_probe(struct udevice *dev) if (vd->flags & VD_FLAG_INIT_DONE) continue; - k3_avs_program_voltage(priv, vd, vd->opp); + ret = k3_avs_program_voltage(priv, vd, vd->opp); + if (ret) + dev_warn(dev, "Could not program AVS voltage for VD%d, vd->opp=%d, ret=%d\n", + vd->id, vd->opp, ret); } if (!device_is_compatible(priv->dev, "ti,am654-avs")) @@ -460,6 +492,12 @@ static struct vd_data j721e_vd_data[] = { { .id = J721E_VDD_MPU, .opp = AM6_OPP_NOM, + /* + * XXX: DEPRECATION WARNING: Around 2 u-boot versions + * + * These values will be picked up from DT, kept for backward + * compatibility + */ .dev_id = 202, /* J721E_DEV_A72SS0_CORE0 */ .clk_id = 2, /* ARM clock */ .opps = { diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 22c65681f0a..38817622fca 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -130,6 +130,7 @@ config MMC_HW_PARTITIONING config SUPPORT_EMMC_RPMB bool "Support eMMC replay protected memory block (RPMB)" imply CMD_MMC_RPMB + select SHA256 help Enable support for reading, writing and programming the key for the Replay Protection Memory Block partition in eMMC. diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c index 8551eac7018..e1110cace89 100644 --- a/drivers/mmc/dw_mmc.c +++ b/drivers/mmc/dw_mmc.c @@ -214,66 +214,24 @@ static unsigned int dwmci_get_timeout(struct mmc *mmc, const unsigned int size) return timeout; } -static int dwmci_data_transfer_fifo(struct dwmci_host *host, - struct mmc_data *data, u32 mask) +static int dwmci_data_transfer(struct dwmci_host *host, struct mmc_data *data) { - const u32 int_rx = mask & (DWMCI_INTMSK_RXDR | DWMCI_INTMSK_DTO); - const u32 int_tx = mask & DWMCI_INTMSK_TXDR; + struct mmc *mmc = host->mmc; int ret = 0; - u32 len = 0, size, i; - u32 *buf; - - size = (data->blocksize * data->blocks) / 4; - if (!host->fifo_mode || !size) - return 0; + u32 timeout, mask, size, i, len = 0; + u32 *buf = NULL; + ulong start = get_timer(0); + size = data->blocksize * data->blocks; if (data->flags == MMC_DATA_READ) buf = (unsigned int *)data->dest; else buf = (unsigned int *)data->src; - if (data->flags == MMC_DATA_READ && int_rx) { - dwmci_writel(host, DWMCI_RINTSTS, int_rx); - while (size) { - ret = dwmci_fifo_ready(host, DWMCI_FIFO_EMPTY, &len); - if (ret < 0) - break; - - len = (len >> DWMCI_FIFO_SHIFT) & DWMCI_FIFO_MASK; - len = min(size, len); - for (i = 0; i < len; i++) - *buf++ = dwmci_readl(host, DWMCI_DATA); - size = size > len ? (size - len) : 0; - } - } else if (data->flags == MMC_DATA_WRITE && int_tx) { - while (size) { - ret = dwmci_fifo_ready(host, DWMCI_FIFO_FULL, &len); - if (ret < 0) - break; - - len = host->fifo_depth - ((len >> DWMCI_FIFO_SHIFT) & - DWMCI_FIFO_MASK); - len = min(size, len); - for (i = 0; i < len; i++) - dwmci_writel(host, DWMCI_DATA, *buf++); - size = size > len ? (size - len) : 0; - } - dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_TXDR); - } - - return ret; -} - -static int dwmci_data_transfer(struct dwmci_host *host, struct mmc_data *data) -{ - struct mmc *mmc = host->mmc; - int ret = 0; - u32 timeout, mask, size; - ulong start = get_timer(0); - - size = data->blocksize * data->blocks; timeout = dwmci_get_timeout(mmc, size); + size /= 4; + for (;;) { mask = dwmci_readl(host, DWMCI_RINTSTS); /* Error during data transfer */ @@ -283,7 +241,50 @@ static int dwmci_data_transfer(struct dwmci_host *host, struct mmc_data *data) break; } - ret = dwmci_data_transfer_fifo(host, data, mask); + if (host->fifo_mode && size) { + len = 0; + if (data->flags == MMC_DATA_READ && + (mask & (DWMCI_INTMSK_RXDR | DWMCI_INTMSK_DTO))) { + dwmci_writel(host, DWMCI_RINTSTS, + mask & (DWMCI_INTMSK_RXDR | + DWMCI_INTMSK_DTO)); + while (size) { + ret = dwmci_fifo_ready(host, + DWMCI_FIFO_EMPTY, + &len); + if (ret < 0) + break; + + len = (len >> DWMCI_FIFO_SHIFT) & + DWMCI_FIFO_MASK; + len = min(size, len); + for (i = 0; i < len; i++) + *buf++ = + dwmci_readl(host, DWMCI_DATA); + size = size > len ? (size - len) : 0; + } + } else if (data->flags == MMC_DATA_WRITE && + (mask & DWMCI_INTMSK_TXDR)) { + while (size) { + ret = dwmci_fifo_ready(host, + DWMCI_FIFO_FULL, + &len); + if (ret < 0) + break; + + len = host->fifo_depth - ((len >> + DWMCI_FIFO_SHIFT) & + DWMCI_FIFO_MASK); + len = min(size, len); + for (i = 0; i < len; i++) + dwmci_writel(host, DWMCI_DATA, + *buf++); + size = size > len ? (size - len) : 0; + } + dwmci_writel(host, DWMCI_RINTSTS, + DWMCI_INTMSK_TXDR); + } + } /* Data arrived correctly */ if (mask & DWMCI_INTMSK_DTO) { diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 6f5395c7b9b..f5c9868bbca 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -194,27 +194,26 @@ struct sfdp_bfpt { /** * struct spi_nor_fixups - SPI NOR fixup hooks - * @default_init: called after default flash parameters init. Used to tweak - * flash parameters when information provided by the flash_info - * table is incomplete or wrong. * @post_bfpt: called after the BFPT table has been parsed - * @post_sfdp: called after SFDP has been parsed (is also called for SPI NORs - * that do not support RDSFDP). Typically used to tweak various - * parameters that could not be extracted by other means (i.e. - * when information provided by the SFDP/flash_info tables are - * incomplete or wrong). + * @post_sfdp: called after SFDP has been parsed. Typically used to tweak + * various parameters that could not be extracted by other means + * (i.e. when information provided by the SFDP tables are incomplete + * or wrong). + * @late_init: used to initialize flash parameters that are not declared in the + * JESD216 SFDP standard, or where SFDP tables not defined at all. * * Those hooks can be used to tweak the SPI NOR configuration when the SFDP * table is broken or not available. */ struct spi_nor_fixups { - void (*default_init)(struct spi_nor *nor); int (*post_bfpt)(struct spi_nor *nor, const struct sfdp_parameter_header *bfpt_header, const struct sfdp_bfpt *bfpt, struct spi_nor_flash_parameter *params); void (*post_sfdp)(struct spi_nor *nor, struct spi_nor_flash_parameter *params); + void (*late_init)(struct spi_nor *nor, + struct spi_nor_flash_parameter *params); }; #define SPI_NOR_SRST_SLEEP_LEN 200 @@ -3045,13 +3044,12 @@ static int spi_nor_parse_sfdp(struct spi_nor *nor, /** * spi_nor_post_sfdp_fixups() - Updates the flash's parameters and settings - * after SFDP has been parsed (is also called for SPI NORs that do not - * support RDSFDP). + * after SFDP has been parsed. * @nor: pointer to a 'struct spi_nor' * * Typically used to tweak various parameters that could not be extracted by - * other means (i.e. when information provided by the SFDP/flash_info tables - * are incomplete or wrong). + * other means (i.e. when information provided by the SFDP tables are incomplete + * or wrong). */ static void spi_nor_post_sfdp_fixups(struct spi_nor *nor, struct spi_nor_flash_parameter *params) @@ -3060,10 +3058,11 @@ static void spi_nor_post_sfdp_fixups(struct spi_nor *nor, nor->fixups->post_sfdp(nor, params); } -static void spi_nor_default_init_fixups(struct spi_nor *nor) +static void spi_nor_late_init_fixups(struct spi_nor *nor, + struct spi_nor_flash_parameter *params) { - if (nor->fixups && nor->fixups->default_init) - nor->fixups->default_init(nor); + if (nor->fixups && nor->fixups->late_init) + nor->fixups->late_init(nor, params); } static int spi_nor_init_params(struct spi_nor *nor, @@ -3081,6 +3080,7 @@ static int spi_nor_init_params(struct spi_nor *nor, memset(params, 0, sizeof(*params)); /* Set SPI NOR sizes. */ + params->writesize = 1; params->size = info->sector_size * info->n_sectors; params->page_size = info->page_size; @@ -3176,8 +3176,6 @@ static int spi_nor_init_params(struct spi_nor *nor, } } - spi_nor_default_init_fixups(nor); - /* Override the parameters with data read from SFDP tables. */ nor->addr_width = 0; nor->mtd.erasesize = 0; @@ -3193,6 +3191,8 @@ static int spi_nor_init_params(struct spi_nor *nor, } else { memcpy(params, &sfdp_params, sizeof(*params)); } + + spi_nor_post_sfdp_fixups(nor, params); } #if CONFIG_IS_ENABLED(DM_SPI) && CONFIG_IS_ENABLED(SPI_ADVANCE) /* @@ -3250,7 +3250,7 @@ static int spi_nor_init_params(struct spi_nor *nor, params->page_size <<= 1; } #endif - spi_nor_post_sfdp_fixups(nor, params); + spi_nor_late_init_fixups(nor, params); return 0; } @@ -3714,7 +3714,8 @@ static int s25fs_s_setup(struct spi_nor *nor, const struct flash_info *info, return spi_nor_default_setup(nor, info, params); } -static void s25fs_s_default_init(struct spi_nor *nor) +static void s25fs_s_late_init(struct spi_nor *nor, + struct spi_nor_flash_parameter *params) { nor->setup = s25fs_s_setup; } @@ -3764,9 +3765,9 @@ static void s25fs_s_post_sfdp_fixup(struct spi_nor *nor, } static struct spi_nor_fixups s25fs_s_fixups = { - .default_init = s25fs_s_default_init, .post_bfpt = s25fs_s_post_bfpt_fixup, .post_sfdp = s25fs_s_post_sfdp_fixup, + .late_init = s25fs_s_late_init, }; static int s25_s28_mdp_ready(struct spi_nor *nor) @@ -3850,9 +3851,17 @@ static int s25_s28_setup(struct spi_nor *nor, const struct flash_info *info, return spi_nor_default_setup(nor, info, params); } -static void s25_default_init(struct spi_nor *nor) +static void s25_late_init(struct spi_nor *nor, + struct spi_nor_flash_parameter *params) { nor->setup = s25_s28_setup; + + /* + * Programming is supported only in 16-byte ECC data unit granularity. + * Byte-programming, bit-walking, or multiple program operations to the + * same ECC data unit without an erase are not allowed. + */ + params->writesize = 16; } static int s25_s28_post_bfpt_fixup(struct spi_nor *nor, @@ -3931,9 +3940,9 @@ static void s25_post_sfdp_fixup(struct spi_nor *nor, } static struct spi_nor_fixups s25_fixups = { - .default_init = s25_default_init, .post_bfpt = s25_s28_post_bfpt_fixup, .post_sfdp = s25_post_sfdp_fixup, + .late_init = s25_late_init, }; static int s25fl256l_setup(struct spi_nor *nor, const struct flash_info *info, @@ -3942,13 +3951,14 @@ static int s25fl256l_setup(struct spi_nor *nor, const struct flash_info *info, return -ENOTSUPP; /* Bank Address Register is not supported */ } -static void s25fl256l_default_init(struct spi_nor *nor) +static void s25fl256l_late_init(struct spi_nor *nor, + struct spi_nor_flash_parameter *params) { nor->setup = s25fl256l_setup; } static struct spi_nor_fixups s25fl256l_fixups = { - .default_init = s25fl256l_default_init, + .late_init = s25fl256l_late_init, }; #endif @@ -4011,10 +4021,18 @@ static int spi_nor_cypress_octal_dtr_enable(struct spi_nor *nor) return 0; } -static void s28hx_t_default_init(struct spi_nor *nor) +static void s28hx_t_late_init(struct spi_nor *nor, + struct spi_nor_flash_parameter *params) { nor->octal_dtr_enable = spi_nor_cypress_octal_dtr_enable; nor->setup = s25_s28_setup; + + /* + * Programming is supported only in 16-byte ECC data unit granularity. + * Byte-programming, bit-walking, or multiple program operations to the + * same ECC data unit without an erase are not allowed. + */ + params->writesize = 16; } static void s28hx_t_post_sfdp_fixup(struct spi_nor *nor, @@ -4049,9 +4067,9 @@ static void s28hx_t_post_sfdp_fixup(struct spi_nor *nor, } static struct spi_nor_fixups s28hx_t_fixups = { - .default_init = s28hx_t_default_init, .post_sfdp = s28hx_t_post_sfdp_fixup, .post_bfpt = s25_s28_post_bfpt_fixup, + .late_init = s28hx_t_late_init, }; #endif /* CONFIG_SPI_FLASH_S28HX_T */ @@ -4103,7 +4121,8 @@ static int spi_nor_micron_octal_dtr_enable(struct spi_nor *nor) return 0; } -static void mt35xu512aba_default_init(struct spi_nor *nor) +static void mt35xu512aba_late_init(struct spi_nor *nor, + struct spi_nor_flash_parameter *params) { nor->octal_dtr_enable = spi_nor_micron_octal_dtr_enable; } @@ -4132,8 +4151,8 @@ static void mt35xu512aba_post_sfdp_fixup(struct spi_nor *nor, } static struct spi_nor_fixups mt35xu512aba_fixups = { - .default_init = mt35xu512aba_default_init, .post_sfdp = mt35xu512aba_post_sfdp_fixup, + .late_init = mt35xu512aba_late_init, }; #endif /* CONFIG_SPI_FLASH_MT35XU */ @@ -4193,7 +4212,8 @@ static int spi_nor_macronix_octal_dtr_enable(struct spi_nor *nor) return 0; } -static void macronix_octal_default_init(struct spi_nor *nor) +static void macronix_octal_late_init(struct spi_nor *nor, + struct spi_nor_flash_parameter *params) { nor->octal_dtr_enable = spi_nor_macronix_octal_dtr_enable; } @@ -4210,8 +4230,8 @@ static void macronix_octal_post_sfdp_fixup(struct spi_nor *nor, } static struct spi_nor_fixups macronix_octal_fixups = { - .default_init = macronix_octal_default_init, .post_sfdp = macronix_octal_post_sfdp_fixup, + .late_init = macronix_octal_late_init, }; #endif /* CONFIG_SPI_FLASH_MACRONIX */ @@ -4422,7 +4442,9 @@ void spi_nor_set_fixups(struct spi_nor *nor) #endif #if CONFIG_IS_ENABLED(SPI_FLASH_MACRONIX) - nor->fixups = ¯onix_octal_fixups; + if (JEDEC_MFR(nor->info) == SNOR_MFR_MACRONIX && + nor->info->flags & SPI_NOR_OCTAL_DTR_READ) + nor->fixups = ¯onix_octal_fixups; #endif /* SPI_FLASH_MACRONIX */ } @@ -4499,7 +4521,7 @@ int spi_nor_scan(struct spi_nor *nor) mtd->dev = nor->dev; mtd->priv = nor; mtd->type = MTD_NORFLASH; - mtd->writesize = 1; + mtd->writesize = params.writesize; mtd->flags = MTD_CAP_NORFLASH; mtd->size = params.size; mtd->_erase = spi_nor_erase; diff --git a/drivers/mtd/ubi/build.c b/drivers/mtd/ubi/build.c index cf0d702421f..104537784ab 100644 --- a/drivers/mtd/ubi/build.c +++ b/drivers/mtd/ubi/build.c @@ -679,10 +679,8 @@ static int io_init(struct ubi_device *ubi, int max_beb_per1024) ubi->bad_peb_limit = get_bad_peb_limit(ubi, max_beb_per1024); } - if (ubi->mtd->type == MTD_NORFLASH) { - ubi_assert(ubi->mtd->writesize == 1); + if (ubi->mtd->type == MTD_NORFLASH) ubi->nor_flash = 1; - } ubi->min_io_size = ubi->mtd->writesize; ubi->hdrs_min_io_size = ubi->mtd->writesize >> ubi->mtd->subpage_sft; diff --git a/drivers/mtd/ubi/io.c b/drivers/mtd/ubi/io.c index 14be95b74bc..45699b4a477 100644 --- a/drivers/mtd/ubi/io.c +++ b/drivers/mtd/ubi/io.c @@ -563,7 +563,14 @@ int ubi_io_sync_erase(struct ubi_device *ubi, int pnum, int torture) return -EROFS; } - if (ubi->nor_flash) { + /* + * If the flash is ECC-ed then we have to erase the ECC block before we + * can write to it. But the write is in preparation to an erase in the + * first place. This means we cannot zero out EC and VID before the + * erase and we just have to hope the flash starts erasing from the + * start of the page. + */ + if (ubi->nor_flash && ubi->mtd->writesize == 1) { err = nor_erase_prepare(ubi, pnum); if (err) return err; diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 403d7e1c679..89f7411bdf3 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -48,6 +48,7 @@ config DM_DSA bool "Enable Driver Model for DSA switches" depends on DM_MDIO depends on PHY_FIXED + depends on !NET_LWIP help Enable driver model for DSA switches @@ -96,7 +97,7 @@ config DSA_SANDBOX menuconfig NETDEVICES bool "Network device support" - depends on NET + depends on NET || NET_LWIP select DM_ETH help You must select Y to enable any network device support @@ -342,6 +343,7 @@ config ESSEDMA config ETH_SANDBOX depends on SANDBOX + depends on NET default y bool "Sandbox: Mocked Ethernet driver" help @@ -350,8 +352,20 @@ config ETH_SANDBOX This driver is particularly useful in the test/dm/eth.c tests +config ETH_SANDBOX_LWIP + depends on SANDBOX + depends on NET_LWIP + default y + bool "Sandbox: Mocked Ethernet driver (for NET_LWIP)" + help + This driver is meant as a replacement for ETH_SANDBOX when + the network stack is NET_LWIP rather than NET. It currently + does nothing, i.e. it drops the sent packets and never receives + data. + config ETH_SANDBOX_RAW depends on SANDBOX + depends on NET default y bool "Sandbox: Bridge to Linux Raw Sockets" help diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 4946a63f80f..f5ab1f5dedf 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -39,6 +39,7 @@ obj-$(CONFIG_ETH_DESIGNWARE_SOCFPGA) += dwmac_socfpga.o obj-$(CONFIG_ETH_SANDBOX) += sandbox.o obj-$(CONFIG_ETH_SANDBOX_RAW) += sandbox-raw-bus.o obj-$(CONFIG_ETH_SANDBOX_RAW) += sandbox-raw.o +obj-$(CONFIG_ETH_SANDBOX_LWIP) += sandbox-lwip.o obj-$(CONFIG_FEC_MXC) += fec_mxc.o obj-$(CONFIG_FMAN_ENET) += fm/ obj-$(CONFIG_FMAN_ENET) += fsl_mdio.o diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index a9efc509814..13e73810ad6 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -11,7 +11,7 @@ config MV88E6352_SWITCH menuconfig PHYLIB bool "Ethernet PHY (physical media interface) support" - depends on NET + depends on NET || NET_LWIP help Enable Ethernet PHY (physical media interface) support. diff --git a/drivers/net/sandbox-lwip.c b/drivers/net/sandbox-lwip.c new file mode 100644 index 00000000000..3721033c310 --- /dev/null +++ b/drivers/net/sandbox-lwip.c @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2015 National Instruments + * + * (C) Copyright 2015 + * Joe Hershberger <joe.hershberger@ni.com> + */ + +#include <dm.h> +#include <log.h> +#include <malloc.h> +#include <net.h> +#include <asm/eth.h> +#include <asm/global_data.h> +#include <asm/test.h> + +DECLARE_GLOBAL_DATA_PTR; + +static int sb_lwip_eth_start(struct udevice *dev) +{ + debug("eth_sandbox_lwip: Start\n"); + + return 0; +} + +static int sb_lwip_eth_send(struct udevice *dev, void *packet, int length) +{ + debug("eth_sandbox_lwip: Send packet %d\n", length); + + return -ENOTSUPP; +} + +static int sb_lwip_eth_recv(struct udevice *dev, int flags, uchar **packetp) +{ + return -EAGAIN; +} + +static int sb_lwip_eth_free_pkt(struct udevice *dev, uchar *packet, int length) +{ + return 0; +} + +static void sb_lwip_eth_stop(struct udevice *dev) +{ +} + +static int sb_lwip_eth_write_hwaddr(struct udevice *dev) +{ + return 0; +} + +static const struct eth_ops sb_eth_ops = { + .start = sb_lwip_eth_start, + .send = sb_lwip_eth_send, + .recv = sb_lwip_eth_recv, + .free_pkt = sb_lwip_eth_free_pkt, + .stop = sb_lwip_eth_stop, + .write_hwaddr = sb_lwip_eth_write_hwaddr, +}; + +static int sb_lwip_eth_remove(struct udevice *dev) +{ + return 0; +} + +static int sb_lwip_eth_of_to_plat(struct udevice *dev) +{ + return 0; +} + +static const struct udevice_id sb_eth_ids[] = { + { .compatible = "sandbox,eth" }, + { } +}; + +U_BOOT_DRIVER(eth_sandbox) = { + .name = "eth_lwip_sandbox", + .id = UCLASS_ETH, + .of_match = sb_eth_ids, + .of_to_plat = sb_lwip_eth_of_to_plat, + .remove = sb_lwip_eth_remove, + .ops = &sb_eth_ops, + .priv_auto = 0, + .plat_auto = sizeof(struct eth_pdata), +}; diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 22a56f4ca38..876a5fa57ee 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -137,6 +137,12 @@ config PCI_GT64120 bool "GT64120 PCI support" depends on MIPS +config PCIE_CDNS_TI + bool "TI K3 PCIe support" + help + Say Y here to enable support for the Cadence PCIe Controller + on TI's K3 SoCs. + config PCI_PHYTIUM bool "Phytium PCIe support" help diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index 5b2d2969802..bf361cd0fba 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_PCI) += pci_auto_common.o pci_common.o obj-$(CONFIG_PCIE_ECAM_GENERIC) += pcie_ecam_generic.o obj-$(CONFIG_PCIE_ECAM_SYNQUACER) += pcie_ecam_synquacer.o obj-$(CONFIG_PCIE_APPLE) += pcie_apple.o +obj-$(CONFIG_PCIE_CDNS_TI) += pcie_cdns_ti.o obj-$(CONFIG_PCI_FTPCI100) += pci_ftpci100.o obj-$(CONFIG_PCI_GT64120) += pci_gt64120.o obj-$(CONFIG_PCI_MPC85XX) += pci_mpc85xx.o diff --git a/drivers/pci/pcie_cdns_ti.c b/drivers/pci/pcie_cdns_ti.c new file mode 100644 index 00000000000..41469a186a3 --- /dev/null +++ b/drivers/pci/pcie_cdns_ti.c @@ -0,0 +1,853 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com + * + * PCIe controller driver for TI's K3 SoCs with Cadence PCIe controller + * + * Ported from the Linux driver - drivers/pci/controller/cadence/pci-j721e.c + * + * Author: Siddharth Vadapalli <s-vadapalli@ti.com> + * + */ + +#include <asm/gpio.h> +#include <clk-uclass.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <generic-phy.h> +#include <linux/delay.h> +#include <linux/io.h> +#include <linux/ioport.h> +#include <linux/log2.h> +#include <power-domain.h> +#include <regmap.h> +#include <syscon.h> + +#define CDNS_PCIE_LM_BASE 0x00100000 +#define CDNS_PCIE_LM_ID (CDNS_PCIE_LM_BASE + 0x0044) +#define CDNS_PCIE_LTSSM_CTRL_CAP (CDNS_PCIE_LM_BASE + 0x0054) +#define CDNS_PCIE_LM_RC_BAR_CFG (CDNS_PCIE_LM_BASE + 0x0300) + +#define CDNS_PCIE_LM_ID_VENDOR_MASK GENMASK(15, 0) +#define CDNS_PCIE_LM_ID_VENDOR_SHIFT 0 +#define CDNS_PCIE_LM_ID_VENDOR(vid) \ + (((vid) << CDNS_PCIE_LM_ID_VENDOR_SHIFT) & CDNS_PCIE_LM_ID_VENDOR_MASK) +#define CDNS_PCIE_LM_ID_SUBSYS_MASK GENMASK(31, 16) +#define CDNS_PCIE_LM_ID_SUBSYS_SHIFT 16 +#define CDNS_PCIE_LM_ID_SUBSYS(sub) \ + (((sub) << CDNS_PCIE_LM_ID_SUBSYS_SHIFT) & CDNS_PCIE_LM_ID_SUBSYS_MASK) + +#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK GENMASK(8, 6) +#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL(c) \ + (((c) << 6) & CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK) + +#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK GENMASK(16, 14) +#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL(c) \ + (((c) << 14) & CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK) + +#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE BIT(17) +#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS BIT(18) +#define CDNS_PCIE_LM_RC_BAR_CFG_IO_ENABLE BIT(19) +#define CDNS_PCIE_LM_RC_BAR_CFG_IO_32BITS BIT(20) + +#define CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED 0x0 +#define CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS 0x4 +#define CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS 0x5 +#define CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS 0x6 +#define CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS 0x7 + +#define LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar) \ + (CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS << (((bar) * 8) + 6)) +#define LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar) \ + (CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS << (((bar) * 8) + 6)) +#define LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar) \ + (CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS << (((bar) * 8) + 6)) +#define LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar) \ + (CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS << (((bar) * 8) + 6)) +#define LM_RC_BAR_CFG_APERTURE(bar, aperture) \ + (((aperture) - 2) << ((bar) * 8)) + +#define CDNS_PCIE_RP_BASE 0x00200000 +#define CDNS_PCIE_RP_CAP_OFFSET 0xc0 + +/* + * Address Translation Registers + */ +#define CDNS_PCIE_AT_BASE 0x00400000 + +/* Region r Outbound AXI to PCIe Address Translation Register 0 */ +#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(r) \ + (CDNS_PCIE_AT_BASE + 0x0000 + ((r) & 0x1f) * 0x0020) +#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK GENMASK(5, 0) +#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS(nbits) \ + (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK) +#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK GENMASK(19, 12) +#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) \ + (((devfn) << 12) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK) +#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK GENMASK(27, 20) +#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS(bus) \ + (((bus) << 20) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK) + +/* Region r Outbound AXI to PCIe Address Translation Register 1 */ +#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(r) \ + (CDNS_PCIE_AT_BASE + 0x0004 + ((r) & 0x1f) * 0x0020) + +/* Region r Outbound PCIe Descriptor Register 0 */ +#define CDNS_PCIE_AT_OB_REGION_DESC0(r) \ + (CDNS_PCIE_AT_BASE + 0x0008 + ((r) & 0x1f) * 0x0020) +#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MEM 0x2 +#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_IO 0x6 +#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE0 0xa +#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE1 0xb + +/* Bit 23 MUST be set in RC mode. */ +#define CDNS_PCIE_AT_OB_REGION_DESC0_HARDCODED_RID BIT(23) +#define CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK GENMASK(31, 24) +#define CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN(devfn) \ + (((devfn) << 24) & CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK) + +/* Region r Outbound PCIe Descriptor Register 1 */ +#define CDNS_PCIE_AT_OB_REGION_DESC1(r) \ + (CDNS_PCIE_AT_BASE + 0x000c + ((r) & 0x1f) * 0x0020) +#define CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK GENMASK(7, 0) +#define CDNS_PCIE_AT_OB_REGION_DESC1_BUS(bus) \ + ((bus) & CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK) + +/* Region r AXI Region Base Address Register 0 */ +#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(r) \ + (CDNS_PCIE_AT_BASE + 0x0018 + ((r) & 0x1f) * 0x0020) +#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK GENMASK(5, 0) +#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) \ + (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK) + +/* Region r AXI Region Base Address Register 1 */ +#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(r) \ + (CDNS_PCIE_AT_BASE + 0x001c + ((r) & 0x1f) * 0x0020) + +/* Root Port BAR Inbound PCIe to AXI Address Translation Register */ +#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0(bar) \ + (CDNS_PCIE_AT_BASE + 0x0800 + (bar) * 0x0008) +#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK GENMASK(5, 0) +#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS(nbits) \ + (((nbits) - 1) & CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK) +#define CDNS_PCIE_AT_IB_RP_BAR_ADDR1(bar) \ + (CDNS_PCIE_AT_BASE + 0x0804 + (bar) * 0x0008) + +/* AXI link down register */ +#define CDNS_PCIE_AT_LINKDOWN (CDNS_PCIE_AT_BASE + 0x0824) + +#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY_MASK GENMASK(2, 1) +#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY_SHIFT 1 +#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY(delay) \ + (((delay) << CDNS_PCIE_DETECT_QUIET_MIN_DELAY_SHIFT) & \ + CDNS_PCIE_DETECT_QUIET_MIN_DELAY_MASK) + +#define CDNS_PCIE_RP_MAX_IB 0x3 + +#define LINK_TRAINING_ENABLE BIT(0) +#define LINK_WAIT_MAX_RETRIES 10 +#define LINK_WAIT_UDELAY_MAX 100000 +#define LINK_RETRAIN_MAX_RETRIES 1000 + +#define PCIE_USER_CMD_STATUS_REG_OFFSET 0x4 +#define PCIE_USER_LINK_STATUS_REG_OFFSET 0x14 +#define PCIE_USER_LINK_STATUS_MASK GENMASK(1, 0) + +#define CDNS_TI_PCIE_MODE_RC BIT(7) +#define PCIE_MODE_SEL_MASK BIT(7) +#define PCIE_GEN_SEL_MASK GENMASK(1, 0) +#define PCIE_LINK_WIDTH_MASK GENMASK(9, 8) + +enum cdns_ti_pcie_mode { + PCIE_MODE_RC, + PCIE_MODE_EP, +}; + +enum cdns_pcie_rp_bar { + RP_BAR_UNDEFINED = -1, + RP_BAR0, + RP_BAR1, + RP_NO_BAR +}; + +static u8 bar_aperture_mask[] = { + [RP_BAR0] = 0x1F, + [RP_BAR1] = 0xF, +}; + +enum link_status { + NO_RECEIVERS_DETECTED, + LINK_TRAINING_IN_PROGRESS, + LINK_UP_DL_IN_PROGRESS, + LINK_UP_DL_COMPLETED, +}; + +struct pcie_cdns_ti_data { + enum cdns_ti_pcie_mode mode; + unsigned int quirk_retrain_flag:1; + unsigned int quirk_detect_quiet_flag:1; + unsigned int max_lanes; +}; + +struct pcie_cdns_ti { + struct udevice *dev; + void __iomem *intd_cfg_base; + void __iomem *user_cfg_base; + void __iomem *reg_base; + void __iomem *cfg_base; + fdt_size_t cfg_size; + struct regmap *syscon_base; + struct pci_controller *host_bridge; + u32 device_id; + u32 max_link_speed; + u32 num_lanes; + u32 pcie_ctrl_offset; + u32 vendor_id; + u32 mode; + unsigned int quirk_retrain_flag:1; + unsigned int quirk_detect_quiet_flag:1; + bool avail_ib_bar[CDNS_PCIE_RP_MAX_IB]; + + /* IO, MEM & PREFETCH PCI regions */ + struct pci_region io; + struct pci_region mem; + struct pci_region prefetch; +}; + +/* Cadence PCIe Controller register access helpers */ +static inline void pcie_cdns_ti_writel(struct pcie_cdns_ti *pcie, u32 reg, u32 val) +{ + writel(val, pcie->reg_base + reg); +} + +static inline u32 pcie_cdns_ti_readl(struct pcie_cdns_ti *pcie, u32 reg) +{ + return readl(pcie->reg_base + reg); +} + +/* Root Port register access helpers */ +static inline void pcie_cdns_ti_rp_writeb(struct pcie_cdns_ti *pcie, + u32 reg, u8 val) +{ + void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg; + + writeb(val, addr); +} + +static inline void pcie_cdns_ti_rp_writew(struct pcie_cdns_ti *pcie, + u32 reg, u16 val) +{ + void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg; + + writew(val, addr); +} + +static inline u16 pcie_cdns_ti_rp_readw(struct pcie_cdns_ti *pcie, u32 reg) +{ + void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg; + + return readw(addr); +} + +/* User register access helpers */ +static inline u32 pcie_cdns_ti_user_readl(struct pcie_cdns_ti *pcie, u32 offset) +{ + return readl(pcie->user_cfg_base + offset); +} + +static inline void pcie_cdns_ti_user_writel(struct pcie_cdns_ti *pcie, u32 offset, + u32 val) +{ + writel(val, pcie->user_cfg_base + offset); +} + +void __iomem *pcie_cdns_ti_map_bus(struct pcie_cdns_ti *pcie, pci_dev_t bdf, + uint offset) +{ + int busnr, devnr, funcnr, devfn; + u32 addr0, desc0; + + busnr = PCI_BUS(bdf); + devnr = PCI_DEV(bdf); + funcnr = PCI_FUNC(bdf); + devfn = (devnr << 3) | funcnr; + + if (busnr == 0) { + if (devfn) + return NULL; + return pcie->reg_base + (offset & 0xfff); + } + + if (!(pcie_cdns_ti_readl(pcie, CDNS_PCIE_LM_BASE) & 0x1)) + return NULL; + + pcie_cdns_ti_writel(pcie, CDNS_PCIE_AT_LINKDOWN, 0x0); + + addr0 = CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS(12) | + CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) | + CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS(busnr); + pcie_cdns_ti_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(0), addr0); + + desc0 = CDNS_PCIE_AT_OB_REGION_DESC0_HARDCODED_RID | + CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN(0); + + if (busnr == 1) + desc0 |= CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE0; + else + desc0 |= CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE1; + + pcie_cdns_ti_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC0(0), desc0); + + return pcie->cfg_base + (offset & 0xfff); +} + +static int pcie_cdns_ti_read_config(const struct udevice *bus, pci_dev_t bdf, + uint offset, ulong *valuep, + enum pci_size_t size) +{ + struct pcie_cdns_ti *pcie = dev_get_priv(bus); + void __iomem *addr; + ulong value; + + addr = pcie_cdns_ti_map_bus(pcie, bdf, offset & ~0x3); + if (!addr) { + debug("%s: bdf out of range\n", __func__); + *valuep = pci_get_ff(size); + return 0; + } + + value = readl(addr); + *valuep = pci_conv_32_to_size(value, offset, size); + + return 0; +} + +static int pcie_cdns_ti_write_config(struct udevice *bus, pci_dev_t bdf, + uint offset, ulong value, + enum pci_size_t size) +{ + struct pcie_cdns_ti *pcie = dev_get_priv(bus); + void __iomem *addr; + ulong prev; + + addr = pcie_cdns_ti_map_bus(pcie, bdf, offset & ~0x3); + if (!addr) { + debug("%s: bdf out of range\n", __func__); + return 0; + } + + prev = readl(addr); + value = pci_conv_size_to_32(prev, value, offset, size); + writel(value, addr); + + return 0; +} + +static int pcie_cdns_ti_ctrl_init(struct pcie_cdns_ti *pcie) +{ + struct regmap *syscon = pcie->syscon_base; + u32 val = 0; + + if (pcie->mode == PCIE_MODE_RC) + val = CDNS_TI_PCIE_MODE_RC; + + /* Set mode of operation */ + regmap_update_bits(syscon, pcie->pcie_ctrl_offset, PCIE_MODE_SEL_MASK, + val); + + /* Set link speed */ + regmap_update_bits(syscon, pcie->pcie_ctrl_offset, PCIE_GEN_SEL_MASK, + pcie->max_link_speed - 1); + + /* Set link width */ + regmap_update_bits(syscon, pcie->pcie_ctrl_offset, PCIE_LINK_WIDTH_MASK, + (pcie->num_lanes - 1) << 8); + return 0; +} + +static void pcie_cdns_ti_detect_quiet_quirk(struct pcie_cdns_ti *pcie) +{ + u32 delay = 0x3; + u32 ltssm_ctrl_cap; + + ltssm_ctrl_cap = pcie_cdns_ti_readl(pcie, CDNS_PCIE_LTSSM_CTRL_CAP); + ltssm_ctrl_cap = ((ltssm_ctrl_cap & + ~CDNS_PCIE_DETECT_QUIET_MIN_DELAY_MASK) | + CDNS_PCIE_DETECT_QUIET_MIN_DELAY(delay)); + + pcie_cdns_ti_writel(pcie, CDNS_PCIE_LTSSM_CTRL_CAP, ltssm_ctrl_cap); + ltssm_ctrl_cap = pcie_cdns_ti_readl(pcie, CDNS_PCIE_LTSSM_CTRL_CAP); +} + +static void pcie_cdns_ti_start_user_link(struct pcie_cdns_ti *pcie) +{ + u32 reg; + + reg = pcie_cdns_ti_user_readl(pcie, PCIE_USER_CMD_STATUS_REG_OFFSET); + reg |= LINK_TRAINING_ENABLE; + pcie_cdns_ti_user_writel(pcie, PCIE_USER_CMD_STATUS_REG_OFFSET, reg); +} + +static bool pcie_cdns_ti_user_link_up(struct pcie_cdns_ti *pcie) +{ + u32 reg; + + reg = pcie_cdns_ti_user_readl(pcie, PCIE_USER_LINK_STATUS_REG_OFFSET); + reg &= PCIE_USER_LINK_STATUS_MASK; + if (reg == LINK_UP_DL_COMPLETED) + return true; + + return false; +} + +static int pcie_cdns_ti_host_wait_for_link(struct pcie_cdns_ti *pcie) +{ + int retries; + + for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { + if (pcie_cdns_ti_user_link_up(pcie)) { + dev_info(pcie->dev, "link up\n"); + return 0; + } + udelay(LINK_WAIT_UDELAY_MAX); + } + + dev_err(pcie->dev, "failed to bring up link\n"); + return -ETIMEDOUT; +} + +static int pcie_cdns_ti_host_training_complete(struct pcie_cdns_ti *pcie) +{ + u32 pcie_cap_off = CDNS_PCIE_RP_CAP_OFFSET; + int retries; + u16 lnk_stat; + + /* Wait for link training to complete */ + for (retries = 0; retries < LINK_RETRAIN_MAX_RETRIES; retries++) { + lnk_stat = pcie_cdns_ti_rp_readw(pcie, pcie_cap_off + + PCI_EXP_LNKSTA); + if (!(lnk_stat & PCI_EXP_LNKSTA_LT)) + break; + udelay(1000); + } + + if (!(lnk_stat & PCI_EXP_LNKSTA_LT)) + return 0; + + return -ETIMEDOUT; +} + +static int pcie_cdns_ti_retrain_link(struct pcie_cdns_ti *pcie) +{ + u32 lnk_cap_sls, pcie_cap_off = CDNS_PCIE_RP_CAP_OFFSET; + u16 lnk_stat, lnk_ctl; + int ret = 0; + + lnk_cap_sls = pcie_cdns_ti_readl(pcie, (CDNS_PCIE_RP_BASE + + pcie_cap_off + + PCI_EXP_LNKCAP)); + if ((lnk_cap_sls & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB) + return ret; + + lnk_stat = pcie_cdns_ti_rp_readw(pcie, pcie_cap_off + PCI_EXP_LNKSTA); + if ((lnk_stat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB) { + lnk_ctl = pcie_cdns_ti_rp_readw(pcie, + pcie_cap_off + PCI_EXP_LNKCTL); + lnk_ctl |= PCI_EXP_LNKCTL_RL; + pcie_cdns_ti_rp_writew(pcie, pcie_cap_off + PCI_EXP_LNKCTL, + lnk_ctl); + + ret = pcie_cdns_ti_host_training_complete(pcie); + if (ret) + return ret; + + ret = pcie_cdns_ti_host_wait_for_link(pcie); + } + return ret; +} + +static int pcie_cdns_ti_start_host_link(struct pcie_cdns_ti *pcie) +{ + int ret; + + ret = pcie_cdns_ti_host_wait_for_link(pcie); + if (!ret && pcie->quirk_retrain_flag) + ret = pcie_cdns_ti_retrain_link(pcie); + + return ret; +} + +static void pcie_cdns_ti_init_root_port(struct pcie_cdns_ti *pcie) +{ + u32 val, ctrl, id; + + ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED; + val = CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL(ctrl) | + CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL(ctrl) | + CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE | + CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS | + CDNS_PCIE_LM_RC_BAR_CFG_IO_ENABLE | + CDNS_PCIE_LM_RC_BAR_CFG_IO_32BITS; + pcie_cdns_ti_writel(pcie, CDNS_PCIE_LM_RC_BAR_CFG, val); + + if (pcie->vendor_id != 0xffff) { + id = CDNS_PCIE_LM_ID_VENDOR(pcie->vendor_id) | + CDNS_PCIE_LM_ID_SUBSYS(pcie->vendor_id); + pcie_cdns_ti_writel(pcie, CDNS_PCIE_LM_ID, id); + } + + if (pcie->device_id != 0xffff) + pcie_cdns_ti_rp_writew(pcie, PCI_DEVICE_ID, pcie->device_id); + + pcie_cdns_ti_rp_writeb(pcie, PCI_CLASS_REVISION, 0); + pcie_cdns_ti_rp_writeb(pcie, PCI_CLASS_PROG, 0); + pcie_cdns_ti_rp_writew(pcie, PCI_CLASS_DEVICE, PCI_CLASS_BRIDGE_PCI); +} + +void pcie_cdns_ti_set_outbound_region(struct pcie_cdns_ti *pcie, u8 busnr, + u8 fn, u32 r, bool is_io, u64 cpu_addr, + u64 pci_addr, u32 size) +{ + u64 sz = 1ULL << fls64(size - 1); + int nbits = ilog2(sz); + u32 addr0, addr1, desc0, desc1; + + if (nbits < 8) + nbits = 8; + + addr0 = CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS(nbits) | + (lower_32_bits(pci_addr) & GENMASK(31, 8)); + addr1 = upper_32_bits(pci_addr); + + pcie_cdns_ti_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(r), addr0); + pcie_cdns_ti_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(r), addr1); + + if (is_io) + desc0 = CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_IO; + else + desc0 = CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MEM; + desc1 = 0; + + desc0 |= CDNS_PCIE_AT_OB_REGION_DESC0_HARDCODED_RID | + CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN(0); + desc1 |= CDNS_PCIE_AT_OB_REGION_DESC1_BUS(busnr); + + pcie_cdns_ti_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC0(r), desc0); + pcie_cdns_ti_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC1(r), desc1); + + addr0 = CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) | + (lower_32_bits(cpu_addr) & GENMASK(31, 8)); + addr1 = upper_32_bits(cpu_addr); + + pcie_cdns_ti_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(r), addr0); + pcie_cdns_ti_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(r), addr1); +} + +static int pcie_cdns_ti_bar_ib_config(struct pcie_cdns_ti *pcie, + enum cdns_pcie_rp_bar bar, + u64 cpu_addr, u64 size, + unsigned long flags) +{ + u32 addr0, addr1, aperture, value; + + if (!pcie->avail_ib_bar[bar]) + return -EBUSY; + + pcie->avail_ib_bar[bar] = false; + + aperture = ilog2(size); + addr0 = CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS(aperture) | + (lower_32_bits(cpu_addr) & GENMASK(31, 8)); + addr1 = upper_32_bits(cpu_addr); + pcie_cdns_ti_writel(pcie, CDNS_PCIE_AT_IB_RP_BAR_ADDR0(bar), addr0); + pcie_cdns_ti_writel(pcie, CDNS_PCIE_AT_IB_RP_BAR_ADDR1(bar), addr1); + + if (bar == RP_NO_BAR) + return 0; + + value = pcie_cdns_ti_readl(pcie, CDNS_PCIE_LM_RC_BAR_CFG); + value &= ~(LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar) | + LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar) | + LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar) | + LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar) | + LM_RC_BAR_CFG_APERTURE(bar, bar_aperture_mask[bar] + 2)); + if (size + cpu_addr >= SZ_4G) { + if (!(flags & IORESOURCE_PREFETCH)) + value |= LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar); + value |= LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar); + } else { + if (!(flags & IORESOURCE_PREFETCH)) + value |= LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar); + value |= LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar); + } + + value |= LM_RC_BAR_CFG_APERTURE(bar, aperture); + pcie_cdns_ti_writel(pcie, CDNS_PCIE_LM_RC_BAR_CFG, value); + + return 0; +} + +static int pcie_cdns_ti_map_dma_ranges(struct pcie_cdns_ti *pcie) +{ + u32 no_bar_nbits = 32; + int ret; + + /* + * Assume that DMA-Ranges have not been specified. + * TODO: Add support for "dma-ranges". + */ + dev_read_u32(pcie->dev, "cdns,no-bar-match-nbits", + &no_bar_nbits); + ret = pcie_cdns_ti_bar_ib_config(pcie, RP_NO_BAR, 0x0, + (u64)1 << no_bar_nbits, 0); + if (ret) + dev_err(pcie->dev, "IB BAR: %d config failed\n", + RP_NO_BAR); + return ret; +} + +static int pcie_cdns_ti_init_address_translation(struct pcie_cdns_ti *pcie) +{ + struct pci_controller *hb = pcie->host_bridge; + u32 addr0, addr1, desc1, region = 1; + u64 cpu_addr = (u64)pcie->cfg_base; + int i, busnr = 0; + + /* + * Reserve region 0 for PCI configure space accesses: + * OB_REGION_PCI_ADDR0 and OB_REGION_DESC0 are updated dynamically by + * cdns_pci_map_bus(), other region registers are set here once for all. + */ + addr1 = 0; /* Should be programmed to zero. */ + desc1 = CDNS_PCIE_AT_OB_REGION_DESC1_BUS(busnr); + pcie_cdns_ti_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(0), addr1); + pcie_cdns_ti_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC1(0), desc1); + + addr0 = CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(12) | + (lower_32_bits(cpu_addr) & GENMASK(31, 8)); + addr1 = upper_32_bits(cpu_addr); + pcie_cdns_ti_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(0), addr0); + pcie_cdns_ti_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(0), addr1); + + for (i = 0; i < hb->region_count; i++) { + if (hb->regions[i].flags == PCI_REGION_IO) { + pcie->io.phys_start = hb->regions[i].phys_start; /* IO base */ + pcie->io.bus_start = hb->regions[i].bus_start; /* IO_bus_addr */ + pcie->io.size = hb->regions[i].size; /* IO size */ + + pcie_cdns_ti_set_outbound_region(pcie, busnr, 0, region, + true, pcie->io.phys_start, + pcie->io.bus_start, + pcie->io.size); + } else { + pcie->mem.phys_start = hb->regions[i].phys_start; /* MEM base */ + pcie->mem.bus_start = hb->regions[i].bus_start; /* MEM_bus_addr */ + pcie->mem.size = hb->regions[i].size; /* MEM size */ + + pcie_cdns_ti_set_outbound_region(pcie, busnr, 0, region, + false, pcie->mem.phys_start, + pcie->mem.bus_start, + pcie->mem.size); + } + region++; + } + + return pcie_cdns_ti_map_dma_ranges(pcie); +} + +static int pcie_cdns_ti_host_init(struct pcie_cdns_ti *pcie) +{ + pcie_cdns_ti_init_root_port(pcie); + + return pcie_cdns_ti_init_address_translation(pcie); +} + +static int pcie_cdns_ti_setup_host(struct pcie_cdns_ti *pcie) +{ + enum cdns_pcie_rp_bar bar; + int ret; + + if (pcie->quirk_detect_quiet_flag) + pcie_cdns_ti_detect_quiet_quirk(pcie); + + pcie_cdns_ti_start_user_link(pcie); + + ret = pcie_cdns_ti_start_host_link(pcie); + if (ret) + return ret; + + for (bar = RP_BAR0; bar <= RP_NO_BAR; bar++) + pcie->avail_ib_bar[bar] = true; + + ret = pcie_cdns_ti_host_init(pcie); + if (ret) + return ret; + + return 0; +} + +static int pcie_cdns_ti_probe(struct udevice *dev) +{ + struct pcie_cdns_ti *pcie = dev_get_priv(dev); + struct udevice *pci_ctlr = pci_get_controller(dev); + struct pci_controller *host_bridge = dev_get_uclass_priv(pci_ctlr); + const struct pcie_cdns_ti_data *data; + struct power_domain pci_pwrdmn; + struct gpio_desc *gpiod; + struct phy serdes; + struct clk *clk; + int ret; + + pcie->dev = dev; + pcie->host_bridge = host_bridge; + + data = (struct pcie_cdns_ti_data *)dev_get_driver_data(dev); + if (!data) + return -EINVAL; + + pcie->mode = data->mode; + pcie->quirk_retrain_flag = data->quirk_retrain_flag; + pcie->quirk_detect_quiet_flag = data->quirk_detect_quiet_flag; + + if (pcie->num_lanes > data->max_lanes) { + dev_warn(dev, "cannot support %d lanes, defaulting to %d\n", + pcie->num_lanes, data->max_lanes); + pcie->num_lanes = data->max_lanes; + } + + ret = power_domain_get_by_index(dev, &pci_pwrdmn, 0); + if (ret) { + dev_err(dev, "failed to get power domain\n"); + return ret; + } + + ret = power_domain_on(&pci_pwrdmn); + if (ret) { + dev_err(dev, "failed to power on\n"); + return ret; + } + + clk = devm_clk_get(dev, "fck"); + if (IS_ERR(clk)) { + ret = PTR_ERR(clk); + dev_err(dev, "failed to get functional clock\n"); + return ret; + } + + ret = generic_phy_get_by_name(dev, "pcie-phy", &serdes); + if (ret) { + dev_err(dev, "unable to get serdes"); + return ret; + } + generic_phy_reset(&serdes); + generic_phy_init(&serdes); + generic_phy_power_on(&serdes); + + ret = pcie_cdns_ti_ctrl_init(pcie); + if (ret) + return ret; + + gpiod = devm_gpiod_get_optional(dev, "reset", GPIOD_IS_OUT); + if (IS_ERR(gpiod)) { + ret = PTR_ERR(gpiod); + if (ret != -EPROBE_DEFER) + dev_err(dev, "Failed to get reset GPIO\n"); + return ret; + } + + if (gpiod) { + ret = dm_gpio_set_value(gpiod, 0); + udelay(200); + ret = dm_gpio_set_value(gpiod, 1); + if (ret) + return ret; + } + + ret = pcie_cdns_ti_setup_host(pcie); + if (ret) + return ret; + + return 0; +} + +static int pcie_cdns_ti_of_to_plat(struct udevice *dev) +{ + struct pcie_cdns_ti *pcie = dev_get_priv(dev); + struct regmap *syscon; + u32 offset; + int ret; + + pcie->intd_cfg_base = dev_remap_addr_name(dev, "intd_cfg"); + if (!pcie->intd_cfg_base) + return -EINVAL; + + pcie->user_cfg_base = dev_remap_addr_name(dev, "user_cfg"); + if (!pcie->user_cfg_base) + return -EINVAL; + + pcie->reg_base = dev_remap_addr_name(dev, "reg"); + if (!pcie->reg_base) + return -EINVAL; + + pcie->cfg_base = dev_remap_addr_name(dev, "cfg"); + if (!pcie->cfg_base) + return -EINVAL; + + pcie->vendor_id = 0xffff; + pcie->device_id = 0xffff; + dev_read_u32(dev, "vendor-id", &pcie->vendor_id); + dev_read_u32(dev, "device-id", &pcie->device_id); + + ret = dev_read_u32(dev, "num-lanes", &pcie->num_lanes); + if (ret) + return ret; + + ret = dev_read_u32(dev, "max-link-speed", &pcie->max_link_speed); + if (ret) + return ret; + + syscon = syscon_regmap_lookup_by_phandle(dev, "ti,syscon-pcie-ctrl"); + if (IS_ERR(syscon)) { + if (PTR_ERR(syscon) == -ENODEV) + return 0; + return PTR_ERR(syscon); + } + + ret = dev_read_u32_index(dev, "ti,syscon-pcie-ctrl", 1, &offset); + if (ret) + return ret; + + pcie->syscon_base = syscon; + pcie->pcie_ctrl_offset = offset; + + return 0; +} + +static const struct dm_pci_ops pcie_cdns_ti_ops = { + .read_config = pcie_cdns_ti_read_config, + .write_config = pcie_cdns_ti_write_config, +}; + +static const struct pcie_cdns_ti_data j7200_pcie_rc_data = { + .mode = PCIE_MODE_RC, + .quirk_detect_quiet_flag = true, + .max_lanes = 2, +}; + +static const struct udevice_id pcie_cdns_ti_ids[] = { + { + .compatible = "ti,j7200-pcie-host", + .data = (ulong)&j7200_pcie_rc_data, + }, + {}, +}; + +U_BOOT_DRIVER(pcie_cdns_ti) = { + .name = "pcie_cdns_ti", + .id = UCLASS_PCI, + .of_match = pcie_cdns_ti_ids, + .ops = &pcie_cdns_ti_ops, + .of_to_plat = pcie_cdns_ti_of_to_plat, + .probe = pcie_cdns_ti_probe, + .priv_auto = sizeof(struct pcie_cdns_ti), +}; diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig index 562c1a3b122..bbcbcee4c35 100644 --- a/drivers/power/pmic/Kconfig +++ b/drivers/power/pmic/Kconfig @@ -394,6 +394,7 @@ config SPL_PMIC_LP87565 config PMIC_TPS65941 bool "Enable driver for Texas Instruments TPS65941 PMIC" + depends on DM_PMIC help The TPS65941 is a PMIC containing a bunch of SMPS & LDOs. This driver binds the pmic children. diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c index 9feaa1eceec..a08678dde4e 100644 --- a/drivers/serial/serial-uclass.c +++ b/drivers/serial/serial-uclass.c @@ -18,6 +18,7 @@ #include <dm/lists.h> #include <dm/device-internal.h> #include <dm/of_access.h> +#include <linux/build_bug.h> #include <linux/delay.h> DECLARE_GLOBAL_DATA_PTR; @@ -328,11 +329,15 @@ static int __serial_tstc(struct udevice *dev) static int _serial_tstc(struct udevice *dev) { struct serial_dev_priv *upriv = dev_get_uclass_priv(dev); + uint wr, avail; - /* Read all available chars into the RX buffer */ - while (__serial_tstc(dev)) { - upriv->buf[upriv->wr_ptr++] = __serial_getc(dev); - upriv->wr_ptr %= CONFIG_SERIAL_RX_BUFFER_SIZE; + BUILD_BUG_ON_NOT_POWER_OF_2(CONFIG_SERIAL_RX_BUFFER_SIZE); + + /* Read all available chars into the RX buffer while there's room */ + avail = CONFIG_SERIAL_RX_BUFFER_SIZE - (upriv->wr_ptr - upriv->rd_ptr); + while (avail-- && __serial_tstc(dev)) { + wr = upriv->wr_ptr++ % CONFIG_SERIAL_RX_BUFFER_SIZE; + upriv->buf[wr] = __serial_getc(dev); } return upriv->rd_ptr != upriv->wr_ptr ? 1 : 0; @@ -342,12 +347,13 @@ static int _serial_getc(struct udevice *dev) { struct serial_dev_priv *upriv = dev_get_uclass_priv(dev); char val; + uint rd; if (upriv->rd_ptr == upriv->wr_ptr) return __serial_getc(dev); - val = upriv->buf[upriv->rd_ptr++]; - upriv->rd_ptr %= CONFIG_SERIAL_RX_BUFFER_SIZE; + rd = upriv->rd_ptr++ % CONFIG_SERIAL_RX_BUFFER_SIZE; + val = upriv->buf[rd]; return val; } @@ -582,11 +588,6 @@ static int serial_post_probe(struct udevice *dev) sdev.getc = serial_stub_getc; sdev.tstc = serial_stub_tstc; -#if CONFIG_IS_ENABLED(SERIAL_RX_BUFFER) - /* Allocate the RX buffer */ - upriv->buf = malloc(CONFIG_SERIAL_RX_BUFFER_SIZE); -#endif - stdio_register_dev(&sdev, &upriv->sdev); #endif return 0; diff --git a/drivers/timer/tsc_timer.c b/drivers/timer/tsc_timer.c index 80c084f380d..dd16ab320b2 100644 --- a/drivers/timer/tsc_timer.c +++ b/drivers/timer/tsc_timer.c @@ -83,7 +83,7 @@ static unsigned long cpu_mhz_from_cpuid(void) if (cpuid_eax(0) < 0x16) return 0; - return cpuid_eax(0x16); + return cpuid_eax(0x15); } /* @@ -299,10 +299,19 @@ static unsigned long __maybe_unused quick_pit_calibrate(void) if (!pit_expect_msb(0xff-i, &delta, &d2)) break; + delta -= tsc; + + /* + * Extrapolate the error and fail fast if the error will + * never be below 500 ppm. + */ + if (i == 1 && + d1 + d2 >= (delta * MAX_QUICK_PIT_ITERATIONS) >> 11) + return 0; + /* * Iterate until the error is less than 500 ppm */ - delta -= tsc; if (d1+d2 >= delta >> 11) continue; @@ -403,6 +412,10 @@ static void tsc_timer_ensure_setup(bool early) if (!gd->arch.clock_rate) { unsigned long fast_calibrate; + /* deal with this being called before x86_cpu_init_f() */ + if (!gd->arch.x86_vendor) + x86_get_identity_for_timer(); + /** * There is no obvious way to obtain this information from EFI * boot services. This value was measured on a Framework Laptop @@ -438,6 +451,7 @@ static void tsc_timer_ensure_setup(bool early) return; done: + fast_calibrate = min(fast_calibrate, 4000UL); if (!gd->arch.clock_rate) gd->arch.clock_rate = fast_calibrate * 1000000; } diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig index 311aaa7e67f..960b6a906ac 100644 --- a/drivers/usb/Kconfig +++ b/drivers/usb/Kconfig @@ -85,6 +85,8 @@ source "drivers/usb/emul/Kconfig" source "drivers/usb/phy/Kconfig" +source "drivers/usb/tcpm/Kconfig" + source "drivers/usb/ulpi/Kconfig" if USB_HOST diff --git a/drivers/usb/cdns3/gadget.c b/drivers/usb/cdns3/gadget.c index ac7e469469a..a30c40ef80e 100644 --- a/drivers/usb/cdns3/gadget.c +++ b/drivers/usb/cdns3/gadget.c @@ -1637,6 +1637,14 @@ void cdns3_ep_config(struct cdns3_endpoint *priv_ep) else priv_ep->trb_burst_size = 16; + /* + * The Endpoint is configured to handle a maximum packet size of + * max_packet_size. Hence, set priv_ep->endpoint.maxpacket to + * max_packet_size. This is necessary to ensure that the TD_SIZE + * is calculated correctly in cdns3_ep_run_transfer(). + */ + priv_ep->endpoint.maxpacket = max_packet_size; + ret = cdns3_ep_onchip_buffer_reserve(priv_dev, buffering + 1, !!priv_ep->dir); if (ret) { diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index 7374ce950da..b572ea340c8 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -670,6 +670,7 @@ struct dwc3_scratchpad_array { * @ep0_trb: dma address of ep0_trb * @ep0_usb_req: dummy req used while handling STD USB requests * @ep0_bounce_addr: dma address of ep0_bounce + * @setup_buf_addr: dma address of setup_buf * @scratch_addr: dma address of scratchbuf * @lock: for synchronizing * @dev: pointer to our struct device @@ -757,6 +758,7 @@ struct dwc3 { dma_addr_t ep0_trb_addr; dma_addr_t ep0_bounce_addr; dma_addr_t scratch_addr; + dma_addr_t setup_buf_addr; struct dwc3_request ep0_usb_req; /* device lock */ diff --git a/drivers/usb/dwc3/ep0.c b/drivers/usb/dwc3/ep0.c index 24f516a131b..531f0b522af 100644 --- a/drivers/usb/dwc3/ep0.c +++ b/drivers/usb/dwc3/ep0.c @@ -380,7 +380,7 @@ static int dwc3_ep0_handle_status(struct dwc3 *dwc, dep = dwc->eps[0]; dwc->ep0_usb_req.dep = dep; dwc->ep0_usb_req.request.length = sizeof(*response_pkt); - dwc->ep0_usb_req.request.buf = dwc->setup_buf; + dwc->ep0_usb_req.request.buf = (void *)dwc->setup_buf_addr; dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl; return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req); @@ -662,7 +662,7 @@ static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) dep = dwc->eps[0]; dwc->ep0_usb_req.dep = dep; dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket; - dwc->ep0_usb_req.request.buf = dwc->setup_buf; + dwc->ep0_usb_req.request.buf = (void *)dwc->setup_buf_addr; dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl; return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req); @@ -742,6 +742,8 @@ static void dwc3_ep0_inspect_setup(struct dwc3 *dwc, if (!dwc->gadget_driver) goto out; + dwc3_invalidate_cache((uintptr_t)ctrl, sizeof(*ctrl)); + len = le16_to_cpu(ctrl->wLength); if (!len) { dwc->three_stage_setup = false; diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c index fe33e307d3e..e5a383407a2 100644 --- a/drivers/usb/dwc3/gadget.c +++ b/drivers/usb/dwc3/gadget.c @@ -2534,6 +2534,8 @@ static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf) while (left > 0) { union dwc3_event event; + dwc3_invalidate_cache((uintptr_t)evt->buf, evt->length); + event.raw = *(u32 *) (evt->buf + evt->lpos); dwc3_process_event_entry(dwc, &event); @@ -2653,8 +2655,8 @@ int dwc3_gadget_init(struct dwc3 *dwc) goto err1; } - dwc->setup_buf = memalign(CONFIG_SYS_CACHELINE_SIZE, - DWC3_EP0_BOUNCE_SIZE); + dwc->setup_buf = dma_alloc_coherent(DWC3_EP0_BOUNCE_SIZE, + (unsigned long *)&dwc->setup_buf_addr); if (!dwc->setup_buf) { ret = -ENOMEM; goto err2; @@ -2701,7 +2703,7 @@ err4: dma_free_coherent(dwc->ep0_bounce); err3: - kfree(dwc->setup_buf); + dma_free_coherent(dwc->setup_buf); err2: dma_free_coherent(dwc->ep0_trb); @@ -2723,7 +2725,7 @@ void dwc3_gadget_exit(struct dwc3 *dwc) dma_free_coherent(dwc->ep0_bounce); - kfree(dwc->setup_buf); + dma_free_coherent(dwc->setup_buf); dma_free_coherent(dwc->ep0_trb); diff --git a/drivers/usb/dwc3/io.h b/drivers/usb/dwc3/io.h index 04791d4c9be..c1ab0288142 100644 --- a/drivers/usb/dwc3/io.h +++ b/drivers/usb/dwc3/io.h @@ -50,6 +50,17 @@ static inline void dwc3_writel(void __iomem *base, u32 offset, u32 value) static inline void dwc3_flush_cache(uintptr_t addr, int length) { - flush_dcache_range(addr, addr + ROUND(length, CACHELINE_SIZE)); + uintptr_t start_addr = (uintptr_t)addr & ~(CACHELINE_SIZE - 1); + uintptr_t end_addr = ALIGN((uintptr_t)addr + length, CACHELINE_SIZE); + + flush_dcache_range((unsigned long)start_addr, (unsigned long)end_addr); +} + +static inline void dwc3_invalidate_cache(uintptr_t addr, int length) +{ + uintptr_t start_addr = (uintptr_t)addr & ~(CACHELINE_SIZE - 1); + uintptr_t end_addr = ALIGN((uintptr_t)addr + length, CACHELINE_SIZE); + + invalidate_dcache_range((unsigned long)start_addr, (unsigned long)end_addr); } #endif /* __DRIVERS_USB_DWC3_IO_H */ diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig index 1694ad03183..010084ef7f3 100644 --- a/drivers/usb/gadget/Kconfig +++ b/drivers/usb/gadget/Kconfig @@ -233,7 +233,7 @@ endif # USB_GADGET_DOWNLOAD config USB_ETHER bool "USB Ethernet Gadget" - depends on NET + depends on NET || NET_LWIP default y if ARCH_SUNXI && USB_MUSB_GADGET help Creates an Ethernet network device through a USB peripheral diff --git a/drivers/usb/tcpm/Kconfig b/drivers/usb/tcpm/Kconfig new file mode 100644 index 00000000000..9be4b496e82 --- /dev/null +++ b/drivers/usb/tcpm/Kconfig @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0 + +config TYPEC_TCPM + tristate "USB Type-C Port Controller Manager" + depends on DM + help + The Type-C Port Controller Manager provides a USB PD and USB Type-C + state machine for use with Type-C Port Controllers. + +config TYPEC_FUSB302 + tristate "Fairchild FUSB302 Type-C chip driver" + depends on DM && DM_I2C && TYPEC_TCPM + help + The Fairchild FUSB302 Type-C chip driver that works with + Type-C Port Controller Manager to provide USB PD and USB + Type-C functionalities. diff --git a/drivers/usb/tcpm/Makefile b/drivers/usb/tcpm/Makefile new file mode 100644 index 00000000000..668d33155bf --- /dev/null +++ b/drivers/usb/tcpm/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-$(CONFIG_TYPEC_TCPM) += tcpm.o tcpm-uclass.o +obj-$(CONFIG_TYPEC_FUSB302) += fusb302.o diff --git a/drivers/usb/tcpm/fusb302.c b/drivers/usb/tcpm/fusb302.c new file mode 100644 index 00000000000..fe93ff3d339 --- /dev/null +++ b/drivers/usb/tcpm/fusb302.c @@ -0,0 +1,1323 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2016-2017 Google, Inc + * + * Fairchild FUSB302 Type-C Chip Driver + */ + +#include <dm.h> +#include <i2c.h> +#include <asm/gpio.h> +#include <linux/delay.h> +#include <linux/err.h> +#include <dm/device_compat.h> +#include <usb/tcpm.h> +#include "fusb302_reg.h" + +#define FUSB302_MAX_MSG_LEN 0x1F + +enum toggling_mode { + TOGGLING_MODE_OFF, + TOGGLING_MODE_DRP, + TOGGLING_MODE_SNK, + TOGGLING_MODE_SRC, +}; + +enum src_current_status { + SRC_CURRENT_DEFAULT, + SRC_CURRENT_MEDIUM, + SRC_CURRENT_HIGH, +}; + +static const u8 ra_mda_value[] = { + [SRC_CURRENT_DEFAULT] = 4, /* 210mV */ + [SRC_CURRENT_MEDIUM] = 9, /* 420mV */ + [SRC_CURRENT_HIGH] = 18, /* 798mV */ +}; + +static const u8 rd_mda_value[] = { + [SRC_CURRENT_DEFAULT] = 38, /* 1638mV */ + [SRC_CURRENT_MEDIUM] = 38, /* 1638mV */ + [SRC_CURRENT_HIGH] = 61, /* 2604mV */ +}; + +struct fusb302_chip { + enum toggling_mode toggling_mode; + enum src_current_status src_current_status; + bool intr_togdone; + bool intr_bc_lvl; + bool intr_comp_chng; + + /* port status */ + bool vconn_on; + bool vbus_present; + enum typec_cc_polarity cc_polarity; + enum typec_cc_status cc1; + enum typec_cc_status cc2; +}; + +static int fusb302_i2c_write(struct udevice *dev, u8 address, u8 data) +{ + int ret; + + ret = dm_i2c_write(dev, address, &data, 1); + if (ret) + dev_err(dev, "cannot write 0x%02x to 0x%02x, ret=%d\n", + data, address, ret); + + return ret; +} + +static int fusb302_i2c_block_write(struct udevice *dev, u8 address, + u8 length, const u8 *data) +{ + int ret; + + if (!length) + return 0; + + ret = dm_i2c_write(dev, address, data, length); + if (ret) + dev_err(dev, "cannot block write 0x%02x, len=%d, ret=%d\n", + address, length, ret); + + return ret; +} + +static int fusb302_i2c_read(struct udevice *dev, u8 address, u8 *data) +{ + int ret, retries; + + for (retries = 0; retries < 3; retries++) { + ret = dm_i2c_read(dev, address, data, 1); + if (ret == 0) + return ret; + dev_err(dev, "cannot read %02x, ret=%d\n", address, ret); + } + + return ret; +} + +static int fusb302_i2c_block_read(struct udevice *dev, u8 address, + u8 length, u8 *data) +{ + int ret; + + if (!length) + return 0; + + ret = dm_i2c_read(dev, address, data, length); + if (ret) + dev_err(dev, "cannot block read 0x%02x, len=%d, ret=%d\n", + address, length, ret); + return ret; +} + +static int fusb302_i2c_mask_write(struct udevice *dev, u8 address, + u8 mask, u8 value) +{ + int ret; + u8 data; + + ret = fusb302_i2c_read(dev, address, &data); + if (ret) + return ret; + data &= ~mask; + data |= value; + ret = fusb302_i2c_write(dev, address, data); + if (ret) + return ret; + + return ret; +} + +static int fusb302_i2c_set_bits(struct udevice *dev, u8 address, u8 set_bits) +{ + return fusb302_i2c_mask_write(dev, address, 0x00, set_bits); +} + +static int fusb302_i2c_clear_bits(struct udevice *dev, u8 address, u8 clear_bits) +{ + return fusb302_i2c_mask_write(dev, address, clear_bits, 0x00); +} + +static int fusb302_sw_reset(struct udevice *dev) +{ + int ret = fusb302_i2c_write(dev, FUSB_REG_RESET, FUSB_REG_RESET_SW_RESET); + + if (ret) + dev_err(dev, "cannot sw reset the fusb302: %d\n", ret); + + return ret; +} + +static int fusb302_enable_tx_auto_retries(struct udevice *dev, u8 retry_count) +{ + int ret; + + ret = fusb302_i2c_set_bits(dev, FUSB_REG_CONTROL3, retry_count | + FUSB_REG_CONTROL3_AUTO_RETRY); + + return ret; +} + +/* + * mask all interrupt on the chip + */ +static int fusb302_mask_interrupt(struct udevice *dev) +{ + int ret; + + ret = fusb302_i2c_write(dev, FUSB_REG_MASK, 0xFF); + if (ret) + return ret; + ret = fusb302_i2c_write(dev, FUSB_REG_MASKA, 0xFF); + if (ret) + return ret; + ret = fusb302_i2c_write(dev, FUSB_REG_MASKB, 0xFF); + if (ret) + return ret; + ret = fusb302_i2c_set_bits(dev, FUSB_REG_CONTROL0, + FUSB_REG_CONTROL0_INT_MASK); + return ret; +} + +/* + * initialize interrupt on the chip + * - unmasked interrupt: VBUS_OK + */ +static int fusb302_init_interrupt(struct udevice *dev) +{ + int ret; + + ret = fusb302_i2c_write(dev, FUSB_REG_MASK, + 0xFF & ~FUSB_REG_MASK_VBUSOK); + if (ret) + return ret; + ret = fusb302_i2c_write(dev, FUSB_REG_MASKA, 0xFF); + if (ret) + return ret; + ret = fusb302_i2c_write(dev, FUSB_REG_MASKB, 0xFF); + if (ret) + return ret; + ret = fusb302_i2c_clear_bits(dev, FUSB_REG_CONTROL0, + FUSB_REG_CONTROL0_INT_MASK); + return ret; +} + +static int fusb302_set_power_mode(struct udevice *dev, u8 power_mode) +{ + int ret; + + ret = fusb302_i2c_write(dev, FUSB_REG_POWER, power_mode); + + return ret; +} + +static int fusb302_init(struct udevice *dev) +{ + struct fusb302_chip *chip = dev_get_priv(dev); + int ret; + u8 data; + + ret = fusb302_sw_reset(dev); + if (ret) + return ret; + ret = fusb302_enable_tx_auto_retries(dev, FUSB_REG_CONTROL3_N_RETRIES_3); + if (ret) + return ret; + ret = fusb302_init_interrupt(dev); + if (ret) + return ret; + ret = fusb302_set_power_mode(dev, FUSB_REG_POWER_PWR_ALL); + if (ret) + return ret; + ret = fusb302_i2c_read(dev, FUSB_REG_STATUS0, &data); + if (ret) + return ret; + chip->vbus_present = !!(data & FUSB_REG_STATUS0_VBUSOK); + ret = fusb302_i2c_read(dev, FUSB_REG_DEVICE_ID, &data); + if (ret) + return ret; + dev_info(dev, "fusb302 device ID: 0x%02x\n", data); + + return ret; +} + +static int fusb302_get_vbus(struct udevice *dev) +{ + struct fusb302_chip *chip = dev_get_priv(dev); + + return chip->vbus_present ? 1 : 0; +} + +static int fusb302_set_src_current(struct udevice *dev, + enum src_current_status status) +{ + struct fusb302_chip *chip = dev_get_priv(dev); + int ret; + + chip->src_current_status = status; + switch (status) { + case SRC_CURRENT_DEFAULT: + ret = fusb302_i2c_mask_write(dev, FUSB_REG_CONTROL0, + FUSB_REG_CONTROL0_HOST_CUR_MASK, + FUSB_REG_CONTROL0_HOST_CUR_DEF); + break; + case SRC_CURRENT_MEDIUM: + ret = fusb302_i2c_mask_write(dev, FUSB_REG_CONTROL0, + FUSB_REG_CONTROL0_HOST_CUR_MASK, + FUSB_REG_CONTROL0_HOST_CUR_MED); + break; + case SRC_CURRENT_HIGH: + ret = fusb302_i2c_mask_write(dev, FUSB_REG_CONTROL0, + FUSB_REG_CONTROL0_HOST_CUR_MASK, + FUSB_REG_CONTROL0_HOST_CUR_HIGH); + break; + default: + ret = -EINVAL; + break; + } + + return ret; +} + +static int fusb302_set_toggling(struct udevice *dev, + enum toggling_mode mode) +{ + struct fusb302_chip *chip = dev_get_priv(dev); + int ret; + + /* first disable toggling */ + ret = fusb302_i2c_clear_bits(dev, FUSB_REG_CONTROL2, + FUSB_REG_CONTROL2_TOGGLE); + if (ret) + return ret; + /* mask interrupts for SRC or SNK */ + ret = fusb302_i2c_set_bits(dev, FUSB_REG_MASK, + FUSB_REG_MASK_BC_LVL | + FUSB_REG_MASK_COMP_CHNG); + if (ret) + return ret; + chip->intr_bc_lvl = false; + chip->intr_comp_chng = false; + /* configure toggling mode: none/snk/src/drp */ + switch (mode) { + case TOGGLING_MODE_OFF: + ret = fusb302_i2c_mask_write(dev, FUSB_REG_CONTROL2, + FUSB_REG_CONTROL2_MODE_MASK, + FUSB_REG_CONTROL2_MODE_NONE); + break; + case TOGGLING_MODE_SNK: + ret = fusb302_i2c_mask_write(dev, FUSB_REG_CONTROL2, + FUSB_REG_CONTROL2_MODE_MASK, + FUSB_REG_CONTROL2_MODE_UFP); + break; + case TOGGLING_MODE_SRC: + ret = fusb302_i2c_mask_write(dev, FUSB_REG_CONTROL2, + FUSB_REG_CONTROL2_MODE_MASK, + FUSB_REG_CONTROL2_MODE_DFP); + break; + case TOGGLING_MODE_DRP: + ret = fusb302_i2c_mask_write(dev, FUSB_REG_CONTROL2, + FUSB_REG_CONTROL2_MODE_MASK, + FUSB_REG_CONTROL2_MODE_DRP); + break; + default: + break; + } + + if (ret) + return ret; + + if (mode == TOGGLING_MODE_OFF) { + /* mask TOGDONE interrupt */ + ret = fusb302_i2c_set_bits(dev, FUSB_REG_MASKA, + FUSB_REG_MASKA_TOGDONE); + if (ret) + return ret; + chip->intr_togdone = false; + } else { + /* Datasheet says vconn MUST be off when toggling */ + if (chip->vconn_on) + dev_warn(dev, "Vconn is on during toggle start\n"); + /* unmask TOGDONE interrupt */ + ret = fusb302_i2c_clear_bits(dev, FUSB_REG_MASKA, + FUSB_REG_MASKA_TOGDONE); + if (ret) + return ret; + chip->intr_togdone = true; + /* start toggling */ + ret = fusb302_i2c_set_bits(dev, FUSB_REG_CONTROL2, + FUSB_REG_CONTROL2_TOGGLE); + if (ret) + return ret; + /* during toggling, consider cc as Open */ + chip->cc1 = TYPEC_CC_OPEN; + chip->cc2 = TYPEC_CC_OPEN; + } + chip->toggling_mode = mode; + + return ret; +} + +static const enum src_current_status cc_src_current[] = { + [TYPEC_CC_OPEN] = SRC_CURRENT_DEFAULT, + [TYPEC_CC_RA] = SRC_CURRENT_DEFAULT, + [TYPEC_CC_RD] = SRC_CURRENT_DEFAULT, + [TYPEC_CC_RP_DEF] = SRC_CURRENT_DEFAULT, + [TYPEC_CC_RP_1_5] = SRC_CURRENT_MEDIUM, + [TYPEC_CC_RP_3_0] = SRC_CURRENT_HIGH, +}; + +static int fusb302_set_cc(struct udevice *dev, enum typec_cc_status cc) +{ + struct fusb302_chip *chip = dev_get_priv(dev); + const u8 switches0_mask = FUSB_REG_SWITCHES0_CC1_PU_EN | + FUSB_REG_SWITCHES0_CC2_PU_EN | + FUSB_REG_SWITCHES0_CC1_PD_EN | + FUSB_REG_SWITCHES0_CC2_PD_EN; + u8 rd_mda, switches0_data = 0x00; + int ret; + + switch (cc) { + case TYPEC_CC_OPEN: + break; + case TYPEC_CC_RD: + switches0_data |= FUSB_REG_SWITCHES0_CC1_PD_EN | + FUSB_REG_SWITCHES0_CC2_PD_EN; + break; + case TYPEC_CC_RP_DEF: + case TYPEC_CC_RP_1_5: + case TYPEC_CC_RP_3_0: + switches0_data |= (chip->cc_polarity == TYPEC_POLARITY_CC1) ? + FUSB_REG_SWITCHES0_CC1_PU_EN : + FUSB_REG_SWITCHES0_CC2_PU_EN; + break; + default: + dev_err(dev, "unsupported CC value: %s\n", + typec_cc_status_name[cc]); + ret = -EINVAL; + goto done; + } + + ret = fusb302_set_toggling(dev, TOGGLING_MODE_OFF); + if (ret) { + dev_err(dev, "cannot set toggling mode: %d\n", ret); + goto done; + } + + ret = fusb302_i2c_mask_write(dev, FUSB_REG_SWITCHES0, + switches0_mask, switches0_data); + if (ret) { + dev_err(dev, "cannot set pull-up/-down: %d\n", ret); + goto done; + } + /* reset the cc status */ + chip->cc1 = TYPEC_CC_OPEN; + chip->cc2 = TYPEC_CC_OPEN; + + /* adjust current for SRC */ + ret = fusb302_set_src_current(dev, cc_src_current[cc]); + if (ret) { + dev_err(dev, "cannot set src current %s: %d\n", + typec_cc_status_name[cc], ret); + goto done; + } + + /* enable/disable interrupts, BC_LVL for SNK and COMP_CHNG for SRC */ + switch (cc) { + case TYPEC_CC_RP_DEF: + case TYPEC_CC_RP_1_5: + case TYPEC_CC_RP_3_0: + rd_mda = rd_mda_value[cc_src_current[cc]]; + ret = fusb302_i2c_write(dev, FUSB_REG_MEASURE, rd_mda); + if (ret) { + dev_err(dev, "cannot set SRC measure value: %d\n", ret); + goto done; + } + ret = fusb302_i2c_mask_write(dev, FUSB_REG_MASK, + FUSB_REG_MASK_BC_LVL | + FUSB_REG_MASK_COMP_CHNG, + FUSB_REG_MASK_BC_LVL); + if (ret) { + dev_err(dev, "cannot set SRC irq: %d\n", ret); + goto done; + } + chip->intr_comp_chng = true; + break; + case TYPEC_CC_RD: + ret = fusb302_i2c_mask_write(dev, FUSB_REG_MASK, + FUSB_REG_MASK_BC_LVL | + FUSB_REG_MASK_COMP_CHNG, + FUSB_REG_MASK_COMP_CHNG); + if (ret) { + dev_err(dev, "cannot set SRC irq: %d\n", ret); + goto done; + } + chip->intr_bc_lvl = true; + break; + default: + break; + } +done: + return ret; +} + +static int fusb302_get_cc(struct udevice *dev, enum typec_cc_status *cc1, + enum typec_cc_status *cc2) +{ + struct fusb302_chip *chip = dev_get_priv(dev); + + *cc1 = chip->cc1; + *cc2 = chip->cc2; + dev_dbg(dev, "get cc1 = %s, cc2 = %s\n", typec_cc_status_name[*cc1], + typec_cc_status_name[*cc2]); + + return 0; +} + +static int fusb302_set_vconn(struct udevice *dev, bool on) +{ + struct fusb302_chip *chip = dev_get_priv(dev); + int ret; + u8 switches0_data = 0x00; + u8 switches0_mask = FUSB_REG_SWITCHES0_VCONN_CC1 | + FUSB_REG_SWITCHES0_VCONN_CC2; + + if (chip->vconn_on == on) { + ret = 0; + dev_dbg(dev, "vconn is already %s\n", on ? "on" : "off"); + goto done; + } + if (on) { + switches0_data = (chip->cc_polarity == TYPEC_POLARITY_CC1) ? + FUSB_REG_SWITCHES0_VCONN_CC2 : + FUSB_REG_SWITCHES0_VCONN_CC1; + } + ret = fusb302_i2c_mask_write(dev, FUSB_REG_SWITCHES0, + switches0_mask, switches0_data); + if (ret) + goto done; + dev_dbg(dev, "set vconn = %s\n", on ? "on" : "off"); +done: + return ret; +} + +static int fusb302_set_vbus(struct udevice *dev, bool on, bool charge) +{ + return 0; +} + +static int fusb302_pd_tx_flush(struct udevice *dev) +{ + return fusb302_i2c_set_bits(dev, FUSB_REG_CONTROL0, + FUSB_REG_CONTROL0_TX_FLUSH); +} + +static int fusb302_pd_rx_flush(struct udevice *dev) +{ + return fusb302_i2c_set_bits(dev, FUSB_REG_CONTROL1, + FUSB_REG_CONTROL1_RX_FLUSH); +} + +static int fusb302_pd_set_auto_goodcrc(struct udevice *dev, bool on) +{ + if (on) + return fusb302_i2c_set_bits(dev, FUSB_REG_SWITCHES1, + FUSB_REG_SWITCHES1_AUTO_GCRC); + return fusb302_i2c_clear_bits(dev, FUSB_REG_SWITCHES1, + FUSB_REG_SWITCHES1_AUTO_GCRC); +} + +static int fusb302_pd_set_interrupts(struct udevice *dev, bool on) +{ + int ret; + u8 mask_interrupts = FUSB_REG_MASK_COLLISION; + u8 maska_interrupts = FUSB_REG_MASKA_RETRYFAIL | + FUSB_REG_MASKA_HARDSENT | + FUSB_REG_MASKA_TX_SUCCESS | + FUSB_REG_MASKA_HARDRESET; + u8 maskb_interrupts = FUSB_REG_MASKB_GCRCSENT; + + ret = on ? + fusb302_i2c_clear_bits(dev, FUSB_REG_MASK, mask_interrupts) : + fusb302_i2c_set_bits(dev, FUSB_REG_MASK, mask_interrupts); + if (ret) + return ret; + ret = on ? + fusb302_i2c_clear_bits(dev, FUSB_REG_MASKA, maska_interrupts) : + fusb302_i2c_set_bits(dev, FUSB_REG_MASKA, maska_interrupts); + if (ret) + return ret; + ret = on ? + fusb302_i2c_clear_bits(dev, FUSB_REG_MASKB, maskb_interrupts) : + fusb302_i2c_set_bits(dev, FUSB_REG_MASKB, maskb_interrupts); + return ret; +} + +static int fusb302_set_pd_rx(struct udevice *dev, bool on) +{ + int ret; + + ret = fusb302_pd_rx_flush(dev); + if (ret) { + dev_err(dev, "cannot flush pd rx buffer: %d\n", ret); + goto done; + } + ret = fusb302_pd_tx_flush(dev); + if (ret) { + dev_err(dev, "cannot flush pd tx buffer: %d\n", ret); + goto done; + } + ret = fusb302_pd_set_auto_goodcrc(dev, on); + if (ret) { + dev_err(dev, "cannot turn %s auto GoodCRC: %d\n", + on ? "on" : "off", ret); + goto done; + } + ret = fusb302_pd_set_interrupts(dev, on); + if (ret) { + dev_err(dev, "cannot turn %s pd interrupts: %d\n", + on ? "on" : "off", ret); + goto done; + } + dev_dbg(dev, "set pd RX %s\n", on ? "on" : "off"); +done: + return ret; +} + +static int fusb302_set_roles(struct udevice *dev, bool attached, + enum typec_role pwr, enum typec_data_role data) +{ + int ret; + u8 switches1_mask = FUSB_REG_SWITCHES1_POWERROLE | + FUSB_REG_SWITCHES1_DATAROLE; + u8 switches1_data = 0x00; + + if (pwr == TYPEC_SOURCE) + switches1_data |= FUSB_REG_SWITCHES1_POWERROLE; + if (data == TYPEC_HOST) + switches1_data |= FUSB_REG_SWITCHES1_DATAROLE; + ret = fusb302_i2c_mask_write(dev, FUSB_REG_SWITCHES1, + switches1_mask, switches1_data); + if (ret) { + dev_err(dev, "unable to set pd header %s, %s, ret=%d\n", + typec_role_name[pwr], typec_data_role_name[data], ret); + goto done; + } + dev_dbg(dev, "pd header : %s, %s\n", typec_role_name[pwr], + typec_data_role_name[data]); +done: + + return ret; +} + +static int fusb302_start_toggling(struct udevice *dev, + enum typec_port_type port_type, + enum typec_cc_status cc) +{ + enum toggling_mode mode = TOGGLING_MODE_OFF; + int ret; + + switch (port_type) { + case TYPEC_PORT_SRC: + mode = TOGGLING_MODE_SRC; + break; + case TYPEC_PORT_SNK: + mode = TOGGLING_MODE_SNK; + break; + case TYPEC_PORT_DRP: + mode = TOGGLING_MODE_DRP; + break; + } + + ret = fusb302_set_src_current(dev, cc_src_current[cc]); + if (ret) { + dev_err(dev, "unable to set src current %s, ret=%d", + typec_cc_status_name[cc], ret); + goto done; + } + ret = fusb302_set_toggling(dev, mode); + if (ret) { + dev_err(dev, "unable to start drp toggling: %d\n", ret); + goto done; + } + dev_info(dev, "fusb302 start drp toggling\n"); +done: + + return ret; +} + +static int fusb302_pd_send_message(struct udevice *dev, + const struct pd_message *msg) +{ + int ret; + /* SOP tokens */ + u8 buf[40] = {FUSB302_TKN_SYNC1, FUSB302_TKN_SYNC1, FUSB302_TKN_SYNC1, + FUSB302_TKN_SYNC2}; + u8 pos = 4; + int len; + + len = pd_header_cnt_le(msg->header) * 4; + /* plug 2 for header */ + len += 2; + if (len > FUSB302_MAX_MSG_LEN) { + dev_err(dev, "PD message too long %d (incl. header)", len); + return -EINVAL; + } + /* packsym tells the FUSB302 chip that the next X bytes are payload */ + buf[pos++] = FUSB302_TKN_PACKSYM | (len & FUSB302_MAX_MSG_LEN); + memcpy(&buf[pos], &msg->header, sizeof(msg->header)); + pos += sizeof(msg->header); + + len -= 2; + memcpy(&buf[pos], msg->payload, len); + pos += len; + + /* CRC */ + buf[pos++] = FUSB302_TKN_JAMCRC; + /* EOP */ + buf[pos++] = FUSB302_TKN_EOP; + /* turn tx off after sending message */ + buf[pos++] = FUSB302_TKN_TXOFF; + /* start transmission */ + buf[pos++] = FUSB302_TKN_TXON; + + ret = fusb302_i2c_block_write(dev, FUSB_REG_FIFOS, pos, buf); + if (ret) + return ret; + dev_dbg(dev, "Send PD message (header=0x%x len=%d)\n", msg->header, len); + + return ret; +} + +static int fusb302_pd_send_hardreset(struct udevice *dev) +{ + return fusb302_i2c_set_bits(dev, FUSB_REG_CONTROL3, + FUSB_REG_CONTROL3_SEND_HARDRESET); +} + +static const char * const transmit_type_name[] = { + [TCPC_TX_SOP] = "SOP", + [TCPC_TX_SOP_PRIME] = "SOP'", + [TCPC_TX_SOP_PRIME_PRIME] = "SOP''", + [TCPC_TX_SOP_DEBUG_PRIME] = "DEBUG'", + [TCPC_TX_SOP_DEBUG_PRIME_PRIME] = "DEBUG''", + [TCPC_TX_HARD_RESET] = "HARD_RESET", + [TCPC_TX_CABLE_RESET] = "CABLE_RESET", + [TCPC_TX_BIST_MODE_2] = "BIST_MODE_2", +}; + +static int fusb302_pd_transmit(struct udevice *dev, enum tcpm_transmit_type type, + const struct pd_message *msg, unsigned int negotiated_rev) +{ + int ret; + + switch (type) { + case TCPC_TX_SOP: + /* nRetryCount 3 in P2.0 spec, whereas 2 in PD3.0 spec */ + ret = fusb302_enable_tx_auto_retries(dev, negotiated_rev > PD_REV20 ? + FUSB_REG_CONTROL3_N_RETRIES_2 : + FUSB_REG_CONTROL3_N_RETRIES_3); + if (ret) + dev_err(dev, "cannot update retry count: %d\n", ret); + + ret = fusb302_pd_send_message(dev, msg); + if (ret) + dev_err(dev, "cannot send PD message: %d\n", ret); + break; + case TCPC_TX_HARD_RESET: + ret = fusb302_pd_send_hardreset(dev); + if (ret) + dev_err(dev, "cannot send hardreset: %d\n", ret); + break; + default: + dev_err(dev, "type %s not supported", transmit_type_name[type]); + ret = -EINVAL; + } + + return ret; +} + +static enum typec_cc_status fusb302_bc_lvl_to_cc(u8 bc_lvl) +{ + if (bc_lvl == FUSB_REG_STATUS0_BC_LVL_1230_MAX) + return TYPEC_CC_RP_3_0; + if (bc_lvl == FUSB_REG_STATUS0_BC_LVL_600_1230) + return TYPEC_CC_RP_1_5; + if (bc_lvl == FUSB_REG_STATUS0_BC_LVL_200_600) + return TYPEC_CC_RP_DEF; + return TYPEC_CC_OPEN; +} + +static void fusb302_bc_lvl_handler(struct udevice *dev) +{ + struct fusb302_chip *chip = dev_get_priv(dev); + enum typec_cc_status cc_status; + u8 status0, bc_lvl; + int ret; + + if (!chip->intr_bc_lvl) { + dev_err(dev, "BC_LVL interrupt is turned off, abort\n"); + goto done; + } + ret = fusb302_i2c_read(dev, FUSB_REG_STATUS0, &status0); + if (ret) + goto done; + + dev_dbg(dev, "BC_LVL handler, status0 = 0x%02x\n", status0); + if (status0 & FUSB_REG_STATUS0_ACTIVITY) + dev_info(dev, "CC activities detected, delay handling\n"); + bc_lvl = status0 & FUSB_REG_STATUS0_BC_LVL_MASK; + cc_status = fusb302_bc_lvl_to_cc(bc_lvl); + if (chip->cc_polarity == TYPEC_POLARITY_CC1) { + if (chip->cc1 != cc_status) { + dev_dbg(dev, "cc1: %s -> %s\n", + typec_cc_status_name[chip->cc1], + typec_cc_status_name[cc_status]); + chip->cc1 = cc_status; + tcpm_cc_change(dev); + } + } else { + if (chip->cc2 != cc_status) { + dev_dbg(dev, "cc2: %s -> %s\n", + typec_cc_status_name[chip->cc2], + typec_cc_status_name[cc_status]); + chip->cc2 = cc_status; + tcpm_cc_change(dev); + } + } + +done: + return; +} + +static int fusb302_enter_low_power_mode(struct udevice *dev, + bool attached, bool pd_capable) +{ + unsigned int reg; + int ret; + + ret = fusb302_mask_interrupt(dev); + if (ret) + return ret; + if (attached && pd_capable) + reg = FUSB_REG_POWER_PWR_MEDIUM; + else if (attached) + reg = FUSB_REG_POWER_PWR_LOW; + else + reg = 0; + + return fusb302_set_power_mode(dev, reg); +} + +static const char * const cc_polarity_name[] = { + [TYPEC_POLARITY_CC1] = "Polarity_CC1", + [TYPEC_POLARITY_CC2] = "Polarity_CC2", +}; + +static int fusb302_set_cc_polarity_and_pull(struct udevice *dev, + enum typec_cc_polarity cc_polarity, + bool pull_up, bool pull_down) +{ + struct fusb302_chip *chip = dev_get_priv(dev); + int ret; + u8 switches0_data = 0x00; + u8 switches1_mask = FUSB_REG_SWITCHES1_TXCC1_EN | + FUSB_REG_SWITCHES1_TXCC2_EN; + u8 switches1_data = 0x00; + + if (pull_down) + switches0_data |= FUSB_REG_SWITCHES0_CC1_PD_EN | + FUSB_REG_SWITCHES0_CC2_PD_EN; + + if (cc_polarity == TYPEC_POLARITY_CC1) { + switches0_data |= FUSB_REG_SWITCHES0_MEAS_CC1; + if (chip->vconn_on) + switches0_data |= FUSB_REG_SWITCHES0_VCONN_CC2; + if (pull_up) + switches0_data |= FUSB_REG_SWITCHES0_CC1_PU_EN; + switches1_data = FUSB_REG_SWITCHES1_TXCC1_EN; + } else { + switches0_data |= FUSB_REG_SWITCHES0_MEAS_CC2; + if (chip->vconn_on) + switches0_data |= FUSB_REG_SWITCHES0_VCONN_CC1; + if (pull_up) + switches0_data |= FUSB_REG_SWITCHES0_CC2_PU_EN; + switches1_data = FUSB_REG_SWITCHES1_TXCC2_EN; + } + ret = fusb302_i2c_write(dev, FUSB_REG_SWITCHES0, switches0_data); + if (ret) + return ret; + ret = fusb302_i2c_mask_write(dev, FUSB_REG_SWITCHES1, + switches1_mask, switches1_data); + if (ret) + return ret; + chip->cc_polarity = cc_polarity; + + return ret; +} + +static int fusb302_handle_togdone_snk(struct udevice *dev, + u8 togdone_result) +{ + struct fusb302_chip *chip = dev_get_priv(dev); + int ret; + u8 status0; + u8 bc_lvl; + enum typec_cc_polarity cc_polarity; + enum typec_cc_status cc_status_active, cc1, cc2; + + /* set polarity and pull_up, pull_down */ + cc_polarity = (togdone_result == FUSB_REG_STATUS1A_TOGSS_SNK1) ? + TYPEC_POLARITY_CC1 : TYPEC_POLARITY_CC2; + ret = fusb302_set_cc_polarity_and_pull(dev, cc_polarity, false, true); + if (ret) { + dev_err(dev, "cannot set cc polarity %s, ret = %d\n", + cc_polarity_name[cc_polarity], ret); + return ret; + } + /* fusb302_set_cc_polarity() has set the correct measure block */ + ret = fusb302_i2c_read(dev, FUSB_REG_STATUS0, &status0); + if (ret < 0) + return ret; + bc_lvl = status0 & FUSB_REG_STATUS0_BC_LVL_MASK; + cc_status_active = fusb302_bc_lvl_to_cc(bc_lvl); + /* restart toggling if the cc status on the active line is OPEN */ + if (cc_status_active == TYPEC_CC_OPEN) { + dev_info(dev, "restart toggling as CC_OPEN detected\n"); + ret = fusb302_set_toggling(dev, chip->toggling_mode); + return ret; + } + /* update tcpm with the new cc value */ + cc1 = (cc_polarity == TYPEC_POLARITY_CC1) ? + cc_status_active : TYPEC_CC_OPEN; + cc2 = (cc_polarity == TYPEC_POLARITY_CC2) ? + cc_status_active : TYPEC_CC_OPEN; + if (chip->cc1 != cc1 || chip->cc2 != cc2) { + chip->cc1 = cc1; + chip->cc2 = cc2; + tcpm_cc_change(dev); + } + /* turn off toggling */ + ret = fusb302_set_toggling(dev, TOGGLING_MODE_OFF); + if (ret) { + dev_err(dev, "cannot set toggling mode off, ret=%d\n", ret); + return ret; + } + /* unmask bc_lvl interrupt */ + ret = fusb302_i2c_clear_bits(dev, FUSB_REG_MASK, FUSB_REG_MASK_BC_LVL); + if (ret) { + dev_err(dev, "cannot unmask bc_lcl irq, ret=%d\n", ret); + return ret; + } + chip->intr_bc_lvl = true; + dev_dbg(dev, "detected cc1=%s, cc2=%s\n", + typec_cc_status_name[cc1], + typec_cc_status_name[cc2]); + + return ret; +} + +/* On error returns < 0, otherwise a typec_cc_status value */ +static int fusb302_get_src_cc_status(struct udevice *dev, + enum typec_cc_polarity cc_polarity, + enum typec_cc_status *cc) +{ + struct fusb302_chip *chip = dev_get_priv(dev); + u8 ra_mda = ra_mda_value[chip->src_current_status]; + u8 rd_mda = rd_mda_value[chip->src_current_status]; + u8 switches0_data, status0; + int ret; + + /* Step 1: Set switches so that we measure the right CC pin */ + switches0_data = (cc_polarity == TYPEC_POLARITY_CC1) ? + FUSB_REG_SWITCHES0_CC1_PU_EN | FUSB_REG_SWITCHES0_MEAS_CC1 : + FUSB_REG_SWITCHES0_CC2_PU_EN | FUSB_REG_SWITCHES0_MEAS_CC2; + ret = fusb302_i2c_write(dev, FUSB_REG_SWITCHES0, switches0_data); + if (ret < 0) + return ret; + + fusb302_i2c_read(dev, FUSB_REG_SWITCHES0, &status0); + dev_dbg(dev, "get_src_cc_status switches: 0x%0x", status0); + + /* Step 2: Set compararator volt to differentiate between Open and Rd */ + ret = fusb302_i2c_write(dev, FUSB_REG_MEASURE, rd_mda); + if (ret) + return ret; + + udelay(100); + ret = fusb302_i2c_read(dev, FUSB_REG_STATUS0, &status0); + if (ret) + return ret; + + dev_dbg(dev, "get_src_cc_status rd_mda status0: 0x%0x", status0); + if (status0 & FUSB_REG_STATUS0_COMP) { + *cc = TYPEC_CC_OPEN; + return 0; + } + + /* Step 3: Set compararator input to differentiate between Rd and Ra. */ + ret = fusb302_i2c_write(dev, FUSB_REG_MEASURE, ra_mda); + if (ret) + return ret; + + udelay(100); + ret = fusb302_i2c_read(dev, FUSB_REG_STATUS0, &status0); + if (ret) + return ret; + + dev_dbg(dev, "get_src_cc_status ra_mda status0: 0x%0x", status0); + if (status0 & FUSB_REG_STATUS0_COMP) + *cc = TYPEC_CC_RD; + else + *cc = TYPEC_CC_RA; + + return 0; +} + +static int fusb302_handle_togdone_src(struct udevice *dev, + u8 togdone_result) +{ + /* + * - set polarity (measure cc, vconn, tx) + * - set pull_up, pull_down + * - set cc1, cc2, and update to tcpm state machine + * - set I_COMP interrupt on + */ + struct fusb302_chip *chip = dev_get_priv(dev); + u8 rd_mda = rd_mda_value[chip->src_current_status]; + enum toggling_mode toggling_mode = chip->toggling_mode; + enum typec_cc_polarity cc_polarity; + enum typec_cc_status cc1, cc2; + int ret; + + /* + * The toggle-engine will stop in a src state if it sees either Ra or + * Rd. Determine the status for both CC pins, starting with the one + * where toggling stopped, as that is where the switches point now. + */ + if (togdone_result == FUSB_REG_STATUS1A_TOGSS_SRC1) + ret = fusb302_get_src_cc_status(dev, TYPEC_POLARITY_CC1, &cc1); + else + ret = fusb302_get_src_cc_status(dev, TYPEC_POLARITY_CC2, &cc2); + if (ret) + return ret; + /* we must turn off toggling before we can measure the other pin */ + ret = fusb302_set_toggling(dev, TOGGLING_MODE_OFF); + if (ret) { + dev_err(dev, "cannot set toggling mode off, ret=%d\n", ret); + return ret; + } + /* get the status of the other pin */ + if (togdone_result == FUSB_REG_STATUS1A_TOGSS_SRC1) + ret = fusb302_get_src_cc_status(dev, TYPEC_POLARITY_CC2, &cc2); + else + ret = fusb302_get_src_cc_status(dev, TYPEC_POLARITY_CC1, &cc1); + if (ret) + return ret; + + /* determine polarity based on the status of both pins */ + if (cc1 == TYPEC_CC_RD && (cc2 == TYPEC_CC_OPEN || cc2 == TYPEC_CC_RA)) { + cc_polarity = TYPEC_POLARITY_CC1; + } else if (cc2 == TYPEC_CC_RD && + (cc1 == TYPEC_CC_OPEN || cc1 == TYPEC_CC_RA)) { + cc_polarity = TYPEC_POLARITY_CC2; + } else { + dev_err(dev, "unexpected CC status cc1=%s, cc2=%s, restarting toggling\n", + typec_cc_status_name[cc1], + typec_cc_status_name[cc2]); + return fusb302_set_toggling(dev, toggling_mode); + } + /* set polarity and pull_up, pull_down */ + ret = fusb302_set_cc_polarity_and_pull(dev, cc_polarity, true, false); + if (ret < 0) { + dev_err(dev, "cannot set cc polarity %s, ret=%d\n", + cc_polarity_name[cc_polarity], ret); + return ret; + } + /* update tcpm with the new cc value */ + if (chip->cc1 != cc1 || chip->cc2 != cc2) { + chip->cc1 = cc1; + chip->cc2 = cc2; + tcpm_cc_change(dev); + } + /* set MDAC to Rd threshold, and unmask I_COMP for unplug detection */ + ret = fusb302_i2c_write(dev, FUSB_REG_MEASURE, rd_mda); + if (ret) + return ret; + /* unmask comp_chng interrupt */ + ret = fusb302_i2c_clear_bits(dev, FUSB_REG_MASK, + FUSB_REG_MASK_COMP_CHNG); + if (ret) { + dev_err(dev, "cannot unmask comp_chng irq, ret=%d\n", ret); + return ret; + } + chip->intr_comp_chng = true; + dev_dbg(dev, "detected cc1=%s, cc2=%s\n", + typec_cc_status_name[cc1], + typec_cc_status_name[cc2]); + + return ret; +} + +static int fusb302_handle_togdone(struct udevice *dev) +{ + struct fusb302_chip *chip = dev_get_priv(dev); + u8 togdone_result, status1a; + int ret; + + ret = fusb302_i2c_read(dev, FUSB_REG_STATUS1A, &status1a); + if (ret < 0) + return ret; + togdone_result = (status1a >> FUSB_REG_STATUS1A_TOGSS_POS) & + FUSB_REG_STATUS1A_TOGSS_MASK; + switch (togdone_result) { + case FUSB_REG_STATUS1A_TOGSS_SNK1: + case FUSB_REG_STATUS1A_TOGSS_SNK2: + return fusb302_handle_togdone_snk(dev, togdone_result); + case FUSB_REG_STATUS1A_TOGSS_SRC1: + case FUSB_REG_STATUS1A_TOGSS_SRC2: + return fusb302_handle_togdone_src(dev, togdone_result); + case FUSB_REG_STATUS1A_TOGSS_AA: + /* doesn't support */ + dev_err(dev, "AudioAccessory not supported\n"); + fusb302_set_toggling(dev, chip->toggling_mode); + break; + default: + dev_err(dev, "TOGDONE with an invalid state: %d\n", + togdone_result); + fusb302_set_toggling(dev, chip->toggling_mode); + break; + } + return ret; +} + +static int fusb302_pd_reset(struct udevice *dev) +{ + return fusb302_i2c_set_bits(dev, FUSB_REG_RESET, + FUSB_REG_RESET_PD_RESET); +} + +static int fusb302_pd_read_message(struct udevice *dev, + struct pd_message *msg) +{ + int len, ret; + u8 crc[4]; + u8 token; + + /* first SOP token */ + ret = fusb302_i2c_read(dev, FUSB_REG_FIFOS, &token); + if (ret) + return ret; + ret = fusb302_i2c_block_read(dev, FUSB_REG_FIFOS, 2, + (u8 *)&msg->header); + if (ret) + return ret; + len = pd_header_cnt_le(msg->header) * 4; + /* add 4 to length to include the CRC */ + if (len > PD_MAX_PAYLOAD * 4) { + dev_err(dev, "PD message too long %d\n", len); + return -EINVAL; + } + if (len > 0) { + ret = fusb302_i2c_block_read(dev, FUSB_REG_FIFOS, len, + (u8 *)msg->payload); + if (ret) + return ret; + } + /* another 4 bytes to read CRC out */ + ret = fusb302_i2c_block_read(dev, FUSB_REG_FIFOS, 4, crc); + if (ret) + return ret; + dev_dbg(dev, "Received PD message (header=0x%x len=%d)\n", msg->header, len); + + /* + * Check if we've read off a GoodCRC message. If so then indicate to + * TCPM that the previous transmission has completed. Otherwise we pass + * the received message over to TCPM for processing. + * + * We make this check here instead of basing the reporting decision on + * the IRQ event type, as it's possible for the chip to report the + * TX_SUCCESS and GCRCSENT events out of order on occasion, so we need + * to check the message type to ensure correct reporting to TCPM. + */ + if (!len && (pd_header_type_le(msg->header) == PD_CTRL_GOOD_CRC)) + tcpm_pd_transmit_complete(dev, TCPC_TX_SUCCESS); + else + tcpm_pd_receive(dev, msg); + + return ret; +} + +static void fusb302_interrupt_handle(struct udevice *dev) +{ + struct fusb302_chip *chip = dev_get_priv(dev); + u8 interrupt; + u8 interrupta; + u8 interruptb; + u8 status0; + bool vbus_present; + bool comp_result; + bool intr_togdone; + bool intr_bc_lvl; + bool intr_comp_chng; + struct pd_message pd_msg; + int ret; + + /* grab a snapshot of intr flags */ + intr_togdone = chip->intr_togdone; + intr_bc_lvl = chip->intr_bc_lvl; + intr_comp_chng = chip->intr_comp_chng; + + ret = fusb302_i2c_read(dev, FUSB_REG_INTERRUPT, &interrupt); + if (ret) + return; + ret = fusb302_i2c_read(dev, FUSB_REG_INTERRUPTA, &interrupta); + if (ret) + return; + ret = fusb302_i2c_read(dev, FUSB_REG_INTERRUPTB, &interruptb); + if (ret) + return; + ret = fusb302_i2c_read(dev, FUSB_REG_STATUS0, &status0); + if (ret) + return; + + /* + * Since we are polling the IRQs, avoid printing messages when there + * no interrupts at all to avoid spamming the log. + */ + if (interrupt != 0 || interrupta != 0 || interruptb != 0) + dev_dbg(dev, "IRQ: 0x%02x, a: 0x%02x, b: 0x%02x, status0: 0x%02x\n", + interrupt, interrupta, interruptb, status0); + + if (interrupt & FUSB_REG_INTERRUPT_VBUSOK) { + vbus_present = !!(status0 & FUSB_REG_STATUS0_VBUSOK); + dev_dbg(dev, "IRQ: VBUS_OK, vbus=%s\n", + vbus_present ? "On" : "Off"); + if (vbus_present != chip->vbus_present) { + chip->vbus_present = vbus_present; + tcpm_vbus_change(dev); + } + } + + if ((interrupta & FUSB_REG_INTERRUPTA_TOGDONE) && intr_togdone) { + dev_dbg(dev, "IRQ: TOGDONE\n"); + ret = fusb302_handle_togdone(dev); + if (ret) { + dev_err(dev, "handle togdone error: %d\n", ret); + return; + } + } + + if ((interrupt & FUSB_REG_INTERRUPT_BC_LVL) && intr_bc_lvl) { + dev_dbg(dev, "IRQ: BC_LVL, handler pending\n"); + fusb302_bc_lvl_handler(dev); + } + + if ((interrupt & FUSB_REG_INTERRUPT_COMP_CHNG) && intr_comp_chng) { + comp_result = !!(status0 & FUSB_REG_STATUS0_COMP); + dev_dbg(dev, "IRQ: COMP_CHNG, comp=%s\n", + comp_result ? "true" : "false"); + if (comp_result) { + /* cc level > Rd_threshold, detach */ + chip->cc1 = TYPEC_CC_OPEN; + chip->cc2 = TYPEC_CC_OPEN; + tcpm_cc_change(dev); + } + } + + if (interrupt & FUSB_REG_INTERRUPT_COLLISION) { + dev_dbg(dev, "IRQ: PD collision\n"); + tcpm_pd_transmit_complete(dev, TCPC_TX_FAILED); + } + + if (interrupta & FUSB_REG_INTERRUPTA_RETRYFAIL) { + dev_dbg(dev, "IRQ: PD retry failed\n"); + tcpm_pd_transmit_complete(dev, TCPC_TX_FAILED); + } + + if (interrupta & FUSB_REG_INTERRUPTA_HARDSENT) { + dev_dbg(dev, "IRQ: PD hardreset sent\n"); + ret = fusb302_pd_reset(dev); + if (ret) { + dev_err(dev, "cannot PD reset, ret=%d\n", ret); + return; + } + tcpm_pd_transmit_complete(dev, TCPC_TX_SUCCESS); + } + + if (interrupta & FUSB_REG_INTERRUPTA_TX_SUCCESS) { + dev_dbg(dev, "IRQ: PD tx success\n"); + ret = fusb302_pd_read_message(dev, &pd_msg); + if (ret) { + dev_err(dev, "cannot read in PD message, ret=%d\n", ret); + return; + } + } + + if (interrupta & FUSB_REG_INTERRUPTA_HARDRESET) { + dev_dbg(dev, "IRQ: PD received hardreset\n"); + ret = fusb302_pd_reset(dev); + if (ret) { + dev_err(dev, "cannot PD reset, ret=%d\n", ret); + return; + } + tcpm_pd_hard_reset(dev); + } + + if (interruptb & FUSB_REG_INTERRUPTB_GCRCSENT) { + dev_dbg(dev, "IRQ: PD sent good CRC\n"); + ret = fusb302_pd_read_message(dev, &pd_msg); + if (ret) { + dev_err(dev, "cannot read in PD message, ret=%d\n", ret); + return; + } + } +} + +static void fusb302_poll_event(struct udevice *dev) +{ + fusb302_interrupt_handle(dev); +} + +static int fusb302_get_connector_node(struct udevice *dev, ofnode *connector_node) +{ + *connector_node = dev_read_subnode(dev, "connector"); + if (!ofnode_valid(*connector_node)) { + dev_err(dev, "'connector' node is not found\n"); + return -ENODEV; + } + + return 0; +} + +static struct dm_tcpm_ops fusb302_ops = { + .get_connector_node = fusb302_get_connector_node, + .init = fusb302_init, + .get_vbus = fusb302_get_vbus, + .set_cc = fusb302_set_cc, + .get_cc = fusb302_get_cc, + .set_vconn = fusb302_set_vconn, + .set_vbus = fusb302_set_vbus, + .set_pd_rx = fusb302_set_pd_rx, + .set_roles = fusb302_set_roles, + .start_toggling = fusb302_start_toggling, + .pd_transmit = fusb302_pd_transmit, + .poll_event = fusb302_poll_event, + .enter_low_power_mode = fusb302_enter_low_power_mode, +}; + +static const struct udevice_id fusb302_ids[] = { + { .compatible = "fcs,fusb302" }, + { } +}; + +U_BOOT_DRIVER(fusb302) = { + .name = "fusb302", + .id = UCLASS_TCPM, + .of_match = fusb302_ids, + .ops = &fusb302_ops, + .priv_auto = sizeof(struct fusb302_chip), +}; diff --git a/drivers/usb/tcpm/fusb302_reg.h b/drivers/usb/tcpm/fusb302_reg.h new file mode 100644 index 00000000000..edc0e4b0f1e --- /dev/null +++ b/drivers/usb/tcpm/fusb302_reg.h @@ -0,0 +1,177 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2016-2017 Google, Inc + * + * Fairchild FUSB302 Type-C Chip Driver + */ + +#ifndef FUSB302_REG_H +#define FUSB302_REG_H + +#define FUSB_REG_DEVICE_ID 0x01 +#define FUSB_REG_SWITCHES0 0x02 +#define FUSB_REG_SWITCHES0_CC2_PU_EN BIT(7) +#define FUSB_REG_SWITCHES0_CC1_PU_EN BIT(6) +#define FUSB_REG_SWITCHES0_VCONN_CC2 BIT(5) +#define FUSB_REG_SWITCHES0_VCONN_CC1 BIT(4) +#define FUSB_REG_SWITCHES0_MEAS_CC2 BIT(3) +#define FUSB_REG_SWITCHES0_MEAS_CC1 BIT(2) +#define FUSB_REG_SWITCHES0_CC2_PD_EN BIT(1) +#define FUSB_REG_SWITCHES0_CC1_PD_EN BIT(0) +#define FUSB_REG_SWITCHES1 0x03 +#define FUSB_REG_SWITCHES1_POWERROLE BIT(7) +#define FUSB_REG_SWITCHES1_SPECREV1 BIT(6) +#define FUSB_REG_SWITCHES1_SPECREV0 BIT(5) +#define FUSB_REG_SWITCHES1_DATAROLE BIT(4) +#define FUSB_REG_SWITCHES1_AUTO_GCRC BIT(2) +#define FUSB_REG_SWITCHES1_TXCC2_EN BIT(1) +#define FUSB_REG_SWITCHES1_TXCC1_EN BIT(0) +#define FUSB_REG_MEASURE 0x04 +#define FUSB_REG_MEASURE_MDAC5 BIT(7) +#define FUSB_REG_MEASURE_MDAC4 BIT(6) +#define FUSB_REG_MEASURE_MDAC3 BIT(5) +#define FUSB_REG_MEASURE_MDAC2 BIT(4) +#define FUSB_REG_MEASURE_MDAC1 BIT(3) +#define FUSB_REG_MEASURE_MDAC0 BIT(2) +#define FUSB_REG_MEASURE_VBUS BIT(1) +#define FUSB_REG_MEASURE_XXXX5 BIT(0) +#define FUSB_REG_CONTROL0 0x06 +#define FUSB_REG_CONTROL0_TX_FLUSH BIT(6) +#define FUSB_REG_CONTROL0_INT_MASK BIT(5) +#define FUSB_REG_CONTROL0_HOST_CUR_MASK (0xC) +#define FUSB_REG_CONTROL0_HOST_CUR_HIGH (0xC) +#define FUSB_REG_CONTROL0_HOST_CUR_MED (0x8) +#define FUSB_REG_CONTROL0_HOST_CUR_DEF (0x4) +#define FUSB_REG_CONTROL0_TX_START BIT(0) +#define FUSB_REG_CONTROL1 0x07 +#define FUSB_REG_CONTROL1_ENSOP2DB BIT(6) +#define FUSB_REG_CONTROL1_ENSOP1DB BIT(5) +#define FUSB_REG_CONTROL1_BIST_MODE2 BIT(4) +#define FUSB_REG_CONTROL1_RX_FLUSH BIT(2) +#define FUSB_REG_CONTROL1_ENSOP2 BIT(1) +#define FUSB_REG_CONTROL1_ENSOP1 BIT(0) +#define FUSB_REG_CONTROL2 0x08 +#define FUSB_REG_CONTROL2_MODE BIT(1) +#define FUSB_REG_CONTROL2_MODE_MASK (0x6) +#define FUSB_REG_CONTROL2_MODE_DFP (0x6) +#define FUSB_REG_CONTROL2_MODE_UFP (0x4) +#define FUSB_REG_CONTROL2_MODE_DRP (0x2) +#define FUSB_REG_CONTROL2_MODE_NONE (0x0) +#define FUSB_REG_CONTROL2_TOGGLE BIT(0) +#define FUSB_REG_CONTROL3 0x09 +#define FUSB_REG_CONTROL3_SEND_HARDRESET BIT(6) +#define FUSB_REG_CONTROL3_BIST_TMODE BIT(5) /* 302B Only */ +#define FUSB_REG_CONTROL3_AUTO_HARDRESET BIT(4) +#define FUSB_REG_CONTROL3_AUTO_SOFTRESET BIT(3) +#define FUSB_REG_CONTROL3_N_RETRIES BIT(1) +#define FUSB_REG_CONTROL3_N_RETRIES_MASK (0x6) +#define FUSB_REG_CONTROL3_N_RETRIES_3 (0x6) +#define FUSB_REG_CONTROL3_N_RETRIES_2 (0x4) +#define FUSB_REG_CONTROL3_N_RETRIES_1 (0x2) +#define FUSB_REG_CONTROL3_AUTO_RETRY BIT(0) +#define FUSB_REG_MASK 0x0A +#define FUSB_REG_MASK_VBUSOK BIT(7) +#define FUSB_REG_MASK_ACTIVITY BIT(6) +#define FUSB_REG_MASK_COMP_CHNG BIT(5) +#define FUSB_REG_MASK_CRC_CHK BIT(4) +#define FUSB_REG_MASK_ALERT BIT(3) +#define FUSB_REG_MASK_WAKE BIT(2) +#define FUSB_REG_MASK_COLLISION BIT(1) +#define FUSB_REG_MASK_BC_LVL BIT(0) +#define FUSB_REG_POWER 0x0B +#define FUSB_REG_POWER_PWR BIT(0) +#define FUSB_REG_POWER_PWR_LOW 0x1 +#define FUSB_REG_POWER_PWR_MEDIUM 0x3 +#define FUSB_REG_POWER_PWR_HIGH 0x7 +#define FUSB_REG_POWER_PWR_ALL 0xF +#define FUSB_REG_RESET 0x0C +#define FUSB_REG_RESET_PD_RESET BIT(1) +#define FUSB_REG_RESET_SW_RESET BIT(0) +#define FUSB_REG_MASKA 0x0E +#define FUSB_REG_MASKA_OCP_TEMP BIT(7) +#define FUSB_REG_MASKA_TOGDONE BIT(6) +#define FUSB_REG_MASKA_SOFTFAIL BIT(5) +#define FUSB_REG_MASKA_RETRYFAIL BIT(4) +#define FUSB_REG_MASKA_HARDSENT BIT(3) +#define FUSB_REG_MASKA_TX_SUCCESS BIT(2) +#define FUSB_REG_MASKA_SOFTRESET BIT(1) +#define FUSB_REG_MASKA_HARDRESET BIT(0) +#define FUSB_REG_MASKB 0x0F +#define FUSB_REG_MASKB_GCRCSENT BIT(0) +#define FUSB_REG_STATUS0A 0x3C +#define FUSB_REG_STATUS0A_SOFTFAIL BIT(5) +#define FUSB_REG_STATUS0A_RETRYFAIL BIT(4) +#define FUSB_REG_STATUS0A_POWER BIT(2) +#define FUSB_REG_STATUS0A_RX_SOFT_RESET BIT(1) +#define FUSB_REG_STATUS0A_RX_HARD_RESET BIT(0) +#define FUSB_REG_STATUS1A 0x3D +#define FUSB_REG_STATUS1A_TOGSS BIT(3) +#define FUSB_REG_STATUS1A_TOGSS_RUNNING 0x0 +#define FUSB_REG_STATUS1A_TOGSS_SRC1 0x1 +#define FUSB_REG_STATUS1A_TOGSS_SRC2 0x2 +#define FUSB_REG_STATUS1A_TOGSS_SNK1 0x5 +#define FUSB_REG_STATUS1A_TOGSS_SNK2 0x6 +#define FUSB_REG_STATUS1A_TOGSS_AA 0x7 +#define FUSB_REG_STATUS1A_TOGSS_POS (3) +#define FUSB_REG_STATUS1A_TOGSS_MASK (0x7) +#define FUSB_REG_STATUS1A_RXSOP2DB BIT(2) +#define FUSB_REG_STATUS1A_RXSOP1DB BIT(1) +#define FUSB_REG_STATUS1A_RXSOP BIT(0) +#define FUSB_REG_INTERRUPTA 0x3E +#define FUSB_REG_INTERRUPTA_OCP_TEMP BIT(7) +#define FUSB_REG_INTERRUPTA_TOGDONE BIT(6) +#define FUSB_REG_INTERRUPTA_SOFTFAIL BIT(5) +#define FUSB_REG_INTERRUPTA_RETRYFAIL BIT(4) +#define FUSB_REG_INTERRUPTA_HARDSENT BIT(3) +#define FUSB_REG_INTERRUPTA_TX_SUCCESS BIT(2) +#define FUSB_REG_INTERRUPTA_SOFTRESET BIT(1) +#define FUSB_REG_INTERRUPTA_HARDRESET BIT(0) +#define FUSB_REG_INTERRUPTB 0x3F +#define FUSB_REG_INTERRUPTB_GCRCSENT BIT(0) +#define FUSB_REG_STATUS0 0x40 +#define FUSB_REG_STATUS0_VBUSOK BIT(7) +#define FUSB_REG_STATUS0_ACTIVITY BIT(6) +#define FUSB_REG_STATUS0_COMP BIT(5) +#define FUSB_REG_STATUS0_CRC_CHK BIT(4) +#define FUSB_REG_STATUS0_ALERT BIT(3) +#define FUSB_REG_STATUS0_WAKE BIT(2) +#define FUSB_REG_STATUS0_BC_LVL_MASK 0x03 +#define FUSB_REG_STATUS0_BC_LVL_0_200 0x0 +#define FUSB_REG_STATUS0_BC_LVL_200_600 0x1 +#define FUSB_REG_STATUS0_BC_LVL_600_1230 0x2 +#define FUSB_REG_STATUS0_BC_LVL_1230_MAX 0x3 +#define FUSB_REG_STATUS0_BC_LVL1 BIT(1) +#define FUSB_REG_STATUS0_BC_LVL0 BIT(0) +#define FUSB_REG_STATUS1 0x41 +#define FUSB_REG_STATUS1_RXSOP2 BIT(7) +#define FUSB_REG_STATUS1_RXSOP1 BIT(6) +#define FUSB_REG_STATUS1_RX_EMPTY BIT(5) +#define FUSB_REG_STATUS1_RX_FULL BIT(4) +#define FUSB_REG_STATUS1_TX_EMPTY BIT(3) +#define FUSB_REG_STATUS1_TX_FULL BIT(2) +#define FUSB_REG_INTERRUPT 0x42 +#define FUSB_REG_INTERRUPT_VBUSOK BIT(7) +#define FUSB_REG_INTERRUPT_ACTIVITY BIT(6) +#define FUSB_REG_INTERRUPT_COMP_CHNG BIT(5) +#define FUSB_REG_INTERRUPT_CRC_CHK BIT(4) +#define FUSB_REG_INTERRUPT_ALERT BIT(3) +#define FUSB_REG_INTERRUPT_WAKE BIT(2) +#define FUSB_REG_INTERRUPT_COLLISION BIT(1) +#define FUSB_REG_INTERRUPT_BC_LVL BIT(0) +#define FUSB_REG_FIFOS 0x43 + +/* Tokens defined for the FUSB302 TX FIFO */ +enum fusb302_txfifo_tokens { + FUSB302_TKN_TXON = 0xA1, + FUSB302_TKN_SYNC1 = 0x12, + FUSB302_TKN_SYNC2 = 0x13, + FUSB302_TKN_SYNC3 = 0x1B, + FUSB302_TKN_RST1 = 0x15, + FUSB302_TKN_RST2 = 0x16, + FUSB302_TKN_PACKSYM = 0x80, + FUSB302_TKN_JAMCRC = 0xFF, + FUSB302_TKN_EOP = 0x14, + FUSB302_TKN_TXOFF = 0xFE, +}; + +#endif diff --git a/drivers/usb/tcpm/tcpm-internal.h b/drivers/usb/tcpm/tcpm-internal.h new file mode 100644 index 00000000000..56144209002 --- /dev/null +++ b/drivers/usb/tcpm/tcpm-internal.h @@ -0,0 +1,173 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright 2015-2017 Google, Inc + * Copyright 2024 Collabora + */ + +#ifndef __LINUX_USB_TCPM_INTERNAL_H +#define __LINUX_USB_TCPM_INTERNAL_H + +#define FOREACH_TCPM_STATE(S) \ + S(INVALID_STATE), \ + S(TOGGLING), \ + S(SRC_UNATTACHED), \ + S(SRC_ATTACH_WAIT), \ + S(SRC_ATTACHED), \ + S(SRC_STARTUP), \ + S(SRC_SEND_CAPABILITIES), \ + S(SRC_SEND_CAPABILITIES_TIMEOUT), \ + S(SRC_NEGOTIATE_CAPABILITIES), \ + S(SRC_TRANSITION_SUPPLY), \ + S(SRC_READY), \ + S(SRC_WAIT_NEW_CAPABILITIES), \ + \ + S(SNK_UNATTACHED), \ + S(SNK_ATTACH_WAIT), \ + S(SNK_DEBOUNCED), \ + S(SNK_ATTACHED), \ + S(SNK_STARTUP), \ + S(SNK_DISCOVERY), \ + S(SNK_DISCOVERY_DEBOUNCE), \ + S(SNK_DISCOVERY_DEBOUNCE_DONE), \ + S(SNK_WAIT_CAPABILITIES), \ + S(SNK_NEGOTIATE_CAPABILITIES), \ + S(SNK_TRANSITION_SINK), \ + S(SNK_TRANSITION_SINK_VBUS), \ + S(SNK_READY), \ + \ + S(HARD_RESET_SEND), \ + S(HARD_RESET_START), \ + S(SRC_HARD_RESET_VBUS_OFF), \ + S(SRC_HARD_RESET_VBUS_ON), \ + S(SNK_HARD_RESET_SINK_OFF), \ + S(SNK_HARD_RESET_WAIT_VBUS), \ + S(SNK_HARD_RESET_SINK_ON), \ + \ + S(SOFT_RESET), \ + S(SOFT_RESET_SEND), \ + \ + S(DR_SWAP_ACCEPT), \ + S(DR_SWAP_CHANGE_DR), \ + \ + S(ERROR_RECOVERY), \ + S(PORT_RESET), \ + S(PORT_RESET_WAIT_OFF) + +#define GENERATE_TCPM_ENUM(e) e +#define GENERATE_TCPM_STRING(s) #s +#define TCPM_POLL_EVENT_TIME_OUT 2000 + +enum tcpm_state { + FOREACH_TCPM_STATE(GENERATE_TCPM_ENUM) +}; + +enum pd_msg_request { + PD_MSG_NONE = 0, + PD_MSG_CTRL_REJECT, + PD_MSG_CTRL_WAIT, + PD_MSG_CTRL_NOT_SUPP, + PD_MSG_DATA_SINK_CAP, + PD_MSG_DATA_SOURCE_CAP, +}; + +struct tcpm_port { + enum typec_port_type typec_type; + int typec_prefer_role; + + enum typec_role vconn_role; + enum typec_role pwr_role; + enum typec_data_role data_role; + + struct typec_partner *partner; + + enum typec_cc_status cc_req; + enum typec_cc_status cc1; + enum typec_cc_status cc2; + enum typec_cc_polarity polarity; + + bool attached; + bool connected; + int poll_event_cnt; + enum typec_port_type port_type; + + /* + * Set to true when vbus is greater than VSAFE5V min. + * Set to false when vbus falls below vSinkDisconnect max threshold. + */ + bool vbus_present; + + /* + * Set to true when vbus is less than VSAFE0V max. + * Set to false when vbus is greater than VSAFE0V max. + */ + bool vbus_vsafe0v; + + bool vbus_never_low; + bool vbus_source; + bool vbus_charge; + + int try_role; + + enum pd_msg_request queued_message; + + enum tcpm_state enter_state; + enum tcpm_state prev_state; + enum tcpm_state state; + enum tcpm_state delayed_state; + unsigned long delay_ms; + + bool state_machine_running; + + bool tx_complete; + enum tcpm_transmit_status tx_status; + + unsigned int negotiated_rev; + unsigned int message_id; + unsigned int caps_count; + unsigned int hard_reset_count; + bool pd_capable; + bool explicit_contract; + unsigned int rx_msgid; + + /* Partner capabilities/requests */ + u32 sink_request; + u32 source_caps[PDO_MAX_OBJECTS]; + unsigned int nr_source_caps; + u32 sink_caps[PDO_MAX_OBJECTS]; + unsigned int nr_sink_caps; + + /* + * whether to wait for the Type-C device to send the DR_SWAP Message flag + * For Type-C device with Dual-Role Power and Dual-Role Data, the port side + * is used as sink + ufp, then the tcpm framework needs to wait for Type-C + * device to initiate DR_swap Message. + */ + bool wait_dr_swap_message; + + /* Local capabilities */ + u32 src_pdo[PDO_MAX_OBJECTS]; + unsigned int nr_src_pdo; + u32 snk_pdo[PDO_MAX_OBJECTS]; + unsigned int nr_snk_pdo; + + unsigned int operating_snk_mw; + bool update_sink_caps; + + /* Requested current / voltage to the port partner */ + u32 req_current_limit; + u32 req_supply_voltage; + /* Actual current / voltage limit of the local port */ + u32 current_limit; + u32 supply_voltage; + + /* port belongs to a self powered device */ + bool self_powered; + + unsigned long delay_target; +}; + +extern const char * const tcpm_states[]; + +int tcpm_post_probe(struct udevice *dev); + +#endif diff --git a/drivers/usb/tcpm/tcpm-uclass.c b/drivers/usb/tcpm/tcpm-uclass.c new file mode 100644 index 00000000000..d4fe260e0db --- /dev/null +++ b/drivers/usb/tcpm/tcpm-uclass.c @@ -0,0 +1,149 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024 Collabora Ltd. + * + * USB Power Delivery protocol stack. + */ + +#include <dm/device.h> +#include <dm/device_compat.h> +#include <dm/uclass.h> +#include <linux/err.h> +#include <usb/tcpm.h> +#include "tcpm-internal.h" + +int tcpm_get_voltage(struct udevice *dev) +{ + struct tcpm_port *port = dev_get_uclass_plat(dev); + + return port->supply_voltage; +} + +int tcpm_get_current(struct udevice *dev) +{ + struct tcpm_port *port = dev_get_uclass_plat(dev); + + return port->current_limit; +} + +enum typec_orientation tcpm_get_orientation(struct udevice *dev) +{ + struct tcpm_port *port = dev_get_uclass_plat(dev); + + switch (port->polarity) { + case TYPEC_POLARITY_CC1: + return TYPEC_ORIENTATION_NORMAL; + case TYPEC_POLARITY_CC2: + return TYPEC_ORIENTATION_REVERSE; + default: + return TYPEC_ORIENTATION_NONE; + } +} + +const char *tcpm_get_state(struct udevice *dev) +{ + struct tcpm_port *port = dev_get_uclass_plat(dev); + + return tcpm_states[port->state]; +} + +int tcpm_get_pd_rev(struct udevice *dev) +{ + struct tcpm_port *port = dev_get_uclass_plat(dev); + + return port->negotiated_rev; +} + +enum typec_role tcpm_get_pwr_role(struct udevice *dev) +{ + struct tcpm_port *port = dev_get_uclass_plat(dev); + + return port->pwr_role; +} + +enum typec_data_role tcpm_get_data_role(struct udevice *dev) +{ + struct tcpm_port *port = dev_get_uclass_plat(dev); + + return port->data_role; +} + +bool tcpm_is_connected(struct udevice *dev) +{ + struct tcpm_port *port = dev_get_uclass_plat(dev); + + return port->connected; +} + +int tcpm_get(int index, struct udevice **devp) +{ + return uclass_get_device(UCLASS_TCPM, index, devp); +} + +static int tcpm_post_bind(struct udevice *dev) +{ + const struct dm_tcpm_ops *drvops = dev_get_driver_ops(dev); + const char *cap_str; + ofnode node; + int ret; + + /* + * USB Power Delivery (USB PD) specification requires, that communication + * with a sink happens within roughly 5 seconds. Otherwise the source + * might assume that the sink does not support USB PD. Starting to do + * USB PD communication after that results in a hard reset, which briefly + * removes any power from the USB-C port. + * + * On systems with alternative power supplies this is not an issue, but + * systems, which get soleley powered through their USB-C port will end + * up losing their power supply and doing a board level reset. The hard + * reset will also restart the 5 second timeout. That means a operating + * system initializing USB PD will put the system into a boot loop when + * it takes more than 5 seconds from cold boot to the operating system + * starting to transmit USB PD messages. + * + * The issue can be avoided by doing the initial USB PD communication + * in U-Boot. The operating system can then re-negotiate by doing a + * soft reset, which does not trigger removal of the supply voltage. + * + * Since the TCPM state machine is quite complex and depending on the + * remote side can take quite some time to finish, this tries to limit + * the automatic probing to systems probably relying on power being + * provided by the USB-C port(s): + * + * 1. self-powered devices won't reset when the USB-C port looses power + * 2. if the power is allowed to go into anything else than sink mode + * it is not the only power source + */ + ret = drvops->get_connector_node(dev, &node); + if (ret) + return ret; + + if (ofnode_read_bool(node, "self-powered")) + return 0; + + cap_str = ofnode_read_string(node, "power-role"); + if (!cap_str) + return -EINVAL; + + if (strcmp("sink", cap_str)) + return 0; + + /* Do not auto-probe PD controller when PD is disabled */ + if (ofnode_read_bool(node, "pd-disable")) + return 0; + + dev_info(dev, "probing Type-C port manager..."); + + dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND); + + return 0; +} + +UCLASS_DRIVER(tcpm) = { + .id = UCLASS_TCPM, + .name = "tcpm", + .per_device_plat_auto = sizeof(struct tcpm_port), + .post_bind = tcpm_post_bind, + .post_probe = tcpm_post_probe, +}; diff --git a/drivers/usb/tcpm/tcpm.c b/drivers/usb/tcpm/tcpm.c new file mode 100644 index 00000000000..0aee57cb2f4 --- /dev/null +++ b/drivers/usb/tcpm/tcpm.c @@ -0,0 +1,2288 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2015-2017 Google, Inc + * + * USB Power Delivery protocol stack. + */ + +#include <asm/gpio.h> +#include <asm/io.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <dm/device-internal.h> +#include <dm/devres.h> +#include <linux/compat.h> +#include <linux/delay.h> +#include <linux/err.h> +#include <linux/iopoll.h> +#include <time.h> +#include <usb/tcpm.h> +#include "tcpm-internal.h" + +DECLARE_GLOBAL_DATA_PTR; + +const char * const tcpm_states[] = { + FOREACH_TCPM_STATE(GENERATE_TCPM_STRING) +}; + +const char * const typec_pd_rev_name[] = { + [PD_REV10] = "rev1", + [PD_REV20] = "rev2", + [PD_REV30] = "rev3", +}; + +const char * const typec_role_name[] = { + [TYPEC_SINK] = "sink", + [TYPEC_SOURCE] = "source", +}; + +const char * const typec_data_role_name[] = { + [TYPEC_DEVICE] = "device", + [TYPEC_HOST] = "host", +}; + +const char * const typec_orientation_name[] = { + [TYPEC_ORIENTATION_NONE] = "none", + [TYPEC_ORIENTATION_NORMAL] = "normal", + [TYPEC_ORIENTATION_REVERSE] = "reverse", +}; + +const char * const typec_cc_status_name[] = { + [TYPEC_CC_OPEN] = "open", + [TYPEC_CC_RA] = "ra", + [TYPEC_CC_RD] = "rd", + [TYPEC_CC_RP_DEF] = "rp-def", + [TYPEC_CC_RP_1_5] = "rp-1.5", + [TYPEC_CC_RP_3_0] = "rp-3.0", +}; + +static inline bool tcpm_cc_is_sink(enum typec_cc_status cc) +{ + return cc == TYPEC_CC_RP_DEF || + cc == TYPEC_CC_RP_1_5 || + cc == TYPEC_CC_RP_3_0; +} + +static inline bool tcpm_port_is_sink(struct tcpm_port *port) +{ + bool cc1_is_snk = tcpm_cc_is_sink(port->cc1); + bool cc2_is_snk = tcpm_cc_is_sink(port->cc2); + + return (cc1_is_snk && !cc2_is_snk) || + (cc2_is_snk && !cc1_is_snk); +} + +static inline bool tcpm_cc_is_source(enum typec_cc_status cc) +{ + return cc == TYPEC_CC_RD; +} + +static inline bool tcpm_port_is_source(struct tcpm_port *port) +{ + bool cc1_is_src = tcpm_cc_is_source(port->cc1); + bool cc2_is_src = tcpm_cc_is_source(port->cc2); + + return (cc1_is_src && !cc2_is_src) || + (cc2_is_src && !cc1_is_src); +} + +static inline bool tcpm_try_src(struct tcpm_port *port) +{ + return port->try_role == TYPEC_SOURCE && + port->port_type == TYPEC_PORT_DRP; +} + +static inline void tcpm_reset_event_cnt(struct udevice *dev) +{ + struct tcpm_port *port = dev_get_uclass_plat(dev); + + port->poll_event_cnt = 0; +} + +static enum tcpm_state tcpm_default_state(struct tcpm_port *port) +{ + if (port->port_type == TYPEC_PORT_DRP) { + if (port->try_role == TYPEC_SINK) + return SNK_UNATTACHED; + else if (port->try_role == TYPEC_SOURCE) + return SRC_UNATTACHED; + } else if (port->port_type == TYPEC_PORT_SNK) { + return SNK_UNATTACHED; + } + return SRC_UNATTACHED; +} + +static bool tcpm_port_is_disconnected(struct tcpm_port *port) +{ + return (!port->attached && port->cc1 == TYPEC_CC_OPEN && + port->cc2 == TYPEC_CC_OPEN) || + (port->attached && ((port->polarity == TYPEC_POLARITY_CC1 && + port->cc1 == TYPEC_CC_OPEN) || + (port->polarity == TYPEC_POLARITY_CC2 && + port->cc2 == TYPEC_CC_OPEN))); +} + +static void tcpm_set_cc(struct udevice *dev, enum typec_cc_status cc) +{ + const struct dm_tcpm_ops *drvops = dev_get_driver_ops(dev); + struct tcpm_port *port = dev_get_uclass_plat(dev); + + dev_dbg(dev, "TCPM: set cc = %d\n", cc); + port->cc_req = cc; + drvops->set_cc(dev, cc); +} + +/* + * Determine RP value to set based on maximum current supported + * by a port if configured as source. + * Returns CC value to report to link partner. + */ +static enum typec_cc_status tcpm_rp_cc(struct tcpm_port *port) +{ + const u32 *src_pdo = port->src_pdo; + int nr_pdo = port->nr_src_pdo; + int i; + + /* + * Search for first entry with matching voltage. + * It should report the maximum supported current. + */ + for (i = 0; i < nr_pdo; i++) { + const u32 pdo = src_pdo[i]; + + if (pdo_type(pdo) == PDO_TYPE_FIXED && + pdo_fixed_voltage(pdo) == 5000) { + unsigned int curr = pdo_max_current(pdo); + + if (curr >= 3000) + return TYPEC_CC_RP_3_0; + else if (curr >= 1500) + return TYPEC_CC_RP_1_5; + return TYPEC_CC_RP_DEF; + } + } + + return TYPEC_CC_RP_DEF; +} + +static void tcpm_check_and_run_delayed_work(struct udevice *dev); + +static bool tcpm_transmit_helper(struct udevice *dev) +{ + const struct dm_tcpm_ops *drvops = dev_get_driver_ops(dev); + struct tcpm_port *port = dev_get_uclass_plat(dev); + + drvops->poll_event(dev); + udelay(500); + tcpm_check_and_run_delayed_work(dev); + return port->tx_complete; +} + +static int tcpm_pd_transmit(struct udevice *dev, + enum tcpm_transmit_type type, + const struct pd_message *msg) +{ + const struct dm_tcpm_ops *drvops = dev_get_driver_ops(dev); + struct tcpm_port *port = dev_get_uclass_plat(dev); + u32 timeout_us = PD_T_TCPC_TX_TIMEOUT * 1000; + bool tx_complete; + int ret; + + if (msg) + dev_dbg(dev, "TCPM: PD TX, header: %#x\n", + le16_to_cpu(msg->header)); + else + dev_dbg(dev, "TCPM: PD TX, type: %#x\n", type); + + port->tx_complete = false; + ret = drvops->pd_transmit(dev, type, msg, port->negotiated_rev); + if (ret < 0) + return ret; + + /* + * At this point we basically need to block until the TCPM controller + * returns successful transmission. Since this is usually done using + * the generic interrupt status bits, we poll for any events. That + * will clear the interrupt status, so we also need to process any + * of the incoming events. This means we will do more processing and + * thus let's give everything a bit more time. + */ + timeout_us *= 5; + ret = read_poll_timeout(tcpm_transmit_helper, tx_complete, + !tx_complete, false, timeout_us, dev); + if (ret < 0) { + dev_err(dev, "TCPM: PD transmit data failed: %d\n", ret); + return ret; + } + + switch (port->tx_status) { + case TCPC_TX_SUCCESS: + port->message_id = (port->message_id + 1) & PD_HEADER_ID_MASK; + break; + case TCPC_TX_DISCARDED: + ret = -EAGAIN; + break; + case TCPC_TX_FAILED: + default: + ret = -EIO; + break; + } + + return ret; +} + +void tcpm_pd_transmit_complete(struct udevice *dev, + enum tcpm_transmit_status status) +{ + struct tcpm_port *port = dev_get_uclass_plat(dev); + + dev_dbg(dev, "TCPM: PD TX complete, status: %u\n", status); + tcpm_reset_event_cnt(dev); + port->tx_status = status; + port->tx_complete = true; +} + +static int tcpm_set_polarity(struct udevice *dev, + enum typec_cc_polarity polarity) +{ + struct tcpm_port *port = dev_get_uclass_plat(dev); + const struct dm_tcpm_ops *drvops = dev_get_driver_ops(dev); + int ret; + + dev_dbg(dev, "TCPM: set polarity = %d\n", polarity); + + if (drvops->set_polarity) { + ret = drvops->set_polarity(dev, polarity); + if (ret < 0) + return ret; + } + + port->polarity = polarity; + + return 0; +} + +static int tcpm_set_vconn(struct udevice *dev, bool enable) +{ + const struct dm_tcpm_ops *drvops = dev_get_driver_ops(dev); + struct tcpm_port *port = dev_get_uclass_plat(dev); + int ret; + + dev_dbg(dev, "TCPM: set vconn = %d\n", enable); + + ret = drvops->set_vconn(dev, enable); + if (!ret) + port->vconn_role = enable ? TYPEC_SOURCE : TYPEC_SINK; + + return ret; +} + +static inline u32 tcpm_get_current_limit(struct tcpm_port *port) +{ + switch (port->polarity ? port->cc2 : port->cc1) { + case TYPEC_CC_RP_1_5: + return 1500; + case TYPEC_CC_RP_3_0: + return 3000; + case TYPEC_CC_RP_DEF: + default: + return 0; + } +} + +static int tcpm_set_current_limit(struct udevice *dev, u32 max_ma, u32 mv) +{ + struct tcpm_port *port = dev_get_uclass_plat(dev); + int ret = -EOPNOTSUPP; + + dev_info(dev, "TCPM: set voltage limit = %u mV\n", mv); + dev_info(dev, "TCPM: set current limit = %u mA\n", max_ma); + + port->supply_voltage = mv; + port->current_limit = max_ma; + + return ret; +} + +static int tcpm_set_attached_state(struct udevice *dev, bool attached) +{ + const struct dm_tcpm_ops *drvops = dev_get_driver_ops(dev); + struct tcpm_port *port = dev_get_uclass_plat(dev); + + return drvops->set_roles(dev, attached, port->pwr_role, + port->data_role); +} + +static int tcpm_set_roles(struct udevice *dev, bool attached, + enum typec_role role, enum typec_data_role data) +{ + const struct dm_tcpm_ops *drvops = dev_get_driver_ops(dev); + struct tcpm_port *port = dev_get_uclass_plat(dev); + int ret; + + ret = drvops->set_roles(dev, attached, role, data); + if (ret < 0) + return ret; + + port->pwr_role = role; + port->data_role = data; + + return 0; +} + +static int tcpm_pd_send_source_caps(struct udevice *dev) +{ + struct tcpm_port *port = dev_get_uclass_plat(dev); + struct pd_message msg; + int i; + + memset(&msg, 0, sizeof(msg)); + + if (!port->nr_src_pdo) { + /* No source capabilities defined, sink only */ + msg.header = PD_HEADER_LE(PD_CTRL_REJECT, + port->pwr_role, + port->data_role, + port->negotiated_rev, + port->message_id, 0); + } else { + msg.header = PD_HEADER_LE(PD_DATA_SOURCE_CAP, + port->pwr_role, + port->data_role, + port->negotiated_rev, + port->message_id, + port->nr_src_pdo); + } + + for (i = 0; i < port->nr_src_pdo; i++) + msg.payload[i] = cpu_to_le32(port->src_pdo[i]); + + return tcpm_pd_transmit(dev, TCPC_TX_SOP, &msg); +} + +static int tcpm_pd_send_sink_caps(struct udevice *dev) +{ + struct tcpm_port *port = dev_get_uclass_plat(dev); + struct pd_message msg; + unsigned int i; + + memset(&msg, 0, sizeof(msg)); + + if (!port->nr_snk_pdo) { + /* No sink capabilities defined, source only */ + msg.header = PD_HEADER_LE(PD_CTRL_REJECT, + port->pwr_role, + port->data_role, + port->negotiated_rev, + port->message_id, 0); + } else { + msg.header = PD_HEADER_LE(PD_DATA_SINK_CAP, + port->pwr_role, + port->data_role, + port->negotiated_rev, + port->message_id, + port->nr_snk_pdo); + } + + for (i = 0; i < port->nr_snk_pdo; i++) + msg.payload[i] = cpu_to_le32(port->snk_pdo[i]); + + return tcpm_pd_transmit(dev, TCPC_TX_SOP, &msg); +} + +static void tcpm_state_machine(struct udevice *dev); + +static inline void tcpm_timer_uninit(struct udevice *dev) +{ + struct tcpm_port *port = dev_get_uclass_plat(dev); + + port->delay_target = 0; +} + +static void tcpm_timer_init(struct udevice *dev, uint32_t ms) +{ + struct tcpm_port *port = dev_get_uclass_plat(dev); + unsigned long time_us = ms * 1000; + + port->delay_target = timer_get_us() + time_us; +} + +static void tcpm_check_and_run_delayed_work(struct udevice *dev) +{ + struct tcpm_port *port = dev_get_uclass_plat(dev); + + /* no delayed state changes scheduled */ + if (port->delay_target == 0) + return; + + /* it's not yet time */ + if (timer_get_us() < port->delay_target) + return; + + tcpm_timer_uninit(dev); + tcpm_state_machine(dev); +} + +static void mod_tcpm_delayed_work(struct udevice *dev, unsigned int delay_ms) +{ + if (delay_ms) { + tcpm_timer_init(dev, delay_ms); + } else { + tcpm_timer_uninit(dev); + tcpm_state_machine(dev); + } +} + +static void tcpm_set_state(struct udevice *dev, enum tcpm_state state, + unsigned int delay_ms) +{ + struct tcpm_port *port = dev_get_uclass_plat(dev); + + if (delay_ms) { + dev_dbg(dev, "TCPM: pending state change %s -> %s @ %u ms [%s]\n", + tcpm_states[port->state], tcpm_states[state], delay_ms, + typec_pd_rev_name[port->negotiated_rev]); + port->delayed_state = state; + mod_tcpm_delayed_work(dev, delay_ms); + port->delay_ms = delay_ms; + } else { + dev_dbg(dev, "TCPM: state change %s -> %s\n", + tcpm_states[port->state], tcpm_states[state]); + port->delayed_state = INVALID_STATE; + port->prev_state = port->state; + port->state = state; + /* + * Don't re-queue the state machine work item if we're currently + * in the state machine and we're immediately changing states. + * tcpm_state_machine_work() will continue running the state + * machine. + */ + if (!port->state_machine_running) + mod_tcpm_delayed_work(dev, 0); + } +} + +static void tcpm_set_state_cond(struct udevice *dev, enum tcpm_state state, + unsigned int delay_ms) +{ + struct tcpm_port *port = dev_get_uclass_plat(dev); + + if (port->enter_state == port->state) + tcpm_set_state(dev, state, delay_ms); + else + dev_dbg(dev, "TCPM: skipped %sstate change %s -> %s [%u ms], context state %s [%s]\n", + delay_ms ? "delayed " : "", + tcpm_states[port->state], tcpm_states[state], + delay_ms, tcpm_states[port->enter_state], + typec_pd_rev_name[port->negotiated_rev]); +} + +static void tcpm_queue_message(struct udevice *dev, + enum pd_msg_request message) +{ + struct tcpm_port *port = dev_get_uclass_plat(dev); + + port->queued_message = message; + mod_tcpm_delayed_work(dev, 0); +} + +enum pdo_err { + PDO_NO_ERR, + PDO_ERR_NO_VSAFE5V, + PDO_ERR_VSAFE5V_NOT_FIRST, + PDO_ERR_PDO_TYPE_NOT_IN_ORDER, + PDO_ERR_FIXED_NOT_SORTED, + PDO_ERR_VARIABLE_BATT_NOT_SORTED, + PDO_ERR_DUPE_PDO, + PDO_ERR_PPS_APDO_NOT_SORTED, + PDO_ERR_DUPE_PPS_APDO, +}; + +static const char * const pdo_err_msg[] = { + [PDO_ERR_NO_VSAFE5V] = + " err: source/sink caps should at least have vSafe5V", + [PDO_ERR_VSAFE5V_NOT_FIRST] = + " err: vSafe5V Fixed Supply Object Shall always be the first object", + [PDO_ERR_PDO_TYPE_NOT_IN_ORDER] = + " err: PDOs should be in the following order: Fixed; Battery; Variable", + [PDO_ERR_FIXED_NOT_SORTED] = + " err: Fixed supply pdos should be in increasing order of their fixed voltage", + [PDO_ERR_VARIABLE_BATT_NOT_SORTED] = + " err: Variable/Battery supply pdos should be in increasing order of their minimum voltage", + [PDO_ERR_DUPE_PDO] = + " err: Variable/Batt supply pdos cannot have same min/max voltage", + [PDO_ERR_PPS_APDO_NOT_SORTED] = + " err: Programmable power supply apdos should be in increasing order of their maximum voltage", + [PDO_ERR_DUPE_PPS_APDO] = + " err: Programmable power supply apdos cannot have same min/max voltage and max current", +}; + +static enum pdo_err tcpm_caps_err(struct udevice *dev, const u32 *pdo, + unsigned int nr_pdo) +{ + unsigned int i; + + /* Should at least contain vSafe5v */ + if (nr_pdo < 1) + return PDO_ERR_NO_VSAFE5V; + + /* The vSafe5V Fixed Supply Object Shall always be the first object */ + if (pdo_type(pdo[0]) != PDO_TYPE_FIXED || + pdo_fixed_voltage(pdo[0]) != VSAFE5V) + return PDO_ERR_VSAFE5V_NOT_FIRST; + + for (i = 1; i < nr_pdo; i++) { + if (pdo_type(pdo[i]) < pdo_type(pdo[i - 1])) { + return PDO_ERR_PDO_TYPE_NOT_IN_ORDER; + } else if (pdo_type(pdo[i]) == pdo_type(pdo[i - 1])) { + enum pd_pdo_type type = pdo_type(pdo[i]); + + switch (type) { + /* + * The remaining Fixed Supply Objects, if + * present, shall be sent in voltage order; + * lowest to highest. + */ + case PDO_TYPE_FIXED: + if (pdo_fixed_voltage(pdo[i]) <= + pdo_fixed_voltage(pdo[i - 1])) + return PDO_ERR_FIXED_NOT_SORTED; + break; + /* + * The Battery Supply Objects and Variable + * supply, if present shall be sent in Minimum + * Voltage order; lowest to highest. + */ + case PDO_TYPE_VAR: + case PDO_TYPE_BATT: + if (pdo_min_voltage(pdo[i]) < + pdo_min_voltage(pdo[i - 1])) + return PDO_ERR_VARIABLE_BATT_NOT_SORTED; + else if ((pdo_min_voltage(pdo[i]) == + pdo_min_voltage(pdo[i - 1])) && + (pdo_max_voltage(pdo[i]) == + pdo_max_voltage(pdo[i - 1]))) + return PDO_ERR_DUPE_PDO; + break; + /* + * The Programmable Power Supply APDOs, if present, + * shall be sent in Maximum Voltage order; + * lowest to highest. + */ + case PDO_TYPE_APDO: + if (pdo_apdo_type(pdo[i]) != APDO_TYPE_PPS) + break; + + if (pdo_pps_apdo_max_voltage(pdo[i]) < + pdo_pps_apdo_max_voltage(pdo[i - 1])) + return PDO_ERR_PPS_APDO_NOT_SORTED; + else if (pdo_pps_apdo_min_voltage(pdo[i]) == + pdo_pps_apdo_min_voltage(pdo[i - 1]) && + pdo_pps_apdo_max_voltage(pdo[i]) == + pdo_pps_apdo_max_voltage(pdo[i - 1]) && + pdo_pps_apdo_max_current(pdo[i]) == + pdo_pps_apdo_max_current(pdo[i - 1])) + return PDO_ERR_DUPE_PPS_APDO; + break; + default: + dev_err(dev, "TCPM: Unknown pdo type\n"); + } + } + } + + return PDO_NO_ERR; +} + +static int tcpm_validate_caps(struct udevice *dev, const u32 *pdo, + unsigned int nr_pdo) +{ + enum pdo_err err_index = tcpm_caps_err(dev, pdo, nr_pdo); + + if (err_index != PDO_NO_ERR) { + dev_err(dev, "TCPM:%s\n", pdo_err_msg[err_index]); + return -EINVAL; + } + + return 0; +} + +/* + * PD (data, control) command handling functions + */ +static inline enum tcpm_state ready_state(struct tcpm_port *port) +{ + if (port->pwr_role == TYPEC_SOURCE) + return SRC_READY; + else + return SNK_READY; +} + +static void tcpm_pd_data_request(struct udevice *dev, + const struct pd_message *msg) +{ + enum pd_data_msg_type type = pd_header_type_le(msg->header); + struct tcpm_port *port = dev_get_uclass_plat(dev); + unsigned int cnt = pd_header_cnt_le(msg->header); + unsigned int rev = pd_header_rev_le(msg->header); + unsigned int i; + + switch (type) { + case PD_DATA_SOURCE_CAP: + for (i = 0; i < cnt; i++) + port->source_caps[i] = le32_to_cpu(msg->payload[i]); + + port->nr_source_caps = cnt; + + tcpm_validate_caps(dev, port->source_caps, + port->nr_source_caps); + + /* + * Adjust revision in subsequent message headers, as required, + * to comply with 6.2.1.1.5 of the USB PD 3.0 spec. We don't + * support Rev 1.0 so just do nothing in that scenario. + */ + if (rev == PD_REV10) + break; + + if (rev < PD_MAX_REV) + port->negotiated_rev = rev; + + if ((pdo_type(port->source_caps[0]) == PDO_TYPE_FIXED) && + (port->source_caps[0] & PDO_FIXED_DUAL_ROLE) && + (port->source_caps[0] & PDO_FIXED_DATA_SWAP)) { + /* Dual role power and data, eg: self-powered Type-C */ + port->wait_dr_swap_message = true; + } else { + /* Non-Dual role power, eg: adapter */ + port->wait_dr_swap_message = false; + } + + /* + * This message may be received even if VBUS is not + * present. This is quite unexpected; see USB PD + * specification, sections 8.3.3.6.3.1 and 8.3.3.6.3.2. + * However, at the same time, we must be ready to + * receive this message and respond to it 15ms after + * receiving PS_RDY during power swap operations, no matter + * if VBUS is available or not (USB PD specification, + * section 6.5.9.2). + * So we need to accept the message either way, + * but be prepared to keep waiting for VBUS after it was + * handled. + */ + tcpm_set_state(dev, SNK_NEGOTIATE_CAPABILITIES, 0); + break; + case PD_DATA_REQUEST: + /* + * Adjust revision in subsequent message headers, as required, + * to comply with 6.2.1.1.5 of the USB PD 3.0 spec. We don't + * support Rev 1.0 so just reject in that scenario. + */ + if (rev == PD_REV10) { + tcpm_queue_message(dev, PD_MSG_CTRL_REJECT); + break; + } + + if (rev < PD_MAX_REV) + port->negotiated_rev = rev; + + port->sink_request = le32_to_cpu(msg->payload[0]); + + tcpm_set_state(dev, SRC_NEGOTIATE_CAPABILITIES, 0); + break; + case PD_DATA_SINK_CAP: + /* We don't do anything with this at the moment... */ + for (i = 0; i < cnt; i++) + port->sink_caps[i] = le32_to_cpu(msg->payload[i]); + + port->nr_sink_caps = cnt; + break; + default: + break; + } +} + +static void tcpm_pd_ctrl_request(struct udevice *dev, + const struct pd_message *msg) +{ + enum pd_ctrl_msg_type type = pd_header_type_le(msg->header); + struct tcpm_port *port = dev_get_uclass_plat(dev); + enum tcpm_state next_state; + + switch (type) { + case PD_CTRL_GOOD_CRC: + case PD_CTRL_PING: + break; + case PD_CTRL_GET_SOURCE_CAP: + switch (port->state) { + case SRC_READY: + case SNK_READY: + tcpm_queue_message(dev, PD_MSG_DATA_SOURCE_CAP); + break; + default: + tcpm_queue_message(dev, PD_MSG_CTRL_REJECT); + break; + } + break; + case PD_CTRL_GET_SINK_CAP: + switch (port->state) { + case SRC_READY: + case SNK_READY: + tcpm_queue_message(dev, PD_MSG_DATA_SINK_CAP); + break; + default: + tcpm_queue_message(dev, PD_MSG_CTRL_REJECT); + break; + } + break; + case PD_CTRL_GOTO_MIN: + break; + case PD_CTRL_PS_RDY: + switch (port->state) { + case SNK_TRANSITION_SINK: + if (port->vbus_present) { + tcpm_set_current_limit(dev, + port->req_current_limit, + port->req_supply_voltage); + port->explicit_contract = true; + tcpm_set_state(dev, SNK_READY, 0); + } else { + /* + * Seen after power swap. Keep waiting for VBUS + * in a transitional state. + */ + tcpm_set_state(dev, + SNK_TRANSITION_SINK_VBUS, 0); + } + break; + default: + break; + } + break; + case PD_CTRL_REJECT: + case PD_CTRL_WAIT: + case PD_CTRL_NOT_SUPP: + switch (port->state) { + case SNK_NEGOTIATE_CAPABILITIES: + /* USB PD specification, Figure 8-43 */ + if (port->explicit_contract) + next_state = SNK_READY; + else + next_state = SNK_WAIT_CAPABILITIES; + + tcpm_set_state(dev, next_state, 0); + break; + default: + break; + } + break; + case PD_CTRL_ACCEPT: + switch (port->state) { + case SNK_NEGOTIATE_CAPABILITIES: + tcpm_set_state(dev, SNK_TRANSITION_SINK, 0); + break; + case SOFT_RESET_SEND: + port->message_id = 0; + port->rx_msgid = -1; + if (port->pwr_role == TYPEC_SOURCE) + next_state = SRC_SEND_CAPABILITIES; + else + next_state = SNK_WAIT_CAPABILITIES; + tcpm_set_state(dev, next_state, 0); + break; + default: + break; + } + break; + case PD_CTRL_SOFT_RESET: + tcpm_set_state(dev, SOFT_RESET, 0); + break; + case PD_CTRL_DR_SWAP: + if (port->port_type != TYPEC_PORT_DRP) { + tcpm_queue_message(dev, PD_MSG_CTRL_REJECT); + break; + } + /* + * 6.3.9: If an alternate mode is active, a request to swap + * alternate modes shall trigger a port reset. + */ + switch (port->state) { + case SRC_READY: + case SNK_READY: + tcpm_set_state(dev, DR_SWAP_ACCEPT, 0); + break; + default: + tcpm_queue_message(dev, PD_MSG_CTRL_WAIT); + break; + } + break; + case PD_CTRL_PR_SWAP: + case PD_CTRL_VCONN_SWAP: + case PD_CTRL_GET_SOURCE_CAP_EXT: + case PD_CTRL_GET_STATUS: + case PD_CTRL_FR_SWAP: + case PD_CTRL_GET_PPS_STATUS: + case PD_CTRL_GET_COUNTRY_CODES: + /* Currently not supported */ + dev_err(dev, "TCPM: Currently not supported type %#x\n", type); + tcpm_queue_message(dev, PD_MSG_CTRL_NOT_SUPP); + break; + default: + dev_err(dev, "TCPM: Unrecognized ctrl message type %#x\n", type); + break; + } +} + +static void tcpm_pd_rx_handler(struct udevice *dev, + const struct pd_message *msg) +{ + struct tcpm_port *port = dev_get_uclass_plat(dev); + unsigned int cnt = pd_header_cnt_le(msg->header); + bool remote_is_host, local_is_host; + + dev_dbg(dev, "TCPM: PD RX, header: %#x [%d]\n", + le16_to_cpu(msg->header), port->attached); + + if (port->attached) { + enum pd_ctrl_msg_type type = pd_header_type_le(msg->header); + unsigned int msgid = pd_header_msgid_le(msg->header); + + /* + * USB PD standard, 6.6.1.2: + * "... if MessageID value in a received Message is the + * same as the stored value, the receiver shall return a + * GoodCRC Message with that MessageID value and drop + * the Message (this is a retry of an already received + * Message). Note: this shall not apply to the Soft_Reset + * Message which always has a MessageID value of zero." + */ + if (msgid == port->rx_msgid && type != PD_CTRL_SOFT_RESET) + return; + port->rx_msgid = msgid; + + /* + * If both ends believe to be DFP/host, we have a data role + * mismatch. + */ + remote_is_host = !!(le16_to_cpu(msg->header) & PD_HEADER_DATA_ROLE); + local_is_host = port->data_role == TYPEC_HOST; + if (remote_is_host == local_is_host) { + dev_err(dev, "TCPM: data role mismatch, initiating error recovery\n"); + tcpm_set_state(dev, ERROR_RECOVERY, 0); + } else { + if (cnt) + tcpm_pd_data_request(dev, msg); + else + tcpm_pd_ctrl_request(dev, msg); + } + } +} + +void tcpm_pd_receive(struct udevice *dev, const struct pd_message *msg) +{ + tcpm_reset_event_cnt(dev); + tcpm_pd_rx_handler(dev, msg); +} + +static int tcpm_pd_send_control(struct udevice *dev, + enum pd_ctrl_msg_type type) +{ + struct tcpm_port *port = dev_get_uclass_plat(dev); + struct pd_message msg; + + memset(&msg, 0, sizeof(msg)); + msg.header = PD_HEADER_LE(type, port->pwr_role, + port->data_role, + port->negotiated_rev, + port->message_id, 0); + + return tcpm_pd_transmit(dev, TCPC_TX_SOP, &msg); +} + +/* + * Send queued message without affecting state. + * Return true if state machine should go back to sleep, + * false otherwise. + */ +static bool tcpm_send_queued_message(struct udevice *dev) +{ + struct tcpm_port *port = dev_get_uclass_plat(dev); + enum pd_msg_request queued_message; + int max_messages = 100; + + do { + queued_message = port->queued_message; + port->queued_message = PD_MSG_NONE; + max_messages--; + + switch (queued_message) { + case PD_MSG_CTRL_WAIT: + tcpm_pd_send_control(dev, PD_CTRL_WAIT); + break; + case PD_MSG_CTRL_REJECT: + tcpm_pd_send_control(dev, PD_CTRL_REJECT); + break; + case PD_MSG_CTRL_NOT_SUPP: + tcpm_pd_send_control(dev, PD_CTRL_NOT_SUPP); + break; + case PD_MSG_DATA_SINK_CAP: + tcpm_pd_send_sink_caps(dev); + break; + case PD_MSG_DATA_SOURCE_CAP: + tcpm_pd_send_source_caps(dev); + break; + default: + break; + } + } while (max_messages > 0 && port->queued_message != PD_MSG_NONE); + + if (!max_messages) + dev_err(dev, "Aborted sending of too many queued messages\n"); + + return false; +} + +static int tcpm_pd_check_request(struct udevice *dev) +{ + struct tcpm_port *port = dev_get_uclass_plat(dev); + u32 pdo, rdo = port->sink_request; + unsigned int max, op, pdo_max, index; + enum pd_pdo_type type; + + index = rdo_index(rdo); + if (!index || index > port->nr_src_pdo) + return -EINVAL; + + pdo = port->src_pdo[index - 1]; + type = pdo_type(pdo); + switch (type) { + case PDO_TYPE_FIXED: + case PDO_TYPE_VAR: + max = rdo_max_current(rdo); + op = rdo_op_current(rdo); + pdo_max = pdo_max_current(pdo); + + if (op > pdo_max) + return -EINVAL; + if (max > pdo_max && !(rdo & RDO_CAP_MISMATCH)) + return -EINVAL; + + if (type == PDO_TYPE_FIXED) + dev_dbg(dev, "TCPM: Requested %u mV, %u mA for %u / %u mA\n", + pdo_fixed_voltage(pdo), pdo_max, op, max); + else + dev_dbg(dev, "TCPM: Requested %u -> %u mV, %u mA for %u / %u mA\n", + pdo_min_voltage(pdo), pdo_max_voltage(pdo), + pdo_max, op, max); + break; + case PDO_TYPE_BATT: + max = rdo_max_power(rdo); + op = rdo_op_power(rdo); + pdo_max = pdo_max_power(pdo); + + if (op > pdo_max) + return -EINVAL; + if (max > pdo_max && !(rdo & RDO_CAP_MISMATCH)) + return -EINVAL; + dev_info(dev, "TCPM: Requested %u -> %u mV, %u mW for %u / %u mW\n", + pdo_min_voltage(pdo), pdo_max_voltage(pdo), + pdo_max, op, max); + break; + default: + return -EINVAL; + } + + return 0; +} + +#define min_power(x, y) min(pdo_max_power(x), pdo_max_power(y)) +#define min_current(x, y) min(pdo_max_current(x), pdo_max_current(y)) + +static int tcpm_pd_select_pdo(struct udevice *dev, int *sink_pdo, + int *src_pdo) +{ + struct tcpm_port *port = dev_get_uclass_plat(dev); + unsigned int i, j, max_src_mv = 0, min_src_mv = 0, max_mw = 0, + max_mv = 0, src_mw = 0, src_ma = 0, max_snk_mv = 0, + min_snk_mv = 0; + int ret = -EINVAL; + + /* + * Select the source PDO providing the most power which has a + * matchig sink cap. + */ + for (i = 0; i < port->nr_source_caps; i++) { + u32 pdo = port->source_caps[i]; + enum pd_pdo_type type = pdo_type(pdo); + + switch (type) { + case PDO_TYPE_FIXED: + max_src_mv = pdo_fixed_voltage(pdo); + min_src_mv = max_src_mv; + break; + case PDO_TYPE_BATT: + case PDO_TYPE_VAR: + max_src_mv = pdo_max_voltage(pdo); + min_src_mv = pdo_min_voltage(pdo); + break; + case PDO_TYPE_APDO: + continue; + default: + dev_err(dev, "TCPM: Invalid source PDO type, ignoring\n"); + continue; + } + + switch (type) { + case PDO_TYPE_FIXED: + case PDO_TYPE_VAR: + src_ma = pdo_max_current(pdo); + src_mw = src_ma * min_src_mv / 1000; + break; + case PDO_TYPE_BATT: + src_mw = pdo_max_power(pdo); + break; + case PDO_TYPE_APDO: + continue; + default: + dev_err(dev, "TCPM: Invalid source PDO type, ignoring\n"); + continue; + } + + for (j = 0; j < port->nr_snk_pdo; j++) { + pdo = port->snk_pdo[j]; + + switch (pdo_type(pdo)) { + case PDO_TYPE_FIXED: + max_snk_mv = pdo_fixed_voltage(pdo); + min_snk_mv = max_snk_mv; + break; + case PDO_TYPE_BATT: + case PDO_TYPE_VAR: + max_snk_mv = pdo_max_voltage(pdo); + min_snk_mv = pdo_min_voltage(pdo); + break; + case PDO_TYPE_APDO: + continue; + default: + dev_err(dev, "TCPM: Invalid sink PDO type, ignoring\n"); + continue; + } + + if (max_src_mv <= max_snk_mv && min_src_mv >= min_snk_mv) { + /* Prefer higher voltages if available */ + if ((src_mw == max_mw && min_src_mv > max_mv) || + src_mw > max_mw) { + *src_pdo = i; + *sink_pdo = j; + max_mw = src_mw; + max_mv = min_src_mv; + ret = 0; + } + } + } + } + + return ret; +} + +static int tcpm_pd_build_request(struct udevice *dev, u32 *rdo) +{ + struct tcpm_port *port = dev_get_uclass_plat(dev); + unsigned int mv, ma, mw, flags; + unsigned int max_ma, max_mw; + enum pd_pdo_type type; + u32 pdo, matching_snk_pdo; + int src_pdo_index = 0; + int snk_pdo_index = 0; + int ret; + + ret = tcpm_pd_select_pdo(dev, &snk_pdo_index, &src_pdo_index); + if (ret < 0) + return ret; + + pdo = port->source_caps[src_pdo_index]; + matching_snk_pdo = port->snk_pdo[snk_pdo_index]; + type = pdo_type(pdo); + + switch (type) { + case PDO_TYPE_FIXED: + mv = pdo_fixed_voltage(pdo); + break; + case PDO_TYPE_BATT: + case PDO_TYPE_VAR: + mv = pdo_min_voltage(pdo); + break; + default: + dev_err(dev, "TCPM: Invalid PDO selected!\n"); + return -EINVAL; + } + + /* Select maximum available current within the sink pdo's limit */ + if (type == PDO_TYPE_BATT) { + mw = min_power(pdo, matching_snk_pdo); + ma = 1000 * mw / mv; + } else { + ma = min_current(pdo, matching_snk_pdo); + mw = ma * mv / 1000; + } + + flags = RDO_USB_COMM | RDO_NO_SUSPEND; + + /* Set mismatch bit if offered power is less than operating power */ + max_ma = ma; + max_mw = mw; + if (mw < port->operating_snk_mw) { + flags |= RDO_CAP_MISMATCH; + if (type == PDO_TYPE_BATT && + (pdo_max_power(matching_snk_pdo) > pdo_max_power(pdo))) + max_mw = pdo_max_power(matching_snk_pdo); + else if (pdo_max_current(matching_snk_pdo) > + pdo_max_current(pdo)) + max_ma = pdo_max_current(matching_snk_pdo); + } + + dev_dbg(dev, "TCPM: cc=%d cc1=%d cc2=%d vbus=%d vconn=%s polarity=%d\n", + port->cc_req, port->cc1, port->cc2, port->vbus_source, + port->vconn_role == TYPEC_SOURCE ? "source" : "sink", + port->polarity); + + if (type == PDO_TYPE_BATT) { + *rdo = RDO_BATT(src_pdo_index + 1, mw, max_mw, flags); + + dev_info(dev, "TCPM: requesting PDO %d: %u mV, %u mW%s\n", + src_pdo_index, mv, mw, + flags & RDO_CAP_MISMATCH ? " [mismatch]" : ""); + } else { + *rdo = RDO_FIXED(src_pdo_index + 1, ma, max_ma, flags); + + dev_info(dev, "TCPM: requesting PDO %d: %u mV, %u mA%s\n", + src_pdo_index, mv, ma, + flags & RDO_CAP_MISMATCH ? " [mismatch]" : ""); + } + + port->req_current_limit = ma; + port->req_supply_voltage = mv; + + return 0; +} + +static int tcpm_pd_send_request(struct udevice *dev) +{ + struct tcpm_port *port = dev_get_uclass_plat(dev); + struct pd_message msg; + int ret; + u32 rdo; + + ret = tcpm_pd_build_request(dev, &rdo); + if (ret < 0) + return ret; + + memset(&msg, 0, sizeof(msg)); + msg.header = PD_HEADER_LE(PD_DATA_REQUEST, + port->pwr_role, + port->data_role, + port->negotiated_rev, + port->message_id, 1); + msg.payload[0] = cpu_to_le32(rdo); + + return tcpm_pd_transmit(dev, TCPC_TX_SOP, &msg); +} + +static int tcpm_set_vbus(struct udevice *dev, bool enable) +{ + struct tcpm_port *port = dev_get_uclass_plat(dev); + const struct dm_tcpm_ops *drvops = dev_get_driver_ops(dev); + int ret; + + if (enable && port->vbus_charge) + return -EINVAL; + + dev_dbg(dev, "TCPM: set vbus = %d charge = %d\n", + enable, port->vbus_charge); + + ret = drvops->set_vbus(dev, enable, port->vbus_charge); + if (ret < 0) + return ret; + + port->vbus_source = enable; + return 0; +} + +static int tcpm_set_charge(struct udevice *dev, bool charge) +{ + const struct dm_tcpm_ops *drvops = dev_get_driver_ops(dev); + struct tcpm_port *port = dev_get_uclass_plat(dev); + int ret; + + if (charge && port->vbus_source) + return -EINVAL; + + if (charge != port->vbus_charge) { + dev_dbg(dev, "TCPM: set vbus = %d charge = %d\n", + port->vbus_source, charge); + ret = drvops->set_vbus(dev, port->vbus_source, + charge); + if (ret < 0) + return ret; + } + port->vbus_charge = charge; + return 0; +} + +static bool tcpm_start_toggling(struct udevice *dev, enum typec_cc_status cc) +{ + const struct dm_tcpm_ops *drvops = dev_get_driver_ops(dev); + struct tcpm_port *port = dev_get_uclass_plat(dev); + int ret; + + if (!drvops->start_toggling) + return false; + + dev_dbg(dev, "TCPM: Start toggling\n"); + ret = drvops->start_toggling(dev, port->port_type, cc); + return ret == 0; +} + +static int tcpm_init_vbus(struct udevice *dev) +{ + const struct dm_tcpm_ops *drvops = dev_get_driver_ops(dev); + struct tcpm_port *port = dev_get_uclass_plat(dev); + int ret; + + ret = drvops->set_vbus(dev, false, false); + port->vbus_source = false; + port->vbus_charge = false; + return ret; +} + +static int tcpm_init_vconn(struct udevice *dev) +{ + const struct dm_tcpm_ops *drvops = dev_get_driver_ops(dev); + struct tcpm_port *port = dev_get_uclass_plat(dev); + int ret; + + ret = drvops->set_vconn(dev, false); + port->vconn_role = TYPEC_SINK; + return ret; +} + +static inline void tcpm_typec_connect(struct tcpm_port *port) +{ + if (!port->connected) + port->connected = true; +} + +static int tcpm_src_attach(struct udevice *dev) +{ + const struct dm_tcpm_ops *drvops = dev_get_driver_ops(dev); + struct tcpm_port *port = dev_get_uclass_plat(dev); + enum typec_cc_polarity polarity = + port->cc2 == TYPEC_CC_RD ? TYPEC_POLARITY_CC2 + : TYPEC_POLARITY_CC1; + int ret; + + if (port->attached) + return 0; + + ret = tcpm_set_polarity(dev, polarity); + if (ret < 0) + return ret; + + ret = tcpm_set_roles(dev, true, TYPEC_SOURCE, TYPEC_HOST); + if (ret < 0) + return ret; + + ret = drvops->set_pd_rx(dev, true); + if (ret < 0) + goto out_disable_mux; + + /* + * USB Type-C specification, version 1.2, + * chapter 4.5.2.2.8.1 (Attached.SRC Requirements) + * Enable VCONN only if the non-RD port is set to RA. + */ + if ((polarity == TYPEC_POLARITY_CC1 && port->cc2 == TYPEC_CC_RA) || + (polarity == TYPEC_POLARITY_CC2 && port->cc1 == TYPEC_CC_RA)) { + ret = tcpm_set_vconn(dev, true); + if (ret < 0) + goto out_disable_pd; + } + + ret = tcpm_set_vbus(dev, true); + if (ret < 0) + goto out_disable_vconn; + + port->pd_capable = false; + + port->partner = NULL; + + port->attached = true; + + return 0; + +out_disable_vconn: + tcpm_set_vconn(dev, false); +out_disable_pd: + drvops->set_pd_rx(dev, false); +out_disable_mux: + dev_err(dev, "TCPM: CC connected in %s as DFP\n", + polarity ? "CC2" : "CC1"); + return 0; +} + +static inline void tcpm_typec_disconnect(struct tcpm_port *port) +{ + if (port->connected) { + port->partner = NULL; + port->connected = false; + } +} + +static void tcpm_reset_port(struct udevice *dev) +{ + const struct dm_tcpm_ops *drvops = dev_get_driver_ops(dev); + struct tcpm_port *port = dev_get_uclass_plat(dev); + + tcpm_timer_uninit(dev); + tcpm_typec_disconnect(port); + tcpm_reset_event_cnt(dev); + port->wait_dr_swap_message = false; + port->attached = false; + port->pd_capable = false; + + /* + * First Rx ID should be 0; set this to a sentinel of -1 so that + * we can check tcpm_pd_rx_handler() if we had seen it before. + */ + port->rx_msgid = -1; + + drvops->set_pd_rx(dev, false); + tcpm_init_vbus(dev); /* also disables charging */ + tcpm_init_vconn(dev); + tcpm_set_current_limit(dev, 0, 0); + tcpm_set_polarity(dev, TYPEC_POLARITY_CC1); + tcpm_set_attached_state(dev, false); + port->nr_sink_caps = 0; +} + +static void tcpm_detach(struct udevice *dev) +{ + struct tcpm_port *port = dev_get_uclass_plat(dev); + + if (tcpm_port_is_disconnected(port)) + port->hard_reset_count = 0; + + if (!port->attached) + return; + + tcpm_reset_port(dev); +} + +static void tcpm_src_detach(struct udevice *dev) +{ + tcpm_detach(dev); +} + +static int tcpm_snk_attach(struct udevice *dev) +{ + struct tcpm_port *port = dev_get_uclass_plat(dev); + int ret; + + if (port->attached) + return 0; + + ret = tcpm_set_polarity(dev, port->cc2 != TYPEC_CC_OPEN ? + TYPEC_POLARITY_CC2 : TYPEC_POLARITY_CC1); + if (ret < 0) + return ret; + + ret = tcpm_set_roles(dev, true, TYPEC_SINK, TYPEC_DEVICE); + if (ret < 0) + return ret; + + port->pd_capable = false; + + port->partner = NULL; + + port->attached = true; + dev_info(dev, "TCPM: CC connected in %s as UFP\n", + port->cc1 != TYPEC_CC_OPEN ? "CC1" : "CC2"); + + return 0; +} + +static void tcpm_snk_detach(struct udevice *dev) +{ + tcpm_detach(dev); +} + +static inline enum tcpm_state hard_reset_state(struct tcpm_port *port) +{ + if (port->hard_reset_count < PD_N_HARD_RESET_COUNT) + return HARD_RESET_SEND; + if (port->pd_capable) + return ERROR_RECOVERY; + if (port->pwr_role == TYPEC_SOURCE) + return SRC_UNATTACHED; + if (port->state == SNK_WAIT_CAPABILITIES) + return SNK_READY; + return SNK_UNATTACHED; +} + +static inline enum tcpm_state unattached_state(struct tcpm_port *port) +{ + if (port->port_type == TYPEC_PORT_DRP) { + if (port->pwr_role == TYPEC_SOURCE) + return SRC_UNATTACHED; + else + return SNK_UNATTACHED; + } else if (port->port_type == TYPEC_PORT_SRC) { + return SRC_UNATTACHED; + } + + return SNK_UNATTACHED; +} + +static void run_state_machine(struct udevice *dev) +{ + const struct dm_tcpm_ops *drvops = dev_get_driver_ops(dev); + struct tcpm_port *port = dev_get_uclass_plat(dev); + int ret; + + port->enter_state = port->state; + switch (port->state) { + case TOGGLING: + break; + /* SRC states */ + case SRC_UNATTACHED: + tcpm_src_detach(dev); + if (tcpm_start_toggling(dev, tcpm_rp_cc(port))) { + tcpm_set_state(dev, TOGGLING, 0); + break; + } + tcpm_set_cc(dev, tcpm_rp_cc(port)); + if (port->port_type == TYPEC_PORT_DRP) + tcpm_set_state(dev, SNK_UNATTACHED, PD_T_DRP_SNK); + break; + case SRC_ATTACH_WAIT: + if (tcpm_port_is_source(port)) + tcpm_set_state(dev, SRC_ATTACHED, PD_T_CC_DEBOUNCE); + break; + + case SRC_ATTACHED: + ret = tcpm_src_attach(dev); + /* + * Currently, vbus control is not implemented, + * and the SRC detection process cannot be fully implemented. + */ + tcpm_set_state(dev, SRC_READY, 0); + break; + case SRC_STARTUP: + port->caps_count = 0; + port->negotiated_rev = PD_MAX_REV; + port->message_id = 0; + port->rx_msgid = -1; + port->explicit_contract = false; + tcpm_set_state(dev, SRC_SEND_CAPABILITIES, 0); + break; + case SRC_SEND_CAPABILITIES: + port->caps_count++; + if (port->caps_count > PD_N_CAPS_COUNT) { + tcpm_set_state(dev, SRC_READY, 0); + break; + } + ret = tcpm_pd_send_source_caps(dev); + if (ret < 0) { + tcpm_set_state(dev, SRC_SEND_CAPABILITIES, + PD_T_SEND_SOURCE_CAP); + } else { + /* + * Per standard, we should clear the reset counter here. + * However, that can result in state machine hang-ups. + * Reset it only in READY state to improve stability. + */ + /* port->hard_reset_count = 0; */ + port->caps_count = 0; + port->pd_capable = true; + tcpm_set_state_cond(dev, SRC_SEND_CAPABILITIES_TIMEOUT, + PD_T_SEND_SOURCE_CAP); + } + break; + case SRC_SEND_CAPABILITIES_TIMEOUT: + /* + * Error recovery for a PD_DATA_SOURCE_CAP reply timeout. + * + * PD 2.0 sinks are supposed to accept src-capabilities with a + * 3.0 header and simply ignore any src PDOs which the sink does + * not understand such as PPS but some 2.0 sinks instead ignore + * the entire PD_DATA_SOURCE_CAP message, causing contract + * negotiation to fail. + * + * After PD_N_HARD_RESET_COUNT hard-reset attempts, we try + * sending src-capabilities with a lower PD revision to + * make these broken sinks work. + */ + if (port->hard_reset_count < PD_N_HARD_RESET_COUNT) { + tcpm_set_state(dev, HARD_RESET_SEND, 0); + } else if (port->negotiated_rev > PD_REV20) { + port->negotiated_rev--; + port->hard_reset_count = 0; + tcpm_set_state(dev, SRC_SEND_CAPABILITIES, 0); + } else { + tcpm_set_state(dev, hard_reset_state(port), 0); + } + break; + case SRC_NEGOTIATE_CAPABILITIES: + ret = tcpm_pd_check_request(dev); + if (ret < 0) { + tcpm_pd_send_control(dev, PD_CTRL_REJECT); + if (!port->explicit_contract) { + tcpm_set_state(dev, + SRC_WAIT_NEW_CAPABILITIES, 0); + } else { + tcpm_set_state(dev, SRC_READY, 0); + } + } else { + tcpm_pd_send_control(dev, PD_CTRL_ACCEPT); + tcpm_set_state(dev, SRC_TRANSITION_SUPPLY, + PD_T_SRC_TRANSITION); + } + break; + case SRC_TRANSITION_SUPPLY: + /* XXX: regulator_set_voltage(vbus, ...) */ + tcpm_pd_send_control(dev, PD_CTRL_PS_RDY); + port->explicit_contract = true; + tcpm_set_state_cond(dev, SRC_READY, 0); + break; + case SRC_READY: + port->hard_reset_count = 0; + + tcpm_typec_connect(port); + break; + case SRC_WAIT_NEW_CAPABILITIES: + /* Nothing to do... */ + break; + + /* SNK states */ + case SNK_UNATTACHED: + tcpm_snk_detach(dev); + if (tcpm_start_toggling(dev, TYPEC_CC_RD)) { + tcpm_set_state(dev, TOGGLING, 0); + break; + } + tcpm_set_cc(dev, TYPEC_CC_RD); + if (port->port_type == TYPEC_PORT_DRP) + tcpm_set_state(dev, SRC_UNATTACHED, PD_T_DRP_SRC); + break; + case SNK_ATTACH_WAIT: + if ((port->cc1 == TYPEC_CC_OPEN && + port->cc2 != TYPEC_CC_OPEN) || + (port->cc1 != TYPEC_CC_OPEN && + port->cc2 == TYPEC_CC_OPEN)) + tcpm_set_state(dev, SNK_DEBOUNCED, + PD_T_CC_DEBOUNCE); + else if (tcpm_port_is_disconnected(port)) + tcpm_set_state(dev, SNK_UNATTACHED, + PD_T_CC_DEBOUNCE); + break; + case SNK_DEBOUNCED: + if (tcpm_port_is_disconnected(port)) + tcpm_set_state(dev, SNK_UNATTACHED, PD_T_PD_DEBOUNCE); + else if (port->vbus_present) + tcpm_set_state(dev, SNK_ATTACHED, 0); + else + /* Wait for VBUS, but not forever */ + tcpm_set_state(dev, PORT_RESET, PD_T_PS_SOURCE_ON); + break; + case SNK_ATTACHED: + ret = tcpm_snk_attach(dev); + if (ret < 0) + tcpm_set_state(dev, SNK_UNATTACHED, 0); + else + tcpm_set_state(dev, SNK_STARTUP, 0); + break; + case SNK_STARTUP: + port->negotiated_rev = PD_MAX_REV; + port->message_id = 0; + port->rx_msgid = -1; + port->explicit_contract = false; + tcpm_set_state(dev, SNK_DISCOVERY, 0); + break; + case SNK_DISCOVERY: + if (port->vbus_present) { + tcpm_set_current_limit(dev, + tcpm_get_current_limit(port), + 5000); + tcpm_set_charge(dev, true); + tcpm_set_state(dev, SNK_WAIT_CAPABILITIES, 0); + break; + } + /* + * For DRP, timeouts differ. Also, handling is supposed to be + * different and much more complex (dead battery detection; + * see USB power delivery specification, section 8.3.3.6.1.5.1). + */ + tcpm_set_state(dev, hard_reset_state(port), + port->port_type == TYPEC_PORT_DRP ? + PD_T_DB_DETECT : PD_T_NO_RESPONSE); + break; + case SNK_DISCOVERY_DEBOUNCE: + tcpm_set_state(dev, SNK_DISCOVERY_DEBOUNCE_DONE, + PD_T_CC_DEBOUNCE); + break; + case SNK_DISCOVERY_DEBOUNCE_DONE: + tcpm_set_state(dev, unattached_state(port), 0); + break; + case SNK_WAIT_CAPABILITIES: + ret = drvops->set_pd_rx(dev, true); + if (ret < 0) { + tcpm_set_state(dev, SNK_READY, 0); + break; + } + /* + * If VBUS has never been low, and we time out waiting + * for source cap, try a soft reset first, in case we + * were already in a stable contract before this boot. + * Do this only once. + */ + if (port->vbus_never_low) { + port->vbus_never_low = false; + tcpm_set_state(dev, SOFT_RESET_SEND, + PD_T_SINK_WAIT_CAP); + } else { + tcpm_set_state(dev, hard_reset_state(port), + PD_T_SINK_WAIT_CAP); + } + break; + case SNK_NEGOTIATE_CAPABILITIES: + port->pd_capable = true; + port->hard_reset_count = 0; + ret = tcpm_pd_send_request(dev); + if (ret < 0) { + /* Let the Source send capabilities again. */ + tcpm_set_state(dev, SNK_WAIT_CAPABILITIES, 0); + } else { + tcpm_set_state_cond(dev, hard_reset_state(port), + PD_T_SENDER_RESPONSE); + } + break; + case SNK_TRANSITION_SINK: + case SNK_TRANSITION_SINK_VBUS: + tcpm_set_state(dev, hard_reset_state(port), + PD_T_PS_TRANSITION); + break; + case SNK_READY: + port->update_sink_caps = false; + tcpm_typec_connect(port); + /* + * Here poll_event_cnt is cleared, waiting for self-powered Type-C devices + * to send DR_swap Messge until 1s (TCPM_POLL_EVENT_TIME_OUT * 500us)timeout + */ + if (port->wait_dr_swap_message) + tcpm_reset_event_cnt(dev); + + break; + + /* Hard_Reset states */ + case HARD_RESET_SEND: + tcpm_pd_transmit(dev, TCPC_TX_HARD_RESET, NULL); + tcpm_set_state(dev, HARD_RESET_START, 0); + port->wait_dr_swap_message = false; + break; + case HARD_RESET_START: + port->hard_reset_count++; + drvops->set_pd_rx(dev, false); + port->nr_sink_caps = 0; + if (port->pwr_role == TYPEC_SOURCE) + tcpm_set_state(dev, SRC_HARD_RESET_VBUS_OFF, + PD_T_PS_HARD_RESET); + else + tcpm_set_state(dev, SNK_HARD_RESET_SINK_OFF, 0); + break; + case SRC_HARD_RESET_VBUS_OFF: + tcpm_set_vconn(dev, true); + tcpm_set_vbus(dev, false); + tcpm_set_roles(dev, port->self_powered, TYPEC_SOURCE, + TYPEC_HOST); + tcpm_set_state(dev, SRC_HARD_RESET_VBUS_ON, PD_T_SRC_RECOVER); + break; + case SRC_HARD_RESET_VBUS_ON: + tcpm_set_vconn(dev, true); + tcpm_set_vbus(dev, true); + drvops->set_pd_rx(dev, true); + tcpm_set_attached_state(dev, true); + tcpm_set_state(dev, SRC_UNATTACHED, PD_T_PS_SOURCE_ON); + break; + case SNK_HARD_RESET_SINK_OFF: + tcpm_set_vconn(dev, false); + if (port->pd_capable) + tcpm_set_charge(dev, false); + tcpm_set_roles(dev, port->self_powered, TYPEC_SINK, + TYPEC_DEVICE); + /* + * VBUS may or may not toggle, depending on the adapter. + * If it doesn't toggle, transition to SNK_HARD_RESET_SINK_ON + * directly after timeout. + */ + tcpm_set_state(dev, SNK_HARD_RESET_SINK_ON, PD_T_SAFE_0V); + break; + case SNK_HARD_RESET_WAIT_VBUS: + /* Assume we're disconnected if VBUS doesn't come back. */ + tcpm_set_state(dev, SNK_UNATTACHED, + PD_T_SRC_RECOVER_MAX + PD_T_SRC_TURN_ON); + break; + case SNK_HARD_RESET_SINK_ON: + /* Note: There is no guarantee that VBUS is on in this state */ + /* + * XXX: + * The specification suggests that dual mode ports in sink + * mode should transition to state PE_SRC_Transition_to_default. + * See USB power delivery specification chapter 8.3.3.6.1.3. + * This would mean to + * - turn off VCONN, reset power supply + * - request hardware reset + * - turn on VCONN + * - Transition to state PE_Src_Startup + * SNK only ports shall transition to state Snk_Startup + * (see chapter 8.3.3.3.8). + * Similar, dual-mode ports in source mode should transition + * to PE_SNK_Transition_to_default. + */ + if (port->pd_capable) { + tcpm_set_current_limit(dev, + tcpm_get_current_limit(port), + 5000); + tcpm_set_charge(dev, true); + } + tcpm_set_attached_state(dev, true); + tcpm_set_state(dev, SNK_STARTUP, 0); + break; + + /* Soft_Reset states */ + case SOFT_RESET: + port->message_id = 0; + port->rx_msgid = -1; + tcpm_pd_send_control(dev, PD_CTRL_ACCEPT); + if (port->pwr_role == TYPEC_SOURCE) + tcpm_set_state(dev, SRC_SEND_CAPABILITIES, 0); + else + tcpm_set_state(dev, SNK_WAIT_CAPABILITIES, 0); + break; + case SOFT_RESET_SEND: + port->message_id = 0; + port->rx_msgid = -1; + if (tcpm_pd_send_control(dev, PD_CTRL_SOFT_RESET)) + tcpm_set_state_cond(dev, hard_reset_state(port), 0); + else + tcpm_set_state_cond(dev, hard_reset_state(port), + PD_T_SENDER_RESPONSE); + break; + + /* DR_Swap states */ + case DR_SWAP_ACCEPT: + tcpm_pd_send_control(dev, PD_CTRL_ACCEPT); + tcpm_set_state_cond(dev, DR_SWAP_CHANGE_DR, 0); + break; + case DR_SWAP_CHANGE_DR: + if (port->data_role == TYPEC_HOST) { + tcpm_set_roles(dev, true, port->pwr_role, + TYPEC_DEVICE); + } else { + tcpm_set_roles(dev, true, port->pwr_role, + TYPEC_HOST); + } + /* DR_swap process complete, wait_dr_swap_message is cleared */ + port->wait_dr_swap_message = false; + tcpm_set_state(dev, ready_state(port), 0); + break; + case ERROR_RECOVERY: + tcpm_set_state(dev, PORT_RESET, 0); + break; + case PORT_RESET: + tcpm_reset_port(dev); + if (port->self_powered) + tcpm_set_cc(dev, TYPEC_CC_OPEN); + else + tcpm_set_cc(dev, tcpm_default_state(port) == SNK_UNATTACHED ? + TYPEC_CC_RD : tcpm_rp_cc(port)); + tcpm_set_state(dev, PORT_RESET_WAIT_OFF, + PD_T_ERROR_RECOVERY); + break; + case PORT_RESET_WAIT_OFF: + tcpm_set_state(dev, + tcpm_default_state(port), + port->vbus_present ? PD_T_PS_SOURCE_OFF : 0); + break; + default: + dev_err(dev, "TCPM: Unexpected port state %d\n", port->state); + break; + } +} + +static void tcpm_state_machine(struct udevice *dev) +{ + struct tcpm_port *port = dev_get_uclass_plat(dev); + enum tcpm_state prev_state; + + mutex_lock(&port->lock); + port->state_machine_running = true; + + if (port->queued_message && tcpm_send_queued_message(dev)) + goto done; + + /* If we were queued due to a delayed state change, update it now */ + if (port->delayed_state) { + dev_dbg(dev, "TCPM: state change %s -> %s [delayed %ld ms]\n", + tcpm_states[port->state], + tcpm_states[port->delayed_state], port->delay_ms); + port->prev_state = port->state; + port->state = port->delayed_state; + port->delayed_state = INVALID_STATE; + } + + /* + * Continue running as long as we have (non-delayed) state changes + * to make. + */ + do { + prev_state = port->state; + run_state_machine(dev); + if (port->queued_message) + tcpm_send_queued_message(dev); + } while (port->state != prev_state && !port->delayed_state); + +done: + port->state_machine_running = false; + mutex_unlock(&port->lock); +} + +static void _tcpm_cc_change(struct udevice *dev, enum typec_cc_status cc1, + enum typec_cc_status cc2) +{ + struct tcpm_port *port = dev_get_uclass_plat(dev); + enum typec_cc_status old_cc1, old_cc2; + enum tcpm_state new_state; + + old_cc1 = port->cc1; + old_cc2 = port->cc2; + port->cc1 = cc1; + port->cc2 = cc2; + + dev_dbg(dev, "TCPM: CC1: %u -> %u, CC2: %u -> %u [state %s, polarity %d, %s]\n", + old_cc1, cc1, old_cc2, cc2, tcpm_states[port->state], + port->polarity, + tcpm_port_is_disconnected(port) ? "disconnected" : "connected"); + + switch (port->state) { + case TOGGLING: + if (tcpm_port_is_source(port)) + tcpm_set_state(dev, SRC_ATTACH_WAIT, 0); + else if (tcpm_port_is_sink(port)) + tcpm_set_state(dev, SNK_ATTACH_WAIT, 0); + break; + case SRC_UNATTACHED: + case SRC_ATTACH_WAIT: + if (tcpm_port_is_disconnected(port)) + tcpm_set_state(dev, SRC_UNATTACHED, 0); + else if (cc1 != old_cc1 || cc2 != old_cc2) + tcpm_set_state(dev, SRC_ATTACH_WAIT, 0); + break; + case SRC_ATTACHED: + case SRC_SEND_CAPABILITIES: + case SRC_READY: + if (tcpm_port_is_disconnected(port) || + !tcpm_port_is_source(port)) + tcpm_set_state(dev, SRC_UNATTACHED, 0); + break; + case SNK_UNATTACHED: + if (tcpm_port_is_sink(port)) + tcpm_set_state(dev, SNK_ATTACH_WAIT, 0); + break; + case SNK_ATTACH_WAIT: + if ((port->cc1 == TYPEC_CC_OPEN && + port->cc2 != TYPEC_CC_OPEN) || + (port->cc1 != TYPEC_CC_OPEN && + port->cc2 == TYPEC_CC_OPEN)) + new_state = SNK_DEBOUNCED; + else if (tcpm_port_is_disconnected(port)) + new_state = SNK_UNATTACHED; + else + break; + if (new_state != port->delayed_state) + tcpm_set_state(dev, SNK_ATTACH_WAIT, 0); + break; + case SNK_DEBOUNCED: + if (tcpm_port_is_disconnected(port)) + new_state = SNK_UNATTACHED; + else if (port->vbus_present) + new_state = tcpm_try_src(port) ? INVALID_STATE : SNK_ATTACHED; + else + new_state = SNK_UNATTACHED; + if (new_state != port->delayed_state) + tcpm_set_state(dev, SNK_DEBOUNCED, 0); + break; + case SNK_READY: + if (tcpm_port_is_disconnected(port)) + tcpm_set_state(dev, unattached_state(port), 0); + else if (!port->pd_capable && + (cc1 != old_cc1 || cc2 != old_cc2)) + tcpm_set_current_limit(dev, + tcpm_get_current_limit(port), + 5000); + break; + + case SNK_DISCOVERY: + /* CC line is unstable, wait for debounce */ + if (tcpm_port_is_disconnected(port)) + tcpm_set_state(dev, SNK_DISCOVERY_DEBOUNCE, 0); + break; + case SNK_DISCOVERY_DEBOUNCE: + break; + + case PORT_RESET: + case PORT_RESET_WAIT_OFF: + /* + * State set back to default mode once the timer completes. + * Ignore CC changes here. + */ + break; + default: + /* + * While acting as sink and auto vbus discharge is enabled, Allow disconnect + * to be driven by vbus disconnect. + */ + if (tcpm_port_is_disconnected(port)) + tcpm_set_state(dev, unattached_state(port), 0); + break; + } +} + +static void _tcpm_pd_vbus_on(struct udevice *dev) +{ + struct tcpm_port *port = dev_get_uclass_plat(dev); + + dev_dbg(dev, "TCPM: VBUS on event\n"); + port->vbus_present = true; + /* + * When vbus_present is true i.e. Voltage at VBUS is greater than VSAFE5V implicitly + * states that vbus is not at VSAFE0V, hence clear the vbus_vsafe0v flag here. + */ + port->vbus_vsafe0v = false; + + switch (port->state) { + case SNK_TRANSITION_SINK_VBUS: + port->explicit_contract = true; + tcpm_set_state(dev, SNK_READY, 0); + break; + case SNK_DISCOVERY: + tcpm_set_state(dev, SNK_DISCOVERY, 0); + break; + case SNK_DEBOUNCED: + tcpm_set_state(dev, SNK_ATTACHED, 0); + break; + case SNK_HARD_RESET_WAIT_VBUS: + tcpm_set_state(dev, SNK_HARD_RESET_SINK_ON, 0); + break; + case SRC_ATTACHED: + tcpm_set_state(dev, SRC_STARTUP, 0); + break; + case SRC_HARD_RESET_VBUS_ON: + tcpm_set_state(dev, SRC_STARTUP, 0); + break; + + case PORT_RESET: + case PORT_RESET_WAIT_OFF: + /* + * State set back to default mode once the timer completes. + * Ignore vbus changes here. + */ + break; + + default: + break; + } +} + +static void _tcpm_pd_vbus_off(struct udevice *dev) +{ + struct tcpm_port *port = dev_get_uclass_plat(dev); + + dev_dbg(dev, "TCPM: VBUS off event\n"); + port->vbus_present = false; + port->vbus_never_low = false; + switch (port->state) { + case SNK_HARD_RESET_SINK_OFF: + tcpm_set_state(dev, SNK_HARD_RESET_WAIT_VBUS, 0); + break; + case HARD_RESET_SEND: + break; + case SNK_ATTACH_WAIT: + tcpm_set_state(dev, SNK_UNATTACHED, 0); + break; + + case SNK_NEGOTIATE_CAPABILITIES: + break; + + case PORT_RESET_WAIT_OFF: + tcpm_set_state(dev, tcpm_default_state(port), 0); + break; + + case PORT_RESET: + /* + * State set back to default mode once the timer completes. + * Ignore vbus changes here. + */ + break; + + default: + if (port->pwr_role == TYPEC_SINK && port->attached) + tcpm_set_state(dev, SNK_UNATTACHED, 0); + break; + } +} + +void tcpm_cc_change(struct udevice *dev) +{ + const struct dm_tcpm_ops *drvops = dev_get_driver_ops(dev); + enum typec_cc_status cc1, cc2; + + tcpm_reset_event_cnt(dev); + if (drvops->get_cc(dev, &cc1, &cc2) == 0) + _tcpm_cc_change(dev, cc1, cc2); +} + +void tcpm_vbus_change(struct udevice *dev) +{ + const struct dm_tcpm_ops *drvops = dev_get_driver_ops(dev); + bool vbus; + + tcpm_reset_event_cnt(dev); + vbus = drvops->get_vbus(dev); + if (vbus) + _tcpm_pd_vbus_on(dev); + else + _tcpm_pd_vbus_off(dev); +} + +void tcpm_pd_hard_reset(struct udevice *dev) +{ + struct tcpm_port *port = dev_get_uclass_plat(dev); + + tcpm_reset_event_cnt(dev); + dev_dbg(dev, "TCPM: Received hard reset\n"); + + /* If a hard reset message is received during the port reset process, + * we should ignore it, that is, do not set port->state to HARD_RESET_START. + */ + if (port->state == PORT_RESET || port->state == PORT_RESET_WAIT_OFF) + return; + + /* + * If we keep receiving hard reset requests, executing the hard reset + * must have failed. Revert to error recovery if that happens. + */ + tcpm_set_state(dev, + port->hard_reset_count < PD_N_HARD_RESET_COUNT ? + HARD_RESET_START : ERROR_RECOVERY, + 0); +} + +static void tcpm_init(struct udevice *dev) +{ + const struct dm_tcpm_ops *drvops = dev_get_driver_ops(dev); + struct tcpm_port *port = dev_get_uclass_plat(dev); + enum typec_cc_status cc1, cc2; + + drvops->init(dev); + + tcpm_reset_port(dev); + + /* + * XXX + * Should possibly wait for VBUS to settle if it was enabled locally + * since tcpm_reset_port() will disable VBUS. + */ + port->vbus_present = drvops->get_vbus(dev); + if (port->vbus_present) + port->vbus_never_low = true; + + /* + * 1. When vbus_present is true, voltage on VBUS is already at VSAFE5V. + * So implicitly vbus_vsafe0v = false. + * + * 2. When vbus_present is false and TCPC does NOT support querying + * vsafe0v status, then, it's best to assume vbus is at VSAFE0V i.e. + * vbus_vsafe0v is true. + * + * 3. When vbus_present is false and TCPC does support querying vsafe0v, + * then, query tcpc for vsafe0v status. + */ + if (port->vbus_present) + port->vbus_vsafe0v = false; + else + port->vbus_vsafe0v = true; + + tcpm_set_state(dev, tcpm_default_state(port), 0); + + if (drvops->get_cc(dev, &cc1, &cc2) == 0) + _tcpm_cc_change(dev, cc1, cc2); +} + +static int tcpm_fw_get_caps(struct udevice *dev) +{ + const struct dm_tcpm_ops *drvops = dev_get_driver_ops(dev); + struct tcpm_port *port = dev_get_uclass_plat(dev); + ofnode node; + const char *cap_str; + int ret; + u32 mw; + + ret = drvops->get_connector_node(dev, &node); + if (ret) + return ret; + + cap_str = ofnode_read_string(node, "power-role"); + if (!cap_str) + return -EINVAL; + + if (!strcmp("dual", cap_str)) + port->typec_type = TYPEC_PORT_DRP; + else if (!strcmp("source", cap_str)) + port->typec_type = TYPEC_PORT_SRC; + else if (!strcmp("sink", cap_str)) + port->typec_type = TYPEC_PORT_SNK; + else + return -EINVAL; + + port->port_type = port->typec_type; + + if (port->port_type == TYPEC_PORT_SNK) + goto sink; + + /* Get source pdos */ + ret = ofnode_read_size(node, "source-pdos") / sizeof(u32); + if (ret <= 0) + return -EINVAL; + + port->nr_src_pdo = min(ret, PDO_MAX_OBJECTS); + ret = ofnode_read_u32_array(node, "source-pdos", + port->src_pdo, port->nr_src_pdo); + if (ret || tcpm_validate_caps(dev, port->src_pdo, port->nr_src_pdo)) + return -EINVAL; + + if (port->port_type == TYPEC_PORT_SRC) + return 0; + + /* Get the preferred power role for DRP */ + cap_str = ofnode_read_string(node, "try-power-role"); + if (!cap_str) + return -EINVAL; + + if (!strcmp("sink", cap_str)) + port->typec_prefer_role = TYPEC_SINK; + else if (!strcmp("source", cap_str)) + port->typec_prefer_role = TYPEC_SOURCE; + else + return -EINVAL; + + if (port->typec_prefer_role < 0) + return -EINVAL; +sink: + /* Get sink pdos */ + ret = ofnode_read_size(node, "sink-pdos") / sizeof(u32); + if (ret <= 0) + return -EINVAL; + + port->nr_snk_pdo = min(ret, PDO_MAX_OBJECTS); + ret = ofnode_read_u32_array(node, "sink-pdos", + port->snk_pdo, port->nr_snk_pdo); + if (ret || tcpm_validate_caps(dev, port->snk_pdo, port->nr_snk_pdo)) + return -EINVAL; + + if (ofnode_read_u32_array(node, "op-sink-microwatt", &mw, 1)) + return -EINVAL; + port->operating_snk_mw = mw / 1000; + + port->self_powered = ofnode_read_bool(node, "self-powered"); + + return 0; +} + +static int tcpm_port_init(struct udevice *dev) +{ + struct tcpm_port *port = dev_get_uclass_plat(dev); + int err; + + err = tcpm_fw_get_caps(dev); + if (err < 0) { + dev_err(dev, "TCPM: please check the dts config: %d\n", err); + return err; + } + + port->try_role = port->typec_prefer_role; + port->port_type = port->typec_type; + + tcpm_init(dev); + + dev_info(dev, "TCPM: init finished\n"); + + return 0; +} + +static void tcpm_poll_event(struct udevice *dev) +{ + const struct dm_tcpm_ops *drvops = dev_get_driver_ops(dev); + struct tcpm_port *port = dev_get_uclass_plat(dev); + + if (!drvops->get_vbus(dev)) + return; + + while (port->poll_event_cnt < TCPM_POLL_EVENT_TIME_OUT) { + if (!port->wait_dr_swap_message && + (port->state == SNK_READY || port->state == SRC_READY)) + break; + + drvops->poll_event(dev); + port->poll_event_cnt++; + udelay(500); + tcpm_check_and_run_delayed_work(dev); + } + + if (port->state != SNK_READY && port->state != SRC_READY) + dev_warn(dev, "TCPM: exit in state %s\n", + tcpm_states[port->state]); + + /* + * At this time, call the callback function of the respective pd chip + * to enter the low-power mode. In order to reduce the time spent on + * the PD chip driver as much as possible, the tcpm framework does not + * fully process the communication initiated by the device,so it should + * be noted that we can disable the internal oscillator, etc., but do + * not turn off the power of the transceiver module, otherwise the + * self-powered Type-C device will initiate a Message(eg: self-powered + * Type-C hub initiates a SINK capability request(PD_CTRL_GET_SINK_CAP)) + * and the pd chip cannot reply to GoodCRC, causing the self-powered Type-C + * device to switch vbus to vSafe5v, or even turn off vbus. + */ + if (!drvops->enter_low_power_mode) + return; + + if (drvops->enter_low_power_mode(dev, port->attached, port->pd_capable)) + dev_err(dev, "TCPM: failed to enter low power\n"); + else + dev_info(dev, "TCPM: PD chip enter low power mode\n"); +} + +int tcpm_post_probe(struct udevice *dev) +{ + int ret = tcpm_port_init(dev); + + if (ret < 0) { + dev_err(dev, "failed to tcpm port init\n"); + return ret; + } + + tcpm_poll_event(dev); + + return 0; +} diff --git a/drivers/video/vidconsole-uclass.c b/drivers/video/vidconsole-uclass.c index 80e7adf6a1a..ebe96bf0c2f 100644 --- a/drivers/video/vidconsole-uclass.c +++ b/drivers/video/vidconsole-uclass.c @@ -94,7 +94,9 @@ static void vidconsole_newline(struct udevice *dev) priv->ycur += priv->y_charsize; /* Check if we need to scroll the terminal */ - if ((priv->ycur + priv->y_charsize) / priv->y_charsize > priv->rows) { + if (vid_priv->rot % 2 ? + priv->ycur + priv->x_charsize > vid_priv->xsize : + priv->ycur + priv->y_charsize > vid_priv->ysize) { vidconsole_move_rows(dev, 0, rows, priv->rows - rows); for (i = 0; i < rows; i++) vidconsole_set_row(dev, priv->rows - i - 1, diff --git a/drivers/video/video-uclass.c b/drivers/video/video-uclass.c index 9823673f817..a5b3e898066 100644 --- a/drivers/video/video-uclass.c +++ b/drivers/video/video-uclass.c @@ -294,6 +294,9 @@ static const struct vid_rgb colours[VID_COLOUR_COUNT] = { { 0xff, 0x00, 0xff }, /* bright magenta */ { 0x00, 0xff, 0xff }, /* bright cyan */ { 0xff, 0xff, 0xff }, /* white */ + + /* an extra one for menus */ + { 0x40, 0x40, 0x40 }, /* dark gray */ }; u32 video_index_to_colour(struct video_priv *priv, enum colour_idx idx) diff --git a/drivers/virtio/virtio_blk.c b/drivers/virtio/virtio_blk.c index 3404f61eba5..2f999fc8bbe 100644 --- a/drivers/virtio/virtio_blk.c +++ b/drivers/virtio/virtio_blk.c @@ -18,30 +18,82 @@ struct virtio_blk_priv { struct virtqueue *vq; }; +static const u32 feature[] = { + VIRTIO_BLK_F_WRITE_ZEROES +}; + +static void virtio_blk_init_header_sg(struct udevice *dev, u64 sector, u32 type, + struct virtio_blk_outhdr *out_hdr, struct virtio_sg *sg) +{ + const bool sector_is_needed = type == VIRTIO_BLK_T_IN || + type == VIRTIO_BLK_T_OUT; + + out_hdr->type = cpu_to_virtio32(dev, type); + out_hdr->sector = cpu_to_virtio64(dev, sector_is_needed ? sector : 0); + + sg->addr = out_hdr; + sg->length = sizeof(*out_hdr); +} + +static void virtio_blk_init_write_zeroes_sg(struct udevice *dev, u64 sector, lbaint_t blkcnt, + struct virtio_blk_discard_write_zeroes *wz, + struct virtio_sg *sg) +{ + wz->sector = cpu_to_virtio64(dev, sector); + wz->num_sectors = cpu_to_virtio32(dev, blkcnt); + wz->flags = cpu_to_virtio32(dev, 0); + + sg->addr = wz; + sg->length = sizeof(*wz); +} + +static void virtio_blk_init_status_sg(u8 *status, struct virtio_sg *sg) +{ + sg->addr = status; + sg->length = sizeof(*status); +} + +static void virtio_blk_init_data_sg(void *buffer, lbaint_t blkcnt, struct virtio_sg *sg) +{ + sg->addr = buffer; + sg->length = blkcnt * 512; +} + static ulong virtio_blk_do_req(struct udevice *dev, u64 sector, lbaint_t blkcnt, void *buffer, u32 type) { struct virtio_blk_priv *priv = dev_get_priv(dev); + struct virtio_blk_outhdr out_hdr; + struct virtio_blk_discard_write_zeroes wz_hdr; unsigned int num_out = 0, num_in = 0; + struct virtio_sg hdr_sg, wz_sg, data_sg, status_sg; struct virtio_sg *sgs[3]; u8 status; int ret; - struct virtio_blk_outhdr out_hdr = { - .type = cpu_to_virtio32(dev, type), - .sector = cpu_to_virtio64(dev, sector), - }; - struct virtio_sg hdr_sg = { &out_hdr, sizeof(out_hdr) }; - struct virtio_sg data_sg = { buffer, blkcnt * 512 }; - struct virtio_sg status_sg = { &status, sizeof(status) }; - + virtio_blk_init_header_sg(dev, sector, type, &out_hdr, &hdr_sg); sgs[num_out++] = &hdr_sg; - if (type & VIRTIO_BLK_T_OUT) - sgs[num_out++] = &data_sg; - else - sgs[num_out + num_in++] = &data_sg; - + switch (type) { + case VIRTIO_BLK_T_IN: + case VIRTIO_BLK_T_OUT: + virtio_blk_init_data_sg(buffer, blkcnt, &data_sg); + if (type & VIRTIO_BLK_T_OUT) + sgs[num_out++] = &data_sg; + else + sgs[num_out + num_in++] = &data_sg; + break; + + case VIRTIO_BLK_T_WRITE_ZEROES: + virtio_blk_init_write_zeroes_sg(dev, sector, blkcnt, &wz_hdr, &wz_sg); + sgs[num_out++] = &wz_sg; + break; + + default: + return -EINVAL; + } + + virtio_blk_init_status_sg(&status, &status_sg); sgs[num_out + num_in++] = &status_sg; log_debug("dev=%s, active=%d, priv=%p, priv->vq=%p\n", dev->name, device_active(dev), priv, priv->vq); @@ -75,6 +127,15 @@ static ulong virtio_blk_write(struct udevice *dev, lbaint_t start, VIRTIO_BLK_T_OUT); } +static ulong virtio_blk_erase(struct udevice *dev, lbaint_t start, + lbaint_t blkcnt) +{ + if (!virtio_has_feature(dev, VIRTIO_BLK_F_WRITE_ZEROES)) + return -EOPNOTSUPP; + + return virtio_blk_do_req(dev, start, blkcnt, NULL, VIRTIO_BLK_T_WRITE_ZEROES); +} + static int virtio_blk_bind(struct udevice *dev) { struct virtio_dev_priv *uc_priv = dev_get_uclass_priv(dev->parent); @@ -104,7 +165,8 @@ static int virtio_blk_bind(struct udevice *dev) desc->bdev = dev; /* Indicate what driver features we support */ - virtio_driver_features_init(uc_priv, NULL, 0, NULL, 0); + virtio_driver_features_init(uc_priv, feature, ARRAY_SIZE(feature), + NULL, 0); return 0; } @@ -131,6 +193,7 @@ static int virtio_blk_probe(struct udevice *dev) static const struct blk_ops virtio_blk_ops = { .read = virtio_blk_read, .write = virtio_blk_write, + .erase = virtio_blk_erase, }; U_BOOT_DRIVER(virtio_blk) = { diff --git a/drivers/virtio/virtio_blk.h b/drivers/virtio/virtio_blk.h index 8d8e02fa2ea..b37ba264df4 100644 --- a/drivers/virtio/virtio_blk.h +++ b/drivers/virtio/virtio_blk.h @@ -17,6 +17,8 @@ #define VIRTIO_BLK_F_BLK_SIZE 6 /* Block size of disk is available */ #define VIRTIO_BLK_F_TOPOLOGY 10 /* Topology information is available */ #define VIRTIO_BLK_F_MQ 12 /* Support more than one vq */ +#define VIRTIO_BLK_F_DISCARD 13 /* Discard is supported */ +#define VIRTIO_BLK_F_WRITE_ZEROES 14 /* Write zeroes is supported */ /* Legacy feature bits */ #ifndef VIRTIO_BLK_NO_LEGACY @@ -65,6 +67,39 @@ struct __packed virtio_blk_config { /* number of vqs, only available when VIRTIO_BLK_F_MQ is set */ __u16 num_queues; + + /* the next 3 entries are guarded by VIRTIO_BLK_F_DISCARD */ + /* + * The maximum discard sectors (in 512-byte sectors) for + * one segment. + */ + __u32 max_discard_sectors; + /* + * The maximum number of discard segments in a + * discard command. + */ + __u32 max_discard_seg; + /* Discard commands must be aligned to this number of sectors. */ + __u32 discard_sector_alignment; + + /* the next 3 entries are guarded by VIRTIO_BLK_F_WRITE_ZEROES */ + /* + * The maximum number of write zeroes sectors (in 512-byte sectors) in + * one segment. + */ + __u32 max_write_zeroes_sectors; + /* + * The maximum number of segments in a write zeroes + * command. + */ + __u32 max_write_zeroes_seg; + /* + * Set if a VIRTIO_BLK_T_WRITE_ZEROES request may result in the + * deallocation of one or more of the sectors. + */ + __u8 write_zeroes_may_unmap; + + __u8 unused1[3]; }; /* @@ -93,6 +128,9 @@ struct __packed virtio_blk_config { /* Get device ID command */ #define VIRTIO_BLK_T_GET_ID 8 +/* Write zeroes command */ +#define VIRTIO_BLK_T_WRITE_ZEROES 13 + #ifndef VIRTIO_BLK_NO_LEGACY /* Barrier before this op */ #define VIRTIO_BLK_T_BARRIER 0x80000000 @@ -112,6 +150,15 @@ struct virtio_blk_outhdr { __virtio64 sector; }; +struct virtio_blk_discard_write_zeroes { + /* discard/write zeroes start sector */ + __virtio64 sector; + /* number of discard/write zeroes sectors */ + __virtio32 num_sectors; + /* flags for this range */ + __virtio32 flags; +}; + #ifndef VIRTIO_BLK_NO_LEGACY struct virtio_scsi_inhdr { __virtio32 errors; |