diff options
Diffstat (limited to 'drivers')
37 files changed, 2544 insertions, 1915 deletions
diff --git a/drivers/block/sandbox.c b/drivers/block/sandbox.c index ec34f1ad8c2..6c74d66037e 100644 --- a/drivers/block/sandbox.c +++ b/drivers/block/sandbox.c @@ -25,7 +25,7 @@ static unsigned long host_block_read(struct udevice *dev, struct udevice *host_dev = dev_get_parent(dev); struct host_sb_plat *plat = dev_get_plat(host_dev); - if (os_lseek(plat->fd, start * desc->blksz, OS_SEEK_SET) == -1) { + if (os_lseek(plat->fd, start * desc->blksz, OS_SEEK_SET) < 0) { printf("ERROR: Invalid block %lx\n", start); return -1; } @@ -44,7 +44,7 @@ static unsigned long host_block_write(struct udevice *dev, struct udevice *host_dev = dev_get_parent(dev); struct host_sb_plat *plat = dev_get_plat(host_dev); - if (os_lseek(plat->fd, start * desc->blksz, OS_SEEK_SET) == -1) { + if (os_lseek(plat->fd, start * desc->blksz, OS_SEEK_SET) < 0) { printf("ERROR: Invalid block %lx\n", start); return -1; } diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c index 2beb63030f2..23b9787612a 100644 --- a/drivers/clk/mediatek/clk-mt7622.c +++ b/drivers/clk/mediatek/clk-mt7622.c @@ -66,6 +66,24 @@ static const struct mtk_pll_data apmixed_plls[] = { 21, 0x358, 1, 0x35c, 0), }; +static const struct mtk_gate_regs apmixed_cg_regs = { + .set_ofs = 0x8, + .clr_ofs = 0x8, + .sta_ofs = 0x8, +}; + +#define GATE_APMIXED(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &apmixed_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_NO_SETCLR_INV, \ + } + +static const struct mtk_gate apmixed_cgs[] = { + GATE_APMIXED(CLK_APMIXED_MAIN_CORE_EN, CLK_APMIXED_MAINPLL, 5), +}; + /* topckgen */ #define FACTOR0(_id, _parent, _mult, _div) \ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) @@ -366,6 +384,20 @@ static const struct mtk_composite top_muxes[] = { }; /* infracfg */ +#define APMIXED_PARENT(_id) PARENT(_id, CLK_PARENT_APMIXED) +#define XTAL_PARENT(_id) PARENT(_id, CLK_PARENT_XTAL) + +static const struct mtk_parent infra_mux1_parents[] = { + XTAL_PARENT(CLK_XTAL), + APMIXED_PARENT(CLK_APMIXED_MAINPLL), + APMIXED_PARENT(CLK_APMIXED_MAIN_CORE_EN), + APMIXED_PARENT(CLK_APMIXED_MAINPLL), +}; + +static const struct mtk_composite infra_muxes[] = { + MUX_MIXED(CLK_INFRA_MUX1_SEL, infra_mux1_parents, 0x000, 2, 2), +}; + static const struct mtk_gate_regs infra_cg_regs = { .set_ofs = 0x40, .clr_ofs = 0x44, @@ -382,14 +414,26 @@ static const struct mtk_gate_regs infra_cg_regs = { static const struct mtk_gate infra_cgs[] = { GATE_INFRA(CLK_INFRA_DBGCLK_PD, CLK_TOP_AXI_SEL, 0), - GATE_INFRA(CLK_INFRA_TRNG, CLK_TOP_AXI_SEL, 2), GATE_INFRA(CLK_INFRA_AUDIO_PD, CLK_TOP_AUD_INTBUS_SEL, 5), GATE_INFRA(CLK_INFRA_IRRX_PD, CLK_TOP_IRRX_SEL, 16), GATE_INFRA(CLK_INFRA_APXGPT_PD, CLK_TOP_F10M_REF_SEL, 18), GATE_INFRA(CLK_INFRA_PMIC_PD, CLK_TOP_PMICSPI_SEL, 22), + GATE_INFRA(CLK_INFRA_TRNG, CLK_TOP_AXI_SEL, 2), }; /* pericfg */ +static const int peribus_ck_parents[] = { + CLK_TOP_SYSPLL1_D8, + CLK_TOP_SYSPLL1_D4, +}; + +#define PERI_MUX(_id, _parents, _reg, _shift, _width) \ + MUX_FLAGS(_id, _parents, _reg, _shift, _width, CLK_PARENT_TOPCKGEN) + +static const struct mtk_composite peri_muxes[] = { + PERI_MUX(CLK_PERIBUS_SEL, peribus_ck_parents, 0x05c, 0, 1), +}; + static const struct mtk_gate_regs peri0_cg_regs = { .set_ofs = 0x8, .clr_ofs = 0x10, @@ -402,13 +446,17 @@ static const struct mtk_gate_regs peri1_cg_regs = { .sta_ofs = 0x1C, }; -#define GATE_PERI0(_id, _parent, _shift) { \ +#define GATE_PERI0_FLAGS(_id, _parent, _shift, _flags) { \ .id = _id, \ .parent = _parent, \ .regs = &peri0_cg_regs, \ .shift = _shift, \ - .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ + .flags = _flags, \ } +#define GATE_PERI0(_id, _parent, _shift) \ + GATE_PERI0_FLAGS(_id, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) +#define GATE_PERI0_XTAL(_id, _parent, _shift) \ + GATE_PERI0_FLAGS(_id, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_XTAL) #define GATE_PERI1(_id, _parent, _shift) { \ .id = _id, \ @@ -421,14 +469,14 @@ static const struct mtk_gate_regs peri1_cg_regs = { static const struct mtk_gate peri_cgs[] = { /* PERI0 */ GATE_PERI0(CLK_PERI_THERM_PD, CLK_TOP_AXI_SEL, 1), - GATE_PERI0(CLK_PERI_PWM1_PD, CLK_XTAL, 2), - GATE_PERI0(CLK_PERI_PWM2_PD, CLK_XTAL, 3), - GATE_PERI0(CLK_PERI_PWM3_PD, CLK_XTAL, 4), - GATE_PERI0(CLK_PERI_PWM4_PD, CLK_XTAL, 5), - GATE_PERI0(CLK_PERI_PWM5_PD, CLK_XTAL, 6), - GATE_PERI0(CLK_PERI_PWM6_PD, CLK_XTAL, 7), - GATE_PERI0(CLK_PERI_PWM7_PD, CLK_XTAL, 8), - GATE_PERI0(CLK_PERI_PWM_PD, CLK_XTAL, 9), + GATE_PERI0_XTAL(CLK_PERI_PWM1_PD, CLK_XTAL, 2), + GATE_PERI0_XTAL(CLK_PERI_PWM2_PD, CLK_XTAL, 3), + GATE_PERI0_XTAL(CLK_PERI_PWM3_PD, CLK_XTAL, 4), + GATE_PERI0_XTAL(CLK_PERI_PWM4_PD, CLK_XTAL, 5), + GATE_PERI0_XTAL(CLK_PERI_PWM5_PD, CLK_XTAL, 6), + GATE_PERI0_XTAL(CLK_PERI_PWM6_PD, CLK_XTAL, 7), + GATE_PERI0_XTAL(CLK_PERI_PWM7_PD, CLK_XTAL, 8), + GATE_PERI0_XTAL(CLK_PERI_PWM_PD, CLK_XTAL, 9), GATE_PERI0(CLK_PERI_AP_DMA_PD, CLK_TOP_AXI_SEL, 12), GATE_PERI0(CLK_PERI_MSDC30_0_PD, CLK_TOP_MSDC30_0_SEL, 13), GATE_PERI0(CLK_PERI_MSDC30_1_PD, CLK_TOP_MSDC30_1_SEL, 14), @@ -436,12 +484,13 @@ static const struct mtk_gate peri_cgs[] = { GATE_PERI0(CLK_PERI_UART1_PD, CLK_TOP_AXI_SEL, 18), GATE_PERI0(CLK_PERI_UART2_PD, CLK_TOP_AXI_SEL, 19), GATE_PERI0(CLK_PERI_UART3_PD, CLK_TOP_AXI_SEL, 20), + GATE_PERI0(CLK_PERI_UART4_PD, CLK_TOP_AXI_SEL, 21), GATE_PERI0(CLK_PERI_BTIF_PD, CLK_TOP_AXI_SEL, 22), GATE_PERI0(CLK_PERI_I2C0_PD, CLK_TOP_AXI_SEL, 23), GATE_PERI0(CLK_PERI_I2C1_PD, CLK_TOP_AXI_SEL, 24), GATE_PERI0(CLK_PERI_I2C2_PD, CLK_TOP_AXI_SEL, 25), GATE_PERI0(CLK_PERI_SPI1_PD, CLK_TOP_SPI1_SEL, 26), - GATE_PERI0(CLK_PERI_AUXADC_PD, CLK_XTAL, 27), + GATE_PERI0_XTAL(CLK_PERI_AUXADC_PD, CLK_XTAL, 27), GATE_PERI0(CLK_PERI_SPI0_PD, CLK_TOP_SPI0_SEL, 28), GATE_PERI0(CLK_PERI_SNFI_PD, CLK_TOP_NFI_INFRA_SEL, 29), GATE_PERI0(CLK_PERI_NFI_PD, CLK_TOP_AXI_SEL, 30), @@ -550,12 +599,33 @@ static const struct mtk_gate ssusb_cgs[] = { GATE_SSUSB(CLK_SSUSB_DMA_EN, CLK_TOP_HIF_SEL, 8), }; +static const struct mtk_clk_tree mt7622_apmixed_clk_tree = { + .xtal2_rate = 25 * MHZ, + .plls = apmixed_plls, + .gates_offs = CLK_APMIXED_MAIN_CORE_EN, + .gates = apmixed_cgs, +}; + +static const struct mtk_clk_tree mt7622_infra_clk_tree = { + .xtal_rate = 25 * MHZ, + .muxes_offs = CLK_INFRA_MUX1_SEL, + .gates_offs = CLK_INFRA_DBGCLK_PD, + .muxes = infra_muxes, + .gates = infra_cgs, +}; + +static const struct mtk_clk_tree mt7622_peri_clk_tree = { + .xtal_rate = 25 * MHZ, + .muxes_offs = CLK_PERIBUS_SEL, + .gates_offs = CLK_PERI_THERM_PD, + .muxes = peri_muxes, + .gates = peri_cgs, +}; + static const struct mtk_clk_tree mt7622_clk_tree = { .xtal_rate = 25 * MHZ, - .xtal2_rate = 25 * MHZ, .fdivs_offs = CLK_TOP_TO_USB3_SYS, .muxes_offs = CLK_TOP_AXI_SEL, - .plls = apmixed_plls, .fclks = top_fixed_clks, .fdivs = top_fixed_divs, .muxes = top_muxes, @@ -582,7 +652,7 @@ static int mt7622_apmixedsys_probe(struct udevice *dev) struct mtk_clk_priv *priv = dev_get_priv(dev); int ret; - ret = mtk_common_clk_init(dev, &mt7622_clk_tree); + ret = mtk_common_clk_init(dev, &mt7622_apmixed_clk_tree); if (ret) return ret; @@ -603,12 +673,12 @@ static int mt7622_topckgen_probe(struct udevice *dev) static int mt7622_infracfg_probe(struct udevice *dev) { - return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, infra_cgs); + return mtk_common_clk_infrasys_init(dev, &mt7622_infra_clk_tree); } static int mt7622_pericfg_probe(struct udevice *dev) { - return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, peri_cgs); + return mtk_common_clk_infrasys_init(dev, &mt7622_peri_clk_tree); } static int mt7622_pciesys_probe(struct udevice *dev) diff --git a/drivers/clk/mediatek/clk-mt7623.c b/drivers/clk/mediatek/clk-mt7623.c index 5072c9983c1..d0b80f48b0a 100644 --- a/drivers/clk/mediatek/clk-mt7623.c +++ b/drivers/clk/mediatek/clk-mt7623.c @@ -25,6 +25,22 @@ #define AXI_DIV_SEL(x) (x) /* apmixedsys */ +static const int pll_id_offs_map[] = { + [CLK_APMIXED_ARMPLL] = 0, + [CLK_APMIXED_MAINPLL] = 1, + [CLK_APMIXED_UNIVPLL] = 2, + [CLK_APMIXED_MMPLL] = 3, + [CLK_APMIXED_MSDCPLL] = 4, + [CLK_APMIXED_TVDPLL] = 5, + [CLK_APMIXED_AUD1PLL] = 6, + [CLK_APMIXED_TRGPLL] = 7, + [CLK_APMIXED_ETHPLL] = 8, + [CLK_APMIXED_VDECPLL] = 9, + [CLK_APMIXED_HADDS2PLL] = 10, + [CLK_APMIXED_AUD2PLL] = 11, + [CLK_APMIXED_TVD2PLL] = 12, +}; + #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ _pd_shift, _pcw_reg, _pcw_shift) { \ .id = _id, \ @@ -71,6 +87,176 @@ static const struct mtk_pll_data apmixed_plls[] = { }; /* topckgen */ + +/* Fixed CLK exposed upstream by the hdmi PHY driver */ +#define CLK_TOP_HDMITX_CLKDIG_CTS CLK_TOP_NR + +static const int top_id_offs_map[CLK_TOP_NR + 1] = { + /* Fixed CLK */ + [CLK_TOP_DPI] = 0, + [CLK_TOP_DMPLL] = 1, + [CLK_TOP_VENCPLL] = 2, + [CLK_TOP_HDMI_0_PIX340M] = 3, + [CLK_TOP_HDMI_0_DEEP340M] = 4, + [CLK_TOP_HDMI_0_PLL340M] = 5, + [CLK_TOP_HADDS2_FB] = 6, + [CLK_TOP_WBG_DIG_416M] = 7, + [CLK_TOP_DSI0_LNTC_DSI] = 8, + [CLK_TOP_HDMI_SCL_RX] = 9, + [CLK_TOP_32K_EXTERNAL] = 10, + [CLK_TOP_HDMITX_CLKDIG_CTS] = 11, + [CLK_TOP_AUD_EXT1] = 12, + [CLK_TOP_AUD_EXT2] = 13, + [CLK_TOP_NFI1X_PAD] = 14, + /* Factor CLK */ + [CLK_TOP_SYSPLL] = 15, + [CLK_TOP_SYSPLL_D2] = 16, + [CLK_TOP_SYSPLL_D3] = 17, + [CLK_TOP_SYSPLL_D5] = 18, + [CLK_TOP_SYSPLL_D7] = 19, + [CLK_TOP_SYSPLL1_D2] = 20, + [CLK_TOP_SYSPLL1_D4] = 21, + [CLK_TOP_SYSPLL1_D8] = 22, + [CLK_TOP_SYSPLL1_D16] = 23, + [CLK_TOP_SYSPLL2_D2] = 24, + [CLK_TOP_SYSPLL2_D4] = 25, + [CLK_TOP_SYSPLL2_D8] = 26, + [CLK_TOP_SYSPLL3_D2] = 27, + [CLK_TOP_SYSPLL3_D4] = 28, + [CLK_TOP_SYSPLL4_D2] = 29, + [CLK_TOP_SYSPLL4_D4] = 30, + [CLK_TOP_UNIVPLL] = 31, + [CLK_TOP_UNIVPLL_D2] = 32, + [CLK_TOP_UNIVPLL_D3] = 33, + [CLK_TOP_UNIVPLL_D5] = 34, + [CLK_TOP_UNIVPLL_D7] = 35, + [CLK_TOP_UNIVPLL_D26] = 36, + [CLK_TOP_UNIVPLL_D52] = 37, + [CLK_TOP_UNIVPLL_D108] = 38, + [CLK_TOP_USB_PHY48M] = 39, + [CLK_TOP_UNIVPLL1_D2] = 40, + [CLK_TOP_UNIVPLL1_D4] = 41, + [CLK_TOP_UNIVPLL1_D8] = 42, + [CLK_TOP_UNIVPLL2_D2] = 43, + [CLK_TOP_UNIVPLL2_D4] = 44, + [CLK_TOP_UNIVPLL2_D8] = 45, + [CLK_TOP_UNIVPLL2_D16] = 46, + [CLK_TOP_UNIVPLL2_D32] = 47, + [CLK_TOP_UNIVPLL3_D2] = 48, + [CLK_TOP_UNIVPLL3_D4] = 49, + [CLK_TOP_UNIVPLL3_D8] = 50, + [CLK_TOP_MSDCPLL] = 51, + [CLK_TOP_MSDCPLL_D2] = 52, + [CLK_TOP_MSDCPLL_D4] = 53, + [CLK_TOP_MSDCPLL_D8] = 54, + [CLK_TOP_MMPLL] = 55, + [CLK_TOP_MMPLL_D2] = 56, + [CLK_TOP_DMPLL_D2] = 57, + [CLK_TOP_DMPLL_D4] = 58, + [CLK_TOP_DMPLL_X2] = 59, + [CLK_TOP_TVDPLL] = 60, + [CLK_TOP_TVDPLL_D2] = 61, + [CLK_TOP_TVDPLL_D4] = 62, + [CLK_TOP_VDECPLL] = 63, + [CLK_TOP_TVD2PLL] = 64, + [CLK_TOP_TVD2PLL_D2] = 65, + [CLK_TOP_MIPIPLL] = 66, + [CLK_TOP_MIPIPLL_D2] = 67, + [CLK_TOP_MIPIPLL_D4] = 68, + [CLK_TOP_HDMIPLL] = 69, + [CLK_TOP_HDMIPLL_D2] = 70, + [CLK_TOP_HDMIPLL_D3] = 71, + [CLK_TOP_ARMPLL_1P3G] = 72, + [CLK_TOP_AUDPLL] = 73, + [CLK_TOP_AUDPLL_D4] = 74, + [CLK_TOP_AUDPLL_D8] = 75, + [CLK_TOP_AUDPLL_D16] = 76, + [CLK_TOP_AUDPLL_D24] = 77, + [CLK_TOP_AUD1PLL_98M] = 78, + [CLK_TOP_AUD2PLL_90M] = 79, + [CLK_TOP_HADDS2PLL_98M] = 80, + [CLK_TOP_HADDS2PLL_294M] = 81, + [CLK_TOP_ETHPLL_500M] = 82, + [CLK_TOP_CLK26M_D8] = 83, + [CLK_TOP_32K_INTERNAL] = 84, + [CLK_TOP_AXISEL_D4] = 85, + [CLK_TOP_8BDAC] = 86, + /* MUX CLK */ + [CLK_TOP_AXI_SEL] = 87, + [CLK_TOP_MEM_SEL] = 88, + [CLK_TOP_DDRPHYCFG_SEL] = 89, + [CLK_TOP_MM_SEL] = 90, + [CLK_TOP_PWM_SEL] = 91, + [CLK_TOP_VDEC_SEL] = 92, + [CLK_TOP_MFG_SEL] = 93, + [CLK_TOP_CAMTG_SEL] = 94, + [CLK_TOP_UART_SEL] = 95, + [CLK_TOP_SPI0_SEL] = 96, + [CLK_TOP_USB20_SEL] = 97, + [CLK_TOP_MSDC30_0_SEL] = 98, + [CLK_TOP_MSDC30_1_SEL] = 99, + [CLK_TOP_MSDC30_2_SEL] = 100, + [CLK_TOP_AUDIO_SEL] = 101, + [CLK_TOP_AUDINTBUS_SEL] = 102, + [CLK_TOP_PMICSPI_SEL] = 103, + [CLK_TOP_SCP_SEL] = 104, + [CLK_TOP_DPI0_SEL] = 105, + [CLK_TOP_DPI1_SEL] = 106, + [CLK_TOP_TVE_SEL] = 107, + [CLK_TOP_HDMI_SEL] = 108, + [CLK_TOP_APLL_SEL] = 109, + [CLK_TOP_RTC_SEL] = 110, + [CLK_TOP_NFI2X_SEL] = 111, + [CLK_TOP_EMMC_HCLK_SEL] = 112, + [CLK_TOP_FLASH_SEL] = 113, + [CLK_TOP_DI_SEL] = 114, + [CLK_TOP_NR_SEL] = 115, + [CLK_TOP_OSD_SEL] = 116, + [CLK_TOP_HDMIRX_BIST_SEL] = 117, + [CLK_TOP_INTDIR_SEL] = 118, + [CLK_TOP_ASM_I_SEL] = 119, + [CLK_TOP_ASM_M_SEL] = 120, + [CLK_TOP_ASM_H_SEL] = 121, + [CLK_TOP_MS_CARD_SEL] = 122, + [CLK_TOP_ETHIF_SEL] = 123, + [CLK_TOP_HDMIRX26_24_SEL] = 124, + [CLK_TOP_MSDC30_3_SEL] = 125, + [CLK_TOP_CMSYS_SEL] = 126, + [CLK_TOP_SPI1_SEL] = 127, + [CLK_TOP_SPI2_SEL] = 128, + [CLK_TOP_8BDAC_SEL] = 129, + [CLK_TOP_AUD2DVD_SEL] = 130, + [CLK_TOP_PADMCLK_SEL] = 131, + [CLK_TOP_AUD_MUX1_SEL] = 132, + [CLK_TOP_AUD_MUX2_SEL] = 133, + [CLK_TOP_AUDPLL_MUX_SEL] = 134, + [CLK_TOP_AUD_K1_SRC_SEL] = 135, + [CLK_TOP_AUD_K2_SRC_SEL] = 136, + [CLK_TOP_AUD_K3_SRC_SEL] = 137, + [CLK_TOP_AUD_K4_SRC_SEL] = 138, + [CLK_TOP_AUD_K5_SRC_SEL] = 139, + [CLK_TOP_AUD_K6_SRC_SEL] = 140, + /* Misc CLK only used as parents */ + [CLK_TOP_AUD_EXTCK1_DIV] = 141, + [CLK_TOP_AUD_EXTCK2_DIV] = 142, + [CLK_TOP_AUD_MUX1_DIV] = 143, + [CLK_TOP_AUD_MUX2_DIV] = 144, + [CLK_TOP_AUD_K1_SRC_DIV] = 145, + [CLK_TOP_AUD_K2_SRC_DIV] = 146, + [CLK_TOP_AUD_K3_SRC_DIV] = 147, + [CLK_TOP_AUD_K4_SRC_DIV] = 148, + [CLK_TOP_AUD_K5_SRC_DIV] = 149, + [CLK_TOP_AUD_K6_SRC_DIV] = 150, + [CLK_TOP_AUD_48K_TIMING] = 151, + [CLK_TOP_AUD_44K_TIMING] = 152, + [CLK_TOP_AUD_I2S1_MCLK] = 153, + [CLK_TOP_AUD_I2S2_MCLK] = 154, + [CLK_TOP_AUD_I2S3_MCLK] = 155, + [CLK_TOP_AUD_I2S4_MCLK] = 156, + [CLK_TOP_AUD_I2S5_MCLK] = 157, + [CLK_TOP_AUD_I2S6_MCLK] = 158, +}; + #define FACTOR0(_id, _parent, _mult, _div) \ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) @@ -586,21 +772,26 @@ static const struct mtk_gate_regs infra_cg_regs = { .sta_ofs = 0x48, }; -#define GATE_INFRA(_id, _parent, _shift) { \ +#define GATE_INFRA_FLAGS(_id, _parent, _shift, _flags) { \ .id = _id, \ .parent = _parent, \ .regs = &infra_cg_regs, \ .shift = _shift, \ - .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ + .flags = _flags, \ } +#define GATE_INFRA(_id, _parent, _shift) \ + GATE_INFRA_FLAGS(_id, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) +#define GATE_INFRA_XTAL(_id, _parent, _shift) \ + GATE_INFRA_FLAGS(_id, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_XTAL) + static const struct mtk_gate infra_cgs[] = { GATE_INFRA(CLK_INFRA_DBG, CLK_TOP_AXI_SEL, 0), GATE_INFRA(CLK_INFRA_SMI, CLK_TOP_MM_SEL, 1), GATE_INFRA(CLK_INFRA_QAXI_CM4, CLK_TOP_AXI_SEL, 2), GATE_INFRA(CLK_INFRA_AUD_SPLIN_B, CLK_TOP_HADDS2PLL_294M, 4), - GATE_INFRA(CLK_INFRA_AUDIO, CLK_XTAL, 5), - GATE_INFRA(CLK_INFRA_EFUSE, CLK_XTAL, 6), + GATE_INFRA_XTAL(CLK_INFRA_AUDIO, CLK_XTAL, 5), + GATE_INFRA_XTAL(CLK_INFRA_EFUSE, CLK_XTAL, 6), GATE_INFRA(CLK_INFRA_L2C_SRAM, CLK_TOP_MM_SEL, 7), GATE_INFRA(CLK_INFRA_M4U, CLK_TOP_MEM_SEL, 8), GATE_INFRA(CLK_INFRA_CONNMCU, CLK_TOP_WBG_DIG_416M, 12), @@ -616,6 +807,74 @@ static const struct mtk_gate infra_cgs[] = { }; /* pericfg */ +static const int peri_id_offs_map[] = { + /* MUX CLK */ + [CLK_PERI_UART0_SEL] = 1, + [CLK_PERI_UART1_SEL] = 2, + [CLK_PERI_UART2_SEL] = 3, + [CLK_PERI_UART3_SEL] = 4, + /* GATE CLK */ + [CLK_PERI_NFI] = 5, + [CLK_PERI_THERM] = 6, + [CLK_PERI_PWM1] = 7, + [CLK_PERI_PWM2] = 8, + [CLK_PERI_PWM3] = 9, + [CLK_PERI_PWM4] = 10, + [CLK_PERI_PWM5] = 11, + [CLK_PERI_PWM6] = 12, + [CLK_PERI_PWM7] = 13, + [CLK_PERI_PWM] = 14, + [CLK_PERI_USB0] = 15, + [CLK_PERI_USB1] = 16, + [CLK_PERI_AP_DMA] = 17, + [CLK_PERI_MSDC30_0] = 18, + [CLK_PERI_MSDC30_1] = 19, + [CLK_PERI_MSDC30_2] = 20, + [CLK_PERI_MSDC30_3] = 21, + [CLK_PERI_MSDC50_3] = 22, + [CLK_PERI_NLI] = 23, + [CLK_PERI_UART0] = 24, + [CLK_PERI_UART1] = 25, + [CLK_PERI_UART2] = 26, + [CLK_PERI_UART3] = 27, + [CLK_PERI_BTIF] = 28, + [CLK_PERI_I2C0] = 29, + [CLK_PERI_I2C1] = 30, + [CLK_PERI_I2C2] = 31, + [CLK_PERI_I2C3] = 32, + [CLK_PERI_AUXADC] = 33, + [CLK_PERI_SPI0] = 34, + [CLK_PERI_ETH] = 35, + [CLK_PERI_USB0_MCU] = 36, + [CLK_PERI_USB1_MCU] = 37, + [CLK_PERI_USB_SLV] = 38, + [CLK_PERI_GCPU] = 39, + [CLK_PERI_NFI_ECC] = 40, + [CLK_PERI_NFI_PAD] = 41, + [CLK_PERI_FLASH] = 42, + [CLK_PERI_HOST89_INT] = 43, + [CLK_PERI_HOST89_SPI] = 44, + [CLK_PERI_HOST89_DVD] = 45, + [CLK_PERI_SPI1] = 46, + [CLK_PERI_SPI2] = 47, + [CLK_PERI_FCI] = 48, +}; + +#define TOP_PARENT(_id) PARENT(_id, CLK_PARENT_TOPCKGEN) +#define XTAL_PARENT(_id) PARENT(_id, CLK_PARENT_XTAL) + +static const struct mtk_parent uart_ck_sel_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_UART_SEL), +}; + +static const struct mtk_composite peri_muxes[] = { + MUX_MIXED(CLK_PERI_UART0_SEL, uart_ck_sel_parents, 0x40C, 0, 1), + MUX_MIXED(CLK_PERI_UART1_SEL, uart_ck_sel_parents, 0x40C, 1, 1), + MUX_MIXED(CLK_PERI_UART2_SEL, uart_ck_sel_parents, 0x40C, 2, 1), + MUX_MIXED(CLK_PERI_UART3_SEL, uart_ck_sel_parents, 0x40C, 3, 1), +}; + static const struct mtk_gate_regs peri0_cg_regs = { .set_ofs = 0x8, .clr_ofs = 0x10, @@ -628,13 +887,17 @@ static const struct mtk_gate_regs peri1_cg_regs = { .sta_ofs = 0x1C, }; -#define GATE_PERI0(_id, _parent, _shift) { \ +#define GATE_PERI0_FLAGS(_id, _parent, _shift, _flags) { \ .id = _id, \ .parent = _parent, \ .regs = &peri0_cg_regs, \ .shift = _shift, \ - .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ + .flags = _flags, \ } +#define GATE_PERI0(_id, _parent, _shift) \ + GATE_PERI0_FLAGS(_id, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) +#define GATE_PERI0_XTAL(_id, _parent, _shift) \ + GATE_PERI0_FLAGS(_id, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_XTAL) #define GATE_PERI1(_id, _parent, _shift) { \ .id = _id, \ @@ -672,10 +935,10 @@ static const struct mtk_gate peri_cgs[] = { GATE_PERI0(CLK_PERI_I2C0, CLK_TOP_AXI_SEL, 24), GATE_PERI0(CLK_PERI_I2C1, CLK_TOP_AXI_SEL, 25), GATE_PERI0(CLK_PERI_I2C2, CLK_TOP_AXI_SEL, 26), - GATE_PERI0(CLK_PERI_I2C3, CLK_XTAL, 27), - GATE_PERI0(CLK_PERI_AUXADC, CLK_XTAL, 28), + GATE_PERI0_XTAL(CLK_PERI_I2C3, CLK_XTAL, 27), + GATE_PERI0_XTAL(CLK_PERI_AUXADC, CLK_XTAL, 28), GATE_PERI0(CLK_PERI_SPI0, CLK_TOP_SPI0_SEL, 29), - GATE_PERI0(CLK_PERI_ETH, CLK_XTAL, 30), + GATE_PERI0_XTAL(CLK_PERI_ETH, CLK_XTAL, 30), GATE_PERI0(CLK_PERI_USB0_MCU, CLK_TOP_AXI_SEL, 31), GATE_PERI1(CLK_PERI_USB1_MCU, CLK_TOP_AXI_SEL, 0), @@ -730,12 +993,17 @@ static const struct mtk_gate hif_cgs[] = { GATE_ETH_HIF1(CLK_HIFSYS_PCIE2, CLK_TOP_ETHPLL_500M, 26), }; -static const struct mtk_clk_tree mt7623_clk_tree = { - .xtal_rate = 26 * MHZ, +static const struct mtk_clk_tree mt7623_apmixedsys_clk_tree = { .xtal2_rate = 26 * MHZ, - .fdivs_offs = CLK_TOP_SYSPLL, - .muxes_offs = CLK_TOP_AXI_SEL, + .id_offs_map = pll_id_offs_map, .plls = apmixed_plls, +}; + +static const struct mtk_clk_tree mt7623_topckgen_clk_tree = { + .xtal_rate = 26 * MHZ, + .id_offs_map = top_id_offs_map, + .fdivs_offs = top_id_offs_map[CLK_TOP_SYSPLL], + .muxes_offs = top_id_offs_map[CLK_TOP_AXI_SEL], .fclks = top_fixed_clks, .fdivs = top_fixed_divs, .muxes = top_muxes, @@ -760,7 +1028,7 @@ static int mt7623_apmixedsys_probe(struct udevice *dev) struct mtk_clk_priv *priv = dev_get_priv(dev); int ret; - ret = mtk_common_clk_init(dev, &mt7623_clk_tree); + ret = mtk_common_clk_init(dev, &mt7623_apmixedsys_clk_tree); if (ret) return ret; @@ -774,27 +1042,45 @@ static int mt7623_apmixedsys_probe(struct udevice *dev) static int mt7623_topckgen_probe(struct udevice *dev) { - return mtk_common_clk_init(dev, &mt7623_clk_tree); + return mtk_common_clk_init(dev, &mt7623_topckgen_clk_tree); } +static const struct mtk_clk_tree mt7623_clk_gate_tree = { + /* Each CLK ID for gates clock starts at index 1 */ + .gates_offs = 1, + .xtal_rate = 26 * MHZ, +}; + static int mt7623_infracfg_probe(struct udevice *dev) { - return mtk_common_clk_gate_init(dev, &mt7623_clk_tree, infra_cgs); + return mtk_common_clk_gate_init(dev, &mt7623_clk_gate_tree, + infra_cgs); } +static const struct mtk_clk_tree mt7623_clk_peri_tree = { + .id_offs_map = peri_id_offs_map, + .muxes_offs = peri_id_offs_map[CLK_PERI_UART0_SEL], + .gates_offs = peri_id_offs_map[CLK_PERI_NFI], + .muxes = peri_muxes, + .gates = peri_cgs, + .xtal_rate = 26 * MHZ, +}; + static int mt7623_pericfg_probe(struct udevice *dev) { - return mtk_common_clk_gate_init(dev, &mt7623_clk_tree, peri_cgs); + return mtk_common_clk_infrasys_init(dev, &mt7623_clk_peri_tree); } static int mt7623_hifsys_probe(struct udevice *dev) { - return mtk_common_clk_gate_init(dev, &mt7623_clk_tree, hif_cgs); + return mtk_common_clk_gate_init(dev, &mt7623_clk_gate_tree, + hif_cgs); } static int mt7623_ethsys_probe(struct udevice *dev) { - return mtk_common_clk_gate_init(dev, &mt7623_clk_tree, eth_cgs); + return mtk_common_clk_gate_init(dev, &mt7623_clk_gate_tree, + eth_cgs); } static int mt7623_ethsys_hifsys_bind(struct udevice *dev) @@ -889,7 +1175,7 @@ U_BOOT_DRIVER(mtk_clk_pericfg) = { .of_match = mt7623_pericfg_compat, .probe = mt7623_pericfg_probe, .priv_auto = sizeof(struct mtk_cg_priv), - .ops = &mtk_clk_gate_ops, + .ops = &mtk_clk_infrasys_ops, .flags = DM_FLAG_PRE_RELOC, }; diff --git a/drivers/clk/mediatek/clk-mt7981.c b/drivers/clk/mediatek/clk-mt7981.c index 13dc3df0e9e..97073918006 100644 --- a/drivers/clk/mediatek/clk-mt7981.c +++ b/drivers/clk/mediatek/clk-mt7981.c @@ -29,204 +29,204 @@ /* FIXED PLLS */ static const struct mtk_fixed_clk fixed_pll_clks[] = { - FIXED_CLK(CK_APMIXED_ARMPLL, CLK_XTAL, 1300000000), - FIXED_CLK(CK_APMIXED_NET2PLL, CLK_XTAL, 800000000), - FIXED_CLK(CK_APMIXED_MMPLL, CLK_XTAL, 720000000), - FIXED_CLK(CK_APMIXED_SGMPLL, CLK_XTAL, 325000000), - FIXED_CLK(CK_APMIXED_WEDMCUPLL, CLK_XTAL, 208000000), - FIXED_CLK(CK_APMIXED_NET1PLL, CLK_XTAL, 2500000000), - FIXED_CLK(CK_APMIXED_MPLL, CLK_XTAL, 416000000), - FIXED_CLK(CK_APMIXED_APLL2, CLK_XTAL, 196608000), + FIXED_CLK(CLK_APMIXED_ARMPLL, CLK_XTAL, 1300000000), + FIXED_CLK(CLK_APMIXED_NET2PLL, CLK_XTAL, 800000000), + FIXED_CLK(CLK_APMIXED_MMPLL, CLK_XTAL, 720000000), + FIXED_CLK(CLK_APMIXED_SGMPLL, CLK_XTAL, 325000000), + FIXED_CLK(CLK_APMIXED_WEDMCUPLL, CLK_XTAL, 208000000), + FIXED_CLK(CLK_APMIXED_NET1PLL, CLK_XTAL, 2500000000), + FIXED_CLK(CLK_APMIXED_MPLL, CLK_XTAL, 416000000), + FIXED_CLK(CLK_APMIXED_APLL2, CLK_XTAL, 196608000), }; /* TOPCKGEN FIXED CLK */ static const struct mtk_fixed_clk top_fixed_clks[] = { - FIXED_CLK(CK_TOP_CB_CKSQ_40M, CLK_XTAL, 40000000), + FIXED_CLK(CLK_TOP_CB_CKSQ_40M, CLK_XTAL, 40000000), }; /* TOPCKGEN FIXED DIV */ static const struct mtk_fixed_factor top_fixed_divs[] = { - PLL_FACTOR(CK_TOP_CB_M_416M, "cb_m_416m", CK_APMIXED_MPLL, 1, 1), - PLL_FACTOR(CK_TOP_CB_M_D2, "cb_m_d2", CK_APMIXED_MPLL, 1, 2), - PLL_FACTOR(CK_TOP_CB_M_D3, "cb_m_d3", CK_APMIXED_MPLL, 1, 3), - PLL_FACTOR(CK_TOP_M_D3_D2, "m_d3_d2", CK_APMIXED_MPLL, 1, 2), - PLL_FACTOR(CK_TOP_CB_M_D4, "cb_m_d4", CK_APMIXED_MPLL, 1, 4), - PLL_FACTOR(CK_TOP_CB_M_D8, "cb_m_d8", CK_APMIXED_MPLL, 1, 8), - PLL_FACTOR(CK_TOP_M_D8_D2, "m_d8_d2", CK_APMIXED_MPLL, 1, 16), - PLL_FACTOR(CK_TOP_CB_MM_720M, "cb_mm_720m", CK_APMIXED_MMPLL, 1, 1), - PLL_FACTOR(CK_TOP_CB_MM_D2, "cb_mm_d2", CK_APMIXED_MMPLL, 1, 2), - PLL_FACTOR(CK_TOP_CB_MM_D3, "cb_mm_d3", CK_APMIXED_MMPLL, 1, 3), - PLL_FACTOR(CK_TOP_CB_MM_D3_D5, "cb_mm_d3_d5", CK_APMIXED_MMPLL, 1, 15), - PLL_FACTOR(CK_TOP_CB_MM_D4, "cb_mm_d4", CK_APMIXED_MMPLL, 1, 4), - PLL_FACTOR(CK_TOP_CB_MM_D6, "cb_mm_d6", CK_APMIXED_MMPLL, 1, 6), - PLL_FACTOR(CK_TOP_MM_D6_D2, "mm_d6_d2", CK_APMIXED_MMPLL, 1, 12), - PLL_FACTOR(CK_TOP_CB_MM_D8, "cb_mm_d8", CK_APMIXED_MMPLL, 1, 8), - PLL_FACTOR(CK_TOP_CB_APLL2_196M, "cb_apll2_196m", CK_APMIXED_APLL2, 1, + PLL_FACTOR(CLK_TOP_CB_M_416M, "cb_m_416m", CLK_APMIXED_MPLL, 1, 1), + PLL_FACTOR(CLK_TOP_CB_M_D2, "cb_m_d2", CLK_APMIXED_MPLL, 1, 2), + PLL_FACTOR(CLK_TOP_CB_M_D3, "cb_m_d3", CLK_APMIXED_MPLL, 1, 3), + PLL_FACTOR(CLK_TOP_M_D3_D2, "m_d3_d2", CLK_APMIXED_MPLL, 1, 2), + PLL_FACTOR(CLK_TOP_CB_M_D4, "cb_m_d4", CLK_APMIXED_MPLL, 1, 4), + PLL_FACTOR(CLK_TOP_CB_M_D8, "cb_m_d8", CLK_APMIXED_MPLL, 1, 8), + PLL_FACTOR(CLK_TOP_M_D8_D2, "m_d8_d2", CLK_APMIXED_MPLL, 1, 16), + PLL_FACTOR(CLK_TOP_CB_MM_720M, "cb_mm_720m", CLK_APMIXED_MMPLL, 1, 1), + PLL_FACTOR(CLK_TOP_CB_MM_D2, "cb_mm_d2", CLK_APMIXED_MMPLL, 1, 2), + PLL_FACTOR(CLK_TOP_CB_MM_D3, "cb_mm_d3", CLK_APMIXED_MMPLL, 1, 3), + PLL_FACTOR(CLK_TOP_CB_MM_D3_D5, "cb_mm_d3_d5", CLK_APMIXED_MMPLL, 1, 15), + PLL_FACTOR(CLK_TOP_CB_MM_D4, "cb_mm_d4", CLK_APMIXED_MMPLL, 1, 4), + PLL_FACTOR(CLK_TOP_CB_MM_D6, "cb_mm_d6", CLK_APMIXED_MMPLL, 1, 6), + PLL_FACTOR(CLK_TOP_MM_D6_D2, "mm_d6_d2", CLK_APMIXED_MMPLL, 1, 12), + PLL_FACTOR(CLK_TOP_CB_MM_D8, "cb_mm_d8", CLK_APMIXED_MMPLL, 1, 8), + PLL_FACTOR(CLK_TOP_CB_APLL2_196M, "cb_apll2_196m", CLK_APMIXED_APLL2, 1, 1), - PLL_FACTOR(CK_TOP_APLL2_D2, "apll2_d2", CK_APMIXED_APLL2, 1, 2), - PLL_FACTOR(CK_TOP_APLL2_D4, "apll2_d4", CK_APMIXED_APLL2, 1, 4), - PLL_FACTOR(CK_TOP_NET1_2500M, "net1_2500m", CK_APMIXED_NET1PLL, 1, 1), - PLL_FACTOR(CK_TOP_CB_NET1_D4, "cb_net1_d4", CK_APMIXED_NET1PLL, 1, 4), - PLL_FACTOR(CK_TOP_CB_NET1_D5, "cb_net1_d5", CK_APMIXED_NET1PLL, 1, 5), - PLL_FACTOR(CK_TOP_NET1_D5_D2, "net1_d5_d2", CK_APMIXED_NET1PLL, 1, 10), - PLL_FACTOR(CK_TOP_NET1_D5_D4, "net1_d5_d4", CK_APMIXED_NET1PLL, 1, 20), - PLL_FACTOR(CK_TOP_CB_NET1_D8, "cb_net1_d8", CK_APMIXED_NET1PLL, 1, 8), - PLL_FACTOR(CK_TOP_NET1_D8_D2, "net1_d8_d2", CK_APMIXED_NET1PLL, 1, 16), - PLL_FACTOR(CK_TOP_NET1_D8_D4, "net1_d8_d4", CK_APMIXED_NET1PLL, 1, 32), - PLL_FACTOR(CK_TOP_CB_NET2_800M, "cb_net2_800m", CK_APMIXED_NET2PLL, 1, + PLL_FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", CLK_APMIXED_APLL2, 1, 2), + PLL_FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", CLK_APMIXED_APLL2, 1, 4), + PLL_FACTOR(CLK_TOP_NET1_2500M, "net1_2500m", CLK_APMIXED_NET1PLL, 1, 1), + PLL_FACTOR(CLK_TOP_CB_NET1_D4, "cb_net1_d4", CLK_APMIXED_NET1PLL, 1, 4), + PLL_FACTOR(CLK_TOP_CB_NET1_D5, "cb_net1_d5", CLK_APMIXED_NET1PLL, 1, 5), + PLL_FACTOR(CLK_TOP_NET1_D5_D2, "net1_d5_d2", CLK_APMIXED_NET1PLL, 1, 10), + PLL_FACTOR(CLK_TOP_NET1_D5_D4, "net1_d5_d4", CLK_APMIXED_NET1PLL, 1, 20), + PLL_FACTOR(CLK_TOP_CB_NET1_D8, "cb_net1_d8", CLK_APMIXED_NET1PLL, 1, 8), + PLL_FACTOR(CLK_TOP_NET1_D8_D2, "net1_d8_d2", CLK_APMIXED_NET1PLL, 1, 16), + PLL_FACTOR(CLK_TOP_NET1_D8_D4, "net1_d8_d4", CLK_APMIXED_NET1PLL, 1, 32), + PLL_FACTOR(CLK_TOP_CB_NET2_800M, "cb_net2_800m", CLK_APMIXED_NET2PLL, 1, 1), - PLL_FACTOR(CK_TOP_CB_NET2_D2, "cb_net2_d2", CK_APMIXED_NET2PLL, 1, 2), - PLL_FACTOR(CK_TOP_CB_NET2_D4, "cb_net2_d4", CK_APMIXED_NET2PLL, 1, 4), - PLL_FACTOR(CK_TOP_NET2_D4_D2, "net2_d4_d2", CK_APMIXED_NET2PLL, 1, 8), - PLL_FACTOR(CK_TOP_NET2_D4_D4, "net2_d4_d4", CK_APMIXED_NET2PLL, 1, 16), - PLL_FACTOR(CK_TOP_CB_NET2_D6, "cb_net2_d6", CK_APMIXED_NET2PLL, 1, 6), - PLL_FACTOR(CK_TOP_CB_WEDMCU_208M, "cb_wedmcu_208m", - CK_APMIXED_WEDMCUPLL, 1, 1), - PLL_FACTOR(CK_TOP_CB_SGM_325M, "cb_sgm_325m", CK_APMIXED_SGMPLL, 1, 1), - TOP_FACTOR(CK_TOP_CKSQ_40M_D2, "cksq_40m_d2", CK_TOP_CB_CKSQ_40M, 1, 2), - TOP_FACTOR(CK_TOP_CB_RTC_32K, "cb_rtc_32k", CK_TOP_CB_CKSQ_40M, 1, + PLL_FACTOR(CLK_TOP_CB_NET2_D2, "cb_net2_d2", CLK_APMIXED_NET2PLL, 1, 2), + PLL_FACTOR(CLK_TOP_CB_NET2_D4, "cb_net2_d4", CLK_APMIXED_NET2PLL, 1, 4), + PLL_FACTOR(CLK_TOP_NET2_D4_D2, "net2_d4_d2", CLK_APMIXED_NET2PLL, 1, 8), + PLL_FACTOR(CLK_TOP_NET2_D4_D4, "net2_d4_d4", CLK_APMIXED_NET2PLL, 1, 16), + PLL_FACTOR(CLK_TOP_CB_NET2_D6, "cb_net2_d6", CLK_APMIXED_NET2PLL, 1, 6), + PLL_FACTOR(CLK_TOP_CB_WEDMCU_208M, "cb_wedmcu_208m", + CLK_APMIXED_WEDMCUPLL, 1, 1), + PLL_FACTOR(CLK_TOP_CB_SGM_325M, "cb_sgm_325m", CLK_APMIXED_SGMPLL, 1, 1), + TOP_FACTOR(CLK_TOP_CKSQ_40M_D2, "cksq_40m_d2", CLK_TOP_CB_CKSQ_40M, 1, 2), + TOP_FACTOR(CLK_TOP_CB_RTC_32K, "cb_rtc_32k", CLK_TOP_CB_CKSQ_40M, 1, 1250), - TOP_FACTOR(CK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", CK_TOP_CB_CKSQ_40M, 1, + TOP_FACTOR(CLK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", CLK_TOP_CB_CKSQ_40M, 1, 1220), - TOP_FACTOR(CK_TOP_USB_TX250M, "usb_tx250m", CK_TOP_CB_CKSQ_40M, 1, 1), - TOP_FACTOR(CK_TOP_FAUD, "faud", CK_TOP_CB_CKSQ_40M, 1, 1), - TOP_FACTOR(CK_TOP_NFI1X, "nfi1x", CK_TOP_NFI1X_SEL, 1, 1), - TOP_FACTOR(CK_TOP_USB_EQ_RX250M, "usb_eq_rx250m", CK_TOP_CB_CKSQ_40M, 1, + TOP_FACTOR(CLK_TOP_USB_TX250M, "usb_tx250m", CLK_TOP_CB_CKSQ_40M, 1, 1), + TOP_FACTOR(CLK_TOP_FAUD, "faud", CLK_TOP_AUD_SEL, 1, 1), + TOP_FACTOR(CLK_TOP_NFI1X, "nfi1x", CLK_TOP_NFI1X_SEL, 1, 1), + TOP_FACTOR(CLK_TOP_USB_EQ_RX250M, "usb_eq_rx250m", CLK_TOP_CB_CKSQ_40M, 1, 1), - TOP_FACTOR(CK_TOP_USB_CDR_CK, "usb_cdr", CK_TOP_CB_CKSQ_40M, 1, 1), - TOP_FACTOR(CK_TOP_USB_LN0_CK, "usb_ln0", CK_TOP_CB_CKSQ_40M, 1, 1), - TOP_FACTOR(CK_TOP_SPINFI_BCK, "spinfi_bck", CK_TOP_SPINFI_SEL, 1, 1), - TOP_FACTOR(CK_TOP_SPI, "spi", CK_TOP_SPI_SEL, 1, 1), - TOP_FACTOR(CK_TOP_SPIM_MST, "spim_mst", CK_TOP_SPIM_MST_SEL, 1, 1), - TOP_FACTOR(CK_TOP_UART_BCK, "uart_bck", CK_TOP_UART_SEL, 1, 1), - TOP_FACTOR(CK_TOP_PWM_BCK, "pwm_bck", CK_TOP_PWM_SEL, 1, 1), - TOP_FACTOR(CK_TOP_I2C_BCK, "i2c_bck", CK_TOP_I2C_SEL, 1, 1), - TOP_FACTOR(CK_TOP_PEXTP_TL, "pextp_tl", CK_TOP_PEXTP_TL_SEL, 1, 1), - TOP_FACTOR(CK_TOP_EMMC_208M, "emmc_208m", CK_TOP_EMMC_208M_SEL, 1, 1), - TOP_FACTOR(CK_TOP_EMMC_400M, "emmc_400m", CK_TOP_EMMC_400M_SEL, 1, 1), - TOP_FACTOR(CK_TOP_DRAMC_REF, "dramc_ref", CK_TOP_DRAMC_SEL, 1, 1), - TOP_FACTOR(CK_TOP_DRAMC_MD32, "dramc_md32", CK_TOP_DRAMC_MD32_SEL, 1, + TOP_FACTOR(CLK_TOP_USB_CDR_CK, "usb_cdr", CLK_TOP_CB_CKSQ_40M, 1, 1), + TOP_FACTOR(CLK_TOP_USB_LN0_CK, "usb_ln0", CLK_TOP_CB_CKSQ_40M, 1, 1), + TOP_FACTOR(CLK_TOP_SPINFI_BCK, "spinfi_bck", CLK_TOP_SPINFI_SEL, 1, 1), + TOP_FACTOR(CLK_TOP_SPI, "spi", CLK_TOP_SPI_SEL, 1, 1), + TOP_FACTOR(CLK_TOP_SPIM_MST, "spim_mst", CLK_TOP_SPIM_MST_SEL, 1, 1), + TOP_FACTOR(CLK_TOP_UART_BCK, "uart_bck", CLK_TOP_UART_SEL, 1, 1), + TOP_FACTOR(CLK_TOP_PWM_BCK, "pwm_bck", CLK_TOP_PWM_SEL, 1, 1), + TOP_FACTOR(CLK_TOP_I2C_BCK, "i2c_bck", CLK_TOP_I2C_SEL, 1, 1), + TOP_FACTOR(CLK_TOP_PEXTP_TL, "pextp_tl", CLK_TOP_PEXTP_TL_SEL, 1, 1), + TOP_FACTOR(CLK_TOP_EMMC_208M, "emmc_208m", CLK_TOP_EMMC_208M_SEL, 1, 1), + TOP_FACTOR(CLK_TOP_EMMC_400M, "emmc_400m", CLK_TOP_EMMC_400M_SEL, 1, 1), + TOP_FACTOR(CLK_TOP_DRAMC_REF, "dramc_ref", CLK_TOP_DRAMC_SEL, 1, 1), + TOP_FACTOR(CLK_TOP_DRAMC_MD32, "dramc_md32", CLK_TOP_DRAMC_MD32_SEL, 1, 1), - TOP_FACTOR(CK_TOP_SYSAXI, "sysaxi", CK_TOP_SYSAXI_SEL, 1, 1), - TOP_FACTOR(CK_TOP_SYSAPB, "sysapb", CK_TOP_SYSAPB_SEL, 1, 1), - TOP_FACTOR(CK_TOP_ARM_DB_MAIN, "arm_db_main", CK_TOP_ARM_DB_MAIN_SEL, 1, + TOP_FACTOR(CLK_TOP_SYSAXI, "sysaxi", CLK_TOP_SYSAXI_SEL, 1, 1), + TOP_FACTOR(CLK_TOP_SYSAPB, "sysapb", CLK_TOP_SYSAPB_SEL, 1, 1), + TOP_FACTOR(CLK_TOP_ARM_DB_MAIN, "arm_db_main", CLK_TOP_ARM_DB_MAIN_SEL, 1, 1), - TOP_FACTOR(CK_TOP_AP2CNN_HOST, "ap2cnn_host", CK_TOP_AP2CNN_HOST_SEL, 1, + TOP_FACTOR(CLK_TOP_AP2CNN_HOST, "ap2cnn_host", CLK_TOP_AP2CNN_HOST_SEL, 1, 1), - TOP_FACTOR(CK_TOP_NETSYS, "netsys", CK_TOP_NETSYS_SEL, 1, 1), - TOP_FACTOR(CK_TOP_NETSYS_500M, "netsys_500m", CK_TOP_NETSYS_500M_SEL, 1, + TOP_FACTOR(CLK_TOP_NETSYS, "netsys", CLK_TOP_NETSYS_SEL, 1, 1), + TOP_FACTOR(CLK_TOP_NETSYS_500M, "netsys_500m", CLK_TOP_NETSYS_500M_SEL, 1, 1), - TOP_FACTOR(CK_TOP_NETSYS_WED_MCU, "netsys_wed_mcu", - CK_TOP_NETSYS_MCU_SEL, 1, 1), - TOP_FACTOR(CK_TOP_NETSYS_2X, "netsys_2x", CK_TOP_NETSYS_2X_SEL, 1, 1), - TOP_FACTOR(CK_TOP_SGM_325M, "sgm_325m", CK_TOP_SGM_325M_SEL, 1, 1), - TOP_FACTOR(CK_TOP_SGM_REG, "sgm_reg", CK_TOP_SGM_REG_SEL, 1, 1), - TOP_FACTOR(CK_TOP_F26M, "csw_f26m", CK_TOP_F26M_SEL, 1, 1), - TOP_FACTOR(CK_TOP_EIP97B, "eip97b", CK_TOP_EIP97B_SEL, 1, 1), - TOP_FACTOR(CK_TOP_USB3_PHY, "usb3_phy", CK_TOP_USB3_PHY_SEL, 1, 1), - TOP_FACTOR(CK_TOP_AUD, "aud", CK_TOP_FAUD, 1, 1), - TOP_FACTOR(CK_TOP_A1SYS, "a1sys", CK_TOP_A1SYS_SEL, 1, 1), - TOP_FACTOR(CK_TOP_AUD_L, "aud_l", CK_TOP_AUD_L_SEL, 1, 1), - TOP_FACTOR(CK_TOP_A_TUNER, "a_tuner", CK_TOP_A_TUNER_SEL, 1, 1), - TOP_FACTOR(CK_TOP_U2U3_REF, "u2u3_ref", CK_TOP_U2U3_SEL, 1, 1), - TOP_FACTOR(CK_TOP_U2U3_SYS, "u2u3_sys", CK_TOP_U2U3_SYS_SEL, 1, 1), - TOP_FACTOR(CK_TOP_U2U3_XHCI, "u2u3_xhci", CK_TOP_U2U3_XHCI_SEL, 1, 1), - TOP_FACTOR(CK_TOP_USB_FRMCNT, "usb_frmcnt", CK_TOP_USB_FRMCNT_SEL, 1, + TOP_FACTOR(CLK_TOP_NETSYS_WED_MCU, "netsys_wed_mcu", + CLK_TOP_NETSYS_MCU_SEL, 1, 1), + TOP_FACTOR(CLK_TOP_NETSYS_2X, "netsys_2x", CLK_TOP_NETSYS_2X_SEL, 1, 1), + TOP_FACTOR(CLK_TOP_SGM_325M, "sgm_325m", CLK_TOP_SGM_325M_SEL, 1, 1), + TOP_FACTOR(CLK_TOP_SGM_REG, "sgm_reg", CLK_TOP_SGM_REG_SEL, 1, 1), + TOP_FACTOR(CLK_TOP_F26M, "csw_f26m", CLK_TOP_F26M_SEL, 1, 1), + TOP_FACTOR(CLK_TOP_EIP97B, "eip97b", CLK_TOP_EIP97B_SEL, 1, 1), + TOP_FACTOR(CLK_TOP_USB3_PHY, "usb3_phy", CLK_TOP_USB3_PHY_SEL, 1, 1), + TOP_FACTOR(CLK_TOP_AUD, "aud", CLK_TOP_FAUD, 1, 1), + TOP_FACTOR(CLK_TOP_A1SYS, "a1sys", CLK_TOP_A1SYS_SEL, 1, 1), + TOP_FACTOR(CLK_TOP_AUD_L, "aud_l", CLK_TOP_AUD_L_SEL, 1, 1), + TOP_FACTOR(CLK_TOP_A_TUNER, "a_tuner", CLK_TOP_A_TUNER_SEL, 1, 1), + TOP_FACTOR(CLK_TOP_U2U3_REF, "u2u3_ref", CLK_TOP_U2U3_SEL, 1, 1), + TOP_FACTOR(CLK_TOP_U2U3_SYS, "u2u3_sys", CLK_TOP_U2U3_SYS_SEL, 1, 1), + TOP_FACTOR(CLK_TOP_U2U3_XHCI, "u2u3_xhci", CLK_TOP_U2U3_XHCI_SEL, 1, 1), + TOP_FACTOR(CLK_TOP_USB_FRMCNT, "usb_frmcnt", CLK_TOP_USB_FRMCNT_SEL, 1, 1), }; /* TOPCKGEN MUX PARENTS */ -static const int nfi1x_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MM_D4, - CK_TOP_NET1_D8_D2, CK_TOP_CB_NET2_D6, - CK_TOP_CB_M_D4, CK_TOP_CB_MM_D8, - CK_TOP_NET1_D8_D4, CK_TOP_CB_M_D8 }; +static const int nfi1x_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_MM_D4, + CLK_TOP_NET1_D8_D2, CLK_TOP_CB_NET2_D6, + CLK_TOP_CB_M_D4, CLK_TOP_CB_MM_D8, + CLK_TOP_NET1_D8_D4, CLK_TOP_CB_M_D8 }; -static const int spinfi_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_CB_CKSQ_40M, - CK_TOP_NET1_D5_D4, CK_TOP_CB_M_D4, - CK_TOP_CB_MM_D8, CK_TOP_NET1_D8_D4, - CK_TOP_MM_D6_D2, CK_TOP_CB_M_D8 }; +static const int spinfi_parents[] = { CLK_TOP_CKSQ_40M_D2, CLK_TOP_CB_CKSQ_40M, + CLK_TOP_NET1_D5_D4, CLK_TOP_CB_M_D4, + CLK_TOP_CB_MM_D8, CLK_TOP_NET1_D8_D4, + CLK_TOP_MM_D6_D2, CLK_TOP_CB_M_D8 }; -static const int spi_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2, - CK_TOP_CB_MM_D4, CK_TOP_NET1_D8_D2, - CK_TOP_CB_NET2_D6, CK_TOP_NET1_D5_D4, - CK_TOP_CB_M_D4, CK_TOP_NET1_D8_D4 }; +static const int spi_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_M_D2, + CLK_TOP_CB_MM_D4, CLK_TOP_NET1_D8_D2, + CLK_TOP_CB_NET2_D6, CLK_TOP_NET1_D5_D4, + CLK_TOP_CB_M_D4, CLK_TOP_NET1_D8_D4 }; -static const int uart_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D8, - CK_TOP_M_D8_D2 }; +static const int uart_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_M_D8, + CLK_TOP_M_D8_D2 }; -static const int pwm_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D8_D2, - CK_TOP_NET1_D5_D4, CK_TOP_CB_M_D4, - CK_TOP_M_D8_D2, CK_TOP_CB_RTC_32K }; +static const int pwm_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_NET1_D8_D2, + CLK_TOP_NET1_D5_D4, CLK_TOP_CB_M_D4, + CLK_TOP_M_D8_D2, CLK_TOP_CB_RTC_32K }; -static const int i2c_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4, - CK_TOP_CB_M_D4, CK_TOP_NET1_D8_D4 }; +static const int i2c_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_NET1_D5_D4, + CLK_TOP_CB_M_D4, CLK_TOP_NET1_D8_D4 }; -static const int pextp_tl_ck_parents[] = { CK_TOP_CB_CKSQ_40M, - CK_TOP_NET1_D5_D4, CK_TOP_CB_M_D4, - CK_TOP_CB_RTC_32K }; +static const int pextp_tl_ck_parents[] = { CLK_TOP_CB_CKSQ_40M, + CLK_TOP_NET1_D5_D4, CLK_TOP_CB_M_D4, + CLK_TOP_CB_RTC_32K }; static const int emmc_208m_parents[] = { - CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2, CK_TOP_CB_NET2_D4, - CK_TOP_CB_APLL2_196M, CK_TOP_CB_MM_D4, CK_TOP_NET1_D8_D2, - CK_TOP_CB_MM_D6 + CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_M_D2, CLK_TOP_CB_NET2_D4, + CLK_TOP_CB_APLL2_196M, CLK_TOP_CB_MM_D4, CLK_TOP_NET1_D8_D2, + CLK_TOP_CB_MM_D6 }; -static const int emmc_400m_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET2_D2, - CK_TOP_CB_MM_D2, CK_TOP_CB_NET2_D2 }; +static const int emmc_400m_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_NET2_D2, + CLK_TOP_CB_MM_D2, CLK_TOP_CB_NET2_D2 }; -static const int csw_f26m_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_M_D8_D2 }; +static const int csw_f26m_parents[] = { CLK_TOP_CKSQ_40M_D2, CLK_TOP_M_D8_D2 }; -static const int dramc_md32_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2, - CK_TOP_CB_WEDMCU_208M }; +static const int dramc_md32_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_M_D2, + CLK_TOP_CB_WEDMCU_208M }; -static const int sysaxi_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D8_D2 }; +static const int sysaxi_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_NET1_D8_D2 }; -static const int sysapb_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_M_D3_D2 }; +static const int sysapb_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_M_D3_D2 }; -static const int arm_db_main_parents[] = { CK_TOP_CB_CKSQ_40M, - CK_TOP_CB_NET2_D6 }; +static const int arm_db_main_parents[] = { CLK_TOP_CB_CKSQ_40M, + CLK_TOP_CB_NET2_D6 }; -static const int ap2cnn_host_parents[] = { CK_TOP_CB_CKSQ_40M, - CK_TOP_NET1_D8_D4 }; +static const int ap2cnn_host_parents[] = { CLK_TOP_CB_CKSQ_40M, + CLK_TOP_NET1_D8_D4 }; -static const int netsys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MM_D2 }; +static const int netsys_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_MM_D2 }; -static const int netsys_500m_parents[] = { CK_TOP_CB_CKSQ_40M, - CK_TOP_CB_NET1_D5 }; +static const int netsys_500m_parents[] = { CLK_TOP_CB_CKSQ_40M, + CLK_TOP_CB_NET1_D5 }; -static const int netsys_mcu_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MM_720M, - CK_TOP_CB_NET1_D4, CK_TOP_CB_NET1_D5, - CK_TOP_CB_M_416M }; +static const int netsys_mcu_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_MM_720M, + CLK_TOP_CB_NET1_D4, CLK_TOP_CB_NET1_D5, + CLK_TOP_CB_M_416M }; -static const int netsys_2x_parents[] = { CK_TOP_CB_CKSQ_40M, - CK_TOP_CB_NET2_800M, - CK_TOP_CB_MM_720M }; +static const int netsys_2x_parents[] = { CLK_TOP_CB_CKSQ_40M, + CLK_TOP_CB_NET2_800M, + CLK_TOP_CB_MM_720M }; -static const int sgm_325m_parents[] = { CK_TOP_CB_CKSQ_40M, - CK_TOP_CB_SGM_325M }; +static const int sgm_325m_parents[] = { CLK_TOP_CB_CKSQ_40M, + CLK_TOP_CB_SGM_325M }; -static const int sgm_reg_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET2_D4 }; +static const int sgm_reg_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_NET2_D4 }; -static const int eip97b_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET1_D5, - CK_TOP_CB_M_416M, CK_TOP_CB_MM_D2, - CK_TOP_NET1_D5_D2 }; +static const int eip97b_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_NET1_D5, + CLK_TOP_CB_M_416M, CLK_TOP_CB_MM_D2, + CLK_TOP_NET1_D5_D2 }; -static const int aud_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_APLL2_196M }; +static const int aud_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_APLL2_196M }; -static const int a1sys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_APLL2_D4 }; +static const int a1sys_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_APLL2_D4 }; -static const int aud_l_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_APLL2_196M, - CK_TOP_M_D8_D2 }; +static const int aud_l_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_APLL2_196M, + CLK_TOP_M_D8_D2 }; -static const int a_tuner_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_APLL2_D4, - CK_TOP_M_D8_D2 }; +static const int a_tuner_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_APLL2_D4, + CLK_TOP_M_D8_D2 }; -static const int u2u3_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_M_D8_D2 }; +static const int u2u3_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_M_D8_D2 }; -static const int u2u3_sys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4 }; +static const int u2u3_sys_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_NET1_D5_D4 }; -static const int usb_frmcnt_parents[] = { CK_TOP_CB_CKSQ_40M, - CK_TOP_CB_MM_D3_D5 }; +static const int usb_frmcnt_parents[] = { CLK_TOP_CB_CKSQ_40M, + CLK_TOP_CB_MM_D3_D5 }; #define TOP_MUX(_id, _name, _parents, _mux_ofs, _mux_set_ofs, _mux_clr_ofs, \ _shift, _width, _gate, _upd_ofs, _upd) \ @@ -242,174 +242,150 @@ static const int usb_frmcnt_parents[] = { CK_TOP_CB_CKSQ_40M, /* TOPCKGEN MUX_GATE */ static const struct mtk_composite top_muxes[] = { - TOP_MUX(CK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, 0x0, 0x4, 0x8, 0, + TOP_MUX(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, 0x0, 0x4, 0x8, 0, 3, 7, 0x1c0, 0), - TOP_MUX(CK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, 0x0, 0x4, 0x8, + TOP_MUX(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, 0x0, 0x4, 0x8, 8, 3, 15, 0x1c0, 1), - TOP_MUX(CK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x0, 0x4, 0x8, 16, 3, + TOP_MUX(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x0, 0x4, 0x8, 16, 3, 23, 0x1c0, 2), - TOP_MUX(CK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, 0x0, 0x4, 0x8, + TOP_MUX(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, 0x0, 0x4, 0x8, 24, 3, 31, 0x1c0, 3), - TOP_MUX(CK_TOP_UART_SEL, "uart_sel", uart_parents, 0x10, 0x14, 0x18, 0, + TOP_MUX(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x10, 0x14, 0x18, 0, 2, 7, 0x1c0, 4), - TOP_MUX(CK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x10, 0x14, 0x18, 8, 3, + TOP_MUX(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x10, 0x14, 0x18, 8, 3, 15, 0x1c0, 5), - TOP_MUX(CK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x10, 0x14, 0x18, 16, 2, + TOP_MUX(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x10, 0x14, 0x18, 16, 2, 23, 0x1c0, 6), - TOP_MUX(CK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", pextp_tl_ck_parents, + TOP_MUX(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", pextp_tl_ck_parents, 0x10, 0x14, 0x18, 24, 2, 31, 0x1c0, 7), - TOP_MUX(CK_TOP_EMMC_208M_SEL, "emmc_208m_sel", emmc_208m_parents, 0x20, + TOP_MUX(CLK_TOP_EMMC_208M_SEL, "emmc_208m_sel", emmc_208m_parents, 0x20, 0x24, 0x28, 0, 3, 7, 0x1c0, 8), - TOP_MUX(CK_TOP_EMMC_400M_SEL, "emmc_400m_sel", emmc_400m_parents, 0x20, + TOP_MUX(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel", emmc_400m_parents, 0x20, 0x24, 0x28, 8, 2, 15, 0x1c0, 9), - TOP_MUX(CK_TOP_F26M_SEL, "csw_f26m_sel", csw_f26m_parents, 0x20, 0x24, + TOP_MUX(CLK_TOP_F26M_SEL, "csw_f26m_sel", csw_f26m_parents, 0x20, 0x24, 0x28, 16, 1, 23, 0x1c0, 10), - TOP_MUX(CK_TOP_DRAMC_SEL, "dramc_sel", csw_f26m_parents, 0x20, 0x24, + TOP_MUX(CLK_TOP_DRAMC_SEL, "dramc_sel", csw_f26m_parents, 0x20, 0x24, 0x28, 24, 1, 31, 0x1c0, 11), - TOP_MUX(CK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", dramc_md32_parents, + TOP_MUX(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", dramc_md32_parents, 0x30, 0x34, 0x38, 0, 2, 7, 0x1c0, 12), - TOP_MUX(CK_TOP_SYSAXI_SEL, "sysaxi_sel", sysaxi_parents, 0x30, 0x34, + TOP_MUX(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", sysaxi_parents, 0x30, 0x34, 0x38, 8, 1, 15, 0x1c0, 13), - TOP_MUX(CK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, 0x30, 0x34, + TOP_MUX(CLK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, 0x30, 0x34, 0x38, 16, 1, 23, 0x1c0, 14), - TOP_MUX(CK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel", arm_db_main_parents, + TOP_MUX(CLK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel", arm_db_main_parents, 0x30, 0x34, 0x38, 24, 1, 31, 0x1c0, 15), - TOP_MUX(CK_TOP_AP2CNN_HOST_SEL, "ap2cnn_host_sel", ap2cnn_host_parents, + TOP_MUX(CLK_TOP_AP2CNN_HOST_SEL, "ap2cnn_host_sel", ap2cnn_host_parents, 0x40, 0x44, 0x48, 0, 1, 7, 0x1c0, 16), - TOP_MUX(CK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 0x40, 0x44, + TOP_MUX(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 0x40, 0x44, 0x48, 8, 1, 15, 0x1c0, 17), - TOP_MUX(CK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", netsys_500m_parents, + TOP_MUX(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", netsys_500m_parents, 0x40, 0x44, 0x48, 16, 1, 23, 0x1c0, 18), - TOP_MUX(CK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", netsys_mcu_parents, + TOP_MUX(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", netsys_mcu_parents, 0x40, 0x44, 0x48, 24, 3, 31, 0x1c0, 19), - TOP_MUX(CK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, 0x50, + TOP_MUX(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, 0x50, 0x54, 0x58, 0, 2, 7, 0x1c0, 20), - TOP_MUX(CK_TOP_SGM_325M_SEL, "sgm_325m_sel", sgm_325m_parents, 0x50, + TOP_MUX(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel", sgm_325m_parents, 0x50, 0x54, 0x58, 8, 1, 15, 0x1c0, 21), - TOP_MUX(CK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents, 0x50, 0x54, + TOP_MUX(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents, 0x50, 0x54, 0x58, 16, 1, 23, 0x1c0, 22), - TOP_MUX(CK_TOP_EIP97B_SEL, "eip97b_sel", eip97b_parents, 0x50, 0x54, + TOP_MUX(CLK_TOP_EIP97B_SEL, "eip97b_sel", eip97b_parents, 0x50, 0x54, 0x58, 24, 3, 31, 0x1c0, 23), - TOP_MUX(CK_TOP_USB3_PHY_SEL, "usb3_phy_sel", csw_f26m_parents, 0x60, + TOP_MUX(CLK_TOP_USB3_PHY_SEL, "usb3_phy_sel", csw_f26m_parents, 0x60, 0x64, 0x68, 0, 1, 7, 0x1c0, 24), - TOP_MUX(CK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x60, 0x64, 0x68, 8, 1, + TOP_MUX(CLK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x60, 0x64, 0x68, 8, 1, 15, 0x1c0, 25), - TOP_MUX(CK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 0x60, 0x64, 0x68, + TOP_MUX(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 0x60, 0x64, 0x68, 16, 1, 23, 0x1c0, 26), - TOP_MUX(CK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 0x60, 0x64, 0x68, + TOP_MUX(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 0x60, 0x64, 0x68, 24, 2, 31, 0x1c0, 27), - TOP_MUX(CK_TOP_A_TUNER_SEL, "a_tuner_sel", a_tuner_parents, 0x70, 0x74, + TOP_MUX(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", a_tuner_parents, 0x70, 0x74, 0x78, 0, 2, 7, 0x1c0, 28), - TOP_MUX(CK_TOP_U2U3_SEL, "u2u3_sel", u2u3_parents, 0x70, 0x74, 0x78, 8, + TOP_MUX(CLK_TOP_U2U3_SEL, "u2u3_sel", u2u3_parents, 0x70, 0x74, 0x78, 8, 1, 15, 0x1c0, 29), - TOP_MUX(CK_TOP_U2U3_SYS_SEL, "u2u3_sys_sel", u2u3_sys_parents, 0x70, + TOP_MUX(CLK_TOP_U2U3_SYS_SEL, "u2u3_sys_sel", u2u3_sys_parents, 0x70, 0x74, 0x78, 16, 1, 23, 0x1c0, 30), - TOP_MUX(CK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel", u2u3_sys_parents, 0x70, + TOP_MUX(CLK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel", u2u3_sys_parents, 0x70, 0x74, 0x78, 24, 1, 31, 0x1c4, 0), - TOP_MUX(CK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel", usb_frmcnt_parents, + TOP_MUX(CLK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel", usb_frmcnt_parents, 0x80, 0x84, 0x88, 0, 1, 7, 0x1c4, 1), }; /* INFRA FIXED DIV */ static const struct mtk_fixed_factor infra_fixed_divs[] = { - TOP_FACTOR(CK_INFRA_CK_F26M, "infra_ck_f26m", CK_TOP_F26M_SEL, 1, 1), - TOP_FACTOR(CK_INFRA_UART, "infra_uart", CK_TOP_UART_SEL, 1, 1), - TOP_FACTOR(CK_INFRA_ISPI0, "infra_ispi0", CK_TOP_SPI_SEL, 1, 1), - TOP_FACTOR(CK_INFRA_I2C, "infra_i2c", CK_TOP_I2C_SEL, 1, 1), - TOP_FACTOR(CK_INFRA_ISPI1, "infra_ispi1", CK_TOP_SPIM_MST_SEL, 1, 1), - TOP_FACTOR(CK_INFRA_PWM, "infra_pwm", CK_TOP_PWM_SEL, 1, 1), - TOP_FACTOR(CK_INFRA_66M_MCK, "infra_66m_mck", CK_TOP_SYSAXI_SEL, 1, 2), - TOP_FACTOR(CK_INFRA_CK_F32K, "infra_ck_f32k", CK_TOP_CB_RTC_32P7K, 1, - 1), - TOP_FACTOR(CK_INFRA_PCIE_CK, "infra_pcie", CK_TOP_PEXTP_TL_SEL, 1, 1), - INFRA_FACTOR(CK_INFRA_PWM_BCK, "infra_pwm_bck", CK_INFRA_PWM_BSEL, 1, - 1), - INFRA_FACTOR(CK_INFRA_PWM_CK1, "infra_pwm_ck1", CK_INFRA_PWM1_SEL, 1, - 1), - INFRA_FACTOR(CK_INFRA_PWM_CK2, "infra_pwm_ck2", CK_INFRA_PWM2_SEL, 1, - 1), - TOP_FACTOR(CK_INFRA_133M_HCK, "infra_133m_hck", CK_TOP_SYSAXI, 1, 1), - INFRA_FACTOR(CK_INFRA_66M_PHCK, "infra_66m_phck", CK_INFRA_133M_HCK, 1, - 1), - TOP_FACTOR(CK_INFRA_FAUD_L_CK, "infra_faud_l", CK_TOP_AUD_L, 1, 1), - TOP_FACTOR(CK_INFRA_FAUD_AUD_CK, "infra_faud_aud", CK_TOP_A1SYS, 1, 1), - TOP_FACTOR(CK_INFRA_FAUD_EG2_CK, "infra_faud_eg2", CK_TOP_A_TUNER, 1, - 1), - TOP_FACTOR(CK_INFRA_I2CS_CK, "infra_i2cs", CK_TOP_I2C_BCK, 1, 1), - INFRA_FACTOR(CK_INFRA_MUX_UART0, "infra_mux_uart0", CK_INFRA_UART0_SEL, - 1, 1), - INFRA_FACTOR(CK_INFRA_MUX_UART1, "infra_mux_uart1", CK_INFRA_UART1_SEL, - 1, 1), - INFRA_FACTOR(CK_INFRA_MUX_UART2, "infra_mux_uart2", CK_INFRA_UART2_SEL, - 1, 1), - TOP_FACTOR(CK_INFRA_NFI_CK, "infra_nfi", CK_TOP_NFI1X, 1, 1), - TOP_FACTOR(CK_INFRA_SPINFI_CK, "infra_spinfi", CK_TOP_SPINFI_BCK, 1, 1), - INFRA_FACTOR(CK_INFRA_MUX_SPI0, "infra_mux_spi0", CK_INFRA_SPI0_SEL, 1, - 1), - INFRA_FACTOR(CK_INFRA_MUX_SPI1, "infra_mux_spi1", CK_INFRA_SPI1_SEL, 1, - 1), - INFRA_FACTOR(CK_INFRA_MUX_SPI2, "infra_mux_spi2", CK_INFRA_SPI2_SEL, 1, - 1), - TOP_FACTOR(CK_INFRA_RTC_32K, "infra_rtc_32k", CK_TOP_CB_RTC_32K, 1, 1), - TOP_FACTOR(CK_INFRA_FMSDC_CK, "infra_fmsdc", CK_TOP_EMMC_400M, 1, 1), - TOP_FACTOR(CK_INFRA_FMSDC_HCK_CK, "infra_fmsdc_hck", CK_TOP_EMMC_208M, - 1, 1), - TOP_FACTOR(CK_INFRA_PERI_133M, "infra_peri_133m", CK_TOP_SYSAXI, 1, 1), - TOP_FACTOR(CK_INFRA_133M_PHCK, "infra_133m_phck", CK_TOP_SYSAXI, 1, 1), - TOP_FACTOR(CK_INFRA_USB_SYS_CK, "infra_usb_sys", CK_TOP_U2U3_SYS, 1, 1), - TOP_FACTOR(CK_INFRA_USB_CK, "infra_usb", CK_TOP_U2U3_REF, 1, 1), - TOP_FACTOR(CK_INFRA_USB_XHCI_CK, "infra_usb_xhci", CK_TOP_U2U3_XHCI, 1, - 1), - TOP_FACTOR(CK_INFRA_PCIE_GFMUX_TL_O_PRE, "infra_pcie_mux", - CK_TOP_PEXTP_TL, 1, 1), - TOP_FACTOR(CK_INFRA_F26M_CK0, "infra_f26m_ck0", CK_TOP_F26M, 1, 1), - TOP_FACTOR(CK_INFRA_133M_MCK, "infra_133m_mck", CK_TOP_SYSAXI, 1, 1), + TOP_FACTOR(CLK_INFRA_66M_MCK, "infra_66m_mck", CLK_TOP_SYSAXI_SEL, 1, 2), }; /* INFRASYS MUX PARENTS */ -static const int infra_uart0_parents[] = { CK_INFRA_CK_F26M, CK_INFRA_UART }; +#define INFRA_PARENT(_id) PARENT(_id, CLK_PARENT_INFRASYS) +#define TOP_PARENT(_id) PARENT(_id, CLK_PARENT_TOPCKGEN) +#define VOID_PARENT PARENT(-1, 0) -static const int infra_spi0_parents[] = { CK_INFRA_I2C, CK_INFRA_ISPI0 }; +static const struct mtk_parent infra_uart0_parents[] = { + TOP_PARENT(CLK_TOP_F26M_SEL), + TOP_PARENT(CLK_TOP_UART_SEL) +}; + +static const struct mtk_parent infra_spi0_parents[] = { + TOP_PARENT(CLK_TOP_I2C_SEL), + TOP_PARENT(CLK_TOP_SPI_SEL) +}; -static const int infra_spi1_parents[] = { CK_INFRA_I2C, CK_INFRA_ISPI1 }; +static const struct mtk_parent infra_spi1_parents[] = { + TOP_PARENT(CLK_TOP_I2C_SEL), + TOP_PARENT(CLK_TOP_SPIM_MST_SEL) +}; -static const int infra_pwm1_parents[] = { -1, -1, -1, CK_INFRA_PWM }; +static const struct mtk_parent infra_pwm1_parents[] = { + VOID_PARENT, + TOP_PARENT(CLK_TOP_PWM_SEL) +}; -static const int infra_pwm_bsel_parents[] = { -1, -1, -1, CK_INFRA_PWM }; +static const struct mtk_parent infra_pwm_bsel_parents[] = { + TOP_PARENT(CLK_TOP_CB_RTC_32P7K), + TOP_PARENT(CLK_TOP_F26M_SEL), + INFRA_PARENT(CLK_INFRA_66M_MCK), + TOP_PARENT(CLK_TOP_PWM_SEL) +}; -static const int infra_pcie_parents[] = { CK_INFRA_CK_F32K, CK_INFRA_CK_F26M, - CK_TOP_CB_CKSQ_40M, CK_INFRA_PCIE_CK}; +static const struct mtk_parent infra_pcie_parents[] = { + TOP_PARENT(CLK_TOP_CB_RTC_32P7K), + TOP_PARENT(CLK_TOP_F26M_SEL), + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_PEXTP_TL_SEL) +}; #define INFRA_MUX(_id, _name, _parents, _reg, _shift, _width) \ { \ .id = _id, .mux_reg = (_reg) + 0x8, \ .mux_set_reg = (_reg) + 0x0, .mux_clr_reg = (_reg) + 0x4, \ .mux_shift = _shift, .mux_mask = BIT(_width) - 1, \ - .parent = _parents, .num_parents = ARRAY_SIZE(_parents), \ - .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_INFRASYS, \ + .parent_flags = _parents, .num_parents = ARRAY_SIZE(_parents), \ + .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_MIXED, \ } /* INFRA MUX */ static const struct mtk_composite infra_muxes[] = { - INFRA_MUX(CK_INFRA_UART0_SEL, "infra_uart0_sel", infra_uart0_parents, + INFRA_MUX(CLK_INFRA_UART0_SEL, "infra_uart0_sel", infra_uart0_parents, 0x10, 0, 1), - INFRA_MUX(CK_INFRA_UART1_SEL, "infra_uart1_sel", infra_uart0_parents, + INFRA_MUX(CLK_INFRA_UART1_SEL, "infra_uart1_sel", infra_uart0_parents, 0x10, 1, 1), - INFRA_MUX(CK_INFRA_UART2_SEL, "infra_uart2_sel", infra_uart0_parents, + INFRA_MUX(CLK_INFRA_UART2_SEL, "infra_uart2_sel", infra_uart0_parents, 0x10, 2, 1), - INFRA_MUX(CK_INFRA_SPI0_SEL, "infra_spi0_sel", infra_spi0_parents, 0x10, + INFRA_MUX(CLK_INFRA_SPI0_SEL, "infra_spi0_sel", infra_spi0_parents, 0x10, 4, 1), - INFRA_MUX(CK_INFRA_SPI1_SEL, "infra_spi1_sel", infra_spi1_parents, 0x10, + INFRA_MUX(CLK_INFRA_SPI1_SEL, "infra_spi1_sel", infra_spi1_parents, 0x10, 5, 1), - INFRA_MUX(CK_INFRA_SPI2_SEL, "infra_spi2_sel", infra_spi0_parents, 0x10, + INFRA_MUX(CLK_INFRA_SPI2_SEL, "infra_spi2_sel", infra_spi0_parents, 0x10, 6, 1), - INFRA_MUX(CK_INFRA_PWM1_SEL, "infra_pwm1_sel", infra_pwm1_parents, 0x10, - 9, 2), - INFRA_MUX(CK_INFRA_PWM2_SEL, "infra_pwm2_sel", infra_pwm1_parents, 0x10, - 11, 2), - INFRA_MUX(CK_INFRA_PWM_BSEL, "infra_pwm_bsel", infra_pwm_bsel_parents, + INFRA_MUX(CLK_INFRA_PWM1_SEL, "infra_pwm1_sel", infra_pwm1_parents, 0x10, + 9, 1), + INFRA_MUX(CLK_INFRA_PWM2_SEL, "infra_pwm2_sel", infra_pwm1_parents, 0x10, + 11, 1), + INFRA_MUX(CLK_INFRA_PWM3_SEL, "infra_pwm3_sel", infra_pwm1_parents, 0x10, + 15, 1), + INFRA_MUX(CLK_INFRA_PWM_BSEL, "infra_pwm_bsel", infra_pwm_bsel_parents, 0x10, 13, 2), - INFRA_MUX(CK_INFRA_PCIE_SEL, "infra_pcie_sel", infra_pcie_parents, 0x20, + INFRA_MUX(CLK_INFRA_PCIE_SEL, "infra_pcie_sel", infra_pcie_parents, 0x20, 0, 2), }; @@ -431,92 +407,105 @@ static const struct mtk_gate_regs infra_2_cg_regs = { .sta_ofs = 0x68, }; -#define GATE_INFRA0(_id, _name, _parent, _shift) \ +#define GATE_INFRA0(_id, _name, _parent, _shift, _flags) \ { \ .id = _id, .parent = _parent, .regs = &infra_0_cg_regs, \ .shift = _shift, \ - .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \ + .flags = _flags, \ } +#define GATE_INFRA0_INFRA(_id, _name, _parent, _shift) \ + GATE_INFRA0(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS) +#define GATE_INFRA0_TOP(_id, _name, _parent, _shift) \ + GATE_INFRA0(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) -#define GATE_INFRA1(_id, _name, _parent, _shift) \ +#define GATE_INFRA1(_id, _name, _parent, _shift, _flags) \ { \ .id = _id, .parent = _parent, .regs = &infra_1_cg_regs, \ .shift = _shift, \ - .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \ + .flags = _flags, \ } +#define GATE_INFRA1_INFRA(_id, _name, _parent, _shift) \ + GATE_INFRA1(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS) +#define GATE_INFRA1_TOP(_id, _name, _parent, _shift) \ + GATE_INFRA1(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) -#define GATE_INFRA2(_id, _name, _parent, _shift) \ +#define GATE_INFRA2(_id, _name, _parent, _shift, _flags) \ { \ .id = _id, .parent = _parent, .regs = &infra_2_cg_regs, \ .shift = _shift, \ - .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \ + .flags = _flags, \ } +#define GATE_INFRA2_INFRA(_id, _name, _parent, _shift) \ + GATE_INFRA2(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS) +#define GATE_INFRA2_TOP(_id, _name, _parent, _shift) \ + GATE_INFRA2(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) /* INFRA GATE */ -static const struct mtk_gate infracfg_ao_gates[] = { - GATE_INFRA0(CK_INFRA_GPT_STA, "infra_gpt_sta", CK_INFRA_66M_MCK, 0), - GATE_INFRA0(CK_INFRA_PWM_HCK, "infra_pwm_hck", CK_INFRA_66M_MCK, 1), - GATE_INFRA0(CK_INFRA_PWM_STA, "infra_pwm_sta", CK_INFRA_PWM_BCK, 2), - GATE_INFRA0(CK_INFRA_PWM1_CK, "infra_pwm1", CK_INFRA_PWM_CK1, 3), - GATE_INFRA0(CK_INFRA_PWM2_CK, "infra_pwm2", CK_INFRA_PWM_CK2, 4), - GATE_INFRA0(CK_INFRA_CQ_DMA_CK, "infra_cq_dma", CK_INFRA_133M_HCK, 6), - GATE_INFRA0(CK_INFRA_AUD_BUS_CK, "infra_aud_bus", CK_INFRA_66M_PHCK, 8), - GATE_INFRA0(CK_INFRA_AUD_26M_CK, "infra_aud_26m", CK_INFRA_CK_F26M, 9), - GATE_INFRA0(CK_INFRA_AUD_L_CK, "infra_aud_l", CK_INFRA_FAUD_L_CK, 10), - GATE_INFRA0(CK_INFRA_AUD_AUD_CK, "infra_aud_aud", CK_INFRA_FAUD_AUD_CK, - 11), - GATE_INFRA0(CK_INFRA_AUD_EG2_CK, "infra_aud_eg2", CK_INFRA_FAUD_EG2_CK, - 13), - GATE_INFRA0(CK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", CK_INFRA_CK_F26M, - 14), - GATE_INFRA0(CK_INFRA_DBG_CK, "infra_dbg", CK_INFRA_66M_MCK, 15), - GATE_INFRA0(CK_INFRA_AP_DMA_CK, "infra_ap_dma", CK_INFRA_66M_MCK, 16), - GATE_INFRA0(CK_INFRA_SEJ_CK, "infra_sej", CK_INFRA_66M_MCK, 24), - GATE_INFRA0(CK_INFRA_SEJ_13M_CK, "infra_sej_13m", CK_INFRA_CK_F26M, 25), - GATE_INFRA1(CK_INFRA_THERM_CK, "infra_therm", CK_INFRA_CK_F26M, 0), - GATE_INFRA1(CK_INFRA_I2CO_CK, "infra_i2co", CK_INFRA_I2CS_CK, 1), - GATE_INFRA1(CK_INFRA_UART0_CK, "infra_uart0", CK_INFRA_MUX_UART0, 2), - GATE_INFRA1(CK_INFRA_UART1_CK, "infra_uart1", CK_INFRA_MUX_UART1, 3), - GATE_INFRA1(CK_INFRA_UART2_CK, "infra_uart2", CK_INFRA_MUX_UART2, 4), - GATE_INFRA1(CK_INFRA_SPI2_CK, "infra_spi2", CK_INFRA_MUX_SPI2, 6), - GATE_INFRA1(CK_INFRA_SPI2_HCK_CK, "infra_spi2_hck", CK_INFRA_66M_MCK, - 7), - GATE_INFRA1(CK_INFRA_NFI1_CK, "infra_nfi1", CK_INFRA_NFI_CK, 8), - GATE_INFRA1(CK_INFRA_SPINFI1_CK, "infra_spinfi1", CK_INFRA_SPINFI_CK, +static const struct mtk_gate infracfg_gates[] = { + GATE_INFRA0_INFRA(CLK_INFRA_GPT_STA, "infra_gpt_sta", CLK_INFRA_66M_MCK, 0), + GATE_INFRA0_INFRA(CLK_INFRA_PWM_HCK, "infra_pwm_hck", CLK_INFRA_66M_MCK, 1), + GATE_INFRA0_INFRA(CLK_INFRA_PWM_STA, "infra_pwm_sta", CLK_INFRA_PWM_BSEL, 2), + GATE_INFRA0_INFRA(CLK_INFRA_PWM1_CK, "infra_pwm1", CLK_INFRA_PWM1_SEL, 3), + GATE_INFRA0_INFRA(CLK_INFRA_PWM2_CK, "infra_pwm2", CLK_INFRA_PWM2_SEL, 4), + GATE_INFRA0_INFRA(CLK_INFRA_PWM3_CK, "infra_pwm3", CLK_INFRA_PWM3_SEL, 27), + GATE_INFRA0_TOP(CLK_INFRA_CQ_DMA_CK, "infra_cq_dma", CLK_TOP_SYSAXI, 6), + GATE_INFRA0_TOP(CLK_INFRA_AUD_BUS_CK, "infra_aud_bus", CLK_TOP_SYSAXI, 8), + GATE_INFRA0_TOP(CLK_INFRA_AUD_26M_CK, "infra_aud_26m", CLK_TOP_F26M_SEL, 9), + GATE_INFRA0_TOP(CLK_INFRA_AUD_L_CK, "infra_aud_l", CLK_TOP_AUD_L, 10), + GATE_INFRA0_TOP(CLK_INFRA_AUD_AUD_CK, "infra_aud_aud", CLK_TOP_A1SYS, + 11), + GATE_INFRA0_TOP(CLK_INFRA_AUD_EG2_CK, "infra_aud_eg2", CLK_TOP_A_TUNER, + 13), + GATE_INFRA0_TOP(CLK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", CLK_TOP_F26M_SEL, + 14), + GATE_INFRA0_INFRA(CLK_INFRA_DBG_CK, "infra_dbg", CLK_INFRA_66M_MCK, 15), + GATE_INFRA0_INFRA(CLK_INFRA_AP_DMA_CK, "infra_ap_dma", CLK_INFRA_66M_MCK, 16), + GATE_INFRA0_INFRA(CLK_INFRA_SEJ_CK, "infra_sej", CLK_INFRA_66M_MCK, 24), + GATE_INFRA0_TOP(CLK_INFRA_SEJ_13M_CK, "infra_sej_13m", CLK_TOP_F26M_SEL, 25), + GATE_INFRA1_TOP(CLK_INFRA_THERM_CK, "infra_therm", CLK_TOP_F26M_SEL, 0), + GATE_INFRA1_TOP(CLK_INFRA_I2C0_CK, "infra_i2c0", CLK_TOP_I2C_BCK, 1), + GATE_INFRA1_INFRA(CLK_INFRA_UART0_CK, "infra_uart0", CLK_INFRA_UART0_SEL, 2), + GATE_INFRA1_INFRA(CLK_INFRA_UART1_CK, "infra_uart1", CLK_INFRA_UART1_SEL, 3), + GATE_INFRA1_INFRA(CLK_INFRA_UART2_CK, "infra_uart2", CLK_INFRA_UART2_SEL, 4), + GATE_INFRA1_INFRA(CLK_INFRA_SPI2_CK, "infra_spi2", CLK_INFRA_SPI2_SEL, 6), + GATE_INFRA1_INFRA(CLK_INFRA_SPI2_HCK_CK, "infra_spi2_hck", CLK_INFRA_66M_MCK, + 7), + GATE_INFRA1_TOP(CLK_INFRA_NFI1_CK, "infra_nfi1", CLK_TOP_NFI1X, 8), + GATE_INFRA1_TOP(CLK_INFRA_SPINFI1_CK, "infra_spinfi1", CLK_TOP_SPINFI_BCK, 9), - GATE_INFRA1(CK_INFRA_NFI_HCK_CK, "infra_nfi_hck", CK_INFRA_66M_MCK, 10), - GATE_INFRA1(CK_INFRA_SPI0_CK, "infra_spi0", CK_INFRA_MUX_SPI0, 11), - GATE_INFRA1(CK_INFRA_SPI1_CK, "infra_spi1", CK_INFRA_MUX_SPI1, 12), - GATE_INFRA1(CK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", CK_INFRA_66M_MCK, - 13), - GATE_INFRA1(CK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", CK_INFRA_66M_MCK, - 14), - GATE_INFRA1(CK_INFRA_FRTC_CK, "infra_frtc", CK_INFRA_RTC_32K, 15), - GATE_INFRA1(CK_INFRA_MSDC_CK, "infra_msdc", CK_INFRA_FMSDC_CK, 16), - GATE_INFRA1(CK_INFRA_MSDC_HCK_CK, "infra_msdc_hck", - CK_INFRA_FMSDC_HCK_CK, 17), - GATE_INFRA1(CK_INFRA_MSDC_133M_CK, "infra_msdc_133m", - CK_INFRA_PERI_133M, 18), - GATE_INFRA1(CK_INFRA_MSDC_66M_CK, "infra_msdc_66m", CK_INFRA_66M_PHCK, - 19), - GATE_INFRA1(CK_INFRA_ADC_26M_CK, "infra_adc_26m", CK_TOP_F26M, 20), - GATE_INFRA1(CK_INFRA_ADC_FRC_CK, "infra_adc_frc", CK_TOP_F26M, 21), - GATE_INFRA1(CK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", CK_INFRA_NFI_CK, - 23), - GATE_INFRA1(CK_INFRA_I2C_MCK_CK, "infra_i2c_mck", CK_INFRA_133M_MCK, - 25), - GATE_INFRA1(CK_INFRA_I2C_PCK_CK, "infra_i2c_pck", CK_INFRA_66M_MCK, 26), - GATE_INFRA2(CK_INFRA_IUSB_133_CK, "infra_iusb_133", CK_INFRA_133M_PHCK, - 0), - GATE_INFRA2(CK_INFRA_IUSB_66M_CK, "infra_iusb_66m", CK_INFRA_66M_PHCK, - 1), - GATE_INFRA2(CK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", CK_INFRA_USB_SYS_CK, - 2), - GATE_INFRA2(CK_INFRA_IUSB_CK, "infra_iusb", CK_INFRA_USB_CK, 3), - GATE_INFRA2(CK_INFRA_IPCIE_CK, "infra_ipcie", - CK_INFRA_PCIE_GFMUX_TL_O_PRE, 12), - GATE_INFRA2(CK_INFRA_IPCIER_CK, "infra_ipcier", CK_INFRA_F26M_CK0, 14), - GATE_INFRA2(CK_INFRA_IPCIEB_CK, "infra_ipcieb", CK_INFRA_133M_PHCK, 15), + GATE_INFRA1_INFRA(CLK_INFRA_NFI_HCK_CK, "infra_nfi_hck", CLK_INFRA_66M_MCK, 10), + GATE_INFRA1_INFRA(CLK_INFRA_SPI0_CK, "infra_spi0", CLK_INFRA_SPI0_SEL, 11), + GATE_INFRA1_INFRA(CLK_INFRA_SPI1_CK, "infra_spi1", CLK_INFRA_SPI1_SEL, 12), + GATE_INFRA1_INFRA(CLK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", CLK_INFRA_66M_MCK, + 13), + GATE_INFRA1_INFRA(CLK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", CLK_INFRA_66M_MCK, + 14), + GATE_INFRA1_TOP(CLK_INFRA_FRTC_CK, "infra_frtc", CLK_TOP_CB_RTC_32K, 15), + GATE_INFRA1_TOP(CLK_INFRA_MSDC_CK, "infra_msdc", CLK_TOP_EMMC_400M, 16), + GATE_INFRA1_TOP(CLK_INFRA_MSDC_HCK_CK, "infra_msdc_hck", + CLK_TOP_EMMC_208M, 17), + GATE_INFRA1_TOP(CLK_INFRA_MSDC_133M_CK, "infra_msdc_133m", + CLK_TOP_SYSAXI, 18), + GATE_INFRA1_TOP(CLK_INFRA_MSDC_66M_CK, "infra_msdc_66m", CLK_TOP_SYSAXI, + 19), + GATE_INFRA1_INFRA(CLK_INFRA_ADC_26M_CK, "infra_adc_26m", CLK_INFRA_ADC_FRC_CK, 20), + GATE_INFRA1_TOP(CLK_INFRA_ADC_FRC_CK, "infra_adc_frc", CLK_TOP_F26M, 21), + GATE_INFRA1_TOP(CLK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", CLK_TOP_NFI1X, + 23), + GATE_INFRA1_TOP(CLK_INFRA_I2C_MCK_CK, "infra_i2c_mck", CLK_TOP_SYSAXI, + 25), + GATE_INFRA1_INFRA(CLK_INFRA_I2C_PCK_CK, "infra_i2c_pck", CLK_INFRA_66M_MCK, 26), + GATE_INFRA2_TOP(CLK_INFRA_IUSB_133_CK, "infra_iusb_133", CLK_TOP_SYSAXI, + 0), + GATE_INFRA2_TOP(CLK_INFRA_IUSB_66M_CK, "infra_iusb_66m", CLK_TOP_SYSAXI, + 1), + GATE_INFRA2_TOP(CLK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", CLK_TOP_U2U3_SYS, + 2), + GATE_INFRA2_TOP(CLK_INFRA_IUSB_CK, "infra_iusb", CLK_TOP_U2U3_REF, 3), + GATE_INFRA2_TOP(CLK_INFRA_IPCIE_CK, "infra_ipcie", CLK_TOP_PEXTP_TL, 12), + GATE_INFRA2_TOP(CLK_INFRA_IPCIE_PIPE_CK, "infra_ipcie_pipe", CLK_TOP_CB_CKSQ_40M, 13), + GATE_INFRA2_TOP(CLK_INFRA_IPCIER_CK, "infra_ipcier", CLK_TOP_F26M, 14), + GATE_INFRA2_TOP(CLK_INFRA_IPCIEB_CK, "infra_ipcieb", CLK_TOP_SYSAXI, 15), }; static const struct mtk_clk_tree mt7981_fixed_pll_clk_tree = { @@ -526,19 +515,22 @@ static const struct mtk_clk_tree mt7981_fixed_pll_clk_tree = { }; static const struct mtk_clk_tree mt7981_topckgen_clk_tree = { - .fdivs_offs = CK_TOP_CB_M_416M, - .muxes_offs = CK_TOP_NFI1X_SEL, + .fdivs_offs = CLK_TOP_CB_M_416M, + .muxes_offs = CLK_TOP_NFI1X_SEL, .fclks = top_fixed_clks, .fdivs = top_fixed_divs, .muxes = top_muxes, - .flags = CLK_BYPASS_XTAL, + .flags = CLK_BYPASS_XTAL | CLK_TOPCKGEN, }; static const struct mtk_clk_tree mt7981_infracfg_clk_tree = { - .fdivs_offs = CK_INFRA_CK_F26M, - .muxes_offs = CK_INFRA_UART0_SEL, + .fdivs_offs = CLK_INFRA_66M_MCK, + .muxes_offs = CLK_INFRA_UART0_SEL, + .gates_offs = CLK_INFRA_GPT_STA, .fdivs = infra_fixed_divs, .muxes = infra_muxes, + .gates = infracfg_gates, + .flags = CLK_INFRASYS, }; static const struct udevice_id mt7981_fixed_pll_compat[] = { @@ -592,20 +584,9 @@ static const struct udevice_id mt7981_infracfg_compat[] = { {} }; -static const struct udevice_id mt7981_infracfg_ao_compat[] = { - { .compatible = "mediatek,mt7981-infracfg_ao" }, - {} -}; - static int mt7981_infracfg_probe(struct udevice *dev) { - return mtk_common_clk_init(dev, &mt7981_infracfg_clk_tree); -} - -static int mt7981_infracfg_ao_probe(struct udevice *dev) -{ - return mtk_common_clk_gate_init(dev, &mt7981_infracfg_clk_tree, - infracfg_ao_gates); + return mtk_common_clk_infrasys_init(dev, &mt7981_infracfg_clk_tree); } U_BOOT_DRIVER(mtk_clk_infracfg) = { @@ -618,14 +599,72 @@ U_BOOT_DRIVER(mtk_clk_infracfg) = { .flags = DM_FLAG_PRE_RELOC, }; -U_BOOT_DRIVER(mtk_clk_infracfg_ao) = { - .name = "mt7981-clock-infracfg-ao", +/* sgmiisys */ +static const struct mtk_gate_regs sgmii_cg_regs = { + .set_ofs = 0xe4, + .clr_ofs = 0xe4, + .sta_ofs = 0xe4, +}; + +#define GATE_SGMII(_id, _name, _parent, _shift) \ + { \ + .id = _id, .parent = _parent, .regs = &sgmii_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \ + } + +static const struct mtk_gate sgmii0_cgs[] = { + GATE_SGMII(CLK_SGM0_TX_EN, "sgm0_tx_en", CLK_TOP_USB_TX250M, 2), + GATE_SGMII(CLK_SGM0_RX_EN, "sgm0_rx_en", CLK_TOP_USB_EQ_RX250M, 3), + GATE_SGMII(CLK_SGM0_CK0_EN, "sgm0_ck0_en", CLK_TOP_USB_LN0_CK, 4), + GATE_SGMII(CLK_SGM0_CDR_CK0_EN, "sgm0_cdr_ck0_en", CLK_TOP_USB_CDR_CK, 5), +}; + +static int mt7981_sgmii0sys_probe(struct udevice *dev) +{ + return mtk_common_clk_gate_init(dev, &mt7981_topckgen_clk_tree, + sgmii0_cgs); +} + +static const struct udevice_id mt7981_sgmii0sys_compat[] = { + { .compatible = "mediatek,mt7981-sgmiisys_0", }, + {} +}; + +U_BOOT_DRIVER(mtk_clk_sgmii0sys) = { + .name = "mt7981-clock-sgmii0sys", .id = UCLASS_CLK, - .of_match = mt7981_infracfg_ao_compat, - .probe = mt7981_infracfg_ao_probe, + .of_match = mt7981_sgmii0sys_compat, + .probe = mt7981_sgmii0sys_probe, + .priv_auto = sizeof(struct mtk_cg_priv), + .ops = &mtk_clk_gate_ops, +}; + +static const struct mtk_gate sgmii1_cgs[] = { + GATE_SGMII(CLK_SGM1_TX_EN, "sgm1_tx_en", CLK_TOP_USB_TX250M, 2), + GATE_SGMII(CLK_SGM1_RX_EN, "sgm1_rx_en", CLK_TOP_USB_EQ_RX250M, 3), + GATE_SGMII(CLK_SGM1_CK1_EN, "sgm1_ck1_en", CLK_TOP_USB_LN0_CK, 4), + GATE_SGMII(CLK_SGM1_CDR_CK1_EN, "sgm1_cdr_ck1_en", CLK_TOP_USB_CDR_CK, 5), +}; + +static int mt7981_sgmii1sys_probe(struct udevice *dev) +{ + return mtk_common_clk_gate_init(dev, &mt7981_topckgen_clk_tree, + sgmii1_cgs); +} + +static const struct udevice_id mt7981_sgmii1sys_compat[] = { + { .compatible = "mediatek,mt7981-sgmiisys_1", }, + {} +}; + +U_BOOT_DRIVER(mtk_clk_sgmii1sys) = { + .name = "mt7981-clock-sgmii1sys", + .id = UCLASS_CLK, + .of_match = mt7981_sgmii1sys_compat, + .probe = mt7981_sgmii1sys_probe, .priv_auto = sizeof(struct mtk_cg_priv), .ops = &mtk_clk_gate_ops, - .flags = DM_FLAG_PRE_RELOC, }; /* ethsys */ @@ -643,10 +682,10 @@ static const struct mtk_gate_regs eth_cg_regs = { } static const struct mtk_gate eth_cgs[] = { - GATE_ETH(CK_ETH_FE_EN, "eth_fe_en", CK_TOP_NETSYS_2X, 6), - GATE_ETH(CK_ETH_GP2_EN, "eth_gp2_en", CK_TOP_SGM_325M, 7), - GATE_ETH(CK_ETH_GP1_EN, "eth_gp1_en", CK_TOP_SGM_325M, 8), - GATE_ETH(CK_ETH_WOCPU0_EN, "eth_wocpu0_en", CK_TOP_NETSYS_WED_MCU, 15), + GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", CLK_TOP_NETSYS_2X, 6), + GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", CLK_TOP_SGM_325M, 7), + GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", CLK_TOP_SGM_325M, 8), + GATE_ETH(CLK_ETH_WOCPU0_EN, "eth_wocpu0_en", CLK_TOP_NETSYS_WED_MCU, 15), }; static int mt7981_ethsys_probe(struct udevice *dev) diff --git a/drivers/clk/mediatek/clk-mt7986.c b/drivers/clk/mediatek/clk-mt7986.c index efc3d4120b7..c5cc77243d0 100644 --- a/drivers/clk/mediatek/clk-mt7986.c +++ b/drivers/clk/mediatek/clk-mt7986.c @@ -18,6 +18,11 @@ #define MT7986_CLK_PDN 0x250 #define MT7986_CLK_PDN_EN_WRITE BIT(31) +#define APMIXED_PARENT(_id) PARENT(_id, CLK_PARENT_APMIXED) +#define INFRA_PARENT(_id) PARENT(_id, CLK_PARENT_INFRASYS) +#define TOP_PARENT(_id) PARENT(_id, CLK_PARENT_TOPCKGEN) +#define VOID_PARENT PARENT(-1, 0) + #define PLL_FACTOR(_id, _name, _parent, _mult, _div) \ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) @@ -29,177 +34,195 @@ /* FIXED PLLS */ static const struct mtk_fixed_clk fixed_pll_clks[] = { - FIXED_CLK(CK_APMIXED_ARMPLL, CLK_XTAL, 2000000000), - FIXED_CLK(CK_APMIXED_NET2PLL, CLK_XTAL, 800000000), - FIXED_CLK(CK_APMIXED_MMPLL, CLK_XTAL, 1440000000), - FIXED_CLK(CK_APMIXED_SGMPLL, CLK_XTAL, 325000000), - FIXED_CLK(CK_APMIXED_WEDMCUPLL, CLK_XTAL, 760000000), - FIXED_CLK(CK_APMIXED_NET1PLL, CLK_XTAL, 2500000000), - FIXED_CLK(CK_APMIXED_MPLL, CLK_XTAL, 416000000), - FIXED_CLK(CK_APMIXED_APLL2, CLK_XTAL, 196608000), + FIXED_CLK(CLK_APMIXED_ARMPLL, CLK_XTAL, 2000000000), + FIXED_CLK(CLK_APMIXED_NET2PLL, CLK_XTAL, 800000000), + FIXED_CLK(CLK_APMIXED_MMPLL, CLK_XTAL, 1440000000), + FIXED_CLK(CLK_APMIXED_SGMPLL, CLK_XTAL, 325000000), + FIXED_CLK(CLK_APMIXED_WEDMCUPLL, CLK_XTAL, 760000000), + FIXED_CLK(CLK_APMIXED_NET1PLL, CLK_XTAL, 2500000000), + FIXED_CLK(CLK_APMIXED_MPLL, CLK_XTAL, 416000000), + FIXED_CLK(CLK_APMIXED_APLL2, CLK_XTAL, 196608000), }; /* TOPCKGEN FIXED CLK */ static const struct mtk_fixed_clk top_fixed_clks[] = { - FIXED_CLK(CK_TOP_CB_CKSQ_40M, CLK_XTAL, 40000000), + FIXED_CLK(CLK_TOP_XTAL, CLK_XTAL, 40000000), }; /* TOPCKGEN FIXED DIV */ static const struct mtk_fixed_factor top_fixed_divs[] = { - PLL_FACTOR(CK_TOP_CB_M_416M, "cb_m_416m", CK_APMIXED_MPLL, 1, 1), - PLL_FACTOR(CK_TOP_CB_M_D2, "cb_m_d2", CK_APMIXED_MPLL, 1, 2), - PLL_FACTOR(CK_TOP_CB_M_D4, "cb_m_d4", CK_APMIXED_MPLL, 1, 4), - PLL_FACTOR(CK_TOP_CB_M_D8, "cb_m_d8", CK_APMIXED_MPLL, 1, 8), - PLL_FACTOR(CK_TOP_M_D8_D2, "m_d8_d2", CK_APMIXED_MPLL, 1, 16), - PLL_FACTOR(CK_TOP_M_D3_D2, "m_d3_d2", CK_APMIXED_MPLL, 1, 2), - PLL_FACTOR(CK_TOP_CB_MM_D2, "cb_mm_d2", CK_APMIXED_MMPLL, 1, 2), - PLL_FACTOR(CK_TOP_CB_MM_D4, "cb_mm_d4", CK_APMIXED_MMPLL, 1, 4), - PLL_FACTOR(CK_TOP_CB_MM_D8, "cb_mm_d8", CK_APMIXED_MMPLL, 1, 8), - PLL_FACTOR(CK_TOP_MM_D8_D2, "mm_d8_d2", CK_APMIXED_MMPLL, 1, 16), - PLL_FACTOR(CK_TOP_MM_D3_D8, "mm_d3_d8", CK_APMIXED_MMPLL, 1, 8), - PLL_FACTOR(CK_TOP_CB_U2_PHYD_CK, "cb_u2_phyd", CK_APMIXED_MMPLL, 1, 30), - PLL_FACTOR(CK_TOP_CB_APLL2_196M, "cb_apll2_196m", CK_APMIXED_APLL2, 1, - 1), - PLL_FACTOR(CK_TOP_APLL2_D4, "apll2_d4", CK_APMIXED_APLL2, 1, 4), - PLL_FACTOR(CK_TOP_CB_NET1_D4, "cb_net1_d4", CK_APMIXED_NET1PLL, 1, 4), - PLL_FACTOR(CK_TOP_CB_NET1_D5, "cb_net1_d5", CK_APMIXED_NET1PLL, 1, 5), - PLL_FACTOR(CK_TOP_NET1_D5_D2, "net1_d5_d2", CK_APMIXED_NET1PLL, 1, 10), - PLL_FACTOR(CK_TOP_NET1_D5_D4, "net1_d5_d4", CK_APMIXED_NET1PLL, 1, 20), - PLL_FACTOR(CK_TOP_NET1_D8_D2, "net1_d8_d2", CK_APMIXED_NET1PLL, 1, 16), - PLL_FACTOR(CK_TOP_NET1_D8_D4, "net1_d8_d4", CK_APMIXED_NET1PLL, 1, 32), - PLL_FACTOR(CK_TOP_CB_NET2_800M, "cb_net2_800m", CK_APMIXED_NET2PLL, 1, - 1), - PLL_FACTOR(CK_TOP_CB_NET2_D4, "cb_net2_d4", CK_APMIXED_NET2PLL, 1, 4), - PLL_FACTOR(CK_TOP_NET2_D4_D2, "net2_d4_d2", CK_APMIXED_NET2PLL, 1, 8), - PLL_FACTOR(CK_TOP_NET2_D3_D2, "net2_d3_d2", CK_APMIXED_NET2PLL, 1, 2), - PLL_FACTOR(CK_TOP_CB_WEDMCU_760M, "cb_wedmcu_760m", - CK_APMIXED_WEDMCUPLL, 1, 1), - PLL_FACTOR(CK_TOP_WEDMCU_D5_D2, "wedmcu_d5_d2", CK_APMIXED_WEDMCUPLL, 1, - 10), - PLL_FACTOR(CK_TOP_CB_SGM_325M, "cb_sgm_325m", CK_APMIXED_SGMPLL, 1, 1), - TOP_FACTOR(CK_TOP_CB_CKSQ_40M_D2, "cb_cksq_40m_d2", CK_TOP_CB_CKSQ_40M, + /* TOP Factors */ + TOP_FACTOR(CLK_TOP_XTAL_D2, "xtal_d2", CLK_TOP_XTAL, 1, 2), - TOP_FACTOR(CK_TOP_CB_RTC_32K, "cb_rtc_32k", CK_TOP_CB_CKSQ_40M, 1, + TOP_FACTOR(CLK_TOP_RTC_32K, "rtc_32k", CLK_TOP_XTAL, 1, 1250), - TOP_FACTOR(CK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", CK_TOP_CB_CKSQ_40M, 1, + TOP_FACTOR(CLK_TOP_RTC_32P7K, "rtc_32p7k", CLK_TOP_XTAL, 1, 1220), - TOP_FACTOR(CK_TOP_NFI1X, "nfi1x", CK_TOP_NFI1X_SEL, 1, 1), - TOP_FACTOR(CK_TOP_USB_EQ_RX250M, "usb_eq_rx250m", CK_TOP_CB_CKSQ_40M, 1, - 1), - TOP_FACTOR(CK_TOP_USB_TX250M, "usb_tx250m", CK_TOP_CB_CKSQ_40M, 1, 1), - TOP_FACTOR(CK_TOP_USB_LN0_CK, "usb_ln0", CK_TOP_CB_CKSQ_40M, 1, 1), - TOP_FACTOR(CK_TOP_USB_CDR_CK, "usb_cdr", CK_TOP_CB_CKSQ_40M, 1, 1), - TOP_FACTOR(CK_TOP_SPINFI_BCK, "spinfi_bck", CK_TOP_SPINFI_SEL, 1, 1), - TOP_FACTOR(CK_TOP_I2C_BCK, "i2c_bck", CK_TOP_I2C_SEL, 1, 1), - TOP_FACTOR(CK_TOP_PEXTP_TL, "pextp_tl", CK_TOP_PEXTP_TL_SEL, 1, 1), - TOP_FACTOR(CK_TOP_EMMC_250M, "emmc_250m", CK_TOP_EMMC_250M_SEL, 1, 1), - TOP_FACTOR(CK_TOP_EMMC_416M, "emmc_416m", CK_TOP_EMMC_416M_SEL, 1, 1), - TOP_FACTOR(CK_TOP_F_26M_ADC_CK, "f_26m_adc", CK_TOP_F_26M_ADC_SEL, 1, - 1), - TOP_FACTOR(CK_TOP_SYSAXI, "sysaxi", CK_TOP_SYSAXI_SEL, 1, 1), - TOP_FACTOR(CK_TOP_NETSYS_WED_MCU, "netsys_wed_mcu", - CK_TOP_NETSYS_MCU_SEL, 1, 1), - TOP_FACTOR(CK_TOP_NETSYS_2X, "netsys_2x", CK_TOP_NETSYS_2X_SEL, 1, 1), - TOP_FACTOR(CK_TOP_SGM_325M, "sgm_325m", CK_TOP_SGM_325M_SEL, 1, 1), - TOP_FACTOR(CK_TOP_A1SYS, "a1sys", CK_TOP_A1SYS_SEL, 1, 1), - TOP_FACTOR(CK_TOP_EIP_B, "eip_b", CK_TOP_EIP_B_SEL, 1, 1), - TOP_FACTOR(CK_TOP_F26M, "csw_f26m", CK_TOP_F26M_SEL, 1, 1), - TOP_FACTOR(CK_TOP_AUD_L, "aud_l", CK_TOP_AUD_L_SEL, 1, 1), - TOP_FACTOR(CK_TOP_A_TUNER, "a_tuner", CK_TOP_A_TUNER_SEL, 2, 1), - TOP_FACTOR(CK_TOP_U2U3_REF, "u2u3_ref", CK_TOP_U2U3_SEL, 1, 1), - TOP_FACTOR(CK_TOP_U2U3_SYS, "u2u3_sys", CK_TOP_U2U3_SYS_SEL, 1, 1), - TOP_FACTOR(CK_TOP_U2U3_XHCI, "u2u3_xhci", CK_TOP_U2U3_XHCI_SEL, 1, 1), - TOP_FACTOR(CK_TOP_AP2CNN_HOST, "ap2cnn_host", CK_TOP_AP2CNN_HOST_SEL, 1, - 1), + /* Not defined upstream and not used */ + /* TOP_FACTOR(CLK_TOP_A_TUNER, "a_tuner", CLK_TOP_A_TUNER_SEL, 2, 1), */ + /* MPLL */ + PLL_FACTOR(CLK_TOP_MPLL_D2, "mpll_d2", CLK_APMIXED_MPLL, 1, 2), + PLL_FACTOR(CLK_TOP_MPLL_D4, "mpll_d4", CLK_APMIXED_MPLL, 1, 4), + PLL_FACTOR(CLK_TOP_MPLL_D8, "mpll_d8", CLK_APMIXED_MPLL, 1, 8), + PLL_FACTOR(CLK_TOP_MPLL_D8_D2, "mpll_d8_d2", CLK_APMIXED_MPLL, 1, 16), + PLL_FACTOR(CLK_TOP_MPLL_D3_D2, "mpll_d3_d2", CLK_APMIXED_MPLL, 1, 2), + /* MMPLL */ + PLL_FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", CLK_APMIXED_MMPLL, 1, 2), + PLL_FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", CLK_APMIXED_MMPLL, 1, 4), + PLL_FACTOR(CLK_TOP_MMPLL_D8, "mmpll_d8", CLK_APMIXED_MMPLL, 1, 8), + PLL_FACTOR(CLK_TOP_MMPLL_D8_D2, "mmpll_d8_d2", CLK_APMIXED_MMPLL, 1, 16), + PLL_FACTOR(CLK_TOP_MMPLL_D3_D8, "mmpll_d3_d8", CLK_APMIXED_MMPLL, 1, 8), + PLL_FACTOR(CLK_TOP_MMPLL_U2PHYD, "mmpll_u2phy", CLK_APMIXED_MMPLL, 1, 30), + /* APLL2 */ + PLL_FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", CLK_APMIXED_APLL2, 1, 4), + /* NET1PLL */ + PLL_FACTOR(CLK_TOP_NET1PLL_D4, "net1pll_d4", CLK_APMIXED_NET1PLL, 1, 4), + PLL_FACTOR(CLK_TOP_NET1PLL_D5, "net1pll_d5", CLK_APMIXED_NET1PLL, 1, 5), + PLL_FACTOR(CLK_TOP_NET1PLL_D5_D2, "net1pll_d5_d2", CLK_APMIXED_NET1PLL, 1, 10), + PLL_FACTOR(CLK_TOP_NET1PLL_D5_D4, "net1pll_d5_d4", CLK_APMIXED_NET1PLL, 1, 20), + PLL_FACTOR(CLK_TOP_NET1PLL_D8_D2, "net1pll_d8_d2", CLK_APMIXED_NET1PLL, 1, 16), + PLL_FACTOR(CLK_TOP_NET1PLL_D8_D4, "net1pll_d8_d4", CLK_APMIXED_NET1PLL, 1, 32), + /* NET2PLL */ + PLL_FACTOR(CLK_TOP_NET2PLL_D4, "net2pll_d4", CLK_APMIXED_NET2PLL, 1, 4), + PLL_FACTOR(CLK_TOP_NET2PLL_D4_D2, "net2pll_d4_d2", CLK_APMIXED_NET2PLL, 1, 8), + PLL_FACTOR(CLK_TOP_NET2PLL_D3_D2, "net2pll_d3_d2", CLK_APMIXED_NET2PLL, 1, 2), + /* WEDMCUPLL */ + PLL_FACTOR(CLK_TOP_WEDMCUPLL_D5_D2, "wedmcupll_d5_d2", CLK_APMIXED_WEDMCUPLL, 1, + 10), }; /* TOPCKGEN MUX PARENTS */ -static const int nfi1x_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MM_D8, - CK_TOP_NET1_D8_D2, CK_TOP_NET2_D3_D2, - CK_TOP_CB_M_D4, CK_TOP_MM_D8_D2, - CK_TOP_WEDMCU_D5_D2, CK_TOP_CB_M_D8 }; +static const struct mtk_parent nfi1x_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MMPLL_D8), + TOP_PARENT(CLK_TOP_NET1PLL_D8_D2), TOP_PARENT(CLK_TOP_NET2PLL_D3_D2), + TOP_PARENT(CLK_TOP_MPLL_D4), TOP_PARENT(CLK_TOP_MMPLL_D8_D2), + TOP_PARENT(CLK_TOP_WEDMCUPLL_D5_D2), TOP_PARENT(CLK_TOP_MPLL_D8), +}; -static const int spinfi_parents[] = { - CK_TOP_CB_CKSQ_40M_D2, CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4, - CK_TOP_CB_M_D4, CK_TOP_MM_D8_D2, CK_TOP_WEDMCU_D5_D2, - CK_TOP_MM_D3_D8, CK_TOP_CB_M_D8 +static const struct mtk_parent spinfi_parents[] = { + TOP_PARENT(CLK_TOP_XTAL_D2), TOP_PARENT(CLK_TOP_XTAL), + TOP_PARENT(CLK_TOP_NET1PLL_D5_D4), TOP_PARENT(CLK_TOP_MPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D8_D2), TOP_PARENT(CLK_TOP_WEDMCUPLL_D5_D2), + TOP_PARENT(CLK_TOP_MMPLL_D3_D8), TOP_PARENT(CLK_TOP_MPLL_D8), }; -static const int spi_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2, - CK_TOP_CB_MM_D8, CK_TOP_NET1_D8_D2, - CK_TOP_NET2_D3_D2, CK_TOP_NET1_D5_D4, - CK_TOP_CB_M_D4, CK_TOP_WEDMCU_D5_D2 }; +static const struct mtk_parent spi_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MPLL_D2), + TOP_PARENT(CLK_TOP_MMPLL_D8), TOP_PARENT(CLK_TOP_NET1PLL_D8_D2), + TOP_PARENT(CLK_TOP_NET2PLL_D3_D2), TOP_PARENT(CLK_TOP_NET1PLL_D5_D4), + TOP_PARENT(CLK_TOP_MPLL_D4), TOP_PARENT(CLK_TOP_WEDMCUPLL_D5_D2), +}; -static const int uart_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D8, - CK_TOP_M_D8_D2 }; +static const struct mtk_parent uart_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MPLL_D8), + TOP_PARENT(CLK_TOP_MPLL_D8_D2), +}; -static const int pwm_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D8_D2, - CK_TOP_NET1_D5_D4, CK_TOP_CB_M_D4 }; +static const struct mtk_parent pwm_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D8_D2), + TOP_PARENT(CLK_TOP_NET1PLL_D5_D4), TOP_PARENT(CLK_TOP_MPLL_D4), +}; -static const int i2c_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4, - CK_TOP_CB_M_D4, CK_TOP_NET1_D8_D4 }; +static const struct mtk_parent i2c_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D5_D4), + TOP_PARENT(CLK_TOP_MPLL_D4), TOP_PARENT(CLK_TOP_NET1PLL_D8_D4), +}; -static const int pextp_tl_ck_parents[] = { CK_TOP_CB_CKSQ_40M, - CK_TOP_NET1_D5_D4, CK_TOP_NET2_D4_D2, - CK_TOP_CB_RTC_32K }; +static const struct mtk_parent pextp_tl_ck_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D5_D4), + TOP_PARENT(CLK_TOP_NET2PLL_D4_D2), TOP_PARENT(CLK_TOP_RTC_32K), +}; -static const int emmc_250m_parents[] = { CK_TOP_CB_CKSQ_40M, - CK_TOP_NET1_D5_D2 }; +static const struct mtk_parent emmc_250m_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D5_D2), +}; -static const int emmc_416m_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_416M }; +static const struct mtk_parent emmc_416m_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_MPLL), +}; -static const int f_26m_adc_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_M_D8_D2 }; +static const struct mtk_parent f_26m_adc_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MPLL_D8_D2), +}; -static const int dramc_md32_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2 }; +static const struct mtk_parent dramc_md32_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MPLL_D2), +}; -static const int sysaxi_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D8_D2, - CK_TOP_CB_NET2_D4 }; +static const struct mtk_parent sysaxi_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D8_D2), + TOP_PARENT(CLK_TOP_NET2PLL_D4), +}; -static const int sysapb_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_M_D3_D2, - CK_TOP_NET2_D4_D2 }; +static const struct mtk_parent sysapb_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MPLL_D3_D2), + TOP_PARENT(CLK_TOP_NET2PLL_D4_D2), +}; -static const int arm_db_main_parents[] = { CK_TOP_CB_CKSQ_40M, - CK_TOP_NET2_D3_D2 }; +static const struct mtk_parent arm_db_main_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET2PLL_D3_D2), +}; -static const int arm_db_jtsel_parents[] = { -1, CK_TOP_CB_CKSQ_40M }; +static const struct mtk_parent arm_db_jtsel_parents[] = { + VOID_PARENT, TOP_PARENT(CLK_TOP_XTAL), +}; -static const int netsys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MM_D4 }; +static const struct mtk_parent netsys_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MMPLL_D4), +}; -static const int netsys_500m_parents[] = { CK_TOP_CB_CKSQ_40M, - CK_TOP_CB_NET1_D5 }; +static const struct mtk_parent netsys_500m_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D5), +}; -static const int netsys_mcu_parents[] = { CK_TOP_CB_CKSQ_40M, - CK_TOP_CB_WEDMCU_760M, - CK_TOP_CB_MM_D2, CK_TOP_CB_NET1_D4, - CK_TOP_CB_NET1_D5 }; +static const struct mtk_parent netsys_mcu_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_WEDMCUPLL), + TOP_PARENT(CLK_TOP_MMPLL_D2), TOP_PARENT(CLK_TOP_NET1PLL_D4), + TOP_PARENT(CLK_TOP_NET1PLL_D5), +}; -static const int netsys_2x_parents[] = { CK_TOP_CB_CKSQ_40M, - CK_TOP_CB_NET2_800M, - CK_TOP_CB_WEDMCU_760M, - CK_TOP_CB_MM_D2 }; +static const struct mtk_parent netsys_2x_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_APMIXED_NET2PLL), + APMIXED_PARENT(CLK_APMIXED_WEDMCUPLL), TOP_PARENT(CLK_TOP_MMPLL_D2), +}; -static const int sgm_325m_parents[] = { CK_TOP_CB_CKSQ_40M, - CK_TOP_CB_SGM_325M }; +static const struct mtk_parent sgm_325m_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_SGMPLL), +}; -static const int sgm_reg_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D8_D4 }; +static const struct mtk_parent sgm_reg_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D8_D4), +}; -static const int a1sys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_APLL2_D4 }; +static const struct mtk_parent a1sys_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_APLL2_D4), +}; -static const int conn_mcusys_parents[] = { CK_TOP_CB_CKSQ_40M, - CK_TOP_CB_MM_D2 }; +static const struct mtk_parent conn_mcusys_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MMPLL_D2), +}; -static const int eip_b_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET2_800M }; +static const struct mtk_parent eip_b_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_NET2PLL), +}; -static const int aud_l_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_APLL2_196M, - CK_TOP_M_D8_D2 }; +static const struct mtk_parent aud_l_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_APLL2), + TOP_PARENT(CLK_TOP_MPLL_D8_D2), +}; -static const int a_tuner_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_APLL2_D4, - CK_TOP_M_D8_D2 }; +static const struct mtk_parent a_tuner_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_APLL2_D4), + TOP_PARENT(CLK_TOP_MPLL_D8_D2), +}; -static const int u2u3_sys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4 }; +static const struct mtk_parent u2u3_sys_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D5_D4), +}; -static const int da_u2_refsel_parents[] = { CK_TOP_CB_CKSQ_40M, - CK_TOP_CB_U2_PHYD_CK }; +static const struct mtk_parent da_u2_refsel_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MMPLL_U2PHYD), +}; #define TOP_MUX(_id, _name, _parents, _mux_ofs, _mux_set_ofs, _mux_clr_ofs, \ _shift, _width, _gate, _upd_ofs, _upd) \ @@ -208,199 +231,167 @@ static const int da_u2_refsel_parents[] = { CK_TOP_CB_CKSQ_40M, .mux_clr_reg = _mux_clr_ofs, .upd_reg = _upd_ofs, \ .upd_shift = _upd, .mux_shift = _shift, \ .mux_mask = BIT(_width) - 1, .gate_reg = _mux_ofs, \ - .gate_shift = _gate, .parent = _parents, \ + .gate_shift = _gate, .parent_flags = _parents, \ .num_parents = ARRAY_SIZE(_parents), \ - .flags = CLK_MUX_SETCLR_UPD, \ + .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_MIXED, \ } /* TOPCKGEN MUX_GATE */ static const struct mtk_composite top_muxes[] = { /* CLK_CFG_0 */ - TOP_MUX(CK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, 0x000, 0x004, + TOP_MUX(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, 0x000, 0x004, 0x008, 0, 3, 7, 0x1C0, 0), - TOP_MUX(CK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, 0x000, 0x004, + TOP_MUX(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, 0x000, 0x004, 0x008, 8, 3, 15, 0x1C0, 1), - TOP_MUX(CK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x000, 0x004, 0x008, 16, + TOP_MUX(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x000, 0x004, 0x008, 16, 3, 23, 0x1C0, 2), - TOP_MUX(CK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, 0x000, 0x004, + TOP_MUX(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, 0x000, 0x004, 0x008, 24, 3, 31, 0x1C0, 3), /* CLK_CFG_1 */ - TOP_MUX(CK_TOP_UART_SEL, "uart_sel", uart_parents, 0x010, 0x014, 0x018, + TOP_MUX(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x010, 0x014, 0x018, 0, 2, 7, 0x1C0, 4), - TOP_MUX(CK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x010, 0x014, 0x018, 8, + TOP_MUX(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x010, 0x014, 0x018, 8, 2, 15, 0x1C0, 5), - TOP_MUX(CK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x010, 0x014, 0x018, 16, + TOP_MUX(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x010, 0x014, 0x018, 16, 2, 23, 0x1C0, 6), - TOP_MUX(CK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", pextp_tl_ck_parents, + TOP_MUX(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", pextp_tl_ck_parents, 0x010, 0x014, 0x018, 24, 2, 31, 0x1C0, 7), /* CLK_CFG_2 */ - TOP_MUX(CK_TOP_EMMC_250M_SEL, "emmc_250m_sel", emmc_250m_parents, 0x020, + TOP_MUX(CLK_TOP_EMMC_250M_SEL, "emmc_250m_sel", emmc_250m_parents, 0x020, 0x024, 0x028, 0, 1, 7, 0x1C0, 8), - TOP_MUX(CK_TOP_EMMC_416M_SEL, "emmc_416m_sel", emmc_416m_parents, 0x020, + TOP_MUX(CLK_TOP_EMMC_416M_SEL, "emmc_416m_sel", emmc_416m_parents, 0x020, 0x024, 0x028, 8, 1, 15, 0x1C0, 9), - TOP_MUX(CK_TOP_F_26M_ADC_SEL, "f_26m_adc_sel", f_26m_adc_parents, 0x020, + TOP_MUX(CLK_TOP_F_26M_ADC_SEL, "f_26m_adc_sel", f_26m_adc_parents, 0x020, 0x024, 0x028, 16, 1, 23, 0x1C0, 10), - TOP_MUX(CK_TOP_DRAMC_SEL, "dramc_sel", f_26m_adc_parents, 0x020, 0x024, + TOP_MUX(CLK_TOP_DRAMC_SEL, "dramc_sel", f_26m_adc_parents, 0x020, 0x024, 0x028, 24, 1, 31, 0x1C0, 11), /* CLK_CFG_3 */ - TOP_MUX(CK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", dramc_md32_parents, + TOP_MUX(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", dramc_md32_parents, 0x030, 0x034, 0x038, 0, 1, 7, 0x1C0, 12), - TOP_MUX(CK_TOP_SYSAXI_SEL, "sysaxi_sel", sysaxi_parents, 0x030, 0x034, + TOP_MUX(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", sysaxi_parents, 0x030, 0x034, 0x038, 8, 2, 15, 0x1C0, 13), - TOP_MUX(CK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, 0x030, 0x034, + TOP_MUX(CLK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, 0x030, 0x034, 0x038, 16, 2, 23, 0x1C0, 14), - TOP_MUX(CK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel", arm_db_main_parents, + TOP_MUX(CLK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel", arm_db_main_parents, 0x030, 0x034, 0x038, 24, 1, 31, 0x1C0, 15), /* CLK_CFG_4 */ - TOP_MUX(CK_TOP_ARM_DB_JTSEL, "arm_db_jtsel", arm_db_jtsel_parents, + TOP_MUX(CLK_TOP_ARM_DB_JTSEL, "arm_db_jtsel", arm_db_jtsel_parents, 0x040, 0x044, 0x048, 0, 1, 7, 0x1C0, 16), - TOP_MUX(CK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 0x040, 0x044, + TOP_MUX(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 0x040, 0x044, 0x048, 8, 1, 15, 0x1C0, 17), - TOP_MUX(CK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", netsys_500m_parents, + TOP_MUX(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", netsys_500m_parents, 0x040, 0x044, 0x048, 16, 1, 23, 0x1C0, 18), - TOP_MUX(CK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", netsys_mcu_parents, + TOP_MUX(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", netsys_mcu_parents, 0x040, 0x044, 0x048, 24, 3, 31, 0x1C0, 19), /* CLK_CFG_5 */ - TOP_MUX(CK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, 0x050, + TOP_MUX(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, 0x050, 0x054, 0x058, 0, 2, 7, 0x1C0, 20), - TOP_MUX(CK_TOP_SGM_325M_SEL, "sgm_325m_sel", sgm_325m_parents, 0x050, + TOP_MUX(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel", sgm_325m_parents, 0x050, 0x054, 0x058, 8, 1, 15, 0x1C0, 21), - TOP_MUX(CK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents, 0x050, + TOP_MUX(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents, 0x050, 0x054, 0x058, 16, 1, 23, 0x1C0, 22), - TOP_MUX(CK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 0x050, 0x054, + TOP_MUX(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 0x050, 0x054, 0x058, 24, 1, 31, 0x1C0, 23), /* CLK_CFG_6 */ - TOP_MUX(CK_TOP_CONN_MCUSYS_SEL, "conn_mcusys_sel", conn_mcusys_parents, + TOP_MUX(CLK_TOP_CONN_MCUSYS_SEL, "conn_mcusys_sel", conn_mcusys_parents, 0x060, 0x064, 0x068, 0, 1, 7, 0x1C0, 24), - TOP_MUX(CK_TOP_EIP_B_SEL, "eip_b_sel", eip_b_parents, 0x060, 0x064, + TOP_MUX(CLK_TOP_EIP_B_SEL, "eip_b_sel", eip_b_parents, 0x060, 0x064, 0x068, 8, 1, 15, 0x1C0, 25), - TOP_MUX(CK_TOP_PCIE_PHY_SEL, "pcie_phy_sel", f_26m_adc_parents, 0x060, + TOP_MUX(CLK_TOP_PCIE_PHY_SEL, "pcie_phy_sel", f_26m_adc_parents, 0x060, 0x064, 0x068, 16, 1, 23, 0x1C0, 26), - TOP_MUX(CK_TOP_USB3_PHY_SEL, "usb3_phy_sel", f_26m_adc_parents, 0x060, + TOP_MUX(CLK_TOP_USB3_PHY_SEL, "usb3_phy_sel", f_26m_adc_parents, 0x060, 0x064, 0x068, 24, 1, 31, 0x1C0, 27), /* CLK_CFG_7 */ - TOP_MUX(CK_TOP_F26M_SEL, "csw_f26m_sel", f_26m_adc_parents, 0x070, + TOP_MUX(CLK_TOP_F26M_SEL, "csw_f26m_sel", f_26m_adc_parents, 0x070, 0x074, 0x078, 0, 1, 7, 0x1C0, 28), - TOP_MUX(CK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 0x070, 0x074, + TOP_MUX(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 0x070, 0x074, 0x078, 8, 2, 15, 0x1C0, 29), - TOP_MUX(CK_TOP_A_TUNER_SEL, "a_tuner_sel", a_tuner_parents, 0x070, + TOP_MUX(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", a_tuner_parents, 0x070, 0x074, 0x078, 16, 2, 23, 0x1C0, 30), - TOP_MUX(CK_TOP_U2U3_SEL, "u2u3_sel", f_26m_adc_parents, 0x070, 0x074, + TOP_MUX(CLK_TOP_U2U3_SEL, "u2u3_sel", f_26m_adc_parents, 0x070, 0x074, 0x078, 24, 1, 31, 0x1C4, 0), /* CLK_CFG_8 */ - TOP_MUX(CK_TOP_U2U3_SYS_SEL, "u2u3_sys_sel", u2u3_sys_parents, 0x080, + TOP_MUX(CLK_TOP_U2U3_SYS_SEL, "u2u3_sys_sel", u2u3_sys_parents, 0x080, 0x084, 0x088, 0, 1, 7, 0x1C4, 1), - TOP_MUX(CK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel", u2u3_sys_parents, 0x080, + TOP_MUX(CLK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel", u2u3_sys_parents, 0x080, 0x084, 0x088, 8, 1, 15, 0x1C4, 2), - TOP_MUX(CK_TOP_DA_U2_REFSEL, "da_u2_refsel", da_u2_refsel_parents, + TOP_MUX(CLK_TOP_DA_U2_REFSEL, "da_u2_refsel", da_u2_refsel_parents, 0x080, 0x084, 0x088, 16, 1, 23, 0x1C4, 3), - TOP_MUX(CK_TOP_DA_U2_CK_1P_SEL, "da_u2_ck_1p_sel", da_u2_refsel_parents, + TOP_MUX(CLK_TOP_DA_U2_CK_1P_SEL, "da_u2_ck_1p_sel", da_u2_refsel_parents, 0x080, 0x084, 0x088, 24, 1, 31, 0x1C4, 4), /* CLK_CFG_9 */ - TOP_MUX(CK_TOP_AP2CNN_HOST_SEL, "ap2cnn_host_sel", sgm_reg_parents, + TOP_MUX(CLK_TOP_AP2CNN_HOST_SEL, "ap2cnn_host_sel", sgm_reg_parents, 0x090, 0x094, 0x098, 0, 1, 7, 0x1C4, 5), }; /* INFRA FIXED DIV */ static const struct mtk_fixed_factor infra_fixed_divs[] = { - TOP_FACTOR(CK_INFRA_CK_F26M, "infra_ck_f26m", CK_TOP_F26M_SEL, 1, 1), - TOP_FACTOR(CK_INFRA_UART, "infra_uart", CK_TOP_UART_SEL, 1, 1), - TOP_FACTOR(CK_INFRA_ISPI0, "infra_ispi0", CK_TOP_SPI_SEL, 1, 1), - TOP_FACTOR(CK_INFRA_I2C, "infra_i2c", CK_TOP_I2C_SEL, 1, 1), - TOP_FACTOR(CK_INFRA_ISPI1, "infra_ispi1", CK_TOP_SPINFI_SEL, 1, 1), - TOP_FACTOR(CK_INFRA_PWM, "infra_pwm", CK_TOP_PWM_SEL, 1, 1), - TOP_FACTOR(CK_INFRA_66M_MCK, "infra_66m_mck", CK_TOP_SYSAXI_SEL, 1, 2), - TOP_FACTOR(CK_INFRA_CK_F32K, "infra_ck_f32k", CK_TOP_CB_RTC_32P7K, 1, - 1), - TOP_FACTOR(CK_INFRA_PCIE_CK, "infra_pcie", CK_TOP_PEXTP_TL_SEL, 1, 1), - INFRA_FACTOR(CK_INFRA_PWM_BCK, "infra_pwm_bck", CK_INFRA_PWM_BSEL, 1, - 1), - INFRA_FACTOR(CK_INFRA_PWM_CK1, "infra_pwm_ck1", CK_INFRA_PWM1_SEL, 1, - 1), - INFRA_FACTOR(CK_INFRA_PWM_CK2, "infra_pwm_ck2", CK_INFRA_PWM2_SEL, 1, - 1), - TOP_FACTOR(CK_INFRA_133M_HCK, "infra_133m_hck", CK_TOP_SYSAXI, 1, 1), - TOP_FACTOR(CK_INFRA_EIP_CK, "infra_eip", CK_TOP_EIP_B, 1, 1), - INFRA_FACTOR(CK_INFRA_66M_PHCK, "infra_66m_phck", CK_INFRA_133M_HCK, 1, - 1), - TOP_FACTOR(CK_INFRA_FAUD_L_CK, "infra_faud_l", CK_TOP_AUD_L, 1, 1), - TOP_FACTOR(CK_INFRA_FAUD_AUD_CK, "infra_faud_aud", CK_TOP_A1SYS, 1, 1), - TOP_FACTOR(CK_INFRA_FAUD_EG2_CK, "infra_faud_eg2", CK_TOP_A_TUNER, 1, - 1), - TOP_FACTOR(CK_INFRA_I2CS_CK, "infra_i2cs", CK_TOP_I2C_BCK, 1, 1), - INFRA_FACTOR(CK_INFRA_MUX_UART0, "infra_mux_uart0", CK_INFRA_UART0_SEL, - 1, 1), - INFRA_FACTOR(CK_INFRA_MUX_UART1, "infra_mux_uart1", CK_INFRA_UART1_SEL, - 1, 1), - INFRA_FACTOR(CK_INFRA_MUX_UART2, "infra_mux_uart2", CK_INFRA_UART2_SEL, - 1, 1), - TOP_FACTOR(CK_INFRA_NFI_CK, "infra_nfi", CK_TOP_NFI1X, 1, 1), - TOP_FACTOR(CK_INFRA_SPINFI_CK, "infra_spinfi", CK_TOP_SPINFI_BCK, 1, 1), - INFRA_FACTOR(CK_INFRA_MUX_SPI0, "infra_mux_spi0", CK_INFRA_SPI0_SEL, 1, - 1), - INFRA_FACTOR(CK_INFRA_MUX_SPI1, "infra_mux_spi1", CK_INFRA_SPI1_SEL, 1, - 1), - TOP_FACTOR(CK_INFRA_RTC_32K, "infra_rtc_32k", CK_TOP_CB_RTC_32K, 1, 1), - TOP_FACTOR(CK_INFRA_FMSDC_CK, "infra_fmsdc", CK_TOP_EMMC_416M, 1, 1), - TOP_FACTOR(CK_INFRA_FMSDC_HCK_CK, "infra_fmsdc_hck", CK_TOP_EMMC_250M, - 1, 1), - TOP_FACTOR(CK_INFRA_PERI_133M, "infra_peri_133m", CK_TOP_SYSAXI, 1, 1), - TOP_FACTOR(CK_INFRA_133M_PHCK, "infra_133m_phck", CK_TOP_SYSAXI, 1, 1), - TOP_FACTOR(CK_INFRA_USB_SYS_CK, "infra_usb_sys", CK_TOP_U2U3_SYS, 1, 1), - TOP_FACTOR(CK_INFRA_USB_CK, "infra_usb", CK_TOP_U2U3_REF, 1, 1), - TOP_FACTOR(CK_INFRA_USB_XHCI_CK, "infra_usb_xhci", CK_TOP_U2U3_XHCI, 1, - 1), - TOP_FACTOR(CK_INFRA_PCIE_GFMUX_TL_O_PRE, "infra_pcie_mux", - CK_TOP_PEXTP_TL, 1, 1), - TOP_FACTOR(CK_INFRA_F26M_CK0, "infra_f26m_ck0", CK_TOP_F26M, 1, 1), - TOP_FACTOR(CK_INFRA_HD_133M, "infra_hd_133m", CK_TOP_SYSAXI, 1, 1), + TOP_FACTOR(CLK_INFRA_SYSAXI_D2, "infra_sysaxi_d2", CLK_TOP_SYSAXI_SEL, 1, 2), }; /* INFRASYS MUX PARENTS */ -static const int infra_uart0_parents[] = { CK_INFRA_CK_F26M, CK_INFRA_UART }; -static const int infra_spi0_parents[] = { CK_INFRA_I2C, CK_INFRA_ISPI0 }; -static const int infra_spi1_parents[] = { CK_INFRA_I2C, CK_INFRA_ISPI1 }; +static const struct mtk_parent infra_uart0_parents[] = { + TOP_PARENT(CLK_TOP_F26M_SEL), + TOP_PARENT(CLK_TOP_UART_SEL) +}; + +static const struct mtk_parent infra_spi0_parents[] = { + TOP_PARENT(CLK_TOP_I2C_SEL), + TOP_PARENT(CLK_TOP_SPI_SEL) +}; + +static const struct mtk_parent infra_spi1_parents[] = { + TOP_PARENT(CLK_TOP_I2C_SEL), + TOP_PARENT(CLK_TOP_SPINFI_SEL) +}; -static const int infra_pwm_bsel_parents[] = { CK_INFRA_CK_F32K, - CK_INFRA_CK_F26M, - CK_INFRA_66M_MCK, CK_INFRA_PWM }; +static const struct mtk_parent infra_pwm_bsel_parents[] = { + TOP_PARENT(CLK_TOP_RTC_32P7K), + TOP_PARENT(CLK_TOP_F26M_SEL), + INFRA_PARENT(CLK_INFRA_SYSAXI_D2), + TOP_PARENT(CLK_TOP_PWM_SEL) +}; -static const int infra_pcie_parents[] = { CK_INFRA_CK_F32K, CK_INFRA_CK_F26M, - -1, CK_INFRA_PCIE_CK }; +static const struct mtk_parent infra_pcie_parents[] = { + TOP_PARENT(CLK_TOP_RTC_32P7K), + TOP_PARENT(CLK_TOP_F26M_SEL), + TOP_PARENT(CLK_TOP_XTAL), + TOP_PARENT(CLK_TOP_PEXTP_TL_SEL) +}; #define INFRA_MUX(_id, _name, _parents, _reg, _shift, _width) \ { \ .id = _id, .mux_reg = (_reg) + 0x8, \ .mux_set_reg = (_reg) + 0x0, .mux_clr_reg = (_reg) + 0x4, \ .mux_shift = _shift, .mux_mask = BIT(_width) - 1, \ - .parent = _parents, .num_parents = ARRAY_SIZE(_parents), \ - .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_INFRASYS, \ + .parent_flags = _parents, .num_parents = ARRAY_SIZE(_parents), \ + .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_MIXED, \ } /* INFRA MUX */ static const struct mtk_composite infra_muxes[] = { /* MODULE_CLK_SEL_0 */ - INFRA_MUX(CK_INFRA_UART0_SEL, "infra_uart0_sel", infra_uart0_parents, + INFRA_MUX(CLK_INFRA_UART0_SEL, "infra_uart0_sel", infra_uart0_parents, 0x10, 0, 1), - INFRA_MUX(CK_INFRA_UART1_SEL, "infra_uart1_sel", infra_uart0_parents, + INFRA_MUX(CLK_INFRA_UART1_SEL, "infra_uart1_sel", infra_uart0_parents, 0x10, 1, 1), - INFRA_MUX(CK_INFRA_UART2_SEL, "infra_uart2_sel", infra_uart0_parents, + INFRA_MUX(CLK_INFRA_UART2_SEL, "infra_uart2_sel", infra_uart0_parents, 0x10, 2, 1), - INFRA_MUX(CK_INFRA_SPI0_SEL, "infra_spi0_sel", infra_spi0_parents, 0x10, + INFRA_MUX(CLK_INFRA_SPI0_SEL, "infra_spi0_sel", infra_spi0_parents, 0x10, 4, 1), - INFRA_MUX(CK_INFRA_SPI1_SEL, "infra_spi1_sel", infra_spi1_parents, 0x10, + INFRA_MUX(CLK_INFRA_SPI1_SEL, "infra_spi1_sel", infra_spi1_parents, 0x10, 5, 1), - INFRA_MUX(CK_INFRA_PWM1_SEL, "infra_pwm1_sel", infra_pwm_bsel_parents, + INFRA_MUX(CLK_INFRA_PWM1_SEL, "infra_pwm1_sel", infra_pwm_bsel_parents, 0x10, 9, 2), - INFRA_MUX(CK_INFRA_PWM2_SEL, "infra_pwm2_sel", infra_pwm_bsel_parents, + INFRA_MUX(CLK_INFRA_PWM2_SEL, "infra_pwm2_sel", infra_pwm_bsel_parents, 0x10, 11, 2), - INFRA_MUX(CK_INFRA_PWM_BSEL, "infra_pwm_bsel", infra_pwm_bsel_parents, + INFRA_MUX(CLK_INFRA_PWM_BSEL, "infra_pwm_bsel", infra_pwm_bsel_parents, 0x10, 13, 2), /* MODULE_CLK_SEL_1 */ - INFRA_MUX(CK_INFRA_PCIE_SEL, "infra_pcie_sel", infra_pcie_parents, 0x20, + INFRA_MUX(CLK_INFRA_PCIE_SEL, "infra_pcie_sel", infra_pcie_parents, 0x20, 0, 2), }; @@ -422,113 +413,131 @@ static const struct mtk_gate_regs infra_2_cg_regs = { .sta_ofs = 0x68, }; -#define GATE_INFRA0(_id, _name, _parent, _shift) \ +#define GATE_INFRA0(_id, _name, _parent, _shift, _flags) \ { \ .id = _id, .parent = _parent, .regs = &infra_0_cg_regs, \ .shift = _shift, \ - .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \ + .flags = _flags, \ } +#define GATE_INFRA0_INFRA(_id, _name, _parent, _shift) \ + GATE_INFRA0(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS) +#define GATE_INFRA0_TOP(_id, _name, _parent, _shift) \ + GATE_INFRA0(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) -#define GATE_INFRA1(_id, _name, _parent, _shift) \ +#define GATE_INFRA1(_id, _name, _parent, _shift, _flags) \ { \ .id = _id, .parent = _parent, .regs = &infra_1_cg_regs, \ .shift = _shift, \ - .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \ + .flags = _flags, \ } +#define GATE_INFRA1_INFRA(_id, _name, _parent, _shift) \ + GATE_INFRA1(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS) +#define GATE_INFRA1_TOP(_id, _name, _parent, _shift) \ + GATE_INFRA1(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) -#define GATE_INFRA2(_id, _name, _parent, _shift) \ +#define GATE_INFRA2(_id, _name, _parent, _shift, _flags) \ { \ .id = _id, .parent = _parent, .regs = &infra_2_cg_regs, \ .shift = _shift, \ - .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \ + .flags = _flags, \ } +#define GATE_INFRA2_INFRA(_id, _name, _parent, _shift) \ + GATE_INFRA2(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS) +#define GATE_INFRA2_TOP(_id, _name, _parent, _shift) \ + GATE_INFRA2(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) /* INFRA GATE */ -static const struct mtk_gate infracfg_ao_gates[] = { +static const struct mtk_gate infracfg_gates[] = { /* INFRA0 */ - GATE_INFRA0(CK_INFRA_GPT_STA, "infra_gpt_sta", CK_INFRA_66M_MCK, 0), - GATE_INFRA0(CK_INFRA_PWM_HCK, "infra_pwm_hck", CK_INFRA_66M_MCK, 1), - GATE_INFRA0(CK_INFRA_PWM_STA, "infra_pwm_sta", CK_INFRA_PWM_BCK, 2), - GATE_INFRA0(CK_INFRA_PWM1_CK, "infra_pwm1", CK_INFRA_PWM_CK1, 3), - GATE_INFRA0(CK_INFRA_PWM2_CK, "infra_pwm2", CK_INFRA_PWM_CK2, 4), - GATE_INFRA0(CK_INFRA_CQ_DMA_CK, "infra_cq_dma", CK_INFRA_133M_HCK, 6), - GATE_INFRA0(CK_INFRA_EIP97_CK, "infra_eip97", CK_INFRA_EIP_CK, 7), - GATE_INFRA0(CK_INFRA_AUD_BUS_CK, "infra_aud_bus", CK_INFRA_66M_PHCK, 8), - GATE_INFRA0(CK_INFRA_AUD_26M_CK, "infra_aud_26m", CK_INFRA_CK_F26M, 9), - GATE_INFRA0(CK_INFRA_AUD_L_CK, "infra_aud_l", CK_INFRA_FAUD_L_CK, 10), - GATE_INFRA0(CK_INFRA_AUD_AUD_CK, "infra_aud_aud", CK_INFRA_FAUD_AUD_CK, - 11), - GATE_INFRA0(CK_INFRA_AUD_EG2_CK, "infra_aud_eg2", CK_INFRA_FAUD_EG2_CK, - 13), - GATE_INFRA0(CK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", CK_INFRA_CK_F26M, - 14), - GATE_INFRA0(CK_INFRA_DBG_CK, "infra_dbg", CK_INFRA_66M_MCK, 15), - GATE_INFRA0(CK_INFRA_AP_DMA_CK, "infra_ap_dma", CK_INFRA_66M_MCK, 16), - GATE_INFRA0(CK_INFRA_SEJ_CK, "infra_sej", CK_INFRA_66M_MCK, 24), - GATE_INFRA0(CK_INFRA_SEJ_13M_CK, "infra_sej_13m", CK_INFRA_CK_F26M, 25), - GATE_INFRA0(CK_INFRA_TRNG_CK, "infra_trng", CK_INFRA_HD_133M, 26), + GATE_INFRA0_INFRA(CLK_INFRA_GPT_STA, "infra_gpt_sta", CLK_INFRA_SYSAXI_D2, 0), + GATE_INFRA0_INFRA(CLK_INFRA_PWM_HCK, "infra_pwm_hck", CLK_INFRA_SYSAXI_D2, 1), + GATE_INFRA0_INFRA(CLK_INFRA_PWM_STA, "infra_pwm_sta", CLK_INFRA_PWM_BSEL, 2), + GATE_INFRA0_INFRA(CLK_INFRA_PWM1_CK, "infra_pwm1", CLK_INFRA_PWM1_SEL, 3), + GATE_INFRA0_INFRA(CLK_INFRA_PWM2_CK, "infra_pwm2", CLK_INFRA_PWM2_SEL, 4), + GATE_INFRA0_TOP(CLK_INFRA_CQ_DMA_CK, "infra_cq_dma", CLK_TOP_SYSAXI_SEL, 6), + GATE_INFRA0_TOP(CLK_INFRA_EIP97_CK, "infra_eip97", CLK_TOP_EIP_B_SEL, 7), + GATE_INFRA0_TOP(CLK_INFRA_AUD_BUS_CK, "infra_aud_bus", CLK_TOP_SYSAXI_SEL, 8), + GATE_INFRA0_TOP(CLK_INFRA_AUD_26M_CK, "infra_aud_26m", CLK_TOP_F26M_SEL, 9), + GATE_INFRA0_TOP(CLK_INFRA_AUD_L_CK, "infra_aud_l", CLK_TOP_AUD_L_SEL, 10), + GATE_INFRA0_TOP(CLK_INFRA_AUD_AUD_CK, "infra_aud_aud", CLK_TOP_A1SYS_SEL, + 11), + GATE_INFRA0_TOP(CLK_INFRA_AUD_EG2_CK, "infra_aud_eg2", CLK_TOP_A_TUNER_SEL, + 13), + GATE_INFRA0_TOP(CLK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", CLK_TOP_F26M_SEL, + 14), + GATE_INFRA0_INFRA(CLK_INFRA_DBG_CK, "infra_dbg", CLK_INFRA_SYSAXI_D2, 15), + GATE_INFRA0_INFRA(CLK_INFRA_AP_DMA_CK, "infra_ap_dma", CLK_INFRA_SYSAXI_D2, 16), + GATE_INFRA0_INFRA(CLK_INFRA_SEJ_CK, "infra_sej", CLK_INFRA_SYSAXI_D2, 24), + GATE_INFRA0_TOP(CLK_INFRA_SEJ_13M_CK, "infra_sej_13m", CLK_TOP_F26M_SEL, 25), /* INFRA1 */ - GATE_INFRA1(CK_INFRA_THERM_CK, "infra_therm", CK_INFRA_CK_F26M, 0), - GATE_INFRA1(CK_INFRA_I2CO_CK, "infra_i2co", CK_INFRA_I2CS_CK, 1), - GATE_INFRA1(CK_INFRA_UART0_CK, "infra_uart0", CK_INFRA_MUX_UART0, 2), - GATE_INFRA1(CK_INFRA_UART1_CK, "infra_uart1", CK_INFRA_MUX_UART1, 3), - GATE_INFRA1(CK_INFRA_UART2_CK, "infra_uart2", CK_INFRA_MUX_UART2, 4), - GATE_INFRA1(CK_INFRA_NFI1_CK, "infra_nfi1", CK_INFRA_NFI_CK, 8), - GATE_INFRA1(CK_INFRA_SPINFI1_CK, "infra_spinfi1", CK_INFRA_SPINFI_CK, - 9), - GATE_INFRA1(CK_INFRA_NFI_HCK_CK, "infra_nfi_hck", CK_INFRA_66M_MCK, 10), - GATE_INFRA1(CK_INFRA_SPI0_CK, "infra_spi0", CK_INFRA_MUX_SPI0, 11), - GATE_INFRA1(CK_INFRA_SPI1_CK, "infra_spi1", CK_INFRA_MUX_SPI1, 12), - GATE_INFRA1(CK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", CK_INFRA_66M_MCK, - 13), - GATE_INFRA1(CK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", CK_INFRA_66M_MCK, - 14), - GATE_INFRA1(CK_INFRA_FRTC_CK, "infra_frtc", CK_INFRA_RTC_32K, 15), - GATE_INFRA1(CK_INFRA_MSDC_CK, "infra_msdc", CK_INFRA_FMSDC_CK, 16), - GATE_INFRA1(CK_INFRA_MSDC_HCK_CK, "infra_msdc_hck", - CK_INFRA_FMSDC_HCK_CK, 17), - GATE_INFRA1(CK_INFRA_MSDC_133M_CK, "infra_msdc_133m", - CK_INFRA_PERI_133M, 18), - GATE_INFRA1(CK_INFRA_MSDC_66M_CK, "infra_msdc_66m", CK_INFRA_66M_PHCK, - 19), - GATE_INFRA1(CK_INFRA_ADC_26M_CK, "infra_adc_26m", CK_INFRA_CK_F26M, 20), - GATE_INFRA1(CK_INFRA_ADC_FRC_CK, "infra_adc_frc", CK_INFRA_CK_F26M, 21), - GATE_INFRA1(CK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", CK_INFRA_NFI_CK, - 23), + GATE_INFRA1_TOP(CLK_INFRA_THERM_CK, "infra_therm", CLK_TOP_F26M_SEL, 0), + GATE_INFRA1_TOP(CLK_INFRA_I2C0_CK, "infra_i2co", CLK_TOP_I2C_SEL, 1), + GATE_INFRA1_INFRA(CLK_INFRA_UART0_CK, "infra_uart0", CLK_INFRA_UART0_SEL, 2), + GATE_INFRA1_INFRA(CLK_INFRA_UART1_CK, "infra_uart1", CLK_INFRA_UART1_SEL, 3), + GATE_INFRA1_INFRA(CLK_INFRA_UART2_CK, "infra_uart2", CLK_INFRA_UART2_SEL, 4), + GATE_INFRA1_TOP(CLK_INFRA_NFI1_CK, "infra_nfi1", CLK_TOP_NFI1X_SEL, 8), + GATE_INFRA1_TOP(CLK_INFRA_SPINFI1_CK, "infra_spinfi1", CLK_TOP_SPINFI_SEL, + 9), + GATE_INFRA1_INFRA(CLK_INFRA_NFI_HCK_CK, "infra_nfi_hck", CLK_INFRA_SYSAXI_D2, 10), + GATE_INFRA1_INFRA(CLK_INFRA_SPI0_CK, "infra_spi0", CLK_INFRA_SPI0_SEL, 11), + GATE_INFRA1_INFRA(CLK_INFRA_SPI1_CK, "infra_spi1", CLK_INFRA_SPI1_SEL, 12), + GATE_INFRA1_INFRA(CLK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", CLK_INFRA_SYSAXI_D2, + 13), + GATE_INFRA1_INFRA(CLK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", CLK_INFRA_SYSAXI_D2, + 14), + GATE_INFRA1_TOP(CLK_INFRA_FRTC_CK, "infra_frtc", CLK_TOP_RTC_32K, 15), + GATE_INFRA1_TOP(CLK_INFRA_MSDC_CK, "infra_msdc", CLK_TOP_EMMC_416M_SEL, 16), + GATE_INFRA1_TOP(CLK_INFRA_MSDC_HCK_CK, "infra_msdc_hck", + CLK_TOP_EMMC_250M_SEL, 17), + GATE_INFRA1_TOP(CLK_INFRA_MSDC_133M_CK, "infra_msdc_133m", + CLK_TOP_SYSAXI_SEL, 18), + GATE_INFRA1_INFRA(CLK_INFRA_MSDC_66M_CK, "infra_msdc_66m", CLK_INFRA_SYSAXI_D2, + 19), + GATE_INFRA1_INFRA(CLK_INFRA_ADC_26M_CK, "infra_adc_26m", CLK_INFRA_ADC_FRC_CK, 20), + GATE_INFRA1_TOP(CLK_INFRA_ADC_FRC_CK, "infra_adc_frc", CLK_TOP_F26M_SEL, 21), + GATE_INFRA1_TOP(CLK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", CLK_TOP_NFI1X_SEL, + 23), /* INFRA2 */ - GATE_INFRA2(CK_INFRA_IUSB_133_CK, "infra_iusb_133", CK_INFRA_133M_PHCK, - 0), - GATE_INFRA2(CK_INFRA_IUSB_66M_CK, "infra_iusb_66m", CK_INFRA_66M_PHCK, - 1), - GATE_INFRA2(CK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", CK_INFRA_USB_SYS_CK, - 2), - GATE_INFRA2(CK_INFRA_IUSB_CK, "infra_iusb", CK_INFRA_USB_CK, 3), - GATE_INFRA2(CK_INFRA_IPCIE_CK, "infra_ipcie", CK_INFRA_PCIE_CK, 13), - GATE_INFRA2(CK_INFRA_IPCIER_CK, "infra_ipcier", CK_INFRA_F26M_CK0, 15), - GATE_INFRA2(CK_INFRA_IPCIEB_CK, "infra_ipcieb", CK_INFRA_133M_PHCK, 15), + GATE_INFRA2_TOP(CLK_INFRA_IUSB_133_CK, "infra_iusb_133", CLK_TOP_SYSAXI_SEL, + 0), + GATE_INFRA2_INFRA(CLK_INFRA_IUSB_66M_CK, "infra_iusb_66m", CLK_INFRA_SYSAXI_D2, + 1), + GATE_INFRA2_TOP(CLK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", CLK_TOP_U2U3_SYS_SEL, + 2), + GATE_INFRA2_TOP(CLK_INFRA_IUSB_CK, "infra_iusb", CLK_TOP_U2U3_SEL, 3), + GATE_INFRA2_TOP(CLK_INFRA_IPCIE_CK, "infra_ipcie", CLK_TOP_PEXTP_TL_SEL, 12), + GATE_INFRA2_TOP(CLK_INFRA_IPCIE_PIPE_CK, "infra_ipcie_pipe", CLK_TOP_XTAL, 13), + GATE_INFRA2_TOP(CLK_INFRA_IPCIER_CK, "infra_ipcier", CLK_TOP_F26M_SEL, 14), + GATE_INFRA2_TOP(CLK_INFRA_IPCIEB_CK, "infra_ipcieb", CLK_TOP_SYSAXI_SEL, 15), + /* upstream linux unordered */ + GATE_INFRA0_TOP(CLK_INFRA_TRNG_CK, "infra_trng", CLK_TOP_SYSAXI_SEL, 26), }; static const struct mtk_clk_tree mt7986_fixed_pll_clk_tree = { .fdivs_offs = CLK_APMIXED_NR_CLK, .xtal_rate = 40 * MHZ, .fclks = fixed_pll_clks, + .flags = CLK_APMIXED, }; static const struct mtk_clk_tree mt7986_topckgen_clk_tree = { - .fdivs_offs = CK_TOP_CB_M_416M, - .muxes_offs = CK_TOP_NFI1X_SEL, + .fdivs_offs = CLK_TOP_XTAL_D2, + .muxes_offs = CLK_TOP_NFI1X_SEL, .fclks = top_fixed_clks, .fdivs = top_fixed_divs, .muxes = top_muxes, - .flags = CLK_BYPASS_XTAL, + .flags = CLK_BYPASS_XTAL | CLK_TOPCKGEN, }; static const struct mtk_clk_tree mt7986_infracfg_clk_tree = { - .fdivs_offs = CK_INFRA_CK_F26M, - .muxes_offs = CK_INFRA_UART0_SEL, + .fdivs_offs = CLK_INFRA_SYSAXI_D2, + .muxes_offs = CLK_INFRA_UART0_SEL, + .gates_offs = CLK_INFRA_GPT_STA, .fdivs = infra_fixed_divs, .muxes = infra_muxes, + .gates = infracfg_gates, + .flags = CLK_INFRASYS, }; static const struct udevice_id mt7986_fixed_pll_compat[] = { @@ -582,20 +591,9 @@ static const struct udevice_id mt7986_infracfg_compat[] = { {} }; -static const struct udevice_id mt7986_infracfg_ao_compat[] = { - { .compatible = "mediatek,mt7986-infracfg_ao" }, - {} -}; - static int mt7986_infracfg_probe(struct udevice *dev) { - return mtk_common_clk_init(dev, &mt7986_infracfg_clk_tree); -} - -static int mt7986_infracfg_ao_probe(struct udevice *dev) -{ - return mtk_common_clk_gate_init(dev, &mt7986_infracfg_clk_tree, - infracfg_ao_gates); + return mtk_common_clk_infrasys_init(dev, &mt7986_infracfg_clk_tree); } U_BOOT_DRIVER(mtk_clk_infracfg) = { @@ -608,16 +606,6 @@ U_BOOT_DRIVER(mtk_clk_infracfg) = { .flags = DM_FLAG_PRE_RELOC, }; -U_BOOT_DRIVER(mtk_clk_infracfg_ao) = { - .name = "mt7986-clock-infracfg-ao", - .id = UCLASS_CLK, - .of_match = mt7986_infracfg_ao_compat, - .probe = mt7986_infracfg_ao_probe, - .priv_auto = sizeof(struct mtk_cg_priv), - .ops = &mtk_clk_gate_ops, - .flags = DM_FLAG_PRE_RELOC, -}; - /* ethsys */ static const struct mtk_gate_regs eth_cg_regs = { .sta_ofs = 0x30, @@ -631,11 +619,11 @@ static const struct mtk_gate_regs eth_cg_regs = { } static const struct mtk_gate eth_cgs[] = { - GATE_ETH(CK_ETH_FE_EN, "eth_fe_en", CK_TOP_NETSYS_2X, 7), - GATE_ETH(CK_ETH_GP2_EN, "eth_gp2_en", CK_TOP_SGM_325M, 8), - GATE_ETH(CK_ETH_GP1_EN, "eth_gp1_en", CK_TOP_SGM_325M, 8), - GATE_ETH(CK_ETH_WOCPU1_EN, "eth_wocpu1_en", CK_TOP_NETSYS_WED_MCU, 14), - GATE_ETH(CK_ETH_WOCPU0_EN, "eth_wocpu0_en", CK_TOP_NETSYS_WED_MCU, 15), + GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", CLK_TOP_NETSYS_2X_SEL, 7), + GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", CLK_TOP_SGM_325M_SEL, 8), + GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", CLK_TOP_SGM_325M_SEL, 8), + GATE_ETH(CLK_ETH_WOCPU1_EN, "eth_wocpu1_en", CLK_TOP_NETSYS_MCU_SEL, 14), + GATE_ETH(CLK_ETH_WOCPU0_EN, "eth_wocpu0_en", CLK_TOP_NETSYS_MCU_SEL, 15), }; static int mt7986_ethsys_probe(struct udevice *dev) diff --git a/drivers/clk/mediatek/clk-mt7988.c b/drivers/clk/mediatek/clk-mt7988.c index 32b04511781..8f4e8f4e8c9 100644 --- a/drivers/clk/mediatek/clk-mt7988.c +++ b/drivers/clk/mediatek/clk-mt7988.c @@ -35,225 +35,243 @@ /* FIXED PLLS */ static const struct mtk_fixed_clk apmixedsys_mtk_plls[] = { - FIXED_CLK(CK_APMIXED_NETSYSPLL, CLK_XTAL, 850000000), - FIXED_CLK(CK_APMIXED_MPLL, CLK_XTAL, 416000000), - FIXED_CLK(CK_APMIXED_MMPLL, CLK_XTAL, 720000000), - FIXED_CLK(CK_APMIXED_APLL2, CLK_XTAL, 196608000), - FIXED_CLK(CK_APMIXED_NET1PLL, CLK_XTAL, 2500000000), - FIXED_CLK(CK_APMIXED_NET2PLL, CLK_XTAL, 800000000), - FIXED_CLK(CK_APMIXED_WEDMCUPLL, CLK_XTAL, 208000000), - FIXED_CLK(CK_APMIXED_SGMPLL, CLK_XTAL, 325000000), - FIXED_CLK(CK_APMIXED_ARM_B, CLK_XTAL, 1500000000), - FIXED_CLK(CK_APMIXED_CCIPLL2_B, CLK_XTAL, 960000000), - FIXED_CLK(CK_APMIXED_USXGMIIPLL, CLK_XTAL, 644533000), - FIXED_CLK(CK_APMIXED_MSDCPLL, CLK_XTAL, 400000000), + FIXED_CLK(CLK_APMIXED_NETSYSPLL, CLK_XTAL, 850000000), + FIXED_CLK(CLK_APMIXED_MPLL, CLK_XTAL, 416000000), + FIXED_CLK(CLK_APMIXED_MMPLL, CLK_XTAL, 720000000), + FIXED_CLK(CLK_APMIXED_APLL2, CLK_XTAL, 196608000), + FIXED_CLK(CLK_APMIXED_NET1PLL, CLK_XTAL, 2500000000), + FIXED_CLK(CLK_APMIXED_NET2PLL, CLK_XTAL, 800000000), + FIXED_CLK(CLK_APMIXED_WEDMCUPLL, CLK_XTAL, 208000000), + FIXED_CLK(CLK_APMIXED_SGMPLL, CLK_XTAL, 325000000), + FIXED_CLK(CLK_APMIXED_ARM_B, CLK_XTAL, 1500000000), + FIXED_CLK(CLK_APMIXED_CCIPLL2_B, CLK_XTAL, 960000000), + FIXED_CLK(CLK_APMIXED_USXGMIIPLL, CLK_XTAL, 644533000), + FIXED_CLK(CLK_APMIXED_MSDCPLL, CLK_XTAL, 400000000), +}; + +/* TOPCKGEN FIXED CLK */ +static const struct mtk_fixed_clk topckgen_mtk_fixed_clks[] = { + FIXED_CLK(CLK_TOP_XTAL, CLK_XTAL, 40000000), }; /* TOPCKGEN FIXED DIV */ static const struct mtk_fixed_factor topckgen_mtk_fixed_factors[] = { - XTAL_FACTOR(CK_TOP_CB_CKSQ_40M, "cb_cksq_40m", CLK_XTAL, 1, 1), - PLL_FACTOR(CK_TOP_CB_M_416M, "cb_m_416m", CK_APMIXED_MPLL, 1, 1), - PLL_FACTOR(CK_TOP_CB_M_D2, "cb_m_d2", CK_APMIXED_MPLL, 1, 2), - PLL_FACTOR(CK_TOP_M_D3_D2, "m_d3_d2", CK_APMIXED_MPLL, 1, 2), - PLL_FACTOR(CK_TOP_CB_M_D4, "cb_m_d4", CK_APMIXED_MPLL, 1, 4), - PLL_FACTOR(CK_TOP_CB_M_D8, "cb_m_d8", CK_APMIXED_MPLL, 1, 8), - PLL_FACTOR(CK_TOP_M_D8_D2, "m_d8_d2", CK_APMIXED_MPLL, 1, 16), - PLL_FACTOR(CK_TOP_CB_MM_720M, "cb_mm_720m", CK_APMIXED_MMPLL, 1, 1), - PLL_FACTOR(CK_TOP_CB_MM_D2, "cb_mm_d2", CK_APMIXED_MMPLL, 1, 2), - PLL_FACTOR(CK_TOP_CB_MM_D3_D5, "cb_mm_d3_d5", CK_APMIXED_MMPLL, 1, 15), - PLL_FACTOR(CK_TOP_CB_MM_D4, "cb_mm_d4", CK_APMIXED_MMPLL, 1, 4), - PLL_FACTOR(CK_TOP_MM_D6_D2, "mm_d6_d2", CK_APMIXED_MMPLL, 1, 12), - PLL_FACTOR(CK_TOP_CB_MM_D8, "cb_mm_d8", CK_APMIXED_MMPLL, 1, 8), - PLL_FACTOR(CK_TOP_CB_APLL2_196M, "cb_apll2_196m", CK_APMIXED_APLL2, 1, - 1), - PLL_FACTOR(CK_TOP_CB_APLL2_D4, "cb_apll2_d4", CK_APMIXED_APLL2, 1, 4), - PLL_FACTOR(CK_TOP_CB_NET1_D4, "cb_net1_d4", CK_APMIXED_NET1PLL, 1, 4), - PLL_FACTOR(CK_TOP_CB_NET1_D5, "cb_net1_d5", CK_APMIXED_NET1PLL, 1, 5), - PLL_FACTOR(CK_TOP_NET1_D5_D2, "net1_d5_d2", CK_APMIXED_NET1PLL, 1, 10), - PLL_FACTOR(CK_TOP_NET1_D5_D4, "net1_d5_d4", CK_APMIXED_NET1PLL, 1, 20), - PLL_FACTOR(CK_TOP_CB_NET1_D8, "cb_net1_d8", CK_APMIXED_NET1PLL, 1, 8), - PLL_FACTOR(CK_TOP_NET1_D8_D2, "net1_d8_d2", CK_APMIXED_NET1PLL, 1, 16), - PLL_FACTOR(CK_TOP_NET1_D8_D4, "net1_d8_d4", CK_APMIXED_NET1PLL, 1, 32), - PLL_FACTOR(CK_TOP_NET1_D8_D8, "net1_d8_d8", CK_APMIXED_NET1PLL, 1, 64), - PLL_FACTOR(CK_TOP_NET1_D8_D16, "net1_d8_d16", CK_APMIXED_NET1PLL, 1, - 128), - PLL_FACTOR(CK_TOP_CB_NET2_800M, "cb_net2_800m", CK_APMIXED_NET2PLL, 1, - 1), - PLL_FACTOR(CK_TOP_CB_NET2_D2, "cb_net2_d2", CK_APMIXED_NET2PLL, 1, 2), - PLL_FACTOR(CK_TOP_CB_NET2_D4, "cb_net2_d4", CK_APMIXED_NET2PLL, 1, 4), - PLL_FACTOR(CK_TOP_NET2_D4_D4, "net2_d4_d4", CK_APMIXED_NET2PLL, 1, 16), - PLL_FACTOR(CK_TOP_NET2_D4_D8, "net2_d4_d8", CK_APMIXED_NET2PLL, 1, 32), - PLL_FACTOR(CK_TOP_CB_NET2_D6, "cb_net2_d6", CK_APMIXED_NET2PLL, 1, 6), - PLL_FACTOR(CK_TOP_CB_NET2_D8, "cb_net2_d8", CK_APMIXED_NET2PLL, 1, 8), - PLL_FACTOR(CK_TOP_CB_WEDMCU_208M, "cb_wedmcu_208m", - CK_APMIXED_WEDMCUPLL, 1, 1), - PLL_FACTOR(CK_TOP_CB_SGM_325M, "cb_sgm_325m", CK_APMIXED_SGMPLL, 1, 1), - PLL_FACTOR(CK_TOP_CB_NETSYS_850M, "cb_netsys_850m", - CK_APMIXED_NETSYSPLL, 1, 1), - PLL_FACTOR(CK_TOP_CB_MSDC_400M, "cb_msdc_400m", CK_APMIXED_MSDCPLL, 1, - 1), - TOP_FACTOR(CK_TOP_CKSQ_40M_D2, "cksq_40m_d2", CK_TOP_CB_CKSQ_40M, 1, 2), - TOP_FACTOR(CK_TOP_CB_RTC_32K, "cb_rtc_32k", CK_TOP_CB_CKSQ_40M, 1, + TOP_FACTOR(CLK_TOP_XTAL_D2, "xtal_d2", CLK_TOP_XTAL, 1, 2), + TOP_FACTOR(CLK_TOP_RTC_32K, "rtc_32k", CLK_TOP_XTAL, 1, 1250), - TOP_FACTOR(CK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", CK_TOP_CB_CKSQ_40M, 1, + TOP_FACTOR(CLK_TOP_RTC_32P7K, "rtc_32p7k", CLK_TOP_XTAL, 1, 1220), - TOP_FACTOR(CK_TOP_INFRA_F32K, "csw_infra_f32k", CK_TOP_CB_RTC_32P7K, 1, - 1), - XTAL_FACTOR(CK_TOP_CKSQ_SRC, "cksq_src", CLK_XTAL, 1, 1), - TOP_FACTOR(CK_TOP_NETSYS_2X, "netsys_2x", CK_TOP_NETSYS_2X_SEL, 1, 1), - TOP_FACTOR(CK_TOP_NETSYS_GSW, "netsys_gsw", CK_TOP_NETSYS_GSW_SEL, 1, - 1), - TOP_FACTOR(CK_TOP_NETSYS_WED_MCU, "netsys_wed_mcu", - CK_TOP_NETSYS_MCU_SEL, 1, 1), - TOP_FACTOR(CK_TOP_EIP197, "eip197", CK_TOP_EIP197_SEL, 1, 1), - TOP_FACTOR(CK_TOP_EMMC_250M, "emmc_250m", CK_TOP_EMMC_250M_SEL, 1, 1), - TOP_FACTOR(CK_TOP_EMMC_400M, "emmc_400m", CK_TOP_EMMC_400M_SEL, 1, 1), - TOP_FACTOR(CK_TOP_SPI, "spi", CK_TOP_SPI_SEL, 1, 1), - TOP_FACTOR(CK_TOP_SPIM_MST, "spim_mst", CK_TOP_SPIM_MST_SEL, 1, 1), - TOP_FACTOR(CK_TOP_NFI1X, "nfi1x", CK_TOP_NFI1X_SEL, 1, 1), - TOP_FACTOR(CK_TOP_SPINFI_BCK, "spinfi_bck", CK_TOP_SPINFI_SEL, 1, 1), - TOP_FACTOR(CK_TOP_I2C_BCK, "i2c_bck", CK_TOP_I2C_SEL, 1, 1), - TOP_FACTOR(CK_TOP_USB_SYS, "usb_sys", CK_TOP_USB_SYS_SEL, 1, 1), - TOP_FACTOR(CK_TOP_USB_SYS_P1, "usb_sys_p1", CK_TOP_USB_SYS_P1_SEL, 1, - 1), - TOP_FACTOR(CK_TOP_USB_XHCI, "usb_xhci", CK_TOP_USB_XHCI_SEL, 1, 1), - TOP_FACTOR(CK_TOP_USB_XHCI_P1, "usb_xhci_p1", CK_TOP_USB_XHCI_P1_SEL, 1, - 1), - TOP_FACTOR(CK_TOP_USB_FRMCNT, "usb_frmcnt", CK_TOP_USB_FRMCNT_SEL, 1, - 1), - TOP_FACTOR(CK_TOP_USB_FRMCNT_P1, "usb_frmcnt_p1", - CK_TOP_USB_FRMCNT_P1_SEL, 1, 1), - TOP_FACTOR(CK_TOP_AUD, "aud", CK_TOP_AUD_SEL, 1, 1), - TOP_FACTOR(CK_TOP_A1SYS, "a1sys", CK_TOP_A1SYS_SEL, 1, 1), - TOP_FACTOR(CK_TOP_AUD_L, "aud_l", CK_TOP_AUD_L_SEL, 1, 1), - TOP_FACTOR(CK_TOP_A_TUNER, "a_tuner", CK_TOP_A_TUNER_SEL, 1, 1), - TOP_FACTOR(CK_TOP_SYSAXI, "sysaxi", CK_TOP_SYSAXI_SEL, 1, 1), - TOP_FACTOR(CK_TOP_INFRA_F26M, "csw_infra_f26m", CK_TOP_INFRA_F26M_SEL, - 1, 1), - TOP_FACTOR(CK_TOP_USB_REF, "usb_ref", CK_TOP_CKSQ_SRC, 1, 1), - TOP_FACTOR(CK_TOP_USB_CK_P1, "usb_ck_p1", CK_TOP_CKSQ_SRC, 1, 1), + PLL_FACTOR(CLK_TOP_MPLL_D2, "mpll_d2", CLK_APMIXED_MPLL, 1, 2), + PLL_FACTOR(CLK_TOP_MPLL_D3_D2, "mpll_d3_d2", CLK_APMIXED_MPLL, 1, 2), + PLL_FACTOR(CLK_TOP_MPLL_D4, "mpll_d4", CLK_APMIXED_MPLL, 1, 4), + PLL_FACTOR(CLK_TOP_MPLL_D8, "mpll_d8", CLK_APMIXED_MPLL, 1, 8), + PLL_FACTOR(CLK_TOP_MPLL_D8_D2, "mpll_d8_d2", CLK_APMIXED_MPLL, 1, 16), + PLL_FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", CLK_APMIXED_MMPLL, 1, 2), + PLL_FACTOR(CLK_TOP_MMPLL_D3_D5, "mmpll_d3_d5", CLK_APMIXED_MMPLL, 1, 15), + PLL_FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", CLK_APMIXED_MMPLL, 1, 4), + PLL_FACTOR(CLK_TOP_MMPLL_D6_D2, "mmpll_d6_d2", CLK_APMIXED_MMPLL, 1, 12), + PLL_FACTOR(CLK_TOP_MMPLL_D8, "mmpll_d8", CLK_APMIXED_MMPLL, 1, 8), + PLL_FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", CLK_APMIXED_APLL2, 1, 4), + PLL_FACTOR(CLK_TOP_NET1PLL_D4, "net1pll_d4", CLK_APMIXED_NET1PLL, 1, 4), + PLL_FACTOR(CLK_TOP_NET1PLL_D5, "net1pll_d5", CLK_APMIXED_NET1PLL, 1, 5), + PLL_FACTOR(CLK_TOP_NET1PLL_D5_D2, "net1pll_d5_d2", CLK_APMIXED_NET1PLL, 1, 10), + PLL_FACTOR(CLK_TOP_NET1PLL_D5_D4, "net1pll_d5_d4", CLK_APMIXED_NET1PLL, 1, 20), + PLL_FACTOR(CLK_TOP_NET1PLL_D8, "net1pll_d8", CLK_APMIXED_NET1PLL, 1, 8), + PLL_FACTOR(CLK_TOP_NET1PLL_D8_D2, "net1pll_d8_d2", CLK_APMIXED_NET1PLL, 1, 16), + PLL_FACTOR(CLK_TOP_NET1PLL_D8_D4, "net1pll_d8_d4", CLK_APMIXED_NET1PLL, 1, 32), + PLL_FACTOR(CLK_TOP_NET1PLL_D8_D8, "net1pll_d8_d8", CLK_APMIXED_NET1PLL, 1, 64), + PLL_FACTOR(CLK_TOP_NET1PLL_D8_D16, "net1pll_d8_d16", CLK_APMIXED_NET1PLL, 1, + 128), + PLL_FACTOR(CLK_TOP_NET2PLL_D2, "net2pll_d2", CLK_APMIXED_NET2PLL, 1, 2), + PLL_FACTOR(CLK_TOP_NET2PLL_D4, "net2pll_d4", CLK_APMIXED_NET2PLL, 1, 4), + PLL_FACTOR(CLK_TOP_NET2PLL_D4_D4, "net2pll_d4_d4", CLK_APMIXED_NET2PLL, 1, 16), + PLL_FACTOR(CLK_TOP_NET2PLL_D4_D8, "net2pll_d4_d8", CLK_APMIXED_NET2PLL, 1, 32), + PLL_FACTOR(CLK_TOP_NET2PLL_D6, "net2pll_d6", CLK_APMIXED_NET2PLL, 1, 6), + PLL_FACTOR(CLK_TOP_NET2PLL_D8, "net2pll_d8", CLK_APMIXED_NET2PLL, 1, 8), }; /* TOPCKGEN MUX PARENTS */ -static const int netsys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET2_D2, - CK_TOP_CB_MM_D2 }; +#define APMIXED_PARENT(_id) PARENT(_id, CLK_PARENT_APMIXED) +#define TOP_PARENT(_id) PARENT(_id, CLK_PARENT_TOPCKGEN) -static const int netsys_500m_parents[] = { CK_TOP_CB_CKSQ_40M, - CK_TOP_CB_NET1_D5, - CK_TOP_NET1_D5_D2 }; +static const struct mtk_parent netsys_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET2PLL_D2), + TOP_PARENT(CLK_TOP_MMPLL_D2), +}; -static const int netsys_2x_parents[] = { CK_TOP_CB_CKSQ_40M, - CK_TOP_CB_NET2_800M, - CK_TOP_CB_MM_720M }; +static const struct mtk_parent netsys_500m_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D5), + TOP_PARENT(CLK_TOP_NET1PLL_D5_D2), +}; -static const int netsys_gsw_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET1_D4, - CK_TOP_CB_NET1_D5 }; +static const struct mtk_parent netsys_2x_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_NET2PLL), + APMIXED_PARENT(CLK_APMIXED_MMPLL), +}; -static const int eth_gmii_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4 }; +static const struct mtk_parent netsys_gsw_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D4), + TOP_PARENT(CLK_TOP_NET1PLL_D5), +}; -static const int netsys_mcu_parents[] = { - CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET2_800M, CK_TOP_CB_MM_720M, - CK_TOP_CB_NET1_D4, CK_TOP_CB_NET1_D5, CK_TOP_CB_M_416M +static const struct mtk_parent eth_gmii_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D5_D4), }; -static const int eip197_parents[] = { - CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NETSYS_850M, CK_TOP_CB_NET2_800M, - CK_TOP_CB_MM_720M, CK_TOP_CB_NET1_D4, CK_TOP_CB_NET1_D5 +static const struct mtk_parent netsys_mcu_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_NET2PLL), + APMIXED_PARENT(CLK_APMIXED_MMPLL), TOP_PARENT(CLK_TOP_NET1PLL_D4), + TOP_PARENT(CLK_TOP_NET1PLL_D5), APMIXED_PARENT(CLK_APMIXED_MPLL), }; -static const int axi_infra_parents[] = { CK_TOP_CB_CKSQ_40M, - CK_TOP_NET1_D8_D2 }; +static const struct mtk_parent eip197_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_NETSYSPLL), + APMIXED_PARENT(CLK_APMIXED_NET2PLL), APMIXED_PARENT(CLK_APMIXED_MMPLL), + TOP_PARENT(CLK_TOP_NET1PLL_D4), TOP_PARENT(CLK_TOP_NET1PLL_D5), +}; -static const int uart_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D8, - CK_TOP_M_D8_D2 }; +static const struct mtk_parent axi_infra_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D8_D2), +}; -static const int emmc_250m_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D2, - CK_TOP_CB_MM_D4 }; +static const struct mtk_parent uart_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MPLL_D8), + TOP_PARENT(CLK_TOP_MPLL_D8_D2), +}; -static const int emmc_400m_parents[] = { - CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MSDC_400M, CK_TOP_CB_MM_D2, - CK_TOP_CB_M_D2, CK_TOP_CB_MM_D4, CK_TOP_NET1_D8_D2 +static const struct mtk_parent emmc_250m_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D5_D2), + TOP_PARENT(CLK_TOP_MMPLL_D4), }; -static const int spi_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2, - CK_TOP_CB_MM_D4, CK_TOP_NET1_D8_D2, - CK_TOP_CB_NET2_D6, CK_TOP_NET1_D5_D4, - CK_TOP_CB_M_D4, CK_TOP_NET1_D8_D4 }; +static const struct mtk_parent emmc_400m_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_MSDCPLL), + TOP_PARENT(CLK_TOP_MMPLL_D2), TOP_PARENT(CLK_TOP_MPLL_D2), + TOP_PARENT(CLK_TOP_MMPLL_D4), TOP_PARENT(CLK_TOP_NET1PLL_D8_D2), +}; -static const int nfi1x_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MM_D4, - CK_TOP_NET1_D8_D2, CK_TOP_CB_NET2_D6, - CK_TOP_CB_M_D4, CK_TOP_CB_MM_D8, - CK_TOP_NET1_D8_D4, CK_TOP_CB_M_D8 }; +static const struct mtk_parent spi_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MPLL_D2), + TOP_PARENT(CLK_TOP_MMPLL_D4), TOP_PARENT(CLK_TOP_NET1PLL_D8_D2), + TOP_PARENT(CLK_TOP_NET2PLL_D6), TOP_PARENT(CLK_TOP_NET1PLL_D5_D4), + TOP_PARENT(CLK_TOP_MPLL_D4), TOP_PARENT(CLK_TOP_NET1PLL_D8_D4), +}; -static const int spinfi_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_CB_CKSQ_40M, - CK_TOP_NET1_D5_D4, CK_TOP_CB_M_D4, - CK_TOP_CB_MM_D8, CK_TOP_NET1_D8_D4, - CK_TOP_MM_D6_D2, CK_TOP_CB_M_D8 }; +static const struct mtk_parent nfi1x_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MMPLL_D4), + TOP_PARENT(CLK_TOP_NET1PLL_D8_D2), TOP_PARENT(CLK_TOP_NET2PLL_D6), + TOP_PARENT(CLK_TOP_MPLL_D4), TOP_PARENT(CLK_TOP_MMPLL_D8), + TOP_PARENT(CLK_TOP_NET1PLL_D8_D4), TOP_PARENT(CLK_TOP_MPLL_D8), +}; -static const int pwm_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D8_D2, - CK_TOP_NET1_D5_D4, CK_TOP_CB_M_D4, - CK_TOP_M_D8_D2, CK_TOP_CB_RTC_32K }; +static const struct mtk_parent spinfi_parents[] = { + TOP_PARENT(CLK_TOP_XTAL_D2), TOP_PARENT(CLK_TOP_XTAL), + TOP_PARENT(CLK_TOP_NET1PLL_D5_D4), TOP_PARENT(CLK_TOP_MPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D8), TOP_PARENT(CLK_TOP_NET1PLL_D8_D4), + TOP_PARENT(CLK_TOP_MMPLL_D6_D2), TOP_PARENT(CLK_TOP_MPLL_D8), +}; -static const int i2c_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4, - CK_TOP_CB_M_D4, CK_TOP_NET1_D8_D4 }; +static const struct mtk_parent pwm_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D8_D2), + TOP_PARENT(CLK_TOP_NET1PLL_D5_D4), TOP_PARENT(CLK_TOP_MPLL_D4), + TOP_PARENT(CLK_TOP_MPLL_D8_D2), TOP_PARENT(CLK_TOP_RTC_32K), +}; -static const int pcie_mbist_250m_parents[] = { CK_TOP_CB_CKSQ_40M, - CK_TOP_NET1_D5_D2 }; +static const struct mtk_parent i2c_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D5_D4), + TOP_PARENT(CLK_TOP_MPLL_D4), TOP_PARENT(CLK_TOP_NET1PLL_D8_D4), +}; -static const int pextp_tl_ck_parents[] = { CK_TOP_CB_CKSQ_40M, - CK_TOP_CB_NET2_D6, CK_TOP_CB_MM_D8, - CK_TOP_M_D8_D2, CK_TOP_CB_RTC_32K }; +static const struct mtk_parent pcie_mbist_250m_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D5_D2), +}; -static const int usb_frmcnt_parents[] = { CK_TOP_CB_CKSQ_40M, - CK_TOP_CB_MM_D3_D5 }; +static const struct mtk_parent pextp_tl_ck_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET2PLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D8), TOP_PARENT(CLK_TOP_MPLL_D8_D2), + TOP_PARENT(CLK_TOP_RTC_32K), +}; -static const int aud_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_APLL2_196M }; +static const struct mtk_parent usb_frmcnt_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MMPLL_D3_D5), +}; -static const int a1sys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_APLL2_D4 }; +static const struct mtk_parent aud_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_APLL2), +}; -static const int aud_l_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_APLL2_196M, - CK_TOP_M_D8_D2 }; +static const struct mtk_parent a1sys_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_APLL2_D4), +}; + +static const struct mtk_parent aud_l_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_APLL2), + TOP_PARENT(CLK_TOP_MPLL_D8_D2), +}; -static const int sspxtp_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_M_D8_D2 }; +static const struct mtk_parent sspxtp_parents[] = { + TOP_PARENT(CLK_TOP_XTAL_D2), TOP_PARENT(CLK_TOP_MPLL_D8_D2), +}; -static const int usxgmii_sbus_0_parents[] = { CK_TOP_CB_CKSQ_40M, - CK_TOP_NET1_D8_D4 }; +static const struct mtk_parent usxgmii_sbus_0_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D8_D4), +}; -static const int sgm_0_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_SGM_325M }; +static const struct mtk_parent sgm_0_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_SGMPLL), +}; -static const int sysapb_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_M_D3_D2 }; +static const struct mtk_parent sysapb_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MPLL_D3_D2), +}; -static const int eth_refck_50m_parents[] = { CK_TOP_CB_CKSQ_40M, - CK_TOP_NET2_D4_D4 }; +static const struct mtk_parent eth_refck_50m_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET2PLL_D4_D4), +}; -static const int eth_sys_200m_parents[] = { CK_TOP_CB_CKSQ_40M, - CK_TOP_CB_NET2_D4 }; +static const struct mtk_parent eth_sys_200m_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET2PLL_D4), +}; -static const int eth_xgmii_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_NET1_D8_D8, - CK_TOP_NET1_D8_D16 }; +static const struct mtk_parent eth_xgmii_parents[] = { + TOP_PARENT(CLK_TOP_XTAL_D2), TOP_PARENT(CLK_TOP_NET1PLL_D8_D8), + TOP_PARENT(CLK_TOP_NET1PLL_D8_D16), +}; -static const int bus_tops_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET1_D5, - CK_TOP_CB_NET2_D2 }; +static const struct mtk_parent bus_tops_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D5), + TOP_PARENT(CLK_TOP_NET2PLL_D2), +}; -static const int npu_tops_parents[] = { CK_TOP_CB_CKSQ_40M, - CK_TOP_CB_NET2_800M }; +static const struct mtk_parent npu_tops_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_NET2PLL), +}; -static const int dramc_md32_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2, - CK_TOP_CB_WEDMCU_208M }; +static const struct mtk_parent dramc_md32_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MPLL_D2), + APMIXED_PARENT(CLK_APMIXED_WEDMCUPLL), +}; -static const int da_xtp_glb_p0_parents[] = { CK_TOP_CB_CKSQ_40M, - CK_TOP_CB_NET2_D8 }; +static const struct mtk_parent da_xtp_glb_p0_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET2PLL_D8), +}; -static const int mcusys_backup_625m_parents[] = { CK_TOP_CB_CKSQ_40M, - CK_TOP_CB_NET1_D4 }; +static const struct mtk_parent mcusys_backup_625m_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D4), +}; -static const int macsec_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_SGM_325M, - CK_TOP_CB_NET1_D8 }; +static const struct mtk_parent macsec_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_SGMPLL), + TOP_PARENT(CLK_TOP_NET1PLL_D8), +}; -static const int netsys_tops_400m_parents[] = { CK_TOP_CB_CKSQ_40M, - CK_TOP_CB_NET2_D2 }; +static const struct mtk_parent netsys_tops_400m_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET2PLL_D2), +}; -static const int eth_mii_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_NET2_D4_D8 }; +static const struct mtk_parent eth_mii_parents[] = { + TOP_PARENT(CLK_TOP_XTAL_D2), TOP_PARENT(CLK_TOP_NET2PLL_D4_D8), +}; #define TOP_MUX(_id, _name, _parents, _mux_ofs, _mux_set_ofs, _mux_clr_ofs, \ _shift, _width, _gate, _upd_ofs, _upd) \ @@ -262,278 +280,204 @@ static const int eth_mii_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_NET2_D4_D8 }; .mux_clr_reg = _mux_clr_ofs, .upd_reg = _upd_ofs, \ .upd_shift = _upd, .mux_shift = _shift, \ .mux_mask = BIT(_width) - 1, .gate_reg = _mux_ofs, \ - .gate_shift = _gate, .parent = _parents, \ + .gate_shift = _gate, .parent_flags = _parents, \ .num_parents = ARRAY_SIZE(_parents), \ - .flags = CLK_MUX_SETCLR_UPD, \ + .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_MIXED, \ } /* TOPCKGEN MUX_GATE */ static const struct mtk_composite topckgen_mtk_muxes[] = { - TOP_MUX(CK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 0x0, 0x4, 0x8, + TOP_MUX(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 0x0, 0x4, 0x8, 0, 2, 7, 0x1c0, 0), - TOP_MUX(CK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", netsys_500m_parents, + TOP_MUX(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", netsys_500m_parents, 0x0, 0x4, 0x8, 8, 2, 15, 0x1c0, 1), - TOP_MUX(CK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, 0x0, + TOP_MUX(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, 0x0, 0x4, 0x8, 16, 2, 23, 0x1c0, 2), - TOP_MUX(CK_TOP_NETSYS_GSW_SEL, "netsys_gsw_sel", netsys_gsw_parents, + TOP_MUX(CLK_TOP_NETSYS_GSW_SEL, "netsys_gsw_sel", netsys_gsw_parents, 0x0, 0x4, 0x8, 24, 2, 31, 0x1c0, 3), - TOP_MUX(CK_TOP_ETH_GMII_SEL, "eth_gmii_sel", eth_gmii_parents, 0x10, + TOP_MUX(CLK_TOP_ETH_GMII_SEL, "eth_gmii_sel", eth_gmii_parents, 0x10, 0x14, 0x18, 0, 1, 7, 0x1c0, 4), - TOP_MUX(CK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", netsys_mcu_parents, + TOP_MUX(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", netsys_mcu_parents, 0x10, 0x14, 0x18, 8, 3, 15, 0x1c0, 5), - TOP_MUX(CK_TOP_NETSYS_PAO_2X_SEL, "netsys_pao_2x_sel", + TOP_MUX(CLK_TOP_NETSYS_PAO_2X_SEL, "netsys_pao_2x_sel", netsys_mcu_parents, 0x10, 0x14, 0x18, 16, 3, 23, 0x1c0, 6), - TOP_MUX(CK_TOP_EIP197_SEL, "eip197_sel", eip197_parents, 0x10, 0x14, + TOP_MUX(CLK_TOP_EIP197_SEL, "eip197_sel", eip197_parents, 0x10, 0x14, 0x18, 24, 3, 31, 0x1c0, 7), - TOP_MUX(CK_TOP_AXI_INFRA_SEL, "axi_infra_sel", axi_infra_parents, 0x20, + TOP_MUX(CLK_TOP_AXI_INFRA_SEL, "axi_infra_sel", axi_infra_parents, 0x20, 0x24, 0x28, 0, 1, 7, 0x1c0, 8), - TOP_MUX(CK_TOP_UART_SEL, "uart_sel", uart_parents, 0x20, 0x24, 0x28, 8, + TOP_MUX(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x20, 0x24, 0x28, 8, 2, 15, 0x1c0, 9), - TOP_MUX(CK_TOP_EMMC_250M_SEL, "emmc_250m_sel", emmc_250m_parents, 0x20, + TOP_MUX(CLK_TOP_EMMC_250M_SEL, "emmc_250m_sel", emmc_250m_parents, 0x20, 0x24, 0x28, 16, 2, 23, 0x1c0, 10), - TOP_MUX(CK_TOP_EMMC_400M_SEL, "emmc_400m_sel", emmc_400m_parents, 0x20, + TOP_MUX(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel", emmc_400m_parents, 0x20, 0x24, 0x28, 24, 3, 31, 0x1c0, 11), - TOP_MUX(CK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x30, 0x34, 0x38, 0, 3, + TOP_MUX(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x30, 0x34, 0x38, 0, 3, 7, 0x1c0, 12), - TOP_MUX(CK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, 0x30, 0x34, + TOP_MUX(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, 0x30, 0x34, 0x38, 8, 3, 15, 0x1c0, 13), - TOP_MUX(CK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, 0x30, 0x34, 0x38, + TOP_MUX(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, 0x30, 0x34, 0x38, 16, 3, 23, 0x1c0, 14), - TOP_MUX(CK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, 0x30, 0x34, + TOP_MUX(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, 0x30, 0x34, 0x38, 24, 3, 31, 0x1c0, 15), - TOP_MUX(CK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x40, 0x44, 0x48, 0, 3, + TOP_MUX(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x40, 0x44, 0x48, 0, 3, 7, 0x1c0, 16), - TOP_MUX(CK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x40, 0x44, 0x48, 8, 2, + TOP_MUX(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x40, 0x44, 0x48, 8, 2, 15, 0x1c0, 17), - TOP_MUX(CK_TOP_PCIE_MBIST_250M_SEL, "pcie_mbist_250m_sel", + TOP_MUX(CLK_TOP_PCIE_MBIST_250M_SEL, "pcie_mbist_250m_sel", pcie_mbist_250m_parents, 0x40, 0x44, 0x48, 16, 1, 23, 0x1c0, 18), - TOP_MUX(CK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", pextp_tl_ck_parents, + TOP_MUX(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", pextp_tl_ck_parents, 0x40, 0x44, 0x48, 24, 3, 31, 0x1c0, 19), - TOP_MUX(CK_TOP_PEXTP_TL_P1_SEL, "pextp_tl_ck_p1_sel", + TOP_MUX(CLK_TOP_PEXTP_TL_P1_SEL, "pextp_tl_ck_p1_sel", pextp_tl_ck_parents, 0x50, 0x54, 0x58, 0, 3, 7, 0x1c0, 20), - TOP_MUX(CK_TOP_PEXTP_TL_P2_SEL, "pextp_tl_ck_p2_sel", + TOP_MUX(CLK_TOP_PEXTP_TL_P2_SEL, "pextp_tl_ck_p2_sel", pextp_tl_ck_parents, 0x50, 0x54, 0x58, 8, 3, 15, 0x1c0, 21), - TOP_MUX(CK_TOP_PEXTP_TL_P3_SEL, "pextp_tl_ck_p3_sel", + TOP_MUX(CLK_TOP_PEXTP_TL_P3_SEL, "pextp_tl_ck_p3_sel", pextp_tl_ck_parents, 0x50, 0x54, 0x58, 16, 3, 23, 0x1c0, 22), - TOP_MUX(CK_TOP_USB_SYS_SEL, "usb_sys_sel", eth_gmii_parents, 0x50, 0x54, + TOP_MUX(CLK_TOP_USB_SYS_SEL, "usb_sys_sel", eth_gmii_parents, 0x50, 0x54, 0x58, 24, 1, 31, 0x1c0, 23), - TOP_MUX(CK_TOP_USB_SYS_P1_SEL, "usb_sys_p1_sel", eth_gmii_parents, 0x60, + TOP_MUX(CLK_TOP_USB_SYS_P1_SEL, "usb_sys_p1_sel", eth_gmii_parents, 0x60, 0x64, 0x68, 0, 1, 7, 0x1c0, 24), - TOP_MUX(CK_TOP_USB_XHCI_SEL, "usb_xhci_sel", eth_gmii_parents, 0x60, + TOP_MUX(CLK_TOP_USB_XHCI_SEL, "usb_xhci_sel", eth_gmii_parents, 0x60, 0x64, 0x68, 8, 1, 15, 0x1c0, 25), - TOP_MUX(CK_TOP_USB_XHCI_P1_SEL, "usb_xhci_p1_sel", eth_gmii_parents, + TOP_MUX(CLK_TOP_USB_XHCI_P1_SEL, "usb_xhci_p1_sel", eth_gmii_parents, 0x60, 0x64, 0x68, 16, 1, 23, 0x1c0, 26), - TOP_MUX(CK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel", usb_frmcnt_parents, + TOP_MUX(CLK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel", usb_frmcnt_parents, 0x60, 0x64, 0x68, 24, 1, 31, 0x1c0, 27), - TOP_MUX(CK_TOP_USB_FRMCNT_P1_SEL, "usb_frmcnt_p1_sel", + TOP_MUX(CLK_TOP_USB_FRMCNT_P1_SEL, "usb_frmcnt_p1_sel", usb_frmcnt_parents, 0x70, 0x74, 0x78, 0, 1, 7, 0x1c0, 28), - TOP_MUX(CK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x70, 0x74, 0x78, 8, 1, + TOP_MUX(CLK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x70, 0x74, 0x78, 8, 1, 15, 0x1c0, 29), - TOP_MUX(CK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 0x70, 0x74, 0x78, + TOP_MUX(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 0x70, 0x74, 0x78, 16, 1, 23, 0x1c0, 30), - TOP_MUX(CK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 0x70, 0x74, 0x78, + TOP_MUX(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 0x70, 0x74, 0x78, 24, 2, 31, 0x1c4, 0), - TOP_MUX(CK_TOP_A_TUNER_SEL, "a_tuner_sel", a1sys_parents, 0x80, 0x84, + TOP_MUX(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", a1sys_parents, 0x80, 0x84, 0x88, 0, 1, 7, 0x1c4, 1), - TOP_MUX(CK_TOP_SSPXTP_SEL, "sspxtp_sel", sspxtp_parents, 0x80, 0x84, + TOP_MUX(CLK_TOP_SSPXTP_SEL, "sspxtp_sel", sspxtp_parents, 0x80, 0x84, 0x88, 8, 1, 15, 0x1c4, 2), - TOP_MUX(CK_TOP_USB_PHY_SEL, "usb_phy_sel", sspxtp_parents, 0x80, 0x84, + TOP_MUX(CLK_TOP_USB_PHY_SEL, "usb_phy_sel", sspxtp_parents, 0x80, 0x84, 0x88, 16, 1, 23, 0x1c4, 3), - TOP_MUX(CK_TOP_USXGMII_SBUS_0_SEL, "usxgmii_sbus_0_sel", + TOP_MUX(CLK_TOP_USXGMII_SBUS_0_SEL, "usxgmii_sbus_0_sel", usxgmii_sbus_0_parents, 0x80, 0x84, 0x88, 24, 1, 31, 0x1c4, 4), - TOP_MUX(CK_TOP_USXGMII_SBUS_1_SEL, "usxgmii_sbus_1_sel", + TOP_MUX(CLK_TOP_USXGMII_SBUS_1_SEL, "usxgmii_sbus_1_sel", usxgmii_sbus_0_parents, 0x90, 0x94, 0x98, 0, 1, 7, 0x1c4, 5), - TOP_MUX(CK_TOP_SGM_0_SEL, "sgm_0_sel", sgm_0_parents, 0x90, 0x94, 0x98, + TOP_MUX(CLK_TOP_SGM_0_SEL, "sgm_0_sel", sgm_0_parents, 0x90, 0x94, 0x98, 8, 1, 15, 0x1c4, 6), - TOP_MUX(CK_TOP_SGM_SBUS_0_SEL, "sgm_sbus_0_sel", usxgmii_sbus_0_parents, + TOP_MUX(CLK_TOP_SGM_SBUS_0_SEL, "sgm_sbus_0_sel", usxgmii_sbus_0_parents, 0x90, 0x94, 0x98, 16, 1, 23, 0x1c4, 7), - TOP_MUX(CK_TOP_SGM_1_SEL, "sgm_1_sel", sgm_0_parents, 0x90, 0x94, 0x98, + TOP_MUX(CLK_TOP_SGM_1_SEL, "sgm_1_sel", sgm_0_parents, 0x90, 0x94, 0x98, 24, 1, 31, 0x1c4, 8), - TOP_MUX(CK_TOP_SGM_SBUS_1_SEL, "sgm_sbus_1_sel", usxgmii_sbus_0_parents, + TOP_MUX(CLK_TOP_SGM_SBUS_1_SEL, "sgm_sbus_1_sel", usxgmii_sbus_0_parents, 0xa0, 0xa4, 0xa8, 0, 1, 7, 0x1c4, 9), - TOP_MUX(CK_TOP_XFI_PHY_0_XTAL_SEL, "xfi_phy_0_xtal_sel", sspxtp_parents, + TOP_MUX(CLK_TOP_XFI_PHY_0_XTAL_SEL, "xfi_phy_0_xtal_sel", sspxtp_parents, 0xa0, 0xa4, 0xa8, 8, 1, 15, 0x1c4, 10), - TOP_MUX(CK_TOP_XFI_PHY_1_XTAL_SEL, "xfi_phy_1_xtal_sel", sspxtp_parents, + TOP_MUX(CLK_TOP_XFI_PHY_1_XTAL_SEL, "xfi_phy_1_xtal_sel", sspxtp_parents, 0xa0, 0xa4, 0xa8, 16, 1, 23, 0x1c4, 11), - TOP_MUX(CK_TOP_SYSAXI_SEL, "sysaxi_sel", axi_infra_parents, 0xa0, 0xa4, + TOP_MUX(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", axi_infra_parents, 0xa0, 0xa4, 0xa8, 24, 1, 31, 0x1c4, 12), - TOP_MUX(CK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, 0xb0, 0xb4, + TOP_MUX(CLK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, 0xb0, 0xb4, 0xb8, 0, 1, 7, 0x1c4, 13), - TOP_MUX(CK_TOP_ETH_REFCK_50M_SEL, "eth_refck_50m_sel", + TOP_MUX(CLK_TOP_ETH_REFCK_50M_SEL, "eth_refck_50m_sel", eth_refck_50m_parents, 0xb0, 0xb4, 0xb8, 8, 1, 15, 0x1c4, 14), - TOP_MUX(CK_TOP_ETH_SYS_200M_SEL, "eth_sys_200m_sel", + TOP_MUX(CLK_TOP_ETH_SYS_200M_SEL, "eth_sys_200m_sel", eth_sys_200m_parents, 0xb0, 0xb4, 0xb8, 16, 1, 23, 0x1c4, 15), - TOP_MUX(CK_TOP_ETH_SYS_SEL, "eth_sys_sel", pcie_mbist_250m_parents, + TOP_MUX(CLK_TOP_ETH_SYS_SEL, "eth_sys_sel", pcie_mbist_250m_parents, 0xb0, 0xb4, 0xb8, 24, 1, 31, 0x1c4, 16), - TOP_MUX(CK_TOP_ETH_XGMII_SEL, "eth_xgmii_sel", eth_xgmii_parents, 0xc0, + TOP_MUX(CLK_TOP_ETH_XGMII_SEL, "eth_xgmii_sel", eth_xgmii_parents, 0xc0, 0xc4, 0xc8, 0, 2, 7, 0x1c4, 17), - TOP_MUX(CK_TOP_BUS_TOPS_SEL, "bus_tops_sel", bus_tops_parents, 0xc0, + TOP_MUX(CLK_TOP_BUS_TOPS_SEL, "bus_tops_sel", bus_tops_parents, 0xc0, 0xc4, 0xc8, 8, 2, 15, 0x1c4, 18), - TOP_MUX(CK_TOP_NPU_TOPS_SEL, "npu_tops_sel", npu_tops_parents, 0xc0, + TOP_MUX(CLK_TOP_NPU_TOPS_SEL, "npu_tops_sel", npu_tops_parents, 0xc0, 0xc4, 0xc8, 16, 1, 23, 0x1c4, 19), - TOP_MUX(CK_TOP_DRAMC_SEL, "dramc_sel", sspxtp_parents, 0xc0, 0xc4, 0xc8, + TOP_MUX(CLK_TOP_DRAMC_SEL, "dramc_sel", sspxtp_parents, 0xc0, 0xc4, 0xc8, 24, 1, 31, 0x1c4, 20), - TOP_MUX(CK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", dramc_md32_parents, + TOP_MUX(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", dramc_md32_parents, 0xd0, 0xd4, 0xd8, 0, 2, 7, 0x1c4, 21), - TOP_MUX(CK_TOP_INFRA_F26M_SEL, "csw_infra_f26m_sel", sspxtp_parents, + TOP_MUX(CLK_TOP_INFRA_F26M_SEL, "csw_infra_f26m_sel", sspxtp_parents, 0xd0, 0xd4, 0xd8, 8, 1, 15, 0x1c4, 22), - TOP_MUX(CK_TOP_PEXTP_P0_SEL, "pextp_p0_sel", sspxtp_parents, 0xd0, 0xd4, + TOP_MUX(CLK_TOP_PEXTP_P0_SEL, "pextp_p0_sel", sspxtp_parents, 0xd0, 0xd4, 0xd8, 16, 1, 23, 0x1c4, 23), - TOP_MUX(CK_TOP_PEXTP_P1_SEL, "pextp_p1_sel", sspxtp_parents, 0xd0, 0xd4, + TOP_MUX(CLK_TOP_PEXTP_P1_SEL, "pextp_p1_sel", sspxtp_parents, 0xd0, 0xd4, 0xd8, 24, 1, 31, 0x1c4, 24), - TOP_MUX(CK_TOP_PEXTP_P2_SEL, "pextp_p2_sel", sspxtp_parents, 0xe0, 0xe4, + TOP_MUX(CLK_TOP_PEXTP_P2_SEL, "pextp_p2_sel", sspxtp_parents, 0xe0, 0xe4, 0xe8, 0, 1, 7, 0x1c4, 25), - TOP_MUX(CK_TOP_PEXTP_P3_SEL, "pextp_p3_sel", sspxtp_parents, 0xe0, 0xe4, + TOP_MUX(CLK_TOP_PEXTP_P3_SEL, "pextp_p3_sel", sspxtp_parents, 0xe0, 0xe4, 0xe8, 8, 1, 15, 0x1c4, 26), - TOP_MUX(CK_TOP_DA_XTP_GLB_P0_SEL, "da_xtp_glb_p0_sel", + TOP_MUX(CLK_TOP_DA_XTP_GLB_P0_SEL, "da_xtp_glb_p0_sel", da_xtp_glb_p0_parents, 0xe0, 0xe4, 0xe8, 16, 1, 23, 0x1c4, 27), - TOP_MUX(CK_TOP_DA_XTP_GLB_P1_SEL, "da_xtp_glb_p1_sel", + TOP_MUX(CLK_TOP_DA_XTP_GLB_P1_SEL, "da_xtp_glb_p1_sel", da_xtp_glb_p0_parents, 0xe0, 0xe4, 0xe8, 24, 1, 31, 0x1c4, 28), - TOP_MUX(CK_TOP_DA_XTP_GLB_P2_SEL, "da_xtp_glb_p2_sel", + TOP_MUX(CLK_TOP_DA_XTP_GLB_P2_SEL, "da_xtp_glb_p2_sel", da_xtp_glb_p0_parents, 0xf0, 0xf4, 0xf8, 0, 1, 7, 0x1c4, 29), - TOP_MUX(CK_TOP_DA_XTP_GLB_P3_SEL, "da_xtp_glb_p3_sel", + TOP_MUX(CLK_TOP_DA_XTP_GLB_P3_SEL, "da_xtp_glb_p3_sel", da_xtp_glb_p0_parents, 0xf0, 0xf4, 0xf8, 8, 1, 15, 0x1c4, 30), - TOP_MUX(CK_TOP_CKM_SEL, "ckm_sel", sspxtp_parents, 0xf0, 0xf4, 0xf8, 16, + TOP_MUX(CLK_TOP_CKM_SEL, "ckm_sel", sspxtp_parents, 0xf0, 0xf4, 0xf8, 16, 1, 23, 0x1c8, 0), - TOP_MUX(CK_TOP_DA_SELM_XTAL_SEL, "da_selm_xtal_sel", sspxtp_parents, + TOP_MUX(CLK_TOP_DA_SEL, "da_sel", sspxtp_parents, 0xf0, 0xf4, 0xf8, 24, 1, 31, 0x1c8, 1), - TOP_MUX(CK_TOP_PEXTP_SEL, "pextp_sel", sspxtp_parents, 0x100, 0x104, + TOP_MUX(CLK_TOP_PEXTP_SEL, "pextp_sel", sspxtp_parents, 0x100, 0x104, 0x108, 0, 1, 7, 0x1c8, 2), - TOP_MUX(CK_TOP_TOPS_P2_26M_SEL, "tops_p2_26m_sel", sspxtp_parents, + TOP_MUX(CLK_TOP_TOPS_P2_26M_SEL, "tops_p2_26m_sel", sspxtp_parents, 0x100, 0x104, 0x108, 8, 1, 15, 0x1c8, 3), - TOP_MUX(CK_TOP_MCUSYS_BACKUP_625M_SEL, "mcusys_backup_625m_sel", + TOP_MUX(CLK_TOP_MCUSYS_BACKUP_625M_SEL, "mcusys_backup_625m_sel", mcusys_backup_625m_parents, 0x100, 0x104, 0x108, 16, 1, 23, 0x1c8, 4), - TOP_MUX(CK_TOP_NETSYS_SYNC_250M_SEL, "netsys_sync_250m_sel", + TOP_MUX(CLK_TOP_NETSYS_SYNC_250M_SEL, "netsys_sync_250m_sel", pcie_mbist_250m_parents, 0x100, 0x104, 0x108, 24, 1, 31, 0x1c8, 5), - TOP_MUX(CK_TOP_MACSEC_SEL, "macsec_sel", macsec_parents, 0x110, 0x114, + TOP_MUX(CLK_TOP_MACSEC_SEL, "macsec_sel", macsec_parents, 0x110, 0x114, 0x118, 0, 2, 7, 0x1c8, 6), - TOP_MUX(CK_TOP_NETSYS_TOPS_400M_SEL, "netsys_tops_400m_sel", + TOP_MUX(CLK_TOP_NETSYS_TOPS_400M_SEL, "netsys_tops_400m_sel", netsys_tops_400m_parents, 0x110, 0x114, 0x118, 8, 1, 15, 0x1c8, 7), - TOP_MUX(CK_TOP_NETSYS_PPEFB_250M_SEL, "netsys_ppefb_250m_sel", + TOP_MUX(CLK_TOP_NETSYS_PPEFB_250M_SEL, "netsys_ppefb_250m_sel", pcie_mbist_250m_parents, 0x110, 0x114, 0x118, 16, 1, 23, 0x1c8, 8), - TOP_MUX(CK_TOP_NETSYS_WARP_SEL, "netsys_warp_sel", netsys_parents, + TOP_MUX(CLK_TOP_NETSYS_WARP_SEL, "netsys_warp_sel", netsys_parents, 0x110, 0x114, 0x118, 24, 2, 31, 0x1c8, 9), - TOP_MUX(CK_TOP_ETH_MII_SEL, "eth_mii_sel", eth_mii_parents, 0x120, + TOP_MUX(CLK_TOP_ETH_MII_SEL, "eth_mii_sel", eth_mii_parents, 0x120, 0x124, 0x128, 0, 1, 7, 0x1c8, 10), - TOP_MUX(CK_TOP_CK_NPU_SEL_CM_TOPS_SEL, "ck_npu_sel_cm_tops_sel", + TOP_MUX(CLK_TOP_NPU_SEL, "ck_npu_sel", netsys_2x_parents, 0x120, 0x124, 0x128, 8, 2, 15, 0x1c8, 11), }; -/* INFRA FIXED DIV */ -static const struct mtk_fixed_factor infracfg_mtk_fixed_factor[] = { - TOP_FACTOR(CK_INFRA_CK_F26M, "infra_ck_f26m", CK_TOP_INFRA_F26M_SEL, 1, - 1), - TOP_FACTOR(CK_INFRA_PWM_O, "infra_pwm_o", CK_TOP_PWM_SEL, 1, 1), - TOP_FACTOR(CK_INFRA_PCIE_OCC_P0, "infra_pcie_ck_occ_p0", - CK_TOP_PEXTP_TL_SEL, 1, 1), - TOP_FACTOR(CK_INFRA_PCIE_OCC_P1, "infra_pcie_ck_occ_p1", - CK_TOP_PEXTP_TL_P1_SEL, 1, 1), - TOP_FACTOR(CK_INFRA_PCIE_OCC_P2, "infra_pcie_ck_occ_p2", - CK_TOP_PEXTP_TL_P2_SEL, 1, 1), - TOP_FACTOR(CK_INFRA_PCIE_OCC_P3, "infra_pcie_ck_occ_p3", - CK_TOP_PEXTP_TL_P3_SEL, 1, 1), - TOP_FACTOR(CK_INFRA_133M_HCK, "infra_133m_hck", CK_TOP_SYSAXI, 1, 1), - INFRA_FACTOR(CK_INFRA_133M_PHCK, "infra_133m_phck", CK_INFRA_133M_HCK, - 1, 1), - INFRA_FACTOR(CK_INFRA_66M_PHCK, "infra_66m_phck", CK_INFRA_133M_HCK, 1, - 1), - TOP_FACTOR(CK_INFRA_FAUD_L_O, "infra_faud_l_o", CK_TOP_AUD_L, 1, 1), - TOP_FACTOR(CK_INFRA_FAUD_AUD_O, "infra_faud_aud_o", CK_TOP_A1SYS, 1, 1), - TOP_FACTOR(CK_INFRA_FAUD_EG2_O, "infra_faud_eg2_o", CK_TOP_A_TUNER, 1, - 1), - TOP_FACTOR(CK_INFRA_I2C_O, "infra_i2c_o", CK_TOP_I2C_BCK, 1, 1), - TOP_FACTOR(CK_INFRA_UART_O0, "infra_uart_o0", CK_TOP_UART_SEL, 1, 1), - TOP_FACTOR(CK_INFRA_UART_O1, "infra_uart_o1", CK_TOP_UART_SEL, 1, 1), - TOP_FACTOR(CK_INFRA_UART_O2, "infra_uart_o2", CK_TOP_UART_SEL, 1, 1), - TOP_FACTOR(CK_INFRA_NFI_O, "infra_nfi_o", CK_TOP_NFI1X, 1, 1), - TOP_FACTOR(CK_INFRA_SPINFI_O, "infra_spinfi_o", CK_TOP_SPINFI_BCK, 1, - 1), - TOP_FACTOR(CK_INFRA_SPI0_O, "infra_spi0_o", CK_TOP_SPI, 1, 1), - TOP_FACTOR(CK_INFRA_SPI1_O, "infra_spi1_o", CK_TOP_SPIM_MST, 1, 1), - INFRA_FACTOR(CK_INFRA_LB_MUX_FRTC, "infra_lb_mux_frtc", CK_INFRA_FRTC, - 1, 1), - TOP_FACTOR(CK_INFRA_FRTC, "infra_frtc", CK_TOP_CB_RTC_32K, 1, 1), - TOP_FACTOR(CK_INFRA_FMSDC400_O, "infra_fmsdc400_o", CK_TOP_EMMC_400M, 1, - 1), - TOP_FACTOR(CK_INFRA_FMSDC2_HCK_OCC, "infra_fmsdc2_hck_occ", - CK_TOP_EMMC_250M, 1, 1), - TOP_FACTOR(CK_INFRA_PERI_133M, "infra_peri_133m", CK_TOP_SYSAXI, 1, 1), - TOP_FACTOR(CK_INFRA_USB_O, "infra_usb_o", CK_TOP_USB_REF, 1, 1), - TOP_FACTOR(CK_INFRA_USB_O_P1, "infra_usb_o_p1", CK_TOP_USB_CK_P1, 1, 1), - TOP_FACTOR(CK_INFRA_USB_FRMCNT_O, "infra_usb_frmcnt_o", - CK_TOP_USB_FRMCNT, 1, 1), - TOP_FACTOR(CK_INFRA_USB_FRMCNT_O_P1, "infra_usb_frmcnt_o_p1", - CK_TOP_USB_FRMCNT_P1, 1, 1), - TOP_FACTOR(CK_INFRA_USB_XHCI_O, "infra_usb_xhci_o", CK_TOP_USB_XHCI, 1, - 1), - TOP_FACTOR(CK_INFRA_USB_XHCI_O_P1, "infra_usb_xhci_o_p1", - CK_TOP_USB_XHCI_P1, 1, 1), - XTAL_FACTOR(CK_INFRA_USB_PIPE_O, "infra_usb_pipe_o", CLK_XTAL, 1, 1), - XTAL_FACTOR(CK_INFRA_USB_PIPE_O_P1, "infra_usb_pipe_o_p1", CLK_XTAL, 1, - 1), - XTAL_FACTOR(CK_INFRA_USB_UTMI_O, "infra_usb_utmi_o", CLK_XTAL, 1, 1), - XTAL_FACTOR(CK_INFRA_USB_UTMI_O_P1, "infra_usb_utmi_o_p1", CLK_XTAL, 1, - 1), - XTAL_FACTOR(CK_INFRA_PCIE_PIPE_OCC_P0, "infra_pcie_pipe_ck_occ_p0", - CLK_XTAL, 1, 1), - XTAL_FACTOR(CK_INFRA_PCIE_PIPE_OCC_P1, "infra_pcie_pipe_ck_occ_p1", - CLK_XTAL, 1, 1), - XTAL_FACTOR(CK_INFRA_PCIE_PIPE_OCC_P2, "infra_pcie_pipe_ck_occ_p2", - CLK_XTAL, 1, 1), - XTAL_FACTOR(CK_INFRA_PCIE_PIPE_OCC_P3, "infra_pcie_pipe_ck_occ_p3", - CLK_XTAL, 1, 1), - TOP_FACTOR(CK_INFRA_F26M_O0, "infra_f26m_o0", CK_TOP_INFRA_F26M, 1, 1), - TOP_FACTOR(CK_INFRA_F26M_O1, "infra_f26m_o1", CK_TOP_INFRA_F26M, 1, 1), - TOP_FACTOR(CK_INFRA_133M_MCK, "infra_133m_mck", CK_TOP_SYSAXI, 1, 1), - TOP_FACTOR(CK_INFRA_66M_MCK, "infra_66m_mck", CK_TOP_SYSAXI, 1, 1), - TOP_FACTOR(CK_INFRA_PERI_66M_O, "infra_peri_66m_o", CK_TOP_SYSAXI, 1, - 1), - TOP_FACTOR(CK_INFRA_USB_SYS_O, "infra_usb_sys_o", CK_TOP_USB_SYS, 1, 1), - TOP_FACTOR(CK_INFRA_USB_SYS_O_P1, "infra_usb_sys_o_p1", - CK_TOP_USB_SYS_P1, 1, 1), -}; - /* INFRASYS MUX PARENTS */ -static const int infra_mux_uart0_parents[] = { CK_INFRA_CK_F26M, - CK_INFRA_UART_O0 }; +static const int infra_mux_uart0_parents[] = { CLK_TOP_INFRA_F26M_SEL, + CLK_TOP_UART_SEL }; -static const int infra_mux_uart1_parents[] = { CK_INFRA_CK_F26M, - CK_INFRA_UART_O1 }; +static const int infra_mux_uart1_parents[] = { CLK_TOP_INFRA_F26M_SEL, + CLK_TOP_UART_SEL }; -static const int infra_mux_uart2_parents[] = { CK_INFRA_CK_F26M, - CK_INFRA_UART_O2 }; +static const int infra_mux_uart2_parents[] = { CLK_TOP_INFRA_F26M_SEL, + CLK_TOP_UART_SEL }; -static const int infra_mux_spi0_parents[] = { CK_INFRA_I2C_O, CK_INFRA_SPI0_O }; +static const int infra_mux_spi0_parents[] = { CLK_TOP_I2C_SEL, CLK_TOP_SPI_SEL }; -static const int infra_mux_spi1_parents[] = { CK_INFRA_I2C_O, CK_INFRA_SPI1_O }; +static const int infra_mux_spi1_parents[] = { CLK_TOP_I2C_SEL, CLK_TOP_SPIM_MST_SEL }; -static const int infra_pwm_bck_parents[] = { CK_TOP_INFRA_F32K, - CK_INFRA_CK_F26M, CK_INFRA_66M_MCK, - CK_INFRA_PWM_O }; +static const int infra_pwm_bck_parents[] = { CLK_TOP_RTC_32P7K, + CLK_TOP_INFRA_F26M_SEL, CLK_TOP_SYSAXI_SEL, + CLK_TOP_PWM_SEL }; static const int infra_pcie_gfmux_tl_ck_o_p0_parents[] = { - CK_TOP_INFRA_F32K, CK_INFRA_CK_F26M, CK_INFRA_CK_F26M, - CK_INFRA_PCIE_OCC_P0 + CLK_TOP_RTC_32P7K, CLK_TOP_INFRA_F26M_SEL, CLK_TOP_INFRA_F26M_SEL, + CLK_TOP_PEXTP_TL_SEL }; static const int infra_pcie_gfmux_tl_ck_o_p1_parents[] = { - CK_TOP_INFRA_F32K, CK_INFRA_CK_F26M, CK_INFRA_CK_F26M, - CK_INFRA_PCIE_OCC_P1 + CLK_TOP_RTC_32P7K, CLK_TOP_INFRA_F26M_SEL, CLK_TOP_INFRA_F26M_SEL, + CLK_TOP_PEXTP_TL_P1_SEL }; static const int infra_pcie_gfmux_tl_ck_o_p2_parents[] = { - CK_TOP_INFRA_F32K, CK_INFRA_CK_F26M, CK_INFRA_CK_F26M, - CK_INFRA_PCIE_OCC_P2 + CLK_TOP_RTC_32P7K, CLK_TOP_INFRA_F26M_SEL, CLK_TOP_INFRA_F26M_SEL, + CLK_TOP_PEXTP_TL_P2_SEL }; static const int infra_pcie_gfmux_tl_ck_o_p3_parents[] = { - CK_TOP_INFRA_F32K, CK_INFRA_CK_F26M, CK_INFRA_CK_F26M, - CK_INFRA_PCIE_OCC_P3 + CLK_TOP_RTC_32P7K, CLK_TOP_INFRA_F26M_SEL, CLK_TOP_INFRA_F26M_SEL, + CLK_TOP_PEXTP_TL_P3_SEL }; #define INFRA_MUX(_id, _name, _parents, _reg, _shift, _width) \ @@ -542,51 +486,51 @@ static const int infra_pcie_gfmux_tl_ck_o_p3_parents[] = { .mux_clr_reg = _reg + 0x4, .mux_shift = _shift, \ .mux_mask = BIT(_width) - 1, .parent = _parents, \ .num_parents = ARRAY_SIZE(_parents), \ - .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_INFRASYS, \ + .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_TOPCKGEN, \ } /* INFRA MUX */ static const struct mtk_composite infracfg_mtk_mux[] = { - INFRA_MUX(CK_INFRA_MUX_UART0_SEL, "infra_mux_uart0_sel", + INFRA_MUX(CLK_INFRA_MUX_UART0_SEL, "infra_mux_uart0_sel", infra_mux_uart0_parents, 0x10, 0, 1), - INFRA_MUX(CK_INFRA_MUX_UART1_SEL, "infra_mux_uart1_sel", + INFRA_MUX(CLK_INFRA_MUX_UART1_SEL, "infra_mux_uart1_sel", infra_mux_uart1_parents, 0x10, 1, 1), - INFRA_MUX(CK_INFRA_MUX_UART2_SEL, "infra_mux_uart2_sel", + INFRA_MUX(CLK_INFRA_MUX_UART2_SEL, "infra_mux_uart2_sel", infra_mux_uart2_parents, 0x10, 2, 1), - INFRA_MUX(CK_INFRA_MUX_SPI0_SEL, "infra_mux_spi0_sel", + INFRA_MUX(CLK_INFRA_MUX_SPI0_SEL, "infra_mux_spi0_sel", infra_mux_spi0_parents, 0x10, 4, 1), - INFRA_MUX(CK_INFRA_MUX_SPI1_SEL, "infra_mux_spi1_sel", + INFRA_MUX(CLK_INFRA_MUX_SPI1_SEL, "infra_mux_spi1_sel", infra_mux_spi1_parents, 0x10, 5, 1), - INFRA_MUX(CK_INFRA_MUX_SPI2_SEL, "infra_mux_spi2_sel", + INFRA_MUX(CLK_INFRA_MUX_SPI2_SEL, "infra_mux_spi2_sel", infra_mux_spi0_parents, 0x10, 6, 1), - INFRA_MUX(CK_INFRA_PWM_SEL, "infra_pwm_sel", infra_pwm_bck_parents, + INFRA_MUX(CLK_INFRA_PWM_SEL, "infra_pwm_sel", infra_pwm_bck_parents, 0x10, 14, 2), - INFRA_MUX(CK_INFRA_PWM_CK1_SEL, "infra_pwm_ck1_sel", + INFRA_MUX(CLK_INFRA_PWM_CK1_SEL, "infra_pwm_ck1_sel", infra_pwm_bck_parents, 0x10, 16, 2), - INFRA_MUX(CK_INFRA_PWM_CK2_SEL, "infra_pwm_ck2_sel", + INFRA_MUX(CLK_INFRA_PWM_CK2_SEL, "infra_pwm_ck2_sel", infra_pwm_bck_parents, 0x10, 18, 2), - INFRA_MUX(CK_INFRA_PWM_CK3_SEL, "infra_pwm_ck3_sel", + INFRA_MUX(CLK_INFRA_PWM_CK3_SEL, "infra_pwm_ck3_sel", infra_pwm_bck_parents, 0x10, 20, 2), - INFRA_MUX(CK_INFRA_PWM_CK4_SEL, "infra_pwm_ck4_sel", + INFRA_MUX(CLK_INFRA_PWM_CK4_SEL, "infra_pwm_ck4_sel", infra_pwm_bck_parents, 0x10, 22, 2), - INFRA_MUX(CK_INFRA_PWM_CK5_SEL, "infra_pwm_ck5_sel", + INFRA_MUX(CLK_INFRA_PWM_CK5_SEL, "infra_pwm_ck5_sel", infra_pwm_bck_parents, 0x10, 24, 2), - INFRA_MUX(CK_INFRA_PWM_CK6_SEL, "infra_pwm_ck6_sel", + INFRA_MUX(CLK_INFRA_PWM_CK6_SEL, "infra_pwm_ck6_sel", infra_pwm_bck_parents, 0x10, 26, 2), - INFRA_MUX(CK_INFRA_PWM_CK7_SEL, "infra_pwm_ck7_sel", + INFRA_MUX(CLK_INFRA_PWM_CK7_SEL, "infra_pwm_ck7_sel", infra_pwm_bck_parents, 0x10, 28, 2), - INFRA_MUX(CK_INFRA_PWM_CK8_SEL, "infra_pwm_ck8_sel", + INFRA_MUX(CLK_INFRA_PWM_CK8_SEL, "infra_pwm_ck8_sel", infra_pwm_bck_parents, 0x10, 30, 2), - INFRA_MUX(CK_INFRA_PCIE_GFMUX_TL_O_P0_SEL, + INFRA_MUX(CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL, "infra_pcie_gfmux_tl_o_p0_sel", infra_pcie_gfmux_tl_ck_o_p0_parents, 0x20, 0, 2), - INFRA_MUX(CK_INFRA_PCIE_GFMUX_TL_O_P1_SEL, + INFRA_MUX(CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL, "infra_pcie_gfmux_tl_o_p1_sel", infra_pcie_gfmux_tl_ck_o_p1_parents, 0x20, 2, 2), - INFRA_MUX(CK_INFRA_PCIE_GFMUX_TL_O_P2_SEL, + INFRA_MUX(CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL, "infra_pcie_gfmux_tl_o_p2_sel", infra_pcie_gfmux_tl_ck_o_p2_parents, 0x20, 4, 2), - INFRA_MUX(CK_INFRA_PCIE_GFMUX_TL_O_P3_SEL, + INFRA_MUX(CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL, "infra_pcie_gfmux_tl_o_p3_sel", infra_pcie_gfmux_tl_ck_o_p3_parents, 0x20, 6, 2), }; @@ -615,218 +559,238 @@ static const struct mtk_gate_regs infra_3_cg_regs = { .sta_ofs = 0x68, }; -#define GATE_INFRA0(_id, _name, _parent, _shift) \ +#define GATE_INFRA0(_id, _name, _parent, _shift, _flags) \ { \ .id = _id, .parent = _parent, .regs = &infra_0_cg_regs, \ .shift = _shift, \ - .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \ + .flags = _flags, \ } +#define GATE_INFRA0_INFRA(_id, _name, _parent, _shift) \ + GATE_INFRA0(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS) +#define GATE_INFRA0_TOP(_id, _name, _parent, _shift) \ + GATE_INFRA0(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) -#define GATE_INFRA1(_id, _name, _parent, _shift) \ +#define GATE_INFRA1(_id, _name, _parent, _shift, _flags) \ { \ .id = _id, .parent = _parent, .regs = &infra_1_cg_regs, \ .shift = _shift, \ - .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \ + .flags = _flags, \ } +#define GATE_INFRA1_INFRA(_id, _name, _parent, _shift) \ + GATE_INFRA1(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS) +#define GATE_INFRA1_TOP(_id, _name, _parent, _shift) \ + GATE_INFRA1(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) -#define GATE_INFRA2(_id, _name, _parent, _shift) \ +#define GATE_INFRA2(_id, _name, _parent, _shift, _flags) \ { \ .id = _id, .parent = _parent, .regs = &infra_2_cg_regs, \ .shift = _shift, \ - .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \ + .flags = _flags, \ } +#define GATE_INFRA2_INFRA(_id, _name, _parent, _shift) \ + GATE_INFRA2(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS) +#define GATE_INFRA2_TOP(_id, _name, _parent, _shift) \ + GATE_INFRA2(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) -#define GATE_INFRA3(_id, _name, _parent, _shift) \ +#define GATE_INFRA3(_id, _name, _parent, _shift, _flags) \ { \ .id = _id, .parent = _parent, .regs = &infra_3_cg_regs, \ .shift = _shift, \ - .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \ + .flags = _flags, \ } +#define GATE_INFRA3_INFRA(_id, _name, _parent, _shift) \ + GATE_INFRA3(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS) +#define GATE_INFRA3_TOP(_id, _name, _parent, _shift) \ + GATE_INFRA3(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) +#define GATE_INFRA3_XTAL(_id, _name, _parent, _shift) \ + GATE_INFRA3(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_XTAL) /* INFRA GATE */ static const struct mtk_gate infracfg_mtk_gates[] = { - GATE_INFRA1(CK_INFRA_66M_GPT_BCK, "infra_hf_66m_gpt_bck", - CK_INFRA_66M_MCK, 0), - GATE_INFRA1(CK_INFRA_66M_PWM_HCK, "infra_hf_66m_pwm_hck", - CK_INFRA_66M_MCK, 1), - GATE_INFRA1(CK_INFRA_66M_PWM_BCK, "infra_hf_66m_pwm_bck", - CK_INFRA_PWM_SEL, 2), - GATE_INFRA1(CK_INFRA_66M_PWM_CK1, "infra_hf_66m_pwm_ck1", - CK_INFRA_PWM_CK1_SEL, 3), - GATE_INFRA1(CK_INFRA_66M_PWM_CK2, "infra_hf_66m_pwm_ck2", - CK_INFRA_PWM_CK2_SEL, 4), - GATE_INFRA1(CK_INFRA_66M_PWM_CK3, "infra_hf_66m_pwm_ck3", - CK_INFRA_PWM_CK3_SEL, 5), - GATE_INFRA1(CK_INFRA_66M_PWM_CK4, "infra_hf_66m_pwm_ck4", - CK_INFRA_PWM_CK4_SEL, 6), - GATE_INFRA1(CK_INFRA_66M_PWM_CK5, "infra_hf_66m_pwm_ck5", - CK_INFRA_PWM_CK5_SEL, 7), - GATE_INFRA1(CK_INFRA_66M_PWM_CK6, "infra_hf_66m_pwm_ck6", - CK_INFRA_PWM_CK6_SEL, 8), - GATE_INFRA1(CK_INFRA_66M_PWM_CK7, "infra_hf_66m_pwm_ck7", - CK_INFRA_PWM_CK7_SEL, 9), - GATE_INFRA1(CK_INFRA_66M_PWM_CK8, "infra_hf_66m_pwm_ck8", - CK_INFRA_PWM_CK8_SEL, 10), - GATE_INFRA1(CK_INFRA_133M_CQDMA_BCK, "infra_hf_133m_cqdma_bck", - CK_INFRA_133M_MCK, 12), - GATE_INFRA1(CK_INFRA_66M_AUD_SLV_BCK, "infra_66m_aud_slv_bck", - CK_INFRA_66M_PHCK, 13), - GATE_INFRA1(CK_INFRA_AUD_26M, "infra_f_faud_26m", CK_INFRA_CK_F26M, 14), - GATE_INFRA1(CK_INFRA_AUD_L, "infra_f_faud_l", CK_INFRA_FAUD_L_O, 15), - GATE_INFRA1(CK_INFRA_AUD_AUD, "infra_f_aud_aud", CK_INFRA_FAUD_AUD_O, - 16), - GATE_INFRA1(CK_INFRA_AUD_EG2, "infra_f_faud_eg2", CK_INFRA_FAUD_EG2_O, - 18), - GATE_INFRA1(CK_INFRA_DRAMC_F26M, "infra_dramc_f26m", CK_INFRA_CK_F26M, - 19), - GATE_INFRA1(CK_INFRA_133M_DBG_ACKM, "infra_hf_133m_dbg_ackm", - CK_INFRA_133M_MCK, 20), - GATE_INFRA1(CK_INFRA_66M_AP_DMA_BCK, "infra_66m_ap_dma_bck", - CK_INFRA_66M_MCK, 21), - GATE_INFRA1(CK_INFRA_66M_SEJ_BCK, "infra_hf_66m_sej_bck", - CK_INFRA_66M_MCK, 29), - GATE_INFRA1(CK_INFRA_PRE_CK_SEJ_F13M, "infra_pre_ck_sej_f13m", - CK_INFRA_CK_F26M, 30), - GATE_INFRA1(CK_INFRA_66M_TRNG, "infra_hf_66m_trng", CK_INFRA_PERI_66M_O, - 31), - GATE_INFRA2(CK_INFRA_26M_THERM_SYSTEM, "infra_hf_26m_therm_system", - CK_INFRA_CK_F26M, 0), - GATE_INFRA2(CK_INFRA_I2C_BCK, "infra_i2c_bck", CK_INFRA_I2C_O, 1), - GATE_INFRA2(CK_INFRA_66M_UART0_PCK, "infra_hf_66m_uart0_pck", - CK_INFRA_66M_MCK, 3), - GATE_INFRA2(CK_INFRA_66M_UART1_PCK, "infra_hf_66m_uart1_pck", - CK_INFRA_66M_MCK, 4), - GATE_INFRA2(CK_INFRA_66M_UART2_PCK, "infra_hf_66m_uart2_pck", - CK_INFRA_66M_MCK, 5), - GATE_INFRA2(CK_INFRA_52M_UART0_CK, "infra_f_52m_uart0", - CK_INFRA_MUX_UART0_SEL, 3), - GATE_INFRA2(CK_INFRA_52M_UART1_CK, "infra_f_52m_uart1", - CK_INFRA_MUX_UART1_SEL, 4), - GATE_INFRA2(CK_INFRA_52M_UART2_CK, "infra_f_52m_uart2", - CK_INFRA_MUX_UART2_SEL, 5), - GATE_INFRA2(CK_INFRA_NFI, "infra_f_fnfi", CK_INFRA_NFI_O, 9), - GATE_INFRA2(CK_INFRA_SPINFI, "infra_f_fspinfi", CK_INFRA_SPINFI_O, 10), - GATE_INFRA2(CK_INFRA_66M_NFI_HCK, "infra_hf_66m_nfi_hck", - CK_INFRA_66M_MCK, 11), - GATE_INFRA2(CK_INFRA_104M_SPI0, "infra_hf_104m_spi0", - CK_INFRA_MUX_SPI0_SEL, 12), - GATE_INFRA2(CK_INFRA_104M_SPI1, "infra_hf_104m_spi1", - CK_INFRA_MUX_SPI1_SEL, 13), - GATE_INFRA2(CK_INFRA_104M_SPI2_BCK, "infra_hf_104m_spi2_bck", - CK_INFRA_MUX_SPI2_SEL, 14), - GATE_INFRA2(CK_INFRA_66M_SPI0_HCK, "infra_hf_66m_spi0_hck", - CK_INFRA_66M_MCK, 15), - GATE_INFRA2(CK_INFRA_66M_SPI1_HCK, "infra_hf_66m_spi1_hck", - CK_INFRA_66M_MCK, 16), - GATE_INFRA2(CK_INFRA_66M_SPI2_HCK, "infra_hf_66m_spi2_hck", - CK_INFRA_66M_MCK, 17), - GATE_INFRA2(CK_INFRA_66M_FLASHIF_AXI, "infra_hf_66m_flashif_axi", - CK_INFRA_66M_MCK, 18), - GATE_INFRA2(CK_INFRA_RTC, "infra_f_frtc", CK_INFRA_LB_MUX_FRTC, 19), - GATE_INFRA2(CK_INFRA_26M_ADC_BCK, "infra_f_26m_adc_bck", - CK_INFRA_F26M_O1, 20), - GATE_INFRA2(CK_INFRA_RC_ADC, "infra_f_frc_adc", CK_INFRA_26M_ADC_BCK, - 21), - GATE_INFRA2(CK_INFRA_MSDC400, "infra_f_fmsdc400", CK_INFRA_FMSDC400_O, - 22), - GATE_INFRA2(CK_INFRA_MSDC2_HCK, "infra_f_fmsdc2_hck", - CK_INFRA_FMSDC2_HCK_OCC, 23), - GATE_INFRA2(CK_INFRA_133M_MSDC_0_HCK, "infra_hf_133m_msdc_0_hck", - CK_INFRA_PERI_133M, 24), - GATE_INFRA2(CK_INFRA_66M_MSDC_0_HCK, "infra_66m_msdc_0_hck", - CK_INFRA_66M_PHCK, 25), - GATE_INFRA2(CK_INFRA_133M_CPUM_BCK, "infra_hf_133m_cpum_bck", - CK_INFRA_133M_MCK, 26), - GATE_INFRA2(CK_INFRA_BIST2FPC, "infra_hf_fbist2fpc", CK_INFRA_NFI_O, - 27), - GATE_INFRA2(CK_INFRA_I2C_X16W_MCK_CK_P1, "infra_hf_i2c_x16w_mck_ck_p1", - CK_INFRA_133M_MCK, 29), - GATE_INFRA2(CK_INFRA_I2C_X16W_PCK_CK_P1, "infra_hf_i2c_x16w_pck_ck_p1", - CK_INFRA_66M_PHCK, 31), - GATE_INFRA3(CK_INFRA_133M_USB_HCK, "infra_133m_usb_hck", - CK_INFRA_133M_PHCK, 0), - GATE_INFRA3(CK_INFRA_133M_USB_HCK_CK_P1, "infra_133m_usb_hck_ck_p1", - CK_INFRA_133M_PHCK, 1), - GATE_INFRA3(CK_INFRA_66M_USB_HCK, "infra_66m_usb_hck", - CK_INFRA_66M_PHCK, 2), - GATE_INFRA3(CK_INFRA_66M_USB_HCK_CK_P1, "infra_66m_usb_hck_ck_p1", - CK_INFRA_66M_PHCK, 3), - GATE_INFRA3(CK_INFRA_USB_SYS, "infra_usb_sys", CK_INFRA_USB_SYS_O, 4), - GATE_INFRA3(CK_INFRA_USB_SYS_CK_P1, "infra_usb_sys_ck_p1", - CK_INFRA_USB_SYS_O_P1, 5), - GATE_INFRA3(CK_INFRA_USB_REF, "infra_usb_ref", CK_INFRA_USB_O, 6), - GATE_INFRA3(CK_INFRA_USB_CK_P1, "infra_usb_ck_p1", CK_INFRA_USB_O_P1, - 7), - GATE_INFRA3(CK_INFRA_USB_FRMCNT, "infra_usb_frmcnt", - CK_INFRA_USB_FRMCNT_O, 8), - GATE_INFRA3(CK_INFRA_USB_FRMCNT_CK_P1, "infra_usb_frmcnt_ck_p1", - CK_INFRA_USB_FRMCNT_O_P1, 9), - GATE_INFRA3(CK_INFRA_USB_PIPE, "infra_usb_pipe", CK_INFRA_USB_PIPE_O, - 10), - GATE_INFRA3(CK_INFRA_USB_PIPE_CK_P1, "infra_usb_pipe_ck_p1", - CK_INFRA_USB_PIPE_O_P1, 11), - GATE_INFRA3(CK_INFRA_USB_UTMI, "infra_usb_utmi", CK_INFRA_USB_UTMI_O, - 12), - GATE_INFRA3(CK_INFRA_USB_UTMI_CK_P1, "infra_usb_utmi_ck_p1", - CK_INFRA_USB_UTMI_O_P1, 13), - GATE_INFRA3(CK_INFRA_USB_XHCI, "infra_usb_xhci", CK_INFRA_USB_XHCI_O, - 14), - GATE_INFRA3(CK_INFRA_USB_XHCI_CK_P1, "infra_usb_xhci_ck_p1", - CK_INFRA_USB_XHCI_O_P1, 15), - GATE_INFRA3(CK_INFRA_PCIE_GFMUX_TL_P0, "infra_pcie_gfmux_tl_ck_p0", - CK_INFRA_PCIE_GFMUX_TL_O_P0_SEL, 20), - GATE_INFRA3(CK_INFRA_PCIE_GFMUX_TL_P1, "infra_pcie_gfmux_tl_ck_p1", - CK_INFRA_PCIE_GFMUX_TL_O_P1_SEL, 21), - GATE_INFRA3(CK_INFRA_PCIE_GFMUX_TL_P2, "infra_pcie_gfmux_tl_ck_p2", - CK_INFRA_PCIE_GFMUX_TL_O_P2_SEL, 22), - GATE_INFRA3(CK_INFRA_PCIE_GFMUX_TL_P3, "infra_pcie_gfmux_tl_ck_p3", - CK_INFRA_PCIE_GFMUX_TL_O_P3_SEL, 23), - GATE_INFRA3(CK_INFRA_PCIE_PIPE_P0, "infra_pcie_pipe_ck_p0", - CK_INFRA_PCIE_PIPE_OCC_P0, 24), - GATE_INFRA3(CK_INFRA_PCIE_PIPE_P1, "infra_pcie_pipe_ck_p1", - CK_INFRA_PCIE_PIPE_OCC_P1, 25), - GATE_INFRA3(CK_INFRA_PCIE_PIPE_P2, "infra_pcie_pipe_ck_p2", - CK_INFRA_PCIE_PIPE_OCC_P2, 26), - GATE_INFRA3(CK_INFRA_PCIE_PIPE_P3, "infra_pcie_pipe_ck_p3", - CK_INFRA_PCIE_PIPE_OCC_P3, 27), - GATE_INFRA3(CK_INFRA_133M_PCIE_CK_P0, "infra_133m_pcie_ck_p0", - CK_INFRA_133M_PHCK, 28), - GATE_INFRA3(CK_INFRA_133M_PCIE_CK_P1, "infra_133m_pcie_ck_p1", - CK_INFRA_133M_PHCK, 29), - GATE_INFRA3(CK_INFRA_133M_PCIE_CK_P2, "infra_133m_pcie_ck_p2", - CK_INFRA_133M_PHCK, 30), - GATE_INFRA3(CK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3", - CK_INFRA_133M_PHCK, 31), - GATE_INFRA0(CK_INFRA_PCIE_PERI_26M_CK_P0, - "infra_pcie_peri_ck_26m_ck_p0", CK_INFRA_F26M_O0, 7), - GATE_INFRA0(CK_INFRA_PCIE_PERI_26M_CK_P1, - "infra_pcie_peri_ck_26m_ck_p1", CK_INFRA_F26M_O0, 8), - GATE_INFRA0(CK_INFRA_PCIE_PERI_26M_CK_P2, - "infra_pcie_peri_ck_26m_ck_p2", CK_INFRA_F26M_O0, 9), - GATE_INFRA0(CK_INFRA_PCIE_PERI_26M_CK_P3, - "infra_pcie_peri_ck_26m_ck_p3", CK_INFRA_F26M_O0, 10), + GATE_INFRA0_TOP(CLK_INFRA_PCIE_PERI_26M_CK_P0, + "infra_pcie_peri_ck_26m_ck_p0", CLK_TOP_INFRA_F26M_SEL, 7), + GATE_INFRA0_TOP(CLK_INFRA_PCIE_PERI_26M_CK_P1, + "infra_pcie_peri_ck_26m_ck_p1", CLK_TOP_INFRA_F26M_SEL, 8), + GATE_INFRA0_INFRA(CLK_INFRA_PCIE_PERI_26M_CK_P2, + "infra_pcie_peri_ck_26m_ck_p2", CLK_INFRA_PCIE_PERI_26M_CK_P3, 9), + GATE_INFRA0_TOP(CLK_INFRA_PCIE_PERI_26M_CK_P3, + "infra_pcie_peri_ck_26m_ck_p3", CLK_TOP_INFRA_F26M_SEL, 10), + GATE_INFRA1_TOP(CLK_INFRA_66M_GPT_BCK, "infra_hf_66m_gpt_bck", + CLK_TOP_SYSAXI_SEL, 0), + GATE_INFRA1_TOP(CLK_INFRA_66M_PWM_HCK, "infra_hf_66m_pwm_hck", + CLK_TOP_SYSAXI_SEL, 1), + GATE_INFRA1_INFRA(CLK_INFRA_66M_PWM_BCK, "infra_hf_66m_pwm_bck", + CLK_INFRA_PWM_SEL, 2), + GATE_INFRA1_INFRA(CLK_INFRA_66M_PWM_CK1, "infra_hf_66m_pwm_ck1", + CLK_INFRA_PWM_CK1_SEL, 3), + GATE_INFRA1_INFRA(CLK_INFRA_66M_PWM_CK2, "infra_hf_66m_pwm_ck2", + CLK_INFRA_PWM_CK2_SEL, 4), + GATE_INFRA1_INFRA(CLK_INFRA_66M_PWM_CK3, "infra_hf_66m_pwm_ck3", + CLK_INFRA_PWM_CK3_SEL, 5), + GATE_INFRA1_INFRA(CLK_INFRA_66M_PWM_CK4, "infra_hf_66m_pwm_ck4", + CLK_INFRA_PWM_CK4_SEL, 6), + GATE_INFRA1_INFRA(CLK_INFRA_66M_PWM_CK5, "infra_hf_66m_pwm_ck5", + CLK_INFRA_PWM_CK5_SEL, 7), + GATE_INFRA1_INFRA(CLK_INFRA_66M_PWM_CK6, "infra_hf_66m_pwm_ck6", + CLK_INFRA_PWM_CK6_SEL, 8), + GATE_INFRA1_INFRA(CLK_INFRA_66M_PWM_CK7, "infra_hf_66m_pwm_ck7", + CLK_INFRA_PWM_CK7_SEL, 9), + GATE_INFRA1_INFRA(CLK_INFRA_66M_PWM_CK8, "infra_hf_66m_pwm_ck8", + CLK_INFRA_PWM_CK8_SEL, 10), + GATE_INFRA1_TOP(CLK_INFRA_133M_CQDMA_BCK, "infra_hf_133m_cqdma_bck", + CLK_TOP_SYSAXI_SEL, 12), + GATE_INFRA1_TOP(CLK_INFRA_66M_AUD_SLV_BCK, "infra_66m_aud_slv_bck", + CLK_TOP_SYSAXI_SEL, 13), + GATE_INFRA1_TOP(CLK_INFRA_AUD_26M, "infra_f_faud_26m", CLK_TOP_INFRA_F26M_SEL, 14), + GATE_INFRA1_TOP(CLK_INFRA_AUD_L, "infra_f_faud_l", CLK_TOP_AUD_L_SEL, 15), + GATE_INFRA1_TOP(CLK_INFRA_AUD_AUD, "infra_f_aud_aud", CLK_TOP_A1SYS_SEL, + 16), + GATE_INFRA1_TOP(CLK_INFRA_AUD_EG2, "infra_f_faud_eg2", CLK_TOP_A_TUNER_SEL, + 18), + GATE_INFRA1_TOP(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m", CLK_TOP_INFRA_F26M_SEL, + 19), + GATE_INFRA1_TOP(CLK_INFRA_133M_DBG_ACKM, "infra_hf_133m_dbg_ackm", + CLK_TOP_SYSAXI_SEL, 20), + GATE_INFRA1_TOP(CLK_INFRA_66M_AP_DMA_BCK, "infra_66m_ap_dma_bck", + CLK_TOP_SYSAXI_SEL, 21), + GATE_INFRA1_TOP(CLK_INFRA_66M_SEJ_BCK, "infra_hf_66m_sej_bck", + CLK_TOP_SYSAXI_SEL, 29), + GATE_INFRA1_TOP(CLK_INFRA_PRE_CK_SEJ_F13M, "infra_pre_ck_sej_f13m", + CLK_TOP_INFRA_F26M_SEL, 30), + /* GATE_INFRA1_TOP(CLK_INFRA_66M_TRNG, "infra_hf_66m_trng", CLK_TOP_SYSAXI_SEL, + 31), */ + GATE_INFRA2_TOP(CLK_INFRA_26M_THERM_SYSTEM, "infra_hf_26m_therm_system", + CLK_TOP_INFRA_F26M_SEL, 0), + GATE_INFRA2_TOP(CLK_INFRA_I2C_BCK, "infra_i2c_bck", CLK_TOP_I2C_SEL, 1), + /* GATE_INFRA2_TOP(CLK_INFRA_66M_UART0_PCK, "infra_hf_66m_uart0_pck", + CLK_TOP_SYSAXI_SEL, 3), */ + /* GATE_INFRA2_TOP(CLK_INFRA_66M_UART1_PCK, "infra_hf_66m_uart1_pck", + CLK_TOP_SYSAXI_SEL, 4), */ + /* GATE_INFRA2_TOP(CLK_INFRA_66M_UART2_PCK, "infra_hf_66m_uart2_pck", + CLK_TOP_SYSAXI_SEL, 5), */ + GATE_INFRA2_INFRA(CLK_INFRA_52M_UART0_CK, "infra_f_52m_uart0", + CLK_INFRA_MUX_UART0_SEL, 3), + GATE_INFRA2_INFRA(CLK_INFRA_52M_UART1_CK, "infra_f_52m_uart1", + CLK_INFRA_MUX_UART1_SEL, 4), + GATE_INFRA2_INFRA(CLK_INFRA_52M_UART2_CK, "infra_f_52m_uart2", + CLK_INFRA_MUX_UART2_SEL, 5), + GATE_INFRA2_TOP(CLK_INFRA_NFI, "infra_f_fnfi", CLK_TOP_NFI1X_SEL, 9), + GATE_INFRA2_TOP(CLK_INFRA_SPINFI, "infra_f_fspinfi", CLK_TOP_SPINFI_SEL, 10), + GATE_INFRA2_TOP(CLK_INFRA_66M_NFI_HCK, "infra_hf_66m_nfi_hck", + CLK_TOP_SYSAXI_SEL, 11), + GATE_INFRA2_INFRA(CLK_INFRA_104M_SPI0, "infra_hf_104m_spi0", + CLK_INFRA_MUX_SPI0_SEL, 12), + GATE_INFRA2_INFRA(CLK_INFRA_104M_SPI1, "infra_hf_104m_spi1", + CLK_INFRA_MUX_SPI1_SEL, 13), + GATE_INFRA2_INFRA(CLK_INFRA_104M_SPI2_BCK, "infra_hf_104m_spi2_bck", + CLK_INFRA_MUX_SPI2_SEL, 14), + GATE_INFRA2_TOP(CLK_INFRA_66M_SPI0_HCK, "infra_hf_66m_spi0_hck", + CLK_TOP_SYSAXI_SEL, 15), + GATE_INFRA2_TOP(CLK_INFRA_66M_SPI1_HCK, "infra_hf_66m_spi1_hck", + CLK_TOP_SYSAXI_SEL, 16), + GATE_INFRA2_TOP(CLK_INFRA_66M_SPI2_HCK, "infra_hf_66m_spi2_hck", + CLK_TOP_SYSAXI_SEL, 17), + GATE_INFRA2_TOP(CLK_INFRA_66M_FLASHIF_AXI, "infra_hf_66m_flashif_axi", + CLK_TOP_SYSAXI_SEL, 18), + GATE_INFRA2_TOP(CLK_INFRA_RTC, "infra_f_frtc", CLK_TOP_RTC_32K, 19), + GATE_INFRA2_TOP(CLK_INFRA_26M_ADC_BCK, "infra_f_26m_adc_bck", + CLK_TOP_INFRA_F26M_SEL, 20), + GATE_INFRA2_INFRA(CLK_INFRA_RC_ADC, "infra_f_frc_adc", CLK_INFRA_26M_ADC_BCK, + 21), + GATE_INFRA2_TOP(CLK_INFRA_MSDC400, "infra_f_fmsdc400", CLK_TOP_EMMC_400M_SEL, + 22), + GATE_INFRA2_TOP(CLK_INFRA_MSDC2_HCK, "infra_f_fmsdc2_hck", + CLK_TOP_EMMC_250M_SEL, 23), + GATE_INFRA2_TOP(CLK_INFRA_133M_MSDC_0_HCK, "infra_hf_133m_msdc_0_hck", + CLK_TOP_SYSAXI_SEL, 24), + GATE_INFRA2_TOP(CLK_INFRA_66M_MSDC_0_HCK, "infra_66m_msdc_0_hck", + CLK_TOP_SYSAXI_SEL, 25), + GATE_INFRA2_TOP(CLK_INFRA_133M_CPUM_BCK, "infra_hf_133m_cpum_bck", + CLK_TOP_SYSAXI_SEL, 26), + GATE_INFRA2_TOP(CLK_INFRA_BIST2FPC, "infra_hf_fbist2fpc", CLK_TOP_NFI1X_SEL, + 27), + GATE_INFRA2_TOP(CLK_INFRA_I2C_X16W_MCK_CK_P1, "infra_hf_i2c_x16w_mck_ck_p1", + CLK_TOP_SYSAXI_SEL, 29), + GATE_INFRA2_TOP(CLK_INFRA_I2C_X16W_PCK_CK_P1, "infra_hf_i2c_x16w_pck_ck_p1", + CLK_TOP_SYSAXI_SEL, 31), + GATE_INFRA3_TOP(CLK_INFRA_133M_USB_HCK, "infra_133m_usb_hck", + CLK_TOP_SYSAXI_SEL, 0), + GATE_INFRA3_TOP(CLK_INFRA_133M_USB_HCK_CK_P1, "infra_133m_usb_hck_ck_p1", + CLK_TOP_SYSAXI_SEL, 1), + GATE_INFRA3_TOP(CLK_INFRA_66M_USB_HCK, "infra_66m_usb_hck", + CLK_TOP_SYSAXI_SEL, 2), + GATE_INFRA3_TOP(CLK_INFRA_66M_USB_HCK_CK_P1, "infra_66m_usb_hck_ck_p1", + CLK_TOP_SYSAXI_SEL, 3), + GATE_INFRA3_TOP(CLK_INFRA_USB_SYS, "infra_usb_sys", CLK_TOP_USB_SYS_SEL, 4), + GATE_INFRA3_TOP(CLK_INFRA_USB_SYS_CK_P1, "infra_usb_sys_ck_p1", + CLK_TOP_USB_SYS_P1_SEL, 5), + GATE_INFRA3_XTAL(CLK_INFRA_USB_REF, "infra_usb_ref", CLK_XTAL, 6), + GATE_INFRA3_XTAL(CLK_INFRA_USB_CK_P1, "infra_usb_ck_p1", CLK_XTAL, + 7), + GATE_INFRA3_TOP(CLK_INFRA_USB_FRMCNT, "infra_usb_frmcnt", + CLK_TOP_USB_FRMCNT_SEL, 8), + GATE_INFRA3_TOP(CLK_INFRA_USB_FRMCNT_CK_P1, "infra_usb_frmcnt_ck_p1", + CLK_TOP_USB_FRMCNT_P1_SEL, 9), + GATE_INFRA3_XTAL(CLK_INFRA_USB_PIPE, "infra_usb_pipe", CLK_XTAL, + 10), + GATE_INFRA3_XTAL(CLK_INFRA_USB_PIPE_CK_P1, "infra_usb_pipe_ck_p1", + CLK_XTAL, 11), + GATE_INFRA3_XTAL(CLK_INFRA_USB_UTMI, "infra_usb_utmi", CLK_XTAL, + 12), + GATE_INFRA3_XTAL(CLK_INFRA_USB_UTMI_CK_P1, "infra_usb_utmi_ck_p1", + CLK_XTAL, 13), + GATE_INFRA3_TOP(CLK_INFRA_USB_XHCI, "infra_usb_xhci", CLK_TOP_USB_XHCI_SEL, + 14), + GATE_INFRA3_TOP(CLK_INFRA_USB_XHCI_CK_P1, "infra_usb_xhci_ck_p1", + CLK_TOP_USB_XHCI_P1_SEL, 15), + GATE_INFRA3_INFRA(CLK_INFRA_PCIE_GFMUX_TL_P0, "infra_pcie_gfmux_tl_ck_p0", + CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL, 20), + GATE_INFRA3_INFRA(CLK_INFRA_PCIE_GFMUX_TL_P1, "infra_pcie_gfmux_tl_ck_p1", + CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL, 21), + GATE_INFRA3_INFRA(CLK_INFRA_PCIE_GFMUX_TL_P2, "infra_pcie_gfmux_tl_ck_p2", + CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL, 22), + GATE_INFRA3_INFRA(CLK_INFRA_PCIE_GFMUX_TL_P3, "infra_pcie_gfmux_tl_ck_p3", + CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL, 23), + GATE_INFRA3_XTAL(CLK_INFRA_PCIE_PIPE_P0, "infra_pcie_pipe_ck_p0", + CLK_XTAL, 24), + GATE_INFRA3_XTAL(CLK_INFRA_PCIE_PIPE_P1, "infra_pcie_pipe_ck_p1", + CLK_XTAL, 25), + GATE_INFRA3_XTAL(CLK_INFRA_PCIE_PIPE_P2, "infra_pcie_pipe_ck_p2", + CLK_XTAL, 26), + GATE_INFRA3_XTAL(CLK_INFRA_PCIE_PIPE_P3, "infra_pcie_pipe_ck_p3", + CLK_XTAL, 27), + GATE_INFRA3_TOP(CLK_INFRA_133M_PCIE_CK_P0, "infra_133m_pcie_ck_p0", + CLK_TOP_SYSAXI_SEL, 28), + GATE_INFRA3_TOP(CLK_INFRA_133M_PCIE_CK_P1, "infra_133m_pcie_ck_p1", + CLK_TOP_SYSAXI_SEL, 29), + GATE_INFRA3_TOP(CLK_INFRA_133M_PCIE_CK_P2, "infra_133m_pcie_ck_p2", + CLK_TOP_SYSAXI_SEL, 30), + GATE_INFRA3_TOP(CLK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3", + CLK_TOP_SYSAXI_SEL, 31), }; static const struct mtk_clk_tree mt7988_fixed_pll_clk_tree = { .fdivs_offs = ARRAY_SIZE(apmixedsys_mtk_plls), .fclks = apmixedsys_mtk_plls, + .flags = CLK_APMIXED, .xtal_rate = 40 * MHZ, }; static const struct mtk_clk_tree mt7988_topckgen_clk_tree = { - .fdivs_offs = CK_TOP_CB_CKSQ_40M, - .muxes_offs = CK_TOP_NETSYS_SEL, + .fdivs_offs = CLK_TOP_XTAL_D2, + .muxes_offs = CLK_TOP_NETSYS_SEL, + .fclks = topckgen_mtk_fixed_clks, .fdivs = topckgen_mtk_fixed_factors, .muxes = topckgen_mtk_muxes, - .flags = CLK_BYPASS_XTAL, + .flags = CLK_BYPASS_XTAL | CLK_TOPCKGEN, .xtal_rate = 40 * MHZ, }; static const struct mtk_clk_tree mt7988_infracfg_clk_tree = { - .fdivs_offs = CK_INFRA_CK_F26M, - .muxes_offs = CK_INFRA_MUX_UART0_SEL, - .fdivs = infracfg_mtk_fixed_factor, + .muxes_offs = CLK_INFRA_MUX_UART0_SEL, + .gates_offs = CLK_INFRA_PCIE_PERI_26M_CK_P0, .muxes = infracfg_mtk_mux, + .gates = infracfg_mtk_gates, .flags = CLK_BYPASS_XTAL, .xtal_rate = 40 * MHZ, }; @@ -884,20 +848,9 @@ static const struct udevice_id mt7988_infracfg_compat[] = { {} }; -static const struct udevice_id mt7988_infracfg_ao_cgs_compat[] = { - { .compatible = "mediatek,mt7988-infracfg_ao_cgs" }, - {} -}; - static int mt7988_infracfg_probe(struct udevice *dev) { - return mtk_common_clk_init(dev, &mt7988_infracfg_clk_tree); -} - -static int mt7988_infracfg_ao_cgs_probe(struct udevice *dev) -{ - return mtk_common_clk_gate_init(dev, &mt7988_infracfg_clk_tree, - infracfg_mtk_gates); + return mtk_common_clk_infrasys_init(dev, &mt7988_infracfg_clk_tree); } U_BOOT_DRIVER(mtk_clk_infracfg) = { @@ -910,16 +863,6 @@ U_BOOT_DRIVER(mtk_clk_infracfg) = { .flags = DM_FLAG_PRE_RELOC, }; -U_BOOT_DRIVER(mtk_clk_infracfg_ao_cgs) = { - .name = "mt7988-clock-infracfg_ao_cgs", - .id = UCLASS_CLK, - .of_match = mt7988_infracfg_ao_cgs_compat, - .probe = mt7988_infracfg_ao_cgs_probe, - .priv_auto = sizeof(struct mtk_cg_priv), - .ops = &mtk_clk_gate_ops, - .flags = DM_FLAG_PRE_RELOC, -}; - /* ETHDMA */ static const struct mtk_gate_regs ethdma_cg_regs = { @@ -936,7 +879,7 @@ static const struct mtk_gate_regs ethdma_cg_regs = { } static const struct mtk_gate ethdma_mtk_gate[] = { - GATE_ETHDMA(CK_ETHDMA_FE_EN, "ethdma_fe_en", CK_TOP_NETSYS_2X, 6), + GATE_ETHDMA(CLK_ETHDMA_FE_EN, "ethdma_fe_en", CLK_TOP_NETSYS_2X_SEL, 6), }; static int mt7988_ethdma_probe(struct udevice *dev) @@ -991,10 +934,10 @@ static const struct mtk_gate_regs sgmii0_cg_regs = { } static const struct mtk_gate sgmiisys_0_mtk_gate[] = { - /* connect to fake clock, so use CK_TOP_CB_CKSQ_40M as the clock parent */ - GATE_SGMII0(CK_SGM0_TX_EN, "sgm0_tx_en", CK_TOP_CB_CKSQ_40M, 2), - /* connect to fake clock, so use CK_TOP_CB_CKSQ_40M as the clock parent */ - GATE_SGMII0(CK_SGM0_RX_EN, "sgm0_rx_en", CK_TOP_CB_CKSQ_40M, 3), + /* connect to fake clock, so use CLK_TOP_XTAL as the clock parent */ + GATE_SGMII0(CLK_SGM0_TX_EN, "sgm0_tx_en", CLK_TOP_XTAL, 2), + /* connect to fake clock, so use CLK_TOP_XTAL as the clock parent */ + GATE_SGMII0(CLK_SGM0_RX_EN, "sgm0_rx_en", CLK_TOP_XTAL, 3), }; static int mt7988_sgmiisys_0_probe(struct udevice *dev) @@ -1035,10 +978,10 @@ static const struct mtk_gate_regs sgmii1_cg_regs = { } static const struct mtk_gate sgmiisys_1_mtk_gate[] = { - /* connect to fake clock, so use CK_TOP_CB_CKSQ_40M as the clock parent */ - GATE_SGMII1(CK_SGM1_TX_EN, "sgm1_tx_en", CK_TOP_CB_CKSQ_40M, 2), - /* connect to fake clock, so use CK_TOP_CB_CKSQ_40M as the clock parent */ - GATE_SGMII1(CK_SGM1_RX_EN, "sgm1_rx_en", CK_TOP_CB_CKSQ_40M, 3), + /* connect to fake clock, so use CLK_TOP_XTAL as the clock parent */ + GATE_SGMII1(CLK_SGM1_TX_EN, "sgm1_tx_en", CLK_TOP_XTAL, 2), + /* connect to fake clock, so use CLK_TOP_XTAL as the clock parent */ + GATE_SGMII1(CLK_SGM1_RX_EN, "sgm1_rx_en", CLK_TOP_XTAL, 3), }; static int mt7988_sgmiisys_1_probe(struct udevice *dev) @@ -1079,12 +1022,12 @@ static const struct mtk_gate_regs ethwarp_cg_regs = { } static const struct mtk_gate ethwarp_mtk_gate[] = { - GATE_ETHWARP(CK_ETHWARP_WOCPU2_EN, "ethwarp_wocpu2_en", - CK_TOP_NETSYS_WED_MCU, 13), - GATE_ETHWARP(CK_ETHWARP_WOCPU1_EN, "ethwarp_wocpu1_en", - CK_TOP_NETSYS_WED_MCU, 14), - GATE_ETHWARP(CK_ETHWARP_WOCPU0_EN, "ethwarp_wocpu0_en", - CK_TOP_NETSYS_WED_MCU, 15), + GATE_ETHWARP(CLK_ETHWARP_WOCPU2_EN, "ethwarp_wocpu2_en", + CLK_TOP_NETSYS_MCU_SEL, 13), + GATE_ETHWARP(CLK_ETHWARP_WOCPU1_EN, "ethwarp_wocpu1_en", + CLK_TOP_NETSYS_MCU_SEL, 14), + GATE_ETHWARP(CLK_ETHWARP_WOCPU0_EN, "ethwarp_wocpu0_en", + CLK_TOP_NETSYS_MCU_SEL, 15), }; static int mt7988_ethwarp_probe(struct udevice *dev) diff --git a/drivers/clk/mpc83xx_clk.c b/drivers/clk/mpc83xx_clk.c index a29ad0d7a68..a43fff2e7ed 100644 --- a/drivers/clk/mpc83xx_clk.c +++ b/drivers/clk/mpc83xx_clk.c @@ -358,7 +358,7 @@ static int mpc83xx_clk_probe(struct udevice *dev) gd->mem_clk = priv->speed[MPC83XX_CLK_MEM]; if (mpc83xx_has_pci(type)) - gd->pci_clk = priv->speed[MPC83XX_CLK_PCI]; + gd->arch.pci_clk = priv->speed[MPC83XX_CLK_PCI]; gd->cpu_clk = priv->speed[MPC83XX_CLK_CORE]; gd->bus_clk = priv->speed[MPC83XX_CLK_CSB]; diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 24cefebd1b2..89924041299 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -8,6 +8,7 @@ #include <dm.h> #include <dt-structs.h> #include <errno.h> +#include <handoff.h> #include <log.h> #include <malloc.h> #include <mapmem.h> @@ -1467,7 +1468,7 @@ static int rk3399_clk_probe(struct udevice *dev) init_clocks = true; #elif CONFIG_IS_ENABLED(HANDOFF) if (!(gd->flags & GD_FLG_RELOC)) { - if (!(gd->spl_handoff)) + if (!handoff_get()) init_clocks = true; } #endif diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c index 31091bb4495..888dfb7ff33 100644 --- a/drivers/ddr/fsl/main.c +++ b/drivers/ddr/fsl/main.c @@ -111,7 +111,7 @@ static int ddr_i2c_read(DEV_TYPE *dev, unsigned int addr, #if CONFIG_IS_ENABLED(DM_I2C) ret = dm_i2c_read(dev, 0, buf, len); #else - ret = i2c_read(dev->chip, addr, alen, buf, len); + ret = 0; #endif return ret; @@ -162,7 +162,6 @@ static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address) }; dev = &ldev; - i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM); #endif #ifdef CONFIG_SYS_FSL_DDR4 diff --git a/drivers/i2c/i2c_core.c b/drivers/i2c/i2c_core.c index 7c43a5546d3..cccd45027db 100644 --- a/drivers/i2c/i2c_core.c +++ b/drivers/i2c/i2c_core.c @@ -33,137 +33,8 @@ struct i2c_adapter *i2c_get_adapter(int index) return i2c_adap_p; } -#if !defined(CFG_SYS_I2C_DIRECT_BUS) -struct i2c_bus_hose i2c_bus[CFG_SYS_NUM_I2C_BUSES] = - CFG_SYS_I2C_BUSES; -#endif - DECLARE_GLOBAL_DATA_PTR; -#ifndef CFG_SYS_I2C_DIRECT_BUS -/* - * i2c_mux_set() - * ------------- - * - * This turns on the given channel on I2C multiplexer chip connected to - * a given I2C adapter directly or via other multiplexers. In the latter - * case the entire multiplexer chain must be initialized first starting - * with the one connected directly to the adapter. When disabling a chain - * muxes must be programmed in reverse order, starting with the one - * farthest from the adapter. - * - * mux_id is the multiplexer chip type from defined in i2c.h. So far only - * NXP (Philips) PCA954x multiplexers are supported. Switches are NOT - * supported (anybody uses them?) - */ - -static int i2c_mux_set(struct i2c_adapter *adap, int mux_id, int chip, - int channel) -{ - uint8_t buf; - int ret; - - /* channel < 0 - turn off the mux */ - if (channel < 0) { - buf = 0; - ret = adap->write(adap, chip, 0, 0, &buf, 1); - if (ret) - printf("%s: Could not turn off the mux.\n", __func__); - return ret; - } - - switch (mux_id) { - case I2C_MUX_PCA9540_ID: - case I2C_MUX_PCA9542_ID: - if (channel > 1) - return -1; - buf = (uint8_t)((channel & 0x01) | (1 << 2)); - break; - case I2C_MUX_PCA9544_ID: - if (channel > 3) - return -1; - buf = (uint8_t)((channel & 0x03) | (1 << 2)); - break; - case I2C_MUX_PCA9547_ID: - if (channel > 7) - return -1; - buf = (uint8_t)((channel & 0x07) | (1 << 3)); - break; - case I2C_MUX_PCA9548_ID: - if (channel > 7) - return -1; - buf = (uint8_t)(0x01 << channel); - break; - default: - printf("%s: wrong mux id: %d\n", __func__, mux_id); - return -1; - } - - ret = adap->write(adap, chip, 0, 0, &buf, 1); - if (ret) - printf("%s: could not set mux: id: %d chip: %x channel: %d\n", - __func__, mux_id, chip, channel); - return ret; -} - -static int i2c_mux_set_all(void) -{ - struct i2c_bus_hose *i2c_bus_tmp = &i2c_bus[I2C_BUS]; - int i; - - /* Connect requested bus if behind muxes */ - if (i2c_bus_tmp->next_hop[0].chip != 0) { - /* Set all muxes along the path to that bus */ - for (i = 0; i < CFG_SYS_I2C_MAX_HOPS; i++) { - int ret; - - if (i2c_bus_tmp->next_hop[i].chip == 0) - break; - - ret = i2c_mux_set(I2C_ADAP, - i2c_bus_tmp->next_hop[i].mux.id, - i2c_bus_tmp->next_hop[i].chip, - i2c_bus_tmp->next_hop[i].channel); - if (ret != 0) - return ret; - } - } - return 0; -} - -static int i2c_mux_disconnect_all(void) -{ - struct i2c_bus_hose *i2c_bus_tmp = &i2c_bus[I2C_BUS]; - int i; - uint8_t buf = 0; - - if (I2C_ADAP->init_done == 0) - return 0; - - /* Disconnect current bus (turn off muxes if any) */ - if ((i2c_bus_tmp->next_hop[0].chip != 0) && - (I2C_ADAP->init_done != 0)) { - i = CFG_SYS_I2C_MAX_HOPS; - do { - uint8_t chip; - int ret; - - chip = i2c_bus_tmp->next_hop[--i].chip; - if (chip == 0) - continue; - - ret = I2C_ADAP->write(I2C_ADAP, chip, 0, 0, &buf, 1); - if (ret != 0) { - printf("i2c: mux disconnect error\n"); - return ret; - } - } while (i > 0); - } - - return 0; -} -#endif - /* * i2c_init_bus(): * --------------- @@ -237,11 +108,6 @@ int i2c_set_bus_num(unsigned int bus) if ((bus == I2C_BUS) && (I2C_ADAP->init_done > 0)) return 0; -#ifndef CFG_SYS_I2C_DIRECT_BUS - if (bus >= CFG_SYS_NUM_I2C_BUSES) - return -1; -#endif - max = ll_entry_count(struct i2c_adapter, i2c); if (I2C_ADAPTER(bus) >= max) { printf("Error, wrong i2c adapter %d max %d possible\n", @@ -249,17 +115,10 @@ int i2c_set_bus_num(unsigned int bus) return -2; } -#ifndef CFG_SYS_I2C_DIRECT_BUS - i2c_mux_disconnect_all(); -#endif - gd->cur_i2c_bus = bus; if (I2C_ADAP->init_done == 0) i2c_init_bus(bus, I2C_ADAP->speed, I2C_ADAP->slaveaddr); -#ifndef CFG_SYS_I2C_DIRECT_BUS - i2c_mux_set_all(); -#endif return 0; } diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c index 84c0050eac0..2f3cb5908c9 100644 --- a/drivers/i2c/mxc_i2c.c +++ b/drivers/i2c/mxc_i2c.c @@ -620,6 +620,7 @@ int enable_i2c_clk(unsigned char enable, unsigned int i2c_num) __attribute__((weak, alias("__enable_i2c_clk"))); #if !CONFIG_IS_ENABLED(DM_I2C) + /* * Read data from I2C device * diff --git a/drivers/i2c/soft_i2c.c b/drivers/i2c/soft_i2c.c index 89ddf821063..79f7a320502 100644 --- a/drivers/i2c/soft_i2c.c +++ b/drivers/i2c/soft_i2c.c @@ -107,16 +107,13 @@ DECLARE_GLOBAL_DATA_PTR; /*----------------------------------------------------------------------- * Local functions */ -#if !defined(CONFIG_SYS_I2C_INIT_BOARD) static void send_reset (void); -#endif static void send_start (void); static void send_stop (void); static void send_ack (int); static int write_byte (uchar byte); static uchar read_byte (int); -#if !defined(CONFIG_SYS_I2C_INIT_BOARD) /*----------------------------------------------------------------------- * Send a reset sequence consisting of 9 clocks with the data signal high * to clock any confused device back into an idle state. Also send a @@ -144,7 +141,6 @@ static void send_reset(void) send_stop(); I2C_TRISTATE; } -#endif /*----------------------------------------------------------------------- * START: High -> Low on SDA while SCL is High @@ -277,12 +273,6 @@ static uchar read_byte(int ack) */ static void soft_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr) { -#if defined(CONFIG_SYS_I2C_INIT_BOARD) - /* call board specific i2c bus reset routine before accessing the */ - /* environment, which might be in a chip on that bus. For details */ - /* about this problem see doc/I2C_Edge_Conditions. */ - i2c_init_board(); -#else /* * WARNING: Do NOT save speed in a static variable: if the * I2C routines are called before RAM is initialized (to read @@ -290,7 +280,6 @@ static void soft_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr) * system will crash. */ send_reset (); -#endif } /*----------------------------------------------------------------------- diff --git a/drivers/mmc/ca_dw_mmc.c b/drivers/mmc/ca_dw_mmc.c index 54a2ba4795e..1af5ec0532e 100644 --- a/drivers/mmc/ca_dw_mmc.c +++ b/drivers/mmc/ca_dw_mmc.c @@ -86,7 +86,7 @@ unsigned int ca_dwmci_get_mmc_clock(struct dwmci_host *host, uint freq) clk_div = 1; } - return SD_SCLK_MAX / clk_div / (host->div + 1); + return SD_SCLK_MAX / clk_div; } static int ca_dwmmc_of_to_plat(struct udevice *dev) diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c index f4ecd7422ce..8551eac7018 100644 --- a/drivers/mmc/dw_mmc.c +++ b/drivers/mmc/dw_mmc.c @@ -20,6 +20,47 @@ #define PAGE_SIZE 4096 +/* Internal DMA Controller (IDMAC) descriptor for 32-bit addressing mode */ +struct dwmci_idmac32 { + u32 des0; /* Control descriptor */ + u32 des1; /* Buffer size */ + u32 des2; /* Buffer physical address */ + u32 des3; /* Next descriptor physical address */ +} __aligned(ARCH_DMA_MINALIGN); + +/* Internal DMA Controller (IDMAC) descriptor for 64-bit addressing mode */ +struct dwmci_idmac64 { + u32 des0; /* Control descriptor */ + u32 des1; /* Reserved */ + u32 des2; /* Buffer sizes */ + u32 des3; /* Reserved */ + u32 des4; /* Lower 32-bits of Buffer Address Pointer 1 */ + u32 des5; /* Upper 32-bits of Buffer Address Pointer 1 */ + u32 des6; /* Lower 32-bits of Next Descriptor Address */ + u32 des7; /* Upper 32-bits of Next Descriptor Address */ +} __aligned(ARCH_DMA_MINALIGN); + +/* Register offsets for DW MMC blocks with 32-bit IDMAC */ +static const struct dwmci_idmac_regs dwmci_idmac_regs32 = { + .dbaddrl = DWMCI_DBADDR, + .idsts = DWMCI_IDSTS, + .idinten = DWMCI_IDINTEN, + .dscaddrl = DWMCI_DSCADDR, + .bufaddrl = DWMCI_BUFADDR, +}; + +/* Register offsets for DW MMC blocks with 64-bit IDMAC */ +static const struct dwmci_idmac_regs dwmci_idmac_regs64 = { + .dbaddrl = DWMCI_DBADDRL, + .dbaddru = DWMCI_DBADDRU, + .idsts = DWMCI_IDSTS64, + .idinten = DWMCI_IDINTEN64, + .dscaddrl = DWMCI_DSCADDRL, + .dscaddru = DWMCI_DSCADDRU, + .bufaddrl = DWMCI_BUFADDRL, + .bufaddru = DWMCI_BUFADDRU, +}; + static int dwmci_wait_reset(struct dwmci_host *host, u32 value) { unsigned long timeout = 1000; @@ -35,57 +76,98 @@ static int dwmci_wait_reset(struct dwmci_host *host, u32 value) return 0; } -static void dwmci_set_idma_desc(struct dwmci_idmac *idmac, - u32 desc0, u32 desc1, u32 desc2) +static void dwmci_set_idma_desc32(struct dwmci_idmac32 *desc, u32 control, + u32 buf_size, u32 buf_addr) { - struct dwmci_idmac *desc = idmac; + phys_addr_t desc_phys = virt_to_phys(desc); + u32 next_desc_phys = desc_phys + sizeof(struct dwmci_idmac32); - desc->flags = desc0; - desc->cnt = desc1; - desc->addr = desc2; - desc->next_addr = (ulong)desc + sizeof(struct dwmci_idmac); + desc->des0 = control; + desc->des1 = buf_size; + desc->des2 = buf_addr; + desc->des3 = next_desc_phys; } -static void dwmci_prepare_data(struct dwmci_host *host, - struct mmc_data *data, - struct dwmci_idmac *cur_idmac, - void *bounce_buffer) +static void dwmci_set_idma_desc64(struct dwmci_idmac64 *desc, u32 control, + u32 buf_size, u64 buf_addr) { - unsigned long ctrl; - unsigned int i = 0, flags, cnt, blk_cnt; + phys_addr_t desc_phys = virt_to_phys(desc); + u64 next_desc_phys = desc_phys + sizeof(struct dwmci_idmac64); + + desc->des0 = control; + desc->des1 = 0; + desc->des2 = buf_size; + desc->des3 = 0; + desc->des4 = buf_addr & 0xffffffff; + desc->des5 = buf_addr >> 32; + desc->des6 = next_desc_phys & 0xffffffff; + desc->des7 = next_desc_phys >> 32; +} + +static void dwmci_prepare_desc(struct dwmci_host *host, struct mmc_data *data, + void *cur_idmac, void *bounce_buffer) +{ + struct dwmci_idmac32 *desc32 = cur_idmac; + struct dwmci_idmac64 *desc64 = cur_idmac; ulong data_start, data_end; + unsigned int blk_cnt, i; + data_start = (ulong)cur_idmac; blk_cnt = data->blocks; - dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET); - - /* Clear IDMAC interrupt */ - dwmci_writel(host, DWMCI_IDSTS, 0xFFFFFFFF); + for (i = 0;; i++) { + phys_addr_t buf_phys = virt_to_phys(bounce_buffer); + unsigned int flags, cnt; - data_start = (ulong)cur_idmac; - dwmci_writel(host, DWMCI_DBADDR, (ulong)cur_idmac); - - do { - flags = DWMCI_IDMAC_OWN | DWMCI_IDMAC_CH ; - flags |= (i == 0) ? DWMCI_IDMAC_FS : 0; + flags = DWMCI_IDMAC_OWN | DWMCI_IDMAC_CH; + if (i == 0) + flags |= DWMCI_IDMAC_FS; if (blk_cnt <= 8) { flags |= DWMCI_IDMAC_LD; cnt = data->blocksize * blk_cnt; - } else + } else { cnt = data->blocksize * 8; + } - dwmci_set_idma_desc(cur_idmac, flags, cnt, - (ulong)bounce_buffer + (i * PAGE_SIZE)); + if (host->dma_64bit_address) { + dwmci_set_idma_desc64(desc64, flags, cnt, + buf_phys + i * PAGE_SIZE); + desc64++; + } else { + dwmci_set_idma_desc32(desc32, flags, cnt, + buf_phys + i * PAGE_SIZE); + desc32++; + } - cur_idmac++; if (blk_cnt <= 8) break; blk_cnt -= 8; - i++; - } while(1); + } - data_end = (ulong)cur_idmac; + if (host->dma_64bit_address) + data_end = (ulong)desc64; + else + data_end = (ulong)desc32; flush_dcache_range(data_start, roundup(data_end, ARCH_DMA_MINALIGN)); +} + +static void dwmci_prepare_data(struct dwmci_host *host, struct mmc_data *data, + void *cur_idmac, void *bounce_buffer) +{ + const u32 idmacl = virt_to_phys(cur_idmac) & 0xffffffff; + const u32 idmacu = (u64)virt_to_phys(cur_idmac) >> 32; + unsigned long ctrl; + + dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET); + + /* Clear IDMAC interrupt */ + dwmci_writel(host, host->regs->idsts, 0xffffffff); + + dwmci_writel(host, host->regs->dbaddrl, idmacl); + if (host->dma_64bit_address) + dwmci_writel(host, host->regs->dbaddru, idmacu); + + dwmci_prepare_desc(host, data, cur_idmac, bounce_buffer); ctrl = dwmci_readl(host, DWMCI_CTRL); ctrl |= DWMCI_IDMAC_EN | DWMCI_DMA_EN; @@ -132,90 +214,86 @@ static unsigned int dwmci_get_timeout(struct mmc *mmc, const unsigned int size) return timeout; } -static int dwmci_data_transfer(struct dwmci_host *host, struct mmc_data *data) +static int dwmci_data_transfer_fifo(struct dwmci_host *host, + struct mmc_data *data, u32 mask) { - struct mmc *mmc = host->mmc; + const u32 int_rx = mask & (DWMCI_INTMSK_RXDR | DWMCI_INTMSK_DTO); + const u32 int_tx = mask & DWMCI_INTMSK_TXDR; int ret = 0; - u32 timeout, mask, size, i, len = 0; - u32 *buf = NULL; - ulong start = get_timer(0); - u32 fifo_depth = (((host->fifoth_val & RX_WMARK_MASK) >> - RX_WMARK_SHIFT) + 1) * 2; + u32 len = 0, size, i; + u32 *buf; + + size = (data->blocksize * data->blocks) / 4; + if (!host->fifo_mode || !size) + return 0; - size = data->blocksize * data->blocks; if (data->flags == MMC_DATA_READ) buf = (unsigned int *)data->dest; else buf = (unsigned int *)data->src; - timeout = dwmci_get_timeout(mmc, size); + if (data->flags == MMC_DATA_READ && int_rx) { + dwmci_writel(host, DWMCI_RINTSTS, int_rx); + while (size) { + ret = dwmci_fifo_ready(host, DWMCI_FIFO_EMPTY, &len); + if (ret < 0) + break; + + len = (len >> DWMCI_FIFO_SHIFT) & DWMCI_FIFO_MASK; + len = min(size, len); + for (i = 0; i < len; i++) + *buf++ = dwmci_readl(host, DWMCI_DATA); + size = size > len ? (size - len) : 0; + } + } else if (data->flags == MMC_DATA_WRITE && int_tx) { + while (size) { + ret = dwmci_fifo_ready(host, DWMCI_FIFO_FULL, &len); + if (ret < 0) + break; + + len = host->fifo_depth - ((len >> DWMCI_FIFO_SHIFT) & + DWMCI_FIFO_MASK); + len = min(size, len); + for (i = 0; i < len; i++) + dwmci_writel(host, DWMCI_DATA, *buf++); + size = size > len ? (size - len) : 0; + } + dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_TXDR); + } - size /= 4; + return ret; +} + +static int dwmci_data_transfer(struct dwmci_host *host, struct mmc_data *data) +{ + struct mmc *mmc = host->mmc; + int ret = 0; + u32 timeout, mask, size; + ulong start = get_timer(0); + + size = data->blocksize * data->blocks; + timeout = dwmci_get_timeout(mmc, size); for (;;) { mask = dwmci_readl(host, DWMCI_RINTSTS); - /* Error during data transfer. */ + /* Error during data transfer */ if (mask & (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) { debug("%s: DATA ERROR!\n", __func__); ret = -EINVAL; break; } - if (host->fifo_mode && size) { - len = 0; - if (data->flags == MMC_DATA_READ && - (mask & (DWMCI_INTMSK_RXDR | DWMCI_INTMSK_DTO))) { - dwmci_writel(host, DWMCI_RINTSTS, - mask & (DWMCI_INTMSK_RXDR | - DWMCI_INTMSK_DTO)); - while (size) { - ret = dwmci_fifo_ready(host, - DWMCI_FIFO_EMPTY, - &len); - if (ret < 0) - break; - - len = (len >> DWMCI_FIFO_SHIFT) & - DWMCI_FIFO_MASK; - len = min(size, len); - for (i = 0; i < len; i++) - *buf++ = - dwmci_readl(host, DWMCI_DATA); - size = size > len ? (size - len) : 0; - } - } else if (data->flags == MMC_DATA_WRITE && - (mask & DWMCI_INTMSK_TXDR)) { - while (size) { - ret = dwmci_fifo_ready(host, - DWMCI_FIFO_FULL, - &len); - if (ret < 0) - break; - - len = fifo_depth - ((len >> - DWMCI_FIFO_SHIFT) & - DWMCI_FIFO_MASK); - len = min(size, len); - for (i = 0; i < len; i++) - dwmci_writel(host, DWMCI_DATA, - *buf++); - size = size > len ? (size - len) : 0; - } - dwmci_writel(host, DWMCI_RINTSTS, - DWMCI_INTMSK_TXDR); - } - } + ret = dwmci_data_transfer_fifo(host, data, mask); - /* Data arrived correctly. */ + /* Data arrived correctly */ if (mask & DWMCI_INTMSK_DTO) { ret = 0; break; } - /* Check for timeout. */ + /* Check for timeout */ if (get_timer(start) > timeout) { - debug("%s: Timeout waiting for data!\n", - __func__); + debug("%s: Timeout waiting for data!\n", __func__); ret = -ETIMEDOUT; break; } @@ -226,8 +304,35 @@ static int dwmci_data_transfer(struct dwmci_host *host, struct mmc_data *data) return ret; } +static int dwmci_dma_transfer(struct dwmci_host *host, uint flags, + struct bounce_buffer *bbstate) +{ + int ret; + u32 mask, ctrl; + + if (flags == MMC_DATA_READ) + mask = DWMCI_IDINTEN_RI; + else + mask = DWMCI_IDINTEN_TI; + + ret = wait_for_bit_le32(host->ioaddr + host->regs->idsts, mask, true, + 1000, false); + if (ret) + debug("%s: DWMCI_IDINTEN mask 0x%x timeout\n", __func__, mask); + + /* Clear interrupts */ + dwmci_writel(host, host->regs->idsts, DWMCI_IDINTEN_MASK); + + ctrl = dwmci_readl(host, DWMCI_CTRL); + ctrl &= ~DWMCI_DMA_EN; + dwmci_writel(host, DWMCI_CTRL, ctrl); + + bounce_buffer_stop(bbstate); + return ret; +} + static int dwmci_set_transfer_mode(struct dwmci_host *host, - struct mmc_data *data) + struct mmc_data *data) { unsigned long mode; @@ -238,33 +343,30 @@ static int dwmci_set_transfer_mode(struct dwmci_host *host, return mode; } -#ifdef CONFIG_DM_MMC -static int dwmci_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, - struct mmc_data *data) +static void dwmci_wait_while_busy(struct dwmci_host *host, struct mmc_cmd *cmd) { - struct mmc *mmc = mmc_get_mmc_dev(dev); -#else -static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, - struct mmc_data *data) -{ -#endif - struct dwmci_host *host = mmc->priv; - ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac, cur_idmac, - data ? DIV_ROUND_UP(data->blocks, 8) : 0); - int ret = 0, flags = 0, i; - unsigned int timeout = 500; - u32 retry = 100000; - u32 mask, ctrl; - ulong start = get_timer(0); - struct bounce_buffer bbstate; + unsigned int timeout = 500; /* msec */ + ulong start; + start = get_timer(0); while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) { if (get_timer(start) > timeout) { - debug("%s: Timeout on data busy, continue anyway\n", __func__); + debug("%s: Timeout on data busy, continue anyway\n", + __func__); break; } } +} +static int dwmci_send_cmd_common(struct dwmci_host *host, struct mmc_cmd *cmd, + struct mmc_data *data, void *cur_idmac) +{ + int ret, flags = 0, i; + u32 retry = 100000; + u32 mask; + struct bounce_buffer bbstate; + + dwmci_wait_while_busy(host, cmd); dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL); if (data) { @@ -276,12 +378,12 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, } else { if (data->flags == MMC_DATA_READ) { ret = bounce_buffer_start(&bbstate, - (void*)data->dest, + (void *)data->dest, data->blocksize * data->blocks, GEN_BB_WRITE); } else { ret = bounce_buffer_start(&bbstate, - (void*)data->src, + (void *)data->src, data->blocksize * data->blocks, GEN_BB_READ); } @@ -316,9 +418,9 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, if (cmd->resp_type & MMC_RSP_CRC) flags |= DWMCI_CMD_CHECK_CRC; - flags |= (cmd->cmdidx | DWMCI_CMD_START | DWMCI_CMD_USE_HOLD_REG); + flags |= cmd->cmdidx | DWMCI_CMD_START | DWMCI_CMD_USE_HOLD_REG; - debug("Sending CMD%d\n",cmd->cmdidx); + debug("Sending CMD%d\n", cmd->cmdidx); dwmci_writel(host, DWMCI_CMD, flags); @@ -332,7 +434,7 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, } if (i == retry) { - debug("%s: Timeout.\n", __func__); + debug("%s: Timeout\n", __func__); return -ETIMEDOUT; } @@ -345,14 +447,14 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, * below shall be debug(). eMMC cards also do not favor * CMD8, please keep that in mind. */ - debug("%s: Response Timeout.\n", __func__); + debug("%s: Response Timeout\n", __func__); return -ETIMEDOUT; } else if (mask & DWMCI_INTMSK_RE) { - debug("%s: Response Error.\n", __func__); + debug("%s: Response Error\n", __func__); return -EIO; } else if ((cmd->resp_type & MMC_RSP_CRC) && (mask & DWMCI_INTMSK_RCRC)) { - debug("%s: Response CRC Error.\n", __func__); + debug("%s: Response CRC Error\n", __func__); return -EIO; } @@ -369,26 +471,8 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, if (data) { ret = dwmci_data_transfer(host, data); - - /* only dma mode need it */ - if (!host->fifo_mode) { - if (data->flags == MMC_DATA_READ) - mask = DWMCI_IDINTEN_RI; - else - mask = DWMCI_IDINTEN_TI; - ret = wait_for_bit_le32(host->ioaddr + DWMCI_IDSTS, - mask, true, 1000, false); - if (ret) - debug("%s: DWMCI_IDINTEN mask 0x%x timeout.\n", - __func__, mask); - /* clear interrupts */ - dwmci_writel(host, DWMCI_IDSTS, DWMCI_IDINTEN_MASK); - - ctrl = dwmci_readl(host, DWMCI_CTRL); - ctrl &= ~(DWMCI_DMA_EN); - dwmci_writel(host, DWMCI_CTRL, ctrl); - bounce_buffer_stop(&bbstate); - } + if (!host->fifo_mode) + ret = dwmci_dma_transfer(host, data->flags, &bbstate); } udelay(100); @@ -396,40 +480,39 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, return ret; } -static int dwmci_setup_bus(struct dwmci_host *host, u32 freq) +#ifdef CONFIG_DM_MMC +static int dwmci_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, + struct mmc_data *data) { - u32 div, status; - int timeout = 10000; - unsigned long sclk; + struct mmc *mmc = mmc_get_mmc_dev(dev); +#else +static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, + struct mmc_data *data) +{ +#endif + struct dwmci_host *host = mmc->priv; + const size_t buf_size = data ? DIV_ROUND_UP(data->blocks, 8) : 0; - if ((freq == host->clock) || (freq == 0)) - return 0; - /* - * If host->get_mmc_clk isn't defined, - * then assume that host->bus_hz is source clock value. - * host->bus_hz should be set by user. - */ - if (host->get_mmc_clk) - sclk = host->get_mmc_clk(host, freq); - else if (host->bus_hz) - sclk = host->bus_hz; - else { - debug("%s: Didn't get source clock value.\n", __func__); - return -EINVAL; + if (host->dma_64bit_address) { + ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac64, idmac, buf_size); + return dwmci_send_cmd_common(host, cmd, data, idmac); + } else { + ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac32, idmac, buf_size); + return dwmci_send_cmd_common(host, cmd, data, idmac); } +} - if (sclk == freq) - div = 0; /* bypass mode */ - else - div = DIV_ROUND_UP(sclk, 2 * freq); - - dwmci_writel(host, DWMCI_CLKENA, 0); - dwmci_writel(host, DWMCI_CLKSRC, 0); +static int dwmci_control_clken(struct dwmci_host *host, bool on) +{ + const u32 val = on ? DWMCI_CLKEN_ENABLE | DWMCI_CLKEN_LOW_PWR : 0; + const u32 cmd_only_clk = DWMCI_CMD_PRV_DAT_WAIT | DWMCI_CMD_UPD_CLK; + int timeout = 10000; + u32 status; - dwmci_writel(host, DWMCI_CLKDIV, div); - dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT | - DWMCI_CMD_UPD_CLK | DWMCI_CMD_START); + dwmci_writel(host, DWMCI_CLKENA, val); + /* Inform CIU */ + dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_START | cmd_only_clk); do { status = dwmci_readl(host, DWMCI_CMD); if (timeout-- < 0) { @@ -438,20 +521,62 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq) } } while (status & DWMCI_CMD_START); - dwmci_writel(host, DWMCI_CLKENA, DWMCI_CLKEN_ENABLE | - DWMCI_CLKEN_LOW_PWR); + return 0; +} - dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT | - DWMCI_CMD_UPD_CLK | DWMCI_CMD_START); +/* + * Update the clock divider. + * + * To prevent a clock glitch keep the clock stopped during the update of + * clock divider and clock source. + */ +static int dwmci_update_div(struct dwmci_host *host, u32 div) +{ + int ret; - timeout = 10000; - do { - status = dwmci_readl(host, DWMCI_CMD); - if (timeout-- < 0) { - debug("%s: Timeout!\n", __func__); - return -ETIMEDOUT; - } - } while (status & DWMCI_CMD_START); + /* Disable clock */ + ret = dwmci_control_clken(host, false); + if (ret) + return ret; + + /* Set clock to desired speed */ + dwmci_writel(host, DWMCI_CLKDIV, div); + dwmci_writel(host, DWMCI_CLKSRC, 0); + + /* Enable clock */ + return dwmci_control_clken(host, true); +} + +static int dwmci_setup_bus(struct dwmci_host *host, u32 freq) +{ + u32 div; + unsigned long sclk; + int ret; + + if (freq == host->clock || freq == 0) + return 0; + + /* + * If host->get_mmc_clk isn't defined, then assume that host->bus_hz is + * source clock value. host->bus_hz should be set by user. + */ + if (host->get_mmc_clk) { + sclk = host->get_mmc_clk(host, freq); + } else if (host->bus_hz) { + sclk = host->bus_hz; + } else { + debug("%s: Didn't get source clock value\n", __func__); + return -EINVAL; + } + + if (sclk == freq) + div = 0; /* bypass mode */ + else + div = DIV_ROUND_UP(sclk, 2 * freq); + + ret = dwmci_update_div(host, div); + if (ret) + return ret; host->clock = freq; @@ -469,7 +594,7 @@ static int dwmci_set_ios(struct mmc *mmc) struct dwmci_host *host = (struct dwmci_host *)mmc->priv; u32 ctype, regs; - debug("Buswidth = %d, clock: %d\n", mmc->bus_width, mmc->clock); + debug("Bus width = %d, clock: %d\n", mmc->bus_width, mmc->clock); dwmci_setup_bus(host, mmc->clock); switch (mmc->bus_width) { @@ -524,6 +649,48 @@ static int dwmci_set_ios(struct mmc *mmc) return 0; } +static void dwmci_init_fifo(struct dwmci_host *host) +{ + u32 fifo_thr, fifoth_val; + + if (!host->fifo_depth) { + u32 fifo_size; + + /* + * Automatically detect FIFO depth from FIFOTH register. + * Power-on value of RX_WMark is FIFO_DEPTH-1. + */ + fifo_size = dwmci_readl(host, DWMCI_FIFOTH); + fifo_size = ((fifo_size & RX_WMARK_MASK) >> RX_WMARK_SHIFT) + 1; + host->fifo_depth = fifo_size; + } + + fifo_thr = host->fifo_depth / 2; + fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_thr - 1) | TX_WMARK(fifo_thr); + dwmci_writel(host, DWMCI_FIFOTH, fifoth_val); +} + +static void dwmci_init_dma(struct dwmci_host *host) +{ + int addr_config; + + if (host->fifo_mode) + return; + + addr_config = (dwmci_readl(host, DWMCI_HCON) >> 27) & 0x1; + if (addr_config == 1) { + host->dma_64bit_address = true; + host->regs = &dwmci_idmac_regs64; + debug("%s: IDMAC supports 64-bit address mode\n", __func__); + } else { + host->dma_64bit_address = false; + host->regs = &dwmci_idmac_regs32; + debug("%s: IDMAC supports 32-bit address mode\n", __func__); + } + + dwmci_writel(host, host->regs->idinten, DWMCI_IDINTEN_MASK); +} + static int dwmci_init(struct mmc *mmc) { struct dwmci_host *host = mmc->priv; @@ -541,30 +708,18 @@ static int dwmci_init(struct mmc *mmc) /* Enumerate at 400KHz */ dwmci_setup_bus(host, mmc->cfg->f_min); - dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF); + dwmci_writel(host, DWMCI_RINTSTS, 0xffffffff); dwmci_writel(host, DWMCI_INTMASK, 0); - dwmci_writel(host, DWMCI_TMOUT, 0xFFFFFFFF); + dwmci_writel(host, DWMCI_TMOUT, 0xffffffff); - dwmci_writel(host, DWMCI_IDINTEN, 0); dwmci_writel(host, DWMCI_BMOD, 1); - - if (!host->fifoth_val) { - uint32_t fifo_size; - - fifo_size = dwmci_readl(host, DWMCI_FIFOTH); - fifo_size = ((fifo_size & RX_WMARK_MASK) >> RX_WMARK_SHIFT) + 1; - host->fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size / 2 - 1) | - TX_WMARK(fifo_size / 2); - } - dwmci_writel(host, DWMCI_FIFOTH, host->fifoth_val); + dwmci_init_fifo(host); + dwmci_init_dma(host); dwmci_writel(host, DWMCI_CLKENA, 0); dwmci_writel(host, DWMCI_CLKSRC, 0); - if (!host->fifo_mode) - dwmci_writel(host, DWMCI_IDINTEN, DWMCI_IDINTEN_MASK); - return 0; } @@ -590,7 +745,7 @@ static const struct mmc_ops dwmci_ops = { #endif void dwmci_setup_cfg(struct mmc_config *cfg, struct dwmci_host *host, - u32 max_clk, u32 min_clk) + u32 max_clk, u32 min_clk) { cfg->name = host->name; #ifndef CONFIG_DM_MMC @@ -626,7 +781,7 @@ int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk) dwmci_setup_cfg(&host->cfg, host, max_clk, min_clk); host->mmc = mmc_create(&host->cfg, host); - if (host->mmc == NULL) + if (!host->mmc) return -1; return 0; diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c index a51f762988d..c8bf89d6d35 100644 --- a/drivers/mmc/exynos_dw_mmc.c +++ b/drivers/mmc/exynos_dw_mmc.c @@ -4,10 +4,9 @@ * Jaehoon Chung <jh80.chung@samsung.com> */ +#include <clk.h> #include <dwmmc.h> -#include <fdtdec.h> #include <asm/global_data.h> -#include <linux/libfdt.h> #include <malloc.h> #include <errno.h> #include <asm/arch/dwmmc.h> @@ -15,6 +14,7 @@ #include <asm/arch/pinmux.h> #include <asm/arch/power.h> #include <asm/gpio.h> +#include <linux/err.h> #include <linux/printk.h> #define DWMMC_MAX_CH_NUM 4 @@ -23,6 +23,11 @@ #define DWMMC_MMC0_SDR_TIMING_VAL 0x03030001 #define DWMMC_MMC2_SDR_TIMING_VAL 0x03020001 +#define EXYNOS4412_FIXED_CIU_CLK_DIV 4 + +/* Quirks */ +#define DWMCI_QUIRK_DISABLE_SMU BIT(0) + #ifdef CONFIG_DM_MMC #include <dm.h> DECLARE_GLOBAL_DATA_PTR; @@ -33,35 +38,117 @@ struct exynos_mmc_plat { }; #endif -/* Exynos implmentation specific drver private data */ +/* Chip specific data */ +struct exynos_dwmmc_variant { + u32 clksel; /* CLKSEL register offset */ + u8 div; /* (optional) fixed clock divider value: 0..7 */ + u32 quirks; /* quirk flags - see DWMCI_QUIRK_... */ +}; + +/* Exynos implementation specific driver private data */ struct dwmci_exynos_priv_data { #ifdef CONFIG_DM_MMC struct dwmci_host host; #endif + struct clk clk; u32 sdr_timing; + u32 ddr_timing; + const struct exynos_dwmmc_variant *chip; }; -/* - * Function used as callback function to initialise the - * CLKSEL register for every mmc channel. - */ -static int exynos_dwmci_clksel(struct dwmci_host *host) +static struct dwmci_exynos_priv_data *exynos_dwmmc_get_priv( + struct dwmci_host *host) { #ifdef CONFIG_DM_MMC - struct dwmci_exynos_priv_data *priv = - container_of(host, struct dwmci_exynos_priv_data, host); + return container_of(host, struct dwmci_exynos_priv_data, host); #else - struct dwmci_exynos_priv_data *priv = host->priv; + return host->priv; #endif - dwmci_writel(host, DWMCI_CLKSEL, priv->sdr_timing); +} + +/** + * exynos_dwmmc_get_sclk - Get source clock (SDCLKIN) rate + * @host: MMC controller object + * @rate: Will contain clock rate, Hz + * + * Return: 0 on success or negative value on error + */ +static int exynos_dwmmc_get_sclk(struct dwmci_host *host, unsigned long *rate) +{ +#ifdef CONFIG_CPU_V7A + *rate = get_mmc_clk(host->dev_index); +#else + struct dwmci_exynos_priv_data *priv = exynos_dwmmc_get_priv(host); + + *rate = clk_get_rate(&priv->clk); +#endif + + if (IS_ERR_VALUE(*rate)) + return *rate; return 0; } -unsigned int exynos_dwmci_get_clk(struct dwmci_host *host, uint freq) +/** + * exynos_dwmmc_set_sclk - Set source clock (SDCLKIN) rate + * @host: MMC controller object + * @rate: Desired clock rate, Hz + * + * Return: 0 on success or negative value on error + */ +static int exynos_dwmmc_set_sclk(struct dwmci_host *host, unsigned long rate) { + int err; + +#ifdef CONFIG_CPU_V7A unsigned long sclk; - int8_t clk_div; + unsigned int div; + + err = exynos_dwmmc_get_sclk(host, &sclk); + if (err) + return err; + + div = DIV_ROUND_UP(sclk, rate); + set_mmc_clk(host->dev_index, div); +#else + struct dwmci_exynos_priv_data *priv = exynos_dwmmc_get_priv(host); + + err = clk_set_rate(&priv->clk, rate); + if (err < 0) + return err; +#endif + + return 0; +} + +/* Configure CLKSEL register with chosen timing values */ +static int exynos_dwmci_clksel(struct dwmci_host *host) +{ + struct dwmci_exynos_priv_data *priv = exynos_dwmmc_get_priv(host); + u32 timing; + + if (host->mmc->selected_mode == MMC_DDR_52) + timing = priv->ddr_timing; + else + timing = priv->sdr_timing; + + dwmci_writel(host, priv->chip->clksel, timing); + + return 0; +} + +/** + * exynos_dwmmc_get_ciu_div - Get internal clock divider value + * @host: MMC controller object + * + * Returns: Divider value, in range of 1..8 + */ +static u8 exynos_dwmmc_get_ciu_div(struct dwmci_host *host) +{ + struct dwmci_exynos_priv_data *priv = exynos_dwmmc_get_priv(host); + + if (priv->chip->div) + return priv->chip->div + 1; /* * Since SDCLKIN is divided inside controller by the DIVRATIO @@ -69,22 +156,42 @@ unsigned int exynos_dwmci_get_clk(struct dwmci_host *host, uint freq) * clock value to calculate the CLKDIV value. * as per user manual:cclk_in = SDCLKIN / (DIVRATIO + 1) */ - clk_div = ((dwmci_readl(host, DWMCI_CLKSEL) >> DWMCI_DIVRATIO_BIT) - & DWMCI_DIVRATIO_MASK) + 1; - sclk = get_mmc_clk(host->dev_index); + return ((dwmci_readl(host, priv->chip->clksel) >> DWMCI_DIVRATIO_BIT) + & DWMCI_DIVRATIO_MASK) + 1; +} - /* - * Assume to know divider value. - * When clock unit is broken, need to set "host->div" - */ - return sclk / clk_div / (host->div + 1); +static unsigned int exynos_dwmci_get_clk(struct dwmci_host *host, uint freq) +{ + unsigned long sclk; + u8 clk_div; + int err; + + /* Should be double rate for DDR mode */ + if (host->mmc->selected_mode == MMC_DDR_52 && host->mmc->bus_width == 8) + freq *= 2; + + clk_div = exynos_dwmmc_get_ciu_div(host); + err = exynos_dwmmc_set_sclk(host, freq * clk_div); + if (err) { + printf("DWMMC%d: failed to set clock rate (%d); " + "continue anyway\n", host->dev_index, err); + } + + err = exynos_dwmmc_get_sclk(host, &sclk); + if (err) { + printf("DWMMC%d: failed to get clock rate (%d)\n", + host->dev_index, err); + return 0; + } + + return sclk / clk_div; } static void exynos_dwmci_board_init(struct dwmci_host *host) { - struct dwmci_exynos_priv_data *priv = host->priv; + struct dwmci_exynos_priv_data *priv = exynos_dwmmc_get_priv(host); - if (host->quirks & DWMCI_QUIRK_DISABLE_SMU) { + if (priv->chip->quirks & DWMCI_QUIRK_DISABLE_SMU) { dwmci_writel(host, EMMCP_MPSBEGIN0, 0); dwmci_writel(host, EMMCP_SEND0, 0); dwmci_writel(host, EMMCP_CTRL0, @@ -94,73 +201,27 @@ static void exynos_dwmci_board_init(struct dwmci_host *host) MPSCTRL_NON_SECURE_WRITE_BIT | MPSCTRL_VALID); } - /* Set to timing value at initial time */ if (priv->sdr_timing) exynos_dwmci_clksel(host); } -static int exynos_dwmci_core_init(struct dwmci_host *host) -{ - unsigned int div; - unsigned long freq, sclk; - - if (host->bus_hz) - freq = host->bus_hz; - else - freq = DWMMC_MAX_FREQ; - - /* request mmc clock vlaue of 52MHz. */ - sclk = get_mmc_clk(host->dev_index); - div = DIV_ROUND_UP(sclk, freq); - /* set the clock divisor for mmc */ - set_mmc_clk(host->dev_index, div); - - host->name = "EXYNOS DWMMC"; -#ifdef CONFIG_EXYNOS5420 - host->quirks = DWMCI_QUIRK_DISABLE_SMU; -#endif - host->board_init = exynos_dwmci_board_init; - - host->caps = MMC_MODE_DDR_52MHz; - host->clksel = exynos_dwmci_clksel; - host->get_mmc_clk = exynos_dwmci_get_clk; - -#ifndef CONFIG_DM_MMC - /* Add the mmc channel to be registered with mmc core */ - if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) { - printf("DWMMC%d registration failed\n", host->dev_index); - return -1; - } -#endif - - return 0; -} - -static int do_dwmci_init(struct dwmci_host *host) +#ifdef CONFIG_DM_MMC +static int exynos_dwmmc_of_to_plat(struct udevice *dev) { - int flag, err; - - flag = host->buswidth == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE; - err = exynos_pinmux_config(host->dev_id, flag); - if (err) { - printf("DWMMC%d not configure\n", host->dev_index); - return err; - } + struct dwmci_exynos_priv_data *priv = dev_get_priv(dev); + struct dwmci_host *host = &priv->host; + u32 div, timing[2]; + int err; - return exynos_dwmci_core_init(host); -} + priv->chip = (struct exynos_dwmmc_variant *)dev_get_driver_data(dev); -static int exynos_dwmci_get_config(const void *blob, int node, - struct dwmci_host *host, - struct dwmci_exynos_priv_data *priv) -{ - int err = 0; - u32 base, timing[3]; +#ifdef CONFIG_CPU_V7A + const void *blob = gd->fdt_blob; + int node = dev_of_offset(dev); - /* Extract device id for each mmc channel */ + /* Obtain device ID for current MMC channel */ host->dev_id = pinmux_decode_periph_id(blob, node); - - host->dev_index = fdtdec_get_int(blob, node, "index", host->dev_id); + host->dev_index = dev_read_u32_default(dev, "index", host->dev_id); if (host->dev_index == host->dev_id) host->dev_index = host->dev_id - PERIPH_ID_SDMMC0; @@ -168,31 +229,34 @@ static int exynos_dwmci_get_config(const void *blob, int node, printf("DWMMC%d: Can't get the dev index\n", host->dev_index); return -EINVAL; } +#else + if (dev_read_bool(dev, "non-removable")) + host->dev_index = 0; /* eMMC */ + else + host->dev_index = 2; /* SD card */ +#endif - /* Get the bus width from the device node (Default is 4bit buswidth) */ - host->buswidth = fdtdec_get_int(blob, node, "samsung,bus-width", 4); - - /* Set the base address from the device node */ - base = fdtdec_get_addr(blob, node, "reg"); - if (!base) { + host->ioaddr = dev_read_addr_ptr(dev); + if (!host->ioaddr) { printf("DWMMC%d: Can't get base address\n", host->dev_index); return -EINVAL; } - host->ioaddr = (void *)base; - /* Extract the timing info from the node */ - err = fdtdec_get_int_array(blob, node, "samsung,timing", timing, 3); + if (priv->chip->div) + div = priv->chip->div; + else + div = dev_read_u32_default(dev, "samsung,dw-mshc-ciu-div", 0); + + err = dev_read_u32_array(dev, "samsung,dw-mshc-sdr-timing", timing, 2); if (err) { - printf("DWMMC%d: Can't get sdr-timings for devider\n", - host->dev_index); + printf("DWMMC%d: Can't get sdr-timings\n", host->dev_index); return -EINVAL; } + priv->sdr_timing = DWMCI_SET_SAMPLE_CLK(timing[0]) | + DWMCI_SET_DRV_CLK(timing[1]) | + DWMCI_SET_DIV_RATIO(div); - priv->sdr_timing = (DWMCI_SET_SAMPLE_CLK(timing[0]) | - DWMCI_SET_DRV_CLK(timing[1]) | - DWMCI_SET_DIV_RATIO(timing[2])); - - /* sdr_timing didn't assigned anything, use the default value */ + /* sdr_timing wasn't set, use the default value */ if (!priv->sdr_timing) { if (host->dev_index == 0) priv->sdr_timing = DWMMC_MMC0_SDR_TIMING_VAL; @@ -200,35 +264,82 @@ static int exynos_dwmci_get_config(const void *blob, int node, priv->sdr_timing = DWMMC_MMC2_SDR_TIMING_VAL; } - host->fifoth_val = fdtdec_get_int(blob, node, "fifoth_val", 0); - host->bus_hz = fdtdec_get_int(blob, node, "bus_hz", 0); - host->div = fdtdec_get_int(blob, node, "div", 0); + err = dev_read_u32_array(dev, "samsung,dw-mshc-ddr-timing", timing, 2); + if (err) { + debug("DWMMC%d: Can't get ddr-timings, using sdr-timings\n", + host->dev_index); + priv->ddr_timing = priv->sdr_timing; + } else { + priv->ddr_timing = DWMCI_SET_SAMPLE_CLK(timing[0]) | + DWMCI_SET_DRV_CLK(timing[1]) | + DWMCI_SET_DIV_RATIO(div); + } + + host->buswidth = dev_read_u32_default(dev, "bus-width", 4); + host->fifo_depth = dev_read_u32_default(dev, "fifo-depth", 0); + host->bus_hz = dev_read_u32_default(dev, "clock-frequency", 0); return 0; } -#ifdef CONFIG_DM_MMC static int exynos_dwmmc_probe(struct udevice *dev) { struct exynos_mmc_plat *plat = dev_get_plat(dev); struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); struct dwmci_exynos_priv_data *priv = dev_get_priv(dev); struct dwmci_host *host = &priv->host; + unsigned long freq; int err; - err = exynos_dwmci_get_config(gd->fdt_blob, dev_of_offset(dev), host, - priv); +#ifndef CONFIG_CPU_V7A + err = clk_get_by_index(dev, 1, &priv->clk); /* ciu */ if (err) return err; - err = do_dwmci_init(host); - if (err) +#endif + +#ifdef CONFIG_CPU_V7A + int flag; + + flag = host->buswidth == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE; + err = exynos_pinmux_config(host->dev_id, flag); + if (err) { + printf("DWMMC%d not configure\n", host->dev_index); return err; + } +#endif + + if (host->bus_hz) + freq = host->bus_hz; + else + freq = DWMMC_MAX_FREQ; + err = exynos_dwmmc_set_sclk(host, freq); + if (err) { + printf("DWMMC%d: failed to set clock rate on probe (%d); " + "continue anyway\n", host->dev_index, err); + } + + host->name = dev->name; + host->board_init = exynos_dwmci_board_init; + host->caps = MMC_MODE_DDR_52MHz; + host->clksel = exynos_dwmci_clksel; + host->get_mmc_clk = exynos_dwmci_get_clk; + +#ifdef CONFIG_BLK dwmci_setup_cfg(&plat->cfg, host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ); host->mmc = &plat->mmc; +#else + err = add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ); + if (err) { + printf("DWMMC%d registration failed\n", host->dev_index); + return err; + } +#endif + host->mmc->priv = &priv->host; - host->priv = dev; upriv->mmc = host->mmc; + host->mmc->dev = dev; + host->priv = dev; return dwmci_probe(dev); } @@ -240,9 +351,34 @@ static int exynos_dwmmc_bind(struct udevice *dev) return dwmci_bind(dev, &plat->mmc, &plat->cfg); } +static const struct exynos_dwmmc_variant exynos4_drv_data = { + .clksel = DWMCI_CLKSEL, + .div = EXYNOS4412_FIXED_CIU_CLK_DIV - 1, +}; + +static const struct exynos_dwmmc_variant exynos5_drv_data = { + .clksel = DWMCI_CLKSEL, +#ifdef CONFIG_EXYNOS5420 + .quirks = DWMCI_QUIRK_DISABLE_SMU, +#endif +}; + +static const struct exynos_dwmmc_variant exynos7_smu_drv_data = { + .clksel = DWMCI_CLKSEL64, + .quirks = DWMCI_QUIRK_DISABLE_SMU, +}; + static const struct udevice_id exynos_dwmmc_ids[] = { - { .compatible = "samsung,exynos4412-dw-mshc" }, - { .compatible = "samsung,exynos-dwmmc" }, + { + .compatible = "samsung,exynos4412-dw-mshc", + .data = (ulong)&exynos4_drv_data, + }, { + .compatible = "samsung,exynos-dwmmc", + .data = (ulong)&exynos5_drv_data, + }, { + .compatible = "samsung,exynos7-dw-mshc-smu", + .data = (ulong)&exynos7_smu_drv_data, + }, { } }; @@ -250,9 +386,10 @@ U_BOOT_DRIVER(exynos_dwmmc_drv) = { .name = "exynos_dwmmc", .id = UCLASS_MMC, .of_match = exynos_dwmmc_ids, + .of_to_plat = exynos_dwmmc_of_to_plat, .bind = exynos_dwmmc_bind, - .ops = &dm_dwmci_ops, .probe = exynos_dwmmc_probe, + .ops = &dm_dwmci_ops, .priv_auto = sizeof(struct dwmci_exynos_priv_data), .plat_auto = sizeof(struct exynos_mmc_plat), }; diff --git a/drivers/mmc/ftsdc010_mci.h b/drivers/mmc/ftsdc010_mci.h index 782d92be2f5..36187cfa04f 100644 --- a/drivers/mmc/ftsdc010_mci.h +++ b/drivers/mmc/ftsdc010_mci.h @@ -28,7 +28,6 @@ struct ftsdc010_chip { int dev_index; int dev_id; int buswidth; - u32 fifoth_val; struct mmc *mmc; void *priv; bool fifo_mode; diff --git a/drivers/mmc/hi6220_dw_mmc.c b/drivers/mmc/hi6220_dw_mmc.c index c68a9157bfc..0302f5c296b 100644 --- a/drivers/mmc/hi6220_dw_mmc.c +++ b/drivers/mmc/hi6220_dw_mmc.c @@ -36,7 +36,7 @@ struct hi6220_dwmmc_priv_data { struct hisi_mmc_data { unsigned int clock; bool use_fifo; - u32 fifoth_val; + u32 fifo_depth; }; static int hi6220_dwmmc_of_to_plat(struct udevice *dev) @@ -125,7 +125,7 @@ static int hi6220_dwmmc_probe(struct udevice *dev) host->mmc = &plat->mmc; host->fifo_mode = mmc_data->use_fifo; - host->fifoth_val = mmc_data->fifoth_val; + host->fifo_depth = mmc_data->fifo_depth; host->mmc->priv = &priv->host; upriv->mmc = host->mmc; host->mmc->dev = dev; @@ -158,8 +158,7 @@ static const struct hisi_mmc_data hi6220_mmc_data = { static const struct hisi_mmc_data hi3798mv2x_mmc_data = { .clock = 50000000, .use_fifo = false, - // FIFO depth is 256 - .fifoth_val = MSIZE(4) | RX_WMARK(0x7f) | TX_WMARK(0x80), + .fifo_depth = 256, }; static const struct udevice_id hi6220_dwmmc_ids[] = { diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index cf8277cbed8..9644aa7aa43 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -294,7 +294,7 @@ int mmc_poll_for_busy(struct mmc *mmc, int timeout_ms) if (status & MMC_STATUS_MASK) { #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) - pr_err("Status Error: 0x%08x\n", status); + log_err("Status Error: %#08x\n", status); #endif return -ECOMM; } @@ -307,7 +307,7 @@ int mmc_poll_for_busy(struct mmc *mmc, int timeout_ms) if (timeout_ms <= 0) { #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) - pr_err("Timeout waiting card ready\n"); + log_err("Timeout waiting card ready\n"); #endif return -ETIMEDOUT; } @@ -449,7 +449,7 @@ static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start, if (blkcnt > 1) { if (mmc_send_stop_transmission(mmc, false)) { #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) - pr_err("mmc fail to send stop cmd\n"); + log_err("mmc fail to send stop cmd\n"); #endif return 0; } @@ -500,8 +500,8 @@ ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt, if ((start + blkcnt) > block_dev->lba) { #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) - pr_err("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n", - start + blkcnt, block_dev->lba); + log_err("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n", + start + blkcnt, block_dev->lba); #endif return 0; } @@ -996,7 +996,7 @@ static int mmc_get_capabilities(struct mmc *mmc) return 0; if (!ext_csd) { - pr_err("No ext_csd found!\n"); /* this should enver happen */ + log_err("No ext_csd found!\n"); /* this should never happen */ return -ENOTSUPP; } @@ -1108,17 +1108,17 @@ int mmc_hwpart_config(struct mmc *mmc, return -EINVAL; if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) { - pr_err("eMMC >= 4.4 required for enhanced user data area\n"); + log_err("eMMC >= 4.4 required for enhanced user data area\n"); return -EMEDIUMTYPE; } if (!(mmc->part_support & PART_SUPPORT)) { - pr_err("Card does not support partitioning\n"); + log_err("Card does not support partitioning\n"); return -EMEDIUMTYPE; } if (!mmc->hc_wp_grp_size) { - pr_err("Card does not define HC WP group size\n"); + log_err("Card does not define HC WP group size\n"); return -EMEDIUMTYPE; } @@ -1126,8 +1126,7 @@ int mmc_hwpart_config(struct mmc *mmc, if (conf->user.enh_size) { if (conf->user.enh_size % mmc->hc_wp_grp_size || conf->user.enh_start % mmc->hc_wp_grp_size) { - pr_err("User data enhanced area not HC WP group " - "size aligned\n"); + log_err("User data enhanced area not HC WP group size aligned\n"); return -EINVAL; } part_attrs |= EXT_CSD_ENH_USR; @@ -1145,8 +1144,8 @@ int mmc_hwpart_config(struct mmc *mmc, for (pidx = 0; pidx < 4; pidx++) { if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) { - pr_err("GP%i partition not HC WP group size " - "aligned\n", pidx+1); + log_err("GP%i partition not HC WP group-size aligned\n", + pidx + 1); return -EINVAL; } gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size; @@ -1157,7 +1156,7 @@ int mmc_hwpart_config(struct mmc *mmc, } if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) { - pr_err("Card does not support enhanced attribute\n"); + log_err("Card does not support enhanced attribute\n"); return -EMEDIUMTYPE; } @@ -1170,8 +1169,8 @@ int mmc_hwpart_config(struct mmc *mmc, (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) + ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT]; if (tot_enh_size_mult > max_enh_size_mult) { - pr_err("Total enhanced size exceeds maximum (%u > %u)\n", - tot_enh_size_mult, max_enh_size_mult); + log_err("Total enhanced size exceeds maximum (%#x > %#x)\n", + tot_enh_size_mult, max_enh_size_mult); return -EMEDIUMTYPE; } @@ -1204,7 +1203,7 @@ int mmc_hwpart_config(struct mmc *mmc, if (ext_csd[EXT_CSD_PARTITION_SETTING] & EXT_CSD_PARTITION_SETTING_COMPLETED) { - pr_err("Card already partitioned\n"); + log_err("Card already partitioned\n"); return -EPERM; } @@ -1875,7 +1874,7 @@ error: } } - pr_err("unable to select a mode\n"); + log_err("unable to select a mode\n"); return -ENOTSUPP; } @@ -2253,7 +2252,7 @@ error: } } - pr_err("unable to select a mode : %d\n", err); + log_err("unable to select a mode: %d\n", err); return -ENOTSUPP; } @@ -2921,7 +2920,8 @@ retry: if (err) { #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) if (!quiet) - pr_err("Card did not respond to voltage select! : %d\n", err); + log_err("Card did not respond to voltage select! : %d\n", + err); #endif return -EOPNOTSUPP; } @@ -2954,7 +2954,7 @@ int mmc_start_init(struct mmc *mmc) | MMC_CAP(MMC_LEGACY) | MMC_MODE_1BIT); } else { - pr_err("bus_mode requested is not supported\n"); + log_err("bus_mode requested is not supported\n"); return -EINVAL; } } @@ -2974,7 +2974,7 @@ int mmc_start_init(struct mmc *mmc) if (no_card) { mmc->has_init = 0; #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) - pr_err("MMC: no card present\n"); + log_err("MMC: no card present\n"); #endif return -ENOMEDIUM; } @@ -3103,7 +3103,7 @@ static int mmc_probe(struct bd_info *bis) uclass_foreach_dev(dev, uc) { ret = device_probe(dev); if (ret) - pr_err("%s - probe failed: %d\n", dev->name, ret); + log_err("%s - probe failed: %d\n", dev->name, ret); } return 0; diff --git a/drivers/mmc/nexell_dw_mmc.c b/drivers/mmc/nexell_dw_mmc.c index 2e1ce54c7d5..80df617e07e 100644 --- a/drivers/mmc/nexell_dw_mmc.c +++ b/drivers/mmc/nexell_dw_mmc.c @@ -186,10 +186,7 @@ static int nexell_dwmmc_probe(struct udevice *dev) struct dwmci_host *host = &priv->host; struct udevice *pwr_dev __maybe_unused; - host->fifoth_val = MSIZE(0x2) | - RX_WMARK(priv->fifo_size / 2 - 1) | - TX_WMARK(priv->fifo_size / 2); - + host->fifo_depth = priv->fifo_size; host->fifo_mode = priv->fifo_mode; dwmci_setup_cfg(&plat->cfg, host, priv->max_freq, priv->min_freq); diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c index 549fb80f198..fb77b049834 100644 --- a/drivers/mmc/rockchip_dw_mmc.c +++ b/drivers/mmc/rockchip_dw_mmc.c @@ -138,10 +138,7 @@ static int rockchip_dwmmc_probe(struct udevice *dev) if (ret < 0) return ret; #endif - host->fifoth_val = MSIZE(0x2) | - RX_WMARK(priv->fifo_depth / 2 - 1) | - TX_WMARK(priv->fifo_depth / 2); - + host->fifo_depth = priv->fifo_depth; host->fifo_mode = priv->fifo_mode; #if CONFIG_IS_ENABLED(MMC_PWRSEQ) diff --git a/drivers/mmc/s5p_sdhci.c b/drivers/mmc/s5p_sdhci.c index 80dbb38c9b3..278019f02ab 100644 --- a/drivers/mmc/s5p_sdhci.c +++ b/drivers/mmc/s5p_sdhci.c @@ -166,7 +166,7 @@ static int sdhci_get_config(const void *blob, int node, struct sdhci_host *host) host->index = dev_id - PERIPH_ID_SDMMC0; /* Get bus width */ - bus_width = fdtdec_get_int(blob, node, "samsung,bus-width", 0); + bus_width = fdtdec_get_int(blob, node, "bus-width", 0); if (bus_width <= 0) { debug("MMC: Can't get bus-width\n"); return -EINVAL; diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index 560b7e889c7..4833b5158c7 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -32,8 +32,7 @@ static void sdhci_reset(struct sdhci_host *host, u8 mask) sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) { if (timeout == 0) { - printf("%s: Reset 0x%x never completed.\n", - __func__, (int)mask); + log_warning("Reset %#x never completed\n", mask); return; } timeout--; @@ -139,8 +138,7 @@ static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data) do { stat = sdhci_readl(host, SDHCI_INT_STATUS); if (stat & SDHCI_INT_ERROR) { - pr_debug("%s: Error detected in status(0x%X)!\n", - __func__, stat); + log_debug("Error detected in status(%#x)!\n", stat); return -EIO; } if (!transfer_done && (stat & rdy)) { @@ -173,7 +171,7 @@ static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data) if (timeout-- > 0) udelay(10); else { - printf("%s: Transfer data timeout\n", __func__); + log_err("Transfer data timeout\n"); return -ETIMEDOUT; } } while (!(stat & SDHCI_INT_DATA_END)); @@ -232,13 +230,13 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { if (time >= cmd_timeout) { - printf("%s: MMC: %d busy ", __func__, mmc_dev); + log_warning("mmc%d busy ", mmc_dev); if (2 * cmd_timeout <= SDHCI_CMD_MAX_TIMEOUT) { cmd_timeout += cmd_timeout; - printf("timeout increasing to: %u ms.\n", - cmd_timeout); + log_warning("timeout increasing to: %u ms\n", + cmd_timeout); } else { - puts("timeout.\n"); + log_warning("timeout\n"); return -ECOMM; } } @@ -316,8 +314,8 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, } if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) { - printf("%s: Timeout for status update: %08x %08x\n", - __func__, stat, mask); + log_warning("Timeout for status update: %08x %08x\n", + stat, mask); return -ETIMEDOUT; } } while ((stat & mask) != mask); @@ -358,7 +356,7 @@ static int sdhci_execute_tuning(struct udevice *dev, uint opcode) struct mmc *mmc = mmc_get_mmc_dev(dev); struct sdhci_host *host = mmc->priv; - debug("%s\n", __func__); + log_debug("sdhci tuning\n"); if (host->ops && host->ops->platform_execute_tuning) { err = host->ops->platform_execute_tuning(mmc, opcode); @@ -380,8 +378,7 @@ int sdhci_set_clock(struct mmc *mmc, unsigned int clock) while (sdhci_readl(host, SDHCI_PRESENT_STATE) & (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) { if (timeout == 0) { - printf("%s: Timeout to wait cmd & data inhibit\n", - __func__); + log_err("Timeout waiting for cmd & data inhibit\n"); return -EBUSY; } @@ -397,7 +394,7 @@ int sdhci_set_clock(struct mmc *mmc, unsigned int clock) if (host->ops && host->ops->set_delay) { ret = host->ops->set_delay(host); if (ret) { - printf("%s: Error while setting tap delay\n", __func__); + log_err("Error while setting tap delay\n"); return ret; } } @@ -405,7 +402,7 @@ int sdhci_set_clock(struct mmc *mmc, unsigned int clock) if (host->ops && host->ops->config_dll) { ret = host->ops->config_dll(host, clock, false); if (ret) { - printf("%s: Error while configuring dll\n", __func__); + log_err("Error configuring dll\n"); return ret; } } @@ -456,7 +453,7 @@ int sdhci_set_clock(struct mmc *mmc, unsigned int clock) if (host->ops && host->ops->config_dll) { ret = host->ops->config_dll(host, clock, true); if (ret) { - printf("%s: Error while configuring dll\n", __func__); + log_err("Error while configuring dll\n"); return ret; } } @@ -472,8 +469,7 @@ int sdhci_set_clock(struct mmc *mmc, unsigned int clock) while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) & SDHCI_CLOCK_INT_STABLE)) { if (timeout == 0) { - printf("%s: Internal clock never stabilised.\n", - __func__); + log_err("Internal clock never stabilised.\n"); return -EBUSY; } timeout--; @@ -738,8 +734,7 @@ static int sdhci_init(struct mmc *mmc) if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) { host->align_buffer = memalign(8, 512 * 1024); if (!host->align_buffer) { - printf("%s: Aligned buffer alloc failed!!!\n", - __func__); + log_err("Aligned buffer alloc failed\n"); return -ENOMEM; } } @@ -881,20 +876,18 @@ int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host, #else caps = sdhci_readl(host, SDHCI_CAPABILITIES); #endif - debug("%s, caps: 0x%x\n", __func__, caps); + log_debug("caps: %#x\n", caps); #if CONFIG_IS_ENABLED(MMC_SDHCI_SDMA) if ((caps & SDHCI_CAN_DO_SDMA)) { host->flags |= USE_SDMA; } else { - debug("%s: Your controller doesn't support SDMA!!\n", - __func__); + log_debug("Controller doesn't support SDMA\n"); } #endif #if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA) if (!(caps & SDHCI_CAN_DO_ADMA2)) { - printf("%s: Your controller doesn't support ADMA!!\n", - __func__); + log_err("Controller doesn't support ADMA\n"); return -EINVAL; } if (!host->adma_desc_table) { @@ -927,7 +920,7 @@ int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host, #else caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1); #endif - debug("%s, caps_1: 0x%x\n", __func__, caps_1); + log_debug("caps_1: %#x\n", caps_1); host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >> SDHCI_CLOCK_MUL_SHIFT; @@ -953,8 +946,7 @@ int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host, host->max_clk *= host->clk_mul; } if (host->max_clk == 0) { - printf("%s: Hardware doesn't specify base clock frequency\n", - __func__); + log_err("Hardware doesn't specify base clock frequency\n"); return -EINVAL; } if (f_max && (f_max < host->max_clk)) @@ -1047,7 +1039,7 @@ int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min) host->mmc = mmc_create(&host->cfg, host); if (host->mmc == NULL) { - printf("%s: mmc create fail!\n", __func__); + log_err("mmc create fail\n"); return -ENOMEM; } diff --git a/drivers/mmc/snps_dw_mmc.c b/drivers/mmc/snps_dw_mmc.c index 9bdbe5070b1..f30331e51f7 100644 --- a/drivers/mmc/snps_dw_mmc.c +++ b/drivers/mmc/snps_dw_mmc.c @@ -81,7 +81,7 @@ static int snps_dwmmc_of_to_plat(struct udevice *dev) host->ioaddr = dev_read_addr_ptr(dev); /* - * If fifo-depth is unset don't set fifoth_val - we will try to + * If fifo-depth is unset don't set fifo_depth - we will try to * auto detect it. */ ret = dev_read_u32(dev, "fifo-depth", &fifo_depth); @@ -89,9 +89,7 @@ static int snps_dwmmc_of_to_plat(struct udevice *dev) if (fifo_depth < FIFO_MIN || fifo_depth > FIFO_MAX) return -EINVAL; - host->fifoth_val = MSIZE(0x2) | - RX_WMARK(fifo_depth / 2 - 1) | - TX_WMARK(fifo_depth / 2); + host->fifo_depth = fifo_depth; } host->buswidth = dev_read_u32_default(dev, "bus-width", 4); diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c index f738019b835..3147d3019c0 100644 --- a/drivers/mmc/socfpga_dw_mmc.c +++ b/drivers/mmc/socfpga_dw_mmc.c @@ -134,8 +134,8 @@ static int socfpga_dwmmc_of_to_plat(struct udevice *dev) * We only have one dwmmc block on gen5 SoCFPGA. */ host->dev_index = 0; - host->fifoth_val = MSIZE(0x2) | - RX_WMARK(fifo_depth / 2 - 1) | TX_WMARK(fifo_depth / 2); + + host->fifo_depth = fifo_depth; priv->drvsel = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev), "drvsel", 3); priv->smplsel = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev), diff --git a/drivers/pinctrl/pinctrl-generic.c b/drivers/pinctrl/pinctrl-generic.c index 2464acf0b85..81a9327eb35 100644 --- a/drivers/pinctrl/pinctrl-generic.c +++ b/drivers/pinctrl/pinctrl-generic.c @@ -22,7 +22,7 @@ static int pinctrl_pin_name_to_selector(struct udevice *dev, const char *pin) if (!ops->get_pins_count || !ops->get_pin_name) { dev_dbg(dev, "get_pins_count or get_pin_name missing\n"); - return -ENOSYS; + return -ENOENT; } npins = ops->get_pins_count(dev); @@ -35,7 +35,7 @@ static int pinctrl_pin_name_to_selector(struct udevice *dev, const char *pin) return selector; } - return -ENOSYS; + return -ENOENT; } /** @@ -53,7 +53,7 @@ static int pinctrl_group_name_to_selector(struct udevice *dev, if (!ops->get_groups_count || !ops->get_group_name) { dev_dbg(dev, "get_groups_count or get_group_name missing\n"); - return -ENOSYS; + return -ENOENT; } ngroups = ops->get_groups_count(dev); @@ -66,7 +66,7 @@ static int pinctrl_group_name_to_selector(struct udevice *dev, return selector; } - return -ENOSYS; + return -ENOENT; } #if CONFIG_IS_ENABLED(PINMUX) @@ -86,7 +86,7 @@ static int pinmux_func_name_to_selector(struct udevice *dev, if (!ops->get_functions_count || !ops->get_function_name) { dev_dbg(dev, "get_functions_count or get_function_name missing\n"); - return -ENOSYS; + return -ENOENT; } nfuncs = ops->get_functions_count(dev); @@ -99,7 +99,7 @@ static int pinmux_func_name_to_selector(struct udevice *dev, return selector; } - return -ENOSYS; + return -ENOENT; } /** @@ -119,14 +119,14 @@ static int pinmux_enable_setting(struct udevice *dev, bool is_group, if (is_group) { if (!ops->pinmux_group_set) { dev_dbg(dev, "pinmux_group_set op missing\n"); - return -ENOSYS; + return -ENOENT; } return ops->pinmux_group_set(dev, selector, func_selector); } else { if (!ops->pinmux_set) { dev_dbg(dev, "pinmux_set op missing\n"); - return -ENOSYS; + return -ENOENT; } return ops->pinmux_set(dev, selector, func_selector); } @@ -162,7 +162,7 @@ static int pinconf_prop_name_to_param(struct udevice *dev, if (!ops->pinconf_num_params || !ops->pinconf_params) { dev_dbg(dev, "pinconf_num_params or pinconf_params missing\n"); - return -ENOSYS; + return -ENOENT; } p = ops->pinconf_params; @@ -176,7 +176,7 @@ static int pinconf_prop_name_to_param(struct udevice *dev, } } - return -ENOSYS; + return -ENOENT; } /** @@ -198,7 +198,7 @@ static int pinconf_enable_setting(struct udevice *dev, bool is_group, if (is_group) { if (!ops->pinconf_group_set) { dev_dbg(dev, "pinconf_group_set op missing\n"); - return -ENOSYS; + return -ENOENT; } return ops->pinconf_group_set(dev, selector, param, @@ -206,7 +206,7 @@ static int pinconf_enable_setting(struct udevice *dev, bool is_group, } else { if (!ops->pinconf_set) { dev_dbg(dev, "pinconf_set op missing\n"); - return -ENOSYS; + return -ENOENT; } return ops->pinconf_set(dev, selector, param, argument); } @@ -215,7 +215,7 @@ static int pinconf_enable_setting(struct udevice *dev, bool is_group, static int pinconf_prop_name_to_param(struct udevice *dev, const char *property, u32 *default_value) { - return -ENOSYS; + return -ENOENT; } static int pinconf_enable_setting(struct udevice *dev, bool is_group, diff --git a/drivers/power/power_i2c.c b/drivers/power/power_i2c.c index a871fc41987..c2fc1c6b42f 100644 --- a/drivers/power/power_i2c.c +++ b/drivers/power/power_i2c.c @@ -33,8 +33,6 @@ int pmic_reg_write(struct pmic *p, u32 reg, u32 val) p->bus); return -ENXIO; } -#else /* Non DM I2C support - will be removed */ - I2C_SET_BUS(p->bus); #endif switch (pmic_i2c_tx_num) { @@ -93,9 +91,6 @@ int pmic_reg_read(struct pmic *p, u32 reg, u32 *val) return -ENXIO; } ret = dm_i2c_read(dev, reg, buf, pmic_i2c_tx_num); -#else /* Non DM I2C support - will be removed */ - I2C_SET_BUS(p->bus); - ret = i2c_read(pmic_i2c_addr, reg, 1, buf, pmic_i2c_tx_num); #endif if (ret) return ret; diff --git a/drivers/spi/soft_spi.c b/drivers/spi/soft_spi.c index 9bdb4a5bff9..a8ec2f4f7b4 100644 --- a/drivers/spi/soft_spi.c +++ b/drivers/spi/soft_spi.c @@ -237,6 +237,18 @@ static int soft_spi_of_to_plat(struct udevice *dev) return 0; } +static int retrieve_num_chipselects(struct udevice *dev) +{ + int chipselects; + int ret; + + ret = ofnode_read_u32(dev_ofnode(dev), "num-chipselects", &chipselects); + if (ret) + return ret; + + return chipselects; +} + static int soft_spi_probe(struct udevice *dev) { struct spi_slave *slave = dev_get_parent_priv(dev); @@ -249,7 +261,15 @@ static int soft_spi_probe(struct udevice *dev) ret = gpio_request_by_name(dev, "cs-gpios", 0, &plat->cs, GPIOD_IS_OUT | cs_flags); - if (ret) + /* + * If num-chipselects is zero we're ignoring absence of cs-gpios. This + * code relies on the fact that `gpio_request_by_name` call above + * initiailizes plat->cs to correct value with invalid GPIO even when + * there is no cs-gpios node in dts. All other functions which work + * with plat->cs verify it via `dm_gpio_is_valid` before using it, so + * such value doesn't cause any problems. + */ + if (ret && retrieve_num_chipselects(dev) != 0) return -EINVAL; ret = gpio_request_by_name(dev, "gpio-sck", 0, &plat->sclk, @@ -271,7 +291,7 @@ static int soft_spi_probe(struct udevice *dev) ret = gpio_request_by_name(dev, "gpio-miso", 0, &plat->miso, GPIOD_IS_IN); if (ret) - ret = gpio_request_by_name(dev, "gpio-miso", 0, &plat->miso, + ret = gpio_request_by_name(dev, "miso-gpios", 0, &plat->miso, GPIOD_IS_IN); if (ret) plat->flags |= SPI_MASTER_NO_RX; diff --git a/drivers/usb/emul/sandbox_flash.c b/drivers/usb/emul/sandbox_flash.c index 24420e3d51e..b5176bb30ce 100644 --- a/drivers/usb/emul/sandbox_flash.c +++ b/drivers/usb/emul/sandbox_flash.c @@ -196,7 +196,7 @@ static int handle_ufi_command(struct sandbox_flash_priv *priv, const void *buff, priv->fd != -1) { offset = os_lseek(priv->fd, info->seek_block * info->block_size, OS_SEEK_SET); - if (offset == (off_t)-1) + if (offset < 0) setup_fail_response(priv); else setup_response(priv); diff --git a/drivers/usb/gadget/atmel_usba_udc.c b/drivers/usb/gadget/atmel_usba_udc.c index f99553df8d4..a77037a7094 100644 --- a/drivers/usb/gadget/atmel_usba_udc.c +++ b/drivers/usb/gadget/atmel_usba_udc.c @@ -7,16 +7,28 @@ * Bo Shen <voice.shen@atmel.com> */ -#include <linux/bitops.h> -#include <linux/errno.h> +#include <clk.h> +#include <dm.h> +#include <log.h> +#include <malloc.h> #include <asm/gpio.h> #include <asm/hardware.h> +#include <dm/device_compat.h> +#include <dm/devres.h> +#include <linux/bitops.h> +#include <linux/errno.h> #include <linux/list.h> -#include <linux/printk.h> #include <linux/usb/ch9.h> #include <linux/usb/gadget.h> #include <linux/usb/atmel_usba_udc.h> -#include <malloc.h> + +#if CONFIG_IS_ENABLED(DM_USB_GADGET) +#include <mach/atmel_usba_udc.h> + +static int usba_udc_start(struct usb_gadget *gadget, + struct usb_gadget_driver *driver); +static int usba_udc_stop(struct usb_gadget *gadget); +#endif /* CONFIG_IS_ENABLED(DM_USB_GADGET) */ #include "atmel_usba_udc.h" @@ -506,10 +518,32 @@ usba_udc_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered) return 0; } +static int usba_udc_pullup(struct usb_gadget *gadget, int is_on) +{ + struct usba_udc *udc = to_usba_udc(gadget); + u32 ctrl; + + ctrl = usba_readl(udc, CTRL); + + if (is_on) + ctrl &= ~USBA_DETACH; + else + ctrl |= USBA_DETACH; + + usba_writel(udc, CTRL, ctrl); + + return 0; +} + static const struct usb_gadget_ops usba_udc_ops = { .get_frame = usba_udc_get_frame, .wakeup = usba_udc_wakeup, .set_selfpowered = usba_udc_set_selfpowered, + .pullup = usba_udc_pullup, +#if CONFIG_IS_ENABLED(DM_USB_GADGET) + .udc_start = usba_udc_start, + .udc_stop = usba_udc_stop, +#endif }; static struct usb_endpoint_descriptor usba_ep0_desc = { @@ -1153,7 +1187,7 @@ static int usba_udc_irq(struct usba_udc *udc) return 0; } -static int atmel_usba_start(struct usba_udc *udc) +static int usba_udc_enable(struct usba_udc *udc) { udc->devstatus = 1 << USB_DEVICE_SELF_POWERED; @@ -1168,7 +1202,7 @@ static int atmel_usba_start(struct usba_udc *udc) return 0; } -static int atmel_usba_stop(struct usba_udc *udc) +static int usba_udc_disable(struct usba_udc *udc) { udc->gadget.speed = USB_SPEED_UNKNOWN; reset_all_endpoints(udc); @@ -1179,6 +1213,47 @@ static int atmel_usba_stop(struct usba_udc *udc) return 0; } +static struct usba_ep *usba_udc_pdata(struct usba_platform_data *pdata, + struct usba_udc *udc) +{ + struct usba_ep *eps; + int i; + + eps = malloc(sizeof(struct usba_ep) * pdata->num_ep); + if (!eps) { + log_err("failed to alloc eps\n"); + return NULL; + } + + udc->gadget.ep0 = &eps[0].ep; + + INIT_LIST_HEAD(&udc->gadget.ep_list); + INIT_LIST_HEAD(&eps[0].ep.ep_list); + + for (i = 0; i < pdata->num_ep; i++) { + struct usba_ep *ep = &eps[i]; + + ep->ep_regs = udc->regs + USBA_EPT_BASE(i); + ep->dma_regs = udc->regs + USBA_DMA_BASE(i); + ep->fifo = udc->fifo + USBA_FIFO_BASE(i); + ep->ep.ops = &usba_ep_ops; + ep->ep.name = pdata->ep[i].name; + ep->ep.maxpacket = pdata->ep[i].fifo_size; + ep->fifo_size = ep->ep.maxpacket; + ep->udc = udc; + INIT_LIST_HEAD(&ep->queue); + ep->nr_banks = pdata->ep[i].nr_banks; + ep->index = pdata->ep[i].index; + ep->can_dma = pdata->ep[i].can_dma; + ep->can_isoc = pdata->ep[i].can_isoc; + if (i) + list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list); + }; + + return eps; +} + +#if !CONFIG_IS_ENABLED(DM_USB_GADGET) static struct usba_udc controller = { .regs = (unsigned *)ATMEL_BASE_UDPHS, .fifo = (unsigned *)ATMEL_BASE_UDPHS_FIFO, @@ -1204,22 +1279,22 @@ int usb_gadget_register_driver(struct usb_gadget_driver *driver) int ret; if (!driver || !driver->bind || !driver->setup) { - printf("bad paramter\n"); + log_err("bad parameter\n"); return -EINVAL; } if (udc->driver) { - printf("UDC already has a gadget driver\n"); + log_err("UDC already has a gadget driver\n"); return -EBUSY; } - atmel_usba_start(udc); + usba_udc_enable(udc); udc->driver = driver; ret = driver->bind(&udc->gadget); if (ret) { - pr_err("driver->bind() returned %d\n", ret); + log_err("driver->bind() returned %d\n", ret); udc->driver = NULL; } @@ -1231,7 +1306,7 @@ int usb_gadget_unregister_driver(struct usb_gadget_driver *driver) struct usba_udc *udc = &controller; if (!driver || !driver->unbind || !driver->disconnect) { - pr_err("bad paramter\n"); + log_err("bad parameter\n"); return -EINVAL; } @@ -1239,58 +1314,145 @@ int usb_gadget_unregister_driver(struct usb_gadget_driver *driver) driver->unbind(&udc->gadget); udc->driver = NULL; - atmel_usba_stop(udc); + usba_udc_disable(udc); return 0; } -static struct usba_ep *usba_udc_pdata(struct usba_platform_data *pdata, - struct usba_udc *udc) +int usba_udc_probe(struct usba_platform_data *pdata) { - struct usba_ep *eps; - int i; + struct usba_udc *udc; - eps = malloc(sizeof(struct usba_ep) * pdata->num_ep); - if (!eps) { - pr_err("failed to alloc eps\n"); - return NULL; - } + udc = &controller; - udc->gadget.ep0 = &eps[0].ep; + udc->usba_ep = usba_udc_pdata(pdata, udc); - INIT_LIST_HEAD(&udc->gadget.ep_list); - INIT_LIST_HEAD(&eps[0].ep.ep_list); + return 0; +} - for (i = 0; i < pdata->num_ep; i++) { - struct usba_ep *ep = &eps[i]; +#else /* !CONFIG_IS_ENABLED(DM_USB_GADGET) */ +struct usba_priv_data { + struct clk_bulk clks; + struct usba_udc udc; +}; - ep->ep_regs = udc->regs + USBA_EPT_BASE(i); - ep->dma_regs = udc->regs + USBA_DMA_BASE(i); - ep->fifo = udc->fifo + USBA_FIFO_BASE(i); - ep->ep.ops = &usba_ep_ops; - ep->ep.name = pdata->ep[i].name; - ep->ep.maxpacket = pdata->ep[i].fifo_size; - ep->fifo_size = ep->ep.maxpacket; - ep->udc = udc; - INIT_LIST_HEAD(&ep->queue); - ep->nr_banks = pdata->ep[i].nr_banks; - ep->index = pdata->ep[i].index; - ep->can_dma = pdata->ep[i].can_dma; - ep->can_isoc = pdata->ep[i].can_isoc; - if (i) - list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list); - }; +static int usba_udc_start(struct usb_gadget *gadget, + struct usb_gadget_driver *driver) +{ + struct usba_udc *udc = to_usba_udc(gadget); - return eps; + usba_udc_enable(udc); + + udc->driver = driver; + return 0; } -int usba_udc_probe(struct usba_platform_data *pdata) +static int usba_udc_stop(struct usb_gadget *gadget) { - struct usba_udc *udc; + struct usba_udc *udc = to_usba_udc(gadget); - udc = &controller; + udc->driver = NULL; - udc->usba_ep = usba_udc_pdata(pdata, udc); + usba_udc_disable(udc); + return 0; +} + +static int usba_udc_clk_init(struct udevice *dev, struct clk_bulk *clks) +{ + int ret; + + ret = clk_get_bulk(dev, clks); + if (ret == -ENOSYS) + return 0; + + if (ret) + return ret; + + ret = clk_enable_bulk(clks); + if (ret) { + clk_release_bulk(clks); + return ret; + } return 0; } + +static int usba_udc_probe(struct udevice *dev) +{ + struct usba_priv_data *priv = dev_get_priv(dev); + struct usba_udc *udc = &priv->udc; + int ret; + + udc->fifo = (void __iomem *)dev_remap_addr_index(dev, FIFO_IOMEM_ID); + if (!udc->fifo) + return -EINVAL; + + udc->regs = (void __iomem *)dev_remap_addr_index(dev, CTRL_IOMEM_ID); + if (!udc->regs) + return -EINVAL; + + ret = usba_udc_clk_init(dev, &priv->clks); + if (ret) + return ret; + + udc->usba_ep = usba_udc_pdata(&pdata, udc); + + udc->gadget.ops = &usba_udc_ops; + udc->gadget.speed = USB_SPEED_HIGH, + udc->gadget.is_dualspeed = 1, + udc->gadget.name = "atmel_usba_udc", + + ret = usb_add_gadget_udc((struct device *)dev, &udc->gadget); + if (ret) + goto err; + + return 0; +err: + free(udc->usba_ep); + + clk_release_bulk(&priv->clks); + + return ret; +} + +static int usba_udc_remove(struct udevice *dev) +{ + struct usba_priv_data *priv = dev_get_priv(dev); + + usb_del_gadget_udc(&priv->udc.gadget); + + free(priv->udc.usba_ep); + + clk_release_bulk(&priv->clks); + + return dm_scan_fdt_dev(dev); +} + +static int usba_udc_handle_interrupts(struct udevice *dev) +{ + struct usba_priv_data *priv = dev_get_priv(dev); + + return usba_udc_irq(&priv->udc); +} + +static const struct usb_gadget_generic_ops usba_udc_gadget_ops = { + .handle_interrupts = usba_udc_handle_interrupts, +}; + +static const struct udevice_id usba_udc_ids[] = { + { .compatible = "atmel,at91sam9rl-udc" }, + { .compatible = "atmel,at91sam9g45-udc" }, + { .compatible = "atmel,sama5d3-udc" }, + {} +}; + +U_BOOT_DRIVER(atmel_usba_udc) = { + .name = "atmel_usba_udc", + .id = UCLASS_USB_GADGET_GENERIC, + .of_match = usba_udc_ids, + .ops = &usba_udc_gadget_ops, + .probe = usba_udc_probe, + .remove = usba_udc_remove, + .priv_auto = sizeof(struct usba_priv_data), +}; +#endif /* !CONFIG_IS_ENABLED(DM_USB_GADGET) */ diff --git a/drivers/usb/gadget/atmel_usba_udc.h b/drivers/usb/gadget/atmel_usba_udc.h index f6cb48c1cff..7f5e98f6c4c 100644 --- a/drivers/usb/gadget/atmel_usba_udc.h +++ b/drivers/usb/gadget/atmel_usba_udc.h @@ -211,6 +211,9 @@ #define EP0_EPT_SIZE USBA_EPT_SIZE_64 #define EP0_NR_BANKS 1 +#define FIFO_IOMEM_ID 0 +#define CTRL_IOMEM_ID 1 + #define DBG_ERR 0x0001 /* report all error returns */ #define DBG_HW 0x0002 /* debug hardware initialization */ #define DBG_GADGET 0x0004 /* calls to/from gadget driver */ diff --git a/drivers/usb/gadget/f_sdp.c b/drivers/usb/gadget/f_sdp.c index 514c097591b..5d62eb475d0 100644 --- a/drivers/usb/gadget/f_sdp.c +++ b/drivers/usb/gadget/f_sdp.c @@ -842,9 +842,7 @@ static int sdp_handle_in_ep(struct spl_image_info *spl_image, struct spl_load_info load; debug("Found FIT\n"); - load.priv = header; - spl_set_bl_len(&load, 1); - load.read = sdp_load_read; + spl_load_init(&load, sdp_load_read, header, 1); spl_load_simple_fit(spl_image, &load, 0, header); @@ -855,9 +853,7 @@ static int sdp_handle_in_ep(struct spl_image_info *spl_image, valid_container_hdr((void *)header)) { struct spl_load_info load; - load.priv = header; - spl_set_bl_len(&load, 1); - load.read = sdp_load_read; + spl_load_init(&load, sdp_load_read, header, 1); spl_load_imx_container(spl_image, &load, 0); return SDP_EXIT; } diff --git a/drivers/usb/gadget/udc/udc-uclass.c b/drivers/usb/gadget/udc/udc-uclass.c index fbe62bbce47..723d1cdfd78 100644 --- a/drivers/usb/gadget/udc/udc-uclass.c +++ b/drivers/usb/gadget/udc/udc-uclass.c @@ -83,7 +83,7 @@ __weak int dm_usb_gadget_handle_interrupts(struct udevice *dev) #if CONFIG_IS_ENABLED(DM) UCLASS_DRIVER(usb_gadget_generic) = { .id = UCLASS_USB_GADGET_GENERIC, - .name = "usb", + .name = "usb_gadget", .flags = DM_UC_FLAG_SEQ_ALIAS, }; #endif diff --git a/drivers/usb/host/ohci-lpc32xx.c b/drivers/usb/host/ohci-lpc32xx.c index ed04cae7afe..bf89bf8ab49 100644 --- a/drivers/usb/host/ohci-lpc32xx.c +++ b/drivers/usb/host/ohci-lpc32xx.c @@ -94,10 +94,6 @@ static int isp1301_set_value(struct udevice *dev, int reg, u8 value) static void isp1301_configure(struct udevice *dev) { -#if !CONFIG_IS_ENABLED(DM_I2C) - i2c_set_bus_num(I2C_2); -#endif - /* * LPC32XX only supports DAT_SE0 USB mode * This sequence is important diff --git a/drivers/video/imx/mxc_ipuv3_fb.c b/drivers/video/imx/mxc_ipuv3_fb.c index 039b22086a9..fdeb3cabea7 100644 --- a/drivers/video/imx/mxc_ipuv3_fb.c +++ b/drivers/video/imx/mxc_ipuv3_fb.c @@ -403,7 +403,6 @@ static int mxcfb_map_video_memory(struct fb_info *fbi) (uint32_t) fbi->fix.smem_start, fbi->fix.smem_len); fbi->screen_size = fbi->fix.smem_len; - gd->fb_base = fbi->fix.smem_start; /* Clear the screen */ memset((char *)fbi->screen_base, 0, fbi->fix.smem_len); @@ -633,7 +632,6 @@ static int ipuv3_video_probe(struct udevice *dev) mmu_set_region_dcache_behaviour(fb_start, fb_end - fb_start, DCACHE_WRITEBACK); video_set_flush_dcache(dev, true); - gd->fb_base = fb_start; return 0; } diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c index 792d6314d15..e72839cead4 100644 --- a/drivers/video/mxsfb.c +++ b/drivers/video/mxsfb.c @@ -335,7 +335,6 @@ static int mxs_video_probe(struct udevice *dev) mmu_set_region_dcache_behaviour(fb_start, fb_end - fb_start, DCACHE_WRITEBACK); video_set_flush_dcache(dev, true); - gd->fb_base = plat->base; return ret; } diff --git a/drivers/video/video-uclass.c b/drivers/video/video-uclass.c index a5aa8dd5295..41bb7647fda 100644 --- a/drivers/video/video-uclass.c +++ b/drivers/video/video-uclass.c @@ -145,13 +145,26 @@ int video_reserve(ulong *addrp) *addrp -= CONFIG_VAL(VIDEO_PCI_DEFAULT_FB_SIZE); gd->video_bottom = *addrp; - gd->fb_base = *addrp; debug("Video frame buffers from %lx to %lx\n", gd->video_bottom, gd->video_top); return 0; } +ulong video_get_fb(void) +{ + struct udevice *dev; + + uclass_find_first_device(UCLASS_VIDEO, &dev); + if (dev) { + const struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev); + + return uc_plat->base; + } + + return 0; +} + int video_fill_part(struct udevice *dev, int xstart, int ystart, int xend, int yend, u32 colour) { @@ -210,7 +223,6 @@ int video_reserve_from_bloblist(struct video_handoff *ho) return -ENOENT; gd->video_bottom = ho->fb; - gd->fb_base = ho->fb; gd->video_top = ho->fb + ho->size; debug("%s: Reserving %lx bytes at %08x as per bloblist received\n", __func__, (unsigned long)ho->size, (u32)ho->fb); diff --git a/drivers/video/zynqmp/zynqmp_dpsub.c b/drivers/video/zynqmp/zynqmp_dpsub.c index 1405b29cb8b..76abfeac443 100644 --- a/drivers/video/zynqmp/zynqmp_dpsub.c +++ b/drivers/video/zynqmp/zynqmp_dpsub.c @@ -49,7 +49,7 @@ static void dma_init_video_descriptor(struct udevice *dev) DPDMA_DESCRIPTOR_ADDR_EXT_SRC_ADDR_EXT_SHIFT) | (upper_32_bits((u64)&cur_desc))); cur_desc.next_desr = lower_32_bits((u64)&cur_desc); - cur_desc.src_addr = lower_32_bits((u64)gd->fb_base); + cur_desc.src_addr = lower_32_bits((u64)video_get_fb()); } static void dma_set_descriptor_address(struct udevice *dev) @@ -2134,7 +2134,6 @@ static int zynqmp_dpsub_probe(struct udevice *dev) dev_dbg(dev, "BPP in bits %d, bpix %d\n", priv->non_live_graphics->bpp, uc_priv->bpix); - uc_priv->fb = (void *)gd->fb_base; uc_priv->xsize = vidc_video_timing_modes[priv->video_mode].video_timing.h_active; uc_priv->ysize = vidc_video_timing_modes[priv->video_mode].video_timing.v_active; /* Calculated by core but need it for my own setup */ |