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-rw-r--r--drivers/clk/clk_versal.c4
-rw-r--r--drivers/gpio/zynqmp_gpio_modepin.c3
-rw-r--r--drivers/mmc/zynq_sdhci.c2
-rw-r--r--drivers/mtd/spi/spi-nor-ids.c68
-rw-r--r--drivers/net/zynq_gem.c42
-rw-r--r--drivers/pinctrl/pinctrl-uclass.c34
-rw-r--r--drivers/soc/soc_xilinx_zynqmp.c2
7 files changed, 125 insertions, 30 deletions
diff --git a/drivers/clk/clk_versal.c b/drivers/clk/clk_versal.c
index 76fde00491b..faebbab1c6d 100644
--- a/drivers/clk/clk_versal.c
+++ b/drivers/clk/clk_versal.c
@@ -657,7 +657,9 @@ static int versal_clk_probe(struct udevice *dev)
if (ret < 0)
return -EINVAL;
- versal_clock_setup();
+ ret = versal_clock_setup();
+ if (ret < 0)
+ return ret;
priv->clk = clock;
diff --git a/drivers/gpio/zynqmp_gpio_modepin.c b/drivers/gpio/zynqmp_gpio_modepin.c
index 078fd833959..e9565ff5430 100644
--- a/drivers/gpio/zynqmp_gpio_modepin.c
+++ b/drivers/gpio/zynqmp_gpio_modepin.c
@@ -48,6 +48,9 @@ static int modepin_gpio_set_value(struct udevice *dev, unsigned int offset,
int ret;
ret = get_gpio_modepin(ret_payload);
+ if (ret)
+ return ret;
+
if (value)
out_val = OUTVAL(offset) | ret_payload[1];
else
diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index 7dcf6ad8422..be4075c97a4 100644
--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c
@@ -249,7 +249,7 @@ static int arasan_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
u32 ctrl;
struct sdhci_host *host;
struct arasan_sdhci_priv *priv = dev_get_priv(mmc->dev);
- char tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT;
+ int tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT;
dev_dbg(mmc->dev, "%s\n", __func__);
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index a862fbd707b..3f8b7967893 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -118,6 +118,36 @@ const struct flash_info spi_nor_ids[] = {
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
},
+ /* adding these 3V QSPI flash parts */
+ {INFO("gd25b256", 0xc84019, 0, 64 * 1024, 512, SECT_4K |
+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES) },
+ {INFO("gd25b512", 0xc8471A, 0, 64 * 1024, 1024, SECT_4K |
+ SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+ {INFO("gd55b01g", 0xc8471B, 0, 64 * 1024, 2048, SECT_4K |
+ SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+ {INFO("gd55b02g", 0xc8471C, 0, 64 * 1024, 4096, SECT_4K |
+ SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+ {INFO("gd25f64", 0xc84317, 0, 64 * 1024, 128, SECT_4K |
+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)},
+ {INFO("gd25f128", 0xc84318, 0, 64 * 1024, 256, SECT_4K |
+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)},
+ {INFO("gd25f256", 0xc84319, 0, 64 * 1024, 512, SECT_4K |
+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+ {INFO("gd55f512", 0xc8431A, 0, 64 * 1024, 1024, SECT_4K |
+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+ {INFO("gd25t512", 0xc8461A, 0, 64 * 1024, 1024, SECT_4K |
+ SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+ {INFO("gd55t01g", 0xc8461B, 0, 64 * 1024, 2048, SECT_4K |
+ SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+ {INFO("gd55t02g", 0xc8461C, 0, 64 * 1024, 4096, SECT_4K |
+ SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+ /* adding these 3V OSPI flash parts */
+ {INFO("gd25x512", 0xc8481A, 0, 64 * 1024, 1024, SECT_4K |
+ SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)},
+ {INFO("gd55x01g", 0xc8481B, 0, 64 * 1024, 2048, SECT_4K |
+ SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)},
+ {INFO("gd55x02g", 0xc8481C, 0, 64 * 1024, 4096, SECT_4K |
+ SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)},
{
INFO("gd25lq128", 0xc86018, 0, 64 * 1024, 256,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
@@ -128,10 +158,48 @@ const struct flash_info spi_nor_ids[] = {
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
},
+ /* adding these 1.8V QSPI flash parts */
+ {INFO("gd25lb256", 0xc86719, 0, 64 * 1024, 512, SECT_4K |
+ SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+ {INFO("gd25lb512", 0xc8671A, 0, 64 * 1024, 1024, SECT_4K |
+ SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+ {INFO("gd55lb01g", 0xc8671B, 0, 64 * 1024, 2048, SECT_4K |
+ SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+ {INFO("gd55lb02g", 0xc8671C, 0, 64 * 1024, 4096, SECT_4K |
+ SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+ {INFO("gd25lf80", 0xc86314, 0, 64 * 1024, 16, SECT_4K |
+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)},
+ {INFO("gd25lf16", 0xc86315, 0, 64 * 1024, 32, SECT_4K |
+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)},
+ {INFO("gd25lf32", 0xc86316, 0, 64 * 1024, 64, SECT_4K |
+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK) },
+ {INFO("gd25lf64", 0xc86317, 0, 64 * 1024, 128, SECT_4K |
+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK) },
+ {INFO("gd25lf128", 0xc86318, 0, 64 * 1024, 256, SECT_4K |
+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK) },
+ {INFO("gd25lf255", 0xc86319, 0, 64 * 1024, 512, SECT_4K |
+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+ {INFO("gd25lf511", 0xc8631A, 0, 64 * 1024, 1024, SECT_4K |
+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+ {INFO("gd25lt256", 0xc86619, 0, 64 * 1024, 512, SECT_4K |
+ SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+ {INFO("gd25lt512", 0xc8661A, 0, 64 * 1024, 1024, SECT_4K |
+ SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+ {INFO("gd55lt01g", 0xc8661B, 0, 64 * 1024, 2048, SECT_4K |
+ SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+ {INFO("gd55lt02g", 0xc8661C, 0, 64 * 1024, 4096, SECT_4K |
+ SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
{
INFO("gd25lx256e", 0xc86819, 0, 64 * 1024, 512,
SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)
},
+ /* adding these 1.8V OSPI flash parts */
+ {INFO("gd25lx512", 0xc8681A, 0, 64 * 1024, 1024, SECT_4K |
+ SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)},
+ {INFO("gd55lx01g", 0xc8681B, 0, 64 * 1024, 2048, SECT_4K |
+ SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)},
+ {INFO("gd55lx02g", 0xc8681C, 0, 64 * 1024, 4096, SECT_4K |
+ SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)},
#endif
#ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */
/* ISSI */
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index 507b19b7597..cc49788012f 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -125,6 +125,10 @@
*/
#define PHY_DETECT_MASK 0x1808
+/* PCS (SGMII) Link Status */
+#define ZYNQ_GEM_PCSSTATUS_LINK BIT(2)
+#define ZYNQ_GEM_PCSSTATUS_ANEG_COMPL BIT(5)
+
/* TX BD status masks */
#define ZYNQ_GEM_TXBUF_FRMLEN_MASK 0x000007ff
#define ZYNQ_GEM_TXBUF_EXHAUSTED 0x08000000
@@ -164,7 +168,8 @@ struct zynq_gem_regs {
u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */
u32 reserved9[20];
u32 pcscntrl;
- u32 rserved12[36];
+ u32 pcsstatus;
+ u32 rserved12[35];
u32 dcfg6; /* 0x294 Design config reg6 */
u32 reserved7[106];
u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */
@@ -491,12 +496,37 @@ static int zynq_gem_init(struct udevice *dev)
* Must be written after PCS_SEL is set in nwconfig,
* otherwise writes will not take effect.
*/
- if (priv->phydev->phy_id != PHY_FIXED_ID)
+ if (priv->phydev->phy_id != PHY_FIXED_ID) {
writel(readl(&regs->pcscntrl) | ZYNQ_GEM_PCS_CTL_ANEG_ENBL,
&regs->pcscntrl);
- else
+ /*
+ * When the PHY link is already up, the PCS link needs
+ * to get re-checked
+ */
+ if (priv->phydev->link) {
+ u32 pcsstatus;
+
+ pcsstatus = ZYNQ_GEM_PCSSTATUS_LINK |
+ ZYNQ_GEM_PCSSTATUS_ANEG_COMPL;
+ ret = wait_for_bit_le32(&regs->pcsstatus,
+ pcsstatus,
+ true, 5000, true);
+ if (ret) {
+ dev_warn(dev,
+ "no PCS (SGMII) link\n");
+ } else {
+ /*
+ * Some additional minimal delay seems
+ * to be needed so that the first
+ * packet will be sent correctly
+ */
+ mdelay(1);
+ }
+ }
+ } else {
writel(readl(&regs->pcscntrl) & ~ZYNQ_GEM_PCS_CTL_ANEG_ENBL,
&regs->pcscntrl);
+ }
}
#endif
@@ -821,7 +851,8 @@ static int zynq_gem_probe(struct udevice *dev)
if (priv->interface == PHY_INTERFACE_MODE_SGMII && phy.dev) {
if (IS_ENABLED(CONFIG_DM_ETH_PHY)) {
- if (device_is_compatible(dev, "cdns,zynqmp-gem")) {
+ if (device_is_compatible(dev, "cdns,zynqmp-gem") ||
+ device_is_compatible(dev, "xlnx,zynqmp-gem")) {
ret = gem_zynqmp_set_dynamic_config(dev);
if (ret) {
dev_err
@@ -922,8 +953,11 @@ static int zynq_gem_of_to_plat(struct udevice *dev)
}
static const struct udevice_id zynq_gem_ids[] = {
+ { .compatible = "xlnx,versal-gem", .data = RXCLK_EN },
{ .compatible = "cdns,versal-gem", .data = RXCLK_EN },
+ { .compatible = "xlnx,zynqmp-gem" },
{ .compatible = "cdns,zynqmp-gem" },
+ { .compatible = "xlnx,zynq-gem" },
{ .compatible = "cdns,zynq-gem" },
{ .compatible = "cdns,gem" },
{ }
diff --git a/drivers/pinctrl/pinctrl-uclass.c b/drivers/pinctrl/pinctrl-uclass.c
index a1b85ca87e5..8837726cc16 100644
--- a/drivers/pinctrl/pinctrl-uclass.c
+++ b/drivers/pinctrl/pinctrl-uclass.c
@@ -20,7 +20,6 @@
DECLARE_GLOBAL_DATA_PTR;
-#if CONFIG_IS_ENABLED(PINCTRL_FULL)
/**
* pinctrl_config_one() - apply pinctrl settings for a single node
*
@@ -71,13 +70,13 @@ static int pinctrl_select_state_full(struct udevice *dev, const char *statename)
*/
state = dectoul(statename, &end);
if (*end)
- return -EINVAL;
+ return -ENOSYS;
}
snprintf(propname, sizeof(propname), "pinctrl-%d", state);
list = dev_read_prop(dev, propname, &size);
if (!list)
- return -EINVAL;
+ return -ENOSYS;
size /= sizeof(*list);
for (i = 0; i < size; i++) {
@@ -148,6 +147,7 @@ static int pinconfig_post_bind(struct udevice *dev)
return 0;
}
+#if CONFIG_IS_ENABLED(PINCTRL_FULL)
UCLASS_DRIVER(pinconfig) = {
.id = UCLASS_PINCONFIG,
#if CONFIG_IS_ENABLED(PINCONF_RECURSIVE)
@@ -160,17 +160,6 @@ U_BOOT_DRIVER(pinconfig_generic) = {
.name = "pinconfig",
.id = UCLASS_PINCONFIG,
};
-
-#else
-static int pinctrl_select_state_full(struct udevice *dev, const char *statename)
-{
- return -ENODEV;
-}
-
-static int pinconfig_post_bind(struct udevice *dev)
-{
- return 0;
-}
#endif
static int
@@ -317,10 +306,10 @@ int pinctrl_select_state(struct udevice *dev, const char *statename)
* Try full-implemented pinctrl first.
* If it fails or is not implemented, try simple one.
*/
- if (pinctrl_select_state_full(dev, statename))
- return pinctrl_select_state_simple(dev);
+ if (CONFIG_IS_ENABLED(PINCTRL_FULL))
+ return pinctrl_select_state_full(dev, statename);
- return 0;
+ return pinctrl_select_state_simple(dev);
}
int pinctrl_request(struct udevice *dev, int func, int flags)
@@ -393,7 +382,7 @@ int pinctrl_get_pin_muxing(struct udevice *dev, int selector, char *buf,
}
/**
- * pinconfig_post_bind() - post binding for PINCTRL uclass
+ * pinctrl_post_bind() - post binding for PINCTRL uclass
* Recursively bind child nodes as pinconfig devices in case of full pinctrl.
*
* @dev: pinctrl device
@@ -409,12 +398,11 @@ static int __maybe_unused pinctrl_post_bind(struct udevice *dev)
}
/*
- * If set_state callback is set, we assume this pinctrl driver is the
- * full implementation. In this case, its child nodes should be bound
- * so that peripheral devices can easily search in parent devices
- * during later DT-parsing.
+ * If the pinctrl driver has the full implementation, its child nodes
+ * should be bound so that peripheral devices can easily search in
+ * parent devices during later DT-parsing.
*/
- if (ops->set_state)
+ if (CONFIG_IS_ENABLED(PINCTRL_FULL))
return pinconfig_post_bind(dev);
return 0;
diff --git a/drivers/soc/soc_xilinx_zynqmp.c b/drivers/soc/soc_xilinx_zynqmp.c
index a51bcdb478f..afa277f6049 100644
--- a/drivers/soc/soc_xilinx_zynqmp.c
+++ b/drivers/soc/soc_xilinx_zynqmp.c
@@ -186,7 +186,7 @@ static const struct zynqmp_device zynqmp_devices[] = {
.variants = ZYNQMP_VARIANT_DR,
},
{
- .id = 0x04714093,
+ .id = 0x04712093,
.device = 24,
.variants = 0,
},
generated by cgit v1.2.3 (git 2.0.4) at 2025-08-03 08:51:59 +0000