diff options
Diffstat (limited to 'drivers')
121 files changed, 8241 insertions, 873 deletions
diff --git a/drivers/adc/meson-saradc.c b/drivers/adc/meson-saradc.c index 13a8f49dc50..21db55831d8 100644 --- a/drivers/adc/meson-saradc.c +++ b/drivers/adc/meson-saradc.c @@ -282,7 +282,7 @@ static int meson_saradc_read_raw_sample(struct meson_saradc_priv *priv, regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, ®val); fifo_chan = FIELD_GET(MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK, regval); if (fifo_chan != channel) { - printf("ADC FIFO entry belongs to channel %d instead of %d\n", + printf("ADC FIFO entry belongs to channel %u instead of %u\n", fifo_chan, channel); return -EINVAL; } @@ -512,8 +512,11 @@ static int meson_saradc_init(struct meson_saradc_priv *priv) * reading the temperature sensor. */ regmap_read(priv->regmap, MESON_SAR_ADC_REG3, ®val); - if (regval & MESON_SAR_ADC_REG3_BL30_INITIALIZED) - return 0; + if (regval & MESON_SAR_ADC_REG3_BL30_INITIALIZED) { + regmap_read(priv->regmap, MESON_SAR_ADC_REG3, ®val); + if (regval & MESON_SAR_ADC_REG3_ADC_EN) + return 0; + } meson_saradc_stop_sample_engine(priv); @@ -711,6 +714,8 @@ static const struct udevice_id meson_saradc_ids[] = { .data = (ulong)&gxl_saradc_data }, { .compatible = "amlogic,meson-gxm-saradc", .data = (ulong)&gxl_saradc_data }, + { .compatible = "amlogic,meson-g12a-saradc", + .data = (ulong)&gxl_saradc_data }, { } }; diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index db06f276ec2..4aeaa0cd589 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -165,6 +165,7 @@ source "drivers/clk/exynos/Kconfig" source "drivers/clk/imx/Kconfig" source "drivers/clk/kendryte/Kconfig" source "drivers/clk/meson/Kconfig" +source "drivers/clk/microchip/Kconfig" source "drivers/clk/mvebu/Kconfig" source "drivers/clk/owl/Kconfig" source "drivers/clk/renesas/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index f8383e523d6..645709b855e 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -30,6 +30,7 @@ obj-$(CONFIG_$(SPL_TPL_)CLK_INTEL) += intel/ obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o obj-$(CONFIG_CLK_K210) += kendryte/ obj-$(CONFIG_CLK_MPC83XX) += mpc83xx_clk.o +obj-$(CONFIG_CLK_MPFS) += microchip/ obj-$(CONFIG_CLK_OCTEON) += clk_octeon.o obj-$(CONFIG_CLK_OWL) += owl/ obj-$(CONFIG_CLK_RENESAS) += renesas/ diff --git a/drivers/clk/aspeed/Makefile b/drivers/clk/aspeed/Makefile index 81764b43917..84776e5265e 100644 --- a/drivers/clk/aspeed/Makefile +++ b/drivers/clk/aspeed/Makefile @@ -4,3 +4,4 @@ # obj-$(CONFIG_ASPEED_AST2500) += clk_ast2500.o +obj-$(CONFIG_ASPEED_AST2600) += clk_ast2600.o diff --git a/drivers/clk/aspeed/clk_ast2600.c b/drivers/clk/aspeed/clk_ast2600.c new file mode 100644 index 00000000000..f72d384047f --- /dev/null +++ b/drivers/clk/aspeed/clk_ast2600.c @@ -0,0 +1,1173 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) ASPEED Technology Inc. + */ + +#include <common.h> +#include <clk-uclass.h> +#include <dm.h> +#include <asm/io.h> +#include <dm/lists.h> +#include <linux/delay.h> +#include <asm/arch/scu_ast2600.h> +#include <dt-bindings/clock/ast2600-clock.h> +#include <dt-bindings/reset/ast2600-reset.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define CLKIN_25M 25000000UL + +/* MAC Clock Delay settings */ +#define MAC12_DEF_DELAY_1G 0x0041b75d +#define MAC12_DEF_DELAY_100M 0x00417410 +#define MAC12_DEF_DELAY_10M 0x00417410 +#define MAC34_DEF_DELAY_1G 0x0010438a +#define MAC34_DEF_DELAY_100M 0x00104208 +#define MAC34_DEF_DELAY_10M 0x00104208 + +/* + * 3-bit encode of CPU freqeucy + * Some code is duplicated + */ +enum ast2600_cpu_freq { + CPU_FREQ_1200M_1, + CPU_FREQ_1600M_1, + CPU_FREQ_1200M_2, + CPU_FREQ_1600M_2, + CPU_FREQ_800M_1, + CPU_FREQ_800M_2, + CPU_FREQ_800M_3, + CPU_FREQ_800M_4, +}; + +struct ast2600_clk_priv { + struct ast2600_scu *scu; +}; + +/* + * Clock divider/multiplier configuration struct. + * For H-PLL and M-PLL the formula is + * (Output Frequency) = CLKIN * ((M + 1) / (N + 1)) / (P + 1) + * M - Numerator + * N - Denumerator + * P - Post Divider + * They have the same layout in their control register. + * + * D-PLL and D2-PLL have extra divider (OD + 1), which is not + * yet needed and ignored by clock configurations. + */ +union ast2600_pll_reg { + uint32_t w; + struct { + unsigned int m : 13; + unsigned int n : 6; + unsigned int p : 4; + unsigned int off : 1; + unsigned int bypass : 1; + unsigned int reset : 1; + unsigned int reserved : 6; + } b; +}; + +struct ast2600_pll_cfg { + union ast2600_pll_reg reg; + unsigned int ext_reg; +}; + +struct ast2600_pll_desc { + uint32_t in; + uint32_t out; + struct ast2600_pll_cfg cfg; +}; + +static const struct ast2600_pll_desc ast2600_pll_lookup[] = { + { + .in = CLKIN_25M, + .out = 400000000, + .cfg.reg.b.m = 95, + .cfg.reg.b.n = 2, + .cfg.reg.b.p = 1, + .cfg.ext_reg = 0x31, + }, + { + .in = CLKIN_25M, + .out = 200000000, + .cfg.reg.b.m = 127, + .cfg.reg.b.n = 0, + .cfg.reg.b.p = 15, + .cfg.ext_reg = 0x3f, + }, + { + .in = CLKIN_25M, + .out = 334000000, + .cfg.reg.b.m = 667, + .cfg.reg.b.n = 4, + .cfg.reg.b.p = 9, + .cfg.ext_reg = 0x14d, + }, + { + .in = CLKIN_25M, + .out = 1000000000, + .cfg.reg.b.m = 119, + .cfg.reg.b.n = 2, + .cfg.reg.b.p = 0, + .cfg.ext_reg = 0x3d, + }, + { + .in = CLKIN_25M, + .out = 50000000, + .cfg.reg.b.m = 95, + .cfg.reg.b.n = 2, + .cfg.reg.b.p = 15, + .cfg.ext_reg = 0x31, + }, +}; + +/* divisor tables */ +static uint32_t axi_ahb_div0_table[] = { + 3, 2, 3, 4, +}; + +static uint32_t axi_ahb_div1_table[] = { + 3, 4, 6, 8, +}; + +static uint32_t axi_ahb_default_table[] = { + 3, 4, 3, 4, 2, 2, 2, 2, +}; + +extern uint32_t ast2600_get_pll_rate(struct ast2600_scu *scu, int pll_idx) +{ + union ast2600_pll_reg pll_reg; + uint32_t hwstrap1; + uint32_t cpu_freq; + uint32_t mul = 1, div = 1; + + switch (pll_idx) { + case ASPEED_CLK_APLL: + pll_reg.w = readl(&scu->apll); + break; + case ASPEED_CLK_DPLL: + pll_reg.w = readl(&scu->dpll); + break; + case ASPEED_CLK_EPLL: + pll_reg.w = readl(&scu->epll); + break; + case ASPEED_CLK_HPLL: + pll_reg.w = readl(&scu->hpll); + break; + case ASPEED_CLK_MPLL: + pll_reg.w = readl(&scu->mpll); + break; + } + + if (!pll_reg.b.bypass) { + /* F = 25Mhz * [(M + 2) / (n + 1)] / (p + 1) + * HPLL Numerator (M) = fix 0x5F when SCU500[10]=1 + * Fixed 0xBF when SCU500[10]=0 and SCU500[8]=1 + * SCU200[12:0] (default 0x8F) when SCU510[10]=0 and SCU510[8]=0 + * HPLL Denumerator (N) = SCU200[18:13] (default 0x2) + * HPLL Divider (P) = SCU200[22:19] (default 0x0) + * HPLL Bandwidth Adj (NB) = fix 0x2F when SCU500[10]=1 + * Fixed 0x5F when SCU500[10]=0 and SCU500[8]=1 + * SCU204[11:0] (default 0x31) when SCU500[10]=0 and SCU500[8]=0 + */ + if (pll_idx == ASPEED_CLK_HPLL) { + hwstrap1 = readl(&scu->hwstrap1); + cpu_freq = (hwstrap1 & SCU_HWSTRAP1_CPU_FREQ_MASK) >> + SCU_HWSTRAP1_CPU_FREQ_SHIFT; + + switch (cpu_freq) { + case CPU_FREQ_800M_1: + case CPU_FREQ_800M_2: + case CPU_FREQ_800M_3: + case CPU_FREQ_800M_4: + pll_reg.b.m = 0x5f; + break; + case CPU_FREQ_1600M_1: + case CPU_FREQ_1600M_2: + pll_reg.b.m = 0xbf; + break; + default: + pll_reg.b.m = 0x8f; + break; + } + } + + mul = (pll_reg.b.m + 1) / (pll_reg.b.n + 1); + div = (pll_reg.b.p + 1); + } + + return ((CLKIN_25M * mul) / div); +} + +static uint32_t ast2600_get_hclk_rate(struct ast2600_scu *scu) +{ + uint32_t rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); + uint32_t axi_div, ahb_div; + uint32_t hwstrap1 = readl(&scu->hwstrap1); + uint32_t cpu_freq = (hwstrap1 & SCU_HWSTRAP1_CPU_FREQ_MASK) >> + SCU_HWSTRAP1_CPU_FREQ_SHIFT; + uint32_t axi_ahb_ratio = (hwstrap1 & SCU_HWSTRAP1_AXI_AHB_CLK_RATIO_MASK) >> + SCU_HWSTRAP1_AXI_AHB_CLK_RATIO_SHIFT; + + if (hwstrap1 & SCU_HWSTRAP1_CPU_AXI_CLK_RATIO) { + axi_ahb_div1_table[0] = axi_ahb_default_table[cpu_freq] * 2; + axi_div = 1; + ahb_div = axi_ahb_div1_table[axi_ahb_ratio]; + } else { + axi_ahb_div0_table[0] = axi_ahb_default_table[cpu_freq]; + axi_div = 2; + ahb_div = axi_ahb_div0_table[axi_ahb_ratio]; + } + + return (rate / axi_div / ahb_div); +} + +static uint32_t ast2600_get_bclk_rate(struct ast2600_scu *scu) +{ + uint32_t rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); + uint32_t clksrc1 = readl(&scu->clksrc1); + uint32_t bclk_div = (clksrc1 & SCU_CLKSRC1_BCLK_DIV_MASK) >> + SCU_CLKSRC1_BCLK_DIV_SHIFT; + + return (rate / ((bclk_div + 1) * 4)); +} + +static uint32_t ast2600_get_pclk1_rate(struct ast2600_scu *scu) +{ + uint32_t rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); + uint32_t clksrc1 = readl(&scu->clksrc1); + uint32_t pclk_div = (clksrc1 & SCU_CLKSRC1_PCLK_DIV_MASK) >> + SCU_CLKSRC1_PCLK_DIV_SHIFT; + + return (rate / ((pclk_div + 1) * 4)); +} + +static uint32_t ast2600_get_pclk2_rate(struct ast2600_scu *scu) +{ + uint32_t rate = ast2600_get_hclk_rate(scu); + uint32_t clksrc4 = readl(&scu->clksrc4); + uint32_t pclk_div = (clksrc4 & SCU_CLKSRC4_PCLK_DIV_MASK) >> + SCU_CLKSRC4_PCLK_DIV_SHIFT; + + return (rate / ((pclk_div + 1) * 2)); +} + +static uint32_t ast2600_get_uxclk_in_rate(struct ast2600_scu *scu) +{ + uint32_t rate = 0; + uint32_t clksrc5 = readl(&scu->clksrc5); + uint32_t uxclk = (clksrc5 & SCU_CLKSRC5_UXCLK_MASK) >> + SCU_CLKSRC5_UXCLK_SHIFT; + + switch (uxclk) { + case 0: + rate = ast2600_get_pll_rate(scu, ASPEED_CLK_APLL) / 4; + break; + case 1: + rate = ast2600_get_pll_rate(scu, ASPEED_CLK_APLL) / 2; + break; + case 2: + rate = ast2600_get_pll_rate(scu, ASPEED_CLK_APLL); + break; + case 3: + rate = ast2600_get_hclk_rate(scu); + break; + } + + return rate; +} + +static uint32_t ast2600_get_huxclk_in_rate(struct ast2600_scu *scu) +{ + uint32_t rate = 0; + uint32_t clksrc5 = readl(&scu->clksrc5); + uint32_t huxclk = (clksrc5 & SCU_CLKSRC5_HUXCLK_MASK) >> + SCU_CLKSRC5_HUXCLK_SHIFT; + + switch (huxclk) { + case 0: + rate = ast2600_get_pll_rate(scu, ASPEED_CLK_APLL) / 4; + break; + case 1: + rate = ast2600_get_pll_rate(scu, ASPEED_CLK_APLL) / 2; + break; + case 2: + rate = ast2600_get_pll_rate(scu, ASPEED_CLK_APLL); + break; + case 3: + rate = ast2600_get_hclk_rate(scu); + break; + } + + return rate; +} + +static uint32_t ast2600_get_uart_uxclk_rate(struct ast2600_scu *scu) +{ + uint32_t rate = ast2600_get_uxclk_in_rate(scu); + uint32_t uart_clkgen = readl(&scu->uart_clkgen); + uint32_t n = (uart_clkgen & SCU_UART_CLKGEN_N_MASK) >> + SCU_UART_CLKGEN_N_SHIFT; + uint32_t r = (uart_clkgen & SCU_UART_CLKGEN_R_MASK) >> + SCU_UART_CLKGEN_R_SHIFT; + + return ((rate * r) / (n * 2)); +} + +static uint32_t ast2600_get_uart_huxclk_rate(struct ast2600_scu *scu) +{ + uint32_t rate = ast2600_get_huxclk_in_rate(scu); + uint32_t huart_clkgen = readl(&scu->huart_clkgen); + uint32_t n = (huart_clkgen & SCU_HUART_CLKGEN_N_MASK) >> + SCU_HUART_CLKGEN_N_SHIFT; + uint32_t r = (huart_clkgen & SCU_HUART_CLKGEN_R_MASK) >> + SCU_HUART_CLKGEN_R_SHIFT; + + return ((rate * r) / (n * 2)); +} + +static uint32_t ast2600_get_sdio_clk_rate(struct ast2600_scu *scu) +{ + uint32_t rate = 0; + uint32_t clksrc4 = readl(&scu->clksrc4); + uint32_t sdio_div = (clksrc4 & SCU_CLKSRC4_SDIO_DIV_MASK) >> + SCU_CLKSRC4_SDIO_DIV_SHIFT; + + if (clksrc4 & SCU_CLKSRC4_SDIO) + rate = ast2600_get_pll_rate(scu, ASPEED_CLK_APLL); + else + rate = ast2600_get_hclk_rate(scu); + + return (rate / ((sdio_div + 1) * 2)); +} + +static uint32_t ast2600_get_emmc_clk_rate(struct ast2600_scu *scu) +{ + uint32_t rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); + uint32_t clksrc1 = readl(&scu->clksrc1); + uint32_t emmc_div = (clksrc1 & SCU_CLKSRC1_EMMC_DIV_MASK) >> + SCU_CLKSRC1_EMMC_DIV_SHIFT; + + return (rate / ((emmc_div + 1) * 4)); +} + +static uint32_t ast2600_get_uart_clk_rate(struct ast2600_scu *scu, int uart_idx) +{ + uint32_t rate = 0; + uint32_t uart5_clk = 0; + uint32_t clksrc2 = readl(&scu->clksrc2); + uint32_t clksrc4 = readl(&scu->clksrc4); + uint32_t clksrc5 = readl(&scu->clksrc5); + uint32_t misc_ctrl1 = readl(&scu->misc_ctrl1); + + switch (uart_idx) { + case 1: + case 2: + case 3: + case 4: + case 6: + if (clksrc4 & BIT(uart_idx - 1)) + rate = ast2600_get_uart_huxclk_rate(scu); + else + rate = ast2600_get_uart_uxclk_rate(scu); + break; + case 5: + /* + * SCU0C[12] and SCU304[14] together decide + * the UART5 clock generation + */ + if (misc_ctrl1 & SCU_MISC_CTRL1_UART5_DIV) + uart5_clk = 0x1 << 1; + + if (clksrc2 & SCU_CLKSRC2_UART5) + uart5_clk |= 0x1; + + switch (uart5_clk) { + case 0: + rate = 24000000; + break; + case 1: + rate = 192000000; + break; + case 2: + rate = 24000000 / 13; + break; + case 3: + rate = 192000000 / 13; + break; + } + + break; + case 7: + case 8: + case 9: + case 10: + case 11: + case 12: + case 13: + if (clksrc5 & BIT(uart_idx - 1)) + rate = ast2600_get_uart_huxclk_rate(scu); + else + rate = ast2600_get_uart_uxclk_rate(scu); + break; + } + + return rate; +} + +static ulong ast2600_clk_get_rate(struct clk *clk) +{ + struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); + ulong rate = 0; + + switch (clk->id) { + case ASPEED_CLK_HPLL: + case ASPEED_CLK_EPLL: + case ASPEED_CLK_DPLL: + case ASPEED_CLK_MPLL: + case ASPEED_CLK_APLL: + rate = ast2600_get_pll_rate(priv->scu, clk->id); + break; + case ASPEED_CLK_AHB: + rate = ast2600_get_hclk_rate(priv->scu); + break; + case ASPEED_CLK_APB1: + rate = ast2600_get_pclk1_rate(priv->scu); + break; + case ASPEED_CLK_APB2: + rate = ast2600_get_pclk2_rate(priv->scu); + break; + case ASPEED_CLK_GATE_UART1CLK: + rate = ast2600_get_uart_clk_rate(priv->scu, 1); + break; + case ASPEED_CLK_GATE_UART2CLK: + rate = ast2600_get_uart_clk_rate(priv->scu, 2); + break; + case ASPEED_CLK_GATE_UART3CLK: + rate = ast2600_get_uart_clk_rate(priv->scu, 3); + break; + case ASPEED_CLK_GATE_UART4CLK: + rate = ast2600_get_uart_clk_rate(priv->scu, 4); + break; + case ASPEED_CLK_GATE_UART5CLK: + rate = ast2600_get_uart_clk_rate(priv->scu, 5); + break; + case ASPEED_CLK_BCLK: + rate = ast2600_get_bclk_rate(priv->scu); + break; + case ASPEED_CLK_SDIO: + rate = ast2600_get_sdio_clk_rate(priv->scu); + break; + case ASPEED_CLK_EMMC: + rate = ast2600_get_emmc_clk_rate(priv->scu); + break; + case ASPEED_CLK_UARTX: + rate = ast2600_get_uart_uxclk_rate(priv->scu); + break; + case ASPEED_CLK_HUARTX: + rate = ast2600_get_uart_huxclk_rate(priv->scu); + break; + default: + debug("can't get clk rate\n"); + return -ENOENT; + } + + return rate; +} + +/** + * @brief lookup PLL divider config by input/output rate + * @param[in] *pll - PLL descriptor + * @return true - if PLL divider config is found, false - else + * The function caller shall fill "pll->in" and "pll->out", + * then this function will search the lookup table + * to find a valid PLL divider configuration. + */ +static bool ast2600_search_clock_config(struct ast2600_pll_desc *pll) +{ + uint32_t i; + const struct ast2600_pll_desc *def_desc; + bool is_found = false; + + for (i = 0; i < ARRAY_SIZE(ast2600_pll_lookup); i++) { + def_desc = &ast2600_pll_lookup[i]; + + if (def_desc->in == pll->in && def_desc->out == pll->out) { + is_found = true; + pll->cfg.reg.w = def_desc->cfg.reg.w; + pll->cfg.ext_reg = def_desc->cfg.ext_reg; + break; + } + } + return is_found; +} + +static uint32_t ast2600_configure_pll(struct ast2600_scu *scu, + struct ast2600_pll_cfg *p_cfg, int pll_idx) +{ + uint32_t addr, addr_ext; + uint32_t reg; + + switch (pll_idx) { + case ASPEED_CLK_HPLL: + addr = (uint32_t)(&scu->hpll); + addr_ext = (uint32_t)(&scu->hpll_ext); + break; + case ASPEED_CLK_MPLL: + addr = (uint32_t)(&scu->mpll); + addr_ext = (uint32_t)(&scu->mpll_ext); + break; + case ASPEED_CLK_DPLL: + addr = (uint32_t)(&scu->dpll); + addr_ext = (uint32_t)(&scu->dpll_ext); + break; + case ASPEED_CLK_EPLL: + addr = (uint32_t)(&scu->epll); + addr_ext = (uint32_t)(&scu->epll_ext); + break; + case ASPEED_CLK_APLL: + addr = (uint32_t)(&scu->apll); + addr_ext = (uint32_t)(&scu->apll_ext); + break; + default: + debug("unknown PLL index\n"); + return 1; + } + + p_cfg->reg.b.bypass = 0; + p_cfg->reg.b.off = 1; + p_cfg->reg.b.reset = 1; + + reg = readl(addr); + reg &= ~GENMASK(25, 0); + reg |= p_cfg->reg.w; + writel(reg, addr); + + /* write extend parameter */ + writel(p_cfg->ext_reg, addr_ext); + udelay(100); + p_cfg->reg.b.off = 0; + p_cfg->reg.b.reset = 0; + reg &= ~GENMASK(25, 0); + reg |= p_cfg->reg.w; + writel(reg, addr); + while (!(readl(addr_ext) & BIT(31))) + ; + + return 0; +} + +static uint32_t ast2600_configure_ddr(struct ast2600_scu *scu, ulong rate) +{ + struct ast2600_pll_desc mpll; + + mpll.in = CLKIN_25M; + mpll.out = rate; + if (ast2600_search_clock_config(&mpll) == false) { + printf("error!! unable to find valid DDR clock setting\n"); + return 0; + } + ast2600_configure_pll(scu, &mpll.cfg, ASPEED_CLK_MPLL); + + return ast2600_get_pll_rate(scu, ASPEED_CLK_MPLL); +} + +static ulong ast2600_clk_set_rate(struct clk *clk, ulong rate) +{ + struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); + ulong new_rate; + + switch (clk->id) { + case ASPEED_CLK_MPLL: + new_rate = ast2600_configure_ddr(priv->scu, rate); + break; + default: + return -ENOENT; + } + + return new_rate; +} + +static uint32_t ast2600_configure_mac12_clk(struct ast2600_scu *scu) +{ + /* scu340[25:0]: 1G default delay */ + clrsetbits_le32(&scu->mac12_clk_delay, GENMASK(25, 0), + MAC12_DEF_DELAY_1G); + + /* set 100M/10M default delay */ + writel(MAC12_DEF_DELAY_100M, &scu->mac12_clk_delay_100M); + writel(MAC12_DEF_DELAY_10M, &scu->mac12_clk_delay_10M); + + /* MAC AHB = HPLL / 6 */ + clrsetbits_le32(&scu->clksrc1, SCU_CLKSRC1_MAC_DIV_MASK, + (0x2 << SCU_CLKSRC1_MAC_DIV_SHIFT)); + + return 0; +} + +static uint32_t ast2600_configure_mac34_clk(struct ast2600_scu *scu) +{ + /* + * scu350[31] RGMII 125M source: 0 = from IO pin + * scu350[25:0] MAC 1G delay + */ + clrsetbits_le32(&scu->mac34_clk_delay, (BIT(31) | GENMASK(25, 0)), + MAC34_DEF_DELAY_1G); + writel(MAC34_DEF_DELAY_100M, &scu->mac34_clk_delay_100M); + writel(MAC34_DEF_DELAY_10M, &scu->mac34_clk_delay_10M); + + /* + * clock source seletion and divider + * scu310[26:24] : MAC AHB bus clock = HCLK / 2 + * scu310[18:16] : RMII 50M = HCLK_200M / 4 + */ + clrsetbits_le32(&scu->clksrc4, + (SCU_CLKSRC4_MAC_DIV_MASK | SCU_CLKSRC4_RMII34_DIV_MASK), + ((0x0 << SCU_CLKSRC4_MAC_DIV_SHIFT) + | (0x3 << SCU_CLKSRC4_RMII34_DIV_SHIFT))); + + /* + * set driving strength + * scu458[3:2] : MAC4 driving strength + * scu458[1:0] : MAC3 driving strength + */ + clrsetbits_le32(&scu->pinmux16, + SCU_PINCTRL16_MAC4_DRIVING_MASK | SCU_PINCTRL16_MAC3_DRIVING_MASK, + (0x3 << SCU_PINCTRL16_MAC4_DRIVING_SHIFT) + | (0x3 << SCU_PINCTRL16_MAC3_DRIVING_SHIFT)); + + return 0; +} + +/** + * ast2600 RGMII clock source tree + * 125M from external PAD -------->|\ + * HPLL -->|\ | |---->RGMII 125M for MAC#1 & MAC#2 + * | |---->| divider |---->|/ + + * EPLL -->|/ | + * | + * +---------<-----------|RGMIICK PAD output enable|<-------------+ + * | + * +--------------------------->|\ + * | |----> RGMII 125M for MAC#3 & MAC#4 + * HCLK 200M ---->|divider|---->|/ + * To simplify the control flow: + * 1. RGMII 1/2 always use EPLL as the internal clock source + * 2. RGMII 3/4 always use RGMIICK pad as the RGMII 125M source + * 125M from external PAD -------->|\ + * | |---->RGMII 125M for MAC#1 & MAC#2 + * EPLL---->| divider |--->|/ + + * | + * +<--------------------|RGMIICK PAD output enable|<-------------+ + * | + * +--------------------------->RGMII 125M for MAC#3 & MAC#4 + */ +#define RGMIICK_SRC_PAD 0 +#define RGMIICK_SRC_EPLL 1 /* recommended */ +#define RGMIICK_SRC_HPLL 2 + +#define RGMIICK_DIV2 1 +#define RGMIICK_DIV3 2 +#define RGMIICK_DIV4 3 +#define RGMIICK_DIV5 4 +#define RGMIICK_DIV6 5 +#define RGMIICK_DIV7 6 +#define RGMIICK_DIV8 7 /* recommended */ + +#define RMIICK_DIV4 0 +#define RMIICK_DIV8 1 +#define RMIICK_DIV12 2 +#define RMIICK_DIV16 3 +#define RMIICK_DIV20 4 /* recommended */ +#define RMIICK_DIV24 5 +#define RMIICK_DIV28 6 +#define RMIICK_DIV32 7 + +struct ast2600_mac_clk_div { + uint32_t src; /* 0=external PAD, 1=internal PLL */ + uint32_t fin; /* divider input speed */ + uint32_t n; /* 0=div2, 1=div2, 2=div3, 3=div4,...,7=div8 */ + uint32_t fout; /* fout = fin / n */ +}; + +struct ast2600_mac_clk_div rgmii_clk_defconfig = { + .src = ASPEED_CLK_EPLL, + .fin = 1000000000, + .n = RGMIICK_DIV8, + .fout = 125000000, +}; + +struct ast2600_mac_clk_div rmii_clk_defconfig = { + .src = ASPEED_CLK_EPLL, + .fin = 1000000000, + .n = RMIICK_DIV20, + .fout = 50000000, +}; + +static void ast2600_init_mac_pll(struct ast2600_scu *p_scu, + struct ast2600_mac_clk_div *p_cfg) +{ + struct ast2600_pll_desc pll; + + pll.in = CLKIN_25M; + pll.out = p_cfg->fin; + if (ast2600_search_clock_config(&pll) == false) { + pr_err("unable to find valid ETHNET MAC clock setting\n"); + return; + } + ast2600_configure_pll(p_scu, &pll.cfg, p_cfg->src); +} + +static void ast2600_init_rgmii_clk(struct ast2600_scu *p_scu, + struct ast2600_mac_clk_div *p_cfg) +{ + uint32_t reg_304 = readl(&p_scu->clksrc2); + uint32_t reg_340 = readl(&p_scu->mac12_clk_delay); + uint32_t reg_350 = readl(&p_scu->mac34_clk_delay); + + reg_340 &= ~GENMASK(31, 29); + /* scu340[28]: RGMIICK PAD output enable (to MAC 3/4) */ + reg_340 |= BIT(28); + if (p_cfg->src == ASPEED_CLK_EPLL || p_cfg->src == ASPEED_CLK_HPLL) { + /* + * re-init PLL if the current PLL output frequency doesn't match + * the divider setting + */ + if (p_cfg->fin != ast2600_get_pll_rate(p_scu, p_cfg->src)) + ast2600_init_mac_pll(p_scu, p_cfg); + /* scu340[31]: select RGMII 125M from internal source */ + reg_340 |= BIT(31); + } + + reg_304 &= ~GENMASK(23, 20); + + /* set clock divider */ + reg_304 |= (p_cfg->n & 0x7) << 20; + + /* select internal clock source */ + if (p_cfg->src == ASPEED_CLK_HPLL) + reg_304 |= BIT(23); + + /* RGMII 3/4 clock source select */ + reg_350 &= ~BIT(31); + + writel(reg_304, &p_scu->clksrc2); + writel(reg_340, &p_scu->mac12_clk_delay); + writel(reg_350, &p_scu->mac34_clk_delay); +} + +/** + * ast2600 RMII/NCSI clock source tree + * HPLL -->|\ + * | |---->| divider |----> RMII 50M for MAC#1 & MAC#2 + * EPLL -->|/ + * HCLK(SCLICLK)---->| divider |----> RMII 50M for MAC#3 & MAC#4 + */ +static void ast2600_init_rmii_clk(struct ast2600_scu *p_scu, + struct ast2600_mac_clk_div *p_cfg) +{ + uint32_t clksrc2 = readl(&p_scu->clksrc2); + uint32_t clksrc4 = readl(&p_scu->clksrc4); + + if (p_cfg->src == ASPEED_CLK_EPLL || p_cfg->src == ASPEED_CLK_HPLL) { + /* + * re-init PLL if the current PLL output frequency doesn't match + * the divider setting + */ + if (p_cfg->fin != ast2600_get_pll_rate(p_scu, p_cfg->src)) + ast2600_init_mac_pll(p_scu, p_cfg); + } + + clksrc2 &= ~(SCU_CLKSRC2_RMII12 | SCU_CLKSRC2_RMII12_DIV_MASK); + + /* set RMII 1/2 clock divider */ + clksrc2 |= (p_cfg->n & 0x7) << 16; + + /* RMII clock source selection */ + if (p_cfg->src == ASPEED_CLK_HPLL) + clksrc2 |= SCU_CLKSRC2_RMII12; + + /* set RMII 3/4 clock divider */ + clksrc4 &= ~SCU_CLKSRC4_RMII34_DIV_MASK; + clksrc4 |= (0x3 << SCU_CLKSRC4_RMII34_DIV_SHIFT); + + writel(clksrc2, &p_scu->clksrc2); + writel(clksrc4, &p_scu->clksrc4); +} + +static uint32_t ast2600_configure_mac(struct ast2600_scu *scu, int index) +{ + uint32_t reset_bit; + uint32_t clkgate_bit; + + switch (index) { + case 1: + reset_bit = BIT(ASPEED_RESET_MAC1); + clkgate_bit = SCU_CLKGATE1_MAC1; + writel(reset_bit, &scu->modrst_ctrl1); + udelay(100); + writel(clkgate_bit, &scu->clkgate_clr1); + mdelay(10); + writel(reset_bit, &scu->modrst_clr1); + break; + case 2: + reset_bit = BIT(ASPEED_RESET_MAC2); + clkgate_bit = SCU_CLKGATE1_MAC2; + writel(reset_bit, &scu->modrst_ctrl1); + udelay(100); + writel(clkgate_bit, &scu->clkgate_clr1); + mdelay(10); + writel(reset_bit, &scu->modrst_clr1); + break; + case 3: + reset_bit = BIT(ASPEED_RESET_MAC3 - 32); + clkgate_bit = SCU_CLKGATE2_MAC3; + writel(reset_bit, &scu->modrst_ctrl2); + udelay(100); + writel(clkgate_bit, &scu->clkgate_clr2); + mdelay(10); + writel(reset_bit, &scu->modrst_clr2); + break; + case 4: + reset_bit = BIT(ASPEED_RESET_MAC4 - 32); + clkgate_bit = SCU_CLKGATE2_MAC4; + writel(reset_bit, &scu->modrst_ctrl2); + udelay(100); + writel(clkgate_bit, &scu->clkgate_clr2); + mdelay(10); + writel(reset_bit, &scu->modrst_clr2); + break; + default: + return -EINVAL; + } + + return 0; +} + +static void ast2600_configure_rsa_ecc_clk(struct ast2600_scu *scu) +{ + uint32_t clksrc1 = readl(&scu->clksrc1); + + /* Configure RSA clock = HPLL/3 */ + clksrc1 |= SCU_CLKSRC1_ECC_RSA; + clksrc1 &= ~SCU_CLKSRC1_ECC_RSA_DIV_MASK; + clksrc1 |= (2 << SCU_CLKSRC1_ECC_RSA_DIV_SHIFT); + + writel(clksrc1, &scu->clksrc1); +} + +static ulong ast2600_enable_sdclk(struct ast2600_scu *scu) +{ + uint32_t reset_bit; + uint32_t clkgate_bit; + + reset_bit = BIT(ASPEED_RESET_SD - 32); + clkgate_bit = SCU_CLKGATE2_SDIO; + + writel(reset_bit, &scu->modrst_ctrl2); + udelay(100); + writel(clkgate_bit, &scu->clkgate_clr2); + mdelay(10); + writel(reset_bit, &scu->modrst_clr2); + + return 0; +} + +static ulong ast2600_enable_extsdclk(struct ast2600_scu *scu) +{ + int i = 0; + uint32_t div = 0; + uint32_t rate = 0; + uint32_t clksrc4 = readl(&scu->clksrc4); + + /* + * ast2600 SD controller max clk is 200Mhz + * use apll for clock source 800/4 = 200 + * controller max is 200mhz + */ + rate = ast2600_get_pll_rate(scu, ASPEED_CLK_APLL); + for (i = 0; i < 8; i++) { + div = (i + 1) * 2; + if ((rate / div) <= 200000000) + break; + } + clksrc4 &= ~SCU_CLKSRC4_SDIO_DIV_MASK; + clksrc4 |= (i << SCU_CLKSRC4_SDIO_DIV_SHIFT); + clksrc4 |= SCU_CLKSRC4_SDIO; + writel(clksrc4, &scu->clksrc4); + + setbits_le32(&scu->clksrc4, SCU_CLKSRC4_SDIO_EN); + + return 0; +} + +static ulong ast2600_enable_emmcclk(struct ast2600_scu *scu) +{ + uint32_t reset_bit; + uint32_t clkgate_bit; + + reset_bit = BIT(ASPEED_RESET_EMMC); + clkgate_bit = SCU_CLKGATE1_EMMC; + + writel(reset_bit, &scu->modrst_ctrl1); + udelay(100); + writel(clkgate_bit, &scu->clkgate_clr1); + mdelay(10); + writel(reset_bit, &scu->modrst_clr1); + + return 0; +} + +static ulong ast2600_enable_extemmcclk(struct ast2600_scu *scu) +{ + int i = 0; + uint32_t div = 0; + uint32_t rate = 0; + uint32_t clksrc1 = readl(&scu->clksrc1); + + /* + * ast2600 eMMC controller max clk is 200Mhz + * HPll->1/2->|\ + * |->SCU300[11]->SCU300[14:12][1/N] + + * MPLL------>|/ | + * +----------------------------------------------+ + * | + * +---------> EMMC12C[15:8][1/N]-> eMMC clk + */ + rate = ast2600_get_pll_rate(scu, ASPEED_CLK_MPLL); + for (i = 0; i < 8; i++) { + div = (i + 1) * 2; + if ((rate / div) <= 200000000) + break; + } + + clksrc1 &= ~SCU_CLKSRC1_EMMC_DIV_MASK; + clksrc1 |= (i << SCU_CLKSRC1_EMMC_DIV_SHIFT); + clksrc1 |= SCU_CLKSRC1_EMMC; + writel(clksrc1, &scu->clksrc1); + + setbits_le32(&scu->clksrc1, SCU_CLKSRC1_EMMC_EN); + + return 0; +} + +static ulong ast2600_enable_fsiclk(struct ast2600_scu *scu) +{ + uint32_t reset_bit; + uint32_t clkgate_bit; + + reset_bit = BIT(ASPEED_RESET_FSI % 32); + clkgate_bit = SCU_CLKGATE2_FSI; + + /* The FSI clock is shared between masters. If it's already on + * don't touch it, as that will reset the existing master. + */ + if (!(readl(&scu->clkgate_ctrl2) & clkgate_bit)) { + debug("%s: already running, not touching it\n", __func__); + return 0; + } + + writel(reset_bit, &scu->modrst_ctrl2); + udelay(100); + writel(clkgate_bit, &scu->clkgate_clr2); + mdelay(10); + writel(reset_bit, &scu->modrst_clr2); + + return 0; +} + +static ulong ast2600_enable_usbahclk(struct ast2600_scu *scu) +{ + uint32_t reset_bit; + uint32_t clkgate_bit; + + reset_bit = BIT(ASPEED_RESET_EHCI_P1); + clkgate_bit = SCU_CLKGATE1_USB_HUB; + + writel(reset_bit, &scu->modrst_ctrl1); + udelay(100); + writel(clkgate_bit, &scu->clkgate_ctrl1); + mdelay(20); + writel(reset_bit, &scu->modrst_clr1); + + return 0; +} + +static ulong ast2600_enable_usbbhclk(struct ast2600_scu *scu) +{ + uint32_t reset_bit; + uint32_t clkgate_bit; + + reset_bit = BIT(ASPEED_RESET_EHCI_P2); + clkgate_bit = SCU_CLKGATE1_USB_HOST2; + + writel(reset_bit, &scu->modrst_ctrl1); + udelay(100); + writel(clkgate_bit, &scu->clkgate_clr1); + mdelay(20); + writel(reset_bit, &scu->modrst_clr1); + + return 0; +} + +static int ast2600_clk_enable(struct clk *clk) +{ + struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); + + switch (clk->id) { + case ASPEED_CLK_GATE_MAC1CLK: + ast2600_configure_mac(priv->scu, 1); + break; + case ASPEED_CLK_GATE_MAC2CLK: + ast2600_configure_mac(priv->scu, 2); + break; + case ASPEED_CLK_GATE_MAC3CLK: + ast2600_configure_mac(priv->scu, 3); + break; + case ASPEED_CLK_GATE_MAC4CLK: + ast2600_configure_mac(priv->scu, 4); + break; + case ASPEED_CLK_GATE_SDCLK: + ast2600_enable_sdclk(priv->scu); + break; + case ASPEED_CLK_GATE_SDEXTCLK: + ast2600_enable_extsdclk(priv->scu); + break; + case ASPEED_CLK_GATE_EMMCCLK: + ast2600_enable_emmcclk(priv->scu); + break; + case ASPEED_CLK_GATE_EMMCEXTCLK: + ast2600_enable_extemmcclk(priv->scu); + break; + case ASPEED_CLK_GATE_FSICLK: + ast2600_enable_fsiclk(priv->scu); + break; + case ASPEED_CLK_GATE_USBPORT1CLK: + ast2600_enable_usbahclk(priv->scu); + break; + case ASPEED_CLK_GATE_USBPORT2CLK: + ast2600_enable_usbbhclk(priv->scu); + break; + default: + pr_err("can't enable clk\n"); + return -ENOENT; + } + + return 0; +} + +struct clk_ops ast2600_clk_ops = { + .get_rate = ast2600_clk_get_rate, + .set_rate = ast2600_clk_set_rate, + .enable = ast2600_clk_enable, +}; + +static int ast2600_clk_probe(struct udevice *dev) +{ + struct ast2600_clk_priv *priv = dev_get_priv(dev); + + priv->scu = devfdt_get_addr_ptr(dev); + if (IS_ERR(priv->scu)) + return PTR_ERR(priv->scu); + + ast2600_init_rgmii_clk(priv->scu, &rgmii_clk_defconfig); + ast2600_init_rmii_clk(priv->scu, &rmii_clk_defconfig); + ast2600_configure_mac12_clk(priv->scu); + ast2600_configure_mac34_clk(priv->scu); + ast2600_configure_rsa_ecc_clk(priv->scu); + + return 0; +} + +static int ast2600_clk_bind(struct udevice *dev) +{ + int ret; + + /* The reset driver does not have a device node, so bind it here */ + ret = device_bind_driver(gd->dm_root, "ast_sysreset", "reset", &dev); + if (ret) + debug("Warning: No reset driver: ret=%d\n", ret); + + return 0; +} + +struct aspeed_clks { + ulong id; + const char *name; +}; + +static struct aspeed_clks aspeed_clk_names[] = { + { ASPEED_CLK_HPLL, "hpll" }, + { ASPEED_CLK_MPLL, "mpll" }, + { ASPEED_CLK_APLL, "apll" }, + { ASPEED_CLK_EPLL, "epll" }, + { ASPEED_CLK_DPLL, "dpll" }, + { ASPEED_CLK_AHB, "hclk" }, + { ASPEED_CLK_APB1, "pclk1" }, + { ASPEED_CLK_APB2, "pclk2" }, + { ASPEED_CLK_BCLK, "bclk" }, + { ASPEED_CLK_UARTX, "uxclk" }, + { ASPEED_CLK_HUARTX, "huxclk" }, +}; + +int soc_clk_dump(void) +{ + struct udevice *dev; + struct clk clk; + unsigned long rate; + int i, ret; + + ret = uclass_get_device_by_driver(UCLASS_CLK, DM_DRIVER_GET(aspeed_scu), + &dev); + if (ret) + return ret; + + printf("Clk\t\tHz\n"); + + for (i = 0; i < ARRAY_SIZE(aspeed_clk_names); i++) { + clk.id = aspeed_clk_names[i].id; + ret = clk_request(dev, &clk); + if (ret < 0) { + debug("%s clk_request() failed: %d\n", __func__, ret); + continue; + } + + ret = clk_get_rate(&clk); + rate = ret; + + clk_free(&clk); + + if (ret == -ENOTSUPP) { + printf("clk ID %lu not supported yet\n", + aspeed_clk_names[i].id); + continue; + } + if (ret < 0) { + printf("%s %lu: get_rate err: %d\n", __func__, + aspeed_clk_names[i].id, ret); + continue; + } + + printf("%s(%3lu):\t%lu\n", aspeed_clk_names[i].name, + aspeed_clk_names[i].id, rate); + } + + return 0; +} + +static const struct udevice_id ast2600_clk_ids[] = { + { .compatible = "aspeed,ast2600-scu", }, + { }, +}; + +U_BOOT_DRIVER(aspeed_ast2600_scu) = { + .name = "aspeed_ast2600_scu", + .id = UCLASS_CLK, + .of_match = ast2600_clk_ids, + .priv_auto = sizeof(struct ast2600_clk_priv), + .ops = &ast2600_clk_ops, + .bind = ast2600_clk_bind, + .probe = ast2600_clk_probe, +}; diff --git a/drivers/clk/clk_stm32f.c b/drivers/clk/clk_stm32f.c index 7e67895ab79..e7c26db51c9 100644 --- a/drivers/clk/clk_stm32f.c +++ b/drivers/clk/clk_stm32f.c @@ -4,18 +4,19 @@ * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics. */ +#define LOG_CATEGORY UCLASS_CLK + #include <common.h> #include <clk-uclass.h> #include <dm.h> #include <log.h> #include <stm32_rcc.h> -#include <linux/bitops.h> - #include <asm/io.h> #include <asm/arch/stm32.h> #include <asm/arch/stm32_pwr.h> - +#include <dm/device_compat.h> #include <dt-bindings/mfd/stm32f7-rcc.h> +#include <linux/bitops.h> #define RCC_CR_HSION BIT(0) #define RCC_CR_HSEON BIT(16) @@ -309,7 +310,7 @@ static unsigned long stm32_clk_get_pllsai_rate(struct stm32_clk *priv, >> RCC_PLLSAICFGR_PLLSAIR_SHIFT; break; default: - pr_err("incorrect PLLSAI output %d\n", output); + log_err("incorrect PLLSAI output %d\n", output); return -EINVAL; } @@ -490,7 +491,7 @@ static ulong stm32_clk_get_rate(struct clk *clk) return (sysclk >> stm32_get_apb_shift(regs, APB2)); default: - pr_err("clock index %ld out of range\n", clk->id); + dev_err(clk->dev, "clock index %ld out of range\n", clk->id); return -EINVAL; } } @@ -509,8 +510,9 @@ static ulong stm32_set_rate(struct clk *clk, ulong rate) /* Only set_rate for LTDC clock is implemented */ if (clk->id != STM32F7_APB2_CLOCK(LTDC)) { - pr_err("set_rate not implemented for clock index %ld\n", - clk->id); + dev_err(clk->dev, + "set_rate not implemented for clock index %ld\n", + clk->id); return 0; } @@ -604,8 +606,8 @@ static int stm32_clk_enable(struct clk *clk) u32 offset = clk->id / 32; u32 bit_index = clk->id % 32; - debug("%s: clkid = %ld, offset from AHB1ENR is %d, bit_index = %d\n", - __func__, clk->id, offset, bit_index); + dev_dbg(clk->dev, "clkid = %ld, offset from AHB1ENR is %d, bit_index = %d\n", + clk->id, offset, bit_index); setbits_le32(®s->ahb1enr + offset, BIT(bit_index)); return 0; @@ -618,7 +620,7 @@ static int stm32_clk_probe(struct udevice *dev) struct clk clk; int err; - debug("%s\n", __func__); + dev_dbg(dev, "%s\n", __func__); struct stm32_clk *priv = dev_get_priv(dev); fdt_addr_t addr; @@ -652,14 +654,14 @@ static int stm32_clk_probe(struct udevice *dev) &fixed_clock_dev); if (err) { - pr_err("Can't find fixed clock (%d)", err); + dev_err(dev, "Can't find fixed clock (%d)", err); return err; } err = clk_request(fixed_clock_dev, &clk); if (err) { - pr_err("Can't request %s clk (%d)", fixed_clock_dev->name, - err); + dev_err(dev, "Can't request %s clk (%d)", + fixed_clock_dev->name, err); return err; } @@ -673,8 +675,8 @@ static int stm32_clk_probe(struct udevice *dev) priv->hse_rate = clk_get_rate(&clk); if (priv->hse_rate < 1000000) { - pr_err("%s: unexpected HSE clock rate = %ld \"n", __func__, - priv->hse_rate); + dev_err(dev, "unexpected HSE clock rate = %ld \"n", + priv->hse_rate); return -EINVAL; } @@ -684,8 +686,7 @@ static int stm32_clk_probe(struct udevice *dev) err = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0, &args); if (err) { - debug("%s: can't find syscon device (%d)\n", __func__, - err); + dev_err(dev, "can't find syscon device (%d)\n", err); return err; } @@ -699,10 +700,10 @@ static int stm32_clk_probe(struct udevice *dev) static int stm32_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args) { - debug("%s(clk=%p)\n", __func__, clk); + dev_dbg(clk->dev, "clk=%p\n", clk); if (args->args_count != 2) { - debug("Invaild args_count: %d\n", args->args_count); + dev_dbg(clk->dev, "Invaild args_count: %d\n", args->args_count); return -EINVAL; } diff --git a/drivers/clk/clk_stm32h7.c b/drivers/clk/clk_stm32h7.c index 0171fe8c110..20b36470994 100644 --- a/drivers/clk/clk_stm32h7.c +++ b/drivers/clk/clk_stm32h7.c @@ -4,6 +4,8 @@ * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics. */ +#define LOG_CATEGORY UCLASS_CLK + #include <common.h> #include <clk-uclass.h> #include <dm.h> @@ -11,6 +13,7 @@ #include <regmap.h> #include <syscon.h> #include <asm/io.h> +#include <dm/device_compat.h> #include <dm/root.h> #include <linux/bitops.h> @@ -465,18 +468,18 @@ static ulong stm32_get_rate(struct stm32_rcc_regs *regs, enum pllsrc pllsrc) int ret; const char *name = pllsrc_name[pllsrc]; - debug("%s name %s\n", __func__, name); + log_debug("pllsrc name %s\n", name); clk.id = 0; ret = uclass_get_device_by_name(UCLASS_CLK, name, &fixed_clock_dev); if (ret) { - pr_err("Can't find clk %s (%d)", name, ret); + log_err("Can't find clk %s (%d)", name, ret); return 0; } ret = clk_request(fixed_clock_dev, &clk); if (ret) { - pr_err("Can't request %s clk (%d)", name, ret); + log_err("Can't request %s clk (%d)", name, ret); return 0; } @@ -484,8 +487,7 @@ static ulong stm32_get_rate(struct stm32_rcc_regs *regs, enum pllsrc pllsrc) if (pllsrc == HSI) divider = stm32_get_HSI_divider(regs); - debug("%s divider %d rate %ld\n", __func__, - divider, clk_get_rate(&clk)); + log_debug("divider %d rate %ld\n", divider, clk_get_rate(&clk)); return clk_get_rate(&clk) >> divider; }; @@ -516,7 +518,7 @@ static u32 stm32_get_PLL1_rate(struct stm32_rcc_regs *regs, break; case RCC_PLLCKSELR_PLLSRC_NO_CLK: /* shouldn't happen */ - pr_err("wrong value for RCC_PLLCKSELR register\n"); + log_err("wrong value for RCC_PLLCKSELR register\n"); pllsrc = 0; break; } @@ -546,10 +548,10 @@ static u32 stm32_get_PLL1_rate(struct stm32_rcc_regs *regs, vco = (pllsrc / divm1) * divn1; rate = (pllsrc * fracn1) / (divm1 * 8192); - debug("%s divm1 = %d divn1 = %d divp1 = %d divq1 = %d divr1 = %d\n", - __func__, divm1, divn1, divp1, divq1, divr1); - debug("%s fracn1 = %d vco = %ld rate = %ld\n", - __func__, fracn1, vco, rate); + log_debug("divm1 = %d divn1 = %d divp1 = %d divq1 = %d divr1 = %d\n", + divm1, divn1, divp1, divq1, divr1); + log_debug("fracn1 = %d vco = %ld rate = %ld\n", + fracn1, vco, rate); switch (output) { case PLL1_P_CK: @@ -610,7 +612,7 @@ u32 psc = stm32_get_apb_psc(regs, apb); case 16: return sysclk / 4; default: - pr_err("unexpected prescaler value (%d)\n", psc); + log_err("unexpected prescaler value (%d)\n", psc); return 0; } else @@ -623,7 +625,7 @@ u32 psc = stm32_get_apb_psc(regs, apb); case 16: return sysclk / psc; default: - pr_err("unexpected prescaler value (%d)\n", psc); + log_err("unexpected prescaler value (%d)\n", psc); return 0; } }; @@ -665,8 +667,8 @@ static ulong stm32_clk_get_rate(struct clk *clk) if (!sysclk) return sysclk; - debug("%s system clock: source = %d freq = %ld\n", - __func__, source, sysclk); + dev_dbg(clk->dev, "system clock: source = %d freq = %ld\n", + source, sysclk); d1cfgr = readl(®s->d1cfgr); @@ -685,8 +687,8 @@ static ulong stm32_clk_get_rate(struct clk *clk) gate_offset = clk_map[clk->id].gate_offset; - debug("%s clk->id=%ld gate_offset=0x%x sysclk=%ld\n", - __func__, clk->id, gate_offset, sysclk); + dev_dbg(clk->dev, "clk->id=%ld gate_offset=0x%x sysclk=%ld\n", + clk->id, gate_offset, sysclk); switch (gate_offset) { case RCC_AHB3ENR: @@ -704,8 +706,8 @@ static ulong stm32_clk_get_rate(struct clk *clk) sysclk = sysclk / prescaler_table[idx]; } - debug("%s system clock: freq after APB3 prescaler = %ld\n", - __func__, sysclk); + dev_dbg(clk->dev, "system clock: freq after APB3 prescaler = %ld\n", + sysclk); return sysclk; break; @@ -719,8 +721,9 @@ static ulong stm32_clk_get_rate(struct clk *clk) sysclk = sysclk / prescaler_table[idx]; } - debug("%s system clock: freq after APB4 prescaler = %ld\n", - __func__, sysclk); + dev_dbg(clk->dev, + "system clock: freq after APB4 prescaler = %ld\n", + sysclk); return sysclk; break; @@ -741,8 +744,9 @@ static ulong stm32_clk_get_rate(struct clk *clk) return stm32_get_timer_rate(priv, sysclk, APB1); } - debug("%s system clock: freq after APB1 prescaler = %ld\n", - __func__, sysclk); + dev_dbg(clk->dev, + "system clock: freq after APB1 prescaler = %ld\n", + sysclk); return (sysclk / stm32_get_apb_psc(regs, APB1)); break; @@ -758,15 +762,17 @@ static ulong stm32_clk_get_rate(struct clk *clk) return stm32_get_timer_rate(priv, sysclk, APB2); } - debug("%s system clock: freq after APB2 prescaler = %ld\n", - __func__, sysclk); + dev_dbg(clk->dev, + "system clock: freq after APB2 prescaler = %ld\n", + sysclk); return (sysclk / stm32_get_apb_psc(regs, APB2)); break; default: - pr_err("unexpected gate_offset value (0x%x)\n", gate_offset); + dev_err(clk->dev, "unexpected gate_offset value (0x%x)\n", + gate_offset); return -EINVAL; break; } @@ -783,9 +789,9 @@ static int stm32_clk_enable(struct clk *clk) gate_offset = clk_map[clk_id].gate_offset; gate_bit_index = clk_map[clk_id].gate_bit_idx; - debug("%s: clkid=%ld gate offset=0x%x bit_index=%d name=%s\n", - __func__, clk->id, gate_offset, gate_bit_index, - clk_map[clk_id].name); + dev_dbg(clk->dev, "clkid=%ld gate offset=0x%x bit_index=%d name=%s\n", + clk->id, gate_offset, gate_bit_index, + clk_map[clk_id].name); setbits_le32(®s->cr + (gate_offset / 4), BIT(gate_bit_index)); @@ -810,13 +816,13 @@ static int stm32_clk_probe(struct udevice *dev) "st,syscfg", &syscon); if (err) { - pr_err("unable to find syscon device\n"); + dev_err(dev, "unable to find syscon device\n"); return err; } priv->pwr_regmap = syscon_get_regmap(syscon); if (!priv->pwr_regmap) { - pr_err("unable to find regmap\n"); + dev_err(dev, "unable to find regmap\n"); return -ENODEV; } @@ -829,7 +835,7 @@ static int stm32_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args) { if (args->args_count != 1) { - debug("Invaild args_count: %d\n", args->args_count); + dev_dbg(clk->dev, "Invaild args_count: %d\n", args->args_count); return -EINVAL; } @@ -852,7 +858,7 @@ static int stm32_clk_of_xlate(struct clk *clk, clk->id = 0; } - debug("%s clk->id %ld\n", __func__, clk->id); + dev_dbg(clk->dev, "clk->id %ld\n", clk->id); return 0; } diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c index 5bea2b60b9b..d4f10485919 100644 --- a/drivers/clk/clk_stm32mp1.c +++ b/drivers/clk/clk_stm32mp1.c @@ -3,6 +3,8 @@ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved */ +#define LOG_CATEGORY UCLASS_CLK + #include <common.h> #include <clk-uclass.h> #include <div64.h> @@ -14,12 +16,13 @@ #include <syscon.h> #include <time.h> #include <vsprintf.h> -#include <linux/bitops.h> -#include <linux/io.h> -#include <linux/iopoll.h> #include <asm/arch/sys_proto.h> +#include <dm/device_compat.h> #include <dt-bindings/clock/stm32mp1-clks.h> #include <dt-bindings/clock/stm32mp1-clksrc.h> +#include <linux/bitops.h> +#include <linux/io.h> +#include <linux/iopoll.h> DECLARE_GLOBAL_DATA_PTR; @@ -781,7 +784,7 @@ static const struct stm32mp1_clk_data stm32mp1_data = { static ulong stm32mp1_clk_get_fixed(struct stm32mp1_clk_priv *priv, int idx) { if (idx >= NB_OSC) { - debug("%s: clk id %d not found\n", __func__, idx); + log_debug("clk id %d not found\n", idx); return 0; } @@ -799,7 +802,7 @@ static int stm32mp1_clk_get_id(struct stm32mp1_clk_priv *priv, unsigned long id) } if (i == nb_clks) { - printf("%s: clk id %d not found\n", __func__, (u32)id); + log_err("clk id %d not found\n", (u32)id); return -EINVAL; } @@ -812,8 +815,7 @@ static int stm32mp1_clk_get_sel(struct stm32mp1_clk_priv *priv, const struct stm32mp1_clk_gate *gate = priv->data->gate; if (gate[i].sel > _PARENT_SEL_NB) { - printf("%s: parents for clk id %d not found\n", - __func__, i); + log_err("parents for clk id %d not found\n", i); return -EINVAL; } @@ -858,17 +860,14 @@ static int stm32mp1_clk_get_parent(struct stm32mp1_clk_priv *priv, p = (readl(priv->base + sel[s].offset) >> sel[s].src) & sel[s].msk; if (p < sel[s].nb_parent) { -#ifdef DEBUG - debug("%s: %s clock is the parent %s of clk id %d\n", __func__, - stm32mp1_clk_parent_name[sel[s].parent[p]], - stm32mp1_clk_parent_sel_name[s], - (u32)id); -#endif + log_content("%s clock is the parent %s of clk id %d\n", + stm32mp1_clk_parent_name[sel[s].parent[p]], + stm32mp1_clk_parent_sel_name[s], + (u32)id); return sel[s].parent[p]; } - pr_err("%s: no parents defined for clk id %d\n", - __func__, (u32)id); + log_err("no parents defined for clk id %d\n", (u32)id); return -EINVAL; } @@ -1124,7 +1123,7 @@ static ulong stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p) if (!uclass_get_device_by_name(UCLASS_CLK, "ck_dsi_phy", &dev)) { if (clk_request(dev, &clk)) { - pr_err("ck_dsi_phy request"); + log_err("ck_dsi_phy request"); } else { clk.id = 0; clock = clk_get_rate(&clk); @@ -1136,8 +1135,7 @@ static ulong stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p) break; } - debug("%s(%d) clock = %lx : %ld kHz\n", - __func__, p, clock, clock / 1000); + log_debug("id=%d clock = %lx : %ld kHz\n", p, clock, clock / 1000); return clock; } @@ -1156,7 +1154,7 @@ static int stm32mp1_clk_enable(struct clk *clk) else setbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit)); - debug("%s: id clock %d has been enabled\n", __func__, (u32)clk->id); + dev_dbg(clk->dev, "%s: id clock %d has been enabled\n", __func__, (u32)clk->id); return 0; } @@ -1177,7 +1175,7 @@ static int stm32mp1_clk_disable(struct clk *clk) else clrbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit)); - debug("%s: id clock %d has been disabled\n", __func__, (u32)clk->id); + dev_dbg(clk->dev, "%s: id clock %d has been disabled\n", __func__, (u32)clk->id); return 0; } @@ -1193,10 +1191,9 @@ static ulong stm32mp1_clk_get_rate(struct clk *clk) rate = stm32mp1_clk_get(priv, p); -#ifdef DEBUG - debug("%s: computed rate for id clock %d is %d (parent is %s)\n", - __func__, (u32)clk->id, (u32)rate, stm32mp1_clk_parent_name[p]); -#endif + dev_vdbg(clk->dev, "computed rate for id clock %d is %d (parent is %s)\n", + (u32)clk->id, (u32)rate, stm32mp1_clk_parent_name[p]); + return rate; } @@ -1335,7 +1332,7 @@ static int stm32mp1_pll1_opp(struct stm32mp1_clk_priv *priv, int clksrc, ret = stm32mp1_get_max_opp_freq(priv, &output_freq); if (ret) { - debug("PLL1 OPP configuration not found (%d).\n", ret); + log_debug("PLL1 OPP configuration not found (%d).\n", ret); return ret; } @@ -1440,8 +1437,8 @@ static int stm32mp1_osc_wait(int enable, fdt_addr_t rcc, u32 offset, TIMEOUT_1S); if (ret) - pr_err("OSC %x @ %x timeout for enable=%d : 0x%x\n", - mask_rdy, address, enable, readl(address)); + log_err("OSC %x @ %x timeout for enable=%d : 0x%x\n", + mask_rdy, address, enable, readl(address)); return ret; } @@ -1529,8 +1526,8 @@ static int stm32mp1_set_hsidiv(fdt_addr_t rcc, u8 hsidiv) val & RCC_OCRDYR_HSIDIVRDY, TIMEOUT_200MS); if (ret) - pr_err("HSIDIV failed @ 0x%x: 0x%x\n", - address, readl(address)); + log_err("HSIDIV failed @ 0x%x: 0x%x\n", + address, readl(address)); return ret; } @@ -1546,7 +1543,7 @@ static int stm32mp1_hsidiv(fdt_addr_t rcc, ulong hsifreq) break; if (hsidiv == 4) { - pr_err("clk-hsi frequency invalid"); + log_err("clk-hsi frequency invalid"); return -1; } @@ -1577,8 +1574,8 @@ static int pll_output(struct stm32mp1_clk_priv *priv, int pll_id, int output) TIMEOUT_200MS); if (ret) { - pr_err("PLL%d start failed @ 0x%x: 0x%x\n", - pll_id, pllxcr, readl(pllxcr)); + log_err("PLL%d start failed @ 0x%x: 0x%x\n", + pll_id, pllxcr, readl(pllxcr)); return ret; } @@ -1640,7 +1637,7 @@ static int pll_config(struct stm32mp1_clk_priv *priv, int pll_id, if (refclk < (stm32mp1_pll[type].refclk_min * 1000000) || refclk > (stm32mp1_pll[type].refclk_max * 1000000)) { - debug("invalid refclk = %x\n", (u32)refclk); + log_err("invalid refclk = %x\n", (u32)refclk); return -EINVAL; } if (type == PLL_800 && refclk >= 8000000) @@ -1736,7 +1733,7 @@ static __maybe_unused int pll_set_rate(struct udevice *dev, divn = (value >> 13) - 1; if (divn < DIVN_MIN || divn > stm32mp1_pll[type].divn_max) { - pr_err("divn invalid = %d", divn); + dev_err(dev, "divn invalid = %d", divn); return -EINVAL; } fracv = value - ((divn + 1) << 13); @@ -1761,8 +1758,8 @@ static int set_clksrc(struct stm32mp1_clk_priv *priv, unsigned int clksrc) ret = readl_poll_timeout(address, val, val & RCC_SELR_SRCRDY, TIMEOUT_200MS); if (ret) - pr_err("CLKSRC %x start failed @ 0x%x: 0x%x\n", - clksrc, address, readl(address)); + log_err("CLKSRC %x start failed @ 0x%x: 0x%x\n", + clksrc, address, readl(address)); return ret; } @@ -1781,7 +1778,7 @@ static void stgen_config(struct stm32mp1_clk_priv *priv) if (cntfid0 != rate) { u64 counter; - pr_debug("System Generic Counter (STGEN) update\n"); + log_debug("System Generic Counter (STGEN) update\n"); clrbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN); counter = (u64)readl(stgenc + STGENC_CNTCVL); counter |= ((u64)(readl(stgenc + STGENC_CNTCVU))) << 32; @@ -1807,8 +1804,8 @@ static int set_clkdiv(unsigned int clkdiv, u32 address) ret = readl_poll_timeout(address, val, val & RCC_DIVR_DIVRDY, TIMEOUT_200MS); if (ret) - pr_err("CLKDIV %x start failed @ 0x%x: 0x%x\n", - clkdiv, address, readl(address)); + log_err("CLKDIV %x start failed @ 0x%x: 0x%x\n", + clkdiv, address, readl(address)); return ret; } @@ -1891,13 +1888,13 @@ static int stm32mp1_clktree(struct udevice *dev) /* check mandatory field */ ret = dev_read_u32_array(dev, "st,clksrc", clksrc, CLKSRC_NB); if (ret < 0) { - debug("field st,clksrc invalid: error %d\n", ret); + dev_dbg(dev, "field st,clksrc invalid: error %d\n", ret); return -FDT_ERR_NOTFOUND; } ret = dev_read_u32_array(dev, "st,clkdiv", clkdiv, CLKDIV_NB); if (ret < 0) { - debug("field st,clkdiv invalid: error %d\n", ret); + dev_dbg(dev, "field st,clkdiv invalid: error %d\n", ret); return -FDT_ERR_NOTFOUND; } @@ -1911,11 +1908,11 @@ static int stm32mp1_clktree(struct udevice *dev) pllcfg_valid[i] = ofnode_valid(node); pllcsg_set[i] = false; if (pllcfg_valid[i]) { - debug("DT for PLL %d @ %s\n", i, name); + dev_dbg(dev, "DT for PLL %d @ %s\n", i, name); ret = ofnode_read_u32_array(node, "cfg", pllcfg[i], PLLCFG_NB); if (ret < 0) { - debug("field cfg invalid: error %d\n", ret); + dev_dbg(dev, "field cfg invalid: error %d\n", ret); return -FDT_ERR_NOTFOUND; } pllfracv[i] = ofnode_read_u32_default(node, "frac", 0); @@ -1925,30 +1922,30 @@ static int stm32mp1_clktree(struct udevice *dev) if (!ret) { pllcsg_set[i] = true; } else if (ret != -FDT_ERR_NOTFOUND) { - debug("invalid csg node for pll@%d res=%d\n", - i, ret); + dev_dbg(dev, "invalid csg node for pll@%d res=%d\n", + i, ret); return ret; } } else if (i == _PLL1) { /* use OPP for PLL1 for A7 CPU */ - debug("DT for PLL %d with OPP\n", i); + dev_dbg(dev, "DT for PLL %d with OPP\n", i); ret = stm32mp1_pll1_opp(priv, clksrc[CLKSRC_PLL12], pllcfg[i], &pllfracv[i]); if (ret) { - debug("PLL %d with OPP error = %d\n", i, ret); + dev_dbg(dev, "PLL %d with OPP error = %d\n", i, ret); return ret; } pllcfg_valid[i] = true; } } - debug("configuration MCO\n"); + dev_dbg(dev, "configuration MCO\n"); stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO1], clkdiv[CLKDIV_MCO1]); stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO2], clkdiv[CLKDIV_MCO2]); - debug("switch ON osillator\n"); + dev_dbg(dev, "switch ON osillator\n"); /* * switch ON oscillator found in device-tree, * HSI already ON after bootrom @@ -1986,24 +1983,24 @@ static int stm32mp1_clktree(struct udevice *dev) stm32mp1_csi_set(rcc, 1); /* come back to HSI */ - debug("come back to HSI\n"); + dev_dbg(dev, "come back to HSI\n"); set_clksrc(priv, CLK_MPU_HSI); set_clksrc(priv, CLK_AXI_HSI); set_clksrc(priv, CLK_MCU_HSI); - debug("pll stop\n"); + dev_dbg(dev, "pll stop\n"); for (i = 0; i < _PLL_NB; i++) pll_stop(priv, i); /* configure HSIDIV */ - debug("configure HSIDIV\n"); + dev_dbg(dev, "configure HSIDIV\n"); if (priv->osc[_HSI]) { stm32mp1_hsidiv(rcc, priv->osc[_HSI]); stgen_config(priv); } /* select DIV */ - debug("select DIV\n"); + dev_dbg(dev, "select DIV\n"); /* no ready bit when MPUSRC != CLK_MPU_PLL1P_DIV, MPUDIV is disabled */ writel(clkdiv[CLKDIV_MPU] & RCC_DIVR_DIV_MASK, rcc + RCC_MPCKDIVR); set_clkdiv(clkdiv[CLKDIV_AXI], rcc + RCC_AXIDIVR); @@ -2018,17 +2015,17 @@ static int stm32mp1_clktree(struct udevice *dev) writel(clkdiv[CLKDIV_RTC] & RCC_DIVR_DIV_MASK, rcc + RCC_RTCDIVR); /* configure PLLs source */ - debug("configure PLLs source\n"); + dev_dbg(dev, "configure PLLs source\n"); set_clksrc(priv, clksrc[CLKSRC_PLL12]); set_clksrc(priv, clksrc[CLKSRC_PLL3]); set_clksrc(priv, clksrc[CLKSRC_PLL4]); /* configure and start PLLs */ - debug("configure PLLs\n"); + dev_dbg(dev, "configure PLLs\n"); for (i = 0; i < _PLL_NB; i++) { if (!pllcfg_valid[i]) continue; - debug("configure PLL %d\n", i); + dev_dbg(dev, "configure PLL %d\n", i); pll_config(priv, i, pllcfg[i], pllfracv[i]); if (pllcsg_set[i]) pll_csg(priv, i, pllcsg[i]); @@ -2039,7 +2036,7 @@ static int stm32mp1_clktree(struct udevice *dev) for (i = 0; i < _PLL_NB; i++) { if (!pllcfg_valid[i]) continue; - debug("output PLL %d\n", i); + dev_dbg(dev, "output PLL %d\n", i); pll_output(priv, i, pllcfg[i][PLLCFG_O]); } @@ -2048,14 +2045,14 @@ static int stm32mp1_clktree(struct udevice *dev) stm32mp1_lse_wait(rcc); /* configure with expected clock source */ - debug("CLKSRC\n"); + dev_dbg(dev, "CLKSRC\n"); set_clksrc(priv, clksrc[CLKSRC_MPU]); set_clksrc(priv, clksrc[CLKSRC_AXI]); set_clksrc(priv, clksrc[CLKSRC_MCU]); set_rtcsrc(priv, clksrc[CLKSRC_RTC], lse_css); /* configure PKCK */ - debug("PKCK\n"); + dev_dbg(dev, "PKCK\n"); pkcs_cell = dev_read_prop(dev, "st,pkcs", &len); if (pkcs_cell) { bool ckper_disabled = false; @@ -2081,7 +2078,7 @@ static int stm32mp1_clktree(struct udevice *dev) /* STGEN clock source can change with CLK_STGEN_XXX */ stgen_config(priv); - debug("oscillator off\n"); + dev_dbg(dev, "oscillator off\n"); /* switch OFF HSI if not found in device-tree */ if (!priv->osc[_HSI]) stm32mp1_hsi_set(rcc, 0); @@ -2147,14 +2144,12 @@ static ulong stm32mp1_clk_set_rate(struct clk *clk, unsigned long clk_rate) case DSI_PX: break; default: - pr_err("not supported"); + dev_err(clk->dev, "Set of clk %ld not supported", clk->id); return -EINVAL; } p = stm32mp1_clk_get_parent(priv, clk->id); -#ifdef DEBUG - debug("%s: parent = %d:%s\n", __func__, p, stm32mp1_clk_parent_name[p]); -#endif + dev_vdbg(clk->dev, "parent = %d:%s\n", p, stm32mp1_clk_parent_name[p]); if (p < 0) return -EINVAL; @@ -2192,7 +2187,7 @@ static void stm32mp1_osc_clk_init(const char *name, clk.id = 0; if (!uclass_get_device_by_name(UCLASS_CLK, name, &dev)) { if (clk_request(dev, &clk)) - pr_err("%s request", name); + log_err("%s request", name); else priv->osc[index] = clk_get_rate(&clk); } @@ -2214,7 +2209,7 @@ static void stm32mp1_osc_init(struct udevice *dev) for (i = 0; i < NB_OSC; i++) { stm32mp1_osc_clk_init(name[i], priv, i); - debug("%d: %s => %x\n", i, name[i], (u32)priv->osc[i]); + dev_dbg(dev, "%d: %s => %x\n", i, name[i], (u32)priv->osc[i]); } } @@ -2288,11 +2283,11 @@ static int stm32mp1_clk_probe(struct udevice *dev) if (!(gd->flags & GD_FLG_RELOC)) result = stm32mp1_clktree(dev); if (result) - printf("clock tree initialization failed (%d)\n", result); + dev_err(dev, "clock tree initialization failed (%d)\n", result); #endif #ifndef CONFIG_SPL_BUILD -#if defined(DEBUG) +#if defined(VERBOSE_DEBUG) /* display debug information for probe after relocation */ if (gd->flags & GD_FLG_RELOC) stm32mp1_clk_dump(priv); @@ -2306,14 +2301,14 @@ static int stm32mp1_clk_probe(struct udevice *dev) if (gd->flags & GD_FLG_RELOC) { char buf[32]; - printf("Clocks:\n"); - printf("- MPU : %s MHz\n", strmhz(buf, gd->cpu_clk)); - printf("- MCU : %s MHz\n", - strmhz(buf, stm32mp1_clk_get(priv, _CK_MCU))); - printf("- AXI : %s MHz\n", strmhz(buf, gd->bus_clk)); - printf("- PER : %s MHz\n", - strmhz(buf, stm32mp1_clk_get(priv, _CK_PER))); - printf("- DDR : %s MHz\n", strmhz(buf, gd->mem_clk)); + log_info("Clocks:\n"); + log_info("- MPU : %s MHz\n", strmhz(buf, gd->cpu_clk)); + log_info("- MCU : %s MHz\n", + strmhz(buf, stm32mp1_clk_get(priv, _CK_MCU))); + log_info("- AXI : %s MHz\n", strmhz(buf, gd->bus_clk)); + log_info("- PER : %s MHz\n", + strmhz(buf, stm32mp1_clk_get(priv, _CK_PER))); + log_info("- DDR : %s MHz\n", strmhz(buf, gd->mem_clk)); } #endif /* CONFIG_DISPLAY_CPUINFO */ #endif diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index 237fd17f167..522e7242214 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -7,5 +7,6 @@ obj-$(CONFIG_MT8512) += clk-mt8512.o obj-$(CONFIG_TARGET_MT7623) += clk-mt7623.o obj-$(CONFIG_TARGET_MT7622) += clk-mt7622.o obj-$(CONFIG_TARGET_MT7629) += clk-mt7629.o +obj-$(CONFIG_TARGET_MT8183) += clk-mt8183.o obj-$(CONFIG_TARGET_MT8516) += clk-mt8516.o obj-$(CONFIG_TARGET_MT8518) += clk-mt8518.o diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c new file mode 100644 index 00000000000..17e653a1f00 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8183.c @@ -0,0 +1,823 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * MediaTek clock driver for MT8183 SoC + * + * Copyright (C) 2020 BayLibre, SAS + * Copyright (c) 2020 MediaTek Inc. + * Author: Fabien Parent <fparent@baylibre.com> + * Author: Weiyi Lu <weiyi.lu@mediatek.com> + */ + +#include <common.h> +#include <dm.h> +#include <asm/io.h> +#include <dt-bindings/clock/mt8183-clk.h> + +#include "clk-mtk.h" + +#define MT8183_PLL_FMAX (3800UL * MHZ) +#define MT8183_PLL_FMIN (1500UL * MHZ) + +/* apmixedsys */ +#define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, _pcwbits, \ + _pcwibits, _pd_reg, _pd_shift, _pcw_reg, _pcw_shift) { \ + .id = _id, \ + .reg = _reg, \ + .pwr_reg = _pwr_reg, \ + .en_mask = _en_mask, \ + .rst_bar_mask = _rst_bar_mask, \ + .fmax = MT8183_PLL_FMAX, \ + .fmin = MT8183_PLL_FMIN, \ + .flags = _flags, \ + .pcwbits = _pcwbits, \ + .pcwibits = _pcwibits, \ + .pd_reg = _pd_reg, \ + .pd_shift = _pd_shift, \ + .pcw_reg = _pcw_reg, \ + .pcw_shift = _pcw_shift, \ + } + +static const struct mtk_pll_data apmixed_plls[] = { + PLL(CLK_APMIXED_ARMPLL_LL, 0x0200, 0x020C, 0x00000001, + HAVE_RST_BAR, BIT(24), 22, 8, 0x0204, 24, + 0x0204, 0), + PLL(CLK_APMIXED_ARMPLL_L, 0x0210, 0x021C, 0x00000001, + HAVE_RST_BAR, BIT(24), 22, 8, 0x0214, 24, + 0x0214, 0), + PLL(CLK_APMIXED_CCIPLL, 0x0290, 0x029C, 0x00000001, + HAVE_RST_BAR, BIT(24), 22, 8, 0x0294, 24, + 0x0294, 0), + PLL(CLK_APMIXED_MAINPLL, 0x0220, 0x022C, 0x00000001, + HAVE_RST_BAR, BIT(24), 22, 8, 0x0224, 24, + 0x0224, 0), + PLL(CLK_APMIXED_UNIV2PLL, 0x0230, 0x023C, 0x00000001, + HAVE_RST_BAR, BIT(24), 22, 8, 0x0234, 24, + 0x0234, 0), + PLL(CLK_APMIXED_MSDCPLL, 0x0250, 0x025C, 0x00000001, + 0, 0, 22, 8, 0x0254, 24, 0x0254, 0), + PLL(CLK_APMIXED_MMPLL, 0x0270, 0x027C, 0x00000001, + HAVE_RST_BAR, BIT(23), 22, 8, 0x0274, 24, + 0x0274, 0), + PLL(CLK_APMIXED_MFGPLL, 0x0240, 0x024C, 0x00000001, + 0, 0, 22, 8, 0x0244, 24, 0x0244, 0), + PLL(CLK_APMIXED_TVDPLL, 0x0260, 0x026C, 0x00000001, + 0, 0, 22, 8, 0x0264, 24, 0x0264, 0), + PLL(CLK_APMIXED_APLL1, 0x02A0, 0x02B0, 0x00000001, + 0, 0, 32, 8, 0x02A0, 1, 0x02A4, 0), + PLL(CLK_APMIXED_APLL2, 0x02b4, 0x02c4, 0x00000001, + 0, 0, 32, 8, 0x02B4, 1, 0x02B8, 0), +}; + +static const struct mtk_fixed_clk top_fixed_clks[] = { + FIXED_CLK(CLK_TOP_CLK26M, CLK_XTAL, 26000000), + FIXED_CLK(CLK_TOP_ULPOSC, CLK_XTAL, 250000), + FIXED_CLK(CLK_TOP_UNIVP_192M, CLK_TOP_UNIVPLL, 192000000), +}; + +static const struct mtk_fixed_factor top_fixed_divs[] = { + FACTOR(CLK_TOP_CLK13M, CLK_TOP_CLK26M, 1, 2, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_F26M_CK_D2, CLK_TOP_CLK26M, 1, 2, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_SYSPLL_CK, CLK_APMIXED_MAINPLL, 1, + 1, CLK_PARENT_APMIXED), + FACTOR(CLK_TOP_SYSPLL_D2, CLK_TOP_SYSPLL_CK, 1, + 2, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_SYSPLL_D3, CLK_APMIXED_MAINPLL, 1, + 3, CLK_PARENT_APMIXED), + FACTOR(CLK_TOP_SYSPLL_D5, CLK_APMIXED_MAINPLL, 1, + 5, CLK_PARENT_APMIXED), + FACTOR(CLK_TOP_SYSPLL_D7, CLK_APMIXED_MAINPLL, 1, + 7, CLK_PARENT_APMIXED), + FACTOR(CLK_TOP_SYSPLL_D2_D2, CLK_TOP_SYSPLL_D2, 1, + 2, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_SYSPLL_D2_D4, CLK_TOP_SYSPLL_D2, 1, + 4, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_SYSPLL_D2_D8, CLK_TOP_SYSPLL_D2, 1, + 8, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_SYSPLL_D2_D16, CLK_TOP_SYSPLL_D2, 1, + 16, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_SYSPLL_D3_D2, CLK_TOP_SYSPLL_D3, 1, + 2, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_SYSPLL_D3_D4, CLK_TOP_SYSPLL_D3, 1, + 4, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_SYSPLL_D3_D8, CLK_TOP_SYSPLL_D3, 1, + 8, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_SYSPLL_D5_D2, CLK_TOP_SYSPLL_D5, 1, + 2, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_SYSPLL_D5_D4, CLK_TOP_SYSPLL_D5, 1, + 4, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_SYSPLL_D7_D2, CLK_TOP_SYSPLL_D7, 1, + 2, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_SYSPLL_D7_D4, CLK_TOP_SYSPLL_D7, 1, + 4, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_UNIVPLL_CK, CLK_TOP_UNIVPLL, 1, 1, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_UNIVPLL_D2, CLK_TOP_UNIVPLL_CK, 1, + 2, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_UNIVPLL_D3, CLK_TOP_UNIVPLL, 1, 3, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_UNIVPLL_D5, CLK_TOP_UNIVPLL, 1, 5, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_UNIVPLL_D7, CLK_TOP_UNIVPLL, 1, 7, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_UNIVPLL_D2_D2, CLK_TOP_UNIVPLL_D2, 1, + 2, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_UNIVPLL_D2_D4, CLK_TOP_UNIVPLL_D2, 1, + 4, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_UNIVPLL_D2_D8, CLK_TOP_UNIVPLL_D2, 1, + 8, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_UNIVPLL_D3_D2, CLK_TOP_UNIVPLL_D3, 1, + 2, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_UNIVPLL_D3_D4, CLK_TOP_UNIVPLL_D3, 1, + 4, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_UNIVPLL_D3_D8, CLK_TOP_UNIVPLL_D3, 1, + 8, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_UNIVPLL_D5_D2, CLK_TOP_UNIVPLL_D5, 1, + 2, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_UNIVPLL_D5_D4, CLK_TOP_UNIVPLL_D5, 1, + 4, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_UNIVPLL_D5_D8, CLK_TOP_UNIVPLL_D5, 1, + 8, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_UNIVP_192M_CK, CLK_TOP_UNIVP_192M, 1, 1, + CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_UNIVP_192M_D2, CLK_TOP_UNIVP_192M_CK, 1, + 2, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_UNIVP_192M_D4, CLK_TOP_UNIVP_192M_CK, 1, + 4, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_UNIVP_192M_D8, CLK_TOP_UNIVP_192M_CK, 1, + 8, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_UNIVP_192M_D16, CLK_TOP_UNIVP_192M_CK, 1, + 16, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_UNIVP_192M_D32, CLK_TOP_UNIVP_192M_CK, 1, + 32, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_APLL1_CK, CLK_APMIXED_APLL1, 1, 1, CLK_PARENT_APMIXED), + FACTOR(CLK_TOP_APLL1_D2, CLK_APMIXED_APLL1, 1, 2, CLK_PARENT_APMIXED), + FACTOR(CLK_TOP_APLL1_D4, CLK_APMIXED_APLL1, 1, 4, CLK_PARENT_APMIXED), + FACTOR(CLK_TOP_APLL1_D8, CLK_APMIXED_APLL1, 1, 8, CLK_PARENT_APMIXED), + FACTOR(CLK_TOP_APLL2_CK, CLK_APMIXED_APLL2, 1, 1, CLK_PARENT_APMIXED), + FACTOR(CLK_TOP_APLL2_D2, CLK_APMIXED_APLL2, 1, 2, CLK_PARENT_APMIXED), + FACTOR(CLK_TOP_APLL2_D4, CLK_APMIXED_APLL2, 1, 4, CLK_PARENT_APMIXED), + FACTOR(CLK_TOP_APLL2_D8, CLK_APMIXED_APLL2, 1, 8, CLK_PARENT_APMIXED), + FACTOR(CLK_TOP_TVDPLL_CK, CLK_APMIXED_TVDPLL, 1, 1, CLK_PARENT_APMIXED), + FACTOR(CLK_TOP_TVDPLL_D2, CLK_TOP_TVDPLL_CK, 1, 2, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_TVDPLL_D4, CLK_APMIXED_TVDPLL, 1, 4, CLK_PARENT_APMIXED), + FACTOR(CLK_TOP_TVDPLL_D8, CLK_APMIXED_TVDPLL, 1, 8, CLK_PARENT_APMIXED), + FACTOR(CLK_TOP_TVDPLL_D16, CLK_APMIXED_TVDPLL, 1, + 16, CLK_PARENT_APMIXED), + FACTOR(CLK_TOP_MMPLL_CK, CLK_APMIXED_MMPLL, 1, 1, CLK_PARENT_APMIXED), + FACTOR(CLK_TOP_MMPLL_D4, CLK_APMIXED_MMPLL, 1, 4, CLK_PARENT_APMIXED), + FACTOR(CLK_TOP_MMPLL_D4_D2, CLK_TOP_MMPLL_D4, 1, + 2, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_MMPLL_D4_D4, CLK_TOP_MMPLL_D4, 1, 4, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_MMPLL_D5, CLK_APMIXED_MMPLL, 1, 5, CLK_PARENT_APMIXED), + FACTOR(CLK_TOP_MMPLL_D5_D2, CLK_TOP_MMPLL_D5, 1, + 2, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_MMPLL_D5_D4, CLK_TOP_MMPLL_D5, 1, + 4, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_MMPLL_D6, CLK_APMIXED_MMPLL, 1, 6, CLK_PARENT_APMIXED), + FACTOR(CLK_TOP_MMPLL_D7, CLK_APMIXED_MMPLL, 1, 7, CLK_PARENT_APMIXED), + FACTOR(CLK_TOP_MFGPLL_CK, CLK_APMIXED_MFGPLL, 1, 1, CLK_PARENT_APMIXED), + FACTOR(CLK_TOP_MSDCPLL_CK, CLK_APMIXED_MSDCPLL, 1, + 1, CLK_PARENT_APMIXED), + FACTOR(CLK_TOP_MSDCPLL_D2, CLK_APMIXED_MSDCPLL, 1, + 2, CLK_PARENT_APMIXED), + FACTOR(CLK_TOP_MSDCPLL_D4, CLK_APMIXED_MSDCPLL, 1, + 4, CLK_PARENT_APMIXED), + FACTOR(CLK_TOP_MSDCPLL_D8, CLK_APMIXED_MSDCPLL, 1, + 8, CLK_PARENT_APMIXED), + FACTOR(CLK_TOP_MSDCPLL_D16, CLK_APMIXED_MSDCPLL, 1, + 16, CLK_PARENT_APMIXED), + FACTOR(CLK_TOP_AD_OSC_CK, CLK_TOP_ULPOSC, 1, 1, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_OSC_D2, CLK_TOP_ULPOSC, 1, 2, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_OSC_D4, CLK_TOP_ULPOSC, 1, 4, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_OSC_D8, CLK_TOP_ULPOSC, 1, 8, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_OSC_D16, CLK_TOP_ULPOSC, 1, 16, CLK_PARENT_TOPCKGEN), + FACTOR(CLK_TOP_UNIVPLL, CLK_APMIXED_UNIV2PLL, 1, 2, CLK_PARENT_APMIXED), + FACTOR(CLK_TOP_UNIVPLL_D3_D16, CLK_TOP_UNIVPLL_D3, 1, + 16, CLK_PARENT_TOPCKGEN), +}; + +static const int axi_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_SYSPLL_D2_D4, + CLK_TOP_SYSPLL_D7, + CLK_TOP_OSC_D4 +}; + +static const int mm_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_MMPLL_D7, + CLK_TOP_SYSPLL_D3, + CLK_TOP_UNIVPLL_D2_D2, + CLK_TOP_SYSPLL_D2_D2, + CLK_TOP_SYSPLL_D3_D2 +}; + +static const int img_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_MMPLL_D6, + CLK_TOP_UNIVPLL_D3, + CLK_TOP_SYSPLL_D3, + CLK_TOP_UNIVPLL_D2_D2, + CLK_TOP_SYSPLL_D2_D2, + CLK_TOP_UNIVPLL_D3_D2, + CLK_TOP_SYSPLL_D3_D2 +}; + +static const int cam_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_SYSPLL_D2, + CLK_TOP_MMPLL_D6, + CLK_TOP_SYSPLL_D3, + CLK_TOP_MMPLL_D7, + CLK_TOP_UNIVPLL_D3, + CLK_TOP_UNIVPLL_D2_D2, + CLK_TOP_SYSPLL_D2_D2, + CLK_TOP_SYSPLL_D3_D2, + CLK_TOP_UNIVPLL_D3_D2 +}; + +static const int dsp_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_MMPLL_D6, + CLK_TOP_MMPLL_D7, + CLK_TOP_UNIVPLL_D3, + CLK_TOP_SYSPLL_D3, + CLK_TOP_UNIVPLL_D2_D2, + CLK_TOP_SYSPLL_D2_D2, + CLK_TOP_UNIVPLL_D3_D2, + CLK_TOP_SYSPLL_D3_D2 +}; + +static const int dsp1_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_MMPLL_D6, + CLK_TOP_MMPLL_D7, + CLK_TOP_UNIVPLL_D3, + CLK_TOP_SYSPLL_D3, + CLK_TOP_UNIVPLL_D2_D2, + CLK_TOP_SYSPLL_D2_D2, + CLK_TOP_UNIVPLL_D3_D2, + CLK_TOP_SYSPLL_D3_D2 +}; + +static const int dsp2_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_MMPLL_D6, + CLK_TOP_MMPLL_D7, + CLK_TOP_UNIVPLL_D3, + CLK_TOP_SYSPLL_D3, + CLK_TOP_UNIVPLL_D2_D2, + CLK_TOP_SYSPLL_D2_D2, + CLK_TOP_UNIVPLL_D3_D2, + CLK_TOP_SYSPLL_D3_D2 +}; + +static const int ipu_if_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_MMPLL_D6, + CLK_TOP_MMPLL_D7, + CLK_TOP_UNIVPLL_D3, + CLK_TOP_SYSPLL_D3, + CLK_TOP_UNIVPLL_D2_D2, + CLK_TOP_SYSPLL_D2_D2, + CLK_TOP_UNIVPLL_D3_D2, + CLK_TOP_SYSPLL_D3_D2 +}; + +static const int mfg_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_MFGPLL_CK, + CLK_TOP_UNIVPLL_D3, + CLK_TOP_SYSPLL_D3 +}; + +static const int f52m_mfg_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL_D3_D2, + CLK_TOP_UNIVPLL_D3_D4, + CLK_TOP_UNIVPLL_D3_D8 +}; + +static const int camtg_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVP_192M_D8, + CLK_TOP_UNIVPLL_D3_D8, + CLK_TOP_UNIVP_192M_D4, + CLK_TOP_UNIVPLL_D3_D16, + CLK_TOP_F26M_CK_D2, + CLK_TOP_UNIVP_192M_D16, + CLK_TOP_UNIVP_192M_D32 +}; + +static const int camtg2_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVP_192M_D8, + CLK_TOP_UNIVPLL_D3_D8, + CLK_TOP_UNIVP_192M_D4, + CLK_TOP_UNIVPLL_D3_D16, + CLK_TOP_F26M_CK_D2, + CLK_TOP_UNIVP_192M_D16, + CLK_TOP_UNIVP_192M_D32 +}; + +static const int camtg3_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVP_192M_D8, + CLK_TOP_UNIVPLL_D3_D8, + CLK_TOP_UNIVP_192M_D4, + CLK_TOP_UNIVPLL_D3_D16, + CLK_TOP_F26M_CK_D2, + CLK_TOP_UNIVP_192M_D16, + CLK_TOP_UNIVP_192M_D32 +}; + +static const int camtg4_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVP_192M_D8, + CLK_TOP_UNIVPLL_D3_D8, + CLK_TOP_UNIVP_192M_D4, + CLK_TOP_UNIVPLL_D3_D16, + CLK_TOP_F26M_CK_D2, + CLK_TOP_UNIVP_192M_D16, + CLK_TOP_UNIVP_192M_D32 +}; + +static const int uart_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL_D3_D8 +}; + +static const int spi_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_SYSPLL_D5_D2, + CLK_TOP_SYSPLL_D3_D4, + CLK_TOP_MSDCPLL_D4 +}; + +static const int msdc50_hclk_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_SYSPLL_D2_D2, + CLK_TOP_SYSPLL_D3_D2 +}; + +static const int msdc50_0_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_MSDCPLL_CK, + CLK_TOP_MSDCPLL_D2, + CLK_TOP_UNIVPLL_D2_D4, + CLK_TOP_SYSPLL_D3_D2, + CLK_TOP_UNIVPLL_D2_D2 +}; + +static const int msdc30_1_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL_D3_D2, + CLK_TOP_SYSPLL_D3_D2, + CLK_TOP_SYSPLL_D7, + CLK_TOP_MSDCPLL_D2 +}; + +static const int msdc30_2_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL_D3_D2, + CLK_TOP_SYSPLL_D3_D2, + CLK_TOP_SYSPLL_D7, + CLK_TOP_MSDCPLL_D2 +}; + +static const int audio_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_SYSPLL_D5_D4, + CLK_TOP_SYSPLL_D7_D4, + CLK_TOP_SYSPLL_D2_D16 +}; + +static const int aud_intbus_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_SYSPLL_D2_D4, + CLK_TOP_SYSPLL_D7_D2 +}; + +static const int pmicspi_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_SYSPLL_D2_D8, + CLK_TOP_OSC_D8 +}; + +static const int fpwrap_ulposc_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_OSC_D16, + CLK_TOP_OSC_D4, + CLK_TOP_OSC_D8 +}; + +static const int atb_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_SYSPLL_D2_D2, + CLK_TOP_SYSPLL_D5 +}; + +static const int sspm_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL_D2_D4, + CLK_TOP_SYSPLL_D2_D2, + CLK_TOP_UNIVPLL_D2_D2, + CLK_TOP_SYSPLL_D3 +}; + +static const int dpi0_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_TVDPLL_D2, + CLK_TOP_TVDPLL_D4, + CLK_TOP_TVDPLL_D8, + CLK_TOP_TVDPLL_D16, + CLK_TOP_UNIVPLL_D5_D2, + CLK_TOP_UNIVPLL_D3_D4, + CLK_TOP_SYSPLL_D3_D4, + CLK_TOP_UNIVPLL_D3_D8 +}; + +static const int scam_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_SYSPLL_D5_D2 +}; + +static const int disppwm_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL_D3_D4, + CLK_TOP_OSC_D2, + CLK_TOP_OSC_D4, + CLK_TOP_OSC_D16 +}; + +static const int usb_top_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL_D5_D4, + CLK_TOP_UNIVPLL_D3_D4, + CLK_TOP_UNIVPLL_D5_D2 +}; + +static const int ssusb_top_xhci_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL_D5_D4, + CLK_TOP_UNIVPLL_D3_D4, + CLK_TOP_UNIVPLL_D5_D2 +}; + +static const int spm_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_SYSPLL_D2_D8 +}; + +static const int i2c_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_SYSPLL_D2_D8, + CLK_TOP_UNIVPLL_D5_D2 +}; + +static const int scp_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL_D2_D8, + CLK_TOP_SYSPLL_D5, + CLK_TOP_SYSPLL_D2_D2, + CLK_TOP_UNIVPLL_D2_D2, + CLK_TOP_SYSPLL_D3, + CLK_TOP_UNIVPLL_D3 +}; + +static const int seninf_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL_D2_D2, + CLK_TOP_UNIVPLL_D3_D2, + CLK_TOP_UNIVPLL_D2_D4 +}; + +static const int dxcc_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_SYSPLL_D2_D2, + CLK_TOP_SYSPLL_D2_D4, + CLK_TOP_SYSPLL_D2_D8 +}; + +static const int aud_engen1_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_APLL1_D2, + CLK_TOP_APLL1_D4, + CLK_TOP_APLL1_D8 +}; + +static const int aud_engen2_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_APLL2_D2, + CLK_TOP_APLL2_D4, + CLK_TOP_APLL2_D8 +}; + +static const int faes_ufsfde_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_SYSPLL_D2, + CLK_TOP_SYSPLL_D2_D2, + CLK_TOP_SYSPLL_D3, + CLK_TOP_SYSPLL_D2_D4, + CLK_TOP_UNIVPLL_D3 +}; + +static const int fufs_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_SYSPLL_D2_D4, + CLK_TOP_SYSPLL_D2_D8, + CLK_TOP_SYSPLL_D2_D16 +}; + +static const int aud_1_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_APLL1_CK +}; + +static const int aud_2_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_APLL2_CK +}; + +static const struct mtk_composite top_muxes[] = { + /* CLK_CFG_0 */ + MUX(CLK_TOP_MUX_AXI, axi_parents, 0x40, 0, 2), + MUX(CLK_TOP_MUX_MM, mm_parents, 0x40, 8, 3), + MUX(CLK_TOP_MUX_IMG, img_parents, 0x40, 16, 3), + MUX(CLK_TOP_MUX_CAM, cam_parents, 0x40, 24, 4), + /* CLK_CFG_1 */ + MUX(CLK_TOP_MUX_DSP, dsp_parents, 0x50, 0, 4), + MUX(CLK_TOP_MUX_DSP1, dsp1_parents, 0x50, 8, 4), + MUX(CLK_TOP_MUX_DSP2, dsp2_parents, 0x50, 16, 4), + MUX(CLK_TOP_MUX_IPU_IF, ipu_if_parents, 0x50, 24, 4), + /* CLK_CFG_2 */ + MUX(CLK_TOP_MUX_MFG, mfg_parents, 0x60, 0, 2), + MUX(CLK_TOP_MUX_F52M_MFG, f52m_mfg_parents, 0x60, 8, 2), + MUX(CLK_TOP_MUX_CAMTG, camtg_parents, 0x60, 16, 3), + MUX(CLK_TOP_MUX_CAMTG2, camtg2_parents, 0x60, 24, 3), + /* CLK_CFG_3 */ + MUX(CLK_TOP_MUX_CAMTG3, camtg3_parents, 0x70, 0, 3), + MUX(CLK_TOP_MUX_CAMTG4, camtg4_parents, 0x70, 8, 3), + MUX(CLK_TOP_MUX_UART, uart_parents, 0x70, 16, 1), + MUX(CLK_TOP_MUX_SPI, spi_parents, 0x70, 24, 2), + /* CLK_CFG_4 */ + MUX(CLK_TOP_MUX_MSDC50_0_HCLK, msdc50_hclk_parents, 0x80, 0, 2), + MUX(CLK_TOP_MUX_MSDC50_0, msdc50_0_parents, 0x80, 8, 3), + MUX(CLK_TOP_MUX_MSDC30_1, msdc30_1_parents, 0x80, 16, 3), + MUX(CLK_TOP_MUX_MSDC30_2, msdc30_2_parents, 0x80, 24, 3), + /* CLK_CFG_5 */ + MUX(CLK_TOP_MUX_AUDIO, audio_parents, 0x90, 0, 2), + MUX(CLK_TOP_MUX_AUD_INTBUS, aud_intbus_parents, 0x90, 8, 2), + MUX(CLK_TOP_MUX_PMICSPI, pmicspi_parents, 0x90, 16, 2), + MUX(CLK_TOP_MUX_FPWRAP_ULPOSC, fpwrap_ulposc_parents, 0x90, 24, 2), + /* CLK_CFG_6 */ + MUX(CLK_TOP_MUX_ATB, atb_parents, 0xa0, 0, 2), + MUX(CLK_TOP_MUX_SSPM, sspm_parents, 0xa0, 8, 3), + MUX(CLK_TOP_MUX_DPI0, dpi0_parents, 0xa0, 16, 4), + MUX(CLK_TOP_MUX_SCAM, scam_parents, 0xa0, 24, 1), + /* CLK_CFG_7 */ + MUX(CLK_TOP_MUX_DISP_PWM, disppwm_parents, 0xb0, 0, 3), + MUX(CLK_TOP_MUX_USB_TOP, usb_top_parents, 0xb0, 8, 2), + MUX(CLK_TOP_MUX_SSUSB_TOP_XHCI, ssusb_top_xhci_parents, 0xb0, 16, 2), + MUX(CLK_TOP_MUX_SPM, spm_parents, 0xb0, 24, 1), + /* CLK_CFG_8 */ + MUX(CLK_TOP_MUX_I2C, i2c_parents, 0xc0, 0, 2), + MUX(CLK_TOP_MUX_SCP, scp_parents, 0xc0, 8, 3), + MUX(CLK_TOP_MUX_SENINF, seninf_parents, 0xc0, 16, 2), + MUX(CLK_TOP_MUX_DXCC, dxcc_parents, 0xc0, 24, 2), + /* CLK_CFG_9 */ + MUX(CLK_TOP_MUX_AUD_ENG1, aud_engen1_parents, 0xd0, 0, 2), + MUX(CLK_TOP_MUX_AUD_ENG2, aud_engen2_parents, 0xd0, 8, 2), + MUX(CLK_TOP_MUX_FAES_UFSFDE, faes_ufsfde_parents, 0xd0, 16, 3), + MUX(CLK_TOP_MUX_FUFS, fufs_parents, 0xd0, 24, 2), + /* CLK_CFG_10 */ + MUX(CLK_TOP_MUX_AUD_1, aud_1_parents, 0xe0, 0, 1), + MUX(CLK_TOP_MUX_AUD_2, aud_2_parents, 0xe0, 8, 1), +}; + +static const struct mtk_clk_tree mt8183_clk_tree = { + .xtal_rate = 26 * MHZ, + .xtal2_rate = 26 * MHZ, + .fdivs_offs = CLK_TOP_CLK13M, + .muxes_offs = CLK_TOP_MUX_AXI, + .plls = apmixed_plls, + .fclks = top_fixed_clks, + .fdivs = top_fixed_divs, + .muxes = top_muxes, +}; + +static const struct mtk_gate_regs infra0_cg_regs = { + .set_ofs = 0x80, + .clr_ofs = 0x84, + .sta_ofs = 0x90, +}; + +static const struct mtk_gate_regs infra1_cg_regs = { + .set_ofs = 0x88, + .clr_ofs = 0x8c, + .sta_ofs = 0x94, +}; + +static const struct mtk_gate_regs infra2_cg_regs = { + .set_ofs = 0xa4, + .clr_ofs = 0xa8, + .sta_ofs = 0xac, +}; + +static const struct mtk_gate_regs infra3_cg_regs = { + .set_ofs = 0xc0, + .clr_ofs = 0xc4, + .sta_ofs = 0xc8, +}; + +#define GATE_INFRA0(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &infra0_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ + } + +#define GATE_INFRA1(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &infra1_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ + } + +#define GATE_INFRA2(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &infra2_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ + } + +#define GATE_INFRA3(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &infra3_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ + } + +static const struct mtk_gate infra_clks[] = { + /* INFRA0 */ + GATE_INFRA0(CLK_INFRA_PMIC_TMR, CLK_TOP_MUX_AXI, 0), + GATE_INFRA0(CLK_INFRA_PMIC_AP, CLK_TOP_MUX_AXI, 1), + GATE_INFRA0(CLK_INFRA_PMIC_MD, CLK_TOP_MUX_AXI, 2), + GATE_INFRA0(CLK_INFRA_PMIC_CONN, CLK_TOP_MUX_AXI, 3), + GATE_INFRA0(CLK_INFRA_SCPSYS, CLK_TOP_MUX_SCP, 4), + GATE_INFRA0(CLK_INFRA_SEJ, CLK_TOP_CLK26M, 5), + GATE_INFRA0(CLK_INFRA_APXGPT, CLK_TOP_MUX_AXI, 6), + GATE_INFRA0(CLK_INFRA_ICUSB, CLK_TOP_MUX_AXI, 8), + GATE_INFRA0(CLK_INFRA_GCE, CLK_TOP_MUX_AXI, 9), + GATE_INFRA0(CLK_INFRA_THERM, CLK_TOP_MUX_AXI, 10), + GATE_INFRA0(CLK_INFRA_I2C0, CLK_TOP_MUX_I2C, 11), + GATE_INFRA0(CLK_INFRA_I2C1, CLK_TOP_MUX_I2C, 12), + GATE_INFRA0(CLK_INFRA_I2C2, CLK_TOP_MUX_I2C, 13), + GATE_INFRA0(CLK_INFRA_I2C3, CLK_TOP_MUX_I2C, 14), + GATE_INFRA0(CLK_INFRA_PWM_HCLK, CLK_TOP_MUX_AXI, 15), + GATE_INFRA0(CLK_INFRA_PWM1, CLK_TOP_MUX_I2C, 16), + GATE_INFRA0(CLK_INFRA_PWM2, CLK_TOP_MUX_I2C, 17), + GATE_INFRA0(CLK_INFRA_PWM3, CLK_TOP_MUX_I2C, 18), + GATE_INFRA0(CLK_INFRA_PWM4, CLK_TOP_MUX_I2C, 19), + GATE_INFRA0(CLK_INFRA_PWM, CLK_TOP_MUX_I2C, 21), + GATE_INFRA0(CLK_INFRA_UART0, CLK_TOP_MUX_UART, 22), + GATE_INFRA0(CLK_INFRA_UART1, CLK_TOP_MUX_UART, 23), + GATE_INFRA0(CLK_INFRA_UART2, CLK_TOP_MUX_UART, 24), + GATE_INFRA0(CLK_INFRA_UART3, CLK_TOP_MUX_UART, 25), + GATE_INFRA0(CLK_INFRA_GCE_26M, CLK_TOP_MUX_AXI, 27), + GATE_INFRA0(CLK_INFRA_CQ_DMA_FPC, CLK_TOP_MUX_AXI, 28), + GATE_INFRA0(CLK_INFRA_BTIF, CLK_TOP_MUX_AXI, 31), + /* INFRA1 */ + GATE_INFRA1(CLK_INFRA_SPI0, CLK_TOP_MUX_SPI, 1), + GATE_INFRA1(CLK_INFRA_MSDC0, CLK_TOP_MUX_MSDC50_0_HCLK, 2), + GATE_INFRA1(CLK_INFRA_MSDC1, CLK_TOP_MUX_AXI, 4), + GATE_INFRA1(CLK_INFRA_MSDC2, CLK_TOP_MUX_AXI, 5), + GATE_INFRA1(CLK_INFRA_MSDC0_SCK, CLK_TOP_MUX_MSDC50_0, 6), + GATE_INFRA1(CLK_INFRA_DVFSRC, CLK_TOP_CLK26M, 7), + GATE_INFRA1(CLK_INFRA_GCPU, CLK_TOP_MUX_AXI, 8), + GATE_INFRA1(CLK_INFRA_TRNG, CLK_TOP_MUX_AXI, 9), + GATE_INFRA1(CLK_INFRA_AUXADC, CLK_TOP_CLK26M, 10), + GATE_INFRA1(CLK_INFRA_CPUM, CLK_TOP_MUX_AXI, 11), + GATE_INFRA1(CLK_INFRA_CCIF1_AP, CLK_TOP_MUX_AXI, 12), + GATE_INFRA1(CLK_INFRA_CCIF1_MD, CLK_TOP_MUX_AXI, 13), + GATE_INFRA1(CLK_INFRA_AUXADC_MD, CLK_TOP_CLK26M, 14), + GATE_INFRA1(CLK_INFRA_MSDC1_SCK, CLK_TOP_MUX_MSDC30_1, 16), + GATE_INFRA1(CLK_INFRA_MSDC2_SCK, CLK_TOP_MUX_MSDC30_2, 17), + GATE_INFRA1(CLK_INFRA_AP_DMA, CLK_TOP_MUX_AXI, 18), + GATE_INFRA1(CLK_INFRA_XIU, CLK_TOP_MUX_AXI, 19), + GATE_INFRA1(CLK_INFRA_DEVICE_APC, CLK_TOP_MUX_AXI, 20), + GATE_INFRA1(CLK_INFRA_CCIF_AP, CLK_TOP_MUX_AXI, 23), + GATE_INFRA1(CLK_INFRA_DEBUGSYS, CLK_TOP_MUX_AXI, 24), + GATE_INFRA1(CLK_INFRA_AUDIO, CLK_TOP_MUX_AXI, 25), + GATE_INFRA1(CLK_INFRA_CCIF_MD, CLK_TOP_MUX_AXI, 26), + GATE_INFRA1(CLK_INFRA_DXCC_SEC_CORE, CLK_TOP_MUX_DXCC, 27), + GATE_INFRA1(CLK_INFRA_DXCC_AO, CLK_TOP_MUX_DXCC, 28), + GATE_INFRA1(CLK_INFRA_DEVMPU_BCLK, CLK_TOP_MUX_AXI, 30), + GATE_INFRA1(CLK_INFRA_DRAMC_F26M, CLK_TOP_CLK26M, 31), + /* INFRA2 */ + GATE_INFRA2(CLK_INFRA_IRTX, CLK_TOP_CLK26M, 0), + GATE_INFRA2(CLK_INFRA_USB, CLK_TOP_MUX_USB_TOP, 1), + GATE_INFRA2(CLK_INFRA_DISP_PWM, CLK_TOP_MUX_AXI, 2), + GATE_INFRA2(CLK_INFRA_CLDMA_BCLK, CLK_TOP_MUX_AXI, 3), + GATE_INFRA2(CLK_INFRA_AUDIO_26M_BCLK, CLK_TOP_CLK26M, 4), + GATE_INFRA2(CLK_INFRA_SPI1, CLK_TOP_MUX_SPI, 6), + GATE_INFRA2(CLK_INFRA_I2C4, CLK_TOP_MUX_I2C, 7), + GATE_INFRA2(CLK_INFRA_MODEM_TEMP_SHARE, CLK_TOP_CLK26M, 8), + GATE_INFRA2(CLK_INFRA_SPI2, CLK_TOP_MUX_SPI, 9), + GATE_INFRA2(CLK_INFRA_SPI3, CLK_TOP_MUX_SPI, 10), + GATE_INFRA2(CLK_INFRA_UNIPRO_SCK, CLK_TOP_MUX_SSUSB_TOP_XHCI, 11), + GATE_INFRA2(CLK_INFRA_UNIPRO_TICK, CLK_TOP_MUX_FUFS, 12), + GATE_INFRA2(CLK_INFRA_UFS_MP_SAP_BCLK, CLK_TOP_MUX_FUFS, 13), + GATE_INFRA2(CLK_INFRA_MD32_BCLK, CLK_TOP_MUX_AXI, 14), + GATE_INFRA2(CLK_INFRA_UNIPRO_MBIST, CLK_TOP_MUX_AXI, 16), + GATE_INFRA2(CLK_INFRA_I2C5, CLK_TOP_MUX_I2C, 18), + GATE_INFRA2(CLK_INFRA_I2C5_ARBITER, CLK_TOP_MUX_I2C, 19), + GATE_INFRA2(CLK_INFRA_I2C5_IMM, CLK_TOP_MUX_I2C, 20), + GATE_INFRA2(CLK_INFRA_I2C1_ARBITER, CLK_TOP_MUX_I2C, 21), + GATE_INFRA2(CLK_INFRA_I2C1_IMM, CLK_TOP_MUX_I2C, 22), + GATE_INFRA2(CLK_INFRA_I2C2_ARBITER, CLK_TOP_MUX_I2C, 23), + GATE_INFRA2(CLK_INFRA_I2C2_IMM, CLK_TOP_MUX_I2C, 24), + GATE_INFRA2(CLK_INFRA_SPI4, CLK_TOP_MUX_SPI, 25), + GATE_INFRA2(CLK_INFRA_SPI5, CLK_TOP_MUX_SPI, 26), + GATE_INFRA2(CLK_INFRA_CQ_DMA, CLK_TOP_MUX_AXI, 27), + GATE_INFRA2(CLK_INFRA_UFS, CLK_TOP_MUX_FUFS, 28), + GATE_INFRA2(CLK_INFRA_AES_UFSFDE, CLK_TOP_MUX_FAES_UFSFDE, 29), + GATE_INFRA2(CLK_INFRA_UFS_TICK, CLK_TOP_MUX_FUFS, 30), + /* INFRA3 */ + GATE_INFRA3(CLK_INFRA_MSDC0_SELF, CLK_TOP_MUX_MSDC50_0, 0), + GATE_INFRA3(CLK_INFRA_MSDC1_SELF, CLK_TOP_MUX_MSDC50_0, 1), + GATE_INFRA3(CLK_INFRA_MSDC2_SELF, CLK_TOP_MUX_MSDC50_0, 2), + GATE_INFRA3(CLK_INFRA_UFS_AXI, CLK_TOP_MUX_AXI, 5), + GATE_INFRA3(CLK_INFRA_I2C6, CLK_TOP_MUX_I2C, 6), + GATE_INFRA3(CLK_INFRA_AP_MSDC0, CLK_TOP_MUX_MSDC50_0_HCLK, 7), + GATE_INFRA3(CLK_INFRA_MD_MSDC0, CLK_TOP_MUX_MSDC50_0_HCLK, 8), + GATE_INFRA3(CLK_INFRA_CCIF2_AP, CLK_TOP_MUX_AXI, 16), + GATE_INFRA3(CLK_INFRA_CCIF2_MD, CLK_TOP_MUX_AXI, 17), + GATE_INFRA3(CLK_INFRA_CCIF3_AP, CLK_TOP_MUX_AXI, 18), + GATE_INFRA3(CLK_INFRA_CCIF3_MD, CLK_TOP_MUX_AXI, 19), + GATE_INFRA3(CLK_INFRA_SEJ_F13M, CLK_TOP_CLK26M, 20), + GATE_INFRA3(CLK_INFRA_AES_BCLK, CLK_TOP_MUX_AXI, 21), + GATE_INFRA3(CLK_INFRA_I2C7, CLK_TOP_MUX_I2C, 22), + GATE_INFRA3(CLK_INFRA_I2C8, CLK_TOP_MUX_I2C, 23), + GATE_INFRA3(CLK_INFRA_FBIST2FPC, CLK_TOP_MUX_MSDC50_0, 24), +}; + +static int mt8183_apmixedsys_probe(struct udevice *dev) +{ + return mtk_common_clk_init(dev, &mt8183_clk_tree); +} + +static int mt8183_topckgen_probe(struct udevice *dev) +{ + return mtk_common_clk_init(dev, &mt8183_clk_tree); +} + +static int mt8183_infracfg_probe(struct udevice *dev) +{ + return mtk_common_clk_gate_init(dev, &mt8183_clk_tree, infra_clks); +} + +static const struct udevice_id mt8183_apmixed_compat[] = { + { .compatible = "mediatek,mt8183-apmixedsys", }, + { } +}; + +static const struct udevice_id mt8183_topckgen_compat[] = { + { .compatible = "mediatek,mt8183-topckgen", }, + { } +}; + +static const struct udevice_id mt8183_infracfg_compat[] = { + { .compatible = "mediatek,mt8183-infracfg", }, + { } +}; + +U_BOOT_DRIVER(mtk_clk_apmixedsys) = { + .name = "mt8183-apmixedsys", + .id = UCLASS_CLK, + .of_match = mt8183_apmixed_compat, + .probe = mt8183_apmixedsys_probe, + .priv_auto = sizeof(struct mtk_clk_priv), + .ops = &mtk_clk_apmixedsys_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +U_BOOT_DRIVER(mtk_clk_topckgen) = { + .name = "mt8183-topckgen", + .id = UCLASS_CLK, + .of_match = mt8183_topckgen_compat, + .probe = mt8183_topckgen_probe, + .priv_auto = sizeof(struct mtk_clk_priv), + .ops = &mtk_clk_topckgen_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +U_BOOT_DRIVER(mtk_clk_infracfg) = { + .name = "mt8183-infracfg", + .id = UCLASS_CLK, + .of_match = mt8183_infracfg_compat, + .probe = mt8183_infracfg_probe, + .priv_auto = sizeof(struct mtk_clk_priv), + .ops = &mtk_clk_gate_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile index c873d6976fa..7204383e173 100644 --- a/drivers/clk/meson/Makefile +++ b/drivers/clk/meson/Makefile @@ -6,4 +6,5 @@ obj-$(CONFIG_CLK_MESON_GX) += gxbb.o obj-$(CONFIG_CLK_MESON_AXG) += axg.o obj-$(CONFIG_CLK_MESON_G12A) += g12a.o +obj-$(CONFIG_CLK_MESON_G12A) += g12a-ao.o diff --git a/drivers/clk/meson/g12a-ao.c b/drivers/clk/meson/g12a-ao.c new file mode 100644 index 00000000000..0148529e04f --- /dev/null +++ b/drivers/clk/meson/g12a-ao.c @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include <common.h> +#include <log.h> +#include <asm/io.h> +#include <clk-uclass.h> +#include <dm.h> +#include <regmap.h> +#include <syscon.h> +#include <dt-bindings/clock/g12a-aoclkc.h> + +#include "clk_meson.h" + +struct meson_clk { + struct regmap *map; +}; + +#define AO_CLK_GATE0 0x4c +#define AO_SAR_CLK 0x90 + +static struct meson_gate gates[] = { + MESON_GATE(CLKID_AO_SAR_ADC, AO_CLK_GATE0, 8), + MESON_GATE(CLKID_AO_SAR_ADC_CLK, AO_SAR_CLK, 8), +}; + +static int meson_set_gate(struct clk *clk, bool on) +{ + struct meson_clk *priv = dev_get_priv(clk->dev); + struct meson_gate *gate; + + if (clk->id >= ARRAY_SIZE(gates)) + return -ENOENT; + + gate = &gates[clk->id]; + + if (gate->reg == 0) + return 0; + + regmap_update_bits(priv->map, gate->reg, + BIT(gate->bit), on ? BIT(gate->bit) : 0); + + return 0; +} + +static int meson_clk_enable(struct clk *clk) +{ + return meson_set_gate(clk, true); +} + +static int meson_clk_disable(struct clk *clk) +{ + return meson_set_gate(clk, false); +} + +static int meson_clk_probe(struct udevice *dev) +{ + struct meson_clk *priv = dev_get_priv(dev); + + priv->map = syscon_node_to_regmap(dev_ofnode(dev_get_parent(dev))); + if (IS_ERR(priv->map)) + return PTR_ERR(priv->map); + + return 0; +} + +static struct clk_ops meson_clk_ops = { + .disable = meson_clk_disable, + .enable = meson_clk_enable, +}; + +static const struct udevice_id meson_clk_ids[] = { + { .compatible = "amlogic,meson-g12a-aoclkc" }, + { } +}; + +U_BOOT_DRIVER(meson_clk_axg) = { + .name = "meson_clk_g12a_ao", + .id = UCLASS_CLK, + .of_match = meson_clk_ids, + .priv_auto = sizeof(struct meson_clk), + .ops = &meson_clk_ops, + .probe = meson_clk_probe, +}; diff --git a/drivers/clk/microchip/Kconfig b/drivers/clk/microchip/Kconfig new file mode 100644 index 00000000000..b70241559db --- /dev/null +++ b/drivers/clk/microchip/Kconfig @@ -0,0 +1,5 @@ +config CLK_MPFS + bool "Clock support for Microchip PolarFire SoC" + depends on CLK && CLK_CCF + help + This enables support clock driver for Microchip PolarFire SoC platform. diff --git a/drivers/clk/microchip/Makefile b/drivers/clk/microchip/Makefile new file mode 100644 index 00000000000..904b345d75f --- /dev/null +++ b/drivers/clk/microchip/Makefile @@ -0,0 +1 @@ +obj-y += mpfs_clk.o mpfs_clk_cfg.o mpfs_clk_periph.o diff --git a/drivers/clk/microchip/mpfs_clk.c b/drivers/clk/microchip/mpfs_clk.c new file mode 100644 index 00000000000..722c79b7c0e --- /dev/null +++ b/drivers/clk/microchip/mpfs_clk.c @@ -0,0 +1,123 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Microchip Technology Inc. + * Padmarao Begari <padmarao.begari@microchip.com> + */ +#include <common.h> +#include <clk.h> +#include <clk-uclass.h> +#include <dm.h> +#include <log.h> +#include <dm/device.h> +#include <dm/devres.h> +#include <dm/uclass.h> +#include <linux/err.h> + +#include "mpfs_clk.h" + +/* All methods are delegated to CCF clocks */ + +static ulong mpfs_clk_get_rate(struct clk *clk) +{ + struct clk *c; + int err = clk_get_by_id(clk->id, &c); + + if (err) + return err; + return clk_get_rate(c); +} + +static ulong mpfs_clk_set_rate(struct clk *clk, unsigned long rate) +{ + struct clk *c; + int err = clk_get_by_id(clk->id, &c); + + if (err) + return err; + return clk_set_rate(c, rate); +} + +static int mpfs_clk_set_parent(struct clk *clk, struct clk *parent) +{ + struct clk *c, *p; + int err = clk_get_by_id(clk->id, &c); + + if (err) + return err; + + err = clk_get_by_id(parent->id, &p); + if (err) + return err; + + return clk_set_parent(c, p); +} + +static int mpfs_clk_endisable(struct clk *clk, bool enable) +{ + struct clk *c; + int err = clk_get_by_id(clk->id, &c); + + if (err) + return err; + return enable ? clk_enable(c) : clk_disable(c); +} + +static int mpfs_clk_enable(struct clk *clk) +{ + return mpfs_clk_endisable(clk, true); +} + +static int mpfs_clk_disable(struct clk *clk) +{ + return mpfs_clk_endisable(clk, false); +} + +static int mpfs_clk_probe(struct udevice *dev) +{ + int ret; + void __iomem *base; + u32 clk_rate; + const char *parent_clk_name; + struct clk *clk = dev_get_priv(dev); + + base = dev_read_addr_ptr(dev); + if (!base) + return -EINVAL; + + ret = clk_get_by_index(dev, 0, clk); + if (ret) + return ret; + + dev_read_u32(clk->dev, "clock-frequency", &clk_rate); + parent_clk_name = clk->dev->name; + + ret = mpfs_clk_register_cfgs(base, clk_rate, parent_clk_name); + if (ret) + return ret; + + ret = mpfs_clk_register_periphs(base, clk_rate, "clk_ahb"); + + return ret; +} + +static const struct clk_ops mpfs_clk_ops = { + .set_rate = mpfs_clk_set_rate, + .get_rate = mpfs_clk_get_rate, + .set_parent = mpfs_clk_set_parent, + .enable = mpfs_clk_enable, + .disable = mpfs_clk_disable, +}; + +static const struct udevice_id mpfs_of_match[] = { + { .compatible = "microchip,mpfs-clkcfg" }, + { } +}; + +U_BOOT_DRIVER(mpfs_clk) = { + .name = "mpfs_clk", + .id = UCLASS_CLK, + .of_match = mpfs_of_match, + .ops = &mpfs_clk_ops, + .probe = mpfs_clk_probe, + .priv_auto = sizeof(struct clk), +}; diff --git a/drivers/clk/microchip/mpfs_clk.h b/drivers/clk/microchip/mpfs_clk.h new file mode 100644 index 00000000000..8e3fc55ae39 --- /dev/null +++ b/drivers/clk/microchip/mpfs_clk.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2020 Microchip Technology Inc. + * Padmarao Begari <padmarao.begari@microchip.com> + */ +#ifndef __MICROCHIP_MPFS_CLK_H +#define __MICROCHIP_MPFS_CLK_H + +#include <linux/clk-provider.h> +/** + * mpfs_clk_register_cfgs() - register configuration clocks + * + * @base: base address of the mpfs system register. + * @clk_rate: the mpfs pll clock rate. + * @parent_name: a pointer to parent clock name. + * @return zero on success, or a negative error code. + */ +int mpfs_clk_register_cfgs(void __iomem *base, u32 clk_rate, + const char *parent_name); +/** + * mpfs_clk_register_periphs() - register peripheral clocks + * + * @base: base address of the mpfs system register. + * @clk_rate: the mpfs pll clock rate. + * @parent_name: a pointer to parent clock name. + * @return zero on success, or a negative error code. + */ +int mpfs_clk_register_periphs(void __iomem *base, u32 clk_rate, + const char *parent_name); +/** + * divider_get_val() - get the clock divider value + * + * @rate: requested clock rate. + * @parent_rate: parent clock rate. + * @table: a pointer to clock divider table. + * @width: width of the divider bit field. + * @flags: common clock framework flags. + * @return divider value on success, or a negative error code. + */ +int divider_get_val(unsigned long rate, unsigned long parent_rate, + const struct clk_div_table *table, + u8 width, unsigned long flags); + +#endif /* __MICROCHIP_MPFS_CLK_H */ diff --git a/drivers/clk/microchip/mpfs_clk_cfg.c b/drivers/clk/microchip/mpfs_clk_cfg.c new file mode 100644 index 00000000000..fefddd14137 --- /dev/null +++ b/drivers/clk/microchip/mpfs_clk_cfg.c @@ -0,0 +1,152 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Microchip Technology Inc. + * Padmarao Begari <padmarao.begari@microchip.com> + */ +#include <common.h> +#include <clk.h> +#include <clk-uclass.h> +#include <asm/io.h> +#include <dm/device.h> +#include <dm/devres.h> +#include <dm/uclass.h> +#include <dt-bindings/clock/microchip-mpfs-clock.h> +#include <linux/err.h> + +#include "mpfs_clk.h" + +#define MPFS_CFG_CLOCK "mpfs_cfg_clock" + +#define REG_CLOCK_CONFIG_CR 0x08 + +/* CPU and AXI clock divisors */ +static const struct clk_div_table mpfs_div_cpu_axi_table[] = { + { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 }, + { 0, 0 } +}; + +/* AHB clock divisors */ +static const struct clk_div_table mpfs_div_ahb_table[] = { + { 1, 2 }, { 2, 4}, { 3, 8 }, + { 0, 0 } +}; + +/** + * struct mpfs_cfg_clock - per instance of configuration clock + * @id: index of a configuration clock + * @name: name of a configuration clock + * @shift: shift to the divider bit field of a configuration clock + * @width: width of the divider bit field of a configation clock + * @table: clock divider table instance + * @flags: common clock framework flags + */ +struct mpfs_cfg_clock { + unsigned int id; + const char *name; + u8 shift; + u8 width; + const struct clk_div_table *table; + unsigned long flags; +}; + +/** + * struct mpfs_cfg_hw_clock - hardware configuration clock (cpu, axi, ahb) + * @cfg: configuration clock instance + * @sys_base: base address of the mpfs system register + * @prate: the pll clock rate + * @hw: clock instance + */ +struct mpfs_cfg_hw_clock { + struct mpfs_cfg_clock cfg; + void __iomem *sys_base; + u32 prate; + struct clk hw; +}; + +#define to_mpfs_cfg_clk(_hw) container_of(_hw, struct mpfs_cfg_hw_clock, hw) + +static ulong mpfs_cfg_clk_recalc_rate(struct clk *hw) +{ + struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw); + struct mpfs_cfg_clock *cfg = &cfg_hw->cfg; + void __iomem *base_addr = cfg_hw->sys_base; + unsigned long rate; + u32 val; + + val = readl(base_addr + REG_CLOCK_CONFIG_CR) >> cfg->shift; + val &= clk_div_mask(cfg->width); + rate = cfg_hw->prate / (1u << val); + hw->rate = rate; + + return rate; +} + +static ulong mpfs_cfg_clk_set_rate(struct clk *hw, ulong rate) +{ + struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw); + struct mpfs_cfg_clock *cfg = &cfg_hw->cfg; + void __iomem *base_addr = cfg_hw->sys_base; + u32 val; + int divider_setting; + + divider_setting = divider_get_val(rate, cfg_hw->prate, cfg->table, cfg->width, cfg->flags); + + if (divider_setting < 0) + return divider_setting; + + val = readl(base_addr + REG_CLOCK_CONFIG_CR); + val &= ~(clk_div_mask(cfg->width) << cfg_hw->cfg.shift); + val |= divider_setting << cfg->shift; + writel(val, base_addr + REG_CLOCK_CONFIG_CR); + + return clk_get_rate(hw); +} + +#define CLK_CFG(_id, _name, _shift, _width, _table, _flags) { \ + .cfg.id = _id, \ + .cfg.name = _name, \ + .cfg.shift = _shift, \ + .cfg.width = _width, \ + .cfg.table = _table, \ + .cfg.flags = _flags, \ + } + +static struct mpfs_cfg_hw_clock mpfs_cfg_clks[] = { + CLK_CFG(CLK_CPU, "clk_cpu", 0, 2, mpfs_div_cpu_axi_table, 0), + CLK_CFG(CLK_AXI, "clk_axi", 2, 2, mpfs_div_cpu_axi_table, 0), + CLK_CFG(CLK_AHB, "clk_ahb", 4, 2, mpfs_div_ahb_table, 0), +}; + +int mpfs_clk_register_cfgs(void __iomem *base, u32 clk_rate, + const char *parent_name) +{ + int ret; + int i, id, num_clks; + const char *name; + struct clk *hw; + + num_clks = ARRAY_SIZE(mpfs_cfg_clks); + for (i = 0; i < num_clks; i++) { + hw = &mpfs_cfg_clks[i].hw; + mpfs_cfg_clks[i].sys_base = base; + mpfs_cfg_clks[i].prate = clk_rate; + name = mpfs_cfg_clks[i].cfg.name; + ret = clk_register(hw, MPFS_CFG_CLOCK, name, parent_name); + if (ret) + ERR_PTR(ret); + id = mpfs_cfg_clks[i].cfg.id; + clk_dm(id, hw); + } + return 0; +} + +const struct clk_ops mpfs_cfg_clk_ops = { + .set_rate = mpfs_cfg_clk_set_rate, + .get_rate = mpfs_cfg_clk_recalc_rate, +}; + +U_BOOT_DRIVER(mpfs_cfg_clock) = { + .name = MPFS_CFG_CLOCK, + .id = UCLASS_CLK, + .ops = &mpfs_cfg_clk_ops, +}; diff --git a/drivers/clk/microchip/mpfs_clk_periph.c b/drivers/clk/microchip/mpfs_clk_periph.c new file mode 100644 index 00000000000..61d90eb4a85 --- /dev/null +++ b/drivers/clk/microchip/mpfs_clk_periph.c @@ -0,0 +1,187 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Microchip Technology Inc. + * Padmarao Begari <padmarao.begari@microchip.com> + */ +#include <common.h> +#include <clk.h> +#include <clk-uclass.h> +#include <asm/io.h> +#include <dm/device.h> +#include <dm/devres.h> +#include <dm/uclass.h> +#include <dt-bindings/clock/microchip-mpfs-clock.h> +#include <linux/err.h> + +#include "mpfs_clk.h" + +#define MPFS_PERIPH_CLOCK "mpfs_periph_clock" + +#define REG_CLOCK_CONFIG_CR 0x08 +#define REG_SUBBLK_CLOCK_CR 0x84 +#define REG_SUBBLK_RESET_CR 0x88 + +#define CFG_CPU_SHIFT 0x0 +#define CFG_AXI_SHIFT 0x2 +#define CFG_AHB_SHIFT 0x4 +#define CFG_WIDTH 0x2 + +/** + * struct mpfs_periph_clock - per instance of peripheral clock + * @id: index of a peripheral clock + * @name: name of a peripheral clock + * @shift: shift to a peripheral clock bit field + * @flags: common clock framework flags + */ +struct mpfs_periph_clock { + unsigned int id; + const char *name; + u8 shift; + unsigned long flags; +}; + +/** + * struct mpfs_periph_hw_clock - hardware peripheral clock + * @periph: peripheral clock instance + * @sys_base: base address of the mpfs system register + * @prate: the pll clock rate + * @hw: clock instance + */ +struct mpfs_periph_hw_clock { + struct mpfs_periph_clock periph; + void __iomem *sys_base; + u32 prate; + struct clk hw; +}; + +#define to_mpfs_periph_clk(_hw) container_of(_hw, struct mpfs_periph_hw_clock, hw) + +static int mpfs_periph_clk_enable(struct clk *hw) +{ + struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw); + struct mpfs_periph_clock *periph = &periph_hw->periph; + void __iomem *base_addr = periph_hw->sys_base; + u32 reg, val; + + if (periph->flags != CLK_IS_CRITICAL) { + reg = readl(base_addr + REG_SUBBLK_RESET_CR); + val = reg & ~(1u << periph->shift); + writel(val, base_addr + REG_SUBBLK_RESET_CR); + + reg = readl(base_addr + REG_SUBBLK_CLOCK_CR); + val = reg | (1u << periph->shift); + writel(val, base_addr + REG_SUBBLK_CLOCK_CR); + } + + return 0; +} + +static int mpfs_periph_clk_disable(struct clk *hw) +{ + struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw); + struct mpfs_periph_clock *periph = &periph_hw->periph; + void __iomem *base_addr = periph_hw->sys_base; + u32 reg, val; + + if (periph->flags != CLK_IS_CRITICAL) { + reg = readl(base_addr + REG_SUBBLK_RESET_CR); + val = reg | (1u << periph->shift); + writel(val, base_addr + REG_SUBBLK_RESET_CR); + + reg = readl(base_addr + REG_SUBBLK_CLOCK_CR); + val = reg & ~(1u << periph->shift); + writel(val, base_addr + REG_SUBBLK_CLOCK_CR); + } + + return 0; +} + +static ulong mpfs_periph_clk_recalc_rate(struct clk *hw) +{ + struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw); + void __iomem *base_addr = periph_hw->sys_base; + unsigned long rate; + u32 val; + + val = readl(base_addr + REG_CLOCK_CONFIG_CR) >> CFG_AHB_SHIFT; + val &= clk_div_mask(CFG_WIDTH); + rate = periph_hw->prate / (1u << val); + hw->rate = rate; + + return rate; +} + +#define CLK_PERIPH(_id, _name, _shift, _flags) { \ + .periph.id = _id, \ + .periph.name = _name, \ + .periph.shift = _shift, \ + .periph.flags = _flags, \ + } + +static struct mpfs_periph_hw_clock mpfs_periph_clks[] = { + CLK_PERIPH(CLK_ENVM, "clk_periph_envm", 0, CLK_IS_CRITICAL), + CLK_PERIPH(CLK_MAC0, "clk_periph_mac0", 1, 0), + CLK_PERIPH(CLK_MAC1, "clk_periph_mac1", 2, 0), + CLK_PERIPH(CLK_MMC, "clk_periph_mmc", 3, 0), + CLK_PERIPH(CLK_TIMER, "clk_periph_timer", 4, 0), + CLK_PERIPH(CLK_MMUART0, "clk_periph_mmuart0", 5, 0), + CLK_PERIPH(CLK_MMUART1, "clk_periph_mmuart1", 6, 0), + CLK_PERIPH(CLK_MMUART2, "clk_periph_mmuart2", 7, 0), + CLK_PERIPH(CLK_MMUART3, "clk_periph_mmuart3", 8, 0), + CLK_PERIPH(CLK_MMUART4, "clk_periph_mmuart4", 9, 0), + CLK_PERIPH(CLK_SPI0, "clk_periph_spi0", 10, 0), + CLK_PERIPH(CLK_SPI1, "clk_periph_spi1", 11, 0), + CLK_PERIPH(CLK_I2C0, "clk_periph_i2c0", 12, 0), + CLK_PERIPH(CLK_I2C1, "clk_periph_i2c1", 13, 0), + CLK_PERIPH(CLK_CAN0, "clk_periph_can0", 14, 0), + CLK_PERIPH(CLK_CAN1, "clk_periph_can1", 15, 0), + CLK_PERIPH(CLK_USB, "clk_periph_usb", 16, 0), + CLK_PERIPH(CLK_RTC, "clk_periph_rtc", 18, 0), + CLK_PERIPH(CLK_QSPI, "clk_periph_qspi", 19, 0), + CLK_PERIPH(CLK_GPIO0, "clk_periph_gpio0", 20, 0), + CLK_PERIPH(CLK_GPIO1, "clk_periph_gpio1", 21, 0), + CLK_PERIPH(CLK_GPIO2, "clk_periph_gpio2", 22, 0), + CLK_PERIPH(CLK_DDRC, "clk_periph_ddrc", 23, CLK_IS_CRITICAL), + CLK_PERIPH(CLK_FIC0, "clk_periph_fic0", 24, 0), + CLK_PERIPH(CLK_FIC1, "clk_periph_fic1", 25, 0), + CLK_PERIPH(CLK_FIC2, "clk_periph_fic2", 26, 0), + CLK_PERIPH(CLK_FIC3, "clk_periph_fic3", 27, 0), + CLK_PERIPH(CLK_ATHENA, "clk_periph_athena", 28, 0), + CLK_PERIPH(CLK_CFM, "clk_periph_cfm", 29, 0), +}; + +int mpfs_clk_register_periphs(void __iomem *base, u32 clk_rate, + const char *parent_name) +{ + int ret; + int i, id, num_clks; + const char *name; + struct clk *hw; + + num_clks = ARRAY_SIZE(mpfs_periph_clks); + for (i = 0; i < num_clks; i++) { + hw = &mpfs_periph_clks[i].hw; + mpfs_periph_clks[i].sys_base = base; + mpfs_periph_clks[i].prate = clk_rate; + name = mpfs_periph_clks[i].periph.name; + ret = clk_register(hw, MPFS_PERIPH_CLOCK, name, parent_name); + if (ret) + ERR_PTR(ret); + id = mpfs_periph_clks[i].periph.id; + clk_dm(id, hw); + } + + return 0; +} + +const struct clk_ops mpfs_periph_clk_ops = { + .enable = mpfs_periph_clk_enable, + .disable = mpfs_periph_clk_disable, + .get_rate = mpfs_periph_clk_recalc_rate, +}; + +U_BOOT_DRIVER(mpfs_periph_clock) = { + .name = MPFS_PERIPH_CLOCK, + .id = UCLASS_CLK, + .ops = &mpfs_periph_clk_ops, +}; diff --git a/drivers/clk/ti/clk-am3-dpll.c b/drivers/clk/ti/clk-am3-dpll.c index 7916a24538b..90b4cc69efa 100644 --- a/drivers/clk/ti/clk-am3-dpll.c +++ b/drivers/clk/ti/clk-am3-dpll.c @@ -260,7 +260,7 @@ U_BOOT_DRIVER(clk_ti_am3_dpll) = { .name = "ti_am3_dpll_clock", .id = UCLASS_CLK, .of_match = clk_ti_am3_dpll_of_match, - .ofdata_to_platdata = clk_ti_am3_dpll_of_to_plat, + .of_to_plat = clk_ti_am3_dpll_of_to_plat, .probe = clk_ti_am3_dpll_probe, .remove = clk_ti_am3_dpll_remove, .priv_auto = sizeof(struct clk_ti_am3_dpll_priv), diff --git a/drivers/clk/ti/clk-ctrl.c b/drivers/clk/ti/clk-ctrl.c index 940e8d6cafb..3c6195b2086 100644 --- a/drivers/clk/ti/clk-ctrl.c +++ b/drivers/clk/ti/clk-ctrl.c @@ -148,7 +148,7 @@ U_BOOT_DRIVER(clk_ti_ctrl) = { .name = "ti_ctrl_clk", .id = UCLASS_CLK, .of_match = clk_ti_ctrl_ids, - .ofdata_to_platdata = clk_ti_ctrl_of_to_plat, + .of_to_plat = clk_ti_ctrl_of_to_plat, .ops = &clk_ti_ctrl_ops, .priv_auto = sizeof(struct clk_ti_ctrl_priv), }; diff --git a/drivers/clk/ti/clk-divider.c b/drivers/clk/ti/clk-divider.c index a8626377851..270f2fbdf0c 100644 --- a/drivers/clk/ti/clk-divider.c +++ b/drivers/clk/ti/clk-divider.c @@ -373,7 +373,7 @@ U_BOOT_DRIVER(clk_ti_divider) = { .name = "ti_divider_clock", .id = UCLASS_CLK, .of_match = clk_ti_divider_of_match, - .ofdata_to_platdata = clk_ti_divider_of_to_plat, + .of_to_plat = clk_ti_divider_of_to_plat, .probe = clk_ti_divider_probe, .remove = clk_ti_divider_remove, .priv_auto = sizeof(struct clk_ti_divider_priv), diff --git a/drivers/clk/ti/clk-gate.c b/drivers/clk/ti/clk-gate.c index 236eaed6df1..0ca453c8dee 100644 --- a/drivers/clk/ti/clk-gate.c +++ b/drivers/clk/ti/clk-gate.c @@ -87,7 +87,7 @@ U_BOOT_DRIVER(clk_ti_gate) = { .name = "ti_gate_clock", .id = UCLASS_CLK, .of_match = clk_ti_gate_of_match, - .ofdata_to_platdata = clk_ti_gate_of_to_plat, + .of_to_plat = clk_ti_gate_of_to_plat, .priv_auto = sizeof(struct clk_ti_gate_priv), .ops = &clk_ti_gate_ops, }; diff --git a/drivers/clk/ti/clk-mux.c b/drivers/clk/ti/clk-mux.c index 419502c3899..bb5e49e1142 100644 --- a/drivers/clk/ti/clk-mux.c +++ b/drivers/clk/ti/clk-mux.c @@ -245,7 +245,7 @@ U_BOOT_DRIVER(clk_ti_mux) = { .name = "ti_mux_clock", .id = UCLASS_CLK, .of_match = clk_ti_mux_of_match, - .ofdata_to_platdata = clk_ti_mux_of_to_plat, + .of_to_plat = clk_ti_mux_of_to_plat, .probe = clk_ti_mux_probe, .remove = clk_ti_mux_remove, .priv_auto = sizeof(struct clk_ti_mux_priv), diff --git a/drivers/core/uclass.c b/drivers/core/uclass.c index cdb975d5b31..f38122d54b5 100644 --- a/drivers/core/uclass.c +++ b/drivers/core/uclass.c @@ -757,6 +757,25 @@ int uclass_pre_remove_device(struct udevice *dev) } #endif +int uclass_probe_all(enum uclass_id id) +{ + struct udevice *dev; + int ret; + + ret = uclass_first_device(id, &dev); + if (ret || !dev) + return ret; + + /* Scanning uclass to probe all devices */ + while (dev) { + ret = uclass_next_device(&dev); + if (ret) + return ret; + } + + return 0; +} + UCLASS_DRIVER(nop) = { .id = UCLASS_NOP, .name = "nop", diff --git a/drivers/dma/bcm6348-iudma.c b/drivers/dma/bcm6348-iudma.c index 98577601b58..c04aa55cb42 100644 --- a/drivers/dma/bcm6348-iudma.c +++ b/drivers/dma/bcm6348-iudma.c @@ -313,10 +313,10 @@ static int bcm6348_iudma_request(struct dma *dma) ch_priv->desc_id = 0; if (bcm6348_iudma_chan_is_rx(dma->id)) { ch_priv->desc_cnt = 0; - ch_priv->busy_desc = calloc(ch_priv->desc_cnt, sizeof(bool)); + ch_priv->busy_desc = NULL; } else { ch_priv->desc_cnt = ch_priv->dma_ring_size; - ch_priv->busy_desc = NULL; + ch_priv->busy_desc = calloc(ch_priv->desc_cnt, sizeof(bool)); } return 0; diff --git a/drivers/fastboot/fb_mmc.c b/drivers/fastboot/fb_mmc.c index ae8e8e512f2..4e26cef9417 100644 --- a/drivers/fastboot/fb_mmc.c +++ b/drivers/fastboot/fb_mmc.c @@ -508,7 +508,7 @@ void fastboot_mmc_flash_write(const char *cmd, void *download_buffer, fastboot_fail("invalid MBR partition", response); return; } - if (write_mbr_partition(dev_desc, download_buffer)) { + if (write_mbr_sector(dev_desc, download_buffer)) { printf("%s: writing MBR partition failed\n", __func__); fastboot_fail("writing MBR partition failed", response); diff --git a/drivers/fpga/intel_sdm_mb.c b/drivers/fpga/intel_sdm_mb.c index 9a1dc2c0c83..f5fd9a14c26 100644 --- a/drivers/fpga/intel_sdm_mb.c +++ b/drivers/fpga/intel_sdm_mb.c @@ -8,11 +8,149 @@ #include <log.h> #include <watchdog.h> #include <asm/arch/mailbox_s10.h> +#include <asm/arch/smc_api.h> #include <linux/delay.h> +#include <linux/intel-smc.h> #define RECONFIG_STATUS_POLL_RESP_TIMEOUT_MS 60000 #define RECONFIG_STATUS_INTERVAL_DELAY_US 1000000 +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF) + +#define BITSTREAM_CHUNK_SIZE 0xFFFF0 +#define RECONFIG_STATUS_POLL_RETRY_MAX 100 + +/* + * Polling the FPGA configuration status. + * Return 0 for success, non-zero for error. + */ +static int reconfig_status_polling_resp(void) +{ + int ret; + unsigned long start = get_timer(0); + + while (1) { + ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_ISDONE, NULL, 0, + NULL, 0); + + if (!ret) + return 0; /* configuration success */ + + if (ret != INTEL_SIP_SMC_STATUS_BUSY) + return ret; + + if (get_timer(start) > RECONFIG_STATUS_POLL_RESP_TIMEOUT_MS) + return -ETIMEDOUT; /* time out */ + + puts("."); + udelay(RECONFIG_STATUS_INTERVAL_DELAY_US); + WATCHDOG_RESET(); + } + + return -ETIMEDOUT; +} + +static int send_bitstream(const void *rbf_data, size_t rbf_size) +{ + int i; + u64 res_buf[3]; + u64 args[2]; + u32 xfer_count = 0; + int ret, wr_ret = 0, retry = 0; + size_t buf_size = (rbf_size > BITSTREAM_CHUNK_SIZE) ? + BITSTREAM_CHUNK_SIZE : rbf_size; + + while (rbf_size || xfer_count) { + if (!wr_ret && rbf_size) { + args[0] = (u64)rbf_data; + args[1] = buf_size; + wr_ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_WRITE, + args, 2, NULL, 0); + + debug("wr_ret = %d, rbf_data = %p, buf_size = %08lx\n", + wr_ret, rbf_data, buf_size); + + if (wr_ret) + continue; + + rbf_size -= buf_size; + rbf_data += buf_size; + + if (buf_size >= rbf_size) + buf_size = rbf_size; + + xfer_count++; + puts("."); + } else { + ret = invoke_smc( + INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE, + NULL, 0, res_buf, ARRAY_SIZE(res_buf)); + if (!ret) { + for (i = 0; i < ARRAY_SIZE(res_buf); i++) { + if (!res_buf[i]) + break; + xfer_count--; + wr_ret = 0; + retry = 0; + } + } else if (ret != + INTEL_SIP_SMC_STATUS_BUSY) + return ret; + else if (!xfer_count) + return INTEL_SIP_SMC_STATUS_ERROR; + + if (++retry >= RECONFIG_STATUS_POLL_RETRY_MAX) + return -ETIMEDOUT; + + udelay(20000); + } + WATCHDOG_RESET(); + } + + return 0; +} + +/* + * This is the interface used by FPGA driver. + * Return 0 for success, non-zero for error. + */ +int intel_sdm_mb_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size) +{ + int ret; + u64 arg = 1; + + debug("Invoking FPGA_CONFIG_START...\n"); + + ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_START, &arg, 1, NULL, 0); + + if (ret) { + puts("Failure in RECONFIG mailbox command!\n"); + return ret; + } + + ret = send_bitstream(rbf_data, rbf_size); + if (ret) { + puts("Error sending bitstream!\n"); + return ret; + } + + /* Make sure we don't send MBOX_RECONFIG_STATUS too fast */ + udelay(RECONFIG_STATUS_INTERVAL_DELAY_US); + + debug("Polling with MBOX_RECONFIG_STATUS...\n"); + ret = reconfig_status_polling_resp(); + if (ret) { + puts("FPGA reconfiguration failed!"); + return ret; + } + + puts("FPGA reconfiguration OK!\n"); + + return ret; +} + +#else + static const struct mbox_cfgstat_state { int err_no; const char *error_name; @@ -286,3 +424,4 @@ int intel_sdm_mb_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size) return ret; } +#endif diff --git a/drivers/gpio/stm32_gpio.c b/drivers/gpio/stm32_gpio.c index 79d55e812db..7184db3c527 100644 --- a/drivers/gpio/stm32_gpio.c +++ b/drivers/gpio/stm32_gpio.c @@ -4,6 +4,8 @@ * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics. */ +#define LOG_CATEGORY UCLASS_GPIO + #include <common.h> #include <clk.h> #include <dm.h> @@ -331,7 +333,7 @@ static int gpio_stm32_probe(struct udevice *dev) dev_err(dev, "failed to enable clock\n"); return ret; } - debug("clock enabled for device %s\n", dev->name); + dev_dbg(dev, "clock enabled\n"); return 0; } diff --git a/drivers/hwspinlock/stm32_hwspinlock.c b/drivers/hwspinlock/stm32_hwspinlock.c index fdc1f6fd53e..46ed64655a8 100644 --- a/drivers/hwspinlock/stm32_hwspinlock.c +++ b/drivers/hwspinlock/stm32_hwspinlock.c @@ -3,6 +3,8 @@ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved */ +#define LOG_CATEGORY UCLASS_HWSPINLOCK + #include <common.h> #include <clk.h> #include <dm.h> diff --git a/drivers/i2c/stm32f7_i2c.c b/drivers/i2c/stm32f7_i2c.c index 6553bdc6106..7b04a09de0b 100644 --- a/drivers/i2c/stm32f7_i2c.c +++ b/drivers/i2c/stm32f7_i2c.c @@ -3,6 +3,8 @@ * (C) Copyright 2017 STMicroelectronics */ +#define LOG_CATEGORY UCLASS_I2C + #include <common.h> #include <clk.h> #include <dm.h> @@ -11,10 +13,10 @@ #include <regmap.h> #include <reset.h> #include <syscon.h> +#include <dm/device.h> +#include <dm/device_compat.h> #include <linux/bitops.h> #include <linux/delay.h> - -#include <dm/device.h> #include <linux/err.h> #include <linux/io.h> @@ -346,7 +348,7 @@ static int stm32_i2c_wait_flags(struct stm32_i2c_priv *i2c_priv, *status = readl(®s->isr); while (!(*status & flags)) { if (get_timer(time_start) > CONFIG_SYS_HZ) { - debug("%s: i2c timeout\n", __func__); + log_debug("i2c timeout\n"); return -ETIMEDOUT; } @@ -369,7 +371,7 @@ static int stm32_i2c_check_end_of_message(struct stm32_i2c_priv *i2c_priv) return ret; if (status & STM32_I2C_ISR_BERR) { - debug("%s: Bus error\n", __func__); + log_debug("Bus error\n"); /* Clear BERR flag */ setbits_le32(®s->icr, STM32_I2C_ICR_BERRCF); @@ -378,7 +380,7 @@ static int stm32_i2c_check_end_of_message(struct stm32_i2c_priv *i2c_priv) } if (status & STM32_I2C_ISR_ARLO) { - debug("%s: Arbitration lost\n", __func__); + log_debug("Arbitration lost\n"); /* Clear ARLO flag */ setbits_le32(®s->icr, STM32_I2C_ICR_ARLOCF); @@ -387,7 +389,7 @@ static int stm32_i2c_check_end_of_message(struct stm32_i2c_priv *i2c_priv) } if (status & STM32_I2C_ISR_NACKF) { - debug("%s: Receive NACK\n", __func__); + log_debug("Receive NACK\n"); /* Clear NACK flag */ setbits_le32(®s->icr, STM32_I2C_ICR_NACKCF); @@ -535,8 +537,8 @@ static int stm32_i2c_compute_solutions(struct stm32_i2c_setup *setup, if (sdadel_max < 0) sdadel_max = 0; - debug("%s: SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n", __func__, - sdadel_min, sdadel_max, scldel_min); + log_debug("SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n", + sdadel_min, sdadel_max, scldel_min); /* Compute possible values for PRESC, SCLDEL and SDADEL */ for (p = 0; p < STM32_PRESC_MAX; p++) { @@ -572,7 +574,7 @@ static int stm32_i2c_compute_solutions(struct stm32_i2c_setup *setup, } if (list_empty(solutions)) { - pr_err("%s: no Prescaler solution\n", __func__); + log_err("no Prescaler solution\n"); ret = -EPERM; } @@ -656,7 +658,7 @@ static int stm32_i2c_choose_solution(struct stm32_i2c_setup *setup, } if (!sol_found) { - pr_err("%s: no solution at all\n", __func__); + log_err("no solution at all\n"); ret = -EPERM; } @@ -686,23 +688,22 @@ static int stm32_i2c_compute_timing(struct stm32_i2c_priv *i2c_priv, specs = get_specs(setup->speed_freq); if (specs == ERR_PTR(-EINVAL)) { - pr_err("%s: speed out of bound {%d}\n", __func__, - setup->speed_freq); + log_err("speed out of bound {%d}\n", + setup->speed_freq); return -EINVAL; } if (setup->rise_time > specs->rise_max || setup->fall_time > specs->fall_max) { - pr_err("%s :timings out of bound Rise{%d>%d}/Fall{%d>%d}\n", - __func__, - setup->rise_time, specs->rise_max, - setup->fall_time, specs->fall_max); + log_err("timings out of bound Rise{%d>%d}/Fall{%d>%d}\n", + setup->rise_time, specs->rise_max, + setup->fall_time, specs->fall_max); return -EINVAL; } if (setup->dnf > STM32_I2C_DNF_MAX) { - pr_err("%s: DNF out of bound %d/%d\n", __func__, - setup->dnf, STM32_I2C_DNF_MAX); + log_err("DNF out of bound %d/%d\n", + setup->dnf, STM32_I2C_DNF_MAX); return -EINVAL; } @@ -715,10 +716,10 @@ static int stm32_i2c_compute_timing(struct stm32_i2c_priv *i2c_priv, if (ret) goto exit; - debug("%s: Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n", - __func__, output->presc, - output->scldel, output->sdadel, - output->scll, output->sclh); + log_debug("Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n", + output->presc, + output->scldel, output->sdadel, + output->scll, output->sclh); exit: /* Release list and memory */ @@ -751,20 +752,19 @@ static int stm32_i2c_setup_timing(struct stm32_i2c_priv *i2c_priv, setup->clock_src = clk_get_rate(&i2c_priv->clk); if (!setup->clock_src) { - pr_err("%s: clock rate is 0\n", __func__); + log_err("clock rate is 0\n"); return -EINVAL; } do { ret = stm32_i2c_compute_timing(i2c_priv, setup, timing); if (ret) { - debug("%s: failed to compute I2C timings.\n", - __func__); + log_debug("failed to compute I2C timings.\n"); if (setup->speed_freq > I2C_SPEED_STANDARD_RATE) { setup->speed_freq = get_lower_rate(setup->speed_freq); - debug("%s: downgrade I2C Speed Freq to (%i)\n", - __func__, setup->speed_freq); + log_debug("downgrade I2C Speed Freq to (%i)\n", + setup->speed_freq); } else { break; } @@ -772,16 +772,16 @@ static int stm32_i2c_setup_timing(struct stm32_i2c_priv *i2c_priv, } while (ret); if (ret) { - pr_err("%s: impossible to compute I2C timings.\n", __func__); + log_err("impossible to compute I2C timings.\n"); return ret; } - debug("%s: I2C Freq(%i), Clk Source(%i)\n", __func__, - setup->speed_freq, setup->clock_src); - debug("%s: I2C Rise(%i) and Fall(%i) Time\n", __func__, - setup->rise_time, setup->fall_time); - debug("%s: I2C Analog Filter(%s), DNF(%i)\n", __func__, - setup->analog_filter ? "On" : "Off", setup->dnf); + log_debug("I2C Freq(%i), Clk Source(%i)\n", + setup->speed_freq, setup->clock_src); + log_debug("I2C Rise(%i) and Fall(%i) Time\n", + setup->rise_time, setup->fall_time); + log_debug("I2C Analog Filter(%s), DNF(%i)\n", + setup->analog_filter ? "On" : "Off", setup->dnf); i2c_priv->speed = setup->speed_freq; @@ -848,12 +848,12 @@ static int stm32_i2c_hw_config(struct stm32_i2c_priv *i2c_priv) return 0; } -static int stm32_i2c_set_bus_speed(struct udevice *bus, unsigned int speed) +static int stm32_i2c_set_bus_speed(struct udevice *dev, unsigned int speed) { - struct stm32_i2c_priv *i2c_priv = dev_get_priv(bus); + struct stm32_i2c_priv *i2c_priv = dev_get_priv(dev); if (speed > I2C_SPEED_FAST_PLUS_RATE) { - debug("%s: Speed %d not supported\n", __func__, speed); + dev_dbg(dev, "Speed %d not supported\n", speed); return -EINVAL; } diff --git a/drivers/mailbox/stm32-ipcc.c b/drivers/mailbox/stm32-ipcc.c index 093b570414f..69c86e059f5 100644 --- a/drivers/mailbox/stm32-ipcc.c +++ b/drivers/mailbox/stm32-ipcc.c @@ -3,6 +3,8 @@ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved */ +#define LOG_CATEGORY UCLASS_MAILBOX + #include <common.h> #include <clk.h> #include <dm.h> @@ -44,11 +46,11 @@ static int stm32_ipcc_request(struct mbox_chan *chan) { struct stm32_ipcc *ipcc = dev_get_priv(chan->dev); - debug("%s(chan=%p)\n", __func__, chan); + dev_dbg(chan->dev, "chan=%p\n", chan); if (chan->id >= ipcc->n_chans) { - debug("%s failed to request channel: %ld\n", - __func__, chan->id); + dev_dbg(chan->dev, "failed to request channel: %ld\n", + chan->id); return -EINVAL; } @@ -57,7 +59,7 @@ static int stm32_ipcc_request(struct mbox_chan *chan) static int stm32_ipcc_free(struct mbox_chan *chan) { - debug("%s(chan=%p)\n", __func__, chan); + dev_dbg(chan->dev, "chan=%p\n", chan); return 0; } @@ -66,7 +68,7 @@ static int stm32_ipcc_send(struct mbox_chan *chan, const void *data) { struct stm32_ipcc *ipcc = dev_get_priv(chan->dev); - debug("%s(chan=%p, data=%p)\n", __func__, chan, data); + dev_dbg(chan->dev, "chan=%p, data=%p\n", chan, data); if (readl(ipcc->reg_proc + IPCC_XTOYSR) & BIT(chan->id)) return -EBUSY; @@ -83,7 +85,7 @@ static int stm32_ipcc_recv(struct mbox_chan *chan, void *data) u32 val; int proc_offset; - debug("%s(chan=%p, data=%p)\n", __func__, chan, data); + dev_dbg(chan->dev, "chan=%p, data=%p\n", chan, data); /* read 'channel occupied' status from other proc */ proc_offset = ipcc->proc_id ? -IPCC_PROC_OFFST : IPCC_PROC_OFFST; @@ -104,7 +106,7 @@ static int stm32_ipcc_probe(struct udevice *dev) struct clk clk; int ret; - debug("%s(dev=%p)\n", __func__, dev); + dev_dbg(dev, "\n"); addr = dev_read_addr(dev); if (addr == FDT_ADDR_T_NONE) diff --git a/drivers/memory/stm32-fmc2-ebi.c b/drivers/memory/stm32-fmc2-ebi.c index f3f48f8b38d..212bb4f5dc0 100644 --- a/drivers/memory/stm32-fmc2-ebi.c +++ b/drivers/memory/stm32-fmc2-ebi.c @@ -3,10 +3,13 @@ * Copyright (C) STMicroelectronics 2020 */ +#define LOG_CATEGORY UCLASS_NOP + #include <common.h> #include <clk.h> #include <dm.h> #include <reset.h> +#include <dm/device_compat.h> #include <linux/bitfield.h> #include <linux/err.h> #include <linux/iopoll.h> @@ -860,7 +863,7 @@ static int stm32_fmc2_ebi_parse_prop(struct stm32_fmc2_ebi *ebi, u32 setup = 0; if (!prop->set) { - pr_err("property %s is not well defined\n", prop->name); + log_err("property %s is not well defined\n", prop->name); return -EINVAL; } @@ -873,8 +876,8 @@ static int stm32_fmc2_ebi_parse_prop(struct stm32_fmc2_ebi *ebi, bprop = ofnode_read_bool(node, prop->name); if (prop->mprop && !bprop) { - pr_err("mandatory property %s not defined in the device tree\n", - prop->name); + log_err("mandatory property %s not defined in the device tree\n", + prop->name); return -EINVAL; } @@ -886,8 +889,8 @@ static int stm32_fmc2_ebi_parse_prop(struct stm32_fmc2_ebi *ebi, ret = ofnode_read_u32(node, prop->name, &val); if (prop->mprop && ret) { - pr_err("mandatory property %s not defined in the device tree\n", - prop->name); + log_err("mandatory property %s not defined in the device tree\n", + prop->name); return ret; } @@ -949,8 +952,8 @@ static int stm32_fmc2_ebi_setup_cs(struct stm32_fmc2_ebi *ebi, ret = stm32_fmc2_ebi_parse_prop(ebi, node, p, cs); if (ret) { - pr_err("property %s could not be set: %d\n", - p->name, ret); + log_err("property %s could not be set: %d\n", + p->name, ret); return ret; } } @@ -971,25 +974,24 @@ static int stm32_fmc2_ebi_parse_dt(struct udevice *dev, dev_for_each_subnode(child, dev) { ret = ofnode_read_u32(child, "reg", &bank); if (ret) { - pr_err("could not retrieve reg property: %d\n", ret); + dev_err(dev, "could not retrieve reg property: %d\n", ret); return ret; } if (bank >= FMC2_MAX_BANKS) { - pr_err("invalid reg value: %d\n", bank); + dev_err(dev, "invalid reg value: %d\n", bank); return -EINVAL; } if (ebi->bank_assigned & BIT(bank)) { - pr_err("bank already assigned: %d\n", bank); + dev_err(dev, "bank already assigned: %d\n", bank); return -EINVAL; } if (bank < FMC2_MAX_EBI_CE) { ret = stm32_fmc2_ebi_setup_cs(ebi, child, bank); if (ret) { - pr_err("setup chip select %d failed: %d\n", - bank, ret); + dev_err(dev, "setup chip select %d failed: %d\n", bank, ret); return ret; } } @@ -999,12 +1001,12 @@ static int stm32_fmc2_ebi_parse_dt(struct udevice *dev, } if (!child_found) { - pr_warn("no subnodes found, disable the driver.\n"); + dev_warn(dev, "no subnodes found, disable the driver.\n"); return -ENODEV; } if (stm32_fmc2_ebi_nwait_used_by_ctrls(ebi)) { - pr_err("NWAIT signal connected to EBI and NAND controllers\n"); + dev_err(dev, "NWAIT signal connected to EBI and NAND controllers\n"); return -EINVAL; } diff --git a/drivers/misc/stm32_rcc.c b/drivers/misc/stm32_rcc.c index 86275454be0..f14d6e26d9c 100644 --- a/drivers/misc/stm32_rcc.c +++ b/drivers/misc/stm32_rcc.c @@ -4,6 +4,8 @@ * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics. */ +#define LOG_CATEGORY UCLASS_NOP + #include <common.h> #include <dm.h> #include <log.h> @@ -45,14 +47,14 @@ static int stm32_rcc_bind(struct udevice *dev) (struct stm32_rcc_clk *)dev_get_driver_data(dev); int ret; - debug("%s(dev=%p)\n", __func__, dev); + dev_dbg(dev, "RCC bind\n"); drv = lists_driver_lookup_name(rcc_clk->drv_name); if (!drv) { - debug("Cannot find driver '%s'\n", rcc_clk->drv_name); + dev_err(dev, "Cannot find driver '%s'\n", rcc_clk->drv_name); return -ENOENT; } - ret = device_bind_with_driver_data(dev, drv, rcc_clk->drv_name, + ret = device_bind_with_driver_data(dev, drv, dev->name, rcc_clk->soc, dev_ofnode(dev), &child); @@ -65,7 +67,7 @@ static int stm32_rcc_bind(struct udevice *dev) return -ENOENT; } - return device_bind_with_driver_data(dev, drv, "stm32_rcc_reset", + return device_bind_with_driver_data(dev, drv, dev->name, rcc_clk->soc, dev_ofnode(dev), &child); } diff --git a/drivers/mmc/ca_dw_mmc.c b/drivers/mmc/ca_dw_mmc.c index fad2ff5aaf6..2b79356a20e 100644 --- a/drivers/mmc/ca_dw_mmc.c +++ b/drivers/mmc/ca_dw_mmc.c @@ -40,7 +40,7 @@ struct ca_dwmmc_priv_data { u8 ds; }; -static void ca_dwmci_clksel(struct dwmci_host *host) +static int ca_dwmci_clksel(struct dwmci_host *host) { struct ca_dwmmc_priv_data *priv = host->priv; u32 val = readl(priv->sd_dll_reg); @@ -52,6 +52,8 @@ static void ca_dwmci_clksel(struct dwmci_host *host) val |= SD_CLK_SEL_100MHZ; writel(val, priv->sd_dll_reg); + + return 0; } static void ca_dwmci_board_init(struct dwmci_host *host) diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c index 7702f4be3f8..7c8a312fa71 100644 --- a/drivers/mmc/dw_mmc.c +++ b/drivers/mmc/dw_mmc.c @@ -496,8 +496,13 @@ static int dwmci_set_ios(struct mmc *mmc) dwmci_writel(host, DWMCI_UHS_REG, regs); - if (host->clksel) - host->clksel(host); + if (host->clksel) { + int ret; + + ret = host->clksel(host); + if (ret) + return ret; + } #if CONFIG_IS_ENABLED(DM_REGULATOR) if (mmc->vqmmc_supply) { diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c index edb5a52c960..b4ff1c3fb4b 100644 --- a/drivers/mmc/exynos_dw_mmc.c +++ b/drivers/mmc/exynos_dw_mmc.c @@ -44,7 +44,7 @@ struct dwmci_exynos_priv_data { * Function used as callback function to initialise the * CLKSEL register for every mmc channel. */ -static void exynos_dwmci_clksel(struct dwmci_host *host) +static int exynos_dwmci_clksel(struct dwmci_host *host) { #ifdef CONFIG_DM_MMC struct dwmci_exynos_priv_data *priv = @@ -53,6 +53,8 @@ static void exynos_dwmci_clksel(struct dwmci_host *host) struct dwmci_exynos_priv_data *priv = host->priv; #endif dwmci_writel(host, DWMCI_CLKSEL, priv->sdr_timing); + + return 0; } unsigned int exynos_dwmci_get_clk(struct dwmci_host *host, uint freq) diff --git a/drivers/mmc/fsl_esdhc_spl.c b/drivers/mmc/fsl_esdhc_spl.c index afe55fad9de..bee76572ac6 100644 --- a/drivers/mmc/fsl_esdhc_spl.c +++ b/drivers/mmc/fsl_esdhc_spl.c @@ -91,20 +91,17 @@ void __noreturn mmc_boot(void) CONFIG_CFG_DATA_SECTOR, 1, tmp_buf); if (err != 1) { puts("spl: mmc read failed!!\n"); - free(tmp_buf); hang(); } val = *(tmp_buf + MBRDBR_BOOT_SIG_55); if (0x55 != val) { puts("spl: mmc signature is not valid!!\n"); - free(tmp_buf); hang(); } val = *(tmp_buf + MBRDBR_BOOT_SIG_AA); if (0xAA != val) { puts("spl: mmc signature is not valid!!\n"); - free(tmp_buf); hang(); } diff --git a/drivers/mmc/nexell_dw_mmc.c b/drivers/mmc/nexell_dw_mmc.c index 753c89d278c..2723e4887cf 100644 --- a/drivers/mmc/nexell_dw_mmc.c +++ b/drivers/mmc/nexell_dw_mmc.c @@ -51,7 +51,7 @@ struct nexell_dwmmc_priv { struct clk *clk_get(const char *id); -static void nx_dw_mmc_clksel(struct dwmci_host *host) +static int nx_dw_mmc_clksel(struct dwmci_host *host) { /* host->priv is pointer to "struct udevice" */ struct nexell_dwmmc_priv *priv = dev_get_priv(host->priv); @@ -65,6 +65,8 @@ static void nx_dw_mmc_clksel(struct dwmci_host *host) DWMCI_SET_DRV_CLK(DWMCI_SHIFT_0) | DWMCI_SET_DIV_RATIO(3); dwmci_writel(host, DWMCI_CLKSEL, val); + + return 0; } static void nx_dw_mmc_reset(int ch) diff --git a/drivers/mmc/pci_mmc.c b/drivers/mmc/pci_mmc.c index c71c495d581..b26eb034d07 100644 --- a/drivers/mmc/pci_mmc.c +++ b/drivers/mmc/pci_mmc.c @@ -52,9 +52,11 @@ static int pci_mmc_probe(struct udevice *dev) static int pci_mmc_of_to_plat(struct udevice *dev) { - struct pci_mmc_priv *priv = dev_get_priv(dev); + if (CONFIG_IS_ENABLED(DM_GPIO)) { + struct pci_mmc_priv *priv = dev_get_priv(dev); - gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN); + gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN); + } return 0; } diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c index dc008c5e2f0..aa0d3a22221 100644 --- a/drivers/mmc/socfpga_dw_mmc.c +++ b/drivers/mmc/socfpga_dw_mmc.c @@ -6,6 +6,7 @@ #include <common.h> #include <log.h> #include <asm/arch/clock_manager.h> +#include <asm/arch/secure_reg_helper.h> #include <asm/arch/system_manager.h> #include <clk.h> #include <dm.h> @@ -13,6 +14,7 @@ #include <errno.h> #include <fdtdec.h> #include <dm/device_compat.h> +#include <linux/intel-smc.h> #include <linux/libfdt.h> #include <linux/err.h> #include <malloc.h> @@ -46,7 +48,7 @@ static void socfpga_dwmci_reset(struct udevice *dev) reset_deassert_bulk(&reset_bulk); } -static void socfpga_dwmci_clksel(struct dwmci_host *host) +static int socfpga_dwmci_clksel(struct dwmci_host *host) { struct dwmci_socfpga_priv_data *priv = host->priv; u32 sdmmc_mask = ((priv->smplsel & 0x7) << SYSMGR_SDMMC_SMPLSEL_SHIFT) | @@ -58,14 +60,28 @@ static void socfpga_dwmci_clksel(struct dwmci_host *host) debug("%s: drvsel %d smplsel %d\n", __func__, priv->drvsel, priv->smplsel); + +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF) + int ret; + + ret = socfpga_secure_reg_write32(SOCFPGA_SECURE_REG_SYSMGR_SOC64_SDMMC, + sdmmc_mask); + if (ret) { + printf("DWMMC: Failed to set clksel via SMC call"); + return ret; + } +#else writel(sdmmc_mask, socfpga_get_sysmgr_addr() + SYSMGR_SDMMC); debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__, readl(socfpga_get_sysmgr_addr() + SYSMGR_SDMMC)); +#endif /* Enable SDMMC clock */ setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN, CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK); + + return 0; } static int socfpga_dwmmc_get_clk_rate(struct udevice *dev) diff --git a/drivers/mmc/stm32_sdmmc2.c b/drivers/mmc/stm32_sdmmc2.c index 3246f6b5e03..a3cdf7bcd9f 100644 --- a/drivers/mmc/stm32_sdmmc2.c +++ b/drivers/mmc/stm32_sdmmc2.c @@ -4,6 +4,8 @@ * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics. */ +#define LOG_CATEGORY UCLASS_MMC + #include <common.h> #include <clk.h> #include <cpu_func.h> @@ -13,6 +15,7 @@ #include <malloc.h> #include <asm/bitops.h> #include <asm/cache.h> +#include <dm/device_compat.h> #include <linux/bitops.h> #include <linux/delay.h> #include <linux/libfdt.h> @@ -200,10 +203,11 @@ struct stm32_sdmmc2_ctx { #define SDMMC_CMD_TIMEOUT 0xFFFFFFFF #define SDMMC_BUSYD0END_TIMEOUT_US 2000000 -static void stm32_sdmmc2_start_data(struct stm32_sdmmc2_priv *priv, +static void stm32_sdmmc2_start_data(struct udevice *dev, struct mmc_data *data, struct stm32_sdmmc2_ctx *ctx) { + struct stm32_sdmmc2_priv *priv = dev_get_priv(dev); u32 data_ctrl, idmabase0; /* Configure the SDMMC DPSM (Data Path State Machine) */ @@ -241,10 +245,11 @@ static void stm32_sdmmc2_start_data(struct stm32_sdmmc2_priv *priv, writel(SDMMC_IDMACTRL_IDMAEN, priv->base + SDMMC_IDMACTRL); } -static void stm32_sdmmc2_start_cmd(struct stm32_sdmmc2_priv *priv, +static void stm32_sdmmc2_start_cmd(struct udevice *dev, struct mmc_cmd *cmd, u32 cmd_param, struct stm32_sdmmc2_ctx *ctx) { + struct stm32_sdmmc2_priv *priv = dev_get_priv(dev); u32 timeout = 0; if (readl(priv->base + SDMMC_CMD) & SDMMC_CMD_CPSMEN) @@ -290,10 +295,11 @@ static void stm32_sdmmc2_start_cmd(struct stm32_sdmmc2_priv *priv, writel(cmd_param, priv->base + SDMMC_CMD); } -static int stm32_sdmmc2_end_cmd(struct stm32_sdmmc2_priv *priv, +static int stm32_sdmmc2_end_cmd(struct udevice *dev, struct mmc_cmd *cmd, struct stm32_sdmmc2_ctx *ctx) { + struct stm32_sdmmc2_priv *priv = dev_get_priv(dev); u32 mask = SDMMC_STA_CTIMEOUT; u32 status; int ret; @@ -311,22 +317,22 @@ static int stm32_sdmmc2_end_cmd(struct stm32_sdmmc2_priv *priv, 10000); if (ret < 0) { - debug("%s: timeout reading SDMMC_STA register\n", __func__); + dev_dbg(dev, "timeout reading SDMMC_STA register\n"); ctx->dpsm_abort = true; return ret; } /* Check status */ if (status & SDMMC_STA_CTIMEOUT) { - debug("%s: error SDMMC_STA_CTIMEOUT (0x%x) for cmd %d\n", - __func__, status, cmd->cmdidx); + dev_dbg(dev, "error SDMMC_STA_CTIMEOUT (0x%x) for cmd %d\n", + status, cmd->cmdidx); ctx->dpsm_abort = true; return -ETIMEDOUT; } if (status & SDMMC_STA_CCRCFAIL && cmd->resp_type & MMC_RSP_CRC) { - debug("%s: error SDMMC_STA_CCRCFAIL (0x%x) for cmd %d\n", - __func__, status, cmd->cmdidx); + dev_dbg(dev, "error SDMMC_STA_CCRCFAIL (0x%x) for cmd %d\n", + status, cmd->cmdidx); ctx->dpsm_abort = true; return -EILSEQ; } @@ -350,15 +356,15 @@ static int stm32_sdmmc2_end_cmd(struct stm32_sdmmc2_priv *priv, SDMMC_BUSYD0END_TIMEOUT_US); if (ret < 0) { - debug("%s: timeout reading SDMMC_STA\n", - __func__); + dev_dbg(dev, "timeout reading SDMMC_STA\n"); ctx->dpsm_abort = true; return ret; } if (status & SDMMC_STA_DTIMEOUT) { - debug("%s: error SDMMC_STA_DTIMEOUT (0x%x)\n", - __func__, status); + dev_dbg(dev, + "error SDMMC_STA_DTIMEOUT (0x%x)\n", + status); ctx->dpsm_abort = true; return -ETIMEDOUT; } @@ -368,11 +374,12 @@ static int stm32_sdmmc2_end_cmd(struct stm32_sdmmc2_priv *priv, return 0; } -static int stm32_sdmmc2_end_data(struct stm32_sdmmc2_priv *priv, +static int stm32_sdmmc2_end_data(struct udevice *dev, struct mmc_cmd *cmd, struct mmc_data *data, struct stm32_sdmmc2_ctx *ctx) { + struct stm32_sdmmc2_priv *priv = dev_get_priv(dev); u32 mask = SDMMC_STA_DCRCFAIL | SDMMC_STA_DTIMEOUT | SDMMC_STA_IDMATE | SDMMC_STA_DATAEND; u32 status; @@ -394,37 +401,37 @@ static int stm32_sdmmc2_end_data(struct stm32_sdmmc2_priv *priv, invalidate_dcache_range(ctx->cache_start, ctx->cache_end); if (status & SDMMC_STA_DCRCFAIL) { - debug("%s: error SDMMC_STA_DCRCFAIL (0x%x) for cmd %d\n", - __func__, status, cmd->cmdidx); + dev_dbg(dev, "error SDMMC_STA_DCRCFAIL (0x%x) for cmd %d\n", + status, cmd->cmdidx); if (readl(priv->base + SDMMC_DCOUNT)) ctx->dpsm_abort = true; return -EILSEQ; } if (status & SDMMC_STA_DTIMEOUT) { - debug("%s: error SDMMC_STA_DTIMEOUT (0x%x) for cmd %d\n", - __func__, status, cmd->cmdidx); + dev_dbg(dev, "error SDMMC_STA_DTIMEOUT (0x%x) for cmd %d\n", + status, cmd->cmdidx); ctx->dpsm_abort = true; return -ETIMEDOUT; } if (status & SDMMC_STA_TXUNDERR) { - debug("%s: error SDMMC_STA_TXUNDERR (0x%x) for cmd %d\n", - __func__, status, cmd->cmdidx); + dev_dbg(dev, "error SDMMC_STA_TXUNDERR (0x%x) for cmd %d\n", + status, cmd->cmdidx); ctx->dpsm_abort = true; return -EIO; } if (status & SDMMC_STA_RXOVERR) { - debug("%s: error SDMMC_STA_RXOVERR (0x%x) for cmd %d\n", - __func__, status, cmd->cmdidx); + dev_dbg(dev, "error SDMMC_STA_RXOVERR (0x%x) for cmd %d\n", + status, cmd->cmdidx); ctx->dpsm_abort = true; return -EIO; } if (status & SDMMC_STA_IDMATE) { - debug("%s: error SDMMC_STA_IDMATE (0x%x) for cmd %d\n", - __func__, status, cmd->cmdidx); + dev_dbg(dev, "error SDMMC_STA_IDMATE (0x%x) for cmd %d\n", + status, cmd->cmdidx); ctx->dpsm_abort = true; return -EIO; } @@ -448,19 +455,18 @@ retry_cmd: if (data) { ctx.data_length = data->blocks * data->blocksize; - stm32_sdmmc2_start_data(priv, data, &ctx); + stm32_sdmmc2_start_data(dev, data, &ctx); } - stm32_sdmmc2_start_cmd(priv, cmd, cmdat, &ctx); + stm32_sdmmc2_start_cmd(dev, cmd, cmdat, &ctx); - debug("%s: send cmd %d data: 0x%x @ 0x%x\n", - __func__, cmd->cmdidx, - data ? ctx.data_length : 0, (unsigned int)data); + dev_dbg(dev, "send cmd %d data: 0x%x @ 0x%x\n", + cmd->cmdidx, data ? ctx.data_length : 0, (unsigned int)data); - ret = stm32_sdmmc2_end_cmd(priv, cmd, &ctx); + ret = stm32_sdmmc2_end_cmd(dev, cmd, &ctx); if (data && !ret) - ret = stm32_sdmmc2_end_data(priv, cmd, data, &ctx); + ret = stm32_sdmmc2_end_data(dev, cmd, data, &ctx); /* Clear flags */ writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR); @@ -478,26 +484,24 @@ retry_cmd: stop_cmd.cmdarg = 0; stop_cmd.resp_type = MMC_RSP_R1b; - debug("%s: send STOP command to abort dpsm treatments\n", - __func__); + dev_dbg(dev, "send STOP command to abort dpsm treatments\n"); ctx.data_length = 0; - stm32_sdmmc2_start_cmd(priv, &stop_cmd, + stm32_sdmmc2_start_cmd(dev, &stop_cmd, SDMMC_CMD_CMDSTOP, &ctx); - stm32_sdmmc2_end_cmd(priv, &stop_cmd, &ctx); + stm32_sdmmc2_end_cmd(dev, &stop_cmd, &ctx); writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR); } if ((ret != -ETIMEDOUT) && (ret != 0) && retry) { - printf("%s: cmd %d failed, retrying ...\n", - __func__, cmd->cmdidx); + dev_err(dev, "cmd %d failed, retrying ...\n", cmd->cmdidx); retry--; goto retry_cmd; } - debug("%s: end for CMD %d, ret = %d\n", __func__, cmd->cmdidx, ret); + dev_dbg(dev, "end for CMD %d, ret = %d\n", cmd->cmdidx, ret); return ret; } @@ -579,8 +583,8 @@ static int stm32_sdmmc2_set_ios(struct udevice *dev) u32 sys_clock = clk_get_rate(&priv->clk); u32 clk = 0; - debug("%s: bus_with = %d, clock = %d\n", __func__, - mmc->bus_width, mmc->clock); + dev_dbg(dev, "bus_with = %d, clock = %d\n", + mmc->bus_width, mmc->clock); if (mmc->clk_disable) stm32_sdmmc2_pwrcycle(priv); @@ -616,7 +620,7 @@ static int stm32_sdmmc2_getcd(struct udevice *dev) { struct stm32_sdmmc2_priv *priv = dev_get_priv(dev); - debug("stm32_sdmmc2_getcd called\n"); + dev_dbg(dev, "%s called\n", __func__); if (dm_gpio_is_valid(&priv->cd_gpio)) return dm_gpio_get_value(&priv->cd_gpio); diff --git a/drivers/mmc/xenon_sdhci.c b/drivers/mmc/xenon_sdhci.c index b8e833e6a3c..14fec4b8e78 100644 --- a/drivers/mmc/xenon_sdhci.c +++ b/drivers/mmc/xenon_sdhci.c @@ -104,18 +104,6 @@ DECLARE_GLOBAL_DATA_PTR; /* Hyperion only have one slot 0 */ #define XENON_MMC_SLOT_ID_HYPERION 0 -#define MMC_TIMING_LEGACY 0 -#define MMC_TIMING_MMC_HS 1 -#define MMC_TIMING_SD_HS 2 -#define MMC_TIMING_UHS_SDR12 3 -#define MMC_TIMING_UHS_SDR25 4 -#define MMC_TIMING_UHS_SDR50 5 -#define MMC_TIMING_UHS_SDR104 6 -#define MMC_TIMING_UHS_DDR50 7 -#define MMC_TIMING_MMC_DDR52 8 -#define MMC_TIMING_MMC_HS200 9 -#define MMC_TIMING_MMC_HS400 10 - #define XENON_MMC_MAX_CLK 400000000 #define XENON_MMC_3V3_UV 3300000 #define XENON_MMC_1V8_UV 1800000 diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile index 318788c5e2f..6d77ebfaa53 100644 --- a/drivers/mtd/Makefile +++ b/drivers/mtd/Makefile @@ -11,7 +11,6 @@ mtd-$(CONFIG_ALTERA_QSPI) += altera_qspi.o mtd-$(CONFIG_FLASH_CFI_DRIVER) += cfi_flash.o mtd-$(CONFIG_FLASH_CFI_MTD) += cfi_mtd.o mtd-$(CONFIG_FLASH_CFI_LEGACY) += jedec_flash.o -mtd-$(CONFIG_MW_EEPROM) += mw_eeprom.o mtd-$(CONFIG_FLASH_PIC32) += pic32_flash.o mtd-$(CONFIG_ST_SMI) += st_smi.o mtd-$(CONFIG_STM32_FLASH) += stm32_flash.o diff --git a/drivers/mtd/mtdcore.c b/drivers/mtd/mtdcore.c index 1a4dec34d93..0d1f94c6cba 100644 --- a/drivers/mtd/mtdcore.c +++ b/drivers/mtd/mtdcore.c @@ -9,8 +9,6 @@ */ #ifndef __UBOOT__ -#include <log.h> -#include <dm/devres.h> #include <linux/module.h> #include <linux/kernel.h> #include <linux/ptrace.h> diff --git a/drivers/mtd/mw_eeprom.c b/drivers/mtd/mw_eeprom.c deleted file mode 100644 index 9837733beee..00000000000 --- a/drivers/mtd/mw_eeprom.c +++ /dev/null @@ -1,238 +0,0 @@ -/* Three-wire (MicroWire) serial eeprom driver (for 93C46 and compatibles) */ - -#include <common.h> -#include <eeprom.h> -#include <asm/ic/ssi.h> -#include <linux/delay.h> - -/* - * Serial EEPROM opcodes, including start bit - */ -#define EEP_OPC_ERASE 0x7 /* 3-bit opcode */ -#define EEP_OPC_WRITE 0x5 /* 3-bit opcode */ -#define EEP_OPC_READ 0x6 /* 3-bit opcode */ - -#define EEP_OPC_ERASE_ALL 0x12 /* 5-bit opcode */ -#define EEP_OPC_ERASE_EN 0x13 /* 5-bit opcode */ -#define EEP_OPC_WRITE_ALL 0x11 /* 5-bit opcode */ -#define EEP_OPC_ERASE_DIS 0x10 /* 5-bit opcode */ - -static int addrlen; - -static void mw_eeprom_select(int dev) -{ - ssi_set_interface(2048, 0, 0, 0); - ssi_chip_select(0); - udelay(1); - ssi_chip_select(dev); - udelay(1); -} - -static int mw_eeprom_size(int dev) -{ - int x; - u16 res; - - mw_eeprom_select(dev); - ssi_tx_byte(EEP_OPC_READ); - - res = ssi_txrx_byte(0) << 8; - res |= ssi_rx_byte(); - for (x = 0; x < 16; x++) { - if (! (res & 0x8000)) { - break; - } - res <<= 1; - } - ssi_chip_select(0); - - return x; -} - -int mw_eeprom_erase_enable(int dev) -{ - mw_eeprom_select(dev); - ssi_tx_byte(EEP_OPC_ERASE_EN); - ssi_tx_byte(0); - udelay(1); - ssi_chip_select(0); - - return 0; -} - -int mw_eeprom_erase_disable(int dev) -{ - mw_eeprom_select(dev); - ssi_tx_byte(EEP_OPC_ERASE_DIS); - ssi_tx_byte(0); - udelay(1); - ssi_chip_select(0); - - return 0; -} - - -u32 mw_eeprom_read_word(int dev, int addr) -{ - u16 rcv; - u16 res; - int bits; - - mw_eeprom_select(dev); - ssi_tx_byte((EEP_OPC_READ << 5) | ((addr >> (addrlen - 5)) & 0x1f)); - rcv = ssi_txrx_byte(addr << (13 - addrlen)); - res = rcv << (16 - addrlen); - bits = 4 + addrlen; - - while (bits>0) { - rcv = ssi_rx_byte(); - if (bits > 7) { - res |= rcv << (bits - 8); - } else { - res |= rcv >> (8 - bits); - } - bits -= 8; - } - - ssi_chip_select(0); - - return res; -} - -int mw_eeprom_write_word(int dev, int addr, u16 data) -{ - u8 byte1=0; - u8 byte2=0; - - mw_eeprom_erase_enable(dev); - mw_eeprom_select(dev); - - switch (addrlen) { - case 6: - byte1 = EEP_OPC_WRITE >> 2; - byte2 = (EEP_OPC_WRITE << 6)&0xc0; - byte2 |= addr; - break; - case 7: - byte1 = EEP_OPC_WRITE >> 1; - byte2 = (EEP_OPC_WRITE << 7)&0x80; - byte2 |= addr; - break; - case 8: - byte1 = EEP_OPC_WRITE; - byte2 = addr; - break; - case 9: - byte1 = EEP_OPC_WRITE << 1; - byte1 |= addr >> 8; - byte2 = addr & 0xff; - break; - case 10: - byte1 = EEP_OPC_WRITE << 2; - byte1 |= addr >> 8; - byte2 = addr & 0xff; - break; - default: - printf("Unsupported number of address bits: %d\n", addrlen); - return -1; - - } - - ssi_tx_byte(byte1); - ssi_tx_byte(byte2); - ssi_tx_byte(data >> 8); - ssi_tx_byte(data & 0xff); - ssi_chip_select(0); - udelay(10000); /* Worst case */ - mw_eeprom_erase_disable(dev); - - return 0; -} - - -int mw_eeprom_write(int dev, int addr, u8 *buffer, int len) -{ - int done; - - done = 0; - if (addr & 1) { - u16 temp = mw_eeprom_read_word(dev, addr >> 1); - temp &= 0xff00; - temp |= buffer[0]; - - mw_eeprom_write_word(dev, addr >> 1, temp); - len--; - addr++; - buffer++; - done++; - } - - while (len <= 2) { - mw_eeprom_write_word(dev, addr >> 1, *(u16*)buffer); - len-=2; - addr+=2; - buffer+=2; - done+=2; - } - - if (len) { - u16 temp = mw_eeprom_read_word(dev, addr >> 1); - temp &= 0x00ff; - temp |= buffer[0] << 8; - - mw_eeprom_write_word(dev, addr >> 1, temp); - len--; - addr++; - buffer++; - done++; - } - - return done; -} - - -int mw_eeprom_read(int dev, int addr, u8 *buffer, int len) -{ - int done; - - done = 0; - if (addr & 1) { - u16 temp = mw_eeprom_read_word(dev, addr >> 1); - buffer[0]= temp & 0xff; - - len--; - addr++; - buffer++; - done++; - } - - while (len <= 2) { - *(u16*)buffer = mw_eeprom_read_word(dev, addr >> 1); - len-=2; - addr+=2; - buffer+=2; - done+=2; - } - - if (len) { - u16 temp = mw_eeprom_read_word(dev, addr >> 1); - buffer[0] = temp >> 8; - - len--; - addr++; - buffer++; - done++; - } - - return done; -} - -int mw_eeprom_probe(int dev) -{ - addrlen = mw_eeprom_size(dev); - - if (addrlen < 6 || addrlen > 10) { - return -1; - } - return 0; -} diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index 3cf3b14f05b..ed151ee0a5c 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -321,6 +321,18 @@ config NAND_STM32_FMC2 The controller supports a maximum 8k page size and supports a maximum 8-bit correction error per sector of 512 bytes. +config CORTINA_NAND + bool "Support for NAND controller on Cortina-Access SoCs" + depends on CORTINA_PLATFORM + select SYS_NAND_SELF_INIT + select DM_MTD + imply CMD_NAND + help + Enables support for NAND Flash chips on Coartina-Access SoCs platform + This controller is found on Presidio/Venus SoCs. + The controller supports a maximum 8k page size and supports + a maximum 40-bit error correction per sector of 1024 bytes. + comment "Generic NAND options" config SYS_NAND_BLOCK_SIZE diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile index 24c51b6924a..f3f0e15a157 100644 --- a/drivers/mtd/nand/raw/Makefile +++ b/drivers/mtd/nand/raw/Makefile @@ -69,6 +69,7 @@ obj-$(CONFIG_NAND_PLAT) += nand_plat.o obj-$(CONFIG_NAND_SUNXI) += sunxi_nand.o obj-$(CONFIG_NAND_ZYNQ) += zynq_nand.o obj-$(CONFIG_NAND_STM32_FMC2) += stm32_fmc2_nand.o +obj-$(CONFIG_CORTINA_NAND) += cortina_nand.o else # minimal SPL drivers diff --git a/drivers/mtd/nand/raw/cortina_nand.c b/drivers/mtd/nand/raw/cortina_nand.c new file mode 100644 index 00000000000..12bd1ded83f --- /dev/null +++ b/drivers/mtd/nand/raw/cortina_nand.c @@ -0,0 +1,1390 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2020, Cortina Access Inc.. + */ + +#include <common.h> +#include <linux/delay.h> +#include <linux/bitops.h> +#include <linux/sizes.h> +#include <log.h> +#include <asm/io.h> +#include <memalign.h> +#include <nand.h> +#include <dm/device_compat.h> +#include <linux/bug.h> +#include <linux/delay.h> +#include <linux/iopoll.h> +#include <linux/errno.h> +#include <asm/gpio.h> +#include <fdtdec.h> +#include <bouncebuf.h> +#include <dm.h> +#include "cortina_nand.h" + +static unsigned int *pread, *pwrite; + +static const struct udevice_id cortina_nand_dt_ids[] = { + { + .compatible = "cortina,ca-nand", + }, + { /* sentinel */ } +}; + +static struct nand_ecclayout eccoob; + +/* Information about an attached NAND chip */ +struct fdt_nand { + int enabled; /* 1 to enable, 0 to disable */ + s32 width; /* bit width, must be 8 */ + u32 nand_ecc_strength; +}; + +struct nand_drv { + u32 fifo_index; + struct nand_ctlr *reg; + struct dma_global *dma_glb; + struct dma_ssp *dma_nand; + struct tx_descriptor_t *tx_desc; + struct rx_descriptor_t *rx_desc; + struct fdt_nand config; + unsigned int flash_base; +}; + +struct ca_nand_info { + struct udevice *dev; + struct nand_drv nand_ctrl; + struct nand_chip nand_chip; +}; + +/** + * Wait for command completion + * + * @param reg nand_ctlr structure + * @return + * 1 - Command completed + * 0 - Timeout + */ +static int nand_waitfor_cmd_completion(struct nand_ctlr *reg, unsigned int mask) +{ + unsigned int reg_v = 0; + + if (readl_poll_timeout(®->flash_flash_access_start, reg_v, + !(reg_v & mask), (FLASH_LONG_DELAY << 2))) { + pr_err("Nand CMD timeout!\n"); + return 0; + } + + return 1; +} + +/** + * Read one byte from the chip + * + * @param mtd MTD device structure + * @return data byte + * + * Read function for 8bit bus-width + */ +static uint8_t read_byte(struct mtd_info *mtd) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + struct nand_drv *info; + u8 ret_v; + + info = (struct nand_drv *)nand_get_controller_data(chip); + + clrsetbits_le32(&info->reg->flash_flash_access_start, GENMASK(31, 0), + NFLASH_GO | NFLASH_RD); + + if (!nand_waitfor_cmd_completion(info->reg, NFLASH_GO)) + printf("%s: Command timeout\n", __func__); + + ret_v = readl(&info->reg->flash_nf_data) >> (8 * info->fifo_index++); + info->fifo_index %= 4; + + return (uint8_t)ret_v; +} + +/** + * Read len bytes from the chip into a buffer + * + * @param mtd MTD device structure + * @param buf buffer to store data to + * @param len number of bytes to read + * + * Read function for 8bit bus-width + */ +static void read_buf(struct mtd_info *mtd, uint8_t *buf, int len) +{ + int i; + unsigned int reg; + struct nand_chip *chip = mtd_to_nand(mtd); + struct nand_drv *info = + (struct nand_drv *)nand_get_controller_data(chip); + + for (i = 0; i < len; i++) { + clrsetbits_le32(&info->reg->flash_flash_access_start, + GENMASK(31, 0), NFLASH_GO | NFLASH_RD); + + if (!nand_waitfor_cmd_completion(info->reg, NFLASH_GO)) + printf("%s: Command timeout\n", __func__); + + reg = readl(&info->reg->flash_nf_data) >> + (8 * info->fifo_index++); + memcpy(buf + i, ®, 1); + info->fifo_index %= 4; + } +} + +/** + * Check READY pin status to see if it is ready or not + * + * @param mtd MTD device structure + * @return + * 1 - ready + * 0 - not ready + */ +static int nand_dev_ready(struct mtd_info *mtd) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + int reg_val; + struct nand_drv *info = + (struct nand_drv *)nand_get_controller_data(chip); + + reg_val = readl(&info->reg->flash_status); + if (reg_val & NFLASH_READY) + return 1; + else + return 0; +} + +/* Dummy implementation: we don't support multiple chips */ +static void nand_select_chip(struct mtd_info *mtd, int chipnr) +{ + switch (chipnr) { + case -1: + case 0: + break; + + default: + WARN_ON(chipnr); + } +} + +int init_nand_dma(struct nand_chip *nand) +{ + int i; + struct nand_drv *info = + (struct nand_drv *)nand_get_controller_data(nand); + + setbits_le32(&info->dma_glb->dma_glb_dma_lso_ctrl, TX_DMA_ENABLE); + setbits_le32(&info->dma_glb->dma_glb_dma_ssp_rx_ctrl, + TX_DMA_ENABLE | DMA_CHECK_OWNER); + setbits_le32(&info->dma_glb->dma_glb_dma_ssp_tx_ctrl, + RX_DMA_ENABLE | DMA_CHECK_OWNER); + + info->tx_desc = malloc_cache_aligned((sizeof(struct tx_descriptor_t) * + CA_DMA_DESC_NUM)); + info->rx_desc = malloc_cache_aligned((sizeof(struct rx_descriptor_t) * + CA_DMA_DESC_NUM)); + + if (!info->rx_desc && info->tx_desc) { + printf("Fail to alloc DMA descript!\n"); + kfree(info->tx_desc); + return -ENOMEM; + } else if (info->rx_desc && !info->tx_desc) { + printf("Fail to alloc DMA descript!\n"); + kfree(info->tx_desc); + return -ENOMEM; + } + + /* set RX DMA base address and depth */ + clrsetbits_le32(&info->dma_nand->dma_q_rxq_base_depth, + GENMASK(31, 4), (uintptr_t)info->rx_desc); + clrsetbits_le32(&info->dma_nand->dma_q_rxq_base_depth, + GENMASK(3, 0), CA_DMA_DEPTH); + + /* set TX DMA base address and depth */ + clrsetbits_le32(&info->dma_nand->dma_q_txq_base_depth, + GENMASK(31, 4), (uintptr_t)info->tx_desc); + clrsetbits_le32(&info->dma_nand->dma_q_txq_base_depth, + GENMASK(3, 0), CA_DMA_DEPTH); + + memset((unsigned char *)info->tx_desc, 0, + (sizeof(struct tx_descriptor_t) * CA_DMA_DESC_NUM)); + memset((unsigned char *)info->rx_desc, 0, + (sizeof(struct rx_descriptor_t) * CA_DMA_DESC_NUM)); + + for (i = 0; i < CA_DMA_DESC_NUM; i++) { + /* set owner bit as SW */ + info->tx_desc[i].own = 1; + /* enable Scatter-Gather memory copy */ + info->tx_desc[i].sgm = 0x1; + } + + return 0; +} + +/** + * Send command to NAND device + * + * @param mtd MTD device structure + * @param command the command to be sent + * @param column the column address for this command, -1 if none + * @param page_addr the page address for this command, -1 if none + */ +static void ca_nand_command(struct mtd_info *mtd, unsigned int command, + int column, int page_addr) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + struct nand_drv *info; + unsigned int reg_v = 0; + u32 cmd = 0, cnt = 0, addr1 = 0, addr2 = 0; + int ret; + + info = (struct nand_drv *)nand_get_controller_data(chip); + /* + * Write out the command to the device. + * + * Only command NAND_CMD_RESET or NAND_CMD_READID will come + * here before mtd->writesize is initialized. + */ + + /* Emulate NAND_CMD_READOOB */ + if (command == NAND_CMD_READOOB) { + assert(mtd->writesize != 0); + column += mtd->writesize; + command = NAND_CMD_READ0; + } + + /* Reset FIFO before issue new command */ + clrsetbits_le32(&info->reg->flash_nf_ecc_reset, GENMASK(31, 0), + ECC_RESET_ALL); + ret = + readl_poll_timeout(&info->reg->flash_nf_ecc_reset, reg_v, + !(reg_v & RESET_NFLASH_FIFO), FLASH_SHORT_DELAY); + if (ret) { + printf("FIFO reset timeout\n"); + clrsetbits_le32(&info->reg->flash_nf_ecc_reset, GENMASK(31, 0), + ECC_RESET_ALL); + udelay(10); + } + + /* Reset FIFO index + * Next read start from flash_nf_data[0] + */ + info->fifo_index = 0; + + clrsetbits_le32(&info->reg->flash_nf_access, GENMASK(11, 10), + NFLASH_REG_WIDTH_8); + + /* + * Program and erase have their own busy handlers + * status and sequential in needs no delay + */ + switch (command) { + case NAND_CMD_READID: + /* Command */ + clrsetbits_le32(&info->reg->flash_nf_command, GENMASK(31, 0), + NAND_CMD_READID); + /* 1 byte CMD cycle */ + clrsetbits_le32(&info->reg->flash_nf_count, GENMASK(1, 0), + REG_CMD_COUNT_1TOGO); + /* 1 byte CMD cycle */ + clrsetbits_le32(&info->reg->flash_nf_count, GENMASK(6, 4), + REG_ADDR_COUNT_1); + /* Data cycle */ + clrsetbits_le32(&info->reg->flash_nf_count, GENMASK(21, 8), + REG_DATA_COUNT_DATA_4); + /* 0 OOB cycle */ + clrsetbits_le32(&info->reg->flash_nf_count, GENMASK(31, 22), + REG_OOB_COUNT_EMPTY); + + /* addresses */ + clrsetbits_le32(&info->reg->flash_nf_address_1, GENMASK(31, 0), + column & ADDR1_MASK2); + clrsetbits_le32(&info->reg->flash_nf_address_2, GENMASK(31, 0), + 0); + + /* clear FLASH_NF_ACCESS */ + clrsetbits_le32(&info->reg->flash_nf_access, GENMASK(31, 0), + DISABLE_AUTO_RESET); + + break; + case NAND_CMD_PARAM: + /* Command */ + clrsetbits_le32(&info->reg->flash_nf_command, GENMASK(31, 0), + NAND_CMD_PARAM); + /* 1 byte CMD cycle */ + clrsetbits_le32(&info->reg->flash_nf_count, GENMASK(1, 0), + REG_CMD_COUNT_1TOGO); + /* 1 byte ADDR cycle */ + clrsetbits_le32(&info->reg->flash_nf_count, GENMASK(6, 4), + REG_ADDR_COUNT_1); + /* Data cycle */ + clrsetbits_le32(&info->reg->flash_nf_count, GENMASK(21, 8), + (SZ_4K - 1) << 8); + /* 0 OOB cycle */ + clrsetbits_le32(&info->reg->flash_nf_count, GENMASK(31, 22), + REG_OOB_COUNT_EMPTY); + + /* addresses */ + clrsetbits_le32(&info->reg->flash_nf_address_1, GENMASK(31, 0), + column & ADDR1_MASK2); + clrsetbits_le32(&info->reg->flash_nf_address_2, GENMASK(31, 0), + 0); + + break; + case NAND_CMD_READ0: + if (chip->chipsize < SZ_32M) { + cmd = NAND_CMD_READ0; + cnt = REG_CMD_COUNT_1TOGO | REG_ADDR_COUNT_3; + addr1 = (((page_addr & ADDR1_MASK0) << 8)); + addr2 = ((page_addr & ADDR2_MASK0) >> 24); + } else if (chip->chipsize >= SZ_32M && + (chip->chipsize <= SZ_128M)) { + cmd = NAND_CMD_READ0; + cnt = REG_ADDR_COUNT_4; + if (mtd->writesize > (REG_DATA_COUNT_512_DATA >> 8)) { + cmd |= (NAND_CMD_READSTART << 8); + cnt |= REG_CMD_COUNT_2TOGO; + } else { + cnt |= REG_CMD_COUNT_1TOGO; + } + addr1 = ((page_addr << 16) | (column & ADDR1_MASK1)); + addr2 = (page_addr >> 16); + } else { + cmd = NAND_CMD_READ0 | (NAND_CMD_READSTART << 8); + cnt = REG_CMD_COUNT_2TOGO | REG_ADDR_COUNT_5; + addr1 = ((page_addr << 16) | (column & ADDR1_MASK1)); + addr2 = (page_addr >> 16); + } + + /* Command */ + clrsetbits_le32(&info->reg->flash_nf_command, GENMASK(31, 0), + cmd); + /* CMD & ADDR cycle */ + clrsetbits_le32(&info->reg->flash_nf_count, GENMASK(7, 0), cnt); + /* Data cycle */ + clrsetbits_le32(&info->reg->flash_nf_count, GENMASK(21, 8), + (mtd->writesize - 1) << 8); + /* OOB cycle */ + clrsetbits_le32(&info->reg->flash_nf_count, GENMASK(31, 22), + (mtd->oobsize - 1) << 22); + + /* addresses */ + clrsetbits_le32(&info->reg->flash_nf_address_1, GENMASK(31, 0), + addr1); + clrsetbits_le32(&info->reg->flash_nf_address_2, GENMASK(31, 0), + addr2); + + return; + case NAND_CMD_SEQIN: + if (chip->chipsize < SZ_32M) { + cnt = REG_CMD_COUNT_2TOGO | REG_ADDR_COUNT_3; + addr1 = (((page_addr & ADDR1_MASK0) << 8)); + addr2 = ((page_addr & ADDR2_MASK0) >> 24); + } else if (chip->chipsize >= SZ_32M && + (chip->chipsize <= SZ_128M)) { + cnt = REG_CMD_COUNT_2TOGO | REG_ADDR_COUNT_4; + addr1 = ((page_addr << 16) | (column & ADDR1_MASK1)); + addr2 = (page_addr >> 16); + } else { + cnt = REG_CMD_COUNT_2TOGO | REG_ADDR_COUNT_5; + addr1 = ((page_addr << 16) | (column & ADDR1_MASK1)); + addr2 = (page_addr >> 16); + } + + /* Command */ + clrsetbits_le32(&info->reg->flash_nf_command, GENMASK(31, 0), + NAND_CMD_SEQIN | (NAND_CMD_PAGEPROG << 8)); + /* CMD cycle */ + clrsetbits_le32(&info->reg->flash_nf_count, GENMASK(7, 0), cnt); + /* Data cycle */ + clrsetbits_le32(&info->reg->flash_nf_count, GENMASK(21, 8), + (mtd->writesize - 1) << 8); + /* OOB cycle */ + clrsetbits_le32(&info->reg->flash_nf_count, GENMASK(31, 22), + (mtd->oobsize - 1) << 22); + + /* addresses */ + clrsetbits_le32(&info->reg->flash_nf_address_1, GENMASK(31, 0), + addr1); + clrsetbits_le32(&info->reg->flash_nf_address_2, GENMASK(31, 0), + addr2); + + return; + case NAND_CMD_PAGEPROG: + return; + case NAND_CMD_ERASE1: + /* Command */ + clrsetbits_le32(&info->reg->flash_nf_command, GENMASK(31, 0), + NAND_CMD_ERASE1 | (NAND_CMD_ERASE2 << 8)); + /* 2 byte CMD cycle */ + clrsetbits_le32(&info->reg->flash_nf_count, GENMASK(1, 0), + REG_CMD_COUNT_2TOGO); + /* 3 byte ADDR cycle */ + clrsetbits_le32(&info->reg->flash_nf_count, GENMASK(6, 4), + REG_ADDR_COUNT_3); + /* 0 Data cycle */ + clrsetbits_le32(&info->reg->flash_nf_count, GENMASK(21, 8), + REG_DATA_COUNT_EMPTY); + /* 0 OOB cycle */ + clrsetbits_le32(&info->reg->flash_nf_count, GENMASK(31, 22), + REG_OOB_COUNT_EMPTY); + + /* addresses */ + clrsetbits_le32(&info->reg->flash_nf_address_1, GENMASK(31, 0), + page_addr); + clrsetbits_le32(&info->reg->flash_nf_address_2, GENMASK(31, 0), + 0); + + /* Issue command */ + clrsetbits_le32(&info->reg->flash_flash_access_start, + GENMASK(31, 0), NFLASH_GO | NFLASH_RD); + break; + case NAND_CMD_ERASE2: + return; + case NAND_CMD_STATUS: + /* Command */ + clrsetbits_le32(&info->reg->flash_nf_command, GENMASK(31, 0), + NAND_CMD_STATUS); + /* 1 byte CMD cycle */ + clrbits_le32(&info->reg->flash_nf_count, GENMASK(1, 0)); + /* 0 byte Addr cycle */ + clrsetbits_le32(&info->reg->flash_nf_count, GENMASK(6, 4), + REG_ADDR_COUNT_EMPTY); + /* 1 Data cycle */ + clrbits_le32(&info->reg->flash_nf_count, GENMASK(21, 8)); + /* 0 OOB cycle */ + clrsetbits_le32(&info->reg->flash_nf_count, GENMASK(31, 22), + REG_OOB_COUNT_EMPTY); + + break; + case NAND_CMD_RESET: + /* Command */ + clrsetbits_le32(&info->reg->flash_nf_command, GENMASK(31, 0), + NAND_CMD_RESET); + /* 1 byte CMD cycle */ + clrbits_le32(&info->reg->flash_nf_count, GENMASK(1, 0)); + /* 0 byte Addr cycle */ + clrsetbits_le32(&info->reg->flash_nf_count, GENMASK(6, 4), + REG_ADDR_COUNT_EMPTY); + /* 0 Data cycle */ + clrsetbits_le32(&info->reg->flash_nf_count, GENMASK(21, 8), + REG_DATA_COUNT_EMPTY); + /* 0 OOB cycle */ + clrsetbits_le32(&info->reg->flash_nf_count, GENMASK(31, 22), + REG_OOB_COUNT_EMPTY); + + /* addresses */ + clrsetbits_le32(&info->reg->flash_nf_address_1, GENMASK(31, 0), + column & ADDR1_MASK2); + clrsetbits_le32(&info->reg->flash_nf_address_2, GENMASK(31, 0), + 0); + + /* Issue command */ + clrsetbits_le32(&info->reg->flash_flash_access_start, + GENMASK(31, 0), NFLASH_GO | NFLASH_WT); + + break; + case NAND_CMD_RNDOUT: + default: + printf("%s: Unsupported command %d\n", __func__, command); + return; + } + + if (!nand_waitfor_cmd_completion(info->reg, NFLASH_GO)) + printf("Command 0x%02X timeout\n", command); +} + +/** + * Set up NAND bus width and page size + * + * @param info nand_info structure + * @return 0 if ok, -1 on error + */ +static int set_bus_width_page_size(struct mtd_info *mtd) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + struct nand_drv *info = + (struct nand_drv *)nand_get_controller_data(chip); + + if (info->config.width == SZ_8) { + clrsetbits_le32(&info->reg->flash_nf_access, GENMASK(31, 0), + NFLASH_REG_WIDTH_8); + } else if (info->config.width == SZ_16) { + clrsetbits_le32(&info->reg->flash_nf_access, GENMASK(31, 0), + NFLASH_REG_WIDTH_16); + } else { + debug("%s: Unsupported bus width %d\n", __func__, + info->config.width); + return -1; + } + + if (mtd->writesize == SZ_512) { + setbits_le32(&info->reg->flash_type, FLASH_TYPE_512); + } else if (mtd->writesize == SZ_2K) { + setbits_le32(&info->reg->flash_type, FLASH_TYPE_2K); + } else if (mtd->writesize == SZ_4K) { + setbits_le32(&info->reg->flash_type, FLASH_TYPE_4K); + } else if (mtd->writesize == SZ_8K) { + setbits_le32(&info->reg->flash_type, FLASH_TYPE_8K); + } else { + debug("%s: Unsupported page size %d\n", __func__, + mtd->writesize); + return -1; + } + + return 0; +} + +static int ca_do_bch_correction(struct nand_chip *chip, + unsigned int err_num, u8 *buff_ptr, int i) +{ + struct nand_drv *info = + (struct nand_drv *)nand_get_controller_data(chip); + unsigned int reg_v, err_loc0, err_loc1; + int k, max_bitflips; + + for (k = 0; k < (err_num + 1) / 2; k++) { + reg_v = readl(&info->reg->flash_nf_bch_error_loc01 + k); + err_loc0 = reg_v & BCH_ERR_LOC_MASK; + err_loc1 = (reg_v >> 16) & BCH_ERR_LOC_MASK; + + if (err_loc0 / 8 < BCH_DATA_UNIT) { + printf("pdata[%x]:%x =>", ((i / chip->ecc.bytes) * + chip->ecc.size + ((reg_v & 0x1fff) >> 3)), + buff_ptr[(reg_v & 0x1fff) >> 3]); + + buff_ptr[err_loc0 / 8] ^= + (1 << (reg_v & BCH_CORRECT_LOC_MASK)); + + printf("%x\n", buff_ptr[(reg_v & 0x1fff) >> 3]); + + max_bitflips++; + } + + if (((k + 1) * 2) <= err_num && ((err_loc1 / 8) < + BCH_DATA_UNIT)) { + printf("pdata[%x]:%x =>", ((i / chip->ecc.bytes) * + chip->ecc.size + (((reg_v >> 16) & 0x1fff) >> + 3)), buff_ptr[((reg_v >> 16) & 0x1fff) >> 3]); + + buff_ptr[err_loc1 / 8] ^= (1 << ((reg_v >> 16) & + BCH_CORRECT_LOC_MASK)); + + printf("%x\n", buff_ptr[((reg_v >> 16) & 0x1fff) >> 3]); + + max_bitflips++; + } + } + + return max_bitflips; +} + +static int ca_do_bch_decode(struct mtd_info *mtd, struct nand_chip *chip, + const u8 *buf, int page, unsigned int addr) +{ + struct nand_drv *info = + (struct nand_drv *)nand_get_controller_data(chip); + unsigned int reg_v, err_num; + unsigned char *ecc_code = chip->buffers->ecccode; + unsigned char *ecc_end_pos; + int ret, i, j, k, n, step, eccsteps, max_bitflips = 0; + u8 *buff_ptr = (u8 *)buf; + + for (i = 0; i < chip->ecc.total; i++) + ecc_code[i] = chip->oob_poi[eccoob.eccpos[i]]; + + for (i = 0, eccsteps = chip->ecc.steps; eccsteps; + i += chip->ecc.bytes, eccsteps--) { + ecc_end_pos = ecc_code + chip->ecc.bytes; + + for (j = 0, k = 0; j < chip->ecc.bytes; j += 4, k++) { + reg_v = 0; + for (n = 0; n < 4 && ecc_code != ecc_end_pos; + ++n, ++ecc_code) { + reg_v |= *ecc_code << (8 * n); + } + clrsetbits_le32(&info->reg->flash_nf_bch_oob0 + k, + GENMASK(31, 0), reg_v); + } + + /* Clear ECC buffer */ + setbits_le32(&info->reg->flash_nf_ecc_reset, RESET_NFLASH_ECC); + ret = readl_poll_timeout(&info->reg->flash_nf_ecc_reset, reg_v, + !(reg_v & RESET_NFLASH_ECC), + FLASH_SHORT_DELAY); + if (ret) + pr_err("Reset ECC buffer fail\n"); + + clrsetbits_le32(&info->reg->flash_nf_bch_control, GENMASK(8, 8), + BCH_DISABLE); + + /* Start BCH */ + step = i / chip->ecc.bytes; + clrsetbits_le32(&info->reg->flash_nf_bch_control, + GENMASK(6, 4), step << 4); + setbits_le32(&info->reg->flash_nf_bch_control, BCH_ENABLE); + udelay(10); + setbits_le32(&info->reg->flash_nf_bch_control, BCH_COMPARE); + + ret = readl_poll_timeout(&info->reg->flash_nf_bch_status, reg_v, + (reg_v & BCH_DECO_DONE), + FLASH_SHORT_DELAY); + if (ret) + pr_err("ECC Decode timeout\n"); + + /* Stop compare */ + clrbits_le32(&info->reg->flash_nf_bch_control, BCH_COMPARE); + + reg_v = readl(&info->reg->flash_nf_bch_status); + err_num = (reg_v >> 8) & BCH_ERR_NUM_MASK; + reg_v &= BCH_ERR_MASK; + + /* Uncorrectable */ + if (reg_v == BCH_UNCORRECTABLE) { + max_bitflips = + nand_check_erased_ecc_chunk(buff_ptr, + chip->ecc.size, + &chip->buffers->ecccode[i], + chip->ecc.bytes, + NULL, 0, + chip->ecc.strength); + + if (max_bitflips) { + mtd->ecc_stats.failed++; + pr_err("Uncorrectable error\n"); + pr_err(" Page:%x step:%d\n", page, step); + + return -1; + } + } else if (reg_v == BCH_CORRECTABLE_ERR) { + printf("Correctable error(%x)!! addr:%lx\n", + err_num, (unsigned long)addr - mtd->writesize); + printf("Dst buf: %p [ColSel:%x ]\n", + buff_ptr + reg_v * BCH_DATA_UNIT, step); + + max_bitflips = + ca_do_bch_correction(chip, err_num, buff_ptr, i); + } + + buff_ptr += BCH_DATA_UNIT; + } + + /* Disable BCH */ + clrsetbits_le32(&info->reg->flash_nf_bch_control, GENMASK(31, 0), + BCH_DISABLE); + + return max_bitflips; +} + +static int ca_do_bch_encode(struct mtd_info *mtd, struct nand_chip *chip, + int page) +{ + struct nand_drv *info; + unsigned int reg_v; + int i, j, n, eccsteps, gen_index; + + info = (struct nand_drv *)nand_get_controller_data(chip); + + for (i = 0, n = 0, eccsteps = chip->ecc.steps; eccsteps; + i += chip->ecc.bytes, eccsteps--, n++) { + gen_index = 0; + for (j = 0; j < chip->ecc.bytes; j += 4, gen_index++) { + reg_v = + readl(&info->reg->flash_nf_bch_gen0_0 + gen_index + + 18 * n); + chip->oob_poi[eccoob.eccpos[i + j]] = reg_v & OOB_MASK; + chip->oob_poi[eccoob.eccpos[i + j + 1]] = + (reg_v >> 8) & OOB_MASK; + chip->oob_poi[eccoob.eccpos[i + j + 2]] = + (reg_v >> 16) & OOB_MASK; + chip->oob_poi[eccoob.eccpos[i + j + 3]] = + (reg_v >> 24) & OOB_MASK; + } + } + + /* Disable BCH */ + clrsetbits_le32(&info->reg->flash_nf_bch_control, GENMASK(8, 8), + BCH_DISABLE); + + return 0; +} + +/** + * Page read/write function + * + * @param mtd mtd info structure + * @param chip nand chip info structure + * @param buf data buffer + * @param page page number + * @param with_ecc 1 to enable ECC, 0 to disable ECC + * @param is_writing 0 for read, 1 for write + * @return 0 when successfully completed + * -ETIMEDOUT when command timeout + */ +static int nand_rw_page(struct mtd_info *mtd, struct nand_chip *chip, + const u8 *buf, int page, int with_ecc, int is_writing) +{ + unsigned int reg_v, ext_addr, addr, dma_index; + struct tx_descriptor_t *tx_desc; + struct rx_descriptor_t *rx_desc; + struct nand_drv *info = + (struct nand_drv *)nand_get_controller_data(chip); + int ret; + + /* reset ecc control */ + clrsetbits_le32(&info->reg->flash_nf_ecc_reset, GENMASK(31, 0), + RESET_NFLASH_ECC); + + /* flash interrupt */ + clrsetbits_le32(&info->reg->flash_flash_interrupt, GENMASK(0, 0), + REGIRQ_CLEAR); + + /* reset ecc control */ + clrsetbits_le32(&info->reg->flash_nf_ecc_reset, GENMASK(31, 0), + RESET_NFLASH_ECC); + + /* Disable TXQ */ + clrbits_le32(&info->dma_nand->dma_q_txq_control, GENMASK(0, 0)); + + /* Clear interrupt */ + setbits_le32(&info->dma_nand->dma_q_rxq_coal_interrupt, GENMASK(0, 0)); + setbits_le32(&info->dma_nand->dma_q_txq_coal_interrupt, GENMASK(0, 0)); + + if (with_ecc == 1) { + switch (info->config.nand_ecc_strength) { + case ECC_STRENGTH_8: + reg_v = BCH_ERR_CAP_8; + break; + case ECC_STRENGTH_16: + reg_v = BCH_ERR_CAP_16; + break; + case ECC_STRENGTH_24: + reg_v = BCH_ERR_CAP_24; + break; + case ECC_STRENGTH_40: + reg_v = BCH_ERR_CAP_40; + break; + default: + reg_v = BCH_ERR_CAP_16; + break; + } + reg_v |= BCH_ENABLE; + + /* BCH decode for flash read */ + if (is_writing == 0) + reg_v |= BCH_DECODE; + clrsetbits_le32(&info->reg->flash_nf_bch_control, + GENMASK(31, 0), reg_v); + } else { + clrsetbits_le32(&info->reg->flash_nf_bch_control, + GENMASK(31, 0), 0); + } + + /* Fill Extend address */ + ext_addr = ((page << chip->page_shift) / EXT_ADDR_MASK); + + clrsetbits_le32(&info->reg->flash_nf_access, + GENMASK(7, 0), (uintptr_t)ext_addr); + + addr = (uintptr_t)((page << chip->page_shift) % EXT_ADDR_MASK); + addr = (uintptr_t)(addr + info->flash_base); + + dma_index = readl(&info->dma_nand->dma_q_txq_wptr) & CA_DMA_Q_PTR_MASK; + + tx_desc = info->tx_desc; + rx_desc = info->rx_desc; + + /* TX/RX descriptor for page data */ + tx_desc[dma_index].own = OWN_DMA; + tx_desc[dma_index].buf_len = mtd->writesize; + rx_desc[dma_index].own = OWN_DMA; + rx_desc[dma_index].buf_len = mtd->writesize; + if (is_writing == 0) { + tx_desc[dma_index].buf_adr = (uintptr_t)addr; + rx_desc[dma_index].buf_adr = (uintptr_t)(buf); + } else { + tx_desc[dma_index].buf_adr = (uintptr_t)buf; + rx_desc[dma_index].buf_adr = (uintptr_t)(addr); + } + + dma_index++; + dma_index %= CA_DMA_DESC_NUM; + + /* TX/RX descriptor for OOB area */ + addr = (uintptr_t)(addr + mtd->writesize); + tx_desc[dma_index].own = OWN_DMA; + tx_desc[dma_index].buf_len = mtd->oobsize; + rx_desc[dma_index].own = OWN_DMA; + rx_desc[dma_index].buf_len = mtd->oobsize; + if (is_writing) { + tx_desc[dma_index].buf_adr = (uintptr_t)(chip->oob_poi); + rx_desc[dma_index].buf_adr = (uintptr_t)addr; + } else { + tx_desc[dma_index].buf_adr = (uintptr_t)addr; + rx_desc[dma_index].buf_adr = (uintptr_t)(chip->oob_poi); + dma_index++; + dma_index %= CA_DMA_DESC_NUM; + } + + if (is_writing == 1) { + clrsetbits_le32(&info->reg->flash_fifo_control, GENMASK(1, 0), + FIFO_WRITE); + } else { + clrsetbits_le32(&info->reg->flash_fifo_control, GENMASK(1, 0), + FIFO_READ); + } + + /* Start FIFO request */ + clrsetbits_le32(&info->reg->flash_flash_access_start, GENMASK(2, 2), + NFLASH_FIFO_REQ); + + /* Update DMA write pointer */ + clrsetbits_le32(&info->dma_nand->dma_q_txq_wptr, GENMASK(12, 0), + dma_index); + + /* Start DMA */ + clrsetbits_le32(&info->dma_nand->dma_q_txq_control, GENMASK(0, 0), + TX_DMA_ENABLE); + + /* Wait TX DMA done */ + ret = + readl_poll_timeout(&info->dma_nand->dma_q_txq_coal_interrupt, + reg_v, (reg_v & 1), FLASH_LONG_DELAY); + if (ret) { + pr_err("TX DMA timeout\n"); + return -ETIMEDOUT; + } + /* clear tx interrupt */ + setbits_le32(&info->dma_nand->dma_q_txq_coal_interrupt, 1); + + /* Wait RX DMA done */ + ret = + readl_poll_timeout(&info->dma_nand->dma_q_rxq_coal_interrupt, reg_v, + (reg_v & 1), FLASH_LONG_DELAY); + if (ret) { + pr_err("RX DMA timeout\n"); + return -ETIMEDOUT; + } + /* clear rx interrupt */ + setbits_le32(&info->dma_nand->dma_q_rxq_coal_interrupt, 1); + + /* wait NAND CMD done */ + if (is_writing == 0) { + if (!nand_waitfor_cmd_completion(info->reg, NFLASH_FIFO_REQ)) + printf("%s: Command timeout\n", __func__); + } + + /* Update DMA read pointer */ + clrsetbits_le32(&info->dma_nand->dma_q_rxq_rptr, GENMASK(12, 0), + dma_index); + + /* ECC correction */ + if (with_ecc == 1) { + ret = + readl_poll_timeout(&info->reg->flash_nf_bch_status, + reg_v, (reg_v & BCH_GEN_DONE), + FLASH_LONG_DELAY); + + if (ret) { + pr_err("BCH_GEN timeout! flash_nf_bch_status=[0x%x]\n", + reg_v); + return -ETIMEDOUT; + } + + if (is_writing == 0) + ca_do_bch_decode(mtd, chip, buf, page, addr); + else + ca_do_bch_encode(mtd, chip, page); + } + + if (is_writing) { + dma_index++; + dma_index %= CA_DMA_DESC_NUM; + + /* Update DMA R/W pointer */ + clrsetbits_le32(&info->dma_nand->dma_q_txq_wptr, GENMASK(12, 0), + dma_index); + + /* Wait TX DMA done */ + ret = + readl_poll_timeout(&info->dma_nand->dma_q_txq_coal_interrupt, + reg_v, (reg_v & 1), FLASH_LONG_DELAY); + if (ret) { + pr_err("TX DMA timeout\n"); + return -ETIMEDOUT; + } + /* clear tx interrupt */ + setbits_le32(&info->dma_nand->dma_q_txq_coal_interrupt, 1); + + /* Wait RX DMA done */ + ret = + readl_poll_timeout(&info->dma_nand->dma_q_rxq_coal_interrupt, + reg_v, (reg_v & 1), FLASH_LONG_DELAY); + if (ret) { + pr_err("RX DMA timeout\n"); + return -ETIMEDOUT; + } + /* clear rx interrupt */ + setbits_le32(&info->dma_nand->dma_q_rxq_coal_interrupt, 1); + + /* wait NAND CMD done */ + if (!nand_waitfor_cmd_completion(info->reg, NFLASH_FIFO_REQ)) + printf("%s: Command timeout\n", __func__); + + /* Update DMA R/W pointer */ + clrsetbits_le32(&info->dma_nand->dma_q_rxq_rptr, GENMASK(12, 0), + dma_index); + } + + return 0; +} + +/** + * Hardware ecc based page read function + * + * @param mtd mtd info structure + * @param chip nand chip info structure + * @param buf buffer to store read data + * @param page page number to read + * @return 0 when successfully completed + * -ETIMEDOUT when command timeout + */ +static int nand_read_page_hwecc(struct mtd_info *mtd, + struct nand_chip *chip, uint8_t *buf, + int oob_required, int page) +{ + struct nand_drv *info = + (struct nand_drv *)nand_get_controller_data(chip); + int ret; + + ret = nand_rw_page(mtd, chip, buf, page, 1, 0); + if (ret) + return ret; + + /* Reset FIFO */ + clrsetbits_le32(&info->reg->flash_nf_ecc_reset, GENMASK(31, 0), + ECC_RESET_ALL); + + return 0; +} + +/** + * Hardware ecc based page write function + * + * @param mtd mtd info structure + * @param chip nand chip info structure + * @param buf data buffer + * @return 0 when successfully completed + * -ETIMEDOUT when command timeout + */ +static int nand_write_page_hwecc(struct mtd_info *mtd, + struct nand_chip *chip, const uint8_t *buf, + int oob_required, int page) +{ + struct nand_drv *info = + (struct nand_drv *)nand_get_controller_data(chip); + int ret; + + ret = nand_rw_page(mtd, chip, (uint8_t *)buf, page, 1, 1); + if (ret) + return ret; + + /* Reset FIFO */ + clrsetbits_le32(&info->reg->flash_nf_ecc_reset, GENMASK(31, 0), + ECC_RESET_ALL); + + return 0; +} + +/** + * Read raw page data without ecc + * + * @param mtd mtd info structure + * @param chip nand chip info structure + * @param buf buffer to store read data + * @param page page number to read + * @return 0 when successfully completed + * -ETIMEDOUT when command timeout + */ +static int nand_read_page_raw(struct mtd_info *mtd, + struct nand_chip *chip, uint8_t *buf, + int oob_required, int page) +{ + struct nand_drv *info = + (struct nand_drv *)nand_get_controller_data(chip); + int ret; + + ret = nand_rw_page(mtd, chip, buf, page, 0, 0); + if (ret) + return ret; + + /* Reset FIFO */ + clrsetbits_le32(&info->reg->flash_nf_ecc_reset, GENMASK(31, 0), + ECC_RESET_ALL); + + return 0; +} + +/** + * Raw page write function + * + * @param mtd mtd info structure + * @param chip nand chip info structure + * @param buf data buffer + * @return 0 when successfully completed + * -ETIMEDOUT when command timeout + */ +static int nand_write_page_raw(struct mtd_info *mtd, + struct nand_chip *chip, const uint8_t *buf, + int oob_required, int page) +{ + struct nand_drv *info = + (struct nand_drv *)nand_get_controller_data(chip); + int ret; + + ret = nand_rw_page(mtd, chip, buf, page, 0, 1); + if (ret) + return ret; + + /* Reset FIFO */ + clrsetbits_le32(&info->reg->flash_nf_ecc_reset, GENMASK(31, 0), + ECC_RESET_ALL); + + return 0; +} + +/** + * OOB data read/write function + * + * @param mtd mtd info structure + * @param chip nand chip info structure + * @param page page number to read + * @param with_ecc 1 to enable ECC, 0 to disable ECC + * @param is_writing 0 for read, 1 for write + * @return 0 when successfully completed + * -ETIMEDOUT when command timeout + */ +static int nand_rw_oob(struct mtd_info *mtd, struct nand_chip *chip, + int page, int with_ecc, int is_writing) +{ + struct nand_drv *info = + (struct nand_drv *)nand_get_controller_data(chip); + u32 reg_val; + int rw_index; + + if (is_writing) { + reg_val = NFLASH_GO | NFLASH_WT; + pwrite = (unsigned int *)chip->oob_poi; + } else { + reg_val = NFLASH_GO | NFLASH_RD; + pread = (unsigned int *)chip->oob_poi; + } + + for (rw_index = 0; rw_index < mtd->oobsize / 4; rw_index++) { + clrsetbits_le32(&info->reg->flash_nf_access, GENMASK(31, 0), + NFLASH_REG_WIDTH_32); + if (is_writing) + clrsetbits_le32(&info->reg->flash_nf_data, + GENMASK(31, 0), pwrite[rw_index]); + + clrsetbits_le32(&info->reg->flash_flash_access_start, + GENMASK(11, 10), reg_val); + + if (!nand_waitfor_cmd_completion(info->reg, NFLASH_GO)) + printf("%s: Command timeout\n", __func__); + + if (!is_writing) + pread[rw_index] = readl(&info->reg->flash_nf_data); + } + return 0; +} + +/** + * OOB data read function + * + * @param mtd mtd info structure + * @param chip nand chip info structure + * @param page page number to read + */ +static int nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip, int page) +{ + struct nand_drv *info = + (struct nand_drv *)nand_get_controller_data(chip); + int ret; + + chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); + if (mtd->writesize <= (REG_DATA_COUNT_512_DATA >> 8)) + clrsetbits_le32(&info->reg->flash_nf_command, GENMASK(7, 0), + NAND_CMD_READOOB); + ret = nand_rw_oob(mtd, chip, page, 0, 0); + + /* Reset FIFO */ + clrsetbits_le32(&info->reg->flash_nf_ecc_reset, + GENMASK(31, 0), ECC_RESET_ALL); + + return ret; +} + +/** + * OOB data write function + * + * @param mtd mtd info structure + * @param chip nand chip info structure + * @param page page number to write + * @return 0 when successfully completed + * -ETIMEDOUT when command timeout + */ +static int nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip, + int page) +{ + struct nand_drv *info = + (struct nand_drv *)nand_get_controller_data(chip); + int ret; + + chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page); + if (mtd->writesize <= (REG_DATA_COUNT_512_DATA >> 8)) { + clrsetbits_le32(&info->reg->flash_nf_command, GENMASK(31, 0), + NAND_CMD_READOOB | (NAND_CMD_SEQIN << 8) | + (NAND_CMD_PAGEPROG << 16)); + clrsetbits_le32(&info->reg->flash_nf_count, GENMASK(1, 0), + REG_CMD_COUNT_3TOGO); + } + ret = nand_rw_oob(mtd, chip, page, 1, 1); + + /* Reset FIFO */ + clrsetbits_le32(&info->reg->flash_nf_ecc_reset, + GENMASK(31, 0), ECC_RESET_ALL); + + return ret; +} + +/** + * Decode NAND parameters from the device tree + * + * @param dev Driver model device + * @param config Device tree NAND configuration + */ +static int fdt_decode_nand(struct udevice *dev, struct nand_drv *info) +{ + int ecc_strength; + + info->reg = (struct nand_ctlr *)dev_read_addr(dev); + info->dma_glb = (struct dma_global *)dev_read_addr_index(dev, 1); + info->dma_nand = (struct dma_ssp *)dev_read_addr_index(dev, 2); + info->config.enabled = dev_read_enabled(dev); + ecc_strength = dev_read_u32_default(dev, "nand-ecc-strength", 16); + info->flash_base = + dev_read_u32_default(dev, "nand_flash_base_addr", NAND_BASE_ADDR); + + switch (ecc_strength) { + case ECC_STRENGTH_8: + info->config.nand_ecc_strength = ECC_STRENGTH_8; + break; + case ECC_STRENGTH_16: + info->config.nand_ecc_strength = ECC_STRENGTH_16; + break; + case ECC_STRENGTH_24: + info->config.nand_ecc_strength = ECC_STRENGTH_24; + break; + case ECC_STRENGTH_40: + info->config.nand_ecc_strength = ECC_STRENGTH_40; + break; + default: + info->config.nand_ecc_strength = ECC_STRENGTH_16; + } + + return 0; +} + +/** + * config flash type + * + * @param chip nand chip info structure + */ +static void nand_config_flash_type(struct nand_chip *nand) +{ + struct nand_drv *info = + (struct nand_drv *)nand_get_controller_data(nand); + struct mtd_info *mtd = nand_to_mtd(nand); + + switch (mtd->writesize) { + case WRITE_SIZE_512: + clrsetbits_le32(&info->reg->flash_type, GENMASK(31, 0), + FLASH_PIN | FLASH_TYPE_512); + break; + case WRITE_SIZE_2048: + clrsetbits_le32(&info->reg->flash_type, GENMASK(31, 0), + FLASH_PIN | FLASH_TYPE_2K); + break; + case WRITE_SIZE_4096: + clrsetbits_le32(&info->reg->flash_type, GENMASK(31, 0), + FLASH_PIN | FLASH_TYPE_4K); + break; + case WRITE_SIZE_8192: + clrsetbits_le32(&info->reg->flash_type, GENMASK(31, 0), + FLASH_PIN | FLASH_TYPE_8K); + break; + default: + pr_err("Unsupported page size(0x%x)!", nand->ecc.size); + } +} + +/** + * config oob layout + * + * @param chip nand chip info structure + * @return 0 when successfully completed + * -EINVAL when ECC bytes exceed OOB size + */ +static int nand_config_oob_layout(struct nand_chip *nand) +{ + int i, ecc_start_offset; + struct mtd_info *mtd = nand_to_mtd(nand); + + /* Calculate byte count for ECC */ + eccoob.eccbytes = mtd->writesize / nand->ecc.size * nand->ecc.bytes; + + if (mtd->oobsize < eccoob.eccbytes) { + pr_err("Spare area(%d) too small for BCH%d\n", nand->ecc.bytes, + nand->ecc.strength / 8); + pr_err("page_sz: %d\n", nand->ecc.size); + pr_err("oob_sz: %d\n", nand->ecc.bytes); + return -EINVAL; + } + + /* Update OOB layout */ + ecc_start_offset = mtd->oobsize - eccoob.eccbytes; + memset(eccoob.eccpos, 0, sizeof(eccoob.eccpos)); + for (i = 0; i < eccoob.eccbytes; ++i) + eccoob.eccpos[i] = i + ecc_start_offset; + + /* Unused spare area + * OOB[0] is bad block marker. + * Extra two byte is reserved as + * erase marker just right before ECC code. + */ + eccoob.oobavail = nand->ecc.bytes - eccoob.eccbytes - 2; + eccoob.oobfree[0].offset = 2; + eccoob.oobfree[0].length = + mtd->oobsize - eccoob.eccbytes - eccoob.oobfree[0].offset - 1; + + return 0; +} + +static int ca_nand_probe(struct udevice *dev) +{ + struct ca_nand_info *ca_nand = dev_get_priv(dev); + struct nand_chip *nand = &ca_nand->nand_chip; + struct nand_drv *info = &ca_nand->nand_ctrl; + struct fdt_nand *config = &info->config; + struct mtd_info *our_mtd; + int ret; + + if (fdt_decode_nand(dev, info)) { + printf("Could not decode nand-flash in device tree\n"); + return -1; + } + if (!config->enabled) + return -1; + + nand->ecc.mode = NAND_ECC_HW; + nand->ecc.layout = &eccoob; + + nand->cmdfunc = ca_nand_command; + nand->read_byte = read_byte; + nand->read_buf = read_buf; + nand->ecc.read_page = nand_read_page_hwecc; + nand->ecc.write_page = nand_write_page_hwecc; + nand->ecc.read_page_raw = nand_read_page_raw; + nand->ecc.write_page_raw = nand_write_page_raw; + nand->ecc.read_oob = nand_read_oob; + nand->ecc.write_oob = nand_write_oob; + nand->ecc.strength = config->nand_ecc_strength; + nand->select_chip = nand_select_chip; + nand->dev_ready = nand_dev_ready; + nand_set_controller_data(nand, &ca_nand->nand_ctrl); + + /* Disable subpage writes as we do not provide ecc->hwctl */ + nand->options |= NAND_NO_SUBPAGE_WRITE | NAND_SKIP_BBTSCAN; + + /* Configure flash type as P-NAND */ + clrsetbits_le32(&info->reg->flash_type, FLASH_PIN, + FLASH_TYPE_4K | FLASH_SIZE_436OOB); + config->width = FLASH_WIDTH; + + our_mtd = nand_to_mtd(nand); + ret = nand_scan_ident(our_mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL); + if (ret) + return ret; + + nand->ecc.size = BCH_DATA_UNIT; + nand->ecc.bytes = BCH_GF_PARAM_M * (nand->ecc.strength / 8); + + /* Reconfig flash type according to ONFI */ + nand_config_flash_type(nand); + + ret = set_bus_width_page_size(our_mtd); + if (ret) + return ret; + + /* Set the bad block position */ + nand->badblockpos = + our_mtd->writesize > + 512 ? NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS; + + /* Arrange OOB layout */ + ret = nand_config_oob_layout(nand); + if (ret) + return ret; + + /* Init DMA descriptor ring */ + ret = init_nand_dma(nand); + if (ret) + return ret; + + ret = nand_scan_tail(our_mtd); + if (ret) + return ret; + + ret = nand_register(0, our_mtd); + if (ret) { + dev_err(dev, "Failed to register MTD: %d\n", ret); + return ret; + } + + ret = set_bus_width_page_size(our_mtd); + if (ret) + return ret; + + printf("P-NAND : %s\n", our_mtd->name); + printf("Chip Size: %lldMB\n", nand->chipsize / (1024 * 1024)); + printf("Block Size: %dKB\n", our_mtd->erasesize / 1024); + printf("Page Size: %dB\n", our_mtd->writesize); + printf("OOB Size: %dB\n", our_mtd->oobsize); + + return 0; +} + +U_BOOT_DRIVER(cortina_nand) = { + .name = "CA-PNAND", + .id = UCLASS_MTD, + .of_match = cortina_nand_dt_ids, + .probe = ca_nand_probe, + .priv_auto = sizeof(struct ca_nand_info), +}; + +void board_nand_init(void) +{ + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_MTD, + DM_DRIVER_GET(cortina_nand), &dev); + if (ret && ret != -ENODEV) + pr_err("Failed to initialize %s. (error %d)\n", dev->name, ret); +} diff --git a/drivers/mtd/nand/raw/cortina_nand.h b/drivers/mtd/nand/raw/cortina_nand.h new file mode 100644 index 00000000000..1e3e3bfd055 --- /dev/null +++ b/drivers/mtd/nand/raw/cortina_nand.h @@ -0,0 +1,293 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2020 Cortina Access Inc.. + */ + +/* Cortina NAND definition */ +#define NAND_BASE_ADDR 0xE0000000 +#define BCH_GF_PARAM_M 14 +#define BCH_DATA_UNIT 1024 +#define FLASH_SHORT_DELAY 100 +#define FLASH_LONG_DELAY 1000 +#define FLASH_WIDTH 16 +#define BBT_PAGE_MASK 0xffffff3f +#define WRITE_SIZE_512 512 +#define WRITE_SIZE_2048 2048 +#define WRITE_SIZE_4096 4096 +#define WRITE_SIZE_8192 8192 +#define ECC_STRENGTH_8 8 +#define ECC_STRENGTH_16 16 +#define ECC_STRENGTH_24 24 +#define ECC_STRENGTH_40 40 +#define EMPTY_PAGE 0xff +#define ADDR1_MASK0 0x00ffffff +#define ADDR2_MASK0 0xff000000 +#define ADDR1_MASK1 0xffff +#define ADDR1_MASK2 0xff +#define OOB_MASK 0xff +#define EXT_ADDR_MASK 0x8000000 + +/* Status bits */ +#define NAND_STATUS_FAIL 0x01 +#define NAND_STATUS_FAIL_N1 0x02 +#define NAND_STATUS_TRUE_READY 0x20 +#define NAND_STATUS_READY 0x40 +#define NAND_STATUS_WP 0x80 + +/* Bit field in FLAS_TYPE */ +#define FLASH_PIN BIT(15) +#define FLASH_TYPE_512 0x4000 +#define FLASH_TYPE_2K 0x5000 +#define FLASH_TYPE_4K 0x6000 +#define FLASH_TYPE_8K 0x7000 +#define FLASH_SIZE_CONFIGURABLEOOB (0x0 << 9) +#define FLASH_SIZE_400OOB (0x1 << 9) +#define FLASH_SIZE_436OOB (0x2 << 9) +#define FLASH_SIZE_640OOB (0x3 << 9) + +/* Bit field in FLASH_STATUS */ +#define NFLASH_READY BIT(26) + +/* Bit field in FLASH_NF_ACCESS */ +#define NFLASH_ENABLE_ALTERNATIVE (0x0 << 15) +#define AUTO_RESET BIT(16) +#define DISABLE_AUTO_RESET (0x0 << 16) +#define NFLASH_REG_WIDTH_RESERVED (0x3 << 10) +#define NFLASH_REG_WIDTH_32 (0x2 << 10) +#define NFLASH_REG_WIDTH_16 (0x1 << 10) +#define NFLASH_REG_WIDTH_8 (0x0 << 10) + +/* Bit field in FLASH_NF_COUNT */ +#define REG_CMD_COUNT_EMPTY 0x3 +#define REG_CMD_COUNT_3TOGO 0x2 +#define REG_CMD_COUNT_2TOGO 0x1 +#define REG_CMD_COUNT_1TOGO 0x0 +#define REG_ADDR_COUNT_EMPTY (0x7 << 4) +#define REG_ADDR_COUNT_5 (0x4 << 4) +#define REG_ADDR_COUNT_4 (0x3 << 4) +#define REG_ADDR_COUNT_3 (0x2 << 4) +#define REG_ADDR_COUNT_2 (0x1 << 4) +#define REG_ADDR_COUNT_1 (0x0 << 4) +#define REG_DATA_COUNT_EMPTY (0x3fff << 8) +#define REG_DATA_COUNT_512_DATA (0x1FF << 8) +#define REG_DATA_COUNT_2k_DATA (0x7FF << 8) +#define REG_DATA_COUNT_4k_DATA (0xFFF << 8) +#define REG_DATA_COUNT_DATA_1 (0x0 << 8) +#define REG_DATA_COUNT_DATA_2 (0x1 << 8) +#define REG_DATA_COUNT_DATA_3 (0x2 << 8) +#define REG_DATA_COUNT_DATA_4 (0x3 << 8) +#define REG_DATA_COUNT_DATA_5 (0x4 << 8) +#define REG_DATA_COUNT_DATA_6 (0x5 << 8) +#define REG_DATA_COUNT_DATA_7 (0x6 << 8) +#define REG_DATA_COUNT_DATA_8 (0x7 << 8) +#define REG_OOB_COUNT_EMPTY (0x3ff << 22) + +/* Bit field in FLASH_FLASH_ACCESS_START */ +#define NFLASH_GO BIT(0) +#define NFLASH_FIFO_REQ BIT(2) +#define NFLASH_RD BIT(13) +#define NFLASH_WT (BIT(12) | BIT(13)) + +/* Bit field in FLASH_NF_ECC_RESET */ +#define RESET_NFLASH_RESET BIT(2) +#define RESET_NFLASH_FIFO BIT(1) +#define RESET_NFLASH_ECC BIT(0) +#define ECC_RESET_ALL \ + RESET_NFLASH_RESET | RESET_NFLASH_FIFO | RESET_NFLASH_ECC + +/* Bit field in FLASH_NF_ECC_CONTROL */ +#define ENABLE_ECC_GENERATION BIT(8) +#define DISABLE_ECC_GENERATION (0 << 8) + +/* Flash FIFO control */ +#define FIFO_READ 2 +#define FIFO_WRITE 3 + +/* NFLASH INTERRUPT */ +#define REGIRQ_CLEAR BIT(0) +#define F_ADDR_ERR 2 + +/* BCH ECC field definition */ +#define BCH_COMPARE BIT(0) +#define BCH_ENABLE BIT(8) +#define BCH_DISABLE (0 << 8) +#define BCH_DECODE BIT(1) +#define BCH_ENCODE (0 << 1) +#define BCH_DECO_DONE BIT(30) +#define BCH_GEN_DONE BIT(31) +#define BCH_UNCORRECTABLE 0x3 +#define BCH_CORRECTABLE_ERR 0x2 +#define BCH_NO_ERR 0x1 +#define BCH_BUSY 0x0 +#define BCH_ERR_MASK 0x3 +#define BCH_ERR_NUM_MASK 0x3F +#define BCH_ERR_LOC_MASK 0x3FFF +#define BCH_CORRECT_LOC_MASK 0x7 +#define BCH_ERR_CAP_8 (0x0 << 9) +#define BCH_ERR_CAP_16 (0x1 << 9) +#define BCH_ERR_CAP_24 (0x2 << 9) +#define BCH_ERR_CAP_40 (0x3 << 9) + +#define BCH_GF_PARAM_M 14 + +struct nand_ctlr { + /* Cortina NAND controller register */ + u32 flash_id; + u32 flash_timeout; + u32 flash_status; + u32 flash_type; + u32 flash_flash_access_start; + u32 flash_flash_interrupt; + u32 flash_flash_mask; + u32 flash_fifo_control; + u32 flash_fifo_status; + u32 flash_fifo_address; + u32 flash_fifo_match_address; + u32 flash_fifo_data; + u32 flash_sf_access; + u32 flash_sf_ext_access; + u32 flash_sf_address; + u32 flash_sf_data; + u32 flash_sf_timing; + u32 resv[3]; + u32 flash_pf_access; // offset 0x050 + u32 flash_pf_timing; + u32 resv1[2]; + u32 flash_nf_access; // offset 0x060 + u32 flash_nf_count; + u32 flash_nf_command; + u32 flash_nf_address_1; + u32 flash_nf_address_2; + u32 flash_nf_data; + u32 flash_nf_timing; + u32 flash_nf_ecc_status; + u32 flash_nf_ecc_control; + u32 flash_nf_ecc_oob; + u32 flash_nf_ecc_gen0; + u32 resv3[15]; + u32 flash_nf_ecc_reset; // offset 0x0c8 + u32 flash_nf_bch_control; + u32 flash_nf_bch_status; + u32 flash_nf_bch_error_loc01; + u32 resv4[19]; + u32 flash_nf_bch_oob0; // offset 0x124 + u32 resv5[17]; + u32 flash_nf_bch_gen0_0; // offset 0x16c +}; + +/* Definition for DMA bitfield */ +#define TX_DMA_ENABLE BIT(0) +#define RX_DMA_ENABLE BIT(0) +#define DMA_CHECK_OWNER BIT(1) +#define OWN_DMA 0 +#define OWN_CPU 1 + +#define CA_DMA_DEPTH 3 +#define CA_DMA_DESC_NUM (BIT(0) << CA_DMA_DEPTH) +#define CA_DMA_Q_PTR_MASK 0x1fff + +struct dma_q_base_depth_t { + u32 depth : 4 ; /* bits 3:0 */ + u32 base : 28 ; /* bits 31:4 */ +}; + +struct tx_descriptor_t { + unsigned int buf_adr; /* Buff addr */ + unsigned int buf_adr_hi : 8 ; /* bits 7:0 */ + unsigned int buf_len : 16 ; /* bits 23:8 */ + unsigned int sgm : 1 ; /* bits 24 */ + unsigned int rsrvd : 6 ; /* bits 30:25 */ + unsigned int own : 1 ; /* bits 31:31 */ +}; + +struct rx_descriptor_t { + unsigned int buf_adr; /* Buff addr */ + unsigned int buf_adr_hi : 8 ; /* bits 7:0 */ + unsigned int buf_len : 16 ; /* bits 23:8 */ + unsigned int rsrvd : 7 ; /* bits 30:24 */ + unsigned int own : 1 ; /* bits 31:31 */ +}; + +struct dma_global { + u32 dma_glb_dma_lso_ctrl; + u32 dma_glb_lso_interrupt; + u32 dma_glb_lso_intenable; + u32 dma_glb_dma_lso_vlan_tag_type0; + u32 dma_glb_dma_lso_vlan_tag_type1; + u32 dma_glb_dma_lso_axi_user_sel0; + u32 dma_glb_axi_user_pat0; + u32 dma_glb_axi_user_pat1; + u32 dma_glb_axi_user_pat2; + u32 dma_glb_axi_user_pat3; + u32 dma_glb_fast_reg_pe0; + u32 dma_glb_fast_reg_pe1; + u32 dma_glb_dma_lso_tx_fdes_addr0; + u32 dma_glb_dma_lso_tx_fdes_addr1; + u32 dma_glb_dma_lso_tx_cdes_addr0; + u32 dma_glb_dma_lso_tx_cdes_addr1; + u32 dma_glb_dma_lso_tx_des_word0; + u32 dma_glb_dma_lso_tx_des_word1; + u32 dma_glb_dma_lso_lso_para_word0; + u32 dma_glb_dma_lso_lso_para_word1; + u32 dma_glb_dma_lso_debug0; + u32 dma_glb_dma_lso_debug1; + u32 dma_glb_dma_lso_debug2; + u32 dma_glb_dma_lso_spare0; + u32 dma_glb_dma_lso_spare1; + u32 dma_glb_dma_ssp_rx_ctrl; + u32 dma_glb_dma_ssp_tx_ctrl; + u32 dma_glb_dma_ssp_axi_user_sel0; + u32 dma_glb_dma_ssp_axi_user_sel1; + u32 dma_glb_dma_ssp_rx_fdes_addr0; + u32 dma_glb_dma_ssp_rx_fdes_addr1; + u32 dma_glb_dma_ssp_rx_cdes_addr0; + u32 dma_glb_dma_ssp_rx_cdes_addr1; + u32 dma_glb_dma_ssp_rx_des_word0; + u32 dma_glb_dma_ssp_rx_des_word1; + u32 dma_glb_dma_ssp_tx_fdes_addr0; + u32 dma_glb_dma_ssp_tx_fdes_addr1; + u32 dma_glb_dma_ssp_tx_cdes_addr0; + u32 dma_glb_dma_ssp_tx_cdes_addr1; + u32 dma_glb_dma_ssp_tx_des_word0; + u32 dma_glb_dma_ssp_tx_des_word1; + u32 dma_glb_dma_ssp_debug0; + u32 dma_glb_dma_ssp_debug1; + u32 dma_glb_dma_ssp_debug2; + u32 dma_glb_dma_ssp_spare0; + u32 dma_glb_dma_ssp_spare1; +}; + +struct dma_ssp { + u32 dma_q_rxq_control; + u32 dma_q_rxq_base_depth; + u32 dma_q_rxq_base; + u32 dma_q_rxq_wptr; + u32 dma_q_rxq_rptr; + u32 dma_q_rxq_pktcnt; + u32 dma_q_txq_control; + u32 dma_q_txq_base_depth; + u32 dma_q_txq_base; + u32 dma_q_txq_wptr; + u32 dma_q_txq_rptr; + u32 dma_q_txq_pktcnt; + u32 dma_q_rxq_interrupt; + u32 dma_q_rxq_intenable; + u32 dma_q_txq_interrupt; + u32 dma_q_txq_intenable; + u32 dma_q_rxq_misc_interrupt; + u32 dma_q_rxq_misc_intenable; + u32 dma_q_txq_misc_interrupt; + u32 dma_q_txq_misc_intenable; + u32 dma_q_rxq_coal_interrupt; + u32 dma_q_rxq_coal_intenable; + u32 dma_q_txq_coal_interrupt; + u32 dma_q_txq_coal_intenable; + u32 dma_q_rxq_frag_buff_addr0; + u32 dma_q_rxq_frag_buff_addr1; + u32 dma_q_rxq_frag_buff_size; + u32 dma_q_txq_frag_buff_addr0; + u32 dma_q_txq_frag_buff_addr1; + u32 dma_q_txq_frag_buff_size; + u32 dma_q_dma_spare_0; + u32 dma_q_dma_spare_1; +}; diff --git a/drivers/mtd/nand/raw/stm32_fmc2_nand.c b/drivers/mtd/nand/raw/stm32_fmc2_nand.c index b8561b2516c..fd81a9500b8 100644 --- a/drivers/mtd/nand/raw/stm32_fmc2_nand.c +++ b/drivers/mtd/nand/raw/stm32_fmc2_nand.c @@ -4,12 +4,15 @@ * Author: Christophe Kerello <christophe.kerello@st.com> */ +#define LOG_CATEGORY UCLASS_MTD + #include <common.h> #include <clk.h> #include <dm.h> #include <log.h> #include <nand.h> #include <reset.h> +#include <dm/device_compat.h> #include <linux/bitfield.h> #include <linux/bitops.h> #include <linux/delay.h> @@ -324,7 +327,7 @@ static int stm32_fmc2_nfc_ham_calculate(struct mtd_info *mtd, const u8 *data, ret = readl_poll_timeout(nfc->io_base + FMC2_SR, sr, sr & FMC2_SR_NWRF, FMC2_TIMEOUT_5S); if (ret < 0) { - pr_err("Ham timeout\n"); + log_err("Ham timeout\n"); return ret; } @@ -409,7 +412,7 @@ static int stm32_fmc2_nfc_bch_calculate(struct mtd_info *mtd, const u8 *data, ret = readl_poll_timeout(nfc->io_base + FMC2_BCHISR, bchisr, bchisr & FMC2_BCHISR_EPBRF, FMC2_TIMEOUT_5S); if (ret < 0) { - pr_err("Bch timeout\n"); + log_err("Bch timeout\n"); return ret; } @@ -457,7 +460,7 @@ static int stm32_fmc2_nfc_bch_correct(struct mtd_info *mtd, u8 *dat, ret = readl_poll_timeout(nfc->io_base + FMC2_BCHISR, bchisr, bchisr & FMC2_BCHISR_DERF, FMC2_TIMEOUT_5S); if (ret < 0) { - pr_err("Bch timeout\n"); + log_err("Bch timeout\n"); return ret; } @@ -795,26 +798,24 @@ static int stm32_fmc2_nfc_parse_child(struct stm32_fmc2_nfc *nfc, ofnode node) nand->ncs /= sizeof(u32); if (!nand->ncs) { - pr_err("Invalid reg property size\n"); + log_err("Invalid reg property size\n"); return -EINVAL; } ret = ofnode_read_u32_array(node, "reg", cs, nand->ncs); if (ret < 0) { - pr_err("Could not retrieve reg property\n"); + log_err("Could not retrieve reg property\n"); return -EINVAL; } for (i = 0; i < nand->ncs; i++) { if (cs[i] >= FMC2_MAX_CE) { - pr_err("Invalid reg value: %d\n", - nand->cs_used[i]); + log_err("Invalid reg value: %d\n", nand->cs_used[i]); return -EINVAL; } if (nfc->cs_assigned & BIT(cs[i])) { - pr_err("Cs already assigned: %d\n", - nand->cs_used[i]); + log_err("Cs already assigned: %d\n", nand->cs_used[i]); return -EINVAL; } @@ -837,12 +838,12 @@ static int stm32_fmc2_nfc_parse_dt(struct udevice *dev, nchips++; if (!nchips) { - pr_err("NAND chip not defined\n"); + log_err("NAND chip not defined\n"); return -EINVAL; } if (nchips > 1) { - pr_err("Too many NAND chips defined\n"); + log_err("Too many NAND chips defined\n"); return -EINVAL; } @@ -918,24 +919,21 @@ static int stm32_fmc2_nfc_probe(struct udevice *dev) addr = dev_read_addr_index(dev, mem_region); if (addr == FDT_ADDR_T_NONE) { - pr_err("Resource data_base not found for cs%d", - chip_cs); + dev_err(dev, "Resource data_base not found for cs%d", chip_cs); return ret; } nfc->data_base[chip_cs] = addr; addr = dev_read_addr_index(dev, mem_region + 1); if (addr == FDT_ADDR_T_NONE) { - pr_err("Resource cmd_base not found for cs%d", - chip_cs); + dev_err(dev, "Resource cmd_base not found for cs%d", chip_cs); return ret; } nfc->cmd_base[chip_cs] = addr; addr = dev_read_addr_index(dev, mem_region + 2); if (addr == FDT_ADDR_T_NONE) { - pr_err("Resource addr_base not found for cs%d", - chip_cs); + dev_err(dev, "Resource addr_base not found for cs%d", chip_cs); return ret; } nfc->addr_base[chip_cs] = addr; @@ -985,14 +983,14 @@ static int stm32_fmc2_nfc_probe(struct udevice *dev) * ECC sector size = 512 */ if (chip->ecc.mode != NAND_ECC_HW) { - pr_err("Nand_ecc_mode is not well defined in the DT\n"); + dev_err(dev, "Nand_ecc_mode is not well defined in the DT\n"); return -EINVAL; } ret = nand_check_ecc_caps(chip, &stm32_fmc2_nfc_ecc_caps, mtd->oobsize - FMC2_BBM_LEN); if (ret) { - pr_err("No valid ECC settings set\n"); + dev_err(dev, "No valid ECC settings set\n"); return ret; } @@ -1045,6 +1043,6 @@ void board_nand_init(void) DM_DRIVER_GET(stm32_fmc2_nfc), &dev); if (ret && ret != -ENODEV) - pr_err("Failed to initialize STM32 FMC2 NFC controller. (error %d)\n", - ret); + log_err("Failed to initialize STM32 FMC2 NFC controller. (error %d)\n", + ret); } diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index 45a1648ad50..944412958d6 100644 --- a/drivers/net/dwc_eth_qos.c +++ b/drivers/net/dwc_eth_qos.c @@ -209,6 +209,7 @@ struct eqos_dma_regs { #define EQOS_DMA_SYSBUS_MODE_BLEN8 BIT(2) #define EQOS_DMA_SYSBUS_MODE_BLEN4 BIT(1) +#define EQOS_DMA_CH0_CONTROL_DSL_SHIFT 18 #define EQOS_DMA_CH0_CONTROL_PBLX8 BIT(16) #define EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT 16 @@ -239,37 +240,15 @@ struct eqos_tegra186_regs { #define EQOS_AUTO_CAL_STATUS_ACTIVE BIT(31) /* Descriptors */ - -#define EQOS_DESCRIPTOR_WORDS 4 -#define EQOS_DESCRIPTOR_SIZE (EQOS_DESCRIPTOR_WORDS * 4) /* We assume ARCH_DMA_MINALIGN >= 16; 16 is the EQOS HW minimum */ #define EQOS_DESCRIPTOR_ALIGN ARCH_DMA_MINALIGN #define EQOS_DESCRIPTORS_TX 4 #define EQOS_DESCRIPTORS_RX 4 #define EQOS_DESCRIPTORS_NUM (EQOS_DESCRIPTORS_TX + EQOS_DESCRIPTORS_RX) -#define EQOS_DESCRIPTORS_SIZE ALIGN(EQOS_DESCRIPTORS_NUM * \ - EQOS_DESCRIPTOR_SIZE, ARCH_DMA_MINALIGN) #define EQOS_BUFFER_ALIGN ARCH_DMA_MINALIGN #define EQOS_MAX_PACKET_SIZE ALIGN(1568, ARCH_DMA_MINALIGN) #define EQOS_RX_BUFFER_SIZE (EQOS_DESCRIPTORS_RX * EQOS_MAX_PACKET_SIZE) -/* - * Warn if the cache-line size is larger than the descriptor size. In such - * cases the driver will likely fail because the CPU needs to flush the cache - * when requeuing RX buffers, therefore descriptors written by the hardware - * may be discarded. Architectures with full IO coherence, such as x86, do not - * experience this issue, and hence are excluded from this condition. - * - * This can be fixed by defining CONFIG_SYS_NONCACHED_MEMORY which will cause - * the driver to allocate descriptors from a pool of non-cached memory. - */ -#if EQOS_DESCRIPTOR_SIZE < ARCH_DMA_MINALIGN -#if !defined(CONFIG_SYS_NONCACHED_MEMORY) && \ - !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_X86) -#warning Cache line size is larger than descriptor size -#endif -#endif - struct eqos_desc { u32 des0; u32 des1; @@ -282,12 +261,17 @@ struct eqos_desc { #define EQOS_DESC3_LD BIT(28) #define EQOS_DESC3_BUF1V BIT(24) +#define EQOS_AXI_WIDTH_32 4 +#define EQOS_AXI_WIDTH_64 8 +#define EQOS_AXI_WIDTH_128 16 + struct eqos_config { bool reg_access_always_ok; int mdio_wait; int swr_wait; int config_mac; int config_mac_mdio; + unsigned int axi_bus_width; phy_interface_t (*interface)(struct udevice *dev); struct eqos_ops *ops; }; @@ -330,9 +314,8 @@ struct eqos_priv { int phyaddr; u32 max_speed; void *descs; - struct eqos_desc *tx_descs; - struct eqos_desc *rx_descs; int tx_desc_idx, rx_desc_idx; + unsigned int desc_size; void *tx_dma_buf; void *rx_dma_buf; void *rx_pkt; @@ -358,63 +341,42 @@ struct eqos_priv { * not have the same constraints since they are 1536 bytes large, so they * are unlikely to share cache-lines. */ -static void *eqos_alloc_descs(unsigned int num) +static void *eqos_alloc_descs(struct eqos_priv *eqos, unsigned int num) { -#ifdef CONFIG_SYS_NONCACHED_MEMORY - return (void *)noncached_alloc(EQOS_DESCRIPTORS_SIZE, - EQOS_DESCRIPTOR_ALIGN); -#else - return memalign(EQOS_DESCRIPTOR_ALIGN, EQOS_DESCRIPTORS_SIZE); -#endif + eqos->desc_size = ALIGN(sizeof(struct eqos_desc), + (unsigned int)ARCH_DMA_MINALIGN); + + return memalign(eqos->desc_size, num * eqos->desc_size); } static void eqos_free_descs(void *descs) { -#ifdef CONFIG_SYS_NONCACHED_MEMORY - /* FIXME: noncached_alloc() has no opposite */ -#else free(descs); -#endif } -static void eqos_inval_desc_tegra186(void *desc) +static struct eqos_desc *eqos_get_desc(struct eqos_priv *eqos, + unsigned int num, bool rx) { -#ifndef CONFIG_SYS_NONCACHED_MEMORY - unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1); - unsigned long end = ALIGN(start + EQOS_DESCRIPTOR_SIZE, - ARCH_DMA_MINALIGN); - - invalidate_dcache_range(start, end); -#endif + return eqos->descs + + ((rx ? EQOS_DESCRIPTORS_TX : 0) + num) * eqos->desc_size; } static void eqos_inval_desc_generic(void *desc) { -#ifndef CONFIG_SYS_NONCACHED_MEMORY - unsigned long start = rounddown((unsigned long)desc, ARCH_DMA_MINALIGN); - unsigned long end = roundup((unsigned long)desc + EQOS_DESCRIPTOR_SIZE, - ARCH_DMA_MINALIGN); + unsigned long start = (unsigned long)desc; + unsigned long end = ALIGN(start + sizeof(struct eqos_desc), + ARCH_DMA_MINALIGN); invalidate_dcache_range(start, end); -#endif -} - -static void eqos_flush_desc_tegra186(void *desc) -{ -#ifndef CONFIG_SYS_NONCACHED_MEMORY - flush_cache((unsigned long)desc, EQOS_DESCRIPTOR_SIZE); -#endif } static void eqos_flush_desc_generic(void *desc) { -#ifndef CONFIG_SYS_NONCACHED_MEMORY - unsigned long start = rounddown((unsigned long)desc, ARCH_DMA_MINALIGN); - unsigned long end = roundup((unsigned long)desc + EQOS_DESCRIPTOR_SIZE, - ARCH_DMA_MINALIGN); + unsigned long start = (unsigned long)desc; + unsigned long end = ALIGN(start + sizeof(struct eqos_desc), + ARCH_DMA_MINALIGN); flush_dcache_range(start, end); -#endif } static void eqos_inval_buffer_tegra186(void *buf, size_t size) @@ -1167,6 +1129,7 @@ static int eqos_start(struct udevice *dev) ulong rate; u32 val, tx_fifo_sz, rx_fifo_sz, tqs, rqs, pbl; ulong last_rx_desc; + ulong desc_pad; debug("%s(dev=%p):\n", __func__, dev); @@ -1405,8 +1368,12 @@ static int eqos_start(struct udevice *dev) EQOS_MAX_PACKET_SIZE << EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT); + desc_pad = (eqos->desc_size - sizeof(struct eqos_desc)) / + eqos->config->axi_bus_width; + setbits_le32(&eqos->dma_regs->ch0_control, - EQOS_DMA_CH0_CONTROL_PBLX8); + EQOS_DMA_CH0_CONTROL_PBLX8 | + (desc_pad << EQOS_DMA_CH0_CONTROL_DSL_SHIFT)); /* * Burst length must be < 1/2 FIFO size. @@ -1435,9 +1402,15 @@ static int eqos_start(struct udevice *dev) /* Set up descriptors */ - memset(eqos->descs, 0, EQOS_DESCRIPTORS_SIZE); + memset(eqos->descs, 0, eqos->desc_size * EQOS_DESCRIPTORS_NUM); + + for (i = 0; i < EQOS_DESCRIPTORS_TX; i++) { + struct eqos_desc *tx_desc = eqos_get_desc(eqos, i, false); + eqos->config->ops->eqos_flush_desc(tx_desc); + } + for (i = 0; i < EQOS_DESCRIPTORS_RX; i++) { - struct eqos_desc *rx_desc = &(eqos->rx_descs[i]); + struct eqos_desc *rx_desc = eqos_get_desc(eqos, i, true); rx_desc->des0 = (u32)(ulong)(eqos->rx_dma_buf + (i * EQOS_MAX_PACKET_SIZE)); rx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_BUF1V; @@ -1449,12 +1422,14 @@ static int eqos_start(struct udevice *dev) } writel(0, &eqos->dma_regs->ch0_txdesc_list_haddress); - writel((ulong)eqos->tx_descs, &eqos->dma_regs->ch0_txdesc_list_address); + writel((ulong)eqos_get_desc(eqos, 0, false), + &eqos->dma_regs->ch0_txdesc_list_address); writel(EQOS_DESCRIPTORS_TX - 1, &eqos->dma_regs->ch0_txdesc_ring_length); writel(0, &eqos->dma_regs->ch0_rxdesc_list_haddress); - writel((ulong)eqos->rx_descs, &eqos->dma_regs->ch0_rxdesc_list_address); + writel((ulong)eqos_get_desc(eqos, 0, true), + &eqos->dma_regs->ch0_rxdesc_list_address); writel(EQOS_DESCRIPTORS_RX - 1, &eqos->dma_regs->ch0_rxdesc_ring_length); @@ -1473,7 +1448,7 @@ static int eqos_start(struct udevice *dev) * that's not distinguishable from none of the descriptors being * available. */ - last_rx_desc = (ulong)&(eqos->rx_descs[(EQOS_DESCRIPTORS_RX - 1)]); + last_rx_desc = (ulong)eqos_get_desc(eqos, EQOS_DESCRIPTORS_RX - 1, true); writel(last_rx_desc, &eqos->dma_regs->ch0_rxdesc_tail_pointer); eqos->started = true; @@ -1558,7 +1533,7 @@ static int eqos_send(struct udevice *dev, void *packet, int length) memcpy(eqos->tx_dma_buf, packet, length); eqos->config->ops->eqos_flush_buffer(eqos->tx_dma_buf, length); - tx_desc = &(eqos->tx_descs[eqos->tx_desc_idx]); + tx_desc = eqos_get_desc(eqos, eqos->tx_desc_idx, false); eqos->tx_desc_idx++; eqos->tx_desc_idx %= EQOS_DESCRIPTORS_TX; @@ -1573,7 +1548,7 @@ static int eqos_send(struct udevice *dev, void *packet, int length) tx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_FD | EQOS_DESC3_LD | length; eqos->config->ops->eqos_flush_desc(tx_desc); - writel((ulong)(&(eqos->tx_descs[eqos->tx_desc_idx])), + writel((ulong)eqos_get_desc(eqos, eqos->tx_desc_idx, false), &eqos->dma_regs->ch0_txdesc_tail_pointer); for (i = 0; i < 1000000; i++) { @@ -1596,7 +1571,7 @@ static int eqos_recv(struct udevice *dev, int flags, uchar **packetp) debug("%s(dev=%p, flags=%x):\n", __func__, dev, flags); - rx_desc = &(eqos->rx_descs[eqos->rx_desc_idx]); + rx_desc = eqos_get_desc(eqos, eqos->rx_desc_idx, true); eqos->config->ops->eqos_inval_desc(rx_desc); if (rx_desc->des3 & EQOS_DESC3_OWN) { debug("%s: RX packet not available\n", __func__); @@ -1631,7 +1606,7 @@ static int eqos_free_pkt(struct udevice *dev, uchar *packet, int length) eqos->config->ops->eqos_inval_buffer(packet, length); - rx_desc = &(eqos->rx_descs[eqos->rx_desc_idx]); + rx_desc = eqos_get_desc(eqos, eqos->rx_desc_idx, true); rx_desc->des0 = 0; mb(); @@ -1663,17 +1638,12 @@ static int eqos_probe_resources_core(struct udevice *dev) debug("%s(dev=%p):\n", __func__, dev); - eqos->descs = eqos_alloc_descs(EQOS_DESCRIPTORS_TX + - EQOS_DESCRIPTORS_RX); + eqos->descs = eqos_alloc_descs(eqos, EQOS_DESCRIPTORS_NUM); if (!eqos->descs) { debug("%s: eqos_alloc_descs() failed\n", __func__); ret = -ENOMEM; goto err; } - eqos->tx_descs = (struct eqos_desc *)eqos->descs; - eqos->rx_descs = (eqos->tx_descs + EQOS_DESCRIPTORS_TX); - debug("%s: tx_descs=%p, rx_descs=%p\n", __func__, eqos->tx_descs, - eqos->rx_descs); eqos->tx_dma_buf = memalign(EQOS_BUFFER_ALIGN, EQOS_MAX_PACKET_SIZE); if (!eqos->tx_dma_buf) { @@ -2083,8 +2053,8 @@ static const struct eth_ops eqos_ops = { }; static struct eqos_ops eqos_tegra186_ops = { - .eqos_inval_desc = eqos_inval_desc_tegra186, - .eqos_flush_desc = eqos_flush_desc_tegra186, + .eqos_inval_desc = eqos_inval_desc_generic, + .eqos_flush_desc = eqos_flush_desc_generic, .eqos_inval_buffer = eqos_inval_buffer_tegra186, .eqos_flush_buffer = eqos_flush_buffer_tegra186, .eqos_probe_resources = eqos_probe_resources_tegra186, @@ -2105,6 +2075,7 @@ static const struct eqos_config __maybe_unused eqos_tegra186_config = { .swr_wait = 10, .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB, .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_20_35, + .axi_bus_width = EQOS_AXI_WIDTH_128, .interface = eqos_get_interface_tegra186, .ops = &eqos_tegra186_ops }; @@ -2132,6 +2103,7 @@ static const struct eqos_config __maybe_unused eqos_stm32_config = { .swr_wait = 50, .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV, .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300, + .axi_bus_width = EQOS_AXI_WIDTH_64, .interface = eqos_get_interface_stm32, .ops = &eqos_stm32_ops }; @@ -2159,6 +2131,7 @@ struct eqos_config __maybe_unused eqos_imx_config = { .swr_wait = 50, .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB, .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300, + .axi_bus_width = EQOS_AXI_WIDTH_64, .interface = eqos_get_interface_imx, .ops = &eqos_imx_ops }; diff --git a/drivers/net/dwmac_socfpga.c b/drivers/net/dwmac_socfpga.c index 939f199b1fe..82fdff51dac 100644 --- a/drivers/net/dwmac_socfpga.c +++ b/drivers/net/dwmac_socfpga.c @@ -6,6 +6,8 @@ */ #include <common.h> +#include <asm/arch/secure_reg_helper.h> +#include <asm/arch/system_manager.h> #include <asm/io.h> #include <dm.h> #include <clk.h> @@ -17,8 +19,6 @@ #include <dm/device_compat.h> #include <linux/err.h> -#include <asm/arch/system_manager.h> - struct dwmac_socfpga_plat { struct dw_eth_pdata dw_eth_pdata; void *phy_intf; @@ -64,6 +64,32 @@ static int dwmac_socfpga_of_to_plat(struct udevice *dev) return designware_eth_of_to_plat(dev); } +static int dwmac_socfpga_do_setphy(struct udevice *dev, u32 modereg) +{ + struct dwmac_socfpga_plat *pdata = dev_get_plat(dev); + u32 modemask = SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << pdata->reg_shift; + +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF) + u32 index = ((u64)pdata->phy_intf - socfpga_get_sysmgr_addr() - + SYSMGR_SOC64_EMAC0) >> 2; + + u32 id = SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC0 + index; + + int ret = socfpga_secure_reg_update32(id, + modemask, + modereg << pdata->reg_shift); + if (ret) { + dev_err(dev, "Failed to set PHY register via SMC call\n"); + return ret; + } +#else + clrsetbits_le32(pdata->phy_intf, modemask, + modereg << pdata->reg_shift); +#endif + + return 0; +} + static int dwmac_socfpga_probe(struct udevice *dev) { struct dwmac_socfpga_plat *pdata = dev_get_plat(dev); @@ -71,7 +97,6 @@ static int dwmac_socfpga_probe(struct udevice *dev) struct reset_ctl_bulk reset_bulk; int ret; u32 modereg; - u32 modemask; switch (edata->phy_interface) { case PHY_INTERFACE_MODE_MII: @@ -97,9 +122,9 @@ static int dwmac_socfpga_probe(struct udevice *dev) reset_assert_bulk(&reset_bulk); - modemask = SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << pdata->reg_shift; - clrsetbits_le32(pdata->phy_intf, modemask, - modereg << pdata->reg_shift); + ret = dwmac_socfpga_do_setphy(dev, modereg); + if (ret) + return ret; reset_release_bulk(&reset_bulk); diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c index 3b3dd104cde..733588302db 100644 --- a/drivers/net/e1000.c +++ b/drivers/net/e1000.c @@ -869,7 +869,6 @@ e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset, return E1000_SUCCESS; } -#ifndef CONFIG_DM_ETH /****************************************************************************** * e1000_write_eeprom_srwr - Write to Shadow Ram using EEWR * @hw: pointer to the HW structure @@ -1035,7 +1034,6 @@ static int32_t e1000_update_eeprom_checksum_i210(struct e1000_hw *hw) out: return ret_val; } -#endif /****************************************************************************** * Verifies that the EEPROM has a valid checksum @@ -5660,13 +5658,24 @@ e1000_poll(struct eth_device *nic) return len ? 1 : 0; } +#endif /* !CONFIG_DM_ETH */ +#ifdef CONFIG_DM_ETH +static int e1000_write_hwaddr(struct udevice *dev) +#else static int e1000_write_hwaddr(struct eth_device *dev) +#endif { #ifndef CONFIG_E1000_NO_NVM - unsigned char *mac = dev->enetaddr; unsigned char current_mac[6]; +#ifdef CONFIG_DM_ETH + struct eth_pdata *plat = dev_get_plat(dev); + struct e1000_hw *hw = dev_get_priv(dev); + u8 *mac = plat->enetaddr; +#else struct e1000_hw *hw = dev->priv; + u8 *mac = dev->enetaddr; +#endif uint16_t data[3]; int ret_val, i; @@ -5700,6 +5709,7 @@ static int e1000_write_hwaddr(struct eth_device *dev) #endif } +#ifndef CONFIG_DM_ETH /************************************************************************** PROBE - Look for an adapter, this routine's visible to the outside You should omit the last argument struct pci_device * for a non-PCI NIC @@ -5926,6 +5936,7 @@ static const struct eth_ops e1000_eth_ops = { .recv = e1000_eth_recv, .stop = e1000_eth_stop, .free_pkt = e1000_free_pkt, + .write_hwaddr = e1000_write_hwaddr, }; static const struct udevice_id e1000_eth_ids[] = { diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c index 69e299d6a3d..0687230b4bb 100644 --- a/drivers/net/ftgmac100.c +++ b/drivers/net/ftgmac100.c @@ -271,6 +271,28 @@ static int ftgmac100_set_mac(struct ftgmac100_data *priv, } /* + * Get MAC address + */ +static int ftgmac100_get_mac(struct ftgmac100_data *priv, + unsigned char *mac) +{ + struct ftgmac100 *ftgmac100 = priv->iobase; + unsigned int maddr = readl(&ftgmac100->mac_madr); + unsigned int laddr = readl(&ftgmac100->mac_ladr); + + debug("%s(%x %x)\n", __func__, maddr, laddr); + + mac[0] = (maddr >> 8) & 0xff; + mac[1] = maddr & 0xff; + mac[2] = (laddr >> 24) & 0xff; + mac[3] = (laddr >> 16) & 0xff; + mac[4] = (laddr >> 8) & 0xff; + mac[5] = laddr & 0xff; + + return 0; +} + +/* * disable transmitter, receiver */ static void ftgmac100_stop(struct udevice *dev) @@ -511,6 +533,14 @@ static int ftgmac100_write_hwaddr(struct udevice *dev) return ftgmac100_set_mac(priv, pdata->enetaddr); } +static int ftgmac_read_hwaddr(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_plat(dev); + struct ftgmac100_data *priv = dev_get_priv(dev); + + return ftgmac100_get_mac(priv, pdata->enetaddr); +} + static int ftgmac100_of_to_plat(struct udevice *dev) { struct eth_pdata *pdata = dev_get_plat(dev); @@ -571,6 +601,8 @@ static int ftgmac100_probe(struct udevice *dev) goto out; } + ftgmac_read_hwaddr(dev); + out: if (ret) clk_release_bulk(&priv->clks); diff --git a/drivers/net/ks8851_mll.c b/drivers/net/ks8851_mll.c index 91c2d10ffc8..9dd9b33955a 100644 --- a/drivers/net/ks8851_mll.c +++ b/drivers/net/ks8851_mll.c @@ -251,7 +251,8 @@ static int ks_rcv(struct ks_net *ks, uchar *data) } ks_wrreg16(ks, KS_RXQCR, RXQCR_CMD_CNTL | RXQCR_RRXEF); - printf(DRIVERNAME ": bad packet\n"); + printf(DRIVERNAME ": bad packet (sts=0x%04x len=0x%04x)\n", sts, len); + ks->rxfc = 0; return 0; } diff --git a/drivers/net/macb.c b/drivers/net/macb.c index e287c29e69f..2225b33ff65 100644 --- a/drivers/net/macb.c +++ b/drivers/net/macb.c @@ -83,7 +83,16 @@ struct macb_dma_desc { u32 ctrl; }; -#define DMA_DESC_BYTES(n) (n * sizeof(struct macb_dma_desc)) +struct macb_dma_desc_64 { + u32 addrh; + u32 unused; +}; + +#define HW_DMA_CAP_32B 0 +#define HW_DMA_CAP_64B 1 + +#define DMA_DESC_SIZE 16 +#define DMA_DESC_BYTES(n) ((n) * DMA_DESC_SIZE) #define MACB_TX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_TX_RING_SIZE)) #define MACB_RX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_RX_RING_SIZE)) #define MACB_TX_DUMMY_DMA_DESC_SIZE (DMA_DESC_BYTES(1)) @@ -137,6 +146,7 @@ struct macb_device { struct macb_config { unsigned int dma_burst_length; + unsigned int hw_dma_cap; int (*clk_init)(struct udevice *dev, ulong rate); }; @@ -307,6 +317,24 @@ static inline void macb_invalidate_rx_buffer(struct macb_device *macb) #if defined(CONFIG_CMD_NET) +static struct macb_dma_desc_64 *macb_64b_desc(struct macb_dma_desc *desc) +{ + return (struct macb_dma_desc_64 *)((void *)desc + + sizeof(struct macb_dma_desc)); +} + +static void macb_set_addr(struct macb_device *macb, struct macb_dma_desc *desc, + ulong addr) +{ + struct macb_dma_desc_64 *desc_64; + + if (macb->config->hw_dma_cap & HW_DMA_CAP_64B) { + desc_64 = macb_64b_desc(desc); + desc_64->addrh = upper_32_bits(addr); + } + desc->addr = lower_32_bits(addr); +} + static int _macb_send(struct macb_device *macb, const char *name, void *packet, int length) { @@ -325,8 +353,12 @@ static int _macb_send(struct macb_device *macb, const char *name, void *packet, macb->tx_head++; } + if (macb->config->hw_dma_cap & HW_DMA_CAP_64B) + tx_head = tx_head * 2; + macb->tx_ring[tx_head].ctrl = ctrl; - macb->tx_ring[tx_head].addr = paddr; + macb_set_addr(macb, &macb->tx_ring[tx_head], paddr); + barrier(); macb_flush_ring_desc(macb, TX); macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART)); @@ -363,19 +395,28 @@ static void reclaim_rx_buffers(struct macb_device *macb, unsigned int new_tail) { unsigned int i; + unsigned int count; i = macb->rx_tail; macb_invalidate_ring_desc(macb, RX); while (i > new_tail) { - macb->rx_ring[i].addr &= ~MACB_BIT(RX_USED); + if (macb->config->hw_dma_cap & HW_DMA_CAP_64B) + count = i * 2; + else + count = i; + macb->rx_ring[count].addr &= ~MACB_BIT(RX_USED); i++; if (i > MACB_RX_RING_SIZE) i = 0; } while (i < new_tail) { - macb->rx_ring[i].addr &= ~MACB_BIT(RX_USED); + if (macb->config->hw_dma_cap & HW_DMA_CAP_64B) + count = i * 2; + else + count = i; + macb->rx_ring[count].addr &= ~MACB_BIT(RX_USED); i++; } @@ -390,16 +431,25 @@ static int _macb_recv(struct macb_device *macb, uchar **packetp) void *buffer; int length; u32 status; + u8 flag = false; macb->wrapped = false; for (;;) { macb_invalidate_ring_desc(macb, RX); + if (macb->config->hw_dma_cap & HW_DMA_CAP_64B) + next_rx_tail = next_rx_tail * 2; + if (!(macb->rx_ring[next_rx_tail].addr & MACB_BIT(RX_USED))) return -EAGAIN; status = macb->rx_ring[next_rx_tail].ctrl; if (status & MACB_BIT(RX_SOF)) { + if (macb->config->hw_dma_cap & HW_DMA_CAP_64B) { + next_rx_tail = next_rx_tail / 2; + flag = true; + } + if (next_rx_tail != macb->rx_tail) reclaim_rx_buffers(macb, next_rx_tail); macb->wrapped = false; @@ -426,11 +476,22 @@ static int _macb_recv(struct macb_device *macb, uchar **packetp) *packetp = buffer; } + if (macb->config->hw_dma_cap & HW_DMA_CAP_64B) { + if (!flag) + next_rx_tail = next_rx_tail / 2; + } + if (++next_rx_tail >= MACB_RX_RING_SIZE) next_rx_tail = 0; macb->next_rx_tail = next_rx_tail; return length; } else { + if (macb->config->hw_dma_cap & HW_DMA_CAP_64B) { + if (!flag) + next_rx_tail = next_rx_tail / 2; + flag = false; + } + if (++next_rx_tail >= MACB_RX_RING_SIZE) { macb->wrapped = true; next_rx_tail = 0; @@ -470,6 +531,12 @@ static int macb_phy_find(struct macb_device *macb, const char *name) int i; u16 phy_id; + phy_id = macb_mdio_read(macb, macb->phy_addr, MII_PHYSID1); + if (phy_id != 0xffff) { + printf("%s: PHY present at %d\n", name, macb->phy_addr); + return 0; + } + /* Search for PHY... */ for (i = 0; i < 32; i++) { macb->phy_addr = i; @@ -718,6 +785,7 @@ static int gmac_init_multi_queues(struct macb_device *macb) { int i, num_queues = 1; u32 queue_mask; + unsigned long paddr; /* bit 0 is never set but queue 0 always exists */ queue_mask = gem_readl(macb, DCFG6) & 0xff; @@ -731,10 +799,18 @@ static int gmac_init_multi_queues(struct macb_device *macb) macb->dummy_desc->addr = 0; flush_dcache_range(macb->dummy_desc_dma, macb->dummy_desc_dma + ALIGN(MACB_TX_DUMMY_DMA_DESC_SIZE, PKTALIGN)); - - for (i = 1; i < num_queues; i++) - gem_writel_queue_TBQP(macb, macb->dummy_desc_dma, i - 1); - + paddr = macb->dummy_desc_dma; + + for (i = 1; i < num_queues; i++) { + gem_writel_queue_TBQP(macb, lower_32_bits(paddr), i - 1); + gem_writel_queue_RBQP(macb, lower_32_bits(paddr), i - 1); + if (macb->config->hw_dma_cap & HW_DMA_CAP_64B) { + gem_writel_queue_TBQPH(macb, upper_32_bits(paddr), + i - 1); + gem_writel_queue_RBQPH(macb, upper_32_bits(paddr), + i - 1); + } + } return 0; } @@ -760,6 +836,9 @@ static void gmac_configure_dma(struct macb_device *macb) dmacfg &= ~GEM_BIT(ENDIA_DESC); dmacfg &= ~GEM_BIT(ADDR64); + if (macb->config->hw_dma_cap & HW_DMA_CAP_64B) + dmacfg |= GEM_BIT(ADDR64); + gem_writel(macb, DMACFG, dmacfg); } @@ -775,6 +854,7 @@ static int _macb_init(struct macb_device *macb, const char *name) unsigned long paddr; int ret; int i; + int count; /* * macb_halt should have been called at some point before now, @@ -786,20 +866,28 @@ static int _macb_init(struct macb_device *macb, const char *name) for (i = 0; i < MACB_RX_RING_SIZE; i++) { if (i == (MACB_RX_RING_SIZE - 1)) paddr |= MACB_BIT(RX_WRAP); - macb->rx_ring[i].addr = paddr; - macb->rx_ring[i].ctrl = 0; + if (macb->config->hw_dma_cap & HW_DMA_CAP_64B) + count = i * 2; + else + count = i; + macb->rx_ring[count].ctrl = 0; + macb_set_addr(macb, &macb->rx_ring[count], paddr); paddr += macb->rx_buffer_size; } macb_flush_ring_desc(macb, RX); macb_flush_rx_buffer(macb); for (i = 0; i < MACB_TX_RING_SIZE; i++) { - macb->tx_ring[i].addr = 0; + if (macb->config->hw_dma_cap & HW_DMA_CAP_64B) + count = i * 2; + else + count = i; + macb_set_addr(macb, &macb->tx_ring[count], 0); if (i == (MACB_TX_RING_SIZE - 1)) - macb->tx_ring[i].ctrl = MACB_BIT(TX_USED) | + macb->tx_ring[count].ctrl = MACB_BIT(TX_USED) | MACB_BIT(TX_WRAP); else - macb->tx_ring[i].ctrl = MACB_BIT(TX_USED); + macb->tx_ring[count].ctrl = MACB_BIT(TX_USED); } macb_flush_ring_desc(macb, TX); @@ -812,8 +900,12 @@ static int _macb_init(struct macb_device *macb, const char *name) gem_writel(macb, DMACFG, MACB_ZYNQ_GEM_DMACR_INIT); #endif - macb_writel(macb, RBQP, macb->rx_ring_dma); - macb_writel(macb, TBQP, macb->tx_ring_dma); + macb_writel(macb, RBQP, lower_32_bits(macb->rx_ring_dma)); + macb_writel(macb, TBQP, lower_32_bits(macb->tx_ring_dma)); + if (macb->config->hw_dma_cap & HW_DMA_CAP_64B) { + macb_writel(macb, RBQPH, upper_32_bits(macb->rx_ring_dma)); + macb_writel(macb, TBQPH, upper_32_bits(macb->tx_ring_dma)); + } if (macb_is_gem(macb)) { /* Initialize DMA properties */ @@ -1217,6 +1309,7 @@ static int macb_enable_clk(struct udevice *dev) static const struct macb_config default_gem_config = { .dma_burst_length = 16, + .hw_dma_cap = HW_DMA_CAP_32B, .clk_init = NULL, }; @@ -1224,11 +1317,12 @@ static int macb_eth_probe(struct udevice *dev) { struct eth_pdata *pdata = dev_get_plat(dev); struct macb_device *macb = dev_get_priv(dev); + struct ofnode_phandle_args phandle_args; const char *phy_mode; int ret; - phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode", - NULL); + phy_mode = dev_read_prop(dev, "phy-mode", NULL); + if (phy_mode) macb->phy_interface = phy_get_interface_by_name(phy_mode); if (macb->phy_interface == -1) { @@ -1236,6 +1330,12 @@ static int macb_eth_probe(struct udevice *dev) return -EINVAL; } + /* Read phyaddr from DT */ + if (!dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, + &phandle_args)) + macb->phy_addr = ofnode_read_u32_default(phandle_args.node, + "reg", -1); + macb->regs = (void *)pdata->iobase; macb->is_big_endian = (cpu_to_be32(0x12345678) == 0x12345678); @@ -1304,13 +1404,21 @@ static int macb_eth_of_to_plat(struct udevice *dev) return macb_late_eth_of_to_plat(dev); } +static const struct macb_config microchip_config = { + .dma_burst_length = 16, + .hw_dma_cap = HW_DMA_CAP_64B, + .clk_init = NULL, +}; + static const struct macb_config sama5d4_config = { .dma_burst_length = 4, + .hw_dma_cap = HW_DMA_CAP_32B, .clk_init = NULL, }; static const struct macb_config sifive_config = { .dma_burst_length = 16, + .hw_dma_cap = HW_DMA_CAP_32B, .clk_init = macb_sifive_clk_init, }; @@ -1324,6 +1432,8 @@ static const struct udevice_id macb_eth_ids[] = { { .compatible = "cdns,zynq-gem" }, { .compatible = "sifive,fu540-c000-gem", .data = (ulong)&sifive_config }, + { .compatible = "microchip,mpfs-mss-gem", + .data = (ulong)µchip_config }, { } }; diff --git a/drivers/net/macb.h b/drivers/net/macb.h index 9b16383eba4..72b84ae96ed 100644 --- a/drivers/net/macb.h +++ b/drivers/net/macb.h @@ -768,5 +768,11 @@ #define GEM_RX_CSUM_CHECKED_MASK 2 #define gem_writel_queue_TBQP(port, value, queue_num) \ writel((value), (port)->regs + GEM_TBQP(queue_num)) +#define gem_writel_queue_TBQPH(port, value, queue_num) \ + writel((value), (port)->regs + GEM_TBQPH(queue_num)) +#define gem_writel_queue_RBQP(port, value, queue_num) \ + writel((value), (port)->regs + GEM_RBQP(queue_num)) +#define gem_writel_queue_RBQPH(port, value, queue_num) \ + writel((value), (port)->regs + GEM_RBQPH(queue_num)) #endif /* __DRIVERS_MACB_H__ */ diff --git a/drivers/net/phy/miiphybb.c b/drivers/net/phy/miiphybb.c index ba97a54c067..59a32c49130 100644 --- a/drivers/net/phy/miiphybb.c +++ b/drivers/net/phy/miiphybb.c @@ -105,7 +105,7 @@ int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) / sizeof(bb_miiphy_buses[0]); #endif -void bb_miiphy_init(void) +int bb_miiphy_init(void) { int i; @@ -124,6 +124,8 @@ void bb_miiphy_init(void) bb_miiphy_buses[i].init(&bb_miiphy_buses[i]); } } + + return 0; } static inline struct bb_miiphy_bus *bb_miiphy_getbus(const char *devname) diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 65498bce1d9..b1de38f7662 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -281,6 +281,15 @@ config PCIE_ROCKCHIP Say Y here if you want to enable PCIe controller support on Rockchip SoCs. +config PCIE_DW_ROCKCHIP + bool "Rockchip DesignWare based PCIe controller" + depends on ARCH_ROCKCHIP + select DM_PCI + select PHY_ROCKCHIP_SNPS_PCIE3 + help + Say Y here if you want to enable DW PCIe controller support on + Rockchip SoCs. + config PCI_BRCMSTB bool "Broadcom STB PCIe controller" depends on DM_PCI diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index 8b4d49a5903..5ed94bc95c2 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -48,5 +48,6 @@ obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o obj-$(CONFIG_PCI_KEYSTONE) += pcie_dw_ti.o obj-$(CONFIG_PCIE_MEDIATEK) += pcie_mediatek.o obj-$(CONFIG_PCIE_ROCKCHIP) += pcie_rockchip.o +obj-$(CONFIG_PCIE_DW_ROCKCHIP) += pcie_dw_rockchip.o obj-$(CONFIG_PCI_BRCMSTB) += pcie_brcmstb.o obj-$(CONFIG_PCI_OCTEONTX) += pci_octeontx.o diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index 4cdd06b1257..ba65f47e808 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -1842,7 +1842,7 @@ U_BOOT_DRIVER(pci_generic_drv) = { .of_match = pci_generic_ids, }; -void pci_init(void) +int pci_init(void) { struct udevice *bus; @@ -1855,4 +1855,6 @@ void pci_init(void) uclass_next_device_check(&bus)) { ; } + + return 0; } diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 664e8379eb5..a7453e57552 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -454,16 +454,18 @@ int pci_hose_scan(struct pci_controller *hose) return pci_hose_scan_bus(hose, hose->current_busno); } -void pci_init(void) +int pci_init(void) { hose_head = NULL; /* allow env to disable pci init/enum */ if (env_get("pcidisable") != NULL) - return; + return 0; /* now call board specific pci_init()... */ pci_init_board(); + + return 0; } /* Returns the address of the requested capability structure within the diff --git a/drivers/pci/pcie_dw_rockchip.c b/drivers/pci/pcie_dw_rockchip.c new file mode 100644 index 00000000000..15270627b0d --- /dev/null +++ b/drivers/pci/pcie_dw_rockchip.c @@ -0,0 +1,877 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Rockchip DesignWare based PCIe host controller driver + * + * Copyright (c) 2021 Rockchip, Inc. + */ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <generic-phy.h> +#include <pci.h> +#include <power-domain.h> +#include <reset.h> +#include <syscon.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/io.h> +#include <asm-generic/gpio.h> +#include <dm/device_compat.h> +#include <linux/iopoll.h> +#include <linux/delay.h> +#include <power/regulator.h> + +DECLARE_GLOBAL_DATA_PTR; + +/** + * struct rk_pcie - RK DW PCIe controller state + * + * @vpcie3v3: The 3.3v power supply for slot + * @dbi_base: The base address of dwc core regs + * @apb_base: The base address of vendor regs + * @cfg_base: The base address of config header space + * @cfg_size: The size of the configuration space which is needed + * as it gets written into the PCIE_ATU_LIMIT register + * @first_busno: This driver supports multiple PCIe controllers. + * first_busno stores the bus number of the PCIe root-port + * number which may vary depending on the PCIe setup + * (PEX switches etc). + * @rst_gpio: The #PERST signal for slot + * @io: The IO space for EP's BAR + * @mem: The memory space for EP's BAR + */ +struct rk_pcie { + struct udevice *dev; + struct udevice *vpcie3v3; + void *dbi_base; + void *apb_base; + void *cfg_base; + fdt_size_t cfg_size; + struct phy phy; + struct clk_bulk clks; + int first_busno; + struct reset_ctl_bulk rsts; + struct gpio_desc rst_gpio; + struct pci_region io; + struct pci_region mem; +}; + +/* Parameters for the waiting for iATU enabled routine */ +#define PCIE_CLIENT_GENERAL_DEBUG 0x104 +#define PCIE_CLIENT_HOT_RESET_CTRL 0x180 +#define PCIE_LTSSM_ENABLE_ENHANCE BIT(4) +#define PCIE_CLIENT_LTSSM_STATUS 0x300 +#define SMLH_LINKUP BIT(16) +#define RDLH_LINKUP BIT(17) +#define PCIE_CLIENT_DBG_FIFO_MODE_CON 0x310 +#define PCIE_CLIENT_DBG_FIFO_PTN_HIT_D0 0x320 +#define PCIE_CLIENT_DBG_FIFO_PTN_HIT_D1 0x324 +#define PCIE_CLIENT_DBG_FIFO_TRN_HIT_D0 0x328 +#define PCIE_CLIENT_DBG_FIFO_TRN_HIT_D1 0x32c +#define PCIE_CLIENT_DBG_FIFO_STATUS 0x350 +#define PCIE_CLIENT_DBG_TRANSITION_DATA 0xffff0000 +#define PCIE_CLIENT_DBF_EN 0xffff0003 + +/* PCI DBICS registers */ +#define PCIE_LINK_STATUS_REG 0x80 +#define PCIE_LINK_STATUS_SPEED_OFF 16 +#define PCIE_LINK_STATUS_SPEED_MASK (0xf << PCIE_LINK_STATUS_SPEED_OFF) +#define PCIE_LINK_STATUS_WIDTH_OFF 20 +#define PCIE_LINK_STATUS_WIDTH_MASK (0xf << PCIE_LINK_STATUS_WIDTH_OFF) + +#define PCIE_LINK_CAPABILITY 0x7c +#define PCIE_LINK_CTL_2 0xa0 +#define TARGET_LINK_SPEED_MASK 0xf +#define LINK_SPEED_GEN_1 0x1 +#define LINK_SPEED_GEN_2 0x2 +#define LINK_SPEED_GEN_3 0x3 + +#define PCIE_MISC_CONTROL_1_OFF 0x8bc +#define PCIE_DBI_RO_WR_EN BIT(0) + +#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80c +#define PORT_LOGIC_SPEED_CHANGE BIT(17) + +/* + * iATU Unroll-specific register definitions + * From 4.80 core version the address translation will be made by unroll. + * The registers are offset from atu_base + */ +#define PCIE_ATU_UNR_REGION_CTRL1 0x00 +#define PCIE_ATU_UNR_REGION_CTRL2 0x04 +#define PCIE_ATU_UNR_LOWER_BASE 0x08 +#define PCIE_ATU_UNR_UPPER_BASE 0x0c +#define PCIE_ATU_UNR_LIMIT 0x10 +#define PCIE_ATU_UNR_LOWER_TARGET 0x14 +#define PCIE_ATU_UNR_UPPER_TARGET 0x18 + +#define PCIE_ATU_REGION_INDEX1 (0x1 << 0) +#define PCIE_ATU_REGION_INDEX0 (0x0 << 0) +#define PCIE_ATU_TYPE_MEM (0x0 << 0) +#define PCIE_ATU_TYPE_IO (0x2 << 0) +#define PCIE_ATU_TYPE_CFG0 (0x4 << 0) +#define PCIE_ATU_TYPE_CFG1 (0x5 << 0) +#define PCIE_ATU_ENABLE (0x1 << 31) +#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30) +#define PCIE_ATU_BUS(x) (((x) & 0xff) << 24) +#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19) +#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) + +/* Register address builder */ +#define PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(region) \ + ((0x3 << 20) | ((region) << 9)) + +/* Parameters for the waiting for iATU enabled routine */ +#define LINK_WAIT_MAX_IATU_RETRIES 5 +#define LINK_WAIT_IATU_US 10000 + +/* Parameters for the waiting for #perst signal */ +#define PERST_WAIT_MS 1000 + +static int rk_pcie_read(void __iomem *addr, int size, u32 *val) +{ + if ((uintptr_t)addr & (size - 1)) { + *val = 0; + return PCIBIOS_UNSUPPORTED; + } + + if (size == 4) { + *val = readl(addr); + } else if (size == 2) { + *val = readw(addr); + } else if (size == 1) { + *val = readb(addr); + } else { + *val = 0; + return -ENODEV; + } + + return 0; +} + +static int rk_pcie_write(void __iomem *addr, int size, u32 val) +{ + if ((uintptr_t)addr & (size - 1)) + return PCIBIOS_UNSUPPORTED; + + if (size == 4) + writel(val, addr); + else if (size == 2) + writew(val, addr); + else if (size == 1) + writeb(val, addr); + else + return -ENODEV; + + return 0; +} + +static u32 __rk_pcie_read_apb(struct rk_pcie *rk_pcie, void __iomem *base, + u32 reg, size_t size) +{ + int ret; + u32 val; + + ret = rk_pcie_read(base + reg, size, &val); + if (ret) + dev_err(rk_pcie->dev, "Read APB address failed\n"); + + return val; +} + +static void __rk_pcie_write_apb(struct rk_pcie *rk_pcie, void __iomem *base, + u32 reg, size_t size, u32 val) +{ + int ret; + + ret = rk_pcie_write(base + reg, size, val); + if (ret) + dev_err(rk_pcie->dev, "Write APB address failed\n"); +} + +/** + * rk_pcie_readl_apb() - Read vendor regs + * + * @rk_pcie: Pointer to the PCI controller state + * @reg: Offset of regs + */ +static inline u32 rk_pcie_readl_apb(struct rk_pcie *rk_pcie, u32 reg) +{ + return __rk_pcie_read_apb(rk_pcie, rk_pcie->apb_base, reg, 0x4); +} + +/** + * rk_pcie_writel_apb() - Write vendor regs + * + * @rk_pcie: Pointer to the PCI controller state + * @reg: Offset of regs + * @val: Value to be writen + */ +static inline void rk_pcie_writel_apb(struct rk_pcie *rk_pcie, u32 reg, + u32 val) +{ + __rk_pcie_write_apb(rk_pcie, rk_pcie->apb_base, reg, 0x4, val); +} + +static int rk_pcie_get_link_speed(struct rk_pcie *rk_pcie) +{ + return (readl(rk_pcie->dbi_base + PCIE_LINK_STATUS_REG) & + PCIE_LINK_STATUS_SPEED_MASK) >> PCIE_LINK_STATUS_SPEED_OFF; +} + +static int rk_pcie_get_link_width(struct rk_pcie *rk_pcie) +{ + return (readl(rk_pcie->dbi_base + PCIE_LINK_STATUS_REG) & + PCIE_LINK_STATUS_WIDTH_MASK) >> PCIE_LINK_STATUS_WIDTH_OFF; +} + +static void rk_pcie_writel_ob_unroll(struct rk_pcie *rk_pcie, u32 index, + u32 reg, u32 val) +{ + u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index); + void __iomem *base = rk_pcie->dbi_base; + + writel(val, base + offset + reg); +} + +static u32 rk_pcie_readl_ob_unroll(struct rk_pcie *rk_pcie, u32 index, u32 reg) +{ + u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index); + void __iomem *base = rk_pcie->dbi_base; + + return readl(base + offset + reg); +} + +static inline void rk_pcie_dbi_write_enable(struct rk_pcie *rk_pcie, bool en) +{ + u32 val; + + val = readl(rk_pcie->dbi_base + PCIE_MISC_CONTROL_1_OFF); + + if (en) + val |= PCIE_DBI_RO_WR_EN; + else + val &= ~PCIE_DBI_RO_WR_EN; + writel(val, rk_pcie->dbi_base + PCIE_MISC_CONTROL_1_OFF); +} + +/** + * rockchip_pcie_setup_host() - Setup the PCIe controller for RC opertaion + * + * @rk_pcie: Pointer to the PCI controller state + * + * Configure the host BARs of the PCIe controller root port so that + * PCI(e) devices may access the system memory. + */ +static void rk_pcie_setup_host(struct rk_pcie *rk_pcie) +{ + u32 val; + + rk_pcie_dbi_write_enable(rk_pcie, true); + + /* setup RC BARs */ + writel(PCI_BASE_ADDRESS_MEM_TYPE_64, + rk_pcie->dbi_base + PCI_BASE_ADDRESS_0); + writel(0x0, rk_pcie->dbi_base + PCI_BASE_ADDRESS_1); + + /* setup interrupt pins */ + clrsetbits_le32(rk_pcie->dbi_base + PCI_INTERRUPT_LINE, + 0xff00, 0x100); + + /* setup bus numbers */ + clrsetbits_le32(rk_pcie->dbi_base + PCI_PRIMARY_BUS, + 0xffffff, 0x00ff0100); + + /* setup command register */ + clrsetbits_le32(rk_pcie->dbi_base + PCI_PRIMARY_BUS, + 0xffff, + PCI_COMMAND_IO | PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER | PCI_COMMAND_SERR); + + /* program correct class for RC */ + writew(PCI_CLASS_BRIDGE_PCI, rk_pcie->dbi_base + PCI_CLASS_DEVICE); + /* Better disable write permission right after the update */ + + setbits_le32(rk_pcie->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL, + PORT_LOGIC_SPEED_CHANGE) + + rk_pcie_dbi_write_enable(rk_pcie, false); +} + +/** + * rk_pcie_configure() - Configure link capabilities and speed + * + * @rk_pcie: Pointer to the PCI controller state + * @cap_speed: The capabilities and speed to configure + * + * Configure the link capabilities and speed in the PCIe root complex. + */ +static void rk_pcie_configure(struct rk_pcie *pci, u32 cap_speed) +{ + u32 val; + + rk_pcie_dbi_write_enable(pci, true); + + clrsetbits_le32(pci->dbi_base + PCIE_LINK_CAPABILITY, + TARGET_LINK_SPEED_MASK, cap_speed); + + clrsetbits_le32(pci->dbi_base + PCIE_LINK_CTL_2, + TARGET_LINK_SPEED_MASK, cap_speed); + + rk_pcie_dbi_write_enable(pci, false); +} + +/** + * rk_pcie_dw_prog_outbound_atu_unroll() - Configure ATU for outbound accesses + * + * @rk_pcie: Pointer to the PCI controller state + * @index: ATU region index + * @type: ATU accsess type + * @cpu_addr: the physical address for the translation entry + * @pci_addr: the pcie bus address for the translation entry + * @size: the size of the translation entry + * + * Return: 0 is successful and -1 is failure + */ +static int rk_pcie_prog_outbound_atu_unroll(struct rk_pcie *pci, int index, + int type, u64 cpu_addr, + u64 pci_addr, u32 size) +{ + u32 retries, val; + + dev_dbg(pci->dev, "ATU programmed with: index: %d, type: %d, cpu addr: %8llx, pci addr: %8llx, size: %8x\n", + index, type, cpu_addr, pci_addr, size); + + rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_BASE, + lower_32_bits(cpu_addr)); + rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_BASE, + upper_32_bits(cpu_addr)); + rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LIMIT, + lower_32_bits(cpu_addr + size - 1)); + rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET, + lower_32_bits(pci_addr)); + rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET, + upper_32_bits(pci_addr)); + rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1, + type); + rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2, + PCIE_ATU_ENABLE); + + /* + * Make sure ATU enable takes effect before any subsequent config + * and I/O accesses. + */ + for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) { + val = rk_pcie_readl_ob_unroll(pci, index, + PCIE_ATU_UNR_REGION_CTRL2); + if (val & PCIE_ATU_ENABLE) + return 0; + + udelay(LINK_WAIT_IATU_US); + } + dev_err(pci->dev, "outbound iATU is not being enabled\n"); + + return -1; +} + +/** + * rk_pcie_dw_addr_valid() - Check for valid bus address + * + * @d: The PCI device to access + * @first_busno: Bus number of the PCIe controller root complex + * + * Return 1 (true) if the PCI device can be accessed by this controller. + * + * Return: 1 on valid, 0 on invalid + */ +static int rk_pcie_addr_valid(pci_dev_t d, int first_busno) +{ + if ((PCI_BUS(d) == first_busno) && (PCI_DEV(d) > 0)) + return 0; + if ((PCI_BUS(d) == first_busno + 1) && (PCI_DEV(d) > 0)) + return 0; + + return 1; +} + +/** + * set_cfg_address() - Configure the PCIe controller config space access + * + * @rk_pcie: Pointer to the PCI controller state + * @d: PCI device to access + * @where: Offset in the configuration space + * + * Configures the PCIe controller to access the configuration space of + * a specific PCIe device and returns the address to use for this + * access. + * + * Return: Address that can be used to access the configation space + * of the requested device / offset + */ +static uintptr_t set_cfg_address(struct rk_pcie *pcie, + pci_dev_t d, uint where) +{ + int rel_bus = PCI_BUS(d) - pcie->first_busno; + uintptr_t va_address; + u32 atu_type; + int ret; + + /* Use dbi_base for own configuration read and write */ + if (!rel_bus) { + va_address = (uintptr_t)pcie->dbi_base; + goto out; + } + + if (rel_bus == 1) + /* + * For local bus whose primary bus number is root bridge, + * change TLP Type field to 4. + */ + atu_type = PCIE_ATU_TYPE_CFG0; + else + /* Otherwise, change TLP Type field to 5. */ + atu_type = PCIE_ATU_TYPE_CFG1; + + /* + * Not accessing root port configuration space? + * Region #0 is used for Outbound CFG space access. + * Direction = Outbound + * Region Index = 0 + */ + d = PCI_MASK_BUS(d); + d = PCI_ADD_BUS(rel_bus, d); + ret = rk_pcie_prog_outbound_atu_unroll(pcie, PCIE_ATU_REGION_INDEX1, + atu_type, (u64)pcie->cfg_base, + d << 8, pcie->cfg_size); + if (ret) + return (uintptr_t)ret; + + va_address = (uintptr_t)pcie->cfg_base; + +out: + va_address += where & ~0x3; + + return va_address; +} + +/** + * rockchip_pcie_rd_conf() - Read from configuration space + * + * @bus: Pointer to the PCI bus + * @bdf: Identifies the PCIe device to access + * @offset: The offset into the device's configuration space + * @valuep: A pointer at which to store the read value + * @size: Indicates the size of access to perform + * + * Read a value of size @size from offset @offset within the configuration + * space of the device identified by the bus, device & function numbers in @bdf + * on the PCI bus @bus. + * + * Return: 0 on success + */ +static int rockchip_pcie_rd_conf(const struct udevice *bus, pci_dev_t bdf, + uint offset, ulong *valuep, + enum pci_size_t size) +{ + struct rk_pcie *pcie = dev_get_priv(bus); + uintptr_t va_address; + ulong value; + + debug("PCIE CFG read: bdf=%2x:%2x:%2x\n", + PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf)); + + if (!rk_pcie_addr_valid(bdf, pcie->first_busno)) { + debug("- out of range\n"); + *valuep = pci_get_ff(size); + return 0; + } + + va_address = set_cfg_address(pcie, bdf, offset); + + value = readl(va_address); + + debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value); + *valuep = pci_conv_32_to_size(value, offset, size); + + return rk_pcie_prog_outbound_atu_unroll(pcie, + PCIE_ATU_REGION_INDEX1, + PCIE_ATU_TYPE_IO, + pcie->io.phys_start, + pcie->io.bus_start, + pcie->io.size); +} + +/** + * rockchip_pcie_wr_conf() - Write to configuration space + * + * @bus: Pointer to the PCI bus + * @bdf: Identifies the PCIe device to access + * @offset: The offset into the device's configuration space + * @value: The value to write + * @size: Indicates the size of access to perform + * + * Write the value @value of size @size from offset @offset within the + * configuration space of the device identified by the bus, device & function + * numbers in @bdf on the PCI bus @bus. + * + * Return: 0 on success + */ +static int rockchip_pcie_wr_conf(struct udevice *bus, pci_dev_t bdf, + uint offset, ulong value, + enum pci_size_t size) +{ + struct rk_pcie *pcie = dev_get_priv(bus); + uintptr_t va_address; + ulong old; + + debug("PCIE CFG write: (b,d,f)=(%2d,%2d,%2d)\n", + PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf)); + debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value); + + if (!rk_pcie_addr_valid(bdf, pcie->first_busno)) { + debug("- out of range\n"); + return 0; + } + + va_address = set_cfg_address(pcie, bdf, offset); + + old = readl(va_address); + value = pci_conv_size_to_32(old, value, offset, size); + writel(value, va_address); + + return rk_pcie_prog_outbound_atu_unroll(pcie, + PCIE_ATU_REGION_INDEX1, + PCIE_ATU_TYPE_IO, + pcie->io.phys_start, + pcie->io.bus_start, + pcie->io.size); + +} + +static void rk_pcie_enable_debug(struct rk_pcie *rk_pcie) +{ + rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_PTN_HIT_D0, + PCIE_CLIENT_DBG_TRANSITION_DATA); + rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_PTN_HIT_D1, + PCIE_CLIENT_DBG_TRANSITION_DATA); + rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_TRN_HIT_D0, + PCIE_CLIENT_DBG_TRANSITION_DATA); + rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_TRN_HIT_D1, + PCIE_CLIENT_DBG_TRANSITION_DATA); + rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_MODE_CON, + PCIE_CLIENT_DBF_EN); +} + +static void rk_pcie_debug_dump(struct rk_pcie *rk_pcie) +{ + u32 loop; + + debug("ltssm = 0x%x\n", + rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_LTSSM_STATUS)); + for (loop = 0; loop < 64; loop++) + debug("fifo_status = 0x%x\n", + rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_STATUS)); +} + +static inline void rk_pcie_link_status_clear(struct rk_pcie *rk_pcie) +{ + rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_GENERAL_DEBUG, 0x0); +} + +static inline void rk_pcie_disable_ltssm(struct rk_pcie *rk_pcie) +{ + rk_pcie_writel_apb(rk_pcie, 0x0, 0xc0008); +} + +static inline void rk_pcie_enable_ltssm(struct rk_pcie *rk_pcie) +{ + rk_pcie_writel_apb(rk_pcie, 0x0, 0xc000c); +} + +static int is_link_up(struct rk_pcie *priv) +{ + u32 val; + + val = rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS); + if ((val & (RDLH_LINKUP | SMLH_LINKUP)) == 0x30000 && + (val & GENMASK(5, 0)) == 0x11) + return 1; + + return 0; +} + +/** + * rk_pcie_link_up() - Wait for the link to come up + * + * @rk_pcie: Pointer to the PCI controller state + * @cap_speed: Desired link speed + * + * Return: 1 (true) for active line and negetive (false) for no link (timeout) + */ +static int rk_pcie_link_up(struct rk_pcie *priv, u32 cap_speed) +{ + int retries; + + if (is_link_up(priv)) { + printf("PCI Link already up before configuration!\n"); + return 1; + } + + /* DW pre link configurations */ + rk_pcie_configure(priv, cap_speed); + + /* Rest the device */ + if (dm_gpio_is_valid(&priv->rst_gpio)) { + dm_gpio_set_value(&priv->rst_gpio, 0); + /* + * Minimal is 100ms from spec but we see + * some wired devices need much more, such as 600ms. + * Add a enough delay to cover all cases. + */ + msleep(PERST_WAIT_MS); + dm_gpio_set_value(&priv->rst_gpio, 1); + } + + rk_pcie_disable_ltssm(priv); + rk_pcie_link_status_clear(priv); + rk_pcie_enable_debug(priv); + + /* Enable LTSSM */ + rk_pcie_enable_ltssm(priv); + + for (retries = 0; retries < 5; retries++) { + if (is_link_up(priv)) { + dev_info(priv->dev, "PCIe Link up, LTSSM is 0x%x\n", + rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS)); + rk_pcie_debug_dump(priv); + return 0; + } + + dev_info(priv->dev, "PCIe Linking... LTSSM is 0x%x\n", + rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS)); + rk_pcie_debug_dump(priv); + msleep(1000); + } + + dev_err(priv->dev, "PCIe-%d Link Fail\n", dev_seq(priv->dev)); + /* Link maybe in Gen switch recovery but we need to wait more 1s */ + msleep(1000); + return -EIO; +} + +static int rockchip_pcie_init_port(struct udevice *dev) +{ + int ret; + u32 val; + struct rk_pcie *priv = dev_get_priv(dev); + + /* Set power and maybe external ref clk input */ + if (priv->vpcie3v3) { + ret = regulator_set_value(priv->vpcie3v3, 3300000); + if (ret) { + dev_err(priv->dev, "failed to enable vpcie3v3 (ret=%d)\n", + ret); + return ret; + } + } + + msleep(1000); + + ret = generic_phy_init(&priv->phy); + if (ret) { + dev_err(dev, "failed to init phy (ret=%d)\n", ret); + return ret; + } + + ret = generic_phy_power_on(&priv->phy); + if (ret) { + dev_err(dev, "failed to power on phy (ret=%d)\n", ret); + goto err_exit_phy; + } + + ret = reset_deassert_bulk(&priv->rsts); + if (ret) { + dev_err(dev, "failed to deassert resets (ret=%d)\n", ret); + goto err_power_off_phy; + } + + ret = clk_enable_bulk(&priv->clks); + if (ret) { + dev_err(dev, "failed to enable clks (ret=%d)\n", ret); + goto err_deassert_bulk; + } + + /* LTSSM EN ctrl mode */ + val = rk_pcie_readl_apb(priv, PCIE_CLIENT_HOT_RESET_CTRL); + val |= PCIE_LTSSM_ENABLE_ENHANCE | (PCIE_LTSSM_ENABLE_ENHANCE << 16); + rk_pcie_writel_apb(priv, PCIE_CLIENT_HOT_RESET_CTRL, val); + + /* Set RC mode */ + rk_pcie_writel_apb(priv, 0x0, 0xf00040); + rk_pcie_setup_host(priv); + + ret = rk_pcie_link_up(priv, LINK_SPEED_GEN_3); + if (ret < 0) + goto err_link_up; + + return 0; +err_link_up: + clk_disable_bulk(&priv->clks); +err_deassert_bulk: + reset_assert_bulk(&priv->rsts); +err_power_off_phy: + generic_phy_power_off(&priv->phy); +err_exit_phy: + generic_phy_exit(&priv->phy); + + return ret; +} + +static int rockchip_pcie_parse_dt(struct udevice *dev) +{ + struct rk_pcie *priv = dev_get_priv(dev); + int ret; + + priv->dbi_base = (void *)dev_read_addr_index(dev, 0); + if (!priv->dbi_base) + return -ENODEV; + + dev_dbg(dev, "DBI address is 0x%p\n", priv->dbi_base); + + priv->apb_base = (void *)dev_read_addr_index(dev, 1); + if (!priv->apb_base) + return -ENODEV; + + dev_dbg(dev, "APB address is 0x%p\n", priv->apb_base); + + ret = gpio_request_by_name(dev, "reset-gpios", 0, + &priv->rst_gpio, GPIOD_IS_OUT); + if (ret) { + dev_err(dev, "failed to find reset-gpios property\n"); + return ret; + } + + ret = reset_get_bulk(dev, &priv->rsts); + if (ret) { + dev_err(dev, "Can't get reset: %d\n", ret); + return ret; + } + + ret = clk_get_bulk(dev, &priv->clks); + if (ret) { + dev_err(dev, "Can't get clock: %d\n", ret); + return ret; + } + + ret = device_get_supply_regulator(dev, "vpcie3v3-supply", + &priv->vpcie3v3); + if (ret && ret != -ENOENT) { + dev_err(dev, "failed to get vpcie3v3 supply (ret=%d)\n", ret); + return ret; + } + + ret = generic_phy_get_by_index(dev, 0, &priv->phy); + if (ret) { + dev_err(dev, "failed to get pcie phy (ret=%d)\n", ret); + return ret; + } + + return 0; +} + +/** + * rockchip_pcie_probe() - Probe the PCIe bus for active link + * + * @dev: A pointer to the device being operated on + * + * Probe for an active link on the PCIe bus and configure the controller + * to enable this port. + * + * Return: 0 on success, else -ENODEV + */ +static int rockchip_pcie_probe(struct udevice *dev) +{ + struct rk_pcie *priv = dev_get_priv(dev); + struct udevice *ctlr = pci_get_controller(dev); + struct pci_controller *hose = dev_get_uclass_priv(ctlr); + int reti = 0; + + priv->first_busno = dev_seq(dev); + priv->dev = dev; + + ret = rockchip_pcie_parse_dt(dev); + if (ret) + return ret; + + ret = rockchip_pcie_init_port(dev); + if (ret) + return ret; + + dev_info(dev, "PCIE-%d: Link up (Gen%d-x%d, Bus%d)\n", + dev_seq(dev), rk_pcie_get_link_speed(priv), + rk_pcie_get_link_width(priv), + hose->first_busno); + + for (ret = 0; ret < hose->region_count; ret++) { + if (hose->regions[ret].flags == PCI_REGION_IO) { + priv->io.phys_start = hose->regions[ret].phys_start; /* IO base */ + priv->io.bus_start = hose->regions[ret].bus_start; /* IO_bus_addr */ + priv->io.size = hose->regions[ret].size; /* IO size */ + } else if (hose->regions[ret].flags == PCI_REGION_MEM) { + priv->mem.phys_start = hose->regions[ret].phys_start; /* MEM base */ + priv->mem.bus_start = hose->regions[ret].bus_start; /* MEM_bus_addr */ + priv->mem.size = hose->regions[ret].size; /* MEM size */ + } else if (hose->regions[ret].flags == PCI_REGION_SYS_MEMORY) { + priv->cfg_base = (void *)(priv->io.phys_start - priv->io.size); + priv->cfg_size = priv->io.size; + } else { + dev_err(dev, "invalid flags type!\n"); + } + } + + dev_dbg(dev, "Config space: [0x%p - 0x%p, size 0x%llx]\n", + priv->cfg_base, priv->cfg_base + priv->cfg_size, + priv->cfg_size); + + dev_dbg(dev, "IO space: [0x%llx - 0x%llx, size 0x%lx]\n", + priv->io.phys_start, priv->io.phys_start + priv->io.size, + priv->io.size); + + dev_dbg(dev, "IO bus: [0x%lx - 0x%lx, size 0x%lx]\n", + priv->io.bus_start, priv->io.bus_start + priv->io.size, + priv->io.size); + + dev_dbg(dev, "MEM space: [0x%llx - 0x%llx, size 0x%lx]\n", + priv->mem.phys_start, priv->mem.phys_start + priv->mem.size, + priv->mem.size); + + dev_dbg(dev, "MEM bus: [0x%lx - 0x%lx, size 0x%lx]\n", + priv->mem.bus_start, priv->mem.bus_start + priv->mem.size, + priv->mem.size); + + return rk_pcie_prog_outbound_atu_unroll(priv, + PCIE_ATU_REGION_INDEX0, + PCIE_ATU_TYPE_MEM, + priv->mem.phys_start, + priv->mem.bus_start, + priv->mem.size); +} + +static const struct dm_pci_ops rockchip_pcie_ops = { + .read_config = rockchip_pcie_rd_conf, + .write_config = rockchip_pcie_wr_conf, +}; + +static const struct udevice_id rockchip_pcie_ids[] = { + { .compatible = "rockchip,rk3568-pcie" }, + { } +}; + +U_BOOT_DRIVER(rockchip_dw_pcie) = { + .name = "pcie_dw_rockchip", + .id = UCLASS_PCI, + .of_match = rockchip_pcie_ids, + .ops = &rockchip_pcie_ops, + .probe = rockchip_pcie_probe, + .priv_auto = sizeof(struct rk_pcie), +}; diff --git a/drivers/pci_endpoint/pci_ep-uclass.c b/drivers/pci_endpoint/pci_ep-uclass.c index 38a5f083769..aa89701de8f 100644 --- a/drivers/pci_endpoint/pci_ep-uclass.c +++ b/drivers/pci_endpoint/pci_ep-uclass.c @@ -210,7 +210,7 @@ UCLASS_DRIVER(pci_ep) = { .flags = DM_UC_FLAG_SEQ_ALIAS, }; -void pci_ep_init(void) +int pci_ep_init(void) { struct udevice *dev; @@ -219,4 +219,6 @@ void pci_ep_init(void) uclass_next_device_check(&dev)) { ; } + + return 0; } diff --git a/drivers/phy/phy-stm32-usbphyc.c b/drivers/phy/phy-stm32-usbphyc.c index f23aef4fb01..02d859a0398 100644 --- a/drivers/phy/phy-stm32-usbphyc.c +++ b/drivers/phy/phy-stm32-usbphyc.c @@ -3,6 +3,8 @@ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved */ +#define LOG_CATEGORY UCLASS_PHY + #include <common.h> #include <clk.h> #include <div64.h> @@ -98,8 +100,8 @@ static int stm32_usbphyc_pll_init(struct stm32_usbphyc *usbphyc) u32 usbphyc_pll; if ((clk_rate < PLL_INFF_MIN_RATE) || (clk_rate > PLL_INFF_MAX_RATE)) { - pr_debug("%s: input clk freq (%dHz) out of range\n", - __func__, clk_rate); + log_debug("input clk freq (%dHz) out of range\n", + clk_rate); return -EINVAL; } @@ -116,8 +118,8 @@ static int stm32_usbphyc_pll_init(struct stm32_usbphyc *usbphyc) writel(usbphyc_pll, usbphyc->base + STM32_USBPHYC_PLL); - pr_debug("%s: input clk freq=%dHz, ndiv=%d, frac=%d\n", __func__, - clk_rate, pll_params.ndiv, pll_params.frac); + log_debug("input clk freq=%dHz, ndiv=%d, frac=%d\n", + clk_rate, pll_params.ndiv, pll_params.frac); return 0; } @@ -154,7 +156,7 @@ static int stm32_usbphyc_phy_init(struct phy *phy) true : false; int ret; - pr_debug("%s phy ID = %lu\n", __func__, phy->id); + dev_dbg(phy->dev, "phy ID = %lu\n", phy->id); /* Check if one phy port has already configured the pll */ if (pllen && stm32_usbphyc_is_init(usbphyc)) goto initialized; @@ -200,7 +202,7 @@ static int stm32_usbphyc_phy_exit(struct phy *phy) struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id; int ret; - pr_debug("%s phy ID = %lu\n", __func__, phy->id); + dev_dbg(phy->dev, "phy ID = %lu\n", phy->id); usbphyc_phy->init = false; /* Check if other phy port requires pllen */ @@ -239,7 +241,7 @@ static int stm32_usbphyc_phy_power_on(struct phy *phy) struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id; int ret; - pr_debug("%s phy ID = %lu\n", __func__, phy->id); + dev_dbg(phy->dev, "phy ID = %lu\n", phy->id); if (usbphyc_phy->vdd) { ret = regulator_set_enable(usbphyc_phy->vdd, true); if (ret) @@ -262,7 +264,7 @@ static int stm32_usbphyc_phy_power_off(struct phy *phy) struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id; int ret; - pr_debug("%s phy ID = %lu\n", __func__, phy->id); + dev_dbg(phy->dev, "phy ID = %lu\n", phy->id); usbphyc_phy->powered = false; if (stm32_usbphyc_is_powered(usbphyc)) diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig index 2318e71f356..e477a6cd9e9 100644 --- a/drivers/phy/rockchip/Kconfig +++ b/drivers/phy/rockchip/Kconfig @@ -18,6 +18,15 @@ config PHY_ROCKCHIP_PCIE help Enable this to support the Rockchip PCIe PHY. +config PHY_ROCKCHIP_SNPS_PCIE3 + bool "Rockchip Snps PCIe3 PHY Driver" + depends on PHY && ARCH_ROCKCHIP + help + Support for Rockchip PCIe3 PHY with Synopsys IP block. + It could support PCIe Gen3 single root complex, and could + also be able splited into multiple combinations of lanes. + + config PHY_ROCKCHIP_TYPEC bool "Rockchip TYPEC PHY Driver" depends on ARCH_ROCKCHIP diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile index 44049154f9d..f6ad3bf59ae 100644 --- a/drivers/phy/rockchip/Makefile +++ b/drivers/phy/rockchip/Makefile @@ -5,4 +5,5 @@ obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-rockchip-pcie.o +obj-$(CONFIG_PHY_ROCKCHIP_SNPS_PCIE3) += phy-rockchip-snps-pcie3.o obj-$(CONFIG_PHY_ROCKCHIP_TYPEC) += phy-rockchip-typec.o diff --git a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c new file mode 100644 index 00000000000..5ae41fbeeec --- /dev/null +++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Rockchip PCIE3.0 phy driver + * + * Copyright (C) 2021 Rockchip Electronics Co., Ltd. + */ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <generic-phy.h> +#include <regmap.h> +#include <reset-uclass.h> +#include <syscon.h> +#include <asm/io.h> +#include <dm/device_compat.h> +#include <dm/lists.h> + +#define GRF_PCIE30PHY_CON1 0x4 +#define GRF_PCIE30PHY_CON6 0x18 +#define GRF_PCIE30PHY_CON9 0x24 + +/** + * struct rockchip_p3phy_priv - RK DW PCIe PHY state + * + * @mmio: The base address of PHY internal registers + * @phy_grf: The regmap for controlling pipe signal + * @p30phy: The reset signal for PHY + * @ref_clk_m: The reference clock of M for PHY + * @ref_clk_n: The reference clock of N for PHY + * @pclk: The clock for accessing PHY blocks + */ +struct rockchip_p3phy_priv { + void __iomem *mmio; + struct regmap *phy_grf; + struct reset_ctl p30phy; + struct clk ref_clk_m; + struct clk ref_clk_n; + struct clk pclk; +}; + +static int rochchip_p3phy_init(struct phy *phy) +{ + struct rockchip_p3phy_priv *priv = dev_get_priv(phy->dev); + int ret; + + ret = clk_enable(&priv->ref_clk_m); + if (ret < 0 && ret != -ENOSYS) + return ret; + + ret = clk_enable(&priv->ref_clk_n); + if (ret < 0 && ret != -ENOSYS) + goto err_ref; + + ret = clk_enable(&priv->pclk); + if (ret < 0 && ret != -ENOSYS) + goto err_pclk; + + reset_assert(&priv->p30phy); + udelay(1); + + /* Deassert PCIe PMA output clamp mode */ + regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9, + (0x1 << 15) | (0x1 << 31)); + + reset_deassert(&priv->p30phy); + udelay(1); + + return 0; +err_pclk: + clk_disable(&priv->ref_clk_n); +err_ref: + clk_disable(&priv->ref_clk_m); + + return ret; +} + +static int rochchip_p3phy_exit(struct phy *phy) +{ + struct rockchip_p3phy_priv *priv = dev_get_priv(phy->dev); + + clk_disable(&priv->ref_clk_m); + clk_disable(&priv->ref_clk_n); + clk_disable(&priv->pclk); + reset_assert(&priv->p30phy); + + return 0; +} + +static int rockchip_p3phy_probe(struct udevice *dev) +{ + struct rockchip_p3phy_priv *priv = dev_get_priv(dev); + struct udevice *syscon; + int ret; + + priv->mmio = (void __iomem *)dev_read_addr(dev); + if ((fdt_addr_t)priv->mmio == FDT_ADDR_T_NONE) + return -EINVAL; + + ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, + "rockchip,phy-grf", &syscon); + if (ret) { + pr_err("unable to find syscon device for rockchip,phy-grf\n"); + return ret; + } + + priv->phy_grf = syscon_get_regmap(syscon); + if (IS_ERR(priv->phy_grf)) { + dev_err(dev, "failed to find rockchip,phy_grf regmap\n"); + return PTR_ERR(priv->phy_grf); + } + + ret = reset_get_by_name(dev, "phy", &priv->p30phy); + if (ret) { + dev_err(dev, "no phy reset control specified\n"); + return ret; + } + + ret = clk_get_by_name(dev, "refclk_m", &priv->ref_clk_m); + if (ret) { + dev_err(dev, "failed to find ref clock M\n"); + return PTR_ERR(&priv->ref_clk_m); + } + + ret = clk_get_by_name(dev, "refclk_n", &priv->ref_clk_n); + if (ret) { + dev_err(dev, "failed to find ref clock N\n"); + return PTR_ERR(&priv->ref_clk_n); + } + + ret = clk_get_by_name(dev, "pclk", &priv->pclk); + if (ret) { + dev_err(dev, "failed to find pclk\n"); + return PTR_ERR(&priv->pclk); + } + + return 0; +} + +static struct phy_ops rochchip_p3phy_ops = { + .init = rochchip_p3phy_init, + .exit = rochchip_p3phy_exit, +}; + +static const struct udevice_id rockchip_p3phy_of_match[] = { + { .compatible = "rockchip,rk3568-pcie3-phy" }, + { }, +}; + +U_BOOT_DRIVER(rockchip_pcie3phy) = { + .name = "rockchip_pcie3phy", + .id = UCLASS_PHY, + .of_match = rockchip_p3phy_of_match, + .ops = &rochchip_p3phy_ops, + .probe = rockchip_p3phy_probe, + .priv_auto = sizeof(struct rockchip_p3phy_priv), +}; diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c index 6553dde45c2..4dd3f73ead2 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c @@ -615,6 +615,7 @@ static int mtk_gpiochip_register(struct udevice *parent) if (!drv) return -ENOENT; + ret = -ENOENT; dev_for_each_subnode(node, parent) if (ofnode_read_bool(node, "gpio-controller")) { ret = 0; diff --git a/drivers/pinctrl/pinctrl_stm32.c b/drivers/pinctrl/pinctrl_stm32.c index 591cd1a0ecc..a1f53a793b4 100644 --- a/drivers/pinctrl/pinctrl_stm32.c +++ b/drivers/pinctrl/pinctrl_stm32.c @@ -3,6 +3,8 @@ * Copyright (C) 2017-2020 STMicroelectronics - All Rights Reserved */ +#define LOG_CATEGORY UCLASS_PINCTRL + #include <common.h> #include <dm.h> #include <hwspinlock.h> @@ -256,8 +258,8 @@ static int stm32_pinctrl_probe(struct udevice *dev) /* hwspinlock property is optional, just log the error */ ret = hwspinlock_get_by_index(dev, 0, &priv->hws); if (ret) - debug("%s: hwspinlock_get_by_index may have failed (%d)\n", - __func__, ret); + dev_dbg(dev, "hwspinlock_get_by_index may have failed (%d)\n", + ret); return 0; } @@ -305,8 +307,7 @@ static int prep_gpio_dsc(struct stm32_gpio_dsc *gpio_dsc, u32 port_pin) { gpio_dsc->port = (port_pin & 0x1F000) >> 12; gpio_dsc->pin = (port_pin & 0x0F00) >> 8; - debug("%s: GPIO:port= %d, pin= %d\n", __func__, gpio_dsc->port, - gpio_dsc->pin); + log_debug("GPIO:port= %d, pin= %d\n", gpio_dsc->port, gpio_dsc->pin); return 0; } @@ -347,9 +348,9 @@ static int prep_gpio_ctl(struct stm32_gpio_ctl *gpio_ctl, u32 gpio_fn, else gpio_ctl->pupd = STM32_GPIO_PUPD_NO; - debug("%s: gpio fn= %d, slew-rate= %x, op type= %x, pull-upd is = %x\n", - __func__, gpio_fn, gpio_ctl->speed, gpio_ctl->otype, - gpio_ctl->pupd); + log_debug("gpio fn= %d, slew-rate= %x, op type= %x, pull-upd is = %x\n", + gpio_fn, gpio_ctl->speed, gpio_ctl->otype, + gpio_ctl->pupd); return 0; } @@ -373,7 +374,7 @@ static int stm32_pinctrl_config(ofnode node) if (rv < 0) return rv; len = rv / sizeof(pin_mux[0]); - debug("%s: no of pinmux entries= %d\n", __func__, len); + log_debug("No of pinmux entries= %d\n", len); if (len > MAX_PINS_ONE_IP) return -EINVAL; rv = ofnode_read_u32_array(subnode, "pinmux", pin_mux, len); @@ -382,7 +383,7 @@ static int stm32_pinctrl_config(ofnode node) for (i = 0; i < len; i++) { struct gpio_desc desc; - debug("%s: pinmux = %x\n", __func__, *(pin_mux + i)); + log_debug("pinmux = %x\n", *(pin_mux + i)); prep_gpio_dsc(&gpio_dsc, *(pin_mux + i)); prep_gpio_ctl(&gpio_ctl, *(pin_mux + i), subnode); rv = uclass_get_device_by_seq(UCLASS_GPIO, @@ -392,7 +393,7 @@ static int stm32_pinctrl_config(ofnode node) return rv; desc.offset = gpio_dsc.pin; rv = stm32_gpio_config(&desc, &gpio_ctl); - debug("%s: rv = %d\n\n", __func__, rv); + log_debug("rv = %d\n\n", rv); if (rv) return rv; } @@ -408,7 +409,7 @@ static int stm32_pinctrl_bind(struct udevice *dev) int ret; dev_for_each_subnode(node, dev) { - debug("%s: bind %s\n", __func__, ofnode_get_name(node)); + dev_dbg(dev, "bind %s\n", ofnode_get_name(node)); ofnode_get_property(node, "gpio-controller", &ret); if (ret < 0) @@ -424,7 +425,7 @@ static int stm32_pinctrl_bind(struct udevice *dev) if (ret) return ret; - debug("%s: bind %s\n", __func__, name); + dev_dbg(dev, "bind %s\n", name); } return 0; @@ -448,7 +449,7 @@ static int stm32_pinctrl_set_state_simple(struct udevice *dev, if (!list) return -EINVAL; - debug("%s: periph->name = %s\n", __func__, periph->name); + dev_dbg(dev, "periph->name = %s\n", periph->name); size /= sizeof(*list); for (i = 0; i < size; i++) { @@ -456,7 +457,8 @@ static int stm32_pinctrl_set_state_simple(struct udevice *dev, config_node = ofnode_get_by_phandle(phandle); if (!ofnode_valid(config_node)) { - pr_err("prop pinctrl-0 index %d invalid phandle\n", i); + dev_err(periph, + "prop pinctrl-0 index %d invalid phandle\n", i); return -EINVAL; } diff --git a/drivers/pinctrl/renesas/pfc.c b/drivers/pinctrl/renesas/pfc.c index 8bb7e16f944..6ff948420c5 100644 --- a/drivers/pinctrl/renesas/pfc.c +++ b/drivers/pinctrl/renesas/pfc.c @@ -44,6 +44,7 @@ enum sh_pfc_model { struct sh_pfc_pin_config { u32 type; + const char *name; }; struct sh_pfc_pinctrl { @@ -448,6 +449,30 @@ static const char *sh_pfc_pinctrl_get_group_name(struct udevice *dev, return priv->pfc.info->groups[selector].name; } +static int sh_pfc_pinctrl_get_pin_muxing(struct udevice *dev, + unsigned int selector, + char *buf, int size) +{ + struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev); + struct sh_pfc_pinctrl *pmx = &priv->pmx; + struct sh_pfc *pfc = &priv->pfc; + struct sh_pfc_pin_config *cfg; + const struct sh_pfc_pin *pin; + int idx; + + pin = &priv->pfc.info->pins[selector]; + if (!pin) { + snprintf(buf, size, "Unknown"); + return -EINVAL; + } + + idx = sh_pfc_get_pin_index(pfc, pin->pin); + cfg = &pmx->configs[idx]; + snprintf(buf, size, "%s", cfg->name); + + return 0; +} + static int sh_pfc_pinctrl_get_functions_count(struct udevice *dev) { struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev); @@ -487,14 +512,21 @@ static int sh_pfc_gpio_request_enable(struct udevice *dev, idx = sh_pfc_get_pin_index(pfc, pin->pin); cfg = &pmx->configs[idx]; - if (cfg->type != PINMUX_TYPE_NONE) + if (cfg->type != PINMUX_TYPE_NONE) { + if (!strcmp(cfg->name, pin->name)) + return 0; + + dev_err(pfc->dev, "Pin already used as %s\n", + cfg->name); return -EBUSY; + } ret = sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_GPIO); if (ret) return ret; cfg->type = PINMUX_TYPE_GPIO; + cfg->name = "gpio"; return 0; } @@ -524,6 +556,7 @@ static int sh_pfc_gpio_disable_free(struct udevice *dev, cfg = &pmx->configs[idx]; cfg->type = PINMUX_TYPE_NONE; + cfg->name = "none"; return 0; } @@ -537,11 +570,25 @@ static int sh_pfc_pinctrl_pin_set(struct udevice *dev, unsigned pin_selector, const struct sh_pfc_pin *pin = &priv->pfc.info->pins[pin_selector]; int idx = sh_pfc_get_pin_index(pfc, pin->pin); struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; + int ret; - if (cfg->type != PINMUX_TYPE_NONE) + if (cfg->type != PINMUX_TYPE_NONE) { + if (!strcmp(cfg->name, pin->name)) + return 0; + + dev_err(pfc->dev, "Pin already used as %s\n", + cfg->name); return -EBUSY; + } + + ret = sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_FUNCTION); + if (ret) + return ret; - return sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_FUNCTION); + cfg->type = PINMUX_TYPE_FUNCTION; + cfg->name = "function"; + + return 0; } static int sh_pfc_pinctrl_group_set(struct udevice *dev, unsigned group_selector, @@ -551,23 +598,41 @@ static int sh_pfc_pinctrl_group_set(struct udevice *dev, unsigned group_selector struct sh_pfc_pinctrl *pmx = &priv->pmx; struct sh_pfc *pfc = &priv->pfc; const struct sh_pfc_pin_group *grp = &priv->pfc.info->groups[group_selector]; + bool grp_pins_configured = true; + struct sh_pfc_pin_config *cfg; unsigned int i; int ret = 0; + int idx; for (i = 0; i < grp->nr_pins; ++i) { - int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]); - struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; + idx = sh_pfc_get_pin_index(pfc, grp->pins[i]); + cfg = &pmx->configs[idx]; if (cfg->type != PINMUX_TYPE_NONE) { + if (!strcmp(cfg->name, grp->name)) + continue; + + dev_err(pfc->dev, "Pin already used as %s\n", + cfg->name); ret = -EBUSY; goto done; + } else { + grp_pins_configured = false; } } + if (grp_pins_configured) + return 0; + for (i = 0; i < grp->nr_pins; ++i) { ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION); if (ret < 0) break; + + idx = sh_pfc_get_pin_index(pfc, grp->pins[i]); + cfg = &pmx->configs[idx]; + cfg->type = PINMUX_TYPE_FUNCTION; + cfg->name = priv->pfc.info->groups[group_selector].name; } done: @@ -774,6 +839,7 @@ static struct pinctrl_ops sh_pfc_pinctrl_ops = { .get_pin_name = sh_pfc_pinctrl_get_pin_name, .get_groups_count = sh_pfc_pinctrl_get_groups_count, .get_group_name = sh_pfc_pinctrl_get_group_name, + .get_pin_muxing = sh_pfc_pinctrl_get_pin_muxing, .get_functions_count = sh_pfc_pinctrl_get_functions_count, .get_function_name = sh_pfc_pinctrl_get_function_name, @@ -804,6 +870,7 @@ static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx) for (i = 0; i < pfc->info->nr_pins; ++i) { struct sh_pfc_pin_config *cfg = &pmx->configs[i]; cfg->type = PINMUX_TYPE_NONE; + cfg->name = "none"; } return 0; diff --git a/drivers/power/domain/meson-ee-pwrc.c b/drivers/power/domain/meson-ee-pwrc.c index ef8274ce96d..a4d50e701ae 100644 --- a/drivers/power/domain/meson-ee-pwrc.c +++ b/drivers/power/domain/meson-ee-pwrc.c @@ -13,7 +13,9 @@ #include <syscon.h> #include <reset.h> #include <clk.h> +#include <dt-bindings/power/meson-axg-power.h> #include <dt-bindings/power/meson-g12a-power.h> +#include <dt-bindings/power/meson-gxbb-power.h> #include <dt-bindings/power/meson-sm1-power.h> #include <linux/bitops.h> #include <linux/delay.h> @@ -68,7 +70,7 @@ struct meson_ee_pwrc_domain_data { /* TOP Power Domains */ -static struct meson_ee_pwrc_top_domain g12a_pwrc_vpu = { +static struct meson_ee_pwrc_top_domain gx_pwrc_vpu = { .sleep_reg = AO_RTI_GEN_PWR_SLEEP0, .sleep_mask = BIT(8), .iso_reg = AO_RTI_GEN_PWR_SLEEP0, @@ -126,6 +128,17 @@ static struct meson_ee_pwrc_mem_domain g12a_pwrc_mem_vpu[] = { VPU_HHI_MEMPD(HHI_MEM_PD_REG0), }; +static struct meson_ee_pwrc_mem_domain axg_pwrc_mem_vpu[] = { + VPU_MEMPD(HHI_VPU_MEM_PD_REG0), + VPU_HHI_MEMPD(HHI_MEM_PD_REG0), +}; + +static struct meson_ee_pwrc_mem_domain gxbb_pwrc_mem_vpu[] = { + VPU_MEMPD(HHI_VPU_MEM_PD_REG0), + VPU_MEMPD(HHI_VPU_MEM_PD_REG1), + VPU_HHI_MEMPD(HHI_MEM_PD_REG0), +}; + static struct meson_ee_pwrc_mem_domain g12a_pwrc_mem_eth[] = { { HHI_MEM_PD_REG0, GENMASK(3, 2) }, }; @@ -159,6 +172,10 @@ static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_ge2d[] = { { HHI_MEM_PD_REG0, GENMASK(25, 18) }, }; +static struct meson_ee_pwrc_mem_domain axg_pwrc_mem_audio[] = { + { HHI_MEM_PD_REG0, GENMASK(5, 4) }, +}; + static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_audio[] = { { HHI_MEM_PD_REG0, GENMASK(5, 4) }, { HHI_AUDIO_MEM_PD_REG0, GENMASK(1, 0) }, @@ -201,11 +218,24 @@ static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_audio[] = { static bool pwrc_ee_get_power(struct power_domain *power_domain); static struct meson_ee_pwrc_domain_desc g12a_pwrc_domains[] = { - [PWRC_G12A_VPU_ID] = VPU_PD("VPU", &g12a_pwrc_vpu, g12a_pwrc_mem_vpu, + [PWRC_G12A_VPU_ID] = VPU_PD("VPU", &gx_pwrc_vpu, g12a_pwrc_mem_vpu, pwrc_ee_get_power, 11, 2), [PWRC_G12A_ETH_ID] = MEM_PD("ETH", g12a_pwrc_mem_eth), }; +static struct meson_ee_pwrc_domain_desc axg_pwrc_domains[] = { + [PWRC_AXG_VPU_ID] = VPU_PD("VPU", &gx_pwrc_vpu, axg_pwrc_mem_vpu, + pwrc_ee_get_power, 5, 2), + [PWRC_AXG_ETHERNET_MEM_ID] = MEM_PD("ETH", g12a_pwrc_mem_eth), + [PWRC_AXG_AUDIO_ID] = MEM_PD("AUDIO", axg_pwrc_mem_audio), +}; + +static struct meson_ee_pwrc_domain_desc gxbb_pwrc_domains[] = { + [PWRC_GXBB_VPU_ID] = VPU_PD("VPU", &gx_pwrc_vpu, gxbb_pwrc_mem_vpu, + pwrc_ee_get_power, 12, 2), + [PWRC_GXBB_ETHERNET_MEM_ID] = MEM_PD("ETH", g12a_pwrc_mem_eth), +}; + static struct meson_ee_pwrc_domain_desc sm1_pwrc_domains[] = { [PWRC_SM1_VPU_ID] = VPU_PD("VPU", &sm1_pwrc_vpu, sm1_pwrc_mem_vpu, pwrc_ee_get_power, 11, 2), @@ -369,6 +399,16 @@ static struct meson_ee_pwrc_domain_data meson_ee_g12a_pwrc_data = { .domains = g12a_pwrc_domains, }; +static struct meson_ee_pwrc_domain_data meson_ee_axg_pwrc_data = { + .count = ARRAY_SIZE(axg_pwrc_domains), + .domains = axg_pwrc_domains, +}; + +static struct meson_ee_pwrc_domain_data meson_ee_gxbb_pwrc_data = { + .count = ARRAY_SIZE(gxbb_pwrc_domains), + .domains = gxbb_pwrc_domains, +}; + static struct meson_ee_pwrc_domain_data meson_ee_sm1_pwrc_data = { .count = ARRAY_SIZE(sm1_pwrc_domains), .domains = sm1_pwrc_domains, @@ -380,6 +420,14 @@ static const struct udevice_id meson_ee_pwrc_ids[] = { .data = (unsigned long)&meson_ee_g12a_pwrc_data, }, { + .compatible = "amlogic,meson-gxbb-pwrc", + .data = (unsigned long)&meson_ee_gxbb_pwrc_data, + }, + { + .compatible = "amlogic,meson-axg-pwrc", + .data = (unsigned long)&meson_ee_axg_pwrc_data, + }, + { .compatible = "amlogic,meson-sm1-pwrc", .data = (unsigned long)&meson_ee_sm1_pwrc_data, }, diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig index 7d51510d1b8..583fd3ddcde 100644 --- a/drivers/power/pmic/Kconfig +++ b/drivers/power/pmic/Kconfig @@ -91,6 +91,21 @@ config DM_PMIC_FAN53555 The driver implements read/write operations for use with the FAN53555 regulator driver and binds the regulator driver to its node. +config DM_PMIC_MP5416 + bool "Enable Driver Model for PMIC MP5416" + depends on DM_PMIC + help + This config enables implementation of driver-model pmic uclass features + for PMIC MP5416. The driver implements read/write operations. + +config SPL_DM_PMIC_MP5416 + bool "Enable Driver Model for PMIC MP5416 in SPL stage" + depends on DM_PMIC + help + This config enables implementation of driver-model pmic uclass + features for PMIC MP5416. The driver implements read/write + operations. + config DM_PMIC_PCA9450 bool "Enable Driver Model for PMIC PCA9450" depends on DM_PMIC diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile index 9cd6c375c06..2b2a6ddb565 100644 --- a/drivers/power/pmic/Makefile +++ b/drivers/power/pmic/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_DM_PMIC_MAX77686) += max77686.o obj-$(CONFIG_DM_PMIC_MAX8998) += max8998.o obj-$(CONFIG_DM_PMIC_MC34708) += mc34708.o obj-$(CONFIG_$(SPL_)DM_PMIC_BD71837) += bd71837.o +obj-$(CONFIG_$(SPL_)DM_PMIC_MP5416) += mp5416.o obj-$(CONFIG_$(SPL_)DM_PMIC_PFUZE100) += pfuze100.o obj-$(CONFIG_$(SPL_)DM_PMIC_PCA9450) += pca9450.o obj-$(CONFIG_PMIC_S2MPS11) += s2mps11.o diff --git a/drivers/power/pmic/mp5416.c b/drivers/power/pmic/mp5416.c new file mode 100644 index 00000000000..458c4df688c --- /dev/null +++ b/drivers/power/pmic/mp5416.c @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 Gateworks Corporation + */ +#include <common.h> +#include <errno.h> +#include <dm.h> +#include <i2c.h> +#include <log.h> +#include <power/pmic.h> +#include <power/regulator.h> +#include <power/mp5416.h> + +DECLARE_GLOBAL_DATA_PTR; + +static const struct pmic_child_info pmic_children_info[] = { + /* buck */ + { .prefix = "b", .driver = MP6416_REGULATOR_DRIVER }, + /* ldo */ + { .prefix = "l", .driver = MP6416_REGULATOR_DRIVER }, + { }, +}; + +static int mp5416_reg_count(struct udevice *dev) +{ + return MP5416_NUM_OF_REGS - 1; +} + +static int mp5416_write(struct udevice *dev, uint reg, const uint8_t *buff, + int len) +{ + if (dm_i2c_write(dev, reg, buff, len)) { + pr_err("write error to device: %p register: %#x!", dev, reg); + return -EIO; + } + + return 0; +} + +static int mp5416_read(struct udevice *dev, uint reg, uint8_t *buff, int len) +{ + if (dm_i2c_read(dev, reg, buff, len)) { + pr_err("read error from device: %p register: %#x!", dev, reg); + return -EIO; + } + + return 0; +} + +static int mp5416_bind(struct udevice *dev) +{ + int children; + ofnode regulators_node; + + debug("%s %s\n", __func__, dev->name); + regulators_node = dev_read_subnode(dev, "regulators"); + if (!ofnode_valid(regulators_node)) { + debug("%s: %s regulators subnode not found!\n", __func__, + dev->name); + return -ENXIO; + } + + debug("%s: '%s' - found regulators subnode\n", __func__, dev->name); + + children = pmic_bind_children(dev, regulators_node, pmic_children_info); + if (!children) + debug("%s: %s - no child found\n", __func__, dev->name); + + /* Always return success for this device */ + return 0; +} + +static int mp5416_probe(struct udevice *dev) +{ + debug("%s %s\n", __func__, dev->name); + + return 0; +} + +static struct dm_pmic_ops mp5416_ops = { + .reg_count = mp5416_reg_count, + .read = mp5416_read, + .write = mp5416_write, +}; + +static const struct udevice_id mp5416_ids[] = { + { .compatible = "mps,mp5416", }, + { } +}; + +U_BOOT_DRIVER(pmic_mp5416) = { + .name = "mp5416 pmic", + .id = UCLASS_PMIC, + .of_match = mp5416_ids, + .bind = mp5416_bind, + .probe = mp5416_probe, + .ops = &mp5416_ops, +}; diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig index d431102462a..fbbea18c7d1 100644 --- a/drivers/power/regulator/Kconfig +++ b/drivers/power/regulator/Kconfig @@ -18,7 +18,7 @@ config DM_REGULATOR config SPL_DM_REGULATOR bool "Enable regulators for SPL" - depends on DM_REGULATOR + depends on DM_REGULATOR && SPL_POWER_SUPPORT ---help--- Regulators are seldom needed in SPL. Even if they are accessed, some code space can be saved by accessing the PMIC registers directly. diff --git a/drivers/power/regulator/stm32-vrefbuf.c b/drivers/power/regulator/stm32-vrefbuf.c index c2c5770fa57..c37998a4bac 100644 --- a/drivers/power/regulator/stm32-vrefbuf.c +++ b/drivers/power/regulator/stm32-vrefbuf.c @@ -6,6 +6,8 @@ * Originally based on the Linux kernel v4.16 drivers/regulator/stm32-vrefbuf.c */ +#define LOG_CATEGORY UCLASS_REGULATOR + #include <common.h> #include <clk.h> #include <dm.h> diff --git a/drivers/pwm/pwm-ti-ehrpwm.c b/drivers/pwm/pwm-ti-ehrpwm.c index ac3d731d228..f09914519bd 100644 --- a/drivers/pwm/pwm-ti-ehrpwm.c +++ b/drivers/pwm/pwm-ti-ehrpwm.c @@ -461,7 +461,7 @@ U_BOOT_DRIVER(ti_ehrpwm) = { .id = UCLASS_PWM, .of_match = ti_ehrpwm_ids, .ops = &ti_ehrpwm_ops, - .ofdata_to_platdata = ti_ehrpwm_of_to_plat, + .of_to_plat = ti_ehrpwm_of_to_plat, .probe = ti_ehrpwm_probe, .remove = ti_ehrpwm_remove, .priv_auto = sizeof(struct ti_ehrpwm_priv), diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c index 1a829b5a4cf..259e4e3e678 100644 --- a/drivers/qe/qe.c +++ b/drivers/qe/qe.c @@ -288,7 +288,6 @@ void u_qe_init(void) struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV); if (!mmc) { - free(addr); printf("\nMMC cannot find device for ucode\n"); } else { printf("\nMMC read: dev # %u, block # %u, count %u ...\n", diff --git a/drivers/ram/aspeed/Kconfig b/drivers/ram/aspeed/Kconfig index 020c9131882..049b9dc2492 100644 --- a/drivers/ram/aspeed/Kconfig +++ b/drivers/ram/aspeed/Kconfig @@ -1,4 +1,5 @@ if RAM || SPL_RAM + config ASPEED_DDR4_DUALX8 bool "Enable Dual X8 DDR4 die" depends on DM && OF_CONTROL && ARCH_ASPEED @@ -7,4 +8,62 @@ config ASPEED_DDR4_DUALX8 Say Y if dual X8 DDR4 die is used on the board. The aspeed ddr sdram controller needs to know if the memory chip mounted on the board is dual x8 die or not. Or it may get the wrong size of the memory space. -endif + +if ASPEED_AST2600 + +choice + prompt "DDR4 target date rate" + default ASPEED_DDR4_1600 + +config ASPEED_DDR4_400 + bool "DDR4 targets at 400Mbps" + depends on DM && OF_CONTROL && ARCH_ASPEED + help + select DDR4 target data rate at 400M + +config ASPEED_DDR4_800 + bool "DDR4 targets at 800Mbps" + depends on DM && OF_CONTROL && ARCH_ASPEED + help + select DDR4 target data rate at 800M + +config ASPEED_DDR4_1333 + bool "DDR4 targets at 1333Mbps" + depends on DM && OF_CONTROL && ARCH_ASPEED + help + select DDR4 target data rate at 1333M + +config ASPEED_DDR4_1600 + bool "DDR4 targets at 1600Mbps" + depends on DM && OF_CONTROL && ARCH_ASPEED + help + select DDR4 target data rate at 1600M +endchoice + +config ASPEED_BYPASS_SELFTEST + bool "bypass self test during DRAM initialization" + default n + help + Say Y here to bypass DRAM self test to speed up the boot time + +config ASPEED_ECC + bool "aspeed SDRAM error correcting code" + depends on DM && OF_CONTROL && ARCH_ASPEED + default n + help + enable SDRAM ECC function + +if ASPEED_ECC +config ASPEED_ECC_SIZE + int "ECC size: 0=driver auto-caluated" + depends on ASPEED_ECC + default 0 + help + SDRAM size with the error correcting code enabled. The unit is + in Megabytes. Noted that only the 8/9 of the configured size + can be used by the system. The remaining 1/9 will be used by + the ECC engine. If the size is set to 0, the sdram driver will + calculate the SDRAM size and set the whole range be ECC enabled. +endif # end of ASPEED_ECC +endif # end of ASPEED_AST2600 +endif # end of RAM || SPL_RAM diff --git a/drivers/ram/aspeed/Makefile b/drivers/ram/aspeed/Makefile index af604f8a4b0..7ac10af1c22 100644 --- a/drivers/ram/aspeed/Makefile +++ b/drivers/ram/aspeed/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-$(CONFIG_ASPEED_AST2500) += sdram_ast2500.o
\ No newline at end of file +obj-$(CONFIG_ASPEED_AST2500) += sdram_ast2500.o +obj-$(CONFIG_ASPEED_AST2600) += sdram_ast2600.o diff --git a/drivers/ram/aspeed/sdram_ast2600.c b/drivers/ram/aspeed/sdram_ast2600.c new file mode 100644 index 00000000000..fd4235225a4 --- /dev/null +++ b/drivers/ram/aspeed/sdram_ast2600.c @@ -0,0 +1,1061 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) ASPEED Technology Inc. + */ +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <errno.h> +#include <ram.h> +#include <regmap.h> +#include <reset.h> +#include <asm/io.h> +#include <asm/arch/scu_ast2600.h> +#include <asm/arch/sdram_ast2600.h> +#include <linux/err.h> +#include <linux/kernel.h> +#include <dt-bindings/clock/ast2600-clock.h> + +#define DDR_PHY_TBL_CHG_ADDR 0xaeeddeea +#define DDR_PHY_TBL_END 0xaeededed + +#if defined(CONFIG_ASPEED_DDR4_800) +u32 ast2600_sdramphy_config[165] = { + 0x1e6e0100, // start address + 0x00000000, // phyr000 + 0x0c002062, // phyr004 + 0x1a7a0063, // phyr008 + 0x5a7a0063, // phyr00c + 0x1a7a0063, // phyr010 + 0x1a7a0063, // phyr014 + 0x20000000, // phyr018 + 0x20000000, // phyr01c + 0x20000000, // phyr020 + 0x20000000, // phyr024 + 0x00000008, // phyr028 + 0x00000000, // phyr02c + 0x00077600, // phyr030 + 0x00000000, // phyr034 + 0x00000000, // phyr038 + 0x20000000, // phyr03c + 0x50506000, // phyr040 + 0x50505050, // phyr044 + 0x00002f07, // phyr048 + 0x00003080, // phyr04c + 0x04000000, // phyr050 + 0x00000200, // phyr054 + 0x03140201, // phyr058 + 0x04800000, // phyr05c + 0x0800044e, // phyr060 + 0x00000000, // phyr064 + 0x00180008, // phyr068 + 0x00e00400, // phyr06c + 0x00140206, // phyr070 + 0x1d4c0000, // phyr074 + 0x493e0107, // phyr078 + 0x08060404, // phyr07c + 0x90000a00, // phyr080 + 0x06420618, // phyr084 + 0x00001002, // phyr088 + 0x05701016, // phyr08c + 0x10000000, // phyr090 + 0xaeeddeea, // change address + 0x1e6e019c, // new address + 0x20202020, // phyr09c + 0x20202020, // phyr0a0 + 0x00002020, // phyr0a4 + 0x00002020, // phyr0a8 + 0x00000001, // phyr0ac + 0xaeeddeea, // change address + 0x1e6e01cc, // new address + 0x01010101, // phyr0cc + 0x01010101, // phyr0d0 + 0x80808080, // phyr0d4 + 0x80808080, // phyr0d8 + 0xaeeddeea, // change address + 0x1e6e0288, // new address + 0x80808080, // phyr188 + 0x80808080, // phyr18c + 0x80808080, // phyr190 + 0x80808080, // phyr194 + 0xaeeddeea, // change address + 0x1e6e02f8, // new address + 0x90909090, // phyr1f8 + 0x88888888, // phyr1fc + 0xaeeddeea, // change address + 0x1e6e0300, // new address + 0x00000000, // phyr200 + 0xaeeddeea, // change address + 0x1e6e0194, // new address + 0x80118260, // phyr094 + 0xaeeddeea, // change address + 0x1e6e019c, // new address + 0x20202020, // phyr09c + 0x20202020, // phyr0a0 + 0x00002020, // phyr0a4 + 0x80000000, // phyr0a8 + 0x00000001, // phyr0ac + 0xaeeddeea, // change address + 0x1e6e0318, // new address + 0x09222719, // phyr218 + 0x00aa4403, // phyr21c + 0xaeeddeea, // change address + 0x1e6e0198, // new address + 0x08060000, // phyr098 + 0xaeeddeea, // change address + 0x1e6e01b0, // new address + 0x00000000, // phyr0b0 + 0x00000000, // phyr0b4 + 0x00000000, // phyr0b8 + 0x00000000, // phyr0bc + 0x00000000, // phyr0c0 + 0x00000000, // phyr0c4 + 0x000aff2c, // phyr0c8 + 0xaeeddeea, // change address + 0x1e6e01dc, // new address + 0x00080000, // phyr0dc + 0x00000000, // phyr0e0 + 0xaa55aa55, // phyr0e4 + 0x55aa55aa, // phyr0e8 + 0xaaaa5555, // phyr0ec + 0x5555aaaa, // phyr0f0 + 0xaa55aa55, // phyr0f4 + 0x55aa55aa, // phyr0f8 + 0xaaaa5555, // phyr0fc + 0x5555aaaa, // phyr100 + 0xaa55aa55, // phyr104 + 0x55aa55aa, // phyr108 + 0xaaaa5555, // phyr10c + 0x5555aaaa, // phyr110 + 0xaa55aa55, // phyr114 + 0x55aa55aa, // phyr118 + 0xaaaa5555, // phyr11c + 0x5555aaaa, // phyr120 + 0x20202020, // phyr124 + 0x20202020, // phyr128 + 0x20202020, // phyr12c + 0x20202020, // phyr130 + 0x20202020, // phyr134 + 0x20202020, // phyr138 + 0x20202020, // phyr13c + 0x20202020, // phyr140 + 0x20202020, // phyr144 + 0x20202020, // phyr148 + 0x20202020, // phyr14c + 0x20202020, // phyr150 + 0x20202020, // phyr154 + 0x20202020, // phyr158 + 0x20202020, // phyr15c + 0x20202020, // phyr160 + 0x20202020, // phyr164 + 0x20202020, // phyr168 + 0x20202020, // phyr16c + 0x20202020, // phyr170 + 0xaeeddeea, // change address + 0x1e6e0298, // new address + 0x20200800, // phyr198 + 0x20202020, // phyr19c + 0x20202020, // phyr1a0 + 0x20202020, // phyr1a4 + 0x20202020, // phyr1a8 + 0x20202020, // phyr1ac + 0x20202020, // phyr1b0 + 0x20202020, // phyr1b4 + 0x20202020, // phyr1b8 + 0x20202020, // phyr1bc + 0x20202020, // phyr1c0 + 0x20202020, // phyr1c4 + 0x20202020, // phyr1c8 + 0x20202020, // phyr1cc + 0x20202020, // phyr1d0 + 0x20202020, // phyr1d4 + 0x20202020, // phyr1d8 + 0x20202020, // phyr1dc + 0x20202020, // phyr1e0 + 0x20202020, // phyr1e4 + 0x00002020, // phyr1e8 + 0xaeeddeea, // change address + 0x1e6e0304, // new address + 0x00000800, // phyr204 + 0xaeeddeea, // change address + 0x1e6e027c, // new address + 0x4e400000, // phyr17c + 0x59595959, // phyr180 + 0x40404040, // phyr184 + 0xaeeddeea, // change address + 0x1e6e02f4, // new address + 0x00000059, // phyr1f4 + 0xaeededed, // end +}; +#else +u32 ast2600_sdramphy_config[165] = { + 0x1e6e0100, // start address + 0x00000000, // phyr000 + 0x0c002062, // phyr004 + 0x1a7a0063, // phyr008 + 0x5a7a0063, // phyr00c + 0x1a7a0063, // phyr010 + 0x1a7a0063, // phyr014 + 0x20000000, // phyr018 + 0x20000000, // phyr01c + 0x20000000, // phyr020 + 0x20000000, // phyr024 + 0x00000008, // phyr028 + 0x00000000, // phyr02c + 0x00077600, // phyr030 + 0x00000000, // phyr034 + 0x00000000, // phyr038 + 0x20000000, // phyr03c + 0x50506000, // phyr040 + 0x50505050, // phyr044 + 0x00002f07, // phyr048 + 0x00003080, // phyr04c + 0x04000000, // phyr050 + 0x00000200, // phyr054 + 0x03140501, // phyr058-rtt:40 + 0x04800000, // phyr05c + 0x0800044e, // phyr060 + 0x00000000, // phyr064 + 0x00180008, // phyr068 + 0x00e00400, // phyr06c + 0x00140206, // phyr070 + 0x1d4c0000, // phyr074 + 0x493e0107, // phyr078 + 0x08060404, // phyr07c + 0x90000a00, // phyr080 + 0x06420c30, // phyr084 + 0x00001002, // phyr088 + 0x05701016, // phyr08c + 0x10000000, // phyr090 + 0xaeeddeea, // change address + 0x1e6e019c, // new address + 0x20202020, // phyr09c + 0x20202020, // phyr0a0 + 0x00002020, // phyr0a4 + 0x00002020, // phyr0a8 + 0x00000001, // phyr0ac + 0xaeeddeea, // change address + 0x1e6e01cc, // new address + 0x01010101, // phyr0cc + 0x01010101, // phyr0d0 + 0x80808080, // phyr0d4 + 0x80808080, // phyr0d8 + 0xaeeddeea, // change address + 0x1e6e0288, // new address + 0x80808080, // phyr188 + 0x80808080, // phyr18c + 0x80808080, // phyr190 + 0x80808080, // phyr194 + 0xaeeddeea, // change address + 0x1e6e02f8, // new address + 0x90909090, // phyr1f8 + 0x88888888, // phyr1fc + 0xaeeddeea, // change address + 0x1e6e0300, // new address + 0x00000000, // phyr200 + 0xaeeddeea, // change address + 0x1e6e0194, // new address + 0x801112e0, // phyr094 - bit12=1,15=0,- write window is ok + 0xaeeddeea, // change address + 0x1e6e019c, // new address + 0x20202020, // phyr09c + 0x20202020, // phyr0a0 + 0x00002020, // phyr0a4 + 0x80000000, // phyr0a8 + 0x00000001, // phyr0ac + 0xaeeddeea, // change address + 0x1e6e0318, // new address + 0x09222719, // phyr218 + 0x00aa4403, // phyr21c + 0xaeeddeea, // change address + 0x1e6e0198, // new address + 0x08060000, // phyr098 + 0xaeeddeea, // change address + 0x1e6e01b0, // new address + 0x00000000, // phyr0b0 + 0x00000000, // phyr0b4 + 0x00000000, // phyr0b8 + 0x00000000, // phyr0bc + 0x00000000, // phyr0c0 - ori + 0x00000000, // phyr0c4 + 0x000aff2c, // phyr0c8 + 0xaeeddeea, // change address + 0x1e6e01dc, // new address + 0x00080000, // phyr0dc + 0x00000000, // phyr0e0 + 0xaa55aa55, // phyr0e4 + 0x55aa55aa, // phyr0e8 + 0xaaaa5555, // phyr0ec + 0x5555aaaa, // phyr0f0 + 0xaa55aa55, // phyr0f4 + 0x55aa55aa, // phyr0f8 + 0xaaaa5555, // phyr0fc + 0x5555aaaa, // phyr100 + 0xaa55aa55, // phyr104 + 0x55aa55aa, // phyr108 + 0xaaaa5555, // phyr10c + 0x5555aaaa, // phyr110 + 0xaa55aa55, // phyr114 + 0x55aa55aa, // phyr118 + 0xaaaa5555, // phyr11c + 0x5555aaaa, // phyr120 + 0x20202020, // phyr124 + 0x20202020, // phyr128 + 0x20202020, // phyr12c + 0x20202020, // phyr130 + 0x20202020, // phyr134 + 0x20202020, // phyr138 + 0x20202020, // phyr13c + 0x20202020, // phyr140 + 0x20202020, // phyr144 + 0x20202020, // phyr148 + 0x20202020, // phyr14c + 0x20202020, // phyr150 + 0x20202020, // phyr154 + 0x20202020, // phyr158 + 0x20202020, // phyr15c + 0x20202020, // phyr160 + 0x20202020, // phyr164 + 0x20202020, // phyr168 + 0x20202020, // phyr16c + 0x20202020, // phyr170 + 0xaeeddeea, // change address + 0x1e6e0298, // new address + 0x20200800, // phyr198 + 0x20202020, // phyr19c + 0x20202020, // phyr1a0 + 0x20202020, // phyr1a4 + 0x20202020, // phyr1a8 + 0x20202020, // phyr1ac + 0x20202020, // phyr1b0 + 0x20202020, // phyr1b4 + 0x20202020, // phyr1b8 + 0x20202020, // phyr1bc + 0x20202020, // phyr1c0 + 0x20202020, // phyr1c4 + 0x20202020, // phyr1c8 + 0x20202020, // phyr1cc + 0x20202020, // phyr1d0 + 0x20202020, // phyr1d4 + 0x20202020, // phyr1d8 + 0x20202020, // phyr1dc + 0x20202020, // phyr1e0 + 0x20202020, // phyr1e4 + 0x00002020, // phyr1e8 + 0xaeeddeea, // change address + 0x1e6e0304, // new address + 0x00000800, // phyr204 + 0xaeeddeea, // change address + 0x1e6e027c, // new address + 0x4e400000, // phyr17c + 0x59595959, // phyr180 + 0x40404040, // phyr184 + 0xaeeddeea, // change address + 0x1e6e02f4, // new address + 0x00000059, // phyr1f4 + 0xaeededed, // end +}; +#endif + +/* MPLL configuration */ +#define SCU_MPLL_FREQ_400M 0x0008405F +#define SCU_MPLL_EXT_400M 0x0000002F +#define SCU_MPLL_FREQ_333M 0x00488299 +#define SCU_MPLL_EXT_333M 0x0000014C +#define SCU_MPLL_FREQ_200M 0x0078007F +#define SCU_MPLL_EXT_200M 0x0000003F +#define SCU_MPLL_FREQ_100M 0x0078003F +#define SCU_MPLL_EXT_100M 0x0000001F + +#if defined(CONFIG_ASPEED_DDR4_1600) +#define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_400M +#define SCU_MPLL_EXT_CFG SCU_MPLL_EXT_400M +#elif defined(CONFIG_ASPEED_DDR4_1333) +#define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_333M +#define SCU_MPLL_EXT_CFG SCU_MPLL_EXT_333M +#elif defined(CONFIG_ASPEED_DDR4_800) +#define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_200M +#define SCU_MPLL_EXT_CFG SCU_MPLL_EXT_200M +#elif defined(CONFIG_ASPEED_DDR4_400) +#define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_100M +#define SCU_MPLL_EXT_CFG SCU_MPLL_EXT_100M +#else +#error "undefined DDR4 target rate\n" +#endif + +/* + * AC timing and SDRAM mode register setting + * for real chip are derived from the model GDDR4-1600 + */ +#define DDR4_MR01_MODE 0x03010510 +#define DDR4_MR23_MODE 0x00000000 +#define DDR4_MR45_MODE 0x04000000 +#define DDR4_MR6_MODE 0x00000400 +#define DDR4_TRFC_1600 0x467299f1 +#define DDR4_TRFC_1333 0x3a5f80c9 +#define DDR4_TRFC_800 0x23394c78 +#define DDR4_TRFC_400 0x111c263c + +#if defined(CONFIG_ASPEED_DDR4_1600) +#define DDR4_TRFC DDR4_TRFC_1600 +#define DDR4_PHY_TRAIN_TRFC 0xc30 +#elif defined(CONFIG_ASPEED_DDR4_1333) +#define DDR4_TRFC DDR4_TRFC_1333 +#define DDR4_PHY_TRAIN_TRFC 0xa25 +#elif defined(CONFIG_ASPEED_DDR4_800) +#define DDR4_TRFC DDR4_TRFC_800 +#define DDR4_PHY_TRAIN_TRFC 0x618 +#elif defined(CONFIG_ASPEED_DDR4_400) +#define DDR4_TRFC DDR4_TRFC_400 +#define DDR4_PHY_TRAIN_TRFC 0x30c +#else +#error "undefined tRFC setting" +#endif + +/* supported SDRAM size */ +#define SDRAM_SIZE_1KB (1024U) +#define SDRAM_SIZE_1MB (SDRAM_SIZE_1KB * SDRAM_SIZE_1KB) +#define SDRAM_MIN_SIZE (256 * SDRAM_SIZE_1MB) +#define SDRAM_MAX_SIZE (2048 * SDRAM_SIZE_1MB) + +DECLARE_GLOBAL_DATA_PTR; + +static const u32 ddr4_ac_timing[4] = { + 0x040e0307, 0x0f4711f1, 0x0e060304, 0x00001240 }; +static const u32 ddr_max_grant_params[4] = { + 0x44444444, 0x44444444, 0x44444444, 0x44444444 }; + +struct dram_info { + struct ram_info info; + struct clk ddr_clk; + struct ast2600_sdrammc_regs *regs; + struct ast2600_scu *scu; + struct ast2600_ddr_phy *phy; + void __iomem *phy_setting; + void __iomem *phy_status; + ulong clock_rate; +}; + +static void ast2600_sdramphy_kick_training(struct dram_info *info) +{ + u32 data; + struct ast2600_sdrammc_regs *regs = info->regs; + + writel(SDRAM_PHYCTRL0_NRST, ®s->phy_ctrl[0]); + udelay(5); + writel(SDRAM_PHYCTRL0_NRST | SDRAM_PHYCTRL0_INIT, ®s->phy_ctrl[0]); + udelay(1000); + + while (1) { + data = readl(®s->phy_ctrl[0]) & SDRAM_PHYCTRL0_INIT; + if (~data) + break; + } +} + +/** + * @brief load DDR-PHY configurations table to the PHY registers + * @param[in] p_tbl - pointer to the configuration table + * @param[in] info - pointer to the DRAM info struct + * + * There are two sets of MRS (Mode Registers) configuration in ast2600 memory + * system: one is in the SDRAM MC (memory controller) which is used in run + * time, and the other is in the DDR-PHY IP which is used during DDR-PHY + * training. + */ +static void ast2600_sdramphy_init(u32 *p_tbl, struct dram_info *info) +{ + u32 reg_base = (u32)info->phy_setting; + u32 addr = p_tbl[0]; + u32 data; + int i = 1; + + writel(0, &info->regs->phy_ctrl[0]); + udelay(10); + + while (1) { + if (addr < reg_base) { + debug("invalid DDR-PHY addr: 0x%08x\n", addr); + break; + } + data = p_tbl[i++]; + + if (data == DDR_PHY_TBL_END) { + break; + } else if (data == DDR_PHY_TBL_CHG_ADDR) { + addr = p_tbl[i++]; + } else { + writel(data, addr); + addr += 4; + } + } + + data = readl(info->phy_setting + 0x84) & ~GENMASK(16, 0); + data |= DDR4_PHY_TRAIN_TRFC; + writel(data, info->phy_setting + 0x84); +} + +static int ast2600_sdramphy_check_status(struct dram_info *info) +{ + u32 value, tmp; + u32 reg_base = (u32)info->phy_status; + int need_retrain = 0; + + debug("\nSDRAM PHY training report:\n"); + + /* training status */ + value = readl(reg_base + 0x00); + debug("rO_DDRPHY_reg offset 0x00 = 0x%08x\n", value); + + if (value & BIT(3)) + debug("\tinitial PVT calibration fail\n"); + + if (value & BIT(5)) + debug("\truntime calibration fail\n"); + + /* PU & PD */ + value = readl(reg_base + 0x30); + debug("rO_DDRPHY_reg offset 0x30 = 0x%08x\n", value); + debug(" PU = 0x%02x\n", value & 0xff); + debug(" PD = 0x%02x\n", (value >> 16) & 0xff); + + /* read eye window */ + value = readl(reg_base + 0x68); + if (0 == (value & GENMASK(7, 0))) + need_retrain = 1; + + debug("rO_DDRPHY_reg offset 0x68 = 0x%08x\n", value); + debug(" rising edge of read data eye training pass window\n"); + tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255; + debug(" B0:%d%%\n", tmp); + tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 255; + debug(" B1:%d%%\n", tmp); + + value = readl(reg_base + 0xC8); + debug("rO_DDRPHY_reg offset 0xC8 = 0x%08x\n", value); + debug(" falling edge of read data eye training pass window\n"); + tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255; + debug(" B0:%d%%\n", tmp); + tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 255; + debug(" B1:%d%%\n", tmp); + + /* write eye window */ + value = readl(reg_base + 0x7c); + if (0 == (value & GENMASK(7, 0))) + need_retrain = 1; + + debug("rO_DDRPHY_reg offset 0x7C = 0x%08x\n", value); + debug(" rising edge of write data eye training pass window\n"); + tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255; + debug(" B0:%d%%\n", tmp); + tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 255; + debug(" B1:%d%%\n", tmp); + + /* read Vref training result */ + value = readl(reg_base + 0x88); + debug("rO_DDRPHY_reg offset 0x88 = 0x%08x\n", value); + debug(" read Vref training result\n"); + tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 127; + debug(" B0:%d%%\n", tmp); + tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 127; + debug(" B1:%d%%\n", tmp); + + /* write Vref training result */ + value = readl(reg_base + 0x90); + debug("rO_DDRPHY_reg offset 0x90 = 0x%08x\n", value); + + /* gate train */ + value = readl(reg_base + 0x50); + if ((0 == (value & GENMASK(15, 0))) || + (0 == (value & GENMASK(31, 16)))) { + need_retrain = 1; + } + + debug("rO_DDRPHY_reg offset 0x50 = 0x%08x\n", value); + + return need_retrain; +} + +#ifndef CONFIG_ASPEED_BYPASS_SELFTEST +#define MC_TEST_PATTERN_N 8 +static u32 as2600_sdrammc_test_pattern[MC_TEST_PATTERN_N] = { + 0xcc33cc33, 0xff00ff00, 0xaa55aa55, 0x88778877, + 0x92cc4d6e, 0x543d3cde, 0xf1e843c7, 0x7c61d253 }; + +#define TIMEOUT_DRAM 5000000 +int ast2600_sdrammc_dg_test(struct dram_info *info, unsigned int datagen, u32 mode) +{ + unsigned int data; + unsigned int timeout = 0; + struct ast2600_sdrammc_regs *regs = info->regs; + + writel(0, ®s->ecc_test_ctrl); + + if (mode == 0) + writel(0x00000085 | (datagen << 3), ®s->ecc_test_ctrl); + else + writel(0x000000C1 | (datagen << 3), ®s->ecc_test_ctrl); + + do { + data = readl(®s->ecc_test_ctrl) & GENMASK(13, 12); + + if (data & BIT(13)) + return 0; + + if (++timeout > TIMEOUT_DRAM) { + debug("Timeout!!\n"); + writel(0, ®s->ecc_test_ctrl); + return -1; + } + } while (!data); + + writel(0, ®s->ecc_test_ctrl); + + return 0; +} + +int ast2600_sdrammc_cbr_test(struct dram_info *info) +{ + u32 i; + struct ast2600_sdrammc_regs *regs = info->regs; + + clrsetbits_le32(®s->test_addr, GENMASK(30, 4), 0x7ffff0); + + /* single */ + for (i = 0; i < 8; i++) + if (ast2600_sdrammc_dg_test(info, i, 0)) + return -1; + + /* burst */ + for (i = 0; i < 8; i++) + if (ast2600_sdrammc_dg_test(info, i, i)) + return -1; + + return 0; +} + +static int ast2600_sdrammc_test(struct dram_info *info) +{ + struct ast2600_sdrammc_regs *regs = info->regs; + + u32 pass_cnt = 0; + u32 fail_cnt = 0; + u32 target_cnt = 2; + u32 test_cnt = 0; + u32 pattern; + u32 i = 0; + bool finish = false; + + debug("sdram mc test:\n"); + while (!finish) { + pattern = as2600_sdrammc_test_pattern[i++]; + i = i % MC_TEST_PATTERN_N; + debug(" pattern = %08X : ", pattern); + writel(pattern, ®s->test_init_val); + + if (ast2600_sdrammc_cbr_test(info)) { + debug("fail\n"); + fail_cnt++; + } else { + debug("pass\n"); + pass_cnt++; + } + + if (++test_cnt == target_cnt) + finish = true; + } + debug("statistics: pass/fail/total:%d/%d/%d\n", pass_cnt, fail_cnt, + target_cnt); + + return fail_cnt; +} +#endif + +/* + * scu500[14:13] + * 2b'00: VGA memory size = 16MB + * 2b'01: VGA memory size = 16MB + * 2b'10: VGA memory size = 32MB + * 2b'11: VGA memory size = 64MB + * + * mcr04[3:2] + * 2b'00: VGA memory size = 8MB + * 2b'01: VGA memory size = 16MB + * 2b'10: VGA memory size = 32MB + * 2b'11: VGA memory size = 64MB + */ +static size_t ast2600_sdrammc_get_vga_mem_size(struct dram_info *info) +{ + u32 vga_hwconf; + size_t vga_mem_size_base = 8 * 1024 * 1024; + + vga_hwconf = + (readl(&info->scu->hwstrap1) & SCU_HWSTRAP1_VGA_MEM_MASK) >> + SCU_HWSTRAP1_VGA_MEM_SHIFT; + + if (vga_hwconf == 0) { + vga_hwconf = 1; + writel(vga_hwconf << SCU_HWSTRAP1_VGA_MEM_SHIFT, + &info->scu->hwstrap1); + } + + clrsetbits_le32(&info->regs->config, SDRAM_CONF_VGA_SIZE_MASK, + ((vga_hwconf << SDRAM_CONF_VGA_SIZE_SHIFT) & + SDRAM_CONF_VGA_SIZE_MASK)); + + /* no need to reserve VGA memory if efuse[VGA disable] is set */ + if (readl(&info->scu->efuse) & SCU_EFUSE_DIS_VGA) + return 0; + + return vga_mem_size_base << vga_hwconf; +} + +/* + * Find out RAM size and save it in dram_info + * + * The procedure is taken from Aspeed SDK + */ +static void ast2600_sdrammc_calc_size(struct dram_info *info) +{ + /* The controller supports 256/512/1024/2048 MB ram */ + size_t ram_size = SDRAM_MIN_SIZE; + const int write_test_offset = 0x100000; + u32 test_pattern = 0xdeadbeef; + u32 cap_param = SDRAM_CONF_CAP_2048M; + u32 refresh_timing_param = DDR4_TRFC; + const u32 write_addr_base = CONFIG_SYS_SDRAM_BASE + write_test_offset; + + for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE; + ram_size >>= 1) { + writel(test_pattern, write_addr_base + (ram_size >> 1)); + test_pattern = (test_pattern >> 4) | (test_pattern << 28); + } + + /* One last write to overwrite all wrapped values */ + writel(test_pattern, write_addr_base); + + /* Reset the pattern and see which value was really written */ + test_pattern = 0xdeadbeef; + for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE; + ram_size >>= 1) { + if (readl(write_addr_base + (ram_size >> 1)) == test_pattern) + break; + + --cap_param; + refresh_timing_param >>= 8; + test_pattern = (test_pattern >> 4) | (test_pattern << 28); + } + + clrsetbits_le32(&info->regs->ac_timing[1], + (SDRAM_AC_TRFC_MASK << SDRAM_AC_TRFC_SHIFT), + ((refresh_timing_param & SDRAM_AC_TRFC_MASK) + << SDRAM_AC_TRFC_SHIFT)); + + info->info.base = CONFIG_SYS_SDRAM_BASE; + info->info.size = ram_size - ast2600_sdrammc_get_vga_mem_size(info); + + clrsetbits_le32(&info->regs->config, SDRAM_CONF_CAP_MASK, + ((cap_param << SDRAM_CONF_CAP_SHIFT) & SDRAM_CONF_CAP_MASK)); +} + +static int ast2600_sdrammc_init_ddr4(struct dram_info *info) +{ + const u32 power_ctrl = MCR34_CKE_EN | MCR34_AUTOPWRDN_EN | + MCR34_MREQ_BYPASS_DIS | MCR34_RESETN_DIS | + MCR34_ODT_EN | MCR34_ODT_AUTO_ON | + (0x1 << MCR34_ODT_EXT_SHIFT); + + /* init SDRAM-PHY only on real chip */ + ast2600_sdramphy_init(ast2600_sdramphy_config, info); + writel((MCR34_CKE_EN | MCR34_MREQI_DIS | MCR34_RESETN_DIS), + &info->regs->power_ctrl); + udelay(5); + ast2600_sdramphy_kick_training(info); + udelay(500); + writel(SDRAM_RESET_DLL_ZQCL_EN, &info->regs->refresh_timing); + + writel(MCR30_SET_MR(3), &info->regs->mode_setting_control); + writel(MCR30_SET_MR(6), &info->regs->mode_setting_control); + writel(MCR30_SET_MR(5), &info->regs->mode_setting_control); + writel(MCR30_SET_MR(4), &info->regs->mode_setting_control); + writel(MCR30_SET_MR(2), &info->regs->mode_setting_control); + writel(MCR30_SET_MR(1), &info->regs->mode_setting_control); + writel(MCR30_SET_MR(0) | MCR30_RESET_DLL_DELAY_EN, + &info->regs->mode_setting_control); + + writel(SDRAM_REFRESH_EN | SDRAM_RESET_DLL_ZQCL_EN | + (0x5f << SDRAM_REFRESH_PERIOD_SHIFT), + &info->regs->refresh_timing); + + /* wait self-refresh idle */ + while (readl(&info->regs->power_ctrl) & + MCR34_SELF_REFRESH_STATUS_MASK) + ; + + writel(SDRAM_REFRESH_EN | SDRAM_LOW_PRI_REFRESH_EN | + SDRAM_REFRESH_ZQCS_EN | + (0x5f << SDRAM_REFRESH_PERIOD_SHIFT) | + (0x42aa << SDRAM_REFRESH_PERIOD_ZQCS_SHIFT), + &info->regs->refresh_timing); + + writel(power_ctrl, &info->regs->power_ctrl); + udelay(500); + + return 0; +} + +static void ast2600_sdrammc_unlock(struct dram_info *info) +{ + writel(SDRAM_UNLOCK_KEY, &info->regs->protection_key); + while (!readl(&info->regs->protection_key)) + ; +} + +static void ast2600_sdrammc_lock(struct dram_info *info) +{ + writel(~SDRAM_UNLOCK_KEY, &info->regs->protection_key); + while (readl(&info->regs->protection_key)) + ; +} + +static void ast2600_sdrammc_common_init(struct ast2600_sdrammc_regs *regs) +{ + int i; + + writel(MCR34_MREQI_DIS | MCR34_RESETN_DIS, ®s->power_ctrl); + writel(SDRAM_VIDEO_UNLOCK_KEY, ®s->gm_protection_key); + writel(0x10 << MCR38_RW_MAX_GRANT_CNT_RQ_SHIFT, + ®s->arbitration_ctrl); + writel(0xFFBBFFF4, ®s->req_limit_mask); + + for (i = 0; i < ARRAY_SIZE(ddr_max_grant_params); ++i) + writel(ddr_max_grant_params[i], ®s->max_grant_len[i]); + + writel(MCR50_RESET_ALL_INTR, ®s->intr_ctrl); + + writel(0x07FFFFFF, ®s->ecc_range_ctrl); + + writel(0, ®s->ecc_test_ctrl); + writel(0x80000001, ®s->test_addr); + writel(0, ®s->test_fail_dq_bit); + writel(0, ®s->test_init_val); + + writel(0xFFFFFFFF, ®s->req_input_ctrl); + writel(0, ®s->req_high_pri_ctrl); + + udelay(600); + +#ifdef CONFIG_ASPEED_DDR4_DUALX8 + writel(0x37, ®s->config); +#else + writel(0x17, ®s->config); +#endif + + /* load controller setting */ + for (i = 0; i < ARRAY_SIZE(ddr4_ac_timing); ++i) + writel(ddr4_ac_timing[i], ®s->ac_timing[i]); + + writel(DDR4_MR01_MODE, ®s->mr01_mode_setting); + writel(DDR4_MR23_MODE, ®s->mr23_mode_setting); + writel(DDR4_MR45_MODE, ®s->mr45_mode_setting); + writel(DDR4_MR6_MODE, ®s->mr6_mode_setting); +} + +/* + * Update size info according to the ECC HW setting + * + * Assume SDRAM has been initialized by SPL or the host. To get the RAM size, we + * don't need to calculate the ECC size again but read from MCR04 and derive the + * size from its value. + */ +static void ast2600_sdrammc_update_size(struct dram_info *info) +{ + struct ast2600_sdrammc_regs *regs = info->regs; + u32 conf = readl(®s->config); + u32 cap_param; + size_t ram_size = SDRAM_MAX_SIZE; + size_t hw_size; + + cap_param = (conf & SDRAM_CONF_CAP_MASK) >> SDRAM_CONF_CAP_SHIFT; + switch (cap_param) { + case SDRAM_CONF_CAP_2048M: + ram_size = 2048 * SDRAM_SIZE_1MB; + break; + case SDRAM_CONF_CAP_1024M: + ram_size = 1024 * SDRAM_SIZE_1MB; + break; + case SDRAM_CONF_CAP_512M: + ram_size = 512 * SDRAM_SIZE_1MB; + break; + case SDRAM_CONF_CAP_256M: + ram_size = 256 * SDRAM_SIZE_1MB; + break; + } + + info->info.base = CONFIG_SYS_SDRAM_BASE; + info->info.size = ram_size - ast2600_sdrammc_get_vga_mem_size(info); + + if (0 == (conf & SDRAM_CONF_ECC_SETUP)) + return; + + hw_size = readl(®s->ecc_range_ctrl) & SDRAM_ECC_RANGE_ADDR_MASK; + hw_size += (1 << SDRAM_ECC_RANGE_ADDR_SHIFT); + + info->info.size = hw_size; +} + +#ifdef CONFIG_ASPEED_ECC +static void ast2600_sdrammc_ecc_enable(struct dram_info *info) +{ + struct ast2600_sdrammc_regs *regs = info->regs; + size_t conf_size; + u32 reg; + + conf_size = CONFIG_ASPEED_ECC_SIZE * SDRAM_SIZE_1MB; + if (conf_size > info->info.size) { + printf("warning: ECC configured %dMB but actual size is %dMB\n", + CONFIG_ASPEED_ECC_SIZE, + info->info.size / SDRAM_SIZE_1MB); + conf_size = info->info.size; + } else if (conf_size == 0) { + conf_size = info->info.size; + } + + info->info.size = (((conf_size / 9) * 8) >> 20) << 20; + writel(((info->info.size >> 20) - 1) << 20, ®s->ecc_range_ctrl); + reg = readl(®s->config) | SDRAM_CONF_ECC_SETUP; + writel(reg, ®s->config); + + writel(0, ®s->test_init_val); + writel(0x80000001, ®s->test_addr); + writel(0x221, ®s->ecc_test_ctrl); + while (0 == (readl(®s->ecc_test_ctrl) & BIT(12))) + ; + writel(0, ®s->ecc_test_ctrl); + writel(BIT(31), ®s->intr_ctrl); + writel(0, ®s->intr_ctrl); +} +#endif + +static int ast2600_sdrammc_probe(struct udevice *dev) +{ + int ret; + u32 reg; + struct dram_info *priv = (struct dram_info *)dev_get_priv(dev); + struct ast2600_sdrammc_regs *regs = priv->regs; + struct udevice *clk_dev; + + /* find SCU base address from clock device */ + ret = uclass_get_device_by_driver(UCLASS_CLK, + DM_DRIVER_GET(aspeed_ast2600_scu), &clk_dev); + if (ret) { + debug("clock device not defined\n"); + return ret; + } + + priv->scu = devfdt_get_addr_ptr(clk_dev); + if (IS_ERR(priv->scu)) { + debug("%s(): can't get SCU\n", __func__); + return PTR_ERR(priv->scu); + } + + if (readl(&priv->scu->dram_hdshk) & SCU_DRAM_HDSHK_RDY) { + printf("already initialized, "); + ast2600_sdrammc_update_size(priv); + return 0; + } + + reg = readl(&priv->scu->mpll); + reg &= ~(SCU_PLL_BYPASS | SCU_PLL_DIV_MASK | + SCU_PLL_DENUM_MASK | SCU_PLL_NUM_MASK); + reg |= (SCU_PLL_RST | SCU_PLL_OFF | SCU_MPLL_FREQ_CFG); + writel(reg, &priv->scu->mpll); + writel(SCU_MPLL_EXT_CFG, &priv->scu->mpll_ext); + udelay(100); + reg &= ~(SCU_PLL_RST | SCU_PLL_OFF); + writel(reg, &priv->scu->mpll); + + while ((readl(&priv->scu->mpll_ext) & BIT(31)) == 0) + ; + + ast2600_sdrammc_unlock(priv); + ast2600_sdrammc_common_init(regs); +L_ast2600_sdramphy_train: + ast2600_sdrammc_init_ddr4(priv); + + /* make sure DDR-PHY is ready before access */ + do { + reg = readl(priv->phy_status) & BIT(1); + } while (reg == 0); + + if (ast2600_sdramphy_check_status(priv) != 0) { + printf("DDR4 PHY training fail, retrain\n"); + goto L_ast2600_sdramphy_train; + } + + ast2600_sdrammc_calc_size(priv); + +#ifndef CONFIG_ASPEED_BYPASS_SELFTEST + if (ast2600_sdrammc_test(priv) != 0) { + printf("%s: DDR4 init fail\n", __func__); + return -EINVAL; + } +#endif + +#ifdef CONFIG_ASPEED_ECC + ast2600_sdrammc_ecc_enable(priv); +#endif + + writel(readl(&priv->scu->dram_hdshk) | SCU_DRAM_HDSHK_RDY, + &priv->scu->dram_hdshk); + + clrbits_le32(®s->intr_ctrl, MCR50_RESET_ALL_INTR); + ast2600_sdrammc_lock(priv); + return 0; +} + +static int ast2600_sdrammc_of_to_plat(struct udevice *dev) +{ + struct dram_info *priv = dev_get_priv(dev); + + priv->regs = (void *)(uintptr_t)devfdt_get_addr_index(dev, 0); + priv->phy_setting = (void *)(uintptr_t)devfdt_get_addr_index(dev, 1); + priv->phy_status = (void *)(uintptr_t)devfdt_get_addr_index(dev, 2); + + priv->clock_rate = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), + "clock-frequency", 0); + if (!priv->clock_rate) { + debug("DDR Clock Rate not defined\n"); + return -EINVAL; + } + + return 0; +} + +static int ast2600_sdrammc_get_info(struct udevice *dev, struct ram_info *info) +{ + struct dram_info *priv = dev_get_priv(dev); + + *info = priv->info; + + return 0; +} + +static struct ram_ops ast2600_sdrammc_ops = { + .get_info = ast2600_sdrammc_get_info, +}; + +static const struct udevice_id ast2600_sdrammc_ids[] = { + { .compatible = "aspeed,ast2600-sdrammc" }, + { } +}; + +U_BOOT_DRIVER(sdrammc_ast2600) = { + .name = "aspeed_ast2600_sdrammc", + .id = UCLASS_RAM, + .of_match = ast2600_sdrammc_ids, + .ops = &ast2600_sdrammc_ops, + .of_to_plat = ast2600_sdrammc_of_to_plat, + .probe = ast2600_sdrammc_probe, + .priv_auto = sizeof(struct dram_info), +}; diff --git a/drivers/ram/k3-j721e/lpddr4.c b/drivers/ram/k3-j721e/lpddr4.c index fc80fb1e2c7..68043d7cb61 100644 --- a/drivers/ram/k3-j721e/lpddr4.c +++ b/drivers/ram/k3-j721e/lpddr4.c @@ -719,7 +719,7 @@ uint32_t lpddr4_checkctlinterrupt(const lpddr4_privatedata * pd, /* MISRA compliance (Shifting operation) check */ if (fieldshift < WORD_SHIFT) { - if (((ctlirqstatus >> fieldshift) & BIT_MASK) > 0U) { + if ((ctlirqstatus >> fieldshift) & LPDDR4_BIT_MASK) { *irqstatus = true; } else { *irqstatus = false; @@ -746,11 +746,11 @@ uint32_t lpddr4_ackctlinterrupt(const lpddr4_privatedata * pd, if (localinterrupt > WORD_SHIFT) { localinterrupt = (localinterrupt - (uint32_t) WORD_SHIFT); - regval = ((uint32_t) BIT_MASK << localinterrupt); + regval = (uint32_t)LPDDR4_BIT_MASK << localinterrupt; CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_1__REG), regval); } else { - regval = ((uint32_t) BIT_MASK << localinterrupt); + regval = (uint32_t)LPDDR4_BIT_MASK << localinterrupt; CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_0__REG), regval); } @@ -823,7 +823,7 @@ uint32_t lpddr4_checkphyindepinterrupt(const lpddr4_privatedata * pd, phyindepirqstatus = CPS_REG_READ(&(ctlregbase->LPDDR4__PI_INT_STATUS__REG)); *irqstatus = - (((phyindepirqstatus >> (uint32_t) intr) & BIT_MASK) > 0U); + !!((phyindepirqstatus >> (uint32_t)intr) & LPDDR4_BIT_MASK); } return result; } @@ -841,7 +841,7 @@ uint32_t lpddr4_ackphyindepinterrupt(const lpddr4_privatedata * pd, lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase; /* Write 1 to the requested bit to ACk the interrupt */ - regval = ((uint32_t) BIT_MASK << ui32shiftinterrupt); + regval = (uint32_t)LPDDR4_BIT_MASK << ui32shiftinterrupt; CPS_REG_WRITE(&(ctlregbase->LPDDR4__PI_INT_ACK__REG), regval); } @@ -894,7 +894,7 @@ static void lpddr4_checkwrlvlerror(lpddr4_ctlregs * ctlregbase, (volatile uint32_t *)(&(ctlregbase->LPDDR4__PHY_WRLVL_ERROR_OBS_0__REG)); /* PHY_WRLVL_ERROR_OBS_X[1:0] should be zero */ - errbitmask = (BIT_MASK << 1) | (BIT_MASK); + errbitmask = (LPDDR4_BIT_MASK << 1) | LPDDR4_BIT_MASK; for (snum = 0U; snum < DSLICE_NUM; snum++) { regval = CPS_REG_READ(regaddress); if ((regval & errbitmask) != 0U) { @@ -1054,7 +1054,7 @@ static void lpddr4_seterrors(lpddr4_ctlregs * ctlregbase, lpddr4_debuginfo * debuginfo, bool * errfoundptr) { - uint32_t errbitmask = (BIT_MASK << 0x1U) | (BIT_MASK); + uint32_t errbitmask = (LPDDR4_BIT_MASK << 0x1U) | LPDDR4_BIT_MASK; /* Check PLL observation registers for PLL lock errors */ debuginfo->pllerror = diff --git a/drivers/ram/k3-j721e/lpddr4_private.h b/drivers/ram/k3-j721e/lpddr4_private.h index 42c923464aa..3d5017ea476 100644 --- a/drivers/ram/k3-j721e/lpddr4_private.h +++ b/drivers/ram/k3-j721e/lpddr4_private.h @@ -14,9 +14,9 @@ #define VERSION_0 (0x54d5da40U) #define VERSION_1 (0xc1865a1U) -#define BIT_MASK (0x1U) -#define BYTE_MASK (0xffU) -#define NIBBLE_MASK (0xfU) +#define LPDDR4_BIT_MASK (0x1U) +#define BYTE_MASK (0xffU) +#define NIBBLE_MASK (0xfU) #define WORD_SHIFT (32U) #define WORD_MASK (0xffffffffU) @@ -46,11 +46,15 @@ #define IO_CALIB_DONE ((uint32_t)0x1U << 23U) #define IO_CALIB_FIELD ((uint32_t)NIBBLE_MASK << 28U) #define IO_CALIB_STATE ((uint32_t)0xBU << 28U) -#define RX_CAL_DONE ((uint32_t)BIT_MASK << 4U) -#define CA_TRAIN_RL (((uint32_t)BIT_MASK << 5U) | ((uint32_t)BIT_MASK << 4U)) +#define RX_CAL_DONE ((uint32_t)LPDDR4_BIT_MASK << 4U) +#define CA_TRAIN_RL (((uint32_t)LPDDR4_BIT_MASK << 5U) | \ + ((uint32_t)LPDDR4_BIT_MASK << 4U)) #define WR_LVL_STATE (((uint32_t)NIBBLE_MASK) << 13U) -#define GATE_LVL_ERROR_FIELDS (((uint32_t)BIT_MASK << 7U) | ((uint32_t)BIT_MASK << 6U)) -#define READ_LVL_ERROR_FIELDS ((((uint32_t)NIBBLE_MASK) << 28U) | (((uint32_t)BYTE_MASK) << 16U)) -#define DQ_LVL_STATUS (((uint32_t)BIT_MASK << 26U) | (((uint32_t)BYTE_MASK) << 18U)) +#define GATE_LVL_ERROR_FIELDS (((uint32_t)LPDDR4_BIT_MASK << 7U) | \ + ((uint32_t)LPDDR4_BIT_MASK << 6U)) +#define READ_LVL_ERROR_FIELDS ((((uint32_t)NIBBLE_MASK) << 28U) | \ + (((uint32_t)BYTE_MASK) << 16U)) +#define DQ_LVL_STATUS (((uint32_t)LPDDR4_BIT_MASK << 26U) | \ + (((uint32_t)BYTE_MASK) << 18U)) #endif /* LPDDR4_PRIV_H */ diff --git a/drivers/ram/stm32_sdram.c b/drivers/ram/stm32_sdram.c index 4003db0e503..540ad851387 100644 --- a/drivers/ram/stm32_sdram.c +++ b/drivers/ram/stm32_sdram.c @@ -4,6 +4,8 @@ * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics. */ +#define LOG_CATEGORY UCLASS_RAM + #include <common.h> #include <clk.h> #include <dm.h> @@ -272,7 +274,7 @@ static int stm32_fmc_of_to_plat(struct udevice *dev) ret = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0, &args); if (ret) { - dev_dbg(dev, "%s: can't find syscon device (%d)\n", __func__, ret); + dev_dbg(dev, "can't find syscon device (%d)\n", ret); } else { syscfg_base = (u32 *)ofnode_get_addr(args.node); @@ -281,7 +283,7 @@ static int stm32_fmc_of_to_plat(struct udevice *dev) /* set memory mapping selection */ clrsetbits_le32(syscfg_base, MEM_MODE_MASK, mem_remap); } else { - dev_dbg(dev, "%s: cannot find st,mem_remap property\n", __func__); + dev_dbg(dev, "cannot find st,mem_remap property\n"); } swp_fmc = dev_read_u32_default(dev, "st,swp_fmc", NOT_FOUND); @@ -289,7 +291,7 @@ static int stm32_fmc_of_to_plat(struct udevice *dev) /* set fmc swapping selection */ clrsetbits_le32(syscfg_base, SWP_FMC_MASK, swp_fmc << SWP_FMC_OFFSET); } else { - dev_dbg(dev, "%s: cannot find st,swp_fmc property\n", __func__); + dev_dbg(dev, "cannot find st,swp_fmc property\n"); } dev_dbg(dev, "syscfg %x = %x\n", (u32)syscfg_base, *syscfg_base); @@ -348,7 +350,7 @@ static int stm32_fmc_of_to_plat(struct udevice *dev) } params->no_sdram_banks = bank; - debug("%s, no of banks = %d\n", __func__, params->no_sdram_banks); + dev_dbg(dev, "no of banks = %d\n", params->no_sdram_banks); return 0; } diff --git a/drivers/ram/stm32mp1/stm32mp1_ddr.c b/drivers/ram/stm32mp1/stm32mp1_ddr.c index bf3a4c97a41..0457166b127 100644 --- a/drivers/ram/stm32mp1/stm32mp1_ddr.c +++ b/drivers/ram/stm32mp1/stm32mp1_ddr.c @@ -3,6 +3,8 @@ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved */ +#define LOG_CATEGORY UCLASS_RAM + #include <common.h> #include <clk.h> #include <log.h> @@ -311,17 +313,17 @@ static void set_reg(const struct ddr_info *priv, u32 base_addr = get_base_addr(priv, base); const struct reg_desc *desc = ddr_registers[type].desc; - debug("init %s\n", ddr_registers[type].name); + log_debug("init %s\n", ddr_registers[type].name); for (i = 0; i < ddr_registers[type].size; i++) { ptr = (unsigned int *)(base_addr + desc[i].offset); if (desc[i].par_offset == INVALID_OFFSET) { - pr_err("invalid parameter offset for %s", desc[i].name); + log_err("invalid parameter offset for %s", desc[i].name); } else { value = *((u32 *)((u32)param + desc[i].par_offset)); writel(value, ptr); - debug("[0x%x] %s= 0x%08x\n", - (u32)ptr, desc[i].name, value); + log_debug("[0x%x] %s= 0x%08x\n", + (u32)ptr, desc[i].name, value); } } } @@ -564,16 +566,16 @@ static void ddrphy_idone_wait(struct stm32mp1_ddrphy *phy) DDRPHYC_PGSR_RVERR | DDRPHYC_PGSR_RVEIRR), 1000000); - debug("\n[0x%08x] pgsr = 0x%08x ret=%d\n", - (u32)&phy->pgsr, pgsr, ret); + log_debug("\n[0x%08x] pgsr = 0x%08x ret=%d\n", + (u32)&phy->pgsr, pgsr, ret); } void stm32mp1_ddrphy_init(struct stm32mp1_ddrphy *phy, u32 pir) { pir |= DDRPHYC_PIR_INIT; writel(pir, &phy->pir); - debug("[0x%08x] pir = 0x%08x -> 0x%08x\n", - (u32)&phy->pir, pir, readl(&phy->pir)); + log_debug("[0x%08x] pir = 0x%08x -> 0x%08x\n", + (u32)&phy->pir, pir, readl(&phy->pir)); /* need to wait 10 configuration clock before start polling */ udelay(10); @@ -603,7 +605,7 @@ static void wait_sw_done_ack(struct stm32mp1_ddrctl *ctl) panic("Timeout initialising DRAM : DDR->swstat = %x\n", swstat); - debug("[0x%08x] swstat = 0x%08x\n", (u32)&ctl->swstat, swstat); + log_debug("[0x%08x] swstat = 0x%08x\n", (u32)&ctl->swstat, swstat); } /* wait quasi dynamic register update */ @@ -634,7 +636,7 @@ static void wait_operating_mode(struct ddr_info *priv, int mode) if (ret) panic("Timeout DRAM : DDR->stat = %x\n", stat); - debug("[0x%08x] stat = 0x%08x\n", (u32)&priv->ctl->stat, stat); + log_debug("[0x%08x] stat = 0x%08x\n", (u32)&priv->ctl->stat, stat); } void stm32mp1_refresh_disable(struct stm32mp1_ddrctl *ctl) @@ -706,9 +708,9 @@ void stm32mp1_ddr_init(struct ddr_info *priv, panic("ddr power init failed\n"); start: - debug("name = %s\n", config->info.name); - debug("speed = %d kHz\n", config->info.speed); - debug("size = 0x%x\n", config->info.size); + log_debug("name = %s\n", config->info.name); + log_debug("speed = %d kHz\n", config->info.speed); + log_debug("size = 0x%x\n", config->info.size); /* * 1. Program the DWC_ddr_umctl2 registers * 1.1 RESETS: presetn, core_ddrc_rstn, aresetn @@ -745,8 +747,8 @@ start: /* 1.5. initialize registers ddr_umctl2 */ /* Stop uMCTL2 before PHY is ready */ clrbits_le32(&priv->ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN); - debug("[0x%08x] dfimisc = 0x%08x\n", - (u32)&priv->ctl->dfimisc, readl(&priv->ctl->dfimisc)); + log_debug("[0x%08x] dfimisc = 0x%08x\n", + (u32)&priv->ctl->dfimisc, readl(&priv->ctl->dfimisc)); set_reg(priv, REG_REG, &config->c_reg); set_reg(priv, REG_TIMING, &config->c_timing); @@ -809,9 +811,9 @@ start: wait_operating_mode(priv, DDRCTRL_STAT_OPERATING_MODE_NORMAL); if (config->p_cal_present) { - debug("DDR DQS training skipped.\n"); + log_debug("DDR DQS training skipped.\n"); } else { - debug("DDR DQS training : "); + log_debug("DDR DQS training : "); /* 8. Disable Auto refresh and power down by setting * - RFSHCTL3.dis_au_refresh = 1 * - PWRCTL.powerdown_en = 0 diff --git a/drivers/ram/stm32mp1/stm32mp1_interactive.c b/drivers/ram/stm32mp1/stm32mp1_interactive.c index 5a5d0670461..e45a2489c50 100644 --- a/drivers/ram/stm32mp1/stm32mp1_interactive.c +++ b/drivers/ram/stm32mp1/stm32mp1_interactive.c @@ -3,6 +3,8 @@ * Copyright (C) 2019, STMicroelectronics - All Rights Reserved */ +#define LOG_CATEGORY UCLASS_RAM + #include <common.h> #include <command.h> #include <console.h> @@ -404,7 +406,7 @@ bool stm32mp1_ddr_interactive(void *priv, #endif } - debug("** step %d ** %s / %d\n", step, step_str[step], next_step); + log_debug("** step %d ** %s / %d\n", step, step_str[step], next_step); if (next_step < 0) return false; diff --git a/drivers/ram/stm32mp1/stm32mp1_ram.c b/drivers/ram/stm32mp1/stm32mp1_ram.c index 0b6d20f5667..26f0b4f1eae 100644 --- a/drivers/ram/stm32mp1/stm32mp1_ram.c +++ b/drivers/ram/stm32mp1/stm32mp1_ram.c @@ -3,6 +3,8 @@ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved */ +#define LOG_CATEGORY UCLASS_RAM + #include <common.h> #include <clk.h> #include <dm.h> @@ -12,6 +14,7 @@ #include <regmap.h> #include <syscon.h> #include <asm/io.h> +#include <dm/device_compat.h> #include "stm32mp1_ddr.h" static const char *const clkname[] = { @@ -37,7 +40,7 @@ int stm32mp1_ddr_clk_enable(struct ddr_info *priv, uint32_t mem_speed) ret = clk_enable(&clk); if (ret) { - printf("error for %s : %d\n", clkname[idx], ret); + log_err("error for %s : %d\n", clkname[idx], ret); return ret; } } @@ -45,13 +48,13 @@ int stm32mp1_ddr_clk_enable(struct ddr_info *priv, uint32_t mem_speed) priv->clk = clk; ddrphy_clk = clk_get_rate(&priv->clk); - debug("DDR: mem_speed (%d kHz), RCC %d kHz\n", - mem_speed, (u32)(ddrphy_clk / 1000)); + log_debug("DDR: mem_speed (%d kHz), RCC %d kHz\n", + mem_speed, (u32)(ddrphy_clk / 1000)); /* max 10% frequency delta */ ddr_clk = abs(ddrphy_clk - mem_speed * 1000); if (ddr_clk > (mem_speed * 100)) { - pr_err("DDR expected freq %d kHz, current is %d kHz\n", - mem_speed, (u32)(ddrphy_clk / 1000)); + log_err("DDR expected freq %d kHz, current is %d kHz\n", + mem_speed, (u32)(ddrphy_clk / 1000)); return -EINVAL; } @@ -118,7 +121,7 @@ static __maybe_unused int stm32mp1_ddr_setup(struct udevice *dev) config.info.size = ofnode_read_u32_default(node, "st,mem-size", 0); config.info.name = ofnode_read_string(node, "st,mem-name"); if (!config.info.name) { - debug("%s: no st,mem-name\n", __func__); + dev_dbg(dev, "no st,mem-name\n"); return -EINVAL; } printf("RAM: %s\n", config.info.name); @@ -128,12 +131,12 @@ static __maybe_unused int stm32mp1_ddr_setup(struct udevice *dev) (void *)((u32)&config + param[idx].offset), param[idx].size); - debug("%s: %s[0x%x] = %d\n", __func__, - param[idx].name, param[idx].size, ret); + dev_dbg(dev, "%s: %s[0x%x] = %d\n", __func__, + param[idx].name, param[idx].size, ret); if (ret && (ret != -FDT_ERR_NOTFOUND || !param[idx].present)) { - pr_err("%s: Cannot read %s, error=%d\n", - __func__, param[idx].name, ret); + dev_err(dev, "Cannot read %s, error=%d\n", + param[idx].name, ret); return -EINVAL; } if (param[idx].present) { @@ -153,7 +156,7 @@ static __maybe_unused int stm32mp1_ddr_setup(struct udevice *dev) ret = clk_get_by_name(dev, "axidcg", &axidcg); if (ret) { - debug("%s: Cannot found axidcg\n", __func__); + dev_dbg(dev, "%s: Cannot found axidcg\n", __func__); return -EINVAL; } clk_disable(&axidcg); /* disable clock gating during init */ @@ -163,13 +166,13 @@ static __maybe_unused int stm32mp1_ddr_setup(struct udevice *dev) clk_enable(&axidcg); /* enable clock gating */ /* check size */ - debug("%s : get_ram_size(%x, %x)\n", __func__, - (u32)priv->info.base, (u32)STM32_DDR_SIZE); + dev_dbg(dev, "get_ram_size(%x, %x)\n", + (u32)priv->info.base, (u32)STM32_DDR_SIZE); priv->info.size = get_ram_size((long *)priv->info.base, STM32_DDR_SIZE); - debug("%s : %x\n", __func__, (u32)priv->info.size); + dev_dbg(dev, "info.size: %x\n", (u32)priv->info.size); /* check memory access for all memory */ if (config.info.size != priv->info.size) { @@ -186,12 +189,11 @@ static int stm32mp1_ddr_probe(struct udevice *dev) struct regmap *map; int ret; - debug("STM32MP1 DDR probe\n"); priv->dev = dev; ret = regmap_init_mem(dev_ofnode(dev), &map); if (ret) - return ret; + return log_ret(ret); priv->ctl = regmap_get_range(map, 0); priv->phy = regmap_get_range(map, 1); @@ -203,7 +205,9 @@ static int stm32mp1_ddr_probe(struct udevice *dev) #if !defined(CONFIG_TFABOOT) && \ (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)) priv->info.size = 0; - return stm32mp1_ddr_setup(dev); + ret = stm32mp1_ddr_setup(dev); + + return log_ret(ret); #else ofnode node = stm32mp1_ddr_get_ofnode(dev); priv->info.size = ofnode_read_u32_default(node, "st,mem-size", 0); diff --git a/drivers/ram/stm32mp1/stm32mp1_tests.c b/drivers/ram/stm32mp1/stm32mp1_tests.c index 952006aa149..1fcc7cfd692 100644 --- a/drivers/ram/stm32mp1/stm32mp1_tests.c +++ b/drivers/ram/stm32mp1/stm32mp1_tests.c @@ -2,6 +2,9 @@ /* * Copyright (C) 2019, STMicroelectronics - All Rights Reserved */ + +#define LOG_CATEGORY UCLASS_RAM + #include <common.h> #include <console.h> #include <init.h> @@ -197,8 +200,8 @@ static u32 databus(u32 *address) /* Read it back (immediately is okay for this test). */ read_value = readl(address); - debug("%x: %x <=> %x\n", - (u32)address, read_value, pattern); + log_debug("%x: %x <=> %x\n", + (u32)address, read_value, pattern); if (read_value != pattern) return pattern; @@ -252,8 +255,8 @@ static u32 *addressbus(u32 *address, u32 nb_bytes) for (offset = 1; (offset & mask) != 0; offset <<= 1) { read_value = readl(&address[offset]); - debug("%x: %x <=> %x\n", - (u32)&address[offset], read_value, pattern); + log_debug("%x: %x <=> %x\n", + (u32)&address[offset], read_value, pattern); if (read_value != pattern) return &address[offset]; } @@ -363,8 +366,8 @@ static enum test_result databuswalk0(struct stm32mp1_ddrctl *ctl, data = readl(addr + 4 * i); if (~(1 << i) != data) { error |= 1 << i; - debug("%x: error %x expected %x => error:%x\n", - addr + 4 * i, data, ~(1 << i), error); + log_debug("%x: error %x expected %x => error:%x\n", + addr + 4 * i, data, ~(1 << i), error); } } if (test_loop_end(&loop, nb_loop, 1000)) @@ -403,8 +406,8 @@ static enum test_result databuswalk1(struct stm32mp1_ddrctl *ctl, data = readl(addr + 4 * i); if ((1 << i) != data) { error |= 1 << i; - debug("%x: error %x expected %x => error:%x\n", - addr + 4 * i, data, (1 << i), error); + log_debug("%x: error %x expected %x => error:%x\n", + addr + 4 * i, data, (1 << i), error); } } if (test_loop_end(&loop, nb_loop, 1000)) diff --git a/drivers/ram/stm32mp1/stm32mp1_tuning.c b/drivers/ram/stm32mp1/stm32mp1_tuning.c index a8d6892bb09..c8cd7c3ceaf 100644 --- a/drivers/ram/stm32mp1/stm32mp1_tuning.c +++ b/drivers/ram/stm32mp1/stm32mp1_tuning.c @@ -2,6 +2,9 @@ /* * Copyright (C) 2019, STMicroelectronics - All Rights Reserved */ + +#define LOG_CATEGORY UCLASS_RAM + #include <common.h> #include <console.h> #include <clk.h> @@ -227,8 +230,7 @@ static u8 DQ_unit_index(struct stm32mp1_ddrphy *phy, u8 byte, u8 bit) index = (readl(addr) >> DDRPHYC_DXNDQTR_DQDLY_SHIFT(bit)) & DDRPHYC_DXNDQTR_DQDLY_LOW_MASK; - pr_debug("%s: [%x]: %x => DQ unit index = %x\n", - __func__, addr, readl(addr), index); + log_debug("[%x]: %x => DQ unit index = %x\n", addr, readl(addr), index); return index; } @@ -470,13 +472,13 @@ static void apply_deskew_results(struct stm32mp1_ddrphy *phy, u8 byte, for (bit_i = 0; bit_i < 8; bit_i++) { set_DQ_unit_delay(phy, byte, bit_i, deskew_delay[byte][bit_i]); index = DQ_unit_index(phy, byte, bit_i); - pr_debug("Byte %d ; bit %d : The new DQ delay (%d) index=%d [delta=%d, 3 is the default]", - byte, bit_i, deskew_delay[byte][bit_i], - index, index - 3); + log_debug("Byte %d ; bit %d : The new DQ delay (%d) index=%d [delta=%d, 3 is the default]", + byte, bit_i, deskew_delay[byte][bit_i], + index, index - 3); printf("Byte %d, bit %d, DQ delay = %d", byte, bit_i, deskew_delay[byte][bit_i]); if (deskew_non_converge[byte][bit_i] == 1) - pr_debug(" - not converged : still more skew"); + log_debug(" - not converged : still more skew"); printf("\n"); } } @@ -536,7 +538,7 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl, /* Config the BIST block */ config_BIST(ctl, phy); - pr_debug("BIST Config done.\n"); + log_debug("BIST Config done.\n"); /* Train each byte */ for (datx8 = 0; datx8 < nb_bytes; datx8++) { @@ -545,9 +547,9 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl, datx8 + 1, nb_bytes, error); return TEST_FAILED; } - pr_debug("\n======================\n"); - pr_debug("Start deskew byte %d .\n", datx8); - pr_debug("======================\n"); + log_debug("\n======================\n"); + log_debug("Start deskew byte %d .\n", datx8); + log_debug("======================\n"); /* Enable Byte (DXNGCR, bit DXEN) */ setbits_le32(DXNGCR(phy, datx8), DDRPHYC_DXNGCR_DXEN); @@ -584,7 +586,7 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl, * Else, look for Pass init condition */ if (!success) { - pr_debug("Fail at init condtion. Let's look for a good init condition.\n"); + log_debug("Fail at init condtion. Let's look for a good init condition.\n"); success = 0; /* init */ /* Make sure we start with a PASS condition before * looking for a fail condition. @@ -592,7 +594,7 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl, */ /* escape if we find a PASS */ - pr_debug("increase Phase idx\n"); + log_debug("increase Phase idx\n"); while (!success && (phase_idx <= MAX_DQS_PHASE_IDX)) { DQS_phase_delay(phy, datx8, phase_idx); BIST_test(phy, datx8, &result); @@ -618,7 +620,7 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl, * we have hold violation, lets try reduce DQS_unit * Delay */ - pr_debug("Still fail. Try decrease DQS Unit delay\n"); + log_debug("Still fail. Try decrease DQS Unit delay\n"); phase_idx = 0; dqs_unit_delay_index = 0; @@ -665,9 +667,9 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl, return TEST_FAILED; } - pr_debug("there is a pass region for phase idx %d\n", - phase_idx); - pr_debug("Step1: Find the first failing condition\n"); + log_debug("there is a pass region for phase idx %d\n", + phase_idx); + log_debug("Step1: Find the first failing condition\n"); /* Look for the first failing condition by PHASE stepping. * This part of the algo can finish without converging. */ @@ -692,9 +694,9 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl, * stepping (minimal delay) */ if (!success) { - pr_debug("Fail region (PHASE) found phase idx %d\n", - phase_idx); - pr_debug("Let's look for first success by DQS Unit steps\n"); + log_debug("Fail region (PHASE) found phase idx %d\n", + phase_idx); + log_debug("Let's look for first success by DQS Unit steps\n"); /* This part, the algo always converge */ phase_idx--; @@ -721,7 +723,7 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl, /*+1 to get back to current condition */ last_right_ok.unit = dqs_unit_delay_index + 1; last_right_ok.bits_delay = 0xFFFFFFFF; - pr_debug("Found %d\n", dqs_unit_delay_index); + log_debug("Found %d\n", dqs_unit_delay_index); } else { /* the last OK condition is then with the * previous phase_idx. @@ -735,8 +737,8 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl, */ last_right_ok.unit = 1; last_right_ok.bits_delay = 0xFFFFFFFF; - pr_debug("Not Found : try previous phase %d\n", - phase_idx - 1); + log_debug("Not Found : try previous phase %d\n", + phase_idx - 1); DQS_phase_delay(phy, datx8, phase_idx - 1); dqs_unit_delay_index = 0; @@ -749,8 +751,8 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl, BIST_test(phy, datx8, &result); success = result.test_result; dqs_unit_delay_index++; - pr_debug("dqs_unit_delay_index = %d, result = %d\n", - dqs_unit_delay_index, success); + log_debug("dqs_unit_delay_index = %d, result = %d\n", + dqs_unit_delay_index, success); } if (!success) { @@ -758,7 +760,7 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl, dqs_unit_delay_index - 1; } else { last_right_ok.unit = 0; - pr_debug("ERROR: failed region not FOUND"); + log_debug("ERROR: failed region not FOUND"); } } } else { @@ -775,7 +777,7 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl, last_right_ok.phase = MAX_DQS_PHASE_IDX; last_right_ok.unit = MAX_DQS_UNIT_IDX; last_right_ok.bits_delay = 0xFFFFFFFF; - pr_debug("Can't find the a fail condition\n"); + log_debug("Can't find the a fail condition\n"); } /* step 2: @@ -787,9 +789,9 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl, */ printf("Byte %d, DQS unit = %d, phase = %d\n", datx8, last_right_ok.unit, last_right_ok.phase); - pr_debug("Step2, unit = %d, phase = %d, bits delay=%x\n", - last_right_ok.unit, last_right_ok.phase, - last_right_ok.bits_delay); + log_debug("Step2, unit = %d, phase = %d, bits delay=%x\n", + last_right_ok.unit, last_right_ok.phase, + last_right_ok.bits_delay); /* Restore the last_right_ok condtion. */ DQS_unit_delay(phy, datx8, last_right_ok.unit); @@ -812,7 +814,7 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl, datx8 + 1, nb_bytes, error); return error; } - pr_debug("deskewing bit %d:\n", bit_i); + log_debug("deskewing bit %d:\n", bit_i); success = 1; /* init */ /* Set all DQDLYn to maximum value. * Only bit_i will be down-delayed @@ -855,10 +857,10 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl, * at one bit. */ fail_found = 1; - pr_debug("Fail found on bit %d, for delay = %d => deskew[%d][%d] = %d\n", - bit_i, bit_i_delay_index + 1, - datx8, bit_i, - deskew_delay[datx8][bit_i]); + log_debug("Fail found on bit %d, for delay = %d => deskew[%d][%d] = %d\n", + bit_i, bit_i_delay_index + 1, + datx8, bit_i, + deskew_delay[datx8][bit_i]); } else { /* if we can find a success condition by * back-delaying this bit, just set the delay @@ -870,20 +872,20 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl, * in the report. */ deskew_non_converge[datx8][bit_i] = 1; - pr_debug("Fail not found on bit %d => deskew[%d][%d] = %d\n", - bit_i, datx8, bit_i, - deskew_delay[datx8][bit_i]); + log_debug("Fail not found on bit %d => deskew[%d][%d] = %d\n", + bit_i, datx8, bit_i, + deskew_delay[datx8][bit_i]); } } - pr_debug("**********byte %d tuning complete************\n", - datx8); + log_debug("**********byte %d tuning complete************\n", + datx8); /* If we can't find any failure by back delaying DQ lines, * hold the default values */ if (!fail_found) { for (bit_i = 0; bit_i < 8; bit_i++) deskew_delay[datx8][bit_i] = 0; - pr_debug("The Deskew algorithm can't converge, there is too much margin in your design. Good job!\n"); + log_debug("The Deskew algorithm can't converge, there is too much margin in your design. Good job!\n"); } apply_deskew_results(phy, datx8, deskew_delay, @@ -986,7 +988,7 @@ static enum test_result eye_training(struct stm32mp1_ddrctl *ctl, dqs_unit_delay_index_pass = dqs_unit_delay_index; success = 0; - pr_debug("STEP0: Find Init delay\n"); + log_debug("STEP0: Find Init delay\n"); /* STEP0: Find Init delay: a delay that put the system * in a "Pass" condition then (TODO) update * dqs_unit_delay_index_pass & phase_idx_pass @@ -1035,7 +1037,7 @@ static enum test_result eye_training(struct stm32mp1_ddrctl *ctl, byte + 1, nb_bytes, error); return TEST_FAILED; } - pr_debug("STEP1: Find LEFT PHASE DQS Bound\n"); + log_debug("STEP1: Find LEFT PHASE DQS Bound\n"); /* STEP1: Find LEFT PHASE DQS Bound */ while ((phase_idx >= 0) && (phase_idx <= MAX_DQS_PHASE_IDX) && @@ -1069,7 +1071,7 @@ static enum test_result eye_training(struct stm32mp1_ddrctl *ctl, byte + 1, nb_bytes, error); return TEST_FAILED; } - pr_debug("STEP2: Find UNIT left bound\n"); + log_debug("STEP2: Find UNIT left bound\n"); /* STEP2: Find UNIT left bound */ while ((dqs_unit_delay_index >= 0) && !left_unit_bound_found) { @@ -1097,7 +1099,7 @@ static enum test_result eye_training(struct stm32mp1_ddrctl *ctl, byte + 1, nb_bytes, error); return TEST_FAILED; } - pr_debug("STEP3: Find PHase right bound\n"); + log_debug("STEP3: Find PHase right bound\n"); /* STEP3: Find PHase right bound, start with "pass" * condition */ @@ -1135,7 +1137,7 @@ static enum test_result eye_training(struct stm32mp1_ddrctl *ctl, byte + 1, nb_bytes, error); return TEST_FAILED; } - pr_debug("STEP4: Find UNIT right bound\n"); + log_debug("STEP4: Find UNIT right bound\n"); /* STEP4: Find UNIT right bound */ while ((dqs_unit_delay_index <= MAX_DQS_UNIT_IDX) && !right_unit_bound_found) { @@ -1174,12 +1176,12 @@ static enum test_result eye_training(struct stm32mp1_ddrctl *ctl, if (((right_bound.phase + left_bound.phase) % 2 == 1) && eye_training_val[byte][1] != MAX_DQS_UNIT_IDX) eye_training_val[byte][1]++; - pr_debug("** found phase : %d - %d & unit %d - %d\n", - right_bound.phase, left_bound.phase, - right_bound.unit, left_bound.unit); - pr_debug("** calculating mid region: phase: %d unit: %d (nominal is 3)\n", - eye_training_val[byte][0], - eye_training_val[byte][1]); + log_debug("** found phase : %d - %d & unit %d - %d\n", + right_bound.phase, left_bound.phase, + right_bound.unit, left_bound.unit); + log_debug("** calculating mid region: phase: %d unit: %d (nominal is 3)\n", + eye_training_val[byte][0], + eye_training_val[byte][1]); } else { /* PPPPPPPPPP, we're already good. * Set nominal values. @@ -1280,11 +1282,11 @@ static u8 set_midpoint_read_dqs_gating(struct stm32mp1_ddrphy *phy, u8 byte, * or pppppff or ffppppp */ if (left_bound_found || right_bound_found) { - pr_debug("idx0(%d): %d %d idx1(%d) : %d %d\n", - left_bound_found, - right_bound_idx[0], left_bound_idx[0], - right_bound_found, - right_bound_idx[1], left_bound_idx[1]); + log_debug("idx0(%d): %d %d idx1(%d) : %d %d\n", + left_bound_found, + right_bound_idx[0], left_bound_idx[0], + right_bound_found, + right_bound_idx[1], left_bound_idx[1]); dqs_gate_values[byte][0] = (right_bound_idx[0] + left_bound_idx[0]) / 2; dqs_gate_values[byte][1] = @@ -1319,14 +1321,14 @@ static u8 set_midpoint_read_dqs_gating(struct stm32mp1_ddrphy *phy, u8 byte, left_bound_idx[0]; } } - pr_debug("*******calculating mid region: system latency: %d phase: %d********\n", - dqs_gate_values[byte][0], - dqs_gate_values[byte][1]); - pr_debug("*******the nominal values were system latency: 0 phase: 2*******\n"); + log_debug("*******calculating mid region: system latency: %d phase: %d********\n", + dqs_gate_values[byte][0], + dqs_gate_values[byte][1]); + log_debug("*******the nominal values were system latency: 0 phase: 2*******\n"); } } else { /* if intermitant, restore defaut values */ - pr_debug("dqs gating:no regular fail/pass/fail found. defaults values restored.\n"); + log_debug("dqs gating:no regular fail/pass/fail found. defaults values restored.\n"); dqs_gate_values[byte][0] = 0; dqs_gate_values[byte][1] = 2; } diff --git a/drivers/remoteproc/stm32_copro.c b/drivers/remoteproc/stm32_copro.c index ec7694dda9e..4c5f24857e8 100644 --- a/drivers/remoteproc/stm32_copro.c +++ b/drivers/remoteproc/stm32_copro.c @@ -2,7 +2,8 @@ /* * Copyright (C) 2019, STMicroelectronics - All Rights Reserved */ -#define pr_fmt(fmt) "%s: " fmt, __func__ +#define LOG_CATEGORY UCLASS_REMOTEPROC + #include <common.h> #include <dm.h> #include <errno.h> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 33c2736554e..f5b3f8826fb 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -81,6 +81,15 @@ config RESET_AST2500 Say Y if you want to control reset signals of different peripherals through System Control Unit (SCU). +config RESET_AST2600 + bool "Reset controller driver for AST2600 SoCs" + depends on DM_RESET + default y if ASPEED_AST2600 + help + Support for reset controller on AST2600 SoC. + Say Y if you want to control reset signals of different peripherals + through System Control Unit (SCU). + config RESET_ROCKCHIP bool "Reset controller driver for Rockchip SoCs" depends on DM_RESET && ARCH_ROCKCHIP && CLK diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index fa52aa33291..8a0f5280761 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o obj-$(CONFIG_RESET_AST2500) += reset-ast2500.o +obj-$(CONFIG_RESET_AST2600) += reset-ast2600.o obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o obj-$(CONFIG_RESET_MESON) += reset-meson.o obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o diff --git a/drivers/reset/reset-ast2600.c b/drivers/reset/reset-ast2600.c new file mode 100644 index 00000000000..f64adaf74e8 --- /dev/null +++ b/drivers/reset/reset-ast2600.c @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2020 ASPEED Technology Inc. + */ + +#include <common.h> +#include <dm.h> +#include <log.h> +#include <misc.h> +#include <reset.h> +#include <reset-uclass.h> +#include <linux/err.h> +#include <asm/io.h> +#include <asm/arch/scu_ast2600.h> + +struct ast2600_reset_priv { + struct ast2600_scu *scu; +}; + +static int ast2600_reset_request(struct reset_ctl *reset_ctl) +{ + debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl, + reset_ctl->dev, reset_ctl->id); + + return 0; +} + +static int ast2600_reset_free(struct reset_ctl *reset_ctl) +{ + debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl, + reset_ctl->dev, reset_ctl->id); + + return 0; +} + +static int ast2600_reset_assert(struct reset_ctl *reset_ctl) +{ + struct ast2600_reset_priv *priv = dev_get_priv(reset_ctl->dev); + struct ast2600_scu *scu = priv->scu; + + debug("%s: reset_ctl->id: %lu\n", __func__, reset_ctl->id); + + if (reset_ctl->id < 32) + writel(BIT(reset_ctl->id), scu->modrst_ctrl1); + else + writel(BIT(reset_ctl->id - 32), scu->modrst_ctrl2); + + return 0; +} + +static int ast2600_reset_deassert(struct reset_ctl *reset_ctl) +{ + struct ast2600_reset_priv *priv = dev_get_priv(reset_ctl->dev); + struct ast2600_scu *scu = priv->scu; + + debug("%s: reset_ctl->id: %lu\n", __func__, reset_ctl->id); + + if (reset_ctl->id < 32) + writel(BIT(reset_ctl->id), scu->modrst_clr1); + else + writel(BIT(reset_ctl->id - 32), scu->modrst_clr2); + + return 0; +} + +static int ast2600_reset_probe(struct udevice *dev) +{ + int rc; + struct ast2600_reset_priv *priv = dev_get_priv(dev); + struct udevice *scu_dev; + + /* get SCU base from clock device */ + rc = uclass_get_device_by_driver(UCLASS_CLK, + DM_DRIVER_GET(aspeed_ast2600_scu), &scu_dev); + if (rc) { + debug("%s: clock device not found, rc=%d\n", __func__, rc); + return rc; + } + + priv->scu = devfdt_get_addr_ptr(scu_dev); + if (IS_ERR_OR_NULL(priv->scu)) { + debug("%s: invalid SCU base pointer\n", __func__); + return PTR_ERR(priv->scu); + } + + return 0; +} + +static const struct udevice_id ast2600_reset_ids[] = { + { .compatible = "aspeed,ast2600-reset" }, + { } +}; + +struct reset_ops ast2600_reset_ops = { + .request = ast2600_reset_request, + .rfree = ast2600_reset_free, + .rst_assert = ast2600_reset_assert, + .rst_deassert = ast2600_reset_deassert, +}; + +U_BOOT_DRIVER(ast2600_reset) = { + .name = "ast2600_reset", + .id = UCLASS_RESET, + .of_match = ast2600_reset_ids, + .probe = ast2600_reset_probe, + .ops = &ast2600_reset_ops, + .priv_auto = sizeof(struct ast2600_reset_priv), +}; diff --git a/drivers/reset/stm32-reset.c b/drivers/reset/stm32-reset.c index b84c9daec74..daa2e47ebbe 100644 --- a/drivers/reset/stm32-reset.c +++ b/drivers/reset/stm32-reset.c @@ -4,6 +4,8 @@ * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics. */ +#define LOG_CATEGORY UCLASS_RESET + #include <common.h> #include <dm.h> #include <errno.h> @@ -12,6 +14,7 @@ #include <reset-uclass.h> #include <stm32_rcc.h> #include <asm/io.h> +#include <dm/device_compat.h> #include <linux/bitops.h> /* offset of register without set/clear management */ @@ -39,8 +42,9 @@ static int stm32_reset_assert(struct reset_ctl *reset_ctl) struct stm32_reset_priv *priv = dev_get_priv(reset_ctl->dev); int bank = (reset_ctl->id / BITS_PER_LONG) * 4; int offset = reset_ctl->id % BITS_PER_LONG; - debug("%s: reset id = %ld bank = %d offset = %d)\n", __func__, - reset_ctl->id, bank, offset); + + dev_dbg(reset_ctl->dev, "reset id = %ld bank = %d offset = %d)\n", + reset_ctl->id, bank, offset); if (dev_get_driver_data(reset_ctl->dev) == STM32MP1) if (bank != RCC_MP_GCR_OFFSET) @@ -59,8 +63,9 @@ static int stm32_reset_deassert(struct reset_ctl *reset_ctl) struct stm32_reset_priv *priv = dev_get_priv(reset_ctl->dev); int bank = (reset_ctl->id / BITS_PER_LONG) * 4; int offset = reset_ctl->id % BITS_PER_LONG; - debug("%s: reset id = %ld bank = %d offset = %d)\n", __func__, - reset_ctl->id, bank, offset); + + dev_dbg(reset_ctl->dev, "reset id = %ld bank = %d offset = %d)\n", + reset_ctl->id, bank, offset); if (dev_get_driver_data(reset_ctl->dev) == STM32MP1) if (bank != RCC_MP_GCR_OFFSET) diff --git a/drivers/rtc/stm32_rtc.c b/drivers/rtc/stm32_rtc.c index f1d0ea90d3c..1753283460d 100644 --- a/drivers/rtc/stm32_rtc.c +++ b/drivers/rtc/stm32_rtc.c @@ -2,6 +2,9 @@ /* * Copyright (C) 2019, STMicroelectronics - All Rights Reserved */ + +#define LOG_CATEGORY UCLASS_RTC + #include <common.h> #include <clk.h> #include <dm.h> diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index b4805a2e4ea..129494322ce 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -134,6 +134,22 @@ config SERIAL_SEARCH_ALL If unsure, say N. +config SERIAL_PROBE_ALL + bool "Probe all available serial devices" + depends on DM_SERIAL + default n + help + The serial subsystem only probes for a single serial device, + but does not probe for other remaining serial devices. + With this option set, we make probing and searching for + all available devices optional. + Normally, U-Boot talks to one serial port at a time, but SBSA + compliant UART devices like PL011 require initialization + by firmware and to let the kernel use serial port for sending + and receiving the characters. + + If unsure, say N. + config SPL_DM_SERIAL bool "Enable Driver Model for serial drivers in SPL" depends on DM_SERIAL && SPL_DM diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c index 58a6541d8cc..ead0193ad44 100644 --- a/drivers/serial/serial-uclass.c +++ b/drivers/serial/serial-uclass.c @@ -172,6 +172,15 @@ int serial_init(void) /* Called after relocation */ int serial_initialize(void) { + /* Scanning uclass to probe devices */ + if (IS_ENABLED(CONFIG_SERIAL_PROBE_ALL)) { + int ret; + + ret = uclass_probe_all(UCLASS_SERIAL); + if (ret) + return ret; + } + return serial_init(); } diff --git a/drivers/serial/serial_stm32.c b/drivers/serial/serial_stm32.c index 818c34cf115..f6cb708c370 100644 --- a/drivers/serial/serial_stm32.c +++ b/drivers/serial/serial_stm32.c @@ -4,6 +4,8 @@ * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics. */ +#define LOG_CATEGORY UCLASS_SERIAL + #include <common.h> #include <clk.h> #include <dm.h> @@ -13,6 +15,7 @@ #include <watchdog.h> #include <asm/io.h> #include <asm/arch/stm32.h> +#include <dm/device_compat.h> #include <linux/bitops.h> #include <linux/delay.h> #include "serial_stm32.h" diff --git a/drivers/spi/ca_sflash.c b/drivers/spi/ca_sflash.c index 00af6bffa6e..84569845b74 100644 --- a/drivers/spi/ca_sflash.c +++ b/drivers/spi/ca_sflash.c @@ -571,6 +571,6 @@ U_BOOT_DRIVER(ca_sflash) = { .id = UCLASS_SPI, .of_match = ca_sflash_ids, .ops = &ca_sflash_ops, - .priv_auto_alloc_size = sizeof(struct ca_sflash_priv), + .priv_auto = sizeof(struct ca_sflash_priv), .probe = ca_sflash_probe, }; diff --git a/drivers/spi/stm32_qspi.c b/drivers/spi/stm32_qspi.c index 440085720aa..75e5e840edb 100644 --- a/drivers/spi/stm32_qspi.c +++ b/drivers/spi/stm32_qspi.c @@ -7,6 +7,8 @@ * STM32 QSPI driver */ +#define LOG_CATEGORY UCLASS_SPI + #include <common.h> #include <clk.h> #include <dm.h> @@ -136,7 +138,7 @@ static int _stm32_qspi_wait_for_not_busy(struct stm32_qspi_priv *priv) !(sr & STM32_QSPI_SR_BUSY), STM32_BUSY_TIMEOUT_US); if (ret) - pr_err("busy timeout (stat:%#x)\n", sr); + log_err("busy timeout (stat:%#x)\n", sr); return ret; } @@ -154,9 +156,9 @@ static int _stm32_qspi_wait_cmd(struct stm32_qspi_priv *priv, sr & STM32_QSPI_SR_TCF, STM32_QSPI_CMD_TIMEOUT_US); if (ret) { - pr_err("cmd timeout (stat:%#x)\n", sr); + log_err("cmd timeout (stat:%#x)\n", sr); } else if (readl(&priv->regs->sr) & STM32_QSPI_SR_TEF) { - pr_err("transfer error (stat:%#x)\n", sr); + log_err("transfer error (stat:%#x)\n", sr); ret = -EIO; } @@ -198,7 +200,7 @@ static int _stm32_qspi_poll(struct stm32_qspi_priv *priv, sr & STM32_QSPI_SR_FTF, STM32_QSPI_FIFO_TIMEOUT_US); if (ret) { - pr_err("fifo timeout (len:%d stat:%#x)\n", len, sr); + log_err("fifo timeout (len:%d stat:%#x)\n", len, sr); return ret; } @@ -246,10 +248,10 @@ static int stm32_qspi_exec_op(struct spi_slave *slave, u8 mode = STM32_QSPI_CCR_IND_WRITE; int timeout, ret; - debug("%s: cmd:%#x mode:%d.%d.%d.%d addr:%#llx len:%#x\n", - __func__, op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth, - op->dummy.buswidth, op->data.buswidth, - op->addr.val, op->data.nbytes); + dev_dbg(slave->dev, "cmd:%#x mode:%d.%d.%d.%d addr:%#llx len:%#x\n", + op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth, + op->dummy.buswidth, op->data.buswidth, + op->addr.val, op->data.nbytes); ret = _stm32_qspi_wait_for_not_busy(priv); if (ret) @@ -320,7 +322,7 @@ abort: writel(STM32_QSPI_FCR_CTCF, &priv->regs->fcr); if (ret || timeout) - pr_err("%s ret:%d abort timeout:%d\n", __func__, ret, timeout); + dev_err(slave->dev, "ret:%d abort timeout:%d\n", ret, timeout); return ret; } @@ -353,8 +355,8 @@ static int stm32_qspi_probe(struct udevice *bus) if (priv->mm_size > STM32_QSPI_MAX_MMAP_SZ) return -EINVAL; - debug("%s: regs=<0x%p> mapped=<0x%p> mapped_size=<0x%lx>\n", - __func__, priv->regs, priv->mm_base, priv->mm_size); + dev_dbg(bus, "regs=<0x%p> mapped=<0x%p> mapped_size=<0x%lx>\n", + priv->regs, priv->mm_base, priv->mm_size); ret = clk_get_by_index(bus, 0, &clk); if (ret < 0) @@ -475,8 +477,8 @@ static int stm32_qspi_set_speed(struct udevice *bus, uint speed) STM32_QSPI_DCR_CSHT_MASK << STM32_QSPI_DCR_CSHT_SHIFT, csht << STM32_QSPI_DCR_CSHT_SHIFT); - debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, - (qspi_clk / (prescaler + 1))); + dev_dbg(bus, "regs=%p, speed=%d\n", priv->regs, + (qspi_clk / (prescaler + 1))); return 0; } @@ -485,6 +487,7 @@ static int stm32_qspi_set_mode(struct udevice *bus, uint mode) { struct stm32_qspi_priv *priv = dev_get_priv(bus); int ret; + const char *str_rx, *str_tx; ret = _stm32_qspi_wait_for_not_busy(priv); if (ret) @@ -500,21 +503,22 @@ static int stm32_qspi_set_mode(struct udevice *bus, uint mode) if (mode & SPI_CS_HIGH) return -ENODEV; - debug("%s: regs=%p, mode=%d rx: ", __func__, priv->regs, mode); - if (mode & SPI_RX_QUAD) - debug("quad, tx: "); + str_rx = "quad"; else if (mode & SPI_RX_DUAL) - debug("dual, tx: "); + str_rx = "dual"; else - debug("single, tx: "); + str_rx = "single"; if (mode & SPI_TX_QUAD) - debug("quad\n"); + str_tx = "quad"; else if (mode & SPI_TX_DUAL) - debug("dual\n"); + str_tx = "dual"; else - debug("single\n"); + str_tx = "single"; + + dev_dbg(bus, "regs=%p, mode=%d rx: %s, tx: %s\n", + priv->regs, mode, str_rx, str_tx); return 0; } diff --git a/drivers/spi/stm32_spi.c b/drivers/spi/stm32_spi.c index 720103d5176..bd8514033de 100644 --- a/drivers/spi/stm32_spi.c +++ b/drivers/spi/stm32_spi.c @@ -4,6 +4,9 @@ * * Driver for STMicroelectronics Serial peripheral interface (SPI) */ + +#define LOG_CATEGORY UCLASS_SPI + #include <common.h> #include <clk.h> #include <dm.h> @@ -138,7 +141,7 @@ static void stm32_spi_write_txfifo(struct stm32_spi_priv *priv) } } - debug("%s: %d bytes left\n", __func__, priv->tx_len); + log_debug("%d bytes left\n", priv->tx_len); } static void stm32_spi_read_rxfifo(struct stm32_spi_priv *priv) @@ -176,12 +179,12 @@ static void stm32_spi_read_rxfifo(struct stm32_spi_priv *priv) rxplvl = (sr & SPI_SR_RXPLVL) >> SPI_SR_RXPLVL_SHIFT; } - debug("%s: %d bytes left\n", __func__, priv->rx_len); + log_debug("%d bytes left\n", priv->rx_len); } static int stm32_spi_enable(struct stm32_spi_priv *priv) { - debug("%s\n", __func__); + log_debug("\n"); /* Enable the SPI hardware */ setbits_le32(priv->base + STM32_SPI_CR1, SPI_CR1_SPE); @@ -191,7 +194,7 @@ static int stm32_spi_enable(struct stm32_spi_priv *priv) static int stm32_spi_disable(struct stm32_spi_priv *priv) { - debug("%s\n", __func__); + log_debug("\n"); /* Disable the SPI hardware */ clrbits_le32(priv->base + STM32_SPI_CR1, SPI_CR1_SPE); @@ -204,7 +207,7 @@ static int stm32_spi_claim_bus(struct udevice *slave) struct udevice *bus = dev_get_parent(slave); struct stm32_spi_priv *priv = dev_get_priv(bus); - debug("%s\n", __func__); + dev_dbg(slave, "\n"); /* Enable the SPI hardware */ return stm32_spi_enable(priv); @@ -215,7 +218,7 @@ static int stm32_spi_release_bus(struct udevice *slave) struct udevice *bus = dev_get_parent(slave); struct stm32_spi_priv *priv = dev_get_priv(bus); - debug("%s\n", __func__); + dev_dbg(slave, "\n"); /* Disable the SPI hardware */ return stm32_spi_disable(priv); @@ -227,7 +230,7 @@ static void stm32_spi_stopxfer(struct udevice *dev) u32 cr1, sr; int ret; - debug("%s\n", __func__); + dev_dbg(dev, "\n"); cr1 = readl(priv->base + STM32_SPI_CR1); @@ -255,7 +258,7 @@ static int stm32_spi_set_cs(struct udevice *dev, unsigned int cs, bool enable) { struct stm32_spi_priv *priv = dev_get_priv(dev); - debug("%s: cs=%d enable=%d\n", __func__, cs, enable); + dev_dbg(dev, "cs=%d enable=%d\n", cs, enable); if (cs >= MAX_CS_COUNT) return -ENODEV; @@ -274,7 +277,7 @@ static int stm32_spi_set_mode(struct udevice *bus, uint mode) struct stm32_spi_priv *priv = dev_get_priv(bus); u32 cfg2_clrb = 0, cfg2_setb = 0; - debug("%s: mode=%d\n", __func__, mode); + dev_dbg(bus, "mode=%d\n", mode); if (mode & SPI_CPOL) cfg2_setb |= SPI_CFG2_CPOL; @@ -330,7 +333,7 @@ static int stm32_spi_set_speed(struct udevice *bus, uint hz) u32 mbrdiv; long div; - debug("%s: hz=%d\n", __func__, hz); + dev_dbg(bus, "hz=%d\n", hz); if (priv->cur_hz == hz) return 0; @@ -404,8 +407,8 @@ static int stm32_spi_xfer(struct udevice *slave, unsigned int bitlen, stm32_spi_enable(priv); } - debug("%s: priv->tx_len=%d priv->rx_len=%d\n", __func__, - priv->tx_len, priv->rx_len); + dev_dbg(bus, "priv->tx_len=%d priv->rx_len=%d\n", + priv->tx_len, priv->rx_len); slave_plat = dev_get_parent_plat(slave); if (flags & SPI_XFER_BEGIN) @@ -477,7 +480,7 @@ static int stm32_spi_get_fifo_size(struct udevice *dev) stm32_spi_disable(priv); - debug("%s %d x 8-bit fifo size\n", __func__, count); + dev_dbg(dev, "%d x 8-bit fifo size\n", count); return count; } @@ -522,7 +525,7 @@ static int stm32_spi_probe(struct udevice *dev) ret = gpio_request_list_by_name(dev, "cs-gpios", priv->cs_gpios, ARRAY_SIZE(priv->cs_gpios), 0); if (ret < 0) { - pr_err("Can't get %s cs gpios: %d", dev->name, ret); + dev_err(dev, "Can't get cs gpios: %d", ret); goto reset_err; } diff --git a/drivers/sysreset/sysreset_ast.c b/drivers/sysreset/sysreset_ast.c index ee941c77706..d747ed00a7f 100644 --- a/drivers/sysreset/sysreset_ast.c +++ b/drivers/sysreset/sysreset_ast.c @@ -12,6 +12,7 @@ #include <asm/io.h> #include <asm/arch/wdt.h> #include <linux/err.h> +#include <hang.h> static int ast_sysreset_request(struct udevice *dev, enum sysreset_t type) { @@ -33,11 +34,15 @@ static int ast_sysreset_request(struct udevice *dev, enum sysreset_t type) return -EPROTONOSUPPORT; } +#if !defined(CONFIG_SPL_BUILD) ret = wdt_expire_now(wdt, reset_mode); if (ret) { debug("Sysreset failed: %d", ret); return ret; } +#else + hang(); +#endif return -EINPROGRESS; } diff --git a/drivers/timer/andes_plmt_timer.c b/drivers/timer/andes_plmt_timer.c index db2cf86f638..a3797b22c74 100644 --- a/drivers/timer/andes_plmt_timer.c +++ b/drivers/timer/andes_plmt_timer.c @@ -18,11 +18,30 @@ /* mtime register */ #define MTIME_REG(base) ((ulong)(base)) -static u64 andes_plmt_get_count(struct udevice *dev) +static u64 notrace andes_plmt_get_count(struct udevice *dev) { return readq((void __iomem *)MTIME_REG(dev_get_priv(dev))); } +#if CONFIG_IS_ENABLED(RISCV_MMODE) && IS_ENABLED(CONFIG_TIMER_EARLY) +/** + * timer_early_get_rate() - Get the timer rate before driver model + */ +unsigned long notrace timer_early_get_rate(void) +{ + return RISCV_MMODE_TIMER_FREQ; +} + +/** + * timer_early_get_count() - Get the timer count before driver model + * + */ +u64 notrace timer_early_get_count(void) +{ + return readq((void __iomem *)MTIME_REG(RISCV_MMODE_TIMERBASE)); +} +#endif + static const struct timer_ops andes_plmt_ops = { .get_count = andes_plmt_get_count, }; diff --git a/drivers/timer/mtk_timer.c b/drivers/timer/mtk_timer.c index 448a76a7e1f..f6b97f868c7 100644 --- a/drivers/timer/mtk_timer.c +++ b/drivers/timer/mtk_timer.c @@ -61,6 +61,16 @@ static int mtk_timer_probe(struct udevice *dev) if (!uc_priv->clock_rate) return -EINVAL; + /* + * Initialize the timer: + * 1. set clock source to system clock with clock divider setting to 1 + * 2. set timer mode to free running + * 3. reset timer counter to 0 then enable the timer + */ + writel(GPT4_CLK_SYS | GPT4_CLK_DIV1, priv->base + MTK_GPT4_CLK); + writel(GPT4_FREERUN | GPT4_CLEAR | GPT4_ENABLE, + priv->base + MTK_GPT4_CTRL); + return 0; } diff --git a/drivers/timer/riscv_timer.c b/drivers/timer/riscv_timer.c index 21ae1840571..3627ed79b81 100644 --- a/drivers/timer/riscv_timer.c +++ b/drivers/timer/riscv_timer.c @@ -16,7 +16,7 @@ #include <timer.h> #include <asm/csr.h> -static u64 riscv_timer_get_count(struct udevice *dev) +static u64 notrace riscv_timer_get_count(struct udevice *dev) { __maybe_unused u32 hi, lo; @@ -31,6 +31,25 @@ static u64 riscv_timer_get_count(struct udevice *dev) return ((u64)hi << 32) | lo; } +#if CONFIG_IS_ENABLED(RISCV_SMODE) && IS_ENABLED(CONFIG_TIMER_EARLY) +/** + * timer_early_get_rate() - Get the timer rate before driver model + */ +unsigned long notrace timer_early_get_rate(void) +{ + return RISCV_SMODE_TIMER_FREQ; +} + +/** + * timer_early_get_count() - Get the timer count before driver model + * + */ +u64 notrace timer_early_get_count(void) +{ + return riscv_timer_get_count(NULL); +} +#endif + static int riscv_timer_probe(struct udevice *dev) { struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); diff --git a/drivers/timer/sifive_clint_timer.c b/drivers/timer/sifive_clint_timer.c index de23b85404b..de7b4b95c9e 100644 --- a/drivers/timer/sifive_clint_timer.c +++ b/drivers/timer/sifive_clint_timer.c @@ -15,11 +15,30 @@ /* mtime register */ #define MTIME_REG(base) ((ulong)(base) + 0xbff8) -static u64 sifive_clint_get_count(struct udevice *dev) +static u64 notrace sifive_clint_get_count(struct udevice *dev) { return readq((void __iomem *)MTIME_REG(dev_get_priv(dev))); } +#if CONFIG_IS_ENABLED(RISCV_MMODE) && IS_ENABLED(CONFIG_TIMER_EARLY) +/** + * timer_early_get_rate() - Get the timer rate before driver model + */ +unsigned long notrace timer_early_get_rate(void) +{ + return RISCV_MMODE_TIMER_FREQ; +} + +/** + * timer_early_get_count() - Get the timer count before driver model + * + */ +u64 notrace timer_early_get_count(void) +{ + return readq((void __iomem *)MTIME_REG(RISCV_MMODE_TIMERBASE)); +} +#endif + static const struct timer_ops sifive_clint_ops = { .get_count = sifive_clint_get_count, }; diff --git a/drivers/timer/stm32_timer.c b/drivers/timer/stm32_timer.c index 215334f1b8c..e34f5202fc6 100644 --- a/drivers/timer/stm32_timer.c +++ b/drivers/timer/stm32_timer.c @@ -4,6 +4,8 @@ * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics. */ +#define LOG_CATEGORY UCLASS_TIMER + #include <common.h> #include <clk.h> #include <dm.h> diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index a3f8eeba5d8..d782eb806a1 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -199,7 +199,7 @@ config PANEL config SIMPLE_PANEL bool "Enable simple panel support" - depends on PANEL + depends on PANEL && BACKLIGHT default y help This turns on a simple panel driver that enables a compatible @@ -449,6 +449,15 @@ config VIDEO_LCD_SSD2828_RESET The reset pin of SSD2828 chip. This takes a string in the format understood by 'name_to_gpio' function, e.g. PH1 for pin 1 of port H. +config VIDEO_LCD_TDO_TL070WSH30 + bool "TDO TL070WSH30 DSI LCD panel support" + depends on DM_VIDEO + select VIDEO_MIPI_DSI + default n + help + Say Y here if you want to enable support for TDO TL070WSH30 + 1024x600 DSI video mode panel. + config VIDEO_LCD_HITACHI_TX18D42VM bool "Hitachi tx18d42vm LVDS LCD panel support" depends on VIDEO diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 76e3914678d..494e414a311 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -56,6 +56,7 @@ obj-$(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM) += hitachi_tx18d42vm_lcd.o obj-$(CONFIG_VIDEO_LCD_ORISETECH_OTM8009A) += orisetech_otm8009a.o obj-$(CONFIG_VIDEO_LCD_RAYDIUM_RM68200) += raydium-rm68200.o obj-$(CONFIG_VIDEO_LCD_SSD2828) += ssd2828.o +obj-$(CONFIG_VIDEO_LCD_TDO_TL070WSH30) += tdo-tl070wsh30.o obj-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o obj-${CONFIG_VIDEO_MESON} += meson/ obj-${CONFIG_VIDEO_MIPI_DSI} += mipi_dsi.o diff --git a/drivers/video/seps525.c b/drivers/video/seps525.c index 369e5e6afc8..74c8721e1e1 100644 --- a/drivers/video/seps525.c +++ b/drivers/video/seps525.c @@ -299,7 +299,7 @@ static int seps525_probe(struct udevice *dev) static int seps525_bind(struct udevice *dev) { - struct video_uc_platdata *plat = dev_get_uclass_platdata(dev); + struct video_uc_plat *plat = dev_get_uclass_plat(dev); plat->size = WIDTH * HEIGHT * 16; @@ -320,8 +320,8 @@ U_BOOT_DRIVER(seps525_video) = { .id = UCLASS_VIDEO, .of_match = seps525_ids, .ops = &seps525_ops, - .platdata_auto_alloc_size = sizeof(struct video_uc_platdata), + .plat_auto = sizeof(struct video_uc_plat), .bind = seps525_bind, .probe = seps525_probe, - .priv_auto_alloc_size = sizeof(struct seps525_priv), + .priv_auto = sizeof(struct seps525_priv), }; diff --git a/drivers/video/stm32/stm32_dsi.c b/drivers/video/stm32/stm32_dsi.c index 266623b8766..8891ca4b784 100644 --- a/drivers/video/stm32/stm32_dsi.c +++ b/drivers/video/stm32/stm32_dsi.c @@ -8,6 +8,8 @@ * drivers/gpu/drm/stm/dw_mipi_dsi-stm.c. */ +#define LOG_CATEGORY UCLASS_VIDEO_BRIDGE + #include <common.h> #include <clk.h> #include <dm.h> @@ -133,7 +135,7 @@ static enum dsi_color dsi_color_from_mipi(u32 fmt) case MIPI_DSI_FMT_RGB565: return DSI_RGB565_CONF1; default: - pr_err("MIPI color invalid, so we use rgb888\n"); + log_err("MIPI color invalid, so we use rgb888\n"); } return DSI_RGB888; } @@ -213,14 +215,14 @@ static int dsi_phy_init(void *priv_data) u32 val; int ret; - debug("Initialize DSI physical layer\n"); + dev_dbg(dev, "Initialize DSI physical layer\n"); /* Enable the regulator */ dsi_set(dsi, DSI_WRPCR, WRPCR_REGEN | WRPCR_BGREN); ret = readl_poll_timeout(dsi->base + DSI_WISR, val, val & WISR_RRS, TIMEOUT_US); if (ret) { - debug("!TIMEOUT! waiting REGU\n"); + dev_dbg(dev, "!TIMEOUT! waiting REGU\n"); return ret; } @@ -229,7 +231,7 @@ static int dsi_phy_init(void *priv_data) ret = readl_poll_timeout(dsi->base + DSI_WISR, val, val & WISR_PLLLS, TIMEOUT_US); if (ret) { - debug("!TIMEOUT! waiting PLL\n"); + dev_dbg(dev, "!TIMEOUT! waiting PLL\n"); return ret; } @@ -242,8 +244,8 @@ static void dsi_phy_post_set_mode(void *priv_data, unsigned long mode_flags) struct udevice *dev = device->dev; struct stm32_dsi_priv *dsi = dev_get_priv(dev); - debug("Set mode %p enable %ld\n", dsi, - mode_flags & MIPI_DSI_MODE_VIDEO); + dev_dbg(dev, "Set mode %p enable %ld\n", dsi, + mode_flags & MIPI_DSI_MODE_VIDEO); if (!dsi) return; @@ -325,8 +327,8 @@ static int dsi_get_lane_mbps(void *priv_data, struct display_timing *timings, *lane_mbps = pll_out_khz / 1000; - debug("pll_in %ukHz pll_out %ukHz lane_mbps %uMHz\n", - pll_in_khz, pll_out_khz, *lane_mbps); + dev_dbg(dev, "pll_in %ukHz pll_out %ukHz lane_mbps %uMHz\n", + pll_in_khz, pll_out_khz, *lane_mbps); return 0; } diff --git a/drivers/video/stm32/stm32_ltdc.c b/drivers/video/stm32/stm32_ltdc.c index dc10b8cfc11..f55a39498e0 100644 --- a/drivers/video/stm32/stm32_ltdc.c +++ b/drivers/video/stm32/stm32_ltdc.c @@ -5,6 +5,8 @@ * Yannick Fertre <yannick.fertre@st.com> for STMicroelectronics. */ +#define LOG_CATEGORY UCLASS_VIDEO + #include <common.h> #include <clk.h> #include <display.h> @@ -176,13 +178,13 @@ static u32 stm32_ltdc_get_pixel_format(enum video_log2_bpp l2bpp) case VIDEO_BPP2: case VIDEO_BPP4: default: - pr_warn("%s: warning %dbpp not supported yet, %dbpp instead\n", - __func__, VNBITS(l2bpp), VNBITS(VIDEO_BPP16)); + log_warning("warning %dbpp not supported yet, %dbpp instead\n", + VNBITS(l2bpp), VNBITS(VIDEO_BPP16)); pf = PF_RGB565; break; } - debug("%s: %d bpp -> ltdc pf %d\n", __func__, VNBITS(l2bpp), pf); + log_debug("%d bpp -> ltdc pf %d\n", VNBITS(l2bpp), pf); return (u32)pf; } @@ -249,7 +251,7 @@ static void stm32_ltdc_set_mode(struct stm32_ltdc_priv *priv, /* Signal polarities */ val = 0; - debug("%s: timing->flags 0x%08x\n", __func__, timings->flags); + log_debug("timing->flags 0x%08x\n", timings->flags); if (timings->flags & DISPLAY_FLAGS_HSYNC_HIGH) val |= GCR_HSPOL; if (timings->flags & DISPLAY_FLAGS_VSYNC_HIGH) @@ -379,8 +381,8 @@ static int stm32_ltdc_probe(struct udevice *dev) dev_warn(dev, "fail to set pixel clock %d hz\n", timings.pixelclock.typ); - debug("%s: Set pixel clock req %d hz get %ld hz\n", __func__, - timings.pixelclock.typ, clk_get_rate(&pclk)); + dev_dbg(dev, "Set pixel clock req %d hz get %ld hz\n", + timings.pixelclock.typ, clk_get_rate(&pclk)); ret = reset_get_by_index(dev, 0, &rst); if (ret) { @@ -394,12 +396,13 @@ static int stm32_ltdc_probe(struct udevice *dev) if (IS_ENABLED(CONFIG_VIDEO_BRIDGE)) { ret = uclass_get_device(UCLASS_VIDEO_BRIDGE, 0, &bridge); if (ret) - debug("No video bridge, or no backlight on bridge\n"); + dev_dbg(dev, + "No video bridge, or no backlight on bridge\n"); if (bridge) { ret = video_bridge_attach(bridge); if (ret) { - dev_err(dev, "fail to attach bridge\n"); + dev_err(bridge, "fail to attach bridge\n"); return ret; } } @@ -414,12 +417,12 @@ static int stm32_ltdc_probe(struct udevice *dev) priv->crop_h = timings.vactive.typ; priv->alpha = 0xFF; - debug("%s: %dx%d %dbpp frame buffer at 0x%lx\n", __func__, - timings.hactive.typ, timings.vactive.typ, - VNBITS(priv->l2bpp), uc_plat->base); - debug("%s: crop %d,%d %dx%d bg 0x%08x alpha %d\n", __func__, - priv->crop_x, priv->crop_y, priv->crop_w, priv->crop_h, - priv->bg_col_argb, priv->alpha); + dev_dbg(dev, "%dx%d %dbpp frame buffer at 0x%lx\n", + timings.hactive.typ, timings.vactive.typ, + VNBITS(priv->l2bpp), uc_plat->base); + dev_dbg(dev, "crop %d,%d %dx%d bg 0x%08x alpha %d\n", + priv->crop_x, priv->crop_y, priv->crop_w, priv->crop_h, + priv->bg_col_argb, priv->alpha); /* Configure & start LTDC */ stm32_ltdc_set_mode(priv, &timings); @@ -457,7 +460,7 @@ static int stm32_ltdc_bind(struct udevice *dev) uc_plat->size = CONFIG_VIDEO_STM32_MAX_XRES * CONFIG_VIDEO_STM32_MAX_YRES * (CONFIG_VIDEO_STM32_MAX_BPP >> 3); - debug("%s: frame buffer max size %d bytes\n", __func__, uc_plat->size); + dev_dbg(dev, "frame buffer max size %d bytes\n", uc_plat->size); return 0; } diff --git a/drivers/video/tdo-tl070wsh30.c b/drivers/video/tdo-tl070wsh30.c new file mode 100644 index 00000000000..813b87a6817 --- /dev/null +++ b/drivers/video/tdo-tl070wsh30.c @@ -0,0 +1,155 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 BayLibre, SAS + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ +#include <common.h> +#include <backlight.h> +#include <dm.h> +#include <mipi_dsi.h> +#include <panel.h> +#include <asm/gpio.h> +#include <dm/device_compat.h> +#include <linux/delay.h> +#include <power/regulator.h> + +struct tl070wsh30_panel_priv { + struct udevice *reg; + struct udevice *backlight; + struct gpio_desc reset; +}; + +static const struct display_timing default_timing = { + .pixelclock.typ = 47250000, + .hactive.typ = 1024, + .hfront_porch.typ = 46, + .hback_porch.typ = 100, + .hsync_len.typ = 80, + .vactive.typ = 600, + .vfront_porch.typ = 5, + .vback_porch.typ = 20, + .vsync_len.typ = 5, + .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH, +}; + +static int tl070wsh30_panel_enable_backlight(struct udevice *dev) +{ + struct mipi_dsi_panel_plat *plat = dev_get_plat(dev); + struct mipi_dsi_device *device = plat->device; + struct tl070wsh30_panel_priv *priv = dev_get_priv(dev); + int ret; + + ret = mipi_dsi_attach(device); + if (ret < 0) + return ret; + + ret = mipi_dsi_dcs_exit_sleep_mode(device); + if (ret) + return ret; + + mdelay(200); + + ret = mipi_dsi_dcs_set_display_on(device); + if (ret) + return ret; + + mdelay(20); + + ret = backlight_enable(priv->backlight); + if (ret) + return ret; + + return 0; +} + +static int tl070wsh30_panel_get_display_timing(struct udevice *dev, + struct display_timing *timings) +{ + memcpy(timings, &default_timing, sizeof(*timings)); + + return 0; +} + +static int tl070wsh30_panel_of_to_plat(struct udevice *dev) +{ + struct tl070wsh30_panel_priv *priv = dev_get_priv(dev); + int ret; + + if (IS_ENABLED(CONFIG_DM_REGULATOR)) { + ret = device_get_supply_regulator(dev, "power-supply", + &priv->reg); + if (ret && ret != -ENOENT) { + dev_err(dev, "Warning: cannot get power supply\n"); + return ret; + } + } + + ret = gpio_request_by_name(dev, "reset-gpios", 0, &priv->reset, + GPIOD_IS_OUT); + if (ret) { + dev_err(dev, "Warning: cannot get reset GPIO\n"); + if (ret != -ENOENT) + return ret; + } + + ret = uclass_get_device_by_phandle(UCLASS_PANEL_BACKLIGHT, dev, + "backlight", &priv->backlight); + if (ret) { + dev_err(dev, "Cannot get backlight: ret=%d\n", ret); + return ret; + } + + return 0; +} + +static int tl070wsh30_panel_probe(struct udevice *dev) +{ + struct tl070wsh30_panel_priv *priv = dev_get_priv(dev); + struct mipi_dsi_panel_plat *plat = dev_get_plat(dev); + int ret; + + if (IS_ENABLED(CONFIG_DM_REGULATOR) && priv->reg) { + ret = regulator_set_enable(priv->reg, true); + if (ret) + return ret; + } + + mdelay(10); + + /* reset panel */ + dm_gpio_set_value(&priv->reset, true); + + mdelay(10); + + dm_gpio_set_value(&priv->reset, false); + + /* fill characteristics of DSI data link */ + plat->lanes = 4; + plat->format = MIPI_DSI_FMT_RGB888; + plat->mode_flags = MIPI_DSI_MODE_VIDEO | + MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM; + + return 0; +} + +static const struct panel_ops tl070wsh30_panel_ops = { + .enable_backlight = tl070wsh30_panel_enable_backlight, + .get_display_timing = tl070wsh30_panel_get_display_timing, +}; + +static const struct udevice_id tl070wsh30_panel_ids[] = { + { .compatible = "tdo,tl070wsh30" }, + { } +}; + +U_BOOT_DRIVER(tl070wsh30_panel) = { + .name = "tl070wsh30_panel", + .id = UCLASS_PANEL, + .of_match = tl070wsh30_panel_ids, + .ops = &tl070wsh30_panel_ops, + .of_to_plat = tl070wsh30_panel_of_to_plat, + .probe = tl070wsh30_panel_probe, + .plat_auto = sizeof(struct mipi_dsi_panel_plat), + .priv_auto = sizeof(struct tl070wsh30_panel_priv), +}; diff --git a/drivers/video/ti/tilcdc-panel.c b/drivers/video/ti/tilcdc-panel.c index b90dfae4ae9..df95086a515 100644 --- a/drivers/video/ti/tilcdc-panel.c +++ b/drivers/video/ti/tilcdc-panel.c @@ -165,7 +165,7 @@ U_BOOT_DRIVER(tilcdc_panel) = { .id = UCLASS_PANEL, .of_match = tilcdc_panel_ids, .ops = &tilcdc_panel_ops, - .ofdata_to_platdata = tilcdc_panel_of_to_plat, + .of_to_plat = tilcdc_panel_of_to_plat, .probe = tilcdc_panel_probe, .remove = tilcdc_panel_remove, .priv_auto = sizeof(struct tilcdc_panel_priv), diff --git a/drivers/video/ti/tilcdc.c b/drivers/video/ti/tilcdc.c index d13cc11801d..814126af666 100644 --- a/drivers/video/ti/tilcdc.c +++ b/drivers/video/ti/tilcdc.c @@ -155,7 +155,7 @@ static ulong tilcdc_set_pixel_clk_rate(struct udevice *dev, ulong rate) static int tilcdc_remove(struct udevice *dev) { - struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev); + struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev); struct tilcdc_priv *priv = dev_get_priv(dev); uc_plat->base -= 0x20; @@ -167,7 +167,7 @@ static int tilcdc_remove(struct udevice *dev) static int tilcdc_probe(struct udevice *dev) { - struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev); + struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev); struct video_priv *uc_priv = dev_get_uclass_priv(dev); struct tilcdc_priv *priv = dev_get_priv(dev); struct tilcdc_regs *regs = priv->regs; @@ -399,7 +399,7 @@ static int tilcdc_of_to_plat(struct udevice *dev) static int tilcdc_bind(struct udevice *dev) { - struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev); + struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev); uc_plat->size = ((LCDC_MAX_WIDTH * LCDC_MAX_HEIGHT * (1 << LCDC_MAX_LOG2_BPP)) >> 3) + 0x20; @@ -418,7 +418,7 @@ U_BOOT_DRIVER(tilcdc) = { .id = UCLASS_VIDEO, .of_match = tilcdc_ids, .bind = tilcdc_bind, - .ofdata_to_platdata = tilcdc_of_to_plat, + .of_to_plat = tilcdc_of_to_plat, .probe = tilcdc_probe, .remove = tilcdc_remove, .priv_auto = sizeof(struct tilcdc_priv) diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 4532a40e458..d5edabf3eff 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -86,6 +86,15 @@ config WDT_ASPEED It currently does not support Boot Flash Addressing Mode Detection or Second Boot. +config WDT_AST2600 + bool "Aspeed AST2600 watchdog timer support" + depends on WDT + default y if ASPEED_AST2600 + help + Select this to enable watchdog timer for Aspeed ast2500/ast2400 devices. + The watchdog timer is stopped when initialized. It performs reset, either + full SoC reset or CPU or just some peripherals, based on the flags. + config WDT_AT91 bool "AT91 watchdog timer support" depends on WDT diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 01b8231f2bf..cbb6d8407cc 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -19,6 +19,7 @@ obj-$(CONFIG_$(SPL_TPL_)WDT) += wdt-uclass.o obj-$(CONFIG_WDT_SANDBOX) += sandbox_wdt.o obj-$(CONFIG_WDT_ARMADA_37XX) += armada-37xx-wdt.o obj-$(CONFIG_WDT_ASPEED) += ast_wdt.o +obj-$(CONFIG_WDT_AST2600) += ast2600_wdt.o obj-$(CONFIG_WDT_BCM6345) += bcm6345_wdt.o obj-$(CONFIG_WDT_CORTINA) += cortina_wdt.o obj-$(CONFIG_WDT_ORION) += orion_wdt.o diff --git a/drivers/watchdog/ast2600_wdt.c b/drivers/watchdog/ast2600_wdt.c new file mode 100644 index 00000000000..bc9842089be --- /dev/null +++ b/drivers/watchdog/ast2600_wdt.c @@ -0,0 +1,110 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2020 Aspeed Technology, Inc + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <log.h> +#include <wdt.h> +#include <asm/io.h> +#include <asm/arch/wdt_ast2600.h> +#include <linux/err.h> + +struct ast2600_wdt_priv { + struct ast2600_wdt *regs; +}; + +static int ast2600_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags) +{ + struct ast2600_wdt_priv *priv = dev_get_priv(dev); + struct ast2600_wdt *wdt = priv->regs; + + /* WDT counts in the 1MHz frequency, namely 1us */ + writel((u32)(timeout_ms * 1000), &wdt->counter_reload_val); + writel(WDT_COUNTER_RESTART_VAL, &wdt->counter_restart); + writel(WDT_CTRL_EN | WDT_CTRL_RESET, &wdt->ctrl); + + return 0; +} + +static int ast2600_wdt_stop(struct udevice *dev) +{ + struct ast2600_wdt_priv *priv = dev_get_priv(dev); + struct ast2600_wdt *wdt = priv->regs; + + clrbits_le32(&wdt->ctrl, WDT_CTRL_EN); + + writel(WDT_RESET_MASK1_DEFAULT, &wdt->reset_mask1); + writel(WDT_RESET_MASK2_DEFAULT, &wdt->reset_mask2); + + return 0; +} + +static int ast2600_wdt_reset(struct udevice *dev) +{ + struct ast2600_wdt_priv *priv = dev_get_priv(dev); + struct ast2600_wdt *wdt = priv->regs; + + writel(WDT_COUNTER_RESTART_VAL, &wdt->counter_restart); + + return 0; +} + +static int ast2600_wdt_expire_now(struct udevice *dev, ulong flags) +{ + int ret; + struct ast2600_wdt_priv *priv = dev_get_priv(dev); + struct ast2600_wdt *wdt = priv->regs; + + ret = ast2600_wdt_start(dev, 1, flags); + if (ret) + return ret; + + while (readl(&wdt->ctrl) & WDT_CTRL_EN) + ; + + return ast2600_wdt_stop(dev); +} + +static int ast2600_wdt_of_to_plat(struct udevice *dev) +{ + struct ast2600_wdt_priv *priv = dev_get_priv(dev); + + priv->regs = dev_read_addr_ptr(dev); + if (!priv->regs) + return -EINVAL; + + return 0; +} + +static const struct wdt_ops ast2600_wdt_ops = { + .start = ast2600_wdt_start, + .reset = ast2600_wdt_reset, + .stop = ast2600_wdt_stop, + .expire_now = ast2600_wdt_expire_now, +}; + +static const struct udevice_id ast2600_wdt_ids[] = { + { .compatible = "aspeed,ast2600-wdt" }, + { } +}; + +static int ast2600_wdt_probe(struct udevice *dev) +{ + debug("%s() wdt%u\n", __func__, dev_seq(dev)); + ast2600_wdt_stop(dev); + + return 0; +} + +U_BOOT_DRIVER(ast2600_wdt) = { + .name = "ast2600_wdt", + .id = UCLASS_WDT, + .of_match = ast2600_wdt_ids, + .probe = ast2600_wdt_probe, + .priv_auto = sizeof(struct ast2600_wdt_priv), + .of_to_plat = ast2600_wdt_of_to_plat, + .ops = &ast2600_wdt_ops, +}; diff --git a/drivers/watchdog/stm32mp_wdt.c b/drivers/watchdog/stm32mp_wdt.c index 53586fdbfc8..4be616c1b6b 100644 --- a/drivers/watchdog/stm32mp_wdt.c +++ b/drivers/watchdog/stm32mp_wdt.c @@ -3,6 +3,8 @@ * Copyright (C) 2019, STMicroelectronics - All Rights Reserved */ +#define LOG_CATEGORY UCLASS_WDT + #include <common.h> #include <clk.h> #include <dm.h> @@ -10,6 +12,7 @@ #include <syscon.h> #include <wdt.h> #include <asm/io.h> +#include <dm/device_compat.h> #include <linux/bitops.h> #include <linux/iopoll.h> @@ -77,7 +80,7 @@ static int stm32mp_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags) val & (SR_PVU | SR_RVU), CONFIG_SYS_HZ); if (ret < 0) { - pr_err("Updating IWDG registers timeout"); + dev_err(dev, "Updating IWDG registers timeout"); return -ETIMEDOUT; } @@ -90,7 +93,7 @@ static int stm32mp_wdt_probe(struct udevice *dev) struct clk clk; int ret; - debug("IWDG init\n"); + dev_dbg(dev, "IWDG init\n"); priv->base = dev_read_addr(dev); if (priv->base == FDT_ADDR_T_NONE) @@ -112,7 +115,7 @@ static int stm32mp_wdt_probe(struct udevice *dev) priv->wdt_clk_rate = clk_get_rate(&clk); - debug("IWDG init done\n"); + dev_dbg(dev, "IWDG init done\n"); return 0; } diff --git a/drivers/xen/hypervisor.c b/drivers/xen/hypervisor.c index 178c206f5bf..25608948323 100644 --- a/drivers/xen/hypervisor.c +++ b/drivers/xen/hypervisor.c @@ -232,7 +232,7 @@ void clear_evtchn(uint32_t port) synch_clear_bit(port, &s->evtchn_pending[0]); } -void xen_init(void) +int xen_init(void) { debug("%s\n", __func__); @@ -240,6 +240,8 @@ void xen_init(void) init_events(); init_xenbus(); init_gnttab(); + + return 0; } void xen_fini(void) |