diff options
Diffstat (limited to 'drivers')
149 files changed, 11008 insertions, 2092 deletions
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig index 4fbb63a148a..29ceab849c0 100644 --- a/drivers/ata/Kconfig +++ b/drivers/ata/Kconfig @@ -1,6 +1,7 @@ config AHCI bool "Support SATA controllers with driver model" depends on DM + select BLK help This enables a uclass for disk controllers in U-Boot. Various driver types can use this, such as AHCI/SATA. It does not provide any standard @@ -9,6 +10,7 @@ config AHCI config SATA bool "Support SATA controllers" + select BLK help This enables support for SATA (Serial Advanced Technology Attachment), a serial bus standard for connecting to hard drives and diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig index 5283d8981e0..750b0bd2082 100644 --- a/drivers/block/Kconfig +++ b/drivers/block/Kconfig @@ -1,8 +1,5 @@ config BLK - bool # "Support block devices" - depends on DM - def_bool y if MMC || USB || SCSI || NVME || IDE || AHCI || SATA - def_bool y if EFI_MEDIA || VIRTIO_BLK || PVBLOCK + bool help Enable support for block devices, such as SCSI, MMC and USB flash sticks. These provide a block-level interface which permits @@ -100,6 +97,7 @@ config TPL_BLOCK_CACHE config EFI_MEDIA bool "Support EFI media drivers" default y if EFI || SANDBOX + select BLK help Enable this to support media devices on top of UEFI. This enables just the uclass so you also need a specific driver to make this do @@ -139,6 +137,7 @@ endif # EFI_MEDIA config IDE bool "Support IDE controllers" + select BLK help Enables support for IDE (Integrated Drive Electronics) hard drives. This allows access to raw blocks and filesystems on an IDE drive @@ -148,7 +147,7 @@ config IDE if IDE config SYS_IDE_MAXBUS - hex "Maximumm number of IDE buses" + hex "Maximum number of IDE buses" default 2 help This is the number of IDE buses provided by the board. Each one diff --git a/drivers/button/button-qcom-pmic.c b/drivers/button/button-qcom-pmic.c index ad7fed3ddaa..f9f0948ae09 100644 --- a/drivers/button/button-qcom-pmic.c +++ b/drivers/button/button-qcom-pmic.c @@ -15,6 +15,7 @@ #include <power/pmic.h> #include <spmi/spmi.h> #include <linux/bitops.h> +#include <time.h> #define REG_TYPE 0x4 #define REG_SUBTYPE 0x5 @@ -31,6 +32,7 @@ struct qcom_pmic_btn_priv { u32 status_bit; int code; struct udevice *pmic; + ulong last_release_time; }; #define PON_INT_RT_STS 0x10 @@ -42,13 +44,21 @@ struct qcom_pmic_btn_priv { static enum button_state_t qcom_pwrkey_get_state(struct udevice *dev) { struct qcom_pmic_btn_priv *priv = dev_get_priv(dev); + bool pressed; + int reg; - int reg = pmic_reg_read(priv->pmic, priv->base + PON_INT_RT_STS); + if (get_timer_us(0) - priv->last_release_time < 25000) + return BUTTON_OFF; + reg = pmic_reg_read(priv->pmic, priv->base + PON_INT_RT_STS); if (reg < 0) return 0; - return (reg & BIT(priv->status_bit)) != 0; + pressed = !!(reg & BIT(priv->status_bit)); + if (!pressed) + priv->last_release_time = get_timer_us(0); + + return pressed; } static int qcom_pwrkey_get_code(struct udevice *dev) diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index e631f79e4dd..e412c92cafc 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_TARGET_MT7629) += clk-mt7629.o obj-$(CONFIG_TARGET_MT7986) += clk-mt7986.o obj-$(CONFIG_TARGET_MT7981) += clk-mt7981.o obj-$(CONFIG_TARGET_MT7988) += clk-mt7988.o +obj-$(CONFIG_TARGET_MT7987) += clk-mt7987.o obj-$(CONFIG_TARGET_MT8183) += clk-mt8183.o obj-$(CONFIG_TARGET_MT8365) += clk-mt8365.o obj-$(CONFIG_TARGET_MT8516) += clk-mt8516.o diff --git a/drivers/clk/mediatek/clk-mt7629.c b/drivers/clk/mediatek/clk-mt7629.c index 380ab9b9b0b..94fc5e51456 100644 --- a/drivers/clk/mediatek/clk-mt7629.c +++ b/drivers/clk/mediatek/clk-mt7629.c @@ -574,6 +574,18 @@ static const struct mtk_clk_tree mt7629_clk_tree = { .muxes = top_muxes, }; +static const struct mtk_clk_tree mt7629_peri_clk_tree = { + .xtal_rate = 40 * MHZ, + .xtal2_rate = 20 * MHZ, + .gates_offs = CLK_PERI_PWM1_PD, + .fdivs_offs = CLK_TOP_TO_USB3_SYS, + .muxes_offs = CLK_TOP_AXI_SEL, + .plls = apmixed_plls, + .fclks = top_fixed_clks, + .fdivs = top_fixed_divs, + .muxes = top_muxes, +}; + static int mt7629_mcucfg_probe(struct udevice *dev) { void __iomem *base; @@ -619,7 +631,7 @@ static int mt7629_infracfg_probe(struct udevice *dev) static int mt7629_pericfg_probe(struct udevice *dev) { - return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, peri_cgs); + return mtk_common_clk_gate_init(dev, &mt7629_peri_clk_tree, peri_cgs); } static int mt7629_ethsys_probe(struct udevice *dev) diff --git a/drivers/clk/mediatek/clk-mt7981.c b/drivers/clk/mediatek/clk-mt7981.c index 97073918006..60814652322 100644 --- a/drivers/clk/mediatek/clk-mt7981.c +++ b/drivers/clk/mediatek/clk-mt7981.c @@ -359,6 +359,7 @@ static const struct mtk_parent infra_pcie_parents[] = { .id = _id, .mux_reg = (_reg) + 0x8, \ .mux_set_reg = (_reg) + 0x0, .mux_clr_reg = (_reg) + 0x4, \ .mux_shift = _shift, .mux_mask = BIT(_width) - 1, \ + .gate_shift = -1, .upd_shift = -1, \ .parent_flags = _parents, .num_parents = ARRAY_SIZE(_parents), \ .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_MIXED, \ } diff --git a/drivers/clk/mediatek/clk-mt7986.c b/drivers/clk/mediatek/clk-mt7986.c index c5cc77243d0..f9d6f9c1749 100644 --- a/drivers/clk/mediatek/clk-mt7986.c +++ b/drivers/clk/mediatek/clk-mt7986.c @@ -366,6 +366,7 @@ static const struct mtk_parent infra_pcie_parents[] = { .id = _id, .mux_reg = (_reg) + 0x8, \ .mux_set_reg = (_reg) + 0x0, .mux_clr_reg = (_reg) + 0x4, \ .mux_shift = _shift, .mux_mask = BIT(_width) - 1, \ + .gate_shift = -1, .upd_shift = -1, \ .parent_flags = _parents, .num_parents = ARRAY_SIZE(_parents), \ .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_MIXED, \ } diff --git a/drivers/clk/mediatek/clk-mt7987.c b/drivers/clk/mediatek/clk-mt7987.c new file mode 100644 index 00000000000..173686a38e8 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt7987.c @@ -0,0 +1,848 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * MediaTek clock driver for MT7987 SoC + * + * Copyright (C) 2024 MediaTek Inc. + * Author: Sam Shih <sam.shih@mediatek.com> + */ + +#include <dm.h> +#include <log.h> +#include <asm/arch-mediatek/reset.h> +#include <asm/io.h> +#include <dt-bindings/clock/mediatek,mt7987-clk.h> +#include <linux/bitops.h> + +#include "clk-mtk.h" + +#define MT7987_XTAL_RATE (40 * MHZ) +#define MT7987_CLK_PDN 0x250 +#define MT7987_CLK_PDN_EN_WRITE BIT(31) + +#define XTAL_FACTOR(_id, _name, _parent, _mult, _div) \ + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_XTAL) + +#define PLL_FACTOR(_id, _name, _parent, _mult, _div) \ + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) + +#define TOP_FACTOR(_id, _name, _parent, _mult, _div) \ + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN) + +#define INFRA_FACTOR(_id, _name, _parent, _mult, _div) \ + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_INFRASYS) + +/* FIXED PLLS */ +static const struct mtk_fixed_clk apmixedsys_mtk_plls[] = { + FIXED_CLK(CLK_APMIXED_MPLL, CLK_XTAL, 416000000), + FIXED_CLK(CLK_APMIXED_APLL2, CLK_XTAL, 196608000), + FIXED_CLK(CLK_APMIXED_NET1PLL, CLK_XTAL, 2500000000), + FIXED_CLK(CLK_APMIXED_NET2PLL, CLK_XTAL, 800000000), + FIXED_CLK(CLK_APMIXED_WEDMCUPLL, CLK_XTAL, 208000000), + FIXED_CLK(CLK_APMIXED_SGMPLL, CLK_XTAL, 325000000), + FIXED_CLK(CLK_APMIXED_ARM_LL, CLK_XTAL, 2000000000), + FIXED_CLK(CLK_APMIXED_MSDCPLL, CLK_XTAL, 384000000), +}; + +static const struct mtk_clk_tree mt7987_fixed_pll_clk_tree = { + .fdivs_offs = ARRAY_SIZE(apmixedsys_mtk_plls), + .fclks = apmixedsys_mtk_plls, + .flags = CLK_APMIXED, + .xtal_rate = 40 * MHZ, +}; + +static const struct udevice_id mt7987_fixed_pll_compat[] = { + { .compatible = "mediatek,mt7987-fixed-plls" }, + { .compatible = "mediatek,mt7987-apmixedsys" }, + {} +}; + +static int mt7987_fixed_pll_probe(struct udevice *dev) +{ + return mtk_common_clk_init(dev, &mt7987_fixed_pll_clk_tree); +} + +U_BOOT_DRIVER(mtk_clk_apmixedsys) = { + .name = "mt7987-clock-fixed-pll", + .id = UCLASS_CLK, + .of_match = mt7987_fixed_pll_compat, + .probe = mt7987_fixed_pll_probe, + .priv_auto = sizeof(struct mtk_clk_priv), + .ops = &mtk_clk_topckgen_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +/* TOPCKGEN FIXED DIV */ +static const struct mtk_fixed_factor topckgen_mtk_fixed_factors[] = { + PLL_FACTOR(CLK_TOP_CB_M_D2, "cb_m_d2", CLK_APMIXED_MPLL, 1, 2), + PLL_FACTOR(CLK_TOP_CB_M_D3, "cb_m_d3", CLK_APMIXED_MPLL, 1, 3), + PLL_FACTOR(CLK_TOP_M_D3_D2, "m_d3_d2", CLK_APMIXED_MPLL, 1, 6), + PLL_FACTOR(CLK_TOP_CB_M_D4, "cb_m_d4", CLK_APMIXED_MPLL, 1, 4), + PLL_FACTOR(CLK_TOP_CB_M_D8, "cb_m_d8", CLK_APMIXED_MPLL, 1, 8), + PLL_FACTOR(CLK_TOP_M_D8_D2, "m_d8_d2", CLK_APMIXED_MPLL, 1, 16), + PLL_FACTOR(CLK_TOP_CB_APLL2_D4, "cb_apll2_d4", CLK_APMIXED_APLL2, 1, 4), + PLL_FACTOR(CLK_TOP_CB_NET1_D3, "cb_net1_d3", CLK_APMIXED_NET1PLL, 1, 3), + PLL_FACTOR(CLK_TOP_CB_NET1_D4, "cb_net1_d4", CLK_APMIXED_NET1PLL, 1, 4), + PLL_FACTOR(CLK_TOP_CB_NET1_D5, "cb_net1_d5", CLK_APMIXED_NET1PLL, 1, 5), + PLL_FACTOR(CLK_TOP_NET1_D5_D2, "net1_d5_d2", CLK_APMIXED_NET1PLL, 1, 10), + PLL_FACTOR(CLK_TOP_NET1_D5_D4, "net1_d5_d4", CLK_APMIXED_NET1PLL, 1, 20), + PLL_FACTOR(CLK_TOP_CB_NET1_D7, "cb_net1_d7", CLK_APMIXED_NET1PLL, 1, 7), + PLL_FACTOR(CLK_TOP_NET1_D7_D2, "net1_d7_d2", CLK_APMIXED_NET1PLL, 1, 14), + PLL_FACTOR(CLK_TOP_NET1_D7_D4, "net1_d7_d4", CLK_APMIXED_NET1PLL, 1, 28), + PLL_FACTOR(CLK_TOP_NET1_D8_D2, "net1_d8_d2", CLK_APMIXED_NET1PLL, 1, 16), + PLL_FACTOR(CLK_TOP_NET1_D8_D4, "net1_d8_d4", CLK_APMIXED_NET1PLL, 1, 32), + PLL_FACTOR(CLK_TOP_NET1_D8_D8, "net1_d8_d8", CLK_APMIXED_NET1PLL, 1, 64), + PLL_FACTOR(CLK_TOP_NET1_D8_D16, "net1_d8_d16", CLK_APMIXED_NET1PLL, 1, 128), + PLL_FACTOR(CLK_TOP_CB_NET2_D2, "cb_net2_d2", CLK_APMIXED_NET2PLL, 1, 2), + PLL_FACTOR(CLK_TOP_CB_NET2_D4, "cb_net2_d4", CLK_APMIXED_NET2PLL, 1, 4), + PLL_FACTOR(CLK_TOP_NET2_D4_D4, "net2_d4_d4", CLK_APMIXED_NET2PLL, 1, 16), + PLL_FACTOR(CLK_TOP_NET2_D4_D8, "net2_d4_d8", CLK_APMIXED_NET2PLL, 1, 32), + PLL_FACTOR(CLK_TOP_CB_NET2_D6, "cb_net2_d6", CLK_APMIXED_NET2PLL, 1, 6), + PLL_FACTOR(CLK_TOP_NET2_D7_D2, "net2_d7_d2", CLK_APMIXED_NET2PLL, 1, 14), + PLL_FACTOR(CLK_TOP_CB_NET2_D8, "cb_net2_d8", CLK_APMIXED_NET2PLL, 1, 8), + PLL_FACTOR(CLK_TOP_MSDC_D2, "msdc_d2", CLK_APMIXED_MSDCPLL, 1, 2), + XTAL_FACTOR(CLK_TOP_CB_CKSQ_40M, "cb_cksq_40m", CLK_XTAL, 1, 1), + TOP_FACTOR(CLK_TOP_CKSQ_40M_D2, "cksq_40m_d2", CLK_TOP_CB_CKSQ_40M, 1, 2), + TOP_FACTOR(CLK_TOP_CB_RTC_32K, "cb_rtc_32k", CLK_TOP_CB_CKSQ_40M, 1, 1250), + TOP_FACTOR(CLK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", CLK_TOP_CB_CKSQ_40M, 1, 1221), +}; + +/* TOPCKGEN MUX PARENTS */ +#define APMIXED_PARENT(_id) PARENT(_id, CLK_PARENT_APMIXED) +#define TOP_PARENT(_id) PARENT(_id, CLK_PARENT_TOPCKGEN) + +/* CLK_TOP_NETSYS_SEL (netsys_sel) in topckgen */ +static const struct mtk_parent netsys_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_NET2_D2) +}; + +/* CLK_TOP_NETSYS_500M_SEL (netsys_500m_sel) in topckgen */ +static const struct mtk_parent netsys_500m_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_NET1_D5), + TOP_PARENT(CLK_TOP_NET1_D5_D2) +}; + +/* CLK_TOP_NETSYS_2X_SEL (netsys_2x_sel) in topckgen */ +static const struct mtk_parent netsys_2x_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + APMIXED_PARENT(CLK_APMIXED_NET2PLL) +}; + +/* CLK_TOP_ETH_GMII_SEL (eth_gmii_sel) in topckgen */ +static const struct mtk_parent eth_gmii_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_NET1_D5_D4) +}; + +/* CLK_TOP_EIP_SEL (eip_sel) in topckgen */ +static const struct mtk_parent eip_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_NET1_D3), + APMIXED_PARENT(CLK_APMIXED_NET2PLL), + TOP_PARENT(CLK_TOP_CB_NET1_D4), + TOP_PARENT(CLK_TOP_CB_NET1_D5) +}; + +/* CLK_TOP_AXI_INFRA_SEL (axi_infra_sel) in topckgen */ +static const struct mtk_parent axi_infra_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_NET1_D8_D2) +}; + +/* CLK_TOP_UART_SEL (uart_sel) in topckgen */ +static const struct mtk_parent uart_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_M_D8), + TOP_PARENT(CLK_TOP_M_D8_D2) +}; + +/* CLK_TOP_EMMC_250M_SEL (emmc_250m_sel) in topckgen */ +static const struct mtk_parent emmc_250m_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_NET1_D5_D2), + TOP_PARENT(CLK_TOP_NET1_D7_D2) +}; + +/* CLK_TOP_EMMC_400M_SEL (emmc_400m_sel) in topckgen */ +static const struct mtk_parent emmc_400m_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + APMIXED_PARENT(CLK_APMIXED_MSDCPLL), + TOP_PARENT(CLK_TOP_CB_NET1_D7), + TOP_PARENT(CLK_TOP_CB_M_D2), + TOP_PARENT(CLK_TOP_NET1_D7_D2), + TOP_PARENT(CLK_TOP_CB_NET2_D6) +}; + +/* CLK_TOP_SPI_SEL (spi_sel) in topckgen */ +static const struct mtk_parent spi_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_M_D2), + TOP_PARENT(CLK_TOP_NET1_D7_D2), + TOP_PARENT(CLK_TOP_NET1_D8_D2), + TOP_PARENT(CLK_TOP_CB_NET2_D6), + TOP_PARENT(CLK_TOP_NET1_D5_D4), + TOP_PARENT(CLK_TOP_CB_M_D4), + TOP_PARENT(CLK_TOP_NET1_D8_D4) +}; + +/* CLK_TOP_NFI_SEL (nfi_sel) in topckgen */ +static const struct mtk_parent nfi_parents[] = { + TOP_PARENT(CLK_TOP_CKSQ_40M_D2), + TOP_PARENT(CLK_TOP_NET1_D8_D2), + TOP_PARENT(CLK_TOP_CB_M_D3), + TOP_PARENT(CLK_TOP_NET1_D5_D4), + TOP_PARENT(CLK_TOP_CB_M_D4), + TOP_PARENT(CLK_TOP_NET1_D7_D4), + TOP_PARENT(CLK_TOP_NET1_D8_D4), + TOP_PARENT(CLK_TOP_M_D3_D2), + TOP_PARENT(CLK_TOP_NET2_D7_D2), + TOP_PARENT(CLK_TOP_CB_M_D8) +}; + +/* CLK_TOP_PWM_SEL (pwm_sel) in topckgen */ +static const struct mtk_parent pwm_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_NET1_D8_D2), + TOP_PARENT(CLK_TOP_NET1_D5_D4), + TOP_PARENT(CLK_TOP_CB_M_D4), + TOP_PARENT(CLK_TOP_M_D8_D2), + TOP_PARENT(CLK_TOP_CB_RTC_32K) +}; + +/* CLK_TOP_I2C_SEL (i2c_sel) in topckgen */ +static const struct mtk_parent i2c_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_NET1_D5_D4), + TOP_PARENT(CLK_TOP_CB_M_D4), + TOP_PARENT(CLK_TOP_NET1_D8_D4) +}; + +/* CLK_TOP_PCIE_MBIST_250M_SEL (pcie_mbist_250m_sel) in topckgen */ +static const struct mtk_parent pcie_mbist_250m_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_NET1_D5_D2) +}; + +/* CLK_TOP_PEXTP_TL_SEL (pextp_tl_ck_sel) in topckgen */ +static const struct mtk_parent pextp_tl_ck_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_NET2_D6), + TOP_PARENT(CLK_TOP_NET1_D7_D4), + TOP_PARENT(CLK_TOP_M_D8_D2), + TOP_PARENT(CLK_TOP_CB_RTC_32K) +}; + +/* CLK_TOP_AUD_SEL (aud_sel) in topckgen */ +static const struct mtk_parent aud_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + APMIXED_PARENT(CLK_APMIXED_APLL2) +}; + +/* CLK_TOP_A1SYS_SEL (a1sys_sel) in topckgen */ +static const struct mtk_parent a1sys_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_APLL2_D4) +}; + +/* CLK_TOP_AUD_L_SEL (aud_l_sel) in topckgen */ +static const struct mtk_parent aud_l_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + APMIXED_PARENT(CLK_APMIXED_APLL2), + TOP_PARENT(CLK_TOP_M_D8_D2) +}; + +/* CLK_TOP_USB_PHY_SEL (usb_phy_sel) in topckgen */ +static const struct mtk_parent usb_phy_parents[] = { + TOP_PARENT(CLK_TOP_CKSQ_40M_D2), + TOP_PARENT(CLK_TOP_M_D8_D2) +}; + +/* CLK_TOP_SGM_0_SEL (sgm_0_sel) in topckgen */ +static const struct mtk_parent sgm_0_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + APMIXED_PARENT(CLK_APMIXED_SGMPLL) +}; + +/* CLK_TOP_SGM_SBUS_0_SEL (sgm_sbus_0_sel) in topckgen */ +static const struct mtk_parent sgm_sbus_0_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_NET1_D8_D4) +}; + +/* CLK_TOP_SYSAPB_SEL (sysapb_sel) in topckgen */ +static const struct mtk_parent sysapb_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_M_D3_D2) +}; + +/* CLK_TOP_ETH_REFCK_50M_SEL (eth_refck_50m_sel) in topckgen */ +static const struct mtk_parent eth_refck_50m_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_NET2_D4_D4) +}; + +/* CLK_TOP_ETH_SYS_200M_SEL (eth_sys_200m_sel) in topckgen */ +static const struct mtk_parent eth_sys_200m_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_NET2_D4) +}; + +/* CLK_TOP_ETH_XGMII_SEL (eth_xgmii_sel) in topckgen */ +static const struct mtk_parent eth_xgmii_parents[] = { + TOP_PARENT(CLK_TOP_CKSQ_40M_D2), + TOP_PARENT(CLK_TOP_NET1_D8_D8), + TOP_PARENT(CLK_TOP_NET1_D8_D16) +}; + +/* CLK_TOP_DRAMC_MD32_SEL (dramc_md32_sel) in topckgen */ +static const struct mtk_parent dramc_md32_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_M_D2), + APMIXED_PARENT(CLK_APMIXED_WEDMCUPLL) +}; + +/* CLK_TOP_DA_XTP_GLB_P0_SEL (da_xtp_glb_p0_sel) in topckgen */ +static const struct mtk_parent da_xtp_glb_p0_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_NET2_D8) +}; + +/* CLK_TOP_DA_CKM_XTAL_SEL (da_ckm_xtal_sel) in topckgen */ +static const struct mtk_parent da_ckm_xtal_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_M_D8_D2) +}; + +/* CLK_TOP_ETH_MII_SEL (eth_mii_sel) in topckgen */ +static const struct mtk_parent eth_mii_parents[] = { + TOP_PARENT(CLK_TOP_CKSQ_40M_D2), + TOP_PARENT(CLK_TOP_NET2_D4_D8) +}; + +/* CLK_TOP_EMMC_200M_SEL (emmc_200m_sel) in topckgen */ +static const struct mtk_parent emmc_200m_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_MSDC_D2), + TOP_PARENT(CLK_TOP_NET1_D7_D2), + TOP_PARENT(CLK_TOP_CB_NET2_D6), + TOP_PARENT(CLK_TOP_NET1_D7_D4) +}; + +#define TOP_MUX(_id, _name, _parents, _mux_ofs, _mux_set_ofs, _mux_clr_ofs, \ + _shift, _width, _gate, _upd_ofs, _upd) \ + { \ + .id = (_id), .mux_reg = (_mux_ofs), \ + .mux_set_reg = (_mux_set_ofs), .mux_clr_reg = (_mux_clr_ofs), \ + .upd_reg = (_upd_ofs), .upd_shift = (_upd), \ + .mux_shift = (_shift), .mux_mask = BIT(_width) - 1, \ + .gate_reg = (_mux_ofs), .gate_shift = (_gate), \ + .parent_flags = (_parents), \ + .num_parents = ARRAY_SIZE(_parents), \ + .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_MIXED, \ + } + +/* TOPCKGEN MUX_GATE */ +static const struct mtk_composite topckgen_mtk_muxes[] = { + TOP_MUX(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, + 0x000, 0x004, 0x008, 0, 1, 7, 0x1C0, 0), + TOP_MUX(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", + netsys_500m_parents, 0x000, 0x004, 0x008, 8, 2, 15, 0x1C0, 1), + TOP_MUX(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, + 0x000, 0x004, 0x008, 16, 1, 23, 0x1C0, 2), + TOP_MUX(CLK_TOP_ETH_GMII_SEL, "eth_gmii_sel", eth_gmii_parents, + 0x000, 0x004, 0x008, 24, 1, 31, 0x1C0, 3), + TOP_MUX(CLK_TOP_EIP_SEL, "eip_sel", eip_parents, + 0x010, 0x014, 0x018, 0, 3, 7, 0x1C0, 4), + TOP_MUX(CLK_TOP_AXI_INFRA_SEL, "axi_infra_sel", axi_infra_parents, + 0x010, 0x014, 0x018, 8, 1, 15, 0x1C0, 5), + TOP_MUX(CLK_TOP_UART_SEL, "uart_sel", uart_parents, + 0x010, 0x014, 0x018, 16, 2, 23, 0x1C0, 6), + TOP_MUX(CLK_TOP_EMMC_250M_SEL, "emmc_250m_sel", emmc_250m_parents, + 0x010, 0x014, 0x018, 24, 2, 31, 0x1C0, 7), + TOP_MUX(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel", emmc_400m_parents, + 0x020, 0x024, 0x028, 0, 3, 7, 0x1C0, 8), + TOP_MUX(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, + 0x020, 0x024, 0x028, 8, 3, 15, 0x1C0, 9), + TOP_MUX(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, + 0x020, 0x024, 0x028, 16, 3, 23, 0x1C0, 10), + TOP_MUX(CLK_TOP_NFI_SEL, "nfi_sel", nfi_parents, + 0x020, 0x024, 0x028, 24, 4, 31, 0x1C0, 11), + TOP_MUX(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, + 0x030, 0x034, 0x038, 0, 3, 7, 0x1C0, 12), + TOP_MUX(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, + 0x030, 0x034, 0x038, 8, 2, 15, 0x1C0, 13), + TOP_MUX(CLK_TOP_PCIE_MBIST_250M_SEL, "pcie_mbist_250m_sel", + pcie_mbist_250m_parents, 0x030, 0x034, 0x038, 16, 1, 23, 0x1C0, 14), + TOP_MUX(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", pextp_tl_ck_parents, + 0x030, 0x034, 0x038, 24, 3, 31, 0x1C0, 15), + TOP_MUX(CLK_TOP_PEXTP_TL_P1_SEL, "pextp_tl_ck_p1_sel", + pextp_tl_ck_parents, 0x040, 0x044, 0x048, 0, 3, 7, 0x1C0, 16), + TOP_MUX(CLK_TOP_USB_SYS_P1_SEL, "usb_sys_p1_sel", eth_gmii_parents, + 0x040, 0x044, 0x048, 8, 1, 15, 0x1C0, 17), + TOP_MUX(CLK_TOP_USB_XHCI_P1_SEL, "usb_xhci_p1_sel", eth_gmii_parents, + 0x040, 0x044, 0x048, 16, 1, 23, 0x1C0, 18), + TOP_MUX(CLK_TOP_AUD_SEL, "aud_sel", aud_parents, + 0x040, 0x044, 0x048, 24, 1, 31, 0x1C0, 19), + TOP_MUX(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, + 0x050, 0x054, 0x058, 0, 1, 7, 0x1C0, 20), + TOP_MUX(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, + 0x050, 0x054, 0x058, 8, 2, 15, 0x1C0, 21), + TOP_MUX(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", a1sys_parents, + 0x050, 0x054, 0x058, 16, 1, 23, 0x1C0, 22), + TOP_MUX(CLK_TOP_USB_PHY_SEL, "usb_phy_sel", usb_phy_parents, + 0x050, 0x054, 0x058, 24, 1, 31, 0x1C0, 23), + TOP_MUX(CLK_TOP_SGM_0_SEL, "sgm_0_sel", sgm_0_parents, + 0x060, 0x064, 0x068, 0, 1, 7, 0x1C0, 24), + TOP_MUX(CLK_TOP_SGM_SBUS_0_SEL, "sgm_sbus_0_sel", sgm_sbus_0_parents, + 0x060, 0x064, 0x068, 8, 1, 15, 0x1C0, 25), + TOP_MUX(CLK_TOP_SGM_1_SEL, "sgm_1_sel", sgm_0_parents, + 0x060, 0x064, 0x068, 16, 1, 23, 0x1C0, 26), + TOP_MUX(CLK_TOP_SGM_SBUS_1_SEL, "sgm_sbus_1_sel", sgm_sbus_0_parents, + 0x060, 0x064, 0x068, 24, 1, 31, 0x1C0, 27), + TOP_MUX(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", axi_infra_parents, + 0x070, 0x074, 0x078, 0, 1, 7, 0x1C0, 28), + TOP_MUX(CLK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, + 0x070, 0x074, 0x078, 8, 1, 15, 0x1C0, 29), + TOP_MUX(CLK_TOP_ETH_REFCK_50M_SEL, "eth_refck_50m_sel", + eth_refck_50m_parents, 0x070, 0x074, 0x078, 16, 1, 23, 0x1C0, 30), + TOP_MUX(CLK_TOP_ETH_SYS_200M_SEL, "eth_sys_200m_sel", + eth_sys_200m_parents, 0x070, 0x074, 0x078, 24, 1, 31, 0x1C4, 0), + TOP_MUX(CLK_TOP_ETH_SYS_SEL, "eth_sys_sel", pcie_mbist_250m_parents, + 0x080, 0x084, 0x088, 0, 1, 7, 0x1C4, 1), + TOP_MUX(CLK_TOP_ETH_XGMII_SEL, "eth_xgmii_sel", eth_xgmii_parents, + 0x080, 0x084, 0x088, 8, 2, 15, 0x1C4, 2), + TOP_MUX(CLK_TOP_DRAMC_SEL, "dramc_sel", usb_phy_parents, + 0x080, 0x084, 0x088, 16, 1, 23, 0x1C4, 3), + TOP_MUX(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", dramc_md32_parents, + 0x080, 0x084, 0x088, 24, 2, 31, 0x1C4, 4), + TOP_MUX(CLK_TOP_INFRA_F26M_SEL, "csw_infra_f26m_sel", + usb_phy_parents, 0x090, 0x094, 0x098, 0, 1, 7, 0x1C4, 5), + TOP_MUX(CLK_TOP_PEXTP_P0_SEL, "pextp_p0_sel", usb_phy_parents, + 0x090, 0x094, 0x098, 8, 1, 15, 0x1C4, 6), + TOP_MUX(CLK_TOP_PEXTP_P1_SEL, "pextp_p1_sel", usb_phy_parents, + 0x090, 0x094, 0x098, 16, 1, 23, 0x1C4, 7), + TOP_MUX(CLK_TOP_DA_XTP_GLB_P0_SEL, "da_xtp_glb_p0_sel", + da_xtp_glb_p0_parents, 0x090, 0x094, 0x098, 24, 1, 31, 0x1C4, 8), + TOP_MUX(CLK_TOP_DA_XTP_GLB_P1_SEL, "da_xtp_glb_p1_sel", + da_xtp_glb_p0_parents, 0x0A0, 0x0A4, 0x0A8, 0, 1, 7, 0x1C4, 9), + TOP_MUX(CLK_TOP_CKM_SEL, "ckm_sel", usb_phy_parents, + 0x0A0, 0x0A4, 0x0A8, 8, 1, 15, 0x1C4, 10), + TOP_MUX(CLK_TOP_DA_CKM_XTAL_SEL, "da_ckm_xtal_sel", + da_ckm_xtal_parents, 0x0A0, 0x0A4, 0x0A8, 16, 1, 23, 0x1C4, 11), + TOP_MUX(CLK_TOP_PEXTP_SEL, "pextp_sel", usb_phy_parents, + 0x0A0, 0x0A4, 0x0A8, 24, 1, 31, 0x1C4, 12), + TOP_MUX(CLK_TOP_ETH_MII_SEL, "eth_mii_sel", eth_mii_parents, + 0x0B0, 0x0B4, 0x0B8, 0, 1, 7, 0x1C4, 13), + TOP_MUX(CLK_TOP_EMMC_200M_SEL, "emmc_200m_sel", emmc_200m_parents, + 0x0B0, 0x0B4, 0x0B8, 8, 3, 15, 0x1C4, 14), +}; + +static const struct mtk_clk_tree mt7987_topckgen_clk_tree = { + .muxes_offs = CLK_TOP_NETSYS_SEL, + .fdivs = topckgen_mtk_fixed_factors, + .muxes = topckgen_mtk_muxes, + .flags = CLK_BYPASS_XTAL | CLK_TOPCKGEN, + .xtal_rate = MT7987_XTAL_RATE, +}; + +static const struct udevice_id mt7987_topckgen_compat[] = { + { .compatible = "mediatek,mt7987-topckgen" }, + {} +}; + +static int mt7987_topckgen_probe(struct udevice *dev) +{ + struct mtk_clk_priv *priv = dev_get_priv(dev); + + priv->base = dev_read_addr_ptr(dev); + if (!priv->base) + return -ENOENT; + + writel(MT7987_CLK_PDN_EN_WRITE, priv->base + MT7987_CLK_PDN); + return mtk_common_clk_init(dev, &mt7987_topckgen_clk_tree); +} + +U_BOOT_DRIVER(mtk_clk_topckgen) = { + .name = "mt7987-clock-topckgen", + .id = UCLASS_CLK, + .of_match = mt7987_topckgen_compat, + .probe = mt7987_topckgen_probe, + .priv_auto = sizeof(struct mtk_clk_priv), + .ops = &mtk_clk_topckgen_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +/* INFRASYS MUX PARENTS */ + +/* CLK_INFRA_MUX_UART0_SEL (infra_mux_uart0_sel) in infracfg */ +static const int infra_mux_uart0_parents[] = { + CLK_TOP_INFRA_F26M_SEL, + CLK_TOP_UART_SEL +}; + +/* CLK_INFRA_MUX_UART1_SEL (infra_mux_uart1_sel) in infracfg */ +static const int infra_mux_uart1_parents[] = { + CLK_TOP_INFRA_F26M_SEL, + CLK_TOP_UART_SEL +}; + +/* CLK_INFRA_MUX_UART2_SEL (infra_mux_uart2_sel) in infracfg */ +static const int infra_mux_uart2_parents[] = { + CLK_TOP_INFRA_F26M_SEL, + CLK_TOP_UART_SEL +}; + +/* CLK_INFRA_MUX_SPI0_SEL (infra_mux_spi0_sel) in infracfg */ +static const int infra_mux_spi0_parents[] = { + CLK_TOP_I2C_SEL, + CLK_TOP_SPI_SEL +}; + +/* CLK_INFRA_MUX_SPI1_SEL (infra_mux_spi1_sel) in infracfg */ +static const int infra_mux_spi1_parents[] = { + CLK_TOP_I2C_SEL, + CLK_TOP_SPIM_MST_SEL +}; + +/* CLK_INFRA_MUX_SPI2_BCK_SEL (infra_mux_spi2_bck_sel) in infracfg */ +static const int infra_mux_spi2_bck_parents[] = { + CLK_TOP_I2C_SEL, + CLK_TOP_SPI_SEL +}; + +/* CLK_INFRA_PWM_BCK_SEL (infra_pwm_bck_sel) in infracfg */ +static const int infra_pwm_bck_parents[] = { + CLK_TOP_CB_RTC_32P7K, + CLK_TOP_INFRA_F26M_SEL, + CLK_TOP_SYSAXI_SEL, + CLK_TOP_PWM_SEL +}; + +/* CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL (infra_pcie_gfmux_tl_ck_o_p0_sel) in infracfg */ +static const int infra_pcie_gfmux_tl_ck_o_p0_parents[] = { + CLK_TOP_CB_RTC_32P7K, + CLK_TOP_INFRA_F26M_SEL, + CLK_TOP_INFRA_F26M_SEL, + CLK_TOP_PEXTP_TL_SEL +}; + +/* CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL (infra_pcie_gfmux_tl_ck_o_p1_sel) in infracfg */ +static const int infra_pcie_gfmux_tl_ck_o_p1_parents[] = { + CLK_TOP_CB_RTC_32P7K, + CLK_TOP_INFRA_F26M_SEL, + CLK_TOP_INFRA_F26M_SEL, + CLK_TOP_PEXTP_TL_P1_SEL +}; + +#define INFRA_MUX(_id, _name, _parents, _reg, _shift, _width) \ + { \ + .id = (_id), .mux_reg = (_reg) + 0x8, \ + .mux_clr_reg = (_reg) + 0x4, .mux_set_reg = (_reg) + 0x0, \ + .mux_shift = (_shift), .mux_mask = BIT(_width) - 1, \ + .gate_shift = -1, .upd_shift = -1, \ + .parent = (_parents), .num_parents = ARRAY_SIZE(_parents), \ + .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_TOPCKGEN, \ + } + +/* INFRA MUX */ +static const struct mtk_composite infracfg_mtk_mux[] = { + INFRA_MUX(CLK_INFRA_MUX_UART0_SEL, "infra_mux_uart0_sel", + infra_mux_uart0_parents, 0x0010, 0, 1), + INFRA_MUX(CLK_INFRA_MUX_UART1_SEL, "infra_mux_uart1_sel", + infra_mux_uart1_parents, 0x0010, 1, 1), + INFRA_MUX(CLK_INFRA_MUX_UART2_SEL, "infra_mux_uart2_sel", + infra_mux_uart2_parents, 0x0010, 2, 1), + INFRA_MUX(CLK_INFRA_MUX_SPI0_SEL, "infra_mux_spi0_sel", + infra_mux_spi0_parents, 0x0010, 4, 1), + INFRA_MUX(CLK_INFRA_MUX_SPI1_SEL, "infra_mux_spi1_sel", + infra_mux_spi1_parents, 0x0010, 5, 1), + INFRA_MUX(CLK_INFRA_MUX_SPI2_BCK_SEL, "infra_mux_spi2_bck_sel", + infra_mux_spi2_bck_parents, 0x0010, 6, 1), + INFRA_MUX(CLK_INFRA_PWM_BCK_SEL, "infra_pwm_bck_sel", + infra_pwm_bck_parents, 0x0010, 14, 2), + INFRA_MUX(CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL, "infra_pcie_gfmux_tl_ck_o_p0_sel", + infra_pcie_gfmux_tl_ck_o_p0_parents, 0x0020, 0, 2), + INFRA_MUX(CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL, "infra_pcie_gfmux_tl_ck_o_p1_sel", + infra_pcie_gfmux_tl_ck_o_p1_parents, 0x0020, 2, 2), +}; + +static const struct mtk_gate_regs infra_0_cg_regs = { + .set_ofs = 0x10, + .clr_ofs = 0x14, + .sta_ofs = 0x18, +}; + +static const struct mtk_gate_regs infra_1_cg_regs = { + .set_ofs = 0x40, + .clr_ofs = 0x44, + .sta_ofs = 0x48, +}; + +static const struct mtk_gate_regs infra_2_cg_regs = { + .set_ofs = 0x50, + .clr_ofs = 0x54, + .sta_ofs = 0x58, +}; + +static const struct mtk_gate_regs infra_3_cg_regs = { + .set_ofs = 0x60, + .clr_ofs = 0x64, + .sta_ofs = 0x68, +}; + +#define GATE_INFRA0(_id, _name, _parent, _shift, _flags) \ + { \ + .id = (_id), .parent = (_parent), .regs = &infra_0_cg_regs, \ + .shift = (_shift), \ + .flags = (_flags), \ + } +#define GATE_INFRA0_INFRA(_id, _name, _parent, _shift) \ + GATE_INFRA0(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS) +#define GATE_INFRA0_TOP(_id, _name, _parent, _shift) \ + GATE_INFRA0(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) + +#define GATE_INFRA1(_id, _name, _parent, _shift, _flags) \ + { \ + .id = (_id), .parent = (_parent), .regs = &infra_1_cg_regs, \ + .shift = (_shift), \ + .flags = (_flags), \ + } +#define GATE_INFRA1_INFRA(_id, _name, _parent, _shift) \ + GATE_INFRA1(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS) +#define GATE_INFRA1_TOP(_id, _name, _parent, _shift) \ + GATE_INFRA1(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) + +#define GATE_INFRA2(_id, _name, _parent, _shift, _flags) \ + { \ + .id = (_id), .parent = (_parent), .regs = &infra_2_cg_regs, \ + .shift = (_shift), \ + .flags = (_flags), \ + } +#define GATE_INFRA2_INFRA(_id, _name, _parent, _shift) \ + GATE_INFRA2(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS) +#define GATE_INFRA2_TOP(_id, _name, _parent, _shift) \ + GATE_INFRA2(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) + +#define GATE_INFRA3(_id, _name, _parent, _shift, _flags) \ + { \ + .id = (_id), .parent = (_parent), .regs = &infra_3_cg_regs, \ + .shift = (_shift), \ + .flags = (_flags), \ + } +#define GATE_INFRA3_INFRA(_id, _name, _parent, _shift) \ + GATE_INFRA3(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS) +#define GATE_INFRA3_TOP(_id, _name, _parent, _shift) \ + GATE_INFRA3(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) +#define GATE_INFRA3_XTAL(_id, _name, _parent, _shift) \ + GATE_INFRA3(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_XTAL) + +/* INFRA GATE */ +static const struct mtk_gate infracfg_mtk_gates[] = { + GATE_INFRA1_TOP(CLK_INFRA_66M_GPT_BCK, + "infra_hf_66m_gpt_bck", CLK_TOP_SYSAXI_SEL, 0), + GATE_INFRA1_TOP(CLK_INFRA_66M_PWM_HCK, + "infra_hf_66m_pwm_hck", CLK_TOP_SYSAXI_SEL, 1), + GATE_INFRA1_INFRA(CLK_INFRA_66M_PWM_BCK, + "infra_hf_66m_pwm_bck", CLK_INFRA_PWM_BCK_SEL, 2), + GATE_INFRA1_TOP(CLK_INFRA_133M_CQDMA_BCK, + "infra_hf_133m_cqdma_bck", CLK_TOP_SYSAXI_SEL, 12), + GATE_INFRA1_TOP(CLK_INFRA_66M_AUD_SLV_BCK, + "infra_66m_aud_slv_bck", CLK_TOP_SYSAXI_SEL, 13), + GATE_INFRA1_TOP(CLK_INFRA_AUD_26M, "infra_f_faud_26m", + CLK_TOP_INFRA_F26M_SEL, 14), + GATE_INFRA1_TOP(CLK_INFRA_AUD_L, "infra_f_faud_l", CLK_TOP_AUD_L_SEL, 15), + GATE_INFRA1_TOP(CLK_INFRA_AUD_AUD, "infra_f_aud_aud", CLK_TOP_A1SYS_SEL, 16), + GATE_INFRA1_TOP(CLK_INFRA_AUD_EG2, "infra_f_faud_eg2", + CLK_TOP_A_TUNER_SEL, 18), + GATE_INFRA1_TOP(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m", + CLK_TOP_INFRA_F26M_SEL, 19), + GATE_INFRA1_TOP(CLK_INFRA_133M_DBG_ACKM, + "infra_hf_133m_dbg_ackm", CLK_TOP_SYSAXI_SEL, 20), + GATE_INFRA1_TOP(CLK_INFRA_66M_AP_DMA_BCK, + "infra_66m_ap_dma_bck", CLK_TOP_SYSAXI_SEL, 21), + GATE_INFRA1_TOP(CLK_INFRA_MSDC200_SRC, "infra_f_fmsdc200_src", + CLK_TOP_EMMC_200M_SEL, 28), + GATE_INFRA1_TOP(CLK_INFRA_66M_SEJ_BCK, + "infra_hf_66m_sej_bck", CLK_TOP_SYSAXI_SEL, 29), + GATE_INFRA1_TOP(CLK_INFRA_PRE_CK_SEJ_F13M, + "infra_pre_ck_sej_f13m", CLK_TOP_INFRA_F26M_SEL, 30), + GATE_INFRA1_TOP(CLK_INFRA_66M_TRNG, "infra_hf_66m_trng", + CLK_TOP_SYSAXI_SEL, 31), + GATE_INFRA2_TOP(CLK_INFRA_26M_THERM_SYSTEM, + "infra_hf_26m_therm_system", CLK_TOP_INFRA_F26M_SEL, 0), + GATE_INFRA2_TOP(CLK_INFRA_I2C_BCK, "infra_i2c_bck", CLK_TOP_I2C_SEL, 1), + GATE_INFRA2_TOP(CLK_INFRA_66M_UART0_PCK, + "infra_hf_66m_uart0_pck", CLK_TOP_SYSAXI_SEL, 3), + GATE_INFRA2_TOP(CLK_INFRA_66M_UART1_PCK, + "infra_hf_66m_uart1_pck", CLK_TOP_SYSAXI_SEL, 4), + GATE_INFRA2_TOP(CLK_INFRA_66M_UART2_PCK, + "infra_hf_66m_uart2_pck", CLK_TOP_SYSAXI_SEL, 5), + GATE_INFRA2_INFRA(CLK_INFRA_52M_UART0_CK, + "infra_f_52m_uart0", CLK_INFRA_MUX_UART0_SEL, 3), + GATE_INFRA2_INFRA(CLK_INFRA_52M_UART1_CK, + "infra_f_52m_uart1", CLK_INFRA_MUX_UART1_SEL, 4), + GATE_INFRA2_INFRA(CLK_INFRA_52M_UART2_CK, + "infra_f_52m_uart2", CLK_INFRA_MUX_UART2_SEL, 5), + GATE_INFRA2_TOP(CLK_INFRA_NFI, "infra_f_fnfi", CLK_TOP_NFI_SEL, 9), + GATE_INFRA2_TOP(CLK_INFRA_66M_NFI_HCK, + "infra_hf_66m_nfi_hck", CLK_TOP_SYSAXI_SEL, 11), + GATE_INFRA2_INFRA(CLK_INFRA_104M_SPI0, "infra_hf_104m_spi0", + CLK_INFRA_MUX_SPI0_SEL, 12), + GATE_INFRA2_INFRA(CLK_INFRA_104M_SPI1, "infra_hf_104m_spi1", + CLK_INFRA_MUX_SPI1_SEL, 13), + GATE_INFRA2_INFRA(CLK_INFRA_104M_SPI2_BCK, + "infra_hf_104m_spi2_bck", CLK_INFRA_MUX_SPI2_BCK_SEL, 14), + GATE_INFRA2_TOP(CLK_INFRA_66M_SPI0_HCK, + "infra_hf_66m_spi0_hck", CLK_TOP_SYSAXI_SEL, 15), + GATE_INFRA2_TOP(CLK_INFRA_66M_SPI1_HCK, + "infra_hf_66m_spi1_hck", CLK_TOP_SYSAXI_SEL, 16), + GATE_INFRA2_TOP(CLK_INFRA_66M_SPI2_HCK, + "infra_hf_66m_spi2_hck", CLK_TOP_SYSAXI_SEL, 17), + GATE_INFRA2_TOP(CLK_INFRA_66M_FLASHIF_AXI, + "infra_hf_66m_flashif_axi", CLK_TOP_SYSAXI_SEL, 18), + GATE_INFRA2_TOP(CLK_INFRA_RTC, "infra_f_frtc", CLK_TOP_CB_RTC_32K, 19), + GATE_INFRA2_TOP(CLK_INFRA_26M_ADC_BCK, "infra_f_26m_adc_bck", + CLK_TOP_INFRA_F26M_SEL, 20), + GATE_INFRA2_INFRA(CLK_INFRA_RC_ADC, "infra_f_frc_adc", + CLK_INFRA_26M_ADC_BCK, 21), + GATE_INFRA2_TOP(CLK_INFRA_MSDC400, "infra_f_fmsdc400", + CLK_TOP_EMMC_400M_SEL, 22), + GATE_INFRA2_TOP(CLK_INFRA_MSDC2_HCK, "infra_f_fmsdc2_hck", + CLK_TOP_EMMC_250M_SEL, 23), + GATE_INFRA2_TOP(CLK_INFRA_133M_MSDC_0_HCK, + "infra_hf_133m_msdc_0_hck", CLK_TOP_SYSAXI_SEL, 24), + GATE_INFRA2_TOP(CLK_INFRA_66M_MSDC_0_HCK, + "infra_66m_msdc_0_hck", CLK_TOP_SYSAXI_SEL, 25), + GATE_INFRA2_TOP(CLK_INFRA_133M_CPUM_BCK, + "infra_hf_133m_cpum_bck", CLK_TOP_SYSAXI_SEL, 26), + GATE_INFRA2_TOP(CLK_INFRA_BIST2FPC, "infra_hf_fbist2fpc", + CLK_TOP_NFI_SEL, 27), + GATE_INFRA2_TOP(CLK_INFRA_I2C_X16W_MCK_CK_P1, + "infra_hf_i2c_x16w_mck_ck_p1", CLK_TOP_SYSAXI_SEL, 29), + GATE_INFRA2_TOP(CLK_INFRA_I2C_X16W_PCK_CK_P1, + "infra_hf_i2c_x16w_pck_ck_p1", CLK_TOP_SYSAXI_SEL, 31), + GATE_INFRA3_TOP(CLK_INFRA_133M_USB_HCK, + "infra_133m_usb_hck", CLK_TOP_SYSAXI_SEL, 0), + GATE_INFRA3_TOP(CLK_INFRA_133M_USB_HCK_CK_P1, + "infra_133m_usb_hck_ck_p1", CLK_TOP_SYSAXI_SEL, 1), + GATE_INFRA3_TOP(CLK_INFRA_66M_USB_HCK, "infra_66m_usb_hck", + CLK_TOP_SYSAXI_SEL, 2), + GATE_INFRA3_TOP(CLK_INFRA_66M_USB_HCK_CK_P1, + "infra_66m_usb_hck_ck_p1", CLK_TOP_SYSAXI_SEL, 3), + GATE_INFRA3_TOP(CLK_INFRA_USB_SYS_CK_P1, + "infra_usb_sys_ck_p1", CLK_TOP_USB_SYS_P1_SEL, 5), + GATE_INFRA3_TOP(CLK_INFRA_USB_CK_P1, "infra_usb_ck_p1", + CLK_TOP_CB_CKSQ_40M, 7), + GATE_INFRA3_TOP(CLK_INFRA_USB_FRMCNT_CK_P1, + "infra_usb_frmcnt_ck_p1", CLK_TOP_CKSQ_40M_D2, 9), + GATE_INFRA3_XTAL(CLK_INFRA_USB_PIPE_CK_P1, + "infra_usb_pipe_ck_p1", CLK_XTAL, 11), + GATE_INFRA3_XTAL(CLK_INFRA_USB_UTMI_CK_P1, + "infra_usb_utmi_ck_p1", CLK_XTAL, 13), + GATE_INFRA3_TOP(CLK_INFRA_USB_XHCI_CK_P1, + "infra_usb_xhci_ck_p1", CLK_TOP_USB_XHCI_P1_SEL, 15), + GATE_INFRA3_INFRA(CLK_INFRA_PCIE_GFMUX_TL_P0, + "infra_pcie_gfmux_tl_ck_p0", CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL, 20), + GATE_INFRA3_INFRA(CLK_INFRA_PCIE_GFMUX_TL_P1, + "infra_pcie_gfmux_tl_ck_p1", CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL, 21), + GATE_INFRA3_XTAL(CLK_INFRA_PCIE_PIPE_P0, + "infra_pcie_pipe_ck_p0", CLK_XTAL, 24), + GATE_INFRA3_XTAL(CLK_INFRA_PCIE_PIPE_P1, + "infra_pcie_pipe_ck_p1", CLK_XTAL, 25), + GATE_INFRA3_TOP(CLK_INFRA_133M_PCIE_CK_P0, + "infra_133m_pcie_ck_p0", CLK_TOP_SYSAXI_SEL, 28), + GATE_INFRA3_TOP(CLK_INFRA_133M_PCIE_CK_P1, + "infra_133m_pcie_ck_p1", CLK_TOP_SYSAXI_SEL, 29), + GATE_INFRA0_TOP(CLK_INFRA_PCIE_PERI_26M_CK_P0, + "infra_pcie_peri_ck_26m_ck_p0", CLK_TOP_INFRA_F26M_SEL, 7), + GATE_INFRA0_TOP(CLK_INFRA_PCIE_PERI_26M_CK_P1, + "infra_pcie_peri_ck_26m_ck_p1", CLK_TOP_INFRA_F26M_SEL, 8), +}; + +static const struct mtk_clk_tree mt7987_infracfg_clk_tree = { + .muxes_offs = CLK_INFRA_MUX_UART0_SEL, + .gates_offs = CLK_INFRA_66M_GPT_BCK, + .muxes = infracfg_mtk_mux, + .gates = infracfg_mtk_gates, + .flags = CLK_BYPASS_XTAL, + .xtal_rate = MT7987_XTAL_RATE, +}; + +static const struct udevice_id mt7987_infracfg_compat[] = { + { .compatible = "mediatek,mt7987-infracfg_ao" }, + { .compatible = "mediatek,mt7987-infracfg" }, + {} +}; + +static int mt7987_infracfg_probe(struct udevice *dev) +{ + return mtk_common_clk_infrasys_init(dev, &mt7987_infracfg_clk_tree); +} + +U_BOOT_DRIVER(mtk_clk_infracfg) = { + .name = "mt7987-clock-infracfg", + .id = UCLASS_CLK, + .of_match = mt7987_infracfg_compat, + .probe = mt7987_infracfg_probe, + .priv_auto = sizeof(struct mtk_clk_priv), + .ops = &mtk_clk_infrasys_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +/* ethsys */ +static const struct mtk_gate_regs eth_cg_regs = { + .set_ofs = 0x30, + .clr_ofs = 0x30, + .sta_ofs = 0x30, +}; + +#define GATE_ETH_TOP(_id, _name, _parent, _shift) \ + { \ + .id = (_id), .parent = (_parent), .regs = ð_cg_regs, \ + .shift = (_shift), \ + .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \ + } + +static const struct mtk_gate eth_cgs[] = { + GATE_ETH_TOP(CLK_ETHDMA_FE_EN, "ethdma_fe_en", CLK_TOP_NETSYS_2X_SEL, 6), + GATE_ETH_TOP(CLK_ETHDMA_GP2_EN, "ethdma_gp2_en", CLK_TOP_NETSYS_500M_SEL, 7), + GATE_ETH_TOP(CLK_ETHDMA_GP1_EN, "ethdma_gp1_en", CLK_TOP_NETSYS_500M_SEL, 8), + GATE_ETH_TOP(CLK_ETHDMA_GP3_EN, "ethdma_gp3_en", CLK_TOP_NETSYS_500M_SEL, 10), +}; + +static int mt7987_ethsys_probe(struct udevice *dev) +{ + return mtk_common_clk_gate_init(dev, &mt7987_topckgen_clk_tree, + eth_cgs); +} + +static int mt7987_ethsys_bind(struct udevice *dev) +{ + int ret = 0; + + if (CONFIG_IS_ENABLED(RESET_MEDIATEK)) { + ret = mediatek_reset_bind(dev, ETHSYS_HIFSYS_RST_CTRL_OFS, 1); + if (ret) + debug("Warning: failed to bind reset controller\n"); + } + + return ret; +} + +static const struct udevice_id mt7987_ethsys_compat[] = { + { + .compatible = "mediatek,mt7987-ethsys", + }, + {} +}; + +U_BOOT_DRIVER(mtk_clk_ethsys) = { + .name = "mt7987-clock-ethsys", + .id = UCLASS_CLK, + .of_match = mt7987_ethsys_compat, + .probe = mt7987_ethsys_probe, + .bind = mt7987_ethsys_bind, + .priv_auto = sizeof(struct mtk_cg_priv), + .ops = &mtk_clk_gate_ops, +}; diff --git a/drivers/clk/mediatek/clk-mt7988.c b/drivers/clk/mediatek/clk-mt7988.c index 8f4e8f4e8c9..73fd9c6bea6 100644 --- a/drivers/clk/mediatek/clk-mt7988.c +++ b/drivers/clk/mediatek/clk-mt7988.c @@ -485,6 +485,7 @@ static const int infra_pcie_gfmux_tl_ck_o_p3_parents[] = { .id = _id, .mux_reg = _reg + 0x8, .mux_set_reg = _reg + 0x0, \ .mux_clr_reg = _reg + 0x4, .mux_shift = _shift, \ .mux_mask = BIT(_width) - 1, .parent = _parents, \ + .gate_shift = -1, .upd_shift = -1, \ .num_parents = ARRAY_SIZE(_parents), \ .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_TOPCKGEN, \ } diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index d76fca5dba4..cb867acc48c 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -47,6 +47,14 @@ config CLK_QCOM_QCS404 on the Snapdragon QCS404 SoC. This driver supports the clocks and resets exposed by the GCC hardware block. +config CLK_QCOM_SA8775P + bool "Qualcomm SA8775 GCC" + select CLK_QCOM + help + Say Y here to enable support for the Global Clock Controller + on the Snapdragon SA8775 SoC. This driver supports the clocks + and resets exposed by the GCC hardware block. + config CLK_QCOM_SDM845 bool "Qualcomm SDM845 GCC" select CLK_QCOM @@ -103,6 +111,14 @@ config CLK_QCOM_SC7280 on the Snapdragon SC7280 SoC. This driver supports the clocks and resets exposed by the GCC hardware block. +config CLK_QCOM_X1E80100 + bool "Qualcomm X1E80100 GCC" + select CLK_QCOM + help + Say Y here to enable support for the Global Clock Controller + on the Snapdragon X1E80100 SoC. This driver supports the clocks + and resets exposed by the GCC hardware block. + endmenu endif diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index ab33f1c5faf..1bc0f15005b 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -9,9 +9,11 @@ obj-$(CONFIG_CLK_QCOM_APQ8096) += clock-apq8096.o obj-$(CONFIG_CLK_QCOM_IPQ4019) += clock-ipq4019.o obj-$(CONFIG_CLK_QCOM_QCM2290) += clock-qcm2290.o obj-$(CONFIG_CLK_QCOM_QCS404) += clock-qcs404.o +obj-$(CONFIG_CLK_QCOM_SA8775P) += clock-sa8775p.o obj-$(CONFIG_CLK_QCOM_SC7280) += clock-sc7280.o obj-$(CONFIG_CLK_QCOM_SM6115) += clock-sm6115.o obj-$(CONFIG_CLK_QCOM_SM8150) += clock-sm8150.o obj-$(CONFIG_CLK_QCOM_SM8250) += clock-sm8250.o obj-$(CONFIG_CLK_QCOM_SM8550) += clock-sm8550.o obj-$(CONFIG_CLK_QCOM_SM8650) += clock-sm8650.o +obj-$(CONFIG_CLK_QCOM_X1E80100) += clock-x1e80100.o diff --git a/drivers/clk/qcom/clock-qcom.c b/drivers/clk/qcom/clock-qcom.c index 25ca67e537d..7687bbe6a23 100644 --- a/drivers/clk/qcom/clock-qcom.c +++ b/drivers/clk/qcom/clock-qcom.c @@ -166,6 +166,25 @@ void clk_rcg_set_rate(phys_addr_t base, uint32_t cmd_rcgr, int div, clk_bcr_update(base + cmd_rcgr); } +#define PHY_MUX_MASK GENMASK(1, 0) +#define PHY_MUX_PHY_SRC 0 +#define PHY_MUX_REF_SRC 2 + +void clk_phy_mux_enable(phys_addr_t base, uint32_t cmd_rcgr, bool enabled) +{ + u32 cfg; + + /* setup src select and divider */ + cfg = readl(base + cmd_rcgr); + cfg &= ~(PHY_MUX_MASK); + if (enabled) + cfg |= FIELD_PREP(PHY_MUX_MASK, PHY_MUX_PHY_SRC); + else + cfg |= FIELD_PREP(PHY_MUX_MASK, PHY_MUX_REF_SRC); + + writel(cfg, base + cmd_rcgr); +} + const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, uint rate) { if (!f) diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h index 78d9b1d81ec..ff336dea39c 100644 --- a/drivers/clk/qcom/clock-qcom.h +++ b/drivers/clk/qcom/clock-qcom.h @@ -6,6 +6,7 @@ #define _CLOCK_QCOM_H #include <asm/io.h> +#include <linux/bitfield.h> #define CFG_CLK_SRC_CXO (0 << 8) #define CFG_CLK_SRC_GPLL0 (1 << 8) @@ -102,6 +103,7 @@ void clk_rcg_set_rate_mnd(phys_addr_t base, uint32_t cmd_rcgr, int div, int m, int n, int source, u8 mnd_width); void clk_rcg_set_rate(phys_addr_t base, uint32_t cmd_rcgr, int div, int source); +void clk_phy_mux_enable(phys_addr_t base, uint32_t cmd_rcgr, bool enabled); static inline void qcom_gate_clk_en(const struct msm_clk_priv *priv, unsigned long id) { diff --git a/drivers/clk/qcom/clock-sa8775p.c b/drivers/clk/qcom/clock-sa8775p.c new file mode 100644 index 00000000000..e31f24ed4f0 --- /dev/null +++ b/drivers/clk/qcom/clock-sa8775p.c @@ -0,0 +1,142 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Clock drivers for Qualcomm sa8775p + * + * (C) Copyright 2024 Linaro Ltd. + */ + +#include <linux/types.h> +#include <clk-uclass.h> +#include <dm.h> +#include <linux/delay.h> +#include <asm/io.h> +#include <linux/bug.h> +#include <linux/bitops.h> +#include <dt-bindings/clock/qcom,sa8775p-gcc.h> +#include "clock-qcom.h" + +#define USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR 0xf038 +#define USB30_PRIM_MASTER_CLK_CMD_RCGR 0xf020 + +static ulong sa8775p_set_rate(struct clk *clk, ulong rate) +{ + struct msm_clk_priv *priv = dev_get_priv(clk->dev); + + if (clk->id < priv->data->num_clks) + debug("%s: %s, requested rate=%ld\n", __func__, + priv->data->clks[clk->id].name, rate); + + switch (clk->id) { + case GCC_USB30_PRIM_MOCK_UTMI_CLK: + WARN(rate != 19200000, "Unexpected rate for USB30_PRIM_MOCK_UTMI_CLK: %lu\n", rate); + clk_rcg_set_rate(priv->base, USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR, 0, CFG_CLK_SRC_CXO); + return rate; + case GCC_USB30_PRIM_MASTER_CLK: + WARN(rate != 200000000, "Unexpected rate for USB30_PRIM_MASTER_CLK: %lu\n", rate); + clk_rcg_set_rate_mnd(priv->base, USB30_PRIM_MASTER_CLK_CMD_RCGR, + 1, 0, 0, CFG_CLK_SRC_GPLL0_ODD, 8); + clk_rcg_set_rate(priv->base, 0xf064, 0, 0); + return rate; + default: + return 0; + } +} + +static const struct gate_clk sa8775p_clks[] = { + GATE_CLK(GCC_CFG_NOC_USB3_PRIM_AXI_CLK, 0x1b088, 1), + GATE_CLK(GCC_USB30_PRIM_MASTER_CLK, 0x1b018, 1), + GATE_CLK(GCC_AGGRE_USB3_PRIM_AXI_CLK, 0x1b084, 1), + GATE_CLK(GCC_USB30_PRIM_SLEEP_CLK, 0x1b020, 1), + GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0x1b024, 1), + GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK, 0x1b05c, 1), + GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0x1b060, 1), +}; + +static int sa8775p_enable(struct clk *clk) +{ + struct msm_clk_priv *priv = dev_get_priv(clk->dev); + + if (priv->data->num_clks < clk->id) { + debug("%s: unknown clk id %lu\n", __func__, clk->id); + return 0; + } + + debug("%s: clk %ld: %s\n", __func__, clk->id, sa8775p_clks[clk->id].name); + + switch (clk->id) { + case GCC_AGGRE_USB3_PRIM_AXI_CLK: + qcom_gate_clk_en(priv, GCC_USB30_PRIM_MASTER_CLK); + fallthrough; + case GCC_USB30_PRIM_MASTER_CLK: + qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_AUX_CLK); + qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_COM_AUX_CLK); + break; + } + + qcom_gate_clk_en(priv, clk->id); + + return 0; +} + +static const struct qcom_reset_map sa8775p_gcc_resets[] = { + [GCC_CAMERA_BCR] = { 0x32000 }, + [GCC_DISPLAY1_BCR] = { 0xC7000 }, + [GCC_DISPLAY_BCR] = { 0x33000 }, + [GCC_EMAC0_BCR] = { 0xB6000 }, + [GCC_EMAC1_BCR] = { 0xB4000 }, + [GCC_GPU_BCR] = { 0x7D000 }, + [GCC_MMSS_BCR] = { 0x17000 }, + [GCC_PCIE_0_BCR] = { 0xa9000 }, + [GCC_PCIE_0_LINK_DOWN_BCR] = { 0xBF000 }, + [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0xBF008 }, + [GCC_PCIE_0_PHY_BCR] = { 0xAD144 }, + [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0xBF00C }, + [GCC_PCIE_1_BCR] = { 0x77000 }, + [GCC_PCIE_1_LINK_DOWN_BCR] = { 0xAE084 }, + [GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0xAE090 }, + [GCC_PCIE_1_PHY_BCR] = { 0xAE08C }, + [GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0xAE094 }, + [GCC_PDM_BCR] = { 0x3F000 }, + [GCC_QUPV3_WRAPPER_0_BCR] = { 0x23000 }, + [GCC_QUPV3_WRAPPER_1_BCR] = { 0x24000 }, + [GCC_QUPV3_WRAPPER_2_BCR] = { 0x2A000 }, + [GCC_QUPV3_WRAPPER_3_BCR] = { 0xC4000 }, + [GCC_SDCC1_BCR] = { 0x20000 }, + [GCC_TSCSS_BCR] = { 0x21000 }, + [GCC_UFS_CARD_BCR] = { 0x81000 }, + [GCC_UFS_PHY_BCR] = { 0x83000 }, +}; + +static const struct qcom_power_map sa8775p_gdscs[] = { + [UFS_PHY_GDSC] = { 0x83004 }, + [USB30_PRIM_GDSC] = { 0x1B004 }, +}; + +static struct msm_clk_data sa8775_gcc_data = { + .resets = sa8775p_gcc_resets, + .num_resets = ARRAY_SIZE(sa8775p_gcc_resets), + .clks = sa8775p_clks, + .num_clks = ARRAY_SIZE(sa8775p_clks), + + .power_domains = sa8775p_gdscs, + .num_power_domains = ARRAY_SIZE(sa8775p_gdscs), + + .enable = sa8775p_enable, + .set_rate = sa8775p_set_rate, +}; + +static const struct udevice_id gcc_sa8775p_of_match[] = { + { + .compatible = "qcom,sa8775p-gcc", + .data = (ulong)&sa8775_gcc_data, + }, + { } +}; + +U_BOOT_DRIVER(gcc_sa8775p) = { + .name = "gcc_sa8775p", + .id = UCLASS_NOP, + .of_match = gcc_sa8775p_of_match, + .bind = qcom_cc_bind, + .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF, +}; diff --git a/drivers/clk/qcom/clock-sm8550.c b/drivers/clk/qcom/clock-sm8550.c index c0249925cc7..62b5a409e8e 100644 --- a/drivers/clk/qcom/clock-sm8550.c +++ b/drivers/clk/qcom/clock-sm8550.c @@ -57,6 +57,16 @@ static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { { } }; +static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = { + F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0), + { } +}; + +static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = { + F(100000000, CFG_CLK_SRC_GPLL0_EVEN, 3, 0, 0), + { } +}; + static ulong sm8550_set_rate(struct clk *clk, ulong rate) { struct msm_clk_priv *priv = dev_get_priv(clk->dev); @@ -84,6 +94,24 @@ static ulong sm8550_set_rate(struct clk *clk, ulong rate) case GCC_USB3_PRIM_PHY_AUX_CLK_SRC: clk_rcg_set_rate(priv->base, 0x39070, 0, 0); return TCXO_DIV2_RATE; + case GCC_PCIE_0_AUX_CLK: + freq = qcom_find_freq(ftbl_gcc_pcie_0_aux_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, 0x6b074, + freq->pre_div, freq->m, freq->n, freq->src, 16); + return freq->freq; + case GCC_PCIE_1_AUX_CLK: + freq = qcom_find_freq(ftbl_gcc_pcie_0_aux_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, 0x8d07c, + freq->pre_div, freq->m, freq->n, freq->src, 16); + return freq->freq; + case GCC_PCIE_0_PHY_RCHNG_CLK: + freq = qcom_find_freq(ftbl_gcc_pcie_0_phy_rchng_clk_src, rate); + clk_rcg_set_rate(priv->base, 0x6b058, freq->pre_div, freq->src); + return freq->freq; + case GCC_PCIE_1_PHY_RCHNG_CLK: + freq = qcom_find_freq(ftbl_gcc_pcie_0_phy_rchng_clk_src, rate); + clk_rcg_set_rate(priv->base, 0x8d060, freq->pre_div, freq->src); + return freq->freq; default: return 0; } @@ -182,6 +210,14 @@ static int sm8550_enable(struct clk *clk) qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_AUX_CLK); qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_COM_AUX_CLK); break; + case GCC_PCIE_0_PIPE_CLK: + // GCC_PCIE_0_PIPE_CLK_SRC + clk_phy_mux_enable(priv->base, 0x6b070, true); + break; + case GCC_PCIE_1_PIPE_CLK: + // GCC_PCIE_1_PIPE_CLK_SRC + clk_phy_mux_enable(priv->base, 0x8d078, true); + break; } qcom_gate_clk_en(priv, clk->id); diff --git a/drivers/clk/qcom/clock-sm8650.c b/drivers/clk/qcom/clock-sm8650.c index 0ce83e9b243..9baaecb571f 100644 --- a/drivers/clk/qcom/clock-sm8650.c +++ b/drivers/clk/qcom/clock-sm8650.c @@ -54,6 +54,16 @@ static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { { } }; +static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = { + F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0), + { } +}; + +static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = { + F(100000000, CFG_CLK_SRC_GPLL0_EVEN, 3, 0, 0), + { } +}; + static ulong sm8650_set_rate(struct clk *clk, ulong rate) { struct msm_clk_priv *priv = dev_get_priv(clk->dev); @@ -81,6 +91,24 @@ static ulong sm8650_set_rate(struct clk *clk, ulong rate) case GCC_USB3_PRIM_PHY_AUX_CLK_SRC: clk_rcg_set_rate(priv->base, 0x39070, 0, 0); return TCXO_DIV2_RATE; + case GCC_PCIE_0_AUX_CLK: + freq = qcom_find_freq(ftbl_gcc_pcie_0_aux_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, 0x6b074, + freq->pre_div, freq->m, freq->n, freq->src, 16); + return freq->freq; + case GCC_PCIE_1_AUX_CLK: + freq = qcom_find_freq(ftbl_gcc_pcie_0_aux_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, 0x8d07c, + freq->pre_div, freq->m, freq->n, freq->src, 16); + return freq->freq; + case GCC_PCIE_0_PHY_RCHNG_CLK: + freq = qcom_find_freq(ftbl_gcc_pcie_0_phy_rchng_clk_src, rate); + clk_rcg_set_rate(priv->base, 0x6b058, freq->pre_div, freq->src); + return freq->freq; + case GCC_PCIE_1_PHY_RCHNG_CLK: + freq = qcom_find_freq(ftbl_gcc_pcie_0_phy_rchng_clk_src, rate); + clk_rcg_set_rate(priv->base, 0x8d060, freq->pre_div, freq->src); + return freq->freq; default: return 0; } @@ -179,6 +207,14 @@ static int sm8650_enable(struct clk *clk) qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_AUX_CLK); qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_COM_AUX_CLK); break; + case GCC_PCIE_0_PIPE_CLK: + // GCC_PCIE_0_PIPE_CLK_SRC + clk_phy_mux_enable(priv->base, 0x6b070, true); + break; + case GCC_PCIE_1_PIPE_CLK: + // GCC_PCIE_1_PIPE_CLK_SRC + clk_phy_mux_enable(priv->base, 0x8d078, true); + break; } qcom_gate_clk_en(priv, clk->id); diff --git a/drivers/clk/qcom/clock-x1e80100.c b/drivers/clk/qcom/clock-x1e80100.c new file mode 100644 index 00000000000..bd9c6ed1c8a --- /dev/null +++ b/drivers/clk/qcom/clock-x1e80100.c @@ -0,0 +1,402 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Clock drivers for Qualcomm x1e80100 + * + * (C) Copyright 2024 Linaro Ltd. + */ + +#include <clk-uclass.h> +#include <dm.h> +#include <linux/delay.h> +#include <errno.h> +#include <asm/io.h> +#include <linux/bug.h> +#include <linux/bitops.h> +#include <dt-bindings/clock/qcom,x1e80100-gcc.h> +#include <dt-bindings/clock/qcom,x1e80100-tcsr.h> + +#include "clock-qcom.h" + +/* On-board TCXO, TOFIX get from DT */ +#define TCXO_RATE 38400000 + +/* bi_tcxo_div2 divided after RPMh output */ +#define TCXO_DIV2_RATE (TCXO_RATE / 2) + +static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s4_clk_src[] = { + F(7372800, CFG_CLK_SRC_GPLL0_EVEN, 1, 384, 15625), + F(14745600, CFG_CLK_SRC_GPLL0_EVEN, 1, 768, 15625), + F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0), + F(29491200, CFG_CLK_SRC_GPLL0_EVEN, 1, 1536, 15625), + F(32000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 75), + F(48000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 25), + F(64000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 16, 75), + F(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0), + F(80000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 15), + F(96000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 25), + F(100000000, CFG_CLK_SRC_GPLL0, 6, 0, 0), + { } +}; + +static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { + F(400000, CFG_CLK_SRC_CXO, 12, 1, 4), + F(25000000, CFG_CLK_SRC_GPLL0_EVEN, 12, 0, 0), + F(100000000, CFG_CLK_SRC_GPLL0_EVEN, 3, 0, 0), + /* TOFIX F(202000000, CFG_CLK_SRC_GPLL9, 4, 0, 0), */ + { } +}; + +static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { + F(66666667, CFG_CLK_SRC_GPLL0_EVEN, 4.5, 0, 0), + F(133333333, CFG_CLK_SRC_GPLL0, 4.5, 0, 0), + F(200000000, CFG_CLK_SRC_GPLL0, 3, 0, 0), + F(240000000, CFG_CLK_SRC_GPLL0, 2.5, 0, 0), + { } +}; + +static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = { + F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0), + { } +}; + +static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = { + F(100000000, CFG_CLK_SRC_GPLL0_EVEN, 3, 0, 0), + { } +}; + +static ulong x1e80100_set_rate(struct clk *clk, ulong rate) +{ + struct msm_clk_priv *priv = dev_get_priv(clk->dev); + const struct freq_tbl *freq; + + switch (clk->id) { + case GCC_QUPV3_WRAP2_S5_CLK: /* UART21 */ + freq = qcom_find_freq(ftbl_gcc_qupv3_wrap0_s4_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, 0x1e500, + freq->pre_div, freq->m, freq->n, freq->src, 16); + return freq->freq; + case GCC_SDCC2_APPS_CLK: + freq = qcom_find_freq(ftbl_gcc_sdcc2_apps_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, 0x14018, + freq->pre_div, freq->m, freq->n, freq->src, 8); + return freq->freq; + case GCC_USB30_PRIM_MASTER_CLK: + freq = qcom_find_freq(ftbl_gcc_usb30_prim_master_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, 0x3902c, + freq->pre_div, freq->m, freq->n, freq->src, 8); + return freq->freq; + case GCC_USB30_PRIM_MOCK_UTMI_CLK: + clk_rcg_set_rate(priv->base, 0x39044, 0, 0); + return TCXO_DIV2_RATE; + case GCC_PCIE_4_AUX_CLK: + freq = qcom_find_freq(ftbl_gcc_pcie_0_aux_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, 0x6b080, + freq->pre_div, freq->m, freq->n, freq->src, 16); + return freq->freq; + case GCC_PCIE_4_PHY_RCHNG_CLK: + freq = qcom_find_freq(ftbl_gcc_pcie_0_phy_rchng_clk_src, rate); + clk_rcg_set_rate(priv->base, 0x6b064, freq->pre_div, freq->src); + return freq->freq; + case GCC_PCIE_6A_AUX_CLK: + freq = qcom_find_freq(ftbl_gcc_pcie_0_aux_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, 0x3108c, + freq->pre_div, freq->m, freq->n, freq->src, 16); + return freq->freq; + case GCC_PCIE_6A_PHY_RCHNG_CLK: + freq = qcom_find_freq(ftbl_gcc_pcie_0_phy_rchng_clk_src, rate); + clk_rcg_set_rate(priv->base, 0x31070, freq->pre_div, freq->src); + return freq->freq; + default: + return 0; + } +} + +static const struct gate_clk x1e80100_clks[] = { + GATE_CLK(GCC_AGGRE_UFS_PHY_AXI_CLK, 0x770e4, BIT(0)), + GATE_CLK(GCC_CFG_NOC_USB3_PRIM_AXI_CLK, 0x3908c, BIT(0)), + GATE_CLK(GCC_CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK, 0x52000, BIT(20)), + GATE_CLK(GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK, 0x52028, BIT(22)), + GATE_CLK(GCC_CNOC_PCIE_SOUTH_SF_AXI_CLK, 0x52028, BIT(12)), + GATE_CLK(GCC_CNOC_PCIE_NORTH_SF_AXI_CLK, 0x52008, BIT(6)), + GATE_CLK(GCC_PCIE_4_AUX_CLK, 0x52008, BIT(3)), + GATE_CLK(GCC_PCIE_4_CFG_AHB_CLK, 0x52008, BIT(2)), + GATE_CLK(GCC_PCIE_4_MSTR_AXI_CLK, 0x52008, BIT(1)), + GATE_CLK(GCC_PCIE_4_PHY_RCHNG_CLK, 0x52000, BIT(22)), + GATE_CLK(GCC_PCIE_4_PIPE_CLK, 0x52008, BIT(4)), + GATE_CLK(GCC_PCIE_4_SLV_AXI_CLK, 0x52008, BIT(0)), + GATE_CLK(GCC_PCIE_4_SLV_Q2A_AXI_CLK, 0x52008, BIT(5)), + GATE_CLK(GCC_PCIE_6A_AUX_CLK, 0x52018, BIT(24)), + GATE_CLK(GCC_PCIE_6A_CFG_AHB_CLK, 0x52018, BIT(23)), + GATE_CLK(GCC_PCIE_6A_MSTR_AXI_CLK, 0x52018, BIT(22)), + GATE_CLK(GCC_PCIE_6A_PHY_RCHNG_CLK, 0x52018, BIT(27)), + GATE_CLK(GCC_PCIE_6A_PIPE_CLK, 0x52018, BIT(26)), + GATE_CLK(GCC_PCIE_6A_SLV_AXI_CLK, 0x52018, BIT(21)), + GATE_CLK(GCC_PCIE_6A_SLV_Q2A_AXI_CLK, 0x52018, BIT(20)), + GATE_CLK(GCC_QUPV3_WRAP2_CORE_2X_CLK, 0x52010, BIT(3)), + GATE_CLK(GCC_QUPV3_WRAP2_CORE_CLK, 0x52010, BIT(0)), + GATE_CLK(GCC_QUPV3_WRAP2_S0_CLK, 0x52010, BIT(4)), + GATE_CLK(GCC_QUPV3_WRAP2_S1_CLK, 0x52010, BIT(5)), + GATE_CLK(GCC_QUPV3_WRAP2_S2_CLK, 0x52010, BIT(6)), + GATE_CLK(GCC_QUPV3_WRAP2_S3_CLK, 0x52010, BIT(7)), + GATE_CLK(GCC_QUPV3_WRAP2_S4_CLK, 0x52010, BIT(8)), + GATE_CLK(GCC_QUPV3_WRAP2_S5_CLK, 0x52010, BIT(9)), + GATE_CLK(GCC_QUPV3_WRAP2_S6_CLK, 0x52010, BIT(10)), + GATE_CLK(GCC_QUPV3_WRAP2_S7_CLK, 0x52010, BIT(17)), + GATE_CLK(GCC_QUPV3_WRAP_2_M_AHB_CLK, 0x52010, BIT(2)), + GATE_CLK(GCC_QUPV3_WRAP_2_S_AHB_CLK, 0x52010, BIT(1)), + GATE_CLK(GCC_USB30_PRIM_MASTER_CLK, 0x39018, BIT(0)), + GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0x39028, BIT(0)), + GATE_CLK(GCC_USB30_PRIM_SLEEP_CLK, 0x39024, BIT(0)), + GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK, 0x39060, BIT(0)), + GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0x39064, BIT(0)), + GATE_CLK(GCC_USB3_PRIM_PHY_PIPE_CLK, 0x39068, BIT(0)), +}; + +static int x1e80100_enable(struct clk *clk) +{ + struct msm_clk_priv *priv = dev_get_priv(clk->dev); + + switch (clk->id) { + case GCC_AGGRE_USB3_PRIM_AXI_CLK: + qcom_gate_clk_en(priv, GCC_USB30_PRIM_MASTER_CLK); + fallthrough; + case GCC_USB30_PRIM_MASTER_CLK: + qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_AUX_CLK); + qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_COM_AUX_CLK); + break; + case GCC_PCIE_4_PIPE_CLK: + // GCC_PCIE_4_PIPE_CLK_SRC + clk_phy_mux_enable(priv->base, 0x6b07c, true); + break; + case GCC_PCIE_6A_PIPE_CLK: + // GCC_PCIE_6A_PIPE_CLK_SRC + clk_phy_mux_enable(priv->base, 0x31088, true); + break; + } + + qcom_gate_clk_en(priv, clk->id); + + return 0; +} + +static const struct qcom_reset_map x1e80100_gcc_resets[] = { + [GCC_AV1E_BCR] = { 0x4a000 }, + [GCC_CAMERA_BCR] = { 0x26000 }, + [GCC_DISPLAY_BCR] = { 0x27000 }, + [GCC_GPU_BCR] = { 0x71000 }, + [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 }, + [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 }, + [GCC_PCIE_0_PHY_BCR] = { 0x6c01c }, + [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x6c028 }, + [GCC_PCIE_0_TUNNEL_BCR] = { 0xa0000 }, + [GCC_PCIE_1_LINK_DOWN_BCR] = { 0x8e014 }, + [GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x8e020 }, + [GCC_PCIE_1_PHY_BCR] = { 0x8e01c }, + [GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x8e024 }, + [GCC_PCIE_1_TUNNEL_BCR] = { 0x2c000 }, + [GCC_PCIE_2_LINK_DOWN_BCR] = { 0xa5014 }, + [GCC_PCIE_2_NOCSR_COM_PHY_BCR] = { 0xa5020 }, + [GCC_PCIE_2_PHY_BCR] = { 0xa501c }, + [GCC_PCIE_2_PHY_NOCSR_COM_PHY_BCR] = { 0xa5028 }, + [GCC_PCIE_2_TUNNEL_BCR] = { 0x13000 }, + [GCC_PCIE_3_BCR] = { 0x58000 }, + [GCC_PCIE_3_LINK_DOWN_BCR] = { 0xab014 }, + [GCC_PCIE_3_NOCSR_COM_PHY_BCR] = { 0xab020 }, + [GCC_PCIE_3_PHY_BCR] = { 0xab01c }, + [GCC_PCIE_3_PHY_NOCSR_COM_PHY_BCR] = { 0xab024 }, + [GCC_PCIE_4_BCR] = { 0x6b000 }, + [GCC_PCIE_4_LINK_DOWN_BCR] = { 0xb3014 }, + [GCC_PCIE_4_NOCSR_COM_PHY_BCR] = { 0xb3020 }, + [GCC_PCIE_4_PHY_BCR] = { 0xb301c }, + [GCC_PCIE_4_PHY_NOCSR_COM_PHY_BCR] = { 0xb3028 }, + [GCC_PCIE_5_BCR] = { 0x2f000 }, + [GCC_PCIE_5_LINK_DOWN_BCR] = { 0xaa014 }, + [GCC_PCIE_5_NOCSR_COM_PHY_BCR] = { 0xaa020 }, + [GCC_PCIE_5_PHY_BCR] = { 0xaa01c }, + [GCC_PCIE_5_PHY_NOCSR_COM_PHY_BCR] = { 0xaa028 }, + [GCC_PCIE_6A_BCR] = { 0x31000 }, + [GCC_PCIE_6A_LINK_DOWN_BCR] = { 0xac014 }, + [GCC_PCIE_6A_NOCSR_COM_PHY_BCR] = { 0xac020 }, + [GCC_PCIE_6A_PHY_BCR] = { 0xac01c }, + [GCC_PCIE_6A_PHY_NOCSR_COM_PHY_BCR] = { 0xac024 }, + [GCC_PCIE_6B_BCR] = { 0x8d000 }, + [GCC_PCIE_6B_LINK_DOWN_BCR] = { 0xb5014 }, + [GCC_PCIE_6B_NOCSR_COM_PHY_BCR] = { 0xb5020 }, + [GCC_PCIE_6B_PHY_BCR] = { 0xb501c }, + [GCC_PCIE_6B_PHY_NOCSR_COM_PHY_BCR] = { 0xb5024 }, + [GCC_PCIE_PHY_BCR] = { 0x6f000 }, + [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f00c }, + [GCC_PCIE_PHY_COM_BCR] = { 0x6f010 }, + [GCC_PCIE_RSCC_BCR] = { 0xa4000 }, + [GCC_PDM_BCR] = { 0x33000 }, + [GCC_QUPV3_WRAPPER_0_BCR] = { 0x42000 }, + [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 }, + [GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 }, + [GCC_QUSB2PHY_HS0_MP_BCR] = { 0x1200c }, + [GCC_QUSB2PHY_HS1_MP_BCR] = { 0x12010 }, + [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 }, + [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 }, + [GCC_QUSB2PHY_TERT_BCR] = { 0x12008 }, + [GCC_QUSB2PHY_USB20_HS_BCR] = { 0x12014 }, + [GCC_SDCC2_BCR] = { 0x14000 }, + [GCC_SDCC4_BCR] = { 0x16000 }, + [GCC_UFS_PHY_BCR] = { 0x77000 }, + [GCC_USB20_PRIM_BCR] = { 0x29000 }, + [GCC_USB30_MP_BCR] = { 0x17000 }, + [GCC_USB30_PRIM_BCR] = { 0x39000 }, + [GCC_USB30_SEC_BCR] = { 0xa1000 }, + [GCC_USB30_TERT_BCR] = { 0xa2000 }, + [GCC_USB3_MP_SS0_PHY_BCR] = { 0x19008 }, + [GCC_USB3_MP_SS1_PHY_BCR] = { 0x54008 }, + [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 }, + [GCC_USB3_PHY_SEC_BCR] = { 0x2a000 }, + [GCC_USB3_PHY_TERT_BCR] = { 0xa3000 }, + [GCC_USB3_UNIPHY_MP0_BCR] = { 0x19000 }, + [GCC_USB3_UNIPHY_MP1_BCR] = { 0x54000 }, + [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 }, + [GCC_USB3PHY_PHY_SEC_BCR] = { 0x2a004 }, + [GCC_USB3PHY_PHY_TERT_BCR] = { 0xa3004 }, + [GCC_USB3UNIPHY_PHY_MP0_BCR] = { 0x19004 }, + [GCC_USB3UNIPHY_PHY_MP1_BCR] = { 0x54004 }, + [GCC_USB4_0_BCR] = { 0x9f000 }, + [GCC_USB4_0_DP0_PHY_PRIM_BCR] = { 0x50010 }, + [GCC_USB4_1_DP0_PHY_SEC_BCR] = { 0x2a010 }, + [GCC_USB4_2_DP0_PHY_TERT_BCR] = { 0xa3010 }, + [GCC_USB4_1_BCR] = { 0x2b000 }, + [GCC_USB4_2_BCR] = { 0x11000 }, + [GCC_USB_0_PHY_BCR] = { 0x50020 }, + [GCC_USB_1_PHY_BCR] = { 0x2a020 }, + [GCC_USB_2_PHY_BCR] = { 0xa3020 }, + [GCC_VIDEO_BCR] = { 0x32000 }, +}; + +static const struct qcom_power_map x1e80100_gdscs[] = { + [GCC_PCIE_0_TUNNEL_GDSC] = { 0xa0004 }, + [GCC_PCIE_1_TUNNEL_GDSC] = { 0x2c004 }, + [GCC_PCIE_2_TUNNEL_GDSC] = { 0x13004 }, + [GCC_PCIE_3_GDSC] = { 0x58004 }, + [GCC_PCIE_3_PHY_GDSC] = { 0x3e000 }, + [GCC_PCIE_4_GDSC] = { 0x6b004 }, + [GCC_PCIE_4_PHY_GDSC] = { 0x6c000 }, + [GCC_PCIE_5_GDSC] = { 0x2f004 }, + [GCC_PCIE_5_PHY_GDSC] = { 0x30000 }, + [GCC_PCIE_6_PHY_GDSC] = { 0x8e000 }, + [GCC_PCIE_6A_GDSC] = { 0x31004 }, + [GCC_PCIE_6B_GDSC] = { 0x8d004 }, + [GCC_UFS_MEM_PHY_GDSC] = { 0x9e000 }, + [GCC_UFS_PHY_GDSC] = { 0x77004 }, + [GCC_USB20_PRIM_GDSC] = { 0x29004 }, + [GCC_USB30_MP_GDSC] = { 0x17004 }, + [GCC_USB30_PRIM_GDSC] = { 0x39004 }, + [GCC_USB30_SEC_GDSC] = { 0xa1004 }, + [GCC_USB30_TERT_GDSC] = { 0xa2004 }, + [GCC_USB3_MP_SS0_PHY_GDSC] = { 0x1900c }, + [GCC_USB3_MP_SS1_PHY_GDSC] = { 0x5400c }, + [GCC_USB4_0_GDSC] = { 0x9f004 }, + [GCC_USB4_1_GDSC] = { 0x2b004 }, + [GCC_USB4_2_GDSC] = { 0x11004 }, + [GCC_USB_0_PHY_GDSC] = { 0x50024 }, + [GCC_USB_1_PHY_GDSC] = { 0x2a024 }, + [GCC_USB_2_PHY_GDSC] = { 0xa3024 }, +}; + +static struct msm_clk_data x1e80100_gcc_data = { + .resets = x1e80100_gcc_resets, + .num_resets = ARRAY_SIZE(x1e80100_gcc_resets), + .clks = x1e80100_clks, + .num_clks = ARRAY_SIZE(x1e80100_clks), + .power_domains = x1e80100_gdscs, + .num_power_domains = ARRAY_SIZE(x1e80100_gdscs), + + .enable = x1e80100_enable, + .set_rate = x1e80100_set_rate, +}; + +static const struct udevice_id gcc_x1e80100_of_match[] = { + { + .compatible = "qcom,x1e80100-gcc", + .data = (ulong)&x1e80100_gcc_data, + }, + { } +}; + +U_BOOT_DRIVER(gcc_x1e80100) = { + .name = "gcc_x1e80100", + .id = UCLASS_NOP, + .of_match = gcc_x1e80100_of_match, + .bind = qcom_cc_bind, + .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF, +}; + +/* TCSRCC */ + +static const struct gate_clk x1e80100_tcsr_clks[] = { + GATE_CLK(TCSR_PCIE_2L_4_CLKREF_EN, 0x15100, BIT(0)), + GATE_CLK(TCSR_PCIE_2L_5_CLKREF_EN, 0x15104, BIT(0)), + GATE_CLK(TCSR_PCIE_8L_CLKREF_EN, 0x15108, BIT(0)), + GATE_CLK(TCSR_USB3_MP0_CLKREF_EN, 0x1510c, BIT(0)), + GATE_CLK(TCSR_USB3_MP1_CLKREF_EN, 0x15110, BIT(0)), + GATE_CLK(TCSR_USB2_1_CLKREF_EN, 0x15114, BIT(0)), + GATE_CLK(TCSR_UFS_PHY_CLKREF_EN, 0x15118, BIT(0)), + GATE_CLK(TCSR_USB4_1_CLKREF_EN, 0x15120, BIT(0)), + GATE_CLK(TCSR_USB4_2_CLKREF_EN, 0x15124, BIT(0)), + GATE_CLK(TCSR_USB2_2_CLKREF_EN, 0x15128, BIT(0)), + GATE_CLK(TCSR_PCIE_4L_CLKREF_EN, 0x1512c, BIT(0)), + GATE_CLK(TCSR_EDP_CLKREF_EN, 0x15130, BIT(0)), +}; + +static struct msm_clk_data x1e80100_tcsrcc_data = { + .clks = x1e80100_tcsr_clks, + .num_clks = ARRAY_SIZE(x1e80100_tcsr_clks), +}; + +static int tcsrcc_x1e80100_clk_enable(struct clk *clk) +{ + struct msm_clk_priv *priv = dev_get_priv(clk->dev); + + qcom_gate_clk_en(priv, clk->id); + + return 0; +} + +static ulong tcsrcc_x1e80100_clk_get_rate(struct clk *clk) +{ + return TCXO_RATE; +} + +static int tcsrcc_x1e80100_clk_probe(struct udevice *dev) +{ + struct msm_clk_data *data = (struct msm_clk_data *)dev_get_driver_data(dev); + struct msm_clk_priv *priv = dev_get_priv(dev); + + priv->base = dev_read_addr(dev); + if (priv->base == FDT_ADDR_T_NONE) + return -EINVAL; + + priv->data = data; + + return 0; +} + +static struct clk_ops tcsrcc_x1e80100_clk_ops = { + .enable = tcsrcc_x1e80100_clk_enable, + .get_rate = tcsrcc_x1e80100_clk_get_rate, +}; + +static const struct udevice_id tcsrcc_x1e80100_of_match[] = { + { + .compatible = "qcom,x1e80100-tcsr", + .data = (ulong)&x1e80100_tcsrcc_data, + }, + { } +}; + +U_BOOT_DRIVER(tcsrcc_x1e80100) = { + .name = "tcsrcc_x1e80100", + .id = UCLASS_CLK, + .of_match = tcsrcc_x1e80100_of_match, + .ops = &tcsrcc_x1e80100_clk_ops, + .priv_auto = sizeof(struct msm_clk_priv), + .probe = tcsrcc_x1e80100_clk_probe, + .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF, +}; diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c index 43c44fadbe7..a4ff1c41abb 100644 --- a/drivers/clk/rockchip/clk_rk3288.c +++ b/drivers/clk/rockchip/clk_rk3288.c @@ -903,11 +903,11 @@ static int __maybe_unused rk3288_gmac_set_parent(struct clk *clk, struct clk *pa int ret; /* - * If the requested parent is in the same clock-controller and - * the id is SCLK_MAC_PLL ("mac_pll_src"), switch to the internal - * clock. + * If the requested parent is in the same clock-controller the + * likely parent is the unexported SCLK_MAC_PLL ("mac_pll_src"), + * switch to the internal clock. */ - if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC_PLL)) { + if (parent->dev == clk->dev) { debug("%s: switching GAMC to SCLK_MAC_PLL\n", __func__); rk_clrsetreg(&cru->cru_clksel_con[21], RMII_EXTCLK_MASK, 0); return 0; diff --git a/drivers/clk/stm32/clk-stm32h7.c b/drivers/clk/stm32/clk-stm32h7.c index a554eda504d..6acf2ff0a8f 100644 --- a/drivers/clk/stm32/clk-stm32h7.c +++ b/drivers/clk/stm32/clk-stm32h7.c @@ -18,6 +18,9 @@ #include <dt-bindings/clock/stm32h7-clks.h> +/* must be equal to last peripheral clock index */ +#define LAST_PERIF_BANK SYSCFG_CK + /* RCC CR specific definitions */ #define RCC_CR_HSION BIT(0) #define RCC_CR_HSIRDY BIT(2) diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c index c8161827d1c..26e014d5c53 100644 --- a/drivers/core/ofnode.c +++ b/drivers/core/ofnode.c @@ -118,7 +118,7 @@ int oftree_new(oftree *treep) return log_msg_ret("liv", ret); tree = oftree_from_np(root); } else { - const int size = 1024; + const int size = 4096; void *fdt; ret = check_tree_count(); @@ -309,6 +309,29 @@ bool ofnode_name_eq(ofnode node, const char *name) return (strlen(name) == len) && !strncmp(node_name, name, len); } +bool ofnode_name_eq_unit(ofnode node, const char *name) +{ + const char *node_name, *p; + int len; + + assert(ofnode_valid(node)); + + node_name = ofnode_get_name(node); + + /* check the whole name */ + if (!strcmp(node_name, name)) + return true; + + /* if @name has no unit address, try the node name without it */ + len = strlen(name); + p = strchr(node_name, '@'); + if (p && !strchr(name, '@') && len == p - node_name && + !strncmp(node_name, name, len)) + return true; + + return false; +} + int ofnode_read_u8(ofnode node, const char *propname, u8 *outp) { const u8 *cell; @@ -576,14 +599,9 @@ ofnode ofnode_find_subnode(ofnode node, const char *subnode_name) log_debug("%s: %s: ", __func__, subnode_name); if (ofnode_is_np(node)) { - struct device_node *np = ofnode_to_np(node); - - for (np = np->child; np; np = np->sibling) { - if (!strcmp(subnode_name, np->name)) - break; - } - subnode = np_to_ofnode(np); + subnode = ofnode_find_subnode_unit(node, subnode_name); } else { + /* special case to avoid code-size increase */ int ooffset = fdt_subnode_offset(ofnode_to_fdt(node), ofnode_to_offset(node), subnode_name); subnode = noffset_to_ofnode(node, ooffset); @@ -594,6 +612,26 @@ ofnode ofnode_find_subnode(ofnode node, const char *subnode_name) return subnode; } +ofnode ofnode_find_subnode_unit(ofnode node, const char *subnode_name) +{ + ofnode subnode, found = ofnode_null(); + + assert(ofnode_valid(node)); + log_debug("%s: ", subnode_name); + + ofnode_for_each_subnode(subnode, node) { + if (ofnode_name_eq_unit(subnode, subnode_name)) { + found = subnode; + break; + } + } + + log_debug("%s\n", ofnode_valid(found) ? + ofnode_get_name(found) : "<none>"); + + return found; +} + int ofnode_read_u32_array(ofnode node, const char *propname, u32 *out_values, size_t sz) { @@ -1710,9 +1748,10 @@ ofnode ofnode_by_prop_value(ofnode from, const char *propname, int ofnode_write_prop(ofnode node, const char *propname, const void *value, int len, bool copy) { + int ret; + if (of_live_active()) { void *newval; - int ret; if (copy) { newval = malloc(len); @@ -1726,8 +1765,12 @@ int ofnode_write_prop(ofnode node, const char *propname, const void *value, free(newval); return ret; } else { - return fdt_setprop(ofnode_to_fdt(node), ofnode_to_offset(node), - propname, value, len); + ret = fdt_setprop(ofnode_to_fdt(node), ofnode_to_offset(node), + propname, value, len); + if (ret) + return ret == -FDT_ERR_NOSPACE ? -ENOSPC : -EINVAL; + + return 0; } } @@ -2015,7 +2058,7 @@ int ofnode_add_subnode(ofnode node, const char *name, ofnode *subnodep) ret = -EEXIST; } if (offset < 0) - return -EINVAL; + return offset == -FDT_ERR_NOSPACE ? -ENOSPC : -EINVAL; subnode = noffset_to_ofnode(node, offset); } diff --git a/drivers/core/root.c b/drivers/core/root.c index c7fb58285ca..15b8c83fee9 100644 --- a/drivers/core/root.c +++ b/drivers/core/root.c @@ -288,26 +288,40 @@ void *dm_priv_to_rw(void *priv) } #endif -static int dm_probe_devices(struct udevice *dev, bool pre_reloc_only) +/** + * dm_probe_devices() - Check whether to probe a device and all children + * + * Probes the device if DM_FLAG_PROBE_AFTER_BIND is enabled for it. Then scans + * all its children recursively to do the same. + * + * @dev: Device to (maybe) probe + * Return 0 if OK, -ve on error + */ +static int dm_probe_devices(struct udevice *dev) { - ofnode node = dev_ofnode(dev); struct udevice *child; - int ret; - - if (pre_reloc_only && - (!ofnode_valid(node) || !ofnode_pre_reloc(node)) && - !(dev->driver->flags & DM_FLAG_PRE_RELOC)) - goto probe_children; if (dev_get_flags(dev) & DM_FLAG_PROBE_AFTER_BIND) { + int ret; + ret = device_probe(dev); if (ret) return ret; } -probe_children: list_for_each_entry(child, &dev->child_head, sibling_node) - dm_probe_devices(child, pre_reloc_only); + dm_probe_devices(child); + + return 0; +} + +int dm_autoprobe(void) +{ + int ret; + + ret = dm_probe_devices(gd->dm_root); + if (ret) + return log_msg_ret("pro", ret); return 0; } @@ -344,7 +358,7 @@ static int dm_scan(bool pre_reloc_only) if (ret) return ret; - return dm_probe_devices(gd->dm_root, pre_reloc_only); + return 0; } int dm_init_and_scan(bool pre_reloc_only) diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c index dac4023ccfd..3013c4741d0 100644 --- a/drivers/dma/ti/k3-udma.c +++ b/drivers/dma/ti/k3-udma.c @@ -1331,6 +1331,8 @@ static int udma_get_mmrs(struct udevice *dev) continue; if (i == MMR_RCHANRT && ud->rchan_cnt == 0) continue; + if (i == MMR_RFLOW && ud->match_data->type == DMA_TYPE_BCDMA) + continue; ud->mmrs[i] = dev_read_addr_name_ptr(dev, mmr_names[i]); if (!ud->mmrs[i]) diff --git a/drivers/fastboot/fb_mmc.c b/drivers/fastboot/fb_mmc.c index f11eb66761b..dca7c222f35 100644 --- a/drivers/fastboot/fb_mmc.c +++ b/drivers/fastboot/fb_mmc.c @@ -211,8 +211,8 @@ static int fb_mmc_erase_mmc_hwpart(struct blk_desc *dev_desc) return 1; } - printf("........ erased %lu bytes from mmc hwpart[%u]\n", - dev_desc->lba * dev_desc->blksz, dev_desc->hwpart); + printf("........ erased %llu bytes from mmc hwpart[%u]\n", + (u64)(dev_desc->lba * dev_desc->blksz), dev_desc->hwpart); return 0; } @@ -257,8 +257,8 @@ static void fb_mmc_boot_ops(struct blk_desc *dev_desc, void *buffer, return; } - printf("........ wrote %lu bytes to EMMC_BOOT%d\n", - blkcnt * blksz, hwpart); + printf("........ wrote %llu bytes to EMMC_BOOT%d\n", + (u64)(blkcnt * blksz), hwpart); } else { /* erase */ if (fb_mmc_erase_mmc_hwpart(dev_desc)) { pr_err("Failed to erase EMMC_BOOT%d\n", hwpart); diff --git a/drivers/fpga/fpga.c b/drivers/fpga/fpga.c index 1f6782537de..f88267e01b6 100644 --- a/drivers/fpga/fpga.c +++ b/drivers/fpga/fpga.c @@ -33,9 +33,9 @@ static void fpga_no_sup(char *fn, char *msg) /* fpga_get_desc * map a device number to a descriptor */ -const fpga_desc *const fpga_get_desc(int devnum) +const fpga_desc *fpga_get_desc(int devnum) { - fpga_desc *desc = (fpga_desc *)NULL; + const fpga_desc *desc = NULL; if ((devnum >= 0) && (devnum < next_desc)) { desc = &desc_table[devnum]; @@ -50,8 +50,8 @@ const fpga_desc *const fpga_get_desc(int devnum) * fpga_validate * generic parameter checking code */ -const fpga_desc *const fpga_validate(int devnum, const void *buf, - size_t bsize, char *fn) +const fpga_desc *fpga_validate(int devnum, const void *buf, + size_t bsize, char *fn) { const fpga_desc *desc = fpga_get_desc(devnum); @@ -60,7 +60,7 @@ const fpga_desc *const fpga_validate(int devnum, const void *buf, if (!buf) { printf("%s: Null buffer.\n", fn); - return (fpga_desc * const)NULL; + return NULL; } return desc; } @@ -72,7 +72,7 @@ const fpga_desc *const fpga_validate(int devnum, const void *buf, static int fpga_dev_info(int devnum) { int ret_val = FPGA_FAIL; /* assume failure */ - const fpga_desc * const desc = fpga_get_desc(devnum); + const fpga_desc *desc = fpga_get_desc(devnum); if (desc) { debug("%s: Device Descriptor @ 0x%p\n", @@ -374,7 +374,7 @@ int fpga_info(int devnum) #if CONFIG_IS_ENABLED(FPGA_LOAD_SECURE) int fpga_compatible2flag(int devnum, const char *compatible) { - const fpga_desc * const desc = fpga_get_desc(devnum); + const fpga_desc *desc = fpga_get_desc(devnum); if (!desc) return 0; diff --git a/drivers/fpga/intel_sdm_mb.c b/drivers/fpga/intel_sdm_mb.c index 5a65bd98779..5fe4dbdfd32 100644 --- a/drivers/fpga/intel_sdm_mb.c +++ b/drivers/fpga/intel_sdm_mb.c @@ -22,18 +22,630 @@ #define BITSTREAM_CHUNK_SIZE 0xFFFF0 #define RECONFIG_STATUS_POLL_RETRY_MAX 100 +static const struct mbox_cfgstat_major_err { + int err_no; + const char *error_name; +} mbox_cfgstat_major_err[] = { + {MBOX_CFGSTATE_MAJOR_ERR_WRONG_BL31_VER, + "Please check ATF BL31 version, require v2.11 above to print more error status."}, + {MBOX_CFGSTATE_MAJOR_ERR_STATE_CONFIG, + "Mailbox in configuration state."}, + {MBOX_CFGSTATE_MAJOR_ERR_BITSTREAM_ERR, + "Bitstream Invalid."}, + {MBOX_CFGSTATE_MAJOR_ERR_EXT_HW_ACCESS_FAIL, + "External HW access failure."}, + {MBOX_CFGSTATE_MAJOR_ERR_BITSTREAM_CORRUPTION, + "Bitstream valid but corrupted. Bitstream corruption error when reading the bitstream from the source." + }, + {MBOX_CFGSTATE_MAJOR_ERR_INTERNAL_ERR, + "Bitstream element not understood. Internal error."}, + {MBOX_CFGSTATE_MAJOR_ERR_DEVICE_ERR, + "Unable to communicate on internal configuration network. Device operation error."}, + {MBOX_CFGSTATE_MAJOR_ERR_HPS_WDT, + "HPS Watchdog Timer. HPS watchdog timeout failure."}, + {MBOX_CFGSTATE_MAJOR_ERR_INTERNAL_UNKNOWN_ERR, + "Other unknown error occurred"}, + {MBOX_CFGSTATE_MAJOR_ERR_SYSTEM_INIT_ERR, + "Error before main CMF start. System initialization failure."}, + {MBOX_CFGSTATE_MAJOR_ERR_DECRYPTION_ERR, + "Decryption Error."}, + {MBOX_CFGSTATE_MAJOR_ERR_VERIFY_IMAGE_ERR, + "Verify image error."}, + {MBOX_CFGSTATE_MAJOR_ERR_UNK, + "Unknown error number at major field!"} +}; + +#define MBOX_CFGSTAT_MAJOR_ERR_MAX ARRAY_SIZE(mbox_cfgstat_major_err) + +static const struct mbox_cfgstat_minor_err { + int err_no; + const char *error_name; +} mbox_cfgstat_minor_err[] = { + {MBOX_CFGSTATE_MINOR_ERR_BASIC_ERR, + "Catchall Error."}, + {MBOX_CFGSTATE_MINOR_ERR_CNT_RESP_ERR, + "Detected an error during configuration. Detected an error during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_QSPI_DEV_ERR, + "QSPI Device related error. Detected QSPI device related error during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_INV, + "Bitstream section main descriptor invalid. Detected an error during configuration due to a corrupted bitstream." + }, + {MBOX_CFGSTATE_MINOR_ERR_BS_INCOMPATIBLE, + "Bistream not compatible with device. Detected an error during configuration due to incompatible bitstream with the device." + }, + {MBOX_CFGSTATE_MINOR_ERR_BS_INV_SHA, + "Bitstream invalid SHA setting. Detected an error during configuration due to a corrupted bitstream." + }, + {MBOX_CFGSTATE_MINOR_ERR_ROUTE_FAIL, + "Bitstream processing route failed. Detected an error during configuration due to a corrupted bitstream." + }, + {MBOX_CFGSTATE_MINOR_ERR_GO_BIT_ALREADY_SET, + "Failed DMA during bitstream processing. Detected an error during configuration due to a corrupted bitstream." + }, + {MBOX_CFGSTATE_MINOR_ERR_CPU_BLK_FAIL, + "Failed DMA during bitstream processing. Detected an error during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_ACT_SKIP_FAIL, + "Skip action failed. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_ACT_MCAST_FAIL, + "Multicast Action Failed. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_ACT_IND_SZ_FAIL, + "Index Size Action Failed. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_ACT_IF_FAIL, + "If Action Failed. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_ACT_PIN_FAIL, + "Pin Action Failed. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_ACT_FUSEFLTR_FAIL, + "Fuse Filter Action Failed. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_ACT_GENERIC_FAIL, + "Other Action Failed. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_DATA_STARVE_ERR, + "Datapath starved. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_CNT_RAM_INIT_FAIL, + "CNT/SSM RAM Initialization Failed. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_ACT_SETUP_S4, + "S4 Setup Failed. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_WIPE_DATA_STARVE, + "Datapath starved during wipe. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_FUSE_RD_FAIL, + "eFUSE Read Failure. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_AUTH_FAIL, + "Authentication Failure. Detected a bitstream authentication error during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_SHA_FAIL, + "Bitstream Section Main Descriptor Hash Check Failed. Detected an error during configuration due to a corrupted bitstream." + }, + {MBOX_CFGSTATE_MINOR_ERR_SKIP_DATA_RAM_FAIL, + "Skip Action Failed. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_ACT_FIXED_FAIL, + "Fixed Action Failed. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_ACT_MCAST_FLTR_FAIL, + "Multicast Filter Action Failed. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_ACT_SECTOR_FAIL, + "Sector Group Action Failed. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_ACT_HASH_FAIL, + "Hash Action Failed. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_ACT_DECOMP_SETUP_FAIL, + "Decompression Setup Action Failed. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_INTERNAL_OS_ERR, + "RTOS Error. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_WIPE_FAIL, + "Wipe Bitstream Failed. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_CNOC_ERR, + "Internal Configuration Network Failure. Detected an error during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_PMF_RESUME_FAIL, + "Power Management Firmware Failed Resume. Detected an error during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_PMF_RUN_FAIL, + "Power Management Firmware Failed Run. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_PMF_PAUSE_FAIL, + "Power Management Firmware Failed Pause. Detected an error during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_RET_INT_ASSERT_FAIL, + "Internal Configuration Network Return Interrupt Failure. Detected an error during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_STATE_MACHINE_ERR, + "Configuration State Machine Error. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_CMF_TRANSITION_FAIL, + "Error during CMF load/reload. Detected a firmware transition error during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_SHA_SETUP_FAIL, + "Error setting up SHA engine. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_WR_DMA_TIMEOUT, + "Write DMA timed out. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_MEM_ALLOC_FAIL, + "Out of Memory. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_SYNC_RD_FAIL, + "Sync Block Read Fail. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_CHK_CFG_REQ_FAIL, + "Configuration Status Check Failed. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_HPS_CFG_REQ_FAIL, + "HPS Configuration Request Failed. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_CFG_HANDLE_ERR, + "Driver Handle Error. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_INV_ACTION_ITEM, + "Bistream contains invalid action. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_SKIP_DATA_PREBUF_ERR, + "Prebuffer Error during Skip Action. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_MBOX_TIMEOUT, + "Mailbox Processing Timeout. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_AVST_FIFO_OVERFLOW_ERR, + "AVST FIFO Overflow. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_RD_DMA_TIMEOUT, + "Read DMA timed out. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_PMF_INIT_ERR, + "Power Management Firmware Initialization Error. Detected a PMBUS error during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_PMF_SHUTDOWN_ERR, + "Power Management Firmware Shutdown Error. Detected a PMBUS error during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_BITSTREAM_INTERRUPTED, + "Bitstream processing was interrupted by another event. Detected an error during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_FPGA_MBOX_WIPE_TIMEOUT, + "Mailbox Wipe Timeout. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_TYPE_INV, + "Bitstream Section Main Descriptor Type is Invalid. Detected an error during configuration due to a corrupted bitstream." + }, + {MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_VERSION_INV, + "Bitstream Section Main Descriptor Version is Invalid. Detected an error during configuration due to a corrupted bitstream." + }, + {MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_DEVICE_TYPE_INV, + "Bitstream Section Main Descriptor Device is Invalid. Detected an error during configuration due to a corrupted bitstream." + }, + {MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_DESIGN_HASH_ERR, + "Bitstream Section Main Descriptor Hash Mismatch. Detected an error during configuration due to a corrupted bitstream." + }, + {MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_EXT_REF_CLK_ERR, + "Bitstream Section Main Descriptor External Clock Setting Invalid. Detected an error during configuration due to a corrupted bitstream." + }, + {MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_PWR_TBL_INV, + "Bitstream Section Main Descriptor Power Table is invalid. Detected an error during configuration due to a corrupted bitstream." + }, + {MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_PIN_TBL_OFST_ERR, + "Bitstream Section Main Descriptor Offset to Pin Table is Invalid. Detected an error during configuration due to a corrupted bitstream." + }, + {MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_PIN_TBL_INV, + "Bitstream Section Main Descriptor Pin Table is Invalid. Detected an error during configuration due to a corrupted bitstream." + }, + {MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_NO_PIN_TBL, + "Bitstream Section Main Descriptor missing pin table. Detected an error during configuration due to a corrupted bitstream." + }, + {MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_CFG_CLK_PLL_FAILED, + "Bitstream Section Main Descriptor PLL setting failure. Detected an error during configuration due to a corrupted bitstream." + }, + {MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_AS_CLK_FAILED, + "Bitstream Section Main Descriptor QSPI Clock Setting Failure. Detected an error during configuration due to a corrupted bitstream." + }, + {MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_POF_ID_FAILED, + "Bitstream Section Main Descriptor POF ID not valid. Detected an incompatible PR bitstream during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_PW_TBL_OFST_ERR, + "code not used."}, + {MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_PP_TBL_OFST_ERR, + "code not used."}, + {MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_PP_TBL_INV, + "code not used."}, + {MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_SP_TBL_OFST_ERR, + "code not used."}, + {MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_SP_TBL_INV, + "code not used."}, + {MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_SU_TBL_OFST_ERR, + "code not used."}, + {MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_SU_TBL_INV, + "code not used."}, + {MBOX_CFGSTATE_MINOR_ERR_MBOX_TASK_CRYPTO_SRC_CLR_ERR, + "Mailbox Source Failed to Clear. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_MBOX_TASK_EVENT_GROUP_POST_ERR, + "Mailbox Event Post Error. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_TRNG_TEST_FAIL, + "True Random Number Generator Failed Test. Detected an error during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_MBOX_TASK_ANTI_DOS_TMR_INIT_ERR, + "Mailbox Anti-DOS Timer failed initialization. Detected an error during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_OS_STK_CHK_ERR, + "RTOS Stack Check Error. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_MBOX_TASK_INIT, + "Mailbox Task failed to initialize. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_COMPAT_ID_MATCH_ERR, + "Bitstream Section Main Descriptor Compatibility ID mismatch. Detected a bitstream error during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_COMPAT_ID_INV, + "Bitstream Section Main Descriptor Compatibility ID not Valid. Detected an error during configuration due to a corrupted bitstream." + }, + {MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_AES_ECRYPT_CHK_FAIL, + "Bitstream Section Main Descriptor AES Test Failed. Detected an error during configuration due to a corrupted bitstream." + }, + {MBOX_CFGSTATE_MINOR_ERR_ACT_KEY_FAIL, + "Key Action Failure. Detected a bitstream decryption error during configuration due to a corrupted bitstream." + }, + {MBOX_CFGSTATE_MINOR_ERR_ACT_KEY_CHALLENGE_FAIL, + "Key Challenge Failure. Detected a bitstream decryption error during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_MBOX_TASK_MSGQ_DEQUEUE_FAIL, + "Mailbox Task Queue failed to dequeue. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_SECT_COMPAT_CHK_ERR, + "Bitstream Section Compatibility Check Error. Detected an error during configuration due to a corrupted bitstream." + }, + {MBOX_CFGSTATE_MINOR_ERR_SECT_COMPAT_UPDATE_ERR, + "Bitstream Section Compatibility Update Error. Detected an error during configuration due to a corrupted bitstream." + }, + {MBOX_CFGSTATE_MINOR_ERR_SECT_SEC_CHK_FAILED, + "Bitstream Section Security Check Failed. Detected an error during configuration due to a corrupted bitstream." + }, + {MBOX_CFGSTATE_MINOR_ERR_CNT_RAM_ECC_ERR_UNRECOVERABLE, + "Unrecoverable Error in CNT/SSM RAM. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_MBOX_REFORMAT_INPUT_ERR, + "Mailbox Input Processing Error. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_MBOX_REFORMAT_OUTPUT_ERR, + "Mailbox Output Processing Error. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_MBOX_WLBL_ERR, + "(Provision only) Provision CMF's allowed mailbox cmd group is invalid. Detected an error during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_MBOX_HOOK_CB_ERR, + "Mailbox Callback Error. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_CMF_RLD_DECOMP_LOAD_ERR, + "CMF Reload failed to load Decompression Code. Detected an error during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_CMF_RLD_DECOMP_RUN_ERR, + "CMF Reload failed to run Decompression Code. Detected an error during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_CNT_PERIPH_ECC_ERR_UNRECOVERABLE, + "Unrecoverable Error in CNT/SSM Peripheral. Detected an error during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_MAIN_SECT_ADDR_ERR, + "(Provision only) invalid Flash image CMF header's main section address. Detected an error during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_SCRAMBLE_RATIO_CHK_FAIL, + "Bitstream Section Main Descriptor Invalid Scrambler Ratio. Detected an error during configuration due to a corrupted bitstream." + }, + {MBOX_CFGSTATE_MINOR_ERR_TAMPER_EVENT_TRIGGERED, + "Tamper Detected. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_ANTI_TAMPER_TBL_INV, + "Bitstream Section Main Descriptor Anti Tamper Table Invalid. Detected an error during configuration due to a corrupted bitstream." + }, + {MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_EXT_CLCK_MODE_DISALLOWED, + "External Clock info presented, but external clock not allowed on device. Detected an error during configuration due to a corrupted bitstream." + }, + {MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_SEC_OPTIONS_INIT_FAIL, + "Bitstream Section Main Descriptor Security Option Initialization Failed. Detected an error during configuration due to a corrupted bitstream." + }, + {MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_EN_USR_CAN_FUSE_INV, + "User cancellation fuse table initialization failed. Detected an error during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_AS_DEVICE_NO_SGX_ERR, + "Not yet turned on for Rearch code. Detected an incompatible bitstream during configuration. You cannot use the bitstream from an advanced security-enabled devices on a non-advanced security-enabled device." + }, + {MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_POF_ID_LIMIT_EXCEED_ERR, + "Not yet turned on for Rearch code. Detected an invalid bitstream during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_PROVISION_CMF_INV_STATE, + "(Provision only) Internal state machine wrong state. Detected an error during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_PROVISION_CMF_FATAL_ERR, + "(Provision only) Fatal error detected with Provision CMF. Detected an error during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_PROVISION_CMF_SM_EXIT_FAIL, + "(Provision only) State machine's state function exit error. Detected an error during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_PROVISION_CMF_SM_ENTRY_FAIL, + "(Provision only) State machine's state function entry error. Detected an error during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_ACTION_DATA_UNSUPPORTED_CTX, + "Not yet turned on for Rearch code. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_CMF_EXCEPTION, + "Processor Exception. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_ECC_INIT_FAIL, + "SDM Peripheral ECC Initialization Failure. Detected an error during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_DEFAULT_UNREGISTERED_ISR, + "Unregistered Interrupt Occurred. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_GENERAL_TIMEOUT, + "Execution Timeout. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_ACT_OPERATION_CLK_FAIL, + "Clock Operation Action Failed. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_ACT_VERIFY_HASH_FAIL, + "Verify Hash Action Failed. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_CFG_STATE_UPDATE_ERR, + "Error updating configuration state. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_READ_DDR_HASH_FAIL, + "Error while reading HPS DDR hash from main descriptor."}, + {MBOX_CFGSTATE_MINOR_ERR_CVP_FLOW_ERR, + "Error during CvP Phase 2 data flow handling or handshake."}, + {MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_KEYED_HASH_ERR, + "Encountered keyed hash error while processing a main descriptor."}, + {MBOX_CFGSTATE_MINOR_ERR_CMF_DESC_BAD_JTAG_ID, + "New CMF Descriptor JTAG ID mismatch with original configured CMF JTAG ID." + }, + {MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_PMF_NOT_SUPPORTED, + "The IO Descriptor contains a power table but the current CMF does not support PMF. Bitstream incompatile with Firmware." + }, + { + MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_ANTI_TAMPER_NOT_SUPPORTED, + "The IO Descriptor contains anti-tamper setting but the current CMF does not support anti-tamper. Bitstream incompatile with Firmware." + }, + {MBOX_CFGSTATE_MINOR_ERR_ACT_RECOVERY_FAIL, + "Recovery Action Failed. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_COLD_RESET_CMF_CORRUPTED, + "Error when process CMF section after cold reset. Detected CMF section error or incompatible upon cold reset using JTAG or AVST." + }, + {MBOX_CFGSTATE_MINOR_ERR_COLD_RESET_IO_HPS_CORRUPTED, + "Error when process IO/HPIO/HPS section after cold reset and hps wipe. Detected an error when try to bring up HPS again after cold reset." + }, + {MBOX_CFGSTATE_MINOR_ERR_COLD_RESET_FPGA_CORRUPTED, + "Error when process FPGA section header after cold reset. Detected an error in FPGA after successfully bring up HPS." + }, + {MBOX_CFGSTATE_MINOR_ERR_CRC_CHK_FAIL, + " CRC32 Check Fail. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_COMPAT_TBL_SFIXED_VALUE_INV, + "Error when process compatibility table in main section header. SFixed offset value in compatibility table is not valid." + }, + { + MBOX_CFGSTATE_MINOR_ERR_FEATURE_EN_FUSE_NOT_BLOWN, + "Error bitstream contains feature(s) that are only allowed when a feature fuse is blown on the device, and the device did not have the feature fuse blown. Bitstream requires feature enable fuse to be blown." + }, + {MBOX_CFGSTATE_MINOR_ERR_UIB_REFCLK_MISSING, + "UIB REFCLK missing. Device requires refclk to proceed configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_UIB_REFCLK_TIMEOUT, + "UIB REFCLK timeout. Device requires refclk to proceed configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_UIB_REFCLK_TIMEOUT_MISSING, + "UIB REFCLK missing and timeout. Device requires refclk to proceed configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_TRAMP_SYNC_BLCK_ERR, + "Sync block before SSBL processing failure. Detected a firmware error during reconfiguration." + }, + {MBOX_CFGSTATE_MINOR_ERR_TRAMP_SSBL_SHA_ERR, + "SSBL sha mismatch with bitstream. Detected a bitstream error during reconfiguration." + }, + {MBOX_CFGSTATE_MINOR_ERR_TRAMP_BLCK0_SHA_MISMATCH_ERR, + "Block0 Sha mismatch when trampoline reloads. Detected a bitstream error during reconfiguration." + }, + {MBOX_CFGSTATE_MINOR_ERR_TRAMP_BLCK0_AUTH_ERR, + "Trampoline authentication failure. Detected a bitstream error during reconfiguration." + }, + {MBOX_CFGSTATE_MINOR_ERR_TRAMP_TRAMP_LOAD_ERR, + "Trampoline Load compressed tramp failure. Detected a bitstream error during reconfiguration." + }, + {MBOX_CFGSTATE_MINOR_ERR_TRAMP_CMF_SIZE_ERR, + "Trampoline failed to retrieve SSBL or TSBL load information. Detected a bitstream error during reconfiguration." + }, + {MBOX_CFGSTATE_MINOR_ERR_TRAMP_TRANSITION_ERR, + "Trampoline failed to find a bootable DCMF. Detected an error during application images transition." + }, + {MBOX_CFGSTATE_MINOR_ERR_TRAMP_SYNC_ERR, + "Only used by RMA and ENG loader on legacy code. Detected an error during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_TRAMP_LOAD_CERT_ERR, + "Main CMF failed to authenticate a certificate bitstream. Detected a bitstream authentication error during reconfiguration." + }, + {MBOX_CFGSTATE_MINOR_ERR_TRAMP_LOAD_NOT_ALLOWED_ERR, + "Only used by Provision CMF, failure to initialize HW drivers. Detected an error during reconfiguration." + }, + {MBOX_CFGSTATE_MINOR_ERR_TRAMP_FUSE_ERR, + "Only used by RMA and Eng loader on Legacy code. Detected an error during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_TRAMP_INPUT_BUFFER_ERR, + "Provision CMF only, Trampoline inbuf HW access error. Detected a hardware error during reconfiguration." + }, + {MBOX_CFGSTATE_MINOR_ERR_TRAMP_CMF_TYPE_ERR, + "Trampoline/DCMF loading another CMF andfound CMF type mismatched with current one. Detected a bitstream error during reconfiguration." + }, + {MBOX_CFGSTATE_MINOR_ERR_TRAMP_QSPI_INDR_READ_START_ERR, + "Trampoline QSPI indirect read start error. Detected an error when accessing the QSPI flash." + }, + {MBOX_CFGSTATE_MINOR_ERR_PMF_I2C_COMM_ERR, + "Generic I2C error, ie Bad Address."}, + {MBOX_CFGSTATE_MINOR_ERR_PMF_TARGET_VOLTAGE_ERR, + "Failed to reach Target Voltage. Voltage Regulator unable to achieve the requested voltage." + }, + {MBOX_CFGSTATE_MINOR_ERR_PMF_HANDSHAKE_ERR, + "Slave Mode ALERT/VOUT_COMMAND handshake did not happen."}, + {MBOX_CFGSTATE_MINOR_ERR_PMF_ITD_OUT_OF_RANGE_ERR, + "Fuse values calculated voltage greater that cutoff max. ITD fuse is out of range." + }, + {MBOX_CFGSTATE_MINOR_ERR_PMF_PWR_TABLE_ERR, + "Error while reading or processing the Power Table. Internal Error while reading or decoding the Bitstream's Power Table." + }, + {MBOX_CFGSTATE_MINOR_ERR_PMF_EFUSE_DECODE_ERR, + "Error while reading or decoding the efuse values. Internal Error while reading or decoding the efuse values." + }, + {MBOX_CFGSTATE_MINOR_ERR_PMF_VCCL_PWRGOOD_ERR, + "Failed to verify the vccl power is good. Failed to validate the vccl power is valid on the board." + }, + {MBOX_CFGSTATE_MINOR_ERR_PMF_CLR_FAULTS_ERR, + "Error while sending CLEAR_FAULTS command. Error while sending CLEAR_FAULTS command," + }, + {MBOX_CFGSTATE_MINOR_ERR_PMF_VOUT_MODE_ERR, + "Error while sending VOUT_MODE command. Error while sending VOUT_MODE command,"}, + {MBOX_CFGSTATE_MINOR_ERR_PMF_PAGE_COMMAND_ERR, + "Error while sending PAGE_COMMAND command. Error while sending PAGE_COMMAND command," + }, + {MBOX_CFGSTATE_MINOR_ERR_PMF_VOUT_COMMAND_ERR, + "Error while sending VOUT_COMMAND command. Error while sending VOUT_COMMAND command," + }, + {MBOX_CFGSTATE_MINOR_ERR_PMF_READ_VOUT_ERR, + "Error while sending READ_VOUT command. Error while sending READ_VOUT command,"}, + {MBOX_CFGSTATE_MINOR_ERR_PMF_LTM4677_DEFAULT_ADC_CTRL_ERR, + "Error while sending the vendor specific LTM4677 MFR_ADC_CTRL command. Error while sending the vendor specific LTM4677 MFR_ADC_CTRL command," + }, + {MBOX_CFGSTATE_MINOR_ERR_PMF_FIRST_I2C_CMD_FAILED_ERR, + "First I2C messaged failed, ie Bad Address. The first I2C command has failed, no response from Voltage Regulator." + }, + {MBOX_CFGSTATE_MINOR_ERR_RSU_CMF_AUTH_ERR, + "Failed to authenticate CMF section. Detected a firmware authentication error during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_RSU_USER_AUTH_ERR, + "Failed to authenticate USER section. Detected a bitstream authentication error during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_RSU_CMF_DESC_SHA_MISMATCH, + "Block0 SHA mismatch when DCMF loads an APP image. Detected an error when loading the application image from flash." + }, + {MBOX_CFGSTATE_MINOR_ERR_RSU_POINTERS_NOT_FOUND_ERR, + "RSU CPB table parsing failed. Detected an error when parsing the RSU CPB block." + }, + {MBOX_CFGSTATE_MINOR_ERR_RSU_QSPI_FREQ_CHANGE, + "QSPI reference clock freq update failed. Detected an error during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_RSU_FACTORY_IMG_FAILED, + "RSU factory image failed to boot. Detected an error when loading the factory image. Check the factory image validity. If corrupted, regenerate and reprogram again the factory image in the flash. When authentication enabled," + }, + {MBOX_CFGSTATE_MINOR_ERR_RSU_CMF_TYPE_ERR, + "APP image CMF type mismatched with DCMF. Detected an error when loading the application image." + }, + { + MBOX_CFGSTATE_MINOR_ERR_RSU_UCMF_SIG_DESC_ERR, + "UCMF reports failure in parsing of an signature block, can be from new DCMF, new DCIO or new Factory. Detected an error during factory image update in flash." + }, + {MBOX_CFGSTATE_MINOR_ERR_RSU_UCMF_INTERNAL_AUTH_ERR, + "UCMF reports authentication failure of new DCMF, new DCIO or new Factory. Detected an error during DCMF update in flash." + }, + {MBOX_CFGSTATE_MINOR_ERR_RSU_UCMF_COPY_FAILED, + "UCMF reports QSPI flash write failure while upgrading DCMF, DCIO or Factory. Detected an error during DCMF update in flash." + }, + {MBOX_CFGSTATE_MINOR_ERR_RSU_UCMF_ERASE_FAILED, + "UCMF reports QSPI flash erase failure while upgrading DCMF, DCIO or Factory. Detected an error during DCMF update in flash." + }, + {MBOX_CFGSTATE_MINOR_ERR_RSU_RM_UCMF_FROM_CPB_FAILED, + "UCMF reports failure to remove UCMF address from RSU CPB table. Detected an error during RSU CPB table update in flash." + }, + {MBOX_CFGSTATE_MINOR_ERR_RSU_UCMF_COMBINED_APP_AUTH_ERR, + "UCMF reports authentication failure of new combined app image. Detected an error during combined app image update in flash." + }, + {MBOX_CFGSTATE_MINOR_ERR_RSU_UCMF_FLASH_ACCESS_ERR, + "UCMF failed to upgrade for more than max retry times. Detected an error during DCMF update in flash." + }, + {MBOX_CFGSTATE_MINOR_ERR_RSU_DCMF_DCIO_CORRUPTED, + "DCMF reports failure when parse dcio section, causing force factory boot. Detected an error when parsing dcio section." + }, + {MBOX_CFGSTATE_MINOR_ERR_RSU_DCMF_CPB0_CORRUPTED, + "DCMF reports failure when parse cpb0 and thus cpb1 is used. Detected an error in RSU CPB0 table." + }, + {MBOX_CFGSTATE_MINOR_ERR_RSU_DCMF_CPB1_CORRUPTED, + "DCMF reports failure when parse both cpb0 and cpb1, causing force factory boot. Detected an error in both RSU CPB0 and CPB1 table." + }, + {MBOX_CFGSTATE_MINOR_ERR_RSU_PROVISION_COMPLETE, + "Non-JTAG Provisioning Successful. Non-Jtag Provisioning was Successful DCMF will load next highest priority application image." + }, + {MBOX_CFGSTATE_MINOR_ERR_RSU_PROVISION_ERR, + "Non-JTAG Provisioning Failed. An error occurred while provisioning the device."}, + {MBOX_CFGSTATE_MINOR_ERR_SYSINIT_EFUSE_INIT_FAIL, + "Efuse cache generation failure. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_SYSINIT_SEC_PROT_ERR, + "Security lock and disable driver failure. Detected an error during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_SYSINIT_EFUSE_LCK_ERR, + "efuse lock operation failure."}, + {MBOX_CFGSTATE_MINOR_ERR_SYSINIT_SEC_BBRAM_CLEAN_ERR, + "BBRAM clean up failure."}, + {MBOX_CFGSTATE_MINOR_ERR_SYSINIT_ENG_LOAD_DIMK_ERR, + "DIMK failed to derive device identity."}, + {MBOX_CFGSTATE_MINOR_ERR_SYSINIT_SEC_UKV_CLEAN_ERR, + "Key Vault clean up failure."}, + {MBOX_CFGSTATE_MINOR_ERR_SYSINIT_EFUSE_ZERO_ERR, + "No security efuse allowed."}, + {MBOX_CFGSTATE_MINOR_ERR_SYSINIT_ENG_LOAD_ERR, + "efuse policy check failed."}, + {MBOX_CFGSTATE_MINOR_ERR_SYSINIT_PERST_INIT_FAIL, + "Peristent data initialization failure. Detected an error during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_SYSINIT_DIMK_INIT_FAIL, + "DIMK Initialization failure. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_SYSINIT_PERST_SECONDARY_INIT_FAIL, + "Handoff data include CMF main and signature blocks validation failure. Detected an error during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_SYSINIT_BR_INFO_INIT_FAIL, + "CMF Bootrom header validation failure."}, + {MBOX_CFGSTATE_MINOR_ERR_SYSINIT_CMF_DESC_FAIL, + "CMF Descriptor failure."}, + {MBOX_CFGSTATE_MINOR_ERR_SYSINIT_DRNG_INIT_FAIL, + "DRNG Initialization failed."}, + {MBOX_CFGSTATE_MINOR_ERR_UNK, + "Unknown error number at minor field!"} +}; + +#define MBOX_CFGSTAT_MINOR_ERR_MAX ARRAY_SIZE(mbox_cfgstat_minor_err) + +struct mbox_err_msg { + const char *major_err_str; + const char *minor_err_str; +}; + +static void mbox_cfgstat_to_str(int err, struct mbox_err_msg *err_msg) +{ + int i; + u32 major_err; + u32 minor_err; + + major_err = FIELD_GET(MBOX_CFG_STATUS_MAJOR_ERR_MSK, err); + + minor_err = FIELD_GET(MBOX_CFG_STATUS_MINOR_ERR_MSK, err); + + if (!err_msg) { + printf("Invalid argument\n"); + return; + } + + err_msg->major_err_str = ""; + err_msg->minor_err_str = ""; + + /* + * In the case of getting error number 0, meaning the + * ATF BL31 is not supporting the feature yet thus, + * the SMC call will return 0 at the second argument + * return the message to indicate that current BL31 + * is not yet supporting feature and need to check + * the BL31 version. + */ + if (err == 0) { + err_msg->major_err_str = mbox_cfgstat_major_err[err].error_name; + return; + } + + /* Initialize the major error string with unknown error */ + err_msg->major_err_str = mbox_cfgstat_major_err[0].error_name; + + for (i = 0; i < MBOX_CFGSTAT_MAJOR_ERR_MAX - 1; i++) { + if (mbox_cfgstat_major_err[i].err_no == major_err) { + err_msg->major_err_str = mbox_cfgstat_major_err[i].error_name; + break; + } + } + + /* Return configuration state if device still under config state */ + if (major_err == MBOX_CFGSTATE_MAJOR_ERR_STATE_CONFIG) + return; + + /* Initialize the minor error string with unknown error */ + err_msg->minor_err_str = mbox_cfgstat_minor_err[0].error_name; + + for (i = 0; i < MBOX_CFGSTAT_MINOR_ERR_MAX - 1; i++) { + if (mbox_cfgstat_minor_err[i].err_no == minor_err) { + err_msg->minor_err_str = mbox_cfgstat_minor_err[i].error_name; + break; + } + } +} + /* * Polling the FPGA configuration status. * Return 0 for success, non-zero for error. */ -static int reconfig_status_polling_resp(void) +static int reconfig_status_polling_resp(uint32_t *error_status) { int ret; + u64 res_buf[3]; unsigned long start = get_timer(0); while (1) { ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_ISDONE, NULL, 0, - NULL, 0); + res_buf, ARRAY_SIZE(res_buf)); + + if (error_status) + *error_status = (uint32_t)res_buf[0]; if (!ret) return 0; /* configuration success */ @@ -120,29 +732,44 @@ int intel_sdm_mb_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size) { int ret; u64 arg = 1; + u32 err_status = 0; + u64 res_buf[3]; + struct mbox_err_msg err_msg; debug("Invoking FPGA_CONFIG_START...\n"); ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_START, &arg, 1, NULL, 0); if (ret) { - puts("Failure in RECONFIG mailbox command!\n"); + puts("U-Boot SMC: Failure in RECONFIG mailbox command!\n"); return ret; } ret = send_bitstream(rbf_data, rbf_size); if (ret) { - puts("Error sending bitstream!\n"); + puts("\nU-Boot SMC: Error sending bitstream!\n"); + ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_ISDONE, NULL, 0, + res_buf, ARRAY_SIZE(res_buf)); + + err_status = res_buf[0]; + mbox_cfgstat_to_str(err_status, &err_msg); + printf("SDM: Config status: (0x%x)\nSDM Err: %s\n%s\n", err_status, + err_msg.major_err_str, err_msg.minor_err_str); + return ret; } /* Make sure we don't send MBOX_RECONFIG_STATUS too fast */ udelay(RECONFIG_STATUS_INTERVAL_DELAY_US); - debug("Polling with MBOX_RECONFIG_STATUS...\n"); - ret = reconfig_status_polling_resp(); + debug("U-Boot SMC: Polling with MBOX_RECONFIG_STATUS...\n"); + ret = reconfig_status_polling_resp(&err_status); if (ret) { - puts("FPGA reconfiguration failed!"); + printf("\nU-Boot SMC: FPGA reconfiguration failed!\n"); + mbox_cfgstat_to_str(err_status, &err_msg); + printf("SDM: Config status: (0x%x)\nSDM Err:%s\n%s\n", err_status, + err_msg.major_err_str, err_msg.minor_err_str); + return ret; } diff --git a/drivers/gpio/adp5585_gpio.c b/drivers/gpio/adp5585_gpio.c index ea0cb75459b..114583b3c3b 100644 --- a/drivers/gpio/adp5585_gpio.c +++ b/drivers/gpio/adp5585_gpio.c @@ -224,7 +224,7 @@ static int adp5585_probe(struct udevice *dev) } static const struct udevice_id adp5585_ids[] = { - { .compatible = "adp5585" }, + { .compatible = "adi,adp5585" }, { } }; diff --git a/drivers/led/led-uclass.c b/drivers/led/led-uclass.c index 760750568c0..27ef890ed0a 100644 --- a/drivers/led/led-uclass.c +++ b/drivers/led/led-uclass.c @@ -13,6 +13,25 @@ #include <dm/lists.h> #include <dm/root.h> #include <dm/uclass-internal.h> +#include <dt-bindings/leds/common.h> + +static const char * const led_colors[LED_COLOR_ID_MAX] = { + [LED_COLOR_ID_WHITE] = "white", + [LED_COLOR_ID_RED] = "red", + [LED_COLOR_ID_GREEN] = "green", + [LED_COLOR_ID_BLUE] = "blue", + [LED_COLOR_ID_AMBER] = "amber", + [LED_COLOR_ID_VIOLET] = "violet", + [LED_COLOR_ID_YELLOW] = "yellow", + [LED_COLOR_ID_IR] = "ir", + [LED_COLOR_ID_MULTI] = "multicolor", + [LED_COLOR_ID_RGB] = "rgb", + [LED_COLOR_ID_PURPLE] = "purple", + [LED_COLOR_ID_ORANGE] = "orange", + [LED_COLOR_ID_PINK] = "pink", + [LED_COLOR_ID_CYAN] = "cyan", + [LED_COLOR_ID_LIME] = "lime", +}; int led_bind_generic(struct udevice *parent, const char *driver_name) { @@ -232,11 +251,54 @@ int led_activity_blink(void) #endif #endif -static const char *led_get_label(ofnode node) +static const char *led_get_function_name(struct udevice *dev) +{ + struct led_uc_plat *uc_plat; + const char *func; + u32 color; + u32 enumerator; + int ret; + int cp; + + if (!dev) + return NULL; + + uc_plat = dev_get_uclass_plat(dev); + if (!uc_plat) + return NULL; + + if (uc_plat->label) + return uc_plat->label; + + /* Now try to detect function label name */ + func = dev_read_string(dev, "function"); + cp = dev_read_u32(dev, "color", &color); + if (cp == 0 || func) { + ret = dev_read_u32(dev, "function-enumerator", &enumerator); + if (!ret) { + snprintf(uc_plat->name, LED_MAX_NAME_SIZE, + "%s:%s-%d", + cp ? "" : led_colors[color], + func ? func : "", enumerator); + } else { + snprintf(uc_plat->name, LED_MAX_NAME_SIZE, + "%s:%s", + cp ? "" : led_colors[color], + func ? func : ""); + } + uc_plat->label = uc_plat->name; + } + + return uc_plat->label; +} + +static const char *led_get_label(struct udevice *dev, ofnode node) { const char *label; label = ofnode_read_string(node, "label"); + if (!label) + label = led_get_function_name(dev); if (!label && !ofnode_read_string(node, "compatible")) label = ofnode_get_name(node); @@ -249,7 +311,7 @@ static int led_post_bind(struct udevice *dev) const char *default_state; if (!uc_plat->label) - uc_plat->label = led_get_label(dev_ofnode(dev)); + uc_plat->label = led_get_label(dev, dev_ofnode(dev)); uc_plat->default_state = LEDST_COUNT; @@ -314,14 +376,14 @@ static int led_init(struct uclass *uc) #ifdef CONFIG_LED_BOOT ret = ofnode_options_get_by_phandle("boot-led", &led_node); if (!ret) - priv->boot_led_label = led_get_label(led_node); + priv->boot_led_label = led_get_label(NULL, led_node); priv->boot_led_period = ofnode_options_read_int("boot-led-period-ms", 250); #endif #ifdef CONFIG_LED_ACTIVITY ret = ofnode_options_get_by_phandle("activity-led", &led_node); if (!ret) - priv->activity_led_label = led_get_label(led_node); + priv->activity_led_label = led_get_label(NULL, led_node); priv->activity_led_period = ofnode_options_read_int("activity-led-period-ms", 250); #endif diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 6009d55f400..da84b35e804 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -568,7 +568,7 @@ config QFW_MMIO config QFW_SMBIOS bool default y - depends on QFW && SMBIOS && !SANDBOX + depends on QFW && SMBIOS && !SANDBOX && !SYSINFO_SMBIOS help Hidden option to read SMBIOS tables from QEMU. diff --git a/drivers/misc/qfw_acpi.c b/drivers/misc/qfw_acpi.c index 7ffed1e8c02..0d0cf764689 100644 --- a/drivers/misc/qfw_acpi.c +++ b/drivers/misc/qfw_acpi.c @@ -7,6 +7,7 @@ #define LOG_CATEGORY UCLASS_QFW #include <acpi/acpi_table.h> +#include <bloblist.h> #include <errno.h> #include <malloc.h> #include <mapmem.h> @@ -160,6 +161,15 @@ ulong write_acpi_tables(ulong addr) struct bios_linker_entry *entry; uint32_t size; struct udevice *dev; + struct acpi_ctx *ctx; + + ctx = malloc(sizeof(*ctx)); + if (!ctx) { + printf("error: out of memory for acpi ctx\n"); + return addr; + } + + acpi_setup_ctx(ctx, addr); ret = qfw_get_dev(&dev); if (ret) { @@ -257,6 +267,29 @@ ulong acpi_get_rsdp_addr(void) return file->addr; } +void acpi_write_rsdp(struct acpi_rsdp *rsdp, struct acpi_rsdt *rsdt, + struct acpi_xsdt *xsdt) +{ + memset(rsdp, 0, sizeof(struct acpi_rsdp)); + + memcpy(rsdp->signature, RSDP_SIG, 8); + memcpy(rsdp->oem_id, OEM_ID, 6); + + if (rsdt) + rsdp->rsdt_address = nomap_to_sysmem(rsdt); + + if (xsdt) + rsdp->xsdt_address = nomap_to_sysmem(xsdt); + + rsdp->length = sizeof(struct acpi_rsdp); + rsdp->revision = ACPI_RSDP_REV_ACPI_2_0; + + /* Calculate checksums */ + rsdp->checksum = table_compute_checksum(rsdp, 20); + rsdp->ext_checksum = table_compute_checksum(rsdp, + sizeof(struct acpi_rsdp)); +} + #ifndef CONFIG_X86 static int evt_write_acpi_tables(void) { @@ -264,9 +297,9 @@ static int evt_write_acpi_tables(void) void *ptr; /* Reserve 64K for ACPI tables, aligned to a 4K boundary */ - ptr = memalign(SZ_4K, SZ_64K); + ptr = bloblist_add(BLOBLISTT_ACPI_TABLES, SZ_64K, 12); if (!ptr) - return -ENOMEM; + return -ENOBUFS; addr = map_to_sysmem(ptr); /* Generate ACPI tables */ diff --git a/drivers/misc/qfw_smbios.c b/drivers/misc/qfw_smbios.c index c3e8c310d00..93c4a80286b 100644 --- a/drivers/misc/qfw_smbios.c +++ b/drivers/misc/qfw_smbios.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY UCLASS_QFW +#include <bloblist.h> #include <efi_loader.h> #include <errno.h> #include <log.h> @@ -15,6 +16,7 @@ #include <tables_csum.h> #include <linux/sizes.h> #include <asm/global_data.h> +#include <linux/err.h> DECLARE_GLOBAL_DATA_PTR; @@ -105,11 +107,10 @@ out: /** * qfw_write_smbios_tables() - copy SMBIOS tables from QEMU * - * @addr: target buffer - * @size: size of target buffer + * @addr: address of target buffer * Return: 0 for success, -ve on error */ -static int qfw_write_smbios_tables(u8 *addr, uint32_t size) +ulong write_smbios_table(ulong addr) { int ret; struct udevice *dev; @@ -143,16 +144,13 @@ static int qfw_write_smbios_tables(u8 *addr, uint32_t size) table = qfw_load_smbios_table(dev, &table_size, "etc/smbios/smbios-tables"); - if (table_size + sizeof(struct smbios3_entry) > size) { - free(table); - return -ENOMEM; - } - memcpy(addr, table, table_size); + memcpy((void *)addr, table, table_size); free(table); - return 0; + return addr + table_size; } +#ifndef CONFIG_X86 /** * qfw_evt_write_smbios_tables() - event handler for copying QEMU SMBIOS tables * @@ -160,9 +158,9 @@ static int qfw_write_smbios_tables(u8 *addr, uint32_t size) */ static int qfw_evt_write_smbios_tables(void) { - phys_addr_t addr; + ulong addr, end; void *ptr; - int ret; + /* * TODO: * This size is currently hard coded in lib/efi_loader/efi_smbios.c. @@ -170,22 +168,21 @@ static int qfw_evt_write_smbios_tables(void) */ uint32_t size = SZ_4K; - /* Reserve 64K for SMBIOS tables, aligned to a 4K boundary */ - ptr = memalign(SZ_4K, size); - if (!ptr) { - log_err("Out of memory\n"); - return -ENOMEM; - } + log_debug("qfw_evt_write_smbios_tables bloblist\n"); + /* Reserve 4K for SMBIOS tables, aligned to a 4K boundary */ + ptr = bloblist_add(BLOBLISTT_SMBIOS_TABLES, size, 12); + if (!ptr) + return log_msg_ret("bloblist", -ENOBUFS); + addr = map_to_sysmem(ptr); /* Generate SMBIOS tables */ - ret = qfw_write_smbios_tables(ptr, size); - if (ret) { - if (CONFIG_IS_ENABLED(GENERATE_SMBIOS_TABLE)) { - log_info("Falling back to U-Boot generated SMBIOS tables\n"); - write_smbios_table(addr); - } + end = write_smbios_table(addr); + if (IS_ERR_VALUE(end)) { + log_warning("SMBIOS: Failed to write (err=%dE)\n", (int)end); } else { + if (end - addr > size) + return -ENOMEM; log_debug("SMBIOS tables copied from QEMU\n"); } @@ -193,5 +190,5 @@ static int qfw_evt_write_smbios_tables(void) return 0; } - EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, qfw_evt_write_smbios_tables); +#endif /* !X86 */ diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index f4fdf15242c..4827834b4aa 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -3,7 +3,8 @@ menu "MMC Host controller Support" config MMC bool "MMC/SD/SDIO card support" default ARM || PPC || SANDBOX - select DM_MMC if DM + select BLK + select DM_MMC help This selects MultiMediaCard, Secure Digital and Secure Digital I/O support. @@ -39,14 +40,14 @@ config MMC_BROKEN_CD If card detection feature is broken, just poll to detect. config DM_MMC - bool "Enable MMC controllers using Driver Model" + bool depends on DM help - This enables the MultiMediaCard (MMC) uclass which supports MMC and - Secure Digital I/O (SDIO) cards. Both removable (SD, micro-SD, etc.) - and non-removable (e.g. eMMC chip) devices are supported. These - appear as block devices in U-Boot and can support filesystems such - as EXT4 and FAT. + This enables the MultiMediaCard (MMC) driver model uclass which + supports MMC and Secure Digital I/O (SDIO) cards. Both removable (SD, + micro-SD, etc.) and non-removable (e.g. eMMC chip) devices are + supported. These appear as block devices in U-Boot and can support + filesystems such as EXT4 and FAT. config SPL_DM_MMC bool "Enable MMC controllers using Driver Model in SPL" @@ -79,7 +80,7 @@ config MMC_SDHCI_ADMA_HELPERS config MMC_SPI bool "Support for SPI-based MMC controller" - depends on DM_MMC && DM_SPI + depends on DM_SPI help This selects SPI-based MMC controllers. If you have an MMC controller on a SPI bus, say Y here. @@ -97,7 +98,6 @@ config MMC_SPI_CRC_ON config ARM_PL180_MMCI bool "ARM AMBA Multimedia Card Interface and compatible support" - depends on DM_MMC help This selects the ARM(R) AMBA(R) PrimeCell Multimedia Card Interface (PL180, PL181 and compatible) support. @@ -258,7 +258,6 @@ config MMC_DW config MMC_DW_CORTINA bool "Cortina specific extensions for Synopsys DW Memory Card Interface" - depends on DM_MMC depends on MMC_DW help This selects support for Cortina SoC specific extensions to the @@ -285,7 +284,7 @@ config MMC_DW_K3 config MMC_DW_ROCKCHIP bool "Rockchip SD/MMC controller support" - depends on DM_MMC && OF_CONTROL + depends on OF_CONTROL depends on MMC_DW help This enables support for the Rockchip SD/MMM controller, which is @@ -306,7 +305,6 @@ config MMC_DW_SOCFPGA config MMC_DW_SNPS bool "Extensions for DW Memory Card Interface used in Synopsys ARC devboards" depends on MMC_DW - depends on DM_MMC depends on OF_CONTROL depends on CLK help @@ -317,13 +315,12 @@ config NEXELL_DWMMC bool "Nexell SD/MMC controller support" depends on ARCH_NEXELL depends on MMC_DW - depends on DM_MMC depends on PINCTRL_NEXELL default y config MMC_MESON_GX bool "Meson GX EMMC controller support" - depends on DM_MMC && ARCH_MESON + depends on ARCH_MESON help Support for EMMC host controller on Meson GX ARM SoCs platform (S905) @@ -338,7 +335,7 @@ config MMC_MXC config MMC_OWL bool "Actions OWL Multimedia Card Interface support" - depends on ARCH_OWL && DM_MMC && BLK + depends on ARCH_OWL help This selects the OWL SD/MMC host controller found on board based on Actions S700/S900 SoC. @@ -366,7 +363,6 @@ config MMC_PCI config MMC_OCTEONTX bool "Marvell Octeon Multimedia Card Interface support" depends on (ARCH_OCTEON || ARCH_OCTEONTX || ARCH_OCTEONTX2) - depends on DM_MMC select MMC_SUPPORTS_TUNING if ARCH_OCTEONTX2 help This selects the Octeon Multimedia card Interface. @@ -377,7 +373,7 @@ config MMC_OCTEONTX config MVEBU_MMC bool "Kirkwood MMC controller support" - depends on DM_MMC && ARCH_KIRKWOOD + depends on ARCH_KIRKWOOD help Support for MMC host controller on Kirkwood SoCs. If you are on a Kirkwood architecture, say Y here. @@ -386,8 +382,7 @@ config MVEBU_MMC config MMC_OMAP_HS bool "TI OMAP High Speed Multimedia Card Interface support" - select DM_REGULATOR_PBIAS if DM_MMC && DM_REGULATOR - select DM_REGULATOR_PBIAS if DM_MMC && DM_REGULATOR + select DM_REGULATOR_PBIAS if DM_REGULATOR help This selects the TI OMAP High Speed Multimedia card Interface. If you have an omap2plus board with a Multimedia Card slot, @@ -430,7 +425,6 @@ config SH_MMCIF config MMC_UNIPHIER bool "UniPhier SD/MMC Host Controller support" depends on ARCH_UNIPHIER - depends on DM_MMC depends on OF_CONTROL help This selects support for the Matsushita SD/MMC Host Controller on @@ -439,7 +433,6 @@ config MMC_UNIPHIER config RENESAS_SDHI bool "Renesas R-Car SD/MMC Host Controller support" depends on ARCH_RENESAS - depends on DM_MMC depends on OF_CONTROL select BOUNCE_BUFFER help @@ -449,7 +442,6 @@ config RENESAS_SDHI config MMC_BCM2835 bool "BCM2835 family custom SD/MMC Host Controller support" depends on ARCH_BCM283X - depends on DM_MMC depends on OF_CONTROL default y help @@ -469,7 +461,7 @@ config JZ47XX_MMC config MMC_SANDBOX bool "Sandbox MMC support" depends on SANDBOX - depends on DM_MMC && OF_CONTROL + depends on OF_CONTROL help This select a dummy sandbox MMC driver. At present this does nothing other than allow sandbox to be build with MMC support. This @@ -559,7 +551,6 @@ config FIXED_SDHCI_ALIGNED_BUFFER config MMC_SDHCI_ASPEED bool "Aspeed SDHCI controller" depends on ARCH_ASPEED - depends on DM_MMC depends on MMC_SDHCI select MISC help @@ -571,7 +562,7 @@ config MMC_SDHCI_ASPEED config MMC_SDHCI_ATMEL bool "Atmel SDHCI controller support" depends on ARCH_AT91 - depends on DM_MMC && ARCH_AT91 + depends on ARCH_AT91 depends on MMC_SDHCI help This enables support for the Atmel SDHCI controller, which supports @@ -606,7 +597,6 @@ config MMC_SDHCI_BCMSTB config MMC_SDHCI_CADENCE bool "SDHCI support for the Cadence SD/SDIO/eMMC controller" - depends on DM_MMC depends on MMC_SDHCI depends on OF_CONTROL help @@ -618,7 +608,6 @@ config MMC_SDHCI_CADENCE config MMC_SDHCI_CV1800B bool "SDHCI support for the CV1800B SD/SDIO/eMMC controller" - depends on DM_MMC depends on MMC_SDHCI depends on OF_CONTROL help @@ -633,7 +622,7 @@ config MMC_SDHCI_AM654 bool "SDHCI Controller on TI's Am654 devices" depends on ARCH_K3 depends on MMC_SDHCI - depends on DM_MMC && OF_CONTROL && BLK + depends on OF_CONTROL depends on REGMAP select MMC_SDHCI_IO_ACCESSORS help @@ -653,7 +642,6 @@ config MMC_SDHCI_IPROC config MMC_SDHCI_F_SDH30 bool "SDHCI support for Fujitsu Semiconductor/Socionext F_SDH30" - depends on DM_MMC depends on MMC_SDHCI help This selects the Secure Digital Host Controller Interface (SDHCI) @@ -673,7 +661,6 @@ config MMC_SDHCI_KONA config MMC_SDHCI_MSM bool "Qualcomm SDHCI controller" - depends on DM_MMC depends on MMC_SDHCI help Enables support for SDHCI 2.0 controller present on some Qualcomm @@ -685,7 +672,6 @@ config MMC_SDHCI_MV bool "SDHCI support on Marvell platform" depends on ARCH_MVEBU depends on MMC_SDHCI - depends on DM_MMC help This selects the Secure Digital Host Controller Interface on Marvell platform. @@ -697,7 +683,6 @@ config MMC_SDHCI_MV config MMC_SDHCI_NPCM bool "SDHCI support on Nuvoton NPCM device" depends on MMC_SDHCI - depends on DM_MMC help This selects the Secure Digital Host Controller Interface (SDHCI) on Nuvoton NPCM device. @@ -708,7 +693,7 @@ config MMC_SDHCI_NPCM config MMC_SDHCI_PIC32 bool "Microchip PIC32 on-chip SDHCI support" - depends on DM_MMC && MACH_PIC32 + depends on MACH_PIC32 depends on MMC_SDHCI help Support for Microchip PIC32 SDHCI controller. @@ -716,7 +701,6 @@ config MMC_SDHCI_PIC32 config MMC_SDHCI_ROCKCHIP bool "Arasan SDHCI controller for Rockchip support" depends on ARCH_ROCKCHIP - depends on DM_MMC && BLK depends on MMC_SDHCI help Support for Arasan SDHCI host controller on Rockchip ARM SoCs platform @@ -735,7 +719,6 @@ config MMC_SDHCI_S5P config MMC_SDHCI_SNPS bool "Synopsys DesignWare SDHCI controller" depends on MMC_SDHCI - depends on DM_MMC help Support for DesignWare SDHCI host controller on Alibaba TH1520 SoC. This is a highly configurable and programmable, high performance @@ -753,7 +736,7 @@ config MMC_SDHCI_STI config MMC_SDHCI_XENON bool "SDHCI support for the Xenon SDHCI controller" - depends on MMC_SDHCI && DM_MMC && OF_CONTROL + depends on MMC_SDHCI && OF_CONTROL help Support for Xenon SDHCI host controller on Marvell Armada 3700 7k/8k ARM SoCs platforms @@ -764,7 +747,6 @@ config MMC_SDHCI_XENON config MMC_SDHCI_TANGIER bool "Tangier SDHCI controller support" - depends on DM_MMC && BLK depends on MMC_SDHCI help This selects support for SDHCI controller on Tanginer @@ -800,7 +782,7 @@ config TEGRA124_MMC_DISABLE_EXT_LOOPBACK config MMC_SDHCI_ZYNQ bool "Arasan SDHCI controller support" - depends on DM_MMC && OF_CONTROL && BLK + depends on OF_CONTROL depends on MMC_SDHCI help Support for Arasan SDHCI host controller on Zynq/ZynqMP ARM SoCs platform @@ -842,7 +824,6 @@ config MMC_SUNXI_HAS_MODE_SWITCH config MMC_PITON bool "MMC support for OpenPiton SoC" - depends on DM_MMC && BLK help This selects support for the SD host controller on OpenPiton SoC. Note that this SD controller directly exposes the contents of the @@ -851,7 +832,7 @@ config MMC_PITON config GENERIC_ATMEL_MCI bool "Atmel Multimedia Card Interface support" - depends on DM_MMC && ARCH_AT91 + depends on ARCH_AT91 help This enables support for Atmel High Speed Multimedia Card Interface (HSMCI), which supports the MultiMedia Card (MMC) Specification V4.3, @@ -860,7 +841,7 @@ config GENERIC_ATMEL_MCI config STM32_SDMMC2 bool "STMicroelectronics STM32H7 SD/MMC Host Controller support" - depends on DM_MMC && OF_CONTROL + depends on OF_CONTROL help This selects support for the SD/MMC controller on STM32H7 SoCs. If you have a board based on such a SoC and with a SD/MMC slot, @@ -880,7 +861,6 @@ config FTSDC010_SDIO config MMC_MTK bool "MediaTek SD/MMC Card Interface support" depends on ARCH_MEDIATEK || ARCH_MTMIPS - depends on DM_MMC depends on OF_CONTROL help This selects the MediaTek(R) Secure digital and Multimedia card Interface. @@ -911,7 +891,7 @@ config FSL_ESDHC_SUPPORT_ADMA2 config FSL_ESDHC_33V_IO_RELIABILITY_WORKAROUND bool "enable eSDHC workaround for 3.3v IO reliability issue" - depends on FSL_ESDHC && DM_MMC + depends on FSL_ESDHC help When eSDHC operates at 3.3v, damage can accumulate in an internal level shifter at a higher than expected rate. The faster the interface diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c index e1110cace89..a51494380ce 100644 --- a/drivers/mmc/dw_mmc.c +++ b/drivers/mmc/dw_mmc.c @@ -724,7 +724,7 @@ static int dwmci_init(struct mmc *mmc) return 0; } -#ifdef CONFIG_DM_MMC +#if CONFIG_IS_ENABLED(DM_MMC) int dwmci_probe(struct udevice *dev) { struct mmc *mmc = mmc_get_mmc_dev(dev); @@ -749,7 +749,7 @@ void dwmci_setup_cfg(struct mmc_config *cfg, struct dwmci_host *host, u32 max_clk, u32 min_clk) { cfg->name = host->name; -#ifndef CONFIG_DM_MMC +#if !CONFIG_IS_ENABLED(DM_MMC) cfg->ops = &dwmci_ops; #endif cfg->f_min = min_clk; diff --git a/drivers/mmc/mtk-sd.c b/drivers/mmc/mtk-sd.c index d676cf9e314..2bc700b0d05 100644 --- a/drivers/mmc/mtk-sd.c +++ b/drivers/mmc/mtk-sd.c @@ -329,6 +329,7 @@ struct msdc_compatible { u8 clk_div_bits; bool pad_tune0; bool async_fifo; + bool async_fifo_crcsts; bool data_tune; bool busy_check; bool stop_clk_fix; @@ -1553,8 +1554,12 @@ static void msdc_init_hw(struct msdc_host *host) /* use async fifo to avoid tune internal delay */ clrbits_le32(&host->base->patch_bit2, MSDC_PB2_CFGRESP); - clrbits_le32(&host->base->patch_bit2, - MSDC_PB2_CFGCRCSTS); + if (host->dev_comp->async_fifo_crcsts) + setbits_le32(&host->base->patch_bit2, + MSDC_PB2_CFGCRCSTS); + else + clrbits_le32(&host->base->patch_bit2, + MSDC_PB2_CFGCRCSTS); } if (host->dev_comp->data_tune) { @@ -1844,6 +1849,17 @@ static const struct msdc_compatible mt7986_compat = { .enhance_rx = true, }; +static const struct msdc_compatible mt7987_compat = { + .clk_div_bits = 12, + .pad_tune0 = true, + .async_fifo = true, + .async_fifo_crcsts = true, + .data_tune = true, + .busy_check = true, + .stop_clk_fix = true, + .enhance_rx = true, +}; + static const struct msdc_compatible mt7981_compat = { .clk_div_bits = 12, .pad_tune0 = true, @@ -1886,6 +1902,7 @@ static const struct udevice_id msdc_ids[] = { { .compatible = "mediatek,mt7622-mmc", .data = (ulong)&mt7622_compat }, { .compatible = "mediatek,mt7623-mmc", .data = (ulong)&mt7623_compat }, { .compatible = "mediatek,mt7986-mmc", .data = (ulong)&mt7986_compat }, + { .compatible = "mediatek,mt7987-mmc", .data = (ulong)&mt7987_compat }, { .compatible = "mediatek,mt7981-mmc", .data = (ulong)&mt7981_compat }, { .compatible = "mediatek,mt8512-mmc", .data = (ulong)&mt8512_compat }, { .compatible = "mediatek,mt8516-mmc", .data = (ulong)&mt8516_compat }, diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig index c71c1e5547c..2b7f5e5ed7b 100644 --- a/drivers/mtd/Kconfig +++ b/drivers/mtd/Kconfig @@ -34,7 +34,7 @@ config MTD_CONCAT config MTD_BLOCK bool "Enable block device access to MTD devices" - depends on BLK + select BLK help Enable support for block device access to MTD devices using blk_ops abstraction. @@ -216,7 +216,7 @@ config STM32_FLASH STM32 MCU. config SYS_MAX_FLASH_SECT - int "Maximumm number of sectors on a flash chip" + int "Maximum number of sectors on a flash chip" depends on MTD_NOR_FLASH || FLASH_CFI_DRIVER default 512 diff --git a/drivers/mtd/ubi/Kconfig b/drivers/mtd/ubi/Kconfig index c027d898a64..ba77c034736 100644 --- a/drivers/mtd/ubi/Kconfig +++ b/drivers/mtd/ubi/Kconfig @@ -116,7 +116,7 @@ config MTD_UBI_FM_DEBUG config UBI_BLOCK bool "Enable UBI block device support" - depends on BLK + select BLK help Enable UBI block device support using blk_ops abstraction. diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 88ff025a37b..1563404ca17 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -966,26 +966,7 @@ config TSEC_ENET This driver implements support for the (Enhanced) Three-Speed Ethernet Controller found on Freescale SoCs. -config MEDIATEK_ETH - bool "MediaTek Ethernet GMAC Driver" - select PHYLIB - select DM_GPIO - select DM_RESET - help - This Driver support MediaTek Ethernet GMAC - Say Y to enable support for the MediaTek Ethernet GMAC. - -if MEDIATEK_ETH - -config MTK_ETH_SGMII - bool - default y if ARCH_MEDIATEK && !TARGET_MT7623 - -config MTK_ETH_XGMII - bool - default y if TARGET_MT7987 || TARGET_MT7988 - -endif # MEDIATEK_ETH +source "drivers/net/mtk_eth/Kconfig" config HIFEMAC_ETH bool "HiSilicon Fast Ethernet Controller" @@ -1019,6 +1000,20 @@ config FSL_ENETC This driver supports the NXP ENETC Ethernet controller found on some of the NXP SoCs. +config FSL_ENETC_NETC_BLK_CTRL + bool "NXP ENETC NETC blocks control driver" + depends on FSL_ENETC && IMX95 + default y if IMX95 + help + This driver configures Integrated Endpoint Register Block (IERB) and + Privileged Register Block (PRB) of NETC. For i.MX platforms, it also + includes the configuration of NETCMIX block. + The IERB contains registers that are used for pre-boot initialization, + debug, and non-customer configuration. The PRB controls global reset + and global error handling for NETC. The NETCMIX block is mainly used + to set MII protocol and PCS protocol of the links, it also contains + settings for some other functions. + config MDIO_GPIO_BITBANG bool "GPIO bitbanging MDIO driver" depends on DM_MDIO && DM_GPIO diff --git a/drivers/net/Makefile b/drivers/net/Makefile index e51a917933e..80d70212971 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -44,6 +44,7 @@ obj-$(CONFIG_FEC_MXC) += fec_mxc.o obj-$(CONFIG_FMAN_ENET) += fm/ obj-$(CONFIG_FMAN_ENET) += fsl_mdio.o obj-$(CONFIG_FSL_ENETC) += fsl_enetc.o fsl_enetc_mdio.o +obj-$(CONFIG_FSL_ENETC_NETC_BLK_CTRL) += fsl_enetc_netc_blk_ctrl.o obj-$(CONFIG_FSL_LS_MDIO) += fsl_ls_mdio.o obj-$(CONFIG_FSL_MC_ENET) += fsl-mc/ obj-$(CONFIG_FSL_MC_ENET) += ldpaa_eth/ @@ -68,7 +69,7 @@ obj-$(CONFIG_MDIO_MUX_MESON_GXL) += mdio_mux_meson_gxl.o obj-$(CONFIG_MDIO_MUX_MMIOREG) += mdio_mux_mmioreg.o obj-$(CONFIG_MDIO_MUX_SANDBOX) += mdio_mux_sandbox.o obj-$(CONFIG_MDIO_SANDBOX) += mdio_sandbox.o -obj-$(CONFIG_MEDIATEK_ETH) += mtk_eth.o +obj-$(CONFIG_MEDIATEK_ETH) += mtk_eth/ obj-$(CONFIG_MPC8XX_FEC) += mpc8xx_fec.o obj-$(CONFIG_MT7620_ETH) += mt7620-eth.o obj-$(CONFIG_MT7628_ETH) += mt7628-eth.o diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 07b0f49ef58..0a1fff38727 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -741,6 +741,18 @@ int designware_eth_probe(struct udevice *dev) puts("Error enabling phy supply\n"); return ret; } +#if IS_ENABLED(CONFIG_ARCH_NPCM8XX) + int phy_uv; + + phy_uv = dev_read_u32_default(dev, "phy-supply-microvolt", 0); + if (phy_uv) { + ret = regulator_set_value(phy_supply, phy_uv); + if (ret) { + puts("Error setting phy voltage\n"); + return ret; + } + } +#endif } #endif @@ -784,6 +796,39 @@ int designware_eth_probe(struct udevice *dev) priv->bus = miiphy_get_dev_by_name(dev->name); priv->dev = dev; +#if IS_ENABLED(CONFIG_BITBANGMII) && IS_ENABLED(CONFIG_DM_GPIO) + if (dev_read_bool(dev, "snps,bitbang-mii")) { + int bus_idx; + + debug("\n%s: use bitbang mii..\n", dev->name); + ret = gpio_request_by_name(dev, "snps,mdc-gpio", 0, + &priv->mdc_gpio, GPIOD_IS_OUT + | GPIOD_IS_OUT_ACTIVE); + if (ret) { + debug("no mdc-gpio\n"); + return ret; + } + ret = gpio_request_by_name(dev, "snps,mdio-gpio", 0, + &priv->mdio_gpio, GPIOD_IS_OUT + | GPIOD_IS_OUT_ACTIVE); + if (ret) { + debug("no mdio-gpio\n"); + return ret; + } + priv->bb_delay = dev_read_u32_default(dev, "snps,bitbang-delay", 1); + + for (bus_idx = 0; bus_idx < bb_miiphy_buses_num; bus_idx++) { + if (!bb_miiphy_buses[bus_idx].priv) { + bb_miiphy_buses[bus_idx].priv = priv; + strlcpy(bb_miiphy_buses[bus_idx].name, priv->bus->name, + MDIO_NAME_LEN); + priv->bus->read = bb_miiphy_read; + priv->bus->write = bb_miiphy_write; + break; + } + } + } +#endif ret = dw_phy_init(priv, dev); debug("%s, ret=%d\n", __func__, ret); if (!ret) @@ -894,3 +939,83 @@ static struct pci_device_id supported[] = { }; U_BOOT_PCI_DEVICE(eth_designware, supported); + +#if IS_ENABLED(CONFIG_BITBANGMII) && IS_ENABLED(CONFIG_DM_GPIO) +static int dw_eth_bb_mdio_active(struct bb_miiphy_bus *bus) +{ + struct dw_eth_dev *priv = bus->priv; + struct gpio_desc *desc = &priv->mdio_gpio; + + desc->flags = 0; + dm_gpio_set_dir_flags(&priv->mdio_gpio, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + + return 0; +} + +static int dw_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus) +{ + struct dw_eth_dev *priv = bus->priv; + struct gpio_desc *desc = &priv->mdio_gpio; + + desc->flags = 0; + dm_gpio_set_dir_flags(&priv->mdio_gpio, GPIOD_IS_IN); + + return 0; +} + +static int dw_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v) +{ + struct dw_eth_dev *priv = bus->priv; + + if (v) + dm_gpio_set_value(&priv->mdio_gpio, 1); + else + dm_gpio_set_value(&priv->mdio_gpio, 0); + + return 0; +} + +static int dw_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v) +{ + struct dw_eth_dev *priv = bus->priv; + + *v = dm_gpio_get_value(&priv->mdio_gpio); + + return 0; +} + +static int dw_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v) +{ + struct dw_eth_dev *priv = bus->priv; + + if (v) + dm_gpio_set_value(&priv->mdc_gpio, 1); + else + dm_gpio_set_value(&priv->mdc_gpio, 0); + + return 0; +} + +static int dw_eth_bb_delay(struct bb_miiphy_bus *bus) +{ + struct dw_eth_dev *priv = bus->priv; + + udelay(priv->bb_delay); + return 0; +} + +struct bb_miiphy_bus bb_miiphy_buses[] = { + { + .name = BB_MII_DEVNAME, + .mdio_active = dw_eth_bb_mdio_active, + .mdio_tristate = dw_eth_bb_mdio_tristate, + .set_mdio = dw_eth_bb_set_mdio, + .get_mdio = dw_eth_bb_get_mdio, + .set_mdc = dw_eth_bb_set_mdc, + .delay = dw_eth_bb_delay, + .priv = NULL, + } +}; + +int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses); +#endif diff --git a/drivers/net/designware.h b/drivers/net/designware.h index e47101ccaf6..cccf9d54e02 100644 --- a/drivers/net/designware.h +++ b/drivers/net/designware.h @@ -229,7 +229,11 @@ struct dw_eth_dev { u32 max_speed; u32 tx_currdescnum; u32 rx_currdescnum; - +#if IS_ENABLED(CONFIG_BITBANGMII) && IS_ENABLED(CONFIG_DM_GPIO) + u32 bb_delay; + struct gpio_desc mdc_gpio; + struct gpio_desc mdio_gpio; +#endif struct eth_mac_regs *mac_regs_p; struct eth_dma_regs *dma_regs_p; #if CONFIG_IS_ENABLED(DM_GPIO) diff --git a/drivers/net/dwc_eth_xgmac.c b/drivers/net/dwc_eth_xgmac.c index d3e5f9255f5..cf8227b1b4d 100644 --- a/drivers/net/dwc_eth_xgmac.c +++ b/drivers/net/dwc_eth_xgmac.c @@ -152,7 +152,9 @@ static int xgmac_mdio_read(struct mii_dev *bus, int mdio_addr, int mdio_devad, ret = xgmac_mdio_wait_idle(xgmac); if (ret) { - pr_err("MDIO not idle at entry: %d\n", ret); + pr_err("%s MDIO not idle at entry: %d\n", + xgmac->dev->name, ret); + return ret; } @@ -172,7 +174,9 @@ static int xgmac_mdio_read(struct mii_dev *bus, int mdio_addr, int mdio_devad, ret = xgmac_mdio_wait_idle(xgmac); if (ret) { - pr_err("MDIO not idle at entry: %d\n", ret); + pr_err("%s MDIO not idle at entry: %d\n", + xgmac->dev->name, ret); + return ret; } @@ -181,7 +185,9 @@ static int xgmac_mdio_read(struct mii_dev *bus, int mdio_addr, int mdio_devad, ret = xgmac_mdio_wait_idle(xgmac); if (ret) { - pr_err("MDIO read didn't complete: %d\n", ret); + pr_err("%s MDIO read didn't complete: %d\n", + xgmac->dev->name, ret); + return ret; } @@ -206,7 +212,9 @@ static int xgmac_mdio_write(struct mii_dev *bus, int mdio_addr, int mdio_devad, ret = xgmac_mdio_wait_idle(xgmac); if (ret) { - pr_err("MDIO not idle at entry: %d\n", ret); + pr_err("%s MDIO not idle at entry: %d\n", + xgmac->dev->name, ret); + return ret; } @@ -229,7 +237,9 @@ static int xgmac_mdio_write(struct mii_dev *bus, int mdio_addr, int mdio_devad, ret = xgmac_mdio_wait_idle(xgmac); if (ret) { - pr_err("MDIO not idle at entry: %d\n", ret); + pr_err("%s MDIO not idle at entry: %d\n", + xgmac->dev->name, ret); + return ret; } @@ -238,7 +248,9 @@ static int xgmac_mdio_write(struct mii_dev *bus, int mdio_addr, int mdio_devad, ret = xgmac_mdio_wait_idle(xgmac); if (ret) { - pr_err("MDIO write didn't complete: %d\n", ret); + pr_err("%s MDIO write didn't complete: %d\n", + xgmac->dev->name, ret); + return ret; } @@ -323,7 +335,7 @@ static int xgmac_adjust_link(struct udevice *dev) else ret = xgmac_set_half_duplex(dev); if (ret < 0) { - pr_err("xgmac_set_*_duplex() failed: %d\n", ret); + pr_err("%s xgmac_set_*_duplex() failed: %d\n", dev->name, ret); return ret; } @@ -341,26 +353,28 @@ static int xgmac_adjust_link(struct udevice *dev) ret = xgmac_set_mii_speed_10(dev); break; default: - pr_err("invalid speed %d\n", xgmac->phy->speed); + pr_err("%s invalid speed %d\n", dev->name, xgmac->phy->speed); return -EINVAL; } if (ret < 0) { - pr_err("xgmac_set_*mii_speed*() failed: %d\n", ret); + pr_err("%s xgmac_set_*mii_speed*() failed: %d\n", dev->name, ret); return ret; } if (en_calibration) { ret = xgmac->config->ops->xgmac_calibrate_pads(dev); if (ret < 0) { - pr_err("xgmac_calibrate_pads() failed: %d\n", - ret); + pr_err("%s xgmac_calibrate_pads() failed: %d\n", + dev->name, ret); + return ret; } } else { ret = xgmac->config->ops->xgmac_disable_calibration(dev); if (ret < 0) { - pr_err("xgmac_disable_calibration() failed: %d\n", - ret); + pr_err("%s xgmac_disable_calibration() failed: %d\n", + dev->name, ret); + return ret; } } @@ -456,7 +470,7 @@ static int xgmac_start(struct udevice *dev) ret = xgmac->config->ops->xgmac_start_resets(dev); if (ret < 0) { - pr_err("xgmac_start_resets() failed: %d\n", ret); + pr_err("%s xgmac_start_resets() failed: %d\n", dev->name, ret); goto err; } @@ -466,13 +480,13 @@ static int xgmac_start(struct udevice *dev) XGMAC_DMA_MODE_SWR, false, xgmac->config->swr_wait, false); if (ret) { - pr_err("XGMAC_DMA_MODE_SWR stuck: %d\n", ret); + pr_err("%s XGMAC_DMA_MODE_SWR stuck: %d\n", dev->name, ret); goto err_stop_resets; } ret = xgmac->config->ops->xgmac_calibrate_pads(dev); if (ret < 0) { - pr_err("xgmac_calibrate_pads() failed: %d\n", ret); + pr_err("%s xgmac_calibrate_pads() failed: %d\n", dev->name, ret); goto err_stop_resets; } @@ -485,14 +499,16 @@ static int xgmac_start(struct udevice *dev) xgmac->phy = phy_connect(xgmac->mii, addr, dev, xgmac->config->interface(dev)); if (!xgmac->phy) { - pr_err("phy_connect() failed\n"); + pr_err("%s phy_connect() failed\n", dev->name); goto err_stop_resets; } if (xgmac->max_speed) { ret = phy_set_supported(xgmac->phy, xgmac->max_speed); if (ret) { - pr_err("phy_set_supported() failed: %d\n", ret); + pr_err("%s phy_set_supported() failed: %d\n", + dev->name, ret); + goto err_shutdown_phy; } } @@ -500,25 +516,25 @@ static int xgmac_start(struct udevice *dev) xgmac->phy->node = xgmac->phy_of_node; ret = phy_config(xgmac->phy); if (ret < 0) { - pr_err("phy_config() failed: %d\n", ret); + pr_err("%s phy_config() failed: %d\n", dev->name, ret); goto err_shutdown_phy; } } ret = phy_startup(xgmac->phy); if (ret < 0) { - pr_err("phy_startup() failed: %d\n", ret); + pr_err("%s phy_startup() failed: %d\n", dev->name, ret); goto err_shutdown_phy; } if (!xgmac->phy->link) { - pr_err("No link\n"); + pr_err("%s No link\n", dev->name); goto err_shutdown_phy; } ret = xgmac_adjust_link(dev); if (ret < 0) { - pr_err("xgmac_adjust_link() failed: %d\n", ret); + pr_err("%s xgmac_adjust_link() failed: %d\n", dev->name, ret); goto err_shutdown_phy; } @@ -611,7 +627,7 @@ static int xgmac_start(struct udevice *dev) ret = xgmac_write_hwaddr(dev); if (ret < 0) { - pr_err("xgmac_write_hwaddr() failed: %d\n", ret); + pr_err("%s xgmac_write_hwaddr() failed: %d\n", dev->name, ret); goto err; } @@ -738,7 +754,7 @@ err_shutdown_phy: err_stop_resets: xgmac->config->ops->xgmac_stop_resets(dev); err: - pr_err("FAILED: %d\n", ret); + pr_err("%s FAILED: %d\n", dev->name, ret); return ret; } @@ -1047,7 +1063,7 @@ static int xgmac_probe(struct udevice *dev) xgmac->regs = dev_read_addr(dev); if (xgmac->regs == FDT_ADDR_T_NONE) { - pr_err("dev_read_addr() failed\n"); + pr_err("%s dev_read_addr() failed\n", dev->name); return -ENODEV; } xgmac->mac_regs = (void *)(xgmac->regs + XGMAC_MAC_REGS_BASE); @@ -1058,19 +1074,23 @@ static int xgmac_probe(struct udevice *dev) ret = xgmac_probe_resources_core(dev); if (ret < 0) { - pr_err("xgmac_probe_resources_core() failed: %d\n", ret); + pr_err("%s xgmac_probe_resources_core() failed: %d\n", + dev->name, ret); + return ret; } ret = xgmac->config->ops->xgmac_probe_resources(dev); if (ret < 0) { - pr_err("xgmac_probe_resources() failed: %d\n", ret); + pr_err("%s xgmac_probe_resources() failed: %d\n", + dev->name, ret); + goto err_remove_resources_core; } ret = xgmac->config->ops->xgmac_start_clks(dev); if (ret < 0) { - pr_err("xgmac_start_clks() failed: %d\n", ret); + pr_err("%s xgmac_start_clks() failed: %d\n", dev->name, ret); return ret; } @@ -1080,7 +1100,7 @@ static int xgmac_probe(struct udevice *dev) if (!xgmac->mii) { xgmac->mii = mdio_alloc(); if (!xgmac->mii) { - pr_err("mdio_alloc() failed\n"); + pr_err("%s mdio_alloc() failed\n", dev->name); ret = -ENOMEM; goto err_stop_clks; } @@ -1091,7 +1111,9 @@ static int xgmac_probe(struct udevice *dev) ret = mdio_register(xgmac->mii); if (ret < 0) { - pr_err("mdio_register() failed: %d\n", ret); + pr_err("%s mdio_register() failed: %d\n", + dev->name, ret); + goto err_free_mdio; } } diff --git a/drivers/net/dwc_eth_xgmac_socfpga.c b/drivers/net/dwc_eth_xgmac_socfpga.c index 87fb7e887e7..c89c8a188b7 100644 --- a/drivers/net/dwc_eth_xgmac_socfpga.c +++ b/drivers/net/dwc_eth_xgmac_socfpga.c @@ -29,6 +29,25 @@ #define SOCFPGA_XGMAC_SYSCON_ARG_COUNT 2 +phy_interface_t dwxgmac_of_get_mac_mode(struct udevice *dev) +{ + const char *mac_mode; + int i; + + debug("%s(dev=%p):\n", __func__, dev); + mac_mode = dev_read_string(dev, "mac-mode"); + if (!mac_mode) + return PHY_INTERFACE_MODE_NA; + + if (mac_mode) { + for (i = 0; i < PHY_INTERFACE_MODE_MAX; i++) { + if (!strcmp(mac_mode, phy_interface_strings[i])) + return i; + } + } + return PHY_INTERFACE_MODE_NA; +} + static int dwxgmac_socfpga_do_setphy(struct udevice *dev, u32 modereg) { struct xgmac_priv *xgmac = dev_get_priv(dev); @@ -66,12 +85,17 @@ static int xgmac_probe_resources_socfpga(struct udevice *dev) struct ofnode_phandle_args args; void *range; phy_interface_t interface; + phy_interface_t mac_mode; int ret; u32 modereg; interface = xgmac->config->interface(dev); + mac_mode = dwxgmac_of_get_mac_mode(dev); + + if (mac_mode == PHY_INTERFACE_MODE_NA) + mac_mode = interface; - switch (interface) { + switch (mac_mode) { case PHY_INTERFACE_MODE_MII: case PHY_INTERFACE_MODE_GMII: modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII; @@ -80,6 +104,7 @@ static int xgmac_probe_resources_socfpga(struct udevice *dev) modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII; break; case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII; break; default: diff --git a/drivers/net/dwmac_socfpga.c b/drivers/net/dwmac_socfpga.c index a9e2d8c0972..a55f3e29f9f 100644 --- a/drivers/net/dwmac_socfpga.c +++ b/drivers/net/dwmac_socfpga.c @@ -106,6 +106,9 @@ static int dwmac_socfpga_probe(struct udevice *dev) modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII; break; case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII; break; default: diff --git a/drivers/net/fsl_enetc.c b/drivers/net/fsl_enetc.c index a6b0bafc8c6..52fa820f518 100644 --- a/drivers/net/fsl_enetc.c +++ b/drivers/net/fsl_enetc.c @@ -2,8 +2,10 @@ /* * ENETC ethernet controller driver * Copyright 2017-2021 NXP + * Copyright 2023-2025 NXP */ +#include <clk.h> #include <dm.h> #include <errno.h> #include <fdt_support.h> @@ -16,52 +18,267 @@ #include <miiphy.h> #include <linux/bug.h> #include <linux/delay.h> +#include <linux/build_bug.h> + +#ifdef CONFIG_ARCH_IMX9 +#include <asm/mach-imx/sys_proto.h> +#include <cpu_func.h> +#endif #include "fsl_enetc.h" #define ENETC_DRIVER_NAME "enetc_eth" +/* + * Calculate number of buffer descriptors per cacheline, and compile-time + * validate that: + * - the RX and TX descriptors are the same size + * - the descriptors fit exactly into cachelines without overlap + * - all descriptors fit exactly into cachelines + */ +#define ENETC_NUM_BD_IN_CL \ + ((ARCH_DMA_MINALIGN / sizeof(struct enetc_tx_bd)) + \ + BUILD_BUG_ON_ZERO(sizeof(struct enetc_tx_bd) != \ + sizeof(union enetc_rx_bd)) + \ + BUILD_BUG_ON_ZERO(ARCH_DMA_MINALIGN % sizeof(struct enetc_tx_bd)) + \ + BUILD_BUG_ON_ZERO(ARCH_DMA_MINALIGN % sizeof(union enetc_rx_bd)) + \ + BUILD_BUG_ON_ZERO(ENETC_BD_CNT % \ + (ARCH_DMA_MINALIGN / sizeof(struct enetc_tx_bd)))) + static int enetc_remove(struct udevice *dev); +static int enetc_is_imx95(struct udevice *dev) +{ + struct pci_child_plat *pplat = dev_get_parent_plat(dev); + + /* Test whether this is i.MX95 ENETCv4. This may be optimized out. */ + return IS_ENABLED(CONFIG_ARCH_IMX9) && + pplat->vendor == PCI_VENDOR_ID_PHILIPS; +} + +static int enetc_is_ls1028a(struct udevice *dev) +{ + struct pci_child_plat *pplat = dev_get_parent_plat(dev); + + /* Test whether this is LS1028A ENETC. This may be optimized out. */ + return IS_ENABLED(CONFIG_ARCH_LS1028A) && + pplat->vendor == PCI_VENDOR_ID_FREESCALE; +} + +static int enetc_dev_id(struct udevice *dev) +{ + if (enetc_is_imx95(dev)) + return PCI_DEV(pci_get_devfn(dev)) >> 3; + if (enetc_is_ls1028a(dev)) + return PCI_FUNC(pci_get_devfn(dev)); + + return 0; +} + +static void enetc_inval_rxbd(struct udevice *dev) +{ + struct enetc_priv *priv = dev_get_priv(dev); + union enetc_rx_bd *desc = &priv->enetc_rxbd[priv->rx_bdr.next_prod_idx]; + unsigned long start = rounddown((unsigned long)desc, ARCH_DMA_MINALIGN); + unsigned long end = roundup((unsigned long)desc + sizeof(*desc), + ARCH_DMA_MINALIGN); + + if (enetc_is_imx95(dev)) + invalidate_dcache_range(start, end); +} + +static void enetc_flush_bd(struct udevice *dev, int pi, bool tx) +{ + struct enetc_priv *priv = dev_get_priv(dev); + union enetc_rx_bd *rxdesc = &priv->enetc_rxbd[pi]; + struct enetc_tx_bd *txdesc = &priv->enetc_txbd[pi]; + unsigned long desc = tx ? (unsigned long)txdesc : (unsigned long)rxdesc; + unsigned long size = tx ? sizeof(*txdesc) : sizeof(*rxdesc); + unsigned long start = rounddown(desc, ARCH_DMA_MINALIGN); + unsigned long end = roundup(desc + size, ARCH_DMA_MINALIGN); + + if (enetc_is_imx95(dev)) + flush_dcache_range(start, end); +} + +static void enetc_inval_buffer(struct udevice *dev, void *buf, size_t size) +{ + unsigned long start = rounddown((unsigned long)buf, ARCH_DMA_MINALIGN); + unsigned long end = roundup((unsigned long)buf + size, + ARCH_DMA_MINALIGN); + + if (enetc_is_imx95(dev)) + invalidate_dcache_range(start, end); +} + +static void enetc_flush_buffer(struct udevice *dev, void *buf, size_t size) +{ + unsigned long start = rounddown((unsigned long)buf, ARCH_DMA_MINALIGN); + unsigned long end = roundup((unsigned long)buf + size, + ARCH_DMA_MINALIGN); + + if (enetc_is_imx95(dev)) + flush_dcache_range(start, end); +} + +/* register accessors */ +static u32 enetc_read_reg(void __iomem *addr) +{ + return readl(addr); +} + +static void enetc_write_reg(void __iomem *addr, u32 val) +{ + writel(val, addr); +} + +static void enetc_write(struct enetc_priv *priv, u32 off, u32 val) +{ + enetc_write_reg(priv->regs_base + off, val); +} + +/* base port register accessors */ +static void enetc_write_pmr(struct udevice *dev, u32 val) +{ + struct enetc_data *data = (struct enetc_data *)dev_get_driver_data(dev); + struct enetc_priv *priv = dev_get_priv(dev); + const u32 off = ENETC_PMR + data->reg_offset_pmr; + + enetc_write_reg(priv->port_regs + off, val); +} + +static void enetc_write_psipmar(struct udevice *dev, int n, u32 val) +{ + struct enetc_data *data = (struct enetc_data *)dev_get_driver_data(dev); + struct enetc_priv *priv = dev_get_priv(dev); + const u32 off = (n ? ENETC_PSIPMAR1 : ENETC_PSIPMAR0) + + data->reg_offset_psipmar; + + enetc_write_reg(priv->port_regs + off, val); +} + +/* port station register accessors */ +static void enetc_write_psicfgr(struct udevice *dev, int port, u32 val) +{ + struct enetc_data *data = (struct enetc_data *)dev_get_driver_data(dev); + struct enetc_priv *priv = dev_get_priv(dev); + const u32 off = ENETC_PSICFGR(port, ENETC_PSICFGR_SHIFT_LS) + + data->reg_offset_psicfgr; + + enetc_write_reg(priv->port_regs + off, val); +} + +/* port register accessors */ +static u32 enetc_read_pcapr_mdio(struct udevice *dev) +{ + struct enetc_data *data = (struct enetc_data *)dev_get_driver_data(dev); + struct enetc_priv *priv = dev_get_priv(dev); + const u32 off = ENETC_PCAPR0 + data->reg_offset_pcapr; + const u32 reg = enetc_read_reg(priv->port_regs + off); + + if (enetc_is_imx95(dev)) + return reg & ENETC_PCS_PROT; + else if (enetc_is_ls1028a(dev)) + return reg & ENETC_PCAPRO_MDIO; + + return 0; +} + +static void enetc_write_port(struct enetc_priv *priv, u32 off, u32 val) +{ + enetc_write_reg(priv->port_regs + off, val); +} + +/* MAC port register accessors */ +static u32 enetc_read_mac_port(struct udevice *dev, u32 off) +{ + struct enetc_data *data = (struct enetc_data *)dev_get_driver_data(dev); + struct enetc_priv *priv = dev_get_priv(dev); + + return enetc_read_reg(priv->port_regs + data->reg_offset_mac + off); +} + +static void enetc_write_mac_port(struct udevice *dev, u32 off, u32 val) +{ + struct enetc_data *data = (struct enetc_data *)dev_get_driver_data(dev); + struct enetc_priv *priv = dev_get_priv(dev); + + enetc_write_reg(priv->port_regs + data->reg_offset_mac + off, val); +} + +/* BDR register accessor, see also ENETC_BDR() */ +static void enetc_bdr_write(struct enetc_priv *priv, int type, int n, + u32 off, u32 val) +{ + enetc_write(priv, ENETC_BDR(type, n, off), val); +} + /* * sets the MAC address in IERB registers, this setting is persistent and * carried over to Linux. */ -static void enetc_set_ierb_primary_mac(struct udevice *dev, int devfn, - const u8 *enetaddr) -{ -#ifdef CONFIG_ARCH_LS1028A -/* - * LS1028A is the only part with IERB at this time and there are plans to change - * its structure, keep this LS1028A specific for now - */ #define IERB_BASE 0x1f0800000ULL #define IERB_PFMAC(pf, vf, n) (IERB_BASE + 0x8000 + (pf) * 0x100 + (vf) * 8 \ + (n) * 4) -static int ierb_fn_to_pf[] = {0, 1, 2, -1, -1, -1, 3}; - +static void enetc_set_ierb_primary_mac(struct udevice *dev, void *blob) +{ + static int ierb_fn_to_pf[] = { 0, 1, 2, -1, -1, -1, 3 }; + struct pci_child_plat *ppdata = dev_get_parent_plat(dev); + struct eth_pdata *pdata = dev_get_plat(dev); + struct enetc_priv *priv = dev_get_priv(dev); + const u8 *enetaddr = pdata->enetaddr; u16 lower = *(const u16 *)(enetaddr + 4); u32 upper = *(const u32 *)enetaddr; + int devfn, offset; + char path[256]; - if (ierb_fn_to_pf[devfn] < 0) + if (enetc_is_imx95(dev)) { + /* + * Configure the ENETC primary MAC addresses - Set register + * PMAR0/1 for SI 0 and PSIaPMAR0/1 for SI 1, 2 .. a + * (optionally pre-configured in IERB). + */ + devfn = enetc_dev_id(dev); + if (devfn > 2) + return; + + enetc_write(priv, IMX95_ENETC_SIPMAR0, upper); + enetc_write(priv, IMX95_ENETC_SIPMAR1, lower); + + snprintf(path, 256, "/soc/pcie@%x/ethernet@%x,%x", + PCI_BUS(dm_pci_get_bdf(dev)), PCI_DEV(ppdata->devfn), + PCI_FUNC(ppdata->devfn)); + } else if (enetc_is_ls1028a(dev)) { + /* + * LS1028A is the only part with IERB at this time and + * there are plans to change its structure, keep this + * LS1028A specific for now. + */ + devfn = PCI_FUNC(ppdata->devfn); + + if (ierb_fn_to_pf[devfn] < 0) + return; + + out_le32(IERB_PFMAC(ierb_fn_to_pf[devfn], 0, 0), upper); + out_le32(IERB_PFMAC(ierb_fn_to_pf[devfn], 0, 1), (u32)lower); + + snprintf(path, 256, "/soc/pcie@1f0000000/ethernet@%x,%x", + PCI_DEV(ppdata->devfn), PCI_FUNC(ppdata->devfn)); + } else { return; + } - out_le32(IERB_PFMAC(ierb_fn_to_pf[devfn], 0, 0), upper); - out_le32(IERB_PFMAC(ierb_fn_to_pf[devfn], 0, 1), (u32)lower); -#endif + offset = fdt_path_offset(blob, path); + if (offset >= 0) + fdt_setprop(blob, offset, "mac-address", pdata->enetaddr, 6); } /* sets up primary MAC addresses in DT/IERB */ void fdt_fixup_enetc_mac(void *blob) { - struct pci_child_plat *ppdata; - struct eth_pdata *pdata; struct udevice *dev; struct uclass *uc; - char path[256]; - int offset; - int devfn; uclass_get(UCLASS_ETH, &uc); uclass_foreach_dev(dev, uc) { @@ -69,18 +286,7 @@ void fdt_fixup_enetc_mac(void *blob) strcmp(dev->driver->name, ENETC_DRIVER_NAME)) continue; - pdata = dev_get_plat(dev); - ppdata = dev_get_parent_plat(dev); - devfn = PCI_FUNC(ppdata->devfn); - - enetc_set_ierb_primary_mac(dev, devfn, pdata->enetaddr); - - snprintf(path, 256, "/soc/pcie@1f0000000/ethernet@%x,%x", - PCI_DEV(ppdata->devfn), PCI_FUNC(ppdata->devfn)); - offset = fdt_path_offset(blob, path); - if (offset < 0) - continue; - fdt_setprop(blob, offset, "mac-address", pdata->enetaddr, 6); + enetc_set_ierb_primary_mac(dev, blob); } } @@ -101,7 +307,7 @@ static int enetc_bind(struct udevice *dev) * PCI function # and enetc#N based on interface count */ if (ofnode_valid(dev_ofnode(dev))) - sprintf(name, "enetc-%u", PCI_FUNC(pci_get_devfn(dev))); + sprintf(name, "enetc-%u", enetc_dev_id(dev)); else sprintf(name, "enetc#%u", eth_num_devices++); device_set_name(dev, name); @@ -181,10 +387,9 @@ static int enetc_init_sgmii(struct udevice *dev) /* set up MAC for RGMII */ static void enetc_init_rgmii(struct udevice *dev, struct phy_device *phydev) { - struct enetc_priv *priv = dev_get_priv(dev); - u32 old_val, val; + u32 old_val, val, dpx = 0; - old_val = val = enetc_read_port(priv, ENETC_PM_IF_MODE); + old_val = val = enetc_read_mac_port(dev, ENETC_PM_IF_MODE); /* disable unreliable RGMII in-band signaling and force the MAC into * the speed negotiated by the PHY. @@ -202,15 +407,20 @@ static void enetc_init_rgmii(struct udevice *dev, struct phy_device *phydev) val |= ENETC_PM_IFM_SSP_10; } + if (enetc_is_imx95(dev)) + dpx = ENETC_PM_IFM_FULL_DPX_IMX; + else if (enetc_is_ls1028a(dev)) + dpx = ENETC_PM_IFM_FULL_DPX_LS; + if (phydev->duplex == DUPLEX_FULL) - val |= ENETC_PM_IFM_FULL_DPX; + val |= dpx; else - val &= ~ENETC_PM_IFM_FULL_DPX; + val &= ~dpx; if (val == old_val) return; - enetc_write_port(priv, ENETC_PM_IF_MODE, val); + enetc_write_mac_port(dev, ENETC_PM_IF_MODE, val); } /* set up MAC configuration for the given interface type */ @@ -230,9 +440,12 @@ static void enetc_setup_mac_iface(struct udevice *dev, case PHY_INTERFACE_MODE_USXGMII: case PHY_INTERFACE_MODE_10GBASER: /* set ifmode to (US)XGMII */ - if_mode = enetc_read_port(priv, ENETC_PM_IF_MODE); - if_mode &= ~ENETC_PM_IF_IFMODE_MASK; - enetc_write_port(priv, ENETC_PM_IF_MODE, if_mode); + if_mode = enetc_read_mac_port(dev, ENETC_PM_IF_MODE); + if (enetc_is_imx95(dev)) + if_mode &= ~ENETC_PM_IF_IFMODE_MASK_IMX; + else if (enetc_is_ls1028a(dev)) + if_mode &= ~ENETC_PM_IF_IFMODE_MASK_LS; + enetc_write_mac_port(dev, ENETC_PM_IF_MODE, if_mode); break; }; } @@ -263,7 +476,7 @@ static void enetc_start_pcs(struct udevice *dev) struct enetc_priv *priv = dev_get_priv(dev); /* register internal MDIO for debug purposes */ - if (enetc_read_port(priv, ENETC_PCAPR0) & ENETC_PCAPRO_MDIO) { + if (enetc_read_pcapr_mdio(dev)) { priv->imdio.read = enetc_mdio_read; priv->imdio.write = enetc_mdio_write; priv->imdio.priv = priv->port_regs + ENETC_PM_IMDIO_BASE; @@ -375,6 +588,21 @@ static int enetc_remove(struct udevice *dev) return 0; } +static int enetc_imx95_write_hwaddr(struct udevice *dev) +{ + struct eth_pdata *plat = dev_get_plat(dev); + struct enetc_priv *priv = dev_get_priv(dev); + u8 *addr = plat->enetaddr; + + u16 lower = *(const u16 *)(addr + 4); + u32 upper = *(const u32 *)addr; + + enetc_write_port(priv, IMX95_ENETC_PMAR0, upper); + enetc_write_port(priv, IMX95_ENETC_PMAR1, lower); + + return 0; +} + /* * LS1028A is the only part with IERB at this time and there are plans to * change its structure, keep this LS1028A specific for now. @@ -413,39 +641,46 @@ static int enetc_ls1028a_write_hwaddr(struct udevice *dev) static int enetc_write_hwaddr(struct udevice *dev) { struct eth_pdata *plat = dev_get_plat(dev); - struct enetc_priv *priv = dev_get_priv(dev); u8 *addr = plat->enetaddr; - if (IS_ENABLED(CONFIG_ARCH_LS1028A)) + if (enetc_is_imx95(dev)) + return enetc_imx95_write_hwaddr(dev); + if (enetc_is_ls1028a(dev)) return enetc_ls1028a_write_hwaddr(dev); u16 lower = *(const u16 *)(addr + 4); u32 upper = *(const u32 *)addr; - enetc_write_port(priv, ENETC_PSIPMAR0, upper); - enetc_write_port(priv, ENETC_PSIPMAR1, lower); + enetc_write_psipmar(dev, 0, upper); + enetc_write_psipmar(dev, 1, lower); return 0; } /* Configure port parameters (# of rings, frame size, enable port) */ -static void enetc_enable_si_port(struct enetc_priv *priv) +static void enetc_enable_si_port(struct udevice *dev) { - u32 val; + struct enetc_priv *priv = dev_get_priv(dev); + u32 val = ENETC_PM_CC_TXP_IMX | ENETC_PM_CC_TX | ENETC_PM_CC_RX; /* set Rx/Tx BDR count */ - val = ENETC_PSICFGR_SET_TXBDR(ENETC_TX_BDR_CNT); - val |= ENETC_PSICFGR_SET_RXBDR(ENETC_RX_BDR_CNT); - enetc_write_port(priv, ENETC_PSICFGR(0), val); + enetc_write_psicfgr(dev, 0, ENETC_PSICFGR_SET_BDR(ENETC_RX_BDR_CNT, + ENETC_TX_BDR_CNT)); /* set Rx max frame size */ - enetc_write_port(priv, ENETC_PM_MAXFRM, ENETC_RX_MAXFRM_SIZE); + enetc_write_mac_port(dev, ENETC_PM_MAXFRM, ENETC_RX_MAXFRM_SIZE); /* enable MAC port */ - enetc_write_port(priv, ENETC_PM_CC, ENETC_PM_CC_RX_TX_EN); + if (enetc_is_ls1028a(dev)) + val |= ENETC_PM_CC_TXP_LS | ENETC_PM_CC_PROMIS; + enetc_write_mac_port(dev, ENETC_PM_CC, val); /* enable port */ - enetc_write_port(priv, ENETC_PMR, ENETC_PMR_SI0_EN); + if (enetc_is_imx95(dev)) + enetc_write_port(priv, ENETC_POR, 0x0); + enetc_write_pmr(dev, ENETC_PMR_SI0_EN); /* set SI cache policy */ - enetc_write(priv, ENETC_SICAR0, - ENETC_SICAR_RD_CFG | ENETC_SICAR_WR_CFG); + enetc_write(priv, ENETC_SICAR0, ENETC_SICAR_WR_CFG | + (enetc_is_imx95(dev) ? + ENETC_SICAR_RD_CFG_IMX : + ENETC_SICAR_RD_CFG_LS)); /* enable SI */ enetc_write(priv, ENETC_SIMR, ENETC_SIMR_EN); } @@ -536,6 +771,8 @@ static void enetc_setup_rx_bdr(struct udevice *dev) priv->enetc_rxbd[i].w.addr = enetc_rxb_address(dev, i); /* each RX buffer must be aligned to 64B */ WARN_ON(priv->enetc_rxbd[i].w.addr & (ARCH_DMA_MINALIGN - 1)); + + enetc_flush_bd(dev, i, false); } /* reset producer (ENETC owned) and consumer (SW owned) index */ @@ -556,6 +793,7 @@ static void enetc_setup_rx_bdr(struct udevice *dev) */ static int enetc_start(struct udevice *dev) { + int ret; struct enetc_priv *priv = dev_get_priv(dev); /* reset and enable the PCI device */ @@ -563,15 +801,19 @@ static int enetc_start(struct udevice *dev) dm_pci_clrset_config16(dev, PCI_COMMAND, 0, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); - enetc_enable_si_port(priv); + enetc_enable_si_port(dev); /* setup Tx/Rx buffer descriptors */ enetc_setup_tx_bdr(dev); enetc_setup_rx_bdr(dev); + ret = phy_startup(priv->phy); + if (ret) + return ret; + enetc_setup_mac_iface(dev, priv->phy); - return phy_startup(priv->phy); + return 0; } /* @@ -614,6 +856,8 @@ static int enetc_send(struct udevice *dev, void *packet, int length) enetc_dbg(dev, "TxBD[%d]send: pkt_len=%d, buff @0x%x%08x\n", pi, length, upper_32_bits((u64)nv_packet), lower_32_bits((u64)nv_packet)); + enetc_flush_buffer(dev, packet, length); + /* prepare Tx BD */ memset(&priv->enetc_txbd[pi], 0x0, sizeof(struct enetc_tx_bd)); priv->enetc_txbd[pi].addr = @@ -621,7 +865,10 @@ static int enetc_send(struct udevice *dev, void *packet, int length) priv->enetc_txbd[pi].buf_len = cpu_to_le16(length); priv->enetc_txbd[pi].frm_len = cpu_to_le16(length); priv->enetc_txbd[pi].flags = cpu_to_le16(ENETC_TXBD_FLAGS_F); + dmb(); + enetc_flush_bd(dev, pi, true); + /* send frame: increment producer index */ pi = (pi + 1) % txr->bd_count; txr->next_prod_idx = pi; @@ -643,15 +890,15 @@ static int enetc_recv(struct udevice *dev, int flags, uchar **packetp) { struct enetc_priv *priv = dev_get_priv(dev); struct bd_ring *rxr = &priv->rx_bdr; - int tries = ENETC_POLL_TRIES; int pi = rxr->next_prod_idx; - int ci = rxr->next_cons_idx; + int tries = ENETC_POLL_TRIES; u32 status; int len; u8 rdy; do { dmb(); + enetc_inval_rxbd(dev); status = le32_to_cpu(priv->enetc_rxbd[pi].r.lstatus); /* check if current BD is ready to be consumed */ rdy = ENETC_RXBD_STATUS_R(status); @@ -663,45 +910,162 @@ static int enetc_recv(struct udevice *dev, int flags, uchar **packetp) dmb(); len = le16_to_cpu(priv->enetc_rxbd[pi].r.buf_len); *packetp = (uchar *)enetc_rxb_address(dev, pi); + enetc_inval_buffer(dev, *packetp, len); enetc_dbg(dev, "RxBD[%d]: len=%d err=%d pkt=0x%x%08x\n", pi, len, ENETC_RXBD_STATUS_ERRORS(status), upper_32_bits((u64)*packetp), lower_32_bits((u64)*packetp)); - /* BD clean up and advance to next in ring */ - memset(&priv->enetc_rxbd[pi], 0, sizeof(union enetc_rx_bd)); - priv->enetc_rxbd[pi].w.addr = enetc_rxb_address(dev, pi); + return len; +} + +static int enetc_free_pkt(struct udevice *dev, uchar *packet, int length) +{ + const int bd_num_in_cl = enetc_is_imx95(dev) ? ENETC_NUM_BD_IN_CL : 1; + struct enetc_priv *priv = dev_get_priv(dev); + struct bd_ring *rxr = &priv->rx_bdr; + int pi = rxr->next_prod_idx; + int ci = rxr->next_cons_idx; + uchar *packet_expected; + int i; + + packet_expected = (uchar *)enetc_rxb_address(dev, pi); + if (packet != packet_expected) { + printf("%s: Unexpected packet (expected %p)\n", __func__, + packet_expected); + return -EINVAL; + } + rxr->next_prod_idx = (pi + 1) % rxr->bd_count; ci = (ci + 1) % rxr->bd_count; rxr->next_cons_idx = ci; dmb(); - /* free up the slot in the ring for HW */ - enetc_write_reg(rxr->cons_idx, ci); - return len; + if ((pi + 1) % bd_num_in_cl == 0) { + /* BD clean up and advance to next in ring */ + for (i = 0; i < bd_num_in_cl; i++) { + memset(&priv->enetc_rxbd[pi - i], 0, sizeof(union enetc_rx_bd)); + priv->enetc_rxbd[pi - i].w.addr = enetc_rxb_address(dev, pi - i); + } + + /* Will flush all bds in one cacheline */ + enetc_flush_bd(dev, pi - bd_num_in_cl + 1, false); + + /* free up the slot in the ring for HW */ + enetc_write_reg(rxr->cons_idx, ci); + } + + return 0; +} + +#if IS_ENABLED(CONFIG_ARCH_IMX9) +static int enetc_read_rom_hwaddr(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_plat(dev); + unsigned int dev_id = enetc_dev_id(dev); + unsigned char *mac = pdata->enetaddr; + + if (dev_id > 2) + return -EINVAL; + + imx_get_mac_from_fuse(dev_id, mac); + + return !is_valid_ethaddr(mac); } -static const struct eth_ops enetc_ops = { +static const struct eth_ops enetc_ops_imx = { + .start = enetc_start, + .send = enetc_send, + .recv = enetc_recv, + .stop = enetc_stop, + .free_pkt = enetc_free_pkt, + .write_hwaddr = enetc_write_hwaddr, + .read_rom_hwaddr = enetc_read_rom_hwaddr, +}; + +static int enetc_probe_imx(struct udevice *dev) +{ + struct clk *clk; + int ret; + + clk = devm_clk_get_optional(dev, "ref"); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + ret = clk_enable(clk); + if (ret) + return ret; + + ret = enetc_probe(dev); + if (ret) + clk_disable(clk); + + return ret; +} + +U_BOOT_DRIVER(eth_enetc_imx) = { + .name = ENETC_DRIVER_NAME, + .id = UCLASS_ETH, + .bind = enetc_bind, + .probe = enetc_probe_imx, + .remove = enetc_remove, + .ops = &enetc_ops_imx, + .priv_auto = sizeof(struct enetc_priv), + .plat_auto = sizeof(struct eth_pdata), +}; + +static const struct enetc_data enetc_data_imx = { + .reg_offset_pmr = ENETC_PMR_OFFSET_IMX, + .reg_offset_psipmar = ENETC_PSIPMARn_OFFSET_IMX, + .reg_offset_pcapr = ENETC_PCAPR_OFFSET_IMX, + .reg_offset_psicfgr = ENETC_PSICFGR_OFFSET_IMX, + .reg_offset_mac = ENETC_PM_OFFSET_IMX, +}; + +static struct pci_device_id enetc_ids_imx[] = { + { + PCI_DEVICE(PCI_VENDOR_ID_PHILIPS, PCI_DEVICE_ID_ENETC4_ETH), + .driver_data = (ulong)&enetc_data_imx, + }, + {} +}; + +U_BOOT_PCI_DEVICE(eth_enetc_imx, enetc_ids_imx); +#endif + +static const struct eth_ops enetc_ops_ls = { .start = enetc_start, .send = enetc_send, .recv = enetc_recv, .stop = enetc_stop, + .free_pkt = enetc_free_pkt, .write_hwaddr = enetc_write_hwaddr, }; -U_BOOT_DRIVER(eth_enetc) = { +U_BOOT_DRIVER(eth_enetc_ls) = { .name = ENETC_DRIVER_NAME, .id = UCLASS_ETH, .bind = enetc_bind, .probe = enetc_probe, .remove = enetc_remove, - .ops = &enetc_ops, + .ops = &enetc_ops_ls, .priv_auto = sizeof(struct enetc_priv), .plat_auto = sizeof(struct eth_pdata), }; -static struct pci_device_id enetc_ids[] = { - { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, PCI_DEVICE_ID_ENETC_ETH) }, +static const struct enetc_data enetc_data_ls = { + .reg_offset_pmr = ENETC_PMR_OFFSET_LS, + .reg_offset_psipmar = ENETC_PSIPMARn_OFFSET_LS, + .reg_offset_pcapr = ENETC_PCAPR_OFFSET_LS, + .reg_offset_psicfgr = ENETC_PSICFGR_OFFSET_LS, + .reg_offset_mac = ENETC_PM_OFFSET_LS, +}; + +static struct pci_device_id enetc_ids_ls[] = { + { + PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, PCI_DEVICE_ID_ENETC_ETH), + .driver_data = (ulong)&enetc_data_ls, + }, {} }; -U_BOOT_PCI_DEVICE(eth_enetc, enetc_ids); +U_BOOT_PCI_DEVICE(eth_enetc_ls, enetc_ids_ls); diff --git a/drivers/net/fsl_enetc.h b/drivers/net/fsl_enetc.h index f2acf367aa3..804df853bf5 100644 --- a/drivers/net/fsl_enetc.h +++ b/drivers/net/fsl_enetc.h @@ -12,7 +12,9 @@ /* PCI function IDs */ #define PCI_DEVICE_ID_ENETC_ETH 0xE100 +#define PCI_DEVICE_ID_ENETC4_ETH 0xE101 #define PCI_DEVICE_ID_ENETC_MDIO 0xEE01 +#define PCI_DEVICE_ID_ENETC4_EMDIO 0xEE00 /* ENETC Ethernet controller registers */ /* Station interface register offsets */ @@ -22,7 +24,8 @@ /* write cache cfg: snoop, no allocate, data & BD coherent */ #define ENETC_SICAR_WR_CFG 0x6767 /* read cache cfg: coherent copy, look up, don't alloc in cache */ -#define ENETC_SICAR_RD_CFG 0x27270000 +#define ENETC_SICAR_RD_CFG_LS 0x27270000 +#define ENETC_SICAR_RD_CFG_IMX 0x2b2b0000 #define ENETC_SIROCT 0x300 #define ENETC_SIRFRM 0x308 #define ENETC_SITOCT 0x320 @@ -57,32 +60,60 @@ enum enetc_bdr_type {TX, RX}; #define ENETC_PORT_REGS_OFF 0x10000 /* Port registers */ +#define ENETC_PMR_OFFSET_IMX 0x0010 +#define ENETC_PMR_OFFSET_LS 0x0000 #define ENETC_PMR 0x0000 #define ENETC_PMR_SI0_EN BIT(16) #define ENETC_PSIPMMR 0x0018 -#define ENETC_PSIPMAR0 0x0100 -#define ENETC_PSIPMAR1 0x0104 -#define ENETC_PCAPR0 0x0900 -#define ENETC_PCAPRO_MDIO BIT(11) -#define ENETC_PSICFGR(n) (0x0940 + (n) * 0x10) -#define ENETC_PSICFGR_SET_TXBDR(val) ((val) & 0xff) -#define ENETC_PSICFGR_SET_RXBDR(val) (((val) & 0xff) << 16) +#define ENETC_PSIPMARn_OFFSET_IMX 0x0000 +#define ENETC_PSIPMARn_OFFSET_LS 0x0080 +#define ENETC_PSIPMAR0 0x0080 +#define ENETC_PSIPMAR1 0x0084 +#define ENETC_PCAPR_OFFSET_IMX 0x4008 +#define ENETC_PCAPR_OFFSET_LS 0x0900 +#define ENETC_PCAPR0 0x0000 +#define ENETC_PCAPRO_MDIO BIT(11) /* LS only */ +#define ENETC_PCS_PROT GENMASK(15, 0) /* IMX only */ +/* ENETC base registers */ +#define ENETC_PSICFGR_OFFSET_LS 0x0940 +#define ENETC_PSICFGR_SHIFT_LS 0x10 +#define ENETC_PSICFGR_OFFSET_IMX 0x2010 +#define ENETC_PSICFGR_SHIFT_IMX 0x80 +#define ENETC_PSICFGR(n, s) ((n) * (s)) +#define ENETC_PSICFGR_SET_BDR(rx, tx) (((rx) << 16) | (tx)) /* MAC configuration */ -#define ENETC_PM_CC 0x8008 +#define ENETC_PM_OFFSET_IMX 0x5000 +#define ENETC_PM_OFFSET_LS 0x8000 +#define ENETC_PM_CC 0x0008 #define ENETC_PM_CC_DEFAULT 0x0810 -#define ENETC_PM_CC_RX_TX_EN 0x8813 -#define ENETC_PM_MAXFRM 0x8014 +#define ENETC_PM_CC_TXP_IMX BIT(15) +#define ENETC_PM_CC_TXP_LS BIT(11) +#define ENETC_PM_CC_PROMIS BIT(4) +#define ENETC_PM_CC_TX BIT(1) +#define ENETC_PM_CC_RX BIT(0) +#define ENETC_PM_MAXFRM 0x0014 #define ENETC_RX_MAXFRM_SIZE PKTSIZE_ALIGN -#define ENETC_PM_IMDIO_BASE 0x8030 -#define ENETC_PM_IF_MODE 0x8300 +#define ENETC_PM_IMDIO_BASE 0x0030 +#define ENETC_PM_IF_MODE 0x0300 #define ENETC_PM_IF_MODE_RG BIT(2) #define ENETC_PM_IF_MODE_AN_ENA BIT(15) #define ENETC_PM_IFM_SSP_MASK GENMASK(14, 13) #define ENETC_PM_IFM_SSP_1000 (2 << 13) #define ENETC_PM_IFM_SSP_100 (0 << 13) #define ENETC_PM_IFM_SSP_10 (1 << 13) -#define ENETC_PM_IFM_FULL_DPX BIT(12) -#define ENETC_PM_IF_IFMODE_MASK GENMASK(1, 0) +#define ENETC_PM_IFM_FULL_DPX_IMX BIT(6) +#define ENETC_PM_IFM_FULL_DPX_LS BIT(12) +#define ENETC_PM_IF_IFMODE_MASK_IMX GENMASK(2, 0) +#define ENETC_PM_IF_IFMODE_MASK_LS GENMASK(1, 0) + +/* i.MX95 specific registers */ +#define IMX95_ENETC_SIPMAR0 0x80 +#define IMX95_ENETC_SIPMAR1 0x84 + +/* Port registers */ +#define IMX95_ENETC_PMAR0 0x4020 +#define IMX95_ENETC_PMAR1 0x4024 +#define ENETC_POR 0x4100 /* buffer descriptors count must be multiple of 8 and aligned to 128 bytes */ #define ENETC_BD_CNT CONFIG_SYS_RX_ETH_BUFFER @@ -163,25 +194,14 @@ struct enetc_priv { struct phy_device *phy; }; -/* register accessors */ -#define enetc_read_reg(x) readl((x)) -#define enetc_write_reg(x, val) writel((val), (x)) -#define enetc_read(priv, off) enetc_read_reg((priv)->regs_base + (off)) -#define enetc_write(priv, off, v) \ - enetc_write_reg((priv)->regs_base + (off), v) - -/* port register accessors */ -#define enetc_port_regs(priv, off) ((priv)->port_regs + (off)) -#define enetc_read_port(priv, off) \ - enetc_read_reg(enetc_port_regs((priv), (off))) -#define enetc_write_port(priv, off, v) \ - enetc_write_reg(enetc_port_regs((priv), (off)), v) - -/* BDR register accessors, see ENETC_BDR() */ -#define enetc_bdr_read(priv, t, n, off) \ - enetc_read(priv, ENETC_BDR(t, n, off)) -#define enetc_bdr_write(priv, t, n, off, val) \ - enetc_write(priv, ENETC_BDR(t, n, off), val) +struct enetc_data { + /* Register layout offsets */ + u16 reg_offset_pmr; + u16 reg_offset_psipmar; + u16 reg_offset_pcapr; + u16 reg_offset_psicfgr; + u16 reg_offset_mac; +}; /* PCS / internal SoC PHY ID, it defaults to 0 on all interfaces */ #define ENETC_PCS_PHY_ADDR 0 diff --git a/drivers/net/fsl_enetc_mdio.c b/drivers/net/fsl_enetc_mdio.c index 2d5fcbb6dbd..c1d491f2c5a 100644 --- a/drivers/net/fsl_enetc_mdio.c +++ b/drivers/net/fsl_enetc_mdio.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * ENETC ethernet controller driver - * Copyright 2019 NXP + * Copyright 2019-2025 NXP */ #include <dm.h> @@ -14,6 +14,16 @@ #include "fsl_enetc.h" +static u32 enetc_read(struct enetc_mdio_priv *priv, u32 off) +{ + return readl(priv->regs_base + off); +} + +static void enetc_write(struct enetc_mdio_priv *priv, u32 off, u32 val) +{ + writel(val, priv->regs_base + off); +} + static void enetc_mdio_wait_bsy(struct enetc_mdio_priv *priv) { int to = 10000; @@ -122,7 +132,9 @@ static int enetc_mdio_bind(struct udevice *dev) static int enetc_mdio_probe(struct udevice *dev) { + struct pci_child_plat *pplat = dev_get_parent_plat(dev); struct enetc_mdio_priv *priv = dev_get_priv(dev); + u16 cmd = PCI_COMMAND_MEMORY; priv->regs_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_TYPE, 0); if (!priv->regs_base) { @@ -132,7 +144,10 @@ static int enetc_mdio_probe(struct udevice *dev) priv->regs_base += ENETC_MDIO_BASE; - dm_pci_clrset_config16(dev, PCI_COMMAND, 0, PCI_COMMAND_MEMORY); + if (pplat->vendor == PCI_VENDOR_ID_PHILIPS) /* i.MX95 */ + cmd |= PCI_COMMAND_MASTER; + + dm_pci_clrset_config16(dev, PCI_COMMAND, 0, cmd); return 0; } @@ -148,6 +163,7 @@ U_BOOT_DRIVER(enetc_mdio) = { static struct pci_device_id enetc_mdio_ids[] = { { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, PCI_DEVICE_ID_ENETC_MDIO) }, + { PCI_DEVICE(PCI_VENDOR_ID_PHILIPS, PCI_DEVICE_ID_ENETC4_EMDIO) }, { } }; diff --git a/drivers/net/fsl_enetc_netc_blk_ctrl.c b/drivers/net/fsl_enetc_netc_blk_ctrl.c new file mode 100644 index 00000000000..46b68d3d8a4 --- /dev/null +++ b/drivers/net/fsl_enetc_netc_blk_ctrl.c @@ -0,0 +1,346 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * NXP NETC Blocks Control Driver + * + * Copyright 2024 NXP + * + * This driver is used for pre-initialization of NETC, such as PCS and MII + * protocols, LDID, warm reset, etc. Therefore, all NETC device drivers can + * only be probed after the netc-blk-crtl driver has completed initialization. + * In addition, when the system enters suspend mode, IERB, PRB, and NETCMIX + * will be powered off, except for WOL. Therefore, when the system resumes, + * these blocks need to be reinitialized. + */ + +#include <asm/io.h> +#include <clk.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <linux/bitfield.h> +#include <linux/delay.h> +#include <linux/errno.h> +#include <linux/iopoll.h> +#include <phy_interface.h> + +/* NETCMIX registers */ +#define IMX95_CFG_LINK_IO_VAR 0x0 +#define IO_VAR_16FF_16G_SERDES 0x1 +#define IO_VAR(port, var) (((var) & 0xf) << ((port) << 2)) + +#define IMX95_CFG_LINK_MII_PROT 0x4 +#define CFG_LINK_MII_PORT_0 GENMASK(3, 0) +#define CFG_LINK_MII_PORT_1 GENMASK(7, 4) +#define MII_PROT_MII 0x0 +#define MII_PROT_RMII 0x1 +#define MII_PROT_RGMII 0x2 +#define MII_PROT_SERIAL 0x3 +#define MII_PROT(port, prot) (((prot) & 0xf) << ((port) << 2)) + +#define IMX95_CFG_LINK_PCS_PROT(a) (0x8 + (a) * 4) +#define PCS_PROT_1G_SGMII BIT(0) +#define PCS_PROT_2500M_SGMII BIT(1) +#define PCS_PROT_XFI BIT(3) +#define PCS_PROT_SFI BIT(4) +#define PCS_PROT_10G_SXGMII BIT(6) + +/* NETC privileged register block register */ +#define PRB_NETCRR 0x100 +#define NETCRR_SR BIT(0) +#define NETCRR_LOCK BIT(1) + +#define PRB_NETCSR 0x104 +#define NETCSR_ERROR BIT(0) +#define NETCSR_STATE BIT(1) + +/* NETC integrated endpoint register block register */ +#define IERB_EMDIOFAUXR 0x344 +#define IERB_T0FAUXR 0x444 +#define IERB_EFAUXR(a) (0x3044 + 0x100 * (a)) +#define IERB_VFAUXR(a) (0x4004 + 0x40 * (a)) +#define FAUXR_LDID GENMASK(3, 0) + +/* Platform information */ +#define IMX95_ENETC0_BUS_DEVFN 0x0 +#define IMX95_ENETC1_BUS_DEVFN 0x40 +#define IMX95_ENETC2_BUS_DEVFN 0x80 + +/* Flags for different platforms */ +#define NETC_HAS_NETCMIX BIT(0) + +struct netc_blk_ctrl { + void __iomem *prb; + void __iomem *ierb; + void __iomem *netcmix; +}; + +static void netc_reg_write(void __iomem *base, u32 offset, u32 val) +{ + writel(val, base + offset); +} + +static u32 netc_reg_read(void __iomem *base, u32 offset) +{ + return readl(base + offset); +} + +static int netc_of_pci_get_bus_devfn(ofnode node) +{ + u32 reg[5]; + int error; + + error = ofnode_read_u32_array(node, "reg", reg, ARRAY_SIZE(reg)); + if (error) + return error; + + return (reg[0] >> 8) & 0xffff; +} + +static int netc_get_link_mii_protocol(phy_interface_t interface) +{ + switch (interface) { + case PHY_INTERFACE_MODE_MII: + return MII_PROT_MII; + case PHY_INTERFACE_MODE_RMII: + return MII_PROT_RMII; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + return MII_PROT_RGMII; + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_2500BASEX: + case PHY_INTERFACE_MODE_10GBASER: + case PHY_INTERFACE_MODE_XGMII: + case PHY_INTERFACE_MODE_USXGMII: + return MII_PROT_SERIAL; + default: + return -EINVAL; + } +} + +static int imx95_netcmix_init(struct udevice *dev) +{ + struct netc_blk_ctrl *priv = dev_get_priv(dev); + ofnode child, gchild; + phy_interface_t interface; + int bus_devfn, mii_proto; + u32 val; + + /* Default setting of MII protocol */ + val = MII_PROT(0, MII_PROT_RGMII) | MII_PROT(1, MII_PROT_RGMII) | + MII_PROT(2, MII_PROT_SERIAL); + + /* Update the link MII protocol through parsing phy-mode */ + dev_for_each_subnode(child, dev) { + if (!ofnode_is_enabled(child)) + continue; + + ofnode_for_each_subnode(gchild, child) { + if (!ofnode_is_enabled(gchild)) + continue; + + if (!ofnode_device_is_compatible(gchild, "pci1131,e101")) + continue; + + bus_devfn = netc_of_pci_get_bus_devfn(gchild); + if (bus_devfn < 0) + return -EINVAL; + + if (bus_devfn == IMX95_ENETC2_BUS_DEVFN) + continue; + + interface = ofnode_read_phy_mode(gchild); + if (interface == -1) + continue; + + mii_proto = netc_get_link_mii_protocol(interface); + if (mii_proto < 0) + return -EINVAL; + + switch (bus_devfn) { + case IMX95_ENETC0_BUS_DEVFN: + val &= ~CFG_LINK_MII_PORT_0; + val |= FIELD_PREP(CFG_LINK_MII_PORT_0, mii_proto); + break; + case IMX95_ENETC1_BUS_DEVFN: + val &= ~CFG_LINK_MII_PORT_1; + val |= FIELD_PREP(CFG_LINK_MII_PORT_1, mii_proto); + break; + default: + return -EINVAL; + } + } + } + + /* Configure Link I/O variant */ + netc_reg_write(priv->netcmix, IMX95_CFG_LINK_IO_VAR, + IO_VAR(2, IO_VAR_16FF_16G_SERDES)); + /* Configure Link 2 PCS protocol */ + netc_reg_write(priv->netcmix, IMX95_CFG_LINK_PCS_PROT(2), + PCS_PROT_10G_SXGMII); + netc_reg_write(priv->netcmix, IMX95_CFG_LINK_MII_PROT, val); + + return 0; +} + +static bool netc_ierb_is_locked(struct netc_blk_ctrl *priv) +{ + return !!(netc_reg_read(priv->prb, PRB_NETCRR) & NETCRR_LOCK); +} + +static int netc_lock_ierb(struct netc_blk_ctrl *priv) +{ + u32 val; + + netc_reg_write(priv->prb, PRB_NETCRR, NETCRR_LOCK); + + return readl_poll_timeout(priv->prb + PRB_NETCSR, val, + !(val & NETCSR_STATE), 2000); +} + +static int netc_unlock_ierb_with_warm_reset(struct netc_blk_ctrl *priv) +{ + u32 val; + + netc_reg_write(priv->prb, PRB_NETCRR, 0); + + return readl_poll_timeout(priv->prb + PRB_NETCRR, val, + !(val & NETCRR_LOCK), 100000); +} + +static int imx95_ierb_init(struct udevice *dev) +{ + struct netc_blk_ctrl *priv = dev_get_priv(dev); + + /* EMDIO : No MSI-X intterupt */ + netc_reg_write(priv->ierb, IERB_EMDIOFAUXR, 0); + /* ENETC0 PF */ + netc_reg_write(priv->ierb, IERB_EFAUXR(0), 0); + /* ENETC0 VF0 */ + netc_reg_write(priv->ierb, IERB_VFAUXR(0), 1); + /* ENETC0 VF1 */ + netc_reg_write(priv->ierb, IERB_VFAUXR(1), 2); + /* ENETC1 PF */ + netc_reg_write(priv->ierb, IERB_EFAUXR(1), 3); + /* ENETC1 VF0 */ + netc_reg_write(priv->ierb, IERB_VFAUXR(2), 5); + /* ENETC1 VF1 */ + netc_reg_write(priv->ierb, IERB_VFAUXR(3), 6); + /* ENETC2 PF */ + netc_reg_write(priv->ierb, IERB_EFAUXR(2), 4); + /* ENETC2 VF0 */ + netc_reg_write(priv->ierb, IERB_VFAUXR(4), 5); + /* ENETC2 VF1 */ + netc_reg_write(priv->ierb, IERB_VFAUXR(5), 6); + /* NETC TIMER */ + netc_reg_write(priv->ierb, IERB_T0FAUXR, 7); + + return 0; +} + +static int netc_ierb_init(struct udevice *dev) +{ + struct netc_blk_ctrl *priv = dev_get_priv(dev); + int err; + + if (netc_ierb_is_locked(priv)) { + err = netc_unlock_ierb_with_warm_reset(priv); + if (err) { + dev_err(dev, "Unlock IERB failed.\n"); + return err; + } + } + + err = imx95_ierb_init(dev); + if (err) + return err; + + err = netc_lock_ierb(priv); + if (err) { + dev_err(dev, "Lock IERB failed.\n"); + return err; + } + + return 0; +} + +static int netc_prb_check_error(struct netc_blk_ctrl *priv) +{ + if (netc_reg_read(priv->prb, PRB_NETCSR) & NETCSR_ERROR) + return -1; + + return 0; +} + +static const struct udevice_id netc_blk_ctrl_match[] = { + { .compatible = "nxp,imx95-netc-blk-ctrl" }, + {}, +}; + +static int netc_blk_ctrl_probe(struct udevice *dev) +{ + struct netc_blk_ctrl *priv = dev_get_priv(dev); + struct clk *ipg_clk; + fdt_addr_t regs; + int err; + + ipg_clk = devm_clk_get_optional(dev, "ipg"); + if (IS_ERR(ipg_clk)) { + dev_err(dev, "Set ipg clock failed\n"); + return PTR_ERR(ipg_clk); + } + + err = clk_prepare_enable(ipg_clk); + if (err) { + dev_err(dev, "Enable ipg clock failed\n"); + return PTR_ERR(ipg_clk); + } + + regs = dev_read_addr_name(dev, "ierb"); + if (regs == FDT_ADDR_T_NONE) { + dev_err(dev, "Missing IERB resource\n"); + return -EINVAL; + } + + priv->ierb = (void __iomem *)regs; + regs = dev_read_addr_name(dev, "prb"); + if (regs == FDT_ADDR_T_NONE) { + dev_err(dev, "Missing PRB resource\n"); + return -EINVAL; + } + + priv->prb = (void __iomem *)regs; + regs = dev_read_addr_name(dev, "netcmix"); + if (regs == FDT_ADDR_T_NONE) { + dev_err(dev, "Missing NETCMIX resource\n"); + return -EINVAL; + } + + priv->netcmix = (void __iomem *)regs; + + err = imx95_netcmix_init(dev); + if (err) { + dev_err(dev, "Initializing NETCMIX failed\n"); + return err; + } + + err = netc_ierb_init(dev); + if (err) { + dev_err(dev, "Initializing IERB failed\n"); + return err; + } + + if (netc_prb_check_error(priv) < 0) + dev_warn(dev, "The current IERB configuration is invalid\n"); + + return 0; +} + +U_BOOT_DRIVER(netc_blk_ctrl_drv) = { + .name = "netc_blk_ctrl", + .id = UCLASS_SIMPLE_BUS, + .of_match = netc_blk_ctrl_match, + .probe = netc_blk_ctrl_probe, + .priv_auto = sizeof(struct netc_blk_ctrl), + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/net/mtk_eth/Kconfig b/drivers/net/mtk_eth/Kconfig new file mode 100644 index 00000000000..e8cdf408237 --- /dev/null +++ b/drivers/net/mtk_eth/Kconfig @@ -0,0 +1,39 @@ + +config MEDIATEK_ETH + bool "MediaTek Ethernet GMAC Driver" + select PHYLIB + select DM_GPIO + select DM_RESET + help + This Driver support MediaTek Ethernet GMAC + Say Y to enable support for the MediaTek Ethernet GMAC. + +if MEDIATEK_ETH + +config MTK_ETH_SGMII + bool + default y if ARCH_MEDIATEK && !TARGET_MT7623 + +config MTK_ETH_XGMII + bool + default y if TARGET_MT7987 || TARGET_MT7988 + +config MTK_ETH_SWITCH_MT7530 + bool "Support for MediaTek MT7530 ethernet switch" + default y if TARGET_MT7623 || SOC_MT7621 + +config MTK_ETH_SWITCH_MT7531 + bool "Support for MediaTek MT7531 ethernet switch" + default y if TARGET_MT7622 || TARGET_MT7629 || TARGET_MT7981 || \ + TARGET_MT7986 || TARGET_MT7987 + +config MTK_ETH_SWITCH_MT7988 + bool "Support for MediaTek MT7988 built-in ethernet switch" + depends on TARGET_MT7988 + default y + +config MTK_ETH_SWITCH_AN8855 + bool "Support for Airoha AN8855 ethernet switch" + default y if TARGET_MT7981 || TARGET_MT7987 + +endif # MEDIATEK_ETH diff --git a/drivers/net/mtk_eth/Makefile b/drivers/net/mtk_eth/Makefile new file mode 100644 index 00000000000..a342325ed5d --- /dev/null +++ b/drivers/net/mtk_eth/Makefile @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2025 MediaTek Inc. +# Author: Weijie Gao <weijie.gao@mediatek.com> + +obj-y += mtk_eth.o +obj-$(CONFIG_MTK_ETH_SWITCH_MT7530) += mt753x.o mt7530.o +obj-$(CONFIG_MTK_ETH_SWITCH_MT7531) += mt753x.o mt7531.o +obj-$(CONFIG_MTK_ETH_SWITCH_MT7988) += mt753x.o mt7988.o +obj-$(CONFIG_MTK_ETH_SWITCH_AN8855) += an8855.o diff --git a/drivers/net/mtk_eth/an8855.c b/drivers/net/mtk_eth/an8855.c new file mode 100644 index 00000000000..25a98e0f935 --- /dev/null +++ b/drivers/net/mtk_eth/an8855.c @@ -0,0 +1,1095 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 MediaTek Inc. + * + * Author: Neal Yen <neal.yen@mediatek.com> + * Author: Weijie Gao <weijie.gao@mediatek.com> + */ + +#include <phy.h> +#include <miiphy.h> +#include <linux/bitops.h> +#include <linux/delay.h> +#include <linux/mdio.h> +#include <linux/mii.h> +#include "mtk_eth.h" + +/* AN8855 Register Definitions */ +#define AN8855_SYS_CTRL_REG 0x100050c0 +#define AN8855_SW_SYS_RST BIT(31) + +#define AN8855_PMCR_REG(p) (0x10210000 + (p) * 0x200) +#define AN8855_FORCE_MODE_LNK BIT(31) +#define AN8855_FORCE_MODE 0xb31593f0 + +#define AN8855_PORT_CTRL_BASE 0x10208000 +#define AN8855_PORT_CTRL_REG(p, r) (AN8855_PORT_CTRL_BASE + (p) * 0x200 + (r)) + +#define AN8855_PORTMATRIX_REG(p) AN8855_PORT_CTRL_REG(p, 0x44) + +#define AN8855_PVC(p) AN8855_PORT_CTRL_REG(p, 0x10) +#define AN8855_STAG_VPID_S 16 +#define AN8855_STAG_VPID_M 0xffff0000 +#define AN8855_VLAN_ATTR_S 6 +#define AN8855_VLAN_ATTR_M 0xc0 + +#define VLAN_ATTR_USER 0 + +#define AN8855_INT_MASK 0x100050F0 +#define AN8855_INT_SYS_BIT BIT(15) + +#define AN8855_RG_CLK_CPU_ICG 0x10005034 +#define AN8855_MCU_ENABLE BIT(3) + +#define AN8855_RG_TIMER_CTL 0x1000a100 +#define AN8855_WDOG_ENABLE BIT(25) + +#define AN8855_CKGCR 0x10213e1c + +#define AN8855_SCU_BASE 0x10000000 +#define AN8855_RG_RGMII_TXCK_C (AN8855_SCU_BASE + 0x1d0) +#define AN8855_RG_GPIO_LED_MODE (AN8855_SCU_BASE + 0x0054) +#define AN8855_RG_GPIO_LED_SEL(i) (AN8855_SCU_BASE + (0x0058 + ((i) * 4))) +#define AN8855_RG_INTB_MODE (AN8855_SCU_BASE + 0x0080) +#define AN8855_RG_GDMP_RAM (AN8855_SCU_BASE + 0x10000) +#define AN8855_RG_GPIO_L_INV (AN8855_SCU_BASE + 0x0010) +#define AN8855_RG_GPIO_CTRL (AN8855_SCU_BASE + 0xa300) +#define AN8855_RG_GPIO_DATA (AN8855_SCU_BASE + 0xa304) +#define AN8855_RG_GPIO_OE (AN8855_SCU_BASE + 0xa314) + +#define AN8855_HSGMII_AN_CSR_BASE 0x10220000 +#define AN8855_SGMII_REG_AN0 (AN8855_HSGMII_AN_CSR_BASE + 0x000) +#define AN8855_SGMII_REG_AN_13 (AN8855_HSGMII_AN_CSR_BASE + 0x034) +#define AN8855_SGMII_REG_AN_FORCE_CL37 (AN8855_HSGMII_AN_CSR_BASE + 0x060) + +#define AN8855_HSGMII_CSR_PCS_BASE 0x10220000 +#define AN8855_RG_HSGMII_PCS_CTROL_1 (AN8855_HSGMII_CSR_PCS_BASE + 0xa00) +#define AN8855_RG_AN_SGMII_MODE_FORCE (AN8855_HSGMII_CSR_PCS_BASE + 0xa24) + +#define AN8855_MULTI_SGMII_CSR_BASE 0x10224000 +#define AN8855_SGMII_STS_CTRL_0 (AN8855_MULTI_SGMII_CSR_BASE + 0x018) +#define AN8855_MSG_RX_CTRL_0 (AN8855_MULTI_SGMII_CSR_BASE + 0x100) +#define AN8855_MSG_RX_LIK_STS_0 (AN8855_MULTI_SGMII_CSR_BASE + 0x514) +#define AN8855_MSG_RX_LIK_STS_2 (AN8855_MULTI_SGMII_CSR_BASE + 0x51c) +#define AN8855_PHY_RX_FORCE_CTRL_0 (AN8855_MULTI_SGMII_CSR_BASE + 0x520) + +#define AN8855_XFI_CSR_PCS_BASE 0x10225000 +#define AN8855_RG_USXGMII_AN_CONTROL_0 (AN8855_XFI_CSR_PCS_BASE + 0xbf8) + +#define AN8855_MULTI_PHY_RA_CSR_BASE 0x10226000 +#define AN8855_RG_RATE_ADAPT_CTRL_0 (AN8855_MULTI_PHY_RA_CSR_BASE + 0x000) +#define AN8855_RATE_ADP_P0_CTRL_0 (AN8855_MULTI_PHY_RA_CSR_BASE + 0x100) +#define AN8855_MII_RA_AN_ENABLE (AN8855_MULTI_PHY_RA_CSR_BASE + 0x300) + +#define AN8855_QP_DIG_CSR_BASE 0x1022a000 +#define AN8855_QP_CK_RST_CTRL_4 (AN8855_QP_DIG_CSR_BASE + 0x310) +#define AN8855_QP_DIG_MODE_CTRL_0 (AN8855_QP_DIG_CSR_BASE + 0x324) +#define AN8855_QP_DIG_MODE_CTRL_1 (AN8855_QP_DIG_CSR_BASE + 0x330) + +#define AN8855_QP_PMA_TOP_BASE 0x1022e000 +#define AN8855_PON_RXFEDIG_CTRL_0 (AN8855_QP_PMA_TOP_BASE + 0x100) +#define AN8855_PON_RXFEDIG_CTRL_9 (AN8855_QP_PMA_TOP_BASE + 0x124) + +#define AN8855_SS_LCPLL_PWCTL_SETTING_2 (AN8855_QP_PMA_TOP_BASE + 0x208) +#define AN8855_SS_LCPLL_TDC_FLT_2 (AN8855_QP_PMA_TOP_BASE + 0x230) +#define AN8855_SS_LCPLL_TDC_FLT_5 (AN8855_QP_PMA_TOP_BASE + 0x23c) +#define AN8855_SS_LCPLL_TDC_PCW_1 (AN8855_QP_PMA_TOP_BASE + 0x248) +#define AN8855_INTF_CTRL_8 (AN8855_QP_PMA_TOP_BASE + 0x320) +#define AN8855_INTF_CTRL_9 (AN8855_QP_PMA_TOP_BASE + 0x324) +#define AN8855_PLL_CTRL_0 (AN8855_QP_PMA_TOP_BASE + 0x400) +#define AN8855_PLL_CTRL_2 (AN8855_QP_PMA_TOP_BASE + 0x408) +#define AN8855_PLL_CTRL_3 (AN8855_QP_PMA_TOP_BASE + 0x40c) +#define AN8855_PLL_CTRL_4 (AN8855_QP_PMA_TOP_BASE + 0x410) +#define AN8855_PLL_CK_CTRL_0 (AN8855_QP_PMA_TOP_BASE + 0x414) +#define AN8855_RX_DLY_0 (AN8855_QP_PMA_TOP_BASE + 0x614) +#define AN8855_RX_CTRL_2 (AN8855_QP_PMA_TOP_BASE + 0x630) +#define AN8855_RX_CTRL_5 (AN8855_QP_PMA_TOP_BASE + 0x63c) +#define AN8855_RX_CTRL_6 (AN8855_QP_PMA_TOP_BASE + 0x640) +#define AN8855_RX_CTRL_7 (AN8855_QP_PMA_TOP_BASE + 0x644) +#define AN8855_RX_CTRL_8 (AN8855_QP_PMA_TOP_BASE + 0x648) +#define AN8855_RX_CTRL_26 (AN8855_QP_PMA_TOP_BASE + 0x690) +#define AN8855_RX_CTRL_42 (AN8855_QP_PMA_TOP_BASE + 0x6d0) + +#define AN8855_QP_ANA_CSR_BASE 0x1022f000 +#define AN8855_RG_QP_RX_DAC_EN (AN8855_QP_ANA_CSR_BASE + 0x00) +#define AN8855_RG_QP_RXAFE_RESERVE (AN8855_QP_ANA_CSR_BASE + 0x04) +#define AN8855_RG_QP_CDR_LPF_MJV_LIM (AN8855_QP_ANA_CSR_BASE + 0x0c) +#define AN8855_RG_QP_CDR_LPF_SETVALUE (AN8855_QP_ANA_CSR_BASE + 0x14) +#define AN8855_RG_QP_CDR_PR_CKREF_DIV1 (AN8855_QP_ANA_CSR_BASE + 0x18) +#define AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE (AN8855_QP_ANA_CSR_BASE + 0x1c) +#define AN8855_RG_QP_CDR_FORCE_IBANDLPF_R_OFF (AN8855_QP_ANA_CSR_BASE + 0x20) +#define AN8855_RG_QP_TX_MODE_16B_EN (AN8855_QP_ANA_CSR_BASE + 0x28) +#define AN8855_RG_QP_PLL_IPLL_DIG_PWR_SEL (AN8855_QP_ANA_CSR_BASE + 0x3c) +#define AN8855_RG_QP_PLL_SDM_ORD (AN8855_QP_ANA_CSR_BASE + 0x40) + +#define AN8855_ETHER_SYS_BASE 0x1028c800 +#define RG_GPHY_AFE_PWD (AN8855_ETHER_SYS_BASE + 0x40) + +#define AN8855_PKG_SEL 0x10000094 +#define PAG_SEL_AN8855H 0x2 + +/* PHY LED Register bitmap of define */ +#define PHY_LED_CTRL_SELECT 0x3e8 +#define PHY_SINGLE_LED_ON_CTRL(i) (0x3e0 + ((i) * 2)) +#define PHY_SINGLE_LED_BLK_CTRL(i) (0x3e1 + ((i) * 2)) +#define PHY_SINGLE_LED_ON_DUR(i) (0x3e9 + ((i) * 2)) +#define PHY_SINGLE_LED_BLK_DUR(i) (0x3ea + ((i) * 2)) + +#define PHY_PMA_CTRL 0x340 + +#define PHY_DEV1F 0x1f + +#define PHY_LED_ON_CTRL(i) (0x24 + ((i) * 2)) +#define LED_ON_EN BIT(15) +#define LED_ON_POL BIT(14) +#define LED_ON_EVT_MASK 0x7f + +/* LED ON Event */ +#define LED_ON_EVT_FORCE BIT(6) +#define LED_ON_EVT_LINK_HD BIT(5) +#define LED_ON_EVT_LINK_FD BIT(4) +#define LED_ON_EVT_LINK_DOWN BIT(3) +#define LED_ON_EVT_LINK_10M BIT(2) +#define LED_ON_EVT_LINK_100M BIT(1) +#define LED_ON_EVT_LINK_1000M BIT(0) + +#define PHY_LED_BLK_CTRL(i) (0x25 + ((i) * 2)) +#define LED_BLK_EVT_MASK 0x3ff +/* LED Blinking Event */ +#define LED_BLK_EVT_FORCE BIT(9) +#define LED_BLK_EVT_10M_RX_ACT BIT(5) +#define LED_BLK_EVT_10M_TX_ACT BIT(4) +#define LED_BLK_EVT_100M_RX_ACT BIT(3) +#define LED_BLK_EVT_100M_TX_ACT BIT(2) +#define LED_BLK_EVT_1000M_RX_ACT BIT(1) +#define LED_BLK_EVT_1000M_TX_ACT BIT(0) + +#define PHY_LED_BCR (0x21) +#define LED_BCR_EXT_CTRL BIT(15) +#define LED_BCR_CLK_EN BIT(3) +#define LED_BCR_TIME_TEST BIT(2) +#define LED_BCR_MODE_MASK 3 +#define LED_BCR_MODE_DISABLE 0 + +#define PHY_LED_ON_DUR 0x22 +#define LED_ON_DUR_MASK 0xffff + +#define PHY_LED_BLK_DUR 0x23 +#define LED_BLK_DUR_MASK 0xffff + +#define PHY_LED_BLINK_DUR_CTRL 0x720 + +/* Definition of LED */ +#define LED_ON_EVENT (LED_ON_EVT_LINK_1000M | \ + LED_ON_EVT_LINK_100M | LED_ON_EVT_LINK_10M |\ + LED_ON_EVT_LINK_HD | LED_ON_EVT_LINK_FD) + +#define LED_BLK_EVENT (LED_BLK_EVT_1000M_TX_ACT | \ + LED_BLK_EVT_1000M_RX_ACT | \ + LED_BLK_EVT_100M_TX_ACT | \ + LED_BLK_EVT_100M_RX_ACT | \ + LED_BLK_EVT_10M_TX_ACT | \ + LED_BLK_EVT_10M_RX_ACT) + +#define LED_FREQ AIR_LED_BLK_DUR_64M + +#define AN8855_NUM_PHYS 5 +#define AN8855_NUM_PORTS 6 +#define AN8855_PHY_ADDR(base, addr) (((base) + (addr)) & 0x1f) + +/* PHY LED Register bitmap of define */ +#define PHY_LED_CTRL_SELECT 0x3e8 +#define PHY_SINGLE_LED_ON_CTRL(i) (0x3e0 + ((i) * 2)) +#define PHY_SINGLE_LED_BLK_CTRL(i) (0x3e1 + ((i) * 2)) +#define PHY_SINGLE_LED_ON_DUR(i) (0x3e9 + ((i) * 2)) +#define PHY_SINGLE_LED_BLK_DUR(i) (0x3ea + ((i) * 2)) + +/* AN8855 LED */ +enum an8855_led_blk_dur { + AIR_LED_BLK_DUR_32M, + AIR_LED_BLK_DUR_64M, + AIR_LED_BLK_DUR_128M, + AIR_LED_BLK_DUR_256M, + AIR_LED_BLK_DUR_512M, + AIR_LED_BLK_DUR_1024M, + AIR_LED_BLK_DUR_LAST +}; + +enum an8855_led_polarity { + LED_LOW, + LED_HIGH, +}; + +enum an8855_led_mode { + AN8855_LED_MODE_DISABLE, + AN8855_LED_MODE_USER_DEFINE, + AN8855_LED_MODE_LAST +}; + +enum phy_led_idx { + P0_LED0, + P0_LED1, + P0_LED2, + P0_LED3, + P1_LED0, + P1_LED1, + P1_LED2, + P1_LED3, + P2_LED0, + P2_LED1, + P2_LED2, + P2_LED3, + P3_LED0, + P3_LED1, + P3_LED2, + P3_LED3, + P4_LED0, + P4_LED1, + P4_LED2, + P4_LED3, + PHY_LED_MAX +}; + +struct an8855_led_cfg { + u16 en; + u8 phy_led_idx; + u16 pol; + u16 on_cfg; + u16 blk_cfg; + u8 led_freq; +}; + +struct an8855_switch_priv { + struct mtk_eth_switch_priv epriv; + struct mii_dev *mdio_bus; + u32 phy_base; +}; + +/* AN8855 Reference Board */ +static const struct an8855_led_cfg led_cfg[] = { +/************************************************************************* + * Enable, LED idx, LED Polarity, LED ON event, LED Blink event LED Freq + ************************************************************************* + */ + /* GPIO0 */ + {1, P4_LED0, LED_HIGH, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, + /* GPIO1 */ + {1, P4_LED1, LED_HIGH, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, + /* GPIO2 */ + {1, P0_LED0, LED_HIGH, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, + /* GPIO3 */ + {1, P0_LED1, LED_HIGH, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, + /* GPIO4 */ + {1, P1_LED0, LED_LOW, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, + /* GPIO5 */ + {1, P1_LED1, LED_LOW, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, + /* GPIO6 */ + {0, PHY_LED_MAX, LED_LOW, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, + /* GPIO7 */ + {0, PHY_LED_MAX, LED_HIGH, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, + /* GPIO8 */ + {0, PHY_LED_MAX, LED_HIGH, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, + /* GPIO9 */ + {1, P2_LED0, LED_HIGH, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, + /* GPIO10 */ + {1, P2_LED1, LED_HIGH, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, + /* GPIO11 */ + {1, P3_LED0, LED_HIGH, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, + /* GPIO12 */ + {1, P3_LED1, LED_HIGH, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, + /* GPIO13 */ + {0, PHY_LED_MAX, LED_HIGH, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, + /* GPIO14 */ + {0, PHY_LED_MAX, LED_HIGH, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, + /* GPIO15 */ + {0, PHY_LED_MAX, LED_HIGH, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, + /* GPIO16 */ + {0, PHY_LED_MAX, LED_HIGH, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, + /* GPIO17 */ + {0, PHY_LED_MAX, LED_HIGH, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, + /* GPIO18 */ + {0, PHY_LED_MAX, LED_HIGH, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, + /* GPIO19 */ + {0, PHY_LED_MAX, LED_LOW, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, + /* GPIO20 */ + {0, PHY_LED_MAX, LED_LOW, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, +}; + +static int __an8855_reg_read(struct mtk_eth_priv *priv, u8 phy_base, u32 reg, u32 *data) +{ + int ret, low_word, high_word; + + ret = mtk_mii_write(priv, phy_base, 0x1f, 0x4); + if (ret) + return ret; + + ret = mtk_mii_write(priv, phy_base, 0x10, 0); + if (ret) + return ret; + + ret = mtk_mii_write(priv, phy_base, 0x15, ((reg >> 16) & 0xFFFF)); + if (ret) + return ret; + + ret = mtk_mii_write(priv, phy_base, 0x16, (reg & 0xFFFF)); + if (ret) + return ret; + + low_word = mtk_mii_read(priv, phy_base, 0x18); + if (low_word < 0) + return low_word; + + high_word = mtk_mii_read(priv, phy_base, 0x17); + if (high_word < 0) + return high_word; + + ret = mtk_mii_write(priv, phy_base, 0x1f, 0); + if (ret) + return ret; + + ret = mtk_mii_write(priv, phy_base, 0x10, 0); + if (ret) + return ret; + + if (data) + *data = ((u32)high_word << 16) | (low_word & 0xffff); + + return 0; +} + +static int an8855_reg_read(struct an8855_switch_priv *priv, u32 reg, u32 *data) +{ + return __an8855_reg_read(priv->epriv.eth, priv->phy_base, reg, data); +} + +static int an8855_reg_write(struct an8855_switch_priv *priv, u32 reg, u32 data) +{ + int ret; + + ret = mtk_mii_write(priv->epriv.eth, priv->phy_base, 0x1f, 0x4); + if (ret) + return ret; + + ret = mtk_mii_write(priv->epriv.eth, priv->phy_base, 0x10, 0); + if (ret) + return ret; + + ret = mtk_mii_write(priv->epriv.eth, priv->phy_base, 0x11, + ((reg >> 16) & 0xFFFF)); + if (ret) + return ret; + + ret = mtk_mii_write(priv->epriv.eth, priv->phy_base, 0x12, + (reg & 0xFFFF)); + if (ret) + return ret; + + ret = mtk_mii_write(priv->epriv.eth, priv->phy_base, 0x13, + ((data >> 16) & 0xFFFF)); + if (ret) + return ret; + + ret = mtk_mii_write(priv->epriv.eth, priv->phy_base, 0x14, + (data & 0xFFFF)); + if (ret) + return ret; + + ret = mtk_mii_write(priv->epriv.eth, priv->phy_base, 0x1f, 0); + if (ret) + return ret; + + ret = mtk_mii_write(priv->epriv.eth, priv->phy_base, 0x10, 0); + if (ret) + return ret; + + return 0; +} + +static int an8855_phy_cl45_read(struct an8855_switch_priv *priv, int port, + int devad, int regnum, u16 *data) +{ + u16 phy_addr = AN8855_PHY_ADDR(priv->phy_base, port); + + *data = mtk_mmd_ind_read(priv->epriv.eth, phy_addr, devad, regnum); + + return 0; +} + +static int an8855_phy_cl45_write(struct an8855_switch_priv *priv, int port, + int devad, int regnum, u16 data) +{ + u16 phy_addr = AN8855_PHY_ADDR(priv->phy_base, port); + + mtk_mmd_ind_write(priv->epriv.eth, phy_addr, devad, regnum, data); + + return 0; +} + +static int an8855_port_sgmii_init(struct an8855_switch_priv *priv, u32 port) +{ + u32 val = 0; + + if (port != 5) { + printf("an8855: port %d is not a SGMII port\n", port); + return -EINVAL; + } + + /* PLL */ + an8855_reg_read(priv, AN8855_QP_DIG_MODE_CTRL_1, &val); + val &= ~(0x3 << 2); + val |= (0x1 << 2); + an8855_reg_write(priv, AN8855_QP_DIG_MODE_CTRL_1, val); + + /* PLL - LPF */ + an8855_reg_read(priv, AN8855_PLL_CTRL_2, &val); + val &= ~(0x3 << 0); + val |= (0x1 << 0); + val &= ~(0x7 << 2); + val |= (0x5 << 2); + val &= ~GENMASK(7, 6); + val &= ~(0x7 << 8); + val |= (0x3 << 8); + val |= BIT(29); + val &= ~GENMASK(13, 12); + an8855_reg_write(priv, AN8855_PLL_CTRL_2, val); + + /* PLL - ICO */ + an8855_reg_read(priv, AN8855_PLL_CTRL_4, &val); + val |= BIT(2); + an8855_reg_write(priv, AN8855_PLL_CTRL_4, val); + + an8855_reg_read(priv, AN8855_PLL_CTRL_2, &val); + val &= ~BIT(14); + an8855_reg_write(priv, AN8855_PLL_CTRL_2, val); + + /* PLL - CHP */ + an8855_reg_read(priv, AN8855_PLL_CTRL_2, &val); + val &= ~(0xf << 16); + val |= (0x6 << 16); + an8855_reg_write(priv, AN8855_PLL_CTRL_2, val); + + /* PLL - PFD */ + an8855_reg_read(priv, AN8855_PLL_CTRL_2, &val); + val &= ~(0x3 << 20); + val |= (0x1 << 20); + val &= ~(0x3 << 24); + val |= (0x1 << 24); + val &= ~BIT(26); + an8855_reg_write(priv, AN8855_PLL_CTRL_2, val); + + /* PLL - POSTDIV */ + an8855_reg_read(priv, AN8855_PLL_CTRL_2, &val); + val |= BIT(22); + val &= ~BIT(27); + val &= ~BIT(28); + an8855_reg_write(priv, AN8855_PLL_CTRL_2, val); + + /* PLL - SDM */ + an8855_reg_read(priv, AN8855_PLL_CTRL_4, &val); + val &= ~GENMASK(4, 3); + an8855_reg_write(priv, AN8855_PLL_CTRL_4, val); + + an8855_reg_read(priv, AN8855_PLL_CTRL_2, &val); + val &= ~BIT(30); + an8855_reg_write(priv, AN8855_PLL_CTRL_2, val); + + an8855_reg_read(priv, AN8855_SS_LCPLL_PWCTL_SETTING_2, &val); + val &= ~(0x3 << 16); + val |= (0x1 << 16); + an8855_reg_write(priv, AN8855_SS_LCPLL_PWCTL_SETTING_2, val); + + an8855_reg_write(priv, AN8855_SS_LCPLL_TDC_FLT_2, 0x7a000000); + an8855_reg_write(priv, AN8855_SS_LCPLL_TDC_PCW_1, 0x7a000000); + + an8855_reg_read(priv, AN8855_SS_LCPLL_TDC_FLT_5, &val); + val &= ~BIT(24); + an8855_reg_write(priv, AN8855_SS_LCPLL_TDC_FLT_5, val); + + an8855_reg_read(priv, AN8855_PLL_CK_CTRL_0, &val); + val &= ~BIT(8); + an8855_reg_write(priv, AN8855_PLL_CK_CTRL_0, val); + + /* PLL - SS */ + an8855_reg_read(priv, AN8855_PLL_CTRL_3, &val); + val &= ~GENMASK(15, 0); + an8855_reg_write(priv, AN8855_PLL_CTRL_3, val); + + an8855_reg_read(priv, AN8855_PLL_CTRL_4, &val); + val &= ~GENMASK(1, 0); + an8855_reg_write(priv, AN8855_PLL_CTRL_4, val); + + an8855_reg_read(priv, AN8855_PLL_CTRL_3, &val); + val &= ~GENMASK(31, 16); + an8855_reg_write(priv, AN8855_PLL_CTRL_3, val); + + /* PLL - TDC */ + an8855_reg_read(priv, AN8855_PLL_CK_CTRL_0, &val); + val &= ~BIT(9); + an8855_reg_write(priv, AN8855_PLL_CK_CTRL_0, val); + + an8855_reg_read(priv, AN8855_RG_QP_PLL_SDM_ORD, &val); + val |= BIT(3); + val |= BIT(4); + an8855_reg_write(priv, AN8855_RG_QP_PLL_SDM_ORD, val); + + an8855_reg_read(priv, AN8855_RG_QP_RX_DAC_EN, &val); + val &= ~(0x3 << 16); + val |= (0x2 << 16); + an8855_reg_write(priv, AN8855_RG_QP_RX_DAC_EN, val); + + /* TCL Disable (only for Co-SIM) */ + an8855_reg_read(priv, AN8855_PON_RXFEDIG_CTRL_0, &val); + val &= ~BIT(12); + an8855_reg_write(priv, AN8855_PON_RXFEDIG_CTRL_0, val); + + /* TX Init */ + an8855_reg_read(priv, AN8855_RG_QP_TX_MODE_16B_EN, &val); + val &= ~BIT(0); + val &= ~(0xffff << 16); + val |= (0x4 << 16); + an8855_reg_write(priv, AN8855_RG_QP_TX_MODE_16B_EN, val); + + /* RX Control */ + an8855_reg_read(priv, AN8855_RG_QP_RXAFE_RESERVE, &val); + val |= BIT(11); + an8855_reg_write(priv, AN8855_RG_QP_RXAFE_RESERVE, val); + + an8855_reg_read(priv, AN8855_RG_QP_CDR_LPF_MJV_LIM, &val); + val &= ~(0x3 << 4); + val |= (0x1 << 4); + an8855_reg_write(priv, AN8855_RG_QP_CDR_LPF_MJV_LIM, val); + + an8855_reg_read(priv, AN8855_RG_QP_CDR_LPF_SETVALUE, &val); + val &= ~(0xf << 25); + val |= (0x1 << 25); + val &= ~(0x7 << 29); + val |= (0x3 << 29); + an8855_reg_write(priv, AN8855_RG_QP_CDR_LPF_SETVALUE, val); + + an8855_reg_read(priv, AN8855_RG_QP_CDR_PR_CKREF_DIV1, &val); + val &= ~(0x1f << 8); + val |= (0xf << 8); + an8855_reg_write(priv, AN8855_RG_QP_CDR_PR_CKREF_DIV1, val); + + an8855_reg_read(priv, AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE, &val); + val &= ~(0x3f << 0); + val |= (0x19 << 0); + val &= ~BIT(6); + an8855_reg_write(priv, AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE, val); + + an8855_reg_read(priv, AN8855_RG_QP_CDR_FORCE_IBANDLPF_R_OFF, &val); + val &= ~(0x7f << 6); + val |= (0x21 << 6); + val &= ~(0x3 << 16); + val |= (0x2 << 16); + val &= ~BIT(13); + an8855_reg_write(priv, AN8855_RG_QP_CDR_FORCE_IBANDLPF_R_OFF, val); + + an8855_reg_read(priv, AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE, &val); + val &= ~BIT(30); + an8855_reg_write(priv, AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE, val); + + an8855_reg_read(priv, AN8855_RG_QP_CDR_PR_CKREF_DIV1, &val); + val &= ~(0x7 << 24); + val |= (0x4 << 24); + an8855_reg_write(priv, AN8855_RG_QP_CDR_PR_CKREF_DIV1, val); + + an8855_reg_read(priv, AN8855_PLL_CTRL_0, &val); + val |= BIT(0); + an8855_reg_write(priv, AN8855_PLL_CTRL_0, val); + + an8855_reg_read(priv, AN8855_RX_CTRL_26, &val); + val &= ~BIT(23); + val |= BIT(26); + an8855_reg_write(priv, AN8855_RX_CTRL_26, val); + + an8855_reg_read(priv, AN8855_RX_DLY_0, &val); + val &= ~(0xff << 0); + val |= (0x6f << 0); + val |= GENMASK(13, 8); + an8855_reg_write(priv, AN8855_RX_DLY_0, val); + + an8855_reg_read(priv, AN8855_RX_CTRL_42, &val); + val &= ~(0x1fff << 0); + val |= (0x150 << 0); + an8855_reg_write(priv, AN8855_RX_CTRL_42, val); + + an8855_reg_read(priv, AN8855_RX_CTRL_2, &val); + val &= ~(0x1fff << 16); + val |= (0x150 << 16); + an8855_reg_write(priv, AN8855_RX_CTRL_2, val); + + an8855_reg_read(priv, AN8855_PON_RXFEDIG_CTRL_9, &val); + val &= ~(0x7 << 0); + val |= (0x1 << 0); + an8855_reg_write(priv, AN8855_PON_RXFEDIG_CTRL_9, val); + + an8855_reg_read(priv, AN8855_RX_CTRL_8, &val); + val &= ~(0xfff << 16); + val |= (0x200 << 16); + val &= ~(0x7fff << 14); + val |= (0xfff << 14); + an8855_reg_write(priv, AN8855_RX_CTRL_8, val); + + /* Frequency memter */ + an8855_reg_read(priv, AN8855_RX_CTRL_5, &val); + val &= ~(0xfffff << 10); + val |= (0x10 << 10); + an8855_reg_write(priv, AN8855_RX_CTRL_5, val); + + an8855_reg_read(priv, AN8855_RX_CTRL_6, &val); + val &= ~(0xfffff << 0); + val |= (0x64 << 0); + an8855_reg_write(priv, AN8855_RX_CTRL_6, val); + + an8855_reg_read(priv, AN8855_RX_CTRL_7, &val); + val &= ~(0xfffff << 0); + val |= (0x2710 << 0); + an8855_reg_write(priv, AN8855_RX_CTRL_7, val); + + /* PCS Init */ + an8855_reg_read(priv, AN8855_RG_HSGMII_PCS_CTROL_1, &val); + val &= ~BIT(30); + an8855_reg_write(priv, AN8855_RG_HSGMII_PCS_CTROL_1, val); + + /* Rate Adaption */ + an8855_reg_read(priv, AN8855_RATE_ADP_P0_CTRL_0, &val); + val &= ~BIT(31); + an8855_reg_write(priv, AN8855_RATE_ADP_P0_CTRL_0, val); + + an8855_reg_read(priv, AN8855_RG_RATE_ADAPT_CTRL_0, &val); + val |= BIT(0); + val |= BIT(4); + val |= GENMASK(27, 26); + an8855_reg_write(priv, AN8855_RG_RATE_ADAPT_CTRL_0, val); + + /* Disable AN */ + an8855_reg_read(priv, AN8855_SGMII_REG_AN0, &val); + val &= ~BIT(12); + an8855_reg_write(priv, AN8855_SGMII_REG_AN0, val); + + /* Force Speed */ + an8855_reg_read(priv, AN8855_SGMII_STS_CTRL_0, &val); + val |= BIT(2); + val |= GENMASK(5, 4); + an8855_reg_write(priv, AN8855_SGMII_STS_CTRL_0, val); + + /* bypass flow control to MAC */ + an8855_reg_write(priv, AN8855_MSG_RX_LIK_STS_0, 0x01010107); + an8855_reg_write(priv, AN8855_MSG_RX_LIK_STS_2, 0x00000EEF); + + return 0; +} + +static void an8855_led_set_usr_def(struct an8855_switch_priv *priv, u8 entity, + enum an8855_led_polarity pol, u16 on_evt, + u16 blk_evt, u8 led_freq) +{ + u32 cl45_data; + + if (pol == LED_HIGH) + on_evt |= LED_ON_POL; + else + on_evt &= ~LED_ON_POL; + + /* LED on event */ + an8855_phy_cl45_write(priv, (entity / 4), 0x1e, + PHY_SINGLE_LED_ON_CTRL(entity % 4), + on_evt | LED_ON_EN); + + /* LED blink event */ + an8855_phy_cl45_write(priv, (entity / 4), 0x1e, + PHY_SINGLE_LED_BLK_CTRL(entity % 4), + blk_evt); + + /* LED freq */ + switch (led_freq) { + case AIR_LED_BLK_DUR_32M: + cl45_data = 0x30e; + break; + + case AIR_LED_BLK_DUR_64M: + cl45_data = 0x61a; + break; + + case AIR_LED_BLK_DUR_128M: + cl45_data = 0xc35; + break; + + case AIR_LED_BLK_DUR_256M: + cl45_data = 0x186a; + break; + + case AIR_LED_BLK_DUR_512M: + cl45_data = 0x30d4; + break; + + case AIR_LED_BLK_DUR_1024M: + cl45_data = 0x61a8; + break; + + default: + cl45_data = 0; + break; + } + + an8855_phy_cl45_write(priv, (entity / 4), 0x1e, + PHY_SINGLE_LED_BLK_DUR(entity % 4), + cl45_data); + + an8855_phy_cl45_write(priv, (entity / 4), 0x1e, + PHY_SINGLE_LED_ON_DUR(entity % 4), + (cl45_data >> 1)); + + /* Disable DATA & BAD_SSD for port LED blink behavior */ + cl45_data = mtk_mmd_ind_read(priv->epriv.eth, (entity / 4), 0x1e, PHY_PMA_CTRL); + cl45_data &= ~BIT(0); + cl45_data &= ~BIT(15); + an8855_phy_cl45_write(priv, (entity / 4), 0x1e, PHY_PMA_CTRL, cl45_data); +} + +static int an8855_led_set_mode(struct an8855_switch_priv *priv, u8 mode) +{ + u16 cl45_data; + + an8855_phy_cl45_read(priv, 0, 0x1f, PHY_LED_BCR, &cl45_data); + + switch (mode) { + case AN8855_LED_MODE_DISABLE: + cl45_data &= ~LED_BCR_EXT_CTRL; + cl45_data &= ~LED_BCR_MODE_MASK; + cl45_data |= LED_BCR_MODE_DISABLE; + break; + + case AN8855_LED_MODE_USER_DEFINE: + cl45_data |= LED_BCR_EXT_CTRL; + cl45_data |= LED_BCR_CLK_EN; + break; + + default: + printf("an8855: LED mode%d is not supported!\n", mode); + return -EINVAL; + } + + an8855_phy_cl45_write(priv, 0, 0x1f, PHY_LED_BCR, cl45_data); + + return 0; +} + +static int an8855_led_set_state(struct an8855_switch_priv *priv, u8 entity, + u8 state) +{ + u16 cl45_data = 0; + + /* Change to per port contorl */ + an8855_phy_cl45_read(priv, (entity / 4), 0x1e, PHY_LED_CTRL_SELECT, + &cl45_data); + + if (state == 1) + cl45_data |= (1 << (entity % 4)); + else + cl45_data &= ~(1 << (entity % 4)); + + an8855_phy_cl45_write(priv, (entity / 4), 0x1e, PHY_LED_CTRL_SELECT, + cl45_data); + + /* LED enable setting */ + an8855_phy_cl45_read(priv, (entity / 4), 0x1e, + PHY_SINGLE_LED_ON_CTRL(entity % 4), &cl45_data); + + if (state == 1) + cl45_data |= LED_ON_EN; + else + cl45_data &= ~LED_ON_EN; + + an8855_phy_cl45_write(priv, (entity / 4), 0x1e, + PHY_SINGLE_LED_ON_CTRL(entity % 4), cl45_data); + + return 0; +} + +static int an8855_led_init(struct an8855_switch_priv *priv) +{ + u32 val, id, tmp_id = 0; + int ret; + + ret = an8855_led_set_mode(priv, AN8855_LED_MODE_USER_DEFINE); + if (ret) { + printf("an8855: led_set_mode failed with %d!\n", ret); + return ret; + } + + for (id = 0; id < ARRAY_SIZE(led_cfg); id++) { + ret = an8855_led_set_state(priv, led_cfg[id].phy_led_idx, + led_cfg[id].en); + if (ret != 0) { + printf("an8855: led_set_state failed with %d!\n", ret); + return ret; + } + + if (led_cfg[id].en == 1) { + an8855_led_set_usr_def(priv, + led_cfg[id].phy_led_idx, + led_cfg[id].pol, + led_cfg[id].on_cfg, + led_cfg[id].blk_cfg, + led_cfg[id].led_freq); + } + } + + /* Setting for System LED & Loop LED */ + an8855_reg_write(priv, AN8855_RG_GPIO_OE, 0x0); + an8855_reg_write(priv, AN8855_RG_GPIO_CTRL, 0x0); + an8855_reg_write(priv, AN8855_RG_GPIO_L_INV, 0); + + an8855_reg_write(priv, AN8855_RG_GPIO_CTRL, 0x1001); + an8855_reg_read(priv, AN8855_RG_GPIO_DATA, &val); + val |= GENMASK(3, 1); + val &= ~(BIT(0)); + val &= ~(BIT(6)); + an8855_reg_write(priv, AN8855_RG_GPIO_DATA, val); + + an8855_reg_read(priv, AN8855_RG_GPIO_OE, &val); + val |= 0x41; + an8855_reg_write(priv, AN8855_RG_GPIO_OE, val); + + /* Mapping between GPIO & LED */ + val = 0; + for (id = 0; id < ARRAY_SIZE(led_cfg); id++) { + /* Skip GPIO6, due to GPIO6 does not support PORT LED */ + if (id == 6) + continue; + + if (led_cfg[id].en == 1) { + if (id < 7) + val |= led_cfg[id].phy_led_idx << ((id % 4) * 8); + else + val |= led_cfg[id].phy_led_idx << (((id - 1) % 4) * 8); + } + + if (id < 7) + tmp_id = id; + else + tmp_id = id - 1; + + if ((tmp_id % 4) == 0x3) { + an8855_reg_write(priv, + AN8855_RG_GPIO_LED_SEL(tmp_id / 4), + val); + val = 0; + } + } + + /* Turn on LAN LED mode */ + val = 0; + for (id = 0; id < ARRAY_SIZE(led_cfg); id++) { + if (led_cfg[id].en == 1) + val |= 0x1 << id; + } + an8855_reg_write(priv, AN8855_RG_GPIO_LED_MODE, val); + + /* Force clear blink pulse for per port LED */ + an8855_phy_cl45_write(priv, 0, 0x1f, PHY_LED_BLINK_DUR_CTRL, 0x1f); + udelay(1000); + an8855_phy_cl45_write(priv, 0, 0x1f, PHY_LED_BLINK_DUR_CTRL, 0); + + return 0; +} + +static void an8855_port_isolation(struct an8855_switch_priv *priv) +{ + u32 i; + + for (i = 0; i < AN8855_NUM_PORTS; i++) { + /* Set port matrix mode */ + if (i != 5) + an8855_reg_write(priv, AN8855_PORTMATRIX_REG(i), 0x20); + else + an8855_reg_write(priv, AN8855_PORTMATRIX_REG(i), 0x1f); + + /* Set port mode to user port */ + an8855_reg_write(priv, AN8855_PVC(i), + (0x8100 << AN8855_STAG_VPID_S) | + (VLAN_ATTR_USER << AN8855_VLAN_ATTR_S)); + } +} + +static void an8855_mac_control(struct mtk_eth_switch_priv *swpriv, bool enable) +{ + struct an8855_switch_priv *priv = (struct an8855_switch_priv *)swpriv; + u32 pmcr = AN8855_FORCE_MODE_LNK; + + if (enable) + pmcr = AN8855_FORCE_MODE; + + an8855_reg_write(priv, AN8855_PMCR_REG(5), pmcr); +} + +static int an8855_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) +{ + struct an8855_switch_priv *priv = bus->priv; + + if (devad < 0) + return mtk_mii_read(priv->epriv.eth, addr, reg); + + return mtk_mmd_ind_read(priv->epriv.eth, addr, devad, reg); +} + +static int an8855_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, + u16 val) +{ + struct an8855_switch_priv *priv = bus->priv; + + if (devad < 0) + return mtk_mii_write(priv->epriv.eth, addr, reg, val); + + return mtk_mmd_ind_write(priv->epriv.eth, addr, devad, reg, val); +} + +static int an8855_mdio_register(struct an8855_switch_priv *priv) +{ + struct mii_dev *mdio_bus = mdio_alloc(); + int ret; + + if (!mdio_bus) + return -ENOMEM; + + mdio_bus->read = an8855_mdio_read; + mdio_bus->write = an8855_mdio_write; + snprintf(mdio_bus->name, sizeof(mdio_bus->name), priv->epriv.sw->name); + + mdio_bus->priv = priv; + + ret = mdio_register(mdio_bus); + if (ret) { + mdio_free(mdio_bus); + return ret; + } + + priv->mdio_bus = mdio_bus; + + return 0; +} + +static int an8855_setup(struct mtk_eth_switch_priv *swpriv) +{ + struct an8855_switch_priv *priv = (struct an8855_switch_priv *)swpriv; + u16 phy_addr, phy_val; + u32 i, id, val = 0; + int ret; + + priv->phy_base = 1; + + /* Turn off PHYs */ + for (i = 0; i < AN8855_NUM_PHYS; i++) { + phy_addr = AN8855_PHY_ADDR(priv->phy_base, i); + phy_val = mtk_mii_read(priv->epriv.eth, phy_addr, MII_BMCR); + phy_val |= BMCR_PDOWN; + mtk_mii_write(priv->epriv.eth, phy_addr, MII_BMCR, phy_val); + } + + /* Force MAC link down before reset */ + an8855_reg_write(priv, AN8855_PMCR_REG(5), AN8855_FORCE_MODE_LNK); + + /* Switch soft reset */ + an8855_reg_write(priv, AN8855_SYS_CTRL_REG, AN8855_SW_SYS_RST); + mdelay(100); + + an8855_reg_read(priv, AN8855_PKG_SEL, &val); + if ((val & 0x7) == PAG_SEL_AN8855H) { + /* Release power down */ + an8855_reg_write(priv, RG_GPHY_AFE_PWD, 0x0); + + /* Invert for LED activity change */ + an8855_reg_read(priv, AN8855_RG_GPIO_L_INV, &val); + for (id = 0; id < ARRAY_SIZE(led_cfg); id++) { + if (led_cfg[id].pol == LED_HIGH && led_cfg[id].en == 1) + val |= 0x1 << id; + } + an8855_reg_write(priv, AN8855_RG_GPIO_L_INV, (val | 0x1)); + + /* MCU NOP CMD */ + an8855_reg_write(priv, AN8855_RG_GDMP_RAM, 0x846); + an8855_reg_write(priv, AN8855_RG_GDMP_RAM + 4, 0x4a); + + /* Enable MCU */ + an8855_reg_read(priv, AN8855_RG_CLK_CPU_ICG, &val); + an8855_reg_write(priv, AN8855_RG_CLK_CPU_ICG, + val | AN8855_MCU_ENABLE); + udelay(1000); + + /* Disable MCU watchdog */ + an8855_reg_read(priv, AN8855_RG_TIMER_CTL, &val); + an8855_reg_write(priv, AN8855_RG_TIMER_CTL, + (val & (~AN8855_WDOG_ENABLE))); + + /* LED settings for T830 reference board */ + ret = an8855_led_init(priv); + if (ret < 0) { + printf("an8855: an8855_led_init failed with %d\n", ret); + return ret; + } + } + + switch (priv->epriv.phy_interface) { + case PHY_INTERFACE_MODE_2500BASEX: + an8855_port_sgmii_init(priv, 5); + break; + + default: + break; + } + + an8855_reg_read(priv, AN8855_CKGCR, &val); + val &= ~(0x3); + an8855_reg_write(priv, AN8855_CKGCR, val); + + /* Enable port isolation to block inter-port communication */ + an8855_port_isolation(priv); + + /* Turn on PHYs */ + for (i = 0; i < AN8855_NUM_PHYS; i++) { + phy_addr = AN8855_PHY_ADDR(priv->phy_base, i); + phy_val = mtk_mii_read(priv->epriv.eth, phy_addr, MII_BMCR); + phy_val &= ~BMCR_PDOWN; + mtk_mii_write(priv->epriv.eth, phy_addr, MII_BMCR, phy_val); + } + + return an8855_mdio_register(priv); +} + +static int an8855_cleanup(struct mtk_eth_switch_priv *swpriv) +{ + struct an8855_switch_priv *priv = (struct an8855_switch_priv *)swpriv; + + mdio_unregister(priv->mdio_bus); + + return 0; +} + +static int an8855_detect(struct mtk_eth_priv *priv) +{ + int ret; + u32 val; + + ret = __an8855_reg_read(priv, 1, 0x10005000, &val); + if (ret) + return ret; + + if (val == 0x8855) + return 0; + + return -ENODEV; +} + +MTK_ETH_SWITCH(an8855) = { + .name = "an8855", + .desc = "Airoha AN8855", + .priv_size = sizeof(struct an8855_switch_priv), + .reset_wait_time = 100, + + .detect = an8855_detect, + .setup = an8855_setup, + .cleanup = an8855_cleanup, + .mac_control = an8855_mac_control, +}; diff --git a/drivers/net/mtk_eth/mt7530.c b/drivers/net/mtk_eth/mt7530.c new file mode 100644 index 00000000000..3065d35e126 --- /dev/null +++ b/drivers/net/mtk_eth/mt7530.c @@ -0,0 +1,281 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 MediaTek Inc. + * + * Author: Weijie Gao <weijie.gao@mediatek.com> + * Author: Mark Lee <mark-mc.lee@mediatek.com> + */ + +#include <miiphy.h> +#include <linux/delay.h> +#include <linux/mdio.h> +#include <linux/mii.h> +#include "mtk_eth.h" +#include "mt753x.h" + +#define CHIP_REV 0x7ffc +#define CHIP_NAME_S 16 +#define CHIP_NAME_M 0xffff0000 +#define CHIP_REV_S 0 +#define CHIP_REV_M 0x0f + +static void mt7530_core_reg_write(struct mt753x_switch_priv *priv, u32 reg, + u32 val) +{ + u8 phy_addr = MT753X_PHY_ADDR(priv->phy_base, 0); + + mtk_mmd_ind_write(priv->epriv.eth, phy_addr, 0x1f, reg, val); +} + +static int mt7530_pad_clk_setup(struct mt753x_switch_priv *priv, int mode) +{ + u32 ncpo1, ssc_delta; + + switch (mode) { + case PHY_INTERFACE_MODE_RGMII: + ncpo1 = 0x0c80; + ssc_delta = 0x87; + break; + + default: + printf("error: xMII mode %d is not supported\n", mode); + return -EINVAL; + } + + /* Disable MT7530 core clock */ + mt7530_core_reg_write(priv, CORE_TRGMII_GSW_CLK_CG, 0); + + /* Disable MT7530 PLL */ + mt7530_core_reg_write(priv, CORE_GSWPLL_GRP1, + (2 << RG_GSWPLL_POSDIV_200M_S) | + (32 << RG_GSWPLL_FBKDIV_200M_S)); + + /* For MT7530 core clock = 500Mhz */ + mt7530_core_reg_write(priv, CORE_GSWPLL_GRP2, + (1 << RG_GSWPLL_POSDIV_500M_S) | + (25 << RG_GSWPLL_FBKDIV_500M_S)); + + /* Enable MT7530 PLL */ + mt7530_core_reg_write(priv, CORE_GSWPLL_GRP1, + (2 << RG_GSWPLL_POSDIV_200M_S) | + (32 << RG_GSWPLL_FBKDIV_200M_S) | + RG_GSWPLL_EN_PRE); + + udelay(20); + + mt7530_core_reg_write(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); + + /* Setup the MT7530 TRGMII Tx Clock */ + mt7530_core_reg_write(priv, CORE_PLL_GROUP5, ncpo1); + mt7530_core_reg_write(priv, CORE_PLL_GROUP6, 0); + mt7530_core_reg_write(priv, CORE_PLL_GROUP10, ssc_delta); + mt7530_core_reg_write(priv, CORE_PLL_GROUP11, ssc_delta); + mt7530_core_reg_write(priv, CORE_PLL_GROUP4, RG_SYSPLL_DDSFBK_EN | + RG_SYSPLL_BIAS_EN | RG_SYSPLL_BIAS_LPF_EN); + + mt7530_core_reg_write(priv, CORE_PLL_GROUP2, + RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN | + (1 << RG_SYSPLL_POSDIV_S)); + + mt7530_core_reg_write(priv, CORE_PLL_GROUP7, + RG_LCDDS_PCW_NCPO_CHG | (3 << RG_LCCDS_C_S) | + RG_LCDDS_PWDB | RG_LCDDS_ISO_EN); + + /* Enable MT7530 core clock */ + mt7530_core_reg_write(priv, CORE_TRGMII_GSW_CLK_CG, + REG_GSWCK_EN | REG_TRGMIICK_EN); + + return 0; +} + +static void mt7530_mac_control(struct mtk_eth_switch_priv *swpriv, bool enable) +{ + struct mt753x_switch_priv *priv = (struct mt753x_switch_priv *)swpriv; + u32 pmcr = FORCE_MODE; + + if (enable) + pmcr = priv->pmcr; + + mt753x_reg_write(priv, PMCR_REG(6), pmcr); +} + +static int mt7530_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) +{ + struct mt753x_switch_priv *priv = bus->priv; + + if (devad < 0) + return mtk_mii_read(priv->epriv.eth, addr, reg); + + return mtk_mmd_ind_read(priv->epriv.eth, addr, devad, reg); +} + +static int mt7530_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, + u16 val) +{ + struct mt753x_switch_priv *priv = bus->priv; + + if (devad < 0) + return mtk_mii_write(priv->epriv.eth, addr, reg, val); + + return mtk_mmd_ind_write(priv->epriv.eth, addr, devad, reg, val); +} + +static int mt7530_mdio_register(struct mt753x_switch_priv *priv) +{ + struct mii_dev *mdio_bus = mdio_alloc(); + int ret; + + if (!mdio_bus) + return -ENOMEM; + + mdio_bus->read = mt7530_mdio_read; + mdio_bus->write = mt7530_mdio_write; + snprintf(mdio_bus->name, sizeof(mdio_bus->name), priv->epriv.sw->name); + + mdio_bus->priv = priv; + + ret = mdio_register(mdio_bus); + if (ret) { + mdio_free(mdio_bus); + return ret; + } + + priv->mdio_bus = mdio_bus; + + return 0; +} + +static int mt7530_setup(struct mtk_eth_switch_priv *swpriv) +{ + struct mt753x_switch_priv *priv = (struct mt753x_switch_priv *)swpriv; + u16 phy_addr, phy_val; + u32 i, val, txdrv; + + priv->smi_addr = MT753X_DFL_SMI_ADDR; + priv->reg_read = mt753x_mdio_reg_read; + priv->reg_write = mt753x_mdio_reg_write; + + if (!MTK_HAS_CAPS(priv->epriv.soc->caps, MTK_TRGMII_MT7621_CLK)) { + /* Select 250MHz clk for RGMII mode */ + mtk_ethsys_rmw(priv->epriv.eth, ETHSYS_CLKCFG0_REG, + ETHSYS_TRGMII_CLK_SEL362_5, 0); + + txdrv = 8; + } else { + txdrv = 4; + } + + /* Modify HWTRAP first to allow direct access to internal PHYs */ + mt753x_reg_read(priv, HWTRAP_REG, &val); + val |= CHG_TRAP; + val &= ~C_MDIO_BPS; + mt753x_reg_write(priv, MHWTRAP_REG, val); + + /* Calculate the phy base address */ + val = ((val & SMI_ADDR_M) >> SMI_ADDR_S) << 3; + priv->phy_base = (val | 0x7) + 1; + + /* Turn off PHYs */ + for (i = 0; i < MT753X_NUM_PHYS; i++) { + phy_addr = MT753X_PHY_ADDR(priv->phy_base, i); + phy_val = mtk_mii_read(priv->epriv.eth, phy_addr, MII_BMCR); + phy_val |= BMCR_PDOWN; + mtk_mii_write(priv->epriv.eth, phy_addr, MII_BMCR, phy_val); + } + + /* Force MAC link down before reset */ + mt753x_reg_write(priv, PMCR_REG(5), FORCE_MODE); + mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE); + + /* MT7530 reset */ + mt753x_reg_write(priv, SYS_CTRL_REG, SW_SYS_RST | SW_REG_RST); + udelay(100); + + val = (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) | + MAC_MODE | FORCE_MODE | + MAC_TX_EN | MAC_RX_EN | + BKOFF_EN | BACKPR_EN | + (SPEED_1000M << FORCE_SPD_S) | + FORCE_DPX | FORCE_LINK; + + /* MT7530 Port6: Forced 1000M/FD, FC disabled */ + priv->pmcr = val; + + /* MT7530 Port5: Forced link down */ + mt753x_reg_write(priv, PMCR_REG(5), FORCE_MODE); + + /* Keep MAC link down before starting eth */ + mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE); + + /* MT7530 Port6: Set to RGMII */ + mt753x_reg_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_M, P6_INTF_MODE_RGMII); + + /* Hardware Trap: Enable Port6, Disable Port5 */ + mt753x_reg_read(priv, HWTRAP_REG, &val); + val |= CHG_TRAP | LOOPDET_DIS | P5_INTF_DIS | + (P5_INTF_SEL_GMAC5 << P5_INTF_SEL_S) | + (P5_INTF_MODE_RGMII << P5_INTF_MODE_S); + val &= ~(C_MDIO_BPS | P6_INTF_DIS); + mt753x_reg_write(priv, MHWTRAP_REG, val); + + /* Setup switch core pll */ + mt7530_pad_clk_setup(priv, priv->epriv.phy_interface); + + /* Lower Tx Driving for TRGMII path */ + for (i = 0 ; i < NUM_TRGMII_CTRL ; i++) + mt753x_reg_write(priv, MT7530_TRGMII_TD_ODT(i), + (txdrv << TD_DM_DRVP_S) | + (txdrv << TD_DM_DRVN_S)); + + for (i = 0 ; i < NUM_TRGMII_CTRL; i++) + mt753x_reg_rmw(priv, MT7530_TRGMII_RD(i), RD_TAP_M, 16); + + /* Enable port isolation to block inter-port communication */ + mt753x_port_isolation(priv); + + /* Turn on PHYs */ + for (i = 0; i < MT753X_NUM_PHYS; i++) { + phy_addr = MT753X_PHY_ADDR(priv->phy_base, i); + phy_val = mtk_mii_read(priv->epriv.eth, phy_addr, MII_BMCR); + phy_val &= ~BMCR_PDOWN; + mtk_mii_write(priv->epriv.eth, phy_addr, MII_BMCR, phy_val); + } + + return mt7530_mdio_register(priv); +} + +static int mt7530_cleanup(struct mtk_eth_switch_priv *swpriv) +{ + struct mt753x_switch_priv *priv = (struct mt753x_switch_priv *)swpriv; + + mdio_unregister(priv->mdio_bus); + + return 0; +} + +static int mt7530_detect(struct mtk_eth_priv *priv) +{ + int ret; + u32 rev; + + ret = __mt753x_mdio_reg_read(priv, MT753X_DFL_SMI_ADDR, CHIP_REV, &rev); + if (ret) + return ret; + + if (((rev & CHIP_NAME_M) >> CHIP_NAME_S) == 0x7530) + return 0; + + return -ENODEV; +} + +MTK_ETH_SWITCH(mt7530) = { + .name = "mt7530", + .desc = "MediaTek MT7530", + .priv_size = sizeof(struct mt753x_switch_priv), + .reset_wait_time = 1000, + + .detect = mt7530_detect, + .setup = mt7530_setup, + .cleanup = mt7530_cleanup, + .mac_control = mt7530_mac_control, +}; diff --git a/drivers/net/mtk_eth/mt7531.c b/drivers/net/mtk_eth/mt7531.c new file mode 100644 index 00000000000..32d6bebbbdb --- /dev/null +++ b/drivers/net/mtk_eth/mt7531.c @@ -0,0 +1,293 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 MediaTek Inc. + * + * Author: Weijie Gao <weijie.gao@mediatek.com> + * Author: Mark Lee <mark-mc.lee@mediatek.com> + */ + +#include <miiphy.h> +#include <linux/delay.h> +#include <linux/mdio.h> +#include <linux/mii.h> +#include "mtk_eth.h" +#include "mt753x.h" + +#define CHIP_REV 0x781C +#define CHIP_NAME_S 16 +#define CHIP_NAME_M 0xffff0000 +#define CHIP_REV_S 0 +#define CHIP_REV_M 0x0f +#define CHIP_REV_E1 0x0 + +static int mt7531_core_reg_read(struct mt753x_switch_priv *priv, u32 reg) +{ + u8 phy_addr = MT753X_PHY_ADDR(priv->phy_base, 0); + + return mt7531_mmd_read(priv, phy_addr, 0x1f, reg); +} + +static void mt7531_core_reg_write(struct mt753x_switch_priv *priv, u32 reg, + u32 val) +{ + u8 phy_addr = MT753X_PHY_ADDR(priv->phy_base, 0); + + mt7531_mmd_write(priv, phy_addr, 0x1f, reg, val); +} + +static void mt7531_core_pll_setup(struct mt753x_switch_priv *priv) +{ + /* Step 1 : Disable MT7531 COREPLL */ + mt753x_reg_rmw(priv, MT7531_PLLGP_EN, EN_COREPLL, 0); + + /* Step 2: switch to XTAL output */ + mt753x_reg_rmw(priv, MT7531_PLLGP_EN, SW_CLKSW, SW_CLKSW); + + mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_EN, 0); + + /* Step 3: disable PLLGP and enable program PLLGP */ + mt753x_reg_rmw(priv, MT7531_PLLGP_EN, SW_PLLGP, SW_PLLGP); + + /* Step 4: program COREPLL output frequency to 500MHz */ + mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_POSDIV_M, + 2 << RG_COREPLL_POSDIV_S); + udelay(25); + + /* Currently, support XTAL 25Mhz only */ + mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_SDM_PCW_M, + 0x140000 << RG_COREPLL_SDM_PCW_S); + + /* Set feedback divide ratio update signal to high */ + mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_SDM_PCW_CHG, + RG_COREPLL_SDM_PCW_CHG); + + /* Wait for at least 16 XTAL clocks */ + udelay(10); + + /* Step 5: set feedback divide ratio update signal to low */ + mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_SDM_PCW_CHG, 0); + + /* add enable 325M clock for SGMII */ + mt753x_reg_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000); + + /* add enable 250SSC clock for RGMII */ + mt753x_reg_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000); + + /*Step 6: Enable MT7531 PLL */ + mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_EN, RG_COREPLL_EN); + + mt753x_reg_rmw(priv, MT7531_PLLGP_EN, EN_COREPLL, EN_COREPLL); + + udelay(25); +} + +static int mt7531_port_sgmii_init(struct mt753x_switch_priv *priv, u32 port) +{ + if (port != 5 && port != 6) { + printf("mt7531: port %d is not a SGMII port\n", port); + return -EINVAL; + } + + /* Set SGMII GEN2 speed(2.5G) */ + mt753x_reg_rmw(priv, MT7531_PHYA_CTRL_SIGNAL3(port), SGMSYS_SPEED_MASK, + FIELD_PREP(SGMSYS_SPEED_MASK, SGMSYS_SPEED_2500)); + + /* Disable SGMII AN */ + mt753x_reg_rmw(priv, MT7531_PCS_CONTROL_1(port), + SGMII_AN_ENABLE, 0); + + /* SGMII force mode setting */ + mt753x_reg_write(priv, MT7531_SGMII_MODE(port), SGMII_FORCE_MODE); + + /* Release PHYA power down state */ + mt753x_reg_rmw(priv, MT7531_QPHY_PWR_STATE_CTRL(port), + SGMII_PHYA_PWD, 0); + + return 0; +} + +static int mt7531_port_rgmii_init(struct mt753x_switch_priv *priv, u32 port) +{ + u32 val; + + if (port != 5) { + printf("error: RGMII mode is not available for port %d\n", + port); + return -EINVAL; + } + + mt753x_reg_read(priv, MT7531_CLKGEN_CTRL, &val); + val |= GP_CLK_EN; + val &= ~GP_MODE_M; + val |= GP_MODE_RGMII << GP_MODE_S; + val |= TXCLK_NO_REVERSE; + val |= RXCLK_NO_DELAY; + val &= ~CLK_SKEW_IN_M; + val |= CLK_SKEW_IN_NO_CHANGE << CLK_SKEW_IN_S; + val &= ~CLK_SKEW_OUT_M; + val |= CLK_SKEW_OUT_NO_CHANGE << CLK_SKEW_OUT_S; + mt753x_reg_write(priv, MT7531_CLKGEN_CTRL, val); + + return 0; +} + +static void mt7531_phy_setting(struct mt753x_switch_priv *priv) +{ + int i; + u32 val; + + for (i = 0; i < MT753X_NUM_PHYS; i++) { + /* Enable HW auto downshift */ + mt7531_mii_write(priv, i, 0x1f, 0x1); + val = mt7531_mii_read(priv, i, PHY_EXT_REG_14); + val |= PHY_EN_DOWN_SHFIT; + mt7531_mii_write(priv, i, PHY_EXT_REG_14, val); + + /* PHY link down power saving enable */ + val = mt7531_mii_read(priv, i, PHY_EXT_REG_17); + val |= PHY_LINKDOWN_POWER_SAVING_EN; + mt7531_mii_write(priv, i, PHY_EXT_REG_17, val); + + val = mt7531_mmd_read(priv, i, 0x1e, PHY_DEV1E_REG_0C6); + val &= ~PHY_POWER_SAVING_M; + val |= PHY_POWER_SAVING_TX << PHY_POWER_SAVING_S; + mt7531_mmd_write(priv, i, 0x1e, PHY_DEV1E_REG_0C6, val); + } +} + +static void mt7531_mac_control(struct mtk_eth_switch_priv *swpriv, bool enable) +{ + struct mt753x_switch_priv *priv = (struct mt753x_switch_priv *)swpriv; + u32 pmcr = FORCE_MODE_LNK; + + if (enable) + pmcr = priv->pmcr; + + mt753x_reg_write(priv, PMCR_REG(5), pmcr); + mt753x_reg_write(priv, PMCR_REG(6), pmcr); +} + +static int mt7531_setup(struct mtk_eth_switch_priv *swpriv) +{ + struct mt753x_switch_priv *priv = (struct mt753x_switch_priv *)swpriv; + u32 i, val, pmcr, port5_sgmii; + u16 phy_addr, phy_val; + + priv->smi_addr = MT753X_DFL_SMI_ADDR; + priv->phy_base = (priv->smi_addr + 1) & MT753X_SMI_ADDR_MASK; + priv->reg_read = mt753x_mdio_reg_read; + priv->reg_write = mt753x_mdio_reg_write; + + /* Turn off PHYs */ + for (i = 0; i < MT753X_NUM_PHYS; i++) { + phy_addr = MT753X_PHY_ADDR(priv->phy_base, i); + phy_val = mt7531_mii_read(priv, phy_addr, MII_BMCR); + phy_val |= BMCR_PDOWN; + mt7531_mii_write(priv, phy_addr, MII_BMCR, phy_val); + } + + /* Force MAC link down before reset */ + mt753x_reg_write(priv, PMCR_REG(5), FORCE_MODE_LNK); + mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE_LNK); + + /* Switch soft reset */ + mt753x_reg_write(priv, SYS_CTRL_REG, SW_SYS_RST | SW_REG_RST); + udelay(100); + + /* Enable MDC input Schmitt Trigger */ + mt753x_reg_rmw(priv, MT7531_SMT0_IOLB, SMT_IOLB_5_SMI_MDC_EN, + SMT_IOLB_5_SMI_MDC_EN); + + mt7531_core_pll_setup(priv); + + mt753x_reg_read(priv, MT7531_TOP_SIG_SR, &val); + port5_sgmii = !!(val & PAD_DUAL_SGMII_EN); + + /* port5 support either RGMII or SGMII, port6 only support SGMII. */ + switch (priv->epriv.phy_interface) { + case PHY_INTERFACE_MODE_RGMII: + if (!port5_sgmii) + mt7531_port_rgmii_init(priv, 5); + break; + + case PHY_INTERFACE_MODE_2500BASEX: + mt7531_port_sgmii_init(priv, 6); + if (port5_sgmii) + mt7531_port_sgmii_init(priv, 5); + break; + + default: + break; + } + + pmcr = MT7531_FORCE_MODE | + (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) | + MAC_MODE | MAC_TX_EN | MAC_RX_EN | + BKOFF_EN | BACKPR_EN | + FORCE_RX_FC | FORCE_TX_FC | + (SPEED_1000M << FORCE_SPD_S) | FORCE_DPX | + FORCE_LINK; + + priv->pmcr = pmcr; + + /* Keep MAC link down before starting eth */ + mt753x_reg_write(priv, PMCR_REG(5), FORCE_MODE_LNK); + mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE_LNK); + + /* Enable port isolation to block inter-port communication */ + mt753x_port_isolation(priv); + + /* Turn on PHYs */ + for (i = 0; i < MT753X_NUM_PHYS; i++) { + phy_addr = MT753X_PHY_ADDR(priv->phy_base, i); + phy_val = mt7531_mii_read(priv, phy_addr, MII_BMCR); + phy_val &= ~BMCR_PDOWN; + mt7531_mii_write(priv, phy_addr, MII_BMCR, phy_val); + } + + mt7531_phy_setting(priv); + + /* Enable Internal PHYs */ + val = mt7531_core_reg_read(priv, CORE_PLL_GROUP4); + val |= MT7531_BYPASS_MODE; + val &= ~MT7531_POWER_ON_OFF; + mt7531_core_reg_write(priv, CORE_PLL_GROUP4, val); + + return mt7531_mdio_register(priv); +} + +static int mt7531_cleanup(struct mtk_eth_switch_priv *swpriv) +{ + struct mt753x_switch_priv *priv = (struct mt753x_switch_priv *)swpriv; + + mdio_unregister(priv->mdio_bus); + + return 0; +} + +static int mt7531_detect(struct mtk_eth_priv *priv) +{ + int ret; + u32 rev; + + ret = __mt753x_mdio_reg_read(priv, MT753X_DFL_SMI_ADDR, CHIP_REV, &rev); + if (ret) + return ret; + + if (((rev & CHIP_NAME_M) >> CHIP_NAME_S) == 0x7531) + return 0; + + return -ENODEV; +} + +MTK_ETH_SWITCH(mt7531) = { + .name = "mt7531", + .desc = "MediaTek MT7531", + .priv_size = sizeof(struct mt753x_switch_priv), + .reset_wait_time = 200, + + .detect = mt7531_detect, + .setup = mt7531_setup, + .cleanup = mt7531_cleanup, + .mac_control = mt7531_mac_control, +}; diff --git a/drivers/net/mtk_eth/mt753x.c b/drivers/net/mtk_eth/mt753x.c new file mode 100644 index 00000000000..cdd52f3ff1b --- /dev/null +++ b/drivers/net/mtk_eth/mt753x.c @@ -0,0 +1,262 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 MediaTek Inc. + * + * Author: Weijie Gao <weijie.gao@mediatek.com> + * Author: Mark Lee <mark-mc.lee@mediatek.com> + */ + +#include <errno.h> +#include <time.h> +#include "mtk_eth.h" +#include "mt753x.h" + +/* + * MT753x Internal Register Address Bits + * ------------------------------------------------------------------- + * | 15 14 13 12 11 10 9 8 7 6 | 5 4 3 2 | 1 0 | + * |----------------------------------------|---------------|--------| + * | Page Address | Reg Address | Unused | + * ------------------------------------------------------------------- + */ + +int __mt753x_mdio_reg_read(struct mtk_eth_priv *priv, u32 smi_addr, u32 reg, + u32 *data) +{ + int ret, low_word, high_word; + + /* Write page address */ + ret = mtk_mii_write(priv, smi_addr, 0x1f, reg >> 6); + if (ret) + return ret; + + /* Read low word */ + low_word = mtk_mii_read(priv, smi_addr, (reg >> 2) & 0xf); + if (low_word < 0) + return low_word; + + /* Read high word */ + high_word = mtk_mii_read(priv, smi_addr, 0x10); + if (high_word < 0) + return high_word; + + if (data) + *data = ((u32)high_word << 16) | (low_word & 0xffff); + + return 0; +} + +int mt753x_mdio_reg_read(struct mt753x_switch_priv *priv, u32 reg, u32 *data) +{ + return __mt753x_mdio_reg_read(priv->epriv.eth, priv->smi_addr, reg, + data); +} + +int mt753x_mdio_reg_write(struct mt753x_switch_priv *priv, u32 reg, u32 data) +{ + int ret; + + /* Write page address */ + ret = mtk_mii_write(priv->epriv.eth, priv->smi_addr, 0x1f, reg >> 6); + if (ret) + return ret; + + /* Write low word */ + ret = mtk_mii_write(priv->epriv.eth, priv->smi_addr, (reg >> 2) & 0xf, + data & 0xffff); + if (ret) + return ret; + + /* Write high word */ + return mtk_mii_write(priv->epriv.eth, priv->smi_addr, 0x10, data >> 16); +} + +int mt753x_reg_read(struct mt753x_switch_priv *priv, u32 reg, u32 *data) +{ + return priv->reg_read(priv, reg, data); +} + +int mt753x_reg_write(struct mt753x_switch_priv *priv, u32 reg, u32 data) +{ + return priv->reg_write(priv, reg, data); +} + +void mt753x_reg_rmw(struct mt753x_switch_priv *priv, u32 reg, u32 clr, u32 set) +{ + u32 val; + + priv->reg_read(priv, reg, &val); + val &= ~clr; + val |= set; + priv->reg_write(priv, reg, val); +} + +/* Indirect MDIO clause 22/45 access */ +static int mt7531_mii_rw(struct mt753x_switch_priv *priv, int phy, int reg, + u16 data, u32 cmd, u32 st) +{ + u32 val, timeout_ms; + ulong timeout; + int ret = 0; + + val = (st << MDIO_ST_S) | + ((cmd << MDIO_CMD_S) & MDIO_CMD_M) | + ((phy << MDIO_PHY_ADDR_S) & MDIO_PHY_ADDR_M) | + ((reg << MDIO_REG_ADDR_S) & MDIO_REG_ADDR_M); + + if (cmd == MDIO_CMD_WRITE || cmd == MDIO_CMD_ADDR) + val |= data & MDIO_RW_DATA_M; + + mt753x_reg_write(priv, MT7531_PHY_IAC, val | PHY_ACS_ST); + + timeout_ms = 100; + timeout = get_timer(0); + while (1) { + mt753x_reg_read(priv, MT7531_PHY_IAC, &val); + + if ((val & PHY_ACS_ST) == 0) + break; + + if (get_timer(timeout) > timeout_ms) + return -ETIMEDOUT; + } + + if (cmd == MDIO_CMD_READ || cmd == MDIO_CMD_READ_C45) { + mt753x_reg_read(priv, MT7531_PHY_IAC, &val); + ret = val & MDIO_RW_DATA_M; + } + + return ret; +} + +int mt7531_mii_read(struct mt753x_switch_priv *priv, u8 phy, u8 reg) +{ + u8 phy_addr; + + if (phy >= MT753X_NUM_PHYS) + return -EINVAL; + + phy_addr = MT753X_PHY_ADDR(priv->phy_base, phy); + + return mt7531_mii_rw(priv, phy_addr, reg, 0, MDIO_CMD_READ, + MDIO_ST_C22); +} + +int mt7531_mii_write(struct mt753x_switch_priv *priv, u8 phy, u8 reg, u16 val) +{ + u8 phy_addr; + + if (phy >= MT753X_NUM_PHYS) + return -EINVAL; + + phy_addr = MT753X_PHY_ADDR(priv->phy_base, phy); + + return mt7531_mii_rw(priv, phy_addr, reg, val, MDIO_CMD_WRITE, + MDIO_ST_C22); +} + +int mt7531_mmd_read(struct mt753x_switch_priv *priv, u8 addr, u8 devad, + u16 reg) +{ + u8 phy_addr; + int ret; + + if (addr >= MT753X_NUM_PHYS) + return -EINVAL; + + phy_addr = MT753X_PHY_ADDR(priv->phy_base, addr); + + ret = mt7531_mii_rw(priv, phy_addr, devad, reg, MDIO_CMD_ADDR, + MDIO_ST_C45); + if (ret) + return ret; + + return mt7531_mii_rw(priv, phy_addr, devad, 0, MDIO_CMD_READ_C45, + MDIO_ST_C45); +} + +int mt7531_mmd_write(struct mt753x_switch_priv *priv, u8 addr, u8 devad, + u16 reg, u16 val) +{ + u8 phy_addr; + int ret; + + if (addr >= MT753X_NUM_PHYS) + return 0; + + phy_addr = MT753X_PHY_ADDR(priv->phy_base, addr); + + ret = mt7531_mii_rw(priv, phy_addr, devad, reg, MDIO_CMD_ADDR, + MDIO_ST_C45); + if (ret) + return ret; + + return mt7531_mii_rw(priv, phy_addr, devad, val, MDIO_CMD_WRITE, + MDIO_ST_C45); +} + +static int mt7531_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) +{ + struct mt753x_switch_priv *priv = bus->priv; + + if (devad < 0) + return mt7531_mii_read(priv, addr, reg); + + return mt7531_mmd_read(priv, addr, devad, reg); +} + +static int mt7531_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, + u16 val) +{ + struct mt753x_switch_priv *priv = bus->priv; + + if (devad < 0) + return mt7531_mii_write(priv, addr, reg, val); + + return mt7531_mmd_write(priv, addr, devad, reg, val); +} + +int mt7531_mdio_register(struct mt753x_switch_priv *priv) +{ + struct mii_dev *mdio_bus = mdio_alloc(); + int ret; + + if (!mdio_bus) + return -ENOMEM; + + mdio_bus->read = mt7531_mdio_read; + mdio_bus->write = mt7531_mdio_write; + snprintf(mdio_bus->name, sizeof(mdio_bus->name), priv->epriv.sw->name); + + mdio_bus->priv = priv; + + ret = mdio_register(mdio_bus); + if (ret) { + mdio_free(mdio_bus); + return ret; + } + + priv->mdio_bus = mdio_bus; + + return 0; +} + +void mt753x_port_isolation(struct mt753x_switch_priv *priv) +{ + u32 i; + + for (i = 0; i < MT753X_NUM_PORTS; i++) { + /* Set port matrix mode */ + if (i != 6) + mt753x_reg_write(priv, PCR_REG(i), + (0x40 << PORT_MATRIX_S)); + else + mt753x_reg_write(priv, PCR_REG(i), + (0x3f << PORT_MATRIX_S)); + + /* Set port mode to user port */ + mt753x_reg_write(priv, PVC_REG(i), + (0x8100 << STAG_VPID_S) | + (VLAN_ATTR_USER << VLAN_ATTR_S)); + } +} diff --git a/drivers/net/mtk_eth/mt753x.h b/drivers/net/mtk_eth/mt753x.h new file mode 100644 index 00000000000..65046a1421c --- /dev/null +++ b/drivers/net/mtk_eth/mt753x.h @@ -0,0 +1,286 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2025 MediaTek Inc. + * + * Author: Weijie Gao <weijie.gao@mediatek.com> + * Author: Mark Lee <mark-mc.lee@mediatek.com> + */ + +#ifndef _MTK_ETH_MT753X_H_ +#define _MTK_ETH_MT753X_H_ + +#include <phy.h> +#include <miiphy.h> +#include <linux/bitops.h> +#include <linux/bitfield.h> + +struct mtk_eth_priv; + +#define MT753X_NUM_PHYS 5 +#define MT753X_NUM_PORTS 7 +#define MT753X_DFL_SMI_ADDR 31 +#define MT753X_SMI_ADDR_MASK 0x1f + +#define MT753X_PHY_ADDR(base, addr) \ + (((base) + (addr)) & 0x1f) + +/* MT7530 Registers */ +#define PCR_REG(p) (0x2004 + (p) * 0x100) +#define PORT_MATRIX_S 16 +#define PORT_MATRIX_M 0xff0000 + +#define PVC_REG(p) (0x2010 + (p) * 0x100) +#define STAG_VPID_S 16 +#define STAG_VPID_M 0xffff0000 +#define VLAN_ATTR_S 6 +#define VLAN_ATTR_M 0xc0 + +/* VLAN_ATTR: VLAN attributes */ +#define VLAN_ATTR_USER 0 +#define VLAN_ATTR_STACK 1 +#define VLAN_ATTR_TRANSLATION 2 +#define VLAN_ATTR_TRANSPARENT 3 + +#define PMCR_REG(p) (0x3000 + (p) * 0x100) +/* XXX: all fields of MT7530 are defined under GMAC_PORT_MCR + * MT7531 specific fields are defined below + */ +#define FORCE_MODE_EEE1G BIT(25) +#define FORCE_MODE_EEE100 BIT(26) +#define FORCE_MODE_TX_FC BIT(27) +#define FORCE_MODE_RX_FC BIT(28) +#define FORCE_MODE_DPX BIT(29) +#define FORCE_MODE_SPD BIT(30) +#define FORCE_MODE_LNK BIT(31) +#define MT7531_FORCE_MODE FORCE_MODE_TX_FC | FORCE_MODE_RX_FC | \ + FORCE_MODE_DPX | FORCE_MODE_SPD | \ + FORCE_MODE_LNK +#define MT7988_FORCE_MODE FORCE_MODE_TX_FC | FORCE_MODE_RX_FC | \ + FORCE_MODE_DPX | FORCE_MODE_SPD | \ + FORCE_MODE_LNK + +/* MT7531 SGMII Registers */ +#define MT7531_SGMII_REG_BASE 0x5000 +#define MT7531_SGMII_REG_PORT_BASE 0x1000 +#define MT7531_SGMII_REG(p, r) (MT7531_SGMII_REG_BASE + \ + (p) * MT7531_SGMII_REG_PORT_BASE + (r)) +#define MT7531_PCS_CONTROL_1(p) MT7531_SGMII_REG(((p) - 5), 0x00) +#define MT7531_SGMII_MODE(p) MT7531_SGMII_REG(((p) - 5), 0x20) +#define MT7531_QPHY_PWR_STATE_CTRL(p) MT7531_SGMII_REG(((p) - 5), 0xe8) +#define MT7531_PHYA_CTRL_SIGNAL3(p) MT7531_SGMII_REG(((p) - 5), 0x128) +#define MT7531_PHYA_ANA_SYSPLL(p) MT7531_SGMII_REG(((p) - 5), 0x158) +/* XXX: all fields of MT7531 SGMII are defined under SGMSYS */ + +/* MT753x System Control Register */ +#define SYS_CTRL_REG 0x7000 +#define SW_PHY_RST BIT(2) +#define SW_SYS_RST BIT(1) +#define SW_REG_RST BIT(0) + +/* MT7531 */ +#define MT7531_PHY_IAC 0x701c +/* XXX: all fields are defined under GMAC_PIAC_REG */ + +#define MT7531_CLKGEN_CTRL 0x7500 +#define CLK_SKEW_OUT_S 8 +#define CLK_SKEW_OUT_M 0x300 +#define CLK_SKEW_IN_S 6 +#define CLK_SKEW_IN_M 0xc0 +#define RXCLK_NO_DELAY BIT(5) +#define TXCLK_NO_REVERSE BIT(4) +#define GP_MODE_S 1 +#define GP_MODE_M 0x06 +#define GP_CLK_EN BIT(0) + +/* Values of GP_MODE */ +#define GP_MODE_RGMII 0 +#define GP_MODE_MII 1 +#define GP_MODE_REV_MII 2 + +/* Values of CLK_SKEW_IN */ +#define CLK_SKEW_IN_NO_CHANGE 0 +#define CLK_SKEW_IN_DELAY_100PPS 1 +#define CLK_SKEW_IN_DELAY_200PPS 2 +#define CLK_SKEW_IN_REVERSE 3 + +/* Values of CLK_SKEW_OUT */ +#define CLK_SKEW_OUT_NO_CHANGE 0 +#define CLK_SKEW_OUT_DELAY_100PPS 1 +#define CLK_SKEW_OUT_DELAY_200PPS 2 +#define CLK_SKEW_OUT_REVERSE 3 + +#define HWTRAP_REG 0x7800 +/* MT7530 Modified Hardware Trap Status Registers */ +#define MHWTRAP_REG 0x7804 +#define CHG_TRAP BIT(16) +#define LOOPDET_DIS BIT(14) +#define P5_INTF_SEL_S 13 +#define P5_INTF_SEL_M 0x2000 +#define SMI_ADDR_S 11 +#define SMI_ADDR_M 0x1800 +#define XTAL_FSEL_S 9 +#define XTAL_FSEL_M 0x600 +#define P6_INTF_DIS BIT(8) +#define P5_INTF_MODE_S 7 +#define P5_INTF_MODE_M 0x80 +#define P5_INTF_DIS BIT(6) +#define C_MDIO_BPS BIT(5) +#define CHIP_MODE_S 0 +#define CHIP_MODE_M 0x0f + +/* P5_INTF_SEL: Interface type of Port5 */ +#define P5_INTF_SEL_GPHY 0 +#define P5_INTF_SEL_GMAC5 1 + +/* P5_INTF_MODE: Interface mode of Port5 */ +#define P5_INTF_MODE_GMII_MII 0 +#define P5_INTF_MODE_RGMII 1 + +#define MT7530_P6ECR 0x7830 +#define P6_INTF_MODE_M 0x3 +#define P6_INTF_MODE_S 0 + +/* P6_INTF_MODE: Interface mode of Port6 */ +#define P6_INTF_MODE_RGMII 0 +#define P6_INTF_MODE_TRGMII 1 + +#define MT7530_TRGMII_RD(n) (0x7a10 + (n) * 8) +#define RD_TAP_S 0 +#define RD_TAP_M 0x7f + +#define MT7530_TRGMII_TD_ODT(n) (0x7a54 + (n) * 8) +/* XXX: all fields are defined under GMAC_TRGMII_TD_ODT */ + +/* TOP Signals Status Register */ +#define MT7531_TOP_SIG_SR 0x780c +#define PAD_MCM_SMI_EN BIT(0) +#define PAD_DUAL_SGMII_EN BIT(1) + +/* MT7531 PLLGP Registers */ +#define MT7531_PLLGP_EN 0x7820 +#define EN_COREPLL BIT(2) +#define SW_CLKSW BIT(1) +#define SW_PLLGP BIT(0) + +#define MT7531_PLLGP_CR0 0x78a8 +#define RG_COREPLL_EN BIT(22) +#define RG_COREPLL_POSDIV_S 23 +#define RG_COREPLL_POSDIV_M 0x3800000 +#define RG_COREPLL_SDM_PCW_S 1 +#define RG_COREPLL_SDM_PCW_M 0x3ffffe +#define RG_COREPLL_SDM_PCW_CHG BIT(0) + +/* MT7531 RGMII and SGMII PLL clock */ +#define MT7531_ANA_PLLGP_CR2 0x78b0 +#define MT7531_ANA_PLLGP_CR5 0x78bc + +/* MT7531 GPIO GROUP IOLB SMT0 Control */ +#define MT7531_SMT0_IOLB 0x7f04 +#define SMT_IOLB_5_SMI_MDC_EN BIT(5) + +/* MT7530 GPHY MDIO MMD Registers */ +#define CORE_PLL_GROUP2 0x401 +#define RG_SYSPLL_EN_NORMAL BIT(15) +#define RG_SYSPLL_VODEN BIT(14) +#define RG_SYSPLL_POSDIV_S 5 +#define RG_SYSPLL_POSDIV_M 0x60 + +#define CORE_PLL_GROUP4 0x403 +#define MT7531_BYPASS_MODE BIT(4) +#define MT7531_POWER_ON_OFF BIT(5) +#define RG_SYSPLL_DDSFBK_EN BIT(12) +#define RG_SYSPLL_BIAS_EN BIT(11) +#define RG_SYSPLL_BIAS_LPF_EN BIT(10) + +#define CORE_PLL_GROUP5 0x404 +#define RG_LCDDS_PCW_NCPO1_S 0 +#define RG_LCDDS_PCW_NCPO1_M 0xffff + +#define CORE_PLL_GROUP6 0x405 +#define RG_LCDDS_PCW_NCPO0_S 0 +#define RG_LCDDS_PCW_NCPO0_M 0xffff + +#define CORE_PLL_GROUP7 0x406 +#define RG_LCDDS_PWDB BIT(15) +#define RG_LCDDS_ISO_EN BIT(13) +#define RG_LCCDS_C_S 4 +#define RG_LCCDS_C_M 0x70 +#define RG_LCDDS_PCW_NCPO_CHG BIT(3) + +#define CORE_PLL_GROUP10 0x409 +#define RG_LCDDS_SSC_DELTA_S 0 +#define RG_LCDDS_SSC_DELTA_M 0xfff + +#define CORE_PLL_GROUP11 0x40a +#define RG_LCDDS_SSC_DELTA1_S 0 +#define RG_LCDDS_SSC_DELTA1_M 0xfff + +#define CORE_GSWPLL_GRP1 0x40d +#define RG_GSWPLL_POSDIV_200M_S 12 +#define RG_GSWPLL_POSDIV_200M_M 0x3000 +#define RG_GSWPLL_EN_PRE BIT(11) +#define RG_GSWPLL_FBKDIV_200M_S 0 +#define RG_GSWPLL_FBKDIV_200M_M 0xff + +#define CORE_GSWPLL_GRP2 0x40e +#define RG_GSWPLL_POSDIV_500M_S 8 +#define RG_GSWPLL_POSDIV_500M_M 0x300 +#define RG_GSWPLL_FBKDIV_500M_S 0 +#define RG_GSWPLL_FBKDIV_500M_M 0xff + +#define CORE_TRGMII_GSW_CLK_CG 0x410 +#define REG_GSWCK_EN BIT(0) +#define REG_TRGMIICK_EN BIT(1) + +/* Extend PHY Control Register 3 */ +#define PHY_EXT_REG_14 0x14 + +/* Fields of PHY_EXT_REG_14 */ +#define PHY_EN_DOWN_SHFIT BIT(4) + +/* Extend PHY Control Register 4 */ +#define PHY_EXT_REG_17 0x17 + +/* Fields of PHY_EXT_REG_17 */ +#define PHY_LINKDOWN_POWER_SAVING_EN BIT(4) + +/* PHY RXADC Control Register 7 */ +#define PHY_DEV1E_REG_0C6 0x0c6 + +/* Fields of PHY_DEV1E_REG_0C6 */ +#define PHY_POWER_SAVING_S 8 +#define PHY_POWER_SAVING_M 0x300 +#define PHY_POWER_SAVING_TX 0x0 + +struct mt753x_switch_priv { + struct mtk_eth_switch_priv epriv; + struct mii_dev *mdio_bus; + u32 smi_addr; + u32 phy_base; + u32 pmcr; + + int (*reg_read)(struct mt753x_switch_priv *priv, u32 reg, u32 *data); + int (*reg_write)(struct mt753x_switch_priv *priv, u32 reg, u32 data); +}; + +int __mt753x_mdio_reg_read(struct mtk_eth_priv *priv, u32 smi_addr, u32 reg, + u32 *data); +int mt753x_mdio_reg_read(struct mt753x_switch_priv *priv, u32 reg, u32 *data); +int mt753x_mdio_reg_write(struct mt753x_switch_priv *priv, u32 reg, u32 data); + +int mt753x_reg_read(struct mt753x_switch_priv *priv, u32 reg, u32 *data); +int mt753x_reg_write(struct mt753x_switch_priv *priv, u32 reg, u32 data); +void mt753x_reg_rmw(struct mt753x_switch_priv *priv, u32 reg, u32 clr, u32 set); + +int mt7531_mii_read(struct mt753x_switch_priv *priv, u8 phy, u8 reg); +int mt7531_mii_write(struct mt753x_switch_priv *priv, u8 phy, u8 reg, u16 val); +int mt7531_mmd_read(struct mt753x_switch_priv *priv, u8 addr, u8 devad, + u16 reg); +int mt7531_mmd_write(struct mt753x_switch_priv *priv, u8 addr, u8 devad, + u16 reg, u16 val); + +int mt7531_mdio_register(struct mt753x_switch_priv *priv); + +void mt753x_port_isolation(struct mt753x_switch_priv *priv); + +#endif /* _MTK_ETH_MT753X_H_ */ diff --git a/drivers/net/mtk_eth/mt7988.c b/drivers/net/mtk_eth/mt7988.c new file mode 100644 index 00000000000..a416d87840c --- /dev/null +++ b/drivers/net/mtk_eth/mt7988.c @@ -0,0 +1,160 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 MediaTek Inc. + * + * Author: Weijie Gao <weijie.gao@mediatek.com> + * Author: Mark Lee <mark-mc.lee@mediatek.com> + */ + +#include <miiphy.h> +#include <linux/delay.h> +#include <linux/mdio.h> +#include <linux/mii.h> +#include <linux/io.h> +#include "mtk_eth.h" +#include "mt753x.h" + +static int mt7988_reg_read(struct mt753x_switch_priv *priv, u32 reg, u32 *data) +{ + *data = readl(priv->epriv.ethsys_base + GSW_BASE + reg); + + return 0; +} + +static int mt7988_reg_write(struct mt753x_switch_priv *priv, u32 reg, u32 data) +{ + writel(data, priv->epriv.ethsys_base + GSW_BASE + reg); + + return 0; +} + +static void mt7988_phy_setting(struct mt753x_switch_priv *priv) +{ + u16 val; + u32 i; + + for (i = 0; i < MT753X_NUM_PHYS; i++) { + /* Enable HW auto downshift */ + mt7531_mii_write(priv, i, 0x1f, 0x1); + val = mt7531_mii_read(priv, i, PHY_EXT_REG_14); + val |= PHY_EN_DOWN_SHFIT; + mt7531_mii_write(priv, i, PHY_EXT_REG_14, val); + + /* PHY link down power saving enable */ + val = mt7531_mii_read(priv, i, PHY_EXT_REG_17); + val |= PHY_LINKDOWN_POWER_SAVING_EN; + mt7531_mii_write(priv, i, PHY_EXT_REG_17, val); + } +} + +static void mt7988_mac_control(struct mtk_eth_switch_priv *swpriv, bool enable) +{ + struct mt753x_switch_priv *priv = (struct mt753x_switch_priv *)swpriv; + u32 pmcr = FORCE_MODE_LNK; + + if (enable) + pmcr = priv->pmcr; + + mt7988_reg_write(priv, PMCR_REG(6), pmcr); +} + +static int mt7988_setup(struct mtk_eth_switch_priv *swpriv) +{ + struct mt753x_switch_priv *priv = (struct mt753x_switch_priv *)swpriv; + u16 phy_addr, phy_val; + u32 pmcr; + int i; + + priv->smi_addr = MT753X_DFL_SMI_ADDR; + priv->phy_base = (priv->smi_addr + 1) & MT753X_SMI_ADDR_MASK; + priv->reg_read = mt7988_reg_read; + priv->reg_write = mt7988_reg_write; + + /* Turn off PHYs */ + for (i = 0; i < MT753X_NUM_PHYS; i++) { + phy_addr = MT753X_PHY_ADDR(priv->phy_base, i); + phy_val = mt7531_mii_read(priv, phy_addr, MII_BMCR); + phy_val |= BMCR_PDOWN; + mt7531_mii_write(priv, phy_addr, MII_BMCR, phy_val); + } + + switch (priv->epriv.phy_interface) { + case PHY_INTERFACE_MODE_USXGMII: + /* Use CPU bridge instead of actual USXGMII path */ + + /* Disable GDM1 RX CRC stripping */ + /* mtk_fe_rmw(priv, 0x500, BIT(16), 0); */ + + /* Set GDM1 no drop */ + mtk_fe_rmw(priv->epriv.eth, PSE_NO_DROP_CFG_REG, 0, + PSE_NO_DROP_GDM1); + + /* Enable GSW CPU bridge as USXGMII */ + /* mtk_fe_rmw(priv, 0x504, BIT(31), BIT(31)); */ + + /* Enable GDM1 to GSW CPU bridge */ + mtk_gmac_rmw(priv->epriv.eth, GMAC_MAC_MISC_REG, 0, BIT(0)); + + /* XGMAC force link up */ + mtk_gmac_rmw(priv->epriv.eth, GMAC_XGMAC_STS_REG, 0, + P1_XGMAC_FORCE_LINK); + + /* Setup GSW CPU bridge IPG */ + mtk_gmac_rmw(priv->epriv.eth, GMAC_GSW_CFG_REG, + GSWTX_IPG_M | GSWRX_IPG_M, + (0xB << GSWTX_IPG_S) | (0xB << GSWRX_IPG_S)); + break; + default: + printf("Error: MT7988 GSW does not support %s interface\n", + phy_string_for_interface(priv->epriv.phy_interface)); + break; + } + + pmcr = MT7988_FORCE_MODE | + (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) | + MAC_MODE | MAC_TX_EN | MAC_RX_EN | + BKOFF_EN | BACKPR_EN | + FORCE_RX_FC | FORCE_TX_FC | + (SPEED_1000M << FORCE_SPD_S) | FORCE_DPX | + FORCE_LINK; + + priv->pmcr = pmcr; + + /* Keep MAC link down before starting eth */ + mt7988_reg_write(priv, PMCR_REG(6), FORCE_MODE_LNK); + + /* Enable port isolation to block inter-port communication */ + mt753x_port_isolation(priv); + + /* Turn on PHYs */ + for (i = 0; i < MT753X_NUM_PHYS; i++) { + phy_addr = MT753X_PHY_ADDR(priv->phy_base, i); + phy_val = mt7531_mii_read(priv, phy_addr, MII_BMCR); + phy_val &= ~BMCR_PDOWN; + mt7531_mii_write(priv, phy_addr, MII_BMCR, phy_val); + } + + mt7988_phy_setting(priv); + + return mt7531_mdio_register(priv); +} + +static int mt7531_cleanup(struct mtk_eth_switch_priv *swpriv) +{ + struct mt753x_switch_priv *priv = (struct mt753x_switch_priv *)swpriv; + + mdio_unregister(priv->mdio_bus); + + return 0; +} + +MTK_ETH_SWITCH(mt7988) = { + .name = "mt7988", + .desc = "MediaTek MT7988 built-in switch", + .priv_size = sizeof(struct mt753x_switch_priv), + .reset_wait_time = 50, + + .setup = mt7988_setup, + .cleanup = mt7531_cleanup, + .mac_control = mt7988_mac_control, +}; diff --git a/drivers/net/mtk_eth.c b/drivers/net/mtk_eth/mtk_eth.c index 454caa3cd3a..5d6a42bceb4 100644 --- a/drivers/net/mtk_eth.c +++ b/drivers/net/mtk_eth/mtk_eth.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2018 MediaTek Inc. + * Copyright (C) 2025 MediaTek Inc. * * Author: Weijie Gao <weijie.gao@mediatek.com> * Author: Mark Lee <mark-mc.lee@mediatek.com> @@ -35,14 +35,6 @@ #define RX_TOTAL_BUF_SIZE (NUM_RX_DESC * PKTSIZE_ALIGN) #define TOTAL_PKT_BUF_SIZE (TX_TOTAL_BUF_SIZE + RX_TOTAL_BUF_SIZE) -#define MT753X_NUM_PHYS 5 -#define MT753X_NUM_PORTS 7 -#define MT753X_DFL_SMI_ADDR 31 -#define MT753X_SMI_ADDR_MASK 0x1f - -#define MT753X_PHY_ADDR(base, addr) \ - (((base) + (addr)) & 0x1f) - #define GDMA_FWD_TO_CPU \ (0x20000000 | \ GDM_ICS_EN | \ @@ -75,32 +67,6 @@ (DP_DISCARD << MC_DP_S) | \ (DP_DISCARD << UN_DP_S)) -enum mtk_switch { - SW_NONE, - SW_MT7530, - SW_MT7531, - SW_MT7988, -}; - -/* struct mtk_soc_data - This is the structure holding all differences - * among various plaforms - * @caps Flags shown the extra capability for the SoC - * @ana_rgc3: The offset for register ANA_RGC3 related to - * sgmiisys syscon - * @gdma_count: Number of GDMAs - * @pdma_base: Register base of PDMA block - * @txd_size: Tx DMA descriptor size. - * @rxd_size: Rx DMA descriptor size. - */ -struct mtk_soc_data { - u32 caps; - u32 ana_rgc3; - u32 gdma_count; - u32 pdma_base; - u32 txd_size; - u32 rxd_size; -}; - struct mtk_eth_priv { char pkt_pool[TOTAL_PKT_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN); @@ -113,7 +79,6 @@ struct mtk_eth_priv { void __iomem *fe_base; void __iomem *gmac_base; void __iomem *sgmii_base; - void __iomem *gsw_base; struct regmap *ethsys_regmap; @@ -125,11 +90,6 @@ struct mtk_eth_priv { struct regmap *toprgu_regmap; struct mii_dev *mdio_bus; - int (*mii_read)(struct mtk_eth_priv *priv, u8 phy, u8 reg); - int (*mii_write)(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 val); - int (*mmd_read)(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg); - int (*mmd_write)(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg, - u16 val); const struct mtk_soc_data *soc; int gmac_id; @@ -143,13 +103,8 @@ struct mtk_eth_priv { int phy_interface; int phy_addr; - enum mtk_switch sw; - int (*switch_init)(struct mtk_eth_priv *priv); - void (*switch_mac_control)(struct mtk_eth_priv *priv, bool enable); - u32 mt753x_smi_addr; - u32 mt753x_phy_base; - u32 mt753x_pmcr; - u32 mt753x_reset_wait_time; + struct mtk_eth_switch_priv *swpriv; + const char *swname; struct gpio_desc rst_gpio; int mcm; @@ -184,7 +139,7 @@ static void mtk_gdma_write(struct mtk_eth_priv *priv, int no, u32 reg, writel(val, priv->fe_base + gdma_base + reg); } -static void mtk_fe_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, u32 set) +void mtk_fe_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, u32 set) { clrsetbits_le32(priv->fe_base + reg, clr, set); } @@ -199,13 +154,12 @@ static void mtk_gmac_write(struct mtk_eth_priv *priv, u32 reg, u32 val) writel(val, priv->gmac_base + reg); } -static void mtk_gmac_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, u32 set) +void mtk_gmac_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, u32 set) { clrsetbits_le32(priv->gmac_base + reg, clr, set); } -static void mtk_ethsys_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, - u32 set) +void mtk_ethsys_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, u32 set) { uint val; @@ -226,16 +180,6 @@ static void mtk_infra_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, regmap_write(priv->infra_regmap, reg, val); } -static u32 mtk_gsw_read(struct mtk_eth_priv *priv, u32 reg) -{ - return readl(priv->gsw_base + reg); -} - -static void mtk_gsw_write(struct mtk_eth_priv *priv, u32 reg, u32 val) -{ - writel(val, priv->gsw_base + reg); -} - /* Direct MDIO clause 22/45 access via SoC */ static int mtk_mii_rw(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 data, u32 cmd, u32 st) @@ -269,19 +213,19 @@ static int mtk_mii_rw(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 data, } /* Direct MDIO clause 22 read via SoC */ -static int mtk_mii_read(struct mtk_eth_priv *priv, u8 phy, u8 reg) +int mtk_mii_read(struct mtk_eth_priv *priv, u8 phy, u8 reg) { return mtk_mii_rw(priv, phy, reg, 0, MDIO_CMD_READ, MDIO_ST_C22); } /* Direct MDIO clause 22 write via SoC */ -static int mtk_mii_write(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 data) +int mtk_mii_write(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 data) { return mtk_mii_rw(priv, phy, reg, data, MDIO_CMD_WRITE, MDIO_ST_C22); } /* Direct MDIO clause 45 read via SoC */ -static int mtk_mmd_read(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg) +int mtk_mmd_read(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg) { int ret; @@ -294,8 +238,8 @@ static int mtk_mmd_read(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg) } /* Direct MDIO clause 45 write via SoC */ -static int mtk_mmd_write(struct mtk_eth_priv *priv, u8 addr, u8 devad, - u16 reg, u16 val) +int mtk_mmd_write(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg, + u16 val) { int ret; @@ -308,232 +252,52 @@ static int mtk_mmd_write(struct mtk_eth_priv *priv, u8 addr, u8 devad, } /* Indirect MDIO clause 45 read via MII registers */ -static int mtk_mmd_ind_read(struct mtk_eth_priv *priv, u8 addr, u8 devad, - u16 reg) +int mtk_mmd_ind_read(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg) { int ret; - ret = priv->mii_write(priv, addr, MII_MMD_ACC_CTL_REG, - (MMD_ADDR << MMD_CMD_S) | - ((devad << MMD_DEVAD_S) & MMD_DEVAD_M)); + ret = mtk_mii_write(priv, addr, MII_MMD_ACC_CTL_REG, + (MMD_ADDR << MMD_CMD_S) | + ((devad << MMD_DEVAD_S) & MMD_DEVAD_M)); if (ret) return ret; - ret = priv->mii_write(priv, addr, MII_MMD_ADDR_DATA_REG, reg); + ret = mtk_mii_write(priv, addr, MII_MMD_ADDR_DATA_REG, reg); if (ret) return ret; - ret = priv->mii_write(priv, addr, MII_MMD_ACC_CTL_REG, - (MMD_DATA << MMD_CMD_S) | - ((devad << MMD_DEVAD_S) & MMD_DEVAD_M)); + ret = mtk_mii_write(priv, addr, MII_MMD_ACC_CTL_REG, + (MMD_DATA << MMD_CMD_S) | + ((devad << MMD_DEVAD_S) & MMD_DEVAD_M)); if (ret) return ret; - return priv->mii_read(priv, addr, MII_MMD_ADDR_DATA_REG); + return mtk_mii_read(priv, addr, MII_MMD_ADDR_DATA_REG); } /* Indirect MDIO clause 45 write via MII registers */ -static int mtk_mmd_ind_write(struct mtk_eth_priv *priv, u8 addr, u8 devad, - u16 reg, u16 val) +int mtk_mmd_ind_write(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg, + u16 val) { int ret; - ret = priv->mii_write(priv, addr, MII_MMD_ACC_CTL_REG, - (MMD_ADDR << MMD_CMD_S) | - ((devad << MMD_DEVAD_S) & MMD_DEVAD_M)); + ret = mtk_mii_write(priv, addr, MII_MMD_ACC_CTL_REG, + (MMD_ADDR << MMD_CMD_S) | + ((devad << MMD_DEVAD_S) & MMD_DEVAD_M)); if (ret) return ret; - ret = priv->mii_write(priv, addr, MII_MMD_ADDR_DATA_REG, reg); + ret = mtk_mii_write(priv, addr, MII_MMD_ADDR_DATA_REG, reg); if (ret) return ret; - ret = priv->mii_write(priv, addr, MII_MMD_ACC_CTL_REG, - (MMD_DATA << MMD_CMD_S) | - ((devad << MMD_DEVAD_S) & MMD_DEVAD_M)); + ret = mtk_mii_write(priv, addr, MII_MMD_ACC_CTL_REG, + (MMD_DATA << MMD_CMD_S) | + ((devad << MMD_DEVAD_S) & MMD_DEVAD_M)); if (ret) return ret; - return priv->mii_write(priv, addr, MII_MMD_ADDR_DATA_REG, val); -} - -/* - * MT7530 Internal Register Address Bits - * ------------------------------------------------------------------- - * | 15 14 13 12 11 10 9 8 7 6 | 5 4 3 2 | 1 0 | - * |----------------------------------------|---------------|--------| - * | Page Address | Reg Address | Unused | - * ------------------------------------------------------------------- - */ - -static int mt753x_reg_read(struct mtk_eth_priv *priv, u32 reg, u32 *data) -{ - int ret, low_word, high_word; - - if (priv->sw == SW_MT7988) { - *data = mtk_gsw_read(priv, reg); - return 0; - } - - /* Write page address */ - ret = mtk_mii_write(priv, priv->mt753x_smi_addr, 0x1f, reg >> 6); - if (ret) - return ret; - - /* Read low word */ - low_word = mtk_mii_read(priv, priv->mt753x_smi_addr, (reg >> 2) & 0xf); - if (low_word < 0) - return low_word; - - /* Read high word */ - high_word = mtk_mii_read(priv, priv->mt753x_smi_addr, 0x10); - if (high_word < 0) - return high_word; - - if (data) - *data = ((u32)high_word << 16) | (low_word & 0xffff); - - return 0; -} - -static int mt753x_reg_write(struct mtk_eth_priv *priv, u32 reg, u32 data) -{ - int ret; - - if (priv->sw == SW_MT7988) { - mtk_gsw_write(priv, reg, data); - return 0; - } - - /* Write page address */ - ret = mtk_mii_write(priv, priv->mt753x_smi_addr, 0x1f, reg >> 6); - if (ret) - return ret; - - /* Write low word */ - ret = mtk_mii_write(priv, priv->mt753x_smi_addr, (reg >> 2) & 0xf, - data & 0xffff); - if (ret) - return ret; - - /* Write high word */ - return mtk_mii_write(priv, priv->mt753x_smi_addr, 0x10, data >> 16); -} - -static void mt753x_reg_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, - u32 set) -{ - u32 val; - - mt753x_reg_read(priv, reg, &val); - val &= ~clr; - val |= set; - mt753x_reg_write(priv, reg, val); -} - -/* Indirect MDIO clause 22/45 access */ -static int mt7531_mii_rw(struct mtk_eth_priv *priv, int phy, int reg, u16 data, - u32 cmd, u32 st) -{ - ulong timeout; - u32 val, timeout_ms; - int ret = 0; - - val = (st << MDIO_ST_S) | - ((cmd << MDIO_CMD_S) & MDIO_CMD_M) | - ((phy << MDIO_PHY_ADDR_S) & MDIO_PHY_ADDR_M) | - ((reg << MDIO_REG_ADDR_S) & MDIO_REG_ADDR_M); - - if (cmd == MDIO_CMD_WRITE || cmd == MDIO_CMD_ADDR) - val |= data & MDIO_RW_DATA_M; - - mt753x_reg_write(priv, MT7531_PHY_IAC, val | PHY_ACS_ST); - - timeout_ms = 100; - timeout = get_timer(0); - while (1) { - mt753x_reg_read(priv, MT7531_PHY_IAC, &val); - - if ((val & PHY_ACS_ST) == 0) - break; - - if (get_timer(timeout) > timeout_ms) - return -ETIMEDOUT; - } - - if (cmd == MDIO_CMD_READ || cmd == MDIO_CMD_READ_C45) { - mt753x_reg_read(priv, MT7531_PHY_IAC, &val); - ret = val & MDIO_RW_DATA_M; - } - - return ret; -} - -static int mt7531_mii_ind_read(struct mtk_eth_priv *priv, u8 phy, u8 reg) -{ - u8 phy_addr; - - if (phy >= MT753X_NUM_PHYS) - return -EINVAL; - - phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, phy); - - return mt7531_mii_rw(priv, phy_addr, reg, 0, MDIO_CMD_READ, - MDIO_ST_C22); -} - -static int mt7531_mii_ind_write(struct mtk_eth_priv *priv, u8 phy, u8 reg, - u16 val) -{ - u8 phy_addr; - - if (phy >= MT753X_NUM_PHYS) - return -EINVAL; - - phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, phy); - - return mt7531_mii_rw(priv, phy_addr, reg, val, MDIO_CMD_WRITE, - MDIO_ST_C22); -} - -static int mt7531_mmd_ind_read(struct mtk_eth_priv *priv, u8 addr, u8 devad, - u16 reg) -{ - u8 phy_addr; - int ret; - - if (addr >= MT753X_NUM_PHYS) - return -EINVAL; - - phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, addr); - - ret = mt7531_mii_rw(priv, phy_addr, devad, reg, MDIO_CMD_ADDR, - MDIO_ST_C45); - if (ret) - return ret; - - return mt7531_mii_rw(priv, phy_addr, devad, 0, MDIO_CMD_READ_C45, - MDIO_ST_C45); -} - -static int mt7531_mmd_ind_write(struct mtk_eth_priv *priv, u8 addr, u8 devad, - u16 reg, u16 val) -{ - u8 phy_addr; - int ret; - - if (addr >= MT753X_NUM_PHYS) - return 0; - - phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, addr); - - ret = mt7531_mii_rw(priv, phy_addr, devad, reg, MDIO_CMD_ADDR, - MDIO_ST_C45); - if (ret) - return ret; - - return mt7531_mii_rw(priv, phy_addr, devad, val, MDIO_CMD_WRITE, - MDIO_ST_C45); + return mtk_mii_write(priv, addr, MII_MMD_ADDR_DATA_REG, val); } static int mtk_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) @@ -541,9 +305,9 @@ static int mtk_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) struct mtk_eth_priv *priv = bus->priv; if (devad < 0) - return priv->mii_read(priv, addr, reg); - else - return priv->mmd_read(priv, addr, devad, reg); + return mtk_mii_read(priv, addr, reg); + + return mtk_mmd_read(priv, addr, devad, reg); } static int mtk_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, @@ -552,9 +316,9 @@ static int mtk_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, struct mtk_eth_priv *priv = bus->priv; if (devad < 0) - return priv->mii_write(priv, addr, reg, val); - else - return priv->mmd_write(priv, addr, devad, reg, val); + return mtk_mii_write(priv, addr, reg, val); + + return mtk_mmd_write(priv, addr, devad, reg, val); } static int mtk_mdio_register(struct udevice *dev) @@ -566,28 +330,6 @@ static int mtk_mdio_register(struct udevice *dev) if (!mdio_bus) return -ENOMEM; - /* Assign MDIO access APIs according to the switch/phy */ - switch (priv->sw) { - case SW_MT7530: - priv->mii_read = mtk_mii_read; - priv->mii_write = mtk_mii_write; - priv->mmd_read = mtk_mmd_ind_read; - priv->mmd_write = mtk_mmd_ind_write; - break; - case SW_MT7531: - case SW_MT7988: - priv->mii_read = mt7531_mii_ind_read; - priv->mii_write = mt7531_mii_ind_write; - priv->mmd_read = mt7531_mmd_ind_read; - priv->mmd_write = mt7531_mmd_ind_write; - break; - default: - priv->mii_read = mtk_mii_read; - priv->mii_write = mtk_mii_write; - priv->mmd_read = mtk_mmd_read; - priv->mmd_write = mtk_mmd_write; - } - mdio_bus->read = mtk_mdio_read; mdio_bus->write = mtk_mdio_write; snprintf(mdio_bus->name, sizeof(mdio_bus->name), dev->name); @@ -604,531 +346,91 @@ static int mtk_mdio_register(struct udevice *dev) return 0; } -static int mt753x_core_reg_read(struct mtk_eth_priv *priv, u32 reg) -{ - u8 phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, 0); - - return priv->mmd_read(priv, phy_addr, 0x1f, reg); -} - -static void mt753x_core_reg_write(struct mtk_eth_priv *priv, u32 reg, u32 val) -{ - u8 phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, 0); - - priv->mmd_write(priv, phy_addr, 0x1f, reg, val); -} - -static int mt7530_pad_clk_setup(struct mtk_eth_priv *priv, int mode) -{ - u32 ncpo1, ssc_delta; - - switch (mode) { - case PHY_INTERFACE_MODE_RGMII: - ncpo1 = 0x0c80; - ssc_delta = 0x87; - break; - default: - printf("error: xMII mode %d not supported\n", mode); - return -EINVAL; - } - - /* Disable MT7530 core clock */ - mt753x_core_reg_write(priv, CORE_TRGMII_GSW_CLK_CG, 0); - - /* Disable MT7530 PLL */ - mt753x_core_reg_write(priv, CORE_GSWPLL_GRP1, - (2 << RG_GSWPLL_POSDIV_200M_S) | - (32 << RG_GSWPLL_FBKDIV_200M_S)); - - /* For MT7530 core clock = 500Mhz */ - mt753x_core_reg_write(priv, CORE_GSWPLL_GRP2, - (1 << RG_GSWPLL_POSDIV_500M_S) | - (25 << RG_GSWPLL_FBKDIV_500M_S)); - - /* Enable MT7530 PLL */ - mt753x_core_reg_write(priv, CORE_GSWPLL_GRP1, - (2 << RG_GSWPLL_POSDIV_200M_S) | - (32 << RG_GSWPLL_FBKDIV_200M_S) | - RG_GSWPLL_EN_PRE); - - udelay(20); - - mt753x_core_reg_write(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); - - /* Setup the MT7530 TRGMII Tx Clock */ - mt753x_core_reg_write(priv, CORE_PLL_GROUP5, ncpo1); - mt753x_core_reg_write(priv, CORE_PLL_GROUP6, 0); - mt753x_core_reg_write(priv, CORE_PLL_GROUP10, ssc_delta); - mt753x_core_reg_write(priv, CORE_PLL_GROUP11, ssc_delta); - mt753x_core_reg_write(priv, CORE_PLL_GROUP4, RG_SYSPLL_DDSFBK_EN | - RG_SYSPLL_BIAS_EN | RG_SYSPLL_BIAS_LPF_EN); - - mt753x_core_reg_write(priv, CORE_PLL_GROUP2, - RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN | - (1 << RG_SYSPLL_POSDIV_S)); - - mt753x_core_reg_write(priv, CORE_PLL_GROUP7, - RG_LCDDS_PCW_NCPO_CHG | (3 << RG_LCCDS_C_S) | - RG_LCDDS_PWDB | RG_LCDDS_ISO_EN); - - /* Enable MT7530 core clock */ - mt753x_core_reg_write(priv, CORE_TRGMII_GSW_CLK_CG, - REG_GSWCK_EN | REG_TRGMIICK_EN); - - return 0; -} - -static void mt7530_mac_control(struct mtk_eth_priv *priv, bool enable) -{ - u32 pmcr = FORCE_MODE; - - if (enable) - pmcr = priv->mt753x_pmcr; - - mt753x_reg_write(priv, PMCR_REG(6), pmcr); -} - -static int mt7530_setup(struct mtk_eth_priv *priv) -{ - u16 phy_addr, phy_val; - u32 val, txdrv; - int i; - - if (!MTK_HAS_CAPS(priv->soc->caps, MTK_TRGMII_MT7621_CLK)) { - /* Select 250MHz clk for RGMII mode */ - mtk_ethsys_rmw(priv, ETHSYS_CLKCFG0_REG, - ETHSYS_TRGMII_CLK_SEL362_5, 0); - - txdrv = 8; - } else { - txdrv = 4; - } - - /* Modify HWTRAP first to allow direct access to internal PHYs */ - mt753x_reg_read(priv, HWTRAP_REG, &val); - val |= CHG_TRAP; - val &= ~C_MDIO_BPS; - mt753x_reg_write(priv, MHWTRAP_REG, val); - - /* Calculate the phy base address */ - val = ((val & SMI_ADDR_M) >> SMI_ADDR_S) << 3; - priv->mt753x_phy_base = (val | 0x7) + 1; - - /* Turn off PHYs */ - for (i = 0; i < MT753X_NUM_PHYS; i++) { - phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, i); - phy_val = priv->mii_read(priv, phy_addr, MII_BMCR); - phy_val |= BMCR_PDOWN; - priv->mii_write(priv, phy_addr, MII_BMCR, phy_val); - } - - /* Force MAC link down before reset */ - mt753x_reg_write(priv, PMCR_REG(5), FORCE_MODE); - mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE); - - /* MT7530 reset */ - mt753x_reg_write(priv, SYS_CTRL_REG, SW_SYS_RST | SW_REG_RST); - udelay(100); - - val = (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) | - MAC_MODE | FORCE_MODE | - MAC_TX_EN | MAC_RX_EN | - BKOFF_EN | BACKPR_EN | - (SPEED_1000M << FORCE_SPD_S) | - FORCE_DPX | FORCE_LINK; - - /* MT7530 Port6: Forced 1000M/FD, FC disabled */ - priv->mt753x_pmcr = val; - - /* MT7530 Port5: Forced link down */ - mt753x_reg_write(priv, PMCR_REG(5), FORCE_MODE); - - /* Keep MAC link down before starting eth */ - mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE); - - /* MT7530 Port6: Set to RGMII */ - mt753x_reg_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_M, P6_INTF_MODE_RGMII); - - /* Hardware Trap: Enable Port6, Disable Port5 */ - mt753x_reg_read(priv, HWTRAP_REG, &val); - val |= CHG_TRAP | LOOPDET_DIS | P5_INTF_DIS | - (P5_INTF_SEL_GMAC5 << P5_INTF_SEL_S) | - (P5_INTF_MODE_RGMII << P5_INTF_MODE_S); - val &= ~(C_MDIO_BPS | P6_INTF_DIS); - mt753x_reg_write(priv, MHWTRAP_REG, val); - - /* Setup switch core pll */ - mt7530_pad_clk_setup(priv, priv->phy_interface); - - /* Lower Tx Driving for TRGMII path */ - for (i = 0 ; i < NUM_TRGMII_CTRL ; i++) - mt753x_reg_write(priv, MT7530_TRGMII_TD_ODT(i), - (txdrv << TD_DM_DRVP_S) | - (txdrv << TD_DM_DRVN_S)); - - for (i = 0 ; i < NUM_TRGMII_CTRL; i++) - mt753x_reg_rmw(priv, MT7530_TRGMII_RD(i), RD_TAP_M, 16); - - /* Turn on PHYs */ - for (i = 0; i < MT753X_NUM_PHYS; i++) { - phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, i); - phy_val = priv->mii_read(priv, phy_addr, MII_BMCR); - phy_val &= ~BMCR_PDOWN; - priv->mii_write(priv, phy_addr, MII_BMCR, phy_val); - } - - return 0; -} - -static void mt7531_core_pll_setup(struct mtk_eth_priv *priv, int mcm) +static int mtk_switch_init(struct mtk_eth_priv *priv) { - /* Step 1 : Disable MT7531 COREPLL */ - mt753x_reg_rmw(priv, MT7531_PLLGP_EN, EN_COREPLL, 0); - - /* Step 2: switch to XTAL output */ - mt753x_reg_rmw(priv, MT7531_PLLGP_EN, SW_CLKSW, SW_CLKSW); - - mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_EN, 0); - - /* Step 3: disable PLLGP and enable program PLLGP */ - mt753x_reg_rmw(priv, MT7531_PLLGP_EN, SW_PLLGP, SW_PLLGP); - - /* Step 4: program COREPLL output frequency to 500MHz */ - mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_POSDIV_M, - 2 << RG_COREPLL_POSDIV_S); - udelay(25); - - /* Currently, support XTAL 25Mhz only */ - mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_SDM_PCW_M, - 0x140000 << RG_COREPLL_SDM_PCW_S); - - /* Set feedback divide ratio update signal to high */ - mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_SDM_PCW_CHG, - RG_COREPLL_SDM_PCW_CHG); - - /* Wait for at least 16 XTAL clocks */ - udelay(10); - - /* Step 5: set feedback divide ratio update signal to low */ - mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_SDM_PCW_CHG, 0); - - /* add enable 325M clock for SGMII */ - mt753x_reg_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000); - - /* add enable 250SSC clock for RGMII */ - mt753x_reg_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000); - - /*Step 6: Enable MT7531 PLL */ - mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_EN, RG_COREPLL_EN); - - mt753x_reg_rmw(priv, MT7531_PLLGP_EN, EN_COREPLL, EN_COREPLL); - - udelay(25); -} - -static int mt7531_port_sgmii_init(struct mtk_eth_priv *priv, - u32 port) -{ - if (port != 5 && port != 6) { - printf("mt7531: port %d is not a SGMII port\n", port); - return -EINVAL; - } - - /* Set SGMII GEN2 speed(2.5G) */ - mt753x_reg_rmw(priv, MT7531_PHYA_CTRL_SIGNAL3(port), SGMSYS_SPEED_MASK, - FIELD_PREP(SGMSYS_SPEED_MASK, SGMSYS_SPEED_2500)); - - /* Disable SGMII AN */ - mt753x_reg_rmw(priv, MT7531_PCS_CONTROL_1(port), - SGMII_AN_ENABLE, 0); - - /* SGMII force mode setting */ - mt753x_reg_write(priv, MT7531_SGMII_MODE(port), SGMII_FORCE_MODE); - - /* Release PHYA power down state */ - mt753x_reg_rmw(priv, MT7531_QPHY_PWR_STATE_CTRL(port), - SGMII_PHYA_PWD, 0); - - return 0; -} - -static int mt7531_port_rgmii_init(struct mtk_eth_priv *priv, u32 port) -{ - u32 val; - - if (port != 5) { - printf("error: RGMII mode is not available for port %d\n", - port); - return -EINVAL; - } - - mt753x_reg_read(priv, MT7531_CLKGEN_CTRL, &val); - val |= GP_CLK_EN; - val &= ~GP_MODE_M; - val |= GP_MODE_RGMII << GP_MODE_S; - val |= TXCLK_NO_REVERSE; - val |= RXCLK_NO_DELAY; - val &= ~CLK_SKEW_IN_M; - val |= CLK_SKEW_IN_NO_CHANGE << CLK_SKEW_IN_S; - val &= ~CLK_SKEW_OUT_M; - val |= CLK_SKEW_OUT_NO_CHANGE << CLK_SKEW_OUT_S; - mt753x_reg_write(priv, MT7531_CLKGEN_CTRL, val); - - return 0; -} - -static void mt7531_phy_setting(struct mtk_eth_priv *priv) -{ - int i; - u32 val; - - for (i = 0; i < MT753X_NUM_PHYS; i++) { - /* Enable HW auto downshift */ - priv->mii_write(priv, i, 0x1f, 0x1); - val = priv->mii_read(priv, i, PHY_EXT_REG_14); - val |= PHY_EN_DOWN_SHFIT; - priv->mii_write(priv, i, PHY_EXT_REG_14, val); - - /* PHY link down power saving enable */ - val = priv->mii_read(priv, i, PHY_EXT_REG_17); - val |= PHY_LINKDOWN_POWER_SAVING_EN; - priv->mii_write(priv, i, PHY_EXT_REG_17, val); - - val = priv->mmd_read(priv, i, 0x1e, PHY_DEV1E_REG_0C6); - val &= ~PHY_POWER_SAVING_M; - val |= PHY_POWER_SAVING_TX << PHY_POWER_SAVING_S; - priv->mmd_write(priv, i, 0x1e, PHY_DEV1E_REG_0C6, val); - } -} - -static void mt7531_mac_control(struct mtk_eth_priv *priv, bool enable) -{ - u32 pmcr = FORCE_MODE_LNK; - - if (enable) - pmcr = priv->mt753x_pmcr; - - mt753x_reg_write(priv, PMCR_REG(5), pmcr); - mt753x_reg_write(priv, PMCR_REG(6), pmcr); -} - -static int mt7531_setup(struct mtk_eth_priv *priv) -{ - u16 phy_addr, phy_val; - u32 val; - u32 pmcr; - u32 port5_sgmii; - int i; - - priv->mt753x_phy_base = (priv->mt753x_smi_addr + 1) & - MT753X_SMI_ADDR_MASK; - - /* Turn off PHYs */ - for (i = 0; i < MT753X_NUM_PHYS; i++) { - phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, i); - phy_val = priv->mii_read(priv, phy_addr, MII_BMCR); - phy_val |= BMCR_PDOWN; - priv->mii_write(priv, phy_addr, MII_BMCR, phy_val); - } - - /* Force MAC link down before reset */ - mt753x_reg_write(priv, PMCR_REG(5), FORCE_MODE_LNK); - mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE_LNK); - - /* Switch soft reset */ - mt753x_reg_write(priv, SYS_CTRL_REG, SW_SYS_RST | SW_REG_RST); - udelay(100); - - /* Enable MDC input Schmitt Trigger */ - mt753x_reg_rmw(priv, MT7531_SMT0_IOLB, SMT_IOLB_5_SMI_MDC_EN, - SMT_IOLB_5_SMI_MDC_EN); - - mt7531_core_pll_setup(priv, priv->mcm); - - mt753x_reg_read(priv, MT7531_TOP_SIG_SR, &val); - port5_sgmii = !!(val & PAD_DUAL_SGMII_EN); - - /* port5 support either RGMII or SGMII, port6 only support SGMII. */ - switch (priv->phy_interface) { - case PHY_INTERFACE_MODE_RGMII: - if (!port5_sgmii) - mt7531_port_rgmii_init(priv, 5); - break; - case PHY_INTERFACE_MODE_2500BASEX: - mt7531_port_sgmii_init(priv, 6); - if (port5_sgmii) - mt7531_port_sgmii_init(priv, 5); - break; - default: - break; - } - - pmcr = MT7531_FORCE_MODE | - (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) | - MAC_MODE | MAC_TX_EN | MAC_RX_EN | - BKOFF_EN | BACKPR_EN | - FORCE_RX_FC | FORCE_TX_FC | - (SPEED_1000M << FORCE_SPD_S) | FORCE_DPX | - FORCE_LINK; - - priv->mt753x_pmcr = pmcr; - - /* Keep MAC link down before starting eth */ - mt753x_reg_write(priv, PMCR_REG(5), FORCE_MODE_LNK); - mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE_LNK); - - /* Turn on PHYs */ - for (i = 0; i < MT753X_NUM_PHYS; i++) { - phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, i); - phy_val = priv->mii_read(priv, phy_addr, MII_BMCR); - phy_val &= ~BMCR_PDOWN; - priv->mii_write(priv, phy_addr, MII_BMCR, phy_val); - } - - mt7531_phy_setting(priv); - - /* Enable Internal PHYs */ - val = mt753x_core_reg_read(priv, CORE_PLL_GROUP4); - val |= MT7531_BYPASS_MODE; - val &= ~MT7531_POWER_ON_OFF; - mt753x_core_reg_write(priv, CORE_PLL_GROUP4, val); - - return 0; -} - -static void mt7988_phy_setting(struct mtk_eth_priv *priv) -{ - u16 val; - u32 i; - - for (i = 0; i < MT753X_NUM_PHYS; i++) { - /* Enable HW auto downshift */ - priv->mii_write(priv, i, 0x1f, 0x1); - val = priv->mii_read(priv, i, PHY_EXT_REG_14); - val |= PHY_EN_DOWN_SHFIT; - priv->mii_write(priv, i, PHY_EXT_REG_14, val); - - /* PHY link down power saving enable */ - val = priv->mii_read(priv, i, PHY_EXT_REG_17); - val |= PHY_LINKDOWN_POWER_SAVING_EN; - priv->mii_write(priv, i, PHY_EXT_REG_17, val); - } -} - -static void mt7988_mac_control(struct mtk_eth_priv *priv, bool enable) -{ - u32 pmcr = FORCE_MODE_LNK; - - if (enable) - pmcr = priv->mt753x_pmcr; - - mt753x_reg_write(priv, PMCR_REG(6), pmcr); -} - -static int mt7988_setup(struct mtk_eth_priv *priv) -{ - u16 phy_addr, phy_val; - u32 pmcr; - int i; - - priv->gsw_base = regmap_get_range(priv->ethsys_regmap, 0) + GSW_BASE; - - priv->mt753x_phy_base = (priv->mt753x_smi_addr + 1) & - MT753X_SMI_ADDR_MASK; - - /* Turn off PHYs */ - for (i = 0; i < MT753X_NUM_PHYS; i++) { - phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, i); - phy_val = priv->mii_read(priv, phy_addr, MII_BMCR); - phy_val |= BMCR_PDOWN; - priv->mii_write(priv, phy_addr, MII_BMCR, phy_val); - } - - switch (priv->phy_interface) { - case PHY_INTERFACE_MODE_USXGMII: - /* Use CPU bridge instead of actual USXGMII path */ - - /* Set GDM1 no drop */ - mtk_fe_rmw(priv, PSE_NO_DROP_CFG_REG, 0, PSE_NO_DROP_GDM1); - - /* Enable GDM1 to GSW CPU bridge */ - mtk_gmac_rmw(priv, GMAC_MAC_MISC_REG, 0, BIT(0)); - - /* XGMAC force link up */ - mtk_gmac_rmw(priv, GMAC_XGMAC_STS_REG, 0, P1_XGMAC_FORCE_LINK); - - /* Setup GSW CPU bridge IPG */ - mtk_gmac_rmw(priv, GMAC_GSW_CFG_REG, GSWTX_IPG_M | GSWRX_IPG_M, - (0xB << GSWTX_IPG_S) | (0xB << GSWRX_IPG_S)); - break; - default: - printf("Error: MT7988 GSW does not support %s interface\n", - phy_string_for_interface(priv->phy_interface)); - break; - } + struct mtk_eth_switch *swdrvs = ll_entry_start(struct mtk_eth_switch, + mtk_eth_switch); + const u32 n_swdrvs = ll_entry_count(struct mtk_eth_switch, + mtk_eth_switch); + struct mtk_eth_switch *tmp, *swdrv = NULL; + u32 reset_wait_time = 500; + size_t priv_size; + int ret; - pmcr = MT7988_FORCE_MODE | - (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) | - MAC_MODE | MAC_TX_EN | MAC_RX_EN | - BKOFF_EN | BACKPR_EN | - FORCE_RX_FC | FORCE_TX_FC | - (SPEED_1000M << FORCE_SPD_S) | FORCE_DPX | - FORCE_LINK; - - priv->mt753x_pmcr = pmcr; - - /* Keep MAC link down before starting eth */ - mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE_LNK); - - /* Turn on PHYs */ - for (i = 0; i < MT753X_NUM_PHYS; i++) { - phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, i); - phy_val = priv->mii_read(priv, phy_addr, MII_BMCR); - phy_val &= ~BMCR_PDOWN; - priv->mii_write(priv, phy_addr, MII_BMCR, phy_val); + if (strcmp(priv->swname, "auto")) { + for (tmp = swdrvs; tmp < swdrvs + n_swdrvs; tmp++) { + if (!strcmp(tmp->name, priv->swname)) { + swdrv = tmp; + break; + } + } } - mt7988_phy_setting(priv); - - return 0; -} - -static int mt753x_switch_init(struct mtk_eth_priv *priv) -{ - int ret; - int i; + if (swdrv) + reset_wait_time = swdrv->reset_wait_time; /* Global reset switch */ if (priv->mcm) { reset_assert(&priv->rst_mcm); udelay(1000); reset_deassert(&priv->rst_mcm); - mdelay(priv->mt753x_reset_wait_time); + mdelay(reset_wait_time); } else if (dm_gpio_is_valid(&priv->rst_gpio)) { dm_gpio_set_value(&priv->rst_gpio, 0); udelay(1000); dm_gpio_set_value(&priv->rst_gpio, 1); - mdelay(priv->mt753x_reset_wait_time); + mdelay(reset_wait_time); } - ret = priv->switch_init(priv); - if (ret) - return ret; + if (!swdrv) { + for (tmp = swdrvs; tmp < swdrvs + n_swdrvs; tmp++) { + if (!tmp->detect) + continue; - /* Set port isolation */ - for (i = 0; i < MT753X_NUM_PORTS; i++) { - /* Set port matrix mode */ - if (i != 6) - mt753x_reg_write(priv, PCR_REG(i), - (0x40 << PORT_MATRIX_S)); - else - mt753x_reg_write(priv, PCR_REG(i), - (0x3f << PORT_MATRIX_S)); + ret = tmp->detect(priv); + if (!ret) { + swdrv = tmp; + break; + } + } + + if (!swdrv) { + printf("Error: unable to detect switch\n"); + return -ENODEV; + } + } else { + if (swdrv->detect) { + ret = swdrv->detect(priv); + if (ret) { + printf("Error: switch probing failed\n"); + return -ENODEV; + } + } + } + + printf("%s\n", swdrv->desc); + + priv_size = swdrv->priv_size; + if (priv_size < sizeof(struct mtk_eth_switch_priv)) + priv_size = sizeof(struct mtk_eth_switch_priv); + + priv->swpriv = calloc(1, priv_size); + if (!priv->swpriv) { + printf("Error: no memory for switch data\n"); + return -ENOMEM; + } + + priv->swpriv->eth = priv; + priv->swpriv->soc = priv->soc; + priv->swpriv->phy_interface = priv->phy_interface; + priv->swpriv->sw = swdrv; + priv->swpriv->ethsys_base = regmap_get_range(priv->ethsys_regmap, 0); - /* Set port mode to user port */ - mt753x_reg_write(priv, PVC_REG(i), - (0x8100 << STAG_VPID_S) | - (VLAN_ATTR_USER << VLAN_ATTR_S)); + ret = swdrv->setup(priv->swpriv); + if (ret) { + free(priv->swpriv); + priv->swpriv = NULL; + return ret; } return 0; @@ -1759,7 +1061,8 @@ static int mtk_eth_start(struct udevice *dev) } if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3)) { - if (priv->sw == SW_MT7988 && priv->gmac_id == 0) { + if (priv->swpriv && !strcmp(priv->swpriv->sw->name, "mt7988") && + priv->gmac_id == 0) { mtk_gdma_write(priv, priv->gmac_id, GDMA_IG_CTRL_REG, GDMA_BRIDGE_TO_CPU); @@ -1778,11 +1081,12 @@ static int mtk_eth_start(struct udevice *dev) mtk_eth_fifo_init(priv); - if (priv->switch_mac_control) - priv->switch_mac_control(priv, true); - - /* Start PHY */ - if (priv->sw == SW_NONE) { + if (priv->swpriv) { + /* Enable communication with switch */ + if (priv->swpriv->sw->mac_control) + priv->swpriv->sw->mac_control(priv->swpriv, true); + } else { + /* Start PHY */ ret = mtk_phy_start(priv); if (ret) return ret; @@ -1799,8 +1103,10 @@ static void mtk_eth_stop(struct udevice *dev) { struct mtk_eth_priv *priv = dev_get_priv(dev); - if (priv->switch_mac_control) - priv->switch_mac_control(priv, false); + if (priv->swpriv) { + if (priv->swpriv->sw->mac_control) + priv->swpriv->sw->mac_control(priv->swpriv, false); + } mtk_pdma_rmw(priv, PDMA_GLO_CFG_REG, TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN, 0); @@ -1953,11 +1259,11 @@ static int mtk_eth_probe(struct udevice *dev) return ret; /* Probe phy if switch is not specified */ - if (priv->sw == SW_NONE) + if (!priv->swname) return mtk_phy_probe(dev); /* Initialize switch */ - return mt753x_switch_init(priv); + return mtk_switch_init(priv); } static int mtk_eth_remove(struct udevice *dev) @@ -1971,6 +1277,12 @@ static int mtk_eth_remove(struct udevice *dev) /* Stop possibly started DMA */ mtk_eth_stop(dev); + if (priv->swpriv) { + if (priv->swpriv->sw->cleanup) + priv->swpriv->sw->cleanup(priv->swpriv); + free(priv->swpriv); + } + return 0; } @@ -1980,7 +1292,6 @@ static int mtk_eth_of_to_plat(struct udevice *dev) struct mtk_eth_priv *priv = dev_get_priv(dev); struct ofnode_phandle_args args; struct regmap *regmap; - const char *str; ofnode subnode; int ret; @@ -2126,36 +1437,8 @@ static int mtk_eth_of_to_plat(struct udevice *dev) return PTR_ERR(priv->toprgu_regmap); } - /* check for switch first, otherwise phy will be used */ - priv->sw = SW_NONE; - priv->switch_init = NULL; - priv->switch_mac_control = NULL; - str = dev_read_string(dev, "mediatek,switch"); - - if (str) { - if (!strcmp(str, "mt7530")) { - priv->sw = SW_MT7530; - priv->switch_init = mt7530_setup; - priv->switch_mac_control = mt7530_mac_control; - priv->mt753x_smi_addr = MT753X_DFL_SMI_ADDR; - priv->mt753x_reset_wait_time = 1000; - } else if (!strcmp(str, "mt7531")) { - priv->sw = SW_MT7531; - priv->switch_init = mt7531_setup; - priv->switch_mac_control = mt7531_mac_control; - priv->mt753x_smi_addr = MT753X_DFL_SMI_ADDR; - priv->mt753x_reset_wait_time = 200; - } else if (!strcmp(str, "mt7988")) { - priv->sw = SW_MT7988; - priv->switch_init = mt7988_setup; - priv->switch_mac_control = mt7988_mac_control; - priv->mt753x_smi_addr = MT753X_DFL_SMI_ADDR; - priv->mt753x_reset_wait_time = 50; - } else { - printf("error: unsupported switch\n"); - return -EINVAL; - } - + priv->swname = dev_read_string(dev, "mediatek,switch"); + if (priv->swname) { priv->mcm = dev_read_bool(dev, "mediatek,mcm"); if (priv->mcm) { ret = reset_get_by_name(dev, "mcm", &priv->rst_mcm); @@ -2194,6 +1477,15 @@ static const struct mtk_soc_data mt7988_data = { .rxd_size = sizeof(struct mtk_rx_dma_v2), }; +static const struct mtk_soc_data mt7987_data = { + .caps = MT7987_CAPS, + .ana_rgc3 = 0x128, + .gdma_count = 3, + .pdma_base = PDMA_V3_BASE, + .txd_size = sizeof(struct mtk_tx_dma_v2), + .rxd_size = sizeof(struct mtk_rx_dma_v2), +}; + static const struct mtk_soc_data mt7986_data = { .caps = MT7986_CAPS, .ana_rgc3 = 0x128, @@ -2248,6 +1540,7 @@ static const struct mtk_soc_data mt7621_data = { static const struct udevice_id mtk_eth_ids[] = { { .compatible = "mediatek,mt7988-eth", .data = (ulong)&mt7988_data }, + { .compatible = "mediatek,mt7987-eth", .data = (ulong)&mt7987_data }, { .compatible = "mediatek,mt7986-eth", .data = (ulong)&mt7986_data }, { .compatible = "mediatek,mt7981-eth", .data = (ulong)&mt7981_data }, { .compatible = "mediatek,mt7629-eth", .data = (ulong)&mt7629_data }, @@ -2271,10 +1564,10 @@ U_BOOT_DRIVER(mtk_eth) = { .id = UCLASS_ETH, .of_match = mtk_eth_ids, .of_to_plat = mtk_eth_of_to_plat, - .plat_auto = sizeof(struct eth_pdata), + .plat_auto = sizeof(struct eth_pdata), .probe = mtk_eth_probe, .remove = mtk_eth_remove, .ops = &mtk_eth_ops, - .priv_auto = sizeof(struct mtk_eth_priv), + .priv_auto = sizeof(struct mtk_eth_priv), .flags = DM_FLAG_ALLOC_PRIV_DMA, }; diff --git a/drivers/net/mtk_eth.h b/drivers/net/mtk_eth/mtk_eth.h index 1aa037907c5..0ad32799128 100644 --- a/drivers/net/mtk_eth.h +++ b/drivers/net/mtk_eth/mtk_eth.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2018 MediaTek Inc. + * Copyright (C) 2025 MediaTek Inc. * * Author: Weijie Gao <weijie.gao@mediatek.com> * Author: Mark Lee <mark-mc.lee@mediatek.com> @@ -9,9 +9,55 @@ #ifndef _MTK_ETH_H_ #define _MTK_ETH_H_ +#include <linker_lists.h> #include <linux/bitops.h> #include <linux/bitfield.h> +struct mtk_eth_priv; +struct mtk_eth_switch_priv; + +/* struct mtk_soc_data - This is the structure holding all differences + * among various plaforms + * @caps Flags shown the extra capability for the SoC + * @ana_rgc3: The offset for register ANA_RGC3 related to + * sgmiisys syscon + * @gdma_count: Number of GDMAs + * @pdma_base: Register base of PDMA block + * @txd_size: Tx DMA descriptor size. + * @rxd_size: Rx DMA descriptor size. + */ +struct mtk_soc_data { + u32 caps; + u32 ana_rgc3; + u32 gdma_count; + u32 pdma_base; + u32 txd_size; + u32 rxd_size; +}; + +struct mtk_eth_switch { + const char *name; + const char *desc; + size_t priv_size; + u32 reset_wait_time; + + int (*detect)(struct mtk_eth_priv *priv); + int (*setup)(struct mtk_eth_switch_priv *priv); + int (*cleanup)(struct mtk_eth_switch_priv *priv); + void (*mac_control)(struct mtk_eth_switch_priv *priv, bool enable); +}; + +#define MTK_ETH_SWITCH(__name) \ + ll_entry_declare(struct mtk_eth_switch, __name, mtk_eth_switch) + +struct mtk_eth_switch_priv { + struct mtk_eth_priv *eth; + const struct mtk_eth_switch *sw; + const struct mtk_soc_data *soc; + void *ethsys_base; + int phy_interface; +}; + enum mkt_eth_capabilities { MTK_TRGMII_BIT, MTK_TRGMII_MT7621_CLK_BIT, @@ -36,7 +82,6 @@ enum mkt_eth_capabilities { /* Supported path present on SoCs */ #define MTK_ETH_PATH_GMAC1_TRGMII BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT) - #define MTK_ETH_PATH_GMAC2_SGMII BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT) #define MTK_ETH_PATH_MT7622_SGMII BIT(MTK_ETH_PATH_MT7622_SGMII_BIT) #define MTK_ETH_PATH_MT7629_GMAC2 BIT(MTK_ETH_PATH_MT7629_GMAC2_BIT) @@ -59,6 +104,8 @@ enum mkt_eth_capabilities { #define MT7986_CAPS (MTK_NETSYS_V2) +#define MT7987_CAPS (MTK_NETSYS_V3 | MTK_GMAC2_U3_QPHY | MTK_INFRA) + #define MT7988_CAPS (MTK_NETSYS_V3 | MTK_INFRA) /* Frame Engine Register Bases */ @@ -72,7 +119,6 @@ enum mkt_eth_capabilities { #define GSW_BASE 0x20000 /* Ethernet subsystem registers */ - #define ETHSYS_SYSCFG1_REG 0x14 #define SYSCFG1_GE_MODE_S(n) (12 + ((n) * 2)) #define SYSCFG1_GE_MODE_M 0x3 @@ -191,7 +237,6 @@ enum mkt_eth_capabilities { #define DP_DISCARD 7 /* GMAC Registers */ - #define GMAC_PPSC_REG 0x0000 #define PHY_MDC_CFG GENMASK(29, 24) #define MDC_TURBO BIT(20) @@ -272,6 +317,8 @@ enum mkt_eth_capabilities { #define RX_RST BIT(31) #define RXC_DQSISEL BIT(30) +#define NUM_TRGMII_CTRL 5 + #define GMAC_TRGMII_TD_ODT(n) (0x354 + (n) * 8) #define TD_DM_DRVN_S 4 #define TD_DM_DRVN_M 0xf0 @@ -288,164 +335,7 @@ enum mkt_eth_capabilities { #define XGMAC_FORCE_TX_FC BIT(5) #define XGMAC_FORCE_RX_FC BIT(4) -/* MT7530 Registers */ - -#define PCR_REG(p) (0x2004 + (p) * 0x100) -#define PORT_MATRIX_S 16 -#define PORT_MATRIX_M 0xff0000 - -#define PVC_REG(p) (0x2010 + (p) * 0x100) -#define STAG_VPID_S 16 -#define STAG_VPID_M 0xffff0000 -#define VLAN_ATTR_S 6 -#define VLAN_ATTR_M 0xc0 - -/* VLAN_ATTR: VLAN attributes */ -#define VLAN_ATTR_USER 0 -#define VLAN_ATTR_STACK 1 -#define VLAN_ATTR_TRANSLATION 2 -#define VLAN_ATTR_TRANSPARENT 3 - -#define PMCR_REG(p) (0x3000 + (p) * 0x100) -/* XXX: all fields of MT7530 are defined under GMAC_PORT_MCR - * MT7531 specific fields are defined below - */ -#define FORCE_MODE_EEE1G BIT(25) -#define FORCE_MODE_EEE100 BIT(26) -#define FORCE_MODE_TX_FC BIT(27) -#define FORCE_MODE_RX_FC BIT(28) -#define FORCE_MODE_DPX BIT(29) -#define FORCE_MODE_SPD BIT(30) -#define FORCE_MODE_LNK BIT(31) -#define MT7531_FORCE_MODE FORCE_MODE_EEE1G | FORCE_MODE_EEE100 |\ - FORCE_MODE_TX_FC | FORCE_MODE_RX_FC | \ - FORCE_MODE_DPX | FORCE_MODE_SPD | \ - FORCE_MODE_LNK -#define MT7988_FORCE_MODE FORCE_MODE_TX_FC | FORCE_MODE_RX_FC | \ - FORCE_MODE_DPX | FORCE_MODE_SPD | \ - FORCE_MODE_LNK - -/* MT7531 SGMII Registers */ -#define MT7531_SGMII_REG_BASE 0x5000 -#define MT7531_SGMII_REG_PORT_BASE 0x1000 -#define MT7531_SGMII_REG(p, r) (MT7531_SGMII_REG_BASE + \ - (p) * MT7531_SGMII_REG_PORT_BASE + (r)) -#define MT7531_PCS_CONTROL_1(p) MT7531_SGMII_REG(((p) - 5), 0x00) -#define MT7531_SGMII_MODE(p) MT7531_SGMII_REG(((p) - 5), 0x20) -#define MT7531_QPHY_PWR_STATE_CTRL(p) MT7531_SGMII_REG(((p) - 5), 0xe8) -#define MT7531_PHYA_CTRL_SIGNAL3(p) MT7531_SGMII_REG(((p) - 5), 0x128) -/* XXX: all fields of MT7531 SGMII are defined under SGMSYS */ - -/* MT753x System Control Register */ -#define SYS_CTRL_REG 0x7000 -#define SW_PHY_RST BIT(2) -#define SW_SYS_RST BIT(1) -#define SW_REG_RST BIT(0) - -/* MT7531 */ -#define MT7531_PHY_IAC 0x701c -/* XXX: all fields are defined under GMAC_PIAC_REG */ - -#define MT7531_CLKGEN_CTRL 0x7500 -#define CLK_SKEW_OUT_S 8 -#define CLK_SKEW_OUT_M 0x300 -#define CLK_SKEW_IN_S 6 -#define CLK_SKEW_IN_M 0xc0 -#define RXCLK_NO_DELAY BIT(5) -#define TXCLK_NO_REVERSE BIT(4) -#define GP_MODE_S 1 -#define GP_MODE_M 0x06 -#define GP_CLK_EN BIT(0) - -/* Values of GP_MODE */ -#define GP_MODE_RGMII 0 -#define GP_MODE_MII 1 -#define GP_MODE_REV_MII 2 - -/* Values of CLK_SKEW_IN */ -#define CLK_SKEW_IN_NO_CHANGE 0 -#define CLK_SKEW_IN_DELAY_100PPS 1 -#define CLK_SKEW_IN_DELAY_200PPS 2 -#define CLK_SKEW_IN_REVERSE 3 - -/* Values of CLK_SKEW_OUT */ -#define CLK_SKEW_OUT_NO_CHANGE 0 -#define CLK_SKEW_OUT_DELAY_100PPS 1 -#define CLK_SKEW_OUT_DELAY_200PPS 2 -#define CLK_SKEW_OUT_REVERSE 3 - -#define HWTRAP_REG 0x7800 -/* MT7530 Modified Hardware Trap Status Registers */ -#define MHWTRAP_REG 0x7804 -#define CHG_TRAP BIT(16) -#define LOOPDET_DIS BIT(14) -#define P5_INTF_SEL_S 13 -#define P5_INTF_SEL_M 0x2000 -#define SMI_ADDR_S 11 -#define SMI_ADDR_M 0x1800 -#define XTAL_FSEL_S 9 -#define XTAL_FSEL_M 0x600 -#define P6_INTF_DIS BIT(8) -#define P5_INTF_MODE_S 7 -#define P5_INTF_MODE_M 0x80 -#define P5_INTF_DIS BIT(6) -#define C_MDIO_BPS BIT(5) -#define CHIP_MODE_S 0 -#define CHIP_MODE_M 0x0f - -/* P5_INTF_SEL: Interface type of Port5 */ -#define P5_INTF_SEL_GPHY 0 -#define P5_INTF_SEL_GMAC5 1 - -/* P5_INTF_MODE: Interface mode of Port5 */ -#define P5_INTF_MODE_GMII_MII 0 -#define P5_INTF_MODE_RGMII 1 - -#define MT7530_P6ECR 0x7830 -#define P6_INTF_MODE_M 0x3 -#define P6_INTF_MODE_S 0 - -/* P6_INTF_MODE: Interface mode of Port6 */ -#define P6_INTF_MODE_RGMII 0 -#define P6_INTF_MODE_TRGMII 1 - -#define NUM_TRGMII_CTRL 5 - -#define MT7530_TRGMII_RD(n) (0x7a10 + (n) * 8) -#define RD_TAP_S 0 -#define RD_TAP_M 0x7f - -#define MT7530_TRGMII_TD_ODT(n) (0x7a54 + (n) * 8) -/* XXX: all fields are defined under GMAC_TRGMII_TD_ODT */ - -/* TOP Signals Status Register */ -#define MT7531_TOP_SIG_SR 0x780c -#define PAD_MCM_SMI_EN BIT(0) -#define PAD_DUAL_SGMII_EN BIT(1) - -/* MT7531 PLLGP Registers */ -#define MT7531_PLLGP_EN 0x7820 -#define EN_COREPLL BIT(2) -#define SW_CLKSW BIT(1) -#define SW_PLLGP BIT(0) - -#define MT7531_PLLGP_CR0 0x78a8 -#define RG_COREPLL_EN BIT(22) -#define RG_COREPLL_POSDIV_S 23 -#define RG_COREPLL_POSDIV_M 0x3800000 -#define RG_COREPLL_SDM_PCW_S 1 -#define RG_COREPLL_SDM_PCW_M 0x3ffffe -#define RG_COREPLL_SDM_PCW_CHG BIT(0) - -/* MT7531 RGMII and SGMII PLL clock */ -#define MT7531_ANA_PLLGP_CR2 0x78b0 -#define MT7531_ANA_PLLGP_CR5 0x78bc - -/* MT7531 GPIO GROUP IOLB SMT0 Control */ -#define MT7531_SMT0_IOLB 0x7f04 -#define SMT_IOLB_5_SMI_MDC_EN BIT(5) - -/* MT7530 GPHY MDIO Indirect Access Registers */ +/* MDIO Indirect Access Registers */ #define MII_MMD_ACC_CTL_REG 0x0d #define MMD_CMD_S 14 #define MMD_CMD_M 0xc000 @@ -460,80 +350,6 @@ enum mkt_eth_capabilities { #define MII_MMD_ADDR_DATA_REG 0x0e -/* MT7530 GPHY MDIO MMD Registers */ -#define CORE_PLL_GROUP2 0x401 -#define RG_SYSPLL_EN_NORMAL BIT(15) -#define RG_SYSPLL_VODEN BIT(14) -#define RG_SYSPLL_POSDIV_S 5 -#define RG_SYSPLL_POSDIV_M 0x60 - -#define CORE_PLL_GROUP4 0x403 -#define MT7531_BYPASS_MODE BIT(4) -#define MT7531_POWER_ON_OFF BIT(5) -#define RG_SYSPLL_DDSFBK_EN BIT(12) -#define RG_SYSPLL_BIAS_EN BIT(11) -#define RG_SYSPLL_BIAS_LPF_EN BIT(10) - -#define CORE_PLL_GROUP5 0x404 -#define RG_LCDDS_PCW_NCPO1_S 0 -#define RG_LCDDS_PCW_NCPO1_M 0xffff - -#define CORE_PLL_GROUP6 0x405 -#define RG_LCDDS_PCW_NCPO0_S 0 -#define RG_LCDDS_PCW_NCPO0_M 0xffff - -#define CORE_PLL_GROUP7 0x406 -#define RG_LCDDS_PWDB BIT(15) -#define RG_LCDDS_ISO_EN BIT(13) -#define RG_LCCDS_C_S 4 -#define RG_LCCDS_C_M 0x70 -#define RG_LCDDS_PCW_NCPO_CHG BIT(3) - -#define CORE_PLL_GROUP10 0x409 -#define RG_LCDDS_SSC_DELTA_S 0 -#define RG_LCDDS_SSC_DELTA_M 0xfff - -#define CORE_PLL_GROUP11 0x40a -#define RG_LCDDS_SSC_DELTA1_S 0 -#define RG_LCDDS_SSC_DELTA1_M 0xfff - -#define CORE_GSWPLL_GRP1 0x40d -#define RG_GSWPLL_POSDIV_200M_S 12 -#define RG_GSWPLL_POSDIV_200M_M 0x3000 -#define RG_GSWPLL_EN_PRE BIT(11) -#define RG_GSWPLL_FBKDIV_200M_S 0 -#define RG_GSWPLL_FBKDIV_200M_M 0xff - -#define CORE_GSWPLL_GRP2 0x40e -#define RG_GSWPLL_POSDIV_500M_S 8 -#define RG_GSWPLL_POSDIV_500M_M 0x300 -#define RG_GSWPLL_FBKDIV_500M_S 0 -#define RG_GSWPLL_FBKDIV_500M_M 0xff - -#define CORE_TRGMII_GSW_CLK_CG 0x410 -#define REG_GSWCK_EN BIT(0) -#define REG_TRGMIICK_EN BIT(1) - -/* Extend PHY Control Register 3 */ -#define PHY_EXT_REG_14 0x14 - -/* Fields of PHY_EXT_REG_14 */ -#define PHY_EN_DOWN_SHFIT BIT(4) - -/* Extend PHY Control Register 4 */ -#define PHY_EXT_REG_17 0x17 - -/* Fields of PHY_EXT_REG_17 */ -#define PHY_LINKDOWN_POWER_SAVING_EN BIT(4) - -/* PHY RXADC Control Register 7 */ -#define PHY_DEV1E_REG_0C6 0x0c6 - -/* Fields of PHY_DEV1E_REG_0C6 */ -#define PHY_POWER_SAVING_S 8 -#define PHY_POWER_SAVING_M 0x300 -#define PHY_POWER_SAVING_TX 0x0 - /* PDMA descriptors */ struct mtk_rx_dma { unsigned int rxd1; @@ -597,4 +413,17 @@ struct mtk_tx_dma_v2 { #define PDMA_V2_RXD2_PLEN0_GET(_v) FIELD_GET(PDMA_V2_RXD2_PLEN0_M, (_v)) #define PDMA_V2_RXD2_PLEN0_SET(_v) FIELD_PREP(PDMA_V2_RXD2_PLEN0_M, (_v)) +void mtk_fe_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, u32 set); +void mtk_gmac_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, u32 set); +void mtk_ethsys_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, u32 set); + +int mtk_mii_read(struct mtk_eth_priv *priv, u8 phy, u8 reg); +int mtk_mii_write(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 data); +int mtk_mmd_read(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg); +int mtk_mmd_write(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg, + u16 val); +int mtk_mmd_ind_read(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg); +int mtk_mmd_ind_write(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg, + u16 val); + #endif /* _MTK_ETH_H_ */ diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 13e73810ad6..3132718e4f8 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -2,10 +2,6 @@ config BITBANGMII bool "Bit-banged ethernet MII management channel support" -config BITBANGMII_MULTI - bool "Enable the multi bus support" - depends on BITBANGMII - config MV88E6352_SWITCH bool "Marvell 88E6352 switch support" diff --git a/drivers/net/phy/miiphybb.c b/drivers/net/phy/miiphybb.c index b143137893f..9f5f9b12c9f 100644 --- a/drivers/net/phy/miiphybb.c +++ b/drivers/net/phy/miiphybb.c @@ -17,90 +17,6 @@ #include <miiphy.h> #include <asm/global_data.h> -#ifndef CONFIG_BITBANGMII_MULTI - -/* - * If CONFIG_BITBANGMII_MULTI is not defined we use a - * compatibility layer with the previous miiphybb implementation - * based on macros usage. - * - */ -static int bb_mii_init_wrap(struct bb_miiphy_bus *bus) -{ -#ifdef MII_INIT - MII_INIT; -#endif - return 0; -} - -static int bb_mdio_active_wrap(struct bb_miiphy_bus *bus) -{ -#ifdef MDIO_DECLARE - MDIO_DECLARE; -#endif - MDIO_ACTIVE; - return 0; -} - -static int bb_mdio_tristate_wrap(struct bb_miiphy_bus *bus) -{ -#ifdef MDIO_DECLARE - MDIO_DECLARE; -#endif - MDIO_TRISTATE; - return 0; -} - -static int bb_set_mdio_wrap(struct bb_miiphy_bus *bus, int v) -{ -#ifdef MDIO_DECLARE - MDIO_DECLARE; -#endif - MDIO(v); - return 0; -} - -static int bb_get_mdio_wrap(struct bb_miiphy_bus *bus, int *v) -{ -#ifdef MDIO_DECLARE - MDIO_DECLARE; -#endif - *v = MDIO_READ; - return 0; -} - -static int bb_set_mdc_wrap(struct bb_miiphy_bus *bus, int v) -{ -#ifdef MDC_DECLARE - MDC_DECLARE; -#endif - MDC(v); - return 0; -} - -static int bb_delay_wrap(struct bb_miiphy_bus *bus) -{ - MIIDELAY; - return 0; -} - -struct bb_miiphy_bus bb_miiphy_buses[] = { - { - .name = BB_MII_DEVNAME, - .init = bb_mii_init_wrap, - .mdio_active = bb_mdio_active_wrap, - .mdio_tristate = bb_mdio_tristate_wrap, - .set_mdio = bb_set_mdio_wrap, - .get_mdio = bb_get_mdio_wrap, - .set_mdc = bb_set_mdc_wrap, - .delay = bb_delay_wrap, - } -}; - -int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) / - sizeof(bb_miiphy_buses[0]); -#endif - int bb_miiphy_init(void) { int i; @@ -114,7 +30,6 @@ int bb_miiphy_init(void) static inline struct bb_miiphy_bus *bb_miiphy_getbus(const char *devname) { -#ifdef CONFIG_BITBANGMII_MULTI int i; /* Search the correct bus */ @@ -124,10 +39,6 @@ static inline struct bb_miiphy_bus *bb_miiphy_getbus(const char *devname) } } return NULL; -#else - /* We have just one bitbanging bus */ - return &bb_miiphy_buses[0]; -#endif } /***************************************************************************** @@ -272,9 +183,7 @@ int bb_miiphy_read(struct mii_dev *miidev, int addr, int devad, int reg) bus->set_mdc(bus, 1); bus->delay(bus); -#ifdef DEBUG - printf("miiphy_read(0x%x) @ 0x%x = 0x%04x\n", reg, addr, rdreg); -#endif + debug("%s[%s](0x%x) @ 0x%x = 0x%04x\n", __func__, miidev->name, reg, addr, rdreg); return rdreg; } diff --git a/drivers/net/phy/ti_phy_init.c b/drivers/net/phy/ti_phy_init.c index a0878193ac0..850c0cbec96 100644 --- a/drivers/net/phy/ti_phy_init.c +++ b/drivers/net/phy/ti_phy_init.c @@ -10,12 +10,58 @@ #include <phy.h> #include "ti_phy_init.h" +#define DP83822_DEVADDR 0x1f + +#define MII_DP83822_RCSR 0x17 + +/* RCSR bits */ +#define DP83822_RX_CLK_SHIFT BIT(12) +#define DP83822_TX_CLK_SHIFT BIT(11) + +/* DP83822 specific RGMII RX/TX delay configuration. */ +static int dp83822_config(struct phy_device *phydev) +{ + ofnode node = phy_get_ofnode(phydev); + u32 rgmii_delay = 0; + u32 rx_delay = 0; + u32 tx_delay = 0; + int ret; + + ret = ofnode_read_u32(node, "rx-internal-delay-ps", &rx_delay); + if (ret) { + rx_delay = phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || + phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID; + } + + ret = ofnode_read_u32(node, "tx-internal-delay-ps", &tx_delay); + if (ret) { + tx_delay = phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || + phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID; + } + + /* Bit set means Receive path internal clock shift is ENABLED */ + if (rx_delay) + rgmii_delay |= DP83822_RX_CLK_SHIFT; + + /* Bit set means Transmit path internal clock shift is DISABLED */ + if (!tx_delay) + rgmii_delay |= DP83822_TX_CLK_SHIFT; + + ret = phy_modify_mmd(phydev, DP83822_DEVADDR, MII_DP83822_RCSR, + DP83822_RX_CLK_SHIFT | DP83822_TX_CLK_SHIFT, + rgmii_delay); + if (ret) + return ret; + + return genphy_config_aneg(phydev); +} + U_BOOT_PHY_DRIVER(dp83822) = { .name = "TI DP83822", .uid = 0x2000a240, .mask = 0xfffffff0, .features = PHY_BASIC_FEATURES, - .config = &genphy_config_aneg, + .config = &dp83822_config, .startup = &genphy_startup, .shutdown = &genphy_shutdown, }; diff --git a/drivers/net/ravb.c b/drivers/net/ravb.c index 231764e60b5..7286ad19598 100644 --- a/drivers/net/ravb.c +++ b/drivers/net/ravb.c @@ -560,12 +560,12 @@ static int ravb_remove(struct udevice *dev) return 0; } -int ravb_bb_init(struct bb_miiphy_bus *bus) +static int ravb_bb_init(struct bb_miiphy_bus *bus) { return 0; } -int ravb_bb_mdio_active(struct bb_miiphy_bus *bus) +static int ravb_bb_mdio_active(struct bb_miiphy_bus *bus) { struct ravb_priv *eth = bus->priv; @@ -574,7 +574,7 @@ int ravb_bb_mdio_active(struct bb_miiphy_bus *bus) return 0; } -int ravb_bb_mdio_tristate(struct bb_miiphy_bus *bus) +static int ravb_bb_mdio_tristate(struct bb_miiphy_bus *bus) { struct ravb_priv *eth = bus->priv; @@ -583,7 +583,7 @@ int ravb_bb_mdio_tristate(struct bb_miiphy_bus *bus) return 0; } -int ravb_bb_set_mdio(struct bb_miiphy_bus *bus, int v) +static int ravb_bb_set_mdio(struct bb_miiphy_bus *bus, int v) { struct ravb_priv *eth = bus->priv; @@ -595,7 +595,7 @@ int ravb_bb_set_mdio(struct bb_miiphy_bus *bus, int v) return 0; } -int ravb_bb_get_mdio(struct bb_miiphy_bus *bus, int *v) +static int ravb_bb_get_mdio(struct bb_miiphy_bus *bus, int *v) { struct ravb_priv *eth = bus->priv; @@ -604,7 +604,7 @@ int ravb_bb_get_mdio(struct bb_miiphy_bus *bus, int *v) return 0; } -int ravb_bb_set_mdc(struct bb_miiphy_bus *bus, int v) +static int ravb_bb_set_mdc(struct bb_miiphy_bus *bus, int v) { struct ravb_priv *eth = bus->priv; @@ -616,7 +616,7 @@ int ravb_bb_set_mdc(struct bb_miiphy_bus *bus, int v) return 0; } -int ravb_bb_delay(struct bb_miiphy_bus *bus) +static int ravb_bb_delay(struct bb_miiphy_bus *bus) { udelay(10); diff --git a/drivers/nvme/Kconfig b/drivers/nvme/Kconfig index 73edb355160..d138867666b 100644 --- a/drivers/nvme/Kconfig +++ b/drivers/nvme/Kconfig @@ -4,6 +4,7 @@ config NVME bool "NVM Express device support" + select BLK help This option enables support for NVM Express devices. It supports basic functions of NVMe (read/write). diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 41901433e8c..4f876d39875 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -371,6 +371,14 @@ config PCIE_DW_MESON Say Y here if you want to enable DW PCIe controller support on Amlogic SoCs. +config PCIE_DW_QCOM + bool "Qualcomm DesignWare based PCIe controller" + depends on ARCH_SNAPDRAGON + select PCIE_DW_COMMON + help + Say Y here if you want to enable DW PCIe controller support on + Qualcomm SoCs. + config PCIE_ROCKCHIP bool "Enable Rockchip PCIe driver" depends on ARCH_ROCKCHIP diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index bf361cd0fba..ba53f594963 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -47,6 +47,7 @@ obj-$(CONFIG_PCIE_MEDIATEK_GEN3) += pcie_mediatek_gen3.o obj-$(CONFIG_PCIE_ROCKCHIP) += pcie_rockchip.o obj-$(CONFIG_PCIE_DW_ROCKCHIP) += pcie_dw_rockchip.o obj-$(CONFIG_PCIE_DW_MESON) += pcie_dw_meson.o +obj-$(CONFIG_PCIE_DW_QCOM) += pcie_dw_qcom.o obj-$(CONFIG_PCI_BRCMSTB) += pcie_brcmstb.o obj-$(CONFIG_PCI_OCTEONTX) += pci_octeontx.o obj-$(CONFIG_PCIE_OCTEON) += pcie_octeon.o diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c index 2753df275ca..3697ad00be2 100644 --- a/drivers/pci/pci_rom.c +++ b/drivers/pci/pci_rom.c @@ -347,6 +347,7 @@ int vesa_setup_video_priv(struct vesa_mode_info *vesa, u64 fb, case 32: case 24: uc_priv->bpix = VIDEO_BPP32; + uc_priv->format = VIDEO_X8B8G8R8; break; case 16: uc_priv->bpix = VIDEO_BPP16; @@ -392,6 +393,7 @@ int vesa_setup_video(struct udevice *dev, int (*int15_handler)(void)) uc_priv->ysize = ho->ysize; uc_priv->line_length = ho->line_length; uc_priv->bpix = ho->bpix; + uc_priv->format = ho->format; } else { bootstage_start(BOOTSTAGE_ID_ACCUM_LCD, "vesa display"); ret = dm_pci_run_vga_bios(dev, int15_handler, @@ -438,6 +440,7 @@ int vesa_setup_video(struct udevice *dev, int (*int15_handler)(void)) ho->ysize = uc_priv->ysize; ho->line_length = uc_priv->line_length; ho->bpix = uc_priv->bpix; + ho->format = uc_priv->format; } return 0; diff --git a/drivers/pci/pcie_dw_common.c b/drivers/pci/pcie_dw_common.c index 0673e516c6f..78961271a8e 100644 --- a/drivers/pci/pcie_dw_common.c +++ b/drivers/pci/pcie_dw_common.c @@ -267,6 +267,48 @@ int pcie_dw_write_config(struct udevice *bus, pci_dev_t bdf, pcie->io.bus_start, pcie->io.size); } +/* + * These interfaces resemble the pci_find_*capability() interfaces, but these + * are for configuring host controllers, which are bridges *to* PCI devices but + * are not PCI devices themselves. + */ +static u8 pcie_dw_find_next_cap(struct pcie_dw *pci, u8 cap_ptr, u8 cap) +{ + u8 cap_id, next_cap_ptr; + u32 val; + u16 reg; + + if (!cap_ptr) + return 0; + + val = readl(pci->dbi_base + (cap_ptr & ~0x3)); + reg = pci_conv_32_to_size(val, cap_ptr, 2); + cap_id = (reg & 0x00ff); + + if (cap_id > PCI_CAP_ID_MAX) + return 0; + + if (cap_id == cap) + return cap_ptr; + + next_cap_ptr = (reg & 0xff00) >> 8; + return pcie_dw_find_next_cap(pci, next_cap_ptr, cap); +} + +u8 pcie_dw_find_capability(struct pcie_dw *pci, u8 cap) +{ + u8 next_cap_ptr; + u32 val; + u16 reg; + + val = readl(pci->dbi_base + (PCI_CAPABILITY_LIST & ~0x3)); + reg = pci_conv_32_to_size(val, PCI_CAPABILITY_LIST, 2); + + next_cap_ptr = (reg & 0x00ff); + + return pcie_dw_find_next_cap(pci, next_cap_ptr, cap); +} + /** * pcie_dw_setup_host() - Setup the PCIe controller for RC opertaion * diff --git a/drivers/pci/pcie_dw_common.h b/drivers/pci/pcie_dw_common.h index e0f7796f2a8..8cb99a12ea1 100644 --- a/drivers/pci/pcie_dw_common.h +++ b/drivers/pci/pcie_dw_common.h @@ -139,6 +139,8 @@ int pcie_dw_read_config(const struct udevice *bus, pci_dev_t bdf, uint offset, u int pcie_dw_write_config(struct udevice *bus, pci_dev_t bdf, uint offset, ulong value, enum pci_size_t size); +u8 pcie_dw_find_capability(struct pcie_dw *pci, u8 cap); + static inline void dw_pcie_dbi_write_enable(struct pcie_dw *pci, bool en) { u32 val; diff --git a/drivers/pci/pcie_dw_qcom.c b/drivers/pci/pcie_dw_qcom.c new file mode 100644 index 00000000000..39b4cd4efe2 --- /dev/null +++ b/drivers/pci/pcie_dw_qcom.c @@ -0,0 +1,571 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include <clk.h> +#include <dm.h> +#include <generic-phy.h> +#include <pci.h> +#include <u-boot/crc.h> +#include <power-domain.h> +#include <reset.h> +#include <syscon.h> +#include <malloc.h> +#include <power/regulator.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm-generic/gpio.h> +#include <dm/device_compat.h> +#include <linux/iopoll.h> +#include <linux/delay.h> +#include <linux/log2.h> +#include <linux/bitfield.h> + +#include "pcie_dw_common.h" + +DECLARE_GLOBAL_DATA_PTR; + +struct qcom_pcie; + +struct qcom_pcie_ops { + int (*config_sid)(struct qcom_pcie *priv); +}; + +#define NUM_SUPPLIES 2 + +struct qcom_pcie { + /* Must be first member of the struct */ + struct pcie_dw dw; + void *parf; + struct phy phy; + struct reset_ctl_bulk rsts; + struct clk_bulk clks; + struct gpio_desc rst_gpio; + struct qcom_pcie_ops *ops; + struct udevice *vregs[NUM_SUPPLIES]; +}; + +/* PARF registers */ +#define PARF_SYS_CTRL 0x00 +#define PARF_PM_CTRL 0x20 +#define PARF_PCS_DEEMPH 0x34 +#define PARF_PCS_SWING 0x38 +#define PARF_PHY_CTRL 0x40 +#define PARF_PHY_REFCLK 0x4c +#define PARF_CONFIG_BITS 0x50 +#define PARF_DBI_BASE_ADDR 0x168 +#define PARF_MHI_CLOCK_RESET_CTRL 0x174 +#define PARF_AXI_MSTR_WR_ADDR_HALT 0x178 +#define PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1a8 +#define PARF_Q2A_FLUSH 0x1ac +#define PARF_LTSSM 0x1b0 +#define PARF_SID_OFFSET 0x234 +#define PARF_BDF_TRANSLATE_CFG 0x24c +#define PARF_SLV_ADDR_SPACE_SIZE 0x358 +#define PARF_DEVICE_TYPE 0x1000 +#define PARF_BDF_TO_SID_TABLE_N 0x2000 + +/* ELBI registers */ +#define ELBI_SYS_CTRL 0x04 + +/* DBI registers */ +#define AXI_MSTR_RESP_COMP_CTRL0 0x818 +#define AXI_MSTR_RESP_COMP_CTRL1 0x81c +#define MISC_CONTROL_1_REG 0x8bc + +/* MHI registers */ +#define PARF_DEBUG_CNT_PM_LINKST_IN_L2 0xc04 +#define PARF_DEBUG_CNT_PM_LINKST_IN_L1 0xc0c +#define PARF_DEBUG_CNT_PM_LINKST_IN_L0S 0xc10 +#define PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1 0xc84 +#define PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2 0xc88 + +/* PARF_SYS_CTRL register fields */ +#define MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN BIT(29) +#define MST_WAKEUP_EN BIT(13) +#define SLV_WAKEUP_EN BIT(12) +#define MSTR_ACLK_CGC_DIS BIT(10) +#define SLV_ACLK_CGC_DIS BIT(9) +#define CORE_CLK_CGC_DIS BIT(6) +#define AUX_PWR_DET BIT(4) +#define L23_CLK_RMV_DIS BIT(2) +#define L1_CLK_RMV_DIS BIT(1) + +/* PARF_PM_CTRL register fields */ +#define REQ_NOT_ENTR_L1 BIT(5) + +/* PARF_PCS_DEEMPH register fields */ +#define PCS_DEEMPH_TX_DEEMPH_GEN1(x) FIELD_PREP(GENMASK(21, 16), x) +#define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) FIELD_PREP(GENMASK(13, 8), x) +#define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x) FIELD_PREP(GENMASK(5, 0), x) + +/* PARF_PCS_SWING register fields */ +#define PCS_SWING_TX_SWING_FULL(x) FIELD_PREP(GENMASK(14, 8), x) +#define PCS_SWING_TX_SWING_LOW(x) FIELD_PREP(GENMASK(6, 0), x) + +/* PARF_PHY_CTRL register fields */ +#define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK GENMASK(20, 16) +#define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) FIELD_PREP(PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK, x) +#define PHY_TEST_PWR_DOWN BIT(0) + +/* PARF_PHY_REFCLK register fields */ +#define PHY_REFCLK_SSP_EN BIT(16) +#define PHY_REFCLK_USE_PAD BIT(12) + +/* PARF_CONFIG_BITS register fields */ +#define PHY_RX0_EQ(x) FIELD_PREP(GENMASK(26, 24), x) + +/* PARF_SLV_ADDR_SPACE_SIZE register value */ +#define SLV_ADDR_SPACE_SZ 0x10000000 + +/* PARF_MHI_CLOCK_RESET_CTRL register fields */ +#define AHB_CLK_EN BIT(0) +#define MSTR_AXI_CLK_EN BIT(1) +#define BYPASS BIT(4) + +/* PARF_AXI_MSTR_WR_ADDR_HALT register fields */ +#define EN BIT(31) + +/* PARF_LTSSM register fields */ +#define LTSSM_EN BIT(8) + +/* PARF_DEVICE_TYPE register fields */ +#define DEVICE_TYPE_RC 0x4 + +/* ELBI_SYS_CTRL register fields */ +#define ELBI_SYS_CTRL_LT_ENABLE BIT(0) + +/* AXI_MSTR_RESP_COMP_CTRL0 register fields */ +#define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K 0x4 +#define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_4K 0x5 + +/* AXI_MSTR_RESP_COMP_CTRL1 register fields */ +#define CFG_BRIDGE_SB_INIT BIT(0) + +/* MISC_CONTROL_1_REG register fields */ +#define DBI_RO_WR_EN 1 + +/* PCI_EXP_SLTCAP register fields */ +#define PCIE_CAP_SLOT_POWER_LIMIT_VAL FIELD_PREP(PCI_EXP_SLTCAP_SPLV, 250) +#define PCIE_CAP_SLOT_POWER_LIMIT_SCALE FIELD_PREP(PCI_EXP_SLTCAP_SPLS, 1) +#define PCIE_CAP_SLOT_VAL (PCI_EXP_SLTCAP_ABP | \ + PCI_EXP_SLTCAP_PCP | \ + PCI_EXP_SLTCAP_MRLSP | \ + PCI_EXP_SLTCAP_AIP | \ + PCI_EXP_SLTCAP_PIP | \ + PCI_EXP_SLTCAP_HPS | \ + PCI_EXP_SLTCAP_HPC | \ + PCI_EXP_SLTCAP_EIP | \ + PCIE_CAP_SLOT_POWER_LIMIT_VAL | \ + PCIE_CAP_SLOT_POWER_LIMIT_SCALE) + +#define PERST_DELAY_US 1000 + +#define LINK_WAIT_MAX_RETRIES 10 +#define LINK_WAIT_USLEEP 100000 + +#define QCOM_PCIE_CRC8_POLYNOMIAL (BIT(2) | BIT(1) | BIT(0)) + +#define CRC8_TABLE_SIZE 256 + +static bool qcom_pcie_wait_link_up(struct qcom_pcie *priv) +{ + u8 offset = pcie_dw_find_capability(&priv->dw, PCI_CAP_ID_EXP); + unsigned int cnt = 0; + u16 val; + + do { + val = readw(priv->dw.dbi_base + offset + PCI_EXP_LNKSTA); + + if ((val & PCI_EXP_LNKSTA_DLLLA)) + return true; + cnt++; + + udelay(LINK_WAIT_USLEEP); + } while (cnt < LINK_WAIT_MAX_RETRIES); + + return false; +} + +static void qcom_pcie_clear_aspm_l0s(struct qcom_pcie *priv) +{ + u8 offset = pcie_dw_find_capability(&priv->dw, PCI_CAP_ID_EXP); + u32 val; + + dw_pcie_dbi_write_enable(&priv->dw, true); + + val = readl(priv->dw.dbi_base + offset + PCI_EXP_LNKCAP); + val &= ~PCI_EXP_LNKCAP_ASPM_L0S; + writel(val, priv->dw.dbi_base + offset + PCI_EXP_LNKCAP); + + dw_pcie_dbi_write_enable(&priv->dw, false); +} + +static void qcom_pcie_clear_hpc(struct qcom_pcie *priv) +{ + u8 offset = pcie_dw_find_capability(&priv->dw, PCI_CAP_ID_EXP); + u32 val; + + dw_pcie_dbi_write_enable(&priv->dw, true); + + val = readl(priv->dw.dbi_base + offset + PCI_EXP_SLTCAP); + val &= ~PCI_EXP_SLTCAP_HPC; + writel(val, priv->dw.dbi_base + offset + PCI_EXP_SLTCAP); + + dw_pcie_dbi_write_enable(&priv->dw, false); +} + +static void qcom_pcie_set_lanes(struct qcom_pcie *priv, unsigned int lanes) +{ + u8 offset = pcie_dw_find_capability(&priv->dw, PCI_CAP_ID_EXP); + u32 val; + + val = readl(priv->dw.dbi_base + offset + PCI_EXP_LNKCAP); + val &= ~PCI_EXP_LNKCAP_MLW; + val |= FIELD_PREP(PCI_EXP_LNKCAP_MLW, lanes); + writel(val, priv->dw.dbi_base + offset + PCI_EXP_LNKCAP); +} + +static int qcom_pcie_config_sid_1_9_0(struct qcom_pcie *priv) +{ + /* iommu map structure */ + struct { + u32 bdf; + u32 phandle; + u32 smmu_sid; + u32 smmu_sid_len; + } *map; + void *bdf_to_sid_base = priv->parf + PARF_BDF_TO_SID_TABLE_N; + int i, nr_map, size = 0; + u32 smmu_sid_base; + + dev_read_prop(priv->dw.dev, "iommu-map", &size); + if (!size) + return 0; + + map = malloc(size); + if (!map) + return -ENOMEM; + + dev_read_u32_array(priv->dw.dev, "iommu-map", (u32 *)map, size / sizeof(u32)); + + nr_map = size / (sizeof(*map)); + + /* Registers need to be zero out first */ + memset_io(bdf_to_sid_base, 0, CRC8_TABLE_SIZE * sizeof(u32)); + + /* Extract the SMMU SID base from the first entry of iommu-map */ + smmu_sid_base = map[0].smmu_sid; + + /* Look for an available entry to hold the mapping */ + for (i = 0; i < nr_map; i++) { + __be16 bdf_be = cpu_to_be16(map[i].bdf); + u32 val; + u8 hash; + + hash = crc8(QCOM_PCIE_CRC8_POLYNOMIAL, (u8 *)&bdf_be, sizeof(bdf_be)); + + val = readl(bdf_to_sid_base + hash * sizeof(u32)); + + /* If the register is already populated, look for next available entry */ + while (val) { + u8 current_hash = hash++; + u8 next_mask = 0xff; + + /* If NEXT field is NULL then update it with next hash */ + if (!(val & next_mask)) { + val |= (u32)hash; + writel(val, bdf_to_sid_base + current_hash * sizeof(u32)); + } + + val = readl(bdf_to_sid_base + hash * sizeof(u32)); + } + + /* BDF [31:16] | SID [15:8] | NEXT [7:0] */ + val = map[i].bdf << 16 | (map[i].smmu_sid - smmu_sid_base) << 8 | 0; + writel(val, bdf_to_sid_base + hash * sizeof(u32)); + } + + free(map); + + return 0; +} + +static void qcom_pcie_configure(struct qcom_pcie *priv) +{ + u32 val; + + dw_pcie_dbi_write_enable(&priv->dw, true); + + val = readl(priv->dw.dbi_base + PCIE_PORT_LINK_CONTROL); + val &= ~PORT_LINK_FAST_LINK_MODE; + val |= PORT_LINK_DLL_LINK_EN; + val &= ~PORT_LINK_MODE_MASK; + val |= PORT_LINK_MODE_2_LANES; + writel(val, priv->dw.dbi_base + PCIE_PORT_LINK_CONTROL); + + val = readl(priv->dw.dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL); + val &= ~PORT_LOGIC_LINK_WIDTH_MASK; + val |= PORT_LOGIC_LINK_WIDTH_2_LANES; + writel(val, priv->dw.dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL); + + qcom_pcie_set_lanes(priv, 2); + + dw_pcie_dbi_write_enable(&priv->dw, false); +} + +static int qcom_pcie_init_port(struct udevice *dev) +{ + struct qcom_pcie *priv = dev_get_priv(dev); + int vreg, ret; + u32 val; + + dm_gpio_set_value(&priv->rst_gpio, 1); + udelay(PERST_DELAY_US); + + ret = generic_phy_init(&priv->phy); + if (ret) { + dev_err(dev, "failed to init phy (%d)\n", ret); + return ret; + } + + udelay(PERST_DELAY_US); + + for (vreg = 0; vreg < NUM_SUPPLIES; ++vreg) { + ret = regulator_set_enable(priv->vregs[vreg], true); + if (ret && ret != -ENOSYS) + dev_warn(dev, "failed to enable regulator %d (%d)\n", vreg, ret); + } + + ret = clk_enable_bulk(&priv->clks); + if (ret) { + dev_err(dev, "failed to enable clocks (%d)\n", ret); + goto err_power_off_phy; + } + + ret = reset_assert_bulk(&priv->rsts); + if (ret) { + dev_err(dev, "failed to assert resets (%d)\n", ret); + goto err_disable_clks; + } + + udelay(PERST_DELAY_US); + + ret = reset_deassert_bulk(&priv->rsts); + if (ret) { + dev_err(dev, "failed to deassert resets (%d)\n", ret); + goto err_power_off_phy; + } + + udelay(PERST_DELAY_US); + + /* configure PCIe to RC mode */ + writel(DEVICE_TYPE_RC, priv->parf + PARF_DEVICE_TYPE); + + /* enable PCIe clocks and resets */ + val = readl(priv->parf + PARF_PHY_CTRL); + val &= ~PHY_TEST_PWR_DOWN; + writel(val, priv->parf + PARF_PHY_CTRL); + + /* change DBI base address */ + writel(0, priv->parf + PARF_DBI_BASE_ADDR); + + /* MAC PHY_POWERDOWN MUX DISABLE */ + val = readl(priv->parf + PARF_SYS_CTRL); + val &= ~MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN; + writel(val, priv->parf + PARF_SYS_CTRL); + + val = readl(priv->parf + PARF_MHI_CLOCK_RESET_CTRL); + val |= BYPASS; + writel(val, priv->parf + PARF_MHI_CLOCK_RESET_CTRL); + + /* Enable L1 and L1SS */ + val = readl(priv->parf + PARF_PM_CTRL); + val &= ~REQ_NOT_ENTR_L1; + writel(val, priv->parf + PARF_PM_CTRL); + + val = readl(priv->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); + val |= EN; + writel(val, priv->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); + + ret = generic_phy_power_on(&priv->phy); + if (ret) { + dev_err(dev, "failed to power on phy (%d)\n", ret); + goto err_exit_phy; + } + + qcom_pcie_clear_aspm_l0s(priv); + qcom_pcie_clear_hpc(priv); + + mdelay(100); + dm_gpio_set_value(&priv->rst_gpio, 0); + udelay(PERST_DELAY_US); + + if (priv->ops && priv->ops->config_sid) { + ret = priv->ops->config_sid(priv); + if (ret) + goto err_deassert_bulk; + } + + qcom_pcie_configure(priv); + + pcie_dw_setup_host(&priv->dw); + + /* enable link training */ + val = readl(priv->parf + PARF_LTSSM); + val |= LTSSM_EN; + writel(val, priv->parf + PARF_LTSSM); + + return 0; +err_deassert_bulk: + reset_assert_bulk(&priv->rsts); +err_disable_clks: + clk_disable_bulk(&priv->clks); +err_power_off_phy: + generic_phy_power_off(&priv->phy); +err_exit_phy: + generic_phy_exit(&priv->phy); + + return ret; +} + +static const char *qcom_pcie_vregs[NUM_SUPPLIES] = { + "vdda-supply", + "vddpe-3v3-supply", +}; + +static int qcom_pcie_parse_dt(struct udevice *dev) +{ + struct qcom_pcie *priv = dev_get_priv(dev); + int vreg, ret; + + priv->dw.dbi_base = dev_read_addr_name_ptr(dev, "dbi"); + if (!priv->dw.dbi_base) + return -EINVAL; + + dev_dbg(dev, "DBI address is 0x%p\n", priv->dw.dbi_base); + + priv->dw.atu_base = dev_read_addr_name_ptr(dev, "atu"); + if (!priv->dw.atu_base) + return -EINVAL; + + dev_dbg(dev, "ATU address is 0x%p\n", priv->dw.atu_base); + + priv->parf = dev_read_addr_name_ptr(dev, "parf"); + if (!priv->parf) + return -EINVAL; + + dev_dbg(dev, "PARF address is 0x%p\n", priv->parf); + + ret = gpio_request_by_name(dev, "perst-gpios", 0, + &priv->rst_gpio, GPIOD_IS_OUT); + if (ret) { + dev_err(dev, "failed to find reset-gpios property\n"); + return ret; + } + + ret = reset_get_bulk(dev, &priv->rsts); + if (ret) { + dev_err(dev, "failed to get resets (%d)\n", ret); + return ret; + } + + ret = clk_get_bulk(dev, &priv->clks); + if (ret) { + dev_err(dev, "failed to get clocks (%d)\n", ret); + return ret; + } + + ret = generic_phy_get_by_index(dev, 0, &priv->phy); + if (ret) { + dev_err(dev, "failed to get pcie phy (%d)\n", ret); + return ret; + } + + for (vreg = 0; vreg < NUM_SUPPLIES; ++vreg) { + ret = device_get_supply_regulator(dev, qcom_pcie_vregs[vreg], &priv->vregs[vreg]); + if (ret) + dev_warn(dev, "failed to get regulator %d (%d)\n", vreg, ret); + } + + return 0; +} + +/** + * qcom_pcie_probe() - Probe the PCIe bus for active link + * + * @dev: A pointer to the device being operated on + * + * Probe for an active link on the PCIe bus and configure the controller + * to enable this port. + * + * Return: 0 on success, else -ENODEV + */ +static int qcom_pcie_probe(struct udevice *dev) +{ + struct qcom_pcie *priv = dev_get_priv(dev); + struct udevice *ctlr = pci_get_controller(dev); + struct pci_controller *hose = dev_get_uclass_priv(ctlr); + int ret = 0; + + priv->dw.first_busno = dev_seq(dev); + priv->dw.dev = dev; + + ret = qcom_pcie_parse_dt(dev); + if (ret) + return ret; + + ret = qcom_pcie_init_port(dev); + if (ret) { + dm_gpio_free(dev, &priv->rst_gpio); + return ret; + } + + if (qcom_pcie_wait_link_up(priv)) + printf("PCIE-%d: Link up (Gen%d-x%d, Bus%d)\n", + dev_seq(dev), pcie_dw_get_link_speed(&priv->dw), + pcie_dw_get_link_width(&priv->dw), + hose->first_busno); + else + printf("PCIE-%d: Link up timeout\n", dev_seq(dev)); + + return pcie_dw_prog_outbound_atu_unroll(&priv->dw, + PCIE_ATU_REGION_INDEX0, + PCIE_ATU_TYPE_MEM, + priv->dw.mem.phys_start, + priv->dw.mem.bus_start, + priv->dw.mem.size); +} + +static const struct dm_pci_ops qcom_pcie_ops = { + .read_config = pcie_dw_read_config, + .write_config = pcie_dw_write_config, +}; + +static const struct qcom_pcie_ops ops_1_9_0 = { + .config_sid = qcom_pcie_config_sid_1_9_0, +}; + +static const struct udevice_id qcom_pcie_ids[] = { + { .compatible = "qcom,pcie-sa8540p", .data = (ulong)&ops_1_9_0 }, + { .compatible = "qcom,pcie-sc7280", .data = (ulong)&ops_1_9_0 }, + { .compatible = "qcom,pcie-sc8180x", .data = (ulong)&ops_1_9_0 }, + { .compatible = "qcom,pcie-sc8280xp", .data = (ulong)&ops_1_9_0 }, + { .compatible = "qcom,pcie-sdm845" }, + { .compatible = "qcom,pcie-sdx55", .data = (ulong)&ops_1_9_0 }, + { .compatible = "qcom,pcie-sm8150", .data = (ulong)&ops_1_9_0 }, + { .compatible = "qcom,pcie-sm8250", .data = (ulong)&ops_1_9_0 }, + { .compatible = "qcom,pcie-sm8350", .data = (ulong)&ops_1_9_0 }, + { .compatible = "qcom,pcie-sm8450-pcie0", .data = (ulong)&ops_1_9_0 }, + { .compatible = "qcom,pcie-sm8450-pcie1", .data = (ulong)&ops_1_9_0 }, + { .compatible = "qcom,pcie-sm8550", .data = (ulong)&ops_1_9_0 }, + { .compatible = "qcom,pcie-x1e80100", .data = (ulong)&ops_1_9_0 }, + { } +}; + +U_BOOT_DRIVER(qcom_dw_pcie) = { + .name = "pcie_dw_qcom", + .id = UCLASS_PCI, + .of_match = qcom_pcie_ids, + .ops = &qcom_pcie_ops, + .probe = qcom_pcie_probe, + .priv_auto = sizeof(struct qcom_pcie), +}; diff --git a/drivers/pci/pcie_mediatek_gen3.c b/drivers/pci/pcie_mediatek_gen3.c index 0149edae0bf..1818d4c1e30 100644 --- a/drivers/pci/pcie_mediatek_gen3.c +++ b/drivers/pci/pcie_mediatek_gen3.c @@ -83,6 +83,28 @@ struct mtk_pcie { struct phy phy; }; +static pci_dev_t convert_bdf(const struct udevice *controller, pci_dev_t bdf) +{ + int bdfs[3]; + + bdfs[0] = PCI_BUS(bdf); + bdfs[1] = PCI_DEV(bdf); + bdfs[2] = PCI_FUNC(bdf); + + /* + * One MediaTek PCIe Gen3 controller has only one port, where PCI bus 0 on + * this port represents the controller itself and bus 1 represents the + * external PCIe device. If multiple PCIe controllers are probed in U-Boot, + * U-Boot will use bus numbers greater than 2 as input parameters. Therefore, + * we should convert the BDF bus number to either 0 or 1 by subtracting the + * offset by controller->seq_ + */ + + bdfs[0] = bdfs[0] - controller->seq_; + + return PCI_BDF(bdfs[0], bdfs[1], bdfs[2]); +} + static void mtk_pcie_config_tlp_header(const struct udevice *bus, pci_dev_t devfn, int where, int size) @@ -91,6 +113,8 @@ static void mtk_pcie_config_tlp_header(const struct udevice *bus, int bytes; u32 val; + devfn = convert_bdf(bus, devfn); + size = 1 << size; bytes = (GENMASK(size - 1, 0) & 0xf) << (where & 0x3); diff --git a/drivers/phy/qcom/Kconfig b/drivers/phy/qcom/Kconfig index 5c77203d606..61e5e2fca41 100644 --- a/drivers/phy/qcom/Kconfig +++ b/drivers/phy/qcom/Kconfig @@ -12,6 +12,12 @@ config PHY_QCOM_IPQ4019_USB help Support for the USB PHY-s on Qualcomm IPQ40xx SoC-s. +config PHY_QCOM_QMP_PCIE + tristate "Qualcomm QMP PCIe PHY driver" + depends on PHY && ARCH_SNAPDRAGON + help + Enable this to support the PCIe QMP PHY on various Qualcomm chipsets. + config PHY_QCOM_QMP_UFS tristate "Qualcomm QMP UFS PHY driver" depends on PHY && ARCH_SNAPDRAGON diff --git a/drivers/phy/qcom/Makefile b/drivers/phy/qcom/Makefile index dc3ed492696..1c4e7d8d391 100644 --- a/drivers/phy/qcom/Makefile +++ b/drivers/phy/qcom/Makefile @@ -1,5 +1,6 @@ obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o obj-$(CONFIG_MSM8916_USB_PHY) += msm8916-usbh-phy.o +obj-$(CONFIG_PHY_QCOM_QMP_PCIE) += phy-qcom-qmp-pcie.o obj-$(CONFIG_PHY_QCOM_QMP_UFS) += phy-qcom-qmp-ufs.o obj-$(CONFIG_PHY_QCOM_QUSB2) += phy-qcom-qusb2.o obj-$(CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2) += phy-qcom-snps-femto-v2.o diff --git a/drivers/phy/qcom/phy-qcom-qmp-pcie-qhp.h b/drivers/phy/qcom/phy-qcom-qmp-pcie-qhp.h new file mode 100644 index 00000000000..e4a4d2cd85e --- /dev/null +++ b/drivers/phy/qcom/phy-qcom-qmp-pcie-qhp.h @@ -0,0 +1,123 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_PCIE_QHP_H_ +#define QCOM_PHY_QMP_PCIE_QHP_H_ + +/* PCIE GEN3 COM registers */ +#define PCIE_GEN3_QHP_COM_SSC_EN_CENTER 0x14 +#define PCIE_GEN3_QHP_COM_SSC_PER1 0x20 +#define PCIE_GEN3_QHP_COM_SSC_PER2 0x24 +#define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1 0x28 +#define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2 0x2c +#define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1 0x34 +#define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1 0x38 +#define PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN 0x54 +#define PCIE_GEN3_QHP_COM_CLK_ENABLE1 0x58 +#define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0 0x6c +#define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0 0x70 +#define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1 0x78 +#define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1 0x7c +#define PCIE_GEN3_QHP_COM_BGV_TRIM 0x98 +#define PCIE_GEN3_QHP_COM_CP_CTRL_MODE0 0xb4 +#define PCIE_GEN3_QHP_COM_CP_CTRL_MODE1 0xb8 +#define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0 0xc0 +#define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1 0xc4 +#define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0 0xcc +#define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1 0xd0 +#define PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL 0xdc +#define PCIE_GEN3_QHP_COM_RESTRIM_CTRL2 0xf0 +#define PCIE_GEN3_QHP_COM_LOCK_CMP_EN 0xf8 +#define PCIE_GEN3_QHP_COM_DEC_START_MODE0 0x100 +#define PCIE_GEN3_QHP_COM_DEC_START_MODE1 0x108 +#define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0 0x11c +#define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0 0x120 +#define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0 0x124 +#define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1 0x128 +#define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1 0x12c +#define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1 0x130 +#define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0 0x150 +#define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1 0x158 +#define PCIE_GEN3_QHP_COM_VCO_TUNE_MAP 0x178 +#define PCIE_GEN3_QHP_COM_BG_CTRL 0x1c8 +#define PCIE_GEN3_QHP_COM_CLK_SELECT 0x1cc +#define PCIE_GEN3_QHP_COM_HSCLK_SEL1 0x1d0 +#define PCIE_GEN3_QHP_COM_CORECLK_DIV 0x1e0 +#define PCIE_GEN3_QHP_COM_CORE_CLK_EN 0x1e8 +#define PCIE_GEN3_QHP_COM_CMN_CONFIG 0x1f0 +#define PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL 0x1fc +#define PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1 0x21c +#define PCIE_GEN3_QHP_COM_CMN_MODE 0x224 +#define PCIE_GEN3_QHP_COM_VREGCLK_DIV1 0x228 +#define PCIE_GEN3_QHP_COM_VREGCLK_DIV2 0x22c + +/* PCIE GEN3 QHP Lane registers */ +#define PCIE_GEN3_QHP_L0_DRVR_CTRL0 0xc +#define PCIE_GEN3_QHP_L0_DRVR_CTRL1 0x10 +#define PCIE_GEN3_QHP_L0_DRVR_CTRL2 0x14 +#define PCIE_GEN3_QHP_L0_DRVR_TAP_EN 0x18 +#define PCIE_GEN3_QHP_L0_TX_BAND_MODE 0x60 +#define PCIE_GEN3_QHP_L0_LANE_MODE 0x64 +#define PCIE_GEN3_QHP_L0_PARALLEL_RATE 0x7c +#define PCIE_GEN3_QHP_L0_CML_CTRL_MODE0 0xc0 +#define PCIE_GEN3_QHP_L0_CML_CTRL_MODE1 0xc4 +#define PCIE_GEN3_QHP_L0_CML_CTRL_MODE2 0xc8 +#define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1 0xd0 +#define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2 0xd4 +#define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0 0xd8 +#define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1 0xdc +#define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2 0xe0 +#define PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE 0xfc +#define PCIE_GEN3_QHP_L0_CGA_THRESH_DFE 0x100 +#define PCIE_GEN3_QHP_L0_RXENGINE_EN0 0x108 +#define PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME 0x114 +#define PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME 0x118 +#define PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME 0x11c +#define PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME 0x120 +#define PCIE_GEN3_QHP_L0_VGA_GAIN 0x124 +#define PCIE_GEN3_QHP_L0_DFE_GAIN 0x128 +#define PCIE_GEN3_QHP_L0_EQ_GAIN 0x130 +#define PCIE_GEN3_QHP_L0_OFFSET_GAIN 0x134 +#define PCIE_GEN3_QHP_L0_PRE_GAIN 0x138 +#define PCIE_GEN3_QHP_L0_VGA_INITVAL 0x13c +#define PCIE_GEN3_QHP_L0_EQ_INTVAL 0x154 +#define PCIE_GEN3_QHP_L0_EDAC_INITVAL 0x160 +#define PCIE_GEN3_QHP_L0_RXEQ_INITB0 0x168 +#define PCIE_GEN3_QHP_L0_RXEQ_INITB1 0x16c +#define PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1 0x178 +#define PCIE_GEN3_QHP_L0_RXEQ_CTRL 0x180 +#define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0 0x184 +#define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1 0x188 +#define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2 0x18c +#define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0 0x190 +#define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1 0x194 +#define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2 0x198 +#define PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG 0x19c +#define PCIE_GEN3_QHP_L0_RX_BAND 0x1a4 +#define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0 0x1c0 +#define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1 0x1c4 +#define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2 0x1c8 +#define PCIE_GEN3_QHP_L0_SIGDET_ENABLES 0x230 +#define PCIE_GEN3_QHP_L0_SIGDET_CNTRL 0x234 +#define PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL 0x238 +#define PCIE_GEN3_QHP_L0_DCC_GAIN 0x2a4 +#define PCIE_GEN3_QHP_L0_RSM_START 0x2a8 +#define PCIE_GEN3_QHP_L0_RX_EN_SIGNAL 0x2ac +#define PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL 0x2b0 +#define PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0 0x2b8 +#define PCIE_GEN3_QHP_L0_TS0_TIMER 0x2c0 +#define PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE 0x2c4 +#define PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET 0x2cc + +/* PCIE GEN3 PCS registers */ +#define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB 0x2c +#define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB 0x40 +#define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB 0x54 +#define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB 0x68 +#define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG 0x15c +#define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5 0x16c +#define PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG 0x174 + +#endif diff --git a/drivers/phy/qcom/phy-qcom-qmp-pcie.c b/drivers/phy/qcom/phy-qcom-qmp-pcie.c new file mode 100644 index 00000000000..2f6ff259b35 --- /dev/null +++ b/drivers/phy/qcom/phy-qcom-qmp-pcie.c @@ -0,0 +1,1131 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023 Bhupesh Sharma <bhupesh.sharma@linaro.org> + * + * Based on Linux driver + */ + +#include <clk.h> +#include <clk-uclass.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <dm/devres.h> +#include <generic-phy.h> +#include <malloc.h> +#include <reset.h> +#include <power/regulator.h> + +#include <asm/io.h> +#include <linux/bitops.h> +#include <linux/clk-provider.h> +#include <linux/delay.h> +#include <linux/iopoll.h> +#include <linux/ioport.h> + +#include "phy-qcom-qmp.h" +#include "phy-qcom-qmp-pcs-misc-v3.h" +#include "phy-qcom-qmp-pcs-v5.h" +#include "phy-qcom-qmp-pcs-v6.h" +#include "phy-qcom-qmp-pcs-v6_20.h" +#include "phy-qcom-qmp-pcs-pcie-v6.h" +#include "phy-qcom-qmp-pcs-pcie-v6_20.h" +#include "phy-qcom-qmp-pcie-qhp.h" +#include "phy-qcom-qmp-qserdes-com-v6.h" +#include "phy-qcom-qmp-qserdes-txrx-v6.h" +#include "phy-qcom-qmp-qserdes-txrx-v6_20.h" +#include "phy-qcom-qmp-qserdes-ln-shrd-v6.h" + +/* QPHY_SW_RESET bit */ +#define SW_RESET BIT(0) +/* QPHY_POWER_DOWN_CONTROL */ +#define SW_PWRDN BIT(0) +#define REFCLK_DRV_DSBL BIT(1) +/* QPHY_START_CONTROL bits */ +#define SERDES_START BIT(0) +#define PCS_START BIT(1) +/* QPHY_PCS_READY_STATUS bit */ +#define PCS_READY BIT(0) + +/* QPHY_PCS_STATUS bit */ +#define PHYSTATUS BIT(6) +#define PHYSTATUS_4_20 BIT(7) + +#define PHY_INIT_COMPLETE_TIMEOUT (200 * 10000) + +#define NUM_SUPPLIES 3 + +struct qmp_pcie_init_tbl { + unsigned int offset; + unsigned int val; + /* + * mask of lanes for which this register is written + * for cases when second lane needs different values + */ + u8 lane_mask; +}; + +#define QMP_PHY_INIT_CFG(o, v) \ + { \ + .offset = o, \ + .val = v, \ + .lane_mask = 0xff, \ + } + +#define QMP_PHY_INIT_CFG_LANE(o, v, l) \ + { \ + .offset = o, \ + .val = v, \ + .lane_mask = l, \ + } + +/* set of registers with offsets different per-PHY */ +enum qphy_reg_layout { + /* PCS registers */ + QPHY_SW_RESET, + QPHY_START_CTRL, + QPHY_PCS_STATUS, + QPHY_PCS_POWER_DOWN_CONTROL, + /* Keep last to ensure regs_layout arrays are properly initialized */ + QPHY_LAYOUT_SIZE +}; + +static const unsigned int pciephy_v5_regs_layout[QPHY_LAYOUT_SIZE] = { + [QPHY_SW_RESET] = QPHY_V5_PCS_SW_RESET, + [QPHY_START_CTRL] = QPHY_V5_PCS_START_CONTROL, + [QPHY_PCS_STATUS] = QPHY_V5_PCS_PCS_STATUS1, + [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_POWER_DOWN_CONTROL, +}; + +static const unsigned int pciephy_v6_regs_layout[QPHY_LAYOUT_SIZE] = { + [QPHY_SW_RESET] = QPHY_V6_PCS_SW_RESET, + [QPHY_START_CTRL] = QPHY_V6_PCS_START_CONTROL, + [QPHY_PCS_STATUS] = QPHY_V6_PCS_PCS_STATUS1, + [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V6_PCS_POWER_DOWN_CONTROL, +}; + +static const struct qmp_pcie_init_tbl sm8550_qmp_gen3x2_pcie_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xf8), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x93), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x42), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0d), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x34), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xaa), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0x55), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0x55), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC_3, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0), +}; + +static const struct qmp_pcie_init_tbl sm8550_qmp_gen3x2_pcie_tx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0x15), + QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_4, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V6_TX_PI_QEC_CTRL, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x18), +}; + +static const struct qmp_pcie_init_tbl sm8550_qmp_gen3x2_pcie_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_GM_CAL, 0x11), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xbf), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xb7), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xea), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_LOW, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH, 0x5c), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH2, 0x9c), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH3, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH4, 0x89), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_LOW, 0xdc), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH, 0x94), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH2, 0x5b), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH3, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH4, 0x89), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_TX_ADAPT_POST_THRESH, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FO_GAIN, 0x09), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_GAIN, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH1, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH2, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL2, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIDGET_ENABLES, 0x1c), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_LOW, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_TRIM, 0x08), +}; + +static const struct qmp_pcie_init_tbl sm8550_qmp_gen3x2_pcie_pcs_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V6_PCS_REFGEN_REQ_CONFIG1, 0x05), + QMP_PHY_INIT_CFG(QPHY_V6_PCS_RX_SIGDET_LVL, 0x77), + QMP_PHY_INIT_CFG(QPHY_V6_PCS_RATE_SLEW_CNTRL1, 0x0b), + QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG2, 0x0f), + QMP_PHY_INIT_CFG(QPHY_V6_PCS_PCS_TX_RX_CONFIG, 0x8c), +}; + +static const struct qmp_pcie_init_tbl sm8550_qmp_gen3x2_pcie_pcs_misc_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_EQ_CONFIG1, 0x1e), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_RXEQEVAL_TIME, 0x27), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), +}; + +static const struct qmp_pcie_init_tbl sm8550_qmp_gen4x2_pcie_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x26), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x68), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0xab), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xaa), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x12), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xf8), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0d), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xaa), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_POST_DIV_MUX, 0x40), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x46), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MISC_1, 0x88), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MODE, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_VCO_DC_LEVEL_CTRL, 0x0f), +}; + +static const struct qmp_pcie_init_tbl sm8550_qmp_gen4x2_pcie_ln_shrd_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RXCLK_DIV2_CTRL, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_DFE_DAC_ENABLE1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2, 0x0d), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B0, 0x12), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B1, 0x12), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B2, 0xdb), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B3, 0x9a), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B4, 0x38), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B5, 0xb6), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B6, 0x64), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_SUMMER_CAL_SPD_MODE, 0x5b), +}; + +static const struct qmp_pcie_init_tbl sm8550_qmp_gen4x2_pcie_tx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1d), + QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_RX, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_1, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_3, 0x51), + QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_TRAN_DRVR_EMP_EN, 0x34), +}; + +static const struct qmp_pcie_init_tbl sm8550_qmp_gen4x2_pcie_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_GAIN_RATE_2, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_PI_CONTROLS, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_CAL_CTRL2, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_POSTCAL_OFFSET, 0x7c), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_3, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_TX_ADPT_CTRL, 0x10), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_GM_CAL, 0x0d), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_SIGDET_ENABLES, 0x1c), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_PHPRE_CTRL, 0x20), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x09), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B0, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B1, 0xb3), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B2, 0x58), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B3, 0x9a), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B4, 0x26), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B5, 0xb6), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B6, 0xee), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B0, 0xdb), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B1, 0xdb), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B2, 0xa0), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B3, 0xdf), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B4, 0x78), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B5, 0x76), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B6, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V6_20_VGA_CAL_CNTRL1, 0x00), +}; + +static const struct qmp_pcie_init_tbl sm8550_qmp_gen4x2_pcie_pcs_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_G12S1_TXDEEMPH_M6DB, 0x17), + QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_G3S2_PRE_GAIN, 0x2e), + QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_RX_SIGDET_LVL, 0xcc), + QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG4, 0x00), + QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG5, 0x22), + QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_TX_RX_CONFIG1, 0x04), + QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_TX_RX_CONFIG2, 0x02), +}; + +static const struct qmp_pcie_init_tbl sm8550_qmp_gen4x2_pcie_pcs_misc_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_DRIVE, 0xc1), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_OSC_DTCT_ATCIONS, 0x00), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG1, 0x16), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G3_RXEQEVAL_TIME, 0x27), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_RXEQEVAL_TIME, 0x27), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG5, 0x02), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_PRE_GAIN, 0x2e), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG1, 0x03), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG3, 0x28), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_TX_RX_CONFIG, 0xc0), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_POWER_STATE_CONFIG2, 0x1d), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG5, 0x0f), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G3_FOM_EQ_CONFIG5, 0xf2), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_FOM_EQ_CONFIG5, 0xf2), +}; + +static const struct qmp_pcie_init_tbl sm8650_qmp_gen4x2_pcie_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_PI_CONTROLS, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_CAL_CTRL2, 0x82), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_3, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_GM_CAL, 0x0d), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_SIGDET_ENABLES, 0x1c), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_PHPRE_CTRL, 0x20), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B0, 0xd3), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B1, 0xd3), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B3, 0x9a), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B4, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B5, 0xb6), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B6, 0xee), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B0, 0x23), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B1, 0x9b), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B2, 0x60), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B3, 0xdf), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B4, 0x43), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B5, 0x76), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B6, 0xff), +}; + +static const struct qmp_pcie_init_tbl x1e80100_qmp_gen4x2_pcie_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x26), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x68), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0xab), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xaa), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x12), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xf8), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0d), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xaa), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_POST_DIV_MUX, 0x40), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x46), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MISC_1, 0x88), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MODE, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_VCO_DC_LEVEL_CTRL, 0x0f), +}; + +static const struct qmp_pcie_init_tbl x1e80100_qmp_gen4x2_pcie_ln_shrd_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RXCLK_DIV2_CTRL, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_DFE_DAC_ENABLE1, 0x88), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2, 0x0d), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B0, 0xd4), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B1, 0x12), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B2, 0xdb), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B3, 0x9a), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B4, 0x32), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B5, 0xb6), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B6, 0x64), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_SUMMER_CAL_SPD_MODE, 0x5b), +}; + +static const struct qmp_pcie_init_tbl x1e80100_qmp_gen4x2_pcie_tx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1d), + QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_RX, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_1, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_2, 0x10), + QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_3, 0x51), + QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_TRAN_DRVR_EMP_EN, 0x34), +}; + +static const struct qmp_pcie_init_tbl x1e80100_qmp_gen4x2_pcie_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_GAIN_RATE_2, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_PI_CONTROLS, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_CAL_CTRL2, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_POSTCAL_OFFSET, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_BKUP_CTRL1, 0x15), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_1, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_2, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_3, 0x45), + QMP_PHY_INIT_CFG_LANE(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0a, 1), + QMP_PHY_INIT_CFG_LANE(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0b, 2), + QMP_PHY_INIT_CFG(QSERDES_V6_20_VGA_CAL_CNTRL1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_GM_CAL, 0x0d), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_SIGDET_ENABLES, 0x1c), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_PHPRE_CTRL, 0x20), + QMP_PHY_INIT_CFG_LANE(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x3a, 1), + QMP_PHY_INIT_CFG_LANE(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38, 2), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x39), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B0, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B1, 0xb3), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B2, 0x58), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B3, 0x9a), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B4, 0x26), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B5, 0xb6), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B6, 0xee), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B0, 0xe4), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B1, 0xa4), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B2, 0x60), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B3, 0xdf), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B4, 0x4b), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B5, 0x76), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B6, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_TX_ADPT_CTRL, 0x10), +}; + +static const struct qmp_pcie_init_tbl x1e80100_qmp_gen4x2_pcie_pcs_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_G3S2_PRE_GAIN, 0x2e), + QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_RX_SIGDET_LVL, 0xcc), + QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG4, 0x00), + QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG5, 0x22), + QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_TX_RX_CONFIG1, 0x04), + QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_TX_RX_CONFIG2, 0x02), +}; + +static const struct qmp_pcie_init_tbl x1e80100_qmp_gen4x2_pcie_pcs_misc_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_DRIVE, 0xc1), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_OSC_DTCT_ATCIONS, 0x00), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG1, 0x16), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG5, 0x02), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_PRE_GAIN, 0x2e), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG1, 0x03), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG3, 0x28), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G3_RXEQEVAL_TIME, 0x27), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_RXEQEVAL_TIME, 0x27), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_TX_RX_CONFIG, 0xc0), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_POWER_STATE_CONFIG2, 0x1d), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG5, 0x18), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G3_FOM_EQ_CONFIG5, 0x7a), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_FOM_EQ_CONFIG5, 0x8a), +}; + +struct qmp_pcie_offsets { + u16 serdes; + u16 pcs; + u16 pcs_misc; + u16 tx; + u16 rx; + u16 tx2; + u16 rx2; + u16 ln_shrd; +}; + +struct qmp_pcie_cfg_tbls { + /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ + const struct qmp_pcie_init_tbl *serdes; + int serdes_num; + const struct qmp_pcie_init_tbl *tx; + int tx_num; + const struct qmp_pcie_init_tbl *rx; + int rx_num; + const struct qmp_pcie_init_tbl *pcs; + int pcs_num; + const struct qmp_pcie_init_tbl *pcs_misc; + int pcs_misc_num; + const struct qmp_pcie_init_tbl *ln_shrd; + int ln_shrd_num; +}; + +/* struct qmp_pcie_cfg - per-PHY initialization config */ +struct qmp_pcie_cfg { + int lanes; + + const struct qmp_pcie_offsets *offsets; + + /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */ + const struct qmp_pcie_cfg_tbls tbls; + + /* regulators to be requested */ + const char * const *vreg_list; + int num_vregs; + /* resets to be requested */ + const char * const *reset_list; + int num_resets; + + /* array of registers with different offsets */ + const unsigned int *regs; + + unsigned int pwrdn_ctrl; + /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */ + unsigned int phy_status; + + bool has_nocsr_reset; +}; + +struct qmp_pcie_priv { + struct phy *phy; + + void __iomem *serdes; + void __iomem *pcs; + void __iomem *pcs_misc; + void __iomem *tx; + void __iomem *rx; + void __iomem *tx2; + void __iomem *rx2; + void __iomem *ln_shrd; + + struct clk *clks; + unsigned int clk_count; + + struct clk pipe_clk; + + struct reset_ctl *resets; + unsigned int reset_count; + + struct reset_ctl nocsr_reset; + + struct udevice *vregs[NUM_SUPPLIES]; + unsigned int vreg_count; + + const struct qmp_pcie_cfg *cfg; + struct udevice *dev; +}; + +static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) +{ + u32 reg; + + reg = readl(base + offset); + reg |= val; + writel(reg, base + offset); + + /* ensure that above write is through */ + readl(base + offset); +} + +static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) +{ + u32 reg; + + reg = readl(base + offset); + reg &= ~val; + writel(reg, base + offset); + + /* ensure that above write is through */ + readl(base + offset); +} + +/* list of clocks required by phy */ +static const char * const qmp_pciephy_clk_l[] = { + "aux", "cfg_ahb", "ref", "rchng", +}; + +/* list of regulators */ +static const char * const qmp_phy_vreg_l[] = { + "vdda-phy-supply", "vdda-pll-supply", +}; + +static const char * const sm8550_qmp_phy_vreg_l[] = { + "vdda-phy-supply", "vdda-pll-supply", "vdda-qref-supply", +}; + +/* list of resets */ +static const char * const sdm845_pciephy_reset_l[] = { + "phy", +}; + +static const struct qmp_pcie_offsets qmp_pcie_offsets_v5 = { + .serdes = 0, + .pcs = 0x0200, + .pcs_misc = 0x0600, + .tx = 0x0e00, + .rx = 0x1000, + .tx2 = 0x1600, + .rx2 = 0x1800, +}; + +static const struct qmp_pcie_offsets qmp_pcie_offsets_v6_20 = { + .serdes = 0x1000, + .pcs = 0x1200, + .pcs_misc = 0x1400, + .tx = 0x0000, + .rx = 0x0200, + .tx2 = 0x0800, + .rx2 = 0x0a00, + .ln_shrd = 0x0e00, +}; + +static const struct qmp_pcie_cfg sm8550_qmp_gen3x2_pciephy_cfg = { + .lanes = 2, + + .offsets = &qmp_pcie_offsets_v5, + + .tbls = { + .serdes = sm8550_qmp_gen3x2_pcie_serdes_tbl, + .serdes_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_serdes_tbl), + .tx = sm8550_qmp_gen3x2_pcie_tx_tbl, + .tx_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_tx_tbl), + .rx = sm8550_qmp_gen3x2_pcie_rx_tbl, + .rx_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_rx_tbl), + .pcs = sm8550_qmp_gen3x2_pcie_pcs_tbl, + .pcs_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_tbl), + .pcs_misc = sm8550_qmp_gen3x2_pcie_pcs_misc_tbl, + .pcs_misc_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_misc_tbl), + }, + .reset_list = sdm845_pciephy_reset_l, + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = pciephy_v5_regs_layout, + + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, + .phy_status = PHYSTATUS, +}; + +static const struct qmp_pcie_cfg sm8550_qmp_gen4x2_pciephy_cfg = { + .lanes = 2, + + .offsets = &qmp_pcie_offsets_v6_20, + + .tbls = { + .serdes = sm8550_qmp_gen4x2_pcie_serdes_tbl, + .serdes_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_serdes_tbl), + .tx = sm8550_qmp_gen4x2_pcie_tx_tbl, + .tx_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_tx_tbl), + .rx = sm8550_qmp_gen4x2_pcie_rx_tbl, + .rx_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_rx_tbl), + .pcs = sm8550_qmp_gen4x2_pcie_pcs_tbl, + .pcs_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_tbl), + .pcs_misc = sm8550_qmp_gen4x2_pcie_pcs_misc_tbl, + .pcs_misc_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_misc_tbl), + .ln_shrd = sm8550_qmp_gen4x2_pcie_ln_shrd_tbl, + .ln_shrd_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_ln_shrd_tbl), + }, + .reset_list = sdm845_pciephy_reset_l, + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), + .vreg_list = sm8550_qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l), + .regs = pciephy_v6_regs_layout, + + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, + .phy_status = PHYSTATUS_4_20, + .has_nocsr_reset = true, +}; + +static const struct qmp_pcie_cfg sm8650_qmp_gen4x2_pciephy_cfg = { + .lanes = 2, + + .offsets = &qmp_pcie_offsets_v6_20, + + .tbls = { + .serdes = sm8550_qmp_gen4x2_pcie_serdes_tbl, + .serdes_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_serdes_tbl), + .tx = sm8550_qmp_gen4x2_pcie_tx_tbl, + .tx_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_tx_tbl), + .rx = sm8650_qmp_gen4x2_pcie_rx_tbl, + .rx_num = ARRAY_SIZE(sm8650_qmp_gen4x2_pcie_rx_tbl), + .pcs = sm8550_qmp_gen4x2_pcie_pcs_tbl, + .pcs_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_tbl), + .pcs_misc = sm8550_qmp_gen4x2_pcie_pcs_misc_tbl, + .pcs_misc_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_misc_tbl), + .ln_shrd = sm8550_qmp_gen4x2_pcie_ln_shrd_tbl, + .ln_shrd_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_ln_shrd_tbl), + }, + .reset_list = sdm845_pciephy_reset_l, + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), + .vreg_list = sm8550_qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l), + .regs = pciephy_v6_regs_layout, + + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, + .phy_status = PHYSTATUS_4_20, + .has_nocsr_reset = true, +}; + +static const struct qmp_pcie_cfg x1e80100_qmp_gen4x2_pciephy_cfg = { + .lanes = 2, + + .offsets = &qmp_pcie_offsets_v6_20, + + .tbls = { + .serdes = x1e80100_qmp_gen4x2_pcie_serdes_tbl, + .serdes_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_serdes_tbl), + .tx = x1e80100_qmp_gen4x2_pcie_tx_tbl, + .tx_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_tx_tbl), + .rx = x1e80100_qmp_gen4x2_pcie_rx_tbl, + .rx_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_rx_tbl), + .pcs = x1e80100_qmp_gen4x2_pcie_pcs_tbl, + .pcs_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_pcs_tbl), + .pcs_misc = x1e80100_qmp_gen4x2_pcie_pcs_misc_tbl, + .pcs_misc_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_pcs_misc_tbl), + .ln_shrd = x1e80100_qmp_gen4x2_pcie_ln_shrd_tbl, + .ln_shrd_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_ln_shrd_tbl), + }, + .reset_list = sdm845_pciephy_reset_l, + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = pciephy_v6_regs_layout, + + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, + .phy_status = PHYSTATUS_4_20, + .has_nocsr_reset = true, +}; + +static void qmp_pcie_configure_lane(void __iomem *base, + const struct qmp_pcie_init_tbl tbl[], + int num, u8 lane_mask) +{ + int i; + const struct qmp_pcie_init_tbl *t = tbl; + + if (!t) + return; + + for (i = 0; i < num; i++, t++) { + if (!(t->lane_mask & lane_mask)) + continue; + + writel(t->val, base + t->offset); + } +} + +static void qmp_pcie_configure(void __iomem *base, + const struct qmp_pcie_init_tbl tbl[], + int num) +{ + qmp_pcie_configure_lane(base, tbl, num, 0xff); +} + +static void qmp_pcie_init_registers(struct qmp_pcie_priv *qmp, const struct qmp_pcie_cfg *cfg) +{ + const struct qmp_pcie_cfg_tbls *tbls = &cfg->tbls; + void __iomem *serdes = qmp->serdes; + void __iomem *tx = qmp->tx; + void __iomem *rx = qmp->rx; + void __iomem *tx2 = qmp->tx2; + void __iomem *rx2 = qmp->rx2; + void __iomem *pcs = qmp->pcs; + void __iomem *pcs_misc = qmp->pcs_misc; + void __iomem *ln_shrd = qmp->ln_shrd; + + qmp_pcie_configure(serdes, tbls->serdes, tbls->serdes_num); + + qmp_pcie_configure_lane(tx, tbls->tx, tbls->tx_num, 1); + qmp_pcie_configure_lane(rx, tbls->rx, tbls->rx_num, 1); + + if (cfg->lanes >= 2) { + qmp_pcie_configure_lane(tx2, tbls->tx, tbls->tx_num, 2); + qmp_pcie_configure_lane(rx2, tbls->rx, tbls->rx_num, 2); + } + + qmp_pcie_configure(pcs, tbls->pcs, tbls->pcs_num); + qmp_pcie_configure(pcs_misc, tbls->pcs_misc, tbls->pcs_misc_num); + + qmp_pcie_configure(ln_shrd, tbls->ln_shrd, tbls->ln_shrd_num); +} + +static int qmp_pcie_do_reset(struct qmp_pcie_priv *qmp) +{ + const struct qmp_pcie_cfg *cfg = qmp->cfg; + int i, ret; + + for (i = 0; i < qmp->reset_count; i++) { + ret = reset_assert(&qmp->resets[i]); + if (ret) + return ret; + } + + if (cfg->has_nocsr_reset) + reset_assert(&qmp->nocsr_reset); + + udelay(10); + + for (i = 0; i < qmp->reset_count; i++) { + ret = reset_deassert(&qmp->resets[i]); + if (ret) + return ret; + } + + udelay(50); + + return 0; +} + +static int qmp_pcie_power_on(struct phy *phy) +{ + struct qmp_pcie_priv *qmp = dev_get_priv(phy->dev); + const struct qmp_pcie_cfg *cfg = qmp->cfg; + void __iomem *pcs = qmp->pcs; + void __iomem *status; + unsigned int mask, val; + int ret, i; + + for (i = 0; i < qmp->vreg_count; i++) { + ret = regulator_set_enable(qmp->vregs[i], true); + if (ret && ret != -ENOSYS) + dev_err(phy->dev, "failed to enable regulator %d (%d)\n", i, ret); + } + + ret = qmp_pcie_do_reset(qmp); + if (ret) + return ret; + + for (i = 0; i < qmp->clk_count; i++) { + ret = clk_enable(&qmp->clks[i]); + if (ret && ret != -ENOSYS) { + dev_err(phy->dev, "failed to enable clock %d\n", i); + return ret; + } + } + + /* Power down PHY */ + qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], cfg->pwrdn_ctrl); + + qmp_pcie_init_registers(qmp, cfg); + + clk_enable(&qmp->pipe_clk); + + if (cfg->has_nocsr_reset) + reset_deassert(&qmp->nocsr_reset); + + /* Pull PHY out of reset state */ + qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); + + /* start SerDes */ + qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START); + + status = pcs + cfg->regs[QPHY_PCS_STATUS]; + mask = cfg->phy_status; + ret = readl_poll_timeout(status, val, !(val & mask), PHY_INIT_COMPLETE_TIMEOUT); + if (ret) { + dev_err(phy->dev, "phy initialization timed-out\n"); + return ret; + } + + return 0; +} + +static int qmp_pcie_power_off(struct phy *phy) +{ + struct qmp_pcie_priv *qmp = dev_get_priv(phy->dev); + const struct qmp_pcie_cfg *cfg = qmp->cfg; + + clk_disable(&qmp->pipe_clk); + + /* PHY reset */ + qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); + + /* stop SerDes and Phy-Coding-Sublayer */ + qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL], + SERDES_START | PCS_START); + + /* Put PHY into POWER DOWN state: active low */ + qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], + cfg->pwrdn_ctrl); + + return 0; +} + +static int qmp_pcie_vreg_init(struct udevice *dev, struct qmp_pcie_priv *qmp) +{ + const struct qmp_pcie_cfg *cfg = qmp->cfg; + unsigned int vreg; + int ret; + + qmp->vreg_count = cfg->num_vregs; + + for (vreg = 0; vreg < NUM_SUPPLIES && vreg < qmp->vreg_count; ++vreg) { + ret = device_get_supply_regulator(dev, cfg->vreg_list[vreg], &qmp->vregs[vreg]); + if (ret) + dev_warn(dev, "failed to get regulator %d (%d)\n", vreg, ret); + + regulator_set_enable(qmp->vregs[vreg], true); + } + + return 0; +} + +static int qmp_pcie_reset_init(struct udevice *dev, struct qmp_pcie_priv *qmp) +{ + const struct qmp_pcie_cfg *cfg = qmp->cfg; + int num = cfg->num_resets; + int i, ret; + + qmp->reset_count = 0; + qmp->resets = devm_kcalloc(dev, num, sizeof(*qmp->resets), GFP_KERNEL); + if (!qmp->resets) + return -ENOMEM; + + for (i = 0; i < num; i++) { + ret = reset_get_by_name(dev, cfg->reset_list[i], &qmp->resets[i]); + if (ret) { + dev_err(dev, "failed to get reset %d\n", i); + goto reset_get_err; + } + + ++qmp->reset_count; + } + + if (cfg->has_nocsr_reset) { + ret = reset_get_by_name(dev, "phy_nocsr", &qmp->nocsr_reset); + if (ret) + dev_warn(dev, "failed to get nocsr reset\n"); + } + + return 0; + +reset_get_err: + reset_release_all(qmp->resets, qmp->reset_count); + + return ret; +} + +static int qmp_pcie_clk_init(struct udevice *dev, struct qmp_pcie_priv *qmp) +{ + int num = ARRAY_SIZE(qmp_pciephy_clk_l); + int i, ret; + + qmp->clk_count = 0; + qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); + if (!qmp->clks) + return -ENOMEM; + + for (i = 0; i < num; i++) { + ret = clk_get_by_name(dev, qmp_pciephy_clk_l[i], &qmp->clks[i]); + /* Ignore failure to get ref clock */ + if (ret && strcmp(qmp_pciephy_clk_l[i], "ref") != 0) { + dev_err(dev, "failed to get clock %d\n", i); + goto clk_get_err; + } + + ++qmp->clk_count; + } + + ret = clk_get_by_name(dev, "pipe", &qmp->pipe_clk); + if (ret) + dev_warn(dev, "failed to get pipe clock\n"); + + return 0; + +clk_get_err: + clk_release_all(qmp->clks, qmp->clk_count); + + return ret; +} + +static int qmp_pcie_parse_dt(struct udevice *dev, struct qmp_pcie_priv *qmp) +{ + const struct qmp_pcie_offsets *offs = qmp->cfg->offsets; + const struct qmp_pcie_cfg *cfg = qmp->cfg; + struct resource res; + int ret; + + if (!qmp->cfg->offsets) { + dev_err(dev, "missing PCIE offsets\n"); + return -EINVAL; + } + + ret = ofnode_read_resource(dev_ofnode(dev), 0, &res); + if (ret) { + dev_err(dev, "can't get reg property\n"); + return ret; + } + + qmp->serdes = (void __iomem *)res.start + offs->serdes; + qmp->pcs = (void __iomem *)res.start + offs->pcs; + qmp->pcs_misc = (void __iomem *)res.start + offs->pcs_misc; + qmp->tx = (void __iomem *)res.start + offs->tx; + qmp->rx = (void __iomem *)res.start + offs->rx; + + if (qmp->cfg->lanes >= 2) { + qmp->tx2 = (void __iomem *)res.start + offs->tx2; + qmp->rx2 = (void __iomem *)res.start + offs->rx2; + } + + if (cfg->tbls.ln_shrd) + qmp->ln_shrd = (void __iomem *)res.start + offs->ln_shrd; + + return 0; +} + +static int qmp_pcie_probe(struct udevice *dev) +{ + struct qmp_pcie_priv *qmp = dev_get_priv(dev); + int ret; + + qmp->serdes = (void __iomem *)dev_read_addr(dev); + if (IS_ERR(qmp->serdes)) + return PTR_ERR(qmp->serdes); + + qmp->cfg = (const struct qmp_pcie_cfg *)dev_get_driver_data(dev); + if (!qmp->cfg) + return -EINVAL; + + ret = qmp_pcie_clk_init(dev, qmp); + if (ret) { + dev_err(dev, "failed to get PCIE clks\n"); + return ret; + } + + ret = qmp_pcie_vreg_init(dev, qmp); + if (ret) { + dev_err(dev, "failed to get PCIE voltage regulators\n"); + return ret; + } + + ret = qmp_pcie_reset_init(dev, qmp); + if (ret) { + dev_err(dev, "failed to get PCIE resets\n"); + return ret; + } + + qmp->dev = dev; + + return qmp_pcie_parse_dt(dev, qmp); +} + +static struct phy_ops qmp_pcie_ops = { + .power_on = qmp_pcie_power_on, + .power_off = qmp_pcie_power_off, +}; + +static const struct udevice_id qmp_pcie_ids[] = { + { + .compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy", + .data = (ulong)&sm8550_qmp_gen3x2_pciephy_cfg, + }, { + .compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy", + .data = (ulong)&sm8550_qmp_gen4x2_pciephy_cfg + }, { + .compatible = "qcom,sm8650-qmp-gen3x2-pcie-phy", + .data = (ulong)&sm8550_qmp_gen3x2_pciephy_cfg, + }, { + .compatible = "qcom,sm8650-qmp-gen4x2-pcie-phy", + .data = (ulong)&sm8650_qmp_gen4x2_pciephy_cfg + }, { + .compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy", + .data = (ulong)&sm8550_qmp_gen3x2_pciephy_cfg + }, { + .compatible = "qcom,x1e80100-qmp-gen4x2-pcie-phy", + .data = (ulong)&x1e80100_qmp_gen4x2_pciephy_cfg + }, { + .compatible = "qcom,x1e80100-qmp-gen4x4-pcie-phy", + .data = (ulong)&x1e80100_qmp_gen4x2_pciephy_cfg + }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(qcom_qmp_pcie) = { + .name = "qcom-qmp-pcie", + .id = UCLASS_PHY, + .of_match = qmp_pcie_ids, + .ops = &qmp_pcie_ops, + .probe = qmp_pcie_probe, + .priv_auto = sizeof(struct qmp_pcie_priv), +}; diff --git a/drivers/phy/qcom/phy-qcom-qmp-pcs-misc-v3.h b/drivers/phy/qcom/phy-qcom-qmp-pcs-misc-v3.h new file mode 100644 index 00000000000..a45bd301bc9 --- /dev/null +++ b/drivers/phy/qcom/phy-qcom-qmp-pcs-misc-v3.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_PCS_MISC_V3_H_ +#define QCOM_PHY_QMP_PCS_MISC_V3_H_ + +/* Only for QMP V3 PHY - PCS_MISC registers */ +#define QPHY_V3_PCS_MISC_CLAMP_ENABLE 0x0c +#define QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2 0x2c +#define QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1 0x44 +#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2 0x54 +#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4 0x5c +#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5 0x60 + +#endif diff --git a/drivers/phy/qcom/phy-qcom-qmp-pcs-pcie-v4.h b/drivers/phy/qcom/phy-qcom-qmp-pcs-pcie-v4.h new file mode 100644 index 00000000000..4cc02288d41 --- /dev/null +++ b/drivers/phy/qcom/phy-qcom-qmp-pcs-pcie-v4.h @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_PCS_PCIE_V4_H_ +#define QCOM_PHY_QMP_PCS_PCIE_V4_H_ + +/* Only for QMP V4 PHY - PCS_PCIE registers (same as PCS_MISC?) */ +#define QPHY_V4_PCS_PCIE_INT_AUX_CLK_STATUS 0x00 +#define QPHY_V4_PCS_PCIE_OSC_DTCT_STATUS 0x04 +#define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG1 0x08 +#define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2 0x0c +#define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG3 0x10 +#define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4 0x14 +#define QPHY_V4_PCS_PCIE_PCS_TX_RX_CONFIG 0x18 +#define QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x1c +#define QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_CNTRL 0x20 +#define QPHY_V4_PCS_PCIE_EPCLK_PRE_PLL_LOCK_DLY_AUXCLK 0x24 +#define QPHY_V4_PCS_PCIE_EPCLK_DLY_COUNT_VAL_L 0x28 +#define QPHY_V4_PCS_PCIE_EPCLK_DLY_COUNT_VAL_H 0x2c +#define QPHY_V4_PCS_PCIE_RX_IDLE_DTCT_CNTRL1 0x30 +#define QPHY_V4_PCS_PCIE_RX_IDLE_DTCT_CNTRL2 0x34 +#define QPHY_V4_PCS_PCIE_SIGDET_CNTRL 0x38 +#define QPHY_V4_PCS_PCIE_SIGDET_LOW_2_IDLE_TIME 0x3c +#define QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x40 +#define QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H 0x44 +#define QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x48 +#define QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H 0x4c +#define QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x50 +#define QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG2 0x54 +#define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG1 0x58 +#define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG2 0x5c +#define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG3 0x60 +#define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG4 0x64 +#define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG5 0x68 +#define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG6 0x6c +#define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG7 0x70 +#define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG1 0x74 +#define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2 0x78 +#define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG3 0x7c +#define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4 0x80 +#define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x84 +#define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG6 0x88 +#define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG7 0x8c +#define QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS 0x90 +#define QPHY_V4_PCS_PCIE_LOCAL_FS 0x94 +#define QPHY_V4_PCS_PCIE_LOCAL_LF 0x98 +#define QPHY_V4_PCS_PCIE_LOCAL_FS_RS 0x9c +#define QPHY_V4_PCS_PCIE_EQ_CONFIG1 0xa0 +#define QPHY_V4_PCS_PCIE_EQ_CONFIG2 0xa4 +#define QPHY_V4_PCS_PCIE_PRESET_P0_P1_PRE 0xa8 +#define QPHY_V4_PCS_PCIE_PRESET_P2_P3_PRE 0xac +#define QPHY_V4_PCS_PCIE_PRESET_P4_P5_PRE 0xb0 +#define QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE 0xb4 +#define QPHY_V4_PCS_PCIE_PRESET_P8_P9_PRE 0xb8 +#define QPHY_V4_PCS_PCIE_PRESET_P10_PRE 0xbc +#define QPHY_V4_PCS_PCIE_PRESET_P1_P3_PRE_RS 0xc0 +#define QPHY_V4_PCS_PCIE_PRESET_P4_P5_PRE_RS 0xc4 +#define QPHY_V4_PCS_PCIE_PRESET_P6_P9_PRE_RS 0xc8 +#define QPHY_V4_PCS_PCIE_PRESET_P0_P1_POST 0xcc +#define QPHY_V4_PCS_PCIE_PRESET_P2_P3_POST 0xd0 +#define QPHY_V4_PCS_PCIE_PRESET_P4_P5_POST 0xd4 +#define QPHY_V4_PCS_PCIE_PRESET_P6_P7_POST 0xd8 +#define QPHY_V4_PCS_PCIE_PRESET_P8_P9_POST 0xdc +#define QPHY_V4_PCS_PCIE_PRESET_P10_POST 0xe0 +#define QPHY_V4_PCS_PCIE_PRESET_P1_P3_POST_RS 0xe4 +#define QPHY_V4_PCS_PCIE_PRESET_P4_P5_POST_RS 0xe8 +#define QPHY_V4_PCS_PCIE_PRESET_P6_P9_POST_RS 0xec +#define QPHY_V4_PCS_PCIE_RXEQEVAL_TIME 0xf0 + +#endif diff --git a/drivers/phy/qcom/phy-qcom-qmp-pcs-pcie-v4_20.h b/drivers/phy/qcom/phy-qcom-qmp-pcs-pcie-v4_20.h new file mode 100644 index 00000000000..ac872a9eff9 --- /dev/null +++ b/drivers/phy/qcom/phy-qcom-qmp-pcs-pcie-v4_20.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_PCS_PCIE_V4_20_H_ +#define QCOM_PHY_QMP_PCS_PCIE_V4_20_H_ + +#define QPHY_V4_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c +#define QPHY_V4_20_PCS_PCIE_OSC_DTCT_ACTIONS 0x090 +#define QPHY_V4_20_PCS_PCIE_EQ_CONFIG1 0x0a0 +#define QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME 0x0f0 +#define QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME 0x0f4 +#define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2 0x0fc +#define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5 0x108 +#define QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2 0x824 +#define QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2 0x828 + +#endif diff --git a/drivers/phy/qcom/phy-qcom-qmp-pcs-pcie-v5.h b/drivers/phy/qcom/phy-qcom-qmp-pcs-pcie-v5.h new file mode 100644 index 00000000000..2801bcf10f2 --- /dev/null +++ b/drivers/phy/qcom/phy-qcom-qmp-pcs-pcie-v5.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_PCS_PCIE_V5_H_ +#define QCOM_PHY_QMP_PCS_PCIE_V5_H_ + +/* Only for QMP V5 PHY - PCS_PCIE registers */ +#define QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG2 0x0c +#define QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG4 0x14 +#define QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20 +#define QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x54 +#define QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS 0x94 +#define QPHY_V5_PCS_PCIE_EQ_CONFIG2 0xa8 + +#endif diff --git a/drivers/phy/qcom/phy-qcom-qmp-pcs-pcie-v5_20.h b/drivers/phy/qcom/phy-qcom-qmp-pcs-pcie-v5_20.h new file mode 100644 index 00000000000..cdf8c04ea07 --- /dev/null +++ b/drivers/phy/qcom/phy-qcom-qmp-pcs-pcie-v5_20.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_PCS_PCIE_V5_20_H_ +#define QCOM_PHY_QMP_PCS_PCIE_V5_20_H_ + +/* Only for QMP V5_20 PHY - PCIe PCS registers */ +#define QPHY_V5_20_PCS_PCIE_POWER_STATE_CONFIG2 0x00c +#define QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c +#define QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x084 +#define QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS 0x090 +#define QPHY_V5_20_PCS_PCIE_EQ_CONFIG1 0x0a0 +#define QPHY_V5_20_PCS_PCIE_PRESET_P10_POST 0x0e0 +#define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG2 0x0fc +#define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5 0x108 +#define QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN 0x15c +#define QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3 0x184 +#define QPHY_V5_20_PCS_LANE1_INSIG_SW_CTRL2 0xa24 +#define QPHY_V5_20_PCS_LANE1_INSIG_MX_CTRL2 0xa28 + +#endif diff --git a/drivers/phy/qcom/phy-qcom-qmp-pcs-pcie-v6.h b/drivers/phy/qcom/phy-qcom-qmp-pcs-pcie-v6.h new file mode 100644 index 00000000000..0ca79333d94 --- /dev/null +++ b/drivers/phy/qcom/phy-qcom-qmp-pcs-pcie-v6.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef QCOM_PHY_QMP_PCS_PCIE_V6_H_ +#define QCOM_PHY_QMP_PCS_PCIE_V6_H_ + +/* Only for QMP V6 PHY - PCIE have different offsets than V5 */ +#define QPHY_PCIE_V6_PCS_PCIE_EQ_CONFIG1 0xa4 +#define QPHY_PCIE_V6_PCS_PCIE_RXEQEVAL_TIME 0xf4 +#define QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG2 0x0c +#define QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG4 0x14 +#define QPHY_PCIE_V6_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20 +#define QPHY_PCIE_V6_PCS_PCIE_OSC_DTCT_ACTIONS 0x94 + +#endif diff --git a/drivers/phy/qcom/phy-qcom-qmp-pcs-pcie-v6_20.h b/drivers/phy/qcom/phy-qcom-qmp-pcs-pcie-v6_20.h new file mode 100644 index 00000000000..dfcecf31a60 --- /dev/null +++ b/drivers/phy/qcom/phy-qcom-qmp-pcs-pcie-v6_20.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef QCOM_PHY_QMP_PCS_PCIE_V6_20_H_ +#define QCOM_PHY_QMP_PCS_PCIE_V6_20_H_ + +/* Only for QMP V6_20 PHY - PCIE have different offsets than V5 */ +#define QPHY_PCIE_V6_20_PCS_POWER_STATE_CONFIG2 0x00c +#define QPHY_PCIE_V6_20_PCS_TX_RX_CONFIG 0x018 +#define QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_DRIVE 0x01c +#define QPHY_PCIE_V6_20_PCS_OSC_DTCT_ATCIONS 0x090 +#define QPHY_PCIE_V6_20_PCS_EQ_CONFIG1 0x0a0 +#define QPHY_PCIE_V6_20_PCS_G3_RXEQEVAL_TIME 0x0f0 +#define QPHY_PCIE_V6_20_PCS_G4_RXEQEVAL_TIME 0x0f4 +#define QPHY_PCIE_V6_20_PCS_EQ_CONFIG5 0x108 +#define QPHY_PCIE_V6_20_PCS_G4_PRE_GAIN 0x15c +#define QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG1 0x17c +#define QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG3 0x184 +#define QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG5 0x18c +#define QPHY_PCIE_V6_20_PCS_G3_FOM_EQ_CONFIG5 0x1ac +#define QPHY_PCIE_V6_20_PCS_G4_FOM_EQ_CONFIG5 0x1c0 + +#endif diff --git a/drivers/phy/qcom/phy-qcom-qmp-pcs-v5.h b/drivers/phy/qcom/phy-qcom-qmp-pcs-v5.h new file mode 100644 index 00000000000..36cc80bb905 --- /dev/null +++ b/drivers/phy/qcom/phy-qcom-qmp-pcs-v5.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_PCS_V5_H_ +#define QCOM_PHY_QMP_PCS_V5_H_ + +/* Only for QMP V5 PHY - USB/PCIe PCS registers */ +#define QPHY_V5_PCS_SW_RESET 0x000 +#define QPHY_V5_PCS_PCS_STATUS1 0x014 +#define QPHY_V5_PCS_POWER_DOWN_CONTROL 0x040 +#define QPHY_V5_PCS_START_CONTROL 0x044 +#define QPHY_V5_PCS_LOCK_DETECT_CONFIG1 0x0c4 +#define QPHY_V5_PCS_LOCK_DETECT_CONFIG2 0x0c8 +#define QPHY_V5_PCS_LOCK_DETECT_CONFIG3 0x0cc +#define QPHY_V5_PCS_LOCK_DETECT_CONFIG6 0x0d8 +#define QPHY_V5_PCS_REFGEN_REQ_CONFIG1 0x0dc +#define QPHY_V5_PCS_G3S2_PRE_GAIN 0x170 +#define QPHY_V5_PCS_RX_SIGDET_LVL 0x188 +#define QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_L 0x190 +#define QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_H 0x194 +#define QPHY_V5_PCS_RATE_SLEW_CNTRL1 0x198 +#define QPHY_V5_PCS_CDR_RESET_TIME 0x1b0 +#define QPHY_V5_PCS_RX_CONFIG 0x1b0 +#define QPHY_V5_PCS_ALIGN_DETECT_CONFIG1 0x1c0 +#define QPHY_V5_PCS_ALIGN_DETECT_CONFIG2 0x1c4 +#define QPHY_V5_PCS_PCS_TX_RX_CONFIG 0x1d0 +#define QPHY_V5_PCS_EQ_CONFIG1 0x1dc +#define QPHY_V5_PCS_EQ_CONFIG2 0x1e0 +#define QPHY_V5_PCS_EQ_CONFIG3 0x1e4 +#define QPHY_V5_PCS_EQ_CONFIG5 0x1ec + +#endif diff --git a/drivers/phy/qcom/phy-qcom-qmp-pcs-v6.h b/drivers/phy/qcom/phy-qcom-qmp-pcs-v6.h new file mode 100644 index 00000000000..08299d2b78f --- /dev/null +++ b/drivers/phy/qcom/phy-qcom-qmp-pcs-v6.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef QCOM_PHY_QMP_PCS_V6_H_ +#define QCOM_PHY_QMP_PCS_V6_H_ + +/* Only for QMP V6 PHY - USB/PCIe PCS registers */ +#define QPHY_V6_PCS_SW_RESET 0x000 +#define QPHY_V6_PCS_PCS_STATUS1 0x014 +#define QPHY_V6_PCS_POWER_DOWN_CONTROL 0x040 +#define QPHY_V6_PCS_START_CONTROL 0x044 +#define QPHY_V6_PCS_POWER_STATE_CONFIG1 0x090 +#define QPHY_V6_PCS_LOCK_DETECT_CONFIG1 0x0c4 +#define QPHY_V6_PCS_LOCK_DETECT_CONFIG2 0x0c8 +#define QPHY_V6_PCS_LOCK_DETECT_CONFIG3 0x0cc +#define QPHY_V6_PCS_LOCK_DETECT_CONFIG6 0x0d8 +#define QPHY_V6_PCS_REFGEN_REQ_CONFIG1 0x0dc +#define QPHY_V6_PCS_RX_SIGDET_LVL 0x188 +#define QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_L 0x190 +#define QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_H 0x194 +#define QPHY_V6_PCS_RATE_SLEW_CNTRL1 0x198 +#define QPHY_V6_PCS_CDR_RESET_TIME 0x1b0 +#define QPHY_V6_PCS_ALIGN_DETECT_CONFIG1 0x1c0 +#define QPHY_V6_PCS_ALIGN_DETECT_CONFIG2 0x1c4 +#define QPHY_V6_PCS_PCS_TX_RX_CONFIG 0x1d0 +#define QPHY_V6_PCS_EQ_CONFIG1 0x1dc +#define QPHY_V6_PCS_EQ_CONFIG2 0x1e0 +#define QPHY_V6_PCS_EQ_CONFIG5 0x1ec + +#endif diff --git a/drivers/phy/qcom/phy-qcom-qmp-pcs-v6_20.h b/drivers/phy/qcom/phy-qcom-qmp-pcs-v6_20.h new file mode 100644 index 00000000000..4d9615cc038 --- /dev/null +++ b/drivers/phy/qcom/phy-qcom-qmp-pcs-v6_20.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef QCOM_PHY_QMP_PCS_V6_20_H_ +#define QCOM_PHY_QMP_PCS_V6_20_H_ + +/* Only for QMP V6_20 PHY - USB/PCIe PCS registers */ +#define QPHY_V6_20_PCS_G12S1_TXDEEMPH_M6DB 0x170 +#define QPHY_V6_20_PCS_G3S2_PRE_GAIN 0x178 +#define QPHY_V6_20_PCS_RX_SIGDET_LVL 0x190 +#define QPHY_V6_20_PCS_COM_ELECIDLE_DLY_SEL 0x1b8 +#define QPHY_V6_20_PCS_TX_RX_CONFIG1 0x1dc +#define QPHY_V6_20_PCS_TX_RX_CONFIG2 0x1e0 +#define QPHY_V6_20_PCS_EQ_CONFIG4 0x1f8 +#define QPHY_V6_20_PCS_EQ_CONFIG5 0x1fc + +#endif diff --git a/drivers/phy/qcom/phy-qcom-qmp-qserdes-com-v5.h b/drivers/phy/qcom/phy-qcom-qmp-qserdes-com-v5.h new file mode 100644 index 00000000000..c8afdf7bc1e --- /dev/null +++ b/drivers/phy/qcom/phy-qcom-qmp-qserdes-com-v5.h @@ -0,0 +1,124 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_QSERDES_COM_V5_H_ +#define QCOM_PHY_QMP_QSERDES_COM_V5_H_ + +/* Only for QMP V5 PHY - QSERDES COM registers */ +#define QSERDES_V5_COM_ATB_SEL1 0x000 +#define QSERDES_V5_COM_ATB_SEL2 0x004 +#define QSERDES_V5_COM_FREQ_UPDATE 0x008 +#define QSERDES_V5_COM_BG_TIMER 0x00c +#define QSERDES_V5_COM_SSC_EN_CENTER 0x010 +#define QSERDES_V5_COM_SSC_ADJ_PER1 0x014 +#define QSERDES_V5_COM_SSC_ADJ_PER2 0x018 +#define QSERDES_V5_COM_SSC_PER1 0x01c +#define QSERDES_V5_COM_SSC_PER2 0x020 +#define QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0 0x024 +#define QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0 0x028 +#define QSERDES_V5_COM_SSC_STEP_SIZE3_MODE0 0x02c +#define QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1 0x030 +#define QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1 0x034 +#define QSERDES_V5_COM_SSC_STEP_SIZE3_MODE1 0x038 +#define QSERDES_V5_COM_POST_DIV 0x03c +#define QSERDES_V5_COM_POST_DIV_MUX 0x040 +#define QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN 0x044 +#define QSERDES_V5_COM_CLK_ENABLE1 0x048 +#define QSERDES_V5_COM_SYS_CLK_CTRL 0x04c +#define QSERDES_V5_COM_SYSCLK_BUF_ENABLE 0x050 +#define QSERDES_V5_COM_PLL_EN 0x054 +#define QSERDES_V5_COM_PLL_IVCO 0x058 +#define QSERDES_V5_COM_CMN_IETRIM 0x05c +#define QSERDES_V5_COM_CMN_IPTRIM 0x060 +#define QSERDES_V5_COM_EP_CLOCK_DETECT_CTRL 0x064 +#define QSERDES_V5_COM_SYSCLK_DET_COMP_STATUS 0x068 +#define QSERDES_V5_COM_CLK_EP_DIV_MODE0 0x06c +#define QSERDES_V5_COM_CLK_EP_DIV_MODE1 0x070 +#define QSERDES_V5_COM_CP_CTRL_MODE0 0x074 +#define QSERDES_V5_COM_CP_CTRL_MODE1 0x078 +#define QSERDES_V5_COM_PLL_RCTRL_MODE0 0x07c +#define QSERDES_V5_COM_PLL_RCTRL_MODE1 0x080 +#define QSERDES_V5_COM_PLL_CCTRL_MODE0 0x084 +#define QSERDES_V5_COM_PLL_CCTRL_MODE1 0x088 +#define QSERDES_V5_COM_PLL_CNTRL 0x08c +#define QSERDES_V5_COM_BIAS_EN_CTRL_BY_PSM 0x090 +#define QSERDES_V5_COM_SYSCLK_EN_SEL 0x094 +#define QSERDES_V5_COM_CML_SYSCLK_SEL 0x098 +#define QSERDES_V5_COM_RESETSM_CNTRL 0x09c +#define QSERDES_V5_COM_RESETSM_CNTRL2 0x0a0 +#define QSERDES_V5_COM_LOCK_CMP_EN 0x0a4 +#define QSERDES_V5_COM_LOCK_CMP_CFG 0x0a8 +#define QSERDES_V5_COM_LOCK_CMP1_MODE0 0x0ac +#define QSERDES_V5_COM_LOCK_CMP2_MODE0 0x0b0 +#define QSERDES_V5_COM_LOCK_CMP1_MODE1 0x0b4 +#define QSERDES_V5_COM_LOCK_CMP2_MODE1 0x0b8 +#define QSERDES_V5_COM_DEC_START_MODE0 0x0bc +#define QSERDES_V5_COM_DEC_START_MSB_MODE0 0x0c0 +#define QSERDES_V5_COM_DEC_START_MODE1 0x0c4 +#define QSERDES_V5_COM_DEC_START_MSB_MODE1 0x0c8 +#define QSERDES_V5_COM_DIV_FRAC_START1_MODE0 0x0cc +#define QSERDES_V5_COM_DIV_FRAC_START2_MODE0 0x0d0 +#define QSERDES_V5_COM_DIV_FRAC_START3_MODE0 0x0d4 +#define QSERDES_V5_COM_DIV_FRAC_START1_MODE1 0x0d8 +#define QSERDES_V5_COM_DIV_FRAC_START2_MODE1 0x0dc +#define QSERDES_V5_COM_DIV_FRAC_START3_MODE1 0x0e0 +#define QSERDES_V5_COM_INTEGLOOP_INITVAL 0x0e4 +#define QSERDES_V5_COM_INTEGLOOP_EN 0x0e8 +#define QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0 0x0ec +#define QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE0 0x0f0 +#define QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1 0x0f4 +#define QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE1 0x0f8 +#define QSERDES_V5_COM_INTEGLOOP_P_PATH_GAIN0 0x0fc +#define QSERDES_V5_COM_INTEGLOOP_P_PATH_GAIN1 0x100 +#define QSERDES_V5_COM_VCOCAL_DEADMAN_CTRL 0x104 +#define QSERDES_V5_COM_VCO_TUNE_CTRL 0x108 +#define QSERDES_V5_COM_VCO_TUNE_MAP 0x10c +#define QSERDES_V5_COM_VCO_TUNE1_MODE0 0x110 +#define QSERDES_V5_COM_VCO_TUNE2_MODE0 0x114 +#define QSERDES_V5_COM_VCO_TUNE1_MODE1 0x118 +#define QSERDES_V5_COM_VCO_TUNE2_MODE1 0x11c +#define QSERDES_V5_COM_VCO_TUNE_INITVAL1 0x120 +#define QSERDES_V5_COM_VCO_TUNE_INITVAL2 0x124 +#define QSERDES_V5_COM_VCO_TUNE_MINVAL1 0x128 +#define QSERDES_V5_COM_VCO_TUNE_MINVAL2 0x12c +#define QSERDES_V5_COM_VCO_TUNE_MAXVAL1 0x130 +#define QSERDES_V5_COM_VCO_TUNE_MAXVAL2 0x134 +#define QSERDES_V5_COM_VCO_TUNE_TIMER1 0x138 +#define QSERDES_V5_COM_VCO_TUNE_TIMER2 0x13c +#define QSERDES_V5_COM_CMN_STATUS 0x140 +#define QSERDES_V5_COM_RESET_SM_STATUS 0x144 +#define QSERDES_V5_COM_RESTRIM_CODE_STATUS 0x148 +#define QSERDES_V5_COM_PLLCAL_CODE1_STATUS 0x14c +#define QSERDES_V5_COM_PLLCAL_CODE2_STATUS 0x150 +#define QSERDES_V5_COM_CLK_SELECT 0x154 +#define QSERDES_V5_COM_HSCLK_SEL 0x158 +#define QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL 0x15c +#define QSERDES_V5_COM_INTEGLOOP_BINCODE_STATUS 0x160 +#define QSERDES_V5_COM_PLL_ANALOG 0x164 +#define QSERDES_V5_COM_CORECLK_DIV_MODE0 0x168 +#define QSERDES_V5_COM_CORECLK_DIV_MODE1 0x16c +#define QSERDES_V5_COM_SW_RESET 0x170 +#define QSERDES_V5_COM_CORE_CLK_EN 0x174 +#define QSERDES_V5_COM_C_READY_STATUS 0x178 +#define QSERDES_V5_COM_CMN_CONFIG 0x17c +#define QSERDES_V5_COM_CMN_RATE_OVERRIDE 0x180 +#define QSERDES_V5_COM_SVS_MODE_CLK_SEL 0x184 +#define QSERDES_V5_COM_DEBUG_BUS0 0x188 +#define QSERDES_V5_COM_DEBUG_BUS1 0x18c +#define QSERDES_V5_COM_DEBUG_BUS2 0x190 +#define QSERDES_V5_COM_DEBUG_BUS3 0x194 +#define QSERDES_V5_COM_DEBUG_BUS_SEL 0x198 +#define QSERDES_V5_COM_CMN_MISC1 0x19c +#define QSERDES_V5_COM_CMN_MODE 0x1a0 +#define QSERDES_V5_COM_CMN_MODE_CONTD 0x1a4 +#define QSERDES_V5_COM_VCO_DC_LEVEL_CTRL 0x1a8 +#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac +#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0 +#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4 +#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8 +#define QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc +#define QSERDES_V5_COM_RESERVED_1 0x1c0 + +#endif diff --git a/drivers/phy/qcom/phy-qcom-qmp-qserdes-ln-shrd-v6.h b/drivers/phy/qcom/phy-qcom-qmp-qserdes-ln-shrd-v6.h new file mode 100644 index 00000000000..86d7d796d5d --- /dev/null +++ b/drivers/phy/qcom/phy-qcom-qmp-qserdes-ln-shrd-v6.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef QCOM_PHY_QMP_QSERDES_LN_SHRD_V6_H_ +#define QCOM_PHY_QMP_QSERDES_LN_SHRD_V6_H_ + +#define QSERDES_V6_LN_SHRD_RXCLK_DIV2_CTRL 0xa0 +#define QSERDES_V6_LN_SHRD_RX_Q_EN_RATES 0xb0 +#define QSERDES_V6_LN_SHRD_DFE_DAC_ENABLE1 0xb4 +#define QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1 0xc4 +#define QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2 0xc8 +#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B0 0xd4 +#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B1 0xd8 +#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B2 0xdc +#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B3 0xe0 +#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B4 0xe4 +#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B5 0xe8 +#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B6 0xec +#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE210 0xf0 +#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE3 0xf4 +#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE210 0xf8 +#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE3 0xfc +#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE210 0x100 +#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE3 0x104 +#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH4_RATE3 0x10c +#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH5_RATE3 0x114 +#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH6_RATE3 0x11c +#define QSERDES_V6_LN_SHRD_RX_SUMMER_CAL_SPD_MODE 0x128 + +#endif diff --git a/drivers/phy/qcom/phy-qcom-qmp-qserdes-txrx-v5.h b/drivers/phy/qcom/phy-qcom-qmp-qserdes-txrx-v5.h new file mode 100644 index 00000000000..fe8f3e330d0 --- /dev/null +++ b/drivers/phy/qcom/phy-qcom-qmp-qserdes-txrx-v5.h @@ -0,0 +1,231 @@ + +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_QSERDES_TXRX_V5_H_ +#define QCOM_PHY_QMP_QSERDES_TXRX_V5_H_ + +/* Only for QMP V5 PHY - TX registers */ +#define QSERDES_V5_TX_BIST_MODE_LANENO 0x000 +#define QSERDES_V5_TX_BIST_INVERT 0x004 +#define QSERDES_V5_TX_CLKBUF_ENABLE 0x008 +#define QSERDES_V5_TX_TX_EMP_POST1_LVL 0x00c +#define QSERDES_V5_TX_TX_IDLE_LVL_LARGE_AMP 0x010 +#define QSERDES_V5_TX_TX_DRV_LVL 0x014 +#define QSERDES_V5_TX_TX_DRV_LVL_OFFSET 0x018 +#define QSERDES_V5_TX_RESET_TSYNC_EN 0x01c +#define QSERDES_V5_TX_PRE_STALL_LDO_BOOST_EN 0x020 +#define QSERDES_V5_TX_TX_BAND 0x024 +#define QSERDES_V5_TX_SLEW_CNTL 0x028 +#define QSERDES_V5_TX_INTERFACE_SELECT 0x02c +#define QSERDES_V5_TX_LPB_EN 0x030 +#define QSERDES_V5_TX_RES_CODE_LANE_TX 0x034 +#define QSERDES_V5_TX_RES_CODE_LANE_RX 0x038 +#define QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX 0x03c +#define QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX 0x040 +#define QSERDES_V5_TX_PERL_LENGTH1 0x044 +#define QSERDES_V5_TX_PERL_LENGTH2 0x048 +#define QSERDES_V5_TX_SERDES_BYP_EN_OUT 0x04c +#define QSERDES_V5_TX_DEBUG_BUS_SEL 0x050 +#define QSERDES_V5_TX_TRANSCEIVER_BIAS_EN 0x054 +#define QSERDES_V5_TX_HIGHZ_DRVR_EN 0x058 +#define QSERDES_V5_TX_TX_POL_INV 0x05c +#define QSERDES_V5_TX_PARRATE_REC_DETECT_IDLE_EN 0x060 +#define QSERDES_V5_TX_BIST_PATTERN1 0x064 +#define QSERDES_V5_TX_BIST_PATTERN2 0x068 +#define QSERDES_V5_TX_BIST_PATTERN3 0x06c +#define QSERDES_V5_TX_BIST_PATTERN4 0x070 +#define QSERDES_V5_TX_BIST_PATTERN5 0x074 +#define QSERDES_V5_TX_BIST_PATTERN6 0x078 +#define QSERDES_V5_TX_BIST_PATTERN7 0x07c +#define QSERDES_V5_TX_BIST_PATTERN8 0x080 +#define QSERDES_V5_TX_LANE_MODE_1 0x084 +#define QSERDES_V5_TX_LANE_MODE_2 0x088 +#define QSERDES_V5_TX_LANE_MODE_3 0x08c +#define QSERDES_V5_TX_LANE_MODE_4 0x090 +#define QSERDES_V5_TX_LANE_MODE_5 0x094 +#define QSERDES_V5_TX_ATB_SEL1 0x098 +#define QSERDES_V5_TX_ATB_SEL2 0x09c +#define QSERDES_V5_TX_RCV_DETECT_LVL 0x0a0 +#define QSERDES_V5_TX_RCV_DETECT_LVL_2 0x0a4 +#define QSERDES_V5_TX_PRBS_SEED1 0x0a8 +#define QSERDES_V5_TX_PRBS_SEED2 0x0ac +#define QSERDES_V5_TX_PRBS_SEED3 0x0b0 +#define QSERDES_V5_TX_PRBS_SEED4 0x0b4 +#define QSERDES_V5_TX_RESET_GEN 0x0b8 +#define QSERDES_V5_TX_RESET_GEN_MUXES 0x0bc +#define QSERDES_V5_TX_TRAN_DRVR_EMP_EN 0x0c0 +#define QSERDES_V5_TX_TX_INTERFACE_MODE 0x0c4 +#define QSERDES_V5_TX_VMODE_CTRL1 0x0c8 +#define QSERDES_V5_TX_ALOG_OBSV_BUS_CTRL_1 0x0cc +#define QSERDES_V5_TX_BIST_STATUS 0x0d0 +#define QSERDES_V5_TX_BIST_ERROR_COUNT1 0x0d4 +#define QSERDES_V5_TX_BIST_ERROR_COUNT2 0x0d8 +#define QSERDES_V5_TX_ALOG_OBSV_BUS_STATUS_1 0x0dc +#define QSERDES_V5_TX_LANE_DIG_CONFIG 0x0e0 +#define QSERDES_V5_TX_PI_QEC_CTRL 0x0e4 +#define QSERDES_V5_TX_PRE_EMPH 0x0e8 +#define QSERDES_V5_TX_SW_RESET 0x0ec +#define QSERDES_V5_TX_DCC_OFFSET 0x0f0 +#define QSERDES_V5_TX_DCC_CMUX_POSTCAL_OFFSET 0x0f4 +#define QSERDES_V5_TX_DCC_CMUX_CAL_CTRL1 0x0f8 +#define QSERDES_V5_TX_DCC_CMUX_CAL_CTRL2 0x0fc +#define QSERDES_V5_TX_DIG_BKUP_CTRL 0x100 +#define QSERDES_V5_TX_DEBUG_BUS0 0x104 +#define QSERDES_V5_TX_DEBUG_BUS1 0x108 +#define QSERDES_V5_TX_DEBUG_BUS2 0x10c +#define QSERDES_V5_TX_DEBUG_BUS3 0x110 +#define QSERDES_V5_TX_READ_EQCODE 0x114 +#define QSERDES_V5_TX_READ_OFFSETCODE 0x118 +#define QSERDES_V5_TX_IA_ERROR_COUNTER_LOW 0x11c +#define QSERDES_V5_TX_IA_ERROR_COUNTER_HIGH 0x120 +#define QSERDES_V5_TX_VGA_READ_CODE 0x124 +#define QSERDES_V5_TX_VTH_READ_CODE 0x128 +#define QSERDES_V5_TX_DFE_TAP1_READ_CODE 0x12c +#define QSERDES_V5_TX_DFE_TAP2_READ_CODE 0x130 +#define QSERDES_V5_TX_IDAC_STATUS_I 0x134 +#define QSERDES_V5_TX_IDAC_STATUS_IBAR 0x138 +#define QSERDES_V5_TX_IDAC_STATUS_Q 0x13c +#define QSERDES_V5_TX_IDAC_STATUS_QBAR 0x140 +#define QSERDES_V5_TX_IDAC_STATUS_A 0x144 +#define QSERDES_V5_TX_IDAC_STATUS_ABAR 0x148 +#define QSERDES_V5_TX_IDAC_STATUS_SM_ON 0x14c +#define QSERDES_V5_TX_IDAC_STATUS_CAL_DONE 0x150 +#define QSERDES_V5_TX_IDAC_STATUS_SIGNERROR 0x154 +#define QSERDES_V5_TX_DCC_CAL_STATUS 0x158 +#define QSERDES_V5_TX_DCC_READ_CODE_STATUS 0x15c + +/* Only for QMP V5 PHY - RX registers */ +#define QSERDES_V5_RX_UCDR_FO_GAIN_HALF 0x000 +#define QSERDES_V5_RX_UCDR_FO_GAIN_QUARTER 0x004 +#define QSERDES_V5_RX_UCDR_FO_GAIN 0x008 +#define QSERDES_V5_RX_UCDR_SO_GAIN_HALF 0x00c +#define QSERDES_V5_RX_UCDR_SO_GAIN_QUARTER 0x010 +#define QSERDES_V5_RX_UCDR_SO_GAIN 0x014 +#define QSERDES_V5_RX_UCDR_SVS_FO_GAIN_HALF 0x018 +#define QSERDES_V5_RX_UCDR_SVS_FO_GAIN_QUARTER 0x01c +#define QSERDES_V5_RX_UCDR_SVS_FO_GAIN 0x020 +#define QSERDES_V5_RX_UCDR_SVS_SO_GAIN_HALF 0x024 +#define QSERDES_V5_RX_UCDR_SVS_SO_GAIN_QUARTER 0x028 +#define QSERDES_V5_RX_UCDR_SVS_SO_GAIN 0x02c +#define QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN 0x030 +#define QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034 +#define QSERDES_V5_RX_UCDR_FO_TO_SO_DELAY 0x038 +#define QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c +#define QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040 +#define QSERDES_V5_RX_UCDR_PI_CONTROLS 0x044 +#define QSERDES_V5_RX_UCDR_PI_CTRL2 0x048 +#define QSERDES_V5_RX_UCDR_SB2_THRESH1 0x04c +#define QSERDES_V5_RX_UCDR_SB2_THRESH2 0x050 +#define QSERDES_V5_RX_UCDR_SB2_GAIN1 0x054 +#define QSERDES_V5_RX_UCDR_SB2_GAIN2 0x058 +#define QSERDES_V5_RX_AUX_CONTROL 0x05c +#define QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE 0x060 +#define QSERDES_V5_RX_RCLK_AUXDATA_SEL 0x064 +#define QSERDES_V5_RX_AC_JTAG_ENABLE 0x068 +#define QSERDES_V5_RX_AC_JTAG_INITP 0x06c +#define QSERDES_V5_RX_AC_JTAG_INITN 0x070 +#define QSERDES_V5_RX_AC_JTAG_LVL 0x074 +#define QSERDES_V5_RX_AC_JTAG_MODE 0x078 +#define QSERDES_V5_RX_AC_JTAG_RESET 0x07c +#define QSERDES_V5_RX_RX_TERM_BW 0x080 +#define QSERDES_V5_RX_RX_RCVR_IQ_EN 0x084 +#define QSERDES_V5_RX_RX_IDAC_I_DC_OFFSETS 0x088 +#define QSERDES_V5_RX_RX_IDAC_IBAR_DC_OFFSETS 0x08c +#define QSERDES_V5_RX_RX_IDAC_Q_DC_OFFSETS 0x090 +#define QSERDES_V5_RX_RX_IDAC_QBAR_DC_OFFSETS 0x094 +#define QSERDES_V5_RX_RX_IDAC_A_DC_OFFSETS 0x098 +#define QSERDES_V5_RX_RX_IDAC_ABAR_DC_OFFSETS 0x09c +#define QSERDES_V5_RX_RX_IDAC_EN 0x0a0 +#define QSERDES_V5_RX_RX_IDAC_ENABLES 0x0a4 +#define QSERDES_V5_RX_RX_IDAC_SIGN 0x0a8 +#define QSERDES_V5_RX_RX_HIGHZ_HIGHRATE 0x0ac +#define QSERDES_V5_RX_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET 0x0b0 +#define QSERDES_V5_RX_DFE_1 0x0b4 +#define QSERDES_V5_RX_DFE_2 0x0b8 +#define QSERDES_V5_RX_DFE_3 0x0bc +#define QSERDES_V5_RX_DFE_4 0x0c0 +#define QSERDES_V5_RX_TX_ADAPT_PRE_THRESH1 0x0c4 +#define QSERDES_V5_RX_TX_ADAPT_PRE_THRESH2 0x0c8 +#define QSERDES_V5_RX_TX_ADAPT_POST_THRESH 0x0cc +#define QSERDES_V5_RX_TX_ADAPT_MAIN_THRESH 0x0d0 +#define QSERDES_V5_RX_VGA_CAL_CNTRL1 0x0d4 +#define QSERDES_V5_RX_VGA_CAL_CNTRL2 0x0d8 +#define QSERDES_V5_RX_GM_CAL 0x0dc +#define QSERDES_V5_RX_RX_VGA_GAIN2_LSB 0x0e0 +#define QSERDES_V5_RX_RX_VGA_GAIN2_MSB 0x0e4 +#define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1 0x0e8 +#define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2 0x0ec +#define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3 0x0f0 +#define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4 0x0f4 +#define QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW 0x0f8 +#define QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH 0x0fc +#define QSERDES_V5_RX_RX_IDAC_MEASURE_TIME 0x100 +#define QSERDES_V5_RX_RX_IDAC_ACCUMULATOR 0x104 +#define QSERDES_V5_RX_RX_EQ_OFFSET_LSB 0x108 +#define QSERDES_V5_RX_RX_EQ_OFFSET_MSB 0x10c +#define QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110 +#define QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x114 +#define QSERDES_V5_RX_SIGDET_ENABLES 0x118 +#define QSERDES_V5_RX_SIGDET_CNTRL 0x11c +#define QSERDES_V5_RX_SIGDET_LVL 0x120 +#define QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL 0x124 +#define QSERDES_V5_RX_RX_BAND 0x128 +#define QSERDES_V5_RX_CDR_FREEZE_UP_DN 0x12c +#define QSERDES_V5_RX_CDR_RESET_OVERRIDE 0x130 +#define QSERDES_V5_RX_RX_INTERFACE_MODE 0x134 +#define QSERDES_V5_RX_JITTER_GEN_MODE 0x138 +#define QSERDES_V5_RX_SJ_AMP1 0x13c +#define QSERDES_V5_RX_SJ_AMP2 0x140 +#define QSERDES_V5_RX_SJ_PER1 0x144 +#define QSERDES_V5_RX_SJ_PER2 0x148 +#define QSERDES_V5_RX_PPM_OFFSET1 0x14c +#define QSERDES_V5_RX_PPM_OFFSET2 0x150 +#define QSERDES_V5_RX_SIGN_PPM_PERIOD1 0x154 +#define QSERDES_V5_RX_SIGN_PPM_PERIOD2 0x158 +#define QSERDES_V5_RX_RX_MODE_00_LOW 0x15c +#define QSERDES_V5_RX_RX_MODE_00_HIGH 0x160 +#define QSERDES_V5_RX_RX_MODE_00_HIGH2 0x164 +#define QSERDES_V5_RX_RX_MODE_00_HIGH3 0x168 +#define QSERDES_V5_RX_RX_MODE_00_HIGH4 0x16c +#define QSERDES_V5_RX_RX_MODE_01_LOW 0x170 +#define QSERDES_V5_RX_RX_MODE_01_HIGH 0x174 +#define QSERDES_V5_RX_RX_MODE_01_HIGH2 0x178 +#define QSERDES_V5_RX_RX_MODE_01_HIGH3 0x17c +#define QSERDES_V5_RX_RX_MODE_01_HIGH4 0x180 +#define QSERDES_V5_RX_RX_MODE_10_LOW 0x184 +#define QSERDES_V5_RX_RX_MODE_10_HIGH 0x188 +#define QSERDES_V5_RX_RX_MODE_10_HIGH2 0x18c +#define QSERDES_V5_RX_RX_MODE_10_HIGH3 0x190 +#define QSERDES_V5_RX_RX_MODE_10_HIGH4 0x194 +#define QSERDES_V5_RX_PHPRE_CTRL 0x198 +#define QSERDES_V5_RX_PHPRE_INITVAL 0x19c +#define QSERDES_V5_RX_DFE_EN_TIMER 0x1a0 +#define QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET 0x1a4 +#define QSERDES_V5_RX_DCC_CTRL1 0x1a8 +#define QSERDES_V5_RX_DCC_CTRL2 0x1ac +#define QSERDES_V5_RX_VTH_CODE 0x1b0 +#define QSERDES_V5_RX_VTH_MIN_THRESH 0x1b4 +#define QSERDES_V5_RX_VTH_MAX_THRESH 0x1b8 +#define QSERDES_V5_RX_ALOG_OBSV_BUS_CTRL_1 0x1bc +#define QSERDES_V5_RX_PI_CTRL1 0x1c0 +#define QSERDES_V5_RX_PI_CTRL2 0x1c4 +#define QSERDES_V5_RX_PI_QUAD 0x1c8 +#define QSERDES_V5_RX_IDATA1 0x1cc +#define QSERDES_V5_RX_IDATA2 0x1d0 +#define QSERDES_V5_RX_AUX_DATA1 0x1d4 +#define QSERDES_V5_RX_AUX_DATA2 0x1d8 +#define QSERDES_V5_RX_AC_JTAG_OUTP 0x1dc +#define QSERDES_V5_RX_AC_JTAG_OUTN 0x1e0 +#define QSERDES_V5_RX_RX_SIGDET 0x1e4 +#define QSERDES_V5_RX_ALOG_OBSV_BUS_STATUS_1 0x1e8 + +/* Only for QMP V5 UFS ? */ +#define QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0x178 +#define QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0x17c +#define QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0x180 +#define QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0x184 + +#endif diff --git a/drivers/phy/qcom/phy-qcom-qmp-qserdes-txrx-v6.h b/drivers/phy/qcom/phy-qcom-qmp-qserdes-txrx-v6.h new file mode 100644 index 00000000000..23ffcfae9ef --- /dev/null +++ b/drivers/phy/qcom/phy-qcom-qmp-qserdes-txrx-v6.h @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef QCOM_PHY_QMP_QSERDES_TXRX_USB_V6_H_ +#define QCOM_PHY_QMP_QSERDES_TXRX_USB_V6_H_ + +#define QSERDES_V6_TX_CLKBUF_ENABLE 0x08 +#define QSERDES_V6_TX_TX_EMP_POST1_LVL 0x0c +#define QSERDES_V6_TX_TX_DRV_LVL 0x14 +#define QSERDES_V6_TX_RESET_TSYNC_EN 0x1c +#define QSERDES_V6_TX_PRE_STALL_LDO_BOOST_EN 0x20 +#define QSERDES_V6_TX_TX_BAND 0x24 +#define QSERDES_V6_TX_INTERFACE_SELECT 0x2c +#define QSERDES_V6_TX_RES_CODE_LANE_TX 0x34 +#define QSERDES_V6_TX_RES_CODE_LANE_RX 0x38 +#define QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX 0x3c +#define QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX 0x40 +#define QSERDES_V6_TX_TRANSCEIVER_BIAS_EN 0x54 +#define QSERDES_V6_TX_HIGHZ_DRVR_EN 0x58 +#define QSERDES_V6_TX_TX_POL_INV 0x5c +#define QSERDES_V6_TX_PARRATE_REC_DETECT_IDLE_EN 0x60 +#define QSERDES_V6_TX_BIST_PATTERN7 0x7c +#define QSERDES_V6_TX_LANE_MODE_1 0x84 +#define QSERDES_V6_TX_LANE_MODE_2 0x88 +#define QSERDES_V6_TX_LANE_MODE_3 0x8c +#define QSERDES_V6_TX_LANE_MODE_4 0x90 +#define QSERDES_V6_TX_LANE_MODE_5 0x94 +#define QSERDES_V6_TX_RCV_DETECT_LVL_2 0xa4 +#define QSERDES_V6_TX_TRAN_DRVR_EMP_EN 0xc0 +#define QSERDES_V6_TX_TX_INTERFACE_MODE 0xc4 +#define QSERDES_V6_TX_VMODE_CTRL1 0xc8 +#define QSERDES_V6_TX_PI_QEC_CTRL 0xe4 + +#define QSERDES_V6_RX_UCDR_FO_GAIN 0x08 +#define QSERDES_V6_RX_UCDR_SO_GAIN 0x14 +#define QSERDES_V6_RX_UCDR_FASTLOCK_FO_GAIN 0x30 +#define QSERDES_V6_RX_UCDR_SO_SATURATION_AND_ENABLE 0x34 +#define QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_LOW 0x3c +#define QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_HIGH 0x40 +#define QSERDES_V6_RX_UCDR_PI_CONTROLS 0x44 +#define QSERDES_V6_RX_UCDR_SB2_THRESH1 0x4c +#define QSERDES_V6_RX_UCDR_SB2_THRESH2 0x50 +#define QSERDES_V6_RX_UCDR_SB2_GAIN1 0x54 +#define QSERDES_V6_RX_UCDR_SB2_GAIN2 0x58 +#define QSERDES_V6_RX_AUX_DATA_TCOARSE_TFINE 0x60 +#define QSERDES_V6_RX_TX_ADAPT_POST_THRESH 0xcc +#define QSERDES_V6_RX_VGA_CAL_CNTRL1 0xd4 +#define QSERDES_V6_RX_VGA_CAL_CNTRL2 0xd8 +#define QSERDES_V6_RX_GM_CAL 0xdc +#define QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL2 0xec +#define QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL3 0xf0 +#define QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL4 0xf4 +#define QSERDES_V6_RX_RX_IDAC_TSETTLE_LOW 0xf8 +#define QSERDES_V6_RX_RX_IDAC_TSETTLE_HIGH 0xfc +#define QSERDES_V6_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110 +#define QSERDES_V6_RX_SIDGET_ENABLES 0x118 +#define QSERDES_V6_RX_SIGDET_CNTRL 0x11c +#define QSERDES_V6_RX_SIGDET_DEGLITCH_CNTRL 0x124 +#define QSERDES_V6_RX_RX_MODE_00_LOW 0x15c +#define QSERDES_V6_RX_RX_MODE_00_HIGH 0x160 +#define QSERDES_V6_RX_RX_MODE_00_HIGH2 0x164 +#define QSERDES_V6_RX_RX_MODE_00_HIGH3 0x168 +#define QSERDES_V6_RX_RX_MODE_00_HIGH4 0x16c +#define QSERDES_V6_RX_RX_MODE_01_LOW 0x170 +#define QSERDES_V6_RX_RX_MODE_01_HIGH 0x174 +#define QSERDES_V6_RX_RX_MODE_01_HIGH2 0x178 +#define QSERDES_V6_RX_RX_MODE_01_HIGH3 0x17c +#define QSERDES_V6_RX_RX_MODE_01_HIGH4 0x180 +#define QSERDES_V6_RX_RX_MODE_10_LOW 0x184 +#define QSERDES_V6_RX_RX_MODE_10_HIGH 0x188 +#define QSERDES_V6_RX_RX_MODE_10_HIGH2 0x18c +#define QSERDES_V6_RX_RX_MODE_10_HIGH3 0x190 +#define QSERDES_V6_RX_RX_MODE_10_HIGH4 0x194 +#define QSERDES_V6_RX_DFE_EN_TIMER 0x1a0 +#define QSERDES_V6_RX_DFE_CTLE_POST_CAL_OFFSET 0x1a4 +#define QSERDES_V6_RX_DCC_CTRL1 0x1a8 +#define QSERDES_V6_RX_VTH_CODE 0x1b0 +#define QSERDES_V6_RX_SIGDET_CAL_CTRL1 0x1e4 +#define QSERDES_V6_RX_SIGDET_CAL_TRIM 0x1f8 + +#endif diff --git a/drivers/phy/qcom/phy-qcom-qmp-qserdes-txrx-v6_20.h b/drivers/phy/qcom/phy-qcom-qmp-qserdes-txrx-v6_20.h new file mode 100644 index 00000000000..7bac5d5c6c3 --- /dev/null +++ b/drivers/phy/qcom/phy-qcom-qmp-qserdes-txrx-v6_20.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef QCOM_PHY_QMP_QSERDES_TXRX_PCIE_V6_20_H_ +#define QCOM_PHY_QMP_QSERDES_TXRX_PCIE_V6_20_H_ + +#define QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_TX 0x30 +#define QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_RX 0x34 +#define QSERDES_V6_20_TX_TRAN_DRVR_EMP_EN 0xac +#define QSERDES_V6_20_TX_LANE_MODE_1 0x78 +#define QSERDES_V6_20_TX_LANE_MODE_2 0x7c +#define QSERDES_V6_20_TX_LANE_MODE_3 0x80 + +#define QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2 0x08 +#define QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3 0x0c +#define QSERDES_V6_20_RX_UCDR_SO_GAIN_RATE_2 0x18 +#define QSERDES_V6_20_RX_UCDR_PI_CONTROLS 0x20 +#define QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3 0x34 +#define QSERDES_V6_20_RX_IVCM_CAL_CTRL2 0x9c +#define QSERDES_V6_20_RX_IVCM_POSTCAL_OFFSET 0xa0 +#define QSERDES_V6_20_RX_DFE_1 0xac +#define QSERDES_V6_20_RX_DFE_2 0xb0 +#define QSERDES_V6_20_RX_DFE_3 0xb4 +#define QSERDES_V6_20_RX_TX_ADPT_CTRL 0xd4 +#define QSERDES_V6_20_VGA_CAL_CNTRL1 0xe0 +#define QSERDES_V6_20_RX_VGA_CAL_MAN_VAL 0xe8 +#define QSERDES_V6_20_RX_GM_CAL 0x10c +#define QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4 0x120 +#define QSERDES_V6_20_RX_SIGDET_ENABLES 0x148 +#define QSERDES_V6_20_RX_PHPRE_CTRL 0x188 +#define QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET 0x194 +#define QSERDES_V6_20_RX_Q_PI_INTRINSIC_BIAS_RATE32 0x1dc +#define QSERDES_V6_20_RX_MODE_RATE2_B0 0x1f4 +#define QSERDES_V6_20_RX_MODE_RATE2_B1 0x1f8 +#define QSERDES_V6_20_RX_MODE_RATE2_B2 0x1fc +#define QSERDES_V6_20_RX_MODE_RATE2_B3 0x200 +#define QSERDES_V6_20_RX_MODE_RATE2_B4 0x204 +#define QSERDES_V6_20_RX_MODE_RATE2_B5 0x208 +#define QSERDES_V6_20_RX_MODE_RATE2_B6 0x20c +#define QSERDES_V6_20_RX_MODE_RATE3_B0 0x210 +#define QSERDES_V6_20_RX_MODE_RATE3_B1 0x214 +#define QSERDES_V6_20_RX_MODE_RATE3_B2 0x218 +#define QSERDES_V6_20_RX_MODE_RATE3_B3 0x21c +#define QSERDES_V6_20_RX_MODE_RATE3_B4 0x220 +#define QSERDES_V6_20_RX_MODE_RATE3_B5 0x224 +#define QSERDES_V6_20_RX_MODE_RATE3_B6 0x228 +#define QSERDES_V6_20_RX_BKUP_CTRL1 0x22c + +#endif diff --git a/drivers/phy/qcom/phy-qcom-qmp-ufs.c b/drivers/phy/qcom/phy-qcom-qmp-ufs.c index 5c90d60e7d1..449b9767778 100644 --- a/drivers/phy/qcom/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qcom/phy-qcom-qmp-ufs.c @@ -33,8 +33,10 @@ #include "phy-qcom-qmp-pcs-ufs-v6.h" #include "phy-qcom-qmp-qserdes-com-v4.h" +#include "phy-qcom-qmp-qserdes-com-v5.h" #include "phy-qcom-qmp-qserdes-com-v6.h" #include "phy-qcom-qmp-qserdes-txrx-v4.h" +#include "phy-qcom-qmp-qserdes-txrx-v5.h" #include "phy-qcom-qmp-qserdes-txrx-ufs-v6.h" /* QPHY_SW_RESET bit */ @@ -97,6 +99,13 @@ static const unsigned int ufsphy_v4_regs_layout[QPHY_LAYOUT_SIZE] = { [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL, }; +static const unsigned int ufsphy_v5_regs_layout[QPHY_LAYOUT_SIZE] = { + [QPHY_START_CTRL] = QPHY_V5_PCS_UFS_PHY_START, + [QPHY_PCS_READY_STATUS] = QPHY_V5_PCS_UFS_READY_STATUS, + [QPHY_SW_RESET] = QPHY_V5_PCS_UFS_SW_RESET, + [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_UFS_POWER_DOWN_CONTROL, +}; + static const unsigned int ufsphy_v6_regs_layout[QPHY_LAYOUT_SIZE] = { [QPHY_START_CTRL] = QPHY_V6_PCS_UFS_PHY_START, [QPHY_PCS_READY_STATUS] = QPHY_V6_PCS_UFS_READY_STATUS, @@ -458,6 +467,128 @@ static const struct qmp_ufs_init_tbl sm8650_ufsphy_rx[] = { QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL, 0x30), }; +static const struct qmp_ufs_init_tbl sm8350_ufsphy_serdes[] = { + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x19), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x98), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x65), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23), +}; + +static const struct qmp_ufs_init_tbl sm8350_ufsphy_hs_b_serdes[] = { + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06), +}; + +static const struct qmp_ufs_init_tbl sm8350_ufsphy_tx[] = { + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xf5), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c), +}; + +static const struct qmp_ufs_init_tbl sm8350_ufsphy_rx[] = { + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_BAND, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf1), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x1b), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x10), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x6d), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x6d), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xed), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3b), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x3c), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xe0), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xc8), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xc8), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x3b), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xb7), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_LOW, 0xe0), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH, 0xc8), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xc8), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3b), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xb7), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c), +}; + +static const struct qmp_ufs_init_tbl sm8350_ufsphy_pcs[] = { + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02), +}; + +static const struct qmp_ufs_init_tbl sm8350_ufsphy_g4_tx[] = { + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xe5), +}; + +static const struct qmp_ufs_init_tbl sm8350_ufsphy_g4_rx[] = { + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x81), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x6f), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x20), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbf), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xbf), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x2d), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x6d), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x6d), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xed), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0x3c), +}; + +static const struct qmp_ufs_init_tbl sm8350_ufsphy_g4_pcs[] = { + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a), +}; + static const struct qmp_ufs_init_tbl sm8650_ufsphy_pcs[] = { QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02), QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), @@ -690,6 +821,11 @@ static const char * const sdm845_ufs_phy_clk_l[] = { "ref", "ref_aux", }; +/* the primary usb3 phy on sm8250 doesn't have a ref clock */ +static const char * const sm8450_ufs_phy_clk_l[] = { + "qref", "ref", "ref_aux", +}; + /* list of regulators */ static const char * const qmp_ufs_vreg_l[] = { "vdda-phy", "vdda-pll", @@ -909,6 +1045,40 @@ static const struct qmp_ufs_cfg sc7280_ufsphy_cfg = { .regs = ufsphy_v4_regs_layout, }; +static const struct qmp_ufs_cfg sa8775p_ufsphy_cfg = { + .lanes = 2, + + .offsets = &qmp_ufs_offsets, + + .tbls = { + .serdes = sm8350_ufsphy_serdes, + .serdes_num = ARRAY_SIZE(sm8350_ufsphy_serdes), + .tx = sm8350_ufsphy_tx, + .tx_num = ARRAY_SIZE(sm8350_ufsphy_tx), + .rx = sm8350_ufsphy_rx, + .rx_num = ARRAY_SIZE(sm8350_ufsphy_rx), + .pcs = sm8350_ufsphy_pcs, + .pcs_num = ARRAY_SIZE(sm8350_ufsphy_pcs), + }, + .tbls_hs_b = { + .serdes = sm8350_ufsphy_hs_b_serdes, + .serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes), + }, + .tbls_hs_g4 = { + .tx = sm8350_ufsphy_g4_tx, + .tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx), + .rx = sm8350_ufsphy_g4_rx, + .rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx), + .pcs = sm8350_ufsphy_g4_pcs, + .pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs), + }, + .clk_list = sm8450_ufs_phy_clk_l, + .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l), + .vreg_list = qmp_ufs_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_ufs_vreg_l), + .regs = ufsphy_v5_regs_layout, +}; + static void qmp_ufs_configure_lane(void __iomem *base, const struct qmp_ufs_init_tbl tbl[], int num, @@ -1295,6 +1465,7 @@ static struct phy_ops qmp_ufs_ops = { }; static const struct udevice_id qmp_ufs_ids[] = { + { .compatible = "qcom,sa8775p-qmp-ufs-phy", .data = (ulong)&sa8775p_ufsphy_cfg, }, { .compatible = "qcom,sdm845-qmp-ufs-phy", .data = (ulong)&sdm845_ufsphy_cfg }, { .compatible = "qcom,sm8150-qmp-ufs-phy", .data = (ulong)&sm8150_ufsphy_cfg }, { .compatible = "qcom,sm8250-qmp-ufs-phy", .data = (ulong)&sm8250_ufsphy_cfg }, diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig index 34d23cece51..8b9180bd2aa 100644 --- a/drivers/pinctrl/mediatek/Kconfig +++ b/drivers/pinctrl/mediatek/Kconfig @@ -24,6 +24,10 @@ config PINCTRL_MT7986 bool "MT7986 SoC pinctrl driver" select PINCTRL_MTK +config PINCTRL_MT7987 + bool "MT7987 SoC pinctrl driver" + select PINCTRL_MTK + config PINCTRL_MT7988 bool "MT7988 SoC pinctrl driver" select PINCTRL_MTK diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile index de39d1ea436..b25e74e4e00 100644 --- a/drivers/pinctrl/mediatek/Makefile +++ b/drivers/pinctrl/mediatek/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o obj-$(CONFIG_PINCTRL_MT7981) += pinctrl-mt7981.o obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o +obj-$(CONFIG_PINCTRL_MT7987) += pinctrl-mt7987.o obj-$(CONFIG_PINCTRL_MT7988) += pinctrl-mt7988.o obj-$(CONFIG_PINCTRL_MT8512) += pinctrl-mt8512.o obj-$(CONFIG_PINCTRL_MT8516) += pinctrl-mt8516.o diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7981.c b/drivers/pinctrl/mediatek/pinctrl-mt7981.c index 047e37bc9cd..6b9769067b0 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7981.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c @@ -569,6 +569,11 @@ static const struct mtk_pin_desc mt7981_pins[] = { MT7981_TYPE1_PIN(56, "WF_HB10"), }; +/* List all groups consisting of these pins dedicated to the enablement of + * certain hardware block and the corresponding mode for all of the pins. + * The hardware probably has multiple combinations of these pinouts. + */ + /* WA_AICE */ static const int mt7981_wa_aice1_pins[] = { 0, 1, }; static const int mt7981_wa_aice1_funcs[] = { 2, 2, }; @@ -632,6 +637,9 @@ static const int mt7981_wo0_jtag_1_funcs[] = { 5, 5, 5, 5, 5, }; static const int mt7981_uart2_0_pins[] = { 4, 5, 6, 7, }; static const int mt7981_uart2_0_funcs[] = { 3, 3, 3, 3, }; +static const int mt7981_uart2_0_tx_rx_pins[] = { 4, 5, }; +static const int mt7981_uart2_0_tx_rx_funcs[] = { 3, 3, }; + /* GBE_LED0 */ static const int mt7981_gbe_led0_pins[] = { 8, }; static const int mt7981_gbe_led0_funcs[] = { 3, }; @@ -718,6 +726,17 @@ static const int mt7981_drv_vbus_pins[] = { 14, }; static const int mt7981_drv_vbus_funcs[] = { 1, }; /* EMMC */ +static const int mt7981_emmc_reset_pins[] = { 15, }; +static const int mt7981_emmc_reset_funcs[] = { 2, }; + +static const int mt7981_emmc_4_pins[] = { 16, 17, 18, 19, 24, 25, }; +static const int mt7981_emmc_4_funcs[] = { 2, 2, 2, 2, 2, 2, }; + +static const int mt7981_emmc_8_pins[] = { + 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, }; +static const int mt7981_emmc_8_funcs[] = { + 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; + static const int mt7981_emmc_45_pins[] = { 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, }; static const int mt7981_emmc_45_funcs[] = { @@ -754,6 +773,12 @@ static const int mt7981_uart1_0_funcs[] = { 4, 4, 4, 4, }; static const int mt7981_uart1_1_pins[] = { 26, 27, 28, 29, }; static const int mt7981_uart1_1_funcs[] = { 2, 2, 2, 2, }; +static const int mt7981_uart1_2_pins[] = { 9, 10, }; +static const int mt7981_uart1_2_funcs[] = { 2, 2, }; + +static const int mt7981_uart1_3_pins[] = { 26, 27, }; +static const int mt7981_uart1_3_funcs[] = { 2, 2, }; + /* UART2 */ static const int mt7981_uart2_1_pins[] = { 22, 23, 24, 25, }; static const int mt7981_uart2_1_funcs[] = { 3, 3, 3, 3, }; @@ -832,6 +857,8 @@ static const struct mtk_group_desc mt7981_groups[] = { PINCTRL_PIN_GROUP("wo0_jtag_0", mt7981_wo0_jtag_0), /* @GPIO(4,7) WM_JTAG(3) */ PINCTRL_PIN_GROUP("uart2_0", mt7981_uart2_0), + /* @GPIO(4,5) WM_JTAG(4) */ + PINCTRL_PIN_GROUP("uart2_0_tx_rx", mt7981_uart2_0_tx_rx), /* @GPIO(8) GBE_LED0(3) */ PINCTRL_PIN_GROUP("gbe_led0", mt7981_gbe_led0), /* @GPIO(4,6) PTA_EXT(4) */ @@ -844,7 +871,7 @@ static const struct mtk_group_desc mt7981_groups[] = { PINCTRL_PIN_GROUP("spi1_0", mt7981_spi1_0), /* @GPIO(6,7) I2C(5) */ PINCTRL_PIN_GROUP("i2c0_0", mt7981_i2c0_0), - /* @GPIO(8): DFD_NTRST(6) */ + /* @GPIO(0,1,4,5): DFD_NTRST(6) */ PINCTRL_PIN_GROUP("dfd_ntrst", mt7981_dfd_ntrst), /* @GPIO(9,10): WM_AICE(2) */ PINCTRL_PIN_GROUP("wm_aice1", mt7981_wm_aice1), @@ -870,6 +897,12 @@ static const struct mtk_group_desc mt7981_groups[] = { PINCTRL_PIN_GROUP("udi", mt7981_udi), /* @GPIO(14) DRV_VBUS(1) */ PINCTRL_PIN_GROUP("drv_vbus", mt7981_drv_vbus), + /* @GPIO(15): EMMC_RSTB(2) */ + PINCTRL_PIN_GROUP("emmc_reset", mt7981_emmc_reset), + /* @GPIO(16,17,18,19,24,25): EMMC_DATx, EMMC_CLK, EMMC_CMD */ + PINCTRL_PIN_GROUP("emmc_4", mt7981_emmc_4), + /* @GPIO(16,17,18,19,20,21,22,23,24,25): EMMC_DATx, EMMC_CLK, EMMC_CMD */ + PINCTRL_PIN_GROUP("emmc_8", mt7981_emmc_8), /* @GPIO(15,25): EMMC(2) */ PINCTRL_PIN_GROUP("emmc_45", mt7981_emmc_45), /* @GPIO(16,21): SNFI(3) */ @@ -888,8 +921,12 @@ static const struct mtk_group_desc mt7981_groups[] = { PINCTRL_PIN_GROUP("uart1_0", mt7981_uart1_0), /* @GPIO(26,29): UART1(2) */ PINCTRL_PIN_GROUP("uart1_1", mt7981_uart1_1), + /* @GPIO(9,10): UART1(2) */ + PINCTRL_PIN_GROUP("uart1_2", mt7981_uart1_2), + /* @GPIO(26,27): UART1(2) */ + PINCTRL_PIN_GROUP("uart1_3", mt7981_uart1_3), /* @GPIO(22,25): UART2(3) */ - PINCTRL_PIN_GROUP("uart2_0", mt7981_uart2_1), + PINCTRL_PIN_GROUP("uart2_1", mt7981_uart2_1), /* @GPIO(22,24) PTA_EXT(4) */ PINCTRL_PIN_GROUP("pta_ext_1", mt7981_pta_ext_1), /* @GPIO(20,21): WM_UART(4) */ @@ -964,9 +1001,10 @@ static const struct mtk_io_type_desc mt7981_io_type_desc[] = { */ static const char *const mt7981_wa_aice_groups[] = { "wa_aice1", "wa_aice2", "wm_aice1_1", "wa_aice3", "wm_aice1_2", }; -static const char *const mt7981_uart_groups[] = { "wm_uart_0", "uart2_0", - "net_wo0_uart_txd_0", "net_wo0_uart_txd_1", "net_wo0_uart_txd_2", - "uart1_0", "uart1_1", "uart2_0", "wm_aurt_1", "wm_aurt_2", "uart0", }; +static const char *const mt7981_uart_groups[] = { "net_wo0_uart_txd_0", + "net_wo0_uart_txd_1", "net_wo0_uart_txd_2", "uart0", "uart1_0", + "uart1_1", "uart1_2", "uart1_3", "uart2_0", "uart2_0_tx_rx", "uart2_1", + "wm_uart_0", "wm_aurt_1", "wm_aurt_2", }; static const char *const mt7981_dfd_groups[] = { "dfd", "dfd_ntrst", }; static const char *const mt7981_wdt_groups[] = { "watchdog", "watchdog1", }; static const char *const mt7981_pcie_groups[] = { "pcie_pereset", "pcie_clk", @@ -986,7 +1024,8 @@ static const char *const mt7981_i2c_groups[] = { "i2c0_0", "i2c0_1", static const char *const mt7981_pcm_groups[] = { "pcm", }; static const char *const mt7981_udi_groups[] = { "udi", }; static const char *const mt7981_usb_groups[] = { "drv_vbus", }; -static const char *const mt7981_flash_groups[] = { "emmc_45", "snfi", }; +static const char *const mt7981_flash_groups[] = { "emmc_reset", "emmc_4", + "emmc_8", "emmc_45", "snfi", }; static const char *const mt7981_ethernet_groups[] = { "smi_mdc_mdio", "gbe_ext_mdc_mdio", "wf0_mode1", "wf0_mode3", "mt7531_int", }; static const char *const mt7981_ant_groups[] = { "ant_sel", }; @@ -1012,8 +1051,9 @@ static const struct mtk_function_desc mt7981_functions[] = { }; static const char *const mt7981_pinctrl_register_base_names[] = { - "gpio_base", "iocfg_rt_base", "iocfg_rm_base", "iocfg_rb_base", - "iocfg_lb_base", "iocfg_bl_base", "iocfg_tm_base", "iocfg_tl_base", + "gpio", "iocfg_rt", "iocfg_rm", "iocfg_rb", + "iocfg_lb", "iocfg_bl", "iocfg_tm", "iocfg_tl", + "eint", }; static const struct mtk_pinctrl_soc mt7981_data = { diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7987.c b/drivers/pinctrl/mediatek/pinctrl-mt7987.c new file mode 100644 index 00000000000..db672d26798 --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mt7987.c @@ -0,0 +1,736 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024 MediaTek Inc. + * Author: Tim.Kuo <tim.kuo@mediatek.com> + */ + +#include <dm.h> +#include "pinctrl-mtk-common.h" + +enum MT7987_PINCTRL_REG_PAGE { + GPIO_BASE, + IOCFG_RB_BASE, + IOCFG_LB_BASE, + IOCFG_RT1_BASE, + IOCFG_RT2_BASE, + IOCFG_TL_BASE, +}; + +/* + * IO_TYPE_GRP0 / IO_TYPE_GRP1 + * MT7987 pins can be divided into two groups: + * - PUPD_R0_R1 + * - PU/PD + * Here, we divide pins with PU/PD to be IO_TYPE_GRP0 and those with PUPD_R0_R1 + * to be IO_TYPE_GRP1. + * - PUPD_R0_R1 : IO_TYPE_GRP0 + * - PU/PD : IO_TYPE_GRP1 + * DRV_GRP4 + * For MT7987, thr driving of pins can start from 2mA and increase by 2mA + * increments up to 16mA. + */ +#define MT7987_TYPE0_PIN(_number, _name) \ + MTK_TYPED_PIN(_number, _name, DRV_GRP4, IO_TYPE_GRP0) + +#define MT7987_TYPE1_PIN(_number, _name) \ + MTK_TYPED_PIN(_number, _name, DRV_GRP4, IO_TYPE_GRP1) + +#define PIN_FIELD_GPIO(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \ + PIN_FIELD_BASE_CALC(_s_pin, _e_pin, GPIO_BASE, _s_addr, _x_addrs, \ + _s_bit, _x_bits, 32, 0) + +#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ + _x_bits) \ + PIN_FIELD_BASE_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, \ + _s_bit, _x_bits, 32, 0) + +#define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ + _x_bits) \ + PIN_FIELD_BASE_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, \ + _s_bit, _x_bits, 32, 1) + +static const struct mtk_pin_field_calc mt7987_pin_mode_range[] = { + PIN_FIELD_GPIO(0, 49, 0x300, 0x10, 0, 4), +}; + +static const struct mtk_pin_field_calc mt7987_pin_dir_range[] = { + PIN_FIELD_GPIO(0, 49, 0x0, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt7987_pin_di_range[] = { + PIN_FIELD_GPIO(0, 49, 0x200, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt7987_pin_do_range[] = { + PIN_FIELD_GPIO(0, 49, 0x100, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt7987_pin_ies_range[] = { + PIN_FIELD_BASE(0, 0, IOCFG_RT2_BASE, 0x20, 0x10, 3, 1), + PIN_FIELD_BASE(1, 1, IOCFG_RT2_BASE, 0x20, 0x10, 2, 1), + PIN_FIELD_BASE(2, 2, IOCFG_RT2_BASE, 0x20, 0x10, 11, 1), + PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x20, 0x10, 2, 1), + PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x20, 0x10, 1, 1), + PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x20, 0x10, 3, 1), + PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x20, 0x10, 0, 1), + PIN_FIELD_BASE(7, 7, IOCFG_TL_BASE, 0x20, 0x10, 4, 1), + PIN_FIELD_BASE(8, 8, IOCFG_RB_BASE, 0x10, 0x10, 2, 1), + PIN_FIELD_BASE(9, 9, IOCFG_RB_BASE, 0x10, 0x10, 1, 1), + PIN_FIELD_BASE(10, 10, IOCFG_RB_BASE, 0x10, 0x10, 0, 1), + PIN_FIELD_BASE(11, 11, IOCFG_RB_BASE, 0x10, 0x10, 3, 1), + PIN_FIELD_BASE(12, 12, IOCFG_RB_BASE, 0x10, 0x10, 4, 1), + PIN_FIELD_BASE(13, 13, IOCFG_RT1_BASE, 0x20, 0x10, 0, 1), + PIN_FIELD_BASE(14, 14, IOCFG_RT1_BASE, 0x20, 0x10, 15, 1), + PIN_FIELD_BASE(15, 15, IOCFG_RT1_BASE, 0x20, 0x10, 3, 1), + PIN_FIELD_BASE(16, 16, IOCFG_RT1_BASE, 0x20, 0x10, 7, 1), + PIN_FIELD_BASE(17, 17, IOCFG_RT1_BASE, 0x20, 0x10, 6, 1), + PIN_FIELD_BASE(18, 18, IOCFG_RT1_BASE, 0x20, 0x10, 4, 1), + PIN_FIELD_BASE(19, 19, IOCFG_RT1_BASE, 0x20, 0x10, 5, 1), + PIN_FIELD_BASE(20, 20, IOCFG_RT1_BASE, 0x20, 0x10, 8, 1), + PIN_FIELD_BASE(21, 21, IOCFG_RT1_BASE, 0x20, 0x10, 9, 1), + PIN_FIELD_BASE(22, 22, IOCFG_RT1_BASE, 0x20, 0x10, 12, 1), + PIN_FIELD_BASE(23, 23, IOCFG_RT1_BASE, 0x20, 0x10, 11, 1), + PIN_FIELD_BASE(24, 24, IOCFG_RT1_BASE, 0x20, 0x10, 10, 1), + PIN_FIELD_BASE(25, 25, IOCFG_RT1_BASE, 0x20, 0x10, 13, 1), + PIN_FIELD_BASE(26, 26, IOCFG_RT1_BASE, 0x20, 0x10, 14, 1), + PIN_FIELD_BASE(27, 27, IOCFG_RT2_BASE, 0x20, 0x10, 9, 1), + PIN_FIELD_BASE(28, 28, IOCFG_RT2_BASE, 0x20, 0x10, 7, 1), + PIN_FIELD_BASE(29, 29, IOCFG_RT2_BASE, 0x20, 0x10, 8, 1), + PIN_FIELD_BASE(30, 30, IOCFG_RT2_BASE, 0x20, 0x10, 10, 1), + PIN_FIELD_BASE(31, 31, IOCFG_TL_BASE, 0x20, 0x10, 5, 1), + PIN_FIELD_BASE(32, 32, IOCFG_TL_BASE, 0x20, 0x10, 6, 1), + PIN_FIELD_BASE(33, 33, IOCFG_LB_BASE, 0x20, 0x10, 2, 1), + PIN_FIELD_BASE(34, 34, IOCFG_LB_BASE, 0x20, 0x10, 0, 1), + PIN_FIELD_BASE(35, 35, IOCFG_LB_BASE, 0x20, 0x10, 4, 1), + PIN_FIELD_BASE(36, 36, IOCFG_LB_BASE, 0x20, 0x10, 3, 1), + PIN_FIELD_BASE(37, 37, IOCFG_LB_BASE, 0x20, 0x10, 1, 1), + PIN_FIELD_BASE(38, 38, IOCFG_LB_BASE, 0x20, 0x10, 5, 1), + PIN_FIELD_BASE(39, 39, IOCFG_RT1_BASE, 0x20, 0x10, 1, 1), + PIN_FIELD_BASE(40, 40, IOCFG_RT1_BASE, 0x20, 0x10, 2, 1), + PIN_FIELD_BASE(41, 41, IOCFG_RT2_BASE, 0x20, 0x10, 0, 1), + PIN_FIELD_BASE(42, 42, IOCFG_RT2_BASE, 0x20, 0x10, 1, 1), + PIN_FIELD_BASE(43, 43, IOCFG_RT2_BASE, 0x20, 0x10, 4, 1), + PIN_FIELD_BASE(44, 44, IOCFG_RT2_BASE, 0x20, 0x10, 5, 1), + PIN_FIELD_BASE(45, 45, IOCFG_RT2_BASE, 0x20, 0x10, 6, 1), + PIN_FIELD_BASE(46, 46, IOCFG_TL_BASE, 0x20, 0x10, 9, 1), + PIN_FIELD_BASE(47, 47, IOCFG_TL_BASE, 0x20, 0x10, 10, 1), + PIN_FIELD_BASE(48, 48, IOCFG_TL_BASE, 0x20, 0x10, 7, 1), + PIN_FIELD_BASE(49, 49, IOCFG_TL_BASE, 0x20, 0x10, 8, 1), +}; + +static const struct mtk_pin_field_calc mt7987_pin_smt_range[] = { + PIN_FIELD_BASE(0, 0, IOCFG_RT2_BASE, 0x90, 0x10, 3, 1), + PIN_FIELD_BASE(1, 1, IOCFG_RT2_BASE, 0x90, 0x10, 2, 1), + PIN_FIELD_BASE(2, 2, IOCFG_RT2_BASE, 0x90, 0x10, 11, 1), + PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x90, 0x10, 2, 1), + PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x90, 0x10, 1, 1), + PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x90, 0x10, 3, 1), + PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x90, 0x10, 0, 1), + PIN_FIELD_BASE(7, 7, IOCFG_TL_BASE, 0x90, 0x10, 4, 1), + PIN_FIELD_BASE(8, 8, IOCFG_RB_BASE, 0x70, 0x10, 2, 1), + PIN_FIELD_BASE(9, 9, IOCFG_RB_BASE, 0x70, 0x10, 1, 1), + PIN_FIELD_BASE(10, 10, IOCFG_RB_BASE, 0x70, 0x10, 0, 1), + PIN_FIELD_BASE(11, 11, IOCFG_RB_BASE, 0x70, 0x10, 3, 1), + PIN_FIELD_BASE(12, 12, IOCFG_RB_BASE, 0x70, 0x10, 4, 1), + PIN_FIELD_BASE(13, 13, IOCFG_RT1_BASE, 0xA0, 0x10, 0, 1), + PIN_FIELD_BASE(14, 14, IOCFG_RT1_BASE, 0xA0, 0x10, 15, 1), + PIN_FIELD_BASE(15, 15, IOCFG_RT1_BASE, 0xA0, 0x10, 3, 1), + PIN_FIELD_BASE(16, 16, IOCFG_RT1_BASE, 0xA0, 0x10, 7, 1), + PIN_FIELD_BASE(17, 17, IOCFG_RT1_BASE, 0xA0, 0x10, 6, 1), + PIN_FIELD_BASE(18, 18, IOCFG_RT1_BASE, 0xA0, 0x10, 4, 1), + PIN_FIELD_BASE(19, 19, IOCFG_RT1_BASE, 0xA0, 0x10, 5, 1), + PIN_FIELD_BASE(20, 20, IOCFG_RT1_BASE, 0xA0, 0x10, 8, 1), + PIN_FIELD_BASE(21, 21, IOCFG_RT1_BASE, 0xA0, 0x10, 9, 1), + PIN_FIELD_BASE(22, 22, IOCFG_RT1_BASE, 0xA0, 0x10, 12, 1), + PIN_FIELD_BASE(23, 23, IOCFG_RT1_BASE, 0xA0, 0x10, 11, 1), + PIN_FIELD_BASE(24, 24, IOCFG_RT1_BASE, 0xA0, 0x10, 10, 1), + PIN_FIELD_BASE(25, 25, IOCFG_RT1_BASE, 0xA0, 0x10, 13, 1), + PIN_FIELD_BASE(26, 26, IOCFG_RT1_BASE, 0xA0, 0x10, 14, 1), + PIN_FIELD_BASE(27, 27, IOCFG_RT2_BASE, 0x90, 0x10, 9, 1), + PIN_FIELD_BASE(28, 28, IOCFG_RT2_BASE, 0x90, 0x10, 7, 1), + PIN_FIELD_BASE(29, 29, IOCFG_RT2_BASE, 0x90, 0x10, 8, 1), + PIN_FIELD_BASE(30, 30, IOCFG_RT2_BASE, 0x90, 0x10, 10, 1), + PIN_FIELD_BASE(31, 31, IOCFG_TL_BASE, 0x90, 0x10, 5, 1), + PIN_FIELD_BASE(32, 32, IOCFG_TL_BASE, 0x90, 0x10, 6, 1), + PIN_FIELD_BASE(33, 33, IOCFG_LB_BASE, 0x60, 0x10, 2, 1), + PIN_FIELD_BASE(34, 34, IOCFG_LB_BASE, 0x60, 0x10, 0, 1), + PIN_FIELD_BASE(35, 35, IOCFG_LB_BASE, 0x60, 0x10, 4, 1), + PIN_FIELD_BASE(36, 36, IOCFG_LB_BASE, 0x60, 0x10, 3, 1), + PIN_FIELD_BASE(37, 37, IOCFG_LB_BASE, 0x60, 0x10, 1, 1), + PIN_FIELD_BASE(38, 38, IOCFG_LB_BASE, 0x60, 0x10, 5, 1), + PIN_FIELD_BASE(39, 39, IOCFG_RT1_BASE, 0xA0, 0x10, 1, 1), + PIN_FIELD_BASE(40, 40, IOCFG_RT1_BASE, 0xA0, 0x10, 2, 1), + PIN_FIELD_BASE(41, 41, IOCFG_RT2_BASE, 0x90, 0x10, 0, 1), + PIN_FIELD_BASE(42, 42, IOCFG_RT2_BASE, 0x90, 0x10, 1, 1), + PIN_FIELD_BASE(43, 43, IOCFG_RT2_BASE, 0x90, 0x10, 4, 1), + PIN_FIELD_BASE(44, 44, IOCFG_RT2_BASE, 0x90, 0x10, 5, 1), + PIN_FIELD_BASE(45, 45, IOCFG_RT2_BASE, 0x90, 0x10, 6, 1), + PIN_FIELD_BASE(46, 46, IOCFG_TL_BASE, 0x90, 0x10, 9, 1), + PIN_FIELD_BASE(47, 47, IOCFG_TL_BASE, 0x90, 0x10, 10, 1), + PIN_FIELD_BASE(48, 48, IOCFG_TL_BASE, 0x90, 0x10, 7, 1), + PIN_FIELD_BASE(49, 49, IOCFG_TL_BASE, 0x90, 0x10, 8, 1), +}; + +static const struct mtk_pin_field_calc mt7987_pin_pu_range[] = { + PIN_FIELD_BASE(33, 33, IOCFG_LB_BASE, 0x40, 0x10, 2, 1), + PIN_FIELD_BASE(34, 34, IOCFG_LB_BASE, 0x40, 0x10, 0, 1), + PIN_FIELD_BASE(35, 35, IOCFG_LB_BASE, 0x40, 0x10, 4, 1), + PIN_FIELD_BASE(36, 36, IOCFG_LB_BASE, 0x40, 0x10, 3, 1), + PIN_FIELD_BASE(37, 37, IOCFG_LB_BASE, 0x40, 0x10, 1, 1), + PIN_FIELD_BASE(38, 38, IOCFG_LB_BASE, 0x40, 0x10, 5, 1), +}; + +static const struct mtk_pin_field_calc mt7987_pin_pd_range[] = { + PIN_FIELD_BASE(33, 33, IOCFG_LB_BASE, 0x30, 0x10, 2, 1), + PIN_FIELD_BASE(34, 34, IOCFG_LB_BASE, 0x30, 0x10, 0, 1), + PIN_FIELD_BASE(35, 35, IOCFG_LB_BASE, 0x30, 0x10, 4, 1), + PIN_FIELD_BASE(36, 36, IOCFG_LB_BASE, 0x30, 0x10, 3, 1), + PIN_FIELD_BASE(37, 37, IOCFG_LB_BASE, 0x30, 0x10, 1, 1), + PIN_FIELD_BASE(38, 38, IOCFG_LB_BASE, 0x30, 0x10, 5, 1), +}; + +static const struct mtk_pin_field_calc mt7987_pin_drv_range[] = { + PIN_FIELD_BASE(0, 0, IOCFG_RT2_BASE, 0x0, 0x10, 9, 3), + PIN_FIELD_BASE(1, 1, IOCFG_RT2_BASE, 0x0, 0x10, 6, 3), + PIN_FIELD_BASE(2, 2, IOCFG_RT2_BASE, 0x10, 0x10, 3, 3), + PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x0, 0x10, 6, 3), + PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x0, 0x10, 3, 3), + PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x0, 0x10, 9, 3), + PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x0, 0x10, 0, 3), + PIN_FIELD_BASE(7, 7, IOCFG_TL_BASE, 0x0, 0x10, 12, 3), + PIN_FIELD_BASE(8, 8, IOCFG_RB_BASE, 0x0, 0x10, 6, 3), + PIN_FIELD_BASE(9, 9, IOCFG_RB_BASE, 0x0, 0x10, 3, 3), + PIN_FIELD_BASE(10, 10, IOCFG_RB_BASE, 0x0, 0x10, 0, 3), + PIN_FIELD_BASE(11, 11, IOCFG_RB_BASE, 0x0, 0x10, 9, 3), + PIN_FIELD_BASE(12, 12, IOCFG_RB_BASE, 0x0, 0x10, 12, 3), + PIN_FIELD_BASE(13, 13, IOCFG_RT1_BASE, 0x0, 0x10, 0, 3), + PIN_FIELD_BASE(14, 14, IOCFG_RT1_BASE, 0x10, 0x10, 15, 3), + PIN_FIELD_BASE(15, 15, IOCFG_RT1_BASE, 0x0, 0x10, 9, 3), + PIN_FIELD_BASE(16, 16, IOCFG_RT1_BASE, 0x0, 0x10, 21, 3), + PIN_FIELD_BASE(17, 17, IOCFG_RT1_BASE, 0x0, 0x10, 18, 3), + PIN_FIELD_BASE(18, 18, IOCFG_RT1_BASE, 0x0, 0x10, 12, 3), + PIN_FIELD_BASE(19, 19, IOCFG_RT1_BASE, 0x0, 0x10, 15, 3), + PIN_FIELD_BASE(20, 20, IOCFG_RT1_BASE, 0x0, 0x10, 24, 3), + PIN_FIELD_BASE(21, 21, IOCFG_RT1_BASE, 0x0, 0x10, 27, 3), + PIN_FIELD_BASE(22, 22, IOCFG_RT1_BASE, 0x10, 0x10, 6, 3), + PIN_FIELD_BASE(23, 23, IOCFG_RT1_BASE, 0x10, 0x10, 3, 3), + PIN_FIELD_BASE(24, 24, IOCFG_RT1_BASE, 0x10, 0x10, 0, 3), + PIN_FIELD_BASE(25, 25, IOCFG_RT1_BASE, 0x10, 0x10, 9, 3), + PIN_FIELD_BASE(26, 26, IOCFG_RT1_BASE, 0x10, 0x10, 12, 3), + PIN_FIELD_BASE(27, 27, IOCFG_RT2_BASE, 0x0, 0x10, 27, 3), + PIN_FIELD_BASE(28, 28, IOCFG_RT2_BASE, 0x0, 0x10, 21, 3), + PIN_FIELD_BASE(29, 29, IOCFG_RT2_BASE, 0x0, 0x10, 24, 3), + PIN_FIELD_BASE(30, 30, IOCFG_RT2_BASE, 0x10, 0x10, 0, 3), + PIN_FIELD_BASE(31, 31, IOCFG_TL_BASE, 0x0, 0x10, 15, 3), + PIN_FIELD_BASE(32, 32, IOCFG_TL_BASE, 0x0, 0x10, 18, 3), + PIN_FIELD_BASE(33, 33, IOCFG_LB_BASE, 0x0, 0x10, 6, 3), + PIN_FIELD_BASE(34, 34, IOCFG_LB_BASE, 0x0, 0x10, 0, 3), + PIN_FIELD_BASE(35, 35, IOCFG_LB_BASE, 0x0, 0x10, 12, 3), + PIN_FIELD_BASE(36, 36, IOCFG_LB_BASE, 0x0, 0x10, 9, 3), + PIN_FIELD_BASE(37, 37, IOCFG_LB_BASE, 0x0, 0x10, 3, 3), + PIN_FIELD_BASE(38, 38, IOCFG_LB_BASE, 0x0, 0x10, 15, 3), + PIN_FIELD_BASE(39, 39, IOCFG_RT1_BASE, 0x0, 0x10, 3, 3), + PIN_FIELD_BASE(40, 40, IOCFG_RT1_BASE, 0x0, 0x10, 6, 3), + PIN_FIELD_BASE(41, 41, IOCFG_RT2_BASE, 0x0, 0x10, 0, 3), + PIN_FIELD_BASE(42, 42, IOCFG_RT2_BASE, 0x0, 0x10, 3, 3), + PIN_FIELD_BASE(43, 43, IOCFG_RT2_BASE, 0x0, 0x10, 12, 3), + PIN_FIELD_BASE(44, 44, IOCFG_RT2_BASE, 0x0, 0x10, 15, 3), + PIN_FIELD_BASE(45, 45, IOCFG_RT2_BASE, 0x0, 0x10, 18, 3), + PIN_FIELD_BASE(46, 46, IOCFG_TL_BASE, 0x0, 0x10, 27, 3), + PIN_FIELD_BASE(47, 47, IOCFG_TL_BASE, 0x10, 0x10, 0, 3), + PIN_FIELD_BASE(48, 48, IOCFG_TL_BASE, 0x0, 0x10, 21, 3), + PIN_FIELD_BASE(49, 49, IOCFG_TL_BASE, 0x0, 0x10, 24, 3), +}; + +static const struct mtk_pin_field_calc mt7987_pin_pupd_range[] = { + PIN_FIELD_BASE(0, 0, IOCFG_RT2_BASE, 0x30, 0x10, 3, 1), + PIN_FIELD_BASE(1, 1, IOCFG_RT2_BASE, 0x30, 0x10, 2, 1), + PIN_FIELD_BASE(2, 2, IOCFG_RT2_BASE, 0x30, 0x10, 11, 1), + PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x30, 0x10, 2, 1), + PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x30, 0x10, 1, 1), + PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x30, 0x10, 3, 1), + PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x30, 0x10, 0, 1), + PIN_FIELD_BASE(7, 7, IOCFG_TL_BASE, 0x30, 0x10, 4, 1), + PIN_FIELD_BASE(8, 8, IOCFG_RB_BASE, 0x20, 0x10, 2, 1), + PIN_FIELD_BASE(9, 9, IOCFG_RB_BASE, 0x20, 0x10, 1, 1), + PIN_FIELD_BASE(10, 10, IOCFG_RB_BASE, 0x20, 0x10, 0, 1), + PIN_FIELD_BASE(11, 11, IOCFG_RB_BASE, 0x20, 0x10, 3, 1), + PIN_FIELD_BASE(12, 12, IOCFG_RB_BASE, 0x20, 0x10, 4, 1), + PIN_FIELD_BASE(13, 13, IOCFG_RT1_BASE, 0x30, 0x10, 0, 1), + PIN_FIELD_BASE(14, 14, IOCFG_RT1_BASE, 0x30, 0x10, 15, 1), + PIN_FIELD_BASE(15, 15, IOCFG_RT1_BASE, 0x30, 0x10, 3, 1), + PIN_FIELD_BASE(16, 16, IOCFG_RT1_BASE, 0x30, 0x10, 7, 1), + PIN_FIELD_BASE(17, 17, IOCFG_RT1_BASE, 0x30, 0x10, 6, 1), + PIN_FIELD_BASE(18, 18, IOCFG_RT1_BASE, 0x30, 0x10, 4, 1), + PIN_FIELD_BASE(19, 19, IOCFG_RT1_BASE, 0x30, 0x10, 5, 1), + PIN_FIELD_BASE(20, 20, IOCFG_RT1_BASE, 0x30, 0x10, 8, 1), + PIN_FIELD_BASE(21, 21, IOCFG_RT1_BASE, 0x30, 0x10, 9, 1), + PIN_FIELD_BASE(22, 22, IOCFG_RT1_BASE, 0x30, 0x10, 12, 1), + PIN_FIELD_BASE(23, 23, IOCFG_RT1_BASE, 0x30, 0x10, 11, 1), + PIN_FIELD_BASE(24, 24, IOCFG_RT1_BASE, 0x30, 0x10, 10, 1), + PIN_FIELD_BASE(25, 25, IOCFG_RT1_BASE, 0x30, 0x10, 13, 1), + PIN_FIELD_BASE(26, 26, IOCFG_RT1_BASE, 0x30, 0x10, 14, 1), + PIN_FIELD_BASE(27, 27, IOCFG_RT2_BASE, 0x30, 0x10, 9, 1), + PIN_FIELD_BASE(28, 28, IOCFG_RT2_BASE, 0x30, 0x10, 7, 1), + PIN_FIELD_BASE(29, 29, IOCFG_RT2_BASE, 0x30, 0x10, 8, 1), + PIN_FIELD_BASE(30, 30, IOCFG_RT2_BASE, 0x30, 0x10, 10, 1), + PIN_FIELD_BASE(31, 31, IOCFG_TL_BASE, 0x30, 0x10, 5, 1), + PIN_FIELD_BASE(32, 32, IOCFG_TL_BASE, 0x30, 0x10, 6, 1), + + PIN_FIELD_BASE(39, 39, IOCFG_RT1_BASE, 0x30, 0x10, 1, 1), + PIN_FIELD_BASE(40, 40, IOCFG_RT1_BASE, 0x30, 0x10, 2, 1), + PIN_FIELD_BASE(41, 41, IOCFG_RT2_BASE, 0x30, 0x10, 0, 1), + PIN_FIELD_BASE(42, 42, IOCFG_RT2_BASE, 0x30, 0x10, 1, 1), + PIN_FIELD_BASE(43, 43, IOCFG_RT2_BASE, 0x30, 0x10, 4, 1), + PIN_FIELD_BASE(44, 44, IOCFG_RT2_BASE, 0x30, 0x10, 5, 1), + PIN_FIELD_BASE(45, 45, IOCFG_RT2_BASE, 0x30, 0x10, 6, 1), + PIN_FIELD_BASE(46, 46, IOCFG_TL_BASE, 0x30, 0x10, 9, 1), + PIN_FIELD_BASE(47, 47, IOCFG_TL_BASE, 0x30, 0x10, 10, 1), + PIN_FIELD_BASE(48, 48, IOCFG_TL_BASE, 0x30, 0x10, 7, 1), + PIN_FIELD_BASE(49, 49, IOCFG_TL_BASE, 0x30, 0x10, 8, 1), +}; + +static const struct mtk_pin_field_calc mt7987_pin_r0_range[] = { + PIN_FIELD_BASE(0, 0, IOCFG_RT2_BASE, 0x40, 0x10, 3, 1), + PIN_FIELD_BASE(1, 1, IOCFG_RT2_BASE, 0x40, 0x10, 2, 1), + PIN_FIELD_BASE(2, 2, IOCFG_RT2_BASE, 0x40, 0x10, 11, 1), + PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x40, 0x10, 2, 1), + PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x40, 0x10, 1, 1), + PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x40, 0x10, 3, 1), + PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x40, 0x10, 0, 1), + PIN_FIELD_BASE(7, 7, IOCFG_TL_BASE, 0x40, 0x10, 4, 1), + PIN_FIELD_BASE(8, 8, IOCFG_RB_BASE, 0x30, 0x10, 2, 1), + PIN_FIELD_BASE(9, 9, IOCFG_RB_BASE, 0x30, 0x10, 1, 1), + PIN_FIELD_BASE(10, 10, IOCFG_RB_BASE, 0x30, 0x10, 0, 1), + PIN_FIELD_BASE(11, 11, IOCFG_RB_BASE, 0x30, 0x10, 3, 1), + PIN_FIELD_BASE(12, 12, IOCFG_RB_BASE, 0x30, 0x10, 4, 1), + PIN_FIELD_BASE(13, 13, IOCFG_RT1_BASE, 0x40, 0x10, 0, 1), + PIN_FIELD_BASE(14, 14, IOCFG_RT1_BASE, 0x40, 0x10, 15, 1), + PIN_FIELD_BASE(15, 15, IOCFG_RT1_BASE, 0x40, 0x10, 3, 1), + PIN_FIELD_BASE(16, 16, IOCFG_RT1_BASE, 0x40, 0x10, 7, 1), + PIN_FIELD_BASE(17, 17, IOCFG_RT1_BASE, 0x40, 0x10, 6, 1), + PIN_FIELD_BASE(18, 18, IOCFG_RT1_BASE, 0x40, 0x10, 4, 1), + PIN_FIELD_BASE(19, 19, IOCFG_RT1_BASE, 0x40, 0x10, 5, 1), + PIN_FIELD_BASE(20, 20, IOCFG_RT1_BASE, 0x40, 0x10, 8, 1), + PIN_FIELD_BASE(21, 21, IOCFG_RT1_BASE, 0x40, 0x10, 9, 1), + PIN_FIELD_BASE(22, 22, IOCFG_RT1_BASE, 0x40, 0x10, 12, 1), + PIN_FIELD_BASE(23, 23, IOCFG_RT1_BASE, 0x40, 0x10, 11, 1), + PIN_FIELD_BASE(24, 24, IOCFG_RT1_BASE, 0x40, 0x10, 10, 1), + PIN_FIELD_BASE(25, 25, IOCFG_RT1_BASE, 0x40, 0x10, 13, 1), + PIN_FIELD_BASE(26, 26, IOCFG_RT1_BASE, 0x40, 0x10, 14, 1), + PIN_FIELD_BASE(27, 27, IOCFG_RT2_BASE, 0x40, 0x10, 9, 1), + PIN_FIELD_BASE(28, 28, IOCFG_RT2_BASE, 0x40, 0x10, 7, 1), + PIN_FIELD_BASE(29, 29, IOCFG_RT2_BASE, 0x40, 0x10, 8, 1), + PIN_FIELD_BASE(30, 30, IOCFG_RT2_BASE, 0x40, 0x10, 10, 1), + PIN_FIELD_BASE(31, 31, IOCFG_TL_BASE, 0x40, 0x10, 5, 1), + PIN_FIELD_BASE(32, 32, IOCFG_TL_BASE, 0x40, 0x10, 6, 1), + + PIN_FIELD_BASE(39, 39, IOCFG_RT1_BASE, 0x40, 0x10, 1, 1), + PIN_FIELD_BASE(40, 40, IOCFG_RT1_BASE, 0x40, 0x10, 2, 1), + PIN_FIELD_BASE(41, 41, IOCFG_RT2_BASE, 0x40, 0x10, 0, 1), + PIN_FIELD_BASE(42, 42, IOCFG_RT2_BASE, 0x40, 0x10, 1, 1), + PIN_FIELD_BASE(43, 43, IOCFG_RT2_BASE, 0x40, 0x10, 4, 1), + PIN_FIELD_BASE(44, 44, IOCFG_RT2_BASE, 0x40, 0x10, 5, 1), + PIN_FIELD_BASE(45, 45, IOCFG_RT2_BASE, 0x40, 0x10, 6, 1), + PIN_FIELD_BASE(46, 46, IOCFG_TL_BASE, 0x40, 0x10, 9, 1), + PIN_FIELD_BASE(47, 47, IOCFG_TL_BASE, 0x40, 0x10, 10, 1), + PIN_FIELD_BASE(48, 48, IOCFG_TL_BASE, 0x40, 0x10, 7, 1), + PIN_FIELD_BASE(49, 49, IOCFG_TL_BASE, 0x40, 0x10, 8, 1), +}; + +static const struct mtk_pin_field_calc mt7987_pin_r1_range[] = { + PIN_FIELD_BASE(0, 0, IOCFG_RT2_BASE, 0x50, 0x10, 3, 1), + PIN_FIELD_BASE(1, 1, IOCFG_RT2_BASE, 0x50, 0x10, 2, 1), + PIN_FIELD_BASE(2, 2, IOCFG_RT2_BASE, 0x50, 0x10, 11, 1), + PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x50, 0x10, 2, 1), + PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x50, 0x10, 1, 1), + PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x50, 0x10, 3, 1), + PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x50, 0x10, 0, 1), + PIN_FIELD_BASE(7, 7, IOCFG_TL_BASE, 0x50, 0x10, 4, 1), + PIN_FIELD_BASE(8, 8, IOCFG_RB_BASE, 0x40, 0x10, 2, 1), + PIN_FIELD_BASE(9, 9, IOCFG_RB_BASE, 0x40, 0x10, 1, 1), + PIN_FIELD_BASE(10, 10, IOCFG_RB_BASE, 0x40, 0x10, 0, 1), + PIN_FIELD_BASE(11, 11, IOCFG_RB_BASE, 0x40, 0x10, 3, 1), + PIN_FIELD_BASE(12, 12, IOCFG_RB_BASE, 0x40, 0x10, 4, 1), + PIN_FIELD_BASE(13, 13, IOCFG_RT1_BASE, 0x50, 0x10, 0, 1), + PIN_FIELD_BASE(14, 14, IOCFG_RT1_BASE, 0x50, 0x10, 15, 1), + PIN_FIELD_BASE(15, 15, IOCFG_RT1_BASE, 0x50, 0x10, 3, 1), + PIN_FIELD_BASE(16, 16, IOCFG_RT1_BASE, 0x50, 0x10, 7, 1), + PIN_FIELD_BASE(17, 17, IOCFG_RT1_BASE, 0x50, 0x10, 6, 1), + PIN_FIELD_BASE(18, 18, IOCFG_RT1_BASE, 0x50, 0x10, 4, 1), + PIN_FIELD_BASE(19, 19, IOCFG_RT1_BASE, 0x50, 0x10, 5, 1), + PIN_FIELD_BASE(20, 20, IOCFG_RT1_BASE, 0x50, 0x10, 8, 1), + PIN_FIELD_BASE(21, 21, IOCFG_RT1_BASE, 0x50, 0x10, 9, 1), + PIN_FIELD_BASE(22, 22, IOCFG_RT1_BASE, 0x50, 0x10, 12, 1), + PIN_FIELD_BASE(23, 23, IOCFG_RT1_BASE, 0x50, 0x10, 11, 1), + PIN_FIELD_BASE(24, 24, IOCFG_RT1_BASE, 0x50, 0x10, 10, 1), + PIN_FIELD_BASE(25, 25, IOCFG_RT1_BASE, 0x50, 0x10, 13, 1), + PIN_FIELD_BASE(26, 26, IOCFG_RT1_BASE, 0x50, 0x10, 14, 1), + PIN_FIELD_BASE(27, 27, IOCFG_RT2_BASE, 0x50, 0x10, 9, 1), + PIN_FIELD_BASE(28, 28, IOCFG_RT2_BASE, 0x50, 0x10, 7, 1), + PIN_FIELD_BASE(29, 29, IOCFG_RT2_BASE, 0x50, 0x10, 8, 1), + PIN_FIELD_BASE(30, 30, IOCFG_RT2_BASE, 0x50, 0x10, 10, 1), + PIN_FIELD_BASE(31, 31, IOCFG_TL_BASE, 0x50, 0x10, 5, 1), + PIN_FIELD_BASE(32, 32, IOCFG_TL_BASE, 0x50, 0x10, 6, 1), + + PIN_FIELD_BASE(39, 39, IOCFG_RT1_BASE, 0x50, 0x10, 1, 1), + PIN_FIELD_BASE(40, 40, IOCFG_RT1_BASE, 0x50, 0x10, 2, 1), + PIN_FIELD_BASE(41, 41, IOCFG_RT2_BASE, 0x50, 0x10, 0, 1), + PIN_FIELD_BASE(42, 42, IOCFG_RT2_BASE, 0x50, 0x10, 1, 1), + PIN_FIELD_BASE(43, 43, IOCFG_RT2_BASE, 0x50, 0x10, 4, 1), + PIN_FIELD_BASE(44, 44, IOCFG_RT2_BASE, 0x50, 0x10, 5, 1), + PIN_FIELD_BASE(45, 45, IOCFG_RT2_BASE, 0x50, 0x10, 6, 1), + PIN_FIELD_BASE(46, 46, IOCFG_TL_BASE, 0x50, 0x10, 9, 1), + PIN_FIELD_BASE(47, 47, IOCFG_TL_BASE, 0x50, 0x10, 10, 1), + PIN_FIELD_BASE(48, 48, IOCFG_TL_BASE, 0x50, 0x10, 7, 1), + PIN_FIELD_BASE(49, 49, IOCFG_TL_BASE, 0x50, 0x10, 8, 1), +}; + +static const struct mtk_pin_reg_calc mt7987_reg_cals[] = { + [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7987_pin_mode_range), + [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7987_pin_dir_range), + [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7987_pin_di_range), + [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7987_pin_do_range), + [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7987_pin_smt_range), + [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7987_pin_ies_range), + [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7987_pin_pu_range), + [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7987_pin_pd_range), + [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7987_pin_drv_range), + [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7987_pin_pupd_range), + [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7987_pin_r0_range), + [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7987_pin_r1_range), +}; + +static const struct mtk_pin_desc mt7987_pins[] = { + MT7987_TYPE0_PIN(0, "GPIO_WPS"), + MT7987_TYPE0_PIN(1, "GPIO_RESET"), + MT7987_TYPE0_PIN(2, "SYS_WATCHDOG"), + MT7987_TYPE0_PIN(3, "JTAG_JTDO"), + MT7987_TYPE0_PIN(4, "JTAG_JTDI"), + MT7987_TYPE0_PIN(5, "JTAG_JTMS"), + MT7987_TYPE0_PIN(6, "JTAG_JTCLK"), + MT7987_TYPE0_PIN(7, "JTAG_JTRST_N"), + MT7987_TYPE0_PIN(8, "PCM_DTX_I2S_DOUT"), + MT7987_TYPE0_PIN(9, "PCM_DRX_I2S_DIN"), + MT7987_TYPE0_PIN(10, "PCM_CLK_I2S_BCLK"), + MT7987_TYPE0_PIN(11, "PCM_FS_I2S_LRCK"), + MT7987_TYPE0_PIN(12, "PCM_MCK_I2S_MCLK"), + MT7987_TYPE0_PIN(13, "PWM0"), + MT7987_TYPE0_PIN(14, "USB_VBUS"), + MT7987_TYPE0_PIN(15, "SPI0_CLK"), + MT7987_TYPE0_PIN(16, "SPI0_MOSI"), + MT7987_TYPE0_PIN(17, "SPI0_MISO"), + MT7987_TYPE0_PIN(18, "SPI0_CS"), + MT7987_TYPE0_PIN(19, "SPI0_HOLD"), + MT7987_TYPE0_PIN(20, "SPI0_WP"), + MT7987_TYPE0_PIN(21, "SPI1_CLK"), + MT7987_TYPE0_PIN(22, "SPI1_MOSI"), + MT7987_TYPE0_PIN(23, "SPI1_MISO"), + MT7987_TYPE0_PIN(24, "SPI1_CS"), + MT7987_TYPE0_PIN(25, "SPI2_CLK"), + MT7987_TYPE0_PIN(26, "SPI2_MOSI"), + MT7987_TYPE0_PIN(27, "SPI2_MISO"), + MT7987_TYPE0_PIN(28, "SPI2_CS"), + MT7987_TYPE0_PIN(29, "SPI2_HOLD"), + MT7987_TYPE0_PIN(30, "SPI2_WP"), + MT7987_TYPE0_PIN(31, "UART0_RXD"), + MT7987_TYPE0_PIN(32, "UART0_TXD"), + MT7987_TYPE1_PIN(33, "PCIE_PERESET_N_0"), + MT7987_TYPE1_PIN(34, "PCIE_CLK_REQ_0"), + MT7987_TYPE1_PIN(35, "PCIE_WAKE_N_0"), + MT7987_TYPE1_PIN(36, "PCIE_PERESET_N_1"), + MT7987_TYPE1_PIN(37, "PCIE_CLK_REQ_1"), + MT7987_TYPE1_PIN(38, "PCIE_WAKE_N_1"), + MT7987_TYPE0_PIN(39, "SMI_MDC"), + MT7987_TYPE0_PIN(40, "SMI_MDIO"), + MT7987_TYPE0_PIN(41, "GBE_INT"), + MT7987_TYPE0_PIN(42, "GBE_RESET"), + MT7987_TYPE0_PIN(43, "I2C_SCLK"), + MT7987_TYPE0_PIN(44, "I2C_SDATA"), + MT7987_TYPE0_PIN(45, "2P5G_LED0"), + MT7987_TYPE0_PIN(46, "UART1_RXD"), + MT7987_TYPE0_PIN(47, "UART1_TXD"), + MT7987_TYPE0_PIN(48, "UART1_CTS"), + MT7987_TYPE0_PIN(49, "UART1_RTS"), +}; + +/* watchdog */ +static const int mt7987_watchdog_pins[] = {2}; +static const int mt7987_watchdog_funcs[] = {1}; + +/* jtag */ +static const int mt7987_jtag_pins[] = {3, 4, 5, 6, 7}; +static const int mt7987_jtag_funcs[] = {1, 1, 1, 1, 1}; + +/* pcm */ +static const int mt7987_pcm0_0_pins[] = {3, 4, 5, 6, 7}; +static const int mt7987_pcm0_0_funcs[] = {2, 2, 2, 2, 2}; + +static const int mt7987_pcm0_1_pins[] = {8, 9, 10, 11, 12}; +static const int mt7987_pcm0_1_funcs[] = {1, 1, 1, 1, 1}; + +/* uart */ +static const int mt7987_uart0_pins[] = {31, 32}; +static const int mt7987_uart0_funcs[] = {1, 1}; + +static const int mt7987_uart1_0_pins[] = {3, 4, 5, 6}; +static const int mt7987_uart1_0_funcs[] = {3, 3, 3, 3}; + +static const int mt7987_uart1_1_pins[] = {21, 22, 23, 24}; +static const int mt7987_uart1_1_funcs[] = {3, 3, 3, 3}; + +static const int mt7987_uart1_2_pins[] = {46, 47, 48, 49}; +static const int mt7987_uart1_2_funcs[] = {1, 1, 1, 1}; + +static const int mt7987_uart2_0_pins[] = {8, 9, 10, 11}; +static const int mt7987_uart2_0_funcs[] = {2, 2, 2, 2}; + +static const int mt7987_uart2_1_pins[] = {25, 26, 27, 28}; +static const int mt7987_uart2_1_funcs[] = {2, 2, 2, 2}; + +/* pwm */ +static const int mt7987_pwm0_pins[] = {13}; +static const int mt7987_pwm0_funcs[] = {1}; + +static const int mt7987_pwm1_0_pins[] = {7}; +static const int mt7987_pwm1_0_funcs[] = {3}; + +static const int mt7987_pwm1_1_pins[] = {43}; +static const int mt7987_pwm1_1_funcs[] = {2}; + +static const int mt7987_pwm2_0_pins[] = {12}; +static const int mt7987_pwm2_0_funcs[] = {2}; + +static const int mt7987_pwm2_1_pins[] = {44}; +static const int mt7987_pwm2_1_funcs[] = {2}; + +/* vbus */ +static const int mt7987_drv_vbus_p1_pins[] = {14}; +static const int mt7987_drv_vbus_p1_funcs[] = {1}; + +static const int mt7987_drv_vbus_pins[] = {48}; +static const int mt7987_drv_vbus_funcs[] = {3}; + +/* 2p5gbe_led */ +static const int mt7987_2p5gbe_led0_pins[] = {45}; +static const int mt7987_2p5gbe_led0_funcs[] = {1}; + +static const int mt7987_2p5gbe_led1_0_pins[] = {13}; +static const int mt7987_2p5gbe_led1_0_funcs[] = {2}; + +static const int mt7987_2p5gbe_led1_1_pins[] = {49}; +static const int mt7987_2p5gbe_led1_1_funcs[] = {3}; + +/* mdc, mdio */ +static const int mt7987_2p5g_ext_mdc_mdio_pins[] = {23, 24}; +static const int mt7987_2p5g_ext_mdc_mdio_funcs[] = {4, 4}; + +static const int mt7987_mdc_mdio_pins[] = {39, 40}; +static const int mt7987_mdc_mdio_funcs[] = {1, 1}; + +/* spi */ +static const int mt7987_spi0_pins[] = {15, 16, 17, 18}; +static const int mt7987_spi0_funcs[] = {1, 1, 1, 1}; + +static const int mt7987_spi0_wp_hold_pins[] = {19, 20}; +static const int mt7987_spi0_wp_hold_funcs[] = {1, 1}; + +static const int mt7987_spi1_pins[] = {21, 22, 23, 24}; +static const int mt7987_spi1_funcs[] = {1, 1, 1, 1}; + +static const int mt7987_spi1_1_pins[] = {46, 47, 48, 49}; +static const int mt7987_spi1_1_funcs[] = {2, 2, 2, 2}; + +static const int mt7987_spi2_pins[] = {25, 26, 27, 28}; +static const int mt7987_spi2_funcs[] = {1, 1, 1, 1}; + +static const int mt7987_spi2_wp_hold_pins[] = {29, 30}; +static const int mt7987_spi2_wp_hold_funcs[] = {1, 1}; + +/* emmc */ +static const int mt7987_emmc_45_pins[] = {14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24}; +static const int mt7987_emmc_45_funcs[] = {2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2}; + +/* sd */ +static const int mt7987_sd_pins[] = {15, 16, 17, 18, 23, 24}; +static const int mt7987_sd_funcs[] = {2, 2, 2, 2, 2, 2}; + +/* i2c */ +static const int mt7987_i2c0_0_pins[] = {29, 30}; +static const int mt7987_i2c0_0_funcs[] = {2, 2}; + +static const int mt7987_i2c0_1_pins[] = {39, 40}; +static const int mt7987_i2c0_1_funcs[] = {2, 2}; + +static const int mt7987_i2c0_2_pins[] = {43, 44}; +static const int mt7987_i2c0_2_funcs[] = {1, 1}; + +/* pcie */ +static const int mt7987_pcie0_pereset_pins[] = {33}; +static const int mt7987_pcie0_pereset_funcs[] = {1}; + +static const int mt7987_pcie0_clkreq_pins[] = {34}; +static const int mt7987_pcie0_clkreq_funcs[] = {1}; + +static const int mt7987_pcie0_wake_pins[] = {35}; +static const int mt7987_pcie0_wake_funcs[] = {1}; + +static const int mt7987_pcie1_pereset_pins[] = {36}; +static const int mt7987_pcie1_pereset_funcs[] = {1}; + +static const int mt7987_pcie1_clkreq_pins[] = {37}; +static const int mt7987_pcie1_clkreq_funcs[] = {1}; + +static const int mt7987_pcie1_wake_pins[] = {38}; +static const int mt7987_pcie1_wake_funcs[] = {1}; + +static const int mt7987_pcie_phy_i2c_pins[] = {43, 44}; +static const int mt7987_pcie_phy_i2c_funcs[] = {3, 3}; + +/* snfi */ +static const int mt7987_snfi_pins[] = {25, 26, 27, 28, 29, 30}; +static const int mt7987_snfi_funcs[] = {3, 3, 3, 3, 3, 3}; + +/* + * - int hsgmii : + * For pin41 and pin46, they now can only be used as gpio mode for polling + * event. Hence, there's no need to open their pinctrl setting. + * - dfd, udi : + * Due to dfd & udi functions are only used as detection pins for cpu during + * dvt testing stage, we also remove their pinctrl setting. + */ + +static const struct mtk_group_desc mt7987_groups[] = { + PINCTRL_PIN_GROUP("watchdog", mt7987_watchdog), + PINCTRL_PIN_GROUP("jtag", mt7987_jtag), + PINCTRL_PIN_GROUP("pcm0_0", mt7987_pcm0_0), + PINCTRL_PIN_GROUP("pcm0_1", mt7987_pcm0_1), + PINCTRL_PIN_GROUP("uart0", mt7987_uart0), + PINCTRL_PIN_GROUP("uart1_0", mt7987_uart1_0), + PINCTRL_PIN_GROUP("uart1_1", mt7987_uart1_1), + PINCTRL_PIN_GROUP("uart1_2", mt7987_uart1_2), + PINCTRL_PIN_GROUP("uart2_0", mt7987_uart2_0), + PINCTRL_PIN_GROUP("uart2_1", mt7987_uart2_1), + PINCTRL_PIN_GROUP("pwm0", mt7987_pwm0), + PINCTRL_PIN_GROUP("pwm1_0", mt7987_pwm1_0), + PINCTRL_PIN_GROUP("pwm1_1", mt7987_pwm1_1), + PINCTRL_PIN_GROUP("pwm2_0", mt7987_pwm2_0), + PINCTRL_PIN_GROUP("pwm2_1", mt7987_pwm2_1), + PINCTRL_PIN_GROUP("drv_vbus_p1", mt7987_drv_vbus_p1), + PINCTRL_PIN_GROUP("drv_vbus", mt7987_drv_vbus), + PINCTRL_PIN_GROUP("2p5gbe_led0", mt7987_2p5gbe_led0), + PINCTRL_PIN_GROUP("2p5gbe_led1_0", mt7987_2p5gbe_led1_0), + PINCTRL_PIN_GROUP("2p5gbe_led1_1", mt7987_2p5gbe_led1_1), + PINCTRL_PIN_GROUP("2p5g_ext_mdc_mdio", mt7987_2p5g_ext_mdc_mdio), + PINCTRL_PIN_GROUP("mdc_mdio", mt7987_mdc_mdio), + PINCTRL_PIN_GROUP("spi0", mt7987_spi0), + PINCTRL_PIN_GROUP("spi0_wp_hold", mt7987_spi0_wp_hold), + PINCTRL_PIN_GROUP("spi1", mt7987_spi1), + PINCTRL_PIN_GROUP("spi1_1", mt7987_spi1_1), + PINCTRL_PIN_GROUP("spi2", mt7987_spi2), + PINCTRL_PIN_GROUP("spi2_wp_hold", mt7987_spi2_wp_hold), + PINCTRL_PIN_GROUP("emmc_45", mt7987_emmc_45), + PINCTRL_PIN_GROUP("sd", mt7987_sd), + PINCTRL_PIN_GROUP("i2c0_0", mt7987_i2c0_0), + PINCTRL_PIN_GROUP("i2c0_1", mt7987_i2c0_1), + PINCTRL_PIN_GROUP("i2c0_2", mt7987_i2c0_2), + PINCTRL_PIN_GROUP("pcie_phy_i2c", mt7987_pcie_phy_i2c), + PINCTRL_PIN_GROUP("pcie0_pereset", mt7987_pcie0_pereset), + PINCTRL_PIN_GROUP("pcie0_clkreq", mt7987_pcie0_clkreq), + PINCTRL_PIN_GROUP("pcie0_wake", mt7987_pcie0_wake), + PINCTRL_PIN_GROUP("pcie1_pereset", mt7987_pcie1_pereset), + PINCTRL_PIN_GROUP("pcie1_clkreq", mt7987_pcie1_clkreq), + PINCTRL_PIN_GROUP("pcie1_wake", mt7987_pcie1_wake), + PINCTRL_PIN_GROUP("snfi", mt7987_snfi), +}; + +static const struct mtk_io_type_desc mt7987_io_type_desc[] = { + [IO_TYPE_GRP0] = { + .name = "18OD33", + .bias_set = mtk_pinconf_bias_set_pupd_r1_r0, + .drive_set = mtk_pinconf_drive_set_v1, + .input_enable = mtk_pinconf_input_enable_v1, + }, + [IO_TYPE_GRP1] = { + .name = "18A01", + .bias_set = mtk_pinconf_bias_set_pu_pd, + .drive_set = mtk_pinconf_drive_set_v1, + .input_enable = mtk_pinconf_input_enable_v1, + }, +}; + +static const char *const mt7987_wdt_groups[] = {"watchdog",}; +static const char *const mt7987_jtag_groups[] = {"jtag",}; +static const char *const mt7987_pcm_groups[] = {"pcm0_0", "pcm0_1"}; +static const char *const mt7987_uart_groups[] = {"uart0", "uart1_0", "uart1_1", + "uart1_2", "uart2_0", "uart2_1",}; +static const char *const mt7987_pwm_groups[] = {"pwm0", "pwm1_0", "pwm1_1", "pwm2_0", + "pwm2_1",}; +static const char *const mt7987_usb_groups[] = {"drv_vbus_p1", "drv_vbus",}; +static const char *const mt7987_led_groups[] = {"2p5gbe_led0", "2p5gbe_led1_0", + "2p5gbe_led1_1",}; +static const char *const mt7987_ethernet_groups[] = {"2p5g_ext_mdc_mdio", "mdc_mdio",}; +static const char *const mt7987_spi_groups[] = {"spi0", "spi0_wp_hold", "spi1", + "spi1_1", "spi2", "spi2_wp_hold",}; +static const char *const mt7987_flash_groups[] = {"emmc_45", "snfi", "sd",}; +static const char *const mt7987_i2c_groups[] = {"i2c0_0", "i2c0_1", "i2c0_2",}; +static const char *const mt7987_pcie_groups[] = {"pcie_phy_i2c", "pcie0_pereset", + "pcie0_clkreq", "pcie0_wake", + "pcie1_pereset", "pcie1_clkreq", + "pcie1_wake",}; + +static const struct mtk_function_desc mt7987_functions[] = { + {"wdt", mt7987_wdt_groups, ARRAY_SIZE(mt7987_wdt_groups)}, + {"jtag", mt7987_jtag_groups, ARRAY_SIZE(mt7987_jtag_groups)}, + {"pcm", mt7987_pcm_groups, ARRAY_SIZE(mt7987_pcm_groups)}, + {"uart", mt7987_uart_groups, ARRAY_SIZE(mt7987_uart_groups)}, + {"pwm", mt7987_pwm_groups, ARRAY_SIZE(mt7987_pwm_groups)}, + {"usb", mt7987_usb_groups, ARRAY_SIZE(mt7987_usb_groups)}, + {"led", mt7987_led_groups, ARRAY_SIZE(mt7987_led_groups)}, + {"eth", mt7987_ethernet_groups, ARRAY_SIZE(mt7987_ethernet_groups)}, + {"spi", mt7987_spi_groups, ARRAY_SIZE(mt7987_spi_groups)}, + {"flash", mt7987_flash_groups, ARRAY_SIZE(mt7987_flash_groups)}, + {"i2c", mt7987_i2c_groups, ARRAY_SIZE(mt7987_i2c_groups)}, + {"pcie", mt7987_pcie_groups, ARRAY_SIZE(mt7987_pcie_groups)}, +}; + +static const char *const mt7987_pinctrl_register_base_names[] = { + "gpio", "iocfg_rb", "iocfg_lb", "iocfg_rt1", "iocfg_rt2", "iocfg_tl", +}; + +static const struct mtk_pinctrl_soc mt7987_data = { + .name = "mt7987_pinctrl", + .reg_cal = mt7987_reg_cals, + .pins = mt7987_pins, + .npins = ARRAY_SIZE(mt7987_pins), + .grps = mt7987_groups, + .ngrps = ARRAY_SIZE(mt7987_groups), + .funcs = mt7987_functions, + .nfuncs = ARRAY_SIZE(mt7987_functions), + .io_type = mt7987_io_type_desc, + .ntype = ARRAY_SIZE(mt7987_io_type_desc), + .gpio_mode = 0, + .base_names = mt7987_pinctrl_register_base_names, + .nbase_names = ARRAY_SIZE(mt7987_pinctrl_register_base_names), + .base_calc = 1, +}; + +static int mtk_pinctrl_mt7987_probe(struct udevice *dev) +{ + return mtk_pinctrl_common_probe(dev, &mt7987_data); +} + +static const struct udevice_id mt7987_pctrl_match[] = { + {.compatible = "mediatek,mt7987-pinctrl"}, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(mt7987_pinctrl) = { + .name = "mt7987_pinctrl", + .id = UCLASS_PINCTRL, + .of_match = mt7987_pctrl_match, + .ops = &mtk_pinctrl_ops, + .bind = mtk_pinctrl_common_bind, + .probe = mtk_pinctrl_mt7987_probe, + .priv_auto = sizeof(struct mtk_pinctrl_priv), +}; diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7988.c b/drivers/pinctrl/mediatek/pinctrl-mt7988.c index 1f384e86f4e..639e2415c63 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7988.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7988.c @@ -1233,8 +1233,7 @@ static const struct mtk_function_desc mt7988_functions[] = { }; static const char *const mt7988_pinctrl_register_base_names[] = { - "gpio_base", "iocfg_tr_base", "iocfg_br_base", "iocfg_rb_base", - "iocfg_lb_base", "iocfg_tl_base", + "gpio", "iocfg_tr", "iocfg_br", "iocfg_rb", "iocfg_lb", "iocfg_tl", }; static const struct mtk_pinctrl_soc mt7988_data = { diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c index 3760c4611ce..4aecb84504a 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c @@ -816,7 +816,11 @@ int mtk_pinctrl_common_probe(struct udevice *dev, nbase_names = 1; for (i = 0; i < nbase_names; i++) { - addr = devfdt_get_addr_index(dev, i); + if (soc->base_names) + addr = dev_read_addr_name(dev, soc->base_names[i]); + else + addr = dev_read_addr_index(dev, i); + if (addr == FDT_ADDR_T_NONE) return -EINVAL; priv->base[i] = (void __iomem *)addr; diff --git a/drivers/pinctrl/nxp/Kconfig b/drivers/pinctrl/nxp/Kconfig index 06c26f156f6..d13c5f2a6d5 100644 --- a/drivers/pinctrl/nxp/Kconfig +++ b/drivers/pinctrl/nxp/Kconfig @@ -1,14 +1,15 @@ config PINCTRL_IMX bool -config PINCTRL_IMX_SCU +config PINCTRL_IMX_MMIO bool + select PINCTRL_IMX config PINCTRL_IMX5 bool "IMX5 pinctrl driver" depends on ARCH_MX5 && PINCTRL_FULL select DEVRES - select PINCTRL_IMX + select PINCTRL_IMX_MMIO help Say Y here to enable the imx5 pinctrl driver @@ -22,7 +23,7 @@ config PINCTRL_IMX6 bool "IMX6 pinctrl driver" depends on ARCH_MX6 && PINCTRL_FULL select DEVRES - select PINCTRL_IMX + select PINCTRL_IMX_MMIO help Say Y here to enable the imx6 pinctrl driver @@ -36,7 +37,7 @@ config PINCTRL_IMX7 bool "IMX7 pinctrl driver" depends on ARCH_MX7 && PINCTRL_FULL select DEVRES - select PINCTRL_IMX + select PINCTRL_IMX_MMIO help Say Y here to enable the imx7 pinctrl driver @@ -50,7 +51,7 @@ config PINCTRL_IMX7ULP bool "IMX7ULP pinctrl driver" depends on ARCH_MX7ULP && PINCTRL_FULL select DEVRES - select PINCTRL_IMX + select PINCTRL_IMX_MMIO help Say Y here to enable the imx7ulp pinctrl driver @@ -64,7 +65,7 @@ config PINCTRL_IMX8ULP bool "IMX8ULP pinctrl driver" depends on ARCH_IMX8ULP && PINCTRL_FULL select DEVRES - select PINCTRL_IMX + select PINCTRL_IMX_MMIO help Say Y here to enable the imx8ulp pinctrl driver @@ -79,7 +80,6 @@ config PINCTRL_IMX8 depends on ARCH_IMX8 && PINCTRL_FULL select DEVRES select PINCTRL_IMX - select PINCTRL_IMX_SCU help Say Y here to enable the imx8 pinctrl driver @@ -92,7 +92,7 @@ config PINCTRL_IMX8 config PINCTRL_IMX8M bool "IMX8M pinctrl driver" depends on ARCH_IMX8M && PINCTRL_FULL - select PINCTRL_IMX + select PINCTRL_IMX_MMIO help Say Y here to enable the imx8m pinctrl driver @@ -105,7 +105,7 @@ config PINCTRL_IMX8M config PINCTRL_IMX93 bool "IMX8M pinctrl driver" depends on ARCH_IMX9 && PINCTRL_FULL - select PINCTRL_IMX + select PINCTRL_IMX_MMIO help Say Y here to enable the imx8m pinctrl driver @@ -129,7 +129,7 @@ config PINCTRL_IMXRT bool "IMXRT pinctrl driver" depends on ARCH_IMXRT && PINCTRL_FULL select DEVRES - select PINCTRL_IMX + select PINCTRL_IMX_MMIO help Say Y here to enable the imxrt pinctrl driver @@ -143,7 +143,7 @@ config PINCTRL_VYBRID bool "Vybrid (vf610) pinctrl driver" depends on ARCH_VF610 && PINCTRL_FULL select DEVRES - select PINCTRL_IMX + select PINCTRL_IMX_MMIO help Say Y here to enable the Vybrid (vf610) pinctrl driver diff --git a/drivers/pinctrl/nxp/Makefile b/drivers/pinctrl/nxp/Makefile index f10aa6ef188..44e37c631e5 100644 --- a/drivers/pinctrl/nxp/Makefile +++ b/drivers/pinctrl/nxp/Makefile @@ -1,10 +1,10 @@ obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o +obj-$(CONFIG_PINCTRL_IMX_MMIO) += pinctrl-imx-mmio.o obj-$(CONFIG_PINCTRL_IMX5) += pinctrl-imx5.o obj-$(CONFIG_PINCTRL_IMX6) += pinctrl-imx6.o obj-$(CONFIG_PINCTRL_IMX7) += pinctrl-imx7.o obj-$(CONFIG_PINCTRL_IMX7ULP) += pinctrl-imx7ulp.o obj-$(CONFIG_PINCTRL_IMX8ULP) += pinctrl-imx8ulp.o -obj-$(CONFIG_PINCTRL_IMX_SCU) += pinctrl-scu.o obj-$(CONFIG_PINCTRL_IMX8) += pinctrl-imx8.o obj-$(CONFIG_PINCTRL_IMX8M) += pinctrl-imx8m.o obj-$(CONFIG_PINCTRL_IMX93) += pinctrl-imx93.o diff --git a/drivers/pinctrl/nxp/pinctrl-imx-mmio.c b/drivers/pinctrl/nxp/pinctrl-imx-mmio.c new file mode 100644 index 00000000000..6ee108a0120 --- /dev/null +++ b/drivers/pinctrl/nxp/pinctrl-imx-mmio.c @@ -0,0 +1,228 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016 Peng Fan <van.freenix@gmail.com> + */ + +#include <malloc.h> +#include <mapmem.h> +#include <asm/global_data.h> +#include <dm/device_compat.h> +#include <dm/devres.h> +#include <linux/bitops.h> +#include <linux/io.h> +#include <linux/err.h> +#include <dm.h> +#include <dm/pinctrl.h> + +#include "pinctrl-imx.h" + +DECLARE_GLOBAL_DATA_PTR; + +int imx_pinctrl_set_state_mmio(struct udevice *dev, struct udevice *config) +{ + struct imx_pinctrl_priv *priv = dev_get_priv(dev); + struct imx_pinctrl_soc_info *info = priv->info; + u32 mux_shift = info->mux_mask ? ffs(info->mux_mask) - 1 : 0; + u32 input_val, mux_mode, config_val; + int mux_reg, conf_reg, input_reg; + int npins, pin_size; + int i, j = 0, ret; + u32 *pin_data; + + if (info->flags & SHARE_MUX_CONF_REG) + pin_size = SHARE_FSL_PIN_SIZE; + else + pin_size = FSL_PIN_SIZE; + + ret = imx_pinctrl_set_state_common(dev, config, pin_size, + &pin_data, &npins); + if (ret) + return ret; + + /* + * Refer to linux documentation for details: + * Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt + */ + for (i = 0; i < npins; i++) { + mux_reg = pin_data[j++]; + + if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg) + mux_reg = -1; + + if (info->flags & SHARE_MUX_CONF_REG) { + conf_reg = mux_reg; + } else { + conf_reg = pin_data[j++]; + if (!(info->flags & ZERO_OFFSET_VALID) && + !conf_reg) + conf_reg = -1; + } + + if ((mux_reg == -1) || (conf_reg == -1)) { + dev_err(dev, "Error mux_reg or conf_reg\n"); + devm_kfree(dev, pin_data); + return -EINVAL; + } + + input_reg = pin_data[j++]; + mux_mode = pin_data[j++]; + input_val = pin_data[j++]; + config_val = pin_data[j++]; + + dev_dbg(dev, "mux_reg 0x%x, conf_reg 0x%x, input_reg 0x%x, mux_mode 0x%x, input_val 0x%x, config_val 0x%x\n", + mux_reg, conf_reg, input_reg, mux_mode, + input_val, config_val); + + if (config_val & IMX_PAD_SION) + mux_mode |= IOMUXC_CONFIG_SION; + + config_val &= ~IMX_PAD_SION; + + /* Set Mux */ + if (info->flags & SHARE_MUX_CONF_REG) { + clrsetbits_le32(info->base + mux_reg, + info->mux_mask, + mux_mode << mux_shift); + } else { + writel(mux_mode, info->base + mux_reg); + } + + dev_dbg(dev, "write mux: offset 0x%x val 0x%x\n", + mux_reg, mux_mode); + + /* + * Set select input + * + * If the select input value begins with 0xff, + * it's a quirky select input and the value should + * be interpreted as below. + * 31 23 15 7 0 + * | 0xff | shift | width | select | + * It's used to work around the problem that the + * select input for some pin is not implemented in + * the select input register but in some general + * purpose register. We encode the select input + * value, width and shift of the bit field into + * input_val cell of pin function ID in device tree, + * and then decode them here for setting up the select + * input bits in general purpose register. + */ + + if (input_val >> 24 == 0xff) { + u32 val = input_val; + u8 select = val & 0xff; + u8 width = (val >> 8) & 0xff; + u8 shift = (val >> 16) & 0xff; + u32 mask = ((1 << width) - 1) << shift; + /* + * The input_reg[i] here is actually some + * IOMUXC general purpose register, not + * regular select input register. + */ + val = readl(info->base + input_reg); + val &= ~mask; + val |= select << shift; + writel(val, info->base + input_reg); + } else if (input_reg) { + /* + * Regular select input register can never be + * at offset 0, and we only print register + * value for regular case. + */ + if (info->input_sel_base) + writel(input_val, + info->input_sel_base + + input_reg); + else + writel(input_val, + info->base + input_reg); + + dev_dbg(dev, "select_input: offset 0x%x val 0x%x\n", + input_reg, input_val); + } + + /* Set config */ + if (!(config_val & IMX_NO_PAD_CTL)) { + if (info->flags & SHARE_MUX_CONF_REG) { + clrsetbits_le32(info->base + conf_reg, + ~info->mux_mask, + config_val); + } else { + writel(config_val, + info->base + conf_reg); + } + + dev_dbg(dev, "write config: offset 0x%x val 0x%x\n", + conf_reg, config_val); + } + } + + devm_kfree(dev, pin_data); + + return 0; +} + + +int imx_pinctrl_probe_mmio(struct udevice *dev) +{ + struct imx_pinctrl_soc_info *info = + (struct imx_pinctrl_soc_info *)dev_get_driver_data(dev); + struct imx_pinctrl_priv *priv = dev_get_priv(dev); + struct ofnode_phandle_args arg; + ofnode node = dev_ofnode(dev); + fdt_addr_t addr; + fdt_size_t size; + int ret; + + ret = imx_pinctrl_probe_common(dev); + if (ret) + return ret; + + addr = ofnode_get_addr_size_index(node, 0, &size); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + info->base = map_sysmem(addr, size); + if (!info->base) + return -ENOMEM; + priv->info = info; + + info->mux_mask = ofnode_read_u32_default(node, "fsl,mux_mask", 0); + /* + * Refer to linux documentation for details: + * Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt + */ + if (ofnode_read_bool(node, "fsl,input-sel")) { + ret = ofnode_parse_phandle_with_args(node, "fsl,input-sel", + NULL, 0, 0, &arg); + if (ret) { + dev_err(dev, "iomuxc fsl,input-sel property not found\n"); + return -EINVAL; + } + + addr = ofnode_get_addr_size(arg.node, "reg", &size); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + info->input_sel_base = map_sysmem(addr, size); + if (!info->input_sel_base) + return -ENOMEM; + } + + dev_dbg(dev, "initialized IMX pinctrl driver\n"); + + return 0; +} + +int imx_pinctrl_remove_mmio(struct udevice *dev) +{ + struct imx_pinctrl_priv *priv = dev_get_priv(dev); + struct imx_pinctrl_soc_info *info = priv->info; + + if (info->input_sel_base) + unmap_sysmem(info->input_sel_base); + if (info->base) + unmap_sysmem(info->base); + + return 0; +} diff --git a/drivers/pinctrl/nxp/pinctrl-imx.c b/drivers/pinctrl/nxp/pinctrl-imx.c index b1960c56b51..7d91ccfb26f 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx.c +++ b/drivers/pinctrl/nxp/pinctrl-imx.c @@ -18,28 +18,15 @@ DECLARE_GLOBAL_DATA_PTR; -static int imx_pinctrl_set_state(struct udevice *dev, struct udevice *config) +int imx_pinctrl_set_state_common(struct udevice *dev, struct udevice *config, + int pin_size, u32 **pin_data, int *npins) { - struct imx_pinctrl_priv *priv = dev_get_priv(dev); - struct imx_pinctrl_soc_info *info = priv->info; ofnode node = dev_ofnode(config); const struct fdt_property *prop; - u32 *pin_data; - int npins, size, pin_size; - int mux_reg, conf_reg, input_reg; - u32 input_val, mux_mode, config_val; - u32 mux_shift = info->mux_mask ? ffs(info->mux_mask) - 1 : 0; - int i, j = 0; + int size; dev_dbg(dev, "%s: %s\n", __func__, config->name); - if (info->flags & IMX8_USE_SCU) - pin_size = SHARE_IMX8_PIN_SIZE; - else if (info->flags & SHARE_MUX_CONF_REG) - pin_size = SHARE_FSL_PIN_SIZE; - else - pin_size = FSL_PIN_SIZE; - prop = ofnode_get_property(node, "fsl,pins", &size); if (!prop) { dev_err(dev, "No fsl,pins property in node %s\n", config->name); @@ -52,161 +39,26 @@ static int imx_pinctrl_set_state(struct udevice *dev, struct udevice *config) return -EINVAL; } - pin_data = devm_kzalloc(dev, size, 0); - if (!pin_data) + *pin_data = devm_kzalloc(dev, size, 0); + if (!*pin_data) return -ENOMEM; - if (ofnode_read_u32_array(node, "fsl,pins", - pin_data, size >> 2)) { + if (ofnode_read_u32_array(node, "fsl,pins", *pin_data, size >> 2)) { dev_err(dev, "Error reading pin data.\n"); - devm_kfree(dev, pin_data); + devm_kfree(dev, *pin_data); return -EINVAL; } - npins = size / pin_size; - - if (info->flags & IMX8_USE_SCU) { - imx_pinctrl_scu_conf_pins(info, pin_data, npins); - } else { - /* - * Refer to linux documentation for details: - * Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt - */ - for (i = 0; i < npins; i++) { - mux_reg = pin_data[j++]; - - if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg) - mux_reg = -1; - - if (info->flags & SHARE_MUX_CONF_REG) { - conf_reg = mux_reg; - } else { - conf_reg = pin_data[j++]; - if (!(info->flags & ZERO_OFFSET_VALID) && - !conf_reg) - conf_reg = -1; - } - - if ((mux_reg == -1) || (conf_reg == -1)) { - dev_err(dev, "Error mux_reg or conf_reg\n"); - devm_kfree(dev, pin_data); - return -EINVAL; - } - - input_reg = pin_data[j++]; - mux_mode = pin_data[j++]; - input_val = pin_data[j++]; - config_val = pin_data[j++]; - - dev_dbg(dev, "mux_reg 0x%x, conf_reg 0x%x, " - "input_reg 0x%x, mux_mode 0x%x, " - "input_val 0x%x, config_val 0x%x\n", - mux_reg, conf_reg, input_reg, mux_mode, - input_val, config_val); - - if (config_val & IMX_PAD_SION) - mux_mode |= IOMUXC_CONFIG_SION; - - config_val &= ~IMX_PAD_SION; - - /* Set Mux */ - if (info->flags & SHARE_MUX_CONF_REG) { - clrsetbits_le32(info->base + mux_reg, - info->mux_mask, - mux_mode << mux_shift); - } else { - writel(mux_mode, info->base + mux_reg); - } - - dev_dbg(dev, "write mux: offset 0x%x val 0x%x\n", - mux_reg, mux_mode); - - /* - * Set select input - * - * If the select input value begins with 0xff, - * it's a quirky select input and the value should - * be interpreted as below. - * 31 23 15 7 0 - * | 0xff | shift | width | select | - * It's used to work around the problem that the - * select input for some pin is not implemented in - * the select input register but in some general - * purpose register. We encode the select input - * value, width and shift of the bit field into - * input_val cell of pin function ID in device tree, - * and then decode them here for setting up the select - * input bits in general purpose register. - */ - - if (input_val >> 24 == 0xff) { - u32 val = input_val; - u8 select = val & 0xff; - u8 width = (val >> 8) & 0xff; - u8 shift = (val >> 16) & 0xff; - u32 mask = ((1 << width) - 1) << shift; - /* - * The input_reg[i] here is actually some - * IOMUXC general purpose register, not - * regular select input register. - */ - val = readl(info->base + input_reg); - val &= ~mask; - val |= select << shift; - writel(val, info->base + input_reg); - } else if (input_reg) { - /* - * Regular select input register can never be - * at offset 0, and we only print register - * value for regular case. - */ - if (info->input_sel_base) - writel(input_val, - info->input_sel_base + - input_reg); - else - writel(input_val, - info->base + input_reg); - - dev_dbg(dev, "select_input: offset 0x%x val " - "0x%x\n", input_reg, input_val); - } - - /* Set config */ - if (!(config_val & IMX_NO_PAD_CTL)) { - if (info->flags & SHARE_MUX_CONF_REG) { - clrsetbits_le32(info->base + conf_reg, - ~info->mux_mask, - config_val); - } else { - writel(config_val, - info->base + conf_reg); - } - - dev_dbg(dev, "write config: offset 0x%x val " - "0x%x\n", conf_reg, config_val); - } - } - } - - devm_kfree(dev, pin_data); + *npins = size / pin_size; return 0; } -const struct pinctrl_ops imx_pinctrl_ops = { - .set_state = imx_pinctrl_set_state, -}; - -int imx_pinctrl_probe(struct udevice *dev, - struct imx_pinctrl_soc_info *info) +int imx_pinctrl_probe_common(struct udevice *dev) { + struct imx_pinctrl_soc_info *info = + (struct imx_pinctrl_soc_info *)dev_get_driver_data(dev); struct imx_pinctrl_priv *priv = dev_get_priv(dev); - struct ofnode_phandle_args arg; - ofnode node = dev_ofnode(dev); - fdt_addr_t addr; - fdt_size_t size; - int ret; if (!info) { dev_err(dev, "wrong pinctrl info\n"); @@ -216,57 +68,5 @@ int imx_pinctrl_probe(struct udevice *dev, priv->dev = dev; priv->info = info; - if (info->flags & IMX8_USE_SCU) - return 0; - - addr = ofnode_get_addr_size_index(dev_ofnode(dev), 0, &size); - if (addr == FDT_ADDR_T_NONE) - return -EINVAL; - - info->base = map_sysmem(addr, size); - if (!info->base) - return -ENOMEM; - priv->info = info; - - info->mux_mask = ofnode_read_u32(node, "fsl,mux_mask", 0); - /* - * Refer to linux documentation for details: - * Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt - */ - if (ofnode_read_bool(node, "fsl,input-sel")) { - ret = ofnode_parse_phandle_with_args(node, "fsl,input-sel", - NULL, 0, 0, &arg); - if (ret) { - dev_err(dev, "iomuxc fsl,input-sel property not found\n"); - return -EINVAL; - } - - addr = ofnode_get_addr_size(arg.node, "reg", &size); - if (addr == FDT_ADDR_T_NONE) - return -EINVAL; - - info->input_sel_base = map_sysmem(addr, size); - if (!info->input_sel_base) - return -ENOMEM; - } - - dev_dbg(dev, "initialized IMX pinctrl driver\n"); - - return 0; -} - -int imx_pinctrl_remove(struct udevice *dev) -{ - struct imx_pinctrl_priv *priv = dev_get_priv(dev); - struct imx_pinctrl_soc_info *info = priv->info; - - if (info->flags & IMX8_USE_SCU) - return 0; - - if (info->input_sel_base) - unmap_sysmem(info->input_sel_base); - if (info->base) - unmap_sysmem(info->base); - return 0; } diff --git a/drivers/pinctrl/nxp/pinctrl-imx.h b/drivers/pinctrl/nxp/pinctrl-imx.h index fa4c084e2fc..9adf999d3bb 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx.h +++ b/drivers/pinctrl/nxp/pinctrl-imx.h @@ -28,8 +28,6 @@ struct imx_pinctrl_priv { struct imx_pinctrl_soc_info *info; }; -extern const struct pinctrl_ops imx_pinctrl_ops; - #define IMX_NO_PAD_CTL 0x80000000 /* no pin config need */ #define IMX_PAD_SION 0x40000000 /* set SION */ @@ -50,19 +48,13 @@ extern const struct pinctrl_ops imx_pinctrl_ops; #define IOMUXC_CONFIG_SION (0x1 << 4) -int imx_pinctrl_probe(struct udevice *dev, struct imx_pinctrl_soc_info *info); +int imx_pinctrl_probe_common(struct udevice *dev); +int imx_pinctrl_probe_mmio(struct udevice *dev); -int imx_pinctrl_remove(struct udevice *dev); +int imx_pinctrl_remove_mmio(struct udevice *dev); -#ifdef CONFIG_PINCTRL_IMX_SCU -int imx_pinctrl_scu_conf_pins(struct imx_pinctrl_soc_info *info, - u32 *pin_data, int npins); -#else -static inline int imx_pinctrl_scu_conf_pins(struct imx_pinctrl_soc_info *info, - u32 *pin_data, int npins) -{ - return 0; -} -#endif +int imx_pinctrl_set_state_common(struct udevice *dev, struct udevice *config, + int pin_size, u32 **pin_data, int *npins); +int imx_pinctrl_set_state_mmio(struct udevice *dev, struct udevice *config); #endif /* __DRIVERS_PINCTRL_IMX_H */ diff --git a/drivers/pinctrl/nxp/pinctrl-imx5.c b/drivers/pinctrl/nxp/pinctrl-imx5.c index 6b690fdce8f..af853bea180 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx5.c +++ b/drivers/pinctrl/nxp/pinctrl-imx5.c @@ -11,14 +11,6 @@ static struct imx_pinctrl_soc_info imx5_pinctrl_soc_info __section(".data"); -static int imx5_pinctrl_probe(struct udevice *dev) -{ - struct imx_pinctrl_soc_info *info = - (struct imx_pinctrl_soc_info *)dev_get_driver_data(dev); - - return imx_pinctrl_probe(dev, info); -} - static const struct udevice_id imx5_pinctrl_match[] = { { .compatible = "fsl,imx53-iomuxc", @@ -31,13 +23,17 @@ static const struct udevice_id imx5_pinctrl_match[] = { { /* sentinel */ } }; +static const struct pinctrl_ops imx5_pinctrl_ops = { + .set_state = imx_pinctrl_set_state_mmio, +}; + U_BOOT_DRIVER(imx5_pinctrl) = { .name = "imx5-pinctrl", .id = UCLASS_PINCTRL, .of_match = of_match_ptr(imx5_pinctrl_match), - .probe = imx5_pinctrl_probe, - .remove = imx_pinctrl_remove, + .probe = imx_pinctrl_probe_mmio, + .remove = imx_pinctrl_remove_mmio, .priv_auto = sizeof(struct imx_pinctrl_priv), - .ops = &imx_pinctrl_ops, + .ops = &imx5_pinctrl_ops, .flags = DM_FLAG_PRE_RELOC, }; diff --git a/drivers/pinctrl/nxp/pinctrl-imx6.c b/drivers/pinctrl/nxp/pinctrl-imx6.c index 322eec87ff5..5c6aac56eb7 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx6.c +++ b/drivers/pinctrl/nxp/pinctrl-imx6.c @@ -20,14 +20,6 @@ static struct imx_pinctrl_soc_info imx6_snvs_pinctrl_soc_info = { .flags = ZERO_OFFSET_VALID, }; -static int imx6_pinctrl_probe(struct udevice *dev) -{ - struct imx_pinctrl_soc_info *info = - (struct imx_pinctrl_soc_info *)dev_get_driver_data(dev); - - return imx_pinctrl_probe(dev, info); -} - static const struct udevice_id imx6_pinctrl_match[] = { { .compatible = "fsl,imx6q-iomuxc", .data = (ulong)&imx6_pinctrl_soc_info }, { .compatible = "fsl,imx6dl-iomuxc", .data = (ulong)&imx6_pinctrl_soc_info }, @@ -40,14 +32,18 @@ static const struct udevice_id imx6_pinctrl_match[] = { { /* sentinel */ } }; +static const struct pinctrl_ops imx6_pinctrl_ops = { + .set_state = imx_pinctrl_set_state_mmio, +}; + U_BOOT_DRIVER(fsl_imx6q_iomuxc) = { .name = "fsl_imx6q_iomuxc", .id = UCLASS_PINCTRL, .of_match = of_match_ptr(imx6_pinctrl_match), - .probe = imx6_pinctrl_probe, - .remove = imx_pinctrl_remove, + .probe = imx_pinctrl_probe_mmio, + .remove = imx_pinctrl_remove_mmio, .priv_auto = sizeof(struct imx_pinctrl_priv), - .ops = &imx_pinctrl_ops, + .ops = &imx6_pinctrl_ops, .flags = DM_FLAG_PRE_RELOC, }; diff --git a/drivers/pinctrl/nxp/pinctrl-imx7.c b/drivers/pinctrl/nxp/pinctrl-imx7.c index a8275e26456..14c3d4d4e77 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx7.c +++ b/drivers/pinctrl/nxp/pinctrl-imx7.c @@ -14,27 +14,23 @@ static struct imx_pinctrl_soc_info imx7_lpsr_pinctrl_soc_info = { .flags = ZERO_OFFSET_VALID, }; -static int imx7_pinctrl_probe(struct udevice *dev) -{ - struct imx_pinctrl_soc_info *info = - (struct imx_pinctrl_soc_info *)dev_get_driver_data(dev); - - return imx_pinctrl_probe(dev, info); -} - static const struct udevice_id imx7_pinctrl_match[] = { { .compatible = "fsl,imx7d-iomuxc", .data = (ulong)&imx7_pinctrl_soc_info }, { .compatible = "fsl,imx7d-iomuxc-lpsr", .data = (ulong)&imx7_lpsr_pinctrl_soc_info }, { /* sentinel */ } }; +static const struct pinctrl_ops imx7_pinctrl_ops = { + .set_state = imx_pinctrl_set_state_mmio, +}; + U_BOOT_DRIVER(imx7_pinctrl) = { .name = "imx7-pinctrl", .id = UCLASS_PINCTRL, .of_match = of_match_ptr(imx7_pinctrl_match), - .probe = imx7_pinctrl_probe, - .remove = imx_pinctrl_remove, + .probe = imx_pinctrl_probe_mmio, + .remove = imx_pinctrl_remove_mmio, .priv_auto = sizeof(struct imx_pinctrl_priv), - .ops = &imx_pinctrl_ops, + .ops = &imx7_pinctrl_ops, .flags = DM_FLAG_PRE_RELOC, }; diff --git a/drivers/pinctrl/nxp/pinctrl-imx7ulp.c b/drivers/pinctrl/nxp/pinctrl-imx7ulp.c index 7ea2dbe7d36..400e1266822 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx7ulp.c +++ b/drivers/pinctrl/nxp/pinctrl-imx7ulp.c @@ -18,27 +18,23 @@ static struct imx_pinctrl_soc_info imx7ulp_pinctrl_soc_info1 = { .flags = ZERO_OFFSET_VALID | SHARE_MUX_CONF_REG | CFG_IBE_OBE, }; -static int imx7ulp_pinctrl_probe(struct udevice *dev) -{ - struct imx_pinctrl_soc_info *info = - (struct imx_pinctrl_soc_info *)dev_get_driver_data(dev); - - return imx_pinctrl_probe(dev, info); -} - static const struct udevice_id imx7ulp_pinctrl_match[] = { { .compatible = "fsl,imx7ulp-iomuxc-0", .data = (ulong)&imx7ulp_pinctrl_soc_info0 }, { .compatible = "fsl,imx7ulp-iomuxc-1", .data = (ulong)&imx7ulp_pinctrl_soc_info1 }, { /* sentinel */ } }; +static const struct pinctrl_ops imx7ulp_pinctrl_ops = { + .set_state = imx_pinctrl_set_state_mmio, +}; + U_BOOT_DRIVER(imx7ulp_pinctrl) = { .name = "imx7ulp-pinctrl", .id = UCLASS_PINCTRL, .of_match = of_match_ptr(imx7ulp_pinctrl_match), - .probe = imx7ulp_pinctrl_probe, - .remove = imx_pinctrl_remove, + .probe = imx_pinctrl_probe_mmio, + .remove = imx_pinctrl_remove_mmio, .priv_auto = sizeof(struct imx_pinctrl_priv), - .ops = &imx_pinctrl_ops, + .ops = &imx7ulp_pinctrl_ops, .flags = DM_FLAG_PRE_RELOC, }; diff --git a/drivers/pinctrl/nxp/pinctrl-imx8.c b/drivers/pinctrl/nxp/pinctrl-imx8.c index 4e9a9ea6808..9b3b5aec07a 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx8.c +++ b/drivers/pinctrl/nxp/pinctrl-imx8.c @@ -3,6 +3,12 @@ * Copyright 2018 NXP */ +#include <dm.h> +#include <errno.h> +#include <linux/bitops.h> +#include <asm/io.h> +#include <firmware/imx/sci/sci.h> +#include <misc.h> #include <asm/global_data.h> #include <dm/device.h> #include <dm/pinctrl.h> @@ -11,31 +17,91 @@ DECLARE_GLOBAL_DATA_PTR; -static struct imx_pinctrl_soc_info imx8_pinctrl_soc_info = { - .flags = IMX8_USE_SCU, -}; +#define PADRING_IFMUX_EN_SHIFT 31 +#define PADRING_IFMUX_EN_MASK BIT(31) +#define PADRING_GP_EN_SHIFT 30 +#define PADRING_GP_EN_MASK BIT(30) +#define PADRING_IFMUX_SHIFT 27 +#define PADRING_IFMUX_MASK GENMASK(29, 27) -static int imx8_pinctrl_probe(struct udevice *dev) +static int imx_pinconf_scu_set(struct imx_pinctrl_soc_info *info, u32 pad, + u32 mux, u32 val) { - struct imx_pinctrl_soc_info *info = - (struct imx_pinctrl_soc_info *)dev_get_driver_data(dev); + int ret; + + /* + * Mux should be done in pmx set, but we do not have a good api + * to handle that in scfw, so config it in pad conf func + */ + + if (!sc_rm_is_pad_owned(-1, pad)) { + debug("Pad[%u] is not owned by curr partition\n", pad); + return -EPERM; + } - return imx_pinctrl_probe(dev, info); + val |= PADRING_IFMUX_EN_MASK; + val |= PADRING_GP_EN_MASK; + val |= (mux << PADRING_IFMUX_SHIFT) & PADRING_IFMUX_MASK; + + ret = sc_pad_set(-1, pad, val); + if (ret) + printf("%s %d\n", __func__, ret); + + return 0; } +int imx_pinctrl_set_state_scu(struct udevice *dev, struct udevice *config) +{ + struct imx_pinctrl_priv *priv = dev_get_priv(dev); + struct imx_pinctrl_soc_info *info = priv->info; + int pin_id, mux, config_val; + u32 *pin_data; + int i, j = 0; + int npins; + int ret; + + ret = imx_pinctrl_set_state_common(dev, config, SHARE_IMX8_PIN_SIZE, + &pin_data, &npins); + if (ret) + return ret; + + /* + * Refer to linux documentation for details: + * Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt + */ + for (i = 0; i < npins; i++) { + pin_id = pin_data[j++]; + mux = pin_data[j++]; + config_val = pin_data[j++]; + + ret = imx_pinconf_scu_set(info, pin_id, mux, config_val); + if (ret && ret != -EPERM) + printf("Set pin %d, mux %d, val %d, error\n", pin_id, + mux, config_val); + } + + return 0; +} +static struct imx_pinctrl_soc_info imx8_pinctrl_soc_info = { + .flags = IMX8_USE_SCU, +}; + static const struct udevice_id imx8_pinctrl_match[] = { { .compatible = "fsl,imx8qxp-iomuxc", .data = (ulong)&imx8_pinctrl_soc_info }, { .compatible = "fsl,imx8qm-iomuxc", .data = (ulong)&imx8_pinctrl_soc_info }, { /* sentinel */ } }; +static const struct pinctrl_ops imx8_pinctrl_ops = { + .set_state = imx_pinctrl_set_state_scu, +}; + U_BOOT_DRIVER(imx8_pinctrl) = { .name = "imx8_pinctrl", .id = UCLASS_PINCTRL, .of_match = of_match_ptr(imx8_pinctrl_match), - .probe = imx8_pinctrl_probe, - .remove = imx_pinctrl_remove, + .probe = imx_pinctrl_probe_common, .priv_auto = sizeof(struct imx_pinctrl_priv), - .ops = &imx_pinctrl_ops, + .ops = &imx8_pinctrl_ops, .flags = DM_FLAG_PRE_RELOC, }; diff --git a/drivers/pinctrl/nxp/pinctrl-imx8m.c b/drivers/pinctrl/nxp/pinctrl-imx8m.c index 6ea66a080b2..d9c63b3aca6 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx8m.c +++ b/drivers/pinctrl/nxp/pinctrl-imx8m.c @@ -10,14 +10,6 @@ static struct imx_pinctrl_soc_info imx8mq_pinctrl_soc_info __section(".data"); -static int imx8mq_pinctrl_probe(struct udevice *dev) -{ - struct imx_pinctrl_soc_info *info = - (struct imx_pinctrl_soc_info *)dev_get_driver_data(dev); - - return imx_pinctrl_probe(dev, info); -} - static const struct udevice_id imx8m_pinctrl_match[] = { { .compatible = "fsl,imx8mq-iomuxc", .data = (ulong)&imx8mq_pinctrl_soc_info }, { .compatible = "fsl,imx8mm-iomuxc", .data = (ulong)&imx8mq_pinctrl_soc_info }, @@ -26,13 +18,17 @@ static const struct udevice_id imx8m_pinctrl_match[] = { { /* sentinel */ } }; +static const struct pinctrl_ops imx8m_pinctrl_ops = { + .set_state = imx_pinctrl_set_state_mmio, +}; + U_BOOT_DRIVER(imx8mq_pinctrl) = { .name = "imx8mq-pinctrl", .id = UCLASS_PINCTRL, .of_match = of_match_ptr(imx8m_pinctrl_match), - .probe = imx8mq_pinctrl_probe, - .remove = imx_pinctrl_remove, + .probe = imx_pinctrl_probe_mmio, + .remove = imx_pinctrl_remove_mmio, .priv_auto = sizeof(struct imx_pinctrl_priv), - .ops = &imx_pinctrl_ops, + .ops = &imx8m_pinctrl_ops, .flags = DM_FLAG_PRE_RELOC, }; diff --git a/drivers/pinctrl/nxp/pinctrl-imx8ulp.c b/drivers/pinctrl/nxp/pinctrl-imx8ulp.c index 73d3c009d5b..2df63625191 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx8ulp.c +++ b/drivers/pinctrl/nxp/pinctrl-imx8ulp.c @@ -17,27 +17,23 @@ static struct imx_pinctrl_soc_info imx8ulp_pinctrl_soc_info1 = { .flags = ZERO_OFFSET_VALID | SHARE_MUX_CONF_REG | CFG_IBE_OBE, }; -static int imx8ulp_pinctrl_probe(struct udevice *dev) -{ - struct imx_pinctrl_soc_info *info = - (struct imx_pinctrl_soc_info *)dev_get_driver_data(dev); - - return imx_pinctrl_probe(dev, info); -} - static const struct udevice_id imx8ulp_pinctrl_match[] = { { .compatible = "fsl,imx8ulp-iomuxc0", .data = (ulong)&imx8ulp_pinctrl_soc_info0 }, { .compatible = "fsl,imx8ulp-iomuxc1", .data = (ulong)&imx8ulp_pinctrl_soc_info1 }, { /* sentinel */ } }; +static const struct pinctrl_ops imx8ulp_pinctrl_ops = { + .set_state = imx_pinctrl_set_state_mmio, +}; + U_BOOT_DRIVER(imx8ulp_pinctrl) = { .name = "imx8ulp-pinctrl", .id = UCLASS_PINCTRL, .of_match = of_match_ptr(imx8ulp_pinctrl_match), - .probe = imx8ulp_pinctrl_probe, - .remove = imx_pinctrl_remove, + .probe = imx_pinctrl_probe_mmio, + .remove = imx_pinctrl_remove_mmio, .priv_auto = sizeof(struct imx_pinctrl_priv), - .ops = &imx_pinctrl_ops, + .ops = &imx8ulp_pinctrl_ops, .flags = DM_FLAG_PRE_RELOC, }; diff --git a/drivers/pinctrl/nxp/pinctrl-imx93.c b/drivers/pinctrl/nxp/pinctrl-imx93.c index 8d8ffec6d9a..5d250db1081 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx93.c +++ b/drivers/pinctrl/nxp/pinctrl-imx93.c @@ -12,27 +12,23 @@ static struct imx_pinctrl_soc_info imx93_pinctrl_soc_info __section(".data") = { .flags = ZERO_OFFSET_VALID, }; -static int imx93_pinctrl_probe(struct udevice *dev) -{ - struct imx_pinctrl_soc_info *info = - (struct imx_pinctrl_soc_info *)dev_get_driver_data(dev); - - return imx_pinctrl_probe(dev, info); -} - static const struct udevice_id imx93_pinctrl_match[] = { { .compatible = "fsl,imx93-iomuxc", .data = (ulong)&imx93_pinctrl_soc_info }, { .compatible = "fsl,imx91-iomuxc", .data = (ulong)&imx93_pinctrl_soc_info }, { /* sentinel */ } }; +static const struct pinctrl_ops imx93_pinctrl_ops = { + .set_state = imx_pinctrl_set_state_mmio, +}; + U_BOOT_DRIVER(imx93_pinctrl) = { .name = "imx93-pinctrl", .id = UCLASS_PINCTRL, .of_match = of_match_ptr(imx93_pinctrl_match), - .probe = imx93_pinctrl_probe, - .remove = imx_pinctrl_remove, + .probe = imx_pinctrl_probe_mmio, + .remove = imx_pinctrl_remove_mmio, .priv_auto = sizeof(struct imx_pinctrl_priv), - .ops = &imx_pinctrl_ops, + .ops = &imx93_pinctrl_ops, .flags = DM_FLAG_PRE_RELOC, }; diff --git a/drivers/pinctrl/nxp/pinctrl-imxrt.c b/drivers/pinctrl/nxp/pinctrl-imxrt.c index 23f07f8d1e0..39000ceb923 100644 --- a/drivers/pinctrl/nxp/pinctrl-imxrt.c +++ b/drivers/pinctrl/nxp/pinctrl-imxrt.c @@ -13,27 +13,23 @@ static struct imx_pinctrl_soc_info imxrt_pinctrl_soc_info = { .flags = ZERO_OFFSET_VALID, }; -static int imxrt_pinctrl_probe(struct udevice *dev) -{ - struct imx_pinctrl_soc_info *info = - (struct imx_pinctrl_soc_info *)dev_get_driver_data(dev); - - return imx_pinctrl_probe(dev, info); -} - static const struct udevice_id imxrt_pinctrl_match[] = { { .compatible = "fsl,imxrt-iomuxc", .data = (ulong)&imxrt_pinctrl_soc_info }, { /* sentinel */ } }; +static const struct pinctrl_ops imxrt_pinctrl_ops = { + .set_state = imx_pinctrl_set_state_mmio, +}; + U_BOOT_DRIVER(imxrt_pinctrl) = { .name = "imxrt-pinctrl", .id = UCLASS_PINCTRL, .of_match = of_match_ptr(imxrt_pinctrl_match), - .probe = imxrt_pinctrl_probe, - .remove = imx_pinctrl_remove, + .probe = imx_pinctrl_probe_mmio, + .remove = imx_pinctrl_remove_mmio, .priv_auto = sizeof(struct imx_pinctrl_priv), - .ops = &imx_pinctrl_ops, + .ops = &imxrt_pinctrl_ops, .flags = DM_FLAG_PRE_RELOC, }; diff --git a/drivers/pinctrl/nxp/pinctrl-scu.c b/drivers/pinctrl/nxp/pinctrl-scu.c deleted file mode 100644 index 42d5c96468c..00000000000 --- a/drivers/pinctrl/nxp/pinctrl-scu.c +++ /dev/null @@ -1,70 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2018-2019 NXP - */ - -#include <errno.h> -#include <linux/bitops.h> -#include <asm/io.h> -#include <firmware/imx/sci/sci.h> -#include <misc.h> - -#include "pinctrl-imx.h" - -#define PADRING_IFMUX_EN_SHIFT 31 -#define PADRING_IFMUX_EN_MASK BIT(31) -#define PADRING_GP_EN_SHIFT 30 -#define PADRING_GP_EN_MASK BIT(30) -#define PADRING_IFMUX_SHIFT 27 -#define PADRING_IFMUX_MASK GENMASK(29, 27) - -static int imx_pinconf_scu_set(struct imx_pinctrl_soc_info *info, u32 pad, - u32 mux, u32 val) -{ - int ret; - - /* - * Mux should be done in pmx set, but we do not have a good api - * to handle that in scfw, so config it in pad conf func - */ - - if (!sc_rm_is_pad_owned(-1, pad)) { - debug("Pad[%u] is not owned by curr partition\n", pad); - return -EPERM; - } - - val |= PADRING_IFMUX_EN_MASK; - val |= PADRING_GP_EN_MASK; - val |= (mux << PADRING_IFMUX_SHIFT) & PADRING_IFMUX_MASK; - - ret = sc_pad_set(-1, pad, val); - if (ret) - printf("%s %d\n", __func__, ret); - - return 0; -} - -int imx_pinctrl_scu_conf_pins(struct imx_pinctrl_soc_info *info, u32 *pin_data, - int npins) -{ - int pin_id, mux, config_val; - int i, j = 0; - int ret; - - /* - * Refer to linux documentation for details: - * Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt - */ - for (i = 0; i < npins; i++) { - pin_id = pin_data[j++]; - mux = pin_data[j++]; - config_val = pin_data[j++]; - - ret = imx_pinconf_scu_set(info, pin_id, mux, config_val); - if (ret && ret != -EPERM) - printf("Set pin %d, mux %d, val %d, error\n", pin_id, - mux, config_val); - } - - return 0; -} diff --git a/drivers/pinctrl/nxp/pinctrl-vf610.c b/drivers/pinctrl/nxp/pinctrl-vf610.c index adf3073f1be..cbff8dcefd8 100644 --- a/drivers/pinctrl/nxp/pinctrl-vf610.c +++ b/drivers/pinctrl/nxp/pinctrl-vf610.c @@ -13,27 +13,23 @@ static struct imx_pinctrl_soc_info vf610_pinctrl_soc_info = { .flags = SHARE_MUX_CONF_REG | ZERO_OFFSET_VALID, }; -static int vf610_pinctrl_probe(struct udevice *dev) -{ - struct imx_pinctrl_soc_info *info = - (struct imx_pinctrl_soc_info *)dev_get_driver_data(dev); - - return imx_pinctrl_probe(dev, info); -} - static const struct udevice_id vf610_pinctrl_match[] = { { .compatible = "fsl,vf610-iomuxc", .data = (ulong)&vf610_pinctrl_soc_info }, { /* sentinel */ } }; +static const struct pinctrl_ops vf610_pinctrl_ops = { + .set_state = imx_pinctrl_set_state_mmio, +}; + U_BOOT_DRIVER(vf610_pinctrl) = { .name = "vf610-pinctrl", .id = UCLASS_PINCTRL, .of_match = of_match_ptr(vf610_pinctrl_match), - .probe = vf610_pinctrl_probe, - .remove = imx_pinctrl_remove, + .probe = imx_pinctrl_probe_mmio, + .remove = imx_pinctrl_remove_mmio, .priv_auto = sizeof(struct imx_pinctrl_priv), - .ops = &imx_pinctrl_ops, + .ops = &vf610_pinctrl_ops, .flags = DM_FLAG_PRE_RELOC, }; diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index 4f93a34281d..d3eb6998551 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -83,6 +83,13 @@ config PINCTRL_QCOM_SM8650 Say Y here to enable support for pinctrl on the Snapdragon SM8650 SoC, as well as the associated GPIO driver. +config PINCTRL_QCOM_X1E80100 + bool "Qualcomm X1E80100 GCC" + select PINCTRL_QCOM + help + Say Y here to enable support for pinctrl on the Snapdragon X1E80100 SoC, + as well as the associated GPIO driver. + endmenu endif diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 43d0dd29222..06d3c95f93a 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -14,3 +14,4 @@ obj-$(CONFIG_PINCTRL_QCOM_SM8150) += pinctrl-sm8150.o obj-$(CONFIG_PINCTRL_QCOM_SM8250) += pinctrl-sm8250.o obj-$(CONFIG_PINCTRL_QCOM_SM8550) += pinctrl-sm8550.o obj-$(CONFIG_PINCTRL_QCOM_SM8650) += pinctrl-sm8650.o +obj-$(CONFIG_PINCTRL_QCOM_X1E80100) += pinctrl-x1e80100.o diff --git a/drivers/pinctrl/qcom/pinctrl-sm8550.c b/drivers/pinctrl/qcom/pinctrl-sm8550.c index c65dfe0435e..25b972a6d82 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8550.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8550.c @@ -16,6 +16,7 @@ static char pin_name[MAX_PIN_NAME_LEN] __section(".data"); static const struct pinctrl_function msm_pinctrl_functions[] = { {"qup1_se7", 1}, {"gpio", 0}, + {"pcie1_clk_req_n", 1}, }; #define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ diff --git a/drivers/pinctrl/qcom/pinctrl-sm8650.c b/drivers/pinctrl/qcom/pinctrl-sm8650.c index 58fc94e71ac..9146d6abd9a 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8650.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8650.c @@ -16,6 +16,8 @@ static char pin_name[MAX_PIN_NAME_LEN] __section(".data"); static const struct pinctrl_function msm_pinctrl_functions[] = { {"qup2_se7", 1}, {"gpio", 0}, + {"pcie0_clk_req_n", 1}, + {"pcie1_clk_req_n", 1}, }; #define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ diff --git a/drivers/pinctrl/qcom/pinctrl-x1e80100.c b/drivers/pinctrl/qcom/pinctrl-x1e80100.c new file mode 100644 index 00000000000..f39dc426d68 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-x1e80100.c @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Qualcomm x1e80100 pinctrl + * + * (C) Copyright 2024 Linaro Ltd. + * + */ + +#include <dm.h> + +#include "pinctrl-qcom.h" + +#define MAX_PIN_NAME_LEN 32 +static char pin_name[MAX_PIN_NAME_LEN] __section(".data"); + +static const struct pinctrl_function msm_pinctrl_functions[] = { + {"qup2_se5", 1}, + {"pcie3_clk", 1}, + {"pcie4_clk", 1}, + {"pcie5_clk", 1}, + {"pcie6a_clk", 1}, + {"pcie6b_clk", 1}, + {"gpio", 0}, +}; + +#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .name = pg_name, \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + } + +#define UFS_RESET(pg_name, ctl) \ + { \ + .name = pg_name, \ + .ctl_reg = ctl, \ + .io_reg = ctl + 0x4, \ + .pull_bit = 3, \ + .drv_bit = 0, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = 0, \ + } + +static const struct msm_special_pin_data msm_special_pins_data[] = { + [0] = UFS_RESET("ufs_reset", 0xf9000), + [1] = SDC_QDSD_PINGROUP("sdc2_clk", 0xf2000, 14, 6), + [2] = SDC_QDSD_PINGROUP("sdc2_cmd", 0xf2000, 11, 3), + [3] = SDC_QDSD_PINGROUP("sdc2_data", 0xf2000, 9, 0), +}; + +static const char *x1e80100_get_function_name(struct udevice *dev, + unsigned int selector) +{ + return msm_pinctrl_functions[selector].name; +} + +static const char *x1e80100_get_pin_name(struct udevice *dev, + unsigned int selector) +{ + if (selector >= 238 && selector <= 241) + snprintf(pin_name, MAX_PIN_NAME_LEN, + msm_special_pins_data[selector - 238].name); + else + snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector); + + return pin_name; +} + +static unsigned int x1e80100_get_function_mux(__maybe_unused unsigned int pin, + unsigned int selector) +{ + return msm_pinctrl_functions[selector].val; +} + +static struct msm_pinctrl_data x1e80100_data = { + .pin_data = { + .pin_count = 242, + .special_pins_start = 238, + .special_pins_data = msm_special_pins_data, + }, + .functions_count = ARRAY_SIZE(msm_pinctrl_functions), + .get_function_name = x1e80100_get_function_name, + .get_function_mux = x1e80100_get_function_mux, + .get_pin_name = x1e80100_get_pin_name, +}; + +static const struct udevice_id msm_pinctrl_ids[] = { + { .compatible = "qcom,x1e80100-tlmm", .data = (ulong)&x1e80100_data }, + { /* Sentinel */ } +}; + +U_BOOT_DRIVER(pinctrl_x1e80100) = { + .name = "pinctrl_x1e80100", + .id = UCLASS_NOP, + .of_match = msm_pinctrl_ids, + .ops = &msm_pinctrl_ops, + .bind = msm_pinctrl_bind, +}; + diff --git a/drivers/pinctrl/starfive/pinctrl-starfive.c b/drivers/pinctrl/starfive/pinctrl-starfive.c index 95b1a752de2..1b942e6f045 100644 --- a/drivers/pinctrl/starfive/pinctrl-starfive.c +++ b/drivers/pinctrl/starfive/pinctrl-starfive.c @@ -348,7 +348,7 @@ static const struct dm_gpio_ops starfive_gpio_ops = { .set_value = starfive_gpio_set_value, }; -static struct driver starfive_gpio_driver = { +U_BOOT_DRIVER(starfive_gpio) = { .name = "starfive_gpio", .id = UCLASS_GPIO, .probe = starfive_gpio_probe, @@ -367,7 +367,7 @@ static int starfive_gpiochip_register(struct udevice *parent) return -ENOENT; node = dev_ofnode(parent); - ret = device_bind_with_driver_data(parent, &starfive_gpio_driver, + ret = device_bind_with_driver_data(parent, DM_DRIVER_REF(starfive_gpio), "starfive_gpio", 0, node, &dev); return (ret == 0) ? 0 : ret; diff --git a/drivers/power/pmic/tps65941.c b/drivers/power/pmic/tps65941.c index c3490db2a08..57d470521fc 100644 --- a/drivers/power/pmic/tps65941.c +++ b/drivers/power/pmic/tps65941.c @@ -74,7 +74,7 @@ static const struct udevice_id tps65941_ids[] = { { .compatible = "ti,tps659412", .data = TPS659411 }, { .compatible = "ti,tps659413", .data = TPS659413 }, { .compatible = "ti,lp876441", .data = LP876441 }, - { .compatible = "ti,tps65224", .data = TPS65224 }, + { .compatible = "ti,tps65224-q1", .data = TPS65224 }, { .compatible = "ti,tps6594-q1", .data = TPS659411 }, { .compatible = "ti,tps6593-q1", .data = TPS659413 }, { .compatible = "ti,lp8764-q1", .data = LP876441 }, diff --git a/drivers/power/regulator/qcom-rpmh-regulator.c b/drivers/power/regulator/qcom-rpmh-regulator.c index 2dc261d83e3..70df51b5fa4 100644 --- a/drivers/power/regulator/qcom-rpmh-regulator.c +++ b/drivers/power/regulator/qcom-rpmh-regulator.c @@ -536,6 +536,21 @@ static const struct rpmh_vreg_init_data pm8550ve_vreg_data[] = { {} }; +static const struct rpmh_vreg_init_data pmc8380_vreg_data[] = { + RPMH_VREG("smps1", "smp%s1", &pmic5_ftsmps525_lv, "vdd-s1"), + RPMH_VREG("smps2", "smp%s2", &pmic5_ftsmps525_lv, "vdd-s2"), + RPMH_VREG("smps3", "smp%s3", &pmic5_ftsmps525_lv, "vdd-s3"), + RPMH_VREG("smps4", "smp%s4", &pmic5_ftsmps525_mv, "vdd-s4"), + RPMH_VREG("smps5", "smp%s5", &pmic5_ftsmps525_lv, "vdd-s5"), + RPMH_VREG("smps6", "smp%s6", &pmic5_ftsmps525_lv, "vdd-s6"), + RPMH_VREG("smps7", "smp%s7", &pmic5_ftsmps525_lv, "vdd-s7"), + RPMH_VREG("smps8", "smp%s8", &pmic5_ftsmps525_lv, "vdd-s8"), + RPMH_VREG("ldo1", "ldo%s1", &pmic5_nldo515, "vdd-l1"), + RPMH_VREG("ldo2", "ldo%s2", &pmic5_nldo515, "vdd-l2"), + RPMH_VREG("ldo3", "ldo%s3", &pmic5_nldo515, "vdd-l3"), + {} +}; + /* probe an individual regulator */ static int rpmh_regulator_probe(struct udevice *dev) { @@ -662,6 +677,10 @@ static const struct udevice_id rpmh_regulator_ids[] = { .compatible = "qcom,pm8550vs-rpmh-regulators", .data = (ulong)pm8550vs_vreg_data, }, + { + .compatible = "qcom,pmc8380-rpmh-regulators", + .data = (ulong)pmc8380_vreg_data, + }, { /* sentinal */ }, }; diff --git a/drivers/power/regulator/tps65219_regulator.c b/drivers/power/regulator/tps65219_regulator.c index b7124fed024..88abc896b3a 100644 --- a/drivers/power/regulator/tps65219_regulator.c +++ b/drivers/power/regulator/tps65219_regulator.c @@ -72,12 +72,12 @@ static int tps65219_buck_enable(struct udevice *dev, int op, bool *enable) static int tps65219_buck_volt2val(int uV) { - if (uV > TPS65219_BUCK_VOLT_MAX) + if (uV > TPS65219_BUCK_3V4) return -EINVAL; - else if (uV >= 1400000) - return (uV - 1400000) / 100000 + 0x20; - else if (uV >= 600000) - return (uV - 600000) / 25000 + 0x00; + else if (uV >= TPS65219_BUCK_1V4) + return (uV - TPS65219_BUCK_1V4) / TPS65219_VOLT_STEP_100MV + TPS65219_BUCK_REG_1V4; + else if (uV >= TPS65219_BUCK_0V6) + return (uV - TPS65219_BUCK_0V6) / TPS65219_VOLT_STEP_25MV + TPS65219_BUCK_REG_0V6; else return -EINVAL; } @@ -86,12 +86,12 @@ static int tps65219_buck_val2volt(int val) { if (val > TPS65219_VOLT_MASK) return -EINVAL; - else if (val > 0x34) - return TPS65219_BUCK_VOLT_MAX; - else if (val > 0x20) - return 1400000 + (val - 0x20) * 100000; - else if (val >= 0) - return 600000 + val * 25000; + else if (val > TPS65219_BUCK_REG_3V4) + return TPS65219_BUCK_3V4; + else if (val > TPS65219_BUCK_REG_1V4) + return TPS65219_BUCK_1V4 + (val - TPS65219_BUCK_REG_1V4) * TPS65219_VOLT_STEP_100MV; + else if (val >= TPS65219_BUCK_REG_0V6) + return TPS65219_BUCK_0V6 + val * TPS65219_VOLT_STEP_25MV; else return -EINVAL; } @@ -161,7 +161,7 @@ static int tps65219_ldo_volt2val(int idx, int uV) if (uV > max) return -EINVAL; else if (uV >= base) - return (uV - TPS65219_LDO12_VOLT_MIN) / 50000; + return (uV - TPS65219_LDO12_VOLT_MIN) / TPS65219_VOLT_STEP_50MV; else return -EINVAL; } @@ -187,7 +187,7 @@ static int tps65219_ldo_val2volt(int idx, int val) else if (val <= reg_base) return base; else if (val >= 0) - return TPS65219_LDO12_VOLT_MIN + (50000 * val); + return TPS65219_LDO12_VOLT_MIN + (TPS65219_VOLT_STEP_50MV * val); else return -EINVAL; } @@ -250,7 +250,7 @@ static int tps65219_ldo_probe(struct udevice *dev) /* idx must be in 1..TPS65219_LDO_NUM */ idx = dev->driver_data; if (idx < 1 || idx > TPS65219_LDO_NUM) { - printf("Wrong ID for regulator\n"); + pr_err("Wrong ID for regulator\n"); return -EINVAL; } @@ -271,7 +271,7 @@ static int tps65219_buck_probe(struct udevice *dev) /* idx must be in 1..TPS65219_BUCK_NUM */ idx = dev->driver_data; if (idx < 1 || idx > TPS65219_BUCK_NUM) { - printf("Wrong ID for regulator\n"); + pr_err("Wrong ID for regulator\n"); return -EINVAL; } diff --git a/drivers/pwm/pwm-mtk.c b/drivers/pwm/pwm-mtk.c index 9776a41ff48..5cf2eba2ba0 100644 --- a/drivers/pwm/pwm-mtk.c +++ b/drivers/pwm/pwm-mtk.c @@ -192,7 +192,7 @@ static const struct mtk_pwm_soc mt7629_data = { }; static const struct mtk_pwm_soc mt7981_data = { - .num_pwms = 2, + .num_pwms = 3, .pwm45_fixup = false, .reg_ver = PWM_REG_V2, }; diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig index 2b0cd312883..899d7585489 100644 --- a/drivers/ram/Kconfig +++ b/drivers/ram/Kconfig @@ -116,6 +116,16 @@ config IMXRT_SDRAM to support external memories like sdram, psram & nand. This driver is for the sdram memory interface with the SEMC. +config K3_INLINE_ECC + bool "Enable TI Inline ECC support" + depends on K3_DDRSS + help + Enable Inline ECC support on K3 platforms. 1/9th of the SDRAM space + is used for ECC storage and the rest 8/9th is available for system + use. Enabling ECC increases boot time as the ECC protected regions + need to be primed with a predefined value prior to enabling ECC + check. + source "drivers/ram/aspeed/Kconfig" source "drivers/ram/cadence/Kconfig" source "drivers/ram/octeon/Kconfig" diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c b/drivers/ram/k3-ddrss/k3-ddrss.c index 6e9202b9579..ff87faf6a22 100644 --- a/drivers/ram/k3-ddrss/k3-ddrss.c +++ b/drivers/ram/k3-ddrss/k3-ddrss.c @@ -6,6 +6,7 @@ */ #include <config.h> +#include <time.h> #include <clk.h> #include <div64.h> #include <dm.h> @@ -32,6 +33,12 @@ #define DDRSS_V2A_CTL_REG 0x0020 #define DDRSS_ECC_CTRL_REG 0x0120 +#define DDRSS_V2A_CTL_REG_SDRAM_IDX_CALC(x) ((ilog2(x) - 16) << 5) +#define DDRSS_V2A_CTL_REG_SDRAM_IDX_MASK (~(0x1F << 0x5)) +#define DDRSS_V2A_CTL_REG_REGION_IDX_MASK (~(0X1F)) +#define DDRSS_V2A_CTL_REG_REGION_IDX_DEFAULT 0xF + +#define DDRSS_ECC_CTRL_REG_DEFAULT 0x0 #define DDRSS_ECC_CTRL_REG_ECC_EN BIT(0) #define DDRSS_ECC_CTRL_REG_RMW_EN BIT(1) #define DDRSS_ECC_CTRL_REG_ECC_CK BIT(2) @@ -44,6 +51,11 @@ #define DDRSS_ECC_R2_STR_ADDR_REG 0x0140 #define DDRSS_ECC_R2_END_ADDR_REG 0x0144 #define DDRSS_ECC_1B_ERR_CNT_REG 0x0150 +#define DDRSS_V2A_INT_SET_REG 0x00a8 + +#define DDRSS_V2A_INT_SET_REG_ECC1BERR_EN BIT(3) +#define DDRSS_V2A_INT_SET_REG_ECC2BERR_EN BIT(4) +#define DDRSS_V2A_INT_SET_REG_ECCM1BERR_EN BIT(5) #define SINGLE_DDR_SUBSYSTEM 0x1 #define MULTI_DDR_SUBSYSTEM 0x2 @@ -120,8 +132,8 @@ struct k3_msmc { #define K3_DDRSS_MAX_ECC_REGIONS 3 struct k3_ddrss_ecc_region { - u32 start; - u32 range; + u64 start; + u64 range; }; struct k3_ddrss_desc { @@ -145,7 +157,9 @@ struct k3_ddrss_desc { lpddr4_privatedata pd; struct k3_ddrss_ecc_region ecc_regions[K3_DDRSS_MAX_ECC_REGIONS]; u64 ecc_reserved_space; - bool ti_ecc_enabled; + u64 ddr_bank_base[CONFIG_NR_DRAM_BANKS]; + u64 ddr_bank_size[CONFIG_NR_DRAM_BANKS]; + u64 ddr_ram_size; }; struct reginitdata { @@ -399,8 +413,6 @@ static int k3_ddrss_ofdata_to_priv(struct udevice *dev) if (ret) dev_err(dev, "ddr fhs cnt not populated %d\n", ret); - ddrss->ti_ecc_enabled = dev_read_bool(dev, "ti,ecc-enable"); - return ret; } @@ -542,27 +554,190 @@ void k3_lpddr4_start(struct k3_ddrss_desc *ddrss) } } -static void k3_ddrss_set_ecc_range_r0(u32 base, u32 start_address, u32 size) +static void k3_ddrss_set_ecc_range_r0(u32 base, u64 start_address, u64 size) { writel((start_address) >> 16, base + DDRSS_ECC_R0_STR_ADDR_REG); writel((start_address + size - 1) >> 16, base + DDRSS_ECC_R0_END_ADDR_REG); } -static void k3_ddrss_preload_ecc_mem_region(u32 *addr, u32 size, u32 word) +#define BIST_MODE_MEM_INIT 4 +#define BIST_MEM_INIT_TIMEOUT 10000 /* 1msec loops per block = 10s */ +static void k3_lpddr4_bist_init_mem_region(struct k3_ddrss_desc *ddrss, + u64 addr, u64 size, + u32 pattern) { - int i; + lpddr4_obj *driverdt = ddrss->driverdt; + lpddr4_privatedata *pd = &ddrss->pd; + u32 status, offset, regval; + bool int_status; + int i = 0; + + /* Set BIST_START_ADDR_0 [31:0] */ + regval = (u32)(addr & TH_FLD_MASK(LPDDR4__BIST_START_ADDRESS_0__FLD)); + TH_OFFSET_FROM_REG(LPDDR4__BIST_START_ADDRESS_0__REG, CTL_SHIFT, offset); + driverdt->writereg(pd, LPDDR4_CTL_REGS, offset, regval); + + /* Set BIST_START_ADDR_1 [32 or 34:32] */ + regval = (u32)(addr >> TH_FLD_WIDTH(LPDDR4__BIST_START_ADDRESS_0__FLD)); + regval &= TH_FLD_MASK(LPDDR4__BIST_START_ADDRESS_1__FLD); + TH_OFFSET_FROM_REG(LPDDR4__BIST_START_ADDRESS_1__REG, CTL_SHIFT, offset); + driverdt->writereg(pd, LPDDR4_CTL_REGS, offset, regval); + + /* Set ADDR_SPACE = log2(size) */ + regval = (u32)(ilog2(size) << TH_FLD_SHIFT(LPDDR4__ADDR_SPACE__FLD)); + TH_OFFSET_FROM_REG(LPDDR4__ADDR_SPACE__REG, CTL_SHIFT, offset); + driverdt->writereg(pd, LPDDR4_CTL_REGS, offset, regval); + + /* Enable the BIST data check. On 32bit lpddr4 (e.g J7) this shares a + * register with ADDR_SPACE and BIST_GO. + */ + TH_OFFSET_FROM_REG(LPDDR4__BIST_DATA_CHECK__REG, CTL_SHIFT, offset); + driverdt->readreg(pd, LPDDR4_CTL_REGS, offset, ®val); + regval |= TH_FLD_MASK(LPDDR4__BIST_DATA_CHECK__FLD); + driverdt->writereg(pd, LPDDR4_CTL_REGS, offset, regval); + /* Clear the address check bit */ + TH_OFFSET_FROM_REG(LPDDR4__BIST_ADDR_CHECK__REG, CTL_SHIFT, offset); + driverdt->readreg(pd, LPDDR4_CTL_REGS, offset, ®val); + regval &= ~TH_FLD_MASK(LPDDR4__BIST_ADDR_CHECK__FLD); + driverdt->writereg(pd, LPDDR4_CTL_REGS, offset, regval); + + /* Set BIST_TEST_MODE[2:0] to memory initialize (4) */ + regval = BIST_MODE_MEM_INIT; + TH_OFFSET_FROM_REG(LPDDR4__BIST_TEST_MODE__REG, CTL_SHIFT, offset); + driverdt->writereg(pd, LPDDR4_CTL_REGS, offset, regval); + + /* Set BIST_DATA_PATTERN[31:0] */ + TH_OFFSET_FROM_REG(LPDDR4__BIST_DATA_PATTERN_0__REG, CTL_SHIFT, offset); + driverdt->writereg(pd, LPDDR4_CTL_REGS, offset, pattern); + + /* Set BIST_DATA_PATTERN[63:32] */ + TH_OFFSET_FROM_REG(LPDDR4__BIST_DATA_PATTERN_1__REG, CTL_SHIFT, offset); + driverdt->writereg(pd, LPDDR4_CTL_REGS, offset, pattern); + + udelay(1000); + + /* Enable the programmed BIST operation - BIST_GO = 1 */ + TH_OFFSET_FROM_REG(LPDDR4__BIST_GO__REG, CTL_SHIFT, offset); + driverdt->readreg(pd, LPDDR4_CTL_REGS, offset, ®val); + regval |= TH_FLD_MASK(LPDDR4__BIST_GO__FLD); + driverdt->writereg(pd, LPDDR4_CTL_REGS, offset, regval); + + /* Wait for the BIST_DONE interrupt */ + while (i < BIST_MEM_INIT_TIMEOUT) { + status = driverdt->checkctlinterrupt(pd, LPDDR4_INTR_BIST_DONE, + &int_status); + if (!status & int_status) { + /* Clear LPDDR4_INTR_BIST_DONE */ + driverdt->ackctlinterrupt(pd, LPDDR4_INTR_BIST_DONE); + break; + } + udelay(1000); + i++; + } + + /* Before continuing we have to stop BIST - BIST_GO = 0 */ + TH_OFFSET_FROM_REG(LPDDR4__BIST_GO__REG, CTL_SHIFT, offset); + driverdt->writereg(pd, LPDDR4_CTL_REGS, offset, 0); + /* Timeout hit while priming the memory. We can't continue, + * since the memory is not fully initialized and we most + * likely get an uncorrectable error exception while booting. + */ + if (i == BIST_MEM_INIT_TIMEOUT) { + printf("ERROR: Timeout while priming the memory.\n"); + hang(); + } +} + +static void k3_ddrss_lpddr4_preload_full_mem(struct k3_ddrss_desc *ddrss, + u64 total_size, u32 pattern) +{ + u32 done, max_size2; + + /* Get the max size (log2) supported in this config (16/32 lpddr4) + * from the start_addess width - 16bit: 8G, 32bit: 32G + */ + max_size2 = TH_FLD_WIDTH(LPDDR4__BIST_START_ADDRESS_0__FLD) + + TH_FLD_WIDTH(LPDDR4__BIST_START_ADDRESS_1__FLD) + 1; + + /* ECC is enabled in dt but we can't preload the memory if + * the memory configuration is recognized and supported. + */ + if (!total_size || total_size > (1ull << max_size2) || + total_size & (total_size - 1)) { + printf("ECC: the memory configuration is not supported\n"); + hang(); + } printf("ECC is enabled, priming DDR which will take several seconds.\n"); + done = get_timer(0); + k3_lpddr4_bist_init_mem_region(ddrss, 0, total_size, pattern); + printf("ECC: priming DDR completed in %lu msec\n", get_timer(done)); +} + +static void k3_ddrss_ddr_bank_base_size_calc(struct k3_ddrss_desc *ddrss) +{ + int bank, na, ns, len, parent; + const fdt32_t *ptr, *end; + + for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { + ddrss->ddr_bank_base[bank] = 0; + ddrss->ddr_bank_size[bank] = 0; + } + + ofnode mem = ofnode_null(); - for (i = 0; i < (size / 4); i++) - addr[i] = word; + do { + mem = ofnode_by_prop_value(mem, "device_type", "memory", 7); + } while (!ofnode_is_enabled(mem)); + + const void *fdt = ofnode_to_fdt(mem); + int node = ofnode_to_offset(mem); + const char *property = "reg"; + + parent = fdt_parent_offset(fdt, node); + na = fdt_address_cells(fdt, parent); + ns = fdt_size_cells(fdt, parent); + ptr = fdt_getprop(fdt, node, property, &len); + end = ptr + len / sizeof(*ptr); + + for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { + if (ptr + na + ns <= end) { + if (CONFIG_IS_ENABLED(OF_TRANSLATE)) + ddrss->ddr_bank_base[bank] = fdt_translate_address(fdt, node, ptr); + else + ddrss->ddr_bank_base[bank] = fdtdec_get_number(ptr, na); + + ddrss->ddr_bank_size[bank] = fdtdec_get_number(&ptr[na], ns); + } + + ptr += na + ns; + } + + for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) + ddrss->ddr_ram_size += ddrss->ddr_bank_size[bank]; +} + +static void k3_ddrss_ddr_reg_init(struct k3_ddrss_desc *ddrss) +{ + u32 v2a_ctl_reg, sdram_idx; + + sdram_idx = DDRSS_V2A_CTL_REG_SDRAM_IDX_CALC(ddrss->ddr_ram_size); + v2a_ctl_reg = readl(ddrss->ddrss_ss_cfg + DDRSS_V2A_CTL_REG); + v2a_ctl_reg = (v2a_ctl_reg & DDRSS_V2A_CTL_REG_SDRAM_IDX_MASK) | sdram_idx; + + if (IS_ENABLED(CONFIG_SOC_K3_AM642)) + v2a_ctl_reg = (v2a_ctl_reg & DDRSS_V2A_CTL_REG_REGION_IDX_MASK) | + DDRSS_V2A_CTL_REG_REGION_IDX_DEFAULT; + + writel(v2a_ctl_reg, ddrss->ddrss_ss_cfg + DDRSS_V2A_CTL_REG); + writel(DDRSS_ECC_CTRL_REG_DEFAULT, ddrss->ddrss_ss_cfg + DDRSS_ECC_CTRL_REG); } static void k3_ddrss_lpddr4_ecc_calc_reserved_mem(struct k3_ddrss_desc *ddrss) { fdtdec_setup_mem_size_base_lowest(); - ddrss->ecc_reserved_space = gd->ram_size; + ddrss->ecc_reserved_space = ddrss->ddr_ram_size; do_div(ddrss->ecc_reserved_space, 9); /* Round to clean number */ @@ -571,25 +746,29 @@ static void k3_ddrss_lpddr4_ecc_calc_reserved_mem(struct k3_ddrss_desc *ddrss) static void k3_ddrss_lpddr4_ecc_init(struct k3_ddrss_desc *ddrss) { - u32 ecc_region_start = ddrss->ecc_regions[0].start; - u32 ecc_range = ddrss->ecc_regions[0].range; + u64 ecc_region_start = ddrss->ecc_regions[0].start; + u64 ecc_range = ddrss->ecc_regions[0].range; u32 base = (u32)ddrss->ddrss_ss_cfg; u32 val; /* Only Program region 0 which covers full ddr space */ - k3_ddrss_set_ecc_range_r0(base, ecc_region_start - gd->ram_base, ecc_range); + k3_ddrss_set_ecc_range_r0(base, ecc_region_start - ddrss->ddr_bank_base[0], ecc_range); /* Enable ECC, RMW, WR_ALLOC */ writel(DDRSS_ECC_CTRL_REG_ECC_EN | DDRSS_ECC_CTRL_REG_RMW_EN | DDRSS_ECC_CTRL_REG_WR_ALLOC, base + DDRSS_ECC_CTRL_REG); - /* Preload ECC Mem region with 0's */ - k3_ddrss_preload_ecc_mem_region((u32 *)ecc_region_start, ecc_range, - 0x00000000); + /* Preload the full memory with 0's using the BIST engine of + * the LPDDR4 controller. + */ + k3_ddrss_lpddr4_preload_full_mem(ddrss, ddrss->ddr_ram_size, 0); /* Clear Error Count Register */ writel(0x1, base + DDRSS_ECC_1B_ERR_CNT_REG); + writel(DDRSS_V2A_INT_SET_REG_ECC1BERR_EN | DDRSS_V2A_INT_SET_REG_ECC2BERR_EN | + DDRSS_V2A_INT_SET_REG_ECCM1BERR_EN, base + DDRSS_V2A_INT_SET_REG); + /* Enable ECC Check */ val = readl(base + DDRSS_ECC_CTRL_REG); val |= DDRSS_ECC_CTRL_REG_ECC_CK; @@ -612,11 +791,9 @@ static int k3_ddrss_probe(struct udevice *dev) if (ret) return ret; -#ifdef CONFIG_K3_AM64_DDRSS - /* AM64x supports only up to 2 GB SDRAM */ - writel(0x000001EF, ddrss->ddrss_ss_cfg + DDRSS_V2A_CTL_REG); - writel(0x0, ddrss->ddrss_ss_cfg + DDRSS_ECC_CTRL_REG); -#endif + k3_ddrss_ddr_bank_base_size_calc(ddrss); + + k3_ddrss_ddr_reg_init(ddrss); ddrss->driverdt = lpddr4_getinstance(); @@ -630,7 +807,7 @@ static int k3_ddrss_probe(struct udevice *dev) k3_lpddr4_start(ddrss); - if (ddrss->ti_ecc_enabled) { + if (IS_ENABLED(CONFIG_K3_INLINE_ECC)) { if (!ddrss->ddrss_ss_cfg) { printf("%s: ss_cfg is required if ecc is enabled but not provided.", __func__); @@ -640,8 +817,8 @@ static int k3_ddrss_probe(struct udevice *dev) k3_ddrss_lpddr4_ecc_calc_reserved_mem(ddrss); /* Always configure one region that covers full DDR space */ - ddrss->ecc_regions[0].start = gd->ram_base; - ddrss->ecc_regions[0].range = gd->ram_size - ddrss->ecc_reserved_space; + ddrss->ecc_regions[0].start = ddrss->ddr_bank_base[0]; + ddrss->ecc_regions[0].range = ddrss->ddr_ram_size - ddrss->ecc_reserved_space; k3_ddrss_lpddr4_ecc_init(ddrss); } @@ -650,30 +827,24 @@ static int k3_ddrss_probe(struct udevice *dev) int k3_ddrss_ddr_fdt_fixup(struct udevice *dev, void *blob, struct bd_info *bd) { - struct k3_ddrss_desc *ddrss = dev_get_priv(dev); - u64 start[CONFIG_NR_DRAM_BANKS]; - u64 size[CONFIG_NR_DRAM_BANKS]; int bank; + struct k3_ddrss_desc *ddrss = dev_get_priv(dev); if (ddrss->ecc_reserved_space == 0) return 0; for (bank = CONFIG_NR_DRAM_BANKS - 1; bank >= 0; bank--) { - if (ddrss->ecc_reserved_space > bd->bi_dram[bank].size) { - ddrss->ecc_reserved_space -= bd->bi_dram[bank].size; - bd->bi_dram[bank].size = 0; + if (ddrss->ecc_reserved_space > ddrss->ddr_bank_size[bank]) { + ddrss->ecc_reserved_space -= ddrss->ddr_bank_size[bank]; + ddrss->ddr_bank_size[bank] = 0; } else { - bd->bi_dram[bank].size -= ddrss->ecc_reserved_space; + ddrss->ddr_bank_size[bank] -= ddrss->ecc_reserved_space; break; } } - for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - start[bank] = bd->bi_dram[bank].start; - size[bank] = bd->bi_dram[bank].size; - } - - return fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS); + return fdt_fixup_memory_banks(blob, ddrss->ddr_bank_base, + ddrss->ddr_bank_size, CONFIG_NR_DRAM_BANKS); } static int k3_ddrss_get_info(struct udevice *dev, struct ram_info *info) diff --git a/drivers/remoteproc/renesas_apmu.c b/drivers/remoteproc/renesas_apmu.c index 32d138e6487..1a50cd3289b 100644 --- a/drivers/remoteproc/renesas_apmu.c +++ b/drivers/remoteproc/renesas_apmu.c @@ -68,6 +68,13 @@ static int renesas_apmu_rproc_load(struct udevice *dev, ulong addr, ulong size) flush_dcache_range(trampolineaddr, trampolineaddr + sizeof(renesas_apmu_rproc_trampoline)); + invalidate_dcache_range(trampolineaddr, + trampolineaddr + + sizeof(renesas_apmu_rproc_trampoline)); + flush_dcache_range(addr, addr + size); + invalidate_dcache_range(addr, addr + size); + asm volatile("dsb sy\n"); + asm volatile("isb sy\n"); /* CR52 boot address set */ writel(trampolineaddr | APMU_CRBARP_CR_VLD_BARP, diff --git a/drivers/rng/msm_rng.c b/drivers/rng/msm_rng.c index 658c153d3ed..f790d3b60f9 100644 --- a/drivers/rng/msm_rng.c +++ b/drivers/rng/msm_rng.c @@ -34,6 +34,7 @@ struct msm_rng_priv { phys_addr_t base; struct clk clk; + bool skip_init; }; static int msm_rng_read(struct udevice *dev, void *data, size_t len) @@ -100,10 +101,15 @@ static int msm_rng_probe(struct udevice *dev) int ret; + priv->skip_init = (bool)dev_get_driver_data(dev); + priv->base = dev_read_addr(dev); if (priv->base == FDT_ADDR_T_NONE) return -EINVAL; + if (priv->skip_init) + return 0; + ret = clk_get_by_index(dev, 0, &priv->clk); if (ret) return ret; @@ -119,6 +125,9 @@ static int msm_rng_remove(struct udevice *dev) { struct msm_rng_priv *priv = dev_get_priv(dev); + if (priv->skip_init) + return 0; + return msm_rng_enable(priv, 0); } @@ -127,7 +136,9 @@ static const struct dm_rng_ops msm_rng_ops = { }; static const struct udevice_id msm_rng_match[] = { - { .compatible = "qcom,prng", }, + { .compatible = "qcom,prng", .data = (ulong)false }, + { .compatible = "qcom,prng-ee", .data = (ulong)true }, + { .compatible = "qcom,trng", .data = (ulong)true }, {}, }; diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 9c2d1398247..6467f20422b 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -294,7 +294,7 @@ config RTC_DAVINCI config RTC_ZYNQMP bool "Enable ZynqMP RTC driver" - depends on ARCH_ZYNQMP + depends on DM_RTC && (ARCH_ZYNQMP || ARCH_VERSAL || ARCH_VERSAL_NET || ARCH_VERSAL2) help Say "yes" here to support the on chip real time clock present on Xilinx ZynqMP SoC. diff --git a/drivers/rtc/emul_rtc.c b/drivers/rtc/emul_rtc.c index 97a8d9bb7df..6817daad18f 100644 --- a/drivers/rtc/emul_rtc.c +++ b/drivers/rtc/emul_rtc.c @@ -58,7 +58,7 @@ static int emul_rtc_set(struct udevice *dev, const struct rtc_time *time) return 0; } -int emul_rtc_probe(struct udevice *dev) +static int emul_rtc_probe(struct udevice *dev) { struct emul_rtc *priv = dev_get_priv(dev); const char *epoch_str; diff --git a/drivers/rtc/max313xx.c b/drivers/rtc/max313xx.c index 60400235dd0..2cb3f245041 100644 --- a/drivers/rtc/max313xx.c +++ b/drivers/rtc/max313xx.c @@ -285,7 +285,7 @@ static int max313xx_set_time(struct udevice *dev, const struct rtc_time *t) regs[5] = bin2bcd(t->tm_mon); regs[6] = bin2bcd((t->tm_year - 2000) % 100); - if ((t->tm_year - 2000) >= 200) + if (t->tm_year >= 2100) regs[5] |= FIELD_PREP(MAX313XX_MONTH_CENTURY, 1); ret = dm_i2c_write(dev, rtc->chip->sec_reg, regs, 7); @@ -308,6 +308,11 @@ static int max313xx_set_time(struct udevice *dev, const struct rtc_time *t) return ret; break; + case ID_MAX31343: + /* Time is not updated for 1 second after writing */ + /* Sleep here so the date command shows the new time */ + mdelay(1000); + break; default: break; } diff --git a/drivers/scsi/Kconfig b/drivers/scsi/Kconfig index 7e21c4ae2bb..fc87d34cca3 100644 --- a/drivers/scsi/Kconfig +++ b/drivers/scsi/Kconfig @@ -1,5 +1,6 @@ config SCSI bool "Support SCSI controllers with driver model" + select BLK help This enables support for SCSI (Small Computer System Interface), a parallel interface widely used with storage peripherals such as diff --git a/drivers/scsi/scsi.c b/drivers/scsi/scsi.c index bcdeda95ed1..cd0b84c0622 100644 --- a/drivers/scsi/scsi.c +++ b/drivers/scsi/scsi.c @@ -38,7 +38,7 @@ void scsi_setup_read16(struct scsi_cmd *pccb, lbaint_t start, unsigned long blocks) { pccb->cmd[0] = SCSI_READ16; - pccb->cmd[1] = pccb->lun << 5; + pccb->cmd[1] = 0; pccb->cmd[2] = (unsigned char)(start >> 56) & 0xff; pccb->cmd[3] = (unsigned char)(start >> 48) & 0xff; pccb->cmd[4] = (unsigned char)(start >> 40) & 0xff; @@ -66,7 +66,7 @@ void scsi_setup_read16(struct scsi_cmd *pccb, lbaint_t start, static void scsi_setup_inquiry(struct scsi_cmd *pccb) { pccb->cmd[0] = SCSI_INQUIRY; - pccb->cmd[1] = pccb->lun << 5; + pccb->cmd[1] = 0; pccb->cmd[2] = 0; pccb->cmd[3] = 0; if (pccb->datalen > 255) @@ -82,7 +82,7 @@ static void scsi_setup_read_ext(struct scsi_cmd *pccb, lbaint_t start, unsigned short blocks) { pccb->cmd[0] = SCSI_READ10; - pccb->cmd[1] = pccb->lun << 5; + pccb->cmd[1] = 0; pccb->cmd[2] = (unsigned char)(start >> 24) & 0xff; pccb->cmd[3] = (unsigned char)(start >> 16) & 0xff; pccb->cmd[4] = (unsigned char)(start >> 8) & 0xff; @@ -103,7 +103,7 @@ static void scsi_setup_write_ext(struct scsi_cmd *pccb, lbaint_t start, unsigned short blocks) { pccb->cmd[0] = SCSI_WRITE10; - pccb->cmd[1] = pccb->lun << 5; + pccb->cmd[1] = 0; pccb->cmd[2] = (unsigned char)(start >> 24) & 0xff; pccb->cmd[3] = (unsigned char)(start >> 16) & 0xff; pccb->cmd[4] = (unsigned char)(start >> 8) & 0xff; @@ -289,7 +289,7 @@ static int scsi_read_capacity(struct udevice *dev, struct scsi_cmd *pccb, memset(pccb->cmd, '\0', sizeof(pccb->cmd)); pccb->cmd[0] = SCSI_RD_CAPAC10; - pccb->cmd[1] = pccb->lun << 5; + pccb->cmd[1] = 0; pccb->cmdlen = 10; pccb->dma_dir = DMA_FROM_DEVICE; pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */ @@ -353,7 +353,7 @@ static int scsi_read_capacity(struct udevice *dev, struct scsi_cmd *pccb, static void scsi_setup_test_unit_ready(struct scsi_cmd *pccb) { pccb->cmd[0] = SCSI_TST_U_RDY; - pccb->cmd[1] = pccb->lun << 5; + pccb->cmd[1] = 0; pccb->cmd[2] = 0; pccb->cmd[3] = 0; pccb->cmd[4] = 0; diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index c3b884b6d00..0e267d097c5 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -464,7 +464,7 @@ int ns16550_serial_getinfo(struct udevice *dev, struct serial_device_info *info) struct ns16550_plat *plat = com_port->plat; /* save code size */ - if (!not_xpl()) + if (!not_xpl() && !CONFIG_IS_ENABLED(UPL_OUT)) return -ENOSYS; info->type = SERIAL_CHIP_16550_COMPATIBLE; @@ -605,6 +605,7 @@ static const struct udevice_id ns16550_serial_ids[] = { { .compatible = "ingenic,jz4780-uart", .data = PORT_JZ4780 }, { .compatible = "nvidia,tegra20-uart", .data = PORT_NS16550 }, { .compatible = "snps,dw-apb-uart", .data = PORT_NS16550 }, + { .compatible = "intel,xscale-uart", .data = PORT_NS16550 }, {} }; #endif /* OF_REAL */ diff --git a/drivers/spi/atmel_spi.h b/drivers/spi/atmel_spi.h deleted file mode 100644 index 9663cca5e66..00000000000 --- a/drivers/spi/atmel_spi.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - * Register definitions for the Atmel AT32/AT91 SPI Controller - */ - -/* Register offsets */ -#include <linux/bitops.h> -#define ATMEL_SPI_CR 0x0000 -#define ATMEL_SPI_MR 0x0004 -#define ATMEL_SPI_RDR 0x0008 -#define ATMEL_SPI_TDR 0x000c -#define ATMEL_SPI_SR 0x0010 -#define ATMEL_SPI_IER 0x0014 -#define ATMEL_SPI_IDR 0x0018 -#define ATMEL_SPI_IMR 0x001c -#define ATMEL_SPI_CSR(x) (0x0030 + 4 * (x)) -#define ATMEL_SPI_VERSION 0x00fc - -/* Bits in CR */ -#define ATMEL_SPI_CR_SPIEN BIT(0) -#define ATMEL_SPI_CR_SPIDIS BIT(1) -#define ATMEL_SPI_CR_SWRST BIT(7) -#define ATMEL_SPI_CR_LASTXFER BIT(24) - -/* Bits in MR */ -#define ATMEL_SPI_MR_MSTR BIT(0) -#define ATMEL_SPI_MR_PS BIT(1) -#define ATMEL_SPI_MR_PCSDEC BIT(2) -#define ATMEL_SPI_MR_FDIV BIT(3) -#define ATMEL_SPI_MR_MODFDIS BIT(4) -#define ATMEL_SPI_MR_WDRBT BIT(5) -#define ATMEL_SPI_MR_LLB BIT(7) -#define ATMEL_SPI_MR_PCS(x) (((x) & 15) << 16) -#define ATMEL_SPI_MR_DLYBCS(x) ((x) << 24) - -/* Bits in RDR */ -#define ATMEL_SPI_RDR_RD(x) (x) -#define ATMEL_SPI_RDR_PCS(x) ((x) << 16) - -/* Bits in TDR */ -#define ATMEL_SPI_TDR_TD(x) (x) -#define ATMEL_SPI_TDR_PCS(x) ((x) << 16) -#define ATMEL_SPI_TDR_LASTXFER BIT(24) - -/* Bits in SR/IER/IDR/IMR */ -#define ATMEL_SPI_SR_RDRF BIT(0) -#define ATMEL_SPI_SR_TDRE BIT(1) -#define ATMEL_SPI_SR_MODF BIT(2) -#define ATMEL_SPI_SR_OVRES BIT(3) -#define ATMEL_SPI_SR_ENDRX BIT(4) -#define ATMEL_SPI_SR_ENDTX BIT(5) -#define ATMEL_SPI_SR_RXBUFF BIT(6) -#define ATMEL_SPI_SR_TXBUFE BIT(7) -#define ATMEL_SPI_SR_NSSR BIT(8) -#define ATMEL_SPI_SR_TXEMPTY BIT(9) -#define ATMEL_SPI_SR_SPIENS BIT(16) - -/* Bits in CSRx */ -#define ATMEL_SPI_CSRx_CPOL BIT(0) -#define ATMEL_SPI_CSRx_NCPHA BIT(1) -#define ATMEL_SPI_CSRx_CSAAT BIT(3) -#define ATMEL_SPI_CSRx_BITS(x) ((x) << 4) -#define ATMEL_SPI_CSRx_SCBR(x) ((x) << 8) -#define ATMEL_SPI_CSRx_SCBR_MAX GENMASK(7, 0) -#define ATMEL_SPI_CSRx_DLYBS(x) ((x) << 16) -#define ATMEL_SPI_CSRx_DLYBCT(x) ((x) << 24) - -/* Bits in VERSION */ -#define ATMEL_SPI_VERSION_REV(x) ((x) & 0xfff) -#define ATMEL_SPI_VERSION_MFN(x) ((x) << 16) - -/* Constants for CSRx:BITS */ -#define ATMEL_SPI_BITS_8 0 -#define ATMEL_SPI_BITS_9 1 -#define ATMEL_SPI_BITS_10 2 -#define ATMEL_SPI_BITS_11 3 -#define ATMEL_SPI_BITS_12 4 -#define ATMEL_SPI_BITS_13 5 -#define ATMEL_SPI_BITS_14 6 -#define ATMEL_SPI_BITS_15 7 -#define ATMEL_SPI_BITS_16 8 - -/* Register access macros */ -#define spi_readl(as, reg) \ - readl(as->regs + ATMEL_SPI_##reg) -#define spi_writel(as, reg, value) \ - writel(value, as->regs + ATMEL_SPI_##reg) diff --git a/drivers/spi/cadence_ospi_versal.c b/drivers/spi/cadence_ospi_versal.c index dcf28c75596..816916de16d 100644 --- a/drivers/spi/cadence_ospi_versal.c +++ b/drivers/spi/cadence_ospi_versal.c @@ -24,6 +24,13 @@ int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv, u8 opcode, addr_bytes, *rxbuf, dummy_cycles; n_rx = op->data.nbytes; + + if (op->addr.dtr && (op->addr.val % 2)) { + n_rx += 1; + writel(op->addr.val & ~0x1, + priv->regbase + CQSPI_REG_INDIRECTRDSTARTADDR); + } + rxbuf = op->data.buf.in; rx_rem = n_rx % 4; bytes_to_dma = n_rx - rx_rem; @@ -104,6 +111,11 @@ int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv, memcpy(rxbuf, &data, rx_rem); } + if (op->addr.dtr && (op->addr.val % 2)) { + rxbuf -= bytes_to_dma; + memcpy(rxbuf, rxbuf + 1, n_rx - 1); + } + return 0; } diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h index 693474a2871..1f9125cd239 100644 --- a/drivers/spi/cadence_qspi.h +++ b/drivers/spi/cadence_qspi.h @@ -307,7 +307,7 @@ int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv, const struct spi_mem_op *op); int cadence_qspi_apb_wait_for_dma_cmplt(struct cadence_spi_priv *priv); int cadence_qspi_apb_exec_flash_cmd(void *reg_base, unsigned int reg); -int cadence_qspi_versal_flash_reset(struct udevice *dev); +int cadence_qspi_flash_reset(struct udevice *dev); ofnode cadence_qspi_get_subnode(struct udevice *dev); void cadence_qspi_apb_enable_linear_mode(bool enable); diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index 93ab2b5635f..f2f69cf9f12 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -151,9 +151,9 @@ static int cadence_qspi_set_protocol(struct cadence_spi_priv *priv, /* Return 1 if idle, otherwise return 0 (busy). */ static unsigned int cadence_qspi_wait_idle(void *reg_base) { - unsigned int start, count = 0; + unsigned long start, count = 0; /* timeout in unit of ms */ - unsigned int timeout = 5000; + unsigned long timeout = 5000; start = get_timer(0); for ( ; get_timer(start) < timeout ; ) { @@ -170,7 +170,7 @@ static unsigned int cadence_qspi_wait_idle(void *reg_base) } /* Timeout, still in busy mode. */ - printf("QSPI: QSPI is still busy after poll for %d ms.\n", timeout); + printf("QSPI: QSPI is still busy after poll for %lu ms.\n", timeout); return 0; } diff --git a/drivers/spi/mtk_spim.c b/drivers/spi/mtk_spim.c index b66bcfc4233..2b2c31b4b3f 100644 --- a/drivers/spi/mtk_spim.c +++ b/drivers/spi/mtk_spim.c @@ -359,6 +359,9 @@ static bool mtk_spim_supports_op(struct spi_slave *slave, struct udevice *bus = dev_get_parent(slave->dev); struct mtk_spim_priv *priv = dev_get_priv(bus); + if (!spi_mem_default_supports_op(slave, op)) + return false; + if (op->cmd.buswidth == 0 || op->cmd.buswidth > 4 || op->addr.buswidth > 4 || op->dummy.buswidth > 4 || op->data.buswidth > 4) @@ -648,7 +651,7 @@ static int mtk_spim_probe(struct udevice *dev) struct mtk_spim_priv *priv = dev_get_priv(dev); int ret; - priv->base = devfdt_get_addr_ptr(dev); + priv->base = dev_read_addr_ptr(dev); if (!priv->base) return -EINVAL; diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c index 4251bf28cd3..2a095d0c58e 100644 --- a/drivers/spi/zynqmp_gqspi.c +++ b/drivers/spi/zynqmp_gqspi.c @@ -255,7 +255,7 @@ static u32 zynqmp_qspi_bus_select(struct zynqmp_qspi_priv *priv) GQSPI_GFIFO_CS_LOWER | GQSPI_GFIFO_CS_UPPER; else - debug("Wrong Bus selection:0x%x\n", priv->bus); + log_debug("Wrong Bus selection:0x%x\n", priv->bus); } else { if (priv->u_page) gqspi_fifo_reg = GQSPI_GFIFO_LOW_BUS | diff --git a/drivers/sysinfo/sandbox.c b/drivers/sysinfo/sandbox.c index d39720958f0..af54fe87596 100644 --- a/drivers/sysinfo/sandbox.c +++ b/drivers/sysinfo/sandbox.c @@ -13,6 +13,7 @@ struct sysinfo_sandbox_priv { bool called_detect; int test_i1; int test_i2; + u32 test_data[2]; }; char vacation_spots[][64] = {"R'lyeh", "Dreamlands", "Plateau of Leng", @@ -24,6 +25,8 @@ int sysinfo_sandbox_detect(struct udevice *dev) priv->called_detect = true; priv->test_i2 = 100; + priv->test_data[0] = 0xabcdabcd; + priv->test_data[1] = 0xdeadbeef; return 0; } @@ -79,6 +82,21 @@ int sysinfo_sandbox_get_str(struct udevice *dev, int id, size_t size, char *val) return -ENOENT; } +int sysinfo_sandbox_get_data(struct udevice *dev, int id, void **buf, + size_t *size) +{ + struct sysinfo_sandbox_priv *priv = dev_get_priv(dev); + + switch (id) { + case DATA_TEST: + *buf = priv->test_data; + *size = sizeof(priv->test_data); + return 0; + } + + return -ENOENT; +} + static const struct udevice_id sysinfo_sandbox_ids[] = { { .compatible = "sandbox,sysinfo-sandbox" }, { /* sentinel */ } @@ -89,6 +107,7 @@ static const struct sysinfo_ops sysinfo_sandbox_ops = { .get_bool = sysinfo_sandbox_get_bool, .get_int = sysinfo_sandbox_get_int, .get_str = sysinfo_sandbox_get_str, + .get_data = sysinfo_sandbox_get_data, }; int sysinfo_sandbox_probe(struct udevice *dev) diff --git a/drivers/sysinfo/sandbox.h b/drivers/sysinfo/sandbox.h index a7cbac0ce18..47b7f5ef9fe 100644 --- a/drivers/sysinfo/sandbox.h +++ b/drivers/sysinfo/sandbox.h @@ -9,4 +9,5 @@ enum { INT_TEST1, INT_TEST2, STR_VACATIONSPOT, + DATA_TEST, }; diff --git a/drivers/sysinfo/smbios.c b/drivers/sysinfo/smbios.c index a7ac8e3f072..99104274f72 100644 --- a/drivers/sysinfo/smbios.c +++ b/drivers/sysinfo/smbios.c @@ -5,14 +5,240 @@ */ #include <dm.h> +#include <smbios_plat.h> #include <sysinfo.h> +/* platform information storage */ +struct processor_info processor_info; +struct cache_info cache_info[SYSINFO_CACHE_LVL_MAX]; +struct sysinfo_plat sysinfo_smbios_p = { + /* Processor Information */ + .processor = &processor_info, + /* Cache Information */ + .cache = &cache_info[0], +}; + +/* structure for smbios private data storage */ +struct sysinfo_plat_priv { + struct processor_info *t4; + struct smbios_type7 t7[SYSINFO_CACHE_LVL_MAX]; + u16 cache_handles[SYSINFO_CACHE_LVL_MAX]; + u8 cache_level; +}; + +static void smbios_cache_info_dump(struct smbios_type7 *cache_info) +{ + log_debug("SMBIOS Type 7 (Cache Information):\n"); + log_debug("Cache Configuration: 0x%04x\n", cache_info->config.data); + log_debug("Maximum Cache Size: %u KB\n", cache_info->max_size.data); + log_debug("Installed Size: %u KB\n", cache_info->inst_size.data); + log_debug("Supported SRAM Type: 0x%04x\n", + cache_info->supp_sram_type.data); + log_debug("Current SRAM Type: 0x%04x\n", + cache_info->curr_sram_type.data); + log_debug("Cache Speed: %u\n", cache_info->speed); + log_debug("Error Correction Type: %u\n", cache_info->err_corr_type); + log_debug("System Cache Type: %u\n", cache_info->sys_cache_type); + log_debug("Associativity: %u\n", cache_info->associativity); + log_debug("Maximum Cache Size 2: %u KB\n", cache_info->max_size2.data); + log_debug("Installed Cache Size 2: %u KB\n", + cache_info->inst_size2.data); +} + +/* weak function for the platforms not yet supported */ +__weak int sysinfo_get_cache_info(u8 level, struct cache_info *cache_info) +{ + return -ENOSYS; +} + +__weak int sysinfo_get_processor_info(struct processor_info *pinfo) +{ + return -ENOSYS; +} + +void sysinfo_cache_info_default(struct cache_info *ci) +{ + memset(ci, 0, sizeof(*ci)); + ci->config.data = SMBIOS_CACHE_LOCATE_UNKNOWN | SMBIOS_CACHE_OP_UND; + ci->supp_sram_type.fields.unknown = 1; + ci->curr_sram_type.fields.unknown = 1; + ci->speed = SMBIOS_CACHE_SPEED_UNKNOWN; + ci->err_corr_type = SMBIOS_CACHE_ERRCORR_UNKNOWN; + ci->cache_type = SMBIOS_CACHE_SYSCACHE_TYPE_UNKNOWN; +} + +static int sysinfo_plat_detect(struct udevice *dev) +{ + return 0; +} + +static int sysinfo_plat_get_str(struct udevice *dev, int id, + size_t size, char *val) +{ + struct sysinfo_plat_priv *priv = dev_get_priv(dev); + const char *str = NULL; + + switch (id) { + case SYSID_SM_PROCESSOR_MANUFACT: + str = priv->t4->manufacturer; + break; + default: + break; + } + + if (!str) + return -ENOSYS; + + strlcpy(val, str, size); + + return 0; +} + +static int sysinfo_plat_get_int(struct udevice *dev, int id, int *val) +{ + struct sysinfo_plat_priv *priv = dev_get_priv(dev); + u8 i; + + if (id >= SYSID_SM_CACHE_INFO_START && + id <= SYSID_SM_CACHE_INFO_END) { + /* For smbios type 7 */ + for (i = 0; i < priv->cache_level; i++) { + switch (id - i) { + case SYSID_SM_CACHE_MAX_SIZE: + *val = priv->t7[i].max_size.data; + return 0; + case SYSID_SM_CACHE_INST_SIZE: + *val = priv->t7[i].inst_size.data; + return 0; + case SYSID_SM_CACHE_SCACHE_TYPE: + *val = priv->t7[i].sys_cache_type; + return 0; + case SYSID_SM_CACHE_ASSOC: + *val = priv->t7[i].associativity; + return 0; + case SYSID_SM_CACHE_MAX_SIZE2: + *val = priv->t7[i].max_size2.data; + return 0; + case SYSID_SM_CACHE_INST_SIZE2: + *val = priv->t7[i].inst_size2.data; + return 0; + default: + break; + } + } + return -ENOSYS; + } + + switch (id) { + case SYSID_SM_PROCESSOR_CORE_CNT: + *val = priv->t4->core_count; + break; + case SYSID_SM_PROCESSOR_CORE_EN: + *val = priv->t4->core_enabled; + break; + case SYSID_SM_PROCESSOR_CHARA: + *val = priv->t4->characteristics; + break; + case SYSID_SM_CACHE_LEVEL: + if (!priv->cache_level) /* No cache detected */ + return -ENOSYS; + *val = priv->cache_level - 1; + break; + default: + return -ENOSYS; + } + + return 0; +} + +static int sysinfo_plat_get_data(struct udevice *dev, int id, void **buf, + size_t *size) +{ + struct sysinfo_plat_priv *priv = dev_get_priv(dev); + + switch (id) { + case SYSID_SM_PROCESSOR_ID: + *buf = priv->t4->id; + *size = sizeof(priv->t4->id); + break; + case SYSID_SM_CACHE_HANDLE: + *buf = &priv->cache_handles[0]; + *size = sizeof(priv->cache_handles); + break; + default: + return -EOPNOTSUPP; + } + return 0; +} + +static int sysinfo_plat_probe(struct udevice *dev) +{ + struct sysinfo_plat_priv *priv = dev_get_priv(dev); + struct sysinfo_plat *plat = &sysinfo_smbios_p; + u8 level; + + if (!sysinfo_get_processor_info(plat->processor)) + priv->t4 = plat->processor; + + for (level = 0; level < SYSINFO_CACHE_LVL_MAX; level++) { + struct cache_info *pcache = plat->cache + level; + + if (sysinfo_get_cache_info(level, pcache)) + break; /* no more levels */ + + /* + * Fill in the SMBIOS type 7 structure, + * skip the header members (type, length, handle), + * and the ones in DT smbios node. + */ + priv->t7[level].sys_cache_type = pcache->cache_type; + priv->t7[level].associativity = pcache->associativity; + + if (pcache->max_size > SMBIOS_CACHE_SIZE_EXT_KB) { + priv->t7[level].max_size.data = 0xFFFF; + priv->t7[level].max_size2.fields.size = + pcache->max_size / 64; + priv->t7[level].max_size2.fields.granu = + SMBIOS_CACHE_GRANU_64K; + } else { + priv->t7[level].max_size.fields.size = pcache->max_size; + priv->t7[level].max_size.fields.granu = + SMBIOS_CACHE_GRANU_1K; + priv->t7[level].max_size2.data = 0; + } + if (pcache->inst_size > SMBIOS_CACHE_SIZE_EXT_KB) { + priv->t7[level].inst_size.data = 0xFFFF; + priv->t7[level].inst_size2.fields.size = + pcache->inst_size / 64; + priv->t7[level].inst_size2.fields.granu = + SMBIOS_CACHE_GRANU_64K; + } else { + priv->t7[level].inst_size.fields.size = + pcache->inst_size; + priv->t7[level].inst_size.fields.granu = + SMBIOS_CACHE_GRANU_1K; + priv->t7[level].inst_size2.data = 0; + } + smbios_cache_info_dump(&priv->t7[level]); + } + if (!level) /* no cache detected */ + return -ENOSYS; + + priv->cache_level = level; + + return 0; +} + static const struct udevice_id sysinfo_smbios_ids[] = { { .compatible = "u-boot,sysinfo-smbios" }, { /* sentinel */ } }; static const struct sysinfo_ops sysinfo_smbios_ops = { + .detect = sysinfo_plat_detect, + .get_str = sysinfo_plat_get_str, + .get_int = sysinfo_plat_get_int, + .get_data = sysinfo_plat_get_data, }; U_BOOT_DRIVER(sysinfo_smbios) = { @@ -20,4 +246,6 @@ U_BOOT_DRIVER(sysinfo_smbios) = { .id = UCLASS_SYSINFO, .of_match = sysinfo_smbios_ids, .ops = &sysinfo_smbios_ops, + .priv_auto = sizeof(struct sysinfo_plat_priv), + .probe = sysinfo_plat_probe, }; diff --git a/drivers/sysinfo/sysinfo-uclass.c b/drivers/sysinfo/sysinfo-uclass.c index d77d1e3ee44..3c0cd51273e 100644 --- a/drivers/sysinfo/sysinfo-uclass.c +++ b/drivers/sysinfo/sysinfo-uclass.c @@ -99,6 +99,26 @@ int sysinfo_get_str(struct udevice *dev, int id, size_t size, char *val) return ops->get_str(dev, id, size, val); } +int sysinfo_get_data(struct udevice *dev, int id, void **data, size_t *size) +{ + struct sysinfo_priv *priv; + struct sysinfo_ops *ops; + + if (!dev) + return -ENOSYS; + + priv = dev_get_uclass_priv(dev); + ops = sysinfo_get_ops(dev); + + if (!priv->detected) + return -EPERM; + + if (!ops->get_data) + return -ENOSYS; + + return ops->get_data(dev, id, data, size); +} + UCLASS_DRIVER(sysinfo) = { .id = UCLASS_SYSINFO, .name = "sysinfo", diff --git a/drivers/tpm/Kconfig b/drivers/tpm/Kconfig index d59102d9a6b..01bc686d367 100644 --- a/drivers/tpm/Kconfig +++ b/drivers/tpm/Kconfig @@ -209,6 +209,15 @@ config TPM2_MMIO to the device using the standard TPM Interface Specification (TIS) protocol. +config TPM2_EVENT_LOG_SIZE + int "EventLog size" + depends on TPM_V2 + default 65536 + help + Define the size of the EventLog. Note that this is going to be + allocated twice. One for the eventlog it self and one for the + configuration table that is required from the TCG2 spec + endif # TPM_V2 endmenu diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig index 960b6a906ac..99c6649e417 100644 --- a/drivers/usb/Kconfig +++ b/drivers/usb/Kconfig @@ -1,5 +1,6 @@ menuconfig USB bool "USB support" + select BLK ---help--- Universal Serial Bus (USB) is a specification for a serial bus subsystem which offers higher speeds and more features than the diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 24786a2bc91..a656265890e 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -217,14 +217,14 @@ config USB_EHCI_MX6 Enables support for the on-chip EHCI controller on i.MX6 SoCs. config USB_EHCI_MX7 - bool "Support for i.MX7 on-chip EHCI USB controller" - depends on ARCH_MX7 || IMX8M || IMX93 + bool "Support for i.MX7/i.MX8M/i.MX9 on-chip EHCI USB controller" + depends on ARCH_MX7 || IMX8M || IMX93 || IMX95 select EHCI_HCD_INIT_AFTER_RESET if ARCH_MX7 - select PHY if IMX8M || IMX93 - select NOP_PHY if IMX8M || IMX93 + select PHY if IMX8M || IMX93 || IMX95 + select NOP_PHY if IMX8M || IMX93 || IMX95 default y ---help--- - Enables support for the on-chip EHCI controller on i.MX7 SoCs. + Enables support for the on-chip EHCI controller on i.MX7/i.MX8M/i.MX9 SoCs. config USB_EHCI_MXS bool "Support for i.MX23/i.MX28 EHCI USB controller" diff --git a/drivers/usb/host/ehci-mx5.c b/drivers/usb/host/ehci-mx5.c index d8f521befe1..1392d29bc13 100644 --- a/drivers/usb/host/ehci-mx5.c +++ b/drivers/usb/host/ehci-mx5.c @@ -287,9 +287,9 @@ static int ehci_usb_probe(struct udevice *dev) debug("%s: No vbus supply\n", dev->name); if (!ret && priv->vbus_supply) { - ret = regulator_set_enable(priv->vbus_supply, - (type == USB_INIT_DEVICE) ? - false : true); + ret = regulator_set_enable_if_allowed(priv->vbus_supply, + (type == USB_INIT_DEVICE) ? + false : true); if (ret) { puts("Error enabling VBUS supply\n"); return ret; diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c index a93fa5d5455..a8748cef7ad 100644 --- a/drivers/usb/host/ehci-mx6.c +++ b/drivers/usb/host/ehci-mx6.c @@ -479,9 +479,9 @@ static int mx6_init_after_reset(struct ehci_ctrl *dev) #if CONFIG_IS_ENABLED(DM_REGULATOR) if (priv->vbus_supply) { int ret; - ret = regulator_set_enable(priv->vbus_supply, - (type == USB_INIT_DEVICE) ? - false : true); + ret = regulator_set_enable_if_allowed(priv->vbus_supply, + (type == USB_INIT_DEVICE) ? + false : true); if (ret && ret != -ENOSYS) { printf("Error enabling VBUS supply (ret=%i)\n", ret); return ret; diff --git a/drivers/video/bochs.c b/drivers/video/bochs.c index 00e673a4db0..c34bc23f274 100644 --- a/drivers/video/bochs.c +++ b/drivers/video/bochs.c @@ -64,6 +64,7 @@ static int bochs_init_fb(struct udevice *dev) uc_priv->xsize = xsize; uc_priv->ysize = ysize; uc_priv->bpix = VIDEO_BPP32; + uc_priv->format = VIDEO_X8B8G8R8; /* setup video mode */ bochs_write(mmio, INDEX_ENABLE, 0); diff --git a/drivers/video/video-uclass.c b/drivers/video/video-uclass.c index a5b3e898066..ff4f2199585 100644 --- a/drivers/video/video-uclass.c +++ b/drivers/video/video-uclass.c @@ -589,6 +589,7 @@ static int video_post_probe(struct udevice *dev) ho->ysize = priv->ysize; ho->line_length = priv->line_length; ho->bpix = priv->bpix; + ho->format = priv->format; } if (IS_ENABLED(CONFIG_VIDEO_COPY) && plat->copy_base) diff --git a/drivers/virtio/Kconfig b/drivers/virtio/Kconfig index 1de68867d52..512ac376f18 100644 --- a/drivers/virtio/Kconfig +++ b/drivers/virtio/Kconfig @@ -64,6 +64,7 @@ config VIRTIO_NET config VIRTIO_BLK bool "virtio block driver" depends on VIRTIO + select BLK help This is the virtual block driver for virtio. It can be used with QEMU based targets. diff --git a/drivers/watchdog/rti_wdt.c b/drivers/watchdog/rti_wdt.c index 99168d0cad0..7b387266b99 100644 --- a/drivers/watchdog/rti_wdt.c +++ b/drivers/watchdog/rti_wdt.c @@ -131,18 +131,19 @@ static int rti_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags) u32 timer_margin; int ret; - if (readl(priv->regs + RTIDWDCTRL) == WDENABLE_KEY) + timer_margin = timeout_ms * priv->clk_hz / 1000; + timer_margin >>= WDT_PRELOAD_SHIFT; + if (timer_margin > WDT_PRELOAD_MAX) + timer_margin = WDT_PRELOAD_MAX; + + if (readl(priv->regs + RTIDWDCTRL) == WDENABLE_KEY && + readl(priv->regs + RTIDWDPRLD) != timer_margin) return -EBUSY; ret = rti_wdt_load_fw(dev); if (ret < 0) return ret; - timer_margin = timeout_ms * priv->clk_hz / 1000; - timer_margin >>= WDT_PRELOAD_SHIFT; - if (timer_margin > WDT_PRELOAD_MAX) - timer_margin = WDT_PRELOAD_MAX; - writel(timer_margin, priv->regs + RTIDWDPRLD); writel(RTIWWDRX_NMI, priv->regs + RTIWWDRXCTRL); writel(RTIWWDSIZE_50P, priv->regs + RTIWWDSIZECTRL); @@ -186,14 +187,6 @@ static int rti_wdt_probe(struct udevice *dev) priv->clk_hz = clk_get_rate(&clk); - /* - * If watchdog is running at 32k clock, it is not accurate. - * Adjust frequency down in this case so that it does not expire - * earlier than expected. - */ - if (priv->clk_hz < 32768) - priv->clk_hz = priv->clk_hz * 9 / 10; - return 0; } |