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-rw-r--r--drivers/adc/adc-uclass.c2
-rw-r--r--drivers/adc/stm32-adc.c83
-rw-r--r--drivers/ata/ahci-pci.c2
-rw-r--r--drivers/clk/rockchip/clk_rk3128.c8
-rw-r--r--drivers/clk/stm32/Kconfig15
-rw-r--r--drivers/clk/stm32/Makefile2
-rw-r--r--drivers/clk/stm32/clk-stm32-core.c268
-rw-r--r--drivers/clk/stm32/clk-stm32-core.h276
-rw-r--r--drivers/clk/stm32/clk-stm32mp13.c841
-rw-r--r--drivers/clk/stm32/stm32mp13_rcc.h288
-rw-r--r--drivers/clk/ti/clk-k3.c6
-rw-r--r--drivers/ddr/fsl/ctrl_regs.c17
-rw-r--r--drivers/ddr/fsl/mpc85xx_ddr_gen1.c2
-rw-r--r--drivers/ddr/fsl/util.c6
-rw-r--r--drivers/ddr/marvell/axp/ddr3_axp_config.h2
-rw-r--r--drivers/dma/fsl_dma.c4
-rw-r--r--drivers/firmware/scmi/scmi_agent-uclass.c5
-rw-r--r--drivers/firmware/ti_sci_static_data.h4
-rw-r--r--drivers/fpga/ACEX1K.c22
-rw-r--r--drivers/fpga/Kconfig4
-rw-r--r--drivers/fpga/cyclon2.c12
-rw-r--r--drivers/fpga/spartan2.c44
-rw-r--r--drivers/fpga/spartan3.c44
-rw-r--r--drivers/fpga/virtex2.c29
-rw-r--r--drivers/i2c/Kconfig2
-rw-r--r--drivers/i2c/i2c_core.c10
-rw-r--r--drivers/i2c/mv_i2c.c33
-rw-r--r--drivers/i2c/mvtwsi.c12
-rw-r--r--drivers/misc/gsc.c2
-rw-r--r--drivers/mmc/Kconfig14
-rw-r--r--drivers/mmc/fsl_esdhc_imx.c2
-rw-r--r--drivers/mtd/Kconfig28
-rw-r--r--drivers/mtd/cfi_flash.c4
-rw-r--r--drivers/mtd/mtd_uboot.c4
-rw-r--r--drivers/mtd/nand/core.c3
-rw-r--r--drivers/mtd/nand/raw/Kconfig7
-rw-r--r--drivers/mtd/nand/raw/atmel_nand.c4
-rw-r--r--drivers/mtd/nand/raw/fsl_ifc_spl.c6
-rw-r--r--drivers/mtd/nand/raw/lpc32xx_nand_mlc.c14
-rw-r--r--drivers/mtd/nand/raw/lpc32xx_nand_slc.c16
-rw-r--r--drivers/mtd/nand/raw/mxc_nand.c4
-rw-r--r--drivers/mtd/nand/raw/mxs_nand_spl.c2
-rw-r--r--drivers/mtd/nand/raw/nand_base.c7
-rw-r--r--drivers/mtd/nand/raw/nand_spl_loaders.c2
-rw-r--r--drivers/mtd/nand/raw/octeontx_bch.c5
-rw-r--r--drivers/mtd/nand/raw/octeontx_nand.c5
-rw-r--r--drivers/mtd/nand/raw/omap_gpmc.c68
-rw-r--r--drivers/mtd/ubi/Kconfig12
-rw-r--r--drivers/net/Kconfig36
-rw-r--r--drivers/net/Makefile1
-rw-r--r--drivers/net/bnxt/Kconfig1
-rw-r--r--drivers/net/dc2114x.c156
-rw-r--r--drivers/net/designware.c112
-rw-r--r--drivers/net/designware.h5
-rw-r--r--drivers/net/dm9000x.c66
-rw-r--r--drivers/net/e1000.c216
-rw-r--r--drivers/net/e1000.h11
-rw-r--r--drivers/net/eepro100.c134
-rw-r--r--drivers/net/ethoc.c85
-rw-r--r--drivers/net/fec_mxc.c8
-rw-r--r--drivers/net/fec_mxc.h2
-rw-r--r--drivers/net/fm/Makefile1
-rw-r--r--drivers/net/fm/eth.c238
-rw-r--r--drivers/net/fm/fm.c4
-rw-r--r--drivers/net/fm/fm.h8
-rw-r--r--drivers/net/fm/init.c386
-rw-r--r--drivers/net/fm/memac_phy.c52
-rw-r--r--drivers/net/fsl-mc/mc.c21
-rw-r--r--drivers/net/ldpaa_eth/ldpaa_eth.c198
-rw-r--r--drivers/net/ldpaa_eth/ldpaa_eth.h4
-rw-r--r--drivers/net/macb.c194
-rw-r--r--drivers/net/mcfmii.c16
-rw-r--r--drivers/net/mscc_eswitch/Kconfig10
-rw-r--r--drivers/net/mvgbe.c218
-rw-r--r--drivers/net/mvgbe.h15
-rw-r--r--drivers/net/netconsole.c8
-rw-r--r--drivers/net/pcnet.c136
-rw-r--r--drivers/net/phy/Kconfig3
-rw-r--r--drivers/net/phy/aquantia.c2
-rw-r--r--drivers/net/phy/atheros.c2
-rw-r--r--drivers/net/phy/dp83867.c14
-rw-r--r--drivers/net/phy/dp83869.c14
-rw-r--r--drivers/net/phy/et1011c.c2
-rw-r--r--drivers/net/phy/marvell.c7
-rw-r--r--drivers/net/phy/micrel_ksz90x1.c18
-rw-r--r--drivers/net/phy/phy.c13
-rw-r--r--drivers/net/qe/Kconfig1
-rw-r--r--drivers/net/qe/uec.h1
-rw-r--r--drivers/net/rtl8139.c112
-rw-r--r--drivers/net/rtl8169.c166
-rw-r--r--drivers/net/sh_eth.c180
-rw-r--r--drivers/net/sh_eth.h16
-rw-r--r--drivers/net/smc911x.c147
-rw-r--r--drivers/net/sunxi_emac.c2
-rw-r--r--drivers/net/ti/Kconfig13
-rw-r--r--drivers/net/ti/cpsw.c100
-rw-r--r--drivers/net/ti/keystone_net.c14
-rw-r--r--drivers/net/tsec.c209
-rw-r--r--drivers/net/vsc9953.c2754
-rw-r--r--drivers/pci/pci-rcar-gen3.c6
-rw-r--r--drivers/pci/pcie_dw_common.c2
-rw-r--r--drivers/pci/pcie_dw_common.h1
-rw-r--r--drivers/pci/pcie_imx.c22
-rw-r--r--drivers/phy/phy-stm32-usbphyc.c2
-rw-r--r--drivers/phy/rockchip/phy-rockchip-inno-usb2.c2
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sunxi.c7
-rw-r--r--drivers/pinctrl/uniphier/pinctrl-uniphier-core.c3
-rw-r--r--drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c20
-rw-r--r--drivers/power/domain/ti-power-domain.c6
-rw-r--r--drivers/power/pmic/Kconfig3
-rw-r--r--drivers/power/pmic/pmic-uclass.c4
-rw-r--r--drivers/power/pmic/pmic_ltc3676.c2
-rw-r--r--drivers/power/pmic/pmic_pfuze100.c2
-rw-r--r--drivers/power/pmic/pmic_pfuze3000.c2
-rw-r--r--drivers/power/power_fsl.c8
-rw-r--r--drivers/pwm/pwm-imx.c2
-rw-r--r--drivers/qe/Makefile2
-rw-r--r--drivers/qe/uccf.c509
-rw-r--r--drivers/qe/uccf.h119
-rw-r--r--drivers/qe/uec.c1436
-rw-r--r--drivers/qe/uec.h692
-rw-r--r--drivers/qe/uec_phy.c930
-rw-r--r--drivers/qe/uec_phy.h214
-rw-r--r--drivers/ram/Kconfig11
-rw-r--r--drivers/ram/k3-ddrss/16bit/lpddr4_16bit_obj_if.h14
-rw-r--r--drivers/ram/k3-ddrss/16bit/lpddr4_16bit_structs_if.h15
-rw-r--r--drivers/ram/k3-ddrss/32bit/lpddr4_32bit_obj_if.h14
-rw-r--r--drivers/ram/k3-ddrss/32bit/lpddr4_32bit_structs_if.h15
-rw-r--r--drivers/ram/k3-ddrss/Makefile18
-rw-r--r--drivers/ram/k3-ddrss/am62a/lpddr4_address_slice_0_macros.h778
-rw-r--r--drivers/ram/k3-ddrss/am62a/lpddr4_address_slice_1_macros.h778
-rw-r--r--drivers/ram/k3-ddrss/am62a/lpddr4_address_slice_2_macros.h778
-rw-r--r--drivers/ram/k3-ddrss/am62a/lpddr4_am62a_ctl_regs_rw_masks.h25
-rw-r--r--drivers/ram/k3-ddrss/am62a/lpddr4_am62a_if.h108
-rw-r--r--drivers/ram/k3-ddrss/am62a/lpddr4_am62a_obj_if.h14
-rw-r--r--drivers/ram/k3-ddrss/am62a/lpddr4_am62a_structs_if.h15
-rw-r--r--drivers/ram/k3-ddrss/am62a/lpddr4_ctl_regs.h1721
-rw-r--r--drivers/ram/k3-ddrss/am62a/lpddr4_data_slice_0_macros.h2292
-rw-r--r--drivers/ram/k3-ddrss/am62a/lpddr4_data_slice_1_macros.h2292
-rw-r--r--drivers/ram/k3-ddrss/am62a/lpddr4_data_slice_2_macros.h2292
-rw-r--r--drivers/ram/k3-ddrss/am62a/lpddr4_data_slice_3_macros.h2292
-rw-r--r--drivers/ram/k3-ddrss/am62a/lpddr4_ddr_controller_macros.h6560
-rw-r--r--drivers/ram/k3-ddrss/am62a/lpddr4_phy_core_macros.h1986
-rw-r--r--drivers/ram/k3-ddrss/am62a/lpddr4_pi_macros.h6892
-rw-r--r--drivers/ram/k3-ddrss/am64/lpddr4_address_slice_0_macros.h (renamed from drivers/ram/k3-ddrss/16bit/lpddr4_address_slice_0_macros.h)4
-rw-r--r--drivers/ram/k3-ddrss/am64/lpddr4_address_slice_1_macros.h (renamed from drivers/ram/k3-ddrss/16bit/lpddr4_address_slice_1_macros.h)4
-rw-r--r--drivers/ram/k3-ddrss/am64/lpddr4_address_slice_2_macros.h (renamed from drivers/ram/k3-ddrss/16bit/lpddr4_address_slice_2_macros.h)4
-rw-r--r--drivers/ram/k3-ddrss/am64/lpddr4_am64_ctl_regs_rw_masks.h (renamed from drivers/ram/k3-ddrss/16bit/lpddr4_ctl_regs_rw_masks.h)4
-rw-r--r--drivers/ram/k3-ddrss/am64/lpddr4_am64_if.h (renamed from drivers/ram/k3-ddrss/16bit/lpddr4_16bit_if.h)10
-rw-r--r--drivers/ram/k3-ddrss/am64/lpddr4_am64_obj_if.h14
-rw-r--r--drivers/ram/k3-ddrss/am64/lpddr4_am64_structs_if.h15
-rw-r--r--drivers/ram/k3-ddrss/am64/lpddr4_ctl_regs.h (renamed from drivers/ram/k3-ddrss/16bit/lpddr4_ctl_regs.h)4
-rw-r--r--drivers/ram/k3-ddrss/am64/lpddr4_data_slice_0_macros.h (renamed from drivers/ram/k3-ddrss/16bit/lpddr4_data_slice_0_macros.h)4
-rw-r--r--drivers/ram/k3-ddrss/am64/lpddr4_data_slice_1_macros.h (renamed from drivers/ram/k3-ddrss/16bit/lpddr4_data_slice_1_macros.h)4
-rw-r--r--drivers/ram/k3-ddrss/am64/lpddr4_ddr_controller_macros.h (renamed from drivers/ram/k3-ddrss/16bit/lpddr4_ddr_controller_macros.h)4
-rw-r--r--drivers/ram/k3-ddrss/am64/lpddr4_phy_core_macros.h (renamed from drivers/ram/k3-ddrss/16bit/lpddr4_phy_core_macros.h)4
-rw-r--r--drivers/ram/k3-ddrss/am64/lpddr4_pi_macros.h (renamed from drivers/ram/k3-ddrss/16bit/lpddr4_pi_macros.h)4
-rw-r--r--drivers/ram/k3-ddrss/cps_drv_lpddr4.h4
-rw-r--r--drivers/ram/k3-ddrss/j721e/lpddr4_address_slice_0_macros.h (renamed from drivers/ram/k3-ddrss/32bit/lpddr4_address_slice_0_macros.h)4
-rw-r--r--drivers/ram/k3-ddrss/j721e/lpddr4_ctl_regs.h (renamed from drivers/ram/k3-ddrss/32bit/lpddr4_ctl_regs.h)4
-rw-r--r--drivers/ram/k3-ddrss/j721e/lpddr4_data_slice_0_macros.h (renamed from drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_0_macros.h)4
-rw-r--r--drivers/ram/k3-ddrss/j721e/lpddr4_data_slice_1_macros.h (renamed from drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_1_macros.h)4
-rw-r--r--drivers/ram/k3-ddrss/j721e/lpddr4_data_slice_2_macros.h (renamed from drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_2_macros.h)4
-rw-r--r--drivers/ram/k3-ddrss/j721e/lpddr4_data_slice_3_macros.h (renamed from drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_3_macros.h)4
-rw-r--r--drivers/ram/k3-ddrss/j721e/lpddr4_ddr_controller_macros.h (renamed from drivers/ram/k3-ddrss/32bit/lpddr4_ddr_controller_macros.h)4
-rw-r--r--drivers/ram/k3-ddrss/j721e/lpddr4_j721e_ctl_regs_rw_masks.h (renamed from drivers/ram/k3-ddrss/32bit/lpddr4_ctl_regs_rw_masks.h)4
-rw-r--r--drivers/ram/k3-ddrss/j721e/lpddr4_j721e_if.h (renamed from drivers/ram/k3-ddrss/32bit/lpddr4_32bit_if.h)10
-rw-r--r--drivers/ram/k3-ddrss/j721e/lpddr4_j721e_obj_if.h14
-rw-r--r--drivers/ram/k3-ddrss/j721e/lpddr4_j721e_structs_if.h15
-rw-r--r--drivers/ram/k3-ddrss/j721e/lpddr4_phy_core_macros.h (renamed from drivers/ram/k3-ddrss/32bit/lpddr4_phy_core_macros.h)4
-rw-r--r--drivers/ram/k3-ddrss/j721e/lpddr4_pi_macros.h (renamed from drivers/ram/k3-ddrss/32bit/lpddr4_pi_macros.h)4
-rw-r--r--drivers/ram/k3-ddrss/k3-ddrss.c1
-rw-r--r--drivers/ram/k3-ddrss/lpddr4.c67
-rw-r--r--drivers/ram/k3-ddrss/lpddr4.h33
-rw-r--r--drivers/ram/k3-ddrss/lpddr4_16bit.h33
-rw-r--r--drivers/ram/k3-ddrss/lpddr4_am62a_ctl_regs_rw_masks.c1726
-rw-r--r--drivers/ram/k3-ddrss/lpddr4_am64_ctl_regs_rw_masks.c (renamed from drivers/ram/k3-ddrss/lpddr4_16bit_ctl_regs_rw_masks.c)6
-rw-r--r--drivers/ram/k3-ddrss/lpddr4_am6x.c (renamed from drivers/ram/k3-ddrss/lpddr4_16bit.c)16
-rw-r--r--drivers/ram/k3-ddrss/lpddr4_am6x.h45
-rw-r--r--drivers/ram/k3-ddrss/lpddr4_am6x_sanity.h (renamed from drivers/ram/k3-ddrss/lpddr4_16bit_sanity.h)20
-rw-r--r--drivers/ram/k3-ddrss/lpddr4_if.h12
-rw-r--r--drivers/ram/k3-ddrss/lpddr4_j721e.c (renamed from drivers/ram/k3-ddrss/lpddr4_32bit.c)7
-rw-r--r--drivers/ram/k3-ddrss/lpddr4_j721e.h (renamed from drivers/ram/k3-ddrss/lpddr4_32bit.h)20
-rw-r--r--drivers/ram/k3-ddrss/lpddr4_j721e_ctl_regs_rw_masks.c (renamed from drivers/ram/k3-ddrss/lpddr4_32bit_ctl_regs_rw_masks.c)6
-rw-r--r--drivers/ram/k3-ddrss/lpddr4_j721e_sanity.h (renamed from drivers/ram/k3-ddrss/lpddr4_32bit_sanity.h)17
-rw-r--r--drivers/ram/k3-ddrss/lpddr4_obj_if.c5
-rw-r--r--drivers/ram/k3-ddrss/lpddr4_obj_if.h6
-rw-r--r--drivers/ram/k3-ddrss/lpddr4_private.h60
-rw-r--r--drivers/ram/k3-ddrss/lpddr4_sanity.h20
-rw-r--r--drivers/ram/k3-ddrss/lpddr4_structs_if.h4
-rw-r--r--drivers/ram/mpc83xx_sdram.c7
-rw-r--r--drivers/rtc/Kconfig9
-rw-r--r--drivers/rtc/Makefile1
-rw-r--r--drivers/rtc/ftrtc010.c4
-rw-r--r--drivers/rtc/ht1380.c329
-rw-r--r--drivers/rtc/mc146818.c2
-rw-r--r--drivers/scsi/scsi.c4
-rw-r--r--drivers/serial/Kconfig9
-rw-r--r--drivers/serial/Makefile18
-rw-r--r--drivers/serial/atmel_usart.c20
-rw-r--r--drivers/serial/serial-uclass.c8
-rw-r--r--drivers/serial/serial.c2
-rw-r--r--drivers/serial/serial_arc.c8
-rw-r--r--drivers/serial/serial_lpuart.c39
-rw-r--r--drivers/serial/serial_mpc8xx.c15
-rw-r--r--drivers/serial/serial_mtk.c3
-rw-r--r--drivers/serial/serial_mvebu_a3700.c8
-rw-r--r--drivers/serial/serial_mxc.c6
-rw-r--r--drivers/serial/serial_pl01x.c21
-rw-r--r--drivers/serial/serial_pl01x_internal.h2
-rw-r--r--drivers/serial/serial_s5p4418_pl011.c94
-rw-r--r--drivers/serial/serial_sh.c2
-rw-r--r--drivers/serial/serial_sh.h8
-rw-r--r--drivers/serial/usbtty.c50
-rw-r--r--drivers/serial/usbtty.h4
-rw-r--r--drivers/soc/soc_ti_k3.c4
-rw-r--r--drivers/sound/sandbox.c9
-rw-r--r--drivers/sound/sound.c5
-rw-r--r--drivers/spi/Kconfig10
-rw-r--r--drivers/spi/cf_spi.c12
-rw-r--r--drivers/spi/sandbox_spi.c4
-rw-r--r--drivers/usb/Kconfig1
-rw-r--r--drivers/usb/eth/asix.c255
-rw-r--r--drivers/usb/eth/asix88179.c250
-rw-r--r--drivers/usb/eth/mcs7830.c276
-rw-r--r--drivers/usb/eth/r8152.c275
-rw-r--r--drivers/usb/eth/r8152.h2
-rw-r--r--drivers/usb/eth/smsc95xx.c234
-rw-r--r--drivers/usb/eth/usb_ether.c199
-rw-r--r--drivers/usb/gadget/ep0.c19
-rw-r--r--drivers/usb/gadget/ether.c97
-rw-r--r--drivers/usb/gadget/f_dfu.c8
-rw-r--r--drivers/usb/gadget/f_sdp.c2
-rw-r--r--drivers/usb/gadget/rndis.c18
-rw-r--r--drivers/usb/gadget/rndis.h11
-rw-r--r--drivers/usb/host/ehci-mx5.c4
-rw-r--r--drivers/usb/host/ehci-mx6.c8
-rw-r--r--drivers/usb/host/ohci-lpc32xx.c2
-rw-r--r--drivers/usb/host/usb-uclass.c43
-rw-r--r--drivers/video/nexell_display.c2
-rw-r--r--drivers/watchdog/designware_wdt.c2
241 files changed, 33567 insertions, 12414 deletions
diff --git a/drivers/adc/adc-uclass.c b/drivers/adc/adc-uclass.c
index 67137ffb341..9646e4d7062 100644
--- a/drivers/adc/adc-uclass.c
+++ b/drivers/adc/adc-uclass.c
@@ -22,7 +22,7 @@
#define CHECK_MASK (!CHECK_NUMBER)
/* TODO: add support for timer uclass (for early calls) */
-#ifdef CONFIG_SANDBOX_ARCH
+#ifdef CONFIG_SANDBOX
#define sdelay(x) udelay(x)
#else
extern void sdelay(unsigned long loops);
diff --git a/drivers/adc/stm32-adc.c b/drivers/adc/stm32-adc.c
index ad8d1a32cdb..85efc119dbf 100644
--- a/drivers/adc/stm32-adc.c
+++ b/drivers/adc/stm32-adc.c
@@ -162,12 +162,8 @@ static int stm32_adc_channel_data(struct udevice *dev, int channel,
return 0;
}
-static int stm32_adc_chan_of_init(struct udevice *dev)
+static int stm32_adc_get_legacy_chan_count(struct udevice *dev)
{
- struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev);
- struct stm32_adc *adc = dev_get_priv(dev);
- u32 chans[STM32_ADC_CH_MAX];
- unsigned int i, num_channels;
int ret;
/* Retrieve single ended channels listed in device tree */
@@ -176,12 +172,16 @@ static int stm32_adc_chan_of_init(struct udevice *dev)
dev_err(dev, "can't get st,adc-channels: %d\n", ret);
return ret;
}
- num_channels = ret / sizeof(u32);
- if (num_channels > adc->cfg->max_channels) {
- dev_err(dev, "too many st,adc-channels: %d\n", num_channels);
- return -EINVAL;
- }
+ return (ret / sizeof(u32));
+}
+
+static int stm32_adc_legacy_chan_init(struct udevice *dev, unsigned int num_channels)
+{
+ struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev);
+ struct stm32_adc *adc = dev_get_priv(dev);
+ u32 chans[STM32_ADC_CH_MAX];
+ int i, ret;
ret = dev_read_u32_array(dev, "st,adc-channels", chans, num_channels);
if (ret < 0) {
@@ -197,6 +197,69 @@ static int stm32_adc_chan_of_init(struct udevice *dev)
uc_pdata->channel_mask |= 1 << chans[i];
}
+ return ret;
+}
+
+static int stm32_adc_generic_chan_init(struct udevice *dev, unsigned int num_channels)
+{
+ struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev);
+ struct stm32_adc *adc = dev_get_priv(dev);
+ ofnode child;
+ int val, ret;
+
+ ofnode_for_each_subnode(child, dev_ofnode(dev)) {
+ ret = ofnode_read_u32(child, "reg", &val);
+ if (ret) {
+ dev_err(dev, "Missing channel index %d\n", ret);
+ return ret;
+ }
+
+ if (val >= adc->cfg->max_channels) {
+ dev_err(dev, "Invalid channel %d\n", val);
+ return -EINVAL;
+ }
+
+ uc_pdata->channel_mask |= 1 << val;
+ }
+
+ return 0;
+}
+
+static int stm32_adc_chan_of_init(struct udevice *dev)
+{
+ struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev);
+ struct stm32_adc *adc = dev_get_priv(dev);
+ unsigned int num_channels;
+ int ret;
+ bool legacy = false;
+
+ num_channels = dev_get_child_count(dev);
+ /* If no channels have been found, fallback to channels legacy properties. */
+ if (!num_channels) {
+ legacy = true;
+
+ ret = stm32_adc_get_legacy_chan_count(dev);
+ if (!ret) {
+ dev_err(dev, "No channel found\n");
+ return -ENODATA;
+ } else if (ret < 0) {
+ return ret;
+ }
+ num_channels = ret;
+ }
+
+ if (num_channels > adc->cfg->max_channels) {
+ dev_err(dev, "too many st,adc-channels: %d\n", num_channels);
+ return -EINVAL;
+ }
+
+ if (legacy)
+ ret = stm32_adc_legacy_chan_init(dev, num_channels);
+ else
+ ret = stm32_adc_generic_chan_init(dev, num_channels);
+ if (ret < 0)
+ return ret;
+
uc_pdata->data_mask = (1 << adc->cfg->num_bits) - 1;
uc_pdata->data_format = ADC_DATA_FORMAT_BIN;
uc_pdata->data_timeout_us = 100000;
diff --git a/drivers/ata/ahci-pci.c b/drivers/ata/ahci-pci.c
index 797e0d570e8..5356b9d83d3 100644
--- a/drivers/ata/ahci-pci.c
+++ b/drivers/ata/ahci-pci.c
@@ -37,7 +37,7 @@ U_BOOT_DRIVER(ahci_pci) = {
static struct pci_device_id ahci_pci_supported[] = {
{ PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_SATA_AHCI, ~0) },
- { PCI_DEVICE(0x1b21, 0x0611) },
+ { PCI_DEVICE(PCI_VENDOR_ID_ASMEDIA, 0x0611) },
{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6121) },
{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6145) },
{},
diff --git a/drivers/clk/rockchip/clk_rk3128.c b/drivers/clk/rockchip/clk_rk3128.c
index d5b2b63dd79..13e176cdad1 100644
--- a/drivers/clk/rockchip/clk_rk3128.c
+++ b/drivers/clk/rockchip/clk_rk3128.c
@@ -438,7 +438,7 @@ static ulong rk3128_vop_set_clk(struct rk3128_cru *cru, ulong clk_id, uint hz)
VIO1_SEL_GPLL << VIO1_PLL_SHIFT |
(src_clk_div - 1) << VIO1_DIV_SHIFT);
break;
- case DCLK_LCDC:
+ case DCLK_VOP:
if (pll_para_config(hz, &cpll_config))
return -1;
rkclk_set_pll(cru, CLK_CODEC, &cpll_config);
@@ -471,7 +471,7 @@ static ulong rk3128_vop_get_rate(struct rk3128_cru *cru, ulong clk_id)
div = (con >> 8) & 0x1f;
parent = GPLL_HZ;
break;
- case DCLK_LCDC:
+ case DCLK_VOP:
con = readl(&cru->cru_clksel_con[27]);
div = (con >> 8) & 0xfff;
parent = rkclk_pll_get_rate(cru, CLK_CODEC);
@@ -497,7 +497,7 @@ static ulong rk3128_clk_get_rate(struct clk *clk)
return rk3128_peri_get_pclk(priv->cru, clk->id);
case SCLK_SARADC:
return rk3128_saradc_get_clk(priv->cru);
- case DCLK_LCDC:
+ case DCLK_VOP:
case ACLK_VIO0:
case ACLK_VIO1:
return rk3128_vop_get_rate(priv->cru, clk->id);
@@ -515,7 +515,7 @@ static ulong rk3128_clk_set_rate(struct clk *clk, ulong rate)
switch (clk->id) {
case 0 ... 63:
return 0;
- case DCLK_LCDC:
+ case DCLK_VOP:
case ACLK_VIO0:
case ACLK_VIO1:
new_rate = rk3128_vop_set_clk(priv->cru,
diff --git a/drivers/clk/stm32/Kconfig b/drivers/clk/stm32/Kconfig
index eac3fc1e9df..7a34ea23c38 100644
--- a/drivers/clk/stm32/Kconfig
+++ b/drivers/clk/stm32/Kconfig
@@ -14,6 +14,12 @@ config CLK_STM32H7
This clock driver adds support for RCC clock management
for STM32H7 SoCs.
+config CLK_STM32_CORE
+ bool "Enable RCC clock core driver for STM32MP"
+ depends on ARCH_STM32MP && CLK
+ select CLK_CCF
+ select CLK_COMPOSITE_CCF
+
config CLK_STM32MP1
bool "Enable RCC clock driver for STM32MP15"
depends on ARCH_STM32MP && CLK
@@ -21,3 +27,12 @@ config CLK_STM32MP1
help
Enable the STM32 clock (RCC) driver. Enable support for
manipulating STM32MP15's on-SoC clocks.
+
+config CLK_STM32MP13
+ bool "Enable RCC clock driver for STM32MP13"
+ depends on ARCH_STM32MP && CLK
+ default y if STM32MP13x
+ select CLK_STM32_CORE
+ help
+ Enable the STM32 clock (RCC) driver. Enable support for
+ manipulating STM32MP13's on-SoC clocks.
diff --git a/drivers/clk/stm32/Makefile b/drivers/clk/stm32/Makefile
index f66f2954033..20afbc3cfce 100644
--- a/drivers/clk/stm32/Makefile
+++ b/drivers/clk/stm32/Makefile
@@ -2,6 +2,8 @@
#
# Copyright (C) 2022, STMicroelectronics - All Rights Reserved
+obj-$(CONFIG_CLK_STM32_CORE) += clk-stm32-core.o
obj-$(CONFIG_CLK_STM32F) += clk-stm32f.o
obj-$(CONFIG_CLK_STM32H7) += clk-stm32h7.o
obj-$(CONFIG_CLK_STM32MP1) += clk-stm32mp1.o
+obj-$(CONFIG_CLK_STM32MP13) += clk-stm32mp13.o
diff --git a/drivers/clk/stm32/clk-stm32-core.c b/drivers/clk/stm32/clk-stm32-core.c
new file mode 100644
index 00000000000..37e996e78f9
--- /dev/null
+++ b/drivers/clk/stm32/clk-stm32-core.c
@@ -0,0 +1,268 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
+/*
+ * Copyright (C) 2022, STMicroelectronics - All Rights Reserved
+ * Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics.
+ */
+
+#define LOG_CATEGORY UCLASS_CLK
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <log.h>
+#include <asm/io.h>
+#include <dm/device_compat.h>
+#include <linux/clk-provider.h>
+#include "clk-stm32-core.h"
+
+int stm32_rcc_init(struct udevice *dev,
+ const struct stm32_clock_match_data *data)
+{
+ int i;
+ u8 *cpt;
+ struct stm32mp_rcc_priv *priv = dev_get_priv(dev);
+ fdt_addr_t base = dev_read_addr(dev->parent);
+ const struct clk_stm32_clock_data *clock_data = data->clock_data;
+
+ if (base == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ priv->base = (void __iomem *)base;
+
+ /* allocate the counter of user for internal RCC gates, common for several user */
+ cpt = kzalloc(clock_data->num_gates, GFP_KERNEL);
+ if (!cpt)
+ return -ENOMEM;
+
+ priv->gate_cpt = cpt;
+
+ priv->data = clock_data;
+
+ for (i = 0; i < data->num_clocks; i++) {
+ const struct clock_config *cfg = &data->tab_clocks[i];
+ struct clk *clk = ERR_PTR(-ENOENT);
+
+ if (data->check_security && data->check_security(priv->base, cfg))
+ continue;
+
+ if (cfg->setup) {
+ clk = cfg->setup(dev, cfg);
+ clk->id = cfg->id;
+ } else {
+ dev_err(dev, "failed to register clock %s\n", cfg->name);
+ return -ENOENT;
+ }
+ }
+
+ return 0;
+}
+
+ulong clk_stm32_get_rate_by_name(const char *name)
+{
+ struct udevice *dev;
+
+ if (!uclass_get_device_by_name(UCLASS_CLK, name, &dev)) {
+ struct clk *clk = dev_get_clk_ptr(dev);
+
+ return clk_get_rate(clk);
+ }
+
+ return 0;
+}
+
+const struct clk_ops stm32_clk_ops = {
+ .enable = ccf_clk_enable,
+ .disable = ccf_clk_disable,
+ .get_rate = ccf_clk_get_rate,
+ .set_rate = ccf_clk_set_rate,
+};
+
+#define RCC_MP_ENCLRR_OFFSET 4
+
+static void clk_stm32_gate_set_state(void __iomem *base,
+ const struct clk_stm32_clock_data *data,
+ u8 *cpt, u16 gate_id, int enable)
+{
+ const struct stm32_gate_cfg *gate_cfg = &data->gates[gate_id];
+ void __iomem *addr = base + gate_cfg->reg_off;
+ u8 set_clr = gate_cfg->set_clr ? RCC_MP_ENCLRR_OFFSET : 0;
+
+ if (enable) {
+ if (cpt[gate_id]++ > 0)
+ return;
+
+ if (set_clr)
+ writel(BIT(gate_cfg->bit_idx), addr);
+ else
+ writel(readl(addr) | BIT(gate_cfg->bit_idx), addr);
+ } else {
+ if (--cpt[gate_id] > 0)
+ return;
+
+ if (set_clr)
+ writel(BIT(gate_cfg->bit_idx), addr + set_clr);
+ else
+ writel(readl(addr) & ~BIT(gate_cfg->bit_idx), addr);
+ }
+}
+
+static int clk_stm32_gate_enable(struct clk *clk)
+{
+ struct clk_stm32_gate *stm32_gate = to_clk_stm32_gate(clk);
+ struct stm32mp_rcc_priv *priv = stm32_gate->priv;
+
+ clk_stm32_gate_set_state(priv->base, priv->data, priv->gate_cpt,
+ stm32_gate->gate_id, 1);
+
+ return 0;
+}
+
+static int clk_stm32_gate_disable(struct clk *clk)
+{
+ struct clk_stm32_gate *stm32_gate = to_clk_stm32_gate(clk);
+ struct stm32mp_rcc_priv *priv = stm32_gate->priv;
+
+ clk_stm32_gate_set_state(priv->base, priv->data, priv->gate_cpt,
+ stm32_gate->gate_id, 0);
+
+ return 0;
+}
+
+static const struct clk_ops clk_stm32_gate_ops = {
+ .enable = clk_stm32_gate_enable,
+ .disable = clk_stm32_gate_disable,
+ .get_rate = clk_generic_get_rate,
+};
+
+#define UBOOT_DM_CLK_STM32_GATE "clk_stm32_gate"
+
+U_BOOT_DRIVER(clk_stm32_gate) = {
+ .name = UBOOT_DM_CLK_STM32_GATE,
+ .id = UCLASS_CLK,
+ .ops = &clk_stm32_gate_ops,
+};
+
+struct clk *clk_stm32_gate_register(struct udevice *dev,
+ const struct clock_config *cfg)
+{
+ struct stm32mp_rcc_priv *priv = dev_get_priv(dev);
+ struct stm32_clk_gate_cfg *clk_cfg = cfg->clock_cfg;
+ struct clk_stm32_gate *stm32_gate;
+ struct clk *clk;
+ int ret;
+
+ stm32_gate = kzalloc(sizeof(*stm32_gate), GFP_KERNEL);
+ if (!stm32_gate)
+ return ERR_PTR(-ENOMEM);
+
+ stm32_gate->priv = priv;
+ stm32_gate->gate_id = clk_cfg->gate_id;
+
+ clk = &stm32_gate->clk;
+ clk->flags = cfg->flags;
+
+ ret = clk_register(clk, UBOOT_DM_CLK_STM32_GATE,
+ cfg->name, cfg->parent_name);
+ if (ret) {
+ kfree(stm32_gate);
+ return ERR_PTR(ret);
+ }
+
+ return clk;
+}
+
+struct clk *
+clk_stm32_register_composite(struct udevice *dev,
+ const struct clock_config *cfg)
+{
+ struct stm32_clk_composite_cfg *composite = cfg->clock_cfg;
+ const char *const *parent_names;
+ int num_parents;
+ struct clk *clk = ERR_PTR(-ENOMEM);
+ struct clk_mux *mux = NULL;
+ struct clk_stm32_gate *gate = NULL;
+ struct clk_divider *div = NULL;
+ struct clk *mux_clk = NULL;
+ const struct clk_ops *mux_ops = NULL;
+ struct clk *gate_clk = NULL;
+ const struct clk_ops *gate_ops = NULL;
+ struct clk *div_clk = NULL;
+ const struct clk_ops *div_ops = NULL;
+ struct stm32mp_rcc_priv *priv = dev_get_priv(dev);
+ const struct clk_stm32_clock_data *data = priv->data;
+
+ if (composite->mux_id != NO_STM32_MUX) {
+ const struct stm32_mux_cfg *mux_cfg;
+
+ mux = kzalloc(sizeof(*mux), GFP_KERNEL);
+ if (!mux)
+ goto fail;
+
+ mux_cfg = &data->muxes[composite->mux_id];
+
+ mux->reg = priv->base + mux_cfg->reg_off;
+ mux->shift = mux_cfg->shift;
+ mux->mask = BIT(mux_cfg->width) - 1;
+ mux->num_parents = mux_cfg->num_parents;
+ mux->flags = 0;
+ mux->parent_names = mux_cfg->parent_names;
+
+ mux_clk = &mux->clk;
+ mux_ops = &clk_mux_ops;
+
+ parent_names = mux_cfg->parent_names;
+ num_parents = mux_cfg->num_parents;
+ } else {
+ parent_names = &cfg->parent_name;
+ num_parents = 1;
+ }
+
+ if (composite->div_id != NO_STM32_DIV) {
+ const struct stm32_div_cfg *div_cfg;
+
+ div = kzalloc(sizeof(*div), GFP_KERNEL);
+ if (!div)
+ goto fail;
+
+ div_cfg = &data->dividers[composite->div_id];
+
+ div->reg = priv->base + div_cfg->reg_off;
+ div->shift = div_cfg->shift;
+ div->width = div_cfg->width;
+ div->width = div_cfg->width;
+ div->flags = div_cfg->div_flags;
+ div->table = div_cfg->table;
+
+ div_clk = &div->clk;
+ div_ops = &clk_divider_ops;
+ }
+
+ if (composite->gate_id != NO_STM32_GATE) {
+ gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+ if (!gate)
+ goto fail;
+
+ gate->priv = priv;
+ gate->gate_id = composite->gate_id;
+
+ gate_clk = &gate->clk;
+ gate_ops = &clk_stm32_gate_ops;
+ }
+
+ clk = clk_register_composite(NULL, cfg->name,
+ parent_names, num_parents,
+ mux_clk, mux_ops,
+ div_clk, div_ops,
+ gate_clk, gate_ops,
+ cfg->flags);
+ if (IS_ERR(clk))
+ goto fail;
+
+ return clk;
+
+fail:
+ kfree(gate);
+ kfree(div);
+ kfree(mux);
+ return ERR_CAST(clk);
+}
diff --git a/drivers/clk/stm32/clk-stm32-core.h b/drivers/clk/stm32/clk-stm32-core.h
new file mode 100644
index 00000000000..53c2b467ab8
--- /dev/null
+++ b/drivers/clk/stm32/clk-stm32-core.h
@@ -0,0 +1,276 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause */
+/*
+ * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
+ * Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics.
+ */
+
+struct stm32_clock_match_data;
+
+/**
+ * struct stm32_mux_cfg - multiplexer configuration
+ *
+ * @parent_names: array of string names for all possible parents
+ * @num_parents: number of possible parents
+ * @reg_off: register controlling multiplexer
+ * @shift: shift to multiplexer bit field
+ * @width: width of the multiplexer bit field
+ * @mux_flags: hardware-specific flags
+ * @table: array of register values corresponding to the parent
+ * index
+ */
+struct stm32_mux_cfg {
+ const char * const *parent_names;
+ u8 num_parents;
+ u32 reg_off;
+ u8 shift;
+ u8 width;
+ u8 mux_flags;
+ u32 *table;
+};
+
+/**
+ * struct stm32_gate_cfg - gating configuration
+ *
+ * @reg_off: register controlling gate
+ * @bit_idx: single bit controlling gate
+ * @gate_flags: hardware-specific flags
+ * @set_clr: 0 : normal gate, 1 : has a register to clear the gate
+ */
+struct stm32_gate_cfg {
+ u32 reg_off;
+ u8 bit_idx;
+ u8 gate_flags;
+ u8 set_clr;
+};
+
+/**
+ * struct stm32_div_cfg - divider configuration
+ *
+ * @reg_off: register containing the divider
+ * @shift: shift to the divider bit field
+ * @width: width of the divider bit field
+ * @table: array of value/divider pairs, last entry should have div = 0
+ */
+struct stm32_div_cfg {
+ u32 reg_off;
+ u8 shift;
+ u8 width;
+ u8 div_flags;
+ const struct clk_div_table *table;
+};
+
+#define NO_STM32_MUX -1
+#define NO_STM32_DIV -1
+#define NO_STM32_GATE -1
+
+/**
+ * struct stm32_composite_cfg - composite configuration
+ *
+ * @mux: index of a multiplexer
+ * @gate: index of a gate
+ * @div: index of a divider
+ */
+struct stm32_composite_cfg {
+ int mux;
+ int gate;
+ int div;
+};
+
+/**
+ * struct clock_config - clock configuration
+ *
+ * @id: binding id of the clock
+ * @name: clock name
+ * @parent_name: name of the clock parent
+ * @flags: framework-specific flags
+ * @sec_id: secure id (use to known if the clock is secured or not)
+ * @clock_cfg: specific clock data configuration
+ * @setup: specific call back to reister the clock (will use
+ * clock_cfg data as input)
+ */
+struct clock_config {
+ unsigned long id;
+ const char *name;
+ const char *parent_name;
+ unsigned long flags;
+ int sec_id;
+ void *clock_cfg;
+
+ struct clk *(*setup)(struct udevice *dev,
+ const struct clock_config *cfg);
+};
+
+/**
+ * struct clk_stm32_clock_data - clock data
+ *
+ * @num_gates: number of defined gates
+ * @gates: array of gate configuration
+ * @muxes: array of multiplexer configuration
+ * @dividers: array of divider configuration
+ */
+struct clk_stm32_clock_data {
+ unsigned int num_gates;
+ const struct stm32_gate_cfg *gates;
+ const struct stm32_mux_cfg *muxes;
+ const struct stm32_div_cfg *dividers;
+};
+
+/**
+ * struct stm32_clock_match_data - clock match data
+ *
+ * @num_gates: number of clocks
+ * @tab_clocks: array of clock configuration
+ * @clock_data: definition of all gates / dividers / multiplexers
+ * @check_security: call back to check if clock is secured or not
+ */
+struct stm32_clock_match_data {
+ unsigned int num_clocks;
+ const struct clock_config *tab_clocks;
+ const struct clk_stm32_clock_data *clock_data;
+ int (*check_security)(void __iomem *base,
+ const struct clock_config *cfg);
+};
+
+/**
+ * struct stm32mp_rcc_priv - private struct for stm32mp clocks
+ *
+ * @base: base register of RCC driver
+ * @gate_cpt: array of refcounting for gate with more than one
+ * clocks as input. See explanation of Peripheral clock enabling
+ * below.
+ * @data: data for gate / divider / multiplexer configuration
+ */
+struct stm32mp_rcc_priv {
+ void __iomem *base;
+ u8 *gate_cpt;
+ const struct clk_stm32_clock_data *data;
+};
+
+int stm32_rcc_init(struct udevice *dev,
+ const struct stm32_clock_match_data *data);
+
+/**
+ * STM32 Gate
+ *
+ * PCE (Peripheral Clock Enabling) Peripheral
+ *
+ * ------------------------------ ----------
+ * | | | |
+ * | | | PERx |
+ * bus_ck | ----- | | |
+ * ------------->|------------------| | | ckg_bus_perx | |
+ * | | AND |-----|---------------->| |
+ * | -----------| | | | |
+ * | | ----- | | |
+ * | | | | |
+ * | ----- | | |
+ * Perx_EN |-----|---| GCL | Gating | | |
+ * | ----- Control | | |
+ * | | Logic | | |
+ * | | | | |
+ * | | ----- | | |
+ * | -----------| | | ckg_ker_perx | |
+ * perx_ker_ck | | AND |-----|---------------->| |
+ * ------------->|------------------| | | | |
+ * | ----- | | |
+ * | | | |
+ * | | | |
+ * ------------------------------ ----------
+
+ * Each peripheral requires a bus interface clock, named ckg_bus_perx
+ * (for peripheral ‘x’).
+ * Some peripherals (SAI, UART...) need also a dedicated clock for their
+ * communication interface, this clock is generally asynchronous with respect to
+ * the bus interface clock, and is named kernel clock (ckg_ker_perx).
+
+ * Both clocks can be gated by one Perx_EN enable bit.
+ * Then we have to manage a refcounting on gate level to avoid gate if one
+ * the bus or the Kernel was enable.
+ *
+ * Example:
+ * 1) enable the bus clock
+ * --> bus_clk ref_counting = 1, gate_ref_count = 1
+ * 2) enable the kernel clock
+ * --> perx_ker_ck ref_counting = 1, gate_ref_count = 2
+ * 3) disable kernel clock
+ *  ---> perx_ker_ck ref_counting = 0, gate_ref_count = 1
+ *  ==> then i will not gate because gate_ref_count > 0
+ * 4) disable bus clock
+ * --> bus_clk ref_counting = 0, gate_ref_count = 0
+ * ==> then i can gate (write in the register) because
+ * gate_ref_count = 0
+ */
+
+struct clk_stm32_gate {
+ struct clk clk;
+ struct stm32mp_rcc_priv *priv;
+ int gate_id;
+};
+
+#define to_clk_stm32_gate(_clk) container_of(_clk, struct clk_stm32_gate, clk)
+
+struct clk *
+clk_stm32_gate_register(struct udevice *dev,
+ const struct clock_config *cfg);
+
+struct clk *
+clk_stm32_register_composite(struct udevice *dev,
+ const struct clock_config *cfg);
+
+struct stm32_clk_gate_cfg {
+ int gate_id;
+};
+
+#define STM32_GATE(_id, _name, _parent, _flags, _gate_id, _sec_id) \
+{ \
+ .id = _id, \
+ .sec_id = _sec_id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .flags = _flags, \
+ .clock_cfg = &(struct stm32_clk_gate_cfg) { \
+ .gate_id = _gate_id, \
+ }, \
+ .setup = clk_stm32_gate_register, \
+}
+
+struct stm32_clk_composite_cfg {
+ int gate_id;
+ int mux_id;
+ int div_id;
+};
+
+#define STM32_COMPOSITE(_id, _name, _flags, _sec_id, \
+ _gate_id, _mux_id, _div_id) \
+{ \
+ .id = _id, \
+ .name = _name, \
+ .sec_id = _sec_id, \
+ .flags = _flags, \
+ .clock_cfg = &(struct stm32_clk_composite_cfg) { \
+ .gate_id = _gate_id, \
+ .mux_id = _mux_id, \
+ .div_id = _div_id, \
+ }, \
+ .setup = clk_stm32_register_composite, \
+}
+
+#define STM32_COMPOSITE_NOMUX(_id, _name, _parent, _flags, _sec_id, \
+ _gate_id, _div_id) \
+{ \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .sec_id = _sec_id, \
+ .flags = _flags, \
+ .clock_cfg = &(struct stm32_clk_composite_cfg) { \
+ .gate_id = _gate_id, \
+ .mux_id = NO_STM32_MUX, \
+ .div_id = _div_id, \
+ }, \
+ .setup = clk_stm32_register_composite, \
+}
+
+extern const struct clk_ops stm32_clk_ops;
+
+ulong clk_stm32_get_rate_by_name(const char *name);
diff --git a/drivers/clk/stm32/clk-stm32mp13.c b/drivers/clk/stm32/clk-stm32mp13.c
new file mode 100644
index 00000000000..5174ae53a1a
--- /dev/null
+++ b/drivers/clk/stm32/clk-stm32mp13.c
@@ -0,0 +1,841 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
+/*
+ * Copyright (C) 2022, STMicroelectronics - All Rights Reserved
+ * Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics.
+ */
+
+#define LOG_CATEGORY UCLASS_CLK
+
+#include <clk-uclass.h>
+#include <common.h>
+#include <dm.h>
+#include <log.h>
+#include <asm/io.h>
+#include <dt-bindings/clock/stm32mp13-clks.h>
+#include <linux/clk-provider.h>
+
+#include "clk-stm32-core.h"
+#include "stm32mp13_rcc.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const char * const adc12_src[] = {
+ "pll4_r", "ck_per", "pll3_q"
+};
+
+static const char * const dcmipp_src[] = {
+ "ck_axi", "pll2_q", "pll4_p", "ck_per",
+};
+
+static const char * const eth12_src[] = {
+ "pll4_p", "pll3_q"
+};
+
+static const char * const fdcan_src[] = {
+ "ck_hse", "pll3_q", "pll4_q", "pll4_r"
+};
+
+static const char * const fmc_src[] = {
+ "ck_axi", "pll3_r", "pll4_p", "ck_per"
+};
+
+static const char * const i2c12_src[] = {
+ "pclk1", "pll4_r", "ck_hsi", "ck_csi"
+};
+
+static const char * const i2c345_src[] = {
+ "pclk6", "pll4_r", "ck_hsi", "ck_csi"
+};
+
+static const char * const lptim1_src[] = {
+ "pclk1", "pll4_p", "pll3_q", "ck_lse", "ck_lsi", "ck_per"
+};
+
+static const char * const lptim23_src[] = {
+ "pclk3", "pll4_q", "ck_per", "ck_lse", "ck_lsi"
+};
+
+static const char * const lptim45_src[] = {
+ "pclk3", "pll4_p", "pll3_q", "ck_lse", "ck_lsi", "ck_per"
+};
+
+static const char * const mco1_src[] = {
+ "ck_hsi", "ck_hse", "ck_csi", "ck_lsi", "ck_lse"
+};
+
+static const char * const mco2_src[] = {
+ "ck_mpu", "ck_axi", "ck_mlahb", "pll4_p", "ck_hse", "ck_hsi"
+};
+
+static const char * const qspi_src[] = {
+ "ck_axi", "pll3_r", "pll4_p", "ck_per"
+};
+
+static const char * const rng1_src[] = {
+ "ck_csi", "pll4_r", "reserved", "ck_lsi"
+};
+
+static const char * const saes_src[] = {
+ "ck_axi", "ck_per", "pll4_r", "ck_lsi"
+};
+
+static const char * const sai1_src[] = {
+ "pll4_q", "pll3_q", "i2s_ckin", "ck_per", "pll3_r"
+};
+
+static const char * const sai2_src[] = {
+ "pll4_q", "pll3_q", "i2s_ckin", "ck_per", "spdif_ck_symb", "pll3_r"
+};
+
+static const char * const sdmmc12_src[] = {
+ "ck_axi", "pll3_r", "pll4_p", "ck_hsi"
+};
+
+static const char * const spdif_src[] = {
+ "pll4_p", "pll3_q", "ck_hsi"
+};
+
+static const char * const spi123_src[] = {
+ "pll4_p", "pll3_q", "i2s_ckin", "ck_per", "pll3_r"
+};
+
+static const char * const spi4_src[] = {
+ "pclk6", "pll4_q", "ck_hsi", "ck_csi", "ck_hse", "i2s_ckin"
+};
+
+static const char * const spi5_src[] = {
+ "pclk6", "pll4_q", "ck_hsi", "ck_csi", "ck_hse"
+};
+
+static const char * const stgen_src[] = {
+ "ck_hsi", "ck_hse"
+};
+
+static const char * const usart12_src[] = {
+ "pclk6", "pll3_q", "ck_hsi", "ck_csi", "pll4_q", "ck_hse"
+};
+
+static const char * const usart34578_src[] = {
+ "pclk1", "pll4_q", "ck_hsi", "ck_csi", "ck_hse"
+};
+
+static const char * const usart6_src[] = {
+ "pclk2", "pll4_q", "ck_hsi", "ck_csi", "ck_hse"
+};
+
+static const char * const usbo_src[] = {
+ "pll4_r", "ck_usbo_48m"
+};
+
+static const char * const usbphy_src[] = {
+ "ck_hse", "pll4_r", "clk-hse-div2"
+};
+
+enum enum_mux_cfg {
+ MUX_I2C12,
+ MUX_LPTIM45,
+ MUX_SPI23,
+ MUX_UART35,
+ MUX_UART78,
+ MUX_ADC1,
+ MUX_ADC2,
+ MUX_DCMIPP,
+ MUX_ETH1,
+ MUX_ETH2,
+ MUX_FDCAN,
+ MUX_FMC,
+ MUX_I2C3,
+ MUX_I2C4,
+ MUX_I2C5,
+ MUX_LPTIM1,
+ MUX_LPTIM2,
+ MUX_LPTIM3,
+ MUX_QSPI,
+ MUX_RNG1,
+ MUX_SAES,
+ MUX_SAI1,
+ MUX_SAI2,
+ MUX_SDMMC1,
+ MUX_SDMMC2,
+ MUX_SPDIF,
+ MUX_SPI1,
+ MUX_SPI4,
+ MUX_SPI5,
+ MUX_STGEN,
+ MUX_UART1,
+ MUX_UART2,
+ MUX_UART4,
+ MUX_UART6,
+ MUX_USBO,
+ MUX_USBPHY,
+ MUX_MCO1,
+ MUX_MCO2
+};
+
+#define MUX_CFG(id, src, _offset, _shift, _witdh) \
+ [id] = { \
+ .num_parents = ARRAY_SIZE(src), \
+ .parent_names = (src), \
+ .reg_off = (_offset), \
+ .shift = (_shift), \
+ .width = (_witdh), \
+ }
+
+static const struct stm32_mux_cfg stm32mp13_muxes[] = {
+ MUX_CFG(MUX_I2C12, i2c12_src, RCC_I2C12CKSELR, 0, 3),
+ MUX_CFG(MUX_LPTIM45, lptim45_src, RCC_LPTIM45CKSELR, 0, 3),
+ MUX_CFG(MUX_SPI23, spi123_src, RCC_SPI2S23CKSELR, 0, 3),
+ MUX_CFG(MUX_UART35, usart34578_src, RCC_UART35CKSELR, 0, 3),
+ MUX_CFG(MUX_UART78, usart34578_src, RCC_UART78CKSELR, 0, 3),
+ MUX_CFG(MUX_ADC1, adc12_src, RCC_ADC12CKSELR, 0, 2),
+ MUX_CFG(MUX_ADC2, adc12_src, RCC_ADC12CKSELR, 2, 2),
+ MUX_CFG(MUX_DCMIPP, dcmipp_src, RCC_DCMIPPCKSELR, 0, 2),
+ MUX_CFG(MUX_ETH1, eth12_src, RCC_ETH12CKSELR, 0, 2),
+ MUX_CFG(MUX_ETH2, eth12_src, RCC_ETH12CKSELR, 8, 2),
+ MUX_CFG(MUX_FDCAN, fdcan_src, RCC_FDCANCKSELR, 0, 2),
+ MUX_CFG(MUX_FMC, fmc_src, RCC_FMCCKSELR, 0, 2),
+ MUX_CFG(MUX_I2C3, i2c345_src, RCC_I2C345CKSELR, 0, 3),
+ MUX_CFG(MUX_I2C4, i2c345_src, RCC_I2C345CKSELR, 3, 3),
+ MUX_CFG(MUX_I2C5, i2c345_src, RCC_I2C345CKSELR, 6, 3),
+ MUX_CFG(MUX_LPTIM1, lptim1_src, RCC_LPTIM1CKSELR, 0, 3),
+ MUX_CFG(MUX_LPTIM2, lptim23_src, RCC_LPTIM23CKSELR, 0, 3),
+ MUX_CFG(MUX_LPTIM3, lptim23_src, RCC_LPTIM23CKSELR, 3, 3),
+ MUX_CFG(MUX_MCO1, mco1_src, RCC_MCO1CFGR, 0, 3),
+ MUX_CFG(MUX_MCO2, mco2_src, RCC_MCO2CFGR, 0, 3),
+ MUX_CFG(MUX_QSPI, qspi_src, RCC_QSPICKSELR, 0, 2),
+ MUX_CFG(MUX_RNG1, rng1_src, RCC_RNG1CKSELR, 0, 2),
+ MUX_CFG(MUX_SAES, saes_src, RCC_SAESCKSELR, 0, 2),
+ MUX_CFG(MUX_SAI1, sai1_src, RCC_SAI1CKSELR, 0, 3),
+ MUX_CFG(MUX_SAI2, sai2_src, RCC_SAI2CKSELR, 0, 3),
+ MUX_CFG(MUX_SDMMC1, sdmmc12_src, RCC_SDMMC12CKSELR, 0, 3),
+ MUX_CFG(MUX_SDMMC2, sdmmc12_src, RCC_SDMMC12CKSELR, 3, 3),
+ MUX_CFG(MUX_SPDIF, spdif_src, RCC_SPDIFCKSELR, 0, 2),
+ MUX_CFG(MUX_SPI1, spi123_src, RCC_SPI2S1CKSELR, 0, 3),
+ MUX_CFG(MUX_SPI4, spi4_src, RCC_SPI45CKSELR, 0, 3),
+ MUX_CFG(MUX_SPI5, spi5_src, RCC_SPI45CKSELR, 3, 3),
+ MUX_CFG(MUX_STGEN, stgen_src, RCC_STGENCKSELR, 0, 2),
+ MUX_CFG(MUX_UART1, usart12_src, RCC_UART12CKSELR, 0, 3),
+ MUX_CFG(MUX_UART2, usart12_src, RCC_UART12CKSELR, 3, 3),
+ MUX_CFG(MUX_UART4, usart34578_src, RCC_UART4CKSELR, 0, 3),
+ MUX_CFG(MUX_UART6, usart6_src, RCC_UART6CKSELR, 0, 3),
+ MUX_CFG(MUX_USBO, usbo_src, RCC_USBCKSELR, 4, 1),
+ MUX_CFG(MUX_USBPHY, usbphy_src, RCC_USBCKSELR, 0, 2),
+};
+
+enum enum_gate_cfg {
+ GATE_ZERO, /* reserved for no gate */
+ GATE_MCO1,
+ GATE_MCO2,
+ GATE_DBGCK,
+ GATE_TRACECK,
+ GATE_DDRC1,
+ GATE_DDRC1LP,
+ GATE_DDRPHYC,
+ GATE_DDRPHYCLP,
+ GATE_DDRCAPB,
+ GATE_DDRCAPBLP,
+ GATE_AXIDCG,
+ GATE_DDRPHYCAPB,
+ GATE_DDRPHYCAPBLP,
+ GATE_TIM2,
+ GATE_TIM3,
+ GATE_TIM4,
+ GATE_TIM5,
+ GATE_TIM6,
+ GATE_TIM7,
+ GATE_LPTIM1,
+ GATE_SPI2,
+ GATE_SPI3,
+ GATE_USART3,
+ GATE_UART4,
+ GATE_UART5,
+ GATE_UART7,
+ GATE_UART8,
+ GATE_I2C1,
+ GATE_I2C2,
+ GATE_SPDIF,
+ GATE_TIM1,
+ GATE_TIM8,
+ GATE_SPI1,
+ GATE_USART6,
+ GATE_SAI1,
+ GATE_SAI2,
+ GATE_DFSDM,
+ GATE_ADFSDM,
+ GATE_FDCAN,
+ GATE_LPTIM2,
+ GATE_LPTIM3,
+ GATE_LPTIM4,
+ GATE_LPTIM5,
+ GATE_VREF,
+ GATE_DTS,
+ GATE_PMBCTRL,
+ GATE_HDP,
+ GATE_SYSCFG,
+ GATE_DCMIPP,
+ GATE_DDRPERFM,
+ GATE_IWDG2APB,
+ GATE_USBPHY,
+ GATE_STGENRO,
+ GATE_LTDC,
+ GATE_TZC,
+ GATE_ETZPC,
+ GATE_IWDG1APB,
+ GATE_BSEC,
+ GATE_STGENC,
+ GATE_USART1,
+ GATE_USART2,
+ GATE_SPI4,
+ GATE_SPI5,
+ GATE_I2C3,
+ GATE_I2C4,
+ GATE_I2C5,
+ GATE_TIM12,
+ GATE_TIM13,
+ GATE_TIM14,
+ GATE_TIM15,
+ GATE_TIM16,
+ GATE_TIM17,
+ GATE_DMA1,
+ GATE_DMA2,
+ GATE_DMAMUX1,
+ GATE_DMA3,
+ GATE_DMAMUX2,
+ GATE_ADC1,
+ GATE_ADC2,
+ GATE_USBO,
+ GATE_TSC,
+ GATE_GPIOA,
+ GATE_GPIOB,
+ GATE_GPIOC,
+ GATE_GPIOD,
+ GATE_GPIOE,
+ GATE_GPIOF,
+ GATE_GPIOG,
+ GATE_GPIOH,
+ GATE_GPIOI,
+ GATE_PKA,
+ GATE_SAES,
+ GATE_CRYP1,
+ GATE_HASH1,
+ GATE_RNG1,
+ GATE_BKPSRAM,
+ GATE_AXIMC,
+ GATE_MCE,
+ GATE_ETH1CK,
+ GATE_ETH1TX,
+ GATE_ETH1RX,
+ GATE_ETH1MAC,
+ GATE_FMC,
+ GATE_QSPI,
+ GATE_SDMMC1,
+ GATE_SDMMC2,
+ GATE_CRC1,
+ GATE_USBH,
+ GATE_ETH2CK,
+ GATE_ETH2TX,
+ GATE_ETH2RX,
+ GATE_ETH2MAC,
+ GATE_ETH1STP,
+ GATE_ETH2STP,
+ GATE_MDMA
+};
+
+#define GATE_CFG(id, _offset, _bit_idx, _offset_clr) \
+ [id] = { \
+ .reg_off = (_offset), \
+ .bit_idx = (_bit_idx), \
+ .set_clr = (_offset_clr), \
+ }
+
+static const struct stm32_gate_cfg stm32mp13_gates[] = {
+ GATE_CFG(GATE_MCO1, RCC_MCO1CFGR, 12, 0),
+ GATE_CFG(GATE_MCO2, RCC_MCO2CFGR, 12, 0),
+ GATE_CFG(GATE_DBGCK, RCC_DBGCFGR, 8, 0),
+ GATE_CFG(GATE_TRACECK, RCC_DBGCFGR, 9, 0),
+ GATE_CFG(GATE_DDRC1, RCC_DDRITFCR, 0, 0),
+ GATE_CFG(GATE_DDRC1LP, RCC_DDRITFCR, 1, 0),
+ GATE_CFG(GATE_DDRPHYC, RCC_DDRITFCR, 4, 0),
+ GATE_CFG(GATE_DDRPHYCLP, RCC_DDRITFCR, 5, 0),
+ GATE_CFG(GATE_DDRCAPB, RCC_DDRITFCR, 6, 0),
+ GATE_CFG(GATE_DDRCAPBLP, RCC_DDRITFCR, 7, 0),
+ GATE_CFG(GATE_AXIDCG, RCC_DDRITFCR, 8, 0),
+ GATE_CFG(GATE_DDRPHYCAPB, RCC_DDRITFCR, 9, 0),
+ GATE_CFG(GATE_DDRPHYCAPBLP, RCC_DDRITFCR, 10, 0),
+ GATE_CFG(GATE_TIM2, RCC_MP_APB1ENSETR, 0, 1),
+ GATE_CFG(GATE_TIM3, RCC_MP_APB1ENSETR, 1, 1),
+ GATE_CFG(GATE_TIM4, RCC_MP_APB1ENSETR, 2, 1),
+ GATE_CFG(GATE_TIM5, RCC_MP_APB1ENSETR, 3, 1),
+ GATE_CFG(GATE_TIM6, RCC_MP_APB1ENSETR, 4, 1),
+ GATE_CFG(GATE_TIM7, RCC_MP_APB1ENSETR, 5, 1),
+ GATE_CFG(GATE_LPTIM1, RCC_MP_APB1ENSETR, 9, 1),
+ GATE_CFG(GATE_SPI2, RCC_MP_APB1ENSETR, 11, 1),
+ GATE_CFG(GATE_SPI3, RCC_MP_APB1ENSETR, 12, 1),
+ GATE_CFG(GATE_USART3, RCC_MP_APB1ENSETR, 15, 1),
+ GATE_CFG(GATE_UART4, RCC_MP_APB1ENSETR, 16, 1),
+ GATE_CFG(GATE_UART5, RCC_MP_APB1ENSETR, 17, 1),
+ GATE_CFG(GATE_UART7, RCC_MP_APB1ENSETR, 18, 1),
+ GATE_CFG(GATE_UART8, RCC_MP_APB1ENSETR, 19, 1),
+ GATE_CFG(GATE_I2C1, RCC_MP_APB1ENSETR, 21, 1),
+ GATE_CFG(GATE_I2C2, RCC_MP_APB1ENSETR, 22, 1),
+ GATE_CFG(GATE_SPDIF, RCC_MP_APB1ENSETR, 26, 1),
+ GATE_CFG(GATE_TIM1, RCC_MP_APB2ENSETR, 0, 1),
+ GATE_CFG(GATE_TIM8, RCC_MP_APB2ENSETR, 1, 1),
+ GATE_CFG(GATE_SPI1, RCC_MP_APB2ENSETR, 8, 1),
+ GATE_CFG(GATE_USART6, RCC_MP_APB2ENSETR, 13, 1),
+ GATE_CFG(GATE_SAI1, RCC_MP_APB2ENSETR, 16, 1),
+ GATE_CFG(GATE_SAI2, RCC_MP_APB2ENSETR, 17, 1),
+ GATE_CFG(GATE_DFSDM, RCC_MP_APB2ENSETR, 20, 1),
+ GATE_CFG(GATE_ADFSDM, RCC_MP_APB2ENSETR, 21, 1),
+ GATE_CFG(GATE_FDCAN, RCC_MP_APB2ENSETR, 24, 1),
+ GATE_CFG(GATE_LPTIM2, RCC_MP_APB3ENSETR, 0, 1),
+ GATE_CFG(GATE_LPTIM3, RCC_MP_APB3ENSETR, 1, 1),
+ GATE_CFG(GATE_LPTIM4, RCC_MP_APB3ENSETR, 2, 1),
+ GATE_CFG(GATE_LPTIM5, RCC_MP_APB3ENSETR, 3, 1),
+ GATE_CFG(GATE_VREF, RCC_MP_APB3ENSETR, 13, 1),
+ GATE_CFG(GATE_DTS, RCC_MP_APB3ENSETR, 16, 1),
+ GATE_CFG(GATE_PMBCTRL, RCC_MP_APB3ENSETR, 17, 1),
+ GATE_CFG(GATE_HDP, RCC_MP_APB3ENSETR, 20, 1),
+ GATE_CFG(GATE_SYSCFG, RCC_MP_NS_APB3ENSETR, 0, 1),
+ GATE_CFG(GATE_DCMIPP, RCC_MP_APB4ENSETR, 1, 1),
+ GATE_CFG(GATE_DDRPERFM, RCC_MP_APB4ENSETR, 8, 1),
+ GATE_CFG(GATE_IWDG2APB, RCC_MP_APB4ENSETR, 15, 1),
+ GATE_CFG(GATE_USBPHY, RCC_MP_APB4ENSETR, 16, 1),
+ GATE_CFG(GATE_STGENRO, RCC_MP_APB4ENSETR, 20, 1),
+ GATE_CFG(GATE_LTDC, RCC_MP_NS_APB4ENSETR, 0, 1),
+ GATE_CFG(GATE_TZC, RCC_MP_APB5ENSETR, 11, 1),
+ GATE_CFG(GATE_ETZPC, RCC_MP_APB5ENSETR, 13, 1),
+ GATE_CFG(GATE_IWDG1APB, RCC_MP_APB5ENSETR, 15, 1),
+ GATE_CFG(GATE_BSEC, RCC_MP_APB5ENSETR, 16, 1),
+ GATE_CFG(GATE_STGENC, RCC_MP_APB5ENSETR, 20, 1),
+ GATE_CFG(GATE_USART1, RCC_MP_APB6ENSETR, 0, 1),
+ GATE_CFG(GATE_USART2, RCC_MP_APB6ENSETR, 1, 1),
+ GATE_CFG(GATE_SPI4, RCC_MP_APB6ENSETR, 2, 1),
+ GATE_CFG(GATE_SPI5, RCC_MP_APB6ENSETR, 3, 1),
+ GATE_CFG(GATE_I2C3, RCC_MP_APB6ENSETR, 4, 1),
+ GATE_CFG(GATE_I2C4, RCC_MP_APB6ENSETR, 5, 1),
+ GATE_CFG(GATE_I2C5, RCC_MP_APB6ENSETR, 6, 1),
+ GATE_CFG(GATE_TIM12, RCC_MP_APB6ENSETR, 7, 1),
+ GATE_CFG(GATE_TIM13, RCC_MP_APB6ENSETR, 8, 1),
+ GATE_CFG(GATE_TIM14, RCC_MP_APB6ENSETR, 9, 1),
+ GATE_CFG(GATE_TIM15, RCC_MP_APB6ENSETR, 10, 1),
+ GATE_CFG(GATE_TIM16, RCC_MP_APB6ENSETR, 11, 1),
+ GATE_CFG(GATE_TIM17, RCC_MP_APB6ENSETR, 12, 1),
+ GATE_CFG(GATE_DMA1, RCC_MP_AHB2ENSETR, 0, 1),
+ GATE_CFG(GATE_DMA2, RCC_MP_AHB2ENSETR, 1, 1),
+ GATE_CFG(GATE_DMAMUX1, RCC_MP_AHB2ENSETR, 2, 1),
+ GATE_CFG(GATE_DMA3, RCC_MP_AHB2ENSETR, 3, 1),
+ GATE_CFG(GATE_DMAMUX2, RCC_MP_AHB2ENSETR, 4, 1),
+ GATE_CFG(GATE_ADC1, RCC_MP_AHB2ENSETR, 5, 1),
+ GATE_CFG(GATE_ADC2, RCC_MP_AHB2ENSETR, 6, 1),
+ GATE_CFG(GATE_USBO, RCC_MP_AHB2ENSETR, 8, 1),
+ GATE_CFG(GATE_TSC, RCC_MP_AHB4ENSETR, 15, 1),
+ GATE_CFG(GATE_GPIOA, RCC_MP_NS_AHB4ENSETR, 0, 1),
+ GATE_CFG(GATE_GPIOB, RCC_MP_NS_AHB4ENSETR, 1, 1),
+ GATE_CFG(GATE_GPIOC, RCC_MP_NS_AHB4ENSETR, 2, 1),
+ GATE_CFG(GATE_GPIOD, RCC_MP_NS_AHB4ENSETR, 3, 1),
+ GATE_CFG(GATE_GPIOE, RCC_MP_NS_AHB4ENSETR, 4, 1),
+ GATE_CFG(GATE_GPIOF, RCC_MP_NS_AHB4ENSETR, 5, 1),
+ GATE_CFG(GATE_GPIOG, RCC_MP_NS_AHB4ENSETR, 6, 1),
+ GATE_CFG(GATE_GPIOH, RCC_MP_NS_AHB4ENSETR, 7, 1),
+ GATE_CFG(GATE_GPIOI, RCC_MP_NS_AHB4ENSETR, 8, 1),
+ GATE_CFG(GATE_PKA, RCC_MP_AHB5ENSETR, 2, 1),
+ GATE_CFG(GATE_SAES, RCC_MP_AHB5ENSETR, 3, 1),
+ GATE_CFG(GATE_CRYP1, RCC_MP_AHB5ENSETR, 4, 1),
+ GATE_CFG(GATE_HASH1, RCC_MP_AHB5ENSETR, 5, 1),
+ GATE_CFG(GATE_RNG1, RCC_MP_AHB5ENSETR, 6, 1),
+ GATE_CFG(GATE_BKPSRAM, RCC_MP_AHB5ENSETR, 8, 1),
+ GATE_CFG(GATE_AXIMC, RCC_MP_AHB5ENSETR, 16, 1),
+ GATE_CFG(GATE_MCE, RCC_MP_AHB6ENSETR, 1, 1),
+ GATE_CFG(GATE_ETH1CK, RCC_MP_AHB6ENSETR, 7, 1),
+ GATE_CFG(GATE_ETH1TX, RCC_MP_AHB6ENSETR, 8, 1),
+ GATE_CFG(GATE_ETH1RX, RCC_MP_AHB6ENSETR, 9, 1),
+ GATE_CFG(GATE_ETH1MAC, RCC_MP_AHB6ENSETR, 10, 1),
+ GATE_CFG(GATE_FMC, RCC_MP_AHB6ENSETR, 12, 1),
+ GATE_CFG(GATE_QSPI, RCC_MP_AHB6ENSETR, 14, 1),
+ GATE_CFG(GATE_SDMMC1, RCC_MP_AHB6ENSETR, 16, 1),
+ GATE_CFG(GATE_SDMMC2, RCC_MP_AHB6ENSETR, 17, 1),
+ GATE_CFG(GATE_CRC1, RCC_MP_AHB6ENSETR, 20, 1),
+ GATE_CFG(GATE_USBH, RCC_MP_AHB6ENSETR, 24, 1),
+ GATE_CFG(GATE_ETH2CK, RCC_MP_AHB6ENSETR, 27, 1),
+ GATE_CFG(GATE_ETH2TX, RCC_MP_AHB6ENSETR, 28, 1),
+ GATE_CFG(GATE_ETH2RX, RCC_MP_AHB6ENSETR, 29, 1),
+ GATE_CFG(GATE_ETH2MAC, RCC_MP_AHB6ENSETR, 30, 1),
+ GATE_CFG(GATE_ETH1STP, RCC_MP_AHB6LPENSETR, 11, 1),
+ GATE_CFG(GATE_ETH2STP, RCC_MP_AHB6LPENSETR, 31, 1),
+ GATE_CFG(GATE_MDMA, RCC_MP_NS_AHB6ENSETR, 0, 1),
+};
+
+static const struct clk_div_table ck_trace_div_table[] = {
+ { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 },
+ { 4, 16 }, { 5, 16 }, { 6, 16 }, { 7, 16 },
+ { 0 },
+};
+
+enum enum_div_cfg {
+ DIV_MCO1,
+ DIV_MCO2,
+ DIV_TRACE,
+ DIV_ETH1PTP,
+ DIV_ETH2PTP,
+ LAST_DIV
+};
+
+#define DIV_CFG(id, _offset, _shift, _width, _flags, _table) \
+ [id] = { \
+ .reg_off = _offset, \
+ .shift = _shift, \
+ .width = _width, \
+ .div_flags = _flags, \
+ .table = _table, \
+ }
+
+static const struct stm32_div_cfg stm32mp13_dividers[LAST_DIV] = {
+ DIV_CFG(DIV_MCO1, RCC_MCO1CFGR, 4, 4, 0, NULL),
+ DIV_CFG(DIV_MCO2, RCC_MCO2CFGR, 4, 4, 0, NULL),
+ DIV_CFG(DIV_TRACE, RCC_DBGCFGR, 0, 3, 0, ck_trace_div_table),
+ DIV_CFG(DIV_ETH1PTP, RCC_ETH12CKSELR, 4, 4, 0, NULL),
+ DIV_CFG(DIV_ETH2PTP, RCC_ETH12CKSELR, 12, 4, 0, NULL),
+};
+
+struct clk_stm32_securiy {
+ u16 offset;
+ u8 bit_idx;
+};
+
+enum securit_clk {
+ SECF_NONE,
+ SECF_LPTIM2,
+ SECF_LPTIM3,
+ SECF_VREF,
+ SECF_DCMIPP,
+ SECF_USBPHY,
+ SECF_RTC,
+ SECF_TZC,
+ SECF_ETZPC,
+ SECF_IWDG1,
+ SECF_BSEC,
+ SECF_STGENC,
+ SECF_STGENRO,
+ SECF_USART1,
+ SECF_USART2,
+ SECF_SPI4,
+ SECF_SPI5,
+ SECF_I2C3,
+ SECF_I2C4,
+ SECF_I2C5,
+ SECF_TIM12,
+ SECF_TIM13,
+ SECF_TIM14,
+ SECF_TIM15,
+ SECF_TIM16,
+ SECF_TIM17,
+ SECF_DMA3,
+ SECF_DMAMUX2,
+ SECF_ADC1,
+ SECF_ADC2,
+ SECF_USBO,
+ SECF_TSC,
+ SECF_PKA,
+ SECF_SAES,
+ SECF_CRYP1,
+ SECF_HASH1,
+ SECF_RNG1,
+ SECF_BKPSRAM,
+ SECF_MCE,
+ SECF_FMC,
+ SECF_QSPI,
+ SECF_SDMMC1,
+ SECF_SDMMC2,
+ SECF_ETH1CK,
+ SECF_ETH1TX,
+ SECF_ETH1RX,
+ SECF_ETH1MAC,
+ SECF_ETH1STP,
+ SECF_ETH2CK,
+ SECF_ETH2TX,
+ SECF_ETH2RX,
+ SECF_ETH2MAC,
+ SECF_ETH2STP,
+ SECF_MCO1,
+ SECF_MCO2
+};
+
+#define SECF(_sec_id, _offset, _bit_idx) \
+ [_sec_id] = { \
+ .offset = _offset, \
+ .bit_idx = _bit_idx, \
+ }
+
+static const struct clk_stm32_securiy stm32mp13_security[] = {
+ SECF(SECF_LPTIM2, RCC_APB3SECSR, RCC_APB3SECSR_LPTIM2SECF),
+ SECF(SECF_LPTIM3, RCC_APB3SECSR, RCC_APB3SECSR_LPTIM3SECF),
+ SECF(SECF_VREF, RCC_APB3SECSR, RCC_APB3SECSR_VREFSECF),
+ SECF(SECF_DCMIPP, RCC_APB4SECSR, RCC_APB4SECSR_DCMIPPSECF),
+ SECF(SECF_USBPHY, RCC_APB4SECSR, RCC_APB4SECSR_USBPHYSECF),
+ SECF(SECF_RTC, RCC_APB5SECSR, RCC_APB5SECSR_RTCSECF),
+ SECF(SECF_TZC, RCC_APB5SECSR, RCC_APB5SECSR_TZCSECF),
+ SECF(SECF_ETZPC, RCC_APB5SECSR, RCC_APB5SECSR_ETZPCSECF),
+ SECF(SECF_IWDG1, RCC_APB5SECSR, RCC_APB5SECSR_IWDG1SECF),
+ SECF(SECF_BSEC, RCC_APB5SECSR, RCC_APB5SECSR_BSECSECF),
+ SECF(SECF_STGENC, RCC_APB5SECSR, RCC_APB5SECSR_STGENCSECF),
+ SECF(SECF_STGENRO, RCC_APB5SECSR, RCC_APB5SECSR_STGENROSECF),
+ SECF(SECF_USART1, RCC_APB6SECSR, RCC_APB6SECSR_USART1SECF),
+ SECF(SECF_USART2, RCC_APB6SECSR, RCC_APB6SECSR_USART2SECF),
+ SECF(SECF_SPI4, RCC_APB6SECSR, RCC_APB6SECSR_SPI4SECF),
+ SECF(SECF_SPI5, RCC_APB6SECSR, RCC_APB6SECSR_SPI5SECF),
+ SECF(SECF_I2C3, RCC_APB6SECSR, RCC_APB6SECSR_I2C3SECF),
+ SECF(SECF_I2C4, RCC_APB6SECSR, RCC_APB6SECSR_I2C4SECF),
+ SECF(SECF_I2C5, RCC_APB6SECSR, RCC_APB6SECSR_I2C5SECF),
+ SECF(SECF_TIM12, RCC_APB6SECSR, RCC_APB6SECSR_TIM12SECF),
+ SECF(SECF_TIM13, RCC_APB6SECSR, RCC_APB6SECSR_TIM13SECF),
+ SECF(SECF_TIM14, RCC_APB6SECSR, RCC_APB6SECSR_TIM14SECF),
+ SECF(SECF_TIM15, RCC_APB6SECSR, RCC_APB6SECSR_TIM15SECF),
+ SECF(SECF_TIM16, RCC_APB6SECSR, RCC_APB6SECSR_TIM16SECF),
+ SECF(SECF_TIM17, RCC_APB6SECSR, RCC_APB6SECSR_TIM17SECF),
+ SECF(SECF_DMA3, RCC_AHB2SECSR, RCC_AHB2SECSR_DMA3SECF),
+ SECF(SECF_DMAMUX2, RCC_AHB2SECSR, RCC_AHB2SECSR_DMAMUX2SECF),
+ SECF(SECF_ADC1, RCC_AHB2SECSR, RCC_AHB2SECSR_ADC1SECF),
+ SECF(SECF_ADC2, RCC_AHB2SECSR, RCC_AHB2SECSR_ADC2SECF),
+ SECF(SECF_USBO, RCC_AHB2SECSR, RCC_AHB2SECSR_USBOSECF),
+ SECF(SECF_TSC, RCC_AHB4SECSR, RCC_AHB4SECSR_TSCSECF),
+ SECF(SECF_PKA, RCC_AHB5SECSR, RCC_AHB5SECSR_PKASECF),
+ SECF(SECF_SAES, RCC_AHB5SECSR, RCC_AHB5SECSR_SAESSECF),
+ SECF(SECF_CRYP1, RCC_AHB5SECSR, RCC_AHB5SECSR_CRYP1SECF),
+ SECF(SECF_HASH1, RCC_AHB5SECSR, RCC_AHB5SECSR_HASH1SECF),
+ SECF(SECF_RNG1, RCC_AHB5SECSR, RCC_AHB5SECSR_RNG1SECF),
+ SECF(SECF_BKPSRAM, RCC_AHB5SECSR, RCC_AHB5SECSR_BKPSRAMSECF),
+ SECF(SECF_MCE, RCC_AHB6SECSR, RCC_AHB6SECSR_MCESECF),
+ SECF(SECF_FMC, RCC_AHB6SECSR, RCC_AHB6SECSR_FMCSECF),
+ SECF(SECF_QSPI, RCC_AHB6SECSR, RCC_AHB6SECSR_QSPISECF),
+ SECF(SECF_SDMMC1, RCC_AHB6SECSR, RCC_AHB6SECSR_SDMMC1SECF),
+ SECF(SECF_SDMMC2, RCC_AHB6SECSR, RCC_AHB6SECSR_SDMMC2SECF),
+ SECF(SECF_ETH1CK, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH1CKSECF),
+ SECF(SECF_ETH1TX, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH1TXSECF),
+ SECF(SECF_ETH1RX, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH1RXSECF),
+ SECF(SECF_ETH1MAC, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH1MACSECF),
+ SECF(SECF_ETH1STP, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH1STPSECF),
+ SECF(SECF_ETH2CK, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH2CKSECF),
+ SECF(SECF_ETH2TX, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH2TXSECF),
+ SECF(SECF_ETH2RX, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH2RXSECF),
+ SECF(SECF_ETH2MAC, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH2MACSECF),
+ SECF(SECF_ETH2STP, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH2STPSECF),
+ SECF(SECF_MCO1, RCC_SECCFGR, RCC_SECCFGR_MCO1SECF),
+ SECF(SECF_MCO2, RCC_SECCFGR, RCC_SECCFGR_MCO2SECF),
+};
+
+#define PCLK(_id, _name, _parent, _flags, _gate_id, _sec_id) \
+ STM32_GATE(_id, _name, _parent, _flags, _gate_id, _sec_id)
+
+#define TIMER(_id, _name, _parent, _flags, _gate_id, _sec_id) \
+ STM32_GATE(_id, _name, _parent, ((_flags) | CLK_SET_RATE_PARENT), \
+ _gate_id, _sec_id)
+
+#define KCLK(_id, _name, _flags, _gate_id, _mux_id, _sec_id) \
+ STM32_COMPOSITE(_id, _name, _flags, _sec_id, \
+ _gate_id, _mux_id, NO_STM32_DIV)
+
+static const struct clock_config stm32mp13_clock_cfg[] = {
+ TIMER(TIM2_K, "tim2_k", "timg1_ck", 0, GATE_TIM2, SECF_NONE),
+ TIMER(TIM3_K, "tim3_k", "timg1_ck", 0, GATE_TIM3, SECF_NONE),
+ TIMER(TIM4_K, "tim4_k", "timg1_ck", 0, GATE_TIM4, SECF_NONE),
+ TIMER(TIM5_K, "tim5_k", "timg1_ck", 0, GATE_TIM5, SECF_NONE),
+ TIMER(TIM6_K, "tim6_k", "timg1_ck", 0, GATE_TIM6, SECF_NONE),
+ TIMER(TIM7_K, "tim7_k", "timg1_ck", 0, GATE_TIM7, SECF_NONE),
+ TIMER(TIM1_K, "tim1_k", "timg2_ck", 0, GATE_TIM1, SECF_NONE),
+ TIMER(TIM8_K, "tim8_k", "timg2_ck", 0, GATE_TIM8, SECF_NONE),
+ TIMER(TIM12_K, "tim12_k", "timg3_ck", 0, GATE_TIM12, SECF_TIM12),
+ TIMER(TIM13_K, "tim13_k", "timg3_ck", 0, GATE_TIM13, SECF_TIM13),
+ TIMER(TIM14_K, "tim14_k", "timg3_ck", 0, GATE_TIM14, SECF_TIM14),
+ TIMER(TIM15_K, "tim15_k", "timg3_ck", 0, GATE_TIM15, SECF_TIM15),
+ TIMER(TIM16_K, "tim16_k", "timg3_ck", 0, GATE_TIM16, SECF_TIM16),
+ TIMER(TIM17_K, "tim17_k", "timg3_ck", 0, GATE_TIM17, SECF_TIM17),
+
+ /* Peripheral clocks */
+ PCLK(SYSCFG, "syscfg", "pclk3", 0, GATE_SYSCFG, SECF_NONE),
+ PCLK(VREF, "vref", "pclk3", 0, GATE_VREF, SECF_VREF),
+ PCLK(PMBCTRL, "pmbctrl", "pclk3", 0, GATE_PMBCTRL, SECF_NONE),
+ PCLK(HDP, "hdp", "pclk3", 0, GATE_HDP, SECF_NONE),
+ PCLK(IWDG2, "iwdg2", "pclk4", 0, GATE_IWDG2APB, SECF_NONE),
+ PCLK(STGENRO, "stgenro", "pclk4", 0, GATE_STGENRO, SECF_STGENRO),
+ PCLK(TZPC, "tzpc", "pclk5", 0, GATE_TZC, SECF_TZC),
+ PCLK(IWDG1, "iwdg1", "pclk5", 0, GATE_IWDG1APB, SECF_IWDG1),
+ PCLK(BSEC, "bsec", "pclk5", 0, GATE_BSEC, SECF_BSEC),
+ PCLK(DMA1, "dma1", "ck_mlahb", 0, GATE_DMA1, SECF_NONE),
+ PCLK(DMA2, "dma2", "ck_mlahb", 0, GATE_DMA2, SECF_NONE),
+ PCLK(DMAMUX1, "dmamux1", "ck_mlahb", 0, GATE_DMAMUX1, SECF_NONE),
+ PCLK(DMAMUX2, "dmamux2", "ck_mlahb", 0, GATE_DMAMUX2, SECF_DMAMUX2),
+ PCLK(ADC1, "adc1", "ck_mlahb", 0, GATE_ADC1, SECF_ADC1),
+ PCLK(ADC2, "adc2", "ck_mlahb", 0, GATE_ADC2, SECF_ADC2),
+ PCLK(GPIOA, "gpioa", "pclk4", 0, GATE_GPIOA, SECF_NONE),
+ PCLK(GPIOB, "gpiob", "pclk4", 0, GATE_GPIOB, SECF_NONE),
+ PCLK(GPIOC, "gpioc", "pclk4", 0, GATE_GPIOC, SECF_NONE),
+ PCLK(GPIOD, "gpiod", "pclk4", 0, GATE_GPIOD, SECF_NONE),
+ PCLK(GPIOE, "gpioe", "pclk4", 0, GATE_GPIOE, SECF_NONE),
+ PCLK(GPIOF, "gpiof", "pclk4", 0, GATE_GPIOF, SECF_NONE),
+ PCLK(GPIOG, "gpiog", "pclk4", 0, GATE_GPIOG, SECF_NONE),
+ PCLK(GPIOH, "gpioh", "pclk4", 0, GATE_GPIOH, SECF_NONE),
+ PCLK(GPIOI, "gpioi", "pclk4", 0, GATE_GPIOI, SECF_NONE),
+ PCLK(TSC, "tsc", "pclk4", 0, GATE_TSC, SECF_TZC),
+ PCLK(PKA, "pka", "ck_axi", 0, GATE_PKA, SECF_PKA),
+ PCLK(CRYP1, "cryp1", "ck_axi", 0, GATE_CRYP1, SECF_CRYP1),
+ PCLK(HASH1, "hash1", "ck_axi", 0, GATE_HASH1, SECF_HASH1),
+ PCLK(BKPSRAM, "bkpsram", "ck_axi", 0, GATE_BKPSRAM, SECF_BKPSRAM),
+ PCLK(MDMA, "mdma", "ck_axi", 0, GATE_MDMA, SECF_NONE),
+ PCLK(ETH1TX, "eth1tx", "ck_axi", 0, GATE_ETH1TX, SECF_ETH1TX),
+ PCLK(ETH1RX, "eth1rx", "ck_axi", 0, GATE_ETH1RX, SECF_ETH1RX),
+ PCLK(ETH1MAC, "eth1mac", "ck_axi", 0, GATE_ETH1MAC, SECF_ETH1MAC),
+ PCLK(ETH2TX, "eth2tx", "ck_axi", 0, GATE_ETH2TX, SECF_ETH2TX),
+ PCLK(ETH2RX, "eth2rx", "ck_axi", 0, GATE_ETH2RX, SECF_ETH2RX),
+ PCLK(ETH2MAC, "eth2mac", "ck_axi", 0, GATE_ETH2MAC, SECF_ETH2MAC),
+ PCLK(CRC1, "crc1", "ck_axi", 0, GATE_CRC1, SECF_NONE),
+ PCLK(USBH, "usbh", "ck_axi", 0, GATE_USBH, SECF_NONE),
+ PCLK(DDRPERFM, "ddrperfm", "pclk4", 0, GATE_DDRPERFM, SECF_NONE),
+ PCLK(ETH1STP, "eth1stp", "ck_axi", 0, GATE_ETH1STP, SECF_ETH1STP),
+ PCLK(ETH2STP, "eth2stp", "ck_axi", 0, GATE_ETH2STP, SECF_ETH2STP),
+
+ /* Kernel clocks */
+ KCLK(SDMMC1_K, "sdmmc1_k", 0, GATE_SDMMC1, MUX_SDMMC1, SECF_SDMMC1),
+ KCLK(SDMMC2_K, "sdmmc2_k", 0, GATE_SDMMC2, MUX_SDMMC2, SECF_SDMMC2),
+ KCLK(FMC_K, "fmc_k", 0, GATE_FMC, MUX_FMC, SECF_FMC),
+ KCLK(QSPI_K, "qspi_k", 0, GATE_QSPI, MUX_QSPI, SECF_QSPI),
+ KCLK(SPI2_K, "spi2_k", 0, GATE_SPI2, MUX_SPI23, SECF_NONE),
+ KCLK(SPI3_K, "spi3_k", 0, GATE_SPI3, MUX_SPI23, SECF_NONE),
+ KCLK(I2C1_K, "i2c1_k", 0, GATE_I2C1, MUX_I2C12, SECF_NONE),
+ KCLK(I2C2_K, "i2c2_k", 0, GATE_I2C2, MUX_I2C12, SECF_NONE),
+ KCLK(LPTIM4_K, "lptim4_k", 0, GATE_LPTIM4, MUX_LPTIM45, SECF_NONE),
+ KCLK(LPTIM5_K, "lptim5_k", 0, GATE_LPTIM5, MUX_LPTIM45, SECF_NONE),
+ KCLK(USART3_K, "usart3_k", 0, GATE_USART3, MUX_UART35, SECF_NONE),
+ KCLK(UART5_K, "uart5_k", 0, GATE_UART5, MUX_UART35, SECF_NONE),
+ KCLK(UART7_K, "uart7_k", 0, GATE_UART7, MUX_UART78, SECF_NONE),
+ KCLK(UART8_K, "uart8_k", 0, GATE_UART8, MUX_UART78, SECF_NONE),
+ KCLK(RNG1_K, "rng1_k", 0, GATE_RNG1, MUX_RNG1, SECF_RNG1),
+ KCLK(USBPHY_K, "usbphy_k", 0, GATE_USBPHY, MUX_USBPHY, SECF_USBPHY),
+ KCLK(STGEN_K, "stgen_k", 0, GATE_STGENC, MUX_STGEN, SECF_STGENC),
+ KCLK(SPDIF_K, "spdif_k", 0, GATE_SPDIF, MUX_SPDIF, SECF_NONE),
+ KCLK(SPI1_K, "spi1_k", 0, GATE_SPI1, MUX_SPI1, SECF_NONE),
+ KCLK(SPI4_K, "spi4_k", 0, GATE_SPI4, MUX_SPI4, SECF_SPI4),
+ KCLK(SPI5_K, "spi5_k", 0, GATE_SPI5, MUX_SPI5, SECF_SPI5),
+ KCLK(I2C3_K, "i2c3_k", 0, GATE_I2C3, MUX_I2C3, SECF_I2C3),
+ KCLK(I2C4_K, "i2c4_k", 0, GATE_I2C4, MUX_I2C4, SECF_I2C4),
+ KCLK(I2C5_K, "i2c5_k", 0, GATE_I2C5, MUX_I2C5, SECF_I2C5),
+ KCLK(LPTIM1_K, "lptim1_k", 0, GATE_LPTIM1, MUX_LPTIM1, SECF_NONE),
+ KCLK(LPTIM2_K, "lptim2_k", 0, GATE_LPTIM2, MUX_LPTIM2, SECF_LPTIM2),
+ KCLK(LPTIM3_K, "lptim3_k", 0, GATE_LPTIM3, MUX_LPTIM3, SECF_LPTIM3),
+ KCLK(USART1_K, "usart1_k", 0, GATE_USART1, MUX_UART1, SECF_USART1),
+ KCLK(USART2_K, "usart2_k", 0, GATE_USART2, MUX_UART2, SECF_USART2),
+ KCLK(UART4_K, "uart4_k", 0, GATE_UART4, MUX_UART4, SECF_NONE),
+ KCLK(USART6_K, "uart6_k", 0, GATE_USART6, MUX_UART6, SECF_NONE),
+ KCLK(FDCAN_K, "fdcan_k", 0, GATE_FDCAN, MUX_FDCAN, SECF_NONE),
+ KCLK(SAI1_K, "sai1_k", 0, GATE_SAI1, MUX_SAI1, SECF_NONE),
+ KCLK(SAI2_K, "sai2_k", 0, GATE_SAI2, MUX_SAI2, SECF_NONE),
+ KCLK(ADC1_K, "adc1_k", 0, GATE_ADC1, MUX_ADC1, SECF_ADC1),
+ KCLK(ADC2_K, "adc2_k", 0, GATE_ADC2, MUX_ADC2, SECF_ADC2),
+ KCLK(DCMIPP_K, "dcmipp_k", 0, GATE_DCMIPP, MUX_DCMIPP, SECF_DCMIPP),
+ KCLK(ADFSDM_K, "adfsdm_k", 0, GATE_ADFSDM, MUX_SAI1, SECF_NONE),
+ KCLK(USBO_K, "usbo_k", 0, GATE_USBO, MUX_USBO, SECF_USBO),
+ KCLK(ETH1CK_K, "eth1ck_k", 0, GATE_ETH1CK, MUX_ETH1, SECF_ETH1CK),
+ KCLK(ETH2CK_K, "eth2ck_k", 0, GATE_ETH2CK, MUX_ETH2, SECF_ETH2CK),
+ KCLK(SAES_K, "saes_k", 0, GATE_SAES, MUX_SAES, SECF_SAES),
+
+ STM32_GATE(DFSDM_K, "dfsdm_k", "ck_mlahb", 0, GATE_DFSDM, SECF_NONE),
+ STM32_GATE(LTDC_PX, "ltdc_px", "pll4_q", CLK_SET_RATE_PARENT,
+ GATE_LTDC, SECF_NONE),
+
+ STM32_GATE(DTS_K, "dts_k", "ck_lse", 0, GATE_DTS, SECF_NONE),
+
+ STM32_COMPOSITE(ETH1PTP_K, "eth1ptp_k", CLK_OPS_PARENT_ENABLE |
+ CLK_SET_RATE_NO_REPARENT, SECF_ETH1CK,
+ NO_STM32_GATE, MUX_ETH1, DIV_ETH1PTP),
+
+ STM32_COMPOSITE(ETH2PTP_K, "eth2ptp_k", CLK_OPS_PARENT_ENABLE |
+ CLK_SET_RATE_NO_REPARENT, SECF_ETH2CK,
+ NO_STM32_GATE, MUX_ETH2, DIV_ETH2PTP),
+
+ /* MCO clocks */
+ STM32_COMPOSITE(CK_MCO1, "ck_mco1", CLK_OPS_PARENT_ENABLE |
+ CLK_SET_RATE_NO_REPARENT, SECF_MCO1,
+ GATE_MCO1, MUX_MCO1, DIV_MCO1),
+
+ STM32_COMPOSITE(CK_MCO2, "ck_mco2", CLK_OPS_PARENT_ENABLE |
+ CLK_SET_RATE_NO_REPARENT, SECF_MCO2,
+ GATE_MCO2, MUX_MCO2, DIV_MCO2),
+
+ /* Debug clocks */
+ STM32_GATE(CK_DBG, "ck_sys_dbg", "ck_axi", CLK_IGNORE_UNUSED,
+ GATE_DBGCK, SECF_NONE),
+
+ STM32_COMPOSITE_NOMUX(CK_TRACE, "ck_trace", "ck_axi",
+ CLK_OPS_PARENT_ENABLE, SECF_NONE,
+ GATE_TRACECK, DIV_TRACE),
+};
+
+static int stm32mp13_check_security(void __iomem *base,
+ const struct clock_config *cfg)
+{
+ int sec_id = cfg->sec_id;
+ int secured = 0;
+
+ if (sec_id != SECF_NONE) {
+ const struct clk_stm32_securiy *secf;
+
+ secf = &stm32mp13_security[sec_id];
+ secured = !!(readl(base + secf->offset) & BIT(secf->bit_idx));
+ }
+
+ return secured;
+}
+
+static const struct stm32_clock_match_data stm32mp13_data = {
+ .tab_clocks = stm32mp13_clock_cfg,
+ .num_clocks = ARRAY_SIZE(stm32mp13_clock_cfg),
+ .clock_data = &(const struct clk_stm32_clock_data) {
+ .num_gates = ARRAY_SIZE(stm32mp13_gates),
+ .gates = stm32mp13_gates,
+ .muxes = stm32mp13_muxes,
+ .dividers = stm32mp13_dividers,
+ },
+ .check_security = stm32mp13_check_security,
+};
+
+static int stm32mp1_clk_probe(struct udevice *dev)
+{
+ struct udevice *scmi;
+ int err;
+
+ /* force SCMI probe to register all SCMI clocks */
+ uclass_get_device_by_driver(UCLASS_CLK, DM_DRIVER_GET(scmi_clock), &scmi);
+
+ err = stm32_rcc_init(dev, &stm32mp13_data);
+ if (err)
+ return err;
+
+ gd->cpu_clk = clk_stm32_get_rate_by_name("ck_mpu");
+ gd->bus_clk = clk_stm32_get_rate_by_name("ck_axi");
+
+ /* DDRPHYC father */
+ gd->mem_clk = clk_stm32_get_rate_by_name("pll2_r");
+
+ if (IS_ENABLED(CONFIG_DISPLAY_CPUINFO)) {
+ if (gd->flags & GD_FLG_RELOC) {
+ char buf[32];
+
+ log_info("Clocks:\n");
+ log_info("- MPU : %s MHz\n", strmhz(buf, gd->cpu_clk));
+ log_info("- AXI : %s MHz\n", strmhz(buf, gd->bus_clk));
+ log_info("- PER : %s MHz\n",
+ strmhz(buf, clk_stm32_get_rate_by_name("ck_per")));
+ log_info("- DDR : %s MHz\n", strmhz(buf, gd->mem_clk));
+ }
+ }
+
+ return 0;
+}
+
+U_BOOT_DRIVER(stm32mp1_clock) = {
+ .name = "stm32mp13_clk",
+ .id = UCLASS_CLK,
+ .ops = &stm32_clk_ops,
+ .priv_auto = sizeof(struct stm32mp_rcc_priv),
+ .probe = stm32mp1_clk_probe,
+};
diff --git a/drivers/clk/stm32/stm32mp13_rcc.h b/drivers/clk/stm32/stm32mp13_rcc.h
new file mode 100644
index 00000000000..e7191b428af
--- /dev/null
+++ b/drivers/clk/stm32/stm32mp13_rcc.h
@@ -0,0 +1,288 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause */
+/*
+ * Copyright (C) 2022, STMicroelectronics - All Rights Reserved
+ *
+ * Configuration settings for the STM32MP13x CPU
+ */
+
+#ifndef STM32MP13_RCC_H
+#define STM32MP13_RCC_H
+
+/* RCC registers */
+#define RCC_SECCFGR 0x0
+#define RCC_MP_SREQSETR 0x100
+#define RCC_MP_SREQCLRR 0x104
+#define RCC_MP_APRSTCR 0x108
+#define RCC_MP_APRSTSR 0x10c
+#define RCC_PWRLPDLYCR 0x110
+#define RCC_MP_GRSTCSETR 0x114
+#define RCC_BR_RSTSCLRR 0x118
+#define RCC_MP_RSTSSETR 0x11c
+#define RCC_MP_RSTSCLRR 0x120
+#define RCC_MP_IWDGFZSETR 0x124
+#define RCC_MP_IWDGFZCLRR 0x128
+#define RCC_MP_CIER 0x200
+#define RCC_MP_CIFR 0x204
+#define RCC_BDCR 0x400
+#define RCC_RDLSICR 0x404
+#define RCC_OCENSETR 0x420
+#define RCC_OCENCLRR 0x424
+#define RCC_OCRDYR 0x428
+#define RCC_HSICFGR 0x440
+#define RCC_CSICFGR 0x444
+#define RCC_MCO1CFGR 0x460
+#define RCC_MCO2CFGR 0x464
+#define RCC_DBGCFGR 0x468
+#define RCC_RCK12SELR 0x480
+#define RCC_RCK3SELR 0x484
+#define RCC_RCK4SELR 0x488
+#define RCC_PLL1CR 0x4a0
+#define RCC_PLL1CFGR1 0x4a4
+#define RCC_PLL1CFGR2 0x4a8
+#define RCC_PLL1FRACR 0x4ac
+#define RCC_PLL1CSGR 0x4b0
+#define RCC_PLL2CR 0x4d0
+#define RCC_PLL2CFGR1 0x4d4
+#define RCC_PLL2CFGR2 0x4d8
+#define RCC_PLL2FRACR 0x4dc
+#define RCC_PLL2CSGR 0x4e0
+#define RCC_PLL3CR 0x500
+#define RCC_PLL3CFGR1 0x504
+#define RCC_PLL3CFGR2 0x508
+#define RCC_PLL3FRACR 0x50c
+#define RCC_PLL3CSGR 0x510
+#define RCC_PLL4CR 0x520
+#define RCC_PLL4CFGR1 0x524
+#define RCC_PLL4CFGR2 0x528
+#define RCC_PLL4FRACR 0x52c
+#define RCC_PLL4CSGR 0x530
+#define RCC_MPCKSELR 0x540
+#define RCC_ASSCKSELR 0x544
+#define RCC_MSSCKSELR 0x548
+#define RCC_CPERCKSELR 0x54c
+#define RCC_RTCDIVR 0x560
+#define RCC_MPCKDIVR 0x564
+#define RCC_AXIDIVR 0x568
+#define RCC_MLAHBDIVR 0x56c
+#define RCC_APB1DIVR 0x570
+#define RCC_APB2DIVR 0x574
+#define RCC_APB3DIVR 0x578
+#define RCC_APB4DIVR 0x57c
+#define RCC_APB5DIVR 0x580
+#define RCC_APB6DIVR 0x584
+#define RCC_TIMG1PRER 0x5a0
+#define RCC_TIMG2PRER 0x5a4
+#define RCC_TIMG3PRER 0x5a8
+#define RCC_DDRITFCR 0x5c0
+#define RCC_I2C12CKSELR 0x600
+#define RCC_I2C345CKSELR 0x604
+#define RCC_SPI2S1CKSELR 0x608
+#define RCC_SPI2S23CKSELR 0x60c
+#define RCC_SPI45CKSELR 0x610
+#define RCC_UART12CKSELR 0x614
+#define RCC_UART35CKSELR 0x618
+#define RCC_UART4CKSELR 0x61c
+#define RCC_UART6CKSELR 0x620
+#define RCC_UART78CKSELR 0x624
+#define RCC_LPTIM1CKSELR 0x628
+#define RCC_LPTIM23CKSELR 0x62c
+#define RCC_LPTIM45CKSELR 0x630
+#define RCC_SAI1CKSELR 0x634
+#define RCC_SAI2CKSELR 0x638
+#define RCC_FDCANCKSELR 0x63c
+#define RCC_SPDIFCKSELR 0x640
+#define RCC_ADC12CKSELR 0x644
+#define RCC_SDMMC12CKSELR 0x648
+#define RCC_ETH12CKSELR 0x64c
+#define RCC_USBCKSELR 0x650
+#define RCC_QSPICKSELR 0x654
+#define RCC_FMCCKSELR 0x658
+#define RCC_RNG1CKSELR 0x65c
+#define RCC_STGENCKSELR 0x660
+#define RCC_DCMIPPCKSELR 0x664
+#define RCC_SAESCKSELR 0x668
+#define RCC_APB1RSTSETR 0x6a0
+#define RCC_APB1RSTCLRR 0x6a4
+#define RCC_APB2RSTSETR 0x6a8
+#define RCC_APB2RSTCLRR 0x6ac
+#define RCC_APB3RSTSETR 0x6b0
+#define RCC_APB3RSTCLRR 0x6b4
+#define RCC_APB4RSTSETR 0x6b8
+#define RCC_APB4RSTCLRR 0x6bc
+#define RCC_APB5RSTSETR 0x6c0
+#define RCC_APB5RSTCLRR 0x6c4
+#define RCC_APB6RSTSETR 0x6c8
+#define RCC_APB6RSTCLRR 0x6cc
+#define RCC_AHB2RSTSETR 0x6d0
+#define RCC_AHB2RSTCLRR 0x6d4
+#define RCC_AHB4RSTSETR 0x6e0
+#define RCC_AHB4RSTCLRR 0x6e4
+#define RCC_AHB5RSTSETR 0x6e8
+#define RCC_AHB5RSTCLRR 0x6ec
+#define RCC_AHB6RSTSETR 0x6f0
+#define RCC_AHB6RSTCLRR 0x6f4
+#define RCC_MP_APB1ENSETR 0x700
+#define RCC_MP_APB1ENCLRR 0x704
+#define RCC_MP_APB2ENSETR 0x708
+#define RCC_MP_APB2ENCLRR 0x70c
+#define RCC_MP_APB3ENSETR 0x710
+#define RCC_MP_APB3ENCLRR 0x714
+#define RCC_MP_S_APB3ENSETR 0x718
+#define RCC_MP_S_APB3ENCLRR 0x71c
+#define RCC_MP_NS_APB3ENSETR 0x720
+#define RCC_MP_NS_APB3ENCLRR 0x724
+#define RCC_MP_APB4ENSETR 0x728
+#define RCC_MP_APB4ENCLRR 0x72c
+#define RCC_MP_S_APB4ENSETR 0x730
+#define RCC_MP_S_APB4ENCLRR 0x734
+#define RCC_MP_NS_APB4ENSETR 0x738
+#define RCC_MP_NS_APB4ENCLRR 0x73c
+#define RCC_MP_APB5ENSETR 0x740
+#define RCC_MP_APB5ENCLRR 0x744
+#define RCC_MP_APB6ENSETR 0x748
+#define RCC_MP_APB6ENCLRR 0x74c
+#define RCC_MP_AHB2ENSETR 0x750
+#define RCC_MP_AHB2ENCLRR 0x754
+#define RCC_MP_AHB4ENSETR 0x760
+#define RCC_MP_AHB4ENCLRR 0x764
+#define RCC_MP_S_AHB4ENSETR 0x768
+#define RCC_MP_S_AHB4ENCLRR 0x76c
+#define RCC_MP_NS_AHB4ENSETR 0x770
+#define RCC_MP_NS_AHB4ENCLRR 0x774
+#define RCC_MP_AHB5ENSETR 0x778
+#define RCC_MP_AHB5ENCLRR 0x77c
+#define RCC_MP_AHB6ENSETR 0x780
+#define RCC_MP_AHB6ENCLRR 0x784
+#define RCC_MP_S_AHB6ENSETR 0x788
+#define RCC_MP_S_AHB6ENCLRR 0x78c
+#define RCC_MP_NS_AHB6ENSETR 0x790
+#define RCC_MP_NS_AHB6ENCLRR 0x794
+#define RCC_MP_APB1LPENSETR 0x800
+#define RCC_MP_APB1LPENCLRR 0x804
+#define RCC_MP_APB2LPENSETR 0x808
+#define RCC_MP_APB2LPENCLRR 0x80c
+#define RCC_MP_APB3LPENSETR 0x810
+#define RCC_MP_APB3LPENCLRR 0x814
+#define RCC_MP_S_APB3LPENSETR 0x818
+#define RCC_MP_S_APB3LPENCLRR 0x81c
+#define RCC_MP_NS_APB3LPENSETR 0x820
+#define RCC_MP_NS_APB3LPENCLRR 0x824
+#define RCC_MP_APB4LPENSETR 0x828
+#define RCC_MP_APB4LPENCLRR 0x82c
+#define RCC_MP_S_APB4LPENSETR 0x830
+#define RCC_MP_S_APB4LPENCLRR 0x834
+#define RCC_MP_NS_APB4LPENSETR 0x838
+#define RCC_MP_NS_APB4LPENCLRR 0x83c
+#define RCC_MP_APB5LPENSETR 0x840
+#define RCC_MP_APB5LPENCLRR 0x844
+#define RCC_MP_APB6LPENSETR 0x848
+#define RCC_MP_APB6LPENCLRR 0x84c
+#define RCC_MP_AHB2LPENSETR 0x850
+#define RCC_MP_AHB2LPENCLRR 0x854
+#define RCC_MP_AHB4LPENSETR 0x858
+#define RCC_MP_AHB4LPENCLRR 0x85c
+#define RCC_MP_S_AHB4LPENSETR 0x868
+#define RCC_MP_S_AHB4LPENCLRR 0x86c
+#define RCC_MP_NS_AHB4LPENSETR 0x870
+#define RCC_MP_NS_AHB4LPENCLRR 0x874
+#define RCC_MP_AHB5LPENSETR 0x878
+#define RCC_MP_AHB5LPENCLRR 0x87c
+#define RCC_MP_AHB6LPENSETR 0x880
+#define RCC_MP_AHB6LPENCLRR 0x884
+#define RCC_MP_S_AHB6LPENSETR 0x888
+#define RCC_MP_S_AHB6LPENCLRR 0x88c
+#define RCC_MP_NS_AHB6LPENSETR 0x890
+#define RCC_MP_NS_AHB6LPENCLRR 0x894
+#define RCC_MP_S_AXIMLPENSETR 0x898
+#define RCC_MP_S_AXIMLPENCLRR 0x89c
+#define RCC_MP_NS_AXIMLPENSETR 0x8a0
+#define RCC_MP_NS_AXIMLPENCLRR 0x8a4
+#define RCC_MP_MLAHBLPENSETR 0x8a8
+#define RCC_MP_MLAHBLPENCLRR 0x8ac
+#define RCC_APB3SECSR 0x8c0
+#define RCC_APB4SECSR 0x8c4
+#define RCC_APB5SECSR 0x8c8
+#define RCC_APB6SECSR 0x8cc
+#define RCC_AHB2SECSR 0x8d0
+#define RCC_AHB4SECSR 0x8d4
+#define RCC_AHB5SECSR 0x8d8
+#define RCC_AHB6SECSR 0x8dc
+#define RCC_VERR 0xff4
+#define RCC_IDR 0xff8
+#define RCC_SIDR 0xffc
+
+/* RCC_SECCFGR register fields */
+#define RCC_SECCFGR_MCO1SECF 22
+#define RCC_SECCFGR_MCO2SECF 23
+
+/* RCC_APB3SECSR register fields */
+#define RCC_APB3SECSR_LPTIM2SECF 0
+#define RCC_APB3SECSR_LPTIM3SECF 1
+#define RCC_APB3SECSR_VREFSECF 13
+
+/* RCC_APB4SECSR register fields */
+#define RCC_APB4SECSR_DCMIPPSECF 1
+#define RCC_APB4SECSR_USBPHYSECF 16
+
+/* RCC_APB5SECSR register fields */
+#define RCC_APB5SECSR_RTCSECF 8
+#define RCC_APB5SECSR_TZCSECF 11
+#define RCC_APB5SECSR_ETZPCSECF 13
+#define RCC_APB5SECSR_IWDG1SECF 15
+#define RCC_APB5SECSR_BSECSECF 16
+#define RCC_APB5SECSR_STGENCSECF 20
+#define RCC_APB5SECSR_STGENROSECF 21
+
+/* RCC_APB6SECSR register fields */
+#define RCC_APB6SECSR_USART1SECF 0
+#define RCC_APB6SECSR_USART2SECF 1
+#define RCC_APB6SECSR_SPI4SECF 2
+#define RCC_APB6SECSR_SPI5SECF 3
+#define RCC_APB6SECSR_I2C3SECF 4
+#define RCC_APB6SECSR_I2C4SECF 5
+#define RCC_APB6SECSR_I2C5SECF 6
+#define RCC_APB6SECSR_TIM12SECF 7
+#define RCC_APB6SECSR_TIM13SECF 8
+#define RCC_APB6SECSR_TIM14SECF 9
+#define RCC_APB6SECSR_TIM15SECF 10
+#define RCC_APB6SECSR_TIM16SECF 11
+#define RCC_APB6SECSR_TIM17SECF 12
+
+/* RCC_AHB2SECSR register fields */
+#define RCC_AHB2SECSR_DMA3SECF 3
+#define RCC_AHB2SECSR_DMAMUX2SECF 4
+#define RCC_AHB2SECSR_ADC1SECF 5
+#define RCC_AHB2SECSR_ADC2SECF 6
+#define RCC_AHB2SECSR_USBOSECF 8
+
+/* RCC_AHB4SECSR register fields */
+#define RCC_AHB4SECSR_TSCSECF 15
+
+/* RCC_AHB5SECSR register fields */
+#define RCC_AHB5SECSR_PKASECF 2
+#define RCC_AHB5SECSR_SAESSECF 3
+#define RCC_AHB5SECSR_CRYP1SECF 4
+#define RCC_AHB5SECSR_HASH1SECF 5
+#define RCC_AHB5SECSR_RNG1SECF 6
+#define RCC_AHB5SECSR_BKPSRAMSECF 8
+
+/* RCC_AHB6SECSR register fields */
+#define RCC_AHB6SECSR_MCESECF 1
+#define RCC_AHB6SECSR_FMCSECF 12
+#define RCC_AHB6SECSR_QSPISECF 14
+#define RCC_AHB6SECSR_SDMMC1SECF 16
+#define RCC_AHB6SECSR_SDMMC2SECF 17
+
+#define RCC_AHB6SECSR_ETH1CKSECF 7
+#define RCC_AHB6SECSR_ETH1TXSECF 8
+#define RCC_AHB6SECSR_ETH1RXSECF 9
+#define RCC_AHB6SECSR_ETH1MACSECF 10
+#define RCC_AHB6SECSR_ETH1STPSECF 11
+
+#define RCC_AHB6SECSR_ETH2CKSECF 27
+#define RCC_AHB6SECSR_ETH2TXSECF 28
+#define RCC_AHB6SECSR_ETH2RXSECF 29
+#define RCC_AHB6SECSR_ETH2MACSECF 30
+#define RCC_AHB6SECSR_ETH2STPSECF 31
+
+#endif /* STM32MP13_RCC_H */
diff --git a/drivers/clk/ti/clk-k3.c b/drivers/clk/ti/clk-k3.c
index 0dd65934b36..ba925fa3c48 100644
--- a/drivers/clk/ti/clk-k3.c
+++ b/drivers/clk/ti/clk-k3.c
@@ -80,6 +80,12 @@ static const struct soc_attr ti_k3_soc_clk_data[] = {
.data = &am62x_clk_platdata,
},
#endif
+#ifdef CONFIG_SOC_K3_AM62A7
+ {
+ .family = "AM62AX",
+ .data = &am62ax_clk_platdata,
+ },
+#endif
{ /* sentinel */ }
};
diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index df7ec484651..759921bc582 100644
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -938,7 +938,7 @@ static void set_ddr_sdram_cfg_2(const unsigned int ctrl_num,
#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
/* Use the DDR controller to auto initialize memory. */
d_init = popts->ecc_init_using_memctl;
- ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE;
+ ddr->ddr_data_init = 0xDEADBEEF;
debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init);
#else
/* Memory will be initialized via DMA, or not at all. */
@@ -1842,19 +1842,6 @@ static void set_ddr_sdram_mode(const unsigned int ctrl_num,
}
#endif
-/* DDR SDRAM Data Initialization (DDR_DATA_INIT) */
-static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr)
-{
- unsigned int init_value; /* Initialization value */
-
-#ifdef CONFIG_MEM_INIT_VALUE
- init_value = CONFIG_MEM_INIT_VALUE;
-#else
- init_value = 0xDEADBEEF;
-#endif
- ddr->ddr_data_init = init_value;
-}
-
/*
* DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL)
* The old controller on the 8540/60 doesn't have this register.
@@ -2537,7 +2524,7 @@ compute_fsl_memctl_config_regs(const unsigned int ctrl_num,
set_ddr_sdram_rcw(ctrl_num, ddr, popts, common_dimm);
set_ddr_sdram_interval(ctrl_num, ddr, popts, common_dimm);
- set_ddr_data_init(ddr);
+ ddr->ddr_data_init = 0xDEADBEEF;
set_ddr_sdram_clk_cntl(ddr, popts);
set_ddr_init_addr(ddr);
set_ddr_init_ext_addr(ddr);
diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen1.c b/drivers/ddr/fsl/mpc85xx_ddr_gen1.c
index 0f1e99eeb03..16186bdbae7 100644
--- a/drivers/ddr/fsl/mpc85xx_ddr_gen1.c
+++ b/drivers/ddr/fsl/mpc85xx_ddr_gen1.c
@@ -73,7 +73,7 @@ ddr_enable_ecc(unsigned int dram_size)
struct ccsr_ddr __iomem *ddr =
(struct ccsr_ddr __iomem *)(CFG_SYS_FSL_DDR_ADDR);
- dma_meminit(CONFIG_MEM_INIT_VALUE, dram_size);
+ dma_meminit(dram_size);
/*
* Enable errors for ECC.
diff --git a/drivers/ddr/fsl/util.c b/drivers/ddr/fsl/util.c
index e49cf6e8e3d..60051392e71 100644
--- a/drivers/ddr/fsl/util.c
+++ b/drivers/ddr/fsl/util.c
@@ -139,10 +139,10 @@ __fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params,
}
#if !defined(CONFIG_PHYS_64BIT)
- if (base >= CONFIG_MAX_MEM_MAPPED)
+ if (base >= CFG_MAX_MEM_MAPPED)
return;
- if ((base + size) >= CONFIG_MAX_MEM_MAPPED)
- size = CONFIG_MAX_MEM_MAPPED - base;
+ if ((base + size) >= CFG_MAX_MEM_MAPPED)
+ size = CFG_MAX_MEM_MAPPED - base;
#endif
if (set_ddr_laws(base, size, law_memctl) < 0) {
printf("%s: ERROR (ctrl #%d, TRGT ID=%x)\n", __func__, ctrl_num,
diff --git a/drivers/ddr/marvell/axp/ddr3_axp_config.h b/drivers/ddr/marvell/axp/ddr3_axp_config.h
index ab09e72623a..04bb4ed8f34 100644
--- a/drivers/ddr/marvell/axp/ddr3_axp_config.h
+++ b/drivers/ddr/marvell/axp/ddr3_axp_config.h
@@ -59,12 +59,10 @@
/* Marvell boards specific configurations */
#if defined(DB_78X60_PCAC)
-#undef CONFIG_SPD_EEPROM
#define STATIC_TRAINING
#endif
#if defined(DB_78X60_AMC)
-#undef CONFIG_SPD_EEPROM
#undef DRAM_ECC
#define DRAM_ECC 1
#endif
diff --git a/drivers/dma/fsl_dma.c b/drivers/dma/fsl_dma.c
index cd78e45d888..700df2236bd 100644
--- a/drivers/dma/fsl_dma.c
+++ b/drivers/dma/fsl_dma.c
@@ -133,7 +133,7 @@ int dmacpy(phys_addr_t dest, phys_addr_t src, phys_size_t count) {
*/
#if ((!defined CONFIG_MPC83xx && defined(CONFIG_DDR_ECC) && \
!defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)))
-void dma_meminit(uint val, uint size)
+void dma_meminit(uint size)
{
uint *p = 0;
uint i = 0;
@@ -142,7 +142,7 @@ void dma_meminit(uint val, uint size)
if (((uint)p & 0x1f) == 0)
ppcDcbz((ulong)p);
- *p = (uint)CONFIG_MEM_INIT_VALUE;
+ *p = (uint)0xDEADBEEF;
if (((uint)p & 0x1c) == 0x1c)
ppcDcbf((ulong)p);
diff --git a/drivers/firmware/scmi/scmi_agent-uclass.c b/drivers/firmware/scmi/scmi_agent-uclass.c
index 8f48de30c8c..9a32678617d 100644
--- a/drivers/firmware/scmi/scmi_agent-uclass.c
+++ b/drivers/firmware/scmi/scmi_agent-uclass.c
@@ -60,6 +60,7 @@ static int scmi_bind_protocols(struct udevice *dev)
{
int ret = 0;
ofnode node;
+ const char *name;
dev_for_each_subnode(node, dev) {
struct driver *drv = NULL;
@@ -71,6 +72,7 @@ static int scmi_bind_protocols(struct udevice *dev)
if (ofnode_read_u32(node, "reg", &protocol_id))
continue;
+ name = ofnode_get_name(node);
switch (protocol_id) {
case SCMI_PROTOCOL_ID_CLOCK:
if (IS_ENABLED(CONFIG_CLK_SCMI))
@@ -100,8 +102,7 @@ static int scmi_bind_protocols(struct udevice *dev)
continue;
}
- ret = device_bind(dev, drv, ofnode_get_name(node), NULL, node,
- NULL);
+ ret = device_bind(dev, drv, name, NULL, node, NULL);
if (ret)
break;
}
diff --git a/drivers/firmware/ti_sci_static_data.h b/drivers/firmware/ti_sci_static_data.h
index 5ae0556a9a4..1a461fab619 100644
--- a/drivers/firmware/ti_sci_static_data.h
+++ b/drivers/firmware/ti_sci_static_data.h
@@ -84,7 +84,7 @@ static struct ti_sci_resource_static_data rm_static_data[] = {
};
#endif /* CONFIG_SOC_K3_J721S2 */
-#if IS_ENABLED(CONFIG_SOC_K3_AM625)
+#if IS_ENABLED(CONFIG_SOC_K3_AM625) || IS_ENABLED(CONFIG_SOC_K3_AM62A7)
static struct ti_sci_resource_static_data rm_static_data[] = {
/* BC channels */
{
@@ -95,7 +95,7 @@ static struct ti_sci_resource_static_data rm_static_data[] = {
},
{ },
};
-#endif /* CONFIG_SOC_K3_AM625 */
+#endif /* CONFIG_SOC_K3_AM625 || CONFIG_SOC_K3_AM62A7 */
#else
static struct ti_sci_resource_static_data rm_static_data[] = {
diff --git a/drivers/fpga/ACEX1K.c b/drivers/fpga/ACEX1K.c
index ca49ee40a71..4c00cdf0b57 100644
--- a/drivers/fpga/ACEX1K.c
+++ b/drivers/fpga/ACEX1K.c
@@ -17,11 +17,11 @@
/* Note: The assumption is that we cannot possibly run fast enough to
* overrun the device (the Slave Parallel mode can free run at 50MHz).
- * If there is a need to operate slower, define CONFIG_FPGA_DELAY in
+ * If there is a need to operate slower, define CFG_FPGA_DELAY in
* the board config file to slow things down.
*/
-#ifndef CONFIG_FPGA_DELAY
-#define CONFIG_FPGA_DELAY()
+#ifndef CFG_FPGA_DELAY
+#define CFG_FPGA_DELAY()
#endif
#ifndef CFG_SYS_FPGA_WAIT
@@ -137,7 +137,7 @@ static int ACEX1K_ps_load(Altera_desc *desc, const void *buf, size_t bsize)
/* Wait for nSTATUS to be released (i.e. deasserted) */
ts = get_timer (0); /* get current time */
do {
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */
puts ("** Timeout waiting for STATUS to go high.\n");
(*fn->abort) (cookie);
@@ -147,7 +147,7 @@ static int ACEX1K_ps_load(Altera_desc *desc, const void *buf, size_t bsize)
} while ((*fn->status) (cookie));
/* Get ready for the burn */
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
/* Load the data */
while (bytecount < bsize) {
@@ -172,13 +172,13 @@ static int ACEX1K_ps_load(Altera_desc *desc, const void *buf, size_t bsize)
do {
/* Deassert the clock */
(*fn->clk) (false, true, cookie);
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
/* Write data */
(*fn->data) ((val & 0x01), true, cookie);
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
/* Assert the clock */
(*fn->clk) (true, true, cookie);
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
val >>= 1;
i --;
} while (i > 0);
@@ -189,7 +189,7 @@ static int ACEX1K_ps_load(Altera_desc *desc, const void *buf, size_t bsize)
#endif
}
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
putc (' '); /* terminate the dotted line */
@@ -210,9 +210,9 @@ static int ACEX1K_ps_load(Altera_desc *desc, const void *buf, size_t bsize)
*/
for (i = 0; i < 12; i++) {
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
(*fn->clk) (true, true, cookie); /* Assert the clock pin */
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
(*fn->clk) (false, true, cookie); /* Deassert the clock pin */
}
diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index 813d6a836d9..11b742eeebf 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -96,6 +96,10 @@ config FPGA_VIRTEX2
Enable Virtex-II FPGA driver for loading in BIT format. This driver
also supports many newer Xilinx FPGA families.
+config SYS_FPGA_CHECK_BUSY
+ bool "Perform busy check during load from FPGA"
+ depends on FPGA_SPARTAN2 || FPGA_SPARTAN3 || FPGA_VIRTEX2
+
config FPGA_ZYNQPL
bool "Enable Xilinx FPGA for Zynq"
depends on ARCH_ZYNQ
diff --git a/drivers/fpga/cyclon2.c b/drivers/fpga/cyclon2.c
index 3eed461e1e5..6e8a313db35 100644
--- a/drivers/fpga/cyclon2.c
+++ b/drivers/fpga/cyclon2.c
@@ -15,11 +15,11 @@
/* Note: The assumption is that we cannot possibly run fast enough to
* overrun the device (the Slave Parallel mode can free run at 50MHz).
- * If there is a need to operate slower, define CONFIG_FPGA_DELAY in
+ * If there is a need to operate slower, define CFG_FPGA_DELAY in
* the board config file to slow things down.
*/
-#ifndef CONFIG_FPGA_DELAY
-#define CONFIG_FPGA_DELAY()
+#ifndef CFG_FPGA_DELAY
+#define CFG_FPGA_DELAY()
#endif
#ifndef CFG_SYS_FPGA_WAIT
@@ -129,7 +129,7 @@ static int CYC2_ps_load(Altera_desc *desc, const void *buf, size_t bsize)
/* Wait for nSTATUS to be asserted */
ts = get_timer(0); /* get current time */
do {
- CONFIG_FPGA_DELAY();
+ CFG_FPGA_DELAY();
if (get_timer(ts) > CFG_SYS_FPGA_WAIT) {
/* check the time */
puts("** Timeout waiting for STATUS to go high.\n");
@@ -139,7 +139,7 @@ static int CYC2_ps_load(Altera_desc *desc, const void *buf, size_t bsize)
} while (!(*fn->status) (cookie));
/* Get ready for the burn */
- CONFIG_FPGA_DELAY();
+ CFG_FPGA_DELAY();
ret = (*fn->write) (buf, bsize, true, cookie);
if (ret) {
@@ -151,7 +151,7 @@ static int CYC2_ps_load(Altera_desc *desc, const void *buf, size_t bsize)
puts(" OK? ...");
#endif
- CONFIG_FPGA_DELAY();
+ CFG_FPGA_DELAY();
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
putc(' '); /* terminate the dotted line */
diff --git a/drivers/fpga/spartan2.c b/drivers/fpga/spartan2.c
index 57a4532f736..6eef87b78e1 100644
--- a/drivers/fpga/spartan2.c
+++ b/drivers/fpga/spartan2.c
@@ -10,15 +10,13 @@
#include <log.h>
#include <spartan2.h> /* Spartan-II device family */
-#undef CONFIG_SYS_FPGA_CHECK_BUSY
-
/* Note: The assumption is that we cannot possibly run fast enough to
* overrun the device (the Slave Parallel mode can free run at 50MHz).
- * If there is a need to operate slower, define CONFIG_FPGA_DELAY in
+ * If there is a need to operate slower, define CFG_FPGA_DELAY in
* the board config file to slow things down.
*/
-#ifndef CONFIG_FPGA_DELAY
-#define CONFIG_FPGA_DELAY()
+#ifndef CFG_FPGA_DELAY
+#define CFG_FPGA_DELAY()
#endif
#ifndef CFG_SYS_FPGA_WAIT
@@ -142,13 +140,13 @@ static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize)
(*fn->pgm) (true, true, cookie); /* Assert the program, commit */
/* Get ready for the burn */
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
(*fn->pgm) (false, true, cookie); /* Deassert the program, commit */
ts = get_timer (0); /* get current time */
/* Now wait for INIT and BUSY to go high */
do {
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */
puts ("** Timeout waiting for INIT to clear.\n");
(*fn->abort) (cookie); /* abort the burn */
@@ -166,9 +164,9 @@ static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize)
/* XXX - Check the error bit? */
(*fn->wdata) (data[bytecount++], true, cookie); /* write the data */
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
(*fn->clk) (false, true, cookie); /* Deassert the clock pin */
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
(*fn->clk) (true, true, cookie); /* Assert the clock pin */
#ifdef CONFIG_SYS_FPGA_CHECK_BUSY
@@ -177,9 +175,9 @@ static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize)
/* XXX - we should have a check in here somewhere to
* make sure we aren't busy forever... */
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
(*fn->clk) (false, true, cookie); /* Deassert the clock pin */
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
(*fn->clk) (true, true, cookie); /* Assert the clock pin */
if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */
@@ -196,7 +194,7 @@ static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize)
#endif
}
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
(*fn->cs) (false, true, cookie); /* Deassert the chip select */
(*fn->wr) (false, true, cookie); /* Deassert the write pin */
@@ -209,9 +207,9 @@ static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize)
ret_val = FPGA_SUCCESS;
while ((*fn->done) (cookie) == FPGA_FAIL) {
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
(*fn->clk) (false, true, cookie); /* Deassert the clock pin */
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
(*fn->clk) (true, true, cookie); /* Assert the clock pin */
if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */
@@ -332,7 +330,7 @@ static int spartan2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
/* Wait for INIT state (init low) */
ts = get_timer (0); /* get current time */
do {
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */
puts ("** Timeout waiting for INIT to start.\n");
return FPGA_FAIL;
@@ -340,13 +338,13 @@ static int spartan2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
} while (!(*fn->init) (cookie));
/* Get ready for the burn */
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
(*fn->pgm) (false, true, cookie); /* Deassert the program, commit */
ts = get_timer (0); /* get current time */
/* Now wait for INIT to go high */
do {
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */
puts ("** Timeout waiting for INIT to clear.\n");
return FPGA_FAIL;
@@ -367,13 +365,13 @@ static int spartan2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
do {
/* Deassert the clock */
(*fn->clk) (false, true, cookie);
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
/* Write data */
(*fn->wr) ((val & 0x80), true, cookie);
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
/* Assert the clock */
(*fn->clk) (true, true, cookie);
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
val <<= 1;
i --;
} while (i > 0);
@@ -384,7 +382,7 @@ static int spartan2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
#endif
}
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
putc ('\n'); /* terminate the dotted line */
@@ -397,9 +395,9 @@ static int spartan2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
while (! (*fn->done) (cookie)) {
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
(*fn->clk) (false, true, cookie); /* Deassert the clock pin */
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
(*fn->clk) (true, true, cookie); /* Assert the clock pin */
putc ('*');
diff --git a/drivers/fpga/spartan3.c b/drivers/fpga/spartan3.c
index fdec89bb815..e892fa571f1 100644
--- a/drivers/fpga/spartan3.c
+++ b/drivers/fpga/spartan3.c
@@ -15,15 +15,13 @@
#include <log.h>
#include <spartan3.h> /* Spartan-II device family */
-#undef CONFIG_SYS_FPGA_CHECK_BUSY
-
/* Note: The assumption is that we cannot possibly run fast enough to
* overrun the device (the Slave Parallel mode can free run at 50MHz).
- * If there is a need to operate slower, define CONFIG_FPGA_DELAY in
+ * If there is a need to operate slower, define CFG_FPGA_DELAY in
* the board config file to slow things down.
*/
-#ifndef CONFIG_FPGA_DELAY
-#define CONFIG_FPGA_DELAY()
+#ifndef CFG_FPGA_DELAY
+#define CFG_FPGA_DELAY()
#endif
#ifndef CFG_SYS_FPGA_WAIT
@@ -147,13 +145,13 @@ static int spartan3_sp_load(xilinx_desc *desc, const void *buf, size_t bsize)
(*fn->pgm) (true, true, cookie); /* Assert the program, commit */
/* Get ready for the burn */
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
(*fn->pgm) (false, true, cookie); /* Deassert the program, commit */
ts = get_timer (0); /* get current time */
/* Now wait for INIT and BUSY to go high */
do {
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */
puts ("** Timeout waiting for INIT to clear.\n");
(*fn->abort) (cookie); /* abort the burn */
@@ -171,9 +169,9 @@ static int spartan3_sp_load(xilinx_desc *desc, const void *buf, size_t bsize)
/* XXX - Check the error bit? */
(*fn->wdata) (data[bytecount++], true, cookie); /* write the data */
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
(*fn->clk) (false, true, cookie); /* Deassert the clock pin */
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
(*fn->clk) (true, true, cookie); /* Assert the clock pin */
#ifdef CONFIG_SYS_FPGA_CHECK_BUSY
@@ -182,9 +180,9 @@ static int spartan3_sp_load(xilinx_desc *desc, const void *buf, size_t bsize)
/* XXX - we should have a check in here somewhere to
* make sure we aren't busy forever... */
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
(*fn->clk) (false, true, cookie); /* Deassert the clock pin */
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
(*fn->clk) (true, true, cookie); /* Assert the clock pin */
if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */
@@ -201,7 +199,7 @@ static int spartan3_sp_load(xilinx_desc *desc, const void *buf, size_t bsize)
#endif
}
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
(*fn->cs) (false, true, cookie); /* Deassert the chip select */
(*fn->wr) (false, true, cookie); /* Deassert the write pin */
@@ -216,9 +214,9 @@ static int spartan3_sp_load(xilinx_desc *desc, const void *buf, size_t bsize)
/* XXX - we should have a check in here somewhere to
* make sure we aren't busy forever... */
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
(*fn->clk) (false, true, cookie); /* Deassert the clock pin */
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
(*fn->clk) (true, true, cookie); /* Assert the clock pin */
if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */
@@ -339,7 +337,7 @@ static int spartan3_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
/* Wait for INIT state (init low) */
ts = get_timer (0); /* get current time */
do {
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */
puts ("** Timeout waiting for INIT to start.\n");
if (*fn->abort)
@@ -349,13 +347,13 @@ static int spartan3_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
} while (!(*fn->init) (cookie));
/* Get ready for the burn */
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
(*fn->pgm) (false, true, cookie); /* Deassert the program, commit */
ts = get_timer (0); /* get current time */
/* Now wait for INIT to go high */
do {
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */
puts ("** Timeout waiting for INIT to clear.\n");
if (*fn->abort)
@@ -383,13 +381,13 @@ static int spartan3_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
do {
/* Deassert the clock */
(*fn->clk) (false, true, cookie);
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
/* Write data */
(*fn->wr) ((val & 0x80), true, cookie);
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
/* Assert the clock */
(*fn->clk) (true, true, cookie);
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
val <<= 1;
i --;
} while (i > 0);
@@ -401,7 +399,7 @@ static int spartan3_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
}
}
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
putc ('\n'); /* terminate the dotted line */
@@ -416,9 +414,9 @@ static int spartan3_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
/* XXX - we should have a check in here somewhere to
* make sure we aren't busy forever... */
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
(*fn->clk) (false, true, cookie); /* Deassert the clock pin */
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
(*fn->clk) (true, true, cookie); /* Assert the clock pin */
putc ('*');
diff --git a/drivers/fpga/virtex2.c b/drivers/fpga/virtex2.c
index 8871deaea6f..fc99a5f4831 100644
--- a/drivers/fpga/virtex2.c
+++ b/drivers/fpga/virtex2.c
@@ -21,17 +21,14 @@
#include <linux/delay.h>
/*
- * If the SelectMap interface can be overrun by the processor, define
- * CONFIG_SYS_FPGA_CHECK_BUSY and/or CONFIG_FPGA_DELAY in the board
+ * If the SelectMap interface can be overrun by the processor, enable
+ * CONFIG_SYS_FPGA_CHECK_BUSY and/or define CFG_FPGA_DELAY in the board
* configuration file and add board-specific support for checking BUSY status.
* By default, assume that the SelectMap interface cannot be overrun.
*/
-#ifndef CONFIG_SYS_FPGA_CHECK_BUSY
-#undef CONFIG_SYS_FPGA_CHECK_BUSY
-#endif
-#ifndef CONFIG_FPGA_DELAY
-#define CONFIG_FPGA_DELAY()
+#ifndef CFG_FPGA_DELAY
+#define CFG_FPGA_DELAY()
#endif
/*
@@ -199,7 +196,7 @@ static int virtex2_slave_pre(xilinx_virtex2_slave_fns *fn, int cookie)
} while (!(*fn->init)(cookie));
(*fn->pgm)(false, true, cookie);
- CONFIG_FPGA_DELAY();
+ CFG_FPGA_DELAY();
if (fn->clk)
(*fn->clk)(true, true, cookie);
@@ -208,7 +205,7 @@ static int virtex2_slave_pre(xilinx_virtex2_slave_fns *fn, int cookie)
*/
ts = get_timer(0);
do {
- CONFIG_FPGA_DELAY();
+ CFG_FPGA_DELAY();
if (get_timer(ts) > CFG_SYS_FPGA_WAIT_INIT) {
printf("%s:%d: ** Timeout after %d ticks waiting for INIT to deassert.\n",
__func__, __LINE__, CFG_SYS_FPGA_WAIT_INIT);
@@ -236,7 +233,7 @@ static int virtex2_slave_post(xilinx_virtex2_slave_fns *fn,
/*
* Finished writing the data; deassert FPGA CS_B and WRITE_B signals.
*/
- CONFIG_FPGA_DELAY();
+ CFG_FPGA_DELAY();
if (fn->cs)
(*fn->cs)(false, true, cookie);
if (fn->wr)
@@ -272,9 +269,9 @@ static int virtex2_slave_post(xilinx_virtex2_slave_fns *fn,
(*fn->wbulkdata)(&dummy, 1, true, cookie);
} else {
(*fn->wdata)(0xff, true, cookie);
- CONFIG_FPGA_DELAY();
+ CFG_FPGA_DELAY();
(*fn->clk)(false, true, cookie);
- CONFIG_FPGA_DELAY();
+ CFG_FPGA_DELAY();
(*fn->clk)(true, true, cookie);
}
}
@@ -338,13 +335,13 @@ static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize)
#endif
(*fn->wdata)(data[bytecount++], true, cookie);
- CONFIG_FPGA_DELAY();
+ CFG_FPGA_DELAY();
/*
* Cycle the clock pin
*/
(*fn->clk)(false, true, cookie);
- CONFIG_FPGA_DELAY();
+ CFG_FPGA_DELAY();
(*fn->clk)(true, true, cookie);
#ifdef CONFIG_SYS_FPGA_CHECK_BUSY
@@ -475,9 +472,9 @@ static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
for (bit = 7; bit >= 0; --bit) {
unsigned char curr_bit = (curr_data >> bit) & 1;
(*fn->wdata)(curr_bit, true, cookie);
- CONFIG_FPGA_DELAY();
+ CFG_FPGA_DELAY();
(*fn->clk)(false, true, cookie);
- CONFIG_FPGA_DELAY();
+ CFG_FPGA_DELAY();
(*fn->clk)(true, true, cookie);
}
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 08b6c7bdcc4..76e19918aad 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -704,7 +704,7 @@ config SYS_I2C_BUS_MAX
depends on ARCH_OMAP2PLUS || ARCH_SOCFPGA
default 2 if TI816X
default 3 if OMAP34XX || AM33XX || AM43XX
- default 4 if ARCH_SOCFPGA || OMAP44XX || TI814X
+ default 4 if ARCH_SOCFPGA || OMAP44XX
default 5 if OMAP54XX
help
Define the maximum number of available I2C buses.
diff --git a/drivers/i2c/i2c_core.c b/drivers/i2c/i2c_core.c
index 7f65db23205..fe0cd75d94a 100644
--- a/drivers/i2c/i2c_core.c
+++ b/drivers/i2c/i2c_core.c
@@ -33,14 +33,14 @@ struct i2c_adapter *i2c_get_adapter(int index)
return i2c_adap_p;
}
-#if !defined(CONFIG_SYS_I2C_DIRECT_BUS)
+#if !defined(CFG_SYS_I2C_DIRECT_BUS)
struct i2c_bus_hose i2c_bus[CFG_SYS_NUM_I2C_BUSES] =
CFG_SYS_I2C_BUSES;
#endif
DECLARE_GLOBAL_DATA_PTR;
-#ifndef CONFIG_SYS_I2C_DIRECT_BUS
+#ifndef CFG_SYS_I2C_DIRECT_BUS
/*
* i2c_mux_set()
* -------------
@@ -237,7 +237,7 @@ int i2c_set_bus_num(unsigned int bus)
if ((bus == I2C_BUS) && (I2C_ADAP->init_done > 0))
return 0;
-#ifndef CONFIG_SYS_I2C_DIRECT_BUS
+#ifndef CFG_SYS_I2C_DIRECT_BUS
if (bus >= CFG_SYS_NUM_I2C_BUSES)
return -1;
#endif
@@ -249,7 +249,7 @@ int i2c_set_bus_num(unsigned int bus)
return -2;
}
-#ifndef CONFIG_SYS_I2C_DIRECT_BUS
+#ifndef CFG_SYS_I2C_DIRECT_BUS
i2c_mux_disconnect_all();
#endif
@@ -257,7 +257,7 @@ int i2c_set_bus_num(unsigned int bus)
if (I2C_ADAP->init_done == 0)
i2c_init_bus(bus, I2C_ADAP->speed, I2C_ADAP->slaveaddr);
-#ifndef CONFIG_SYS_I2C_DIRECT_BUS
+#ifndef CFG_SYS_I2C_DIRECT_BUS
i2c_mux_set_all();
#endif
return 0;
diff --git a/drivers/i2c/mv_i2c.c b/drivers/i2c/mv_i2c.c
index 8ee17f0a450..5bc9cd7b295 100644
--- a/drivers/i2c/mv_i2c.c
+++ b/drivers/i2c/mv_i2c.c
@@ -374,45 +374,12 @@ static int __i2c_write(struct mv_i2c *base, uchar chip, u8 *addr, int alen,
static struct mv_i2c *base_glob;
-#ifdef CONFIG_I2C_MULTI_BUS
-static unsigned long i2c_regs[CONFIG_MV_I2C_NUM] = CONFIG_MV_I2C_REG;
-static unsigned int bus_initialized[CONFIG_MV_I2C_NUM];
-static unsigned int current_bus;
-
-int i2c_set_bus_num(unsigned int bus)
-{
- if ((bus < 0) || (bus >= CONFIG_MV_I2C_NUM)) {
- printf("Bad bus: %d\n", bus);
- return -1;
- }
-
- base_glob = (struct mv_i2c *)i2c_regs[bus];
- current_bus = bus;
-
- if (!bus_initialized[current_bus]) {
- bus_initialized[current_bus] = 1;
- }
-
- return 0;
-}
-
-unsigned int i2c_get_bus_num(void)
-{
- return current_bus;
-}
-#endif
-
/* API Functions */
void i2c_init(int speed, int slaveaddr)
{
u32 val;
-#ifdef CONFIG_I2C_MULTI_BUS
- current_bus = 0;
- base_glob = (struct mv_i2c *)i2c_regs[current_bus];
-#else
base_glob = (struct mv_i2c *)CONFIG_MV_I2C_REG;
-#endif
if (speed > I2C_SPEED_STANDARD_RATE)
val = ICR_FM;
diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c
index a9c7d6e1bc2..2822749971a 100644
--- a/drivers/i2c/mvtwsi.c
+++ b/drivers/i2c/mvtwsi.c
@@ -197,13 +197,13 @@ inline uint calc_tick(uint speed)
static struct mvtwsi_registers *twsi_get_base(struct i2c_adapter *adap)
{
switch (adap->hwadapnr) {
-#ifdef CONFIG_I2C_MVTWSI_BASE0
+#ifdef CFG_I2C_MVTWSI_BASE0
case 0:
- return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE0;
+ return (struct mvtwsi_registers *)CFG_I2C_MVTWSI_BASE0;
#endif
-#ifdef CONFIG_I2C_MVTWSI_BASE1
+#ifdef CFG_I2C_MVTWSI_BASE1
case 1:
- return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE1;
+ return (struct mvtwsi_registers *)CFG_I2C_MVTWSI_BASE1;
#endif
#ifdef CONFIG_I2C_MVTWSI_BASE2
case 2:
@@ -737,13 +737,13 @@ static int twsi_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
10000);
}
-#ifdef CONFIG_I2C_MVTWSI_BASE0
+#ifdef CFG_I2C_MVTWSI_BASE0
U_BOOT_I2C_ADAP_COMPLETE(twsi0, twsi_i2c_init, twsi_i2c_probe,
twsi_i2c_read, twsi_i2c_write,
twsi_i2c_set_bus_speed,
CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)
#endif
-#ifdef CONFIG_I2C_MVTWSI_BASE1
+#ifdef CFG_I2C_MVTWSI_BASE1
U_BOOT_I2C_ADAP_COMPLETE(twsi1, twsi_i2c_init, twsi_i2c_probe,
twsi_i2c_read, twsi_i2c_write,
twsi_i2c_set_bus_speed,
diff --git a/drivers/misc/gsc.c b/drivers/misc/gsc.c
index ec24ca807b0..65c9c2c6ce3 100644
--- a/drivers/misc/gsc.c
+++ b/drivers/misc/gsc.c
@@ -77,7 +77,7 @@ enum {
GSC_SC_RST_CAUSE_MAX = 10,
};
-#if (IS_ENABLED(CONFIG_DM_I2C))
+#if CONFIG_IS_ENABLED(DM_I2C)
struct gsc_priv {
int gscver;
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index bf4d994ff69..878f867c627 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -385,6 +385,11 @@ config MMC_OMAP36XX_PINS
If unsure, say N.
+config HSMMC2_8BIT
+ bool "Enable 8-bit interface for eMMC (interface #2)"
+ depends on MMC_OMAP_HS && (OMAP44XX || OMAP54XX || DRA7XX || AM33XX || \
+ AM43XX || ARCH_KEYSTONE)
+
config SH_SDHI
bool "SuperH/Renesas ARM SoCs on-chip SDHI host controller support"
depends on ARCH_RMOBILE
@@ -820,8 +825,13 @@ config MMC_MTK
endif
+config FSL_SDHC_V2_3
+ bool
+
config FSL_ESDHC
bool "Freescale/NXP eSDHC controller support"
+ select FSL_SDHC_V2_3 if ARCH_P1010 || ARCH_BSC9131 || ARCH_BSC9132 \
+ || ARCH_C29X
help
This selects support for the eSDHC (Enhanced Secure Digital Host
Controller) found on numerous Freescale/NXP SoCs.
@@ -881,6 +891,10 @@ config FSL_USDHC
help
This enables the Ultra Secured Digital Host Controller enhancements
+config FSL_ESDHC_PIN_MUX
+ bool "Perform esdhc device-tree fixup"
+ depends on (FSL_ESDHC || FSL_ESDHC_IMX) && OF_LIBFDT
+
endmenu
config SYS_FSL_ERRATUM_ESDHC111
diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
index 5ee3ce78231..66caf683f74 100644
--- a/drivers/mmc/fsl_esdhc_imx.c
+++ b/drivers/mmc/fsl_esdhc_imx.c
@@ -1360,7 +1360,7 @@ int fsl_esdhc_mmc_init(struct bd_info *bis)
#if CONFIG_IS_ENABLED(OF_LIBFDT)
__weak int esdhc_status_fixup(void *blob, const char *compat)
{
- if (IS_ENABLED(FSL_ESDHC_PIN_MUX) && !hwconfig("esdhc")) {
+ if (IS_ENABLED(CONFIG_FSL_ESDHC_PIN_MUX) && !hwconfig("esdhc")) {
do_fixup_by_compat(blob, compat, "status", "disabled",
sizeof("disabled"), 1);
return 1;
diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig
index d8e2dec0a8d..af45ef00dae 100644
--- a/drivers/mtd/Kconfig
+++ b/drivers/mtd/Kconfig
@@ -77,6 +77,15 @@ config SYS_FLASH_CFI_WIDTH
help
This must be kept in sync with the table in include/flash.h
+config FLASH_SHOW_PROGRESS
+ int "Print out a countdown durinng writes"
+ depends on FLASH_CFI_DRIVER
+ default 45
+ help
+ If set to a non-zero value, print out countdown digits and dots.
+ Recommended value: 45 (9..1) for 80 column displays, 15 (3..1) for 40
+ column displays.
+
config CFI_FLASH
bool "Enable Driver Model for CFI Flash driver"
depends on DM_MTD
@@ -110,6 +119,13 @@ config SYS_FLASH_EMPTY_INFO
bool "Enable displaying empty sectors in flash info"
depends on FLASH_CFI_DRIVER
+config FLASH_SPANSION_S29WS_N
+ bool "Non-standard s29ws-n MirrorBit flash"
+ depends on FLASH_CFI_DRIVER
+ help
+ Enable this if the s29ws-n MirrorBit flash has non-standard addresses
+ for buffered write commands.
+
config FLASH_CFI_MTD
bool "Enable CFI MTD driver"
depends on FLASH_CFI_DRIVER
@@ -147,6 +163,18 @@ config SYS_FLASH_CHECKSUM
If the variable flashchecksum is set in the environment, perform a CRC
of the flash and print the value to console.
+config FLASH_VERIFY
+ bool "Compare writes to NOR flash with source location"
+ depends on MTD_NOR_FLASH
+ help
+ If enabled, the content of the flash (destination) is compared
+ against the source after the write operation. An error message will
+ be printed when the contents are not identical. Please note that
+ this option is useless in nearly all cases, since such flash
+ programming errors usually are detected earlier while
+ unprotecting/erasing/programming. Please only enable this option if
+ you really know what you are doing.
+
config ALTERA_QSPI
bool "Altera Generic Quad SPI Controller"
depends on DM_MTD
diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c
index c1cdd2cbc3e..f378f6fb613 100644
--- a/drivers/mtd/cfi_flash.c
+++ b/drivers/mtd/cfi_flash.c
@@ -1292,7 +1292,7 @@ void flash_print_info(flash_info_t *info)
* effect updates to digit and dots. Repeated code is nasty too, so
* we define it once here.
*/
-#ifdef CONFIG_FLASH_SHOW_PROGRESS
+#if CONFIG_FLASH_SHOW_PROGRESS
#define FLASH_SHOW_PROGRESS(scale, dots, digit, dots_sub) \
if (flash_verbose) { \
dots -= dots_sub; \
@@ -1325,7 +1325,7 @@ int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
int buffered_size;
#endif
-#ifdef CONFIG_FLASH_SHOW_PROGRESS
+#if CONFIG_FLASH_SHOW_PROGRESS
int digit = CONFIG_FLASH_SHOW_PROGRESS;
int scale = 0;
int dots = 0;
diff --git a/drivers/mtd/mtd_uboot.c b/drivers/mtd/mtd_uboot.c
index dd0b0242f95..14ce726b10d 100644
--- a/drivers/mtd/mtd_uboot.c
+++ b/drivers/mtd/mtd_uboot.c
@@ -30,8 +30,6 @@ static const char *get_mtdids(void)
#if defined(CONFIG_SYS_MTDPARTS_RUNTIME)
board_mtdparts_default(&mtdids, &mtdparts);
-#elif defined(MTDIDS_DEFAULT)
- mtdids = MTDIDS_DEFAULT;
#elif defined(CONFIG_MTDIDS_DEFAULT)
mtdids = CONFIG_MTDIDS_DEFAULT;
#endif
@@ -147,8 +145,6 @@ static const char *get_mtdparts(void)
#if defined(CONFIG_SYS_MTDPARTS_RUNTIME)
board_mtdparts_default(&mtdids, &mtdparts);
-#elif defined(MTDPARTS_DEFAULT)
- mtdparts = MTDPARTS_DEFAULT;
#elif defined(CONFIG_MTDPARTS_DEFAULT)
mtdparts = CONFIG_MTDPARTS_DEFAULT;
#endif
diff --git a/drivers/mtd/nand/core.c b/drivers/mtd/nand/core.c
index 99c29670c75..4b9dd6a9269 100644
--- a/drivers/mtd/nand/core.c
+++ b/drivers/mtd/nand/core.c
@@ -129,7 +129,7 @@ EXPORT_SYMBOL_GPL(nanddev_isreserved);
*
* Return: 0 in case of success, a negative error code otherwise.
*/
-int nanddev_erase(struct nand_device *nand, const struct nand_pos *pos)
+static int nanddev_erase(struct nand_device *nand, const struct nand_pos *pos)
{
unsigned int entry;
@@ -147,7 +147,6 @@ int nanddev_erase(struct nand_device *nand, const struct nand_pos *pos)
return nand->ops->erase(nand, pos);
}
-EXPORT_SYMBOL_GPL(nanddev_erase);
/**
* nanddev_mtd_erase() - Generic mtd->_erase() implementation for NAND devices
diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
index 0f2eaebfdbf..ab719a2ff18 100644
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig
@@ -205,6 +205,7 @@ config NAND_DENALI
config NAND_DENALI_DT
bool "Support Denali NAND controller as a DT device"
select NAND_DENALI
+ select SPL_SYS_NAND_SELF_INIT
depends on OF_CONTROL && DM_MTD
help
Enable the driver for NAND flash on platforms using a Denali NAND
@@ -259,7 +260,7 @@ config NAND_LPC32XX_SLC
config NAND_OMAP_GPMC
bool "Support OMAP GPMC NAND controller"
- depends on ARCH_OMAP2PLUS
+ depends on ARCH_OMAP2PLUS || ARCH_KEYSTONE || ARCH_K3
help
Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms.
GPMC controller is used for parallel NAND flash devices, and can
@@ -487,6 +488,10 @@ config SYS_NAND_SIZE
depends on NAND_MXC && SPL_NAND_SUPPORT
default 268435456
+config MXC_NAND_HWECC
+ bool "Hardware ECC support in MXC NAND"
+ depends on NAND_MXC
+
config NAND_MXS
bool "MXS NAND support"
depends on MX23 || MX28 || MX6 || MX7 || IMX8 || IMX8M
diff --git a/drivers/mtd/nand/raw/atmel_nand.c b/drivers/mtd/nand/raw/atmel_nand.c
index 9fbb0b57cf1..b7e473c598d 100644
--- a/drivers/mtd/nand/raw/atmel_nand.c
+++ b/drivers/mtd/nand/raw/atmel_nand.c
@@ -38,10 +38,6 @@
#ifdef CONFIG_ATMEL_NAND_HW_PMECC
-#ifdef CONFIG_SPL_BUILD
-#undef CONFIG_SYS_NAND_ONFI_DETECTION
-#endif
-
struct atmel_nand_host {
struct pmecc_regs __iomem *pmecc;
struct pmecc_errloc_regs __iomem *pmerrloc;
diff --git a/drivers/mtd/nand/raw/fsl_ifc_spl.c b/drivers/mtd/nand/raw/fsl_ifc_spl.c
index 3b464ce10ce..60a865b5667 100644
--- a/drivers/mtd/nand/raw/fsl_ifc_spl.c
+++ b/drivers/mtd/nand/raw/fsl_ifc_spl.c
@@ -278,11 +278,11 @@ void nand_boot(void)
* U-Boot header is appended at end of U-boot image, so
* calculate U-boot header address using U-boot header size.
*/
-#define CONFIG_U_BOOT_HDR_ADDR \
+#define FSL_U_BOOT_HDR_ADDR \
((CFG_SYS_NAND_U_BOOT_START + \
CFG_SYS_NAND_U_BOOT_SIZE) - \
- CONFIG_U_BOOT_HDR_SIZE)
- spl_validate_uboot(CONFIG_U_BOOT_HDR_ADDR,
+ FSL_U_BOOT_HDR_SIZE)
+ spl_validate_uboot(FSL_U_BOOT_HDR_ADDR,
CFG_SYS_NAND_U_BOOT_START);
/*
* In case of failure in validation, spl_validate_uboot would
diff --git a/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c b/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c
index a884c65d18b..28541177609 100644
--- a/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c
+++ b/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c
@@ -141,13 +141,13 @@ static void lpc32xx_nand_init(void)
clk = get_hclk_clk_rate();
writel(
- clkdiv(CONFIG_LPC32XX_NAND_MLC_TCEA_DELAY, 0x03, 24) |
- clkdiv(CONFIG_LPC32XX_NAND_MLC_BUSY_DELAY, 0x1F, 19) |
- clkdiv(CONFIG_LPC32XX_NAND_MLC_NAND_TA, 0x07, 16) |
- clkdiv(CONFIG_LPC32XX_NAND_MLC_RD_HIGH, 0x0F, 12) |
- clkdiv(CONFIG_LPC32XX_NAND_MLC_RD_LOW, 0x0F, 8) |
- clkdiv(CONFIG_LPC32XX_NAND_MLC_WR_HIGH, 0x0F, 4) |
- clkdiv(CONFIG_LPC32XX_NAND_MLC_WR_LOW, 0x0F, 0),
+ clkdiv(CFG_LPC32XX_NAND_MLC_TCEA_DELAY, 0x03, 24) |
+ clkdiv(CFG_LPC32XX_NAND_MLC_BUSY_DELAY, 0x1F, 19) |
+ clkdiv(CFG_LPC32XX_NAND_MLC_NAND_TA, 0x07, 16) |
+ clkdiv(CFG_LPC32XX_NAND_MLC_RD_HIGH, 0x0F, 12) |
+ clkdiv(CFG_LPC32XX_NAND_MLC_RD_LOW, 0x0F, 8) |
+ clkdiv(CFG_LPC32XX_NAND_MLC_WR_HIGH, 0x0F, 4) |
+ clkdiv(CFG_LPC32XX_NAND_MLC_WR_LOW, 0x0F, 0),
&lpc32xx_nand_mlc_registers->time_reg);
}
diff --git a/drivers/mtd/nand/raw/lpc32xx_nand_slc.c b/drivers/mtd/nand/raw/lpc32xx_nand_slc.c
index f4f1b22f5e2..356f8d9440b 100644
--- a/drivers/mtd/nand/raw/lpc32xx_nand_slc.c
+++ b/drivers/mtd/nand/raw/lpc32xx_nand_slc.c
@@ -126,14 +126,14 @@ static void lpc32xx_nand_init(void)
&lpc32xx_nand_slc_regs->icr);
/* Configure NAND flash timings */
- writel(TAC_W_RDY(CONFIG_LPC32XX_NAND_SLC_WDR_CLKS) |
- TAC_W_WIDTH(hclk / CONFIG_LPC32XX_NAND_SLC_WWIDTH) |
- TAC_W_HOLD(hclk / CONFIG_LPC32XX_NAND_SLC_WHOLD) |
- TAC_W_SETUP(hclk / CONFIG_LPC32XX_NAND_SLC_WSETUP) |
- TAC_R_RDY(CONFIG_LPC32XX_NAND_SLC_RDR_CLKS) |
- TAC_R_WIDTH(hclk / CONFIG_LPC32XX_NAND_SLC_RWIDTH) |
- TAC_R_HOLD(hclk / CONFIG_LPC32XX_NAND_SLC_RHOLD) |
- TAC_R_SETUP(hclk / CONFIG_LPC32XX_NAND_SLC_RSETUP),
+ writel(TAC_W_RDY(CFG_LPC32XX_NAND_SLC_WDR_CLKS) |
+ TAC_W_WIDTH(hclk / CFG_LPC32XX_NAND_SLC_WWIDTH) |
+ TAC_W_HOLD(hclk / CFG_LPC32XX_NAND_SLC_WHOLD) |
+ TAC_W_SETUP(hclk / CFG_LPC32XX_NAND_SLC_WSETUP) |
+ TAC_R_RDY(CFG_LPC32XX_NAND_SLC_RDR_CLKS) |
+ TAC_R_WIDTH(hclk / CFG_LPC32XX_NAND_SLC_RWIDTH) |
+ TAC_R_HOLD(hclk / CFG_LPC32XX_NAND_SLC_RHOLD) |
+ TAC_R_SETUP(hclk / CFG_LPC32XX_NAND_SLC_RSETUP),
&lpc32xx_nand_slc_regs->tac);
}
diff --git a/drivers/mtd/nand/raw/mxc_nand.c b/drivers/mtd/nand/raw/mxc_nand.c
index 8aa5f734213..051ded6a240 100644
--- a/drivers/mtd/nand/raw/mxc_nand.c
+++ b/drivers/mtd/nand/raw/mxc_nand.c
@@ -1172,10 +1172,10 @@ int board_nand_init(struct nand_chip *this)
this->write_buf = mxc_nand_write_buf;
this->read_buf = mxc_nand_read_buf;
- host->regs = (struct mxc_nand_regs __iomem *)CONFIG_MXC_NAND_REGS_BASE;
+ host->regs = (struct mxc_nand_regs __iomem *)CFG_MXC_NAND_REGS_BASE;
#ifdef MXC_NFC_V3_2
host->ip_regs =
- (struct mxc_nand_ip_regs __iomem *)CONFIG_MXC_NAND_IP_REGS_BASE;
+ (struct mxc_nand_ip_regs __iomem *)CFG_MXC_NAND_IP_REGS_BASE;
#endif
host->clk_act = 1;
diff --git a/drivers/mtd/nand/raw/mxs_nand_spl.c b/drivers/mtd/nand/raw/mxs_nand_spl.c
index ef03b7789dd..300662994cf 100644
--- a/drivers/mtd/nand/raw/mxs_nand_spl.c
+++ b/drivers/mtd/nand/raw/mxs_nand_spl.c
@@ -257,7 +257,7 @@ int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
while (block <= lastblock && size > 0) {
if (!is_badblock(mtd, mtd->erasesize * block, 1)) {
/* Skip bad blocks */
- while (page < nand_page_per_block) {
+ while (page < nand_page_per_block && size) {
int curr_page = nand_page_per_block * block + page;
if (mxs_read_page_ecc(mtd, page_buf, curr_page) < 0) {
diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c
index 215b9ba84fd..bc61ad03eb0 100644
--- a/drivers/mtd/nand/raw/nand_base.c
+++ b/drivers/mtd/nand/raw/nand_base.c
@@ -4171,10 +4171,13 @@ static void nand_manufacturer_detect(struct nand_chip *chip)
* nand_decode_ext_id() otherwise.
*/
if (chip->manufacturer.desc && chip->manufacturer.desc->ops &&
- chip->manufacturer.desc->ops->detect)
+ chip->manufacturer.desc->ops->detect) {
+ /* The 3rd id byte holds MLC / multichip data */
+ chip->bits_per_cell = nand_get_bits_per_cell(chip->id.data[2]);
chip->manufacturer.desc->ops->detect(chip);
- else
+ } else {
nand_decode_ext_id(chip);
+ }
}
/*
diff --git a/drivers/mtd/nand/raw/nand_spl_loaders.c b/drivers/mtd/nand/raw/nand_spl_loaders.c
index 4befc75c047..156b44d8358 100644
--- a/drivers/mtd/nand/raw/nand_spl_loaders.c
+++ b/drivers/mtd/nand/raw/nand_spl_loaders.c
@@ -23,7 +23,7 @@ int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
if (unlikely(page_offset)) {
memmove(dst, dst + page_offset,
CONFIG_SYS_NAND_PAGE_SIZE);
- dst = (void *)((int)dst - page_offset);
+ dst = (void *)(dst - page_offset);
page_offset = 0;
}
dst += CONFIG_SYS_NAND_PAGE_SIZE;
diff --git a/drivers/mtd/nand/raw/octeontx_bch.c b/drivers/mtd/nand/raw/octeontx_bch.c
index c1d721cabfc..fc16b77416b 100644
--- a/drivers/mtd/nand/raw/octeontx_bch.c
+++ b/drivers/mtd/nand/raw/octeontx_bch.c
@@ -27,11 +27,6 @@
#include <asm/arch/clock.h>
#include "octeontx_bch.h"
-#ifdef DEBUG
-# undef CONFIG_LOGLEVEL
-# define CONFIG_LOGLEVEL 8
-#endif
-
LIST_HEAD(octeontx_bch_devices);
static unsigned int num_vfs = BCH_NR_VF;
static void *bch_pf;
diff --git a/drivers/mtd/nand/raw/octeontx_nand.c b/drivers/mtd/nand/raw/octeontx_nand.c
index b338b204f34..1ffadad9cae 100644
--- a/drivers/mtd/nand/raw/octeontx_nand.c
+++ b/drivers/mtd/nand/raw/octeontx_nand.c
@@ -31,11 +31,6 @@
#include <asm/arch/clock.h>
#include "octeontx_bch.h"
-#ifdef DEBUG
-# undef CONFIG_LOGLEVEL
-# define CONFIG_LOGLEVEL 8
-#endif
-
/*
* The NDF_CMD queue takes commands between 16 - 128 bit.
* All commands must be 16 bit aligned and are little endian.
diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c
index b7d261d8ce1..be3cb3c601b 100644
--- a/drivers/mtd/nand/raw/omap_gpmc.c
+++ b/drivers/mtd/nand/raw/omap_gpmc.c
@@ -8,7 +8,11 @@
#include <log.h>
#include <asm/io.h>
#include <linux/errno.h>
+
+#ifdef CONFIG_ARCH_OMAP2PLUS
#include <asm/arch/mem.h>
+#endif
+
#include <linux/mtd/omap_gpmc.h>
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/rawnand.h>
@@ -17,6 +21,10 @@
#include <nand.h>
#include <linux/mtd/omap_elm.h>
+#ifndef GPMC_MAX_CS
+#define GPMC_MAX_CS 4
+#endif
+
#define BADBLOCK_MARKER_LENGTH 2
#define SECTOR_BYTES 512
#define ECCCLEAR (0x1 << 8)
@@ -29,7 +37,6 @@ static u8 bch8_polynomial[] = {0xef, 0x51, 0x2e, 0x09, 0xed, 0x93, 0x9a, 0xc2,
0x97, 0x79, 0xe5, 0x24, 0xb5};
#endif
static uint8_t cs_next;
-static __maybe_unused struct nand_ecclayout omap_ecclayout;
#if defined(CONFIG_NAND_OMAP_GPMC_WSCFG)
static const int8_t wscfg[CONFIG_SYS_MAX_NAND_DEVICE] =
@@ -47,6 +54,7 @@ struct omap_nand_info {
enum omap_ecc ecc_scheme;
uint8_t cs;
uint8_t ws; /* wait status pin (0,1) */
+ void __iomem *fifo;
};
/* We are wasting a bit of memory but al least we are safe */
@@ -342,6 +350,20 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
return 0;
}
+static inline void omap_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
+{
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct omap_nand_info *info = nand_get_controller_data(chip);
+ u32 alignment = ((uintptr_t)buf | len) & 3;
+
+ if (alignment & 1)
+ readsb(info->fifo, buf, len);
+ else if (alignment & 3)
+ readsw(info->fifo, buf, len >> 1);
+ else
+ readsl(info->fifo, buf, len >> 2);
+}
+
#ifdef CONFIG_NAND_OMAP_GPMC_PREFETCH
#define PREFETCH_CONFIG1_CS_SHIFT 24
@@ -407,7 +429,7 @@ static int __read_prefetch_aligned(struct nand_chip *chip, uint32_t *buf, int le
cnt = PREFETCH_STATUS_FIFO_CNT(cnt);
for (i = 0; i < cnt / 4; i++) {
- *buf++ = readl(CFG_SYS_NAND_BASE);
+ *buf++ = readl(info->fifo);
len -= 4;
}
} while (len);
@@ -417,29 +439,19 @@ static int __read_prefetch_aligned(struct nand_chip *chip, uint32_t *buf, int le
return 0;
}
-static inline void omap_nand_read(struct mtd_info *mtd, uint8_t *buf, int len)
-{
- struct nand_chip *chip = mtd_to_nand(mtd);
-
- if (chip->options & NAND_BUSWIDTH_16)
- nand_read_buf16(mtd, buf, len);
- else
- nand_read_buf(mtd, buf, len);
-}
-
static void omap_nand_read_prefetch(struct mtd_info *mtd, uint8_t *buf, int len)
{
int ret;
- uint32_t head, tail;
+ uintptr_t head, tail;
struct nand_chip *chip = mtd_to_nand(mtd);
/*
* If the destination buffer is unaligned, start with reading
* the overlap byte-wise.
*/
- head = ((uint32_t) buf) % 4;
+ head = ((uintptr_t)buf) % 4;
if (head) {
- omap_nand_read(mtd, buf, head);
+ omap_nand_read_buf(mtd, buf, head);
buf += head;
len -= head;
}
@@ -453,10 +465,10 @@ static void omap_nand_read_prefetch(struct mtd_info *mtd, uint8_t *buf, int len)
ret = __read_prefetch_aligned(chip, (uint32_t *)buf, len - tail);
if (ret < 0) {
/* fallback in case the prefetch engine is busy */
- omap_nand_read(mtd, buf, len);
+ omap_nand_read_buf(mtd, buf, len);
} else if (tail) {
buf += len - tail;
- omap_nand_read(mtd, buf, tail);
+ omap_nand_read_buf(mtd, buf, tail);
}
}
#endif /* CONFIG_NAND_OMAP_GPMC_PREFETCH */
@@ -740,7 +752,7 @@ static void __maybe_unused omap_free_bch(struct mtd_info *mtd)
static int omap_select_ecc_scheme(struct nand_chip *nand,
enum omap_ecc ecc_scheme, unsigned int pagesize, unsigned int oobsize) {
struct omap_nand_info *info = nand_get_controller_data(nand);
- struct nand_ecclayout *ecclayout = &omap_ecclayout;
+ struct nand_ecclayout *ecclayout = nand->ecc.layout;
int eccsteps = pagesize / SECTOR_BYTES;
int i;
@@ -993,6 +1005,8 @@ int board_nand_init(struct nand_chip *nand)
int32_t gpmc_config = 0;
int cs = cs_next++;
int err = 0;
+ struct omap_nand_info *info;
+
/*
* xloader/Uboot's gpmc configuration would have configured GPMC for
* nand type of memory. The following logic scans and latches on to the
@@ -1021,14 +1035,19 @@ int board_nand_init(struct nand_chip *nand)
nand->IO_ADDR_R = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat;
nand->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
- omap_nand_info[cs].control = NULL;
- omap_nand_info[cs].cs = cs;
- omap_nand_info[cs].ws = wscfg[cs];
+
+ info = &omap_nand_info[cs];
+ info->control = NULL;
+ info->cs = cs;
+ info->ws = wscfg[cs];
+ info->fifo = (void __iomem *)CFG_SYS_NAND_BASE;
nand_set_controller_data(nand, &omap_nand_info[cs]);
nand->cmd_ctrl = omap_nand_hwcontrol;
nand->options |= NAND_NO_PADDING | NAND_CACHEPRG;
nand->chip_delay = 100;
- nand->ecc.layout = &omap_ecclayout;
+ nand->ecc.layout = kzalloc(sizeof(*nand->ecc.layout), GFP_KERNEL);
+ if (!nand->ecc.layout)
+ return -ENOMEM;
/* configure driver and controller based on NAND device bus-width */
gpmc_config = readl(&gpmc_cfg->cs[cs].config1);
@@ -1054,10 +1073,7 @@ int board_nand_init(struct nand_chip *nand)
#ifdef CONFIG_NAND_OMAP_GPMC_PREFETCH
nand->read_buf = omap_nand_read_prefetch;
#else
- if (nand->options & NAND_BUSWIDTH_16)
- nand->read_buf = nand_read_buf16;
- else
- nand->read_buf = nand_read_buf;
+ nand->read_buf = omap_nand_read_buf;
#endif
nand->dev_ready = omap_dev_ready;
diff --git a/drivers/mtd/ubi/Kconfig b/drivers/mtd/ubi/Kconfig
index 67a3cf1d7a5..5783d36c048 100644
--- a/drivers/mtd/ubi/Kconfig
+++ b/drivers/mtd/ubi/Kconfig
@@ -20,6 +20,18 @@ config MTD_UBI
if MTD_UBI
+config MTD_UBI_BLOCK
+ def_bool n
+
+config MTD_UBI_MODULE
+ def_bool y
+ help
+ ubi_init() disables returning error codes when built into the Linux
+ kernel so that it doesn't hang the Linux kernel boot process. Since
+ the U-Boot driver code depends on getting valid error codes from this
+ function we just tell the UBI layer that we are building as a module
+ (which only enables the additional error reporting).
+
config MTD_UBI_WL_THRESHOLD
int "UBI wear-leveling threshold"
default 4096
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 13e434e5913..7873538cc2d 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -1,7 +1,6 @@
source "drivers/net/phy/Kconfig"
source "drivers/net/pfe_eth/Kconfig"
source "drivers/net/fsl-mc/Kconfig"
-source "drivers/net/bnxt/Kconfig"
config ETH
def_bool y
@@ -16,6 +15,10 @@ config DM_ETH
This is currently implemented in net/eth-uclass.c
Look in include/net.h for details.
+config SPL_DM_ETH
+ depends on SPL_NET
+ def_bool y
+
config DM_MDIO
bool "Enable Driver Model for MDIO devices"
depends on PHYLIB
@@ -175,6 +178,8 @@ config BCMGENET
help
This driver supports the BCMGENET Ethernet MAC.
+source "drivers/net/bnxt/Kconfig"
+
config CORTINA_NI_ENET
bool "Cortina-Access Ethernet driver"
depends on CORTINA_PLATFORM
@@ -193,6 +198,18 @@ config DRIVER_DM9000
help
The Davicom DM9000 parallel bus external ethernet interface chip.
+config DM9000_BYTE_SWAPPED
+ bool "Byte swapped access for DM9000"
+ depends on DRIVER_DM9000
+
+config DM9000_NO_SROM
+ bool "No SROM on DM9000"
+ depends on DRIVER_DM9000
+
+config DM9000_USE_16BIT
+ bool "Use 16bit access in DM9000"
+ depends on DRIVER_DM9000
+
config DWC_ETH_QOS
bool "Synopsys DWC Ethernet QOS device support"
select PHYLIB
@@ -355,6 +372,7 @@ config FMAN_ENET
select SYS_FMAN_V3 if ARCH_B4420 || ARCH_B4860 || ARCH_LS1043A || \
ARCH_LS1046A || ARCH_T1024 || ARCH_T1040 || ARCH_T1042 || \
ARCH_T2080 || ARCH_T4240
+ select FSL_FM_10GEC_REGULAR_NOTATION if ARCH_T1024
help
This driver support the Freescale FMan Ethernet controller
@@ -374,6 +392,18 @@ config SYS_FMAN_V3
help
SoC has FMan v3 with mEMAC
+config FSL_FM_10GEC_REGULAR_NOTATION
+ bool
+ help
+ On SoCs T4240, T2080, LS1043A, etc, the notation between 10GEC and
+ MAC as below:
+ 10GEC1->MAC9, 10GEC2->MAC10, 10GEC3->MAC1, 10GEC4->MAC2
+ While on SoCs T1024, etc, the notation between 10GEC and MAC as below:
+ 10GEC1->MAC1, 10GEC2->MAC2
+ so we introduce CONFIG_FSL_FM_10GEC_REGULAR_NOTATION to identify the
+ new SoCs on which 10GEC enumeration is consistent with MAC
+ enumeration.
+
config FTMAC100
bool "Ftmac100 Ethernet Support"
help
@@ -679,9 +709,6 @@ config XILINX_AXIMRMAC
config VSC7385_ENET
bool "Vitesse 7385 Switch Firmware Upload driver"
-config VSC9953
- bool "Vitesse VSC9953 L2 Switch driver"
-
config XILINX_EMACLITE
select PHYLIB
select MII
@@ -721,7 +748,6 @@ config RENESAS_RAVB
config MPC8XX_FEC
bool "Fast Ethernet Controller on MPC8XX"
depends on MPC8xx
- depends on DM_ETH
select MII
select SYS_DISCOVER_PHY
help
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index d3fc6b7d3ee..5b4e60eea3e 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -87,7 +87,6 @@ obj-$(CONFIG_SUN8I_EMAC) += sun8i_emac.o
obj-$(CONFIG_TSEC_ENET) += tsec.o fsl_mdio.o
obj-$(CONFIG_TULIP) += dc2114x.o
obj-$(CONFIG_VSC7385_ENET) += vsc7385.o
-obj-$(CONFIG_VSC9953) += vsc9953.o
obj-$(CONFIG_XILINX_AXIEMAC) += xilinx_axi_emac.o
obj-$(CONFIG_XILINX_AXIMRMAC) += xilinx_axi_mrmac.o
obj-$(CONFIG_XILINX_EMACLITE) += xilinx_emaclite.o
diff --git a/drivers/net/bnxt/Kconfig b/drivers/net/bnxt/Kconfig
index 412ecd43033..6ff3ffa137b 100644
--- a/drivers/net/bnxt/Kconfig
+++ b/drivers/net/bnxt/Kconfig
@@ -1,6 +1,5 @@
config BNXT_ETH
bool "BNXT PCI support"
- depends on DM_ETH
select PCI_INIT_R
help
This driver implements support for bnxt pci controller
diff --git a/drivers/net/dc2114x.c b/drivers/net/dc2114x.c
index deedfe76e43..4e7af95b41c 100644
--- a/drivers/net/dc2114x.c
+++ b/drivers/net/dc2114x.c
@@ -73,13 +73,7 @@
#define POLL_DEMAND 1
-#if defined(CONFIG_DM_ETH)
#define phys_to_bus(dev, a) dm_pci_phys_to_mem((dev), (a))
-#elif defined(CONFIG_E500)
-#define phys_to_bus(dev, a) (a)
-#else
-#define phys_to_bus(dev, a) pci_phys_to_mem((dev), (a))
-#endif
#define NUM_RX_DESC PKTBUFSRX
#define NUM_TX_DESC 1 /* Number of TX descriptors */
@@ -103,12 +97,7 @@ struct dc2114x_priv {
int tx_new; /* TX descriptor ring pointer */
char rx_ring_size;
char tx_ring_size;
-#ifdef CONFIG_DM_ETH
struct udevice *devno;
-#else
- struct eth_device dev;
- pci_dev_t devno;
-#endif
char *name;
void __iomem *iobase;
u8 *enetaddr;
@@ -479,150 +468,6 @@ static struct pci_device_id supported[] = {
{ }
};
-#ifndef CONFIG_DM_ETH
-static int dc21x4x_init(struct eth_device *dev, struct bd_info *bis)
-{
- struct dc2114x_priv *priv =
- container_of(dev, struct dc2114x_priv, dev);
-
- /* Ensure we're not sleeping. */
- pci_write_config_byte(priv->devno, PCI_CFDA_PSM, WAKEUP);
-
- return dc21x4x_init_common(priv);
-}
-
-static void dc21x4x_halt(struct eth_device *dev)
-{
- struct dc2114x_priv *priv =
- container_of(dev, struct dc2114x_priv, dev);
-
- dc21x4x_halt_common(priv);
-
- pci_write_config_byte(priv->devno, PCI_CFDA_PSM, SLEEP);
-}
-
-static int dc21x4x_send(struct eth_device *dev, void *packet, int length)
-{
- struct dc2114x_priv *priv =
- container_of(dev, struct dc2114x_priv, dev);
-
- return dc21x4x_send_common(priv, packet, length);
-}
-
-static int dc21x4x_recv(struct eth_device *dev)
-{
- struct dc2114x_priv *priv =
- container_of(dev, struct dc2114x_priv, dev);
- int length = 0;
- int ret;
-
- while (true) {
- ret = dc21x4x_recv_check(priv);
- if (!ret)
- break;
-
- if (ret > 0) {
- length = ret;
- /* Pass the packet up to the protocol layers */
- net_process_received_packet
- (net_rx_packets[priv->rx_new], length - 4);
- }
-
- /*
- * Change buffer ownership for this frame,
- * back to the adapter.
- */
- if (ret != -EAGAIN)
- priv->rx_ring[priv->rx_new].status = cpu_to_le32(R_OWN);
-
- /* Update entry information. */
- priv->rx_new = (priv->rx_new + 1) % priv->rx_ring_size;
- }
-
- return length;
-}
-
-int dc21x4x_initialize(struct bd_info *bis)
-{
- struct dc2114x_priv *priv;
- struct eth_device *dev;
- unsigned short status;
- unsigned char timer;
- unsigned int iobase;
- int card_number = 0;
- pci_dev_t devbusfn;
- int idx = 0;
-
- while (1) {
- devbusfn = pci_find_devices(supported, idx++);
- if (devbusfn == -1)
- break;
-
- pci_read_config_word(devbusfn, PCI_COMMAND, &status);
- status |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
- pci_write_config_word(devbusfn, PCI_COMMAND, status);
-
- pci_read_config_word(devbusfn, PCI_COMMAND, &status);
- if (!(status & PCI_COMMAND_MEMORY)) {
- printf("Error: Can not enable MEMORY access.\n");
- continue;
- }
-
- if (!(status & PCI_COMMAND_MASTER)) {
- printf("Error: Can not enable Bus Mastering.\n");
- continue;
- }
-
- /* Check the latency timer for values >= 0x60. */
- pci_read_config_byte(devbusfn, PCI_LATENCY_TIMER, &timer);
-
- if (timer < 0x60) {
- pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER,
- 0x60);
- }
-
- /* read BAR for memory space access */
- pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, &iobase);
- iobase &= PCI_BASE_ADDRESS_MEM_MASK;
- debug("dc21x4x: DEC 21142 PCI Device @0x%x\n", iobase);
-
- priv = memalign(32, sizeof(*priv));
- if (!priv) {
- printf("Can not allocalte memory of dc21x4x\n");
- break;
- }
- memset(priv, 0, sizeof(*priv));
-
- dev = &priv->dev;
-
- sprintf(dev->name, "dc21x4x#%d", card_number);
- priv->devno = devbusfn;
- priv->name = dev->name;
- priv->enetaddr = dev->enetaddr;
-
- dev->iobase = pci_mem_to_phys(devbusfn, iobase);
- dev->priv = (void *)devbusfn;
- dev->init = dc21x4x_init;
- dev->halt = dc21x4x_halt;
- dev->send = dc21x4x_send;
- dev->recv = dc21x4x_recv;
-
- /* Ensure we're not sleeping. */
- pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP);
-
- udelay(10 * 1000);
-
- read_hw_addr(priv);
-
- eth_register(dev);
-
- card_number++;
- }
-
- return card_number;
-}
-
-#else /* DM_ETH */
static int dc2114x_start(struct udevice *dev)
{
struct eth_pdata *plat = dev_get_plat(dev);
@@ -756,4 +601,3 @@ U_BOOT_DRIVER(eth_dc2114x) = {
};
U_BOOT_PCI_DEVICE(eth_dc2114x, supported);
-#endif
diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index 0e63f70934c..ddaf7ed1d38 100644
--- a/drivers/net/designware.c
+++ b/drivers/net/designware.c
@@ -34,12 +34,8 @@
static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
{
-#ifdef CONFIG_DM_ETH
struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv);
struct eth_mac_regs *mac_p = priv->mac_regs_p;
-#else
- struct eth_mac_regs *mac_p = bus->priv;
-#endif
ulong start;
u16 miiaddr;
int timeout = CONFIG_MDIO_TIMEOUT;
@@ -62,12 +58,8 @@ static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
u16 val)
{
-#ifdef CONFIG_DM_ETH
struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv);
struct eth_mac_regs *mac_p = priv->mac_regs_p;
-#else
- struct eth_mac_regs *mac_p = bus->priv;
-#endif
ulong start;
u16 miiaddr;
int ret = -ETIMEDOUT, timeout = CONFIG_MDIO_TIMEOUT;
@@ -90,7 +82,7 @@ static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
return ret;
}
-#if defined(CONFIG_DM_ETH) && CONFIG_IS_ENABLED(DM_GPIO)
+#if CONFIG_IS_ENABLED(DM_GPIO)
static int __dw_mdio_reset(struct udevice *dev)
{
struct dw_eth_dev *priv = dev_get_priv(dev);
@@ -192,7 +184,7 @@ static int dw_mdio_init(const char *name, void *priv)
bus->read = dw_mdio_read;
bus->write = dw_mdio_write;
snprintf(bus->name, sizeof(bus->name), "%s", name);
-#if defined(CONFIG_DM_ETH) && CONFIG_IS_ENABLED(DM_GPIO)
+#if CONFIG_IS_ENABLED(DM_GPIO)
bus->reset = dw_mdio_reset;
#endif
@@ -575,7 +567,7 @@ static int dw_phy_init(struct dw_eth_dev *priv, void *dev)
struct phy_device *phydev;
int ret;
-#if IS_ENABLED(CONFIG_DM_MDIO) && IS_ENABLED(CONFIG_DM_ETH)
+#if IS_ENABLED(CONFIG_DM_MDIO)
phydev = dm_eth_phy_connect(dev);
if (!phydev)
return -ENODEV;
@@ -605,103 +597,6 @@ static int dw_phy_init(struct dw_eth_dev *priv, void *dev)
return 0;
}
-#ifndef CONFIG_DM_ETH
-static int dw_eth_init(struct eth_device *dev, struct bd_info *bis)
-{
- int ret;
-
- ret = designware_eth_init(dev->priv, dev->enetaddr);
- if (!ret)
- ret = designware_eth_enable(dev->priv);
-
- return ret;
-}
-
-static int dw_eth_send(struct eth_device *dev, void *packet, int length)
-{
- return _dw_eth_send(dev->priv, packet, length);
-}
-
-static int dw_eth_recv(struct eth_device *dev)
-{
- uchar *packet;
- int length;
-
- length = _dw_eth_recv(dev->priv, &packet);
- if (length == -EAGAIN)
- return 0;
- net_process_received_packet(packet, length);
-
- _dw_free_pkt(dev->priv);
-
- return 0;
-}
-
-static void dw_eth_halt(struct eth_device *dev)
-{
- return _dw_eth_halt(dev->priv);
-}
-
-static int dw_write_hwaddr(struct eth_device *dev)
-{
- return _dw_write_hwaddr(dev->priv, dev->enetaddr);
-}
-
-int designware_initialize(ulong base_addr, u32 interface)
-{
- struct eth_device *dev;
- struct dw_eth_dev *priv;
-
- dev = (struct eth_device *) malloc(sizeof(struct eth_device));
- if (!dev)
- return -ENOMEM;
-
- /*
- * Since the priv structure contains the descriptors which need a strict
- * buswidth alignment, memalign is used to allocate memory
- */
- priv = (struct dw_eth_dev *) memalign(ARCH_DMA_MINALIGN,
- sizeof(struct dw_eth_dev));
- if (!priv) {
- free(dev);
- return -ENOMEM;
- }
-
- if ((phys_addr_t)priv + sizeof(*priv) > (1ULL << 32)) {
- printf("designware: buffers are outside DMA memory\n");
- return -EINVAL;
- }
-
- memset(dev, 0, sizeof(struct eth_device));
- memset(priv, 0, sizeof(struct dw_eth_dev));
-
- sprintf(dev->name, "dwmac.%lx", base_addr);
- dev->iobase = (int)base_addr;
- dev->priv = priv;
-
- priv->dev = dev;
- priv->mac_regs_p = (struct eth_mac_regs *)base_addr;
- priv->dma_regs_p = (struct eth_dma_regs *)(base_addr +
- DW_DMA_BASE_OFFSET);
-
- dev->init = dw_eth_init;
- dev->send = dw_eth_send;
- dev->recv = dw_eth_recv;
- dev->halt = dw_eth_halt;
- dev->write_hwaddr = dw_write_hwaddr;
-
- eth_register(dev);
-
- priv->interface = interface;
-
- dw_mdio_init(dev->name, priv->mac_regs_p);
- priv->bus = miiphy_get_dev_by_name(dev->name);
-
- return dw_phy_init(priv, dev);
-}
-#endif
-
-#ifdef CONFIG_DM_ETH
static int designware_eth_start(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_plat(dev);
@@ -971,4 +866,3 @@ static struct pci_device_id supported[] = {
};
U_BOOT_PCI_DEVICE(eth_designware, supported);
-#endif
diff --git a/drivers/net/designware.h b/drivers/net/designware.h
index 3793d550980..138c3c14bf5 100644
--- a/drivers/net/designware.h
+++ b/drivers/net/designware.h
@@ -233,9 +233,6 @@ struct dw_eth_dev {
struct eth_mac_regs *mac_regs_p;
struct eth_dma_regs *dma_regs_p;
-#ifndef CONFIG_DM_ETH
- struct eth_device *dev;
-#endif
#if CONFIG_IS_ENABLED(DM_GPIO)
struct gpio_desc reset_gpio;
#endif
@@ -248,7 +245,6 @@ struct dw_eth_dev {
struct mii_dev *bus;
};
-#ifdef CONFIG_DM_ETH
int designware_eth_of_to_plat(struct udevice *dev);
int designware_eth_probe(struct udevice *dev);
extern const struct eth_ops designware_eth_ops;
@@ -266,6 +262,5 @@ int designware_eth_free_pkt(struct udevice *dev, uchar *packet,
int length);
void designware_eth_stop(struct udevice *dev);
int designware_eth_write_hwaddr(struct udevice *dev);
-#endif
#endif
diff --git a/drivers/net/dm9000x.c b/drivers/net/dm9000x.c
index 07733df533e..b46bdeb23be 100644
--- a/drivers/net/dm9000x.c
+++ b/drivers/net/dm9000x.c
@@ -75,9 +75,6 @@ struct dm9000_priv {
void (*outblk)(struct dm9000_priv *db, void *data_ptr, int count);
void (*inblk)(struct dm9000_priv *db, void *data_ptr, int count);
void (*rx_status)(struct dm9000_priv *db, u16 *rxstatus, u16 *rxlen);
-#ifndef CONFIG_DM_ETH
- struct eth_device dev;
-#endif
void __iomem *base_io;
void __iomem *base_data;
};
@@ -572,68 +569,6 @@ static void dm9000_get_enetaddr(struct dm9000_priv *db, u8 *enetaddr)
static void dm9000_get_enetaddr(struct dm9000_priv *db, u8 *enetaddr) {}
#endif
-#ifndef CONFIG_DM_ETH
-static int dm9000_init(struct eth_device *dev, struct bd_info *bd)
-{
- struct dm9000_priv *db = container_of(dev, struct dm9000_priv, dev);
-
- return dm9000_init_common(db, dev->enetaddr);
-}
-
-static void dm9000_halt(struct eth_device *dev)
-{
- struct dm9000_priv *db = container_of(dev, struct dm9000_priv, dev);
-
- dm9000_halt_common(db);
-}
-
-static int dm9000_send(struct eth_device *dev, void *packet, int length)
-{
- struct dm9000_priv *db = container_of(dev, struct dm9000_priv, dev);
-
- return dm9000_send_common(db, packet, length);
-}
-
-static int dm9000_recv(struct eth_device *dev)
-{
- struct dm9000_priv *db = container_of(dev, struct dm9000_priv, dev);
- int ret;
-
- ret = dm9000_recv_common(db, net_rx_packets[0]);
- if (ret > 0)
- net_process_received_packet(net_rx_packets[0], ret);
-
- return ret;
-}
-
-int dm9000_initialize(struct bd_info *bis)
-{
- struct dm9000_priv *priv;
- struct eth_device *dev;
-
- priv = calloc(1, sizeof(*priv));
- if (!priv)
- return -ENOMEM;
-
- dev = &priv->dev;
-
- priv->base_io = (void __iomem *)DM9000_IO;
- priv->base_data = (void __iomem *)DM9000_DATA;
-
- /* Load MAC address from EEPROM */
- dm9000_get_enetaddr(priv, dev->enetaddr);
-
- dev->init = dm9000_init;
- dev->halt = dm9000_halt;
- dev->send = dm9000_send;
- dev->recv = dm9000_recv;
- strcpy(dev->name, "dm9000");
-
- eth_register(&priv->dev);
-
- return 0;
-}
-#else /* ifdef CONFIG_DM_ETH */
static int dm9000_start(struct udevice *dev)
{
struct dm9000_priv *db = dev_get_priv(dev);
@@ -746,4 +681,3 @@ U_BOOT_DRIVER(dm9000) = {
.plat_auto = sizeof(struct eth_pdata),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
-#endif
diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c
index 5fe016ebaf7..41e6ba760e2 100644
--- a/drivers/net/e1000.c
+++ b/drivers/net/e1000.c
@@ -65,9 +65,7 @@ DEFINE_ALIGN_BUFFER(unsigned char, packet, 4096, E1000_BUFFER_ALIGN);
static int tx_tail;
static int rx_tail, rx_last;
-#ifdef CONFIG_DM_ETH
static int num_cards; /* Number of E1000 devices seen so far */
-#endif
static struct pci_device_id e1000_supported[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82542) },
@@ -1611,13 +1609,8 @@ e1000_reset_hw(struct e1000_hw *hw)
/* For 82542 (rev 2.0), disable MWI before issuing a device reset */
if (hw->mac_type == e1000_82542_rev2_0) {
DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
-#ifdef CONFIG_DM_ETH
dm_pci_write_config16(hw->pdev, PCI_COMMAND,
hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
-#else
- pci_write_config_word(hw->pdev, PCI_COMMAND,
- hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
-#endif
}
/* Clear interrupt mask to stop board from generating interrupts */
@@ -1695,11 +1688,7 @@ e1000_reset_hw(struct e1000_hw *hw)
/* If MWI was previously enabled, reenable it. */
if (hw->mac_type == e1000_82542_rev2_0) {
-#ifdef CONFIG_DM_ETH
dm_pci_write_config16(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
-#else
- pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
-#endif
}
if (hw->mac_type != e1000_igb)
E1000_WRITE_REG(hw, PBA, pba);
@@ -1884,15 +1873,9 @@ e1000_init_hw(struct e1000_hw *hw, unsigned char enetaddr[6])
/* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
if (hw->mac_type == e1000_82542_rev2_0) {
DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
-#ifdef CONFIG_DM_ETH
dm_pci_write_config16(hw->pdev, PCI_COMMAND,
hw->
pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
-#else
- pci_write_config_word(hw->pdev, PCI_COMMAND,
- hw->
- pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
-#endif
E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
E1000_WRITE_FLUSH(hw);
mdelay(5);
@@ -1908,11 +1891,7 @@ e1000_init_hw(struct e1000_hw *hw, unsigned char enetaddr[6])
E1000_WRITE_REG(hw, RCTL, 0);
E1000_WRITE_FLUSH(hw);
mdelay(1);
-#ifdef CONFIG_DM_ETH
dm_pci_write_config16(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
-#else
- pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
-#endif
}
/* Zero out the Multicast HASH table */
@@ -1935,17 +1914,10 @@ e1000_init_hw(struct e1000_hw *hw, unsigned char enetaddr[6])
default:
/* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
if (hw->bus_type == e1000_bus_type_pcix) {
-#ifdef CONFIG_DM_ETH
dm_pci_read_config16(hw->pdev, PCIX_COMMAND_REGISTER,
&pcix_cmd_word);
dm_pci_read_config16(hw->pdev, PCIX_STATUS_REGISTER_HI,
&pcix_stat_hi_word);
-#else
- pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
- &pcix_cmd_word);
- pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI,
- &pcix_stat_hi_word);
-#endif
cmd_mmrbc =
(pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
PCIX_COMMAND_MMRBC_SHIFT;
@@ -1957,13 +1929,8 @@ e1000_init_hw(struct e1000_hw *hw, unsigned char enetaddr[6])
if (cmd_mmrbc > stat_mmrbc) {
pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
-#ifdef CONFIG_DM_ETH
dm_pci_write_config16(hw->pdev, PCIX_COMMAND_REGISTER,
pcix_cmd_word);
-#else
- pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
- pcix_cmd_word);
-#endif
}
}
break;
@@ -5060,7 +5027,6 @@ e1000_sw_init(struct e1000_hw *hw)
int result;
/* PCI config space info */
-#ifdef CONFIG_DM_ETH
dm_pci_read_config16(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id);
dm_pci_read_config16(hw->pdev, PCI_DEVICE_ID, &hw->device_id);
dm_pci_read_config16(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID,
@@ -5069,16 +5035,6 @@ e1000_sw_init(struct e1000_hw *hw)
dm_pci_read_config8(hw->pdev, PCI_REVISION_ID, &hw->revision_id);
dm_pci_read_config16(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word);
-#else
- pci_read_config_word(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id);
- pci_read_config_word(hw->pdev, PCI_DEVICE_ID, &hw->device_id);
- pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID,
- &hw->subsystem_vendor_id);
- pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id);
-
- pci_read_config_byte(hw->pdev, PCI_REVISION_ID, &hw->revision_id);
- pci_read_config_word(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word);
-#endif
/* identify the MAC */
result = e1000_set_mac_type(hw);
@@ -5485,51 +5441,25 @@ void e1000_get_bus_type(struct e1000_hw *hw)
}
}
-#ifndef CONFIG_DM_ETH
-/* A list of all registered e1000 devices */
-static LIST_HEAD(e1000_hw_list);
-#endif
-
-#ifdef CONFIG_DM_ETH
static int e1000_init_one(struct e1000_hw *hw, int cardnum,
struct udevice *devno, unsigned char enetaddr[6])
-#else
-static int e1000_init_one(struct e1000_hw *hw, int cardnum, pci_dev_t devno,
- unsigned char enetaddr[6])
-#endif
{
u32 val;
/* Assign the passed-in values */
-#ifdef CONFIG_DM_ETH
- hw->pdev = devno;
-#else
hw->pdev = devno;
-#endif
hw->cardnum = cardnum;
/* Print a debug message with the IO base address */
-#ifdef CONFIG_DM_ETH
dm_pci_read_config32(devno, PCI_BASE_ADDRESS_0, &val);
-#else
- pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &val);
-#endif
E1000_DBG(hw, "iobase 0x%08x\n", val & 0xfffffff0);
/* Try to enable I/O accesses and bus-mastering */
val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
-#ifdef CONFIG_DM_ETH
dm_pci_write_config32(devno, PCI_COMMAND, val);
-#else
- pci_write_config_dword(devno, PCI_COMMAND, val);
-#endif
/* Make sure it worked */
-#ifdef CONFIG_DM_ETH
dm_pci_read_config32(devno, PCI_COMMAND, &val);
-#else
- pci_read_config_dword(devno, PCI_COMMAND, &val);
-#endif
if (!(val & PCI_COMMAND_MEMORY)) {
E1000_ERR(hw, "Can't enable I/O memory\n");
return -ENOSPC;
@@ -5548,13 +5478,8 @@ static int e1000_init_one(struct e1000_hw *hw, int cardnum, pci_dev_t devno,
#ifndef CONFIG_E1000_NO_NVM
hw->eeprom_semaphore_present = true;
#endif
-#ifdef CONFIG_DM_ETH
hw->hw_addr = dm_pci_map_bar(devno, PCI_BASE_ADDRESS_0, 0, 0,
PCI_REGION_TYPE, PCI_REGION_MEM);
-#else
- hw->hw_addr = pci_map_bar(devno, PCI_BASE_ADDRESS_0,
- PCI_REGION_MEM);
-#endif
hw->mac_type = e1000_undefined;
/* MAC and Phy settings */
@@ -5599,71 +5524,13 @@ static void e1000_name(char *str, int cardnum)
sprintf(str, "e1000#%u", cardnum);
}
-#ifndef CONFIG_DM_ETH
-/**************************************************************************
-TRANSMIT - Transmit a frame
-***************************************************************************/
-static int e1000_transmit(struct eth_device *nic, void *txpacket, int length)
-{
- struct e1000_hw *hw = nic->priv;
-
- return _e1000_transmit(hw, txpacket, length);
-}
-
-/**************************************************************************
-DISABLE - Turn off ethernet interface
-***************************************************************************/
-static void
-e1000_disable(struct eth_device *nic)
-{
- struct e1000_hw *hw = nic->priv;
-
- _e1000_disable(hw);
-}
-
-/**************************************************************************
-INIT - set up ethernet interface(s)
-***************************************************************************/
-static int
-e1000_init(struct eth_device *nic, struct bd_info *bis)
-{
- struct e1000_hw *hw = nic->priv;
-
- return _e1000_init(hw, nic->enetaddr);
-}
-
-static int
-e1000_poll(struct eth_device *nic)
-{
- struct e1000_hw *hw = nic->priv;
- int len;
-
- len = _e1000_poll(hw);
- if (len) {
- net_process_received_packet((uchar *)packet, len);
- fill_rx(hw);
- }
-
- return len ? 1 : 0;
-}
-#endif /* !CONFIG_DM_ETH */
-
-#ifdef CONFIG_DM_ETH
static int e1000_write_hwaddr(struct udevice *dev)
-#else
-static int e1000_write_hwaddr(struct eth_device *dev)
-#endif
{
#ifndef CONFIG_E1000_NO_NVM
unsigned char current_mac[6];
-#ifdef CONFIG_DM_ETH
struct eth_pdata *plat = dev_get_plat(dev);
struct e1000_hw *hw = dev_get_priv(dev);
u8 *mac = plat->enetaddr;
-#else
- struct e1000_hw *hw = dev->priv;
- u8 *mac = dev->enetaddr;
-#endif
uint16_t data[3];
int ret_val, i;
@@ -5701,87 +5568,16 @@ static int e1000_write_hwaddr(struct eth_device *dev)
#endif
}
-#ifndef CONFIG_DM_ETH
-/**************************************************************************
-PROBE - Look for an adapter, this routine's visible to the outside
-You should omit the last argument struct pci_device * for a non-PCI NIC
-***************************************************************************/
-int
-e1000_initialize(struct bd_info * bis)
-{
- unsigned int i;
- pci_dev_t devno;
- int ret;
-
- DEBUGFUNC();
-
- /* Find and probe all the matching PCI devices */
- for (i = 0; (devno = pci_find_devices(e1000_supported, i)) >= 0; i++) {
- /*
- * These will never get freed due to errors, this allows us to
- * perform SPI EEPROM programming from U-Boot, for example.
- */
- struct eth_device *nic = malloc(sizeof(*nic));
- struct e1000_hw *hw = malloc(sizeof(*hw));
- if (!nic || !hw) {
- printf("e1000#%u: Out of Memory!\n", i);
- free(nic);
- free(hw);
- continue;
- }
-
- /* Make sure all of the fields are initially zeroed */
- memset(nic, 0, sizeof(*nic));
- memset(hw, 0, sizeof(*hw));
- nic->priv = hw;
-
- /* Generate a card name */
- e1000_name(nic->name, i);
- hw->name = nic->name;
-
- ret = e1000_init_one(hw, i, devno, nic->enetaddr);
- if (ret)
- continue;
- list_add_tail(&hw->list_node, &e1000_hw_list);
-
- hw->nic = nic;
-
- /* Set up the function pointers and register the device */
- nic->init = e1000_init;
- nic->recv = e1000_poll;
- nic->send = e1000_transmit;
- nic->halt = e1000_disable;
- nic->write_hwaddr = e1000_write_hwaddr;
- eth_register(nic);
- }
-
- return i;
-}
-
-struct e1000_hw *e1000_find_card(unsigned int cardnum)
-{
- struct e1000_hw *hw;
-
- list_for_each_entry(hw, &e1000_hw_list, list_node)
- if (hw->cardnum == cardnum)
- return hw;
-
- return NULL;
-}
-#endif /* !CONFIG_DM_ETH */
-
#ifdef CONFIG_CMD_E1000
static int do_e1000(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
unsigned char *mac = NULL;
-#ifdef CONFIG_DM_ETH
struct eth_pdata *plat;
struct udevice *dev;
char name[30];
int ret;
-#endif
-#if !defined(CONFIG_DM_ETH) || defined(CONFIG_E1000_SPI)
+#if defined(CONFIG_E1000_SPI)
struct e1000_hw *hw;
#endif
int cardnum;
@@ -5793,18 +5589,12 @@ static int do_e1000(struct cmd_tbl *cmdtp, int flag, int argc,
/* Make sure we can find the requested e1000 card */
cardnum = dectoul(argv[1], NULL);
-#ifdef CONFIG_DM_ETH
e1000_name(name, cardnum);
ret = uclass_get_device_by_name(UCLASS_ETH, name, &dev);
if (!ret) {
plat = dev_get_plat(dev);
mac = plat->enetaddr;
}
-#else
- hw = e1000_find_card(cardnum);
- if (hw)
- mac = hw->nic->enetaddr;
-#endif
if (!mac) {
printf("e1000: ERROR: No such device: e1000#%s\n", argv[1]);
return 1;
@@ -5817,9 +5607,7 @@ static int do_e1000(struct cmd_tbl *cmdtp, int flag, int argc,
}
#ifdef CONFIG_E1000_SPI
-#ifdef CONFIG_DM_ETH
hw = dev_get_priv(dev);
-#endif
/* Handle the "SPI" subcommand */
if (!strcmp(argv[2], "spi"))
return do_e1000_spi(cmdtp, hw, argc - 3, argv + 3);
@@ -5843,7 +5631,6 @@ U_BOOT_CMD(
);
#endif /* not CONFIG_CMD_E1000 */
-#ifdef CONFIG_DM_ETH
static int e1000_eth_start(struct udevice *dev)
{
struct eth_pdata *plat = dev_get_plat(dev);
@@ -5948,4 +5735,3 @@ U_BOOT_DRIVER(eth_e1000) = {
};
U_BOOT_PCI_DEVICE(eth_e1000, e1000_supported);
-#endif
diff --git a/drivers/net/e1000.h b/drivers/net/e1000.h
index f96f12c8f44..f788394da87 100644
--- a/drivers/net/e1000.h
+++ b/drivers/net/e1000.h
@@ -21,10 +21,6 @@
#include <linux/list.h>
#include <malloc.h>
#include <net.h>
-/* Avoids a compile error since struct eth_device is not defined */
-#ifndef CONFIG_DM_ETH
-#include <netdev.h>
-#endif
#include <asm/io.h>
#include <pci.h>
@@ -1077,19 +1073,12 @@ typedef enum {
struct e1000_hw {
const char *name;
struct list_head list_node;
-#ifndef CONFIG_DM_ETH
- struct eth_device *nic;
-#endif
#ifdef CONFIG_E1000_SPI
struct spi_slave spi;
#endif
unsigned int cardnum;
-#ifdef CONFIG_DM_ETH
struct udevice *pdev;
-#else
- pci_dev_t pdev;
-#endif
uint8_t *hw_addr;
e1000_mac_type mac_type;
e1000_phy_type phy_type;
diff --git a/drivers/net/eepro100.c b/drivers/net/eepro100.c
index 935cd9c99ce..a0424505bde 100644
--- a/drivers/net/eepro100.c
+++ b/drivers/net/eepro100.c
@@ -206,27 +206,14 @@ struct eepro100_priv {
/* TX descriptor ring pointer */
int tx_next;
int tx_threshold;
-#ifdef CONFIG_DM_ETH
struct udevice *devno;
-#else
- struct eth_device dev;
- pci_dev_t devno;
-#endif
char *name;
void __iomem *iobase;
u8 *enetaddr;
};
-#if defined(CONFIG_DM_ETH)
#define bus_to_phys(dev, a) dm_pci_mem_to_phys((dev), (a))
#define phys_to_bus(dev, a) dm_pci_phys_to_mem((dev), (a))
-#elif defined(CONFIG_E500)
-#define bus_to_phys(dev, a) (a)
-#define phys_to_bus(dev, a) (a)
-#else
-#define bus_to_phys(dev, a) pci_mem_to_phys((dev), (a))
-#define phys_to_bus(dev, a) pci_phys_to_mem((dev), (a))
-#endif
static int INW(struct eepro100_priv *priv, u_long addr)
{
@@ -778,126 +765,6 @@ done:
return;
}
-#ifndef CONFIG_DM_ETH
-static int eepro100_init(struct eth_device *dev, struct bd_info *bis)
-{
- struct eepro100_priv *priv =
- container_of(dev, struct eepro100_priv, dev);
-
- return eepro100_init_common(priv);
-}
-
-static void eepro100_halt(struct eth_device *dev)
-{
- struct eepro100_priv *priv =
- container_of(dev, struct eepro100_priv, dev);
-
- eepro100_halt_common(priv);
-}
-
-static int eepro100_send(struct eth_device *dev, void *packet, int length)
-{
- struct eepro100_priv *priv =
- container_of(dev, struct eepro100_priv, dev);
-
- return eepro100_send_common(priv, packet, length);
-}
-
-static int eepro100_recv(struct eth_device *dev)
-{
- struct eepro100_priv *priv =
- container_of(dev, struct eepro100_priv, dev);
- uchar *packet;
- int ret;
-
- ret = eepro100_recv_common(priv, &packet);
- if (ret > 0)
- net_process_received_packet(packet, ret);
- if (ret)
- eepro100_free_pkt_common(priv);
-
- return ret;
-}
-
-int eepro100_initialize(struct bd_info *bis)
-{
- struct eepro100_priv *priv;
- struct eth_device *dev;
- int card_number = 0;
- u32 iobase, status;
- pci_dev_t devno;
- int idx = 0;
- int ret;
-
- while (1) {
- /* Find PCI device */
- devno = pci_find_devices(supported, idx++);
- if (devno < 0)
- break;
-
- pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &iobase);
- iobase &= ~0xf;
-
- debug("eepro100: Intel i82559 PCI EtherExpressPro @0x%x\n",
- iobase);
-
- pci_write_config_dword(devno, PCI_COMMAND,
- PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
-
- /* Check if I/O accesses and Bus Mastering are enabled. */
- pci_read_config_dword(devno, PCI_COMMAND, &status);
- if (!(status & PCI_COMMAND_MEMORY)) {
- printf("Error: Can not enable MEM access.\n");
- continue;
- }
-
- if (!(status & PCI_COMMAND_MASTER)) {
- printf("Error: Can not enable Bus Mastering.\n");
- continue;
- }
-
- priv = calloc(1, sizeof(*priv));
- if (!priv) {
- printf("eepro100: Can not allocate memory\n");
- break;
- }
- dev = &priv->dev;
-
- sprintf(dev->name, "i82559#%d", card_number);
- priv->name = dev->name;
- /* this have to come before bus_to_phys() */
- priv->devno = devno;
- priv->iobase = (void __iomem *)bus_to_phys(devno, iobase);
- priv->enetaddr = dev->enetaddr;
-
- dev->init = eepro100_init;
- dev->halt = eepro100_halt;
- dev->send = eepro100_send;
- dev->recv = eepro100_recv;
-
- eth_register(dev);
-
- ret = eepro100_initialize_mii(priv);
- if (ret) {
- eth_unregister(dev);
- free(priv);
- return ret;
- }
-
- card_number++;
-
- /* Set the latency timer for value. */
- pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x20);
-
- udelay(10 * 1000);
-
- eepro100_get_hwaddr(priv);
- }
-
- return card_number;
-}
-
-#else /* DM_ETH */
static int eepro100_start(struct udevice *dev)
{
struct eth_pdata *plat = dev_get_plat(dev);
@@ -1014,4 +881,3 @@ U_BOOT_DRIVER(eth_eepro100) = {
};
U_BOOT_PCI_DEVICE(eth_eepro100, supported);
-#endif
diff --git a/drivers/net/ethoc.c b/drivers/net/ethoc.c
index a219affb58a..29067e9e949 100644
--- a/drivers/net/ethoc.c
+++ b/drivers/net/ethoc.c
@@ -643,8 +643,6 @@ static inline int ethoc_phy_init(struct ethoc *priv, void *dev)
#endif
-#ifdef CONFIG_DM_ETH
-
static int ethoc_write_hwaddr(struct udevice *dev)
{
struct ethoc_eth_pdata *pdata = dev_get_plat(dev);
@@ -753,86 +751,3 @@ U_BOOT_DRIVER(ethoc) = {
.priv_auto = sizeof(struct ethoc),
.plat_auto = sizeof(struct ethoc_eth_pdata),
};
-
-#else
-
-static int ethoc_init(struct eth_device *dev, struct bd_info *bd)
-{
- struct ethoc *priv = (struct ethoc *)dev->priv;
-
- return ethoc_init_common(priv);
-}
-
-static int ethoc_write_hwaddr(struct eth_device *dev)
-{
- struct ethoc *priv = (struct ethoc *)dev->priv;
- u8 *mac = dev->enetaddr;
-
- return ethoc_write_hwaddr_common(priv, mac);
-}
-
-static int ethoc_send(struct eth_device *dev, void *packet, int length)
-{
- return ethoc_send_common(dev->priv, packet, length);
-}
-
-static void ethoc_halt(struct eth_device *dev)
-{
- ethoc_disable_rx_and_tx(dev->priv);
-}
-
-static int ethoc_recv(struct eth_device *dev)
-{
- struct ethoc *priv = (struct ethoc *)dev->priv;
- int count;
-
- if (!ethoc_is_new_packet_received(priv))
- return 0;
-
- for (count = 0; count < PKTBUFSRX; ++count) {
- uchar *packetp;
- int size = ethoc_rx_common(priv, &packetp);
-
- if (size < 0)
- break;
- if (size > 0)
- net_process_received_packet(packetp, size);
- ethoc_free_pkt_common(priv);
- }
- return 0;
-}
-
-int ethoc_initialize(u8 dev_num, int base_addr)
-{
- struct ethoc *priv;
- struct eth_device *dev;
-
- priv = malloc(sizeof(*priv));
- if (!priv)
- return 0;
- dev = malloc(sizeof(*dev));
- if (!dev) {
- free(priv);
- return 0;
- }
-
- memset(dev, 0, sizeof(*dev));
- dev->priv = priv;
- dev->iobase = base_addr;
- dev->init = ethoc_init;
- dev->halt = ethoc_halt;
- dev->send = ethoc_send;
- dev->recv = ethoc_recv;
- dev->write_hwaddr = ethoc_write_hwaddr;
- sprintf(dev->name, "%s-%hu", "ETHOC", dev_num);
- priv->iobase = ioremap(dev->iobase, ETHOC_IOSIZE);
-
- eth_register(dev);
-
- ethoc_mdio_init(dev->name, priv);
- ethoc_phy_init(priv, dev);
-
- return 1;
-}
-
-#endif
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index a61a1fc7573..ab52cc119f4 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -268,7 +268,6 @@ static int miiphy_restart_aneg(struct eth_device *dev)
return ret;
}
-#ifndef CONFIG_FEC_FIXED_SPEED
static int miiphy_wait_aneg(struct eth_device *dev)
{
uint32_t start;
@@ -294,7 +293,6 @@ static int miiphy_wait_aneg(struct eth_device *dev)
return 0;
}
-#endif /* CONFIG_FEC_FIXED_SPEED */
#endif
static int fec_rx_task_enable(struct fec_priv *fec)
@@ -536,8 +534,6 @@ static int fec_open(struct udevice *dev)
}
speed = fec->phydev->speed;
}
-#elif CONFIG_FEC_FIXED_SPEED
- speed = CONFIG_FEC_FIXED_SPEED;
#else
miiphy_wait_aneg(edev);
speed = miiphy_speed(edev->name, fec->phy_id);
@@ -1090,8 +1086,8 @@ static int fec_phy_init(struct fec_priv *priv, struct udevice *dev)
int addr;
addr = device_get_phy_addr(priv, dev);
-#ifdef CONFIG_FEC_MXC_PHYADDR
- addr = CONFIG_FEC_MXC_PHYADDR;
+#ifdef CFG_FEC_MXC_PHYADDR
+ addr = CFG_FEC_MXC_PHYADDR;
#endif
phydev = phy_connect(priv->bus, addr, dev, priv->interface);
diff --git a/drivers/net/fec_mxc.h b/drivers/net/fec_mxc.h
index 48faa33d66e..77bfc1cbf45 100644
--- a/drivers/net/fec_mxc.h
+++ b/drivers/net/fec_mxc.h
@@ -263,9 +263,7 @@ struct fec_priv {
uint32_t reset_delay;
uint32_t reset_post_delay;
#endif
-#ifdef CONFIG_DM_ETH
u32 interface;
-#endif
struct clk ipg_clk;
struct clk ahb_clk;
struct clk clk_enet_out;
diff --git a/drivers/net/fm/Makefile b/drivers/net/fm/Makefile
index 5a7d3037af4..b34209d2b3e 100644
--- a/drivers/net/fm/Makefile
+++ b/drivers/net/fm/Makefile
@@ -6,7 +6,6 @@ obj-y += dtsec.o
obj-y += eth.o
obj-y += fdt.o
obj-y += fm.o
-obj-y += init.o
obj-y += tgec.o
obj-y += tgec_phy.o
diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c
index c8381cc7133..9fd26de0d72 100644
--- a/drivers/net/fm/eth.c
+++ b/drivers/net/fm/eth.c
@@ -8,12 +8,10 @@
#include <log.h>
#include <part.h>
#include <asm/io.h>
-#ifdef CONFIG_DM_ETH
#include <dm.h>
#include <dm/ofnode.h>
#include <linux/compat.h>
#include <phy_interface.h>
-#endif
#include <malloc.h>
#include <net.h>
#include <hwconfig.h>
@@ -28,11 +26,6 @@
#include "fm.h"
-#ifndef CONFIG_DM_ETH
-static struct eth_device *devlist[NUM_FM_PORTS];
-static int num_controllers;
-#endif
-
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) && !defined(BITBANGMII)
#define TBIANA_SETTINGS (TBIANA_ASYMMETRIC_PAUSE | TBIANA_SYMMETRIC_PAUSE | \
@@ -53,14 +46,10 @@ static void dtsec_configure_serdes(struct fm_eth *priv)
PHY_INTERFACE_MODE_2500BASEX) ? true : false;
int i = 0, j;
-#ifndef CONFIG_DM_ETH
- bus.priv = priv->mac->phyregs;
-#else
bus.priv = priv->pcs_mdio;
bus.read = memac_mdio_read;
bus.write = memac_mdio_write;
bus.reset = memac_mdio_reset;
-#endif
qsgmii_loop:
/* SGMII IF mode + AN enable only for 1G SGMII, not for 2.5G */
@@ -136,19 +125,6 @@ static void dtsec_init_phy(struct fm_eth *fm_eth)
fm_eth->enet_if == PHY_INTERFACE_MODE_2500BASEX)
dtsec_configure_serdes(fm_eth);
}
-
-#ifndef CONFIG_DM_ETH
-#ifdef CONFIG_PHYLIB
-static int tgec_is_fibre(struct fm_eth *fm)
-{
- char phyopt[20];
-
- sprintf(phyopt, "fsl_fm%d_xaui_phy", fm->fm_index + 1);
-
- return hwconfig_arg_cmp(phyopt, "xfi");
-}
-#endif
-#endif /* CONFIG_DM_ETH */
#endif
static u16 muram_readw(u16 *addr)
@@ -465,18 +441,10 @@ static void fmc_tx_port_graceful_stop_disable(struct fm_eth *fm_eth)
sync();
}
-#ifndef CONFIG_DM_ETH
-static int fm_eth_open(struct eth_device *dev, struct bd_info *bd)
-#else
static int fm_eth_open(struct udevice *dev)
-#endif
{
-#ifndef CONFIG_DM_ETH
- struct fm_eth *fm_eth = dev->priv;
-#else
struct eth_pdata *pdata = dev_get_plat(dev);
struct fm_eth *fm_eth = dev_get_priv(dev);
-#endif
unsigned char *enetaddr;
struct fsl_enet_mac *mac;
#ifdef CONFIG_PHYLIB
@@ -485,11 +453,7 @@ static int fm_eth_open(struct udevice *dev)
mac = fm_eth->mac;
-#ifndef CONFIG_DM_ETH
- enetaddr = &dev->enetaddr[0];
-#else
enetaddr = pdata->enetaddr;
-#endif
/* setup the MAC address */
if (enetaddr[0] & 0x01) {
@@ -512,12 +476,7 @@ static int fm_eth_open(struct udevice *dev)
if (fm_eth->phydev) {
ret = phy_startup(fm_eth->phydev);
if (ret) {
-#ifndef CONFIG_DM_ETH
- printf("%s: Could not initialize\n",
- fm_eth->phydev->dev->name);
-#else
printf("%s: Could not initialize\n", dev->name);
-#endif
return ret;
}
} else {
@@ -540,20 +499,12 @@ static int fm_eth_open(struct udevice *dev)
return fm_eth->phydev->link ? 0 : -1;
}
-#ifndef CONFIG_DM_ETH
-static void fm_eth_halt(struct eth_device *dev)
-#else
static void fm_eth_halt(struct udevice *dev)
-#endif
{
struct fm_eth *fm_eth;
struct fsl_enet_mac *mac;
-#ifndef CONFIG_DM_ETH
- fm_eth = (struct fm_eth *)dev->priv;
-#else
fm_eth = dev_get_priv(dev);
-#endif
mac = fm_eth->mac;
/* graceful stop the transmission of frames */
@@ -571,11 +522,7 @@ static void fm_eth_halt(struct udevice *dev)
#endif
}
-#ifndef CONFIG_DM_ETH
-static int fm_eth_send(struct eth_device *dev, void *buf, int len)
-#else
static int fm_eth_send(struct udevice *dev, void *buf, int len)
-#endif
{
struct fm_eth *fm_eth;
struct fm_port_global_pram *pram;
@@ -583,11 +530,7 @@ static int fm_eth_send(struct udevice *dev, void *buf, int len)
u16 offset_in;
int i;
-#ifndef CONFIG_DM_ETH
- fm_eth = (struct fm_eth *)dev->priv;
-#else
fm_eth = dev_get_priv(dev);
-#endif
pram = fm_eth->tx_pram;
txbd = fm_eth->cur_txbd;
@@ -668,11 +611,7 @@ static struct fm_port_bd *fm_eth_free_one(struct fm_eth *fm_eth,
return rxbd;
}
-#ifndef CONFIG_DM_ETH
-static int fm_eth_recv(struct eth_device *dev)
-#else
static int fm_eth_recv(struct udevice *dev, int flags, uchar **packetp)
-#endif
{
struct fm_eth *fm_eth;
struct fm_port_bd *rxbd;
@@ -681,11 +620,7 @@ static int fm_eth_recv(struct udevice *dev, int flags, uchar **packetp)
int ret = -1;
u8 *data;
-#ifndef CONFIG_DM_ETH
- fm_eth = (struct fm_eth *)dev->priv;
-#else
fm_eth = dev_get_priv(dev);
-#endif
rxbd = fm_eth->cur_rxbd;
status = muram_readw(&rxbd->status);
@@ -695,12 +630,8 @@ static int fm_eth_recv(struct udevice *dev, int flags, uchar **packetp)
buf_lo = in_be32(&rxbd->buf_ptr_lo);
data = (u8 *)((ulong)(buf_hi << 16) << 16 | buf_lo);
len = muram_readw(&rxbd->len);
-#ifndef CONFIG_DM_ETH
- net_process_received_packet(data, len);
-#else
*packetp = data;
return len;
-#endif
} else {
printf("%s: Rx error\n", dev->name);
ret = 0;
@@ -717,7 +648,6 @@ static int fm_eth_recv(struct udevice *dev, int flags, uchar **packetp)
return ret;
}
-#ifdef CONFIG_DM_ETH
static int fm_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
{
struct fm_eth *fm_eth = (struct fm_eth *)dev_get_priv(dev);
@@ -726,65 +656,7 @@ static int fm_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
return 0;
}
-#endif /* CONFIG_DM_ETH */
-
-#ifndef CONFIG_DM_ETH
-static int fm_eth_init_mac(struct fm_eth *fm_eth, struct ccsr_fman *reg)
-{
- struct fsl_enet_mac *mac;
- int num;
- void *base, *phyregs = NULL;
-
- num = fm_eth->num;
-
-#ifdef CONFIG_SYS_FMAN_V3
-#ifndef CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
- if (fm_eth->type == FM_ETH_10G_E) {
- /* 10GEC1/10GEC2 use mEMAC9/mEMAC10 on T2080/T4240.
- * 10GEC3/10GEC4 use mEMAC1/mEMAC2 on T2080.
- * 10GEC1 uses mEMAC1 on T1024.
- * so it needs to change the num.
- */
- if (fm_eth->num >= 2)
- num -= 2;
- else
- num += 8;
- }
-#endif
- base = &reg->memac[num].fm_memac;
- phyregs = &reg->memac[num].fm_memac_mdio;
-#else
- /* Get the mac registers base address */
- if (fm_eth->type == FM_ETH_1G_E) {
- base = &reg->mac_1g[num].fm_dtesc;
- phyregs = &reg->mac_1g[num].fm_mdio.miimcfg;
- } else {
- base = &reg->mac_10g[num].fm_10gec;
- phyregs = &reg->mac_10g[num].fm_10gec_mdio;
- }
-#endif
-
- /* alloc mac controller */
- mac = malloc(sizeof(struct fsl_enet_mac));
- if (!mac)
- return -ENOMEM;
- memset(mac, 0, sizeof(struct fsl_enet_mac));
-
- /* save the mac to fm_eth struct */
- fm_eth->mac = mac;
-
-#ifdef CONFIG_SYS_FMAN_V3
- init_memac(mac, base, phyregs, MAX_RXBUF_LEN);
-#else
- if (fm_eth->type == FM_ETH_1G_E)
- init_dtsec(mac, base, phyregs, MAX_RXBUF_LEN);
- else
- init_tgec(mac, base, phyregs, MAX_RXBUF_LEN);
-#endif
- return 0;
-}
-#else /* CONFIG_DM_ETH */
static int fm_eth_init_mac(struct fm_eth *fm_eth, void *reg)
{
#ifndef CONFIG_SYS_FMAN_V3
@@ -817,15 +689,11 @@ static int fm_eth_init_mac(struct fm_eth *fm_eth, void *reg)
return 0;
}
-#endif /* CONFIG_DM_ETH */
static int init_phy(struct fm_eth *fm_eth)
{
#ifdef CONFIG_PHYLIB
u32 supported = PHY_GBIT_FEATURES;
-#ifndef CONFIG_DM_ETH
- struct phy_device *phydev = NULL;
-#endif
if (fm_eth->type == FM_ETH_10G_E)
supported = PHY_10G_FEATURES;
@@ -836,7 +704,6 @@ static int init_phy(struct fm_eth *fm_eth)
if (fm_eth->type == FM_ETH_1G_E)
dtsec_init_phy(fm_eth);
-#ifdef CONFIG_DM_ETH
#ifdef CONFIG_PHYLIB
#ifdef CONFIG_DM_MDIO
fm_eth->phydev = dm_eth_phy_connect(fm_eth->dev);
@@ -848,112 +715,8 @@ static int init_phy(struct fm_eth *fm_eth)
phy_config(fm_eth->phydev);
#endif
-#else /* CONFIG_DM_ETH */
-#ifdef CONFIG_PHYLIB
- if (fm_eth->bus) {
- phydev = phy_connect(fm_eth->bus, fm_eth->phyaddr, fm_eth->dev,
- fm_eth->enet_if);
- if (!phydev) {
- printf("Failed to connect\n");
- return -1;
- }
- } else {
- return 0;
- }
-
- if (fm_eth->type == FM_ETH_1G_E) {
- supported = (SUPPORTED_10baseT_Half |
- SUPPORTED_10baseT_Full |
- SUPPORTED_100baseT_Half |
- SUPPORTED_100baseT_Full |
- SUPPORTED_1000baseT_Full);
- } else {
- supported = SUPPORTED_10000baseT_Full;
-
- if (tgec_is_fibre(fm_eth))
- phydev->port = PORT_FIBRE;
- }
-
- phydev->supported &= supported;
- phydev->advertising = phydev->supported;
-
- fm_eth->phydev = phydev;
-
- phy_config(phydev);
-#endif
-#endif /* CONFIG_DM_ETH */
- return 0;
-}
-
-#ifndef CONFIG_DM_ETH
-int fm_eth_initialize(struct ccsr_fman *reg, struct fm_eth_info *info)
-{
- struct eth_device *dev;
- struct fm_eth *fm_eth;
- int i, num = info->num;
- int ret;
-
- /* alloc eth device */
- dev = (struct eth_device *)malloc(sizeof(struct eth_device));
- if (!dev)
- return -ENOMEM;
- memset(dev, 0, sizeof(struct eth_device));
-
- /* alloc the FMan ethernet private struct */
- fm_eth = (struct fm_eth *)malloc(sizeof(struct fm_eth));
- if (!fm_eth)
- return -ENOMEM;
- memset(fm_eth, 0, sizeof(struct fm_eth));
-
- /* save off some things we need from the info struct */
- fm_eth->fm_index = info->index - 1; /* keep as 0 based for muram */
- fm_eth->num = num;
- fm_eth->type = info->type;
-
- fm_eth->rx_port = (void *)&reg->port[info->rx_port_id - 1].fm_bmi;
- fm_eth->tx_port = (void *)&reg->port[info->tx_port_id - 1].fm_bmi;
-
- /* set the ethernet max receive length */
- fm_eth->max_rx_len = MAX_RXBUF_LEN;
-
- /* init global mac structure */
- ret = fm_eth_init_mac(fm_eth, reg);
- if (ret)
- return ret;
-
- /* keep same as the manual, we call FMAN1, FMAN2, DTSEC1, DTSEC2, etc */
- if (fm_eth->type == FM_ETH_1G_E)
- sprintf(dev->name, "FM%d@DTSEC%d", info->index, num + 1);
- else
- sprintf(dev->name, "FM%d@TGEC%d", info->index, num + 1);
-
- devlist[num_controllers++] = dev;
- dev->iobase = 0;
- dev->priv = (void *)fm_eth;
- dev->init = fm_eth_open;
- dev->halt = fm_eth_halt;
- dev->send = fm_eth_send;
- dev->recv = fm_eth_recv;
- fm_eth->dev = dev;
- fm_eth->bus = info->bus;
- fm_eth->phyaddr = info->phy_addr;
- fm_eth->enet_if = info->enet_if;
-
- /* startup the FM im */
- ret = fm_eth_startup(fm_eth);
- if (ret)
- return ret;
-
- init_phy(fm_eth);
-
- /* clear the ethernet address */
- for (i = 0; i < 6; i++)
- dev->enetaddr[i] = 0;
- eth_register(dev);
-
return 0;
}
-#else /* CONFIG_DM_ETH */
static int fm_eth_bind(struct udevice *dev)
{
@@ -1139,4 +902,3 @@ U_BOOT_DRIVER(eth_fman) = {
.plat_auto = sizeof(struct eth_pdata),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
-#endif /* CONFIG_DM_ETH */
diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c
index c476cb31200..055dd61fbe5 100644
--- a/drivers/net/fm/fm.c
+++ b/drivers/net/fm/fm.c
@@ -10,9 +10,7 @@
#include <asm/io.h>
#include <linux/errno.h>
#include <u-boot/crc.h>
-#ifdef CONFIG_DM_ETH
#include <dm.h>
-#endif
#include "fm.h"
#include <fsl_qe.h> /* For struct qe_firmware */
@@ -551,7 +549,6 @@ int fm_init_common(int index, struct ccsr_fman *reg)
}
#endif
-#ifdef CONFIG_DM_ETH
struct fman_priv {
struct ccsr_fman *reg;
unsigned int fman_id;
@@ -626,4 +623,3 @@ U_BOOT_DRIVER(fman) = {
.priv_auto = sizeof(struct fman_priv),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
-#endif /* CONFIG_DM_ETH */
diff --git a/drivers/net/fm/fm.h b/drivers/net/fm/fm.h
index 3d9cc5ca069..ba858cc24b0 100644
--- a/drivers/net/fm/fm.h
+++ b/drivers/net/fm/fm.h
@@ -57,7 +57,6 @@ struct fm_port_bd {
#define TxBD_READY 0x8000
#define TxBD_LAST BD_LAST
-#ifdef CONFIG_DM_ETH
enum fm_mac_type {
#ifdef CONFIG_SYS_FMAN_V3
FM_MEMAC,
@@ -66,7 +65,6 @@ enum fm_mac_type {
FM_TGEC,
#endif
};
-#endif
/* Fman ethernet private struct */
/* Rx/Tx queue descriptor */
@@ -115,9 +113,7 @@ void fman_disable_port(enum fm_port port);
void fman_enable_port(enum fm_port port);
int fman_id(struct udevice *dev);
void *fman_port(struct udevice *dev, int num);
-#ifdef CONFIG_DM_ETH
void *fman_mdio(struct udevice *dev, enum fm_mac_type type, int num);
-#endif
struct fsl_enet_mac {
void *base; /* MAC controller registers base address */
@@ -143,13 +139,9 @@ struct fm_eth {
struct mii_dev *bus;
struct phy_device *phydev;
int phyaddr;
-#ifndef CONFIG_DM_ETH
- struct eth_device *dev;
-#else
enum fm_mac_type mac_type;
struct udevice *dev;
struct udevice *pcs_mdio;
-#endif
int max_rx_len;
struct fm_port_global_pram *rx_pram; /* Rx parameter table */
struct fm_port_global_pram *tx_pram; /* Tx parameter table */
diff --git a/drivers/net/fm/init.c b/drivers/net/fm/init.c
deleted file mode 100644
index 618c1bccbe3..00000000000
--- a/drivers/net/fm/init.c
+++ /dev/null
@@ -1,386 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2011-2015 Freescale Semiconductor, Inc.
- */
-#include <errno.h>
-#include <common.h>
-#include <net.h>
-#include <asm/io.h>
-#include <fdt_support.h>
-#include <fsl_mdio.h>
-#ifdef CONFIG_FSL_LAYERSCAPE
-#include <asm/arch/fsl_serdes.h>
-#include <linux/libfdt.h>
-#else
-#include <asm/fsl_serdes.h>
-#endif
-
-#include "fm.h"
-
-#ifndef CONFIG_DM_ETH
-struct fm_eth_info fm_info[] = {
-#if (CFG_SYS_NUM_FM1_DTSEC >= 1)
- FM_DTSEC_INFO_INITIALIZER(1, 1),
-#endif
-#if (CFG_SYS_NUM_FM1_DTSEC >= 2)
- FM_DTSEC_INFO_INITIALIZER(1, 2),
-#endif
-#if (CFG_SYS_NUM_FM1_DTSEC >= 3)
- FM_DTSEC_INFO_INITIALIZER(1, 3),
-#endif
-#if (CFG_SYS_NUM_FM1_DTSEC >= 4)
- FM_DTSEC_INFO_INITIALIZER(1, 4),
-#endif
-#if (CFG_SYS_NUM_FM1_DTSEC >= 5)
- FM_DTSEC_INFO_INITIALIZER(1, 5),
-#endif
-#if (CFG_SYS_NUM_FM1_DTSEC >= 6)
- FM_DTSEC_INFO_INITIALIZER(1, 6),
-#endif
-#if (CFG_SYS_NUM_FM1_DTSEC >= 7)
- FM_DTSEC_INFO_INITIALIZER(1, 9),
-#endif
-#if (CFG_SYS_NUM_FM1_DTSEC >= 8)
- FM_DTSEC_INFO_INITIALIZER(1, 10),
-#endif
-#if (CFG_SYS_NUM_FM2_DTSEC >= 1)
- FM_DTSEC_INFO_INITIALIZER(2, 1),
-#endif
-#if (CFG_SYS_NUM_FM2_DTSEC >= 2)
- FM_DTSEC_INFO_INITIALIZER(2, 2),
-#endif
-#if (CFG_SYS_NUM_FM2_DTSEC >= 3)
- FM_DTSEC_INFO_INITIALIZER(2, 3),
-#endif
-#if (CFG_SYS_NUM_FM2_DTSEC >= 4)
- FM_DTSEC_INFO_INITIALIZER(2, 4),
-#endif
-#if (CFG_SYS_NUM_FM2_DTSEC >= 5)
- FM_DTSEC_INFO_INITIALIZER(2, 5),
-#endif
-#if (CFG_SYS_NUM_FM2_DTSEC >= 6)
- FM_DTSEC_INFO_INITIALIZER(2, 6),
-#endif
-#if (CFG_SYS_NUM_FM2_DTSEC >= 7)
- FM_DTSEC_INFO_INITIALIZER(2, 9),
-#endif
-#if (CFG_SYS_NUM_FM2_DTSEC >= 8)
- FM_DTSEC_INFO_INITIALIZER(2, 10),
-#endif
-#if (CFG_SYS_NUM_FM1_10GEC >= 1)
- FM_TGEC_INFO_INITIALIZER(1, 1),
-#endif
-#if (CFG_SYS_NUM_FM1_10GEC >= 2)
- FM_TGEC_INFO_INITIALIZER(1, 2),
-#endif
-#if (CFG_SYS_NUM_FM1_10GEC >= 3)
- FM_TGEC_INFO_INITIALIZER2(1, 3),
-#endif
-#if (CFG_SYS_NUM_FM1_10GEC >= 4)
- FM_TGEC_INFO_INITIALIZER2(1, 4),
-#endif
-#if (CFG_SYS_NUM_FM2_10GEC >= 1)
- FM_TGEC_INFO_INITIALIZER(2, 1),
-#endif
-#if (CFG_SYS_NUM_FM2_10GEC >= 2)
- FM_TGEC_INFO_INITIALIZER(2, 2),
-#endif
-};
-
-int fm_standard_init(struct bd_info *bis)
-{
- int i;
- struct ccsr_fman *reg;
-
- reg = (void *)CFG_SYS_FSL_FM1_ADDR;
- if (fm_init_common(0, reg))
- return 0;
-
- for (i = 0; i < ARRAY_SIZE(fm_info); i++) {
- if ((fm_info[i].enabled) && (fm_info[i].index == 1))
- fm_eth_initialize(reg, &fm_info[i]);
- }
-
-#if (CFG_SYS_NUM_FMAN == 2)
- reg = (void *)CFG_SYS_FSL_FM2_ADDR;
- if (fm_init_common(1, reg))
- return 0;
-
- for (i = 0; i < ARRAY_SIZE(fm_info); i++) {
- if ((fm_info[i].enabled) && (fm_info[i].index == 2))
- fm_eth_initialize(reg, &fm_info[i]);
- }
-#endif
-
- return 1;
-}
-
-/* simple linear search to map from port to array index */
-static int fm_port_to_index(enum fm_port port)
-{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(fm_info); i++) {
- if (fm_info[i].port == port)
- return i;
- }
-
- return -1;
-}
-
-/*
- * Determine if an interface is actually active based on HW config
- * we expect fman_port_enet_if() to report PHY_INTERFACE_MODE_NA if
- * the interface is not active based on HW cfg of the SoC
- */
-void fman_enet_init(void)
-{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(fm_info); i++) {
- phy_interface_t enet_if;
-
- enet_if = fman_port_enet_if(fm_info[i].port);
- if (enet_if != PHY_INTERFACE_MODE_NA) {
- fm_info[i].enabled = 1;
- fm_info[i].enet_if = enet_if;
- } else {
- fm_info[i].enabled = 0;
- }
- }
-
- return;
-}
-
-void fm_disable_port(enum fm_port port)
-{
- int i = fm_port_to_index(port);
-
- if (i == -1)
- return;
-
- fm_info[i].enabled = 0;
-#ifndef CONFIG_SYS_FMAN_V3
- fman_disable_port(port);
-#endif
-}
-
-void fm_enable_port(enum fm_port port)
-{
- int i = fm_port_to_index(port);
-
- if (i == -1)
- return;
-
- fm_info[i].enabled = 1;
- fman_enable_port(port);
-}
-
-void fm_info_set_mdio(enum fm_port port, struct mii_dev *bus)
-{
- int i = fm_port_to_index(port);
-
- if (i == -1)
- return;
-
- fm_info[i].bus = bus;
-}
-
-void fm_info_set_phy_address(enum fm_port port, int address)
-{
- int i = fm_port_to_index(port);
-
- if (i == -1)
- return;
-
- fm_info[i].phy_addr = address;
-}
-
-/*
- * Returns the PHY address for a given Fman port
- *
- * The port must be set via a prior call to fm_info_set_phy_address().
- * A negative error code is returned if the port is invalid.
- */
-int fm_info_get_phy_address(enum fm_port port)
-{
- int i = fm_port_to_index(port);
-
- if (i == -1)
- return -1;
-
- return fm_info[i].phy_addr;
-}
-
-/*
- * Returns the type of the data interface between the given MAC and its PHY.
- * This is typically determined by the RCW.
- */
-phy_interface_t fm_info_get_enet_if(enum fm_port port)
-{
- int i = fm_port_to_index(port);
-
- if (i == -1)
- return PHY_INTERFACE_MODE_NA;
-
- if (fm_info[i].enabled)
- return fm_info[i].enet_if;
-
- return PHY_INTERFACE_MODE_NA;
-}
-
-static void
-__def_board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
- enum fm_port port, int offset)
-{
- return;
-}
-
-void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
- enum fm_port port, int offset)
- __attribute__((weak, alias("__def_board_ft_fman_fixup_port")));
-
-int ft_fixup_port(void *blob, struct fm_eth_info *info, char *prop)
-{
- int off;
- uint32_t ph;
- phys_addr_t paddr = CFG_SYS_CCSRBAR_PHYS + info->compat_offset;
-#ifndef CONFIG_SYS_FMAN_V3
- u64 dtsec1_addr = (u64)CFG_SYS_CCSRBAR_PHYS +
- CFG_SYS_FSL_FM1_DTSEC1_OFFSET;
-#endif
-
- off = fdt_node_offset_by_compat_reg(blob, prop, paddr);
- if (off == -FDT_ERR_NOTFOUND)
- return -EINVAL;
-
- if (info->enabled) {
- fdt_fixup_phy_connection(blob, off, info->enet_if);
- board_ft_fman_fixup_port(blob, prop, paddr, info->port, off);
- return 0;
- }
-
-#ifdef CONFIG_SYS_FMAN_V3
-#ifndef CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
- /*
- * On T2/T4 SoCs, physically FM1_DTSEC9 and FM1_10GEC1 use the same
- * dual-role MAC, when FM1_10GEC1 is enabled and FM1_DTSEC9
- * is disabled, ensure that the dual-role MAC is not disabled,
- * ditto for other dual-role MACs.
- */
- if (((info->port == FM1_DTSEC9) && (PORT_IS_ENABLED(FM1_10GEC1))) ||
- ((info->port == FM1_DTSEC10) && (PORT_IS_ENABLED(FM1_10GEC2))) ||
- ((info->port == FM1_DTSEC1) && (PORT_IS_ENABLED(FM1_10GEC3))) ||
- ((info->port == FM1_DTSEC2) && (PORT_IS_ENABLED(FM1_10GEC4))) ||
- ((info->port == FM1_10GEC1) && (PORT_IS_ENABLED(FM1_DTSEC9))) ||
- ((info->port == FM1_10GEC2) && (PORT_IS_ENABLED(FM1_DTSEC10))) ||
- ((info->port == FM1_10GEC3) && (PORT_IS_ENABLED(FM1_DTSEC1))) ||
- ((info->port == FM1_10GEC4) && (PORT_IS_ENABLED(FM1_DTSEC2)))
-#if (CFG_SYS_NUM_FMAN == 2)
- ||
- ((info->port == FM2_DTSEC9) && (PORT_IS_ENABLED(FM2_10GEC1))) ||
- ((info->port == FM2_DTSEC10) && (PORT_IS_ENABLED(FM2_10GEC2))) ||
- ((info->port == FM2_10GEC1) && (PORT_IS_ENABLED(FM2_DTSEC9))) ||
- ((info->port == FM2_10GEC2) && (PORT_IS_ENABLED(FM2_DTSEC10)))
-#endif
-#else
- /* FM1_DTSECx and FM1_10GECx use the same dual-role MAC */
- if (((info->port == FM1_DTSEC1) && (PORT_IS_ENABLED(FM1_10GEC1))) ||
- ((info->port == FM1_DTSEC2) && (PORT_IS_ENABLED(FM1_10GEC2))) ||
- ((info->port == FM1_DTSEC3) && (PORT_IS_ENABLED(FM1_10GEC3))) ||
- ((info->port == FM1_DTSEC4) && (PORT_IS_ENABLED(FM1_10GEC4))) ||
- ((info->port == FM1_10GEC1) && (PORT_IS_ENABLED(FM1_DTSEC1))) ||
- ((info->port == FM1_10GEC2) && (PORT_IS_ENABLED(FM1_DTSEC2))) ||
- ((info->port == FM1_10GEC3) && (PORT_IS_ENABLED(FM1_DTSEC3))) ||
- ((info->port == FM1_10GEC4) && (PORT_IS_ENABLED(FM1_DTSEC4)))
-#endif
- )
- return 0;
-#endif
- /* board code might have caused offset to change */
- off = fdt_node_offset_by_compat_reg(blob, prop, paddr);
-
-#ifndef CONFIG_SYS_FMAN_V3
- /* Don't disable FM1-DTSEC1 MAC as its used for MDIO */
- if (paddr != dtsec1_addr)
-#endif
- fdt_status_disabled(blob, off); /* disable the MAC node */
-
- /* disable the fsl,dpa-ethernet node that points to the MAC */
- ph = fdt_get_phandle(blob, off);
- do_fixup_by_prop(blob, "fsl,fman-mac", &ph, sizeof(ph),
- "status", "disabled", strlen("disabled") + 1, 1);
-
- return 0;
-}
-
-void fdt_fixup_fman_ethernet(void *blob)
-{
- int i;
-
-#ifdef CONFIG_SYS_FMAN_V3
- for (i = 0; i < ARRAY_SIZE(fm_info); i++)
- ft_fixup_port(blob, &fm_info[i], "fsl,fman-memac");
-#else
- for (i = 0; i < ARRAY_SIZE(fm_info); i++) {
- /* Try the new compatible first.
- * If the node is missing, try the old.
- */
- if (fm_info[i].type == FM_ETH_1G_E) {
- if (ft_fixup_port(blob, &fm_info[i], "fsl,fman-dtsec"))
- ft_fixup_port(blob, &fm_info[i],
- "fsl,fman-1g-mac");
- } else {
- if (ft_fixup_port(blob, &fm_info[i], "fsl,fman-xgec") &&
- ft_fixup_port(blob, &fm_info[i], "fsl,fman-tgec"))
- ft_fixup_port(blob, &fm_info[i],
- "fsl,fman-10g-mac");
- }
- }
-#endif
-}
-
-/*QSGMII Riser Card can work in SGMII mode, but the PHY address is different.
- *This function scans which Riser Card being used(QSGMII or SGMII Riser Card),
- *then set the correct PHY address
- */
-void set_sgmii_phy(struct mii_dev *bus, enum fm_port base_port,
- unsigned int port_num, int phy_base_addr)
-{
- unsigned int regnum = 0;
- int qsgmii;
- int i;
- int phy_real_addr;
-
- qsgmii = is_qsgmii_riser_card(bus, phy_base_addr, port_num, regnum);
-
- if (!qsgmii)
- return;
-
- for (i = base_port; i < base_port + port_num; i++) {
- if (fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_SGMII) {
- phy_real_addr = phy_base_addr + i - base_port;
- fm_info_set_phy_address(i, phy_real_addr);
- }
- }
-}
-
-/*to check whether qsgmii riser card is used*/
-int is_qsgmii_riser_card(struct mii_dev *bus, int phy_base_addr,
- unsigned int port_num, unsigned regnum)
-{
- int i;
- int val;
-
- if (!bus)
- return 0;
-
- for (i = phy_base_addr; i < phy_base_addr + port_num; i++) {
- val = bus->read(bus, i, MDIO_DEVAD_NONE, regnum);
- if (val != MIIM_TIMEOUT)
- return 1;
- }
-
- return 0;
-}
-#endif /* CONFIG_DM_ETH */
diff --git a/drivers/net/fm/memac_phy.c b/drivers/net/fm/memac_phy.c
index 3ddae97e097..e0b62b94490 100644
--- a/drivers/net/fm/memac_phy.c
+++ b/drivers/net/fm/memac_phy.c
@@ -22,11 +22,9 @@
#define memac_setbits_32(a, v) setbits_be32(a, v)
#endif
-#ifdef CONFIG_DM_ETH
struct fm_mdio_priv {
struct memac_mdio_controller *regs;
};
-#endif
#define MAX_NUM_RETRIES 1000
@@ -88,9 +86,6 @@ int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr,
u32 c45 = 1; /* Default to 10G interface */
int err;
-#ifndef CONFIG_DM_ETH
- regs = bus->priv;
-#else
struct fm_mdio_priv *priv;
if (!bus->priv)
@@ -99,7 +94,6 @@ int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr,
regs = priv->regs;
debug("memac_mdio_write(regs %p, port %d, dev %d, reg %d, val %#x)\n",
regs, port_addr, dev_addr, regnum, value);
-#endif
if (dev_addr == MDIO_DEVAD_NONE) {
c45 = 0; /* clause 22 */
@@ -147,22 +141,14 @@ int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr,
u32 c45 = 1;
int err;
-#ifndef CONFIG_DM_ETH
- regs = bus->priv;
-#else
struct fm_mdio_priv *priv;
if (!bus->priv)
return -EINVAL;
priv = dev_get_priv(bus->priv);
regs = priv->regs;
-#endif
if (dev_addr == MDIO_DEVAD_NONE) {
-#ifndef CONFIG_DM_ETH
- if (!strcmp(bus->name, DEFAULT_FM_TGEC_MDIO_NAME))
- return 0xffff;
-#endif
c45 = 0; /* clause 22 */
dev_addr = regnum & 0x1f;
memac_clrbits_32(&regs->mdio_stat, MDIO_STAT_ENC);
@@ -205,43 +191,6 @@ int memac_mdio_reset(struct mii_dev *bus)
return 0;
}
-#ifndef CONFIG_DM_ETH
-int fm_memac_mdio_init(struct bd_info *bis, struct memac_mdio_info *info)
-{
- struct mii_dev *bus = mdio_alloc();
-
- if (!bus) {
- printf("Failed to allocate FM TGEC MDIO bus\n");
- return -1;
- }
-
- bus->read = memac_mdio_read;
- bus->write = memac_mdio_write;
- bus->reset = memac_mdio_reset;
- strcpy(bus->name, info->name);
-
- bus->priv = info->regs;
-
- /*
- * On some platforms like B4860, default value of MDIO_CLK_DIV bits
- * in mdio_stat(mdio_cfg) register generates MDIO clock too high
- * (much higher than 2.5MHz), violating the IEEE specs.
- * On other platforms like T1040, default value of MDIO_CLK_DIV bits
- * is zero, so MDIO clock is disabled.
- * So, for proper functioning of MDIO, MDIO_CLK_DIV bits needs to
- * be properly initialized.
- * NEG bit default should be '1' as per FMAN-v3 RM, but on platform
- * like T2080QDS, this bit default is '0', which leads to MDIO failure
- * on XAUI PHY, so set this bit definitely.
- */
- memac_setbits_32(
- &((struct memac_mdio_controller *)info->regs)->mdio_stat,
- MDIO_STAT_CLKDIV(258) | MDIO_STAT_NEG);
-
- return mdio_register(bus);
-}
-
-#else /* CONFIG_DM_ETH */
#if defined(CONFIG_PHYLIB) && defined(CONFIG_DM_MDIO)
static int fm_mdio_read(struct udevice *dev, int addr, int devad, int reg)
{
@@ -341,4 +290,3 @@ U_BOOT_DRIVER(fman_mdio) = {
.plat_auto = sizeof(struct mdio_perdev_priv),
};
#endif /* CONFIG_PHYLIB && CONFIG_DM_MDIO */
-#endif /* CONFIG_DM_ETH */
diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c
index 69da465eaab..6b36860187c 100644
--- a/drivers/net/fsl-mc/mc.c
+++ b/drivers/net/fsl-mc/mc.c
@@ -165,21 +165,12 @@ enum mc_fixup_type {
};
static int mc_fixup_mac_addr(void *blob, int nodeoffset,
-#ifdef CONFIG_DM_ETH
const char *propname, struct udevice *eth_dev,
-#else
- const char *propname, struct eth_device *eth_dev,
-#endif
enum mc_fixup_type type)
{
-#ifdef CONFIG_DM_ETH
struct eth_pdata *plat = dev_get_plat(eth_dev);
unsigned char *enetaddr = plat->enetaddr;
int eth_index = dev_seq(eth_dev);
-#else
- unsigned char *enetaddr = eth_dev->enetaddr;
- int eth_index = eth_dev->index;
-#endif
int err = 0, len = 0, size, i;
unsigned char env_enetaddr[ARP_HLEN];
unsigned int enetaddr_32[ARP_HLEN];
@@ -252,11 +243,7 @@ const char *dpl_get_connection_endpoint(void *blob, char *endpoint)
}
static int mc_fixup_dpl_mac_addr(void *blob, int dpmac_id,
-#ifdef CONFIG_DM_ETH
struct udevice *eth_dev)
-#else
- struct eth_device *eth_dev)
-#endif
{
int objoff = fdt_path_offset(blob, "/objects");
int dpmacoff = -1, dpnioff = -1;
@@ -355,11 +342,7 @@ void fdt_fsl_mc_fixup_iommu_map_entry(void *blob)
}
static int mc_fixup_dpc_mac_addr(void *blob, int dpmac_id,
-#ifdef CONFIG_DM_ETH
struct udevice *eth_dev)
-#else
- struct eth_device *eth_dev)
-#endif
{
int nodeoffset = fdt_path_offset(blob, "/board_info/ports"), noff;
int err = 0;
@@ -402,12 +385,8 @@ static int mc_fixup_dpc_mac_addr(void *blob, int dpmac_id,
static int mc_fixup_mac_addrs(void *blob, enum mc_fixup_type type)
{
int i, err = 0, ret = 0;
-#ifdef CONFIG_DM_ETH
#define ETH_NAME_LEN 20
struct udevice *eth_dev;
-#else
- struct eth_device *eth_dev;
-#endif
char ethname[ETH_NAME_LEN];
for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.c b/drivers/net/ldpaa_eth/ldpaa_eth.c
index b6f589eb91a..24850777949 100644
--- a/drivers/net/ldpaa_eth/ldpaa_eth.c
+++ b/drivers/net/ldpaa_eth/ldpaa_eth.c
@@ -24,7 +24,6 @@
#include "ldpaa_eth.h"
#ifdef CONFIG_PHYLIB
-#ifdef CONFIG_DM_ETH
static void init_phy(struct udevice *dev)
{
struct ldpaa_eth_priv *priv = dev_get_priv(dev);
@@ -36,51 +35,6 @@ static void init_phy(struct udevice *dev)
phy_config(priv->phy);
}
-#else
-static int init_phy(struct eth_device *dev)
-{
- struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)dev->priv;
- struct phy_device *phydev = NULL;
- struct mii_dev *bus;
- int phy_addr, phy_num;
- int ret = 0;
-
- bus = wriop_get_mdio(priv->dpmac_id);
- if (bus == NULL)
- return 0;
-
- for (phy_num = 0; phy_num < WRIOP_MAX_PHY_NUM; phy_num++) {
- phy_addr = wriop_get_phy_address(priv->dpmac_id, phy_num);
- if (phy_addr < 0)
- continue;
-
- phydev = phy_connect(bus, phy_addr, dev,
- wriop_get_enet_if(priv->dpmac_id));
- if (!phydev) {
- printf("Failed to connect\n");
- ret = -ENODEV;
- break;
- }
- wriop_set_phy_dev(priv->dpmac_id, phy_num, phydev);
- ret = phy_config(phydev);
- if (ret)
- break;
- }
-
- if (ret) {
- for (phy_num = 0; phy_num < WRIOP_MAX_PHY_NUM; phy_num++) {
- phydev = wriop_get_phy_dev(priv->dpmac_id, phy_num);
- if (!phydev)
- continue;
-
- free(phydev);
- wriop_set_phy_dev(priv->dpmac_id, phy_num, NULL);
- }
- }
-
- return ret;
-}
-#endif
#endif
#ifdef DEBUG
@@ -147,15 +101,9 @@ static void ldpaa_eth_get_dpni_counter(void)
}
}
-#ifdef CONFIG_DM_ETH
static void ldpaa_eth_get_dpmac_counter(struct udevice *dev)
{
struct ldpaa_eth_priv *priv = dev_get_priv(dev);
-#else
-static void ldpaa_eth_get_dpmac_counter(struct eth_device *net_dev)
-{
- struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)net_dev->priv;
-#endif
int err = 0;
u64 value;
@@ -288,16 +236,10 @@ error:
return;
}
-#ifdef CONFIG_DM_ETH
static int ldpaa_eth_pull_dequeue_rx(struct udevice *dev,
int flags, uchar **packetp)
{
struct ldpaa_eth_priv *priv = dev_get_priv(dev);
-#else
-static int ldpaa_eth_pull_dequeue_rx(struct eth_device *dev)
-{
- struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)dev->priv;
-#endif
const struct ldpaa_dq *dq;
const struct dpaa_fd *fd;
int i = 5, err = 0, status;
@@ -354,15 +296,9 @@ static int ldpaa_eth_pull_dequeue_rx(struct eth_device *dev)
return err;
}
-#ifdef CONFIG_DM_ETH
static int ldpaa_eth_tx(struct udevice *dev, void *buf, int len)
{
struct ldpaa_eth_priv *priv = dev_get_priv(dev);
-#else
-static int ldpaa_eth_tx(struct eth_device *net_dev, void *buf, int len)
-{
- struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)net_dev->priv;
-#endif
struct dpaa_fd fd;
u64 buffer_start;
int data_offset, err;
@@ -438,27 +374,6 @@ error:
return err;
}
-static struct phy_device *ldpaa_get_phydev(struct ldpaa_eth_priv *priv)
-{
-#ifdef CONFIG_DM_ETH
- return priv->phy;
-#else
-#ifdef CONFIG_PHYLIB
- struct phy_device *phydev = NULL;
- int phy_num;
-
- /* start the phy devices one by one and update the dpmac state */
- for (phy_num = 0; phy_num < WRIOP_MAX_PHY_NUM; phy_num++) {
- phydev = wriop_get_phy_dev(priv->dpmac_id, phy_num);
- if (phydev)
- return phydev;
- }
- return NULL;
-#endif
- return NULL;
-#endif
-}
-
static int ldpaa_get_dpmac_state(struct ldpaa_eth_priv *priv,
struct dpmac_link_state *state)
{
@@ -479,7 +394,7 @@ static int ldpaa_get_dpmac_state(struct ldpaa_eth_priv *priv,
state->up = 1;
state->options |= DPMAC_LINK_OPT_AUTONEG;
- phydev = ldpaa_get_phydev(priv);
+ phydev = priv->phy;
if (phydev) {
err = phy_startup(phydev);
@@ -509,16 +424,10 @@ static int ldpaa_get_dpmac_state(struct ldpaa_eth_priv *priv,
return 0;
}
-#ifdef CONFIG_DM_ETH
static int ldpaa_eth_open(struct udevice *dev)
{
struct eth_pdata *plat = dev_get_plat(dev);
struct ldpaa_eth_priv *priv = dev_get_priv(dev);
-#else
-static int ldpaa_eth_open(struct eth_device *net_dev, struct bd_info *bd)
-{
- struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)net_dev->priv;
-#endif
struct dpmac_link_state dpmac_link_state = { 0 };
#ifdef DEBUG
struct dpni_link_state link_state;
@@ -526,13 +435,8 @@ static int ldpaa_eth_open(struct eth_device *net_dev, struct bd_info *bd)
int err = 0;
struct dpni_queue d_queue;
-#ifdef CONFIG_DM_ETH
if (eth_is_active(dev))
return 0;
-#else
- if (net_dev->state == ETH_STATE_ACTIVE)
- return 0;
-#endif
if (get_mc_boot_status() != 0) {
printf("ERROR (MC is not booted)\n");
@@ -572,13 +476,8 @@ static int ldpaa_eth_open(struct eth_device *net_dev, struct bd_info *bd)
if (err)
goto err_dpni_bind;
-#ifdef CONFIG_DM_ETH
err = dpni_add_mac_addr(dflt_mc_io, MC_CMD_NO_FLAGS,
dflt_dpni->dpni_handle, plat->enetaddr);
-#else
- err = dpni_add_mac_addr(dflt_mc_io, MC_CMD_NO_FLAGS,
- dflt_dpni->dpni_handle, net_dev->enetaddr);
-#endif
if (err) {
printf("dpni_add_mac_addr() failed\n");
return err;
@@ -651,34 +550,18 @@ err_dpmac_setup:
return err;
}
-#ifdef CONFIG_DM_ETH
static void ldpaa_eth_stop(struct udevice *dev)
{
struct ldpaa_eth_priv *priv = dev_get_priv(dev);
-#else
-static void ldpaa_eth_stop(struct eth_device *net_dev)
-{
- struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)net_dev->priv;
-#endif
struct phy_device *phydev = NULL;
int err = 0;
-#ifdef CONFIG_DM_ETH
if (!eth_is_active(dev))
return;
-#else
- if ((net_dev->state == ETH_STATE_PASSIVE) ||
- (net_dev->state == ETH_STATE_INIT))
- return;
-#endif
#ifdef DEBUG
ldpaa_eth_get_dpni_counter();
-#ifdef CONFIG_DM_ETH
ldpaa_eth_get_dpmac_counter(dev);
-#else
- ldpaa_eth_get_dpmac_counter(net_dev);
-#endif
#endif
err = dprc_disconnect(dflt_mc_io, MC_CMD_NO_FLAGS,
@@ -702,7 +585,7 @@ static void ldpaa_eth_stop(struct eth_device *net_dev)
if (err < 0)
printf("dpni_disable() failed\n");
- phydev = ldpaa_get_phydev(priv);
+ phydev = priv->phy;
if (phydev)
phy_shutdown(phydev);
@@ -1097,7 +980,6 @@ static int ldpaa_dpni_bind(struct ldpaa_eth_priv *priv)
return 0;
}
-#ifdef CONFIG_DM_ETH
static int ldpaa_eth_probe(struct udevice *dev)
{
struct ofnode_phandle_args phandle;
@@ -1177,79 +1059,3 @@ U_BOOT_DRIVER(ldpaa_eth) = {
.priv_auto = sizeof(struct ldpaa_eth_priv),
.plat_auto = sizeof(struct eth_pdata),
};
-
-#else
-
-static int ldpaa_eth_netdev_init(struct eth_device *net_dev,
- phy_interface_t enet_if)
-{
- int err;
- struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)net_dev->priv;
-
- snprintf(net_dev->name, ETH_NAME_LEN, "DPMAC%d@%s", priv->dpmac_id,
- phy_interface_strings[enet_if]);
-
- net_dev->iobase = 0;
- net_dev->init = ldpaa_eth_open;
- net_dev->halt = ldpaa_eth_stop;
- net_dev->send = ldpaa_eth_tx;
- net_dev->recv = ldpaa_eth_pull_dequeue_rx;
-
-#ifdef CONFIG_PHYLIB
- err = init_phy(net_dev);
- if (err < 0)
- return err;
-#endif
-
- err = eth_register(net_dev);
- if (err < 0) {
- printf("eth_register() = %d\n", err);
- return err;
- }
-
- return 0;
-}
-
-int ldpaa_eth_init(int dpmac_id, phy_interface_t enet_if)
-{
- struct eth_device *net_dev = NULL;
- struct ldpaa_eth_priv *priv = NULL;
- int err = 0;
-
- /* Net device */
- net_dev = (struct eth_device *)malloc(sizeof(struct eth_device));
- if (!net_dev) {
- printf("eth_device malloc() failed\n");
- return -ENOMEM;
- }
- memset(net_dev, 0, sizeof(struct eth_device));
-
- /* alloc the ldpaa ethernet private struct */
- priv = (struct ldpaa_eth_priv *)malloc(sizeof(struct ldpaa_eth_priv));
- if (!priv) {
- printf("ldpaa_eth_priv malloc() failed\n");
- free(net_dev);
- return -ENOMEM;
- }
- memset(priv, 0, sizeof(struct ldpaa_eth_priv));
-
- net_dev->priv = (void *)priv;
- priv->net_dev = (struct eth_device *)net_dev;
- priv->dpmac_id = dpmac_id;
- debug("%s dpmac_id=%d\n", __func__, dpmac_id);
-
- err = ldpaa_eth_netdev_init(net_dev, enet_if);
- if (err)
- goto err_netdev_init;
-
- debug("ldpaa ethernet: Probed interface %s\n", net_dev->name);
- return 0;
-
-err_netdev_init:
- free(priv);
- net_dev->priv = NULL;
- free(net_dev);
-
- return err;
-}
-#endif
diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.h b/drivers/net/ldpaa_eth/ldpaa_eth.h
index e90513e56f9..16d0106233e 100644
--- a/drivers/net/ldpaa_eth/ldpaa_eth.h
+++ b/drivers/net/ldpaa_eth/ldpaa_eth.h
@@ -116,13 +116,9 @@ struct ldpaa_fas {
LDPAA_ETH_FAS_TIDE)
struct ldpaa_eth_priv {
-#ifdef CONFIG_DM_ETH
struct phy_device *phy;
int phy_mode;
bool started;
-#else
- struct eth_device *net_dev;
-#endif
uint32_t dpmac_id;
uint16_t dpmac_handle;
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index 65ec1f24ad2..bfc48dac079 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -33,9 +33,6 @@
*/
#include <net.h>
-#ifndef CONFIG_DM_ETH
-#include <netdev.h>
-#endif
#include <malloc.h>
#include <miiphy.h>
@@ -131,21 +128,16 @@ struct macb_device {
unsigned long dummy_desc_dma;
const struct device *dev;
-#ifndef CONFIG_DM_ETH
- struct eth_device netdev;
-#endif
unsigned short phy_addr;
struct mii_dev *bus;
#ifdef CONFIG_PHYLIB
struct phy_device *phydev;
#endif
-#ifdef CONFIG_DM_ETH
#ifdef CONFIG_CLK
unsigned long pclk_rate;
#endif
phy_interface_t phy_interface;
-#endif
};
struct macb_usrio_cfg {
@@ -164,10 +156,6 @@ struct macb_config {
const struct macb_usrio_cfg *usrio;
};
-#ifndef CONFIG_DM_ETH
-#define to_macb(_nd) container_of(_nd, struct macb_device, netdev)
-#endif
-
static int macb_is_gem(struct macb_device *macb)
{
return MACB_BFEXT(IDNUM, macb_readl(macb, MID)) >= 0x2;
@@ -258,13 +246,8 @@ void __weak arch_get_mdio_control(const char *name)
int macb_miiphy_read(struct mii_dev *bus, int phy_adr, int devad, int reg)
{
u16 value = 0;
-#ifdef CONFIG_DM_ETH
struct udevice *dev = eth_get_dev_by_name(bus->name);
struct macb_device *macb = dev_get_priv(dev);
-#else
- struct eth_device *dev = eth_get_dev_by_name(bus->name);
- struct macb_device *macb = to_macb(dev);
-#endif
arch_get_mdio_control(bus->name);
value = macb_mdio_read(macb, phy_adr, reg);
@@ -275,13 +258,8 @@ int macb_miiphy_read(struct mii_dev *bus, int phy_adr, int devad, int reg)
int macb_miiphy_write(struct mii_dev *bus, int phy_adr, int devad, int reg,
u16 value)
{
-#ifdef CONFIG_DM_ETH
struct udevice *dev = eth_get_dev_by_name(bus->name);
struct macb_device *macb = dev_get_priv(dev);
-#else
- struct eth_device *dev = eth_get_dev_by_name(bus->name);
- struct macb_device *macb = to_macb(dev);
-#endif
arch_get_mdio_control(bus->name);
macb_mdio_write(macb, phy_adr, reg, value);
@@ -598,7 +576,6 @@ static int macb_phy_find(struct macb_device *macb, const char *name)
* Returns 0 when operation success and negative errno number
* when operation failed.
*/
-#ifdef CONFIG_DM_ETH
static int macb_sifive_clk_init(struct udevice *dev, ulong rate)
{
void *gemgxl_regs;
@@ -678,22 +655,10 @@ int __weak macb_linkspd_cb(struct udevice *dev, unsigned int speed)
return 0;
}
-#else
-int __weak macb_linkspd_cb(void *regs, unsigned int speed)
-{
- return 0;
-}
-#endif
-#ifdef CONFIG_DM_ETH
static int macb_phy_init(struct udevice *dev, const char *name)
-#else
-static int macb_phy_init(struct macb_device *macb, const char *name)
-#endif
{
-#ifdef CONFIG_DM_ETH
struct macb_device *macb = dev_get_priv(dev);
-#endif
u32 ncfgr;
u16 phy_id, status, adv, lpa;
int media, speed, duplex;
@@ -714,14 +679,8 @@ static int macb_phy_init(struct macb_device *macb, const char *name)
}
#ifdef CONFIG_PHYLIB
-#ifdef CONFIG_DM_ETH
macb->phydev = phy_connect(macb->bus, macb->phy_addr, dev,
macb->phy_interface);
-#else
- /* need to consider other phy interface mode */
- macb->phydev = phy_connect(macb->bus, macb->phy_addr, &macb->netdev,
- PHY_INTERFACE_MODE_RGMII);
-#endif
if (!macb->phydev) {
printf("phy_connect failed\n");
return -ENODEV;
@@ -778,11 +737,7 @@ static int macb_phy_init(struct macb_device *macb, const char *name)
macb_writel(macb, NCFGR, ncfgr);
-#ifdef CONFIG_DM_ETH
ret = macb_linkspd_cb(dev, _1000BASET);
-#else
- ret = macb_linkspd_cb(macb->regs, _1000BASET);
-#endif
if (ret)
return ret;
@@ -807,17 +762,9 @@ static int macb_phy_init(struct macb_device *macb, const char *name)
ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD) | GEM_BIT(GBE));
if (speed) {
ncfgr |= MACB_BIT(SPD);
-#ifdef CONFIG_DM_ETH
ret = macb_linkspd_cb(dev, _100BASET);
-#else
- ret = macb_linkspd_cb(macb->regs, _100BASET);
-#endif
} else {
-#ifdef CONFIG_DM_ETH
ret = macb_linkspd_cb(dev, _10BASET);
-#else
- ret = macb_linkspd_cb(macb->regs, _10BASET);
-#endif
}
if (ret)
@@ -891,16 +838,10 @@ static void gmac_configure_dma(struct macb_device *macb)
gem_writel(macb, DMACFG, dmacfg);
}
-#ifdef CONFIG_DM_ETH
static int _macb_init(struct udevice *dev, const char *name)
-#else
-static int _macb_init(struct macb_device *macb, const char *name)
-#endif
{
-#ifdef CONFIG_DM_ETH
struct macb_device *macb = dev_get_priv(dev);
unsigned int val = 0;
-#endif
unsigned long paddr;
int ret;
int i;
@@ -969,7 +910,6 @@ static int _macb_init(struct macb_device *macb, const char *name)
* When the GMAC IP without GE feature, this bit is used
* to select interface between RMII and MII.
*/
-#ifdef CONFIG_DM_ETH
if (macb->phy_interface == PHY_INTERFACE_MODE_RGMII ||
macb->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
macb->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID ||
@@ -991,16 +931,8 @@ static int _macb_init(struct macb_device *macb, const char *name)
ncfgr |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
macb_writel(macb, NCFGR, ncfgr);
}
-#else
-#if defined(CONFIG_RGMII) || defined(CONFIG_RMII)
- gem_writel(macb, USRIO, macb->config->usrio->rgmii);
-#else
- gem_writel(macb, USRIO, 0);
-#endif
-#endif
} else {
/* choose RMII or MII mode. This depends on the board */
-#ifdef CONFIG_DM_ETH
#ifdef CONFIG_AT91FAMILY
if (macb->phy_interface == PHY_INTERFACE_MODE_RMII) {
macb_writel(macb, USRIO,
@@ -1015,29 +947,9 @@ static int _macb_init(struct macb_device *macb, const char *name)
else
macb_writel(macb, USRIO, macb->config->usrio->mii);
#endif
-#else
-#ifdef CONFIG_RMII
-#ifdef CONFIG_AT91FAMILY
- macb_writel(macb, USRIO, macb->config->usrio->rmii |
- macb->config->usrio->clken);
-#else
- macb_writel(macb, USRIO, 0);
-#endif
-#else
-#ifdef CONFIG_AT91FAMILY
- macb_writel(macb, USRIO, macb->config->usrio->clken);
-#else
- macb_writel(macb, USRIO, macb->config->usrio->mii);
-#endif
-#endif /* CONFIG_RMII */
-#endif
}
-#ifdef CONFIG_DM_ETH
ret = macb_phy_init(dev, name);
-#else
- ret = macb_phy_init(macb, name);
-#endif
if (ret)
return ret;
@@ -1081,7 +993,7 @@ static int _macb_write_hwaddr(struct macb_device *macb, unsigned char *enetaddr)
static u32 macb_mdc_clk_div(int id, struct macb_device *macb)
{
u32 config;
-#if defined(CONFIG_DM_ETH) && defined(CONFIG_CLK)
+#if defined(CONFIG_CLK)
unsigned long macb_hz = macb->pclk_rate;
#else
unsigned long macb_hz = get_macb_pclk_rate(id);
@@ -1103,7 +1015,7 @@ static u32 gem_mdc_clk_div(int id, struct macb_device *macb)
{
u32 config;
-#if defined(CONFIG_DM_ETH) && defined(CONFIG_CLK)
+#if defined(CONFIG_CLK)
unsigned long macb_hz = macb->pclk_rate;
#else
unsigned long macb_hz = get_macb_pclk_rate(id);
@@ -1182,106 +1094,6 @@ static void _macb_eth_initialize(struct macb_device *macb)
macb_writel(macb, NCFGR, ncfgr);
}
-#ifndef CONFIG_DM_ETH
-static int macb_send(struct eth_device *netdev, void *packet, int length)
-{
- struct macb_device *macb = to_macb(netdev);
-
- return _macb_send(macb, netdev->name, packet, length);
-}
-
-static int macb_recv(struct eth_device *netdev)
-{
- struct macb_device *macb = to_macb(netdev);
- uchar *packet;
- int length;
-
- macb->wrapped = false;
- for (;;) {
- macb->next_rx_tail = macb->rx_tail;
- length = _macb_recv(macb, &packet);
- if (length >= 0) {
- net_process_received_packet(packet, length);
- reclaim_rx_buffers(macb, macb->next_rx_tail);
- } else {
- return length;
- }
- }
-}
-
-static int macb_init(struct eth_device *netdev, struct bd_info *bd)
-{
- struct macb_device *macb = to_macb(netdev);
-
- return _macb_init(macb, netdev->name);
-}
-
-static void macb_halt(struct eth_device *netdev)
-{
- struct macb_device *macb = to_macb(netdev);
-
- return _macb_halt(macb);
-}
-
-static int macb_write_hwaddr(struct eth_device *netdev)
-{
- struct macb_device *macb = to_macb(netdev);
-
- return _macb_write_hwaddr(macb, netdev->enetaddr);
-}
-
-int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
-{
- struct macb_device *macb;
- struct eth_device *netdev;
-
- macb = malloc(sizeof(struct macb_device));
- if (!macb) {
- printf("Error: Failed to allocate memory for MACB%d\n", id);
- return -1;
- }
- memset(macb, 0, sizeof(struct macb_device));
-
- netdev = &macb->netdev;
-
- macb->regs = regs;
- macb->phy_addr = phy_addr;
-
- if (macb_is_gem(macb))
- sprintf(netdev->name, "gmac%d", id);
- else
- sprintf(netdev->name, "macb%d", id);
-
- netdev->init = macb_init;
- netdev->halt = macb_halt;
- netdev->send = macb_send;
- netdev->recv = macb_recv;
- netdev->write_hwaddr = macb_write_hwaddr;
-
- _macb_eth_initialize(macb);
-
- eth_register(netdev);
-
-#if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
- int retval;
- struct mii_dev *mdiodev = mdio_alloc();
- if (!mdiodev)
- return -ENOMEM;
- strlcpy(mdiodev->name, netdev->name, MDIO_NAME_LEN);
- mdiodev->read = macb_miiphy_read;
- mdiodev->write = macb_miiphy_write;
-
- retval = mdio_register(mdiodev);
- if (retval < 0)
- return retval;
- macb->bus = miiphy_get_dev_by_name(netdev->name);
-#endif
- return 0;
-}
-#endif /* !CONFIG_DM_ETH */
-
-#ifdef CONFIG_DM_ETH
-
static int macb_start(struct udevice *dev)
{
return _macb_init(dev, dev->name);
@@ -1536,5 +1348,3 @@ U_BOOT_DRIVER(eth_macb) = {
.plat_auto = sizeof(struct eth_pdata),
};
#endif
-
-#endif
diff --git a/drivers/net/mcfmii.c b/drivers/net/mcfmii.c
index e2c8f41876e..48dd558405c 100644
--- a/drivers/net/mcfmii.c
+++ b/drivers/net/mcfmii.c
@@ -85,11 +85,7 @@ void mii_reset(fec_info_t *info)
/* send command to phy using mii, wait for result */
uint mii_send(uint mii_cmd)
{
-#ifdef CONFIG_DM_ETH
struct udevice *dev;
-#else
- struct eth_device *dev;
-#endif
fec_info_t *info;
volatile FEC_T *ep;
uint mii_reply;
@@ -97,11 +93,7 @@ uint mii_send(uint mii_cmd)
/* retrieve from register structure */
dev = eth_get_dev();
-#ifdef CONFIG_DM_ETH
info = dev_get_priv(dev);
-#else
- info = dev->priv;
-#endif
ep = (FEC_T *) info->miibase;
@@ -202,11 +194,7 @@ int mii_discover_phy(fec_info_t *info)
__weak void mii_init(void)
{
-#ifdef CONFIG_DM_ETH
struct udevice *dev;
-#else
- struct eth_device *dev;
-#endif
fec_info_t *info;
volatile FEC_T *fecp;
int miispd = 0, i = 0;
@@ -215,11 +203,7 @@ __weak void mii_init(void)
/* retrieve from register structure */
dev = eth_get_dev();
-#ifdef CONFIG_DM_ETH
info = dev_get_priv(dev);
-#else
- info = dev->priv;
-#endif
fecp = (FEC_T *) info->miibase;
diff --git a/drivers/net/mscc_eswitch/Kconfig b/drivers/net/mscc_eswitch/Kconfig
index 930d2ef1130..f9780661c80 100644
--- a/drivers/net/mscc_eswitch/Kconfig
+++ b/drivers/net/mscc_eswitch/Kconfig
@@ -4,35 +4,35 @@
config MSCC_OCELOT_SWITCH
bool "Ocelot switch driver"
- depends on DM_ETH && ARCH_MSCC
+ depends on ARCH_MSCC
select PHYLIB
help
This driver supports the Ocelot network switch device.
config MSCC_LUTON_SWITCH
bool "Luton switch driver"
- depends on DM_ETH && ARCH_MSCC
+ depends on ARCH_MSCC
select PHYLIB
help
This driver supports the Luton network switch device.
config MSCC_JR2_SWITCH
bool "Jaguar2 switch driver"
- depends on DM_ETH && ARCH_MSCC
+ depends on ARCH_MSCC
select PHYLIB
help
This driver supports the Jaguar2 network switch device.
config MSCC_SERVALT_SWITCH
bool "Servalt switch driver"
- depends on DM_ETH && ARCH_MSCC
+ depends on ARCH_MSCC
select PHYLIB
help
This driver supports the Servalt network switch device.
config MSCC_SERVAL_SWITCH
bool "Serval switch driver"
- depends on DM_ETH && ARCH_MSCC
+ depends on ARCH_MSCC
select PHYLIB
help
This driver supports the Serval network switch device.
diff --git a/drivers/net/mvgbe.c b/drivers/net/mvgbe.c
index a77c0574326..3587ca2124e 100644
--- a/drivers/net/mvgbe.c
+++ b/drivers/net/mvgbe.c
@@ -37,10 +37,6 @@
DECLARE_GLOBAL_DATA_PTR;
-#ifndef CONFIG_MVGBE_PORTS
-# define CONFIG_MVGBE_PORTS {0, 0}
-#endif
-
#define MV_PHY_ADR_REQUEST 0xee
#define MVGBE_SMI_REG (((struct mvgbe_registers *)MVGBE0_BASE)->smi)
#define MVGBE_PGADR_REG 22
@@ -132,12 +128,7 @@ static int __mvgbe_mdio_read(struct mvgbe_device *dmvgbe, int phy_adr,
static int smi_reg_read(struct mii_dev *bus, int phy_adr, int devad,
int reg_ofs)
{
-#ifdef CONFIG_DM_ETH
struct mvgbe_device *dmvgbe = bus->priv;
-#else
- struct eth_device *dev = eth_get_dev_by_name(bus->name);
- struct mvgbe_device *dmvgbe = to_mvgbe(dev);
-#endif
return __mvgbe_mdio_read(dmvgbe, phy_adr, devad, reg_ofs);
}
@@ -189,12 +180,7 @@ static int __mvgbe_mdio_write(struct mvgbe_device *dmvgbe, int phy_adr,
static int smi_reg_write(struct mii_dev *bus, int phy_adr, int devad,
int reg_ofs, u16 data)
{
-#ifdef CONFIG_DM_ETH
struct mvgbe_device *dmvgbe = bus->priv;
-#else
- struct eth_device *dev = eth_get_dev_by_name(bus->name);
- struct mvgbe_device *dmvgbe = to_mvgbe(dev);
-#endif
return __mvgbe_mdio_write(dmvgbe, phy_adr, devad, reg_ofs, data);
}
@@ -432,12 +418,6 @@ static int __mvgbe_init(struct mvgbe_device *dmvgbe, u8 *enetaddr,
const char *name)
{
struct mvgbe_registers *regs = dmvgbe->regs;
-#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) && \
- !defined(CONFIG_PHYLIB) && \
- !defined(CONFIG_DM_ETH) && \
- defined(CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
- int i;
-#endif
/* setup RX rings */
mvgbe_init_rx_desc_ring(dmvgbe);
@@ -486,37 +466,9 @@ static int __mvgbe_init(struct mvgbe_device *dmvgbe, u8 *enetaddr,
/* Enable port Rx. */
MVGBE_REG_WR(regs->rqc, (1 << RXUQ));
-#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) && \
- !defined(CONFIG_PHYLIB) && \
- !defined(CONFIG_DM_ETH) && \
- defined(CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
- /* Wait up to 5s for the link status */
- for (i = 0; i < 5; i++) {
- u16 phyadr;
-
- miiphy_read(name, MV_PHY_ADR_REQUEST,
- MV_PHY_ADR_REQUEST, &phyadr);
- /* Return if we get link up */
- if (miiphy_link(name, phyadr))
- return 0;
- udelay(1000000);
- }
-
- printf("No link on %s\n", name);
- return -1;
-#endif
return 0;
}
-#ifndef CONFIG_DM_ETH
-static int mvgbe_init(struct eth_device *dev)
-{
- struct mvgbe_device *dmvgbe = to_mvgbe(dev);
-
- return __mvgbe_init(dmvgbe, dmvgbe->dev.enetaddr, dmvgbe->dev.name);
-}
-#endif
-
static void __mvgbe_halt(struct mvgbe_device *dmvgbe)
{
struct mvgbe_registers *regs = dmvgbe->regs;
@@ -542,18 +494,6 @@ static void __mvgbe_halt(struct mvgbe_device *dmvgbe)
MVGBE_REG_WR(regs->peim, 0);
}
-#ifndef CONFIG_DM_ETH
-static int mvgbe_halt(struct eth_device *dev)
-{
- struct mvgbe_device *dmvgbe = to_mvgbe(dev);
-
- __mvgbe_halt(dmvgbe);
-
- return 0;
-}
-#endif
-
-#ifdef CONFIG_DM_ETH
static int mvgbe_write_hwaddr(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_plat(dev);
@@ -562,16 +502,6 @@ static int mvgbe_write_hwaddr(struct udevice *dev)
return 0;
}
-#else
-static int mvgbe_write_hwaddr(struct eth_device *dev)
-{
- struct mvgbe_device *dmvgbe = to_mvgbe(dev);
-
- /* Programs net device MAC address after initialization */
- port_uc_addr_set(dmvgbe, dmvgbe->dev.enetaddr);
- return 0;
-}
-#endif
static int __mvgbe_send(struct mvgbe_device *dmvgbe, void *dataptr,
int datasize)
@@ -628,15 +558,6 @@ static int __mvgbe_send(struct mvgbe_device *dmvgbe, void *dataptr,
return 0;
}
-#ifndef CONFIG_DM_ETH
-static int mvgbe_send(struct eth_device *dev, void *dataptr, int datasize)
-{
- struct mvgbe_device *dmvgbe = to_mvgbe(dev);
-
- return __mvgbe_send(dmvgbe, dataptr, datasize);
-}
-#endif
-
static int __mvgbe_recv(struct mvgbe_device *dmvgbe, uchar **packetp)
{
struct mvgbe_rxdesc *p_rxdesc_curr = dmvgbe->p_rxdesc_curr;
@@ -710,35 +631,11 @@ static int __mvgbe_recv(struct mvgbe_device *dmvgbe, uchar **packetp)
return rx_bytes;
}
-#ifndef CONFIG_DM_ETH
-static int mvgbe_recv(struct eth_device *dev)
-{
- struct mvgbe_device *dmvgbe = to_mvgbe(dev);
- uchar *packet;
- int ret;
-
- ret = __mvgbe_recv(dmvgbe, &packet);
- if (ret < 0)
- return ret;
-
- net_process_received_packet(packet, ret);
-
- return 0;
-}
-#endif
-
-#if defined(CONFIG_PHYLIB) || defined(CONFIG_DM_ETH)
-#if defined(CONFIG_DM_ETH)
+#if defined(CONFIG_PHYLIB)
static struct phy_device *__mvgbe_phy_init(struct udevice *dev,
struct mii_dev *bus,
phy_interface_t phy_interface,
int phyid)
-#else
-static struct phy_device *__mvgbe_phy_init(struct eth_device *dev,
- struct mii_dev *bus,
- phy_interface_t phy_interface,
- int phyid)
-#endif
{
struct phy_device *phydev;
@@ -760,38 +657,7 @@ static struct phy_device *__mvgbe_phy_init(struct eth_device *dev,
return phydev;
}
-#endif /* CONFIG_PHYLIB || CONFIG_DM_ETH */
-
-#if defined(CONFIG_PHYLIB) && !defined(CONFIG_DM_ETH)
-int mvgbe_phylib_init(struct eth_device *dev, int phyid)
-{
- struct mii_dev *bus;
- struct phy_device *phydev;
- int ret;
-
- bus = mdio_alloc();
- if (!bus) {
- printf("mdio_alloc failed\n");
- return -ENOMEM;
- }
- bus->read = smi_reg_read;
- bus->write = smi_reg_write;
- strcpy(bus->name, dev->name);
-
- ret = mdio_register(bus);
- if (ret) {
- printf("mdio_register failed\n");
- free(bus);
- return -ENOMEM;
- }
-
- phydev = __mvgbe_phy_init(dev, bus, PHY_INTERFACE_MODE_RGMII, phyid);
- if (!phydev)
- return -ENODEV;
-
- return 0;
-}
-#endif
+#endif /* CONFIG_PHYLIB */
static int mvgbe_alloc_buffers(struct mvgbe_device *dmvgbe)
{
@@ -825,85 +691,6 @@ error1:
return -ENOMEM;
}
-#ifndef CONFIG_DM_ETH
-int mvgbe_initialize(struct bd_info *bis)
-{
- struct mvgbe_device *dmvgbe;
- struct eth_device *dev;
- int devnum;
- int ret;
- u8 used_ports[MAX_MVGBE_DEVS] = CONFIG_MVGBE_PORTS;
-
- for (devnum = 0; devnum < MAX_MVGBE_DEVS; devnum++) {
- /*skip if port is configured not to use */
- if (used_ports[devnum] == 0)
- continue;
-
- dmvgbe = malloc(sizeof(struct mvgbe_device));
- if (!dmvgbe)
- return -ENOMEM;
-
- memset(dmvgbe, 0, sizeof(struct mvgbe_device));
- ret = mvgbe_alloc_buffers(dmvgbe);
- if (ret) {
- printf("Err.. %s Failed to allocate memory\n",
- __func__);
- free(dmvgbe);
- return ret;
- }
-
- dev = &dmvgbe->dev;
-
- /* must be less than sizeof(dev->name) */
- sprintf(dev->name, "egiga%d", devnum);
-
- switch (devnum) {
- case 0:
- dmvgbe->regs = (void *)MVGBE0_BASE;
- break;
-#if defined(MVGBE1_BASE)
- case 1:
- dmvgbe->regs = (void *)MVGBE1_BASE;
- break;
-#endif
- default: /* this should never happen */
- printf("Err..(%s) Invalid device number %d\n",
- __func__, devnum);
- return -1;
- }
-
- dev->init = (void *)mvgbe_init;
- dev->halt = (void *)mvgbe_halt;
- dev->send = (void *)mvgbe_send;
- dev->recv = (void *)mvgbe_recv;
- dev->write_hwaddr = (void *)mvgbe_write_hwaddr;
-
- eth_register(dev);
-
-#if defined(CONFIG_PHYLIB)
- mvgbe_phylib_init(dev, PHY_BASE_ADR + devnum);
-#elif defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
- int retval;
- struct mii_dev *mdiodev = mdio_alloc();
- if (!mdiodev)
- return -ENOMEM;
- strlcpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
- mdiodev->read = smi_reg_read;
- mdiodev->write = smi_reg_write;
-
- retval = mdio_register(mdiodev);
- if (retval < 0)
- return retval;
- /* Set phy address of the port */
- miiphy_write(dev->name, MV_PHY_ADR_REQUEST,
- MV_PHY_ADR_REQUEST, PHY_BASE_ADR + devnum);
-#endif
- }
- return 0;
-}
-#endif
-
-#ifdef CONFIG_DM_ETH
static int mvgbe_port_is_fixed_link(struct mvgbe_device *dmvgbe)
{
return dmvgbe->phyaddr > PHY_MAX_ADDR;
@@ -1046,4 +833,3 @@ U_BOOT_DRIVER(mvgbe) = {
.priv_auto = sizeof(struct mvgbe_device),
.plat_auto = sizeof(struct eth_pdata),
};
-#endif /* CONFIG_DM_ETH */
diff --git a/drivers/net/mvgbe.h b/drivers/net/mvgbe.h
index 44541c0a85e..6514ab67bab 100644
--- a/drivers/net/mvgbe.h
+++ b/drivers/net/mvgbe.h
@@ -11,13 +11,6 @@
#ifndef __MVGBE_H__
#define __MVGBE_H__
-/* PHY_BASE_ADR is board specific and can be configured */
-#if defined (CONFIG_PHY_BASE_ADR)
-#define PHY_BASE_ADR CONFIG_PHY_BASE_ADR
-#else
-#define PHY_BASE_ADR 0x08 /* default phy base addr */
-#endif
-
/* Constants */
#define INT_CAUSE_UNMASK_ALL 0x0007ffff
#define INT_CAUSE_UNMASK_ALL_EXT 0x0011ffff
@@ -30,9 +23,6 @@
#define RXUQ 0 /* Used Rx queue */
#define TXUQ 0 /* Used Rx queue */
-#ifndef CONFIG_DM_ETH
-#define to_mvgbe(_d) container_of(_d, struct mvgbe_device, dev)
-#endif
#define MVGBE_REG_WR(adr, val) writel(val, &adr)
#define MVGBE_REG_RD(adr) readl(&adr)
#define MVGBE_REG_BITS_RESET(adr, val) writel(readl(&adr) & ~(val), &adr)
@@ -481,9 +471,6 @@ struct mvgbe_txdesc {
/* port device data struct */
struct mvgbe_device {
-#ifndef CONFIG_DM_ETH
- struct eth_device dev;
-#endif
struct mvgbe_registers *regs;
struct mvgbe_txdesc *p_txdesc;
struct mvgbe_rxdesc *p_rxdesc;
@@ -491,7 +478,6 @@ struct mvgbe_device {
u8 *p_rxbuf;
u8 *p_aligned_txbuf;
-#ifdef CONFIG_DM_ETH
phy_interface_t phy_interface;
unsigned int link;
unsigned int duplex;
@@ -501,7 +487,6 @@ struct mvgbe_device {
int phyaddr;
struct phy_device *phydev;
struct mii_dev *bus;
-#endif
};
#endif /* __MVGBE_H__ */
diff --git a/drivers/net/netconsole.c b/drivers/net/netconsole.c
index cec96c57150..1e52917ff2c 100644
--- a/drivers/net/netconsole.c
+++ b/drivers/net/netconsole.c
@@ -172,11 +172,7 @@ int nc_input_packet(uchar *pkt, struct in_addr src_ip, unsigned dest_port,
static void nc_send_packet(const char *buf, int len)
{
-#ifdef CONFIG_DM_ETH
struct udevice *eth;
-#else
- struct eth_device *eth;
-#endif
int inited = 0;
uchar *pkt;
uchar *ether;
@@ -298,11 +294,7 @@ static int nc_stdio_getc(struct stdio_dev *dev)
static int nc_stdio_tstc(struct stdio_dev *dev)
{
-#ifdef CONFIG_DM_ETH
struct udevice *eth;
-#else
- struct eth_device *eth;
-#endif
if (input_recursion)
return 0;
diff --git a/drivers/net/pcnet.c b/drivers/net/pcnet.c
index 59ef1043349..a1f3c2bd290 100644
--- a/drivers/net/pcnet.c
+++ b/drivers/net/pcnet.c
@@ -83,13 +83,8 @@ struct pcnet_priv {
/* Receive Buffer space */
unsigned char rx_buf[RX_RING_SIZE][PKT_BUF_SZ + 4];
struct pcnet_uncached_priv *uc;
-#ifdef CONFIG_DM_ETH
struct udevice *dev;
const char *name;
-#else
- pci_dev_t dev;
- char *name;
-#endif
void __iomem *iobase;
u8 *enetaddr;
u16 status;
@@ -142,11 +137,7 @@ static inline pci_addr_t pcnet_virt_to_mem(struct pcnet_priv *lp, void *addr)
{
void *virt_addr = addr;
-#ifdef CONFIG_DM_ETH
return dm_pci_virt_to_mem(lp->dev, virt_addr);
-#else
- return pci_virt_to_mem(lp->dev, virt_addr);
-#endif
}
static struct pci_device_id supported[] = {
@@ -457,132 +448,6 @@ static void pcnet_halt_common(struct pcnet_priv *lp)
printf("%s: TIMEOUT: controller reset failed\n", lp->name);
}
-#ifndef CONFIG_DM_ETH
-static int pcnet_init(struct eth_device *dev, struct bd_info *bis)
-{
- struct pcnet_priv *lp = dev->priv;
-
- return pcnet_init_common(lp);
-}
-
-static int pcnet_send(struct eth_device *dev, void *packet, int pkt_len)
-{
- struct pcnet_priv *lp = dev->priv;
-
- return pcnet_send_common(lp, packet, pkt_len);
-}
-
-static int pcnet_recv(struct eth_device *dev)
-{
- struct pcnet_priv *lp = dev->priv;
- uchar *packet;
- int ret;
-
- ret = pcnet_recv_common(lp, &packet);
- if (ret > 0)
- net_process_received_packet(packet, ret);
- if (ret)
- pcnet_free_pkt_common(lp, ret);
-
- return ret;
-}
-
-static void pcnet_halt(struct eth_device *dev)
-{
- struct pcnet_priv *lp = dev->priv;
-
- pcnet_halt_common(lp);
-}
-
-int pcnet_initialize(struct bd_info *bis)
-{
- pci_dev_t devbusfn;
- struct eth_device *dev;
- struct pcnet_priv *lp;
- u16 command, status;
- int dev_nr = 0;
- u32 bar;
-
- PCNET_DEBUG1("\n%s...\n", __func__);
-
- for (dev_nr = 0; ; dev_nr++) {
- /*
- * Find the PCnet PCI device(s).
- */
- devbusfn = pci_find_devices(supported, dev_nr);
- if (devbusfn < 0)
- break;
-
- /*
- * Allocate and pre-fill the device structure.
- */
- dev = calloc(1, sizeof(*dev));
- if (!dev) {
- printf("pcnet: Can not allocate memory\n");
- break;
- }
-
- /*
- * We only maintain one structure because the drivers will
- * never be used concurrently. In 32bit mode the RX and TX
- * ring entries must be aligned on 16-byte boundaries.
- */
- lp = malloc_cache_aligned(sizeof(*lp));
- lp->uc = map_physmem((phys_addr_t)&lp->ucp,
- sizeof(lp->ucp), MAP_NOCACHE);
- lp->dev = devbusfn;
- flush_dcache_range((unsigned long)lp,
- (unsigned long)lp + sizeof(*lp));
- dev->priv = lp;
- sprintf(dev->name, "pcnet#%d", dev_nr);
- lp->name = dev->name;
- lp->enetaddr = dev->enetaddr;
-
- /*
- * Setup the PCI device.
- */
- pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, &bar);
- lp->iobase = (void *)(pci_mem_to_phys(devbusfn, bar) & ~0xf);
-
- PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%p: ",
- lp->name, devbusfn, lp->iobase);
-
- command = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
- pci_write_config_word(devbusfn, PCI_COMMAND, command);
- pci_read_config_word(devbusfn, PCI_COMMAND, &status);
- if ((status & command) != command) {
- printf("%s: Couldn't enable IO access or Bus Mastering\n",
- lp->name);
- free(dev);
- continue;
- }
-
- pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x40);
-
- /*
- * Probe the PCnet chip.
- */
- if (pcnet_probe_common(lp) < 0) {
- free(dev);
- continue;
- }
-
- /*
- * Setup device structure and register the driver.
- */
- dev->init = pcnet_init;
- dev->halt = pcnet_halt;
- dev->send = pcnet_send;
- dev->recv = pcnet_recv;
-
- eth_register(dev);
- }
-
- udelay(10 * 1000);
-
- return dev_nr;
-}
-#else /* DM_ETH */
static int pcnet_start(struct udevice *dev)
{
struct eth_pdata *plat = dev_get_plat(dev);
@@ -695,4 +560,3 @@ U_BOOT_DRIVER(eth_pcnet) = {
};
U_BOOT_PCI_DEVICE(eth_pcnet, supported);
-#endif
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 86e698190f8..580ac8e8fba 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -315,7 +315,6 @@ config PHY_XILINX
config PHY_XILINX_GMII2RGMII
bool "Xilinx GMII to RGMII Ethernet PHYs support"
- depends on DM_ETH
help
This adds support for Xilinx GMII to RGMII IP core. This IP acts
as bridge between MAC connected over GMII and external phy that
@@ -336,7 +335,6 @@ config PHY_ETHERNET_ID
config PHY_FIXED
bool "Fixed-Link PHY"
- depends on DM_ETH
help
Fixed PHY is used for having a 'fixed-link' to another MAC with a direct
connection (MII, RGMII, ...).
@@ -346,7 +344,6 @@ config PHY_FIXED
config PHY_NCSI
bool "NC-SI based PHY"
- depends on DM_ETH
endif #PHYLIB
diff --git a/drivers/net/phy/aquantia.c b/drivers/net/phy/aquantia.c
index 79fbc115368..8eb6024829d 100644
--- a/drivers/net/phy/aquantia.c
+++ b/drivers/net/phy/aquantia.c
@@ -338,7 +338,6 @@ static int aquantia_set_proto(struct phy_device *phydev,
static int aquantia_dts_config(struct phy_device *phydev)
{
-#ifdef CONFIG_DM_ETH
ofnode node = phydev->node;
u32 prop;
u16 reg;
@@ -374,7 +373,6 @@ static int aquantia_dts_config(struct phy_device *phydev)
(u16)(prop << 1));
}
-#endif
return 0;
}
diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
index fa1fe08518f..c6f9f916459 100644
--- a/drivers/net/phy/atheros.c
+++ b/drivers/net/phy/atheros.c
@@ -191,7 +191,6 @@ static int ar803x_regs_config(struct phy_device *phydev)
static int ar803x_of_init(struct phy_device *phydev)
{
-#if defined(CONFIG_DM_ETH)
struct ar803x_priv *priv;
ofnode node, vddio_reg_node;
u32 strength, freq, min_uV, max_uV;
@@ -306,7 +305,6 @@ static int ar803x_of_init(struct phy_device *phydev)
debug("%s: flags=%x clk_25m_reg=%04x clk_25m_mask=%04x\n", __func__,
priv->flags, priv->clk_25m_reg, priv->clk_25m_mask);
-#endif
return 0;
}
diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c
index 3d862636b6b..a45152bddc9 100644
--- a/drivers/net/phy/dp83867.c
+++ b/drivers/net/phy/dp83867.c
@@ -144,7 +144,6 @@ static int dp83867_config_port_mirroring(struct phy_device *phydev)
return 0;
}
-#if defined(CONFIG_DM_ETH)
/**
* dp83867_data_init - Convenience function for setting PHY specific data
*
@@ -249,19 +248,6 @@ static int dp83867_of_init(struct phy_device *phydev)
return 0;
}
-#else
-static int dp83867_of_init(struct phy_device *phydev)
-{
- struct dp83867_private *dp83867 = phydev->priv;
-
- dp83867->rx_id_delay = DP83867_RGMIIDCTL_2_25_NS;
- dp83867->tx_id_delay = DP83867_RGMIIDCTL_2_75_NS;
- dp83867->fifo_depth = DEFAULT_FIFO_DEPTH;
- dp83867->io_impedance = -EINVAL;
-
- return 0;
-}
-#endif
static int dp83867_config(struct phy_device *phydev)
{
diff --git a/drivers/net/phy/dp83869.c b/drivers/net/phy/dp83869.c
index c9461185cfe..23dbf42b68c 100644
--- a/drivers/net/phy/dp83869.c
+++ b/drivers/net/phy/dp83869.c
@@ -157,7 +157,6 @@ static int dp83869_config_port_mirroring(struct phy_device *phydev)
return 0;
}
-#ifdef CONFIG_DM_ETH
static const int dp83869_internal_delay[] = {250, 500, 750, 1000, 1250, 1500,
1750, 2000, 2250, 2500, 2750, 3000,
3250, 3500, 3750, 4000};
@@ -269,19 +268,6 @@ static int dp83869_of_init(struct phy_device *phydev)
return 0;
}
-#else
-static int dp83869_of_init(struct phy_device *phydev)
-{
- struct dp83869_private *dp83869 = phydev->priv;
-
- dp83869->rx_int_delay = DP83869_RGMIIDCTL_2_25_NS;
- dp83869->tx_int_delay = DP83869_RGMIIDCTL_2_75_NS;
- dp83869->fifo_depth = DEFAULT_FIFO_DEPTH;
- dp83869->io_impedance = -EINVAL;
-
- return 0;
-}
-#endif /* CONFIG_OF_MDIO */
static int dp83869_configure_rgmii(struct phy_device *phydev,
struct dp83869_private *dp83869)
diff --git a/drivers/net/phy/et1011c.c b/drivers/net/phy/et1011c.c
index c243c5b72f8..7eff5ec7cac 100644
--- a/drivers/net/phy/et1011c.c
+++ b/drivers/net/phy/et1011c.c
@@ -60,7 +60,7 @@ static int et1011c_parse_status(struct phy_device *phydev)
mii_reg |
ET1011C_GMII_INTERFACE |
ET1011C_SYS_CLK_EN |
-#ifdef CONFIG_PHY_ET1011C_TX_CLK_FIX
+#ifdef CFG_PHY_ET1011C_TX_CLK_FIX
ET1011C_TX_CLK_EN |
#endif
ET1011C_TX_FIFO_DEPTH_16);
diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
index 212a861596f..1a25775eee6 100644
--- a/drivers/net/phy/marvell.c
+++ b/drivers/net/phy/marvell.c
@@ -104,7 +104,6 @@
#define MIIM_88E151x_MODE_SGMII 1
#define MIIM_88E151x_RESET_OFFS 15
-#if IS_ENABLED(CONFIG_DM_ETH)
static int marvell_read_page(struct phy_device *phydev)
{
return phy_read(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE);
@@ -179,12 +178,6 @@ static int marvell_of_reg_init(struct phy_device *phydev)
err:
return marvell_write_page(phydev, saved_page);
}
-#else
-static int marvell_of_reg_init(struct phy_device *phydev)
-{
- return 0;
-}
-#endif /* CONFIG_DM_ETH */
static int m88e1xxx_phy_extread(struct phy_device *phydev, int addr,
int devaddr, int regnum)
diff --git a/drivers/net/phy/micrel_ksz90x1.c b/drivers/net/phy/micrel_ksz90x1.c
index e5f578201f3..79ebdb5e82a 100644
--- a/drivers/net/phy/micrel_ksz90x1.c
+++ b/drivers/net/phy/micrel_ksz90x1.c
@@ -68,7 +68,6 @@ static int ksz90xx_startup(struct phy_device *phydev)
}
/* Common OF config bits for KSZ9021 and KSZ9031 */
-#ifdef CONFIG_DM_ETH
struct ksz90x1_reg_field {
const char *name;
const u8 size; /* Size of the bitfield, in bits */
@@ -211,23 +210,6 @@ static int ksz9031_center_flp_timing(struct phy_device *phydev)
return ret;
}
-#else /* !CONFIG_DM_ETH */
-static int ksz9021_of_config(struct phy_device *phydev)
-{
- return 0;
-}
-
-static int ksz9031_of_config(struct phy_device *phydev)
-{
- return 0;
-}
-
-static int ksz9031_center_flp_timing(struct phy_device *phydev)
-{
- return 0;
-}
-#endif
-
/*
* KSZ9021
*/
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index 92143cf2369..80230b907c1 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -689,9 +689,7 @@ struct phy_device *phy_device_create(struct mii_dev *bus, int addr,
dev->link = 0;
dev->interface = PHY_INTERFACE_MODE_NA;
-#ifdef CONFIG_DM_ETH
dev->node = ofnode_null();
-#endif
dev->autoneg = AUTONEG_ENABLE;
@@ -922,13 +920,8 @@ struct phy_device *phy_find_by_mask(struct mii_dev *bus, uint phy_mask)
return get_phy_device_by_mask(bus, phy_mask);
}
-#ifdef CONFIG_DM_ETH
void phy_connect_dev(struct phy_device *phydev, struct udevice *dev,
phy_interface_t interface)
-#else
-void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev,
- phy_interface_t interface)
-#endif
{
/* Soft Reset the PHY */
phy_reset(phydev);
@@ -1011,15 +1004,9 @@ static struct phy_device *phy_connect_fixed(struct mii_dev *bus,
}
#endif
-#ifdef CONFIG_DM_ETH
struct phy_device *phy_connect(struct mii_dev *bus, int addr,
struct udevice *dev,
phy_interface_t interface)
-#else
-struct phy_device *phy_connect(struct mii_dev *bus, int addr,
- struct eth_device *dev,
- phy_interface_t interface)
-#endif
{
struct phy_device *phydev = NULL;
uint mask = (addr >= 0) ? (1 << addr) : 0xffffffff;
diff --git a/drivers/net/qe/Kconfig b/drivers/net/qe/Kconfig
index dec88dea2a3..e795e913d42 100644
--- a/drivers/net/qe/Kconfig
+++ b/drivers/net/qe/Kconfig
@@ -4,6 +4,5 @@
config QE_UEC
bool "NXP QE UEC Ethernet controller"
- depends on DM_ETH
help
This driver supports the NXP QE UEC ethernet controller
diff --git a/drivers/net/qe/uec.h b/drivers/net/qe/uec.h
index 551d7061ccc..4510205da32 100644
--- a/drivers/net/qe/uec.h
+++ b/drivers/net/qe/uec.h
@@ -689,5 +689,4 @@ struct uec_priv {
int uec_initialize(struct bd_info *bis, struct uec_inf *uec_info);
int uec_eth_init(struct bd_info *bis, struct uec_inf *uecs, int num);
-int uec_standard_init(struct bd_info *bis);
#endif /* __UEC_H__ */
diff --git a/drivers/net/rtl8139.c b/drivers/net/rtl8139.c
index feeea930fbe..106bc1c7ae7 100644
--- a/drivers/net/rtl8139.c
+++ b/drivers/net/rtl8139.c
@@ -97,13 +97,8 @@
#define DEBUG_TX 0 /* set to 1 to enable debug code */
#define DEBUG_RX 0 /* set to 1 to enable debug code */
-#ifdef CONFIG_DM_ETH
#define bus_to_phys(devno, a) dm_pci_mem_to_phys((devno), (a))
#define phys_to_bus(devno, a) dm_pci_phys_to_mem((devno), (a))
-#else
-#define bus_to_phys(devno, a) pci_mem_to_phys((pci_dev_t)(devno), (a))
-#define phys_to_bus(devno, a) pci_phys_to_mem((pci_dev_t)(devno), (a))
-#endif
/* Symbolic offsets to registers. */
/* Ethernet hardware address. */
@@ -198,12 +193,7 @@
#define RTL_STS_RXSTATUSOK BIT(0)
struct rtl8139_priv {
-#ifndef CONFIG_DM_ETH
- struct eth_device dev;
- pci_dev_t devno;
-#else
struct udevice *devno;
-#endif
unsigned int rxstatus;
unsigned int cur_rx;
unsigned int cur_tx;
@@ -557,107 +547,6 @@ static struct pci_device_id supported[] = {
{ }
};
-#ifndef CONFIG_DM_ETH
-static int rtl8139_bcast_addr(struct eth_device *dev, const u8 *bcast_mac,
- int join)
-{
- return 0;
-}
-
-static int rtl8139_init(struct eth_device *dev, struct bd_info *bis)
-{
- struct rtl8139_priv *priv = container_of(dev, struct rtl8139_priv, dev);
-
- return rtl8139_init_common(priv);
-}
-
-static void rtl8139_stop(struct eth_device *dev)
-{
- struct rtl8139_priv *priv = container_of(dev, struct rtl8139_priv, dev);
-
- return rtl8139_stop_common(priv);
-}
-
-static int rtl8139_send(struct eth_device *dev, void *packet, int length)
-{
- struct rtl8139_priv *priv = container_of(dev, struct rtl8139_priv, dev);
-
- return rtl8139_send_common(priv, packet, length);
-}
-
-static int rtl8139_recv(struct eth_device *dev)
-{
- struct rtl8139_priv *priv = container_of(dev, struct rtl8139_priv, dev);
- unsigned char rxdata[RX_BUF_LEN];
- uchar *packet;
- int ret;
-
- ret = rtl8139_recv_common(priv, rxdata, &packet);
- if (ret) {
- net_process_received_packet(packet, ret);
- rtl8139_free_pkt_common(priv, ret);
- }
-
- return ret;
-}
-
-int rtl8139_initialize(struct bd_info *bis)
-{
- struct rtl8139_priv *priv;
- struct eth_device *dev;
- int card_number = 0;
- pci_dev_t devno;
- int idx = 0;
- u32 iobase;
-
- while (1) {
- /* Find RTL8139 */
- devno = pci_find_devices(supported, idx++);
- if (devno < 0)
- break;
-
- pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase);
- iobase &= ~0xf;
-
- debug("rtl8139: REALTEK RTL8139 @0x%x\n", iobase);
-
- priv = calloc(1, sizeof(*priv));
- if (!priv) {
- printf("Can not allocate memory of rtl8139\n");
- break;
- }
-
- priv->devno = devno;
- priv->ioaddr = (unsigned long)bus_to_phys(devno, iobase);
-
- dev = &priv->dev;
-
- rtl8139_name(dev->name, card_number);
-
- dev->iobase = priv->ioaddr; /* Non-DM compatibility */
- dev->init = rtl8139_init;
- dev->halt = rtl8139_stop;
- dev->send = rtl8139_send;
- dev->recv = rtl8139_recv;
- dev->mcast = rtl8139_bcast_addr;
-
- rtl8139_get_hwaddr(priv);
-
- /* Non-DM compatibility */
- memcpy(priv->dev.enetaddr, priv->enetaddr, 6);
-
- eth_register(dev);
-
- card_number++;
-
- pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x20);
-
- udelay(10 * 1000);
- }
-
- return card_number;
-}
-#else /* DM_ETH */
static int rtl8139_start(struct udevice *dev)
{
struct eth_pdata *plat = dev_get_plat(dev);
@@ -776,4 +665,3 @@ U_BOOT_DRIVER(eth_rtl8139) = {
};
U_BOOT_PCI_DEVICE(eth_rtl8139, supported);
-#endif
diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c
index da2cfb7f550..c9c07a5a8ff 100644
--- a/drivers/net/rtl8169.c
+++ b/drivers/net/rtl8169.c
@@ -47,9 +47,6 @@
#include <malloc.h>
#include <memalign.h>
#include <net.h>
-#ifndef CONFIG_DM_ETH
-#include <netdev.h>
-#endif
#include <asm/cache.h>
#include <asm/io.h>
#include <pci.h>
@@ -514,13 +511,8 @@ static void rtl_flush_buffer(void *buf, size_t size)
/**************************************************************************
RECV - Receive a frame
***************************************************************************/
-#ifdef CONFIG_DM_ETH
static int rtl_recv_common(struct udevice *dev, unsigned long dev_iobase,
uchar **packetp)
-#else
-static int rtl_recv_common(pci_dev_t dev, unsigned long dev_iobase,
- uchar **packetp)
-#endif
{
/* return true if there's an ethernet packet ready to read */
/* nic->packet should contain data on return */
@@ -551,22 +543,12 @@ static int rtl_recv_common(pci_dev_t dev, unsigned long dev_iobase,
else
tpc->RxDescArray[cur_rx].status =
cpu_to_le32(OWNbit + RX_BUF_SIZE);
-#ifdef CONFIG_DM_ETH
tpc->RxDescArray[cur_rx].buf_addr = cpu_to_le32(
dm_pci_mem_to_phys(dev,
(pci_addr_t)(unsigned long)
tpc->RxBufferRing[cur_rx]));
-#else
- tpc->RxDescArray[cur_rx].buf_addr = cpu_to_le32(
- pci_mem_to_phys(dev, (pci_addr_t)(unsigned long)
- tpc->RxBufferRing[cur_rx]));
-#endif
rtl_flush_rx_desc(&tpc->RxDescArray[cur_rx]);
-#ifdef CONFIG_DM_ETH
*packetp = rxdata;
-#else
- net_process_received_packet(rxdata, length);
-#endif
} else {
puts("Error Rx");
length = -EIO;
@@ -584,32 +566,19 @@ static int rtl_recv_common(pci_dev_t dev, unsigned long dev_iobase,
return (0); /* initially as this is called to flush the input */
}
-#ifdef CONFIG_DM_ETH
int rtl8169_eth_recv(struct udevice *dev, int flags, uchar **packetp)
{
struct rtl8169_private *priv = dev_get_priv(dev);
return rtl_recv_common(dev, priv->iobase, packetp);
}
-#else
-static int rtl_recv(struct eth_device *dev)
-{
- return rtl_recv_common((pci_dev_t)(unsigned long)dev->priv,
- dev->iobase, NULL);
-}
-#endif /* nCONFIG_DM_ETH */
#define HZ 1000
/**************************************************************************
SEND - Transmit a frame
***************************************************************************/
-#ifdef CONFIG_DM_ETH
static int rtl_send_common(struct udevice *dev, unsigned long dev_iobase,
void *packet, int length)
-#else
-static int rtl_send_common(pci_dev_t dev, unsigned long dev_iobase,
- void *packet, int length)
-#endif
{
/* send the packet to destination */
@@ -637,13 +606,8 @@ static int rtl_send_common(pci_dev_t dev, unsigned long dev_iobase,
rtl_flush_buffer(ptxb, ALIGN(len, RTL8169_ALIGN));
tpc->TxDescArray[entry].buf_Haddr = 0;
-#ifdef CONFIG_DM_ETH
tpc->TxDescArray[entry].buf_addr = cpu_to_le32(
dm_pci_mem_to_phys(dev, (pci_addr_t)(unsigned long)ptxb));
-#else
- tpc->TxDescArray[entry].buf_addr = cpu_to_le32(
- pci_mem_to_phys(dev, (pci_addr_t)(unsigned long)ptxb));
-#endif
if (entry != (NUM_TX_DESC - 1)) {
tpc->TxDescArray[entry].status =
cpu_to_le32((OWNbit | FSbit | LSbit) |
@@ -680,7 +644,6 @@ static int rtl_send_common(pci_dev_t dev, unsigned long dev_iobase,
return ret;
}
-#ifdef CONFIG_DM_ETH
int rtl8169_eth_send(struct udevice *dev, void *packet, int length)
{
struct rtl8169_private *priv = dev_get_priv(dev);
@@ -688,14 +651,6 @@ int rtl8169_eth_send(struct udevice *dev, void *packet, int length)
return rtl_send_common(dev, priv->iobase, packet, length);
}
-#else
-static int rtl_send(struct eth_device *dev, void *packet, int length)
-{
- return rtl_send_common((pci_dev_t)(unsigned long)dev->priv,
- dev->iobase, packet, length);
-}
-#endif
-
static void rtl8169_set_rx_mode(void)
{
u32 mc_filter[2]; /* Multicast hash filter */
@@ -719,11 +674,7 @@ static void rtl8169_set_rx_mode(void)
RTL_W32(MAR0 + 4, mc_filter[1]);
}
-#ifdef CONFIG_DM_ETH
static void rtl8169_hw_start(struct udevice *dev)
-#else
-static void rtl8169_hw_start(pci_dev_t dev)
-#endif
{
u32 i;
@@ -768,21 +719,11 @@ static void rtl8169_hw_start(pci_dev_t dev)
tpc->cur_rx = 0;
-#ifdef CONFIG_DM_ETH
RTL_W32(TxDescStartAddrLow, dm_pci_mem_to_phys(dev,
(pci_addr_t)(unsigned long)tpc->TxDescArray));
-#else
- RTL_W32(TxDescStartAddrLow, pci_mem_to_phys(dev,
- (pci_addr_t)(unsigned long)tpc->TxDescArray));
-#endif
RTL_W32(TxDescStartAddrHigh, (unsigned long)0);
-#ifdef CONFIG_DM_ETH
RTL_W32(RxDescStartAddrLow, dm_pci_mem_to_phys(
dev, (pci_addr_t)(unsigned long)tpc->RxDescArray));
-#else
- RTL_W32(RxDescStartAddrLow, pci_mem_to_phys(
- dev, (pci_addr_t)(unsigned long)tpc->RxDescArray));
-#endif
RTL_W32(RxDescStartAddrHigh, (unsigned long)0);
/* RTL-8169sc/8110sc or later version */
@@ -804,11 +745,7 @@ static void rtl8169_hw_start(pci_dev_t dev)
#endif
}
-#ifdef CONFIG_DM_ETH
static void rtl8169_init_ring(struct udevice *dev)
-#else
-static void rtl8169_init_ring(pci_dev_t dev)
-#endif
{
int i;
@@ -836,13 +773,8 @@ static void rtl8169_init_ring(pci_dev_t dev)
cpu_to_le32(OWNbit + RX_BUF_SIZE);
tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE];
-#ifdef CONFIG_DM_ETH
tpc->RxDescArray[i].buf_addr = cpu_to_le32(dm_pci_mem_to_phys(
dev, (pci_addr_t)(unsigned long)tpc->RxBufferRing[i]));
-#else
- tpc->RxDescArray[i].buf_addr = cpu_to_le32(pci_mem_to_phys(
- dev, (pci_addr_t)(unsigned long)tpc->RxBufferRing[i]));
-#endif
rtl_flush_rx_desc(&tpc->RxDescArray[i]);
}
@@ -851,13 +783,8 @@ static void rtl8169_init_ring(pci_dev_t dev)
#endif
}
-#ifdef CONFIG_DM_ETH
static void rtl8169_common_start(struct udevice *dev, unsigned char *enetaddr,
unsigned long dev_iobase)
-#else
-static void rtl8169_common_start(pci_dev_t dev, unsigned char *enetaddr,
- unsigned long dev_iobase)
-#endif
{
int i;
@@ -887,7 +814,6 @@ static void rtl8169_common_start(pci_dev_t dev, unsigned char *enetaddr,
#endif
}
-#ifdef CONFIG_DM_ETH
static int rtl8169_eth_start(struct udevice *dev)
{
struct eth_pdata *plat = dev_get_plat(dev);
@@ -897,18 +823,6 @@ static int rtl8169_eth_start(struct udevice *dev)
return 0;
}
-#else
-/**************************************************************************
-RESET - Finish setting up the ethernet interface
-***************************************************************************/
-static int rtl_reset(struct eth_device *dev, struct bd_info *bis)
-{
- rtl8169_common_start((pci_dev_t)(unsigned long)dev->priv,
- dev->enetaddr, dev->iobase);
-
- return 0;
-}
-#endif /* nCONFIG_DM_ETH */
static void rtl_halt_common(unsigned long dev_iobase)
{
@@ -933,24 +847,13 @@ static void rtl_halt_common(unsigned long dev_iobase)
}
}
-#ifdef CONFIG_DM_ETH
void rtl8169_eth_stop(struct udevice *dev)
{
struct rtl8169_private *priv = dev_get_priv(dev);
rtl_halt_common(priv->iobase);
}
-#else
-/**************************************************************************
-HALT - Turn off ethernet interface
-***************************************************************************/
-static void rtl_halt(struct eth_device *dev)
-{
- rtl_halt_common(dev->iobase);
-}
-#endif
-#ifdef CONFIG_DM_ETH
static int rtl8169_write_hwaddr(struct udevice *dev)
{
struct eth_pdata *plat = dev_get_plat(dev);
@@ -965,7 +868,6 @@ static int rtl8169_write_hwaddr(struct udevice *dev)
return 0;
}
-#endif
/**************************************************************************
INIT - Look for an adapter, this routine's visible to the outside
@@ -1118,73 +1020,6 @@ static int rtl_init(unsigned long dev_ioaddr, const char *name,
return 0;
}
-#ifndef CONFIG_DM_ETH
-int rtl8169_initialize(struct bd_info *bis)
-{
- pci_dev_t devno;
- int card_number = 0;
- struct eth_device *dev;
- u32 iobase;
- int idx=0;
-
- while(1){
- unsigned int region;
- u16 device;
- int err;
-
- /* Find RTL8169 */
- if ((devno = pci_find_devices(supported, idx++)) < 0)
- break;
-
- pci_read_config_word(devno, PCI_DEVICE_ID, &device);
- switch (device) {
- case 0x8168:
- region = 2;
- break;
-
- default:
- region = 1;
- break;
- }
-
- pci_read_config_dword(devno, PCI_BASE_ADDRESS_0 + (region * 4), &iobase);
- iobase &= ~0xf;
-
- debug ("rtl8169: REALTEK RTL8169 @0x%x\n", iobase);
-
- dev = (struct eth_device *)malloc(sizeof *dev);
- if (!dev) {
- printf("Can not allocate memory of rtl8169\n");
- break;
- }
-
- memset(dev, 0, sizeof(*dev));
- sprintf (dev->name, "RTL8169#%d", card_number);
-
- dev->priv = (void *)(unsigned long)devno;
- dev->iobase = (int)pci_mem_to_phys(devno, iobase);
-
- dev->init = rtl_reset;
- dev->halt = rtl_halt;
- dev->send = rtl_send;
- dev->recv = rtl_recv;
-
- err = rtl_init(dev->iobase, dev->name, dev->enetaddr);
- if (err < 0) {
- printf(pr_fmt("failed to initialize card: %d\n"), err);
- free(dev);
- continue;
- }
-
- eth_register (dev);
-
- card_number++;
- }
- return card_number;
-}
-#endif
-
-#ifdef CONFIG_DM_ETH
static int rtl8169_eth_probe(struct udevice *dev)
{
struct pci_child_plat *pplat = dev_get_parent_plat(dev);
@@ -1253,4 +1088,3 @@ U_BOOT_DRIVER(eth_rtl8169) = {
};
U_BOOT_PCI_DEVICE(eth_rtl8169, supported);
-#endif
diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
index 1de3ff8add2..8f162ca58fb 100644
--- a/drivers/net/sh_eth.c
+++ b/drivers/net/sh_eth.c
@@ -23,35 +23,33 @@
#include <asm/global_data.h>
#include <asm/io.h>
-#ifdef CONFIG_DM_ETH
#include <clk.h>
#include <dm.h>
#include <linux/mii.h>
#include <asm/gpio.h>
-#endif
#include "sh_eth.h"
-#ifndef CONFIG_SH_ETHER_USE_PORT
-# error "Please define CONFIG_SH_ETHER_USE_PORT"
+#ifndef CFG_SH_ETHER_USE_PORT
+# error "Please define CFG_SH_ETHER_USE_PORT"
#endif
-#ifndef CONFIG_SH_ETHER_PHY_ADDR
-# error "Please define CONFIG_SH_ETHER_PHY_ADDR"
+#ifndef CFG_SH_ETHER_PHY_ADDR
+# error "Please define CFG_SH_ETHER_PHY_ADDR"
#endif
-#if defined(CONFIG_SH_ETHER_CACHE_WRITEBACK) && \
+#if defined(CFG_SH_ETHER_CACHE_WRITEBACK) && \
!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
#define flush_cache_wback(addr, len) \
flush_dcache_range((unsigned long)addr, \
- (unsigned long)(addr + ALIGN(len, CONFIG_SH_ETHER_ALIGNE_SIZE)))
+ (unsigned long)(addr + ALIGN(len, CFG_SH_ETHER_ALIGNE_SIZE)))
#else
#define flush_cache_wback(...)
#endif
-#if defined(CONFIG_SH_ETHER_CACHE_INVALIDATE) && defined(CONFIG_ARM)
+#if defined(CFG_SH_ETHER_CACHE_INVALIDATE) && defined(CONFIG_ARM)
#define invalidate_cache(addr, len) \
{ \
- unsigned long line_size = CONFIG_SH_ETHER_ALIGNE_SIZE; \
+ unsigned long line_size = CFG_SH_ETHER_ALIGNE_SIZE; \
unsigned long start, end; \
\
start = (unsigned long)addr; \
@@ -526,163 +524,6 @@ static int sh_eth_start_common(struct sh_eth_dev *eth)
return 0;
}
-#ifndef CONFIG_DM_ETH
-static int sh_eth_phy_config_legacy(struct sh_eth_dev *eth)
-{
- int ret = 0;
- struct sh_eth_info *port_info = &eth->port_info[eth->port];
- struct eth_device *dev = port_info->dev;
- struct phy_device *phydev;
-
- phydev = phy_connect(
- miiphy_get_dev_by_name(dev->name),
- port_info->phy_addr, dev, CONFIG_SH_ETHER_PHY_MODE);
- port_info->phydev = phydev;
- phy_config(phydev);
-
- return ret;
-}
-
-static int sh_eth_send_legacy(struct eth_device *dev, void *packet, int len)
-{
- struct sh_eth_dev *eth = dev->priv;
-
- return sh_eth_send_common(eth, packet, len);
-}
-
-static int sh_eth_recv_common(struct sh_eth_dev *eth)
-{
- int len = 0;
- struct sh_eth_info *port_info = &eth->port_info[eth->port];
- uchar *packet = (uchar *)ADDR_TO_P2(port_info->rx_desc_cur->rd2);
-
- len = sh_eth_recv_start(eth);
- if (len > 0) {
- invalidate_cache(packet, len);
- net_process_received_packet(packet, len);
- sh_eth_recv_finish(eth);
- } else
- len = 0;
-
- /* Restart the receiver if disabled */
- if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R))
- sh_eth_write(port_info, EDRRR_R, EDRRR);
-
- return len;
-}
-
-static int sh_eth_recv_legacy(struct eth_device *dev)
-{
- struct sh_eth_dev *eth = dev->priv;
-
- return sh_eth_recv_common(eth);
-}
-
-static int sh_eth_init_legacy(struct eth_device *dev, struct bd_info *bd)
-{
- struct sh_eth_dev *eth = dev->priv;
- int ret;
-
- ret = sh_eth_init_common(eth, dev->enetaddr);
- if (ret)
- return ret;
-
- ret = sh_eth_phy_config_legacy(eth);
- if (ret) {
- printf(SHETHER_NAME ": phy config timeout\n");
- goto err_start;
- }
-
- ret = sh_eth_start_common(eth);
- if (ret)
- goto err_start;
-
- return 0;
-
-err_start:
- sh_eth_tx_desc_free(eth);
- sh_eth_rx_desc_free(eth);
- return ret;
-}
-
-void sh_eth_halt_legacy(struct eth_device *dev)
-{
- struct sh_eth_dev *eth = dev->priv;
-
- sh_eth_stop(eth);
-}
-
-int sh_eth_initialize(struct bd_info *bd)
-{
- int ret = 0;
- struct sh_eth_dev *eth = NULL;
- struct eth_device *dev = NULL;
- struct mii_dev *mdiodev;
-
- eth = (struct sh_eth_dev *)malloc(sizeof(struct sh_eth_dev));
- if (!eth) {
- printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
- ret = -ENOMEM;
- goto err;
- }
-
- dev = (struct eth_device *)malloc(sizeof(struct eth_device));
- if (!dev) {
- printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
- ret = -ENOMEM;
- goto err;
- }
- memset(dev, 0, sizeof(struct eth_device));
- memset(eth, 0, sizeof(struct sh_eth_dev));
-
- eth->port = CONFIG_SH_ETHER_USE_PORT;
- eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR;
- eth->port_info[eth->port].iobase =
- (void __iomem *)(BASE_IO_ADDR + 0x800 * eth->port);
-
- dev->priv = (void *)eth;
- dev->iobase = 0;
- dev->init = sh_eth_init_legacy;
- dev->halt = sh_eth_halt_legacy;
- dev->send = sh_eth_send_legacy;
- dev->recv = sh_eth_recv_legacy;
- eth->port_info[eth->port].dev = dev;
-
- strcpy(dev->name, SHETHER_NAME);
-
- /* Register Device to EtherNet subsystem */
- eth_register(dev);
-
- bb_miiphy_buses[0].priv = eth;
- mdiodev = mdio_alloc();
- if (!mdiodev)
- return -ENOMEM;
- strlcpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
- mdiodev->read = bb_miiphy_read;
- mdiodev->write = bb_miiphy_write;
-
- ret = mdio_register(mdiodev);
- if (ret < 0)
- return ret;
-
- if (!eth_env_get_enetaddr("ethaddr", dev->enetaddr))
- puts("Please set MAC address\n");
-
- return ret;
-
-err:
- if (dev)
- free(dev);
-
- if (eth)
- free(eth);
-
- printf(SHETHER_NAME ": Failed\n");
- return ret;
-}
-
-#else /* CONFIG_DM_ETH */
-
struct sh_ether_priv {
struct sh_eth_dev shdev;
@@ -852,8 +693,8 @@ static int sh_ether_probe(struct udevice *udev)
priv->bus = miiphy_get_dev_by_name(udev->name);
- eth->port = CONFIG_SH_ETHER_USE_PORT;
- eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR;
+ eth->port = CFG_SH_ETHER_USE_PORT;
+ eth->port_info[eth->port].phy_addr = CFG_SH_ETHER_PHY_ADDR;
eth->port_info[eth->port].iobase =
(void __iomem *)(uintptr_t)(BASE_IO_ADDR + 0x800 * eth->port);
@@ -955,7 +796,6 @@ U_BOOT_DRIVER(eth_sh_ether) = {
.plat_auto = sizeof(struct eth_pdata),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
-#endif
/******* for bb_miiphy *******/
static int sh_eth_bb_init(struct bb_miiphy_bus *bus)
diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h
index 520f7f73257..1c07610e1ac 100644
--- a/drivers/net/sh_eth.h
+++ b/drivers/net/sh_eth.h
@@ -29,8 +29,8 @@
#endif /* defined(CONFIG_SH) */
/* base padding size is 16 */
-#ifndef CONFIG_SH_ETHER_ALIGNE_SIZE
-#define CONFIG_SH_ETHER_ALIGNE_SIZE 16
+#ifndef CFG_SH_ETHER_ALIGNE_SIZE
+#define CFG_SH_ETHER_ALIGNE_SIZE 16
#endif
/* Number of supported ports */
@@ -47,7 +47,7 @@
/* The size of the tx descriptor is determined by how much padding is used.
4, 20, or 52 bytes of padding can be used */
-#define TX_DESC_PADDING (CONFIG_SH_ETHER_ALIGNE_SIZE - 12)
+#define TX_DESC_PADDING (CFG_SH_ETHER_ALIGNE_SIZE - 12)
/* Tx descriptor. We always use 3 bytes of padding */
struct tx_desc_s {
@@ -62,9 +62,9 @@ struct tx_desc_s {
/* The size of the rx descriptor is determined by how much padding is used.
4, 20, or 52 bytes of padding can be used */
-#define RX_DESC_PADDING (CONFIG_SH_ETHER_ALIGNE_SIZE - 12)
+#define RX_DESC_PADDING (CFG_SH_ETHER_ALIGNE_SIZE - 12)
/* aligned cache line size */
-#define RX_BUF_ALIGNE_SIZE (CONFIG_SH_ETHER_ALIGNE_SIZE > 32 ? 64 : 32)
+#define RX_BUF_ALIGNE_SIZE (CFG_SH_ETHER_ALIGNE_SIZE > 32 ? 64 : 32)
/* Rx descriptor. We always use 4 bytes of padding */
struct rx_desc_s {
@@ -388,11 +388,11 @@ enum DMAC_M_BIT {
#endif
};
-#if CONFIG_SH_ETHER_ALIGNE_SIZE == 64
+#if CFG_SH_ETHER_ALIGNE_SIZE == 64
# define EMDR_DESC EDMR_DL1
-#elif CONFIG_SH_ETHER_ALIGNE_SIZE == 32
+#elif CFG_SH_ETHER_ALIGNE_SIZE == 32
# define EMDR_DESC EDMR_DL0
-#elif CONFIG_SH_ETHER_ALIGNE_SIZE == 16 /* Default */
+#elif CFG_SH_ETHER_ALIGNE_SIZE == 16 /* Default */
# define EMDR_DESC 0
#endif
diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c
index 5d9a73f23d7..5c5ad8b84a9 100644
--- a/drivers/net/smc911x.c
+++ b/drivers/net/smc911x.c
@@ -22,9 +22,6 @@ struct chip_id {
};
struct smc911x_priv {
-#ifndef CONFIG_DM_ETH
- struct eth_device dev;
-#endif
phys_addr_t iobase;
const struct chip_id *chipid;
unsigned char enetaddr[6];
@@ -382,149 +379,6 @@ static int smc911x_recv_common(struct smc911x_priv *priv, u32 *data)
return pktlen;
}
-#ifndef CONFIG_DM_ETH
-
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
-/* wrapper for smc911x_eth_phy_read */
-static int smc911x_miiphy_read(struct mii_dev *bus, int phy, int devad,
- int reg)
-{
- struct eth_device *dev = eth_get_dev_by_name(bus->name);
- struct smc911x_priv *priv = container_of(dev, struct smc911x_priv, dev);
- u16 val = 0;
- int ret;
-
- if (!dev || !priv)
- return -ENODEV;
-
- ret = smc911x_eth_phy_read(priv, phy, reg, &val);
- if (ret < 0)
- return ret;
-
- return val;
-}
-
-/* wrapper for smc911x_eth_phy_write */
-static int smc911x_miiphy_write(struct mii_dev *bus, int phy, int devad,
- int reg, u16 val)
-{
- struct eth_device *dev = eth_get_dev_by_name(bus->name);
- struct smc911x_priv *priv = container_of(dev, struct smc911x_priv, dev);
-
- if (!dev || !priv)
- return -ENODEV;
-
- return smc911x_eth_phy_write(priv, phy, reg, val);
-}
-
-static int smc911x_initialize_mii(struct smc911x_priv *priv)
-{
- struct mii_dev *mdiodev = mdio_alloc();
- int ret;
-
- if (!mdiodev)
- return -ENOMEM;
-
- strlcpy(mdiodev->name, priv->dev.name, MDIO_NAME_LEN);
- mdiodev->read = smc911x_miiphy_read;
- mdiodev->write = smc911x_miiphy_write;
-
- ret = mdio_register(mdiodev);
- if (ret < 0) {
- mdio_free(mdiodev);
- return ret;
- }
-
- return 0;
-}
-#else
-static int smc911x_initialize_mii(struct smc911x_priv *priv)
-{
- return 0;
-}
-#endif
-
-static int smc911x_init(struct eth_device *dev, struct bd_info *bd)
-{
- struct smc911x_priv *priv = container_of(dev, struct smc911x_priv, dev);
-
- return smc911x_init_common(priv);
-}
-
-static void smc911x_halt(struct eth_device *dev)
-{
- struct smc911x_priv *priv = container_of(dev, struct smc911x_priv, dev);
-
- smc911x_halt_common(priv);
-}
-
-static int smc911x_send(struct eth_device *dev, void *packet, int length)
-{
- struct smc911x_priv *priv = container_of(dev, struct smc911x_priv, dev);
-
- return smc911x_send_common(priv, packet, length);
-}
-
-static int smc911x_recv(struct eth_device *dev)
-{
- struct smc911x_priv *priv = container_of(dev, struct smc911x_priv, dev);
- u32 *data = (u32 *)net_rx_packets[0];
- int ret;
-
- ret = smc911x_recv_common(priv, data);
- if (ret)
- net_process_received_packet(net_rx_packets[0], ret);
-
- return ret;
-}
-
-int smc911x_initialize(u8 dev_num, phys_addr_t base_addr)
-{
- struct smc911x_priv *priv;
- int ret;
-
- priv = calloc(1, sizeof(*priv));
- if (!priv)
- return -ENOMEM;
-
- priv->iobase = base_addr;
- priv->dev.iobase = base_addr;
-
- priv->use_32_bit_io = CONFIG_IS_ENABLED(SMC911X_32_BIT);
-
- /* Try to detect chip. Will fail if not present. */
- ret = smc911x_detect_chip(priv);
- if (ret) {
- ret = 0; /* Card not detected is not an error */
- goto err_detect;
- }
-
- if (smc911x_read_mac_address(priv))
- memcpy(priv->dev.enetaddr, priv->enetaddr, 6);
-
- priv->dev.init = smc911x_init;
- priv->dev.halt = smc911x_halt;
- priv->dev.send = smc911x_send;
- priv->dev.recv = smc911x_recv;
- sprintf(priv->dev.name, "%s-%hu", DRIVERNAME, dev_num);
-
- eth_register(&priv->dev);
-
- ret = smc911x_initialize_mii(priv);
- if (ret)
- goto err_mii;
-
- return 1;
-
-err_mii:
- eth_unregister(&priv->dev);
-err_detect:
- free(priv);
- return ret;
-}
-
-#else /* ifdef CONFIG_DM_ETH */
-
static int smc911x_start(struct udevice *dev)
{
struct eth_pdata *plat = dev_get_plat(dev);
@@ -642,4 +496,3 @@ U_BOOT_DRIVER(smc911x) = {
.plat_auto = sizeof(struct eth_pdata),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
-#endif
diff --git a/drivers/net/sunxi_emac.c b/drivers/net/sunxi_emac.c
index 8625e49dae4..ad9e1abd161 100644
--- a/drivers/net/sunxi_emac.c
+++ b/drivers/net/sunxi_emac.c
@@ -164,9 +164,7 @@ struct emac_eth_dev {
struct mii_dev *bus;
struct phy_device *phydev;
int link_printed;
-#ifdef CONFIG_DM_ETH
uchar rx_buf[EMAC_RX_BUFSIZE];
-#endif
};
struct emac_rxhdr {
diff --git a/drivers/net/ti/Kconfig b/drivers/net/ti/Kconfig
index 59c96d862dd..e13dbc94018 100644
--- a/drivers/net/ti/Kconfig
+++ b/drivers/net/ti/Kconfig
@@ -25,6 +25,19 @@ config DRIVER_TI_KEYSTONE_NET
help
This driver supports the TI Keystone 2 Ethernet subsystem
+choice
+ prompt "TI Keystone 2 Ethernet NETCP IP revision"
+ depends on DRIVER_TI_KEYSTONE_NET
+ default KSNET_NETCP_V1_5
+
+config KSNET_NETCP_V1_0
+ bool "NETCP version 1.0"
+
+config KSNET_NETCP_V1_5
+ bool "NETCP version 1.5"
+
+endchoice
+
config TI_AM65_CPSW_NUSS
bool "TI K3 AM65x MCU CPSW Nuss Ethernet controller driver"
depends on ARCH_K3
diff --git a/drivers/net/ti/cpsw.c b/drivers/net/ti/cpsw.c
index 41cba7930d1..3a8cc9c52a5 100644
--- a/drivers/net/ti/cpsw.c
+++ b/drivers/net/ti/cpsw.c
@@ -79,10 +79,6 @@ struct cpsw_slave_regs {
u32 tx_pri_map;
#ifdef CONFIG_AM33XX
u32 gap_thresh;
-#elif defined(CONFIG_TI814X)
- u32 ts_ctl;
- u32 ts_seq_ltype;
- u32 ts_vlan;
#endif
u32 sa_lo;
u32 sa_hi;
@@ -200,11 +196,7 @@ struct cpdma_chan {
((priv)->data)->slaves; slave++)
struct cpsw_priv {
-#ifdef CONFIG_DM_ETH
struct udevice *dev;
-#else
- struct eth_device *dev;
-#endif
struct cpsw_platform_data *data;
int host_port;
@@ -455,15 +447,10 @@ static inline void setbit_and_wait_for_clear32(void *addr)
static void cpsw_set_slave_mac(struct cpsw_slave *slave,
struct cpsw_priv *priv)
{
-#ifdef CONFIG_DM_ETH
struct eth_pdata *pdata = dev_get_plat(priv->dev);
writel(mac_hi(pdata->enetaddr), &slave->regs->sa_hi);
writel(mac_lo(pdata->enetaddr), &slave->regs->sa_lo);
-#else
- __raw_writel(mac_hi(priv->dev->enetaddr), &slave->regs->sa_hi);
- __raw_writel(mac_lo(priv->dev->enetaddr), &slave->regs->sa_lo);
-#endif
}
static int cpsw_slave_update_link(struct cpsw_slave *slave,
@@ -856,21 +843,13 @@ static int cpsw_phy_init(struct cpsw_priv *priv, struct cpsw_slave *slave)
ret = phy_set_supported(phydev, slave->data->max_speed);
if (ret)
return ret;
-#if CONFIG_IS_ENABLED(DM_ETH)
dev_dbg(priv->dev, "Port %u speed forced to %uMbit\n",
slave->slave_num + 1, slave->data->max_speed);
-#else
- log_debug("%s: Port %u speed forced to %uMbit\n",
- priv->dev->name, slave->slave_num + 1,
- slave->data->max_speed);
-#endif
}
phydev->advertising = phydev->supported;
-#ifdef CONFIG_DM_ETH
if (ofnode_valid(slave->data->phy_of_handle))
phydev->node = slave->data->phy_of_handle;
-#endif
priv->phydev = phydev;
phy_config(phydev);
@@ -935,84 +914,6 @@ int _cpsw_register(struct cpsw_priv *priv)
return 0;
}
-#ifndef CONFIG_DM_ETH
-static int cpsw_init(struct eth_device *dev, struct bd_info *bis)
-{
- struct cpsw_priv *priv = dev->priv;
-
- return _cpsw_init(priv, dev->enetaddr);
-}
-
-static void cpsw_halt(struct eth_device *dev)
-{
- struct cpsw_priv *priv = dev->priv;
-
- return _cpsw_halt(priv);
-}
-
-static int cpsw_send(struct eth_device *dev, void *packet, int length)
-{
- struct cpsw_priv *priv = dev->priv;
-
- return _cpsw_send(priv, packet, length);
-}
-
-static int cpsw_recv(struct eth_device *dev)
-{
- struct cpsw_priv *priv = dev->priv;
- uchar *pkt = NULL;
- int len;
-
- len = _cpsw_recv(priv, &pkt);
-
- if (len > 0) {
- net_process_received_packet(pkt, len);
- cpdma_submit(priv, &priv->rx_chan, pkt, PKTSIZE);
- }
-
- return len;
-}
-
-int cpsw_register(struct cpsw_platform_data *data)
-{
- struct cpsw_priv *priv;
- struct eth_device *dev;
- int ret;
-
- dev = calloc(sizeof(*dev), 1);
- if (!dev)
- return -ENOMEM;
-
- priv = calloc(sizeof(*priv), 1);
- if (!priv) {
- free(dev);
- return -ENOMEM;
- }
-
- priv->dev = dev;
- priv->data = data;
-
- strcpy(dev->name, "cpsw");
- dev->iobase = 0;
- dev->init = cpsw_init;
- dev->halt = cpsw_halt;
- dev->send = cpsw_send;
- dev->recv = cpsw_recv;
- dev->priv = priv;
-
- eth_register(dev);
-
- ret = _cpsw_register(priv);
- if (ret < 0) {
- eth_unregister(dev);
- free(dev);
- free(priv);
- return ret;
- }
-
- return 1;
-}
-#else
static int cpsw_eth_start(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_plat(dev);
@@ -1380,4 +1281,3 @@ U_BOOT_DRIVER(eth_cpsw) = {
.priv_auto = sizeof(struct cpsw_priv),
.flags = DM_FLAG_ALLOC_PRIV_DMA | DM_FLAG_PRE_RELOC,
};
-#endif /* CONFIG_DM_ETH */
diff --git a/drivers/net/ti/keystone_net.c b/drivers/net/ti/keystone_net.c
index 1bdbd599d7b..89b04b6fbda 100644
--- a/drivers/net/ti/keystone_net.c
+++ b/drivers/net/ti/keystone_net.c
@@ -370,14 +370,14 @@ struct ks2_serdes ks2_serdes_sgmii_156p25mhz = {
#ifndef CONFIG_SOC_K2G
static void keystone2_net_serdes_setup(void)
{
- ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII_BASE,
+ ks2_serdes_init(CFG_KSNET_SERDES_SGMII_BASE,
&ks2_serdes_sgmii_156p25mhz,
- CONFIG_KSNET_SERDES_LANES_PER_SGMII);
+ CFG_KSNET_SERDES_LANES_PER_SGMII);
#if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
- ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII2_BASE,
+ ks2_serdes_init(CFG_KSNET_SERDES_SGMII2_BASE,
&ks2_serdes_sgmii_156p25mhz,
- CONFIG_KSNET_SERDES_LANES_PER_SGMII);
+ CFG_KSNET_SERDES_LANES_PER_SGMII);
#endif
/* wait till setup */
@@ -592,10 +592,8 @@ static int ks2_eth_probe(struct udevice *dev)
if (priv->has_mdio) {
priv->phydev = phy_connect(priv->mdio_bus, priv->phy_addr,
dev, priv->phy_if);
-#ifdef CONFIG_DM_ETH
- if (ofnode_valid(priv->phy_ofnode))
- priv->phydev->node = priv->phy_ofnode;
-#endif
+ if (ofnode_valid(priv->phy_ofnode))
+ priv->phydev->node = priv->phy_ofnode;
phy_config(priv->phydev);
}
diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index 8b6f034ea16..6e903597595 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -22,34 +22,6 @@
#include <asm/processor.h>
#include <asm/io.h>
-#ifndef CONFIG_DM_ETH
-/* Default initializations for TSEC controllers. */
-
-static struct tsec_info_struct tsec_info[] = {
-#ifdef CONFIG_TSEC1
- STD_TSEC_INFO(1), /* TSEC1 */
-#endif
-#ifdef CONFIG_TSEC2
- STD_TSEC_INFO(2), /* TSEC2 */
-#endif
-#ifdef CONFIG_MPC85XX_FEC
- {
- .regs = TSEC_GET_REGS(2, 0x2000),
- .devname = CONFIG_MPC85XX_FEC_NAME,
- .phyaddr = FEC_PHY_ADDR,
- .flags = FEC_FLAGS,
- .mii_devname = DEFAULT_MII_NAME
- }, /* FEC */
-#endif
-#ifdef CONFIG_TSEC3
- STD_TSEC_INFO(3), /* TSEC3 */
-#endif
-#ifdef CONFIG_TSEC4
- STD_TSEC_INFO(4), /* TSEC4 */
-#endif
-};
-#endif /* CONFIG_DM_ETH */
-
#define TBIANA_SETTINGS ( \
TBIANA_ASYMMETRIC_PAUSE \
| TBIANA_SYMMETRIC_PAUSE \
@@ -57,14 +29,14 @@ static struct tsec_info_struct tsec_info[] = {
)
/* By default force the TBI PHY into 1000Mbps full duplex when in SGMII mode */
-#ifndef CONFIG_TSEC_TBICR_SETTINGS
-#define CONFIG_TSEC_TBICR_SETTINGS ( \
+#ifndef CFG_TSEC_TBICR_SETTINGS
+#define CFG_TSEC_TBICR_SETTINGS ( \
TBICR_PHY_RESET \
| TBICR_ANEG_ENABLE \
| TBICR_FULL_DUPLEX \
| TBICR_SPEED1_SET \
)
-#endif /* CONFIG_TSEC_TBICR_SETTINGS */
+#endif /* CFG_TSEC_TBICR_SETTINGS */
/* Configure the TBI for SGMII operation */
static void tsec_configure_serdes(struct tsec_private *priv)
@@ -78,7 +50,7 @@ static void tsec_configure_serdes(struct tsec_private *priv)
tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
0, TBI_TBICON, TBICON_CLK_SELECT);
tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
- 0, TBI_CR, CONFIG_TSEC_TBICR_SETTINGS);
+ 0, TBI_CR, CFG_TSEC_TBICR_SETTINGS);
}
/* the 'way' for ethernet-CRC-32. Spliced in from Linux lib/crc32.c
@@ -124,23 +96,14 @@ static u32 ether_crc(size_t len, unsigned char const *p)
* for PowerPC (tm) is usually the case) in the register holds
* the entry.
*/
-#ifndef CONFIG_DM_ETH
-static int tsec_mcast_addr(struct eth_device *dev, const u8 *mcast_mac,
- int join)
-#else
static int tsec_mcast_addr(struct udevice *dev, const u8 *mcast_mac, int join)
-#endif
{
struct tsec_private *priv;
struct tsec __iomem *regs;
u32 result, value;
u8 whichbit, whichreg;
-#ifndef CONFIG_DM_ETH
- priv = (struct tsec_private *)dev->priv;
-#else
priv = dev_get_priv(dev);
-#endif
regs = priv->regs;
result = ether_crc(MAC_ADDR_LEN, mcast_mac);
whichbit = (result >> 24) & 0x1f; /* the 5 LSB = which bit to set */
@@ -156,7 +119,7 @@ static int tsec_mcast_addr(struct udevice *dev, const u8 *mcast_mac, int join)
return 0;
}
-static int __maybe_unused tsec_set_promisc(struct udevice *dev, bool enable)
+static int tsec_set_promisc(struct udevice *dev, bool enable)
{
struct tsec_private *priv = dev_get_priv(dev);
struct tsec __iomem *regs = priv->regs;
@@ -271,11 +234,7 @@ static void adjust_link(struct tsec_private *priv, struct phy_device *phydev)
* do the same. Presumably, this would be zero if there were no
* errors
*/
-#ifndef CONFIG_DM_ETH
-static int tsec_send(struct eth_device *dev, void *packet, int length)
-#else
static int tsec_send(struct udevice *dev, void *packet, int length)
-#endif
{
struct tsec_private *priv;
struct tsec __iomem *regs;
@@ -283,11 +242,7 @@ static int tsec_send(struct udevice *dev, void *packet, int length)
u16 status;
int i;
-#ifndef CONFIG_DM_ETH
- priv = (struct tsec_private *)dev->priv;
-#else
priv = dev_get_priv(dev);
-#endif
regs = priv->regs;
/* Find an empty buffer descriptor */
for (i = 0;
@@ -324,42 +279,6 @@ static int tsec_send(struct udevice *dev, void *packet, int length)
return result;
}
-#ifndef CONFIG_DM_ETH
-static int tsec_recv(struct eth_device *dev)
-{
- struct tsec_private *priv = (struct tsec_private *)dev->priv;
- struct tsec __iomem *regs = priv->regs;
-
- while (!(in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY)) {
- int length = in_be16(&priv->rxbd[priv->rx_idx].length);
- u16 status = in_be16(&priv->rxbd[priv->rx_idx].status);
- uchar *packet = net_rx_packets[priv->rx_idx];
-
- /* Send the packet up if there were no errors */
- if (!(status & RXBD_STATS))
- net_process_received_packet(packet, length - 4);
- else
- printf("Got error %x\n", (status & RXBD_STATS));
-
- out_be16(&priv->rxbd[priv->rx_idx].length, 0);
-
- status = RXBD_EMPTY;
- /* Set the wrap bit if this is the last element in the list */
- if ((priv->rx_idx + 1) == PKTBUFSRX)
- status |= RXBD_WRAP;
- out_be16(&priv->rxbd[priv->rx_idx].status, status);
-
- priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX;
- }
-
- if (in_be32(&regs->ievent) & IEVENT_BSY) {
- out_be32(&regs->ievent, IEVENT_BSY);
- out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
- }
-
- return -1;
-}
-#else
static int tsec_recv(struct udevice *dev, int flags, uchar **packetp)
{
struct tsec_private *priv = (struct tsec_private *)dev_get_priv(dev);
@@ -406,22 +325,12 @@ static int tsec_free_pkt(struct udevice *dev, uchar *packet, int length)
return 0;
}
-#endif
-/* Stop the interface */
-#ifndef CONFIG_DM_ETH
-static void tsec_halt(struct eth_device *dev)
-#else
static void tsec_halt(struct udevice *dev)
-#endif
{
struct tsec_private *priv;
struct tsec __iomem *regs;
-#ifndef CONFIG_DM_ETH
- priv = (struct tsec_private *)dev->priv;
-#else
priv = dev_get_priv(dev);
-#endif
regs = priv->regs;
clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
@@ -583,27 +492,15 @@ static void startup_tsec(struct tsec_private *priv)
* that it returns success if the link is up, failure otherwise.
* This allows U-Boot to find the first active controller.
*/
-#ifndef CONFIG_DM_ETH
-static int tsec_init(struct eth_device *dev, struct bd_info *bd)
-#else
static int tsec_init(struct udevice *dev)
-#endif
{
struct tsec_private *priv;
struct tsec __iomem *regs;
-#ifdef CONFIG_DM_ETH
struct eth_pdata *pdata = dev_get_plat(dev);
-#else
- struct eth_device *pdata = dev;
-#endif
u32 tempval;
int ret;
-#ifndef CONFIG_DM_ETH
- priv = (struct tsec_private *)dev->priv;
-#else
priv = dev_get_priv(dev);
-#endif
regs = priv->regs;
/* Make sure the controller is stopped */
tsec_halt(dev);
@@ -715,7 +612,7 @@ static int init_phy(struct tsec_private *priv)
if (priv->interface == PHY_INTERFACE_MODE_SGMII)
tsec_configure_serdes(priv);
-#if defined(CONFIG_DM_ETH) && defined(CONFIG_DM_MDIO)
+#if defined(CONFIG_DM_MDIO)
phydev = dm_eth_phy_connect(priv->dev);
#else
phydev = phy_connect(priv->bus, priv->phyaddr, priv->dev,
@@ -734,99 +631,6 @@ static int init_phy(struct tsec_private *priv)
return 1;
}
-#ifndef CONFIG_DM_ETH
-/*
- * Initialize device structure. Returns success if PHY
- * initialization succeeded (i.e. if it recognizes the PHY)
- */
-static int tsec_initialize(struct bd_info *bis,
- struct tsec_info_struct *tsec_info)
-{
- struct tsec_private *priv;
- struct eth_device *dev;
- int i;
-
- dev = (struct eth_device *)malloc(sizeof(*dev));
-
- if (!dev)
- return 0;
-
- memset(dev, 0, sizeof(*dev));
-
- priv = (struct tsec_private *)malloc(sizeof(*priv));
-
- if (!priv) {
- free(dev);
- return 0;
- }
-
- priv->regs = tsec_info->regs;
- priv->phyregs_sgmii = tsec_info->miiregs_sgmii;
-
- priv->phyaddr = tsec_info->phyaddr;
- priv->tbiaddr = CFG_SYS_TBIPA_VALUE;
- priv->flags = tsec_info->flags;
-
- strcpy(dev->name, tsec_info->devname);
- priv->interface = tsec_info->interface;
- priv->bus = miiphy_get_dev_by_name(tsec_info->mii_devname);
- priv->dev = dev;
- dev->iobase = 0;
- dev->priv = priv;
- dev->init = tsec_init;
- dev->halt = tsec_halt;
- dev->send = tsec_send;
- dev->recv = tsec_recv;
- dev->mcast = tsec_mcast_addr;
-
- /* Tell U-Boot to get the addr from the env */
- for (i = 0; i < 6; i++)
- dev->enetaddr[i] = 0;
-
- eth_register(dev);
-
- /* Reset the MAC */
- setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
- udelay(2); /* Soft Reset must be asserted for 3 TX clocks */
- clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
-
- /* Try to initialize PHY here, and return */
- return init_phy(priv);
-}
-
-/*
- * Initialize all the TSEC devices
- *
- * Returns the number of TSEC devices that were initialized
- */
-int tsec_eth_init(struct bd_info *bis, struct tsec_info_struct *tsecs,
- int num)
-{
- int i;
- int count = 0;
-
- for (i = 0; i < num; i++) {
- int ret = tsec_initialize(bis, &tsecs[i]);
-
- if (ret > 0)
- count += ret;
- }
-
- return count;
-}
-
-int tsec_standard_init(struct bd_info *bis)
-{
- struct fsl_pq_mdio_info info;
-
- info.regs = TSEC_GET_MDIO_REGS_BASE(1);
- info.name = DEFAULT_MII_NAME;
-
- fsl_pq_mdio_init(bis, &info);
-
- return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info));
-}
-#else /* CONFIG_DM_ETH */
int tsec_probe(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_plat(dev);
@@ -966,4 +770,3 @@ U_BOOT_DRIVER(eth_tsec) = {
.plat_auto = sizeof(struct eth_pdata),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
-#endif /* CONFIG_DM_ETH */
diff --git a/drivers/net/vsc9953.c b/drivers/net/vsc9953.c
deleted file mode 100644
index 29f26b4b332..00000000000
--- a/drivers/net/vsc9953.c
+++ /dev/null
@@ -1,2754 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014 - 2015 Freescale Semiconductor, Inc.
- *
- * Driver for the Vitesse VSC9953 L2 Switch
- */
-
-#include <common.h>
-#include <command.h>
-#include <log.h>
-#include <asm/io.h>
-#include <asm/fsl_serdes.h>
-#include <fm_eth.h>
-#include <fsl_memac.h>
-#include <bitfield.h>
-#include <errno.h>
-#include <malloc.h>
-#include <vsc9953.h>
-#include <ethsw.h>
-#include <linux/delay.h>
-
-static struct vsc9953_info vsc9953_l2sw = {
- .port[0] = VSC9953_PORT_INFO_INITIALIZER(0),
- .port[1] = VSC9953_PORT_INFO_INITIALIZER(1),
- .port[2] = VSC9953_PORT_INFO_INITIALIZER(2),
- .port[3] = VSC9953_PORT_INFO_INITIALIZER(3),
- .port[4] = VSC9953_PORT_INFO_INITIALIZER(4),
- .port[5] = VSC9953_PORT_INFO_INITIALIZER(5),
- .port[6] = VSC9953_PORT_INFO_INITIALIZER(6),
- .port[7] = VSC9953_PORT_INFO_INITIALIZER(7),
- .port[8] = VSC9953_PORT_INFO_INITIALIZER(8),
- .port[9] = VSC9953_PORT_INFO_INITIALIZER(9),
-};
-
-void vsc9953_port_info_set_mdio(int port_no, struct mii_dev *bus)
-{
- if (!VSC9953_PORT_CHECK(port_no))
- return;
-
- vsc9953_l2sw.port[port_no].bus = bus;
-}
-
-void vsc9953_port_info_set_phy_address(int port_no, int address)
-{
- if (!VSC9953_PORT_CHECK(port_no))
- return;
-
- vsc9953_l2sw.port[port_no].phyaddr = address;
-}
-
-void vsc9953_port_info_set_phy_int(int port_no, phy_interface_t phy_int)
-{
- if (!VSC9953_PORT_CHECK(port_no))
- return;
-
- vsc9953_l2sw.port[port_no].enet_if = phy_int;
-}
-
-void vsc9953_port_enable(int port_no)
-{
- if (!VSC9953_PORT_CHECK(port_no))
- return;
-
- vsc9953_l2sw.port[port_no].enabled = 1;
-}
-
-void vsc9953_port_disable(int port_no)
-{
- if (!VSC9953_PORT_CHECK(port_no))
- return;
-
- vsc9953_l2sw.port[port_no].enabled = 0;
-}
-
-static void vsc9953_mdio_write(struct vsc9953_mii_mng *phyregs, int port_addr,
- int regnum, int value)
-{
- int timeout = 50000;
-
- out_le32(&phyregs->miimcmd, (0x1 << 31) | ((port_addr & 0x1f) << 25) |
- ((regnum & 0x1f) << 20) | ((value & 0xffff) << 4) |
- (0x1 << 1));
- asm("sync");
-
- while ((in_le32(&phyregs->miimstatus) & 0x8) && --timeout)
- udelay(1);
-
- if (timeout == 0)
- debug("Timeout waiting for MDIO write\n");
-}
-
-static int vsc9953_mdio_read(struct vsc9953_mii_mng *phyregs, int port_addr,
- int regnum)
-{
- int value = 0xFFFF;
- int timeout = 50000;
-
- while ((in_le32(&phyregs->miimstatus) & MIIMIND_OPR_PEND) && --timeout)
- udelay(1);
- if (timeout == 0) {
- debug("Timeout waiting for MDIO operation to finish\n");
- return value;
- }
-
- /* Put the address of the phy, and the register
- * number into MIICMD
- */
- out_le32(&phyregs->miimcmd, (0x1 << 31) | ((port_addr & 0x1f) << 25) |
- ((regnum & 0x1f) << 20) | ((value & 0xffff) << 4) |
- (0x2 << 1));
-
- timeout = 50000;
- /* Wait for the the indication that the read is done */
- while ((in_le32(&phyregs->miimstatus) & 0x8) && --timeout)
- udelay(1);
- if (timeout == 0)
- debug("Timeout waiting for MDIO read\n");
-
- /* Grab the value read from the PHY */
- value = in_le32(&phyregs->miimdata);
-
- if ((value & 0x00030000) == 0)
- return value & 0x0000ffff;
-
- return value;
-}
-
-static int init_phy(struct eth_device *dev)
-{
- struct vsc9953_port_info *l2sw_port = dev->priv;
- struct phy_device *phydev = NULL;
-
-#ifdef CONFIG_PHYLIB
- if (!l2sw_port->bus)
- return 0;
- phydev = phy_connect(l2sw_port->bus, l2sw_port->phyaddr, dev,
- l2sw_port->enet_if);
- if (!phydev) {
- printf("Failed to connect\n");
- return -1;
- }
-
- phydev->supported &= SUPPORTED_10baseT_Half |
- SUPPORTED_10baseT_Full |
- SUPPORTED_100baseT_Half |
- SUPPORTED_100baseT_Full |
- SUPPORTED_1000baseT_Full;
- phydev->advertising = phydev->supported;
-
- l2sw_port->phydev = phydev;
-
- phy_config(phydev);
-#endif
-
- return 0;
-}
-
-static int vsc9953_port_init(int port_no)
-{
- struct eth_device *dev;
-
- /* Internal ports never have a PHY */
- if (VSC9953_INTERNAL_PORT_CHECK(port_no))
- return 0;
-
- /* alloc eth device */
- dev = (struct eth_device *)calloc(1, sizeof(struct eth_device));
- if (!dev)
- return -ENOMEM;
-
- sprintf(dev->name, "SW@PORT%d", port_no);
- dev->priv = &vsc9953_l2sw.port[port_no];
- dev->init = NULL;
- dev->halt = NULL;
- dev->send = NULL;
- dev->recv = NULL;
-
- if (init_phy(dev)) {
- free(dev);
- return -ENODEV;
- }
-
- return 0;
-}
-
-static int vsc9953_vlan_table_poll_idle(void)
-{
- struct vsc9953_analyzer *l2ana_reg;
- int timeout;
-
- l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET +
- VSC9953_ANA_OFFSET);
-
- timeout = 50000;
- while (((in_le32(&l2ana_reg->ana_tables.vlan_access) &
- VSC9953_VLAN_CMD_MASK) != VSC9953_VLAN_CMD_IDLE) && --timeout)
- udelay(1);
-
- return timeout ? 0 : -EBUSY;
-}
-
-#ifdef CONFIG_CMD_ETHSW
-/* Add/remove a port to/from a VLAN */
-static void vsc9953_vlan_table_membership_set(int vid, u32 port_no, u8 add)
-{
- u32 val;
- struct vsc9953_analyzer *l2ana_reg;
-
- l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET +
- VSC9953_ANA_OFFSET);
-
- if (vsc9953_vlan_table_poll_idle() < 0) {
- debug("VLAN table timeout\n");
- return;
- }
-
- val = in_le32(&l2ana_reg->ana_tables.vlan_tidx);
- val = bitfield_replace_by_mask(val, VSC9953_ANA_TBL_VID_MASK, vid);
- out_le32(&l2ana_reg->ana_tables.vlan_tidx, val);
-
- clrsetbits_le32(&l2ana_reg->ana_tables.vlan_access,
- VSC9953_VLAN_CMD_MASK, VSC9953_VLAN_CMD_READ);
-
- if (vsc9953_vlan_table_poll_idle() < 0) {
- debug("VLAN table timeout\n");
- return;
- }
-
- val = in_le32(&l2ana_reg->ana_tables.vlan_tidx);
- val = bitfield_replace_by_mask(val, VSC9953_ANA_TBL_VID_MASK, vid);
- out_le32(&l2ana_reg->ana_tables.vlan_tidx, val);
-
- val = in_le32(&l2ana_reg->ana_tables.vlan_access);
- if (!add) {
- val = bitfield_replace_by_mask(val, VSC9953_VLAN_CMD_MASK,
- VSC9953_VLAN_CMD_WRITE) &
- ~(bitfield_replace_by_mask(0, VSC9953_VLAN_PORT_MASK,
- (1 << port_no)));
- ;
- } else {
- val = bitfield_replace_by_mask(val, VSC9953_VLAN_CMD_MASK,
- VSC9953_VLAN_CMD_WRITE) |
- bitfield_replace_by_mask(0, VSC9953_VLAN_PORT_MASK,
- (1 << port_no));
- }
- out_le32(&l2ana_reg->ana_tables.vlan_access, val);
-
- /* wait for VLAN table command to flush */
- if (vsc9953_vlan_table_poll_idle() < 0) {
- debug("VLAN table timeout\n");
- return;
- }
-}
-
-/* show VLAN membership for a port */
-static void vsc9953_vlan_membership_show(int port_no)
-{
- u32 val;
- struct vsc9953_analyzer *l2ana_reg;
- u32 vid;
-
- l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET +
- VSC9953_ANA_OFFSET);
-
- printf("Port %d VLAN membership: ", port_no);
-
- for (vid = 0; vid < VSC9953_MAX_VLAN; vid++) {
- if (vsc9953_vlan_table_poll_idle() < 0) {
- debug("VLAN table timeout\n");
- return;
- }
-
- val = in_le32(&l2ana_reg->ana_tables.vlan_tidx);
- val = bitfield_replace_by_mask(val, VSC9953_ANA_TBL_VID_MASK,
- vid);
- out_le32(&l2ana_reg->ana_tables.vlan_tidx, val);
-
- clrsetbits_le32(&l2ana_reg->ana_tables.vlan_access,
- VSC9953_VLAN_CMD_MASK, VSC9953_VLAN_CMD_READ);
-
- if (vsc9953_vlan_table_poll_idle() < 0) {
- debug("VLAN table timeout\n");
- return;
- }
-
- val = in_le32(&l2ana_reg->ana_tables.vlan_access);
-
- if (bitfield_extract_by_mask(val, VSC9953_VLAN_PORT_MASK) &
- (1 << port_no))
- printf("%d ", vid);
- }
- printf("\n");
-}
-#endif
-
-/* vlan table set/clear all membership of vid */
-static void vsc9953_vlan_table_membership_all_set(int vid, int set_member)
-{
- uint val;
- struct vsc9953_analyzer *l2ana_reg;
-
- l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET +
- VSC9953_ANA_OFFSET);
-
- if (vsc9953_vlan_table_poll_idle() < 0) {
- debug("VLAN table timeout\n");
- return;
- }
-
- /* read current vlan configuration */
- val = in_le32(&l2ana_reg->ana_tables.vlan_tidx);
- out_le32(&l2ana_reg->ana_tables.vlan_tidx,
- bitfield_replace_by_mask(val, VSC9953_ANA_TBL_VID_MASK, vid));
-
- clrsetbits_le32(&l2ana_reg->ana_tables.vlan_access,
- VSC9953_VLAN_CMD_MASK, VSC9953_VLAN_CMD_READ);
-
- if (vsc9953_vlan_table_poll_idle() < 0) {
- debug("VLAN table timeout\n");
- return;
- }
-
- val = in_le32(&l2ana_reg->ana_tables.vlan_tidx);
- out_le32(&l2ana_reg->ana_tables.vlan_tidx,
- bitfield_replace_by_mask(val, VSC9953_ANA_TBL_VID_MASK, vid));
-
- clrsetbits_le32(&l2ana_reg->ana_tables.vlan_access,
- VSC9953_VLAN_PORT_MASK | VSC9953_VLAN_CMD_MASK,
- VSC9953_VLAN_CMD_WRITE |
- (set_member ? VSC9953_VLAN_PORT_MASK : 0));
-}
-
-#ifdef CONFIG_CMD_ETHSW
-/* Get PVID of a VSC9953 port */
-static int vsc9953_port_vlan_pvid_get(int port_nr, int *pvid)
-{
- u32 val;
- struct vsc9953_analyzer *l2ana_reg;
-
- /* Administrative down */
- if (!vsc9953_l2sw.port[port_nr].enabled) {
- printf("Port %d is administrative down\n", port_nr);
- return -1;
- }
-
- l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET +
- VSC9953_ANA_OFFSET);
-
- /* Get ingress PVID */
- val = in_le32(&l2ana_reg->port[port_nr].vlan_cfg);
- *pvid = bitfield_extract_by_mask(val, VSC9953_VLAN_CFG_VID_MASK);
-
- return 0;
-}
-#endif
-
-/* Set PVID for a VSC9953 port */
-static void vsc9953_port_vlan_pvid_set(int port_no, int pvid)
-{
- uint val;
- struct vsc9953_analyzer *l2ana_reg;
- struct vsc9953_rew_reg *l2rew_reg;
-
- /* Administrative down */
- if (!vsc9953_l2sw.port[port_no].enabled) {
- printf("Port %d is administrative down\n", port_no);
- return;
- }
-
- l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET +
- VSC9953_ANA_OFFSET);
- l2rew_reg = (struct vsc9953_rew_reg *)(VSC9953_OFFSET +
- VSC9953_REW_OFFSET);
-
- /* Set PVID on ingress */
- val = in_le32(&l2ana_reg->port[port_no].vlan_cfg);
- val = bitfield_replace_by_mask(val, VSC9953_VLAN_CFG_VID_MASK, pvid);
- out_le32(&l2ana_reg->port[port_no].vlan_cfg, val);
-
- /* Set PVID on egress */
- val = in_le32(&l2rew_reg->port[port_no].port_vlan_cfg);
- val = bitfield_replace_by_mask(val, VSC9953_PORT_VLAN_CFG_VID_MASK,
- pvid);
- out_le32(&l2rew_reg->port[port_no].port_vlan_cfg, val);
-}
-
-static void vsc9953_port_all_vlan_pvid_set(int pvid)
-{
- int i;
-
- for (i = 0; i < VSC9953_MAX_PORTS; i++)
- vsc9953_port_vlan_pvid_set(i, pvid);
-}
-
-/* Enable/disable vlan aware of a VSC9953 port */
-static void vsc9953_port_vlan_aware_set(int port_no, int enabled)
-{
- struct vsc9953_analyzer *l2ana_reg;
-
- /* Administrative down */
- if (!vsc9953_l2sw.port[port_no].enabled) {
- printf("Port %d is administrative down\n", port_no);
- return;
- }
-
- l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET +
- VSC9953_ANA_OFFSET);
-
- if (enabled)
- setbits_le32(&l2ana_reg->port[port_no].vlan_cfg,
- VSC9953_VLAN_CFG_AWARE_ENA);
- else
- clrbits_le32(&l2ana_reg->port[port_no].vlan_cfg,
- VSC9953_VLAN_CFG_AWARE_ENA);
-}
-
-/* Set all VSC9953 ports' vlan aware */
-static void vsc9953_port_all_vlan_aware_set(int enabled)
-{
- int i;
-
- for (i = 0; i < VSC9953_MAX_PORTS; i++)
- vsc9953_port_vlan_aware_set(i, enabled);
-}
-
-/* Enable/disable vlan pop count of a VSC9953 port */
-static void vsc9953_port_vlan_popcnt_set(int port_no, int popcnt)
-{
- uint val;
- struct vsc9953_analyzer *l2ana_reg;
-
- /* Administrative down */
- if (!vsc9953_l2sw.port[port_no].enabled) {
- printf("Port %d is administrative down\n", port_no);
- return;
- }
-
- if (popcnt > 3 || popcnt < 0) {
- printf("Invalid pop count value: %d\n", port_no);
- return;
- }
-
- l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET +
- VSC9953_ANA_OFFSET);
-
- val = in_le32(&l2ana_reg->port[port_no].vlan_cfg);
- val = bitfield_replace_by_mask(val, VSC9953_VLAN_CFG_POP_CNT_MASK,
- popcnt);
- out_le32(&l2ana_reg->port[port_no].vlan_cfg, val);
-}
-
-/* Set all VSC9953 ports' pop count */
-static void vsc9953_port_all_vlan_poncnt_set(int popcnt)
-{
- int i;
-
- for (i = 0; i < VSC9953_MAX_PORTS; i++)
- vsc9953_port_vlan_popcnt_set(i, popcnt);
-}
-
-/* Enable/disable learning for frames dropped due to ingress filtering */
-static void vsc9953_vlan_ingr_fltr_learn_drop(int enable)
-{
- struct vsc9953_analyzer *l2ana_reg;
-
- l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET +
- VSC9953_ANA_OFFSET);
-
- if (enable)
- setbits_le32(&l2ana_reg->ana.adv_learn, VSC9953_VLAN_CHK);
- else
- clrbits_le32(&l2ana_reg->ana.adv_learn, VSC9953_VLAN_CHK);
-}
-
-enum aggr_code_mode {
- AGGR_CODE_RAND = 0,
- AGGR_CODE_ALL, /* S/D MAC, IPv4 S/D IP, IPv6 Flow Label, S/D PORT */
-};
-
-/* Set aggregation code generation mode */
-static int vsc9953_aggr_code_set(enum aggr_code_mode ac)
-{
- int rc;
- struct vsc9953_analyzer *l2ana_reg;
-
- l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET +
- VSC9953_ANA_OFFSET);
-
- switch (ac) {
- case AGGR_CODE_RAND:
- clrsetbits_le32(&l2ana_reg->common.aggr_cfg,
- VSC9953_AC_DMAC_ENA | VSC9953_AC_SMAC_ENA |
- VSC9953_AC_IP6_LBL_ENA |
- VSC9953_AC_IP6_TCPUDP_ENA |
- VSC9953_AC_IP4_SIPDIP_ENA |
- VSC9953_AC_IP4_TCPUDP_ENA, VSC9953_AC_RND_ENA);
- rc = 0;
- break;
- case AGGR_CODE_ALL:
- clrsetbits_le32(&l2ana_reg->common.aggr_cfg, VSC9953_AC_RND_ENA,
- VSC9953_AC_DMAC_ENA | VSC9953_AC_SMAC_ENA |
- VSC9953_AC_IP6_LBL_ENA |
- VSC9953_AC_IP6_TCPUDP_ENA |
- VSC9953_AC_IP4_SIPDIP_ENA |
- VSC9953_AC_IP4_TCPUDP_ENA);
- rc = 0;
- break;
- default:
- /* unknown mode for aggregation code */
- rc = -EINVAL;
- }
-
- return rc;
-}
-
-/* Egress untag modes of a VSC9953 port */
-enum egress_untag_mode {
- EGRESS_UNTAG_ALL = 0,
- EGRESS_UNTAG_PVID_AND_ZERO,
- EGRESS_UNTAG_ZERO,
- EGRESS_UNTAG_NONE,
-};
-
-#ifdef CONFIG_CMD_ETHSW
-/* Get egress tagging configuration for a VSC9953 port */
-static int vsc9953_port_vlan_egr_untag_get(int port_no,
- enum egress_untag_mode *mode)
-{
- u32 val;
- struct vsc9953_rew_reg *l2rew_reg;
-
- /* Administrative down */
- if (!vsc9953_l2sw.port[port_no].enabled) {
- printf("Port %d is administrative down\n", port_no);
- return -1;
- }
-
- l2rew_reg = (struct vsc9953_rew_reg *)(VSC9953_OFFSET +
- VSC9953_REW_OFFSET);
-
- val = in_le32(&l2rew_reg->port[port_no].port_tag_cfg);
-
- switch (val & VSC9953_TAG_CFG_MASK) {
- case VSC9953_TAG_CFG_NONE:
- *mode = EGRESS_UNTAG_ALL;
- return 0;
- case VSC9953_TAG_CFG_ALL_BUT_PVID_ZERO:
- *mode = EGRESS_UNTAG_PVID_AND_ZERO;
- return 0;
- case VSC9953_TAG_CFG_ALL_BUT_ZERO:
- *mode = EGRESS_UNTAG_ZERO;
- return 0;
- case VSC9953_TAG_CFG_ALL:
- *mode = EGRESS_UNTAG_NONE;
- return 0;
- default:
- printf("Unknown egress tagging configuration for port %d\n",
- port_no);
- return -1;
- }
-}
-
-/* Show egress tagging configuration for a VSC9953 port */
-static void vsc9953_port_vlan_egr_untag_show(int port_no)
-{
- enum egress_untag_mode mode;
-
- if (vsc9953_port_vlan_egr_untag_get(port_no, &mode)) {
- printf("%7d\t%17s\n", port_no, "-");
- return;
- }
-
- printf("%7d\t", port_no);
- switch (mode) {
- case EGRESS_UNTAG_ALL:
- printf("%17s\n", "all");
- break;
- case EGRESS_UNTAG_NONE:
- printf("%17s\n", "none");
- break;
- case EGRESS_UNTAG_PVID_AND_ZERO:
- printf("%17s\n", "PVID and 0");
- break;
- case EGRESS_UNTAG_ZERO:
- printf("%17s\n", "0");
- break;
- default:
- printf("%17s\n", "-");
- }
-}
-#endif
-
-static void vsc9953_port_vlan_egr_untag_set(int port_no,
- enum egress_untag_mode mode)
-{
- struct vsc9953_rew_reg *l2rew_reg;
-
- /* Administrative down */
- if (!vsc9953_l2sw.port[port_no].enabled) {
- printf("Port %d is administrative down\n", port_no);
- return;
- }
-
- l2rew_reg = (struct vsc9953_rew_reg *)(VSC9953_OFFSET +
- VSC9953_REW_OFFSET);
-
- switch (mode) {
- case EGRESS_UNTAG_ALL:
- clrsetbits_le32(&l2rew_reg->port[port_no].port_tag_cfg,
- VSC9953_TAG_CFG_MASK, VSC9953_TAG_CFG_NONE);
- break;
- case EGRESS_UNTAG_PVID_AND_ZERO:
- clrsetbits_le32(&l2rew_reg->port[port_no].port_tag_cfg,
- VSC9953_TAG_CFG_MASK,
- VSC9953_TAG_CFG_ALL_BUT_PVID_ZERO);
- break;
- case EGRESS_UNTAG_ZERO:
- clrsetbits_le32(&l2rew_reg->port[port_no].port_tag_cfg,
- VSC9953_TAG_CFG_MASK,
- VSC9953_TAG_CFG_ALL_BUT_ZERO);
- break;
- case EGRESS_UNTAG_NONE:
- clrsetbits_le32(&l2rew_reg->port[port_no].port_tag_cfg,
- VSC9953_TAG_CFG_MASK, VSC9953_TAG_CFG_ALL);
- break;
- default:
- printf("Unknown untag mode for port %d\n", port_no);
- }
-}
-
-static void vsc9953_port_all_vlan_egress_untagged_set(
- enum egress_untag_mode mode)
-{
- int i;
-
- for (i = 0; i < VSC9953_MAX_PORTS; i++)
- vsc9953_port_vlan_egr_untag_set(i, mode);
-}
-
-static int vsc9953_autoage_time_set(int age_period)
-{
- u32 autoage;
- struct vsc9953_analyzer *l2ana_reg;
-
- l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET +
- VSC9953_ANA_OFFSET);
-
- if (age_period < 0 || age_period > VSC9953_AUTOAGE_PERIOD_MASK)
- return -EINVAL;
-
- autoage = bitfield_replace_by_mask(in_le32(&l2ana_reg->ana.auto_age),
- VSC9953_AUTOAGE_PERIOD_MASK,
- age_period);
- out_le32(&l2ana_reg->ana.auto_age, autoage);
-
- return 0;
-}
-
-#ifdef CONFIG_CMD_ETHSW
-
-/* Enable/disable status of a VSC9953 port */
-static void vsc9953_port_status_set(int port_no, u8 enabled)
-{
- struct vsc9953_qsys_reg *l2qsys_reg;
-
- /* Administrative down */
- if (!vsc9953_l2sw.port[port_no].enabled)
- return;
-
- l2qsys_reg = (struct vsc9953_qsys_reg *)(VSC9953_OFFSET +
- VSC9953_QSYS_OFFSET);
-
- if (enabled)
- setbits_le32(&l2qsys_reg->sys.switch_port_mode[port_no],
- VSC9953_PORT_ENA);
- else
- clrbits_le32(&l2qsys_reg->sys.switch_port_mode[port_no],
- VSC9953_PORT_ENA);
-}
-
-/* Start autonegotiation for a VSC9953 PHY */
-static void vsc9953_phy_autoneg(int port_no)
-{
- if (!vsc9953_l2sw.port[port_no].phydev)
- return;
-
- if (vsc9953_l2sw.port[port_no].phydev->drv->startup(
- vsc9953_l2sw.port[port_no].phydev))
- printf("Failed to start PHY for port %d\n", port_no);
-}
-
-/* Print a VSC9953 port's configuration */
-static void vsc9953_port_config_show(int port_no)
-{
- int speed;
- int duplex;
- int link;
- u8 enabled;
- u32 val;
- struct vsc9953_qsys_reg *l2qsys_reg;
-
- l2qsys_reg = (struct vsc9953_qsys_reg *)(VSC9953_OFFSET +
- VSC9953_QSYS_OFFSET);
-
- val = in_le32(&l2qsys_reg->sys.switch_port_mode[port_no]);
- enabled = vsc9953_l2sw.port[port_no].enabled &&
- (val & VSC9953_PORT_ENA);
-
- /* internal ports (8 and 9) are fixed */
- if (VSC9953_INTERNAL_PORT_CHECK(port_no)) {
- link = 1;
- speed = SPEED_2500;
- duplex = DUPLEX_FULL;
- } else {
- if (vsc9953_l2sw.port[port_no].phydev) {
- link = vsc9953_l2sw.port[port_no].phydev->link;
- speed = vsc9953_l2sw.port[port_no].phydev->speed;
- duplex = vsc9953_l2sw.port[port_no].phydev->duplex;
- } else {
- link = -1;
- speed = -1;
- duplex = -1;
- }
- }
-
- printf("%8d ", port_no);
- printf("%8s ", enabled == 1 ? "enabled" : "disabled");
- printf("%8s ", link == 1 ? "up" : "down");
-
- switch (speed) {
- case SPEED_10:
- printf("%8d ", 10);
- break;
- case SPEED_100:
- printf("%8d ", 100);
- break;
- case SPEED_1000:
- printf("%8d ", 1000);
- break;
- case SPEED_2500:
- printf("%8d ", 2500);
- break;
- case SPEED_10000:
- printf("%8d ", 10000);
- break;
- default:
- printf("%8s ", "-");
- }
-
- printf("%8s\n", duplex == DUPLEX_FULL ? "full" : "half");
-}
-
-/* Show VSC9953 ports' statistics */
-static void vsc9953_port_statistics_show(int port_no)
-{
- u32 rx_val;
- u32 tx_val;
- struct vsc9953_system_reg *l2sys_reg;
-
- /* Administrative down */
- if (!vsc9953_l2sw.port[port_no].enabled) {
- printf("Port %d is administrative down\n", port_no);
- return;
- }
-
- l2sys_reg = (struct vsc9953_system_reg *)(VSC9953_OFFSET +
- VSC9953_SYS_OFFSET);
-
- printf("Statistics for L2 Switch port %d:\n", port_no);
-
- /* Set counter view for our port */
- out_le32(&l2sys_reg->sys.stat_cfg, port_no);
-
-#define VSC9953_STATS_PRINTF "%-15s %10u"
-
- /* Get number of Rx and Tx frames */
- rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_short) +
- in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_frag) +
- in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_jabber) +
- in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_long) +
- in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_64) +
- in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_65_127) +
- in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_128_255) +
- in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_256_511) +
- in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_512_1023) +
- in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_1024_1526) +
- in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_jumbo);
- tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_64) +
- in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_65_127) +
- in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_128_255) +
- in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_256_511) +
- in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_512_1023) +
- in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_1024_1526) +
- in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_jumbo);
- printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n",
- "Rx frames:", rx_val, "Tx frames:", tx_val);
-
- /* Get number of Rx and Tx bytes */
- rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_oct);
- tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_oct);
- printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n",
- "Rx bytes:", rx_val, "Tx bytes:", tx_val);
-
- /* Get number of Rx frames received ok and Tx frames sent ok */
- rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_yellow_prio_0) +
- in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_yellow_prio_1) +
- in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_yellow_prio_2) +
- in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_yellow_prio_3) +
- in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_yellow_prio_4) +
- in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_yellow_prio_5) +
- in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_yellow_prio_6) +
- in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_yellow_prio_7) +
- in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_green_prio_0) +
- in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_green_prio_1) +
- in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_green_prio_2) +
- in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_green_prio_3) +
- in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_green_prio_4) +
- in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_green_prio_5) +
- in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_green_prio_6) +
- in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_green_prio_7);
- tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_64) +
- in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_65_127) +
- in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_128_255) +
- in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_256_511) +
- in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_512_1023) +
- in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_1024_1526) +
- in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_jumbo);
- printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n",
- "Rx frames ok:", rx_val, "Tx frames ok:", tx_val);
-
- /* Get number of Rx and Tx unicast frames */
- rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_uc);
- tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_uc);
- printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n",
- "Rx unicast:", rx_val, "Tx unicast:", tx_val);
-
- /* Get number of Rx and Tx broadcast frames */
- rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_bc);
- tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_bc);
- printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n",
- "Rx broadcast:", rx_val, "Tx broadcast:", tx_val);
-
- /* Get number of Rx and Tx frames of 64B */
- rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_64);
- tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_64);
- printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n",
- "Rx 64B:", rx_val, "Tx 64B:", tx_val);
-
- /* Get number of Rx and Tx frames with sizes between 65B and 127B */
- rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_65_127);
- tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_65_127);
- printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n",
- "Rx 65B-127B:", rx_val, "Tx 65B-127B:", tx_val);
-
- /* Get number of Rx and Tx frames with sizes between 128B and 255B */
- rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_128_255);
- tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_128_255);
- printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n",
- "Rx 128B-255B:", rx_val, "Tx 128B-255B:", tx_val);
-
- /* Get number of Rx and Tx frames with sizes between 256B and 511B */
- rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_256_511);
- tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_256_511);
- printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n",
- "Rx 256B-511B:", rx_val, "Tx 256B-511B:", tx_val);
-
- /* Get number of Rx and Tx frames with sizes between 512B and 1023B */
- rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_512_1023);
- tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_512_1023);
- printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n",
- "Rx 512B-1023B:", rx_val, "Tx 512B-1023B:", tx_val);
-
- /* Get number of Rx and Tx frames with sizes between 1024B and 1526B */
- rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_1024_1526);
- tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_1024_1526);
- printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n",
- "Rx 1024B-1526B:", rx_val, "Tx 1024B-1526B:", tx_val);
-
- /* Get number of Rx and Tx jumbo frames */
- rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_jumbo);
- tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_jumbo);
- printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n",
- "Rx jumbo:", rx_val, "Tx jumbo:", tx_val);
-
- /* Get number of Rx and Tx dropped frames */
- rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_cat_drop) +
- in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_tail) +
- in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_yellow_prio_0) +
- in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_yellow_prio_1) +
- in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_yellow_prio_2) +
- in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_yellow_prio_3) +
- in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_yellow_prio_4) +
- in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_yellow_prio_5) +
- in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_yellow_prio_6) +
- in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_yellow_prio_7) +
- in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_green_prio_0) +
- in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_green_prio_1) +
- in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_green_prio_2) +
- in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_green_prio_3) +
- in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_green_prio_4) +
- in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_green_prio_5) +
- in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_green_prio_6) +
- in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_green_prio_7);
- tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_drop) +
- in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_aged);
- printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n",
- "Rx drops:", rx_val, "Tx drops:", tx_val);
-
- /*
- * Get number of Rx frames with CRC or alignment errors
- * and number of detected Tx collisions
- */
- rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_crc);
- tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_col);
- printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n",
- "Rx CRC&align:", rx_val, "Tx coll:", tx_val);
-
- /*
- * Get number of Rx undersized frames and
- * number of Tx aged frames
- */
- rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_short);
- tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_aged);
- printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n",
- "Rx undersize:", rx_val, "Tx aged:", tx_val);
-
- /* Get number of Rx oversized frames */
- rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_long);
- printf(VSC9953_STATS_PRINTF"\n", "Rx oversized:", rx_val);
-
- /* Get number of Rx fragmented frames */
- rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_frag);
- printf(VSC9953_STATS_PRINTF"\n", "Rx fragments:", rx_val);
-
- /* Get number of Rx jabber errors */
- rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_jabber);
- printf(VSC9953_STATS_PRINTF"\n", "Rx jabbers:", rx_val);
-
- /*
- * Get number of Rx frames filtered due to classification rules or
- * no destination ports
- */
- rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_cat_drop) +
- in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_local);
- printf(VSC9953_STATS_PRINTF"\n", "Rx filtered:", rx_val);
-
- printf("\n");
-}
-
-/* Clear statistics for a VSC9953 port */
-static void vsc9953_port_statistics_clear(int port_no)
-{
- struct vsc9953_system_reg *l2sys_reg;
-
- /* Administrative down */
- if (!vsc9953_l2sw.port[port_no].enabled) {
- printf("Port %d is administrative down\n", port_no);
- return;
- }
-
- l2sys_reg = (struct vsc9953_system_reg *)(VSC9953_OFFSET +
- VSC9953_SYS_OFFSET);
-
- /* Clear all counter groups for our ports */
- out_le32(&l2sys_reg->sys.stat_cfg, port_no |
- VSC9953_STAT_CLEAR_RX | VSC9953_STAT_CLEAR_TX |
- VSC9953_STAT_CLEAR_DR);
-}
-
-enum port_learn_mode {
- PORT_LEARN_NONE,
- PORT_LEARN_AUTO
-};
-
-/* Set learning configuration for a VSC9953 port */
-static void vsc9953_port_learn_mode_set(int port_no, enum port_learn_mode mode)
-{
- struct vsc9953_analyzer *l2ana_reg;
-
- /* Administrative down */
- if (!vsc9953_l2sw.port[port_no].enabled) {
- printf("Port %d is administrative down\n", port_no);
- return;
- }
-
- l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET +
- VSC9953_ANA_OFFSET);
-
- switch (mode) {
- case PORT_LEARN_NONE:
- clrbits_le32(&l2ana_reg->port[port_no].port_cfg,
- VSC9953_PORT_CFG_LEARN_DROP |
- VSC9953_PORT_CFG_LEARN_CPU |
- VSC9953_PORT_CFG_LEARN_AUTO |
- VSC9953_PORT_CFG_LEARN_ENA);
- break;
- case PORT_LEARN_AUTO:
- clrsetbits_le32(&l2ana_reg->port[port_no].port_cfg,
- VSC9953_PORT_CFG_LEARN_DROP |
- VSC9953_PORT_CFG_LEARN_CPU,
- VSC9953_PORT_CFG_LEARN_ENA |
- VSC9953_PORT_CFG_LEARN_AUTO);
- break;
- default:
- printf("Unknown learn mode for port %d\n", port_no);
- }
-}
-
-/* Get learning configuration for a VSC9953 port */
-static int vsc9953_port_learn_mode_get(int port_no, enum port_learn_mode *mode)
-{
- u32 val;
- struct vsc9953_analyzer *l2ana_reg;
-
- /* Administrative down */
- if (!vsc9953_l2sw.port[port_no].enabled) {
- printf("Port %d is administrative down\n", port_no);
- return -1;
- }
-
- l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET +
- VSC9953_ANA_OFFSET);
-
- /* For now we only support HW learning (auto) and no learning */
- val = in_le32(&l2ana_reg->port[port_no].port_cfg);
- if ((val & (VSC9953_PORT_CFG_LEARN_ENA |
- VSC9953_PORT_CFG_LEARN_AUTO)) ==
- (VSC9953_PORT_CFG_LEARN_ENA | VSC9953_PORT_CFG_LEARN_AUTO))
- *mode = PORT_LEARN_AUTO;
- else
- *mode = PORT_LEARN_NONE;
-
- return 0;
-}
-
-/* wait for FDB to become available */
-static int vsc9953_mac_table_poll_idle(void)
-{
- struct vsc9953_analyzer *l2ana_reg;
- u32 timeout;
-
- l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET +
- VSC9953_ANA_OFFSET);
-
- timeout = 50000;
- while (((in_le32(&l2ana_reg->ana_tables.mac_access) &
- VSC9953_MAC_CMD_MASK) !=
- VSC9953_MAC_CMD_IDLE) && --timeout)
- udelay(1);
-
- return timeout ? 0 : -EBUSY;
-}
-
-/* enum describing available commands for the MAC table */
-enum mac_table_cmd {
- MAC_TABLE_READ,
- MAC_TABLE_LOOKUP,
- MAC_TABLE_WRITE,
- MAC_TABLE_LEARN,
- MAC_TABLE_FORGET,
- MAC_TABLE_GET_NEXT,
- MAC_TABLE_AGE,
-};
-
-/* Issues a command to the FDB table */
-static int vsc9953_mac_table_cmd(enum mac_table_cmd cmd)
-{
- struct vsc9953_analyzer *l2ana_reg;
-
- l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET +
- VSC9953_ANA_OFFSET);
-
- switch (cmd) {
- case MAC_TABLE_READ:
- clrsetbits_le32(&l2ana_reg->ana_tables.mac_access,
- VSC9953_MAC_CMD_MASK | VSC9953_MAC_CMD_VALID,
- VSC9953_MAC_CMD_READ);
- break;
- case MAC_TABLE_LOOKUP:
- clrsetbits_le32(&l2ana_reg->ana_tables.mac_access,
- VSC9953_MAC_CMD_MASK, VSC9953_MAC_CMD_READ |
- VSC9953_MAC_CMD_VALID);
- break;
- case MAC_TABLE_WRITE:
- clrsetbits_le32(&l2ana_reg->ana_tables.mac_access,
- VSC9953_MAC_CMD_MASK |
- VSC9953_MAC_ENTRYTYPE_MASK,
- VSC9953_MAC_CMD_WRITE |
- VSC9953_MAC_ENTRYTYPE_LOCKED);
- break;
- case MAC_TABLE_LEARN:
- clrsetbits_le32(&l2ana_reg->ana_tables.mac_access,
- VSC9953_MAC_CMD_MASK |
- VSC9953_MAC_ENTRYTYPE_MASK,
- VSC9953_MAC_CMD_LEARN |
- VSC9953_MAC_ENTRYTYPE_LOCKED |
- VSC9953_MAC_CMD_VALID);
- break;
- case MAC_TABLE_FORGET:
- clrsetbits_le32(&l2ana_reg->ana_tables.mac_access,
- VSC9953_MAC_CMD_MASK |
- VSC9953_MAC_ENTRYTYPE_MASK,
- VSC9953_MAC_CMD_FORGET);
- break;
- case MAC_TABLE_GET_NEXT:
- clrsetbits_le32(&l2ana_reg->ana_tables.mac_access,
- VSC9953_MAC_CMD_MASK |
- VSC9953_MAC_ENTRYTYPE_MASK,
- VSC9953_MAC_CMD_NEXT);
- break;
- case MAC_TABLE_AGE:
- clrsetbits_le32(&l2ana_reg->ana_tables.mac_access,
- VSC9953_MAC_CMD_MASK |
- VSC9953_MAC_ENTRYTYPE_MASK,
- VSC9953_MAC_CMD_AGE);
- break;
- default:
- printf("Unknown MAC table command\n");
- }
-
- if (vsc9953_mac_table_poll_idle() < 0) {
- debug("MAC table timeout\n");
- return -1;
- }
-
- return 0;
-}
-
-/* show the FDB entries that correspond to a port and a VLAN */
-static void vsc9953_mac_table_show(int port_no, int vid)
-{
- int rc[VSC9953_MAX_PORTS];
- enum port_learn_mode mode[VSC9953_MAX_PORTS];
- int i;
- u32 val;
- u32 vlan;
- u32 mach;
- u32 macl;
- u32 dest_indx;
- struct vsc9953_analyzer *l2ana_reg;
-
- l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET +
- VSC9953_ANA_OFFSET);
-
- /* disable auto learning */
- if (port_no == ETHSW_CMD_PORT_ALL) {
- for (i = 0; i < VSC9953_MAX_PORTS; i++) {
- rc[i] = vsc9953_port_learn_mode_get(i, &mode[i]);
- if (!rc[i] && mode[i] != PORT_LEARN_NONE)
- vsc9953_port_learn_mode_set(i, PORT_LEARN_NONE);
- }
- } else {
- rc[port_no] = vsc9953_port_learn_mode_get(port_no,
- &mode[port_no]);
- if (!rc[port_no] && mode[port_no] != PORT_LEARN_NONE)
- vsc9953_port_learn_mode_set(port_no, PORT_LEARN_NONE);
- }
-
- /* write port and vid to get selected FDB entries */
- val = in_le32(&l2ana_reg->ana.anag_efil);
- if (port_no != ETHSW_CMD_PORT_ALL) {
- val = bitfield_replace_by_mask(val, VSC9953_AGE_PORT_MASK,
- port_no) | VSC9953_AGE_PORT_EN;
- }
- if (vid != ETHSW_CMD_VLAN_ALL) {
- val = bitfield_replace_by_mask(val, VSC9953_AGE_VID_MASK,
- vid) | VSC9953_AGE_VID_EN;
- }
- out_le32(&l2ana_reg->ana.anag_efil, val);
-
- /* set MAC and VLAN to 0 to look from beginning */
- clrbits_le32(&l2ana_reg->ana_tables.mach_data,
- VSC9953_MAC_VID_MASK | VSC9953_MAC_MACH_MASK);
- out_le32(&l2ana_reg->ana_tables.macl_data, 0);
-
- /* get entries */
- printf("%10s %17s %5s %4s\n", "EntryType", "MAC", "PORT", "VID");
- do {
- if (vsc9953_mac_table_cmd(MAC_TABLE_GET_NEXT) < 0) {
- debug("GET NEXT MAC table command failed\n");
- break;
- }
-
- val = in_le32(&l2ana_reg->ana_tables.mac_access);
-
- /* get out when an invalid entry is found */
- if (!(val & VSC9953_MAC_CMD_VALID))
- break;
-
- switch (val & VSC9953_MAC_ENTRYTYPE_MASK) {
- case VSC9953_MAC_ENTRYTYPE_NORMAL:
- printf("%10s ", "Dynamic");
- break;
- case VSC9953_MAC_ENTRYTYPE_LOCKED:
- printf("%10s ", "Static");
- break;
- case VSC9953_MAC_ENTRYTYPE_IPV4MCAST:
- printf("%10s ", "IPv4 Mcast");
- break;
- case VSC9953_MAC_ENTRYTYPE_IPV6MCAST:
- printf("%10s ", "IPv6 Mcast");
- break;
- default:
- printf("%10s ", "Unknown");
- }
-
- dest_indx = bitfield_extract_by_mask(val,
- VSC9953_MAC_DESTIDX_MASK);
-
- val = in_le32(&l2ana_reg->ana_tables.mach_data);
- vlan = bitfield_extract_by_mask(val, VSC9953_MAC_VID_MASK);
- mach = bitfield_extract_by_mask(val, VSC9953_MAC_MACH_MASK);
- macl = in_le32(&l2ana_reg->ana_tables.macl_data);
-
- printf("%02x:%02x:%02x:%02x:%02x:%02x ", (mach >> 8) & 0xff,
- mach & 0xff, (macl >> 24) & 0xff, (macl >> 16) & 0xff,
- (macl >> 8) & 0xff, macl & 0xff);
- printf("%5d ", dest_indx);
- printf("%4d\n", vlan);
- } while (1);
-
- /* set learning mode to previous value */
- if (port_no == ETHSW_CMD_PORT_ALL) {
- for (i = 0; i < VSC9953_MAX_PORTS; i++) {
- if (!rc[i] && mode[i] != PORT_LEARN_NONE)
- vsc9953_port_learn_mode_set(i, mode[i]);
- }
- } else {
- /* If administrative down, skip */
- if (!rc[port_no] && mode[port_no] != PORT_LEARN_NONE)
- vsc9953_port_learn_mode_set(port_no, mode[port_no]);
- }
-
- /* reset FDB port and VLAN FDB selection */
- clrbits_le32(&l2ana_reg->ana.anag_efil, VSC9953_AGE_PORT_EN |
- VSC9953_AGE_PORT_MASK | VSC9953_AGE_VID_EN |
- VSC9953_AGE_VID_MASK);
-}
-
-/* Add a static FDB entry */
-static int vsc9953_mac_table_add(u8 port_no, uchar mac[6], int vid)
-{
- u32 val;
- struct vsc9953_analyzer *l2ana_reg;
-
- l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET +
- VSC9953_ANA_OFFSET);
-
- val = in_le32(&l2ana_reg->ana_tables.mach_data);
- val = bitfield_replace_by_mask(val, VSC9953_MACHDATA_VID_MASK, vid) |
- (mac[0] << 8) | (mac[1] << 0);
- out_le32(&l2ana_reg->ana_tables.mach_data, val);
-
- out_le32(&l2ana_reg->ana_tables.macl_data,
- (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) |
- (mac[5] << 0));
-
- /* set on which port is the MAC address added */
- val = in_le32(&l2ana_reg->ana_tables.mac_access);
- val = bitfield_replace_by_mask(val, VSC9953_MAC_DESTIDX_MASK, port_no);
- out_le32(&l2ana_reg->ana_tables.mac_access, val);
-
- if (vsc9953_mac_table_cmd(MAC_TABLE_LEARN) < 0)
- return -1;
-
- /* check if the MAC address was indeed added */
- val = in_le32(&l2ana_reg->ana_tables.mach_data);
- val = bitfield_replace_by_mask(val, VSC9953_MACHDATA_VID_MASK, vid) |
- (mac[0] << 8) | (mac[1] << 0);
- out_le32(&l2ana_reg->ana_tables.mach_data, val);
-
- out_le32(&l2ana_reg->ana_tables.macl_data,
- (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) |
- (mac[5] << 0));
-
- if (vsc9953_mac_table_cmd(MAC_TABLE_READ) < 0)
- return -1;
-
- val = in_le32(&l2ana_reg->ana_tables.mac_access);
-
- if ((port_no != bitfield_extract_by_mask(val,
- VSC9953_MAC_DESTIDX_MASK))) {
- printf("Failed to add MAC address\n");
- return -1;
- }
- return 0;
-}
-
-/* Delete a FDB entry */
-static int vsc9953_mac_table_del(uchar mac[6], u16 vid)
-{
- u32 val;
- struct vsc9953_analyzer *l2ana_reg;
-
- l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET +
- VSC9953_ANA_OFFSET);
-
- /* check first if MAC entry is present */
- val = in_le32(&l2ana_reg->ana_tables.mach_data);
- val = bitfield_replace_by_mask(val, VSC9953_MACHDATA_VID_MASK, vid) |
- (mac[0] << 8) | (mac[1] << 0);
- out_le32(&l2ana_reg->ana_tables.mach_data, val);
-
- out_le32(&l2ana_reg->ana_tables.macl_data,
- (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) |
- (mac[5] << 0));
-
- if (vsc9953_mac_table_cmd(MAC_TABLE_LOOKUP) < 0) {
- debug("Lookup in the MAC table failed\n");
- return -1;
- }
-
- if (!(in_le32(&l2ana_reg->ana_tables.mac_access) &
- VSC9953_MAC_CMD_VALID)) {
- printf("The MAC address: %02x:%02x:%02x:%02x:%02x:%02x ",
- mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
- printf("VLAN: %d does not exist.\n", vid);
- return -1;
- }
-
- /* FDB entry found, proceed to delete */
- val = in_le32(&l2ana_reg->ana_tables.mach_data);
- val = bitfield_replace_by_mask(val, VSC9953_MACHDATA_VID_MASK, vid) |
- (mac[0] << 8) | (mac[1] << 0);
- out_le32(&l2ana_reg->ana_tables.mach_data, val);
-
- out_le32(&l2ana_reg->ana_tables.macl_data, (mac[2] << 24) |
- (mac[3] << 16) | (mac[4] << 8) | (mac[5] << 0));
-
- if (vsc9953_mac_table_cmd(MAC_TABLE_FORGET) < 0)
- return -1;
-
- /* check if the MAC entry is still in FDB */
- val = in_le32(&l2ana_reg->ana_tables.mach_data);
- val = bitfield_replace_by_mask(val, VSC9953_MACHDATA_VID_MASK, vid) |
- (mac[0] << 8) | (mac[1] << 0);
- out_le32(&l2ana_reg->ana_tables.mach_data, val);
-
- out_le32(&l2ana_reg->ana_tables.macl_data, (mac[2] << 24) |
- (mac[3] << 16) | (mac[4] << 8) | (mac[5] << 0));
-
- if (vsc9953_mac_table_cmd(MAC_TABLE_LOOKUP) < 0) {
- debug("Lookup in the MAC table failed\n");
- return -1;
- }
- if (in_le32(&l2ana_reg->ana_tables.mac_access) &
- VSC9953_MAC_CMD_VALID) {
- printf("Failed to delete MAC address\n");
- return -1;
- }
-
- return 0;
-}
-
-/* age the unlocked entries in FDB */
-static void vsc9953_mac_table_age(int port_no, int vid)
-{
- int rc[VSC9953_MAX_PORTS];
- enum port_learn_mode mode[VSC9953_MAX_PORTS];
- u32 val;
- int i;
- struct vsc9953_analyzer *l2ana_reg;
-
- l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET +
- VSC9953_ANA_OFFSET);
-
- /* set port and VID for selective aging */
- val = in_le32(&l2ana_reg->ana.anag_efil);
- if (port_no != ETHSW_CMD_PORT_ALL) {
- /* disable auto learning */
- rc[port_no] = vsc9953_port_learn_mode_get(port_no,
- &mode[port_no]);
- if (!rc[port_no] && mode[port_no] != PORT_LEARN_NONE)
- vsc9953_port_learn_mode_set(port_no, PORT_LEARN_NONE);
-
- val = bitfield_replace_by_mask(val, VSC9953_AGE_PORT_MASK,
- port_no) | VSC9953_AGE_PORT_EN;
- } else {
- /* disable auto learning on all ports */
- for (i = 0; i < VSC9953_MAX_PORTS; i++) {
- rc[i] = vsc9953_port_learn_mode_get(i, &mode[i]);
- if (!rc[i] && mode[i] != PORT_LEARN_NONE)
- vsc9953_port_learn_mode_set(i, PORT_LEARN_NONE);
- }
- }
-
- if (vid != ETHSW_CMD_VLAN_ALL) {
- val = bitfield_replace_by_mask(val, VSC9953_AGE_VID_MASK, vid) |
- VSC9953_AGE_VID_EN;
- }
- out_le32(&l2ana_reg->ana.anag_efil, val);
-
- /* age the dynamic FDB entries */
- vsc9953_mac_table_cmd(MAC_TABLE_AGE);
-
- /* clear previously set port and VID */
- clrbits_le32(&l2ana_reg->ana.anag_efil, VSC9953_AGE_PORT_EN |
- VSC9953_AGE_PORT_MASK | VSC9953_AGE_VID_EN |
- VSC9953_AGE_VID_MASK);
-
- if (port_no != ETHSW_CMD_PORT_ALL) {
- if (!rc[port_no] && mode[port_no] != PORT_LEARN_NONE)
- vsc9953_port_learn_mode_set(port_no, mode[port_no]);
- } else {
- for (i = 0; i < VSC9953_MAX_PORTS; i++) {
- if (!rc[i] && mode[i] != PORT_LEARN_NONE)
- vsc9953_port_learn_mode_set(i, mode[i]);
- }
- }
-}
-
-/* Delete all the dynamic FDB entries */
-static void vsc9953_mac_table_flush(int port, int vid)
-{
- vsc9953_mac_table_age(port, vid);
- vsc9953_mac_table_age(port, vid);
-}
-
-enum egress_vlan_tag {
- EGR_TAG_CLASS = 0,
- EGR_TAG_PVID,
-};
-
-/* Set egress tag mode for a VSC9953 port */
-static void vsc9953_port_vlan_egress_tag_set(int port_no,
- enum egress_vlan_tag mode)
-{
- struct vsc9953_rew_reg *l2rew_reg;
-
- l2rew_reg = (struct vsc9953_rew_reg *)(VSC9953_OFFSET +
- VSC9953_REW_OFFSET);
-
- switch (mode) {
- case EGR_TAG_CLASS:
- clrbits_le32(&l2rew_reg->port[port_no].port_tag_cfg,
- VSC9953_TAG_VID_PVID);
- break;
- case EGR_TAG_PVID:
- setbits_le32(&l2rew_reg->port[port_no].port_tag_cfg,
- VSC9953_TAG_VID_PVID);
- break;
- default:
- printf("Unknown egress VLAN tag mode for port %d\n", port_no);
- }
-}
-
-/* Get egress tag mode for a VSC9953 port */
-static void vsc9953_port_vlan_egress_tag_get(int port_no,
- enum egress_vlan_tag *mode)
-{
- u32 val;
- struct vsc9953_rew_reg *l2rew_reg;
-
- l2rew_reg = (struct vsc9953_rew_reg *)(VSC9953_OFFSET +
- VSC9953_REW_OFFSET);
-
- val = in_le32(&l2rew_reg->port[port_no].port_tag_cfg);
- if (val & VSC9953_TAG_VID_PVID)
- *mode = EGR_TAG_PVID;
- else
- *mode = EGR_TAG_CLASS;
-}
-
-/* VSC9953 VLAN learning modes */
-enum vlan_learning_mode {
- SHARED_VLAN_LEARNING,
- PRIVATE_VLAN_LEARNING,
-};
-
-/* Set VLAN learning mode for VSC9953 */
-static void vsc9953_vlan_learning_set(enum vlan_learning_mode lrn_mode)
-{
- struct vsc9953_analyzer *l2ana_reg;
-
- l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET +
- VSC9953_ANA_OFFSET);
-
- switch (lrn_mode) {
- case SHARED_VLAN_LEARNING:
- setbits_le32(&l2ana_reg->ana.agen_ctrl, VSC9953_FID_MASK_ALL);
- break;
- case PRIVATE_VLAN_LEARNING:
- clrbits_le32(&l2ana_reg->ana.agen_ctrl, VSC9953_FID_MASK_ALL);
- break;
- default:
- printf("Unknown VLAN learn mode\n");
- }
-}
-
-/* Get VLAN learning mode for VSC9953 */
-static int vsc9953_vlan_learning_get(enum vlan_learning_mode *lrn_mode)
-{
- u32 val;
- struct vsc9953_analyzer *l2ana_reg;
-
- l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET +
- VSC9953_ANA_OFFSET);
-
- val = in_le32(&l2ana_reg->ana.agen_ctrl);
-
- if (!(val & VSC9953_FID_MASK_ALL)) {
- *lrn_mode = PRIVATE_VLAN_LEARNING;
- } else if ((val & VSC9953_FID_MASK_ALL) == VSC9953_FID_MASK_ALL) {
- *lrn_mode = SHARED_VLAN_LEARNING;
- } else {
- printf("Unknown VLAN learning mode\n");
- return -EINVAL;
- }
-
- return 0;
-}
-
-/* Enable/disable VLAN ingress filtering on a VSC9953 port */
-static void vsc9953_port_ingress_filtering_set(int port_no, int enabled)
-{
- struct vsc9953_analyzer *l2ana_reg;
-
- l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET +
- VSC9953_ANA_OFFSET);
-
- if (enabled)
- setbits_le32(&l2ana_reg->ana.vlan_mask, 1 << port_no);
- else
- clrbits_le32(&l2ana_reg->ana.vlan_mask, 1 << port_no);
-}
-
-/* Return VLAN ingress filtering on a VSC9953 port */
-static int vsc9953_port_ingress_filtering_get(int port_no)
-{
- u32 val;
- struct vsc9953_analyzer *l2ana_reg;
-
- l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET +
- VSC9953_ANA_OFFSET);
-
- val = in_le32(&l2ana_reg->ana.vlan_mask);
- return !!(val & (1 << port_no));
-}
-
-/* Get the aggregation group of a port */
-static int vsc9953_port_aggr_grp_get(int port_no, int *aggr_grp)
-{
- u32 val;
- struct vsc9953_analyzer *l2ana_reg;
-
- if (!VSC9953_PORT_CHECK(port_no))
- return -EINVAL;
-
- l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET +
- VSC9953_ANA_OFFSET);
-
- val = in_le32(&l2ana_reg->port[port_no].port_cfg);
- *aggr_grp = bitfield_extract_by_mask(val,
- VSC9953_PORT_CFG_PORTID_MASK);
-
- return 0;
-}
-
-static void vsc9953_aggr_grp_members_get(int aggr_grp,
- u8 aggr_membr[VSC9953_MAX_PORTS])
-{
- int port_no;
- int aggr_membr_grp;
-
- for (port_no = 0; port_no < VSC9953_MAX_PORTS; port_no++) {
- aggr_membr[port_no] = 0;
-
- if (vsc9953_port_aggr_grp_get(port_no, &aggr_membr_grp))
- continue;
-
- if (aggr_grp == aggr_membr_grp)
- aggr_membr[port_no] = 1;
- }
-}
-
-static void vsc9953_update_dest_members_masks(int port_no, u32 membr_bitfld_old,
- u32 membr_bitfld_new)
-{
- int i;
- u32 pgid;
- struct vsc9953_analyzer *l2ana_reg;
-
- l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET +
- VSC9953_ANA_OFFSET);
-
- /*
- * NOTE: Only the unicast destination masks are updated, since
- * we do not support for now Layer-2 multicast entries
- */
- for (i = 0; i < VSC9953_MAX_PORTS; i++) {
- if (i == port_no) {
- clrsetbits_le32(&l2ana_reg->port_id_tbl.port_grp_id[i],
- VSC9953_PGID_PORT_MASK,
- membr_bitfld_new);
- continue;
- }
-
- pgid = in_le32(&l2ana_reg->port_id_tbl.port_grp_id[i]);
- if ((u32)(1 << i) & membr_bitfld_old & VSC9953_PGID_PORT_MASK)
- pgid &= ~((u32)(1 << port_no));
- if ((u32)(1 << i) & membr_bitfld_new & VSC9953_PGID_PORT_MASK)
- pgid |= ((u32)(1 << port_no));
-
- out_le32(&l2ana_reg->port_id_tbl.port_grp_id[i], pgid);
- }
-}
-
-static void vsc9953_update_source_members_masks(int port_no,
- u32 membr_bitfld_old,
- u32 membr_bitfld_new)
-{
- int i;
- int index;
- u32 pgid;
- struct vsc9953_analyzer *l2ana_reg;
-
- l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET +
- VSC9953_ANA_OFFSET);
-
- for (i = 0; i < VSC9953_MAX_PORTS + 1; i++) {
- index = PGID_SRC_START + i;
- pgid = in_le32(&l2ana_reg->port_id_tbl.port_grp_id[index]);
- if (i == port_no) {
- pgid = (pgid | VSC9953_PGID_PORT_MASK) &
- ~membr_bitfld_new;
- out_le32(&l2ana_reg->port_id_tbl.port_grp_id[index],
- pgid);
- continue;
- }
-
- if ((u32)(1 << i) & membr_bitfld_old & VSC9953_PGID_PORT_MASK)
- pgid |= (u32)(1 << port_no);
-
- if ((u32)(1 << i) & membr_bitfld_new & VSC9953_PGID_PORT_MASK)
- pgid &= ~(u32)(1 << port_no);
- out_le32(&l2ana_reg->port_id_tbl.port_grp_id[index], pgid);
- }
-}
-
-static u32 vsc9953_aggr_mask_get_next(u32 aggr_mask, u32 member_bitfield)
-{
- if (!member_bitfield)
- return 0;
-
- if (!(aggr_mask & VSC9953_PGID_PORT_MASK))
- aggr_mask = 1;
- else
- aggr_mask <<= 1;
-
- while (!(aggr_mask & member_bitfield)) {
- aggr_mask <<= 1;
- if (!(aggr_mask & VSC9953_PGID_PORT_MASK))
- aggr_mask = 1;
- }
-
- return aggr_mask;
-}
-
-static void vsc9953_update_aggr_members_masks(int port_no, u32 membr_bitfld_old,
- u32 membr_bitfld_new)
-{
- int i;
- u32 pgid;
- u32 aggr_mask_old = 0;
- u32 aggr_mask_new = 0;
- struct vsc9953_analyzer *l2ana_reg;
-
- l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET +
- VSC9953_ANA_OFFSET);
-
- /* Update all the PGID aggregation masks */
- for (i = PGID_AGGR_START; i < PGID_SRC_START; i++) {
- pgid = in_le32(&l2ana_reg->port_id_tbl.port_grp_id[i]);
-
- aggr_mask_old = vsc9953_aggr_mask_get_next(aggr_mask_old,
- membr_bitfld_old);
- pgid = (pgid & ~membr_bitfld_old) | aggr_mask_old;
-
- aggr_mask_new = vsc9953_aggr_mask_get_next(aggr_mask_new,
- membr_bitfld_new);
- pgid = (pgid & ~membr_bitfld_new) | aggr_mask_new;
-
- out_le32(&l2ana_reg->port_id_tbl.port_grp_id[i], pgid);
- }
-}
-
-static u32 vsc9953_aggr_membr_bitfield_get(u8 member[VSC9953_MAX_PORTS])
-{
- int i;
- u32 member_bitfield = 0;
-
- for (i = 0; i < VSC9953_MAX_PORTS; i++) {
- if (member[i])
- member_bitfield |= 1 << i;
- }
- member_bitfield &= VSC9953_PGID_PORT_MASK;
-
- return member_bitfield;
-}
-
-static void vsc9953_update_members_masks(int port_no,
- u8 member_old[VSC9953_MAX_PORTS],
- u8 member_new[VSC9953_MAX_PORTS])
-{
- u32 membr_bitfld_old = vsc9953_aggr_membr_bitfield_get(member_old);
- u32 membr_bitfld_new = vsc9953_aggr_membr_bitfield_get(member_new);
-
- vsc9953_update_dest_members_masks(port_no, membr_bitfld_old,
- membr_bitfld_new);
- vsc9953_update_source_members_masks(port_no, membr_bitfld_old,
- membr_bitfld_new);
- vsc9953_update_aggr_members_masks(port_no, membr_bitfld_old,
- membr_bitfld_new);
-}
-
-/* Set the aggregation group of a port */
-static int vsc9953_port_aggr_grp_set(int port_no, int aggr_grp)
-{
- u8 aggr_membr_old[VSC9953_MAX_PORTS];
- u8 aggr_membr_new[VSC9953_MAX_PORTS];
- int rc;
- int aggr_grp_old;
- u32 val;
- struct vsc9953_analyzer *l2ana_reg;
-
- if (!VSC9953_PORT_CHECK(port_no) || !VSC9953_PORT_CHECK(aggr_grp))
- return -EINVAL;
-
- l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET +
- VSC9953_ANA_OFFSET);
-
- rc = vsc9953_port_aggr_grp_get(port_no, &aggr_grp_old);
- if (rc)
- return rc;
-
- /* get all the members of the old aggregation group */
- vsc9953_aggr_grp_members_get(aggr_grp_old, aggr_membr_old);
-
- /* get all the members of the same aggregation group */
- vsc9953_aggr_grp_members_get(aggr_grp, aggr_membr_new);
-
- /* add current port as member to the new aggregation group */
- aggr_membr_old[port_no] = 0;
- aggr_membr_new[port_no] = 1;
-
- /* update masks */
- vsc9953_update_members_masks(port_no, aggr_membr_old, aggr_membr_new);
-
- /* Change logical port number */
- val = in_le32(&l2ana_reg->port[port_no].port_cfg);
- val = bitfield_replace_by_mask(val,
- VSC9953_PORT_CFG_PORTID_MASK, aggr_grp);
- out_le32(&l2ana_reg->port[port_no].port_cfg, val);
-
- return 0;
-}
-
-static int vsc9953_port_status_key_func(struct ethsw_command_def *parsed_cmd)
-{
- int i;
- u8 enabled;
-
- /* Last keyword should tell us if we should enable/disable the port */
- if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] ==
- ethsw_id_enable)
- enabled = 1;
- else if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] ==
- ethsw_id_disable)
- enabled = 0;
- else
- return CMD_RET_USAGE;
-
- if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) {
- if (!VSC9953_PORT_CHECK(parsed_cmd->port)) {
- printf("Invalid port number: %d\n", parsed_cmd->port);
- return CMD_RET_FAILURE;
- }
- vsc9953_port_status_set(parsed_cmd->port, enabled);
- } else {
- for (i = 0; i < VSC9953_MAX_PORTS; i++)
- vsc9953_port_status_set(i, enabled);
- }
-
- return CMD_RET_SUCCESS;
-}
-
-static int vsc9953_port_config_key_func(struct ethsw_command_def *parsed_cmd)
-{
- int i;
-
- if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) {
- if (!VSC9953_PORT_CHECK(parsed_cmd->port)) {
- printf("Invalid port number: %d\n", parsed_cmd->port);
- return CMD_RET_FAILURE;
- }
- vsc9953_phy_autoneg(parsed_cmd->port);
- printf("%8s %8s %8s %8s %8s\n",
- "Port", "Status", "Link", "Speed",
- "Duplex");
- vsc9953_port_config_show(parsed_cmd->port);
-
- } else {
- for (i = 0; i < VSC9953_MAX_PORTS; i++)
- vsc9953_phy_autoneg(i);
- printf("%8s %8s %8s %8s %8s\n",
- "Port", "Status", "Link", "Speed", "Duplex");
- for (i = 0; i < VSC9953_MAX_PORTS; i++)
- vsc9953_port_config_show(i);
- }
-
- return CMD_RET_SUCCESS;
-}
-
-static int vsc9953_port_stats_key_func(struct ethsw_command_def *parsed_cmd)
-{
- int i;
-
- if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) {
- if (!VSC9953_PORT_CHECK(parsed_cmd->port)) {
- printf("Invalid port number: %d\n", parsed_cmd->port);
- return CMD_RET_FAILURE;
- }
- vsc9953_port_statistics_show(parsed_cmd->port);
- } else {
- for (i = 0; i < VSC9953_MAX_PORTS; i++)
- vsc9953_port_statistics_show(i);
- }
-
- return CMD_RET_SUCCESS;
-}
-
-static int vsc9953_port_stats_clear_key_func(struct ethsw_command_def
- *parsed_cmd)
-{
- int i;
-
- if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) {
- if (!VSC9953_PORT_CHECK(parsed_cmd->port)) {
- printf("Invalid port number: %d\n", parsed_cmd->port);
- return CMD_RET_FAILURE;
- }
- vsc9953_port_statistics_clear(parsed_cmd->port);
- } else {
- for (i = 0; i < VSC9953_MAX_PORTS; i++)
- vsc9953_port_statistics_clear(i);
- }
-
- return CMD_RET_SUCCESS;
-}
-
-static int vsc9953_learn_show_key_func(struct ethsw_command_def *parsed_cmd)
-{
- int i;
- enum port_learn_mode mode;
-
- if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) {
- if (!VSC9953_PORT_CHECK(parsed_cmd->port)) {
- printf("Invalid port number: %d\n", parsed_cmd->port);
- return CMD_RET_FAILURE;
- }
- if (vsc9953_port_learn_mode_get(parsed_cmd->port, &mode))
- return CMD_RET_FAILURE;
- printf("%7s %11s\n", "Port", "Learn mode");
- switch (mode) {
- case PORT_LEARN_NONE:
- printf("%7d %11s\n", parsed_cmd->port, "disable");
- break;
- case PORT_LEARN_AUTO:
- printf("%7d %11s\n", parsed_cmd->port, "auto");
- break;
- default:
- printf("%7d %11s\n", parsed_cmd->port, "-");
- }
- } else {
- printf("%7s %11s\n", "Port", "Learn mode");
- for (i = 0; i < VSC9953_MAX_PORTS; i++) {
- if (vsc9953_port_learn_mode_get(i, &mode))
- continue;
- switch (mode) {
- case PORT_LEARN_NONE:
- printf("%7d %11s\n", i, "disable");
- break;
- case PORT_LEARN_AUTO:
- printf("%7d %11s\n", i, "auto");
- break;
- default:
- printf("%7d %11s\n", i, "-");
- }
- }
- }
-
- return CMD_RET_SUCCESS;
-}
-
-static int vsc9953_learn_set_key_func(struct ethsw_command_def *parsed_cmd)
-{
- int i;
- enum port_learn_mode mode;
-
- /* Last keyword should tell us the learn mode */
- if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] ==
- ethsw_id_auto)
- mode = PORT_LEARN_AUTO;
- else if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] ==
- ethsw_id_disable)
- mode = PORT_LEARN_NONE;
- else
- return CMD_RET_USAGE;
-
- if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) {
- if (!VSC9953_PORT_CHECK(parsed_cmd->port)) {
- printf("Invalid port number: %d\n", parsed_cmd->port);
- return CMD_RET_FAILURE;
- }
- vsc9953_port_learn_mode_set(parsed_cmd->port, mode);
- } else {
- for (i = 0; i < VSC9953_MAX_PORTS; i++)
- vsc9953_port_learn_mode_set(i, mode);
- }
-
- return CMD_RET_SUCCESS;
-}
-
-static int vsc9953_fdb_show_key_func(struct ethsw_command_def *parsed_cmd)
-{
- if (parsed_cmd->port != ETHSW_CMD_PORT_ALL &&
- !VSC9953_PORT_CHECK(parsed_cmd->port)) {
- printf("Invalid port number: %d\n", parsed_cmd->port);
- return CMD_RET_FAILURE;
- }
-
- if (parsed_cmd->vid != ETHSW_CMD_VLAN_ALL &&
- !VSC9953_VLAN_CHECK(parsed_cmd->vid)) {
- printf("Invalid VID number: %d\n", parsed_cmd->vid);
- return CMD_RET_FAILURE;
- }
-
- vsc9953_mac_table_show(parsed_cmd->port, parsed_cmd->vid);
-
- return CMD_RET_SUCCESS;
-}
-
-static int vsc9953_fdb_flush_key_func(struct ethsw_command_def *parsed_cmd)
-{
- if (parsed_cmd->port != ETHSW_CMD_PORT_ALL &&
- !VSC9953_PORT_CHECK(parsed_cmd->port)) {
- printf("Invalid port number: %d\n", parsed_cmd->port);
- return CMD_RET_FAILURE;
- }
-
- if (parsed_cmd->vid != ETHSW_CMD_VLAN_ALL &&
- !VSC9953_VLAN_CHECK(parsed_cmd->vid)) {
- printf("Invalid VID number: %d\n", parsed_cmd->vid);
- return CMD_RET_FAILURE;
- }
-
- vsc9953_mac_table_flush(parsed_cmd->port, parsed_cmd->vid);
-
- return CMD_RET_SUCCESS;
-}
-
-static int vsc9953_fdb_entry_add_key_func(struct ethsw_command_def *parsed_cmd)
-{
- int vid;
-
- /* a port number must be present */
- if (parsed_cmd->port == ETHSW_CMD_PORT_ALL) {
- printf("Please specify a port\n");
- return CMD_RET_FAILURE;
- }
-
- if (!VSC9953_PORT_CHECK(parsed_cmd->port)) {
- printf("Invalid port number: %d\n", parsed_cmd->port);
- return CMD_RET_FAILURE;
- }
-
- /* Use VLAN 1 if VID is not set */
- vid = (parsed_cmd->vid == ETHSW_CMD_VLAN_ALL ? 1 : parsed_cmd->vid);
-
- if (!VSC9953_VLAN_CHECK(vid)) {
- printf("Invalid VID number: %d\n", vid);
- return CMD_RET_FAILURE;
- }
-
- if (vsc9953_mac_table_add(parsed_cmd->port, parsed_cmd->ethaddr, vid))
- return CMD_RET_FAILURE;
-
- return CMD_RET_SUCCESS;
-}
-
-static int vsc9953_fdb_entry_del_key_func(struct ethsw_command_def *parsed_cmd)
-{
- int vid;
-
- /* Use VLAN 1 if VID is not set */
- vid = (parsed_cmd->vid == ETHSW_CMD_VLAN_ALL ? 1 : parsed_cmd->vid);
-
- if (!VSC9953_VLAN_CHECK(vid)) {
- printf("Invalid VID number: %d\n", vid);
- return CMD_RET_FAILURE;
- }
-
- if (vsc9953_mac_table_del(parsed_cmd->ethaddr, vid))
- return CMD_RET_FAILURE;
-
- return CMD_RET_SUCCESS;
-}
-
-static int vsc9953_pvid_show_key_func(struct ethsw_command_def *parsed_cmd)
-{
- int i;
- int pvid;
-
- if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) {
- if (!VSC9953_PORT_CHECK(parsed_cmd->port)) {
- printf("Invalid port number: %d\n", parsed_cmd->port);
- return CMD_RET_FAILURE;
- }
-
- if (vsc9953_port_vlan_pvid_get(parsed_cmd->port, &pvid))
- return CMD_RET_FAILURE;
- printf("%7s %7s\n", "Port", "PVID");
- printf("%7d %7d\n", parsed_cmd->port, pvid);
- } else {
- printf("%7s %7s\n", "Port", "PVID");
- for (i = 0; i < VSC9953_MAX_PORTS; i++) {
- if (vsc9953_port_vlan_pvid_get(i, &pvid))
- continue;
- printf("%7d %7d\n", i, pvid);
- }
- }
-
- return CMD_RET_SUCCESS;
-}
-
-static int vsc9953_pvid_set_key_func(struct ethsw_command_def *parsed_cmd)
-{
- /* PVID number should be set in parsed_cmd->vid */
- if (parsed_cmd->vid == ETHSW_CMD_VLAN_ALL) {
- printf("Please set a pvid value\n");
- return CMD_RET_FAILURE;
- }
-
- if (!VSC9953_VLAN_CHECK(parsed_cmd->vid)) {
- printf("Invalid VID number: %d\n", parsed_cmd->vid);
- return CMD_RET_FAILURE;
- }
-
- if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) {
- if (!VSC9953_PORT_CHECK(parsed_cmd->port)) {
- printf("Invalid port number: %d\n", parsed_cmd->port);
- return CMD_RET_FAILURE;
- }
- vsc9953_port_vlan_pvid_set(parsed_cmd->port, parsed_cmd->vid);
- } else {
- vsc9953_port_all_vlan_pvid_set(parsed_cmd->vid);
- }
-
- return CMD_RET_SUCCESS;
-}
-
-static int vsc9953_vlan_show_key_func(struct ethsw_command_def *parsed_cmd)
-{
- int i;
-
- if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) {
- if (!VSC9953_PORT_CHECK(parsed_cmd->port)) {
- printf("Invalid port number: %d\n", parsed_cmd->port);
- return CMD_RET_FAILURE;
- }
- vsc9953_vlan_membership_show(parsed_cmd->port);
- } else {
- for (i = 0; i < VSC9953_MAX_PORTS; i++)
- vsc9953_vlan_membership_show(i);
- }
-
- return CMD_RET_SUCCESS;
-}
-
-static int vsc9953_vlan_set_key_func(struct ethsw_command_def *parsed_cmd)
-{
- int i;
- int add;
-
- /* VLAN should be set in parsed_cmd->vid */
- if (parsed_cmd->vid == ETHSW_CMD_VLAN_ALL) {
- printf("Please set a vlan value\n");
- return CMD_RET_FAILURE;
- }
-
- if (!VSC9953_VLAN_CHECK(parsed_cmd->vid)) {
- printf("Invalid VID number: %d\n", parsed_cmd->vid);
- return CMD_RET_FAILURE;
- }
-
- /* keywords add/delete should be the last but one in array */
- if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 2] ==
- ethsw_id_add)
- add = 1;
- else if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 2] ==
- ethsw_id_del)
- add = 0;
- else
- return CMD_RET_USAGE;
-
- if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) {
- if (!VSC9953_PORT_CHECK(parsed_cmd->port)) {
- printf("Invalid port number: %d\n", parsed_cmd->port);
- return CMD_RET_FAILURE;
- }
- vsc9953_vlan_table_membership_set(parsed_cmd->vid,
- parsed_cmd->port, add);
- } else {
- for (i = 0; i < VSC9953_MAX_PORTS; i++)
- vsc9953_vlan_table_membership_set(parsed_cmd->vid, i,
- add);
- }
-
- return CMD_RET_SUCCESS;
-}
-static int vsc9953_port_untag_show_key_func(
- struct ethsw_command_def *parsed_cmd)
-{
- int i;
-
- printf("%7s\t%17s\n", "Port", "Untag");
- if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) {
- if (!VSC9953_PORT_CHECK(parsed_cmd->port)) {
- printf("Invalid port number: %d\n", parsed_cmd->port);
- return CMD_RET_FAILURE;
- }
- vsc9953_port_vlan_egr_untag_show(parsed_cmd->port);
- } else {
- for (i = 0; i < VSC9953_MAX_PORTS; i++)
- vsc9953_port_vlan_egr_untag_show(i);
- }
-
- return CMD_RET_SUCCESS;
-}
-
-static int vsc9953_port_untag_set_key_func(struct ethsw_command_def *parsed_cmd)
-{
- int i;
- enum egress_untag_mode mode;
-
- /* keywords for the untagged mode are the last in the array */
- if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] ==
- ethsw_id_all)
- mode = EGRESS_UNTAG_ALL;
- else if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] ==
- ethsw_id_none)
- mode = EGRESS_UNTAG_NONE;
- else if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] ==
- ethsw_id_pvid)
- mode = EGRESS_UNTAG_PVID_AND_ZERO;
- else
- return CMD_RET_USAGE;
-
- if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) {
- if (!VSC9953_PORT_CHECK(parsed_cmd->port)) {
- printf("Invalid port number: %d\n", parsed_cmd->port);
- return CMD_RET_FAILURE;
- }
- vsc9953_port_vlan_egr_untag_set(parsed_cmd->port, mode);
- } else {
- for (i = 0; i < VSC9953_MAX_PORTS; i++)
- vsc9953_port_vlan_egr_untag_set(i, mode);
- }
-
- return CMD_RET_SUCCESS;
-}
-
-static int vsc9953_egr_vlan_tag_show_key_func(
- struct ethsw_command_def *parsed_cmd)
-{
- int i;
- enum egress_vlan_tag mode;
-
- if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) {
- if (!VSC9953_PORT_CHECK(parsed_cmd->port)) {
- printf("Invalid port number: %d\n", parsed_cmd->port);
- return CMD_RET_FAILURE;
- }
- vsc9953_port_vlan_egress_tag_get(parsed_cmd->port, &mode);
- printf("%7s\t%12s\n", "Port", "Egress VID");
- printf("%7d\t", parsed_cmd->port);
- switch (mode) {
- case EGR_TAG_CLASS:
- printf("%12s\n", "classified");
- break;
- case EGR_TAG_PVID:
- printf("%12s\n", "pvid");
- break;
- default:
- printf("%12s\n", "-");
- }
- } else {
- printf("%7s\t%12s\n", "Port", "Egress VID");
- for (i = 0; i < VSC9953_MAX_PORTS; i++) {
- vsc9953_port_vlan_egress_tag_get(i, &mode);
- switch (mode) {
- case EGR_TAG_CLASS:
- printf("%7d\t%12s\n", i, "classified");
- break;
- case EGR_TAG_PVID:
- printf("%7d\t%12s\n", i, "pvid");
- break;
- default:
- printf("%7d\t%12s\n", i, "-");
- }
- }
- }
-
- return CMD_RET_SUCCESS;
-}
-
-static int vsc9953_egr_vlan_tag_set_key_func(
- struct ethsw_command_def *parsed_cmd)
-{
- int i;
- enum egress_vlan_tag mode;
-
- /* keywords for the egress vlan tag mode are the last in the array */
- if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] ==
- ethsw_id_pvid)
- mode = EGR_TAG_PVID;
- else if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] ==
- ethsw_id_classified)
- mode = EGR_TAG_CLASS;
- else
- return CMD_RET_USAGE;
-
- if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) {
- if (!VSC9953_PORT_CHECK(parsed_cmd->port)) {
- printf("Invalid port number: %d\n", parsed_cmd->port);
- return CMD_RET_FAILURE;
- }
- vsc9953_port_vlan_egress_tag_set(parsed_cmd->port, mode);
- } else {
- for (i = 0; i < VSC9953_MAX_PORTS; i++)
- vsc9953_port_vlan_egress_tag_set(i, mode);
- }
-
- return CMD_RET_SUCCESS;
-}
-
-static int vsc9953_vlan_learn_show_key_func(
- struct ethsw_command_def *parsed_cmd)
-{
- int rc;
- enum vlan_learning_mode mode;
-
- rc = vsc9953_vlan_learning_get(&mode);
- if (rc)
- return CMD_RET_FAILURE;
-
- switch (mode) {
- case SHARED_VLAN_LEARNING:
- printf("VLAN learning mode: shared\n");
- break;
- case PRIVATE_VLAN_LEARNING:
- printf("VLAN learning mode: private\n");
- break;
- default:
- printf("Unknown VLAN learning mode\n");
- rc = CMD_RET_FAILURE;
- }
-
- return CMD_RET_SUCCESS;
-}
-
-static int vsc9953_vlan_learn_set_key_func(struct ethsw_command_def *parsed_cmd)
-{
- enum vlan_learning_mode mode;
-
- /* keywords for shared/private are the last in the array */
- if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] ==
- ethsw_id_shared)
- mode = SHARED_VLAN_LEARNING;
- else if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] ==
- ethsw_id_private)
- mode = PRIVATE_VLAN_LEARNING;
- else
- return CMD_RET_USAGE;
-
- vsc9953_vlan_learning_set(mode);
-
- return CMD_RET_SUCCESS;
-}
-
-static int vsc9953_ingr_fltr_show_key_func(struct ethsw_command_def *parsed_cmd)
-{
- int i;
- int enabled;
-
- printf("%7s\t%18s\n", "Port", "Ingress filtering");
- if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) {
- if (!VSC9953_PORT_CHECK(parsed_cmd->port)) {
- printf("Invalid port number: %d\n", parsed_cmd->port);
- return CMD_RET_FAILURE;
- }
- enabled = vsc9953_port_ingress_filtering_get(parsed_cmd->port);
- printf("%7d\t%18s\n", parsed_cmd->port, enabled ? "enable" :
- "disable");
- } else {
- for (i = 0; i < VSC9953_MAX_PORTS; i++) {
- enabled = vsc9953_port_ingress_filtering_get(i);
- printf("%7d\t%18s\n", parsed_cmd->port, enabled ?
- "enable" :
- "disable");
- }
- }
-
- return CMD_RET_SUCCESS;
-}
-
-static int vsc9953_ingr_fltr_set_key_func(struct ethsw_command_def *parsed_cmd)
-{
- int i;
- int enable;
-
- /* keywords for enabling/disabling ingress filtering
- * are the last in the array
- */
- if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] ==
- ethsw_id_enable)
- enable = 1;
- else if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] ==
- ethsw_id_disable)
- enable = 0;
- else
- return CMD_RET_USAGE;
-
- if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) {
- if (!VSC9953_PORT_CHECK(parsed_cmd->port)) {
- printf("Invalid port number: %d\n", parsed_cmd->port);
- return CMD_RET_FAILURE;
- }
- vsc9953_port_ingress_filtering_set(parsed_cmd->port, enable);
- } else {
- for (i = 0; i < VSC9953_MAX_PORTS; i++)
- vsc9953_port_ingress_filtering_set(i, enable);
- }
-
- return CMD_RET_SUCCESS;
-}
-
-static int vsc9953_port_aggr_show_key_func(struct ethsw_command_def *parsed_cmd)
-{
- int i;
- int aggr_grp;
-
- if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) {
- if (!VSC9953_PORT_CHECK(parsed_cmd->port)) {
- printf("Invalid port number: %d\n", parsed_cmd->port);
- return CMD_RET_FAILURE;
- }
-
- if (vsc9953_port_aggr_grp_get(parsed_cmd->port, &aggr_grp))
- return CMD_RET_FAILURE;
- printf("%7s %10s\n", "Port", "Aggr grp");
- printf("%7d %10d\n", parsed_cmd->port, aggr_grp);
- } else {
- printf("%7s %10s\n", "Port", "Aggr grp");
- for (i = 0; i < VSC9953_MAX_PORTS; i++) {
- if (vsc9953_port_aggr_grp_get(i, &aggr_grp))
- continue;
- printf("%7d %10d\n", i, aggr_grp);
- }
- }
-
- return CMD_RET_SUCCESS;
-}
-
-static int vsc9953_port_aggr_set_key_func(struct ethsw_command_def *parsed_cmd)
-{
- int i;
-
- /* Aggregation group number should be set in parsed_cmd->aggr_grp */
- if (parsed_cmd->aggr_grp == ETHSW_CMD_AGGR_GRP_NONE) {
- printf("Please set an aggregation group value\n");
- return CMD_RET_FAILURE;
- }
-
- if (!VSC9953_PORT_CHECK(parsed_cmd->aggr_grp)) {
- printf("Invalid aggregation group number: %d\n",
- parsed_cmd->aggr_grp);
- return CMD_RET_FAILURE;
- }
-
- if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) {
- if (!VSC9953_PORT_CHECK(parsed_cmd->port)) {
- printf("Invalid port number: %d\n", parsed_cmd->port);
- return CMD_RET_FAILURE;
- }
- if (vsc9953_port_aggr_grp_set(parsed_cmd->port,
- parsed_cmd->aggr_grp)) {
- printf("Port %d: failed to set aggr group %d\n",
- parsed_cmd->port, parsed_cmd->aggr_grp);
- }
- } else {
- for (i = 0; i < VSC9953_MAX_PORTS; i++) {
- if (vsc9953_port_aggr_grp_set(i,
- parsed_cmd->aggr_grp)) {
- printf("Port %d: failed to set aggr group %d\n",
- i, parsed_cmd->aggr_grp);
- }
- }
- }
-
- return CMD_RET_SUCCESS;
-}
-
-static struct ethsw_command_func vsc9953_cmd_func = {
- .ethsw_name = "L2 Switch VSC9953",
- .port_enable = &vsc9953_port_status_key_func,
- .port_disable = &vsc9953_port_status_key_func,
- .port_show = &vsc9953_port_config_key_func,
- .port_stats = &vsc9953_port_stats_key_func,
- .port_stats_clear = &vsc9953_port_stats_clear_key_func,
- .port_learn = &vsc9953_learn_set_key_func,
- .port_learn_show = &vsc9953_learn_show_key_func,
- .fdb_show = &vsc9953_fdb_show_key_func,
- .fdb_flush = &vsc9953_fdb_flush_key_func,
- .fdb_entry_add = &vsc9953_fdb_entry_add_key_func,
- .fdb_entry_del = &vsc9953_fdb_entry_del_key_func,
- .pvid_show = &vsc9953_pvid_show_key_func,
- .pvid_set = &vsc9953_pvid_set_key_func,
- .vlan_show = &vsc9953_vlan_show_key_func,
- .vlan_set = &vsc9953_vlan_set_key_func,
- .port_untag_show = &vsc9953_port_untag_show_key_func,
- .port_untag_set = &vsc9953_port_untag_set_key_func,
- .port_egr_vlan_show = &vsc9953_egr_vlan_tag_show_key_func,
- .port_egr_vlan_set = &vsc9953_egr_vlan_tag_set_key_func,
- .vlan_learn_show = &vsc9953_vlan_learn_show_key_func,
- .vlan_learn_set = &vsc9953_vlan_learn_set_key_func,
- .port_ingr_filt_show = &vsc9953_ingr_fltr_show_key_func,
- .port_ingr_filt_set = &vsc9953_ingr_fltr_set_key_func,
- .port_aggr_show = &vsc9953_port_aggr_show_key_func,
- .port_aggr_set = &vsc9953_port_aggr_set_key_func,
-};
-
-#endif /* CONFIG_CMD_ETHSW */
-
-/*****************************************************************************
-At startup, the default configuration would be:
- - HW learning enabled on all ports; (HW default)
- - All ports are in VLAN 1;
- - All ports are VLAN aware;
- - All ports have POP_COUNT 1;
- - All ports have PVID 1;
- - All ports have TPID 0x8100; (HW default)
- - All ports tag frames classified to all VLANs that are not PVID;
-*****************************************************************************/
-void vsc9953_default_configuration(void)
-{
- int i;
-
- if (vsc9953_autoage_time_set(VSC9953_DEFAULT_AGE_TIME))
- debug("VSC9953: failed to set AGE time to %d\n",
- VSC9953_DEFAULT_AGE_TIME);
-
- for (i = 0; i < VSC9953_MAX_VLAN; i++)
- vsc9953_vlan_table_membership_all_set(i, 0);
- vsc9953_port_all_vlan_aware_set(1);
- vsc9953_port_all_vlan_pvid_set(1);
- vsc9953_port_all_vlan_poncnt_set(1);
- vsc9953_vlan_table_membership_all_set(1, 1);
- vsc9953_vlan_ingr_fltr_learn_drop(1);
- vsc9953_port_all_vlan_egress_untagged_set(EGRESS_UNTAG_PVID_AND_ZERO);
- if (vsc9953_aggr_code_set(AGGR_CODE_ALL))
- debug("VSC9953: failed to set default aggregation code mode\n");
-}
-
-static void vcap_entry2cache_init(u32 target, u32 entry_words)
-{
- int i;
-
- for (i = 0; i < entry_words; i++) {
- out_le32((unsigned int *)(VSC9953_OFFSET +
- VSC9953_VCAP_CACHE_ENTRY_DAT(target, i)), 0x00);
- out_le32((unsigned int *)(VSC9953_OFFSET +
- VSC9953_VCAP_CACHE_MASK_DAT(target, i)), 0xFF);
- }
-
- out_le32((unsigned int *)(VSC9953_OFFSET +
- VSC9953_VCAP_CACHE_TG_DAT(target)), 0x00);
- out_le32((unsigned int *)(VSC9953_OFFSET +
- VSC9953_VCAP_CFG_MV_CFG(target)),
- VSC9953_VCAP_CFG_MV_CFG_SIZE(entry_words));
-}
-
-static void vcap_action2cache_init(u32 target, u32 action_words,
- u32 counter_words)
-{
- int i;
-
- for (i = 0; i < action_words; i++)
- out_le32((unsigned int *)(VSC9953_OFFSET +
- VSC9953_VCAP_CACHE_ACTION_DAT(target, i)), 0x00);
-
- for (i = 0; i < counter_words; i++)
- out_le32((unsigned int *)(VSC9953_OFFSET +
- VSC9953_VCAP_CACHE_CNT_DAT(target, i)), 0x00);
-}
-
-static int vcap_cmd(u32 target, u16 ix, int cmd, int sel, int entry_count)
-{
- u32 tgt = target;
- u32 value = (VSC9953_VCAP_UPDATE_CTRL_UPDATE_CMD(cmd) |
- VSC9953_VCAP_UPDATE_CTRL_UPDATE_ADDR(ix) |
- VSC9953_VCAP_UPDATE_CTRL_UPDATE_SHOT);
-
- if ((sel & TCAM_SEL_ENTRY) && ix >= entry_count)
- return CMD_RET_FAILURE;
-
- if (!(sel & TCAM_SEL_ENTRY))
- value |= VSC9953_VCAP_UPDATE_CTRL_UPDATE_ENTRY_DIS;
-
- if (!(sel & TCAM_SEL_ACTION))
- value |= VSC9953_VCAP_UPDATE_CTRL_UPDATE_ACTION_DIS;
-
- if (!(sel & TCAM_SEL_COUNTER))
- value |= VSC9953_VCAP_UPDATE_CTRL_UPDATE_CNT_DIS;
-
- out_le32((unsigned int *)(VSC9953_OFFSET +
- VSC9953_VCAP_CFG_UPDATE_CTRL(tgt)), value);
-
- do {
- value = in_le32((unsigned int *)(VSC9953_OFFSET +
- VSC9953_VCAP_CFG_UPDATE_CTRL(tgt)));
-
- } while (value & VSC9953_VCAP_UPDATE_CTRL_UPDATE_SHOT);
-
- return CMD_RET_SUCCESS;
-}
-
-static void vsc9953_vcap_init(void)
-{
- u32 tgt = VSC9953_ES0;
- int cmd_ret;
-
- /* write entries */
- vcap_entry2cache_init(tgt, ENTRY_WORDS_ES0);
- cmd_ret = vcap_cmd(tgt, 0, TCAM_CMD_INITIALIZE, TCAM_SEL_ENTRY,
- ENTRY_WORDS_ES0);
- if (cmd_ret != CMD_RET_SUCCESS)
- debug("VSC9953:%d invalid TCAM_SEL_ENTRY\n",
- __LINE__);
-
- /* write actions and counters */
- vcap_action2cache_init(tgt, BITS_TO_DWORD(ES0_ACT_WIDTH),
- BITS_TO_DWORD(ES0_CNT_WIDTH));
- out_le32((unsigned int *)(VSC9953_OFFSET +
- VSC9953_VCAP_CFG_MV_CFG(tgt)),
- VSC9953_VCAP_CFG_MV_CFG_SIZE(ES0_ACT_COUNT));
- cmd_ret = vcap_cmd(tgt, 0, TCAM_CMD_INITIALIZE,
- TCAM_SEL_ACTION | TCAM_SEL_COUNTER, ENTRY_WORDS_ES0);
- if (cmd_ret != CMD_RET_SUCCESS)
- debug("VSC9953:%d invalid TCAM_SEL_ACTION | TCAM_SEL_COUNTER\n",
- __LINE__);
-
- tgt = VSC9953_IS1;
-
- /* write entries */
- vcap_entry2cache_init(tgt, ENTRY_WORDS_IS1);
- cmd_ret = vcap_cmd(tgt, 0, TCAM_CMD_INITIALIZE, TCAM_SEL_ENTRY,
- ENTRY_WORDS_IS1);
- if (cmd_ret != CMD_RET_SUCCESS)
- debug("VSC9953:%d invalid TCAM_SEL_ENTRY\n",
- __LINE__);
-
- /* write actions and counters */
- vcap_action2cache_init(tgt, BITS_TO_DWORD(IS1_ACT_WIDTH),
- BITS_TO_DWORD(IS1_CNT_WIDTH));
- out_le32((unsigned int *)(VSC9953_OFFSET +
- VSC9953_VCAP_CFG_MV_CFG(tgt)),
- VSC9953_VCAP_CFG_MV_CFG_SIZE(IS1_ACT_COUNT));
- cmd_ret = vcap_cmd(tgt, 0, TCAM_CMD_INITIALIZE,
- TCAM_SEL_ACTION | TCAM_SEL_COUNTER, ENTRY_WORDS_IS1);
- if (cmd_ret != CMD_RET_SUCCESS)
- debug("VSC9953:%d invalid TCAM_SEL_ACTION | TCAM_SEL_COUNTER\n",
- __LINE__);
-
- tgt = VSC9953_IS2;
-
- /* write entries */
- vcap_entry2cache_init(tgt, ENTRY_WORDS_IS2);
- cmd_ret = vcap_cmd(tgt, 0, TCAM_CMD_INITIALIZE, TCAM_SEL_ENTRY,
- ENTRY_WORDS_IS2);
- if (cmd_ret != CMD_RET_SUCCESS)
- debug("VSC9953:%d invalid selection: TCAM_SEL_ENTRY\n",
- __LINE__);
-
- /* write actions and counters */
- vcap_action2cache_init(tgt, BITS_TO_DWORD(IS2_ACT_WIDTH),
- BITS_TO_DWORD(IS2_CNT_WIDTH));
- out_le32((unsigned int *)(VSC9953_OFFSET +
- VSC9953_VCAP_CFG_MV_CFG(tgt)),
- VSC9953_VCAP_CFG_MV_CFG_SIZE(IS2_ACT_COUNT));
- cmd_ret = vcap_cmd(tgt, 0, TCAM_CMD_INITIALIZE,
- TCAM_SEL_ACTION | TCAM_SEL_COUNTER, ENTRY_WORDS_IS2);
- if (cmd_ret != CMD_RET_SUCCESS)
- debug("VSC9953:%d invalid TCAM_SEL_ACTION | TCAM_SEL_COUNTER\n",
- __LINE__);
-}
-
-void vsc9953_init(struct bd_info *bis)
-{
- u32 i;
- u32 hdx_cfg = 0;
- u32 phy_addr = 0;
- int timeout;
- struct vsc9953_system_reg *l2sys_reg;
- struct vsc9953_qsys_reg *l2qsys_reg;
- struct vsc9953_dev_gmii *l2dev_gmii_reg;
- struct vsc9953_analyzer *l2ana_reg;
- struct vsc9953_devcpu_gcb *l2dev_gcb;
-
- l2dev_gmii_reg = (struct vsc9953_dev_gmii *)(VSC9953_OFFSET +
- VSC9953_DEV_GMII_OFFSET);
-
- l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET +
- VSC9953_ANA_OFFSET);
-
- l2sys_reg = (struct vsc9953_system_reg *)(VSC9953_OFFSET +
- VSC9953_SYS_OFFSET);
-
- l2qsys_reg = (struct vsc9953_qsys_reg *)(VSC9953_OFFSET +
- VSC9953_QSYS_OFFSET);
-
- l2dev_gcb = (struct vsc9953_devcpu_gcb *)(VSC9953_OFFSET +
- VSC9953_DEVCPU_GCB);
-
- out_le32(&l2dev_gcb->chip_regs.soft_rst,
- VSC9953_SOFT_SWC_RST_ENA);
- timeout = 50000;
- while ((in_le32(&l2dev_gcb->chip_regs.soft_rst) &
- VSC9953_SOFT_SWC_RST_ENA) && --timeout)
- udelay(1); /* busy wait for vsc9953 soft reset */
- if (timeout == 0)
- debug("Timeout waiting for VSC9953 to reset\n");
-
- out_le32(&l2sys_reg->sys.reset_cfg, VSC9953_MEM_ENABLE |
- VSC9953_MEM_INIT);
-
- timeout = 50000;
- while ((in_le32(&l2sys_reg->sys.reset_cfg) &
- VSC9953_MEM_INIT) && --timeout)
- udelay(1); /* busy wait for vsc9953 memory init */
- if (timeout == 0)
- debug("Timeout waiting for VSC9953 memory to initialize\n");
-
- out_le32(&l2sys_reg->sys.reset_cfg, (in_le32(&l2sys_reg->sys.reset_cfg)
- | VSC9953_CORE_ENABLE));
-
- /* VSC9953 Setting to be done once only */
- out_le32(&l2qsys_reg->sys.ext_cpu_cfg, 0x00000b00);
-
- for (i = 0; i < VSC9953_MAX_PORTS; i++) {
- if (vsc9953_port_init(i))
- printf("Failed to initialize l2switch port %d\n", i);
-
- if (!vsc9953_l2sw.port[i].enabled)
- continue;
-
- /* Enable VSC9953 GMII Ports Port ID 0 - 7 */
- if (VSC9953_INTERNAL_PORT_CHECK(i)) {
- out_le32(&l2ana_reg->pfc[i].pfc_cfg,
- VSC9953_PFC_FC_QSGMII);
- out_le32(&l2sys_reg->pause_cfg.mac_fc_cfg[i],
- VSC9953_MAC_FC_CFG_QSGMII);
- } else {
- out_le32(&l2ana_reg->pfc[i].pfc_cfg,
- VSC9953_PFC_FC);
- out_le32(&l2sys_reg->pause_cfg.mac_fc_cfg[i],
- VSC9953_MAC_FC_CFG);
- }
-
- l2dev_gmii_reg = (struct vsc9953_dev_gmii *)
- (VSC9953_OFFSET + VSC9953_DEV_GMII_OFFSET +
- T1040_SWITCH_GMII_DEV_OFFSET * i);
-
- out_le32(&l2dev_gmii_reg->port_mode.clock_cfg,
- VSC9953_CLOCK_CFG);
- out_le32(&l2dev_gmii_reg->mac_cfg_status.mac_ena_cfg,
- VSC9953_MAC_ENA_CFG);
- out_le32(&l2dev_gmii_reg->mac_cfg_status.mac_mode_cfg,
- VSC9953_MAC_MODE_CFG);
- out_le32(&l2dev_gmii_reg->mac_cfg_status.mac_ifg_cfg,
- VSC9953_MAC_IFG_CFG);
- /* mac_hdx_cfg varies with port id*/
- hdx_cfg = VSC9953_MAC_HDX_CFG | (i << 16);
- out_le32(&l2dev_gmii_reg->mac_cfg_status.mac_hdx_cfg, hdx_cfg);
- out_le32(&l2sys_reg->sys.front_port_mode[i],
- VSC9953_FRONT_PORT_MODE);
- setbits_le32(&l2qsys_reg->sys.switch_port_mode[i],
- VSC9953_PORT_ENA);
- out_le32(&l2dev_gmii_reg->mac_cfg_status.mac_maxlen_cfg,
- VSC9953_MAC_MAX_LEN);
- out_le32(&l2sys_reg->pause_cfg.pause_cfg[i],
- VSC9953_PAUSE_CFG);
- /* WAIT FOR 2 us*/
- udelay(2);
-
- /* Initialize Lynx PHY Wrappers */
- phy_addr = 0;
- if (vsc9953_l2sw.port[i].enet_if ==
- PHY_INTERFACE_MODE_QSGMII)
- phy_addr = (i + 0x4) & 0x1F;
- else if (vsc9953_l2sw.port[i].enet_if ==
- PHY_INTERFACE_MODE_SGMII)
- phy_addr = (i + 1) & 0x1F;
-
- if (phy_addr) {
- /* SGMII IF mode + AN enable */
- vsc9953_mdio_write(&l2dev_gcb->mii_mng[0], phy_addr,
- 0x14, PHY_SGMII_IF_MODE_AN |
- PHY_SGMII_IF_MODE_SGMII);
- /* Dev ability according to SGMII specification */
- vsc9953_mdio_write(&l2dev_gcb->mii_mng[0], phy_addr,
- 0x4, PHY_SGMII_DEV_ABILITY_SGMII);
- /* Adjust link timer for SGMII
- * 1.6 ms in units of 8 ns = 2 * 10^5 = 0x30d40
- */
- vsc9953_mdio_write(&l2dev_gcb->mii_mng[0], phy_addr,
- 0x13, 0x0003);
- vsc9953_mdio_write(&l2dev_gcb->mii_mng[0], phy_addr,
- 0x12, 0x0d40);
- /* Restart AN */
- vsc9953_mdio_write(&l2dev_gcb->mii_mng[0], phy_addr,
- 0x0, PHY_SGMII_CR_DEF_VAL |
- PHY_SGMII_CR_RESET_AN);
-
- timeout = 50000;
- while ((vsc9953_mdio_read(&l2dev_gcb->mii_mng[0],
- phy_addr, 0x01) & 0x0020) && --timeout)
- udelay(1); /* wait for AN to complete */
- if (timeout == 0)
- debug("Timeout waiting for AN to complete\n");
- }
- }
-
- vsc9953_vcap_init();
- vsc9953_default_configuration();
-
-#ifdef CONFIG_CMD_ETHSW
- if (ethsw_define_functions(&vsc9953_cmd_func) < 0)
- debug("Unable to use \"ethsw\" commands\n");
-#endif
-
- printf("VSC9953 L2 switch initialized\n");
- return;
-}
diff --git a/drivers/pci/pci-rcar-gen3.c b/drivers/pci/pci-rcar-gen3.c
index 49029238d35..1252ef74c58 100644
--- a/drivers/pci/pci-rcar-gen3.c
+++ b/drivers/pci/pci-rcar-gen3.c
@@ -27,7 +27,7 @@
#define PCIECAR 0x000010
#define PCIECCTLR 0x000018
-#define CONFIG_SEND_ENABLE BIT(31)
+#define SEND_ENABLE BIT(31)
#define TYPE0 (0 << 8)
#define TYPE1 BIT(8)
#define PCIECDR 0x000020
@@ -170,9 +170,9 @@ static int rcar_pcie_config_access(const struct udevice *udev,
/* Enable the configuration access */
if (!PCI_BUS(bdf))
- writel(CONFIG_SEND_ENABLE | TYPE0, priv->regs + PCIECCTLR);
+ writel(SEND_ENABLE | TYPE0, priv->regs + PCIECCTLR);
else
- writel(CONFIG_SEND_ENABLE | TYPE1, priv->regs + PCIECCTLR);
+ writel(SEND_ENABLE | TYPE1, priv->regs + PCIECCTLR);
/* Check for errors */
if (readl(priv->regs + PCIEERRFR) & UNSUPPORTED_REQUEST)
diff --git a/drivers/pci/pcie_dw_common.c b/drivers/pci/pcie_dw_common.c
index e66fb1490a5..9f8b016d114 100644
--- a/drivers/pci/pcie_dw_common.c
+++ b/drivers/pci/pcie_dw_common.c
@@ -73,6 +73,8 @@ int pcie_dw_prog_outbound_atu_unroll(struct pcie_dw *pci, int index,
upper_32_bits(cpu_addr));
dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LIMIT,
lower_32_bits(cpu_addr + size - 1));
+ dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_LIMIT,
+ upper_32_bits(cpu_addr + size - 1));
dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET,
lower_32_bits(pci_addr));
dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET,
diff --git a/drivers/pci/pcie_dw_common.h b/drivers/pci/pcie_dw_common.h
index 6b701645af6..e0f7796f2a8 100644
--- a/drivers/pci/pcie_dw_common.h
+++ b/drivers/pci/pcie_dw_common.h
@@ -32,6 +32,7 @@
#define PCIE_ATU_UNR_LIMIT 0x10
#define PCIE_ATU_UNR_LOWER_TARGET 0x14
#define PCIE_ATU_UNR_UPPER_TARGET 0x18
+#define PCIE_ATU_UNR_UPPER_LIMIT 0x20
#define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
#define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c
index 46ac01713ff..da48466480c 100644
--- a/drivers/pci/pcie_imx.c
+++ b/drivers/pci/pcie_imx.c
@@ -534,13 +534,13 @@ static int imx6_pcie_init_phy(void)
int imx6_pcie_toggle_power(struct udevice *vpcie)
{
-#ifdef CONFIG_PCIE_IMX_POWER_GPIO
- gpio_request(CONFIG_PCIE_IMX_POWER_GPIO, "pcie_power");
- gpio_direction_output(CONFIG_PCIE_IMX_POWER_GPIO, 0);
+#ifdef CFG_PCIE_IMX_POWER_GPIO
+ gpio_request(CFG_PCIE_IMX_POWER_GPIO, "pcie_power");
+ gpio_direction_output(CFG_PCIE_IMX_POWER_GPIO, 0);
mdelay(20);
- gpio_set_value(CONFIG_PCIE_IMX_POWER_GPIO, 1);
+ gpio_set_value(CFG_PCIE_IMX_POWER_GPIO, 1);
mdelay(20);
- gpio_free(CONFIG_PCIE_IMX_POWER_GPIO);
+ gpio_free(CFG_PCIE_IMX_POWER_GPIO);
#endif
#if CONFIG_IS_ENABLED(DM_REGULATOR)
@@ -566,7 +566,7 @@ int imx6_pcie_toggle_reset(struct gpio_desc *gpio, bool active_high)
* do self-initialisation.
*
* In case your #PERST pin is connected to a plain GPIO pin of the
- * CPU, you can define CONFIG_PCIE_IMX_PERST_GPIO in your board's
+ * CPU, you can define CFG_PCIE_IMX_PERST_GPIO in your board's
* configuration file and the condition below will handle the rest
* of the reset toggling.
*
@@ -578,13 +578,13 @@ int imx6_pcie_toggle_reset(struct gpio_desc *gpio, bool active_high)
* Linux at all in the first place since it's in some non-reset
* state due to being previously used in U-Boot.
*/
-#ifdef CONFIG_PCIE_IMX_PERST_GPIO
- gpio_request(CONFIG_PCIE_IMX_PERST_GPIO, "pcie_reset");
- gpio_direction_output(CONFIG_PCIE_IMX_PERST_GPIO, 0);
+#ifdef CFG_PCIE_IMX_PERST_GPIO
+ gpio_request(CFG_PCIE_IMX_PERST_GPIO, "pcie_reset");
+ gpio_direction_output(CFG_PCIE_IMX_PERST_GPIO, 0);
mdelay(20);
- gpio_set_value(CONFIG_PCIE_IMX_PERST_GPIO, 1);
+ gpio_set_value(CFG_PCIE_IMX_PERST_GPIO, 1);
mdelay(20);
- gpio_free(CONFIG_PCIE_IMX_PERST_GPIO);
+ gpio_free(CFG_PCIE_IMX_PERST_GPIO);
#else
if (dm_gpio_is_valid(gpio)) {
/* Assert PERST# for 20ms then de-assert */
diff --git a/drivers/phy/phy-stm32-usbphyc.c b/drivers/phy/phy-stm32-usbphyc.c
index 9f0b7d71187..dcf2194e9a7 100644
--- a/drivers/phy/phy-stm32-usbphyc.c
+++ b/drivers/phy/phy-stm32-usbphyc.c
@@ -375,7 +375,7 @@ static int stm32_usbphyc_phy_power_off(struct phy *phy)
return 0;
if (usbphyc_phy->vbus) {
- ret = regulator_set_enable(usbphyc_phy->vbus, false);
+ ret = regulator_set_enable_if_allowed(usbphyc_phy->vbus, false);
if (ret)
return ret;
}
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
index 62b8ba3a4a8..b32a498ea71 100644
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
@@ -119,7 +119,7 @@ static int rockchip_usb2phy_init(struct phy *phy)
int ret;
ret = clk_enable(&priv->phyclk);
- if (ret) {
+ if (ret && ret != -ENOSYS) {
dev_err(phy->dev, "failed to enable phyclk (ret=%d)\n", ret);
return ret;
}
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
index 061104be056..c4fbda7a925 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
@@ -338,6 +338,7 @@ static const struct sunxi_pinctrl_function sun6i_a31_r_pinctrl_functions[] = {
{ "gpio_in", 0 },
{ "gpio_out", 1 },
{ "s_i2c", 2 }, /* PL0-PL1 */
+ { "s_p2wi", 3 }, /* PL0-PL1 */
{ "s_uart", 2 }, /* PL2-PL3 */
};
@@ -404,6 +405,7 @@ static const struct sunxi_pinctrl_function sun8i_a23_r_pinctrl_functions[] = {
{ "gpio_in", 0 },
{ "gpio_out", 1 },
{ "s_i2c", 3 }, /* PL0-PL1 */
+ { "s_rsb", 2 }, /* PL0-PL1 */
{ "s_uart", 2 }, /* PL2-PL3 */
};
@@ -469,6 +471,7 @@ static const struct sunxi_pinctrl_function sun8i_a83t_r_pinctrl_functions[] = {
{ "gpio_in", 0 },
{ "gpio_out", 1 },
{ "s_i2c", 2 }, /* PL8-PL9 */
+ { "s_rsb", 2 }, /* PL0-PL1 */
{ "s_uart", 2 }, /* PL2-PL3 */
};
@@ -574,6 +577,7 @@ static const struct sunxi_pinctrl_function sun9i_a80_r_pinctrl_functions[] = {
{ "gpio_out", 1 },
{ "s_i2c0", 2 }, /* PN0-PN1 */
{ "s_i2c1", 3 }, /* PM8-PM9 */
+ { "s_rsb", 3 }, /* PN0-PN1 */
{ "s_uart", 3 }, /* PL0-PL1 */
};
@@ -615,6 +619,7 @@ static const struct sunxi_pinctrl_function sun50i_a64_r_pinctrl_functions[] = {
{ "gpio_in", 0 },
{ "gpio_out", 1 },
{ "s_i2c", 2 }, /* PL8-PL9 */
+ { "s_rsb", 2 }, /* PL0-PL1 */
{ "s_uart", 2 }, /* PL2-PL3 */
};
@@ -680,6 +685,7 @@ static const struct sunxi_pinctrl_function sun50i_h6_r_pinctrl_functions[] = {
{ "gpio_in", 0 },
{ "gpio_out", 1 },
{ "s_i2c", 3 }, /* PL0-PL1 */
+ { "s_rsb", 2 }, /* PL0-PL1 */
{ "s_uart", 2 }, /* PL2-PL3 */
};
@@ -717,6 +723,7 @@ static const struct sunxi_pinctrl_function sun50i_h616_r_pinctrl_functions[] = {
{ "gpio_in", 0 },
{ "gpio_out", 1 },
{ "s_i2c", 3 }, /* PL0-PL1 */
+ { "s_rsb", 2 }, /* PL0-PL1 */
{ "s_uart", 2 }, /* PL2-PL3 */
};
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
index 631bb1f963b..bdca3f2f715 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
@@ -33,6 +33,9 @@ static int uniphier_pinctrl_get_pins_count(struct udevice *dev)
const struct uniphier_pinctrl_pin *pins = priv->socdata->pins;
int pins_count = priv->socdata->pins_count;
+ if (WARN_ON(!pins_count))
+ return 0; /* no table of pins */
+
/*
* We do not list all pins in the pin table to save memory footprint.
* Report the max pin number + 1 to fake the framework.
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c
index 1fc7bdb5c80..8a8f1269bb5 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c
@@ -1,7 +1,8 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2017 Socionext Inc.
+ * Copyright (C) 2017-2021 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Author: Dai Okamura <dai.okamura@socionext.com>
*/
#include <common.h>
@@ -10,6 +11,21 @@
#include "pinctrl-uniphier.h"
+static const struct uniphier_pinctrl_pin uniphier_pxs3_pins[] = {
+ UNIPHIER_PINCTRL_PIN(62, "RGMII0_TXCLK", 28, UNIPHIER_PIN_DRV_2BIT),
+ UNIPHIER_PINCTRL_PIN(63, "RGMII0_TXD0", 29, UNIPHIER_PIN_DRV_2BIT),
+ UNIPHIER_PINCTRL_PIN(64, "RGMII0_TXD1", 30, UNIPHIER_PIN_DRV_2BIT),
+ UNIPHIER_PINCTRL_PIN(65, "RGMII0_TXD2", 31, UNIPHIER_PIN_DRV_2BIT),
+ UNIPHIER_PINCTRL_PIN(66, "RGMII0_TXD3", 32, UNIPHIER_PIN_DRV_2BIT),
+ UNIPHIER_PINCTRL_PIN(67, "RGMII0_TXCTL", 33, UNIPHIER_PIN_DRV_2BIT),
+ UNIPHIER_PINCTRL_PIN(78, "RGMII1_TXCLK", 44, UNIPHIER_PIN_DRV_2BIT),
+ UNIPHIER_PINCTRL_PIN(79, "RGMII1_TXD0", 45, UNIPHIER_PIN_DRV_2BIT),
+ UNIPHIER_PINCTRL_PIN(80, "RGMII1_TXD1", 46, UNIPHIER_PIN_DRV_2BIT),
+ UNIPHIER_PINCTRL_PIN(81, "RGMII1_TXD2", 47, UNIPHIER_PIN_DRV_2BIT),
+ UNIPHIER_PINCTRL_PIN(82, "RGMII1_TXD3", 48, UNIPHIER_PIN_DRV_2BIT),
+ UNIPHIER_PINCTRL_PIN(83, "RGMII1_TXCTL", 49, UNIPHIER_PIN_DRV_2BIT),
+};
+
static const unsigned emmc_pins[] = {31, 32, 33, 34, 35, 36, 37, 38};
static const int emmc_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0};
static const unsigned emmc_dat8_pins[] = {39, 40, 41, 42};
@@ -121,6 +137,8 @@ static const char * const uniphier_pxs3_functions[] = {
};
static struct uniphier_pinctrl_socdata uniphier_pxs3_pinctrl_socdata = {
+ .pins = uniphier_pxs3_pins,
+ .pins_count = ARRAY_SIZE(uniphier_pxs3_pins),
.groups = uniphier_pxs3_groups,
.groups_count = ARRAY_SIZE(uniphier_pxs3_groups),
.functions = uniphier_pxs3_functions,
diff --git a/drivers/power/domain/ti-power-domain.c b/drivers/power/domain/ti-power-domain.c
index a7f64d04f5c..9e7151307c8 100644
--- a/drivers/power/domain/ti-power-domain.c
+++ b/drivers/power/domain/ti-power-domain.c
@@ -93,6 +93,12 @@ static const struct soc_attr ti_k3_soc_pd_data[] = {
.data = &am62x_pd_platdata,
},
#endif
+#ifdef CONFIG_SOC_K3_AM62A7
+ {
+ .family = "AM62AX",
+ .data = &am62ax_pd_platdata,
+ },
+#endif
{ /* sentinel */ }
};
diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig
index d94048db5f7..176fb07c651 100644
--- a/drivers/power/pmic/Kconfig
+++ b/drivers/power/pmic/Kconfig
@@ -416,6 +416,9 @@ config POWER_HI6553
config POWER_LTC3676
bool "Enable legacy driver for LTC3676 PMIC"
+config POWER_PCA9450
+ bool "Enable legacy driver for PCA9450 PMIC"
+
config POWER_PFUZE100
bool "Enable legacy driver for PFUZE100 PMIC"
diff --git a/drivers/power/pmic/pmic-uclass.c b/drivers/power/pmic/pmic-uclass.c
index 5dcf6d8079d..0e2f5e1f411 100644
--- a/drivers/power/pmic/pmic-uclass.c
+++ b/drivers/power/pmic/pmic-uclass.c
@@ -39,6 +39,10 @@ int pmic_bind_children(struct udevice *pmic, ofnode parent,
node_name = ofnode_get_name(node);
debug("* Found child node: '%s'\n", node_name);
+ if (!ofnode_is_enabled(node)) {
+ debug(" - ignoring disabled device\n");
+ continue;
+ }
child = NULL;
for (info = child_info; info->prefix && info->driver; info++) {
diff --git a/drivers/power/pmic/pmic_ltc3676.c b/drivers/power/pmic/pmic_ltc3676.c
index 00c3e201cd5..af94f37b0f1 100644
--- a/drivers/power/pmic/pmic_ltc3676.c
+++ b/drivers/power/pmic/pmic_ltc3676.c
@@ -23,7 +23,7 @@ int power_ltc3676_init(unsigned char bus)
p->name = name;
p->interface = PMIC_I2C;
p->number_of_regs = LTC3676_NUM_OF_REGS;
- p->hw.i2c.addr = CONFIG_POWER_LTC3676_I2C_ADDR;
+ p->hw.i2c.addr = CFG_POWER_LTC3676_I2C_ADDR;
p->hw.i2c.tx_num = 1;
p->bus = bus;
diff --git a/drivers/power/pmic/pmic_pfuze100.c b/drivers/power/pmic/pmic_pfuze100.c
index c646a0c31f8..5115b55e49d 100644
--- a/drivers/power/pmic/pmic_pfuze100.c
+++ b/drivers/power/pmic/pmic_pfuze100.c
@@ -23,7 +23,7 @@ int power_pfuze100_init(unsigned char bus)
p->name = name;
p->interface = PMIC_I2C;
p->number_of_regs = PFUZE100_NUM_OF_REGS;
- p->hw.i2c.addr = CONFIG_POWER_PFUZE100_I2C_ADDR;
+ p->hw.i2c.addr = CFG_POWER_PFUZE100_I2C_ADDR;
p->hw.i2c.tx_num = 1;
p->bus = bus;
diff --git a/drivers/power/pmic/pmic_pfuze3000.c b/drivers/power/pmic/pmic_pfuze3000.c
index 1077fa5e9d9..a6d97252bc9 100644
--- a/drivers/power/pmic/pmic_pfuze3000.c
+++ b/drivers/power/pmic/pmic_pfuze3000.c
@@ -23,7 +23,7 @@ int power_pfuze3000_init(unsigned char bus)
p->name = name;
p->interface = PMIC_I2C;
p->number_of_regs = PFUZE3000_NUM_OF_REGS;
- p->hw.i2c.addr = CONFIG_POWER_PFUZE3000_I2C_ADDR;
+ p->hw.i2c.addr = CFG_POWER_PFUZE3000_I2C_ADDR;
p->hw.i2c.tx_num = 1;
p->bus = bus;
diff --git a/drivers/power/power_fsl.c b/drivers/power/power_fsl.c
index 9bb7e39f2cc..9dc930fb305 100644
--- a/drivers/power/power_fsl.c
+++ b/drivers/power/power_fsl.c
@@ -39,10 +39,10 @@ int pmic_init(unsigned char bus)
#if defined(CONFIG_POWER_SPI)
p->interface = PMIC_SPI;
- p->hw.spi.cs = CONFIG_FSL_PMIC_CS;
- p->hw.spi.clk = CONFIG_FSL_PMIC_CLK;
- p->hw.spi.mode = CONFIG_FSL_PMIC_MODE;
- p->hw.spi.bitlen = CONFIG_FSL_PMIC_BITLEN;
+ p->hw.spi.cs = CFG_FSL_PMIC_CS;
+ p->hw.spi.clk = CFG_FSL_PMIC_CLK;
+ p->hw.spi.mode = CFG_FSL_PMIC_MODE;
+ p->hw.spi.bitlen = CFG_FSL_PMIC_BITLEN;
p->hw.spi.flags = SPI_XFER_BEGIN | SPI_XFER_END;
p->hw.spi.prepare_tx = pmic_spi_prepare_tx;
#elif defined(CONFIG_POWER_I2C)
diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c
index 9b8a8c189d0..8fbb40cc276 100644
--- a/drivers/pwm/pwm-imx.c
+++ b/drivers/pwm/pwm-imx.c
@@ -76,7 +76,7 @@ int pwm_imx_get_parms(int period_ns, int duty_ns, unsigned long *period_c,
* value here as a define. Replace it when we have the clock
* framework.
*/
- c = CONFIG_IMX6_PWM_PER_CLK;
+ c = CFG_IMX6_PWM_PER_CLK;
c = c * period_ns;
do_div(c, 1000000000);
*period_c = c;
diff --git a/drivers/qe/Makefile b/drivers/qe/Makefile
index 0d31ed1a429..12d0b459fba 100644
--- a/drivers/qe/Makefile
+++ b/drivers/qe/Makefile
@@ -2,6 +2,6 @@
#
# Copyright (C) 2006 Freescale Semiconductor, Inc.
-obj-$(CONFIG_QE) += qe.o uccf.o uec.o uec_phy.o
+obj-$(CONFIG_QE) += qe.o
obj-$(CONFIG_U_QE) += qe.o
obj-$(CONFIG_OF_LIBFDT) += fdt.o
diff --git a/drivers/qe/uccf.c b/drivers/qe/uccf.c
deleted file mode 100644
index d5d734439cf..00000000000
--- a/drivers/qe/uccf.c
+++ /dev/null
@@ -1,509 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2006 Freescale Semiconductor, Inc.
- *
- * Dave Liu <daveliu@freescale.com>
- * based on source code of Shlomi Gridish
- */
-
-#include <common.h>
-#include <malloc.h>
-#include <linux/errno.h>
-#include <asm/io.h>
-#include <linux/immap_qe.h>
-#include "uccf.h"
-#include <fsl_qe.h>
-
-#if !defined(CONFIG_DM_ETH)
-void ucc_fast_transmit_on_demand(struct ucc_fast_priv *uccf)
-{
- out_be16(&uccf->uf_regs->utodr, UCC_FAST_TOD);
-}
-
-u32 ucc_fast_get_qe_cr_subblock(int ucc_num)
-{
- switch (ucc_num) {
- case 0:
- return QE_CR_SUBBLOCK_UCCFAST1;
- case 1:
- return QE_CR_SUBBLOCK_UCCFAST2;
- case 2:
- return QE_CR_SUBBLOCK_UCCFAST3;
- case 3:
- return QE_CR_SUBBLOCK_UCCFAST4;
- case 4:
- return QE_CR_SUBBLOCK_UCCFAST5;
- case 5:
- return QE_CR_SUBBLOCK_UCCFAST6;
- case 6:
- return QE_CR_SUBBLOCK_UCCFAST7;
- case 7:
- return QE_CR_SUBBLOCK_UCCFAST8;
- default:
- return QE_CR_SUBBLOCK_INVALID;
- }
-}
-
-static void ucc_get_cmxucr_reg(int ucc_num, u32 **p_cmxucr,
- u8 *reg_num, u8 *shift)
-{
- switch (ucc_num) {
- case 0: /* UCC1 */
- *p_cmxucr = &qe_immr->qmx.cmxucr1;
- *reg_num = 1;
- *shift = 16;
- break;
- case 2: /* UCC3 */
- *p_cmxucr = &qe_immr->qmx.cmxucr1;
- *reg_num = 1;
- *shift = 0;
- break;
- case 4: /* UCC5 */
- *p_cmxucr = &qe_immr->qmx.cmxucr2;
- *reg_num = 2;
- *shift = 16;
- break;
- case 6: /* UCC7 */
- *p_cmxucr = &qe_immr->qmx.cmxucr2;
- *reg_num = 2;
- *shift = 0;
- break;
- case 1: /* UCC2 */
- *p_cmxucr = &qe_immr->qmx.cmxucr3;
- *reg_num = 3;
- *shift = 16;
- break;
- case 3: /* UCC4 */
- *p_cmxucr = &qe_immr->qmx.cmxucr3;
- *reg_num = 3;
- *shift = 0;
- break;
- case 5: /* UCC6 */
- *p_cmxucr = &qe_immr->qmx.cmxucr4;
- *reg_num = 4;
- *shift = 16;
- break;
- case 7: /* UCC8 */
- *p_cmxucr = &qe_immr->qmx.cmxucr4;
- *reg_num = 4;
- *shift = 0;
- break;
- default:
- break;
- }
-}
-
-static int ucc_set_clk_src(int ucc_num, qe_clock_e clock, comm_dir_e mode)
-{
- u32 *p_cmxucr = NULL;
- u8 reg_num = 0;
- u8 shift = 0;
- u32 clk_bits;
- u32 clk_mask;
- int source = -1;
-
- /* check if the UCC number is in range. */
- if ((ucc_num > UCC_MAX_NUM - 1) || ucc_num < 0)
- return -EINVAL;
-
- if (!(mode == COMM_DIR_RX || mode == COMM_DIR_TX)) {
- printf("%s: bad comm mode type passed\n", __func__);
- return -EINVAL;
- }
-
- ucc_get_cmxucr_reg(ucc_num, &p_cmxucr, &reg_num, &shift);
-
- switch (reg_num) {
- case 1:
- switch (clock) {
- case QE_BRG1:
- source = 1;
- break;
- case QE_BRG2:
- source = 2;
- break;
- case QE_BRG7:
- source = 3;
- break;
- case QE_BRG8:
- source = 4;
- break;
- case QE_CLK9:
- source = 5;
- break;
- case QE_CLK10:
- source = 6;
- break;
- case QE_CLK11:
- source = 7;
- break;
- case QE_CLK12:
- source = 8;
- break;
- case QE_CLK15:
- source = 9;
- break;
- case QE_CLK16:
- source = 10;
- break;
- default:
- source = -1;
- break;
- }
- break;
- case 2:
- switch (clock) {
- case QE_BRG5:
- source = 1;
- break;
- case QE_BRG6:
- source = 2;
- break;
- case QE_BRG7:
- source = 3;
- break;
- case QE_BRG8:
- source = 4;
- break;
- case QE_CLK13:
- source = 5;
- break;
- case QE_CLK14:
- source = 6;
- break;
- case QE_CLK19:
- source = 7;
- break;
- case QE_CLK20:
- source = 8;
- break;
- case QE_CLK15:
- source = 9;
- break;
- case QE_CLK16:
- source = 10;
- break;
- default:
- source = -1;
- break;
- }
- break;
- case 3:
- switch (clock) {
- case QE_BRG9:
- source = 1;
- break;
- case QE_BRG10:
- source = 2;
- break;
- case QE_BRG15:
- source = 3;
- break;
- case QE_BRG16:
- source = 4;
- break;
- case QE_CLK3:
- source = 5;
- break;
- case QE_CLK4:
- source = 6;
- break;
- case QE_CLK17:
- source = 7;
- break;
- case QE_CLK18:
- source = 8;
- break;
- case QE_CLK7:
- source = 9;
- break;
- case QE_CLK8:
- source = 10;
- break;
- case QE_CLK16:
- source = 11;
- break;
- default:
- source = -1;
- break;
- }
- break;
- case 4:
- switch (clock) {
- case QE_BRG13:
- source = 1;
- break;
- case QE_BRG14:
- source = 2;
- break;
- case QE_BRG15:
- source = 3;
- break;
- case QE_BRG16:
- source = 4;
- break;
- case QE_CLK5:
- source = 5;
- break;
- case QE_CLK6:
- source = 6;
- break;
- case QE_CLK21:
- source = 7;
- break;
- case QE_CLK22:
- source = 8;
- break;
- case QE_CLK7:
- source = 9;
- break;
- case QE_CLK8:
- source = 10;
- break;
- case QE_CLK16:
- source = 11;
- break;
- default:
- source = -1;
- break;
- }
- break;
- default:
- source = -1;
- break;
- }
-
- if (source == -1) {
- printf("%s: Bad combination of clock and UCC\n", __func__);
- return -ENOENT;
- }
-
- clk_bits = (u32)source;
- clk_mask = QE_CMXUCR_TX_CLK_SRC_MASK;
- if (mode == COMM_DIR_RX) {
- clk_bits <<= 4; /* Rx field is 4 bits to left of Tx field */
- clk_mask <<= 4; /* Rx field is 4 bits to left of Tx field */
- }
- clk_bits <<= shift;
- clk_mask <<= shift;
-
- out_be32(p_cmxucr, (in_be32(p_cmxucr) & ~clk_mask) | clk_bits);
-
- return 0;
-}
-
-static uint ucc_get_reg_baseaddr(int ucc_num)
-{
- uint base = 0;
-
- /* check if the UCC number is in range */
- if ((ucc_num > UCC_MAX_NUM - 1) || ucc_num < 0) {
- printf("%s: the UCC num not in ranges\n", __func__);
- return 0;
- }
-
- switch (ucc_num) {
- case 0:
- base = 0x00002000;
- break;
- case 1:
- base = 0x00003000;
- break;
- case 2:
- base = 0x00002200;
- break;
- case 3:
- base = 0x00003200;
- break;
- case 4:
- base = 0x00002400;
- break;
- case 5:
- base = 0x00003400;
- break;
- case 6:
- base = 0x00002600;
- break;
- case 7:
- base = 0x00003600;
- break;
- default:
- break;
- }
-
- base = (uint)qe_immr + base;
- return base;
-}
-
-void ucc_fast_enable(struct ucc_fast_priv *uccf, comm_dir_e mode)
-{
- ucc_fast_t *uf_regs;
- u32 gumr;
-
- uf_regs = uccf->uf_regs;
-
- /* Enable reception and/or transmission on this UCC. */
- gumr = in_be32(&uf_regs->gumr);
- if (mode & COMM_DIR_TX) {
- gumr |= UCC_FAST_GUMR_ENT;
- uccf->enabled_tx = 1;
- }
- if (mode & COMM_DIR_RX) {
- gumr |= UCC_FAST_GUMR_ENR;
- uccf->enabled_rx = 1;
- }
- out_be32(&uf_regs->gumr, gumr);
-}
-
-void ucc_fast_disable(struct ucc_fast_priv *uccf, comm_dir_e mode)
-{
- ucc_fast_t *uf_regs;
- u32 gumr;
-
- uf_regs = uccf->uf_regs;
-
- /* Disable reception and/or transmission on this UCC. */
- gumr = in_be32(&uf_regs->gumr);
- if (mode & COMM_DIR_TX) {
- gumr &= ~UCC_FAST_GUMR_ENT;
- uccf->enabled_tx = 0;
- }
- if (mode & COMM_DIR_RX) {
- gumr &= ~UCC_FAST_GUMR_ENR;
- uccf->enabled_rx = 0;
- }
- out_be32(&uf_regs->gumr, gumr);
-}
-
-int ucc_fast_init(struct ucc_fast_inf *uf_info,
- struct ucc_fast_priv **uccf_ret)
-{
- struct ucc_fast_priv *uccf;
- ucc_fast_t *uf_regs;
-
- if (!uf_info)
- return -EINVAL;
-
- if (uf_info->ucc_num < 0 || (uf_info->ucc_num > UCC_MAX_NUM - 1)) {
- printf("%s: Illagal UCC number!\n", __func__);
- return -EINVAL;
- }
-
- uccf = (struct ucc_fast_priv *)malloc(sizeof(struct ucc_fast_priv));
- if (!uccf) {
- printf("%s: No memory for UCC fast data structure!\n",
- __func__);
- return -ENOMEM;
- }
- memset(uccf, 0, sizeof(struct ucc_fast_priv));
-
- /* Save fast UCC structure */
- uccf->uf_info = uf_info;
- uccf->uf_regs = (ucc_fast_t *)ucc_get_reg_baseaddr(uf_info->ucc_num);
-
- if (!uccf->uf_regs) {
- printf("%s: No memory map for UCC fast controller!\n",
- __func__);
- return -ENOMEM;
- }
-
- uccf->enabled_tx = 0;
- uccf->enabled_rx = 0;
-
- uf_regs = uccf->uf_regs;
- uccf->p_ucce = (u32 *)&uf_regs->ucce;
- uccf->p_uccm = (u32 *)&uf_regs->uccm;
-
- /* Init GUEMR register, UCC both Rx and Tx is Fast protocol */
- out_8(&uf_regs->guemr, UCC_GUEMR_SET_RESERVED3 | UCC_GUEMR_MODE_FAST_RX
- | UCC_GUEMR_MODE_FAST_TX);
-
- /* Set GUMR, disable UCC both Rx and Tx, Ethernet protocol */
- out_be32(&uf_regs->gumr, UCC_FAST_GUMR_ETH);
-
- /* Set the Giga ethernet VFIFO stuff */
- if (uf_info->eth_type == GIGA_ETH) {
- /* Allocate memory for Tx Virtual Fifo */
- uccf->ucc_fast_tx_virtual_fifo_base_offset =
- qe_muram_alloc(UCC_GETH_UTFS_GIGA_INIT,
- UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
-
- /* Allocate memory for Rx Virtual Fifo */
- uccf->ucc_fast_rx_virtual_fifo_base_offset =
- qe_muram_alloc(UCC_GETH_URFS_GIGA_INIT +
- UCC_FAST_RX_VIRTUAL_FIFO_SIZE_PAD,
- UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
-
- /* utfb, urfb are offsets from MURAM base */
- out_be32(&uf_regs->utfb,
- uccf->ucc_fast_tx_virtual_fifo_base_offset);
- out_be32(&uf_regs->urfb,
- uccf->ucc_fast_rx_virtual_fifo_base_offset);
-
- /* Set Virtual Fifo registers */
- out_be16(&uf_regs->urfs, UCC_GETH_URFS_GIGA_INIT);
- out_be16(&uf_regs->urfet, UCC_GETH_URFET_GIGA_INIT);
- out_be16(&uf_regs->urfset, UCC_GETH_URFSET_GIGA_INIT);
- out_be16(&uf_regs->utfs, UCC_GETH_UTFS_GIGA_INIT);
- out_be16(&uf_regs->utfet, UCC_GETH_UTFET_GIGA_INIT);
- out_be16(&uf_regs->utftt, UCC_GETH_UTFTT_GIGA_INIT);
- }
-
- /* Set the Fast ethernet VFIFO stuff */
- if (uf_info->eth_type == FAST_ETH) {
- /* Allocate memory for Tx Virtual Fifo */
- uccf->ucc_fast_tx_virtual_fifo_base_offset =
- qe_muram_alloc(UCC_GETH_UTFS_INIT,
- UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
-
- /* Allocate memory for Rx Virtual Fifo */
- uccf->ucc_fast_rx_virtual_fifo_base_offset =
- qe_muram_alloc(UCC_GETH_URFS_INIT +
- UCC_FAST_RX_VIRTUAL_FIFO_SIZE_PAD,
- UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
-
- /* utfb, urfb are offsets from MURAM base */
- out_be32(&uf_regs->utfb,
- uccf->ucc_fast_tx_virtual_fifo_base_offset);
- out_be32(&uf_regs->urfb,
- uccf->ucc_fast_rx_virtual_fifo_base_offset);
-
- /* Set Virtual Fifo registers */
- out_be16(&uf_regs->urfs, UCC_GETH_URFS_INIT);
- out_be16(&uf_regs->urfet, UCC_GETH_URFET_INIT);
- out_be16(&uf_regs->urfset, UCC_GETH_URFSET_INIT);
- out_be16(&uf_regs->utfs, UCC_GETH_UTFS_INIT);
- out_be16(&uf_regs->utfet, UCC_GETH_UTFET_INIT);
- out_be16(&uf_regs->utftt, UCC_GETH_UTFTT_INIT);
- }
-
- /* Rx clock routing */
- if (uf_info->rx_clock != QE_CLK_NONE) {
- if (ucc_set_clk_src(uf_info->ucc_num,
- uf_info->rx_clock, COMM_DIR_RX)) {
- printf("%s: Illegal value for parameter 'RxClock'.\n",
- __func__);
- return -EINVAL;
- }
- }
-
- /* Tx clock routing */
- if (uf_info->tx_clock != QE_CLK_NONE) {
- if (ucc_set_clk_src(uf_info->ucc_num,
- uf_info->tx_clock, COMM_DIR_TX)) {
- printf("%s: Illegal value for parameter 'TxClock'.\n",
- __func__);
- return -EINVAL;
- }
- }
-
- /* Clear interrupt mask register to disable all of interrupts */
- out_be32(&uf_regs->uccm, 0x0);
-
- /* Writing '1' to clear all of envents */
- out_be32(&uf_regs->ucce, 0xffffffff);
-
- *uccf_ret = uccf;
- return 0;
-}
-#endif
diff --git a/drivers/qe/uccf.h b/drivers/qe/uccf.h
deleted file mode 100644
index 99f8458edf6..00000000000
--- a/drivers/qe/uccf.h
+++ /dev/null
@@ -1,119 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2006 Freescale Semiconductor, Inc.
- *
- * Dave Liu <daveliu@freescale.com>
- * based on source code of Shlomi Gridish
- */
-
-#ifndef __UCCF_H__
-#define __UCCF_H__
-
-#include "common.h"
-#include "linux/immap_qe.h"
-#include <fsl_qe.h>
-
-/* Fast or Giga ethernet */
-enum enet_type {
- FAST_ETH,
- GIGA_ETH,
-};
-
-/* General UCC Extended Mode Register */
-#define UCC_GUEMR_MODE_MASK_RX 0x02
-#define UCC_GUEMR_MODE_MASK_TX 0x01
-#define UCC_GUEMR_MODE_FAST_RX 0x02
-#define UCC_GUEMR_MODE_FAST_TX 0x01
-#define UCC_GUEMR_MODE_SLOW_RX 0x00
-#define UCC_GUEMR_MODE_SLOW_TX 0x00
-/* Bit 3 must be set 1 */
-#define UCC_GUEMR_SET_RESERVED3 0x10
-
-/* General UCC FAST Mode Register */
-#define UCC_FAST_GUMR_TCI 0x20000000
-#define UCC_FAST_GUMR_TRX 0x10000000
-#define UCC_FAST_GUMR_TTX 0x08000000
-#define UCC_FAST_GUMR_CDP 0x04000000
-#define UCC_FAST_GUMR_CTSP 0x02000000
-#define UCC_FAST_GUMR_CDS 0x01000000
-#define UCC_FAST_GUMR_CTSS 0x00800000
-#define UCC_FAST_GUMR_TXSY 0x00020000
-#define UCC_FAST_GUMR_RSYN 0x00010000
-#define UCC_FAST_GUMR_RTSM 0x00002000
-#define UCC_FAST_GUMR_REVD 0x00000400
-#define UCC_FAST_GUMR_ENR 0x00000020
-#define UCC_FAST_GUMR_ENT 0x00000010
-
-/* GUMR [MODE] bit maps */
-#define UCC_FAST_GUMR_HDLC 0x00000000
-#define UCC_FAST_GUMR_QMC 0x00000002
-#define UCC_FAST_GUMR_UART 0x00000004
-#define UCC_FAST_GUMR_BISYNC 0x00000008
-#define UCC_FAST_GUMR_ATM 0x0000000a
-#define UCC_FAST_GUMR_ETH 0x0000000c
-
-/* Transmit On Demand (UTORD) */
-#define UCC_SLOW_TOD 0x8000
-#define UCC_FAST_TOD 0x8000
-
-/* Fast Ethernet (10/100 Mbps) */
-/* Rx virtual FIFO size */
-#define UCC_GETH_URFS_INIT 512
-/* 1/2 urfs */
-#define UCC_GETH_URFET_INIT 256
-/* 3/4 urfs */
-#define UCC_GETH_URFSET_INIT 384
-/* Tx virtual FIFO size */
-#define UCC_GETH_UTFS_INIT 512
-/* 1/2 utfs */
-#define UCC_GETH_UTFET_INIT 256
-#define UCC_GETH_UTFTT_INIT 128
-
-/* Gigabit Ethernet (1000 Mbps) */
-/* Rx virtual FIFO size */
-#define UCC_GETH_URFS_GIGA_INIT 4096/*2048*/
-/* 1/2 urfs */
-#define UCC_GETH_URFET_GIGA_INIT 2048/*1024*/
-/* 3/4 urfs */
-#define UCC_GETH_URFSET_GIGA_INIT 3072/*1536*/
-/* Tx virtual FIFO size */
-#define UCC_GETH_UTFS_GIGA_INIT 8192/*2048*/
-/* 1/2 utfs */
-#define UCC_GETH_UTFET_GIGA_INIT 4096/*1024*/
-#define UCC_GETH_UTFTT_GIGA_INIT 0x400/*0x40*/
-
-/* UCC fast alignment */
-#define UCC_FAST_RX_ALIGN 4
-#define UCC_FAST_MRBLR_ALIGNMENT 4
-#define UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT 8
-
-/* Sizes */
-#define UCC_FAST_RX_VIRTUAL_FIFO_SIZE_PAD 8
-
-/* UCC fast structure. */
-struct ucc_fast_inf {
- int ucc_num;
- qe_clock_e rx_clock;
- qe_clock_e tx_clock;
- enum enet_type eth_type;
-};
-
-struct ucc_fast_priv {
- struct ucc_fast_inf *uf_info;
- ucc_fast_t *uf_regs; /* a pointer to memory map of UCC regs */
- u32 *p_ucce; /* a pointer to the event register */
- u32 *p_uccm; /* a pointer to the mask register */
- int enabled_tx; /* whether UCC is enabled for Tx (ENT) */
- int enabled_rx; /* whether UCC is enabled for Rx (ENR) */
- u32 ucc_fast_tx_virtual_fifo_base_offset;
- u32 ucc_fast_rx_virtual_fifo_base_offset;
-};
-
-void ucc_fast_transmit_on_demand(struct ucc_fast_priv *uccf);
-u32 ucc_fast_get_qe_cr_subblock(int ucc_num);
-void ucc_fast_enable(struct ucc_fast_priv *uccf, comm_dir_e mode);
-void ucc_fast_disable(struct ucc_fast_priv *uccf, comm_dir_e mode);
-int ucc_fast_init(struct ucc_fast_inf *uf_info,
- struct ucc_fast_priv **uccf_ret);
-
-#endif /* __UCCF_H__ */
diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c
deleted file mode 100644
index 31088796435..00000000000
--- a/drivers/qe/uec.c
+++ /dev/null
@@ -1,1436 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2006-2011 Freescale Semiconductor, Inc.
- *
- * Dave Liu <daveliu@freescale.com>
- */
-
-#include <common.h>
-#include <log.h>
-#include <net.h>
-#include <malloc.h>
-#include <linux/delay.h>
-#include <linux/errno.h>
-#include <asm/io.h>
-#include <linux/immap_qe.h>
-#include "uccf.h"
-#include "uec.h"
-#include "uec_phy.h"
-#include "miiphy.h"
-#include <fsl_qe.h>
-#include <phy.h>
-
-#if !defined(CONFIG_DM_ETH)
-/* Default UTBIPAR SMI address */
-#ifndef CONFIG_UTBIPAR_INIT_TBIPA
-#define CONFIG_UTBIPAR_INIT_TBIPA 0x1F
-#endif
-
-static struct uec_inf uec_info[] = {
-#ifdef CONFIG_UEC_ETH1
- STD_UEC_INFO(1), /* UEC1 */
-#endif
-#ifdef CONFIG_UEC_ETH2
- STD_UEC_INFO(2), /* UEC2 */
-#endif
-#ifdef CONFIG_UEC_ETH3
- STD_UEC_INFO(3), /* UEC3 */
-#endif
-#ifdef CONFIG_UEC_ETH4
- STD_UEC_INFO(4), /* UEC4 */
-#endif
-#ifdef CONFIG_UEC_ETH5
- STD_UEC_INFO(5), /* UEC5 */
-#endif
-#ifdef CONFIG_UEC_ETH6
- STD_UEC_INFO(6), /* UEC6 */
-#endif
-#ifdef CONFIG_UEC_ETH7
- STD_UEC_INFO(7), /* UEC7 */
-#endif
-#ifdef CONFIG_UEC_ETH8
- STD_UEC_INFO(8), /* UEC8 */
-#endif
-};
-
-#define MAXCONTROLLERS (8)
-
-static struct eth_device *devlist[MAXCONTROLLERS];
-
-static int uec_mac_enable(struct uec_priv *uec, comm_dir_e mode)
-{
- uec_t *uec_regs;
- u32 maccfg1;
-
- if (!uec) {
- printf("%s: uec not initial\n", __func__);
- return -EINVAL;
- }
- uec_regs = uec->uec_regs;
-
- maccfg1 = in_be32(&uec_regs->maccfg1);
-
- if (mode & COMM_DIR_TX) {
- maccfg1 |= MACCFG1_ENABLE_TX;
- out_be32(&uec_regs->maccfg1, maccfg1);
- uec->mac_tx_enabled = 1;
- }
-
- if (mode & COMM_DIR_RX) {
- maccfg1 |= MACCFG1_ENABLE_RX;
- out_be32(&uec_regs->maccfg1, maccfg1);
- uec->mac_rx_enabled = 1;
- }
-
- return 0;
-}
-
-static int uec_mac_disable(struct uec_priv *uec, comm_dir_e mode)
-{
- uec_t *uec_regs;
- u32 maccfg1;
-
- if (!uec) {
- printf("%s: uec not initial\n", __func__);
- return -EINVAL;
- }
- uec_regs = uec->uec_regs;
-
- maccfg1 = in_be32(&uec_regs->maccfg1);
-
- if (mode & COMM_DIR_TX) {
- maccfg1 &= ~MACCFG1_ENABLE_TX;
- out_be32(&uec_regs->maccfg1, maccfg1);
- uec->mac_tx_enabled = 0;
- }
-
- if (mode & COMM_DIR_RX) {
- maccfg1 &= ~MACCFG1_ENABLE_RX;
- out_be32(&uec_regs->maccfg1, maccfg1);
- uec->mac_rx_enabled = 0;
- }
-
- return 0;
-}
-
-static int uec_graceful_stop_tx(struct uec_priv *uec)
-{
- ucc_fast_t *uf_regs;
- u32 cecr_subblock;
- u32 ucce;
-
- if (!uec || !uec->uccf) {
- printf("%s: No handle passed.\n", __func__);
- return -EINVAL;
- }
-
- uf_regs = uec->uccf->uf_regs;
-
- /* Clear the grace stop event */
- out_be32(&uf_regs->ucce, UCCE_GRA);
-
- /* Issue host command */
- cecr_subblock =
- ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
- qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
- (u8)QE_CR_PROTOCOL_ETHERNET, 0);
-
- /* Wait for command to complete */
- do {
- ucce = in_be32(&uf_regs->ucce);
- } while (!(ucce & UCCE_GRA));
-
- uec->grace_stopped_tx = 1;
-
- return 0;
-}
-
-static int uec_graceful_stop_rx(struct uec_priv *uec)
-{
- u32 cecr_subblock;
- u8 ack;
-
- if (!uec) {
- printf("%s: No handle passed.\n", __func__);
- return -EINVAL;
- }
-
- if (!uec->p_rx_glbl_pram) {
- printf("%s: No init rx global parameter\n", __func__);
- return -EINVAL;
- }
-
- /* Clear acknowledge bit */
- ack = uec->p_rx_glbl_pram->rxgstpack;
- ack &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX;
- uec->p_rx_glbl_pram->rxgstpack = ack;
-
- /* Keep issuing cmd and checking ack bit until it is asserted */
- do {
- /* Issue host command */
- cecr_subblock =
- ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
- qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock,
- (u8)QE_CR_PROTOCOL_ETHERNET, 0);
- ack = uec->p_rx_glbl_pram->rxgstpack;
- } while (!(ack & GRACEFUL_STOP_ACKNOWLEDGE_RX));
-
- uec->grace_stopped_rx = 1;
-
- return 0;
-}
-
-static int uec_restart_tx(struct uec_priv *uec)
-{
- u32 cecr_subblock;
-
- if (!uec || !uec->uec_info) {
- printf("%s: No handle passed.\n", __func__);
- return -EINVAL;
- }
-
- cecr_subblock =
- ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
- qe_issue_cmd(QE_RESTART_TX, cecr_subblock,
- (u8)QE_CR_PROTOCOL_ETHERNET, 0);
-
- uec->grace_stopped_tx = 0;
-
- return 0;
-}
-
-static int uec_restart_rx(struct uec_priv *uec)
-{
- u32 cecr_subblock;
-
- if (!uec || !uec->uec_info) {
- printf("%s: No handle passed.\n", __func__);
- return -EINVAL;
- }
-
- cecr_subblock =
- ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
- qe_issue_cmd(QE_RESTART_RX, cecr_subblock,
- (u8)QE_CR_PROTOCOL_ETHERNET, 0);
-
- uec->grace_stopped_rx = 0;
-
- return 0;
-}
-
-static int uec_open(struct uec_priv *uec, comm_dir_e mode)
-{
- struct ucc_fast_priv *uccf;
-
- if (!uec || !uec->uccf) {
- printf("%s: No handle passed.\n", __func__);
- return -EINVAL;
- }
- uccf = uec->uccf;
-
- /* check if the UCC number is in range. */
- if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) {
- printf("%s: ucc_num out of range.\n", __func__);
- return -EINVAL;
- }
-
- /* Enable MAC */
- uec_mac_enable(uec, mode);
-
- /* Enable UCC fast */
- ucc_fast_enable(uccf, mode);
-
- /* RISC microcode start */
- if ((mode & COMM_DIR_TX) && uec->grace_stopped_tx)
- uec_restart_tx(uec);
- if ((mode & COMM_DIR_RX) && uec->grace_stopped_rx)
- uec_restart_rx(uec);
-
- return 0;
-}
-
-static int uec_stop(struct uec_priv *uec, comm_dir_e mode)
-{
- if (!uec || !uec->uccf) {
- printf("%s: No handle passed.\n", __func__);
- return -EINVAL;
- }
-
- /* check if the UCC number is in range. */
- if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) {
- printf("%s: ucc_num out of range.\n", __func__);
- return -EINVAL;
- }
- /* Stop any transmissions */
- if ((mode & COMM_DIR_TX) && !uec->grace_stopped_tx)
- uec_graceful_stop_tx(uec);
-
- /* Stop any receptions */
- if ((mode & COMM_DIR_RX) && !uec->grace_stopped_rx)
- uec_graceful_stop_rx(uec);
-
- /* Disable the UCC fast */
- ucc_fast_disable(uec->uccf, mode);
-
- /* Disable the MAC */
- uec_mac_disable(uec, mode);
-
- return 0;
-}
-
-static int uec_set_mac_duplex(struct uec_priv *uec, int duplex)
-{
- uec_t *uec_regs;
- u32 maccfg2;
-
- if (!uec) {
- printf("%s: uec not initial\n", __func__);
- return -EINVAL;
- }
- uec_regs = uec->uec_regs;
-
- if (duplex == DUPLEX_HALF) {
- maccfg2 = in_be32(&uec_regs->maccfg2);
- maccfg2 &= ~MACCFG2_FDX;
- out_be32(&uec_regs->maccfg2, maccfg2);
- }
-
- if (duplex == DUPLEX_FULL) {
- maccfg2 = in_be32(&uec_regs->maccfg2);
- maccfg2 |= MACCFG2_FDX;
- out_be32(&uec_regs->maccfg2, maccfg2);
- }
-
- return 0;
-}
-
-static int uec_set_mac_if_mode(struct uec_priv *uec,
- phy_interface_t if_mode, int speed)
-{
- phy_interface_t enet_if_mode;
- uec_t *uec_regs;
- u32 upsmr;
- u32 maccfg2;
-
- if (!uec) {
- printf("%s: uec not initial\n", __func__);
- return -EINVAL;
- }
-
- uec_regs = uec->uec_regs;
- enet_if_mode = if_mode;
-
- maccfg2 = in_be32(&uec_regs->maccfg2);
- maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK;
-
- upsmr = in_be32(&uec->uccf->uf_regs->upsmr);
- upsmr &= ~(UPSMR_RPM | UPSMR_TBIM | UPSMR_R10M | UPSMR_RMM);
-
- switch (speed) {
- case SPEED_10:
- maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
- switch (enet_if_mode) {
- case PHY_INTERFACE_MODE_MII:
- break;
- case PHY_INTERFACE_MODE_RGMII:
- upsmr |= (UPSMR_RPM | UPSMR_R10M);
- break;
- case PHY_INTERFACE_MODE_RMII:
- upsmr |= (UPSMR_R10M | UPSMR_RMM);
- break;
- default:
- return -EINVAL;
- }
- break;
- case SPEED_100:
- maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
- switch (enet_if_mode) {
- case PHY_INTERFACE_MODE_MII:
- break;
- case PHY_INTERFACE_MODE_RGMII:
- upsmr |= UPSMR_RPM;
- break;
- case PHY_INTERFACE_MODE_RMII:
- upsmr |= UPSMR_RMM;
- break;
- default:
- return -EINVAL;
- }
- break;
- case SPEED_1000:
- maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
- switch (enet_if_mode) {
- case PHY_INTERFACE_MODE_GMII:
- break;
- case PHY_INTERFACE_MODE_TBI:
- upsmr |= UPSMR_TBIM;
- break;
- case PHY_INTERFACE_MODE_RTBI:
- upsmr |= (UPSMR_RPM | UPSMR_TBIM);
- break;
- case PHY_INTERFACE_MODE_RGMII_RXID:
- case PHY_INTERFACE_MODE_RGMII_TXID:
- case PHY_INTERFACE_MODE_RGMII_ID:
- case PHY_INTERFACE_MODE_RGMII:
- upsmr |= UPSMR_RPM;
- break;
- case PHY_INTERFACE_MODE_SGMII:
- upsmr |= UPSMR_SGMM;
- break;
- default:
- return -EINVAL;
- }
- break;
- default:
- return -EINVAL;
- }
-
- out_be32(&uec_regs->maccfg2, maccfg2);
- out_be32(&uec->uccf->uf_regs->upsmr, upsmr);
-
- return 0;
-}
-
-static int init_mii_management_configuration(uec_mii_t *uec_mii_regs)
-{
- uint timeout = 0x1000;
- u32 miimcfg = 0;
-
- miimcfg = in_be32(&uec_mii_regs->miimcfg);
- miimcfg |= MIIMCFG_MNGMNT_CLC_DIV_INIT_VALUE;
- out_be32(&uec_mii_regs->miimcfg, miimcfg);
-
- /* Wait until the bus is free */
- while ((in_be32(&uec_mii_regs->miimcfg) & MIIMIND_BUSY) && timeout--)
- ;
- if (timeout <= 0) {
- printf("%s: The MII Bus is stuck!", __func__);
- return -ETIMEDOUT;
- }
-
- return 0;
-}
-
-static int init_phy(struct eth_device *dev)
-{
- struct uec_priv *uec;
- uec_mii_t *umii_regs;
- struct uec_mii_info *mii_info;
- struct phy_info *curphy;
- int err;
-
- uec = (struct uec_priv *)dev->priv;
- umii_regs = uec->uec_mii_regs;
-
- uec->oldlink = 0;
- uec->oldspeed = 0;
- uec->oldduplex = -1;
-
- mii_info = malloc(sizeof(*mii_info));
- if (!mii_info) {
- printf("%s: Could not allocate mii_info", dev->name);
- return -ENOMEM;
- }
- memset(mii_info, 0, sizeof(*mii_info));
-
- if (uec->uec_info->uf_info.eth_type == GIGA_ETH)
- mii_info->speed = SPEED_1000;
- else
- mii_info->speed = SPEED_100;
-
- mii_info->duplex = DUPLEX_FULL;
- mii_info->pause = 0;
- mii_info->link = 1;
-
- mii_info->advertising = (ADVERTISED_10baseT_Half |
- ADVERTISED_10baseT_Full |
- ADVERTISED_100baseT_Half |
- ADVERTISED_100baseT_Full |
- ADVERTISED_1000baseT_Full);
- mii_info->autoneg = 1;
- mii_info->mii_id = uec->uec_info->phy_address;
- mii_info->dev = dev;
-
- mii_info->mdio_read = &uec_read_phy_reg;
- mii_info->mdio_write = &uec_write_phy_reg;
-
- uec->mii_info = mii_info;
-
- qe_set_mii_clk_src(uec->uec_info->uf_info.ucc_num);
-
- if (init_mii_management_configuration(umii_regs)) {
- printf("%s: The MII Bus is stuck!", dev->name);
- err = -1;
- goto bus_fail;
- }
-
- /* get info for this PHY */
- curphy = uec_get_phy_info(uec->mii_info);
- if (!curphy) {
- printf("%s: No PHY found", dev->name);
- err = -1;
- goto no_phy;
- }
-
- mii_info->phyinfo = curphy;
-
- /* Run the commands which initialize the PHY */
- if (curphy->init) {
- err = curphy->init(uec->mii_info);
- if (err)
- goto phy_init_fail;
- }
-
- return 0;
-
-phy_init_fail:
-no_phy:
-bus_fail:
- free(mii_info);
- return err;
-}
-
-static void adjust_link(struct eth_device *dev)
-{
- struct uec_priv *uec = (struct uec_priv *)dev->priv;
- struct uec_mii_info *mii_info = uec->mii_info;
-
- if (mii_info->link) {
- /*
- * Now we make sure that we can be in full duplex mode.
- * If not, we operate in half-duplex mode.
- */
- if (mii_info->duplex != uec->oldduplex) {
- if (!(mii_info->duplex)) {
- uec_set_mac_duplex(uec, DUPLEX_HALF);
- printf("%s: Half Duplex\n", dev->name);
- } else {
- uec_set_mac_duplex(uec, DUPLEX_FULL);
- printf("%s: Full Duplex\n", dev->name);
- }
- uec->oldduplex = mii_info->duplex;
- }
-
- if (mii_info->speed != uec->oldspeed) {
- phy_interface_t mode =
- uec->uec_info->enet_interface_type;
- if (uec->uec_info->uf_info.eth_type == GIGA_ETH) {
- switch (mii_info->speed) {
- case SPEED_1000:
- break;
- case SPEED_100:
- printf("switching to rgmii 100\n");
- mode = PHY_INTERFACE_MODE_RGMII;
- break;
- case SPEED_10:
- printf("switching to rgmii 10\n");
- mode = PHY_INTERFACE_MODE_RGMII;
- break;
- default:
- printf("%s: Ack,Speed(%d)is illegal\n",
- dev->name, mii_info->speed);
- break;
- }
- }
-
- /* change phy */
- change_phy_interface_mode(dev, mode, mii_info->speed);
- /* change the MAC interface mode */
- uec_set_mac_if_mode(uec, mode, mii_info->speed);
-
- printf("%s: Speed %dBT\n", dev->name, mii_info->speed);
- uec->oldspeed = mii_info->speed;
- }
-
- if (!uec->oldlink) {
- printf("%s: Link is up\n", dev->name);
- uec->oldlink = 1;
- }
-
- } else { /* if (mii_info->link) */
- if (uec->oldlink) {
- printf("%s: Link is down\n", dev->name);
- uec->oldlink = 0;
- uec->oldspeed = 0;
- uec->oldduplex = -1;
- }
- }
-}
-
-static void phy_change(struct eth_device *dev)
-{
- struct uec_priv *uec = (struct uec_priv *)dev->priv;
-
-#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
- ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
-
- /* QE9 and QE12 need to be set for enabling QE MII management signals */
- setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9);
- setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
-#endif
-
- /* Update the link, speed, duplex */
- uec->mii_info->phyinfo->read_status(uec->mii_info);
-
-#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
- /*
- * QE12 is muxed with LBCTL, it needs to be released for enabling
- * LBCTL signal for LBC usage.
- */
- clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
-#endif
-
- /* Adjust the interface according to speed */
- adjust_link(dev);
-}
-
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
-
-/*
- * Find a device index from the devlist by name
- *
- * Returns:
- * The index where the device is located, -1 on error
- */
-static int uec_miiphy_find_dev_by_name(const char *devname)
-{
- int i;
-
- for (i = 0; i < MAXCONTROLLERS; i++) {
- if (strncmp(devname, devlist[i]->name, strlen(devname)) == 0)
- break;
- }
-
- /* If device cannot be found, returns -1 */
- if (i == MAXCONTROLLERS) {
- debug("%s: device %s not found in devlist\n", __func__,
- devname);
- i = -1;
- }
-
- return i;
-}
-
-/*
- * Read a MII PHY register.
- *
- * Returns:
- * 0 on success
- */
-static int uec_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg)
-{
- unsigned short value = 0;
- int devindex = 0;
-
- if (!bus->name) {
- debug("%s: NULL pointer given\n", __func__);
- } else {
- devindex = uec_miiphy_find_dev_by_name(bus->name);
- if (devindex >= 0)
- value = uec_read_phy_reg(devlist[devindex], addr, reg);
- }
- return value;
-}
-
-/*
- * Write a MII PHY register.
- *
- * Returns:
- * 0 on success
- */
-static int uec_miiphy_write(struct mii_dev *bus, int addr, int devad, int reg,
- u16 value)
-{
- int devindex = 0;
-
- if (!bus->name) {
- debug("%s: NULL pointer given\n", __func__);
- } else {
- devindex = uec_miiphy_find_dev_by_name(bus->name);
- if (devindex >= 0)
- uec_write_phy_reg(devlist[devindex], addr, reg, value);
- }
- return 0;
-}
-#endif
-
-static int uec_set_mac_address(struct uec_priv *uec, u8 *mac_addr)
-{
- uec_t *uec_regs;
- u32 mac_addr1;
- u32 mac_addr2;
-
- if (!uec) {
- printf("%s: uec not initial\n", __func__);
- return -EINVAL;
- }
-
- uec_regs = uec->uec_regs;
-
- /*
- * if a station address of 0x12345678ABCD, perform a write to
- * MACSTNADDR1 of 0xCDAB7856,
- * MACSTNADDR2 of 0x34120000
- */
-
- mac_addr1 = (mac_addr[5] << 24) | (mac_addr[4] << 16) |
- (mac_addr[3] << 8) | (mac_addr[2]);
- out_be32(&uec_regs->macstnaddr1, mac_addr1);
-
- mac_addr2 = ((mac_addr[1] << 24) | (mac_addr[0] << 16)) & 0xffff0000;
- out_be32(&uec_regs->macstnaddr2, mac_addr2);
-
- return 0;
-}
-
-static int uec_convert_threads_num(enum uec_num_of_threads threads_num,
- int *threads_num_ret)
-{
- int num_threads_numerica;
-
- switch (threads_num) {
- case UEC_NUM_OF_THREADS_1:
- num_threads_numerica = 1;
- break;
- case UEC_NUM_OF_THREADS_2:
- num_threads_numerica = 2;
- break;
- case UEC_NUM_OF_THREADS_4:
- num_threads_numerica = 4;
- break;
- case UEC_NUM_OF_THREADS_6:
- num_threads_numerica = 6;
- break;
- case UEC_NUM_OF_THREADS_8:
- num_threads_numerica = 8;
- break;
- default:
- printf("%s: Bad number of threads value.",
- __func__);
- return -EINVAL;
- }
-
- *threads_num_ret = num_threads_numerica;
-
- return 0;
-}
-
-static void uec_init_tx_parameter(struct uec_priv *uec, int num_threads_tx)
-{
- struct uec_inf *uec_info;
- u32 end_bd;
- u8 bmrx = 0;
- int i;
-
- uec_info = uec->uec_info;
-
- /* Alloc global Tx parameter RAM page */
- uec->tx_glbl_pram_offset =
- qe_muram_alloc(sizeof(struct uec_tx_global_pram),
- UEC_TX_GLOBAL_PRAM_ALIGNMENT);
- uec->p_tx_glbl_pram = (struct uec_tx_global_pram *)
- qe_muram_addr(uec->tx_glbl_pram_offset);
-
- /* Zero the global Tx prameter RAM */
- memset(uec->p_tx_glbl_pram, 0, sizeof(struct uec_tx_global_pram));
-
- /* Init global Tx parameter RAM */
-
- /* TEMODER, RMON statistics disable, one Tx queue */
- out_be16(&uec->p_tx_glbl_pram->temoder, TEMODER_INIT_VALUE);
-
- /* SQPTR */
- uec->send_q_mem_reg_offset =
- qe_muram_alloc(sizeof(struct uec_send_queue_qd),
- UEC_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT);
- uec->p_send_q_mem_reg = (struct uec_send_queue_mem_region *)
- qe_muram_addr(uec->send_q_mem_reg_offset);
- out_be32(&uec->p_tx_glbl_pram->sqptr, uec->send_q_mem_reg_offset);
-
- /* Setup the table with TxBDs ring */
- end_bd = (u32)uec->p_tx_bd_ring + (uec_info->tx_bd_ring_len - 1)
- * SIZEOFBD;
- out_be32(&uec->p_send_q_mem_reg->sqqd[0].bd_ring_base,
- (u32)(uec->p_tx_bd_ring));
- out_be32(&uec->p_send_q_mem_reg->sqqd[0].last_bd_completed_address,
- end_bd);
-
- /* Scheduler Base Pointer, we have only one Tx queue, no need it */
- out_be32(&uec->p_tx_glbl_pram->schedulerbasepointer, 0);
-
- /* TxRMON Base Pointer, TxRMON disable, we don't need it */
- out_be32(&uec->p_tx_glbl_pram->txrmonbaseptr, 0);
-
- /* TSTATE, global snooping, big endian, the CSB bus selected */
- bmrx = BMR_INIT_VALUE;
- out_be32(&uec->p_tx_glbl_pram->tstate, ((u32)(bmrx) << BMR_SHIFT));
-
- /* IPH_Offset */
- for (i = 0; i < MAX_IPH_OFFSET_ENTRY; i++)
- out_8(&uec->p_tx_glbl_pram->iphoffset[i], 0);
-
- /* VTAG table */
- for (i = 0; i < UEC_TX_VTAG_TABLE_ENTRY_MAX; i++)
- out_be32(&uec->p_tx_glbl_pram->vtagtable[i], 0);
-
- /* TQPTR */
- uec->thread_dat_tx_offset =
- qe_muram_alloc(num_threads_tx *
- sizeof(struct uec_thread_data_tx) +
- 32 * (num_threads_tx == 1),
- UEC_THREAD_DATA_ALIGNMENT);
-
- uec->p_thread_data_tx = (struct uec_thread_data_tx *)
- qe_muram_addr(uec->thread_dat_tx_offset);
- out_be32(&uec->p_tx_glbl_pram->tqptr, uec->thread_dat_tx_offset);
-}
-
-static void uec_init_rx_parameter(struct uec_priv *uec, int num_threads_rx)
-{
- u8 bmrx = 0;
- int i;
- struct uec_82xx_add_filtering_pram *p_af_pram;
-
- /* Allocate global Rx parameter RAM page */
- uec->rx_glbl_pram_offset =
- qe_muram_alloc(sizeof(struct uec_rx_global_pram),
- UEC_RX_GLOBAL_PRAM_ALIGNMENT);
- uec->p_rx_glbl_pram = (struct uec_rx_global_pram *)
- qe_muram_addr(uec->rx_glbl_pram_offset);
-
- /* Zero Global Rx parameter RAM */
- memset(uec->p_rx_glbl_pram, 0, sizeof(struct uec_rx_global_pram));
-
- /* Init global Rx parameter RAM */
- /*
- * REMODER, Extended feature mode disable, VLAN disable,
- * LossLess flow control disable, Receive firmware statisic disable,
- * Extended address parsing mode disable, One Rx queues,
- * Dynamic maximum/minimum frame length disable, IP checksum check
- * disable, IP address alignment disable
- */
- out_be32(&uec->p_rx_glbl_pram->remoder, REMODER_INIT_VALUE);
-
- /* RQPTR */
- uec->thread_dat_rx_offset =
- qe_muram_alloc(num_threads_rx *
- sizeof(struct uec_thread_data_rx),
- UEC_THREAD_DATA_ALIGNMENT);
- uec->p_thread_data_rx = (struct uec_thread_data_rx *)
- qe_muram_addr(uec->thread_dat_rx_offset);
- out_be32(&uec->p_rx_glbl_pram->rqptr, uec->thread_dat_rx_offset);
-
- /* Type_or_Len */
- out_be16(&uec->p_rx_glbl_pram->typeorlen, 3072);
-
- /* RxRMON base pointer, we don't need it */
- out_be32(&uec->p_rx_glbl_pram->rxrmonbaseptr, 0);
-
- /* IntCoalescingPTR, we don't need it, no interrupt */
- out_be32(&uec->p_rx_glbl_pram->intcoalescingptr, 0);
-
- /* RSTATE, global snooping, big endian, the CSB bus selected */
- bmrx = BMR_INIT_VALUE;
- out_8(&uec->p_rx_glbl_pram->rstate, bmrx);
-
- /* MRBLR */
- out_be16(&uec->p_rx_glbl_pram->mrblr, MAX_RXBUF_LEN);
-
- /* RBDQPTR */
- uec->rx_bd_qs_tbl_offset =
- qe_muram_alloc(sizeof(struct uec_rx_bd_queues_entry) +
- sizeof(struct uec_rx_pref_bds),
- UEC_RX_BD_QUEUES_ALIGNMENT);
- uec->p_rx_bd_qs_tbl = (struct uec_rx_bd_queues_entry *)
- qe_muram_addr(uec->rx_bd_qs_tbl_offset);
-
- /* Zero it */
- memset(uec->p_rx_bd_qs_tbl, 0, sizeof(struct uec_rx_bd_queues_entry) +
- sizeof(struct uec_rx_pref_bds));
- out_be32(&uec->p_rx_glbl_pram->rbdqptr, uec->rx_bd_qs_tbl_offset);
- out_be32(&uec->p_rx_bd_qs_tbl->externalbdbaseptr,
- (u32)uec->p_rx_bd_ring);
-
- /* MFLR */
- out_be16(&uec->p_rx_glbl_pram->mflr, MAX_FRAME_LEN);
- /* MINFLR */
- out_be16(&uec->p_rx_glbl_pram->minflr, MIN_FRAME_LEN);
- /* MAXD1 */
- out_be16(&uec->p_rx_glbl_pram->maxd1, MAX_DMA1_LEN);
- /* MAXD2 */
- out_be16(&uec->p_rx_glbl_pram->maxd2, MAX_DMA2_LEN);
- /* ECAM_PTR */
- out_be32(&uec->p_rx_glbl_pram->ecamptr, 0);
- /* L2QT */
- out_be32(&uec->p_rx_glbl_pram->l2qt, 0);
- /* L3QT */
- for (i = 0; i < 8; i++)
- out_be32(&uec->p_rx_glbl_pram->l3qt[i], 0);
-
- /* VLAN_TYPE */
- out_be16(&uec->p_rx_glbl_pram->vlantype, 0x8100);
- /* TCI */
- out_be16(&uec->p_rx_glbl_pram->vlantci, 0);
-
- /* Clear PQ2 style address filtering hash table */
- p_af_pram = (struct uec_82xx_add_filtering_pram *)
- uec->p_rx_glbl_pram->addressfiltering;
-
- p_af_pram->iaddr_h = 0;
- p_af_pram->iaddr_l = 0;
- p_af_pram->gaddr_h = 0;
- p_af_pram->gaddr_l = 0;
-}
-
-static int uec_issue_init_enet_rxtx_cmd(struct uec_priv *uec,
- int thread_tx, int thread_rx)
-{
- struct uec_init_cmd_pram *p_init_enet_param;
- u32 init_enet_param_offset;
- struct uec_inf *uec_info;
- struct ucc_fast_inf *uf_info;
- int i;
- int snum;
- u32 off;
- u32 entry_val;
- u32 command;
- u32 cecr_subblock;
-
- uec_info = uec->uec_info;
- uf_info = &uec_info->uf_info;
-
- /* Allocate init enet command parameter */
- uec->init_enet_param_offset =
- qe_muram_alloc(sizeof(struct uec_init_cmd_pram), 4);
- init_enet_param_offset = uec->init_enet_param_offset;
- uec->p_init_enet_param = (struct uec_init_cmd_pram *)
- qe_muram_addr(uec->init_enet_param_offset);
-
- /* Zero init enet command struct */
- memset((void *)uec->p_init_enet_param, 0,
- sizeof(struct uec_init_cmd_pram));
-
- /* Init the command struct */
- p_init_enet_param = uec->p_init_enet_param;
- p_init_enet_param->resinit0 = ENET_INIT_PARAM_MAGIC_RES_INIT0;
- p_init_enet_param->resinit1 = ENET_INIT_PARAM_MAGIC_RES_INIT1;
- p_init_enet_param->resinit2 = ENET_INIT_PARAM_MAGIC_RES_INIT2;
- p_init_enet_param->resinit3 = ENET_INIT_PARAM_MAGIC_RES_INIT3;
- p_init_enet_param->resinit4 = ENET_INIT_PARAM_MAGIC_RES_INIT4;
- p_init_enet_param->largestexternallookupkeysize = 0;
-
- p_init_enet_param->rgftgfrxglobal |= ((u32)uec_info->num_threads_rx)
- << ENET_INIT_PARAM_RGF_SHIFT;
- p_init_enet_param->rgftgfrxglobal |= ((u32)uec_info->num_threads_tx)
- << ENET_INIT_PARAM_TGF_SHIFT;
-
- /* Init Rx global parameter pointer */
- p_init_enet_param->rgftgfrxglobal |= uec->rx_glbl_pram_offset |
- (u32)uec_info->risc_rx;
-
- /* Init Rx threads */
- for (i = 0; i < (thread_rx + 1); i++) {
- snum = qe_get_snum();
- if (snum < 0) {
- printf("%s can not get snum\n", __func__);
- return -ENOMEM;
- }
-
- if (i == 0) {
- off = 0;
- } else {
- off = qe_muram_alloc(sizeof(struct uec_thread_rx_pram),
- UEC_THREAD_RX_PRAM_ALIGNMENT);
- }
-
- entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) |
- off | (u32)uec_info->risc_rx;
- p_init_enet_param->rxthread[i] = entry_val;
- }
-
- /* Init Tx global parameter pointer */
- p_init_enet_param->txglobal = uec->tx_glbl_pram_offset |
- (u32)uec_info->risc_tx;
-
- /* Init Tx threads */
- for (i = 0; i < thread_tx; i++) {
- snum = qe_get_snum();
- if (snum < 0) {
- printf("%s can not get snum\n", __func__);
- return -ENOMEM;
- }
-
- off = qe_muram_alloc(sizeof(struct uec_thread_tx_pram),
- UEC_THREAD_TX_PRAM_ALIGNMENT);
-
- entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) |
- off | (u32)uec_info->risc_tx;
- p_init_enet_param->txthread[i] = entry_val;
- }
-
- __asm__ __volatile__("sync");
-
- /* Issue QE command */
- command = QE_INIT_TX_RX;
- cecr_subblock = ucc_fast_get_qe_cr_subblock(uf_info->ucc_num);
- qe_issue_cmd(command, cecr_subblock, (u8)QE_CR_PROTOCOL_ETHERNET,
- init_enet_param_offset);
-
- return 0;
-}
-
-static int uec_startup(struct uec_priv *uec)
-{
- struct uec_inf *uec_info;
- struct ucc_fast_inf *uf_info;
- struct ucc_fast_priv *uccf;
- ucc_fast_t *uf_regs;
- uec_t *uec_regs;
- int num_threads_tx;
- int num_threads_rx;
- u32 utbipar;
- u32 length;
- u32 align;
- struct buffer_descriptor *bd;
- u8 *buf;
- int i;
-
- if (!uec || !uec->uec_info) {
- printf("%s: uec or uec_info not initial\n", __func__);
- return -EINVAL;
- }
-
- uec_info = uec->uec_info;
- uf_info = &uec_info->uf_info;
-
- /* Check if Rx BD ring len is illegal */
- if (uec_info->rx_bd_ring_len < UEC_RX_BD_RING_SIZE_MIN ||
- (uec_info->rx_bd_ring_len % UEC_RX_BD_RING_SIZE_ALIGNMENT)) {
- printf("%s: Rx BD ring len must be multiple of 4, and > 8.\n",
- __func__);
- return -EINVAL;
- }
-
- /* Check if Tx BD ring len is illegal */
- if (uec_info->tx_bd_ring_len < UEC_TX_BD_RING_SIZE_MIN) {
- printf("%s: Tx BD ring length must not be smaller than 2.\n",
- __func__);
- return -EINVAL;
- }
-
- /* Check if MRBLR is illegal */
- if (MAX_RXBUF_LEN == 0 || MAX_RXBUF_LEN % UEC_MRBLR_ALIGNMENT) {
- printf("%s: max rx buffer length must be mutliple of 128.\n",
- __func__);
- return -EINVAL;
- }
-
- /* Both Rx and Tx are stopped */
- uec->grace_stopped_rx = 1;
- uec->grace_stopped_tx = 1;
-
- /* Init UCC fast */
- if (ucc_fast_init(uf_info, &uccf)) {
- printf("%s: failed to init ucc fast\n", __func__);
- return -ENOMEM;
- }
-
- /* Save uccf */
- uec->uccf = uccf;
-
- /* Convert the Tx threads number */
- if (uec_convert_threads_num(uec_info->num_threads_tx,
- &num_threads_tx)) {
- return -EINVAL;
- }
-
- /* Convert the Rx threads number */
- if (uec_convert_threads_num(uec_info->num_threads_rx,
- &num_threads_rx)) {
- return -EINVAL;
- }
-
- uf_regs = uccf->uf_regs;
-
- /* UEC register is following UCC fast registers */
- uec_regs = (uec_t *)(&uf_regs->ucc_eth);
-
- /* Save the UEC register pointer to UEC private struct */
- uec->uec_regs = uec_regs;
-
- /* Init UPSMR, enable hardware statistics (UCC) */
- out_be32(&uec->uccf->uf_regs->upsmr, UPSMR_INIT_VALUE);
-
- /* Init MACCFG1, flow control disable, disable Tx and Rx */
- out_be32(&uec_regs->maccfg1, MACCFG1_INIT_VALUE);
-
- /* Init MACCFG2, length check, MAC PAD and CRC enable */
- out_be32(&uec_regs->maccfg2, MACCFG2_INIT_VALUE);
-
- /* Setup MAC interface mode */
- uec_set_mac_if_mode(uec, uec_info->enet_interface_type,
- uec_info->speed);
-
- /* Setup MII management base */
-#ifndef CONFIG_eTSEC_MDIO_BUS
- uec->uec_mii_regs = (uec_mii_t *)(&uec_regs->miimcfg);
-#else
- uec->uec_mii_regs = (uec_mii_t *)CONFIG_MIIM_ADDRESS;
-#endif
-
- /* Setup MII master clock source */
- qe_set_mii_clk_src(uec_info->uf_info.ucc_num);
-
- /* Setup UTBIPAR */
- utbipar = in_be32(&uec_regs->utbipar);
- utbipar &= ~UTBIPAR_PHY_ADDRESS_MASK;
-
- /* Initialize UTBIPAR address to CONFIG_UTBIPAR_INIT_TBIPA for ALL UEC.
- * This frees up the remaining SMI addresses for use.
- */
- utbipar |= CONFIG_UTBIPAR_INIT_TBIPA << UTBIPAR_PHY_ADDRESS_SHIFT;
- out_be32(&uec_regs->utbipar, utbipar);
-
- /* Configure the TBI for SGMII operation */
- if (uec->uec_info->enet_interface_type == PHY_INTERFACE_MODE_SGMII &&
- uec->uec_info->speed == SPEED_1000) {
- uec_write_phy_reg(uec->dev, uec_regs->utbipar,
- ENET_TBI_MII_ANA, TBIANA_SETTINGS);
-
- uec_write_phy_reg(uec->dev, uec_regs->utbipar,
- ENET_TBI_MII_TBICON, TBICON_CLK_SELECT);
-
- uec_write_phy_reg(uec->dev, uec_regs->utbipar,
- ENET_TBI_MII_CR, TBICR_SETTINGS);
- }
-
- /* Allocate Tx BDs */
- length = ((uec_info->tx_bd_ring_len * SIZEOFBD) /
- UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) *
- UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
- if ((uec_info->tx_bd_ring_len * SIZEOFBD) %
- UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) {
- length += UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
- }
-
- align = UEC_TX_BD_RING_ALIGNMENT;
- uec->tx_bd_ring_offset = (u32)malloc((u32)(length + align));
- if (uec->tx_bd_ring_offset != 0) {
- uec->p_tx_bd_ring = (u8 *)((uec->tx_bd_ring_offset + align)
- & ~(align - 1));
- }
-
- /* Zero all of Tx BDs */
- memset((void *)(uec->tx_bd_ring_offset), 0, length + align);
-
- /* Allocate Rx BDs */
- length = uec_info->rx_bd_ring_len * SIZEOFBD;
- align = UEC_RX_BD_RING_ALIGNMENT;
- uec->rx_bd_ring_offset = (u32)(malloc((u32)(length + align)));
- if (uec->rx_bd_ring_offset != 0) {
- uec->p_rx_bd_ring = (u8 *)((uec->rx_bd_ring_offset + align)
- & ~(align - 1));
- }
-
- /* Zero all of Rx BDs */
- memset((void *)(uec->rx_bd_ring_offset), 0, length + align);
-
- /* Allocate Rx buffer */
- length = uec_info->rx_bd_ring_len * MAX_RXBUF_LEN;
- align = UEC_RX_DATA_BUF_ALIGNMENT;
- uec->rx_buf_offset = (u32)malloc(length + align);
- if (uec->rx_buf_offset != 0) {
- uec->p_rx_buf = (u8 *)((uec->rx_buf_offset + align)
- & ~(align - 1));
- }
-
- /* Zero all of the Rx buffer */
- memset((void *)(uec->rx_buf_offset), 0, length + align);
-
- /* Init TxBD ring */
- bd = (struct buffer_descriptor *)uec->p_tx_bd_ring;
- uec->tx_bd = bd;
-
- for (i = 0; i < uec_info->tx_bd_ring_len; i++) {
- BD_DATA_CLEAR(bd);
- BD_STATUS_SET(bd, 0);
- BD_LENGTH_SET(bd, 0);
- bd++;
- }
- BD_STATUS_SET((--bd), TX_BD_WRAP);
-
- /* Init RxBD ring */
- bd = (struct buffer_descriptor *)uec->p_rx_bd_ring;
- uec->rx_bd = bd;
- buf = uec->p_rx_buf;
- for (i = 0; i < uec_info->rx_bd_ring_len; i++) {
- BD_DATA_SET(bd, buf);
- BD_LENGTH_SET(bd, 0);
- BD_STATUS_SET(bd, RX_BD_EMPTY);
- buf += MAX_RXBUF_LEN;
- bd++;
- }
- BD_STATUS_SET((--bd), RX_BD_WRAP | RX_BD_EMPTY);
-
- /* Init global Tx parameter RAM */
- uec_init_tx_parameter(uec, num_threads_tx);
-
- /* Init global Rx parameter RAM */
- uec_init_rx_parameter(uec, num_threads_rx);
-
- /* Init ethernet Tx and Rx parameter command */
- if (uec_issue_init_enet_rxtx_cmd(uec, num_threads_tx,
- num_threads_rx)) {
- printf("%s issue init enet cmd failed\n", __func__);
- return -ENOMEM;
- }
-
- return 0;
-}
-
-static int uec_init(struct eth_device *dev, struct bd_info *bd)
-{
- struct uec_priv *uec;
- int err, i;
- struct phy_info *curphy;
-#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
- ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
-#endif
-
- uec = (struct uec_priv *)dev->priv;
-
- if (!uec->the_first_run) {
-#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
- /*
- * QE9 and QE12 need to be set for enabling QE MII
- * management signals
- */
- setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9);
- setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
-#endif
-
- err = init_phy(dev);
- if (err) {
- printf("%s: Cannot initialize PHY, aborting.\n",
- dev->name);
- return err;
- }
-
- curphy = uec->mii_info->phyinfo;
-
- if (curphy->config_aneg) {
- err = curphy->config_aneg(uec->mii_info);
- if (err) {
- printf("%s: Can't negotiate PHY\n", dev->name);
- return err;
- }
- }
-
- /* Give PHYs up to 5 sec to report a link */
- i = 50;
- do {
- err = curphy->read_status(uec->mii_info);
- if (!(((i-- > 0) && !uec->mii_info->link) || err))
- break;
- mdelay(100);
- } while (1);
-
-#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
- /* QE12 needs to be released for enabling LBCTL signal*/
- clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
-#endif
-
- if (err || i <= 0)
- printf("warning: %s: timeout on PHY link\n", dev->name);
-
- adjust_link(dev);
- uec->the_first_run = 1;
- }
-
- /* Set up the MAC address */
- if (dev->enetaddr[0] & 0x01) {
- printf("%s: MacAddress is multcast address\n",
- __func__);
- return -1;
- }
- uec_set_mac_address(uec, dev->enetaddr);
-
- err = uec_open(uec, COMM_DIR_RX_AND_TX);
- if (err) {
- printf("%s: cannot enable UEC device\n", dev->name);
- return -1;
- }
-
- phy_change(dev);
-
- return uec->mii_info->link ? 0 : -1;
-}
-
-static void uec_halt(struct eth_device *dev)
-{
- struct uec_priv *uec = (struct uec_priv *)dev->priv;
-
- uec_stop(uec, COMM_DIR_RX_AND_TX);
-}
-
-static int uec_send(struct eth_device *dev, void *buf, int len)
-{
- struct uec_priv *uec;
- struct ucc_fast_priv *uccf;
- struct buffer_descriptor *bd;
- u16 status;
- int i;
- int result = 0;
-
- uec = (struct uec_priv *)dev->priv;
- uccf = uec->uccf;
- bd = uec->tx_bd;
-
- /* Find an empty TxBD */
- for (i = 0; BD_STATUS(bd) & TX_BD_READY; i++) {
- if (i > 0x100000) {
- printf("%s: tx buffer not ready\n", dev->name);
- return result;
- }
- }
-
- /* Init TxBD */
- BD_DATA_SET(bd, buf);
- BD_LENGTH_SET(bd, len);
- status = BD_STATUS(bd);
- status &= BD_WRAP;
- status |= (TX_BD_READY | TX_BD_LAST);
- BD_STATUS_SET(bd, status);
-
- /* Tell UCC to transmit the buffer */
- ucc_fast_transmit_on_demand(uccf);
-
- /* Wait for buffer to be transmitted */
- for (i = 0; BD_STATUS(bd) & TX_BD_READY; i++) {
- if (i > 0x100000) {
- printf("%s: tx error\n", dev->name);
- return result;
- }
- }
-
- /* Ok, the buffer be transimitted */
- BD_ADVANCE(bd, status, uec->p_tx_bd_ring);
- uec->tx_bd = bd;
- result = 1;
-
- return result;
-}
-
-static int uec_recv(struct eth_device *dev)
-{
- struct uec_priv *uec = dev->priv;
- struct buffer_descriptor *bd;
- u16 status;
- u16 len;
- u8 *data;
-
- bd = uec->rx_bd;
- status = BD_STATUS(bd);
-
- while (!(status & RX_BD_EMPTY)) {
- if (!(status & RX_BD_ERROR)) {
- data = BD_DATA(bd);
- len = BD_LENGTH(bd);
- net_process_received_packet(data, len);
- } else {
- printf("%s: Rx error\n", dev->name);
- }
- status &= BD_CLEAN;
- BD_LENGTH_SET(bd, 0);
- BD_STATUS_SET(bd, status | RX_BD_EMPTY);
- BD_ADVANCE(bd, status, uec->p_rx_bd_ring);
- status = BD_STATUS(bd);
- }
- uec->rx_bd = bd;
-
- return 1;
-}
-
-int uec_initialize(struct bd_info *bis, struct uec_inf *uec_info)
-{
- struct eth_device *dev;
- int i;
- struct uec_priv *uec;
- int err;
-
- dev = (struct eth_device *)malloc(sizeof(struct eth_device));
- if (!dev)
- return 0;
- memset(dev, 0, sizeof(struct eth_device));
-
- /* Allocate the UEC private struct */
- uec = (struct uec_priv *)malloc(sizeof(struct uec_priv));
- if (!uec)
- return -ENOMEM;
-
- memset(uec, 0, sizeof(struct uec_priv));
-
- /* Adjust uec_info */
-#if (MAX_QE_RISC == 4)
- uec_info->risc_tx = QE_RISC_ALLOCATION_FOUR_RISCS;
- uec_info->risc_rx = QE_RISC_ALLOCATION_FOUR_RISCS;
-#endif
-
- devlist[uec_info->uf_info.ucc_num] = dev;
-
- uec->uec_info = uec_info;
- uec->dev = dev;
-
- sprintf(dev->name, "UEC%d", uec_info->uf_info.ucc_num);
- dev->iobase = 0;
- dev->priv = (void *)uec;
- dev->init = uec_init;
- dev->halt = uec_halt;
- dev->send = uec_send;
- dev->recv = uec_recv;
-
- /* Clear the ethnet address */
- for (i = 0; i < 6; i++)
- dev->enetaddr[i] = 0;
-
- eth_register(dev);
-
- err = uec_startup(uec);
- if (err) {
- printf("%s: Cannot configure net device, aborting.", dev->name);
- return err;
- }
-
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
- int retval;
- struct mii_dev *mdiodev = mdio_alloc();
-
- if (!mdiodev)
- return -ENOMEM;
- strlcpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
- mdiodev->read = uec_miiphy_read;
- mdiodev->write = uec_miiphy_write;
-
- retval = mdio_register(mdiodev);
- if (retval < 0)
- return retval;
-#endif
-
- return 1;
-}
-
-int uec_eth_init(struct bd_info *bis, struct uec_inf *uecs, int num)
-{
- int i;
-
- for (i = 0; i < num; i++)
- uec_initialize(bis, &uecs[i]);
-
- return 0;
-}
-
-int uec_standard_init(struct bd_info *bis)
-{
- return uec_eth_init(bis, uec_info, ARRAY_SIZE(uec_info));
-}
-#endif
diff --git a/drivers/qe/uec.h b/drivers/qe/uec.h
deleted file mode 100644
index 63371e71bf7..00000000000
--- a/drivers/qe/uec.h
+++ /dev/null
@@ -1,692 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2006-2010 Freescale Semiconductor, Inc.
- *
- * Dave Liu <daveliu@freescale.com>
- * based on source code of Shlomi Gridish
- */
-
-#ifndef __UEC_H__
-#define __UEC_H__
-
-#include "uccf.h"
-#include <fsl_qe.h>
-#include <phy.h>
-
-#define MAX_TX_THREADS 8
-#define MAX_RX_THREADS 8
-#define MAX_TX_QUEUES 8
-#define MAX_RX_QUEUES 8
-#define MAX_PREFETCHED_BDS 4
-#define MAX_IPH_OFFSET_ENTRY 8
-#define MAX_ENET_INIT_PARAM_ENTRIES_RX 9
-#define MAX_ENET_INIT_PARAM_ENTRIES_TX 8
-
-/* UEC UPSMR (Protocol Specific Mode Register)
- */
-#define UPSMR_ECM 0x04000000 /* Enable CAM Miss */
-#define UPSMR_HSE 0x02000000 /* Hardware Statistics Enable */
-#define UPSMR_PRO 0x00400000 /* Promiscuous */
-#define UPSMR_CAP 0x00200000 /* CAM polarity */
-#define UPSMR_RSH 0x00100000 /* Receive Short Frames */
-#define UPSMR_RPM 0x00080000 /* Reduced Pin Mode interfaces */
-#define UPSMR_R10M 0x00040000 /* RGMII/RMII 10 Mode */
-#define UPSMR_RLPB 0x00020000 /* RMII Loopback Mode */
-#define UPSMR_TBIM 0x00010000 /* Ten-bit Interface Mode */
-#define UPSMR_RMM 0x00001000 /* RMII/RGMII Mode */
-#define UPSMR_CAM 0x00000400 /* CAM Address Matching */
-#define UPSMR_BRO 0x00000200 /* Broadcast Address */
-#define UPSMR_RES1 0x00002000 /* Reserved feild - must be 1 */
-#define UPSMR_SGMM 0x00000020 /* SGMII mode */
-
-#define UPSMR_INIT_VALUE (UPSMR_HSE | UPSMR_RES1)
-
-/* UEC MACCFG1 (MAC Configuration 1 Register)
- */
-#define MACCFG1_FLOW_RX 0x00000020 /* Flow Control Rx */
-#define MACCFG1_FLOW_TX 0x00000010 /* Flow Control Tx */
-#define MACCFG1_ENABLE_SYNCHED_RX 0x00000008 /* Enable Rx Sync */
-#define MACCFG1_ENABLE_RX 0x00000004 /* Enable Rx */
-#define MACCFG1_ENABLE_SYNCHED_TX 0x00000002 /* Enable Tx Sync */
-#define MACCFG1_ENABLE_TX 0x00000001 /* Enable Tx */
-
-#define MACCFG1_INIT_VALUE (0)
-
-/* UEC MACCFG2 (MAC Configuration 2 Register)
- */
-#define MACCFG2_PREL 0x00007000
-#define MACCFG2_PREL_SHIFT (31 - 19)
-#define MACCFG2_PREL_MASK 0x0000f000
-#define MACCFG2_SRP 0x00000080
-#define MACCFG2_STP 0x00000040
-#define MACCFG2_RESERVED_1 0x00000020 /* must be set */
-#define MACCFG2_LC 0x00000010 /* Length Check */
-#define MACCFG2_MPE 0x00000008
-#define MACCFG2_FDX 0x00000001 /* Full Duplex */
-#define MACCFG2_FDX_MASK 0x00000001
-#define MACCFG2_PAD_CRC 0x00000004
-#define MACCFG2_CRC_EN 0x00000002
-#define MACCFG2_PAD_AND_CRC_MODE_NONE 0x00000000
-#define MACCFG2_PAD_AND_CRC_MODE_CRC_ONLY 0x00000002
-#define MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC 0x00000004
-#define MACCFG2_INTERFACE_MODE_NIBBLE 0x00000100
-#define MACCFG2_INTERFACE_MODE_BYTE 0x00000200
-#define MACCFG2_INTERFACE_MODE_MASK 0x00000300
-
-#define MACCFG2_INIT_VALUE (MACCFG2_PREL | MACCFG2_RESERVED_1 | \
- MACCFG2_LC | MACCFG2_PAD_CRC | MACCFG2_FDX)
-
-/* UEC Event Register */
-#define UCCE_MPD 0x80000000
-#define UCCE_SCAR 0x40000000
-#define UCCE_GRA 0x20000000
-#define UCCE_CBPR 0x10000000
-#define UCCE_BSY 0x08000000
-#define UCCE_RXC 0x04000000
-#define UCCE_TXC 0x02000000
-#define UCCE_TXE 0x01000000
-#define UCCE_TXB7 0x00800000
-#define UCCE_TXB6 0x00400000
-#define UCCE_TXB5 0x00200000
-#define UCCE_TXB4 0x00100000
-#define UCCE_TXB3 0x00080000
-#define UCCE_TXB2 0x00040000
-#define UCCE_TXB1 0x00020000
-#define UCCE_TXB0 0x00010000
-#define UCCE_RXB7 0x00008000
-#define UCCE_RXB6 0x00004000
-#define UCCE_RXB5 0x00002000
-#define UCCE_RXB4 0x00001000
-#define UCCE_RXB3 0x00000800
-#define UCCE_RXB2 0x00000400
-#define UCCE_RXB1 0x00000200
-#define UCCE_RXB0 0x00000100
-#define UCCE_RXF7 0x00000080
-#define UCCE_RXF6 0x00000040
-#define UCCE_RXF5 0x00000020
-#define UCCE_RXF4 0x00000010
-#define UCCE_RXF3 0x00000008
-#define UCCE_RXF2 0x00000004
-#define UCCE_RXF1 0x00000002
-#define UCCE_RXF0 0x00000001
-
-#define UCCE_TXB (UCCE_TXB7 | UCCE_TXB6 | UCCE_TXB5 | UCCE_TXB4 | \
- UCCE_TXB3 | UCCE_TXB2 | UCCE_TXB1 | UCCE_TXB0)
-#define UCCE_RXB (UCCE_RXB7 | UCCE_RXB6 | UCCE_RXB5 | UCCE_RXB4 | \
- UCCE_RXB3 | UCCE_RXB2 | UCCE_RXB1 | UCCE_RXB0)
-#define UCCE_RXF (UCCE_RXF7 | UCCE_RXF6 | UCCE_RXF5 | UCCE_RXF4 | \
- UCCE_RXF3 | UCCE_RXF2 | UCCE_RXF1 | UCCE_RXF0)
-#define UCCE_OTHER (UCCE_SCAR | UCCE_GRA | UCCE_CBPR | UCCE_BSY | \
- UCCE_RXC | UCCE_TXC | UCCE_TXE)
-
-/* UEC TEMODR Register */
-#define TEMODER_SCHEDULER_ENABLE 0x2000
-#define TEMODER_IP_CHECKSUM_GENERATE 0x0400
-#define TEMODER_PERFORMANCE_OPTIMIZATION_MODE1 0x0200
-#define TEMODER_RMON_STATISTICS 0x0100
-#define TEMODER_NUM_OF_QUEUES_SHIFT (15 - 15)
-
-#define TEMODER_INIT_VALUE 0xc000
-
-/* UEC REMODR Register */
-#define REMODER_RX_RMON_STATISTICS_ENABLE 0x00001000
-#define REMODER_RX_EXTENDED_FEATURES 0x80000000
-#define REMODER_VLAN_OPERATION_TAGGED_SHIFT (31 - 9)
-#define REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT (31 - 10)
-#define REMODER_RX_QOS_MODE_SHIFT (31 - 15)
-#define REMODER_RMON_STATISTICS 0x00001000
-#define REMODER_RX_EXTENDED_FILTERING 0x00000800
-#define REMODER_NUM_OF_QUEUES_SHIFT (31 - 23)
-#define REMODER_DYNAMIC_MAX_FRAME_LENGTH 0x00000008
-#define REMODER_DYNAMIC_MIN_FRAME_LENGTH 0x00000004
-#define REMODER_IP_CHECKSUM_CHECK 0x00000002
-#define REMODER_IP_ADDRESS_ALIGNMENT 0x00000001
-
-#define REMODER_INIT_VALUE 0
-
-/* BMRx - Bus Mode Register */
-#define BMR_GLB 0x20
-#define BMR_BO_BE 0x10
-#define BMR_DTB_SECONDARY_BUS 0x02
-#define BMR_BDB_SECONDARY_BUS 0x01
-
-#define BMR_SHIFT 24
-#define BMR_INIT_VALUE (BMR_GLB | BMR_BO_BE)
-
-/* UEC UCCS (Ethernet Status Register)
- */
-#define UCCS_BPR 0x02
-#define UCCS_PAU 0x02
-#define UCCS_MPD 0x01
-
-/* UEC MIIMCFG (MII Management Configuration Register)
- */
-#define MIIMCFG_RESET_MANAGEMENT 0x80000000
-#define MIIMCFG_NO_PREAMBLE 0x00000010
-#define MIIMCFG_CLOCK_DIVIDE_SHIFT (31 - 31)
-#define MIIMCFG_CLOCK_DIVIDE_MASK 0x0000000f
-#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_4 0x00000001
-#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_6 0x00000002
-#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_8 0x00000003
-#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_10 0x00000004
-#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_14 0x00000005
-#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_20 0x00000006
-#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_28 0x00000007
-
-#define MIIMCFG_MNGMNT_CLC_DIV_INIT_VALUE \
- MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_10
-
-/* UEC MIIMCOM (MII Management Command Register)
- */
-#define MIIMCOM_SCAN_CYCLE 0x00000002 /* Scan cycle */
-#define MIIMCOM_READ_CYCLE 0x00000001 /* Read cycle */
-
-/* UEC MIIMADD (MII Management Address Register)
- */
-#define MIIMADD_PHY_ADDRESS_SHIFT (31 - 23)
-#define MIIMADD_PHY_REGISTER_SHIFT (31 - 31)
-
-/* UEC MIIMCON (MII Management Control Register)
- */
-#define MIIMCON_PHY_CONTROL_SHIFT (31 - 31)
-#define MIIMCON_PHY_STATUS_SHIFT (31 - 31)
-
-/* UEC MIIMIND (MII Management Indicator Register)
- */
-#define MIIMIND_NOT_VALID 0x00000004
-#define MIIMIND_SCAN 0x00000002
-#define MIIMIND_BUSY 0x00000001
-
-/* UEC UTBIPAR (Ten Bit Interface Physical Address Register)
- */
-#define UTBIPAR_PHY_ADDRESS_SHIFT (31 - 31)
-#define UTBIPAR_PHY_ADDRESS_MASK 0x0000001f
-
-/* UEC UESCR (Ethernet Statistics Control Register)
- */
-#define UESCR_AUTOZ 0x8000
-#define UESCR_CLRCNT 0x4000
-#define UESCR_MAXCOV_SHIFT (15 - 7)
-#define UESCR_SCOV_SHIFT (15 - 15)
-
-/****** Tx data struct collection ******/
-/* Tx thread data, each Tx thread has one this struct. */
-struct uec_thread_data_tx {
- u8 res0[136];
-} __packed;
-
-/* Tx thread parameter, each Tx thread has one this struct. */
-struct uec_thread_tx_pram {
- u8 res0[64];
-} __packed;
-
-/* Send queue queue-descriptor, each Tx queue has one this QD */
-struct uec_send_queue_qd {
- u32 bd_ring_base; /* pointer to BD ring base address */
- u8 res0[0x8];
- u32 last_bd_completed_address; /* last entry in BD ring */
- u8 res1[0x30];
-} __packed;
-
-/* Send queue memory region */
-struct uec_send_queue_mem_region {
- struct uec_send_queue_qd sqqd[MAX_TX_QUEUES];
-} __packed;
-
-/* Scheduler struct */
-struct uec_scheduler {
- u16 cpucount0; /* CPU packet counter */
- u16 cpucount1; /* CPU packet counter */
- u16 cecount0; /* QE packet counter */
- u16 cecount1; /* QE packet counter */
- u16 cpucount2; /* CPU packet counter */
- u16 cpucount3; /* CPU packet counter */
- u16 cecount2; /* QE packet counter */
- u16 cecount3; /* QE packet counter */
- u16 cpucount4; /* CPU packet counter */
- u16 cpucount5; /* CPU packet counter */
- u16 cecount4; /* QE packet counter */
- u16 cecount5; /* QE packet counter */
- u16 cpucount6; /* CPU packet counter */
- u16 cpucount7; /* CPU packet counter */
- u16 cecount6; /* QE packet counter */
- u16 cecount7; /* QE packet counter */
- u32 weightstatus[MAX_TX_QUEUES]; /* accumulated weight factor */
- u32 rtsrshadow; /* temporary variable handled by QE */
- u32 time; /* temporary variable handled by QE */
- u32 ttl; /* temporary variable handled by QE */
- u32 mblinterval; /* max burst length interval */
- u16 nortsrbytetime; /* normalized value of byte time in tsr units */
- u8 fracsiz;
- u8 res0[1];
- u8 strictpriorityq; /* Strict Priority Mask register */
- u8 txasap; /* Transmit ASAP register */
- u8 extrabw; /* Extra BandWidth register */
- u8 oldwfqmask; /* temporary variable handled by QE */
- u8 weightfactor[MAX_TX_QUEUES]; /**< weight factor for queues */
- u32 minw; /* temporary variable handled by QE */
- u8 res1[0x70 - 0x64];
-} __packed;
-
-/* Tx firmware counters */
-struct uec_tx_firmware_statistics_pram {
- u32 sicoltx; /* single collision */
- u32 mulcoltx; /* multiple collision */
- u32 latecoltxfr; /* late collision */
- u32 frabortduecol; /* frames aborted due to tx collision */
- u32 frlostinmactxer; /* frames lost due to internal MAC error tx */
- u32 carriersenseertx; /* carrier sense error */
- u32 frtxok; /* frames transmitted OK */
- u32 txfrexcessivedefer;
- u32 txpkts256; /* total packets(including bad) 256~511 B */
- u32 txpkts512; /* total packets(including bad) 512~1023B */
- u32 txpkts1024; /* total packets(including bad) 1024~1518B */
- u32 txpktsjumbo; /* total packets(including bad) >1024 */
-} __packed;
-
-/* Tx global parameter table */
-struct uec_tx_global_pram {
- u16 temoder;
- u8 res0[0x38 - 0x02];
- u32 sqptr;
- u32 schedulerbasepointer;
- u32 txrmonbaseptr;
- u32 tstate;
- u8 iphoffset[MAX_IPH_OFFSET_ENTRY];
- u32 vtagtable[0x8];
- u32 tqptr;
- u8 res2[0x80 - 0x74];
-} __packed;
-
-/****** Rx data struct collection ******/
-/* Rx thread data, each Rx thread has one this struct. */
-struct uec_thread_data_rx {
- u8 res0[40];
-} __packed;
-
-/* Rx thread parameter, each Rx thread has one this struct. */
-struct uec_thread_rx_pram {
- u8 res0[128];
-} __packed;
-
-/* Rx firmware counters */
-struct uec_rx_firmware_statistics_pram {
- u32 frrxfcser; /* frames with crc error */
- u32 fraligner; /* frames with alignment error */
- u32 inrangelenrxer; /* in range length error */
- u32 outrangelenrxer; /* out of range length error */
- u32 frtoolong; /* frame too long */
- u32 runt; /* runt */
- u32 verylongevent; /* very long event */
- u32 symbolerror; /* symbol error */
- u32 dropbsy; /* drop because of BD not ready */
- u8 res0[0x8];
- u32 mismatchdrop; /* drop because of MAC filtering */
- u32 underpkts; /* total frames less than 64 octets */
- u32 pkts256; /* total frames(including bad)256~511 B */
- u32 pkts512; /* total frames(including bad)512~1023 B */
- u32 pkts1024; /* total frames(including bad)1024~1518 B */
- u32 pktsjumbo; /* total frames(including bad) >1024 B */
- u32 frlossinmacer;
- u32 pausefr; /* pause frames */
- u8 res1[0x4];
- u32 removevlan;
- u32 replacevlan;
- u32 insertvlan;
-} __packed;
-
-/* Rx interrupt coalescing entry, each Rx queue has one this entry. */
-struct uec_rx_interrupt_coalescing_entry {
- u32 maxvalue;
- u32 counter;
-} __packed;
-
-struct uec_rx_interrupt_coalescing_table {
- struct uec_rx_interrupt_coalescing_entry entry[MAX_RX_QUEUES];
-} __packed;
-
-/* RxBD queue entry, each Rx queue has one this entry. */
-struct uec_rx_bd_queues_entry {
- u32 bdbaseptr; /* BD base pointer */
- u32 bdptr; /* BD pointer */
- u32 externalbdbaseptr; /* external BD base pointer */
- u32 externalbdptr; /* external BD pointer */
-} __packed;
-
-/* Rx global parameter table */
-struct uec_rx_global_pram {
- u32 remoder; /* ethernet mode reg. */
- u32 rqptr; /* base pointer to the Rx Queues */
- u32 res0[0x1];
- u8 res1[0x20 - 0xc];
- u16 typeorlen;
- u8 res2[0x1];
- u8 rxgstpack; /* ack on GRACEFUL STOP RX command */
- u32 rxrmonbaseptr; /* Rx RMON statistics base */
- u8 res3[0x30 - 0x28];
- u32 intcoalescingptr; /* Interrupt coalescing table pointer */
- u8 res4[0x36 - 0x34];
- u8 rstate;
- u8 res5[0x46 - 0x37];
- u16 mrblr; /* max receive buffer length reg. */
- u32 rbdqptr; /* RxBD parameter table description */
- u16 mflr; /* max frame length reg. */
- u16 minflr; /* min frame length reg. */
- u16 maxd1; /* max dma1 length reg. */
- u16 maxd2; /* max dma2 length reg. */
- u32 ecamptr; /* external CAM address */
- u32 l2qt; /* VLAN priority mapping table. */
- u32 l3qt[0x8]; /* IP priority mapping table. */
- u16 vlantype; /* vlan type */
- u16 vlantci; /* default vlan tci */
- u8 addressfiltering[64];/* address filtering data structure */
- u32 exf_global_param; /* extended filtering global parameters */
- u8 res6[0x100 - 0xc4]; /* Initialize to zero */
-} __packed;
-
-#define GRACEFUL_STOP_ACKNOWLEDGE_RX 0x01
-
-/****** UEC common ******/
-/* UCC statistics - hardware counters */
-struct uec_hardware_statistics {
- u32 tx64;
- u32 tx127;
- u32 tx255;
- u32 rx64;
- u32 rx127;
- u32 rx255;
- u32 txok;
- u16 txcf;
- u32 tmca;
- u32 tbca;
- u32 rxfok;
- u32 rxbok;
- u32 rbyt;
- u32 rmca;
- u32 rbca;
-} __packed;
-
-/* InitEnet command parameter */
-struct uec_init_cmd_pram {
- u8 resinit0;
- u8 resinit1;
- u8 resinit2;
- u8 resinit3;
- u16 resinit4;
- u8 res1[0x1];
- u8 largestexternallookupkeysize;
- u32 rgftgfrxglobal;
- u32 rxthread[MAX_ENET_INIT_PARAM_ENTRIES_RX]; /* rx threads */
- u8 res2[0x38 - 0x30];
- u32 txglobal; /* tx global */
- u32 txthread[MAX_ENET_INIT_PARAM_ENTRIES_TX]; /* tx threads */
- u8 res3[0x1];
-} __packed;
-
-#define ENET_INIT_PARAM_RGF_SHIFT (32 - 4)
-#define ENET_INIT_PARAM_TGF_SHIFT (32 - 8)
-
-#define ENET_INIT_PARAM_RISC_MASK 0x0000003f
-#define ENET_INIT_PARAM_PTR_MASK 0x00ffffc0
-#define ENET_INIT_PARAM_SNUM_MASK 0xff000000
-#define ENET_INIT_PARAM_SNUM_SHIFT 24
-
-#define ENET_INIT_PARAM_MAGIC_RES_INIT0 0x06
-#define ENET_INIT_PARAM_MAGIC_RES_INIT1 0x30
-#define ENET_INIT_PARAM_MAGIC_RES_INIT2 0xff
-#define ENET_INIT_PARAM_MAGIC_RES_INIT3 0x00
-#define ENET_INIT_PARAM_MAGIC_RES_INIT4 0x0400
-
-/* structure representing 82xx Address Filtering Enet Address in PRAM */
-struct uec_82xx_enet_addr {
- u8 res1[0x2];
- u16 h; /* address (MSB) */
- u16 m; /* address */
- u16 l; /* address (LSB) */
-} __packed;
-
-/* structure representing 82xx Address Filtering PRAM */
-struct uec_82xx_add_filtering_pram {
- u32 iaddr_h; /* individual address filter, high */
- u32 iaddr_l; /* individual address filter, low */
- u32 gaddr_h; /* group address filter, high */
- u32 gaddr_l; /* group address filter, low */
- struct uec_82xx_enet_addr taddr;
- struct uec_82xx_enet_addr paddr[4];
- u8 res0[0x40 - 0x38];
-} __packed;
-
-/* Buffer Descriptor */
-struct buffer_descriptor {
- u16 status;
- u16 len;
- u32 data;
-} __packed;
-
-#define SIZEOFBD sizeof(struct buffer_descriptor)
-
-/* Common BD flags */
-#define BD_WRAP 0x2000
-#define BD_INT 0x1000
-#define BD_LAST 0x0800
-#define BD_CLEAN 0x3000
-
-/* TxBD status flags */
-#define TX_BD_READY 0x8000
-#define TX_BD_PADCRC 0x4000
-#define TX_BD_WRAP BD_WRAP
-#define TX_BD_INT BD_INT
-#define TX_BD_LAST BD_LAST
-#define TX_BD_TXCRC 0x0400
-#define TX_BD_DEF 0x0200
-#define TX_BD_PP 0x0100
-#define TX_BD_LC 0x0080
-#define TX_BD_RL 0x0040
-#define TX_BD_RC 0x003C
-#define TX_BD_UNDERRUN 0x0002
-#define TX_BD_TRUNC 0x0001
-
-#define TX_BD_ERROR (TX_BD_UNDERRUN | TX_BD_TRUNC)
-
-/* RxBD status flags */
-#define RX_BD_EMPTY 0x8000
-#define RX_BD_OWNER 0x4000
-#define RX_BD_WRAP BD_WRAP
-#define RX_BD_INT BD_INT
-#define RX_BD_LAST BD_LAST
-#define RX_BD_FIRST 0x0400
-#define RX_BD_CMR 0x0200
-#define RX_BD_MISS 0x0100
-#define RX_BD_BCAST 0x0080
-#define RX_BD_MCAST 0x0040
-#define RX_BD_LG 0x0020
-#define RX_BD_NO 0x0010
-#define RX_BD_SHORT 0x0008
-#define RX_BD_CRCERR 0x0004
-#define RX_BD_OVERRUN 0x0002
-#define RX_BD_IPCH 0x0001
-
-#define RX_BD_ERROR (RX_BD_LG | RX_BD_NO | RX_BD_SHORT | \
- RX_BD_CRCERR | RX_BD_OVERRUN)
-
-/* BD access macros */
-#define BD_STATUS(_bd) (in_be16(&((_bd)->status)))
-#define BD_STATUS_SET(_bd, _v) (out_be16(&((_bd)->status), _v))
-#define BD_LENGTH(_bd) (in_be16(&((_bd)->len)))
-#define BD_LENGTH_SET(_bd, _v) (out_be16(&((_bd)->len), _v))
-#define BD_DATA_CLEAR(_bd) (out_be32(&((_bd)->data), 0))
-#define BD_DATA(_bd) ((u8 *)(((_bd)->data)))
-#define BD_DATA_SET(_bd, _data) (out_be32(&((_bd)->data), (u32)_data))
-#define BD_ADVANCE(_bd, _status, _base) \
- (((_status) & BD_WRAP) ? (_bd) = \
- ((struct buffer_descriptor *)(_base)) : ++(_bd))
-
-/* Rx Prefetched BDs */
-struct uec_rx_pref_bds {
- struct buffer_descriptor bd[MAX_PREFETCHED_BDS]; /* prefetched bd */
-} __packed;
-
-/* Alignments */
-#define UEC_RX_GLOBAL_PRAM_ALIGNMENT 64
-#define UEC_TX_GLOBAL_PRAM_ALIGNMENT 64
-#define UEC_THREAD_RX_PRAM_ALIGNMENT 128
-#define UEC_THREAD_TX_PRAM_ALIGNMENT 64
-#define UEC_THREAD_DATA_ALIGNMENT 256
-#define UEC_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT 32
-#define UEC_SCHEDULER_ALIGNMENT 4
-#define UEC_TX_STATISTICS_ALIGNMENT 4
-#define UEC_RX_STATISTICS_ALIGNMENT 4
-#define UEC_RX_INTERRUPT_COALESCING_ALIGNMENT 4
-#define UEC_RX_BD_QUEUES_ALIGNMENT 8
-#define UEC_RX_PREFETCHED_BDS_ALIGNMENT 128
-#define UEC_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT 4
-#define UEC_RX_BD_RING_ALIGNMENT 32
-#define UEC_TX_BD_RING_ALIGNMENT 32
-#define UEC_MRBLR_ALIGNMENT 128
-#define UEC_RX_BD_RING_SIZE_ALIGNMENT 4
-#define UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT 32
-#define UEC_RX_DATA_BUF_ALIGNMENT 64
-
-#define UEC_VLAN_PRIORITY_MAX 8
-#define UEC_IP_PRIORITY_MAX 64
-#define UEC_TX_VTAG_TABLE_ENTRY_MAX 8
-#define UEC_RX_BD_RING_SIZE_MIN 8
-#define UEC_TX_BD_RING_SIZE_MIN 2
-
-/* TBI / MII Set Register */
-enum enet_tbi_mii_reg {
- ENET_TBI_MII_CR = 0x00,
- ENET_TBI_MII_SR = 0x01,
- ENET_TBI_MII_ANA = 0x04,
- ENET_TBI_MII_ANLPBPA = 0x05,
- ENET_TBI_MII_ANEX = 0x06,
- ENET_TBI_MII_ANNPT = 0x07,
- ENET_TBI_MII_ANLPANP = 0x08,
- ENET_TBI_MII_EXST = 0x0F,
- ENET_TBI_MII_JD = 0x10,
- ENET_TBI_MII_TBICON = 0x11
-};
-
-/* TBI MDIO register bit fields*/
-#define TBICON_CLK_SELECT 0x0020
-#define TBIANA_ASYMMETRIC_PAUSE 0x0100
-#define TBIANA_SYMMETRIC_PAUSE 0x0080
-#define TBIANA_HALF_DUPLEX 0x0040
-#define TBIANA_FULL_DUPLEX 0x0020
-#define TBICR_PHY_RESET 0x8000
-#define TBICR_ANEG_ENABLE 0x1000
-#define TBICR_RESTART_ANEG 0x0200
-#define TBICR_FULL_DUPLEX 0x0100
-#define TBICR_SPEED1_SET 0x0040
-
-#define TBIANA_SETTINGS ( \
- TBIANA_ASYMMETRIC_PAUSE \
- | TBIANA_SYMMETRIC_PAUSE \
- | TBIANA_FULL_DUPLEX \
- )
-
-#define TBICR_SETTINGS ( \
- TBICR_PHY_RESET \
- | TBICR_ANEG_ENABLE \
- | TBICR_FULL_DUPLEX \
- | TBICR_SPEED1_SET \
- )
-
-/* UEC number of threads */
-enum uec_num_of_threads {
- UEC_NUM_OF_THREADS_1 = 0x1, /* 1 */
- UEC_NUM_OF_THREADS_2 = 0x2, /* 2 */
- UEC_NUM_OF_THREADS_4 = 0x0, /* 4 */
- UEC_NUM_OF_THREADS_6 = 0x3, /* 6 */
- UEC_NUM_OF_THREADS_8 = 0x4 /* 8 */
-};
-
-/* UEC initialization info struct */
-#define STD_UEC_INFO(num) \
-{ \
- .uf_info = { \
- .ucc_num = CFG_SYS_UEC##num##_UCC_NUM,\
- .rx_clock = CFG_SYS_UEC##num##_RX_CLK, \
- .tx_clock = CFG_SYS_UEC##num##_TX_CLK, \
- .eth_type = CFG_SYS_UEC##num##_ETH_TYPE,\
- }, \
- .num_threads_tx = UEC_NUM_OF_THREADS_1, \
- .num_threads_rx = UEC_NUM_OF_THREADS_1, \
- .risc_tx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, \
- .risc_rx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, \
- .tx_bd_ring_len = 16, \
- .rx_bd_ring_len = 16, \
- .phy_address = CFG_SYS_UEC##num##_PHY_ADDR, \
- .enet_interface_type = CFG_SYS_UEC##num##_INTERFACE_TYPE, \
- .speed = CFG_SYS_UEC##num##_INTERFACE_SPEED, \
-}
-
-struct uec_inf {
- struct ucc_fast_inf uf_info;
- enum uec_num_of_threads num_threads_tx;
- enum uec_num_of_threads num_threads_rx;
- unsigned int risc_tx;
- unsigned int risc_rx;
- u16 rx_bd_ring_len;
- u16 tx_bd_ring_len;
- u8 phy_address;
- phy_interface_t enet_interface_type;
- int speed;
-};
-
-/* UEC driver initialized info */
-#define MAX_RXBUF_LEN 1536
-#define MAX_FRAME_LEN 1518
-#define MIN_FRAME_LEN 64
-#define MAX_DMA1_LEN 1520
-#define MAX_DMA2_LEN 1520
-
-/* UEC driver private struct */
-struct uec_priv {
- struct uec_inf *uec_info;
- struct ucc_fast_priv *uccf;
- struct eth_device *dev;
- uec_t *uec_regs;
- uec_mii_t *uec_mii_regs;
- /* enet init command parameter */
- struct uec_init_cmd_pram *p_init_enet_param;
- u32 init_enet_param_offset;
- /* Rx and Tx parameter */
- struct uec_rx_global_pram *p_rx_glbl_pram;
- u32 rx_glbl_pram_offset;
- struct uec_tx_global_pram *p_tx_glbl_pram;
- u32 tx_glbl_pram_offset;
- struct uec_send_queue_mem_region *p_send_q_mem_reg;
- u32 send_q_mem_reg_offset;
- struct uec_thread_data_tx *p_thread_data_tx;
- u32 thread_dat_tx_offset;
- struct uec_thread_data_rx *p_thread_data_rx;
- u32 thread_dat_rx_offset;
- struct uec_rx_bd_queues_entry *p_rx_bd_qs_tbl;
- u32 rx_bd_qs_tbl_offset;
- /* BDs specific */
- u8 *p_tx_bd_ring;
- u32 tx_bd_ring_offset;
- u8 *p_rx_bd_ring;
- u32 rx_bd_ring_offset;
- u8 *p_rx_buf;
- u32 rx_buf_offset;
- struct buffer_descriptor *tx_bd;
- struct buffer_descriptor *rx_bd;
- /* Status */
- int mac_tx_enabled;
- int mac_rx_enabled;
- int grace_stopped_tx;
- int grace_stopped_rx;
- int the_first_run;
- /* PHY specific */
- struct uec_mii_info *mii_info;
- int oldspeed;
- int oldduplex;
- int oldlink;
-};
-
-int uec_initialize(struct bd_info *bis, struct uec_inf *uec_info);
-int uec_eth_init(struct bd_info *bis, struct uec_inf *uecs, int num);
-int uec_standard_init(struct bd_info *bis);
-#endif /* __UEC_H__ */
diff --git a/drivers/qe/uec_phy.c b/drivers/qe/uec_phy.c
deleted file mode 100644
index fcf06d10328..00000000000
--- a/drivers/qe/uec_phy.c
+++ /dev/null
@@ -1,930 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2005,2010-2011 Freescale Semiconductor, Inc.
- *
- * Author: Shlomi Gridish
- *
- * Description: UCC GETH Driver -- PHY handling
- * Driver for UEC on QE
- * Based on 8260_io/fcc_enet.c
- */
-
-#include <common.h>
-#include <net.h>
-#include <malloc.h>
-#include <linux/delay.h>
-#include <linux/errno.h>
-#include <linux/immap_qe.h>
-#include <asm/io.h>
-#include "uccf.h"
-#include "uec.h"
-#include "uec_phy.h"
-#include "miiphy.h"
-#include <fsl_qe.h>
-#include <phy.h>
-
-#if !defined(CONFIG_DM_ETH)
-
-#define ugphy_printk(format, arg...) \
- printf(format "\n", ## arg)
-
-#define ugphy_dbg(format, arg...) \
- ugphy_printk(format, ## arg)
-#define ugphy_err(format, arg...) \
- ugphy_printk(format, ## arg)
-#define ugphy_info(format, arg...) \
- ugphy_printk(format, ## arg)
-#define ugphy_warn(format, arg...) \
- ugphy_printk(format, ## arg)
-
-#ifdef UEC_VERBOSE_DEBUG
-#define ugphy_vdbg ugphy_dbg
-#else
-#define ugphy_vdbg(ugeth, fmt, args...) do { } while (0)
-#endif /* UEC_VERBOSE_DEBUG */
-
-/*
- * --------------------------------------------------------------------
- * Fixed PHY (PHY-less) support for Ethernet Ports.
- *
- * Copied from arch/powerpc/cpu/ppc4xx/4xx_enet.c
- *--------------------------------------------------------------------
- *
- * Some boards do not have a PHY for each ethernet port. These ports are known
- * as Fixed PHY (or PHY-less) ports. For such ports, set the appropriate
- * CFG_SYS_UECx_PHY_ADDR equal to CONFIG_FIXED_PHY_ADDR (an unused address)
- * When the drver tries to identify the PHYs, CONFIG_FIXED_PHY will be returned
- * and the driver will search CONFIG_SYS_FIXED_PHY_PORTS to find what network
- * speed and duplex should be for the port.
- *
- * Example board header configuration file:
- * #define CONFIG_FIXED_PHY 0xFFFFFFFF
- * #define CONFIG_SYS_FIXED_PHY_ADDR 0x1E (pick an unused phy address)
- *
- * #define CFG_SYS_UEC1_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR
- * #define CFG_SYS_UEC2_PHY_ADDR 0x02
- * #define CFG_SYS_UEC3_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR
- * #define CFG_SYS_UEC4_PHY_ADDR 0x04
- *
- * #define CONFIG_SYS_FIXED_PHY_PORT(name,speed,duplex) \
- * {name, speed, duplex},
- *
- * #define CONFIG_SYS_FIXED_PHY_PORTS \
- * CONFIG_SYS_FIXED_PHY_PORT("UEC0",SPEED_100,DUPLEX_FULL) \
- * CONFIG_SYS_FIXED_PHY_PORT("UEC2",SPEED_100,DUPLEX_HALF)
- */
-
-#ifndef CONFIG_FIXED_PHY
-#define CONFIG_FIXED_PHY 0xFFFFFFFF /* Fixed PHY (PHY-less) */
-#endif
-
-#ifndef CONFIG_SYS_FIXED_PHY_PORTS
-#define CONFIG_SYS_FIXED_PHY_PORTS /* default is an empty array */
-#endif
-
-struct fixed_phy_port {
- char name[16]; /* ethernet port name */
- unsigned int speed; /* specified speed 10,100 or 1000 */
- unsigned int duplex; /* specified duplex FULL or HALF */
-};
-
-static const struct fixed_phy_port fixed_phy_port[] = {
- CONFIG_SYS_FIXED_PHY_PORTS /* defined in board configuration file */
-};
-
-/*
- * -------------------------------------------------------------------
- * BitBang MII support for ethernet ports
- *
- * Based from MPC8560ADS implementation
- *--------------------------------------------------------------------
- *
- * Example board header file to define bitbang ethernet ports:
- *
- * #define CONFIG_SYS_BITBANG_PHY_PORT(name) name,
- * #define CONFIG_SYS_BITBANG_PHY_PORTS CONFIG_SYS_BITBANG_PHY_PORT("UEC0")
- */
-#ifndef CONFIG_SYS_BITBANG_PHY_PORTS
-#define CONFIG_SYS_BITBANG_PHY_PORTS /* default is an empty array */
-#endif
-
-#if defined(CONFIG_BITBANGMII)
-static const char * const bitbang_phy_port[] = {
- CONFIG_SYS_BITBANG_PHY_PORTS /* defined in board configuration file */
-};
-#endif /* CONFIG_BITBANGMII */
-
-static void config_genmii_advert(struct uec_mii_info *mii_info);
-static void genmii_setup_forced(struct uec_mii_info *mii_info);
-static void genmii_restart_aneg(struct uec_mii_info *mii_info);
-static int gbit_config_aneg(struct uec_mii_info *mii_info);
-static int genmii_config_aneg(struct uec_mii_info *mii_info);
-static int genmii_update_link(struct uec_mii_info *mii_info);
-static int genmii_read_status(struct uec_mii_info *mii_info);
-static u16 uec_phy_read(struct uec_mii_info *mii_info, u16 regnum);
-static void uec_phy_write(struct uec_mii_info *mii_info, u16 regnum,
- u16 val);
-
-/*
- * Write value to the PHY for this device to the register at regnum,
- * waiting until the write is done before it returns. All PHY
- * configuration has to be done through the TSEC1 MIIM regs
- */
-void uec_write_phy_reg(struct eth_device *dev, int mii_id, int regnum,
- int value)
-{
- struct uec_priv *ugeth = (struct uec_priv *)dev->priv;
- uec_mii_t *ug_regs;
- enum enet_tbi_mii_reg mii_reg = (enum enet_tbi_mii_reg)regnum;
- u32 tmp_reg;
-
-#if defined(CONFIG_BITBANGMII)
- u32 i = 0;
-
- for (i = 0; i < ARRAY_SIZE(bitbang_phy_port); i++) {
- if (strncmp(dev->name, bitbang_phy_port[i],
- sizeof(dev->name)) == 0) {
- (void)bb_miiphy_write(NULL, mii_id, regnum, value);
- return;
- }
- }
-#endif /* CONFIG_BITBANGMII */
-
- ug_regs = ugeth->uec_mii_regs;
-
- /* Stop the MII management read cycle */
- out_be32 (&ug_regs->miimcom, 0);
- /* Setting up the MII Management Address Register */
- tmp_reg = ((u32)mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg;
- out_be32 (&ug_regs->miimadd, tmp_reg);
-
- /* Setting up the MII Management Control Register with the value */
- out_be32 (&ug_regs->miimcon, (u32)value);
- sync();
-
- /* Wait till MII management write is complete */
- while ((in_be32 (&ug_regs->miimind)) & MIIMIND_BUSY)
- ;
-}
-
-/*
- * Reads from register regnum in the PHY for device dev,
- * returning the value. Clears miimcom first. All PHY
- * configuration has to be done through the TSEC1 MIIM regs
- */
-int uec_read_phy_reg(struct eth_device *dev, int mii_id, int regnum)
-{
- struct uec_priv *ugeth = (struct uec_priv *)dev->priv;
- uec_mii_t *ug_regs;
- enum enet_tbi_mii_reg mii_reg = (enum enet_tbi_mii_reg)regnum;
- u32 tmp_reg;
- u16 value;
-
-#if defined(CONFIG_BITBANGMII)
- u32 i = 0;
-
- for (i = 0; i < ARRAY_SIZE(bitbang_phy_port); i++) {
- if (strncmp(dev->name, bitbang_phy_port[i],
- sizeof(dev->name)) == 0) {
- (void)bb_miiphy_read(NULL, mii_id, regnum, &value);
- return value;
- }
- }
-#endif /* CONFIG_BITBANGMII */
-
- ug_regs = ugeth->uec_mii_regs;
-
- /* Setting up the MII Management Address Register */
- tmp_reg = ((u32)mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg;
- out_be32 (&ug_regs->miimadd, tmp_reg);
-
- /* clear MII management command cycle */
- out_be32 (&ug_regs->miimcom, 0);
- sync();
-
- /* Perform an MII management read cycle */
- out_be32 (&ug_regs->miimcom, MIIMCOM_READ_CYCLE);
-
- /* Wait till MII management write is complete */
- while ((in_be32 (&ug_regs->miimind)) &
- (MIIMIND_NOT_VALID | MIIMIND_BUSY))
- ;
-
- /* Read MII management status */
- value = (u16)in_be32 (&ug_regs->miimstat);
- if (value == 0xffff)
- ugphy_vdbg
- ("read wrong value : mii_id %d,mii_reg %d, base %08x",
- mii_id, mii_reg, (u32)&ug_regs->miimcfg);
-
- return value;
-}
-
-void mii_clear_phy_interrupt(struct uec_mii_info *mii_info)
-{
- if (mii_info->phyinfo->ack_interrupt)
- mii_info->phyinfo->ack_interrupt(mii_info);
-}
-
-void mii_configure_phy_interrupt(struct uec_mii_info *mii_info,
- u32 interrupts)
-{
- mii_info->interrupts = interrupts;
- if (mii_info->phyinfo->config_intr)
- mii_info->phyinfo->config_intr(mii_info);
-}
-
-/* Writes MII_ADVERTISE with the appropriate values, after
- * sanitizing advertise to make sure only supported features
- * are advertised
- */
-static void config_genmii_advert(struct uec_mii_info *mii_info)
-{
- u32 advertise;
- u16 adv;
-
- /* Only allow advertising what this PHY supports */
- mii_info->advertising &= mii_info->phyinfo->features;
- advertise = mii_info->advertising;
-
- /* Setup standard advertisement */
- adv = uec_phy_read(mii_info, MII_ADVERTISE);
- adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
- if (advertise & ADVERTISED_10baseT_Half)
- adv |= ADVERTISE_10HALF;
- if (advertise & ADVERTISED_10baseT_Full)
- adv |= ADVERTISE_10FULL;
- if (advertise & ADVERTISED_100baseT_Half)
- adv |= ADVERTISE_100HALF;
- if (advertise & ADVERTISED_100baseT_Full)
- adv |= ADVERTISE_100FULL;
- uec_phy_write(mii_info, MII_ADVERTISE, adv);
-}
-
-static void genmii_setup_forced(struct uec_mii_info *mii_info)
-{
- u16 ctrl;
- u32 features = mii_info->phyinfo->features;
-
- ctrl = uec_phy_read(mii_info, MII_BMCR);
-
- ctrl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 |
- BMCR_SPEED1000 | BMCR_ANENABLE);
- ctrl |= BMCR_RESET;
-
- switch (mii_info->speed) {
- case SPEED_1000:
- if (features & (SUPPORTED_1000baseT_Half
- | SUPPORTED_1000baseT_Full)) {
- ctrl |= BMCR_SPEED1000;
- break;
- }
- mii_info->speed = SPEED_100;
- case SPEED_100:
- if (features & (SUPPORTED_100baseT_Half
- | SUPPORTED_100baseT_Full)) {
- ctrl |= BMCR_SPEED100;
- break;
- }
- mii_info->speed = SPEED_10;
- case SPEED_10:
- if (features & (SUPPORTED_10baseT_Half
- | SUPPORTED_10baseT_Full))
- break;
- default: /* Unsupported speed! */
- ugphy_err("%s: Bad speed!", mii_info->dev->name);
- break;
- }
-
- uec_phy_write(mii_info, MII_BMCR, ctrl);
-}
-
-/* Enable and Restart Autonegotiation */
-static void genmii_restart_aneg(struct uec_mii_info *mii_info)
-{
- u16 ctl;
-
- ctl = uec_phy_read(mii_info, MII_BMCR);
- ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
- uec_phy_write(mii_info, MII_BMCR, ctl);
-}
-
-static int gbit_config_aneg(struct uec_mii_info *mii_info)
-{
- u16 adv;
- u32 advertise;
-
- if (mii_info->autoneg) {
- /* Configure the ADVERTISE register */
- config_genmii_advert(mii_info);
- advertise = mii_info->advertising;
-
- adv = uec_phy_read(mii_info, MII_CTRL1000);
- adv &= ~(ADVERTISE_1000FULL |
- ADVERTISE_1000HALF);
- if (advertise & SUPPORTED_1000baseT_Half)
- adv |= ADVERTISE_1000HALF;
- if (advertise & SUPPORTED_1000baseT_Full)
- adv |= ADVERTISE_1000FULL;
- uec_phy_write(mii_info, MII_CTRL1000, adv);
-
- /* Start/Restart aneg */
- genmii_restart_aneg(mii_info);
- } else {
- genmii_setup_forced(mii_info);
- }
-
- return 0;
-}
-
-static int marvell_config_aneg(struct uec_mii_info *mii_info)
-{
- /*
- * The Marvell PHY has an errata which requires
- * that certain registers get written in order
- * to restart autonegotiation
- */
- uec_phy_write(mii_info, MII_BMCR, BMCR_RESET);
-
- uec_phy_write(mii_info, 0x1d, 0x1f);
- uec_phy_write(mii_info, 0x1e, 0x200c);
- uec_phy_write(mii_info, 0x1d, 0x5);
- uec_phy_write(mii_info, 0x1e, 0);
- uec_phy_write(mii_info, 0x1e, 0x100);
-
- gbit_config_aneg(mii_info);
-
- return 0;
-}
-
-static int genmii_config_aneg(struct uec_mii_info *mii_info)
-{
- if (mii_info->autoneg) {
- /*
- * Speed up the common case, if link is already up, speed and
- * duplex match, skip auto neg as it already matches
- */
- if (!genmii_read_status(mii_info) && mii_info->link)
- if (mii_info->duplex == DUPLEX_FULL &&
- mii_info->speed == SPEED_100)
- if (mii_info->advertising &
- ADVERTISED_100baseT_Full)
- return 0;
-
- config_genmii_advert(mii_info);
- genmii_restart_aneg(mii_info);
- } else {
- genmii_setup_forced(mii_info);
- }
-
- return 0;
-}
-
-static int genmii_update_link(struct uec_mii_info *mii_info)
-{
- u16 status;
-
- /* Status is read once to clear old link state */
- uec_phy_read(mii_info, MII_BMSR);
-
- /*
- * Wait if the link is up, and autonegotiation is in progress
- * (ie - we're capable and it's not done)
- */
- status = uec_phy_read(mii_info, MII_BMSR);
- if ((status & BMSR_LSTATUS) && (status & BMSR_ANEGCAPABLE) &&
- !(status & BMSR_ANEGCOMPLETE)) {
- int i = 0;
-
- while (!(status & BMSR_ANEGCOMPLETE)) {
- /*
- * Timeout reached ?
- */
- if (i > UGETH_AN_TIMEOUT) {
- mii_info->link = 0;
- return 0;
- }
-
- i++;
- udelay(1000); /* 1 ms */
- status = uec_phy_read(mii_info, MII_BMSR);
- }
- mii_info->link = 1;
- } else {
- if (status & BMSR_LSTATUS)
- mii_info->link = 1;
- else
- mii_info->link = 0;
- }
-
- return 0;
-}
-
-static int genmii_read_status(struct uec_mii_info *mii_info)
-{
- u16 status;
- int err;
-
- /* Update the link, but return if there was an error */
- err = genmii_update_link(mii_info);
- if (err)
- return err;
-
- if (mii_info->autoneg) {
- status = uec_phy_read(mii_info, MII_STAT1000);
-
- if (status & (LPA_1000FULL | LPA_1000HALF)) {
- mii_info->speed = SPEED_1000;
- if (status & LPA_1000FULL)
- mii_info->duplex = DUPLEX_FULL;
- else
- mii_info->duplex = DUPLEX_HALF;
- } else {
- status = uec_phy_read(mii_info, MII_LPA);
-
- if (status & (LPA_10FULL | LPA_100FULL))
- mii_info->duplex = DUPLEX_FULL;
- else
- mii_info->duplex = DUPLEX_HALF;
- if (status & (LPA_100FULL | LPA_100HALF))
- mii_info->speed = SPEED_100;
- else
- mii_info->speed = SPEED_10;
- }
- mii_info->pause = 0;
- }
- /* On non-aneg, we assume what we put in BMCR is the speed,
- * though magic-aneg shouldn't prevent this case from occurring
- */
-
- return 0;
-}
-
-static int bcm_init(struct uec_mii_info *mii_info)
-{
- struct eth_device *edev = mii_info->dev;
- struct uec_priv *uec = edev->priv;
-
- gbit_config_aneg(mii_info);
-
- if (uec->uec_info->enet_interface_type ==
- PHY_INTERFACE_MODE_RGMII_RXID &&
- uec->uec_info->speed == SPEED_1000) {
- u16 val;
- int cnt = 50;
-
- /* Wait for aneg to complete. */
- do
- val = uec_phy_read(mii_info, MII_BMSR);
- while (--cnt && !(val & BMSR_ANEGCOMPLETE));
-
- /* Set RDX clk delay. */
- uec_phy_write(mii_info, 0x18, 0x7 | (7 << 12));
-
- val = uec_phy_read(mii_info, 0x18);
- /* Set RDX-RXC skew. */
- val |= (1 << 8);
- val |= (7 | (7 << 12));
- /* Write bits 14:0. */
- val |= (1 << 15);
- uec_phy_write(mii_info, 0x18, val);
- }
-
- return 0;
-}
-
-static int uec_marvell_init(struct uec_mii_info *mii_info)
-{
- struct eth_device *edev = mii_info->dev;
- struct uec_priv *uec = edev->priv;
- phy_interface_t iface = uec->uec_info->enet_interface_type;
- int speed = uec->uec_info->speed;
-
- if (speed == SPEED_1000 &&
- (iface == PHY_INTERFACE_MODE_RGMII_ID ||
- iface == PHY_INTERFACE_MODE_RGMII_RXID ||
- iface == PHY_INTERFACE_MODE_RGMII_TXID)) {
- int temp;
-
- temp = uec_phy_read(mii_info, MII_M1111_PHY_EXT_CR);
- if (iface == PHY_INTERFACE_MODE_RGMII_ID) {
- temp |= MII_M1111_RX_DELAY | MII_M1111_TX_DELAY;
- } else if (iface == PHY_INTERFACE_MODE_RGMII_RXID) {
- temp &= ~MII_M1111_TX_DELAY;
- temp |= MII_M1111_RX_DELAY;
- } else if (iface == PHY_INTERFACE_MODE_RGMII_TXID) {
- temp &= ~MII_M1111_RX_DELAY;
- temp |= MII_M1111_TX_DELAY;
- }
- uec_phy_write(mii_info, MII_M1111_PHY_EXT_CR, temp);
-
- temp = uec_phy_read(mii_info, MII_M1111_PHY_EXT_SR);
- temp &= ~MII_M1111_HWCFG_MODE_MASK;
- temp |= MII_M1111_HWCFG_MODE_RGMII;
- uec_phy_write(mii_info, MII_M1111_PHY_EXT_SR, temp);
-
- uec_phy_write(mii_info, MII_BMCR, BMCR_RESET);
- }
-
- return 0;
-}
-
-static int marvell_read_status(struct uec_mii_info *mii_info)
-{
- u16 status;
- int err;
-
- /* Update the link, but return if there was an error */
- err = genmii_update_link(mii_info);
- if (err)
- return err;
-
- /*
- * If the link is up, read the speed and duplex
- * If we aren't autonegotiating, assume speeds
- * are as set
- */
- if (mii_info->autoneg && mii_info->link) {
- int speed;
-
- status = uec_phy_read(mii_info, MII_M1011_PHY_SPEC_STATUS);
-
- /* Get the duplexity */
- if (status & MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX)
- mii_info->duplex = DUPLEX_FULL;
- else
- mii_info->duplex = DUPLEX_HALF;
-
- /* Get the speed */
- speed = status & MII_M1011_PHY_SPEC_STATUS_SPD_MASK;
- switch (speed) {
- case MII_M1011_PHY_SPEC_STATUS_1000:
- mii_info->speed = SPEED_1000;
- break;
- case MII_M1011_PHY_SPEC_STATUS_100:
- mii_info->speed = SPEED_100;
- break;
- default:
- mii_info->speed = SPEED_10;
- break;
- }
- mii_info->pause = 0;
- }
-
- return 0;
-}
-
-static int marvell_ack_interrupt(struct uec_mii_info *mii_info)
-{
- /* Clear the interrupts by reading the reg */
- uec_phy_read(mii_info, MII_M1011_IEVENT);
-
- return 0;
-}
-
-static int marvell_config_intr(struct uec_mii_info *mii_info)
-{
- if (mii_info->interrupts == MII_INTERRUPT_ENABLED)
- uec_phy_write(mii_info, MII_M1011_IMASK, MII_M1011_IMASK_INIT);
- else
- uec_phy_write(mii_info, MII_M1011_IMASK,
- MII_M1011_IMASK_CLEAR);
-
- return 0;
-}
-
-static int dm9161_init(struct uec_mii_info *mii_info)
-{
- /* Reset the PHY */
- uec_phy_write(mii_info, MII_BMCR, uec_phy_read(mii_info, MII_BMCR) |
- BMCR_RESET);
- /* PHY and MAC connect */
- uec_phy_write(mii_info, MII_BMCR, uec_phy_read(mii_info, MII_BMCR) &
- ~BMCR_ISOLATE);
-
- uec_phy_write(mii_info, MII_DM9161_SCR, MII_DM9161_SCR_INIT);
-
- config_genmii_advert(mii_info);
- /* Start/restart aneg */
- genmii_config_aneg(mii_info);
-
- return 0;
-}
-
-static int dm9161_config_aneg(struct uec_mii_info *mii_info)
-{
- return 0;
-}
-
-static int dm9161_read_status(struct uec_mii_info *mii_info)
-{
- u16 status;
- int err;
-
- /* Update the link, but return if there was an error */
- err = genmii_update_link(mii_info);
- if (err)
- return err;
- /*
- * If the link is up, read the speed and duplex
- * If we aren't autonegotiating assume speeds are as set
- */
- if (mii_info->autoneg && mii_info->link) {
- status = uec_phy_read(mii_info, MII_DM9161_SCSR);
- if (status & (MII_DM9161_SCSR_100F | MII_DM9161_SCSR_100H))
- mii_info->speed = SPEED_100;
- else
- mii_info->speed = SPEED_10;
-
- if (status & (MII_DM9161_SCSR_100F | MII_DM9161_SCSR_10F))
- mii_info->duplex = DUPLEX_FULL;
- else
- mii_info->duplex = DUPLEX_HALF;
- }
-
- return 0;
-}
-
-static int dm9161_ack_interrupt(struct uec_mii_info *mii_info)
-{
- /* Clear the interrupt by reading the reg */
- uec_phy_read(mii_info, MII_DM9161_INTR);
-
- return 0;
-}
-
-static int dm9161_config_intr(struct uec_mii_info *mii_info)
-{
- if (mii_info->interrupts == MII_INTERRUPT_ENABLED)
- uec_phy_write(mii_info, MII_DM9161_INTR, MII_DM9161_INTR_INIT);
- else
- uec_phy_write(mii_info, MII_DM9161_INTR, MII_DM9161_INTR_STOP);
-
- return 0;
-}
-
-static void dm9161_close(struct uec_mii_info *mii_info)
-{
-}
-
-static int fixed_phy_aneg(struct uec_mii_info *mii_info)
-{
- mii_info->autoneg = 0; /* Turn off auto negotiation for fixed phy */
- return 0;
-}
-
-static int fixed_phy_read_status(struct uec_mii_info *mii_info)
-{
- int i = 0;
-
- for (i = 0; i < ARRAY_SIZE(fixed_phy_port); i++) {
- if (strncmp(mii_info->dev->name, fixed_phy_port[i].name,
- strlen(mii_info->dev->name)) == 0) {
- mii_info->speed = fixed_phy_port[i].speed;
- mii_info->duplex = fixed_phy_port[i].duplex;
- mii_info->link = 1; /* Link is always UP */
- mii_info->pause = 0;
- break;
- }
- }
- return 0;
-}
-
-static int smsc_config_aneg(struct uec_mii_info *mii_info)
-{
- return 0;
-}
-
-static int smsc_read_status(struct uec_mii_info *mii_info)
-{
- u16 status;
- int err;
-
- /* Update the link, but return if there was an error */
- err = genmii_update_link(mii_info);
- if (err)
- return err;
-
- /*
- * If the link is up, read the speed and duplex
- * If we aren't autonegotiating, assume speeds
- * are as set
- */
- if (mii_info->autoneg && mii_info->link) {
- int val;
-
- status = uec_phy_read(mii_info, 0x1f);
- val = (status & 0x1c) >> 2;
-
- switch (val) {
- case 1:
- mii_info->duplex = DUPLEX_HALF;
- mii_info->speed = SPEED_10;
- break;
- case 5:
- mii_info->duplex = DUPLEX_FULL;
- mii_info->speed = SPEED_10;
- break;
- case 2:
- mii_info->duplex = DUPLEX_HALF;
- mii_info->speed = SPEED_100;
- break;
- case 6:
- mii_info->duplex = DUPLEX_FULL;
- mii_info->speed = SPEED_100;
- break;
- }
- mii_info->pause = 0;
- }
-
- return 0;
-}
-
-static struct phy_info phy_info_dm9161 = {
- .phy_id = 0x0181b880,
- .phy_id_mask = 0x0ffffff0,
- .name = "Davicom DM9161E",
- .init = dm9161_init,
- .config_aneg = dm9161_config_aneg,
- .read_status = dm9161_read_status,
- .close = dm9161_close,
-};
-
-static struct phy_info phy_info_dm9161a = {
- .phy_id = 0x0181b8a0,
- .phy_id_mask = 0x0ffffff0,
- .name = "Davicom DM9161A",
- .features = MII_BASIC_FEATURES,
- .init = dm9161_init,
- .config_aneg = dm9161_config_aneg,
- .read_status = dm9161_read_status,
- .ack_interrupt = dm9161_ack_interrupt,
- .config_intr = dm9161_config_intr,
- .close = dm9161_close,
-};
-
-static struct phy_info phy_info_marvell = {
- .phy_id = 0x01410c00,
- .phy_id_mask = 0xffffff00,
- .name = "Marvell 88E11x1",
- .features = MII_GBIT_FEATURES,
- .init = &uec_marvell_init,
- .config_aneg = &marvell_config_aneg,
- .read_status = &marvell_read_status,
- .ack_interrupt = &marvell_ack_interrupt,
- .config_intr = &marvell_config_intr,
-};
-
-static struct phy_info phy_info_bcm5481 = {
- .phy_id = 0x0143bca0,
- .phy_id_mask = 0xffffff0,
- .name = "Broadcom 5481",
- .features = MII_GBIT_FEATURES,
- .read_status = genmii_read_status,
- .init = bcm_init,
-};
-
-static struct phy_info phy_info_fixedphy = {
- .phy_id = CONFIG_FIXED_PHY,
- .phy_id_mask = CONFIG_FIXED_PHY,
- .name = "Fixed PHY",
- .config_aneg = fixed_phy_aneg,
- .read_status = fixed_phy_read_status,
-};
-
-static struct phy_info phy_info_smsclan8700 = {
- .phy_id = 0x0007c0c0,
- .phy_id_mask = 0xfffffff0,
- .name = "SMSC LAN8700",
- .features = MII_BASIC_FEATURES,
- .config_aneg = smsc_config_aneg,
- .read_status = smsc_read_status,
-};
-
-static struct phy_info phy_info_genmii = {
- .phy_id = 0x00000000,
- .phy_id_mask = 0x00000000,
- .name = "Generic MII",
- .features = MII_BASIC_FEATURES,
- .config_aneg = genmii_config_aneg,
- .read_status = genmii_read_status,
-};
-
-static struct phy_info *phy_info[] = {
- &phy_info_dm9161,
- &phy_info_dm9161a,
- &phy_info_marvell,
- &phy_info_bcm5481,
- &phy_info_smsclan8700,
- &phy_info_fixedphy,
- &phy_info_genmii,
- NULL
-};
-
-static u16 uec_phy_read(struct uec_mii_info *mii_info, u16 regnum)
-{
- return mii_info->mdio_read(mii_info->dev, mii_info->mii_id, regnum);
-}
-
-static void uec_phy_write(struct uec_mii_info *mii_info, u16 regnum, u16 val)
-{
- mii_info->mdio_write(mii_info->dev, mii_info->mii_id, regnum, val);
-}
-
-/* Use the PHY ID registers to determine what type of PHY is attached
- * to device dev. return a struct phy_info structure describing that PHY
- */
-struct phy_info *uec_get_phy_info(struct uec_mii_info *mii_info)
-{
- u16 phy_reg;
- u32 phy_ID;
- int i;
- struct phy_info *info = NULL;
-
- /* Grab the bits from PHYIR1, and put them in the upper half */
- phy_reg = uec_phy_read(mii_info, MII_PHYSID1);
- phy_ID = (phy_reg & 0xffff) << 16;
-
- /* Grab the bits from PHYIR2, and put them in the lower half */
- phy_reg = uec_phy_read(mii_info, MII_PHYSID2);
- phy_ID |= (phy_reg & 0xffff);
-
- /* loop through all the known PHY types, and find one that */
- /* matches the ID we read from the PHY. */
- for (i = 0; phy_info[i]; i++)
- if (phy_info[i]->phy_id ==
- (phy_ID & phy_info[i]->phy_id_mask)) {
- info = phy_info[i];
- break;
- }
-
- /* This shouldn't happen, as we have generic PHY support */
- if (!info) {
- ugphy_info("UEC: PHY id %x is not supported!", phy_ID);
- return NULL;
- }
- ugphy_info("UEC: PHY is %s (%x)", info->name, phy_ID);
-
- return info;
-}
-
-void marvell_phy_interface_mode(struct eth_device *dev, phy_interface_t type,
- int speed)
-{
- struct uec_priv *uec = (struct uec_priv *)dev->priv;
- struct uec_mii_info *mii_info;
- u16 status;
-
- if (!uec->mii_info) {
- printf("%s: the PHY not initialized\n", __func__);
- return;
- }
- mii_info = uec->mii_info;
-
- if (type == PHY_INTERFACE_MODE_RGMII) {
- if (speed == SPEED_100) {
- uec_phy_write(mii_info, 0x00, 0x9140);
- uec_phy_write(mii_info, 0x1d, 0x001f);
- uec_phy_write(mii_info, 0x1e, 0x200c);
- uec_phy_write(mii_info, 0x1d, 0x0005);
- uec_phy_write(mii_info, 0x1e, 0x0000);
- uec_phy_write(mii_info, 0x1e, 0x0100);
- uec_phy_write(mii_info, 0x09, 0x0e00);
- uec_phy_write(mii_info, 0x04, 0x01e1);
- uec_phy_write(mii_info, 0x00, 0x9140);
- uec_phy_write(mii_info, 0x00, 0x1000);
- mdelay(100);
- uec_phy_write(mii_info, 0x00, 0x2900);
- uec_phy_write(mii_info, 0x14, 0x0cd2);
- uec_phy_write(mii_info, 0x00, 0xa100);
- uec_phy_write(mii_info, 0x09, 0x0000);
- uec_phy_write(mii_info, 0x1b, 0x800b);
- uec_phy_write(mii_info, 0x04, 0x05e1);
- uec_phy_write(mii_info, 0x00, 0xa100);
- uec_phy_write(mii_info, 0x00, 0x2100);
- mdelay(1000);
- } else if (speed == SPEED_10) {
- uec_phy_write(mii_info, 0x14, 0x8e40);
- uec_phy_write(mii_info, 0x1b, 0x800b);
- uec_phy_write(mii_info, 0x14, 0x0c82);
- uec_phy_write(mii_info, 0x00, 0x8100);
- mdelay(1000);
- }
- }
-
- /* handle 88e1111 rev.B2 erratum 5.6 */
- if (mii_info->autoneg) {
- status = uec_phy_read(mii_info, MII_BMCR);
- uec_phy_write(mii_info, MII_BMCR, status | BMCR_ANENABLE);
- }
- /* now the B2 will correctly report autoneg completion status */
-}
-
-void change_phy_interface_mode(struct eth_device *dev,
- phy_interface_t type, int speed)
-{
-#ifdef CONFIG_PHY_MODE_NEED_CHANGE
- marvell_phy_interface_mode(dev, type, speed);
-#endif
-}
-#endif
diff --git a/drivers/qe/uec_phy.h b/drivers/qe/uec_phy.h
deleted file mode 100644
index 7fd0e2c5440..00000000000
--- a/drivers/qe/uec_phy.h
+++ /dev/null
@@ -1,214 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2005, 2011 Freescale Semiconductor, Inc.
- *
- * Author: Shlomi Gridish <gridish@freescale.com>
- *
- * Description: UCC ethernet driver -- PHY handling
- * Driver for UEC on QE
- * Based on 8260_io/fcc_enet.c
- */
-#ifndef __UEC_PHY_H__
-#define __UEC_PHY_H__
-
-#include <linux/bitops.h>
-
-#define MII_end ((u32)-2)
-#define MII_read ((u32)-1)
-
-#define MIIMIND_BUSY 0x00000001
-#define MIIMIND_NOTVALID 0x00000004
-
-#define UGETH_AN_TIMEOUT 2000
-
-/* Cicada Extended Control Register 1 */
-#define MII_CIS8201_EXT_CON1 0x17
-#define MII_CIS8201_EXTCON1_INIT 0x0000
-
-/* Cicada Interrupt Mask Register */
-#define MII_CIS8201_IMASK 0x19
-#define MII_CIS8201_IMASK_IEN 0x8000
-#define MII_CIS8201_IMASK_SPEED 0x4000
-#define MII_CIS8201_IMASK_LINK 0x2000
-#define MII_CIS8201_IMASK_DUPLEX 0x1000
-#define MII_CIS8201_IMASK_MASK 0xf000
-
-/* Cicada Interrupt Status Register */
-#define MII_CIS8201_ISTAT 0x1a
-#define MII_CIS8201_ISTAT_STATUS 0x8000
-#define MII_CIS8201_ISTAT_SPEED 0x4000
-#define MII_CIS8201_ISTAT_LINK 0x2000
-#define MII_CIS8201_ISTAT_DUPLEX 0x1000
-
-/* Cicada Auxiliary Control/Status Register */
-#define MII_CIS8201_AUX_CONSTAT 0x1c
-#define MII_CIS8201_AUXCONSTAT_INIT 0x0004
-#define MII_CIS8201_AUXCONSTAT_DUPLEX 0x0020
-#define MII_CIS8201_AUXCONSTAT_SPEED 0x0018
-#define MII_CIS8201_AUXCONSTAT_GBIT 0x0010
-#define MII_CIS8201_AUXCONSTAT_100 0x0008
-
-/* 88E1011 PHY Status Register */
-#define MII_M1011_PHY_SPEC_STATUS 0x11
-#define MII_M1011_PHY_SPEC_STATUS_1000 0x8000
-#define MII_M1011_PHY_SPEC_STATUS_100 0x4000
-#define MII_M1011_PHY_SPEC_STATUS_SPD_MASK 0xc000
-#define MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX 0x2000
-#define MII_M1011_PHY_SPEC_STATUS_RESOLVED 0x0800
-#define MII_M1011_PHY_SPEC_STATUS_LINK 0x0400
-
-#define MII_M1011_IEVENT 0x13
-#define MII_M1011_IEVENT_CLEAR 0x0000
-
-#define MII_M1011_IMASK 0x12
-#define MII_M1011_IMASK_INIT 0x6400
-#define MII_M1011_IMASK_CLEAR 0x0000
-
-/* 88E1111 PHY Register */
-#define MII_M1111_PHY_EXT_CR 0x14
-#define MII_M1111_RX_DELAY 0x80
-#define MII_M1111_TX_DELAY 0x2
-#define MII_M1111_PHY_EXT_SR 0x1b
-#define MII_M1111_HWCFG_MODE_MASK 0xf
-#define MII_M1111_HWCFG_MODE_RGMII 0xb
-
-#define MII_DM9161_SCR 0x10
-#define MII_DM9161_SCR_INIT 0x0610
-#define MII_DM9161_SCR_RMII_INIT 0x0710
-
-/* DM9161 Specified Configuration and Status Register */
-#define MII_DM9161_SCSR 0x11
-#define MII_DM9161_SCSR_100F 0x8000
-#define MII_DM9161_SCSR_100H 0x4000
-#define MII_DM9161_SCSR_10F 0x2000
-#define MII_DM9161_SCSR_10H 0x1000
-
-/* DM9161 Interrupt Register */
-#define MII_DM9161_INTR 0x15
-#define MII_DM9161_INTR_PEND 0x8000
-#define MII_DM9161_INTR_DPLX_MASK 0x0800
-#define MII_DM9161_INTR_SPD_MASK 0x0400
-#define MII_DM9161_INTR_LINK_MASK 0x0200
-#define MII_DM9161_INTR_MASK 0x0100
-#define MII_DM9161_INTR_DPLX_CHANGE 0x0010
-#define MII_DM9161_INTR_SPD_CHANGE 0x0008
-#define MII_DM9161_INTR_LINK_CHANGE 0x0004
-#define MII_DM9161_INTR_INIT 0x0000
-#define MII_DM9161_INTR_STOP \
- (MII_DM9161_INTR_DPLX_MASK | MII_DM9161_INTR_SPD_MASK | \
- MII_DM9161_INTR_LINK_MASK | MII_DM9161_INTR_MASK)
-
-/* DM9161 10BT Configuration/Status */
-#define MII_DM9161_10BTCSR 0x12
-#define MII_DM9161_10BTCSR_INIT 0x7800
-
-#define MII_BASIC_FEATURES (SUPPORTED_10baseT_Half | \
- SUPPORTED_10baseT_Full | \
- SUPPORTED_100baseT_Half | \
- SUPPORTED_100baseT_Full | \
- SUPPORTED_Autoneg | \
- SUPPORTED_TP | \
- SUPPORTED_MII)
-
-#define MII_GBIT_FEATURES (MII_BASIC_FEATURES | \
- SUPPORTED_1000baseT_Half | \
- SUPPORTED_1000baseT_Full)
-
-#define MII_READ_COMMAND 0x00000001
-
-#define MII_INTERRUPT_DISABLED 0x0
-#define MII_INTERRUPT_ENABLED 0x1
-
-#define SPEED_10 10
-#define SPEED_100 100
-#define SPEED_1000 1000
-
-/* Duplex, half or full. */
-#define DUPLEX_HALF 0x00
-#define DUPLEX_FULL 0x01
-
-/* Taken from mii_if_info and sungem_phy.h */
-struct uec_mii_info {
- /* Information about the PHY type */
- /* And management functions */
- struct phy_info *phyinfo;
-
- struct eth_device *dev;
-
- /* forced speed & duplex (no autoneg)
- * partner speed & duplex & pause (autoneg)
- */
- int speed;
- int duplex;
- int pause;
-
- /* The most recently read link state */
- int link;
-
- /* Enabled Interrupts */
- u32 interrupts;
-
- u32 advertising;
- int autoneg;
- int mii_id;
-
- /* private data pointer */
- /* For use by PHYs to maintain extra state */
- void *priv;
-
- /* Provided by ethernet driver */
- int (*mdio_read)(struct eth_device *dev, int mii_id, int reg);
- void (*mdio_write)(struct eth_device *dev, int mii_id, int reg,
- int val);
-};
-
-/* struct phy_info: a structure which defines attributes for a PHY
- *
- * id will contain a number which represents the PHY. During
- * startup, the driver will poll the PHY to find out what its
- * UID--as defined by registers 2 and 3--is. The 32-bit result
- * gotten from the PHY will be ANDed with phy_id_mask to
- * discard any bits which may change based on revision numbers
- * unimportant to functionality
- *
- * There are 6 commands which take a ugeth_mii_info structure.
- * Each PHY must declare config_aneg, and read_status.
- */
-struct phy_info {
- u32 phy_id;
- char *name;
- unsigned int phy_id_mask;
- u32 features;
-
- /* Called to initialize the PHY */
- int (*init)(struct uec_mii_info *mii_info);
-
- /* Called to suspend the PHY for power */
- int (*suspend)(struct uec_mii_info *mii_info);
-
- /* Reconfigures autonegotiation (or disables it) */
- int (*config_aneg)(struct uec_mii_info *mii_info);
-
- /* Determines the negotiated speed and duplex */
- int (*read_status)(struct uec_mii_info *mii_info);
-
- /* Clears any pending interrupts */
- int (*ack_interrupt)(struct uec_mii_info *mii_info);
-
- /* Enables or disables interrupts */
- int (*config_intr)(struct uec_mii_info *mii_info);
-
- /* Clears up any memory if needed */
- void (*close)(struct uec_mii_info *mii_info);
-};
-
-struct phy_info *uec_get_phy_info(struct uec_mii_info *mii_info);
-void uec_write_phy_reg(struct eth_device *dev, int mii_id, int regnum,
- int value);
-int uec_read_phy_reg(struct eth_device *dev, int mii_id, int regnum);
-void mii_clear_phy_interrupt(struct uec_mii_info *mii_info);
-void mii_configure_phy_interrupt(struct uec_mii_info *mii_info,
- u32 interrupts);
-void change_phy_interface_mode(struct eth_device *dev,
- phy_interface_t type, int speed);
-#endif /* __UEC_PHY_H__ */
diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig
index 86857c06272..e085119963b 100644
--- a/drivers/ram/Kconfig
+++ b/drivers/ram/Kconfig
@@ -65,6 +65,7 @@ choice
default K3_J721E_DDRSS if SOC_K3_J721E || SOC_K3_J721S2
default K3_AM64_DDRSS if SOC_K3_AM642
default K3_AM64_DDRSS if SOC_K3_AM625
+ default K3_AM62A_DDRSS if SOC_K3_AM62A7
config K3_J721E_DDRSS
bool "Enable J721E DDRSS support"
@@ -86,6 +87,16 @@ config K3_AM64_DDRSS
Enabling this config adds support for the DDR memory controller
on AM642 family of SoCs.
+config K3_AM62A_DDRSS
+ bool "Enable AM62A DDRSS support"
+ help
+ The AM62A DDR subsystem comprises of a DDR controller, DDR PHY and
+ wrapper logic to integrate these blocks into once device. The DDR
+ subsystem is used to provide an interface to external SDRAM devices
+ which can be utilized for storing programs or any other data.
+ Enabling this option adds support for the DDR memory controller for
+ the AM62A family of SoCs.
+
endchoice
config IMXRT_SDRAM
diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_16bit_obj_if.h b/drivers/ram/k3-ddrss/16bit/lpddr4_16bit_obj_if.h
deleted file mode 100644
index 6c57dd9d00c..00000000000
--- a/drivers/ram/k3-ddrss/16bit/lpddr4_16bit_obj_if.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Cadence DDR Driver
- *
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-#ifndef LPDDR4_16BIT_OBJ_IF_H
-#define LPDDR4_16BIT_OBJ_IF_H
-
-#include "lpddr4_16bit_if.h"
-
-#endif /* LPDDR4_16BIT_OBJ_IF_H */
diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_16bit_structs_if.h b/drivers/ram/k3-ddrss/16bit/lpddr4_16bit_structs_if.h
deleted file mode 100644
index 52973484ecd..00000000000
--- a/drivers/ram/k3-ddrss/16bit/lpddr4_16bit_structs_if.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Cadence DDR Driver
- *
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-#ifndef LPDDR4_16BIT_STRUCTS_IF_H
-#define LPDDR4_16BIT_STRUCTS_IF_H
-
-#include <linux/types.h>
-#include "lpddr4_16bit_if.h"
-
-#endif /* LPDDR4_16BIT_STRUCTS_IF_H */
diff --git a/drivers/ram/k3-ddrss/32bit/lpddr4_32bit_obj_if.h b/drivers/ram/k3-ddrss/32bit/lpddr4_32bit_obj_if.h
deleted file mode 100644
index 7fee54f00d5..00000000000
--- a/drivers/ram/k3-ddrss/32bit/lpddr4_32bit_obj_if.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Cadence DDR Driver
- *
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-#ifndef LPDDR4_32BIT_OBJ_IF_H
-#define LPDDR4_32BIT_OBJ_IF_H
-
-#include "lpddr4_32bit_if.h"
-
-#endif /* LPDDR4_32BIT_OBJ_IF_H */
diff --git a/drivers/ram/k3-ddrss/32bit/lpddr4_32bit_structs_if.h b/drivers/ram/k3-ddrss/32bit/lpddr4_32bit_structs_if.h
deleted file mode 100644
index 69b2a47ab3f..00000000000
--- a/drivers/ram/k3-ddrss/32bit/lpddr4_32bit_structs_if.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Cadence DDR Driver
- *
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-#ifndef LPDDR4_32BIT_STRUCTS_IF_H
-#define LPDDR4_32BIT_STRUCTS_IF_H
-
-#include <linux/types.h>
-#include "lpddr4_32bit_if.h"
-
-#endif /* LPDDR4_32BIT_STRUCTS_IF_H */
diff --git a/drivers/ram/k3-ddrss/Makefile b/drivers/ram/k3-ddrss/Makefile
index 8be00118f50..ba5d9a2f4d3 100644
--- a/drivers/ram/k3-ddrss/Makefile
+++ b/drivers/ram/k3-ddrss/Makefile
@@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-# Copyright (C) 2019-2021 Texas Instruments Incorporated - http://www.ti.com/
+# Copyright (C) 2019-2022 Texas Instruments Incorporated - http://www.ti.com/
#
obj-$(CONFIG_K3_DDRSS) += k3-ddrss.o
@@ -8,10 +8,14 @@ obj-$(CONFIG_K3_DDRSS) += lpddr4_obj_if.o
obj-$(CONFIG_K3_DDRSS) += lpddr4.o
ccflags-$(CONFIG_K3_DDRSS) += -Idrivers/ram/k3-ddrss/
-obj-$(CONFIG_K3_AM64_DDRSS) += lpddr4_16bit.o
-obj-$(CONFIG_K3_AM64_DDRSS) += lpddr4_16bit_ctl_regs_rw_masks.o
-ccflags-$(CONFIG_K3_AM64_DDRSS) += -Idrivers/ram/k3-ddrss/16bit/
+obj-$(CONFIG_K3_AM62A_DDRSS) += lpddr4_am6x.o
+obj-$(CONFIG_K3_AM62A_DDRSS) += lpddr4_am62a_ctl_regs_rw_masks.o
+ccflags-$(CONFIG_K3_AM62A_DDRSS) += -Idrivers/ram/k3-ddrss/am62a/
-obj-$(CONFIG_K3_J721E_DDRSS) += lpddr4_32bit.o
-obj-$(CONFIG_K3_J721E_DDRSS) += lpddr4_32bit_ctl_regs_rw_masks.o
-ccflags-$(CONFIG_K3_J721E_DDRSS) += -Idrivers/ram/k3-ddrss/32bit/
+obj-$(CONFIG_K3_AM64_DDRSS) += lpddr4_am6x.o
+obj-$(CONFIG_K3_AM64_DDRSS) += lpddr4_am64_ctl_regs_rw_masks.o
+ccflags-$(CONFIG_K3_AM64_DDRSS) += -Idrivers/ram/k3-ddrss/am64/
+
+obj-$(CONFIG_K3_J721E_DDRSS) += lpddr4_j721e.o
+obj-$(CONFIG_K3_J721E_DDRSS) += lpddr4_j721e_ctl_regs_rw_masks.o
+ccflags-$(CONFIG_K3_J721E_DDRSS) += -Idrivers/ram/k3-ddrss/j721e/
diff --git a/drivers/ram/k3-ddrss/am62a/lpddr4_address_slice_0_macros.h b/drivers/ram/k3-ddrss/am62a/lpddr4_address_slice_0_macros.h
new file mode 100644
index 00000000000..1cd40c8332c
--- /dev/null
+++ b/drivers/ram/k3-ddrss/am62a/lpddr4_address_slice_0_macros.h
@@ -0,0 +1,778 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef REG_LPDDR4_ADDRESS_SLICE_0_MACROS_H_
+#define REG_LPDDR4_ADDRESS_SLICE_0_MACROS_H_
+
+#define LPDDR4__DENALI_PHY_1024_READ_MASK 0x000107FFU
+#define LPDDR4__DENALI_PHY_1024_WRITE_MASK 0x000107FFU
+#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0_WIDTH 11U
+#define LPDDR4__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0__REG DENALI_PHY_1024
+#define LPDDR4__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_0_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_0_WOSET 0U
+#define LPDDR4__PHY_ADR_CLK_BYPASS_OVERRIDE_0__REG DENALI_PHY_1024
+#define LPDDR4__PHY_ADR_CLK_BYPASS_OVERRIDE_0__FLD LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_0
+
+#define LPDDR4__DENALI_PHY_1024__SC_PHY_ADR_MANUAL_CLEAR_0_MASK 0x07000000U
+#define LPDDR4__DENALI_PHY_1024__SC_PHY_ADR_MANUAL_CLEAR_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1024__SC_PHY_ADR_MANUAL_CLEAR_0_WIDTH 3U
+#define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_0__REG DENALI_PHY_1024
+#define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_0__FLD LPDDR4__DENALI_PHY_1024__SC_PHY_ADR_MANUAL_CLEAR_0
+
+#define LPDDR4__DENALI_PHY_1025_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1025_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_0_WIDTH 32U
+#define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_0__REG DENALI_PHY_1025
+#define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_0__FLD LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_0
+
+#define LPDDR4__DENALI_PHY_1026_READ_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1026_WRITE_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1026__PHY_ADR_LPBK_ERROR_COUNT_OBS_0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1026__PHY_ADR_LPBK_ERROR_COUNT_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1026__PHY_ADR_LPBK_ERROR_COUNT_OBS_0_WIDTH 16U
+#define LPDDR4__PHY_ADR_LPBK_ERROR_COUNT_OBS_0__REG DENALI_PHY_1026
+#define LPDDR4__PHY_ADR_LPBK_ERROR_COUNT_OBS_0__FLD LPDDR4__DENALI_PHY_1026__PHY_ADR_LPBK_ERROR_COUNT_OBS_0
+
+#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MEAS_DLY_STEP_VALUE_0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MEAS_DLY_STEP_VALUE_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MEAS_DLY_STEP_VALUE_0_WIDTH 8U
+#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_VALUE_0__REG DENALI_PHY_1026
+#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_VALUE_0__FLD LPDDR4__DENALI_PHY_1026__PHY_ADR_MEAS_DLY_STEP_VALUE_0
+
+#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0_MASK 0x0F000000U
+#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0_WIDTH 4U
+#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0__REG DENALI_PHY_1026
+#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_1026__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0
+
+#define LPDDR4__DENALI_PHY_1027_READ_MASK 0xFF7F07FFU
+#define LPDDR4__DENALI_PHY_1027_WRITE_MASK 0xFF7F07FFU
+#define LPDDR4__DENALI_PHY_1027__PHY_ADR_MASTER_DLY_LOCK_OBS_0_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1027__PHY_ADR_MASTER_DLY_LOCK_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1027__PHY_ADR_MASTER_DLY_LOCK_OBS_0_WIDTH 11U
+#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_0__REG DENALI_PHY_1027
+#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_0__FLD LPDDR4__DENALI_PHY_1027__PHY_ADR_MASTER_DLY_LOCK_OBS_0
+
+#define LPDDR4__DENALI_PHY_1027__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0_MASK 0x007F0000U
+#define LPDDR4__DENALI_PHY_1027__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1027__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0_WIDTH 7U
+#define LPDDR4__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_1027
+#define LPDDR4__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_1027__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0
+
+#define LPDDR4__DENALI_PHY_1027__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_1027__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1027__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0_WIDTH 8U
+#define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_1027
+#define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_1027__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0
+
+#define LPDDR4__DENALI_PHY_1028_READ_MASK 0x01000707U
+#define LPDDR4__DENALI_PHY_1028_WRITE_MASK 0x01000707U
+#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0_MASK 0x00000007U
+#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0_WIDTH 3U
+#define LPDDR4__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0__REG DENALI_PHY_1028
+#define LPDDR4__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0__FLD LPDDR4__DENALI_PHY_1028__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0
+
+#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0_MASK 0x00000700U
+#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0_WIDTH 3U
+#define LPDDR4__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0__REG DENALI_PHY_1028
+#define LPDDR4__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_1028__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0
+
+#define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_0_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_0_WOSET 0U
+#define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_0__REG DENALI_PHY_1028
+#define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_0__FLD LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_0
+
+#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_WOSET 0U
+#define LPDDR4__PHY_ADR_TSEL_ENABLE_0__REG DENALI_PHY_1028
+#define LPDDR4__PHY_ADR_TSEL_ENABLE_0__FLD LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0
+
+#define LPDDR4__DENALI_PHY_1029_READ_MASK 0x011F7F7FU
+#define LPDDR4__DENALI_PHY_1029_WRITE_MASK 0x011F7F7FU
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_0_MASK 0x0000007FU
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_0_WIDTH 7U
+#define LPDDR4__PHY_ADR_LPBK_CONTROL_0__REG DENALI_PHY_1029
+#define LPDDR4__PHY_ADR_LPBK_CONTROL_0__FLD LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_0
+
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_START_0_MASK 0x00007F00U
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_START_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_START_0_WIDTH 7U
+#define LPDDR4__PHY_ADR_PRBS_PATTERN_START_0__REG DENALI_PHY_1029
+#define LPDDR4__PHY_ADR_PRBS_PATTERN_START_0__FLD LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_START_0
+
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_MASK_0_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_MASK_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_MASK_0_WIDTH 5U
+#define LPDDR4__PHY_ADR_PRBS_PATTERN_MASK_0__REG DENALI_PHY_1029
+#define LPDDR4__PHY_ADR_PRBS_PATTERN_MASK_0__FLD LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_MASK_0
+
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_0_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_0_WOSET 0U
+#define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_0__REG DENALI_PHY_1029
+#define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_0__FLD LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_1030_READ_MASK 0x01070301U
+#define LPDDR4__DENALI_PHY_1030_WRITE_MASK 0x01070301U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_WOSET 0U
+#define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0__REG DENALI_PHY_1030
+#define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_0_MASK 0x00000300U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_0_WIDTH 2U
+#define LPDDR4__PHY_ADR_TYPE_0__REG DENALI_PHY_1030
+#define LPDDR4__PHY_ADR_TYPE_0__FLD LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_0
+
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_WRADDR_SHIFT_OBS_0_MASK 0x00070000U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_WRADDR_SHIFT_OBS_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_WRADDR_SHIFT_OBS_0_WIDTH 3U
+#define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_0__REG DENALI_PHY_1030
+#define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_0__FLD LPDDR4__DENALI_PHY_1030__PHY_ADR_WRADDR_SHIFT_OBS_0
+
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0_WOSET 0U
+#define LPDDR4__PHY_ADR_IE_MODE_0__REG DENALI_PHY_1030
+#define LPDDR4__PHY_ADR_IE_MODE_0__FLD LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0
+
+#define LPDDR4__DENALI_PHY_1031_READ_MASK 0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_1031_WRITE_MASK 0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_0_MASK 0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_0_WIDTH 27U
+#define LPDDR4__PHY_ADR_DDL_MODE_0__REG DENALI_PHY_1031
+#define LPDDR4__PHY_ADR_DDL_MODE_0__FLD LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_0
+
+#define LPDDR4__DENALI_PHY_1032_READ_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_1032_WRITE_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_0_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_0_WIDTH 6U
+#define LPDDR4__PHY_ADR_DDL_MASK_0__REG DENALI_PHY_1032
+#define LPDDR4__PHY_ADR_DDL_MASK_0__FLD LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_0
+
+#define LPDDR4__DENALI_PHY_1033_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1033_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_0_WIDTH 32U
+#define LPDDR4__PHY_ADR_DDL_TEST_OBS_0__REG DENALI_PHY_1033
+#define LPDDR4__PHY_ADR_DDL_TEST_OBS_0__FLD LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_0
+
+#define LPDDR4__DENALI_PHY_1034_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1034_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1034__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1034__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1034__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0_WIDTH 32U
+#define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0__REG DENALI_PHY_1034
+#define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_1034__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0
+
+#define LPDDR4__DENALI_PHY_1035_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1035_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_0_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_0_WIDTH 11U
+#define LPDDR4__PHY_ADR_CALVL_START_0__REG DENALI_PHY_1035
+#define LPDDR4__PHY_ADR_CALVL_START_0__FLD LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_0
+
+#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_COARSE_DLY_0_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_COARSE_DLY_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_COARSE_DLY_0_WIDTH 11U
+#define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_0__REG DENALI_PHY_1035
+#define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_0__FLD LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_COARSE_DLY_0
+
+#define LPDDR4__DENALI_PHY_1036_READ_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1036_WRITE_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_0_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_0_WIDTH 11U
+#define LPDDR4__PHY_ADR_CALVL_QTR_0__REG DENALI_PHY_1036
+#define LPDDR4__PHY_ADR_CALVL_QTR_0__FLD LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_0
+
+#define LPDDR4__DENALI_PHY_1037_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1037_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1037__PHY_ADR_CALVL_SWIZZLE0_0_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1037__PHY_ADR_CALVL_SWIZZLE0_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1037__PHY_ADR_CALVL_SWIZZLE0_0_WIDTH 24U
+#define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_0__REG DENALI_PHY_1037
+#define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_0__FLD LPDDR4__DENALI_PHY_1037__PHY_ADR_CALVL_SWIZZLE0_0
+
+#define LPDDR4__DENALI_PHY_1038_READ_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_1038_WRITE_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_SWIZZLE1_0_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_SWIZZLE1_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_SWIZZLE1_0_WIDTH 24U
+#define LPDDR4__PHY_ADR_CALVL_SWIZZLE1_0__REG DENALI_PHY_1038
+#define LPDDR4__PHY_ADR_CALVL_SWIZZLE1_0__FLD LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_SWIZZLE1_0
+
+#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_RANK_CTRL_0_MASK 0x03000000U
+#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_RANK_CTRL_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_RANK_CTRL_0_WIDTH 2U
+#define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_0__REG DENALI_PHY_1038
+#define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_0__FLD LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_RANK_CTRL_0
+
+#define LPDDR4__DENALI_PHY_1039_READ_MASK 0x01FF0F03U
+#define LPDDR4__DENALI_PHY_1039_WRITE_MASK 0x01FF0F03U
+#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_NUM_PATTERNS_0_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_NUM_PATTERNS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_NUM_PATTERNS_0_WIDTH 2U
+#define LPDDR4__PHY_ADR_CALVL_NUM_PATTERNS_0__REG DENALI_PHY_1039
+#define LPDDR4__PHY_ADR_CALVL_NUM_PATTERNS_0__FLD LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_NUM_PATTERNS_0
+
+#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_RESP_WAIT_CNT_0_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_RESP_WAIT_CNT_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_RESP_WAIT_CNT_0_WIDTH 4U
+#define LPDDR4__PHY_ADR_CALVL_RESP_WAIT_CNT_0__REG DENALI_PHY_1039
+#define LPDDR4__PHY_ADR_CALVL_RESP_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_RESP_WAIT_CNT_0
+
+#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0_WIDTH 9U
+#define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0__REG DENALI_PHY_1039
+#define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0__FLD LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0
+
+#define LPDDR4__DENALI_PHY_1040_READ_MASK 0x07000001U
+#define LPDDR4__DENALI_PHY_1040_WRITE_MASK 0x07000001U
+#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_0_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_0_WOSET 0U
+#define LPDDR4__PHY_ADR_CALVL_DEBUG_MODE_0__REG DENALI_PHY_1040
+#define LPDDR4__PHY_ADR_CALVL_DEBUG_MODE_0__FLD LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_0
+
+#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_0_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_0_WOSET 0U
+#define LPDDR4__SC_PHY_ADR_CALVL_DEBUG_CONT_0__REG DENALI_PHY_1040
+#define LPDDR4__SC_PHY_ADR_CALVL_DEBUG_CONT_0__FLD LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_0
+
+#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_0_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_0_WOSET 0U
+#define LPDDR4__SC_PHY_ADR_CALVL_ERROR_CLR_0__REG DENALI_PHY_1040
+#define LPDDR4__SC_PHY_ADR_CALVL_ERROR_CLR_0__FLD LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_0
+
+#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_OBS_SELECT_0_MASK 0x07000000U
+#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_OBS_SELECT_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_OBS_SELECT_0_WIDTH 3U
+#define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_0__REG DENALI_PHY_1040
+#define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_OBS_SELECT_0
+
+#define LPDDR4__DENALI_PHY_1041_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1041_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1041__PHY_ADR_CALVL_CH0_OBS0_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1041__PHY_ADR_CALVL_CH0_OBS0_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1041__PHY_ADR_CALVL_CH0_OBS0_0_WIDTH 32U
+#define LPDDR4__PHY_ADR_CALVL_CH0_OBS0_0__REG DENALI_PHY_1041
+#define LPDDR4__PHY_ADR_CALVL_CH0_OBS0_0__FLD LPDDR4__DENALI_PHY_1041__PHY_ADR_CALVL_CH0_OBS0_0
+
+#define LPDDR4__DENALI_PHY_1042_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1042_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1042__PHY_ADR_CALVL_CH1_OBS0_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1042__PHY_ADR_CALVL_CH1_OBS0_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1042__PHY_ADR_CALVL_CH1_OBS0_0_WIDTH 32U
+#define LPDDR4__PHY_ADR_CALVL_CH1_OBS0_0__REG DENALI_PHY_1042
+#define LPDDR4__PHY_ADR_CALVL_CH1_OBS0_0__FLD LPDDR4__DENALI_PHY_1042__PHY_ADR_CALVL_CH1_OBS0_0
+
+#define LPDDR4__DENALI_PHY_1043_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1043_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS1_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS1_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS1_0_WIDTH 32U
+#define LPDDR4__PHY_ADR_CALVL_OBS1_0__REG DENALI_PHY_1043
+#define LPDDR4__PHY_ADR_CALVL_OBS1_0__FLD LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS1_0
+
+#define LPDDR4__DENALI_PHY_1044_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1044_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_OBS2_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_OBS2_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_OBS2_0_WIDTH 32U
+#define LPDDR4__PHY_ADR_CALVL_OBS2_0__REG DENALI_PHY_1044
+#define LPDDR4__PHY_ADR_CALVL_OBS2_0__FLD LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_OBS2_0
+
+#define LPDDR4__DENALI_PHY_1045_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1045_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_FG_0_0_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_FG_0_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_FG_0_0_WIDTH 20U
+#define LPDDR4__PHY_ADR_CALVL_FG_0_0__REG DENALI_PHY_1045
+#define LPDDR4__PHY_ADR_CALVL_FG_0_0__FLD LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_FG_0_0
+
+#define LPDDR4__DENALI_PHY_1046_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1046_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_BG_0_0_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_BG_0_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_BG_0_0_WIDTH 20U
+#define LPDDR4__PHY_ADR_CALVL_BG_0_0__REG DENALI_PHY_1046
+#define LPDDR4__PHY_ADR_CALVL_BG_0_0__FLD LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_BG_0_0
+
+#define LPDDR4__DENALI_PHY_1047_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1047_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_FG_1_0_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_FG_1_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_FG_1_0_WIDTH 20U
+#define LPDDR4__PHY_ADR_CALVL_FG_1_0__REG DENALI_PHY_1047
+#define LPDDR4__PHY_ADR_CALVL_FG_1_0__FLD LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_FG_1_0
+
+#define LPDDR4__DENALI_PHY_1048_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1048_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_BG_1_0_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_BG_1_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_BG_1_0_WIDTH 20U
+#define LPDDR4__PHY_ADR_CALVL_BG_1_0__REG DENALI_PHY_1048
+#define LPDDR4__PHY_ADR_CALVL_BG_1_0__FLD LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_BG_1_0
+
+#define LPDDR4__DENALI_PHY_1049_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1049_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_FG_2_0_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_FG_2_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_FG_2_0_WIDTH 20U
+#define LPDDR4__PHY_ADR_CALVL_FG_2_0__REG DENALI_PHY_1049
+#define LPDDR4__PHY_ADR_CALVL_FG_2_0__FLD LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_FG_2_0
+
+#define LPDDR4__DENALI_PHY_1050_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1050_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_BG_2_0_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_BG_2_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_BG_2_0_WIDTH 20U
+#define LPDDR4__PHY_ADR_CALVL_BG_2_0__REG DENALI_PHY_1050
+#define LPDDR4__PHY_ADR_CALVL_BG_2_0__FLD LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_BG_2_0
+
+#define LPDDR4__DENALI_PHY_1051_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1051_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_FG_3_0_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_FG_3_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_FG_3_0_WIDTH 20U
+#define LPDDR4__PHY_ADR_CALVL_FG_3_0__REG DENALI_PHY_1051
+#define LPDDR4__PHY_ADR_CALVL_FG_3_0__FLD LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_FG_3_0
+
+#define LPDDR4__DENALI_PHY_1052_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1052_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1052__PHY_ADR_CALVL_BG_3_0_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1052__PHY_ADR_CALVL_BG_3_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1052__PHY_ADR_CALVL_BG_3_0_WIDTH 20U
+#define LPDDR4__PHY_ADR_CALVL_BG_3_0__REG DENALI_PHY_1052
+#define LPDDR4__PHY_ADR_CALVL_BG_3_0__FLD LPDDR4__DENALI_PHY_1052__PHY_ADR_CALVL_BG_3_0
+
+#define LPDDR4__DENALI_PHY_1053_READ_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1053_WRITE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1053__PHY_ADR_ADDR_SEL_0_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1053__PHY_ADR_ADDR_SEL_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1053__PHY_ADR_ADDR_SEL_0_WIDTH 30U
+#define LPDDR4__PHY_ADR_ADDR_SEL_0__REG DENALI_PHY_1053
+#define LPDDR4__PHY_ADR_ADDR_SEL_0__FLD LPDDR4__DENALI_PHY_1053__PHY_ADR_ADDR_SEL_0
+
+#define LPDDR4__DENALI_PHY_1054_READ_MASK 0x3F3F03FFU
+#define LPDDR4__DENALI_PHY_1054_WRITE_MASK 0x3F3F03FFU
+#define LPDDR4__DENALI_PHY_1054__PHY_ADR_LP4_BOOT_SLV_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_1054__PHY_ADR_LP4_BOOT_SLV_DELAY_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1054__PHY_ADR_LP4_BOOT_SLV_DELAY_0_WIDTH 10U
+#define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_0__REG DENALI_PHY_1054
+#define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_0__FLD LPDDR4__DENALI_PHY_1054__PHY_ADR_LP4_BOOT_SLV_DELAY_0
+
+#define LPDDR4__DENALI_PHY_1054__PHY_ADR_BIT_MASK_0_MASK 0x003F0000U
+#define LPDDR4__DENALI_PHY_1054__PHY_ADR_BIT_MASK_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1054__PHY_ADR_BIT_MASK_0_WIDTH 6U
+#define LPDDR4__PHY_ADR_BIT_MASK_0__REG DENALI_PHY_1054
+#define LPDDR4__PHY_ADR_BIT_MASK_0__FLD LPDDR4__DENALI_PHY_1054__PHY_ADR_BIT_MASK_0
+
+#define LPDDR4__DENALI_PHY_1054__PHY_ADR_SEG_MASK_0_MASK 0x3F000000U
+#define LPDDR4__DENALI_PHY_1054__PHY_ADR_SEG_MASK_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1054__PHY_ADR_SEG_MASK_0_WIDTH 6U
+#define LPDDR4__PHY_ADR_SEG_MASK_0__REG DENALI_PHY_1054
+#define LPDDR4__PHY_ADR_SEG_MASK_0__FLD LPDDR4__DENALI_PHY_1054__PHY_ADR_SEG_MASK_0
+
+#define LPDDR4__DENALI_PHY_1055_READ_MASK 0x3F0F3F3FU
+#define LPDDR4__DENALI_PHY_1055_WRITE_MASK 0x3F0F3F3FU
+#define LPDDR4__DENALI_PHY_1055__PHY_ADR_CALVL_TRAIN_MASK_0_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_1055__PHY_ADR_CALVL_TRAIN_MASK_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1055__PHY_ADR_CALVL_TRAIN_MASK_0_WIDTH 6U
+#define LPDDR4__PHY_ADR_CALVL_TRAIN_MASK_0__REG DENALI_PHY_1055
+#define LPDDR4__PHY_ADR_CALVL_TRAIN_MASK_0__FLD LPDDR4__DENALI_PHY_1055__PHY_ADR_CALVL_TRAIN_MASK_0
+
+#define LPDDR4__DENALI_PHY_1055__PHY_ADR_CSLVL_TRAIN_MASK_0_MASK 0x00003F00U
+#define LPDDR4__DENALI_PHY_1055__PHY_ADR_CSLVL_TRAIN_MASK_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1055__PHY_ADR_CSLVL_TRAIN_MASK_0_WIDTH 6U
+#define LPDDR4__PHY_ADR_CSLVL_TRAIN_MASK_0__REG DENALI_PHY_1055
+#define LPDDR4__PHY_ADR_CSLVL_TRAIN_MASK_0__FLD LPDDR4__DENALI_PHY_1055__PHY_ADR_CSLVL_TRAIN_MASK_0
+
+#define LPDDR4__DENALI_PHY_1055__PHY_ADR_STATIC_TOG_DISABLE_0_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_1055__PHY_ADR_STATIC_TOG_DISABLE_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1055__PHY_ADR_STATIC_TOG_DISABLE_0_WIDTH 4U
+#define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_0__REG DENALI_PHY_1055
+#define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_0__FLD LPDDR4__DENALI_PHY_1055__PHY_ADR_STATIC_TOG_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXIO_CTRL_0_MASK 0x3F000000U
+#define LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXIO_CTRL_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXIO_CTRL_0_WIDTH 6U
+#define LPDDR4__PHY_ADR_SW_TXIO_CTRL_0__REG DENALI_PHY_1055
+#define LPDDR4__PHY_ADR_SW_TXIO_CTRL_0__FLD LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXIO_CTRL_0
+
+#define LPDDR4__DENALI_PHY_1056_READ_MASK 0xFFFFFF03U
+#define LPDDR4__DENALI_PHY_1056_WRITE_MASK 0xFFFFFF03U
+#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_INIT_DISABLE_0_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_INIT_DISABLE_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_INIT_DISABLE_0_WIDTH 2U
+#define LPDDR4__PHY_ADR_DC_INIT_DISABLE_0__REG DENALI_PHY_1056
+#define LPDDR4__PHY_ADR_DC_INIT_DISABLE_0__FLD LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_INIT_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR0_CLK_ADJUST_0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR0_CLK_ADJUST_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR0_CLK_ADJUST_0_WIDTH 8U
+#define LPDDR4__PHY_ADR_DC_ADR0_CLK_ADJUST_0__REG DENALI_PHY_1056
+#define LPDDR4__PHY_ADR_DC_ADR0_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR0_CLK_ADJUST_0
+
+#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR1_CLK_ADJUST_0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR1_CLK_ADJUST_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR1_CLK_ADJUST_0_WIDTH 8U
+#define LPDDR4__PHY_ADR_DC_ADR1_CLK_ADJUST_0__REG DENALI_PHY_1056
+#define LPDDR4__PHY_ADR_DC_ADR1_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR1_CLK_ADJUST_0
+
+#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR2_CLK_ADJUST_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR2_CLK_ADJUST_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR2_CLK_ADJUST_0_WIDTH 8U
+#define LPDDR4__PHY_ADR_DC_ADR2_CLK_ADJUST_0__REG DENALI_PHY_1056
+#define LPDDR4__PHY_ADR_DC_ADR2_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR2_CLK_ADJUST_0
+
+#define LPDDR4__DENALI_PHY_1057_READ_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_PHY_1057_WRITE_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR3_CLK_ADJUST_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR3_CLK_ADJUST_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR3_CLK_ADJUST_0_WIDTH 8U
+#define LPDDR4__PHY_ADR_DC_ADR3_CLK_ADJUST_0__REG DENALI_PHY_1057
+#define LPDDR4__PHY_ADR_DC_ADR3_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR3_CLK_ADJUST_0
+
+#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR4_CLK_ADJUST_0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR4_CLK_ADJUST_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR4_CLK_ADJUST_0_WIDTH 8U
+#define LPDDR4__PHY_ADR_DC_ADR4_CLK_ADJUST_0__REG DENALI_PHY_1057
+#define LPDDR4__PHY_ADR_DC_ADR4_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR4_CLK_ADJUST_0
+
+#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR5_CLK_ADJUST_0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR5_CLK_ADJUST_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR5_CLK_ADJUST_0_WIDTH 8U
+#define LPDDR4__PHY_ADR_DC_ADR5_CLK_ADJUST_0__REG DENALI_PHY_1057
+#define LPDDR4__PHY_ADR_DC_ADR5_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR5_CLK_ADJUST_0
+
+#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0_WOSET 0U
+#define LPDDR4__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0__REG DENALI_PHY_1057
+#define LPDDR4__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_1057__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_1058_READ_MASK 0x3F03FFFFU
+#define LPDDR4__DENALI_PHY_1058_WRITE_MASK 0x3F03FFFFU
+#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_SAMPLE_WAIT_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_SAMPLE_WAIT_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_SAMPLE_WAIT_0_WIDTH 8U
+#define LPDDR4__PHY_ADR_DC_CAL_SAMPLE_WAIT_0__REG DENALI_PHY_1058
+#define LPDDR4__PHY_ADR_DC_CAL_SAMPLE_WAIT_0__FLD LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_SAMPLE_WAIT_0
+
+#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_TIMEOUT_0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_TIMEOUT_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_TIMEOUT_0_WIDTH 8U
+#define LPDDR4__PHY_ADR_DC_CAL_TIMEOUT_0__REG DENALI_PHY_1058
+#define LPDDR4__PHY_ADR_DC_CAL_TIMEOUT_0__FLD LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_TIMEOUT_0
+
+#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_WEIGHT_0_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_WEIGHT_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_WEIGHT_0_WIDTH 2U
+#define LPDDR4__PHY_ADR_DC_WEIGHT_0__REG DENALI_PHY_1058
+#define LPDDR4__PHY_ADR_DC_WEIGHT_0__FLD LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_WEIGHT_0
+
+#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_ADJUST_START_0_MASK 0x3F000000U
+#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_ADJUST_START_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_ADJUST_START_0_WIDTH 6U
+#define LPDDR4__PHY_ADR_DC_ADJUST_START_0__REG DENALI_PHY_1058
+#define LPDDR4__PHY_ADR_DC_ADJUST_START_0__FLD LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_ADJUST_START_0
+
+#define LPDDR4__DENALI_PHY_1059_READ_MASK 0x0101FFFFU
+#define LPDDR4__DENALI_PHY_1059_WRITE_MASK 0x0101FFFFU
+#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_SAMPLE_CNT_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_SAMPLE_CNT_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_SAMPLE_CNT_0_WIDTH 8U
+#define LPDDR4__PHY_ADR_DC_ADJUST_SAMPLE_CNT_0__REG DENALI_PHY_1059
+#define LPDDR4__PHY_ADR_DC_ADJUST_SAMPLE_CNT_0__FLD LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_SAMPLE_CNT_0
+
+#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_THRSHLD_0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_THRSHLD_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_THRSHLD_0_WIDTH 8U
+#define LPDDR4__PHY_ADR_DC_ADJUST_THRSHLD_0__REG DENALI_PHY_1059
+#define LPDDR4__PHY_ADR_DC_ADJUST_THRSHLD_0__FLD LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_THRSHLD_0
+
+#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_DIRECT_0_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_DIRECT_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_DIRECT_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_DIRECT_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_DIRECT_0_WOSET 0U
+#define LPDDR4__PHY_ADR_DC_ADJUST_DIRECT_0__REG DENALI_PHY_1059
+#define LPDDR4__PHY_ADR_DC_ADJUST_DIRECT_0__FLD LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_DIRECT_0
+
+#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_CAL_POLARITY_0_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_CAL_POLARITY_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_CAL_POLARITY_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_CAL_POLARITY_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_CAL_POLARITY_0_WOSET 0U
+#define LPDDR4__PHY_ADR_DC_CAL_POLARITY_0__REG DENALI_PHY_1059
+#define LPDDR4__PHY_ADR_DC_CAL_POLARITY_0__FLD LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_CAL_POLARITY_0
+
+#define LPDDR4__DENALI_PHY_1060_READ_MASK 0x00003F01U
+#define LPDDR4__DENALI_PHY_1060_WRITE_MASK 0x00003F01U
+#define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_WOSET 0U
+#define LPDDR4__PHY_ADR_DC_CAL_START_0__REG DENALI_PHY_1060
+#define LPDDR4__PHY_ADR_DC_CAL_START_0__FLD LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0
+
+#define LPDDR4__DENALI_PHY_1060__PHY_ADR_SW_TXPWR_CTRL_0_MASK 0x00003F00U
+#define LPDDR4__DENALI_PHY_1060__PHY_ADR_SW_TXPWR_CTRL_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1060__PHY_ADR_SW_TXPWR_CTRL_0_WIDTH 6U
+#define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_0__REG DENALI_PHY_1060
+#define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_0__FLD LPDDR4__DENALI_PHY_1060__PHY_ADR_SW_TXPWR_CTRL_0
+
+#define LPDDR4__DENALI_PHY_1061_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1061_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1061__PHY_ADR_TSEL_SELECT_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_1061__PHY_ADR_TSEL_SELECT_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1061__PHY_ADR_TSEL_SELECT_0_WIDTH 8U
+#define LPDDR4__PHY_ADR_TSEL_SELECT_0__REG DENALI_PHY_1061
+#define LPDDR4__PHY_ADR_TSEL_SELECT_0__FLD LPDDR4__DENALI_PHY_1061__PHY_ADR_TSEL_SELECT_0
+
+#define LPDDR4__DENALI_PHY_1061__PHY_ADR_DC_CAL_CLK_SEL_0_MASK 0x00000700U
+#define LPDDR4__DENALI_PHY_1061__PHY_ADR_DC_CAL_CLK_SEL_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1061__PHY_ADR_DC_CAL_CLK_SEL_0_WIDTH 3U
+#define LPDDR4__PHY_ADR_DC_CAL_CLK_SEL_0__REG DENALI_PHY_1061
+#define LPDDR4__PHY_ADR_DC_CAL_CLK_SEL_0__FLD LPDDR4__DENALI_PHY_1061__PHY_ADR_DC_CAL_CLK_SEL_0
+
+#define LPDDR4__DENALI_PHY_1061__PHY_PAD_ADR_IO_CFG_0_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_1061__PHY_PAD_ADR_IO_CFG_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1061__PHY_PAD_ADR_IO_CFG_0_WIDTH 11U
+#define LPDDR4__PHY_PAD_ADR_IO_CFG_0__REG DENALI_PHY_1061
+#define LPDDR4__PHY_PAD_ADR_IO_CFG_0__FLD LPDDR4__DENALI_PHY_1061__PHY_PAD_ADR_IO_CFG_0
+
+#define LPDDR4__DENALI_PHY_1062_READ_MASK 0x07FF1F07U
+#define LPDDR4__DENALI_PHY_1062_WRITE_MASK 0x07FF1F07U
+#define LPDDR4__DENALI_PHY_1062__PHY_PAD_ADR_RX_PCLK_CLK_SEL_0_MASK 0x00000007U
+#define LPDDR4__DENALI_PHY_1062__PHY_PAD_ADR_RX_PCLK_CLK_SEL_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1062__PHY_PAD_ADR_RX_PCLK_CLK_SEL_0_WIDTH 3U
+#define LPDDR4__PHY_PAD_ADR_RX_PCLK_CLK_SEL_0__REG DENALI_PHY_1062
+#define LPDDR4__PHY_PAD_ADR_RX_PCLK_CLK_SEL_0__FLD LPDDR4__DENALI_PHY_1062__PHY_PAD_ADR_RX_PCLK_CLK_SEL_0
+
+#define LPDDR4__DENALI_PHY_1062__PHY_ADR0_SW_WRADDR_SHIFT_0_MASK 0x00001F00U
+#define LPDDR4__DENALI_PHY_1062__PHY_ADR0_SW_WRADDR_SHIFT_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1062__PHY_ADR0_SW_WRADDR_SHIFT_0_WIDTH 5U
+#define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1062
+#define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1062__PHY_ADR0_SW_WRADDR_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_1062__PHY_ADR0_CLK_WR_SLAVE_DELAY_0_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_1062__PHY_ADR0_CLK_WR_SLAVE_DELAY_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1062__PHY_ADR0_CLK_WR_SLAVE_DELAY_0_WIDTH 11U
+#define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_1062
+#define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1062__PHY_ADR0_CLK_WR_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_1063_READ_MASK 0x1F07FF1FU
+#define LPDDR4__DENALI_PHY_1063_WRITE_MASK 0x1F07FF1FU
+#define LPDDR4__DENALI_PHY_1063__PHY_ADR1_SW_WRADDR_SHIFT_0_MASK 0x0000001FU
+#define LPDDR4__DENALI_PHY_1063__PHY_ADR1_SW_WRADDR_SHIFT_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1063__PHY_ADR1_SW_WRADDR_SHIFT_0_WIDTH 5U
+#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1063
+#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1063__PHY_ADR1_SW_WRADDR_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_1063__PHY_ADR1_CLK_WR_SLAVE_DELAY_0_MASK 0x0007FF00U
+#define LPDDR4__DENALI_PHY_1063__PHY_ADR1_CLK_WR_SLAVE_DELAY_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1063__PHY_ADR1_CLK_WR_SLAVE_DELAY_0_WIDTH 11U
+#define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_1063
+#define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1063__PHY_ADR1_CLK_WR_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_1063__PHY_ADR2_SW_WRADDR_SHIFT_0_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_1063__PHY_ADR2_SW_WRADDR_SHIFT_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1063__PHY_ADR2_SW_WRADDR_SHIFT_0_WIDTH 5U
+#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1063
+#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1063__PHY_ADR2_SW_WRADDR_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_1064_READ_MASK 0x001F07FFU
+#define LPDDR4__DENALI_PHY_1064_WRITE_MASK 0x001F07FFU
+#define LPDDR4__DENALI_PHY_1064__PHY_ADR2_CLK_WR_SLAVE_DELAY_0_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1064__PHY_ADR2_CLK_WR_SLAVE_DELAY_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1064__PHY_ADR2_CLK_WR_SLAVE_DELAY_0_WIDTH 11U
+#define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_1064
+#define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1064__PHY_ADR2_CLK_WR_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_1064__PHY_ADR3_SW_WRADDR_SHIFT_0_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_1064__PHY_ADR3_SW_WRADDR_SHIFT_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1064__PHY_ADR3_SW_WRADDR_SHIFT_0_WIDTH 5U
+#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1064
+#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1064__PHY_ADR3_SW_WRADDR_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_1065_READ_MASK 0x001F07FFU
+#define LPDDR4__DENALI_PHY_1065_WRITE_MASK 0x001F07FFU
+#define LPDDR4__DENALI_PHY_1065__PHY_ADR3_CLK_WR_SLAVE_DELAY_0_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1065__PHY_ADR3_CLK_WR_SLAVE_DELAY_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1065__PHY_ADR3_CLK_WR_SLAVE_DELAY_0_WIDTH 11U
+#define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_1065
+#define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1065__PHY_ADR3_CLK_WR_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_1065__PHY_ADR4_SW_WRADDR_SHIFT_0_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_1065__PHY_ADR4_SW_WRADDR_SHIFT_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1065__PHY_ADR4_SW_WRADDR_SHIFT_0_WIDTH 5U
+#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1065
+#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1065__PHY_ADR4_SW_WRADDR_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_1066_READ_MASK 0x001F07FFU
+#define LPDDR4__DENALI_PHY_1066_WRITE_MASK 0x001F07FFU
+#define LPDDR4__DENALI_PHY_1066__PHY_ADR4_CLK_WR_SLAVE_DELAY_0_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1066__PHY_ADR4_CLK_WR_SLAVE_DELAY_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1066__PHY_ADR4_CLK_WR_SLAVE_DELAY_0_WIDTH 11U
+#define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_1066
+#define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1066__PHY_ADR4_CLK_WR_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_1066__PHY_ADR5_SW_WRADDR_SHIFT_0_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_1066__PHY_ADR5_SW_WRADDR_SHIFT_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1066__PHY_ADR5_SW_WRADDR_SHIFT_0_WIDTH 5U
+#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1066
+#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1066__PHY_ADR5_SW_WRADDR_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_1067_READ_MASK 0x000F07FFU
+#define LPDDR4__DENALI_PHY_1067_WRITE_MASK 0x000F07FFU
+#define LPDDR4__DENALI_PHY_1067__PHY_ADR5_CLK_WR_SLAVE_DELAY_0_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1067__PHY_ADR5_CLK_WR_SLAVE_DELAY_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1067__PHY_ADR5_CLK_WR_SLAVE_DELAY_0_WIDTH 11U
+#define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_1067
+#define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1067__PHY_ADR5_CLK_WR_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_1067__PHY_ADR_SW_MASTER_MODE_0_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_1067__PHY_ADR_SW_MASTER_MODE_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1067__PHY_ADR_SW_MASTER_MODE_0_WIDTH 4U
+#define LPDDR4__PHY_ADR_SW_MASTER_MODE_0__REG DENALI_PHY_1067
+#define LPDDR4__PHY_ADR_SW_MASTER_MODE_0__FLD LPDDR4__DENALI_PHY_1067__PHY_ADR_SW_MASTER_MODE_0
+
+#define LPDDR4__DENALI_PHY_1068_READ_MASK 0xFF3F07FFU
+#define LPDDR4__DENALI_PHY_1068_WRITE_MASK 0xFF3F07FFU
+#define LPDDR4__DENALI_PHY_1068__PHY_ADR_MASTER_DELAY_START_0_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1068__PHY_ADR_MASTER_DELAY_START_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1068__PHY_ADR_MASTER_DELAY_START_0_WIDTH 11U
+#define LPDDR4__PHY_ADR_MASTER_DELAY_START_0__REG DENALI_PHY_1068
+#define LPDDR4__PHY_ADR_MASTER_DELAY_START_0__FLD LPDDR4__DENALI_PHY_1068__PHY_ADR_MASTER_DELAY_START_0
+
+#define LPDDR4__DENALI_PHY_1068__PHY_ADR_MASTER_DELAY_STEP_0_MASK 0x003F0000U
+#define LPDDR4__DENALI_PHY_1068__PHY_ADR_MASTER_DELAY_STEP_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1068__PHY_ADR_MASTER_DELAY_STEP_0_WIDTH 6U
+#define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_0__REG DENALI_PHY_1068
+#define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_0__FLD LPDDR4__DENALI_PHY_1068__PHY_ADR_MASTER_DELAY_STEP_0
+
+#define LPDDR4__DENALI_PHY_1068__PHY_ADR_MASTER_DELAY_WAIT_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_1068__PHY_ADR_MASTER_DELAY_WAIT_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1068__PHY_ADR_MASTER_DELAY_WAIT_0_WIDTH 8U
+#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_0__REG DENALI_PHY_1068
+#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_0__FLD LPDDR4__DENALI_PHY_1068__PHY_ADR_MASTER_DELAY_WAIT_0
+
+#define LPDDR4__DENALI_PHY_1069_READ_MASK 0x0103FFFFU
+#define LPDDR4__DENALI_PHY_1069_WRITE_MASK 0x0103FFFFU
+#define LPDDR4__DENALI_PHY_1069__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_1069__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1069__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0_WIDTH 8U
+#define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0__REG DENALI_PHY_1069
+#define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0__FLD LPDDR4__DENALI_PHY_1069__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0
+
+#define LPDDR4__DENALI_PHY_1069__PHY_ADR_SW_CALVL_DVW_MIN_0_MASK 0x0003FF00U
+#define LPDDR4__DENALI_PHY_1069__PHY_ADR_SW_CALVL_DVW_MIN_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1069__PHY_ADR_SW_CALVL_DVW_MIN_0_WIDTH 10U
+#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_0__REG DENALI_PHY_1069
+#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_0__FLD LPDDR4__DENALI_PHY_1069__PHY_ADR_SW_CALVL_DVW_MIN_0
+
+#define LPDDR4__DENALI_PHY_1069__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_1069__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1069__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1069__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1069__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_WOSET 0U
+#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_0__REG DENALI_PHY_1069
+#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_0__FLD LPDDR4__DENALI_PHY_1069__PHY_ADR_SW_CALVL_DVW_MIN_EN_0
+
+#define LPDDR4__DENALI_PHY_1070_READ_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_1070_WRITE_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_1070__PHY_ADR_CALVL_DLY_STEP_0_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_1070__PHY_ADR_CALVL_DLY_STEP_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1070__PHY_ADR_CALVL_DLY_STEP_0_WIDTH 4U
+#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_0__REG DENALI_PHY_1070
+#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_1070__PHY_ADR_CALVL_DLY_STEP_0
+
+#define LPDDR4__DENALI_PHY_1071_READ_MASK 0x03FF010FU
+#define LPDDR4__DENALI_PHY_1071_WRITE_MASK 0x03FF010FU
+#define LPDDR4__DENALI_PHY_1071__PHY_ADR_CALVL_CAPTURE_CNT_0_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_1071__PHY_ADR_CALVL_CAPTURE_CNT_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1071__PHY_ADR_CALVL_CAPTURE_CNT_0_WIDTH 4U
+#define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_0__REG DENALI_PHY_1071
+#define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_0__FLD LPDDR4__DENALI_PHY_1071__PHY_ADR_CALVL_CAPTURE_CNT_0
+
+#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_WOSET 0U
+#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_0__REG DENALI_PHY_1071
+#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_0__FLD LPDDR4__DENALI_PHY_1071__PHY_ADR_MEAS_DLY_STEP_ENABLE_0
+
+#define LPDDR4__DENALI_PHY_1071__PHY_ADR_DC_INIT_SLV_DELAY_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_1071__PHY_ADR_DC_INIT_SLV_DELAY_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1071__PHY_ADR_DC_INIT_SLV_DELAY_0_WIDTH 10U
+#define LPDDR4__PHY_ADR_DC_INIT_SLV_DELAY_0__REG DENALI_PHY_1071
+#define LPDDR4__PHY_ADR_DC_INIT_SLV_DELAY_0__FLD LPDDR4__DENALI_PHY_1071__PHY_ADR_DC_INIT_SLV_DELAY_0
+
+#define LPDDR4__DENALI_PHY_1072_READ_MASK 0x0000FF01U
+#define LPDDR4__DENALI_PHY_1072_WRITE_MASK 0x0000FF01U
+#define LPDDR4__DENALI_PHY_1072__PHY_ADR_DC_CALVL_ENABLE_0_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1072__PHY_ADR_DC_CALVL_ENABLE_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1072__PHY_ADR_DC_CALVL_ENABLE_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1072__PHY_ADR_DC_CALVL_ENABLE_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1072__PHY_ADR_DC_CALVL_ENABLE_0_WOSET 0U
+#define LPDDR4__PHY_ADR_DC_CALVL_ENABLE_0__REG DENALI_PHY_1072
+#define LPDDR4__PHY_ADR_DC_CALVL_ENABLE_0__FLD LPDDR4__DENALI_PHY_1072__PHY_ADR_DC_CALVL_ENABLE_0
+
+#define LPDDR4__DENALI_PHY_1072__PHY_ADR_DC_DM_CLK_THRSHLD_0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_1072__PHY_ADR_DC_DM_CLK_THRSHLD_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1072__PHY_ADR_DC_DM_CLK_THRSHLD_0_WIDTH 8U
+#define LPDDR4__PHY_ADR_DC_DM_CLK_THRSHLD_0__REG DENALI_PHY_1072
+#define LPDDR4__PHY_ADR_DC_DM_CLK_THRSHLD_0__FLD LPDDR4__DENALI_PHY_1072__PHY_ADR_DC_DM_CLK_THRSHLD_0
+
+#endif /* REG_LPDDR4_ADDRESS_SLICE_0_MACROS_H_ */
diff --git a/drivers/ram/k3-ddrss/am62a/lpddr4_address_slice_1_macros.h b/drivers/ram/k3-ddrss/am62a/lpddr4_address_slice_1_macros.h
new file mode 100644
index 00000000000..69521c75c16
--- /dev/null
+++ b/drivers/ram/k3-ddrss/am62a/lpddr4_address_slice_1_macros.h
@@ -0,0 +1,778 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef REG_LPDDR4_ADDRESS_SLICE_1_MACROS_H_
+#define REG_LPDDR4_ADDRESS_SLICE_1_MACROS_H_
+
+#define LPDDR4__DENALI_PHY_1280_READ_MASK 0x000107FFU
+#define LPDDR4__DENALI_PHY_1280_WRITE_MASK 0x000107FFU
+#define LPDDR4__DENALI_PHY_1280__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_1_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1280__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1280__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_1_WIDTH 11U
+#define LPDDR4__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_1__REG DENALI_PHY_1280
+#define LPDDR4__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1280__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_1280__PHY_ADR_CLK_BYPASS_OVERRIDE_1_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_1280__PHY_ADR_CLK_BYPASS_OVERRIDE_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1280__PHY_ADR_CLK_BYPASS_OVERRIDE_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1280__PHY_ADR_CLK_BYPASS_OVERRIDE_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1280__PHY_ADR_CLK_BYPASS_OVERRIDE_1_WOSET 0U
+#define LPDDR4__PHY_ADR_CLK_BYPASS_OVERRIDE_1__REG DENALI_PHY_1280
+#define LPDDR4__PHY_ADR_CLK_BYPASS_OVERRIDE_1__FLD LPDDR4__DENALI_PHY_1280__PHY_ADR_CLK_BYPASS_OVERRIDE_1
+
+#define LPDDR4__DENALI_PHY_1280__SC_PHY_ADR_MANUAL_CLEAR_1_MASK 0x07000000U
+#define LPDDR4__DENALI_PHY_1280__SC_PHY_ADR_MANUAL_CLEAR_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1280__SC_PHY_ADR_MANUAL_CLEAR_1_WIDTH 3U
+#define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_1__REG DENALI_PHY_1280
+#define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_1__FLD LPDDR4__DENALI_PHY_1280__SC_PHY_ADR_MANUAL_CLEAR_1
+
+#define LPDDR4__DENALI_PHY_1281_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1281_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1281__PHY_ADR_LPBK_RESULT_OBS_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1281__PHY_ADR_LPBK_RESULT_OBS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1281__PHY_ADR_LPBK_RESULT_OBS_1_WIDTH 32U
+#define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_1__REG DENALI_PHY_1281
+#define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_1__FLD LPDDR4__DENALI_PHY_1281__PHY_ADR_LPBK_RESULT_OBS_1
+
+#define LPDDR4__DENALI_PHY_1282_READ_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1282_WRITE_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1282__PHY_ADR_LPBK_ERROR_COUNT_OBS_1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1282__PHY_ADR_LPBK_ERROR_COUNT_OBS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1282__PHY_ADR_LPBK_ERROR_COUNT_OBS_1_WIDTH 16U
+#define LPDDR4__PHY_ADR_LPBK_ERROR_COUNT_OBS_1__REG DENALI_PHY_1282
+#define LPDDR4__PHY_ADR_LPBK_ERROR_COUNT_OBS_1__FLD LPDDR4__DENALI_PHY_1282__PHY_ADR_LPBK_ERROR_COUNT_OBS_1
+
+#define LPDDR4__DENALI_PHY_1282__PHY_ADR_MEAS_DLY_STEP_VALUE_1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_1282__PHY_ADR_MEAS_DLY_STEP_VALUE_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1282__PHY_ADR_MEAS_DLY_STEP_VALUE_1_WIDTH 8U
+#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_VALUE_1__REG DENALI_PHY_1282
+#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_VALUE_1__FLD LPDDR4__DENALI_PHY_1282__PHY_ADR_MEAS_DLY_STEP_VALUE_1
+
+#define LPDDR4__DENALI_PHY_1282__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_1_MASK 0x0F000000U
+#define LPDDR4__DENALI_PHY_1282__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1282__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_1_WIDTH 4U
+#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_1__REG DENALI_PHY_1282
+#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_1282__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_1
+
+#define LPDDR4__DENALI_PHY_1283_READ_MASK 0xFF7F07FFU
+#define LPDDR4__DENALI_PHY_1283_WRITE_MASK 0xFF7F07FFU
+#define LPDDR4__DENALI_PHY_1283__PHY_ADR_MASTER_DLY_LOCK_OBS_1_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1283__PHY_ADR_MASTER_DLY_LOCK_OBS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1283__PHY_ADR_MASTER_DLY_LOCK_OBS_1_WIDTH 11U
+#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_1__REG DENALI_PHY_1283
+#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_1__FLD LPDDR4__DENALI_PHY_1283__PHY_ADR_MASTER_DLY_LOCK_OBS_1
+
+#define LPDDR4__DENALI_PHY_1283__PHY_ADR_BASE_SLV_DLY_ENC_OBS_1_MASK 0x007F0000U
+#define LPDDR4__DENALI_PHY_1283__PHY_ADR_BASE_SLV_DLY_ENC_OBS_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1283__PHY_ADR_BASE_SLV_DLY_ENC_OBS_1_WIDTH 7U
+#define LPDDR4__PHY_ADR_BASE_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_1283
+#define LPDDR4__PHY_ADR_BASE_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_1283__PHY_ADR_BASE_SLV_DLY_ENC_OBS_1
+
+#define LPDDR4__DENALI_PHY_1283__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_1_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_1283__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1283__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_1_WIDTH 8U
+#define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_1283
+#define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_1283__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_1
+
+#define LPDDR4__DENALI_PHY_1284_READ_MASK 0x01000707U
+#define LPDDR4__DENALI_PHY_1284_WRITE_MASK 0x01000707U
+#define LPDDR4__DENALI_PHY_1284__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_1_MASK 0x00000007U
+#define LPDDR4__DENALI_PHY_1284__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1284__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_1_WIDTH 3U
+#define LPDDR4__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_1__REG DENALI_PHY_1284
+#define LPDDR4__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_1__FLD LPDDR4__DENALI_PHY_1284__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_1
+
+#define LPDDR4__DENALI_PHY_1284__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_1_MASK 0x00000700U
+#define LPDDR4__DENALI_PHY_1284__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1284__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_1_WIDTH 3U
+#define LPDDR4__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_1__REG DENALI_PHY_1284
+#define LPDDR4__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_1284__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_1
+
+#define LPDDR4__DENALI_PHY_1284__SC_PHY_ADR_SNAP_OBS_REGS_1_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_1284__SC_PHY_ADR_SNAP_OBS_REGS_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1284__SC_PHY_ADR_SNAP_OBS_REGS_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1284__SC_PHY_ADR_SNAP_OBS_REGS_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1284__SC_PHY_ADR_SNAP_OBS_REGS_1_WOSET 0U
+#define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_1__REG DENALI_PHY_1284
+#define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_1__FLD LPDDR4__DENALI_PHY_1284__SC_PHY_ADR_SNAP_OBS_REGS_1
+
+#define LPDDR4__DENALI_PHY_1284__PHY_ADR_TSEL_ENABLE_1_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_1284__PHY_ADR_TSEL_ENABLE_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1284__PHY_ADR_TSEL_ENABLE_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1284__PHY_ADR_TSEL_ENABLE_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1284__PHY_ADR_TSEL_ENABLE_1_WOSET 0U
+#define LPDDR4__PHY_ADR_TSEL_ENABLE_1__REG DENALI_PHY_1284
+#define LPDDR4__PHY_ADR_TSEL_ENABLE_1__FLD LPDDR4__DENALI_PHY_1284__PHY_ADR_TSEL_ENABLE_1
+
+#define LPDDR4__DENALI_PHY_1285_READ_MASK 0x011F7F7FU
+#define LPDDR4__DENALI_PHY_1285_WRITE_MASK 0x011F7F7FU
+#define LPDDR4__DENALI_PHY_1285__PHY_ADR_LPBK_CONTROL_1_MASK 0x0000007FU
+#define LPDDR4__DENALI_PHY_1285__PHY_ADR_LPBK_CONTROL_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1285__PHY_ADR_LPBK_CONTROL_1_WIDTH 7U
+#define LPDDR4__PHY_ADR_LPBK_CONTROL_1__REG DENALI_PHY_1285
+#define LPDDR4__PHY_ADR_LPBK_CONTROL_1__FLD LPDDR4__DENALI_PHY_1285__PHY_ADR_LPBK_CONTROL_1
+
+#define LPDDR4__DENALI_PHY_1285__PHY_ADR_PRBS_PATTERN_START_1_MASK 0x00007F00U
+#define LPDDR4__DENALI_PHY_1285__PHY_ADR_PRBS_PATTERN_START_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1285__PHY_ADR_PRBS_PATTERN_START_1_WIDTH 7U
+#define LPDDR4__PHY_ADR_PRBS_PATTERN_START_1__REG DENALI_PHY_1285
+#define LPDDR4__PHY_ADR_PRBS_PATTERN_START_1__FLD LPDDR4__DENALI_PHY_1285__PHY_ADR_PRBS_PATTERN_START_1
+
+#define LPDDR4__DENALI_PHY_1285__PHY_ADR_PRBS_PATTERN_MASK_1_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_1285__PHY_ADR_PRBS_PATTERN_MASK_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1285__PHY_ADR_PRBS_PATTERN_MASK_1_WIDTH 5U
+#define LPDDR4__PHY_ADR_PRBS_PATTERN_MASK_1__REG DENALI_PHY_1285
+#define LPDDR4__PHY_ADR_PRBS_PATTERN_MASK_1__FLD LPDDR4__DENALI_PHY_1285__PHY_ADR_PRBS_PATTERN_MASK_1
+
+#define LPDDR4__DENALI_PHY_1285__PHY_ADR_PWR_RDC_DISABLE_1_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_1285__PHY_ADR_PWR_RDC_DISABLE_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1285__PHY_ADR_PWR_RDC_DISABLE_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1285__PHY_ADR_PWR_RDC_DISABLE_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1285__PHY_ADR_PWR_RDC_DISABLE_1_WOSET 0U
+#define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_1__REG DENALI_PHY_1285
+#define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_1__FLD LPDDR4__DENALI_PHY_1285__PHY_ADR_PWR_RDC_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_1286_READ_MASK 0x01070301U
+#define LPDDR4__DENALI_PHY_1286_WRITE_MASK 0x01070301U
+#define LPDDR4__DENALI_PHY_1286__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1286__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1286__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1286__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1286__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1_WOSET 0U
+#define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1__REG DENALI_PHY_1286
+#define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1__FLD LPDDR4__DENALI_PHY_1286__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_1286__PHY_ADR_TYPE_1_MASK 0x00000300U
+#define LPDDR4__DENALI_PHY_1286__PHY_ADR_TYPE_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1286__PHY_ADR_TYPE_1_WIDTH 2U
+#define LPDDR4__PHY_ADR_TYPE_1__REG DENALI_PHY_1286
+#define LPDDR4__PHY_ADR_TYPE_1__FLD LPDDR4__DENALI_PHY_1286__PHY_ADR_TYPE_1
+
+#define LPDDR4__DENALI_PHY_1286__PHY_ADR_WRADDR_SHIFT_OBS_1_MASK 0x00070000U
+#define LPDDR4__DENALI_PHY_1286__PHY_ADR_WRADDR_SHIFT_OBS_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1286__PHY_ADR_WRADDR_SHIFT_OBS_1_WIDTH 3U
+#define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_1__REG DENALI_PHY_1286
+#define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_1__FLD LPDDR4__DENALI_PHY_1286__PHY_ADR_WRADDR_SHIFT_OBS_1
+
+#define LPDDR4__DENALI_PHY_1286__PHY_ADR_IE_MODE_1_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_1286__PHY_ADR_IE_MODE_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1286__PHY_ADR_IE_MODE_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1286__PHY_ADR_IE_MODE_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1286__PHY_ADR_IE_MODE_1_WOSET 0U
+#define LPDDR4__PHY_ADR_IE_MODE_1__REG DENALI_PHY_1286
+#define LPDDR4__PHY_ADR_IE_MODE_1__FLD LPDDR4__DENALI_PHY_1286__PHY_ADR_IE_MODE_1
+
+#define LPDDR4__DENALI_PHY_1287_READ_MASK 0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_1287_WRITE_MASK 0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_1287__PHY_ADR_DDL_MODE_1_MASK 0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_1287__PHY_ADR_DDL_MODE_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1287__PHY_ADR_DDL_MODE_1_WIDTH 27U
+#define LPDDR4__PHY_ADR_DDL_MODE_1__REG DENALI_PHY_1287
+#define LPDDR4__PHY_ADR_DDL_MODE_1__FLD LPDDR4__DENALI_PHY_1287__PHY_ADR_DDL_MODE_1
+
+#define LPDDR4__DENALI_PHY_1288_READ_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_1288_WRITE_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_1288__PHY_ADR_DDL_MASK_1_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_1288__PHY_ADR_DDL_MASK_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1288__PHY_ADR_DDL_MASK_1_WIDTH 6U
+#define LPDDR4__PHY_ADR_DDL_MASK_1__REG DENALI_PHY_1288
+#define LPDDR4__PHY_ADR_DDL_MASK_1__FLD LPDDR4__DENALI_PHY_1288__PHY_ADR_DDL_MASK_1
+
+#define LPDDR4__DENALI_PHY_1289_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1289_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1289__PHY_ADR_DDL_TEST_OBS_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1289__PHY_ADR_DDL_TEST_OBS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1289__PHY_ADR_DDL_TEST_OBS_1_WIDTH 32U
+#define LPDDR4__PHY_ADR_DDL_TEST_OBS_1__REG DENALI_PHY_1289
+#define LPDDR4__PHY_ADR_DDL_TEST_OBS_1__FLD LPDDR4__DENALI_PHY_1289__PHY_ADR_DDL_TEST_OBS_1
+
+#define LPDDR4__DENALI_PHY_1290_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1290_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1290__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1290__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1290__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_1_WIDTH 32U
+#define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_1__REG DENALI_PHY_1290
+#define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_1__FLD LPDDR4__DENALI_PHY_1290__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_1
+
+#define LPDDR4__DENALI_PHY_1291_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1291_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1291__PHY_ADR_CALVL_START_1_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1291__PHY_ADR_CALVL_START_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1291__PHY_ADR_CALVL_START_1_WIDTH 11U
+#define LPDDR4__PHY_ADR_CALVL_START_1__REG DENALI_PHY_1291
+#define LPDDR4__PHY_ADR_CALVL_START_1__FLD LPDDR4__DENALI_PHY_1291__PHY_ADR_CALVL_START_1
+
+#define LPDDR4__DENALI_PHY_1291__PHY_ADR_CALVL_COARSE_DLY_1_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_1291__PHY_ADR_CALVL_COARSE_DLY_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1291__PHY_ADR_CALVL_COARSE_DLY_1_WIDTH 11U
+#define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_1__REG DENALI_PHY_1291
+#define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_1__FLD LPDDR4__DENALI_PHY_1291__PHY_ADR_CALVL_COARSE_DLY_1
+
+#define LPDDR4__DENALI_PHY_1292_READ_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1292_WRITE_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1292__PHY_ADR_CALVL_QTR_1_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1292__PHY_ADR_CALVL_QTR_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1292__PHY_ADR_CALVL_QTR_1_WIDTH 11U
+#define LPDDR4__PHY_ADR_CALVL_QTR_1__REG DENALI_PHY_1292
+#define LPDDR4__PHY_ADR_CALVL_QTR_1__FLD LPDDR4__DENALI_PHY_1292__PHY_ADR_CALVL_QTR_1
+
+#define LPDDR4__DENALI_PHY_1293_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1293_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1293__PHY_ADR_CALVL_SWIZZLE0_1_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1293__PHY_ADR_CALVL_SWIZZLE0_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1293__PHY_ADR_CALVL_SWIZZLE0_1_WIDTH 24U
+#define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_1__REG DENALI_PHY_1293
+#define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_1__FLD LPDDR4__DENALI_PHY_1293__PHY_ADR_CALVL_SWIZZLE0_1
+
+#define LPDDR4__DENALI_PHY_1294_READ_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_1294_WRITE_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_1294__PHY_ADR_CALVL_SWIZZLE1_1_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1294__PHY_ADR_CALVL_SWIZZLE1_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1294__PHY_ADR_CALVL_SWIZZLE1_1_WIDTH 24U
+#define LPDDR4__PHY_ADR_CALVL_SWIZZLE1_1__REG DENALI_PHY_1294
+#define LPDDR4__PHY_ADR_CALVL_SWIZZLE1_1__FLD LPDDR4__DENALI_PHY_1294__PHY_ADR_CALVL_SWIZZLE1_1
+
+#define LPDDR4__DENALI_PHY_1294__PHY_ADR_CALVL_RANK_CTRL_1_MASK 0x03000000U
+#define LPDDR4__DENALI_PHY_1294__PHY_ADR_CALVL_RANK_CTRL_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1294__PHY_ADR_CALVL_RANK_CTRL_1_WIDTH 2U
+#define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_1__REG DENALI_PHY_1294
+#define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_1__FLD LPDDR4__DENALI_PHY_1294__PHY_ADR_CALVL_RANK_CTRL_1
+
+#define LPDDR4__DENALI_PHY_1295_READ_MASK 0x01FF0F03U
+#define LPDDR4__DENALI_PHY_1295_WRITE_MASK 0x01FF0F03U
+#define LPDDR4__DENALI_PHY_1295__PHY_ADR_CALVL_NUM_PATTERNS_1_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_1295__PHY_ADR_CALVL_NUM_PATTERNS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1295__PHY_ADR_CALVL_NUM_PATTERNS_1_WIDTH 2U
+#define LPDDR4__PHY_ADR_CALVL_NUM_PATTERNS_1__REG DENALI_PHY_1295
+#define LPDDR4__PHY_ADR_CALVL_NUM_PATTERNS_1__FLD LPDDR4__DENALI_PHY_1295__PHY_ADR_CALVL_NUM_PATTERNS_1
+
+#define LPDDR4__DENALI_PHY_1295__PHY_ADR_CALVL_RESP_WAIT_CNT_1_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_1295__PHY_ADR_CALVL_RESP_WAIT_CNT_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1295__PHY_ADR_CALVL_RESP_WAIT_CNT_1_WIDTH 4U
+#define LPDDR4__PHY_ADR_CALVL_RESP_WAIT_CNT_1__REG DENALI_PHY_1295
+#define LPDDR4__PHY_ADR_CALVL_RESP_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_1295__PHY_ADR_CALVL_RESP_WAIT_CNT_1
+
+#define LPDDR4__DENALI_PHY_1295__PHY_ADR_CALVL_PERIODIC_START_OFFSET_1_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_1295__PHY_ADR_CALVL_PERIODIC_START_OFFSET_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1295__PHY_ADR_CALVL_PERIODIC_START_OFFSET_1_WIDTH 9U
+#define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_1__REG DENALI_PHY_1295
+#define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_1__FLD LPDDR4__DENALI_PHY_1295__PHY_ADR_CALVL_PERIODIC_START_OFFSET_1
+
+#define LPDDR4__DENALI_PHY_1296_READ_MASK 0x07000001U
+#define LPDDR4__DENALI_PHY_1296_WRITE_MASK 0x07000001U
+#define LPDDR4__DENALI_PHY_1296__PHY_ADR_CALVL_DEBUG_MODE_1_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1296__PHY_ADR_CALVL_DEBUG_MODE_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1296__PHY_ADR_CALVL_DEBUG_MODE_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1296__PHY_ADR_CALVL_DEBUG_MODE_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1296__PHY_ADR_CALVL_DEBUG_MODE_1_WOSET 0U
+#define LPDDR4__PHY_ADR_CALVL_DEBUG_MODE_1__REG DENALI_PHY_1296
+#define LPDDR4__PHY_ADR_CALVL_DEBUG_MODE_1__FLD LPDDR4__DENALI_PHY_1296__PHY_ADR_CALVL_DEBUG_MODE_1
+
+#define LPDDR4__DENALI_PHY_1296__SC_PHY_ADR_CALVL_DEBUG_CONT_1_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_1296__SC_PHY_ADR_CALVL_DEBUG_CONT_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1296__SC_PHY_ADR_CALVL_DEBUG_CONT_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1296__SC_PHY_ADR_CALVL_DEBUG_CONT_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1296__SC_PHY_ADR_CALVL_DEBUG_CONT_1_WOSET 0U
+#define LPDDR4__SC_PHY_ADR_CALVL_DEBUG_CONT_1__REG DENALI_PHY_1296
+#define LPDDR4__SC_PHY_ADR_CALVL_DEBUG_CONT_1__FLD LPDDR4__DENALI_PHY_1296__SC_PHY_ADR_CALVL_DEBUG_CONT_1
+
+#define LPDDR4__DENALI_PHY_1296__SC_PHY_ADR_CALVL_ERROR_CLR_1_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_1296__SC_PHY_ADR_CALVL_ERROR_CLR_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1296__SC_PHY_ADR_CALVL_ERROR_CLR_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1296__SC_PHY_ADR_CALVL_ERROR_CLR_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1296__SC_PHY_ADR_CALVL_ERROR_CLR_1_WOSET 0U
+#define LPDDR4__SC_PHY_ADR_CALVL_ERROR_CLR_1__REG DENALI_PHY_1296
+#define LPDDR4__SC_PHY_ADR_CALVL_ERROR_CLR_1__FLD LPDDR4__DENALI_PHY_1296__SC_PHY_ADR_CALVL_ERROR_CLR_1
+
+#define LPDDR4__DENALI_PHY_1296__PHY_ADR_CALVL_OBS_SELECT_1_MASK 0x07000000U
+#define LPDDR4__DENALI_PHY_1296__PHY_ADR_CALVL_OBS_SELECT_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1296__PHY_ADR_CALVL_OBS_SELECT_1_WIDTH 3U
+#define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_1__REG DENALI_PHY_1296
+#define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_1296__PHY_ADR_CALVL_OBS_SELECT_1
+
+#define LPDDR4__DENALI_PHY_1297_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1297_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1297__PHY_ADR_CALVL_CH0_OBS0_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1297__PHY_ADR_CALVL_CH0_OBS0_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1297__PHY_ADR_CALVL_CH0_OBS0_1_WIDTH 32U
+#define LPDDR4__PHY_ADR_CALVL_CH0_OBS0_1__REG DENALI_PHY_1297
+#define LPDDR4__PHY_ADR_CALVL_CH0_OBS0_1__FLD LPDDR4__DENALI_PHY_1297__PHY_ADR_CALVL_CH0_OBS0_1
+
+#define LPDDR4__DENALI_PHY_1298_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1298_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1298__PHY_ADR_CALVL_CH1_OBS0_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1298__PHY_ADR_CALVL_CH1_OBS0_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1298__PHY_ADR_CALVL_CH1_OBS0_1_WIDTH 32U
+#define LPDDR4__PHY_ADR_CALVL_CH1_OBS0_1__REG DENALI_PHY_1298
+#define LPDDR4__PHY_ADR_CALVL_CH1_OBS0_1__FLD LPDDR4__DENALI_PHY_1298__PHY_ADR_CALVL_CH1_OBS0_1
+
+#define LPDDR4__DENALI_PHY_1299_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1299_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1299__PHY_ADR_CALVL_OBS1_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1299__PHY_ADR_CALVL_OBS1_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1299__PHY_ADR_CALVL_OBS1_1_WIDTH 32U
+#define LPDDR4__PHY_ADR_CALVL_OBS1_1__REG DENALI_PHY_1299
+#define LPDDR4__PHY_ADR_CALVL_OBS1_1__FLD LPDDR4__DENALI_PHY_1299__PHY_ADR_CALVL_OBS1_1
+
+#define LPDDR4__DENALI_PHY_1300_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1300_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1300__PHY_ADR_CALVL_OBS2_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1300__PHY_ADR_CALVL_OBS2_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1300__PHY_ADR_CALVL_OBS2_1_WIDTH 32U
+#define LPDDR4__PHY_ADR_CALVL_OBS2_1__REG DENALI_PHY_1300
+#define LPDDR4__PHY_ADR_CALVL_OBS2_1__FLD LPDDR4__DENALI_PHY_1300__PHY_ADR_CALVL_OBS2_1
+
+#define LPDDR4__DENALI_PHY_1301_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1301_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1301__PHY_ADR_CALVL_FG_0_1_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1301__PHY_ADR_CALVL_FG_0_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1301__PHY_ADR_CALVL_FG_0_1_WIDTH 20U
+#define LPDDR4__PHY_ADR_CALVL_FG_0_1__REG DENALI_PHY_1301
+#define LPDDR4__PHY_ADR_CALVL_FG_0_1__FLD LPDDR4__DENALI_PHY_1301__PHY_ADR_CALVL_FG_0_1
+
+#define LPDDR4__DENALI_PHY_1302_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1302_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1302__PHY_ADR_CALVL_BG_0_1_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1302__PHY_ADR_CALVL_BG_0_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1302__PHY_ADR_CALVL_BG_0_1_WIDTH 20U
+#define LPDDR4__PHY_ADR_CALVL_BG_0_1__REG DENALI_PHY_1302
+#define LPDDR4__PHY_ADR_CALVL_BG_0_1__FLD LPDDR4__DENALI_PHY_1302__PHY_ADR_CALVL_BG_0_1
+
+#define LPDDR4__DENALI_PHY_1303_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1303_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1303__PHY_ADR_CALVL_FG_1_1_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1303__PHY_ADR_CALVL_FG_1_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1303__PHY_ADR_CALVL_FG_1_1_WIDTH 20U
+#define LPDDR4__PHY_ADR_CALVL_FG_1_1__REG DENALI_PHY_1303
+#define LPDDR4__PHY_ADR_CALVL_FG_1_1__FLD LPDDR4__DENALI_PHY_1303__PHY_ADR_CALVL_FG_1_1
+
+#define LPDDR4__DENALI_PHY_1304_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1304_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1304__PHY_ADR_CALVL_BG_1_1_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1304__PHY_ADR_CALVL_BG_1_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1304__PHY_ADR_CALVL_BG_1_1_WIDTH 20U
+#define LPDDR4__PHY_ADR_CALVL_BG_1_1__REG DENALI_PHY_1304
+#define LPDDR4__PHY_ADR_CALVL_BG_1_1__FLD LPDDR4__DENALI_PHY_1304__PHY_ADR_CALVL_BG_1_1
+
+#define LPDDR4__DENALI_PHY_1305_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1305_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1305__PHY_ADR_CALVL_FG_2_1_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1305__PHY_ADR_CALVL_FG_2_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1305__PHY_ADR_CALVL_FG_2_1_WIDTH 20U
+#define LPDDR4__PHY_ADR_CALVL_FG_2_1__REG DENALI_PHY_1305
+#define LPDDR4__PHY_ADR_CALVL_FG_2_1__FLD LPDDR4__DENALI_PHY_1305__PHY_ADR_CALVL_FG_2_1
+
+#define LPDDR4__DENALI_PHY_1306_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1306_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1306__PHY_ADR_CALVL_BG_2_1_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1306__PHY_ADR_CALVL_BG_2_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1306__PHY_ADR_CALVL_BG_2_1_WIDTH 20U
+#define LPDDR4__PHY_ADR_CALVL_BG_2_1__REG DENALI_PHY_1306
+#define LPDDR4__PHY_ADR_CALVL_BG_2_1__FLD LPDDR4__DENALI_PHY_1306__PHY_ADR_CALVL_BG_2_1
+
+#define LPDDR4__DENALI_PHY_1307_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1307_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1307__PHY_ADR_CALVL_FG_3_1_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1307__PHY_ADR_CALVL_FG_3_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1307__PHY_ADR_CALVL_FG_3_1_WIDTH 20U
+#define LPDDR4__PHY_ADR_CALVL_FG_3_1__REG DENALI_PHY_1307
+#define LPDDR4__PHY_ADR_CALVL_FG_3_1__FLD LPDDR4__DENALI_PHY_1307__PHY_ADR_CALVL_FG_3_1
+
+#define LPDDR4__DENALI_PHY_1308_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1308_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1308__PHY_ADR_CALVL_BG_3_1_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1308__PHY_ADR_CALVL_BG_3_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1308__PHY_ADR_CALVL_BG_3_1_WIDTH 20U
+#define LPDDR4__PHY_ADR_CALVL_BG_3_1__REG DENALI_PHY_1308
+#define LPDDR4__PHY_ADR_CALVL_BG_3_1__FLD LPDDR4__DENALI_PHY_1308__PHY_ADR_CALVL_BG_3_1
+
+#define LPDDR4__DENALI_PHY_1309_READ_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1309_WRITE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1309__PHY_ADR_ADDR_SEL_1_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1309__PHY_ADR_ADDR_SEL_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1309__PHY_ADR_ADDR_SEL_1_WIDTH 30U
+#define LPDDR4__PHY_ADR_ADDR_SEL_1__REG DENALI_PHY_1309
+#define LPDDR4__PHY_ADR_ADDR_SEL_1__FLD LPDDR4__DENALI_PHY_1309__PHY_ADR_ADDR_SEL_1
+
+#define LPDDR4__DENALI_PHY_1310_READ_MASK 0x3F3F03FFU
+#define LPDDR4__DENALI_PHY_1310_WRITE_MASK 0x3F3F03FFU
+#define LPDDR4__DENALI_PHY_1310__PHY_ADR_LP4_BOOT_SLV_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_1310__PHY_ADR_LP4_BOOT_SLV_DELAY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1310__PHY_ADR_LP4_BOOT_SLV_DELAY_1_WIDTH 10U
+#define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_1__REG DENALI_PHY_1310
+#define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_1__FLD LPDDR4__DENALI_PHY_1310__PHY_ADR_LP4_BOOT_SLV_DELAY_1
+
+#define LPDDR4__DENALI_PHY_1310__PHY_ADR_BIT_MASK_1_MASK 0x003F0000U
+#define LPDDR4__DENALI_PHY_1310__PHY_ADR_BIT_MASK_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1310__PHY_ADR_BIT_MASK_1_WIDTH 6U
+#define LPDDR4__PHY_ADR_BIT_MASK_1__REG DENALI_PHY_1310
+#define LPDDR4__PHY_ADR_BIT_MASK_1__FLD LPDDR4__DENALI_PHY_1310__PHY_ADR_BIT_MASK_1
+
+#define LPDDR4__DENALI_PHY_1310__PHY_ADR_SEG_MASK_1_MASK 0x3F000000U
+#define LPDDR4__DENALI_PHY_1310__PHY_ADR_SEG_MASK_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1310__PHY_ADR_SEG_MASK_1_WIDTH 6U
+#define LPDDR4__PHY_ADR_SEG_MASK_1__REG DENALI_PHY_1310
+#define LPDDR4__PHY_ADR_SEG_MASK_1__FLD LPDDR4__DENALI_PHY_1310__PHY_ADR_SEG_MASK_1
+
+#define LPDDR4__DENALI_PHY_1311_READ_MASK 0x3F0F3F3FU
+#define LPDDR4__DENALI_PHY_1311_WRITE_MASK 0x3F0F3F3FU
+#define LPDDR4__DENALI_PHY_1311__PHY_ADR_CALVL_TRAIN_MASK_1_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_1311__PHY_ADR_CALVL_TRAIN_MASK_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1311__PHY_ADR_CALVL_TRAIN_MASK_1_WIDTH 6U
+#define LPDDR4__PHY_ADR_CALVL_TRAIN_MASK_1__REG DENALI_PHY_1311
+#define LPDDR4__PHY_ADR_CALVL_TRAIN_MASK_1__FLD LPDDR4__DENALI_PHY_1311__PHY_ADR_CALVL_TRAIN_MASK_1
+
+#define LPDDR4__DENALI_PHY_1311__PHY_ADR_CSLVL_TRAIN_MASK_1_MASK 0x00003F00U
+#define LPDDR4__DENALI_PHY_1311__PHY_ADR_CSLVL_TRAIN_MASK_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1311__PHY_ADR_CSLVL_TRAIN_MASK_1_WIDTH 6U
+#define LPDDR4__PHY_ADR_CSLVL_TRAIN_MASK_1__REG DENALI_PHY_1311
+#define LPDDR4__PHY_ADR_CSLVL_TRAIN_MASK_1__FLD LPDDR4__DENALI_PHY_1311__PHY_ADR_CSLVL_TRAIN_MASK_1
+
+#define LPDDR4__DENALI_PHY_1311__PHY_ADR_STATIC_TOG_DISABLE_1_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_1311__PHY_ADR_STATIC_TOG_DISABLE_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1311__PHY_ADR_STATIC_TOG_DISABLE_1_WIDTH 4U
+#define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_1__REG DENALI_PHY_1311
+#define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_1__FLD LPDDR4__DENALI_PHY_1311__PHY_ADR_STATIC_TOG_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_1311__PHY_ADR_SW_TXIO_CTRL_1_MASK 0x3F000000U
+#define LPDDR4__DENALI_PHY_1311__PHY_ADR_SW_TXIO_CTRL_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1311__PHY_ADR_SW_TXIO_CTRL_1_WIDTH 6U
+#define LPDDR4__PHY_ADR_SW_TXIO_CTRL_1__REG DENALI_PHY_1311
+#define LPDDR4__PHY_ADR_SW_TXIO_CTRL_1__FLD LPDDR4__DENALI_PHY_1311__PHY_ADR_SW_TXIO_CTRL_1
+
+#define LPDDR4__DENALI_PHY_1312_READ_MASK 0xFFFFFF03U
+#define LPDDR4__DENALI_PHY_1312_WRITE_MASK 0xFFFFFF03U
+#define LPDDR4__DENALI_PHY_1312__PHY_ADR_DC_INIT_DISABLE_1_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_1312__PHY_ADR_DC_INIT_DISABLE_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1312__PHY_ADR_DC_INIT_DISABLE_1_WIDTH 2U
+#define LPDDR4__PHY_ADR_DC_INIT_DISABLE_1__REG DENALI_PHY_1312
+#define LPDDR4__PHY_ADR_DC_INIT_DISABLE_1__FLD LPDDR4__DENALI_PHY_1312__PHY_ADR_DC_INIT_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_1312__PHY_ADR_DC_ADR0_CLK_ADJUST_1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_1312__PHY_ADR_DC_ADR0_CLK_ADJUST_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1312__PHY_ADR_DC_ADR0_CLK_ADJUST_1_WIDTH 8U
+#define LPDDR4__PHY_ADR_DC_ADR0_CLK_ADJUST_1__REG DENALI_PHY_1312
+#define LPDDR4__PHY_ADR_DC_ADR0_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_1312__PHY_ADR_DC_ADR0_CLK_ADJUST_1
+
+#define LPDDR4__DENALI_PHY_1312__PHY_ADR_DC_ADR1_CLK_ADJUST_1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_1312__PHY_ADR_DC_ADR1_CLK_ADJUST_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1312__PHY_ADR_DC_ADR1_CLK_ADJUST_1_WIDTH 8U
+#define LPDDR4__PHY_ADR_DC_ADR1_CLK_ADJUST_1__REG DENALI_PHY_1312
+#define LPDDR4__PHY_ADR_DC_ADR1_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_1312__PHY_ADR_DC_ADR1_CLK_ADJUST_1
+
+#define LPDDR4__DENALI_PHY_1312__PHY_ADR_DC_ADR2_CLK_ADJUST_1_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_1312__PHY_ADR_DC_ADR2_CLK_ADJUST_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1312__PHY_ADR_DC_ADR2_CLK_ADJUST_1_WIDTH 8U
+#define LPDDR4__PHY_ADR_DC_ADR2_CLK_ADJUST_1__REG DENALI_PHY_1312
+#define LPDDR4__PHY_ADR_DC_ADR2_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_1312__PHY_ADR_DC_ADR2_CLK_ADJUST_1
+
+#define LPDDR4__DENALI_PHY_1313_READ_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_PHY_1313_WRITE_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_PHY_1313__PHY_ADR_DC_ADR3_CLK_ADJUST_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_1313__PHY_ADR_DC_ADR3_CLK_ADJUST_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1313__PHY_ADR_DC_ADR3_CLK_ADJUST_1_WIDTH 8U
+#define LPDDR4__PHY_ADR_DC_ADR3_CLK_ADJUST_1__REG DENALI_PHY_1313
+#define LPDDR4__PHY_ADR_DC_ADR3_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_1313__PHY_ADR_DC_ADR3_CLK_ADJUST_1
+
+#define LPDDR4__DENALI_PHY_1313__PHY_ADR_DC_ADR4_CLK_ADJUST_1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_1313__PHY_ADR_DC_ADR4_CLK_ADJUST_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1313__PHY_ADR_DC_ADR4_CLK_ADJUST_1_WIDTH 8U
+#define LPDDR4__PHY_ADR_DC_ADR4_CLK_ADJUST_1__REG DENALI_PHY_1313
+#define LPDDR4__PHY_ADR_DC_ADR4_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_1313__PHY_ADR_DC_ADR4_CLK_ADJUST_1
+
+#define LPDDR4__DENALI_PHY_1313__PHY_ADR_DC_ADR5_CLK_ADJUST_1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_1313__PHY_ADR_DC_ADR5_CLK_ADJUST_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1313__PHY_ADR_DC_ADR5_CLK_ADJUST_1_WIDTH 8U
+#define LPDDR4__PHY_ADR_DC_ADR5_CLK_ADJUST_1__REG DENALI_PHY_1313
+#define LPDDR4__PHY_ADR_DC_ADR5_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_1313__PHY_ADR_DC_ADR5_CLK_ADJUST_1
+
+#define LPDDR4__DENALI_PHY_1313__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_1_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_1313__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1313__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1313__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1313__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_1_WOSET 0U
+#define LPDDR4__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_1__REG DENALI_PHY_1313
+#define LPDDR4__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_1__FLD LPDDR4__DENALI_PHY_1313__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_1314_READ_MASK 0x3F03FFFFU
+#define LPDDR4__DENALI_PHY_1314_WRITE_MASK 0x3F03FFFFU
+#define LPDDR4__DENALI_PHY_1314__PHY_ADR_DC_CAL_SAMPLE_WAIT_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_1314__PHY_ADR_DC_CAL_SAMPLE_WAIT_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1314__PHY_ADR_DC_CAL_SAMPLE_WAIT_1_WIDTH 8U
+#define LPDDR4__PHY_ADR_DC_CAL_SAMPLE_WAIT_1__REG DENALI_PHY_1314
+#define LPDDR4__PHY_ADR_DC_CAL_SAMPLE_WAIT_1__FLD LPDDR4__DENALI_PHY_1314__PHY_ADR_DC_CAL_SAMPLE_WAIT_1
+
+#define LPDDR4__DENALI_PHY_1314__PHY_ADR_DC_CAL_TIMEOUT_1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_1314__PHY_ADR_DC_CAL_TIMEOUT_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1314__PHY_ADR_DC_CAL_TIMEOUT_1_WIDTH 8U
+#define LPDDR4__PHY_ADR_DC_CAL_TIMEOUT_1__REG DENALI_PHY_1314
+#define LPDDR4__PHY_ADR_DC_CAL_TIMEOUT_1__FLD LPDDR4__DENALI_PHY_1314__PHY_ADR_DC_CAL_TIMEOUT_1
+
+#define LPDDR4__DENALI_PHY_1314__PHY_ADR_DC_WEIGHT_1_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_1314__PHY_ADR_DC_WEIGHT_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1314__PHY_ADR_DC_WEIGHT_1_WIDTH 2U
+#define LPDDR4__PHY_ADR_DC_WEIGHT_1__REG DENALI_PHY_1314
+#define LPDDR4__PHY_ADR_DC_WEIGHT_1__FLD LPDDR4__DENALI_PHY_1314__PHY_ADR_DC_WEIGHT_1
+
+#define LPDDR4__DENALI_PHY_1314__PHY_ADR_DC_ADJUST_START_1_MASK 0x3F000000U
+#define LPDDR4__DENALI_PHY_1314__PHY_ADR_DC_ADJUST_START_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1314__PHY_ADR_DC_ADJUST_START_1_WIDTH 6U
+#define LPDDR4__PHY_ADR_DC_ADJUST_START_1__REG DENALI_PHY_1314
+#define LPDDR4__PHY_ADR_DC_ADJUST_START_1__FLD LPDDR4__DENALI_PHY_1314__PHY_ADR_DC_ADJUST_START_1
+
+#define LPDDR4__DENALI_PHY_1315_READ_MASK 0x0101FFFFU
+#define LPDDR4__DENALI_PHY_1315_WRITE_MASK 0x0101FFFFU
+#define LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_ADJUST_SAMPLE_CNT_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_ADJUST_SAMPLE_CNT_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_ADJUST_SAMPLE_CNT_1_WIDTH 8U
+#define LPDDR4__PHY_ADR_DC_ADJUST_SAMPLE_CNT_1__REG DENALI_PHY_1315
+#define LPDDR4__PHY_ADR_DC_ADJUST_SAMPLE_CNT_1__FLD LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_ADJUST_SAMPLE_CNT_1
+
+#define LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_ADJUST_THRSHLD_1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_ADJUST_THRSHLD_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_ADJUST_THRSHLD_1_WIDTH 8U
+#define LPDDR4__PHY_ADR_DC_ADJUST_THRSHLD_1__REG DENALI_PHY_1315
+#define LPDDR4__PHY_ADR_DC_ADJUST_THRSHLD_1__FLD LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_ADJUST_THRSHLD_1
+
+#define LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_ADJUST_DIRECT_1_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_ADJUST_DIRECT_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_ADJUST_DIRECT_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_ADJUST_DIRECT_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_ADJUST_DIRECT_1_WOSET 0U
+#define LPDDR4__PHY_ADR_DC_ADJUST_DIRECT_1__REG DENALI_PHY_1315
+#define LPDDR4__PHY_ADR_DC_ADJUST_DIRECT_1__FLD LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_ADJUST_DIRECT_1
+
+#define LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_CAL_POLARITY_1_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_CAL_POLARITY_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_CAL_POLARITY_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_CAL_POLARITY_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_CAL_POLARITY_1_WOSET 0U
+#define LPDDR4__PHY_ADR_DC_CAL_POLARITY_1__REG DENALI_PHY_1315
+#define LPDDR4__PHY_ADR_DC_CAL_POLARITY_1__FLD LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_CAL_POLARITY_1
+
+#define LPDDR4__DENALI_PHY_1316_READ_MASK 0x00003F01U
+#define LPDDR4__DENALI_PHY_1316_WRITE_MASK 0x00003F01U
+#define LPDDR4__DENALI_PHY_1316__PHY_ADR_DC_CAL_START_1_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1316__PHY_ADR_DC_CAL_START_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1316__PHY_ADR_DC_CAL_START_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1316__PHY_ADR_DC_CAL_START_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1316__PHY_ADR_DC_CAL_START_1_WOSET 0U
+#define LPDDR4__PHY_ADR_DC_CAL_START_1__REG DENALI_PHY_1316
+#define LPDDR4__PHY_ADR_DC_CAL_START_1__FLD LPDDR4__DENALI_PHY_1316__PHY_ADR_DC_CAL_START_1
+
+#define LPDDR4__DENALI_PHY_1316__PHY_ADR_SW_TXPWR_CTRL_1_MASK 0x00003F00U
+#define LPDDR4__DENALI_PHY_1316__PHY_ADR_SW_TXPWR_CTRL_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1316__PHY_ADR_SW_TXPWR_CTRL_1_WIDTH 6U
+#define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_1__REG DENALI_PHY_1316
+#define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_1__FLD LPDDR4__DENALI_PHY_1316__PHY_ADR_SW_TXPWR_CTRL_1
+
+#define LPDDR4__DENALI_PHY_1317_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1317_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1317__PHY_ADR_TSEL_SELECT_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_1317__PHY_ADR_TSEL_SELECT_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1317__PHY_ADR_TSEL_SELECT_1_WIDTH 8U
+#define LPDDR4__PHY_ADR_TSEL_SELECT_1__REG DENALI_PHY_1317
+#define LPDDR4__PHY_ADR_TSEL_SELECT_1__FLD LPDDR4__DENALI_PHY_1317__PHY_ADR_TSEL_SELECT_1
+
+#define LPDDR4__DENALI_PHY_1317__PHY_ADR_DC_CAL_CLK_SEL_1_MASK 0x00000700U
+#define LPDDR4__DENALI_PHY_1317__PHY_ADR_DC_CAL_CLK_SEL_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1317__PHY_ADR_DC_CAL_CLK_SEL_1_WIDTH 3U
+#define LPDDR4__PHY_ADR_DC_CAL_CLK_SEL_1__REG DENALI_PHY_1317
+#define LPDDR4__PHY_ADR_DC_CAL_CLK_SEL_1__FLD LPDDR4__DENALI_PHY_1317__PHY_ADR_DC_CAL_CLK_SEL_1
+
+#define LPDDR4__DENALI_PHY_1317__PHY_PAD_ADR_IO_CFG_1_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_1317__PHY_PAD_ADR_IO_CFG_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1317__PHY_PAD_ADR_IO_CFG_1_WIDTH 11U
+#define LPDDR4__PHY_PAD_ADR_IO_CFG_1__REG DENALI_PHY_1317
+#define LPDDR4__PHY_PAD_ADR_IO_CFG_1__FLD LPDDR4__DENALI_PHY_1317__PHY_PAD_ADR_IO_CFG_1
+
+#define LPDDR4__DENALI_PHY_1318_READ_MASK 0x07FF1F07U
+#define LPDDR4__DENALI_PHY_1318_WRITE_MASK 0x07FF1F07U
+#define LPDDR4__DENALI_PHY_1318__PHY_PAD_ADR_RX_PCLK_CLK_SEL_1_MASK 0x00000007U
+#define LPDDR4__DENALI_PHY_1318__PHY_PAD_ADR_RX_PCLK_CLK_SEL_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1318__PHY_PAD_ADR_RX_PCLK_CLK_SEL_1_WIDTH 3U
+#define LPDDR4__PHY_PAD_ADR_RX_PCLK_CLK_SEL_1__REG DENALI_PHY_1318
+#define LPDDR4__PHY_PAD_ADR_RX_PCLK_CLK_SEL_1__FLD LPDDR4__DENALI_PHY_1318__PHY_PAD_ADR_RX_PCLK_CLK_SEL_1
+
+#define LPDDR4__DENALI_PHY_1318__PHY_ADR0_SW_WRADDR_SHIFT_1_MASK 0x00001F00U
+#define LPDDR4__DENALI_PHY_1318__PHY_ADR0_SW_WRADDR_SHIFT_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1318__PHY_ADR0_SW_WRADDR_SHIFT_1_WIDTH 5U
+#define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_1__REG DENALI_PHY_1318
+#define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_1__FLD LPDDR4__DENALI_PHY_1318__PHY_ADR0_SW_WRADDR_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_1318__PHY_ADR0_CLK_WR_SLAVE_DELAY_1_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_1318__PHY_ADR0_CLK_WR_SLAVE_DELAY_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1318__PHY_ADR0_CLK_WR_SLAVE_DELAY_1_WIDTH 11U
+#define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_1__REG DENALI_PHY_1318
+#define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1318__PHY_ADR0_CLK_WR_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_1319_READ_MASK 0x1F07FF1FU
+#define LPDDR4__DENALI_PHY_1319_WRITE_MASK 0x1F07FF1FU
+#define LPDDR4__DENALI_PHY_1319__PHY_ADR1_SW_WRADDR_SHIFT_1_MASK 0x0000001FU
+#define LPDDR4__DENALI_PHY_1319__PHY_ADR1_SW_WRADDR_SHIFT_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1319__PHY_ADR1_SW_WRADDR_SHIFT_1_WIDTH 5U
+#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_1__REG DENALI_PHY_1319
+#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_1__FLD LPDDR4__DENALI_PHY_1319__PHY_ADR1_SW_WRADDR_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_1319__PHY_ADR1_CLK_WR_SLAVE_DELAY_1_MASK 0x0007FF00U
+#define LPDDR4__DENALI_PHY_1319__PHY_ADR1_CLK_WR_SLAVE_DELAY_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1319__PHY_ADR1_CLK_WR_SLAVE_DELAY_1_WIDTH 11U
+#define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_1__REG DENALI_PHY_1319
+#define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1319__PHY_ADR1_CLK_WR_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_1319__PHY_ADR2_SW_WRADDR_SHIFT_1_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_1319__PHY_ADR2_SW_WRADDR_SHIFT_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1319__PHY_ADR2_SW_WRADDR_SHIFT_1_WIDTH 5U
+#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_1__REG DENALI_PHY_1319
+#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_1__FLD LPDDR4__DENALI_PHY_1319__PHY_ADR2_SW_WRADDR_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_1320_READ_MASK 0x001F07FFU
+#define LPDDR4__DENALI_PHY_1320_WRITE_MASK 0x001F07FFU
+#define LPDDR4__DENALI_PHY_1320__PHY_ADR2_CLK_WR_SLAVE_DELAY_1_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1320__PHY_ADR2_CLK_WR_SLAVE_DELAY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1320__PHY_ADR2_CLK_WR_SLAVE_DELAY_1_WIDTH 11U
+#define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_1__REG DENALI_PHY_1320
+#define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1320__PHY_ADR2_CLK_WR_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_1320__PHY_ADR3_SW_WRADDR_SHIFT_1_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_1320__PHY_ADR3_SW_WRADDR_SHIFT_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1320__PHY_ADR3_SW_WRADDR_SHIFT_1_WIDTH 5U
+#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_1__REG DENALI_PHY_1320
+#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_1__FLD LPDDR4__DENALI_PHY_1320__PHY_ADR3_SW_WRADDR_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_1321_READ_MASK 0x001F07FFU
+#define LPDDR4__DENALI_PHY_1321_WRITE_MASK 0x001F07FFU
+#define LPDDR4__DENALI_PHY_1321__PHY_ADR3_CLK_WR_SLAVE_DELAY_1_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1321__PHY_ADR3_CLK_WR_SLAVE_DELAY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1321__PHY_ADR3_CLK_WR_SLAVE_DELAY_1_WIDTH 11U
+#define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_1__REG DENALI_PHY_1321
+#define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1321__PHY_ADR3_CLK_WR_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_1321__PHY_ADR4_SW_WRADDR_SHIFT_1_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_1321__PHY_ADR4_SW_WRADDR_SHIFT_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1321__PHY_ADR4_SW_WRADDR_SHIFT_1_WIDTH 5U
+#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_1__REG DENALI_PHY_1321
+#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_1__FLD LPDDR4__DENALI_PHY_1321__PHY_ADR4_SW_WRADDR_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_1322_READ_MASK 0x001F07FFU
+#define LPDDR4__DENALI_PHY_1322_WRITE_MASK 0x001F07FFU
+#define LPDDR4__DENALI_PHY_1322__PHY_ADR4_CLK_WR_SLAVE_DELAY_1_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1322__PHY_ADR4_CLK_WR_SLAVE_DELAY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1322__PHY_ADR4_CLK_WR_SLAVE_DELAY_1_WIDTH 11U
+#define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_1__REG DENALI_PHY_1322
+#define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1322__PHY_ADR4_CLK_WR_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_1322__PHY_ADR5_SW_WRADDR_SHIFT_1_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_1322__PHY_ADR5_SW_WRADDR_SHIFT_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1322__PHY_ADR5_SW_WRADDR_SHIFT_1_WIDTH 5U
+#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_1__REG DENALI_PHY_1322
+#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_1__FLD LPDDR4__DENALI_PHY_1322__PHY_ADR5_SW_WRADDR_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_1323_READ_MASK 0x000F07FFU
+#define LPDDR4__DENALI_PHY_1323_WRITE_MASK 0x000F07FFU
+#define LPDDR4__DENALI_PHY_1323__PHY_ADR5_CLK_WR_SLAVE_DELAY_1_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1323__PHY_ADR5_CLK_WR_SLAVE_DELAY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1323__PHY_ADR5_CLK_WR_SLAVE_DELAY_1_WIDTH 11U
+#define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_1__REG DENALI_PHY_1323
+#define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1323__PHY_ADR5_CLK_WR_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_1323__PHY_ADR_SW_MASTER_MODE_1_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_1323__PHY_ADR_SW_MASTER_MODE_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1323__PHY_ADR_SW_MASTER_MODE_1_WIDTH 4U
+#define LPDDR4__PHY_ADR_SW_MASTER_MODE_1__REG DENALI_PHY_1323
+#define LPDDR4__PHY_ADR_SW_MASTER_MODE_1__FLD LPDDR4__DENALI_PHY_1323__PHY_ADR_SW_MASTER_MODE_1
+
+#define LPDDR4__DENALI_PHY_1324_READ_MASK 0xFF3F07FFU
+#define LPDDR4__DENALI_PHY_1324_WRITE_MASK 0xFF3F07FFU
+#define LPDDR4__DENALI_PHY_1324__PHY_ADR_MASTER_DELAY_START_1_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1324__PHY_ADR_MASTER_DELAY_START_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1324__PHY_ADR_MASTER_DELAY_START_1_WIDTH 11U
+#define LPDDR4__PHY_ADR_MASTER_DELAY_START_1__REG DENALI_PHY_1324
+#define LPDDR4__PHY_ADR_MASTER_DELAY_START_1__FLD LPDDR4__DENALI_PHY_1324__PHY_ADR_MASTER_DELAY_START_1
+
+#define LPDDR4__DENALI_PHY_1324__PHY_ADR_MASTER_DELAY_STEP_1_MASK 0x003F0000U
+#define LPDDR4__DENALI_PHY_1324__PHY_ADR_MASTER_DELAY_STEP_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1324__PHY_ADR_MASTER_DELAY_STEP_1_WIDTH 6U
+#define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_1__REG DENALI_PHY_1324
+#define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_1__FLD LPDDR4__DENALI_PHY_1324__PHY_ADR_MASTER_DELAY_STEP_1
+
+#define LPDDR4__DENALI_PHY_1324__PHY_ADR_MASTER_DELAY_WAIT_1_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_1324__PHY_ADR_MASTER_DELAY_WAIT_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1324__PHY_ADR_MASTER_DELAY_WAIT_1_WIDTH 8U
+#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_1__REG DENALI_PHY_1324
+#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_1__FLD LPDDR4__DENALI_PHY_1324__PHY_ADR_MASTER_DELAY_WAIT_1
+
+#define LPDDR4__DENALI_PHY_1325_READ_MASK 0x0103FFFFU
+#define LPDDR4__DENALI_PHY_1325_WRITE_MASK 0x0103FFFFU
+#define LPDDR4__DENALI_PHY_1325__PHY_ADR_MASTER_DELAY_HALF_MEASURE_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_1325__PHY_ADR_MASTER_DELAY_HALF_MEASURE_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1325__PHY_ADR_MASTER_DELAY_HALF_MEASURE_1_WIDTH 8U
+#define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_1__REG DENALI_PHY_1325
+#define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_1__FLD LPDDR4__DENALI_PHY_1325__PHY_ADR_MASTER_DELAY_HALF_MEASURE_1
+
+#define LPDDR4__DENALI_PHY_1325__PHY_ADR_SW_CALVL_DVW_MIN_1_MASK 0x0003FF00U
+#define LPDDR4__DENALI_PHY_1325__PHY_ADR_SW_CALVL_DVW_MIN_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1325__PHY_ADR_SW_CALVL_DVW_MIN_1_WIDTH 10U
+#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_1__REG DENALI_PHY_1325
+#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_1__FLD LPDDR4__DENALI_PHY_1325__PHY_ADR_SW_CALVL_DVW_MIN_1
+
+#define LPDDR4__DENALI_PHY_1325__PHY_ADR_SW_CALVL_DVW_MIN_EN_1_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_1325__PHY_ADR_SW_CALVL_DVW_MIN_EN_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1325__PHY_ADR_SW_CALVL_DVW_MIN_EN_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1325__PHY_ADR_SW_CALVL_DVW_MIN_EN_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1325__PHY_ADR_SW_CALVL_DVW_MIN_EN_1_WOSET 0U
+#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_1__REG DENALI_PHY_1325
+#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_1__FLD LPDDR4__DENALI_PHY_1325__PHY_ADR_SW_CALVL_DVW_MIN_EN_1
+
+#define LPDDR4__DENALI_PHY_1326_READ_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_1326_WRITE_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_1326__PHY_ADR_CALVL_DLY_STEP_1_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_1326__PHY_ADR_CALVL_DLY_STEP_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1326__PHY_ADR_CALVL_DLY_STEP_1_WIDTH 4U
+#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_1__REG DENALI_PHY_1326
+#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_1326__PHY_ADR_CALVL_DLY_STEP_1
+
+#define LPDDR4__DENALI_PHY_1327_READ_MASK 0x03FF010FU
+#define LPDDR4__DENALI_PHY_1327_WRITE_MASK 0x03FF010FU
+#define LPDDR4__DENALI_PHY_1327__PHY_ADR_CALVL_CAPTURE_CNT_1_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_1327__PHY_ADR_CALVL_CAPTURE_CNT_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1327__PHY_ADR_CALVL_CAPTURE_CNT_1_WIDTH 4U
+#define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_1__REG DENALI_PHY_1327
+#define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_1__FLD LPDDR4__DENALI_PHY_1327__PHY_ADR_CALVL_CAPTURE_CNT_1
+
+#define LPDDR4__DENALI_PHY_1327__PHY_ADR_MEAS_DLY_STEP_ENABLE_1_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_1327__PHY_ADR_MEAS_DLY_STEP_ENABLE_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1327__PHY_ADR_MEAS_DLY_STEP_ENABLE_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1327__PHY_ADR_MEAS_DLY_STEP_ENABLE_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1327__PHY_ADR_MEAS_DLY_STEP_ENABLE_1_WOSET 0U
+#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_1__REG DENALI_PHY_1327
+#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_1__FLD LPDDR4__DENALI_PHY_1327__PHY_ADR_MEAS_DLY_STEP_ENABLE_1
+
+#define LPDDR4__DENALI_PHY_1327__PHY_ADR_DC_INIT_SLV_DELAY_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_1327__PHY_ADR_DC_INIT_SLV_DELAY_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1327__PHY_ADR_DC_INIT_SLV_DELAY_1_WIDTH 10U
+#define LPDDR4__PHY_ADR_DC_INIT_SLV_DELAY_1__REG DENALI_PHY_1327
+#define LPDDR4__PHY_ADR_DC_INIT_SLV_DELAY_1__FLD LPDDR4__DENALI_PHY_1327__PHY_ADR_DC_INIT_SLV_DELAY_1
+
+#define LPDDR4__DENALI_PHY_1328_READ_MASK 0x0000FF01U
+#define LPDDR4__DENALI_PHY_1328_WRITE_MASK 0x0000FF01U
+#define LPDDR4__DENALI_PHY_1328__PHY_ADR_DC_CALVL_ENABLE_1_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1328__PHY_ADR_DC_CALVL_ENABLE_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1328__PHY_ADR_DC_CALVL_ENABLE_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1328__PHY_ADR_DC_CALVL_ENABLE_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1328__PHY_ADR_DC_CALVL_ENABLE_1_WOSET 0U
+#define LPDDR4__PHY_ADR_DC_CALVL_ENABLE_1__REG DENALI_PHY_1328
+#define LPDDR4__PHY_ADR_DC_CALVL_ENABLE_1__FLD LPDDR4__DENALI_PHY_1328__PHY_ADR_DC_CALVL_ENABLE_1
+
+#define LPDDR4__DENALI_PHY_1328__PHY_ADR_DC_DM_CLK_THRSHLD_1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_1328__PHY_ADR_DC_DM_CLK_THRSHLD_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1328__PHY_ADR_DC_DM_CLK_THRSHLD_1_WIDTH 8U
+#define LPDDR4__PHY_ADR_DC_DM_CLK_THRSHLD_1__REG DENALI_PHY_1328
+#define LPDDR4__PHY_ADR_DC_DM_CLK_THRSHLD_1__FLD LPDDR4__DENALI_PHY_1328__PHY_ADR_DC_DM_CLK_THRSHLD_1
+
+#endif /* REG_LPDDR4_ADDRESS_SLICE_1_MACROS_H_ */
diff --git a/drivers/ram/k3-ddrss/am62a/lpddr4_address_slice_2_macros.h b/drivers/ram/k3-ddrss/am62a/lpddr4_address_slice_2_macros.h
new file mode 100644
index 00000000000..abb7640de91
--- /dev/null
+++ b/drivers/ram/k3-ddrss/am62a/lpddr4_address_slice_2_macros.h
@@ -0,0 +1,778 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef REG_LPDDR4_ADDRESS_SLICE_2_MACROS_H_
+#define REG_LPDDR4_ADDRESS_SLICE_2_MACROS_H_
+
+#define LPDDR4__DENALI_PHY_1536_READ_MASK 0x000107FFU
+#define LPDDR4__DENALI_PHY_1536_WRITE_MASK 0x000107FFU
+#define LPDDR4__DENALI_PHY_1536__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_2_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1536__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1536__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_2_WIDTH 11U
+#define LPDDR4__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_2__REG DENALI_PHY_1536
+#define LPDDR4__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1536__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_1536__PHY_ADR_CLK_BYPASS_OVERRIDE_2_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_1536__PHY_ADR_CLK_BYPASS_OVERRIDE_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1536__PHY_ADR_CLK_BYPASS_OVERRIDE_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1536__PHY_ADR_CLK_BYPASS_OVERRIDE_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1536__PHY_ADR_CLK_BYPASS_OVERRIDE_2_WOSET 0U
+#define LPDDR4__PHY_ADR_CLK_BYPASS_OVERRIDE_2__REG DENALI_PHY_1536
+#define LPDDR4__PHY_ADR_CLK_BYPASS_OVERRIDE_2__FLD LPDDR4__DENALI_PHY_1536__PHY_ADR_CLK_BYPASS_OVERRIDE_2
+
+#define LPDDR4__DENALI_PHY_1536__SC_PHY_ADR_MANUAL_CLEAR_2_MASK 0x07000000U
+#define LPDDR4__DENALI_PHY_1536__SC_PHY_ADR_MANUAL_CLEAR_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1536__SC_PHY_ADR_MANUAL_CLEAR_2_WIDTH 3U
+#define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_2__REG DENALI_PHY_1536
+#define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_2__FLD LPDDR4__DENALI_PHY_1536__SC_PHY_ADR_MANUAL_CLEAR_2
+
+#define LPDDR4__DENALI_PHY_1537_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1537_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1537__PHY_ADR_LPBK_RESULT_OBS_2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1537__PHY_ADR_LPBK_RESULT_OBS_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1537__PHY_ADR_LPBK_RESULT_OBS_2_WIDTH 32U
+#define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_2__REG DENALI_PHY_1537
+#define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_2__FLD LPDDR4__DENALI_PHY_1537__PHY_ADR_LPBK_RESULT_OBS_2
+
+#define LPDDR4__DENALI_PHY_1538_READ_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1538_WRITE_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1538__PHY_ADR_LPBK_ERROR_COUNT_OBS_2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1538__PHY_ADR_LPBK_ERROR_COUNT_OBS_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1538__PHY_ADR_LPBK_ERROR_COUNT_OBS_2_WIDTH 16U
+#define LPDDR4__PHY_ADR_LPBK_ERROR_COUNT_OBS_2__REG DENALI_PHY_1538
+#define LPDDR4__PHY_ADR_LPBK_ERROR_COUNT_OBS_2__FLD LPDDR4__DENALI_PHY_1538__PHY_ADR_LPBK_ERROR_COUNT_OBS_2
+
+#define LPDDR4__DENALI_PHY_1538__PHY_ADR_MEAS_DLY_STEP_VALUE_2_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_1538__PHY_ADR_MEAS_DLY_STEP_VALUE_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1538__PHY_ADR_MEAS_DLY_STEP_VALUE_2_WIDTH 8U
+#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_VALUE_2__REG DENALI_PHY_1538
+#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_VALUE_2__FLD LPDDR4__DENALI_PHY_1538__PHY_ADR_MEAS_DLY_STEP_VALUE_2
+
+#define LPDDR4__DENALI_PHY_1538__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_2_MASK 0x0F000000U
+#define LPDDR4__DENALI_PHY_1538__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1538__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_2_WIDTH 4U
+#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_2__REG DENALI_PHY_1538
+#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_1538__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_2
+
+#define LPDDR4__DENALI_PHY_1539_READ_MASK 0xFF7F07FFU
+#define LPDDR4__DENALI_PHY_1539_WRITE_MASK 0xFF7F07FFU
+#define LPDDR4__DENALI_PHY_1539__PHY_ADR_MASTER_DLY_LOCK_OBS_2_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1539__PHY_ADR_MASTER_DLY_LOCK_OBS_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1539__PHY_ADR_MASTER_DLY_LOCK_OBS_2_WIDTH 11U
+#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_2__REG DENALI_PHY_1539
+#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_2__FLD LPDDR4__DENALI_PHY_1539__PHY_ADR_MASTER_DLY_LOCK_OBS_2
+
+#define LPDDR4__DENALI_PHY_1539__PHY_ADR_BASE_SLV_DLY_ENC_OBS_2_MASK 0x007F0000U
+#define LPDDR4__DENALI_PHY_1539__PHY_ADR_BASE_SLV_DLY_ENC_OBS_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1539__PHY_ADR_BASE_SLV_DLY_ENC_OBS_2_WIDTH 7U
+#define LPDDR4__PHY_ADR_BASE_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_1539
+#define LPDDR4__PHY_ADR_BASE_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_1539__PHY_ADR_BASE_SLV_DLY_ENC_OBS_2
+
+#define LPDDR4__DENALI_PHY_1539__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_2_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_1539__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1539__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_2_WIDTH 8U
+#define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_1539
+#define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_1539__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_2
+
+#define LPDDR4__DENALI_PHY_1540_READ_MASK 0x01000707U
+#define LPDDR4__DENALI_PHY_1540_WRITE_MASK 0x01000707U
+#define LPDDR4__DENALI_PHY_1540__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_2_MASK 0x00000007U
+#define LPDDR4__DENALI_PHY_1540__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1540__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_2_WIDTH 3U
+#define LPDDR4__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_2__REG DENALI_PHY_1540
+#define LPDDR4__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_2__FLD LPDDR4__DENALI_PHY_1540__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_2
+
+#define LPDDR4__DENALI_PHY_1540__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_2_MASK 0x00000700U
+#define LPDDR4__DENALI_PHY_1540__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1540__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_2_WIDTH 3U
+#define LPDDR4__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_2__REG DENALI_PHY_1540
+#define LPDDR4__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_1540__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_2
+
+#define LPDDR4__DENALI_PHY_1540__SC_PHY_ADR_SNAP_OBS_REGS_2_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_1540__SC_PHY_ADR_SNAP_OBS_REGS_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1540__SC_PHY_ADR_SNAP_OBS_REGS_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1540__SC_PHY_ADR_SNAP_OBS_REGS_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1540__SC_PHY_ADR_SNAP_OBS_REGS_2_WOSET 0U
+#define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_2__REG DENALI_PHY_1540
+#define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_2__FLD LPDDR4__DENALI_PHY_1540__SC_PHY_ADR_SNAP_OBS_REGS_2
+
+#define LPDDR4__DENALI_PHY_1540__PHY_ADR_TSEL_ENABLE_2_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_1540__PHY_ADR_TSEL_ENABLE_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1540__PHY_ADR_TSEL_ENABLE_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1540__PHY_ADR_TSEL_ENABLE_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1540__PHY_ADR_TSEL_ENABLE_2_WOSET 0U
+#define LPDDR4__PHY_ADR_TSEL_ENABLE_2__REG DENALI_PHY_1540
+#define LPDDR4__PHY_ADR_TSEL_ENABLE_2__FLD LPDDR4__DENALI_PHY_1540__PHY_ADR_TSEL_ENABLE_2
+
+#define LPDDR4__DENALI_PHY_1541_READ_MASK 0x011F7F7FU
+#define LPDDR4__DENALI_PHY_1541_WRITE_MASK 0x011F7F7FU
+#define LPDDR4__DENALI_PHY_1541__PHY_ADR_LPBK_CONTROL_2_MASK 0x0000007FU
+#define LPDDR4__DENALI_PHY_1541__PHY_ADR_LPBK_CONTROL_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1541__PHY_ADR_LPBK_CONTROL_2_WIDTH 7U
+#define LPDDR4__PHY_ADR_LPBK_CONTROL_2__REG DENALI_PHY_1541
+#define LPDDR4__PHY_ADR_LPBK_CONTROL_2__FLD LPDDR4__DENALI_PHY_1541__PHY_ADR_LPBK_CONTROL_2
+
+#define LPDDR4__DENALI_PHY_1541__PHY_ADR_PRBS_PATTERN_START_2_MASK 0x00007F00U
+#define LPDDR4__DENALI_PHY_1541__PHY_ADR_PRBS_PATTERN_START_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1541__PHY_ADR_PRBS_PATTERN_START_2_WIDTH 7U
+#define LPDDR4__PHY_ADR_PRBS_PATTERN_START_2__REG DENALI_PHY_1541
+#define LPDDR4__PHY_ADR_PRBS_PATTERN_START_2__FLD LPDDR4__DENALI_PHY_1541__PHY_ADR_PRBS_PATTERN_START_2
+
+#define LPDDR4__DENALI_PHY_1541__PHY_ADR_PRBS_PATTERN_MASK_2_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_1541__PHY_ADR_PRBS_PATTERN_MASK_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1541__PHY_ADR_PRBS_PATTERN_MASK_2_WIDTH 5U
+#define LPDDR4__PHY_ADR_PRBS_PATTERN_MASK_2__REG DENALI_PHY_1541
+#define LPDDR4__PHY_ADR_PRBS_PATTERN_MASK_2__FLD LPDDR4__DENALI_PHY_1541__PHY_ADR_PRBS_PATTERN_MASK_2
+
+#define LPDDR4__DENALI_PHY_1541__PHY_ADR_PWR_RDC_DISABLE_2_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_1541__PHY_ADR_PWR_RDC_DISABLE_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1541__PHY_ADR_PWR_RDC_DISABLE_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1541__PHY_ADR_PWR_RDC_DISABLE_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1541__PHY_ADR_PWR_RDC_DISABLE_2_WOSET 0U
+#define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_2__REG DENALI_PHY_1541
+#define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_2__FLD LPDDR4__DENALI_PHY_1541__PHY_ADR_PWR_RDC_DISABLE_2
+
+#define LPDDR4__DENALI_PHY_1542_READ_MASK 0x01070301U
+#define LPDDR4__DENALI_PHY_1542_WRITE_MASK 0x01070301U
+#define LPDDR4__DENALI_PHY_1542__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1542__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1542__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1542__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1542__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2_WOSET 0U
+#define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2__REG DENALI_PHY_1542
+#define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2__FLD LPDDR4__DENALI_PHY_1542__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2
+
+#define LPDDR4__DENALI_PHY_1542__PHY_ADR_TYPE_2_MASK 0x00000300U
+#define LPDDR4__DENALI_PHY_1542__PHY_ADR_TYPE_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1542__PHY_ADR_TYPE_2_WIDTH 2U
+#define LPDDR4__PHY_ADR_TYPE_2__REG DENALI_PHY_1542
+#define LPDDR4__PHY_ADR_TYPE_2__FLD LPDDR4__DENALI_PHY_1542__PHY_ADR_TYPE_2
+
+#define LPDDR4__DENALI_PHY_1542__PHY_ADR_WRADDR_SHIFT_OBS_2_MASK 0x00070000U
+#define LPDDR4__DENALI_PHY_1542__PHY_ADR_WRADDR_SHIFT_OBS_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1542__PHY_ADR_WRADDR_SHIFT_OBS_2_WIDTH 3U
+#define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_2__REG DENALI_PHY_1542
+#define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_2__FLD LPDDR4__DENALI_PHY_1542__PHY_ADR_WRADDR_SHIFT_OBS_2
+
+#define LPDDR4__DENALI_PHY_1542__PHY_ADR_IE_MODE_2_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_1542__PHY_ADR_IE_MODE_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1542__PHY_ADR_IE_MODE_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1542__PHY_ADR_IE_MODE_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1542__PHY_ADR_IE_MODE_2_WOSET 0U
+#define LPDDR4__PHY_ADR_IE_MODE_2__REG DENALI_PHY_1542
+#define LPDDR4__PHY_ADR_IE_MODE_2__FLD LPDDR4__DENALI_PHY_1542__PHY_ADR_IE_MODE_2
+
+#define LPDDR4__DENALI_PHY_1543_READ_MASK 0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_1543_WRITE_MASK 0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_1543__PHY_ADR_DDL_MODE_2_MASK 0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_1543__PHY_ADR_DDL_MODE_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1543__PHY_ADR_DDL_MODE_2_WIDTH 27U
+#define LPDDR4__PHY_ADR_DDL_MODE_2__REG DENALI_PHY_1543
+#define LPDDR4__PHY_ADR_DDL_MODE_2__FLD LPDDR4__DENALI_PHY_1543__PHY_ADR_DDL_MODE_2
+
+#define LPDDR4__DENALI_PHY_1544_READ_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_1544_WRITE_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_1544__PHY_ADR_DDL_MASK_2_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_1544__PHY_ADR_DDL_MASK_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1544__PHY_ADR_DDL_MASK_2_WIDTH 6U
+#define LPDDR4__PHY_ADR_DDL_MASK_2__REG DENALI_PHY_1544
+#define LPDDR4__PHY_ADR_DDL_MASK_2__FLD LPDDR4__DENALI_PHY_1544__PHY_ADR_DDL_MASK_2
+
+#define LPDDR4__DENALI_PHY_1545_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1545_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1545__PHY_ADR_DDL_TEST_OBS_2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1545__PHY_ADR_DDL_TEST_OBS_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1545__PHY_ADR_DDL_TEST_OBS_2_WIDTH 32U
+#define LPDDR4__PHY_ADR_DDL_TEST_OBS_2__REG DENALI_PHY_1545
+#define LPDDR4__PHY_ADR_DDL_TEST_OBS_2__FLD LPDDR4__DENALI_PHY_1545__PHY_ADR_DDL_TEST_OBS_2
+
+#define LPDDR4__DENALI_PHY_1546_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1546_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1546__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1546__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1546__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_2_WIDTH 32U
+#define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_2__REG DENALI_PHY_1546
+#define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_2__FLD LPDDR4__DENALI_PHY_1546__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_2
+
+#define LPDDR4__DENALI_PHY_1547_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1547_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1547__PHY_ADR_CALVL_START_2_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1547__PHY_ADR_CALVL_START_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1547__PHY_ADR_CALVL_START_2_WIDTH 11U
+#define LPDDR4__PHY_ADR_CALVL_START_2__REG DENALI_PHY_1547
+#define LPDDR4__PHY_ADR_CALVL_START_2__FLD LPDDR4__DENALI_PHY_1547__PHY_ADR_CALVL_START_2
+
+#define LPDDR4__DENALI_PHY_1547__PHY_ADR_CALVL_COARSE_DLY_2_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_1547__PHY_ADR_CALVL_COARSE_DLY_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1547__PHY_ADR_CALVL_COARSE_DLY_2_WIDTH 11U
+#define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_2__REG DENALI_PHY_1547
+#define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_2__FLD LPDDR4__DENALI_PHY_1547__PHY_ADR_CALVL_COARSE_DLY_2
+
+#define LPDDR4__DENALI_PHY_1548_READ_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1548_WRITE_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1548__PHY_ADR_CALVL_QTR_2_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1548__PHY_ADR_CALVL_QTR_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1548__PHY_ADR_CALVL_QTR_2_WIDTH 11U
+#define LPDDR4__PHY_ADR_CALVL_QTR_2__REG DENALI_PHY_1548
+#define LPDDR4__PHY_ADR_CALVL_QTR_2__FLD LPDDR4__DENALI_PHY_1548__PHY_ADR_CALVL_QTR_2
+
+#define LPDDR4__DENALI_PHY_1549_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1549_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1549__PHY_ADR_CALVL_SWIZZLE0_2_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1549__PHY_ADR_CALVL_SWIZZLE0_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1549__PHY_ADR_CALVL_SWIZZLE0_2_WIDTH 24U
+#define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_2__REG DENALI_PHY_1549
+#define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_2__FLD LPDDR4__DENALI_PHY_1549__PHY_ADR_CALVL_SWIZZLE0_2
+
+#define LPDDR4__DENALI_PHY_1550_READ_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_1550_WRITE_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_1550__PHY_ADR_CALVL_SWIZZLE1_2_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1550__PHY_ADR_CALVL_SWIZZLE1_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1550__PHY_ADR_CALVL_SWIZZLE1_2_WIDTH 24U
+#define LPDDR4__PHY_ADR_CALVL_SWIZZLE1_2__REG DENALI_PHY_1550
+#define LPDDR4__PHY_ADR_CALVL_SWIZZLE1_2__FLD LPDDR4__DENALI_PHY_1550__PHY_ADR_CALVL_SWIZZLE1_2
+
+#define LPDDR4__DENALI_PHY_1550__PHY_ADR_CALVL_RANK_CTRL_2_MASK 0x03000000U
+#define LPDDR4__DENALI_PHY_1550__PHY_ADR_CALVL_RANK_CTRL_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1550__PHY_ADR_CALVL_RANK_CTRL_2_WIDTH 2U
+#define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_2__REG DENALI_PHY_1550
+#define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_2__FLD LPDDR4__DENALI_PHY_1550__PHY_ADR_CALVL_RANK_CTRL_2
+
+#define LPDDR4__DENALI_PHY_1551_READ_MASK 0x01FF0F03U
+#define LPDDR4__DENALI_PHY_1551_WRITE_MASK 0x01FF0F03U
+#define LPDDR4__DENALI_PHY_1551__PHY_ADR_CALVL_NUM_PATTERNS_2_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_1551__PHY_ADR_CALVL_NUM_PATTERNS_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1551__PHY_ADR_CALVL_NUM_PATTERNS_2_WIDTH 2U
+#define LPDDR4__PHY_ADR_CALVL_NUM_PATTERNS_2__REG DENALI_PHY_1551
+#define LPDDR4__PHY_ADR_CALVL_NUM_PATTERNS_2__FLD LPDDR4__DENALI_PHY_1551__PHY_ADR_CALVL_NUM_PATTERNS_2
+
+#define LPDDR4__DENALI_PHY_1551__PHY_ADR_CALVL_RESP_WAIT_CNT_2_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_1551__PHY_ADR_CALVL_RESP_WAIT_CNT_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1551__PHY_ADR_CALVL_RESP_WAIT_CNT_2_WIDTH 4U
+#define LPDDR4__PHY_ADR_CALVL_RESP_WAIT_CNT_2__REG DENALI_PHY_1551
+#define LPDDR4__PHY_ADR_CALVL_RESP_WAIT_CNT_2__FLD LPDDR4__DENALI_PHY_1551__PHY_ADR_CALVL_RESP_WAIT_CNT_2
+
+#define LPDDR4__DENALI_PHY_1551__PHY_ADR_CALVL_PERIODIC_START_OFFSET_2_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_1551__PHY_ADR_CALVL_PERIODIC_START_OFFSET_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1551__PHY_ADR_CALVL_PERIODIC_START_OFFSET_2_WIDTH 9U
+#define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_2__REG DENALI_PHY_1551
+#define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_2__FLD LPDDR4__DENALI_PHY_1551__PHY_ADR_CALVL_PERIODIC_START_OFFSET_2
+
+#define LPDDR4__DENALI_PHY_1552_READ_MASK 0x07000001U
+#define LPDDR4__DENALI_PHY_1552_WRITE_MASK 0x07000001U
+#define LPDDR4__DENALI_PHY_1552__PHY_ADR_CALVL_DEBUG_MODE_2_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1552__PHY_ADR_CALVL_DEBUG_MODE_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1552__PHY_ADR_CALVL_DEBUG_MODE_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1552__PHY_ADR_CALVL_DEBUG_MODE_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1552__PHY_ADR_CALVL_DEBUG_MODE_2_WOSET 0U
+#define LPDDR4__PHY_ADR_CALVL_DEBUG_MODE_2__REG DENALI_PHY_1552
+#define LPDDR4__PHY_ADR_CALVL_DEBUG_MODE_2__FLD LPDDR4__DENALI_PHY_1552__PHY_ADR_CALVL_DEBUG_MODE_2
+
+#define LPDDR4__DENALI_PHY_1552__SC_PHY_ADR_CALVL_DEBUG_CONT_2_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_1552__SC_PHY_ADR_CALVL_DEBUG_CONT_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1552__SC_PHY_ADR_CALVL_DEBUG_CONT_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1552__SC_PHY_ADR_CALVL_DEBUG_CONT_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1552__SC_PHY_ADR_CALVL_DEBUG_CONT_2_WOSET 0U
+#define LPDDR4__SC_PHY_ADR_CALVL_DEBUG_CONT_2__REG DENALI_PHY_1552
+#define LPDDR4__SC_PHY_ADR_CALVL_DEBUG_CONT_2__FLD LPDDR4__DENALI_PHY_1552__SC_PHY_ADR_CALVL_DEBUG_CONT_2
+
+#define LPDDR4__DENALI_PHY_1552__SC_PHY_ADR_CALVL_ERROR_CLR_2_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_1552__SC_PHY_ADR_CALVL_ERROR_CLR_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1552__SC_PHY_ADR_CALVL_ERROR_CLR_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1552__SC_PHY_ADR_CALVL_ERROR_CLR_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1552__SC_PHY_ADR_CALVL_ERROR_CLR_2_WOSET 0U
+#define LPDDR4__SC_PHY_ADR_CALVL_ERROR_CLR_2__REG DENALI_PHY_1552
+#define LPDDR4__SC_PHY_ADR_CALVL_ERROR_CLR_2__FLD LPDDR4__DENALI_PHY_1552__SC_PHY_ADR_CALVL_ERROR_CLR_2
+
+#define LPDDR4__DENALI_PHY_1552__PHY_ADR_CALVL_OBS_SELECT_2_MASK 0x07000000U
+#define LPDDR4__DENALI_PHY_1552__PHY_ADR_CALVL_OBS_SELECT_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1552__PHY_ADR_CALVL_OBS_SELECT_2_WIDTH 3U
+#define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_2__REG DENALI_PHY_1552
+#define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_1552__PHY_ADR_CALVL_OBS_SELECT_2
+
+#define LPDDR4__DENALI_PHY_1553_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1553_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1553__PHY_ADR_CALVL_CH0_OBS0_2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1553__PHY_ADR_CALVL_CH0_OBS0_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1553__PHY_ADR_CALVL_CH0_OBS0_2_WIDTH 32U
+#define LPDDR4__PHY_ADR_CALVL_CH0_OBS0_2__REG DENALI_PHY_1553
+#define LPDDR4__PHY_ADR_CALVL_CH0_OBS0_2__FLD LPDDR4__DENALI_PHY_1553__PHY_ADR_CALVL_CH0_OBS0_2
+
+#define LPDDR4__DENALI_PHY_1554_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1554_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1554__PHY_ADR_CALVL_CH1_OBS0_2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1554__PHY_ADR_CALVL_CH1_OBS0_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1554__PHY_ADR_CALVL_CH1_OBS0_2_WIDTH 32U
+#define LPDDR4__PHY_ADR_CALVL_CH1_OBS0_2__REG DENALI_PHY_1554
+#define LPDDR4__PHY_ADR_CALVL_CH1_OBS0_2__FLD LPDDR4__DENALI_PHY_1554__PHY_ADR_CALVL_CH1_OBS0_2
+
+#define LPDDR4__DENALI_PHY_1555_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1555_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1555__PHY_ADR_CALVL_OBS1_2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1555__PHY_ADR_CALVL_OBS1_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1555__PHY_ADR_CALVL_OBS1_2_WIDTH 32U
+#define LPDDR4__PHY_ADR_CALVL_OBS1_2__REG DENALI_PHY_1555
+#define LPDDR4__PHY_ADR_CALVL_OBS1_2__FLD LPDDR4__DENALI_PHY_1555__PHY_ADR_CALVL_OBS1_2
+
+#define LPDDR4__DENALI_PHY_1556_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1556_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1556__PHY_ADR_CALVL_OBS2_2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1556__PHY_ADR_CALVL_OBS2_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1556__PHY_ADR_CALVL_OBS2_2_WIDTH 32U
+#define LPDDR4__PHY_ADR_CALVL_OBS2_2__REG DENALI_PHY_1556
+#define LPDDR4__PHY_ADR_CALVL_OBS2_2__FLD LPDDR4__DENALI_PHY_1556__PHY_ADR_CALVL_OBS2_2
+
+#define LPDDR4__DENALI_PHY_1557_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1557_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1557__PHY_ADR_CALVL_FG_0_2_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1557__PHY_ADR_CALVL_FG_0_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1557__PHY_ADR_CALVL_FG_0_2_WIDTH 20U
+#define LPDDR4__PHY_ADR_CALVL_FG_0_2__REG DENALI_PHY_1557
+#define LPDDR4__PHY_ADR_CALVL_FG_0_2__FLD LPDDR4__DENALI_PHY_1557__PHY_ADR_CALVL_FG_0_2
+
+#define LPDDR4__DENALI_PHY_1558_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1558_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1558__PHY_ADR_CALVL_BG_0_2_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1558__PHY_ADR_CALVL_BG_0_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1558__PHY_ADR_CALVL_BG_0_2_WIDTH 20U
+#define LPDDR4__PHY_ADR_CALVL_BG_0_2__REG DENALI_PHY_1558
+#define LPDDR4__PHY_ADR_CALVL_BG_0_2__FLD LPDDR4__DENALI_PHY_1558__PHY_ADR_CALVL_BG_0_2
+
+#define LPDDR4__DENALI_PHY_1559_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1559_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1559__PHY_ADR_CALVL_FG_1_2_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1559__PHY_ADR_CALVL_FG_1_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1559__PHY_ADR_CALVL_FG_1_2_WIDTH 20U
+#define LPDDR4__PHY_ADR_CALVL_FG_1_2__REG DENALI_PHY_1559
+#define LPDDR4__PHY_ADR_CALVL_FG_1_2__FLD LPDDR4__DENALI_PHY_1559__PHY_ADR_CALVL_FG_1_2
+
+#define LPDDR4__DENALI_PHY_1560_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1560_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1560__PHY_ADR_CALVL_BG_1_2_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1560__PHY_ADR_CALVL_BG_1_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1560__PHY_ADR_CALVL_BG_1_2_WIDTH 20U
+#define LPDDR4__PHY_ADR_CALVL_BG_1_2__REG DENALI_PHY_1560
+#define LPDDR4__PHY_ADR_CALVL_BG_1_2__FLD LPDDR4__DENALI_PHY_1560__PHY_ADR_CALVL_BG_1_2
+
+#define LPDDR4__DENALI_PHY_1561_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1561_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1561__PHY_ADR_CALVL_FG_2_2_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1561__PHY_ADR_CALVL_FG_2_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1561__PHY_ADR_CALVL_FG_2_2_WIDTH 20U
+#define LPDDR4__PHY_ADR_CALVL_FG_2_2__REG DENALI_PHY_1561
+#define LPDDR4__PHY_ADR_CALVL_FG_2_2__FLD LPDDR4__DENALI_PHY_1561__PHY_ADR_CALVL_FG_2_2
+
+#define LPDDR4__DENALI_PHY_1562_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1562_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1562__PHY_ADR_CALVL_BG_2_2_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1562__PHY_ADR_CALVL_BG_2_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1562__PHY_ADR_CALVL_BG_2_2_WIDTH 20U
+#define LPDDR4__PHY_ADR_CALVL_BG_2_2__REG DENALI_PHY_1562
+#define LPDDR4__PHY_ADR_CALVL_BG_2_2__FLD LPDDR4__DENALI_PHY_1562__PHY_ADR_CALVL_BG_2_2
+
+#define LPDDR4__DENALI_PHY_1563_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1563_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1563__PHY_ADR_CALVL_FG_3_2_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1563__PHY_ADR_CALVL_FG_3_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1563__PHY_ADR_CALVL_FG_3_2_WIDTH 20U
+#define LPDDR4__PHY_ADR_CALVL_FG_3_2__REG DENALI_PHY_1563
+#define LPDDR4__PHY_ADR_CALVL_FG_3_2__FLD LPDDR4__DENALI_PHY_1563__PHY_ADR_CALVL_FG_3_2
+
+#define LPDDR4__DENALI_PHY_1564_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1564_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1564__PHY_ADR_CALVL_BG_3_2_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1564__PHY_ADR_CALVL_BG_3_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1564__PHY_ADR_CALVL_BG_3_2_WIDTH 20U
+#define LPDDR4__PHY_ADR_CALVL_BG_3_2__REG DENALI_PHY_1564
+#define LPDDR4__PHY_ADR_CALVL_BG_3_2__FLD LPDDR4__DENALI_PHY_1564__PHY_ADR_CALVL_BG_3_2
+
+#define LPDDR4__DENALI_PHY_1565_READ_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1565_WRITE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1565__PHY_ADR_ADDR_SEL_2_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1565__PHY_ADR_ADDR_SEL_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1565__PHY_ADR_ADDR_SEL_2_WIDTH 30U
+#define LPDDR4__PHY_ADR_ADDR_SEL_2__REG DENALI_PHY_1565
+#define LPDDR4__PHY_ADR_ADDR_SEL_2__FLD LPDDR4__DENALI_PHY_1565__PHY_ADR_ADDR_SEL_2
+
+#define LPDDR4__DENALI_PHY_1566_READ_MASK 0x3F3F03FFU
+#define LPDDR4__DENALI_PHY_1566_WRITE_MASK 0x3F3F03FFU
+#define LPDDR4__DENALI_PHY_1566__PHY_ADR_LP4_BOOT_SLV_DELAY_2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_1566__PHY_ADR_LP4_BOOT_SLV_DELAY_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1566__PHY_ADR_LP4_BOOT_SLV_DELAY_2_WIDTH 10U
+#define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_2__REG DENALI_PHY_1566
+#define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_2__FLD LPDDR4__DENALI_PHY_1566__PHY_ADR_LP4_BOOT_SLV_DELAY_2
+
+#define LPDDR4__DENALI_PHY_1566__PHY_ADR_BIT_MASK_2_MASK 0x003F0000U
+#define LPDDR4__DENALI_PHY_1566__PHY_ADR_BIT_MASK_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1566__PHY_ADR_BIT_MASK_2_WIDTH 6U
+#define LPDDR4__PHY_ADR_BIT_MASK_2__REG DENALI_PHY_1566
+#define LPDDR4__PHY_ADR_BIT_MASK_2__FLD LPDDR4__DENALI_PHY_1566__PHY_ADR_BIT_MASK_2
+
+#define LPDDR4__DENALI_PHY_1566__PHY_ADR_SEG_MASK_2_MASK 0x3F000000U
+#define LPDDR4__DENALI_PHY_1566__PHY_ADR_SEG_MASK_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1566__PHY_ADR_SEG_MASK_2_WIDTH 6U
+#define LPDDR4__PHY_ADR_SEG_MASK_2__REG DENALI_PHY_1566
+#define LPDDR4__PHY_ADR_SEG_MASK_2__FLD LPDDR4__DENALI_PHY_1566__PHY_ADR_SEG_MASK_2
+
+#define LPDDR4__DENALI_PHY_1567_READ_MASK 0x3F0F3F3FU
+#define LPDDR4__DENALI_PHY_1567_WRITE_MASK 0x3F0F3F3FU
+#define LPDDR4__DENALI_PHY_1567__PHY_ADR_CALVL_TRAIN_MASK_2_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_1567__PHY_ADR_CALVL_TRAIN_MASK_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1567__PHY_ADR_CALVL_TRAIN_MASK_2_WIDTH 6U
+#define LPDDR4__PHY_ADR_CALVL_TRAIN_MASK_2__REG DENALI_PHY_1567
+#define LPDDR4__PHY_ADR_CALVL_TRAIN_MASK_2__FLD LPDDR4__DENALI_PHY_1567__PHY_ADR_CALVL_TRAIN_MASK_2
+
+#define LPDDR4__DENALI_PHY_1567__PHY_ADR_CSLVL_TRAIN_MASK_2_MASK 0x00003F00U
+#define LPDDR4__DENALI_PHY_1567__PHY_ADR_CSLVL_TRAIN_MASK_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1567__PHY_ADR_CSLVL_TRAIN_MASK_2_WIDTH 6U
+#define LPDDR4__PHY_ADR_CSLVL_TRAIN_MASK_2__REG DENALI_PHY_1567
+#define LPDDR4__PHY_ADR_CSLVL_TRAIN_MASK_2__FLD LPDDR4__DENALI_PHY_1567__PHY_ADR_CSLVL_TRAIN_MASK_2
+
+#define LPDDR4__DENALI_PHY_1567__PHY_ADR_STATIC_TOG_DISABLE_2_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_1567__PHY_ADR_STATIC_TOG_DISABLE_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1567__PHY_ADR_STATIC_TOG_DISABLE_2_WIDTH 4U
+#define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_2__REG DENALI_PHY_1567
+#define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_2__FLD LPDDR4__DENALI_PHY_1567__PHY_ADR_STATIC_TOG_DISABLE_2
+
+#define LPDDR4__DENALI_PHY_1567__PHY_ADR_SW_TXIO_CTRL_2_MASK 0x3F000000U
+#define LPDDR4__DENALI_PHY_1567__PHY_ADR_SW_TXIO_CTRL_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1567__PHY_ADR_SW_TXIO_CTRL_2_WIDTH 6U
+#define LPDDR4__PHY_ADR_SW_TXIO_CTRL_2__REG DENALI_PHY_1567
+#define LPDDR4__PHY_ADR_SW_TXIO_CTRL_2__FLD LPDDR4__DENALI_PHY_1567__PHY_ADR_SW_TXIO_CTRL_2
+
+#define LPDDR4__DENALI_PHY_1568_READ_MASK 0xFFFFFF03U
+#define LPDDR4__DENALI_PHY_1568_WRITE_MASK 0xFFFFFF03U
+#define LPDDR4__DENALI_PHY_1568__PHY_ADR_DC_INIT_DISABLE_2_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_1568__PHY_ADR_DC_INIT_DISABLE_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1568__PHY_ADR_DC_INIT_DISABLE_2_WIDTH 2U
+#define LPDDR4__PHY_ADR_DC_INIT_DISABLE_2__REG DENALI_PHY_1568
+#define LPDDR4__PHY_ADR_DC_INIT_DISABLE_2__FLD LPDDR4__DENALI_PHY_1568__PHY_ADR_DC_INIT_DISABLE_2
+
+#define LPDDR4__DENALI_PHY_1568__PHY_ADR_DC_ADR0_CLK_ADJUST_2_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_1568__PHY_ADR_DC_ADR0_CLK_ADJUST_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1568__PHY_ADR_DC_ADR0_CLK_ADJUST_2_WIDTH 8U
+#define LPDDR4__PHY_ADR_DC_ADR0_CLK_ADJUST_2__REG DENALI_PHY_1568
+#define LPDDR4__PHY_ADR_DC_ADR0_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_1568__PHY_ADR_DC_ADR0_CLK_ADJUST_2
+
+#define LPDDR4__DENALI_PHY_1568__PHY_ADR_DC_ADR1_CLK_ADJUST_2_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_1568__PHY_ADR_DC_ADR1_CLK_ADJUST_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1568__PHY_ADR_DC_ADR1_CLK_ADJUST_2_WIDTH 8U
+#define LPDDR4__PHY_ADR_DC_ADR1_CLK_ADJUST_2__REG DENALI_PHY_1568
+#define LPDDR4__PHY_ADR_DC_ADR1_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_1568__PHY_ADR_DC_ADR1_CLK_ADJUST_2
+
+#define LPDDR4__DENALI_PHY_1568__PHY_ADR_DC_ADR2_CLK_ADJUST_2_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_1568__PHY_ADR_DC_ADR2_CLK_ADJUST_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1568__PHY_ADR_DC_ADR2_CLK_ADJUST_2_WIDTH 8U
+#define LPDDR4__PHY_ADR_DC_ADR2_CLK_ADJUST_2__REG DENALI_PHY_1568
+#define LPDDR4__PHY_ADR_DC_ADR2_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_1568__PHY_ADR_DC_ADR2_CLK_ADJUST_2
+
+#define LPDDR4__DENALI_PHY_1569_READ_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_PHY_1569_WRITE_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_PHY_1569__PHY_ADR_DC_ADR3_CLK_ADJUST_2_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_1569__PHY_ADR_DC_ADR3_CLK_ADJUST_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1569__PHY_ADR_DC_ADR3_CLK_ADJUST_2_WIDTH 8U
+#define LPDDR4__PHY_ADR_DC_ADR3_CLK_ADJUST_2__REG DENALI_PHY_1569
+#define LPDDR4__PHY_ADR_DC_ADR3_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_1569__PHY_ADR_DC_ADR3_CLK_ADJUST_2
+
+#define LPDDR4__DENALI_PHY_1569__PHY_ADR_DC_ADR4_CLK_ADJUST_2_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_1569__PHY_ADR_DC_ADR4_CLK_ADJUST_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1569__PHY_ADR_DC_ADR4_CLK_ADJUST_2_WIDTH 8U
+#define LPDDR4__PHY_ADR_DC_ADR4_CLK_ADJUST_2__REG DENALI_PHY_1569
+#define LPDDR4__PHY_ADR_DC_ADR4_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_1569__PHY_ADR_DC_ADR4_CLK_ADJUST_2
+
+#define LPDDR4__DENALI_PHY_1569__PHY_ADR_DC_ADR5_CLK_ADJUST_2_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_1569__PHY_ADR_DC_ADR5_CLK_ADJUST_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1569__PHY_ADR_DC_ADR5_CLK_ADJUST_2_WIDTH 8U
+#define LPDDR4__PHY_ADR_DC_ADR5_CLK_ADJUST_2__REG DENALI_PHY_1569
+#define LPDDR4__PHY_ADR_DC_ADR5_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_1569__PHY_ADR_DC_ADR5_CLK_ADJUST_2
+
+#define LPDDR4__DENALI_PHY_1569__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_2_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_1569__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1569__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1569__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1569__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_2_WOSET 0U
+#define LPDDR4__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_2__REG DENALI_PHY_1569
+#define LPDDR4__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_2__FLD LPDDR4__DENALI_PHY_1569__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_2
+
+#define LPDDR4__DENALI_PHY_1570_READ_MASK 0x3F03FFFFU
+#define LPDDR4__DENALI_PHY_1570_WRITE_MASK 0x3F03FFFFU
+#define LPDDR4__DENALI_PHY_1570__PHY_ADR_DC_CAL_SAMPLE_WAIT_2_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_1570__PHY_ADR_DC_CAL_SAMPLE_WAIT_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1570__PHY_ADR_DC_CAL_SAMPLE_WAIT_2_WIDTH 8U
+#define LPDDR4__PHY_ADR_DC_CAL_SAMPLE_WAIT_2__REG DENALI_PHY_1570
+#define LPDDR4__PHY_ADR_DC_CAL_SAMPLE_WAIT_2__FLD LPDDR4__DENALI_PHY_1570__PHY_ADR_DC_CAL_SAMPLE_WAIT_2
+
+#define LPDDR4__DENALI_PHY_1570__PHY_ADR_DC_CAL_TIMEOUT_2_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_1570__PHY_ADR_DC_CAL_TIMEOUT_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1570__PHY_ADR_DC_CAL_TIMEOUT_2_WIDTH 8U
+#define LPDDR4__PHY_ADR_DC_CAL_TIMEOUT_2__REG DENALI_PHY_1570
+#define LPDDR4__PHY_ADR_DC_CAL_TIMEOUT_2__FLD LPDDR4__DENALI_PHY_1570__PHY_ADR_DC_CAL_TIMEOUT_2
+
+#define LPDDR4__DENALI_PHY_1570__PHY_ADR_DC_WEIGHT_2_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_1570__PHY_ADR_DC_WEIGHT_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1570__PHY_ADR_DC_WEIGHT_2_WIDTH 2U
+#define LPDDR4__PHY_ADR_DC_WEIGHT_2__REG DENALI_PHY_1570
+#define LPDDR4__PHY_ADR_DC_WEIGHT_2__FLD LPDDR4__DENALI_PHY_1570__PHY_ADR_DC_WEIGHT_2
+
+#define LPDDR4__DENALI_PHY_1570__PHY_ADR_DC_ADJUST_START_2_MASK 0x3F000000U
+#define LPDDR4__DENALI_PHY_1570__PHY_ADR_DC_ADJUST_START_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1570__PHY_ADR_DC_ADJUST_START_2_WIDTH 6U
+#define LPDDR4__PHY_ADR_DC_ADJUST_START_2__REG DENALI_PHY_1570
+#define LPDDR4__PHY_ADR_DC_ADJUST_START_2__FLD LPDDR4__DENALI_PHY_1570__PHY_ADR_DC_ADJUST_START_2
+
+#define LPDDR4__DENALI_PHY_1571_READ_MASK 0x0101FFFFU
+#define LPDDR4__DENALI_PHY_1571_WRITE_MASK 0x0101FFFFU
+#define LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_ADJUST_SAMPLE_CNT_2_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_ADJUST_SAMPLE_CNT_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_ADJUST_SAMPLE_CNT_2_WIDTH 8U
+#define LPDDR4__PHY_ADR_DC_ADJUST_SAMPLE_CNT_2__REG DENALI_PHY_1571
+#define LPDDR4__PHY_ADR_DC_ADJUST_SAMPLE_CNT_2__FLD LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_ADJUST_SAMPLE_CNT_2
+
+#define LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_ADJUST_THRSHLD_2_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_ADJUST_THRSHLD_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_ADJUST_THRSHLD_2_WIDTH 8U
+#define LPDDR4__PHY_ADR_DC_ADJUST_THRSHLD_2__REG DENALI_PHY_1571
+#define LPDDR4__PHY_ADR_DC_ADJUST_THRSHLD_2__FLD LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_ADJUST_THRSHLD_2
+
+#define LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_ADJUST_DIRECT_2_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_ADJUST_DIRECT_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_ADJUST_DIRECT_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_ADJUST_DIRECT_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_ADJUST_DIRECT_2_WOSET 0U
+#define LPDDR4__PHY_ADR_DC_ADJUST_DIRECT_2__REG DENALI_PHY_1571
+#define LPDDR4__PHY_ADR_DC_ADJUST_DIRECT_2__FLD LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_ADJUST_DIRECT_2
+
+#define LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_CAL_POLARITY_2_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_CAL_POLARITY_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_CAL_POLARITY_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_CAL_POLARITY_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_CAL_POLARITY_2_WOSET 0U
+#define LPDDR4__PHY_ADR_DC_CAL_POLARITY_2__REG DENALI_PHY_1571
+#define LPDDR4__PHY_ADR_DC_CAL_POLARITY_2__FLD LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_CAL_POLARITY_2
+
+#define LPDDR4__DENALI_PHY_1572_READ_MASK 0x00003F01U
+#define LPDDR4__DENALI_PHY_1572_WRITE_MASK 0x00003F01U
+#define LPDDR4__DENALI_PHY_1572__PHY_ADR_DC_CAL_START_2_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1572__PHY_ADR_DC_CAL_START_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1572__PHY_ADR_DC_CAL_START_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1572__PHY_ADR_DC_CAL_START_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1572__PHY_ADR_DC_CAL_START_2_WOSET 0U
+#define LPDDR4__PHY_ADR_DC_CAL_START_2__REG DENALI_PHY_1572
+#define LPDDR4__PHY_ADR_DC_CAL_START_2__FLD LPDDR4__DENALI_PHY_1572__PHY_ADR_DC_CAL_START_2
+
+#define LPDDR4__DENALI_PHY_1572__PHY_ADR_SW_TXPWR_CTRL_2_MASK 0x00003F00U
+#define LPDDR4__DENALI_PHY_1572__PHY_ADR_SW_TXPWR_CTRL_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1572__PHY_ADR_SW_TXPWR_CTRL_2_WIDTH 6U
+#define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_2__REG DENALI_PHY_1572
+#define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_2__FLD LPDDR4__DENALI_PHY_1572__PHY_ADR_SW_TXPWR_CTRL_2
+
+#define LPDDR4__DENALI_PHY_1573_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1573_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1573__PHY_ADR_TSEL_SELECT_2_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_1573__PHY_ADR_TSEL_SELECT_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1573__PHY_ADR_TSEL_SELECT_2_WIDTH 8U
+#define LPDDR4__PHY_ADR_TSEL_SELECT_2__REG DENALI_PHY_1573
+#define LPDDR4__PHY_ADR_TSEL_SELECT_2__FLD LPDDR4__DENALI_PHY_1573__PHY_ADR_TSEL_SELECT_2
+
+#define LPDDR4__DENALI_PHY_1573__PHY_ADR_DC_CAL_CLK_SEL_2_MASK 0x00000700U
+#define LPDDR4__DENALI_PHY_1573__PHY_ADR_DC_CAL_CLK_SEL_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1573__PHY_ADR_DC_CAL_CLK_SEL_2_WIDTH 3U
+#define LPDDR4__PHY_ADR_DC_CAL_CLK_SEL_2__REG DENALI_PHY_1573
+#define LPDDR4__PHY_ADR_DC_CAL_CLK_SEL_2__FLD LPDDR4__DENALI_PHY_1573__PHY_ADR_DC_CAL_CLK_SEL_2
+
+#define LPDDR4__DENALI_PHY_1573__PHY_PAD_ADR_IO_CFG_2_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_1573__PHY_PAD_ADR_IO_CFG_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1573__PHY_PAD_ADR_IO_CFG_2_WIDTH 11U
+#define LPDDR4__PHY_PAD_ADR_IO_CFG_2__REG DENALI_PHY_1573
+#define LPDDR4__PHY_PAD_ADR_IO_CFG_2__FLD LPDDR4__DENALI_PHY_1573__PHY_PAD_ADR_IO_CFG_2
+
+#define LPDDR4__DENALI_PHY_1574_READ_MASK 0x07FF1F07U
+#define LPDDR4__DENALI_PHY_1574_WRITE_MASK 0x07FF1F07U
+#define LPDDR4__DENALI_PHY_1574__PHY_PAD_ADR_RX_PCLK_CLK_SEL_2_MASK 0x00000007U
+#define LPDDR4__DENALI_PHY_1574__PHY_PAD_ADR_RX_PCLK_CLK_SEL_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1574__PHY_PAD_ADR_RX_PCLK_CLK_SEL_2_WIDTH 3U
+#define LPDDR4__PHY_PAD_ADR_RX_PCLK_CLK_SEL_2__REG DENALI_PHY_1574
+#define LPDDR4__PHY_PAD_ADR_RX_PCLK_CLK_SEL_2__FLD LPDDR4__DENALI_PHY_1574__PHY_PAD_ADR_RX_PCLK_CLK_SEL_2
+
+#define LPDDR4__DENALI_PHY_1574__PHY_ADR0_SW_WRADDR_SHIFT_2_MASK 0x00001F00U
+#define LPDDR4__DENALI_PHY_1574__PHY_ADR0_SW_WRADDR_SHIFT_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1574__PHY_ADR0_SW_WRADDR_SHIFT_2_WIDTH 5U
+#define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_2__REG DENALI_PHY_1574
+#define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_2__FLD LPDDR4__DENALI_PHY_1574__PHY_ADR0_SW_WRADDR_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_1574__PHY_ADR0_CLK_WR_SLAVE_DELAY_2_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_1574__PHY_ADR0_CLK_WR_SLAVE_DELAY_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1574__PHY_ADR0_CLK_WR_SLAVE_DELAY_2_WIDTH 11U
+#define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_2__REG DENALI_PHY_1574
+#define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1574__PHY_ADR0_CLK_WR_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_1575_READ_MASK 0x1F07FF1FU
+#define LPDDR4__DENALI_PHY_1575_WRITE_MASK 0x1F07FF1FU
+#define LPDDR4__DENALI_PHY_1575__PHY_ADR1_SW_WRADDR_SHIFT_2_MASK 0x0000001FU
+#define LPDDR4__DENALI_PHY_1575__PHY_ADR1_SW_WRADDR_SHIFT_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1575__PHY_ADR1_SW_WRADDR_SHIFT_2_WIDTH 5U
+#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_2__REG DENALI_PHY_1575
+#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_2__FLD LPDDR4__DENALI_PHY_1575__PHY_ADR1_SW_WRADDR_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_1575__PHY_ADR1_CLK_WR_SLAVE_DELAY_2_MASK 0x0007FF00U
+#define LPDDR4__DENALI_PHY_1575__PHY_ADR1_CLK_WR_SLAVE_DELAY_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1575__PHY_ADR1_CLK_WR_SLAVE_DELAY_2_WIDTH 11U
+#define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_2__REG DENALI_PHY_1575
+#define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1575__PHY_ADR1_CLK_WR_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_1575__PHY_ADR2_SW_WRADDR_SHIFT_2_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_1575__PHY_ADR2_SW_WRADDR_SHIFT_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1575__PHY_ADR2_SW_WRADDR_SHIFT_2_WIDTH 5U
+#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_2__REG DENALI_PHY_1575
+#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_2__FLD LPDDR4__DENALI_PHY_1575__PHY_ADR2_SW_WRADDR_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_1576_READ_MASK 0x001F07FFU
+#define LPDDR4__DENALI_PHY_1576_WRITE_MASK 0x001F07FFU
+#define LPDDR4__DENALI_PHY_1576__PHY_ADR2_CLK_WR_SLAVE_DELAY_2_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1576__PHY_ADR2_CLK_WR_SLAVE_DELAY_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1576__PHY_ADR2_CLK_WR_SLAVE_DELAY_2_WIDTH 11U
+#define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_2__REG DENALI_PHY_1576
+#define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1576__PHY_ADR2_CLK_WR_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_1576__PHY_ADR3_SW_WRADDR_SHIFT_2_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_1576__PHY_ADR3_SW_WRADDR_SHIFT_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1576__PHY_ADR3_SW_WRADDR_SHIFT_2_WIDTH 5U
+#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_2__REG DENALI_PHY_1576
+#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_2__FLD LPDDR4__DENALI_PHY_1576__PHY_ADR3_SW_WRADDR_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_1577_READ_MASK 0x001F07FFU
+#define LPDDR4__DENALI_PHY_1577_WRITE_MASK 0x001F07FFU
+#define LPDDR4__DENALI_PHY_1577__PHY_ADR3_CLK_WR_SLAVE_DELAY_2_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1577__PHY_ADR3_CLK_WR_SLAVE_DELAY_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1577__PHY_ADR3_CLK_WR_SLAVE_DELAY_2_WIDTH 11U
+#define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_2__REG DENALI_PHY_1577
+#define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1577__PHY_ADR3_CLK_WR_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_1577__PHY_ADR4_SW_WRADDR_SHIFT_2_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_1577__PHY_ADR4_SW_WRADDR_SHIFT_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1577__PHY_ADR4_SW_WRADDR_SHIFT_2_WIDTH 5U
+#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_2__REG DENALI_PHY_1577
+#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_2__FLD LPDDR4__DENALI_PHY_1577__PHY_ADR4_SW_WRADDR_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_1578_READ_MASK 0x001F07FFU
+#define LPDDR4__DENALI_PHY_1578_WRITE_MASK 0x001F07FFU
+#define LPDDR4__DENALI_PHY_1578__PHY_ADR4_CLK_WR_SLAVE_DELAY_2_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1578__PHY_ADR4_CLK_WR_SLAVE_DELAY_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1578__PHY_ADR4_CLK_WR_SLAVE_DELAY_2_WIDTH 11U
+#define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_2__REG DENALI_PHY_1578
+#define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1578__PHY_ADR4_CLK_WR_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_1578__PHY_ADR5_SW_WRADDR_SHIFT_2_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_1578__PHY_ADR5_SW_WRADDR_SHIFT_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1578__PHY_ADR5_SW_WRADDR_SHIFT_2_WIDTH 5U
+#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_2__REG DENALI_PHY_1578
+#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_2__FLD LPDDR4__DENALI_PHY_1578__PHY_ADR5_SW_WRADDR_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_1579_READ_MASK 0x000F07FFU
+#define LPDDR4__DENALI_PHY_1579_WRITE_MASK 0x000F07FFU
+#define LPDDR4__DENALI_PHY_1579__PHY_ADR5_CLK_WR_SLAVE_DELAY_2_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1579__PHY_ADR5_CLK_WR_SLAVE_DELAY_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1579__PHY_ADR5_CLK_WR_SLAVE_DELAY_2_WIDTH 11U
+#define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_2__REG DENALI_PHY_1579
+#define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1579__PHY_ADR5_CLK_WR_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_1579__PHY_ADR_SW_MASTER_MODE_2_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_1579__PHY_ADR_SW_MASTER_MODE_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1579__PHY_ADR_SW_MASTER_MODE_2_WIDTH 4U
+#define LPDDR4__PHY_ADR_SW_MASTER_MODE_2__REG DENALI_PHY_1579
+#define LPDDR4__PHY_ADR_SW_MASTER_MODE_2__FLD LPDDR4__DENALI_PHY_1579__PHY_ADR_SW_MASTER_MODE_2
+
+#define LPDDR4__DENALI_PHY_1580_READ_MASK 0xFF3F07FFU
+#define LPDDR4__DENALI_PHY_1580_WRITE_MASK 0xFF3F07FFU
+#define LPDDR4__DENALI_PHY_1580__PHY_ADR_MASTER_DELAY_START_2_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1580__PHY_ADR_MASTER_DELAY_START_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1580__PHY_ADR_MASTER_DELAY_START_2_WIDTH 11U
+#define LPDDR4__PHY_ADR_MASTER_DELAY_START_2__REG DENALI_PHY_1580
+#define LPDDR4__PHY_ADR_MASTER_DELAY_START_2__FLD LPDDR4__DENALI_PHY_1580__PHY_ADR_MASTER_DELAY_START_2
+
+#define LPDDR4__DENALI_PHY_1580__PHY_ADR_MASTER_DELAY_STEP_2_MASK 0x003F0000U
+#define LPDDR4__DENALI_PHY_1580__PHY_ADR_MASTER_DELAY_STEP_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1580__PHY_ADR_MASTER_DELAY_STEP_2_WIDTH 6U
+#define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_2__REG DENALI_PHY_1580
+#define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_2__FLD LPDDR4__DENALI_PHY_1580__PHY_ADR_MASTER_DELAY_STEP_2
+
+#define LPDDR4__DENALI_PHY_1580__PHY_ADR_MASTER_DELAY_WAIT_2_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_1580__PHY_ADR_MASTER_DELAY_WAIT_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1580__PHY_ADR_MASTER_DELAY_WAIT_2_WIDTH 8U
+#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_2__REG DENALI_PHY_1580
+#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_2__FLD LPDDR4__DENALI_PHY_1580__PHY_ADR_MASTER_DELAY_WAIT_2
+
+#define LPDDR4__DENALI_PHY_1581_READ_MASK 0x0103FFFFU
+#define LPDDR4__DENALI_PHY_1581_WRITE_MASK 0x0103FFFFU
+#define LPDDR4__DENALI_PHY_1581__PHY_ADR_MASTER_DELAY_HALF_MEASURE_2_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_1581__PHY_ADR_MASTER_DELAY_HALF_MEASURE_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1581__PHY_ADR_MASTER_DELAY_HALF_MEASURE_2_WIDTH 8U
+#define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_2__REG DENALI_PHY_1581
+#define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_2__FLD LPDDR4__DENALI_PHY_1581__PHY_ADR_MASTER_DELAY_HALF_MEASURE_2
+
+#define LPDDR4__DENALI_PHY_1581__PHY_ADR_SW_CALVL_DVW_MIN_2_MASK 0x0003FF00U
+#define LPDDR4__DENALI_PHY_1581__PHY_ADR_SW_CALVL_DVW_MIN_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1581__PHY_ADR_SW_CALVL_DVW_MIN_2_WIDTH 10U
+#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_2__REG DENALI_PHY_1581
+#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_2__FLD LPDDR4__DENALI_PHY_1581__PHY_ADR_SW_CALVL_DVW_MIN_2
+
+#define LPDDR4__DENALI_PHY_1581__PHY_ADR_SW_CALVL_DVW_MIN_EN_2_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_1581__PHY_ADR_SW_CALVL_DVW_MIN_EN_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1581__PHY_ADR_SW_CALVL_DVW_MIN_EN_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1581__PHY_ADR_SW_CALVL_DVW_MIN_EN_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1581__PHY_ADR_SW_CALVL_DVW_MIN_EN_2_WOSET 0U
+#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_2__REG DENALI_PHY_1581
+#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_2__FLD LPDDR4__DENALI_PHY_1581__PHY_ADR_SW_CALVL_DVW_MIN_EN_2
+
+#define LPDDR4__DENALI_PHY_1582_READ_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_1582_WRITE_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_1582__PHY_ADR_CALVL_DLY_STEP_2_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_1582__PHY_ADR_CALVL_DLY_STEP_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1582__PHY_ADR_CALVL_DLY_STEP_2_WIDTH 4U
+#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_2__REG DENALI_PHY_1582
+#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_2__FLD LPDDR4__DENALI_PHY_1582__PHY_ADR_CALVL_DLY_STEP_2
+
+#define LPDDR4__DENALI_PHY_1583_READ_MASK 0x03FF010FU
+#define LPDDR4__DENALI_PHY_1583_WRITE_MASK 0x03FF010FU
+#define LPDDR4__DENALI_PHY_1583__PHY_ADR_CALVL_CAPTURE_CNT_2_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_1583__PHY_ADR_CALVL_CAPTURE_CNT_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1583__PHY_ADR_CALVL_CAPTURE_CNT_2_WIDTH 4U
+#define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_2__REG DENALI_PHY_1583
+#define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_2__FLD LPDDR4__DENALI_PHY_1583__PHY_ADR_CALVL_CAPTURE_CNT_2
+
+#define LPDDR4__DENALI_PHY_1583__PHY_ADR_MEAS_DLY_STEP_ENABLE_2_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_1583__PHY_ADR_MEAS_DLY_STEP_ENABLE_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1583__PHY_ADR_MEAS_DLY_STEP_ENABLE_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1583__PHY_ADR_MEAS_DLY_STEP_ENABLE_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1583__PHY_ADR_MEAS_DLY_STEP_ENABLE_2_WOSET 0U
+#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_2__REG DENALI_PHY_1583
+#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_2__FLD LPDDR4__DENALI_PHY_1583__PHY_ADR_MEAS_DLY_STEP_ENABLE_2
+
+#define LPDDR4__DENALI_PHY_1583__PHY_ADR_DC_INIT_SLV_DELAY_2_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_1583__PHY_ADR_DC_INIT_SLV_DELAY_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1583__PHY_ADR_DC_INIT_SLV_DELAY_2_WIDTH 10U
+#define LPDDR4__PHY_ADR_DC_INIT_SLV_DELAY_2__REG DENALI_PHY_1583
+#define LPDDR4__PHY_ADR_DC_INIT_SLV_DELAY_2__FLD LPDDR4__DENALI_PHY_1583__PHY_ADR_DC_INIT_SLV_DELAY_2
+
+#define LPDDR4__DENALI_PHY_1584_READ_MASK 0x0000FF01U
+#define LPDDR4__DENALI_PHY_1584_WRITE_MASK 0x0000FF01U
+#define LPDDR4__DENALI_PHY_1584__PHY_ADR_DC_CALVL_ENABLE_2_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1584__PHY_ADR_DC_CALVL_ENABLE_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1584__PHY_ADR_DC_CALVL_ENABLE_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1584__PHY_ADR_DC_CALVL_ENABLE_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1584__PHY_ADR_DC_CALVL_ENABLE_2_WOSET 0U
+#define LPDDR4__PHY_ADR_DC_CALVL_ENABLE_2__REG DENALI_PHY_1584
+#define LPDDR4__PHY_ADR_DC_CALVL_ENABLE_2__FLD LPDDR4__DENALI_PHY_1584__PHY_ADR_DC_CALVL_ENABLE_2
+
+#define LPDDR4__DENALI_PHY_1584__PHY_ADR_DC_DM_CLK_THRSHLD_2_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_1584__PHY_ADR_DC_DM_CLK_THRSHLD_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1584__PHY_ADR_DC_DM_CLK_THRSHLD_2_WIDTH 8U
+#define LPDDR4__PHY_ADR_DC_DM_CLK_THRSHLD_2__REG DENALI_PHY_1584
+#define LPDDR4__PHY_ADR_DC_DM_CLK_THRSHLD_2__FLD LPDDR4__DENALI_PHY_1584__PHY_ADR_DC_DM_CLK_THRSHLD_2
+
+#endif /* REG_LPDDR4_ADDRESS_SLICE_2_MACROS_H_ */
diff --git a/drivers/ram/k3-ddrss/am62a/lpddr4_am62a_ctl_regs_rw_masks.h b/drivers/ram/k3-ddrss/am62a/lpddr4_am62a_ctl_regs_rw_masks.h
new file mode 100644
index 00000000000..22384a1b742
--- /dev/null
+++ b/drivers/ram/k3-ddrss/am62a/lpddr4_am62a_ctl_regs_rw_masks.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef LPDDR4_RW_MASKS_H_
+#define LPDDR4_RW_MASKS_H_
+
+#include <stdint.h>
+
+extern u32 g_lpddr4_ddr_controller_rw_mask[435];
+extern u32 g_lpddr4_pi_rw_mask[424];
+extern u32 g_lpddr4_data_slice_0_rw_mask[137];
+extern u32 g_lpddr4_data_slice_1_rw_mask[137];
+extern u32 g_lpddr4_data_slice_2_rw_mask[137];
+extern u32 g_lpddr4_data_slice_3_rw_mask[137];
+extern u32 g_lpddr4_address_slice_0_rw_mask[49];
+extern u32 g_lpddr4_address_slice_1_rw_mask[49];
+extern u32 g_lpddr4_address_slice_2_rw_mask[49];
+extern u32 g_lpddr4_phy_core_rw_mask[132];
+
+#endif /* LPDDR4_RW_MASKS_H_ */
diff --git a/drivers/ram/k3-ddrss/am62a/lpddr4_am62a_if.h b/drivers/ram/k3-ddrss/am62a/lpddr4_am62a_if.h
new file mode 100644
index 00000000000..102184a502d
--- /dev/null
+++ b/drivers/ram/k3-ddrss/am62a/lpddr4_am62a_if.h
@@ -0,0 +1,108 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef LPDDR4_AM62A_IF_H
+#define LPDDR4_AM62A_IF_H
+
+#include <linux/types.h>
+
+#define LPDDR4_INTR_MAX_CS (2U)
+
+#define LPDDR4_INTR_CTL_REG_COUNT (435U)
+
+#define LPDDR4_INTR_PHY_INDEP_REG_COUNT (424U)
+
+#define LPDDR4_INTR_PHY_REG_COUNT (1924U)
+
+typedef enum {
+ LPDDR4_INTR_TIMEOUT_ZQ_CAL_INIT = 0U,
+ LPDDR4_INTR_TIMEOUT_ZQ_CALLATCH = 1U,
+ LPDDR4_INTR_TIMEOUT_ZQ_CALSTART = 2U,
+ LPDDR4_INTR_TIMEOUT_MRR_TEMP = 3U,
+ LPDDR4_INTR_TIMEOUT_DQS_OSC_REQ = 4U,
+ LPDDR4_INTR_TIMEOUT_DFI_UPDATE = 5U,
+ LPDDR4_INTR_TIMEOUT_LP_WAKEUP = 6U,
+ LPDDR4_INTR_TIMEOUT_AUTO_REFRESH_MAX = 7U,
+ LPDDR4_INTR_ECC_ERROR = 8U,
+ LPDDR4_INTR_LP_DONE = 9U,
+ LPDDR4_INTR_LP_TIMEOUT = 10U,
+ LPDDR4_INTR_PORT_TIMEOUT = 11U,
+ LPDDR4_INTR_RFIFO_TIMEOUT = 12U,
+ LPDDR4_INTR_TRAINING_ZQ_STATUS = 13U,
+ LPDDR4_INTR_TRAINING_DQS_OSC_DONE = 14U,
+ LPDDR4_INTR_TRAINING_DQS_OSC_UPDATE_DONE = 15U,
+ LPDDR4_INTR_TRAINING_DQS_OSC_OVERFLOW = 16U,
+ LPDDR4_INTR_TRAINING_DQS_OSC_VAR_OUT = 17U,
+ LPDDR4_INTR_USERIF_OUTSIDE_MEM_ACCESS = 18U,
+ LPDDR4_INTR_USERIF_MULTI_OUTSIDE_MEM_ACCESS = 19U,
+ LPDDR4_INTR_USERIF_PORT_CMD_ERROR = 20U,
+ LPDDR4_INTR_USERIF_WRAP = 21U,
+ LPDDR4_INTR_USERIF_INVAL_SETTING = 22U,
+ LPDDR4_INTR_MISC_MRR_TRAFFIC = 23U,
+ LPDDR4_INTR_MISC_SW_REQ_MODE = 24U,
+ LPDDR4_INTR_MISC_CHANGE_TEMP_REFRESH = 25U,
+ LPDDR4_INTR_MISC_TEMP_ALERT = 26U,
+ LPDDR4_INTR_MISC_REFRESH_STATUS = 27U,
+ LPDDR4_INTR_BIST_DONE = 28U,
+ LPDDR4_INTR_CRC = 29U,
+ LPDDR4_INTR_DFI_UPDATE_ERROR = 30U,
+ LPDDR4_INTR_DFI_PHY_ERROR = 31U,
+ LPDDR4_INTR_DFI_BUS_ERROR = 32U,
+ LPDDR4_INTR_DFI_STATE_CHANGE = 33U,
+ LPDDR4_INTR_DFI_DLL_SYNC_DONE = 34U,
+ LPDDR4_INTR_DFI_TIMEOUT = 35U,
+ LPDDR4_INTR_DIMM = 36U,
+ LPDDR4_INTR_FREQ_DFS_REQ_HW_IGNORE = 37U,
+ LPDDR4_INTR_FREQ_DFS_HW_TERMINATE = 38U,
+ LPDDR4_INTR_FREQ_DFS_HW_DONE = 39U,
+ LPDDR4_INTR_FREQ_DFS_REQ_SW_IGNORE = 40U,
+ LPDDR4_INTR_FREQ_DFS_SW_TERMINATE = 41U,
+ LPDDR4_INTR_FREQ_DFS_SW_DONE = 42U,
+ LPDDR4_INTR_INIT_MEM_RESET_DONE = 43U,
+ LPDDR4_INTR_MC_INIT_DONE = 44U,
+ LPDDR4_INTR_INIT_POWER_ON_STATE = 45U,
+ LPDDR4_INTR_MRR_ERROR = 46U,
+ LPDDR4_INTR_MR_READ_DONE = 47U,
+ LPDDR4_INTR_MR_WRITE_DONE = 48U,
+ LPDDR4_INTR_PARITY_ERROR = 49U,
+ LPDDR4_INTR_LOR_BITS = 50U
+} lpddr4_intr_ctlinterrupt;
+
+typedef enum {
+ LPDDR4_INTR_PHY_INDEP_INIT_DONE_BIT = 0U,
+ LPDDR4_INTR_PHY_INDEP_CA_PARITY_ERR_BIT = 1U,
+ LPDDR4_INTR_PHY_INDEP_RDLVL_ERROR_BIT = 2U,
+ LPDDR4_INTR_PHY_INDEP_RDLVL_G_ERROR_BIT = 3U,
+ LPDDR4_INTR_PHY_INDEP_WRLVL_ERROR_BIT = 4U,
+ LPDDR4_INTR_PHY_INDEP_CALVL_ERROR_BIT = 5U,
+ LPDDR4_INTR_PHY_INDEP_WDQLVL_ERROR_BIT = 6U,
+ LPDDR4_INTR_PHY_INDEP_UPDATE_ERROR_BIT = 7U,
+ LPDDR4_INTR_PHY_INDEP_RDLVL_REQ_BIT = 8U,
+ LPDDR4_INTR_PHY_INDEP_RDLVL_GATE_REQ_BIT = 9U,
+ LPDDR4_INTR_PHY_INDEP_WRLVL_REQ_BIT = 10U,
+ LPDDR4_INTR_PHY_INDEP_CALVL_REQ_BIT = 11U,
+ LPDDR4_INTR_PHY_INDEP_WDQLVL_REQ_BIT = 12U,
+ LPDDR4_INTR_PHY_INDEP_LVL_DONE_BIT = 13U,
+ LPDDR4_INTR_PHY_INDEP_BIST_DONE_BIT = 14U,
+ LPDDR4_INTR_PHY_INDEP_TDFI_INIT_TIME_OUT_BIT = 15U,
+ LPDDR4_INTR_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT = 16U,
+ LPDDR4_INTR_PHY_INDEP_MEM_RST_VALID_BIT = 17U,
+ LPDDR4_INTR_PHY_INDEP_ZQ_STATUS_BIT = 18U,
+ LPDDR4_INTR_PHY_INDEP_PERIPHERAL_MRR_DONE_BIT = 19U,
+ LPDDR4_INTR_PHY_INDEP_WRITE_NODEREG_DONE_BIT = 20U,
+ LPDDR4_INTR_PHY_INDEP_FREQ_CHANGE_DONE_BIT = 21U,
+ LPDDR4_INTR_PHY_INDEP_RDLVL_G_DONE_BIT = 22U,
+ LPDDR4_INTR_PHY_INDEP_RDLVL_DONE_BIT = 23U,
+ LPDDR4_INTR_PHY_INDEP_WRLVL_DONE_BIT = 24U,
+ LPDDR4_INTR_PHY_INDEP_CALVL_DONE__BIT = 25U,
+ LPDDR4_INTR_PHY_INDEP_WDQLVL_DONE_BIT = 26U,
+ LPDDR4_INTR_PHY_INDEP_VREF_DONE_BIT = 27U,
+ LPDDR4_INTR_PHY_INDEP_ANY_VALID_BIT = 28U
+} lpddr4_intr_phyindepinterrupt;
+
+#endif /* LPDDR4_AM62A_IF_H */
diff --git a/drivers/ram/k3-ddrss/am62a/lpddr4_am62a_obj_if.h b/drivers/ram/k3-ddrss/am62a/lpddr4_am62a_obj_if.h
new file mode 100644
index 00000000000..4c41863c5b8
--- /dev/null
+++ b/drivers/ram/k3-ddrss/am62a/lpddr4_am62a_obj_if.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef LPDDR4_AM62A_OBJ_IF_H
+#define LPDDR4_AM62A_OBJ_IF_H
+
+#include "lpddr4_am62a_if.h"
+
+#endif /* LPDDR4_AM62A_OBJ_IF_H */
diff --git a/drivers/ram/k3-ddrss/am62a/lpddr4_am62a_structs_if.h b/drivers/ram/k3-ddrss/am62a/lpddr4_am62a_structs_if.h
new file mode 100644
index 00000000000..ab2b1f1a0f4
--- /dev/null
+++ b/drivers/ram/k3-ddrss/am62a/lpddr4_am62a_structs_if.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef LPDDR4_AM62A_STRUCTS_IF_H
+#define LPDDR4_AM62A_STRUCTS_IF_H
+
+#include <linux/types.h>
+#include "lpddr4_am62a_if.h"
+
+#endif /* LPDDR4_AM62A_STRUCTS_IF_H */
diff --git a/drivers/ram/k3-ddrss/am62a/lpddr4_ctl_regs.h b/drivers/ram/k3-ddrss/am62a/lpddr4_ctl_regs.h
new file mode 100644
index 00000000000..7a9ec00c8a4
--- /dev/null
+++ b/drivers/ram/k3-ddrss/am62a/lpddr4_ctl_regs.h
@@ -0,0 +1,1721 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef REG_LPDDR4_CTL_REGS_H_
+#define REG_LPDDR4_CTL_REGS_H_
+
+#include "lpddr4_ddr_controller_macros.h"
+#include "lpddr4_pi_macros.h"
+#include "lpddr4_data_slice_0_macros.h"
+#include "lpddr4_data_slice_1_macros.h"
+#include "lpddr4_data_slice_2_macros.h"
+#include "lpddr4_data_slice_3_macros.h"
+#include "lpddr4_address_slice_0_macros.h"
+#include "lpddr4_address_slice_1_macros.h"
+#include "lpddr4_address_slice_2_macros.h"
+#include "lpddr4_phy_core_macros.h"
+
+typedef struct __attribute__((packed)) lpddr4_ctlregs_s {
+ volatile u32 DENALI_CTL_0;
+ volatile u32 DENALI_CTL_1;
+ volatile u32 DENALI_CTL_2;
+ volatile u32 DENALI_CTL_3;
+ volatile u32 DENALI_CTL_4;
+ volatile u32 DENALI_CTL_5;
+ volatile u32 DENALI_CTL_6;
+ volatile u32 DENALI_CTL_7;
+ volatile u32 DENALI_CTL_8;
+ volatile u32 DENALI_CTL_9;
+ volatile u32 DENALI_CTL_10;
+ volatile u32 DENALI_CTL_11;
+ volatile u32 DENALI_CTL_12;
+ volatile u32 DENALI_CTL_13;
+ volatile u32 DENALI_CTL_14;
+ volatile u32 DENALI_CTL_15;
+ volatile u32 DENALI_CTL_16;
+ volatile u32 DENALI_CTL_17;
+ volatile u32 DENALI_CTL_18;
+ volatile u32 DENALI_CTL_19;
+ volatile u32 DENALI_CTL_20;
+ volatile u32 DENALI_CTL_21;
+ volatile u32 DENALI_CTL_22;
+ volatile u32 DENALI_CTL_23;
+ volatile u32 DENALI_CTL_24;
+ volatile u32 DENALI_CTL_25;
+ volatile u32 DENALI_CTL_26;
+ volatile u32 DENALI_CTL_27;
+ volatile u32 DENALI_CTL_28;
+ volatile u32 DENALI_CTL_29;
+ volatile u32 DENALI_CTL_30;
+ volatile u32 DENALI_CTL_31;
+ volatile u32 DENALI_CTL_32;
+ volatile u32 DENALI_CTL_33;
+ volatile u32 DENALI_CTL_34;
+ volatile u32 DENALI_CTL_35;
+ volatile u32 DENALI_CTL_36;
+ volatile u32 DENALI_CTL_37;
+ volatile u32 DENALI_CTL_38;
+ volatile u32 DENALI_CTL_39;
+ volatile u32 DENALI_CTL_40;
+ volatile u32 DENALI_CTL_41;
+ volatile u32 DENALI_CTL_42;
+ volatile u32 DENALI_CTL_43;
+ volatile u32 DENALI_CTL_44;
+ volatile u32 DENALI_CTL_45;
+ volatile u32 DENALI_CTL_46;
+ volatile u32 DENALI_CTL_47;
+ volatile u32 DENALI_CTL_48;
+ volatile u32 DENALI_CTL_49;
+ volatile u32 DENALI_CTL_50;
+ volatile u32 DENALI_CTL_51;
+ volatile u32 DENALI_CTL_52;
+ volatile u32 DENALI_CTL_53;
+ volatile u32 DENALI_CTL_54;
+ volatile u32 DENALI_CTL_55;
+ volatile u32 DENALI_CTL_56;
+ volatile u32 DENALI_CTL_57;
+ volatile u32 DENALI_CTL_58;
+ volatile u32 DENALI_CTL_59;
+ volatile u32 DENALI_CTL_60;
+ volatile u32 DENALI_CTL_61;
+ volatile u32 DENALI_CTL_62;
+ volatile u32 DENALI_CTL_63;
+ volatile u32 DENALI_CTL_64;
+ volatile u32 DENALI_CTL_65;
+ volatile u32 DENALI_CTL_66;
+ volatile u32 DENALI_CTL_67;
+ volatile u32 DENALI_CTL_68;
+ volatile u32 DENALI_CTL_69;
+ volatile u32 DENALI_CTL_70;
+ volatile u32 DENALI_CTL_71;
+ volatile u32 DENALI_CTL_72;
+ volatile u32 DENALI_CTL_73;
+ volatile u32 DENALI_CTL_74;
+ volatile u32 DENALI_CTL_75;
+ volatile u32 DENALI_CTL_76;
+ volatile u32 DENALI_CTL_77;
+ volatile u32 DENALI_CTL_78;
+ volatile u32 DENALI_CTL_79;
+ volatile u32 DENALI_CTL_80;
+ volatile u32 DENALI_CTL_81;
+ volatile u32 DENALI_CTL_82;
+ volatile u32 DENALI_CTL_83;
+ volatile u32 DENALI_CTL_84;
+ volatile u32 DENALI_CTL_85;
+ volatile u32 DENALI_CTL_86;
+ volatile u32 DENALI_CTL_87;
+ volatile u32 DENALI_CTL_88;
+ volatile u32 DENALI_CTL_89;
+ volatile u32 DENALI_CTL_90;
+ volatile u32 DENALI_CTL_91;
+ volatile u32 DENALI_CTL_92;
+ volatile u32 DENALI_CTL_93;
+ volatile u32 DENALI_CTL_94;
+ volatile u32 DENALI_CTL_95;
+ volatile u32 DENALI_CTL_96;
+ volatile u32 DENALI_CTL_97;
+ volatile u32 DENALI_CTL_98;
+ volatile u32 DENALI_CTL_99;
+ volatile u32 DENALI_CTL_100;
+ volatile u32 DENALI_CTL_101;
+ volatile u32 DENALI_CTL_102;
+ volatile u32 DENALI_CTL_103;
+ volatile u32 DENALI_CTL_104;
+ volatile u32 DENALI_CTL_105;
+ volatile u32 DENALI_CTL_106;
+ volatile u32 DENALI_CTL_107;
+ volatile u32 DENALI_CTL_108;
+ volatile u32 DENALI_CTL_109;
+ volatile u32 DENALI_CTL_110;
+ volatile u32 DENALI_CTL_111;
+ volatile u32 DENALI_CTL_112;
+ volatile u32 DENALI_CTL_113;
+ volatile u32 DENALI_CTL_114;
+ volatile u32 DENALI_CTL_115;
+ volatile u32 DENALI_CTL_116;
+ volatile u32 DENALI_CTL_117;
+ volatile u32 DENALI_CTL_118;
+ volatile u32 DENALI_CTL_119;
+ volatile u32 DENALI_CTL_120;
+ volatile u32 DENALI_CTL_121;
+ volatile u32 DENALI_CTL_122;
+ volatile u32 DENALI_CTL_123;
+ volatile u32 DENALI_CTL_124;
+ volatile u32 DENALI_CTL_125;
+ volatile u32 DENALI_CTL_126;
+ volatile u32 DENALI_CTL_127;
+ volatile u32 DENALI_CTL_128;
+ volatile u32 DENALI_CTL_129;
+ volatile u32 DENALI_CTL_130;
+ volatile u32 DENALI_CTL_131;
+ volatile u32 DENALI_CTL_132;
+ volatile u32 DENALI_CTL_133;
+ volatile u32 DENALI_CTL_134;
+ volatile u32 DENALI_CTL_135;
+ volatile u32 DENALI_CTL_136;
+ volatile u32 DENALI_CTL_137;
+ volatile u32 DENALI_CTL_138;
+ volatile u32 DENALI_CTL_139;
+ volatile u32 DENALI_CTL_140;
+ volatile u32 DENALI_CTL_141;
+ volatile u32 DENALI_CTL_142;
+ volatile u32 DENALI_CTL_143;
+ volatile u32 DENALI_CTL_144;
+ volatile u32 DENALI_CTL_145;
+ volatile u32 DENALI_CTL_146;
+ volatile u32 DENALI_CTL_147;
+ volatile u32 DENALI_CTL_148;
+ volatile u32 DENALI_CTL_149;
+ volatile u32 DENALI_CTL_150;
+ volatile u32 DENALI_CTL_151;
+ volatile u32 DENALI_CTL_152;
+ volatile u32 DENALI_CTL_153;
+ volatile u32 DENALI_CTL_154;
+ volatile u32 DENALI_CTL_155;
+ volatile u32 DENALI_CTL_156;
+ volatile u32 DENALI_CTL_157;
+ volatile u32 DENALI_CTL_158;
+ volatile u32 DENALI_CTL_159;
+ volatile u32 DENALI_CTL_160;
+ volatile u32 DENALI_CTL_161;
+ volatile u32 DENALI_CTL_162;
+ volatile u32 DENALI_CTL_163;
+ volatile u32 DENALI_CTL_164;
+ volatile u32 DENALI_CTL_165;
+ volatile u32 DENALI_CTL_166;
+ volatile u32 DENALI_CTL_167;
+ volatile u32 DENALI_CTL_168;
+ volatile u32 DENALI_CTL_169;
+ volatile u32 DENALI_CTL_170;
+ volatile u32 DENALI_CTL_171;
+ volatile u32 DENALI_CTL_172;
+ volatile u32 DENALI_CTL_173;
+ volatile u32 DENALI_CTL_174;
+ volatile u32 DENALI_CTL_175;
+ volatile u32 DENALI_CTL_176;
+ volatile u32 DENALI_CTL_177;
+ volatile u32 DENALI_CTL_178;
+ volatile u32 DENALI_CTL_179;
+ volatile u32 DENALI_CTL_180;
+ volatile u32 DENALI_CTL_181;
+ volatile u32 DENALI_CTL_182;
+ volatile u32 DENALI_CTL_183;
+ volatile u32 DENALI_CTL_184;
+ volatile u32 DENALI_CTL_185;
+ volatile u32 DENALI_CTL_186;
+ volatile u32 DENALI_CTL_187;
+ volatile u32 DENALI_CTL_188;
+ volatile u32 DENALI_CTL_189;
+ volatile u32 DENALI_CTL_190;
+ volatile u32 DENALI_CTL_191;
+ volatile u32 DENALI_CTL_192;
+ volatile u32 DENALI_CTL_193;
+ volatile u32 DENALI_CTL_194;
+ volatile u32 DENALI_CTL_195;
+ volatile u32 DENALI_CTL_196;
+ volatile u32 DENALI_CTL_197;
+ volatile u32 DENALI_CTL_198;
+ volatile u32 DENALI_CTL_199;
+ volatile u32 DENALI_CTL_200;
+ volatile u32 DENALI_CTL_201;
+ volatile u32 DENALI_CTL_202;
+ volatile u32 DENALI_CTL_203;
+ volatile u32 DENALI_CTL_204;
+ volatile u32 DENALI_CTL_205;
+ volatile u32 DENALI_CTL_206;
+ volatile u32 DENALI_CTL_207;
+ volatile u32 DENALI_CTL_208;
+ volatile u32 DENALI_CTL_209;
+ volatile u32 DENALI_CTL_210;
+ volatile u32 DENALI_CTL_211;
+ volatile u32 DENALI_CTL_212;
+ volatile u32 DENALI_CTL_213;
+ volatile u32 DENALI_CTL_214;
+ volatile u32 DENALI_CTL_215;
+ volatile u32 DENALI_CTL_216;
+ volatile u32 DENALI_CTL_217;
+ volatile u32 DENALI_CTL_218;
+ volatile u32 DENALI_CTL_219;
+ volatile u32 DENALI_CTL_220;
+ volatile u32 DENALI_CTL_221;
+ volatile u32 DENALI_CTL_222;
+ volatile u32 DENALI_CTL_223;
+ volatile u32 DENALI_CTL_224;
+ volatile u32 DENALI_CTL_225;
+ volatile u32 DENALI_CTL_226;
+ volatile u32 DENALI_CTL_227;
+ volatile u32 DENALI_CTL_228;
+ volatile u32 DENALI_CTL_229;
+ volatile u32 DENALI_CTL_230;
+ volatile u32 DENALI_CTL_231;
+ volatile u32 DENALI_CTL_232;
+ volatile u32 DENALI_CTL_233;
+ volatile u32 DENALI_CTL_234;
+ volatile u32 DENALI_CTL_235;
+ volatile u32 DENALI_CTL_236;
+ volatile u32 DENALI_CTL_237;
+ volatile u32 DENALI_CTL_238;
+ volatile u32 DENALI_CTL_239;
+ volatile u32 DENALI_CTL_240;
+ volatile u32 DENALI_CTL_241;
+ volatile u32 DENALI_CTL_242;
+ volatile u32 DENALI_CTL_243;
+ volatile u32 DENALI_CTL_244;
+ volatile u32 DENALI_CTL_245;
+ volatile u32 DENALI_CTL_246;
+ volatile u32 DENALI_CTL_247;
+ volatile u32 DENALI_CTL_248;
+ volatile u32 DENALI_CTL_249;
+ volatile u32 DENALI_CTL_250;
+ volatile u32 DENALI_CTL_251;
+ volatile u32 DENALI_CTL_252;
+ volatile u32 DENALI_CTL_253;
+ volatile u32 DENALI_CTL_254;
+ volatile u32 DENALI_CTL_255;
+ volatile u32 DENALI_CTL_256;
+ volatile u32 DENALI_CTL_257;
+ volatile u32 DENALI_CTL_258;
+ volatile u32 DENALI_CTL_259;
+ volatile u32 DENALI_CTL_260;
+ volatile u32 DENALI_CTL_261;
+ volatile u32 DENALI_CTL_262;
+ volatile u32 DENALI_CTL_263;
+ volatile u32 DENALI_CTL_264;
+ volatile u32 DENALI_CTL_265;
+ volatile u32 DENALI_CTL_266;
+ volatile u32 DENALI_CTL_267;
+ volatile u32 DENALI_CTL_268;
+ volatile u32 DENALI_CTL_269;
+ volatile u32 DENALI_CTL_270;
+ volatile u32 DENALI_CTL_271;
+ volatile u32 DENALI_CTL_272;
+ volatile u32 DENALI_CTL_273;
+ volatile u32 DENALI_CTL_274;
+ volatile u32 DENALI_CTL_275;
+ volatile u32 DENALI_CTL_276;
+ volatile u32 DENALI_CTL_277;
+ volatile u32 DENALI_CTL_278;
+ volatile u32 DENALI_CTL_279;
+ volatile u32 DENALI_CTL_280;
+ volatile u32 DENALI_CTL_281;
+ volatile u32 DENALI_CTL_282;
+ volatile u32 DENALI_CTL_283;
+ volatile u32 DENALI_CTL_284;
+ volatile u32 DENALI_CTL_285;
+ volatile u32 DENALI_CTL_286;
+ volatile u32 DENALI_CTL_287;
+ volatile u32 DENALI_CTL_288;
+ volatile u32 DENALI_CTL_289;
+ volatile u32 DENALI_CTL_290;
+ volatile u32 DENALI_CTL_291;
+ volatile u32 DENALI_CTL_292;
+ volatile u32 DENALI_CTL_293;
+ volatile u32 DENALI_CTL_294;
+ volatile u32 DENALI_CTL_295;
+ volatile u32 DENALI_CTL_296;
+ volatile u32 DENALI_CTL_297;
+ volatile u32 DENALI_CTL_298;
+ volatile u32 DENALI_CTL_299;
+ volatile u32 DENALI_CTL_300;
+ volatile u32 DENALI_CTL_301;
+ volatile u32 DENALI_CTL_302;
+ volatile u32 DENALI_CTL_303;
+ volatile u32 DENALI_CTL_304;
+ volatile u32 DENALI_CTL_305;
+ volatile u32 DENALI_CTL_306;
+ volatile u32 DENALI_CTL_307;
+ volatile u32 DENALI_CTL_308;
+ volatile u32 DENALI_CTL_309;
+ volatile u32 DENALI_CTL_310;
+ volatile u32 DENALI_CTL_311;
+ volatile u32 DENALI_CTL_312;
+ volatile u32 DENALI_CTL_313;
+ volatile u32 DENALI_CTL_314;
+ volatile u32 DENALI_CTL_315;
+ volatile u32 DENALI_CTL_316;
+ volatile u32 DENALI_CTL_317;
+ volatile u32 DENALI_CTL_318;
+ volatile u32 DENALI_CTL_319;
+ volatile u32 DENALI_CTL_320;
+ volatile u32 DENALI_CTL_321;
+ volatile u32 DENALI_CTL_322;
+ volatile u32 DENALI_CTL_323;
+ volatile u32 DENALI_CTL_324;
+ volatile u32 DENALI_CTL_325;
+ volatile u32 DENALI_CTL_326;
+ volatile u32 DENALI_CTL_327;
+ volatile u32 DENALI_CTL_328;
+ volatile u32 DENALI_CTL_329;
+ volatile u32 DENALI_CTL_330;
+ volatile u32 DENALI_CTL_331;
+ volatile u32 DENALI_CTL_332;
+ volatile u32 DENALI_CTL_333;
+ volatile u32 DENALI_CTL_334;
+ volatile u32 DENALI_CTL_335;
+ volatile u32 DENALI_CTL_336;
+ volatile u32 DENALI_CTL_337;
+ volatile u32 DENALI_CTL_338;
+ volatile u32 DENALI_CTL_339;
+ volatile u32 DENALI_CTL_340;
+ volatile u32 DENALI_CTL_341;
+ volatile u32 DENALI_CTL_342;
+ volatile u32 DENALI_CTL_343;
+ volatile u32 DENALI_CTL_344;
+ volatile u32 DENALI_CTL_345;
+ volatile u32 DENALI_CTL_346;
+ volatile u32 DENALI_CTL_347;
+ volatile u32 DENALI_CTL_348;
+ volatile u32 DENALI_CTL_349;
+ volatile u32 DENALI_CTL_350;
+ volatile u32 DENALI_CTL_351;
+ volatile u32 DENALI_CTL_352;
+ volatile u32 DENALI_CTL_353;
+ volatile u32 DENALI_CTL_354;
+ volatile u32 DENALI_CTL_355;
+ volatile u32 DENALI_CTL_356;
+ volatile u32 DENALI_CTL_357;
+ volatile u32 DENALI_CTL_358;
+ volatile u32 DENALI_CTL_359;
+ volatile u32 DENALI_CTL_360;
+ volatile u32 DENALI_CTL_361;
+ volatile u32 DENALI_CTL_362;
+ volatile u32 DENALI_CTL_363;
+ volatile u32 DENALI_CTL_364;
+ volatile u32 DENALI_CTL_365;
+ volatile u32 DENALI_CTL_366;
+ volatile u32 DENALI_CTL_367;
+ volatile u32 DENALI_CTL_368;
+ volatile u32 DENALI_CTL_369;
+ volatile u32 DENALI_CTL_370;
+ volatile u32 DENALI_CTL_371;
+ volatile u32 DENALI_CTL_372;
+ volatile u32 DENALI_CTL_373;
+ volatile u32 DENALI_CTL_374;
+ volatile u32 DENALI_CTL_375;
+ volatile u32 DENALI_CTL_376;
+ volatile u32 DENALI_CTL_377;
+ volatile u32 DENALI_CTL_378;
+ volatile u32 DENALI_CTL_379;
+ volatile u32 DENALI_CTL_380;
+ volatile u32 DENALI_CTL_381;
+ volatile u32 DENALI_CTL_382;
+ volatile u32 DENALI_CTL_383;
+ volatile u32 DENALI_CTL_384;
+ volatile u32 DENALI_CTL_385;
+ volatile u32 DENALI_CTL_386;
+ volatile u32 DENALI_CTL_387;
+ volatile u32 DENALI_CTL_388;
+ volatile u32 DENALI_CTL_389;
+ volatile u32 DENALI_CTL_390;
+ volatile u32 DENALI_CTL_391;
+ volatile u32 DENALI_CTL_392;
+ volatile u32 DENALI_CTL_393;
+ volatile u32 DENALI_CTL_394;
+ volatile u32 DENALI_CTL_395;
+ volatile u32 DENALI_CTL_396;
+ volatile u32 DENALI_CTL_397;
+ volatile u32 DENALI_CTL_398;
+ volatile u32 DENALI_CTL_399;
+ volatile u32 DENALI_CTL_400;
+ volatile u32 DENALI_CTL_401;
+ volatile u32 DENALI_CTL_402;
+ volatile u32 DENALI_CTL_403;
+ volatile u32 DENALI_CTL_404;
+ volatile u32 DENALI_CTL_405;
+ volatile u32 DENALI_CTL_406;
+ volatile u32 DENALI_CTL_407;
+ volatile u32 DENALI_CTL_408;
+ volatile u32 DENALI_CTL_409;
+ volatile u32 DENALI_CTL_410;
+ volatile u32 DENALI_CTL_411;
+ volatile u32 DENALI_CTL_412;
+ volatile u32 DENALI_CTL_413;
+ volatile u32 DENALI_CTL_414;
+ volatile u32 DENALI_CTL_415;
+ volatile u32 DENALI_CTL_416;
+ volatile u32 DENALI_CTL_417;
+ volatile u32 DENALI_CTL_418;
+ volatile u32 DENALI_CTL_419;
+ volatile u32 DENALI_CTL_420;
+ volatile u32 DENALI_CTL_421;
+ volatile u32 DENALI_CTL_422;
+ volatile u32 DENALI_CTL_423;
+ volatile u32 DENALI_CTL_424;
+ volatile u32 DENALI_CTL_425;
+ volatile u32 DENALI_CTL_426;
+ volatile u32 DENALI_CTL_427;
+ volatile u32 DENALI_CTL_428;
+ volatile u32 DENALI_CTL_429;
+ volatile u32 DENALI_CTL_430;
+ volatile u32 DENALI_CTL_431;
+ volatile u32 DENALI_CTL_432;
+ volatile u32 DENALI_CTL_433;
+ volatile u32 DENALI_CTL_434;
+ volatile char pad__0[0x1934U];
+ volatile u32 DENALI_PI_0;
+ volatile u32 DENALI_PI_1;
+ volatile u32 DENALI_PI_2;
+ volatile u32 DENALI_PI_3;
+ volatile u32 DENALI_PI_4;
+ volatile u32 DENALI_PI_5;
+ volatile u32 DENALI_PI_6;
+ volatile u32 DENALI_PI_7;
+ volatile u32 DENALI_PI_8;
+ volatile u32 DENALI_PI_9;
+ volatile u32 DENALI_PI_10;
+ volatile u32 DENALI_PI_11;
+ volatile u32 DENALI_PI_12;
+ volatile u32 DENALI_PI_13;
+ volatile u32 DENALI_PI_14;
+ volatile u32 DENALI_PI_15;
+ volatile u32 DENALI_PI_16;
+ volatile u32 DENALI_PI_17;
+ volatile u32 DENALI_PI_18;
+ volatile u32 DENALI_PI_19;
+ volatile u32 DENALI_PI_20;
+ volatile u32 DENALI_PI_21;
+ volatile u32 DENALI_PI_22;
+ volatile u32 DENALI_PI_23;
+ volatile u32 DENALI_PI_24;
+ volatile u32 DENALI_PI_25;
+ volatile u32 DENALI_PI_26;
+ volatile u32 DENALI_PI_27;
+ volatile u32 DENALI_PI_28;
+ volatile u32 DENALI_PI_29;
+ volatile u32 DENALI_PI_30;
+ volatile u32 DENALI_PI_31;
+ volatile u32 DENALI_PI_32;
+ volatile u32 DENALI_PI_33;
+ volatile u32 DENALI_PI_34;
+ volatile u32 DENALI_PI_35;
+ volatile u32 DENALI_PI_36;
+ volatile u32 DENALI_PI_37;
+ volatile u32 DENALI_PI_38;
+ volatile u32 DENALI_PI_39;
+ volatile u32 DENALI_PI_40;
+ volatile u32 DENALI_PI_41;
+ volatile u32 DENALI_PI_42;
+ volatile u32 DENALI_PI_43;
+ volatile u32 DENALI_PI_44;
+ volatile u32 DENALI_PI_45;
+ volatile u32 DENALI_PI_46;
+ volatile u32 DENALI_PI_47;
+ volatile u32 DENALI_PI_48;
+ volatile u32 DENALI_PI_49;
+ volatile u32 DENALI_PI_50;
+ volatile u32 DENALI_PI_51;
+ volatile u32 DENALI_PI_52;
+ volatile u32 DENALI_PI_53;
+ volatile u32 DENALI_PI_54;
+ volatile u32 DENALI_PI_55;
+ volatile u32 DENALI_PI_56;
+ volatile u32 DENALI_PI_57;
+ volatile u32 DENALI_PI_58;
+ volatile u32 DENALI_PI_59;
+ volatile u32 DENALI_PI_60;
+ volatile u32 DENALI_PI_61;
+ volatile u32 DENALI_PI_62;
+ volatile u32 DENALI_PI_63;
+ volatile u32 DENALI_PI_64;
+ volatile u32 DENALI_PI_65;
+ volatile u32 DENALI_PI_66;
+ volatile u32 DENALI_PI_67;
+ volatile u32 DENALI_PI_68;
+ volatile u32 DENALI_PI_69;
+ volatile u32 DENALI_PI_70;
+ volatile u32 DENALI_PI_71;
+ volatile u32 DENALI_PI_72;
+ volatile u32 DENALI_PI_73;
+ volatile u32 DENALI_PI_74;
+ volatile u32 DENALI_PI_75;
+ volatile u32 DENALI_PI_76;
+ volatile u32 DENALI_PI_77;
+ volatile u32 DENALI_PI_78;
+ volatile u32 DENALI_PI_79;
+ volatile u32 DENALI_PI_80;
+ volatile u32 DENALI_PI_81;
+ volatile u32 DENALI_PI_82;
+ volatile u32 DENALI_PI_83;
+ volatile u32 DENALI_PI_84;
+ volatile u32 DENALI_PI_85;
+ volatile u32 DENALI_PI_86;
+ volatile u32 DENALI_PI_87;
+ volatile u32 DENALI_PI_88;
+ volatile u32 DENALI_PI_89;
+ volatile u32 DENALI_PI_90;
+ volatile u32 DENALI_PI_91;
+ volatile u32 DENALI_PI_92;
+ volatile u32 DENALI_PI_93;
+ volatile u32 DENALI_PI_94;
+ volatile u32 DENALI_PI_95;
+ volatile u32 DENALI_PI_96;
+ volatile u32 DENALI_PI_97;
+ volatile u32 DENALI_PI_98;
+ volatile u32 DENALI_PI_99;
+ volatile u32 DENALI_PI_100;
+ volatile u32 DENALI_PI_101;
+ volatile u32 DENALI_PI_102;
+ volatile u32 DENALI_PI_103;
+ volatile u32 DENALI_PI_104;
+ volatile u32 DENALI_PI_105;
+ volatile u32 DENALI_PI_106;
+ volatile u32 DENALI_PI_107;
+ volatile u32 DENALI_PI_108;
+ volatile u32 DENALI_PI_109;
+ volatile u32 DENALI_PI_110;
+ volatile u32 DENALI_PI_111;
+ volatile u32 DENALI_PI_112;
+ volatile u32 DENALI_PI_113;
+ volatile u32 DENALI_PI_114;
+ volatile u32 DENALI_PI_115;
+ volatile u32 DENALI_PI_116;
+ volatile u32 DENALI_PI_117;
+ volatile u32 DENALI_PI_118;
+ volatile u32 DENALI_PI_119;
+ volatile u32 DENALI_PI_120;
+ volatile u32 DENALI_PI_121;
+ volatile u32 DENALI_PI_122;
+ volatile u32 DENALI_PI_123;
+ volatile u32 DENALI_PI_124;
+ volatile u32 DENALI_PI_125;
+ volatile u32 DENALI_PI_126;
+ volatile u32 DENALI_PI_127;
+ volatile u32 DENALI_PI_128;
+ volatile u32 DENALI_PI_129;
+ volatile u32 DENALI_PI_130;
+ volatile u32 DENALI_PI_131;
+ volatile u32 DENALI_PI_132;
+ volatile u32 DENALI_PI_133;
+ volatile u32 DENALI_PI_134;
+ volatile u32 DENALI_PI_135;
+ volatile u32 DENALI_PI_136;
+ volatile u32 DENALI_PI_137;
+ volatile u32 DENALI_PI_138;
+ volatile u32 DENALI_PI_139;
+ volatile u32 DENALI_PI_140;
+ volatile u32 DENALI_PI_141;
+ volatile u32 DENALI_PI_142;
+ volatile u32 DENALI_PI_143;
+ volatile u32 DENALI_PI_144;
+ volatile u32 DENALI_PI_145;
+ volatile u32 DENALI_PI_146;
+ volatile u32 DENALI_PI_147;
+ volatile u32 DENALI_PI_148;
+ volatile u32 DENALI_PI_149;
+ volatile u32 DENALI_PI_150;
+ volatile u32 DENALI_PI_151;
+ volatile u32 DENALI_PI_152;
+ volatile u32 DENALI_PI_153;
+ volatile u32 DENALI_PI_154;
+ volatile u32 DENALI_PI_155;
+ volatile u32 DENALI_PI_156;
+ volatile u32 DENALI_PI_157;
+ volatile u32 DENALI_PI_158;
+ volatile u32 DENALI_PI_159;
+ volatile u32 DENALI_PI_160;
+ volatile u32 DENALI_PI_161;
+ volatile u32 DENALI_PI_162;
+ volatile u32 DENALI_PI_163;
+ volatile u32 DENALI_PI_164;
+ volatile u32 DENALI_PI_165;
+ volatile u32 DENALI_PI_166;
+ volatile u32 DENALI_PI_167;
+ volatile u32 DENALI_PI_168;
+ volatile u32 DENALI_PI_169;
+ volatile u32 DENALI_PI_170;
+ volatile u32 DENALI_PI_171;
+ volatile u32 DENALI_PI_172;
+ volatile u32 DENALI_PI_173;
+ volatile u32 DENALI_PI_174;
+ volatile u32 DENALI_PI_175;
+ volatile u32 DENALI_PI_176;
+ volatile u32 DENALI_PI_177;
+ volatile u32 DENALI_PI_178;
+ volatile u32 DENALI_PI_179;
+ volatile u32 DENALI_PI_180;
+ volatile u32 DENALI_PI_181;
+ volatile u32 DENALI_PI_182;
+ volatile u32 DENALI_PI_183;
+ volatile u32 DENALI_PI_184;
+ volatile u32 DENALI_PI_185;
+ volatile u32 DENALI_PI_186;
+ volatile u32 DENALI_PI_187;
+ volatile u32 DENALI_PI_188;
+ volatile u32 DENALI_PI_189;
+ volatile u32 DENALI_PI_190;
+ volatile u32 DENALI_PI_191;
+ volatile u32 DENALI_PI_192;
+ volatile u32 DENALI_PI_193;
+ volatile u32 DENALI_PI_194;
+ volatile u32 DENALI_PI_195;
+ volatile u32 DENALI_PI_196;
+ volatile u32 DENALI_PI_197;
+ volatile u32 DENALI_PI_198;
+ volatile u32 DENALI_PI_199;
+ volatile u32 DENALI_PI_200;
+ volatile u32 DENALI_PI_201;
+ volatile u32 DENALI_PI_202;
+ volatile u32 DENALI_PI_203;
+ volatile u32 DENALI_PI_204;
+ volatile u32 DENALI_PI_205;
+ volatile u32 DENALI_PI_206;
+ volatile u32 DENALI_PI_207;
+ volatile u32 DENALI_PI_208;
+ volatile u32 DENALI_PI_209;
+ volatile u32 DENALI_PI_210;
+ volatile u32 DENALI_PI_211;
+ volatile u32 DENALI_PI_212;
+ volatile u32 DENALI_PI_213;
+ volatile u32 DENALI_PI_214;
+ volatile u32 DENALI_PI_215;
+ volatile u32 DENALI_PI_216;
+ volatile u32 DENALI_PI_217;
+ volatile u32 DENALI_PI_218;
+ volatile u32 DENALI_PI_219;
+ volatile u32 DENALI_PI_220;
+ volatile u32 DENALI_PI_221;
+ volatile u32 DENALI_PI_222;
+ volatile u32 DENALI_PI_223;
+ volatile u32 DENALI_PI_224;
+ volatile u32 DENALI_PI_225;
+ volatile u32 DENALI_PI_226;
+ volatile u32 DENALI_PI_227;
+ volatile u32 DENALI_PI_228;
+ volatile u32 DENALI_PI_229;
+ volatile u32 DENALI_PI_230;
+ volatile u32 DENALI_PI_231;
+ volatile u32 DENALI_PI_232;
+ volatile u32 DENALI_PI_233;
+ volatile u32 DENALI_PI_234;
+ volatile u32 DENALI_PI_235;
+ volatile u32 DENALI_PI_236;
+ volatile u32 DENALI_PI_237;
+ volatile u32 DENALI_PI_238;
+ volatile u32 DENALI_PI_239;
+ volatile u32 DENALI_PI_240;
+ volatile u32 DENALI_PI_241;
+ volatile u32 DENALI_PI_242;
+ volatile u32 DENALI_PI_243;
+ volatile u32 DENALI_PI_244;
+ volatile u32 DENALI_PI_245;
+ volatile u32 DENALI_PI_246;
+ volatile u32 DENALI_PI_247;
+ volatile u32 DENALI_PI_248;
+ volatile u32 DENALI_PI_249;
+ volatile u32 DENALI_PI_250;
+ volatile u32 DENALI_PI_251;
+ volatile u32 DENALI_PI_252;
+ volatile u32 DENALI_PI_253;
+ volatile u32 DENALI_PI_254;
+ volatile u32 DENALI_PI_255;
+ volatile u32 DENALI_PI_256;
+ volatile u32 DENALI_PI_257;
+ volatile u32 DENALI_PI_258;
+ volatile u32 DENALI_PI_259;
+ volatile u32 DENALI_PI_260;
+ volatile u32 DENALI_PI_261;
+ volatile u32 DENALI_PI_262;
+ volatile u32 DENALI_PI_263;
+ volatile u32 DENALI_PI_264;
+ volatile u32 DENALI_PI_265;
+ volatile u32 DENALI_PI_266;
+ volatile u32 DENALI_PI_267;
+ volatile u32 DENALI_PI_268;
+ volatile u32 DENALI_PI_269;
+ volatile u32 DENALI_PI_270;
+ volatile u32 DENALI_PI_271;
+ volatile u32 DENALI_PI_272;
+ volatile u32 DENALI_PI_273;
+ volatile u32 DENALI_PI_274;
+ volatile u32 DENALI_PI_275;
+ volatile u32 DENALI_PI_276;
+ volatile u32 DENALI_PI_277;
+ volatile u32 DENALI_PI_278;
+ volatile u32 DENALI_PI_279;
+ volatile u32 DENALI_PI_280;
+ volatile u32 DENALI_PI_281;
+ volatile u32 DENALI_PI_282;
+ volatile u32 DENALI_PI_283;
+ volatile u32 DENALI_PI_284;
+ volatile u32 DENALI_PI_285;
+ volatile u32 DENALI_PI_286;
+ volatile u32 DENALI_PI_287;
+ volatile u32 DENALI_PI_288;
+ volatile u32 DENALI_PI_289;
+ volatile u32 DENALI_PI_290;
+ volatile u32 DENALI_PI_291;
+ volatile u32 DENALI_PI_292;
+ volatile u32 DENALI_PI_293;
+ volatile u32 DENALI_PI_294;
+ volatile u32 DENALI_PI_295;
+ volatile u32 DENALI_PI_296;
+ volatile u32 DENALI_PI_297;
+ volatile u32 DENALI_PI_298;
+ volatile u32 DENALI_PI_299;
+ volatile u32 DENALI_PI_300;
+ volatile u32 DENALI_PI_301;
+ volatile u32 DENALI_PI_302;
+ volatile u32 DENALI_PI_303;
+ volatile u32 DENALI_PI_304;
+ volatile u32 DENALI_PI_305;
+ volatile u32 DENALI_PI_306;
+ volatile u32 DENALI_PI_307;
+ volatile u32 DENALI_PI_308;
+ volatile u32 DENALI_PI_309;
+ volatile u32 DENALI_PI_310;
+ volatile u32 DENALI_PI_311;
+ volatile u32 DENALI_PI_312;
+ volatile u32 DENALI_PI_313;
+ volatile u32 DENALI_PI_314;
+ volatile u32 DENALI_PI_315;
+ volatile u32 DENALI_PI_316;
+ volatile u32 DENALI_PI_317;
+ volatile u32 DENALI_PI_318;
+ volatile u32 DENALI_PI_319;
+ volatile u32 DENALI_PI_320;
+ volatile u32 DENALI_PI_321;
+ volatile u32 DENALI_PI_322;
+ volatile u32 DENALI_PI_323;
+ volatile u32 DENALI_PI_324;
+ volatile u32 DENALI_PI_325;
+ volatile u32 DENALI_PI_326;
+ volatile u32 DENALI_PI_327;
+ volatile u32 DENALI_PI_328;
+ volatile u32 DENALI_PI_329;
+ volatile u32 DENALI_PI_330;
+ volatile u32 DENALI_PI_331;
+ volatile u32 DENALI_PI_332;
+ volatile u32 DENALI_PI_333;
+ volatile u32 DENALI_PI_334;
+ volatile u32 DENALI_PI_335;
+ volatile u32 DENALI_PI_336;
+ volatile u32 DENALI_PI_337;
+ volatile u32 DENALI_PI_338;
+ volatile u32 DENALI_PI_339;
+ volatile u32 DENALI_PI_340;
+ volatile u32 DENALI_PI_341;
+ volatile u32 DENALI_PI_342;
+ volatile u32 DENALI_PI_343;
+ volatile u32 DENALI_PI_344;
+ volatile u32 DENALI_PI_345;
+ volatile u32 DENALI_PI_346;
+ volatile u32 DENALI_PI_347;
+ volatile u32 DENALI_PI_348;
+ volatile u32 DENALI_PI_349;
+ volatile u32 DENALI_PI_350;
+ volatile u32 DENALI_PI_351;
+ volatile u32 DENALI_PI_352;
+ volatile u32 DENALI_PI_353;
+ volatile u32 DENALI_PI_354;
+ volatile u32 DENALI_PI_355;
+ volatile u32 DENALI_PI_356;
+ volatile u32 DENALI_PI_357;
+ volatile u32 DENALI_PI_358;
+ volatile u32 DENALI_PI_359;
+ volatile u32 DENALI_PI_360;
+ volatile u32 DENALI_PI_361;
+ volatile u32 DENALI_PI_362;
+ volatile u32 DENALI_PI_363;
+ volatile u32 DENALI_PI_364;
+ volatile u32 DENALI_PI_365;
+ volatile u32 DENALI_PI_366;
+ volatile u32 DENALI_PI_367;
+ volatile u32 DENALI_PI_368;
+ volatile u32 DENALI_PI_369;
+ volatile u32 DENALI_PI_370;
+ volatile u32 DENALI_PI_371;
+ volatile u32 DENALI_PI_372;
+ volatile u32 DENALI_PI_373;
+ volatile u32 DENALI_PI_374;
+ volatile u32 DENALI_PI_375;
+ volatile u32 DENALI_PI_376;
+ volatile u32 DENALI_PI_377;
+ volatile u32 DENALI_PI_378;
+ volatile u32 DENALI_PI_379;
+ volatile u32 DENALI_PI_380;
+ volatile u32 DENALI_PI_381;
+ volatile u32 DENALI_PI_382;
+ volatile u32 DENALI_PI_383;
+ volatile u32 DENALI_PI_384;
+ volatile u32 DENALI_PI_385;
+ volatile u32 DENALI_PI_386;
+ volatile u32 DENALI_PI_387;
+ volatile u32 DENALI_PI_388;
+ volatile u32 DENALI_PI_389;
+ volatile u32 DENALI_PI_390;
+ volatile u32 DENALI_PI_391;
+ volatile u32 DENALI_PI_392;
+ volatile u32 DENALI_PI_393;
+ volatile u32 DENALI_PI_394;
+ volatile u32 DENALI_PI_395;
+ volatile u32 DENALI_PI_396;
+ volatile u32 DENALI_PI_397;
+ volatile u32 DENALI_PI_398;
+ volatile u32 DENALI_PI_399;
+ volatile u32 DENALI_PI_400;
+ volatile u32 DENALI_PI_401;
+ volatile u32 DENALI_PI_402;
+ volatile u32 DENALI_PI_403;
+ volatile u32 DENALI_PI_404;
+ volatile u32 DENALI_PI_405;
+ volatile u32 DENALI_PI_406;
+ volatile u32 DENALI_PI_407;
+ volatile u32 DENALI_PI_408;
+ volatile u32 DENALI_PI_409;
+ volatile u32 DENALI_PI_410;
+ volatile u32 DENALI_PI_411;
+ volatile u32 DENALI_PI_412;
+ volatile u32 DENALI_PI_413;
+ volatile u32 DENALI_PI_414;
+ volatile u32 DENALI_PI_415;
+ volatile u32 DENALI_PI_416;
+ volatile u32 DENALI_PI_417;
+ volatile u32 DENALI_PI_418;
+ volatile u32 DENALI_PI_419;
+ volatile u32 DENALI_PI_420;
+ volatile u32 DENALI_PI_421;
+ volatile u32 DENALI_PI_422;
+ volatile u32 DENALI_PI_423;
+ volatile char pad__1[0x1960U];
+ volatile u32 DENALI_PHY_0;
+ volatile u32 DENALI_PHY_1;
+ volatile u32 DENALI_PHY_2;
+ volatile u32 DENALI_PHY_3;
+ volatile u32 DENALI_PHY_4;
+ volatile u32 DENALI_PHY_5;
+ volatile u32 DENALI_PHY_6;
+ volatile u32 DENALI_PHY_7;
+ volatile u32 DENALI_PHY_8;
+ volatile u32 DENALI_PHY_9;
+ volatile u32 DENALI_PHY_10;
+ volatile u32 DENALI_PHY_11;
+ volatile u32 DENALI_PHY_12;
+ volatile u32 DENALI_PHY_13;
+ volatile u32 DENALI_PHY_14;
+ volatile u32 DENALI_PHY_15;
+ volatile u32 DENALI_PHY_16;
+ volatile u32 DENALI_PHY_17;
+ volatile u32 DENALI_PHY_18;
+ volatile u32 DENALI_PHY_19;
+ volatile u32 DENALI_PHY_20;
+ volatile u32 DENALI_PHY_21;
+ volatile u32 DENALI_PHY_22;
+ volatile u32 DENALI_PHY_23;
+ volatile u32 DENALI_PHY_24;
+ volatile u32 DENALI_PHY_25;
+ volatile u32 DENALI_PHY_26;
+ volatile u32 DENALI_PHY_27;
+ volatile u32 DENALI_PHY_28;
+ volatile u32 DENALI_PHY_29;
+ volatile u32 DENALI_PHY_30;
+ volatile u32 DENALI_PHY_31;
+ volatile u32 DENALI_PHY_32;
+ volatile u32 DENALI_PHY_33;
+ volatile u32 DENALI_PHY_34;
+ volatile u32 DENALI_PHY_35;
+ volatile u32 DENALI_PHY_36;
+ volatile u32 DENALI_PHY_37;
+ volatile u32 DENALI_PHY_38;
+ volatile u32 DENALI_PHY_39;
+ volatile u32 DENALI_PHY_40;
+ volatile u32 DENALI_PHY_41;
+ volatile u32 DENALI_PHY_42;
+ volatile u32 DENALI_PHY_43;
+ volatile u32 DENALI_PHY_44;
+ volatile u32 DENALI_PHY_45;
+ volatile u32 DENALI_PHY_46;
+ volatile u32 DENALI_PHY_47;
+ volatile u32 DENALI_PHY_48;
+ volatile u32 DENALI_PHY_49;
+ volatile u32 DENALI_PHY_50;
+ volatile u32 DENALI_PHY_51;
+ volatile u32 DENALI_PHY_52;
+ volatile u32 DENALI_PHY_53;
+ volatile u32 DENALI_PHY_54;
+ volatile u32 DENALI_PHY_55;
+ volatile u32 DENALI_PHY_56;
+ volatile u32 DENALI_PHY_57;
+ volatile u32 DENALI_PHY_58;
+ volatile u32 DENALI_PHY_59;
+ volatile u32 DENALI_PHY_60;
+ volatile u32 DENALI_PHY_61;
+ volatile u32 DENALI_PHY_62;
+ volatile u32 DENALI_PHY_63;
+ volatile u32 DENALI_PHY_64;
+ volatile u32 DENALI_PHY_65;
+ volatile u32 DENALI_PHY_66;
+ volatile u32 DENALI_PHY_67;
+ volatile u32 DENALI_PHY_68;
+ volatile u32 DENALI_PHY_69;
+ volatile u32 DENALI_PHY_70;
+ volatile u32 DENALI_PHY_71;
+ volatile u32 DENALI_PHY_72;
+ volatile u32 DENALI_PHY_73;
+ volatile u32 DENALI_PHY_74;
+ volatile u32 DENALI_PHY_75;
+ volatile u32 DENALI_PHY_76;
+ volatile u32 DENALI_PHY_77;
+ volatile u32 DENALI_PHY_78;
+ volatile u32 DENALI_PHY_79;
+ volatile u32 DENALI_PHY_80;
+ volatile u32 DENALI_PHY_81;
+ volatile u32 DENALI_PHY_82;
+ volatile u32 DENALI_PHY_83;
+ volatile u32 DENALI_PHY_84;
+ volatile u32 DENALI_PHY_85;
+ volatile u32 DENALI_PHY_86;
+ volatile u32 DENALI_PHY_87;
+ volatile u32 DENALI_PHY_88;
+ volatile u32 DENALI_PHY_89;
+ volatile u32 DENALI_PHY_90;
+ volatile u32 DENALI_PHY_91;
+ volatile u32 DENALI_PHY_92;
+ volatile u32 DENALI_PHY_93;
+ volatile u32 DENALI_PHY_94;
+ volatile u32 DENALI_PHY_95;
+ volatile u32 DENALI_PHY_96;
+ volatile u32 DENALI_PHY_97;
+ volatile u32 DENALI_PHY_98;
+ volatile u32 DENALI_PHY_99;
+ volatile u32 DENALI_PHY_100;
+ volatile u32 DENALI_PHY_101;
+ volatile u32 DENALI_PHY_102;
+ volatile u32 DENALI_PHY_103;
+ volatile u32 DENALI_PHY_104;
+ volatile u32 DENALI_PHY_105;
+ volatile u32 DENALI_PHY_106;
+ volatile u32 DENALI_PHY_107;
+ volatile u32 DENALI_PHY_108;
+ volatile u32 DENALI_PHY_109;
+ volatile u32 DENALI_PHY_110;
+ volatile u32 DENALI_PHY_111;
+ volatile u32 DENALI_PHY_112;
+ volatile u32 DENALI_PHY_113;
+ volatile u32 DENALI_PHY_114;
+ volatile u32 DENALI_PHY_115;
+ volatile u32 DENALI_PHY_116;
+ volatile u32 DENALI_PHY_117;
+ volatile u32 DENALI_PHY_118;
+ volatile u32 DENALI_PHY_119;
+ volatile u32 DENALI_PHY_120;
+ volatile u32 DENALI_PHY_121;
+ volatile u32 DENALI_PHY_122;
+ volatile u32 DENALI_PHY_123;
+ volatile u32 DENALI_PHY_124;
+ volatile u32 DENALI_PHY_125;
+ volatile u32 DENALI_PHY_126;
+ volatile u32 DENALI_PHY_127;
+ volatile u32 DENALI_PHY_128;
+ volatile u32 DENALI_PHY_129;
+ volatile u32 DENALI_PHY_130;
+ volatile u32 DENALI_PHY_131;
+ volatile u32 DENALI_PHY_132;
+ volatile u32 DENALI_PHY_133;
+ volatile u32 DENALI_PHY_134;
+ volatile u32 DENALI_PHY_135;
+ volatile u32 DENALI_PHY_136;
+ volatile char pad__2[0x1DCU];
+ volatile u32 DENALI_PHY_256;
+ volatile u32 DENALI_PHY_257;
+ volatile u32 DENALI_PHY_258;
+ volatile u32 DENALI_PHY_259;
+ volatile u32 DENALI_PHY_260;
+ volatile u32 DENALI_PHY_261;
+ volatile u32 DENALI_PHY_262;
+ volatile u32 DENALI_PHY_263;
+ volatile u32 DENALI_PHY_264;
+ volatile u32 DENALI_PHY_265;
+ volatile u32 DENALI_PHY_266;
+ volatile u32 DENALI_PHY_267;
+ volatile u32 DENALI_PHY_268;
+ volatile u32 DENALI_PHY_269;
+ volatile u32 DENALI_PHY_270;
+ volatile u32 DENALI_PHY_271;
+ volatile u32 DENALI_PHY_272;
+ volatile u32 DENALI_PHY_273;
+ volatile u32 DENALI_PHY_274;
+ volatile u32 DENALI_PHY_275;
+ volatile u32 DENALI_PHY_276;
+ volatile u32 DENALI_PHY_277;
+ volatile u32 DENALI_PHY_278;
+ volatile u32 DENALI_PHY_279;
+ volatile u32 DENALI_PHY_280;
+ volatile u32 DENALI_PHY_281;
+ volatile u32 DENALI_PHY_282;
+ volatile u32 DENALI_PHY_283;
+ volatile u32 DENALI_PHY_284;
+ volatile u32 DENALI_PHY_285;
+ volatile u32 DENALI_PHY_286;
+ volatile u32 DENALI_PHY_287;
+ volatile u32 DENALI_PHY_288;
+ volatile u32 DENALI_PHY_289;
+ volatile u32 DENALI_PHY_290;
+ volatile u32 DENALI_PHY_291;
+ volatile u32 DENALI_PHY_292;
+ volatile u32 DENALI_PHY_293;
+ volatile u32 DENALI_PHY_294;
+ volatile u32 DENALI_PHY_295;
+ volatile u32 DENALI_PHY_296;
+ volatile u32 DENALI_PHY_297;
+ volatile u32 DENALI_PHY_298;
+ volatile u32 DENALI_PHY_299;
+ volatile u32 DENALI_PHY_300;
+ volatile u32 DENALI_PHY_301;
+ volatile u32 DENALI_PHY_302;
+ volatile u32 DENALI_PHY_303;
+ volatile u32 DENALI_PHY_304;
+ volatile u32 DENALI_PHY_305;
+ volatile u32 DENALI_PHY_306;
+ volatile u32 DENALI_PHY_307;
+ volatile u32 DENALI_PHY_308;
+ volatile u32 DENALI_PHY_309;
+ volatile u32 DENALI_PHY_310;
+ volatile u32 DENALI_PHY_311;
+ volatile u32 DENALI_PHY_312;
+ volatile u32 DENALI_PHY_313;
+ volatile u32 DENALI_PHY_314;
+ volatile u32 DENALI_PHY_315;
+ volatile u32 DENALI_PHY_316;
+ volatile u32 DENALI_PHY_317;
+ volatile u32 DENALI_PHY_318;
+ volatile u32 DENALI_PHY_319;
+ volatile u32 DENALI_PHY_320;
+ volatile u32 DENALI_PHY_321;
+ volatile u32 DENALI_PHY_322;
+ volatile u32 DENALI_PHY_323;
+ volatile u32 DENALI_PHY_324;
+ volatile u32 DENALI_PHY_325;
+ volatile u32 DENALI_PHY_326;
+ volatile u32 DENALI_PHY_327;
+ volatile u32 DENALI_PHY_328;
+ volatile u32 DENALI_PHY_329;
+ volatile u32 DENALI_PHY_330;
+ volatile u32 DENALI_PHY_331;
+ volatile u32 DENALI_PHY_332;
+ volatile u32 DENALI_PHY_333;
+ volatile u32 DENALI_PHY_334;
+ volatile u32 DENALI_PHY_335;
+ volatile u32 DENALI_PHY_336;
+ volatile u32 DENALI_PHY_337;
+ volatile u32 DENALI_PHY_338;
+ volatile u32 DENALI_PHY_339;
+ volatile u32 DENALI_PHY_340;
+ volatile u32 DENALI_PHY_341;
+ volatile u32 DENALI_PHY_342;
+ volatile u32 DENALI_PHY_343;
+ volatile u32 DENALI_PHY_344;
+ volatile u32 DENALI_PHY_345;
+ volatile u32 DENALI_PHY_346;
+ volatile u32 DENALI_PHY_347;
+ volatile u32 DENALI_PHY_348;
+ volatile u32 DENALI_PHY_349;
+ volatile u32 DENALI_PHY_350;
+ volatile u32 DENALI_PHY_351;
+ volatile u32 DENALI_PHY_352;
+ volatile u32 DENALI_PHY_353;
+ volatile u32 DENALI_PHY_354;
+ volatile u32 DENALI_PHY_355;
+ volatile u32 DENALI_PHY_356;
+ volatile u32 DENALI_PHY_357;
+ volatile u32 DENALI_PHY_358;
+ volatile u32 DENALI_PHY_359;
+ volatile u32 DENALI_PHY_360;
+ volatile u32 DENALI_PHY_361;
+ volatile u32 DENALI_PHY_362;
+ volatile u32 DENALI_PHY_363;
+ volatile u32 DENALI_PHY_364;
+ volatile u32 DENALI_PHY_365;
+ volatile u32 DENALI_PHY_366;
+ volatile u32 DENALI_PHY_367;
+ volatile u32 DENALI_PHY_368;
+ volatile u32 DENALI_PHY_369;
+ volatile u32 DENALI_PHY_370;
+ volatile u32 DENALI_PHY_371;
+ volatile u32 DENALI_PHY_372;
+ volatile u32 DENALI_PHY_373;
+ volatile u32 DENALI_PHY_374;
+ volatile u32 DENALI_PHY_375;
+ volatile u32 DENALI_PHY_376;
+ volatile u32 DENALI_PHY_377;
+ volatile u32 DENALI_PHY_378;
+ volatile u32 DENALI_PHY_379;
+ volatile u32 DENALI_PHY_380;
+ volatile u32 DENALI_PHY_381;
+ volatile u32 DENALI_PHY_382;
+ volatile u32 DENALI_PHY_383;
+ volatile u32 DENALI_PHY_384;
+ volatile u32 DENALI_PHY_385;
+ volatile u32 DENALI_PHY_386;
+ volatile u32 DENALI_PHY_387;
+ volatile u32 DENALI_PHY_388;
+ volatile u32 DENALI_PHY_389;
+ volatile u32 DENALI_PHY_390;
+ volatile u32 DENALI_PHY_391;
+ volatile u32 DENALI_PHY_392;
+ volatile char pad__3[0x1DCU];
+ volatile u32 DENALI_PHY_512;
+ volatile u32 DENALI_PHY_513;
+ volatile u32 DENALI_PHY_514;
+ volatile u32 DENALI_PHY_515;
+ volatile u32 DENALI_PHY_516;
+ volatile u32 DENALI_PHY_517;
+ volatile u32 DENALI_PHY_518;
+ volatile u32 DENALI_PHY_519;
+ volatile u32 DENALI_PHY_520;
+ volatile u32 DENALI_PHY_521;
+ volatile u32 DENALI_PHY_522;
+ volatile u32 DENALI_PHY_523;
+ volatile u32 DENALI_PHY_524;
+ volatile u32 DENALI_PHY_525;
+ volatile u32 DENALI_PHY_526;
+ volatile u32 DENALI_PHY_527;
+ volatile u32 DENALI_PHY_528;
+ volatile u32 DENALI_PHY_529;
+ volatile u32 DENALI_PHY_530;
+ volatile u32 DENALI_PHY_531;
+ volatile u32 DENALI_PHY_532;
+ volatile u32 DENALI_PHY_533;
+ volatile u32 DENALI_PHY_534;
+ volatile u32 DENALI_PHY_535;
+ volatile u32 DENALI_PHY_536;
+ volatile u32 DENALI_PHY_537;
+ volatile u32 DENALI_PHY_538;
+ volatile u32 DENALI_PHY_539;
+ volatile u32 DENALI_PHY_540;
+ volatile u32 DENALI_PHY_541;
+ volatile u32 DENALI_PHY_542;
+ volatile u32 DENALI_PHY_543;
+ volatile u32 DENALI_PHY_544;
+ volatile u32 DENALI_PHY_545;
+ volatile u32 DENALI_PHY_546;
+ volatile u32 DENALI_PHY_547;
+ volatile u32 DENALI_PHY_548;
+ volatile u32 DENALI_PHY_549;
+ volatile u32 DENALI_PHY_550;
+ volatile u32 DENALI_PHY_551;
+ volatile u32 DENALI_PHY_552;
+ volatile u32 DENALI_PHY_553;
+ volatile u32 DENALI_PHY_554;
+ volatile u32 DENALI_PHY_555;
+ volatile u32 DENALI_PHY_556;
+ volatile u32 DENALI_PHY_557;
+ volatile u32 DENALI_PHY_558;
+ volatile u32 DENALI_PHY_559;
+ volatile u32 DENALI_PHY_560;
+ volatile u32 DENALI_PHY_561;
+ volatile u32 DENALI_PHY_562;
+ volatile u32 DENALI_PHY_563;
+ volatile u32 DENALI_PHY_564;
+ volatile u32 DENALI_PHY_565;
+ volatile u32 DENALI_PHY_566;
+ volatile u32 DENALI_PHY_567;
+ volatile u32 DENALI_PHY_568;
+ volatile u32 DENALI_PHY_569;
+ volatile u32 DENALI_PHY_570;
+ volatile u32 DENALI_PHY_571;
+ volatile u32 DENALI_PHY_572;
+ volatile u32 DENALI_PHY_573;
+ volatile u32 DENALI_PHY_574;
+ volatile u32 DENALI_PHY_575;
+ volatile u32 DENALI_PHY_576;
+ volatile u32 DENALI_PHY_577;
+ volatile u32 DENALI_PHY_578;
+ volatile u32 DENALI_PHY_579;
+ volatile u32 DENALI_PHY_580;
+ volatile u32 DENALI_PHY_581;
+ volatile u32 DENALI_PHY_582;
+ volatile u32 DENALI_PHY_583;
+ volatile u32 DENALI_PHY_584;
+ volatile u32 DENALI_PHY_585;
+ volatile u32 DENALI_PHY_586;
+ volatile u32 DENALI_PHY_587;
+ volatile u32 DENALI_PHY_588;
+ volatile u32 DENALI_PHY_589;
+ volatile u32 DENALI_PHY_590;
+ volatile u32 DENALI_PHY_591;
+ volatile u32 DENALI_PHY_592;
+ volatile u32 DENALI_PHY_593;
+ volatile u32 DENALI_PHY_594;
+ volatile u32 DENALI_PHY_595;
+ volatile u32 DENALI_PHY_596;
+ volatile u32 DENALI_PHY_597;
+ volatile u32 DENALI_PHY_598;
+ volatile u32 DENALI_PHY_599;
+ volatile u32 DENALI_PHY_600;
+ volatile u32 DENALI_PHY_601;
+ volatile u32 DENALI_PHY_602;
+ volatile u32 DENALI_PHY_603;
+ volatile u32 DENALI_PHY_604;
+ volatile u32 DENALI_PHY_605;
+ volatile u32 DENALI_PHY_606;
+ volatile u32 DENALI_PHY_607;
+ volatile u32 DENALI_PHY_608;
+ volatile u32 DENALI_PHY_609;
+ volatile u32 DENALI_PHY_610;
+ volatile u32 DENALI_PHY_611;
+ volatile u32 DENALI_PHY_612;
+ volatile u32 DENALI_PHY_613;
+ volatile u32 DENALI_PHY_614;
+ volatile u32 DENALI_PHY_615;
+ volatile u32 DENALI_PHY_616;
+ volatile u32 DENALI_PHY_617;
+ volatile u32 DENALI_PHY_618;
+ volatile u32 DENALI_PHY_619;
+ volatile u32 DENALI_PHY_620;
+ volatile u32 DENALI_PHY_621;
+ volatile u32 DENALI_PHY_622;
+ volatile u32 DENALI_PHY_623;
+ volatile u32 DENALI_PHY_624;
+ volatile u32 DENALI_PHY_625;
+ volatile u32 DENALI_PHY_626;
+ volatile u32 DENALI_PHY_627;
+ volatile u32 DENALI_PHY_628;
+ volatile u32 DENALI_PHY_629;
+ volatile u32 DENALI_PHY_630;
+ volatile u32 DENALI_PHY_631;
+ volatile u32 DENALI_PHY_632;
+ volatile u32 DENALI_PHY_633;
+ volatile u32 DENALI_PHY_634;
+ volatile u32 DENALI_PHY_635;
+ volatile u32 DENALI_PHY_636;
+ volatile u32 DENALI_PHY_637;
+ volatile u32 DENALI_PHY_638;
+ volatile u32 DENALI_PHY_639;
+ volatile u32 DENALI_PHY_640;
+ volatile u32 DENALI_PHY_641;
+ volatile u32 DENALI_PHY_642;
+ volatile u32 DENALI_PHY_643;
+ volatile u32 DENALI_PHY_644;
+ volatile u32 DENALI_PHY_645;
+ volatile u32 DENALI_PHY_646;
+ volatile u32 DENALI_PHY_647;
+ volatile u32 DENALI_PHY_648;
+ volatile char pad__4[0x1DCU];
+ volatile u32 DENALI_PHY_768;
+ volatile u32 DENALI_PHY_769;
+ volatile u32 DENALI_PHY_770;
+ volatile u32 DENALI_PHY_771;
+ volatile u32 DENALI_PHY_772;
+ volatile u32 DENALI_PHY_773;
+ volatile u32 DENALI_PHY_774;
+ volatile u32 DENALI_PHY_775;
+ volatile u32 DENALI_PHY_776;
+ volatile u32 DENALI_PHY_777;
+ volatile u32 DENALI_PHY_778;
+ volatile u32 DENALI_PHY_779;
+ volatile u32 DENALI_PHY_780;
+ volatile u32 DENALI_PHY_781;
+ volatile u32 DENALI_PHY_782;
+ volatile u32 DENALI_PHY_783;
+ volatile u32 DENALI_PHY_784;
+ volatile u32 DENALI_PHY_785;
+ volatile u32 DENALI_PHY_786;
+ volatile u32 DENALI_PHY_787;
+ volatile u32 DENALI_PHY_788;
+ volatile u32 DENALI_PHY_789;
+ volatile u32 DENALI_PHY_790;
+ volatile u32 DENALI_PHY_791;
+ volatile u32 DENALI_PHY_792;
+ volatile u32 DENALI_PHY_793;
+ volatile u32 DENALI_PHY_794;
+ volatile u32 DENALI_PHY_795;
+ volatile u32 DENALI_PHY_796;
+ volatile u32 DENALI_PHY_797;
+ volatile u32 DENALI_PHY_798;
+ volatile u32 DENALI_PHY_799;
+ volatile u32 DENALI_PHY_800;
+ volatile u32 DENALI_PHY_801;
+ volatile u32 DENALI_PHY_802;
+ volatile u32 DENALI_PHY_803;
+ volatile u32 DENALI_PHY_804;
+ volatile u32 DENALI_PHY_805;
+ volatile u32 DENALI_PHY_806;
+ volatile u32 DENALI_PHY_807;
+ volatile u32 DENALI_PHY_808;
+ volatile u32 DENALI_PHY_809;
+ volatile u32 DENALI_PHY_810;
+ volatile u32 DENALI_PHY_811;
+ volatile u32 DENALI_PHY_812;
+ volatile u32 DENALI_PHY_813;
+ volatile u32 DENALI_PHY_814;
+ volatile u32 DENALI_PHY_815;
+ volatile u32 DENALI_PHY_816;
+ volatile u32 DENALI_PHY_817;
+ volatile u32 DENALI_PHY_818;
+ volatile u32 DENALI_PHY_819;
+ volatile u32 DENALI_PHY_820;
+ volatile u32 DENALI_PHY_821;
+ volatile u32 DENALI_PHY_822;
+ volatile u32 DENALI_PHY_823;
+ volatile u32 DENALI_PHY_824;
+ volatile u32 DENALI_PHY_825;
+ volatile u32 DENALI_PHY_826;
+ volatile u32 DENALI_PHY_827;
+ volatile u32 DENALI_PHY_828;
+ volatile u32 DENALI_PHY_829;
+ volatile u32 DENALI_PHY_830;
+ volatile u32 DENALI_PHY_831;
+ volatile u32 DENALI_PHY_832;
+ volatile u32 DENALI_PHY_833;
+ volatile u32 DENALI_PHY_834;
+ volatile u32 DENALI_PHY_835;
+ volatile u32 DENALI_PHY_836;
+ volatile u32 DENALI_PHY_837;
+ volatile u32 DENALI_PHY_838;
+ volatile u32 DENALI_PHY_839;
+ volatile u32 DENALI_PHY_840;
+ volatile u32 DENALI_PHY_841;
+ volatile u32 DENALI_PHY_842;
+ volatile u32 DENALI_PHY_843;
+ volatile u32 DENALI_PHY_844;
+ volatile u32 DENALI_PHY_845;
+ volatile u32 DENALI_PHY_846;
+ volatile u32 DENALI_PHY_847;
+ volatile u32 DENALI_PHY_848;
+ volatile u32 DENALI_PHY_849;
+ volatile u32 DENALI_PHY_850;
+ volatile u32 DENALI_PHY_851;
+ volatile u32 DENALI_PHY_852;
+ volatile u32 DENALI_PHY_853;
+ volatile u32 DENALI_PHY_854;
+ volatile u32 DENALI_PHY_855;
+ volatile u32 DENALI_PHY_856;
+ volatile u32 DENALI_PHY_857;
+ volatile u32 DENALI_PHY_858;
+ volatile u32 DENALI_PHY_859;
+ volatile u32 DENALI_PHY_860;
+ volatile u32 DENALI_PHY_861;
+ volatile u32 DENALI_PHY_862;
+ volatile u32 DENALI_PHY_863;
+ volatile u32 DENALI_PHY_864;
+ volatile u32 DENALI_PHY_865;
+ volatile u32 DENALI_PHY_866;
+ volatile u32 DENALI_PHY_867;
+ volatile u32 DENALI_PHY_868;
+ volatile u32 DENALI_PHY_869;
+ volatile u32 DENALI_PHY_870;
+ volatile u32 DENALI_PHY_871;
+ volatile u32 DENALI_PHY_872;
+ volatile u32 DENALI_PHY_873;
+ volatile u32 DENALI_PHY_874;
+ volatile u32 DENALI_PHY_875;
+ volatile u32 DENALI_PHY_876;
+ volatile u32 DENALI_PHY_877;
+ volatile u32 DENALI_PHY_878;
+ volatile u32 DENALI_PHY_879;
+ volatile u32 DENALI_PHY_880;
+ volatile u32 DENALI_PHY_881;
+ volatile u32 DENALI_PHY_882;
+ volatile u32 DENALI_PHY_883;
+ volatile u32 DENALI_PHY_884;
+ volatile u32 DENALI_PHY_885;
+ volatile u32 DENALI_PHY_886;
+ volatile u32 DENALI_PHY_887;
+ volatile u32 DENALI_PHY_888;
+ volatile u32 DENALI_PHY_889;
+ volatile u32 DENALI_PHY_890;
+ volatile u32 DENALI_PHY_891;
+ volatile u32 DENALI_PHY_892;
+ volatile u32 DENALI_PHY_893;
+ volatile u32 DENALI_PHY_894;
+ volatile u32 DENALI_PHY_895;
+ volatile u32 DENALI_PHY_896;
+ volatile u32 DENALI_PHY_897;
+ volatile u32 DENALI_PHY_898;
+ volatile u32 DENALI_PHY_899;
+ volatile u32 DENALI_PHY_900;
+ volatile u32 DENALI_PHY_901;
+ volatile u32 DENALI_PHY_902;
+ volatile u32 DENALI_PHY_903;
+ volatile u32 DENALI_PHY_904;
+ volatile char pad__5[0x1DCU];
+ volatile u32 DENALI_PHY_1024;
+ volatile u32 DENALI_PHY_1025;
+ volatile u32 DENALI_PHY_1026;
+ volatile u32 DENALI_PHY_1027;
+ volatile u32 DENALI_PHY_1028;
+ volatile u32 DENALI_PHY_1029;
+ volatile u32 DENALI_PHY_1030;
+ volatile u32 DENALI_PHY_1031;
+ volatile u32 DENALI_PHY_1032;
+ volatile u32 DENALI_PHY_1033;
+ volatile u32 DENALI_PHY_1034;
+ volatile u32 DENALI_PHY_1035;
+ volatile u32 DENALI_PHY_1036;
+ volatile u32 DENALI_PHY_1037;
+ volatile u32 DENALI_PHY_1038;
+ volatile u32 DENALI_PHY_1039;
+ volatile u32 DENALI_PHY_1040;
+ volatile u32 DENALI_PHY_1041;
+ volatile u32 DENALI_PHY_1042;
+ volatile u32 DENALI_PHY_1043;
+ volatile u32 DENALI_PHY_1044;
+ volatile u32 DENALI_PHY_1045;
+ volatile u32 DENALI_PHY_1046;
+ volatile u32 DENALI_PHY_1047;
+ volatile u32 DENALI_PHY_1048;
+ volatile u32 DENALI_PHY_1049;
+ volatile u32 DENALI_PHY_1050;
+ volatile u32 DENALI_PHY_1051;
+ volatile u32 DENALI_PHY_1052;
+ volatile u32 DENALI_PHY_1053;
+ volatile u32 DENALI_PHY_1054;
+ volatile u32 DENALI_PHY_1055;
+ volatile u32 DENALI_PHY_1056;
+ volatile u32 DENALI_PHY_1057;
+ volatile u32 DENALI_PHY_1058;
+ volatile u32 DENALI_PHY_1059;
+ volatile u32 DENALI_PHY_1060;
+ volatile u32 DENALI_PHY_1061;
+ volatile u32 DENALI_PHY_1062;
+ volatile u32 DENALI_PHY_1063;
+ volatile u32 DENALI_PHY_1064;
+ volatile u32 DENALI_PHY_1065;
+ volatile u32 DENALI_PHY_1066;
+ volatile u32 DENALI_PHY_1067;
+ volatile u32 DENALI_PHY_1068;
+ volatile u32 DENALI_PHY_1069;
+ volatile u32 DENALI_PHY_1070;
+ volatile u32 DENALI_PHY_1071;
+ volatile u32 DENALI_PHY_1072;
+ volatile char pad__6[0x33CU];
+ volatile u32 DENALI_PHY_1280;
+ volatile u32 DENALI_PHY_1281;
+ volatile u32 DENALI_PHY_1282;
+ volatile u32 DENALI_PHY_1283;
+ volatile u32 DENALI_PHY_1284;
+ volatile u32 DENALI_PHY_1285;
+ volatile u32 DENALI_PHY_1286;
+ volatile u32 DENALI_PHY_1287;
+ volatile u32 DENALI_PHY_1288;
+ volatile u32 DENALI_PHY_1289;
+ volatile u32 DENALI_PHY_1290;
+ volatile u32 DENALI_PHY_1291;
+ volatile u32 DENALI_PHY_1292;
+ volatile u32 DENALI_PHY_1293;
+ volatile u32 DENALI_PHY_1294;
+ volatile u32 DENALI_PHY_1295;
+ volatile u32 DENALI_PHY_1296;
+ volatile u32 DENALI_PHY_1297;
+ volatile u32 DENALI_PHY_1298;
+ volatile u32 DENALI_PHY_1299;
+ volatile u32 DENALI_PHY_1300;
+ volatile u32 DENALI_PHY_1301;
+ volatile u32 DENALI_PHY_1302;
+ volatile u32 DENALI_PHY_1303;
+ volatile u32 DENALI_PHY_1304;
+ volatile u32 DENALI_PHY_1305;
+ volatile u32 DENALI_PHY_1306;
+ volatile u32 DENALI_PHY_1307;
+ volatile u32 DENALI_PHY_1308;
+ volatile u32 DENALI_PHY_1309;
+ volatile u32 DENALI_PHY_1310;
+ volatile u32 DENALI_PHY_1311;
+ volatile u32 DENALI_PHY_1312;
+ volatile u32 DENALI_PHY_1313;
+ volatile u32 DENALI_PHY_1314;
+ volatile u32 DENALI_PHY_1315;
+ volatile u32 DENALI_PHY_1316;
+ volatile u32 DENALI_PHY_1317;
+ volatile u32 DENALI_PHY_1318;
+ volatile u32 DENALI_PHY_1319;
+ volatile u32 DENALI_PHY_1320;
+ volatile u32 DENALI_PHY_1321;
+ volatile u32 DENALI_PHY_1322;
+ volatile u32 DENALI_PHY_1323;
+ volatile u32 DENALI_PHY_1324;
+ volatile u32 DENALI_PHY_1325;
+ volatile u32 DENALI_PHY_1326;
+ volatile u32 DENALI_PHY_1327;
+ volatile u32 DENALI_PHY_1328;
+ volatile char pad__7[0x33CU];
+ volatile u32 DENALI_PHY_1536;
+ volatile u32 DENALI_PHY_1537;
+ volatile u32 DENALI_PHY_1538;
+ volatile u32 DENALI_PHY_1539;
+ volatile u32 DENALI_PHY_1540;
+ volatile u32 DENALI_PHY_1541;
+ volatile u32 DENALI_PHY_1542;
+ volatile u32 DENALI_PHY_1543;
+ volatile u32 DENALI_PHY_1544;
+ volatile u32 DENALI_PHY_1545;
+ volatile u32 DENALI_PHY_1546;
+ volatile u32 DENALI_PHY_1547;
+ volatile u32 DENALI_PHY_1548;
+ volatile u32 DENALI_PHY_1549;
+ volatile u32 DENALI_PHY_1550;
+ volatile u32 DENALI_PHY_1551;
+ volatile u32 DENALI_PHY_1552;
+ volatile u32 DENALI_PHY_1553;
+ volatile u32 DENALI_PHY_1554;
+ volatile u32 DENALI_PHY_1555;
+ volatile u32 DENALI_PHY_1556;
+ volatile u32 DENALI_PHY_1557;
+ volatile u32 DENALI_PHY_1558;
+ volatile u32 DENALI_PHY_1559;
+ volatile u32 DENALI_PHY_1560;
+ volatile u32 DENALI_PHY_1561;
+ volatile u32 DENALI_PHY_1562;
+ volatile u32 DENALI_PHY_1563;
+ volatile u32 DENALI_PHY_1564;
+ volatile u32 DENALI_PHY_1565;
+ volatile u32 DENALI_PHY_1566;
+ volatile u32 DENALI_PHY_1567;
+ volatile u32 DENALI_PHY_1568;
+ volatile u32 DENALI_PHY_1569;
+ volatile u32 DENALI_PHY_1570;
+ volatile u32 DENALI_PHY_1571;
+ volatile u32 DENALI_PHY_1572;
+ volatile u32 DENALI_PHY_1573;
+ volatile u32 DENALI_PHY_1574;
+ volatile u32 DENALI_PHY_1575;
+ volatile u32 DENALI_PHY_1576;
+ volatile u32 DENALI_PHY_1577;
+ volatile u32 DENALI_PHY_1578;
+ volatile u32 DENALI_PHY_1579;
+ volatile u32 DENALI_PHY_1580;
+ volatile u32 DENALI_PHY_1581;
+ volatile u32 DENALI_PHY_1582;
+ volatile u32 DENALI_PHY_1583;
+ volatile u32 DENALI_PHY_1584;
+ volatile char pad__8[0x33CU];
+ volatile u32 DENALI_PHY_1792;
+ volatile u32 DENALI_PHY_1793;
+ volatile u32 DENALI_PHY_1794;
+ volatile u32 DENALI_PHY_1795;
+ volatile u32 DENALI_PHY_1796;
+ volatile u32 DENALI_PHY_1797;
+ volatile u32 DENALI_PHY_1798;
+ volatile u32 DENALI_PHY_1799;
+ volatile u32 DENALI_PHY_1800;
+ volatile u32 DENALI_PHY_1801;
+ volatile u32 DENALI_PHY_1802;
+ volatile u32 DENALI_PHY_1803;
+ volatile u32 DENALI_PHY_1804;
+ volatile u32 DENALI_PHY_1805;
+ volatile u32 DENALI_PHY_1806;
+ volatile u32 DENALI_PHY_1807;
+ volatile u32 DENALI_PHY_1808;
+ volatile u32 DENALI_PHY_1809;
+ volatile u32 DENALI_PHY_1810;
+ volatile u32 DENALI_PHY_1811;
+ volatile u32 DENALI_PHY_1812;
+ volatile u32 DENALI_PHY_1813;
+ volatile u32 DENALI_PHY_1814;
+ volatile u32 DENALI_PHY_1815;
+ volatile u32 DENALI_PHY_1816;
+ volatile u32 DENALI_PHY_1817;
+ volatile u32 DENALI_PHY_1818;
+ volatile u32 DENALI_PHY_1819;
+ volatile u32 DENALI_PHY_1820;
+ volatile u32 DENALI_PHY_1821;
+ volatile u32 DENALI_PHY_1822;
+ volatile u32 DENALI_PHY_1823;
+ volatile u32 DENALI_PHY_1824;
+ volatile u32 DENALI_PHY_1825;
+ volatile u32 DENALI_PHY_1826;
+ volatile u32 DENALI_PHY_1827;
+ volatile u32 DENALI_PHY_1828;
+ volatile u32 DENALI_PHY_1829;
+ volatile u32 DENALI_PHY_1830;
+ volatile u32 DENALI_PHY_1831;
+ volatile u32 DENALI_PHY_1832;
+ volatile u32 DENALI_PHY_1833;
+ volatile u32 DENALI_PHY_1834;
+ volatile u32 DENALI_PHY_1835;
+ volatile u32 DENALI_PHY_1836;
+ volatile u32 DENALI_PHY_1837;
+ volatile u32 DENALI_PHY_1838;
+ volatile u32 DENALI_PHY_1839;
+ volatile u32 DENALI_PHY_1840;
+ volatile u32 DENALI_PHY_1841;
+ volatile u32 DENALI_PHY_1842;
+ volatile u32 DENALI_PHY_1843;
+ volatile u32 DENALI_PHY_1844;
+ volatile u32 DENALI_PHY_1845;
+ volatile u32 DENALI_PHY_1846;
+ volatile u32 DENALI_PHY_1847;
+ volatile u32 DENALI_PHY_1848;
+ volatile u32 DENALI_PHY_1849;
+ volatile u32 DENALI_PHY_1850;
+ volatile u32 DENALI_PHY_1851;
+ volatile u32 DENALI_PHY_1852;
+ volatile u32 DENALI_PHY_1853;
+ volatile u32 DENALI_PHY_1854;
+ volatile u32 DENALI_PHY_1855;
+ volatile u32 DENALI_PHY_1856;
+ volatile u32 DENALI_PHY_1857;
+ volatile u32 DENALI_PHY_1858;
+ volatile u32 DENALI_PHY_1859;
+ volatile u32 DENALI_PHY_1860;
+ volatile u32 DENALI_PHY_1861;
+ volatile u32 DENALI_PHY_1862;
+ volatile u32 DENALI_PHY_1863;
+ volatile u32 DENALI_PHY_1864;
+ volatile u32 DENALI_PHY_1865;
+ volatile u32 DENALI_PHY_1866;
+ volatile u32 DENALI_PHY_1867;
+ volatile u32 DENALI_PHY_1868;
+ volatile u32 DENALI_PHY_1869;
+ volatile u32 DENALI_PHY_1870;
+ volatile u32 DENALI_PHY_1871;
+ volatile u32 DENALI_PHY_1872;
+ volatile u32 DENALI_PHY_1873;
+ volatile u32 DENALI_PHY_1874;
+ volatile u32 DENALI_PHY_1875;
+ volatile u32 DENALI_PHY_1876;
+ volatile u32 DENALI_PHY_1877;
+ volatile u32 DENALI_PHY_1878;
+ volatile u32 DENALI_PHY_1879;
+ volatile u32 DENALI_PHY_1880;
+ volatile u32 DENALI_PHY_1881;
+ volatile u32 DENALI_PHY_1882;
+ volatile u32 DENALI_PHY_1883;
+ volatile u32 DENALI_PHY_1884;
+ volatile u32 DENALI_PHY_1885;
+ volatile u32 DENALI_PHY_1886;
+ volatile u32 DENALI_PHY_1887;
+ volatile u32 DENALI_PHY_1888;
+ volatile u32 DENALI_PHY_1889;
+ volatile u32 DENALI_PHY_1890;
+ volatile u32 DENALI_PHY_1891;
+ volatile u32 DENALI_PHY_1892;
+ volatile u32 DENALI_PHY_1893;
+ volatile u32 DENALI_PHY_1894;
+ volatile u32 DENALI_PHY_1895;
+ volatile u32 DENALI_PHY_1896;
+ volatile u32 DENALI_PHY_1897;
+ volatile u32 DENALI_PHY_1898;
+ volatile u32 DENALI_PHY_1899;
+ volatile u32 DENALI_PHY_1900;
+ volatile u32 DENALI_PHY_1901;
+ volatile u32 DENALI_PHY_1902;
+ volatile u32 DENALI_PHY_1903;
+ volatile u32 DENALI_PHY_1904;
+ volatile u32 DENALI_PHY_1905;
+ volatile u32 DENALI_PHY_1906;
+ volatile u32 DENALI_PHY_1907;
+ volatile u32 DENALI_PHY_1908;
+ volatile u32 DENALI_PHY_1909;
+ volatile u32 DENALI_PHY_1910;
+ volatile u32 DENALI_PHY_1911;
+ volatile u32 DENALI_PHY_1912;
+ volatile u32 DENALI_PHY_1913;
+ volatile u32 DENALI_PHY_1914;
+ volatile u32 DENALI_PHY_1915;
+ volatile u32 DENALI_PHY_1916;
+ volatile u32 DENALI_PHY_1917;
+ volatile u32 DENALI_PHY_1918;
+ volatile u32 DENALI_PHY_1919;
+ volatile u32 DENALI_PHY_1920;
+ volatile u32 DENALI_PHY_1921;
+ volatile u32 DENALI_PHY_1922;
+ volatile u32 DENALI_PHY_1923;
+} lpddr4_ctlregs;
+
+#endif /* REG_LPDDR4_CTL_REGS_H_ */
diff --git a/drivers/ram/k3-ddrss/am62a/lpddr4_data_slice_0_macros.h b/drivers/ram/k3-ddrss/am62a/lpddr4_data_slice_0_macros.h
new file mode 100644
index 00000000000..013f1f0343d
--- /dev/null
+++ b/drivers/ram/k3-ddrss/am62a/lpddr4_data_slice_0_macros.h
@@ -0,0 +1,2292 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef REG_LPDDR4_DATA_SLICE_0_MACROS_H_
+#define REG_LPDDR4_DATA_SLICE_0_MACROS_H_
+
+#define LPDDR4__DENALI_PHY_0_READ_MASK 0x07FF7F07U
+#define LPDDR4__DENALI_PHY_0_WRITE_MASK 0x07FF7F07U
+#define LPDDR4__DENALI_PHY_0__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_0_MASK 0x00000007U
+#define LPDDR4__DENALI_PHY_0__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_0__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_0_WIDTH 3U
+#define LPDDR4__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_0__REG DENALI_PHY_0
+#define LPDDR4__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_0__FLD LPDDR4__DENALI_PHY_0__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_0
+
+#define LPDDR4__DENALI_PHY_0__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_0_MASK 0x00007F00U
+#define LPDDR4__DENALI_PHY_0__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_0__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_0_WIDTH 7U
+#define LPDDR4__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_0__REG DENALI_PHY_0
+#define LPDDR4__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_0__FLD LPDDR4__DENALI_PHY_0__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_0
+
+#define LPDDR4__DENALI_PHY_0__PHY_CLK_WR_BYPASS_SLAVE_DELAY_0_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_0__PHY_CLK_WR_BYPASS_SLAVE_DELAY_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_0__PHY_CLK_WR_BYPASS_SLAVE_DELAY_0_WIDTH 11U
+#define LPDDR4__PHY_CLK_WR_BYPASS_SLAVE_DELAY_0__REG DENALI_PHY_0
+#define LPDDR4__PHY_CLK_WR_BYPASS_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_0__PHY_CLK_WR_BYPASS_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_1_READ_MASK 0x0703FF0FU
+#define LPDDR4__DENALI_PHY_1_WRITE_MASK 0x0703FF0FU
+#define LPDDR4__DENALI_PHY_1__PHY_IO_PAD_DELAY_TIMING_BYPASS_0_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_1__PHY_IO_PAD_DELAY_TIMING_BYPASS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1__PHY_IO_PAD_DELAY_TIMING_BYPASS_0_WIDTH 4U
+#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_0__REG DENALI_PHY_1
+#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_0__FLD LPDDR4__DENALI_PHY_1__PHY_IO_PAD_DELAY_TIMING_BYPASS_0
+
+#define LPDDR4__DENALI_PHY_1__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0_MASK 0x0003FF00U
+#define LPDDR4__DENALI_PHY_1__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0_WIDTH 10U
+#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0__REG DENALI_PHY_1
+#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0__FLD LPDDR4__DENALI_PHY_1__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0
+
+#define LPDDR4__DENALI_PHY_1__PHY_WRITE_PATH_LAT_ADD_BYPASS_0_MASK 0x07000000U
+#define LPDDR4__DENALI_PHY_1__PHY_WRITE_PATH_LAT_ADD_BYPASS_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1__PHY_WRITE_PATH_LAT_ADD_BYPASS_0_WIDTH 3U
+#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_0__REG DENALI_PHY_1
+#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_0__FLD LPDDR4__DENALI_PHY_1__PHY_WRITE_PATH_LAT_ADD_BYPASS_0
+
+#define LPDDR4__DENALI_PHY_2_READ_MASK 0x010303FFU
+#define LPDDR4__DENALI_PHY_2_WRITE_MASK 0x010303FFU
+#define LPDDR4__DENALI_PHY_2__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_2__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_2__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0__REG DENALI_PHY_2
+#define LPDDR4__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_2__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_2__PHY_BYPASS_TWO_CYC_PREAMBLE_0_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_2__PHY_BYPASS_TWO_CYC_PREAMBLE_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_2__PHY_BYPASS_TWO_CYC_PREAMBLE_0_WIDTH 2U
+#define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_0__REG DENALI_PHY_2
+#define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_0__FLD LPDDR4__DENALI_PHY_2__PHY_BYPASS_TWO_CYC_PREAMBLE_0
+
+#define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_WOSET 0U
+#define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_0__REG DENALI_PHY_2
+#define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_0__FLD LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0
+
+#define LPDDR4__DENALI_PHY_3_READ_MASK 0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_3_WRITE_MASK 0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ0_SHIFT_0_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ0_SHIFT_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ0_SHIFT_0_WIDTH 6U
+#define LPDDR4__PHY_SW_WRDQ0_SHIFT_0__REG DENALI_PHY_3
+#define LPDDR4__PHY_SW_WRDQ0_SHIFT_0__FLD LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ0_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ1_SHIFT_0_MASK 0x00003F00U
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ1_SHIFT_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ1_SHIFT_0_WIDTH 6U
+#define LPDDR4__PHY_SW_WRDQ1_SHIFT_0__REG DENALI_PHY_3
+#define LPDDR4__PHY_SW_WRDQ1_SHIFT_0__FLD LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ1_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ2_SHIFT_0_MASK 0x003F0000U
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ2_SHIFT_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ2_SHIFT_0_WIDTH 6U
+#define LPDDR4__PHY_SW_WRDQ2_SHIFT_0__REG DENALI_PHY_3
+#define LPDDR4__PHY_SW_WRDQ2_SHIFT_0__FLD LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ2_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ3_SHIFT_0_MASK 0x3F000000U
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ3_SHIFT_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ3_SHIFT_0_WIDTH 6U
+#define LPDDR4__PHY_SW_WRDQ3_SHIFT_0__REG DENALI_PHY_3
+#define LPDDR4__PHY_SW_WRDQ3_SHIFT_0__FLD LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ3_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_4_READ_MASK 0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_4_WRITE_MASK 0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ4_SHIFT_0_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ4_SHIFT_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ4_SHIFT_0_WIDTH 6U
+#define LPDDR4__PHY_SW_WRDQ4_SHIFT_0__REG DENALI_PHY_4
+#define LPDDR4__PHY_SW_WRDQ4_SHIFT_0__FLD LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ4_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ5_SHIFT_0_MASK 0x00003F00U
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ5_SHIFT_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ5_SHIFT_0_WIDTH 6U
+#define LPDDR4__PHY_SW_WRDQ5_SHIFT_0__REG DENALI_PHY_4
+#define LPDDR4__PHY_SW_WRDQ5_SHIFT_0__FLD LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ5_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ6_SHIFT_0_MASK 0x003F0000U
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ6_SHIFT_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ6_SHIFT_0_WIDTH 6U
+#define LPDDR4__PHY_SW_WRDQ6_SHIFT_0__REG DENALI_PHY_4
+#define LPDDR4__PHY_SW_WRDQ6_SHIFT_0__FLD LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ6_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ7_SHIFT_0_MASK 0x3F000000U
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ7_SHIFT_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ7_SHIFT_0_WIDTH 6U
+#define LPDDR4__PHY_SW_WRDQ7_SHIFT_0__REG DENALI_PHY_4
+#define LPDDR4__PHY_SW_WRDQ7_SHIFT_0__FLD LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ7_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_5_READ_MASK 0x01030F3FU
+#define LPDDR4__DENALI_PHY_5_WRITE_MASK 0x01030F3FU
+#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDM_SHIFT_0_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDM_SHIFT_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDM_SHIFT_0_WIDTH 6U
+#define LPDDR4__PHY_SW_WRDM_SHIFT_0__REG DENALI_PHY_5
+#define LPDDR4__PHY_SW_WRDM_SHIFT_0__FLD LPDDR4__DENALI_PHY_5__PHY_SW_WRDM_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDQS_SHIFT_0_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDQS_SHIFT_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDQS_SHIFT_0_WIDTH 4U
+#define LPDDR4__PHY_SW_WRDQS_SHIFT_0__REG DENALI_PHY_5
+#define LPDDR4__PHY_SW_WRDQS_SHIFT_0__FLD LPDDR4__DENALI_PHY_5__PHY_SW_WRDQS_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_5__PHY_PER_RANK_CS_MAP_0_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_5__PHY_PER_RANK_CS_MAP_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_5__PHY_PER_RANK_CS_MAP_0_WIDTH 2U
+#define LPDDR4__PHY_PER_RANK_CS_MAP_0__REG DENALI_PHY_5
+#define LPDDR4__PHY_PER_RANK_CS_MAP_0__FLD LPDDR4__DENALI_PHY_5__PHY_PER_RANK_CS_MAP_0
+
+#define LPDDR4__DENALI_PHY_5__PHY_PER_CS_TRAINING_MULTICAST_EN_0_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_5__PHY_PER_CS_TRAINING_MULTICAST_EN_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_5__PHY_PER_CS_TRAINING_MULTICAST_EN_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_5__PHY_PER_CS_TRAINING_MULTICAST_EN_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_5__PHY_PER_CS_TRAINING_MULTICAST_EN_0_WOSET 0U
+#define LPDDR4__PHY_PER_CS_TRAINING_MULTICAST_EN_0__REG DENALI_PHY_5
+#define LPDDR4__PHY_PER_CS_TRAINING_MULTICAST_EN_0__FLD LPDDR4__DENALI_PHY_5__PHY_PER_CS_TRAINING_MULTICAST_EN_0
+
+#define LPDDR4__DENALI_PHY_6_READ_MASK 0x1F1F0301U
+#define LPDDR4__DENALI_PHY_6_WRITE_MASK 0x1F1F0301U
+#define LPDDR4__DENALI_PHY_6__PHY_PER_CS_TRAINING_INDEX_0_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_6__PHY_PER_CS_TRAINING_INDEX_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_6__PHY_PER_CS_TRAINING_INDEX_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_6__PHY_PER_CS_TRAINING_INDEX_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_6__PHY_PER_CS_TRAINING_INDEX_0_WOSET 0U
+#define LPDDR4__PHY_PER_CS_TRAINING_INDEX_0__REG DENALI_PHY_6
+#define LPDDR4__PHY_PER_CS_TRAINING_INDEX_0__FLD LPDDR4__DENALI_PHY_6__PHY_PER_CS_TRAINING_INDEX_0
+
+#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0_MASK 0x00000300U
+#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0_WIDTH 2U
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0__REG DENALI_PHY_6
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0__FLD LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0
+
+#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_DLY_0_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_DLY_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_DLY_0_WIDTH 5U
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_DLY_0__REG DENALI_PHY_6
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_DLY_0__FLD LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_DLY_0
+
+#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0_WIDTH 5U
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0__REG DENALI_PHY_6
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0__FLD LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0
+
+#define LPDDR4__DENALI_PHY_7_READ_MASK 0x1F030F0FU
+#define LPDDR4__DENALI_PHY_7_WRITE_MASK 0x1F030F0FU
+#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RPTR_UPDATE_0_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RPTR_UPDATE_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RPTR_UPDATE_0_WIDTH 4U
+#define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_0__REG DENALI_PHY_7
+#define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_0__FLD LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RPTR_UPDATE_0
+
+#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0_WIDTH 4U
+#define LPDDR4__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0__REG DENALI_PHY_7
+#define LPDDR4__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0__FLD LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0
+
+#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0_WIDTH 2U
+#define LPDDR4__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0__REG DENALI_PHY_7
+#define LPDDR4__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0_WIDTH 5U
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0__REG DENALI_PHY_7
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0__FLD LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0
+
+#define LPDDR4__DENALI_PHY_8_READ_MASK 0x0101FF03U
+#define LPDDR4__DENALI_PHY_8_WRITE_MASK 0x0101FF03U
+#define LPDDR4__DENALI_PHY_8__PHY_CTRL_LPBK_EN_0_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_8__PHY_CTRL_LPBK_EN_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_8__PHY_CTRL_LPBK_EN_0_WIDTH 2U
+#define LPDDR4__PHY_CTRL_LPBK_EN_0__REG DENALI_PHY_8
+#define LPDDR4__PHY_CTRL_LPBK_EN_0__FLD LPDDR4__DENALI_PHY_8__PHY_CTRL_LPBK_EN_0
+
+#define LPDDR4__DENALI_PHY_8__PHY_LPBK_CONTROL_0_MASK 0x0001FF00U
+#define LPDDR4__DENALI_PHY_8__PHY_LPBK_CONTROL_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_8__PHY_LPBK_CONTROL_0_WIDTH 9U
+#define LPDDR4__PHY_LPBK_CONTROL_0__REG DENALI_PHY_8
+#define LPDDR4__PHY_LPBK_CONTROL_0__FLD LPDDR4__DENALI_PHY_8__PHY_LPBK_CONTROL_0
+
+#define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_WOSET 0U
+#define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_0__REG DENALI_PHY_8
+#define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_0__FLD LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0
+
+#define LPDDR4__DENALI_PHY_9_READ_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_9_WRITE_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_9__PHY_GATE_DELAY_COMP_DISABLE_0_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_9__PHY_GATE_DELAY_COMP_DISABLE_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_9__PHY_GATE_DELAY_COMP_DISABLE_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_9__PHY_GATE_DELAY_COMP_DISABLE_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_9__PHY_GATE_DELAY_COMP_DISABLE_0_WOSET 0U
+#define LPDDR4__PHY_GATE_DELAY_COMP_DISABLE_0__REG DENALI_PHY_9
+#define LPDDR4__PHY_GATE_DELAY_COMP_DISABLE_0__FLD LPDDR4__DENALI_PHY_9__PHY_GATE_DELAY_COMP_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_10_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_10_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_10__PHY_AUTO_TIMING_MARGIN_CONTROL_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_10__PHY_AUTO_TIMING_MARGIN_CONTROL_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_10__PHY_AUTO_TIMING_MARGIN_CONTROL_0_WIDTH 32U
+#define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_0__REG DENALI_PHY_10
+#define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_0__FLD LPDDR4__DENALI_PHY_10__PHY_AUTO_TIMING_MARGIN_CONTROL_0
+
+#define LPDDR4__DENALI_PHY_11_READ_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_11_WRITE_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_11__PHY_AUTO_TIMING_MARGIN_OBS_0_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_11__PHY_AUTO_TIMING_MARGIN_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_11__PHY_AUTO_TIMING_MARGIN_OBS_0_WIDTH 28U
+#define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_0__REG DENALI_PHY_11
+#define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_0__FLD LPDDR4__DENALI_PHY_11__PHY_AUTO_TIMING_MARGIN_OBS_0
+
+#define LPDDR4__DENALI_PHY_12_READ_MASK 0x7F0101FFU
+#define LPDDR4__DENALI_PHY_12_WRITE_MASK 0x7F0101FFU
+#define LPDDR4__DENALI_PHY_12__PHY_DQ_IDLE_0_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_12__PHY_DQ_IDLE_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_12__PHY_DQ_IDLE_0_WIDTH 9U
+#define LPDDR4__PHY_DQ_IDLE_0__REG DENALI_PHY_12
+#define LPDDR4__PHY_DQ_IDLE_0__FLD LPDDR4__DENALI_PHY_12__PHY_DQ_IDLE_0
+
+#define LPDDR4__DENALI_PHY_12__PHY_PDA_MODE_EN_0_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_12__PHY_PDA_MODE_EN_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_12__PHY_PDA_MODE_EN_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_12__PHY_PDA_MODE_EN_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_12__PHY_PDA_MODE_EN_0_WOSET 0U
+#define LPDDR4__PHY_PDA_MODE_EN_0__REG DENALI_PHY_12
+#define LPDDR4__PHY_PDA_MODE_EN_0__FLD LPDDR4__DENALI_PHY_12__PHY_PDA_MODE_EN_0
+
+#define LPDDR4__DENALI_PHY_12__PHY_PRBS_PATTERN_START_0_MASK 0x7F000000U
+#define LPDDR4__DENALI_PHY_12__PHY_PRBS_PATTERN_START_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_12__PHY_PRBS_PATTERN_START_0_WIDTH 7U
+#define LPDDR4__PHY_PRBS_PATTERN_START_0__REG DENALI_PHY_12
+#define LPDDR4__PHY_PRBS_PATTERN_START_0__FLD LPDDR4__DENALI_PHY_12__PHY_PRBS_PATTERN_START_0
+
+#define LPDDR4__DENALI_PHY_13_READ_MASK 0x010101FFU
+#define LPDDR4__DENALI_PHY_13_WRITE_MASK 0x010101FFU
+#define LPDDR4__DENALI_PHY_13__PHY_PRBS_PATTERN_MASK_0_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_13__PHY_PRBS_PATTERN_MASK_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_13__PHY_PRBS_PATTERN_MASK_0_WIDTH 9U
+#define LPDDR4__PHY_PRBS_PATTERN_MASK_0__REG DENALI_PHY_13
+#define LPDDR4__PHY_PRBS_PATTERN_MASK_0__FLD LPDDR4__DENALI_PHY_13__PHY_PRBS_PATTERN_MASK_0
+
+#define LPDDR4__DENALI_PHY_13__PHY_RDLVL_MULTI_PATT_ENABLE_0_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_13__PHY_RDLVL_MULTI_PATT_ENABLE_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_13__PHY_RDLVL_MULTI_PATT_ENABLE_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_13__PHY_RDLVL_MULTI_PATT_ENABLE_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_13__PHY_RDLVL_MULTI_PATT_ENABLE_0_WOSET 0U
+#define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_0__REG DENALI_PHY_13
+#define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_0__FLD LPDDR4__DENALI_PHY_13__PHY_RDLVL_MULTI_PATT_ENABLE_0
+
+#define LPDDR4__DENALI_PHY_13__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_13__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_13__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_13__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_13__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0_WOSET 0U
+#define LPDDR4__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0__REG DENALI_PHY_13
+#define LPDDR4__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0__FLD LPDDR4__DENALI_PHY_13__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_14_READ_MASK 0x03FF7F3FU
+#define LPDDR4__DENALI_PHY_14_WRITE_MASK 0x03FF7F3FU
+#define LPDDR4__DENALI_PHY_14__PHY_VREF_INITIAL_STEPSIZE_0_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_14__PHY_VREF_INITIAL_STEPSIZE_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_14__PHY_VREF_INITIAL_STEPSIZE_0_WIDTH 6U
+#define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_0__REG DENALI_PHY_14
+#define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_0__FLD LPDDR4__DENALI_PHY_14__PHY_VREF_INITIAL_STEPSIZE_0
+
+#define LPDDR4__DENALI_PHY_14__PHY_VREF_TRAIN_OBS_0_MASK 0x00007F00U
+#define LPDDR4__DENALI_PHY_14__PHY_VREF_TRAIN_OBS_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_14__PHY_VREF_TRAIN_OBS_0_WIDTH 7U
+#define LPDDR4__PHY_VREF_TRAIN_OBS_0__REG DENALI_PHY_14
+#define LPDDR4__PHY_VREF_TRAIN_OBS_0__FLD LPDDR4__DENALI_PHY_14__PHY_VREF_TRAIN_OBS_0
+
+#define LPDDR4__DENALI_PHY_14__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_14__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_14__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0__REG DENALI_PHY_14
+#define LPDDR4__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_14__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_15_READ_MASK 0x01FF000FU
+#define LPDDR4__DENALI_PHY_15_WRITE_MASK 0x01FF000FU
+#define LPDDR4__DENALI_PHY_15__PHY_GATE_ERROR_DELAY_SELECT_0_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_15__PHY_GATE_ERROR_DELAY_SELECT_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_15__PHY_GATE_ERROR_DELAY_SELECT_0_WIDTH 4U
+#define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_0__REG DENALI_PHY_15
+#define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_0__FLD LPDDR4__DENALI_PHY_15__PHY_GATE_ERROR_DELAY_SELECT_0
+
+#define LPDDR4__DENALI_PHY_15__SC_PHY_SNAP_OBS_REGS_0_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_15__SC_PHY_SNAP_OBS_REGS_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_15__SC_PHY_SNAP_OBS_REGS_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_15__SC_PHY_SNAP_OBS_REGS_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_15__SC_PHY_SNAP_OBS_REGS_0_WOSET 0U
+#define LPDDR4__SC_PHY_SNAP_OBS_REGS_0__REG DENALI_PHY_15
+#define LPDDR4__SC_PHY_SNAP_OBS_REGS_0__FLD LPDDR4__DENALI_PHY_15__SC_PHY_SNAP_OBS_REGS_0
+
+#define LPDDR4__DENALI_PHY_15__PHY_GATE_SMPL1_SLAVE_DELAY_0_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_15__PHY_GATE_SMPL1_SLAVE_DELAY_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_15__PHY_GATE_SMPL1_SLAVE_DELAY_0_WIDTH 9U
+#define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_0__REG DENALI_PHY_15
+#define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_15__PHY_GATE_SMPL1_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_16_READ_MASK 0x01FF0701U
+#define LPDDR4__DENALI_PHY_16_WRITE_MASK 0x01FF0701U
+#define LPDDR4__DENALI_PHY_16__PHY_LPDDR_0_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_16__PHY_LPDDR_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_16__PHY_LPDDR_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_16__PHY_LPDDR_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_16__PHY_LPDDR_0_WOSET 0U
+#define LPDDR4__PHY_LPDDR_0__REG DENALI_PHY_16
+#define LPDDR4__PHY_LPDDR_0__FLD LPDDR4__DENALI_PHY_16__PHY_LPDDR_0
+
+#define LPDDR4__DENALI_PHY_16__PHY_MEM_CLASS_0_MASK 0x00000700U
+#define LPDDR4__DENALI_PHY_16__PHY_MEM_CLASS_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_16__PHY_MEM_CLASS_0_WIDTH 3U
+#define LPDDR4__PHY_MEM_CLASS_0__REG DENALI_PHY_16
+#define LPDDR4__PHY_MEM_CLASS_0__FLD LPDDR4__DENALI_PHY_16__PHY_MEM_CLASS_0
+
+#define LPDDR4__DENALI_PHY_16__PHY_GATE_SMPL2_SLAVE_DELAY_0_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_16__PHY_GATE_SMPL2_SLAVE_DELAY_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_16__PHY_GATE_SMPL2_SLAVE_DELAY_0_WIDTH 9U
+#define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_0__REG DENALI_PHY_16
+#define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_16__PHY_GATE_SMPL2_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_17_READ_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_17_WRITE_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_17__ON_FLY_GATE_ADJUST_EN_0_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_17__ON_FLY_GATE_ADJUST_EN_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_17__ON_FLY_GATE_ADJUST_EN_0_WIDTH 2U
+#define LPDDR4__ON_FLY_GATE_ADJUST_EN_0__REG DENALI_PHY_17
+#define LPDDR4__ON_FLY_GATE_ADJUST_EN_0__FLD LPDDR4__DENALI_PHY_17__ON_FLY_GATE_ADJUST_EN_0
+
+#define LPDDR4__DENALI_PHY_18_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_18_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_18__PHY_GATE_TRACKING_OBS_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_18__PHY_GATE_TRACKING_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_18__PHY_GATE_TRACKING_OBS_0_WIDTH 32U
+#define LPDDR4__PHY_GATE_TRACKING_OBS_0__REG DENALI_PHY_18
+#define LPDDR4__PHY_GATE_TRACKING_OBS_0__FLD LPDDR4__DENALI_PHY_18__PHY_GATE_TRACKING_OBS_0
+
+#define LPDDR4__DENALI_PHY_19_READ_MASK 0x00000301U
+#define LPDDR4__DENALI_PHY_19_WRITE_MASK 0x00000301U
+#define LPDDR4__DENALI_PHY_19__PHY_DFI40_POLARITY_0_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_19__PHY_DFI40_POLARITY_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_19__PHY_DFI40_POLARITY_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_19__PHY_DFI40_POLARITY_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_19__PHY_DFI40_POLARITY_0_WOSET 0U
+#define LPDDR4__PHY_DFI40_POLARITY_0__REG DENALI_PHY_19
+#define LPDDR4__PHY_DFI40_POLARITY_0__FLD LPDDR4__DENALI_PHY_19__PHY_DFI40_POLARITY_0
+
+#define LPDDR4__DENALI_PHY_19__PHY_LP4_PST_AMBLE_0_MASK 0x00000300U
+#define LPDDR4__DENALI_PHY_19__PHY_LP4_PST_AMBLE_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_19__PHY_LP4_PST_AMBLE_0_WIDTH 2U
+#define LPDDR4__PHY_LP4_PST_AMBLE_0__REG DENALI_PHY_19
+#define LPDDR4__PHY_LP4_PST_AMBLE_0__FLD LPDDR4__DENALI_PHY_19__PHY_LP4_PST_AMBLE_0
+
+#define LPDDR4__DENALI_PHY_20_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_20_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_20__PHY_RDLVL_PATT8_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_20__PHY_RDLVL_PATT8_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_20__PHY_RDLVL_PATT8_0_WIDTH 32U
+#define LPDDR4__PHY_RDLVL_PATT8_0__REG DENALI_PHY_20
+#define LPDDR4__PHY_RDLVL_PATT8_0__FLD LPDDR4__DENALI_PHY_20__PHY_RDLVL_PATT8_0
+
+#define LPDDR4__DENALI_PHY_21_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_21_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_21__PHY_RDLVL_PATT9_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_21__PHY_RDLVL_PATT9_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_21__PHY_RDLVL_PATT9_0_WIDTH 32U
+#define LPDDR4__PHY_RDLVL_PATT9_0__REG DENALI_PHY_21
+#define LPDDR4__PHY_RDLVL_PATT9_0__FLD LPDDR4__DENALI_PHY_21__PHY_RDLVL_PATT9_0
+
+#define LPDDR4__DENALI_PHY_22_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_22_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_22__PHY_RDLVL_PATT10_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_22__PHY_RDLVL_PATT10_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_22__PHY_RDLVL_PATT10_0_WIDTH 32U
+#define LPDDR4__PHY_RDLVL_PATT10_0__REG DENALI_PHY_22
+#define LPDDR4__PHY_RDLVL_PATT10_0__FLD LPDDR4__DENALI_PHY_22__PHY_RDLVL_PATT10_0
+
+#define LPDDR4__DENALI_PHY_23_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_23_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_23__PHY_RDLVL_PATT11_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_23__PHY_RDLVL_PATT11_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_23__PHY_RDLVL_PATT11_0_WIDTH 32U
+#define LPDDR4__PHY_RDLVL_PATT11_0__REG DENALI_PHY_23
+#define LPDDR4__PHY_RDLVL_PATT11_0__FLD LPDDR4__DENALI_PHY_23__PHY_RDLVL_PATT11_0
+
+#define LPDDR4__DENALI_PHY_24_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_24_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_24__PHY_RDLVL_PATT12_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_24__PHY_RDLVL_PATT12_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_24__PHY_RDLVL_PATT12_0_WIDTH 32U
+#define LPDDR4__PHY_RDLVL_PATT12_0__REG DENALI_PHY_24
+#define LPDDR4__PHY_RDLVL_PATT12_0__FLD LPDDR4__DENALI_PHY_24__PHY_RDLVL_PATT12_0
+
+#define LPDDR4__DENALI_PHY_25_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_25_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_25__PHY_RDLVL_PATT13_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_25__PHY_RDLVL_PATT13_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_25__PHY_RDLVL_PATT13_0_WIDTH 32U
+#define LPDDR4__PHY_RDLVL_PATT13_0__REG DENALI_PHY_25
+#define LPDDR4__PHY_RDLVL_PATT13_0__FLD LPDDR4__DENALI_PHY_25__PHY_RDLVL_PATT13_0
+
+#define LPDDR4__DENALI_PHY_26_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_26_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_26__PHY_RDLVL_PATT14_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_26__PHY_RDLVL_PATT14_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_26__PHY_RDLVL_PATT14_0_WIDTH 32U
+#define LPDDR4__PHY_RDLVL_PATT14_0__REG DENALI_PHY_26
+#define LPDDR4__PHY_RDLVL_PATT14_0__FLD LPDDR4__DENALI_PHY_26__PHY_RDLVL_PATT14_0
+
+#define LPDDR4__DENALI_PHY_27_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_27_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_27__PHY_RDLVL_PATT15_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_27__PHY_RDLVL_PATT15_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_27__PHY_RDLVL_PATT15_0_WIDTH 32U
+#define LPDDR4__PHY_RDLVL_PATT15_0__REG DENALI_PHY_27
+#define LPDDR4__PHY_RDLVL_PATT15_0__FLD LPDDR4__DENALI_PHY_27__PHY_RDLVL_PATT15_0
+
+#define LPDDR4__DENALI_PHY_28_READ_MASK 0x070F0107U
+#define LPDDR4__DENALI_PHY_28_WRITE_MASK 0x070F0107U
+#define LPDDR4__DENALI_PHY_28__PHY_SLAVE_LOOP_CNT_UPDATE_0_MASK 0x00000007U
+#define LPDDR4__DENALI_PHY_28__PHY_SLAVE_LOOP_CNT_UPDATE_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_28__PHY_SLAVE_LOOP_CNT_UPDATE_0_WIDTH 3U
+#define LPDDR4__PHY_SLAVE_LOOP_CNT_UPDATE_0__REG DENALI_PHY_28
+#define LPDDR4__PHY_SLAVE_LOOP_CNT_UPDATE_0__FLD LPDDR4__DENALI_PHY_28__PHY_SLAVE_LOOP_CNT_UPDATE_0
+
+#define LPDDR4__DENALI_PHY_28__PHY_SW_FIFO_PTR_RST_DISABLE_0_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_28__PHY_SW_FIFO_PTR_RST_DISABLE_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_28__PHY_SW_FIFO_PTR_RST_DISABLE_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_28__PHY_SW_FIFO_PTR_RST_DISABLE_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_28__PHY_SW_FIFO_PTR_RST_DISABLE_0_WOSET 0U
+#define LPDDR4__PHY_SW_FIFO_PTR_RST_DISABLE_0__REG DENALI_PHY_28
+#define LPDDR4__PHY_SW_FIFO_PTR_RST_DISABLE_0__FLD LPDDR4__DENALI_PHY_28__PHY_SW_FIFO_PTR_RST_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_28__PHY_MASTER_DLY_LOCK_OBS_SELECT_0_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_28__PHY_MASTER_DLY_LOCK_OBS_SELECT_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_28__PHY_MASTER_DLY_LOCK_OBS_SELECT_0_WIDTH 4U
+#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_SELECT_0__REG DENALI_PHY_28
+#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_28__PHY_MASTER_DLY_LOCK_OBS_SELECT_0
+
+#define LPDDR4__DENALI_PHY_28__PHY_RDDQ_ENC_OBS_SELECT_0_MASK 0x07000000U
+#define LPDDR4__DENALI_PHY_28__PHY_RDDQ_ENC_OBS_SELECT_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_28__PHY_RDDQ_ENC_OBS_SELECT_0_WIDTH 3U
+#define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_0__REG DENALI_PHY_28
+#define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_28__PHY_RDDQ_ENC_OBS_SELECT_0
+
+#define LPDDR4__DENALI_PHY_29_READ_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_29_WRITE_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_29__PHY_RDDQS_DQ_ENC_OBS_SELECT_0_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_29__PHY_RDDQS_DQ_ENC_OBS_SELECT_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_29__PHY_RDDQS_DQ_ENC_OBS_SELECT_0_WIDTH 4U
+#define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_0__REG DENALI_PHY_29
+#define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_29__PHY_RDDQS_DQ_ENC_OBS_SELECT_0
+
+#define LPDDR4__DENALI_PHY_29__PHY_WR_ENC_OBS_SELECT_0_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_29__PHY_WR_ENC_OBS_SELECT_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_29__PHY_WR_ENC_OBS_SELECT_0_WIDTH 4U
+#define LPDDR4__PHY_WR_ENC_OBS_SELECT_0__REG DENALI_PHY_29
+#define LPDDR4__PHY_WR_ENC_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_29__PHY_WR_ENC_OBS_SELECT_0
+
+#define LPDDR4__DENALI_PHY_29__PHY_WR_SHIFT_OBS_SELECT_0_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_29__PHY_WR_SHIFT_OBS_SELECT_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_29__PHY_WR_SHIFT_OBS_SELECT_0_WIDTH 4U
+#define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_0__REG DENALI_PHY_29
+#define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_29__PHY_WR_SHIFT_OBS_SELECT_0
+
+#define LPDDR4__DENALI_PHY_29__PHY_FIFO_PTR_OBS_SELECT_0_MASK 0x0F000000U
+#define LPDDR4__DENALI_PHY_29__PHY_FIFO_PTR_OBS_SELECT_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_29__PHY_FIFO_PTR_OBS_SELECT_0_WIDTH 4U
+#define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_0__REG DENALI_PHY_29
+#define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_29__PHY_FIFO_PTR_OBS_SELECT_0
+
+#define LPDDR4__DENALI_PHY_30_READ_MASK 0x3F030001U
+#define LPDDR4__DENALI_PHY_30_WRITE_MASK 0x3F030001U
+#define LPDDR4__DENALI_PHY_30__PHY_LVL_DEBUG_MODE_0_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_30__PHY_LVL_DEBUG_MODE_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_30__PHY_LVL_DEBUG_MODE_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_30__PHY_LVL_DEBUG_MODE_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_30__PHY_LVL_DEBUG_MODE_0_WOSET 0U
+#define LPDDR4__PHY_LVL_DEBUG_MODE_0__REG DENALI_PHY_30
+#define LPDDR4__PHY_LVL_DEBUG_MODE_0__FLD LPDDR4__DENALI_PHY_30__PHY_LVL_DEBUG_MODE_0
+
+#define LPDDR4__DENALI_PHY_30__SC_PHY_LVL_DEBUG_CONT_0_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_30__SC_PHY_LVL_DEBUG_CONT_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_30__SC_PHY_LVL_DEBUG_CONT_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_30__SC_PHY_LVL_DEBUG_CONT_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_30__SC_PHY_LVL_DEBUG_CONT_0_WOSET 0U
+#define LPDDR4__SC_PHY_LVL_DEBUG_CONT_0__REG DENALI_PHY_30
+#define LPDDR4__SC_PHY_LVL_DEBUG_CONT_0__FLD LPDDR4__DENALI_PHY_30__SC_PHY_LVL_DEBUG_CONT_0
+
+#define LPDDR4__DENALI_PHY_30__PHY_WRLVL_ALGO_0_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_30__PHY_WRLVL_ALGO_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_30__PHY_WRLVL_ALGO_0_WIDTH 2U
+#define LPDDR4__PHY_WRLVL_ALGO_0__REG DENALI_PHY_30
+#define LPDDR4__PHY_WRLVL_ALGO_0__FLD LPDDR4__DENALI_PHY_30__PHY_WRLVL_ALGO_0
+
+#define LPDDR4__DENALI_PHY_30__PHY_WRLVL_CAPTURE_CNT_0_MASK 0x3F000000U
+#define LPDDR4__DENALI_PHY_30__PHY_WRLVL_CAPTURE_CNT_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_30__PHY_WRLVL_CAPTURE_CNT_0_WIDTH 6U
+#define LPDDR4__PHY_WRLVL_CAPTURE_CNT_0__REG DENALI_PHY_30
+#define LPDDR4__PHY_WRLVL_CAPTURE_CNT_0__FLD LPDDR4__DENALI_PHY_30__PHY_WRLVL_CAPTURE_CNT_0
+
+#define LPDDR4__DENALI_PHY_31_READ_MASK 0x0F3FFF0FU
+#define LPDDR4__DENALI_PHY_31_WRITE_MASK 0x0F3FFF0FU
+#define LPDDR4__DENALI_PHY_31__PHY_WRLVL_UPDT_WAIT_CNT_0_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_31__PHY_WRLVL_UPDT_WAIT_CNT_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_31__PHY_WRLVL_UPDT_WAIT_CNT_0_WIDTH 4U
+#define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_0__REG DENALI_PHY_31
+#define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_31__PHY_WRLVL_UPDT_WAIT_CNT_0
+
+#define LPDDR4__DENALI_PHY_31__PHY_DQ_MASK_0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_31__PHY_DQ_MASK_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_31__PHY_DQ_MASK_0_WIDTH 8U
+#define LPDDR4__PHY_DQ_MASK_0__REG DENALI_PHY_31
+#define LPDDR4__PHY_DQ_MASK_0__FLD LPDDR4__DENALI_PHY_31__PHY_DQ_MASK_0
+
+#define LPDDR4__DENALI_PHY_31__PHY_GTLVL_CAPTURE_CNT_0_MASK 0x003F0000U
+#define LPDDR4__DENALI_PHY_31__PHY_GTLVL_CAPTURE_CNT_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_31__PHY_GTLVL_CAPTURE_CNT_0_WIDTH 6U
+#define LPDDR4__PHY_GTLVL_CAPTURE_CNT_0__REG DENALI_PHY_31
+#define LPDDR4__PHY_GTLVL_CAPTURE_CNT_0__FLD LPDDR4__DENALI_PHY_31__PHY_GTLVL_CAPTURE_CNT_0
+
+#define LPDDR4__DENALI_PHY_31__PHY_GTLVL_UPDT_WAIT_CNT_0_MASK 0x0F000000U
+#define LPDDR4__DENALI_PHY_31__PHY_GTLVL_UPDT_WAIT_CNT_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_31__PHY_GTLVL_UPDT_WAIT_CNT_0_WIDTH 4U
+#define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_0__REG DENALI_PHY_31
+#define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_31__PHY_GTLVL_UPDT_WAIT_CNT_0
+
+#define LPDDR4__DENALI_PHY_32_READ_MASK 0x1F030F3FU
+#define LPDDR4__DENALI_PHY_32_WRITE_MASK 0x1F030F3FU
+#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_CAPTURE_CNT_0_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_CAPTURE_CNT_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_CAPTURE_CNT_0_WIDTH 6U
+#define LPDDR4__PHY_RDLVL_CAPTURE_CNT_0__REG DENALI_PHY_32
+#define LPDDR4__PHY_RDLVL_CAPTURE_CNT_0__FLD LPDDR4__DENALI_PHY_32__PHY_RDLVL_CAPTURE_CNT_0
+
+#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_UPDT_WAIT_CNT_0_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_UPDT_WAIT_CNT_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_UPDT_WAIT_CNT_0_WIDTH 4U
+#define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_0__REG DENALI_PHY_32
+#define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_32__PHY_RDLVL_UPDT_WAIT_CNT_0
+
+#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_OP_MODE_0_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_OP_MODE_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_OP_MODE_0_WIDTH 2U
+#define LPDDR4__PHY_RDLVL_OP_MODE_0__REG DENALI_PHY_32
+#define LPDDR4__PHY_RDLVL_OP_MODE_0__FLD LPDDR4__DENALI_PHY_32__PHY_RDLVL_OP_MODE_0
+
+#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0_WIDTH 5U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0__REG DENALI_PHY_32
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_32__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0
+
+#define LPDDR4__DENALI_PHY_33_READ_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_33_WRITE_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_33__PHY_RDLVL_DATA_MASK_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_33__PHY_RDLVL_DATA_MASK_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_33__PHY_RDLVL_DATA_MASK_0_WIDTH 8U
+#define LPDDR4__PHY_RDLVL_DATA_MASK_0__REG DENALI_PHY_33
+#define LPDDR4__PHY_RDLVL_DATA_MASK_0__FLD LPDDR4__DENALI_PHY_33__PHY_RDLVL_DATA_MASK_0
+
+#define LPDDR4__DENALI_PHY_33__PHY_RDLVL_DATA_SWIZZLE_0_MASK 0x03FFFF00U
+#define LPDDR4__DENALI_PHY_33__PHY_RDLVL_DATA_SWIZZLE_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_33__PHY_RDLVL_DATA_SWIZZLE_0_WIDTH 18U
+#define LPDDR4__PHY_RDLVL_DATA_SWIZZLE_0__REG DENALI_PHY_33
+#define LPDDR4__PHY_RDLVL_DATA_SWIZZLE_0__FLD LPDDR4__DENALI_PHY_33__PHY_RDLVL_DATA_SWIZZLE_0
+
+#define LPDDR4__DENALI_PHY_34_READ_MASK 0x00073FFFU
+#define LPDDR4__DENALI_PHY_34_WRITE_MASK 0x00073FFFU
+#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_CLK_JITTER_TOLERANCE_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_CLK_JITTER_TOLERANCE_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_CLK_JITTER_TOLERANCE_0_WIDTH 8U
+#define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_0__REG DENALI_PHY_34
+#define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_0__FLD LPDDR4__DENALI_PHY_34__PHY_WDQLVL_CLK_JITTER_TOLERANCE_0
+
+#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_BURST_CNT_0_MASK 0x00003F00U
+#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_BURST_CNT_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_BURST_CNT_0_WIDTH 6U
+#define LPDDR4__PHY_WDQLVL_BURST_CNT_0__REG DENALI_PHY_34
+#define LPDDR4__PHY_WDQLVL_BURST_CNT_0__FLD LPDDR4__DENALI_PHY_34__PHY_WDQLVL_BURST_CNT_0
+
+#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_PATT_0_MASK 0x00070000U
+#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_PATT_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_PATT_0_WIDTH 3U
+#define LPDDR4__PHY_WDQLVL_PATT_0__REG DENALI_PHY_34
+#define LPDDR4__PHY_WDQLVL_PATT_0__FLD LPDDR4__DENALI_PHY_34__PHY_WDQLVL_PATT_0
+
+#define LPDDR4__DENALI_PHY_35_READ_MASK 0x0F0F07FFU
+#define LPDDR4__DENALI_PHY_35_WRITE_MASK 0x0F0F07FFU
+#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0_WIDTH 11U
+#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0__REG DENALI_PHY_35
+#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0__FLD LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0
+
+#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_UPDT_WAIT_CNT_0_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_UPDT_WAIT_CNT_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_UPDT_WAIT_CNT_0_WIDTH 4U
+#define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_0__REG DENALI_PHY_35
+#define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_35__PHY_WDQLVL_UPDT_WAIT_CNT_0
+
+#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DQDM_OBS_SELECT_0_MASK 0x0F000000U
+#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DQDM_OBS_SELECT_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DQDM_OBS_SELECT_0_WIDTH 4U
+#define LPDDR4__PHY_WDQLVL_DQDM_OBS_SELECT_0__REG DENALI_PHY_35
+#define LPDDR4__PHY_WDQLVL_DQDM_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DQDM_OBS_SELECT_0
+
+#define LPDDR4__DENALI_PHY_36_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_36_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_36__PHY_WDQLVL_PERIODIC_OBS_SELECT_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_36__PHY_WDQLVL_PERIODIC_OBS_SELECT_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_36__PHY_WDQLVL_PERIODIC_OBS_SELECT_0_WIDTH 8U
+#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_SELECT_0__REG DENALI_PHY_36
+#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_36__PHY_WDQLVL_PERIODIC_OBS_SELECT_0
+
+#define LPDDR4__DENALI_PHY_36__PHY_WDQLVL_DQ_SLV_DELTA_0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_36__PHY_WDQLVL_DQ_SLV_DELTA_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_36__PHY_WDQLVL_DQ_SLV_DELTA_0_WIDTH 8U
+#define LPDDR4__PHY_WDQLVL_DQ_SLV_DELTA_0__REG DENALI_PHY_36
+#define LPDDR4__PHY_WDQLVL_DQ_SLV_DELTA_0__FLD LPDDR4__DENALI_PHY_36__PHY_WDQLVL_DQ_SLV_DELTA_0
+
+#define LPDDR4__DENALI_PHY_36__PHY_WDQLVL_DM_DLY_STEP_0_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_36__PHY_WDQLVL_DM_DLY_STEP_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_36__PHY_WDQLVL_DM_DLY_STEP_0_WIDTH 4U
+#define LPDDR4__PHY_WDQLVL_DM_DLY_STEP_0__REG DENALI_PHY_36
+#define LPDDR4__PHY_WDQLVL_DM_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_36__PHY_WDQLVL_DM_DLY_STEP_0
+
+#define LPDDR4__DENALI_PHY_36__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_36__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_36__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_36__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_36__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0_WOSET 0U
+#define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0__REG DENALI_PHY_36
+#define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0__FLD LPDDR4__DENALI_PHY_36__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0
+
+#define LPDDR4__DENALI_PHY_37_READ_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_37_WRITE_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_37__PHY_WDQLVL_DATADM_MASK_0_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_37__PHY_WDQLVL_DATADM_MASK_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_37__PHY_WDQLVL_DATADM_MASK_0_WIDTH 9U
+#define LPDDR4__PHY_WDQLVL_DATADM_MASK_0__REG DENALI_PHY_37
+#define LPDDR4__PHY_WDQLVL_DATADM_MASK_0__FLD LPDDR4__DENALI_PHY_37__PHY_WDQLVL_DATADM_MASK_0
+
+#define LPDDR4__DENALI_PHY_38_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_38_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_38__PHY_USER_PATT0_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_38__PHY_USER_PATT0_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_38__PHY_USER_PATT0_0_WIDTH 32U
+#define LPDDR4__PHY_USER_PATT0_0__REG DENALI_PHY_38
+#define LPDDR4__PHY_USER_PATT0_0__FLD LPDDR4__DENALI_PHY_38__PHY_USER_PATT0_0
+
+#define LPDDR4__DENALI_PHY_39_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_39_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_39__PHY_USER_PATT1_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_39__PHY_USER_PATT1_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_39__PHY_USER_PATT1_0_WIDTH 32U
+#define LPDDR4__PHY_USER_PATT1_0__REG DENALI_PHY_39
+#define LPDDR4__PHY_USER_PATT1_0__FLD LPDDR4__DENALI_PHY_39__PHY_USER_PATT1_0
+
+#define LPDDR4__DENALI_PHY_40_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_40_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_40__PHY_USER_PATT2_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_40__PHY_USER_PATT2_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_40__PHY_USER_PATT2_0_WIDTH 32U
+#define LPDDR4__PHY_USER_PATT2_0__REG DENALI_PHY_40
+#define LPDDR4__PHY_USER_PATT2_0__FLD LPDDR4__DENALI_PHY_40__PHY_USER_PATT2_0
+
+#define LPDDR4__DENALI_PHY_41_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_41_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_41__PHY_USER_PATT3_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_41__PHY_USER_PATT3_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_41__PHY_USER_PATT3_0_WIDTH 32U
+#define LPDDR4__PHY_USER_PATT3_0__REG DENALI_PHY_41
+#define LPDDR4__PHY_USER_PATT3_0__FLD LPDDR4__DENALI_PHY_41__PHY_USER_PATT3_0
+
+#define LPDDR4__DENALI_PHY_42_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PHY_42_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PHY_42__PHY_USER_PATT4_0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_42__PHY_USER_PATT4_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_42__PHY_USER_PATT4_0_WIDTH 16U
+#define LPDDR4__PHY_USER_PATT4_0__REG DENALI_PHY_42
+#define LPDDR4__PHY_USER_PATT4_0__FLD LPDDR4__DENALI_PHY_42__PHY_USER_PATT4_0
+
+#define LPDDR4__DENALI_PHY_42__PHY_NTP_MULT_TRAIN_0_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_42__PHY_NTP_MULT_TRAIN_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_42__PHY_NTP_MULT_TRAIN_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_42__PHY_NTP_MULT_TRAIN_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_42__PHY_NTP_MULT_TRAIN_0_WOSET 0U
+#define LPDDR4__PHY_NTP_MULT_TRAIN_0__REG DENALI_PHY_42
+#define LPDDR4__PHY_NTP_MULT_TRAIN_0__FLD LPDDR4__DENALI_PHY_42__PHY_NTP_MULT_TRAIN_0
+
+#define LPDDR4__DENALI_PHY_43_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_43_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_43__PHY_NTP_EARLY_THRESHOLD_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_43__PHY_NTP_EARLY_THRESHOLD_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_43__PHY_NTP_EARLY_THRESHOLD_0_WIDTH 10U
+#define LPDDR4__PHY_NTP_EARLY_THRESHOLD_0__REG DENALI_PHY_43
+#define LPDDR4__PHY_NTP_EARLY_THRESHOLD_0__FLD LPDDR4__DENALI_PHY_43__PHY_NTP_EARLY_THRESHOLD_0
+
+#define LPDDR4__DENALI_PHY_43__PHY_NTP_PERIOD_THRESHOLD_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_43__PHY_NTP_PERIOD_THRESHOLD_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_43__PHY_NTP_PERIOD_THRESHOLD_0_WIDTH 10U
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_0__REG DENALI_PHY_43
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_0__FLD LPDDR4__DENALI_PHY_43__PHY_NTP_PERIOD_THRESHOLD_0
+
+#define LPDDR4__DENALI_PHY_44_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_44_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_44__PHY_NTP_PERIOD_THRESHOLD_MIN_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_44__PHY_NTP_PERIOD_THRESHOLD_MIN_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_44__PHY_NTP_PERIOD_THRESHOLD_MIN_0_WIDTH 10U
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MIN_0__REG DENALI_PHY_44
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MIN_0__FLD LPDDR4__DENALI_PHY_44__PHY_NTP_PERIOD_THRESHOLD_MIN_0
+
+#define LPDDR4__DENALI_PHY_44__PHY_NTP_PERIOD_THRESHOLD_MAX_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_44__PHY_NTP_PERIOD_THRESHOLD_MAX_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_44__PHY_NTP_PERIOD_THRESHOLD_MAX_0_WIDTH 10U
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_0__REG DENALI_PHY_44
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_0__FLD LPDDR4__DENALI_PHY_44__PHY_NTP_PERIOD_THRESHOLD_MAX_0
+
+#define LPDDR4__DENALI_PHY_45_READ_MASK 0x00FF0001U
+#define LPDDR4__DENALI_PHY_45_WRITE_MASK 0x00FF0001U
+#define LPDDR4__DENALI_PHY_45__PHY_CALVL_VREF_DRIVING_SLICE_0_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_45__PHY_CALVL_VREF_DRIVING_SLICE_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_45__PHY_CALVL_VREF_DRIVING_SLICE_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_45__PHY_CALVL_VREF_DRIVING_SLICE_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_45__PHY_CALVL_VREF_DRIVING_SLICE_0_WOSET 0U
+#define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_0__REG DENALI_PHY_45
+#define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_0__FLD LPDDR4__DENALI_PHY_45__PHY_CALVL_VREF_DRIVING_SLICE_0
+
+#define LPDDR4__DENALI_PHY_45__SC_PHY_MANUAL_CLEAR_0_MASK 0x00003F00U
+#define LPDDR4__DENALI_PHY_45__SC_PHY_MANUAL_CLEAR_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_45__SC_PHY_MANUAL_CLEAR_0_WIDTH 6U
+#define LPDDR4__SC_PHY_MANUAL_CLEAR_0__REG DENALI_PHY_45
+#define LPDDR4__SC_PHY_MANUAL_CLEAR_0__FLD LPDDR4__DENALI_PHY_45__SC_PHY_MANUAL_CLEAR_0
+
+#define LPDDR4__DENALI_PHY_45__PHY_FIFO_PTR_OBS_0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_45__PHY_FIFO_PTR_OBS_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_45__PHY_FIFO_PTR_OBS_0_WIDTH 8U
+#define LPDDR4__PHY_FIFO_PTR_OBS_0__REG DENALI_PHY_45
+#define LPDDR4__PHY_FIFO_PTR_OBS_0__FLD LPDDR4__DENALI_PHY_45__PHY_FIFO_PTR_OBS_0
+
+#define LPDDR4__DENALI_PHY_46_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_46_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_46__PHY_LPBK_RESULT_OBS_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_46__PHY_LPBK_RESULT_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_46__PHY_LPBK_RESULT_OBS_0_WIDTH 32U
+#define LPDDR4__PHY_LPBK_RESULT_OBS_0__REG DENALI_PHY_46
+#define LPDDR4__PHY_LPBK_RESULT_OBS_0__FLD LPDDR4__DENALI_PHY_46__PHY_LPBK_RESULT_OBS_0
+
+#define LPDDR4__DENALI_PHY_47_READ_MASK 0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_47_WRITE_MASK 0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_47__PHY_LPBK_ERROR_COUNT_OBS_0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_47__PHY_LPBK_ERROR_COUNT_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_47__PHY_LPBK_ERROR_COUNT_OBS_0_WIDTH 16U
+#define LPDDR4__PHY_LPBK_ERROR_COUNT_OBS_0__REG DENALI_PHY_47
+#define LPDDR4__PHY_LPBK_ERROR_COUNT_OBS_0__FLD LPDDR4__DENALI_PHY_47__PHY_LPBK_ERROR_COUNT_OBS_0
+
+#define LPDDR4__DENALI_PHY_47__PHY_MASTER_DLY_LOCK_OBS_0_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_47__PHY_MASTER_DLY_LOCK_OBS_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_47__PHY_MASTER_DLY_LOCK_OBS_0_WIDTH 11U
+#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_0__REG DENALI_PHY_47
+#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_0__FLD LPDDR4__DENALI_PHY_47__PHY_MASTER_DLY_LOCK_OBS_0
+
+#define LPDDR4__DENALI_PHY_48_READ_MASK 0xFFFF7F7FU
+#define LPDDR4__DENALI_PHY_48_WRITE_MASK 0xFFFF7F7FU
+#define LPDDR4__DENALI_PHY_48__PHY_RDDQ_SLV_DLY_ENC_OBS_0_MASK 0x0000007FU
+#define LPDDR4__DENALI_PHY_48__PHY_RDDQ_SLV_DLY_ENC_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_48__PHY_RDDQ_SLV_DLY_ENC_OBS_0_WIDTH 7U
+#define LPDDR4__PHY_RDDQ_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_48
+#define LPDDR4__PHY_RDDQ_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_48__PHY_RDDQ_SLV_DLY_ENC_OBS_0
+
+#define LPDDR4__DENALI_PHY_48__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0_MASK 0x00007F00U
+#define LPDDR4__DENALI_PHY_48__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_48__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0_WIDTH 7U
+#define LPDDR4__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_48
+#define LPDDR4__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_48__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0
+
+#define LPDDR4__DENALI_PHY_48__PHY_MEAS_DLY_STEP_VALUE_0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_48__PHY_MEAS_DLY_STEP_VALUE_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_48__PHY_MEAS_DLY_STEP_VALUE_0_WIDTH 8U
+#define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_0__REG DENALI_PHY_48
+#define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_0__FLD LPDDR4__DENALI_PHY_48__PHY_MEAS_DLY_STEP_VALUE_0
+
+#define LPDDR4__DENALI_PHY_48__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_48__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_48__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0_WIDTH 8U
+#define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_48
+#define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_48__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0
+
+#define LPDDR4__DENALI_PHY_49_READ_MASK 0x7F07FFFFU
+#define LPDDR4__DENALI_PHY_49_WRITE_MASK 0x7F07FFFFU
+#define LPDDR4__DENALI_PHY_49__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_49__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_49__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0_WIDTH 8U
+#define LPDDR4__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_49
+#define LPDDR4__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_49__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0
+
+#define LPDDR4__DENALI_PHY_49__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0_MASK 0x0007FF00U
+#define LPDDR4__DENALI_PHY_49__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_49__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0_WIDTH 11U
+#define LPDDR4__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_49
+#define LPDDR4__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_49__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0
+
+#define LPDDR4__DENALI_PHY_49__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0_MASK 0x7F000000U
+#define LPDDR4__DENALI_PHY_49__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_49__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0_WIDTH 7U
+#define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_49
+#define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_49__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0
+
+#define LPDDR4__DENALI_PHY_50_READ_MASK 0x0007FFFFU
+#define LPDDR4__DENALI_PHY_50_WRITE_MASK 0x0007FFFFU
+#define LPDDR4__DENALI_PHY_50__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_50__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_50__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0_WIDTH 8U
+#define LPDDR4__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_50
+#define LPDDR4__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_50__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0
+
+#define LPDDR4__DENALI_PHY_50__PHY_WR_ADDER_SLV_DLY_ENC_OBS_0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_50__PHY_WR_ADDER_SLV_DLY_ENC_OBS_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_50__PHY_WR_ADDER_SLV_DLY_ENC_OBS_0_WIDTH 8U
+#define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_50
+#define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_50__PHY_WR_ADDER_SLV_DLY_ENC_OBS_0
+
+#define LPDDR4__DENALI_PHY_50__PHY_WR_SHIFT_OBS_0_MASK 0x00070000U
+#define LPDDR4__DENALI_PHY_50__PHY_WR_SHIFT_OBS_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_50__PHY_WR_SHIFT_OBS_0_WIDTH 3U
+#define LPDDR4__PHY_WR_SHIFT_OBS_0__REG DENALI_PHY_50
+#define LPDDR4__PHY_WR_SHIFT_OBS_0__FLD LPDDR4__DENALI_PHY_50__PHY_WR_SHIFT_OBS_0
+
+#define LPDDR4__DENALI_PHY_51_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_51_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_51__PHY_WRLVL_HARD0_DELAY_OBS_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_51__PHY_WRLVL_HARD0_DELAY_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_51__PHY_WRLVL_HARD0_DELAY_OBS_0_WIDTH 10U
+#define LPDDR4__PHY_WRLVL_HARD0_DELAY_OBS_0__REG DENALI_PHY_51
+#define LPDDR4__PHY_WRLVL_HARD0_DELAY_OBS_0__FLD LPDDR4__DENALI_PHY_51__PHY_WRLVL_HARD0_DELAY_OBS_0
+
+#define LPDDR4__DENALI_PHY_51__PHY_WRLVL_HARD1_DELAY_OBS_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_51__PHY_WRLVL_HARD1_DELAY_OBS_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_51__PHY_WRLVL_HARD1_DELAY_OBS_0_WIDTH 10U
+#define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_0__REG DENALI_PHY_51
+#define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_0__FLD LPDDR4__DENALI_PHY_51__PHY_WRLVL_HARD1_DELAY_OBS_0
+
+#define LPDDR4__DENALI_PHY_52_READ_MASK 0x001FFFFFU
+#define LPDDR4__DENALI_PHY_52_WRITE_MASK 0x001FFFFFU
+#define LPDDR4__DENALI_PHY_52__PHY_WRLVL_STATUS_OBS_0_MASK 0x001FFFFFU
+#define LPDDR4__DENALI_PHY_52__PHY_WRLVL_STATUS_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_52__PHY_WRLVL_STATUS_OBS_0_WIDTH 21U
+#define LPDDR4__PHY_WRLVL_STATUS_OBS_0__REG DENALI_PHY_52
+#define LPDDR4__PHY_WRLVL_STATUS_OBS_0__FLD LPDDR4__DENALI_PHY_52__PHY_WRLVL_STATUS_OBS_0
+
+#define LPDDR4__DENALI_PHY_53_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_53_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_53__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_53__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_53__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0_WIDTH 10U
+#define LPDDR4__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_53
+#define LPDDR4__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_53__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0
+
+#define LPDDR4__DENALI_PHY_53__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_53__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_53__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0_WIDTH 10U
+#define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_53
+#define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_53__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0
+
+#define LPDDR4__DENALI_PHY_54_READ_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_54_WRITE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_54__PHY_WRLVL_ERROR_OBS_0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_54__PHY_WRLVL_ERROR_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_54__PHY_WRLVL_ERROR_OBS_0_WIDTH 16U
+#define LPDDR4__PHY_WRLVL_ERROR_OBS_0__REG DENALI_PHY_54
+#define LPDDR4__PHY_WRLVL_ERROR_OBS_0__FLD LPDDR4__DENALI_PHY_54__PHY_WRLVL_ERROR_OBS_0
+
+#define LPDDR4__DENALI_PHY_54__PHY_GTLVL_HARD0_DELAY_OBS_0_MASK 0x3FFF0000U
+#define LPDDR4__DENALI_PHY_54__PHY_GTLVL_HARD0_DELAY_OBS_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_54__PHY_GTLVL_HARD0_DELAY_OBS_0_WIDTH 14U
+#define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_0__REG DENALI_PHY_54
+#define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_0__FLD LPDDR4__DENALI_PHY_54__PHY_GTLVL_HARD0_DELAY_OBS_0
+
+#define LPDDR4__DENALI_PHY_55_READ_MASK 0x00003FFFU
+#define LPDDR4__DENALI_PHY_55_WRITE_MASK 0x00003FFFU
+#define LPDDR4__DENALI_PHY_55__PHY_GTLVL_HARD1_DELAY_OBS_0_MASK 0x00003FFFU
+#define LPDDR4__DENALI_PHY_55__PHY_GTLVL_HARD1_DELAY_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_55__PHY_GTLVL_HARD1_DELAY_OBS_0_WIDTH 14U
+#define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_0__REG DENALI_PHY_55
+#define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_0__FLD LPDDR4__DENALI_PHY_55__PHY_GTLVL_HARD1_DELAY_OBS_0
+
+#define LPDDR4__DENALI_PHY_56_READ_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_56_WRITE_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_56__PHY_GTLVL_STATUS_OBS_0_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_56__PHY_GTLVL_STATUS_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_56__PHY_GTLVL_STATUS_OBS_0_WIDTH 18U
+#define LPDDR4__PHY_GTLVL_STATUS_OBS_0__REG DENALI_PHY_56
+#define LPDDR4__PHY_GTLVL_STATUS_OBS_0__FLD LPDDR4__DENALI_PHY_56__PHY_GTLVL_STATUS_OBS_0
+
+#define LPDDR4__DENALI_PHY_57_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_57_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_57__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_57__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_57__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0_WIDTH 10U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0__REG DENALI_PHY_57
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_57__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0
+
+#define LPDDR4__DENALI_PHY_57__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_57__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_57__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0_WIDTH 10U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0__REG DENALI_PHY_57
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_57__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0
+
+#define LPDDR4__DENALI_PHY_58_READ_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_58_WRITE_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_58__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_58__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_58__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0_WIDTH 2U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0__REG DENALI_PHY_58
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0__FLD LPDDR4__DENALI_PHY_58__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0
+
+#define LPDDR4__DENALI_PHY_59_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_59_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_59__PHY_RDLVL_STATUS_OBS_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_59__PHY_RDLVL_STATUS_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_59__PHY_RDLVL_STATUS_OBS_0_WIDTH 32U
+#define LPDDR4__PHY_RDLVL_STATUS_OBS_0__REG DENALI_PHY_59
+#define LPDDR4__PHY_RDLVL_STATUS_OBS_0__FLD LPDDR4__DENALI_PHY_59__PHY_RDLVL_STATUS_OBS_0
+
+#define LPDDR4__DENALI_PHY_60_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_60_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_60__PHY_WDQLVL_DQDM_LE_DLY_OBS_0_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_60__PHY_WDQLVL_DQDM_LE_DLY_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_60__PHY_WDQLVL_DQDM_LE_DLY_OBS_0_WIDTH 11U
+#define LPDDR4__PHY_WDQLVL_DQDM_LE_DLY_OBS_0__REG DENALI_PHY_60
+#define LPDDR4__PHY_WDQLVL_DQDM_LE_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_60__PHY_WDQLVL_DQDM_LE_DLY_OBS_0
+
+#define LPDDR4__DENALI_PHY_60__PHY_WDQLVL_DQDM_TE_DLY_OBS_0_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_60__PHY_WDQLVL_DQDM_TE_DLY_OBS_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_60__PHY_WDQLVL_DQDM_TE_DLY_OBS_0_WIDTH 11U
+#define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_0__REG DENALI_PHY_60
+#define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_60__PHY_WDQLVL_DQDM_TE_DLY_OBS_0
+
+#define LPDDR4__DENALI_PHY_61_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_61_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_61__PHY_WDQLVL_STATUS_OBS_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_61__PHY_WDQLVL_STATUS_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_61__PHY_WDQLVL_STATUS_OBS_0_WIDTH 32U
+#define LPDDR4__PHY_WDQLVL_STATUS_OBS_0__REG DENALI_PHY_61
+#define LPDDR4__PHY_WDQLVL_STATUS_OBS_0__FLD LPDDR4__DENALI_PHY_61__PHY_WDQLVL_STATUS_OBS_0
+
+#define LPDDR4__DENALI_PHY_62_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_62_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_62__PHY_WDQLVL_PERIODIC_OBS_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_62__PHY_WDQLVL_PERIODIC_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_62__PHY_WDQLVL_PERIODIC_OBS_0_WIDTH 32U
+#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_0__REG DENALI_PHY_62
+#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_0__FLD LPDDR4__DENALI_PHY_62__PHY_WDQLVL_PERIODIC_OBS_0
+
+#define LPDDR4__DENALI_PHY_63_READ_MASK 0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_63_WRITE_MASK 0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_63__PHY_DDL_MODE_0_MASK 0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_63__PHY_DDL_MODE_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_63__PHY_DDL_MODE_0_WIDTH 31U
+#define LPDDR4__PHY_DDL_MODE_0__REG DENALI_PHY_63
+#define LPDDR4__PHY_DDL_MODE_0__FLD LPDDR4__DENALI_PHY_63__PHY_DDL_MODE_0
+
+#define LPDDR4__DENALI_PHY_64_READ_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_64_WRITE_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_64__PHY_DDL_MASK_0_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_64__PHY_DDL_MASK_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_64__PHY_DDL_MASK_0_WIDTH 6U
+#define LPDDR4__PHY_DDL_MASK_0__REG DENALI_PHY_64
+#define LPDDR4__PHY_DDL_MASK_0__FLD LPDDR4__DENALI_PHY_64__PHY_DDL_MASK_0
+
+#define LPDDR4__DENALI_PHY_65_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_65_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_65__PHY_DDL_TEST_OBS_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_65__PHY_DDL_TEST_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_65__PHY_DDL_TEST_OBS_0_WIDTH 32U
+#define LPDDR4__PHY_DDL_TEST_OBS_0__REG DENALI_PHY_65
+#define LPDDR4__PHY_DDL_TEST_OBS_0__FLD LPDDR4__DENALI_PHY_65__PHY_DDL_TEST_OBS_0
+
+#define LPDDR4__DENALI_PHY_66_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_66_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_66__PHY_DDL_TEST_MSTR_DLY_OBS_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_66__PHY_DDL_TEST_MSTR_DLY_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_66__PHY_DDL_TEST_MSTR_DLY_OBS_0_WIDTH 32U
+#define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_0__REG DENALI_PHY_66
+#define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_66__PHY_DDL_TEST_MSTR_DLY_OBS_0
+
+#define LPDDR4__DENALI_PHY_67_READ_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_67_WRITE_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_67__PHY_DDL_TRACK_UPD_THRESHOLD_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_67__PHY_DDL_TRACK_UPD_THRESHOLD_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_67__PHY_DDL_TRACK_UPD_THRESHOLD_0_WIDTH 8U
+#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_0__REG DENALI_PHY_67
+#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_0__FLD LPDDR4__DENALI_PHY_67__PHY_DDL_TRACK_UPD_THRESHOLD_0
+
+#define LPDDR4__DENALI_PHY_67__PHY_LP4_WDQS_OE_EXTEND_0_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_67__PHY_LP4_WDQS_OE_EXTEND_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_67__PHY_LP4_WDQS_OE_EXTEND_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_67__PHY_LP4_WDQS_OE_EXTEND_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_67__PHY_LP4_WDQS_OE_EXTEND_0_WOSET 0U
+#define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_0__REG DENALI_PHY_67
+#define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_0__FLD LPDDR4__DENALI_PHY_67__PHY_LP4_WDQS_OE_EXTEND_0
+
+#define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ0_0_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ0_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ0_0_WIDTH 9U
+#define LPDDR4__PHY_RX_CAL_DQ0_0__REG DENALI_PHY_67
+#define LPDDR4__PHY_RX_CAL_DQ0_0__FLD LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ0_0
+
+#define LPDDR4__DENALI_PHY_68_READ_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_68_WRITE_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ1_0_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ1_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ1_0_WIDTH 9U
+#define LPDDR4__PHY_RX_CAL_DQ1_0__REG DENALI_PHY_68
+#define LPDDR4__PHY_RX_CAL_DQ1_0__FLD LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ1_0
+
+#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ2_0_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ2_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ2_0_WIDTH 9U
+#define LPDDR4__PHY_RX_CAL_DQ2_0__REG DENALI_PHY_68
+#define LPDDR4__PHY_RX_CAL_DQ2_0__FLD LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ2_0
+
+#define LPDDR4__DENALI_PHY_69_READ_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_69_WRITE_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ3_0_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ3_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ3_0_WIDTH 9U
+#define LPDDR4__PHY_RX_CAL_DQ3_0__REG DENALI_PHY_69
+#define LPDDR4__PHY_RX_CAL_DQ3_0__FLD LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ3_0
+
+#define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ4_0_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ4_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ4_0_WIDTH 9U
+#define LPDDR4__PHY_RX_CAL_DQ4_0__REG DENALI_PHY_69
+#define LPDDR4__PHY_RX_CAL_DQ4_0__FLD LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ4_0
+
+#define LPDDR4__DENALI_PHY_70_READ_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_70_WRITE_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ5_0_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ5_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ5_0_WIDTH 9U
+#define LPDDR4__PHY_RX_CAL_DQ5_0__REG DENALI_PHY_70
+#define LPDDR4__PHY_RX_CAL_DQ5_0__FLD LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ5_0
+
+#define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ6_0_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ6_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ6_0_WIDTH 9U
+#define LPDDR4__PHY_RX_CAL_DQ6_0__REG DENALI_PHY_70
+#define LPDDR4__PHY_RX_CAL_DQ6_0__FLD LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ6_0
+
+#define LPDDR4__DENALI_PHY_71_READ_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_71_WRITE_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_71__PHY_RX_CAL_DQ7_0_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_71__PHY_RX_CAL_DQ7_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_71__PHY_RX_CAL_DQ7_0_WIDTH 9U
+#define LPDDR4__PHY_RX_CAL_DQ7_0__REG DENALI_PHY_71
+#define LPDDR4__PHY_RX_CAL_DQ7_0__FLD LPDDR4__DENALI_PHY_71__PHY_RX_CAL_DQ7_0
+
+#define LPDDR4__DENALI_PHY_72_READ_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_72_WRITE_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_72__PHY_RX_CAL_DM_0_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_72__PHY_RX_CAL_DM_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_72__PHY_RX_CAL_DM_0_WIDTH 18U
+#define LPDDR4__PHY_RX_CAL_DM_0__REG DENALI_PHY_72
+#define LPDDR4__PHY_RX_CAL_DM_0__FLD LPDDR4__DENALI_PHY_72__PHY_RX_CAL_DM_0
+
+#define LPDDR4__DENALI_PHY_73_READ_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_73_WRITE_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_73__PHY_RX_CAL_DQS_0_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_73__PHY_RX_CAL_DQS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_73__PHY_RX_CAL_DQS_0_WIDTH 9U
+#define LPDDR4__PHY_RX_CAL_DQS_0__REG DENALI_PHY_73
+#define LPDDR4__PHY_RX_CAL_DQS_0__FLD LPDDR4__DENALI_PHY_73__PHY_RX_CAL_DQS_0
+
+#define LPDDR4__DENALI_PHY_73__PHY_RX_CAL_FDBK_0_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_73__PHY_RX_CAL_FDBK_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_73__PHY_RX_CAL_FDBK_0_WIDTH 9U
+#define LPDDR4__PHY_RX_CAL_FDBK_0__REG DENALI_PHY_73
+#define LPDDR4__PHY_RX_CAL_FDBK_0__FLD LPDDR4__DENALI_PHY_73__PHY_RX_CAL_FDBK_0
+
+#define LPDDR4__DENALI_PHY_74_READ_MASK 0xFF1F07FFU
+#define LPDDR4__DENALI_PHY_74_WRITE_MASK 0xFF1F07FFU
+#define LPDDR4__DENALI_PHY_74__PHY_PAD_RX_BIAS_EN_0_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_74__PHY_PAD_RX_BIAS_EN_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_74__PHY_PAD_RX_BIAS_EN_0_WIDTH 11U
+#define LPDDR4__PHY_PAD_RX_BIAS_EN_0__REG DENALI_PHY_74
+#define LPDDR4__PHY_PAD_RX_BIAS_EN_0__FLD LPDDR4__DENALI_PHY_74__PHY_PAD_RX_BIAS_EN_0
+
+#define LPDDR4__DENALI_PHY_74__PHY_STATIC_TOG_DISABLE_0_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_74__PHY_STATIC_TOG_DISABLE_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_74__PHY_STATIC_TOG_DISABLE_0_WIDTH 5U
+#define LPDDR4__PHY_STATIC_TOG_DISABLE_0__REG DENALI_PHY_74
+#define LPDDR4__PHY_STATIC_TOG_DISABLE_0__FLD LPDDR4__DENALI_PHY_74__PHY_STATIC_TOG_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_74__PHY_DATA_DC_CAL_SAMPLE_WAIT_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_74__PHY_DATA_DC_CAL_SAMPLE_WAIT_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_74__PHY_DATA_DC_CAL_SAMPLE_WAIT_0_WIDTH 8U
+#define LPDDR4__PHY_DATA_DC_CAL_SAMPLE_WAIT_0__REG DENALI_PHY_74
+#define LPDDR4__PHY_DATA_DC_CAL_SAMPLE_WAIT_0__FLD LPDDR4__DENALI_PHY_74__PHY_DATA_DC_CAL_SAMPLE_WAIT_0
+
+#define LPDDR4__DENALI_PHY_75_READ_MASK 0xFF3F03FFU
+#define LPDDR4__DENALI_PHY_75_WRITE_MASK 0xFF3F03FFU
+#define LPDDR4__DENALI_PHY_75__PHY_DATA_DC_CAL_TIMEOUT_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_75__PHY_DATA_DC_CAL_TIMEOUT_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_75__PHY_DATA_DC_CAL_TIMEOUT_0_WIDTH 8U
+#define LPDDR4__PHY_DATA_DC_CAL_TIMEOUT_0__REG DENALI_PHY_75
+#define LPDDR4__PHY_DATA_DC_CAL_TIMEOUT_0__FLD LPDDR4__DENALI_PHY_75__PHY_DATA_DC_CAL_TIMEOUT_0
+
+#define LPDDR4__DENALI_PHY_75__PHY_DATA_DC_WEIGHT_0_MASK 0x00000300U
+#define LPDDR4__DENALI_PHY_75__PHY_DATA_DC_WEIGHT_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_75__PHY_DATA_DC_WEIGHT_0_WIDTH 2U
+#define LPDDR4__PHY_DATA_DC_WEIGHT_0__REG DENALI_PHY_75
+#define LPDDR4__PHY_DATA_DC_WEIGHT_0__FLD LPDDR4__DENALI_PHY_75__PHY_DATA_DC_WEIGHT_0
+
+#define LPDDR4__DENALI_PHY_75__PHY_DATA_DC_ADJUST_START_0_MASK 0x003F0000U
+#define LPDDR4__DENALI_PHY_75__PHY_DATA_DC_ADJUST_START_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_75__PHY_DATA_DC_ADJUST_START_0_WIDTH 6U
+#define LPDDR4__PHY_DATA_DC_ADJUST_START_0__REG DENALI_PHY_75
+#define LPDDR4__PHY_DATA_DC_ADJUST_START_0__FLD LPDDR4__DENALI_PHY_75__PHY_DATA_DC_ADJUST_START_0
+
+#define LPDDR4__DENALI_PHY_75__PHY_DATA_DC_ADJUST_SAMPLE_CNT_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_75__PHY_DATA_DC_ADJUST_SAMPLE_CNT_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_75__PHY_DATA_DC_ADJUST_SAMPLE_CNT_0_WIDTH 8U
+#define LPDDR4__PHY_DATA_DC_ADJUST_SAMPLE_CNT_0__REG DENALI_PHY_75
+#define LPDDR4__PHY_DATA_DC_ADJUST_SAMPLE_CNT_0__FLD LPDDR4__DENALI_PHY_75__PHY_DATA_DC_ADJUST_SAMPLE_CNT_0
+
+#define LPDDR4__DENALI_PHY_76_READ_MASK 0x010101FFU
+#define LPDDR4__DENALI_PHY_76_WRITE_MASK 0x010101FFU
+#define LPDDR4__DENALI_PHY_76__PHY_DATA_DC_ADJUST_THRSHLD_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_76__PHY_DATA_DC_ADJUST_THRSHLD_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_76__PHY_DATA_DC_ADJUST_THRSHLD_0_WIDTH 8U
+#define LPDDR4__PHY_DATA_DC_ADJUST_THRSHLD_0__REG DENALI_PHY_76
+#define LPDDR4__PHY_DATA_DC_ADJUST_THRSHLD_0__FLD LPDDR4__DENALI_PHY_76__PHY_DATA_DC_ADJUST_THRSHLD_0
+
+#define LPDDR4__DENALI_PHY_76__PHY_DATA_DC_ADJUST_DIRECT_0_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_76__PHY_DATA_DC_ADJUST_DIRECT_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_76__PHY_DATA_DC_ADJUST_DIRECT_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_76__PHY_DATA_DC_ADJUST_DIRECT_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_76__PHY_DATA_DC_ADJUST_DIRECT_0_WOSET 0U
+#define LPDDR4__PHY_DATA_DC_ADJUST_DIRECT_0__REG DENALI_PHY_76
+#define LPDDR4__PHY_DATA_DC_ADJUST_DIRECT_0__FLD LPDDR4__DENALI_PHY_76__PHY_DATA_DC_ADJUST_DIRECT_0
+
+#define LPDDR4__DENALI_PHY_76__PHY_DATA_DC_CAL_POLARITY_0_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_76__PHY_DATA_DC_CAL_POLARITY_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_76__PHY_DATA_DC_CAL_POLARITY_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_76__PHY_DATA_DC_CAL_POLARITY_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_76__PHY_DATA_DC_CAL_POLARITY_0_WOSET 0U
+#define LPDDR4__PHY_DATA_DC_CAL_POLARITY_0__REG DENALI_PHY_76
+#define LPDDR4__PHY_DATA_DC_CAL_POLARITY_0__FLD LPDDR4__DENALI_PHY_76__PHY_DATA_DC_CAL_POLARITY_0
+
+#define LPDDR4__DENALI_PHY_76__PHY_DATA_DC_CAL_START_0_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_76__PHY_DATA_DC_CAL_START_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_76__PHY_DATA_DC_CAL_START_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_76__PHY_DATA_DC_CAL_START_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_76__PHY_DATA_DC_CAL_START_0_WOSET 0U
+#define LPDDR4__PHY_DATA_DC_CAL_START_0__REG DENALI_PHY_76
+#define LPDDR4__PHY_DATA_DC_CAL_START_0__FLD LPDDR4__DENALI_PHY_76__PHY_DATA_DC_CAL_START_0
+
+#define LPDDR4__DENALI_PHY_77_READ_MASK 0x01010703U
+#define LPDDR4__DENALI_PHY_77_WRITE_MASK 0x01010703U
+#define LPDDR4__DENALI_PHY_77__PHY_DATA_DC_SW_RANK_0_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_77__PHY_DATA_DC_SW_RANK_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_77__PHY_DATA_DC_SW_RANK_0_WIDTH 2U
+#define LPDDR4__PHY_DATA_DC_SW_RANK_0__REG DENALI_PHY_77
+#define LPDDR4__PHY_DATA_DC_SW_RANK_0__FLD LPDDR4__DENALI_PHY_77__PHY_DATA_DC_SW_RANK_0
+
+#define LPDDR4__DENALI_PHY_77__PHY_FDBK_PWR_CTRL_0_MASK 0x00000700U
+#define LPDDR4__DENALI_PHY_77__PHY_FDBK_PWR_CTRL_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_77__PHY_FDBK_PWR_CTRL_0_WIDTH 3U
+#define LPDDR4__PHY_FDBK_PWR_CTRL_0__REG DENALI_PHY_77
+#define LPDDR4__PHY_FDBK_PWR_CTRL_0__FLD LPDDR4__DENALI_PHY_77__PHY_FDBK_PWR_CTRL_0
+
+#define LPDDR4__DENALI_PHY_77__PHY_SLV_DLY_CTRL_GATE_DISABLE_0_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_77__PHY_SLV_DLY_CTRL_GATE_DISABLE_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_77__PHY_SLV_DLY_CTRL_GATE_DISABLE_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_77__PHY_SLV_DLY_CTRL_GATE_DISABLE_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_77__PHY_SLV_DLY_CTRL_GATE_DISABLE_0_WOSET 0U
+#define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_0__REG DENALI_PHY_77
+#define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_77__PHY_SLV_DLY_CTRL_GATE_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_77__PHY_RDPATH_GATE_DISABLE_0_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_77__PHY_RDPATH_GATE_DISABLE_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_77__PHY_RDPATH_GATE_DISABLE_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_77__PHY_RDPATH_GATE_DISABLE_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_77__PHY_RDPATH_GATE_DISABLE_0_WOSET 0U
+#define LPDDR4__PHY_RDPATH_GATE_DISABLE_0__REG DENALI_PHY_77
+#define LPDDR4__PHY_RDPATH_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_77__PHY_RDPATH_GATE_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_78_READ_MASK 0x00000101U
+#define LPDDR4__DENALI_PHY_78_WRITE_MASK 0x00000101U
+#define LPDDR4__DENALI_PHY_78__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_78__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_78__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_78__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_78__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0_WOSET 0U
+#define LPDDR4__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0__REG DENALI_PHY_78
+#define LPDDR4__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_78__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_78__PHY_SLICE_PWR_RDC_DISABLE_0_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_78__PHY_SLICE_PWR_RDC_DISABLE_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_78__PHY_SLICE_PWR_RDC_DISABLE_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_78__PHY_SLICE_PWR_RDC_DISABLE_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_78__PHY_SLICE_PWR_RDC_DISABLE_0_WOSET 0U
+#define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_0__REG DENALI_PHY_78
+#define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_0__FLD LPDDR4__DENALI_PHY_78__PHY_SLICE_PWR_RDC_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_79_READ_MASK 0x07FFFF07U
+#define LPDDR4__DENALI_PHY_79_WRITE_MASK 0x07FFFF07U
+#define LPDDR4__DENALI_PHY_79__PHY_DQ_TSEL_ENABLE_0_MASK 0x00000007U
+#define LPDDR4__DENALI_PHY_79__PHY_DQ_TSEL_ENABLE_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_79__PHY_DQ_TSEL_ENABLE_0_WIDTH 3U
+#define LPDDR4__PHY_DQ_TSEL_ENABLE_0__REG DENALI_PHY_79
+#define LPDDR4__PHY_DQ_TSEL_ENABLE_0__FLD LPDDR4__DENALI_PHY_79__PHY_DQ_TSEL_ENABLE_0
+
+#define LPDDR4__DENALI_PHY_79__PHY_DQ_TSEL_SELECT_0_MASK 0x00FFFF00U
+#define LPDDR4__DENALI_PHY_79__PHY_DQ_TSEL_SELECT_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_79__PHY_DQ_TSEL_SELECT_0_WIDTH 16U
+#define LPDDR4__PHY_DQ_TSEL_SELECT_0__REG DENALI_PHY_79
+#define LPDDR4__PHY_DQ_TSEL_SELECT_0__FLD LPDDR4__DENALI_PHY_79__PHY_DQ_TSEL_SELECT_0
+
+#define LPDDR4__DENALI_PHY_79__PHY_DQS_TSEL_ENABLE_0_MASK 0x07000000U
+#define LPDDR4__DENALI_PHY_79__PHY_DQS_TSEL_ENABLE_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_79__PHY_DQS_TSEL_ENABLE_0_WIDTH 3U
+#define LPDDR4__PHY_DQS_TSEL_ENABLE_0__REG DENALI_PHY_79
+#define LPDDR4__PHY_DQS_TSEL_ENABLE_0__FLD LPDDR4__DENALI_PHY_79__PHY_DQS_TSEL_ENABLE_0
+
+#define LPDDR4__DENALI_PHY_80_READ_MASK 0x7F03FFFFU
+#define LPDDR4__DENALI_PHY_80_WRITE_MASK 0x7F03FFFFU
+#define LPDDR4__DENALI_PHY_80__PHY_DQS_TSEL_SELECT_0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_80__PHY_DQS_TSEL_SELECT_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_80__PHY_DQS_TSEL_SELECT_0_WIDTH 16U
+#define LPDDR4__PHY_DQS_TSEL_SELECT_0__REG DENALI_PHY_80
+#define LPDDR4__PHY_DQS_TSEL_SELECT_0__FLD LPDDR4__DENALI_PHY_80__PHY_DQS_TSEL_SELECT_0
+
+#define LPDDR4__DENALI_PHY_80__PHY_TWO_CYC_PREAMBLE_0_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_80__PHY_TWO_CYC_PREAMBLE_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_80__PHY_TWO_CYC_PREAMBLE_0_WIDTH 2U
+#define LPDDR4__PHY_TWO_CYC_PREAMBLE_0__REG DENALI_PHY_80
+#define LPDDR4__PHY_TWO_CYC_PREAMBLE_0__FLD LPDDR4__DENALI_PHY_80__PHY_TWO_CYC_PREAMBLE_0
+
+#define LPDDR4__DENALI_PHY_80__PHY_VREF_INITIAL_START_POINT_0_MASK 0x7F000000U
+#define LPDDR4__DENALI_PHY_80__PHY_VREF_INITIAL_START_POINT_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_80__PHY_VREF_INITIAL_START_POINT_0_WIDTH 7U
+#define LPDDR4__PHY_VREF_INITIAL_START_POINT_0__REG DENALI_PHY_80
+#define LPDDR4__PHY_VREF_INITIAL_START_POINT_0__FLD LPDDR4__DENALI_PHY_80__PHY_VREF_INITIAL_START_POINT_0
+
+#define LPDDR4__DENALI_PHY_81_READ_MASK 0xFF01037FU
+#define LPDDR4__DENALI_PHY_81_WRITE_MASK 0xFF01037FU
+#define LPDDR4__DENALI_PHY_81__PHY_VREF_INITIAL_STOP_POINT_0_MASK 0x0000007FU
+#define LPDDR4__DENALI_PHY_81__PHY_VREF_INITIAL_STOP_POINT_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_81__PHY_VREF_INITIAL_STOP_POINT_0_WIDTH 7U
+#define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_0__REG DENALI_PHY_81
+#define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_0__FLD LPDDR4__DENALI_PHY_81__PHY_VREF_INITIAL_STOP_POINT_0
+
+#define LPDDR4__DENALI_PHY_81__PHY_VREF_TRAINING_CTRL_0_MASK 0x00000300U
+#define LPDDR4__DENALI_PHY_81__PHY_VREF_TRAINING_CTRL_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_81__PHY_VREF_TRAINING_CTRL_0_WIDTH 2U
+#define LPDDR4__PHY_VREF_TRAINING_CTRL_0__REG DENALI_PHY_81
+#define LPDDR4__PHY_VREF_TRAINING_CTRL_0__FLD LPDDR4__DENALI_PHY_81__PHY_VREF_TRAINING_CTRL_0
+
+#define LPDDR4__DENALI_PHY_81__PHY_NTP_TRAIN_EN_0_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_81__PHY_NTP_TRAIN_EN_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_81__PHY_NTP_TRAIN_EN_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_81__PHY_NTP_TRAIN_EN_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_81__PHY_NTP_TRAIN_EN_0_WOSET 0U
+#define LPDDR4__PHY_NTP_TRAIN_EN_0__REG DENALI_PHY_81
+#define LPDDR4__PHY_NTP_TRAIN_EN_0__FLD LPDDR4__DENALI_PHY_81__PHY_NTP_TRAIN_EN_0
+
+#define LPDDR4__DENALI_PHY_81__PHY_NTP_WDQ_STEP_SIZE_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_81__PHY_NTP_WDQ_STEP_SIZE_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_81__PHY_NTP_WDQ_STEP_SIZE_0_WIDTH 8U
+#define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_0__REG DENALI_PHY_81
+#define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_0__FLD LPDDR4__DENALI_PHY_81__PHY_NTP_WDQ_STEP_SIZE_0
+
+#define LPDDR4__DENALI_PHY_82_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_82_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_82__PHY_NTP_WDQ_START_0_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_82__PHY_NTP_WDQ_START_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_82__PHY_NTP_WDQ_START_0_WIDTH 11U
+#define LPDDR4__PHY_NTP_WDQ_START_0__REG DENALI_PHY_82
+#define LPDDR4__PHY_NTP_WDQ_START_0__FLD LPDDR4__DENALI_PHY_82__PHY_NTP_WDQ_START_0
+
+#define LPDDR4__DENALI_PHY_82__PHY_NTP_WDQ_STOP_0_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_82__PHY_NTP_WDQ_STOP_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_82__PHY_NTP_WDQ_STOP_0_WIDTH 11U
+#define LPDDR4__PHY_NTP_WDQ_STOP_0__REG DENALI_PHY_82
+#define LPDDR4__PHY_NTP_WDQ_STOP_0__FLD LPDDR4__DENALI_PHY_82__PHY_NTP_WDQ_STOP_0
+
+#define LPDDR4__DENALI_PHY_83_READ_MASK 0x0103FFFFU
+#define LPDDR4__DENALI_PHY_83_WRITE_MASK 0x0103FFFFU
+#define LPDDR4__DENALI_PHY_83__PHY_NTP_WDQ_BIT_EN_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_83__PHY_NTP_WDQ_BIT_EN_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_83__PHY_NTP_WDQ_BIT_EN_0_WIDTH 8U
+#define LPDDR4__PHY_NTP_WDQ_BIT_EN_0__REG DENALI_PHY_83
+#define LPDDR4__PHY_NTP_WDQ_BIT_EN_0__FLD LPDDR4__DENALI_PHY_83__PHY_NTP_WDQ_BIT_EN_0
+
+#define LPDDR4__DENALI_PHY_83__PHY_WDQLVL_DVW_MIN_0_MASK 0x0003FF00U
+#define LPDDR4__DENALI_PHY_83__PHY_WDQLVL_DVW_MIN_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_83__PHY_WDQLVL_DVW_MIN_0_WIDTH 10U
+#define LPDDR4__PHY_WDQLVL_DVW_MIN_0__REG DENALI_PHY_83
+#define LPDDR4__PHY_WDQLVL_DVW_MIN_0__FLD LPDDR4__DENALI_PHY_83__PHY_WDQLVL_DVW_MIN_0
+
+#define LPDDR4__DENALI_PHY_83__PHY_SW_WDQLVL_DVW_MIN_EN_0_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_83__PHY_SW_WDQLVL_DVW_MIN_EN_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_83__PHY_SW_WDQLVL_DVW_MIN_EN_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_83__PHY_SW_WDQLVL_DVW_MIN_EN_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_83__PHY_SW_WDQLVL_DVW_MIN_EN_0_WOSET 0U
+#define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_0__REG DENALI_PHY_83
+#define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_0__FLD LPDDR4__DENALI_PHY_83__PHY_SW_WDQLVL_DVW_MIN_EN_0
+
+#define LPDDR4__DENALI_PHY_84_READ_MASK 0x1F1F0F3FU
+#define LPDDR4__DENALI_PHY_84_WRITE_MASK 0x1F1F0F3FU
+#define LPDDR4__DENALI_PHY_84__PHY_WDQLVL_PER_START_OFFSET_0_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_84__PHY_WDQLVL_PER_START_OFFSET_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_84__PHY_WDQLVL_PER_START_OFFSET_0_WIDTH 6U
+#define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_0__REG DENALI_PHY_84
+#define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_0__FLD LPDDR4__DENALI_PHY_84__PHY_WDQLVL_PER_START_OFFSET_0
+
+#define LPDDR4__DENALI_PHY_84__PHY_FAST_LVL_EN_0_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_84__PHY_FAST_LVL_EN_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_84__PHY_FAST_LVL_EN_0_WIDTH 4U
+#define LPDDR4__PHY_FAST_LVL_EN_0__REG DENALI_PHY_84
+#define LPDDR4__PHY_FAST_LVL_EN_0__FLD LPDDR4__DENALI_PHY_84__PHY_FAST_LVL_EN_0
+
+#define LPDDR4__DENALI_PHY_84__PHY_PAD_TX_DCD_0_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_84__PHY_PAD_TX_DCD_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_84__PHY_PAD_TX_DCD_0_WIDTH 5U
+#define LPDDR4__PHY_PAD_TX_DCD_0__REG DENALI_PHY_84
+#define LPDDR4__PHY_PAD_TX_DCD_0__FLD LPDDR4__DENALI_PHY_84__PHY_PAD_TX_DCD_0
+
+#define LPDDR4__DENALI_PHY_84__PHY_PAD_RX_DCD_0_0_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_84__PHY_PAD_RX_DCD_0_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_84__PHY_PAD_RX_DCD_0_0_WIDTH 5U
+#define LPDDR4__PHY_PAD_RX_DCD_0_0__REG DENALI_PHY_84
+#define LPDDR4__PHY_PAD_RX_DCD_0_0__FLD LPDDR4__DENALI_PHY_84__PHY_PAD_RX_DCD_0_0
+
+#define LPDDR4__DENALI_PHY_85_READ_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_85_WRITE_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_85__PHY_PAD_RX_DCD_1_0_MASK 0x0000001FU
+#define LPDDR4__DENALI_PHY_85__PHY_PAD_RX_DCD_1_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_85__PHY_PAD_RX_DCD_1_0_WIDTH 5U
+#define LPDDR4__PHY_PAD_RX_DCD_1_0__REG DENALI_PHY_85
+#define LPDDR4__PHY_PAD_RX_DCD_1_0__FLD LPDDR4__DENALI_PHY_85__PHY_PAD_RX_DCD_1_0
+
+#define LPDDR4__DENALI_PHY_85__PHY_PAD_RX_DCD_2_0_MASK 0x00001F00U
+#define LPDDR4__DENALI_PHY_85__PHY_PAD_RX_DCD_2_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_85__PHY_PAD_RX_DCD_2_0_WIDTH 5U
+#define LPDDR4__PHY_PAD_RX_DCD_2_0__REG DENALI_PHY_85
+#define LPDDR4__PHY_PAD_RX_DCD_2_0__FLD LPDDR4__DENALI_PHY_85__PHY_PAD_RX_DCD_2_0
+
+#define LPDDR4__DENALI_PHY_85__PHY_PAD_RX_DCD_3_0_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_85__PHY_PAD_RX_DCD_3_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_85__PHY_PAD_RX_DCD_3_0_WIDTH 5U
+#define LPDDR4__PHY_PAD_RX_DCD_3_0__REG DENALI_PHY_85
+#define LPDDR4__PHY_PAD_RX_DCD_3_0__FLD LPDDR4__DENALI_PHY_85__PHY_PAD_RX_DCD_3_0
+
+#define LPDDR4__DENALI_PHY_85__PHY_PAD_RX_DCD_4_0_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_85__PHY_PAD_RX_DCD_4_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_85__PHY_PAD_RX_DCD_4_0_WIDTH 5U
+#define LPDDR4__PHY_PAD_RX_DCD_4_0__REG DENALI_PHY_85
+#define LPDDR4__PHY_PAD_RX_DCD_4_0__FLD LPDDR4__DENALI_PHY_85__PHY_PAD_RX_DCD_4_0
+
+#define LPDDR4__DENALI_PHY_86_READ_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_86_WRITE_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_86__PHY_PAD_RX_DCD_5_0_MASK 0x0000001FU
+#define LPDDR4__DENALI_PHY_86__PHY_PAD_RX_DCD_5_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_86__PHY_PAD_RX_DCD_5_0_WIDTH 5U
+#define LPDDR4__PHY_PAD_RX_DCD_5_0__REG DENALI_PHY_86
+#define LPDDR4__PHY_PAD_RX_DCD_5_0__FLD LPDDR4__DENALI_PHY_86__PHY_PAD_RX_DCD_5_0
+
+#define LPDDR4__DENALI_PHY_86__PHY_PAD_RX_DCD_6_0_MASK 0x00001F00U
+#define LPDDR4__DENALI_PHY_86__PHY_PAD_RX_DCD_6_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_86__PHY_PAD_RX_DCD_6_0_WIDTH 5U
+#define LPDDR4__PHY_PAD_RX_DCD_6_0__REG DENALI_PHY_86
+#define LPDDR4__PHY_PAD_RX_DCD_6_0__FLD LPDDR4__DENALI_PHY_86__PHY_PAD_RX_DCD_6_0
+
+#define LPDDR4__DENALI_PHY_86__PHY_PAD_RX_DCD_7_0_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_86__PHY_PAD_RX_DCD_7_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_86__PHY_PAD_RX_DCD_7_0_WIDTH 5U
+#define LPDDR4__PHY_PAD_RX_DCD_7_0__REG DENALI_PHY_86
+#define LPDDR4__PHY_PAD_RX_DCD_7_0__FLD LPDDR4__DENALI_PHY_86__PHY_PAD_RX_DCD_7_0
+
+#define LPDDR4__DENALI_PHY_86__PHY_PAD_DM_RX_DCD_0_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_86__PHY_PAD_DM_RX_DCD_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_86__PHY_PAD_DM_RX_DCD_0_WIDTH 5U
+#define LPDDR4__PHY_PAD_DM_RX_DCD_0__REG DENALI_PHY_86
+#define LPDDR4__PHY_PAD_DM_RX_DCD_0__FLD LPDDR4__DENALI_PHY_86__PHY_PAD_DM_RX_DCD_0
+
+#define LPDDR4__DENALI_PHY_87_READ_MASK 0x007F1F1FU
+#define LPDDR4__DENALI_PHY_87_WRITE_MASK 0x007F1F1FU
+#define LPDDR4__DENALI_PHY_87__PHY_PAD_DQS_RX_DCD_0_MASK 0x0000001FU
+#define LPDDR4__DENALI_PHY_87__PHY_PAD_DQS_RX_DCD_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_87__PHY_PAD_DQS_RX_DCD_0_WIDTH 5U
+#define LPDDR4__PHY_PAD_DQS_RX_DCD_0__REG DENALI_PHY_87
+#define LPDDR4__PHY_PAD_DQS_RX_DCD_0__FLD LPDDR4__DENALI_PHY_87__PHY_PAD_DQS_RX_DCD_0
+
+#define LPDDR4__DENALI_PHY_87__PHY_PAD_FDBK_RX_DCD_0_MASK 0x00001F00U
+#define LPDDR4__DENALI_PHY_87__PHY_PAD_FDBK_RX_DCD_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_87__PHY_PAD_FDBK_RX_DCD_0_WIDTH 5U
+#define LPDDR4__PHY_PAD_FDBK_RX_DCD_0__REG DENALI_PHY_87
+#define LPDDR4__PHY_PAD_FDBK_RX_DCD_0__FLD LPDDR4__DENALI_PHY_87__PHY_PAD_FDBK_RX_DCD_0
+
+#define LPDDR4__DENALI_PHY_87__PHY_PAD_DSLICE_IO_CFG_0_MASK 0x007F0000U
+#define LPDDR4__DENALI_PHY_87__PHY_PAD_DSLICE_IO_CFG_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_87__PHY_PAD_DSLICE_IO_CFG_0_WIDTH 7U
+#define LPDDR4__PHY_PAD_DSLICE_IO_CFG_0__REG DENALI_PHY_87
+#define LPDDR4__PHY_PAD_DSLICE_IO_CFG_0__FLD LPDDR4__DENALI_PHY_87__PHY_PAD_DSLICE_IO_CFG_0
+
+#define LPDDR4__DENALI_PHY_88_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_88_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_88__PHY_RDDQ0_SLAVE_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_88__PHY_RDDQ0_SLAVE_DELAY_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_88__PHY_RDDQ0_SLAVE_DELAY_0_WIDTH 10U
+#define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_0__REG DENALI_PHY_88
+#define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_88__PHY_RDDQ0_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_88__PHY_RDDQ1_SLAVE_DELAY_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_88__PHY_RDDQ1_SLAVE_DELAY_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_88__PHY_RDDQ1_SLAVE_DELAY_0_WIDTH 10U
+#define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_0__REG DENALI_PHY_88
+#define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_88__PHY_RDDQ1_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_89_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_89_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_89__PHY_RDDQ2_SLAVE_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_89__PHY_RDDQ2_SLAVE_DELAY_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_89__PHY_RDDQ2_SLAVE_DELAY_0_WIDTH 10U
+#define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_0__REG DENALI_PHY_89
+#define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_89__PHY_RDDQ2_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_89__PHY_RDDQ3_SLAVE_DELAY_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_89__PHY_RDDQ3_SLAVE_DELAY_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_89__PHY_RDDQ3_SLAVE_DELAY_0_WIDTH 10U
+#define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_0__REG DENALI_PHY_89
+#define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_89__PHY_RDDQ3_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_90_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_90_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_90__PHY_RDDQ4_SLAVE_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_90__PHY_RDDQ4_SLAVE_DELAY_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_90__PHY_RDDQ4_SLAVE_DELAY_0_WIDTH 10U
+#define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_0__REG DENALI_PHY_90
+#define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_90__PHY_RDDQ4_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_90__PHY_RDDQ5_SLAVE_DELAY_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_90__PHY_RDDQ5_SLAVE_DELAY_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_90__PHY_RDDQ5_SLAVE_DELAY_0_WIDTH 10U
+#define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_0__REG DENALI_PHY_90
+#define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_90__PHY_RDDQ5_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_91_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_91_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_91__PHY_RDDQ6_SLAVE_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_91__PHY_RDDQ6_SLAVE_DELAY_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_91__PHY_RDDQ6_SLAVE_DELAY_0_WIDTH 10U
+#define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_0__REG DENALI_PHY_91
+#define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_91__PHY_RDDQ6_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_91__PHY_RDDQ7_SLAVE_DELAY_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_91__PHY_RDDQ7_SLAVE_DELAY_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_91__PHY_RDDQ7_SLAVE_DELAY_0_WIDTH 10U
+#define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_0__REG DENALI_PHY_91
+#define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_91__PHY_RDDQ7_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_92_READ_MASK 0x1F0703FFU
+#define LPDDR4__DENALI_PHY_92_WRITE_MASK 0x1F0703FFU
+#define LPDDR4__DENALI_PHY_92__PHY_RDDM_SLAVE_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_92__PHY_RDDM_SLAVE_DELAY_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_92__PHY_RDDM_SLAVE_DELAY_0_WIDTH 10U
+#define LPDDR4__PHY_RDDM_SLAVE_DELAY_0__REG DENALI_PHY_92
+#define LPDDR4__PHY_RDDM_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_92__PHY_RDDM_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_92__PHY_RX_PCLK_CLK_SEL_0_MASK 0x00070000U
+#define LPDDR4__DENALI_PHY_92__PHY_RX_PCLK_CLK_SEL_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_92__PHY_RX_PCLK_CLK_SEL_0_WIDTH 3U
+#define LPDDR4__PHY_RX_PCLK_CLK_SEL_0__REG DENALI_PHY_92
+#define LPDDR4__PHY_RX_PCLK_CLK_SEL_0__FLD LPDDR4__DENALI_PHY_92__PHY_RX_PCLK_CLK_SEL_0
+
+#define LPDDR4__DENALI_PHY_92__PHY_RX_CAL_ALL_DLY_0_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_92__PHY_RX_CAL_ALL_DLY_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_92__PHY_RX_CAL_ALL_DLY_0_WIDTH 5U
+#define LPDDR4__PHY_RX_CAL_ALL_DLY_0__REG DENALI_PHY_92
+#define LPDDR4__PHY_RX_CAL_ALL_DLY_0__FLD LPDDR4__DENALI_PHY_92__PHY_RX_CAL_ALL_DLY_0
+
+#define LPDDR4__DENALI_PHY_93_READ_MASK 0x00000007U
+#define LPDDR4__DENALI_PHY_93_WRITE_MASK 0x00000007U
+#define LPDDR4__DENALI_PHY_93__PHY_DATA_DC_CAL_CLK_SEL_0_MASK 0x00000007U
+#define LPDDR4__DENALI_PHY_93__PHY_DATA_DC_CAL_CLK_SEL_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_93__PHY_DATA_DC_CAL_CLK_SEL_0_WIDTH 3U
+#define LPDDR4__PHY_DATA_DC_CAL_CLK_SEL_0__REG DENALI_PHY_93
+#define LPDDR4__PHY_DATA_DC_CAL_CLK_SEL_0__FLD LPDDR4__DENALI_PHY_93__PHY_DATA_DC_CAL_CLK_SEL_0
+
+#define LPDDR4__DENALI_PHY_94_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_94_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_94__PHY_DQ_OE_TIMING_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_94__PHY_DQ_OE_TIMING_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_94__PHY_DQ_OE_TIMING_0_WIDTH 8U
+#define LPDDR4__PHY_DQ_OE_TIMING_0__REG DENALI_PHY_94
+#define LPDDR4__PHY_DQ_OE_TIMING_0__FLD LPDDR4__DENALI_PHY_94__PHY_DQ_OE_TIMING_0
+
+#define LPDDR4__DENALI_PHY_94__PHY_DQ_TSEL_RD_TIMING_0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_94__PHY_DQ_TSEL_RD_TIMING_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_94__PHY_DQ_TSEL_RD_TIMING_0_WIDTH 8U
+#define LPDDR4__PHY_DQ_TSEL_RD_TIMING_0__REG DENALI_PHY_94
+#define LPDDR4__PHY_DQ_TSEL_RD_TIMING_0__FLD LPDDR4__DENALI_PHY_94__PHY_DQ_TSEL_RD_TIMING_0
+
+#define LPDDR4__DENALI_PHY_94__PHY_DQ_TSEL_WR_TIMING_0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_94__PHY_DQ_TSEL_WR_TIMING_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_94__PHY_DQ_TSEL_WR_TIMING_0_WIDTH 8U
+#define LPDDR4__PHY_DQ_TSEL_WR_TIMING_0__REG DENALI_PHY_94
+#define LPDDR4__PHY_DQ_TSEL_WR_TIMING_0__FLD LPDDR4__DENALI_PHY_94__PHY_DQ_TSEL_WR_TIMING_0
+
+#define LPDDR4__DENALI_PHY_94__PHY_DQS_OE_TIMING_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_94__PHY_DQS_OE_TIMING_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_94__PHY_DQS_OE_TIMING_0_WIDTH 8U
+#define LPDDR4__PHY_DQS_OE_TIMING_0__REG DENALI_PHY_94
+#define LPDDR4__PHY_DQS_OE_TIMING_0__FLD LPDDR4__DENALI_PHY_94__PHY_DQS_OE_TIMING_0
+
+#define LPDDR4__DENALI_PHY_95_READ_MASK 0xFFFFFF0FU
+#define LPDDR4__DENALI_PHY_95_WRITE_MASK 0xFFFFFF0FU
+#define LPDDR4__DENALI_PHY_95__PHY_IO_PAD_DELAY_TIMING_0_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_95__PHY_IO_PAD_DELAY_TIMING_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_95__PHY_IO_PAD_DELAY_TIMING_0_WIDTH 4U
+#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_0__REG DENALI_PHY_95
+#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_0__FLD LPDDR4__DENALI_PHY_95__PHY_IO_PAD_DELAY_TIMING_0
+
+#define LPDDR4__DENALI_PHY_95__PHY_DQS_TSEL_RD_TIMING_0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_95__PHY_DQS_TSEL_RD_TIMING_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_95__PHY_DQS_TSEL_RD_TIMING_0_WIDTH 8U
+#define LPDDR4__PHY_DQS_TSEL_RD_TIMING_0__REG DENALI_PHY_95
+#define LPDDR4__PHY_DQS_TSEL_RD_TIMING_0__FLD LPDDR4__DENALI_PHY_95__PHY_DQS_TSEL_RD_TIMING_0
+
+#define LPDDR4__DENALI_PHY_95__PHY_DQS_OE_RD_TIMING_0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_95__PHY_DQS_OE_RD_TIMING_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_95__PHY_DQS_OE_RD_TIMING_0_WIDTH 8U
+#define LPDDR4__PHY_DQS_OE_RD_TIMING_0__REG DENALI_PHY_95
+#define LPDDR4__PHY_DQS_OE_RD_TIMING_0__FLD LPDDR4__DENALI_PHY_95__PHY_DQS_OE_RD_TIMING_0
+
+#define LPDDR4__DENALI_PHY_95__PHY_DQS_TSEL_WR_TIMING_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_95__PHY_DQS_TSEL_WR_TIMING_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_95__PHY_DQS_TSEL_WR_TIMING_0_WIDTH 8U
+#define LPDDR4__PHY_DQS_TSEL_WR_TIMING_0__REG DENALI_PHY_95
+#define LPDDR4__PHY_DQS_TSEL_WR_TIMING_0__FLD LPDDR4__DENALI_PHY_95__PHY_DQS_TSEL_WR_TIMING_0
+
+#define LPDDR4__DENALI_PHY_96_READ_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_96_WRITE_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_96__PHY_VREF_SETTING_TIME_0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_96__PHY_VREF_SETTING_TIME_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_96__PHY_VREF_SETTING_TIME_0_WIDTH 16U
+#define LPDDR4__PHY_VREF_SETTING_TIME_0__REG DENALI_PHY_96
+#define LPDDR4__PHY_VREF_SETTING_TIME_0__FLD LPDDR4__DENALI_PHY_96__PHY_VREF_SETTING_TIME_0
+
+#define LPDDR4__DENALI_PHY_96__PHY_PAD_VREF_CTRL_DQ_0_MASK 0x0FFF0000U
+#define LPDDR4__DENALI_PHY_96__PHY_PAD_VREF_CTRL_DQ_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_96__PHY_PAD_VREF_CTRL_DQ_0_WIDTH 12U
+#define LPDDR4__PHY_PAD_VREF_CTRL_DQ_0__REG DENALI_PHY_96
+#define LPDDR4__PHY_PAD_VREF_CTRL_DQ_0__FLD LPDDR4__DENALI_PHY_96__PHY_PAD_VREF_CTRL_DQ_0
+
+#define LPDDR4__DENALI_PHY_97_READ_MASK 0x03FFFF01U
+#define LPDDR4__DENALI_PHY_97_WRITE_MASK 0x03FFFF01U
+#define LPDDR4__DENALI_PHY_97__PHY_PER_CS_TRAINING_EN_0_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_97__PHY_PER_CS_TRAINING_EN_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_97__PHY_PER_CS_TRAINING_EN_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_97__PHY_PER_CS_TRAINING_EN_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_97__PHY_PER_CS_TRAINING_EN_0_WOSET 0U
+#define LPDDR4__PHY_PER_CS_TRAINING_EN_0__REG DENALI_PHY_97
+#define LPDDR4__PHY_PER_CS_TRAINING_EN_0__FLD LPDDR4__DENALI_PHY_97__PHY_PER_CS_TRAINING_EN_0
+
+#define LPDDR4__DENALI_PHY_97__PHY_DQ_IE_TIMING_0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_97__PHY_DQ_IE_TIMING_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_97__PHY_DQ_IE_TIMING_0_WIDTH 8U
+#define LPDDR4__PHY_DQ_IE_TIMING_0__REG DENALI_PHY_97
+#define LPDDR4__PHY_DQ_IE_TIMING_0__FLD LPDDR4__DENALI_PHY_97__PHY_DQ_IE_TIMING_0
+
+#define LPDDR4__DENALI_PHY_97__PHY_DQS_IE_TIMING_0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_97__PHY_DQS_IE_TIMING_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_97__PHY_DQS_IE_TIMING_0_WIDTH 8U
+#define LPDDR4__PHY_DQS_IE_TIMING_0__REG DENALI_PHY_97
+#define LPDDR4__PHY_DQS_IE_TIMING_0__FLD LPDDR4__DENALI_PHY_97__PHY_DQS_IE_TIMING_0
+
+#define LPDDR4__DENALI_PHY_97__PHY_RDDATA_EN_IE_DLY_0_MASK 0x03000000U
+#define LPDDR4__DENALI_PHY_97__PHY_RDDATA_EN_IE_DLY_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_97__PHY_RDDATA_EN_IE_DLY_0_WIDTH 2U
+#define LPDDR4__PHY_RDDATA_EN_IE_DLY_0__REG DENALI_PHY_97
+#define LPDDR4__PHY_RDDATA_EN_IE_DLY_0__FLD LPDDR4__DENALI_PHY_97__PHY_RDDATA_EN_IE_DLY_0
+
+#define LPDDR4__DENALI_PHY_98_READ_MASK 0x1F010303U
+#define LPDDR4__DENALI_PHY_98_WRITE_MASK 0x1F010303U
+#define LPDDR4__DENALI_PHY_98__PHY_IE_MODE_0_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_98__PHY_IE_MODE_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_98__PHY_IE_MODE_0_WIDTH 2U
+#define LPDDR4__PHY_IE_MODE_0__REG DENALI_PHY_98
+#define LPDDR4__PHY_IE_MODE_0__FLD LPDDR4__DENALI_PHY_98__PHY_IE_MODE_0
+
+#define LPDDR4__DENALI_PHY_98__PHY_DBI_MODE_0_MASK 0x00000300U
+#define LPDDR4__DENALI_PHY_98__PHY_DBI_MODE_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_98__PHY_DBI_MODE_0_WIDTH 2U
+#define LPDDR4__PHY_DBI_MODE_0__REG DENALI_PHY_98
+#define LPDDR4__PHY_DBI_MODE_0__FLD LPDDR4__DENALI_PHY_98__PHY_DBI_MODE_0
+
+#define LPDDR4__DENALI_PHY_98__PHY_WDQLVL_IE_ON_0_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_98__PHY_WDQLVL_IE_ON_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_98__PHY_WDQLVL_IE_ON_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_98__PHY_WDQLVL_IE_ON_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_98__PHY_WDQLVL_IE_ON_0_WOSET 0U
+#define LPDDR4__PHY_WDQLVL_IE_ON_0__REG DENALI_PHY_98
+#define LPDDR4__PHY_WDQLVL_IE_ON_0__FLD LPDDR4__DENALI_PHY_98__PHY_WDQLVL_IE_ON_0
+
+#define LPDDR4__DENALI_PHY_98__PHY_WDQLVL_RDDATA_EN_DLY_0_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_98__PHY_WDQLVL_RDDATA_EN_DLY_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_98__PHY_WDQLVL_RDDATA_EN_DLY_0_WIDTH 5U
+#define LPDDR4__PHY_WDQLVL_RDDATA_EN_DLY_0__REG DENALI_PHY_98
+#define LPDDR4__PHY_WDQLVL_RDDATA_EN_DLY_0__FLD LPDDR4__DENALI_PHY_98__PHY_WDQLVL_RDDATA_EN_DLY_0
+
+#define LPDDR4__DENALI_PHY_99_READ_MASK 0x0F1F1F1FU
+#define LPDDR4__DENALI_PHY_99_WRITE_MASK 0x0F1F1F1FU
+#define LPDDR4__DENALI_PHY_99__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_0_MASK 0x0000001FU
+#define LPDDR4__DENALI_PHY_99__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_99__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_0_WIDTH 5U
+#define LPDDR4__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_0__REG DENALI_PHY_99
+#define LPDDR4__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_0__FLD LPDDR4__DENALI_PHY_99__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_0
+
+#define LPDDR4__DENALI_PHY_99__PHY_RDDATA_EN_TSEL_DLY_0_MASK 0x00001F00U
+#define LPDDR4__DENALI_PHY_99__PHY_RDDATA_EN_TSEL_DLY_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_99__PHY_RDDATA_EN_TSEL_DLY_0_WIDTH 5U
+#define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_0__REG DENALI_PHY_99
+#define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_0__FLD LPDDR4__DENALI_PHY_99__PHY_RDDATA_EN_TSEL_DLY_0
+
+#define LPDDR4__DENALI_PHY_99__PHY_RDDATA_EN_OE_DLY_0_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_99__PHY_RDDATA_EN_OE_DLY_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_99__PHY_RDDATA_EN_OE_DLY_0_WIDTH 5U
+#define LPDDR4__PHY_RDDATA_EN_OE_DLY_0__REG DENALI_PHY_99
+#define LPDDR4__PHY_RDDATA_EN_OE_DLY_0__FLD LPDDR4__DENALI_PHY_99__PHY_RDDATA_EN_OE_DLY_0
+
+#define LPDDR4__DENALI_PHY_99__PHY_SW_MASTER_MODE_0_MASK 0x0F000000U
+#define LPDDR4__DENALI_PHY_99__PHY_SW_MASTER_MODE_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_99__PHY_SW_MASTER_MODE_0_WIDTH 4U
+#define LPDDR4__PHY_SW_MASTER_MODE_0__REG DENALI_PHY_99
+#define LPDDR4__PHY_SW_MASTER_MODE_0__FLD LPDDR4__DENALI_PHY_99__PHY_SW_MASTER_MODE_0
+
+#define LPDDR4__DENALI_PHY_100_READ_MASK 0xFF3F07FFU
+#define LPDDR4__DENALI_PHY_100_WRITE_MASK 0xFF3F07FFU
+#define LPDDR4__DENALI_PHY_100__PHY_MASTER_DELAY_START_0_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_100__PHY_MASTER_DELAY_START_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_100__PHY_MASTER_DELAY_START_0_WIDTH 11U
+#define LPDDR4__PHY_MASTER_DELAY_START_0__REG DENALI_PHY_100
+#define LPDDR4__PHY_MASTER_DELAY_START_0__FLD LPDDR4__DENALI_PHY_100__PHY_MASTER_DELAY_START_0
+
+#define LPDDR4__DENALI_PHY_100__PHY_MASTER_DELAY_STEP_0_MASK 0x003F0000U
+#define LPDDR4__DENALI_PHY_100__PHY_MASTER_DELAY_STEP_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_100__PHY_MASTER_DELAY_STEP_0_WIDTH 6U
+#define LPDDR4__PHY_MASTER_DELAY_STEP_0__REG DENALI_PHY_100
+#define LPDDR4__PHY_MASTER_DELAY_STEP_0__FLD LPDDR4__DENALI_PHY_100__PHY_MASTER_DELAY_STEP_0
+
+#define LPDDR4__DENALI_PHY_100__PHY_MASTER_DELAY_WAIT_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_100__PHY_MASTER_DELAY_WAIT_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_100__PHY_MASTER_DELAY_WAIT_0_WIDTH 8U
+#define LPDDR4__PHY_MASTER_DELAY_WAIT_0__REG DENALI_PHY_100
+#define LPDDR4__PHY_MASTER_DELAY_WAIT_0__FLD LPDDR4__DENALI_PHY_100__PHY_MASTER_DELAY_WAIT_0
+
+#define LPDDR4__DENALI_PHY_101_READ_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_PHY_101_WRITE_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_PHY_101__PHY_MASTER_DELAY_HALF_MEASURE_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_101__PHY_MASTER_DELAY_HALF_MEASURE_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_101__PHY_MASTER_DELAY_HALF_MEASURE_0_WIDTH 8U
+#define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_0__REG DENALI_PHY_101
+#define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_0__FLD LPDDR4__DENALI_PHY_101__PHY_MASTER_DELAY_HALF_MEASURE_0
+
+#define LPDDR4__DENALI_PHY_101__PHY_RPTR_UPDATE_0_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_101__PHY_RPTR_UPDATE_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_101__PHY_RPTR_UPDATE_0_WIDTH 4U
+#define LPDDR4__PHY_RPTR_UPDATE_0__REG DENALI_PHY_101
+#define LPDDR4__PHY_RPTR_UPDATE_0__FLD LPDDR4__DENALI_PHY_101__PHY_RPTR_UPDATE_0
+
+#define LPDDR4__DENALI_PHY_101__PHY_WRLVL_DLY_STEP_0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_101__PHY_WRLVL_DLY_STEP_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_101__PHY_WRLVL_DLY_STEP_0_WIDTH 8U
+#define LPDDR4__PHY_WRLVL_DLY_STEP_0__REG DENALI_PHY_101
+#define LPDDR4__PHY_WRLVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_101__PHY_WRLVL_DLY_STEP_0
+
+#define LPDDR4__DENALI_PHY_101__PHY_WRLVL_DLY_FINE_STEP_0_MASK 0x0F000000U
+#define LPDDR4__DENALI_PHY_101__PHY_WRLVL_DLY_FINE_STEP_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_101__PHY_WRLVL_DLY_FINE_STEP_0_WIDTH 4U
+#define LPDDR4__PHY_WRLVL_DLY_FINE_STEP_0__REG DENALI_PHY_101
+#define LPDDR4__PHY_WRLVL_DLY_FINE_STEP_0__FLD LPDDR4__DENALI_PHY_101__PHY_WRLVL_DLY_FINE_STEP_0
+
+#define LPDDR4__DENALI_PHY_102_READ_MASK 0x001F0F3FU
+#define LPDDR4__DENALI_PHY_102_WRITE_MASK 0x001F0F3FU
+#define LPDDR4__DENALI_PHY_102__PHY_WRLVL_RESP_WAIT_CNT_0_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_102__PHY_WRLVL_RESP_WAIT_CNT_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_102__PHY_WRLVL_RESP_WAIT_CNT_0_WIDTH 6U
+#define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_0__REG DENALI_PHY_102
+#define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_102__PHY_WRLVL_RESP_WAIT_CNT_0
+
+#define LPDDR4__DENALI_PHY_102__PHY_GTLVL_DLY_STEP_0_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_102__PHY_GTLVL_DLY_STEP_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_102__PHY_GTLVL_DLY_STEP_0_WIDTH 4U
+#define LPDDR4__PHY_GTLVL_DLY_STEP_0__REG DENALI_PHY_102
+#define LPDDR4__PHY_GTLVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_102__PHY_GTLVL_DLY_STEP_0
+
+#define LPDDR4__DENALI_PHY_102__PHY_GTLVL_RESP_WAIT_CNT_0_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_102__PHY_GTLVL_RESP_WAIT_CNT_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_102__PHY_GTLVL_RESP_WAIT_CNT_0_WIDTH 5U
+#define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_0__REG DENALI_PHY_102
+#define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_102__PHY_GTLVL_RESP_WAIT_CNT_0
+
+#define LPDDR4__DENALI_PHY_103_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_103_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_103__PHY_GTLVL_BACK_STEP_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_103__PHY_GTLVL_BACK_STEP_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_103__PHY_GTLVL_BACK_STEP_0_WIDTH 10U
+#define LPDDR4__PHY_GTLVL_BACK_STEP_0__REG DENALI_PHY_103
+#define LPDDR4__PHY_GTLVL_BACK_STEP_0__FLD LPDDR4__DENALI_PHY_103__PHY_GTLVL_BACK_STEP_0
+
+#define LPDDR4__DENALI_PHY_103__PHY_GTLVL_FINAL_STEP_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_103__PHY_GTLVL_FINAL_STEP_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_103__PHY_GTLVL_FINAL_STEP_0_WIDTH 10U
+#define LPDDR4__PHY_GTLVL_FINAL_STEP_0__REG DENALI_PHY_103
+#define LPDDR4__PHY_GTLVL_FINAL_STEP_0__FLD LPDDR4__DENALI_PHY_103__PHY_GTLVL_FINAL_STEP_0
+
+#define LPDDR4__DENALI_PHY_104_READ_MASK 0x01FF0FFFU
+#define LPDDR4__DENALI_PHY_104_WRITE_MASK 0x01FF0FFFU
+#define LPDDR4__DENALI_PHY_104__PHY_WDQLVL_DLY_STEP_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_104__PHY_WDQLVL_DLY_STEP_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_104__PHY_WDQLVL_DLY_STEP_0_WIDTH 8U
+#define LPDDR4__PHY_WDQLVL_DLY_STEP_0__REG DENALI_PHY_104
+#define LPDDR4__PHY_WDQLVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_104__PHY_WDQLVL_DLY_STEP_0
+
+#define LPDDR4__DENALI_PHY_104__PHY_WDQLVL_QTR_DLY_STEP_0_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_104__PHY_WDQLVL_QTR_DLY_STEP_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_104__PHY_WDQLVL_QTR_DLY_STEP_0_WIDTH 4U
+#define LPDDR4__PHY_WDQLVL_QTR_DLY_STEP_0__REG DENALI_PHY_104
+#define LPDDR4__PHY_WDQLVL_QTR_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_104__PHY_WDQLVL_QTR_DLY_STEP_0
+
+#define LPDDR4__DENALI_PHY_104__PHY_WDQLVL_DM_SEARCH_RANGE_0_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_104__PHY_WDQLVL_DM_SEARCH_RANGE_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_104__PHY_WDQLVL_DM_SEARCH_RANGE_0_WIDTH 9U
+#define LPDDR4__PHY_WDQLVL_DM_SEARCH_RANGE_0__REG DENALI_PHY_104
+#define LPDDR4__PHY_WDQLVL_DM_SEARCH_RANGE_0__FLD LPDDR4__DENALI_PHY_104__PHY_WDQLVL_DM_SEARCH_RANGE_0
+
+#define LPDDR4__DENALI_PHY_105_READ_MASK 0x00000F01U
+#define LPDDR4__DENALI_PHY_105_WRITE_MASK 0x00000F01U
+#define LPDDR4__DENALI_PHY_105__PHY_TOGGLE_PRE_SUPPORT_0_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_105__PHY_TOGGLE_PRE_SUPPORT_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_105__PHY_TOGGLE_PRE_SUPPORT_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_105__PHY_TOGGLE_PRE_SUPPORT_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_105__PHY_TOGGLE_PRE_SUPPORT_0_WOSET 0U
+#define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_0__REG DENALI_PHY_105
+#define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_0__FLD LPDDR4__DENALI_PHY_105__PHY_TOGGLE_PRE_SUPPORT_0
+
+#define LPDDR4__DENALI_PHY_105__PHY_RDLVL_DLY_STEP_0_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_105__PHY_RDLVL_DLY_STEP_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_105__PHY_RDLVL_DLY_STEP_0_WIDTH 4U
+#define LPDDR4__PHY_RDLVL_DLY_STEP_0__REG DENALI_PHY_105
+#define LPDDR4__PHY_RDLVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_105__PHY_RDLVL_DLY_STEP_0
+
+#define LPDDR4__DENALI_PHY_106_READ_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_106_WRITE_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_106__PHY_RDLVL_MAX_EDGE_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_106__PHY_RDLVL_MAX_EDGE_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_106__PHY_RDLVL_MAX_EDGE_0_WIDTH 10U
+#define LPDDR4__PHY_RDLVL_MAX_EDGE_0__REG DENALI_PHY_106
+#define LPDDR4__PHY_RDLVL_MAX_EDGE_0__FLD LPDDR4__DENALI_PHY_106__PHY_RDLVL_MAX_EDGE_0
+
+#define LPDDR4__DENALI_PHY_107_READ_MASK 0x00030703U
+#define LPDDR4__DENALI_PHY_107_WRITE_MASK 0x00030703U
+#define LPDDR4__DENALI_PHY_107__PHY_WRPATH_GATE_DISABLE_0_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_107__PHY_WRPATH_GATE_DISABLE_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_107__PHY_WRPATH_GATE_DISABLE_0_WIDTH 2U
+#define LPDDR4__PHY_WRPATH_GATE_DISABLE_0__REG DENALI_PHY_107
+#define LPDDR4__PHY_WRPATH_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_107__PHY_WRPATH_GATE_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_107__PHY_WRPATH_GATE_TIMING_0_MASK 0x00000700U
+#define LPDDR4__DENALI_PHY_107__PHY_WRPATH_GATE_TIMING_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_107__PHY_WRPATH_GATE_TIMING_0_WIDTH 3U
+#define LPDDR4__PHY_WRPATH_GATE_TIMING_0__REG DENALI_PHY_107
+#define LPDDR4__PHY_WRPATH_GATE_TIMING_0__FLD LPDDR4__DENALI_PHY_107__PHY_WRPATH_GATE_TIMING_0
+
+#define LPDDR4__DENALI_PHY_107__PHY_DATA_DC_INIT_DISABLE_0_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_107__PHY_DATA_DC_INIT_DISABLE_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_107__PHY_DATA_DC_INIT_DISABLE_0_WIDTH 2U
+#define LPDDR4__PHY_DATA_DC_INIT_DISABLE_0__REG DENALI_PHY_107
+#define LPDDR4__PHY_DATA_DC_INIT_DISABLE_0__FLD LPDDR4__DENALI_PHY_107__PHY_DATA_DC_INIT_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_108_READ_MASK 0x07FF03FFU
+#define LPDDR4__DENALI_PHY_108_WRITE_MASK 0x07FF03FFU
+#define LPDDR4__DENALI_PHY_108__PHY_DATA_DC_DQS_INIT_SLV_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_108__PHY_DATA_DC_DQS_INIT_SLV_DELAY_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_108__PHY_DATA_DC_DQS_INIT_SLV_DELAY_0_WIDTH 10U
+#define LPDDR4__PHY_DATA_DC_DQS_INIT_SLV_DELAY_0__REG DENALI_PHY_108
+#define LPDDR4__PHY_DATA_DC_DQS_INIT_SLV_DELAY_0__FLD LPDDR4__DENALI_PHY_108__PHY_DATA_DC_DQS_INIT_SLV_DELAY_0
+
+#define LPDDR4__DENALI_PHY_108__PHY_DATA_DC_DQ_INIT_SLV_DELAY_0_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_108__PHY_DATA_DC_DQ_INIT_SLV_DELAY_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_108__PHY_DATA_DC_DQ_INIT_SLV_DELAY_0_WIDTH 11U
+#define LPDDR4__PHY_DATA_DC_DQ_INIT_SLV_DELAY_0__REG DENALI_PHY_108
+#define LPDDR4__PHY_DATA_DC_DQ_INIT_SLV_DELAY_0__FLD LPDDR4__DENALI_PHY_108__PHY_DATA_DC_DQ_INIT_SLV_DELAY_0
+
+#define LPDDR4__DENALI_PHY_109_READ_MASK 0xFFFF0101U
+#define LPDDR4__DENALI_PHY_109_WRITE_MASK 0xFFFF0101U
+#define LPDDR4__DENALI_PHY_109__PHY_DATA_DC_WRLVL_ENABLE_0_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_109__PHY_DATA_DC_WRLVL_ENABLE_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_109__PHY_DATA_DC_WRLVL_ENABLE_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_109__PHY_DATA_DC_WRLVL_ENABLE_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_109__PHY_DATA_DC_WRLVL_ENABLE_0_WOSET 0U
+#define LPDDR4__PHY_DATA_DC_WRLVL_ENABLE_0__REG DENALI_PHY_109
+#define LPDDR4__PHY_DATA_DC_WRLVL_ENABLE_0__FLD LPDDR4__DENALI_PHY_109__PHY_DATA_DC_WRLVL_ENABLE_0
+
+#define LPDDR4__DENALI_PHY_109__PHY_DATA_DC_WDQLVL_ENABLE_0_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_109__PHY_DATA_DC_WDQLVL_ENABLE_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_109__PHY_DATA_DC_WDQLVL_ENABLE_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_109__PHY_DATA_DC_WDQLVL_ENABLE_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_109__PHY_DATA_DC_WDQLVL_ENABLE_0_WOSET 0U
+#define LPDDR4__PHY_DATA_DC_WDQLVL_ENABLE_0__REG DENALI_PHY_109
+#define LPDDR4__PHY_DATA_DC_WDQLVL_ENABLE_0__FLD LPDDR4__DENALI_PHY_109__PHY_DATA_DC_WDQLVL_ENABLE_0
+
+#define LPDDR4__DENALI_PHY_109__PHY_DATA_DC_DM_CLK_SE_THRSHLD_0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_109__PHY_DATA_DC_DM_CLK_SE_THRSHLD_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_109__PHY_DATA_DC_DM_CLK_SE_THRSHLD_0_WIDTH 8U
+#define LPDDR4__PHY_DATA_DC_DM_CLK_SE_THRSHLD_0__REG DENALI_PHY_109
+#define LPDDR4__PHY_DATA_DC_DM_CLK_SE_THRSHLD_0__FLD LPDDR4__DENALI_PHY_109__PHY_DATA_DC_DM_CLK_SE_THRSHLD_0
+
+#define LPDDR4__DENALI_PHY_109__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_109__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_109__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_0_WIDTH 8U
+#define LPDDR4__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_0__REG DENALI_PHY_109
+#define LPDDR4__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_0__FLD LPDDR4__DENALI_PHY_109__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_0
+
+#define LPDDR4__DENALI_PHY_110_READ_MASK 0x001F7F7FU
+#define LPDDR4__DENALI_PHY_110_WRITE_MASK 0x001F7F7FU
+#define LPDDR4__DENALI_PHY_110__PHY_WDQ_OSC_DELTA_0_MASK 0x0000007FU
+#define LPDDR4__DENALI_PHY_110__PHY_WDQ_OSC_DELTA_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_110__PHY_WDQ_OSC_DELTA_0_WIDTH 7U
+#define LPDDR4__PHY_WDQ_OSC_DELTA_0__REG DENALI_PHY_110
+#define LPDDR4__PHY_WDQ_OSC_DELTA_0__FLD LPDDR4__DENALI_PHY_110__PHY_WDQ_OSC_DELTA_0
+
+#define LPDDR4__DENALI_PHY_110__PHY_MEAS_DLY_STEP_ENABLE_0_MASK 0x00007F00U
+#define LPDDR4__DENALI_PHY_110__PHY_MEAS_DLY_STEP_ENABLE_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_110__PHY_MEAS_DLY_STEP_ENABLE_0_WIDTH 7U
+#define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_0__REG DENALI_PHY_110
+#define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_0__FLD LPDDR4__DENALI_PHY_110__PHY_MEAS_DLY_STEP_ENABLE_0
+
+#define LPDDR4__DENALI_PHY_110__PHY_RDDATA_EN_DLY_0_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_110__PHY_RDDATA_EN_DLY_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_110__PHY_RDDATA_EN_DLY_0_WIDTH 5U
+#define LPDDR4__PHY_RDDATA_EN_DLY_0__REG DENALI_PHY_110
+#define LPDDR4__PHY_RDDATA_EN_DLY_0__FLD LPDDR4__DENALI_PHY_110__PHY_RDDATA_EN_DLY_0
+
+#define LPDDR4__DENALI_PHY_111_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_111_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_111__PHY_DQ_DM_SWIZZLE0_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_111__PHY_DQ_DM_SWIZZLE0_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_111__PHY_DQ_DM_SWIZZLE0_0_WIDTH 32U
+#define LPDDR4__PHY_DQ_DM_SWIZZLE0_0__REG DENALI_PHY_111
+#define LPDDR4__PHY_DQ_DM_SWIZZLE0_0__FLD LPDDR4__DENALI_PHY_111__PHY_DQ_DM_SWIZZLE0_0
+
+#define LPDDR4__DENALI_PHY_112_READ_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_112_WRITE_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_112__PHY_DQ_DM_SWIZZLE1_0_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_112__PHY_DQ_DM_SWIZZLE1_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_112__PHY_DQ_DM_SWIZZLE1_0_WIDTH 4U
+#define LPDDR4__PHY_DQ_DM_SWIZZLE1_0__REG DENALI_PHY_112
+#define LPDDR4__PHY_DQ_DM_SWIZZLE1_0__FLD LPDDR4__DENALI_PHY_112__PHY_DQ_DM_SWIZZLE1_0
+
+#define LPDDR4__DENALI_PHY_113_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_113_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_113__PHY_CLK_WRDQ0_SLAVE_DELAY_0_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_113__PHY_CLK_WRDQ0_SLAVE_DELAY_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_113__PHY_CLK_WRDQ0_SLAVE_DELAY_0_WIDTH 11U
+#define LPDDR4__PHY_CLK_WRDQ0_SLAVE_DELAY_0__REG DENALI_PHY_113
+#define LPDDR4__PHY_CLK_WRDQ0_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_113__PHY_CLK_WRDQ0_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_113__PHY_CLK_WRDQ1_SLAVE_DELAY_0_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_113__PHY_CLK_WRDQ1_SLAVE_DELAY_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_113__PHY_CLK_WRDQ1_SLAVE_DELAY_0_WIDTH 11U
+#define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_0__REG DENALI_PHY_113
+#define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_113__PHY_CLK_WRDQ1_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_114_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_114_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_114__PHY_CLK_WRDQ2_SLAVE_DELAY_0_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_114__PHY_CLK_WRDQ2_SLAVE_DELAY_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_114__PHY_CLK_WRDQ2_SLAVE_DELAY_0_WIDTH 11U
+#define LPDDR4__PHY_CLK_WRDQ2_SLAVE_DELAY_0__REG DENALI_PHY_114
+#define LPDDR4__PHY_CLK_WRDQ2_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_114__PHY_CLK_WRDQ2_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_114__PHY_CLK_WRDQ3_SLAVE_DELAY_0_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_114__PHY_CLK_WRDQ3_SLAVE_DELAY_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_114__PHY_CLK_WRDQ3_SLAVE_DELAY_0_WIDTH 11U
+#define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_0__REG DENALI_PHY_114
+#define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_114__PHY_CLK_WRDQ3_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_115_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_115_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_115__PHY_CLK_WRDQ4_SLAVE_DELAY_0_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_115__PHY_CLK_WRDQ4_SLAVE_DELAY_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_115__PHY_CLK_WRDQ4_SLAVE_DELAY_0_WIDTH 11U
+#define LPDDR4__PHY_CLK_WRDQ4_SLAVE_DELAY_0__REG DENALI_PHY_115
+#define LPDDR4__PHY_CLK_WRDQ4_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_115__PHY_CLK_WRDQ4_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_115__PHY_CLK_WRDQ5_SLAVE_DELAY_0_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_115__PHY_CLK_WRDQ5_SLAVE_DELAY_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_115__PHY_CLK_WRDQ5_SLAVE_DELAY_0_WIDTH 11U
+#define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_0__REG DENALI_PHY_115
+#define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_115__PHY_CLK_WRDQ5_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_116_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_116_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_116__PHY_CLK_WRDQ6_SLAVE_DELAY_0_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_116__PHY_CLK_WRDQ6_SLAVE_DELAY_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_116__PHY_CLK_WRDQ6_SLAVE_DELAY_0_WIDTH 11U
+#define LPDDR4__PHY_CLK_WRDQ6_SLAVE_DELAY_0__REG DENALI_PHY_116
+#define LPDDR4__PHY_CLK_WRDQ6_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_116__PHY_CLK_WRDQ6_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_116__PHY_CLK_WRDQ7_SLAVE_DELAY_0_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_116__PHY_CLK_WRDQ7_SLAVE_DELAY_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_116__PHY_CLK_WRDQ7_SLAVE_DELAY_0_WIDTH 11U
+#define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_0__REG DENALI_PHY_116
+#define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_116__PHY_CLK_WRDQ7_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_117_READ_MASK 0x03FF07FFU
+#define LPDDR4__DENALI_PHY_117_WRITE_MASK 0x03FF07FFU
+#define LPDDR4__DENALI_PHY_117__PHY_CLK_WRDM_SLAVE_DELAY_0_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_117__PHY_CLK_WRDM_SLAVE_DELAY_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_117__PHY_CLK_WRDM_SLAVE_DELAY_0_WIDTH 11U
+#define LPDDR4__PHY_CLK_WRDM_SLAVE_DELAY_0__REG DENALI_PHY_117
+#define LPDDR4__PHY_CLK_WRDM_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_117__PHY_CLK_WRDM_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_117__PHY_CLK_WRDQS_SLAVE_DELAY_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_117__PHY_CLK_WRDQS_SLAVE_DELAY_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_117__PHY_CLK_WRDQS_SLAVE_DELAY_0_WIDTH 10U
+#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_0__REG DENALI_PHY_117
+#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_117__PHY_CLK_WRDQS_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_118_READ_MASK 0x0003FF03U
+#define LPDDR4__DENALI_PHY_118_WRITE_MASK 0x0003FF03U
+#define LPDDR4__DENALI_PHY_118__PHY_WRLVL_THRESHOLD_ADJUST_0_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_118__PHY_WRLVL_THRESHOLD_ADJUST_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_118__PHY_WRLVL_THRESHOLD_ADJUST_0_WIDTH 2U
+#define LPDDR4__PHY_WRLVL_THRESHOLD_ADJUST_0__REG DENALI_PHY_118
+#define LPDDR4__PHY_WRLVL_THRESHOLD_ADJUST_0__FLD LPDDR4__DENALI_PHY_118__PHY_WRLVL_THRESHOLD_ADJUST_0
+
+#define LPDDR4__DENALI_PHY_118__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0_MASK 0x0003FF00U
+#define LPDDR4__DENALI_PHY_118__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_118__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0__REG DENALI_PHY_118
+#define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_118__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_119_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_119_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_119__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_119__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_119__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0__REG DENALI_PHY_119
+#define LPDDR4__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_119__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_119__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_119__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_119__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0__REG DENALI_PHY_119
+#define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_119__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_120_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_120_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_120__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_120__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_120__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0__REG DENALI_PHY_120
+#define LPDDR4__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_120__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_120__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_120__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_120__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0__REG DENALI_PHY_120
+#define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_120__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_121_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_121_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_121__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_121__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_121__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0__REG DENALI_PHY_121
+#define LPDDR4__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_121__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_121__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_121__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_121__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0__REG DENALI_PHY_121
+#define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_121__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_122_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_122_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_122__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_122__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_122__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0__REG DENALI_PHY_122
+#define LPDDR4__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_122__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_122__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_122__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_122__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0__REG DENALI_PHY_122
+#define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_122__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_123_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_123_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_123__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_123__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_123__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0__REG DENALI_PHY_123
+#define LPDDR4__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_123__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_123__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_123__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_123__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0__REG DENALI_PHY_123
+#define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_123__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_124_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_124_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_124__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_124__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_124__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0__REG DENALI_PHY_124
+#define LPDDR4__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_124__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_124__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_124__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_124__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0__REG DENALI_PHY_124
+#define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_124__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_125_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_125_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_125__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_125__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_125__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0__REG DENALI_PHY_125
+#define LPDDR4__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_125__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_125__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_125__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_125__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0__REG DENALI_PHY_125
+#define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_125__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_126_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_126_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_126__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_126__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_126__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0__REG DENALI_PHY_126
+#define LPDDR4__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_126__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_126__PHY_RDDQS_DM_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_126__PHY_RDDQS_DM_RISE_SLAVE_DELAY_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_126__PHY_RDDQS_DM_RISE_SLAVE_DELAY_0_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_0__REG DENALI_PHY_126
+#define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_126__PHY_RDDQS_DM_RISE_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_127_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_127_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_127__PHY_RDDQS_DM_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_127__PHY_RDDQS_DM_FALL_SLAVE_DELAY_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_127__PHY_RDDQS_DM_FALL_SLAVE_DELAY_0_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DM_FALL_SLAVE_DELAY_0__REG DENALI_PHY_127
+#define LPDDR4__PHY_RDDQS_DM_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_127__PHY_RDDQS_DM_FALL_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_127__PHY_RDDQS_GATE_SLAVE_DELAY_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_127__PHY_RDDQS_GATE_SLAVE_DELAY_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_127__PHY_RDDQS_GATE_SLAVE_DELAY_0_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_0__REG DENALI_PHY_127
+#define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_127__PHY_RDDQS_GATE_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_128_READ_MASK 0x03FF070FU
+#define LPDDR4__DENALI_PHY_128_WRITE_MASK 0x03FF070FU
+#define LPDDR4__DENALI_PHY_128__PHY_RDDQS_LATENCY_ADJUST_0_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_128__PHY_RDDQS_LATENCY_ADJUST_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_128__PHY_RDDQS_LATENCY_ADJUST_0_WIDTH 4U
+#define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_0__REG DENALI_PHY_128
+#define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_0__FLD LPDDR4__DENALI_PHY_128__PHY_RDDQS_LATENCY_ADJUST_0
+
+#define LPDDR4__DENALI_PHY_128__PHY_WRITE_PATH_LAT_ADD_0_MASK 0x00000700U
+#define LPDDR4__DENALI_PHY_128__PHY_WRITE_PATH_LAT_ADD_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_128__PHY_WRITE_PATH_LAT_ADD_0_WIDTH 3U
+#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_0__REG DENALI_PHY_128
+#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_0__FLD LPDDR4__DENALI_PHY_128__PHY_WRITE_PATH_LAT_ADD_0
+
+#define LPDDR4__DENALI_PHY_128__PHY_WRLVL_DELAY_EARLY_THRESHOLD_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_128__PHY_WRLVL_DELAY_EARLY_THRESHOLD_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_128__PHY_WRLVL_DELAY_EARLY_THRESHOLD_0_WIDTH 10U
+#define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_0__REG DENALI_PHY_128
+#define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_0__FLD LPDDR4__DENALI_PHY_128__PHY_WRLVL_DELAY_EARLY_THRESHOLD_0
+
+#define LPDDR4__DENALI_PHY_129_READ_MASK 0x000103FFU
+#define LPDDR4__DENALI_PHY_129_WRITE_MASK 0x000103FFU
+#define LPDDR4__DENALI_PHY_129__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_129__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_129__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0_WIDTH 10U
+#define LPDDR4__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0__REG DENALI_PHY_129
+#define LPDDR4__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0__FLD LPDDR4__DENALI_PHY_129__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0
+
+#define LPDDR4__DENALI_PHY_129__PHY_WRLVL_EARLY_FORCE_ZERO_0_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_129__PHY_WRLVL_EARLY_FORCE_ZERO_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_129__PHY_WRLVL_EARLY_FORCE_ZERO_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_129__PHY_WRLVL_EARLY_FORCE_ZERO_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_129__PHY_WRLVL_EARLY_FORCE_ZERO_0_WOSET 0U
+#define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_0__REG DENALI_PHY_129
+#define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_0__FLD LPDDR4__DENALI_PHY_129__PHY_WRLVL_EARLY_FORCE_ZERO_0
+
+#define LPDDR4__DENALI_PHY_130_READ_MASK 0x000F03FFU
+#define LPDDR4__DENALI_PHY_130_WRITE_MASK 0x000F03FFU
+#define LPDDR4__DENALI_PHY_130__PHY_GTLVL_RDDQS_SLV_DLY_START_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_130__PHY_GTLVL_RDDQS_SLV_DLY_START_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_130__PHY_GTLVL_RDDQS_SLV_DLY_START_0_WIDTH 10U
+#define LPDDR4__PHY_GTLVL_RDDQS_SLV_DLY_START_0__REG DENALI_PHY_130
+#define LPDDR4__PHY_GTLVL_RDDQS_SLV_DLY_START_0__FLD LPDDR4__DENALI_PHY_130__PHY_GTLVL_RDDQS_SLV_DLY_START_0
+
+#define LPDDR4__DENALI_PHY_130__PHY_GTLVL_LAT_ADJ_START_0_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_130__PHY_GTLVL_LAT_ADJ_START_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_130__PHY_GTLVL_LAT_ADJ_START_0_WIDTH 4U
+#define LPDDR4__PHY_GTLVL_LAT_ADJ_START_0__REG DENALI_PHY_130
+#define LPDDR4__PHY_GTLVL_LAT_ADJ_START_0__FLD LPDDR4__DENALI_PHY_130__PHY_GTLVL_LAT_ADJ_START_0
+
+#define LPDDR4__DENALI_PHY_131_READ_MASK 0x010F07FFU
+#define LPDDR4__DENALI_PHY_131_WRITE_MASK 0x010F07FFU
+#define LPDDR4__DENALI_PHY_131__PHY_WDQLVL_DQDM_SLV_DLY_START_0_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_131__PHY_WDQLVL_DQDM_SLV_DLY_START_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_131__PHY_WDQLVL_DQDM_SLV_DLY_START_0_WIDTH 11U
+#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_0__REG DENALI_PHY_131
+#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_0__FLD LPDDR4__DENALI_PHY_131__PHY_WDQLVL_DQDM_SLV_DLY_START_0
+
+#define LPDDR4__DENALI_PHY_131__PHY_NTP_WRLAT_START_0_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_131__PHY_NTP_WRLAT_START_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_131__PHY_NTP_WRLAT_START_0_WIDTH 4U
+#define LPDDR4__PHY_NTP_WRLAT_START_0__REG DENALI_PHY_131
+#define LPDDR4__PHY_NTP_WRLAT_START_0__FLD LPDDR4__DENALI_PHY_131__PHY_NTP_WRLAT_START_0
+
+#define LPDDR4__DENALI_PHY_131__PHY_NTP_PASS_0_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_131__PHY_NTP_PASS_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_131__PHY_NTP_PASS_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_131__PHY_NTP_PASS_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_131__PHY_NTP_PASS_0_WOSET 0U
+#define LPDDR4__PHY_NTP_PASS_0__REG DENALI_PHY_131
+#define LPDDR4__PHY_NTP_PASS_0__FLD LPDDR4__DENALI_PHY_131__PHY_NTP_PASS_0
+
+#define LPDDR4__DENALI_PHY_132_READ_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_132_WRITE_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_132__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_132__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_132__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0_WIDTH 10U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0__REG DENALI_PHY_132
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0__FLD LPDDR4__DENALI_PHY_132__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0
+
+#define LPDDR4__DENALI_PHY_133_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_133_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_133__PHY_DATA_DC_DQS_CLK_ADJUST_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_133__PHY_DATA_DC_DQS_CLK_ADJUST_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_133__PHY_DATA_DC_DQS_CLK_ADJUST_0_WIDTH 8U
+#define LPDDR4__PHY_DATA_DC_DQS_CLK_ADJUST_0__REG DENALI_PHY_133
+#define LPDDR4__PHY_DATA_DC_DQS_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_133__PHY_DATA_DC_DQS_CLK_ADJUST_0
+
+#define LPDDR4__DENALI_PHY_133__PHY_DATA_DC_DQ0_CLK_ADJUST_0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_133__PHY_DATA_DC_DQ0_CLK_ADJUST_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_133__PHY_DATA_DC_DQ0_CLK_ADJUST_0_WIDTH 8U
+#define LPDDR4__PHY_DATA_DC_DQ0_CLK_ADJUST_0__REG DENALI_PHY_133
+#define LPDDR4__PHY_DATA_DC_DQ0_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_133__PHY_DATA_DC_DQ0_CLK_ADJUST_0
+
+#define LPDDR4__DENALI_PHY_133__PHY_DATA_DC_DQ1_CLK_ADJUST_0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_133__PHY_DATA_DC_DQ1_CLK_ADJUST_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_133__PHY_DATA_DC_DQ1_CLK_ADJUST_0_WIDTH 8U
+#define LPDDR4__PHY_DATA_DC_DQ1_CLK_ADJUST_0__REG DENALI_PHY_133
+#define LPDDR4__PHY_DATA_DC_DQ1_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_133__PHY_DATA_DC_DQ1_CLK_ADJUST_0
+
+#define LPDDR4__DENALI_PHY_133__PHY_DATA_DC_DQ2_CLK_ADJUST_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_133__PHY_DATA_DC_DQ2_CLK_ADJUST_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_133__PHY_DATA_DC_DQ2_CLK_ADJUST_0_WIDTH 8U
+#define LPDDR4__PHY_DATA_DC_DQ2_CLK_ADJUST_0__REG DENALI_PHY_133
+#define LPDDR4__PHY_DATA_DC_DQ2_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_133__PHY_DATA_DC_DQ2_CLK_ADJUST_0
+
+#define LPDDR4__DENALI_PHY_134_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_134_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_134__PHY_DATA_DC_DQ3_CLK_ADJUST_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_134__PHY_DATA_DC_DQ3_CLK_ADJUST_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_134__PHY_DATA_DC_DQ3_CLK_ADJUST_0_WIDTH 8U
+#define LPDDR4__PHY_DATA_DC_DQ3_CLK_ADJUST_0__REG DENALI_PHY_134
+#define LPDDR4__PHY_DATA_DC_DQ3_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_134__PHY_DATA_DC_DQ3_CLK_ADJUST_0
+
+#define LPDDR4__DENALI_PHY_134__PHY_DATA_DC_DQ4_CLK_ADJUST_0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_134__PHY_DATA_DC_DQ4_CLK_ADJUST_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_134__PHY_DATA_DC_DQ4_CLK_ADJUST_0_WIDTH 8U
+#define LPDDR4__PHY_DATA_DC_DQ4_CLK_ADJUST_0__REG DENALI_PHY_134
+#define LPDDR4__PHY_DATA_DC_DQ4_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_134__PHY_DATA_DC_DQ4_CLK_ADJUST_0
+
+#define LPDDR4__DENALI_PHY_134__PHY_DATA_DC_DQ5_CLK_ADJUST_0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_134__PHY_DATA_DC_DQ5_CLK_ADJUST_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_134__PHY_DATA_DC_DQ5_CLK_ADJUST_0_WIDTH 8U
+#define LPDDR4__PHY_DATA_DC_DQ5_CLK_ADJUST_0__REG DENALI_PHY_134
+#define LPDDR4__PHY_DATA_DC_DQ5_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_134__PHY_DATA_DC_DQ5_CLK_ADJUST_0
+
+#define LPDDR4__DENALI_PHY_134__PHY_DATA_DC_DQ6_CLK_ADJUST_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_134__PHY_DATA_DC_DQ6_CLK_ADJUST_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_134__PHY_DATA_DC_DQ6_CLK_ADJUST_0_WIDTH 8U
+#define LPDDR4__PHY_DATA_DC_DQ6_CLK_ADJUST_0__REG DENALI_PHY_134
+#define LPDDR4__PHY_DATA_DC_DQ6_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_134__PHY_DATA_DC_DQ6_CLK_ADJUST_0
+
+#define LPDDR4__DENALI_PHY_135_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_135_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_135__PHY_DATA_DC_DQ7_CLK_ADJUST_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_135__PHY_DATA_DC_DQ7_CLK_ADJUST_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_135__PHY_DATA_DC_DQ7_CLK_ADJUST_0_WIDTH 8U
+#define LPDDR4__PHY_DATA_DC_DQ7_CLK_ADJUST_0__REG DENALI_PHY_135
+#define LPDDR4__PHY_DATA_DC_DQ7_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_135__PHY_DATA_DC_DQ7_CLK_ADJUST_0
+
+#define LPDDR4__DENALI_PHY_135__PHY_DATA_DC_DM_CLK_ADJUST_0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_135__PHY_DATA_DC_DM_CLK_ADJUST_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_135__PHY_DATA_DC_DM_CLK_ADJUST_0_WIDTH 8U
+#define LPDDR4__PHY_DATA_DC_DM_CLK_ADJUST_0__REG DENALI_PHY_135
+#define LPDDR4__PHY_DATA_DC_DM_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_135__PHY_DATA_DC_DM_CLK_ADJUST_0
+
+#define LPDDR4__DENALI_PHY_135__PHY_DSLICE_PAD_BOOSTPN_SETTING_0_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_PHY_135__PHY_DSLICE_PAD_BOOSTPN_SETTING_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_135__PHY_DSLICE_PAD_BOOSTPN_SETTING_0_WIDTH 16U
+#define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_0__REG DENALI_PHY_135
+#define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_0__FLD LPDDR4__DENALI_PHY_135__PHY_DSLICE_PAD_BOOSTPN_SETTING_0
+
+#define LPDDR4__DENALI_PHY_136_READ_MASK 0x0003033FU
+#define LPDDR4__DENALI_PHY_136_WRITE_MASK 0x0003033FU
+#define LPDDR4__DENALI_PHY_136__PHY_DSLICE_PAD_RX_CTLE_SETTING_0_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_136__PHY_DSLICE_PAD_RX_CTLE_SETTING_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_136__PHY_DSLICE_PAD_RX_CTLE_SETTING_0_WIDTH 6U
+#define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_0__REG DENALI_PHY_136
+#define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_0__FLD LPDDR4__DENALI_PHY_136__PHY_DSLICE_PAD_RX_CTLE_SETTING_0
+
+#define LPDDR4__DENALI_PHY_136__PHY_DQ_FFE_0_MASK 0x00000300U
+#define LPDDR4__DENALI_PHY_136__PHY_DQ_FFE_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_136__PHY_DQ_FFE_0_WIDTH 2U
+#define LPDDR4__PHY_DQ_FFE_0__REG DENALI_PHY_136
+#define LPDDR4__PHY_DQ_FFE_0__FLD LPDDR4__DENALI_PHY_136__PHY_DQ_FFE_0
+
+#define LPDDR4__DENALI_PHY_136__PHY_DQS_FFE_0_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_136__PHY_DQS_FFE_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_136__PHY_DQS_FFE_0_WIDTH 2U
+#define LPDDR4__PHY_DQS_FFE_0__REG DENALI_PHY_136
+#define LPDDR4__PHY_DQS_FFE_0__FLD LPDDR4__DENALI_PHY_136__PHY_DQS_FFE_0
+
+#endif /* REG_LPDDR4_DATA_SLICE_0_MACROS_H_ */
diff --git a/drivers/ram/k3-ddrss/am62a/lpddr4_data_slice_1_macros.h b/drivers/ram/k3-ddrss/am62a/lpddr4_data_slice_1_macros.h
new file mode 100644
index 00000000000..c1071120f16
--- /dev/null
+++ b/drivers/ram/k3-ddrss/am62a/lpddr4_data_slice_1_macros.h
@@ -0,0 +1,2292 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef REG_LPDDR4_DATA_SLICE_1_MACROS_H_
+#define REG_LPDDR4_DATA_SLICE_1_MACROS_H_
+
+#define LPDDR4__DENALI_PHY_256_READ_MASK 0x07FF7F07U
+#define LPDDR4__DENALI_PHY_256_WRITE_MASK 0x07FF7F07U
+#define LPDDR4__DENALI_PHY_256__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_1_MASK 0x00000007U
+#define LPDDR4__DENALI_PHY_256__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_256__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_1_WIDTH 3U
+#define LPDDR4__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_1__REG DENALI_PHY_256
+#define LPDDR4__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_1__FLD LPDDR4__DENALI_PHY_256__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_1
+
+#define LPDDR4__DENALI_PHY_256__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_1_MASK 0x00007F00U
+#define LPDDR4__DENALI_PHY_256__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_256__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_1_WIDTH 7U
+#define LPDDR4__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_1__REG DENALI_PHY_256
+#define LPDDR4__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_1__FLD LPDDR4__DENALI_PHY_256__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_1
+
+#define LPDDR4__DENALI_PHY_256__PHY_CLK_WR_BYPASS_SLAVE_DELAY_1_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_256__PHY_CLK_WR_BYPASS_SLAVE_DELAY_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_256__PHY_CLK_WR_BYPASS_SLAVE_DELAY_1_WIDTH 11U
+#define LPDDR4__PHY_CLK_WR_BYPASS_SLAVE_DELAY_1__REG DENALI_PHY_256
+#define LPDDR4__PHY_CLK_WR_BYPASS_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_256__PHY_CLK_WR_BYPASS_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_257_READ_MASK 0x0703FF0FU
+#define LPDDR4__DENALI_PHY_257_WRITE_MASK 0x0703FF0FU
+#define LPDDR4__DENALI_PHY_257__PHY_IO_PAD_DELAY_TIMING_BYPASS_1_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_257__PHY_IO_PAD_DELAY_TIMING_BYPASS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_257__PHY_IO_PAD_DELAY_TIMING_BYPASS_1_WIDTH 4U
+#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_1__REG DENALI_PHY_257
+#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_1__FLD LPDDR4__DENALI_PHY_257__PHY_IO_PAD_DELAY_TIMING_BYPASS_1
+
+#define LPDDR4__DENALI_PHY_257__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1_MASK 0x0003FF00U
+#define LPDDR4__DENALI_PHY_257__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_257__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1_WIDTH 10U
+#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1__REG DENALI_PHY_257
+#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1__FLD LPDDR4__DENALI_PHY_257__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1
+
+#define LPDDR4__DENALI_PHY_257__PHY_WRITE_PATH_LAT_ADD_BYPASS_1_MASK 0x07000000U
+#define LPDDR4__DENALI_PHY_257__PHY_WRITE_PATH_LAT_ADD_BYPASS_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_257__PHY_WRITE_PATH_LAT_ADD_BYPASS_1_WIDTH 3U
+#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_1__REG DENALI_PHY_257
+#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_1__FLD LPDDR4__DENALI_PHY_257__PHY_WRITE_PATH_LAT_ADD_BYPASS_1
+
+#define LPDDR4__DENALI_PHY_258_READ_MASK 0x010303FFU
+#define LPDDR4__DENALI_PHY_258_WRITE_MASK 0x010303FFU
+#define LPDDR4__DENALI_PHY_258__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_258__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_258__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1__REG DENALI_PHY_258
+#define LPDDR4__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_258__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_258__PHY_BYPASS_TWO_CYC_PREAMBLE_1_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_258__PHY_BYPASS_TWO_CYC_PREAMBLE_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_258__PHY_BYPASS_TWO_CYC_PREAMBLE_1_WIDTH 2U
+#define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_1__REG DENALI_PHY_258
+#define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_1__FLD LPDDR4__DENALI_PHY_258__PHY_BYPASS_TWO_CYC_PREAMBLE_1
+
+#define LPDDR4__DENALI_PHY_258__PHY_CLK_BYPASS_OVERRIDE_1_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_258__PHY_CLK_BYPASS_OVERRIDE_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_258__PHY_CLK_BYPASS_OVERRIDE_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_258__PHY_CLK_BYPASS_OVERRIDE_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_258__PHY_CLK_BYPASS_OVERRIDE_1_WOSET 0U
+#define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_1__REG DENALI_PHY_258
+#define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_1__FLD LPDDR4__DENALI_PHY_258__PHY_CLK_BYPASS_OVERRIDE_1
+
+#define LPDDR4__DENALI_PHY_259_READ_MASK 0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_259_WRITE_MASK 0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ0_SHIFT_1_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ0_SHIFT_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ0_SHIFT_1_WIDTH 6U
+#define LPDDR4__PHY_SW_WRDQ0_SHIFT_1__REG DENALI_PHY_259
+#define LPDDR4__PHY_SW_WRDQ0_SHIFT_1__FLD LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ0_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ1_SHIFT_1_MASK 0x00003F00U
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ1_SHIFT_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ1_SHIFT_1_WIDTH 6U
+#define LPDDR4__PHY_SW_WRDQ1_SHIFT_1__REG DENALI_PHY_259
+#define LPDDR4__PHY_SW_WRDQ1_SHIFT_1__FLD LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ1_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ2_SHIFT_1_MASK 0x003F0000U
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ2_SHIFT_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ2_SHIFT_1_WIDTH 6U
+#define LPDDR4__PHY_SW_WRDQ2_SHIFT_1__REG DENALI_PHY_259
+#define LPDDR4__PHY_SW_WRDQ2_SHIFT_1__FLD LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ2_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ3_SHIFT_1_MASK 0x3F000000U
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ3_SHIFT_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ3_SHIFT_1_WIDTH 6U
+#define LPDDR4__PHY_SW_WRDQ3_SHIFT_1__REG DENALI_PHY_259
+#define LPDDR4__PHY_SW_WRDQ3_SHIFT_1__FLD LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ3_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_260_READ_MASK 0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_260_WRITE_MASK 0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ4_SHIFT_1_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ4_SHIFT_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ4_SHIFT_1_WIDTH 6U
+#define LPDDR4__PHY_SW_WRDQ4_SHIFT_1__REG DENALI_PHY_260
+#define LPDDR4__PHY_SW_WRDQ4_SHIFT_1__FLD LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ4_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ5_SHIFT_1_MASK 0x00003F00U
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ5_SHIFT_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ5_SHIFT_1_WIDTH 6U
+#define LPDDR4__PHY_SW_WRDQ5_SHIFT_1__REG DENALI_PHY_260
+#define LPDDR4__PHY_SW_WRDQ5_SHIFT_1__FLD LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ5_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ6_SHIFT_1_MASK 0x003F0000U
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ6_SHIFT_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ6_SHIFT_1_WIDTH 6U
+#define LPDDR4__PHY_SW_WRDQ6_SHIFT_1__REG DENALI_PHY_260
+#define LPDDR4__PHY_SW_WRDQ6_SHIFT_1__FLD LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ6_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ7_SHIFT_1_MASK 0x3F000000U
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ7_SHIFT_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ7_SHIFT_1_WIDTH 6U
+#define LPDDR4__PHY_SW_WRDQ7_SHIFT_1__REG DENALI_PHY_260
+#define LPDDR4__PHY_SW_WRDQ7_SHIFT_1__FLD LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ7_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_261_READ_MASK 0x01030F3FU
+#define LPDDR4__DENALI_PHY_261_WRITE_MASK 0x01030F3FU
+#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDM_SHIFT_1_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDM_SHIFT_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDM_SHIFT_1_WIDTH 6U
+#define LPDDR4__PHY_SW_WRDM_SHIFT_1__REG DENALI_PHY_261
+#define LPDDR4__PHY_SW_WRDM_SHIFT_1__FLD LPDDR4__DENALI_PHY_261__PHY_SW_WRDM_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDQS_SHIFT_1_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDQS_SHIFT_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDQS_SHIFT_1_WIDTH 4U
+#define LPDDR4__PHY_SW_WRDQS_SHIFT_1__REG DENALI_PHY_261
+#define LPDDR4__PHY_SW_WRDQS_SHIFT_1__FLD LPDDR4__DENALI_PHY_261__PHY_SW_WRDQS_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_261__PHY_PER_RANK_CS_MAP_1_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_261__PHY_PER_RANK_CS_MAP_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_261__PHY_PER_RANK_CS_MAP_1_WIDTH 2U
+#define LPDDR4__PHY_PER_RANK_CS_MAP_1__REG DENALI_PHY_261
+#define LPDDR4__PHY_PER_RANK_CS_MAP_1__FLD LPDDR4__DENALI_PHY_261__PHY_PER_RANK_CS_MAP_1
+
+#define LPDDR4__DENALI_PHY_261__PHY_PER_CS_TRAINING_MULTICAST_EN_1_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_261__PHY_PER_CS_TRAINING_MULTICAST_EN_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_261__PHY_PER_CS_TRAINING_MULTICAST_EN_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_261__PHY_PER_CS_TRAINING_MULTICAST_EN_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_261__PHY_PER_CS_TRAINING_MULTICAST_EN_1_WOSET 0U
+#define LPDDR4__PHY_PER_CS_TRAINING_MULTICAST_EN_1__REG DENALI_PHY_261
+#define LPDDR4__PHY_PER_CS_TRAINING_MULTICAST_EN_1__FLD LPDDR4__DENALI_PHY_261__PHY_PER_CS_TRAINING_MULTICAST_EN_1
+
+#define LPDDR4__DENALI_PHY_262_READ_MASK 0x1F1F0301U
+#define LPDDR4__DENALI_PHY_262_WRITE_MASK 0x1F1F0301U
+#define LPDDR4__DENALI_PHY_262__PHY_PER_CS_TRAINING_INDEX_1_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_262__PHY_PER_CS_TRAINING_INDEX_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_262__PHY_PER_CS_TRAINING_INDEX_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_262__PHY_PER_CS_TRAINING_INDEX_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_262__PHY_PER_CS_TRAINING_INDEX_1_WOSET 0U
+#define LPDDR4__PHY_PER_CS_TRAINING_INDEX_1__REG DENALI_PHY_262
+#define LPDDR4__PHY_PER_CS_TRAINING_INDEX_1__FLD LPDDR4__DENALI_PHY_262__PHY_PER_CS_TRAINING_INDEX_1
+
+#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1_MASK 0x00000300U
+#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1_WIDTH 2U
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1__REG DENALI_PHY_262
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1__FLD LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1
+
+#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_DLY_1_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_DLY_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_DLY_1_WIDTH 5U
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_DLY_1__REG DENALI_PHY_262
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_DLY_1__FLD LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_DLY_1
+
+#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1_WIDTH 5U
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1__REG DENALI_PHY_262
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1__FLD LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1
+
+#define LPDDR4__DENALI_PHY_263_READ_MASK 0x1F030F0FU
+#define LPDDR4__DENALI_PHY_263_WRITE_MASK 0x1F030F0FU
+#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RPTR_UPDATE_1_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RPTR_UPDATE_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RPTR_UPDATE_1_WIDTH 4U
+#define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_1__REG DENALI_PHY_263
+#define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_1__FLD LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RPTR_UPDATE_1
+
+#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1_WIDTH 4U
+#define LPDDR4__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1__REG DENALI_PHY_263
+#define LPDDR4__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1__FLD LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1
+
+#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1_WIDTH 2U
+#define LPDDR4__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1__REG DENALI_PHY_263
+#define LPDDR4__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1__FLD LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1_WIDTH 5U
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1__REG DENALI_PHY_263
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1__FLD LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1
+
+#define LPDDR4__DENALI_PHY_264_READ_MASK 0x0101FF03U
+#define LPDDR4__DENALI_PHY_264_WRITE_MASK 0x0101FF03U
+#define LPDDR4__DENALI_PHY_264__PHY_CTRL_LPBK_EN_1_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_264__PHY_CTRL_LPBK_EN_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_264__PHY_CTRL_LPBK_EN_1_WIDTH 2U
+#define LPDDR4__PHY_CTRL_LPBK_EN_1__REG DENALI_PHY_264
+#define LPDDR4__PHY_CTRL_LPBK_EN_1__FLD LPDDR4__DENALI_PHY_264__PHY_CTRL_LPBK_EN_1
+
+#define LPDDR4__DENALI_PHY_264__PHY_LPBK_CONTROL_1_MASK 0x0001FF00U
+#define LPDDR4__DENALI_PHY_264__PHY_LPBK_CONTROL_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_264__PHY_LPBK_CONTROL_1_WIDTH 9U
+#define LPDDR4__PHY_LPBK_CONTROL_1__REG DENALI_PHY_264
+#define LPDDR4__PHY_LPBK_CONTROL_1__FLD LPDDR4__DENALI_PHY_264__PHY_LPBK_CONTROL_1
+
+#define LPDDR4__DENALI_PHY_264__PHY_LPBK_DFX_TIMEOUT_EN_1_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_264__PHY_LPBK_DFX_TIMEOUT_EN_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_264__PHY_LPBK_DFX_TIMEOUT_EN_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_264__PHY_LPBK_DFX_TIMEOUT_EN_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_264__PHY_LPBK_DFX_TIMEOUT_EN_1_WOSET 0U
+#define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_1__REG DENALI_PHY_264
+#define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_1__FLD LPDDR4__DENALI_PHY_264__PHY_LPBK_DFX_TIMEOUT_EN_1
+
+#define LPDDR4__DENALI_PHY_265_READ_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_265_WRITE_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_265__PHY_GATE_DELAY_COMP_DISABLE_1_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_265__PHY_GATE_DELAY_COMP_DISABLE_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_265__PHY_GATE_DELAY_COMP_DISABLE_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_265__PHY_GATE_DELAY_COMP_DISABLE_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_265__PHY_GATE_DELAY_COMP_DISABLE_1_WOSET 0U
+#define LPDDR4__PHY_GATE_DELAY_COMP_DISABLE_1__REG DENALI_PHY_265
+#define LPDDR4__PHY_GATE_DELAY_COMP_DISABLE_1__FLD LPDDR4__DENALI_PHY_265__PHY_GATE_DELAY_COMP_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_266_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_266_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_266__PHY_AUTO_TIMING_MARGIN_CONTROL_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_266__PHY_AUTO_TIMING_MARGIN_CONTROL_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_266__PHY_AUTO_TIMING_MARGIN_CONTROL_1_WIDTH 32U
+#define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_1__REG DENALI_PHY_266
+#define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_1__FLD LPDDR4__DENALI_PHY_266__PHY_AUTO_TIMING_MARGIN_CONTROL_1
+
+#define LPDDR4__DENALI_PHY_267_READ_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_267_WRITE_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_267__PHY_AUTO_TIMING_MARGIN_OBS_1_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_267__PHY_AUTO_TIMING_MARGIN_OBS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_267__PHY_AUTO_TIMING_MARGIN_OBS_1_WIDTH 28U
+#define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_1__REG DENALI_PHY_267
+#define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_1__FLD LPDDR4__DENALI_PHY_267__PHY_AUTO_TIMING_MARGIN_OBS_1
+
+#define LPDDR4__DENALI_PHY_268_READ_MASK 0x7F0101FFU
+#define LPDDR4__DENALI_PHY_268_WRITE_MASK 0x7F0101FFU
+#define LPDDR4__DENALI_PHY_268__PHY_DQ_IDLE_1_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_268__PHY_DQ_IDLE_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_268__PHY_DQ_IDLE_1_WIDTH 9U
+#define LPDDR4__PHY_DQ_IDLE_1__REG DENALI_PHY_268
+#define LPDDR4__PHY_DQ_IDLE_1__FLD LPDDR4__DENALI_PHY_268__PHY_DQ_IDLE_1
+
+#define LPDDR4__DENALI_PHY_268__PHY_PDA_MODE_EN_1_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_268__PHY_PDA_MODE_EN_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_268__PHY_PDA_MODE_EN_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_268__PHY_PDA_MODE_EN_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_268__PHY_PDA_MODE_EN_1_WOSET 0U
+#define LPDDR4__PHY_PDA_MODE_EN_1__REG DENALI_PHY_268
+#define LPDDR4__PHY_PDA_MODE_EN_1__FLD LPDDR4__DENALI_PHY_268__PHY_PDA_MODE_EN_1
+
+#define LPDDR4__DENALI_PHY_268__PHY_PRBS_PATTERN_START_1_MASK 0x7F000000U
+#define LPDDR4__DENALI_PHY_268__PHY_PRBS_PATTERN_START_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_268__PHY_PRBS_PATTERN_START_1_WIDTH 7U
+#define LPDDR4__PHY_PRBS_PATTERN_START_1__REG DENALI_PHY_268
+#define LPDDR4__PHY_PRBS_PATTERN_START_1__FLD LPDDR4__DENALI_PHY_268__PHY_PRBS_PATTERN_START_1
+
+#define LPDDR4__DENALI_PHY_269_READ_MASK 0x010101FFU
+#define LPDDR4__DENALI_PHY_269_WRITE_MASK 0x010101FFU
+#define LPDDR4__DENALI_PHY_269__PHY_PRBS_PATTERN_MASK_1_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_269__PHY_PRBS_PATTERN_MASK_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_269__PHY_PRBS_PATTERN_MASK_1_WIDTH 9U
+#define LPDDR4__PHY_PRBS_PATTERN_MASK_1__REG DENALI_PHY_269
+#define LPDDR4__PHY_PRBS_PATTERN_MASK_1__FLD LPDDR4__DENALI_PHY_269__PHY_PRBS_PATTERN_MASK_1
+
+#define LPDDR4__DENALI_PHY_269__PHY_RDLVL_MULTI_PATT_ENABLE_1_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_269__PHY_RDLVL_MULTI_PATT_ENABLE_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_269__PHY_RDLVL_MULTI_PATT_ENABLE_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_269__PHY_RDLVL_MULTI_PATT_ENABLE_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_269__PHY_RDLVL_MULTI_PATT_ENABLE_1_WOSET 0U
+#define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_1__REG DENALI_PHY_269
+#define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_1__FLD LPDDR4__DENALI_PHY_269__PHY_RDLVL_MULTI_PATT_ENABLE_1
+
+#define LPDDR4__DENALI_PHY_269__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_269__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_269__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_269__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_269__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1_WOSET 0U
+#define LPDDR4__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1__REG DENALI_PHY_269
+#define LPDDR4__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1__FLD LPDDR4__DENALI_PHY_269__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_270_READ_MASK 0x03FF7F3FU
+#define LPDDR4__DENALI_PHY_270_WRITE_MASK 0x03FF7F3FU
+#define LPDDR4__DENALI_PHY_270__PHY_VREF_INITIAL_STEPSIZE_1_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_270__PHY_VREF_INITIAL_STEPSIZE_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_270__PHY_VREF_INITIAL_STEPSIZE_1_WIDTH 6U
+#define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_1__REG DENALI_PHY_270
+#define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_1__FLD LPDDR4__DENALI_PHY_270__PHY_VREF_INITIAL_STEPSIZE_1
+
+#define LPDDR4__DENALI_PHY_270__PHY_VREF_TRAIN_OBS_1_MASK 0x00007F00U
+#define LPDDR4__DENALI_PHY_270__PHY_VREF_TRAIN_OBS_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_270__PHY_VREF_TRAIN_OBS_1_WIDTH 7U
+#define LPDDR4__PHY_VREF_TRAIN_OBS_1__REG DENALI_PHY_270
+#define LPDDR4__PHY_VREF_TRAIN_OBS_1__FLD LPDDR4__DENALI_PHY_270__PHY_VREF_TRAIN_OBS_1
+
+#define LPDDR4__DENALI_PHY_270__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_270__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_270__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1__REG DENALI_PHY_270
+#define LPDDR4__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_270__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_271_READ_MASK 0x01FF000FU
+#define LPDDR4__DENALI_PHY_271_WRITE_MASK 0x01FF000FU
+#define LPDDR4__DENALI_PHY_271__PHY_GATE_ERROR_DELAY_SELECT_1_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_271__PHY_GATE_ERROR_DELAY_SELECT_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_271__PHY_GATE_ERROR_DELAY_SELECT_1_WIDTH 4U
+#define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_1__REG DENALI_PHY_271
+#define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_1__FLD LPDDR4__DENALI_PHY_271__PHY_GATE_ERROR_DELAY_SELECT_1
+
+#define LPDDR4__DENALI_PHY_271__SC_PHY_SNAP_OBS_REGS_1_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_271__SC_PHY_SNAP_OBS_REGS_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_271__SC_PHY_SNAP_OBS_REGS_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_271__SC_PHY_SNAP_OBS_REGS_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_271__SC_PHY_SNAP_OBS_REGS_1_WOSET 0U
+#define LPDDR4__SC_PHY_SNAP_OBS_REGS_1__REG DENALI_PHY_271
+#define LPDDR4__SC_PHY_SNAP_OBS_REGS_1__FLD LPDDR4__DENALI_PHY_271__SC_PHY_SNAP_OBS_REGS_1
+
+#define LPDDR4__DENALI_PHY_271__PHY_GATE_SMPL1_SLAVE_DELAY_1_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_271__PHY_GATE_SMPL1_SLAVE_DELAY_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_271__PHY_GATE_SMPL1_SLAVE_DELAY_1_WIDTH 9U
+#define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_1__REG DENALI_PHY_271
+#define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_271__PHY_GATE_SMPL1_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_272_READ_MASK 0x01FF0701U
+#define LPDDR4__DENALI_PHY_272_WRITE_MASK 0x01FF0701U
+#define LPDDR4__DENALI_PHY_272__PHY_LPDDR_1_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_272__PHY_LPDDR_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_272__PHY_LPDDR_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_272__PHY_LPDDR_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_272__PHY_LPDDR_1_WOSET 0U
+#define LPDDR4__PHY_LPDDR_1__REG DENALI_PHY_272
+#define LPDDR4__PHY_LPDDR_1__FLD LPDDR4__DENALI_PHY_272__PHY_LPDDR_1
+
+#define LPDDR4__DENALI_PHY_272__PHY_MEM_CLASS_1_MASK 0x00000700U
+#define LPDDR4__DENALI_PHY_272__PHY_MEM_CLASS_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_272__PHY_MEM_CLASS_1_WIDTH 3U
+#define LPDDR4__PHY_MEM_CLASS_1__REG DENALI_PHY_272
+#define LPDDR4__PHY_MEM_CLASS_1__FLD LPDDR4__DENALI_PHY_272__PHY_MEM_CLASS_1
+
+#define LPDDR4__DENALI_PHY_272__PHY_GATE_SMPL2_SLAVE_DELAY_1_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_272__PHY_GATE_SMPL2_SLAVE_DELAY_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_272__PHY_GATE_SMPL2_SLAVE_DELAY_1_WIDTH 9U
+#define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_1__REG DENALI_PHY_272
+#define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_272__PHY_GATE_SMPL2_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_273_READ_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_273_WRITE_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_273__ON_FLY_GATE_ADJUST_EN_1_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_273__ON_FLY_GATE_ADJUST_EN_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_273__ON_FLY_GATE_ADJUST_EN_1_WIDTH 2U
+#define LPDDR4__ON_FLY_GATE_ADJUST_EN_1__REG DENALI_PHY_273
+#define LPDDR4__ON_FLY_GATE_ADJUST_EN_1__FLD LPDDR4__DENALI_PHY_273__ON_FLY_GATE_ADJUST_EN_1
+
+#define LPDDR4__DENALI_PHY_274_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_274_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_274__PHY_GATE_TRACKING_OBS_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_274__PHY_GATE_TRACKING_OBS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_274__PHY_GATE_TRACKING_OBS_1_WIDTH 32U
+#define LPDDR4__PHY_GATE_TRACKING_OBS_1__REG DENALI_PHY_274
+#define LPDDR4__PHY_GATE_TRACKING_OBS_1__FLD LPDDR4__DENALI_PHY_274__PHY_GATE_TRACKING_OBS_1
+
+#define LPDDR4__DENALI_PHY_275_READ_MASK 0x00000301U
+#define LPDDR4__DENALI_PHY_275_WRITE_MASK 0x00000301U
+#define LPDDR4__DENALI_PHY_275__PHY_DFI40_POLARITY_1_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_275__PHY_DFI40_POLARITY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_275__PHY_DFI40_POLARITY_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_275__PHY_DFI40_POLARITY_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_275__PHY_DFI40_POLARITY_1_WOSET 0U
+#define LPDDR4__PHY_DFI40_POLARITY_1__REG DENALI_PHY_275
+#define LPDDR4__PHY_DFI40_POLARITY_1__FLD LPDDR4__DENALI_PHY_275__PHY_DFI40_POLARITY_1
+
+#define LPDDR4__DENALI_PHY_275__PHY_LP4_PST_AMBLE_1_MASK 0x00000300U
+#define LPDDR4__DENALI_PHY_275__PHY_LP4_PST_AMBLE_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_275__PHY_LP4_PST_AMBLE_1_WIDTH 2U
+#define LPDDR4__PHY_LP4_PST_AMBLE_1__REG DENALI_PHY_275
+#define LPDDR4__PHY_LP4_PST_AMBLE_1__FLD LPDDR4__DENALI_PHY_275__PHY_LP4_PST_AMBLE_1
+
+#define LPDDR4__DENALI_PHY_276_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_276_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_276__PHY_RDLVL_PATT8_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_276__PHY_RDLVL_PATT8_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_276__PHY_RDLVL_PATT8_1_WIDTH 32U
+#define LPDDR4__PHY_RDLVL_PATT8_1__REG DENALI_PHY_276
+#define LPDDR4__PHY_RDLVL_PATT8_1__FLD LPDDR4__DENALI_PHY_276__PHY_RDLVL_PATT8_1
+
+#define LPDDR4__DENALI_PHY_277_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_277_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_277__PHY_RDLVL_PATT9_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_277__PHY_RDLVL_PATT9_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_277__PHY_RDLVL_PATT9_1_WIDTH 32U
+#define LPDDR4__PHY_RDLVL_PATT9_1__REG DENALI_PHY_277
+#define LPDDR4__PHY_RDLVL_PATT9_1__FLD LPDDR4__DENALI_PHY_277__PHY_RDLVL_PATT9_1
+
+#define LPDDR4__DENALI_PHY_278_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_278_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_278__PHY_RDLVL_PATT10_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_278__PHY_RDLVL_PATT10_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_278__PHY_RDLVL_PATT10_1_WIDTH 32U
+#define LPDDR4__PHY_RDLVL_PATT10_1__REG DENALI_PHY_278
+#define LPDDR4__PHY_RDLVL_PATT10_1__FLD LPDDR4__DENALI_PHY_278__PHY_RDLVL_PATT10_1
+
+#define LPDDR4__DENALI_PHY_279_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_279_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_279__PHY_RDLVL_PATT11_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_279__PHY_RDLVL_PATT11_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_279__PHY_RDLVL_PATT11_1_WIDTH 32U
+#define LPDDR4__PHY_RDLVL_PATT11_1__REG DENALI_PHY_279
+#define LPDDR4__PHY_RDLVL_PATT11_1__FLD LPDDR4__DENALI_PHY_279__PHY_RDLVL_PATT11_1
+
+#define LPDDR4__DENALI_PHY_280_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_280_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_280__PHY_RDLVL_PATT12_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_280__PHY_RDLVL_PATT12_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_280__PHY_RDLVL_PATT12_1_WIDTH 32U
+#define LPDDR4__PHY_RDLVL_PATT12_1__REG DENALI_PHY_280
+#define LPDDR4__PHY_RDLVL_PATT12_1__FLD LPDDR4__DENALI_PHY_280__PHY_RDLVL_PATT12_1
+
+#define LPDDR4__DENALI_PHY_281_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_281_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_281__PHY_RDLVL_PATT13_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_281__PHY_RDLVL_PATT13_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_281__PHY_RDLVL_PATT13_1_WIDTH 32U
+#define LPDDR4__PHY_RDLVL_PATT13_1__REG DENALI_PHY_281
+#define LPDDR4__PHY_RDLVL_PATT13_1__FLD LPDDR4__DENALI_PHY_281__PHY_RDLVL_PATT13_1
+
+#define LPDDR4__DENALI_PHY_282_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_282_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_282__PHY_RDLVL_PATT14_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_282__PHY_RDLVL_PATT14_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_282__PHY_RDLVL_PATT14_1_WIDTH 32U
+#define LPDDR4__PHY_RDLVL_PATT14_1__REG DENALI_PHY_282
+#define LPDDR4__PHY_RDLVL_PATT14_1__FLD LPDDR4__DENALI_PHY_282__PHY_RDLVL_PATT14_1
+
+#define LPDDR4__DENALI_PHY_283_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_283_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_283__PHY_RDLVL_PATT15_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_283__PHY_RDLVL_PATT15_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_283__PHY_RDLVL_PATT15_1_WIDTH 32U
+#define LPDDR4__PHY_RDLVL_PATT15_1__REG DENALI_PHY_283
+#define LPDDR4__PHY_RDLVL_PATT15_1__FLD LPDDR4__DENALI_PHY_283__PHY_RDLVL_PATT15_1
+
+#define LPDDR4__DENALI_PHY_284_READ_MASK 0x070F0107U
+#define LPDDR4__DENALI_PHY_284_WRITE_MASK 0x070F0107U
+#define LPDDR4__DENALI_PHY_284__PHY_SLAVE_LOOP_CNT_UPDATE_1_MASK 0x00000007U
+#define LPDDR4__DENALI_PHY_284__PHY_SLAVE_LOOP_CNT_UPDATE_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_284__PHY_SLAVE_LOOP_CNT_UPDATE_1_WIDTH 3U
+#define LPDDR4__PHY_SLAVE_LOOP_CNT_UPDATE_1__REG DENALI_PHY_284
+#define LPDDR4__PHY_SLAVE_LOOP_CNT_UPDATE_1__FLD LPDDR4__DENALI_PHY_284__PHY_SLAVE_LOOP_CNT_UPDATE_1
+
+#define LPDDR4__DENALI_PHY_284__PHY_SW_FIFO_PTR_RST_DISABLE_1_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_284__PHY_SW_FIFO_PTR_RST_DISABLE_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_284__PHY_SW_FIFO_PTR_RST_DISABLE_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_284__PHY_SW_FIFO_PTR_RST_DISABLE_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_284__PHY_SW_FIFO_PTR_RST_DISABLE_1_WOSET 0U
+#define LPDDR4__PHY_SW_FIFO_PTR_RST_DISABLE_1__REG DENALI_PHY_284
+#define LPDDR4__PHY_SW_FIFO_PTR_RST_DISABLE_1__FLD LPDDR4__DENALI_PHY_284__PHY_SW_FIFO_PTR_RST_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_284__PHY_MASTER_DLY_LOCK_OBS_SELECT_1_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_284__PHY_MASTER_DLY_LOCK_OBS_SELECT_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_284__PHY_MASTER_DLY_LOCK_OBS_SELECT_1_WIDTH 4U
+#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_SELECT_1__REG DENALI_PHY_284
+#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_284__PHY_MASTER_DLY_LOCK_OBS_SELECT_1
+
+#define LPDDR4__DENALI_PHY_284__PHY_RDDQ_ENC_OBS_SELECT_1_MASK 0x07000000U
+#define LPDDR4__DENALI_PHY_284__PHY_RDDQ_ENC_OBS_SELECT_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_284__PHY_RDDQ_ENC_OBS_SELECT_1_WIDTH 3U
+#define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_1__REG DENALI_PHY_284
+#define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_284__PHY_RDDQ_ENC_OBS_SELECT_1
+
+#define LPDDR4__DENALI_PHY_285_READ_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_285_WRITE_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_285__PHY_RDDQS_DQ_ENC_OBS_SELECT_1_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_285__PHY_RDDQS_DQ_ENC_OBS_SELECT_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_285__PHY_RDDQS_DQ_ENC_OBS_SELECT_1_WIDTH 4U
+#define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_1__REG DENALI_PHY_285
+#define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_285__PHY_RDDQS_DQ_ENC_OBS_SELECT_1
+
+#define LPDDR4__DENALI_PHY_285__PHY_WR_ENC_OBS_SELECT_1_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_285__PHY_WR_ENC_OBS_SELECT_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_285__PHY_WR_ENC_OBS_SELECT_1_WIDTH 4U
+#define LPDDR4__PHY_WR_ENC_OBS_SELECT_1__REG DENALI_PHY_285
+#define LPDDR4__PHY_WR_ENC_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_285__PHY_WR_ENC_OBS_SELECT_1
+
+#define LPDDR4__DENALI_PHY_285__PHY_WR_SHIFT_OBS_SELECT_1_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_285__PHY_WR_SHIFT_OBS_SELECT_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_285__PHY_WR_SHIFT_OBS_SELECT_1_WIDTH 4U
+#define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_1__REG DENALI_PHY_285
+#define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_285__PHY_WR_SHIFT_OBS_SELECT_1
+
+#define LPDDR4__DENALI_PHY_285__PHY_FIFO_PTR_OBS_SELECT_1_MASK 0x0F000000U
+#define LPDDR4__DENALI_PHY_285__PHY_FIFO_PTR_OBS_SELECT_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_285__PHY_FIFO_PTR_OBS_SELECT_1_WIDTH 4U
+#define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_1__REG DENALI_PHY_285
+#define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_285__PHY_FIFO_PTR_OBS_SELECT_1
+
+#define LPDDR4__DENALI_PHY_286_READ_MASK 0x3F030001U
+#define LPDDR4__DENALI_PHY_286_WRITE_MASK 0x3F030001U
+#define LPDDR4__DENALI_PHY_286__PHY_LVL_DEBUG_MODE_1_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_286__PHY_LVL_DEBUG_MODE_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_286__PHY_LVL_DEBUG_MODE_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_286__PHY_LVL_DEBUG_MODE_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_286__PHY_LVL_DEBUG_MODE_1_WOSET 0U
+#define LPDDR4__PHY_LVL_DEBUG_MODE_1__REG DENALI_PHY_286
+#define LPDDR4__PHY_LVL_DEBUG_MODE_1__FLD LPDDR4__DENALI_PHY_286__PHY_LVL_DEBUG_MODE_1
+
+#define LPDDR4__DENALI_PHY_286__SC_PHY_LVL_DEBUG_CONT_1_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_286__SC_PHY_LVL_DEBUG_CONT_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_286__SC_PHY_LVL_DEBUG_CONT_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_286__SC_PHY_LVL_DEBUG_CONT_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_286__SC_PHY_LVL_DEBUG_CONT_1_WOSET 0U
+#define LPDDR4__SC_PHY_LVL_DEBUG_CONT_1__REG DENALI_PHY_286
+#define LPDDR4__SC_PHY_LVL_DEBUG_CONT_1__FLD LPDDR4__DENALI_PHY_286__SC_PHY_LVL_DEBUG_CONT_1
+
+#define LPDDR4__DENALI_PHY_286__PHY_WRLVL_ALGO_1_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_286__PHY_WRLVL_ALGO_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_286__PHY_WRLVL_ALGO_1_WIDTH 2U
+#define LPDDR4__PHY_WRLVL_ALGO_1__REG DENALI_PHY_286
+#define LPDDR4__PHY_WRLVL_ALGO_1__FLD LPDDR4__DENALI_PHY_286__PHY_WRLVL_ALGO_1
+
+#define LPDDR4__DENALI_PHY_286__PHY_WRLVL_CAPTURE_CNT_1_MASK 0x3F000000U
+#define LPDDR4__DENALI_PHY_286__PHY_WRLVL_CAPTURE_CNT_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_286__PHY_WRLVL_CAPTURE_CNT_1_WIDTH 6U
+#define LPDDR4__PHY_WRLVL_CAPTURE_CNT_1__REG DENALI_PHY_286
+#define LPDDR4__PHY_WRLVL_CAPTURE_CNT_1__FLD LPDDR4__DENALI_PHY_286__PHY_WRLVL_CAPTURE_CNT_1
+
+#define LPDDR4__DENALI_PHY_287_READ_MASK 0x0F3FFF0FU
+#define LPDDR4__DENALI_PHY_287_WRITE_MASK 0x0F3FFF0FU
+#define LPDDR4__DENALI_PHY_287__PHY_WRLVL_UPDT_WAIT_CNT_1_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_287__PHY_WRLVL_UPDT_WAIT_CNT_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_287__PHY_WRLVL_UPDT_WAIT_CNT_1_WIDTH 4U
+#define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_1__REG DENALI_PHY_287
+#define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_287__PHY_WRLVL_UPDT_WAIT_CNT_1
+
+#define LPDDR4__DENALI_PHY_287__PHY_DQ_MASK_1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_287__PHY_DQ_MASK_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_287__PHY_DQ_MASK_1_WIDTH 8U
+#define LPDDR4__PHY_DQ_MASK_1__REG DENALI_PHY_287
+#define LPDDR4__PHY_DQ_MASK_1__FLD LPDDR4__DENALI_PHY_287__PHY_DQ_MASK_1
+
+#define LPDDR4__DENALI_PHY_287__PHY_GTLVL_CAPTURE_CNT_1_MASK 0x003F0000U
+#define LPDDR4__DENALI_PHY_287__PHY_GTLVL_CAPTURE_CNT_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_287__PHY_GTLVL_CAPTURE_CNT_1_WIDTH 6U
+#define LPDDR4__PHY_GTLVL_CAPTURE_CNT_1__REG DENALI_PHY_287
+#define LPDDR4__PHY_GTLVL_CAPTURE_CNT_1__FLD LPDDR4__DENALI_PHY_287__PHY_GTLVL_CAPTURE_CNT_1
+
+#define LPDDR4__DENALI_PHY_287__PHY_GTLVL_UPDT_WAIT_CNT_1_MASK 0x0F000000U
+#define LPDDR4__DENALI_PHY_287__PHY_GTLVL_UPDT_WAIT_CNT_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_287__PHY_GTLVL_UPDT_WAIT_CNT_1_WIDTH 4U
+#define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_1__REG DENALI_PHY_287
+#define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_287__PHY_GTLVL_UPDT_WAIT_CNT_1
+
+#define LPDDR4__DENALI_PHY_288_READ_MASK 0x1F030F3FU
+#define LPDDR4__DENALI_PHY_288_WRITE_MASK 0x1F030F3FU
+#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_CAPTURE_CNT_1_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_CAPTURE_CNT_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_CAPTURE_CNT_1_WIDTH 6U
+#define LPDDR4__PHY_RDLVL_CAPTURE_CNT_1__REG DENALI_PHY_288
+#define LPDDR4__PHY_RDLVL_CAPTURE_CNT_1__FLD LPDDR4__DENALI_PHY_288__PHY_RDLVL_CAPTURE_CNT_1
+
+#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_UPDT_WAIT_CNT_1_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_UPDT_WAIT_CNT_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_UPDT_WAIT_CNT_1_WIDTH 4U
+#define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_1__REG DENALI_PHY_288
+#define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_288__PHY_RDLVL_UPDT_WAIT_CNT_1
+
+#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_OP_MODE_1_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_OP_MODE_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_OP_MODE_1_WIDTH 2U
+#define LPDDR4__PHY_RDLVL_OP_MODE_1__REG DENALI_PHY_288
+#define LPDDR4__PHY_RDLVL_OP_MODE_1__FLD LPDDR4__DENALI_PHY_288__PHY_RDLVL_OP_MODE_1
+
+#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1_WIDTH 5U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1__REG DENALI_PHY_288
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_288__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1
+
+#define LPDDR4__DENALI_PHY_289_READ_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_289_WRITE_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_289__PHY_RDLVL_DATA_MASK_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_289__PHY_RDLVL_DATA_MASK_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_289__PHY_RDLVL_DATA_MASK_1_WIDTH 8U
+#define LPDDR4__PHY_RDLVL_DATA_MASK_1__REG DENALI_PHY_289
+#define LPDDR4__PHY_RDLVL_DATA_MASK_1__FLD LPDDR4__DENALI_PHY_289__PHY_RDLVL_DATA_MASK_1
+
+#define LPDDR4__DENALI_PHY_289__PHY_RDLVL_DATA_SWIZZLE_1_MASK 0x03FFFF00U
+#define LPDDR4__DENALI_PHY_289__PHY_RDLVL_DATA_SWIZZLE_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_289__PHY_RDLVL_DATA_SWIZZLE_1_WIDTH 18U
+#define LPDDR4__PHY_RDLVL_DATA_SWIZZLE_1__REG DENALI_PHY_289
+#define LPDDR4__PHY_RDLVL_DATA_SWIZZLE_1__FLD LPDDR4__DENALI_PHY_289__PHY_RDLVL_DATA_SWIZZLE_1
+
+#define LPDDR4__DENALI_PHY_290_READ_MASK 0x00073FFFU
+#define LPDDR4__DENALI_PHY_290_WRITE_MASK 0x00073FFFU
+#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_CLK_JITTER_TOLERANCE_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_CLK_JITTER_TOLERANCE_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_CLK_JITTER_TOLERANCE_1_WIDTH 8U
+#define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_1__REG DENALI_PHY_290
+#define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_1__FLD LPDDR4__DENALI_PHY_290__PHY_WDQLVL_CLK_JITTER_TOLERANCE_1
+
+#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_BURST_CNT_1_MASK 0x00003F00U
+#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_BURST_CNT_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_BURST_CNT_1_WIDTH 6U
+#define LPDDR4__PHY_WDQLVL_BURST_CNT_1__REG DENALI_PHY_290
+#define LPDDR4__PHY_WDQLVL_BURST_CNT_1__FLD LPDDR4__DENALI_PHY_290__PHY_WDQLVL_BURST_CNT_1
+
+#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_PATT_1_MASK 0x00070000U
+#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_PATT_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_PATT_1_WIDTH 3U
+#define LPDDR4__PHY_WDQLVL_PATT_1__REG DENALI_PHY_290
+#define LPDDR4__PHY_WDQLVL_PATT_1__FLD LPDDR4__DENALI_PHY_290__PHY_WDQLVL_PATT_1
+
+#define LPDDR4__DENALI_PHY_291_READ_MASK 0x0F0F07FFU
+#define LPDDR4__DENALI_PHY_291_WRITE_MASK 0x0F0F07FFU
+#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1_WIDTH 11U
+#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1__REG DENALI_PHY_291
+#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1__FLD LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1
+
+#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_UPDT_WAIT_CNT_1_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_UPDT_WAIT_CNT_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_UPDT_WAIT_CNT_1_WIDTH 4U
+#define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_1__REG DENALI_PHY_291
+#define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_291__PHY_WDQLVL_UPDT_WAIT_CNT_1
+
+#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DQDM_OBS_SELECT_1_MASK 0x0F000000U
+#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DQDM_OBS_SELECT_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DQDM_OBS_SELECT_1_WIDTH 4U
+#define LPDDR4__PHY_WDQLVL_DQDM_OBS_SELECT_1__REG DENALI_PHY_291
+#define LPDDR4__PHY_WDQLVL_DQDM_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DQDM_OBS_SELECT_1
+
+#define LPDDR4__DENALI_PHY_292_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_292_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_292__PHY_WDQLVL_PERIODIC_OBS_SELECT_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_292__PHY_WDQLVL_PERIODIC_OBS_SELECT_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_292__PHY_WDQLVL_PERIODIC_OBS_SELECT_1_WIDTH 8U
+#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_SELECT_1__REG DENALI_PHY_292
+#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_292__PHY_WDQLVL_PERIODIC_OBS_SELECT_1
+
+#define LPDDR4__DENALI_PHY_292__PHY_WDQLVL_DQ_SLV_DELTA_1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_292__PHY_WDQLVL_DQ_SLV_DELTA_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_292__PHY_WDQLVL_DQ_SLV_DELTA_1_WIDTH 8U
+#define LPDDR4__PHY_WDQLVL_DQ_SLV_DELTA_1__REG DENALI_PHY_292
+#define LPDDR4__PHY_WDQLVL_DQ_SLV_DELTA_1__FLD LPDDR4__DENALI_PHY_292__PHY_WDQLVL_DQ_SLV_DELTA_1
+
+#define LPDDR4__DENALI_PHY_292__PHY_WDQLVL_DM_DLY_STEP_1_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_292__PHY_WDQLVL_DM_DLY_STEP_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_292__PHY_WDQLVL_DM_DLY_STEP_1_WIDTH 4U
+#define LPDDR4__PHY_WDQLVL_DM_DLY_STEP_1__REG DENALI_PHY_292
+#define LPDDR4__PHY_WDQLVL_DM_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_292__PHY_WDQLVL_DM_DLY_STEP_1
+
+#define LPDDR4__DENALI_PHY_292__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_292__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_292__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_292__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_292__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1_WOSET 0U
+#define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1__REG DENALI_PHY_292
+#define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1__FLD LPDDR4__DENALI_PHY_292__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1
+
+#define LPDDR4__DENALI_PHY_293_READ_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_293_WRITE_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_293__PHY_WDQLVL_DATADM_MASK_1_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_293__PHY_WDQLVL_DATADM_MASK_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_293__PHY_WDQLVL_DATADM_MASK_1_WIDTH 9U
+#define LPDDR4__PHY_WDQLVL_DATADM_MASK_1__REG DENALI_PHY_293
+#define LPDDR4__PHY_WDQLVL_DATADM_MASK_1__FLD LPDDR4__DENALI_PHY_293__PHY_WDQLVL_DATADM_MASK_1
+
+#define LPDDR4__DENALI_PHY_294_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_294_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_294__PHY_USER_PATT0_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_294__PHY_USER_PATT0_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_294__PHY_USER_PATT0_1_WIDTH 32U
+#define LPDDR4__PHY_USER_PATT0_1__REG DENALI_PHY_294
+#define LPDDR4__PHY_USER_PATT0_1__FLD LPDDR4__DENALI_PHY_294__PHY_USER_PATT0_1
+
+#define LPDDR4__DENALI_PHY_295_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_295_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_295__PHY_USER_PATT1_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_295__PHY_USER_PATT1_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_295__PHY_USER_PATT1_1_WIDTH 32U
+#define LPDDR4__PHY_USER_PATT1_1__REG DENALI_PHY_295
+#define LPDDR4__PHY_USER_PATT1_1__FLD LPDDR4__DENALI_PHY_295__PHY_USER_PATT1_1
+
+#define LPDDR4__DENALI_PHY_296_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_296_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_296__PHY_USER_PATT2_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_296__PHY_USER_PATT2_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_296__PHY_USER_PATT2_1_WIDTH 32U
+#define LPDDR4__PHY_USER_PATT2_1__REG DENALI_PHY_296
+#define LPDDR4__PHY_USER_PATT2_1__FLD LPDDR4__DENALI_PHY_296__PHY_USER_PATT2_1
+
+#define LPDDR4__DENALI_PHY_297_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_297_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_297__PHY_USER_PATT3_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_297__PHY_USER_PATT3_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_297__PHY_USER_PATT3_1_WIDTH 32U
+#define LPDDR4__PHY_USER_PATT3_1__REG DENALI_PHY_297
+#define LPDDR4__PHY_USER_PATT3_1__FLD LPDDR4__DENALI_PHY_297__PHY_USER_PATT3_1
+
+#define LPDDR4__DENALI_PHY_298_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PHY_298_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PHY_298__PHY_USER_PATT4_1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_298__PHY_USER_PATT4_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_298__PHY_USER_PATT4_1_WIDTH 16U
+#define LPDDR4__PHY_USER_PATT4_1__REG DENALI_PHY_298
+#define LPDDR4__PHY_USER_PATT4_1__FLD LPDDR4__DENALI_PHY_298__PHY_USER_PATT4_1
+
+#define LPDDR4__DENALI_PHY_298__PHY_NTP_MULT_TRAIN_1_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_298__PHY_NTP_MULT_TRAIN_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_298__PHY_NTP_MULT_TRAIN_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_298__PHY_NTP_MULT_TRAIN_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_298__PHY_NTP_MULT_TRAIN_1_WOSET 0U
+#define LPDDR4__PHY_NTP_MULT_TRAIN_1__REG DENALI_PHY_298
+#define LPDDR4__PHY_NTP_MULT_TRAIN_1__FLD LPDDR4__DENALI_PHY_298__PHY_NTP_MULT_TRAIN_1
+
+#define LPDDR4__DENALI_PHY_299_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_299_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_299__PHY_NTP_EARLY_THRESHOLD_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_299__PHY_NTP_EARLY_THRESHOLD_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_299__PHY_NTP_EARLY_THRESHOLD_1_WIDTH 10U
+#define LPDDR4__PHY_NTP_EARLY_THRESHOLD_1__REG DENALI_PHY_299
+#define LPDDR4__PHY_NTP_EARLY_THRESHOLD_1__FLD LPDDR4__DENALI_PHY_299__PHY_NTP_EARLY_THRESHOLD_1
+
+#define LPDDR4__DENALI_PHY_299__PHY_NTP_PERIOD_THRESHOLD_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_299__PHY_NTP_PERIOD_THRESHOLD_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_299__PHY_NTP_PERIOD_THRESHOLD_1_WIDTH 10U
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_1__REG DENALI_PHY_299
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_1__FLD LPDDR4__DENALI_PHY_299__PHY_NTP_PERIOD_THRESHOLD_1
+
+#define LPDDR4__DENALI_PHY_300_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_300_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_300__PHY_NTP_PERIOD_THRESHOLD_MIN_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_300__PHY_NTP_PERIOD_THRESHOLD_MIN_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_300__PHY_NTP_PERIOD_THRESHOLD_MIN_1_WIDTH 10U
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MIN_1__REG DENALI_PHY_300
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MIN_1__FLD LPDDR4__DENALI_PHY_300__PHY_NTP_PERIOD_THRESHOLD_MIN_1
+
+#define LPDDR4__DENALI_PHY_300__PHY_NTP_PERIOD_THRESHOLD_MAX_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_300__PHY_NTP_PERIOD_THRESHOLD_MAX_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_300__PHY_NTP_PERIOD_THRESHOLD_MAX_1_WIDTH 10U
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_1__REG DENALI_PHY_300
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_1__FLD LPDDR4__DENALI_PHY_300__PHY_NTP_PERIOD_THRESHOLD_MAX_1
+
+#define LPDDR4__DENALI_PHY_301_READ_MASK 0x00FF0001U
+#define LPDDR4__DENALI_PHY_301_WRITE_MASK 0x00FF0001U
+#define LPDDR4__DENALI_PHY_301__PHY_CALVL_VREF_DRIVING_SLICE_1_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_301__PHY_CALVL_VREF_DRIVING_SLICE_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_301__PHY_CALVL_VREF_DRIVING_SLICE_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_301__PHY_CALVL_VREF_DRIVING_SLICE_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_301__PHY_CALVL_VREF_DRIVING_SLICE_1_WOSET 0U
+#define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_1__REG DENALI_PHY_301
+#define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_1__FLD LPDDR4__DENALI_PHY_301__PHY_CALVL_VREF_DRIVING_SLICE_1
+
+#define LPDDR4__DENALI_PHY_301__SC_PHY_MANUAL_CLEAR_1_MASK 0x00003F00U
+#define LPDDR4__DENALI_PHY_301__SC_PHY_MANUAL_CLEAR_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_301__SC_PHY_MANUAL_CLEAR_1_WIDTH 6U
+#define LPDDR4__SC_PHY_MANUAL_CLEAR_1__REG DENALI_PHY_301
+#define LPDDR4__SC_PHY_MANUAL_CLEAR_1__FLD LPDDR4__DENALI_PHY_301__SC_PHY_MANUAL_CLEAR_1
+
+#define LPDDR4__DENALI_PHY_301__PHY_FIFO_PTR_OBS_1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_301__PHY_FIFO_PTR_OBS_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_301__PHY_FIFO_PTR_OBS_1_WIDTH 8U
+#define LPDDR4__PHY_FIFO_PTR_OBS_1__REG DENALI_PHY_301
+#define LPDDR4__PHY_FIFO_PTR_OBS_1__FLD LPDDR4__DENALI_PHY_301__PHY_FIFO_PTR_OBS_1
+
+#define LPDDR4__DENALI_PHY_302_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_302_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_302__PHY_LPBK_RESULT_OBS_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_302__PHY_LPBK_RESULT_OBS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_302__PHY_LPBK_RESULT_OBS_1_WIDTH 32U
+#define LPDDR4__PHY_LPBK_RESULT_OBS_1__REG DENALI_PHY_302
+#define LPDDR4__PHY_LPBK_RESULT_OBS_1__FLD LPDDR4__DENALI_PHY_302__PHY_LPBK_RESULT_OBS_1
+
+#define LPDDR4__DENALI_PHY_303_READ_MASK 0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_303_WRITE_MASK 0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_303__PHY_LPBK_ERROR_COUNT_OBS_1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_303__PHY_LPBK_ERROR_COUNT_OBS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_303__PHY_LPBK_ERROR_COUNT_OBS_1_WIDTH 16U
+#define LPDDR4__PHY_LPBK_ERROR_COUNT_OBS_1__REG DENALI_PHY_303
+#define LPDDR4__PHY_LPBK_ERROR_COUNT_OBS_1__FLD LPDDR4__DENALI_PHY_303__PHY_LPBK_ERROR_COUNT_OBS_1
+
+#define LPDDR4__DENALI_PHY_303__PHY_MASTER_DLY_LOCK_OBS_1_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_303__PHY_MASTER_DLY_LOCK_OBS_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_303__PHY_MASTER_DLY_LOCK_OBS_1_WIDTH 11U
+#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_1__REG DENALI_PHY_303
+#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_1__FLD LPDDR4__DENALI_PHY_303__PHY_MASTER_DLY_LOCK_OBS_1
+
+#define LPDDR4__DENALI_PHY_304_READ_MASK 0xFFFF7F7FU
+#define LPDDR4__DENALI_PHY_304_WRITE_MASK 0xFFFF7F7FU
+#define LPDDR4__DENALI_PHY_304__PHY_RDDQ_SLV_DLY_ENC_OBS_1_MASK 0x0000007FU
+#define LPDDR4__DENALI_PHY_304__PHY_RDDQ_SLV_DLY_ENC_OBS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_304__PHY_RDDQ_SLV_DLY_ENC_OBS_1_WIDTH 7U
+#define LPDDR4__PHY_RDDQ_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_304
+#define LPDDR4__PHY_RDDQ_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_304__PHY_RDDQ_SLV_DLY_ENC_OBS_1
+
+#define LPDDR4__DENALI_PHY_304__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1_MASK 0x00007F00U
+#define LPDDR4__DENALI_PHY_304__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_304__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1_WIDTH 7U
+#define LPDDR4__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_304
+#define LPDDR4__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_304__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1
+
+#define LPDDR4__DENALI_PHY_304__PHY_MEAS_DLY_STEP_VALUE_1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_304__PHY_MEAS_DLY_STEP_VALUE_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_304__PHY_MEAS_DLY_STEP_VALUE_1_WIDTH 8U
+#define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_1__REG DENALI_PHY_304
+#define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_1__FLD LPDDR4__DENALI_PHY_304__PHY_MEAS_DLY_STEP_VALUE_1
+
+#define LPDDR4__DENALI_PHY_304__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_304__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_304__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1_WIDTH 8U
+#define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_304
+#define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_304__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1
+
+#define LPDDR4__DENALI_PHY_305_READ_MASK 0x7F07FFFFU
+#define LPDDR4__DENALI_PHY_305_WRITE_MASK 0x7F07FFFFU
+#define LPDDR4__DENALI_PHY_305__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_305__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_305__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1_WIDTH 8U
+#define LPDDR4__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_305
+#define LPDDR4__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_305__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1
+
+#define LPDDR4__DENALI_PHY_305__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1_MASK 0x0007FF00U
+#define LPDDR4__DENALI_PHY_305__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_305__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1_WIDTH 11U
+#define LPDDR4__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_305
+#define LPDDR4__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_305__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1
+
+#define LPDDR4__DENALI_PHY_305__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1_MASK 0x7F000000U
+#define LPDDR4__DENALI_PHY_305__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_305__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1_WIDTH 7U
+#define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_305
+#define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_305__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1
+
+#define LPDDR4__DENALI_PHY_306_READ_MASK 0x0007FFFFU
+#define LPDDR4__DENALI_PHY_306_WRITE_MASK 0x0007FFFFU
+#define LPDDR4__DENALI_PHY_306__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_306__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_306__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1_WIDTH 8U
+#define LPDDR4__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_306
+#define LPDDR4__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_306__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1
+
+#define LPDDR4__DENALI_PHY_306__PHY_WR_ADDER_SLV_DLY_ENC_OBS_1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_306__PHY_WR_ADDER_SLV_DLY_ENC_OBS_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_306__PHY_WR_ADDER_SLV_DLY_ENC_OBS_1_WIDTH 8U
+#define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_306
+#define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_306__PHY_WR_ADDER_SLV_DLY_ENC_OBS_1
+
+#define LPDDR4__DENALI_PHY_306__PHY_WR_SHIFT_OBS_1_MASK 0x00070000U
+#define LPDDR4__DENALI_PHY_306__PHY_WR_SHIFT_OBS_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_306__PHY_WR_SHIFT_OBS_1_WIDTH 3U
+#define LPDDR4__PHY_WR_SHIFT_OBS_1__REG DENALI_PHY_306
+#define LPDDR4__PHY_WR_SHIFT_OBS_1__FLD LPDDR4__DENALI_PHY_306__PHY_WR_SHIFT_OBS_1
+
+#define LPDDR4__DENALI_PHY_307_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_307_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_307__PHY_WRLVL_HARD0_DELAY_OBS_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_307__PHY_WRLVL_HARD0_DELAY_OBS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_307__PHY_WRLVL_HARD0_DELAY_OBS_1_WIDTH 10U
+#define LPDDR4__PHY_WRLVL_HARD0_DELAY_OBS_1__REG DENALI_PHY_307
+#define LPDDR4__PHY_WRLVL_HARD0_DELAY_OBS_1__FLD LPDDR4__DENALI_PHY_307__PHY_WRLVL_HARD0_DELAY_OBS_1
+
+#define LPDDR4__DENALI_PHY_307__PHY_WRLVL_HARD1_DELAY_OBS_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_307__PHY_WRLVL_HARD1_DELAY_OBS_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_307__PHY_WRLVL_HARD1_DELAY_OBS_1_WIDTH 10U
+#define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_1__REG DENALI_PHY_307
+#define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_1__FLD LPDDR4__DENALI_PHY_307__PHY_WRLVL_HARD1_DELAY_OBS_1
+
+#define LPDDR4__DENALI_PHY_308_READ_MASK 0x001FFFFFU
+#define LPDDR4__DENALI_PHY_308_WRITE_MASK 0x001FFFFFU
+#define LPDDR4__DENALI_PHY_308__PHY_WRLVL_STATUS_OBS_1_MASK 0x001FFFFFU
+#define LPDDR4__DENALI_PHY_308__PHY_WRLVL_STATUS_OBS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_308__PHY_WRLVL_STATUS_OBS_1_WIDTH 21U
+#define LPDDR4__PHY_WRLVL_STATUS_OBS_1__REG DENALI_PHY_308
+#define LPDDR4__PHY_WRLVL_STATUS_OBS_1__FLD LPDDR4__DENALI_PHY_308__PHY_WRLVL_STATUS_OBS_1
+
+#define LPDDR4__DENALI_PHY_309_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_309_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_309__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_309__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_309__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1_WIDTH 10U
+#define LPDDR4__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_309
+#define LPDDR4__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_309__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1
+
+#define LPDDR4__DENALI_PHY_309__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_309__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_309__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1_WIDTH 10U
+#define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_309
+#define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_309__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1
+
+#define LPDDR4__DENALI_PHY_310_READ_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_310_WRITE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_310__PHY_WRLVL_ERROR_OBS_1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_310__PHY_WRLVL_ERROR_OBS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_310__PHY_WRLVL_ERROR_OBS_1_WIDTH 16U
+#define LPDDR4__PHY_WRLVL_ERROR_OBS_1__REG DENALI_PHY_310
+#define LPDDR4__PHY_WRLVL_ERROR_OBS_1__FLD LPDDR4__DENALI_PHY_310__PHY_WRLVL_ERROR_OBS_1
+
+#define LPDDR4__DENALI_PHY_310__PHY_GTLVL_HARD0_DELAY_OBS_1_MASK 0x3FFF0000U
+#define LPDDR4__DENALI_PHY_310__PHY_GTLVL_HARD0_DELAY_OBS_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_310__PHY_GTLVL_HARD0_DELAY_OBS_1_WIDTH 14U
+#define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_1__REG DENALI_PHY_310
+#define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_1__FLD LPDDR4__DENALI_PHY_310__PHY_GTLVL_HARD0_DELAY_OBS_1
+
+#define LPDDR4__DENALI_PHY_311_READ_MASK 0x00003FFFU
+#define LPDDR4__DENALI_PHY_311_WRITE_MASK 0x00003FFFU
+#define LPDDR4__DENALI_PHY_311__PHY_GTLVL_HARD1_DELAY_OBS_1_MASK 0x00003FFFU
+#define LPDDR4__DENALI_PHY_311__PHY_GTLVL_HARD1_DELAY_OBS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_311__PHY_GTLVL_HARD1_DELAY_OBS_1_WIDTH 14U
+#define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_1__REG DENALI_PHY_311
+#define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_1__FLD LPDDR4__DENALI_PHY_311__PHY_GTLVL_HARD1_DELAY_OBS_1
+
+#define LPDDR4__DENALI_PHY_312_READ_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_312_WRITE_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_312__PHY_GTLVL_STATUS_OBS_1_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_312__PHY_GTLVL_STATUS_OBS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_312__PHY_GTLVL_STATUS_OBS_1_WIDTH 18U
+#define LPDDR4__PHY_GTLVL_STATUS_OBS_1__REG DENALI_PHY_312
+#define LPDDR4__PHY_GTLVL_STATUS_OBS_1__FLD LPDDR4__DENALI_PHY_312__PHY_GTLVL_STATUS_OBS_1
+
+#define LPDDR4__DENALI_PHY_313_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_313_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_313__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_313__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_313__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1_WIDTH 10U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1__REG DENALI_PHY_313
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1__FLD LPDDR4__DENALI_PHY_313__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1
+
+#define LPDDR4__DENALI_PHY_313__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_313__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_313__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1_WIDTH 10U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1__REG DENALI_PHY_313
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1__FLD LPDDR4__DENALI_PHY_313__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1
+
+#define LPDDR4__DENALI_PHY_314_READ_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_314_WRITE_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_314__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_314__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_314__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1_WIDTH 2U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1__REG DENALI_PHY_314
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1__FLD LPDDR4__DENALI_PHY_314__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1
+
+#define LPDDR4__DENALI_PHY_315_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_315_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_315__PHY_RDLVL_STATUS_OBS_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_315__PHY_RDLVL_STATUS_OBS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_315__PHY_RDLVL_STATUS_OBS_1_WIDTH 32U
+#define LPDDR4__PHY_RDLVL_STATUS_OBS_1__REG DENALI_PHY_315
+#define LPDDR4__PHY_RDLVL_STATUS_OBS_1__FLD LPDDR4__DENALI_PHY_315__PHY_RDLVL_STATUS_OBS_1
+
+#define LPDDR4__DENALI_PHY_316_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_316_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_316__PHY_WDQLVL_DQDM_LE_DLY_OBS_1_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_316__PHY_WDQLVL_DQDM_LE_DLY_OBS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_316__PHY_WDQLVL_DQDM_LE_DLY_OBS_1_WIDTH 11U
+#define LPDDR4__PHY_WDQLVL_DQDM_LE_DLY_OBS_1__REG DENALI_PHY_316
+#define LPDDR4__PHY_WDQLVL_DQDM_LE_DLY_OBS_1__FLD LPDDR4__DENALI_PHY_316__PHY_WDQLVL_DQDM_LE_DLY_OBS_1
+
+#define LPDDR4__DENALI_PHY_316__PHY_WDQLVL_DQDM_TE_DLY_OBS_1_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_316__PHY_WDQLVL_DQDM_TE_DLY_OBS_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_316__PHY_WDQLVL_DQDM_TE_DLY_OBS_1_WIDTH 11U
+#define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_1__REG DENALI_PHY_316
+#define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_1__FLD LPDDR4__DENALI_PHY_316__PHY_WDQLVL_DQDM_TE_DLY_OBS_1
+
+#define LPDDR4__DENALI_PHY_317_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_317_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_317__PHY_WDQLVL_STATUS_OBS_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_317__PHY_WDQLVL_STATUS_OBS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_317__PHY_WDQLVL_STATUS_OBS_1_WIDTH 32U
+#define LPDDR4__PHY_WDQLVL_STATUS_OBS_1__REG DENALI_PHY_317
+#define LPDDR4__PHY_WDQLVL_STATUS_OBS_1__FLD LPDDR4__DENALI_PHY_317__PHY_WDQLVL_STATUS_OBS_1
+
+#define LPDDR4__DENALI_PHY_318_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_318_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_318__PHY_WDQLVL_PERIODIC_OBS_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_318__PHY_WDQLVL_PERIODIC_OBS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_318__PHY_WDQLVL_PERIODIC_OBS_1_WIDTH 32U
+#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_1__REG DENALI_PHY_318
+#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_1__FLD LPDDR4__DENALI_PHY_318__PHY_WDQLVL_PERIODIC_OBS_1
+
+#define LPDDR4__DENALI_PHY_319_READ_MASK 0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_319_WRITE_MASK 0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_319__PHY_DDL_MODE_1_MASK 0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_319__PHY_DDL_MODE_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_319__PHY_DDL_MODE_1_WIDTH 31U
+#define LPDDR4__PHY_DDL_MODE_1__REG DENALI_PHY_319
+#define LPDDR4__PHY_DDL_MODE_1__FLD LPDDR4__DENALI_PHY_319__PHY_DDL_MODE_1
+
+#define LPDDR4__DENALI_PHY_320_READ_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_320_WRITE_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_320__PHY_DDL_MASK_1_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_320__PHY_DDL_MASK_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_320__PHY_DDL_MASK_1_WIDTH 6U
+#define LPDDR4__PHY_DDL_MASK_1__REG DENALI_PHY_320
+#define LPDDR4__PHY_DDL_MASK_1__FLD LPDDR4__DENALI_PHY_320__PHY_DDL_MASK_1
+
+#define LPDDR4__DENALI_PHY_321_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_321_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_321__PHY_DDL_TEST_OBS_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_321__PHY_DDL_TEST_OBS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_321__PHY_DDL_TEST_OBS_1_WIDTH 32U
+#define LPDDR4__PHY_DDL_TEST_OBS_1__REG DENALI_PHY_321
+#define LPDDR4__PHY_DDL_TEST_OBS_1__FLD LPDDR4__DENALI_PHY_321__PHY_DDL_TEST_OBS_1
+
+#define LPDDR4__DENALI_PHY_322_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_322_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_322__PHY_DDL_TEST_MSTR_DLY_OBS_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_322__PHY_DDL_TEST_MSTR_DLY_OBS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_322__PHY_DDL_TEST_MSTR_DLY_OBS_1_WIDTH 32U
+#define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_1__REG DENALI_PHY_322
+#define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_1__FLD LPDDR4__DENALI_PHY_322__PHY_DDL_TEST_MSTR_DLY_OBS_1
+
+#define LPDDR4__DENALI_PHY_323_READ_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_323_WRITE_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_323__PHY_DDL_TRACK_UPD_THRESHOLD_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_323__PHY_DDL_TRACK_UPD_THRESHOLD_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_323__PHY_DDL_TRACK_UPD_THRESHOLD_1_WIDTH 8U
+#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_1__REG DENALI_PHY_323
+#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_1__FLD LPDDR4__DENALI_PHY_323__PHY_DDL_TRACK_UPD_THRESHOLD_1
+
+#define LPDDR4__DENALI_PHY_323__PHY_LP4_WDQS_OE_EXTEND_1_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_323__PHY_LP4_WDQS_OE_EXTEND_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_323__PHY_LP4_WDQS_OE_EXTEND_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_323__PHY_LP4_WDQS_OE_EXTEND_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_323__PHY_LP4_WDQS_OE_EXTEND_1_WOSET 0U
+#define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_1__REG DENALI_PHY_323
+#define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_1__FLD LPDDR4__DENALI_PHY_323__PHY_LP4_WDQS_OE_EXTEND_1
+
+#define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ0_1_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ0_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ0_1_WIDTH 9U
+#define LPDDR4__PHY_RX_CAL_DQ0_1__REG DENALI_PHY_323
+#define LPDDR4__PHY_RX_CAL_DQ0_1__FLD LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ0_1
+
+#define LPDDR4__DENALI_PHY_324_READ_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_324_WRITE_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ1_1_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ1_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ1_1_WIDTH 9U
+#define LPDDR4__PHY_RX_CAL_DQ1_1__REG DENALI_PHY_324
+#define LPDDR4__PHY_RX_CAL_DQ1_1__FLD LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ1_1
+
+#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ2_1_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ2_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ2_1_WIDTH 9U
+#define LPDDR4__PHY_RX_CAL_DQ2_1__REG DENALI_PHY_324
+#define LPDDR4__PHY_RX_CAL_DQ2_1__FLD LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ2_1
+
+#define LPDDR4__DENALI_PHY_325_READ_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_325_WRITE_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ3_1_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ3_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ3_1_WIDTH 9U
+#define LPDDR4__PHY_RX_CAL_DQ3_1__REG DENALI_PHY_325
+#define LPDDR4__PHY_RX_CAL_DQ3_1__FLD LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ3_1
+
+#define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ4_1_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ4_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ4_1_WIDTH 9U
+#define LPDDR4__PHY_RX_CAL_DQ4_1__REG DENALI_PHY_325
+#define LPDDR4__PHY_RX_CAL_DQ4_1__FLD LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ4_1
+
+#define LPDDR4__DENALI_PHY_326_READ_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_326_WRITE_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ5_1_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ5_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ5_1_WIDTH 9U
+#define LPDDR4__PHY_RX_CAL_DQ5_1__REG DENALI_PHY_326
+#define LPDDR4__PHY_RX_CAL_DQ5_1__FLD LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ5_1
+
+#define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ6_1_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ6_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ6_1_WIDTH 9U
+#define LPDDR4__PHY_RX_CAL_DQ6_1__REG DENALI_PHY_326
+#define LPDDR4__PHY_RX_CAL_DQ6_1__FLD LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ6_1
+
+#define LPDDR4__DENALI_PHY_327_READ_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_327_WRITE_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_327__PHY_RX_CAL_DQ7_1_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_327__PHY_RX_CAL_DQ7_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_327__PHY_RX_CAL_DQ7_1_WIDTH 9U
+#define LPDDR4__PHY_RX_CAL_DQ7_1__REG DENALI_PHY_327
+#define LPDDR4__PHY_RX_CAL_DQ7_1__FLD LPDDR4__DENALI_PHY_327__PHY_RX_CAL_DQ7_1
+
+#define LPDDR4__DENALI_PHY_328_READ_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_328_WRITE_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_328__PHY_RX_CAL_DM_1_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_328__PHY_RX_CAL_DM_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_328__PHY_RX_CAL_DM_1_WIDTH 18U
+#define LPDDR4__PHY_RX_CAL_DM_1__REG DENALI_PHY_328
+#define LPDDR4__PHY_RX_CAL_DM_1__FLD LPDDR4__DENALI_PHY_328__PHY_RX_CAL_DM_1
+
+#define LPDDR4__DENALI_PHY_329_READ_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_329_WRITE_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_329__PHY_RX_CAL_DQS_1_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_329__PHY_RX_CAL_DQS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_329__PHY_RX_CAL_DQS_1_WIDTH 9U
+#define LPDDR4__PHY_RX_CAL_DQS_1__REG DENALI_PHY_329
+#define LPDDR4__PHY_RX_CAL_DQS_1__FLD LPDDR4__DENALI_PHY_329__PHY_RX_CAL_DQS_1
+
+#define LPDDR4__DENALI_PHY_329__PHY_RX_CAL_FDBK_1_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_329__PHY_RX_CAL_FDBK_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_329__PHY_RX_CAL_FDBK_1_WIDTH 9U
+#define LPDDR4__PHY_RX_CAL_FDBK_1__REG DENALI_PHY_329
+#define LPDDR4__PHY_RX_CAL_FDBK_1__FLD LPDDR4__DENALI_PHY_329__PHY_RX_CAL_FDBK_1
+
+#define LPDDR4__DENALI_PHY_330_READ_MASK 0xFF1F07FFU
+#define LPDDR4__DENALI_PHY_330_WRITE_MASK 0xFF1F07FFU
+#define LPDDR4__DENALI_PHY_330__PHY_PAD_RX_BIAS_EN_1_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_330__PHY_PAD_RX_BIAS_EN_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_330__PHY_PAD_RX_BIAS_EN_1_WIDTH 11U
+#define LPDDR4__PHY_PAD_RX_BIAS_EN_1__REG DENALI_PHY_330
+#define LPDDR4__PHY_PAD_RX_BIAS_EN_1__FLD LPDDR4__DENALI_PHY_330__PHY_PAD_RX_BIAS_EN_1
+
+#define LPDDR4__DENALI_PHY_330__PHY_STATIC_TOG_DISABLE_1_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_330__PHY_STATIC_TOG_DISABLE_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_330__PHY_STATIC_TOG_DISABLE_1_WIDTH 5U
+#define LPDDR4__PHY_STATIC_TOG_DISABLE_1__REG DENALI_PHY_330
+#define LPDDR4__PHY_STATIC_TOG_DISABLE_1__FLD LPDDR4__DENALI_PHY_330__PHY_STATIC_TOG_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_330__PHY_DATA_DC_CAL_SAMPLE_WAIT_1_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_330__PHY_DATA_DC_CAL_SAMPLE_WAIT_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_330__PHY_DATA_DC_CAL_SAMPLE_WAIT_1_WIDTH 8U
+#define LPDDR4__PHY_DATA_DC_CAL_SAMPLE_WAIT_1__REG DENALI_PHY_330
+#define LPDDR4__PHY_DATA_DC_CAL_SAMPLE_WAIT_1__FLD LPDDR4__DENALI_PHY_330__PHY_DATA_DC_CAL_SAMPLE_WAIT_1
+
+#define LPDDR4__DENALI_PHY_331_READ_MASK 0xFF3F03FFU
+#define LPDDR4__DENALI_PHY_331_WRITE_MASK 0xFF3F03FFU
+#define LPDDR4__DENALI_PHY_331__PHY_DATA_DC_CAL_TIMEOUT_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_331__PHY_DATA_DC_CAL_TIMEOUT_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_331__PHY_DATA_DC_CAL_TIMEOUT_1_WIDTH 8U
+#define LPDDR4__PHY_DATA_DC_CAL_TIMEOUT_1__REG DENALI_PHY_331
+#define LPDDR4__PHY_DATA_DC_CAL_TIMEOUT_1__FLD LPDDR4__DENALI_PHY_331__PHY_DATA_DC_CAL_TIMEOUT_1
+
+#define LPDDR4__DENALI_PHY_331__PHY_DATA_DC_WEIGHT_1_MASK 0x00000300U
+#define LPDDR4__DENALI_PHY_331__PHY_DATA_DC_WEIGHT_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_331__PHY_DATA_DC_WEIGHT_1_WIDTH 2U
+#define LPDDR4__PHY_DATA_DC_WEIGHT_1__REG DENALI_PHY_331
+#define LPDDR4__PHY_DATA_DC_WEIGHT_1__FLD LPDDR4__DENALI_PHY_331__PHY_DATA_DC_WEIGHT_1
+
+#define LPDDR4__DENALI_PHY_331__PHY_DATA_DC_ADJUST_START_1_MASK 0x003F0000U
+#define LPDDR4__DENALI_PHY_331__PHY_DATA_DC_ADJUST_START_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_331__PHY_DATA_DC_ADJUST_START_1_WIDTH 6U
+#define LPDDR4__PHY_DATA_DC_ADJUST_START_1__REG DENALI_PHY_331
+#define LPDDR4__PHY_DATA_DC_ADJUST_START_1__FLD LPDDR4__DENALI_PHY_331__PHY_DATA_DC_ADJUST_START_1
+
+#define LPDDR4__DENALI_PHY_331__PHY_DATA_DC_ADJUST_SAMPLE_CNT_1_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_331__PHY_DATA_DC_ADJUST_SAMPLE_CNT_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_331__PHY_DATA_DC_ADJUST_SAMPLE_CNT_1_WIDTH 8U
+#define LPDDR4__PHY_DATA_DC_ADJUST_SAMPLE_CNT_1__REG DENALI_PHY_331
+#define LPDDR4__PHY_DATA_DC_ADJUST_SAMPLE_CNT_1__FLD LPDDR4__DENALI_PHY_331__PHY_DATA_DC_ADJUST_SAMPLE_CNT_1
+
+#define LPDDR4__DENALI_PHY_332_READ_MASK 0x010101FFU
+#define LPDDR4__DENALI_PHY_332_WRITE_MASK 0x010101FFU
+#define LPDDR4__DENALI_PHY_332__PHY_DATA_DC_ADJUST_THRSHLD_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_332__PHY_DATA_DC_ADJUST_THRSHLD_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_332__PHY_DATA_DC_ADJUST_THRSHLD_1_WIDTH 8U
+#define LPDDR4__PHY_DATA_DC_ADJUST_THRSHLD_1__REG DENALI_PHY_332
+#define LPDDR4__PHY_DATA_DC_ADJUST_THRSHLD_1__FLD LPDDR4__DENALI_PHY_332__PHY_DATA_DC_ADJUST_THRSHLD_1
+
+#define LPDDR4__DENALI_PHY_332__PHY_DATA_DC_ADJUST_DIRECT_1_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_332__PHY_DATA_DC_ADJUST_DIRECT_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_332__PHY_DATA_DC_ADJUST_DIRECT_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_332__PHY_DATA_DC_ADJUST_DIRECT_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_332__PHY_DATA_DC_ADJUST_DIRECT_1_WOSET 0U
+#define LPDDR4__PHY_DATA_DC_ADJUST_DIRECT_1__REG DENALI_PHY_332
+#define LPDDR4__PHY_DATA_DC_ADJUST_DIRECT_1__FLD LPDDR4__DENALI_PHY_332__PHY_DATA_DC_ADJUST_DIRECT_1
+
+#define LPDDR4__DENALI_PHY_332__PHY_DATA_DC_CAL_POLARITY_1_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_332__PHY_DATA_DC_CAL_POLARITY_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_332__PHY_DATA_DC_CAL_POLARITY_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_332__PHY_DATA_DC_CAL_POLARITY_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_332__PHY_DATA_DC_CAL_POLARITY_1_WOSET 0U
+#define LPDDR4__PHY_DATA_DC_CAL_POLARITY_1__REG DENALI_PHY_332
+#define LPDDR4__PHY_DATA_DC_CAL_POLARITY_1__FLD LPDDR4__DENALI_PHY_332__PHY_DATA_DC_CAL_POLARITY_1
+
+#define LPDDR4__DENALI_PHY_332__PHY_DATA_DC_CAL_START_1_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_332__PHY_DATA_DC_CAL_START_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_332__PHY_DATA_DC_CAL_START_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_332__PHY_DATA_DC_CAL_START_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_332__PHY_DATA_DC_CAL_START_1_WOSET 0U
+#define LPDDR4__PHY_DATA_DC_CAL_START_1__REG DENALI_PHY_332
+#define LPDDR4__PHY_DATA_DC_CAL_START_1__FLD LPDDR4__DENALI_PHY_332__PHY_DATA_DC_CAL_START_1
+
+#define LPDDR4__DENALI_PHY_333_READ_MASK 0x01010703U
+#define LPDDR4__DENALI_PHY_333_WRITE_MASK 0x01010703U
+#define LPDDR4__DENALI_PHY_333__PHY_DATA_DC_SW_RANK_1_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_333__PHY_DATA_DC_SW_RANK_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_333__PHY_DATA_DC_SW_RANK_1_WIDTH 2U
+#define LPDDR4__PHY_DATA_DC_SW_RANK_1__REG DENALI_PHY_333
+#define LPDDR4__PHY_DATA_DC_SW_RANK_1__FLD LPDDR4__DENALI_PHY_333__PHY_DATA_DC_SW_RANK_1
+
+#define LPDDR4__DENALI_PHY_333__PHY_FDBK_PWR_CTRL_1_MASK 0x00000700U
+#define LPDDR4__DENALI_PHY_333__PHY_FDBK_PWR_CTRL_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_333__PHY_FDBK_PWR_CTRL_1_WIDTH 3U
+#define LPDDR4__PHY_FDBK_PWR_CTRL_1__REG DENALI_PHY_333
+#define LPDDR4__PHY_FDBK_PWR_CTRL_1__FLD LPDDR4__DENALI_PHY_333__PHY_FDBK_PWR_CTRL_1
+
+#define LPDDR4__DENALI_PHY_333__PHY_SLV_DLY_CTRL_GATE_DISABLE_1_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_333__PHY_SLV_DLY_CTRL_GATE_DISABLE_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_333__PHY_SLV_DLY_CTRL_GATE_DISABLE_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_333__PHY_SLV_DLY_CTRL_GATE_DISABLE_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_333__PHY_SLV_DLY_CTRL_GATE_DISABLE_1_WOSET 0U
+#define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_1__REG DENALI_PHY_333
+#define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_1__FLD LPDDR4__DENALI_PHY_333__PHY_SLV_DLY_CTRL_GATE_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_333__PHY_RDPATH_GATE_DISABLE_1_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_333__PHY_RDPATH_GATE_DISABLE_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_333__PHY_RDPATH_GATE_DISABLE_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_333__PHY_RDPATH_GATE_DISABLE_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_333__PHY_RDPATH_GATE_DISABLE_1_WOSET 0U
+#define LPDDR4__PHY_RDPATH_GATE_DISABLE_1__REG DENALI_PHY_333
+#define LPDDR4__PHY_RDPATH_GATE_DISABLE_1__FLD LPDDR4__DENALI_PHY_333__PHY_RDPATH_GATE_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_334_READ_MASK 0x00000101U
+#define LPDDR4__DENALI_PHY_334_WRITE_MASK 0x00000101U
+#define LPDDR4__DENALI_PHY_334__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_334__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_334__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_334__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_334__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1_WOSET 0U
+#define LPDDR4__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1__REG DENALI_PHY_334
+#define LPDDR4__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1__FLD LPDDR4__DENALI_PHY_334__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_334__PHY_SLICE_PWR_RDC_DISABLE_1_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_334__PHY_SLICE_PWR_RDC_DISABLE_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_334__PHY_SLICE_PWR_RDC_DISABLE_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_334__PHY_SLICE_PWR_RDC_DISABLE_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_334__PHY_SLICE_PWR_RDC_DISABLE_1_WOSET 0U
+#define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_1__REG DENALI_PHY_334
+#define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_1__FLD LPDDR4__DENALI_PHY_334__PHY_SLICE_PWR_RDC_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_335_READ_MASK 0x07FFFF07U
+#define LPDDR4__DENALI_PHY_335_WRITE_MASK 0x07FFFF07U
+#define LPDDR4__DENALI_PHY_335__PHY_DQ_TSEL_ENABLE_1_MASK 0x00000007U
+#define LPDDR4__DENALI_PHY_335__PHY_DQ_TSEL_ENABLE_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_335__PHY_DQ_TSEL_ENABLE_1_WIDTH 3U
+#define LPDDR4__PHY_DQ_TSEL_ENABLE_1__REG DENALI_PHY_335
+#define LPDDR4__PHY_DQ_TSEL_ENABLE_1__FLD LPDDR4__DENALI_PHY_335__PHY_DQ_TSEL_ENABLE_1
+
+#define LPDDR4__DENALI_PHY_335__PHY_DQ_TSEL_SELECT_1_MASK 0x00FFFF00U
+#define LPDDR4__DENALI_PHY_335__PHY_DQ_TSEL_SELECT_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_335__PHY_DQ_TSEL_SELECT_1_WIDTH 16U
+#define LPDDR4__PHY_DQ_TSEL_SELECT_1__REG DENALI_PHY_335
+#define LPDDR4__PHY_DQ_TSEL_SELECT_1__FLD LPDDR4__DENALI_PHY_335__PHY_DQ_TSEL_SELECT_1
+
+#define LPDDR4__DENALI_PHY_335__PHY_DQS_TSEL_ENABLE_1_MASK 0x07000000U
+#define LPDDR4__DENALI_PHY_335__PHY_DQS_TSEL_ENABLE_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_335__PHY_DQS_TSEL_ENABLE_1_WIDTH 3U
+#define LPDDR4__PHY_DQS_TSEL_ENABLE_1__REG DENALI_PHY_335
+#define LPDDR4__PHY_DQS_TSEL_ENABLE_1__FLD LPDDR4__DENALI_PHY_335__PHY_DQS_TSEL_ENABLE_1
+
+#define LPDDR4__DENALI_PHY_336_READ_MASK 0x7F03FFFFU
+#define LPDDR4__DENALI_PHY_336_WRITE_MASK 0x7F03FFFFU
+#define LPDDR4__DENALI_PHY_336__PHY_DQS_TSEL_SELECT_1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_336__PHY_DQS_TSEL_SELECT_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_336__PHY_DQS_TSEL_SELECT_1_WIDTH 16U
+#define LPDDR4__PHY_DQS_TSEL_SELECT_1__REG DENALI_PHY_336
+#define LPDDR4__PHY_DQS_TSEL_SELECT_1__FLD LPDDR4__DENALI_PHY_336__PHY_DQS_TSEL_SELECT_1
+
+#define LPDDR4__DENALI_PHY_336__PHY_TWO_CYC_PREAMBLE_1_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_336__PHY_TWO_CYC_PREAMBLE_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_336__PHY_TWO_CYC_PREAMBLE_1_WIDTH 2U
+#define LPDDR4__PHY_TWO_CYC_PREAMBLE_1__REG DENALI_PHY_336
+#define LPDDR4__PHY_TWO_CYC_PREAMBLE_1__FLD LPDDR4__DENALI_PHY_336__PHY_TWO_CYC_PREAMBLE_1
+
+#define LPDDR4__DENALI_PHY_336__PHY_VREF_INITIAL_START_POINT_1_MASK 0x7F000000U
+#define LPDDR4__DENALI_PHY_336__PHY_VREF_INITIAL_START_POINT_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_336__PHY_VREF_INITIAL_START_POINT_1_WIDTH 7U
+#define LPDDR4__PHY_VREF_INITIAL_START_POINT_1__REG DENALI_PHY_336
+#define LPDDR4__PHY_VREF_INITIAL_START_POINT_1__FLD LPDDR4__DENALI_PHY_336__PHY_VREF_INITIAL_START_POINT_1
+
+#define LPDDR4__DENALI_PHY_337_READ_MASK 0xFF01037FU
+#define LPDDR4__DENALI_PHY_337_WRITE_MASK 0xFF01037FU
+#define LPDDR4__DENALI_PHY_337__PHY_VREF_INITIAL_STOP_POINT_1_MASK 0x0000007FU
+#define LPDDR4__DENALI_PHY_337__PHY_VREF_INITIAL_STOP_POINT_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_337__PHY_VREF_INITIAL_STOP_POINT_1_WIDTH 7U
+#define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_1__REG DENALI_PHY_337
+#define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_1__FLD LPDDR4__DENALI_PHY_337__PHY_VREF_INITIAL_STOP_POINT_1
+
+#define LPDDR4__DENALI_PHY_337__PHY_VREF_TRAINING_CTRL_1_MASK 0x00000300U
+#define LPDDR4__DENALI_PHY_337__PHY_VREF_TRAINING_CTRL_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_337__PHY_VREF_TRAINING_CTRL_1_WIDTH 2U
+#define LPDDR4__PHY_VREF_TRAINING_CTRL_1__REG DENALI_PHY_337
+#define LPDDR4__PHY_VREF_TRAINING_CTRL_1__FLD LPDDR4__DENALI_PHY_337__PHY_VREF_TRAINING_CTRL_1
+
+#define LPDDR4__DENALI_PHY_337__PHY_NTP_TRAIN_EN_1_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_337__PHY_NTP_TRAIN_EN_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_337__PHY_NTP_TRAIN_EN_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_337__PHY_NTP_TRAIN_EN_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_337__PHY_NTP_TRAIN_EN_1_WOSET 0U
+#define LPDDR4__PHY_NTP_TRAIN_EN_1__REG DENALI_PHY_337
+#define LPDDR4__PHY_NTP_TRAIN_EN_1__FLD LPDDR4__DENALI_PHY_337__PHY_NTP_TRAIN_EN_1
+
+#define LPDDR4__DENALI_PHY_337__PHY_NTP_WDQ_STEP_SIZE_1_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_337__PHY_NTP_WDQ_STEP_SIZE_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_337__PHY_NTP_WDQ_STEP_SIZE_1_WIDTH 8U
+#define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_1__REG DENALI_PHY_337
+#define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_1__FLD LPDDR4__DENALI_PHY_337__PHY_NTP_WDQ_STEP_SIZE_1
+
+#define LPDDR4__DENALI_PHY_338_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_338_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_338__PHY_NTP_WDQ_START_1_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_338__PHY_NTP_WDQ_START_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_338__PHY_NTP_WDQ_START_1_WIDTH 11U
+#define LPDDR4__PHY_NTP_WDQ_START_1__REG DENALI_PHY_338
+#define LPDDR4__PHY_NTP_WDQ_START_1__FLD LPDDR4__DENALI_PHY_338__PHY_NTP_WDQ_START_1
+
+#define LPDDR4__DENALI_PHY_338__PHY_NTP_WDQ_STOP_1_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_338__PHY_NTP_WDQ_STOP_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_338__PHY_NTP_WDQ_STOP_1_WIDTH 11U
+#define LPDDR4__PHY_NTP_WDQ_STOP_1__REG DENALI_PHY_338
+#define LPDDR4__PHY_NTP_WDQ_STOP_1__FLD LPDDR4__DENALI_PHY_338__PHY_NTP_WDQ_STOP_1
+
+#define LPDDR4__DENALI_PHY_339_READ_MASK 0x0103FFFFU
+#define LPDDR4__DENALI_PHY_339_WRITE_MASK 0x0103FFFFU
+#define LPDDR4__DENALI_PHY_339__PHY_NTP_WDQ_BIT_EN_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_339__PHY_NTP_WDQ_BIT_EN_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_339__PHY_NTP_WDQ_BIT_EN_1_WIDTH 8U
+#define LPDDR4__PHY_NTP_WDQ_BIT_EN_1__REG DENALI_PHY_339
+#define LPDDR4__PHY_NTP_WDQ_BIT_EN_1__FLD LPDDR4__DENALI_PHY_339__PHY_NTP_WDQ_BIT_EN_1
+
+#define LPDDR4__DENALI_PHY_339__PHY_WDQLVL_DVW_MIN_1_MASK 0x0003FF00U
+#define LPDDR4__DENALI_PHY_339__PHY_WDQLVL_DVW_MIN_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_339__PHY_WDQLVL_DVW_MIN_1_WIDTH 10U
+#define LPDDR4__PHY_WDQLVL_DVW_MIN_1__REG DENALI_PHY_339
+#define LPDDR4__PHY_WDQLVL_DVW_MIN_1__FLD LPDDR4__DENALI_PHY_339__PHY_WDQLVL_DVW_MIN_1
+
+#define LPDDR4__DENALI_PHY_339__PHY_SW_WDQLVL_DVW_MIN_EN_1_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_339__PHY_SW_WDQLVL_DVW_MIN_EN_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_339__PHY_SW_WDQLVL_DVW_MIN_EN_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_339__PHY_SW_WDQLVL_DVW_MIN_EN_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_339__PHY_SW_WDQLVL_DVW_MIN_EN_1_WOSET 0U
+#define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_1__REG DENALI_PHY_339
+#define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_1__FLD LPDDR4__DENALI_PHY_339__PHY_SW_WDQLVL_DVW_MIN_EN_1
+
+#define LPDDR4__DENALI_PHY_340_READ_MASK 0x1F1F0F3FU
+#define LPDDR4__DENALI_PHY_340_WRITE_MASK 0x1F1F0F3FU
+#define LPDDR4__DENALI_PHY_340__PHY_WDQLVL_PER_START_OFFSET_1_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_340__PHY_WDQLVL_PER_START_OFFSET_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_340__PHY_WDQLVL_PER_START_OFFSET_1_WIDTH 6U
+#define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_1__REG DENALI_PHY_340
+#define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_1__FLD LPDDR4__DENALI_PHY_340__PHY_WDQLVL_PER_START_OFFSET_1
+
+#define LPDDR4__DENALI_PHY_340__PHY_FAST_LVL_EN_1_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_340__PHY_FAST_LVL_EN_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_340__PHY_FAST_LVL_EN_1_WIDTH 4U
+#define LPDDR4__PHY_FAST_LVL_EN_1__REG DENALI_PHY_340
+#define LPDDR4__PHY_FAST_LVL_EN_1__FLD LPDDR4__DENALI_PHY_340__PHY_FAST_LVL_EN_1
+
+#define LPDDR4__DENALI_PHY_340__PHY_PAD_TX_DCD_1_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_340__PHY_PAD_TX_DCD_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_340__PHY_PAD_TX_DCD_1_WIDTH 5U
+#define LPDDR4__PHY_PAD_TX_DCD_1__REG DENALI_PHY_340
+#define LPDDR4__PHY_PAD_TX_DCD_1__FLD LPDDR4__DENALI_PHY_340__PHY_PAD_TX_DCD_1
+
+#define LPDDR4__DENALI_PHY_340__PHY_PAD_RX_DCD_0_1_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_340__PHY_PAD_RX_DCD_0_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_340__PHY_PAD_RX_DCD_0_1_WIDTH 5U
+#define LPDDR4__PHY_PAD_RX_DCD_0_1__REG DENALI_PHY_340
+#define LPDDR4__PHY_PAD_RX_DCD_0_1__FLD LPDDR4__DENALI_PHY_340__PHY_PAD_RX_DCD_0_1
+
+#define LPDDR4__DENALI_PHY_341_READ_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_341_WRITE_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_341__PHY_PAD_RX_DCD_1_1_MASK 0x0000001FU
+#define LPDDR4__DENALI_PHY_341__PHY_PAD_RX_DCD_1_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_341__PHY_PAD_RX_DCD_1_1_WIDTH 5U
+#define LPDDR4__PHY_PAD_RX_DCD_1_1__REG DENALI_PHY_341
+#define LPDDR4__PHY_PAD_RX_DCD_1_1__FLD LPDDR4__DENALI_PHY_341__PHY_PAD_RX_DCD_1_1
+
+#define LPDDR4__DENALI_PHY_341__PHY_PAD_RX_DCD_2_1_MASK 0x00001F00U
+#define LPDDR4__DENALI_PHY_341__PHY_PAD_RX_DCD_2_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_341__PHY_PAD_RX_DCD_2_1_WIDTH 5U
+#define LPDDR4__PHY_PAD_RX_DCD_2_1__REG DENALI_PHY_341
+#define LPDDR4__PHY_PAD_RX_DCD_2_1__FLD LPDDR4__DENALI_PHY_341__PHY_PAD_RX_DCD_2_1
+
+#define LPDDR4__DENALI_PHY_341__PHY_PAD_RX_DCD_3_1_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_341__PHY_PAD_RX_DCD_3_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_341__PHY_PAD_RX_DCD_3_1_WIDTH 5U
+#define LPDDR4__PHY_PAD_RX_DCD_3_1__REG DENALI_PHY_341
+#define LPDDR4__PHY_PAD_RX_DCD_3_1__FLD LPDDR4__DENALI_PHY_341__PHY_PAD_RX_DCD_3_1
+
+#define LPDDR4__DENALI_PHY_341__PHY_PAD_RX_DCD_4_1_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_341__PHY_PAD_RX_DCD_4_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_341__PHY_PAD_RX_DCD_4_1_WIDTH 5U
+#define LPDDR4__PHY_PAD_RX_DCD_4_1__REG DENALI_PHY_341
+#define LPDDR4__PHY_PAD_RX_DCD_4_1__FLD LPDDR4__DENALI_PHY_341__PHY_PAD_RX_DCD_4_1
+
+#define LPDDR4__DENALI_PHY_342_READ_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_342_WRITE_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_342__PHY_PAD_RX_DCD_5_1_MASK 0x0000001FU
+#define LPDDR4__DENALI_PHY_342__PHY_PAD_RX_DCD_5_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_342__PHY_PAD_RX_DCD_5_1_WIDTH 5U
+#define LPDDR4__PHY_PAD_RX_DCD_5_1__REG DENALI_PHY_342
+#define LPDDR4__PHY_PAD_RX_DCD_5_1__FLD LPDDR4__DENALI_PHY_342__PHY_PAD_RX_DCD_5_1
+
+#define LPDDR4__DENALI_PHY_342__PHY_PAD_RX_DCD_6_1_MASK 0x00001F00U
+#define LPDDR4__DENALI_PHY_342__PHY_PAD_RX_DCD_6_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_342__PHY_PAD_RX_DCD_6_1_WIDTH 5U
+#define LPDDR4__PHY_PAD_RX_DCD_6_1__REG DENALI_PHY_342
+#define LPDDR4__PHY_PAD_RX_DCD_6_1__FLD LPDDR4__DENALI_PHY_342__PHY_PAD_RX_DCD_6_1
+
+#define LPDDR4__DENALI_PHY_342__PHY_PAD_RX_DCD_7_1_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_342__PHY_PAD_RX_DCD_7_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_342__PHY_PAD_RX_DCD_7_1_WIDTH 5U
+#define LPDDR4__PHY_PAD_RX_DCD_7_1__REG DENALI_PHY_342
+#define LPDDR4__PHY_PAD_RX_DCD_7_1__FLD LPDDR4__DENALI_PHY_342__PHY_PAD_RX_DCD_7_1
+
+#define LPDDR4__DENALI_PHY_342__PHY_PAD_DM_RX_DCD_1_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_342__PHY_PAD_DM_RX_DCD_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_342__PHY_PAD_DM_RX_DCD_1_WIDTH 5U
+#define LPDDR4__PHY_PAD_DM_RX_DCD_1__REG DENALI_PHY_342
+#define LPDDR4__PHY_PAD_DM_RX_DCD_1__FLD LPDDR4__DENALI_PHY_342__PHY_PAD_DM_RX_DCD_1
+
+#define LPDDR4__DENALI_PHY_343_READ_MASK 0x007F1F1FU
+#define LPDDR4__DENALI_PHY_343_WRITE_MASK 0x007F1F1FU
+#define LPDDR4__DENALI_PHY_343__PHY_PAD_DQS_RX_DCD_1_MASK 0x0000001FU
+#define LPDDR4__DENALI_PHY_343__PHY_PAD_DQS_RX_DCD_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_343__PHY_PAD_DQS_RX_DCD_1_WIDTH 5U
+#define LPDDR4__PHY_PAD_DQS_RX_DCD_1__REG DENALI_PHY_343
+#define LPDDR4__PHY_PAD_DQS_RX_DCD_1__FLD LPDDR4__DENALI_PHY_343__PHY_PAD_DQS_RX_DCD_1
+
+#define LPDDR4__DENALI_PHY_343__PHY_PAD_FDBK_RX_DCD_1_MASK 0x00001F00U
+#define LPDDR4__DENALI_PHY_343__PHY_PAD_FDBK_RX_DCD_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_343__PHY_PAD_FDBK_RX_DCD_1_WIDTH 5U
+#define LPDDR4__PHY_PAD_FDBK_RX_DCD_1__REG DENALI_PHY_343
+#define LPDDR4__PHY_PAD_FDBK_RX_DCD_1__FLD LPDDR4__DENALI_PHY_343__PHY_PAD_FDBK_RX_DCD_1
+
+#define LPDDR4__DENALI_PHY_343__PHY_PAD_DSLICE_IO_CFG_1_MASK 0x007F0000U
+#define LPDDR4__DENALI_PHY_343__PHY_PAD_DSLICE_IO_CFG_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_343__PHY_PAD_DSLICE_IO_CFG_1_WIDTH 7U
+#define LPDDR4__PHY_PAD_DSLICE_IO_CFG_1__REG DENALI_PHY_343
+#define LPDDR4__PHY_PAD_DSLICE_IO_CFG_1__FLD LPDDR4__DENALI_PHY_343__PHY_PAD_DSLICE_IO_CFG_1
+
+#define LPDDR4__DENALI_PHY_344_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_344_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_344__PHY_RDDQ0_SLAVE_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_344__PHY_RDDQ0_SLAVE_DELAY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_344__PHY_RDDQ0_SLAVE_DELAY_1_WIDTH 10U
+#define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_1__REG DENALI_PHY_344
+#define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_344__PHY_RDDQ0_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_344__PHY_RDDQ1_SLAVE_DELAY_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_344__PHY_RDDQ1_SLAVE_DELAY_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_344__PHY_RDDQ1_SLAVE_DELAY_1_WIDTH 10U
+#define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_1__REG DENALI_PHY_344
+#define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_344__PHY_RDDQ1_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_345_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_345_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_345__PHY_RDDQ2_SLAVE_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_345__PHY_RDDQ2_SLAVE_DELAY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_345__PHY_RDDQ2_SLAVE_DELAY_1_WIDTH 10U
+#define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_1__REG DENALI_PHY_345
+#define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_345__PHY_RDDQ2_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_345__PHY_RDDQ3_SLAVE_DELAY_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_345__PHY_RDDQ3_SLAVE_DELAY_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_345__PHY_RDDQ3_SLAVE_DELAY_1_WIDTH 10U
+#define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_1__REG DENALI_PHY_345
+#define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_345__PHY_RDDQ3_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_346_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_346_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_346__PHY_RDDQ4_SLAVE_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_346__PHY_RDDQ4_SLAVE_DELAY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_346__PHY_RDDQ4_SLAVE_DELAY_1_WIDTH 10U
+#define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_1__REG DENALI_PHY_346
+#define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_346__PHY_RDDQ4_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_346__PHY_RDDQ5_SLAVE_DELAY_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_346__PHY_RDDQ5_SLAVE_DELAY_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_346__PHY_RDDQ5_SLAVE_DELAY_1_WIDTH 10U
+#define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_1__REG DENALI_PHY_346
+#define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_346__PHY_RDDQ5_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_347_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_347_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_347__PHY_RDDQ6_SLAVE_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_347__PHY_RDDQ6_SLAVE_DELAY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_347__PHY_RDDQ6_SLAVE_DELAY_1_WIDTH 10U
+#define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_1__REG DENALI_PHY_347
+#define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_347__PHY_RDDQ6_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_347__PHY_RDDQ7_SLAVE_DELAY_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_347__PHY_RDDQ7_SLAVE_DELAY_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_347__PHY_RDDQ7_SLAVE_DELAY_1_WIDTH 10U
+#define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_1__REG DENALI_PHY_347
+#define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_347__PHY_RDDQ7_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_348_READ_MASK 0x1F0703FFU
+#define LPDDR4__DENALI_PHY_348_WRITE_MASK 0x1F0703FFU
+#define LPDDR4__DENALI_PHY_348__PHY_RDDM_SLAVE_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_348__PHY_RDDM_SLAVE_DELAY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_348__PHY_RDDM_SLAVE_DELAY_1_WIDTH 10U
+#define LPDDR4__PHY_RDDM_SLAVE_DELAY_1__REG DENALI_PHY_348
+#define LPDDR4__PHY_RDDM_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_348__PHY_RDDM_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_348__PHY_RX_PCLK_CLK_SEL_1_MASK 0x00070000U
+#define LPDDR4__DENALI_PHY_348__PHY_RX_PCLK_CLK_SEL_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_348__PHY_RX_PCLK_CLK_SEL_1_WIDTH 3U
+#define LPDDR4__PHY_RX_PCLK_CLK_SEL_1__REG DENALI_PHY_348
+#define LPDDR4__PHY_RX_PCLK_CLK_SEL_1__FLD LPDDR4__DENALI_PHY_348__PHY_RX_PCLK_CLK_SEL_1
+
+#define LPDDR4__DENALI_PHY_348__PHY_RX_CAL_ALL_DLY_1_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_348__PHY_RX_CAL_ALL_DLY_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_348__PHY_RX_CAL_ALL_DLY_1_WIDTH 5U
+#define LPDDR4__PHY_RX_CAL_ALL_DLY_1__REG DENALI_PHY_348
+#define LPDDR4__PHY_RX_CAL_ALL_DLY_1__FLD LPDDR4__DENALI_PHY_348__PHY_RX_CAL_ALL_DLY_1
+
+#define LPDDR4__DENALI_PHY_349_READ_MASK 0x00000007U
+#define LPDDR4__DENALI_PHY_349_WRITE_MASK 0x00000007U
+#define LPDDR4__DENALI_PHY_349__PHY_DATA_DC_CAL_CLK_SEL_1_MASK 0x00000007U
+#define LPDDR4__DENALI_PHY_349__PHY_DATA_DC_CAL_CLK_SEL_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_349__PHY_DATA_DC_CAL_CLK_SEL_1_WIDTH 3U
+#define LPDDR4__PHY_DATA_DC_CAL_CLK_SEL_1__REG DENALI_PHY_349
+#define LPDDR4__PHY_DATA_DC_CAL_CLK_SEL_1__FLD LPDDR4__DENALI_PHY_349__PHY_DATA_DC_CAL_CLK_SEL_1
+
+#define LPDDR4__DENALI_PHY_350_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_350_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_350__PHY_DQ_OE_TIMING_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_350__PHY_DQ_OE_TIMING_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_350__PHY_DQ_OE_TIMING_1_WIDTH 8U
+#define LPDDR4__PHY_DQ_OE_TIMING_1__REG DENALI_PHY_350
+#define LPDDR4__PHY_DQ_OE_TIMING_1__FLD LPDDR4__DENALI_PHY_350__PHY_DQ_OE_TIMING_1
+
+#define LPDDR4__DENALI_PHY_350__PHY_DQ_TSEL_RD_TIMING_1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_350__PHY_DQ_TSEL_RD_TIMING_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_350__PHY_DQ_TSEL_RD_TIMING_1_WIDTH 8U
+#define LPDDR4__PHY_DQ_TSEL_RD_TIMING_1__REG DENALI_PHY_350
+#define LPDDR4__PHY_DQ_TSEL_RD_TIMING_1__FLD LPDDR4__DENALI_PHY_350__PHY_DQ_TSEL_RD_TIMING_1
+
+#define LPDDR4__DENALI_PHY_350__PHY_DQ_TSEL_WR_TIMING_1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_350__PHY_DQ_TSEL_WR_TIMING_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_350__PHY_DQ_TSEL_WR_TIMING_1_WIDTH 8U
+#define LPDDR4__PHY_DQ_TSEL_WR_TIMING_1__REG DENALI_PHY_350
+#define LPDDR4__PHY_DQ_TSEL_WR_TIMING_1__FLD LPDDR4__DENALI_PHY_350__PHY_DQ_TSEL_WR_TIMING_1
+
+#define LPDDR4__DENALI_PHY_350__PHY_DQS_OE_TIMING_1_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_350__PHY_DQS_OE_TIMING_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_350__PHY_DQS_OE_TIMING_1_WIDTH 8U
+#define LPDDR4__PHY_DQS_OE_TIMING_1__REG DENALI_PHY_350
+#define LPDDR4__PHY_DQS_OE_TIMING_1__FLD LPDDR4__DENALI_PHY_350__PHY_DQS_OE_TIMING_1
+
+#define LPDDR4__DENALI_PHY_351_READ_MASK 0xFFFFFF0FU
+#define LPDDR4__DENALI_PHY_351_WRITE_MASK 0xFFFFFF0FU
+#define LPDDR4__DENALI_PHY_351__PHY_IO_PAD_DELAY_TIMING_1_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_351__PHY_IO_PAD_DELAY_TIMING_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_351__PHY_IO_PAD_DELAY_TIMING_1_WIDTH 4U
+#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_1__REG DENALI_PHY_351
+#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_1__FLD LPDDR4__DENALI_PHY_351__PHY_IO_PAD_DELAY_TIMING_1
+
+#define LPDDR4__DENALI_PHY_351__PHY_DQS_TSEL_RD_TIMING_1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_351__PHY_DQS_TSEL_RD_TIMING_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_351__PHY_DQS_TSEL_RD_TIMING_1_WIDTH 8U
+#define LPDDR4__PHY_DQS_TSEL_RD_TIMING_1__REG DENALI_PHY_351
+#define LPDDR4__PHY_DQS_TSEL_RD_TIMING_1__FLD LPDDR4__DENALI_PHY_351__PHY_DQS_TSEL_RD_TIMING_1
+
+#define LPDDR4__DENALI_PHY_351__PHY_DQS_OE_RD_TIMING_1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_351__PHY_DQS_OE_RD_TIMING_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_351__PHY_DQS_OE_RD_TIMING_1_WIDTH 8U
+#define LPDDR4__PHY_DQS_OE_RD_TIMING_1__REG DENALI_PHY_351
+#define LPDDR4__PHY_DQS_OE_RD_TIMING_1__FLD LPDDR4__DENALI_PHY_351__PHY_DQS_OE_RD_TIMING_1
+
+#define LPDDR4__DENALI_PHY_351__PHY_DQS_TSEL_WR_TIMING_1_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_351__PHY_DQS_TSEL_WR_TIMING_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_351__PHY_DQS_TSEL_WR_TIMING_1_WIDTH 8U
+#define LPDDR4__PHY_DQS_TSEL_WR_TIMING_1__REG DENALI_PHY_351
+#define LPDDR4__PHY_DQS_TSEL_WR_TIMING_1__FLD LPDDR4__DENALI_PHY_351__PHY_DQS_TSEL_WR_TIMING_1
+
+#define LPDDR4__DENALI_PHY_352_READ_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_352_WRITE_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_352__PHY_VREF_SETTING_TIME_1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_352__PHY_VREF_SETTING_TIME_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_352__PHY_VREF_SETTING_TIME_1_WIDTH 16U
+#define LPDDR4__PHY_VREF_SETTING_TIME_1__REG DENALI_PHY_352
+#define LPDDR4__PHY_VREF_SETTING_TIME_1__FLD LPDDR4__DENALI_PHY_352__PHY_VREF_SETTING_TIME_1
+
+#define LPDDR4__DENALI_PHY_352__PHY_PAD_VREF_CTRL_DQ_1_MASK 0x0FFF0000U
+#define LPDDR4__DENALI_PHY_352__PHY_PAD_VREF_CTRL_DQ_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_352__PHY_PAD_VREF_CTRL_DQ_1_WIDTH 12U
+#define LPDDR4__PHY_PAD_VREF_CTRL_DQ_1__REG DENALI_PHY_352
+#define LPDDR4__PHY_PAD_VREF_CTRL_DQ_1__FLD LPDDR4__DENALI_PHY_352__PHY_PAD_VREF_CTRL_DQ_1
+
+#define LPDDR4__DENALI_PHY_353_READ_MASK 0x03FFFF01U
+#define LPDDR4__DENALI_PHY_353_WRITE_MASK 0x03FFFF01U
+#define LPDDR4__DENALI_PHY_353__PHY_PER_CS_TRAINING_EN_1_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_353__PHY_PER_CS_TRAINING_EN_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_353__PHY_PER_CS_TRAINING_EN_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_353__PHY_PER_CS_TRAINING_EN_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_353__PHY_PER_CS_TRAINING_EN_1_WOSET 0U
+#define LPDDR4__PHY_PER_CS_TRAINING_EN_1__REG DENALI_PHY_353
+#define LPDDR4__PHY_PER_CS_TRAINING_EN_1__FLD LPDDR4__DENALI_PHY_353__PHY_PER_CS_TRAINING_EN_1
+
+#define LPDDR4__DENALI_PHY_353__PHY_DQ_IE_TIMING_1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_353__PHY_DQ_IE_TIMING_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_353__PHY_DQ_IE_TIMING_1_WIDTH 8U
+#define LPDDR4__PHY_DQ_IE_TIMING_1__REG DENALI_PHY_353
+#define LPDDR4__PHY_DQ_IE_TIMING_1__FLD LPDDR4__DENALI_PHY_353__PHY_DQ_IE_TIMING_1
+
+#define LPDDR4__DENALI_PHY_353__PHY_DQS_IE_TIMING_1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_353__PHY_DQS_IE_TIMING_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_353__PHY_DQS_IE_TIMING_1_WIDTH 8U
+#define LPDDR4__PHY_DQS_IE_TIMING_1__REG DENALI_PHY_353
+#define LPDDR4__PHY_DQS_IE_TIMING_1__FLD LPDDR4__DENALI_PHY_353__PHY_DQS_IE_TIMING_1
+
+#define LPDDR4__DENALI_PHY_353__PHY_RDDATA_EN_IE_DLY_1_MASK 0x03000000U
+#define LPDDR4__DENALI_PHY_353__PHY_RDDATA_EN_IE_DLY_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_353__PHY_RDDATA_EN_IE_DLY_1_WIDTH 2U
+#define LPDDR4__PHY_RDDATA_EN_IE_DLY_1__REG DENALI_PHY_353
+#define LPDDR4__PHY_RDDATA_EN_IE_DLY_1__FLD LPDDR4__DENALI_PHY_353__PHY_RDDATA_EN_IE_DLY_1
+
+#define LPDDR4__DENALI_PHY_354_READ_MASK 0x1F010303U
+#define LPDDR4__DENALI_PHY_354_WRITE_MASK 0x1F010303U
+#define LPDDR4__DENALI_PHY_354__PHY_IE_MODE_1_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_354__PHY_IE_MODE_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_354__PHY_IE_MODE_1_WIDTH 2U
+#define LPDDR4__PHY_IE_MODE_1__REG DENALI_PHY_354
+#define LPDDR4__PHY_IE_MODE_1__FLD LPDDR4__DENALI_PHY_354__PHY_IE_MODE_1
+
+#define LPDDR4__DENALI_PHY_354__PHY_DBI_MODE_1_MASK 0x00000300U
+#define LPDDR4__DENALI_PHY_354__PHY_DBI_MODE_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_354__PHY_DBI_MODE_1_WIDTH 2U
+#define LPDDR4__PHY_DBI_MODE_1__REG DENALI_PHY_354
+#define LPDDR4__PHY_DBI_MODE_1__FLD LPDDR4__DENALI_PHY_354__PHY_DBI_MODE_1
+
+#define LPDDR4__DENALI_PHY_354__PHY_WDQLVL_IE_ON_1_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_354__PHY_WDQLVL_IE_ON_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_354__PHY_WDQLVL_IE_ON_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_354__PHY_WDQLVL_IE_ON_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_354__PHY_WDQLVL_IE_ON_1_WOSET 0U
+#define LPDDR4__PHY_WDQLVL_IE_ON_1__REG DENALI_PHY_354
+#define LPDDR4__PHY_WDQLVL_IE_ON_1__FLD LPDDR4__DENALI_PHY_354__PHY_WDQLVL_IE_ON_1
+
+#define LPDDR4__DENALI_PHY_354__PHY_WDQLVL_RDDATA_EN_DLY_1_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_354__PHY_WDQLVL_RDDATA_EN_DLY_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_354__PHY_WDQLVL_RDDATA_EN_DLY_1_WIDTH 5U
+#define LPDDR4__PHY_WDQLVL_RDDATA_EN_DLY_1__REG DENALI_PHY_354
+#define LPDDR4__PHY_WDQLVL_RDDATA_EN_DLY_1__FLD LPDDR4__DENALI_PHY_354__PHY_WDQLVL_RDDATA_EN_DLY_1
+
+#define LPDDR4__DENALI_PHY_355_READ_MASK 0x0F1F1F1FU
+#define LPDDR4__DENALI_PHY_355_WRITE_MASK 0x0F1F1F1FU
+#define LPDDR4__DENALI_PHY_355__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_1_MASK 0x0000001FU
+#define LPDDR4__DENALI_PHY_355__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_355__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_1_WIDTH 5U
+#define LPDDR4__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_1__REG DENALI_PHY_355
+#define LPDDR4__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_1__FLD LPDDR4__DENALI_PHY_355__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_1
+
+#define LPDDR4__DENALI_PHY_355__PHY_RDDATA_EN_TSEL_DLY_1_MASK 0x00001F00U
+#define LPDDR4__DENALI_PHY_355__PHY_RDDATA_EN_TSEL_DLY_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_355__PHY_RDDATA_EN_TSEL_DLY_1_WIDTH 5U
+#define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_1__REG DENALI_PHY_355
+#define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_1__FLD LPDDR4__DENALI_PHY_355__PHY_RDDATA_EN_TSEL_DLY_1
+
+#define LPDDR4__DENALI_PHY_355__PHY_RDDATA_EN_OE_DLY_1_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_355__PHY_RDDATA_EN_OE_DLY_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_355__PHY_RDDATA_EN_OE_DLY_1_WIDTH 5U
+#define LPDDR4__PHY_RDDATA_EN_OE_DLY_1__REG DENALI_PHY_355
+#define LPDDR4__PHY_RDDATA_EN_OE_DLY_1__FLD LPDDR4__DENALI_PHY_355__PHY_RDDATA_EN_OE_DLY_1
+
+#define LPDDR4__DENALI_PHY_355__PHY_SW_MASTER_MODE_1_MASK 0x0F000000U
+#define LPDDR4__DENALI_PHY_355__PHY_SW_MASTER_MODE_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_355__PHY_SW_MASTER_MODE_1_WIDTH 4U
+#define LPDDR4__PHY_SW_MASTER_MODE_1__REG DENALI_PHY_355
+#define LPDDR4__PHY_SW_MASTER_MODE_1__FLD LPDDR4__DENALI_PHY_355__PHY_SW_MASTER_MODE_1
+
+#define LPDDR4__DENALI_PHY_356_READ_MASK 0xFF3F07FFU
+#define LPDDR4__DENALI_PHY_356_WRITE_MASK 0xFF3F07FFU
+#define LPDDR4__DENALI_PHY_356__PHY_MASTER_DELAY_START_1_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_356__PHY_MASTER_DELAY_START_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_356__PHY_MASTER_DELAY_START_1_WIDTH 11U
+#define LPDDR4__PHY_MASTER_DELAY_START_1__REG DENALI_PHY_356
+#define LPDDR4__PHY_MASTER_DELAY_START_1__FLD LPDDR4__DENALI_PHY_356__PHY_MASTER_DELAY_START_1
+
+#define LPDDR4__DENALI_PHY_356__PHY_MASTER_DELAY_STEP_1_MASK 0x003F0000U
+#define LPDDR4__DENALI_PHY_356__PHY_MASTER_DELAY_STEP_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_356__PHY_MASTER_DELAY_STEP_1_WIDTH 6U
+#define LPDDR4__PHY_MASTER_DELAY_STEP_1__REG DENALI_PHY_356
+#define LPDDR4__PHY_MASTER_DELAY_STEP_1__FLD LPDDR4__DENALI_PHY_356__PHY_MASTER_DELAY_STEP_1
+
+#define LPDDR4__DENALI_PHY_356__PHY_MASTER_DELAY_WAIT_1_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_356__PHY_MASTER_DELAY_WAIT_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_356__PHY_MASTER_DELAY_WAIT_1_WIDTH 8U
+#define LPDDR4__PHY_MASTER_DELAY_WAIT_1__REG DENALI_PHY_356
+#define LPDDR4__PHY_MASTER_DELAY_WAIT_1__FLD LPDDR4__DENALI_PHY_356__PHY_MASTER_DELAY_WAIT_1
+
+#define LPDDR4__DENALI_PHY_357_READ_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_PHY_357_WRITE_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_PHY_357__PHY_MASTER_DELAY_HALF_MEASURE_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_357__PHY_MASTER_DELAY_HALF_MEASURE_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_357__PHY_MASTER_DELAY_HALF_MEASURE_1_WIDTH 8U
+#define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_1__REG DENALI_PHY_357
+#define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_1__FLD LPDDR4__DENALI_PHY_357__PHY_MASTER_DELAY_HALF_MEASURE_1
+
+#define LPDDR4__DENALI_PHY_357__PHY_RPTR_UPDATE_1_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_357__PHY_RPTR_UPDATE_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_357__PHY_RPTR_UPDATE_1_WIDTH 4U
+#define LPDDR4__PHY_RPTR_UPDATE_1__REG DENALI_PHY_357
+#define LPDDR4__PHY_RPTR_UPDATE_1__FLD LPDDR4__DENALI_PHY_357__PHY_RPTR_UPDATE_1
+
+#define LPDDR4__DENALI_PHY_357__PHY_WRLVL_DLY_STEP_1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_357__PHY_WRLVL_DLY_STEP_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_357__PHY_WRLVL_DLY_STEP_1_WIDTH 8U
+#define LPDDR4__PHY_WRLVL_DLY_STEP_1__REG DENALI_PHY_357
+#define LPDDR4__PHY_WRLVL_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_357__PHY_WRLVL_DLY_STEP_1
+
+#define LPDDR4__DENALI_PHY_357__PHY_WRLVL_DLY_FINE_STEP_1_MASK 0x0F000000U
+#define LPDDR4__DENALI_PHY_357__PHY_WRLVL_DLY_FINE_STEP_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_357__PHY_WRLVL_DLY_FINE_STEP_1_WIDTH 4U
+#define LPDDR4__PHY_WRLVL_DLY_FINE_STEP_1__REG DENALI_PHY_357
+#define LPDDR4__PHY_WRLVL_DLY_FINE_STEP_1__FLD LPDDR4__DENALI_PHY_357__PHY_WRLVL_DLY_FINE_STEP_1
+
+#define LPDDR4__DENALI_PHY_358_READ_MASK 0x001F0F3FU
+#define LPDDR4__DENALI_PHY_358_WRITE_MASK 0x001F0F3FU
+#define LPDDR4__DENALI_PHY_358__PHY_WRLVL_RESP_WAIT_CNT_1_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_358__PHY_WRLVL_RESP_WAIT_CNT_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_358__PHY_WRLVL_RESP_WAIT_CNT_1_WIDTH 6U
+#define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_1__REG DENALI_PHY_358
+#define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_358__PHY_WRLVL_RESP_WAIT_CNT_1
+
+#define LPDDR4__DENALI_PHY_358__PHY_GTLVL_DLY_STEP_1_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_358__PHY_GTLVL_DLY_STEP_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_358__PHY_GTLVL_DLY_STEP_1_WIDTH 4U
+#define LPDDR4__PHY_GTLVL_DLY_STEP_1__REG DENALI_PHY_358
+#define LPDDR4__PHY_GTLVL_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_358__PHY_GTLVL_DLY_STEP_1
+
+#define LPDDR4__DENALI_PHY_358__PHY_GTLVL_RESP_WAIT_CNT_1_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_358__PHY_GTLVL_RESP_WAIT_CNT_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_358__PHY_GTLVL_RESP_WAIT_CNT_1_WIDTH 5U
+#define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_1__REG DENALI_PHY_358
+#define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_358__PHY_GTLVL_RESP_WAIT_CNT_1
+
+#define LPDDR4__DENALI_PHY_359_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_359_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_359__PHY_GTLVL_BACK_STEP_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_359__PHY_GTLVL_BACK_STEP_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_359__PHY_GTLVL_BACK_STEP_1_WIDTH 10U
+#define LPDDR4__PHY_GTLVL_BACK_STEP_1__REG DENALI_PHY_359
+#define LPDDR4__PHY_GTLVL_BACK_STEP_1__FLD LPDDR4__DENALI_PHY_359__PHY_GTLVL_BACK_STEP_1
+
+#define LPDDR4__DENALI_PHY_359__PHY_GTLVL_FINAL_STEP_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_359__PHY_GTLVL_FINAL_STEP_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_359__PHY_GTLVL_FINAL_STEP_1_WIDTH 10U
+#define LPDDR4__PHY_GTLVL_FINAL_STEP_1__REG DENALI_PHY_359
+#define LPDDR4__PHY_GTLVL_FINAL_STEP_1__FLD LPDDR4__DENALI_PHY_359__PHY_GTLVL_FINAL_STEP_1
+
+#define LPDDR4__DENALI_PHY_360_READ_MASK 0x01FF0FFFU
+#define LPDDR4__DENALI_PHY_360_WRITE_MASK 0x01FF0FFFU
+#define LPDDR4__DENALI_PHY_360__PHY_WDQLVL_DLY_STEP_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_360__PHY_WDQLVL_DLY_STEP_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_360__PHY_WDQLVL_DLY_STEP_1_WIDTH 8U
+#define LPDDR4__PHY_WDQLVL_DLY_STEP_1__REG DENALI_PHY_360
+#define LPDDR4__PHY_WDQLVL_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_360__PHY_WDQLVL_DLY_STEP_1
+
+#define LPDDR4__DENALI_PHY_360__PHY_WDQLVL_QTR_DLY_STEP_1_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_360__PHY_WDQLVL_QTR_DLY_STEP_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_360__PHY_WDQLVL_QTR_DLY_STEP_1_WIDTH 4U
+#define LPDDR4__PHY_WDQLVL_QTR_DLY_STEP_1__REG DENALI_PHY_360
+#define LPDDR4__PHY_WDQLVL_QTR_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_360__PHY_WDQLVL_QTR_DLY_STEP_1
+
+#define LPDDR4__DENALI_PHY_360__PHY_WDQLVL_DM_SEARCH_RANGE_1_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_360__PHY_WDQLVL_DM_SEARCH_RANGE_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_360__PHY_WDQLVL_DM_SEARCH_RANGE_1_WIDTH 9U
+#define LPDDR4__PHY_WDQLVL_DM_SEARCH_RANGE_1__REG DENALI_PHY_360
+#define LPDDR4__PHY_WDQLVL_DM_SEARCH_RANGE_1__FLD LPDDR4__DENALI_PHY_360__PHY_WDQLVL_DM_SEARCH_RANGE_1
+
+#define LPDDR4__DENALI_PHY_361_READ_MASK 0x00000F01U
+#define LPDDR4__DENALI_PHY_361_WRITE_MASK 0x00000F01U
+#define LPDDR4__DENALI_PHY_361__PHY_TOGGLE_PRE_SUPPORT_1_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_361__PHY_TOGGLE_PRE_SUPPORT_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_361__PHY_TOGGLE_PRE_SUPPORT_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_361__PHY_TOGGLE_PRE_SUPPORT_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_361__PHY_TOGGLE_PRE_SUPPORT_1_WOSET 0U
+#define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_1__REG DENALI_PHY_361
+#define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_1__FLD LPDDR4__DENALI_PHY_361__PHY_TOGGLE_PRE_SUPPORT_1
+
+#define LPDDR4__DENALI_PHY_361__PHY_RDLVL_DLY_STEP_1_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_361__PHY_RDLVL_DLY_STEP_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_361__PHY_RDLVL_DLY_STEP_1_WIDTH 4U
+#define LPDDR4__PHY_RDLVL_DLY_STEP_1__REG DENALI_PHY_361
+#define LPDDR4__PHY_RDLVL_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_361__PHY_RDLVL_DLY_STEP_1
+
+#define LPDDR4__DENALI_PHY_362_READ_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_362_WRITE_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_362__PHY_RDLVL_MAX_EDGE_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_362__PHY_RDLVL_MAX_EDGE_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_362__PHY_RDLVL_MAX_EDGE_1_WIDTH 10U
+#define LPDDR4__PHY_RDLVL_MAX_EDGE_1__REG DENALI_PHY_362
+#define LPDDR4__PHY_RDLVL_MAX_EDGE_1__FLD LPDDR4__DENALI_PHY_362__PHY_RDLVL_MAX_EDGE_1
+
+#define LPDDR4__DENALI_PHY_363_READ_MASK 0x00030703U
+#define LPDDR4__DENALI_PHY_363_WRITE_MASK 0x00030703U
+#define LPDDR4__DENALI_PHY_363__PHY_WRPATH_GATE_DISABLE_1_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_363__PHY_WRPATH_GATE_DISABLE_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_363__PHY_WRPATH_GATE_DISABLE_1_WIDTH 2U
+#define LPDDR4__PHY_WRPATH_GATE_DISABLE_1__REG DENALI_PHY_363
+#define LPDDR4__PHY_WRPATH_GATE_DISABLE_1__FLD LPDDR4__DENALI_PHY_363__PHY_WRPATH_GATE_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_363__PHY_WRPATH_GATE_TIMING_1_MASK 0x00000700U
+#define LPDDR4__DENALI_PHY_363__PHY_WRPATH_GATE_TIMING_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_363__PHY_WRPATH_GATE_TIMING_1_WIDTH 3U
+#define LPDDR4__PHY_WRPATH_GATE_TIMING_1__REG DENALI_PHY_363
+#define LPDDR4__PHY_WRPATH_GATE_TIMING_1__FLD LPDDR4__DENALI_PHY_363__PHY_WRPATH_GATE_TIMING_1
+
+#define LPDDR4__DENALI_PHY_363__PHY_DATA_DC_INIT_DISABLE_1_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_363__PHY_DATA_DC_INIT_DISABLE_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_363__PHY_DATA_DC_INIT_DISABLE_1_WIDTH 2U
+#define LPDDR4__PHY_DATA_DC_INIT_DISABLE_1__REG DENALI_PHY_363
+#define LPDDR4__PHY_DATA_DC_INIT_DISABLE_1__FLD LPDDR4__DENALI_PHY_363__PHY_DATA_DC_INIT_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_364_READ_MASK 0x07FF03FFU
+#define LPDDR4__DENALI_PHY_364_WRITE_MASK 0x07FF03FFU
+#define LPDDR4__DENALI_PHY_364__PHY_DATA_DC_DQS_INIT_SLV_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_364__PHY_DATA_DC_DQS_INIT_SLV_DELAY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_364__PHY_DATA_DC_DQS_INIT_SLV_DELAY_1_WIDTH 10U
+#define LPDDR4__PHY_DATA_DC_DQS_INIT_SLV_DELAY_1__REG DENALI_PHY_364
+#define LPDDR4__PHY_DATA_DC_DQS_INIT_SLV_DELAY_1__FLD LPDDR4__DENALI_PHY_364__PHY_DATA_DC_DQS_INIT_SLV_DELAY_1
+
+#define LPDDR4__DENALI_PHY_364__PHY_DATA_DC_DQ_INIT_SLV_DELAY_1_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_364__PHY_DATA_DC_DQ_INIT_SLV_DELAY_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_364__PHY_DATA_DC_DQ_INIT_SLV_DELAY_1_WIDTH 11U
+#define LPDDR4__PHY_DATA_DC_DQ_INIT_SLV_DELAY_1__REG DENALI_PHY_364
+#define LPDDR4__PHY_DATA_DC_DQ_INIT_SLV_DELAY_1__FLD LPDDR4__DENALI_PHY_364__PHY_DATA_DC_DQ_INIT_SLV_DELAY_1
+
+#define LPDDR4__DENALI_PHY_365_READ_MASK 0xFFFF0101U
+#define LPDDR4__DENALI_PHY_365_WRITE_MASK 0xFFFF0101U
+#define LPDDR4__DENALI_PHY_365__PHY_DATA_DC_WRLVL_ENABLE_1_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_365__PHY_DATA_DC_WRLVL_ENABLE_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_365__PHY_DATA_DC_WRLVL_ENABLE_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_365__PHY_DATA_DC_WRLVL_ENABLE_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_365__PHY_DATA_DC_WRLVL_ENABLE_1_WOSET 0U
+#define LPDDR4__PHY_DATA_DC_WRLVL_ENABLE_1__REG DENALI_PHY_365
+#define LPDDR4__PHY_DATA_DC_WRLVL_ENABLE_1__FLD LPDDR4__DENALI_PHY_365__PHY_DATA_DC_WRLVL_ENABLE_1
+
+#define LPDDR4__DENALI_PHY_365__PHY_DATA_DC_WDQLVL_ENABLE_1_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_365__PHY_DATA_DC_WDQLVL_ENABLE_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_365__PHY_DATA_DC_WDQLVL_ENABLE_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_365__PHY_DATA_DC_WDQLVL_ENABLE_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_365__PHY_DATA_DC_WDQLVL_ENABLE_1_WOSET 0U
+#define LPDDR4__PHY_DATA_DC_WDQLVL_ENABLE_1__REG DENALI_PHY_365
+#define LPDDR4__PHY_DATA_DC_WDQLVL_ENABLE_1__FLD LPDDR4__DENALI_PHY_365__PHY_DATA_DC_WDQLVL_ENABLE_1
+
+#define LPDDR4__DENALI_PHY_365__PHY_DATA_DC_DM_CLK_SE_THRSHLD_1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_365__PHY_DATA_DC_DM_CLK_SE_THRSHLD_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_365__PHY_DATA_DC_DM_CLK_SE_THRSHLD_1_WIDTH 8U
+#define LPDDR4__PHY_DATA_DC_DM_CLK_SE_THRSHLD_1__REG DENALI_PHY_365
+#define LPDDR4__PHY_DATA_DC_DM_CLK_SE_THRSHLD_1__FLD LPDDR4__DENALI_PHY_365__PHY_DATA_DC_DM_CLK_SE_THRSHLD_1
+
+#define LPDDR4__DENALI_PHY_365__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_1_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_365__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_365__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_1_WIDTH 8U
+#define LPDDR4__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_1__REG DENALI_PHY_365
+#define LPDDR4__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_1__FLD LPDDR4__DENALI_PHY_365__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_1
+
+#define LPDDR4__DENALI_PHY_366_READ_MASK 0x001F7F7FU
+#define LPDDR4__DENALI_PHY_366_WRITE_MASK 0x001F7F7FU
+#define LPDDR4__DENALI_PHY_366__PHY_WDQ_OSC_DELTA_1_MASK 0x0000007FU
+#define LPDDR4__DENALI_PHY_366__PHY_WDQ_OSC_DELTA_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_366__PHY_WDQ_OSC_DELTA_1_WIDTH 7U
+#define LPDDR4__PHY_WDQ_OSC_DELTA_1__REG DENALI_PHY_366
+#define LPDDR4__PHY_WDQ_OSC_DELTA_1__FLD LPDDR4__DENALI_PHY_366__PHY_WDQ_OSC_DELTA_1
+
+#define LPDDR4__DENALI_PHY_366__PHY_MEAS_DLY_STEP_ENABLE_1_MASK 0x00007F00U
+#define LPDDR4__DENALI_PHY_366__PHY_MEAS_DLY_STEP_ENABLE_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_366__PHY_MEAS_DLY_STEP_ENABLE_1_WIDTH 7U
+#define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_1__REG DENALI_PHY_366
+#define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_1__FLD LPDDR4__DENALI_PHY_366__PHY_MEAS_DLY_STEP_ENABLE_1
+
+#define LPDDR4__DENALI_PHY_366__PHY_RDDATA_EN_DLY_1_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_366__PHY_RDDATA_EN_DLY_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_366__PHY_RDDATA_EN_DLY_1_WIDTH 5U
+#define LPDDR4__PHY_RDDATA_EN_DLY_1__REG DENALI_PHY_366
+#define LPDDR4__PHY_RDDATA_EN_DLY_1__FLD LPDDR4__DENALI_PHY_366__PHY_RDDATA_EN_DLY_1
+
+#define LPDDR4__DENALI_PHY_367_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_367_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_367__PHY_DQ_DM_SWIZZLE0_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_367__PHY_DQ_DM_SWIZZLE0_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_367__PHY_DQ_DM_SWIZZLE0_1_WIDTH 32U
+#define LPDDR4__PHY_DQ_DM_SWIZZLE0_1__REG DENALI_PHY_367
+#define LPDDR4__PHY_DQ_DM_SWIZZLE0_1__FLD LPDDR4__DENALI_PHY_367__PHY_DQ_DM_SWIZZLE0_1
+
+#define LPDDR4__DENALI_PHY_368_READ_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_368_WRITE_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_368__PHY_DQ_DM_SWIZZLE1_1_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_368__PHY_DQ_DM_SWIZZLE1_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_368__PHY_DQ_DM_SWIZZLE1_1_WIDTH 4U
+#define LPDDR4__PHY_DQ_DM_SWIZZLE1_1__REG DENALI_PHY_368
+#define LPDDR4__PHY_DQ_DM_SWIZZLE1_1__FLD LPDDR4__DENALI_PHY_368__PHY_DQ_DM_SWIZZLE1_1
+
+#define LPDDR4__DENALI_PHY_369_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_369_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_369__PHY_CLK_WRDQ0_SLAVE_DELAY_1_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_369__PHY_CLK_WRDQ0_SLAVE_DELAY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_369__PHY_CLK_WRDQ0_SLAVE_DELAY_1_WIDTH 11U
+#define LPDDR4__PHY_CLK_WRDQ0_SLAVE_DELAY_1__REG DENALI_PHY_369
+#define LPDDR4__PHY_CLK_WRDQ0_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_369__PHY_CLK_WRDQ0_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_369__PHY_CLK_WRDQ1_SLAVE_DELAY_1_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_369__PHY_CLK_WRDQ1_SLAVE_DELAY_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_369__PHY_CLK_WRDQ1_SLAVE_DELAY_1_WIDTH 11U
+#define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_1__REG DENALI_PHY_369
+#define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_369__PHY_CLK_WRDQ1_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_370_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_370_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_370__PHY_CLK_WRDQ2_SLAVE_DELAY_1_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_370__PHY_CLK_WRDQ2_SLAVE_DELAY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_370__PHY_CLK_WRDQ2_SLAVE_DELAY_1_WIDTH 11U
+#define LPDDR4__PHY_CLK_WRDQ2_SLAVE_DELAY_1__REG DENALI_PHY_370
+#define LPDDR4__PHY_CLK_WRDQ2_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_370__PHY_CLK_WRDQ2_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_370__PHY_CLK_WRDQ3_SLAVE_DELAY_1_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_370__PHY_CLK_WRDQ3_SLAVE_DELAY_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_370__PHY_CLK_WRDQ3_SLAVE_DELAY_1_WIDTH 11U
+#define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_1__REG DENALI_PHY_370
+#define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_370__PHY_CLK_WRDQ3_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_371_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_371_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_371__PHY_CLK_WRDQ4_SLAVE_DELAY_1_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_371__PHY_CLK_WRDQ4_SLAVE_DELAY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_371__PHY_CLK_WRDQ4_SLAVE_DELAY_1_WIDTH 11U
+#define LPDDR4__PHY_CLK_WRDQ4_SLAVE_DELAY_1__REG DENALI_PHY_371
+#define LPDDR4__PHY_CLK_WRDQ4_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_371__PHY_CLK_WRDQ4_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_371__PHY_CLK_WRDQ5_SLAVE_DELAY_1_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_371__PHY_CLK_WRDQ5_SLAVE_DELAY_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_371__PHY_CLK_WRDQ5_SLAVE_DELAY_1_WIDTH 11U
+#define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_1__REG DENALI_PHY_371
+#define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_371__PHY_CLK_WRDQ5_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_372_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_372_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_372__PHY_CLK_WRDQ6_SLAVE_DELAY_1_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_372__PHY_CLK_WRDQ6_SLAVE_DELAY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_372__PHY_CLK_WRDQ6_SLAVE_DELAY_1_WIDTH 11U
+#define LPDDR4__PHY_CLK_WRDQ6_SLAVE_DELAY_1__REG DENALI_PHY_372
+#define LPDDR4__PHY_CLK_WRDQ6_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_372__PHY_CLK_WRDQ6_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_372__PHY_CLK_WRDQ7_SLAVE_DELAY_1_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_372__PHY_CLK_WRDQ7_SLAVE_DELAY_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_372__PHY_CLK_WRDQ7_SLAVE_DELAY_1_WIDTH 11U
+#define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_1__REG DENALI_PHY_372
+#define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_372__PHY_CLK_WRDQ7_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_373_READ_MASK 0x03FF07FFU
+#define LPDDR4__DENALI_PHY_373_WRITE_MASK 0x03FF07FFU
+#define LPDDR4__DENALI_PHY_373__PHY_CLK_WRDM_SLAVE_DELAY_1_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_373__PHY_CLK_WRDM_SLAVE_DELAY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_373__PHY_CLK_WRDM_SLAVE_DELAY_1_WIDTH 11U
+#define LPDDR4__PHY_CLK_WRDM_SLAVE_DELAY_1__REG DENALI_PHY_373
+#define LPDDR4__PHY_CLK_WRDM_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_373__PHY_CLK_WRDM_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_373__PHY_CLK_WRDQS_SLAVE_DELAY_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_373__PHY_CLK_WRDQS_SLAVE_DELAY_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_373__PHY_CLK_WRDQS_SLAVE_DELAY_1_WIDTH 10U
+#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_1__REG DENALI_PHY_373
+#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_373__PHY_CLK_WRDQS_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_374_READ_MASK 0x0003FF03U
+#define LPDDR4__DENALI_PHY_374_WRITE_MASK 0x0003FF03U
+#define LPDDR4__DENALI_PHY_374__PHY_WRLVL_THRESHOLD_ADJUST_1_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_374__PHY_WRLVL_THRESHOLD_ADJUST_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_374__PHY_WRLVL_THRESHOLD_ADJUST_1_WIDTH 2U
+#define LPDDR4__PHY_WRLVL_THRESHOLD_ADJUST_1__REG DENALI_PHY_374
+#define LPDDR4__PHY_WRLVL_THRESHOLD_ADJUST_1__FLD LPDDR4__DENALI_PHY_374__PHY_WRLVL_THRESHOLD_ADJUST_1
+
+#define LPDDR4__DENALI_PHY_374__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1_MASK 0x0003FF00U
+#define LPDDR4__DENALI_PHY_374__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_374__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1__REG DENALI_PHY_374
+#define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_374__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_375_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_375_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_375__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_375__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_375__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1__REG DENALI_PHY_375
+#define LPDDR4__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_375__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_375__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_375__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_375__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1__REG DENALI_PHY_375
+#define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_375__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_376_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_376_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_376__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_376__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_376__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1__REG DENALI_PHY_376
+#define LPDDR4__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_376__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_376__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_376__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_376__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1__REG DENALI_PHY_376
+#define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_376__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_377_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_377_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_377__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_377__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_377__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1__REG DENALI_PHY_377
+#define LPDDR4__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_377__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_377__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_377__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_377__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1__REG DENALI_PHY_377
+#define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_377__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_378_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_378_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_378__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_378__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_378__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1__REG DENALI_PHY_378
+#define LPDDR4__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_378__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_378__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_378__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_378__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1__REG DENALI_PHY_378
+#define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_378__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_379_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_379_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_379__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_379__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_379__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1__REG DENALI_PHY_379
+#define LPDDR4__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_379__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_379__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_379__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_379__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1__REG DENALI_PHY_379
+#define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_379__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_380_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_380_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_380__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_380__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_380__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1__REG DENALI_PHY_380
+#define LPDDR4__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_380__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_380__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_380__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_380__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1__REG DENALI_PHY_380
+#define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_380__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_381_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_381_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_381__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_381__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_381__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1__REG DENALI_PHY_381
+#define LPDDR4__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_381__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_381__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_381__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_381__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1__REG DENALI_PHY_381
+#define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_381__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_382_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_382_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_382__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_382__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_382__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1__REG DENALI_PHY_382
+#define LPDDR4__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_382__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_382__PHY_RDDQS_DM_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_382__PHY_RDDQS_DM_RISE_SLAVE_DELAY_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_382__PHY_RDDQS_DM_RISE_SLAVE_DELAY_1_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_1__REG DENALI_PHY_382
+#define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_382__PHY_RDDQS_DM_RISE_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_383_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_383_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_383__PHY_RDDQS_DM_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_383__PHY_RDDQS_DM_FALL_SLAVE_DELAY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_383__PHY_RDDQS_DM_FALL_SLAVE_DELAY_1_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DM_FALL_SLAVE_DELAY_1__REG DENALI_PHY_383
+#define LPDDR4__PHY_RDDQS_DM_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_383__PHY_RDDQS_DM_FALL_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_383__PHY_RDDQS_GATE_SLAVE_DELAY_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_383__PHY_RDDQS_GATE_SLAVE_DELAY_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_383__PHY_RDDQS_GATE_SLAVE_DELAY_1_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_1__REG DENALI_PHY_383
+#define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_383__PHY_RDDQS_GATE_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_384_READ_MASK 0x03FF070FU
+#define LPDDR4__DENALI_PHY_384_WRITE_MASK 0x03FF070FU
+#define LPDDR4__DENALI_PHY_384__PHY_RDDQS_LATENCY_ADJUST_1_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_384__PHY_RDDQS_LATENCY_ADJUST_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_384__PHY_RDDQS_LATENCY_ADJUST_1_WIDTH 4U
+#define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_1__REG DENALI_PHY_384
+#define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_1__FLD LPDDR4__DENALI_PHY_384__PHY_RDDQS_LATENCY_ADJUST_1
+
+#define LPDDR4__DENALI_PHY_384__PHY_WRITE_PATH_LAT_ADD_1_MASK 0x00000700U
+#define LPDDR4__DENALI_PHY_384__PHY_WRITE_PATH_LAT_ADD_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_384__PHY_WRITE_PATH_LAT_ADD_1_WIDTH 3U
+#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_1__REG DENALI_PHY_384
+#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_1__FLD LPDDR4__DENALI_PHY_384__PHY_WRITE_PATH_LAT_ADD_1
+
+#define LPDDR4__DENALI_PHY_384__PHY_WRLVL_DELAY_EARLY_THRESHOLD_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_384__PHY_WRLVL_DELAY_EARLY_THRESHOLD_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_384__PHY_WRLVL_DELAY_EARLY_THRESHOLD_1_WIDTH 10U
+#define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_1__REG DENALI_PHY_384
+#define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_1__FLD LPDDR4__DENALI_PHY_384__PHY_WRLVL_DELAY_EARLY_THRESHOLD_1
+
+#define LPDDR4__DENALI_PHY_385_READ_MASK 0x000103FFU
+#define LPDDR4__DENALI_PHY_385_WRITE_MASK 0x000103FFU
+#define LPDDR4__DENALI_PHY_385__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_385__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_385__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1_WIDTH 10U
+#define LPDDR4__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1__REG DENALI_PHY_385
+#define LPDDR4__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1__FLD LPDDR4__DENALI_PHY_385__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1
+
+#define LPDDR4__DENALI_PHY_385__PHY_WRLVL_EARLY_FORCE_ZERO_1_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_385__PHY_WRLVL_EARLY_FORCE_ZERO_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_385__PHY_WRLVL_EARLY_FORCE_ZERO_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_385__PHY_WRLVL_EARLY_FORCE_ZERO_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_385__PHY_WRLVL_EARLY_FORCE_ZERO_1_WOSET 0U
+#define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_1__REG DENALI_PHY_385
+#define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_1__FLD LPDDR4__DENALI_PHY_385__PHY_WRLVL_EARLY_FORCE_ZERO_1
+
+#define LPDDR4__DENALI_PHY_386_READ_MASK 0x000F03FFU
+#define LPDDR4__DENALI_PHY_386_WRITE_MASK 0x000F03FFU
+#define LPDDR4__DENALI_PHY_386__PHY_GTLVL_RDDQS_SLV_DLY_START_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_386__PHY_GTLVL_RDDQS_SLV_DLY_START_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_386__PHY_GTLVL_RDDQS_SLV_DLY_START_1_WIDTH 10U
+#define LPDDR4__PHY_GTLVL_RDDQS_SLV_DLY_START_1__REG DENALI_PHY_386
+#define LPDDR4__PHY_GTLVL_RDDQS_SLV_DLY_START_1__FLD LPDDR4__DENALI_PHY_386__PHY_GTLVL_RDDQS_SLV_DLY_START_1
+
+#define LPDDR4__DENALI_PHY_386__PHY_GTLVL_LAT_ADJ_START_1_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_386__PHY_GTLVL_LAT_ADJ_START_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_386__PHY_GTLVL_LAT_ADJ_START_1_WIDTH 4U
+#define LPDDR4__PHY_GTLVL_LAT_ADJ_START_1__REG DENALI_PHY_386
+#define LPDDR4__PHY_GTLVL_LAT_ADJ_START_1__FLD LPDDR4__DENALI_PHY_386__PHY_GTLVL_LAT_ADJ_START_1
+
+#define LPDDR4__DENALI_PHY_387_READ_MASK 0x010F07FFU
+#define LPDDR4__DENALI_PHY_387_WRITE_MASK 0x010F07FFU
+#define LPDDR4__DENALI_PHY_387__PHY_WDQLVL_DQDM_SLV_DLY_START_1_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_387__PHY_WDQLVL_DQDM_SLV_DLY_START_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_387__PHY_WDQLVL_DQDM_SLV_DLY_START_1_WIDTH 11U
+#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_1__REG DENALI_PHY_387
+#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_1__FLD LPDDR4__DENALI_PHY_387__PHY_WDQLVL_DQDM_SLV_DLY_START_1
+
+#define LPDDR4__DENALI_PHY_387__PHY_NTP_WRLAT_START_1_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_387__PHY_NTP_WRLAT_START_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_387__PHY_NTP_WRLAT_START_1_WIDTH 4U
+#define LPDDR4__PHY_NTP_WRLAT_START_1__REG DENALI_PHY_387
+#define LPDDR4__PHY_NTP_WRLAT_START_1__FLD LPDDR4__DENALI_PHY_387__PHY_NTP_WRLAT_START_1
+
+#define LPDDR4__DENALI_PHY_387__PHY_NTP_PASS_1_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_387__PHY_NTP_PASS_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_387__PHY_NTP_PASS_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_387__PHY_NTP_PASS_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_387__PHY_NTP_PASS_1_WOSET 0U
+#define LPDDR4__PHY_NTP_PASS_1__REG DENALI_PHY_387
+#define LPDDR4__PHY_NTP_PASS_1__FLD LPDDR4__DENALI_PHY_387__PHY_NTP_PASS_1
+
+#define LPDDR4__DENALI_PHY_388_READ_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_388_WRITE_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_388__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_388__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_388__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1_WIDTH 10U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1__REG DENALI_PHY_388
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1__FLD LPDDR4__DENALI_PHY_388__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1
+
+#define LPDDR4__DENALI_PHY_389_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_389_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_389__PHY_DATA_DC_DQS_CLK_ADJUST_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_389__PHY_DATA_DC_DQS_CLK_ADJUST_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_389__PHY_DATA_DC_DQS_CLK_ADJUST_1_WIDTH 8U
+#define LPDDR4__PHY_DATA_DC_DQS_CLK_ADJUST_1__REG DENALI_PHY_389
+#define LPDDR4__PHY_DATA_DC_DQS_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_389__PHY_DATA_DC_DQS_CLK_ADJUST_1
+
+#define LPDDR4__DENALI_PHY_389__PHY_DATA_DC_DQ0_CLK_ADJUST_1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_389__PHY_DATA_DC_DQ0_CLK_ADJUST_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_389__PHY_DATA_DC_DQ0_CLK_ADJUST_1_WIDTH 8U
+#define LPDDR4__PHY_DATA_DC_DQ0_CLK_ADJUST_1__REG DENALI_PHY_389
+#define LPDDR4__PHY_DATA_DC_DQ0_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_389__PHY_DATA_DC_DQ0_CLK_ADJUST_1
+
+#define LPDDR4__DENALI_PHY_389__PHY_DATA_DC_DQ1_CLK_ADJUST_1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_389__PHY_DATA_DC_DQ1_CLK_ADJUST_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_389__PHY_DATA_DC_DQ1_CLK_ADJUST_1_WIDTH 8U
+#define LPDDR4__PHY_DATA_DC_DQ1_CLK_ADJUST_1__REG DENALI_PHY_389
+#define LPDDR4__PHY_DATA_DC_DQ1_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_389__PHY_DATA_DC_DQ1_CLK_ADJUST_1
+
+#define LPDDR4__DENALI_PHY_389__PHY_DATA_DC_DQ2_CLK_ADJUST_1_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_389__PHY_DATA_DC_DQ2_CLK_ADJUST_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_389__PHY_DATA_DC_DQ2_CLK_ADJUST_1_WIDTH 8U
+#define LPDDR4__PHY_DATA_DC_DQ2_CLK_ADJUST_1__REG DENALI_PHY_389
+#define LPDDR4__PHY_DATA_DC_DQ2_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_389__PHY_DATA_DC_DQ2_CLK_ADJUST_1
+
+#define LPDDR4__DENALI_PHY_390_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_390_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_390__PHY_DATA_DC_DQ3_CLK_ADJUST_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_390__PHY_DATA_DC_DQ3_CLK_ADJUST_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_390__PHY_DATA_DC_DQ3_CLK_ADJUST_1_WIDTH 8U
+#define LPDDR4__PHY_DATA_DC_DQ3_CLK_ADJUST_1__REG DENALI_PHY_390
+#define LPDDR4__PHY_DATA_DC_DQ3_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_390__PHY_DATA_DC_DQ3_CLK_ADJUST_1
+
+#define LPDDR4__DENALI_PHY_390__PHY_DATA_DC_DQ4_CLK_ADJUST_1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_390__PHY_DATA_DC_DQ4_CLK_ADJUST_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_390__PHY_DATA_DC_DQ4_CLK_ADJUST_1_WIDTH 8U
+#define LPDDR4__PHY_DATA_DC_DQ4_CLK_ADJUST_1__REG DENALI_PHY_390
+#define LPDDR4__PHY_DATA_DC_DQ4_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_390__PHY_DATA_DC_DQ4_CLK_ADJUST_1
+
+#define LPDDR4__DENALI_PHY_390__PHY_DATA_DC_DQ5_CLK_ADJUST_1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_390__PHY_DATA_DC_DQ5_CLK_ADJUST_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_390__PHY_DATA_DC_DQ5_CLK_ADJUST_1_WIDTH 8U
+#define LPDDR4__PHY_DATA_DC_DQ5_CLK_ADJUST_1__REG DENALI_PHY_390
+#define LPDDR4__PHY_DATA_DC_DQ5_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_390__PHY_DATA_DC_DQ5_CLK_ADJUST_1
+
+#define LPDDR4__DENALI_PHY_390__PHY_DATA_DC_DQ6_CLK_ADJUST_1_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_390__PHY_DATA_DC_DQ6_CLK_ADJUST_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_390__PHY_DATA_DC_DQ6_CLK_ADJUST_1_WIDTH 8U
+#define LPDDR4__PHY_DATA_DC_DQ6_CLK_ADJUST_1__REG DENALI_PHY_390
+#define LPDDR4__PHY_DATA_DC_DQ6_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_390__PHY_DATA_DC_DQ6_CLK_ADJUST_1
+
+#define LPDDR4__DENALI_PHY_391_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_391_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_391__PHY_DATA_DC_DQ7_CLK_ADJUST_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_391__PHY_DATA_DC_DQ7_CLK_ADJUST_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_391__PHY_DATA_DC_DQ7_CLK_ADJUST_1_WIDTH 8U
+#define LPDDR4__PHY_DATA_DC_DQ7_CLK_ADJUST_1__REG DENALI_PHY_391
+#define LPDDR4__PHY_DATA_DC_DQ7_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_391__PHY_DATA_DC_DQ7_CLK_ADJUST_1
+
+#define LPDDR4__DENALI_PHY_391__PHY_DATA_DC_DM_CLK_ADJUST_1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_391__PHY_DATA_DC_DM_CLK_ADJUST_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_391__PHY_DATA_DC_DM_CLK_ADJUST_1_WIDTH 8U
+#define LPDDR4__PHY_DATA_DC_DM_CLK_ADJUST_1__REG DENALI_PHY_391
+#define LPDDR4__PHY_DATA_DC_DM_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_391__PHY_DATA_DC_DM_CLK_ADJUST_1
+
+#define LPDDR4__DENALI_PHY_391__PHY_DSLICE_PAD_BOOSTPN_SETTING_1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_PHY_391__PHY_DSLICE_PAD_BOOSTPN_SETTING_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_391__PHY_DSLICE_PAD_BOOSTPN_SETTING_1_WIDTH 16U
+#define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_1__REG DENALI_PHY_391
+#define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_1__FLD LPDDR4__DENALI_PHY_391__PHY_DSLICE_PAD_BOOSTPN_SETTING_1
+
+#define LPDDR4__DENALI_PHY_392_READ_MASK 0x0003033FU
+#define LPDDR4__DENALI_PHY_392_WRITE_MASK 0x0003033FU
+#define LPDDR4__DENALI_PHY_392__PHY_DSLICE_PAD_RX_CTLE_SETTING_1_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_392__PHY_DSLICE_PAD_RX_CTLE_SETTING_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_392__PHY_DSLICE_PAD_RX_CTLE_SETTING_1_WIDTH 6U
+#define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_1__REG DENALI_PHY_392
+#define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_1__FLD LPDDR4__DENALI_PHY_392__PHY_DSLICE_PAD_RX_CTLE_SETTING_1
+
+#define LPDDR4__DENALI_PHY_392__PHY_DQ_FFE_1_MASK 0x00000300U
+#define LPDDR4__DENALI_PHY_392__PHY_DQ_FFE_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_392__PHY_DQ_FFE_1_WIDTH 2U
+#define LPDDR4__PHY_DQ_FFE_1__REG DENALI_PHY_392
+#define LPDDR4__PHY_DQ_FFE_1__FLD LPDDR4__DENALI_PHY_392__PHY_DQ_FFE_1
+
+#define LPDDR4__DENALI_PHY_392__PHY_DQS_FFE_1_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_392__PHY_DQS_FFE_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_392__PHY_DQS_FFE_1_WIDTH 2U
+#define LPDDR4__PHY_DQS_FFE_1__REG DENALI_PHY_392
+#define LPDDR4__PHY_DQS_FFE_1__FLD LPDDR4__DENALI_PHY_392__PHY_DQS_FFE_1
+
+#endif /* REG_LPDDR4_DATA_SLICE_1_MACROS_H_ */
diff --git a/drivers/ram/k3-ddrss/am62a/lpddr4_data_slice_2_macros.h b/drivers/ram/k3-ddrss/am62a/lpddr4_data_slice_2_macros.h
new file mode 100644
index 00000000000..b8fb80e08eb
--- /dev/null
+++ b/drivers/ram/k3-ddrss/am62a/lpddr4_data_slice_2_macros.h
@@ -0,0 +1,2292 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef REG_LPDDR4_DATA_SLICE_2_MACROS_H_
+#define REG_LPDDR4_DATA_SLICE_2_MACROS_H_
+
+#define LPDDR4__DENALI_PHY_512_READ_MASK 0x07FF7F07U
+#define LPDDR4__DENALI_PHY_512_WRITE_MASK 0x07FF7F07U
+#define LPDDR4__DENALI_PHY_512__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_2_MASK 0x00000007U
+#define LPDDR4__DENALI_PHY_512__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_512__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_2_WIDTH 3U
+#define LPDDR4__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_2__REG DENALI_PHY_512
+#define LPDDR4__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_2__FLD LPDDR4__DENALI_PHY_512__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_2
+
+#define LPDDR4__DENALI_PHY_512__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_2_MASK 0x00007F00U
+#define LPDDR4__DENALI_PHY_512__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_512__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_2_WIDTH 7U
+#define LPDDR4__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_2__REG DENALI_PHY_512
+#define LPDDR4__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_2__FLD LPDDR4__DENALI_PHY_512__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_2
+
+#define LPDDR4__DENALI_PHY_512__PHY_CLK_WR_BYPASS_SLAVE_DELAY_2_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_512__PHY_CLK_WR_BYPASS_SLAVE_DELAY_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_512__PHY_CLK_WR_BYPASS_SLAVE_DELAY_2_WIDTH 11U
+#define LPDDR4__PHY_CLK_WR_BYPASS_SLAVE_DELAY_2__REG DENALI_PHY_512
+#define LPDDR4__PHY_CLK_WR_BYPASS_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_512__PHY_CLK_WR_BYPASS_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_513_READ_MASK 0x0703FF0FU
+#define LPDDR4__DENALI_PHY_513_WRITE_MASK 0x0703FF0FU
+#define LPDDR4__DENALI_PHY_513__PHY_IO_PAD_DELAY_TIMING_BYPASS_2_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_513__PHY_IO_PAD_DELAY_TIMING_BYPASS_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_513__PHY_IO_PAD_DELAY_TIMING_BYPASS_2_WIDTH 4U
+#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_2__REG DENALI_PHY_513
+#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_2__FLD LPDDR4__DENALI_PHY_513__PHY_IO_PAD_DELAY_TIMING_BYPASS_2
+
+#define LPDDR4__DENALI_PHY_513__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_2_MASK 0x0003FF00U
+#define LPDDR4__DENALI_PHY_513__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_513__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_2_WIDTH 10U
+#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_2__REG DENALI_PHY_513
+#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_2__FLD LPDDR4__DENALI_PHY_513__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_2
+
+#define LPDDR4__DENALI_PHY_513__PHY_WRITE_PATH_LAT_ADD_BYPASS_2_MASK 0x07000000U
+#define LPDDR4__DENALI_PHY_513__PHY_WRITE_PATH_LAT_ADD_BYPASS_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_513__PHY_WRITE_PATH_LAT_ADD_BYPASS_2_WIDTH 3U
+#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_2__REG DENALI_PHY_513
+#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_2__FLD LPDDR4__DENALI_PHY_513__PHY_WRITE_PATH_LAT_ADD_BYPASS_2
+
+#define LPDDR4__DENALI_PHY_514_READ_MASK 0x010303FFU
+#define LPDDR4__DENALI_PHY_514_WRITE_MASK 0x010303FFU
+#define LPDDR4__DENALI_PHY_514__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_514__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_514__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_2_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_2__REG DENALI_PHY_514
+#define LPDDR4__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_514__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_514__PHY_BYPASS_TWO_CYC_PREAMBLE_2_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_514__PHY_BYPASS_TWO_CYC_PREAMBLE_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_514__PHY_BYPASS_TWO_CYC_PREAMBLE_2_WIDTH 2U
+#define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_2__REG DENALI_PHY_514
+#define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_2__FLD LPDDR4__DENALI_PHY_514__PHY_BYPASS_TWO_CYC_PREAMBLE_2
+
+#define LPDDR4__DENALI_PHY_514__PHY_CLK_BYPASS_OVERRIDE_2_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_514__PHY_CLK_BYPASS_OVERRIDE_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_514__PHY_CLK_BYPASS_OVERRIDE_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_514__PHY_CLK_BYPASS_OVERRIDE_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_514__PHY_CLK_BYPASS_OVERRIDE_2_WOSET 0U
+#define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_2__REG DENALI_PHY_514
+#define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_2__FLD LPDDR4__DENALI_PHY_514__PHY_CLK_BYPASS_OVERRIDE_2
+
+#define LPDDR4__DENALI_PHY_515_READ_MASK 0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_515_WRITE_MASK 0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ0_SHIFT_2_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ0_SHIFT_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ0_SHIFT_2_WIDTH 6U
+#define LPDDR4__PHY_SW_WRDQ0_SHIFT_2__REG DENALI_PHY_515
+#define LPDDR4__PHY_SW_WRDQ0_SHIFT_2__FLD LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ0_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ1_SHIFT_2_MASK 0x00003F00U
+#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ1_SHIFT_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ1_SHIFT_2_WIDTH 6U
+#define LPDDR4__PHY_SW_WRDQ1_SHIFT_2__REG DENALI_PHY_515
+#define LPDDR4__PHY_SW_WRDQ1_SHIFT_2__FLD LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ1_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ2_SHIFT_2_MASK 0x003F0000U
+#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ2_SHIFT_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ2_SHIFT_2_WIDTH 6U
+#define LPDDR4__PHY_SW_WRDQ2_SHIFT_2__REG DENALI_PHY_515
+#define LPDDR4__PHY_SW_WRDQ2_SHIFT_2__FLD LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ2_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ3_SHIFT_2_MASK 0x3F000000U
+#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ3_SHIFT_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ3_SHIFT_2_WIDTH 6U
+#define LPDDR4__PHY_SW_WRDQ3_SHIFT_2__REG DENALI_PHY_515
+#define LPDDR4__PHY_SW_WRDQ3_SHIFT_2__FLD LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ3_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_516_READ_MASK 0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_516_WRITE_MASK 0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ4_SHIFT_2_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ4_SHIFT_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ4_SHIFT_2_WIDTH 6U
+#define LPDDR4__PHY_SW_WRDQ4_SHIFT_2__REG DENALI_PHY_516
+#define LPDDR4__PHY_SW_WRDQ4_SHIFT_2__FLD LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ4_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ5_SHIFT_2_MASK 0x00003F00U
+#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ5_SHIFT_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ5_SHIFT_2_WIDTH 6U
+#define LPDDR4__PHY_SW_WRDQ5_SHIFT_2__REG DENALI_PHY_516
+#define LPDDR4__PHY_SW_WRDQ5_SHIFT_2__FLD LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ5_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ6_SHIFT_2_MASK 0x003F0000U
+#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ6_SHIFT_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ6_SHIFT_2_WIDTH 6U
+#define LPDDR4__PHY_SW_WRDQ6_SHIFT_2__REG DENALI_PHY_516
+#define LPDDR4__PHY_SW_WRDQ6_SHIFT_2__FLD LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ6_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ7_SHIFT_2_MASK 0x3F000000U
+#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ7_SHIFT_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ7_SHIFT_2_WIDTH 6U
+#define LPDDR4__PHY_SW_WRDQ7_SHIFT_2__REG DENALI_PHY_516
+#define LPDDR4__PHY_SW_WRDQ7_SHIFT_2__FLD LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ7_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_517_READ_MASK 0x01030F3FU
+#define LPDDR4__DENALI_PHY_517_WRITE_MASK 0x01030F3FU
+#define LPDDR4__DENALI_PHY_517__PHY_SW_WRDM_SHIFT_2_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_517__PHY_SW_WRDM_SHIFT_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_517__PHY_SW_WRDM_SHIFT_2_WIDTH 6U
+#define LPDDR4__PHY_SW_WRDM_SHIFT_2__REG DENALI_PHY_517
+#define LPDDR4__PHY_SW_WRDM_SHIFT_2__FLD LPDDR4__DENALI_PHY_517__PHY_SW_WRDM_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_517__PHY_SW_WRDQS_SHIFT_2_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_517__PHY_SW_WRDQS_SHIFT_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_517__PHY_SW_WRDQS_SHIFT_2_WIDTH 4U
+#define LPDDR4__PHY_SW_WRDQS_SHIFT_2__REG DENALI_PHY_517
+#define LPDDR4__PHY_SW_WRDQS_SHIFT_2__FLD LPDDR4__DENALI_PHY_517__PHY_SW_WRDQS_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_517__PHY_PER_RANK_CS_MAP_2_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_517__PHY_PER_RANK_CS_MAP_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_517__PHY_PER_RANK_CS_MAP_2_WIDTH 2U
+#define LPDDR4__PHY_PER_RANK_CS_MAP_2__REG DENALI_PHY_517
+#define LPDDR4__PHY_PER_RANK_CS_MAP_2__FLD LPDDR4__DENALI_PHY_517__PHY_PER_RANK_CS_MAP_2
+
+#define LPDDR4__DENALI_PHY_517__PHY_PER_CS_TRAINING_MULTICAST_EN_2_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_517__PHY_PER_CS_TRAINING_MULTICAST_EN_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_517__PHY_PER_CS_TRAINING_MULTICAST_EN_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_517__PHY_PER_CS_TRAINING_MULTICAST_EN_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_517__PHY_PER_CS_TRAINING_MULTICAST_EN_2_WOSET 0U
+#define LPDDR4__PHY_PER_CS_TRAINING_MULTICAST_EN_2__REG DENALI_PHY_517
+#define LPDDR4__PHY_PER_CS_TRAINING_MULTICAST_EN_2__FLD LPDDR4__DENALI_PHY_517__PHY_PER_CS_TRAINING_MULTICAST_EN_2
+
+#define LPDDR4__DENALI_PHY_518_READ_MASK 0x1F1F0301U
+#define LPDDR4__DENALI_PHY_518_WRITE_MASK 0x1F1F0301U
+#define LPDDR4__DENALI_PHY_518__PHY_PER_CS_TRAINING_INDEX_2_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_518__PHY_PER_CS_TRAINING_INDEX_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_518__PHY_PER_CS_TRAINING_INDEX_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_518__PHY_PER_CS_TRAINING_INDEX_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_518__PHY_PER_CS_TRAINING_INDEX_2_WOSET 0U
+#define LPDDR4__PHY_PER_CS_TRAINING_INDEX_2__REG DENALI_PHY_518
+#define LPDDR4__PHY_PER_CS_TRAINING_INDEX_2__FLD LPDDR4__DENALI_PHY_518__PHY_PER_CS_TRAINING_INDEX_2
+
+#define LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_2_MASK 0x00000300U
+#define LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_2_WIDTH 2U
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_2__REG DENALI_PHY_518
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_2__FLD LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_2
+
+#define LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_DLY_2_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_DLY_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_DLY_2_WIDTH 5U
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_DLY_2__REG DENALI_PHY_518
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_DLY_2__FLD LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_DLY_2
+
+#define LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_2_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_2_WIDTH 5U
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_2__REG DENALI_PHY_518
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_2__FLD LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_2
+
+#define LPDDR4__DENALI_PHY_519_READ_MASK 0x1F030F0FU
+#define LPDDR4__DENALI_PHY_519_WRITE_MASK 0x1F030F0FU
+#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RPTR_UPDATE_2_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RPTR_UPDATE_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RPTR_UPDATE_2_WIDTH 4U
+#define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_2__REG DENALI_PHY_519
+#define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_2__FLD LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RPTR_UPDATE_2
+
+#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_2_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_2_WIDTH 4U
+#define LPDDR4__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_2__REG DENALI_PHY_519
+#define LPDDR4__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_2__FLD LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_2
+
+#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_2_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_2_WIDTH 2U
+#define LPDDR4__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_2__REG DENALI_PHY_519
+#define LPDDR4__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_2__FLD LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_2
+
+#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_2_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_2_WIDTH 5U
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_2__REG DENALI_PHY_519
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_2__FLD LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_2
+
+#define LPDDR4__DENALI_PHY_520_READ_MASK 0x0101FF03U
+#define LPDDR4__DENALI_PHY_520_WRITE_MASK 0x0101FF03U
+#define LPDDR4__DENALI_PHY_520__PHY_CTRL_LPBK_EN_2_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_520__PHY_CTRL_LPBK_EN_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_520__PHY_CTRL_LPBK_EN_2_WIDTH 2U
+#define LPDDR4__PHY_CTRL_LPBK_EN_2__REG DENALI_PHY_520
+#define LPDDR4__PHY_CTRL_LPBK_EN_2__FLD LPDDR4__DENALI_PHY_520__PHY_CTRL_LPBK_EN_2
+
+#define LPDDR4__DENALI_PHY_520__PHY_LPBK_CONTROL_2_MASK 0x0001FF00U
+#define LPDDR4__DENALI_PHY_520__PHY_LPBK_CONTROL_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_520__PHY_LPBK_CONTROL_2_WIDTH 9U
+#define LPDDR4__PHY_LPBK_CONTROL_2__REG DENALI_PHY_520
+#define LPDDR4__PHY_LPBK_CONTROL_2__FLD LPDDR4__DENALI_PHY_520__PHY_LPBK_CONTROL_2
+
+#define LPDDR4__DENALI_PHY_520__PHY_LPBK_DFX_TIMEOUT_EN_2_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_520__PHY_LPBK_DFX_TIMEOUT_EN_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_520__PHY_LPBK_DFX_TIMEOUT_EN_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_520__PHY_LPBK_DFX_TIMEOUT_EN_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_520__PHY_LPBK_DFX_TIMEOUT_EN_2_WOSET 0U
+#define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_2__REG DENALI_PHY_520
+#define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_2__FLD LPDDR4__DENALI_PHY_520__PHY_LPBK_DFX_TIMEOUT_EN_2
+
+#define LPDDR4__DENALI_PHY_521_READ_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_521_WRITE_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_521__PHY_GATE_DELAY_COMP_DISABLE_2_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_521__PHY_GATE_DELAY_COMP_DISABLE_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_521__PHY_GATE_DELAY_COMP_DISABLE_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_521__PHY_GATE_DELAY_COMP_DISABLE_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_521__PHY_GATE_DELAY_COMP_DISABLE_2_WOSET 0U
+#define LPDDR4__PHY_GATE_DELAY_COMP_DISABLE_2__REG DENALI_PHY_521
+#define LPDDR4__PHY_GATE_DELAY_COMP_DISABLE_2__FLD LPDDR4__DENALI_PHY_521__PHY_GATE_DELAY_COMP_DISABLE_2
+
+#define LPDDR4__DENALI_PHY_522_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_522_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_522__PHY_AUTO_TIMING_MARGIN_CONTROL_2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_522__PHY_AUTO_TIMING_MARGIN_CONTROL_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_522__PHY_AUTO_TIMING_MARGIN_CONTROL_2_WIDTH 32U
+#define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_2__REG DENALI_PHY_522
+#define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_2__FLD LPDDR4__DENALI_PHY_522__PHY_AUTO_TIMING_MARGIN_CONTROL_2
+
+#define LPDDR4__DENALI_PHY_523_READ_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_523_WRITE_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_523__PHY_AUTO_TIMING_MARGIN_OBS_2_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_523__PHY_AUTO_TIMING_MARGIN_OBS_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_523__PHY_AUTO_TIMING_MARGIN_OBS_2_WIDTH 28U
+#define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_2__REG DENALI_PHY_523
+#define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_2__FLD LPDDR4__DENALI_PHY_523__PHY_AUTO_TIMING_MARGIN_OBS_2
+
+#define LPDDR4__DENALI_PHY_524_READ_MASK 0x7F0101FFU
+#define LPDDR4__DENALI_PHY_524_WRITE_MASK 0x7F0101FFU
+#define LPDDR4__DENALI_PHY_524__PHY_DQ_IDLE_2_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_524__PHY_DQ_IDLE_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_524__PHY_DQ_IDLE_2_WIDTH 9U
+#define LPDDR4__PHY_DQ_IDLE_2__REG DENALI_PHY_524
+#define LPDDR4__PHY_DQ_IDLE_2__FLD LPDDR4__DENALI_PHY_524__PHY_DQ_IDLE_2
+
+#define LPDDR4__DENALI_PHY_524__PHY_PDA_MODE_EN_2_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_524__PHY_PDA_MODE_EN_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_524__PHY_PDA_MODE_EN_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_524__PHY_PDA_MODE_EN_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_524__PHY_PDA_MODE_EN_2_WOSET 0U
+#define LPDDR4__PHY_PDA_MODE_EN_2__REG DENALI_PHY_524
+#define LPDDR4__PHY_PDA_MODE_EN_2__FLD LPDDR4__DENALI_PHY_524__PHY_PDA_MODE_EN_2
+
+#define LPDDR4__DENALI_PHY_524__PHY_PRBS_PATTERN_START_2_MASK 0x7F000000U
+#define LPDDR4__DENALI_PHY_524__PHY_PRBS_PATTERN_START_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_524__PHY_PRBS_PATTERN_START_2_WIDTH 7U
+#define LPDDR4__PHY_PRBS_PATTERN_START_2__REG DENALI_PHY_524
+#define LPDDR4__PHY_PRBS_PATTERN_START_2__FLD LPDDR4__DENALI_PHY_524__PHY_PRBS_PATTERN_START_2
+
+#define LPDDR4__DENALI_PHY_525_READ_MASK 0x010101FFU
+#define LPDDR4__DENALI_PHY_525_WRITE_MASK 0x010101FFU
+#define LPDDR4__DENALI_PHY_525__PHY_PRBS_PATTERN_MASK_2_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_525__PHY_PRBS_PATTERN_MASK_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_525__PHY_PRBS_PATTERN_MASK_2_WIDTH 9U
+#define LPDDR4__PHY_PRBS_PATTERN_MASK_2__REG DENALI_PHY_525
+#define LPDDR4__PHY_PRBS_PATTERN_MASK_2__FLD LPDDR4__DENALI_PHY_525__PHY_PRBS_PATTERN_MASK_2
+
+#define LPDDR4__DENALI_PHY_525__PHY_RDLVL_MULTI_PATT_ENABLE_2_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_525__PHY_RDLVL_MULTI_PATT_ENABLE_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_525__PHY_RDLVL_MULTI_PATT_ENABLE_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_525__PHY_RDLVL_MULTI_PATT_ENABLE_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_525__PHY_RDLVL_MULTI_PATT_ENABLE_2_WOSET 0U
+#define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_2__REG DENALI_PHY_525
+#define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_2__FLD LPDDR4__DENALI_PHY_525__PHY_RDLVL_MULTI_PATT_ENABLE_2
+
+#define LPDDR4__DENALI_PHY_525__PHY_RDLVL_MULTI_PATT_RST_DISABLE_2_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_525__PHY_RDLVL_MULTI_PATT_RST_DISABLE_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_525__PHY_RDLVL_MULTI_PATT_RST_DISABLE_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_525__PHY_RDLVL_MULTI_PATT_RST_DISABLE_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_525__PHY_RDLVL_MULTI_PATT_RST_DISABLE_2_WOSET 0U
+#define LPDDR4__PHY_RDLVL_MULTI_PATT_RST_DISABLE_2__REG DENALI_PHY_525
+#define LPDDR4__PHY_RDLVL_MULTI_PATT_RST_DISABLE_2__FLD LPDDR4__DENALI_PHY_525__PHY_RDLVL_MULTI_PATT_RST_DISABLE_2
+
+#define LPDDR4__DENALI_PHY_526_READ_MASK 0x03FF7F3FU
+#define LPDDR4__DENALI_PHY_526_WRITE_MASK 0x03FF7F3FU
+#define LPDDR4__DENALI_PHY_526__PHY_VREF_INITIAL_STEPSIZE_2_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_526__PHY_VREF_INITIAL_STEPSIZE_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_526__PHY_VREF_INITIAL_STEPSIZE_2_WIDTH 6U
+#define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_2__REG DENALI_PHY_526
+#define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_2__FLD LPDDR4__DENALI_PHY_526__PHY_VREF_INITIAL_STEPSIZE_2
+
+#define LPDDR4__DENALI_PHY_526__PHY_VREF_TRAIN_OBS_2_MASK 0x00007F00U
+#define LPDDR4__DENALI_PHY_526__PHY_VREF_TRAIN_OBS_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_526__PHY_VREF_TRAIN_OBS_2_WIDTH 7U
+#define LPDDR4__PHY_VREF_TRAIN_OBS_2__REG DENALI_PHY_526
+#define LPDDR4__PHY_VREF_TRAIN_OBS_2__FLD LPDDR4__DENALI_PHY_526__PHY_VREF_TRAIN_OBS_2
+
+#define LPDDR4__DENALI_PHY_526__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_2_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_526__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_526__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_2_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_2__REG DENALI_PHY_526
+#define LPDDR4__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_526__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_527_READ_MASK 0x01FF000FU
+#define LPDDR4__DENALI_PHY_527_WRITE_MASK 0x01FF000FU
+#define LPDDR4__DENALI_PHY_527__PHY_GATE_ERROR_DELAY_SELECT_2_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_527__PHY_GATE_ERROR_DELAY_SELECT_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_527__PHY_GATE_ERROR_DELAY_SELECT_2_WIDTH 4U
+#define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_2__REG DENALI_PHY_527
+#define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_2__FLD LPDDR4__DENALI_PHY_527__PHY_GATE_ERROR_DELAY_SELECT_2
+
+#define LPDDR4__DENALI_PHY_527__SC_PHY_SNAP_OBS_REGS_2_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_527__SC_PHY_SNAP_OBS_REGS_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_527__SC_PHY_SNAP_OBS_REGS_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_527__SC_PHY_SNAP_OBS_REGS_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_527__SC_PHY_SNAP_OBS_REGS_2_WOSET 0U
+#define LPDDR4__SC_PHY_SNAP_OBS_REGS_2__REG DENALI_PHY_527
+#define LPDDR4__SC_PHY_SNAP_OBS_REGS_2__FLD LPDDR4__DENALI_PHY_527__SC_PHY_SNAP_OBS_REGS_2
+
+#define LPDDR4__DENALI_PHY_527__PHY_GATE_SMPL1_SLAVE_DELAY_2_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_527__PHY_GATE_SMPL1_SLAVE_DELAY_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_527__PHY_GATE_SMPL1_SLAVE_DELAY_2_WIDTH 9U
+#define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_2__REG DENALI_PHY_527
+#define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_527__PHY_GATE_SMPL1_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_528_READ_MASK 0x01FF0701U
+#define LPDDR4__DENALI_PHY_528_WRITE_MASK 0x01FF0701U
+#define LPDDR4__DENALI_PHY_528__PHY_LPDDR_2_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_528__PHY_LPDDR_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_528__PHY_LPDDR_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_528__PHY_LPDDR_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_528__PHY_LPDDR_2_WOSET 0U
+#define LPDDR4__PHY_LPDDR_2__REG DENALI_PHY_528
+#define LPDDR4__PHY_LPDDR_2__FLD LPDDR4__DENALI_PHY_528__PHY_LPDDR_2
+
+#define LPDDR4__DENALI_PHY_528__PHY_MEM_CLASS_2_MASK 0x00000700U
+#define LPDDR4__DENALI_PHY_528__PHY_MEM_CLASS_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_528__PHY_MEM_CLASS_2_WIDTH 3U
+#define LPDDR4__PHY_MEM_CLASS_2__REG DENALI_PHY_528
+#define LPDDR4__PHY_MEM_CLASS_2__FLD LPDDR4__DENALI_PHY_528__PHY_MEM_CLASS_2
+
+#define LPDDR4__DENALI_PHY_528__PHY_GATE_SMPL2_SLAVE_DELAY_2_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_528__PHY_GATE_SMPL2_SLAVE_DELAY_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_528__PHY_GATE_SMPL2_SLAVE_DELAY_2_WIDTH 9U
+#define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_2__REG DENALI_PHY_528
+#define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_528__PHY_GATE_SMPL2_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_529_READ_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_529_WRITE_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_529__ON_FLY_GATE_ADJUST_EN_2_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_529__ON_FLY_GATE_ADJUST_EN_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_529__ON_FLY_GATE_ADJUST_EN_2_WIDTH 2U
+#define LPDDR4__ON_FLY_GATE_ADJUST_EN_2__REG DENALI_PHY_529
+#define LPDDR4__ON_FLY_GATE_ADJUST_EN_2__FLD LPDDR4__DENALI_PHY_529__ON_FLY_GATE_ADJUST_EN_2
+
+#define LPDDR4__DENALI_PHY_530_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_530_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_530__PHY_GATE_TRACKING_OBS_2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_530__PHY_GATE_TRACKING_OBS_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_530__PHY_GATE_TRACKING_OBS_2_WIDTH 32U
+#define LPDDR4__PHY_GATE_TRACKING_OBS_2__REG DENALI_PHY_530
+#define LPDDR4__PHY_GATE_TRACKING_OBS_2__FLD LPDDR4__DENALI_PHY_530__PHY_GATE_TRACKING_OBS_2
+
+#define LPDDR4__DENALI_PHY_531_READ_MASK 0x00000301U
+#define LPDDR4__DENALI_PHY_531_WRITE_MASK 0x00000301U
+#define LPDDR4__DENALI_PHY_531__PHY_DFI40_POLARITY_2_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_531__PHY_DFI40_POLARITY_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_531__PHY_DFI40_POLARITY_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_531__PHY_DFI40_POLARITY_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_531__PHY_DFI40_POLARITY_2_WOSET 0U
+#define LPDDR4__PHY_DFI40_POLARITY_2__REG DENALI_PHY_531
+#define LPDDR4__PHY_DFI40_POLARITY_2__FLD LPDDR4__DENALI_PHY_531__PHY_DFI40_POLARITY_2
+
+#define LPDDR4__DENALI_PHY_531__PHY_LP4_PST_AMBLE_2_MASK 0x00000300U
+#define LPDDR4__DENALI_PHY_531__PHY_LP4_PST_AMBLE_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_531__PHY_LP4_PST_AMBLE_2_WIDTH 2U
+#define LPDDR4__PHY_LP4_PST_AMBLE_2__REG DENALI_PHY_531
+#define LPDDR4__PHY_LP4_PST_AMBLE_2__FLD LPDDR4__DENALI_PHY_531__PHY_LP4_PST_AMBLE_2
+
+#define LPDDR4__DENALI_PHY_532_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_532_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_532__PHY_RDLVL_PATT8_2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_532__PHY_RDLVL_PATT8_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_532__PHY_RDLVL_PATT8_2_WIDTH 32U
+#define LPDDR4__PHY_RDLVL_PATT8_2__REG DENALI_PHY_532
+#define LPDDR4__PHY_RDLVL_PATT8_2__FLD LPDDR4__DENALI_PHY_532__PHY_RDLVL_PATT8_2
+
+#define LPDDR4__DENALI_PHY_533_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_533_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_533__PHY_RDLVL_PATT9_2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_533__PHY_RDLVL_PATT9_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_533__PHY_RDLVL_PATT9_2_WIDTH 32U
+#define LPDDR4__PHY_RDLVL_PATT9_2__REG DENALI_PHY_533
+#define LPDDR4__PHY_RDLVL_PATT9_2__FLD LPDDR4__DENALI_PHY_533__PHY_RDLVL_PATT9_2
+
+#define LPDDR4__DENALI_PHY_534_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_534_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_534__PHY_RDLVL_PATT10_2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_534__PHY_RDLVL_PATT10_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_534__PHY_RDLVL_PATT10_2_WIDTH 32U
+#define LPDDR4__PHY_RDLVL_PATT10_2__REG DENALI_PHY_534
+#define LPDDR4__PHY_RDLVL_PATT10_2__FLD LPDDR4__DENALI_PHY_534__PHY_RDLVL_PATT10_2
+
+#define LPDDR4__DENALI_PHY_535_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_535_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_535__PHY_RDLVL_PATT11_2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_535__PHY_RDLVL_PATT11_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_535__PHY_RDLVL_PATT11_2_WIDTH 32U
+#define LPDDR4__PHY_RDLVL_PATT11_2__REG DENALI_PHY_535
+#define LPDDR4__PHY_RDLVL_PATT11_2__FLD LPDDR4__DENALI_PHY_535__PHY_RDLVL_PATT11_2
+
+#define LPDDR4__DENALI_PHY_536_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_536_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_536__PHY_RDLVL_PATT12_2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_536__PHY_RDLVL_PATT12_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_536__PHY_RDLVL_PATT12_2_WIDTH 32U
+#define LPDDR4__PHY_RDLVL_PATT12_2__REG DENALI_PHY_536
+#define LPDDR4__PHY_RDLVL_PATT12_2__FLD LPDDR4__DENALI_PHY_536__PHY_RDLVL_PATT12_2
+
+#define LPDDR4__DENALI_PHY_537_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_537_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_537__PHY_RDLVL_PATT13_2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_537__PHY_RDLVL_PATT13_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_537__PHY_RDLVL_PATT13_2_WIDTH 32U
+#define LPDDR4__PHY_RDLVL_PATT13_2__REG DENALI_PHY_537
+#define LPDDR4__PHY_RDLVL_PATT13_2__FLD LPDDR4__DENALI_PHY_537__PHY_RDLVL_PATT13_2
+
+#define LPDDR4__DENALI_PHY_538_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_538_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_538__PHY_RDLVL_PATT14_2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_538__PHY_RDLVL_PATT14_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_538__PHY_RDLVL_PATT14_2_WIDTH 32U
+#define LPDDR4__PHY_RDLVL_PATT14_2__REG DENALI_PHY_538
+#define LPDDR4__PHY_RDLVL_PATT14_2__FLD LPDDR4__DENALI_PHY_538__PHY_RDLVL_PATT14_2
+
+#define LPDDR4__DENALI_PHY_539_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_539_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_539__PHY_RDLVL_PATT15_2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_539__PHY_RDLVL_PATT15_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_539__PHY_RDLVL_PATT15_2_WIDTH 32U
+#define LPDDR4__PHY_RDLVL_PATT15_2__REG DENALI_PHY_539
+#define LPDDR4__PHY_RDLVL_PATT15_2__FLD LPDDR4__DENALI_PHY_539__PHY_RDLVL_PATT15_2
+
+#define LPDDR4__DENALI_PHY_540_READ_MASK 0x070F0107U
+#define LPDDR4__DENALI_PHY_540_WRITE_MASK 0x070F0107U
+#define LPDDR4__DENALI_PHY_540__PHY_SLAVE_LOOP_CNT_UPDATE_2_MASK 0x00000007U
+#define LPDDR4__DENALI_PHY_540__PHY_SLAVE_LOOP_CNT_UPDATE_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_540__PHY_SLAVE_LOOP_CNT_UPDATE_2_WIDTH 3U
+#define LPDDR4__PHY_SLAVE_LOOP_CNT_UPDATE_2__REG DENALI_PHY_540
+#define LPDDR4__PHY_SLAVE_LOOP_CNT_UPDATE_2__FLD LPDDR4__DENALI_PHY_540__PHY_SLAVE_LOOP_CNT_UPDATE_2
+
+#define LPDDR4__DENALI_PHY_540__PHY_SW_FIFO_PTR_RST_DISABLE_2_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_540__PHY_SW_FIFO_PTR_RST_DISABLE_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_540__PHY_SW_FIFO_PTR_RST_DISABLE_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_540__PHY_SW_FIFO_PTR_RST_DISABLE_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_540__PHY_SW_FIFO_PTR_RST_DISABLE_2_WOSET 0U
+#define LPDDR4__PHY_SW_FIFO_PTR_RST_DISABLE_2__REG DENALI_PHY_540
+#define LPDDR4__PHY_SW_FIFO_PTR_RST_DISABLE_2__FLD LPDDR4__DENALI_PHY_540__PHY_SW_FIFO_PTR_RST_DISABLE_2
+
+#define LPDDR4__DENALI_PHY_540__PHY_MASTER_DLY_LOCK_OBS_SELECT_2_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_540__PHY_MASTER_DLY_LOCK_OBS_SELECT_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_540__PHY_MASTER_DLY_LOCK_OBS_SELECT_2_WIDTH 4U
+#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_SELECT_2__REG DENALI_PHY_540
+#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_540__PHY_MASTER_DLY_LOCK_OBS_SELECT_2
+
+#define LPDDR4__DENALI_PHY_540__PHY_RDDQ_ENC_OBS_SELECT_2_MASK 0x07000000U
+#define LPDDR4__DENALI_PHY_540__PHY_RDDQ_ENC_OBS_SELECT_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_540__PHY_RDDQ_ENC_OBS_SELECT_2_WIDTH 3U
+#define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_2__REG DENALI_PHY_540
+#define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_540__PHY_RDDQ_ENC_OBS_SELECT_2
+
+#define LPDDR4__DENALI_PHY_541_READ_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_541_WRITE_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_541__PHY_RDDQS_DQ_ENC_OBS_SELECT_2_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_541__PHY_RDDQS_DQ_ENC_OBS_SELECT_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_541__PHY_RDDQS_DQ_ENC_OBS_SELECT_2_WIDTH 4U
+#define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_2__REG DENALI_PHY_541
+#define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_541__PHY_RDDQS_DQ_ENC_OBS_SELECT_2
+
+#define LPDDR4__DENALI_PHY_541__PHY_WR_ENC_OBS_SELECT_2_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_541__PHY_WR_ENC_OBS_SELECT_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_541__PHY_WR_ENC_OBS_SELECT_2_WIDTH 4U
+#define LPDDR4__PHY_WR_ENC_OBS_SELECT_2__REG DENALI_PHY_541
+#define LPDDR4__PHY_WR_ENC_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_541__PHY_WR_ENC_OBS_SELECT_2
+
+#define LPDDR4__DENALI_PHY_541__PHY_WR_SHIFT_OBS_SELECT_2_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_541__PHY_WR_SHIFT_OBS_SELECT_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_541__PHY_WR_SHIFT_OBS_SELECT_2_WIDTH 4U
+#define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_2__REG DENALI_PHY_541
+#define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_541__PHY_WR_SHIFT_OBS_SELECT_2
+
+#define LPDDR4__DENALI_PHY_541__PHY_FIFO_PTR_OBS_SELECT_2_MASK 0x0F000000U
+#define LPDDR4__DENALI_PHY_541__PHY_FIFO_PTR_OBS_SELECT_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_541__PHY_FIFO_PTR_OBS_SELECT_2_WIDTH 4U
+#define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_2__REG DENALI_PHY_541
+#define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_541__PHY_FIFO_PTR_OBS_SELECT_2
+
+#define LPDDR4__DENALI_PHY_542_READ_MASK 0x3F030001U
+#define LPDDR4__DENALI_PHY_542_WRITE_MASK 0x3F030001U
+#define LPDDR4__DENALI_PHY_542__PHY_LVL_DEBUG_MODE_2_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_542__PHY_LVL_DEBUG_MODE_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_542__PHY_LVL_DEBUG_MODE_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_542__PHY_LVL_DEBUG_MODE_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_542__PHY_LVL_DEBUG_MODE_2_WOSET 0U
+#define LPDDR4__PHY_LVL_DEBUG_MODE_2__REG DENALI_PHY_542
+#define LPDDR4__PHY_LVL_DEBUG_MODE_2__FLD LPDDR4__DENALI_PHY_542__PHY_LVL_DEBUG_MODE_2
+
+#define LPDDR4__DENALI_PHY_542__SC_PHY_LVL_DEBUG_CONT_2_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_542__SC_PHY_LVL_DEBUG_CONT_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_542__SC_PHY_LVL_DEBUG_CONT_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_542__SC_PHY_LVL_DEBUG_CONT_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_542__SC_PHY_LVL_DEBUG_CONT_2_WOSET 0U
+#define LPDDR4__SC_PHY_LVL_DEBUG_CONT_2__REG DENALI_PHY_542
+#define LPDDR4__SC_PHY_LVL_DEBUG_CONT_2__FLD LPDDR4__DENALI_PHY_542__SC_PHY_LVL_DEBUG_CONT_2
+
+#define LPDDR4__DENALI_PHY_542__PHY_WRLVL_ALGO_2_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_542__PHY_WRLVL_ALGO_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_542__PHY_WRLVL_ALGO_2_WIDTH 2U
+#define LPDDR4__PHY_WRLVL_ALGO_2__REG DENALI_PHY_542
+#define LPDDR4__PHY_WRLVL_ALGO_2__FLD LPDDR4__DENALI_PHY_542__PHY_WRLVL_ALGO_2
+
+#define LPDDR4__DENALI_PHY_542__PHY_WRLVL_CAPTURE_CNT_2_MASK 0x3F000000U
+#define LPDDR4__DENALI_PHY_542__PHY_WRLVL_CAPTURE_CNT_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_542__PHY_WRLVL_CAPTURE_CNT_2_WIDTH 6U
+#define LPDDR4__PHY_WRLVL_CAPTURE_CNT_2__REG DENALI_PHY_542
+#define LPDDR4__PHY_WRLVL_CAPTURE_CNT_2__FLD LPDDR4__DENALI_PHY_542__PHY_WRLVL_CAPTURE_CNT_2
+
+#define LPDDR4__DENALI_PHY_543_READ_MASK 0x0F3FFF0FU
+#define LPDDR4__DENALI_PHY_543_WRITE_MASK 0x0F3FFF0FU
+#define LPDDR4__DENALI_PHY_543__PHY_WRLVL_UPDT_WAIT_CNT_2_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_543__PHY_WRLVL_UPDT_WAIT_CNT_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_543__PHY_WRLVL_UPDT_WAIT_CNT_2_WIDTH 4U
+#define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_2__REG DENALI_PHY_543
+#define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_2__FLD LPDDR4__DENALI_PHY_543__PHY_WRLVL_UPDT_WAIT_CNT_2
+
+#define LPDDR4__DENALI_PHY_543__PHY_DQ_MASK_2_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_543__PHY_DQ_MASK_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_543__PHY_DQ_MASK_2_WIDTH 8U
+#define LPDDR4__PHY_DQ_MASK_2__REG DENALI_PHY_543
+#define LPDDR4__PHY_DQ_MASK_2__FLD LPDDR4__DENALI_PHY_543__PHY_DQ_MASK_2
+
+#define LPDDR4__DENALI_PHY_543__PHY_GTLVL_CAPTURE_CNT_2_MASK 0x003F0000U
+#define LPDDR4__DENALI_PHY_543__PHY_GTLVL_CAPTURE_CNT_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_543__PHY_GTLVL_CAPTURE_CNT_2_WIDTH 6U
+#define LPDDR4__PHY_GTLVL_CAPTURE_CNT_2__REG DENALI_PHY_543
+#define LPDDR4__PHY_GTLVL_CAPTURE_CNT_2__FLD LPDDR4__DENALI_PHY_543__PHY_GTLVL_CAPTURE_CNT_2
+
+#define LPDDR4__DENALI_PHY_543__PHY_GTLVL_UPDT_WAIT_CNT_2_MASK 0x0F000000U
+#define LPDDR4__DENALI_PHY_543__PHY_GTLVL_UPDT_WAIT_CNT_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_543__PHY_GTLVL_UPDT_WAIT_CNT_2_WIDTH 4U
+#define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_2__REG DENALI_PHY_543
+#define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_2__FLD LPDDR4__DENALI_PHY_543__PHY_GTLVL_UPDT_WAIT_CNT_2
+
+#define LPDDR4__DENALI_PHY_544_READ_MASK 0x1F030F3FU
+#define LPDDR4__DENALI_PHY_544_WRITE_MASK 0x1F030F3FU
+#define LPDDR4__DENALI_PHY_544__PHY_RDLVL_CAPTURE_CNT_2_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_544__PHY_RDLVL_CAPTURE_CNT_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_544__PHY_RDLVL_CAPTURE_CNT_2_WIDTH 6U
+#define LPDDR4__PHY_RDLVL_CAPTURE_CNT_2__REG DENALI_PHY_544
+#define LPDDR4__PHY_RDLVL_CAPTURE_CNT_2__FLD LPDDR4__DENALI_PHY_544__PHY_RDLVL_CAPTURE_CNT_2
+
+#define LPDDR4__DENALI_PHY_544__PHY_RDLVL_UPDT_WAIT_CNT_2_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_544__PHY_RDLVL_UPDT_WAIT_CNT_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_544__PHY_RDLVL_UPDT_WAIT_CNT_2_WIDTH 4U
+#define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_2__REG DENALI_PHY_544
+#define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_2__FLD LPDDR4__DENALI_PHY_544__PHY_RDLVL_UPDT_WAIT_CNT_2
+
+#define LPDDR4__DENALI_PHY_544__PHY_RDLVL_OP_MODE_2_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_544__PHY_RDLVL_OP_MODE_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_544__PHY_RDLVL_OP_MODE_2_WIDTH 2U
+#define LPDDR4__PHY_RDLVL_OP_MODE_2__REG DENALI_PHY_544
+#define LPDDR4__PHY_RDLVL_OP_MODE_2__FLD LPDDR4__DENALI_PHY_544__PHY_RDLVL_OP_MODE_2
+
+#define LPDDR4__DENALI_PHY_544__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_2_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_544__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_544__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_2_WIDTH 5U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_2__REG DENALI_PHY_544
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_544__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_2
+
+#define LPDDR4__DENALI_PHY_545_READ_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_545_WRITE_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_545__PHY_RDLVL_DATA_MASK_2_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_545__PHY_RDLVL_DATA_MASK_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_545__PHY_RDLVL_DATA_MASK_2_WIDTH 8U
+#define LPDDR4__PHY_RDLVL_DATA_MASK_2__REG DENALI_PHY_545
+#define LPDDR4__PHY_RDLVL_DATA_MASK_2__FLD LPDDR4__DENALI_PHY_545__PHY_RDLVL_DATA_MASK_2
+
+#define LPDDR4__DENALI_PHY_545__PHY_RDLVL_DATA_SWIZZLE_2_MASK 0x03FFFF00U
+#define LPDDR4__DENALI_PHY_545__PHY_RDLVL_DATA_SWIZZLE_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_545__PHY_RDLVL_DATA_SWIZZLE_2_WIDTH 18U
+#define LPDDR4__PHY_RDLVL_DATA_SWIZZLE_2__REG DENALI_PHY_545
+#define LPDDR4__PHY_RDLVL_DATA_SWIZZLE_2__FLD LPDDR4__DENALI_PHY_545__PHY_RDLVL_DATA_SWIZZLE_2
+
+#define LPDDR4__DENALI_PHY_546_READ_MASK 0x00073FFFU
+#define LPDDR4__DENALI_PHY_546_WRITE_MASK 0x00073FFFU
+#define LPDDR4__DENALI_PHY_546__PHY_WDQLVL_CLK_JITTER_TOLERANCE_2_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_546__PHY_WDQLVL_CLK_JITTER_TOLERANCE_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_546__PHY_WDQLVL_CLK_JITTER_TOLERANCE_2_WIDTH 8U
+#define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_2__REG DENALI_PHY_546
+#define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_2__FLD LPDDR4__DENALI_PHY_546__PHY_WDQLVL_CLK_JITTER_TOLERANCE_2
+
+#define LPDDR4__DENALI_PHY_546__PHY_WDQLVL_BURST_CNT_2_MASK 0x00003F00U
+#define LPDDR4__DENALI_PHY_546__PHY_WDQLVL_BURST_CNT_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_546__PHY_WDQLVL_BURST_CNT_2_WIDTH 6U
+#define LPDDR4__PHY_WDQLVL_BURST_CNT_2__REG DENALI_PHY_546
+#define LPDDR4__PHY_WDQLVL_BURST_CNT_2__FLD LPDDR4__DENALI_PHY_546__PHY_WDQLVL_BURST_CNT_2
+
+#define LPDDR4__DENALI_PHY_546__PHY_WDQLVL_PATT_2_MASK 0x00070000U
+#define LPDDR4__DENALI_PHY_546__PHY_WDQLVL_PATT_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_546__PHY_WDQLVL_PATT_2_WIDTH 3U
+#define LPDDR4__PHY_WDQLVL_PATT_2__REG DENALI_PHY_546
+#define LPDDR4__PHY_WDQLVL_PATT_2__FLD LPDDR4__DENALI_PHY_546__PHY_WDQLVL_PATT_2
+
+#define LPDDR4__DENALI_PHY_547_READ_MASK 0x0F0F07FFU
+#define LPDDR4__DENALI_PHY_547_WRITE_MASK 0x0F0F07FFU
+#define LPDDR4__DENALI_PHY_547__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_2_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_547__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_547__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_2_WIDTH 11U
+#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_2__REG DENALI_PHY_547
+#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_2__FLD LPDDR4__DENALI_PHY_547__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_2
+
+#define LPDDR4__DENALI_PHY_547__PHY_WDQLVL_UPDT_WAIT_CNT_2_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_547__PHY_WDQLVL_UPDT_WAIT_CNT_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_547__PHY_WDQLVL_UPDT_WAIT_CNT_2_WIDTH 4U
+#define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_2__REG DENALI_PHY_547
+#define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_2__FLD LPDDR4__DENALI_PHY_547__PHY_WDQLVL_UPDT_WAIT_CNT_2
+
+#define LPDDR4__DENALI_PHY_547__PHY_WDQLVL_DQDM_OBS_SELECT_2_MASK 0x0F000000U
+#define LPDDR4__DENALI_PHY_547__PHY_WDQLVL_DQDM_OBS_SELECT_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_547__PHY_WDQLVL_DQDM_OBS_SELECT_2_WIDTH 4U
+#define LPDDR4__PHY_WDQLVL_DQDM_OBS_SELECT_2__REG DENALI_PHY_547
+#define LPDDR4__PHY_WDQLVL_DQDM_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_547__PHY_WDQLVL_DQDM_OBS_SELECT_2
+
+#define LPDDR4__DENALI_PHY_548_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_548_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_548__PHY_WDQLVL_PERIODIC_OBS_SELECT_2_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_548__PHY_WDQLVL_PERIODIC_OBS_SELECT_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_548__PHY_WDQLVL_PERIODIC_OBS_SELECT_2_WIDTH 8U
+#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_SELECT_2__REG DENALI_PHY_548
+#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_548__PHY_WDQLVL_PERIODIC_OBS_SELECT_2
+
+#define LPDDR4__DENALI_PHY_548__PHY_WDQLVL_DQ_SLV_DELTA_2_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_548__PHY_WDQLVL_DQ_SLV_DELTA_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_548__PHY_WDQLVL_DQ_SLV_DELTA_2_WIDTH 8U
+#define LPDDR4__PHY_WDQLVL_DQ_SLV_DELTA_2__REG DENALI_PHY_548
+#define LPDDR4__PHY_WDQLVL_DQ_SLV_DELTA_2__FLD LPDDR4__DENALI_PHY_548__PHY_WDQLVL_DQ_SLV_DELTA_2
+
+#define LPDDR4__DENALI_PHY_548__PHY_WDQLVL_DM_DLY_STEP_2_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_548__PHY_WDQLVL_DM_DLY_STEP_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_548__PHY_WDQLVL_DM_DLY_STEP_2_WIDTH 4U
+#define LPDDR4__PHY_WDQLVL_DM_DLY_STEP_2__REG DENALI_PHY_548
+#define LPDDR4__PHY_WDQLVL_DM_DLY_STEP_2__FLD LPDDR4__DENALI_PHY_548__PHY_WDQLVL_DM_DLY_STEP_2
+
+#define LPDDR4__DENALI_PHY_548__SC_PHY_WDQLVL_CLR_PREV_RESULTS_2_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_548__SC_PHY_WDQLVL_CLR_PREV_RESULTS_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_548__SC_PHY_WDQLVL_CLR_PREV_RESULTS_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_548__SC_PHY_WDQLVL_CLR_PREV_RESULTS_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_548__SC_PHY_WDQLVL_CLR_PREV_RESULTS_2_WOSET 0U
+#define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_2__REG DENALI_PHY_548
+#define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_2__FLD LPDDR4__DENALI_PHY_548__SC_PHY_WDQLVL_CLR_PREV_RESULTS_2
+
+#define LPDDR4__DENALI_PHY_549_READ_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_549_WRITE_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_549__PHY_WDQLVL_DATADM_MASK_2_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_549__PHY_WDQLVL_DATADM_MASK_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_549__PHY_WDQLVL_DATADM_MASK_2_WIDTH 9U
+#define LPDDR4__PHY_WDQLVL_DATADM_MASK_2__REG DENALI_PHY_549
+#define LPDDR4__PHY_WDQLVL_DATADM_MASK_2__FLD LPDDR4__DENALI_PHY_549__PHY_WDQLVL_DATADM_MASK_2
+
+#define LPDDR4__DENALI_PHY_550_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_550_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_550__PHY_USER_PATT0_2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_550__PHY_USER_PATT0_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_550__PHY_USER_PATT0_2_WIDTH 32U
+#define LPDDR4__PHY_USER_PATT0_2__REG DENALI_PHY_550
+#define LPDDR4__PHY_USER_PATT0_2__FLD LPDDR4__DENALI_PHY_550__PHY_USER_PATT0_2
+
+#define LPDDR4__DENALI_PHY_551_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_551_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_551__PHY_USER_PATT1_2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_551__PHY_USER_PATT1_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_551__PHY_USER_PATT1_2_WIDTH 32U
+#define LPDDR4__PHY_USER_PATT1_2__REG DENALI_PHY_551
+#define LPDDR4__PHY_USER_PATT1_2__FLD LPDDR4__DENALI_PHY_551__PHY_USER_PATT1_2
+
+#define LPDDR4__DENALI_PHY_552_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_552_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_552__PHY_USER_PATT2_2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_552__PHY_USER_PATT2_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_552__PHY_USER_PATT2_2_WIDTH 32U
+#define LPDDR4__PHY_USER_PATT2_2__REG DENALI_PHY_552
+#define LPDDR4__PHY_USER_PATT2_2__FLD LPDDR4__DENALI_PHY_552__PHY_USER_PATT2_2
+
+#define LPDDR4__DENALI_PHY_553_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_553_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_553__PHY_USER_PATT3_2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_553__PHY_USER_PATT3_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_553__PHY_USER_PATT3_2_WIDTH 32U
+#define LPDDR4__PHY_USER_PATT3_2__REG DENALI_PHY_553
+#define LPDDR4__PHY_USER_PATT3_2__FLD LPDDR4__DENALI_PHY_553__PHY_USER_PATT3_2
+
+#define LPDDR4__DENALI_PHY_554_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PHY_554_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PHY_554__PHY_USER_PATT4_2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_554__PHY_USER_PATT4_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_554__PHY_USER_PATT4_2_WIDTH 16U
+#define LPDDR4__PHY_USER_PATT4_2__REG DENALI_PHY_554
+#define LPDDR4__PHY_USER_PATT4_2__FLD LPDDR4__DENALI_PHY_554__PHY_USER_PATT4_2
+
+#define LPDDR4__DENALI_PHY_554__PHY_NTP_MULT_TRAIN_2_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_554__PHY_NTP_MULT_TRAIN_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_554__PHY_NTP_MULT_TRAIN_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_554__PHY_NTP_MULT_TRAIN_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_554__PHY_NTP_MULT_TRAIN_2_WOSET 0U
+#define LPDDR4__PHY_NTP_MULT_TRAIN_2__REG DENALI_PHY_554
+#define LPDDR4__PHY_NTP_MULT_TRAIN_2__FLD LPDDR4__DENALI_PHY_554__PHY_NTP_MULT_TRAIN_2
+
+#define LPDDR4__DENALI_PHY_555_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_555_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_555__PHY_NTP_EARLY_THRESHOLD_2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_555__PHY_NTP_EARLY_THRESHOLD_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_555__PHY_NTP_EARLY_THRESHOLD_2_WIDTH 10U
+#define LPDDR4__PHY_NTP_EARLY_THRESHOLD_2__REG DENALI_PHY_555
+#define LPDDR4__PHY_NTP_EARLY_THRESHOLD_2__FLD LPDDR4__DENALI_PHY_555__PHY_NTP_EARLY_THRESHOLD_2
+
+#define LPDDR4__DENALI_PHY_555__PHY_NTP_PERIOD_THRESHOLD_2_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_555__PHY_NTP_PERIOD_THRESHOLD_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_555__PHY_NTP_PERIOD_THRESHOLD_2_WIDTH 10U
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_2__REG DENALI_PHY_555
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_2__FLD LPDDR4__DENALI_PHY_555__PHY_NTP_PERIOD_THRESHOLD_2
+
+#define LPDDR4__DENALI_PHY_556_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_556_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_556__PHY_NTP_PERIOD_THRESHOLD_MIN_2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_556__PHY_NTP_PERIOD_THRESHOLD_MIN_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_556__PHY_NTP_PERIOD_THRESHOLD_MIN_2_WIDTH 10U
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MIN_2__REG DENALI_PHY_556
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MIN_2__FLD LPDDR4__DENALI_PHY_556__PHY_NTP_PERIOD_THRESHOLD_MIN_2
+
+#define LPDDR4__DENALI_PHY_556__PHY_NTP_PERIOD_THRESHOLD_MAX_2_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_556__PHY_NTP_PERIOD_THRESHOLD_MAX_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_556__PHY_NTP_PERIOD_THRESHOLD_MAX_2_WIDTH 10U
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_2__REG DENALI_PHY_556
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_2__FLD LPDDR4__DENALI_PHY_556__PHY_NTP_PERIOD_THRESHOLD_MAX_2
+
+#define LPDDR4__DENALI_PHY_557_READ_MASK 0x00FF0001U
+#define LPDDR4__DENALI_PHY_557_WRITE_MASK 0x00FF0001U
+#define LPDDR4__DENALI_PHY_557__PHY_CALVL_VREF_DRIVING_SLICE_2_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_557__PHY_CALVL_VREF_DRIVING_SLICE_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_557__PHY_CALVL_VREF_DRIVING_SLICE_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_557__PHY_CALVL_VREF_DRIVING_SLICE_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_557__PHY_CALVL_VREF_DRIVING_SLICE_2_WOSET 0U
+#define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_2__REG DENALI_PHY_557
+#define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_2__FLD LPDDR4__DENALI_PHY_557__PHY_CALVL_VREF_DRIVING_SLICE_2
+
+#define LPDDR4__DENALI_PHY_557__SC_PHY_MANUAL_CLEAR_2_MASK 0x00003F00U
+#define LPDDR4__DENALI_PHY_557__SC_PHY_MANUAL_CLEAR_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_557__SC_PHY_MANUAL_CLEAR_2_WIDTH 6U
+#define LPDDR4__SC_PHY_MANUAL_CLEAR_2__REG DENALI_PHY_557
+#define LPDDR4__SC_PHY_MANUAL_CLEAR_2__FLD LPDDR4__DENALI_PHY_557__SC_PHY_MANUAL_CLEAR_2
+
+#define LPDDR4__DENALI_PHY_557__PHY_FIFO_PTR_OBS_2_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_557__PHY_FIFO_PTR_OBS_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_557__PHY_FIFO_PTR_OBS_2_WIDTH 8U
+#define LPDDR4__PHY_FIFO_PTR_OBS_2__REG DENALI_PHY_557
+#define LPDDR4__PHY_FIFO_PTR_OBS_2__FLD LPDDR4__DENALI_PHY_557__PHY_FIFO_PTR_OBS_2
+
+#define LPDDR4__DENALI_PHY_558_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_558_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_558__PHY_LPBK_RESULT_OBS_2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_558__PHY_LPBK_RESULT_OBS_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_558__PHY_LPBK_RESULT_OBS_2_WIDTH 32U
+#define LPDDR4__PHY_LPBK_RESULT_OBS_2__REG DENALI_PHY_558
+#define LPDDR4__PHY_LPBK_RESULT_OBS_2__FLD LPDDR4__DENALI_PHY_558__PHY_LPBK_RESULT_OBS_2
+
+#define LPDDR4__DENALI_PHY_559_READ_MASK 0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_559_WRITE_MASK 0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_559__PHY_LPBK_ERROR_COUNT_OBS_2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_559__PHY_LPBK_ERROR_COUNT_OBS_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_559__PHY_LPBK_ERROR_COUNT_OBS_2_WIDTH 16U
+#define LPDDR4__PHY_LPBK_ERROR_COUNT_OBS_2__REG DENALI_PHY_559
+#define LPDDR4__PHY_LPBK_ERROR_COUNT_OBS_2__FLD LPDDR4__DENALI_PHY_559__PHY_LPBK_ERROR_COUNT_OBS_2
+
+#define LPDDR4__DENALI_PHY_559__PHY_MASTER_DLY_LOCK_OBS_2_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_559__PHY_MASTER_DLY_LOCK_OBS_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_559__PHY_MASTER_DLY_LOCK_OBS_2_WIDTH 11U
+#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_2__REG DENALI_PHY_559
+#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_2__FLD LPDDR4__DENALI_PHY_559__PHY_MASTER_DLY_LOCK_OBS_2
+
+#define LPDDR4__DENALI_PHY_560_READ_MASK 0xFFFF7F7FU
+#define LPDDR4__DENALI_PHY_560_WRITE_MASK 0xFFFF7F7FU
+#define LPDDR4__DENALI_PHY_560__PHY_RDDQ_SLV_DLY_ENC_OBS_2_MASK 0x0000007FU
+#define LPDDR4__DENALI_PHY_560__PHY_RDDQ_SLV_DLY_ENC_OBS_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_560__PHY_RDDQ_SLV_DLY_ENC_OBS_2_WIDTH 7U
+#define LPDDR4__PHY_RDDQ_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_560
+#define LPDDR4__PHY_RDDQ_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_560__PHY_RDDQ_SLV_DLY_ENC_OBS_2
+
+#define LPDDR4__DENALI_PHY_560__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_2_MASK 0x00007F00U
+#define LPDDR4__DENALI_PHY_560__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_560__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_2_WIDTH 7U
+#define LPDDR4__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_560
+#define LPDDR4__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_560__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_2
+
+#define LPDDR4__DENALI_PHY_560__PHY_MEAS_DLY_STEP_VALUE_2_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_560__PHY_MEAS_DLY_STEP_VALUE_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_560__PHY_MEAS_DLY_STEP_VALUE_2_WIDTH 8U
+#define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_2__REG DENALI_PHY_560
+#define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_2__FLD LPDDR4__DENALI_PHY_560__PHY_MEAS_DLY_STEP_VALUE_2
+
+#define LPDDR4__DENALI_PHY_560__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_2_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_560__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_560__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_2_WIDTH 8U
+#define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_560
+#define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_560__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_2
+
+#define LPDDR4__DENALI_PHY_561_READ_MASK 0x7F07FFFFU
+#define LPDDR4__DENALI_PHY_561_WRITE_MASK 0x7F07FFFFU
+#define LPDDR4__DENALI_PHY_561__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_2_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_561__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_561__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_2_WIDTH 8U
+#define LPDDR4__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_561
+#define LPDDR4__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_561__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_2
+
+#define LPDDR4__DENALI_PHY_561__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_2_MASK 0x0007FF00U
+#define LPDDR4__DENALI_PHY_561__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_561__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_2_WIDTH 11U
+#define LPDDR4__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_561
+#define LPDDR4__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_561__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_2
+
+#define LPDDR4__DENALI_PHY_561__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_2_MASK 0x7F000000U
+#define LPDDR4__DENALI_PHY_561__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_561__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_2_WIDTH 7U
+#define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_561
+#define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_561__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_2
+
+#define LPDDR4__DENALI_PHY_562_READ_MASK 0x0007FFFFU
+#define LPDDR4__DENALI_PHY_562_WRITE_MASK 0x0007FFFFU
+#define LPDDR4__DENALI_PHY_562__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_2_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_562__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_562__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_2_WIDTH 8U
+#define LPDDR4__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_562
+#define LPDDR4__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_562__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_2
+
+#define LPDDR4__DENALI_PHY_562__PHY_WR_ADDER_SLV_DLY_ENC_OBS_2_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_562__PHY_WR_ADDER_SLV_DLY_ENC_OBS_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_562__PHY_WR_ADDER_SLV_DLY_ENC_OBS_2_WIDTH 8U
+#define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_562
+#define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_562__PHY_WR_ADDER_SLV_DLY_ENC_OBS_2
+
+#define LPDDR4__DENALI_PHY_562__PHY_WR_SHIFT_OBS_2_MASK 0x00070000U
+#define LPDDR4__DENALI_PHY_562__PHY_WR_SHIFT_OBS_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_562__PHY_WR_SHIFT_OBS_2_WIDTH 3U
+#define LPDDR4__PHY_WR_SHIFT_OBS_2__REG DENALI_PHY_562
+#define LPDDR4__PHY_WR_SHIFT_OBS_2__FLD LPDDR4__DENALI_PHY_562__PHY_WR_SHIFT_OBS_2
+
+#define LPDDR4__DENALI_PHY_563_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_563_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_563__PHY_WRLVL_HARD0_DELAY_OBS_2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_563__PHY_WRLVL_HARD0_DELAY_OBS_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_563__PHY_WRLVL_HARD0_DELAY_OBS_2_WIDTH 10U
+#define LPDDR4__PHY_WRLVL_HARD0_DELAY_OBS_2__REG DENALI_PHY_563
+#define LPDDR4__PHY_WRLVL_HARD0_DELAY_OBS_2__FLD LPDDR4__DENALI_PHY_563__PHY_WRLVL_HARD0_DELAY_OBS_2
+
+#define LPDDR4__DENALI_PHY_563__PHY_WRLVL_HARD1_DELAY_OBS_2_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_563__PHY_WRLVL_HARD1_DELAY_OBS_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_563__PHY_WRLVL_HARD1_DELAY_OBS_2_WIDTH 10U
+#define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_2__REG DENALI_PHY_563
+#define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_2__FLD LPDDR4__DENALI_PHY_563__PHY_WRLVL_HARD1_DELAY_OBS_2
+
+#define LPDDR4__DENALI_PHY_564_READ_MASK 0x001FFFFFU
+#define LPDDR4__DENALI_PHY_564_WRITE_MASK 0x001FFFFFU
+#define LPDDR4__DENALI_PHY_564__PHY_WRLVL_STATUS_OBS_2_MASK 0x001FFFFFU
+#define LPDDR4__DENALI_PHY_564__PHY_WRLVL_STATUS_OBS_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_564__PHY_WRLVL_STATUS_OBS_2_WIDTH 21U
+#define LPDDR4__PHY_WRLVL_STATUS_OBS_2__REG DENALI_PHY_564
+#define LPDDR4__PHY_WRLVL_STATUS_OBS_2__FLD LPDDR4__DENALI_PHY_564__PHY_WRLVL_STATUS_OBS_2
+
+#define LPDDR4__DENALI_PHY_565_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_565_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_565__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_565__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_565__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_2_WIDTH 10U
+#define LPDDR4__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_565
+#define LPDDR4__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_565__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_2
+
+#define LPDDR4__DENALI_PHY_565__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_2_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_565__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_565__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_2_WIDTH 10U
+#define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_565
+#define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_565__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_2
+
+#define LPDDR4__DENALI_PHY_566_READ_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_566_WRITE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_566__PHY_WRLVL_ERROR_OBS_2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_566__PHY_WRLVL_ERROR_OBS_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_566__PHY_WRLVL_ERROR_OBS_2_WIDTH 16U
+#define LPDDR4__PHY_WRLVL_ERROR_OBS_2__REG DENALI_PHY_566
+#define LPDDR4__PHY_WRLVL_ERROR_OBS_2__FLD LPDDR4__DENALI_PHY_566__PHY_WRLVL_ERROR_OBS_2
+
+#define LPDDR4__DENALI_PHY_566__PHY_GTLVL_HARD0_DELAY_OBS_2_MASK 0x3FFF0000U
+#define LPDDR4__DENALI_PHY_566__PHY_GTLVL_HARD0_DELAY_OBS_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_566__PHY_GTLVL_HARD0_DELAY_OBS_2_WIDTH 14U
+#define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_2__REG DENALI_PHY_566
+#define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_2__FLD LPDDR4__DENALI_PHY_566__PHY_GTLVL_HARD0_DELAY_OBS_2
+
+#define LPDDR4__DENALI_PHY_567_READ_MASK 0x00003FFFU
+#define LPDDR4__DENALI_PHY_567_WRITE_MASK 0x00003FFFU
+#define LPDDR4__DENALI_PHY_567__PHY_GTLVL_HARD1_DELAY_OBS_2_MASK 0x00003FFFU
+#define LPDDR4__DENALI_PHY_567__PHY_GTLVL_HARD1_DELAY_OBS_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_567__PHY_GTLVL_HARD1_DELAY_OBS_2_WIDTH 14U
+#define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_2__REG DENALI_PHY_567
+#define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_2__FLD LPDDR4__DENALI_PHY_567__PHY_GTLVL_HARD1_DELAY_OBS_2
+
+#define LPDDR4__DENALI_PHY_568_READ_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_568_WRITE_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_568__PHY_GTLVL_STATUS_OBS_2_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_568__PHY_GTLVL_STATUS_OBS_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_568__PHY_GTLVL_STATUS_OBS_2_WIDTH 18U
+#define LPDDR4__PHY_GTLVL_STATUS_OBS_2__REG DENALI_PHY_568
+#define LPDDR4__PHY_GTLVL_STATUS_OBS_2__FLD LPDDR4__DENALI_PHY_568__PHY_GTLVL_STATUS_OBS_2
+
+#define LPDDR4__DENALI_PHY_569_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_569_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_569__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_569__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_569__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_2_WIDTH 10U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_2__REG DENALI_PHY_569
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_2__FLD LPDDR4__DENALI_PHY_569__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_2
+
+#define LPDDR4__DENALI_PHY_569__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_2_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_569__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_569__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_2_WIDTH 10U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_2__REG DENALI_PHY_569
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_2__FLD LPDDR4__DENALI_PHY_569__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_2
+
+#define LPDDR4__DENALI_PHY_570_READ_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_570_WRITE_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_570__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_2_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_570__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_570__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_2_WIDTH 2U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_2__REG DENALI_PHY_570
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_2__FLD LPDDR4__DENALI_PHY_570__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_2
+
+#define LPDDR4__DENALI_PHY_571_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_571_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_571__PHY_RDLVL_STATUS_OBS_2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_571__PHY_RDLVL_STATUS_OBS_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_571__PHY_RDLVL_STATUS_OBS_2_WIDTH 32U
+#define LPDDR4__PHY_RDLVL_STATUS_OBS_2__REG DENALI_PHY_571
+#define LPDDR4__PHY_RDLVL_STATUS_OBS_2__FLD LPDDR4__DENALI_PHY_571__PHY_RDLVL_STATUS_OBS_2
+
+#define LPDDR4__DENALI_PHY_572_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_572_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_572__PHY_WDQLVL_DQDM_LE_DLY_OBS_2_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_572__PHY_WDQLVL_DQDM_LE_DLY_OBS_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_572__PHY_WDQLVL_DQDM_LE_DLY_OBS_2_WIDTH 11U
+#define LPDDR4__PHY_WDQLVL_DQDM_LE_DLY_OBS_2__REG DENALI_PHY_572
+#define LPDDR4__PHY_WDQLVL_DQDM_LE_DLY_OBS_2__FLD LPDDR4__DENALI_PHY_572__PHY_WDQLVL_DQDM_LE_DLY_OBS_2
+
+#define LPDDR4__DENALI_PHY_572__PHY_WDQLVL_DQDM_TE_DLY_OBS_2_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_572__PHY_WDQLVL_DQDM_TE_DLY_OBS_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_572__PHY_WDQLVL_DQDM_TE_DLY_OBS_2_WIDTH 11U
+#define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_2__REG DENALI_PHY_572
+#define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_2__FLD LPDDR4__DENALI_PHY_572__PHY_WDQLVL_DQDM_TE_DLY_OBS_2
+
+#define LPDDR4__DENALI_PHY_573_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_573_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_573__PHY_WDQLVL_STATUS_OBS_2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_573__PHY_WDQLVL_STATUS_OBS_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_573__PHY_WDQLVL_STATUS_OBS_2_WIDTH 32U
+#define LPDDR4__PHY_WDQLVL_STATUS_OBS_2__REG DENALI_PHY_573
+#define LPDDR4__PHY_WDQLVL_STATUS_OBS_2__FLD LPDDR4__DENALI_PHY_573__PHY_WDQLVL_STATUS_OBS_2
+
+#define LPDDR4__DENALI_PHY_574_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_574_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_574__PHY_WDQLVL_PERIODIC_OBS_2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_574__PHY_WDQLVL_PERIODIC_OBS_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_574__PHY_WDQLVL_PERIODIC_OBS_2_WIDTH 32U
+#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_2__REG DENALI_PHY_574
+#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_2__FLD LPDDR4__DENALI_PHY_574__PHY_WDQLVL_PERIODIC_OBS_2
+
+#define LPDDR4__DENALI_PHY_575_READ_MASK 0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_575_WRITE_MASK 0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_575__PHY_DDL_MODE_2_MASK 0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_575__PHY_DDL_MODE_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_575__PHY_DDL_MODE_2_WIDTH 31U
+#define LPDDR4__PHY_DDL_MODE_2__REG DENALI_PHY_575
+#define LPDDR4__PHY_DDL_MODE_2__FLD LPDDR4__DENALI_PHY_575__PHY_DDL_MODE_2
+
+#define LPDDR4__DENALI_PHY_576_READ_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_576_WRITE_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_576__PHY_DDL_MASK_2_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_576__PHY_DDL_MASK_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_576__PHY_DDL_MASK_2_WIDTH 6U
+#define LPDDR4__PHY_DDL_MASK_2__REG DENALI_PHY_576
+#define LPDDR4__PHY_DDL_MASK_2__FLD LPDDR4__DENALI_PHY_576__PHY_DDL_MASK_2
+
+#define LPDDR4__DENALI_PHY_577_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_577_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_577__PHY_DDL_TEST_OBS_2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_577__PHY_DDL_TEST_OBS_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_577__PHY_DDL_TEST_OBS_2_WIDTH 32U
+#define LPDDR4__PHY_DDL_TEST_OBS_2__REG DENALI_PHY_577
+#define LPDDR4__PHY_DDL_TEST_OBS_2__FLD LPDDR4__DENALI_PHY_577__PHY_DDL_TEST_OBS_2
+
+#define LPDDR4__DENALI_PHY_578_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_578_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_578__PHY_DDL_TEST_MSTR_DLY_OBS_2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_578__PHY_DDL_TEST_MSTR_DLY_OBS_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_578__PHY_DDL_TEST_MSTR_DLY_OBS_2_WIDTH 32U
+#define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_2__REG DENALI_PHY_578
+#define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_2__FLD LPDDR4__DENALI_PHY_578__PHY_DDL_TEST_MSTR_DLY_OBS_2
+
+#define LPDDR4__DENALI_PHY_579_READ_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_579_WRITE_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_579__PHY_DDL_TRACK_UPD_THRESHOLD_2_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_579__PHY_DDL_TRACK_UPD_THRESHOLD_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_579__PHY_DDL_TRACK_UPD_THRESHOLD_2_WIDTH 8U
+#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_2__REG DENALI_PHY_579
+#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_2__FLD LPDDR4__DENALI_PHY_579__PHY_DDL_TRACK_UPD_THRESHOLD_2
+
+#define LPDDR4__DENALI_PHY_579__PHY_LP4_WDQS_OE_EXTEND_2_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_579__PHY_LP4_WDQS_OE_EXTEND_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_579__PHY_LP4_WDQS_OE_EXTEND_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_579__PHY_LP4_WDQS_OE_EXTEND_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_579__PHY_LP4_WDQS_OE_EXTEND_2_WOSET 0U
+#define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_2__REG DENALI_PHY_579
+#define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_2__FLD LPDDR4__DENALI_PHY_579__PHY_LP4_WDQS_OE_EXTEND_2
+
+#define LPDDR4__DENALI_PHY_579__PHY_RX_CAL_DQ0_2_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_579__PHY_RX_CAL_DQ0_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_579__PHY_RX_CAL_DQ0_2_WIDTH 9U
+#define LPDDR4__PHY_RX_CAL_DQ0_2__REG DENALI_PHY_579
+#define LPDDR4__PHY_RX_CAL_DQ0_2__FLD LPDDR4__DENALI_PHY_579__PHY_RX_CAL_DQ0_2
+
+#define LPDDR4__DENALI_PHY_580_READ_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_580_WRITE_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ1_2_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ1_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ1_2_WIDTH 9U
+#define LPDDR4__PHY_RX_CAL_DQ1_2__REG DENALI_PHY_580
+#define LPDDR4__PHY_RX_CAL_DQ1_2__FLD LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ1_2
+
+#define LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ2_2_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ2_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ2_2_WIDTH 9U
+#define LPDDR4__PHY_RX_CAL_DQ2_2__REG DENALI_PHY_580
+#define LPDDR4__PHY_RX_CAL_DQ2_2__FLD LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ2_2
+
+#define LPDDR4__DENALI_PHY_581_READ_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_581_WRITE_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ3_2_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ3_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ3_2_WIDTH 9U
+#define LPDDR4__PHY_RX_CAL_DQ3_2__REG DENALI_PHY_581
+#define LPDDR4__PHY_RX_CAL_DQ3_2__FLD LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ3_2
+
+#define LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ4_2_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ4_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ4_2_WIDTH 9U
+#define LPDDR4__PHY_RX_CAL_DQ4_2__REG DENALI_PHY_581
+#define LPDDR4__PHY_RX_CAL_DQ4_2__FLD LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ4_2
+
+#define LPDDR4__DENALI_PHY_582_READ_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_582_WRITE_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ5_2_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ5_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ5_2_WIDTH 9U
+#define LPDDR4__PHY_RX_CAL_DQ5_2__REG DENALI_PHY_582
+#define LPDDR4__PHY_RX_CAL_DQ5_2__FLD LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ5_2
+
+#define LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ6_2_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ6_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ6_2_WIDTH 9U
+#define LPDDR4__PHY_RX_CAL_DQ6_2__REG DENALI_PHY_582
+#define LPDDR4__PHY_RX_CAL_DQ6_2__FLD LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ6_2
+
+#define LPDDR4__DENALI_PHY_583_READ_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_583_WRITE_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_583__PHY_RX_CAL_DQ7_2_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_583__PHY_RX_CAL_DQ7_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_583__PHY_RX_CAL_DQ7_2_WIDTH 9U
+#define LPDDR4__PHY_RX_CAL_DQ7_2__REG DENALI_PHY_583
+#define LPDDR4__PHY_RX_CAL_DQ7_2__FLD LPDDR4__DENALI_PHY_583__PHY_RX_CAL_DQ7_2
+
+#define LPDDR4__DENALI_PHY_584_READ_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_584_WRITE_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_584__PHY_RX_CAL_DM_2_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_584__PHY_RX_CAL_DM_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_584__PHY_RX_CAL_DM_2_WIDTH 18U
+#define LPDDR4__PHY_RX_CAL_DM_2__REG DENALI_PHY_584
+#define LPDDR4__PHY_RX_CAL_DM_2__FLD LPDDR4__DENALI_PHY_584__PHY_RX_CAL_DM_2
+
+#define LPDDR4__DENALI_PHY_585_READ_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_585_WRITE_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_585__PHY_RX_CAL_DQS_2_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_585__PHY_RX_CAL_DQS_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_585__PHY_RX_CAL_DQS_2_WIDTH 9U
+#define LPDDR4__PHY_RX_CAL_DQS_2__REG DENALI_PHY_585
+#define LPDDR4__PHY_RX_CAL_DQS_2__FLD LPDDR4__DENALI_PHY_585__PHY_RX_CAL_DQS_2
+
+#define LPDDR4__DENALI_PHY_585__PHY_RX_CAL_FDBK_2_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_585__PHY_RX_CAL_FDBK_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_585__PHY_RX_CAL_FDBK_2_WIDTH 9U
+#define LPDDR4__PHY_RX_CAL_FDBK_2__REG DENALI_PHY_585
+#define LPDDR4__PHY_RX_CAL_FDBK_2__FLD LPDDR4__DENALI_PHY_585__PHY_RX_CAL_FDBK_2
+
+#define LPDDR4__DENALI_PHY_586_READ_MASK 0xFF1F07FFU
+#define LPDDR4__DENALI_PHY_586_WRITE_MASK 0xFF1F07FFU
+#define LPDDR4__DENALI_PHY_586__PHY_PAD_RX_BIAS_EN_2_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_586__PHY_PAD_RX_BIAS_EN_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_586__PHY_PAD_RX_BIAS_EN_2_WIDTH 11U
+#define LPDDR4__PHY_PAD_RX_BIAS_EN_2__REG DENALI_PHY_586
+#define LPDDR4__PHY_PAD_RX_BIAS_EN_2__FLD LPDDR4__DENALI_PHY_586__PHY_PAD_RX_BIAS_EN_2
+
+#define LPDDR4__DENALI_PHY_586__PHY_STATIC_TOG_DISABLE_2_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_586__PHY_STATIC_TOG_DISABLE_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_586__PHY_STATIC_TOG_DISABLE_2_WIDTH 5U
+#define LPDDR4__PHY_STATIC_TOG_DISABLE_2__REG DENALI_PHY_586
+#define LPDDR4__PHY_STATIC_TOG_DISABLE_2__FLD LPDDR4__DENALI_PHY_586__PHY_STATIC_TOG_DISABLE_2
+
+#define LPDDR4__DENALI_PHY_586__PHY_DATA_DC_CAL_SAMPLE_WAIT_2_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_586__PHY_DATA_DC_CAL_SAMPLE_WAIT_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_586__PHY_DATA_DC_CAL_SAMPLE_WAIT_2_WIDTH 8U
+#define LPDDR4__PHY_DATA_DC_CAL_SAMPLE_WAIT_2__REG DENALI_PHY_586
+#define LPDDR4__PHY_DATA_DC_CAL_SAMPLE_WAIT_2__FLD LPDDR4__DENALI_PHY_586__PHY_DATA_DC_CAL_SAMPLE_WAIT_2
+
+#define LPDDR4__DENALI_PHY_587_READ_MASK 0xFF3F03FFU
+#define LPDDR4__DENALI_PHY_587_WRITE_MASK 0xFF3F03FFU
+#define LPDDR4__DENALI_PHY_587__PHY_DATA_DC_CAL_TIMEOUT_2_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_587__PHY_DATA_DC_CAL_TIMEOUT_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_587__PHY_DATA_DC_CAL_TIMEOUT_2_WIDTH 8U
+#define LPDDR4__PHY_DATA_DC_CAL_TIMEOUT_2__REG DENALI_PHY_587
+#define LPDDR4__PHY_DATA_DC_CAL_TIMEOUT_2__FLD LPDDR4__DENALI_PHY_587__PHY_DATA_DC_CAL_TIMEOUT_2
+
+#define LPDDR4__DENALI_PHY_587__PHY_DATA_DC_WEIGHT_2_MASK 0x00000300U
+#define LPDDR4__DENALI_PHY_587__PHY_DATA_DC_WEIGHT_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_587__PHY_DATA_DC_WEIGHT_2_WIDTH 2U
+#define LPDDR4__PHY_DATA_DC_WEIGHT_2__REG DENALI_PHY_587
+#define LPDDR4__PHY_DATA_DC_WEIGHT_2__FLD LPDDR4__DENALI_PHY_587__PHY_DATA_DC_WEIGHT_2
+
+#define LPDDR4__DENALI_PHY_587__PHY_DATA_DC_ADJUST_START_2_MASK 0x003F0000U
+#define LPDDR4__DENALI_PHY_587__PHY_DATA_DC_ADJUST_START_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_587__PHY_DATA_DC_ADJUST_START_2_WIDTH 6U
+#define LPDDR4__PHY_DATA_DC_ADJUST_START_2__REG DENALI_PHY_587
+#define LPDDR4__PHY_DATA_DC_ADJUST_START_2__FLD LPDDR4__DENALI_PHY_587__PHY_DATA_DC_ADJUST_START_2
+
+#define LPDDR4__DENALI_PHY_587__PHY_DATA_DC_ADJUST_SAMPLE_CNT_2_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_587__PHY_DATA_DC_ADJUST_SAMPLE_CNT_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_587__PHY_DATA_DC_ADJUST_SAMPLE_CNT_2_WIDTH 8U
+#define LPDDR4__PHY_DATA_DC_ADJUST_SAMPLE_CNT_2__REG DENALI_PHY_587
+#define LPDDR4__PHY_DATA_DC_ADJUST_SAMPLE_CNT_2__FLD LPDDR4__DENALI_PHY_587__PHY_DATA_DC_ADJUST_SAMPLE_CNT_2
+
+#define LPDDR4__DENALI_PHY_588_READ_MASK 0x010101FFU
+#define LPDDR4__DENALI_PHY_588_WRITE_MASK 0x010101FFU
+#define LPDDR4__DENALI_PHY_588__PHY_DATA_DC_ADJUST_THRSHLD_2_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_588__PHY_DATA_DC_ADJUST_THRSHLD_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_588__PHY_DATA_DC_ADJUST_THRSHLD_2_WIDTH 8U
+#define LPDDR4__PHY_DATA_DC_ADJUST_THRSHLD_2__REG DENALI_PHY_588
+#define LPDDR4__PHY_DATA_DC_ADJUST_THRSHLD_2__FLD LPDDR4__DENALI_PHY_588__PHY_DATA_DC_ADJUST_THRSHLD_2
+
+#define LPDDR4__DENALI_PHY_588__PHY_DATA_DC_ADJUST_DIRECT_2_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_588__PHY_DATA_DC_ADJUST_DIRECT_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_588__PHY_DATA_DC_ADJUST_DIRECT_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_588__PHY_DATA_DC_ADJUST_DIRECT_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_588__PHY_DATA_DC_ADJUST_DIRECT_2_WOSET 0U
+#define LPDDR4__PHY_DATA_DC_ADJUST_DIRECT_2__REG DENALI_PHY_588
+#define LPDDR4__PHY_DATA_DC_ADJUST_DIRECT_2__FLD LPDDR4__DENALI_PHY_588__PHY_DATA_DC_ADJUST_DIRECT_2
+
+#define LPDDR4__DENALI_PHY_588__PHY_DATA_DC_CAL_POLARITY_2_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_588__PHY_DATA_DC_CAL_POLARITY_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_588__PHY_DATA_DC_CAL_POLARITY_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_588__PHY_DATA_DC_CAL_POLARITY_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_588__PHY_DATA_DC_CAL_POLARITY_2_WOSET 0U
+#define LPDDR4__PHY_DATA_DC_CAL_POLARITY_2__REG DENALI_PHY_588
+#define LPDDR4__PHY_DATA_DC_CAL_POLARITY_2__FLD LPDDR4__DENALI_PHY_588__PHY_DATA_DC_CAL_POLARITY_2
+
+#define LPDDR4__DENALI_PHY_588__PHY_DATA_DC_CAL_START_2_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_588__PHY_DATA_DC_CAL_START_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_588__PHY_DATA_DC_CAL_START_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_588__PHY_DATA_DC_CAL_START_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_588__PHY_DATA_DC_CAL_START_2_WOSET 0U
+#define LPDDR4__PHY_DATA_DC_CAL_START_2__REG DENALI_PHY_588
+#define LPDDR4__PHY_DATA_DC_CAL_START_2__FLD LPDDR4__DENALI_PHY_588__PHY_DATA_DC_CAL_START_2
+
+#define LPDDR4__DENALI_PHY_589_READ_MASK 0x01010703U
+#define LPDDR4__DENALI_PHY_589_WRITE_MASK 0x01010703U
+#define LPDDR4__DENALI_PHY_589__PHY_DATA_DC_SW_RANK_2_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_589__PHY_DATA_DC_SW_RANK_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_589__PHY_DATA_DC_SW_RANK_2_WIDTH 2U
+#define LPDDR4__PHY_DATA_DC_SW_RANK_2__REG DENALI_PHY_589
+#define LPDDR4__PHY_DATA_DC_SW_RANK_2__FLD LPDDR4__DENALI_PHY_589__PHY_DATA_DC_SW_RANK_2
+
+#define LPDDR4__DENALI_PHY_589__PHY_FDBK_PWR_CTRL_2_MASK 0x00000700U
+#define LPDDR4__DENALI_PHY_589__PHY_FDBK_PWR_CTRL_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_589__PHY_FDBK_PWR_CTRL_2_WIDTH 3U
+#define LPDDR4__PHY_FDBK_PWR_CTRL_2__REG DENALI_PHY_589
+#define LPDDR4__PHY_FDBK_PWR_CTRL_2__FLD LPDDR4__DENALI_PHY_589__PHY_FDBK_PWR_CTRL_2
+
+#define LPDDR4__DENALI_PHY_589__PHY_SLV_DLY_CTRL_GATE_DISABLE_2_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_589__PHY_SLV_DLY_CTRL_GATE_DISABLE_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_589__PHY_SLV_DLY_CTRL_GATE_DISABLE_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_589__PHY_SLV_DLY_CTRL_GATE_DISABLE_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_589__PHY_SLV_DLY_CTRL_GATE_DISABLE_2_WOSET 0U
+#define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_2__REG DENALI_PHY_589
+#define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_2__FLD LPDDR4__DENALI_PHY_589__PHY_SLV_DLY_CTRL_GATE_DISABLE_2
+
+#define LPDDR4__DENALI_PHY_589__PHY_RDPATH_GATE_DISABLE_2_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_589__PHY_RDPATH_GATE_DISABLE_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_589__PHY_RDPATH_GATE_DISABLE_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_589__PHY_RDPATH_GATE_DISABLE_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_589__PHY_RDPATH_GATE_DISABLE_2_WOSET 0U
+#define LPDDR4__PHY_RDPATH_GATE_DISABLE_2__REG DENALI_PHY_589
+#define LPDDR4__PHY_RDPATH_GATE_DISABLE_2__FLD LPDDR4__DENALI_PHY_589__PHY_RDPATH_GATE_DISABLE_2
+
+#define LPDDR4__DENALI_PHY_590_READ_MASK 0x00000101U
+#define LPDDR4__DENALI_PHY_590_WRITE_MASK 0x00000101U
+#define LPDDR4__DENALI_PHY_590__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_2_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_590__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_590__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_590__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_590__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_2_WOSET 0U
+#define LPDDR4__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_2__REG DENALI_PHY_590
+#define LPDDR4__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_2__FLD LPDDR4__DENALI_PHY_590__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_2
+
+#define LPDDR4__DENALI_PHY_590__PHY_SLICE_PWR_RDC_DISABLE_2_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_590__PHY_SLICE_PWR_RDC_DISABLE_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_590__PHY_SLICE_PWR_RDC_DISABLE_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_590__PHY_SLICE_PWR_RDC_DISABLE_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_590__PHY_SLICE_PWR_RDC_DISABLE_2_WOSET 0U
+#define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_2__REG DENALI_PHY_590
+#define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_2__FLD LPDDR4__DENALI_PHY_590__PHY_SLICE_PWR_RDC_DISABLE_2
+
+#define LPDDR4__DENALI_PHY_591_READ_MASK 0x07FFFF07U
+#define LPDDR4__DENALI_PHY_591_WRITE_MASK 0x07FFFF07U
+#define LPDDR4__DENALI_PHY_591__PHY_DQ_TSEL_ENABLE_2_MASK 0x00000007U
+#define LPDDR4__DENALI_PHY_591__PHY_DQ_TSEL_ENABLE_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_591__PHY_DQ_TSEL_ENABLE_2_WIDTH 3U
+#define LPDDR4__PHY_DQ_TSEL_ENABLE_2__REG DENALI_PHY_591
+#define LPDDR4__PHY_DQ_TSEL_ENABLE_2__FLD LPDDR4__DENALI_PHY_591__PHY_DQ_TSEL_ENABLE_2
+
+#define LPDDR4__DENALI_PHY_591__PHY_DQ_TSEL_SELECT_2_MASK 0x00FFFF00U
+#define LPDDR4__DENALI_PHY_591__PHY_DQ_TSEL_SELECT_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_591__PHY_DQ_TSEL_SELECT_2_WIDTH 16U
+#define LPDDR4__PHY_DQ_TSEL_SELECT_2__REG DENALI_PHY_591
+#define LPDDR4__PHY_DQ_TSEL_SELECT_2__FLD LPDDR4__DENALI_PHY_591__PHY_DQ_TSEL_SELECT_2
+
+#define LPDDR4__DENALI_PHY_591__PHY_DQS_TSEL_ENABLE_2_MASK 0x07000000U
+#define LPDDR4__DENALI_PHY_591__PHY_DQS_TSEL_ENABLE_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_591__PHY_DQS_TSEL_ENABLE_2_WIDTH 3U
+#define LPDDR4__PHY_DQS_TSEL_ENABLE_2__REG DENALI_PHY_591
+#define LPDDR4__PHY_DQS_TSEL_ENABLE_2__FLD LPDDR4__DENALI_PHY_591__PHY_DQS_TSEL_ENABLE_2
+
+#define LPDDR4__DENALI_PHY_592_READ_MASK 0x7F03FFFFU
+#define LPDDR4__DENALI_PHY_592_WRITE_MASK 0x7F03FFFFU
+#define LPDDR4__DENALI_PHY_592__PHY_DQS_TSEL_SELECT_2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_592__PHY_DQS_TSEL_SELECT_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_592__PHY_DQS_TSEL_SELECT_2_WIDTH 16U
+#define LPDDR4__PHY_DQS_TSEL_SELECT_2__REG DENALI_PHY_592
+#define LPDDR4__PHY_DQS_TSEL_SELECT_2__FLD LPDDR4__DENALI_PHY_592__PHY_DQS_TSEL_SELECT_2
+
+#define LPDDR4__DENALI_PHY_592__PHY_TWO_CYC_PREAMBLE_2_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_592__PHY_TWO_CYC_PREAMBLE_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_592__PHY_TWO_CYC_PREAMBLE_2_WIDTH 2U
+#define LPDDR4__PHY_TWO_CYC_PREAMBLE_2__REG DENALI_PHY_592
+#define LPDDR4__PHY_TWO_CYC_PREAMBLE_2__FLD LPDDR4__DENALI_PHY_592__PHY_TWO_CYC_PREAMBLE_2
+
+#define LPDDR4__DENALI_PHY_592__PHY_VREF_INITIAL_START_POINT_2_MASK 0x7F000000U
+#define LPDDR4__DENALI_PHY_592__PHY_VREF_INITIAL_START_POINT_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_592__PHY_VREF_INITIAL_START_POINT_2_WIDTH 7U
+#define LPDDR4__PHY_VREF_INITIAL_START_POINT_2__REG DENALI_PHY_592
+#define LPDDR4__PHY_VREF_INITIAL_START_POINT_2__FLD LPDDR4__DENALI_PHY_592__PHY_VREF_INITIAL_START_POINT_2
+
+#define LPDDR4__DENALI_PHY_593_READ_MASK 0xFF01037FU
+#define LPDDR4__DENALI_PHY_593_WRITE_MASK 0xFF01037FU
+#define LPDDR4__DENALI_PHY_593__PHY_VREF_INITIAL_STOP_POINT_2_MASK 0x0000007FU
+#define LPDDR4__DENALI_PHY_593__PHY_VREF_INITIAL_STOP_POINT_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_593__PHY_VREF_INITIAL_STOP_POINT_2_WIDTH 7U
+#define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_2__REG DENALI_PHY_593
+#define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_2__FLD LPDDR4__DENALI_PHY_593__PHY_VREF_INITIAL_STOP_POINT_2
+
+#define LPDDR4__DENALI_PHY_593__PHY_VREF_TRAINING_CTRL_2_MASK 0x00000300U
+#define LPDDR4__DENALI_PHY_593__PHY_VREF_TRAINING_CTRL_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_593__PHY_VREF_TRAINING_CTRL_2_WIDTH 2U
+#define LPDDR4__PHY_VREF_TRAINING_CTRL_2__REG DENALI_PHY_593
+#define LPDDR4__PHY_VREF_TRAINING_CTRL_2__FLD LPDDR4__DENALI_PHY_593__PHY_VREF_TRAINING_CTRL_2
+
+#define LPDDR4__DENALI_PHY_593__PHY_NTP_TRAIN_EN_2_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_593__PHY_NTP_TRAIN_EN_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_593__PHY_NTP_TRAIN_EN_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_593__PHY_NTP_TRAIN_EN_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_593__PHY_NTP_TRAIN_EN_2_WOSET 0U
+#define LPDDR4__PHY_NTP_TRAIN_EN_2__REG DENALI_PHY_593
+#define LPDDR4__PHY_NTP_TRAIN_EN_2__FLD LPDDR4__DENALI_PHY_593__PHY_NTP_TRAIN_EN_2
+
+#define LPDDR4__DENALI_PHY_593__PHY_NTP_WDQ_STEP_SIZE_2_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_593__PHY_NTP_WDQ_STEP_SIZE_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_593__PHY_NTP_WDQ_STEP_SIZE_2_WIDTH 8U
+#define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_2__REG DENALI_PHY_593
+#define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_2__FLD LPDDR4__DENALI_PHY_593__PHY_NTP_WDQ_STEP_SIZE_2
+
+#define LPDDR4__DENALI_PHY_594_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_594_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_594__PHY_NTP_WDQ_START_2_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_594__PHY_NTP_WDQ_START_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_594__PHY_NTP_WDQ_START_2_WIDTH 11U
+#define LPDDR4__PHY_NTP_WDQ_START_2__REG DENALI_PHY_594
+#define LPDDR4__PHY_NTP_WDQ_START_2__FLD LPDDR4__DENALI_PHY_594__PHY_NTP_WDQ_START_2
+
+#define LPDDR4__DENALI_PHY_594__PHY_NTP_WDQ_STOP_2_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_594__PHY_NTP_WDQ_STOP_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_594__PHY_NTP_WDQ_STOP_2_WIDTH 11U
+#define LPDDR4__PHY_NTP_WDQ_STOP_2__REG DENALI_PHY_594
+#define LPDDR4__PHY_NTP_WDQ_STOP_2__FLD LPDDR4__DENALI_PHY_594__PHY_NTP_WDQ_STOP_2
+
+#define LPDDR4__DENALI_PHY_595_READ_MASK 0x0103FFFFU
+#define LPDDR4__DENALI_PHY_595_WRITE_MASK 0x0103FFFFU
+#define LPDDR4__DENALI_PHY_595__PHY_NTP_WDQ_BIT_EN_2_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_595__PHY_NTP_WDQ_BIT_EN_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_595__PHY_NTP_WDQ_BIT_EN_2_WIDTH 8U
+#define LPDDR4__PHY_NTP_WDQ_BIT_EN_2__REG DENALI_PHY_595
+#define LPDDR4__PHY_NTP_WDQ_BIT_EN_2__FLD LPDDR4__DENALI_PHY_595__PHY_NTP_WDQ_BIT_EN_2
+
+#define LPDDR4__DENALI_PHY_595__PHY_WDQLVL_DVW_MIN_2_MASK 0x0003FF00U
+#define LPDDR4__DENALI_PHY_595__PHY_WDQLVL_DVW_MIN_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_595__PHY_WDQLVL_DVW_MIN_2_WIDTH 10U
+#define LPDDR4__PHY_WDQLVL_DVW_MIN_2__REG DENALI_PHY_595
+#define LPDDR4__PHY_WDQLVL_DVW_MIN_2__FLD LPDDR4__DENALI_PHY_595__PHY_WDQLVL_DVW_MIN_2
+
+#define LPDDR4__DENALI_PHY_595__PHY_SW_WDQLVL_DVW_MIN_EN_2_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_595__PHY_SW_WDQLVL_DVW_MIN_EN_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_595__PHY_SW_WDQLVL_DVW_MIN_EN_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_595__PHY_SW_WDQLVL_DVW_MIN_EN_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_595__PHY_SW_WDQLVL_DVW_MIN_EN_2_WOSET 0U
+#define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_2__REG DENALI_PHY_595
+#define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_2__FLD LPDDR4__DENALI_PHY_595__PHY_SW_WDQLVL_DVW_MIN_EN_2
+
+#define LPDDR4__DENALI_PHY_596_READ_MASK 0x1F1F0F3FU
+#define LPDDR4__DENALI_PHY_596_WRITE_MASK 0x1F1F0F3FU
+#define LPDDR4__DENALI_PHY_596__PHY_WDQLVL_PER_START_OFFSET_2_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_596__PHY_WDQLVL_PER_START_OFFSET_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_596__PHY_WDQLVL_PER_START_OFFSET_2_WIDTH 6U
+#define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_2__REG DENALI_PHY_596
+#define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_2__FLD LPDDR4__DENALI_PHY_596__PHY_WDQLVL_PER_START_OFFSET_2
+
+#define LPDDR4__DENALI_PHY_596__PHY_FAST_LVL_EN_2_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_596__PHY_FAST_LVL_EN_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_596__PHY_FAST_LVL_EN_2_WIDTH 4U
+#define LPDDR4__PHY_FAST_LVL_EN_2__REG DENALI_PHY_596
+#define LPDDR4__PHY_FAST_LVL_EN_2__FLD LPDDR4__DENALI_PHY_596__PHY_FAST_LVL_EN_2
+
+#define LPDDR4__DENALI_PHY_596__PHY_PAD_TX_DCD_2_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_596__PHY_PAD_TX_DCD_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_596__PHY_PAD_TX_DCD_2_WIDTH 5U
+#define LPDDR4__PHY_PAD_TX_DCD_2__REG DENALI_PHY_596
+#define LPDDR4__PHY_PAD_TX_DCD_2__FLD LPDDR4__DENALI_PHY_596__PHY_PAD_TX_DCD_2
+
+#define LPDDR4__DENALI_PHY_596__PHY_PAD_RX_DCD_0_2_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_596__PHY_PAD_RX_DCD_0_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_596__PHY_PAD_RX_DCD_0_2_WIDTH 5U
+#define LPDDR4__PHY_PAD_RX_DCD_0_2__REG DENALI_PHY_596
+#define LPDDR4__PHY_PAD_RX_DCD_0_2__FLD LPDDR4__DENALI_PHY_596__PHY_PAD_RX_DCD_0_2
+
+#define LPDDR4__DENALI_PHY_597_READ_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_597_WRITE_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_597__PHY_PAD_RX_DCD_1_2_MASK 0x0000001FU
+#define LPDDR4__DENALI_PHY_597__PHY_PAD_RX_DCD_1_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_597__PHY_PAD_RX_DCD_1_2_WIDTH 5U
+#define LPDDR4__PHY_PAD_RX_DCD_1_2__REG DENALI_PHY_597
+#define LPDDR4__PHY_PAD_RX_DCD_1_2__FLD LPDDR4__DENALI_PHY_597__PHY_PAD_RX_DCD_1_2
+
+#define LPDDR4__DENALI_PHY_597__PHY_PAD_RX_DCD_2_2_MASK 0x00001F00U
+#define LPDDR4__DENALI_PHY_597__PHY_PAD_RX_DCD_2_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_597__PHY_PAD_RX_DCD_2_2_WIDTH 5U
+#define LPDDR4__PHY_PAD_RX_DCD_2_2__REG DENALI_PHY_597
+#define LPDDR4__PHY_PAD_RX_DCD_2_2__FLD LPDDR4__DENALI_PHY_597__PHY_PAD_RX_DCD_2_2
+
+#define LPDDR4__DENALI_PHY_597__PHY_PAD_RX_DCD_3_2_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_597__PHY_PAD_RX_DCD_3_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_597__PHY_PAD_RX_DCD_3_2_WIDTH 5U
+#define LPDDR4__PHY_PAD_RX_DCD_3_2__REG DENALI_PHY_597
+#define LPDDR4__PHY_PAD_RX_DCD_3_2__FLD LPDDR4__DENALI_PHY_597__PHY_PAD_RX_DCD_3_2
+
+#define LPDDR4__DENALI_PHY_597__PHY_PAD_RX_DCD_4_2_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_597__PHY_PAD_RX_DCD_4_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_597__PHY_PAD_RX_DCD_4_2_WIDTH 5U
+#define LPDDR4__PHY_PAD_RX_DCD_4_2__REG DENALI_PHY_597
+#define LPDDR4__PHY_PAD_RX_DCD_4_2__FLD LPDDR4__DENALI_PHY_597__PHY_PAD_RX_DCD_4_2
+
+#define LPDDR4__DENALI_PHY_598_READ_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_598_WRITE_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_598__PHY_PAD_RX_DCD_5_2_MASK 0x0000001FU
+#define LPDDR4__DENALI_PHY_598__PHY_PAD_RX_DCD_5_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_598__PHY_PAD_RX_DCD_5_2_WIDTH 5U
+#define LPDDR4__PHY_PAD_RX_DCD_5_2__REG DENALI_PHY_598
+#define LPDDR4__PHY_PAD_RX_DCD_5_2__FLD LPDDR4__DENALI_PHY_598__PHY_PAD_RX_DCD_5_2
+
+#define LPDDR4__DENALI_PHY_598__PHY_PAD_RX_DCD_6_2_MASK 0x00001F00U
+#define LPDDR4__DENALI_PHY_598__PHY_PAD_RX_DCD_6_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_598__PHY_PAD_RX_DCD_6_2_WIDTH 5U
+#define LPDDR4__PHY_PAD_RX_DCD_6_2__REG DENALI_PHY_598
+#define LPDDR4__PHY_PAD_RX_DCD_6_2__FLD LPDDR4__DENALI_PHY_598__PHY_PAD_RX_DCD_6_2
+
+#define LPDDR4__DENALI_PHY_598__PHY_PAD_RX_DCD_7_2_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_598__PHY_PAD_RX_DCD_7_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_598__PHY_PAD_RX_DCD_7_2_WIDTH 5U
+#define LPDDR4__PHY_PAD_RX_DCD_7_2__REG DENALI_PHY_598
+#define LPDDR4__PHY_PAD_RX_DCD_7_2__FLD LPDDR4__DENALI_PHY_598__PHY_PAD_RX_DCD_7_2
+
+#define LPDDR4__DENALI_PHY_598__PHY_PAD_DM_RX_DCD_2_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_598__PHY_PAD_DM_RX_DCD_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_598__PHY_PAD_DM_RX_DCD_2_WIDTH 5U
+#define LPDDR4__PHY_PAD_DM_RX_DCD_2__REG DENALI_PHY_598
+#define LPDDR4__PHY_PAD_DM_RX_DCD_2__FLD LPDDR4__DENALI_PHY_598__PHY_PAD_DM_RX_DCD_2
+
+#define LPDDR4__DENALI_PHY_599_READ_MASK 0x007F1F1FU
+#define LPDDR4__DENALI_PHY_599_WRITE_MASK 0x007F1F1FU
+#define LPDDR4__DENALI_PHY_599__PHY_PAD_DQS_RX_DCD_2_MASK 0x0000001FU
+#define LPDDR4__DENALI_PHY_599__PHY_PAD_DQS_RX_DCD_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_599__PHY_PAD_DQS_RX_DCD_2_WIDTH 5U
+#define LPDDR4__PHY_PAD_DQS_RX_DCD_2__REG DENALI_PHY_599
+#define LPDDR4__PHY_PAD_DQS_RX_DCD_2__FLD LPDDR4__DENALI_PHY_599__PHY_PAD_DQS_RX_DCD_2
+
+#define LPDDR4__DENALI_PHY_599__PHY_PAD_FDBK_RX_DCD_2_MASK 0x00001F00U
+#define LPDDR4__DENALI_PHY_599__PHY_PAD_FDBK_RX_DCD_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_599__PHY_PAD_FDBK_RX_DCD_2_WIDTH 5U
+#define LPDDR4__PHY_PAD_FDBK_RX_DCD_2__REG DENALI_PHY_599
+#define LPDDR4__PHY_PAD_FDBK_RX_DCD_2__FLD LPDDR4__DENALI_PHY_599__PHY_PAD_FDBK_RX_DCD_2
+
+#define LPDDR4__DENALI_PHY_599__PHY_PAD_DSLICE_IO_CFG_2_MASK 0x007F0000U
+#define LPDDR4__DENALI_PHY_599__PHY_PAD_DSLICE_IO_CFG_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_599__PHY_PAD_DSLICE_IO_CFG_2_WIDTH 7U
+#define LPDDR4__PHY_PAD_DSLICE_IO_CFG_2__REG DENALI_PHY_599
+#define LPDDR4__PHY_PAD_DSLICE_IO_CFG_2__FLD LPDDR4__DENALI_PHY_599__PHY_PAD_DSLICE_IO_CFG_2
+
+#define LPDDR4__DENALI_PHY_600_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_600_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_600__PHY_RDDQ0_SLAVE_DELAY_2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_600__PHY_RDDQ0_SLAVE_DELAY_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_600__PHY_RDDQ0_SLAVE_DELAY_2_WIDTH 10U
+#define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_2__REG DENALI_PHY_600
+#define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_600__PHY_RDDQ0_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_600__PHY_RDDQ1_SLAVE_DELAY_2_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_600__PHY_RDDQ1_SLAVE_DELAY_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_600__PHY_RDDQ1_SLAVE_DELAY_2_WIDTH 10U
+#define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_2__REG DENALI_PHY_600
+#define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_600__PHY_RDDQ1_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_601_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_601_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_601__PHY_RDDQ2_SLAVE_DELAY_2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_601__PHY_RDDQ2_SLAVE_DELAY_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_601__PHY_RDDQ2_SLAVE_DELAY_2_WIDTH 10U
+#define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_2__REG DENALI_PHY_601
+#define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_601__PHY_RDDQ2_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_601__PHY_RDDQ3_SLAVE_DELAY_2_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_601__PHY_RDDQ3_SLAVE_DELAY_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_601__PHY_RDDQ3_SLAVE_DELAY_2_WIDTH 10U
+#define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_2__REG DENALI_PHY_601
+#define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_601__PHY_RDDQ3_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_602_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_602_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_602__PHY_RDDQ4_SLAVE_DELAY_2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_602__PHY_RDDQ4_SLAVE_DELAY_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_602__PHY_RDDQ4_SLAVE_DELAY_2_WIDTH 10U
+#define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_2__REG DENALI_PHY_602
+#define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_602__PHY_RDDQ4_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_602__PHY_RDDQ5_SLAVE_DELAY_2_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_602__PHY_RDDQ5_SLAVE_DELAY_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_602__PHY_RDDQ5_SLAVE_DELAY_2_WIDTH 10U
+#define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_2__REG DENALI_PHY_602
+#define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_602__PHY_RDDQ5_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_603_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_603_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_603__PHY_RDDQ6_SLAVE_DELAY_2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_603__PHY_RDDQ6_SLAVE_DELAY_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_603__PHY_RDDQ6_SLAVE_DELAY_2_WIDTH 10U
+#define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_2__REG DENALI_PHY_603
+#define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_603__PHY_RDDQ6_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_603__PHY_RDDQ7_SLAVE_DELAY_2_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_603__PHY_RDDQ7_SLAVE_DELAY_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_603__PHY_RDDQ7_SLAVE_DELAY_2_WIDTH 10U
+#define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_2__REG DENALI_PHY_603
+#define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_603__PHY_RDDQ7_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_604_READ_MASK 0x1F0703FFU
+#define LPDDR4__DENALI_PHY_604_WRITE_MASK 0x1F0703FFU
+#define LPDDR4__DENALI_PHY_604__PHY_RDDM_SLAVE_DELAY_2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_604__PHY_RDDM_SLAVE_DELAY_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_604__PHY_RDDM_SLAVE_DELAY_2_WIDTH 10U
+#define LPDDR4__PHY_RDDM_SLAVE_DELAY_2__REG DENALI_PHY_604
+#define LPDDR4__PHY_RDDM_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_604__PHY_RDDM_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_604__PHY_RX_PCLK_CLK_SEL_2_MASK 0x00070000U
+#define LPDDR4__DENALI_PHY_604__PHY_RX_PCLK_CLK_SEL_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_604__PHY_RX_PCLK_CLK_SEL_2_WIDTH 3U
+#define LPDDR4__PHY_RX_PCLK_CLK_SEL_2__REG DENALI_PHY_604
+#define LPDDR4__PHY_RX_PCLK_CLK_SEL_2__FLD LPDDR4__DENALI_PHY_604__PHY_RX_PCLK_CLK_SEL_2
+
+#define LPDDR4__DENALI_PHY_604__PHY_RX_CAL_ALL_DLY_2_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_604__PHY_RX_CAL_ALL_DLY_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_604__PHY_RX_CAL_ALL_DLY_2_WIDTH 5U
+#define LPDDR4__PHY_RX_CAL_ALL_DLY_2__REG DENALI_PHY_604
+#define LPDDR4__PHY_RX_CAL_ALL_DLY_2__FLD LPDDR4__DENALI_PHY_604__PHY_RX_CAL_ALL_DLY_2
+
+#define LPDDR4__DENALI_PHY_605_READ_MASK 0x00000007U
+#define LPDDR4__DENALI_PHY_605_WRITE_MASK 0x00000007U
+#define LPDDR4__DENALI_PHY_605__PHY_DATA_DC_CAL_CLK_SEL_2_MASK 0x00000007U
+#define LPDDR4__DENALI_PHY_605__PHY_DATA_DC_CAL_CLK_SEL_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_605__PHY_DATA_DC_CAL_CLK_SEL_2_WIDTH 3U
+#define LPDDR4__PHY_DATA_DC_CAL_CLK_SEL_2__REG DENALI_PHY_605
+#define LPDDR4__PHY_DATA_DC_CAL_CLK_SEL_2__FLD LPDDR4__DENALI_PHY_605__PHY_DATA_DC_CAL_CLK_SEL_2
+
+#define LPDDR4__DENALI_PHY_606_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_606_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_606__PHY_DQ_OE_TIMING_2_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_606__PHY_DQ_OE_TIMING_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_606__PHY_DQ_OE_TIMING_2_WIDTH 8U
+#define LPDDR4__PHY_DQ_OE_TIMING_2__REG DENALI_PHY_606
+#define LPDDR4__PHY_DQ_OE_TIMING_2__FLD LPDDR4__DENALI_PHY_606__PHY_DQ_OE_TIMING_2
+
+#define LPDDR4__DENALI_PHY_606__PHY_DQ_TSEL_RD_TIMING_2_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_606__PHY_DQ_TSEL_RD_TIMING_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_606__PHY_DQ_TSEL_RD_TIMING_2_WIDTH 8U
+#define LPDDR4__PHY_DQ_TSEL_RD_TIMING_2__REG DENALI_PHY_606
+#define LPDDR4__PHY_DQ_TSEL_RD_TIMING_2__FLD LPDDR4__DENALI_PHY_606__PHY_DQ_TSEL_RD_TIMING_2
+
+#define LPDDR4__DENALI_PHY_606__PHY_DQ_TSEL_WR_TIMING_2_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_606__PHY_DQ_TSEL_WR_TIMING_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_606__PHY_DQ_TSEL_WR_TIMING_2_WIDTH 8U
+#define LPDDR4__PHY_DQ_TSEL_WR_TIMING_2__REG DENALI_PHY_606
+#define LPDDR4__PHY_DQ_TSEL_WR_TIMING_2__FLD LPDDR4__DENALI_PHY_606__PHY_DQ_TSEL_WR_TIMING_2
+
+#define LPDDR4__DENALI_PHY_606__PHY_DQS_OE_TIMING_2_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_606__PHY_DQS_OE_TIMING_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_606__PHY_DQS_OE_TIMING_2_WIDTH 8U
+#define LPDDR4__PHY_DQS_OE_TIMING_2__REG DENALI_PHY_606
+#define LPDDR4__PHY_DQS_OE_TIMING_2__FLD LPDDR4__DENALI_PHY_606__PHY_DQS_OE_TIMING_2
+
+#define LPDDR4__DENALI_PHY_607_READ_MASK 0xFFFFFF0FU
+#define LPDDR4__DENALI_PHY_607_WRITE_MASK 0xFFFFFF0FU
+#define LPDDR4__DENALI_PHY_607__PHY_IO_PAD_DELAY_TIMING_2_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_607__PHY_IO_PAD_DELAY_TIMING_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_607__PHY_IO_PAD_DELAY_TIMING_2_WIDTH 4U
+#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_2__REG DENALI_PHY_607
+#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_2__FLD LPDDR4__DENALI_PHY_607__PHY_IO_PAD_DELAY_TIMING_2
+
+#define LPDDR4__DENALI_PHY_607__PHY_DQS_TSEL_RD_TIMING_2_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_607__PHY_DQS_TSEL_RD_TIMING_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_607__PHY_DQS_TSEL_RD_TIMING_2_WIDTH 8U
+#define LPDDR4__PHY_DQS_TSEL_RD_TIMING_2__REG DENALI_PHY_607
+#define LPDDR4__PHY_DQS_TSEL_RD_TIMING_2__FLD LPDDR4__DENALI_PHY_607__PHY_DQS_TSEL_RD_TIMING_2
+
+#define LPDDR4__DENALI_PHY_607__PHY_DQS_OE_RD_TIMING_2_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_607__PHY_DQS_OE_RD_TIMING_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_607__PHY_DQS_OE_RD_TIMING_2_WIDTH 8U
+#define LPDDR4__PHY_DQS_OE_RD_TIMING_2__REG DENALI_PHY_607
+#define LPDDR4__PHY_DQS_OE_RD_TIMING_2__FLD LPDDR4__DENALI_PHY_607__PHY_DQS_OE_RD_TIMING_2
+
+#define LPDDR4__DENALI_PHY_607__PHY_DQS_TSEL_WR_TIMING_2_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_607__PHY_DQS_TSEL_WR_TIMING_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_607__PHY_DQS_TSEL_WR_TIMING_2_WIDTH 8U
+#define LPDDR4__PHY_DQS_TSEL_WR_TIMING_2__REG DENALI_PHY_607
+#define LPDDR4__PHY_DQS_TSEL_WR_TIMING_2__FLD LPDDR4__DENALI_PHY_607__PHY_DQS_TSEL_WR_TIMING_2
+
+#define LPDDR4__DENALI_PHY_608_READ_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_608_WRITE_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_608__PHY_VREF_SETTING_TIME_2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_608__PHY_VREF_SETTING_TIME_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_608__PHY_VREF_SETTING_TIME_2_WIDTH 16U
+#define LPDDR4__PHY_VREF_SETTING_TIME_2__REG DENALI_PHY_608
+#define LPDDR4__PHY_VREF_SETTING_TIME_2__FLD LPDDR4__DENALI_PHY_608__PHY_VREF_SETTING_TIME_2
+
+#define LPDDR4__DENALI_PHY_608__PHY_PAD_VREF_CTRL_DQ_2_MASK 0x0FFF0000U
+#define LPDDR4__DENALI_PHY_608__PHY_PAD_VREF_CTRL_DQ_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_608__PHY_PAD_VREF_CTRL_DQ_2_WIDTH 12U
+#define LPDDR4__PHY_PAD_VREF_CTRL_DQ_2__REG DENALI_PHY_608
+#define LPDDR4__PHY_PAD_VREF_CTRL_DQ_2__FLD LPDDR4__DENALI_PHY_608__PHY_PAD_VREF_CTRL_DQ_2
+
+#define LPDDR4__DENALI_PHY_609_READ_MASK 0x03FFFF01U
+#define LPDDR4__DENALI_PHY_609_WRITE_MASK 0x03FFFF01U
+#define LPDDR4__DENALI_PHY_609__PHY_PER_CS_TRAINING_EN_2_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_609__PHY_PER_CS_TRAINING_EN_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_609__PHY_PER_CS_TRAINING_EN_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_609__PHY_PER_CS_TRAINING_EN_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_609__PHY_PER_CS_TRAINING_EN_2_WOSET 0U
+#define LPDDR4__PHY_PER_CS_TRAINING_EN_2__REG DENALI_PHY_609
+#define LPDDR4__PHY_PER_CS_TRAINING_EN_2__FLD LPDDR4__DENALI_PHY_609__PHY_PER_CS_TRAINING_EN_2
+
+#define LPDDR4__DENALI_PHY_609__PHY_DQ_IE_TIMING_2_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_609__PHY_DQ_IE_TIMING_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_609__PHY_DQ_IE_TIMING_2_WIDTH 8U
+#define LPDDR4__PHY_DQ_IE_TIMING_2__REG DENALI_PHY_609
+#define LPDDR4__PHY_DQ_IE_TIMING_2__FLD LPDDR4__DENALI_PHY_609__PHY_DQ_IE_TIMING_2
+
+#define LPDDR4__DENALI_PHY_609__PHY_DQS_IE_TIMING_2_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_609__PHY_DQS_IE_TIMING_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_609__PHY_DQS_IE_TIMING_2_WIDTH 8U
+#define LPDDR4__PHY_DQS_IE_TIMING_2__REG DENALI_PHY_609
+#define LPDDR4__PHY_DQS_IE_TIMING_2__FLD LPDDR4__DENALI_PHY_609__PHY_DQS_IE_TIMING_2
+
+#define LPDDR4__DENALI_PHY_609__PHY_RDDATA_EN_IE_DLY_2_MASK 0x03000000U
+#define LPDDR4__DENALI_PHY_609__PHY_RDDATA_EN_IE_DLY_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_609__PHY_RDDATA_EN_IE_DLY_2_WIDTH 2U
+#define LPDDR4__PHY_RDDATA_EN_IE_DLY_2__REG DENALI_PHY_609
+#define LPDDR4__PHY_RDDATA_EN_IE_DLY_2__FLD LPDDR4__DENALI_PHY_609__PHY_RDDATA_EN_IE_DLY_2
+
+#define LPDDR4__DENALI_PHY_610_READ_MASK 0x1F010303U
+#define LPDDR4__DENALI_PHY_610_WRITE_MASK 0x1F010303U
+#define LPDDR4__DENALI_PHY_610__PHY_IE_MODE_2_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_610__PHY_IE_MODE_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_610__PHY_IE_MODE_2_WIDTH 2U
+#define LPDDR4__PHY_IE_MODE_2__REG DENALI_PHY_610
+#define LPDDR4__PHY_IE_MODE_2__FLD LPDDR4__DENALI_PHY_610__PHY_IE_MODE_2
+
+#define LPDDR4__DENALI_PHY_610__PHY_DBI_MODE_2_MASK 0x00000300U
+#define LPDDR4__DENALI_PHY_610__PHY_DBI_MODE_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_610__PHY_DBI_MODE_2_WIDTH 2U
+#define LPDDR4__PHY_DBI_MODE_2__REG DENALI_PHY_610
+#define LPDDR4__PHY_DBI_MODE_2__FLD LPDDR4__DENALI_PHY_610__PHY_DBI_MODE_2
+
+#define LPDDR4__DENALI_PHY_610__PHY_WDQLVL_IE_ON_2_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_610__PHY_WDQLVL_IE_ON_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_610__PHY_WDQLVL_IE_ON_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_610__PHY_WDQLVL_IE_ON_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_610__PHY_WDQLVL_IE_ON_2_WOSET 0U
+#define LPDDR4__PHY_WDQLVL_IE_ON_2__REG DENALI_PHY_610
+#define LPDDR4__PHY_WDQLVL_IE_ON_2__FLD LPDDR4__DENALI_PHY_610__PHY_WDQLVL_IE_ON_2
+
+#define LPDDR4__DENALI_PHY_610__PHY_WDQLVL_RDDATA_EN_DLY_2_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_610__PHY_WDQLVL_RDDATA_EN_DLY_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_610__PHY_WDQLVL_RDDATA_EN_DLY_2_WIDTH 5U
+#define LPDDR4__PHY_WDQLVL_RDDATA_EN_DLY_2__REG DENALI_PHY_610
+#define LPDDR4__PHY_WDQLVL_RDDATA_EN_DLY_2__FLD LPDDR4__DENALI_PHY_610__PHY_WDQLVL_RDDATA_EN_DLY_2
+
+#define LPDDR4__DENALI_PHY_611_READ_MASK 0x0F1F1F1FU
+#define LPDDR4__DENALI_PHY_611_WRITE_MASK 0x0F1F1F1FU
+#define LPDDR4__DENALI_PHY_611__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_2_MASK 0x0000001FU
+#define LPDDR4__DENALI_PHY_611__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_611__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_2_WIDTH 5U
+#define LPDDR4__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_2__REG DENALI_PHY_611
+#define LPDDR4__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_2__FLD LPDDR4__DENALI_PHY_611__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_2
+
+#define LPDDR4__DENALI_PHY_611__PHY_RDDATA_EN_TSEL_DLY_2_MASK 0x00001F00U
+#define LPDDR4__DENALI_PHY_611__PHY_RDDATA_EN_TSEL_DLY_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_611__PHY_RDDATA_EN_TSEL_DLY_2_WIDTH 5U
+#define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_2__REG DENALI_PHY_611
+#define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_2__FLD LPDDR4__DENALI_PHY_611__PHY_RDDATA_EN_TSEL_DLY_2
+
+#define LPDDR4__DENALI_PHY_611__PHY_RDDATA_EN_OE_DLY_2_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_611__PHY_RDDATA_EN_OE_DLY_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_611__PHY_RDDATA_EN_OE_DLY_2_WIDTH 5U
+#define LPDDR4__PHY_RDDATA_EN_OE_DLY_2__REG DENALI_PHY_611
+#define LPDDR4__PHY_RDDATA_EN_OE_DLY_2__FLD LPDDR4__DENALI_PHY_611__PHY_RDDATA_EN_OE_DLY_2
+
+#define LPDDR4__DENALI_PHY_611__PHY_SW_MASTER_MODE_2_MASK 0x0F000000U
+#define LPDDR4__DENALI_PHY_611__PHY_SW_MASTER_MODE_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_611__PHY_SW_MASTER_MODE_2_WIDTH 4U
+#define LPDDR4__PHY_SW_MASTER_MODE_2__REG DENALI_PHY_611
+#define LPDDR4__PHY_SW_MASTER_MODE_2__FLD LPDDR4__DENALI_PHY_611__PHY_SW_MASTER_MODE_2
+
+#define LPDDR4__DENALI_PHY_612_READ_MASK 0xFF3F07FFU
+#define LPDDR4__DENALI_PHY_612_WRITE_MASK 0xFF3F07FFU
+#define LPDDR4__DENALI_PHY_612__PHY_MASTER_DELAY_START_2_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_612__PHY_MASTER_DELAY_START_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_612__PHY_MASTER_DELAY_START_2_WIDTH 11U
+#define LPDDR4__PHY_MASTER_DELAY_START_2__REG DENALI_PHY_612
+#define LPDDR4__PHY_MASTER_DELAY_START_2__FLD LPDDR4__DENALI_PHY_612__PHY_MASTER_DELAY_START_2
+
+#define LPDDR4__DENALI_PHY_612__PHY_MASTER_DELAY_STEP_2_MASK 0x003F0000U
+#define LPDDR4__DENALI_PHY_612__PHY_MASTER_DELAY_STEP_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_612__PHY_MASTER_DELAY_STEP_2_WIDTH 6U
+#define LPDDR4__PHY_MASTER_DELAY_STEP_2__REG DENALI_PHY_612
+#define LPDDR4__PHY_MASTER_DELAY_STEP_2__FLD LPDDR4__DENALI_PHY_612__PHY_MASTER_DELAY_STEP_2
+
+#define LPDDR4__DENALI_PHY_612__PHY_MASTER_DELAY_WAIT_2_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_612__PHY_MASTER_DELAY_WAIT_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_612__PHY_MASTER_DELAY_WAIT_2_WIDTH 8U
+#define LPDDR4__PHY_MASTER_DELAY_WAIT_2__REG DENALI_PHY_612
+#define LPDDR4__PHY_MASTER_DELAY_WAIT_2__FLD LPDDR4__DENALI_PHY_612__PHY_MASTER_DELAY_WAIT_2
+
+#define LPDDR4__DENALI_PHY_613_READ_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_PHY_613_WRITE_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_PHY_613__PHY_MASTER_DELAY_HALF_MEASURE_2_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_613__PHY_MASTER_DELAY_HALF_MEASURE_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_613__PHY_MASTER_DELAY_HALF_MEASURE_2_WIDTH 8U
+#define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_2__REG DENALI_PHY_613
+#define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_2__FLD LPDDR4__DENALI_PHY_613__PHY_MASTER_DELAY_HALF_MEASURE_2
+
+#define LPDDR4__DENALI_PHY_613__PHY_RPTR_UPDATE_2_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_613__PHY_RPTR_UPDATE_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_613__PHY_RPTR_UPDATE_2_WIDTH 4U
+#define LPDDR4__PHY_RPTR_UPDATE_2__REG DENALI_PHY_613
+#define LPDDR4__PHY_RPTR_UPDATE_2__FLD LPDDR4__DENALI_PHY_613__PHY_RPTR_UPDATE_2
+
+#define LPDDR4__DENALI_PHY_613__PHY_WRLVL_DLY_STEP_2_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_613__PHY_WRLVL_DLY_STEP_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_613__PHY_WRLVL_DLY_STEP_2_WIDTH 8U
+#define LPDDR4__PHY_WRLVL_DLY_STEP_2__REG DENALI_PHY_613
+#define LPDDR4__PHY_WRLVL_DLY_STEP_2__FLD LPDDR4__DENALI_PHY_613__PHY_WRLVL_DLY_STEP_2
+
+#define LPDDR4__DENALI_PHY_613__PHY_WRLVL_DLY_FINE_STEP_2_MASK 0x0F000000U
+#define LPDDR4__DENALI_PHY_613__PHY_WRLVL_DLY_FINE_STEP_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_613__PHY_WRLVL_DLY_FINE_STEP_2_WIDTH 4U
+#define LPDDR4__PHY_WRLVL_DLY_FINE_STEP_2__REG DENALI_PHY_613
+#define LPDDR4__PHY_WRLVL_DLY_FINE_STEP_2__FLD LPDDR4__DENALI_PHY_613__PHY_WRLVL_DLY_FINE_STEP_2
+
+#define LPDDR4__DENALI_PHY_614_READ_MASK 0x001F0F3FU
+#define LPDDR4__DENALI_PHY_614_WRITE_MASK 0x001F0F3FU
+#define LPDDR4__DENALI_PHY_614__PHY_WRLVL_RESP_WAIT_CNT_2_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_614__PHY_WRLVL_RESP_WAIT_CNT_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_614__PHY_WRLVL_RESP_WAIT_CNT_2_WIDTH 6U
+#define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_2__REG DENALI_PHY_614
+#define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_2__FLD LPDDR4__DENALI_PHY_614__PHY_WRLVL_RESP_WAIT_CNT_2
+
+#define LPDDR4__DENALI_PHY_614__PHY_GTLVL_DLY_STEP_2_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_614__PHY_GTLVL_DLY_STEP_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_614__PHY_GTLVL_DLY_STEP_2_WIDTH 4U
+#define LPDDR4__PHY_GTLVL_DLY_STEP_2__REG DENALI_PHY_614
+#define LPDDR4__PHY_GTLVL_DLY_STEP_2__FLD LPDDR4__DENALI_PHY_614__PHY_GTLVL_DLY_STEP_2
+
+#define LPDDR4__DENALI_PHY_614__PHY_GTLVL_RESP_WAIT_CNT_2_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_614__PHY_GTLVL_RESP_WAIT_CNT_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_614__PHY_GTLVL_RESP_WAIT_CNT_2_WIDTH 5U
+#define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_2__REG DENALI_PHY_614
+#define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_2__FLD LPDDR4__DENALI_PHY_614__PHY_GTLVL_RESP_WAIT_CNT_2
+
+#define LPDDR4__DENALI_PHY_615_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_615_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_615__PHY_GTLVL_BACK_STEP_2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_615__PHY_GTLVL_BACK_STEP_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_615__PHY_GTLVL_BACK_STEP_2_WIDTH 10U
+#define LPDDR4__PHY_GTLVL_BACK_STEP_2__REG DENALI_PHY_615
+#define LPDDR4__PHY_GTLVL_BACK_STEP_2__FLD LPDDR4__DENALI_PHY_615__PHY_GTLVL_BACK_STEP_2
+
+#define LPDDR4__DENALI_PHY_615__PHY_GTLVL_FINAL_STEP_2_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_615__PHY_GTLVL_FINAL_STEP_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_615__PHY_GTLVL_FINAL_STEP_2_WIDTH 10U
+#define LPDDR4__PHY_GTLVL_FINAL_STEP_2__REG DENALI_PHY_615
+#define LPDDR4__PHY_GTLVL_FINAL_STEP_2__FLD LPDDR4__DENALI_PHY_615__PHY_GTLVL_FINAL_STEP_2
+
+#define LPDDR4__DENALI_PHY_616_READ_MASK 0x01FF0FFFU
+#define LPDDR4__DENALI_PHY_616_WRITE_MASK 0x01FF0FFFU
+#define LPDDR4__DENALI_PHY_616__PHY_WDQLVL_DLY_STEP_2_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_616__PHY_WDQLVL_DLY_STEP_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_616__PHY_WDQLVL_DLY_STEP_2_WIDTH 8U
+#define LPDDR4__PHY_WDQLVL_DLY_STEP_2__REG DENALI_PHY_616
+#define LPDDR4__PHY_WDQLVL_DLY_STEP_2__FLD LPDDR4__DENALI_PHY_616__PHY_WDQLVL_DLY_STEP_2
+
+#define LPDDR4__DENALI_PHY_616__PHY_WDQLVL_QTR_DLY_STEP_2_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_616__PHY_WDQLVL_QTR_DLY_STEP_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_616__PHY_WDQLVL_QTR_DLY_STEP_2_WIDTH 4U
+#define LPDDR4__PHY_WDQLVL_QTR_DLY_STEP_2__REG DENALI_PHY_616
+#define LPDDR4__PHY_WDQLVL_QTR_DLY_STEP_2__FLD LPDDR4__DENALI_PHY_616__PHY_WDQLVL_QTR_DLY_STEP_2
+
+#define LPDDR4__DENALI_PHY_616__PHY_WDQLVL_DM_SEARCH_RANGE_2_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_616__PHY_WDQLVL_DM_SEARCH_RANGE_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_616__PHY_WDQLVL_DM_SEARCH_RANGE_2_WIDTH 9U
+#define LPDDR4__PHY_WDQLVL_DM_SEARCH_RANGE_2__REG DENALI_PHY_616
+#define LPDDR4__PHY_WDQLVL_DM_SEARCH_RANGE_2__FLD LPDDR4__DENALI_PHY_616__PHY_WDQLVL_DM_SEARCH_RANGE_2
+
+#define LPDDR4__DENALI_PHY_617_READ_MASK 0x00000F01U
+#define LPDDR4__DENALI_PHY_617_WRITE_MASK 0x00000F01U
+#define LPDDR4__DENALI_PHY_617__PHY_TOGGLE_PRE_SUPPORT_2_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_617__PHY_TOGGLE_PRE_SUPPORT_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_617__PHY_TOGGLE_PRE_SUPPORT_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_617__PHY_TOGGLE_PRE_SUPPORT_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_617__PHY_TOGGLE_PRE_SUPPORT_2_WOSET 0U
+#define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_2__REG DENALI_PHY_617
+#define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_2__FLD LPDDR4__DENALI_PHY_617__PHY_TOGGLE_PRE_SUPPORT_2
+
+#define LPDDR4__DENALI_PHY_617__PHY_RDLVL_DLY_STEP_2_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_617__PHY_RDLVL_DLY_STEP_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_617__PHY_RDLVL_DLY_STEP_2_WIDTH 4U
+#define LPDDR4__PHY_RDLVL_DLY_STEP_2__REG DENALI_PHY_617
+#define LPDDR4__PHY_RDLVL_DLY_STEP_2__FLD LPDDR4__DENALI_PHY_617__PHY_RDLVL_DLY_STEP_2
+
+#define LPDDR4__DENALI_PHY_618_READ_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_618_WRITE_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_618__PHY_RDLVL_MAX_EDGE_2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_618__PHY_RDLVL_MAX_EDGE_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_618__PHY_RDLVL_MAX_EDGE_2_WIDTH 10U
+#define LPDDR4__PHY_RDLVL_MAX_EDGE_2__REG DENALI_PHY_618
+#define LPDDR4__PHY_RDLVL_MAX_EDGE_2__FLD LPDDR4__DENALI_PHY_618__PHY_RDLVL_MAX_EDGE_2
+
+#define LPDDR4__DENALI_PHY_619_READ_MASK 0x00030703U
+#define LPDDR4__DENALI_PHY_619_WRITE_MASK 0x00030703U
+#define LPDDR4__DENALI_PHY_619__PHY_WRPATH_GATE_DISABLE_2_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_619__PHY_WRPATH_GATE_DISABLE_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_619__PHY_WRPATH_GATE_DISABLE_2_WIDTH 2U
+#define LPDDR4__PHY_WRPATH_GATE_DISABLE_2__REG DENALI_PHY_619
+#define LPDDR4__PHY_WRPATH_GATE_DISABLE_2__FLD LPDDR4__DENALI_PHY_619__PHY_WRPATH_GATE_DISABLE_2
+
+#define LPDDR4__DENALI_PHY_619__PHY_WRPATH_GATE_TIMING_2_MASK 0x00000700U
+#define LPDDR4__DENALI_PHY_619__PHY_WRPATH_GATE_TIMING_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_619__PHY_WRPATH_GATE_TIMING_2_WIDTH 3U
+#define LPDDR4__PHY_WRPATH_GATE_TIMING_2__REG DENALI_PHY_619
+#define LPDDR4__PHY_WRPATH_GATE_TIMING_2__FLD LPDDR4__DENALI_PHY_619__PHY_WRPATH_GATE_TIMING_2
+
+#define LPDDR4__DENALI_PHY_619__PHY_DATA_DC_INIT_DISABLE_2_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_619__PHY_DATA_DC_INIT_DISABLE_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_619__PHY_DATA_DC_INIT_DISABLE_2_WIDTH 2U
+#define LPDDR4__PHY_DATA_DC_INIT_DISABLE_2__REG DENALI_PHY_619
+#define LPDDR4__PHY_DATA_DC_INIT_DISABLE_2__FLD LPDDR4__DENALI_PHY_619__PHY_DATA_DC_INIT_DISABLE_2
+
+#define LPDDR4__DENALI_PHY_620_READ_MASK 0x07FF03FFU
+#define LPDDR4__DENALI_PHY_620_WRITE_MASK 0x07FF03FFU
+#define LPDDR4__DENALI_PHY_620__PHY_DATA_DC_DQS_INIT_SLV_DELAY_2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_620__PHY_DATA_DC_DQS_INIT_SLV_DELAY_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_620__PHY_DATA_DC_DQS_INIT_SLV_DELAY_2_WIDTH 10U
+#define LPDDR4__PHY_DATA_DC_DQS_INIT_SLV_DELAY_2__REG DENALI_PHY_620
+#define LPDDR4__PHY_DATA_DC_DQS_INIT_SLV_DELAY_2__FLD LPDDR4__DENALI_PHY_620__PHY_DATA_DC_DQS_INIT_SLV_DELAY_2
+
+#define LPDDR4__DENALI_PHY_620__PHY_DATA_DC_DQ_INIT_SLV_DELAY_2_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_620__PHY_DATA_DC_DQ_INIT_SLV_DELAY_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_620__PHY_DATA_DC_DQ_INIT_SLV_DELAY_2_WIDTH 11U
+#define LPDDR4__PHY_DATA_DC_DQ_INIT_SLV_DELAY_2__REG DENALI_PHY_620
+#define LPDDR4__PHY_DATA_DC_DQ_INIT_SLV_DELAY_2__FLD LPDDR4__DENALI_PHY_620__PHY_DATA_DC_DQ_INIT_SLV_DELAY_2
+
+#define LPDDR4__DENALI_PHY_621_READ_MASK 0xFFFF0101U
+#define LPDDR4__DENALI_PHY_621_WRITE_MASK 0xFFFF0101U
+#define LPDDR4__DENALI_PHY_621__PHY_DATA_DC_WRLVL_ENABLE_2_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_621__PHY_DATA_DC_WRLVL_ENABLE_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_621__PHY_DATA_DC_WRLVL_ENABLE_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_621__PHY_DATA_DC_WRLVL_ENABLE_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_621__PHY_DATA_DC_WRLVL_ENABLE_2_WOSET 0U
+#define LPDDR4__PHY_DATA_DC_WRLVL_ENABLE_2__REG DENALI_PHY_621
+#define LPDDR4__PHY_DATA_DC_WRLVL_ENABLE_2__FLD LPDDR4__DENALI_PHY_621__PHY_DATA_DC_WRLVL_ENABLE_2
+
+#define LPDDR4__DENALI_PHY_621__PHY_DATA_DC_WDQLVL_ENABLE_2_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_621__PHY_DATA_DC_WDQLVL_ENABLE_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_621__PHY_DATA_DC_WDQLVL_ENABLE_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_621__PHY_DATA_DC_WDQLVL_ENABLE_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_621__PHY_DATA_DC_WDQLVL_ENABLE_2_WOSET 0U
+#define LPDDR4__PHY_DATA_DC_WDQLVL_ENABLE_2__REG DENALI_PHY_621
+#define LPDDR4__PHY_DATA_DC_WDQLVL_ENABLE_2__FLD LPDDR4__DENALI_PHY_621__PHY_DATA_DC_WDQLVL_ENABLE_2
+
+#define LPDDR4__DENALI_PHY_621__PHY_DATA_DC_DM_CLK_SE_THRSHLD_2_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_621__PHY_DATA_DC_DM_CLK_SE_THRSHLD_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_621__PHY_DATA_DC_DM_CLK_SE_THRSHLD_2_WIDTH 8U
+#define LPDDR4__PHY_DATA_DC_DM_CLK_SE_THRSHLD_2__REG DENALI_PHY_621
+#define LPDDR4__PHY_DATA_DC_DM_CLK_SE_THRSHLD_2__FLD LPDDR4__DENALI_PHY_621__PHY_DATA_DC_DM_CLK_SE_THRSHLD_2
+
+#define LPDDR4__DENALI_PHY_621__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_2_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_621__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_621__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_2_WIDTH 8U
+#define LPDDR4__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_2__REG DENALI_PHY_621
+#define LPDDR4__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_2__FLD LPDDR4__DENALI_PHY_621__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_2
+
+#define LPDDR4__DENALI_PHY_622_READ_MASK 0x001F7F7FU
+#define LPDDR4__DENALI_PHY_622_WRITE_MASK 0x001F7F7FU
+#define LPDDR4__DENALI_PHY_622__PHY_WDQ_OSC_DELTA_2_MASK 0x0000007FU
+#define LPDDR4__DENALI_PHY_622__PHY_WDQ_OSC_DELTA_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_622__PHY_WDQ_OSC_DELTA_2_WIDTH 7U
+#define LPDDR4__PHY_WDQ_OSC_DELTA_2__REG DENALI_PHY_622
+#define LPDDR4__PHY_WDQ_OSC_DELTA_2__FLD LPDDR4__DENALI_PHY_622__PHY_WDQ_OSC_DELTA_2
+
+#define LPDDR4__DENALI_PHY_622__PHY_MEAS_DLY_STEP_ENABLE_2_MASK 0x00007F00U
+#define LPDDR4__DENALI_PHY_622__PHY_MEAS_DLY_STEP_ENABLE_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_622__PHY_MEAS_DLY_STEP_ENABLE_2_WIDTH 7U
+#define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_2__REG DENALI_PHY_622
+#define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_2__FLD LPDDR4__DENALI_PHY_622__PHY_MEAS_DLY_STEP_ENABLE_2
+
+#define LPDDR4__DENALI_PHY_622__PHY_RDDATA_EN_DLY_2_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_622__PHY_RDDATA_EN_DLY_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_622__PHY_RDDATA_EN_DLY_2_WIDTH 5U
+#define LPDDR4__PHY_RDDATA_EN_DLY_2__REG DENALI_PHY_622
+#define LPDDR4__PHY_RDDATA_EN_DLY_2__FLD LPDDR4__DENALI_PHY_622__PHY_RDDATA_EN_DLY_2
+
+#define LPDDR4__DENALI_PHY_623_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_623_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_623__PHY_DQ_DM_SWIZZLE0_2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_623__PHY_DQ_DM_SWIZZLE0_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_623__PHY_DQ_DM_SWIZZLE0_2_WIDTH 32U
+#define LPDDR4__PHY_DQ_DM_SWIZZLE0_2__REG DENALI_PHY_623
+#define LPDDR4__PHY_DQ_DM_SWIZZLE0_2__FLD LPDDR4__DENALI_PHY_623__PHY_DQ_DM_SWIZZLE0_2
+
+#define LPDDR4__DENALI_PHY_624_READ_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_624_WRITE_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_624__PHY_DQ_DM_SWIZZLE1_2_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_624__PHY_DQ_DM_SWIZZLE1_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_624__PHY_DQ_DM_SWIZZLE1_2_WIDTH 4U
+#define LPDDR4__PHY_DQ_DM_SWIZZLE1_2__REG DENALI_PHY_624
+#define LPDDR4__PHY_DQ_DM_SWIZZLE1_2__FLD LPDDR4__DENALI_PHY_624__PHY_DQ_DM_SWIZZLE1_2
+
+#define LPDDR4__DENALI_PHY_625_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_625_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_625__PHY_CLK_WRDQ0_SLAVE_DELAY_2_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_625__PHY_CLK_WRDQ0_SLAVE_DELAY_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_625__PHY_CLK_WRDQ0_SLAVE_DELAY_2_WIDTH 11U
+#define LPDDR4__PHY_CLK_WRDQ0_SLAVE_DELAY_2__REG DENALI_PHY_625
+#define LPDDR4__PHY_CLK_WRDQ0_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_625__PHY_CLK_WRDQ0_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_625__PHY_CLK_WRDQ1_SLAVE_DELAY_2_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_625__PHY_CLK_WRDQ1_SLAVE_DELAY_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_625__PHY_CLK_WRDQ1_SLAVE_DELAY_2_WIDTH 11U
+#define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_2__REG DENALI_PHY_625
+#define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_625__PHY_CLK_WRDQ1_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_626_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_626_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_626__PHY_CLK_WRDQ2_SLAVE_DELAY_2_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_626__PHY_CLK_WRDQ2_SLAVE_DELAY_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_626__PHY_CLK_WRDQ2_SLAVE_DELAY_2_WIDTH 11U
+#define LPDDR4__PHY_CLK_WRDQ2_SLAVE_DELAY_2__REG DENALI_PHY_626
+#define LPDDR4__PHY_CLK_WRDQ2_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_626__PHY_CLK_WRDQ2_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_626__PHY_CLK_WRDQ3_SLAVE_DELAY_2_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_626__PHY_CLK_WRDQ3_SLAVE_DELAY_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_626__PHY_CLK_WRDQ3_SLAVE_DELAY_2_WIDTH 11U
+#define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_2__REG DENALI_PHY_626
+#define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_626__PHY_CLK_WRDQ3_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_627_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_627_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_627__PHY_CLK_WRDQ4_SLAVE_DELAY_2_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_627__PHY_CLK_WRDQ4_SLAVE_DELAY_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_627__PHY_CLK_WRDQ4_SLAVE_DELAY_2_WIDTH 11U
+#define LPDDR4__PHY_CLK_WRDQ4_SLAVE_DELAY_2__REG DENALI_PHY_627
+#define LPDDR4__PHY_CLK_WRDQ4_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_627__PHY_CLK_WRDQ4_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_627__PHY_CLK_WRDQ5_SLAVE_DELAY_2_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_627__PHY_CLK_WRDQ5_SLAVE_DELAY_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_627__PHY_CLK_WRDQ5_SLAVE_DELAY_2_WIDTH 11U
+#define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_2__REG DENALI_PHY_627
+#define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_627__PHY_CLK_WRDQ5_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_628_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_628_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_628__PHY_CLK_WRDQ6_SLAVE_DELAY_2_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_628__PHY_CLK_WRDQ6_SLAVE_DELAY_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_628__PHY_CLK_WRDQ6_SLAVE_DELAY_2_WIDTH 11U
+#define LPDDR4__PHY_CLK_WRDQ6_SLAVE_DELAY_2__REG DENALI_PHY_628
+#define LPDDR4__PHY_CLK_WRDQ6_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_628__PHY_CLK_WRDQ6_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_628__PHY_CLK_WRDQ7_SLAVE_DELAY_2_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_628__PHY_CLK_WRDQ7_SLAVE_DELAY_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_628__PHY_CLK_WRDQ7_SLAVE_DELAY_2_WIDTH 11U
+#define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_2__REG DENALI_PHY_628
+#define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_628__PHY_CLK_WRDQ7_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_629_READ_MASK 0x03FF07FFU
+#define LPDDR4__DENALI_PHY_629_WRITE_MASK 0x03FF07FFU
+#define LPDDR4__DENALI_PHY_629__PHY_CLK_WRDM_SLAVE_DELAY_2_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_629__PHY_CLK_WRDM_SLAVE_DELAY_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_629__PHY_CLK_WRDM_SLAVE_DELAY_2_WIDTH 11U
+#define LPDDR4__PHY_CLK_WRDM_SLAVE_DELAY_2__REG DENALI_PHY_629
+#define LPDDR4__PHY_CLK_WRDM_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_629__PHY_CLK_WRDM_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_629__PHY_CLK_WRDQS_SLAVE_DELAY_2_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_629__PHY_CLK_WRDQS_SLAVE_DELAY_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_629__PHY_CLK_WRDQS_SLAVE_DELAY_2_WIDTH 10U
+#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_2__REG DENALI_PHY_629
+#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_629__PHY_CLK_WRDQS_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_630_READ_MASK 0x0003FF03U
+#define LPDDR4__DENALI_PHY_630_WRITE_MASK 0x0003FF03U
+#define LPDDR4__DENALI_PHY_630__PHY_WRLVL_THRESHOLD_ADJUST_2_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_630__PHY_WRLVL_THRESHOLD_ADJUST_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_630__PHY_WRLVL_THRESHOLD_ADJUST_2_WIDTH 2U
+#define LPDDR4__PHY_WRLVL_THRESHOLD_ADJUST_2__REG DENALI_PHY_630
+#define LPDDR4__PHY_WRLVL_THRESHOLD_ADJUST_2__FLD LPDDR4__DENALI_PHY_630__PHY_WRLVL_THRESHOLD_ADJUST_2
+
+#define LPDDR4__DENALI_PHY_630__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_2_MASK 0x0003FF00U
+#define LPDDR4__DENALI_PHY_630__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_630__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_2_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_2__REG DENALI_PHY_630
+#define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_630__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_631_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_631_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_631__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_631__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_631__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_2_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_2__REG DENALI_PHY_631
+#define LPDDR4__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_631__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_631__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_2_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_631__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_631__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_2_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_2__REG DENALI_PHY_631
+#define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_631__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_632_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_632_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_632__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_632__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_632__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_2_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_2__REG DENALI_PHY_632
+#define LPDDR4__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_632__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_632__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_2_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_632__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_632__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_2_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_2__REG DENALI_PHY_632
+#define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_632__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_633_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_633_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_633__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_633__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_633__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_2_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_2__REG DENALI_PHY_633
+#define LPDDR4__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_633__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_633__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_2_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_633__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_633__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_2_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_2__REG DENALI_PHY_633
+#define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_633__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_634_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_634_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_634__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_634__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_634__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_2_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_2__REG DENALI_PHY_634
+#define LPDDR4__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_634__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_634__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_2_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_634__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_634__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_2_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_2__REG DENALI_PHY_634
+#define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_634__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_635_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_635_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_635__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_635__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_635__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_2_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_2__REG DENALI_PHY_635
+#define LPDDR4__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_635__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_635__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_2_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_635__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_635__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_2_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_2__REG DENALI_PHY_635
+#define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_635__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_636_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_636_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_636__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_636__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_636__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_2_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_2__REG DENALI_PHY_636
+#define LPDDR4__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_636__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_636__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_2_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_636__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_636__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_2_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_2__REG DENALI_PHY_636
+#define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_636__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_637_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_637_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_637__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_637__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_637__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_2_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_2__REG DENALI_PHY_637
+#define LPDDR4__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_637__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_637__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_2_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_637__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_637__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_2_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_2__REG DENALI_PHY_637
+#define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_637__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_638_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_638_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_638__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_638__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_638__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_2_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_2__REG DENALI_PHY_638
+#define LPDDR4__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_638__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_638__PHY_RDDQS_DM_RISE_SLAVE_DELAY_2_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_638__PHY_RDDQS_DM_RISE_SLAVE_DELAY_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_638__PHY_RDDQS_DM_RISE_SLAVE_DELAY_2_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_2__REG DENALI_PHY_638
+#define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_638__PHY_RDDQS_DM_RISE_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_639_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_639_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_639__PHY_RDDQS_DM_FALL_SLAVE_DELAY_2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_639__PHY_RDDQS_DM_FALL_SLAVE_DELAY_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_639__PHY_RDDQS_DM_FALL_SLAVE_DELAY_2_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DM_FALL_SLAVE_DELAY_2__REG DENALI_PHY_639
+#define LPDDR4__PHY_RDDQS_DM_FALL_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_639__PHY_RDDQS_DM_FALL_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_639__PHY_RDDQS_GATE_SLAVE_DELAY_2_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_639__PHY_RDDQS_GATE_SLAVE_DELAY_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_639__PHY_RDDQS_GATE_SLAVE_DELAY_2_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_2__REG DENALI_PHY_639
+#define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_639__PHY_RDDQS_GATE_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_640_READ_MASK 0x03FF070FU
+#define LPDDR4__DENALI_PHY_640_WRITE_MASK 0x03FF070FU
+#define LPDDR4__DENALI_PHY_640__PHY_RDDQS_LATENCY_ADJUST_2_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_640__PHY_RDDQS_LATENCY_ADJUST_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_640__PHY_RDDQS_LATENCY_ADJUST_2_WIDTH 4U
+#define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_2__REG DENALI_PHY_640
+#define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_2__FLD LPDDR4__DENALI_PHY_640__PHY_RDDQS_LATENCY_ADJUST_2
+
+#define LPDDR4__DENALI_PHY_640__PHY_WRITE_PATH_LAT_ADD_2_MASK 0x00000700U
+#define LPDDR4__DENALI_PHY_640__PHY_WRITE_PATH_LAT_ADD_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_640__PHY_WRITE_PATH_LAT_ADD_2_WIDTH 3U
+#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_2__REG DENALI_PHY_640
+#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_2__FLD LPDDR4__DENALI_PHY_640__PHY_WRITE_PATH_LAT_ADD_2
+
+#define LPDDR4__DENALI_PHY_640__PHY_WRLVL_DELAY_EARLY_THRESHOLD_2_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_640__PHY_WRLVL_DELAY_EARLY_THRESHOLD_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_640__PHY_WRLVL_DELAY_EARLY_THRESHOLD_2_WIDTH 10U
+#define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_2__REG DENALI_PHY_640
+#define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_2__FLD LPDDR4__DENALI_PHY_640__PHY_WRLVL_DELAY_EARLY_THRESHOLD_2
+
+#define LPDDR4__DENALI_PHY_641_READ_MASK 0x000103FFU
+#define LPDDR4__DENALI_PHY_641_WRITE_MASK 0x000103FFU
+#define LPDDR4__DENALI_PHY_641__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_641__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_641__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2_WIDTH 10U
+#define LPDDR4__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2__REG DENALI_PHY_641
+#define LPDDR4__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2__FLD LPDDR4__DENALI_PHY_641__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2
+
+#define LPDDR4__DENALI_PHY_641__PHY_WRLVL_EARLY_FORCE_ZERO_2_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_641__PHY_WRLVL_EARLY_FORCE_ZERO_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_641__PHY_WRLVL_EARLY_FORCE_ZERO_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_641__PHY_WRLVL_EARLY_FORCE_ZERO_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_641__PHY_WRLVL_EARLY_FORCE_ZERO_2_WOSET 0U
+#define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_2__REG DENALI_PHY_641
+#define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_2__FLD LPDDR4__DENALI_PHY_641__PHY_WRLVL_EARLY_FORCE_ZERO_2
+
+#define LPDDR4__DENALI_PHY_642_READ_MASK 0x000F03FFU
+#define LPDDR4__DENALI_PHY_642_WRITE_MASK 0x000F03FFU
+#define LPDDR4__DENALI_PHY_642__PHY_GTLVL_RDDQS_SLV_DLY_START_2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_642__PHY_GTLVL_RDDQS_SLV_DLY_START_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_642__PHY_GTLVL_RDDQS_SLV_DLY_START_2_WIDTH 10U
+#define LPDDR4__PHY_GTLVL_RDDQS_SLV_DLY_START_2__REG DENALI_PHY_642
+#define LPDDR4__PHY_GTLVL_RDDQS_SLV_DLY_START_2__FLD LPDDR4__DENALI_PHY_642__PHY_GTLVL_RDDQS_SLV_DLY_START_2
+
+#define LPDDR4__DENALI_PHY_642__PHY_GTLVL_LAT_ADJ_START_2_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_642__PHY_GTLVL_LAT_ADJ_START_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_642__PHY_GTLVL_LAT_ADJ_START_2_WIDTH 4U
+#define LPDDR4__PHY_GTLVL_LAT_ADJ_START_2__REG DENALI_PHY_642
+#define LPDDR4__PHY_GTLVL_LAT_ADJ_START_2__FLD LPDDR4__DENALI_PHY_642__PHY_GTLVL_LAT_ADJ_START_2
+
+#define LPDDR4__DENALI_PHY_643_READ_MASK 0x010F07FFU
+#define LPDDR4__DENALI_PHY_643_WRITE_MASK 0x010F07FFU
+#define LPDDR4__DENALI_PHY_643__PHY_WDQLVL_DQDM_SLV_DLY_START_2_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_643__PHY_WDQLVL_DQDM_SLV_DLY_START_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_643__PHY_WDQLVL_DQDM_SLV_DLY_START_2_WIDTH 11U
+#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_2__REG DENALI_PHY_643
+#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_2__FLD LPDDR4__DENALI_PHY_643__PHY_WDQLVL_DQDM_SLV_DLY_START_2
+
+#define LPDDR4__DENALI_PHY_643__PHY_NTP_WRLAT_START_2_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_643__PHY_NTP_WRLAT_START_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_643__PHY_NTP_WRLAT_START_2_WIDTH 4U
+#define LPDDR4__PHY_NTP_WRLAT_START_2__REG DENALI_PHY_643
+#define LPDDR4__PHY_NTP_WRLAT_START_2__FLD LPDDR4__DENALI_PHY_643__PHY_NTP_WRLAT_START_2
+
+#define LPDDR4__DENALI_PHY_643__PHY_NTP_PASS_2_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_643__PHY_NTP_PASS_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_643__PHY_NTP_PASS_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_643__PHY_NTP_PASS_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_643__PHY_NTP_PASS_2_WOSET 0U
+#define LPDDR4__PHY_NTP_PASS_2__REG DENALI_PHY_643
+#define LPDDR4__PHY_NTP_PASS_2__FLD LPDDR4__DENALI_PHY_643__PHY_NTP_PASS_2
+
+#define LPDDR4__DENALI_PHY_644_READ_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_644_WRITE_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_644__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_644__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_644__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_2_WIDTH 10U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_2__REG DENALI_PHY_644
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_2__FLD LPDDR4__DENALI_PHY_644__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_2
+
+#define LPDDR4__DENALI_PHY_645_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_645_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_645__PHY_DATA_DC_DQS_CLK_ADJUST_2_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_645__PHY_DATA_DC_DQS_CLK_ADJUST_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_645__PHY_DATA_DC_DQS_CLK_ADJUST_2_WIDTH 8U
+#define LPDDR4__PHY_DATA_DC_DQS_CLK_ADJUST_2__REG DENALI_PHY_645
+#define LPDDR4__PHY_DATA_DC_DQS_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_645__PHY_DATA_DC_DQS_CLK_ADJUST_2
+
+#define LPDDR4__DENALI_PHY_645__PHY_DATA_DC_DQ0_CLK_ADJUST_2_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_645__PHY_DATA_DC_DQ0_CLK_ADJUST_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_645__PHY_DATA_DC_DQ0_CLK_ADJUST_2_WIDTH 8U
+#define LPDDR4__PHY_DATA_DC_DQ0_CLK_ADJUST_2__REG DENALI_PHY_645
+#define LPDDR4__PHY_DATA_DC_DQ0_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_645__PHY_DATA_DC_DQ0_CLK_ADJUST_2
+
+#define LPDDR4__DENALI_PHY_645__PHY_DATA_DC_DQ1_CLK_ADJUST_2_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_645__PHY_DATA_DC_DQ1_CLK_ADJUST_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_645__PHY_DATA_DC_DQ1_CLK_ADJUST_2_WIDTH 8U
+#define LPDDR4__PHY_DATA_DC_DQ1_CLK_ADJUST_2__REG DENALI_PHY_645
+#define LPDDR4__PHY_DATA_DC_DQ1_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_645__PHY_DATA_DC_DQ1_CLK_ADJUST_2
+
+#define LPDDR4__DENALI_PHY_645__PHY_DATA_DC_DQ2_CLK_ADJUST_2_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_645__PHY_DATA_DC_DQ2_CLK_ADJUST_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_645__PHY_DATA_DC_DQ2_CLK_ADJUST_2_WIDTH 8U
+#define LPDDR4__PHY_DATA_DC_DQ2_CLK_ADJUST_2__REG DENALI_PHY_645
+#define LPDDR4__PHY_DATA_DC_DQ2_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_645__PHY_DATA_DC_DQ2_CLK_ADJUST_2
+
+#define LPDDR4__DENALI_PHY_646_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_646_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_646__PHY_DATA_DC_DQ3_CLK_ADJUST_2_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_646__PHY_DATA_DC_DQ3_CLK_ADJUST_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_646__PHY_DATA_DC_DQ3_CLK_ADJUST_2_WIDTH 8U
+#define LPDDR4__PHY_DATA_DC_DQ3_CLK_ADJUST_2__REG DENALI_PHY_646
+#define LPDDR4__PHY_DATA_DC_DQ3_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_646__PHY_DATA_DC_DQ3_CLK_ADJUST_2
+
+#define LPDDR4__DENALI_PHY_646__PHY_DATA_DC_DQ4_CLK_ADJUST_2_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_646__PHY_DATA_DC_DQ4_CLK_ADJUST_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_646__PHY_DATA_DC_DQ4_CLK_ADJUST_2_WIDTH 8U
+#define LPDDR4__PHY_DATA_DC_DQ4_CLK_ADJUST_2__REG DENALI_PHY_646
+#define LPDDR4__PHY_DATA_DC_DQ4_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_646__PHY_DATA_DC_DQ4_CLK_ADJUST_2
+
+#define LPDDR4__DENALI_PHY_646__PHY_DATA_DC_DQ5_CLK_ADJUST_2_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_646__PHY_DATA_DC_DQ5_CLK_ADJUST_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_646__PHY_DATA_DC_DQ5_CLK_ADJUST_2_WIDTH 8U
+#define LPDDR4__PHY_DATA_DC_DQ5_CLK_ADJUST_2__REG DENALI_PHY_646
+#define LPDDR4__PHY_DATA_DC_DQ5_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_646__PHY_DATA_DC_DQ5_CLK_ADJUST_2
+
+#define LPDDR4__DENALI_PHY_646__PHY_DATA_DC_DQ6_CLK_ADJUST_2_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_646__PHY_DATA_DC_DQ6_CLK_ADJUST_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_646__PHY_DATA_DC_DQ6_CLK_ADJUST_2_WIDTH 8U
+#define LPDDR4__PHY_DATA_DC_DQ6_CLK_ADJUST_2__REG DENALI_PHY_646
+#define LPDDR4__PHY_DATA_DC_DQ6_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_646__PHY_DATA_DC_DQ6_CLK_ADJUST_2
+
+#define LPDDR4__DENALI_PHY_647_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_647_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_647__PHY_DATA_DC_DQ7_CLK_ADJUST_2_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_647__PHY_DATA_DC_DQ7_CLK_ADJUST_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_647__PHY_DATA_DC_DQ7_CLK_ADJUST_2_WIDTH 8U
+#define LPDDR4__PHY_DATA_DC_DQ7_CLK_ADJUST_2__REG DENALI_PHY_647
+#define LPDDR4__PHY_DATA_DC_DQ7_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_647__PHY_DATA_DC_DQ7_CLK_ADJUST_2
+
+#define LPDDR4__DENALI_PHY_647__PHY_DATA_DC_DM_CLK_ADJUST_2_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_647__PHY_DATA_DC_DM_CLK_ADJUST_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_647__PHY_DATA_DC_DM_CLK_ADJUST_2_WIDTH 8U
+#define LPDDR4__PHY_DATA_DC_DM_CLK_ADJUST_2__REG DENALI_PHY_647
+#define LPDDR4__PHY_DATA_DC_DM_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_647__PHY_DATA_DC_DM_CLK_ADJUST_2
+
+#define LPDDR4__DENALI_PHY_647__PHY_DSLICE_PAD_BOOSTPN_SETTING_2_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_PHY_647__PHY_DSLICE_PAD_BOOSTPN_SETTING_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_647__PHY_DSLICE_PAD_BOOSTPN_SETTING_2_WIDTH 16U
+#define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_2__REG DENALI_PHY_647
+#define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_2__FLD LPDDR4__DENALI_PHY_647__PHY_DSLICE_PAD_BOOSTPN_SETTING_2
+
+#define LPDDR4__DENALI_PHY_648_READ_MASK 0x0003033FU
+#define LPDDR4__DENALI_PHY_648_WRITE_MASK 0x0003033FU
+#define LPDDR4__DENALI_PHY_648__PHY_DSLICE_PAD_RX_CTLE_SETTING_2_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_648__PHY_DSLICE_PAD_RX_CTLE_SETTING_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_648__PHY_DSLICE_PAD_RX_CTLE_SETTING_2_WIDTH 6U
+#define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_2__REG DENALI_PHY_648
+#define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_2__FLD LPDDR4__DENALI_PHY_648__PHY_DSLICE_PAD_RX_CTLE_SETTING_2
+
+#define LPDDR4__DENALI_PHY_648__PHY_DQ_FFE_2_MASK 0x00000300U
+#define LPDDR4__DENALI_PHY_648__PHY_DQ_FFE_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_648__PHY_DQ_FFE_2_WIDTH 2U
+#define LPDDR4__PHY_DQ_FFE_2__REG DENALI_PHY_648
+#define LPDDR4__PHY_DQ_FFE_2__FLD LPDDR4__DENALI_PHY_648__PHY_DQ_FFE_2
+
+#define LPDDR4__DENALI_PHY_648__PHY_DQS_FFE_2_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_648__PHY_DQS_FFE_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_648__PHY_DQS_FFE_2_WIDTH 2U
+#define LPDDR4__PHY_DQS_FFE_2__REG DENALI_PHY_648
+#define LPDDR4__PHY_DQS_FFE_2__FLD LPDDR4__DENALI_PHY_648__PHY_DQS_FFE_2
+
+#endif /* REG_LPDDR4_DATA_SLICE_2_MACROS_H_ */
diff --git a/drivers/ram/k3-ddrss/am62a/lpddr4_data_slice_3_macros.h b/drivers/ram/k3-ddrss/am62a/lpddr4_data_slice_3_macros.h
new file mode 100644
index 00000000000..29bdc46e945
--- /dev/null
+++ b/drivers/ram/k3-ddrss/am62a/lpddr4_data_slice_3_macros.h
@@ -0,0 +1,2292 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef REG_LPDDR4_DATA_SLICE_3_MACROS_H_
+#define REG_LPDDR4_DATA_SLICE_3_MACROS_H_
+
+#define LPDDR4__DENALI_PHY_768_READ_MASK 0x07FF7F07U
+#define LPDDR4__DENALI_PHY_768_WRITE_MASK 0x07FF7F07U
+#define LPDDR4__DENALI_PHY_768__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_3_MASK 0x00000007U
+#define LPDDR4__DENALI_PHY_768__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_768__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_3_WIDTH 3U
+#define LPDDR4__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_3__REG DENALI_PHY_768
+#define LPDDR4__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_3__FLD LPDDR4__DENALI_PHY_768__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_3
+
+#define LPDDR4__DENALI_PHY_768__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_3_MASK 0x00007F00U
+#define LPDDR4__DENALI_PHY_768__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_768__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_3_WIDTH 7U
+#define LPDDR4__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_3__REG DENALI_PHY_768
+#define LPDDR4__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_3__FLD LPDDR4__DENALI_PHY_768__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_3
+
+#define LPDDR4__DENALI_PHY_768__PHY_CLK_WR_BYPASS_SLAVE_DELAY_3_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_768__PHY_CLK_WR_BYPASS_SLAVE_DELAY_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_768__PHY_CLK_WR_BYPASS_SLAVE_DELAY_3_WIDTH 11U
+#define LPDDR4__PHY_CLK_WR_BYPASS_SLAVE_DELAY_3__REG DENALI_PHY_768
+#define LPDDR4__PHY_CLK_WR_BYPASS_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_768__PHY_CLK_WR_BYPASS_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_769_READ_MASK 0x0703FF0FU
+#define LPDDR4__DENALI_PHY_769_WRITE_MASK 0x0703FF0FU
+#define LPDDR4__DENALI_PHY_769__PHY_IO_PAD_DELAY_TIMING_BYPASS_3_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_769__PHY_IO_PAD_DELAY_TIMING_BYPASS_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_769__PHY_IO_PAD_DELAY_TIMING_BYPASS_3_WIDTH 4U
+#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_3__REG DENALI_PHY_769
+#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_3__FLD LPDDR4__DENALI_PHY_769__PHY_IO_PAD_DELAY_TIMING_BYPASS_3
+
+#define LPDDR4__DENALI_PHY_769__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_3_MASK 0x0003FF00U
+#define LPDDR4__DENALI_PHY_769__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_769__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_3_WIDTH 10U
+#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_3__REG DENALI_PHY_769
+#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_3__FLD LPDDR4__DENALI_PHY_769__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_3
+
+#define LPDDR4__DENALI_PHY_769__PHY_WRITE_PATH_LAT_ADD_BYPASS_3_MASK 0x07000000U
+#define LPDDR4__DENALI_PHY_769__PHY_WRITE_PATH_LAT_ADD_BYPASS_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_769__PHY_WRITE_PATH_LAT_ADD_BYPASS_3_WIDTH 3U
+#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_3__REG DENALI_PHY_769
+#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_3__FLD LPDDR4__DENALI_PHY_769__PHY_WRITE_PATH_LAT_ADD_BYPASS_3
+
+#define LPDDR4__DENALI_PHY_770_READ_MASK 0x010303FFU
+#define LPDDR4__DENALI_PHY_770_WRITE_MASK 0x010303FFU
+#define LPDDR4__DENALI_PHY_770__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_3_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_770__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_770__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_3_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_3__REG DENALI_PHY_770
+#define LPDDR4__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_770__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_770__PHY_BYPASS_TWO_CYC_PREAMBLE_3_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_770__PHY_BYPASS_TWO_CYC_PREAMBLE_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_770__PHY_BYPASS_TWO_CYC_PREAMBLE_3_WIDTH 2U
+#define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_3__REG DENALI_PHY_770
+#define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_3__FLD LPDDR4__DENALI_PHY_770__PHY_BYPASS_TWO_CYC_PREAMBLE_3
+
+#define LPDDR4__DENALI_PHY_770__PHY_CLK_BYPASS_OVERRIDE_3_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_770__PHY_CLK_BYPASS_OVERRIDE_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_770__PHY_CLK_BYPASS_OVERRIDE_3_WIDTH 1U
+#define LPDDR4__DENALI_PHY_770__PHY_CLK_BYPASS_OVERRIDE_3_WOCLR 0U
+#define LPDDR4__DENALI_PHY_770__PHY_CLK_BYPASS_OVERRIDE_3_WOSET 0U
+#define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_3__REG DENALI_PHY_770
+#define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_3__FLD LPDDR4__DENALI_PHY_770__PHY_CLK_BYPASS_OVERRIDE_3
+
+#define LPDDR4__DENALI_PHY_771_READ_MASK 0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_771_WRITE_MASK 0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ0_SHIFT_3_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ0_SHIFT_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ0_SHIFT_3_WIDTH 6U
+#define LPDDR4__PHY_SW_WRDQ0_SHIFT_3__REG DENALI_PHY_771
+#define LPDDR4__PHY_SW_WRDQ0_SHIFT_3__FLD LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ0_SHIFT_3
+
+#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ1_SHIFT_3_MASK 0x00003F00U
+#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ1_SHIFT_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ1_SHIFT_3_WIDTH 6U
+#define LPDDR4__PHY_SW_WRDQ1_SHIFT_3__REG DENALI_PHY_771
+#define LPDDR4__PHY_SW_WRDQ1_SHIFT_3__FLD LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ1_SHIFT_3
+
+#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ2_SHIFT_3_MASK 0x003F0000U
+#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ2_SHIFT_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ2_SHIFT_3_WIDTH 6U
+#define LPDDR4__PHY_SW_WRDQ2_SHIFT_3__REG DENALI_PHY_771
+#define LPDDR4__PHY_SW_WRDQ2_SHIFT_3__FLD LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ2_SHIFT_3
+
+#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ3_SHIFT_3_MASK 0x3F000000U
+#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ3_SHIFT_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ3_SHIFT_3_WIDTH 6U
+#define LPDDR4__PHY_SW_WRDQ3_SHIFT_3__REG DENALI_PHY_771
+#define LPDDR4__PHY_SW_WRDQ3_SHIFT_3__FLD LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ3_SHIFT_3
+
+#define LPDDR4__DENALI_PHY_772_READ_MASK 0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_772_WRITE_MASK 0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ4_SHIFT_3_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ4_SHIFT_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ4_SHIFT_3_WIDTH 6U
+#define LPDDR4__PHY_SW_WRDQ4_SHIFT_3__REG DENALI_PHY_772
+#define LPDDR4__PHY_SW_WRDQ4_SHIFT_3__FLD LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ4_SHIFT_3
+
+#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ5_SHIFT_3_MASK 0x00003F00U
+#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ5_SHIFT_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ5_SHIFT_3_WIDTH 6U
+#define LPDDR4__PHY_SW_WRDQ5_SHIFT_3__REG DENALI_PHY_772
+#define LPDDR4__PHY_SW_WRDQ5_SHIFT_3__FLD LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ5_SHIFT_3
+
+#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ6_SHIFT_3_MASK 0x003F0000U
+#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ6_SHIFT_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ6_SHIFT_3_WIDTH 6U
+#define LPDDR4__PHY_SW_WRDQ6_SHIFT_3__REG DENALI_PHY_772
+#define LPDDR4__PHY_SW_WRDQ6_SHIFT_3__FLD LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ6_SHIFT_3
+
+#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ7_SHIFT_3_MASK 0x3F000000U
+#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ7_SHIFT_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ7_SHIFT_3_WIDTH 6U
+#define LPDDR4__PHY_SW_WRDQ7_SHIFT_3__REG DENALI_PHY_772
+#define LPDDR4__PHY_SW_WRDQ7_SHIFT_3__FLD LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ7_SHIFT_3
+
+#define LPDDR4__DENALI_PHY_773_READ_MASK 0x01030F3FU
+#define LPDDR4__DENALI_PHY_773_WRITE_MASK 0x01030F3FU
+#define LPDDR4__DENALI_PHY_773__PHY_SW_WRDM_SHIFT_3_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_773__PHY_SW_WRDM_SHIFT_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_773__PHY_SW_WRDM_SHIFT_3_WIDTH 6U
+#define LPDDR4__PHY_SW_WRDM_SHIFT_3__REG DENALI_PHY_773
+#define LPDDR4__PHY_SW_WRDM_SHIFT_3__FLD LPDDR4__DENALI_PHY_773__PHY_SW_WRDM_SHIFT_3
+
+#define LPDDR4__DENALI_PHY_773__PHY_SW_WRDQS_SHIFT_3_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_773__PHY_SW_WRDQS_SHIFT_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_773__PHY_SW_WRDQS_SHIFT_3_WIDTH 4U
+#define LPDDR4__PHY_SW_WRDQS_SHIFT_3__REG DENALI_PHY_773
+#define LPDDR4__PHY_SW_WRDQS_SHIFT_3__FLD LPDDR4__DENALI_PHY_773__PHY_SW_WRDQS_SHIFT_3
+
+#define LPDDR4__DENALI_PHY_773__PHY_PER_RANK_CS_MAP_3_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_773__PHY_PER_RANK_CS_MAP_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_773__PHY_PER_RANK_CS_MAP_3_WIDTH 2U
+#define LPDDR4__PHY_PER_RANK_CS_MAP_3__REG DENALI_PHY_773
+#define LPDDR4__PHY_PER_RANK_CS_MAP_3__FLD LPDDR4__DENALI_PHY_773__PHY_PER_RANK_CS_MAP_3
+
+#define LPDDR4__DENALI_PHY_773__PHY_PER_CS_TRAINING_MULTICAST_EN_3_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_773__PHY_PER_CS_TRAINING_MULTICAST_EN_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_773__PHY_PER_CS_TRAINING_MULTICAST_EN_3_WIDTH 1U
+#define LPDDR4__DENALI_PHY_773__PHY_PER_CS_TRAINING_MULTICAST_EN_3_WOCLR 0U
+#define LPDDR4__DENALI_PHY_773__PHY_PER_CS_TRAINING_MULTICAST_EN_3_WOSET 0U
+#define LPDDR4__PHY_PER_CS_TRAINING_MULTICAST_EN_3__REG DENALI_PHY_773
+#define LPDDR4__PHY_PER_CS_TRAINING_MULTICAST_EN_3__FLD LPDDR4__DENALI_PHY_773__PHY_PER_CS_TRAINING_MULTICAST_EN_3
+
+#define LPDDR4__DENALI_PHY_774_READ_MASK 0x1F1F0301U
+#define LPDDR4__DENALI_PHY_774_WRITE_MASK 0x1F1F0301U
+#define LPDDR4__DENALI_PHY_774__PHY_PER_CS_TRAINING_INDEX_3_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_774__PHY_PER_CS_TRAINING_INDEX_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_774__PHY_PER_CS_TRAINING_INDEX_3_WIDTH 1U
+#define LPDDR4__DENALI_PHY_774__PHY_PER_CS_TRAINING_INDEX_3_WOCLR 0U
+#define LPDDR4__DENALI_PHY_774__PHY_PER_CS_TRAINING_INDEX_3_WOSET 0U
+#define LPDDR4__PHY_PER_CS_TRAINING_INDEX_3__REG DENALI_PHY_774
+#define LPDDR4__PHY_PER_CS_TRAINING_INDEX_3__FLD LPDDR4__DENALI_PHY_774__PHY_PER_CS_TRAINING_INDEX_3
+
+#define LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_3_MASK 0x00000300U
+#define LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_3_WIDTH 2U
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_3__REG DENALI_PHY_774
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_3__FLD LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_3
+
+#define LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_DLY_3_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_DLY_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_DLY_3_WIDTH 5U
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_DLY_3__REG DENALI_PHY_774
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_DLY_3__FLD LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_DLY_3
+
+#define LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_3_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_3_WIDTH 5U
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_3__REG DENALI_PHY_774
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_3__FLD LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_3
+
+#define LPDDR4__DENALI_PHY_775_READ_MASK 0x1F030F0FU
+#define LPDDR4__DENALI_PHY_775_WRITE_MASK 0x1F030F0FU
+#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RPTR_UPDATE_3_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RPTR_UPDATE_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RPTR_UPDATE_3_WIDTH 4U
+#define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_3__REG DENALI_PHY_775
+#define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_3__FLD LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RPTR_UPDATE_3
+
+#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_3_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_3_WIDTH 4U
+#define LPDDR4__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_3__REG DENALI_PHY_775
+#define LPDDR4__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_3__FLD LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_3
+
+#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_3_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_3_WIDTH 2U
+#define LPDDR4__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_3__REG DENALI_PHY_775
+#define LPDDR4__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_3__FLD LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_3
+
+#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_3_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_3_WIDTH 5U
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_3__REG DENALI_PHY_775
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_3__FLD LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_3
+
+#define LPDDR4__DENALI_PHY_776_READ_MASK 0x0101FF03U
+#define LPDDR4__DENALI_PHY_776_WRITE_MASK 0x0101FF03U
+#define LPDDR4__DENALI_PHY_776__PHY_CTRL_LPBK_EN_3_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_776__PHY_CTRL_LPBK_EN_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_776__PHY_CTRL_LPBK_EN_3_WIDTH 2U
+#define LPDDR4__PHY_CTRL_LPBK_EN_3__REG DENALI_PHY_776
+#define LPDDR4__PHY_CTRL_LPBK_EN_3__FLD LPDDR4__DENALI_PHY_776__PHY_CTRL_LPBK_EN_3
+
+#define LPDDR4__DENALI_PHY_776__PHY_LPBK_CONTROL_3_MASK 0x0001FF00U
+#define LPDDR4__DENALI_PHY_776__PHY_LPBK_CONTROL_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_776__PHY_LPBK_CONTROL_3_WIDTH 9U
+#define LPDDR4__PHY_LPBK_CONTROL_3__REG DENALI_PHY_776
+#define LPDDR4__PHY_LPBK_CONTROL_3__FLD LPDDR4__DENALI_PHY_776__PHY_LPBK_CONTROL_3
+
+#define LPDDR4__DENALI_PHY_776__PHY_LPBK_DFX_TIMEOUT_EN_3_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_776__PHY_LPBK_DFX_TIMEOUT_EN_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_776__PHY_LPBK_DFX_TIMEOUT_EN_3_WIDTH 1U
+#define LPDDR4__DENALI_PHY_776__PHY_LPBK_DFX_TIMEOUT_EN_3_WOCLR 0U
+#define LPDDR4__DENALI_PHY_776__PHY_LPBK_DFX_TIMEOUT_EN_3_WOSET 0U
+#define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_3__REG DENALI_PHY_776
+#define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_3__FLD LPDDR4__DENALI_PHY_776__PHY_LPBK_DFX_TIMEOUT_EN_3
+
+#define LPDDR4__DENALI_PHY_777_READ_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_777_WRITE_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_777__PHY_GATE_DELAY_COMP_DISABLE_3_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_777__PHY_GATE_DELAY_COMP_DISABLE_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_777__PHY_GATE_DELAY_COMP_DISABLE_3_WIDTH 1U
+#define LPDDR4__DENALI_PHY_777__PHY_GATE_DELAY_COMP_DISABLE_3_WOCLR 0U
+#define LPDDR4__DENALI_PHY_777__PHY_GATE_DELAY_COMP_DISABLE_3_WOSET 0U
+#define LPDDR4__PHY_GATE_DELAY_COMP_DISABLE_3__REG DENALI_PHY_777
+#define LPDDR4__PHY_GATE_DELAY_COMP_DISABLE_3__FLD LPDDR4__DENALI_PHY_777__PHY_GATE_DELAY_COMP_DISABLE_3
+
+#define LPDDR4__DENALI_PHY_778_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_778_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_778__PHY_AUTO_TIMING_MARGIN_CONTROL_3_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_778__PHY_AUTO_TIMING_MARGIN_CONTROL_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_778__PHY_AUTO_TIMING_MARGIN_CONTROL_3_WIDTH 32U
+#define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_3__REG DENALI_PHY_778
+#define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_3__FLD LPDDR4__DENALI_PHY_778__PHY_AUTO_TIMING_MARGIN_CONTROL_3
+
+#define LPDDR4__DENALI_PHY_779_READ_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_779_WRITE_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_779__PHY_AUTO_TIMING_MARGIN_OBS_3_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_779__PHY_AUTO_TIMING_MARGIN_OBS_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_779__PHY_AUTO_TIMING_MARGIN_OBS_3_WIDTH 28U
+#define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_3__REG DENALI_PHY_779
+#define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_3__FLD LPDDR4__DENALI_PHY_779__PHY_AUTO_TIMING_MARGIN_OBS_3
+
+#define LPDDR4__DENALI_PHY_780_READ_MASK 0x7F0101FFU
+#define LPDDR4__DENALI_PHY_780_WRITE_MASK 0x7F0101FFU
+#define LPDDR4__DENALI_PHY_780__PHY_DQ_IDLE_3_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_780__PHY_DQ_IDLE_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_780__PHY_DQ_IDLE_3_WIDTH 9U
+#define LPDDR4__PHY_DQ_IDLE_3__REG DENALI_PHY_780
+#define LPDDR4__PHY_DQ_IDLE_3__FLD LPDDR4__DENALI_PHY_780__PHY_DQ_IDLE_3
+
+#define LPDDR4__DENALI_PHY_780__PHY_PDA_MODE_EN_3_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_780__PHY_PDA_MODE_EN_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_780__PHY_PDA_MODE_EN_3_WIDTH 1U
+#define LPDDR4__DENALI_PHY_780__PHY_PDA_MODE_EN_3_WOCLR 0U
+#define LPDDR4__DENALI_PHY_780__PHY_PDA_MODE_EN_3_WOSET 0U
+#define LPDDR4__PHY_PDA_MODE_EN_3__REG DENALI_PHY_780
+#define LPDDR4__PHY_PDA_MODE_EN_3__FLD LPDDR4__DENALI_PHY_780__PHY_PDA_MODE_EN_3
+
+#define LPDDR4__DENALI_PHY_780__PHY_PRBS_PATTERN_START_3_MASK 0x7F000000U
+#define LPDDR4__DENALI_PHY_780__PHY_PRBS_PATTERN_START_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_780__PHY_PRBS_PATTERN_START_3_WIDTH 7U
+#define LPDDR4__PHY_PRBS_PATTERN_START_3__REG DENALI_PHY_780
+#define LPDDR4__PHY_PRBS_PATTERN_START_3__FLD LPDDR4__DENALI_PHY_780__PHY_PRBS_PATTERN_START_3
+
+#define LPDDR4__DENALI_PHY_781_READ_MASK 0x010101FFU
+#define LPDDR4__DENALI_PHY_781_WRITE_MASK 0x010101FFU
+#define LPDDR4__DENALI_PHY_781__PHY_PRBS_PATTERN_MASK_3_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_781__PHY_PRBS_PATTERN_MASK_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_781__PHY_PRBS_PATTERN_MASK_3_WIDTH 9U
+#define LPDDR4__PHY_PRBS_PATTERN_MASK_3__REG DENALI_PHY_781
+#define LPDDR4__PHY_PRBS_PATTERN_MASK_3__FLD LPDDR4__DENALI_PHY_781__PHY_PRBS_PATTERN_MASK_3
+
+#define LPDDR4__DENALI_PHY_781__PHY_RDLVL_MULTI_PATT_ENABLE_3_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_781__PHY_RDLVL_MULTI_PATT_ENABLE_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_781__PHY_RDLVL_MULTI_PATT_ENABLE_3_WIDTH 1U
+#define LPDDR4__DENALI_PHY_781__PHY_RDLVL_MULTI_PATT_ENABLE_3_WOCLR 0U
+#define LPDDR4__DENALI_PHY_781__PHY_RDLVL_MULTI_PATT_ENABLE_3_WOSET 0U
+#define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_3__REG DENALI_PHY_781
+#define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_3__FLD LPDDR4__DENALI_PHY_781__PHY_RDLVL_MULTI_PATT_ENABLE_3
+
+#define LPDDR4__DENALI_PHY_781__PHY_RDLVL_MULTI_PATT_RST_DISABLE_3_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_781__PHY_RDLVL_MULTI_PATT_RST_DISABLE_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_781__PHY_RDLVL_MULTI_PATT_RST_DISABLE_3_WIDTH 1U
+#define LPDDR4__DENALI_PHY_781__PHY_RDLVL_MULTI_PATT_RST_DISABLE_3_WOCLR 0U
+#define LPDDR4__DENALI_PHY_781__PHY_RDLVL_MULTI_PATT_RST_DISABLE_3_WOSET 0U
+#define LPDDR4__PHY_RDLVL_MULTI_PATT_RST_DISABLE_3__REG DENALI_PHY_781
+#define LPDDR4__PHY_RDLVL_MULTI_PATT_RST_DISABLE_3__FLD LPDDR4__DENALI_PHY_781__PHY_RDLVL_MULTI_PATT_RST_DISABLE_3
+
+#define LPDDR4__DENALI_PHY_782_READ_MASK 0x03FF7F3FU
+#define LPDDR4__DENALI_PHY_782_WRITE_MASK 0x03FF7F3FU
+#define LPDDR4__DENALI_PHY_782__PHY_VREF_INITIAL_STEPSIZE_3_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_782__PHY_VREF_INITIAL_STEPSIZE_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_782__PHY_VREF_INITIAL_STEPSIZE_3_WIDTH 6U
+#define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_3__REG DENALI_PHY_782
+#define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_3__FLD LPDDR4__DENALI_PHY_782__PHY_VREF_INITIAL_STEPSIZE_3
+
+#define LPDDR4__DENALI_PHY_782__PHY_VREF_TRAIN_OBS_3_MASK 0x00007F00U
+#define LPDDR4__DENALI_PHY_782__PHY_VREF_TRAIN_OBS_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_782__PHY_VREF_TRAIN_OBS_3_WIDTH 7U
+#define LPDDR4__PHY_VREF_TRAIN_OBS_3__REG DENALI_PHY_782
+#define LPDDR4__PHY_VREF_TRAIN_OBS_3__FLD LPDDR4__DENALI_PHY_782__PHY_VREF_TRAIN_OBS_3
+
+#define LPDDR4__DENALI_PHY_782__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_3_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_782__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_782__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_3_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_3__REG DENALI_PHY_782
+#define LPDDR4__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_782__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_783_READ_MASK 0x01FF000FU
+#define LPDDR4__DENALI_PHY_783_WRITE_MASK 0x01FF000FU
+#define LPDDR4__DENALI_PHY_783__PHY_GATE_ERROR_DELAY_SELECT_3_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_783__PHY_GATE_ERROR_DELAY_SELECT_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_783__PHY_GATE_ERROR_DELAY_SELECT_3_WIDTH 4U
+#define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_3__REG DENALI_PHY_783
+#define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_3__FLD LPDDR4__DENALI_PHY_783__PHY_GATE_ERROR_DELAY_SELECT_3
+
+#define LPDDR4__DENALI_PHY_783__SC_PHY_SNAP_OBS_REGS_3_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_783__SC_PHY_SNAP_OBS_REGS_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_783__SC_PHY_SNAP_OBS_REGS_3_WIDTH 1U
+#define LPDDR4__DENALI_PHY_783__SC_PHY_SNAP_OBS_REGS_3_WOCLR 0U
+#define LPDDR4__DENALI_PHY_783__SC_PHY_SNAP_OBS_REGS_3_WOSET 0U
+#define LPDDR4__SC_PHY_SNAP_OBS_REGS_3__REG DENALI_PHY_783
+#define LPDDR4__SC_PHY_SNAP_OBS_REGS_3__FLD LPDDR4__DENALI_PHY_783__SC_PHY_SNAP_OBS_REGS_3
+
+#define LPDDR4__DENALI_PHY_783__PHY_GATE_SMPL1_SLAVE_DELAY_3_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_783__PHY_GATE_SMPL1_SLAVE_DELAY_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_783__PHY_GATE_SMPL1_SLAVE_DELAY_3_WIDTH 9U
+#define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_3__REG DENALI_PHY_783
+#define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_783__PHY_GATE_SMPL1_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_784_READ_MASK 0x01FF0701U
+#define LPDDR4__DENALI_PHY_784_WRITE_MASK 0x01FF0701U
+#define LPDDR4__DENALI_PHY_784__PHY_LPDDR_3_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_784__PHY_LPDDR_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_784__PHY_LPDDR_3_WIDTH 1U
+#define LPDDR4__DENALI_PHY_784__PHY_LPDDR_3_WOCLR 0U
+#define LPDDR4__DENALI_PHY_784__PHY_LPDDR_3_WOSET 0U
+#define LPDDR4__PHY_LPDDR_3__REG DENALI_PHY_784
+#define LPDDR4__PHY_LPDDR_3__FLD LPDDR4__DENALI_PHY_784__PHY_LPDDR_3
+
+#define LPDDR4__DENALI_PHY_784__PHY_MEM_CLASS_3_MASK 0x00000700U
+#define LPDDR4__DENALI_PHY_784__PHY_MEM_CLASS_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_784__PHY_MEM_CLASS_3_WIDTH 3U
+#define LPDDR4__PHY_MEM_CLASS_3__REG DENALI_PHY_784
+#define LPDDR4__PHY_MEM_CLASS_3__FLD LPDDR4__DENALI_PHY_784__PHY_MEM_CLASS_3
+
+#define LPDDR4__DENALI_PHY_784__PHY_GATE_SMPL2_SLAVE_DELAY_3_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_784__PHY_GATE_SMPL2_SLAVE_DELAY_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_784__PHY_GATE_SMPL2_SLAVE_DELAY_3_WIDTH 9U
+#define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_3__REG DENALI_PHY_784
+#define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_784__PHY_GATE_SMPL2_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_785_READ_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_785_WRITE_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_785__ON_FLY_GATE_ADJUST_EN_3_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_785__ON_FLY_GATE_ADJUST_EN_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_785__ON_FLY_GATE_ADJUST_EN_3_WIDTH 2U
+#define LPDDR4__ON_FLY_GATE_ADJUST_EN_3__REG DENALI_PHY_785
+#define LPDDR4__ON_FLY_GATE_ADJUST_EN_3__FLD LPDDR4__DENALI_PHY_785__ON_FLY_GATE_ADJUST_EN_3
+
+#define LPDDR4__DENALI_PHY_786_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_786_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_786__PHY_GATE_TRACKING_OBS_3_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_786__PHY_GATE_TRACKING_OBS_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_786__PHY_GATE_TRACKING_OBS_3_WIDTH 32U
+#define LPDDR4__PHY_GATE_TRACKING_OBS_3__REG DENALI_PHY_786
+#define LPDDR4__PHY_GATE_TRACKING_OBS_3__FLD LPDDR4__DENALI_PHY_786__PHY_GATE_TRACKING_OBS_3
+
+#define LPDDR4__DENALI_PHY_787_READ_MASK 0x00000301U
+#define LPDDR4__DENALI_PHY_787_WRITE_MASK 0x00000301U
+#define LPDDR4__DENALI_PHY_787__PHY_DFI40_POLARITY_3_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_787__PHY_DFI40_POLARITY_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_787__PHY_DFI40_POLARITY_3_WIDTH 1U
+#define LPDDR4__DENALI_PHY_787__PHY_DFI40_POLARITY_3_WOCLR 0U
+#define LPDDR4__DENALI_PHY_787__PHY_DFI40_POLARITY_3_WOSET 0U
+#define LPDDR4__PHY_DFI40_POLARITY_3__REG DENALI_PHY_787
+#define LPDDR4__PHY_DFI40_POLARITY_3__FLD LPDDR4__DENALI_PHY_787__PHY_DFI40_POLARITY_3
+
+#define LPDDR4__DENALI_PHY_787__PHY_LP4_PST_AMBLE_3_MASK 0x00000300U
+#define LPDDR4__DENALI_PHY_787__PHY_LP4_PST_AMBLE_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_787__PHY_LP4_PST_AMBLE_3_WIDTH 2U
+#define LPDDR4__PHY_LP4_PST_AMBLE_3__REG DENALI_PHY_787
+#define LPDDR4__PHY_LP4_PST_AMBLE_3__FLD LPDDR4__DENALI_PHY_787__PHY_LP4_PST_AMBLE_3
+
+#define LPDDR4__DENALI_PHY_788_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_788_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_788__PHY_RDLVL_PATT8_3_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_788__PHY_RDLVL_PATT8_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_788__PHY_RDLVL_PATT8_3_WIDTH 32U
+#define LPDDR4__PHY_RDLVL_PATT8_3__REG DENALI_PHY_788
+#define LPDDR4__PHY_RDLVL_PATT8_3__FLD LPDDR4__DENALI_PHY_788__PHY_RDLVL_PATT8_3
+
+#define LPDDR4__DENALI_PHY_789_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_789_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_789__PHY_RDLVL_PATT9_3_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_789__PHY_RDLVL_PATT9_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_789__PHY_RDLVL_PATT9_3_WIDTH 32U
+#define LPDDR4__PHY_RDLVL_PATT9_3__REG DENALI_PHY_789
+#define LPDDR4__PHY_RDLVL_PATT9_3__FLD LPDDR4__DENALI_PHY_789__PHY_RDLVL_PATT9_3
+
+#define LPDDR4__DENALI_PHY_790_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_790_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_790__PHY_RDLVL_PATT10_3_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_790__PHY_RDLVL_PATT10_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_790__PHY_RDLVL_PATT10_3_WIDTH 32U
+#define LPDDR4__PHY_RDLVL_PATT10_3__REG DENALI_PHY_790
+#define LPDDR4__PHY_RDLVL_PATT10_3__FLD LPDDR4__DENALI_PHY_790__PHY_RDLVL_PATT10_3
+
+#define LPDDR4__DENALI_PHY_791_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_791_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_791__PHY_RDLVL_PATT11_3_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_791__PHY_RDLVL_PATT11_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_791__PHY_RDLVL_PATT11_3_WIDTH 32U
+#define LPDDR4__PHY_RDLVL_PATT11_3__REG DENALI_PHY_791
+#define LPDDR4__PHY_RDLVL_PATT11_3__FLD LPDDR4__DENALI_PHY_791__PHY_RDLVL_PATT11_3
+
+#define LPDDR4__DENALI_PHY_792_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_792_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_792__PHY_RDLVL_PATT12_3_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_792__PHY_RDLVL_PATT12_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_792__PHY_RDLVL_PATT12_3_WIDTH 32U
+#define LPDDR4__PHY_RDLVL_PATT12_3__REG DENALI_PHY_792
+#define LPDDR4__PHY_RDLVL_PATT12_3__FLD LPDDR4__DENALI_PHY_792__PHY_RDLVL_PATT12_3
+
+#define LPDDR4__DENALI_PHY_793_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_793_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_793__PHY_RDLVL_PATT13_3_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_793__PHY_RDLVL_PATT13_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_793__PHY_RDLVL_PATT13_3_WIDTH 32U
+#define LPDDR4__PHY_RDLVL_PATT13_3__REG DENALI_PHY_793
+#define LPDDR4__PHY_RDLVL_PATT13_3__FLD LPDDR4__DENALI_PHY_793__PHY_RDLVL_PATT13_3
+
+#define LPDDR4__DENALI_PHY_794_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_794_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_794__PHY_RDLVL_PATT14_3_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_794__PHY_RDLVL_PATT14_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_794__PHY_RDLVL_PATT14_3_WIDTH 32U
+#define LPDDR4__PHY_RDLVL_PATT14_3__REG DENALI_PHY_794
+#define LPDDR4__PHY_RDLVL_PATT14_3__FLD LPDDR4__DENALI_PHY_794__PHY_RDLVL_PATT14_3
+
+#define LPDDR4__DENALI_PHY_795_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_795_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_795__PHY_RDLVL_PATT15_3_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_795__PHY_RDLVL_PATT15_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_795__PHY_RDLVL_PATT15_3_WIDTH 32U
+#define LPDDR4__PHY_RDLVL_PATT15_3__REG DENALI_PHY_795
+#define LPDDR4__PHY_RDLVL_PATT15_3__FLD LPDDR4__DENALI_PHY_795__PHY_RDLVL_PATT15_3
+
+#define LPDDR4__DENALI_PHY_796_READ_MASK 0x070F0107U
+#define LPDDR4__DENALI_PHY_796_WRITE_MASK 0x070F0107U
+#define LPDDR4__DENALI_PHY_796__PHY_SLAVE_LOOP_CNT_UPDATE_3_MASK 0x00000007U
+#define LPDDR4__DENALI_PHY_796__PHY_SLAVE_LOOP_CNT_UPDATE_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_796__PHY_SLAVE_LOOP_CNT_UPDATE_3_WIDTH 3U
+#define LPDDR4__PHY_SLAVE_LOOP_CNT_UPDATE_3__REG DENALI_PHY_796
+#define LPDDR4__PHY_SLAVE_LOOP_CNT_UPDATE_3__FLD LPDDR4__DENALI_PHY_796__PHY_SLAVE_LOOP_CNT_UPDATE_3
+
+#define LPDDR4__DENALI_PHY_796__PHY_SW_FIFO_PTR_RST_DISABLE_3_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_796__PHY_SW_FIFO_PTR_RST_DISABLE_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_796__PHY_SW_FIFO_PTR_RST_DISABLE_3_WIDTH 1U
+#define LPDDR4__DENALI_PHY_796__PHY_SW_FIFO_PTR_RST_DISABLE_3_WOCLR 0U
+#define LPDDR4__DENALI_PHY_796__PHY_SW_FIFO_PTR_RST_DISABLE_3_WOSET 0U
+#define LPDDR4__PHY_SW_FIFO_PTR_RST_DISABLE_3__REG DENALI_PHY_796
+#define LPDDR4__PHY_SW_FIFO_PTR_RST_DISABLE_3__FLD LPDDR4__DENALI_PHY_796__PHY_SW_FIFO_PTR_RST_DISABLE_3
+
+#define LPDDR4__DENALI_PHY_796__PHY_MASTER_DLY_LOCK_OBS_SELECT_3_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_796__PHY_MASTER_DLY_LOCK_OBS_SELECT_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_796__PHY_MASTER_DLY_LOCK_OBS_SELECT_3_WIDTH 4U
+#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_SELECT_3__REG DENALI_PHY_796
+#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_796__PHY_MASTER_DLY_LOCK_OBS_SELECT_3
+
+#define LPDDR4__DENALI_PHY_796__PHY_RDDQ_ENC_OBS_SELECT_3_MASK 0x07000000U
+#define LPDDR4__DENALI_PHY_796__PHY_RDDQ_ENC_OBS_SELECT_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_796__PHY_RDDQ_ENC_OBS_SELECT_3_WIDTH 3U
+#define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_3__REG DENALI_PHY_796
+#define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_796__PHY_RDDQ_ENC_OBS_SELECT_3
+
+#define LPDDR4__DENALI_PHY_797_READ_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_797_WRITE_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_797__PHY_RDDQS_DQ_ENC_OBS_SELECT_3_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_797__PHY_RDDQS_DQ_ENC_OBS_SELECT_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_797__PHY_RDDQS_DQ_ENC_OBS_SELECT_3_WIDTH 4U
+#define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_3__REG DENALI_PHY_797
+#define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_797__PHY_RDDQS_DQ_ENC_OBS_SELECT_3
+
+#define LPDDR4__DENALI_PHY_797__PHY_WR_ENC_OBS_SELECT_3_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_797__PHY_WR_ENC_OBS_SELECT_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_797__PHY_WR_ENC_OBS_SELECT_3_WIDTH 4U
+#define LPDDR4__PHY_WR_ENC_OBS_SELECT_3__REG DENALI_PHY_797
+#define LPDDR4__PHY_WR_ENC_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_797__PHY_WR_ENC_OBS_SELECT_3
+
+#define LPDDR4__DENALI_PHY_797__PHY_WR_SHIFT_OBS_SELECT_3_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_797__PHY_WR_SHIFT_OBS_SELECT_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_797__PHY_WR_SHIFT_OBS_SELECT_3_WIDTH 4U
+#define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_3__REG DENALI_PHY_797
+#define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_797__PHY_WR_SHIFT_OBS_SELECT_3
+
+#define LPDDR4__DENALI_PHY_797__PHY_FIFO_PTR_OBS_SELECT_3_MASK 0x0F000000U
+#define LPDDR4__DENALI_PHY_797__PHY_FIFO_PTR_OBS_SELECT_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_797__PHY_FIFO_PTR_OBS_SELECT_3_WIDTH 4U
+#define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_3__REG DENALI_PHY_797
+#define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_797__PHY_FIFO_PTR_OBS_SELECT_3
+
+#define LPDDR4__DENALI_PHY_798_READ_MASK 0x3F030001U
+#define LPDDR4__DENALI_PHY_798_WRITE_MASK 0x3F030001U
+#define LPDDR4__DENALI_PHY_798__PHY_LVL_DEBUG_MODE_3_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_798__PHY_LVL_DEBUG_MODE_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_798__PHY_LVL_DEBUG_MODE_3_WIDTH 1U
+#define LPDDR4__DENALI_PHY_798__PHY_LVL_DEBUG_MODE_3_WOCLR 0U
+#define LPDDR4__DENALI_PHY_798__PHY_LVL_DEBUG_MODE_3_WOSET 0U
+#define LPDDR4__PHY_LVL_DEBUG_MODE_3__REG DENALI_PHY_798
+#define LPDDR4__PHY_LVL_DEBUG_MODE_3__FLD LPDDR4__DENALI_PHY_798__PHY_LVL_DEBUG_MODE_3
+
+#define LPDDR4__DENALI_PHY_798__SC_PHY_LVL_DEBUG_CONT_3_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_798__SC_PHY_LVL_DEBUG_CONT_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_798__SC_PHY_LVL_DEBUG_CONT_3_WIDTH 1U
+#define LPDDR4__DENALI_PHY_798__SC_PHY_LVL_DEBUG_CONT_3_WOCLR 0U
+#define LPDDR4__DENALI_PHY_798__SC_PHY_LVL_DEBUG_CONT_3_WOSET 0U
+#define LPDDR4__SC_PHY_LVL_DEBUG_CONT_3__REG DENALI_PHY_798
+#define LPDDR4__SC_PHY_LVL_DEBUG_CONT_3__FLD LPDDR4__DENALI_PHY_798__SC_PHY_LVL_DEBUG_CONT_3
+
+#define LPDDR4__DENALI_PHY_798__PHY_WRLVL_ALGO_3_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_798__PHY_WRLVL_ALGO_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_798__PHY_WRLVL_ALGO_3_WIDTH 2U
+#define LPDDR4__PHY_WRLVL_ALGO_3__REG DENALI_PHY_798
+#define LPDDR4__PHY_WRLVL_ALGO_3__FLD LPDDR4__DENALI_PHY_798__PHY_WRLVL_ALGO_3
+
+#define LPDDR4__DENALI_PHY_798__PHY_WRLVL_CAPTURE_CNT_3_MASK 0x3F000000U
+#define LPDDR4__DENALI_PHY_798__PHY_WRLVL_CAPTURE_CNT_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_798__PHY_WRLVL_CAPTURE_CNT_3_WIDTH 6U
+#define LPDDR4__PHY_WRLVL_CAPTURE_CNT_3__REG DENALI_PHY_798
+#define LPDDR4__PHY_WRLVL_CAPTURE_CNT_3__FLD LPDDR4__DENALI_PHY_798__PHY_WRLVL_CAPTURE_CNT_3
+
+#define LPDDR4__DENALI_PHY_799_READ_MASK 0x0F3FFF0FU
+#define LPDDR4__DENALI_PHY_799_WRITE_MASK 0x0F3FFF0FU
+#define LPDDR4__DENALI_PHY_799__PHY_WRLVL_UPDT_WAIT_CNT_3_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_799__PHY_WRLVL_UPDT_WAIT_CNT_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_799__PHY_WRLVL_UPDT_WAIT_CNT_3_WIDTH 4U
+#define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_3__REG DENALI_PHY_799
+#define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_3__FLD LPDDR4__DENALI_PHY_799__PHY_WRLVL_UPDT_WAIT_CNT_3
+
+#define LPDDR4__DENALI_PHY_799__PHY_DQ_MASK_3_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_799__PHY_DQ_MASK_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_799__PHY_DQ_MASK_3_WIDTH 8U
+#define LPDDR4__PHY_DQ_MASK_3__REG DENALI_PHY_799
+#define LPDDR4__PHY_DQ_MASK_3__FLD LPDDR4__DENALI_PHY_799__PHY_DQ_MASK_3
+
+#define LPDDR4__DENALI_PHY_799__PHY_GTLVL_CAPTURE_CNT_3_MASK 0x003F0000U
+#define LPDDR4__DENALI_PHY_799__PHY_GTLVL_CAPTURE_CNT_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_799__PHY_GTLVL_CAPTURE_CNT_3_WIDTH 6U
+#define LPDDR4__PHY_GTLVL_CAPTURE_CNT_3__REG DENALI_PHY_799
+#define LPDDR4__PHY_GTLVL_CAPTURE_CNT_3__FLD LPDDR4__DENALI_PHY_799__PHY_GTLVL_CAPTURE_CNT_3
+
+#define LPDDR4__DENALI_PHY_799__PHY_GTLVL_UPDT_WAIT_CNT_3_MASK 0x0F000000U
+#define LPDDR4__DENALI_PHY_799__PHY_GTLVL_UPDT_WAIT_CNT_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_799__PHY_GTLVL_UPDT_WAIT_CNT_3_WIDTH 4U
+#define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_3__REG DENALI_PHY_799
+#define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_3__FLD LPDDR4__DENALI_PHY_799__PHY_GTLVL_UPDT_WAIT_CNT_3
+
+#define LPDDR4__DENALI_PHY_800_READ_MASK 0x1F030F3FU
+#define LPDDR4__DENALI_PHY_800_WRITE_MASK 0x1F030F3FU
+#define LPDDR4__DENALI_PHY_800__PHY_RDLVL_CAPTURE_CNT_3_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_800__PHY_RDLVL_CAPTURE_CNT_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_800__PHY_RDLVL_CAPTURE_CNT_3_WIDTH 6U
+#define LPDDR4__PHY_RDLVL_CAPTURE_CNT_3__REG DENALI_PHY_800
+#define LPDDR4__PHY_RDLVL_CAPTURE_CNT_3__FLD LPDDR4__DENALI_PHY_800__PHY_RDLVL_CAPTURE_CNT_3
+
+#define LPDDR4__DENALI_PHY_800__PHY_RDLVL_UPDT_WAIT_CNT_3_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_800__PHY_RDLVL_UPDT_WAIT_CNT_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_800__PHY_RDLVL_UPDT_WAIT_CNT_3_WIDTH 4U
+#define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_3__REG DENALI_PHY_800
+#define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_3__FLD LPDDR4__DENALI_PHY_800__PHY_RDLVL_UPDT_WAIT_CNT_3
+
+#define LPDDR4__DENALI_PHY_800__PHY_RDLVL_OP_MODE_3_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_800__PHY_RDLVL_OP_MODE_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_800__PHY_RDLVL_OP_MODE_3_WIDTH 2U
+#define LPDDR4__PHY_RDLVL_OP_MODE_3__REG DENALI_PHY_800
+#define LPDDR4__PHY_RDLVL_OP_MODE_3__FLD LPDDR4__DENALI_PHY_800__PHY_RDLVL_OP_MODE_3
+
+#define LPDDR4__DENALI_PHY_800__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_3_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_800__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_800__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_3_WIDTH 5U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_3__REG DENALI_PHY_800
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_800__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_3
+
+#define LPDDR4__DENALI_PHY_801_READ_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_801_WRITE_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_801__PHY_RDLVL_DATA_MASK_3_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_801__PHY_RDLVL_DATA_MASK_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_801__PHY_RDLVL_DATA_MASK_3_WIDTH 8U
+#define LPDDR4__PHY_RDLVL_DATA_MASK_3__REG DENALI_PHY_801
+#define LPDDR4__PHY_RDLVL_DATA_MASK_3__FLD LPDDR4__DENALI_PHY_801__PHY_RDLVL_DATA_MASK_3
+
+#define LPDDR4__DENALI_PHY_801__PHY_RDLVL_DATA_SWIZZLE_3_MASK 0x03FFFF00U
+#define LPDDR4__DENALI_PHY_801__PHY_RDLVL_DATA_SWIZZLE_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_801__PHY_RDLVL_DATA_SWIZZLE_3_WIDTH 18U
+#define LPDDR4__PHY_RDLVL_DATA_SWIZZLE_3__REG DENALI_PHY_801
+#define LPDDR4__PHY_RDLVL_DATA_SWIZZLE_3__FLD LPDDR4__DENALI_PHY_801__PHY_RDLVL_DATA_SWIZZLE_3
+
+#define LPDDR4__DENALI_PHY_802_READ_MASK 0x00073FFFU
+#define LPDDR4__DENALI_PHY_802_WRITE_MASK 0x00073FFFU
+#define LPDDR4__DENALI_PHY_802__PHY_WDQLVL_CLK_JITTER_TOLERANCE_3_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_802__PHY_WDQLVL_CLK_JITTER_TOLERANCE_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_802__PHY_WDQLVL_CLK_JITTER_TOLERANCE_3_WIDTH 8U
+#define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_3__REG DENALI_PHY_802
+#define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_3__FLD LPDDR4__DENALI_PHY_802__PHY_WDQLVL_CLK_JITTER_TOLERANCE_3
+
+#define LPDDR4__DENALI_PHY_802__PHY_WDQLVL_BURST_CNT_3_MASK 0x00003F00U
+#define LPDDR4__DENALI_PHY_802__PHY_WDQLVL_BURST_CNT_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_802__PHY_WDQLVL_BURST_CNT_3_WIDTH 6U
+#define LPDDR4__PHY_WDQLVL_BURST_CNT_3__REG DENALI_PHY_802
+#define LPDDR4__PHY_WDQLVL_BURST_CNT_3__FLD LPDDR4__DENALI_PHY_802__PHY_WDQLVL_BURST_CNT_3
+
+#define LPDDR4__DENALI_PHY_802__PHY_WDQLVL_PATT_3_MASK 0x00070000U
+#define LPDDR4__DENALI_PHY_802__PHY_WDQLVL_PATT_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_802__PHY_WDQLVL_PATT_3_WIDTH 3U
+#define LPDDR4__PHY_WDQLVL_PATT_3__REG DENALI_PHY_802
+#define LPDDR4__PHY_WDQLVL_PATT_3__FLD LPDDR4__DENALI_PHY_802__PHY_WDQLVL_PATT_3
+
+#define LPDDR4__DENALI_PHY_803_READ_MASK 0x0F0F07FFU
+#define LPDDR4__DENALI_PHY_803_WRITE_MASK 0x0F0F07FFU
+#define LPDDR4__DENALI_PHY_803__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_3_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_803__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_803__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_3_WIDTH 11U
+#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_3__REG DENALI_PHY_803
+#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_3__FLD LPDDR4__DENALI_PHY_803__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_3
+
+#define LPDDR4__DENALI_PHY_803__PHY_WDQLVL_UPDT_WAIT_CNT_3_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_803__PHY_WDQLVL_UPDT_WAIT_CNT_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_803__PHY_WDQLVL_UPDT_WAIT_CNT_3_WIDTH 4U
+#define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_3__REG DENALI_PHY_803
+#define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_3__FLD LPDDR4__DENALI_PHY_803__PHY_WDQLVL_UPDT_WAIT_CNT_3
+
+#define LPDDR4__DENALI_PHY_803__PHY_WDQLVL_DQDM_OBS_SELECT_3_MASK 0x0F000000U
+#define LPDDR4__DENALI_PHY_803__PHY_WDQLVL_DQDM_OBS_SELECT_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_803__PHY_WDQLVL_DQDM_OBS_SELECT_3_WIDTH 4U
+#define LPDDR4__PHY_WDQLVL_DQDM_OBS_SELECT_3__REG DENALI_PHY_803
+#define LPDDR4__PHY_WDQLVL_DQDM_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_803__PHY_WDQLVL_DQDM_OBS_SELECT_3
+
+#define LPDDR4__DENALI_PHY_804_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_804_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_804__PHY_WDQLVL_PERIODIC_OBS_SELECT_3_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_804__PHY_WDQLVL_PERIODIC_OBS_SELECT_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_804__PHY_WDQLVL_PERIODIC_OBS_SELECT_3_WIDTH 8U
+#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_SELECT_3__REG DENALI_PHY_804
+#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_804__PHY_WDQLVL_PERIODIC_OBS_SELECT_3
+
+#define LPDDR4__DENALI_PHY_804__PHY_WDQLVL_DQ_SLV_DELTA_3_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_804__PHY_WDQLVL_DQ_SLV_DELTA_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_804__PHY_WDQLVL_DQ_SLV_DELTA_3_WIDTH 8U
+#define LPDDR4__PHY_WDQLVL_DQ_SLV_DELTA_3__REG DENALI_PHY_804
+#define LPDDR4__PHY_WDQLVL_DQ_SLV_DELTA_3__FLD LPDDR4__DENALI_PHY_804__PHY_WDQLVL_DQ_SLV_DELTA_3
+
+#define LPDDR4__DENALI_PHY_804__PHY_WDQLVL_DM_DLY_STEP_3_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_804__PHY_WDQLVL_DM_DLY_STEP_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_804__PHY_WDQLVL_DM_DLY_STEP_3_WIDTH 4U
+#define LPDDR4__PHY_WDQLVL_DM_DLY_STEP_3__REG DENALI_PHY_804
+#define LPDDR4__PHY_WDQLVL_DM_DLY_STEP_3__FLD LPDDR4__DENALI_PHY_804__PHY_WDQLVL_DM_DLY_STEP_3
+
+#define LPDDR4__DENALI_PHY_804__SC_PHY_WDQLVL_CLR_PREV_RESULTS_3_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_804__SC_PHY_WDQLVL_CLR_PREV_RESULTS_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_804__SC_PHY_WDQLVL_CLR_PREV_RESULTS_3_WIDTH 1U
+#define LPDDR4__DENALI_PHY_804__SC_PHY_WDQLVL_CLR_PREV_RESULTS_3_WOCLR 0U
+#define LPDDR4__DENALI_PHY_804__SC_PHY_WDQLVL_CLR_PREV_RESULTS_3_WOSET 0U
+#define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_3__REG DENALI_PHY_804
+#define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_3__FLD LPDDR4__DENALI_PHY_804__SC_PHY_WDQLVL_CLR_PREV_RESULTS_3
+
+#define LPDDR4__DENALI_PHY_805_READ_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_805_WRITE_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_805__PHY_WDQLVL_DATADM_MASK_3_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_805__PHY_WDQLVL_DATADM_MASK_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_805__PHY_WDQLVL_DATADM_MASK_3_WIDTH 9U
+#define LPDDR4__PHY_WDQLVL_DATADM_MASK_3__REG DENALI_PHY_805
+#define LPDDR4__PHY_WDQLVL_DATADM_MASK_3__FLD LPDDR4__DENALI_PHY_805__PHY_WDQLVL_DATADM_MASK_3
+
+#define LPDDR4__DENALI_PHY_806_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_806_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_806__PHY_USER_PATT0_3_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_806__PHY_USER_PATT0_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_806__PHY_USER_PATT0_3_WIDTH 32U
+#define LPDDR4__PHY_USER_PATT0_3__REG DENALI_PHY_806
+#define LPDDR4__PHY_USER_PATT0_3__FLD LPDDR4__DENALI_PHY_806__PHY_USER_PATT0_3
+
+#define LPDDR4__DENALI_PHY_807_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_807_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_807__PHY_USER_PATT1_3_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_807__PHY_USER_PATT1_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_807__PHY_USER_PATT1_3_WIDTH 32U
+#define LPDDR4__PHY_USER_PATT1_3__REG DENALI_PHY_807
+#define LPDDR4__PHY_USER_PATT1_3__FLD LPDDR4__DENALI_PHY_807__PHY_USER_PATT1_3
+
+#define LPDDR4__DENALI_PHY_808_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_808_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_808__PHY_USER_PATT2_3_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_808__PHY_USER_PATT2_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_808__PHY_USER_PATT2_3_WIDTH 32U
+#define LPDDR4__PHY_USER_PATT2_3__REG DENALI_PHY_808
+#define LPDDR4__PHY_USER_PATT2_3__FLD LPDDR4__DENALI_PHY_808__PHY_USER_PATT2_3
+
+#define LPDDR4__DENALI_PHY_809_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_809_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_809__PHY_USER_PATT3_3_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_809__PHY_USER_PATT3_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_809__PHY_USER_PATT3_3_WIDTH 32U
+#define LPDDR4__PHY_USER_PATT3_3__REG DENALI_PHY_809
+#define LPDDR4__PHY_USER_PATT3_3__FLD LPDDR4__DENALI_PHY_809__PHY_USER_PATT3_3
+
+#define LPDDR4__DENALI_PHY_810_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PHY_810_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PHY_810__PHY_USER_PATT4_3_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_810__PHY_USER_PATT4_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_810__PHY_USER_PATT4_3_WIDTH 16U
+#define LPDDR4__PHY_USER_PATT4_3__REG DENALI_PHY_810
+#define LPDDR4__PHY_USER_PATT4_3__FLD LPDDR4__DENALI_PHY_810__PHY_USER_PATT4_3
+
+#define LPDDR4__DENALI_PHY_810__PHY_NTP_MULT_TRAIN_3_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_810__PHY_NTP_MULT_TRAIN_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_810__PHY_NTP_MULT_TRAIN_3_WIDTH 1U
+#define LPDDR4__DENALI_PHY_810__PHY_NTP_MULT_TRAIN_3_WOCLR 0U
+#define LPDDR4__DENALI_PHY_810__PHY_NTP_MULT_TRAIN_3_WOSET 0U
+#define LPDDR4__PHY_NTP_MULT_TRAIN_3__REG DENALI_PHY_810
+#define LPDDR4__PHY_NTP_MULT_TRAIN_3__FLD LPDDR4__DENALI_PHY_810__PHY_NTP_MULT_TRAIN_3
+
+#define LPDDR4__DENALI_PHY_811_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_811_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_811__PHY_NTP_EARLY_THRESHOLD_3_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_811__PHY_NTP_EARLY_THRESHOLD_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_811__PHY_NTP_EARLY_THRESHOLD_3_WIDTH 10U
+#define LPDDR4__PHY_NTP_EARLY_THRESHOLD_3__REG DENALI_PHY_811
+#define LPDDR4__PHY_NTP_EARLY_THRESHOLD_3__FLD LPDDR4__DENALI_PHY_811__PHY_NTP_EARLY_THRESHOLD_3
+
+#define LPDDR4__DENALI_PHY_811__PHY_NTP_PERIOD_THRESHOLD_3_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_811__PHY_NTP_PERIOD_THRESHOLD_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_811__PHY_NTP_PERIOD_THRESHOLD_3_WIDTH 10U
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_3__REG DENALI_PHY_811
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_3__FLD LPDDR4__DENALI_PHY_811__PHY_NTP_PERIOD_THRESHOLD_3
+
+#define LPDDR4__DENALI_PHY_812_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_812_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_812__PHY_NTP_PERIOD_THRESHOLD_MIN_3_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_812__PHY_NTP_PERIOD_THRESHOLD_MIN_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_812__PHY_NTP_PERIOD_THRESHOLD_MIN_3_WIDTH 10U
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MIN_3__REG DENALI_PHY_812
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MIN_3__FLD LPDDR4__DENALI_PHY_812__PHY_NTP_PERIOD_THRESHOLD_MIN_3
+
+#define LPDDR4__DENALI_PHY_812__PHY_NTP_PERIOD_THRESHOLD_MAX_3_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_812__PHY_NTP_PERIOD_THRESHOLD_MAX_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_812__PHY_NTP_PERIOD_THRESHOLD_MAX_3_WIDTH 10U
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_3__REG DENALI_PHY_812
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_3__FLD LPDDR4__DENALI_PHY_812__PHY_NTP_PERIOD_THRESHOLD_MAX_3
+
+#define LPDDR4__DENALI_PHY_813_READ_MASK 0x00FF0001U
+#define LPDDR4__DENALI_PHY_813_WRITE_MASK 0x00FF0001U
+#define LPDDR4__DENALI_PHY_813__PHY_CALVL_VREF_DRIVING_SLICE_3_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_813__PHY_CALVL_VREF_DRIVING_SLICE_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_813__PHY_CALVL_VREF_DRIVING_SLICE_3_WIDTH 1U
+#define LPDDR4__DENALI_PHY_813__PHY_CALVL_VREF_DRIVING_SLICE_3_WOCLR 0U
+#define LPDDR4__DENALI_PHY_813__PHY_CALVL_VREF_DRIVING_SLICE_3_WOSET 0U
+#define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_3__REG DENALI_PHY_813
+#define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_3__FLD LPDDR4__DENALI_PHY_813__PHY_CALVL_VREF_DRIVING_SLICE_3
+
+#define LPDDR4__DENALI_PHY_813__SC_PHY_MANUAL_CLEAR_3_MASK 0x00003F00U
+#define LPDDR4__DENALI_PHY_813__SC_PHY_MANUAL_CLEAR_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_813__SC_PHY_MANUAL_CLEAR_3_WIDTH 6U
+#define LPDDR4__SC_PHY_MANUAL_CLEAR_3__REG DENALI_PHY_813
+#define LPDDR4__SC_PHY_MANUAL_CLEAR_3__FLD LPDDR4__DENALI_PHY_813__SC_PHY_MANUAL_CLEAR_3
+
+#define LPDDR4__DENALI_PHY_813__PHY_FIFO_PTR_OBS_3_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_813__PHY_FIFO_PTR_OBS_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_813__PHY_FIFO_PTR_OBS_3_WIDTH 8U
+#define LPDDR4__PHY_FIFO_PTR_OBS_3__REG DENALI_PHY_813
+#define LPDDR4__PHY_FIFO_PTR_OBS_3__FLD LPDDR4__DENALI_PHY_813__PHY_FIFO_PTR_OBS_3
+
+#define LPDDR4__DENALI_PHY_814_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_814_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_814__PHY_LPBK_RESULT_OBS_3_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_814__PHY_LPBK_RESULT_OBS_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_814__PHY_LPBK_RESULT_OBS_3_WIDTH 32U
+#define LPDDR4__PHY_LPBK_RESULT_OBS_3__REG DENALI_PHY_814
+#define LPDDR4__PHY_LPBK_RESULT_OBS_3__FLD LPDDR4__DENALI_PHY_814__PHY_LPBK_RESULT_OBS_3
+
+#define LPDDR4__DENALI_PHY_815_READ_MASK 0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_815_WRITE_MASK 0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_815__PHY_LPBK_ERROR_COUNT_OBS_3_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_815__PHY_LPBK_ERROR_COUNT_OBS_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_815__PHY_LPBK_ERROR_COUNT_OBS_3_WIDTH 16U
+#define LPDDR4__PHY_LPBK_ERROR_COUNT_OBS_3__REG DENALI_PHY_815
+#define LPDDR4__PHY_LPBK_ERROR_COUNT_OBS_3__FLD LPDDR4__DENALI_PHY_815__PHY_LPBK_ERROR_COUNT_OBS_3
+
+#define LPDDR4__DENALI_PHY_815__PHY_MASTER_DLY_LOCK_OBS_3_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_815__PHY_MASTER_DLY_LOCK_OBS_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_815__PHY_MASTER_DLY_LOCK_OBS_3_WIDTH 11U
+#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_3__REG DENALI_PHY_815
+#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_3__FLD LPDDR4__DENALI_PHY_815__PHY_MASTER_DLY_LOCK_OBS_3
+
+#define LPDDR4__DENALI_PHY_816_READ_MASK 0xFFFF7F7FU
+#define LPDDR4__DENALI_PHY_816_WRITE_MASK 0xFFFF7F7FU
+#define LPDDR4__DENALI_PHY_816__PHY_RDDQ_SLV_DLY_ENC_OBS_3_MASK 0x0000007FU
+#define LPDDR4__DENALI_PHY_816__PHY_RDDQ_SLV_DLY_ENC_OBS_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_816__PHY_RDDQ_SLV_DLY_ENC_OBS_3_WIDTH 7U
+#define LPDDR4__PHY_RDDQ_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_816
+#define LPDDR4__PHY_RDDQ_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_816__PHY_RDDQ_SLV_DLY_ENC_OBS_3
+
+#define LPDDR4__DENALI_PHY_816__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_3_MASK 0x00007F00U
+#define LPDDR4__DENALI_PHY_816__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_816__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_3_WIDTH 7U
+#define LPDDR4__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_816
+#define LPDDR4__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_816__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_3
+
+#define LPDDR4__DENALI_PHY_816__PHY_MEAS_DLY_STEP_VALUE_3_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_816__PHY_MEAS_DLY_STEP_VALUE_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_816__PHY_MEAS_DLY_STEP_VALUE_3_WIDTH 8U
+#define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_3__REG DENALI_PHY_816
+#define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_3__FLD LPDDR4__DENALI_PHY_816__PHY_MEAS_DLY_STEP_VALUE_3
+
+#define LPDDR4__DENALI_PHY_816__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_3_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_816__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_816__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_3_WIDTH 8U
+#define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_816
+#define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_816__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_3
+
+#define LPDDR4__DENALI_PHY_817_READ_MASK 0x7F07FFFFU
+#define LPDDR4__DENALI_PHY_817_WRITE_MASK 0x7F07FFFFU
+#define LPDDR4__DENALI_PHY_817__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_3_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_817__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_817__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_3_WIDTH 8U
+#define LPDDR4__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_817
+#define LPDDR4__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_817__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_3
+
+#define LPDDR4__DENALI_PHY_817__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_3_MASK 0x0007FF00U
+#define LPDDR4__DENALI_PHY_817__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_817__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_3_WIDTH 11U
+#define LPDDR4__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_817
+#define LPDDR4__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_817__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_3
+
+#define LPDDR4__DENALI_PHY_817__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_3_MASK 0x7F000000U
+#define LPDDR4__DENALI_PHY_817__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_817__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_3_WIDTH 7U
+#define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_817
+#define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_817__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_3
+
+#define LPDDR4__DENALI_PHY_818_READ_MASK 0x0007FFFFU
+#define LPDDR4__DENALI_PHY_818_WRITE_MASK 0x0007FFFFU
+#define LPDDR4__DENALI_PHY_818__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_3_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_818__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_818__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_3_WIDTH 8U
+#define LPDDR4__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_818
+#define LPDDR4__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_818__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_3
+
+#define LPDDR4__DENALI_PHY_818__PHY_WR_ADDER_SLV_DLY_ENC_OBS_3_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_818__PHY_WR_ADDER_SLV_DLY_ENC_OBS_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_818__PHY_WR_ADDER_SLV_DLY_ENC_OBS_3_WIDTH 8U
+#define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_818
+#define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_818__PHY_WR_ADDER_SLV_DLY_ENC_OBS_3
+
+#define LPDDR4__DENALI_PHY_818__PHY_WR_SHIFT_OBS_3_MASK 0x00070000U
+#define LPDDR4__DENALI_PHY_818__PHY_WR_SHIFT_OBS_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_818__PHY_WR_SHIFT_OBS_3_WIDTH 3U
+#define LPDDR4__PHY_WR_SHIFT_OBS_3__REG DENALI_PHY_818
+#define LPDDR4__PHY_WR_SHIFT_OBS_3__FLD LPDDR4__DENALI_PHY_818__PHY_WR_SHIFT_OBS_3
+
+#define LPDDR4__DENALI_PHY_819_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_819_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_819__PHY_WRLVL_HARD0_DELAY_OBS_3_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_819__PHY_WRLVL_HARD0_DELAY_OBS_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_819__PHY_WRLVL_HARD0_DELAY_OBS_3_WIDTH 10U
+#define LPDDR4__PHY_WRLVL_HARD0_DELAY_OBS_3__REG DENALI_PHY_819
+#define LPDDR4__PHY_WRLVL_HARD0_DELAY_OBS_3__FLD LPDDR4__DENALI_PHY_819__PHY_WRLVL_HARD0_DELAY_OBS_3
+
+#define LPDDR4__DENALI_PHY_819__PHY_WRLVL_HARD1_DELAY_OBS_3_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_819__PHY_WRLVL_HARD1_DELAY_OBS_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_819__PHY_WRLVL_HARD1_DELAY_OBS_3_WIDTH 10U
+#define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_3__REG DENALI_PHY_819
+#define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_3__FLD LPDDR4__DENALI_PHY_819__PHY_WRLVL_HARD1_DELAY_OBS_3
+
+#define LPDDR4__DENALI_PHY_820_READ_MASK 0x001FFFFFU
+#define LPDDR4__DENALI_PHY_820_WRITE_MASK 0x001FFFFFU
+#define LPDDR4__DENALI_PHY_820__PHY_WRLVL_STATUS_OBS_3_MASK 0x001FFFFFU
+#define LPDDR4__DENALI_PHY_820__PHY_WRLVL_STATUS_OBS_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_820__PHY_WRLVL_STATUS_OBS_3_WIDTH 21U
+#define LPDDR4__PHY_WRLVL_STATUS_OBS_3__REG DENALI_PHY_820
+#define LPDDR4__PHY_WRLVL_STATUS_OBS_3__FLD LPDDR4__DENALI_PHY_820__PHY_WRLVL_STATUS_OBS_3
+
+#define LPDDR4__DENALI_PHY_821_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_821_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_821__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_3_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_821__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_821__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_3_WIDTH 10U
+#define LPDDR4__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_821
+#define LPDDR4__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_821__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_3
+
+#define LPDDR4__DENALI_PHY_821__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_3_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_821__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_821__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_3_WIDTH 10U
+#define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_821
+#define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_821__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_3
+
+#define LPDDR4__DENALI_PHY_822_READ_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_822_WRITE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_822__PHY_WRLVL_ERROR_OBS_3_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_822__PHY_WRLVL_ERROR_OBS_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_822__PHY_WRLVL_ERROR_OBS_3_WIDTH 16U
+#define LPDDR4__PHY_WRLVL_ERROR_OBS_3__REG DENALI_PHY_822
+#define LPDDR4__PHY_WRLVL_ERROR_OBS_3__FLD LPDDR4__DENALI_PHY_822__PHY_WRLVL_ERROR_OBS_3
+
+#define LPDDR4__DENALI_PHY_822__PHY_GTLVL_HARD0_DELAY_OBS_3_MASK 0x3FFF0000U
+#define LPDDR4__DENALI_PHY_822__PHY_GTLVL_HARD0_DELAY_OBS_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_822__PHY_GTLVL_HARD0_DELAY_OBS_3_WIDTH 14U
+#define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_3__REG DENALI_PHY_822
+#define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_3__FLD LPDDR4__DENALI_PHY_822__PHY_GTLVL_HARD0_DELAY_OBS_3
+
+#define LPDDR4__DENALI_PHY_823_READ_MASK 0x00003FFFU
+#define LPDDR4__DENALI_PHY_823_WRITE_MASK 0x00003FFFU
+#define LPDDR4__DENALI_PHY_823__PHY_GTLVL_HARD1_DELAY_OBS_3_MASK 0x00003FFFU
+#define LPDDR4__DENALI_PHY_823__PHY_GTLVL_HARD1_DELAY_OBS_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_823__PHY_GTLVL_HARD1_DELAY_OBS_3_WIDTH 14U
+#define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_3__REG DENALI_PHY_823
+#define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_3__FLD LPDDR4__DENALI_PHY_823__PHY_GTLVL_HARD1_DELAY_OBS_3
+
+#define LPDDR4__DENALI_PHY_824_READ_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_824_WRITE_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_824__PHY_GTLVL_STATUS_OBS_3_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_824__PHY_GTLVL_STATUS_OBS_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_824__PHY_GTLVL_STATUS_OBS_3_WIDTH 18U
+#define LPDDR4__PHY_GTLVL_STATUS_OBS_3__REG DENALI_PHY_824
+#define LPDDR4__PHY_GTLVL_STATUS_OBS_3__FLD LPDDR4__DENALI_PHY_824__PHY_GTLVL_STATUS_OBS_3
+
+#define LPDDR4__DENALI_PHY_825_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_825_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_825__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_3_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_825__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_825__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_3_WIDTH 10U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_3__REG DENALI_PHY_825
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_3__FLD LPDDR4__DENALI_PHY_825__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_3
+
+#define LPDDR4__DENALI_PHY_825__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_3_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_825__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_825__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_3_WIDTH 10U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_3__REG DENALI_PHY_825
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_3__FLD LPDDR4__DENALI_PHY_825__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_3
+
+#define LPDDR4__DENALI_PHY_826_READ_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_826_WRITE_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_826__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_3_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_826__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_826__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_3_WIDTH 2U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_3__REG DENALI_PHY_826
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_3__FLD LPDDR4__DENALI_PHY_826__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_3
+
+#define LPDDR4__DENALI_PHY_827_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_827_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_827__PHY_RDLVL_STATUS_OBS_3_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_827__PHY_RDLVL_STATUS_OBS_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_827__PHY_RDLVL_STATUS_OBS_3_WIDTH 32U
+#define LPDDR4__PHY_RDLVL_STATUS_OBS_3__REG DENALI_PHY_827
+#define LPDDR4__PHY_RDLVL_STATUS_OBS_3__FLD LPDDR4__DENALI_PHY_827__PHY_RDLVL_STATUS_OBS_3
+
+#define LPDDR4__DENALI_PHY_828_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_828_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_828__PHY_WDQLVL_DQDM_LE_DLY_OBS_3_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_828__PHY_WDQLVL_DQDM_LE_DLY_OBS_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_828__PHY_WDQLVL_DQDM_LE_DLY_OBS_3_WIDTH 11U
+#define LPDDR4__PHY_WDQLVL_DQDM_LE_DLY_OBS_3__REG DENALI_PHY_828
+#define LPDDR4__PHY_WDQLVL_DQDM_LE_DLY_OBS_3__FLD LPDDR4__DENALI_PHY_828__PHY_WDQLVL_DQDM_LE_DLY_OBS_3
+
+#define LPDDR4__DENALI_PHY_828__PHY_WDQLVL_DQDM_TE_DLY_OBS_3_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_828__PHY_WDQLVL_DQDM_TE_DLY_OBS_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_828__PHY_WDQLVL_DQDM_TE_DLY_OBS_3_WIDTH 11U
+#define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_3__REG DENALI_PHY_828
+#define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_3__FLD LPDDR4__DENALI_PHY_828__PHY_WDQLVL_DQDM_TE_DLY_OBS_3
+
+#define LPDDR4__DENALI_PHY_829_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_829_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_829__PHY_WDQLVL_STATUS_OBS_3_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_829__PHY_WDQLVL_STATUS_OBS_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_829__PHY_WDQLVL_STATUS_OBS_3_WIDTH 32U
+#define LPDDR4__PHY_WDQLVL_STATUS_OBS_3__REG DENALI_PHY_829
+#define LPDDR4__PHY_WDQLVL_STATUS_OBS_3__FLD LPDDR4__DENALI_PHY_829__PHY_WDQLVL_STATUS_OBS_3
+
+#define LPDDR4__DENALI_PHY_830_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_830_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_830__PHY_WDQLVL_PERIODIC_OBS_3_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_830__PHY_WDQLVL_PERIODIC_OBS_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_830__PHY_WDQLVL_PERIODIC_OBS_3_WIDTH 32U
+#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_3__REG DENALI_PHY_830
+#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_3__FLD LPDDR4__DENALI_PHY_830__PHY_WDQLVL_PERIODIC_OBS_3
+
+#define LPDDR4__DENALI_PHY_831_READ_MASK 0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_831_WRITE_MASK 0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_831__PHY_DDL_MODE_3_MASK 0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_831__PHY_DDL_MODE_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_831__PHY_DDL_MODE_3_WIDTH 31U
+#define LPDDR4__PHY_DDL_MODE_3__REG DENALI_PHY_831
+#define LPDDR4__PHY_DDL_MODE_3__FLD LPDDR4__DENALI_PHY_831__PHY_DDL_MODE_3
+
+#define LPDDR4__DENALI_PHY_832_READ_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_832_WRITE_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_832__PHY_DDL_MASK_3_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_832__PHY_DDL_MASK_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_832__PHY_DDL_MASK_3_WIDTH 6U
+#define LPDDR4__PHY_DDL_MASK_3__REG DENALI_PHY_832
+#define LPDDR4__PHY_DDL_MASK_3__FLD LPDDR4__DENALI_PHY_832__PHY_DDL_MASK_3
+
+#define LPDDR4__DENALI_PHY_833_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_833_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_833__PHY_DDL_TEST_OBS_3_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_833__PHY_DDL_TEST_OBS_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_833__PHY_DDL_TEST_OBS_3_WIDTH 32U
+#define LPDDR4__PHY_DDL_TEST_OBS_3__REG DENALI_PHY_833
+#define LPDDR4__PHY_DDL_TEST_OBS_3__FLD LPDDR4__DENALI_PHY_833__PHY_DDL_TEST_OBS_3
+
+#define LPDDR4__DENALI_PHY_834_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_834_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_834__PHY_DDL_TEST_MSTR_DLY_OBS_3_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_834__PHY_DDL_TEST_MSTR_DLY_OBS_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_834__PHY_DDL_TEST_MSTR_DLY_OBS_3_WIDTH 32U
+#define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_3__REG DENALI_PHY_834
+#define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_3__FLD LPDDR4__DENALI_PHY_834__PHY_DDL_TEST_MSTR_DLY_OBS_3
+
+#define LPDDR4__DENALI_PHY_835_READ_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_835_WRITE_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_835__PHY_DDL_TRACK_UPD_THRESHOLD_3_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_835__PHY_DDL_TRACK_UPD_THRESHOLD_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_835__PHY_DDL_TRACK_UPD_THRESHOLD_3_WIDTH 8U
+#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_3__REG DENALI_PHY_835
+#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_3__FLD LPDDR4__DENALI_PHY_835__PHY_DDL_TRACK_UPD_THRESHOLD_3
+
+#define LPDDR4__DENALI_PHY_835__PHY_LP4_WDQS_OE_EXTEND_3_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_835__PHY_LP4_WDQS_OE_EXTEND_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_835__PHY_LP4_WDQS_OE_EXTEND_3_WIDTH 1U
+#define LPDDR4__DENALI_PHY_835__PHY_LP4_WDQS_OE_EXTEND_3_WOCLR 0U
+#define LPDDR4__DENALI_PHY_835__PHY_LP4_WDQS_OE_EXTEND_3_WOSET 0U
+#define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_3__REG DENALI_PHY_835
+#define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_3__FLD LPDDR4__DENALI_PHY_835__PHY_LP4_WDQS_OE_EXTEND_3
+
+#define LPDDR4__DENALI_PHY_835__PHY_RX_CAL_DQ0_3_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_835__PHY_RX_CAL_DQ0_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_835__PHY_RX_CAL_DQ0_3_WIDTH 9U
+#define LPDDR4__PHY_RX_CAL_DQ0_3__REG DENALI_PHY_835
+#define LPDDR4__PHY_RX_CAL_DQ0_3__FLD LPDDR4__DENALI_PHY_835__PHY_RX_CAL_DQ0_3
+
+#define LPDDR4__DENALI_PHY_836_READ_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_836_WRITE_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ1_3_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ1_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ1_3_WIDTH 9U
+#define LPDDR4__PHY_RX_CAL_DQ1_3__REG DENALI_PHY_836
+#define LPDDR4__PHY_RX_CAL_DQ1_3__FLD LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ1_3
+
+#define LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ2_3_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ2_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ2_3_WIDTH 9U
+#define LPDDR4__PHY_RX_CAL_DQ2_3__REG DENALI_PHY_836
+#define LPDDR4__PHY_RX_CAL_DQ2_3__FLD LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ2_3
+
+#define LPDDR4__DENALI_PHY_837_READ_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_837_WRITE_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ3_3_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ3_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ3_3_WIDTH 9U
+#define LPDDR4__PHY_RX_CAL_DQ3_3__REG DENALI_PHY_837
+#define LPDDR4__PHY_RX_CAL_DQ3_3__FLD LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ3_3
+
+#define LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ4_3_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ4_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ4_3_WIDTH 9U
+#define LPDDR4__PHY_RX_CAL_DQ4_3__REG DENALI_PHY_837
+#define LPDDR4__PHY_RX_CAL_DQ4_3__FLD LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ4_3
+
+#define LPDDR4__DENALI_PHY_838_READ_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_838_WRITE_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ5_3_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ5_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ5_3_WIDTH 9U
+#define LPDDR4__PHY_RX_CAL_DQ5_3__REG DENALI_PHY_838
+#define LPDDR4__PHY_RX_CAL_DQ5_3__FLD LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ5_3
+
+#define LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ6_3_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ6_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ6_3_WIDTH 9U
+#define LPDDR4__PHY_RX_CAL_DQ6_3__REG DENALI_PHY_838
+#define LPDDR4__PHY_RX_CAL_DQ6_3__FLD LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ6_3
+
+#define LPDDR4__DENALI_PHY_839_READ_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_839_WRITE_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_839__PHY_RX_CAL_DQ7_3_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_839__PHY_RX_CAL_DQ7_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_839__PHY_RX_CAL_DQ7_3_WIDTH 9U
+#define LPDDR4__PHY_RX_CAL_DQ7_3__REG DENALI_PHY_839
+#define LPDDR4__PHY_RX_CAL_DQ7_3__FLD LPDDR4__DENALI_PHY_839__PHY_RX_CAL_DQ7_3
+
+#define LPDDR4__DENALI_PHY_840_READ_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_840_WRITE_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_840__PHY_RX_CAL_DM_3_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_840__PHY_RX_CAL_DM_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_840__PHY_RX_CAL_DM_3_WIDTH 18U
+#define LPDDR4__PHY_RX_CAL_DM_3__REG DENALI_PHY_840
+#define LPDDR4__PHY_RX_CAL_DM_3__FLD LPDDR4__DENALI_PHY_840__PHY_RX_CAL_DM_3
+
+#define LPDDR4__DENALI_PHY_841_READ_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_841_WRITE_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_841__PHY_RX_CAL_DQS_3_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_841__PHY_RX_CAL_DQS_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_841__PHY_RX_CAL_DQS_3_WIDTH 9U
+#define LPDDR4__PHY_RX_CAL_DQS_3__REG DENALI_PHY_841
+#define LPDDR4__PHY_RX_CAL_DQS_3__FLD LPDDR4__DENALI_PHY_841__PHY_RX_CAL_DQS_3
+
+#define LPDDR4__DENALI_PHY_841__PHY_RX_CAL_FDBK_3_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_841__PHY_RX_CAL_FDBK_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_841__PHY_RX_CAL_FDBK_3_WIDTH 9U
+#define LPDDR4__PHY_RX_CAL_FDBK_3__REG DENALI_PHY_841
+#define LPDDR4__PHY_RX_CAL_FDBK_3__FLD LPDDR4__DENALI_PHY_841__PHY_RX_CAL_FDBK_3
+
+#define LPDDR4__DENALI_PHY_842_READ_MASK 0xFF1F07FFU
+#define LPDDR4__DENALI_PHY_842_WRITE_MASK 0xFF1F07FFU
+#define LPDDR4__DENALI_PHY_842__PHY_PAD_RX_BIAS_EN_3_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_842__PHY_PAD_RX_BIAS_EN_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_842__PHY_PAD_RX_BIAS_EN_3_WIDTH 11U
+#define LPDDR4__PHY_PAD_RX_BIAS_EN_3__REG DENALI_PHY_842
+#define LPDDR4__PHY_PAD_RX_BIAS_EN_3__FLD LPDDR4__DENALI_PHY_842__PHY_PAD_RX_BIAS_EN_3
+
+#define LPDDR4__DENALI_PHY_842__PHY_STATIC_TOG_DISABLE_3_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_842__PHY_STATIC_TOG_DISABLE_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_842__PHY_STATIC_TOG_DISABLE_3_WIDTH 5U
+#define LPDDR4__PHY_STATIC_TOG_DISABLE_3__REG DENALI_PHY_842
+#define LPDDR4__PHY_STATIC_TOG_DISABLE_3__FLD LPDDR4__DENALI_PHY_842__PHY_STATIC_TOG_DISABLE_3
+
+#define LPDDR4__DENALI_PHY_842__PHY_DATA_DC_CAL_SAMPLE_WAIT_3_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_842__PHY_DATA_DC_CAL_SAMPLE_WAIT_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_842__PHY_DATA_DC_CAL_SAMPLE_WAIT_3_WIDTH 8U
+#define LPDDR4__PHY_DATA_DC_CAL_SAMPLE_WAIT_3__REG DENALI_PHY_842
+#define LPDDR4__PHY_DATA_DC_CAL_SAMPLE_WAIT_3__FLD LPDDR4__DENALI_PHY_842__PHY_DATA_DC_CAL_SAMPLE_WAIT_3
+
+#define LPDDR4__DENALI_PHY_843_READ_MASK 0xFF3F03FFU
+#define LPDDR4__DENALI_PHY_843_WRITE_MASK 0xFF3F03FFU
+#define LPDDR4__DENALI_PHY_843__PHY_DATA_DC_CAL_TIMEOUT_3_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_843__PHY_DATA_DC_CAL_TIMEOUT_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_843__PHY_DATA_DC_CAL_TIMEOUT_3_WIDTH 8U
+#define LPDDR4__PHY_DATA_DC_CAL_TIMEOUT_3__REG DENALI_PHY_843
+#define LPDDR4__PHY_DATA_DC_CAL_TIMEOUT_3__FLD LPDDR4__DENALI_PHY_843__PHY_DATA_DC_CAL_TIMEOUT_3
+
+#define LPDDR4__DENALI_PHY_843__PHY_DATA_DC_WEIGHT_3_MASK 0x00000300U
+#define LPDDR4__DENALI_PHY_843__PHY_DATA_DC_WEIGHT_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_843__PHY_DATA_DC_WEIGHT_3_WIDTH 2U
+#define LPDDR4__PHY_DATA_DC_WEIGHT_3__REG DENALI_PHY_843
+#define LPDDR4__PHY_DATA_DC_WEIGHT_3__FLD LPDDR4__DENALI_PHY_843__PHY_DATA_DC_WEIGHT_3
+
+#define LPDDR4__DENALI_PHY_843__PHY_DATA_DC_ADJUST_START_3_MASK 0x003F0000U
+#define LPDDR4__DENALI_PHY_843__PHY_DATA_DC_ADJUST_START_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_843__PHY_DATA_DC_ADJUST_START_3_WIDTH 6U
+#define LPDDR4__PHY_DATA_DC_ADJUST_START_3__REG DENALI_PHY_843
+#define LPDDR4__PHY_DATA_DC_ADJUST_START_3__FLD LPDDR4__DENALI_PHY_843__PHY_DATA_DC_ADJUST_START_3
+
+#define LPDDR4__DENALI_PHY_843__PHY_DATA_DC_ADJUST_SAMPLE_CNT_3_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_843__PHY_DATA_DC_ADJUST_SAMPLE_CNT_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_843__PHY_DATA_DC_ADJUST_SAMPLE_CNT_3_WIDTH 8U
+#define LPDDR4__PHY_DATA_DC_ADJUST_SAMPLE_CNT_3__REG DENALI_PHY_843
+#define LPDDR4__PHY_DATA_DC_ADJUST_SAMPLE_CNT_3__FLD LPDDR4__DENALI_PHY_843__PHY_DATA_DC_ADJUST_SAMPLE_CNT_3
+
+#define LPDDR4__DENALI_PHY_844_READ_MASK 0x010101FFU
+#define LPDDR4__DENALI_PHY_844_WRITE_MASK 0x010101FFU
+#define LPDDR4__DENALI_PHY_844__PHY_DATA_DC_ADJUST_THRSHLD_3_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_844__PHY_DATA_DC_ADJUST_THRSHLD_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_844__PHY_DATA_DC_ADJUST_THRSHLD_3_WIDTH 8U
+#define LPDDR4__PHY_DATA_DC_ADJUST_THRSHLD_3__REG DENALI_PHY_844
+#define LPDDR4__PHY_DATA_DC_ADJUST_THRSHLD_3__FLD LPDDR4__DENALI_PHY_844__PHY_DATA_DC_ADJUST_THRSHLD_3
+
+#define LPDDR4__DENALI_PHY_844__PHY_DATA_DC_ADJUST_DIRECT_3_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_844__PHY_DATA_DC_ADJUST_DIRECT_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_844__PHY_DATA_DC_ADJUST_DIRECT_3_WIDTH 1U
+#define LPDDR4__DENALI_PHY_844__PHY_DATA_DC_ADJUST_DIRECT_3_WOCLR 0U
+#define LPDDR4__DENALI_PHY_844__PHY_DATA_DC_ADJUST_DIRECT_3_WOSET 0U
+#define LPDDR4__PHY_DATA_DC_ADJUST_DIRECT_3__REG DENALI_PHY_844
+#define LPDDR4__PHY_DATA_DC_ADJUST_DIRECT_3__FLD LPDDR4__DENALI_PHY_844__PHY_DATA_DC_ADJUST_DIRECT_3
+
+#define LPDDR4__DENALI_PHY_844__PHY_DATA_DC_CAL_POLARITY_3_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_844__PHY_DATA_DC_CAL_POLARITY_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_844__PHY_DATA_DC_CAL_POLARITY_3_WIDTH 1U
+#define LPDDR4__DENALI_PHY_844__PHY_DATA_DC_CAL_POLARITY_3_WOCLR 0U
+#define LPDDR4__DENALI_PHY_844__PHY_DATA_DC_CAL_POLARITY_3_WOSET 0U
+#define LPDDR4__PHY_DATA_DC_CAL_POLARITY_3__REG DENALI_PHY_844
+#define LPDDR4__PHY_DATA_DC_CAL_POLARITY_3__FLD LPDDR4__DENALI_PHY_844__PHY_DATA_DC_CAL_POLARITY_3
+
+#define LPDDR4__DENALI_PHY_844__PHY_DATA_DC_CAL_START_3_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_844__PHY_DATA_DC_CAL_START_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_844__PHY_DATA_DC_CAL_START_3_WIDTH 1U
+#define LPDDR4__DENALI_PHY_844__PHY_DATA_DC_CAL_START_3_WOCLR 0U
+#define LPDDR4__DENALI_PHY_844__PHY_DATA_DC_CAL_START_3_WOSET 0U
+#define LPDDR4__PHY_DATA_DC_CAL_START_3__REG DENALI_PHY_844
+#define LPDDR4__PHY_DATA_DC_CAL_START_3__FLD LPDDR4__DENALI_PHY_844__PHY_DATA_DC_CAL_START_3
+
+#define LPDDR4__DENALI_PHY_845_READ_MASK 0x01010703U
+#define LPDDR4__DENALI_PHY_845_WRITE_MASK 0x01010703U
+#define LPDDR4__DENALI_PHY_845__PHY_DATA_DC_SW_RANK_3_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_845__PHY_DATA_DC_SW_RANK_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_845__PHY_DATA_DC_SW_RANK_3_WIDTH 2U
+#define LPDDR4__PHY_DATA_DC_SW_RANK_3__REG DENALI_PHY_845
+#define LPDDR4__PHY_DATA_DC_SW_RANK_3__FLD LPDDR4__DENALI_PHY_845__PHY_DATA_DC_SW_RANK_3
+
+#define LPDDR4__DENALI_PHY_845__PHY_FDBK_PWR_CTRL_3_MASK 0x00000700U
+#define LPDDR4__DENALI_PHY_845__PHY_FDBK_PWR_CTRL_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_845__PHY_FDBK_PWR_CTRL_3_WIDTH 3U
+#define LPDDR4__PHY_FDBK_PWR_CTRL_3__REG DENALI_PHY_845
+#define LPDDR4__PHY_FDBK_PWR_CTRL_3__FLD LPDDR4__DENALI_PHY_845__PHY_FDBK_PWR_CTRL_3
+
+#define LPDDR4__DENALI_PHY_845__PHY_SLV_DLY_CTRL_GATE_DISABLE_3_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_845__PHY_SLV_DLY_CTRL_GATE_DISABLE_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_845__PHY_SLV_DLY_CTRL_GATE_DISABLE_3_WIDTH 1U
+#define LPDDR4__DENALI_PHY_845__PHY_SLV_DLY_CTRL_GATE_DISABLE_3_WOCLR 0U
+#define LPDDR4__DENALI_PHY_845__PHY_SLV_DLY_CTRL_GATE_DISABLE_3_WOSET 0U
+#define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_3__REG DENALI_PHY_845
+#define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_3__FLD LPDDR4__DENALI_PHY_845__PHY_SLV_DLY_CTRL_GATE_DISABLE_3
+
+#define LPDDR4__DENALI_PHY_845__PHY_RDPATH_GATE_DISABLE_3_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_845__PHY_RDPATH_GATE_DISABLE_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_845__PHY_RDPATH_GATE_DISABLE_3_WIDTH 1U
+#define LPDDR4__DENALI_PHY_845__PHY_RDPATH_GATE_DISABLE_3_WOCLR 0U
+#define LPDDR4__DENALI_PHY_845__PHY_RDPATH_GATE_DISABLE_3_WOSET 0U
+#define LPDDR4__PHY_RDPATH_GATE_DISABLE_3__REG DENALI_PHY_845
+#define LPDDR4__PHY_RDPATH_GATE_DISABLE_3__FLD LPDDR4__DENALI_PHY_845__PHY_RDPATH_GATE_DISABLE_3
+
+#define LPDDR4__DENALI_PHY_846_READ_MASK 0x00000101U
+#define LPDDR4__DENALI_PHY_846_WRITE_MASK 0x00000101U
+#define LPDDR4__DENALI_PHY_846__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_3_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_846__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_846__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_3_WIDTH 1U
+#define LPDDR4__DENALI_PHY_846__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_3_WOCLR 0U
+#define LPDDR4__DENALI_PHY_846__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_3_WOSET 0U
+#define LPDDR4__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_3__REG DENALI_PHY_846
+#define LPDDR4__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_3__FLD LPDDR4__DENALI_PHY_846__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_3
+
+#define LPDDR4__DENALI_PHY_846__PHY_SLICE_PWR_RDC_DISABLE_3_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_846__PHY_SLICE_PWR_RDC_DISABLE_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_846__PHY_SLICE_PWR_RDC_DISABLE_3_WIDTH 1U
+#define LPDDR4__DENALI_PHY_846__PHY_SLICE_PWR_RDC_DISABLE_3_WOCLR 0U
+#define LPDDR4__DENALI_PHY_846__PHY_SLICE_PWR_RDC_DISABLE_3_WOSET 0U
+#define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_3__REG DENALI_PHY_846
+#define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_3__FLD LPDDR4__DENALI_PHY_846__PHY_SLICE_PWR_RDC_DISABLE_3
+
+#define LPDDR4__DENALI_PHY_847_READ_MASK 0x07FFFF07U
+#define LPDDR4__DENALI_PHY_847_WRITE_MASK 0x07FFFF07U
+#define LPDDR4__DENALI_PHY_847__PHY_DQ_TSEL_ENABLE_3_MASK 0x00000007U
+#define LPDDR4__DENALI_PHY_847__PHY_DQ_TSEL_ENABLE_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_847__PHY_DQ_TSEL_ENABLE_3_WIDTH 3U
+#define LPDDR4__PHY_DQ_TSEL_ENABLE_3__REG DENALI_PHY_847
+#define LPDDR4__PHY_DQ_TSEL_ENABLE_3__FLD LPDDR4__DENALI_PHY_847__PHY_DQ_TSEL_ENABLE_3
+
+#define LPDDR4__DENALI_PHY_847__PHY_DQ_TSEL_SELECT_3_MASK 0x00FFFF00U
+#define LPDDR4__DENALI_PHY_847__PHY_DQ_TSEL_SELECT_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_847__PHY_DQ_TSEL_SELECT_3_WIDTH 16U
+#define LPDDR4__PHY_DQ_TSEL_SELECT_3__REG DENALI_PHY_847
+#define LPDDR4__PHY_DQ_TSEL_SELECT_3__FLD LPDDR4__DENALI_PHY_847__PHY_DQ_TSEL_SELECT_3
+
+#define LPDDR4__DENALI_PHY_847__PHY_DQS_TSEL_ENABLE_3_MASK 0x07000000U
+#define LPDDR4__DENALI_PHY_847__PHY_DQS_TSEL_ENABLE_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_847__PHY_DQS_TSEL_ENABLE_3_WIDTH 3U
+#define LPDDR4__PHY_DQS_TSEL_ENABLE_3__REG DENALI_PHY_847
+#define LPDDR4__PHY_DQS_TSEL_ENABLE_3__FLD LPDDR4__DENALI_PHY_847__PHY_DQS_TSEL_ENABLE_3
+
+#define LPDDR4__DENALI_PHY_848_READ_MASK 0x7F03FFFFU
+#define LPDDR4__DENALI_PHY_848_WRITE_MASK 0x7F03FFFFU
+#define LPDDR4__DENALI_PHY_848__PHY_DQS_TSEL_SELECT_3_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_848__PHY_DQS_TSEL_SELECT_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_848__PHY_DQS_TSEL_SELECT_3_WIDTH 16U
+#define LPDDR4__PHY_DQS_TSEL_SELECT_3__REG DENALI_PHY_848
+#define LPDDR4__PHY_DQS_TSEL_SELECT_3__FLD LPDDR4__DENALI_PHY_848__PHY_DQS_TSEL_SELECT_3
+
+#define LPDDR4__DENALI_PHY_848__PHY_TWO_CYC_PREAMBLE_3_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_848__PHY_TWO_CYC_PREAMBLE_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_848__PHY_TWO_CYC_PREAMBLE_3_WIDTH 2U
+#define LPDDR4__PHY_TWO_CYC_PREAMBLE_3__REG DENALI_PHY_848
+#define LPDDR4__PHY_TWO_CYC_PREAMBLE_3__FLD LPDDR4__DENALI_PHY_848__PHY_TWO_CYC_PREAMBLE_3
+
+#define LPDDR4__DENALI_PHY_848__PHY_VREF_INITIAL_START_POINT_3_MASK 0x7F000000U
+#define LPDDR4__DENALI_PHY_848__PHY_VREF_INITIAL_START_POINT_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_848__PHY_VREF_INITIAL_START_POINT_3_WIDTH 7U
+#define LPDDR4__PHY_VREF_INITIAL_START_POINT_3__REG DENALI_PHY_848
+#define LPDDR4__PHY_VREF_INITIAL_START_POINT_3__FLD LPDDR4__DENALI_PHY_848__PHY_VREF_INITIAL_START_POINT_3
+
+#define LPDDR4__DENALI_PHY_849_READ_MASK 0xFF01037FU
+#define LPDDR4__DENALI_PHY_849_WRITE_MASK 0xFF01037FU
+#define LPDDR4__DENALI_PHY_849__PHY_VREF_INITIAL_STOP_POINT_3_MASK 0x0000007FU
+#define LPDDR4__DENALI_PHY_849__PHY_VREF_INITIAL_STOP_POINT_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_849__PHY_VREF_INITIAL_STOP_POINT_3_WIDTH 7U
+#define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_3__REG DENALI_PHY_849
+#define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_3__FLD LPDDR4__DENALI_PHY_849__PHY_VREF_INITIAL_STOP_POINT_3
+
+#define LPDDR4__DENALI_PHY_849__PHY_VREF_TRAINING_CTRL_3_MASK 0x00000300U
+#define LPDDR4__DENALI_PHY_849__PHY_VREF_TRAINING_CTRL_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_849__PHY_VREF_TRAINING_CTRL_3_WIDTH 2U
+#define LPDDR4__PHY_VREF_TRAINING_CTRL_3__REG DENALI_PHY_849
+#define LPDDR4__PHY_VREF_TRAINING_CTRL_3__FLD LPDDR4__DENALI_PHY_849__PHY_VREF_TRAINING_CTRL_3
+
+#define LPDDR4__DENALI_PHY_849__PHY_NTP_TRAIN_EN_3_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_849__PHY_NTP_TRAIN_EN_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_849__PHY_NTP_TRAIN_EN_3_WIDTH 1U
+#define LPDDR4__DENALI_PHY_849__PHY_NTP_TRAIN_EN_3_WOCLR 0U
+#define LPDDR4__DENALI_PHY_849__PHY_NTP_TRAIN_EN_3_WOSET 0U
+#define LPDDR4__PHY_NTP_TRAIN_EN_3__REG DENALI_PHY_849
+#define LPDDR4__PHY_NTP_TRAIN_EN_3__FLD LPDDR4__DENALI_PHY_849__PHY_NTP_TRAIN_EN_3
+
+#define LPDDR4__DENALI_PHY_849__PHY_NTP_WDQ_STEP_SIZE_3_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_849__PHY_NTP_WDQ_STEP_SIZE_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_849__PHY_NTP_WDQ_STEP_SIZE_3_WIDTH 8U
+#define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_3__REG DENALI_PHY_849
+#define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_3__FLD LPDDR4__DENALI_PHY_849__PHY_NTP_WDQ_STEP_SIZE_3
+
+#define LPDDR4__DENALI_PHY_850_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_850_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_850__PHY_NTP_WDQ_START_3_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_850__PHY_NTP_WDQ_START_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_850__PHY_NTP_WDQ_START_3_WIDTH 11U
+#define LPDDR4__PHY_NTP_WDQ_START_3__REG DENALI_PHY_850
+#define LPDDR4__PHY_NTP_WDQ_START_3__FLD LPDDR4__DENALI_PHY_850__PHY_NTP_WDQ_START_3
+
+#define LPDDR4__DENALI_PHY_850__PHY_NTP_WDQ_STOP_3_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_850__PHY_NTP_WDQ_STOP_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_850__PHY_NTP_WDQ_STOP_3_WIDTH 11U
+#define LPDDR4__PHY_NTP_WDQ_STOP_3__REG DENALI_PHY_850
+#define LPDDR4__PHY_NTP_WDQ_STOP_3__FLD LPDDR4__DENALI_PHY_850__PHY_NTP_WDQ_STOP_3
+
+#define LPDDR4__DENALI_PHY_851_READ_MASK 0x0103FFFFU
+#define LPDDR4__DENALI_PHY_851_WRITE_MASK 0x0103FFFFU
+#define LPDDR4__DENALI_PHY_851__PHY_NTP_WDQ_BIT_EN_3_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_851__PHY_NTP_WDQ_BIT_EN_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_851__PHY_NTP_WDQ_BIT_EN_3_WIDTH 8U
+#define LPDDR4__PHY_NTP_WDQ_BIT_EN_3__REG DENALI_PHY_851
+#define LPDDR4__PHY_NTP_WDQ_BIT_EN_3__FLD LPDDR4__DENALI_PHY_851__PHY_NTP_WDQ_BIT_EN_3
+
+#define LPDDR4__DENALI_PHY_851__PHY_WDQLVL_DVW_MIN_3_MASK 0x0003FF00U
+#define LPDDR4__DENALI_PHY_851__PHY_WDQLVL_DVW_MIN_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_851__PHY_WDQLVL_DVW_MIN_3_WIDTH 10U
+#define LPDDR4__PHY_WDQLVL_DVW_MIN_3__REG DENALI_PHY_851
+#define LPDDR4__PHY_WDQLVL_DVW_MIN_3__FLD LPDDR4__DENALI_PHY_851__PHY_WDQLVL_DVW_MIN_3
+
+#define LPDDR4__DENALI_PHY_851__PHY_SW_WDQLVL_DVW_MIN_EN_3_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_851__PHY_SW_WDQLVL_DVW_MIN_EN_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_851__PHY_SW_WDQLVL_DVW_MIN_EN_3_WIDTH 1U
+#define LPDDR4__DENALI_PHY_851__PHY_SW_WDQLVL_DVW_MIN_EN_3_WOCLR 0U
+#define LPDDR4__DENALI_PHY_851__PHY_SW_WDQLVL_DVW_MIN_EN_3_WOSET 0U
+#define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_3__REG DENALI_PHY_851
+#define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_3__FLD LPDDR4__DENALI_PHY_851__PHY_SW_WDQLVL_DVW_MIN_EN_3
+
+#define LPDDR4__DENALI_PHY_852_READ_MASK 0x1F1F0F3FU
+#define LPDDR4__DENALI_PHY_852_WRITE_MASK 0x1F1F0F3FU
+#define LPDDR4__DENALI_PHY_852__PHY_WDQLVL_PER_START_OFFSET_3_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_852__PHY_WDQLVL_PER_START_OFFSET_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_852__PHY_WDQLVL_PER_START_OFFSET_3_WIDTH 6U
+#define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_3__REG DENALI_PHY_852
+#define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_3__FLD LPDDR4__DENALI_PHY_852__PHY_WDQLVL_PER_START_OFFSET_3
+
+#define LPDDR4__DENALI_PHY_852__PHY_FAST_LVL_EN_3_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_852__PHY_FAST_LVL_EN_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_852__PHY_FAST_LVL_EN_3_WIDTH 4U
+#define LPDDR4__PHY_FAST_LVL_EN_3__REG DENALI_PHY_852
+#define LPDDR4__PHY_FAST_LVL_EN_3__FLD LPDDR4__DENALI_PHY_852__PHY_FAST_LVL_EN_3
+
+#define LPDDR4__DENALI_PHY_852__PHY_PAD_TX_DCD_3_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_852__PHY_PAD_TX_DCD_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_852__PHY_PAD_TX_DCD_3_WIDTH 5U
+#define LPDDR4__PHY_PAD_TX_DCD_3__REG DENALI_PHY_852
+#define LPDDR4__PHY_PAD_TX_DCD_3__FLD LPDDR4__DENALI_PHY_852__PHY_PAD_TX_DCD_3
+
+#define LPDDR4__DENALI_PHY_852__PHY_PAD_RX_DCD_0_3_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_852__PHY_PAD_RX_DCD_0_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_852__PHY_PAD_RX_DCD_0_3_WIDTH 5U
+#define LPDDR4__PHY_PAD_RX_DCD_0_3__REG DENALI_PHY_852
+#define LPDDR4__PHY_PAD_RX_DCD_0_3__FLD LPDDR4__DENALI_PHY_852__PHY_PAD_RX_DCD_0_3
+
+#define LPDDR4__DENALI_PHY_853_READ_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_853_WRITE_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_853__PHY_PAD_RX_DCD_1_3_MASK 0x0000001FU
+#define LPDDR4__DENALI_PHY_853__PHY_PAD_RX_DCD_1_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_853__PHY_PAD_RX_DCD_1_3_WIDTH 5U
+#define LPDDR4__PHY_PAD_RX_DCD_1_3__REG DENALI_PHY_853
+#define LPDDR4__PHY_PAD_RX_DCD_1_3__FLD LPDDR4__DENALI_PHY_853__PHY_PAD_RX_DCD_1_3
+
+#define LPDDR4__DENALI_PHY_853__PHY_PAD_RX_DCD_2_3_MASK 0x00001F00U
+#define LPDDR4__DENALI_PHY_853__PHY_PAD_RX_DCD_2_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_853__PHY_PAD_RX_DCD_2_3_WIDTH 5U
+#define LPDDR4__PHY_PAD_RX_DCD_2_3__REG DENALI_PHY_853
+#define LPDDR4__PHY_PAD_RX_DCD_2_3__FLD LPDDR4__DENALI_PHY_853__PHY_PAD_RX_DCD_2_3
+
+#define LPDDR4__DENALI_PHY_853__PHY_PAD_RX_DCD_3_3_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_853__PHY_PAD_RX_DCD_3_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_853__PHY_PAD_RX_DCD_3_3_WIDTH 5U
+#define LPDDR4__PHY_PAD_RX_DCD_3_3__REG DENALI_PHY_853
+#define LPDDR4__PHY_PAD_RX_DCD_3_3__FLD LPDDR4__DENALI_PHY_853__PHY_PAD_RX_DCD_3_3
+
+#define LPDDR4__DENALI_PHY_853__PHY_PAD_RX_DCD_4_3_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_853__PHY_PAD_RX_DCD_4_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_853__PHY_PAD_RX_DCD_4_3_WIDTH 5U
+#define LPDDR4__PHY_PAD_RX_DCD_4_3__REG DENALI_PHY_853
+#define LPDDR4__PHY_PAD_RX_DCD_4_3__FLD LPDDR4__DENALI_PHY_853__PHY_PAD_RX_DCD_4_3
+
+#define LPDDR4__DENALI_PHY_854_READ_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_854_WRITE_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_854__PHY_PAD_RX_DCD_5_3_MASK 0x0000001FU
+#define LPDDR4__DENALI_PHY_854__PHY_PAD_RX_DCD_5_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_854__PHY_PAD_RX_DCD_5_3_WIDTH 5U
+#define LPDDR4__PHY_PAD_RX_DCD_5_3__REG DENALI_PHY_854
+#define LPDDR4__PHY_PAD_RX_DCD_5_3__FLD LPDDR4__DENALI_PHY_854__PHY_PAD_RX_DCD_5_3
+
+#define LPDDR4__DENALI_PHY_854__PHY_PAD_RX_DCD_6_3_MASK 0x00001F00U
+#define LPDDR4__DENALI_PHY_854__PHY_PAD_RX_DCD_6_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_854__PHY_PAD_RX_DCD_6_3_WIDTH 5U
+#define LPDDR4__PHY_PAD_RX_DCD_6_3__REG DENALI_PHY_854
+#define LPDDR4__PHY_PAD_RX_DCD_6_3__FLD LPDDR4__DENALI_PHY_854__PHY_PAD_RX_DCD_6_3
+
+#define LPDDR4__DENALI_PHY_854__PHY_PAD_RX_DCD_7_3_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_854__PHY_PAD_RX_DCD_7_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_854__PHY_PAD_RX_DCD_7_3_WIDTH 5U
+#define LPDDR4__PHY_PAD_RX_DCD_7_3__REG DENALI_PHY_854
+#define LPDDR4__PHY_PAD_RX_DCD_7_3__FLD LPDDR4__DENALI_PHY_854__PHY_PAD_RX_DCD_7_3
+
+#define LPDDR4__DENALI_PHY_854__PHY_PAD_DM_RX_DCD_3_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_854__PHY_PAD_DM_RX_DCD_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_854__PHY_PAD_DM_RX_DCD_3_WIDTH 5U
+#define LPDDR4__PHY_PAD_DM_RX_DCD_3__REG DENALI_PHY_854
+#define LPDDR4__PHY_PAD_DM_RX_DCD_3__FLD LPDDR4__DENALI_PHY_854__PHY_PAD_DM_RX_DCD_3
+
+#define LPDDR4__DENALI_PHY_855_READ_MASK 0x007F1F1FU
+#define LPDDR4__DENALI_PHY_855_WRITE_MASK 0x007F1F1FU
+#define LPDDR4__DENALI_PHY_855__PHY_PAD_DQS_RX_DCD_3_MASK 0x0000001FU
+#define LPDDR4__DENALI_PHY_855__PHY_PAD_DQS_RX_DCD_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_855__PHY_PAD_DQS_RX_DCD_3_WIDTH 5U
+#define LPDDR4__PHY_PAD_DQS_RX_DCD_3__REG DENALI_PHY_855
+#define LPDDR4__PHY_PAD_DQS_RX_DCD_3__FLD LPDDR4__DENALI_PHY_855__PHY_PAD_DQS_RX_DCD_3
+
+#define LPDDR4__DENALI_PHY_855__PHY_PAD_FDBK_RX_DCD_3_MASK 0x00001F00U
+#define LPDDR4__DENALI_PHY_855__PHY_PAD_FDBK_RX_DCD_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_855__PHY_PAD_FDBK_RX_DCD_3_WIDTH 5U
+#define LPDDR4__PHY_PAD_FDBK_RX_DCD_3__REG DENALI_PHY_855
+#define LPDDR4__PHY_PAD_FDBK_RX_DCD_3__FLD LPDDR4__DENALI_PHY_855__PHY_PAD_FDBK_RX_DCD_3
+
+#define LPDDR4__DENALI_PHY_855__PHY_PAD_DSLICE_IO_CFG_3_MASK 0x007F0000U
+#define LPDDR4__DENALI_PHY_855__PHY_PAD_DSLICE_IO_CFG_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_855__PHY_PAD_DSLICE_IO_CFG_3_WIDTH 7U
+#define LPDDR4__PHY_PAD_DSLICE_IO_CFG_3__REG DENALI_PHY_855
+#define LPDDR4__PHY_PAD_DSLICE_IO_CFG_3__FLD LPDDR4__DENALI_PHY_855__PHY_PAD_DSLICE_IO_CFG_3
+
+#define LPDDR4__DENALI_PHY_856_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_856_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_856__PHY_RDDQ0_SLAVE_DELAY_3_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_856__PHY_RDDQ0_SLAVE_DELAY_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_856__PHY_RDDQ0_SLAVE_DELAY_3_WIDTH 10U
+#define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_3__REG DENALI_PHY_856
+#define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_856__PHY_RDDQ0_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_856__PHY_RDDQ1_SLAVE_DELAY_3_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_856__PHY_RDDQ1_SLAVE_DELAY_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_856__PHY_RDDQ1_SLAVE_DELAY_3_WIDTH 10U
+#define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_3__REG DENALI_PHY_856
+#define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_856__PHY_RDDQ1_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_857_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_857_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_857__PHY_RDDQ2_SLAVE_DELAY_3_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_857__PHY_RDDQ2_SLAVE_DELAY_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_857__PHY_RDDQ2_SLAVE_DELAY_3_WIDTH 10U
+#define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_3__REG DENALI_PHY_857
+#define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_857__PHY_RDDQ2_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_857__PHY_RDDQ3_SLAVE_DELAY_3_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_857__PHY_RDDQ3_SLAVE_DELAY_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_857__PHY_RDDQ3_SLAVE_DELAY_3_WIDTH 10U
+#define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_3__REG DENALI_PHY_857
+#define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_857__PHY_RDDQ3_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_858_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_858_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_858__PHY_RDDQ4_SLAVE_DELAY_3_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_858__PHY_RDDQ4_SLAVE_DELAY_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_858__PHY_RDDQ4_SLAVE_DELAY_3_WIDTH 10U
+#define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_3__REG DENALI_PHY_858
+#define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_858__PHY_RDDQ4_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_858__PHY_RDDQ5_SLAVE_DELAY_3_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_858__PHY_RDDQ5_SLAVE_DELAY_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_858__PHY_RDDQ5_SLAVE_DELAY_3_WIDTH 10U
+#define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_3__REG DENALI_PHY_858
+#define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_858__PHY_RDDQ5_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_859_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_859_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_859__PHY_RDDQ6_SLAVE_DELAY_3_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_859__PHY_RDDQ6_SLAVE_DELAY_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_859__PHY_RDDQ6_SLAVE_DELAY_3_WIDTH 10U
+#define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_3__REG DENALI_PHY_859
+#define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_859__PHY_RDDQ6_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_859__PHY_RDDQ7_SLAVE_DELAY_3_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_859__PHY_RDDQ7_SLAVE_DELAY_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_859__PHY_RDDQ7_SLAVE_DELAY_3_WIDTH 10U
+#define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_3__REG DENALI_PHY_859
+#define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_859__PHY_RDDQ7_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_860_READ_MASK 0x1F0703FFU
+#define LPDDR4__DENALI_PHY_860_WRITE_MASK 0x1F0703FFU
+#define LPDDR4__DENALI_PHY_860__PHY_RDDM_SLAVE_DELAY_3_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_860__PHY_RDDM_SLAVE_DELAY_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_860__PHY_RDDM_SLAVE_DELAY_3_WIDTH 10U
+#define LPDDR4__PHY_RDDM_SLAVE_DELAY_3__REG DENALI_PHY_860
+#define LPDDR4__PHY_RDDM_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_860__PHY_RDDM_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_860__PHY_RX_PCLK_CLK_SEL_3_MASK 0x00070000U
+#define LPDDR4__DENALI_PHY_860__PHY_RX_PCLK_CLK_SEL_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_860__PHY_RX_PCLK_CLK_SEL_3_WIDTH 3U
+#define LPDDR4__PHY_RX_PCLK_CLK_SEL_3__REG DENALI_PHY_860
+#define LPDDR4__PHY_RX_PCLK_CLK_SEL_3__FLD LPDDR4__DENALI_PHY_860__PHY_RX_PCLK_CLK_SEL_3
+
+#define LPDDR4__DENALI_PHY_860__PHY_RX_CAL_ALL_DLY_3_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_860__PHY_RX_CAL_ALL_DLY_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_860__PHY_RX_CAL_ALL_DLY_3_WIDTH 5U
+#define LPDDR4__PHY_RX_CAL_ALL_DLY_3__REG DENALI_PHY_860
+#define LPDDR4__PHY_RX_CAL_ALL_DLY_3__FLD LPDDR4__DENALI_PHY_860__PHY_RX_CAL_ALL_DLY_3
+
+#define LPDDR4__DENALI_PHY_861_READ_MASK 0x00000007U
+#define LPDDR4__DENALI_PHY_861_WRITE_MASK 0x00000007U
+#define LPDDR4__DENALI_PHY_861__PHY_DATA_DC_CAL_CLK_SEL_3_MASK 0x00000007U
+#define LPDDR4__DENALI_PHY_861__PHY_DATA_DC_CAL_CLK_SEL_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_861__PHY_DATA_DC_CAL_CLK_SEL_3_WIDTH 3U
+#define LPDDR4__PHY_DATA_DC_CAL_CLK_SEL_3__REG DENALI_PHY_861
+#define LPDDR4__PHY_DATA_DC_CAL_CLK_SEL_3__FLD LPDDR4__DENALI_PHY_861__PHY_DATA_DC_CAL_CLK_SEL_3
+
+#define LPDDR4__DENALI_PHY_862_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_862_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_862__PHY_DQ_OE_TIMING_3_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_862__PHY_DQ_OE_TIMING_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_862__PHY_DQ_OE_TIMING_3_WIDTH 8U
+#define LPDDR4__PHY_DQ_OE_TIMING_3__REG DENALI_PHY_862
+#define LPDDR4__PHY_DQ_OE_TIMING_3__FLD LPDDR4__DENALI_PHY_862__PHY_DQ_OE_TIMING_3
+
+#define LPDDR4__DENALI_PHY_862__PHY_DQ_TSEL_RD_TIMING_3_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_862__PHY_DQ_TSEL_RD_TIMING_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_862__PHY_DQ_TSEL_RD_TIMING_3_WIDTH 8U
+#define LPDDR4__PHY_DQ_TSEL_RD_TIMING_3__REG DENALI_PHY_862
+#define LPDDR4__PHY_DQ_TSEL_RD_TIMING_3__FLD LPDDR4__DENALI_PHY_862__PHY_DQ_TSEL_RD_TIMING_3
+
+#define LPDDR4__DENALI_PHY_862__PHY_DQ_TSEL_WR_TIMING_3_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_862__PHY_DQ_TSEL_WR_TIMING_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_862__PHY_DQ_TSEL_WR_TIMING_3_WIDTH 8U
+#define LPDDR4__PHY_DQ_TSEL_WR_TIMING_3__REG DENALI_PHY_862
+#define LPDDR4__PHY_DQ_TSEL_WR_TIMING_3__FLD LPDDR4__DENALI_PHY_862__PHY_DQ_TSEL_WR_TIMING_3
+
+#define LPDDR4__DENALI_PHY_862__PHY_DQS_OE_TIMING_3_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_862__PHY_DQS_OE_TIMING_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_862__PHY_DQS_OE_TIMING_3_WIDTH 8U
+#define LPDDR4__PHY_DQS_OE_TIMING_3__REG DENALI_PHY_862
+#define LPDDR4__PHY_DQS_OE_TIMING_3__FLD LPDDR4__DENALI_PHY_862__PHY_DQS_OE_TIMING_3
+
+#define LPDDR4__DENALI_PHY_863_READ_MASK 0xFFFFFF0FU
+#define LPDDR4__DENALI_PHY_863_WRITE_MASK 0xFFFFFF0FU
+#define LPDDR4__DENALI_PHY_863__PHY_IO_PAD_DELAY_TIMING_3_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_863__PHY_IO_PAD_DELAY_TIMING_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_863__PHY_IO_PAD_DELAY_TIMING_3_WIDTH 4U
+#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_3__REG DENALI_PHY_863
+#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_3__FLD LPDDR4__DENALI_PHY_863__PHY_IO_PAD_DELAY_TIMING_3
+
+#define LPDDR4__DENALI_PHY_863__PHY_DQS_TSEL_RD_TIMING_3_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_863__PHY_DQS_TSEL_RD_TIMING_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_863__PHY_DQS_TSEL_RD_TIMING_3_WIDTH 8U
+#define LPDDR4__PHY_DQS_TSEL_RD_TIMING_3__REG DENALI_PHY_863
+#define LPDDR4__PHY_DQS_TSEL_RD_TIMING_3__FLD LPDDR4__DENALI_PHY_863__PHY_DQS_TSEL_RD_TIMING_3
+
+#define LPDDR4__DENALI_PHY_863__PHY_DQS_OE_RD_TIMING_3_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_863__PHY_DQS_OE_RD_TIMING_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_863__PHY_DQS_OE_RD_TIMING_3_WIDTH 8U
+#define LPDDR4__PHY_DQS_OE_RD_TIMING_3__REG DENALI_PHY_863
+#define LPDDR4__PHY_DQS_OE_RD_TIMING_3__FLD LPDDR4__DENALI_PHY_863__PHY_DQS_OE_RD_TIMING_3
+
+#define LPDDR4__DENALI_PHY_863__PHY_DQS_TSEL_WR_TIMING_3_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_863__PHY_DQS_TSEL_WR_TIMING_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_863__PHY_DQS_TSEL_WR_TIMING_3_WIDTH 8U
+#define LPDDR4__PHY_DQS_TSEL_WR_TIMING_3__REG DENALI_PHY_863
+#define LPDDR4__PHY_DQS_TSEL_WR_TIMING_3__FLD LPDDR4__DENALI_PHY_863__PHY_DQS_TSEL_WR_TIMING_3
+
+#define LPDDR4__DENALI_PHY_864_READ_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_864_WRITE_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_864__PHY_VREF_SETTING_TIME_3_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_864__PHY_VREF_SETTING_TIME_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_864__PHY_VREF_SETTING_TIME_3_WIDTH 16U
+#define LPDDR4__PHY_VREF_SETTING_TIME_3__REG DENALI_PHY_864
+#define LPDDR4__PHY_VREF_SETTING_TIME_3__FLD LPDDR4__DENALI_PHY_864__PHY_VREF_SETTING_TIME_3
+
+#define LPDDR4__DENALI_PHY_864__PHY_PAD_VREF_CTRL_DQ_3_MASK 0x0FFF0000U
+#define LPDDR4__DENALI_PHY_864__PHY_PAD_VREF_CTRL_DQ_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_864__PHY_PAD_VREF_CTRL_DQ_3_WIDTH 12U
+#define LPDDR4__PHY_PAD_VREF_CTRL_DQ_3__REG DENALI_PHY_864
+#define LPDDR4__PHY_PAD_VREF_CTRL_DQ_3__FLD LPDDR4__DENALI_PHY_864__PHY_PAD_VREF_CTRL_DQ_3
+
+#define LPDDR4__DENALI_PHY_865_READ_MASK 0x03FFFF01U
+#define LPDDR4__DENALI_PHY_865_WRITE_MASK 0x03FFFF01U
+#define LPDDR4__DENALI_PHY_865__PHY_PER_CS_TRAINING_EN_3_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_865__PHY_PER_CS_TRAINING_EN_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_865__PHY_PER_CS_TRAINING_EN_3_WIDTH 1U
+#define LPDDR4__DENALI_PHY_865__PHY_PER_CS_TRAINING_EN_3_WOCLR 0U
+#define LPDDR4__DENALI_PHY_865__PHY_PER_CS_TRAINING_EN_3_WOSET 0U
+#define LPDDR4__PHY_PER_CS_TRAINING_EN_3__REG DENALI_PHY_865
+#define LPDDR4__PHY_PER_CS_TRAINING_EN_3__FLD LPDDR4__DENALI_PHY_865__PHY_PER_CS_TRAINING_EN_3
+
+#define LPDDR4__DENALI_PHY_865__PHY_DQ_IE_TIMING_3_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_865__PHY_DQ_IE_TIMING_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_865__PHY_DQ_IE_TIMING_3_WIDTH 8U
+#define LPDDR4__PHY_DQ_IE_TIMING_3__REG DENALI_PHY_865
+#define LPDDR4__PHY_DQ_IE_TIMING_3__FLD LPDDR4__DENALI_PHY_865__PHY_DQ_IE_TIMING_3
+
+#define LPDDR4__DENALI_PHY_865__PHY_DQS_IE_TIMING_3_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_865__PHY_DQS_IE_TIMING_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_865__PHY_DQS_IE_TIMING_3_WIDTH 8U
+#define LPDDR4__PHY_DQS_IE_TIMING_3__REG DENALI_PHY_865
+#define LPDDR4__PHY_DQS_IE_TIMING_3__FLD LPDDR4__DENALI_PHY_865__PHY_DQS_IE_TIMING_3
+
+#define LPDDR4__DENALI_PHY_865__PHY_RDDATA_EN_IE_DLY_3_MASK 0x03000000U
+#define LPDDR4__DENALI_PHY_865__PHY_RDDATA_EN_IE_DLY_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_865__PHY_RDDATA_EN_IE_DLY_3_WIDTH 2U
+#define LPDDR4__PHY_RDDATA_EN_IE_DLY_3__REG DENALI_PHY_865
+#define LPDDR4__PHY_RDDATA_EN_IE_DLY_3__FLD LPDDR4__DENALI_PHY_865__PHY_RDDATA_EN_IE_DLY_3
+
+#define LPDDR4__DENALI_PHY_866_READ_MASK 0x1F010303U
+#define LPDDR4__DENALI_PHY_866_WRITE_MASK 0x1F010303U
+#define LPDDR4__DENALI_PHY_866__PHY_IE_MODE_3_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_866__PHY_IE_MODE_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_866__PHY_IE_MODE_3_WIDTH 2U
+#define LPDDR4__PHY_IE_MODE_3__REG DENALI_PHY_866
+#define LPDDR4__PHY_IE_MODE_3__FLD LPDDR4__DENALI_PHY_866__PHY_IE_MODE_3
+
+#define LPDDR4__DENALI_PHY_866__PHY_DBI_MODE_3_MASK 0x00000300U
+#define LPDDR4__DENALI_PHY_866__PHY_DBI_MODE_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_866__PHY_DBI_MODE_3_WIDTH 2U
+#define LPDDR4__PHY_DBI_MODE_3__REG DENALI_PHY_866
+#define LPDDR4__PHY_DBI_MODE_3__FLD LPDDR4__DENALI_PHY_866__PHY_DBI_MODE_3
+
+#define LPDDR4__DENALI_PHY_866__PHY_WDQLVL_IE_ON_3_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_866__PHY_WDQLVL_IE_ON_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_866__PHY_WDQLVL_IE_ON_3_WIDTH 1U
+#define LPDDR4__DENALI_PHY_866__PHY_WDQLVL_IE_ON_3_WOCLR 0U
+#define LPDDR4__DENALI_PHY_866__PHY_WDQLVL_IE_ON_3_WOSET 0U
+#define LPDDR4__PHY_WDQLVL_IE_ON_3__REG DENALI_PHY_866
+#define LPDDR4__PHY_WDQLVL_IE_ON_3__FLD LPDDR4__DENALI_PHY_866__PHY_WDQLVL_IE_ON_3
+
+#define LPDDR4__DENALI_PHY_866__PHY_WDQLVL_RDDATA_EN_DLY_3_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_866__PHY_WDQLVL_RDDATA_EN_DLY_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_866__PHY_WDQLVL_RDDATA_EN_DLY_3_WIDTH 5U
+#define LPDDR4__PHY_WDQLVL_RDDATA_EN_DLY_3__REG DENALI_PHY_866
+#define LPDDR4__PHY_WDQLVL_RDDATA_EN_DLY_3__FLD LPDDR4__DENALI_PHY_866__PHY_WDQLVL_RDDATA_EN_DLY_3
+
+#define LPDDR4__DENALI_PHY_867_READ_MASK 0x0F1F1F1FU
+#define LPDDR4__DENALI_PHY_867_WRITE_MASK 0x0F1F1F1FU
+#define LPDDR4__DENALI_PHY_867__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_3_MASK 0x0000001FU
+#define LPDDR4__DENALI_PHY_867__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_867__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_3_WIDTH 5U
+#define LPDDR4__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_3__REG DENALI_PHY_867
+#define LPDDR4__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_3__FLD LPDDR4__DENALI_PHY_867__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_3
+
+#define LPDDR4__DENALI_PHY_867__PHY_RDDATA_EN_TSEL_DLY_3_MASK 0x00001F00U
+#define LPDDR4__DENALI_PHY_867__PHY_RDDATA_EN_TSEL_DLY_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_867__PHY_RDDATA_EN_TSEL_DLY_3_WIDTH 5U
+#define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_3__REG DENALI_PHY_867
+#define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_3__FLD LPDDR4__DENALI_PHY_867__PHY_RDDATA_EN_TSEL_DLY_3
+
+#define LPDDR4__DENALI_PHY_867__PHY_RDDATA_EN_OE_DLY_3_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_867__PHY_RDDATA_EN_OE_DLY_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_867__PHY_RDDATA_EN_OE_DLY_3_WIDTH 5U
+#define LPDDR4__PHY_RDDATA_EN_OE_DLY_3__REG DENALI_PHY_867
+#define LPDDR4__PHY_RDDATA_EN_OE_DLY_3__FLD LPDDR4__DENALI_PHY_867__PHY_RDDATA_EN_OE_DLY_3
+
+#define LPDDR4__DENALI_PHY_867__PHY_SW_MASTER_MODE_3_MASK 0x0F000000U
+#define LPDDR4__DENALI_PHY_867__PHY_SW_MASTER_MODE_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_867__PHY_SW_MASTER_MODE_3_WIDTH 4U
+#define LPDDR4__PHY_SW_MASTER_MODE_3__REG DENALI_PHY_867
+#define LPDDR4__PHY_SW_MASTER_MODE_3__FLD LPDDR4__DENALI_PHY_867__PHY_SW_MASTER_MODE_3
+
+#define LPDDR4__DENALI_PHY_868_READ_MASK 0xFF3F07FFU
+#define LPDDR4__DENALI_PHY_868_WRITE_MASK 0xFF3F07FFU
+#define LPDDR4__DENALI_PHY_868__PHY_MASTER_DELAY_START_3_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_868__PHY_MASTER_DELAY_START_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_868__PHY_MASTER_DELAY_START_3_WIDTH 11U
+#define LPDDR4__PHY_MASTER_DELAY_START_3__REG DENALI_PHY_868
+#define LPDDR4__PHY_MASTER_DELAY_START_3__FLD LPDDR4__DENALI_PHY_868__PHY_MASTER_DELAY_START_3
+
+#define LPDDR4__DENALI_PHY_868__PHY_MASTER_DELAY_STEP_3_MASK 0x003F0000U
+#define LPDDR4__DENALI_PHY_868__PHY_MASTER_DELAY_STEP_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_868__PHY_MASTER_DELAY_STEP_3_WIDTH 6U
+#define LPDDR4__PHY_MASTER_DELAY_STEP_3__REG DENALI_PHY_868
+#define LPDDR4__PHY_MASTER_DELAY_STEP_3__FLD LPDDR4__DENALI_PHY_868__PHY_MASTER_DELAY_STEP_3
+
+#define LPDDR4__DENALI_PHY_868__PHY_MASTER_DELAY_WAIT_3_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_868__PHY_MASTER_DELAY_WAIT_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_868__PHY_MASTER_DELAY_WAIT_3_WIDTH 8U
+#define LPDDR4__PHY_MASTER_DELAY_WAIT_3__REG DENALI_PHY_868
+#define LPDDR4__PHY_MASTER_DELAY_WAIT_3__FLD LPDDR4__DENALI_PHY_868__PHY_MASTER_DELAY_WAIT_3
+
+#define LPDDR4__DENALI_PHY_869_READ_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_PHY_869_WRITE_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_PHY_869__PHY_MASTER_DELAY_HALF_MEASURE_3_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_869__PHY_MASTER_DELAY_HALF_MEASURE_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_869__PHY_MASTER_DELAY_HALF_MEASURE_3_WIDTH 8U
+#define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_3__REG DENALI_PHY_869
+#define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_3__FLD LPDDR4__DENALI_PHY_869__PHY_MASTER_DELAY_HALF_MEASURE_3
+
+#define LPDDR4__DENALI_PHY_869__PHY_RPTR_UPDATE_3_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_869__PHY_RPTR_UPDATE_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_869__PHY_RPTR_UPDATE_3_WIDTH 4U
+#define LPDDR4__PHY_RPTR_UPDATE_3__REG DENALI_PHY_869
+#define LPDDR4__PHY_RPTR_UPDATE_3__FLD LPDDR4__DENALI_PHY_869__PHY_RPTR_UPDATE_3
+
+#define LPDDR4__DENALI_PHY_869__PHY_WRLVL_DLY_STEP_3_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_869__PHY_WRLVL_DLY_STEP_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_869__PHY_WRLVL_DLY_STEP_3_WIDTH 8U
+#define LPDDR4__PHY_WRLVL_DLY_STEP_3__REG DENALI_PHY_869
+#define LPDDR4__PHY_WRLVL_DLY_STEP_3__FLD LPDDR4__DENALI_PHY_869__PHY_WRLVL_DLY_STEP_3
+
+#define LPDDR4__DENALI_PHY_869__PHY_WRLVL_DLY_FINE_STEP_3_MASK 0x0F000000U
+#define LPDDR4__DENALI_PHY_869__PHY_WRLVL_DLY_FINE_STEP_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_869__PHY_WRLVL_DLY_FINE_STEP_3_WIDTH 4U
+#define LPDDR4__PHY_WRLVL_DLY_FINE_STEP_3__REG DENALI_PHY_869
+#define LPDDR4__PHY_WRLVL_DLY_FINE_STEP_3__FLD LPDDR4__DENALI_PHY_869__PHY_WRLVL_DLY_FINE_STEP_3
+
+#define LPDDR4__DENALI_PHY_870_READ_MASK 0x001F0F3FU
+#define LPDDR4__DENALI_PHY_870_WRITE_MASK 0x001F0F3FU
+#define LPDDR4__DENALI_PHY_870__PHY_WRLVL_RESP_WAIT_CNT_3_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_870__PHY_WRLVL_RESP_WAIT_CNT_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_870__PHY_WRLVL_RESP_WAIT_CNT_3_WIDTH 6U
+#define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_3__REG DENALI_PHY_870
+#define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_3__FLD LPDDR4__DENALI_PHY_870__PHY_WRLVL_RESP_WAIT_CNT_3
+
+#define LPDDR4__DENALI_PHY_870__PHY_GTLVL_DLY_STEP_3_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_870__PHY_GTLVL_DLY_STEP_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_870__PHY_GTLVL_DLY_STEP_3_WIDTH 4U
+#define LPDDR4__PHY_GTLVL_DLY_STEP_3__REG DENALI_PHY_870
+#define LPDDR4__PHY_GTLVL_DLY_STEP_3__FLD LPDDR4__DENALI_PHY_870__PHY_GTLVL_DLY_STEP_3
+
+#define LPDDR4__DENALI_PHY_870__PHY_GTLVL_RESP_WAIT_CNT_3_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_870__PHY_GTLVL_RESP_WAIT_CNT_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_870__PHY_GTLVL_RESP_WAIT_CNT_3_WIDTH 5U
+#define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_3__REG DENALI_PHY_870
+#define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_3__FLD LPDDR4__DENALI_PHY_870__PHY_GTLVL_RESP_WAIT_CNT_3
+
+#define LPDDR4__DENALI_PHY_871_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_871_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_871__PHY_GTLVL_BACK_STEP_3_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_871__PHY_GTLVL_BACK_STEP_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_871__PHY_GTLVL_BACK_STEP_3_WIDTH 10U
+#define LPDDR4__PHY_GTLVL_BACK_STEP_3__REG DENALI_PHY_871
+#define LPDDR4__PHY_GTLVL_BACK_STEP_3__FLD LPDDR4__DENALI_PHY_871__PHY_GTLVL_BACK_STEP_3
+
+#define LPDDR4__DENALI_PHY_871__PHY_GTLVL_FINAL_STEP_3_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_871__PHY_GTLVL_FINAL_STEP_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_871__PHY_GTLVL_FINAL_STEP_3_WIDTH 10U
+#define LPDDR4__PHY_GTLVL_FINAL_STEP_3__REG DENALI_PHY_871
+#define LPDDR4__PHY_GTLVL_FINAL_STEP_3__FLD LPDDR4__DENALI_PHY_871__PHY_GTLVL_FINAL_STEP_3
+
+#define LPDDR4__DENALI_PHY_872_READ_MASK 0x01FF0FFFU
+#define LPDDR4__DENALI_PHY_872_WRITE_MASK 0x01FF0FFFU
+#define LPDDR4__DENALI_PHY_872__PHY_WDQLVL_DLY_STEP_3_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_872__PHY_WDQLVL_DLY_STEP_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_872__PHY_WDQLVL_DLY_STEP_3_WIDTH 8U
+#define LPDDR4__PHY_WDQLVL_DLY_STEP_3__REG DENALI_PHY_872
+#define LPDDR4__PHY_WDQLVL_DLY_STEP_3__FLD LPDDR4__DENALI_PHY_872__PHY_WDQLVL_DLY_STEP_3
+
+#define LPDDR4__DENALI_PHY_872__PHY_WDQLVL_QTR_DLY_STEP_3_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_872__PHY_WDQLVL_QTR_DLY_STEP_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_872__PHY_WDQLVL_QTR_DLY_STEP_3_WIDTH 4U
+#define LPDDR4__PHY_WDQLVL_QTR_DLY_STEP_3__REG DENALI_PHY_872
+#define LPDDR4__PHY_WDQLVL_QTR_DLY_STEP_3__FLD LPDDR4__DENALI_PHY_872__PHY_WDQLVL_QTR_DLY_STEP_3
+
+#define LPDDR4__DENALI_PHY_872__PHY_WDQLVL_DM_SEARCH_RANGE_3_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_872__PHY_WDQLVL_DM_SEARCH_RANGE_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_872__PHY_WDQLVL_DM_SEARCH_RANGE_3_WIDTH 9U
+#define LPDDR4__PHY_WDQLVL_DM_SEARCH_RANGE_3__REG DENALI_PHY_872
+#define LPDDR4__PHY_WDQLVL_DM_SEARCH_RANGE_3__FLD LPDDR4__DENALI_PHY_872__PHY_WDQLVL_DM_SEARCH_RANGE_3
+
+#define LPDDR4__DENALI_PHY_873_READ_MASK 0x00000F01U
+#define LPDDR4__DENALI_PHY_873_WRITE_MASK 0x00000F01U
+#define LPDDR4__DENALI_PHY_873__PHY_TOGGLE_PRE_SUPPORT_3_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_873__PHY_TOGGLE_PRE_SUPPORT_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_873__PHY_TOGGLE_PRE_SUPPORT_3_WIDTH 1U
+#define LPDDR4__DENALI_PHY_873__PHY_TOGGLE_PRE_SUPPORT_3_WOCLR 0U
+#define LPDDR4__DENALI_PHY_873__PHY_TOGGLE_PRE_SUPPORT_3_WOSET 0U
+#define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_3__REG DENALI_PHY_873
+#define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_3__FLD LPDDR4__DENALI_PHY_873__PHY_TOGGLE_PRE_SUPPORT_3
+
+#define LPDDR4__DENALI_PHY_873__PHY_RDLVL_DLY_STEP_3_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_873__PHY_RDLVL_DLY_STEP_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_873__PHY_RDLVL_DLY_STEP_3_WIDTH 4U
+#define LPDDR4__PHY_RDLVL_DLY_STEP_3__REG DENALI_PHY_873
+#define LPDDR4__PHY_RDLVL_DLY_STEP_3__FLD LPDDR4__DENALI_PHY_873__PHY_RDLVL_DLY_STEP_3
+
+#define LPDDR4__DENALI_PHY_874_READ_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_874_WRITE_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_874__PHY_RDLVL_MAX_EDGE_3_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_874__PHY_RDLVL_MAX_EDGE_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_874__PHY_RDLVL_MAX_EDGE_3_WIDTH 10U
+#define LPDDR4__PHY_RDLVL_MAX_EDGE_3__REG DENALI_PHY_874
+#define LPDDR4__PHY_RDLVL_MAX_EDGE_3__FLD LPDDR4__DENALI_PHY_874__PHY_RDLVL_MAX_EDGE_3
+
+#define LPDDR4__DENALI_PHY_875_READ_MASK 0x00030703U
+#define LPDDR4__DENALI_PHY_875_WRITE_MASK 0x00030703U
+#define LPDDR4__DENALI_PHY_875__PHY_WRPATH_GATE_DISABLE_3_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_875__PHY_WRPATH_GATE_DISABLE_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_875__PHY_WRPATH_GATE_DISABLE_3_WIDTH 2U
+#define LPDDR4__PHY_WRPATH_GATE_DISABLE_3__REG DENALI_PHY_875
+#define LPDDR4__PHY_WRPATH_GATE_DISABLE_3__FLD LPDDR4__DENALI_PHY_875__PHY_WRPATH_GATE_DISABLE_3
+
+#define LPDDR4__DENALI_PHY_875__PHY_WRPATH_GATE_TIMING_3_MASK 0x00000700U
+#define LPDDR4__DENALI_PHY_875__PHY_WRPATH_GATE_TIMING_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_875__PHY_WRPATH_GATE_TIMING_3_WIDTH 3U
+#define LPDDR4__PHY_WRPATH_GATE_TIMING_3__REG DENALI_PHY_875
+#define LPDDR4__PHY_WRPATH_GATE_TIMING_3__FLD LPDDR4__DENALI_PHY_875__PHY_WRPATH_GATE_TIMING_3
+
+#define LPDDR4__DENALI_PHY_875__PHY_DATA_DC_INIT_DISABLE_3_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_875__PHY_DATA_DC_INIT_DISABLE_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_875__PHY_DATA_DC_INIT_DISABLE_3_WIDTH 2U
+#define LPDDR4__PHY_DATA_DC_INIT_DISABLE_3__REG DENALI_PHY_875
+#define LPDDR4__PHY_DATA_DC_INIT_DISABLE_3__FLD LPDDR4__DENALI_PHY_875__PHY_DATA_DC_INIT_DISABLE_3
+
+#define LPDDR4__DENALI_PHY_876_READ_MASK 0x07FF03FFU
+#define LPDDR4__DENALI_PHY_876_WRITE_MASK 0x07FF03FFU
+#define LPDDR4__DENALI_PHY_876__PHY_DATA_DC_DQS_INIT_SLV_DELAY_3_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_876__PHY_DATA_DC_DQS_INIT_SLV_DELAY_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_876__PHY_DATA_DC_DQS_INIT_SLV_DELAY_3_WIDTH 10U
+#define LPDDR4__PHY_DATA_DC_DQS_INIT_SLV_DELAY_3__REG DENALI_PHY_876
+#define LPDDR4__PHY_DATA_DC_DQS_INIT_SLV_DELAY_3__FLD LPDDR4__DENALI_PHY_876__PHY_DATA_DC_DQS_INIT_SLV_DELAY_3
+
+#define LPDDR4__DENALI_PHY_876__PHY_DATA_DC_DQ_INIT_SLV_DELAY_3_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_876__PHY_DATA_DC_DQ_INIT_SLV_DELAY_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_876__PHY_DATA_DC_DQ_INIT_SLV_DELAY_3_WIDTH 11U
+#define LPDDR4__PHY_DATA_DC_DQ_INIT_SLV_DELAY_3__REG DENALI_PHY_876
+#define LPDDR4__PHY_DATA_DC_DQ_INIT_SLV_DELAY_3__FLD LPDDR4__DENALI_PHY_876__PHY_DATA_DC_DQ_INIT_SLV_DELAY_3
+
+#define LPDDR4__DENALI_PHY_877_READ_MASK 0xFFFF0101U
+#define LPDDR4__DENALI_PHY_877_WRITE_MASK 0xFFFF0101U
+#define LPDDR4__DENALI_PHY_877__PHY_DATA_DC_WRLVL_ENABLE_3_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_877__PHY_DATA_DC_WRLVL_ENABLE_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_877__PHY_DATA_DC_WRLVL_ENABLE_3_WIDTH 1U
+#define LPDDR4__DENALI_PHY_877__PHY_DATA_DC_WRLVL_ENABLE_3_WOCLR 0U
+#define LPDDR4__DENALI_PHY_877__PHY_DATA_DC_WRLVL_ENABLE_3_WOSET 0U
+#define LPDDR4__PHY_DATA_DC_WRLVL_ENABLE_3__REG DENALI_PHY_877
+#define LPDDR4__PHY_DATA_DC_WRLVL_ENABLE_3__FLD LPDDR4__DENALI_PHY_877__PHY_DATA_DC_WRLVL_ENABLE_3
+
+#define LPDDR4__DENALI_PHY_877__PHY_DATA_DC_WDQLVL_ENABLE_3_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_877__PHY_DATA_DC_WDQLVL_ENABLE_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_877__PHY_DATA_DC_WDQLVL_ENABLE_3_WIDTH 1U
+#define LPDDR4__DENALI_PHY_877__PHY_DATA_DC_WDQLVL_ENABLE_3_WOCLR 0U
+#define LPDDR4__DENALI_PHY_877__PHY_DATA_DC_WDQLVL_ENABLE_3_WOSET 0U
+#define LPDDR4__PHY_DATA_DC_WDQLVL_ENABLE_3__REG DENALI_PHY_877
+#define LPDDR4__PHY_DATA_DC_WDQLVL_ENABLE_3__FLD LPDDR4__DENALI_PHY_877__PHY_DATA_DC_WDQLVL_ENABLE_3
+
+#define LPDDR4__DENALI_PHY_877__PHY_DATA_DC_DM_CLK_SE_THRSHLD_3_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_877__PHY_DATA_DC_DM_CLK_SE_THRSHLD_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_877__PHY_DATA_DC_DM_CLK_SE_THRSHLD_3_WIDTH 8U
+#define LPDDR4__PHY_DATA_DC_DM_CLK_SE_THRSHLD_3__REG DENALI_PHY_877
+#define LPDDR4__PHY_DATA_DC_DM_CLK_SE_THRSHLD_3__FLD LPDDR4__DENALI_PHY_877__PHY_DATA_DC_DM_CLK_SE_THRSHLD_3
+
+#define LPDDR4__DENALI_PHY_877__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_3_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_877__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_877__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_3_WIDTH 8U
+#define LPDDR4__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_3__REG DENALI_PHY_877
+#define LPDDR4__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_3__FLD LPDDR4__DENALI_PHY_877__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_3
+
+#define LPDDR4__DENALI_PHY_878_READ_MASK 0x001F7F7FU
+#define LPDDR4__DENALI_PHY_878_WRITE_MASK 0x001F7F7FU
+#define LPDDR4__DENALI_PHY_878__PHY_WDQ_OSC_DELTA_3_MASK 0x0000007FU
+#define LPDDR4__DENALI_PHY_878__PHY_WDQ_OSC_DELTA_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_878__PHY_WDQ_OSC_DELTA_3_WIDTH 7U
+#define LPDDR4__PHY_WDQ_OSC_DELTA_3__REG DENALI_PHY_878
+#define LPDDR4__PHY_WDQ_OSC_DELTA_3__FLD LPDDR4__DENALI_PHY_878__PHY_WDQ_OSC_DELTA_3
+
+#define LPDDR4__DENALI_PHY_878__PHY_MEAS_DLY_STEP_ENABLE_3_MASK 0x00007F00U
+#define LPDDR4__DENALI_PHY_878__PHY_MEAS_DLY_STEP_ENABLE_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_878__PHY_MEAS_DLY_STEP_ENABLE_3_WIDTH 7U
+#define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_3__REG DENALI_PHY_878
+#define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_3__FLD LPDDR4__DENALI_PHY_878__PHY_MEAS_DLY_STEP_ENABLE_3
+
+#define LPDDR4__DENALI_PHY_878__PHY_RDDATA_EN_DLY_3_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_878__PHY_RDDATA_EN_DLY_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_878__PHY_RDDATA_EN_DLY_3_WIDTH 5U
+#define LPDDR4__PHY_RDDATA_EN_DLY_3__REG DENALI_PHY_878
+#define LPDDR4__PHY_RDDATA_EN_DLY_3__FLD LPDDR4__DENALI_PHY_878__PHY_RDDATA_EN_DLY_3
+
+#define LPDDR4__DENALI_PHY_879_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_879_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_879__PHY_DQ_DM_SWIZZLE0_3_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_879__PHY_DQ_DM_SWIZZLE0_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_879__PHY_DQ_DM_SWIZZLE0_3_WIDTH 32U
+#define LPDDR4__PHY_DQ_DM_SWIZZLE0_3__REG DENALI_PHY_879
+#define LPDDR4__PHY_DQ_DM_SWIZZLE0_3__FLD LPDDR4__DENALI_PHY_879__PHY_DQ_DM_SWIZZLE0_3
+
+#define LPDDR4__DENALI_PHY_880_READ_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_880_WRITE_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_880__PHY_DQ_DM_SWIZZLE1_3_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_880__PHY_DQ_DM_SWIZZLE1_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_880__PHY_DQ_DM_SWIZZLE1_3_WIDTH 4U
+#define LPDDR4__PHY_DQ_DM_SWIZZLE1_3__REG DENALI_PHY_880
+#define LPDDR4__PHY_DQ_DM_SWIZZLE1_3__FLD LPDDR4__DENALI_PHY_880__PHY_DQ_DM_SWIZZLE1_3
+
+#define LPDDR4__DENALI_PHY_881_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_881_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_881__PHY_CLK_WRDQ0_SLAVE_DELAY_3_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_881__PHY_CLK_WRDQ0_SLAVE_DELAY_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_881__PHY_CLK_WRDQ0_SLAVE_DELAY_3_WIDTH 11U
+#define LPDDR4__PHY_CLK_WRDQ0_SLAVE_DELAY_3__REG DENALI_PHY_881
+#define LPDDR4__PHY_CLK_WRDQ0_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_881__PHY_CLK_WRDQ0_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_881__PHY_CLK_WRDQ1_SLAVE_DELAY_3_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_881__PHY_CLK_WRDQ1_SLAVE_DELAY_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_881__PHY_CLK_WRDQ1_SLAVE_DELAY_3_WIDTH 11U
+#define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_3__REG DENALI_PHY_881
+#define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_881__PHY_CLK_WRDQ1_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_882_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_882_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_882__PHY_CLK_WRDQ2_SLAVE_DELAY_3_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_882__PHY_CLK_WRDQ2_SLAVE_DELAY_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_882__PHY_CLK_WRDQ2_SLAVE_DELAY_3_WIDTH 11U
+#define LPDDR4__PHY_CLK_WRDQ2_SLAVE_DELAY_3__REG DENALI_PHY_882
+#define LPDDR4__PHY_CLK_WRDQ2_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_882__PHY_CLK_WRDQ2_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_882__PHY_CLK_WRDQ3_SLAVE_DELAY_3_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_882__PHY_CLK_WRDQ3_SLAVE_DELAY_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_882__PHY_CLK_WRDQ3_SLAVE_DELAY_3_WIDTH 11U
+#define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_3__REG DENALI_PHY_882
+#define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_882__PHY_CLK_WRDQ3_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_883_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_883_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_883__PHY_CLK_WRDQ4_SLAVE_DELAY_3_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_883__PHY_CLK_WRDQ4_SLAVE_DELAY_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_883__PHY_CLK_WRDQ4_SLAVE_DELAY_3_WIDTH 11U
+#define LPDDR4__PHY_CLK_WRDQ4_SLAVE_DELAY_3__REG DENALI_PHY_883
+#define LPDDR4__PHY_CLK_WRDQ4_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_883__PHY_CLK_WRDQ4_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_883__PHY_CLK_WRDQ5_SLAVE_DELAY_3_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_883__PHY_CLK_WRDQ5_SLAVE_DELAY_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_883__PHY_CLK_WRDQ5_SLAVE_DELAY_3_WIDTH 11U
+#define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_3__REG DENALI_PHY_883
+#define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_883__PHY_CLK_WRDQ5_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_884_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_884_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_884__PHY_CLK_WRDQ6_SLAVE_DELAY_3_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_884__PHY_CLK_WRDQ6_SLAVE_DELAY_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_884__PHY_CLK_WRDQ6_SLAVE_DELAY_3_WIDTH 11U
+#define LPDDR4__PHY_CLK_WRDQ6_SLAVE_DELAY_3__REG DENALI_PHY_884
+#define LPDDR4__PHY_CLK_WRDQ6_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_884__PHY_CLK_WRDQ6_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_884__PHY_CLK_WRDQ7_SLAVE_DELAY_3_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_884__PHY_CLK_WRDQ7_SLAVE_DELAY_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_884__PHY_CLK_WRDQ7_SLAVE_DELAY_3_WIDTH 11U
+#define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_3__REG DENALI_PHY_884
+#define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_884__PHY_CLK_WRDQ7_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_885_READ_MASK 0x03FF07FFU
+#define LPDDR4__DENALI_PHY_885_WRITE_MASK 0x03FF07FFU
+#define LPDDR4__DENALI_PHY_885__PHY_CLK_WRDM_SLAVE_DELAY_3_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_885__PHY_CLK_WRDM_SLAVE_DELAY_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_885__PHY_CLK_WRDM_SLAVE_DELAY_3_WIDTH 11U
+#define LPDDR4__PHY_CLK_WRDM_SLAVE_DELAY_3__REG DENALI_PHY_885
+#define LPDDR4__PHY_CLK_WRDM_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_885__PHY_CLK_WRDM_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_885__PHY_CLK_WRDQS_SLAVE_DELAY_3_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_885__PHY_CLK_WRDQS_SLAVE_DELAY_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_885__PHY_CLK_WRDQS_SLAVE_DELAY_3_WIDTH 10U
+#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_3__REG DENALI_PHY_885
+#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_885__PHY_CLK_WRDQS_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_886_READ_MASK 0x0003FF03U
+#define LPDDR4__DENALI_PHY_886_WRITE_MASK 0x0003FF03U
+#define LPDDR4__DENALI_PHY_886__PHY_WRLVL_THRESHOLD_ADJUST_3_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_886__PHY_WRLVL_THRESHOLD_ADJUST_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_886__PHY_WRLVL_THRESHOLD_ADJUST_3_WIDTH 2U
+#define LPDDR4__PHY_WRLVL_THRESHOLD_ADJUST_3__REG DENALI_PHY_886
+#define LPDDR4__PHY_WRLVL_THRESHOLD_ADJUST_3__FLD LPDDR4__DENALI_PHY_886__PHY_WRLVL_THRESHOLD_ADJUST_3
+
+#define LPDDR4__DENALI_PHY_886__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_3_MASK 0x0003FF00U
+#define LPDDR4__DENALI_PHY_886__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_886__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_3_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_3__REG DENALI_PHY_886
+#define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_886__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_887_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_887_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_887__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_3_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_887__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_887__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_3_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_3__REG DENALI_PHY_887
+#define LPDDR4__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_887__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_887__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_3_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_887__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_887__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_3_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_3__REG DENALI_PHY_887
+#define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_887__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_888_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_888_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_888__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_3_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_888__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_888__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_3_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_3__REG DENALI_PHY_888
+#define LPDDR4__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_888__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_888__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_3_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_888__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_888__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_3_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_3__REG DENALI_PHY_888
+#define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_888__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_889_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_889_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_889__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_3_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_889__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_889__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_3_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_3__REG DENALI_PHY_889
+#define LPDDR4__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_889__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_889__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_3_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_889__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_889__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_3_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_3__REG DENALI_PHY_889
+#define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_889__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_890_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_890_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_890__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_3_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_890__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_890__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_3_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_3__REG DENALI_PHY_890
+#define LPDDR4__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_890__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_890__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_3_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_890__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_890__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_3_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_3__REG DENALI_PHY_890
+#define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_890__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_891_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_891_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_891__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_3_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_891__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_891__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_3_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_3__REG DENALI_PHY_891
+#define LPDDR4__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_891__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_891__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_3_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_891__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_891__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_3_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_3__REG DENALI_PHY_891
+#define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_891__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_892_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_892_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_892__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_3_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_892__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_892__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_3_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_3__REG DENALI_PHY_892
+#define LPDDR4__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_892__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_892__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_3_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_892__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_892__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_3_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_3__REG DENALI_PHY_892
+#define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_892__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_893_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_893_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_893__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_3_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_893__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_893__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_3_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_3__REG DENALI_PHY_893
+#define LPDDR4__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_893__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_893__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_3_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_893__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_893__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_3_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_3__REG DENALI_PHY_893
+#define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_893__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_894_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_894_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_894__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_3_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_894__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_894__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_3_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_3__REG DENALI_PHY_894
+#define LPDDR4__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_894__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_894__PHY_RDDQS_DM_RISE_SLAVE_DELAY_3_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_894__PHY_RDDQS_DM_RISE_SLAVE_DELAY_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_894__PHY_RDDQS_DM_RISE_SLAVE_DELAY_3_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_3__REG DENALI_PHY_894
+#define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_894__PHY_RDDQS_DM_RISE_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_895_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_895_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_895__PHY_RDDQS_DM_FALL_SLAVE_DELAY_3_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_895__PHY_RDDQS_DM_FALL_SLAVE_DELAY_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_895__PHY_RDDQS_DM_FALL_SLAVE_DELAY_3_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DM_FALL_SLAVE_DELAY_3__REG DENALI_PHY_895
+#define LPDDR4__PHY_RDDQS_DM_FALL_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_895__PHY_RDDQS_DM_FALL_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_895__PHY_RDDQS_GATE_SLAVE_DELAY_3_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_895__PHY_RDDQS_GATE_SLAVE_DELAY_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_895__PHY_RDDQS_GATE_SLAVE_DELAY_3_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_3__REG DENALI_PHY_895
+#define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_895__PHY_RDDQS_GATE_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_896_READ_MASK 0x03FF070FU
+#define LPDDR4__DENALI_PHY_896_WRITE_MASK 0x03FF070FU
+#define LPDDR4__DENALI_PHY_896__PHY_RDDQS_LATENCY_ADJUST_3_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_896__PHY_RDDQS_LATENCY_ADJUST_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_896__PHY_RDDQS_LATENCY_ADJUST_3_WIDTH 4U
+#define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_3__REG DENALI_PHY_896
+#define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_3__FLD LPDDR4__DENALI_PHY_896__PHY_RDDQS_LATENCY_ADJUST_3
+
+#define LPDDR4__DENALI_PHY_896__PHY_WRITE_PATH_LAT_ADD_3_MASK 0x00000700U
+#define LPDDR4__DENALI_PHY_896__PHY_WRITE_PATH_LAT_ADD_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_896__PHY_WRITE_PATH_LAT_ADD_3_WIDTH 3U
+#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_3__REG DENALI_PHY_896
+#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_3__FLD LPDDR4__DENALI_PHY_896__PHY_WRITE_PATH_LAT_ADD_3
+
+#define LPDDR4__DENALI_PHY_896__PHY_WRLVL_DELAY_EARLY_THRESHOLD_3_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_896__PHY_WRLVL_DELAY_EARLY_THRESHOLD_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_896__PHY_WRLVL_DELAY_EARLY_THRESHOLD_3_WIDTH 10U
+#define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_3__REG DENALI_PHY_896
+#define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_3__FLD LPDDR4__DENALI_PHY_896__PHY_WRLVL_DELAY_EARLY_THRESHOLD_3
+
+#define LPDDR4__DENALI_PHY_897_READ_MASK 0x000103FFU
+#define LPDDR4__DENALI_PHY_897_WRITE_MASK 0x000103FFU
+#define LPDDR4__DENALI_PHY_897__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_3_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_897__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_897__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_3_WIDTH 10U
+#define LPDDR4__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_3__REG DENALI_PHY_897
+#define LPDDR4__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_3__FLD LPDDR4__DENALI_PHY_897__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_3
+
+#define LPDDR4__DENALI_PHY_897__PHY_WRLVL_EARLY_FORCE_ZERO_3_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_897__PHY_WRLVL_EARLY_FORCE_ZERO_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_897__PHY_WRLVL_EARLY_FORCE_ZERO_3_WIDTH 1U
+#define LPDDR4__DENALI_PHY_897__PHY_WRLVL_EARLY_FORCE_ZERO_3_WOCLR 0U
+#define LPDDR4__DENALI_PHY_897__PHY_WRLVL_EARLY_FORCE_ZERO_3_WOSET 0U
+#define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_3__REG DENALI_PHY_897
+#define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_3__FLD LPDDR4__DENALI_PHY_897__PHY_WRLVL_EARLY_FORCE_ZERO_3
+
+#define LPDDR4__DENALI_PHY_898_READ_MASK 0x000F03FFU
+#define LPDDR4__DENALI_PHY_898_WRITE_MASK 0x000F03FFU
+#define LPDDR4__DENALI_PHY_898__PHY_GTLVL_RDDQS_SLV_DLY_START_3_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_898__PHY_GTLVL_RDDQS_SLV_DLY_START_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_898__PHY_GTLVL_RDDQS_SLV_DLY_START_3_WIDTH 10U
+#define LPDDR4__PHY_GTLVL_RDDQS_SLV_DLY_START_3__REG DENALI_PHY_898
+#define LPDDR4__PHY_GTLVL_RDDQS_SLV_DLY_START_3__FLD LPDDR4__DENALI_PHY_898__PHY_GTLVL_RDDQS_SLV_DLY_START_3
+
+#define LPDDR4__DENALI_PHY_898__PHY_GTLVL_LAT_ADJ_START_3_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_898__PHY_GTLVL_LAT_ADJ_START_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_898__PHY_GTLVL_LAT_ADJ_START_3_WIDTH 4U
+#define LPDDR4__PHY_GTLVL_LAT_ADJ_START_3__REG DENALI_PHY_898
+#define LPDDR4__PHY_GTLVL_LAT_ADJ_START_3__FLD LPDDR4__DENALI_PHY_898__PHY_GTLVL_LAT_ADJ_START_3
+
+#define LPDDR4__DENALI_PHY_899_READ_MASK 0x010F07FFU
+#define LPDDR4__DENALI_PHY_899_WRITE_MASK 0x010F07FFU
+#define LPDDR4__DENALI_PHY_899__PHY_WDQLVL_DQDM_SLV_DLY_START_3_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_899__PHY_WDQLVL_DQDM_SLV_DLY_START_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_899__PHY_WDQLVL_DQDM_SLV_DLY_START_3_WIDTH 11U
+#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_3__REG DENALI_PHY_899
+#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_3__FLD LPDDR4__DENALI_PHY_899__PHY_WDQLVL_DQDM_SLV_DLY_START_3
+
+#define LPDDR4__DENALI_PHY_899__PHY_NTP_WRLAT_START_3_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_899__PHY_NTP_WRLAT_START_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_899__PHY_NTP_WRLAT_START_3_WIDTH 4U
+#define LPDDR4__PHY_NTP_WRLAT_START_3__REG DENALI_PHY_899
+#define LPDDR4__PHY_NTP_WRLAT_START_3__FLD LPDDR4__DENALI_PHY_899__PHY_NTP_WRLAT_START_3
+
+#define LPDDR4__DENALI_PHY_899__PHY_NTP_PASS_3_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_899__PHY_NTP_PASS_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_899__PHY_NTP_PASS_3_WIDTH 1U
+#define LPDDR4__DENALI_PHY_899__PHY_NTP_PASS_3_WOCLR 0U
+#define LPDDR4__DENALI_PHY_899__PHY_NTP_PASS_3_WOSET 0U
+#define LPDDR4__PHY_NTP_PASS_3__REG DENALI_PHY_899
+#define LPDDR4__PHY_NTP_PASS_3__FLD LPDDR4__DENALI_PHY_899__PHY_NTP_PASS_3
+
+#define LPDDR4__DENALI_PHY_900_READ_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_900_WRITE_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_900__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_3_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_900__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_900__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_3_WIDTH 10U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_3__REG DENALI_PHY_900
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_3__FLD LPDDR4__DENALI_PHY_900__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_3
+
+#define LPDDR4__DENALI_PHY_901_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_901_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_901__PHY_DATA_DC_DQS_CLK_ADJUST_3_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_901__PHY_DATA_DC_DQS_CLK_ADJUST_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_901__PHY_DATA_DC_DQS_CLK_ADJUST_3_WIDTH 8U
+#define LPDDR4__PHY_DATA_DC_DQS_CLK_ADJUST_3__REG DENALI_PHY_901
+#define LPDDR4__PHY_DATA_DC_DQS_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_901__PHY_DATA_DC_DQS_CLK_ADJUST_3
+
+#define LPDDR4__DENALI_PHY_901__PHY_DATA_DC_DQ0_CLK_ADJUST_3_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_901__PHY_DATA_DC_DQ0_CLK_ADJUST_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_901__PHY_DATA_DC_DQ0_CLK_ADJUST_3_WIDTH 8U
+#define LPDDR4__PHY_DATA_DC_DQ0_CLK_ADJUST_3__REG DENALI_PHY_901
+#define LPDDR4__PHY_DATA_DC_DQ0_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_901__PHY_DATA_DC_DQ0_CLK_ADJUST_3
+
+#define LPDDR4__DENALI_PHY_901__PHY_DATA_DC_DQ1_CLK_ADJUST_3_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_901__PHY_DATA_DC_DQ1_CLK_ADJUST_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_901__PHY_DATA_DC_DQ1_CLK_ADJUST_3_WIDTH 8U
+#define LPDDR4__PHY_DATA_DC_DQ1_CLK_ADJUST_3__REG DENALI_PHY_901
+#define LPDDR4__PHY_DATA_DC_DQ1_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_901__PHY_DATA_DC_DQ1_CLK_ADJUST_3
+
+#define LPDDR4__DENALI_PHY_901__PHY_DATA_DC_DQ2_CLK_ADJUST_3_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_901__PHY_DATA_DC_DQ2_CLK_ADJUST_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_901__PHY_DATA_DC_DQ2_CLK_ADJUST_3_WIDTH 8U
+#define LPDDR4__PHY_DATA_DC_DQ2_CLK_ADJUST_3__REG DENALI_PHY_901
+#define LPDDR4__PHY_DATA_DC_DQ2_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_901__PHY_DATA_DC_DQ2_CLK_ADJUST_3
+
+#define LPDDR4__DENALI_PHY_902_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_902_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_902__PHY_DATA_DC_DQ3_CLK_ADJUST_3_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_902__PHY_DATA_DC_DQ3_CLK_ADJUST_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_902__PHY_DATA_DC_DQ3_CLK_ADJUST_3_WIDTH 8U
+#define LPDDR4__PHY_DATA_DC_DQ3_CLK_ADJUST_3__REG DENALI_PHY_902
+#define LPDDR4__PHY_DATA_DC_DQ3_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_902__PHY_DATA_DC_DQ3_CLK_ADJUST_3
+
+#define LPDDR4__DENALI_PHY_902__PHY_DATA_DC_DQ4_CLK_ADJUST_3_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_902__PHY_DATA_DC_DQ4_CLK_ADJUST_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_902__PHY_DATA_DC_DQ4_CLK_ADJUST_3_WIDTH 8U
+#define LPDDR4__PHY_DATA_DC_DQ4_CLK_ADJUST_3__REG DENALI_PHY_902
+#define LPDDR4__PHY_DATA_DC_DQ4_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_902__PHY_DATA_DC_DQ4_CLK_ADJUST_3
+
+#define LPDDR4__DENALI_PHY_902__PHY_DATA_DC_DQ5_CLK_ADJUST_3_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_902__PHY_DATA_DC_DQ5_CLK_ADJUST_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_902__PHY_DATA_DC_DQ5_CLK_ADJUST_3_WIDTH 8U
+#define LPDDR4__PHY_DATA_DC_DQ5_CLK_ADJUST_3__REG DENALI_PHY_902
+#define LPDDR4__PHY_DATA_DC_DQ5_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_902__PHY_DATA_DC_DQ5_CLK_ADJUST_3
+
+#define LPDDR4__DENALI_PHY_902__PHY_DATA_DC_DQ6_CLK_ADJUST_3_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_902__PHY_DATA_DC_DQ6_CLK_ADJUST_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_902__PHY_DATA_DC_DQ6_CLK_ADJUST_3_WIDTH 8U
+#define LPDDR4__PHY_DATA_DC_DQ6_CLK_ADJUST_3__REG DENALI_PHY_902
+#define LPDDR4__PHY_DATA_DC_DQ6_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_902__PHY_DATA_DC_DQ6_CLK_ADJUST_3
+
+#define LPDDR4__DENALI_PHY_903_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_903_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_903__PHY_DATA_DC_DQ7_CLK_ADJUST_3_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_903__PHY_DATA_DC_DQ7_CLK_ADJUST_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_903__PHY_DATA_DC_DQ7_CLK_ADJUST_3_WIDTH 8U
+#define LPDDR4__PHY_DATA_DC_DQ7_CLK_ADJUST_3__REG DENALI_PHY_903
+#define LPDDR4__PHY_DATA_DC_DQ7_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_903__PHY_DATA_DC_DQ7_CLK_ADJUST_3
+
+#define LPDDR4__DENALI_PHY_903__PHY_DATA_DC_DM_CLK_ADJUST_3_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_903__PHY_DATA_DC_DM_CLK_ADJUST_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_903__PHY_DATA_DC_DM_CLK_ADJUST_3_WIDTH 8U
+#define LPDDR4__PHY_DATA_DC_DM_CLK_ADJUST_3__REG DENALI_PHY_903
+#define LPDDR4__PHY_DATA_DC_DM_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_903__PHY_DATA_DC_DM_CLK_ADJUST_3
+
+#define LPDDR4__DENALI_PHY_903__PHY_DSLICE_PAD_BOOSTPN_SETTING_3_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_PHY_903__PHY_DSLICE_PAD_BOOSTPN_SETTING_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_903__PHY_DSLICE_PAD_BOOSTPN_SETTING_3_WIDTH 16U
+#define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_3__REG DENALI_PHY_903
+#define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_3__FLD LPDDR4__DENALI_PHY_903__PHY_DSLICE_PAD_BOOSTPN_SETTING_3
+
+#define LPDDR4__DENALI_PHY_904_READ_MASK 0x0003033FU
+#define LPDDR4__DENALI_PHY_904_WRITE_MASK 0x0003033FU
+#define LPDDR4__DENALI_PHY_904__PHY_DSLICE_PAD_RX_CTLE_SETTING_3_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_904__PHY_DSLICE_PAD_RX_CTLE_SETTING_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_904__PHY_DSLICE_PAD_RX_CTLE_SETTING_3_WIDTH 6U
+#define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_3__REG DENALI_PHY_904
+#define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_3__FLD LPDDR4__DENALI_PHY_904__PHY_DSLICE_PAD_RX_CTLE_SETTING_3
+
+#define LPDDR4__DENALI_PHY_904__PHY_DQ_FFE_3_MASK 0x00000300U
+#define LPDDR4__DENALI_PHY_904__PHY_DQ_FFE_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_904__PHY_DQ_FFE_3_WIDTH 2U
+#define LPDDR4__PHY_DQ_FFE_3__REG DENALI_PHY_904
+#define LPDDR4__PHY_DQ_FFE_3__FLD LPDDR4__DENALI_PHY_904__PHY_DQ_FFE_3
+
+#define LPDDR4__DENALI_PHY_904__PHY_DQS_FFE_3_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_904__PHY_DQS_FFE_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_904__PHY_DQS_FFE_3_WIDTH 2U
+#define LPDDR4__PHY_DQS_FFE_3__REG DENALI_PHY_904
+#define LPDDR4__PHY_DQS_FFE_3__FLD LPDDR4__DENALI_PHY_904__PHY_DQS_FFE_3
+
+#endif /* REG_LPDDR4_DATA_SLICE_3_MACROS_H_ */
diff --git a/drivers/ram/k3-ddrss/am62a/lpddr4_ddr_controller_macros.h b/drivers/ram/k3-ddrss/am62a/lpddr4_ddr_controller_macros.h
new file mode 100644
index 00000000000..61ae622a79a
--- /dev/null
+++ b/drivers/ram/k3-ddrss/am62a/lpddr4_ddr_controller_macros.h
@@ -0,0 +1,6560 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef REG_LPDDR4_DDR_CONTROLLER_MACROS_H_
+#define REG_LPDDR4_DDR_CONTROLLER_MACROS_H_
+
+#define LPDDR4__DENALI_CTL_0_READ_MASK 0xFFFF0F01U
+#define LPDDR4__DENALI_CTL_0_WRITE_MASK 0xFFFF0F01U
+#define LPDDR4__DENALI_CTL_0__START_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_0__START_SHIFT 0U
+#define LPDDR4__DENALI_CTL_0__START_WIDTH 1U
+#define LPDDR4__DENALI_CTL_0__START_WOCLR 0U
+#define LPDDR4__DENALI_CTL_0__START_WOSET 0U
+#define LPDDR4__START__REG DENALI_CTL_0
+#define LPDDR4__START__FLD LPDDR4__DENALI_CTL_0__START
+
+#define LPDDR4__DENALI_CTL_0__DRAM_CLASS_MASK 0x00000F00U
+#define LPDDR4__DENALI_CTL_0__DRAM_CLASS_SHIFT 8U
+#define LPDDR4__DENALI_CTL_0__DRAM_CLASS_WIDTH 4U
+#define LPDDR4__DRAM_CLASS__REG DENALI_CTL_0
+#define LPDDR4__DRAM_CLASS__FLD LPDDR4__DENALI_CTL_0__DRAM_CLASS
+
+#define LPDDR4__DENALI_CTL_0__CONTROLLER_ID_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_0__CONTROLLER_ID_SHIFT 16U
+#define LPDDR4__DENALI_CTL_0__CONTROLLER_ID_WIDTH 16U
+#define LPDDR4__CONTROLLER_ID__REG DENALI_CTL_0
+#define LPDDR4__CONTROLLER_ID__FLD LPDDR4__DENALI_CTL_0__CONTROLLER_ID
+
+#define LPDDR4__DENALI_CTL_1_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_1_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_1__CONTROLLER_VERSION_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_1__CONTROLLER_VERSION_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_1__CONTROLLER_VERSION_0_WIDTH 32U
+#define LPDDR4__CONTROLLER_VERSION_0__REG DENALI_CTL_1
+#define LPDDR4__CONTROLLER_VERSION_0__FLD LPDDR4__DENALI_CTL_1__CONTROLLER_VERSION_0
+
+#define LPDDR4__DENALI_CTL_2_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_2_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_2__CONTROLLER_VERSION_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_2__CONTROLLER_VERSION_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_2__CONTROLLER_VERSION_1_WIDTH 32U
+#define LPDDR4__CONTROLLER_VERSION_1__REG DENALI_CTL_2
+#define LPDDR4__CONTROLLER_VERSION_1__FLD LPDDR4__DENALI_CTL_2__CONTROLLER_VERSION_1
+
+#define LPDDR4__DENALI_CTL_3_READ_MASK 0xFF030F1FU
+#define LPDDR4__DENALI_CTL_3_WRITE_MASK 0xFF030F1FU
+#define LPDDR4__DENALI_CTL_3__MAX_ROW_REG_MASK 0x0000001FU
+#define LPDDR4__DENALI_CTL_3__MAX_ROW_REG_SHIFT 0U
+#define LPDDR4__DENALI_CTL_3__MAX_ROW_REG_WIDTH 5U
+#define LPDDR4__MAX_ROW_REG__REG DENALI_CTL_3
+#define LPDDR4__MAX_ROW_REG__FLD LPDDR4__DENALI_CTL_3__MAX_ROW_REG
+
+#define LPDDR4__DENALI_CTL_3__MAX_COL_REG_MASK 0x00000F00U
+#define LPDDR4__DENALI_CTL_3__MAX_COL_REG_SHIFT 8U
+#define LPDDR4__DENALI_CTL_3__MAX_COL_REG_WIDTH 4U
+#define LPDDR4__MAX_COL_REG__REG DENALI_CTL_3
+#define LPDDR4__MAX_COL_REG__FLD LPDDR4__DENALI_CTL_3__MAX_COL_REG
+
+#define LPDDR4__DENALI_CTL_3__MAX_CS_REG_MASK 0x00030000U
+#define LPDDR4__DENALI_CTL_3__MAX_CS_REG_SHIFT 16U
+#define LPDDR4__DENALI_CTL_3__MAX_CS_REG_WIDTH 2U
+#define LPDDR4__MAX_CS_REG__REG DENALI_CTL_3
+#define LPDDR4__MAX_CS_REG__FLD LPDDR4__DENALI_CTL_3__MAX_CS_REG
+
+#define LPDDR4__DENALI_CTL_3__READ_DATA_FIFO_DEPTH_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_3__READ_DATA_FIFO_DEPTH_SHIFT 24U
+#define LPDDR4__DENALI_CTL_3__READ_DATA_FIFO_DEPTH_WIDTH 8U
+#define LPDDR4__READ_DATA_FIFO_DEPTH__REG DENALI_CTL_3
+#define LPDDR4__READ_DATA_FIFO_DEPTH__FLD LPDDR4__DENALI_CTL_3__READ_DATA_FIFO_DEPTH
+
+#define LPDDR4__DENALI_CTL_4_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_4_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_4__READ_DATA_FIFO_PTR_WIDTH_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_4__READ_DATA_FIFO_PTR_WIDTH_SHIFT 0U
+#define LPDDR4__DENALI_CTL_4__READ_DATA_FIFO_PTR_WIDTH_WIDTH 8U
+#define LPDDR4__READ_DATA_FIFO_PTR_WIDTH__REG DENALI_CTL_4
+#define LPDDR4__READ_DATA_FIFO_PTR_WIDTH__FLD LPDDR4__DENALI_CTL_4__READ_DATA_FIFO_PTR_WIDTH
+
+#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_DEPTH_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_DEPTH_SHIFT 8U
+#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_DEPTH_WIDTH 8U
+#define LPDDR4__WRITE_DATA_FIFO_DEPTH__REG DENALI_CTL_4
+#define LPDDR4__WRITE_DATA_FIFO_DEPTH__FLD LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_DEPTH
+
+#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_PTR_WIDTH_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_PTR_WIDTH_SHIFT 16U
+#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_PTR_WIDTH_WIDTH 8U
+#define LPDDR4__WRITE_DATA_FIFO_PTR_WIDTH__REG DENALI_CTL_4
+#define LPDDR4__WRITE_DATA_FIFO_PTR_WIDTH__FLD LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_PTR_WIDTH
+
+#define LPDDR4__DENALI_CTL_5_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_5_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_DEPTH_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_DEPTH_SHIFT 0U
+#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_DEPTH_WIDTH 16U
+#define LPDDR4__MEMCD_RMODW_FIFO_DEPTH__REG DENALI_CTL_5
+#define LPDDR4__MEMCD_RMODW_FIFO_DEPTH__FLD LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_DEPTH
+
+#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_PTR_WIDTH_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_PTR_WIDTH_SHIFT 16U
+#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_PTR_WIDTH_WIDTH 8U
+#define LPDDR4__MEMCD_RMODW_FIFO_PTR_WIDTH__REG DENALI_CTL_5
+#define LPDDR4__MEMCD_RMODW_FIFO_PTR_WIDTH__FLD LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_PTR_WIDTH
+
+#define LPDDR4__DENALI_CTL_5__ASYNC_CDC_STAGES_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_5__ASYNC_CDC_STAGES_SHIFT 24U
+#define LPDDR4__DENALI_CTL_5__ASYNC_CDC_STAGES_WIDTH 8U
+#define LPDDR4__ASYNC_CDC_STAGES__REG DENALI_CTL_5
+#define LPDDR4__ASYNC_CDC_STAGES__FLD LPDDR4__DENALI_CTL_5__ASYNC_CDC_STAGES
+
+#define LPDDR4__DENALI_CTL_6_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_6_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_6__AXI0_CMDFIFO_LOG2_DEPTH_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_6__AXI0_CMDFIFO_LOG2_DEPTH_SHIFT 0U
+#define LPDDR4__DENALI_CTL_6__AXI0_CMDFIFO_LOG2_DEPTH_WIDTH 8U
+#define LPDDR4__AXI0_CMDFIFO_LOG2_DEPTH__REG DENALI_CTL_6
+#define LPDDR4__AXI0_CMDFIFO_LOG2_DEPTH__FLD LPDDR4__DENALI_CTL_6__AXI0_CMDFIFO_LOG2_DEPTH
+
+#define LPDDR4__DENALI_CTL_6__AXI0_RDFIFO_LOG2_DEPTH_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_6__AXI0_RDFIFO_LOG2_DEPTH_SHIFT 8U
+#define LPDDR4__DENALI_CTL_6__AXI0_RDFIFO_LOG2_DEPTH_WIDTH 8U
+#define LPDDR4__AXI0_RDFIFO_LOG2_DEPTH__REG DENALI_CTL_6
+#define LPDDR4__AXI0_RDFIFO_LOG2_DEPTH__FLD LPDDR4__DENALI_CTL_6__AXI0_RDFIFO_LOG2_DEPTH
+
+#define LPDDR4__DENALI_CTL_6__AXI0_WR_ARRAY_LOG2_DEPTH_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_6__AXI0_WR_ARRAY_LOG2_DEPTH_SHIFT 16U
+#define LPDDR4__DENALI_CTL_6__AXI0_WR_ARRAY_LOG2_DEPTH_WIDTH 8U
+#define LPDDR4__AXI0_WR_ARRAY_LOG2_DEPTH__REG DENALI_CTL_6
+#define LPDDR4__AXI0_WR_ARRAY_LOG2_DEPTH__FLD LPDDR4__DENALI_CTL_6__AXI0_WR_ARRAY_LOG2_DEPTH
+
+#define LPDDR4__DENALI_CTL_6__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_6__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH_SHIFT 24U
+#define LPDDR4__DENALI_CTL_6__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH_WIDTH 8U
+#define LPDDR4__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH__REG DENALI_CTL_6
+#define LPDDR4__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH__FLD LPDDR4__DENALI_CTL_6__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH
+
+#define LPDDR4__DENALI_CTL_7_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_7_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_7__TINIT_F0_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_7__TINIT_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_7__TINIT_F0_WIDTH 24U
+#define LPDDR4__TINIT_F0__REG DENALI_CTL_7
+#define LPDDR4__TINIT_F0__FLD LPDDR4__DENALI_CTL_7__TINIT_F0
+
+#define LPDDR4__DENALI_CTL_8_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_8_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_8__TINIT3_F0_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_8__TINIT3_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_8__TINIT3_F0_WIDTH 24U
+#define LPDDR4__TINIT3_F0__REG DENALI_CTL_8
+#define LPDDR4__TINIT3_F0__FLD LPDDR4__DENALI_CTL_8__TINIT3_F0
+
+#define LPDDR4__DENALI_CTL_9_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_9_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_9__TINIT4_F0_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_9__TINIT4_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_9__TINIT4_F0_WIDTH 24U
+#define LPDDR4__TINIT4_F0__REG DENALI_CTL_9
+#define LPDDR4__TINIT4_F0__FLD LPDDR4__DENALI_CTL_9__TINIT4_F0
+
+#define LPDDR4__DENALI_CTL_10_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_10_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_10__TINIT5_F0_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_10__TINIT5_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_10__TINIT5_F0_WIDTH 24U
+#define LPDDR4__TINIT5_F0__REG DENALI_CTL_10
+#define LPDDR4__TINIT5_F0__FLD LPDDR4__DENALI_CTL_10__TINIT5_F0
+
+#define LPDDR4__DENALI_CTL_11_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_11_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_11__TINIT_F1_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_11__TINIT_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_11__TINIT_F1_WIDTH 24U
+#define LPDDR4__TINIT_F1__REG DENALI_CTL_11
+#define LPDDR4__TINIT_F1__FLD LPDDR4__DENALI_CTL_11__TINIT_F1
+
+#define LPDDR4__DENALI_CTL_12_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_12_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_12__TINIT3_F1_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_12__TINIT3_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_12__TINIT3_F1_WIDTH 24U
+#define LPDDR4__TINIT3_F1__REG DENALI_CTL_12
+#define LPDDR4__TINIT3_F1__FLD LPDDR4__DENALI_CTL_12__TINIT3_F1
+
+#define LPDDR4__DENALI_CTL_13_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_13_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_13__TINIT4_F1_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_13__TINIT4_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_13__TINIT4_F1_WIDTH 24U
+#define LPDDR4__TINIT4_F1__REG DENALI_CTL_13
+#define LPDDR4__TINIT4_F1__FLD LPDDR4__DENALI_CTL_13__TINIT4_F1
+
+#define LPDDR4__DENALI_CTL_14_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_14_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_14__TINIT5_F1_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_14__TINIT5_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_14__TINIT5_F1_WIDTH 24U
+#define LPDDR4__TINIT5_F1__REG DENALI_CTL_14
+#define LPDDR4__TINIT5_F1__FLD LPDDR4__DENALI_CTL_14__TINIT5_F1
+
+#define LPDDR4__DENALI_CTL_15_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_15_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_15__TINIT_F2_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_15__TINIT_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_15__TINIT_F2_WIDTH 24U
+#define LPDDR4__TINIT_F2__REG DENALI_CTL_15
+#define LPDDR4__TINIT_F2__FLD LPDDR4__DENALI_CTL_15__TINIT_F2
+
+#define LPDDR4__DENALI_CTL_16_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_16_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_16__TINIT3_F2_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_16__TINIT3_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_16__TINIT3_F2_WIDTH 24U
+#define LPDDR4__TINIT3_F2__REG DENALI_CTL_16
+#define LPDDR4__TINIT3_F2__FLD LPDDR4__DENALI_CTL_16__TINIT3_F2
+
+#define LPDDR4__DENALI_CTL_17_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_17_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_17__TINIT4_F2_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_17__TINIT4_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_17__TINIT4_F2_WIDTH 24U
+#define LPDDR4__TINIT4_F2__REG DENALI_CTL_17
+#define LPDDR4__TINIT4_F2__FLD LPDDR4__DENALI_CTL_17__TINIT4_F2
+
+#define LPDDR4__DENALI_CTL_18_READ_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_18_WRITE_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_18__TINIT5_F2_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_18__TINIT5_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_18__TINIT5_F2_WIDTH 24U
+#define LPDDR4__TINIT5_F2__REG DENALI_CTL_18
+#define LPDDR4__TINIT5_F2__FLD LPDDR4__DENALI_CTL_18__TINIT5_F2
+
+#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_SHIFT 24U
+#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_WIDTH 1U
+#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_WOCLR 0U
+#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_WOSET 0U
+#define LPDDR4__NO_AUTO_MRR_INIT__REG DENALI_CTL_18
+#define LPDDR4__NO_AUTO_MRR_INIT__FLD LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT
+
+#define LPDDR4__DENALI_CTL_19_READ_MASK 0x03030301U
+#define LPDDR4__DENALI_CTL_19_WRITE_MASK 0x03030301U
+#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_SHIFT 0U
+#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_WIDTH 1U
+#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_WOCLR 0U
+#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_WOSET 0U
+#define LPDDR4__MRR_ERROR_STATUS__REG DENALI_CTL_19
+#define LPDDR4__MRR_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS
+
+#define LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F0_MASK 0x00000300U
+#define LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F0_WIDTH 2U
+#define LPDDR4__DFI_FREQ_RATIO_F0__REG DENALI_CTL_19
+#define LPDDR4__DFI_FREQ_RATIO_F0__FLD LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F0
+
+#define LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F1_MASK 0x00030000U
+#define LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F1_WIDTH 2U
+#define LPDDR4__DFI_FREQ_RATIO_F1__REG DENALI_CTL_19
+#define LPDDR4__DFI_FREQ_RATIO_F1__FLD LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F1
+
+#define LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F2_MASK 0x03000000U
+#define LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F2_SHIFT 24U
+#define LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F2_WIDTH 2U
+#define LPDDR4__DFI_FREQ_RATIO_F2__REG DENALI_CTL_19
+#define LPDDR4__DFI_FREQ_RATIO_F2__FLD LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F2
+
+#define LPDDR4__DENALI_CTL_20_READ_MASK 0x01030101U
+#define LPDDR4__DENALI_CTL_20_WRITE_MASK 0x01030101U
+#define LPDDR4__DENALI_CTL_20__DFI_CMD_RATIO_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_20__DFI_CMD_RATIO_SHIFT 0U
+#define LPDDR4__DENALI_CTL_20__DFI_CMD_RATIO_WIDTH 1U
+#define LPDDR4__DENALI_CTL_20__DFI_CMD_RATIO_WOCLR 0U
+#define LPDDR4__DENALI_CTL_20__DFI_CMD_RATIO_WOSET 0U
+#define LPDDR4__DFI_CMD_RATIO__REG DENALI_CTL_20
+#define LPDDR4__DFI_CMD_RATIO__FLD LPDDR4__DENALI_CTL_20__DFI_CMD_RATIO
+
+#define LPDDR4__DENALI_CTL_20__NO_MRW_INIT_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_20__NO_MRW_INIT_SHIFT 8U
+#define LPDDR4__DENALI_CTL_20__NO_MRW_INIT_WIDTH 1U
+#define LPDDR4__DENALI_CTL_20__NO_MRW_INIT_WOCLR 0U
+#define LPDDR4__DENALI_CTL_20__NO_MRW_INIT_WOSET 0U
+#define LPDDR4__NO_MRW_INIT__REG DENALI_CTL_20
+#define LPDDR4__NO_MRW_INIT__FLD LPDDR4__DENALI_CTL_20__NO_MRW_INIT
+
+#define LPDDR4__DENALI_CTL_20__ODT_VALUE_MASK 0x00030000U
+#define LPDDR4__DENALI_CTL_20__ODT_VALUE_SHIFT 16U
+#define LPDDR4__DENALI_CTL_20__ODT_VALUE_WIDTH 2U
+#define LPDDR4__ODT_VALUE__REG DENALI_CTL_20
+#define LPDDR4__ODT_VALUE__FLD LPDDR4__DENALI_CTL_20__ODT_VALUE
+
+#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_SHIFT 24U
+#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_WIDTH 1U
+#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_WOCLR 0U
+#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_WOSET 0U
+#define LPDDR4__PHY_INDEP_TRAIN_MODE__REG DENALI_CTL_20
+#define LPDDR4__PHY_INDEP_TRAIN_MODE__FLD LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE
+
+#define LPDDR4__DENALI_CTL_21_READ_MASK 0x1F1F013FU
+#define LPDDR4__DENALI_CTL_21_WRITE_MASK 0x1F1F013FU
+#define LPDDR4__DENALI_CTL_21__TSREF2PHYMSTR_MASK 0x0000003FU
+#define LPDDR4__DENALI_CTL_21__TSREF2PHYMSTR_SHIFT 0U
+#define LPDDR4__DENALI_CTL_21__TSREF2PHYMSTR_WIDTH 6U
+#define LPDDR4__TSREF2PHYMSTR__REG DENALI_CTL_21
+#define LPDDR4__TSREF2PHYMSTR__FLD LPDDR4__DENALI_CTL_21__TSREF2PHYMSTR
+
+#define LPDDR4__DENALI_CTL_21__PHY_INDEP_INIT_MODE_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_21__PHY_INDEP_INIT_MODE_SHIFT 8U
+#define LPDDR4__DENALI_CTL_21__PHY_INDEP_INIT_MODE_WIDTH 1U
+#define LPDDR4__DENALI_CTL_21__PHY_INDEP_INIT_MODE_WOCLR 0U
+#define LPDDR4__DENALI_CTL_21__PHY_INDEP_INIT_MODE_WOSET 0U
+#define LPDDR4__PHY_INDEP_INIT_MODE__REG DENALI_CTL_21
+#define LPDDR4__PHY_INDEP_INIT_MODE__FLD LPDDR4__DENALI_CTL_21__PHY_INDEP_INIT_MODE
+
+#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F0_MASK 0x001F0000U
+#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F0_WIDTH 5U
+#define LPDDR4__DFIBUS_FREQ_F0__REG DENALI_CTL_21
+#define LPDDR4__DFIBUS_FREQ_F0__FLD LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F0
+
+#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F1_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F1_WIDTH 5U
+#define LPDDR4__DFIBUS_FREQ_F1__REG DENALI_CTL_21
+#define LPDDR4__DFIBUS_FREQ_F1__FLD LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F1
+
+#define LPDDR4__DENALI_CTL_22_READ_MASK 0x0303031FU
+#define LPDDR4__DENALI_CTL_22_WRITE_MASK 0x0303031FU
+#define LPDDR4__DENALI_CTL_22__DFIBUS_FREQ_F2_MASK 0x0000001FU
+#define LPDDR4__DENALI_CTL_22__DFIBUS_FREQ_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_22__DFIBUS_FREQ_F2_WIDTH 5U
+#define LPDDR4__DFIBUS_FREQ_F2__REG DENALI_CTL_22
+#define LPDDR4__DFIBUS_FREQ_F2__FLD LPDDR4__DENALI_CTL_22__DFIBUS_FREQ_F2
+
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F0_MASK 0x00000300U
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F0_WIDTH 2U
+#define LPDDR4__FREQ_CHANGE_TYPE_F0__REG DENALI_CTL_22
+#define LPDDR4__FREQ_CHANGE_TYPE_F0__FLD LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F0
+
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F1_MASK 0x00030000U
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F1_WIDTH 2U
+#define LPDDR4__FREQ_CHANGE_TYPE_F1__REG DENALI_CTL_22
+#define LPDDR4__FREQ_CHANGE_TYPE_F1__FLD LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F1
+
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F2_MASK 0x03000000U
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F2_SHIFT 24U
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F2_WIDTH 2U
+#define LPDDR4__FREQ_CHANGE_TYPE_F2__REG DENALI_CTL_22
+#define LPDDR4__FREQ_CHANGE_TYPE_F2__FLD LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F2
+
+#define LPDDR4__DENALI_CTL_23_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_23_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_23__TRST_PWRON_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_23__TRST_PWRON_SHIFT 0U
+#define LPDDR4__DENALI_CTL_23__TRST_PWRON_WIDTH 32U
+#define LPDDR4__TRST_PWRON__REG DENALI_CTL_23
+#define LPDDR4__TRST_PWRON__FLD LPDDR4__DENALI_CTL_23__TRST_PWRON
+
+#define LPDDR4__DENALI_CTL_24_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_24_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_24__CKE_INACTIVE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_24__CKE_INACTIVE_SHIFT 0U
+#define LPDDR4__DENALI_CTL_24__CKE_INACTIVE_WIDTH 32U
+#define LPDDR4__CKE_INACTIVE__REG DENALI_CTL_24
+#define LPDDR4__CKE_INACTIVE__FLD LPDDR4__DENALI_CTL_24__CKE_INACTIVE
+
+#define LPDDR4__DENALI_CTL_25_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_25_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_25__TDLL_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_25__TDLL_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_25__TDLL_F0_WIDTH 16U
+#define LPDDR4__TDLL_F0__REG DENALI_CTL_25
+#define LPDDR4__TDLL_F0__FLD LPDDR4__DENALI_CTL_25__TDLL_F0
+
+#define LPDDR4__DENALI_CTL_25__TDLL_F1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_25__TDLL_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_25__TDLL_F1_WIDTH 16U
+#define LPDDR4__TDLL_F1__REG DENALI_CTL_25
+#define LPDDR4__TDLL_F1__FLD LPDDR4__DENALI_CTL_25__TDLL_F1
+
+#define LPDDR4__DENALI_CTL_26_READ_MASK 0x0301FFFFU
+#define LPDDR4__DENALI_CTL_26_WRITE_MASK 0x0301FFFFU
+#define LPDDR4__DENALI_CTL_26__TDLL_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_26__TDLL_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_26__TDLL_F2_WIDTH 16U
+#define LPDDR4__TDLL_F2__REG DENALI_CTL_26
+#define LPDDR4__TDLL_F2__FLD LPDDR4__DENALI_CTL_26__TDLL_F2
+
+#define LPDDR4__DENALI_CTL_26__LPC_SW_ENTER_DQS_OSC_IN_PROGRESS_ERR_STATUS_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_26__LPC_SW_ENTER_DQS_OSC_IN_PROGRESS_ERR_STATUS_SHIFT 16U
+#define LPDDR4__DENALI_CTL_26__LPC_SW_ENTER_DQS_OSC_IN_PROGRESS_ERR_STATUS_WIDTH 1U
+#define LPDDR4__DENALI_CTL_26__LPC_SW_ENTER_DQS_OSC_IN_PROGRESS_ERR_STATUS_WOCLR 0U
+#define LPDDR4__DENALI_CTL_26__LPC_SW_ENTER_DQS_OSC_IN_PROGRESS_ERR_STATUS_WOSET 0U
+#define LPDDR4__LPC_SW_ENTER_DQS_OSC_IN_PROGRESS_ERR_STATUS__REG DENALI_CTL_26
+#define LPDDR4__LPC_SW_ENTER_DQS_OSC_IN_PROGRESS_ERR_STATUS__FLD LPDDR4__DENALI_CTL_26__LPC_SW_ENTER_DQS_OSC_IN_PROGRESS_ERR_STATUS
+
+#define LPDDR4__DENALI_CTL_26__DQS_OSC_PER_CS_OOV_TRAINING_STATUS_MASK 0x03000000U
+#define LPDDR4__DENALI_CTL_26__DQS_OSC_PER_CS_OOV_TRAINING_STATUS_SHIFT 24U
+#define LPDDR4__DENALI_CTL_26__DQS_OSC_PER_CS_OOV_TRAINING_STATUS_WIDTH 2U
+#define LPDDR4__DQS_OSC_PER_CS_OOV_TRAINING_STATUS__REG DENALI_CTL_26
+#define LPDDR4__DQS_OSC_PER_CS_OOV_TRAINING_STATUS__FLD LPDDR4__DENALI_CTL_26__DQS_OSC_PER_CS_OOV_TRAINING_STATUS
+
+#define LPDDR4__DENALI_CTL_27_READ_MASK 0xFFFFFF01U
+#define LPDDR4__DENALI_CTL_27_WRITE_MASK 0xFFFFFF01U
+#define LPDDR4__DENALI_CTL_27__DQS_OSC_TST_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_27__DQS_OSC_TST_SHIFT 0U
+#define LPDDR4__DENALI_CTL_27__DQS_OSC_TST_WIDTH 1U
+#define LPDDR4__DENALI_CTL_27__DQS_OSC_TST_WOCLR 0U
+#define LPDDR4__DENALI_CTL_27__DQS_OSC_TST_WOSET 0U
+#define LPDDR4__DQS_OSC_TST__REG DENALI_CTL_27
+#define LPDDR4__DQS_OSC_TST__FLD LPDDR4__DENALI_CTL_27__DQS_OSC_TST
+
+#define LPDDR4__DENALI_CTL_27__DQS_OSC_MPC_CMD_MASK 0xFFFFFF00U
+#define LPDDR4__DENALI_CTL_27__DQS_OSC_MPC_CMD_SHIFT 8U
+#define LPDDR4__DENALI_CTL_27__DQS_OSC_MPC_CMD_WIDTH 24U
+#define LPDDR4__DQS_OSC_MPC_CMD__REG DENALI_CTL_27
+#define LPDDR4__DQS_OSC_MPC_CMD__FLD LPDDR4__DENALI_CTL_27__DQS_OSC_MPC_CMD
+
+#define LPDDR4__DENALI_CTL_28_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_28_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_28__MRR_LSB_REG_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_28__MRR_LSB_REG_SHIFT 0U
+#define LPDDR4__DENALI_CTL_28__MRR_LSB_REG_WIDTH 8U
+#define LPDDR4__MRR_LSB_REG__REG DENALI_CTL_28
+#define LPDDR4__MRR_LSB_REG__FLD LPDDR4__DENALI_CTL_28__MRR_LSB_REG
+
+#define LPDDR4__DENALI_CTL_28__MRR_MSB_REG_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_28__MRR_MSB_REG_SHIFT 8U
+#define LPDDR4__DENALI_CTL_28__MRR_MSB_REG_WIDTH 8U
+#define LPDDR4__MRR_MSB_REG__REG DENALI_CTL_28
+#define LPDDR4__MRR_MSB_REG__FLD LPDDR4__DENALI_CTL_28__MRR_MSB_REG
+
+#define LPDDR4__DENALI_CTL_28__DQS_OSC_ENABLE_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_28__DQS_OSC_ENABLE_SHIFT 16U
+#define LPDDR4__DENALI_CTL_28__DQS_OSC_ENABLE_WIDTH 1U
+#define LPDDR4__DENALI_CTL_28__DQS_OSC_ENABLE_WOCLR 0U
+#define LPDDR4__DENALI_CTL_28__DQS_OSC_ENABLE_WOSET 0U
+#define LPDDR4__DQS_OSC_ENABLE__REG DENALI_CTL_28
+#define LPDDR4__DQS_OSC_ENABLE__FLD LPDDR4__DENALI_CTL_28__DQS_OSC_ENABLE
+
+#define LPDDR4__DENALI_CTL_29_READ_MASK 0x000F7FFFU
+#define LPDDR4__DENALI_CTL_29_WRITE_MASK 0x000F7FFFU
+#define LPDDR4__DENALI_CTL_29__DQS_OSC_PERIOD_MASK 0x00007FFFU
+#define LPDDR4__DENALI_CTL_29__DQS_OSC_PERIOD_SHIFT 0U
+#define LPDDR4__DENALI_CTL_29__DQS_OSC_PERIOD_WIDTH 15U
+#define LPDDR4__DQS_OSC_PERIOD__REG DENALI_CTL_29
+#define LPDDR4__DQS_OSC_PERIOD__FLD LPDDR4__DENALI_CTL_29__DQS_OSC_PERIOD
+
+#define LPDDR4__DENALI_CTL_29__FUNC_VALID_CYCLES_MASK 0x000F0000U
+#define LPDDR4__DENALI_CTL_29__FUNC_VALID_CYCLES_SHIFT 16U
+#define LPDDR4__DENALI_CTL_29__FUNC_VALID_CYCLES_WIDTH 4U
+#define LPDDR4__FUNC_VALID_CYCLES__REG DENALI_CTL_29
+#define LPDDR4__FUNC_VALID_CYCLES__FLD LPDDR4__DENALI_CTL_29__FUNC_VALID_CYCLES
+
+#define LPDDR4__DENALI_CTL_30_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_30_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_30__DQS_OSC_NORM_THRESHOLD_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_30__DQS_OSC_NORM_THRESHOLD_SHIFT 0U
+#define LPDDR4__DENALI_CTL_30__DQS_OSC_NORM_THRESHOLD_WIDTH 32U
+#define LPDDR4__DQS_OSC_NORM_THRESHOLD__REG DENALI_CTL_30
+#define LPDDR4__DQS_OSC_NORM_THRESHOLD__FLD LPDDR4__DENALI_CTL_30__DQS_OSC_NORM_THRESHOLD
+
+#define LPDDR4__DENALI_CTL_31_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_31_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_31__DQS_OSC_HIGH_THRESHOLD_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_31__DQS_OSC_HIGH_THRESHOLD_SHIFT 0U
+#define LPDDR4__DENALI_CTL_31__DQS_OSC_HIGH_THRESHOLD_WIDTH 32U
+#define LPDDR4__DQS_OSC_HIGH_THRESHOLD__REG DENALI_CTL_31
+#define LPDDR4__DQS_OSC_HIGH_THRESHOLD__FLD LPDDR4__DENALI_CTL_31__DQS_OSC_HIGH_THRESHOLD
+
+#define LPDDR4__DENALI_CTL_32_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_32_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_32__DQS_OSC_TIMEOUT_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_32__DQS_OSC_TIMEOUT_SHIFT 0U
+#define LPDDR4__DENALI_CTL_32__DQS_OSC_TIMEOUT_WIDTH 32U
+#define LPDDR4__DQS_OSC_TIMEOUT__REG DENALI_CTL_32
+#define LPDDR4__DQS_OSC_TIMEOUT__FLD LPDDR4__DENALI_CTL_32__DQS_OSC_TIMEOUT
+
+#define LPDDR4__DENALI_CTL_33_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_33_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_33__DQS_OSC_PROMOTE_THRESHOLD_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_33__DQS_OSC_PROMOTE_THRESHOLD_SHIFT 0U
+#define LPDDR4__DENALI_CTL_33__DQS_OSC_PROMOTE_THRESHOLD_WIDTH 32U
+#define LPDDR4__DQS_OSC_PROMOTE_THRESHOLD__REG DENALI_CTL_33
+#define LPDDR4__DQS_OSC_PROMOTE_THRESHOLD__FLD LPDDR4__DENALI_CTL_33__DQS_OSC_PROMOTE_THRESHOLD
+
+#define LPDDR4__DENALI_CTL_34_READ_MASK 0xFF00FFFFU
+#define LPDDR4__DENALI_CTL_34_WRITE_MASK 0xFF00FFFFU
+#define LPDDR4__DENALI_CTL_34__OSC_VARIANCE_LIMIT_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_34__OSC_VARIANCE_LIMIT_SHIFT 0U
+#define LPDDR4__DENALI_CTL_34__OSC_VARIANCE_LIMIT_WIDTH 16U
+#define LPDDR4__OSC_VARIANCE_LIMIT__REG DENALI_CTL_34
+#define LPDDR4__OSC_VARIANCE_LIMIT__FLD LPDDR4__DENALI_CTL_34__OSC_VARIANCE_LIMIT
+
+#define LPDDR4__DENALI_CTL_34__DQS_OSC_REQUEST_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_34__DQS_OSC_REQUEST_SHIFT 16U
+#define LPDDR4__DENALI_CTL_34__DQS_OSC_REQUEST_WIDTH 1U
+#define LPDDR4__DENALI_CTL_34__DQS_OSC_REQUEST_WOCLR 0U
+#define LPDDR4__DENALI_CTL_34__DQS_OSC_REQUEST_WOSET 0U
+#define LPDDR4__DQS_OSC_REQUEST__REG DENALI_CTL_34
+#define LPDDR4__DQS_OSC_REQUEST__FLD LPDDR4__DENALI_CTL_34__DQS_OSC_REQUEST
+
+#define LPDDR4__DENALI_CTL_34__TOSCO_F0_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_34__TOSCO_F0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_34__TOSCO_F0_WIDTH 8U
+#define LPDDR4__TOSCO_F0__REG DENALI_CTL_34
+#define LPDDR4__TOSCO_F0__FLD LPDDR4__DENALI_CTL_34__TOSCO_F0
+
+#define LPDDR4__DENALI_CTL_35_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_35_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_35__TOSCO_F1_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_35__TOSCO_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_35__TOSCO_F1_WIDTH 8U
+#define LPDDR4__TOSCO_F1__REG DENALI_CTL_35
+#define LPDDR4__TOSCO_F1__FLD LPDDR4__DENALI_CTL_35__TOSCO_F1
+
+#define LPDDR4__DENALI_CTL_35__TOSCO_F2_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_35__TOSCO_F2_SHIFT 8U
+#define LPDDR4__DENALI_CTL_35__TOSCO_F2_WIDTH 8U
+#define LPDDR4__TOSCO_F2__REG DENALI_CTL_35
+#define LPDDR4__TOSCO_F2__FLD LPDDR4__DENALI_CTL_35__TOSCO_F2
+
+#define LPDDR4__DENALI_CTL_35__DQS_OSC_BASE_VALUE_0_CS0_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_35__DQS_OSC_BASE_VALUE_0_CS0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_35__DQS_OSC_BASE_VALUE_0_CS0_WIDTH 16U
+#define LPDDR4__DQS_OSC_BASE_VALUE_0_CS0__REG DENALI_CTL_35
+#define LPDDR4__DQS_OSC_BASE_VALUE_0_CS0__FLD LPDDR4__DENALI_CTL_35__DQS_OSC_BASE_VALUE_0_CS0
+
+#define LPDDR4__DENALI_CTL_36_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_36_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_36__DQS_OSC_BASE_VALUE_1_CS0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_36__DQS_OSC_BASE_VALUE_1_CS0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_36__DQS_OSC_BASE_VALUE_1_CS0_WIDTH 16U
+#define LPDDR4__DQS_OSC_BASE_VALUE_1_CS0__REG DENALI_CTL_36
+#define LPDDR4__DQS_OSC_BASE_VALUE_1_CS0__FLD LPDDR4__DENALI_CTL_36__DQS_OSC_BASE_VALUE_1_CS0
+
+#define LPDDR4__DENALI_CTL_36__DQS_OSC_BASE_VALUE_2_CS0_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_36__DQS_OSC_BASE_VALUE_2_CS0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_36__DQS_OSC_BASE_VALUE_2_CS0_WIDTH 16U
+#define LPDDR4__DQS_OSC_BASE_VALUE_2_CS0__REG DENALI_CTL_36
+#define LPDDR4__DQS_OSC_BASE_VALUE_2_CS0__FLD LPDDR4__DENALI_CTL_36__DQS_OSC_BASE_VALUE_2_CS0
+
+#define LPDDR4__DENALI_CTL_37_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_37_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_37__DQS_OSC_BASE_VALUE_3_CS0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_37__DQS_OSC_BASE_VALUE_3_CS0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_37__DQS_OSC_BASE_VALUE_3_CS0_WIDTH 16U
+#define LPDDR4__DQS_OSC_BASE_VALUE_3_CS0__REG DENALI_CTL_37
+#define LPDDR4__DQS_OSC_BASE_VALUE_3_CS0__FLD LPDDR4__DENALI_CTL_37__DQS_OSC_BASE_VALUE_3_CS0
+
+#define LPDDR4__DENALI_CTL_37__DQS_OSC_BASE_VALUE_0_CS1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_37__DQS_OSC_BASE_VALUE_0_CS1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_37__DQS_OSC_BASE_VALUE_0_CS1_WIDTH 16U
+#define LPDDR4__DQS_OSC_BASE_VALUE_0_CS1__REG DENALI_CTL_37
+#define LPDDR4__DQS_OSC_BASE_VALUE_0_CS1__FLD LPDDR4__DENALI_CTL_37__DQS_OSC_BASE_VALUE_0_CS1
+
+#define LPDDR4__DENALI_CTL_38_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_38_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_38__DQS_OSC_BASE_VALUE_1_CS1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_38__DQS_OSC_BASE_VALUE_1_CS1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_38__DQS_OSC_BASE_VALUE_1_CS1_WIDTH 16U
+#define LPDDR4__DQS_OSC_BASE_VALUE_1_CS1__REG DENALI_CTL_38
+#define LPDDR4__DQS_OSC_BASE_VALUE_1_CS1__FLD LPDDR4__DENALI_CTL_38__DQS_OSC_BASE_VALUE_1_CS1
+
+#define LPDDR4__DENALI_CTL_38__DQS_OSC_BASE_VALUE_2_CS1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_38__DQS_OSC_BASE_VALUE_2_CS1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_38__DQS_OSC_BASE_VALUE_2_CS1_WIDTH 16U
+#define LPDDR4__DQS_OSC_BASE_VALUE_2_CS1__REG DENALI_CTL_38
+#define LPDDR4__DQS_OSC_BASE_VALUE_2_CS1__FLD LPDDR4__DENALI_CTL_38__DQS_OSC_BASE_VALUE_2_CS1
+
+#define LPDDR4__DENALI_CTL_39_READ_MASK 0x010FFFFFU
+#define LPDDR4__DENALI_CTL_39_WRITE_MASK 0x010FFFFFU
+#define LPDDR4__DENALI_CTL_39__DQS_OSC_BASE_VALUE_3_CS1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_39__DQS_OSC_BASE_VALUE_3_CS1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_39__DQS_OSC_BASE_VALUE_3_CS1_WIDTH 16U
+#define LPDDR4__DQS_OSC_BASE_VALUE_3_CS1__REG DENALI_CTL_39
+#define LPDDR4__DQS_OSC_BASE_VALUE_3_CS1__FLD LPDDR4__DENALI_CTL_39__DQS_OSC_BASE_VALUE_3_CS1
+
+#define LPDDR4__DENALI_CTL_39__DQS_OSC_STATUS_MASK 0x000F0000U
+#define LPDDR4__DENALI_CTL_39__DQS_OSC_STATUS_SHIFT 16U
+#define LPDDR4__DENALI_CTL_39__DQS_OSC_STATUS_WIDTH 4U
+#define LPDDR4__DQS_OSC_STATUS__REG DENALI_CTL_39
+#define LPDDR4__DQS_OSC_STATUS__FLD LPDDR4__DENALI_CTL_39__DQS_OSC_STATUS
+
+#define LPDDR4__DENALI_CTL_39__DQS_OSC_IN_PROGRESS_STATUS_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_39__DQS_OSC_IN_PROGRESS_STATUS_SHIFT 24U
+#define LPDDR4__DENALI_CTL_39__DQS_OSC_IN_PROGRESS_STATUS_WIDTH 1U
+#define LPDDR4__DENALI_CTL_39__DQS_OSC_IN_PROGRESS_STATUS_WOCLR 0U
+#define LPDDR4__DENALI_CTL_39__DQS_OSC_IN_PROGRESS_STATUS_WOSET 0U
+#define LPDDR4__DQS_OSC_IN_PROGRESS_STATUS__REG DENALI_CTL_39
+#define LPDDR4__DQS_OSC_IN_PROGRESS_STATUS__FLD LPDDR4__DENALI_CTL_39__DQS_OSC_IN_PROGRESS_STATUS
+
+#define LPDDR4__DENALI_CTL_40_READ_MASK 0x0F3F7F7FU
+#define LPDDR4__DENALI_CTL_40_WRITE_MASK 0x0F3F7F7FU
+#define LPDDR4__DENALI_CTL_40__CASLAT_LIN_F0_MASK 0x0000007FU
+#define LPDDR4__DENALI_CTL_40__CASLAT_LIN_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_40__CASLAT_LIN_F0_WIDTH 7U
+#define LPDDR4__CASLAT_LIN_F0__REG DENALI_CTL_40
+#define LPDDR4__CASLAT_LIN_F0__FLD LPDDR4__DENALI_CTL_40__CASLAT_LIN_F0
+
+#define LPDDR4__DENALI_CTL_40__WRLAT_F0_MASK 0x00007F00U
+#define LPDDR4__DENALI_CTL_40__WRLAT_F0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_40__WRLAT_F0_WIDTH 7U
+#define LPDDR4__WRLAT_F0__REG DENALI_CTL_40
+#define LPDDR4__WRLAT_F0__FLD LPDDR4__DENALI_CTL_40__WRLAT_F0
+
+#define LPDDR4__DENALI_CTL_40__ADDITIVE_LAT_F0_MASK 0x003F0000U
+#define LPDDR4__DENALI_CTL_40__ADDITIVE_LAT_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_40__ADDITIVE_LAT_F0_WIDTH 6U
+#define LPDDR4__ADDITIVE_LAT_F0__REG DENALI_CTL_40
+#define LPDDR4__ADDITIVE_LAT_F0__FLD LPDDR4__DENALI_CTL_40__ADDITIVE_LAT_F0
+
+#define LPDDR4__DENALI_CTL_40__CA_PARITY_LAT_F0_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_40__CA_PARITY_LAT_F0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_40__CA_PARITY_LAT_F0_WIDTH 4U
+#define LPDDR4__CA_PARITY_LAT_F0__REG DENALI_CTL_40
+#define LPDDR4__CA_PARITY_LAT_F0__FLD LPDDR4__DENALI_CTL_40__CA_PARITY_LAT_F0
+
+#define LPDDR4__DENALI_CTL_41_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_41_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_41__TMOD_PAR_F0_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_41__TMOD_PAR_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_41__TMOD_PAR_F0_WIDTH 8U
+#define LPDDR4__TMOD_PAR_F0__REG DENALI_CTL_41
+#define LPDDR4__TMOD_PAR_F0__FLD LPDDR4__DENALI_CTL_41__TMOD_PAR_F0
+
+#define LPDDR4__DENALI_CTL_41__TMRD_PAR_F0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_41__TMRD_PAR_F0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_41__TMRD_PAR_F0_WIDTH 8U
+#define LPDDR4__TMRD_PAR_F0__REG DENALI_CTL_41
+#define LPDDR4__TMRD_PAR_F0__FLD LPDDR4__DENALI_CTL_41__TMRD_PAR_F0
+
+#define LPDDR4__DENALI_CTL_41__TMOD_PAR_MAX_PL_F0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_41__TMOD_PAR_MAX_PL_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_41__TMOD_PAR_MAX_PL_F0_WIDTH 8U
+#define LPDDR4__TMOD_PAR_MAX_PL_F0__REG DENALI_CTL_41
+#define LPDDR4__TMOD_PAR_MAX_PL_F0__FLD LPDDR4__DENALI_CTL_41__TMOD_PAR_MAX_PL_F0
+
+#define LPDDR4__DENALI_CTL_41__TMRD_PAR_MAX_PL_F0_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_41__TMRD_PAR_MAX_PL_F0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_41__TMRD_PAR_MAX_PL_F0_WIDTH 8U
+#define LPDDR4__TMRD_PAR_MAX_PL_F0__REG DENALI_CTL_41
+#define LPDDR4__TMRD_PAR_MAX_PL_F0__FLD LPDDR4__DENALI_CTL_41__TMRD_PAR_MAX_PL_F0
+
+#define LPDDR4__DENALI_CTL_42_READ_MASK 0x0F3F7F7FU
+#define LPDDR4__DENALI_CTL_42_WRITE_MASK 0x0F3F7F7FU
+#define LPDDR4__DENALI_CTL_42__CASLAT_LIN_F1_MASK 0x0000007FU
+#define LPDDR4__DENALI_CTL_42__CASLAT_LIN_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_42__CASLAT_LIN_F1_WIDTH 7U
+#define LPDDR4__CASLAT_LIN_F1__REG DENALI_CTL_42
+#define LPDDR4__CASLAT_LIN_F1__FLD LPDDR4__DENALI_CTL_42__CASLAT_LIN_F1
+
+#define LPDDR4__DENALI_CTL_42__WRLAT_F1_MASK 0x00007F00U
+#define LPDDR4__DENALI_CTL_42__WRLAT_F1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_42__WRLAT_F1_WIDTH 7U
+#define LPDDR4__WRLAT_F1__REG DENALI_CTL_42
+#define LPDDR4__WRLAT_F1__FLD LPDDR4__DENALI_CTL_42__WRLAT_F1
+
+#define LPDDR4__DENALI_CTL_42__ADDITIVE_LAT_F1_MASK 0x003F0000U
+#define LPDDR4__DENALI_CTL_42__ADDITIVE_LAT_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_42__ADDITIVE_LAT_F1_WIDTH 6U
+#define LPDDR4__ADDITIVE_LAT_F1__REG DENALI_CTL_42
+#define LPDDR4__ADDITIVE_LAT_F1__FLD LPDDR4__DENALI_CTL_42__ADDITIVE_LAT_F1
+
+#define LPDDR4__DENALI_CTL_42__CA_PARITY_LAT_F1_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_42__CA_PARITY_LAT_F1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_42__CA_PARITY_LAT_F1_WIDTH 4U
+#define LPDDR4__CA_PARITY_LAT_F1__REG DENALI_CTL_42
+#define LPDDR4__CA_PARITY_LAT_F1__FLD LPDDR4__DENALI_CTL_42__CA_PARITY_LAT_F1
+
+#define LPDDR4__DENALI_CTL_43_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_43_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_43__TMOD_PAR_F1_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_43__TMOD_PAR_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_43__TMOD_PAR_F1_WIDTH 8U
+#define LPDDR4__TMOD_PAR_F1__REG DENALI_CTL_43
+#define LPDDR4__TMOD_PAR_F1__FLD LPDDR4__DENALI_CTL_43__TMOD_PAR_F1
+
+#define LPDDR4__DENALI_CTL_43__TMRD_PAR_F1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_43__TMRD_PAR_F1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_43__TMRD_PAR_F1_WIDTH 8U
+#define LPDDR4__TMRD_PAR_F1__REG DENALI_CTL_43
+#define LPDDR4__TMRD_PAR_F1__FLD LPDDR4__DENALI_CTL_43__TMRD_PAR_F1
+
+#define LPDDR4__DENALI_CTL_43__TMOD_PAR_MAX_PL_F1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_43__TMOD_PAR_MAX_PL_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_43__TMOD_PAR_MAX_PL_F1_WIDTH 8U
+#define LPDDR4__TMOD_PAR_MAX_PL_F1__REG DENALI_CTL_43
+#define LPDDR4__TMOD_PAR_MAX_PL_F1__FLD LPDDR4__DENALI_CTL_43__TMOD_PAR_MAX_PL_F1
+
+#define LPDDR4__DENALI_CTL_43__TMRD_PAR_MAX_PL_F1_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_43__TMRD_PAR_MAX_PL_F1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_43__TMRD_PAR_MAX_PL_F1_WIDTH 8U
+#define LPDDR4__TMRD_PAR_MAX_PL_F1__REG DENALI_CTL_43
+#define LPDDR4__TMRD_PAR_MAX_PL_F1__FLD LPDDR4__DENALI_CTL_43__TMRD_PAR_MAX_PL_F1
+
+#define LPDDR4__DENALI_CTL_44_READ_MASK 0x0F3F7F7FU
+#define LPDDR4__DENALI_CTL_44_WRITE_MASK 0x0F3F7F7FU
+#define LPDDR4__DENALI_CTL_44__CASLAT_LIN_F2_MASK 0x0000007FU
+#define LPDDR4__DENALI_CTL_44__CASLAT_LIN_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_44__CASLAT_LIN_F2_WIDTH 7U
+#define LPDDR4__CASLAT_LIN_F2__REG DENALI_CTL_44
+#define LPDDR4__CASLAT_LIN_F2__FLD LPDDR4__DENALI_CTL_44__CASLAT_LIN_F2
+
+#define LPDDR4__DENALI_CTL_44__WRLAT_F2_MASK 0x00007F00U
+#define LPDDR4__DENALI_CTL_44__WRLAT_F2_SHIFT 8U
+#define LPDDR4__DENALI_CTL_44__WRLAT_F2_WIDTH 7U
+#define LPDDR4__WRLAT_F2__REG DENALI_CTL_44
+#define LPDDR4__WRLAT_F2__FLD LPDDR4__DENALI_CTL_44__WRLAT_F2
+
+#define LPDDR4__DENALI_CTL_44__ADDITIVE_LAT_F2_MASK 0x003F0000U
+#define LPDDR4__DENALI_CTL_44__ADDITIVE_LAT_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_44__ADDITIVE_LAT_F2_WIDTH 6U
+#define LPDDR4__ADDITIVE_LAT_F2__REG DENALI_CTL_44
+#define LPDDR4__ADDITIVE_LAT_F2__FLD LPDDR4__DENALI_CTL_44__ADDITIVE_LAT_F2
+
+#define LPDDR4__DENALI_CTL_44__CA_PARITY_LAT_F2_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_44__CA_PARITY_LAT_F2_SHIFT 24U
+#define LPDDR4__DENALI_CTL_44__CA_PARITY_LAT_F2_WIDTH 4U
+#define LPDDR4__CA_PARITY_LAT_F2__REG DENALI_CTL_44
+#define LPDDR4__CA_PARITY_LAT_F2__FLD LPDDR4__DENALI_CTL_44__CA_PARITY_LAT_F2
+
+#define LPDDR4__DENALI_CTL_45_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_45_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_45__TMOD_PAR_F2_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_45__TMOD_PAR_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_45__TMOD_PAR_F2_WIDTH 8U
+#define LPDDR4__TMOD_PAR_F2__REG DENALI_CTL_45
+#define LPDDR4__TMOD_PAR_F2__FLD LPDDR4__DENALI_CTL_45__TMOD_PAR_F2
+
+#define LPDDR4__DENALI_CTL_45__TMRD_PAR_F2_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_45__TMRD_PAR_F2_SHIFT 8U
+#define LPDDR4__DENALI_CTL_45__TMRD_PAR_F2_WIDTH 8U
+#define LPDDR4__TMRD_PAR_F2__REG DENALI_CTL_45
+#define LPDDR4__TMRD_PAR_F2__FLD LPDDR4__DENALI_CTL_45__TMRD_PAR_F2
+
+#define LPDDR4__DENALI_CTL_45__TMOD_PAR_MAX_PL_F2_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_45__TMOD_PAR_MAX_PL_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_45__TMOD_PAR_MAX_PL_F2_WIDTH 8U
+#define LPDDR4__TMOD_PAR_MAX_PL_F2__REG DENALI_CTL_45
+#define LPDDR4__TMOD_PAR_MAX_PL_F2__FLD LPDDR4__DENALI_CTL_45__TMOD_PAR_MAX_PL_F2
+
+#define LPDDR4__DENALI_CTL_45__TMRD_PAR_MAX_PL_F2_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_45__TMRD_PAR_MAX_PL_F2_SHIFT 24U
+#define LPDDR4__DENALI_CTL_45__TMRD_PAR_MAX_PL_F2_WIDTH 8U
+#define LPDDR4__TMRD_PAR_MAX_PL_F2__REG DENALI_CTL_45
+#define LPDDR4__TMRD_PAR_MAX_PL_F2__FLD LPDDR4__DENALI_CTL_45__TMRD_PAR_MAX_PL_F2
+
+#define LPDDR4__DENALI_CTL_46_READ_MASK 0xFF1F1F07U
+#define LPDDR4__DENALI_CTL_46_WRITE_MASK 0xFF1F1F07U
+#define LPDDR4__DENALI_CTL_46__TBST_INT_INTERVAL_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_46__TBST_INT_INTERVAL_SHIFT 0U
+#define LPDDR4__DENALI_CTL_46__TBST_INT_INTERVAL_WIDTH 3U
+#define LPDDR4__TBST_INT_INTERVAL__REG DENALI_CTL_46
+#define LPDDR4__TBST_INT_INTERVAL__FLD LPDDR4__DENALI_CTL_46__TBST_INT_INTERVAL
+
+#define LPDDR4__DENALI_CTL_46__TCCD_MASK 0x00001F00U
+#define LPDDR4__DENALI_CTL_46__TCCD_SHIFT 8U
+#define LPDDR4__DENALI_CTL_46__TCCD_WIDTH 5U
+#define LPDDR4__TCCD__REG DENALI_CTL_46
+#define LPDDR4__TCCD__FLD LPDDR4__DENALI_CTL_46__TCCD
+
+#define LPDDR4__DENALI_CTL_46__TCCD_L_F0_MASK 0x001F0000U
+#define LPDDR4__DENALI_CTL_46__TCCD_L_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_46__TCCD_L_F0_WIDTH 5U
+#define LPDDR4__TCCD_L_F0__REG DENALI_CTL_46
+#define LPDDR4__TCCD_L_F0__FLD LPDDR4__DENALI_CTL_46__TCCD_L_F0
+
+#define LPDDR4__DENALI_CTL_46__TRRD_F0_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_46__TRRD_F0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_46__TRRD_F0_WIDTH 8U
+#define LPDDR4__TRRD_F0__REG DENALI_CTL_46
+#define LPDDR4__TRRD_F0__FLD LPDDR4__DENALI_CTL_46__TRRD_F0
+
+#define LPDDR4__DENALI_CTL_47_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_47_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_47__TRRD_L_F0_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_47__TRRD_L_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_47__TRRD_L_F0_WIDTH 8U
+#define LPDDR4__TRRD_L_F0__REG DENALI_CTL_47
+#define LPDDR4__TRRD_L_F0__FLD LPDDR4__DENALI_CTL_47__TRRD_L_F0
+
+#define LPDDR4__DENALI_CTL_47__TRC_F0_MASK 0x0001FF00U
+#define LPDDR4__DENALI_CTL_47__TRC_F0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_47__TRC_F0_WIDTH 9U
+#define LPDDR4__TRC_F0__REG DENALI_CTL_47
+#define LPDDR4__TRC_F0__FLD LPDDR4__DENALI_CTL_47__TRC_F0
+
+#define LPDDR4__DENALI_CTL_48_READ_MASK 0x3F3F01FFU
+#define LPDDR4__DENALI_CTL_48_WRITE_MASK 0x3F3F01FFU
+#define LPDDR4__DENALI_CTL_48__TRAS_MIN_F0_MASK 0x000001FFU
+#define LPDDR4__DENALI_CTL_48__TRAS_MIN_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_48__TRAS_MIN_F0_WIDTH 9U
+#define LPDDR4__TRAS_MIN_F0__REG DENALI_CTL_48
+#define LPDDR4__TRAS_MIN_F0__FLD LPDDR4__DENALI_CTL_48__TRAS_MIN_F0
+
+#define LPDDR4__DENALI_CTL_48__TWTR_F0_MASK 0x003F0000U
+#define LPDDR4__DENALI_CTL_48__TWTR_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_48__TWTR_F0_WIDTH 6U
+#define LPDDR4__TWTR_F0__REG DENALI_CTL_48
+#define LPDDR4__TWTR_F0__FLD LPDDR4__DENALI_CTL_48__TWTR_F0
+
+#define LPDDR4__DENALI_CTL_48__TWTR_L_F0_MASK 0x3F000000U
+#define LPDDR4__DENALI_CTL_48__TWTR_L_F0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_48__TWTR_L_F0_WIDTH 6U
+#define LPDDR4__TWTR_L_F0__REG DENALI_CTL_48
+#define LPDDR4__TWTR_L_F0__FLD LPDDR4__DENALI_CTL_48__TWTR_L_F0
+
+#define LPDDR4__DENALI_CTL_49_READ_MASK 0x1F01FFFFU
+#define LPDDR4__DENALI_CTL_49_WRITE_MASK 0x1F01FFFFU
+#define LPDDR4__DENALI_CTL_49__TRP_F0_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_49__TRP_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_49__TRP_F0_WIDTH 8U
+#define LPDDR4__TRP_F0__REG DENALI_CTL_49
+#define LPDDR4__TRP_F0__FLD LPDDR4__DENALI_CTL_49__TRP_F0
+
+#define LPDDR4__DENALI_CTL_49__TFAW_F0_MASK 0x0001FF00U
+#define LPDDR4__DENALI_CTL_49__TFAW_F0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_49__TFAW_F0_WIDTH 9U
+#define LPDDR4__TFAW_F0__REG DENALI_CTL_49
+#define LPDDR4__TFAW_F0__FLD LPDDR4__DENALI_CTL_49__TFAW_F0
+
+#define LPDDR4__DENALI_CTL_49__TCCD_L_F1_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_49__TCCD_L_F1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_49__TCCD_L_F1_WIDTH 5U
+#define LPDDR4__TCCD_L_F1__REG DENALI_CTL_49
+#define LPDDR4__TCCD_L_F1__FLD LPDDR4__DENALI_CTL_49__TCCD_L_F1
+
+#define LPDDR4__DENALI_CTL_50_READ_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_50_WRITE_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_50__TRRD_F1_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_50__TRRD_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_50__TRRD_F1_WIDTH 8U
+#define LPDDR4__TRRD_F1__REG DENALI_CTL_50
+#define LPDDR4__TRRD_F1__FLD LPDDR4__DENALI_CTL_50__TRRD_F1
+
+#define LPDDR4__DENALI_CTL_50__TRRD_L_F1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_50__TRRD_L_F1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_50__TRRD_L_F1_WIDTH 8U
+#define LPDDR4__TRRD_L_F1__REG DENALI_CTL_50
+#define LPDDR4__TRRD_L_F1__FLD LPDDR4__DENALI_CTL_50__TRRD_L_F1
+
+#define LPDDR4__DENALI_CTL_50__TRC_F1_MASK 0x01FF0000U
+#define LPDDR4__DENALI_CTL_50__TRC_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_50__TRC_F1_WIDTH 9U
+#define LPDDR4__TRC_F1__REG DENALI_CTL_50
+#define LPDDR4__TRC_F1__FLD LPDDR4__DENALI_CTL_50__TRC_F1
+
+#define LPDDR4__DENALI_CTL_51_READ_MASK 0x3F3F01FFU
+#define LPDDR4__DENALI_CTL_51_WRITE_MASK 0x3F3F01FFU
+#define LPDDR4__DENALI_CTL_51__TRAS_MIN_F1_MASK 0x000001FFU
+#define LPDDR4__DENALI_CTL_51__TRAS_MIN_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_51__TRAS_MIN_F1_WIDTH 9U
+#define LPDDR4__TRAS_MIN_F1__REG DENALI_CTL_51
+#define LPDDR4__TRAS_MIN_F1__FLD LPDDR4__DENALI_CTL_51__TRAS_MIN_F1
+
+#define LPDDR4__DENALI_CTL_51__TWTR_F1_MASK 0x003F0000U
+#define LPDDR4__DENALI_CTL_51__TWTR_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_51__TWTR_F1_WIDTH 6U
+#define LPDDR4__TWTR_F1__REG DENALI_CTL_51
+#define LPDDR4__TWTR_F1__FLD LPDDR4__DENALI_CTL_51__TWTR_F1
+
+#define LPDDR4__DENALI_CTL_51__TWTR_L_F1_MASK 0x3F000000U
+#define LPDDR4__DENALI_CTL_51__TWTR_L_F1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_51__TWTR_L_F1_WIDTH 6U
+#define LPDDR4__TWTR_L_F1__REG DENALI_CTL_51
+#define LPDDR4__TWTR_L_F1__FLD LPDDR4__DENALI_CTL_51__TWTR_L_F1
+
+#define LPDDR4__DENALI_CTL_52_READ_MASK 0x1F01FFFFU
+#define LPDDR4__DENALI_CTL_52_WRITE_MASK 0x1F01FFFFU
+#define LPDDR4__DENALI_CTL_52__TRP_F1_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_52__TRP_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_52__TRP_F1_WIDTH 8U
+#define LPDDR4__TRP_F1__REG DENALI_CTL_52
+#define LPDDR4__TRP_F1__FLD LPDDR4__DENALI_CTL_52__TRP_F1
+
+#define LPDDR4__DENALI_CTL_52__TFAW_F1_MASK 0x0001FF00U
+#define LPDDR4__DENALI_CTL_52__TFAW_F1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_52__TFAW_F1_WIDTH 9U
+#define LPDDR4__TFAW_F1__REG DENALI_CTL_52
+#define LPDDR4__TFAW_F1__FLD LPDDR4__DENALI_CTL_52__TFAW_F1
+
+#define LPDDR4__DENALI_CTL_52__TCCD_L_F2_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_52__TCCD_L_F2_SHIFT 24U
+#define LPDDR4__DENALI_CTL_52__TCCD_L_F2_WIDTH 5U
+#define LPDDR4__TCCD_L_F2__REG DENALI_CTL_52
+#define LPDDR4__TCCD_L_F2__FLD LPDDR4__DENALI_CTL_52__TCCD_L_F2
+
+#define LPDDR4__DENALI_CTL_53_READ_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_53_WRITE_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_53__TRRD_F2_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_53__TRRD_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_53__TRRD_F2_WIDTH 8U
+#define LPDDR4__TRRD_F2__REG DENALI_CTL_53
+#define LPDDR4__TRRD_F2__FLD LPDDR4__DENALI_CTL_53__TRRD_F2
+
+#define LPDDR4__DENALI_CTL_53__TRRD_L_F2_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_53__TRRD_L_F2_SHIFT 8U
+#define LPDDR4__DENALI_CTL_53__TRRD_L_F2_WIDTH 8U
+#define LPDDR4__TRRD_L_F2__REG DENALI_CTL_53
+#define LPDDR4__TRRD_L_F2__FLD LPDDR4__DENALI_CTL_53__TRRD_L_F2
+
+#define LPDDR4__DENALI_CTL_53__TRC_F2_MASK 0x01FF0000U
+#define LPDDR4__DENALI_CTL_53__TRC_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_53__TRC_F2_WIDTH 9U
+#define LPDDR4__TRC_F2__REG DENALI_CTL_53
+#define LPDDR4__TRC_F2__FLD LPDDR4__DENALI_CTL_53__TRC_F2
+
+#define LPDDR4__DENALI_CTL_54_READ_MASK 0x3F3F01FFU
+#define LPDDR4__DENALI_CTL_54_WRITE_MASK 0x3F3F01FFU
+#define LPDDR4__DENALI_CTL_54__TRAS_MIN_F2_MASK 0x000001FFU
+#define LPDDR4__DENALI_CTL_54__TRAS_MIN_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_54__TRAS_MIN_F2_WIDTH 9U
+#define LPDDR4__TRAS_MIN_F2__REG DENALI_CTL_54
+#define LPDDR4__TRAS_MIN_F2__FLD LPDDR4__DENALI_CTL_54__TRAS_MIN_F2
+
+#define LPDDR4__DENALI_CTL_54__TWTR_F2_MASK 0x003F0000U
+#define LPDDR4__DENALI_CTL_54__TWTR_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_54__TWTR_F2_WIDTH 6U
+#define LPDDR4__TWTR_F2__REG DENALI_CTL_54
+#define LPDDR4__TWTR_F2__FLD LPDDR4__DENALI_CTL_54__TWTR_F2
+
+#define LPDDR4__DENALI_CTL_54__TWTR_L_F2_MASK 0x3F000000U
+#define LPDDR4__DENALI_CTL_54__TWTR_L_F2_SHIFT 24U
+#define LPDDR4__DENALI_CTL_54__TWTR_L_F2_WIDTH 6U
+#define LPDDR4__TWTR_L_F2__REG DENALI_CTL_54
+#define LPDDR4__TWTR_L_F2__FLD LPDDR4__DENALI_CTL_54__TWTR_L_F2
+
+#define LPDDR4__DENALI_CTL_55_READ_MASK 0xFF01FFFFU
+#define LPDDR4__DENALI_CTL_55_WRITE_MASK 0xFF01FFFFU
+#define LPDDR4__DENALI_CTL_55__TRP_F2_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_55__TRP_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_55__TRP_F2_WIDTH 8U
+#define LPDDR4__TRP_F2__REG DENALI_CTL_55
+#define LPDDR4__TRP_F2__FLD LPDDR4__DENALI_CTL_55__TRP_F2
+
+#define LPDDR4__DENALI_CTL_55__TFAW_F2_MASK 0x0001FF00U
+#define LPDDR4__DENALI_CTL_55__TFAW_F2_SHIFT 8U
+#define LPDDR4__DENALI_CTL_55__TFAW_F2_WIDTH 9U
+#define LPDDR4__TFAW_F2__REG DENALI_CTL_55
+#define LPDDR4__TFAW_F2__FLD LPDDR4__DENALI_CTL_55__TFAW_F2
+
+#define LPDDR4__DENALI_CTL_55__TRTP_F0_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_55__TRTP_F0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_55__TRTP_F0_WIDTH 8U
+#define LPDDR4__TRTP_F0__REG DENALI_CTL_55
+#define LPDDR4__TRTP_F0__FLD LPDDR4__DENALI_CTL_55__TRTP_F0
+
+#define LPDDR4__DENALI_CTL_56_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_56_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_56__TRTP_AP_F0_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_56__TRTP_AP_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_56__TRTP_AP_F0_WIDTH 8U
+#define LPDDR4__TRTP_AP_F0__REG DENALI_CTL_56
+#define LPDDR4__TRTP_AP_F0__FLD LPDDR4__DENALI_CTL_56__TRTP_AP_F0
+
+#define LPDDR4__DENALI_CTL_56__TMRD_F0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_56__TMRD_F0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_56__TMRD_F0_WIDTH 8U
+#define LPDDR4__TMRD_F0__REG DENALI_CTL_56
+#define LPDDR4__TMRD_F0__FLD LPDDR4__DENALI_CTL_56__TMRD_F0
+
+#define LPDDR4__DENALI_CTL_56__TMOD_F0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_56__TMOD_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_56__TMOD_F0_WIDTH 8U
+#define LPDDR4__TMOD_F0__REG DENALI_CTL_56
+#define LPDDR4__TMOD_F0__FLD LPDDR4__DENALI_CTL_56__TMOD_F0
+
+#define LPDDR4__DENALI_CTL_57_READ_MASK 0x1F0FFFFFU
+#define LPDDR4__DENALI_CTL_57_WRITE_MASK 0x1F0FFFFFU
+#define LPDDR4__DENALI_CTL_57__TRAS_MAX_F0_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_57__TRAS_MAX_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_57__TRAS_MAX_F0_WIDTH 20U
+#define LPDDR4__TRAS_MAX_F0__REG DENALI_CTL_57
+#define LPDDR4__TRAS_MAX_F0__FLD LPDDR4__DENALI_CTL_57__TRAS_MAX_F0
+
+#define LPDDR4__DENALI_CTL_57__TCKE_F0_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_57__TCKE_F0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_57__TCKE_F0_WIDTH 5U
+#define LPDDR4__TCKE_F0__REG DENALI_CTL_57
+#define LPDDR4__TCKE_F0__FLD LPDDR4__DENALI_CTL_57__TCKE_F0
+
+#define LPDDR4__DENALI_CTL_58_READ_MASK 0xFFFF3FFFU
+#define LPDDR4__DENALI_CTL_58_WRITE_MASK 0xFFFF3FFFU
+#define LPDDR4__DENALI_CTL_58__TCKESR_F0_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_58__TCKESR_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_58__TCKESR_F0_WIDTH 8U
+#define LPDDR4__TCKESR_F0__REG DENALI_CTL_58
+#define LPDDR4__TCKESR_F0__FLD LPDDR4__DENALI_CTL_58__TCKESR_F0
+
+#define LPDDR4__DENALI_CTL_58__TCCDMW_F0_MASK 0x00003F00U
+#define LPDDR4__DENALI_CTL_58__TCCDMW_F0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_58__TCCDMW_F0_WIDTH 6U
+#define LPDDR4__TCCDMW_F0__REG DENALI_CTL_58
+#define LPDDR4__TCCDMW_F0__FLD LPDDR4__DENALI_CTL_58__TCCDMW_F0
+
+#define LPDDR4__DENALI_CTL_58__TRTP_F1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_58__TRTP_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_58__TRTP_F1_WIDTH 8U
+#define LPDDR4__TRTP_F1__REG DENALI_CTL_58
+#define LPDDR4__TRTP_F1__FLD LPDDR4__DENALI_CTL_58__TRTP_F1
+
+#define LPDDR4__DENALI_CTL_58__TRTP_AP_F1_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_58__TRTP_AP_F1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_58__TRTP_AP_F1_WIDTH 8U
+#define LPDDR4__TRTP_AP_F1__REG DENALI_CTL_58
+#define LPDDR4__TRTP_AP_F1__FLD LPDDR4__DENALI_CTL_58__TRTP_AP_F1
+
+#define LPDDR4__DENALI_CTL_59_READ_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_59_WRITE_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_59__TMRD_F1_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_59__TMRD_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_59__TMRD_F1_WIDTH 8U
+#define LPDDR4__TMRD_F1__REG DENALI_CTL_59
+#define LPDDR4__TMRD_F1__FLD LPDDR4__DENALI_CTL_59__TMRD_F1
+
+#define LPDDR4__DENALI_CTL_59__TMOD_F1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_59__TMOD_F1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_59__TMOD_F1_WIDTH 8U
+#define LPDDR4__TMOD_F1__REG DENALI_CTL_59
+#define LPDDR4__TMOD_F1__FLD LPDDR4__DENALI_CTL_59__TMOD_F1
+
+#define LPDDR4__DENALI_CTL_60_READ_MASK 0x1F0FFFFFU
+#define LPDDR4__DENALI_CTL_60_WRITE_MASK 0x1F0FFFFFU
+#define LPDDR4__DENALI_CTL_60__TRAS_MAX_F1_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_60__TRAS_MAX_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_60__TRAS_MAX_F1_WIDTH 20U
+#define LPDDR4__TRAS_MAX_F1__REG DENALI_CTL_60
+#define LPDDR4__TRAS_MAX_F1__FLD LPDDR4__DENALI_CTL_60__TRAS_MAX_F1
+
+#define LPDDR4__DENALI_CTL_60__TCKE_F1_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_60__TCKE_F1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_60__TCKE_F1_WIDTH 5U
+#define LPDDR4__TCKE_F1__REG DENALI_CTL_60
+#define LPDDR4__TCKE_F1__FLD LPDDR4__DENALI_CTL_60__TCKE_F1
+
+#define LPDDR4__DENALI_CTL_61_READ_MASK 0xFFFF3FFFU
+#define LPDDR4__DENALI_CTL_61_WRITE_MASK 0xFFFF3FFFU
+#define LPDDR4__DENALI_CTL_61__TCKESR_F1_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_61__TCKESR_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_61__TCKESR_F1_WIDTH 8U
+#define LPDDR4__TCKESR_F1__REG DENALI_CTL_61
+#define LPDDR4__TCKESR_F1__FLD LPDDR4__DENALI_CTL_61__TCKESR_F1
+
+#define LPDDR4__DENALI_CTL_61__TCCDMW_F1_MASK 0x00003F00U
+#define LPDDR4__DENALI_CTL_61__TCCDMW_F1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_61__TCCDMW_F1_WIDTH 6U
+#define LPDDR4__TCCDMW_F1__REG DENALI_CTL_61
+#define LPDDR4__TCCDMW_F1__FLD LPDDR4__DENALI_CTL_61__TCCDMW_F1
+
+#define LPDDR4__DENALI_CTL_61__TRTP_F2_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_61__TRTP_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_61__TRTP_F2_WIDTH 8U
+#define LPDDR4__TRTP_F2__REG DENALI_CTL_61
+#define LPDDR4__TRTP_F2__FLD LPDDR4__DENALI_CTL_61__TRTP_F2
+
+#define LPDDR4__DENALI_CTL_61__TRTP_AP_F2_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_61__TRTP_AP_F2_SHIFT 24U
+#define LPDDR4__DENALI_CTL_61__TRTP_AP_F2_WIDTH 8U
+#define LPDDR4__TRTP_AP_F2__REG DENALI_CTL_61
+#define LPDDR4__TRTP_AP_F2__FLD LPDDR4__DENALI_CTL_61__TRTP_AP_F2
+
+#define LPDDR4__DENALI_CTL_62_READ_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_62_WRITE_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_62__TMRD_F2_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_62__TMRD_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_62__TMRD_F2_WIDTH 8U
+#define LPDDR4__TMRD_F2__REG DENALI_CTL_62
+#define LPDDR4__TMRD_F2__FLD LPDDR4__DENALI_CTL_62__TMRD_F2
+
+#define LPDDR4__DENALI_CTL_62__TMOD_F2_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_62__TMOD_F2_SHIFT 8U
+#define LPDDR4__DENALI_CTL_62__TMOD_F2_WIDTH 8U
+#define LPDDR4__TMOD_F2__REG DENALI_CTL_62
+#define LPDDR4__TMOD_F2__FLD LPDDR4__DENALI_CTL_62__TMOD_F2
+
+#define LPDDR4__DENALI_CTL_63_READ_MASK 0x1F0FFFFFU
+#define LPDDR4__DENALI_CTL_63_WRITE_MASK 0x1F0FFFFFU
+#define LPDDR4__DENALI_CTL_63__TRAS_MAX_F2_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_63__TRAS_MAX_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_63__TRAS_MAX_F2_WIDTH 20U
+#define LPDDR4__TRAS_MAX_F2__REG DENALI_CTL_63
+#define LPDDR4__TRAS_MAX_F2__FLD LPDDR4__DENALI_CTL_63__TRAS_MAX_F2
+
+#define LPDDR4__DENALI_CTL_63__TCKE_F2_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_63__TCKE_F2_SHIFT 24U
+#define LPDDR4__DENALI_CTL_63__TCKE_F2_WIDTH 5U
+#define LPDDR4__TCKE_F2__REG DENALI_CTL_63
+#define LPDDR4__TCKE_F2__FLD LPDDR4__DENALI_CTL_63__TCKE_F2
+
+#define LPDDR4__DENALI_CTL_64_READ_MASK 0x07073FFFU
+#define LPDDR4__DENALI_CTL_64_WRITE_MASK 0x07073FFFU
+#define LPDDR4__DENALI_CTL_64__TCKESR_F2_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_64__TCKESR_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_64__TCKESR_F2_WIDTH 8U
+#define LPDDR4__TCKESR_F2__REG DENALI_CTL_64
+#define LPDDR4__TCKESR_F2__FLD LPDDR4__DENALI_CTL_64__TCKESR_F2
+
+#define LPDDR4__DENALI_CTL_64__TCCDMW_F2_MASK 0x00003F00U
+#define LPDDR4__DENALI_CTL_64__TCCDMW_F2_SHIFT 8U
+#define LPDDR4__DENALI_CTL_64__TCCDMW_F2_WIDTH 6U
+#define LPDDR4__TCCDMW_F2__REG DENALI_CTL_64
+#define LPDDR4__TCCDMW_F2__FLD LPDDR4__DENALI_CTL_64__TCCDMW_F2
+
+#define LPDDR4__DENALI_CTL_64__TPPD_MASK 0x00070000U
+#define LPDDR4__DENALI_CTL_64__TPPD_SHIFT 16U
+#define LPDDR4__DENALI_CTL_64__TPPD_WIDTH 3U
+#define LPDDR4__TPPD__REG DENALI_CTL_64
+#define LPDDR4__TPPD__FLD LPDDR4__DENALI_CTL_64__TPPD
+
+#define LPDDR4__DENALI_CTL_64__MC_RESERVED0_MASK 0x07000000U
+#define LPDDR4__DENALI_CTL_64__MC_RESERVED0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_64__MC_RESERVED0_WIDTH 3U
+#define LPDDR4__MC_RESERVED0__REG DENALI_CTL_64
+#define LPDDR4__MC_RESERVED0__FLD LPDDR4__DENALI_CTL_64__MC_RESERVED0
+
+#define LPDDR4__DENALI_CTL_65_READ_MASK 0xFFFF0107U
+#define LPDDR4__DENALI_CTL_65_WRITE_MASK 0xFFFF0107U
+#define LPDDR4__DENALI_CTL_65__MC_RESERVED1_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_65__MC_RESERVED1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_65__MC_RESERVED1_WIDTH 3U
+#define LPDDR4__MC_RESERVED1__REG DENALI_CTL_65
+#define LPDDR4__MC_RESERVED1__FLD LPDDR4__DENALI_CTL_65__MC_RESERVED1
+
+#define LPDDR4__DENALI_CTL_65__WRITEINTERP_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_65__WRITEINTERP_SHIFT 8U
+#define LPDDR4__DENALI_CTL_65__WRITEINTERP_WIDTH 1U
+#define LPDDR4__DENALI_CTL_65__WRITEINTERP_WOCLR 0U
+#define LPDDR4__DENALI_CTL_65__WRITEINTERP_WOSET 0U
+#define LPDDR4__WRITEINTERP__REG DENALI_CTL_65
+#define LPDDR4__WRITEINTERP__FLD LPDDR4__DENALI_CTL_65__WRITEINTERP
+
+#define LPDDR4__DENALI_CTL_65__TRCD_F0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_65__TRCD_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_65__TRCD_F0_WIDTH 8U
+#define LPDDR4__TRCD_F0__REG DENALI_CTL_65
+#define LPDDR4__TRCD_F0__FLD LPDDR4__DENALI_CTL_65__TRCD_F0
+
+#define LPDDR4__DENALI_CTL_65__TWR_F0_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_65__TWR_F0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_65__TWR_F0_WIDTH 8U
+#define LPDDR4__TWR_F0__REG DENALI_CTL_65
+#define LPDDR4__TWR_F0__FLD LPDDR4__DENALI_CTL_65__TWR_F0
+
+#define LPDDR4__DENALI_CTL_66_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_66_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_66__TRCD_F1_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_66__TRCD_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_66__TRCD_F1_WIDTH 8U
+#define LPDDR4__TRCD_F1__REG DENALI_CTL_66
+#define LPDDR4__TRCD_F1__FLD LPDDR4__DENALI_CTL_66__TRCD_F1
+
+#define LPDDR4__DENALI_CTL_66__TWR_F1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_66__TWR_F1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_66__TWR_F1_WIDTH 8U
+#define LPDDR4__TWR_F1__REG DENALI_CTL_66
+#define LPDDR4__TWR_F1__FLD LPDDR4__DENALI_CTL_66__TWR_F1
+
+#define LPDDR4__DENALI_CTL_66__TRCD_F2_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_66__TRCD_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_66__TRCD_F2_WIDTH 8U
+#define LPDDR4__TRCD_F2__REG DENALI_CTL_66
+#define LPDDR4__TRCD_F2__FLD LPDDR4__DENALI_CTL_66__TRCD_F2
+
+#define LPDDR4__DENALI_CTL_66__TWR_F2_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_66__TWR_F2_SHIFT 24U
+#define LPDDR4__DENALI_CTL_66__TWR_F2_WIDTH 8U
+#define LPDDR4__TWR_F2__REG DENALI_CTL_66
+#define LPDDR4__TWR_F2__FLD LPDDR4__DENALI_CTL_66__TWR_F2
+
+#define LPDDR4__DENALI_CTL_67_READ_MASK 0x0101010FU
+#define LPDDR4__DENALI_CTL_67_WRITE_MASK 0x0101010FU
+#define LPDDR4__DENALI_CTL_67__TMRR_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_67__TMRR_SHIFT 0U
+#define LPDDR4__DENALI_CTL_67__TMRR_WIDTH 4U
+#define LPDDR4__TMRR__REG DENALI_CTL_67
+#define LPDDR4__TMRR__FLD LPDDR4__DENALI_CTL_67__TMRR
+
+#define LPDDR4__DENALI_CTL_67__AP_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_67__AP_SHIFT 8U
+#define LPDDR4__DENALI_CTL_67__AP_WIDTH 1U
+#define LPDDR4__DENALI_CTL_67__AP_WOCLR 0U
+#define LPDDR4__DENALI_CTL_67__AP_WOSET 0U
+#define LPDDR4__AP__REG DENALI_CTL_67
+#define LPDDR4__AP__FLD LPDDR4__DENALI_CTL_67__AP
+
+#define LPDDR4__DENALI_CTL_67__CONCURRENTAP_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_67__CONCURRENTAP_SHIFT 16U
+#define LPDDR4__DENALI_CTL_67__CONCURRENTAP_WIDTH 1U
+#define LPDDR4__DENALI_CTL_67__CONCURRENTAP_WOCLR 0U
+#define LPDDR4__DENALI_CTL_67__CONCURRENTAP_WOSET 0U
+#define LPDDR4__CONCURRENTAP__REG DENALI_CTL_67
+#define LPDDR4__CONCURRENTAP__FLD LPDDR4__DENALI_CTL_67__CONCURRENTAP
+
+#define LPDDR4__DENALI_CTL_67__TRAS_LOCKOUT_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_67__TRAS_LOCKOUT_SHIFT 24U
+#define LPDDR4__DENALI_CTL_67__TRAS_LOCKOUT_WIDTH 1U
+#define LPDDR4__DENALI_CTL_67__TRAS_LOCKOUT_WOCLR 0U
+#define LPDDR4__DENALI_CTL_67__TRAS_LOCKOUT_WOSET 0U
+#define LPDDR4__TRAS_LOCKOUT__REG DENALI_CTL_67
+#define LPDDR4__TRAS_LOCKOUT__FLD LPDDR4__DENALI_CTL_67__TRAS_LOCKOUT
+
+#define LPDDR4__DENALI_CTL_68_READ_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_CTL_68_WRITE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_CTL_68__TDAL_F0_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_68__TDAL_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_68__TDAL_F0_WIDTH 8U
+#define LPDDR4__TDAL_F0__REG DENALI_CTL_68
+#define LPDDR4__TDAL_F0__FLD LPDDR4__DENALI_CTL_68__TDAL_F0
+
+#define LPDDR4__DENALI_CTL_68__TDAL_F1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_68__TDAL_F1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_68__TDAL_F1_WIDTH 8U
+#define LPDDR4__TDAL_F1__REG DENALI_CTL_68
+#define LPDDR4__TDAL_F1__FLD LPDDR4__DENALI_CTL_68__TDAL_F1
+
+#define LPDDR4__DENALI_CTL_68__TDAL_F2_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_68__TDAL_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_68__TDAL_F2_WIDTH 8U
+#define LPDDR4__TDAL_F2__REG DENALI_CTL_68
+#define LPDDR4__TDAL_F2__FLD LPDDR4__DENALI_CTL_68__TDAL_F2
+
+#define LPDDR4__DENALI_CTL_68__BSTLEN_MASK 0x3F000000U
+#define LPDDR4__DENALI_CTL_68__BSTLEN_SHIFT 24U
+#define LPDDR4__DENALI_CTL_68__BSTLEN_WIDTH 6U
+#define LPDDR4__BSTLEN__REG DENALI_CTL_68
+#define LPDDR4__BSTLEN__FLD LPDDR4__DENALI_CTL_68__BSTLEN
+
+#define LPDDR4__DENALI_CTL_69_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_69_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_69__TRP_AB_F0_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_69__TRP_AB_F0_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_69__TRP_AB_F0_0_WIDTH 8U
+#define LPDDR4__TRP_AB_F0_0__REG DENALI_CTL_69
+#define LPDDR4__TRP_AB_F0_0__FLD LPDDR4__DENALI_CTL_69__TRP_AB_F0_0
+
+#define LPDDR4__DENALI_CTL_69__TRP_AB_F1_0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_69__TRP_AB_F1_0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_69__TRP_AB_F1_0_WIDTH 8U
+#define LPDDR4__TRP_AB_F1_0__REG DENALI_CTL_69
+#define LPDDR4__TRP_AB_F1_0__FLD LPDDR4__DENALI_CTL_69__TRP_AB_F1_0
+
+#define LPDDR4__DENALI_CTL_69__TRP_AB_F2_0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_69__TRP_AB_F2_0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_69__TRP_AB_F2_0_WIDTH 8U
+#define LPDDR4__TRP_AB_F2_0__REG DENALI_CTL_69
+#define LPDDR4__TRP_AB_F2_0__FLD LPDDR4__DENALI_CTL_69__TRP_AB_F2_0
+
+#define LPDDR4__DENALI_CTL_69__TRP_AB_F0_1_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_69__TRP_AB_F0_1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_69__TRP_AB_F0_1_WIDTH 8U
+#define LPDDR4__TRP_AB_F0_1__REG DENALI_CTL_69
+#define LPDDR4__TRP_AB_F0_1__FLD LPDDR4__DENALI_CTL_69__TRP_AB_F0_1
+
+#define LPDDR4__DENALI_CTL_70_READ_MASK 0x0301FFFFU
+#define LPDDR4__DENALI_CTL_70_WRITE_MASK 0x0301FFFFU
+#define LPDDR4__DENALI_CTL_70__TRP_AB_F1_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_70__TRP_AB_F1_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_70__TRP_AB_F1_1_WIDTH 8U
+#define LPDDR4__TRP_AB_F1_1__REG DENALI_CTL_70
+#define LPDDR4__TRP_AB_F1_1__FLD LPDDR4__DENALI_CTL_70__TRP_AB_F1_1
+
+#define LPDDR4__DENALI_CTL_70__TRP_AB_F2_1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_70__TRP_AB_F2_1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_70__TRP_AB_F2_1_WIDTH 8U
+#define LPDDR4__TRP_AB_F2_1__REG DENALI_CTL_70
+#define LPDDR4__TRP_AB_F2_1__FLD LPDDR4__DENALI_CTL_70__TRP_AB_F2_1
+
+#define LPDDR4__DENALI_CTL_70__REG_DIMM_ENABLE_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_70__REG_DIMM_ENABLE_SHIFT 16U
+#define LPDDR4__DENALI_CTL_70__REG_DIMM_ENABLE_WIDTH 1U
+#define LPDDR4__DENALI_CTL_70__REG_DIMM_ENABLE_WOCLR 0U
+#define LPDDR4__DENALI_CTL_70__REG_DIMM_ENABLE_WOSET 0U
+#define LPDDR4__REG_DIMM_ENABLE__REG DENALI_CTL_70
+#define LPDDR4__REG_DIMM_ENABLE__FLD LPDDR4__DENALI_CTL_70__REG_DIMM_ENABLE
+
+#define LPDDR4__DENALI_CTL_70__ADDRESS_MIRRORING_MASK 0x03000000U
+#define LPDDR4__DENALI_CTL_70__ADDRESS_MIRRORING_SHIFT 24U
+#define LPDDR4__DENALI_CTL_70__ADDRESS_MIRRORING_WIDTH 2U
+#define LPDDR4__ADDRESS_MIRRORING__REG DENALI_CTL_70
+#define LPDDR4__ADDRESS_MIRRORING__FLD LPDDR4__DENALI_CTL_70__ADDRESS_MIRRORING
+
+#define LPDDR4__DENALI_CTL_71_READ_MASK 0x00010101U
+#define LPDDR4__DENALI_CTL_71_WRITE_MASK 0x00010101U
+#define LPDDR4__DENALI_CTL_71__OPTIMAL_RMODW_EN_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_71__OPTIMAL_RMODW_EN_SHIFT 0U
+#define LPDDR4__DENALI_CTL_71__OPTIMAL_RMODW_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_71__OPTIMAL_RMODW_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_71__OPTIMAL_RMODW_EN_WOSET 0U
+#define LPDDR4__OPTIMAL_RMODW_EN__REG DENALI_CTL_71
+#define LPDDR4__OPTIMAL_RMODW_EN__FLD LPDDR4__DENALI_CTL_71__OPTIMAL_RMODW_EN
+
+#define LPDDR4__DENALI_CTL_71__MC_RESERVED2_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_71__MC_RESERVED2_SHIFT 8U
+#define LPDDR4__DENALI_CTL_71__MC_RESERVED2_WIDTH 1U
+#define LPDDR4__DENALI_CTL_71__MC_RESERVED2_WOCLR 0U
+#define LPDDR4__DENALI_CTL_71__MC_RESERVED2_WOSET 0U
+#define LPDDR4__MC_RESERVED2__REG DENALI_CTL_71
+#define LPDDR4__MC_RESERVED2__FLD LPDDR4__DENALI_CTL_71__MC_RESERVED2
+
+#define LPDDR4__DENALI_CTL_71__NO_MEMORY_DM_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_71__NO_MEMORY_DM_SHIFT 16U
+#define LPDDR4__DENALI_CTL_71__NO_MEMORY_DM_WIDTH 1U
+#define LPDDR4__DENALI_CTL_71__NO_MEMORY_DM_WOCLR 0U
+#define LPDDR4__DENALI_CTL_71__NO_MEMORY_DM_WOSET 0U
+#define LPDDR4__NO_MEMORY_DM__REG DENALI_CTL_71
+#define LPDDR4__NO_MEMORY_DM__FLD LPDDR4__DENALI_CTL_71__NO_MEMORY_DM
+
+#define LPDDR4__DENALI_CTL_72_READ_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_CTL_72_WRITE_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_CTL_72__CA_PARITY_ERROR_INJECT_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_CTL_72__CA_PARITY_ERROR_INJECT_SHIFT 0U
+#define LPDDR4__DENALI_CTL_72__CA_PARITY_ERROR_INJECT_WIDTH 26U
+#define LPDDR4__CA_PARITY_ERROR_INJECT__REG DENALI_CTL_72
+#define LPDDR4__CA_PARITY_ERROR_INJECT__FLD LPDDR4__DENALI_CTL_72__CA_PARITY_ERROR_INJECT
+
+#define LPDDR4__DENALI_CTL_73_READ_MASK 0x01010001U
+#define LPDDR4__DENALI_CTL_73_WRITE_MASK 0x01010001U
+#define LPDDR4__DENALI_CTL_73__CA_PARITY_ERROR_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_73__CA_PARITY_ERROR_SHIFT 0U
+#define LPDDR4__DENALI_CTL_73__CA_PARITY_ERROR_WIDTH 1U
+#define LPDDR4__DENALI_CTL_73__CA_PARITY_ERROR_WOCLR 0U
+#define LPDDR4__DENALI_CTL_73__CA_PARITY_ERROR_WOSET 0U
+#define LPDDR4__CA_PARITY_ERROR__REG DENALI_CTL_73
+#define LPDDR4__CA_PARITY_ERROR__FLD LPDDR4__DENALI_CTL_73__CA_PARITY_ERROR
+
+#define LPDDR4__DENALI_CTL_73__AREFRESH_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_73__AREFRESH_SHIFT 8U
+#define LPDDR4__DENALI_CTL_73__AREFRESH_WIDTH 1U
+#define LPDDR4__DENALI_CTL_73__AREFRESH_WOCLR 0U
+#define LPDDR4__DENALI_CTL_73__AREFRESH_WOSET 0U
+#define LPDDR4__AREFRESH__REG DENALI_CTL_73
+#define LPDDR4__AREFRESH__FLD LPDDR4__DENALI_CTL_73__AREFRESH
+
+#define LPDDR4__DENALI_CTL_73__AREF_STATUS_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_73__AREF_STATUS_SHIFT 16U
+#define LPDDR4__DENALI_CTL_73__AREF_STATUS_WIDTH 1U
+#define LPDDR4__DENALI_CTL_73__AREF_STATUS_WOCLR 0U
+#define LPDDR4__DENALI_CTL_73__AREF_STATUS_WOSET 0U
+#define LPDDR4__AREF_STATUS__REG DENALI_CTL_73
+#define LPDDR4__AREF_STATUS__FLD LPDDR4__DENALI_CTL_73__AREF_STATUS
+
+#define LPDDR4__DENALI_CTL_73__TREF_ENABLE_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_73__TREF_ENABLE_SHIFT 24U
+#define LPDDR4__DENALI_CTL_73__TREF_ENABLE_WIDTH 1U
+#define LPDDR4__DENALI_CTL_73__TREF_ENABLE_WOCLR 0U
+#define LPDDR4__DENALI_CTL_73__TREF_ENABLE_WOSET 0U
+#define LPDDR4__TREF_ENABLE__REG DENALI_CTL_73
+#define LPDDR4__TREF_ENABLE__FLD LPDDR4__DENALI_CTL_73__TREF_ENABLE
+
+#define LPDDR4__DENALI_CTL_74_READ_MASK 0x03FF3F07U
+#define LPDDR4__DENALI_CTL_74_WRITE_MASK 0x03FF3F07U
+#define LPDDR4__DENALI_CTL_74__TRFC_OPT_THRESHOLD_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_74__TRFC_OPT_THRESHOLD_SHIFT 0U
+#define LPDDR4__DENALI_CTL_74__TRFC_OPT_THRESHOLD_WIDTH 3U
+#define LPDDR4__TRFC_OPT_THRESHOLD__REG DENALI_CTL_74
+#define LPDDR4__TRFC_OPT_THRESHOLD__FLD LPDDR4__DENALI_CTL_74__TRFC_OPT_THRESHOLD
+
+#define LPDDR4__DENALI_CTL_74__CS_COMPARISON_FOR_REFRESH_DEPTH_MASK 0x00003F00U
+#define LPDDR4__DENALI_CTL_74__CS_COMPARISON_FOR_REFRESH_DEPTH_SHIFT 8U
+#define LPDDR4__DENALI_CTL_74__CS_COMPARISON_FOR_REFRESH_DEPTH_WIDTH 6U
+#define LPDDR4__CS_COMPARISON_FOR_REFRESH_DEPTH__REG DENALI_CTL_74
+#define LPDDR4__CS_COMPARISON_FOR_REFRESH_DEPTH__FLD LPDDR4__DENALI_CTL_74__CS_COMPARISON_FOR_REFRESH_DEPTH
+
+#define LPDDR4__DENALI_CTL_74__TRFC_F0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_CTL_74__TRFC_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_74__TRFC_F0_WIDTH 10U
+#define LPDDR4__TRFC_F0__REG DENALI_CTL_74
+#define LPDDR4__TRFC_F0__FLD LPDDR4__DENALI_CTL_74__TRFC_F0
+
+#define LPDDR4__DENALI_CTL_75_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_75_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_75__TREF_F0_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_75__TREF_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_75__TREF_F0_WIDTH 20U
+#define LPDDR4__TREF_F0__REG DENALI_CTL_75
+#define LPDDR4__TREF_F0__FLD LPDDR4__DENALI_CTL_75__TREF_F0
+
+#define LPDDR4__DENALI_CTL_76_READ_MASK 0x000003FFU
+#define LPDDR4__DENALI_CTL_76_WRITE_MASK 0x000003FFU
+#define LPDDR4__DENALI_CTL_76__TRFC_F1_MASK 0x000003FFU
+#define LPDDR4__DENALI_CTL_76__TRFC_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_76__TRFC_F1_WIDTH 10U
+#define LPDDR4__TRFC_F1__REG DENALI_CTL_76
+#define LPDDR4__TRFC_F1__FLD LPDDR4__DENALI_CTL_76__TRFC_F1
+
+#define LPDDR4__DENALI_CTL_77_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_77_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_77__TREF_F1_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_77__TREF_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_77__TREF_F1_WIDTH 20U
+#define LPDDR4__TREF_F1__REG DENALI_CTL_77
+#define LPDDR4__TREF_F1__FLD LPDDR4__DENALI_CTL_77__TREF_F1
+
+#define LPDDR4__DENALI_CTL_78_READ_MASK 0x000003FFU
+#define LPDDR4__DENALI_CTL_78_WRITE_MASK 0x000003FFU
+#define LPDDR4__DENALI_CTL_78__TRFC_F2_MASK 0x000003FFU
+#define LPDDR4__DENALI_CTL_78__TRFC_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_78__TRFC_F2_WIDTH 10U
+#define LPDDR4__TRFC_F2__REG DENALI_CTL_78
+#define LPDDR4__TRFC_F2__FLD LPDDR4__DENALI_CTL_78__TRFC_F2
+
+#define LPDDR4__DENALI_CTL_79_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_79_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_79__TREF_F2_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_79__TREF_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_79__TREF_F2_WIDTH 20U
+#define LPDDR4__TREF_F2__REG DENALI_CTL_79
+#define LPDDR4__TREF_F2__FLD LPDDR4__DENALI_CTL_79__TREF_F2
+
+#define LPDDR4__DENALI_CTL_80_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_80_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_80__TREF_INTERVAL_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_80__TREF_INTERVAL_SHIFT 0U
+#define LPDDR4__DENALI_CTL_80__TREF_INTERVAL_WIDTH 20U
+#define LPDDR4__TREF_INTERVAL__REG DENALI_CTL_80
+#define LPDDR4__TREF_INTERVAL__FLD LPDDR4__DENALI_CTL_80__TREF_INTERVAL
+
+#define LPDDR4__DENALI_CTL_81_READ_MASK 0x000003FFU
+#define LPDDR4__DENALI_CTL_81_WRITE_MASK 0x000003FFU
+#define LPDDR4__DENALI_CTL_81__TRFC_PB_F0_MASK 0x000003FFU
+#define LPDDR4__DENALI_CTL_81__TRFC_PB_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_81__TRFC_PB_F0_WIDTH 10U
+#define LPDDR4__TRFC_PB_F0__REG DENALI_CTL_81
+#define LPDDR4__TRFC_PB_F0__FLD LPDDR4__DENALI_CTL_81__TRFC_PB_F0
+
+#define LPDDR4__DENALI_CTL_82_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_82_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_82__TREFI_PB_F0_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_82__TREFI_PB_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_82__TREFI_PB_F0_WIDTH 20U
+#define LPDDR4__TREFI_PB_F0__REG DENALI_CTL_82
+#define LPDDR4__TREFI_PB_F0__FLD LPDDR4__DENALI_CTL_82__TREFI_PB_F0
+
+#define LPDDR4__DENALI_CTL_83_READ_MASK 0x000003FFU
+#define LPDDR4__DENALI_CTL_83_WRITE_MASK 0x000003FFU
+#define LPDDR4__DENALI_CTL_83__TRFC_PB_F1_MASK 0x000003FFU
+#define LPDDR4__DENALI_CTL_83__TRFC_PB_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_83__TRFC_PB_F1_WIDTH 10U
+#define LPDDR4__TRFC_PB_F1__REG DENALI_CTL_83
+#define LPDDR4__TRFC_PB_F1__FLD LPDDR4__DENALI_CTL_83__TRFC_PB_F1
+
+#define LPDDR4__DENALI_CTL_84_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_84_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_84__TREFI_PB_F1_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_84__TREFI_PB_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_84__TREFI_PB_F1_WIDTH 20U
+#define LPDDR4__TREFI_PB_F1__REG DENALI_CTL_84
+#define LPDDR4__TREFI_PB_F1__FLD LPDDR4__DENALI_CTL_84__TREFI_PB_F1
+
+#define LPDDR4__DENALI_CTL_85_READ_MASK 0x000003FFU
+#define LPDDR4__DENALI_CTL_85_WRITE_MASK 0x000003FFU
+#define LPDDR4__DENALI_CTL_85__TRFC_PB_F2_MASK 0x000003FFU
+#define LPDDR4__DENALI_CTL_85__TRFC_PB_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_85__TRFC_PB_F2_WIDTH 10U
+#define LPDDR4__TRFC_PB_F2__REG DENALI_CTL_85
+#define LPDDR4__TRFC_PB_F2__FLD LPDDR4__DENALI_CTL_85__TRFC_PB_F2
+
+#define LPDDR4__DENALI_CTL_86_READ_MASK 0x010FFFFFU
+#define LPDDR4__DENALI_CTL_86_WRITE_MASK 0x010FFFFFU
+#define LPDDR4__DENALI_CTL_86__TREFI_PB_F2_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_86__TREFI_PB_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_86__TREFI_PB_F2_WIDTH 20U
+#define LPDDR4__TREFI_PB_F2__REG DENALI_CTL_86
+#define LPDDR4__TREFI_PB_F2__FLD LPDDR4__DENALI_CTL_86__TREFI_PB_F2
+
+#define LPDDR4__DENALI_CTL_86__PBR_EN_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_86__PBR_EN_SHIFT 24U
+#define LPDDR4__DENALI_CTL_86__PBR_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_86__PBR_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_86__PBR_EN_WOSET 0U
+#define LPDDR4__PBR_EN__REG DENALI_CTL_86
+#define LPDDR4__PBR_EN__FLD LPDDR4__DENALI_CTL_86__PBR_EN
+
+#define LPDDR4__DENALI_CTL_87_READ_MASK 0x0FFFFF01U
+#define LPDDR4__DENALI_CTL_87_WRITE_MASK 0x0FFFFF01U
+#define LPDDR4__DENALI_CTL_87__PBR_NUMERIC_ORDER_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_87__PBR_NUMERIC_ORDER_SHIFT 0U
+#define LPDDR4__DENALI_CTL_87__PBR_NUMERIC_ORDER_WIDTH 1U
+#define LPDDR4__DENALI_CTL_87__PBR_NUMERIC_ORDER_WOCLR 0U
+#define LPDDR4__DENALI_CTL_87__PBR_NUMERIC_ORDER_WOSET 0U
+#define LPDDR4__PBR_NUMERIC_ORDER__REG DENALI_CTL_87
+#define LPDDR4__PBR_NUMERIC_ORDER__FLD LPDDR4__DENALI_CTL_87__PBR_NUMERIC_ORDER
+
+#define LPDDR4__DENALI_CTL_87__PBR_MAX_BANK_WAIT_MASK 0x00FFFF00U
+#define LPDDR4__DENALI_CTL_87__PBR_MAX_BANK_WAIT_SHIFT 8U
+#define LPDDR4__DENALI_CTL_87__PBR_MAX_BANK_WAIT_WIDTH 16U
+#define LPDDR4__PBR_MAX_BANK_WAIT__REG DENALI_CTL_87
+#define LPDDR4__PBR_MAX_BANK_WAIT__FLD LPDDR4__DENALI_CTL_87__PBR_MAX_BANK_WAIT
+
+#define LPDDR4__DENALI_CTL_87__PBR_BANK_SELECT_DELAY_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_87__PBR_BANK_SELECT_DELAY_SHIFT 24U
+#define LPDDR4__DENALI_CTL_87__PBR_BANK_SELECT_DELAY_WIDTH 4U
+#define LPDDR4__PBR_BANK_SELECT_DELAY__REG DENALI_CTL_87
+#define LPDDR4__PBR_BANK_SELECT_DELAY__FLD LPDDR4__DENALI_CTL_87__PBR_BANK_SELECT_DELAY
+
+#define LPDDR4__DENALI_CTL_88_READ_MASK 0x001F1F01U
+#define LPDDR4__DENALI_CTL_88_WRITE_MASK 0x001F1F01U
+#define LPDDR4__DENALI_CTL_88__PBR_CONT_REQ_EN_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_88__PBR_CONT_REQ_EN_SHIFT 0U
+#define LPDDR4__DENALI_CTL_88__PBR_CONT_REQ_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_88__PBR_CONT_REQ_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_88__PBR_CONT_REQ_EN_WOSET 0U
+#define LPDDR4__PBR_CONT_REQ_EN__REG DENALI_CTL_88
+#define LPDDR4__PBR_CONT_REQ_EN__FLD LPDDR4__DENALI_CTL_88__PBR_CONT_REQ_EN
+
+#define LPDDR4__DENALI_CTL_88__AREF_PBR_CONT_EN_THRESHOLD_MASK 0x00001F00U
+#define LPDDR4__DENALI_CTL_88__AREF_PBR_CONT_EN_THRESHOLD_SHIFT 8U
+#define LPDDR4__DENALI_CTL_88__AREF_PBR_CONT_EN_THRESHOLD_WIDTH 5U
+#define LPDDR4__AREF_PBR_CONT_EN_THRESHOLD__REG DENALI_CTL_88
+#define LPDDR4__AREF_PBR_CONT_EN_THRESHOLD__FLD LPDDR4__DENALI_CTL_88__AREF_PBR_CONT_EN_THRESHOLD
+
+#define LPDDR4__DENALI_CTL_88__AREF_PBR_CONT_DIS_THRESHOLD_MASK 0x001F0000U
+#define LPDDR4__DENALI_CTL_88__AREF_PBR_CONT_DIS_THRESHOLD_SHIFT 16U
+#define LPDDR4__DENALI_CTL_88__AREF_PBR_CONT_DIS_THRESHOLD_WIDTH 5U
+#define LPDDR4__AREF_PBR_CONT_DIS_THRESHOLD__REG DENALI_CTL_88
+#define LPDDR4__AREF_PBR_CONT_DIS_THRESHOLD__FLD LPDDR4__DENALI_CTL_88__AREF_PBR_CONT_DIS_THRESHOLD
+
+#define LPDDR4__DENALI_CTL_89_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_89_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_89__TPDEX_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_89__TPDEX_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_89__TPDEX_F0_WIDTH 16U
+#define LPDDR4__TPDEX_F0__REG DENALI_CTL_89
+#define LPDDR4__TPDEX_F0__FLD LPDDR4__DENALI_CTL_89__TPDEX_F0
+
+#define LPDDR4__DENALI_CTL_89__TPDEX_F1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_89__TPDEX_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_89__TPDEX_F1_WIDTH 16U
+#define LPDDR4__TPDEX_F1__REG DENALI_CTL_89
+#define LPDDR4__TPDEX_F1__FLD LPDDR4__DENALI_CTL_89__TPDEX_F1
+
+#define LPDDR4__DENALI_CTL_90_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_90_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_90__TPDEX_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_90__TPDEX_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_90__TPDEX_F2_WIDTH 16U
+#define LPDDR4__TPDEX_F2__REG DENALI_CTL_90
+#define LPDDR4__TPDEX_F2__FLD LPDDR4__DENALI_CTL_90__TPDEX_F2
+
+#define LPDDR4__DENALI_CTL_90__TMRRI_F0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_90__TMRRI_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_90__TMRRI_F0_WIDTH 8U
+#define LPDDR4__TMRRI_F0__REG DENALI_CTL_90
+#define LPDDR4__TMRRI_F0__FLD LPDDR4__DENALI_CTL_90__TMRRI_F0
+
+#define LPDDR4__DENALI_CTL_90__TMRRI_F1_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_90__TMRRI_F1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_90__TMRRI_F1_WIDTH 8U
+#define LPDDR4__TMRRI_F1__REG DENALI_CTL_90
+#define LPDDR4__TMRRI_F1__FLD LPDDR4__DENALI_CTL_90__TMRRI_F1
+
+#define LPDDR4__DENALI_CTL_91_READ_MASK 0x1F1F1FFFU
+#define LPDDR4__DENALI_CTL_91_WRITE_MASK 0x1F1F1FFFU
+#define LPDDR4__DENALI_CTL_91__TMRRI_F2_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_91__TMRRI_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_91__TMRRI_F2_WIDTH 8U
+#define LPDDR4__TMRRI_F2__REG DENALI_CTL_91
+#define LPDDR4__TMRRI_F2__FLD LPDDR4__DENALI_CTL_91__TMRRI_F2
+
+#define LPDDR4__DENALI_CTL_91__TCKELCS_F0_MASK 0x00001F00U
+#define LPDDR4__DENALI_CTL_91__TCKELCS_F0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_91__TCKELCS_F0_WIDTH 5U
+#define LPDDR4__TCKELCS_F0__REG DENALI_CTL_91
+#define LPDDR4__TCKELCS_F0__FLD LPDDR4__DENALI_CTL_91__TCKELCS_F0
+
+#define LPDDR4__DENALI_CTL_91__TCKEHCS_F0_MASK 0x001F0000U
+#define LPDDR4__DENALI_CTL_91__TCKEHCS_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_91__TCKEHCS_F0_WIDTH 5U
+#define LPDDR4__TCKEHCS_F0__REG DENALI_CTL_91
+#define LPDDR4__TCKEHCS_F0__FLD LPDDR4__DENALI_CTL_91__TCKEHCS_F0
+
+#define LPDDR4__DENALI_CTL_91__TMRWCKEL_F0_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_91__TMRWCKEL_F0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_91__TMRWCKEL_F0_WIDTH 5U
+#define LPDDR4__TMRWCKEL_F0__REG DENALI_CTL_91
+#define LPDDR4__TMRWCKEL_F0__FLD LPDDR4__DENALI_CTL_91__TMRWCKEL_F0
+
+#define LPDDR4__DENALI_CTL_92_READ_MASK 0x1F1F1F0FU
+#define LPDDR4__DENALI_CTL_92_WRITE_MASK 0x1F1F1F0FU
+#define LPDDR4__DENALI_CTL_92__TZQCKE_F0_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_92__TZQCKE_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_92__TZQCKE_F0_WIDTH 4U
+#define LPDDR4__TZQCKE_F0__REG DENALI_CTL_92
+#define LPDDR4__TZQCKE_F0__FLD LPDDR4__DENALI_CTL_92__TZQCKE_F0
+
+#define LPDDR4__DENALI_CTL_92__TCKELCS_F1_MASK 0x00001F00U
+#define LPDDR4__DENALI_CTL_92__TCKELCS_F1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_92__TCKELCS_F1_WIDTH 5U
+#define LPDDR4__TCKELCS_F1__REG DENALI_CTL_92
+#define LPDDR4__TCKELCS_F1__FLD LPDDR4__DENALI_CTL_92__TCKELCS_F1
+
+#define LPDDR4__DENALI_CTL_92__TCKEHCS_F1_MASK 0x001F0000U
+#define LPDDR4__DENALI_CTL_92__TCKEHCS_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_92__TCKEHCS_F1_WIDTH 5U
+#define LPDDR4__TCKEHCS_F1__REG DENALI_CTL_92
+#define LPDDR4__TCKEHCS_F1__FLD LPDDR4__DENALI_CTL_92__TCKEHCS_F1
+
+#define LPDDR4__DENALI_CTL_92__TMRWCKEL_F1_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_92__TMRWCKEL_F1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_92__TMRWCKEL_F1_WIDTH 5U
+#define LPDDR4__TMRWCKEL_F1__REG DENALI_CTL_92
+#define LPDDR4__TMRWCKEL_F1__FLD LPDDR4__DENALI_CTL_92__TMRWCKEL_F1
+
+#define LPDDR4__DENALI_CTL_93_READ_MASK 0x1F1F1F0FU
+#define LPDDR4__DENALI_CTL_93_WRITE_MASK 0x1F1F1F0FU
+#define LPDDR4__DENALI_CTL_93__TZQCKE_F1_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_93__TZQCKE_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_93__TZQCKE_F1_WIDTH 4U
+#define LPDDR4__TZQCKE_F1__REG DENALI_CTL_93
+#define LPDDR4__TZQCKE_F1__FLD LPDDR4__DENALI_CTL_93__TZQCKE_F1
+
+#define LPDDR4__DENALI_CTL_93__TCKELCS_F2_MASK 0x00001F00U
+#define LPDDR4__DENALI_CTL_93__TCKELCS_F2_SHIFT 8U
+#define LPDDR4__DENALI_CTL_93__TCKELCS_F2_WIDTH 5U
+#define LPDDR4__TCKELCS_F2__REG DENALI_CTL_93
+#define LPDDR4__TCKELCS_F2__FLD LPDDR4__DENALI_CTL_93__TCKELCS_F2
+
+#define LPDDR4__DENALI_CTL_93__TCKEHCS_F2_MASK 0x001F0000U
+#define LPDDR4__DENALI_CTL_93__TCKEHCS_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_93__TCKEHCS_F2_WIDTH 5U
+#define LPDDR4__TCKEHCS_F2__REG DENALI_CTL_93
+#define LPDDR4__TCKEHCS_F2__FLD LPDDR4__DENALI_CTL_93__TCKEHCS_F2
+
+#define LPDDR4__DENALI_CTL_93__TMRWCKEL_F2_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_93__TMRWCKEL_F2_SHIFT 24U
+#define LPDDR4__DENALI_CTL_93__TMRWCKEL_F2_WIDTH 5U
+#define LPDDR4__TMRWCKEL_F2__REG DENALI_CTL_93
+#define LPDDR4__TMRWCKEL_F2__FLD LPDDR4__DENALI_CTL_93__TMRWCKEL_F2
+
+#define LPDDR4__DENALI_CTL_94_READ_MASK 0x1F011F0FU
+#define LPDDR4__DENALI_CTL_94_WRITE_MASK 0x1F011F0FU
+#define LPDDR4__DENALI_CTL_94__TZQCKE_F2_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_94__TZQCKE_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_94__TZQCKE_F2_WIDTH 4U
+#define LPDDR4__TZQCKE_F2__REG DENALI_CTL_94
+#define LPDDR4__TZQCKE_F2__FLD LPDDR4__DENALI_CTL_94__TZQCKE_F2
+
+#define LPDDR4__DENALI_CTL_94__TCSCKE_F0_MASK 0x00001F00U
+#define LPDDR4__DENALI_CTL_94__TCSCKE_F0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_94__TCSCKE_F0_WIDTH 5U
+#define LPDDR4__TCSCKE_F0__REG DENALI_CTL_94
+#define LPDDR4__TCSCKE_F0__FLD LPDDR4__DENALI_CTL_94__TCSCKE_F0
+
+#define LPDDR4__DENALI_CTL_94__CA_DEFAULT_VAL_F0_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_94__CA_DEFAULT_VAL_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_94__CA_DEFAULT_VAL_F0_WIDTH 1U
+#define LPDDR4__DENALI_CTL_94__CA_DEFAULT_VAL_F0_WOCLR 0U
+#define LPDDR4__DENALI_CTL_94__CA_DEFAULT_VAL_F0_WOSET 0U
+#define LPDDR4__CA_DEFAULT_VAL_F0__REG DENALI_CTL_94
+#define LPDDR4__CA_DEFAULT_VAL_F0__FLD LPDDR4__DENALI_CTL_94__CA_DEFAULT_VAL_F0
+
+#define LPDDR4__DENALI_CTL_94__TCSCKE_F1_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_94__TCSCKE_F1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_94__TCSCKE_F1_WIDTH 5U
+#define LPDDR4__TCSCKE_F1__REG DENALI_CTL_94
+#define LPDDR4__TCSCKE_F1__FLD LPDDR4__DENALI_CTL_94__TCSCKE_F1
+
+#define LPDDR4__DENALI_CTL_95_READ_MASK 0x00011F01U
+#define LPDDR4__DENALI_CTL_95_WRITE_MASK 0x00011F01U
+#define LPDDR4__DENALI_CTL_95__CA_DEFAULT_VAL_F1_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_95__CA_DEFAULT_VAL_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_95__CA_DEFAULT_VAL_F1_WIDTH 1U
+#define LPDDR4__DENALI_CTL_95__CA_DEFAULT_VAL_F1_WOCLR 0U
+#define LPDDR4__DENALI_CTL_95__CA_DEFAULT_VAL_F1_WOSET 0U
+#define LPDDR4__CA_DEFAULT_VAL_F1__REG DENALI_CTL_95
+#define LPDDR4__CA_DEFAULT_VAL_F1__FLD LPDDR4__DENALI_CTL_95__CA_DEFAULT_VAL_F1
+
+#define LPDDR4__DENALI_CTL_95__TCSCKE_F2_MASK 0x00001F00U
+#define LPDDR4__DENALI_CTL_95__TCSCKE_F2_SHIFT 8U
+#define LPDDR4__DENALI_CTL_95__TCSCKE_F2_WIDTH 5U
+#define LPDDR4__TCSCKE_F2__REG DENALI_CTL_95
+#define LPDDR4__TCSCKE_F2__FLD LPDDR4__DENALI_CTL_95__TCSCKE_F2
+
+#define LPDDR4__DENALI_CTL_95__CA_DEFAULT_VAL_F2_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_95__CA_DEFAULT_VAL_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_95__CA_DEFAULT_VAL_F2_WIDTH 1U
+#define LPDDR4__DENALI_CTL_95__CA_DEFAULT_VAL_F2_WOCLR 0U
+#define LPDDR4__DENALI_CTL_95__CA_DEFAULT_VAL_F2_WOSET 0U
+#define LPDDR4__CA_DEFAULT_VAL_F2__REG DENALI_CTL_95
+#define LPDDR4__CA_DEFAULT_VAL_F2__FLD LPDDR4__DENALI_CTL_95__CA_DEFAULT_VAL_F2
+
+#define LPDDR4__DENALI_CTL_96_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_96_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_96__TXSR_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_96__TXSR_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_96__TXSR_F0_WIDTH 16U
+#define LPDDR4__TXSR_F0__REG DENALI_CTL_96
+#define LPDDR4__TXSR_F0__FLD LPDDR4__DENALI_CTL_96__TXSR_F0
+
+#define LPDDR4__DENALI_CTL_96__TXSNR_F0_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_96__TXSNR_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_96__TXSNR_F0_WIDTH 16U
+#define LPDDR4__TXSNR_F0__REG DENALI_CTL_96
+#define LPDDR4__TXSNR_F0__FLD LPDDR4__DENALI_CTL_96__TXSNR_F0
+
+#define LPDDR4__DENALI_CTL_97_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_97_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_97__TXSR_F1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_97__TXSR_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_97__TXSR_F1_WIDTH 16U
+#define LPDDR4__TXSR_F1__REG DENALI_CTL_97
+#define LPDDR4__TXSR_F1__FLD LPDDR4__DENALI_CTL_97__TXSR_F1
+
+#define LPDDR4__DENALI_CTL_97__TXSNR_F1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_97__TXSNR_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_97__TXSNR_F1_WIDTH 16U
+#define LPDDR4__TXSNR_F1__REG DENALI_CTL_97
+#define LPDDR4__TXSNR_F1__FLD LPDDR4__DENALI_CTL_97__TXSNR_F1
+
+#define LPDDR4__DENALI_CTL_98_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_98_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_98__TXSR_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_98__TXSR_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_98__TXSR_F2_WIDTH 16U
+#define LPDDR4__TXSR_F2__REG DENALI_CTL_98
+#define LPDDR4__TXSR_F2__FLD LPDDR4__DENALI_CTL_98__TXSR_F2
+
+#define LPDDR4__DENALI_CTL_98__TXSNR_F2_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_98__TXSNR_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_98__TXSNR_F2_WIDTH 16U
+#define LPDDR4__TXSNR_F2__REG DENALI_CTL_98
+#define LPDDR4__TXSNR_F2__FLD LPDDR4__DENALI_CTL_98__TXSNR_F2
+
+#define LPDDR4__DENALI_CTL_99_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_99_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_99__TXPR_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_99__TXPR_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_99__TXPR_F0_WIDTH 16U
+#define LPDDR4__TXPR_F0__REG DENALI_CTL_99
+#define LPDDR4__TXPR_F0__FLD LPDDR4__DENALI_CTL_99__TXPR_F0
+
+#define LPDDR4__DENALI_CTL_99__TXPR_F1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_99__TXPR_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_99__TXPR_F1_WIDTH 16U
+#define LPDDR4__TXPR_F1__REG DENALI_CTL_99
+#define LPDDR4__TXPR_F1__FLD LPDDR4__DENALI_CTL_99__TXPR_F1
+
+#define LPDDR4__DENALI_CTL_100_READ_MASK 0x07FFFFFFU
+#define LPDDR4__DENALI_CTL_100_WRITE_MASK 0x07FFFFFFU
+#define LPDDR4__DENALI_CTL_100__TXPR_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_100__TXPR_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_100__TXPR_F2_WIDTH 16U
+#define LPDDR4__TXPR_F2__REG DENALI_CTL_100
+#define LPDDR4__TXPR_F2__FLD LPDDR4__DENALI_CTL_100__TXPR_F2
+
+#define LPDDR4__DENALI_CTL_100__TSR_F0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_100__TSR_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_100__TSR_F0_WIDTH 8U
+#define LPDDR4__TSR_F0__REG DENALI_CTL_100
+#define LPDDR4__TSR_F0__FLD LPDDR4__DENALI_CTL_100__TSR_F0
+
+#define LPDDR4__DENALI_CTL_100__TESCKE_F0_MASK 0x07000000U
+#define LPDDR4__DENALI_CTL_100__TESCKE_F0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_100__TESCKE_F0_WIDTH 3U
+#define LPDDR4__TESCKE_F0__REG DENALI_CTL_100
+#define LPDDR4__TESCKE_F0__FLD LPDDR4__DENALI_CTL_100__TESCKE_F0
+
+#define LPDDR4__DENALI_CTL_101_READ_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_101_WRITE_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_101__TCSCKEH_F0_MASK 0x0000001FU
+#define LPDDR4__DENALI_CTL_101__TCSCKEH_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_101__TCSCKEH_F0_WIDTH 5U
+#define LPDDR4__TCSCKEH_F0__REG DENALI_CTL_101
+#define LPDDR4__TCSCKEH_F0__FLD LPDDR4__DENALI_CTL_101__TCSCKEH_F0
+
+#define LPDDR4__DENALI_CTL_101__TCKELCMD_F0_MASK 0x00001F00U
+#define LPDDR4__DENALI_CTL_101__TCKELCMD_F0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_101__TCKELCMD_F0_WIDTH 5U
+#define LPDDR4__TCKELCMD_F0__REG DENALI_CTL_101
+#define LPDDR4__TCKELCMD_F0__FLD LPDDR4__DENALI_CTL_101__TCKELCMD_F0
+
+#define LPDDR4__DENALI_CTL_101__TCKEHCMD_F0_MASK 0x001F0000U
+#define LPDDR4__DENALI_CTL_101__TCKEHCMD_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_101__TCKEHCMD_F0_WIDTH 5U
+#define LPDDR4__TCKEHCMD_F0__REG DENALI_CTL_101
+#define LPDDR4__TCKEHCMD_F0__FLD LPDDR4__DENALI_CTL_101__TCKEHCMD_F0
+
+#define LPDDR4__DENALI_CTL_101__TCKCKEL_F0_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_101__TCKCKEL_F0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_101__TCKCKEL_F0_WIDTH 5U
+#define LPDDR4__TCKCKEL_F0__REG DENALI_CTL_101
+#define LPDDR4__TCKCKEL_F0__FLD LPDDR4__DENALI_CTL_101__TCKCKEL_F0
+
+#define LPDDR4__DENALI_CTL_102_READ_MASK 0x1F07FF1FU
+#define LPDDR4__DENALI_CTL_102_WRITE_MASK 0x1F07FF1FU
+#define LPDDR4__DENALI_CTL_102__TCKELPD_F0_MASK 0x0000001FU
+#define LPDDR4__DENALI_CTL_102__TCKELPD_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_102__TCKELPD_F0_WIDTH 5U
+#define LPDDR4__TCKELPD_F0__REG DENALI_CTL_102
+#define LPDDR4__TCKELPD_F0__FLD LPDDR4__DENALI_CTL_102__TCKELPD_F0
+
+#define LPDDR4__DENALI_CTL_102__TSR_F1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_102__TSR_F1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_102__TSR_F1_WIDTH 8U
+#define LPDDR4__TSR_F1__REG DENALI_CTL_102
+#define LPDDR4__TSR_F1__FLD LPDDR4__DENALI_CTL_102__TSR_F1
+
+#define LPDDR4__DENALI_CTL_102__TESCKE_F1_MASK 0x00070000U
+#define LPDDR4__DENALI_CTL_102__TESCKE_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_102__TESCKE_F1_WIDTH 3U
+#define LPDDR4__TESCKE_F1__REG DENALI_CTL_102
+#define LPDDR4__TESCKE_F1__FLD LPDDR4__DENALI_CTL_102__TESCKE_F1
+
+#define LPDDR4__DENALI_CTL_102__TCSCKEH_F1_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_102__TCSCKEH_F1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_102__TCSCKEH_F1_WIDTH 5U
+#define LPDDR4__TCSCKEH_F1__REG DENALI_CTL_102
+#define LPDDR4__TCSCKEH_F1__FLD LPDDR4__DENALI_CTL_102__TCSCKEH_F1
+
+#define LPDDR4__DENALI_CTL_103_READ_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_103_WRITE_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_103__TCKELCMD_F1_MASK 0x0000001FU
+#define LPDDR4__DENALI_CTL_103__TCKELCMD_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_103__TCKELCMD_F1_WIDTH 5U
+#define LPDDR4__TCKELCMD_F1__REG DENALI_CTL_103
+#define LPDDR4__TCKELCMD_F1__FLD LPDDR4__DENALI_CTL_103__TCKELCMD_F1
+
+#define LPDDR4__DENALI_CTL_103__TCKEHCMD_F1_MASK 0x00001F00U
+#define LPDDR4__DENALI_CTL_103__TCKEHCMD_F1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_103__TCKEHCMD_F1_WIDTH 5U
+#define LPDDR4__TCKEHCMD_F1__REG DENALI_CTL_103
+#define LPDDR4__TCKEHCMD_F1__FLD LPDDR4__DENALI_CTL_103__TCKEHCMD_F1
+
+#define LPDDR4__DENALI_CTL_103__TCKCKEL_F1_MASK 0x001F0000U
+#define LPDDR4__DENALI_CTL_103__TCKCKEL_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_103__TCKCKEL_F1_WIDTH 5U
+#define LPDDR4__TCKCKEL_F1__REG DENALI_CTL_103
+#define LPDDR4__TCKCKEL_F1__FLD LPDDR4__DENALI_CTL_103__TCKCKEL_F1
+
+#define LPDDR4__DENALI_CTL_103__TCKELPD_F1_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_103__TCKELPD_F1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_103__TCKELPD_F1_WIDTH 5U
+#define LPDDR4__TCKELPD_F1__REG DENALI_CTL_103
+#define LPDDR4__TCKELPD_F1__FLD LPDDR4__DENALI_CTL_103__TCKELPD_F1
+
+#define LPDDR4__DENALI_CTL_104_READ_MASK 0x1F1F07FFU
+#define LPDDR4__DENALI_CTL_104_WRITE_MASK 0x1F1F07FFU
+#define LPDDR4__DENALI_CTL_104__TSR_F2_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_104__TSR_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_104__TSR_F2_WIDTH 8U
+#define LPDDR4__TSR_F2__REG DENALI_CTL_104
+#define LPDDR4__TSR_F2__FLD LPDDR4__DENALI_CTL_104__TSR_F2
+
+#define LPDDR4__DENALI_CTL_104__TESCKE_F2_MASK 0x00000700U
+#define LPDDR4__DENALI_CTL_104__TESCKE_F2_SHIFT 8U
+#define LPDDR4__DENALI_CTL_104__TESCKE_F2_WIDTH 3U
+#define LPDDR4__TESCKE_F2__REG DENALI_CTL_104
+#define LPDDR4__TESCKE_F2__FLD LPDDR4__DENALI_CTL_104__TESCKE_F2
+
+#define LPDDR4__DENALI_CTL_104__TCSCKEH_F2_MASK 0x001F0000U
+#define LPDDR4__DENALI_CTL_104__TCSCKEH_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_104__TCSCKEH_F2_WIDTH 5U
+#define LPDDR4__TCSCKEH_F2__REG DENALI_CTL_104
+#define LPDDR4__TCSCKEH_F2__FLD LPDDR4__DENALI_CTL_104__TCSCKEH_F2
+
+#define LPDDR4__DENALI_CTL_104__TCKELCMD_F2_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_104__TCKELCMD_F2_SHIFT 24U
+#define LPDDR4__DENALI_CTL_104__TCKELCMD_F2_WIDTH 5U
+#define LPDDR4__TCKELCMD_F2__REG DENALI_CTL_104
+#define LPDDR4__TCKELCMD_F2__FLD LPDDR4__DENALI_CTL_104__TCKELCMD_F2
+
+#define LPDDR4__DENALI_CTL_105_READ_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_105_WRITE_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_105__TCKEHCMD_F2_MASK 0x0000001FU
+#define LPDDR4__DENALI_CTL_105__TCKEHCMD_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_105__TCKEHCMD_F2_WIDTH 5U
+#define LPDDR4__TCKEHCMD_F2__REG DENALI_CTL_105
+#define LPDDR4__TCKEHCMD_F2__FLD LPDDR4__DENALI_CTL_105__TCKEHCMD_F2
+
+#define LPDDR4__DENALI_CTL_105__TCKCKEL_F2_MASK 0x00001F00U
+#define LPDDR4__DENALI_CTL_105__TCKCKEL_F2_SHIFT 8U
+#define LPDDR4__DENALI_CTL_105__TCKCKEL_F2_WIDTH 5U
+#define LPDDR4__TCKCKEL_F2__REG DENALI_CTL_105
+#define LPDDR4__TCKCKEL_F2__FLD LPDDR4__DENALI_CTL_105__TCKCKEL_F2
+
+#define LPDDR4__DENALI_CTL_105__TCKELPD_F2_MASK 0x001F0000U
+#define LPDDR4__DENALI_CTL_105__TCKELPD_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_105__TCKELPD_F2_WIDTH 5U
+#define LPDDR4__TCKELPD_F2__REG DENALI_CTL_105
+#define LPDDR4__TCKELPD_F2__FLD LPDDR4__DENALI_CTL_105__TCKELPD_F2
+
+#define LPDDR4__DENALI_CTL_105__TCMDCKE_F0_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_105__TCMDCKE_F0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_105__TCMDCKE_F0_WIDTH 5U
+#define LPDDR4__TCMDCKE_F0__REG DENALI_CTL_105
+#define LPDDR4__TCMDCKE_F0__FLD LPDDR4__DENALI_CTL_105__TCMDCKE_F0
+
+#define LPDDR4__DENALI_CTL_106_READ_MASK 0x01011F1FU
+#define LPDDR4__DENALI_CTL_106_WRITE_MASK 0x01011F1FU
+#define LPDDR4__DENALI_CTL_106__TCMDCKE_F1_MASK 0x0000001FU
+#define LPDDR4__DENALI_CTL_106__TCMDCKE_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_106__TCMDCKE_F1_WIDTH 5U
+#define LPDDR4__TCMDCKE_F1__REG DENALI_CTL_106
+#define LPDDR4__TCMDCKE_F1__FLD LPDDR4__DENALI_CTL_106__TCMDCKE_F1
+
+#define LPDDR4__DENALI_CTL_106__TCMDCKE_F2_MASK 0x00001F00U
+#define LPDDR4__DENALI_CTL_106__TCMDCKE_F2_SHIFT 8U
+#define LPDDR4__DENALI_CTL_106__TCMDCKE_F2_WIDTH 5U
+#define LPDDR4__TCMDCKE_F2__REG DENALI_CTL_106
+#define LPDDR4__TCMDCKE_F2__FLD LPDDR4__DENALI_CTL_106__TCMDCKE_F2
+
+#define LPDDR4__DENALI_CTL_106__PWRUP_SREFRESH_EXIT_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_106__PWRUP_SREFRESH_EXIT_SHIFT 16U
+#define LPDDR4__DENALI_CTL_106__PWRUP_SREFRESH_EXIT_WIDTH 1U
+#define LPDDR4__DENALI_CTL_106__PWRUP_SREFRESH_EXIT_WOCLR 0U
+#define LPDDR4__DENALI_CTL_106__PWRUP_SREFRESH_EXIT_WOSET 0U
+#define LPDDR4__PWRUP_SREFRESH_EXIT__REG DENALI_CTL_106
+#define LPDDR4__PWRUP_SREFRESH_EXIT__FLD LPDDR4__DENALI_CTL_106__PWRUP_SREFRESH_EXIT
+
+#define LPDDR4__DENALI_CTL_106__SREFRESH_EXIT_NO_REFRESH_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_106__SREFRESH_EXIT_NO_REFRESH_SHIFT 24U
+#define LPDDR4__DENALI_CTL_106__SREFRESH_EXIT_NO_REFRESH_WIDTH 1U
+#define LPDDR4__DENALI_CTL_106__SREFRESH_EXIT_NO_REFRESH_WOCLR 0U
+#define LPDDR4__DENALI_CTL_106__SREFRESH_EXIT_NO_REFRESH_WOSET 0U
+#define LPDDR4__SREFRESH_EXIT_NO_REFRESH__REG DENALI_CTL_106
+#define LPDDR4__SREFRESH_EXIT_NO_REFRESH__FLD LPDDR4__DENALI_CTL_106__SREFRESH_EXIT_NO_REFRESH
+
+#define LPDDR4__DENALI_CTL_107_READ_MASK 0x7F000701U
+#define LPDDR4__DENALI_CTL_107_WRITE_MASK 0x7F000701U
+#define LPDDR4__DENALI_CTL_107__ENABLE_QUICK_SREFRESH_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_107__ENABLE_QUICK_SREFRESH_SHIFT 0U
+#define LPDDR4__DENALI_CTL_107__ENABLE_QUICK_SREFRESH_WIDTH 1U
+#define LPDDR4__DENALI_CTL_107__ENABLE_QUICK_SREFRESH_WOCLR 0U
+#define LPDDR4__DENALI_CTL_107__ENABLE_QUICK_SREFRESH_WOSET 0U
+#define LPDDR4__ENABLE_QUICK_SREFRESH__REG DENALI_CTL_107
+#define LPDDR4__ENABLE_QUICK_SREFRESH__FLD LPDDR4__DENALI_CTL_107__ENABLE_QUICK_SREFRESH
+
+#define LPDDR4__DENALI_CTL_107__CKE_DELAY_MASK 0x00000700U
+#define LPDDR4__DENALI_CTL_107__CKE_DELAY_SHIFT 8U
+#define LPDDR4__DENALI_CTL_107__CKE_DELAY_WIDTH 3U
+#define LPDDR4__CKE_DELAY__REG DENALI_CTL_107
+#define LPDDR4__CKE_DELAY__FLD LPDDR4__DENALI_CTL_107__CKE_DELAY
+
+#define LPDDR4__DENALI_CTL_107__DFS_CMD_MASK 0x001F0000U
+#define LPDDR4__DENALI_CTL_107__DFS_CMD_SHIFT 16U
+#define LPDDR4__DENALI_CTL_107__DFS_CMD_WIDTH 5U
+#define LPDDR4__DFS_CMD__REG DENALI_CTL_107
+#define LPDDR4__DFS_CMD__FLD LPDDR4__DENALI_CTL_107__DFS_CMD
+
+#define LPDDR4__DENALI_CTL_107__DFS_STATUS_MASK 0x7F000000U
+#define LPDDR4__DENALI_CTL_107__DFS_STATUS_SHIFT 24U
+#define LPDDR4__DENALI_CTL_107__DFS_STATUS_WIDTH 7U
+#define LPDDR4__DFS_STATUS__REG DENALI_CTL_107
+#define LPDDR4__DFS_STATUS__FLD LPDDR4__DENALI_CTL_107__DFS_STATUS
+
+#define LPDDR4__DENALI_CTL_108_READ_MASK 0x00FFFF01U
+#define LPDDR4__DENALI_CTL_108_WRITE_MASK 0x00FFFF01U
+#define LPDDR4__DENALI_CTL_108__DFS_ZQ_EN_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_108__DFS_ZQ_EN_SHIFT 0U
+#define LPDDR4__DENALI_CTL_108__DFS_ZQ_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_108__DFS_ZQ_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_108__DFS_ZQ_EN_WOSET 0U
+#define LPDDR4__DFS_ZQ_EN__REG DENALI_CTL_108
+#define LPDDR4__DFS_ZQ_EN__FLD LPDDR4__DENALI_CTL_108__DFS_ZQ_EN
+
+#define LPDDR4__DENALI_CTL_108__DFS_PROMOTE_THRESHOLD_F0_MASK 0x00FFFF00U
+#define LPDDR4__DENALI_CTL_108__DFS_PROMOTE_THRESHOLD_F0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_108__DFS_PROMOTE_THRESHOLD_F0_WIDTH 16U
+#define LPDDR4__DFS_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_108
+#define LPDDR4__DFS_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_108__DFS_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_109_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_109_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_109__DFS_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_109__DFS_PROMOTE_THRESHOLD_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_109__DFS_PROMOTE_THRESHOLD_F1_WIDTH 16U
+#define LPDDR4__DFS_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_109
+#define LPDDR4__DFS_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_109__DFS_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_109__DFS_PROMOTE_THRESHOLD_F2_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_109__DFS_PROMOTE_THRESHOLD_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_109__DFS_PROMOTE_THRESHOLD_F2_WIDTH 16U
+#define LPDDR4__DFS_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_109
+#define LPDDR4__DFS_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_109__DFS_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_110_READ_MASK 0xFF070707U
+#define LPDDR4__DENALI_CTL_110_WRITE_MASK 0xFF070707U
+#define LPDDR4__DENALI_CTL_110__ZQ_STATUS_LOG_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_110__ZQ_STATUS_LOG_SHIFT 0U
+#define LPDDR4__DENALI_CTL_110__ZQ_STATUS_LOG_WIDTH 3U
+#define LPDDR4__ZQ_STATUS_LOG__REG DENALI_CTL_110
+#define LPDDR4__ZQ_STATUS_LOG__FLD LPDDR4__DENALI_CTL_110__ZQ_STATUS_LOG
+
+#define LPDDR4__DENALI_CTL_110__MC_RESERVED3_MASK 0x00000700U
+#define LPDDR4__DENALI_CTL_110__MC_RESERVED3_SHIFT 8U
+#define LPDDR4__DENALI_CTL_110__MC_RESERVED3_WIDTH 3U
+#define LPDDR4__MC_RESERVED3__REG DENALI_CTL_110
+#define LPDDR4__MC_RESERVED3__FLD LPDDR4__DENALI_CTL_110__MC_RESERVED3
+
+#define LPDDR4__DENALI_CTL_110__MC_RESERVED4_MASK 0x00070000U
+#define LPDDR4__DENALI_CTL_110__MC_RESERVED4_SHIFT 16U
+#define LPDDR4__DENALI_CTL_110__MC_RESERVED4_WIDTH 3U
+#define LPDDR4__MC_RESERVED4__REG DENALI_CTL_110
+#define LPDDR4__MC_RESERVED4__FLD LPDDR4__DENALI_CTL_110__MC_RESERVED4
+
+#define LPDDR4__DENALI_CTL_110__MC_RESERVED5_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_110__MC_RESERVED5_SHIFT 24U
+#define LPDDR4__DENALI_CTL_110__MC_RESERVED5_WIDTH 8U
+#define LPDDR4__MC_RESERVED5__REG DENALI_CTL_110
+#define LPDDR4__MC_RESERVED5__FLD LPDDR4__DENALI_CTL_110__MC_RESERVED5
+
+#define LPDDR4__DENALI_CTL_111_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_111_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_111__MC_RESERVED6_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_111__MC_RESERVED6_SHIFT 0U
+#define LPDDR4__DENALI_CTL_111__MC_RESERVED6_WIDTH 8U
+#define LPDDR4__MC_RESERVED6__REG DENALI_CTL_111
+#define LPDDR4__MC_RESERVED6__FLD LPDDR4__DENALI_CTL_111__MC_RESERVED6
+
+#define LPDDR4__DENALI_CTL_111__MC_RESERVED7_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_111__MC_RESERVED7_SHIFT 8U
+#define LPDDR4__DENALI_CTL_111__MC_RESERVED7_WIDTH 8U
+#define LPDDR4__MC_RESERVED7__REG DENALI_CTL_111
+#define LPDDR4__MC_RESERVED7__FLD LPDDR4__DENALI_CTL_111__MC_RESERVED7
+
+#define LPDDR4__DENALI_CTL_111__UPD_CTRLUPD_NORM_THRESHOLD_F0_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_111__UPD_CTRLUPD_NORM_THRESHOLD_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_111__UPD_CTRLUPD_NORM_THRESHOLD_F0_WIDTH 16U
+#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F0__REG DENALI_CTL_111
+#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_111__UPD_CTRLUPD_NORM_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_112_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_112_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_112__UPD_CTRLUPD_HIGH_THRESHOLD_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_112__UPD_CTRLUPD_HIGH_THRESHOLD_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_112__UPD_CTRLUPD_HIGH_THRESHOLD_F0_WIDTH 16U
+#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F0__REG DENALI_CTL_112
+#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_112__UPD_CTRLUPD_HIGH_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_112__UPD_CTRLUPD_TIMEOUT_F0_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_112__UPD_CTRLUPD_TIMEOUT_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_112__UPD_CTRLUPD_TIMEOUT_F0_WIDTH 16U
+#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F0__REG DENALI_CTL_112
+#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_112__UPD_CTRLUPD_TIMEOUT_F0
+
+#define LPDDR4__DENALI_CTL_113_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_113_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_113__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_113__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_113__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0_WIDTH 16U
+#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_113
+#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_113__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_113__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_113__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_113__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0_WIDTH 16U
+#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_113
+#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_113__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_114_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_114_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_114__UPD_CTRLUPD_NORM_THRESHOLD_F1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_114__UPD_CTRLUPD_NORM_THRESHOLD_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_114__UPD_CTRLUPD_NORM_THRESHOLD_F1_WIDTH 16U
+#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F1__REG DENALI_CTL_114
+#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_114__UPD_CTRLUPD_NORM_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_114__UPD_CTRLUPD_HIGH_THRESHOLD_F1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_114__UPD_CTRLUPD_HIGH_THRESHOLD_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_114__UPD_CTRLUPD_HIGH_THRESHOLD_F1_WIDTH 16U
+#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F1__REG DENALI_CTL_114
+#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_114__UPD_CTRLUPD_HIGH_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_115_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_115_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_115__UPD_CTRLUPD_TIMEOUT_F1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_115__UPD_CTRLUPD_TIMEOUT_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_115__UPD_CTRLUPD_TIMEOUT_F1_WIDTH 16U
+#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F1__REG DENALI_CTL_115
+#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_115__UPD_CTRLUPD_TIMEOUT_F1
+
+#define LPDDR4__DENALI_CTL_115__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_115__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_115__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1_WIDTH 16U
+#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_115
+#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_115__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_116_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_116_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_116__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_116__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_116__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1_WIDTH 16U
+#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_116
+#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_116__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_116__UPD_CTRLUPD_NORM_THRESHOLD_F2_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_116__UPD_CTRLUPD_NORM_THRESHOLD_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_116__UPD_CTRLUPD_NORM_THRESHOLD_F2_WIDTH 16U
+#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F2__REG DENALI_CTL_116
+#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_116__UPD_CTRLUPD_NORM_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_117_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_117_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_117__UPD_CTRLUPD_HIGH_THRESHOLD_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_117__UPD_CTRLUPD_HIGH_THRESHOLD_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_117__UPD_CTRLUPD_HIGH_THRESHOLD_F2_WIDTH 16U
+#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F2__REG DENALI_CTL_117
+#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_117__UPD_CTRLUPD_HIGH_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_117__UPD_CTRLUPD_TIMEOUT_F2_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_117__UPD_CTRLUPD_TIMEOUT_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_117__UPD_CTRLUPD_TIMEOUT_F2_WIDTH 16U
+#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F2__REG DENALI_CTL_117
+#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_117__UPD_CTRLUPD_TIMEOUT_F2
+
+#define LPDDR4__DENALI_CTL_118_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_118_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_118__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_118__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_118__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2_WIDTH 16U
+#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_118
+#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_118__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_118__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_118__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_118__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2_WIDTH 16U
+#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_118
+#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_118__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_119_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_119_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_119__TDFI_PHYMSTR_MAX_F0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_119__TDFI_PHYMSTR_MAX_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_119__TDFI_PHYMSTR_MAX_F0_WIDTH 32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_F0__REG DENALI_CTL_119
+#define LPDDR4__TDFI_PHYMSTR_MAX_F0__FLD LPDDR4__DENALI_CTL_119__TDFI_PHYMSTR_MAX_F0
+
+#define LPDDR4__DENALI_CTL_120_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_120_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_120__TDFI_PHYMSTR_MAX_TYPE0_F0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_120__TDFI_PHYMSTR_MAX_TYPE0_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_120__TDFI_PHYMSTR_MAX_TYPE0_F0_WIDTH 32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F0__REG DENALI_CTL_120
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F0__FLD LPDDR4__DENALI_CTL_120__TDFI_PHYMSTR_MAX_TYPE0_F0
+
+#define LPDDR4__DENALI_CTL_121_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_121_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_121__TDFI_PHYMSTR_MAX_TYPE1_F0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_121__TDFI_PHYMSTR_MAX_TYPE1_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_121__TDFI_PHYMSTR_MAX_TYPE1_F0_WIDTH 32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F0__REG DENALI_CTL_121
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F0__FLD LPDDR4__DENALI_CTL_121__TDFI_PHYMSTR_MAX_TYPE1_F0
+
+#define LPDDR4__DENALI_CTL_122_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_122_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_122__TDFI_PHYMSTR_MAX_TYPE2_F0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_122__TDFI_PHYMSTR_MAX_TYPE2_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_122__TDFI_PHYMSTR_MAX_TYPE2_F0_WIDTH 32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F0__REG DENALI_CTL_122
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F0__FLD LPDDR4__DENALI_CTL_122__TDFI_PHYMSTR_MAX_TYPE2_F0
+
+#define LPDDR4__DENALI_CTL_123_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_123_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_123__TDFI_PHYMSTR_MAX_TYPE3_F0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_123__TDFI_PHYMSTR_MAX_TYPE3_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_123__TDFI_PHYMSTR_MAX_TYPE3_F0_WIDTH 32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F0__REG DENALI_CTL_123
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F0__FLD LPDDR4__DENALI_CTL_123__TDFI_PHYMSTR_MAX_TYPE3_F0
+
+#define LPDDR4__DENALI_CTL_124_READ_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_124_WRITE_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_124__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_124__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_124__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0_WIDTH 16U
+#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_124
+#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_124__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_125_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_125_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_125__TDFI_PHYMSTR_RESP_F0_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_125__TDFI_PHYMSTR_RESP_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_125__TDFI_PHYMSTR_RESP_F0_WIDTH 20U
+#define LPDDR4__TDFI_PHYMSTR_RESP_F0__REG DENALI_CTL_125
+#define LPDDR4__TDFI_PHYMSTR_RESP_F0__FLD LPDDR4__DENALI_CTL_125__TDFI_PHYMSTR_RESP_F0
+
+#define LPDDR4__DENALI_CTL_126_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_126_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_126__TDFI_PHYMSTR_MAX_F1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_126__TDFI_PHYMSTR_MAX_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_126__TDFI_PHYMSTR_MAX_F1_WIDTH 32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_F1__REG DENALI_CTL_126
+#define LPDDR4__TDFI_PHYMSTR_MAX_F1__FLD LPDDR4__DENALI_CTL_126__TDFI_PHYMSTR_MAX_F1
+
+#define LPDDR4__DENALI_CTL_127_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_127_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_127__TDFI_PHYMSTR_MAX_TYPE0_F1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_127__TDFI_PHYMSTR_MAX_TYPE0_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_127__TDFI_PHYMSTR_MAX_TYPE0_F1_WIDTH 32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F1__REG DENALI_CTL_127
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F1__FLD LPDDR4__DENALI_CTL_127__TDFI_PHYMSTR_MAX_TYPE0_F1
+
+#define LPDDR4__DENALI_CTL_128_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_128_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_128__TDFI_PHYMSTR_MAX_TYPE1_F1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_128__TDFI_PHYMSTR_MAX_TYPE1_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_128__TDFI_PHYMSTR_MAX_TYPE1_F1_WIDTH 32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F1__REG DENALI_CTL_128
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F1__FLD LPDDR4__DENALI_CTL_128__TDFI_PHYMSTR_MAX_TYPE1_F1
+
+#define LPDDR4__DENALI_CTL_129_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_129_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_129__TDFI_PHYMSTR_MAX_TYPE2_F1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_129__TDFI_PHYMSTR_MAX_TYPE2_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_129__TDFI_PHYMSTR_MAX_TYPE2_F1_WIDTH 32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F1__REG DENALI_CTL_129
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F1__FLD LPDDR4__DENALI_CTL_129__TDFI_PHYMSTR_MAX_TYPE2_F1
+
+#define LPDDR4__DENALI_CTL_130_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_130_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_130__TDFI_PHYMSTR_MAX_TYPE3_F1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_130__TDFI_PHYMSTR_MAX_TYPE3_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_130__TDFI_PHYMSTR_MAX_TYPE3_F1_WIDTH 32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F1__REG DENALI_CTL_130
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F1__FLD LPDDR4__DENALI_CTL_130__TDFI_PHYMSTR_MAX_TYPE3_F1
+
+#define LPDDR4__DENALI_CTL_131_READ_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_131_WRITE_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_131__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_131__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_131__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1_WIDTH 16U
+#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_131
+#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_131__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_132_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_132_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_132__TDFI_PHYMSTR_RESP_F1_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_132__TDFI_PHYMSTR_RESP_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_132__TDFI_PHYMSTR_RESP_F1_WIDTH 20U
+#define LPDDR4__TDFI_PHYMSTR_RESP_F1__REG DENALI_CTL_132
+#define LPDDR4__TDFI_PHYMSTR_RESP_F1__FLD LPDDR4__DENALI_CTL_132__TDFI_PHYMSTR_RESP_F1
+
+#define LPDDR4__DENALI_CTL_133_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_133_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_133__TDFI_PHYMSTR_MAX_F2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_133__TDFI_PHYMSTR_MAX_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_133__TDFI_PHYMSTR_MAX_F2_WIDTH 32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_F2__REG DENALI_CTL_133
+#define LPDDR4__TDFI_PHYMSTR_MAX_F2__FLD LPDDR4__DENALI_CTL_133__TDFI_PHYMSTR_MAX_F2
+
+#define LPDDR4__DENALI_CTL_134_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_134_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_134__TDFI_PHYMSTR_MAX_TYPE0_F2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_134__TDFI_PHYMSTR_MAX_TYPE0_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_134__TDFI_PHYMSTR_MAX_TYPE0_F2_WIDTH 32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F2__REG DENALI_CTL_134
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F2__FLD LPDDR4__DENALI_CTL_134__TDFI_PHYMSTR_MAX_TYPE0_F2
+
+#define LPDDR4__DENALI_CTL_135_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_135_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_135__TDFI_PHYMSTR_MAX_TYPE1_F2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_135__TDFI_PHYMSTR_MAX_TYPE1_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_135__TDFI_PHYMSTR_MAX_TYPE1_F2_WIDTH 32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F2__REG DENALI_CTL_135
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F2__FLD LPDDR4__DENALI_CTL_135__TDFI_PHYMSTR_MAX_TYPE1_F2
+
+#define LPDDR4__DENALI_CTL_136_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_136_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_136__TDFI_PHYMSTR_MAX_TYPE2_F2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_136__TDFI_PHYMSTR_MAX_TYPE2_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_136__TDFI_PHYMSTR_MAX_TYPE2_F2_WIDTH 32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F2__REG DENALI_CTL_136
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F2__FLD LPDDR4__DENALI_CTL_136__TDFI_PHYMSTR_MAX_TYPE2_F2
+
+#define LPDDR4__DENALI_CTL_137_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_137_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_137__TDFI_PHYMSTR_MAX_TYPE3_F2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_137__TDFI_PHYMSTR_MAX_TYPE3_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_137__TDFI_PHYMSTR_MAX_TYPE3_F2_WIDTH 32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F2__REG DENALI_CTL_137
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F2__FLD LPDDR4__DENALI_CTL_137__TDFI_PHYMSTR_MAX_TYPE3_F2
+
+#define LPDDR4__DENALI_CTL_138_READ_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_138_WRITE_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_138__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_138__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_138__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2_WIDTH 16U
+#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_138
+#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_138__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_139_READ_MASK 0x010FFFFFU
+#define LPDDR4__DENALI_CTL_139_WRITE_MASK 0x010FFFFFU
+#define LPDDR4__DENALI_CTL_139__TDFI_PHYMSTR_RESP_F2_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_139__TDFI_PHYMSTR_RESP_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_139__TDFI_PHYMSTR_RESP_F2_WIDTH 20U
+#define LPDDR4__TDFI_PHYMSTR_RESP_F2__REG DENALI_CTL_139
+#define LPDDR4__TDFI_PHYMSTR_RESP_F2__FLD LPDDR4__DENALI_CTL_139__TDFI_PHYMSTR_RESP_F2
+
+#define LPDDR4__DENALI_CTL_139__PHYMSTR_NO_AREF_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_139__PHYMSTR_NO_AREF_SHIFT 24U
+#define LPDDR4__DENALI_CTL_139__PHYMSTR_NO_AREF_WIDTH 1U
+#define LPDDR4__DENALI_CTL_139__PHYMSTR_NO_AREF_WOCLR 0U
+#define LPDDR4__DENALI_CTL_139__PHYMSTR_NO_AREF_WOSET 0U
+#define LPDDR4__PHYMSTR_NO_AREF__REG DENALI_CTL_139
+#define LPDDR4__PHYMSTR_NO_AREF__FLD LPDDR4__DENALI_CTL_139__PHYMSTR_NO_AREF
+
+#define LPDDR4__DENALI_CTL_140_READ_MASK 0x00010103U
+#define LPDDR4__DENALI_CTL_140_WRITE_MASK 0x00010103U
+#define LPDDR4__DENALI_CTL_140__PHYMSTR_ERROR_STATUS_MASK 0x00000003U
+#define LPDDR4__DENALI_CTL_140__PHYMSTR_ERROR_STATUS_SHIFT 0U
+#define LPDDR4__DENALI_CTL_140__PHYMSTR_ERROR_STATUS_WIDTH 2U
+#define LPDDR4__PHYMSTR_ERROR_STATUS__REG DENALI_CTL_140
+#define LPDDR4__PHYMSTR_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_140__PHYMSTR_ERROR_STATUS
+
+#define LPDDR4__DENALI_CTL_140__PHYMSTR_DFI_VERSION_4P0V1_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_140__PHYMSTR_DFI_VERSION_4P0V1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_140__PHYMSTR_DFI_VERSION_4P0V1_WIDTH 1U
+#define LPDDR4__DENALI_CTL_140__PHYMSTR_DFI_VERSION_4P0V1_WOCLR 0U
+#define LPDDR4__DENALI_CTL_140__PHYMSTR_DFI_VERSION_4P0V1_WOSET 0U
+#define LPDDR4__PHYMSTR_DFI_VERSION_4P0V1__REG DENALI_CTL_140
+#define LPDDR4__PHYMSTR_DFI_VERSION_4P0V1__FLD LPDDR4__DENALI_CTL_140__PHYMSTR_DFI_VERSION_4P0V1
+
+#define LPDDR4__DENALI_CTL_140__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_140__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_SHIFT 16U
+#define LPDDR4__DENALI_CTL_140__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_WIDTH 1U
+#define LPDDR4__DENALI_CTL_140__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_WOCLR 0U
+#define LPDDR4__DENALI_CTL_140__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_WOSET 0U
+#define LPDDR4__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE__REG DENALI_CTL_140
+#define LPDDR4__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE__FLD LPDDR4__DENALI_CTL_140__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE
+
+#define LPDDR4__DENALI_CTL_141_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_141_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_141__MRR_TEMPCHK_NORM_THRESHOLD_F0_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_141__MRR_TEMPCHK_NORM_THRESHOLD_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_141__MRR_TEMPCHK_NORM_THRESHOLD_F0_WIDTH 24U
+#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F0__REG DENALI_CTL_141
+#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_141__MRR_TEMPCHK_NORM_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_142_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_142_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_142__MRR_TEMPCHK_HIGH_THRESHOLD_F0_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_142__MRR_TEMPCHK_HIGH_THRESHOLD_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_142__MRR_TEMPCHK_HIGH_THRESHOLD_F0_WIDTH 24U
+#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F0__REG DENALI_CTL_142
+#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_142__MRR_TEMPCHK_HIGH_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_143_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_143_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_143__MRR_TEMPCHK_TIMEOUT_F0_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_143__MRR_TEMPCHK_TIMEOUT_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_143__MRR_TEMPCHK_TIMEOUT_F0_WIDTH 24U
+#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F0__REG DENALI_CTL_143
+#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_143__MRR_TEMPCHK_TIMEOUT_F0
+
+#define LPDDR4__DENALI_CTL_144_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_144_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_144__MRR_TEMPCHK_NORM_THRESHOLD_F1_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_144__MRR_TEMPCHK_NORM_THRESHOLD_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_144__MRR_TEMPCHK_NORM_THRESHOLD_F1_WIDTH 24U
+#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F1__REG DENALI_CTL_144
+#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_144__MRR_TEMPCHK_NORM_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_145_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_145_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_145__MRR_TEMPCHK_HIGH_THRESHOLD_F1_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_145__MRR_TEMPCHK_HIGH_THRESHOLD_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_145__MRR_TEMPCHK_HIGH_THRESHOLD_F1_WIDTH 24U
+#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F1__REG DENALI_CTL_145
+#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_145__MRR_TEMPCHK_HIGH_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_146_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_146_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_146__MRR_TEMPCHK_TIMEOUT_F1_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_146__MRR_TEMPCHK_TIMEOUT_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_146__MRR_TEMPCHK_TIMEOUT_F1_WIDTH 24U
+#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F1__REG DENALI_CTL_146
+#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_146__MRR_TEMPCHK_TIMEOUT_F1
+
+#define LPDDR4__DENALI_CTL_147_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_147_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_147__MRR_TEMPCHK_NORM_THRESHOLD_F2_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_147__MRR_TEMPCHK_NORM_THRESHOLD_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_147__MRR_TEMPCHK_NORM_THRESHOLD_F2_WIDTH 24U
+#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F2__REG DENALI_CTL_147
+#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_147__MRR_TEMPCHK_NORM_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_148_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_148_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_148__MRR_TEMPCHK_HIGH_THRESHOLD_F2_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_148__MRR_TEMPCHK_HIGH_THRESHOLD_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_148__MRR_TEMPCHK_HIGH_THRESHOLD_F2_WIDTH 24U
+#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F2__REG DENALI_CTL_148
+#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_148__MRR_TEMPCHK_HIGH_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_149_READ_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_149_WRITE_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_149__MRR_TEMPCHK_TIMEOUT_F2_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_149__MRR_TEMPCHK_TIMEOUT_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_149__MRR_TEMPCHK_TIMEOUT_F2_WIDTH 24U
+#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F2__REG DENALI_CTL_149
+#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_149__MRR_TEMPCHK_TIMEOUT_F2
+
+#define LPDDR4__DENALI_CTL_149__PPR_CONTROL_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_149__PPR_CONTROL_SHIFT 24U
+#define LPDDR4__DENALI_CTL_149__PPR_CONTROL_WIDTH 1U
+#define LPDDR4__DENALI_CTL_149__PPR_CONTROL_WOCLR 0U
+#define LPDDR4__DENALI_CTL_149__PPR_CONTROL_WOSET 0U
+#define LPDDR4__PPR_CONTROL__REG DENALI_CTL_149
+#define LPDDR4__PPR_CONTROL__FLD LPDDR4__DENALI_CTL_149__PPR_CONTROL
+
+#define LPDDR4__DENALI_CTL_150_READ_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_150_WRITE_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_150__PPR_COMMAND_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_150__PPR_COMMAND_SHIFT 0U
+#define LPDDR4__DENALI_CTL_150__PPR_COMMAND_WIDTH 3U
+#define LPDDR4__PPR_COMMAND__REG DENALI_CTL_150
+#define LPDDR4__PPR_COMMAND__FLD LPDDR4__DENALI_CTL_150__PPR_COMMAND
+
+#define LPDDR4__DENALI_CTL_150__PPR_COMMAND_MRW_REGNUM_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_150__PPR_COMMAND_MRW_REGNUM_SHIFT 8U
+#define LPDDR4__DENALI_CTL_150__PPR_COMMAND_MRW_REGNUM_WIDTH 8U
+#define LPDDR4__PPR_COMMAND_MRW_REGNUM__REG DENALI_CTL_150
+#define LPDDR4__PPR_COMMAND_MRW_REGNUM__FLD LPDDR4__DENALI_CTL_150__PPR_COMMAND_MRW_REGNUM
+
+#define LPDDR4__DENALI_CTL_151_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_151_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_151__PPR_COMMAND_MRW_DATA_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_151__PPR_COMMAND_MRW_DATA_SHIFT 0U
+#define LPDDR4__DENALI_CTL_151__PPR_COMMAND_MRW_DATA_WIDTH 17U
+#define LPDDR4__PPR_COMMAND_MRW_DATA__REG DENALI_CTL_151
+#define LPDDR4__PPR_COMMAND_MRW_DATA__FLD LPDDR4__DENALI_CTL_151__PPR_COMMAND_MRW_DATA
+
+#define LPDDR4__DENALI_CTL_152_READ_MASK 0x0F03FFFFU
+#define LPDDR4__DENALI_CTL_152_WRITE_MASK 0x0F03FFFFU
+#define LPDDR4__DENALI_CTL_152__PPR_ROW_ADDRESS_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_CTL_152__PPR_ROW_ADDRESS_SHIFT 0U
+#define LPDDR4__DENALI_CTL_152__PPR_ROW_ADDRESS_WIDTH 18U
+#define LPDDR4__PPR_ROW_ADDRESS__REG DENALI_CTL_152
+#define LPDDR4__PPR_ROW_ADDRESS__FLD LPDDR4__DENALI_CTL_152__PPR_ROW_ADDRESS
+
+#define LPDDR4__DENALI_CTL_152__PPR_BANK_ADDRESS_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_152__PPR_BANK_ADDRESS_SHIFT 24U
+#define LPDDR4__DENALI_CTL_152__PPR_BANK_ADDRESS_WIDTH 4U
+#define LPDDR4__PPR_BANK_ADDRESS__REG DENALI_CTL_152
+#define LPDDR4__PPR_BANK_ADDRESS__FLD LPDDR4__DENALI_CTL_152__PPR_BANK_ADDRESS
+
+#define LPDDR4__DENALI_CTL_153_READ_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_153_WRITE_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_153__PPR_CS_ADDRESS_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_153__PPR_CS_ADDRESS_SHIFT 0U
+#define LPDDR4__DENALI_CTL_153__PPR_CS_ADDRESS_WIDTH 1U
+#define LPDDR4__DENALI_CTL_153__PPR_CS_ADDRESS_WOCLR 0U
+#define LPDDR4__DENALI_CTL_153__PPR_CS_ADDRESS_WOSET 0U
+#define LPDDR4__PPR_CS_ADDRESS__REG DENALI_CTL_153
+#define LPDDR4__PPR_CS_ADDRESS__FLD LPDDR4__DENALI_CTL_153__PPR_CS_ADDRESS
+
+#define LPDDR4__DENALI_CTL_154_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_154_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_154__PPR_DATA_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_154__PPR_DATA_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_154__PPR_DATA_0_WIDTH 32U
+#define LPDDR4__PPR_DATA_0__REG DENALI_CTL_154
+#define LPDDR4__PPR_DATA_0__FLD LPDDR4__DENALI_CTL_154__PPR_DATA_0
+
+#define LPDDR4__DENALI_CTL_155_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_155_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_155__PPR_DATA_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_155__PPR_DATA_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_155__PPR_DATA_1_WIDTH 32U
+#define LPDDR4__PPR_DATA_1__REG DENALI_CTL_155
+#define LPDDR4__PPR_DATA_1__FLD LPDDR4__DENALI_CTL_155__PPR_DATA_1
+
+#define LPDDR4__DENALI_CTL_156_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_156_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_156__PPR_DATA_2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_156__PPR_DATA_2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_156__PPR_DATA_2_WIDTH 32U
+#define LPDDR4__PPR_DATA_2__REG DENALI_CTL_156
+#define LPDDR4__PPR_DATA_2__FLD LPDDR4__DENALI_CTL_156__PPR_DATA_2
+
+#define LPDDR4__DENALI_CTL_157_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_157_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_157__PPR_DATA_3_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_157__PPR_DATA_3_SHIFT 0U
+#define LPDDR4__DENALI_CTL_157__PPR_DATA_3_WIDTH 32U
+#define LPDDR4__PPR_DATA_3__REG DENALI_CTL_157
+#define LPDDR4__PPR_DATA_3__FLD LPDDR4__DENALI_CTL_157__PPR_DATA_3
+
+#define LPDDR4__DENALI_CTL_158_READ_MASK 0xFFFF0103U
+#define LPDDR4__DENALI_CTL_158_WRITE_MASK 0xFFFF0103U
+#define LPDDR4__DENALI_CTL_158__PPR_STATUS_MASK 0x00000003U
+#define LPDDR4__DENALI_CTL_158__PPR_STATUS_SHIFT 0U
+#define LPDDR4__DENALI_CTL_158__PPR_STATUS_WIDTH 2U
+#define LPDDR4__PPR_STATUS__REG DENALI_CTL_158
+#define LPDDR4__PPR_STATUS__FLD LPDDR4__DENALI_CTL_158__PPR_STATUS
+
+#define LPDDR4__DENALI_CTL_158__FM_OVRIDE_CONTROL_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_158__FM_OVRIDE_CONTROL_SHIFT 8U
+#define LPDDR4__DENALI_CTL_158__FM_OVRIDE_CONTROL_WIDTH 1U
+#define LPDDR4__DENALI_CTL_158__FM_OVRIDE_CONTROL_WOCLR 0U
+#define LPDDR4__DENALI_CTL_158__FM_OVRIDE_CONTROL_WOSET 0U
+#define LPDDR4__FM_OVRIDE_CONTROL__REG DENALI_CTL_158
+#define LPDDR4__FM_OVRIDE_CONTROL__FLD LPDDR4__DENALI_CTL_158__FM_OVRIDE_CONTROL
+
+#define LPDDR4__DENALI_CTL_158__CKSRE_F0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_158__CKSRE_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_158__CKSRE_F0_WIDTH 8U
+#define LPDDR4__CKSRE_F0__REG DENALI_CTL_158
+#define LPDDR4__CKSRE_F0__FLD LPDDR4__DENALI_CTL_158__CKSRE_F0
+
+#define LPDDR4__DENALI_CTL_158__CKSRX_F0_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_158__CKSRX_F0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_158__CKSRX_F0_WIDTH 8U
+#define LPDDR4__CKSRX_F0__REG DENALI_CTL_158
+#define LPDDR4__CKSRX_F0__FLD LPDDR4__DENALI_CTL_158__CKSRX_F0
+
+#define LPDDR4__DENALI_CTL_159_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_159_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_159__CKSRE_F1_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_159__CKSRE_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_159__CKSRE_F1_WIDTH 8U
+#define LPDDR4__CKSRE_F1__REG DENALI_CTL_159
+#define LPDDR4__CKSRE_F1__FLD LPDDR4__DENALI_CTL_159__CKSRE_F1
+
+#define LPDDR4__DENALI_CTL_159__CKSRX_F1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_159__CKSRX_F1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_159__CKSRX_F1_WIDTH 8U
+#define LPDDR4__CKSRX_F1__REG DENALI_CTL_159
+#define LPDDR4__CKSRX_F1__FLD LPDDR4__DENALI_CTL_159__CKSRX_F1
+
+#define LPDDR4__DENALI_CTL_159__CKSRE_F2_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_159__CKSRE_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_159__CKSRE_F2_WIDTH 8U
+#define LPDDR4__CKSRE_F2__REG DENALI_CTL_159
+#define LPDDR4__CKSRE_F2__FLD LPDDR4__DENALI_CTL_159__CKSRE_F2
+
+#define LPDDR4__DENALI_CTL_159__CKSRX_F2_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_159__CKSRX_F2_SHIFT 24U
+#define LPDDR4__DENALI_CTL_159__CKSRX_F2_WIDTH 8U
+#define LPDDR4__CKSRX_F2__REG DENALI_CTL_159
+#define LPDDR4__CKSRX_F2__FLD LPDDR4__DENALI_CTL_159__CKSRX_F2
+
+#define LPDDR4__DENALI_CTL_160_READ_MASK 0x0F0F0003U
+#define LPDDR4__DENALI_CTL_160_WRITE_MASK 0x0F0F0003U
+#define LPDDR4__DENALI_CTL_160__LOWPOWER_REFRESH_ENABLE_MASK 0x00000003U
+#define LPDDR4__DENALI_CTL_160__LOWPOWER_REFRESH_ENABLE_SHIFT 0U
+#define LPDDR4__DENALI_CTL_160__LOWPOWER_REFRESH_ENABLE_WIDTH 2U
+#define LPDDR4__LOWPOWER_REFRESH_ENABLE__REG DENALI_CTL_160
+#define LPDDR4__LOWPOWER_REFRESH_ENABLE__FLD LPDDR4__DENALI_CTL_160__LOWPOWER_REFRESH_ENABLE
+
+#define LPDDR4__DENALI_CTL_160__LP_CMD_MASK 0x00007F00U
+#define LPDDR4__DENALI_CTL_160__LP_CMD_SHIFT 8U
+#define LPDDR4__DENALI_CTL_160__LP_CMD_WIDTH 7U
+#define LPDDR4__LP_CMD__REG DENALI_CTL_160
+#define LPDDR4__LP_CMD__FLD LPDDR4__DENALI_CTL_160__LP_CMD
+
+#define LPDDR4__DENALI_CTL_160__LPI_IDLE_WAKEUP_F0_MASK 0x000F0000U
+#define LPDDR4__DENALI_CTL_160__LPI_IDLE_WAKEUP_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_160__LPI_IDLE_WAKEUP_F0_WIDTH 4U
+#define LPDDR4__LPI_IDLE_WAKEUP_F0__REG DENALI_CTL_160
+#define LPDDR4__LPI_IDLE_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_160__LPI_IDLE_WAKEUP_F0
+
+#define LPDDR4__DENALI_CTL_160__LPI_SR_SHORT_WAKEUP_F0_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_160__LPI_SR_SHORT_WAKEUP_F0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_160__LPI_SR_SHORT_WAKEUP_F0_WIDTH 4U
+#define LPDDR4__LPI_SR_SHORT_WAKEUP_F0__REG DENALI_CTL_160
+#define LPDDR4__LPI_SR_SHORT_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_160__LPI_SR_SHORT_WAKEUP_F0
+
+#define LPDDR4__DENALI_CTL_161_READ_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_161_WRITE_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_161__LPI_SR_LONG_WAKEUP_F0_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_161__LPI_SR_LONG_WAKEUP_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_161__LPI_SR_LONG_WAKEUP_F0_WIDTH 4U
+#define LPDDR4__LPI_SR_LONG_WAKEUP_F0__REG DENALI_CTL_161
+#define LPDDR4__LPI_SR_LONG_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_161__LPI_SR_LONG_WAKEUP_F0
+
+#define LPDDR4__DENALI_CTL_161__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0_MASK 0x00000F00U
+#define LPDDR4__DENALI_CTL_161__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_161__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0_WIDTH 4U
+#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__REG DENALI_CTL_161
+#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_161__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0
+
+#define LPDDR4__DENALI_CTL_161__LPI_PD_WAKEUP_F0_MASK 0x000F0000U
+#define LPDDR4__DENALI_CTL_161__LPI_PD_WAKEUP_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_161__LPI_PD_WAKEUP_F0_WIDTH 4U
+#define LPDDR4__LPI_PD_WAKEUP_F0__REG DENALI_CTL_161
+#define LPDDR4__LPI_PD_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_161__LPI_PD_WAKEUP_F0
+
+#define LPDDR4__DENALI_CTL_161__LPI_SRPD_SHORT_WAKEUP_F0_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_161__LPI_SRPD_SHORT_WAKEUP_F0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_161__LPI_SRPD_SHORT_WAKEUP_F0_WIDTH 4U
+#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__REG DENALI_CTL_161
+#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_161__LPI_SRPD_SHORT_WAKEUP_F0
+
+#define LPDDR4__DENALI_CTL_162_READ_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_162_WRITE_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_162__LPI_SRPD_LONG_WAKEUP_F0_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_162__LPI_SRPD_LONG_WAKEUP_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_162__LPI_SRPD_LONG_WAKEUP_F0_WIDTH 4U
+#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__REG DENALI_CTL_162
+#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_162__LPI_SRPD_LONG_WAKEUP_F0
+
+#define LPDDR4__DENALI_CTL_162__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0_MASK 0x00000F00U
+#define LPDDR4__DENALI_CTL_162__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_162__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0_WIDTH 4U
+#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__REG DENALI_CTL_162
+#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_162__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0
+
+#define LPDDR4__DENALI_CTL_162__LPI_TIMER_WAKEUP_F0_MASK 0x000F0000U
+#define LPDDR4__DENALI_CTL_162__LPI_TIMER_WAKEUP_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_162__LPI_TIMER_WAKEUP_F0_WIDTH 4U
+#define LPDDR4__LPI_TIMER_WAKEUP_F0__REG DENALI_CTL_162
+#define LPDDR4__LPI_TIMER_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_162__LPI_TIMER_WAKEUP_F0
+
+#define LPDDR4__DENALI_CTL_162__LPI_IDLE_WAKEUP_F1_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_162__LPI_IDLE_WAKEUP_F1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_162__LPI_IDLE_WAKEUP_F1_WIDTH 4U
+#define LPDDR4__LPI_IDLE_WAKEUP_F1__REG DENALI_CTL_162
+#define LPDDR4__LPI_IDLE_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_162__LPI_IDLE_WAKEUP_F1
+
+#define LPDDR4__DENALI_CTL_163_READ_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_163_WRITE_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_163__LPI_SR_SHORT_WAKEUP_F1_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_163__LPI_SR_SHORT_WAKEUP_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_163__LPI_SR_SHORT_WAKEUP_F1_WIDTH 4U
+#define LPDDR4__LPI_SR_SHORT_WAKEUP_F1__REG DENALI_CTL_163
+#define LPDDR4__LPI_SR_SHORT_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_163__LPI_SR_SHORT_WAKEUP_F1
+
+#define LPDDR4__DENALI_CTL_163__LPI_SR_LONG_WAKEUP_F1_MASK 0x00000F00U
+#define LPDDR4__DENALI_CTL_163__LPI_SR_LONG_WAKEUP_F1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_163__LPI_SR_LONG_WAKEUP_F1_WIDTH 4U
+#define LPDDR4__LPI_SR_LONG_WAKEUP_F1__REG DENALI_CTL_163
+#define LPDDR4__LPI_SR_LONG_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_163__LPI_SR_LONG_WAKEUP_F1
+
+#define LPDDR4__DENALI_CTL_163__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1_MASK 0x000F0000U
+#define LPDDR4__DENALI_CTL_163__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_163__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1_WIDTH 4U
+#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__REG DENALI_CTL_163
+#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_163__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1
+
+#define LPDDR4__DENALI_CTL_163__LPI_PD_WAKEUP_F1_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_163__LPI_PD_WAKEUP_F1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_163__LPI_PD_WAKEUP_F1_WIDTH 4U
+#define LPDDR4__LPI_PD_WAKEUP_F1__REG DENALI_CTL_163
+#define LPDDR4__LPI_PD_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_163__LPI_PD_WAKEUP_F1
+
+#define LPDDR4__DENALI_CTL_164_READ_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_164_WRITE_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_164__LPI_SRPD_SHORT_WAKEUP_F1_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_164__LPI_SRPD_SHORT_WAKEUP_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_164__LPI_SRPD_SHORT_WAKEUP_F1_WIDTH 4U
+#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__REG DENALI_CTL_164
+#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_164__LPI_SRPD_SHORT_WAKEUP_F1
+
+#define LPDDR4__DENALI_CTL_164__LPI_SRPD_LONG_WAKEUP_F1_MASK 0x00000F00U
+#define LPDDR4__DENALI_CTL_164__LPI_SRPD_LONG_WAKEUP_F1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_164__LPI_SRPD_LONG_WAKEUP_F1_WIDTH 4U
+#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__REG DENALI_CTL_164
+#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_164__LPI_SRPD_LONG_WAKEUP_F1
+
+#define LPDDR4__DENALI_CTL_164__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1_MASK 0x000F0000U
+#define LPDDR4__DENALI_CTL_164__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_164__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1_WIDTH 4U
+#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__REG DENALI_CTL_164
+#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_164__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1
+
+#define LPDDR4__DENALI_CTL_164__LPI_TIMER_WAKEUP_F1_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_164__LPI_TIMER_WAKEUP_F1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_164__LPI_TIMER_WAKEUP_F1_WIDTH 4U
+#define LPDDR4__LPI_TIMER_WAKEUP_F1__REG DENALI_CTL_164
+#define LPDDR4__LPI_TIMER_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_164__LPI_TIMER_WAKEUP_F1
+
+#define LPDDR4__DENALI_CTL_165_READ_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_165_WRITE_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_165__LPI_IDLE_WAKEUP_F2_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_165__LPI_IDLE_WAKEUP_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_165__LPI_IDLE_WAKEUP_F2_WIDTH 4U
+#define LPDDR4__LPI_IDLE_WAKEUP_F2__REG DENALI_CTL_165
+#define LPDDR4__LPI_IDLE_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_165__LPI_IDLE_WAKEUP_F2
+
+#define LPDDR4__DENALI_CTL_165__LPI_SR_SHORT_WAKEUP_F2_MASK 0x00000F00U
+#define LPDDR4__DENALI_CTL_165__LPI_SR_SHORT_WAKEUP_F2_SHIFT 8U
+#define LPDDR4__DENALI_CTL_165__LPI_SR_SHORT_WAKEUP_F2_WIDTH 4U
+#define LPDDR4__LPI_SR_SHORT_WAKEUP_F2__REG DENALI_CTL_165
+#define LPDDR4__LPI_SR_SHORT_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_165__LPI_SR_SHORT_WAKEUP_F2
+
+#define LPDDR4__DENALI_CTL_165__LPI_SR_LONG_WAKEUP_F2_MASK 0x000F0000U
+#define LPDDR4__DENALI_CTL_165__LPI_SR_LONG_WAKEUP_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_165__LPI_SR_LONG_WAKEUP_F2_WIDTH 4U
+#define LPDDR4__LPI_SR_LONG_WAKEUP_F2__REG DENALI_CTL_165
+#define LPDDR4__LPI_SR_LONG_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_165__LPI_SR_LONG_WAKEUP_F2
+
+#define LPDDR4__DENALI_CTL_165__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_165__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2_SHIFT 24U
+#define LPDDR4__DENALI_CTL_165__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2_WIDTH 4U
+#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__REG DENALI_CTL_165
+#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_165__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2
+
+#define LPDDR4__DENALI_CTL_166_READ_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_166_WRITE_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_166__LPI_PD_WAKEUP_F2_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_166__LPI_PD_WAKEUP_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_166__LPI_PD_WAKEUP_F2_WIDTH 4U
+#define LPDDR4__LPI_PD_WAKEUP_F2__REG DENALI_CTL_166
+#define LPDDR4__LPI_PD_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_166__LPI_PD_WAKEUP_F2
+
+#define LPDDR4__DENALI_CTL_166__LPI_SRPD_SHORT_WAKEUP_F2_MASK 0x00000F00U
+#define LPDDR4__DENALI_CTL_166__LPI_SRPD_SHORT_WAKEUP_F2_SHIFT 8U
+#define LPDDR4__DENALI_CTL_166__LPI_SRPD_SHORT_WAKEUP_F2_WIDTH 4U
+#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__REG DENALI_CTL_166
+#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_166__LPI_SRPD_SHORT_WAKEUP_F2
+
+#define LPDDR4__DENALI_CTL_166__LPI_SRPD_LONG_WAKEUP_F2_MASK 0x000F0000U
+#define LPDDR4__DENALI_CTL_166__LPI_SRPD_LONG_WAKEUP_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_166__LPI_SRPD_LONG_WAKEUP_F2_WIDTH 4U
+#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__REG DENALI_CTL_166
+#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_166__LPI_SRPD_LONG_WAKEUP_F2
+
+#define LPDDR4__DENALI_CTL_166__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_166__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2_SHIFT 24U
+#define LPDDR4__DENALI_CTL_166__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2_WIDTH 4U
+#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__REG DENALI_CTL_166
+#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_166__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2
+
+#define LPDDR4__DENALI_CTL_167_READ_MASK 0x00013F0FU
+#define LPDDR4__DENALI_CTL_167_WRITE_MASK 0x00013F0FU
+#define LPDDR4__DENALI_CTL_167__LPI_TIMER_WAKEUP_F2_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_167__LPI_TIMER_WAKEUP_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_167__LPI_TIMER_WAKEUP_F2_WIDTH 4U
+#define LPDDR4__LPI_TIMER_WAKEUP_F2__REG DENALI_CTL_167
+#define LPDDR4__LPI_TIMER_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_167__LPI_TIMER_WAKEUP_F2
+
+#define LPDDR4__DENALI_CTL_167__LPI_WAKEUP_EN_MASK 0x00003F00U
+#define LPDDR4__DENALI_CTL_167__LPI_WAKEUP_EN_SHIFT 8U
+#define LPDDR4__DENALI_CTL_167__LPI_WAKEUP_EN_WIDTH 6U
+#define LPDDR4__LPI_WAKEUP_EN__REG DENALI_CTL_167
+#define LPDDR4__LPI_WAKEUP_EN__FLD LPDDR4__DENALI_CTL_167__LPI_WAKEUP_EN
+
+#define LPDDR4__DENALI_CTL_167__LPI_CTRL_REQ_EN_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_167__LPI_CTRL_REQ_EN_SHIFT 16U
+#define LPDDR4__DENALI_CTL_167__LPI_CTRL_REQ_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_167__LPI_CTRL_REQ_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_167__LPI_CTRL_REQ_EN_WOSET 0U
+#define LPDDR4__LPI_CTRL_REQ_EN__REG DENALI_CTL_167
+#define LPDDR4__LPI_CTRL_REQ_EN__FLD LPDDR4__DENALI_CTL_167__LPI_CTRL_REQ_EN
+
+#define LPDDR4__DENALI_CTL_168_READ_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_168_WRITE_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_168__LPI_TIMER_COUNT_MASK 0x00000FFFU
+#define LPDDR4__DENALI_CTL_168__LPI_TIMER_COUNT_SHIFT 0U
+#define LPDDR4__DENALI_CTL_168__LPI_TIMER_COUNT_WIDTH 12U
+#define LPDDR4__LPI_TIMER_COUNT__REG DENALI_CTL_168
+#define LPDDR4__LPI_TIMER_COUNT__FLD LPDDR4__DENALI_CTL_168__LPI_TIMER_COUNT
+
+#define LPDDR4__DENALI_CTL_168__LPI_WAKEUP_TIMEOUT_MASK 0x0FFF0000U
+#define LPDDR4__DENALI_CTL_168__LPI_WAKEUP_TIMEOUT_SHIFT 16U
+#define LPDDR4__DENALI_CTL_168__LPI_WAKEUP_TIMEOUT_WIDTH 12U
+#define LPDDR4__LPI_WAKEUP_TIMEOUT__REG DENALI_CTL_168
+#define LPDDR4__LPI_WAKEUP_TIMEOUT__FLD LPDDR4__DENALI_CTL_168__LPI_WAKEUP_TIMEOUT
+
+#define LPDDR4__DENALI_CTL_169_READ_MASK 0x0F0F7F07U
+#define LPDDR4__DENALI_CTL_169_WRITE_MASK 0x0F0F7F07U
+#define LPDDR4__DENALI_CTL_169__TDFI_LP_RESP_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_169__TDFI_LP_RESP_SHIFT 0U
+#define LPDDR4__DENALI_CTL_169__TDFI_LP_RESP_WIDTH 3U
+#define LPDDR4__TDFI_LP_RESP__REG DENALI_CTL_169
+#define LPDDR4__TDFI_LP_RESP__FLD LPDDR4__DENALI_CTL_169__TDFI_LP_RESP
+
+#define LPDDR4__DENALI_CTL_169__LP_STATE_MASK 0x00007F00U
+#define LPDDR4__DENALI_CTL_169__LP_STATE_SHIFT 8U
+#define LPDDR4__DENALI_CTL_169__LP_STATE_WIDTH 7U
+#define LPDDR4__LP_STATE__REG DENALI_CTL_169
+#define LPDDR4__LP_STATE__FLD LPDDR4__DENALI_CTL_169__LP_STATE
+
+#define LPDDR4__DENALI_CTL_169__LP_AUTO_ENTRY_EN_MASK 0x000F0000U
+#define LPDDR4__DENALI_CTL_169__LP_AUTO_ENTRY_EN_SHIFT 16U
+#define LPDDR4__DENALI_CTL_169__LP_AUTO_ENTRY_EN_WIDTH 4U
+#define LPDDR4__LP_AUTO_ENTRY_EN__REG DENALI_CTL_169
+#define LPDDR4__LP_AUTO_ENTRY_EN__FLD LPDDR4__DENALI_CTL_169__LP_AUTO_ENTRY_EN
+
+#define LPDDR4__DENALI_CTL_169__LP_AUTO_EXIT_EN_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_169__LP_AUTO_EXIT_EN_SHIFT 24U
+#define LPDDR4__DENALI_CTL_169__LP_AUTO_EXIT_EN_WIDTH 4U
+#define LPDDR4__LP_AUTO_EXIT_EN__REG DENALI_CTL_169
+#define LPDDR4__LP_AUTO_EXIT_EN__FLD LPDDR4__DENALI_CTL_169__LP_AUTO_EXIT_EN
+
+#define LPDDR4__DENALI_CTL_170_READ_MASK 0x000FFF07U
+#define LPDDR4__DENALI_CTL_170_WRITE_MASK 0x000FFF07U
+#define LPDDR4__DENALI_CTL_170__LP_AUTO_MEM_GATE_EN_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_170__LP_AUTO_MEM_GATE_EN_SHIFT 0U
+#define LPDDR4__DENALI_CTL_170__LP_AUTO_MEM_GATE_EN_WIDTH 3U
+#define LPDDR4__LP_AUTO_MEM_GATE_EN__REG DENALI_CTL_170
+#define LPDDR4__LP_AUTO_MEM_GATE_EN__FLD LPDDR4__DENALI_CTL_170__LP_AUTO_MEM_GATE_EN
+
+#define LPDDR4__DENALI_CTL_170__LP_AUTO_PD_IDLE_MASK 0x000FFF00U
+#define LPDDR4__DENALI_CTL_170__LP_AUTO_PD_IDLE_SHIFT 8U
+#define LPDDR4__DENALI_CTL_170__LP_AUTO_PD_IDLE_WIDTH 12U
+#define LPDDR4__LP_AUTO_PD_IDLE__REG DENALI_CTL_170
+#define LPDDR4__LP_AUTO_PD_IDLE__FLD LPDDR4__DENALI_CTL_170__LP_AUTO_PD_IDLE
+
+#define LPDDR4__DENALI_CTL_171_READ_MASK 0xFFFF0FFFU
+#define LPDDR4__DENALI_CTL_171_WRITE_MASK 0xFFFF0FFFU
+#define LPDDR4__DENALI_CTL_171__LP_AUTO_SR_SHORT_IDLE_MASK 0x00000FFFU
+#define LPDDR4__DENALI_CTL_171__LP_AUTO_SR_SHORT_IDLE_SHIFT 0U
+#define LPDDR4__DENALI_CTL_171__LP_AUTO_SR_SHORT_IDLE_WIDTH 12U
+#define LPDDR4__LP_AUTO_SR_SHORT_IDLE__REG DENALI_CTL_171
+#define LPDDR4__LP_AUTO_SR_SHORT_IDLE__FLD LPDDR4__DENALI_CTL_171__LP_AUTO_SR_SHORT_IDLE
+
+#define LPDDR4__DENALI_CTL_171__LP_AUTO_SR_LONG_IDLE_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_171__LP_AUTO_SR_LONG_IDLE_SHIFT 16U
+#define LPDDR4__DENALI_CTL_171__LP_AUTO_SR_LONG_IDLE_WIDTH 8U
+#define LPDDR4__LP_AUTO_SR_LONG_IDLE__REG DENALI_CTL_171
+#define LPDDR4__LP_AUTO_SR_LONG_IDLE__FLD LPDDR4__DENALI_CTL_171__LP_AUTO_SR_LONG_IDLE
+
+#define LPDDR4__DENALI_CTL_171__LP_AUTO_SR_LONG_MC_GATE_IDLE_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_171__LP_AUTO_SR_LONG_MC_GATE_IDLE_SHIFT 24U
+#define LPDDR4__DENALI_CTL_171__LP_AUTO_SR_LONG_MC_GATE_IDLE_WIDTH 8U
+#define LPDDR4__LP_AUTO_SR_LONG_MC_GATE_IDLE__REG DENALI_CTL_171
+#define LPDDR4__LP_AUTO_SR_LONG_MC_GATE_IDLE__FLD LPDDR4__DENALI_CTL_171__LP_AUTO_SR_LONG_MC_GATE_IDLE
+
+#define LPDDR4__DENALI_CTL_172_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_172_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_172__HW_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_172__HW_PROMOTE_THRESHOLD_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_172__HW_PROMOTE_THRESHOLD_F0_WIDTH 16U
+#define LPDDR4__HW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_172
+#define LPDDR4__HW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_172__HW_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_172__HW_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_172__HW_PROMOTE_THRESHOLD_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_172__HW_PROMOTE_THRESHOLD_F1_WIDTH 16U
+#define LPDDR4__HW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_172
+#define LPDDR4__HW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_172__HW_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_173_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_173_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_173__HW_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_173__HW_PROMOTE_THRESHOLD_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_173__HW_PROMOTE_THRESHOLD_F2_WIDTH 16U
+#define LPDDR4__HW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_173
+#define LPDDR4__HW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_173__HW_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_173__LPC_PROMOTE_THRESHOLD_F0_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_173__LPC_PROMOTE_THRESHOLD_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_173__LPC_PROMOTE_THRESHOLD_F0_WIDTH 16U
+#define LPDDR4__LPC_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_173
+#define LPDDR4__LPC_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_173__LPC_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_174_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_174_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_174__LPC_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_174__LPC_PROMOTE_THRESHOLD_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_174__LPC_PROMOTE_THRESHOLD_F1_WIDTH 16U
+#define LPDDR4__LPC_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_174
+#define LPDDR4__LPC_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_174__LPC_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_174__LPC_PROMOTE_THRESHOLD_F2_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_174__LPC_PROMOTE_THRESHOLD_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_174__LPC_PROMOTE_THRESHOLD_F2_WIDTH 16U
+#define LPDDR4__LPC_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_174
+#define LPDDR4__LPC_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_174__LPC_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_175_READ_MASK 0x01010101U
+#define LPDDR4__DENALI_CTL_175_WRITE_MASK 0x01010101U
+#define LPDDR4__DENALI_CTL_175__LPC_SR_CTRLUPD_EN_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_175__LPC_SR_CTRLUPD_EN_SHIFT 0U
+#define LPDDR4__DENALI_CTL_175__LPC_SR_CTRLUPD_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_175__LPC_SR_CTRLUPD_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_175__LPC_SR_CTRLUPD_EN_WOSET 0U
+#define LPDDR4__LPC_SR_CTRLUPD_EN__REG DENALI_CTL_175
+#define LPDDR4__LPC_SR_CTRLUPD_EN__FLD LPDDR4__DENALI_CTL_175__LPC_SR_CTRLUPD_EN
+
+#define LPDDR4__DENALI_CTL_175__LPC_SR_PHYUPD_EN_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_175__LPC_SR_PHYUPD_EN_SHIFT 8U
+#define LPDDR4__DENALI_CTL_175__LPC_SR_PHYUPD_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_175__LPC_SR_PHYUPD_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_175__LPC_SR_PHYUPD_EN_WOSET 0U
+#define LPDDR4__LPC_SR_PHYUPD_EN__REG DENALI_CTL_175
+#define LPDDR4__LPC_SR_PHYUPD_EN__FLD LPDDR4__DENALI_CTL_175__LPC_SR_PHYUPD_EN
+
+#define LPDDR4__DENALI_CTL_175__LPC_SR_PHYMSTR_EN_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_175__LPC_SR_PHYMSTR_EN_SHIFT 16U
+#define LPDDR4__DENALI_CTL_175__LPC_SR_PHYMSTR_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_175__LPC_SR_PHYMSTR_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_175__LPC_SR_PHYMSTR_EN_WOSET 0U
+#define LPDDR4__LPC_SR_PHYMSTR_EN__REG DENALI_CTL_175
+#define LPDDR4__LPC_SR_PHYMSTR_EN__FLD LPDDR4__DENALI_CTL_175__LPC_SR_PHYMSTR_EN
+
+#define LPDDR4__DENALI_CTL_175__LPC_SR_EXIT_CMD_EN_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_175__LPC_SR_EXIT_CMD_EN_SHIFT 24U
+#define LPDDR4__DENALI_CTL_175__LPC_SR_EXIT_CMD_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_175__LPC_SR_EXIT_CMD_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_175__LPC_SR_EXIT_CMD_EN_WOSET 0U
+#define LPDDR4__LPC_SR_EXIT_CMD_EN__REG DENALI_CTL_175
+#define LPDDR4__LPC_SR_EXIT_CMD_EN__FLD LPDDR4__DENALI_CTL_175__LPC_SR_EXIT_CMD_EN
+
+#define LPDDR4__DENALI_CTL_176_READ_MASK 0x0101FF01U
+#define LPDDR4__DENALI_CTL_176_WRITE_MASK 0x0101FF01U
+#define LPDDR4__DENALI_CTL_176__LPC_SR_ZQ_EN_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_176__LPC_SR_ZQ_EN_SHIFT 0U
+#define LPDDR4__DENALI_CTL_176__LPC_SR_ZQ_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_176__LPC_SR_ZQ_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_176__LPC_SR_ZQ_EN_WOSET 0U
+#define LPDDR4__LPC_SR_ZQ_EN__REG DENALI_CTL_176
+#define LPDDR4__LPC_SR_ZQ_EN__FLD LPDDR4__DENALI_CTL_176__LPC_SR_ZQ_EN
+
+#define LPDDR4__DENALI_CTL_176__PWRDN_SHIFT_DELAY_MASK 0x0001FF00U
+#define LPDDR4__DENALI_CTL_176__PWRDN_SHIFT_DELAY_SHIFT 8U
+#define LPDDR4__DENALI_CTL_176__PWRDN_SHIFT_DELAY_WIDTH 9U
+#define LPDDR4__PWRDN_SHIFT_DELAY__REG DENALI_CTL_176
+#define LPDDR4__PWRDN_SHIFT_DELAY__FLD LPDDR4__DENALI_CTL_176__PWRDN_SHIFT_DELAY
+
+#define LPDDR4__DENALI_CTL_176__DFS_ENABLE_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_176__DFS_ENABLE_SHIFT 24U
+#define LPDDR4__DENALI_CTL_176__DFS_ENABLE_WIDTH 1U
+#define LPDDR4__DENALI_CTL_176__DFS_ENABLE_WOCLR 0U
+#define LPDDR4__DENALI_CTL_176__DFS_ENABLE_WOSET 0U
+#define LPDDR4__DFS_ENABLE__REG DENALI_CTL_176
+#define LPDDR4__DFS_ENABLE__FLD LPDDR4__DENALI_CTL_176__DFS_ENABLE
+
+#define LPDDR4__DENALI_CTL_177_READ_MASK 0x00000107U
+#define LPDDR4__DENALI_CTL_177_WRITE_MASK 0x00000107U
+#define LPDDR4__DENALI_CTL_177__DFS_DLL_OFF_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_177__DFS_DLL_OFF_SHIFT 0U
+#define LPDDR4__DENALI_CTL_177__DFS_DLL_OFF_WIDTH 3U
+#define LPDDR4__DFS_DLL_OFF__REG DENALI_CTL_177
+#define LPDDR4__DFS_DLL_OFF__FLD LPDDR4__DENALI_CTL_177__DFS_DLL_OFF
+
+#define LPDDR4__DENALI_CTL_177__DFS_PHY_REG_WRITE_EN_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_177__DFS_PHY_REG_WRITE_EN_SHIFT 8U
+#define LPDDR4__DENALI_CTL_177__DFS_PHY_REG_WRITE_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_177__DFS_PHY_REG_WRITE_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_177__DFS_PHY_REG_WRITE_EN_WOSET 0U
+#define LPDDR4__DFS_PHY_REG_WRITE_EN__REG DENALI_CTL_177
+#define LPDDR4__DFS_PHY_REG_WRITE_EN__FLD LPDDR4__DENALI_CTL_177__DFS_PHY_REG_WRITE_EN
+
+#define LPDDR4__DENALI_CTL_178_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_178_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_178__DFS_PHY_REG_WRITE_ADDR_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_178__DFS_PHY_REG_WRITE_ADDR_SHIFT 0U
+#define LPDDR4__DENALI_CTL_178__DFS_PHY_REG_WRITE_ADDR_WIDTH 32U
+#define LPDDR4__DFS_PHY_REG_WRITE_ADDR__REG DENALI_CTL_178
+#define LPDDR4__DFS_PHY_REG_WRITE_ADDR__FLD LPDDR4__DENALI_CTL_178__DFS_PHY_REG_WRITE_ADDR
+
+#define LPDDR4__DENALI_CTL_179_READ_MASK 0x03FFFF0FU
+#define LPDDR4__DENALI_CTL_179_WRITE_MASK 0x03FFFF0FU
+#define LPDDR4__DENALI_CTL_179__DFS_PHY_REG_WRITE_MASK_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_179__DFS_PHY_REG_WRITE_MASK_SHIFT 0U
+#define LPDDR4__DENALI_CTL_179__DFS_PHY_REG_WRITE_MASK_WIDTH 4U
+#define LPDDR4__DFS_PHY_REG_WRITE_MASK__REG DENALI_CTL_179
+#define LPDDR4__DFS_PHY_REG_WRITE_MASK__FLD LPDDR4__DENALI_CTL_179__DFS_PHY_REG_WRITE_MASK
+
+#define LPDDR4__DENALI_CTL_179__DFS_PHY_REG_WRITE_WAIT_MASK 0x00FFFF00U
+#define LPDDR4__DENALI_CTL_179__DFS_PHY_REG_WRITE_WAIT_SHIFT 8U
+#define LPDDR4__DENALI_CTL_179__DFS_PHY_REG_WRITE_WAIT_WIDTH 16U
+#define LPDDR4__DFS_PHY_REG_WRITE_WAIT__REG DENALI_CTL_179
+#define LPDDR4__DFS_PHY_REG_WRITE_WAIT__FLD LPDDR4__DENALI_CTL_179__DFS_PHY_REG_WRITE_WAIT
+
+#define LPDDR4__DENALI_CTL_179__CURRENT_REG_COPY_MASK 0x03000000U
+#define LPDDR4__DENALI_CTL_179__CURRENT_REG_COPY_SHIFT 24U
+#define LPDDR4__DENALI_CTL_179__CURRENT_REG_COPY_WIDTH 2U
+#define LPDDR4__CURRENT_REG_COPY__REG DENALI_CTL_179
+#define LPDDR4__CURRENT_REG_COPY__FLD LPDDR4__DENALI_CTL_179__CURRENT_REG_COPY
+
+#define LPDDR4__DENALI_CTL_180_READ_MASK 0x00000303U
+#define LPDDR4__DENALI_CTL_180_WRITE_MASK 0x00000303U
+#define LPDDR4__DENALI_CTL_180__INIT_FREQ_MASK 0x00000003U
+#define LPDDR4__DENALI_CTL_180__INIT_FREQ_SHIFT 0U
+#define LPDDR4__DENALI_CTL_180__INIT_FREQ_WIDTH 2U
+#define LPDDR4__INIT_FREQ__REG DENALI_CTL_180
+#define LPDDR4__INIT_FREQ__FLD LPDDR4__DENALI_CTL_180__INIT_FREQ
+
+#define LPDDR4__DENALI_CTL_180__DFIBUS_BOOT_FREQ_MASK 0x00000300U
+#define LPDDR4__DENALI_CTL_180__DFIBUS_BOOT_FREQ_SHIFT 8U
+#define LPDDR4__DENALI_CTL_180__DFIBUS_BOOT_FREQ_WIDTH 2U
+#define LPDDR4__DFIBUS_BOOT_FREQ__REG DENALI_CTL_180
+#define LPDDR4__DFIBUS_BOOT_FREQ__FLD LPDDR4__DENALI_CTL_180__DFIBUS_BOOT_FREQ
+
+#define LPDDR4__DENALI_CTL_181_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_181_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_181__DFS_PHY_REG_WRITE_DATA_F0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_181__DFS_PHY_REG_WRITE_DATA_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_181__DFS_PHY_REG_WRITE_DATA_F0_WIDTH 32U
+#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F0__REG DENALI_CTL_181
+#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F0__FLD LPDDR4__DENALI_CTL_181__DFS_PHY_REG_WRITE_DATA_F0
+
+#define LPDDR4__DENALI_CTL_182_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_182_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_182__DFS_PHY_REG_WRITE_DATA_F1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_182__DFS_PHY_REG_WRITE_DATA_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_182__DFS_PHY_REG_WRITE_DATA_F1_WIDTH 32U
+#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F1__REG DENALI_CTL_182
+#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F1__FLD LPDDR4__DENALI_CTL_182__DFS_PHY_REG_WRITE_DATA_F1
+
+#define LPDDR4__DENALI_CTL_183_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_183_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_183__DFS_PHY_REG_WRITE_DATA_F2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_183__DFS_PHY_REG_WRITE_DATA_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_183__DFS_PHY_REG_WRITE_DATA_F2_WIDTH 32U
+#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F2__REG DENALI_CTL_183
+#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F2__FLD LPDDR4__DENALI_CTL_183__DFS_PHY_REG_WRITE_DATA_F2
+
+#define LPDDR4__DENALI_CTL_184_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_184_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_184__TDFI_INIT_START_F0_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_184__TDFI_INIT_START_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_184__TDFI_INIT_START_F0_WIDTH 24U
+#define LPDDR4__TDFI_INIT_START_F0__REG DENALI_CTL_184
+#define LPDDR4__TDFI_INIT_START_F0__FLD LPDDR4__DENALI_CTL_184__TDFI_INIT_START_F0
+
+#define LPDDR4__DENALI_CTL_185_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_185_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_185__TDFI_INIT_COMPLETE_F0_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_185__TDFI_INIT_COMPLETE_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_185__TDFI_INIT_COMPLETE_F0_WIDTH 24U
+#define LPDDR4__TDFI_INIT_COMPLETE_F0__REG DENALI_CTL_185
+#define LPDDR4__TDFI_INIT_COMPLETE_F0__FLD LPDDR4__DENALI_CTL_185__TDFI_INIT_COMPLETE_F0
+
+#define LPDDR4__DENALI_CTL_186_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_186_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_186__TDFI_INIT_START_F1_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_186__TDFI_INIT_START_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_186__TDFI_INIT_START_F1_WIDTH 24U
+#define LPDDR4__TDFI_INIT_START_F1__REG DENALI_CTL_186
+#define LPDDR4__TDFI_INIT_START_F1__FLD LPDDR4__DENALI_CTL_186__TDFI_INIT_START_F1
+
+#define LPDDR4__DENALI_CTL_187_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_187_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_187__TDFI_INIT_COMPLETE_F1_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_187__TDFI_INIT_COMPLETE_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_187__TDFI_INIT_COMPLETE_F1_WIDTH 24U
+#define LPDDR4__TDFI_INIT_COMPLETE_F1__REG DENALI_CTL_187
+#define LPDDR4__TDFI_INIT_COMPLETE_F1__FLD LPDDR4__DENALI_CTL_187__TDFI_INIT_COMPLETE_F1
+
+#define LPDDR4__DENALI_CTL_188_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_188_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_188__TDFI_INIT_START_F2_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_188__TDFI_INIT_START_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_188__TDFI_INIT_START_F2_WIDTH 24U
+#define LPDDR4__TDFI_INIT_START_F2__REG DENALI_CTL_188
+#define LPDDR4__TDFI_INIT_START_F2__FLD LPDDR4__DENALI_CTL_188__TDFI_INIT_START_F2
+
+#define LPDDR4__DENALI_CTL_189_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_189_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_189__TDFI_INIT_COMPLETE_F2_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_189__TDFI_INIT_COMPLETE_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_189__TDFI_INIT_COMPLETE_F2_WIDTH 24U
+#define LPDDR4__TDFI_INIT_COMPLETE_F2__REG DENALI_CTL_189
+#define LPDDR4__TDFI_INIT_COMPLETE_F2__FLD LPDDR4__DENALI_CTL_189__TDFI_INIT_COMPLETE_F2
+
+#define LPDDR4__DENALI_CTL_190_READ_MASK 0x07FFFFFFU
+#define LPDDR4__DENALI_CTL_190_WRITE_MASK 0x07FFFFFFU
+#define LPDDR4__DENALI_CTL_190__WRITE_MODEREG_MASK 0x07FFFFFFU
+#define LPDDR4__DENALI_CTL_190__WRITE_MODEREG_SHIFT 0U
+#define LPDDR4__DENALI_CTL_190__WRITE_MODEREG_WIDTH 27U
+#define LPDDR4__WRITE_MODEREG__REG DENALI_CTL_190
+#define LPDDR4__WRITE_MODEREG__FLD LPDDR4__DENALI_CTL_190__WRITE_MODEREG
+
+#define LPDDR4__DENALI_CTL_191_READ_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_191_WRITE_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_191__MRW_STATUS_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_191__MRW_STATUS_SHIFT 0U
+#define LPDDR4__DENALI_CTL_191__MRW_STATUS_WIDTH 8U
+#define LPDDR4__MRW_STATUS__REG DENALI_CTL_191
+#define LPDDR4__MRW_STATUS__FLD LPDDR4__DENALI_CTL_191__MRW_STATUS
+
+#define LPDDR4__DENALI_CTL_191__READ_MODEREG_MASK 0x01FFFF00U
+#define LPDDR4__DENALI_CTL_191__READ_MODEREG_SHIFT 8U
+#define LPDDR4__DENALI_CTL_191__READ_MODEREG_WIDTH 17U
+#define LPDDR4__READ_MODEREG__REG DENALI_CTL_191
+#define LPDDR4__READ_MODEREG__FLD LPDDR4__DENALI_CTL_191__READ_MODEREG
+
+#define LPDDR4__DENALI_CTL_192_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_192_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_192__PERIPHERAL_MRR_DATA_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_192__PERIPHERAL_MRR_DATA_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_192__PERIPHERAL_MRR_DATA_0_WIDTH 32U
+#define LPDDR4__PERIPHERAL_MRR_DATA_0__REG DENALI_CTL_192
+#define LPDDR4__PERIPHERAL_MRR_DATA_0__FLD LPDDR4__DENALI_CTL_192__PERIPHERAL_MRR_DATA_0
+
+#define LPDDR4__DENALI_CTL_193_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_193_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_193__PERIPHERAL_MRR_DATA_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_193__PERIPHERAL_MRR_DATA_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_193__PERIPHERAL_MRR_DATA_1_WIDTH 8U
+#define LPDDR4__PERIPHERAL_MRR_DATA_1__REG DENALI_CTL_193
+#define LPDDR4__PERIPHERAL_MRR_DATA_1__FLD LPDDR4__DENALI_CTL_193__PERIPHERAL_MRR_DATA_1
+
+#define LPDDR4__DENALI_CTL_193__AUTO_TEMPCHK_VAL_0_MASK 0x00FFFF00U
+#define LPDDR4__DENALI_CTL_193__AUTO_TEMPCHK_VAL_0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_193__AUTO_TEMPCHK_VAL_0_WIDTH 16U
+#define LPDDR4__AUTO_TEMPCHK_VAL_0__REG DENALI_CTL_193
+#define LPDDR4__AUTO_TEMPCHK_VAL_0__FLD LPDDR4__DENALI_CTL_193__AUTO_TEMPCHK_VAL_0
+
+#define LPDDR4__DENALI_CTL_194_READ_MASK 0x0301FFFFU
+#define LPDDR4__DENALI_CTL_194_WRITE_MASK 0x0301FFFFU
+#define LPDDR4__DENALI_CTL_194__AUTO_TEMPCHK_VAL_1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_194__AUTO_TEMPCHK_VAL_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_194__AUTO_TEMPCHK_VAL_1_WIDTH 16U
+#define LPDDR4__AUTO_TEMPCHK_VAL_1__REG DENALI_CTL_194
+#define LPDDR4__AUTO_TEMPCHK_VAL_1__FLD LPDDR4__DENALI_CTL_194__AUTO_TEMPCHK_VAL_1
+
+#define LPDDR4__DENALI_CTL_194__DISABLE_UPDATE_TVRCG_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_194__DISABLE_UPDATE_TVRCG_SHIFT 16U
+#define LPDDR4__DENALI_CTL_194__DISABLE_UPDATE_TVRCG_WIDTH 1U
+#define LPDDR4__DENALI_CTL_194__DISABLE_UPDATE_TVRCG_WOCLR 0U
+#define LPDDR4__DENALI_CTL_194__DISABLE_UPDATE_TVRCG_WOSET 0U
+#define LPDDR4__DISABLE_UPDATE_TVRCG__REG DENALI_CTL_194
+#define LPDDR4__DISABLE_UPDATE_TVRCG__FLD LPDDR4__DENALI_CTL_194__DISABLE_UPDATE_TVRCG
+
+#define LPDDR4__DENALI_CTL_194__MRW_DFS_UPDATE_FRC_MASK 0x03000000U
+#define LPDDR4__DENALI_CTL_194__MRW_DFS_UPDATE_FRC_SHIFT 24U
+#define LPDDR4__DENALI_CTL_194__MRW_DFS_UPDATE_FRC_WIDTH 2U
+#define LPDDR4__MRW_DFS_UPDATE_FRC__REG DENALI_CTL_194
+#define LPDDR4__MRW_DFS_UPDATE_FRC__FLD LPDDR4__DENALI_CTL_194__MRW_DFS_UPDATE_FRC
+
+#define LPDDR4__DENALI_CTL_195_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_CTL_195_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_CTL_195__TVRCG_ENABLE_F0_MASK 0x000003FFU
+#define LPDDR4__DENALI_CTL_195__TVRCG_ENABLE_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_195__TVRCG_ENABLE_F0_WIDTH 10U
+#define LPDDR4__TVRCG_ENABLE_F0__REG DENALI_CTL_195
+#define LPDDR4__TVRCG_ENABLE_F0__FLD LPDDR4__DENALI_CTL_195__TVRCG_ENABLE_F0
+
+#define LPDDR4__DENALI_CTL_195__TVRCG_DISABLE_F0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_CTL_195__TVRCG_DISABLE_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_195__TVRCG_DISABLE_F0_WIDTH 10U
+#define LPDDR4__TVRCG_DISABLE_F0__REG DENALI_CTL_195
+#define LPDDR4__TVRCG_DISABLE_F0__FLD LPDDR4__DENALI_CTL_195__TVRCG_DISABLE_F0
+
+#define LPDDR4__DENALI_CTL_196_READ_MASK 0x1F1F03FFU
+#define LPDDR4__DENALI_CTL_196_WRITE_MASK 0x1F1F03FFU
+#define LPDDR4__DENALI_CTL_196__TFC_F0_MASK 0x000003FFU
+#define LPDDR4__DENALI_CTL_196__TFC_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_196__TFC_F0_WIDTH 10U
+#define LPDDR4__TFC_F0__REG DENALI_CTL_196
+#define LPDDR4__TFC_F0__FLD LPDDR4__DENALI_CTL_196__TFC_F0
+
+#define LPDDR4__DENALI_CTL_196__TCKFSPE_F0_MASK 0x001F0000U
+#define LPDDR4__DENALI_CTL_196__TCKFSPE_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_196__TCKFSPE_F0_WIDTH 5U
+#define LPDDR4__TCKFSPE_F0__REG DENALI_CTL_196
+#define LPDDR4__TCKFSPE_F0__FLD LPDDR4__DENALI_CTL_196__TCKFSPE_F0
+
+#define LPDDR4__DENALI_CTL_196__TCKFSPX_F0_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_196__TCKFSPX_F0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_196__TCKFSPX_F0_WIDTH 5U
+#define LPDDR4__TCKFSPX_F0__REG DENALI_CTL_196
+#define LPDDR4__TCKFSPX_F0__FLD LPDDR4__DENALI_CTL_196__TCKFSPX_F0
+
+#define LPDDR4__DENALI_CTL_197_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_197_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_197__TVREF_LONG_F0_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_197__TVREF_LONG_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_197__TVREF_LONG_F0_WIDTH 20U
+#define LPDDR4__TVREF_LONG_F0__REG DENALI_CTL_197
+#define LPDDR4__TVREF_LONG_F0__FLD LPDDR4__DENALI_CTL_197__TVREF_LONG_F0
+
+#define LPDDR4__DENALI_CTL_198_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_CTL_198_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_CTL_198__TVRCG_ENABLE_F1_MASK 0x000003FFU
+#define LPDDR4__DENALI_CTL_198__TVRCG_ENABLE_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_198__TVRCG_ENABLE_F1_WIDTH 10U
+#define LPDDR4__TVRCG_ENABLE_F1__REG DENALI_CTL_198
+#define LPDDR4__TVRCG_ENABLE_F1__FLD LPDDR4__DENALI_CTL_198__TVRCG_ENABLE_F1
+
+#define LPDDR4__DENALI_CTL_198__TVRCG_DISABLE_F1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_CTL_198__TVRCG_DISABLE_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_198__TVRCG_DISABLE_F1_WIDTH 10U
+#define LPDDR4__TVRCG_DISABLE_F1__REG DENALI_CTL_198
+#define LPDDR4__TVRCG_DISABLE_F1__FLD LPDDR4__DENALI_CTL_198__TVRCG_DISABLE_F1
+
+#define LPDDR4__DENALI_CTL_199_READ_MASK 0x1F1F03FFU
+#define LPDDR4__DENALI_CTL_199_WRITE_MASK 0x1F1F03FFU
+#define LPDDR4__DENALI_CTL_199__TFC_F1_MASK 0x000003FFU
+#define LPDDR4__DENALI_CTL_199__TFC_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_199__TFC_F1_WIDTH 10U
+#define LPDDR4__TFC_F1__REG DENALI_CTL_199
+#define LPDDR4__TFC_F1__FLD LPDDR4__DENALI_CTL_199__TFC_F1
+
+#define LPDDR4__DENALI_CTL_199__TCKFSPE_F1_MASK 0x001F0000U
+#define LPDDR4__DENALI_CTL_199__TCKFSPE_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_199__TCKFSPE_F1_WIDTH 5U
+#define LPDDR4__TCKFSPE_F1__REG DENALI_CTL_199
+#define LPDDR4__TCKFSPE_F1__FLD LPDDR4__DENALI_CTL_199__TCKFSPE_F1
+
+#define LPDDR4__DENALI_CTL_199__TCKFSPX_F1_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_199__TCKFSPX_F1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_199__TCKFSPX_F1_WIDTH 5U
+#define LPDDR4__TCKFSPX_F1__REG DENALI_CTL_199
+#define LPDDR4__TCKFSPX_F1__FLD LPDDR4__DENALI_CTL_199__TCKFSPX_F1
+
+#define LPDDR4__DENALI_CTL_200_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_200_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_200__TVREF_LONG_F1_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_200__TVREF_LONG_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_200__TVREF_LONG_F1_WIDTH 20U
+#define LPDDR4__TVREF_LONG_F1__REG DENALI_CTL_200
+#define LPDDR4__TVREF_LONG_F1__FLD LPDDR4__DENALI_CTL_200__TVREF_LONG_F1
+
+#define LPDDR4__DENALI_CTL_201_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_CTL_201_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_CTL_201__TVRCG_ENABLE_F2_MASK 0x000003FFU
+#define LPDDR4__DENALI_CTL_201__TVRCG_ENABLE_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_201__TVRCG_ENABLE_F2_WIDTH 10U
+#define LPDDR4__TVRCG_ENABLE_F2__REG DENALI_CTL_201
+#define LPDDR4__TVRCG_ENABLE_F2__FLD LPDDR4__DENALI_CTL_201__TVRCG_ENABLE_F2
+
+#define LPDDR4__DENALI_CTL_201__TVRCG_DISABLE_F2_MASK 0x03FF0000U
+#define LPDDR4__DENALI_CTL_201__TVRCG_DISABLE_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_201__TVRCG_DISABLE_F2_WIDTH 10U
+#define LPDDR4__TVRCG_DISABLE_F2__REG DENALI_CTL_201
+#define LPDDR4__TVRCG_DISABLE_F2__FLD LPDDR4__DENALI_CTL_201__TVRCG_DISABLE_F2
+
+#define LPDDR4__DENALI_CTL_202_READ_MASK 0x1F1F03FFU
+#define LPDDR4__DENALI_CTL_202_WRITE_MASK 0x1F1F03FFU
+#define LPDDR4__DENALI_CTL_202__TFC_F2_MASK 0x000003FFU
+#define LPDDR4__DENALI_CTL_202__TFC_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_202__TFC_F2_WIDTH 10U
+#define LPDDR4__TFC_F2__REG DENALI_CTL_202
+#define LPDDR4__TFC_F2__FLD LPDDR4__DENALI_CTL_202__TFC_F2
+
+#define LPDDR4__DENALI_CTL_202__TCKFSPE_F2_MASK 0x001F0000U
+#define LPDDR4__DENALI_CTL_202__TCKFSPE_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_202__TCKFSPE_F2_WIDTH 5U
+#define LPDDR4__TCKFSPE_F2__REG DENALI_CTL_202
+#define LPDDR4__TCKFSPE_F2__FLD LPDDR4__DENALI_CTL_202__TCKFSPE_F2
+
+#define LPDDR4__DENALI_CTL_202__TCKFSPX_F2_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_202__TCKFSPX_F2_SHIFT 24U
+#define LPDDR4__DENALI_CTL_202__TCKFSPX_F2_WIDTH 5U
+#define LPDDR4__TCKFSPX_F2__REG DENALI_CTL_202
+#define LPDDR4__TCKFSPX_F2__FLD LPDDR4__DENALI_CTL_202__TCKFSPX_F2
+
+#define LPDDR4__DENALI_CTL_203_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_203_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_203__TVREF_LONG_F2_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_203__TVREF_LONG_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_203__TVREF_LONG_F2_WIDTH 20U
+#define LPDDR4__TVREF_LONG_F2__REG DENALI_CTL_203
+#define LPDDR4__TVREF_LONG_F2__FLD LPDDR4__DENALI_CTL_203__TVREF_LONG_F2
+
+#define LPDDR4__DENALI_CTL_204_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_204_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_204__MRR_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_204__MRR_PROMOTE_THRESHOLD_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_204__MRR_PROMOTE_THRESHOLD_F0_WIDTH 16U
+#define LPDDR4__MRR_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_204
+#define LPDDR4__MRR_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_204__MRR_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_204__MRR_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_204__MRR_PROMOTE_THRESHOLD_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_204__MRR_PROMOTE_THRESHOLD_F1_WIDTH 16U
+#define LPDDR4__MRR_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_204
+#define LPDDR4__MRR_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_204__MRR_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_205_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_205_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_205__MRR_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_205__MRR_PROMOTE_THRESHOLD_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_205__MRR_PROMOTE_THRESHOLD_F2_WIDTH 16U
+#define LPDDR4__MRR_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_205
+#define LPDDR4__MRR_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_205__MRR_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_205__MRW_PROMOTE_THRESHOLD_F0_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_205__MRW_PROMOTE_THRESHOLD_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_205__MRW_PROMOTE_THRESHOLD_F0_WIDTH 16U
+#define LPDDR4__MRW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_205
+#define LPDDR4__MRW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_205__MRW_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_206_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_206_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_206__MRW_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_206__MRW_PROMOTE_THRESHOLD_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_206__MRW_PROMOTE_THRESHOLD_F1_WIDTH 16U
+#define LPDDR4__MRW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_206
+#define LPDDR4__MRW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_206__MRW_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_206__MRW_PROMOTE_THRESHOLD_F2_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_206__MRW_PROMOTE_THRESHOLD_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_206__MRW_PROMOTE_THRESHOLD_F2_WIDTH 16U
+#define LPDDR4__MRW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_206
+#define LPDDR4__MRW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_206__MRW_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_207_READ_MASK 0x01FFFF01U
+#define LPDDR4__DENALI_CTL_207_WRITE_MASK 0x01FFFF01U
+#define LPDDR4__DENALI_CTL_207__MR4_DLL_RST_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_207__MR4_DLL_RST_SHIFT 0U
+#define LPDDR4__DENALI_CTL_207__MR4_DLL_RST_WIDTH 1U
+#define LPDDR4__DENALI_CTL_207__MR4_DLL_RST_WOCLR 0U
+#define LPDDR4__DENALI_CTL_207__MR4_DLL_RST_WOSET 0U
+#define LPDDR4__MR4_DLL_RST__REG DENALI_CTL_207
+#define LPDDR4__MR4_DLL_RST__FLD LPDDR4__DENALI_CTL_207__MR4_DLL_RST
+
+#define LPDDR4__DENALI_CTL_207__MR0_DATA_F0_0_MASK 0x01FFFF00U
+#define LPDDR4__DENALI_CTL_207__MR0_DATA_F0_0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_207__MR0_DATA_F0_0_WIDTH 17U
+#define LPDDR4__MR0_DATA_F0_0__REG DENALI_CTL_207
+#define LPDDR4__MR0_DATA_F0_0__FLD LPDDR4__DENALI_CTL_207__MR0_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_208_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_208_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_208__MR1_DATA_F0_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_208__MR1_DATA_F0_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_208__MR1_DATA_F0_0_WIDTH 17U
+#define LPDDR4__MR1_DATA_F0_0__REG DENALI_CTL_208
+#define LPDDR4__MR1_DATA_F0_0__FLD LPDDR4__DENALI_CTL_208__MR1_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_209_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_209_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_209__MR2_DATA_F0_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_209__MR2_DATA_F0_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_209__MR2_DATA_F0_0_WIDTH 17U
+#define LPDDR4__MR2_DATA_F0_0__REG DENALI_CTL_209
+#define LPDDR4__MR2_DATA_F0_0__FLD LPDDR4__DENALI_CTL_209__MR2_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_210_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_210_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_210__MR0_DATA_F1_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_210__MR0_DATA_F1_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_210__MR0_DATA_F1_0_WIDTH 17U
+#define LPDDR4__MR0_DATA_F1_0__REG DENALI_CTL_210
+#define LPDDR4__MR0_DATA_F1_0__FLD LPDDR4__DENALI_CTL_210__MR0_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_211_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_211_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_211__MR1_DATA_F1_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_211__MR1_DATA_F1_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_211__MR1_DATA_F1_0_WIDTH 17U
+#define LPDDR4__MR1_DATA_F1_0__REG DENALI_CTL_211
+#define LPDDR4__MR1_DATA_F1_0__FLD LPDDR4__DENALI_CTL_211__MR1_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_212_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_212_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_212__MR2_DATA_F1_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_212__MR2_DATA_F1_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_212__MR2_DATA_F1_0_WIDTH 17U
+#define LPDDR4__MR2_DATA_F1_0__REG DENALI_CTL_212
+#define LPDDR4__MR2_DATA_F1_0__FLD LPDDR4__DENALI_CTL_212__MR2_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_213_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_213_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_213__MR0_DATA_F2_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_213__MR0_DATA_F2_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_213__MR0_DATA_F2_0_WIDTH 17U
+#define LPDDR4__MR0_DATA_F2_0__REG DENALI_CTL_213
+#define LPDDR4__MR0_DATA_F2_0__FLD LPDDR4__DENALI_CTL_213__MR0_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_214_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_214_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_214__MR1_DATA_F2_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_214__MR1_DATA_F2_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_214__MR1_DATA_F2_0_WIDTH 17U
+#define LPDDR4__MR1_DATA_F2_0__REG DENALI_CTL_214
+#define LPDDR4__MR1_DATA_F2_0__FLD LPDDR4__DENALI_CTL_214__MR1_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_215_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_215_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_215__MR2_DATA_F2_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_215__MR2_DATA_F2_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_215__MR2_DATA_F2_0_WIDTH 17U
+#define LPDDR4__MR2_DATA_F2_0__REG DENALI_CTL_215
+#define LPDDR4__MR2_DATA_F2_0__FLD LPDDR4__DENALI_CTL_215__MR2_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_216_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_216_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_216__MR0_DATA_F0_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_216__MR0_DATA_F0_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_216__MR0_DATA_F0_1_WIDTH 17U
+#define LPDDR4__MR0_DATA_F0_1__REG DENALI_CTL_216
+#define LPDDR4__MR0_DATA_F0_1__FLD LPDDR4__DENALI_CTL_216__MR0_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_217_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_217_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_217__MR1_DATA_F0_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_217__MR1_DATA_F0_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_217__MR1_DATA_F0_1_WIDTH 17U
+#define LPDDR4__MR1_DATA_F0_1__REG DENALI_CTL_217
+#define LPDDR4__MR1_DATA_F0_1__FLD LPDDR4__DENALI_CTL_217__MR1_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_218_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_218_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_218__MR2_DATA_F0_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_218__MR2_DATA_F0_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_218__MR2_DATA_F0_1_WIDTH 17U
+#define LPDDR4__MR2_DATA_F0_1__REG DENALI_CTL_218
+#define LPDDR4__MR2_DATA_F0_1__FLD LPDDR4__DENALI_CTL_218__MR2_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_219_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_219_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_219__MR0_DATA_F1_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_219__MR0_DATA_F1_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_219__MR0_DATA_F1_1_WIDTH 17U
+#define LPDDR4__MR0_DATA_F1_1__REG DENALI_CTL_219
+#define LPDDR4__MR0_DATA_F1_1__FLD LPDDR4__DENALI_CTL_219__MR0_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_220_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_220_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_220__MR1_DATA_F1_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_220__MR1_DATA_F1_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_220__MR1_DATA_F1_1_WIDTH 17U
+#define LPDDR4__MR1_DATA_F1_1__REG DENALI_CTL_220
+#define LPDDR4__MR1_DATA_F1_1__FLD LPDDR4__DENALI_CTL_220__MR1_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_221_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_221_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_221__MR2_DATA_F1_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_221__MR2_DATA_F1_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_221__MR2_DATA_F1_1_WIDTH 17U
+#define LPDDR4__MR2_DATA_F1_1__REG DENALI_CTL_221
+#define LPDDR4__MR2_DATA_F1_1__FLD LPDDR4__DENALI_CTL_221__MR2_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_222_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_222_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_222__MR0_DATA_F2_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_222__MR0_DATA_F2_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_222__MR0_DATA_F2_1_WIDTH 17U
+#define LPDDR4__MR0_DATA_F2_1__REG DENALI_CTL_222
+#define LPDDR4__MR0_DATA_F2_1__FLD LPDDR4__DENALI_CTL_222__MR0_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_223_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_223_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_223__MR1_DATA_F2_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_223__MR1_DATA_F2_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_223__MR1_DATA_F2_1_WIDTH 17U
+#define LPDDR4__MR1_DATA_F2_1__REG DENALI_CTL_223
+#define LPDDR4__MR1_DATA_F2_1__FLD LPDDR4__DENALI_CTL_223__MR1_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_224_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_224_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_224__MR2_DATA_F2_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_224__MR2_DATA_F2_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_224__MR2_DATA_F2_1_WIDTH 17U
+#define LPDDR4__MR2_DATA_F2_1__REG DENALI_CTL_224
+#define LPDDR4__MR2_DATA_F2_1__FLD LPDDR4__DENALI_CTL_224__MR2_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_225_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_225_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_225__MRSINGLE_DATA_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_225__MRSINGLE_DATA_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_225__MRSINGLE_DATA_0_WIDTH 17U
+#define LPDDR4__MRSINGLE_DATA_0__REG DENALI_CTL_225
+#define LPDDR4__MRSINGLE_DATA_0__FLD LPDDR4__DENALI_CTL_225__MRSINGLE_DATA_0
+
+#define LPDDR4__DENALI_CTL_226_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_226_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_226__MRSINGLE_DATA_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_226__MRSINGLE_DATA_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_226__MRSINGLE_DATA_1_WIDTH 17U
+#define LPDDR4__MRSINGLE_DATA_1__REG DENALI_CTL_226
+#define LPDDR4__MRSINGLE_DATA_1__FLD LPDDR4__DENALI_CTL_226__MRSINGLE_DATA_1
+
+#define LPDDR4__DENALI_CTL_227_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_227_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_227__MR3_DATA_F0_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_227__MR3_DATA_F0_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_227__MR3_DATA_F0_0_WIDTH 17U
+#define LPDDR4__MR3_DATA_F0_0__REG DENALI_CTL_227
+#define LPDDR4__MR3_DATA_F0_0__FLD LPDDR4__DENALI_CTL_227__MR3_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_228_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_228_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_228__MR3_DATA_F1_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_228__MR3_DATA_F1_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_228__MR3_DATA_F1_0_WIDTH 17U
+#define LPDDR4__MR3_DATA_F1_0__REG DENALI_CTL_228
+#define LPDDR4__MR3_DATA_F1_0__FLD LPDDR4__DENALI_CTL_228__MR3_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_229_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_229_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_229__MR3_DATA_F2_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_229__MR3_DATA_F2_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_229__MR3_DATA_F2_0_WIDTH 17U
+#define LPDDR4__MR3_DATA_F2_0__REG DENALI_CTL_229
+#define LPDDR4__MR3_DATA_F2_0__FLD LPDDR4__DENALI_CTL_229__MR3_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_230_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_230_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_230__MR3_DATA_F0_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_230__MR3_DATA_F0_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_230__MR3_DATA_F0_1_WIDTH 17U
+#define LPDDR4__MR3_DATA_F0_1__REG DENALI_CTL_230
+#define LPDDR4__MR3_DATA_F0_1__FLD LPDDR4__DENALI_CTL_230__MR3_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_231_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_231_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_231__MR3_DATA_F1_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_231__MR3_DATA_F1_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_231__MR3_DATA_F1_1_WIDTH 17U
+#define LPDDR4__MR3_DATA_F1_1__REG DENALI_CTL_231
+#define LPDDR4__MR3_DATA_F1_1__FLD LPDDR4__DENALI_CTL_231__MR3_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_232_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_232_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_232__MR3_DATA_F2_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_232__MR3_DATA_F2_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_232__MR3_DATA_F2_1_WIDTH 17U
+#define LPDDR4__MR3_DATA_F2_1__REG DENALI_CTL_232
+#define LPDDR4__MR3_DATA_F2_1__FLD LPDDR4__DENALI_CTL_232__MR3_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_233_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_233_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_233__MR4_DATA_F0_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_233__MR4_DATA_F0_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_233__MR4_DATA_F0_0_WIDTH 17U
+#define LPDDR4__MR4_DATA_F0_0__REG DENALI_CTL_233
+#define LPDDR4__MR4_DATA_F0_0__FLD LPDDR4__DENALI_CTL_233__MR4_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_234_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_234_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_234__MR4_DATA_F1_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_234__MR4_DATA_F1_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_234__MR4_DATA_F1_0_WIDTH 17U
+#define LPDDR4__MR4_DATA_F1_0__REG DENALI_CTL_234
+#define LPDDR4__MR4_DATA_F1_0__FLD LPDDR4__DENALI_CTL_234__MR4_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_235_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_235_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_235__MR4_DATA_F2_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_235__MR4_DATA_F2_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_235__MR4_DATA_F2_0_WIDTH 17U
+#define LPDDR4__MR4_DATA_F2_0__REG DENALI_CTL_235
+#define LPDDR4__MR4_DATA_F2_0__FLD LPDDR4__DENALI_CTL_235__MR4_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_236_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_236_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_236__MR4_DATA_F0_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_236__MR4_DATA_F0_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_236__MR4_DATA_F0_1_WIDTH 17U
+#define LPDDR4__MR4_DATA_F0_1__REG DENALI_CTL_236
+#define LPDDR4__MR4_DATA_F0_1__FLD LPDDR4__DENALI_CTL_236__MR4_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_237_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_237_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_237__MR4_DATA_F1_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_237__MR4_DATA_F1_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_237__MR4_DATA_F1_1_WIDTH 17U
+#define LPDDR4__MR4_DATA_F1_1__REG DENALI_CTL_237
+#define LPDDR4__MR4_DATA_F1_1__FLD LPDDR4__DENALI_CTL_237__MR4_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_238_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_238_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_238__MR4_DATA_F2_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_238__MR4_DATA_F2_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_238__MR4_DATA_F2_1_WIDTH 17U
+#define LPDDR4__MR4_DATA_F2_1__REG DENALI_CTL_238
+#define LPDDR4__MR4_DATA_F2_1__FLD LPDDR4__DENALI_CTL_238__MR4_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_239_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_239_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_239__MR5_DATA_F0_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_239__MR5_DATA_F0_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_239__MR5_DATA_F0_0_WIDTH 17U
+#define LPDDR4__MR5_DATA_F0_0__REG DENALI_CTL_239
+#define LPDDR4__MR5_DATA_F0_0__FLD LPDDR4__DENALI_CTL_239__MR5_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_240_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_240_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_240__MR5_DATA_F1_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_240__MR5_DATA_F1_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_240__MR5_DATA_F1_0_WIDTH 17U
+#define LPDDR4__MR5_DATA_F1_0__REG DENALI_CTL_240
+#define LPDDR4__MR5_DATA_F1_0__FLD LPDDR4__DENALI_CTL_240__MR5_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_241_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_241_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_241__MR5_DATA_F2_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_241__MR5_DATA_F2_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_241__MR5_DATA_F2_0_WIDTH 17U
+#define LPDDR4__MR5_DATA_F2_0__REG DENALI_CTL_241
+#define LPDDR4__MR5_DATA_F2_0__FLD LPDDR4__DENALI_CTL_241__MR5_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_242_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_242_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_242__MR5_DATA_F0_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_242__MR5_DATA_F0_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_242__MR5_DATA_F0_1_WIDTH 17U
+#define LPDDR4__MR5_DATA_F0_1__REG DENALI_CTL_242
+#define LPDDR4__MR5_DATA_F0_1__FLD LPDDR4__DENALI_CTL_242__MR5_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_243_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_243_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_243__MR5_DATA_F1_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_243__MR5_DATA_F1_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_243__MR5_DATA_F1_1_WIDTH 17U
+#define LPDDR4__MR5_DATA_F1_1__REG DENALI_CTL_243
+#define LPDDR4__MR5_DATA_F1_1__FLD LPDDR4__DENALI_CTL_243__MR5_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_244_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_244_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_244__MR5_DATA_F2_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_244__MR5_DATA_F2_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_244__MR5_DATA_F2_1_WIDTH 17U
+#define LPDDR4__MR5_DATA_F2_1__REG DENALI_CTL_244
+#define LPDDR4__MR5_DATA_F2_1__FLD LPDDR4__DENALI_CTL_244__MR5_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_245_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_245_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_245__MR6_DATA_F0_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_245__MR6_DATA_F0_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_245__MR6_DATA_F0_0_WIDTH 17U
+#define LPDDR4__MR6_DATA_F0_0__REG DENALI_CTL_245
+#define LPDDR4__MR6_DATA_F0_0__FLD LPDDR4__DENALI_CTL_245__MR6_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_246_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_246_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_246__MR6_DATA_F1_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_246__MR6_DATA_F1_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_246__MR6_DATA_F1_0_WIDTH 17U
+#define LPDDR4__MR6_DATA_F1_0__REG DENALI_CTL_246
+#define LPDDR4__MR6_DATA_F1_0__FLD LPDDR4__DENALI_CTL_246__MR6_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_247_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_247_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_247__MR6_DATA_F2_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_247__MR6_DATA_F2_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_247__MR6_DATA_F2_0_WIDTH 17U
+#define LPDDR4__MR6_DATA_F2_0__REG DENALI_CTL_247
+#define LPDDR4__MR6_DATA_F2_0__FLD LPDDR4__DENALI_CTL_247__MR6_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_248_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_248_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_248__MR6_DATA_F0_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_248__MR6_DATA_F0_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_248__MR6_DATA_F0_1_WIDTH 17U
+#define LPDDR4__MR6_DATA_F0_1__REG DENALI_CTL_248
+#define LPDDR4__MR6_DATA_F0_1__FLD LPDDR4__DENALI_CTL_248__MR6_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_249_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_249_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_249__MR6_DATA_F1_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_249__MR6_DATA_F1_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_249__MR6_DATA_F1_1_WIDTH 17U
+#define LPDDR4__MR6_DATA_F1_1__REG DENALI_CTL_249
+#define LPDDR4__MR6_DATA_F1_1__FLD LPDDR4__DENALI_CTL_249__MR6_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_250_READ_MASK 0xFF01FFFFU
+#define LPDDR4__DENALI_CTL_250_WRITE_MASK 0xFF01FFFFU
+#define LPDDR4__DENALI_CTL_250__MR6_DATA_F2_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_250__MR6_DATA_F2_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_250__MR6_DATA_F2_1_WIDTH 17U
+#define LPDDR4__MR6_DATA_F2_1__REG DENALI_CTL_250
+#define LPDDR4__MR6_DATA_F2_1__FLD LPDDR4__DENALI_CTL_250__MR6_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_250__MR8_DATA_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_250__MR8_DATA_0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_250__MR8_DATA_0_WIDTH 8U
+#define LPDDR4__MR8_DATA_0__REG DENALI_CTL_250
+#define LPDDR4__MR8_DATA_0__FLD LPDDR4__DENALI_CTL_250__MR8_DATA_0
+
+#define LPDDR4__DENALI_CTL_251_READ_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_251_WRITE_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_251__MR8_DATA_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_251__MR8_DATA_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_251__MR8_DATA_1_WIDTH 8U
+#define LPDDR4__MR8_DATA_1__REG DENALI_CTL_251
+#define LPDDR4__MR8_DATA_1__FLD LPDDR4__DENALI_CTL_251__MR8_DATA_1
+
+#define LPDDR4__DENALI_CTL_251__MR10_DATA_F0_0_MASK 0x01FFFF00U
+#define LPDDR4__DENALI_CTL_251__MR10_DATA_F0_0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_251__MR10_DATA_F0_0_WIDTH 17U
+#define LPDDR4__MR10_DATA_F0_0__REG DENALI_CTL_251
+#define LPDDR4__MR10_DATA_F0_0__FLD LPDDR4__DENALI_CTL_251__MR10_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_252_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_252_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_252__MR10_DATA_F1_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_252__MR10_DATA_F1_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_252__MR10_DATA_F1_0_WIDTH 17U
+#define LPDDR4__MR10_DATA_F1_0__REG DENALI_CTL_252
+#define LPDDR4__MR10_DATA_F1_0__FLD LPDDR4__DENALI_CTL_252__MR10_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_253_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_253_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_253__MR10_DATA_F2_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_253__MR10_DATA_F2_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_253__MR10_DATA_F2_0_WIDTH 17U
+#define LPDDR4__MR10_DATA_F2_0__REG DENALI_CTL_253
+#define LPDDR4__MR10_DATA_F2_0__FLD LPDDR4__DENALI_CTL_253__MR10_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_254_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_254_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_254__MR10_DATA_F0_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_254__MR10_DATA_F0_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_254__MR10_DATA_F0_1_WIDTH 17U
+#define LPDDR4__MR10_DATA_F0_1__REG DENALI_CTL_254
+#define LPDDR4__MR10_DATA_F0_1__FLD LPDDR4__DENALI_CTL_254__MR10_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_255_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_255_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_255__MR10_DATA_F1_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_255__MR10_DATA_F1_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_255__MR10_DATA_F1_1_WIDTH 17U
+#define LPDDR4__MR10_DATA_F1_1__REG DENALI_CTL_255
+#define LPDDR4__MR10_DATA_F1_1__FLD LPDDR4__DENALI_CTL_255__MR10_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_256_READ_MASK 0xFF01FFFFU
+#define LPDDR4__DENALI_CTL_256_WRITE_MASK 0xFF01FFFFU
+#define LPDDR4__DENALI_CTL_256__MR10_DATA_F2_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_256__MR10_DATA_F2_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_256__MR10_DATA_F2_1_WIDTH 17U
+#define LPDDR4__MR10_DATA_F2_1__REG DENALI_CTL_256
+#define LPDDR4__MR10_DATA_F2_1__FLD LPDDR4__DENALI_CTL_256__MR10_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_256__MR11_DATA_F0_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_256__MR11_DATA_F0_0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_256__MR11_DATA_F0_0_WIDTH 8U
+#define LPDDR4__MR11_DATA_F0_0__REG DENALI_CTL_256
+#define LPDDR4__MR11_DATA_F0_0__FLD LPDDR4__DENALI_CTL_256__MR11_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_257_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_257_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_257__MR11_DATA_F1_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_257__MR11_DATA_F1_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_257__MR11_DATA_F1_0_WIDTH 8U
+#define LPDDR4__MR11_DATA_F1_0__REG DENALI_CTL_257
+#define LPDDR4__MR11_DATA_F1_0__FLD LPDDR4__DENALI_CTL_257__MR11_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_257__MR11_DATA_F2_0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_257__MR11_DATA_F2_0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_257__MR11_DATA_F2_0_WIDTH 8U
+#define LPDDR4__MR11_DATA_F2_0__REG DENALI_CTL_257
+#define LPDDR4__MR11_DATA_F2_0__FLD LPDDR4__DENALI_CTL_257__MR11_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_257__MR11_DATA_F0_1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_257__MR11_DATA_F0_1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_257__MR11_DATA_F0_1_WIDTH 8U
+#define LPDDR4__MR11_DATA_F0_1__REG DENALI_CTL_257
+#define LPDDR4__MR11_DATA_F0_1__FLD LPDDR4__DENALI_CTL_257__MR11_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_257__MR11_DATA_F1_1_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_257__MR11_DATA_F1_1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_257__MR11_DATA_F1_1_WIDTH 8U
+#define LPDDR4__MR11_DATA_F1_1__REG DENALI_CTL_257
+#define LPDDR4__MR11_DATA_F1_1__FLD LPDDR4__DENALI_CTL_257__MR11_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_258_READ_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_258_WRITE_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_258__MR11_DATA_F2_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_258__MR11_DATA_F2_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_258__MR11_DATA_F2_1_WIDTH 8U
+#define LPDDR4__MR11_DATA_F2_1__REG DENALI_CTL_258
+#define LPDDR4__MR11_DATA_F2_1__FLD LPDDR4__DENALI_CTL_258__MR11_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_258__MR12_DATA_F0_0_MASK 0x01FFFF00U
+#define LPDDR4__DENALI_CTL_258__MR12_DATA_F0_0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_258__MR12_DATA_F0_0_WIDTH 17U
+#define LPDDR4__MR12_DATA_F0_0__REG DENALI_CTL_258
+#define LPDDR4__MR12_DATA_F0_0__FLD LPDDR4__DENALI_CTL_258__MR12_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_259_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_259_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_259__MR12_DATA_F1_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_259__MR12_DATA_F1_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_259__MR12_DATA_F1_0_WIDTH 17U
+#define LPDDR4__MR12_DATA_F1_0__REG DENALI_CTL_259
+#define LPDDR4__MR12_DATA_F1_0__FLD LPDDR4__DENALI_CTL_259__MR12_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_260_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_260_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_260__MR12_DATA_F2_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_260__MR12_DATA_F2_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_260__MR12_DATA_F2_0_WIDTH 17U
+#define LPDDR4__MR12_DATA_F2_0__REG DENALI_CTL_260
+#define LPDDR4__MR12_DATA_F2_0__FLD LPDDR4__DENALI_CTL_260__MR12_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_261_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_261_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_261__MR12_DATA_F0_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_261__MR12_DATA_F0_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_261__MR12_DATA_F0_1_WIDTH 17U
+#define LPDDR4__MR12_DATA_F0_1__REG DENALI_CTL_261
+#define LPDDR4__MR12_DATA_F0_1__FLD LPDDR4__DENALI_CTL_261__MR12_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_262_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_262_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_262__MR12_DATA_F1_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_262__MR12_DATA_F1_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_262__MR12_DATA_F1_1_WIDTH 17U
+#define LPDDR4__MR12_DATA_F1_1__REG DENALI_CTL_262
+#define LPDDR4__MR12_DATA_F1_1__FLD LPDDR4__DENALI_CTL_262__MR12_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_263_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_263_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_263__MR12_DATA_F2_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_263__MR12_DATA_F2_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_263__MR12_DATA_F2_1_WIDTH 17U
+#define LPDDR4__MR12_DATA_F2_1__REG DENALI_CTL_263
+#define LPDDR4__MR12_DATA_F2_1__FLD LPDDR4__DENALI_CTL_263__MR12_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_264_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_264_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_264__MR13_DATA_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_264__MR13_DATA_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_264__MR13_DATA_0_WIDTH 17U
+#define LPDDR4__MR13_DATA_0__REG DENALI_CTL_264
+#define LPDDR4__MR13_DATA_0__FLD LPDDR4__DENALI_CTL_264__MR13_DATA_0
+
+#define LPDDR4__DENALI_CTL_265_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_265_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_265__MR13_DATA_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_265__MR13_DATA_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_265__MR13_DATA_1_WIDTH 17U
+#define LPDDR4__MR13_DATA_1__REG DENALI_CTL_265
+#define LPDDR4__MR13_DATA_1__FLD LPDDR4__DENALI_CTL_265__MR13_DATA_1
+
+#define LPDDR4__DENALI_CTL_266_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_266_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_266__MR14_DATA_F0_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_266__MR14_DATA_F0_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_266__MR14_DATA_F0_0_WIDTH 17U
+#define LPDDR4__MR14_DATA_F0_0__REG DENALI_CTL_266
+#define LPDDR4__MR14_DATA_F0_0__FLD LPDDR4__DENALI_CTL_266__MR14_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_267_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_267_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_267__MR14_DATA_F1_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_267__MR14_DATA_F1_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_267__MR14_DATA_F1_0_WIDTH 17U
+#define LPDDR4__MR14_DATA_F1_0__REG DENALI_CTL_267
+#define LPDDR4__MR14_DATA_F1_0__FLD LPDDR4__DENALI_CTL_267__MR14_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_268_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_268_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_268__MR14_DATA_F2_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_268__MR14_DATA_F2_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_268__MR14_DATA_F2_0_WIDTH 17U
+#define LPDDR4__MR14_DATA_F2_0__REG DENALI_CTL_268
+#define LPDDR4__MR14_DATA_F2_0__FLD LPDDR4__DENALI_CTL_268__MR14_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_269_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_269_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_269__MR14_DATA_F0_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_269__MR14_DATA_F0_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_269__MR14_DATA_F0_1_WIDTH 17U
+#define LPDDR4__MR14_DATA_F0_1__REG DENALI_CTL_269
+#define LPDDR4__MR14_DATA_F0_1__FLD LPDDR4__DENALI_CTL_269__MR14_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_270_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_270_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_270__MR14_DATA_F1_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_270__MR14_DATA_F1_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_270__MR14_DATA_F1_1_WIDTH 17U
+#define LPDDR4__MR14_DATA_F1_1__REG DENALI_CTL_270
+#define LPDDR4__MR14_DATA_F1_1__FLD LPDDR4__DENALI_CTL_270__MR14_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_271_READ_MASK 0xFF01FFFFU
+#define LPDDR4__DENALI_CTL_271_WRITE_MASK 0xFF01FFFFU
+#define LPDDR4__DENALI_CTL_271__MR14_DATA_F2_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_271__MR14_DATA_F2_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_271__MR14_DATA_F2_1_WIDTH 17U
+#define LPDDR4__MR14_DATA_F2_1__REG DENALI_CTL_271
+#define LPDDR4__MR14_DATA_F2_1__FLD LPDDR4__DENALI_CTL_271__MR14_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_271__MR16_DATA_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_271__MR16_DATA_0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_271__MR16_DATA_0_WIDTH 8U
+#define LPDDR4__MR16_DATA_0__REG DENALI_CTL_271
+#define LPDDR4__MR16_DATA_0__FLD LPDDR4__DENALI_CTL_271__MR16_DATA_0
+
+#define LPDDR4__DENALI_CTL_272_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_272_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_272__MR16_DATA_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_272__MR16_DATA_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_272__MR16_DATA_1_WIDTH 8U
+#define LPDDR4__MR16_DATA_1__REG DENALI_CTL_272
+#define LPDDR4__MR16_DATA_1__FLD LPDDR4__DENALI_CTL_272__MR16_DATA_1
+
+#define LPDDR4__DENALI_CTL_272__MR17_DATA_0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_272__MR17_DATA_0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_272__MR17_DATA_0_WIDTH 8U
+#define LPDDR4__MR17_DATA_0__REG DENALI_CTL_272
+#define LPDDR4__MR17_DATA_0__FLD LPDDR4__DENALI_CTL_272__MR17_DATA_0
+
+#define LPDDR4__DENALI_CTL_272__MR17_DATA_1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_272__MR17_DATA_1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_272__MR17_DATA_1_WIDTH 8U
+#define LPDDR4__MR17_DATA_1__REG DENALI_CTL_272
+#define LPDDR4__MR17_DATA_1__FLD LPDDR4__DENALI_CTL_272__MR17_DATA_1
+
+#define LPDDR4__DENALI_CTL_272__MR20_DATA_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_272__MR20_DATA_0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_272__MR20_DATA_0_WIDTH 8U
+#define LPDDR4__MR20_DATA_0__REG DENALI_CTL_272
+#define LPDDR4__MR20_DATA_0__FLD LPDDR4__DENALI_CTL_272__MR20_DATA_0
+
+#define LPDDR4__DENALI_CTL_273_READ_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_273_WRITE_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_273__MR20_DATA_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_273__MR20_DATA_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_273__MR20_DATA_1_WIDTH 8U
+#define LPDDR4__MR20_DATA_1__REG DENALI_CTL_273
+#define LPDDR4__MR20_DATA_1__FLD LPDDR4__DENALI_CTL_273__MR20_DATA_1
+
+#define LPDDR4__DENALI_CTL_273__MR22_DATA_F0_0_MASK 0x01FFFF00U
+#define LPDDR4__DENALI_CTL_273__MR22_DATA_F0_0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_273__MR22_DATA_F0_0_WIDTH 17U
+#define LPDDR4__MR22_DATA_F0_0__REG DENALI_CTL_273
+#define LPDDR4__MR22_DATA_F0_0__FLD LPDDR4__DENALI_CTL_273__MR22_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_274_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_274_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_274__MR22_DATA_F1_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_274__MR22_DATA_F1_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_274__MR22_DATA_F1_0_WIDTH 17U
+#define LPDDR4__MR22_DATA_F1_0__REG DENALI_CTL_274
+#define LPDDR4__MR22_DATA_F1_0__FLD LPDDR4__DENALI_CTL_274__MR22_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_275_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_275_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_275__MR22_DATA_F2_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_275__MR22_DATA_F2_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_275__MR22_DATA_F2_0_WIDTH 17U
+#define LPDDR4__MR22_DATA_F2_0__REG DENALI_CTL_275
+#define LPDDR4__MR22_DATA_F2_0__FLD LPDDR4__DENALI_CTL_275__MR22_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_276_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_276_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_276__MR22_DATA_F0_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_276__MR22_DATA_F0_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_276__MR22_DATA_F0_1_WIDTH 17U
+#define LPDDR4__MR22_DATA_F0_1__REG DENALI_CTL_276
+#define LPDDR4__MR22_DATA_F0_1__FLD LPDDR4__DENALI_CTL_276__MR22_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_277_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_277_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_277__MR22_DATA_F1_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_277__MR22_DATA_F1_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_277__MR22_DATA_F1_1_WIDTH 17U
+#define LPDDR4__MR22_DATA_F1_1__REG DENALI_CTL_277
+#define LPDDR4__MR22_DATA_F1_1__FLD LPDDR4__DENALI_CTL_277__MR22_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_278_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_278_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_278__MR22_DATA_F2_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_278__MR22_DATA_F2_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_278__MR22_DATA_F2_1_WIDTH 17U
+#define LPDDR4__MR22_DATA_F2_1__REG DENALI_CTL_278
+#define LPDDR4__MR22_DATA_F2_1__FLD LPDDR4__DENALI_CTL_278__MR22_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_279_READ_MASK 0x0101FFFFU
+#define LPDDR4__DENALI_CTL_279_WRITE_MASK 0x0101FFFFU
+#define LPDDR4__DENALI_CTL_279__MR23_DATA_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_279__MR23_DATA_SHIFT 0U
+#define LPDDR4__DENALI_CTL_279__MR23_DATA_WIDTH 17U
+#define LPDDR4__MR23_DATA__REG DENALI_CTL_279
+#define LPDDR4__MR23_DATA__FLD LPDDR4__DENALI_CTL_279__MR23_DATA
+
+#define LPDDR4__DENALI_CTL_279__MR_FSP_DATA_VALID_F0_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_279__MR_FSP_DATA_VALID_F0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_279__MR_FSP_DATA_VALID_F0_WIDTH 1U
+#define LPDDR4__DENALI_CTL_279__MR_FSP_DATA_VALID_F0_WOCLR 0U
+#define LPDDR4__DENALI_CTL_279__MR_FSP_DATA_VALID_F0_WOSET 0U
+#define LPDDR4__MR_FSP_DATA_VALID_F0__REG DENALI_CTL_279
+#define LPDDR4__MR_FSP_DATA_VALID_F0__FLD LPDDR4__DENALI_CTL_279__MR_FSP_DATA_VALID_F0
+
+#define LPDDR4__DENALI_CTL_280_READ_MASK 0x01010101U
+#define LPDDR4__DENALI_CTL_280_WRITE_MASK 0x01010101U
+#define LPDDR4__DENALI_CTL_280__MR_FSP_DATA_VALID_F1_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_280__MR_FSP_DATA_VALID_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_280__MR_FSP_DATA_VALID_F1_WIDTH 1U
+#define LPDDR4__DENALI_CTL_280__MR_FSP_DATA_VALID_F1_WOCLR 0U
+#define LPDDR4__DENALI_CTL_280__MR_FSP_DATA_VALID_F1_WOSET 0U
+#define LPDDR4__MR_FSP_DATA_VALID_F1__REG DENALI_CTL_280
+#define LPDDR4__MR_FSP_DATA_VALID_F1__FLD LPDDR4__DENALI_CTL_280__MR_FSP_DATA_VALID_F1
+
+#define LPDDR4__DENALI_CTL_280__MR_FSP_DATA_VALID_F2_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_280__MR_FSP_DATA_VALID_F2_SHIFT 8U
+#define LPDDR4__DENALI_CTL_280__MR_FSP_DATA_VALID_F2_WIDTH 1U
+#define LPDDR4__DENALI_CTL_280__MR_FSP_DATA_VALID_F2_WOCLR 0U
+#define LPDDR4__DENALI_CTL_280__MR_FSP_DATA_VALID_F2_WOSET 0U
+#define LPDDR4__MR_FSP_DATA_VALID_F2__REG DENALI_CTL_280
+#define LPDDR4__MR_FSP_DATA_VALID_F2__FLD LPDDR4__DENALI_CTL_280__MR_FSP_DATA_VALID_F2
+
+#define LPDDR4__DENALI_CTL_280__DFS_FSP_INSYNC_ACTIVE_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_280__DFS_FSP_INSYNC_ACTIVE_SHIFT 16U
+#define LPDDR4__DENALI_CTL_280__DFS_FSP_INSYNC_ACTIVE_WIDTH 1U
+#define LPDDR4__DENALI_CTL_280__DFS_FSP_INSYNC_ACTIVE_WOCLR 0U
+#define LPDDR4__DENALI_CTL_280__DFS_FSP_INSYNC_ACTIVE_WOSET 0U
+#define LPDDR4__DFS_FSP_INSYNC_ACTIVE__REG DENALI_CTL_280
+#define LPDDR4__DFS_FSP_INSYNC_ACTIVE__FLD LPDDR4__DENALI_CTL_280__DFS_FSP_INSYNC_ACTIVE
+
+#define LPDDR4__DENALI_CTL_280__DFS_FSP_INSYNC_INACTIVE_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_280__DFS_FSP_INSYNC_INACTIVE_SHIFT 24U
+#define LPDDR4__DENALI_CTL_280__DFS_FSP_INSYNC_INACTIVE_WIDTH 1U
+#define LPDDR4__DENALI_CTL_280__DFS_FSP_INSYNC_INACTIVE_WOCLR 0U
+#define LPDDR4__DENALI_CTL_280__DFS_FSP_INSYNC_INACTIVE_WOSET 0U
+#define LPDDR4__DFS_FSP_INSYNC_INACTIVE__REG DENALI_CTL_280
+#define LPDDR4__DFS_FSP_INSYNC_INACTIVE__FLD LPDDR4__DENALI_CTL_280__DFS_FSP_INSYNC_INACTIVE
+
+#define LPDDR4__DENALI_CTL_281_READ_MASK 0x01010101U
+#define LPDDR4__DENALI_CTL_281_WRITE_MASK 0x01010101U
+#define LPDDR4__DENALI_CTL_281__FSP_PHY_UPDATE_MRW_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_281__FSP_PHY_UPDATE_MRW_SHIFT 0U
+#define LPDDR4__DENALI_CTL_281__FSP_PHY_UPDATE_MRW_WIDTH 1U
+#define LPDDR4__DENALI_CTL_281__FSP_PHY_UPDATE_MRW_WOCLR 0U
+#define LPDDR4__DENALI_CTL_281__FSP_PHY_UPDATE_MRW_WOSET 0U
+#define LPDDR4__FSP_PHY_UPDATE_MRW__REG DENALI_CTL_281
+#define LPDDR4__FSP_PHY_UPDATE_MRW__FLD LPDDR4__DENALI_CTL_281__FSP_PHY_UPDATE_MRW
+
+#define LPDDR4__DENALI_CTL_281__DFS_ALWAYS_WRITE_FSP_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_281__DFS_ALWAYS_WRITE_FSP_SHIFT 8U
+#define LPDDR4__DENALI_CTL_281__DFS_ALWAYS_WRITE_FSP_WIDTH 1U
+#define LPDDR4__DENALI_CTL_281__DFS_ALWAYS_WRITE_FSP_WOCLR 0U
+#define LPDDR4__DENALI_CTL_281__DFS_ALWAYS_WRITE_FSP_WOSET 0U
+#define LPDDR4__DFS_ALWAYS_WRITE_FSP__REG DENALI_CTL_281
+#define LPDDR4__DFS_ALWAYS_WRITE_FSP__FLD LPDDR4__DENALI_CTL_281__DFS_ALWAYS_WRITE_FSP
+
+#define LPDDR4__DENALI_CTL_281__FSP_STATUS_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_281__FSP_STATUS_SHIFT 16U
+#define LPDDR4__DENALI_CTL_281__FSP_STATUS_WIDTH 1U
+#define LPDDR4__DENALI_CTL_281__FSP_STATUS_WOCLR 0U
+#define LPDDR4__DENALI_CTL_281__FSP_STATUS_WOSET 0U
+#define LPDDR4__FSP_STATUS__REG DENALI_CTL_281
+#define LPDDR4__FSP_STATUS__FLD LPDDR4__DENALI_CTL_281__FSP_STATUS
+
+#define LPDDR4__DENALI_CTL_281__FSP_OP_CURRENT_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_281__FSP_OP_CURRENT_SHIFT 24U
+#define LPDDR4__DENALI_CTL_281__FSP_OP_CURRENT_WIDTH 1U
+#define LPDDR4__DENALI_CTL_281__FSP_OP_CURRENT_WOCLR 0U
+#define LPDDR4__DENALI_CTL_281__FSP_OP_CURRENT_WOSET 0U
+#define LPDDR4__FSP_OP_CURRENT__REG DENALI_CTL_281
+#define LPDDR4__FSP_OP_CURRENT__FLD LPDDR4__DENALI_CTL_281__FSP_OP_CURRENT
+
+#define LPDDR4__DENALI_CTL_282_READ_MASK 0x03010101U
+#define LPDDR4__DENALI_CTL_282_WRITE_MASK 0x03010101U
+#define LPDDR4__DENALI_CTL_282__FSP_WR_CURRENT_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_282__FSP_WR_CURRENT_SHIFT 0U
+#define LPDDR4__DENALI_CTL_282__FSP_WR_CURRENT_WIDTH 1U
+#define LPDDR4__DENALI_CTL_282__FSP_WR_CURRENT_WOCLR 0U
+#define LPDDR4__DENALI_CTL_282__FSP_WR_CURRENT_WOSET 0U
+#define LPDDR4__FSP_WR_CURRENT__REG DENALI_CTL_282
+#define LPDDR4__FSP_WR_CURRENT__FLD LPDDR4__DENALI_CTL_282__FSP_WR_CURRENT
+
+#define LPDDR4__DENALI_CTL_282__FSP0_FRC_VALID_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_282__FSP0_FRC_VALID_SHIFT 8U
+#define LPDDR4__DENALI_CTL_282__FSP0_FRC_VALID_WIDTH 1U
+#define LPDDR4__DENALI_CTL_282__FSP0_FRC_VALID_WOCLR 0U
+#define LPDDR4__DENALI_CTL_282__FSP0_FRC_VALID_WOSET 0U
+#define LPDDR4__FSP0_FRC_VALID__REG DENALI_CTL_282
+#define LPDDR4__FSP0_FRC_VALID__FLD LPDDR4__DENALI_CTL_282__FSP0_FRC_VALID
+
+#define LPDDR4__DENALI_CTL_282__FSP1_FRC_VALID_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_282__FSP1_FRC_VALID_SHIFT 16U
+#define LPDDR4__DENALI_CTL_282__FSP1_FRC_VALID_WIDTH 1U
+#define LPDDR4__DENALI_CTL_282__FSP1_FRC_VALID_WOCLR 0U
+#define LPDDR4__DENALI_CTL_282__FSP1_FRC_VALID_WOSET 0U
+#define LPDDR4__FSP1_FRC_VALID__REG DENALI_CTL_282
+#define LPDDR4__FSP1_FRC_VALID__FLD LPDDR4__DENALI_CTL_282__FSP1_FRC_VALID
+
+#define LPDDR4__DENALI_CTL_282__FSP0_FRC_MASK 0x03000000U
+#define LPDDR4__DENALI_CTL_282__FSP0_FRC_SHIFT 24U
+#define LPDDR4__DENALI_CTL_282__FSP0_FRC_WIDTH 2U
+#define LPDDR4__FSP0_FRC__REG DENALI_CTL_282
+#define LPDDR4__FSP0_FRC__FLD LPDDR4__DENALI_CTL_282__FSP0_FRC
+
+#define LPDDR4__DENALI_CTL_283_READ_MASK 0x3F030003U
+#define LPDDR4__DENALI_CTL_283_WRITE_MASK 0x3F030003U
+#define LPDDR4__DENALI_CTL_283__FSP1_FRC_MASK 0x00000003U
+#define LPDDR4__DENALI_CTL_283__FSP1_FRC_SHIFT 0U
+#define LPDDR4__DENALI_CTL_283__FSP1_FRC_WIDTH 2U
+#define LPDDR4__FSP1_FRC__REG DENALI_CTL_283
+#define LPDDR4__FSP1_FRC__FLD LPDDR4__DENALI_CTL_283__FSP1_FRC
+
+#define LPDDR4__DENALI_CTL_283__BIST_GO_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_283__BIST_GO_SHIFT 8U
+#define LPDDR4__DENALI_CTL_283__BIST_GO_WIDTH 1U
+#define LPDDR4__DENALI_CTL_283__BIST_GO_WOCLR 0U
+#define LPDDR4__DENALI_CTL_283__BIST_GO_WOSET 0U
+#define LPDDR4__BIST_GO__REG DENALI_CTL_283
+#define LPDDR4__BIST_GO__FLD LPDDR4__DENALI_CTL_283__BIST_GO
+
+#define LPDDR4__DENALI_CTL_283__BIST_RESULT_MASK 0x00030000U
+#define LPDDR4__DENALI_CTL_283__BIST_RESULT_SHIFT 16U
+#define LPDDR4__DENALI_CTL_283__BIST_RESULT_WIDTH 2U
+#define LPDDR4__BIST_RESULT__REG DENALI_CTL_283
+#define LPDDR4__BIST_RESULT__FLD LPDDR4__DENALI_CTL_283__BIST_RESULT
+
+#define LPDDR4__DENALI_CTL_283__ADDR_SPACE_MASK 0x3F000000U
+#define LPDDR4__DENALI_CTL_283__ADDR_SPACE_SHIFT 24U
+#define LPDDR4__DENALI_CTL_283__ADDR_SPACE_WIDTH 6U
+#define LPDDR4__ADDR_SPACE__REG DENALI_CTL_283
+#define LPDDR4__ADDR_SPACE__FLD LPDDR4__DENALI_CTL_283__ADDR_SPACE
+
+#define LPDDR4__DENALI_CTL_284_READ_MASK 0x00000101U
+#define LPDDR4__DENALI_CTL_284_WRITE_MASK 0x00000101U
+#define LPDDR4__DENALI_CTL_284__BIST_DATA_CHECK_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_284__BIST_DATA_CHECK_SHIFT 0U
+#define LPDDR4__DENALI_CTL_284__BIST_DATA_CHECK_WIDTH 1U
+#define LPDDR4__DENALI_CTL_284__BIST_DATA_CHECK_WOCLR 0U
+#define LPDDR4__DENALI_CTL_284__BIST_DATA_CHECK_WOSET 0U
+#define LPDDR4__BIST_DATA_CHECK__REG DENALI_CTL_284
+#define LPDDR4__BIST_DATA_CHECK__FLD LPDDR4__DENALI_CTL_284__BIST_DATA_CHECK
+
+#define LPDDR4__DENALI_CTL_284__BIST_ADDR_CHECK_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_284__BIST_ADDR_CHECK_SHIFT 8U
+#define LPDDR4__DENALI_CTL_284__BIST_ADDR_CHECK_WIDTH 1U
+#define LPDDR4__DENALI_CTL_284__BIST_ADDR_CHECK_WOCLR 0U
+#define LPDDR4__DENALI_CTL_284__BIST_ADDR_CHECK_WOSET 0U
+#define LPDDR4__BIST_ADDR_CHECK__REG DENALI_CTL_284
+#define LPDDR4__BIST_ADDR_CHECK__FLD LPDDR4__DENALI_CTL_284__BIST_ADDR_CHECK
+
+#define LPDDR4__DENALI_CTL_285_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_285_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_285__BIST_START_ADDRESS_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_285__BIST_START_ADDRESS_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_285__BIST_START_ADDRESS_0_WIDTH 32U
+#define LPDDR4__BIST_START_ADDRESS_0__REG DENALI_CTL_285
+#define LPDDR4__BIST_START_ADDRESS_0__FLD LPDDR4__DENALI_CTL_285__BIST_START_ADDRESS_0
+
+#define LPDDR4__DENALI_CTL_286_READ_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_286_WRITE_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_286__BIST_START_ADDRESS_1_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_286__BIST_START_ADDRESS_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_286__BIST_START_ADDRESS_1_WIDTH 3U
+#define LPDDR4__BIST_START_ADDRESS_1__REG DENALI_CTL_286
+#define LPDDR4__BIST_START_ADDRESS_1__FLD LPDDR4__DENALI_CTL_286__BIST_START_ADDRESS_1
+
+#define LPDDR4__DENALI_CTL_287_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_287_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_287__BIST_DATA_MASK_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_287__BIST_DATA_MASK_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_287__BIST_DATA_MASK_0_WIDTH 32U
+#define LPDDR4__BIST_DATA_MASK_0__REG DENALI_CTL_287
+#define LPDDR4__BIST_DATA_MASK_0__FLD LPDDR4__DENALI_CTL_287__BIST_DATA_MASK_0
+
+#define LPDDR4__DENALI_CTL_288_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_288_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_288__BIST_DATA_MASK_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_288__BIST_DATA_MASK_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_288__BIST_DATA_MASK_1_WIDTH 32U
+#define LPDDR4__BIST_DATA_MASK_1__REG DENALI_CTL_288
+#define LPDDR4__BIST_DATA_MASK_1__FLD LPDDR4__DENALI_CTL_288__BIST_DATA_MASK_1
+
+#define LPDDR4__DENALI_CTL_289_READ_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_289_WRITE_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_289__BIST_TEST_MODE_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_289__BIST_TEST_MODE_SHIFT 0U
+#define LPDDR4__DENALI_CTL_289__BIST_TEST_MODE_WIDTH 3U
+#define LPDDR4__BIST_TEST_MODE__REG DENALI_CTL_289
+#define LPDDR4__BIST_TEST_MODE__FLD LPDDR4__DENALI_CTL_289__BIST_TEST_MODE
+
+#define LPDDR4__DENALI_CTL_290_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_290_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_290__BIST_DATA_PATTERN_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_290__BIST_DATA_PATTERN_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_290__BIST_DATA_PATTERN_0_WIDTH 32U
+#define LPDDR4__BIST_DATA_PATTERN_0__REG DENALI_CTL_290
+#define LPDDR4__BIST_DATA_PATTERN_0__FLD LPDDR4__DENALI_CTL_290__BIST_DATA_PATTERN_0
+
+#define LPDDR4__DENALI_CTL_291_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_291_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_291__BIST_DATA_PATTERN_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_291__BIST_DATA_PATTERN_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_291__BIST_DATA_PATTERN_1_WIDTH 32U
+#define LPDDR4__BIST_DATA_PATTERN_1__REG DENALI_CTL_291
+#define LPDDR4__BIST_DATA_PATTERN_1__FLD LPDDR4__DENALI_CTL_291__BIST_DATA_PATTERN_1
+
+#define LPDDR4__DENALI_CTL_292_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_292_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_292__BIST_DATA_PATTERN_2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_292__BIST_DATA_PATTERN_2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_292__BIST_DATA_PATTERN_2_WIDTH 32U
+#define LPDDR4__BIST_DATA_PATTERN_2__REG DENALI_CTL_292
+#define LPDDR4__BIST_DATA_PATTERN_2__FLD LPDDR4__DENALI_CTL_292__BIST_DATA_PATTERN_2
+
+#define LPDDR4__DENALI_CTL_293_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_293_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_293__BIST_DATA_PATTERN_3_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_293__BIST_DATA_PATTERN_3_SHIFT 0U
+#define LPDDR4__DENALI_CTL_293__BIST_DATA_PATTERN_3_WIDTH 32U
+#define LPDDR4__BIST_DATA_PATTERN_3__REG DENALI_CTL_293
+#define LPDDR4__BIST_DATA_PATTERN_3__FLD LPDDR4__DENALI_CTL_293__BIST_DATA_PATTERN_3
+
+#define LPDDR4__DENALI_CTL_294_READ_MASK 0x000FFF01U
+#define LPDDR4__DENALI_CTL_294_WRITE_MASK 0x000FFF01U
+#define LPDDR4__DENALI_CTL_294__BIST_RET_STATE_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_294__BIST_RET_STATE_SHIFT 0U
+#define LPDDR4__DENALI_CTL_294__BIST_RET_STATE_WIDTH 1U
+#define LPDDR4__DENALI_CTL_294__BIST_RET_STATE_WOCLR 0U
+#define LPDDR4__DENALI_CTL_294__BIST_RET_STATE_WOSET 0U
+#define LPDDR4__BIST_RET_STATE__REG DENALI_CTL_294
+#define LPDDR4__BIST_RET_STATE__FLD LPDDR4__DENALI_CTL_294__BIST_RET_STATE
+
+#define LPDDR4__DENALI_CTL_294__BIST_ERR_STOP_MASK 0x000FFF00U
+#define LPDDR4__DENALI_CTL_294__BIST_ERR_STOP_SHIFT 8U
+#define LPDDR4__DENALI_CTL_294__BIST_ERR_STOP_WIDTH 12U
+#define LPDDR4__BIST_ERR_STOP__REG DENALI_CTL_294
+#define LPDDR4__BIST_ERR_STOP__FLD LPDDR4__DENALI_CTL_294__BIST_ERR_STOP
+
+#define LPDDR4__DENALI_CTL_295_READ_MASK 0x1F000FFFU
+#define LPDDR4__DENALI_CTL_295_WRITE_MASK 0x1F000FFFU
+#define LPDDR4__DENALI_CTL_295__BIST_ERR_COUNT_MASK 0x00000FFFU
+#define LPDDR4__DENALI_CTL_295__BIST_ERR_COUNT_SHIFT 0U
+#define LPDDR4__DENALI_CTL_295__BIST_ERR_COUNT_WIDTH 12U
+#define LPDDR4__BIST_ERR_COUNT__REG DENALI_CTL_295
+#define LPDDR4__BIST_ERR_COUNT__FLD LPDDR4__DENALI_CTL_295__BIST_ERR_COUNT
+
+#define LPDDR4__DENALI_CTL_295__BIST_RET_STATE_EXIT_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_295__BIST_RET_STATE_EXIT_SHIFT 16U
+#define LPDDR4__DENALI_CTL_295__BIST_RET_STATE_EXIT_WIDTH 1U
+#define LPDDR4__DENALI_CTL_295__BIST_RET_STATE_EXIT_WOCLR 0U
+#define LPDDR4__DENALI_CTL_295__BIST_RET_STATE_EXIT_WOSET 0U
+#define LPDDR4__BIST_RET_STATE_EXIT__REG DENALI_CTL_295
+#define LPDDR4__BIST_RET_STATE_EXIT__FLD LPDDR4__DENALI_CTL_295__BIST_RET_STATE_EXIT
+
+#define LPDDR4__DENALI_CTL_295__LONG_COUNT_MASK_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_295__LONG_COUNT_MASK_SHIFT 24U
+#define LPDDR4__DENALI_CTL_295__LONG_COUNT_MASK_WIDTH 5U
+#define LPDDR4__LONG_COUNT_MASK__REG DENALI_CTL_295
+#define LPDDR4__LONG_COUNT_MASK__FLD LPDDR4__DENALI_CTL_295__LONG_COUNT_MASK
+
+#define LPDDR4__DENALI_CTL_296_READ_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_296_WRITE_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_296__AREF_NORM_THRESHOLD_MASK 0x0000001FU
+#define LPDDR4__DENALI_CTL_296__AREF_NORM_THRESHOLD_SHIFT 0U
+#define LPDDR4__DENALI_CTL_296__AREF_NORM_THRESHOLD_WIDTH 5U
+#define LPDDR4__AREF_NORM_THRESHOLD__REG DENALI_CTL_296
+#define LPDDR4__AREF_NORM_THRESHOLD__FLD LPDDR4__DENALI_CTL_296__AREF_NORM_THRESHOLD
+
+#define LPDDR4__DENALI_CTL_296__AREF_HIGH_THRESHOLD_MASK 0x00001F00U
+#define LPDDR4__DENALI_CTL_296__AREF_HIGH_THRESHOLD_SHIFT 8U
+#define LPDDR4__DENALI_CTL_296__AREF_HIGH_THRESHOLD_WIDTH 5U
+#define LPDDR4__AREF_HIGH_THRESHOLD__REG DENALI_CTL_296
+#define LPDDR4__AREF_HIGH_THRESHOLD__FLD LPDDR4__DENALI_CTL_296__AREF_HIGH_THRESHOLD
+
+#define LPDDR4__DENALI_CTL_296__AREF_MAX_DEFICIT_MASK 0x001F0000U
+#define LPDDR4__DENALI_CTL_296__AREF_MAX_DEFICIT_SHIFT 16U
+#define LPDDR4__DENALI_CTL_296__AREF_MAX_DEFICIT_WIDTH 5U
+#define LPDDR4__AREF_MAX_DEFICIT__REG DENALI_CTL_296
+#define LPDDR4__AREF_MAX_DEFICIT__FLD LPDDR4__DENALI_CTL_296__AREF_MAX_DEFICIT
+
+#define LPDDR4__DENALI_CTL_296__AREF_MAX_CREDIT_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_296__AREF_MAX_CREDIT_SHIFT 24U
+#define LPDDR4__DENALI_CTL_296__AREF_MAX_CREDIT_WIDTH 5U
+#define LPDDR4__AREF_MAX_CREDIT__REG DENALI_CTL_296
+#define LPDDR4__AREF_MAX_CREDIT__FLD LPDDR4__DENALI_CTL_296__AREF_MAX_CREDIT
+
+#define LPDDR4__DENALI_CTL_297_READ_MASK 0xFFFF070FU
+#define LPDDR4__DENALI_CTL_297_WRITE_MASK 0xFFFF070FU
+#define LPDDR4__DENALI_CTL_297__AREF_CMD_MAX_PER_TREFI_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_297__AREF_CMD_MAX_PER_TREFI_SHIFT 0U
+#define LPDDR4__DENALI_CTL_297__AREF_CMD_MAX_PER_TREFI_WIDTH 4U
+#define LPDDR4__AREF_CMD_MAX_PER_TREFI__REG DENALI_CTL_297
+#define LPDDR4__AREF_CMD_MAX_PER_TREFI__FLD LPDDR4__DENALI_CTL_297__AREF_CMD_MAX_PER_TREFI
+
+#define LPDDR4__DENALI_CTL_297__ZQCS_OPT_THRESHOLD_MASK 0x00000700U
+#define LPDDR4__DENALI_CTL_297__ZQCS_OPT_THRESHOLD_SHIFT 8U
+#define LPDDR4__DENALI_CTL_297__ZQCS_OPT_THRESHOLD_WIDTH 3U
+#define LPDDR4__ZQCS_OPT_THRESHOLD__REG DENALI_CTL_297
+#define LPDDR4__ZQCS_OPT_THRESHOLD__FLD LPDDR4__DENALI_CTL_297__ZQCS_OPT_THRESHOLD
+
+#define LPDDR4__DENALI_CTL_297__ZQ_CALSTART_NORM_THRESHOLD_F0_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_297__ZQ_CALSTART_NORM_THRESHOLD_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_297__ZQ_CALSTART_NORM_THRESHOLD_F0_WIDTH 16U
+#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F0__REG DENALI_CTL_297
+#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_297__ZQ_CALSTART_NORM_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_298_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_298_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_298__ZQ_CALSTART_HIGH_THRESHOLD_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_298__ZQ_CALSTART_HIGH_THRESHOLD_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_298__ZQ_CALSTART_HIGH_THRESHOLD_F0_WIDTH 16U
+#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F0__REG DENALI_CTL_298
+#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_298__ZQ_CALSTART_HIGH_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_298__ZQ_CALLATCH_HIGH_THRESHOLD_F0_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_298__ZQ_CALLATCH_HIGH_THRESHOLD_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_298__ZQ_CALLATCH_HIGH_THRESHOLD_F0_WIDTH 16U
+#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F0__REG DENALI_CTL_298
+#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_298__ZQ_CALLATCH_HIGH_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_299_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_299_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_299__ZQ_CS_NORM_THRESHOLD_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_299__ZQ_CS_NORM_THRESHOLD_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_299__ZQ_CS_NORM_THRESHOLD_F0_WIDTH 16U
+#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F0__REG DENALI_CTL_299
+#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_299__ZQ_CS_NORM_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_299__ZQ_CS_HIGH_THRESHOLD_F0_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_299__ZQ_CS_HIGH_THRESHOLD_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_299__ZQ_CS_HIGH_THRESHOLD_F0_WIDTH 16U
+#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F0__REG DENALI_CTL_299
+#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_299__ZQ_CS_HIGH_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_300_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_300_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_300__ZQ_CALSTART_TIMEOUT_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_300__ZQ_CALSTART_TIMEOUT_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_300__ZQ_CALSTART_TIMEOUT_F0_WIDTH 16U
+#define LPDDR4__ZQ_CALSTART_TIMEOUT_F0__REG DENALI_CTL_300
+#define LPDDR4__ZQ_CALSTART_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_300__ZQ_CALSTART_TIMEOUT_F0
+
+#define LPDDR4__DENALI_CTL_300__ZQ_CALLATCH_TIMEOUT_F0_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_300__ZQ_CALLATCH_TIMEOUT_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_300__ZQ_CALLATCH_TIMEOUT_F0_WIDTH 16U
+#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F0__REG DENALI_CTL_300
+#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_300__ZQ_CALLATCH_TIMEOUT_F0
+
+#define LPDDR4__DENALI_CTL_301_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_301_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_301__ZQ_CS_TIMEOUT_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_301__ZQ_CS_TIMEOUT_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_301__ZQ_CS_TIMEOUT_F0_WIDTH 16U
+#define LPDDR4__ZQ_CS_TIMEOUT_F0__REG DENALI_CTL_301
+#define LPDDR4__ZQ_CS_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_301__ZQ_CS_TIMEOUT_F0
+
+#define LPDDR4__DENALI_CTL_301__ZQ_PROMOTE_THRESHOLD_F0_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_301__ZQ_PROMOTE_THRESHOLD_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_301__ZQ_PROMOTE_THRESHOLD_F0_WIDTH 16U
+#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_301
+#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_301__ZQ_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_302_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_302_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_302__ZQ_CALSTART_NORM_THRESHOLD_F1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_302__ZQ_CALSTART_NORM_THRESHOLD_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_302__ZQ_CALSTART_NORM_THRESHOLD_F1_WIDTH 16U
+#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F1__REG DENALI_CTL_302
+#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_302__ZQ_CALSTART_NORM_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_302__ZQ_CALSTART_HIGH_THRESHOLD_F1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_302__ZQ_CALSTART_HIGH_THRESHOLD_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_302__ZQ_CALSTART_HIGH_THRESHOLD_F1_WIDTH 16U
+#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F1__REG DENALI_CTL_302
+#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_302__ZQ_CALSTART_HIGH_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_303_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_303_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_303__ZQ_CALLATCH_HIGH_THRESHOLD_F1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_303__ZQ_CALLATCH_HIGH_THRESHOLD_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_303__ZQ_CALLATCH_HIGH_THRESHOLD_F1_WIDTH 16U
+#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F1__REG DENALI_CTL_303
+#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_303__ZQ_CALLATCH_HIGH_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_303__ZQ_CS_NORM_THRESHOLD_F1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_303__ZQ_CS_NORM_THRESHOLD_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_303__ZQ_CS_NORM_THRESHOLD_F1_WIDTH 16U
+#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F1__REG DENALI_CTL_303
+#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_303__ZQ_CS_NORM_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_304_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_304_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_304__ZQ_CS_HIGH_THRESHOLD_F1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_304__ZQ_CS_HIGH_THRESHOLD_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_304__ZQ_CS_HIGH_THRESHOLD_F1_WIDTH 16U
+#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F1__REG DENALI_CTL_304
+#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_304__ZQ_CS_HIGH_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_304__ZQ_CALSTART_TIMEOUT_F1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_304__ZQ_CALSTART_TIMEOUT_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_304__ZQ_CALSTART_TIMEOUT_F1_WIDTH 16U
+#define LPDDR4__ZQ_CALSTART_TIMEOUT_F1__REG DENALI_CTL_304
+#define LPDDR4__ZQ_CALSTART_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_304__ZQ_CALSTART_TIMEOUT_F1
+
+#define LPDDR4__DENALI_CTL_305_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_305_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_305__ZQ_CALLATCH_TIMEOUT_F1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_305__ZQ_CALLATCH_TIMEOUT_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_305__ZQ_CALLATCH_TIMEOUT_F1_WIDTH 16U
+#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F1__REG DENALI_CTL_305
+#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_305__ZQ_CALLATCH_TIMEOUT_F1
+
+#define LPDDR4__DENALI_CTL_305__ZQ_CS_TIMEOUT_F1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_305__ZQ_CS_TIMEOUT_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_305__ZQ_CS_TIMEOUT_F1_WIDTH 16U
+#define LPDDR4__ZQ_CS_TIMEOUT_F1__REG DENALI_CTL_305
+#define LPDDR4__ZQ_CS_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_305__ZQ_CS_TIMEOUT_F1
+
+#define LPDDR4__DENALI_CTL_306_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_306_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_306__ZQ_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_306__ZQ_PROMOTE_THRESHOLD_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_306__ZQ_PROMOTE_THRESHOLD_F1_WIDTH 16U
+#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_306
+#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_306__ZQ_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_306__ZQ_CALSTART_NORM_THRESHOLD_F2_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_306__ZQ_CALSTART_NORM_THRESHOLD_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_306__ZQ_CALSTART_NORM_THRESHOLD_F2_WIDTH 16U
+#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F2__REG DENALI_CTL_306
+#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_306__ZQ_CALSTART_NORM_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_307_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_307_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_307__ZQ_CALSTART_HIGH_THRESHOLD_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_307__ZQ_CALSTART_HIGH_THRESHOLD_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_307__ZQ_CALSTART_HIGH_THRESHOLD_F2_WIDTH 16U
+#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F2__REG DENALI_CTL_307
+#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_307__ZQ_CALSTART_HIGH_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_307__ZQ_CALLATCH_HIGH_THRESHOLD_F2_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_307__ZQ_CALLATCH_HIGH_THRESHOLD_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_307__ZQ_CALLATCH_HIGH_THRESHOLD_F2_WIDTH 16U
+#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F2__REG DENALI_CTL_307
+#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_307__ZQ_CALLATCH_HIGH_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_308_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_308_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_308__ZQ_CS_NORM_THRESHOLD_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_308__ZQ_CS_NORM_THRESHOLD_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_308__ZQ_CS_NORM_THRESHOLD_F2_WIDTH 16U
+#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F2__REG DENALI_CTL_308
+#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_308__ZQ_CS_NORM_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_308__ZQ_CS_HIGH_THRESHOLD_F2_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_308__ZQ_CS_HIGH_THRESHOLD_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_308__ZQ_CS_HIGH_THRESHOLD_F2_WIDTH 16U
+#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F2__REG DENALI_CTL_308
+#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_308__ZQ_CS_HIGH_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_309_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_309_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_309__ZQ_CALSTART_TIMEOUT_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_309__ZQ_CALSTART_TIMEOUT_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_309__ZQ_CALSTART_TIMEOUT_F2_WIDTH 16U
+#define LPDDR4__ZQ_CALSTART_TIMEOUT_F2__REG DENALI_CTL_309
+#define LPDDR4__ZQ_CALSTART_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_309__ZQ_CALSTART_TIMEOUT_F2
+
+#define LPDDR4__DENALI_CTL_309__ZQ_CALLATCH_TIMEOUT_F2_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_309__ZQ_CALLATCH_TIMEOUT_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_309__ZQ_CALLATCH_TIMEOUT_F2_WIDTH 16U
+#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F2__REG DENALI_CTL_309
+#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_309__ZQ_CALLATCH_TIMEOUT_F2
+
+#define LPDDR4__DENALI_CTL_310_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_310_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_310__ZQ_CS_TIMEOUT_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_310__ZQ_CS_TIMEOUT_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_310__ZQ_CS_TIMEOUT_F2_WIDTH 16U
+#define LPDDR4__ZQ_CS_TIMEOUT_F2__REG DENALI_CTL_310
+#define LPDDR4__ZQ_CS_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_310__ZQ_CS_TIMEOUT_F2
+
+#define LPDDR4__DENALI_CTL_310__ZQ_PROMOTE_THRESHOLD_F2_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_310__ZQ_PROMOTE_THRESHOLD_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_310__ZQ_PROMOTE_THRESHOLD_F2_WIDTH 16U
+#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_310
+#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_310__ZQ_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_311_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_311_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_311__TIMEOUT_TIMER_LOG_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_311__TIMEOUT_TIMER_LOG_SHIFT 0U
+#define LPDDR4__DENALI_CTL_311__TIMEOUT_TIMER_LOG_WIDTH 8U
+#define LPDDR4__TIMEOUT_TIMER_LOG__REG DENALI_CTL_311
+#define LPDDR4__TIMEOUT_TIMER_LOG__FLD LPDDR4__DENALI_CTL_311__TIMEOUT_TIMER_LOG
+
+#define LPDDR4__DENALI_CTL_311__ZQINIT_F0_MASK 0x000FFF00U
+#define LPDDR4__DENALI_CTL_311__ZQINIT_F0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_311__ZQINIT_F0_WIDTH 12U
+#define LPDDR4__ZQINIT_F0__REG DENALI_CTL_311
+#define LPDDR4__ZQINIT_F0__FLD LPDDR4__DENALI_CTL_311__ZQINIT_F0
+
+#define LPDDR4__DENALI_CTL_312_READ_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_312_WRITE_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_312__ZQCL_F0_MASK 0x00000FFFU
+#define LPDDR4__DENALI_CTL_312__ZQCL_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_312__ZQCL_F0_WIDTH 12U
+#define LPDDR4__ZQCL_F0__REG DENALI_CTL_312
+#define LPDDR4__ZQCL_F0__FLD LPDDR4__DENALI_CTL_312__ZQCL_F0
+
+#define LPDDR4__DENALI_CTL_312__ZQCS_F0_MASK 0x0FFF0000U
+#define LPDDR4__DENALI_CTL_312__ZQCS_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_312__ZQCS_F0_WIDTH 12U
+#define LPDDR4__ZQCS_F0__REG DENALI_CTL_312
+#define LPDDR4__ZQCS_F0__FLD LPDDR4__DENALI_CTL_312__ZQCS_F0
+
+#define LPDDR4__DENALI_CTL_313_READ_MASK 0x007F0FFFU
+#define LPDDR4__DENALI_CTL_313_WRITE_MASK 0x007F0FFFU
+#define LPDDR4__DENALI_CTL_313__TZQCAL_F0_MASK 0x00000FFFU
+#define LPDDR4__DENALI_CTL_313__TZQCAL_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_313__TZQCAL_F0_WIDTH 12U
+#define LPDDR4__TZQCAL_F0__REG DENALI_CTL_313
+#define LPDDR4__TZQCAL_F0__FLD LPDDR4__DENALI_CTL_313__TZQCAL_F0
+
+#define LPDDR4__DENALI_CTL_313__TZQLAT_F0_MASK 0x007F0000U
+#define LPDDR4__DENALI_CTL_313__TZQLAT_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_313__TZQLAT_F0_WIDTH 7U
+#define LPDDR4__TZQLAT_F0__REG DENALI_CTL_313
+#define LPDDR4__TZQLAT_F0__FLD LPDDR4__DENALI_CTL_313__TZQLAT_F0
+
+#define LPDDR4__DENALI_CTL_314_READ_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_314_WRITE_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_314__ZQINIT_F1_MASK 0x00000FFFU
+#define LPDDR4__DENALI_CTL_314__ZQINIT_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_314__ZQINIT_F1_WIDTH 12U
+#define LPDDR4__ZQINIT_F1__REG DENALI_CTL_314
+#define LPDDR4__ZQINIT_F1__FLD LPDDR4__DENALI_CTL_314__ZQINIT_F1
+
+#define LPDDR4__DENALI_CTL_314__ZQCL_F1_MASK 0x0FFF0000U
+#define LPDDR4__DENALI_CTL_314__ZQCL_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_314__ZQCL_F1_WIDTH 12U
+#define LPDDR4__ZQCL_F1__REG DENALI_CTL_314
+#define LPDDR4__ZQCL_F1__FLD LPDDR4__DENALI_CTL_314__ZQCL_F1
+
+#define LPDDR4__DENALI_CTL_315_READ_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_315_WRITE_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_315__ZQCS_F1_MASK 0x00000FFFU
+#define LPDDR4__DENALI_CTL_315__ZQCS_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_315__ZQCS_F1_WIDTH 12U
+#define LPDDR4__ZQCS_F1__REG DENALI_CTL_315
+#define LPDDR4__ZQCS_F1__FLD LPDDR4__DENALI_CTL_315__ZQCS_F1
+
+#define LPDDR4__DENALI_CTL_315__TZQCAL_F1_MASK 0x0FFF0000U
+#define LPDDR4__DENALI_CTL_315__TZQCAL_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_315__TZQCAL_F1_WIDTH 12U
+#define LPDDR4__TZQCAL_F1__REG DENALI_CTL_315
+#define LPDDR4__TZQCAL_F1__FLD LPDDR4__DENALI_CTL_315__TZQCAL_F1
+
+#define LPDDR4__DENALI_CTL_316_READ_MASK 0x000FFF7FU
+#define LPDDR4__DENALI_CTL_316_WRITE_MASK 0x000FFF7FU
+#define LPDDR4__DENALI_CTL_316__TZQLAT_F1_MASK 0x0000007FU
+#define LPDDR4__DENALI_CTL_316__TZQLAT_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_316__TZQLAT_F1_WIDTH 7U
+#define LPDDR4__TZQLAT_F1__REG DENALI_CTL_316
+#define LPDDR4__TZQLAT_F1__FLD LPDDR4__DENALI_CTL_316__TZQLAT_F1
+
+#define LPDDR4__DENALI_CTL_316__ZQINIT_F2_MASK 0x000FFF00U
+#define LPDDR4__DENALI_CTL_316__ZQINIT_F2_SHIFT 8U
+#define LPDDR4__DENALI_CTL_316__ZQINIT_F2_WIDTH 12U
+#define LPDDR4__ZQINIT_F2__REG DENALI_CTL_316
+#define LPDDR4__ZQINIT_F2__FLD LPDDR4__DENALI_CTL_316__ZQINIT_F2
+
+#define LPDDR4__DENALI_CTL_317_READ_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_317_WRITE_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_317__ZQCL_F2_MASK 0x00000FFFU
+#define LPDDR4__DENALI_CTL_317__ZQCL_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_317__ZQCL_F2_WIDTH 12U
+#define LPDDR4__ZQCL_F2__REG DENALI_CTL_317
+#define LPDDR4__ZQCL_F2__FLD LPDDR4__DENALI_CTL_317__ZQCL_F2
+
+#define LPDDR4__DENALI_CTL_317__ZQCS_F2_MASK 0x0FFF0000U
+#define LPDDR4__DENALI_CTL_317__ZQCS_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_317__ZQCS_F2_WIDTH 12U
+#define LPDDR4__ZQCS_F2__REG DENALI_CTL_317
+#define LPDDR4__ZQCS_F2__FLD LPDDR4__DENALI_CTL_317__ZQCS_F2
+
+#define LPDDR4__DENALI_CTL_318_READ_MASK 0x037F0FFFU
+#define LPDDR4__DENALI_CTL_318_WRITE_MASK 0x037F0FFFU
+#define LPDDR4__DENALI_CTL_318__TZQCAL_F2_MASK 0x00000FFFU
+#define LPDDR4__DENALI_CTL_318__TZQCAL_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_318__TZQCAL_F2_WIDTH 12U
+#define LPDDR4__TZQCAL_F2__REG DENALI_CTL_318
+#define LPDDR4__TZQCAL_F2__FLD LPDDR4__DENALI_CTL_318__TZQCAL_F2
+
+#define LPDDR4__DENALI_CTL_318__TZQLAT_F2_MASK 0x007F0000U
+#define LPDDR4__DENALI_CTL_318__TZQLAT_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_318__TZQLAT_F2_WIDTH 7U
+#define LPDDR4__TZQLAT_F2__REG DENALI_CTL_318
+#define LPDDR4__TZQLAT_F2__FLD LPDDR4__DENALI_CTL_318__TZQLAT_F2
+
+#define LPDDR4__DENALI_CTL_318__ZQ_SW_REQ_START_LATCH_MAP_MASK 0x03000000U
+#define LPDDR4__DENALI_CTL_318__ZQ_SW_REQ_START_LATCH_MAP_SHIFT 24U
+#define LPDDR4__DENALI_CTL_318__ZQ_SW_REQ_START_LATCH_MAP_WIDTH 2U
+#define LPDDR4__ZQ_SW_REQ_START_LATCH_MAP__REG DENALI_CTL_318
+#define LPDDR4__ZQ_SW_REQ_START_LATCH_MAP__FLD LPDDR4__DENALI_CTL_318__ZQ_SW_REQ_START_LATCH_MAP
+
+#define LPDDR4__DENALI_CTL_319_READ_MASK 0x0FFF0100U
+#define LPDDR4__DENALI_CTL_319_WRITE_MASK 0x0FFF0100U
+#define LPDDR4__DENALI_CTL_319__ZQ_REQ_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_319__ZQ_REQ_SHIFT 0U
+#define LPDDR4__DENALI_CTL_319__ZQ_REQ_WIDTH 4U
+#define LPDDR4__ZQ_REQ__REG DENALI_CTL_319
+#define LPDDR4__ZQ_REQ__FLD LPDDR4__DENALI_CTL_319__ZQ_REQ
+
+#define LPDDR4__DENALI_CTL_319__ZQ_REQ_PENDING_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_319__ZQ_REQ_PENDING_SHIFT 8U
+#define LPDDR4__DENALI_CTL_319__ZQ_REQ_PENDING_WIDTH 1U
+#define LPDDR4__DENALI_CTL_319__ZQ_REQ_PENDING_WOCLR 0U
+#define LPDDR4__DENALI_CTL_319__ZQ_REQ_PENDING_WOSET 0U
+#define LPDDR4__ZQ_REQ_PENDING__REG DENALI_CTL_319
+#define LPDDR4__ZQ_REQ_PENDING__FLD LPDDR4__DENALI_CTL_319__ZQ_REQ_PENDING
+
+#define LPDDR4__DENALI_CTL_319__ZQRESET_F0_MASK 0x0FFF0000U
+#define LPDDR4__DENALI_CTL_319__ZQRESET_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_319__ZQRESET_F0_WIDTH 12U
+#define LPDDR4__ZQRESET_F0__REG DENALI_CTL_319
+#define LPDDR4__ZQRESET_F0__FLD LPDDR4__DENALI_CTL_319__ZQRESET_F0
+
+#define LPDDR4__DENALI_CTL_320_READ_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_320_WRITE_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_320__ZQRESET_F1_MASK 0x00000FFFU
+#define LPDDR4__DENALI_CTL_320__ZQRESET_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_320__ZQRESET_F1_WIDTH 12U
+#define LPDDR4__ZQRESET_F1__REG DENALI_CTL_320
+#define LPDDR4__ZQRESET_F1__FLD LPDDR4__DENALI_CTL_320__ZQRESET_F1
+
+#define LPDDR4__DENALI_CTL_320__ZQRESET_F2_MASK 0x0FFF0000U
+#define LPDDR4__DENALI_CTL_320__ZQRESET_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_320__ZQRESET_F2_WIDTH 12U
+#define LPDDR4__ZQRESET_F2__REG DENALI_CTL_320
+#define LPDDR4__ZQRESET_F2__FLD LPDDR4__DENALI_CTL_320__ZQRESET_F2
+
+#define LPDDR4__DENALI_CTL_321_READ_MASK 0x03030101U
+#define LPDDR4__DENALI_CTL_321_WRITE_MASK 0x03030101U
+#define LPDDR4__DENALI_CTL_321__NO_ZQ_INIT_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_321__NO_ZQ_INIT_SHIFT 0U
+#define LPDDR4__DENALI_CTL_321__NO_ZQ_INIT_WIDTH 1U
+#define LPDDR4__DENALI_CTL_321__NO_ZQ_INIT_WOCLR 0U
+#define LPDDR4__DENALI_CTL_321__NO_ZQ_INIT_WOSET 0U
+#define LPDDR4__NO_ZQ_INIT__REG DENALI_CTL_321
+#define LPDDR4__NO_ZQ_INIT__FLD LPDDR4__DENALI_CTL_321__NO_ZQ_INIT
+
+#define LPDDR4__DENALI_CTL_321__ZQCS_ROTATE_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_321__ZQCS_ROTATE_SHIFT 8U
+#define LPDDR4__DENALI_CTL_321__ZQCS_ROTATE_WIDTH 1U
+#define LPDDR4__DENALI_CTL_321__ZQCS_ROTATE_WOCLR 0U
+#define LPDDR4__DENALI_CTL_321__ZQCS_ROTATE_WOSET 0U
+#define LPDDR4__ZQCS_ROTATE__REG DENALI_CTL_321
+#define LPDDR4__ZQCS_ROTATE__FLD LPDDR4__DENALI_CTL_321__ZQCS_ROTATE
+
+#define LPDDR4__DENALI_CTL_321__ZQ_CAL_START_MAP_0_MASK 0x00030000U
+#define LPDDR4__DENALI_CTL_321__ZQ_CAL_START_MAP_0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_321__ZQ_CAL_START_MAP_0_WIDTH 2U
+#define LPDDR4__ZQ_CAL_START_MAP_0__REG DENALI_CTL_321
+#define LPDDR4__ZQ_CAL_START_MAP_0__FLD LPDDR4__DENALI_CTL_321__ZQ_CAL_START_MAP_0
+
+#define LPDDR4__DENALI_CTL_321__ZQ_CAL_LATCH_MAP_0_MASK 0x03000000U
+#define LPDDR4__DENALI_CTL_321__ZQ_CAL_LATCH_MAP_0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_321__ZQ_CAL_LATCH_MAP_0_WIDTH 2U
+#define LPDDR4__ZQ_CAL_LATCH_MAP_0__REG DENALI_CTL_321
+#define LPDDR4__ZQ_CAL_LATCH_MAP_0__FLD LPDDR4__DENALI_CTL_321__ZQ_CAL_LATCH_MAP_0
+
+#define LPDDR4__DENALI_CTL_322_READ_MASK 0x03030303U
+#define LPDDR4__DENALI_CTL_322_WRITE_MASK 0x03030303U
+#define LPDDR4__DENALI_CTL_322__ZQ_CAL_START_MAP_1_MASK 0x00000003U
+#define LPDDR4__DENALI_CTL_322__ZQ_CAL_START_MAP_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_322__ZQ_CAL_START_MAP_1_WIDTH 2U
+#define LPDDR4__ZQ_CAL_START_MAP_1__REG DENALI_CTL_322
+#define LPDDR4__ZQ_CAL_START_MAP_1__FLD LPDDR4__DENALI_CTL_322__ZQ_CAL_START_MAP_1
+
+#define LPDDR4__DENALI_CTL_322__ZQ_CAL_LATCH_MAP_1_MASK 0x00000300U
+#define LPDDR4__DENALI_CTL_322__ZQ_CAL_LATCH_MAP_1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_322__ZQ_CAL_LATCH_MAP_1_WIDTH 2U
+#define LPDDR4__ZQ_CAL_LATCH_MAP_1__REG DENALI_CTL_322
+#define LPDDR4__ZQ_CAL_LATCH_MAP_1__FLD LPDDR4__DENALI_CTL_322__ZQ_CAL_LATCH_MAP_1
+
+#define LPDDR4__DENALI_CTL_322__BANK_DIFF_0_MASK 0x00030000U
+#define LPDDR4__DENALI_CTL_322__BANK_DIFF_0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_322__BANK_DIFF_0_WIDTH 2U
+#define LPDDR4__BANK_DIFF_0__REG DENALI_CTL_322
+#define LPDDR4__BANK_DIFF_0__FLD LPDDR4__DENALI_CTL_322__BANK_DIFF_0
+
+#define LPDDR4__DENALI_CTL_322__BANK_DIFF_1_MASK 0x03000000U
+#define LPDDR4__DENALI_CTL_322__BANK_DIFF_1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_322__BANK_DIFF_1_WIDTH 2U
+#define LPDDR4__BANK_DIFF_1__REG DENALI_CTL_322
+#define LPDDR4__BANK_DIFF_1__FLD LPDDR4__DENALI_CTL_322__BANK_DIFF_1
+
+#define LPDDR4__DENALI_CTL_323_READ_MASK 0x0F0F0707U
+#define LPDDR4__DENALI_CTL_323_WRITE_MASK 0x0F0F0707U
+#define LPDDR4__DENALI_CTL_323__ROW_DIFF_0_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_323__ROW_DIFF_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_323__ROW_DIFF_0_WIDTH 3U
+#define LPDDR4__ROW_DIFF_0__REG DENALI_CTL_323
+#define LPDDR4__ROW_DIFF_0__FLD LPDDR4__DENALI_CTL_323__ROW_DIFF_0
+
+#define LPDDR4__DENALI_CTL_323__ROW_DIFF_1_MASK 0x00000700U
+#define LPDDR4__DENALI_CTL_323__ROW_DIFF_1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_323__ROW_DIFF_1_WIDTH 3U
+#define LPDDR4__ROW_DIFF_1__REG DENALI_CTL_323
+#define LPDDR4__ROW_DIFF_1__FLD LPDDR4__DENALI_CTL_323__ROW_DIFF_1
+
+#define LPDDR4__DENALI_CTL_323__COL_DIFF_0_MASK 0x000F0000U
+#define LPDDR4__DENALI_CTL_323__COL_DIFF_0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_323__COL_DIFF_0_WIDTH 4U
+#define LPDDR4__COL_DIFF_0__REG DENALI_CTL_323
+#define LPDDR4__COL_DIFF_0__FLD LPDDR4__DENALI_CTL_323__COL_DIFF_0
+
+#define LPDDR4__DENALI_CTL_323__COL_DIFF_1_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_323__COL_DIFF_1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_323__COL_DIFF_1_WIDTH 4U
+#define LPDDR4__COL_DIFF_1__REG DENALI_CTL_323
+#define LPDDR4__COL_DIFF_1__FLD LPDDR4__DENALI_CTL_323__COL_DIFF_1
+
+#define LPDDR4__DENALI_CTL_324_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_324_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_324__CS_VAL_LOWER_0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_324__CS_VAL_LOWER_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_324__CS_VAL_LOWER_0_WIDTH 16U
+#define LPDDR4__CS_VAL_LOWER_0__REG DENALI_CTL_324
+#define LPDDR4__CS_VAL_LOWER_0__FLD LPDDR4__DENALI_CTL_324__CS_VAL_LOWER_0
+
+#define LPDDR4__DENALI_CTL_324__CS_VAL_UPPER_0_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_324__CS_VAL_UPPER_0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_324__CS_VAL_UPPER_0_WIDTH 16U
+#define LPDDR4__CS_VAL_UPPER_0__REG DENALI_CTL_324
+#define LPDDR4__CS_VAL_UPPER_0__FLD LPDDR4__DENALI_CTL_324__CS_VAL_UPPER_0
+
+#define LPDDR4__DENALI_CTL_325_READ_MASK 0x00FFFF03U
+#define LPDDR4__DENALI_CTL_325_WRITE_MASK 0x00FFFF03U
+#define LPDDR4__DENALI_CTL_325__ROW_START_VAL_0_MASK 0x00000003U
+#define LPDDR4__DENALI_CTL_325__ROW_START_VAL_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_325__ROW_START_VAL_0_WIDTH 2U
+#define LPDDR4__ROW_START_VAL_0__REG DENALI_CTL_325
+#define LPDDR4__ROW_START_VAL_0__FLD LPDDR4__DENALI_CTL_325__ROW_START_VAL_0
+
+#define LPDDR4__DENALI_CTL_325__CS_MSK_0_MASK 0x00FFFF00U
+#define LPDDR4__DENALI_CTL_325__CS_MSK_0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_325__CS_MSK_0_WIDTH 16U
+#define LPDDR4__CS_MSK_0__REG DENALI_CTL_325
+#define LPDDR4__CS_MSK_0__FLD LPDDR4__DENALI_CTL_325__CS_MSK_0
+
+#define LPDDR4__DENALI_CTL_326_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_326_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_326__CS_VAL_LOWER_1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_326__CS_VAL_LOWER_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_326__CS_VAL_LOWER_1_WIDTH 16U
+#define LPDDR4__CS_VAL_LOWER_1__REG DENALI_CTL_326
+#define LPDDR4__CS_VAL_LOWER_1__FLD LPDDR4__DENALI_CTL_326__CS_VAL_LOWER_1
+
+#define LPDDR4__DENALI_CTL_326__CS_VAL_UPPER_1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_326__CS_VAL_UPPER_1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_326__CS_VAL_UPPER_1_WIDTH 16U
+#define LPDDR4__CS_VAL_UPPER_1__REG DENALI_CTL_326
+#define LPDDR4__CS_VAL_UPPER_1__FLD LPDDR4__DENALI_CTL_326__CS_VAL_UPPER_1
+
+#define LPDDR4__DENALI_CTL_327_READ_MASK 0x03FFFF03U
+#define LPDDR4__DENALI_CTL_327_WRITE_MASK 0x03FFFF03U
+#define LPDDR4__DENALI_CTL_327__ROW_START_VAL_1_MASK 0x00000003U
+#define LPDDR4__DENALI_CTL_327__ROW_START_VAL_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_327__ROW_START_VAL_1_WIDTH 2U
+#define LPDDR4__ROW_START_VAL_1__REG DENALI_CTL_327
+#define LPDDR4__ROW_START_VAL_1__FLD LPDDR4__DENALI_CTL_327__ROW_START_VAL_1
+
+#define LPDDR4__DENALI_CTL_327__CS_MSK_1_MASK 0x00FFFF00U
+#define LPDDR4__DENALI_CTL_327__CS_MSK_1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_327__CS_MSK_1_WIDTH 16U
+#define LPDDR4__CS_MSK_1__REG DENALI_CTL_327
+#define LPDDR4__CS_MSK_1__FLD LPDDR4__DENALI_CTL_327__CS_MSK_1
+
+#define LPDDR4__DENALI_CTL_327__CS_MAP_NON_POW2_MASK 0x03000000U
+#define LPDDR4__DENALI_CTL_327__CS_MAP_NON_POW2_SHIFT 24U
+#define LPDDR4__DENALI_CTL_327__CS_MAP_NON_POW2_WIDTH 2U
+#define LPDDR4__CS_MAP_NON_POW2__REG DENALI_CTL_327
+#define LPDDR4__CS_MAP_NON_POW2__FLD LPDDR4__DENALI_CTL_327__CS_MAP_NON_POW2
+
+#define LPDDR4__DENALI_CTL_328_READ_MASK 0x1F011F01U
+#define LPDDR4__DENALI_CTL_328_WRITE_MASK 0x1F011F01U
+#define LPDDR4__DENALI_CTL_328__CS_LOWER_ADDR_EN_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_328__CS_LOWER_ADDR_EN_SHIFT 0U
+#define LPDDR4__DENALI_CTL_328__CS_LOWER_ADDR_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_328__CS_LOWER_ADDR_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_328__CS_LOWER_ADDR_EN_WOSET 0U
+#define LPDDR4__CS_LOWER_ADDR_EN__REG DENALI_CTL_328
+#define LPDDR4__CS_LOWER_ADDR_EN__FLD LPDDR4__DENALI_CTL_328__CS_LOWER_ADDR_EN
+
+#define LPDDR4__DENALI_CTL_328__MC_RESERVED8_MASK 0x00001F00U
+#define LPDDR4__DENALI_CTL_328__MC_RESERVED8_SHIFT 8U
+#define LPDDR4__DENALI_CTL_328__MC_RESERVED8_WIDTH 5U
+#define LPDDR4__MC_RESERVED8__REG DENALI_CTL_328
+#define LPDDR4__MC_RESERVED8__FLD LPDDR4__DENALI_CTL_328__MC_RESERVED8
+
+#define LPDDR4__DENALI_CTL_328__MC_RESERVED9_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_328__MC_RESERVED9_SHIFT 16U
+#define LPDDR4__DENALI_CTL_328__MC_RESERVED9_WIDTH 1U
+#define LPDDR4__DENALI_CTL_328__MC_RESERVED9_WOCLR 0U
+#define LPDDR4__DENALI_CTL_328__MC_RESERVED9_WOSET 0U
+#define LPDDR4__MC_RESERVED9__REG DENALI_CTL_328
+#define LPDDR4__MC_RESERVED9__FLD LPDDR4__DENALI_CTL_328__MC_RESERVED9
+
+#define LPDDR4__DENALI_CTL_328__APREBIT_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_328__APREBIT_SHIFT 24U
+#define LPDDR4__DENALI_CTL_328__APREBIT_WIDTH 5U
+#define LPDDR4__APREBIT__REG DENALI_CTL_328
+#define LPDDR4__APREBIT__FLD LPDDR4__DENALI_CTL_328__APREBIT
+
+#define LPDDR4__DENALI_CTL_329_READ_MASK 0x0101FFFFU
+#define LPDDR4__DENALI_CTL_329_WRITE_MASK 0x0101FFFFU
+#define LPDDR4__DENALI_CTL_329__AGE_COUNT_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_329__AGE_COUNT_SHIFT 0U
+#define LPDDR4__DENALI_CTL_329__AGE_COUNT_WIDTH 8U
+#define LPDDR4__AGE_COUNT__REG DENALI_CTL_329
+#define LPDDR4__AGE_COUNT__FLD LPDDR4__DENALI_CTL_329__AGE_COUNT
+
+#define LPDDR4__DENALI_CTL_329__COMMAND_AGE_COUNT_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_329__COMMAND_AGE_COUNT_SHIFT 8U
+#define LPDDR4__DENALI_CTL_329__COMMAND_AGE_COUNT_WIDTH 8U
+#define LPDDR4__COMMAND_AGE_COUNT__REG DENALI_CTL_329
+#define LPDDR4__COMMAND_AGE_COUNT__FLD LPDDR4__DENALI_CTL_329__COMMAND_AGE_COUNT
+
+#define LPDDR4__DENALI_CTL_329__ADDR_CMP_EN_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_329__ADDR_CMP_EN_SHIFT 16U
+#define LPDDR4__DENALI_CTL_329__ADDR_CMP_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_329__ADDR_CMP_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_329__ADDR_CMP_EN_WOSET 0U
+#define LPDDR4__ADDR_CMP_EN__REG DENALI_CTL_329
+#define LPDDR4__ADDR_CMP_EN__FLD LPDDR4__DENALI_CTL_329__ADDR_CMP_EN
+
+#define LPDDR4__DENALI_CTL_329__ADDR_COLLISION_MPM_DIS_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_329__ADDR_COLLISION_MPM_DIS_SHIFT 24U
+#define LPDDR4__DENALI_CTL_329__ADDR_COLLISION_MPM_DIS_WIDTH 1U
+#define LPDDR4__DENALI_CTL_329__ADDR_COLLISION_MPM_DIS_WOCLR 0U
+#define LPDDR4__DENALI_CTL_329__ADDR_COLLISION_MPM_DIS_WOSET 0U
+#define LPDDR4__ADDR_COLLISION_MPM_DIS__REG DENALI_CTL_329
+#define LPDDR4__ADDR_COLLISION_MPM_DIS__FLD LPDDR4__DENALI_CTL_329__ADDR_COLLISION_MPM_DIS
+
+#define LPDDR4__DENALI_CTL_330_READ_MASK 0x01010101U
+#define LPDDR4__DENALI_CTL_330_WRITE_MASK 0x01010101U
+#define LPDDR4__DENALI_CTL_330__BANK_SPLIT_EN_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_330__BANK_SPLIT_EN_SHIFT 0U
+#define LPDDR4__DENALI_CTL_330__BANK_SPLIT_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_330__BANK_SPLIT_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_330__BANK_SPLIT_EN_WOSET 0U
+#define LPDDR4__BANK_SPLIT_EN__REG DENALI_CTL_330
+#define LPDDR4__BANK_SPLIT_EN__FLD LPDDR4__DENALI_CTL_330__BANK_SPLIT_EN
+
+#define LPDDR4__DENALI_CTL_330__PLACEMENT_EN_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_330__PLACEMENT_EN_SHIFT 8U
+#define LPDDR4__DENALI_CTL_330__PLACEMENT_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_330__PLACEMENT_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_330__PLACEMENT_EN_WOSET 0U
+#define LPDDR4__PLACEMENT_EN__REG DENALI_CTL_330
+#define LPDDR4__PLACEMENT_EN__FLD LPDDR4__DENALI_CTL_330__PLACEMENT_EN
+
+#define LPDDR4__DENALI_CTL_330__PRIORITY_EN_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_330__PRIORITY_EN_SHIFT 16U
+#define LPDDR4__DENALI_CTL_330__PRIORITY_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_330__PRIORITY_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_330__PRIORITY_EN_WOSET 0U
+#define LPDDR4__PRIORITY_EN__REG DENALI_CTL_330
+#define LPDDR4__PRIORITY_EN__FLD LPDDR4__DENALI_CTL_330__PRIORITY_EN
+
+#define LPDDR4__DENALI_CTL_330__RW_SAME_EN_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_330__RW_SAME_EN_SHIFT 24U
+#define LPDDR4__DENALI_CTL_330__RW_SAME_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_330__RW_SAME_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_330__RW_SAME_EN_WOSET 0U
+#define LPDDR4__RW_SAME_EN__REG DENALI_CTL_330
+#define LPDDR4__RW_SAME_EN__FLD LPDDR4__DENALI_CTL_330__RW_SAME_EN
+
+#define LPDDR4__DENALI_CTL_331_READ_MASK 0x03010101U
+#define LPDDR4__DENALI_CTL_331_WRITE_MASK 0x03010101U
+#define LPDDR4__DENALI_CTL_331__RW_SAME_PAGE_EN_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_331__RW_SAME_PAGE_EN_SHIFT 0U
+#define LPDDR4__DENALI_CTL_331__RW_SAME_PAGE_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_331__RW_SAME_PAGE_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_331__RW_SAME_PAGE_EN_WOSET 0U
+#define LPDDR4__RW_SAME_PAGE_EN__REG DENALI_CTL_331
+#define LPDDR4__RW_SAME_PAGE_EN__FLD LPDDR4__DENALI_CTL_331__RW_SAME_PAGE_EN
+
+#define LPDDR4__DENALI_CTL_331__CS_SAME_EN_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_331__CS_SAME_EN_SHIFT 8U
+#define LPDDR4__DENALI_CTL_331__CS_SAME_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_331__CS_SAME_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_331__CS_SAME_EN_WOSET 0U
+#define LPDDR4__CS_SAME_EN__REG DENALI_CTL_331
+#define LPDDR4__CS_SAME_EN__FLD LPDDR4__DENALI_CTL_331__CS_SAME_EN
+
+#define LPDDR4__DENALI_CTL_331__W2R_SPLIT_EN_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_331__W2R_SPLIT_EN_SHIFT 16U
+#define LPDDR4__DENALI_CTL_331__W2R_SPLIT_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_331__W2R_SPLIT_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_331__W2R_SPLIT_EN_WOSET 0U
+#define LPDDR4__W2R_SPLIT_EN__REG DENALI_CTL_331
+#define LPDDR4__W2R_SPLIT_EN__FLD LPDDR4__DENALI_CTL_331__W2R_SPLIT_EN
+
+#define LPDDR4__DENALI_CTL_331__DISABLE_RW_GROUP_W_BNK_CONFLICT_MASK 0x03000000U
+#define LPDDR4__DENALI_CTL_331__DISABLE_RW_GROUP_W_BNK_CONFLICT_SHIFT 24U
+#define LPDDR4__DENALI_CTL_331__DISABLE_RW_GROUP_W_BNK_CONFLICT_WIDTH 2U
+#define LPDDR4__DISABLE_RW_GROUP_W_BNK_CONFLICT__REG DENALI_CTL_331
+#define LPDDR4__DISABLE_RW_GROUP_W_BNK_CONFLICT__FLD LPDDR4__DENALI_CTL_331__DISABLE_RW_GROUP_W_BNK_CONFLICT
+
+#define LPDDR4__DENALI_CTL_332_READ_MASK 0x0301011FU
+#define LPDDR4__DENALI_CTL_332_WRITE_MASK 0x0301011FU
+#define LPDDR4__DENALI_CTL_332__NUM_Q_ENTRIES_ACT_DISABLE_MASK 0x0000001FU
+#define LPDDR4__DENALI_CTL_332__NUM_Q_ENTRIES_ACT_DISABLE_SHIFT 0U
+#define LPDDR4__DENALI_CTL_332__NUM_Q_ENTRIES_ACT_DISABLE_WIDTH 5U
+#define LPDDR4__NUM_Q_ENTRIES_ACT_DISABLE__REG DENALI_CTL_332
+#define LPDDR4__NUM_Q_ENTRIES_ACT_DISABLE__FLD LPDDR4__DENALI_CTL_332__NUM_Q_ENTRIES_ACT_DISABLE
+
+#define LPDDR4__DENALI_CTL_332__SWAP_EN_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_332__SWAP_EN_SHIFT 8U
+#define LPDDR4__DENALI_CTL_332__SWAP_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_332__SWAP_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_332__SWAP_EN_WOSET 0U
+#define LPDDR4__SWAP_EN__REG DENALI_CTL_332
+#define LPDDR4__SWAP_EN__FLD LPDDR4__DENALI_CTL_332__SWAP_EN
+
+#define LPDDR4__DENALI_CTL_332__DISABLE_RD_INTERLEAVE_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_332__DISABLE_RD_INTERLEAVE_SHIFT 16U
+#define LPDDR4__DENALI_CTL_332__DISABLE_RD_INTERLEAVE_WIDTH 1U
+#define LPDDR4__DENALI_CTL_332__DISABLE_RD_INTERLEAVE_WOCLR 0U
+#define LPDDR4__DENALI_CTL_332__DISABLE_RD_INTERLEAVE_WOSET 0U
+#define LPDDR4__DISABLE_RD_INTERLEAVE__REG DENALI_CTL_332
+#define LPDDR4__DISABLE_RD_INTERLEAVE__FLD LPDDR4__DENALI_CTL_332__DISABLE_RD_INTERLEAVE
+
+#define LPDDR4__DENALI_CTL_332__INHIBIT_DRAM_CMD_MASK 0x03000000U
+#define LPDDR4__DENALI_CTL_332__INHIBIT_DRAM_CMD_SHIFT 24U
+#define LPDDR4__DENALI_CTL_332__INHIBIT_DRAM_CMD_WIDTH 2U
+#define LPDDR4__INHIBIT_DRAM_CMD__REG DENALI_CTL_332
+#define LPDDR4__INHIBIT_DRAM_CMD__FLD LPDDR4__DENALI_CTL_332__INHIBIT_DRAM_CMD
+
+#define LPDDR4__DENALI_CTL_333_READ_MASK 0x07010F03U
+#define LPDDR4__DENALI_CTL_333_WRITE_MASK 0x07010F03U
+#define LPDDR4__DENALI_CTL_333__CS_MAP_MASK 0x00000003U
+#define LPDDR4__DENALI_CTL_333__CS_MAP_SHIFT 0U
+#define LPDDR4__DENALI_CTL_333__CS_MAP_WIDTH 2U
+#define LPDDR4__CS_MAP__REG DENALI_CTL_333
+#define LPDDR4__CS_MAP__FLD LPDDR4__DENALI_CTL_333__CS_MAP
+
+#define LPDDR4__DENALI_CTL_333__BURST_ON_FLY_BIT_MASK 0x00000F00U
+#define LPDDR4__DENALI_CTL_333__BURST_ON_FLY_BIT_SHIFT 8U
+#define LPDDR4__DENALI_CTL_333__BURST_ON_FLY_BIT_WIDTH 4U
+#define LPDDR4__BURST_ON_FLY_BIT__REG DENALI_CTL_333
+#define LPDDR4__BURST_ON_FLY_BIT__FLD LPDDR4__DENALI_CTL_333__BURST_ON_FLY_BIT
+
+#define LPDDR4__DENALI_CTL_333__MEM_DP_REDUCTION_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_333__MEM_DP_REDUCTION_SHIFT 16U
+#define LPDDR4__DENALI_CTL_333__MEM_DP_REDUCTION_WIDTH 1U
+#define LPDDR4__DENALI_CTL_333__MEM_DP_REDUCTION_WOCLR 0U
+#define LPDDR4__DENALI_CTL_333__MEM_DP_REDUCTION_WOSET 0U
+#define LPDDR4__MEM_DP_REDUCTION__REG DENALI_CTL_333
+#define LPDDR4__MEM_DP_REDUCTION__FLD LPDDR4__DENALI_CTL_333__MEM_DP_REDUCTION
+
+#define LPDDR4__DENALI_CTL_333__MEMDATA_RATIO_0_MASK 0x07000000U
+#define LPDDR4__DENALI_CTL_333__MEMDATA_RATIO_0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_333__MEMDATA_RATIO_0_WIDTH 3U
+#define LPDDR4__MEMDATA_RATIO_0__REG DENALI_CTL_333
+#define LPDDR4__MEMDATA_RATIO_0__FLD LPDDR4__DENALI_CTL_333__MEMDATA_RATIO_0
+
+#define LPDDR4__DENALI_CTL_334_READ_MASK 0x0F0F0F07U
+#define LPDDR4__DENALI_CTL_334_WRITE_MASK 0x0F0F0F07U
+#define LPDDR4__DENALI_CTL_334__MEMDATA_RATIO_1_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_334__MEMDATA_RATIO_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_334__MEMDATA_RATIO_1_WIDTH 3U
+#define LPDDR4__MEMDATA_RATIO_1__REG DENALI_CTL_334
+#define LPDDR4__MEMDATA_RATIO_1__FLD LPDDR4__DENALI_CTL_334__MEMDATA_RATIO_1
+
+#define LPDDR4__DENALI_CTL_334__DEVICE0_BYTE0_CS0_MASK 0x00000F00U
+#define LPDDR4__DENALI_CTL_334__DEVICE0_BYTE0_CS0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_334__DEVICE0_BYTE0_CS0_WIDTH 4U
+#define LPDDR4__DEVICE0_BYTE0_CS0__REG DENALI_CTL_334
+#define LPDDR4__DEVICE0_BYTE0_CS0__FLD LPDDR4__DENALI_CTL_334__DEVICE0_BYTE0_CS0
+
+#define LPDDR4__DENALI_CTL_334__DEVICE1_BYTE0_CS0_MASK 0x000F0000U
+#define LPDDR4__DENALI_CTL_334__DEVICE1_BYTE0_CS0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_334__DEVICE1_BYTE0_CS0_WIDTH 4U
+#define LPDDR4__DEVICE1_BYTE0_CS0__REG DENALI_CTL_334
+#define LPDDR4__DEVICE1_BYTE0_CS0__FLD LPDDR4__DENALI_CTL_334__DEVICE1_BYTE0_CS0
+
+#define LPDDR4__DENALI_CTL_334__DEVICE2_BYTE0_CS0_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_334__DEVICE2_BYTE0_CS0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_334__DEVICE2_BYTE0_CS0_WIDTH 4U
+#define LPDDR4__DEVICE2_BYTE0_CS0__REG DENALI_CTL_334
+#define LPDDR4__DEVICE2_BYTE0_CS0__FLD LPDDR4__DENALI_CTL_334__DEVICE2_BYTE0_CS0
+
+#define LPDDR4__DENALI_CTL_335_READ_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_335_WRITE_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_335__DEVICE3_BYTE0_CS0_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_335__DEVICE3_BYTE0_CS0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_335__DEVICE3_BYTE0_CS0_WIDTH 4U
+#define LPDDR4__DEVICE3_BYTE0_CS0__REG DENALI_CTL_335
+#define LPDDR4__DEVICE3_BYTE0_CS0__FLD LPDDR4__DENALI_CTL_335__DEVICE3_BYTE0_CS0
+
+#define LPDDR4__DENALI_CTL_335__DEVICE0_BYTE0_CS1_MASK 0x00000F00U
+#define LPDDR4__DENALI_CTL_335__DEVICE0_BYTE0_CS1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_335__DEVICE0_BYTE0_CS1_WIDTH 4U
+#define LPDDR4__DEVICE0_BYTE0_CS1__REG DENALI_CTL_335
+#define LPDDR4__DEVICE0_BYTE0_CS1__FLD LPDDR4__DENALI_CTL_335__DEVICE0_BYTE0_CS1
+
+#define LPDDR4__DENALI_CTL_335__DEVICE1_BYTE0_CS1_MASK 0x000F0000U
+#define LPDDR4__DENALI_CTL_335__DEVICE1_BYTE0_CS1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_335__DEVICE1_BYTE0_CS1_WIDTH 4U
+#define LPDDR4__DEVICE1_BYTE0_CS1__REG DENALI_CTL_335
+#define LPDDR4__DEVICE1_BYTE0_CS1__FLD LPDDR4__DENALI_CTL_335__DEVICE1_BYTE0_CS1
+
+#define LPDDR4__DENALI_CTL_335__DEVICE2_BYTE0_CS1_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_335__DEVICE2_BYTE0_CS1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_335__DEVICE2_BYTE0_CS1_WIDTH 4U
+#define LPDDR4__DEVICE2_BYTE0_CS1__REG DENALI_CTL_335
+#define LPDDR4__DEVICE2_BYTE0_CS1__FLD LPDDR4__DENALI_CTL_335__DEVICE2_BYTE0_CS1
+
+#define LPDDR4__DENALI_CTL_336_READ_MASK 0x03011F0FU
+#define LPDDR4__DENALI_CTL_336_WRITE_MASK 0x03011F0FU
+#define LPDDR4__DENALI_CTL_336__DEVICE3_BYTE0_CS1_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_336__DEVICE3_BYTE0_CS1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_336__DEVICE3_BYTE0_CS1_WIDTH 4U
+#define LPDDR4__DEVICE3_BYTE0_CS1__REG DENALI_CTL_336
+#define LPDDR4__DEVICE3_BYTE0_CS1__FLD LPDDR4__DENALI_CTL_336__DEVICE3_BYTE0_CS1
+
+#define LPDDR4__DENALI_CTL_336__Q_FULLNESS_MASK 0x00001F00U
+#define LPDDR4__DENALI_CTL_336__Q_FULLNESS_SHIFT 8U
+#define LPDDR4__DENALI_CTL_336__Q_FULLNESS_WIDTH 5U
+#define LPDDR4__Q_FULLNESS__REG DENALI_CTL_336
+#define LPDDR4__Q_FULLNESS__FLD LPDDR4__DENALI_CTL_336__Q_FULLNESS
+
+#define LPDDR4__DENALI_CTL_336__IN_ORDER_ACCEPT_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_336__IN_ORDER_ACCEPT_SHIFT 16U
+#define LPDDR4__DENALI_CTL_336__IN_ORDER_ACCEPT_WIDTH 1U
+#define LPDDR4__DENALI_CTL_336__IN_ORDER_ACCEPT_WOCLR 0U
+#define LPDDR4__DENALI_CTL_336__IN_ORDER_ACCEPT_WOSET 0U
+#define LPDDR4__IN_ORDER_ACCEPT__REG DENALI_CTL_336
+#define LPDDR4__IN_ORDER_ACCEPT__FLD LPDDR4__DENALI_CTL_336__IN_ORDER_ACCEPT
+
+#define LPDDR4__DENALI_CTL_336__WR_ORDER_REQ_MASK 0x03000000U
+#define LPDDR4__DENALI_CTL_336__WR_ORDER_REQ_SHIFT 24U
+#define LPDDR4__DENALI_CTL_336__WR_ORDER_REQ_WIDTH 2U
+#define LPDDR4__WR_ORDER_REQ__REG DENALI_CTL_336
+#define LPDDR4__WR_ORDER_REQ__FLD LPDDR4__DENALI_CTL_336__WR_ORDER_REQ
+
+#define LPDDR4__DENALI_CTL_337_READ_MASK 0x01010001U
+#define LPDDR4__DENALI_CTL_337_WRITE_MASK 0x01010001U
+#define LPDDR4__DENALI_CTL_337__CONTROLLER_BUSY_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_337__CONTROLLER_BUSY_SHIFT 0U
+#define LPDDR4__DENALI_CTL_337__CONTROLLER_BUSY_WIDTH 1U
+#define LPDDR4__DENALI_CTL_337__CONTROLLER_BUSY_WOCLR 0U
+#define LPDDR4__DENALI_CTL_337__CONTROLLER_BUSY_WOSET 0U
+#define LPDDR4__CONTROLLER_BUSY__REG DENALI_CTL_337
+#define LPDDR4__CONTROLLER_BUSY__FLD LPDDR4__DENALI_CTL_337__CONTROLLER_BUSY
+
+#define LPDDR4__DENALI_CTL_337__CTRLUPD_REQ_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_337__CTRLUPD_REQ_SHIFT 8U
+#define LPDDR4__DENALI_CTL_337__CTRLUPD_REQ_WIDTH 1U
+#define LPDDR4__DENALI_CTL_337__CTRLUPD_REQ_WOCLR 0U
+#define LPDDR4__DENALI_CTL_337__CTRLUPD_REQ_WOSET 0U
+#define LPDDR4__CTRLUPD_REQ__REG DENALI_CTL_337
+#define LPDDR4__CTRLUPD_REQ__FLD LPDDR4__DENALI_CTL_337__CTRLUPD_REQ
+
+#define LPDDR4__DENALI_CTL_337__CTRLUPD_REQ_PER_AREF_EN_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_337__CTRLUPD_REQ_PER_AREF_EN_SHIFT 16U
+#define LPDDR4__DENALI_CTL_337__CTRLUPD_REQ_PER_AREF_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_337__CTRLUPD_REQ_PER_AREF_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_337__CTRLUPD_REQ_PER_AREF_EN_WOSET 0U
+#define LPDDR4__CTRLUPD_REQ_PER_AREF_EN__REG DENALI_CTL_337
+#define LPDDR4__CTRLUPD_REQ_PER_AREF_EN__FLD LPDDR4__DENALI_CTL_337__CTRLUPD_REQ_PER_AREF_EN
+
+#define LPDDR4__DENALI_CTL_337__CTRLUPD_AREF_HP_ENABLE_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_337__CTRLUPD_AREF_HP_ENABLE_SHIFT 24U
+#define LPDDR4__DENALI_CTL_337__CTRLUPD_AREF_HP_ENABLE_WIDTH 1U
+#define LPDDR4__DENALI_CTL_337__CTRLUPD_AREF_HP_ENABLE_WOCLR 0U
+#define LPDDR4__DENALI_CTL_337__CTRLUPD_AREF_HP_ENABLE_WOSET 0U
+#define LPDDR4__CTRLUPD_AREF_HP_ENABLE__REG DENALI_CTL_337
+#define LPDDR4__CTRLUPD_AREF_HP_ENABLE__FLD LPDDR4__DENALI_CTL_337__CTRLUPD_AREF_HP_ENABLE
+
+#define LPDDR4__DENALI_CTL_338_READ_MASK 0x01030303U
+#define LPDDR4__DENALI_CTL_338_WRITE_MASK 0x01030303U
+#define LPDDR4__DENALI_CTL_338__PREAMBLE_SUPPORT_F0_MASK 0x00000003U
+#define LPDDR4__DENALI_CTL_338__PREAMBLE_SUPPORT_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_338__PREAMBLE_SUPPORT_F0_WIDTH 2U
+#define LPDDR4__PREAMBLE_SUPPORT_F0__REG DENALI_CTL_338
+#define LPDDR4__PREAMBLE_SUPPORT_F0__FLD LPDDR4__DENALI_CTL_338__PREAMBLE_SUPPORT_F0
+
+#define LPDDR4__DENALI_CTL_338__PREAMBLE_SUPPORT_F1_MASK 0x00000300U
+#define LPDDR4__DENALI_CTL_338__PREAMBLE_SUPPORT_F1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_338__PREAMBLE_SUPPORT_F1_WIDTH 2U
+#define LPDDR4__PREAMBLE_SUPPORT_F1__REG DENALI_CTL_338
+#define LPDDR4__PREAMBLE_SUPPORT_F1__FLD LPDDR4__DENALI_CTL_338__PREAMBLE_SUPPORT_F1
+
+#define LPDDR4__DENALI_CTL_338__PREAMBLE_SUPPORT_F2_MASK 0x00030000U
+#define LPDDR4__DENALI_CTL_338__PREAMBLE_SUPPORT_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_338__PREAMBLE_SUPPORT_F2_WIDTH 2U
+#define LPDDR4__PREAMBLE_SUPPORT_F2__REG DENALI_CTL_338
+#define LPDDR4__PREAMBLE_SUPPORT_F2__FLD LPDDR4__DENALI_CTL_338__PREAMBLE_SUPPORT_F2
+
+#define LPDDR4__DENALI_CTL_338__RD_PREAMBLE_TRAINING_EN_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_338__RD_PREAMBLE_TRAINING_EN_SHIFT 24U
+#define LPDDR4__DENALI_CTL_338__RD_PREAMBLE_TRAINING_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_338__RD_PREAMBLE_TRAINING_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_338__RD_PREAMBLE_TRAINING_EN_WOSET 0U
+#define LPDDR4__RD_PREAMBLE_TRAINING_EN__REG DENALI_CTL_338
+#define LPDDR4__RD_PREAMBLE_TRAINING_EN__FLD LPDDR4__DENALI_CTL_338__RD_PREAMBLE_TRAINING_EN
+
+#define LPDDR4__DENALI_CTL_339_READ_MASK 0x001F0101U
+#define LPDDR4__DENALI_CTL_339_WRITE_MASK 0x001F0101U
+#define LPDDR4__DENALI_CTL_339__WR_DBI_EN_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_339__WR_DBI_EN_SHIFT 0U
+#define LPDDR4__DENALI_CTL_339__WR_DBI_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_339__WR_DBI_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_339__WR_DBI_EN_WOSET 0U
+#define LPDDR4__WR_DBI_EN__REG DENALI_CTL_339
+#define LPDDR4__WR_DBI_EN__FLD LPDDR4__DENALI_CTL_339__WR_DBI_EN
+
+#define LPDDR4__DENALI_CTL_339__RD_DBI_EN_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_339__RD_DBI_EN_SHIFT 8U
+#define LPDDR4__DENALI_CTL_339__RD_DBI_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_339__RD_DBI_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_339__RD_DBI_EN_WOSET 0U
+#define LPDDR4__RD_DBI_EN__REG DENALI_CTL_339
+#define LPDDR4__RD_DBI_EN__FLD LPDDR4__DENALI_CTL_339__RD_DBI_EN
+
+#define LPDDR4__DENALI_CTL_339__DFI_ERROR_MASK 0x001F0000U
+#define LPDDR4__DENALI_CTL_339__DFI_ERROR_SHIFT 16U
+#define LPDDR4__DENALI_CTL_339__DFI_ERROR_WIDTH 5U
+#define LPDDR4__DFI_ERROR__REG DENALI_CTL_339
+#define LPDDR4__DFI_ERROR__FLD LPDDR4__DENALI_CTL_339__DFI_ERROR
+
+#define LPDDR4__DENALI_CTL_340_READ_MASK 0x010FFFFFU
+#define LPDDR4__DENALI_CTL_340_WRITE_MASK 0x010FFFFFU
+#define LPDDR4__DENALI_CTL_340__DFI_ERROR_INFO_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_340__DFI_ERROR_INFO_SHIFT 0U
+#define LPDDR4__DENALI_CTL_340__DFI_ERROR_INFO_WIDTH 20U
+#define LPDDR4__DFI_ERROR_INFO__REG DENALI_CTL_340
+#define LPDDR4__DFI_ERROR_INFO__FLD LPDDR4__DENALI_CTL_340__DFI_ERROR_INFO
+
+#define LPDDR4__DENALI_CTL_340__BG_ROTATE_EN_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_340__BG_ROTATE_EN_SHIFT 24U
+#define LPDDR4__DENALI_CTL_340__BG_ROTATE_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_340__BG_ROTATE_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_340__BG_ROTATE_EN_WOSET 0U
+#define LPDDR4__BG_ROTATE_EN__REG DENALI_CTL_340
+#define LPDDR4__BG_ROTATE_EN__FLD LPDDR4__DENALI_CTL_340__BG_ROTATE_EN
+
+#define LPDDR4__DENALI_CTL_341__MC_RESERVED10_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_341__MC_RESERVED10_SHIFT 0U
+#define LPDDR4__DENALI_CTL_341__MC_RESERVED10_WIDTH 1U
+#define LPDDR4__DENALI_CTL_341__MC_RESERVED10_WOCLR 0U
+#define LPDDR4__DENALI_CTL_341__MC_RESERVED10_WOSET 0U
+#define LPDDR4__MC_RESERVED10__REG DENALI_CTL_341
+#define LPDDR4__MC_RESERVED10__FLD LPDDR4__DENALI_CTL_341__MC_RESERVED10
+
+#define LPDDR4__DENALI_CTL_342_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_342_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_342__INT_STATUS_MASTER_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_342__INT_STATUS_MASTER_SHIFT 0U
+#define LPDDR4__DENALI_CTL_342__INT_STATUS_MASTER_WIDTH 32U
+#define LPDDR4__INT_STATUS_MASTER__REG DENALI_CTL_342
+#define LPDDR4__INT_STATUS_MASTER__FLD LPDDR4__DENALI_CTL_342__INT_STATUS_MASTER
+
+#define LPDDR4__DENALI_CTL_343_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_343_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_343__INT_MASK_MASTER_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_343__INT_MASK_MASTER_SHIFT 0U
+#define LPDDR4__DENALI_CTL_343__INT_MASK_MASTER_WIDTH 32U
+#define LPDDR4__INT_MASK_MASTER__REG DENALI_CTL_343
+#define LPDDR4__INT_MASK_MASTER__FLD LPDDR4__DENALI_CTL_343__INT_MASK_MASTER
+
+#define LPDDR4__DENALI_CTL_344_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_344_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_344__INT_STATUS_TIMEOUT_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_344__INT_STATUS_TIMEOUT_SHIFT 0U
+#define LPDDR4__DENALI_CTL_344__INT_STATUS_TIMEOUT_WIDTH 32U
+#define LPDDR4__INT_STATUS_TIMEOUT__REG DENALI_CTL_344
+#define LPDDR4__INT_STATUS_TIMEOUT__FLD LPDDR4__DENALI_CTL_344__INT_STATUS_TIMEOUT
+
+#define LPDDR4__DENALI_CTL_345_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_345_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_345__MC_RESERVED11_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_345__MC_RESERVED11_SHIFT 0U
+#define LPDDR4__DENALI_CTL_345__MC_RESERVED11_WIDTH 16U
+#define LPDDR4__MC_RESERVED11__REG DENALI_CTL_345
+#define LPDDR4__MC_RESERVED11__FLD LPDDR4__DENALI_CTL_345__MC_RESERVED11
+
+#define LPDDR4__DENALI_CTL_345__INT_STATUS_LOWPOWER_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_345__INT_STATUS_LOWPOWER_SHIFT 16U
+#define LPDDR4__DENALI_CTL_345__INT_STATUS_LOWPOWER_WIDTH 16U
+#define LPDDR4__INT_STATUS_LOWPOWER__REG DENALI_CTL_345
+#define LPDDR4__INT_STATUS_LOWPOWER__FLD LPDDR4__DENALI_CTL_345__INT_STATUS_LOWPOWER
+
+#define LPDDR4__DENALI_CTL_346_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_346_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_346__MC_RESERVED12_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_346__MC_RESERVED12_SHIFT 0U
+#define LPDDR4__DENALI_CTL_346__MC_RESERVED12_WIDTH 16U
+#define LPDDR4__MC_RESERVED12__REG DENALI_CTL_346
+#define LPDDR4__MC_RESERVED12__FLD LPDDR4__DENALI_CTL_346__MC_RESERVED12
+
+#define LPDDR4__DENALI_CTL_346__MC_RESERVED13_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_346__MC_RESERVED13_SHIFT 16U
+#define LPDDR4__DENALI_CTL_346__MC_RESERVED13_WIDTH 16U
+#define LPDDR4__MC_RESERVED13__REG DENALI_CTL_346
+#define LPDDR4__MC_RESERVED13__FLD LPDDR4__DENALI_CTL_346__MC_RESERVED13
+
+#define LPDDR4__DENALI_CTL_347_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_347_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_347__INT_STATUS_TRAINING_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_347__INT_STATUS_TRAINING_SHIFT 0U
+#define LPDDR4__DENALI_CTL_347__INT_STATUS_TRAINING_WIDTH 32U
+#define LPDDR4__INT_STATUS_TRAINING__REG DENALI_CTL_347
+#define LPDDR4__INT_STATUS_TRAINING__FLD LPDDR4__DENALI_CTL_347__INT_STATUS_TRAINING
+
+#define LPDDR4__DENALI_CTL_348_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_348_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_348__INT_STATUS_USERIF_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_348__INT_STATUS_USERIF_SHIFT 0U
+#define LPDDR4__DENALI_CTL_348__INT_STATUS_USERIF_WIDTH 32U
+#define LPDDR4__INT_STATUS_USERIF__REG DENALI_CTL_348
+#define LPDDR4__INT_STATUS_USERIF__FLD LPDDR4__DENALI_CTL_348__INT_STATUS_USERIF
+
+#define LPDDR4__DENALI_CTL_349_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_349_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_349__INT_STATUS_MISC_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_349__INT_STATUS_MISC_SHIFT 0U
+#define LPDDR4__DENALI_CTL_349__INT_STATUS_MISC_WIDTH 16U
+#define LPDDR4__INT_STATUS_MISC__REG DENALI_CTL_349
+#define LPDDR4__INT_STATUS_MISC__FLD LPDDR4__DENALI_CTL_349__INT_STATUS_MISC
+
+#define LPDDR4__DENALI_CTL_349__INT_STATUS_BIST_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_349__INT_STATUS_BIST_SHIFT 16U
+#define LPDDR4__DENALI_CTL_349__INT_STATUS_BIST_WIDTH 8U
+#define LPDDR4__INT_STATUS_BIST__REG DENALI_CTL_349
+#define LPDDR4__INT_STATUS_BIST__FLD LPDDR4__DENALI_CTL_349__INT_STATUS_BIST
+
+#define LPDDR4__DENALI_CTL_349__MC_RESERVED14_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_349__MC_RESERVED14_SHIFT 24U
+#define LPDDR4__DENALI_CTL_349__MC_RESERVED14_WIDTH 8U
+#define LPDDR4__MC_RESERVED14__REG DENALI_CTL_349
+#define LPDDR4__MC_RESERVED14__FLD LPDDR4__DENALI_CTL_349__MC_RESERVED14
+
+#define LPDDR4__DENALI_CTL_350_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_350_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_350__INT_STATUS_DFI_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_350__INT_STATUS_DFI_SHIFT 0U
+#define LPDDR4__DENALI_CTL_350__INT_STATUS_DFI_WIDTH 8U
+#define LPDDR4__INT_STATUS_DFI__REG DENALI_CTL_350
+#define LPDDR4__INT_STATUS_DFI__FLD LPDDR4__DENALI_CTL_350__INT_STATUS_DFI
+
+#define LPDDR4__DENALI_CTL_350__MC_RESERVED15_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_350__MC_RESERVED15_SHIFT 8U
+#define LPDDR4__DENALI_CTL_350__MC_RESERVED15_WIDTH 8U
+#define LPDDR4__MC_RESERVED15__REG DENALI_CTL_350
+#define LPDDR4__MC_RESERVED15__FLD LPDDR4__DENALI_CTL_350__MC_RESERVED15
+
+#define LPDDR4__DENALI_CTL_350__INT_STATUS_FREQ_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_350__INT_STATUS_FREQ_SHIFT 16U
+#define LPDDR4__DENALI_CTL_350__INT_STATUS_FREQ_WIDTH 8U
+#define LPDDR4__INT_STATUS_FREQ__REG DENALI_CTL_350
+#define LPDDR4__INT_STATUS_FREQ__FLD LPDDR4__DENALI_CTL_350__INT_STATUS_FREQ
+
+#define LPDDR4__DENALI_CTL_350__INT_STATUS_INIT_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_350__INT_STATUS_INIT_SHIFT 24U
+#define LPDDR4__DENALI_CTL_350__INT_STATUS_INIT_WIDTH 8U
+#define LPDDR4__INT_STATUS_INIT__REG DENALI_CTL_350
+#define LPDDR4__INT_STATUS_INIT__FLD LPDDR4__DENALI_CTL_350__INT_STATUS_INIT
+
+#define LPDDR4__DENALI_CTL_351_READ_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_351_WRITE_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_351__INT_STATUS_MODE_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_351__INT_STATUS_MODE_SHIFT 0U
+#define LPDDR4__DENALI_CTL_351__INT_STATUS_MODE_WIDTH 8U
+#define LPDDR4__INT_STATUS_MODE__REG DENALI_CTL_351
+#define LPDDR4__INT_STATUS_MODE__FLD LPDDR4__DENALI_CTL_351__INT_STATUS_MODE
+
+#define LPDDR4__DENALI_CTL_351__INT_STATUS_PARITY_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_351__INT_STATUS_PARITY_SHIFT 8U
+#define LPDDR4__DENALI_CTL_351__INT_STATUS_PARITY_WIDTH 8U
+#define LPDDR4__INT_STATUS_PARITY__REG DENALI_CTL_351
+#define LPDDR4__INT_STATUS_PARITY__FLD LPDDR4__DENALI_CTL_351__INT_STATUS_PARITY
+
+#define LPDDR4__DENALI_CTL_352__INT_ACK_TIMEOUT_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_352__INT_ACK_TIMEOUT_SHIFT 0U
+#define LPDDR4__DENALI_CTL_352__INT_ACK_TIMEOUT_WIDTH 32U
+#define LPDDR4__INT_ACK_TIMEOUT__REG DENALI_CTL_352
+#define LPDDR4__INT_ACK_TIMEOUT__FLD LPDDR4__DENALI_CTL_352__INT_ACK_TIMEOUT
+
+#define LPDDR4__DENALI_CTL_353__MC_RESERVED16_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_353__MC_RESERVED16_SHIFT 0U
+#define LPDDR4__DENALI_CTL_353__MC_RESERVED16_WIDTH 16U
+#define LPDDR4__MC_RESERVED16__REG DENALI_CTL_353
+#define LPDDR4__MC_RESERVED16__FLD LPDDR4__DENALI_CTL_353__MC_RESERVED16
+
+#define LPDDR4__DENALI_CTL_353__INT_ACK_LOWPOWER_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_353__INT_ACK_LOWPOWER_SHIFT 16U
+#define LPDDR4__DENALI_CTL_353__INT_ACK_LOWPOWER_WIDTH 16U
+#define LPDDR4__INT_ACK_LOWPOWER__REG DENALI_CTL_353
+#define LPDDR4__INT_ACK_LOWPOWER__FLD LPDDR4__DENALI_CTL_353__INT_ACK_LOWPOWER
+
+#define LPDDR4__DENALI_CTL_354__MC_RESERVED17_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_354__MC_RESERVED17_SHIFT 0U
+#define LPDDR4__DENALI_CTL_354__MC_RESERVED17_WIDTH 16U
+#define LPDDR4__MC_RESERVED17__REG DENALI_CTL_354
+#define LPDDR4__MC_RESERVED17__FLD LPDDR4__DENALI_CTL_354__MC_RESERVED17
+
+#define LPDDR4__DENALI_CTL_354__MC_RESERVED18_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_354__MC_RESERVED18_SHIFT 16U
+#define LPDDR4__DENALI_CTL_354__MC_RESERVED18_WIDTH 16U
+#define LPDDR4__MC_RESERVED18__REG DENALI_CTL_354
+#define LPDDR4__MC_RESERVED18__FLD LPDDR4__DENALI_CTL_354__MC_RESERVED18
+
+#define LPDDR4__DENALI_CTL_355__INT_ACK_TRAINING_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_355__INT_ACK_TRAINING_SHIFT 0U
+#define LPDDR4__DENALI_CTL_355__INT_ACK_TRAINING_WIDTH 32U
+#define LPDDR4__INT_ACK_TRAINING__REG DENALI_CTL_355
+#define LPDDR4__INT_ACK_TRAINING__FLD LPDDR4__DENALI_CTL_355__INT_ACK_TRAINING
+
+#define LPDDR4__DENALI_CTL_356__INT_ACK_USERIF_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_356__INT_ACK_USERIF_SHIFT 0U
+#define LPDDR4__DENALI_CTL_356__INT_ACK_USERIF_WIDTH 32U
+#define LPDDR4__INT_ACK_USERIF__REG DENALI_CTL_356
+#define LPDDR4__INT_ACK_USERIF__FLD LPDDR4__DENALI_CTL_356__INT_ACK_USERIF
+
+#define LPDDR4__DENALI_CTL_357__INT_ACK_MISC_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_357__INT_ACK_MISC_SHIFT 0U
+#define LPDDR4__DENALI_CTL_357__INT_ACK_MISC_WIDTH 16U
+#define LPDDR4__INT_ACK_MISC__REG DENALI_CTL_357
+#define LPDDR4__INT_ACK_MISC__FLD LPDDR4__DENALI_CTL_357__INT_ACK_MISC
+
+#define LPDDR4__DENALI_CTL_357__INT_ACK_BIST_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_357__INT_ACK_BIST_SHIFT 16U
+#define LPDDR4__DENALI_CTL_357__INT_ACK_BIST_WIDTH 8U
+#define LPDDR4__INT_ACK_BIST__REG DENALI_CTL_357
+#define LPDDR4__INT_ACK_BIST__FLD LPDDR4__DENALI_CTL_357__INT_ACK_BIST
+
+#define LPDDR4__DENALI_CTL_357__MC_RESERVED19_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_357__MC_RESERVED19_SHIFT 24U
+#define LPDDR4__DENALI_CTL_357__MC_RESERVED19_WIDTH 8U
+#define LPDDR4__MC_RESERVED19__REG DENALI_CTL_357
+#define LPDDR4__MC_RESERVED19__FLD LPDDR4__DENALI_CTL_357__MC_RESERVED19
+
+#define LPDDR4__DENALI_CTL_358__INT_ACK_DFI_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_358__INT_ACK_DFI_SHIFT 0U
+#define LPDDR4__DENALI_CTL_358__INT_ACK_DFI_WIDTH 8U
+#define LPDDR4__INT_ACK_DFI__REG DENALI_CTL_358
+#define LPDDR4__INT_ACK_DFI__FLD LPDDR4__DENALI_CTL_358__INT_ACK_DFI
+
+#define LPDDR4__DENALI_CTL_358__MC_RESERVED20_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_358__MC_RESERVED20_SHIFT 8U
+#define LPDDR4__DENALI_CTL_358__MC_RESERVED20_WIDTH 8U
+#define LPDDR4__MC_RESERVED20__REG DENALI_CTL_358
+#define LPDDR4__MC_RESERVED20__FLD LPDDR4__DENALI_CTL_358__MC_RESERVED20
+
+#define LPDDR4__DENALI_CTL_358__INT_ACK_FREQ_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_358__INT_ACK_FREQ_SHIFT 16U
+#define LPDDR4__DENALI_CTL_358__INT_ACK_FREQ_WIDTH 8U
+#define LPDDR4__INT_ACK_FREQ__REG DENALI_CTL_358
+#define LPDDR4__INT_ACK_FREQ__FLD LPDDR4__DENALI_CTL_358__INT_ACK_FREQ
+
+#define LPDDR4__DENALI_CTL_358__INT_ACK_INIT_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_358__INT_ACK_INIT_SHIFT 24U
+#define LPDDR4__DENALI_CTL_358__INT_ACK_INIT_WIDTH 8U
+#define LPDDR4__INT_ACK_INIT__REG DENALI_CTL_358
+#define LPDDR4__INT_ACK_INIT__FLD LPDDR4__DENALI_CTL_358__INT_ACK_INIT
+
+#define LPDDR4__DENALI_CTL_359__INT_ACK_MODE_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_359__INT_ACK_MODE_SHIFT 0U
+#define LPDDR4__DENALI_CTL_359__INT_ACK_MODE_WIDTH 8U
+#define LPDDR4__INT_ACK_MODE__REG DENALI_CTL_359
+#define LPDDR4__INT_ACK_MODE__FLD LPDDR4__DENALI_CTL_359__INT_ACK_MODE
+
+#define LPDDR4__DENALI_CTL_359__INT_ACK_PARITY_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_359__INT_ACK_PARITY_SHIFT 8U
+#define LPDDR4__DENALI_CTL_359__INT_ACK_PARITY_WIDTH 8U
+#define LPDDR4__INT_ACK_PARITY__REG DENALI_CTL_359
+#define LPDDR4__INT_ACK_PARITY__FLD LPDDR4__DENALI_CTL_359__INT_ACK_PARITY
+
+#define LPDDR4__DENALI_CTL_360_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_360_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_360__INT_MASK_TIMEOUT_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_360__INT_MASK_TIMEOUT_SHIFT 0U
+#define LPDDR4__DENALI_CTL_360__INT_MASK_TIMEOUT_WIDTH 32U
+#define LPDDR4__INT_MASK_TIMEOUT__REG DENALI_CTL_360
+#define LPDDR4__INT_MASK_TIMEOUT__FLD LPDDR4__DENALI_CTL_360__INT_MASK_TIMEOUT
+
+#define LPDDR4__DENALI_CTL_361_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_361_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_361__MC_RESERVED21_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_361__MC_RESERVED21_SHIFT 0U
+#define LPDDR4__DENALI_CTL_361__MC_RESERVED21_WIDTH 16U
+#define LPDDR4__MC_RESERVED21__REG DENALI_CTL_361
+#define LPDDR4__MC_RESERVED21__FLD LPDDR4__DENALI_CTL_361__MC_RESERVED21
+
+#define LPDDR4__DENALI_CTL_361__INT_MASK_LOWPOWER_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_361__INT_MASK_LOWPOWER_SHIFT 16U
+#define LPDDR4__DENALI_CTL_361__INT_MASK_LOWPOWER_WIDTH 16U
+#define LPDDR4__INT_MASK_LOWPOWER__REG DENALI_CTL_361
+#define LPDDR4__INT_MASK_LOWPOWER__FLD LPDDR4__DENALI_CTL_361__INT_MASK_LOWPOWER
+
+#define LPDDR4__DENALI_CTL_362_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_362_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_362__MC_RESERVED22_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_362__MC_RESERVED22_SHIFT 0U
+#define LPDDR4__DENALI_CTL_362__MC_RESERVED22_WIDTH 16U
+#define LPDDR4__MC_RESERVED22__REG DENALI_CTL_362
+#define LPDDR4__MC_RESERVED22__FLD LPDDR4__DENALI_CTL_362__MC_RESERVED22
+
+#define LPDDR4__DENALI_CTL_362__MC_RESERVED23_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_362__MC_RESERVED23_SHIFT 16U
+#define LPDDR4__DENALI_CTL_362__MC_RESERVED23_WIDTH 16U
+#define LPDDR4__MC_RESERVED23__REG DENALI_CTL_362
+#define LPDDR4__MC_RESERVED23__FLD LPDDR4__DENALI_CTL_362__MC_RESERVED23
+
+#define LPDDR4__DENALI_CTL_363_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_363_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_363__INT_MASK_TRAINING_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_363__INT_MASK_TRAINING_SHIFT 0U
+#define LPDDR4__DENALI_CTL_363__INT_MASK_TRAINING_WIDTH 32U
+#define LPDDR4__INT_MASK_TRAINING__REG DENALI_CTL_363
+#define LPDDR4__INT_MASK_TRAINING__FLD LPDDR4__DENALI_CTL_363__INT_MASK_TRAINING
+
+#define LPDDR4__DENALI_CTL_364_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_364_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_364__INT_MASK_USERIF_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_364__INT_MASK_USERIF_SHIFT 0U
+#define LPDDR4__DENALI_CTL_364__INT_MASK_USERIF_WIDTH 32U
+#define LPDDR4__INT_MASK_USERIF__REG DENALI_CTL_364
+#define LPDDR4__INT_MASK_USERIF__FLD LPDDR4__DENALI_CTL_364__INT_MASK_USERIF
+
+#define LPDDR4__DENALI_CTL_365_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_365_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_365__INT_MASK_MISC_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_365__INT_MASK_MISC_SHIFT 0U
+#define LPDDR4__DENALI_CTL_365__INT_MASK_MISC_WIDTH 16U
+#define LPDDR4__INT_MASK_MISC__REG DENALI_CTL_365
+#define LPDDR4__INT_MASK_MISC__FLD LPDDR4__DENALI_CTL_365__INT_MASK_MISC
+
+#define LPDDR4__DENALI_CTL_365__INT_MASK_BIST_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_365__INT_MASK_BIST_SHIFT 16U
+#define LPDDR4__DENALI_CTL_365__INT_MASK_BIST_WIDTH 8U
+#define LPDDR4__INT_MASK_BIST__REG DENALI_CTL_365
+#define LPDDR4__INT_MASK_BIST__FLD LPDDR4__DENALI_CTL_365__INT_MASK_BIST
+
+#define LPDDR4__DENALI_CTL_365__MC_RESERVED24_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_365__MC_RESERVED24_SHIFT 24U
+#define LPDDR4__DENALI_CTL_365__MC_RESERVED24_WIDTH 8U
+#define LPDDR4__MC_RESERVED24__REG DENALI_CTL_365
+#define LPDDR4__MC_RESERVED24__FLD LPDDR4__DENALI_CTL_365__MC_RESERVED24
+
+#define LPDDR4__DENALI_CTL_366_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_366_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_366__INT_MASK_DFI_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_366__INT_MASK_DFI_SHIFT 0U
+#define LPDDR4__DENALI_CTL_366__INT_MASK_DFI_WIDTH 8U
+#define LPDDR4__INT_MASK_DFI__REG DENALI_CTL_366
+#define LPDDR4__INT_MASK_DFI__FLD LPDDR4__DENALI_CTL_366__INT_MASK_DFI
+
+#define LPDDR4__DENALI_CTL_366__MC_RESERVED25_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_366__MC_RESERVED25_SHIFT 8U
+#define LPDDR4__DENALI_CTL_366__MC_RESERVED25_WIDTH 8U
+#define LPDDR4__MC_RESERVED25__REG DENALI_CTL_366
+#define LPDDR4__MC_RESERVED25__FLD LPDDR4__DENALI_CTL_366__MC_RESERVED25
+
+#define LPDDR4__DENALI_CTL_366__INT_MASK_FREQ_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_366__INT_MASK_FREQ_SHIFT 16U
+#define LPDDR4__DENALI_CTL_366__INT_MASK_FREQ_WIDTH 8U
+#define LPDDR4__INT_MASK_FREQ__REG DENALI_CTL_366
+#define LPDDR4__INT_MASK_FREQ__FLD LPDDR4__DENALI_CTL_366__INT_MASK_FREQ
+
+#define LPDDR4__DENALI_CTL_366__INT_MASK_INIT_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_366__INT_MASK_INIT_SHIFT 24U
+#define LPDDR4__DENALI_CTL_366__INT_MASK_INIT_WIDTH 8U
+#define LPDDR4__INT_MASK_INIT__REG DENALI_CTL_366
+#define LPDDR4__INT_MASK_INIT__FLD LPDDR4__DENALI_CTL_366__INT_MASK_INIT
+
+#define LPDDR4__DENALI_CTL_367_READ_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_367_WRITE_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_367__INT_MASK_MODE_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_367__INT_MASK_MODE_SHIFT 0U
+#define LPDDR4__DENALI_CTL_367__INT_MASK_MODE_WIDTH 8U
+#define LPDDR4__INT_MASK_MODE__REG DENALI_CTL_367
+#define LPDDR4__INT_MASK_MODE__FLD LPDDR4__DENALI_CTL_367__INT_MASK_MODE
+
+#define LPDDR4__DENALI_CTL_367__INT_MASK_PARITY_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_367__INT_MASK_PARITY_SHIFT 8U
+#define LPDDR4__DENALI_CTL_367__INT_MASK_PARITY_WIDTH 8U
+#define LPDDR4__INT_MASK_PARITY__REG DENALI_CTL_367
+#define LPDDR4__INT_MASK_PARITY__FLD LPDDR4__DENALI_CTL_367__INT_MASK_PARITY
+
+#define LPDDR4__DENALI_CTL_368_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_368_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_368__OUT_OF_RANGE_ADDR_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_368__OUT_OF_RANGE_ADDR_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_368__OUT_OF_RANGE_ADDR_0_WIDTH 32U
+#define LPDDR4__OUT_OF_RANGE_ADDR_0__REG DENALI_CTL_368
+#define LPDDR4__OUT_OF_RANGE_ADDR_0__FLD LPDDR4__DENALI_CTL_368__OUT_OF_RANGE_ADDR_0
+
+#define LPDDR4__DENALI_CTL_369_READ_MASK 0x7F0FFF07U
+#define LPDDR4__DENALI_CTL_369_WRITE_MASK 0x7F0FFF07U
+#define LPDDR4__DENALI_CTL_369__OUT_OF_RANGE_ADDR_1_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_369__OUT_OF_RANGE_ADDR_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_369__OUT_OF_RANGE_ADDR_1_WIDTH 3U
+#define LPDDR4__OUT_OF_RANGE_ADDR_1__REG DENALI_CTL_369
+#define LPDDR4__OUT_OF_RANGE_ADDR_1__FLD LPDDR4__DENALI_CTL_369__OUT_OF_RANGE_ADDR_1
+
+#define LPDDR4__DENALI_CTL_369__OUT_OF_RANGE_LENGTH_MASK 0x000FFF00U
+#define LPDDR4__DENALI_CTL_369__OUT_OF_RANGE_LENGTH_SHIFT 8U
+#define LPDDR4__DENALI_CTL_369__OUT_OF_RANGE_LENGTH_WIDTH 12U
+#define LPDDR4__OUT_OF_RANGE_LENGTH__REG DENALI_CTL_369
+#define LPDDR4__OUT_OF_RANGE_LENGTH__FLD LPDDR4__DENALI_CTL_369__OUT_OF_RANGE_LENGTH
+
+#define LPDDR4__DENALI_CTL_369__OUT_OF_RANGE_TYPE_MASK 0x7F000000U
+#define LPDDR4__DENALI_CTL_369__OUT_OF_RANGE_TYPE_SHIFT 24U
+#define LPDDR4__DENALI_CTL_369__OUT_OF_RANGE_TYPE_WIDTH 7U
+#define LPDDR4__OUT_OF_RANGE_TYPE__REG DENALI_CTL_369
+#define LPDDR4__OUT_OF_RANGE_TYPE__FLD LPDDR4__DENALI_CTL_369__OUT_OF_RANGE_TYPE
+
+#define LPDDR4__DENALI_CTL_370_READ_MASK 0x0000003FU
+#define LPDDR4__DENALI_CTL_370_WRITE_MASK 0x0000003FU
+#define LPDDR4__DENALI_CTL_370__OUT_OF_RANGE_SOURCE_ID_MASK 0x0000003FU
+#define LPDDR4__DENALI_CTL_370__OUT_OF_RANGE_SOURCE_ID_SHIFT 0U
+#define LPDDR4__DENALI_CTL_370__OUT_OF_RANGE_SOURCE_ID_WIDTH 6U
+#define LPDDR4__OUT_OF_RANGE_SOURCE_ID__REG DENALI_CTL_370
+#define LPDDR4__OUT_OF_RANGE_SOURCE_ID__FLD LPDDR4__DENALI_CTL_370__OUT_OF_RANGE_SOURCE_ID
+
+#define LPDDR4__DENALI_CTL_371_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_371_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_371__BIST_EXP_DATA_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_371__BIST_EXP_DATA_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_371__BIST_EXP_DATA_0_WIDTH 32U
+#define LPDDR4__BIST_EXP_DATA_0__REG DENALI_CTL_371
+#define LPDDR4__BIST_EXP_DATA_0__FLD LPDDR4__DENALI_CTL_371__BIST_EXP_DATA_0
+
+#define LPDDR4__DENALI_CTL_372_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_372_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_372__BIST_EXP_DATA_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_372__BIST_EXP_DATA_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_372__BIST_EXP_DATA_1_WIDTH 32U
+#define LPDDR4__BIST_EXP_DATA_1__REG DENALI_CTL_372
+#define LPDDR4__BIST_EXP_DATA_1__FLD LPDDR4__DENALI_CTL_372__BIST_EXP_DATA_1
+
+#define LPDDR4__DENALI_CTL_373_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_373_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_373__BIST_EXP_DATA_2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_373__BIST_EXP_DATA_2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_373__BIST_EXP_DATA_2_WIDTH 32U
+#define LPDDR4__BIST_EXP_DATA_2__REG DENALI_CTL_373
+#define LPDDR4__BIST_EXP_DATA_2__FLD LPDDR4__DENALI_CTL_373__BIST_EXP_DATA_2
+
+#define LPDDR4__DENALI_CTL_374_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_374_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_374__BIST_EXP_DATA_3_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_374__BIST_EXP_DATA_3_SHIFT 0U
+#define LPDDR4__DENALI_CTL_374__BIST_EXP_DATA_3_WIDTH 32U
+#define LPDDR4__BIST_EXP_DATA_3__REG DENALI_CTL_374
+#define LPDDR4__BIST_EXP_DATA_3__FLD LPDDR4__DENALI_CTL_374__BIST_EXP_DATA_3
+
+#define LPDDR4__DENALI_CTL_375_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_375_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_375__BIST_FAIL_DATA_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_375__BIST_FAIL_DATA_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_375__BIST_FAIL_DATA_0_WIDTH 32U
+#define LPDDR4__BIST_FAIL_DATA_0__REG DENALI_CTL_375
+#define LPDDR4__BIST_FAIL_DATA_0__FLD LPDDR4__DENALI_CTL_375__BIST_FAIL_DATA_0
+
+#define LPDDR4__DENALI_CTL_376_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_376_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_376__BIST_FAIL_DATA_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_376__BIST_FAIL_DATA_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_376__BIST_FAIL_DATA_1_WIDTH 32U
+#define LPDDR4__BIST_FAIL_DATA_1__REG DENALI_CTL_376
+#define LPDDR4__BIST_FAIL_DATA_1__FLD LPDDR4__DENALI_CTL_376__BIST_FAIL_DATA_1
+
+#define LPDDR4__DENALI_CTL_377_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_377_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_377__BIST_FAIL_DATA_2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_377__BIST_FAIL_DATA_2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_377__BIST_FAIL_DATA_2_WIDTH 32U
+#define LPDDR4__BIST_FAIL_DATA_2__REG DENALI_CTL_377
+#define LPDDR4__BIST_FAIL_DATA_2__FLD LPDDR4__DENALI_CTL_377__BIST_FAIL_DATA_2
+
+#define LPDDR4__DENALI_CTL_378_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_378_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_378__BIST_FAIL_DATA_3_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_378__BIST_FAIL_DATA_3_SHIFT 0U
+#define LPDDR4__DENALI_CTL_378__BIST_FAIL_DATA_3_WIDTH 32U
+#define LPDDR4__BIST_FAIL_DATA_3__REG DENALI_CTL_378
+#define LPDDR4__BIST_FAIL_DATA_3__FLD LPDDR4__DENALI_CTL_378__BIST_FAIL_DATA_3
+
+#define LPDDR4__DENALI_CTL_379_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_379_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_379__BIST_FAIL_ADDR_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_379__BIST_FAIL_ADDR_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_379__BIST_FAIL_ADDR_0_WIDTH 32U
+#define LPDDR4__BIST_FAIL_ADDR_0__REG DENALI_CTL_379
+#define LPDDR4__BIST_FAIL_ADDR_0__FLD LPDDR4__DENALI_CTL_379__BIST_FAIL_ADDR_0
+
+#define LPDDR4__DENALI_CTL_380_READ_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_380_WRITE_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_380__BIST_FAIL_ADDR_1_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_380__BIST_FAIL_ADDR_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_380__BIST_FAIL_ADDR_1_WIDTH 3U
+#define LPDDR4__BIST_FAIL_ADDR_1__REG DENALI_CTL_380
+#define LPDDR4__BIST_FAIL_ADDR_1__FLD LPDDR4__DENALI_CTL_380__BIST_FAIL_ADDR_1
+
+#define LPDDR4__DENALI_CTL_381_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_381_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_381__PORT_CMD_ERROR_ADDR_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_381__PORT_CMD_ERROR_ADDR_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_381__PORT_CMD_ERROR_ADDR_0_WIDTH 32U
+#define LPDDR4__PORT_CMD_ERROR_ADDR_0__REG DENALI_CTL_381
+#define LPDDR4__PORT_CMD_ERROR_ADDR_0__FLD LPDDR4__DENALI_CTL_381__PORT_CMD_ERROR_ADDR_0
+
+#define LPDDR4__DENALI_CTL_382_READ_MASK 0xFF033F07U
+#define LPDDR4__DENALI_CTL_382_WRITE_MASK 0xFF033F07U
+#define LPDDR4__DENALI_CTL_382__PORT_CMD_ERROR_ADDR_1_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_382__PORT_CMD_ERROR_ADDR_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_382__PORT_CMD_ERROR_ADDR_1_WIDTH 3U
+#define LPDDR4__PORT_CMD_ERROR_ADDR_1__REG DENALI_CTL_382
+#define LPDDR4__PORT_CMD_ERROR_ADDR_1__FLD LPDDR4__DENALI_CTL_382__PORT_CMD_ERROR_ADDR_1
+
+#define LPDDR4__DENALI_CTL_382__PORT_CMD_ERROR_ID_MASK 0x00003F00U
+#define LPDDR4__DENALI_CTL_382__PORT_CMD_ERROR_ID_SHIFT 8U
+#define LPDDR4__DENALI_CTL_382__PORT_CMD_ERROR_ID_WIDTH 6U
+#define LPDDR4__PORT_CMD_ERROR_ID__REG DENALI_CTL_382
+#define LPDDR4__PORT_CMD_ERROR_ID__FLD LPDDR4__DENALI_CTL_382__PORT_CMD_ERROR_ID
+
+#define LPDDR4__DENALI_CTL_382__PORT_CMD_ERROR_TYPE_MASK 0x00030000U
+#define LPDDR4__DENALI_CTL_382__PORT_CMD_ERROR_TYPE_SHIFT 16U
+#define LPDDR4__DENALI_CTL_382__PORT_CMD_ERROR_TYPE_WIDTH 2U
+#define LPDDR4__PORT_CMD_ERROR_TYPE__REG DENALI_CTL_382
+#define LPDDR4__PORT_CMD_ERROR_TYPE__FLD LPDDR4__DENALI_CTL_382__PORT_CMD_ERROR_TYPE
+
+#define LPDDR4__DENALI_CTL_382__TODTL_2CMD_F0_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_382__TODTL_2CMD_F0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_382__TODTL_2CMD_F0_WIDTH 8U
+#define LPDDR4__TODTL_2CMD_F0__REG DENALI_CTL_382
+#define LPDDR4__TODTL_2CMD_F0__FLD LPDDR4__DENALI_CTL_382__TODTL_2CMD_F0
+
+#define LPDDR4__DENALI_CTL_383_READ_MASK 0x0FFF0F0FU
+#define LPDDR4__DENALI_CTL_383_WRITE_MASK 0x0FFF0F0FU
+#define LPDDR4__DENALI_CTL_383__TODTH_WR_F0_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_383__TODTH_WR_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_383__TODTH_WR_F0_WIDTH 4U
+#define LPDDR4__TODTH_WR_F0__REG DENALI_CTL_383
+#define LPDDR4__TODTH_WR_F0__FLD LPDDR4__DENALI_CTL_383__TODTH_WR_F0
+
+#define LPDDR4__DENALI_CTL_383__TODTH_RD_F0_MASK 0x00000F00U
+#define LPDDR4__DENALI_CTL_383__TODTH_RD_F0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_383__TODTH_RD_F0_WIDTH 4U
+#define LPDDR4__TODTH_RD_F0__REG DENALI_CTL_383
+#define LPDDR4__TODTH_RD_F0__FLD LPDDR4__DENALI_CTL_383__TODTH_RD_F0
+
+#define LPDDR4__DENALI_CTL_383__TODTL_2CMD_F1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_383__TODTL_2CMD_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_383__TODTL_2CMD_F1_WIDTH 8U
+#define LPDDR4__TODTL_2CMD_F1__REG DENALI_CTL_383
+#define LPDDR4__TODTL_2CMD_F1__FLD LPDDR4__DENALI_CTL_383__TODTL_2CMD_F1
+
+#define LPDDR4__DENALI_CTL_383__TODTH_WR_F1_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_383__TODTH_WR_F1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_383__TODTH_WR_F1_WIDTH 4U
+#define LPDDR4__TODTH_WR_F1__REG DENALI_CTL_383
+#define LPDDR4__TODTH_WR_F1__FLD LPDDR4__DENALI_CTL_383__TODTH_WR_F1
+
+#define LPDDR4__DENALI_CTL_384_READ_MASK 0x0F0FFF0FU
+#define LPDDR4__DENALI_CTL_384_WRITE_MASK 0x0F0FFF0FU
+#define LPDDR4__DENALI_CTL_384__TODTH_RD_F1_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_384__TODTH_RD_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_384__TODTH_RD_F1_WIDTH 4U
+#define LPDDR4__TODTH_RD_F1__REG DENALI_CTL_384
+#define LPDDR4__TODTH_RD_F1__FLD LPDDR4__DENALI_CTL_384__TODTH_RD_F1
+
+#define LPDDR4__DENALI_CTL_384__TODTL_2CMD_F2_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_384__TODTL_2CMD_F2_SHIFT 8U
+#define LPDDR4__DENALI_CTL_384__TODTL_2CMD_F2_WIDTH 8U
+#define LPDDR4__TODTL_2CMD_F2__REG DENALI_CTL_384
+#define LPDDR4__TODTL_2CMD_F2__FLD LPDDR4__DENALI_CTL_384__TODTL_2CMD_F2
+
+#define LPDDR4__DENALI_CTL_384__TODTH_WR_F2_MASK 0x000F0000U
+#define LPDDR4__DENALI_CTL_384__TODTH_WR_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_384__TODTH_WR_F2_WIDTH 4U
+#define LPDDR4__TODTH_WR_F2__REG DENALI_CTL_384
+#define LPDDR4__TODTH_WR_F2__FLD LPDDR4__DENALI_CTL_384__TODTH_WR_F2
+
+#define LPDDR4__DENALI_CTL_384__TODTH_RD_F2_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_384__TODTH_RD_F2_SHIFT 24U
+#define LPDDR4__DENALI_CTL_384__TODTH_RD_F2_WIDTH 4U
+#define LPDDR4__TODTH_RD_F2__REG DENALI_CTL_384
+#define LPDDR4__TODTH_RD_F2__FLD LPDDR4__DENALI_CTL_384__TODTH_RD_F2
+
+#define LPDDR4__DENALI_CTL_385_READ_MASK 0x01010101U
+#define LPDDR4__DENALI_CTL_385_WRITE_MASK 0x01010101U
+#define LPDDR4__DENALI_CTL_385__ODT_EN_F0_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_385__ODT_EN_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_385__ODT_EN_F0_WIDTH 1U
+#define LPDDR4__DENALI_CTL_385__ODT_EN_F0_WOCLR 0U
+#define LPDDR4__DENALI_CTL_385__ODT_EN_F0_WOSET 0U
+#define LPDDR4__ODT_EN_F0__REG DENALI_CTL_385
+#define LPDDR4__ODT_EN_F0__FLD LPDDR4__DENALI_CTL_385__ODT_EN_F0
+
+#define LPDDR4__DENALI_CTL_385__ODT_EN_F1_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_385__ODT_EN_F1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_385__ODT_EN_F1_WIDTH 1U
+#define LPDDR4__DENALI_CTL_385__ODT_EN_F1_WOCLR 0U
+#define LPDDR4__DENALI_CTL_385__ODT_EN_F1_WOSET 0U
+#define LPDDR4__ODT_EN_F1__REG DENALI_CTL_385
+#define LPDDR4__ODT_EN_F1__FLD LPDDR4__DENALI_CTL_385__ODT_EN_F1
+
+#define LPDDR4__DENALI_CTL_385__ODT_EN_F2_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_385__ODT_EN_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_385__ODT_EN_F2_WIDTH 1U
+#define LPDDR4__DENALI_CTL_385__ODT_EN_F2_WOCLR 0U
+#define LPDDR4__DENALI_CTL_385__ODT_EN_F2_WOSET 0U
+#define LPDDR4__ODT_EN_F2__REG DENALI_CTL_385
+#define LPDDR4__ODT_EN_F2__FLD LPDDR4__DENALI_CTL_385__ODT_EN_F2
+
+#define LPDDR4__DENALI_CTL_385__EN_ODT_ASSERT_EXCEPT_RD_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_385__EN_ODT_ASSERT_EXCEPT_RD_SHIFT 24U
+#define LPDDR4__DENALI_CTL_385__EN_ODT_ASSERT_EXCEPT_RD_WIDTH 1U
+#define LPDDR4__DENALI_CTL_385__EN_ODT_ASSERT_EXCEPT_RD_WOCLR 0U
+#define LPDDR4__DENALI_CTL_385__EN_ODT_ASSERT_EXCEPT_RD_WOSET 0U
+#define LPDDR4__EN_ODT_ASSERT_EXCEPT_RD__REG DENALI_CTL_385
+#define LPDDR4__EN_ODT_ASSERT_EXCEPT_RD__FLD LPDDR4__DENALI_CTL_385__EN_ODT_ASSERT_EXCEPT_RD
+
+#define LPDDR4__DENALI_CTL_386_READ_MASK 0x033F3F3FU
+#define LPDDR4__DENALI_CTL_386_WRITE_MASK 0x033F3F3FU
+#define LPDDR4__DENALI_CTL_386__WR_TO_ODTH_F0_MASK 0x0000003FU
+#define LPDDR4__DENALI_CTL_386__WR_TO_ODTH_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_386__WR_TO_ODTH_F0_WIDTH 6U
+#define LPDDR4__WR_TO_ODTH_F0__REG DENALI_CTL_386
+#define LPDDR4__WR_TO_ODTH_F0__FLD LPDDR4__DENALI_CTL_386__WR_TO_ODTH_F0
+
+#define LPDDR4__DENALI_CTL_386__WR_TO_ODTH_F1_MASK 0x00003F00U
+#define LPDDR4__DENALI_CTL_386__WR_TO_ODTH_F1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_386__WR_TO_ODTH_F1_WIDTH 6U
+#define LPDDR4__WR_TO_ODTH_F1__REG DENALI_CTL_386
+#define LPDDR4__WR_TO_ODTH_F1__FLD LPDDR4__DENALI_CTL_386__WR_TO_ODTH_F1
+
+#define LPDDR4__DENALI_CTL_386__WR_TO_ODTH_F2_MASK 0x003F0000U
+#define LPDDR4__DENALI_CTL_386__WR_TO_ODTH_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_386__WR_TO_ODTH_F2_WIDTH 6U
+#define LPDDR4__WR_TO_ODTH_F2__REG DENALI_CTL_386
+#define LPDDR4__WR_TO_ODTH_F2__FLD LPDDR4__DENALI_CTL_386__WR_TO_ODTH_F2
+
+#define LPDDR4__DENALI_CTL_386__ODT_RD_MAP_CS0_MASK 0x03000000U
+#define LPDDR4__DENALI_CTL_386__ODT_RD_MAP_CS0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_386__ODT_RD_MAP_CS0_WIDTH 2U
+#define LPDDR4__ODT_RD_MAP_CS0__REG DENALI_CTL_386
+#define LPDDR4__ODT_RD_MAP_CS0__FLD LPDDR4__DENALI_CTL_386__ODT_RD_MAP_CS0
+
+#define LPDDR4__DENALI_CTL_387_READ_MASK 0x3F030303U
+#define LPDDR4__DENALI_CTL_387_WRITE_MASK 0x3F030303U
+#define LPDDR4__DENALI_CTL_387__ODT_WR_MAP_CS0_MASK 0x00000003U
+#define LPDDR4__DENALI_CTL_387__ODT_WR_MAP_CS0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_387__ODT_WR_MAP_CS0_WIDTH 2U
+#define LPDDR4__ODT_WR_MAP_CS0__REG DENALI_CTL_387
+#define LPDDR4__ODT_WR_MAP_CS0__FLD LPDDR4__DENALI_CTL_387__ODT_WR_MAP_CS0
+
+#define LPDDR4__DENALI_CTL_387__ODT_RD_MAP_CS1_MASK 0x00000300U
+#define LPDDR4__DENALI_CTL_387__ODT_RD_MAP_CS1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_387__ODT_RD_MAP_CS1_WIDTH 2U
+#define LPDDR4__ODT_RD_MAP_CS1__REG DENALI_CTL_387
+#define LPDDR4__ODT_RD_MAP_CS1__FLD LPDDR4__DENALI_CTL_387__ODT_RD_MAP_CS1
+
+#define LPDDR4__DENALI_CTL_387__ODT_WR_MAP_CS1_MASK 0x00030000U
+#define LPDDR4__DENALI_CTL_387__ODT_WR_MAP_CS1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_387__ODT_WR_MAP_CS1_WIDTH 2U
+#define LPDDR4__ODT_WR_MAP_CS1__REG DENALI_CTL_387
+#define LPDDR4__ODT_WR_MAP_CS1__FLD LPDDR4__DENALI_CTL_387__ODT_WR_MAP_CS1
+
+#define LPDDR4__DENALI_CTL_387__RD_TO_ODTH_F0_MASK 0x3F000000U
+#define LPDDR4__DENALI_CTL_387__RD_TO_ODTH_F0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_387__RD_TO_ODTH_F0_WIDTH 6U
+#define LPDDR4__RD_TO_ODTH_F0__REG DENALI_CTL_387
+#define LPDDR4__RD_TO_ODTH_F0__FLD LPDDR4__DENALI_CTL_387__RD_TO_ODTH_F0
+
+#define LPDDR4__DENALI_CTL_388_READ_MASK 0x1F1F3F3FU
+#define LPDDR4__DENALI_CTL_388_WRITE_MASK 0x1F1F3F3FU
+#define LPDDR4__DENALI_CTL_388__RD_TO_ODTH_F1_MASK 0x0000003FU
+#define LPDDR4__DENALI_CTL_388__RD_TO_ODTH_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_388__RD_TO_ODTH_F1_WIDTH 6U
+#define LPDDR4__RD_TO_ODTH_F1__REG DENALI_CTL_388
+#define LPDDR4__RD_TO_ODTH_F1__FLD LPDDR4__DENALI_CTL_388__RD_TO_ODTH_F1
+
+#define LPDDR4__DENALI_CTL_388__RD_TO_ODTH_F2_MASK 0x00003F00U
+#define LPDDR4__DENALI_CTL_388__RD_TO_ODTH_F2_SHIFT 8U
+#define LPDDR4__DENALI_CTL_388__RD_TO_ODTH_F2_WIDTH 6U
+#define LPDDR4__RD_TO_ODTH_F2__REG DENALI_CTL_388
+#define LPDDR4__RD_TO_ODTH_F2__FLD LPDDR4__DENALI_CTL_388__RD_TO_ODTH_F2
+
+#define LPDDR4__DENALI_CTL_388__RW2MRW_DLY_F0_MASK 0x001F0000U
+#define LPDDR4__DENALI_CTL_388__RW2MRW_DLY_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_388__RW2MRW_DLY_F0_WIDTH 5U
+#define LPDDR4__RW2MRW_DLY_F0__REG DENALI_CTL_388
+#define LPDDR4__RW2MRW_DLY_F0__FLD LPDDR4__DENALI_CTL_388__RW2MRW_DLY_F0
+
+#define LPDDR4__DENALI_CTL_388__RW2MRW_DLY_F1_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_388__RW2MRW_DLY_F1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_388__RW2MRW_DLY_F1_WIDTH 5U
+#define LPDDR4__RW2MRW_DLY_F1__REG DENALI_CTL_388
+#define LPDDR4__RW2MRW_DLY_F1__FLD LPDDR4__DENALI_CTL_388__RW2MRW_DLY_F1
+
+#define LPDDR4__DENALI_CTL_389_READ_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_389_WRITE_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_389__RW2MRW_DLY_F2_MASK 0x0000001FU
+#define LPDDR4__DENALI_CTL_389__RW2MRW_DLY_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_389__RW2MRW_DLY_F2_WIDTH 5U
+#define LPDDR4__RW2MRW_DLY_F2__REG DENALI_CTL_389
+#define LPDDR4__RW2MRW_DLY_F2__FLD LPDDR4__DENALI_CTL_389__RW2MRW_DLY_F2
+
+#define LPDDR4__DENALI_CTL_389__R2R_DIFFCS_DLY_F0_MASK 0x00001F00U
+#define LPDDR4__DENALI_CTL_389__R2R_DIFFCS_DLY_F0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_389__R2R_DIFFCS_DLY_F0_WIDTH 5U
+#define LPDDR4__R2R_DIFFCS_DLY_F0__REG DENALI_CTL_389
+#define LPDDR4__R2R_DIFFCS_DLY_F0__FLD LPDDR4__DENALI_CTL_389__R2R_DIFFCS_DLY_F0
+
+#define LPDDR4__DENALI_CTL_389__R2W_DIFFCS_DLY_F0_MASK 0x001F0000U
+#define LPDDR4__DENALI_CTL_389__R2W_DIFFCS_DLY_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_389__R2W_DIFFCS_DLY_F0_WIDTH 5U
+#define LPDDR4__R2W_DIFFCS_DLY_F0__REG DENALI_CTL_389
+#define LPDDR4__R2W_DIFFCS_DLY_F0__FLD LPDDR4__DENALI_CTL_389__R2W_DIFFCS_DLY_F0
+
+#define LPDDR4__DENALI_CTL_389__W2R_DIFFCS_DLY_F0_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_389__W2R_DIFFCS_DLY_F0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_389__W2R_DIFFCS_DLY_F0_WIDTH 5U
+#define LPDDR4__W2R_DIFFCS_DLY_F0__REG DENALI_CTL_389
+#define LPDDR4__W2R_DIFFCS_DLY_F0__FLD LPDDR4__DENALI_CTL_389__W2R_DIFFCS_DLY_F0
+
+#define LPDDR4__DENALI_CTL_390_READ_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_390_WRITE_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_390__W2W_DIFFCS_DLY_F0_MASK 0x0000001FU
+#define LPDDR4__DENALI_CTL_390__W2W_DIFFCS_DLY_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_390__W2W_DIFFCS_DLY_F0_WIDTH 5U
+#define LPDDR4__W2W_DIFFCS_DLY_F0__REG DENALI_CTL_390
+#define LPDDR4__W2W_DIFFCS_DLY_F0__FLD LPDDR4__DENALI_CTL_390__W2W_DIFFCS_DLY_F0
+
+#define LPDDR4__DENALI_CTL_390__R2R_DIFFCS_DLY_F1_MASK 0x00001F00U
+#define LPDDR4__DENALI_CTL_390__R2R_DIFFCS_DLY_F1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_390__R2R_DIFFCS_DLY_F1_WIDTH 5U
+#define LPDDR4__R2R_DIFFCS_DLY_F1__REG DENALI_CTL_390
+#define LPDDR4__R2R_DIFFCS_DLY_F1__FLD LPDDR4__DENALI_CTL_390__R2R_DIFFCS_DLY_F1
+
+#define LPDDR4__DENALI_CTL_390__R2W_DIFFCS_DLY_F1_MASK 0x001F0000U
+#define LPDDR4__DENALI_CTL_390__R2W_DIFFCS_DLY_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_390__R2W_DIFFCS_DLY_F1_WIDTH 5U
+#define LPDDR4__R2W_DIFFCS_DLY_F1__REG DENALI_CTL_390
+#define LPDDR4__R2W_DIFFCS_DLY_F1__FLD LPDDR4__DENALI_CTL_390__R2W_DIFFCS_DLY_F1
+
+#define LPDDR4__DENALI_CTL_390__W2R_DIFFCS_DLY_F1_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_390__W2R_DIFFCS_DLY_F1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_390__W2R_DIFFCS_DLY_F1_WIDTH 5U
+#define LPDDR4__W2R_DIFFCS_DLY_F1__REG DENALI_CTL_390
+#define LPDDR4__W2R_DIFFCS_DLY_F1__FLD LPDDR4__DENALI_CTL_390__W2R_DIFFCS_DLY_F1
+
+#define LPDDR4__DENALI_CTL_391_READ_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_391_WRITE_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_391__W2W_DIFFCS_DLY_F1_MASK 0x0000001FU
+#define LPDDR4__DENALI_CTL_391__W2W_DIFFCS_DLY_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_391__W2W_DIFFCS_DLY_F1_WIDTH 5U
+#define LPDDR4__W2W_DIFFCS_DLY_F1__REG DENALI_CTL_391
+#define LPDDR4__W2W_DIFFCS_DLY_F1__FLD LPDDR4__DENALI_CTL_391__W2W_DIFFCS_DLY_F1
+
+#define LPDDR4__DENALI_CTL_391__R2R_DIFFCS_DLY_F2_MASK 0x00001F00U
+#define LPDDR4__DENALI_CTL_391__R2R_DIFFCS_DLY_F2_SHIFT 8U
+#define LPDDR4__DENALI_CTL_391__R2R_DIFFCS_DLY_F2_WIDTH 5U
+#define LPDDR4__R2R_DIFFCS_DLY_F2__REG DENALI_CTL_391
+#define LPDDR4__R2R_DIFFCS_DLY_F2__FLD LPDDR4__DENALI_CTL_391__R2R_DIFFCS_DLY_F2
+
+#define LPDDR4__DENALI_CTL_391__R2W_DIFFCS_DLY_F2_MASK 0x001F0000U
+#define LPDDR4__DENALI_CTL_391__R2W_DIFFCS_DLY_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_391__R2W_DIFFCS_DLY_F2_WIDTH 5U
+#define LPDDR4__R2W_DIFFCS_DLY_F2__REG DENALI_CTL_391
+#define LPDDR4__R2W_DIFFCS_DLY_F2__FLD LPDDR4__DENALI_CTL_391__R2W_DIFFCS_DLY_F2
+
+#define LPDDR4__DENALI_CTL_391__W2R_DIFFCS_DLY_F2_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_391__W2R_DIFFCS_DLY_F2_SHIFT 24U
+#define LPDDR4__DENALI_CTL_391__W2R_DIFFCS_DLY_F2_WIDTH 5U
+#define LPDDR4__W2R_DIFFCS_DLY_F2__REG DENALI_CTL_391
+#define LPDDR4__W2R_DIFFCS_DLY_F2__FLD LPDDR4__DENALI_CTL_391__W2R_DIFFCS_DLY_F2
+
+#define LPDDR4__DENALI_CTL_392_READ_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_392_WRITE_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_392__W2W_DIFFCS_DLY_F2_MASK 0x0000001FU
+#define LPDDR4__DENALI_CTL_392__W2W_DIFFCS_DLY_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_392__W2W_DIFFCS_DLY_F2_WIDTH 5U
+#define LPDDR4__W2W_DIFFCS_DLY_F2__REG DENALI_CTL_392
+#define LPDDR4__W2W_DIFFCS_DLY_F2__FLD LPDDR4__DENALI_CTL_392__W2W_DIFFCS_DLY_F2
+
+#define LPDDR4__DENALI_CTL_392__R2W_SAMECS_DLY_F0_MASK 0x00001F00U
+#define LPDDR4__DENALI_CTL_392__R2W_SAMECS_DLY_F0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_392__R2W_SAMECS_DLY_F0_WIDTH 5U
+#define LPDDR4__R2W_SAMECS_DLY_F0__REG DENALI_CTL_392
+#define LPDDR4__R2W_SAMECS_DLY_F0__FLD LPDDR4__DENALI_CTL_392__R2W_SAMECS_DLY_F0
+
+#define LPDDR4__DENALI_CTL_392__R2W_SAMECS_DLY_F1_MASK 0x001F0000U
+#define LPDDR4__DENALI_CTL_392__R2W_SAMECS_DLY_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_392__R2W_SAMECS_DLY_F1_WIDTH 5U
+#define LPDDR4__R2W_SAMECS_DLY_F1__REG DENALI_CTL_392
+#define LPDDR4__R2W_SAMECS_DLY_F1__FLD LPDDR4__DENALI_CTL_392__R2W_SAMECS_DLY_F1
+
+#define LPDDR4__DENALI_CTL_392__R2W_SAMECS_DLY_F2_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_392__R2W_SAMECS_DLY_F2_SHIFT 24U
+#define LPDDR4__DENALI_CTL_392__R2W_SAMECS_DLY_F2_WIDTH 5U
+#define LPDDR4__R2W_SAMECS_DLY_F2__REG DENALI_CTL_392
+#define LPDDR4__R2W_SAMECS_DLY_F2__FLD LPDDR4__DENALI_CTL_392__R2W_SAMECS_DLY_F2
+
+#define LPDDR4__DENALI_CTL_393_READ_MASK 0x0F1F1F1FU
+#define LPDDR4__DENALI_CTL_393_WRITE_MASK 0x0F1F1F1FU
+#define LPDDR4__DENALI_CTL_393__R2R_SAMECS_DLY_MASK 0x0000001FU
+#define LPDDR4__DENALI_CTL_393__R2R_SAMECS_DLY_SHIFT 0U
+#define LPDDR4__DENALI_CTL_393__R2R_SAMECS_DLY_WIDTH 5U
+#define LPDDR4__R2R_SAMECS_DLY__REG DENALI_CTL_393
+#define LPDDR4__R2R_SAMECS_DLY__FLD LPDDR4__DENALI_CTL_393__R2R_SAMECS_DLY
+
+#define LPDDR4__DENALI_CTL_393__W2R_SAMECS_DLY_MASK 0x00001F00U
+#define LPDDR4__DENALI_CTL_393__W2R_SAMECS_DLY_SHIFT 8U
+#define LPDDR4__DENALI_CTL_393__W2R_SAMECS_DLY_WIDTH 5U
+#define LPDDR4__W2R_SAMECS_DLY__REG DENALI_CTL_393
+#define LPDDR4__W2R_SAMECS_DLY__FLD LPDDR4__DENALI_CTL_393__W2R_SAMECS_DLY
+
+#define LPDDR4__DENALI_CTL_393__W2W_SAMECS_DLY_MASK 0x001F0000U
+#define LPDDR4__DENALI_CTL_393__W2W_SAMECS_DLY_SHIFT 16U
+#define LPDDR4__DENALI_CTL_393__W2W_SAMECS_DLY_WIDTH 5U
+#define LPDDR4__W2W_SAMECS_DLY__REG DENALI_CTL_393
+#define LPDDR4__W2W_SAMECS_DLY__FLD LPDDR4__DENALI_CTL_393__W2W_SAMECS_DLY
+
+#define LPDDR4__DENALI_CTL_393__TDQSCK_MAX_F0_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_393__TDQSCK_MAX_F0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_393__TDQSCK_MAX_F0_WIDTH 4U
+#define LPDDR4__TDQSCK_MAX_F0__REG DENALI_CTL_393
+#define LPDDR4__TDQSCK_MAX_F0__FLD LPDDR4__DENALI_CTL_393__TDQSCK_MAX_F0
+
+#define LPDDR4__DENALI_CTL_394_READ_MASK 0x0F070F07U
+#define LPDDR4__DENALI_CTL_394_WRITE_MASK 0x0F070F07U
+#define LPDDR4__DENALI_CTL_394__TDQSCK_MIN_F0_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_394__TDQSCK_MIN_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_394__TDQSCK_MIN_F0_WIDTH 3U
+#define LPDDR4__TDQSCK_MIN_F0__REG DENALI_CTL_394
+#define LPDDR4__TDQSCK_MIN_F0__FLD LPDDR4__DENALI_CTL_394__TDQSCK_MIN_F0
+
+#define LPDDR4__DENALI_CTL_394__TDQSCK_MAX_F1_MASK 0x00000F00U
+#define LPDDR4__DENALI_CTL_394__TDQSCK_MAX_F1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_394__TDQSCK_MAX_F1_WIDTH 4U
+#define LPDDR4__TDQSCK_MAX_F1__REG DENALI_CTL_394
+#define LPDDR4__TDQSCK_MAX_F1__FLD LPDDR4__DENALI_CTL_394__TDQSCK_MAX_F1
+
+#define LPDDR4__DENALI_CTL_394__TDQSCK_MIN_F1_MASK 0x00070000U
+#define LPDDR4__DENALI_CTL_394__TDQSCK_MIN_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_394__TDQSCK_MIN_F1_WIDTH 3U
+#define LPDDR4__TDQSCK_MIN_F1__REG DENALI_CTL_394
+#define LPDDR4__TDQSCK_MIN_F1__FLD LPDDR4__DENALI_CTL_394__TDQSCK_MIN_F1
+
+#define LPDDR4__DENALI_CTL_394__TDQSCK_MAX_F2_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_394__TDQSCK_MAX_F2_SHIFT 24U
+#define LPDDR4__DENALI_CTL_394__TDQSCK_MAX_F2_WIDTH 4U
+#define LPDDR4__TDQSCK_MAX_F2__REG DENALI_CTL_394
+#define LPDDR4__TDQSCK_MAX_F2__FLD LPDDR4__DENALI_CTL_394__TDQSCK_MAX_F2
+
+#define LPDDR4__DENALI_CTL_395_READ_MASK 0x07010107U
+#define LPDDR4__DENALI_CTL_395_WRITE_MASK 0x07010107U
+#define LPDDR4__DENALI_CTL_395__TDQSCK_MIN_F2_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_395__TDQSCK_MIN_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_395__TDQSCK_MIN_F2_WIDTH 3U
+#define LPDDR4__TDQSCK_MIN_F2__REG DENALI_CTL_395
+#define LPDDR4__TDQSCK_MIN_F2__FLD LPDDR4__DENALI_CTL_395__TDQSCK_MIN_F2
+
+#define LPDDR4__DENALI_CTL_395__AXI0_ALL_STROBES_USED_ENABLE_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_395__AXI0_ALL_STROBES_USED_ENABLE_SHIFT 8U
+#define LPDDR4__DENALI_CTL_395__AXI0_ALL_STROBES_USED_ENABLE_WIDTH 1U
+#define LPDDR4__DENALI_CTL_395__AXI0_ALL_STROBES_USED_ENABLE_WOCLR 0U
+#define LPDDR4__DENALI_CTL_395__AXI0_ALL_STROBES_USED_ENABLE_WOSET 0U
+#define LPDDR4__AXI0_ALL_STROBES_USED_ENABLE__REG DENALI_CTL_395
+#define LPDDR4__AXI0_ALL_STROBES_USED_ENABLE__FLD LPDDR4__DENALI_CTL_395__AXI0_ALL_STROBES_USED_ENABLE
+
+#define LPDDR4__DENALI_CTL_395__AXI0_FIXED_PORT_PRIORITY_ENABLE_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_395__AXI0_FIXED_PORT_PRIORITY_ENABLE_SHIFT 16U
+#define LPDDR4__DENALI_CTL_395__AXI0_FIXED_PORT_PRIORITY_ENABLE_WIDTH 1U
+#define LPDDR4__DENALI_CTL_395__AXI0_FIXED_PORT_PRIORITY_ENABLE_WOCLR 0U
+#define LPDDR4__DENALI_CTL_395__AXI0_FIXED_PORT_PRIORITY_ENABLE_WOSET 0U
+#define LPDDR4__AXI0_FIXED_PORT_PRIORITY_ENABLE__REG DENALI_CTL_395
+#define LPDDR4__AXI0_FIXED_PORT_PRIORITY_ENABLE__FLD LPDDR4__DENALI_CTL_395__AXI0_FIXED_PORT_PRIORITY_ENABLE
+
+#define LPDDR4__DENALI_CTL_395__AXI0_R_PRIORITY_MASK 0x07000000U
+#define LPDDR4__DENALI_CTL_395__AXI0_R_PRIORITY_SHIFT 24U
+#define LPDDR4__DENALI_CTL_395__AXI0_R_PRIORITY_WIDTH 3U
+#define LPDDR4__AXI0_R_PRIORITY__REG DENALI_CTL_395
+#define LPDDR4__AXI0_R_PRIORITY__FLD LPDDR4__DENALI_CTL_395__AXI0_R_PRIORITY
+
+#define LPDDR4__DENALI_CTL_396_READ_MASK 0xFF010307U
+#define LPDDR4__DENALI_CTL_396_WRITE_MASK 0xFF010307U
+#define LPDDR4__DENALI_CTL_396__AXI0_W_PRIORITY_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_396__AXI0_W_PRIORITY_SHIFT 0U
+#define LPDDR4__DENALI_CTL_396__AXI0_W_PRIORITY_WIDTH 3U
+#define LPDDR4__AXI0_W_PRIORITY__REG DENALI_CTL_396
+#define LPDDR4__AXI0_W_PRIORITY__FLD LPDDR4__DENALI_CTL_396__AXI0_W_PRIORITY
+
+#define LPDDR4__DENALI_CTL_396__CKE_STATUS_MASK 0x00000300U
+#define LPDDR4__DENALI_CTL_396__CKE_STATUS_SHIFT 8U
+#define LPDDR4__DENALI_CTL_396__CKE_STATUS_WIDTH 2U
+#define LPDDR4__CKE_STATUS__REG DENALI_CTL_396
+#define LPDDR4__CKE_STATUS__FLD LPDDR4__DENALI_CTL_396__CKE_STATUS
+
+#define LPDDR4__DENALI_CTL_396__MEM_RST_VALID_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_396__MEM_RST_VALID_SHIFT 16U
+#define LPDDR4__DENALI_CTL_396__MEM_RST_VALID_WIDTH 1U
+#define LPDDR4__DENALI_CTL_396__MEM_RST_VALID_WOCLR 0U
+#define LPDDR4__DENALI_CTL_396__MEM_RST_VALID_WOSET 0U
+#define LPDDR4__MEM_RST_VALID__REG DENALI_CTL_396
+#define LPDDR4__MEM_RST_VALID__FLD LPDDR4__DENALI_CTL_396__MEM_RST_VALID
+
+#define LPDDR4__DENALI_CTL_396__TDFI_PHY_RDLAT_F0_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_396__TDFI_PHY_RDLAT_F0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_396__TDFI_PHY_RDLAT_F0_WIDTH 8U
+#define LPDDR4__TDFI_PHY_RDLAT_F0__REG DENALI_CTL_396
+#define LPDDR4__TDFI_PHY_RDLAT_F0__FLD LPDDR4__DENALI_CTL_396__TDFI_PHY_RDLAT_F0
+
+#define LPDDR4__DENALI_CTL_397_READ_MASK 0x001FFFFFU
+#define LPDDR4__DENALI_CTL_397_WRITE_MASK 0x001FFFFFU
+#define LPDDR4__DENALI_CTL_397__TDFI_CTRLUPD_MAX_F0_MASK 0x001FFFFFU
+#define LPDDR4__DENALI_CTL_397__TDFI_CTRLUPD_MAX_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_397__TDFI_CTRLUPD_MAX_F0_WIDTH 21U
+#define LPDDR4__TDFI_CTRLUPD_MAX_F0__REG DENALI_CTL_397
+#define LPDDR4__TDFI_CTRLUPD_MAX_F0__FLD LPDDR4__DENALI_CTL_397__TDFI_CTRLUPD_MAX_F0
+
+#define LPDDR4__DENALI_CTL_398_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_398_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_398__TDFI_PHYUPD_TYPE0_F0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_398__TDFI_PHYUPD_TYPE0_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_398__TDFI_PHYUPD_TYPE0_F0_WIDTH 32U
+#define LPDDR4__TDFI_PHYUPD_TYPE0_F0__REG DENALI_CTL_398
+#define LPDDR4__TDFI_PHYUPD_TYPE0_F0__FLD LPDDR4__DENALI_CTL_398__TDFI_PHYUPD_TYPE0_F0
+
+#define LPDDR4__DENALI_CTL_399_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_399_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_399__TDFI_PHYUPD_TYPE1_F0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_399__TDFI_PHYUPD_TYPE1_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_399__TDFI_PHYUPD_TYPE1_F0_WIDTH 32U
+#define LPDDR4__TDFI_PHYUPD_TYPE1_F0__REG DENALI_CTL_399
+#define LPDDR4__TDFI_PHYUPD_TYPE1_F0__FLD LPDDR4__DENALI_CTL_399__TDFI_PHYUPD_TYPE1_F0
+
+#define LPDDR4__DENALI_CTL_400_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_400_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_400__TDFI_PHYUPD_TYPE2_F0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_400__TDFI_PHYUPD_TYPE2_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_400__TDFI_PHYUPD_TYPE2_F0_WIDTH 32U
+#define LPDDR4__TDFI_PHYUPD_TYPE2_F0__REG DENALI_CTL_400
+#define LPDDR4__TDFI_PHYUPD_TYPE2_F0__FLD LPDDR4__DENALI_CTL_400__TDFI_PHYUPD_TYPE2_F0
+
+#define LPDDR4__DENALI_CTL_401_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_401_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_401__TDFI_PHYUPD_TYPE3_F0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_401__TDFI_PHYUPD_TYPE3_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_401__TDFI_PHYUPD_TYPE3_F0_WIDTH 32U
+#define LPDDR4__TDFI_PHYUPD_TYPE3_F0__REG DENALI_CTL_401
+#define LPDDR4__TDFI_PHYUPD_TYPE3_F0__FLD LPDDR4__DENALI_CTL_401__TDFI_PHYUPD_TYPE3_F0
+
+#define LPDDR4__DENALI_CTL_402_READ_MASK 0x007FFFFFU
+#define LPDDR4__DENALI_CTL_402_WRITE_MASK 0x007FFFFFU
+#define LPDDR4__DENALI_CTL_402__TDFI_PHYUPD_RESP_F0_MASK 0x007FFFFFU
+#define LPDDR4__DENALI_CTL_402__TDFI_PHYUPD_RESP_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_402__TDFI_PHYUPD_RESP_F0_WIDTH 23U
+#define LPDDR4__TDFI_PHYUPD_RESP_F0__REG DENALI_CTL_402
+#define LPDDR4__TDFI_PHYUPD_RESP_F0__FLD LPDDR4__DENALI_CTL_402__TDFI_PHYUPD_RESP_F0
+
+#define LPDDR4__DENALI_CTL_403_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_403_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_403__TDFI_CTRLUPD_INTERVAL_F0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_403__TDFI_CTRLUPD_INTERVAL_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_403__TDFI_CTRLUPD_INTERVAL_F0_WIDTH 32U
+#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F0__REG DENALI_CTL_403
+#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F0__FLD LPDDR4__DENALI_CTL_403__TDFI_CTRLUPD_INTERVAL_F0
+
+#define LPDDR4__DENALI_CTL_404_READ_MASK 0xFFFF070FU
+#define LPDDR4__DENALI_CTL_404_WRITE_MASK 0xFFFF070FU
+#define LPDDR4__DENALI_CTL_404__TDFI_CTRL_DELAY_F0_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_404__TDFI_CTRL_DELAY_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_404__TDFI_CTRL_DELAY_F0_WIDTH 4U
+#define LPDDR4__TDFI_CTRL_DELAY_F0__REG DENALI_CTL_404
+#define LPDDR4__TDFI_CTRL_DELAY_F0__FLD LPDDR4__DENALI_CTL_404__TDFI_CTRL_DELAY_F0
+
+#define LPDDR4__DENALI_CTL_404__TDFI_PHY_WRDATA_F0_MASK 0x00000700U
+#define LPDDR4__DENALI_CTL_404__TDFI_PHY_WRDATA_F0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_404__TDFI_PHY_WRDATA_F0_WIDTH 3U
+#define LPDDR4__TDFI_PHY_WRDATA_F0__REG DENALI_CTL_404
+#define LPDDR4__TDFI_PHY_WRDATA_F0__FLD LPDDR4__DENALI_CTL_404__TDFI_PHY_WRDATA_F0
+
+#define LPDDR4__DENALI_CTL_404__TDFI_RDCSLAT_F0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_404__TDFI_RDCSLAT_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_404__TDFI_RDCSLAT_F0_WIDTH 8U
+#define LPDDR4__TDFI_RDCSLAT_F0__REG DENALI_CTL_404
+#define LPDDR4__TDFI_RDCSLAT_F0__FLD LPDDR4__DENALI_CTL_404__TDFI_RDCSLAT_F0
+
+#define LPDDR4__DENALI_CTL_404__TDFI_RDDATA_EN_F0_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_404__TDFI_RDDATA_EN_F0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_404__TDFI_RDDATA_EN_F0_WIDTH 8U
+#define LPDDR4__TDFI_RDDATA_EN_F0__REG DENALI_CTL_404
+#define LPDDR4__TDFI_RDDATA_EN_F0__FLD LPDDR4__DENALI_CTL_404__TDFI_RDDATA_EN_F0
+
+#define LPDDR4__DENALI_CTL_405_READ_MASK 0xFF7FFFFFU
+#define LPDDR4__DENALI_CTL_405_WRITE_MASK 0xFF7FFFFFU
+#define LPDDR4__DENALI_CTL_405__TDFI_WRCSLAT_F0_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_405__TDFI_WRCSLAT_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_405__TDFI_WRCSLAT_F0_WIDTH 8U
+#define LPDDR4__TDFI_WRCSLAT_F0__REG DENALI_CTL_405
+#define LPDDR4__TDFI_WRCSLAT_F0__FLD LPDDR4__DENALI_CTL_405__TDFI_WRCSLAT_F0
+
+#define LPDDR4__DENALI_CTL_405__TDFI_PHY_WRLAT_F0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_405__TDFI_PHY_WRLAT_F0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_405__TDFI_PHY_WRLAT_F0_WIDTH 8U
+#define LPDDR4__TDFI_PHY_WRLAT_F0__REG DENALI_CTL_405
+#define LPDDR4__TDFI_PHY_WRLAT_F0__FLD LPDDR4__DENALI_CTL_405__TDFI_PHY_WRLAT_F0
+
+#define LPDDR4__DENALI_CTL_405__TDFI_CTRLMSG_RESP_F0_MASK 0x007F0000U
+#define LPDDR4__DENALI_CTL_405__TDFI_CTRLMSG_RESP_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_405__TDFI_CTRLMSG_RESP_F0_WIDTH 7U
+#define LPDDR4__TDFI_CTRLMSG_RESP_F0__REG DENALI_CTL_405
+#define LPDDR4__TDFI_CTRLMSG_RESP_F0__FLD LPDDR4__DENALI_CTL_405__TDFI_CTRLMSG_RESP_F0
+
+#define LPDDR4__DENALI_CTL_405__TDFI_PHY_RDLAT_F1_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_405__TDFI_PHY_RDLAT_F1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_405__TDFI_PHY_RDLAT_F1_WIDTH 8U
+#define LPDDR4__TDFI_PHY_RDLAT_F1__REG DENALI_CTL_405
+#define LPDDR4__TDFI_PHY_RDLAT_F1__FLD LPDDR4__DENALI_CTL_405__TDFI_PHY_RDLAT_F1
+
+#define LPDDR4__DENALI_CTL_406_READ_MASK 0x001FFFFFU
+#define LPDDR4__DENALI_CTL_406_WRITE_MASK 0x001FFFFFU
+#define LPDDR4__DENALI_CTL_406__TDFI_CTRLUPD_MAX_F1_MASK 0x001FFFFFU
+#define LPDDR4__DENALI_CTL_406__TDFI_CTRLUPD_MAX_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_406__TDFI_CTRLUPD_MAX_F1_WIDTH 21U
+#define LPDDR4__TDFI_CTRLUPD_MAX_F1__REG DENALI_CTL_406
+#define LPDDR4__TDFI_CTRLUPD_MAX_F1__FLD LPDDR4__DENALI_CTL_406__TDFI_CTRLUPD_MAX_F1
+
+#define LPDDR4__DENALI_CTL_407_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_407_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_407__TDFI_PHYUPD_TYPE0_F1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_407__TDFI_PHYUPD_TYPE0_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_407__TDFI_PHYUPD_TYPE0_F1_WIDTH 32U
+#define LPDDR4__TDFI_PHYUPD_TYPE0_F1__REG DENALI_CTL_407
+#define LPDDR4__TDFI_PHYUPD_TYPE0_F1__FLD LPDDR4__DENALI_CTL_407__TDFI_PHYUPD_TYPE0_F1
+
+#define LPDDR4__DENALI_CTL_408_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_408_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_408__TDFI_PHYUPD_TYPE1_F1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_408__TDFI_PHYUPD_TYPE1_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_408__TDFI_PHYUPD_TYPE1_F1_WIDTH 32U
+#define LPDDR4__TDFI_PHYUPD_TYPE1_F1__REG DENALI_CTL_408
+#define LPDDR4__TDFI_PHYUPD_TYPE1_F1__FLD LPDDR4__DENALI_CTL_408__TDFI_PHYUPD_TYPE1_F1
+
+#define LPDDR4__DENALI_CTL_409_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_409_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_409__TDFI_PHYUPD_TYPE2_F1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_409__TDFI_PHYUPD_TYPE2_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_409__TDFI_PHYUPD_TYPE2_F1_WIDTH 32U
+#define LPDDR4__TDFI_PHYUPD_TYPE2_F1__REG DENALI_CTL_409
+#define LPDDR4__TDFI_PHYUPD_TYPE2_F1__FLD LPDDR4__DENALI_CTL_409__TDFI_PHYUPD_TYPE2_F1
+
+#define LPDDR4__DENALI_CTL_410_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_410_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_410__TDFI_PHYUPD_TYPE3_F1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_410__TDFI_PHYUPD_TYPE3_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_410__TDFI_PHYUPD_TYPE3_F1_WIDTH 32U
+#define LPDDR4__TDFI_PHYUPD_TYPE3_F1__REG DENALI_CTL_410
+#define LPDDR4__TDFI_PHYUPD_TYPE3_F1__FLD LPDDR4__DENALI_CTL_410__TDFI_PHYUPD_TYPE3_F1
+
+#define LPDDR4__DENALI_CTL_411_READ_MASK 0x007FFFFFU
+#define LPDDR4__DENALI_CTL_411_WRITE_MASK 0x007FFFFFU
+#define LPDDR4__DENALI_CTL_411__TDFI_PHYUPD_RESP_F1_MASK 0x007FFFFFU
+#define LPDDR4__DENALI_CTL_411__TDFI_PHYUPD_RESP_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_411__TDFI_PHYUPD_RESP_F1_WIDTH 23U
+#define LPDDR4__TDFI_PHYUPD_RESP_F1__REG DENALI_CTL_411
+#define LPDDR4__TDFI_PHYUPD_RESP_F1__FLD LPDDR4__DENALI_CTL_411__TDFI_PHYUPD_RESP_F1
+
+#define LPDDR4__DENALI_CTL_412_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_412_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_412__TDFI_CTRLUPD_INTERVAL_F1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_412__TDFI_CTRLUPD_INTERVAL_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_412__TDFI_CTRLUPD_INTERVAL_F1_WIDTH 32U
+#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F1__REG DENALI_CTL_412
+#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F1__FLD LPDDR4__DENALI_CTL_412__TDFI_CTRLUPD_INTERVAL_F1
+
+#define LPDDR4__DENALI_CTL_413_READ_MASK 0xFFFF070FU
+#define LPDDR4__DENALI_CTL_413_WRITE_MASK 0xFFFF070FU
+#define LPDDR4__DENALI_CTL_413__TDFI_CTRL_DELAY_F1_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_413__TDFI_CTRL_DELAY_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_413__TDFI_CTRL_DELAY_F1_WIDTH 4U
+#define LPDDR4__TDFI_CTRL_DELAY_F1__REG DENALI_CTL_413
+#define LPDDR4__TDFI_CTRL_DELAY_F1__FLD LPDDR4__DENALI_CTL_413__TDFI_CTRL_DELAY_F1
+
+#define LPDDR4__DENALI_CTL_413__TDFI_PHY_WRDATA_F1_MASK 0x00000700U
+#define LPDDR4__DENALI_CTL_413__TDFI_PHY_WRDATA_F1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_413__TDFI_PHY_WRDATA_F1_WIDTH 3U
+#define LPDDR4__TDFI_PHY_WRDATA_F1__REG DENALI_CTL_413
+#define LPDDR4__TDFI_PHY_WRDATA_F1__FLD LPDDR4__DENALI_CTL_413__TDFI_PHY_WRDATA_F1
+
+#define LPDDR4__DENALI_CTL_413__TDFI_RDCSLAT_F1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_413__TDFI_RDCSLAT_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_413__TDFI_RDCSLAT_F1_WIDTH 8U
+#define LPDDR4__TDFI_RDCSLAT_F1__REG DENALI_CTL_413
+#define LPDDR4__TDFI_RDCSLAT_F1__FLD LPDDR4__DENALI_CTL_413__TDFI_RDCSLAT_F1
+
+#define LPDDR4__DENALI_CTL_413__TDFI_RDDATA_EN_F1_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_413__TDFI_RDDATA_EN_F1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_413__TDFI_RDDATA_EN_F1_WIDTH 8U
+#define LPDDR4__TDFI_RDDATA_EN_F1__REG DENALI_CTL_413
+#define LPDDR4__TDFI_RDDATA_EN_F1__FLD LPDDR4__DENALI_CTL_413__TDFI_RDDATA_EN_F1
+
+#define LPDDR4__DENALI_CTL_414_READ_MASK 0xFF7FFFFFU
+#define LPDDR4__DENALI_CTL_414_WRITE_MASK 0xFF7FFFFFU
+#define LPDDR4__DENALI_CTL_414__TDFI_WRCSLAT_F1_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_414__TDFI_WRCSLAT_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_414__TDFI_WRCSLAT_F1_WIDTH 8U
+#define LPDDR4__TDFI_WRCSLAT_F1__REG DENALI_CTL_414
+#define LPDDR4__TDFI_WRCSLAT_F1__FLD LPDDR4__DENALI_CTL_414__TDFI_WRCSLAT_F1
+
+#define LPDDR4__DENALI_CTL_414__TDFI_PHY_WRLAT_F1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_414__TDFI_PHY_WRLAT_F1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_414__TDFI_PHY_WRLAT_F1_WIDTH 8U
+#define LPDDR4__TDFI_PHY_WRLAT_F1__REG DENALI_CTL_414
+#define LPDDR4__TDFI_PHY_WRLAT_F1__FLD LPDDR4__DENALI_CTL_414__TDFI_PHY_WRLAT_F1
+
+#define LPDDR4__DENALI_CTL_414__TDFI_CTRLMSG_RESP_F1_MASK 0x007F0000U
+#define LPDDR4__DENALI_CTL_414__TDFI_CTRLMSG_RESP_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_414__TDFI_CTRLMSG_RESP_F1_WIDTH 7U
+#define LPDDR4__TDFI_CTRLMSG_RESP_F1__REG DENALI_CTL_414
+#define LPDDR4__TDFI_CTRLMSG_RESP_F1__FLD LPDDR4__DENALI_CTL_414__TDFI_CTRLMSG_RESP_F1
+
+#define LPDDR4__DENALI_CTL_414__TDFI_PHY_RDLAT_F2_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_414__TDFI_PHY_RDLAT_F2_SHIFT 24U
+#define LPDDR4__DENALI_CTL_414__TDFI_PHY_RDLAT_F2_WIDTH 8U
+#define LPDDR4__TDFI_PHY_RDLAT_F2__REG DENALI_CTL_414
+#define LPDDR4__TDFI_PHY_RDLAT_F2__FLD LPDDR4__DENALI_CTL_414__TDFI_PHY_RDLAT_F2
+
+#define LPDDR4__DENALI_CTL_415_READ_MASK 0x001FFFFFU
+#define LPDDR4__DENALI_CTL_415_WRITE_MASK 0x001FFFFFU
+#define LPDDR4__DENALI_CTL_415__TDFI_CTRLUPD_MAX_F2_MASK 0x001FFFFFU
+#define LPDDR4__DENALI_CTL_415__TDFI_CTRLUPD_MAX_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_415__TDFI_CTRLUPD_MAX_F2_WIDTH 21U
+#define LPDDR4__TDFI_CTRLUPD_MAX_F2__REG DENALI_CTL_415
+#define LPDDR4__TDFI_CTRLUPD_MAX_F2__FLD LPDDR4__DENALI_CTL_415__TDFI_CTRLUPD_MAX_F2
+
+#define LPDDR4__DENALI_CTL_416_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_416_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_416__TDFI_PHYUPD_TYPE0_F2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_416__TDFI_PHYUPD_TYPE0_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_416__TDFI_PHYUPD_TYPE0_F2_WIDTH 32U
+#define LPDDR4__TDFI_PHYUPD_TYPE0_F2__REG DENALI_CTL_416
+#define LPDDR4__TDFI_PHYUPD_TYPE0_F2__FLD LPDDR4__DENALI_CTL_416__TDFI_PHYUPD_TYPE0_F2
+
+#define LPDDR4__DENALI_CTL_417_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_417_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_417__TDFI_PHYUPD_TYPE1_F2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_417__TDFI_PHYUPD_TYPE1_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_417__TDFI_PHYUPD_TYPE1_F2_WIDTH 32U
+#define LPDDR4__TDFI_PHYUPD_TYPE1_F2__REG DENALI_CTL_417
+#define LPDDR4__TDFI_PHYUPD_TYPE1_F2__FLD LPDDR4__DENALI_CTL_417__TDFI_PHYUPD_TYPE1_F2
+
+#define LPDDR4__DENALI_CTL_418_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_418_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_418__TDFI_PHYUPD_TYPE2_F2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_418__TDFI_PHYUPD_TYPE2_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_418__TDFI_PHYUPD_TYPE2_F2_WIDTH 32U
+#define LPDDR4__TDFI_PHYUPD_TYPE2_F2__REG DENALI_CTL_418
+#define LPDDR4__TDFI_PHYUPD_TYPE2_F2__FLD LPDDR4__DENALI_CTL_418__TDFI_PHYUPD_TYPE2_F2
+
+#define LPDDR4__DENALI_CTL_419_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_419_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_419__TDFI_PHYUPD_TYPE3_F2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_419__TDFI_PHYUPD_TYPE3_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_419__TDFI_PHYUPD_TYPE3_F2_WIDTH 32U
+#define LPDDR4__TDFI_PHYUPD_TYPE3_F2__REG DENALI_CTL_419
+#define LPDDR4__TDFI_PHYUPD_TYPE3_F2__FLD LPDDR4__DENALI_CTL_419__TDFI_PHYUPD_TYPE3_F2
+
+#define LPDDR4__DENALI_CTL_420_READ_MASK 0x007FFFFFU
+#define LPDDR4__DENALI_CTL_420_WRITE_MASK 0x007FFFFFU
+#define LPDDR4__DENALI_CTL_420__TDFI_PHYUPD_RESP_F2_MASK 0x007FFFFFU
+#define LPDDR4__DENALI_CTL_420__TDFI_PHYUPD_RESP_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_420__TDFI_PHYUPD_RESP_F2_WIDTH 23U
+#define LPDDR4__TDFI_PHYUPD_RESP_F2__REG DENALI_CTL_420
+#define LPDDR4__TDFI_PHYUPD_RESP_F2__FLD LPDDR4__DENALI_CTL_420__TDFI_PHYUPD_RESP_F2
+
+#define LPDDR4__DENALI_CTL_421_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_421_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_421__TDFI_CTRLUPD_INTERVAL_F2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_421__TDFI_CTRLUPD_INTERVAL_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_421__TDFI_CTRLUPD_INTERVAL_F2_WIDTH 32U
+#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F2__REG DENALI_CTL_421
+#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F2__FLD LPDDR4__DENALI_CTL_421__TDFI_CTRLUPD_INTERVAL_F2
+
+#define LPDDR4__DENALI_CTL_422_READ_MASK 0xFFFF070FU
+#define LPDDR4__DENALI_CTL_422_WRITE_MASK 0xFFFF070FU
+#define LPDDR4__DENALI_CTL_422__TDFI_CTRL_DELAY_F2_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_422__TDFI_CTRL_DELAY_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_422__TDFI_CTRL_DELAY_F2_WIDTH 4U
+#define LPDDR4__TDFI_CTRL_DELAY_F2__REG DENALI_CTL_422
+#define LPDDR4__TDFI_CTRL_DELAY_F2__FLD LPDDR4__DENALI_CTL_422__TDFI_CTRL_DELAY_F2
+
+#define LPDDR4__DENALI_CTL_422__TDFI_PHY_WRDATA_F2_MASK 0x00000700U
+#define LPDDR4__DENALI_CTL_422__TDFI_PHY_WRDATA_F2_SHIFT 8U
+#define LPDDR4__DENALI_CTL_422__TDFI_PHY_WRDATA_F2_WIDTH 3U
+#define LPDDR4__TDFI_PHY_WRDATA_F2__REG DENALI_CTL_422
+#define LPDDR4__TDFI_PHY_WRDATA_F2__FLD LPDDR4__DENALI_CTL_422__TDFI_PHY_WRDATA_F2
+
+#define LPDDR4__DENALI_CTL_422__TDFI_RDCSLAT_F2_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_422__TDFI_RDCSLAT_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_422__TDFI_RDCSLAT_F2_WIDTH 8U
+#define LPDDR4__TDFI_RDCSLAT_F2__REG DENALI_CTL_422
+#define LPDDR4__TDFI_RDCSLAT_F2__FLD LPDDR4__DENALI_CTL_422__TDFI_RDCSLAT_F2
+
+#define LPDDR4__DENALI_CTL_422__TDFI_RDDATA_EN_F2_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_422__TDFI_RDDATA_EN_F2_SHIFT 24U
+#define LPDDR4__DENALI_CTL_422__TDFI_RDDATA_EN_F2_WIDTH 8U
+#define LPDDR4__TDFI_RDDATA_EN_F2__REG DENALI_CTL_422
+#define LPDDR4__TDFI_RDDATA_EN_F2__FLD LPDDR4__DENALI_CTL_422__TDFI_RDDATA_EN_F2
+
+#define LPDDR4__DENALI_CTL_423_READ_MASK 0x007FFFFFU
+#define LPDDR4__DENALI_CTL_423_WRITE_MASK 0x007FFFFFU
+#define LPDDR4__DENALI_CTL_423__TDFI_WRCSLAT_F2_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_423__TDFI_WRCSLAT_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_423__TDFI_WRCSLAT_F2_WIDTH 8U
+#define LPDDR4__TDFI_WRCSLAT_F2__REG DENALI_CTL_423
+#define LPDDR4__TDFI_WRCSLAT_F2__FLD LPDDR4__DENALI_CTL_423__TDFI_WRCSLAT_F2
+
+#define LPDDR4__DENALI_CTL_423__TDFI_PHY_WRLAT_F2_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_423__TDFI_PHY_WRLAT_F2_SHIFT 8U
+#define LPDDR4__DENALI_CTL_423__TDFI_PHY_WRLAT_F2_WIDTH 8U
+#define LPDDR4__TDFI_PHY_WRLAT_F2__REG DENALI_CTL_423
+#define LPDDR4__TDFI_PHY_WRLAT_F2__FLD LPDDR4__DENALI_CTL_423__TDFI_PHY_WRLAT_F2
+
+#define LPDDR4__DENALI_CTL_423__TDFI_CTRLMSG_RESP_F2_MASK 0x007F0000U
+#define LPDDR4__DENALI_CTL_423__TDFI_CTRLMSG_RESP_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_423__TDFI_CTRLMSG_RESP_F2_WIDTH 7U
+#define LPDDR4__TDFI_CTRLMSG_RESP_F2__REG DENALI_CTL_423
+#define LPDDR4__TDFI_CTRLMSG_RESP_F2__FLD LPDDR4__DENALI_CTL_423__TDFI_CTRLMSG_RESP_F2
+
+#define LPDDR4__DENALI_CTL_424_READ_MASK 0x7FFFFFFFU
+#define LPDDR4__DENALI_CTL_424_WRITE_MASK 0x7FFFFFFFU
+#define LPDDR4__DENALI_CTL_424__DLL_RST_DELAY_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_424__DLL_RST_DELAY_SHIFT 0U
+#define LPDDR4__DENALI_CTL_424__DLL_RST_DELAY_WIDTH 16U
+#define LPDDR4__DLL_RST_DELAY__REG DENALI_CTL_424
+#define LPDDR4__DLL_RST_DELAY__FLD LPDDR4__DENALI_CTL_424__DLL_RST_DELAY
+
+#define LPDDR4__DENALI_CTL_424__DLL_RST_ADJ_DLY_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_424__DLL_RST_ADJ_DLY_SHIFT 16U
+#define LPDDR4__DENALI_CTL_424__DLL_RST_ADJ_DLY_WIDTH 8U
+#define LPDDR4__DLL_RST_ADJ_DLY__REG DENALI_CTL_424
+#define LPDDR4__DLL_RST_ADJ_DLY__FLD LPDDR4__DENALI_CTL_424__DLL_RST_ADJ_DLY
+
+#define LPDDR4__DENALI_CTL_424__UPDATE_ERROR_STATUS_MASK 0x7F000000U
+#define LPDDR4__DENALI_CTL_424__UPDATE_ERROR_STATUS_SHIFT 24U
+#define LPDDR4__DENALI_CTL_424__UPDATE_ERROR_STATUS_WIDTH 7U
+#define LPDDR4__UPDATE_ERROR_STATUS__REG DENALI_CTL_424
+#define LPDDR4__UPDATE_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_424__UPDATE_ERROR_STATUS
+
+#define LPDDR4__DENALI_CTL_425_READ_MASK 0x0FFFFF03U
+#define LPDDR4__DENALI_CTL_425_WRITE_MASK 0x0FFFFF03U
+#define LPDDR4__DENALI_CTL_425__DRAM_CLK_DISABLE_MASK 0x00000003U
+#define LPDDR4__DENALI_CTL_425__DRAM_CLK_DISABLE_SHIFT 0U
+#define LPDDR4__DENALI_CTL_425__DRAM_CLK_DISABLE_WIDTH 2U
+#define LPDDR4__DRAM_CLK_DISABLE__REG DENALI_CTL_425
+#define LPDDR4__DRAM_CLK_DISABLE__FLD LPDDR4__DENALI_CTL_425__DRAM_CLK_DISABLE
+
+#define LPDDR4__DENALI_CTL_425__TDFI_CTRLUPD_MIN_MASK 0x00FFFF00U
+#define LPDDR4__DENALI_CTL_425__TDFI_CTRLUPD_MIN_SHIFT 8U
+#define LPDDR4__DENALI_CTL_425__TDFI_CTRLUPD_MIN_WIDTH 16U
+#define LPDDR4__TDFI_CTRLUPD_MIN__REG DENALI_CTL_425
+#define LPDDR4__TDFI_CTRLUPD_MIN__FLD LPDDR4__DENALI_CTL_425__TDFI_CTRLUPD_MIN
+
+#define LPDDR4__DENALI_CTL_425__TDFI_DRAM_CLK_DISABLE_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_425__TDFI_DRAM_CLK_DISABLE_SHIFT 24U
+#define LPDDR4__DENALI_CTL_425__TDFI_DRAM_CLK_DISABLE_WIDTH 4U
+#define LPDDR4__TDFI_DRAM_CLK_DISABLE__REG DENALI_CTL_425
+#define LPDDR4__TDFI_DRAM_CLK_DISABLE__FLD LPDDR4__DENALI_CTL_425__TDFI_DRAM_CLK_DISABLE
+
+#define LPDDR4__DENALI_CTL_426_READ_MASK 0x01FF070FU
+#define LPDDR4__DENALI_CTL_426_WRITE_MASK 0x01FF070FU
+#define LPDDR4__DENALI_CTL_426__TDFI_DRAM_CLK_ENABLE_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_426__TDFI_DRAM_CLK_ENABLE_SHIFT 0U
+#define LPDDR4__DENALI_CTL_426__TDFI_DRAM_CLK_ENABLE_WIDTH 4U
+#define LPDDR4__TDFI_DRAM_CLK_ENABLE__REG DENALI_CTL_426
+#define LPDDR4__TDFI_DRAM_CLK_ENABLE__FLD LPDDR4__DENALI_CTL_426__TDFI_DRAM_CLK_ENABLE
+
+#define LPDDR4__DENALI_CTL_426__TDFI_PARIN_LAT_MASK 0x00000700U
+#define LPDDR4__DENALI_CTL_426__TDFI_PARIN_LAT_SHIFT 8U
+#define LPDDR4__DENALI_CTL_426__TDFI_PARIN_LAT_WIDTH 3U
+#define LPDDR4__TDFI_PARIN_LAT__REG DENALI_CTL_426
+#define LPDDR4__TDFI_PARIN_LAT__FLD LPDDR4__DENALI_CTL_426__TDFI_PARIN_LAT
+
+#define LPDDR4__DENALI_CTL_426__TDFI_WRDATA_DELAY_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_426__TDFI_WRDATA_DELAY_SHIFT 16U
+#define LPDDR4__DENALI_CTL_426__TDFI_WRDATA_DELAY_WIDTH 8U
+#define LPDDR4__TDFI_WRDATA_DELAY__REG DENALI_CTL_426
+#define LPDDR4__TDFI_WRDATA_DELAY__FLD LPDDR4__DENALI_CTL_426__TDFI_WRDATA_DELAY
+
+#define LPDDR4__DENALI_CTL_426__DISABLE_MEMORY_MASKED_WRITE_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_426__DISABLE_MEMORY_MASKED_WRITE_SHIFT 24U
+#define LPDDR4__DENALI_CTL_426__DISABLE_MEMORY_MASKED_WRITE_WIDTH 1U
+#define LPDDR4__DENALI_CTL_426__DISABLE_MEMORY_MASKED_WRITE_WOCLR 0U
+#define LPDDR4__DENALI_CTL_426__DISABLE_MEMORY_MASKED_WRITE_WOSET 0U
+#define LPDDR4__DISABLE_MEMORY_MASKED_WRITE__REG DENALI_CTL_426
+#define LPDDR4__DISABLE_MEMORY_MASKED_WRITE__FLD LPDDR4__DENALI_CTL_426__DISABLE_MEMORY_MASKED_WRITE
+
+#define LPDDR4__DENALI_CTL_427_READ_MASK 0x07070701U
+#define LPDDR4__DENALI_CTL_427_WRITE_MASK 0x07070701U
+#define LPDDR4__DENALI_CTL_427__MULTI_CHANNEL_ZQ_CAL_MASTER_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_427__MULTI_CHANNEL_ZQ_CAL_MASTER_SHIFT 0U
+#define LPDDR4__DENALI_CTL_427__MULTI_CHANNEL_ZQ_CAL_MASTER_WIDTH 1U
+#define LPDDR4__DENALI_CTL_427__MULTI_CHANNEL_ZQ_CAL_MASTER_WOCLR 0U
+#define LPDDR4__DENALI_CTL_427__MULTI_CHANNEL_ZQ_CAL_MASTER_WOSET 0U
+#define LPDDR4__MULTI_CHANNEL_ZQ_CAL_MASTER__REG DENALI_CTL_427
+#define LPDDR4__MULTI_CHANNEL_ZQ_CAL_MASTER__FLD LPDDR4__DENALI_CTL_427__MULTI_CHANNEL_ZQ_CAL_MASTER
+
+#define LPDDR4__DENALI_CTL_427__STRATEGY_2TICK_COUNT_MASK 0x00000700U
+#define LPDDR4__DENALI_CTL_427__STRATEGY_2TICK_COUNT_SHIFT 8U
+#define LPDDR4__DENALI_CTL_427__STRATEGY_2TICK_COUNT_WIDTH 3U
+#define LPDDR4__STRATEGY_2TICK_COUNT__REG DENALI_CTL_427
+#define LPDDR4__STRATEGY_2TICK_COUNT__FLD LPDDR4__DENALI_CTL_427__STRATEGY_2TICK_COUNT
+
+#define LPDDR4__DENALI_CTL_427__BANK_ACTIVATE_2TICK_COUNT_MASK 0x00070000U
+#define LPDDR4__DENALI_CTL_427__BANK_ACTIVATE_2TICK_COUNT_SHIFT 16U
+#define LPDDR4__DENALI_CTL_427__BANK_ACTIVATE_2TICK_COUNT_WIDTH 3U
+#define LPDDR4__BANK_ACTIVATE_2TICK_COUNT__REG DENALI_CTL_427
+#define LPDDR4__BANK_ACTIVATE_2TICK_COUNT__FLD LPDDR4__DENALI_CTL_427__BANK_ACTIVATE_2TICK_COUNT
+
+#define LPDDR4__DENALI_CTL_427__PRE_2TICK_COUNT_MASK 0x07000000U
+#define LPDDR4__DENALI_CTL_427__PRE_2TICK_COUNT_SHIFT 24U
+#define LPDDR4__DENALI_CTL_427__PRE_2TICK_COUNT_WIDTH 3U
+#define LPDDR4__PRE_2TICK_COUNT__REG DENALI_CTL_427
+#define LPDDR4__PRE_2TICK_COUNT__FLD LPDDR4__DENALI_CTL_427__PRE_2TICK_COUNT
+
+#define LPDDR4__DENALI_CTL_428_READ_MASK 0x0F070707U
+#define LPDDR4__DENALI_CTL_428_WRITE_MASK 0x0F070707U
+#define LPDDR4__DENALI_CTL_428__STRATEGY_4TICK_COUNT_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_428__STRATEGY_4TICK_COUNT_SHIFT 0U
+#define LPDDR4__DENALI_CTL_428__STRATEGY_4TICK_COUNT_WIDTH 3U
+#define LPDDR4__STRATEGY_4TICK_COUNT__REG DENALI_CTL_428
+#define LPDDR4__STRATEGY_4TICK_COUNT__FLD LPDDR4__DENALI_CTL_428__STRATEGY_4TICK_COUNT
+
+#define LPDDR4__DENALI_CTL_428__BANK_ACTIVATE_4TICK_COUNT_MASK 0x00000700U
+#define LPDDR4__DENALI_CTL_428__BANK_ACTIVATE_4TICK_COUNT_SHIFT 8U
+#define LPDDR4__DENALI_CTL_428__BANK_ACTIVATE_4TICK_COUNT_WIDTH 3U
+#define LPDDR4__BANK_ACTIVATE_4TICK_COUNT__REG DENALI_CTL_428
+#define LPDDR4__BANK_ACTIVATE_4TICK_COUNT__FLD LPDDR4__DENALI_CTL_428__BANK_ACTIVATE_4TICK_COUNT
+
+#define LPDDR4__DENALI_CTL_428__PRE_4TICK_COUNT_MASK 0x00070000U
+#define LPDDR4__DENALI_CTL_428__PRE_4TICK_COUNT_SHIFT 16U
+#define LPDDR4__DENALI_CTL_428__PRE_4TICK_COUNT_WIDTH 3U
+#define LPDDR4__PRE_4TICK_COUNT__REG DENALI_CTL_428
+#define LPDDR4__PRE_4TICK_COUNT__FLD LPDDR4__DENALI_CTL_428__PRE_4TICK_COUNT
+
+#define LPDDR4__DENALI_CTL_428__TMP_2X4_TICK_PLUS_ADJ_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_428__TMP_2X4_TICK_PLUS_ADJ_SHIFT 24U
+#define LPDDR4__DENALI_CTL_428__TMP_2X4_TICK_PLUS_ADJ_WIDTH 4U
+#define LPDDR4__TMP_2X4_TICK_PLUS_ADJ__REG DENALI_CTL_428
+#define LPDDR4__TMP_2X4_TICK_PLUS_ADJ__FLD LPDDR4__DENALI_CTL_428__TMP_2X4_TICK_PLUS_ADJ
+
+#define LPDDR4__DENALI_CTL_429_READ_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_429_WRITE_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_429__TMP_2X4_TICK_MINUS_ADJ_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_429__TMP_2X4_TICK_MINUS_ADJ_SHIFT 0U
+#define LPDDR4__DENALI_CTL_429__TMP_2X4_TICK_MINUS_ADJ_WIDTH 4U
+#define LPDDR4__TMP_2X4_TICK_MINUS_ADJ__REG DENALI_CTL_429
+#define LPDDR4__TMP_2X4_TICK_MINUS_ADJ__FLD LPDDR4__DENALI_CTL_429__TMP_2X4_TICK_MINUS_ADJ
+
+#define LPDDR4__DENALI_CTL_429__TMP_NXN_TICK_PLUS_ADJ_MASK 0x00000F00U
+#define LPDDR4__DENALI_CTL_429__TMP_NXN_TICK_PLUS_ADJ_SHIFT 8U
+#define LPDDR4__DENALI_CTL_429__TMP_NXN_TICK_PLUS_ADJ_WIDTH 4U
+#define LPDDR4__TMP_NXN_TICK_PLUS_ADJ__REG DENALI_CTL_429
+#define LPDDR4__TMP_NXN_TICK_PLUS_ADJ__FLD LPDDR4__DENALI_CTL_429__TMP_NXN_TICK_PLUS_ADJ
+
+#define LPDDR4__DENALI_CTL_429__TMP_NXN_TICK_MINUS_ADJ_MASK 0x000F0000U
+#define LPDDR4__DENALI_CTL_429__TMP_NXN_TICK_MINUS_ADJ_SHIFT 16U
+#define LPDDR4__DENALI_CTL_429__TMP_NXN_TICK_MINUS_ADJ_WIDTH 4U
+#define LPDDR4__TMP_NXN_TICK_MINUS_ADJ__REG DENALI_CTL_429
+#define LPDDR4__TMP_NXN_TICK_MINUS_ADJ__FLD LPDDR4__DENALI_CTL_429__TMP_NXN_TICK_MINUS_ADJ
+
+#define LPDDR4__DENALI_CTL_429__ODT_TICK_PLUS_ADJ_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_429__ODT_TICK_PLUS_ADJ_SHIFT 24U
+#define LPDDR4__DENALI_CTL_429__ODT_TICK_PLUS_ADJ_WIDTH 4U
+#define LPDDR4__ODT_TICK_PLUS_ADJ__REG DENALI_CTL_429
+#define LPDDR4__ODT_TICK_PLUS_ADJ__FLD LPDDR4__DENALI_CTL_429__ODT_TICK_PLUS_ADJ
+
+#define LPDDR4__DENALI_CTL_430_READ_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_430_WRITE_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_430__ODT_TICK_MINUS_ADJ_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_430__ODT_TICK_MINUS_ADJ_SHIFT 0U
+#define LPDDR4__DENALI_CTL_430__ODT_TICK_MINUS_ADJ_WIDTH 4U
+#define LPDDR4__ODT_TICK_MINUS_ADJ__REG DENALI_CTL_430
+#define LPDDR4__ODT_TICK_MINUS_ADJ__FLD LPDDR4__DENALI_CTL_430__ODT_TICK_MINUS_ADJ
+
+#define LPDDR4__DENALI_CTL_430__TRAS_TICK_PLUS_ADJ_MASK 0x00000F00U
+#define LPDDR4__DENALI_CTL_430__TRAS_TICK_PLUS_ADJ_SHIFT 8U
+#define LPDDR4__DENALI_CTL_430__TRAS_TICK_PLUS_ADJ_WIDTH 4U
+#define LPDDR4__TRAS_TICK_PLUS_ADJ__REG DENALI_CTL_430
+#define LPDDR4__TRAS_TICK_PLUS_ADJ__FLD LPDDR4__DENALI_CTL_430__TRAS_TICK_PLUS_ADJ
+
+#define LPDDR4__DENALI_CTL_430__TRAS_TICK_MINUS_ADJ_MASK 0x000F0000U
+#define LPDDR4__DENALI_CTL_430__TRAS_TICK_MINUS_ADJ_SHIFT 16U
+#define LPDDR4__DENALI_CTL_430__TRAS_TICK_MINUS_ADJ_WIDTH 4U
+#define LPDDR4__TRAS_TICK_MINUS_ADJ__REG DENALI_CTL_430
+#define LPDDR4__TRAS_TICK_MINUS_ADJ__FLD LPDDR4__DENALI_CTL_430__TRAS_TICK_MINUS_ADJ
+
+#define LPDDR4__DENALI_CTL_430__TRP_TICK_PLUS_ADJ_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_430__TRP_TICK_PLUS_ADJ_SHIFT 24U
+#define LPDDR4__DENALI_CTL_430__TRP_TICK_PLUS_ADJ_WIDTH 4U
+#define LPDDR4__TRP_TICK_PLUS_ADJ__REG DENALI_CTL_430
+#define LPDDR4__TRP_TICK_PLUS_ADJ__FLD LPDDR4__DENALI_CTL_430__TRP_TICK_PLUS_ADJ
+
+#define LPDDR4__DENALI_CTL_431_READ_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_431_WRITE_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_431__TRP_TICK_MINUS_ADJ_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_431__TRP_TICK_MINUS_ADJ_SHIFT 0U
+#define LPDDR4__DENALI_CTL_431__TRP_TICK_MINUS_ADJ_WIDTH 4U
+#define LPDDR4__TRP_TICK_MINUS_ADJ__REG DENALI_CTL_431
+#define LPDDR4__TRP_TICK_MINUS_ADJ__FLD LPDDR4__DENALI_CTL_431__TRP_TICK_MINUS_ADJ
+
+#define LPDDR4__DENALI_CTL_431__TWR_TICK_PLUS_ADJ_MASK 0x00000F00U
+#define LPDDR4__DENALI_CTL_431__TWR_TICK_PLUS_ADJ_SHIFT 8U
+#define LPDDR4__DENALI_CTL_431__TWR_TICK_PLUS_ADJ_WIDTH 4U
+#define LPDDR4__TWR_TICK_PLUS_ADJ__REG DENALI_CTL_431
+#define LPDDR4__TWR_TICK_PLUS_ADJ__FLD LPDDR4__DENALI_CTL_431__TWR_TICK_PLUS_ADJ
+
+#define LPDDR4__DENALI_CTL_431__TWR_TICK_MINUS_ADJ_MASK 0x000F0000U
+#define LPDDR4__DENALI_CTL_431__TWR_TICK_MINUS_ADJ_SHIFT 16U
+#define LPDDR4__DENALI_CTL_431__TWR_TICK_MINUS_ADJ_WIDTH 4U
+#define LPDDR4__TWR_TICK_MINUS_ADJ__REG DENALI_CTL_431
+#define LPDDR4__TWR_TICK_MINUS_ADJ__FLD LPDDR4__DENALI_CTL_431__TWR_TICK_MINUS_ADJ
+
+#define LPDDR4__DENALI_CTL_431__TMP_4X2_TICK_PLUS_ADJ_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_431__TMP_4X2_TICK_PLUS_ADJ_SHIFT 24U
+#define LPDDR4__DENALI_CTL_431__TMP_4X2_TICK_PLUS_ADJ_WIDTH 4U
+#define LPDDR4__TMP_4X2_TICK_PLUS_ADJ__REG DENALI_CTL_431
+#define LPDDR4__TMP_4X2_TICK_PLUS_ADJ__FLD LPDDR4__DENALI_CTL_431__TMP_4X2_TICK_PLUS_ADJ
+
+#define LPDDR4__DENALI_CTL_432_READ_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_432_WRITE_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_432__TMP_4X2_TICK_MINUS_ADJ_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_432__TMP_4X2_TICK_MINUS_ADJ_SHIFT 0U
+#define LPDDR4__DENALI_CTL_432__TMP_4X2_TICK_MINUS_ADJ_WIDTH 4U
+#define LPDDR4__TMP_4X2_TICK_MINUS_ADJ__REG DENALI_CTL_432
+#define LPDDR4__TMP_4X2_TICK_MINUS_ADJ__FLD LPDDR4__DENALI_CTL_432__TMP_4X2_TICK_MINUS_ADJ
+
+#define LPDDR4__DENALI_CTL_432__TRFC_TICK_PLUS_ADJ_MASK 0x00000F00U
+#define LPDDR4__DENALI_CTL_432__TRFC_TICK_PLUS_ADJ_SHIFT 8U
+#define LPDDR4__DENALI_CTL_432__TRFC_TICK_PLUS_ADJ_WIDTH 4U
+#define LPDDR4__TRFC_TICK_PLUS_ADJ__REG DENALI_CTL_432
+#define LPDDR4__TRFC_TICK_PLUS_ADJ__FLD LPDDR4__DENALI_CTL_432__TRFC_TICK_PLUS_ADJ
+
+#define LPDDR4__DENALI_CTL_432__TRFC_TICK_MINUS_ADJ_MASK 0x000F0000U
+#define LPDDR4__DENALI_CTL_432__TRFC_TICK_MINUS_ADJ_SHIFT 16U
+#define LPDDR4__DENALI_CTL_432__TRFC_TICK_MINUS_ADJ_WIDTH 4U
+#define LPDDR4__TRFC_TICK_MINUS_ADJ__REG DENALI_CTL_432
+#define LPDDR4__TRFC_TICK_MINUS_ADJ__FLD LPDDR4__DENALI_CTL_432__TRFC_TICK_MINUS_ADJ
+
+#define LPDDR4__DENALI_CTL_432__RL_TICK_PLUS_ADJ_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_432__RL_TICK_PLUS_ADJ_SHIFT 24U
+#define LPDDR4__DENALI_CTL_432__RL_TICK_PLUS_ADJ_WIDTH 4U
+#define LPDDR4__RL_TICK_PLUS_ADJ__REG DENALI_CTL_432
+#define LPDDR4__RL_TICK_PLUS_ADJ__FLD LPDDR4__DENALI_CTL_432__RL_TICK_PLUS_ADJ
+
+#define LPDDR4__DENALI_CTL_433_READ_MASK 0xFF0F0F0FU
+#define LPDDR4__DENALI_CTL_433_WRITE_MASK 0xFF0F0F0FU
+#define LPDDR4__DENALI_CTL_433__RL_TICK_MINUS_ADJ_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_433__RL_TICK_MINUS_ADJ_SHIFT 0U
+#define LPDDR4__DENALI_CTL_433__RL_TICK_MINUS_ADJ_WIDTH 4U
+#define LPDDR4__RL_TICK_MINUS_ADJ__REG DENALI_CTL_433
+#define LPDDR4__RL_TICK_MINUS_ADJ__FLD LPDDR4__DENALI_CTL_433__RL_TICK_MINUS_ADJ
+
+#define LPDDR4__DENALI_CTL_433__WL_TICK_PLUS_ADJ_MASK 0x00000F00U
+#define LPDDR4__DENALI_CTL_433__WL_TICK_PLUS_ADJ_SHIFT 8U
+#define LPDDR4__DENALI_CTL_433__WL_TICK_PLUS_ADJ_WIDTH 4U
+#define LPDDR4__WL_TICK_PLUS_ADJ__REG DENALI_CTL_433
+#define LPDDR4__WL_TICK_PLUS_ADJ__FLD LPDDR4__DENALI_CTL_433__WL_TICK_PLUS_ADJ
+
+#define LPDDR4__DENALI_CTL_433__WL_TICK_MINUS_ADJ_MASK 0x000F0000U
+#define LPDDR4__DENALI_CTL_433__WL_TICK_MINUS_ADJ_SHIFT 16U
+#define LPDDR4__DENALI_CTL_433__WL_TICK_MINUS_ADJ_WIDTH 4U
+#define LPDDR4__WL_TICK_MINUS_ADJ__REG DENALI_CTL_433
+#define LPDDR4__WL_TICK_MINUS_ADJ__FLD LPDDR4__DENALI_CTL_433__WL_TICK_MINUS_ADJ
+
+#define LPDDR4__DENALI_CTL_433__NWR_F0_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_433__NWR_F0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_433__NWR_F0_WIDTH 8U
+#define LPDDR4__NWR_F0__REG DENALI_CTL_433
+#define LPDDR4__NWR_F0__FLD LPDDR4__DENALI_CTL_433__NWR_F0
+
+#define LPDDR4__DENALI_CTL_434_READ_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_434_WRITE_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_434__NWR_F1_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_434__NWR_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_434__NWR_F1_WIDTH 8U
+#define LPDDR4__NWR_F1__REG DENALI_CTL_434
+#define LPDDR4__NWR_F1__FLD LPDDR4__DENALI_CTL_434__NWR_F1
+
+#define LPDDR4__DENALI_CTL_434__NWR_F2_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_434__NWR_F2_SHIFT 8U
+#define LPDDR4__DENALI_CTL_434__NWR_F2_WIDTH 8U
+#define LPDDR4__NWR_F2__REG DENALI_CTL_434
+#define LPDDR4__NWR_F2__FLD LPDDR4__DENALI_CTL_434__NWR_F2
+
+#endif /* REG_LPDDR4_DDR_CONTROLLER_MACROS_H_ */
diff --git a/drivers/ram/k3-ddrss/am62a/lpddr4_phy_core_macros.h b/drivers/ram/k3-ddrss/am62a/lpddr4_phy_core_macros.h
new file mode 100644
index 00000000000..a5966d896d3
--- /dev/null
+++ b/drivers/ram/k3-ddrss/am62a/lpddr4_phy_core_macros.h
@@ -0,0 +1,1986 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef REG_LPDDR4_PHY_CORE_MACROS_H_
+#define REG_LPDDR4_PHY_CORE_MACROS_H_
+
+#define LPDDR4__DENALI_PHY_1792_READ_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_1792_WRITE_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_1792__PHY_FREQ_SEL_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_1792__PHY_FREQ_SEL_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1792__PHY_FREQ_SEL_WIDTH 2U
+#define LPDDR4__PHY_FREQ_SEL__REG DENALI_PHY_1792
+#define LPDDR4__PHY_FREQ_SEL__FLD LPDDR4__DENALI_PHY_1792__PHY_FREQ_SEL
+
+#define LPDDR4__DENALI_PHY_1793_READ_MASK 0x1F030101U
+#define LPDDR4__DENALI_PHY_1793_WRITE_MASK 0x1F030101U
+#define LPDDR4__DENALI_PHY_1793__PHY_FREQ_SEL_FROM_REGIF_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1793__PHY_FREQ_SEL_FROM_REGIF_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1793__PHY_FREQ_SEL_FROM_REGIF_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1793__PHY_FREQ_SEL_FROM_REGIF_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1793__PHY_FREQ_SEL_FROM_REGIF_WOSET 0U
+#define LPDDR4__PHY_FREQ_SEL_FROM_REGIF__REG DENALI_PHY_1793
+#define LPDDR4__PHY_FREQ_SEL_FROM_REGIF__FLD LPDDR4__DENALI_PHY_1793__PHY_FREQ_SEL_FROM_REGIF
+
+#define LPDDR4__DENALI_PHY_1793__PHY_FREQ_SEL_MULTICAST_EN_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_1793__PHY_FREQ_SEL_MULTICAST_EN_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1793__PHY_FREQ_SEL_MULTICAST_EN_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1793__PHY_FREQ_SEL_MULTICAST_EN_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1793__PHY_FREQ_SEL_MULTICAST_EN_WOSET 0U
+#define LPDDR4__PHY_FREQ_SEL_MULTICAST_EN__REG DENALI_PHY_1793
+#define LPDDR4__PHY_FREQ_SEL_MULTICAST_EN__FLD LPDDR4__DENALI_PHY_1793__PHY_FREQ_SEL_MULTICAST_EN
+
+#define LPDDR4__DENALI_PHY_1793__PHY_FREQ_SEL_INDEX_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_1793__PHY_FREQ_SEL_INDEX_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1793__PHY_FREQ_SEL_INDEX_WIDTH 2U
+#define LPDDR4__PHY_FREQ_SEL_INDEX__REG DENALI_PHY_1793
+#define LPDDR4__PHY_FREQ_SEL_INDEX__FLD LPDDR4__DENALI_PHY_1793__PHY_FREQ_SEL_INDEX
+
+#define LPDDR4__DENALI_PHY_1793__PHY_SW_GRP0_SHIFT_0_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_1793__PHY_SW_GRP0_SHIFT_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1793__PHY_SW_GRP0_SHIFT_0_WIDTH 5U
+#define LPDDR4__PHY_SW_GRP0_SHIFT_0__REG DENALI_PHY_1793
+#define LPDDR4__PHY_SW_GRP0_SHIFT_0__FLD LPDDR4__DENALI_PHY_1793__PHY_SW_GRP0_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_1794_READ_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_1794_WRITE_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_1794__PHY_SW_GRP1_SHIFT_0_MASK 0x0000001FU
+#define LPDDR4__DENALI_PHY_1794__PHY_SW_GRP1_SHIFT_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1794__PHY_SW_GRP1_SHIFT_0_WIDTH 5U
+#define LPDDR4__PHY_SW_GRP1_SHIFT_0__REG DENALI_PHY_1794
+#define LPDDR4__PHY_SW_GRP1_SHIFT_0__FLD LPDDR4__DENALI_PHY_1794__PHY_SW_GRP1_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_1794__PHY_SW_GRP2_SHIFT_0_MASK 0x00001F00U
+#define LPDDR4__DENALI_PHY_1794__PHY_SW_GRP2_SHIFT_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1794__PHY_SW_GRP2_SHIFT_0_WIDTH 5U
+#define LPDDR4__PHY_SW_GRP2_SHIFT_0__REG DENALI_PHY_1794
+#define LPDDR4__PHY_SW_GRP2_SHIFT_0__FLD LPDDR4__DENALI_PHY_1794__PHY_SW_GRP2_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_1794__PHY_SW_GRP3_SHIFT_0_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_1794__PHY_SW_GRP3_SHIFT_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1794__PHY_SW_GRP3_SHIFT_0_WIDTH 5U
+#define LPDDR4__PHY_SW_GRP3_SHIFT_0__REG DENALI_PHY_1794
+#define LPDDR4__PHY_SW_GRP3_SHIFT_0__FLD LPDDR4__DENALI_PHY_1794__PHY_SW_GRP3_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_1794__PHY_SW_GRP0_SHIFT_1_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_1794__PHY_SW_GRP0_SHIFT_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1794__PHY_SW_GRP0_SHIFT_1_WIDTH 5U
+#define LPDDR4__PHY_SW_GRP0_SHIFT_1__REG DENALI_PHY_1794
+#define LPDDR4__PHY_SW_GRP0_SHIFT_1__FLD LPDDR4__DENALI_PHY_1794__PHY_SW_GRP0_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_1795_READ_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_1795_WRITE_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_1795__PHY_SW_GRP1_SHIFT_1_MASK 0x0000001FU
+#define LPDDR4__DENALI_PHY_1795__PHY_SW_GRP1_SHIFT_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1795__PHY_SW_GRP1_SHIFT_1_WIDTH 5U
+#define LPDDR4__PHY_SW_GRP1_SHIFT_1__REG DENALI_PHY_1795
+#define LPDDR4__PHY_SW_GRP1_SHIFT_1__FLD LPDDR4__DENALI_PHY_1795__PHY_SW_GRP1_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_1795__PHY_SW_GRP2_SHIFT_1_MASK 0x00001F00U
+#define LPDDR4__DENALI_PHY_1795__PHY_SW_GRP2_SHIFT_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1795__PHY_SW_GRP2_SHIFT_1_WIDTH 5U
+#define LPDDR4__PHY_SW_GRP2_SHIFT_1__REG DENALI_PHY_1795
+#define LPDDR4__PHY_SW_GRP2_SHIFT_1__FLD LPDDR4__DENALI_PHY_1795__PHY_SW_GRP2_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_1795__PHY_SW_GRP3_SHIFT_1_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_1795__PHY_SW_GRP3_SHIFT_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1795__PHY_SW_GRP3_SHIFT_1_WIDTH 5U
+#define LPDDR4__PHY_SW_GRP3_SHIFT_1__REG DENALI_PHY_1795
+#define LPDDR4__PHY_SW_GRP3_SHIFT_1__FLD LPDDR4__DENALI_PHY_1795__PHY_SW_GRP3_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_1795__PHY_SW_GRP0_SHIFT_2_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_1795__PHY_SW_GRP0_SHIFT_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1795__PHY_SW_GRP0_SHIFT_2_WIDTH 5U
+#define LPDDR4__PHY_SW_GRP0_SHIFT_2__REG DENALI_PHY_1795
+#define LPDDR4__PHY_SW_GRP0_SHIFT_2__FLD LPDDR4__DENALI_PHY_1795__PHY_SW_GRP0_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_1796_READ_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_1796_WRITE_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_1796__PHY_SW_GRP1_SHIFT_2_MASK 0x0000001FU
+#define LPDDR4__DENALI_PHY_1796__PHY_SW_GRP1_SHIFT_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1796__PHY_SW_GRP1_SHIFT_2_WIDTH 5U
+#define LPDDR4__PHY_SW_GRP1_SHIFT_2__REG DENALI_PHY_1796
+#define LPDDR4__PHY_SW_GRP1_SHIFT_2__FLD LPDDR4__DENALI_PHY_1796__PHY_SW_GRP1_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_1796__PHY_SW_GRP2_SHIFT_2_MASK 0x00001F00U
+#define LPDDR4__DENALI_PHY_1796__PHY_SW_GRP2_SHIFT_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1796__PHY_SW_GRP2_SHIFT_2_WIDTH 5U
+#define LPDDR4__PHY_SW_GRP2_SHIFT_2__REG DENALI_PHY_1796
+#define LPDDR4__PHY_SW_GRP2_SHIFT_2__FLD LPDDR4__DENALI_PHY_1796__PHY_SW_GRP2_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_1796__PHY_SW_GRP3_SHIFT_2_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_1796__PHY_SW_GRP3_SHIFT_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1796__PHY_SW_GRP3_SHIFT_2_WIDTH 5U
+#define LPDDR4__PHY_SW_GRP3_SHIFT_2__REG DENALI_PHY_1796
+#define LPDDR4__PHY_SW_GRP3_SHIFT_2__FLD LPDDR4__DENALI_PHY_1796__PHY_SW_GRP3_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_1796__PHY_SW_GRP0_SHIFT_3_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_1796__PHY_SW_GRP0_SHIFT_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1796__PHY_SW_GRP0_SHIFT_3_WIDTH 5U
+#define LPDDR4__PHY_SW_GRP0_SHIFT_3__REG DENALI_PHY_1796
+#define LPDDR4__PHY_SW_GRP0_SHIFT_3__FLD LPDDR4__DENALI_PHY_1796__PHY_SW_GRP0_SHIFT_3
+
+#define LPDDR4__DENALI_PHY_1797_READ_MASK 0x001F1F1FU
+#define LPDDR4__DENALI_PHY_1797_WRITE_MASK 0x001F1F1FU
+#define LPDDR4__DENALI_PHY_1797__PHY_SW_GRP1_SHIFT_3_MASK 0x0000001FU
+#define LPDDR4__DENALI_PHY_1797__PHY_SW_GRP1_SHIFT_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1797__PHY_SW_GRP1_SHIFT_3_WIDTH 5U
+#define LPDDR4__PHY_SW_GRP1_SHIFT_3__REG DENALI_PHY_1797
+#define LPDDR4__PHY_SW_GRP1_SHIFT_3__FLD LPDDR4__DENALI_PHY_1797__PHY_SW_GRP1_SHIFT_3
+
+#define LPDDR4__DENALI_PHY_1797__PHY_SW_GRP2_SHIFT_3_MASK 0x00001F00U
+#define LPDDR4__DENALI_PHY_1797__PHY_SW_GRP2_SHIFT_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1797__PHY_SW_GRP2_SHIFT_3_WIDTH 5U
+#define LPDDR4__PHY_SW_GRP2_SHIFT_3__REG DENALI_PHY_1797
+#define LPDDR4__PHY_SW_GRP2_SHIFT_3__FLD LPDDR4__DENALI_PHY_1797__PHY_SW_GRP2_SHIFT_3
+
+#define LPDDR4__DENALI_PHY_1797__PHY_SW_GRP3_SHIFT_3_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_1797__PHY_SW_GRP3_SHIFT_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1797__PHY_SW_GRP3_SHIFT_3_WIDTH 5U
+#define LPDDR4__PHY_SW_GRP3_SHIFT_3__REG DENALI_PHY_1797
+#define LPDDR4__PHY_SW_GRP3_SHIFT_3__FLD LPDDR4__DENALI_PHY_1797__PHY_SW_GRP3_SHIFT_3
+
+#define LPDDR4__DENALI_PHY_1798_READ_MASK 0x011F07FFU
+#define LPDDR4__DENALI_PHY_1798_WRITE_MASK 0x011F07FFU
+#define LPDDR4__DENALI_PHY_1798__PHY_GRP_BYPASS_SLAVE_DELAY_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1798__PHY_GRP_BYPASS_SLAVE_DELAY_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1798__PHY_GRP_BYPASS_SLAVE_DELAY_WIDTH 11U
+#define LPDDR4__PHY_GRP_BYPASS_SLAVE_DELAY__REG DENALI_PHY_1798
+#define LPDDR4__PHY_GRP_BYPASS_SLAVE_DELAY__FLD LPDDR4__DENALI_PHY_1798__PHY_GRP_BYPASS_SLAVE_DELAY
+
+#define LPDDR4__DENALI_PHY_1798__PHY_SW_GRP_BYPASS_SHIFT_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_1798__PHY_SW_GRP_BYPASS_SHIFT_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1798__PHY_SW_GRP_BYPASS_SHIFT_WIDTH 5U
+#define LPDDR4__PHY_SW_GRP_BYPASS_SHIFT__REG DENALI_PHY_1798
+#define LPDDR4__PHY_SW_GRP_BYPASS_SHIFT__FLD LPDDR4__DENALI_PHY_1798__PHY_SW_GRP_BYPASS_SHIFT
+
+#define LPDDR4__DENALI_PHY_1798__PHY_GRP_BYPASS_OVERRIDE_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_1798__PHY_GRP_BYPASS_OVERRIDE_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1798__PHY_GRP_BYPASS_OVERRIDE_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1798__PHY_GRP_BYPASS_OVERRIDE_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1798__PHY_GRP_BYPASS_OVERRIDE_WOSET 0U
+#define LPDDR4__PHY_GRP_BYPASS_OVERRIDE__REG DENALI_PHY_1798
+#define LPDDR4__PHY_GRP_BYPASS_OVERRIDE__FLD LPDDR4__DENALI_PHY_1798__PHY_GRP_BYPASS_OVERRIDE
+
+#define LPDDR4__DENALI_PHY_1799_READ_MASK 0x07FF0100U
+#define LPDDR4__DENALI_PHY_1799_WRITE_MASK 0x07FF0100U
+#define LPDDR4__DENALI_PHY_1799__SC_PHY_MANUAL_UPDATE_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1799__SC_PHY_MANUAL_UPDATE_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1799__SC_PHY_MANUAL_UPDATE_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1799__SC_PHY_MANUAL_UPDATE_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1799__SC_PHY_MANUAL_UPDATE_WOSET 0U
+#define LPDDR4__SC_PHY_MANUAL_UPDATE__REG DENALI_PHY_1799
+#define LPDDR4__SC_PHY_MANUAL_UPDATE__FLD LPDDR4__DENALI_PHY_1799__SC_PHY_MANUAL_UPDATE
+
+#define LPDDR4__DENALI_PHY_1799__PHY_MANUAL_UPDATE_PHYUPD_ENABLE_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_1799__PHY_MANUAL_UPDATE_PHYUPD_ENABLE_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1799__PHY_MANUAL_UPDATE_PHYUPD_ENABLE_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1799__PHY_MANUAL_UPDATE_PHYUPD_ENABLE_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1799__PHY_MANUAL_UPDATE_PHYUPD_ENABLE_WOSET 0U
+#define LPDDR4__PHY_MANUAL_UPDATE_PHYUPD_ENABLE__REG DENALI_PHY_1799
+#define LPDDR4__PHY_MANUAL_UPDATE_PHYUPD_ENABLE__FLD LPDDR4__DENALI_PHY_1799__PHY_MANUAL_UPDATE_PHYUPD_ENABLE
+
+#define LPDDR4__DENALI_PHY_1799__PHY_CSLVL_START_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_1799__PHY_CSLVL_START_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1799__PHY_CSLVL_START_WIDTH 11U
+#define LPDDR4__PHY_CSLVL_START__REG DENALI_PHY_1799
+#define LPDDR4__PHY_CSLVL_START__FLD LPDDR4__DENALI_PHY_1799__PHY_CSLVL_START
+
+#define LPDDR4__DENALI_PHY_1800_READ_MASK 0x000107FFU
+#define LPDDR4__DENALI_PHY_1800_WRITE_MASK 0x000107FFU
+#define LPDDR4__DENALI_PHY_1800__PHY_CSLVL_COARSE_DLY_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1800__PHY_CSLVL_COARSE_DLY_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1800__PHY_CSLVL_COARSE_DLY_WIDTH 11U
+#define LPDDR4__PHY_CSLVL_COARSE_DLY__REG DENALI_PHY_1800
+#define LPDDR4__PHY_CSLVL_COARSE_DLY__FLD LPDDR4__DENALI_PHY_1800__PHY_CSLVL_COARSE_DLY
+
+#define LPDDR4__DENALI_PHY_1800__PHY_CSLVL_DEBUG_MODE_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_1800__PHY_CSLVL_DEBUG_MODE_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1800__PHY_CSLVL_DEBUG_MODE_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1800__PHY_CSLVL_DEBUG_MODE_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1800__PHY_CSLVL_DEBUG_MODE_WOSET 0U
+#define LPDDR4__PHY_CSLVL_DEBUG_MODE__REG DENALI_PHY_1800
+#define LPDDR4__PHY_CSLVL_DEBUG_MODE__FLD LPDDR4__DENALI_PHY_1800__PHY_CSLVL_DEBUG_MODE
+
+#define LPDDR4__DENALI_PHY_1800__SC_PHY_CSLVL_DEBUG_CONT_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_1800__SC_PHY_CSLVL_DEBUG_CONT_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1800__SC_PHY_CSLVL_DEBUG_CONT_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1800__SC_PHY_CSLVL_DEBUG_CONT_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1800__SC_PHY_CSLVL_DEBUG_CONT_WOSET 0U
+#define LPDDR4__SC_PHY_CSLVL_DEBUG_CONT__REG DENALI_PHY_1800
+#define LPDDR4__SC_PHY_CSLVL_DEBUG_CONT__FLD LPDDR4__DENALI_PHY_1800__SC_PHY_CSLVL_DEBUG_CONT
+
+#define LPDDR4__DENALI_PHY_1801__SC_PHY_CSLVL_ERROR_CLR_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1801__SC_PHY_CSLVL_ERROR_CLR_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1801__SC_PHY_CSLVL_ERROR_CLR_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1801__SC_PHY_CSLVL_ERROR_CLR_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1801__SC_PHY_CSLVL_ERROR_CLR_WOSET 0U
+#define LPDDR4__SC_PHY_CSLVL_ERROR_CLR__REG DENALI_PHY_1801
+#define LPDDR4__SC_PHY_CSLVL_ERROR_CLR__FLD LPDDR4__DENALI_PHY_1801__SC_PHY_CSLVL_ERROR_CLR
+
+#define LPDDR4__DENALI_PHY_1802_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1802_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1802__PHY_CSLVL_OBS0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1802__PHY_CSLVL_OBS0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1802__PHY_CSLVL_OBS0_WIDTH 32U
+#define LPDDR4__PHY_CSLVL_OBS0__REG DENALI_PHY_1802
+#define LPDDR4__PHY_CSLVL_OBS0__FLD LPDDR4__DENALI_PHY_1802__PHY_CSLVL_OBS0
+
+#define LPDDR4__DENALI_PHY_1803_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1803_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1803__PHY_CSLVL_OBS1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1803__PHY_CSLVL_OBS1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1803__PHY_CSLVL_OBS1_WIDTH 32U
+#define LPDDR4__PHY_CSLVL_OBS1__REG DENALI_PHY_1803
+#define LPDDR4__PHY_CSLVL_OBS1__FLD LPDDR4__DENALI_PHY_1803__PHY_CSLVL_OBS1
+
+#define LPDDR4__DENALI_PHY_1804_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1804_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1804__PHY_CSLVL_OBS2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1804__PHY_CSLVL_OBS2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1804__PHY_CSLVL_OBS2_WIDTH 32U
+#define LPDDR4__PHY_CSLVL_OBS2__REG DENALI_PHY_1804
+#define LPDDR4__PHY_CSLVL_OBS2__FLD LPDDR4__DENALI_PHY_1804__PHY_CSLVL_OBS2
+
+#define LPDDR4__DENALI_PHY_1805_READ_MASK 0x0101FF01U
+#define LPDDR4__DENALI_PHY_1805_WRITE_MASK 0x0101FF01U
+#define LPDDR4__DENALI_PHY_1805__PHY_CSLVL_ENABLE_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1805__PHY_CSLVL_ENABLE_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1805__PHY_CSLVL_ENABLE_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1805__PHY_CSLVL_ENABLE_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1805__PHY_CSLVL_ENABLE_WOSET 0U
+#define LPDDR4__PHY_CSLVL_ENABLE__REG DENALI_PHY_1805
+#define LPDDR4__PHY_CSLVL_ENABLE__FLD LPDDR4__DENALI_PHY_1805__PHY_CSLVL_ENABLE
+
+#define LPDDR4__DENALI_PHY_1805__PHY_CSLVL_PERIODIC_START_OFFSET_MASK 0x0001FF00U
+#define LPDDR4__DENALI_PHY_1805__PHY_CSLVL_PERIODIC_START_OFFSET_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1805__PHY_CSLVL_PERIODIC_START_OFFSET_WIDTH 9U
+#define LPDDR4__PHY_CSLVL_PERIODIC_START_OFFSET__REG DENALI_PHY_1805
+#define LPDDR4__PHY_CSLVL_PERIODIC_START_OFFSET__FLD LPDDR4__DENALI_PHY_1805__PHY_CSLVL_PERIODIC_START_OFFSET
+
+#define LPDDR4__DENALI_PHY_1805__PHY_LP4_BOOT_DISABLE_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_1805__PHY_LP4_BOOT_DISABLE_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1805__PHY_LP4_BOOT_DISABLE_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1805__PHY_LP4_BOOT_DISABLE_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1805__PHY_LP4_BOOT_DISABLE_WOSET 0U
+#define LPDDR4__PHY_LP4_BOOT_DISABLE__REG DENALI_PHY_1805
+#define LPDDR4__PHY_LP4_BOOT_DISABLE__FLD LPDDR4__DENALI_PHY_1805__PHY_LP4_BOOT_DISABLE
+
+#define LPDDR4__DENALI_PHY_1806_READ_MASK 0x0007FF0FU
+#define LPDDR4__DENALI_PHY_1806_WRITE_MASK 0x0007FF0FU
+#define LPDDR4__DENALI_PHY_1806__PHY_CSLVL_CS_MAP_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_1806__PHY_CSLVL_CS_MAP_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1806__PHY_CSLVL_CS_MAP_WIDTH 4U
+#define LPDDR4__PHY_CSLVL_CS_MAP__REG DENALI_PHY_1806
+#define LPDDR4__PHY_CSLVL_CS_MAP__FLD LPDDR4__DENALI_PHY_1806__PHY_CSLVL_CS_MAP
+
+#define LPDDR4__DENALI_PHY_1806__PHY_CSLVL_QTR_MASK 0x0007FF00U
+#define LPDDR4__DENALI_PHY_1806__PHY_CSLVL_QTR_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1806__PHY_CSLVL_QTR_WIDTH 11U
+#define LPDDR4__PHY_CSLVL_QTR__REG DENALI_PHY_1806
+#define LPDDR4__PHY_CSLVL_QTR__FLD LPDDR4__DENALI_PHY_1806__PHY_CSLVL_QTR
+
+#define LPDDR4__DENALI_PHY_1807_READ_MASK 0xFF0F07FFU
+#define LPDDR4__DENALI_PHY_1807_WRITE_MASK 0xFF0F07FFU
+#define LPDDR4__DENALI_PHY_1807__PHY_CSLVL_COARSE_CHK_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1807__PHY_CSLVL_COARSE_CHK_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1807__PHY_CSLVL_COARSE_CHK_WIDTH 11U
+#define LPDDR4__PHY_CSLVL_COARSE_CHK__REG DENALI_PHY_1807
+#define LPDDR4__PHY_CSLVL_COARSE_CHK__FLD LPDDR4__DENALI_PHY_1807__PHY_CSLVL_COARSE_CHK
+
+#define LPDDR4__DENALI_PHY_1807__PHY_CSLVL_COARSE_CAPTURE_CNT_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_1807__PHY_CSLVL_COARSE_CAPTURE_CNT_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1807__PHY_CSLVL_COARSE_CAPTURE_CNT_WIDTH 4U
+#define LPDDR4__PHY_CSLVL_COARSE_CAPTURE_CNT__REG DENALI_PHY_1807
+#define LPDDR4__PHY_CSLVL_COARSE_CAPTURE_CNT__FLD LPDDR4__DENALI_PHY_1807__PHY_CSLVL_COARSE_CAPTURE_CNT
+
+#define LPDDR4__DENALI_PHY_1807__PHY_CALVL_CS_MAP_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_1807__PHY_CALVL_CS_MAP_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1807__PHY_CALVL_CS_MAP_WIDTH 8U
+#define LPDDR4__PHY_CALVL_CS_MAP__REG DENALI_PHY_1807
+#define LPDDR4__PHY_CALVL_CS_MAP__FLD LPDDR4__DENALI_PHY_1807__PHY_CALVL_CS_MAP
+
+#define LPDDR4__DENALI_PHY_1808_READ_MASK 0x01030007U
+#define LPDDR4__DENALI_PHY_1808_WRITE_MASK 0x01030007U
+#define LPDDR4__DENALI_PHY_1808__PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE_MASK 0x00000007U
+#define LPDDR4__DENALI_PHY_1808__PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1808__PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE_WIDTH 3U
+#define LPDDR4__PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE__REG DENALI_PHY_1808
+#define LPDDR4__PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE__FLD LPDDR4__DENALI_PHY_1808__PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE
+
+#define LPDDR4__DENALI_PHY_1808__PHY_ADRCTL_SNAP_OBS_REGS_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_1808__PHY_ADRCTL_SNAP_OBS_REGS_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1808__PHY_ADRCTL_SNAP_OBS_REGS_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1808__PHY_ADRCTL_SNAP_OBS_REGS_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1808__PHY_ADRCTL_SNAP_OBS_REGS_WOSET 0U
+#define LPDDR4__PHY_ADRCTL_SNAP_OBS_REGS__REG DENALI_PHY_1808
+#define LPDDR4__PHY_ADRCTL_SNAP_OBS_REGS__FLD LPDDR4__DENALI_PHY_1808__PHY_ADRCTL_SNAP_OBS_REGS
+
+#define LPDDR4__DENALI_PHY_1808__PHY_DFI_PHYUPD_TYPE_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_1808__PHY_DFI_PHYUPD_TYPE_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1808__PHY_DFI_PHYUPD_TYPE_WIDTH 2U
+#define LPDDR4__PHY_DFI_PHYUPD_TYPE__REG DENALI_PHY_1808
+#define LPDDR4__PHY_DFI_PHYUPD_TYPE__FLD LPDDR4__DENALI_PHY_1808__PHY_DFI_PHYUPD_TYPE
+
+#define LPDDR4__DENALI_PHY_1808__PHY_ADRCTL_LPDDR_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_1808__PHY_ADRCTL_LPDDR_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1808__PHY_ADRCTL_LPDDR_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1808__PHY_ADRCTL_LPDDR_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1808__PHY_ADRCTL_LPDDR_WOSET 0U
+#define LPDDR4__PHY_ADRCTL_LPDDR__REG DENALI_PHY_1808
+#define LPDDR4__PHY_ADRCTL_LPDDR__FLD LPDDR4__DENALI_PHY_1808__PHY_ADRCTL_LPDDR
+
+#define LPDDR4__DENALI_PHY_1809_READ_MASK 0xFFFF0101U
+#define LPDDR4__DENALI_PHY_1809_WRITE_MASK 0xFFFF0101U
+#define LPDDR4__DENALI_PHY_1809__PHY_LP4_ACTIVE_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1809__PHY_LP4_ACTIVE_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1809__PHY_LP4_ACTIVE_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1809__PHY_LP4_ACTIVE_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1809__PHY_LP4_ACTIVE_WOSET 0U
+#define LPDDR4__PHY_LP4_ACTIVE__REG DENALI_PHY_1809
+#define LPDDR4__PHY_LP4_ACTIVE__FLD LPDDR4__DENALI_PHY_1809__PHY_LP4_ACTIVE
+
+#define LPDDR4__DENALI_PHY_1809__PHY_LPDDR3_CS_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_1809__PHY_LPDDR3_CS_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1809__PHY_LPDDR3_CS_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1809__PHY_LPDDR3_CS_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1809__PHY_LPDDR3_CS_WOSET 0U
+#define LPDDR4__PHY_LPDDR3_CS__REG DENALI_PHY_1809
+#define LPDDR4__PHY_LPDDR3_CS__FLD LPDDR4__DENALI_PHY_1809__PHY_LPDDR3_CS
+
+#define LPDDR4__DENALI_PHY_1809__PHY_CLK_DC_CAL_SAMPLE_WAIT_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_1809__PHY_CLK_DC_CAL_SAMPLE_WAIT_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1809__PHY_CLK_DC_CAL_SAMPLE_WAIT_WIDTH 8U
+#define LPDDR4__PHY_CLK_DC_CAL_SAMPLE_WAIT__REG DENALI_PHY_1809
+#define LPDDR4__PHY_CLK_DC_CAL_SAMPLE_WAIT__FLD LPDDR4__DENALI_PHY_1809__PHY_CLK_DC_CAL_SAMPLE_WAIT
+
+#define LPDDR4__DENALI_PHY_1809__PHY_CLK_DC_CAL_TIMEOUT_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_1809__PHY_CLK_DC_CAL_TIMEOUT_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1809__PHY_CLK_DC_CAL_TIMEOUT_WIDTH 8U
+#define LPDDR4__PHY_CLK_DC_CAL_TIMEOUT__REG DENALI_PHY_1809
+#define LPDDR4__PHY_CLK_DC_CAL_TIMEOUT__FLD LPDDR4__DENALI_PHY_1809__PHY_CLK_DC_CAL_TIMEOUT
+
+#define LPDDR4__DENALI_PHY_1810_READ_MASK 0xFF3F0103U
+#define LPDDR4__DENALI_PHY_1810_WRITE_MASK 0xFF3F0103U
+#define LPDDR4__DENALI_PHY_1810__PHY_CLK_DC_WEIGHT_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_1810__PHY_CLK_DC_WEIGHT_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1810__PHY_CLK_DC_WEIGHT_WIDTH 2U
+#define LPDDR4__PHY_CLK_DC_WEIGHT__REG DENALI_PHY_1810
+#define LPDDR4__PHY_CLK_DC_WEIGHT__FLD LPDDR4__DENALI_PHY_1810__PHY_CLK_DC_WEIGHT
+
+#define LPDDR4__DENALI_PHY_1810__PHY_CLK_DC_FREQ_CHG_ADJ_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_1810__PHY_CLK_DC_FREQ_CHG_ADJ_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1810__PHY_CLK_DC_FREQ_CHG_ADJ_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1810__PHY_CLK_DC_FREQ_CHG_ADJ_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1810__PHY_CLK_DC_FREQ_CHG_ADJ_WOSET 0U
+#define LPDDR4__PHY_CLK_DC_FREQ_CHG_ADJ__REG DENALI_PHY_1810
+#define LPDDR4__PHY_CLK_DC_FREQ_CHG_ADJ__FLD LPDDR4__DENALI_PHY_1810__PHY_CLK_DC_FREQ_CHG_ADJ
+
+#define LPDDR4__DENALI_PHY_1810__PHY_CLK_DC_ADJUST_START_MASK 0x003F0000U
+#define LPDDR4__DENALI_PHY_1810__PHY_CLK_DC_ADJUST_START_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1810__PHY_CLK_DC_ADJUST_START_WIDTH 6U
+#define LPDDR4__PHY_CLK_DC_ADJUST_START__REG DENALI_PHY_1810
+#define LPDDR4__PHY_CLK_DC_ADJUST_START__FLD LPDDR4__DENALI_PHY_1810__PHY_CLK_DC_ADJUST_START
+
+#define LPDDR4__DENALI_PHY_1810__PHY_CLK_DC_ADJUST_SAMPLE_CNT_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_1810__PHY_CLK_DC_ADJUST_SAMPLE_CNT_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1810__PHY_CLK_DC_ADJUST_SAMPLE_CNT_WIDTH 8U
+#define LPDDR4__PHY_CLK_DC_ADJUST_SAMPLE_CNT__REG DENALI_PHY_1810
+#define LPDDR4__PHY_CLK_DC_ADJUST_SAMPLE_CNT__FLD LPDDR4__DENALI_PHY_1810__PHY_CLK_DC_ADJUST_SAMPLE_CNT
+
+#define LPDDR4__DENALI_PHY_1811_READ_MASK 0x010101FFU
+#define LPDDR4__DENALI_PHY_1811_WRITE_MASK 0x010101FFU
+#define LPDDR4__DENALI_PHY_1811__PHY_CLK_DC_ADJUST_THRSHLD_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_1811__PHY_CLK_DC_ADJUST_THRSHLD_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1811__PHY_CLK_DC_ADJUST_THRSHLD_WIDTH 8U
+#define LPDDR4__PHY_CLK_DC_ADJUST_THRSHLD__REG DENALI_PHY_1811
+#define LPDDR4__PHY_CLK_DC_ADJUST_THRSHLD__FLD LPDDR4__DENALI_PHY_1811__PHY_CLK_DC_ADJUST_THRSHLD
+
+#define LPDDR4__DENALI_PHY_1811__PHY_CLK_DC_ADJUST_DIRECT_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_1811__PHY_CLK_DC_ADJUST_DIRECT_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1811__PHY_CLK_DC_ADJUST_DIRECT_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1811__PHY_CLK_DC_ADJUST_DIRECT_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1811__PHY_CLK_DC_ADJUST_DIRECT_WOSET 0U
+#define LPDDR4__PHY_CLK_DC_ADJUST_DIRECT__REG DENALI_PHY_1811
+#define LPDDR4__PHY_CLK_DC_ADJUST_DIRECT__FLD LPDDR4__DENALI_PHY_1811__PHY_CLK_DC_ADJUST_DIRECT
+
+#define LPDDR4__DENALI_PHY_1811__PHY_CLK_DC_CAL_POLARITY_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_1811__PHY_CLK_DC_CAL_POLARITY_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1811__PHY_CLK_DC_CAL_POLARITY_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1811__PHY_CLK_DC_CAL_POLARITY_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1811__PHY_CLK_DC_CAL_POLARITY_WOSET 0U
+#define LPDDR4__PHY_CLK_DC_CAL_POLARITY__REG DENALI_PHY_1811
+#define LPDDR4__PHY_CLK_DC_CAL_POLARITY__FLD LPDDR4__DENALI_PHY_1811__PHY_CLK_DC_CAL_POLARITY
+
+#define LPDDR4__DENALI_PHY_1811__PHY_CLK_DC_CAL_START_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_1811__PHY_CLK_DC_CAL_START_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1811__PHY_CLK_DC_CAL_START_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1811__PHY_CLK_DC_CAL_START_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1811__PHY_CLK_DC_CAL_START_WOSET 0U
+#define LPDDR4__PHY_CLK_DC_CAL_START__REG DENALI_PHY_1811
+#define LPDDR4__PHY_CLK_DC_CAL_START__FLD LPDDR4__DENALI_PHY_1811__PHY_CLK_DC_CAL_START
+
+#define LPDDR4__DENALI_PHY_1812_READ_MASK 0x0F0F0100U
+#define LPDDR4__DENALI_PHY_1812_WRITE_MASK 0x0F0F0100U
+#define LPDDR4__DENALI_PHY_1812__SC_PHY_UPDATE_CLK_CAL_VALUES_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1812__SC_PHY_UPDATE_CLK_CAL_VALUES_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1812__SC_PHY_UPDATE_CLK_CAL_VALUES_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1812__SC_PHY_UPDATE_CLK_CAL_VALUES_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1812__SC_PHY_UPDATE_CLK_CAL_VALUES_WOSET 0U
+#define LPDDR4__SC_PHY_UPDATE_CLK_CAL_VALUES__REG DENALI_PHY_1812
+#define LPDDR4__SC_PHY_UPDATE_CLK_CAL_VALUES__FLD LPDDR4__DENALI_PHY_1812__SC_PHY_UPDATE_CLK_CAL_VALUES
+
+#define LPDDR4__DENALI_PHY_1812__PHY_CONTINUOUS_CLK_CAL_UPDATE_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_1812__PHY_CONTINUOUS_CLK_CAL_UPDATE_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1812__PHY_CONTINUOUS_CLK_CAL_UPDATE_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1812__PHY_CONTINUOUS_CLK_CAL_UPDATE_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1812__PHY_CONTINUOUS_CLK_CAL_UPDATE_WOSET 0U
+#define LPDDR4__PHY_CONTINUOUS_CLK_CAL_UPDATE__REG DENALI_PHY_1812
+#define LPDDR4__PHY_CONTINUOUS_CLK_CAL_UPDATE__FLD LPDDR4__DENALI_PHY_1812__PHY_CONTINUOUS_CLK_CAL_UPDATE
+
+#define LPDDR4__DENALI_PHY_1812__PHY_SW_TXIO_CTRL_0_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_1812__PHY_SW_TXIO_CTRL_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1812__PHY_SW_TXIO_CTRL_0_WIDTH 4U
+#define LPDDR4__PHY_SW_TXIO_CTRL_0__REG DENALI_PHY_1812
+#define LPDDR4__PHY_SW_TXIO_CTRL_0__FLD LPDDR4__DENALI_PHY_1812__PHY_SW_TXIO_CTRL_0
+
+#define LPDDR4__DENALI_PHY_1812__PHY_SW_TXIO_CTRL_1_MASK 0x0F000000U
+#define LPDDR4__DENALI_PHY_1812__PHY_SW_TXIO_CTRL_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1812__PHY_SW_TXIO_CTRL_1_WIDTH 4U
+#define LPDDR4__PHY_SW_TXIO_CTRL_1__REG DENALI_PHY_1812
+#define LPDDR4__PHY_SW_TXIO_CTRL_1__FLD LPDDR4__DENALI_PHY_1812__PHY_SW_TXIO_CTRL_1
+
+#define LPDDR4__DENALI_PHY_1813_READ_MASK 0x0F010F0FU
+#define LPDDR4__DENALI_PHY_1813_WRITE_MASK 0x0F010F0FU
+#define LPDDR4__DENALI_PHY_1813__PHY_SW_TXIO_CTRL_2_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_1813__PHY_SW_TXIO_CTRL_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1813__PHY_SW_TXIO_CTRL_2_WIDTH 4U
+#define LPDDR4__PHY_SW_TXIO_CTRL_2__REG DENALI_PHY_1813
+#define LPDDR4__PHY_SW_TXIO_CTRL_2__FLD LPDDR4__DENALI_PHY_1813__PHY_SW_TXIO_CTRL_2
+
+#define LPDDR4__DENALI_PHY_1813__PHY_SW_TXIO_CTRL_3_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_1813__PHY_SW_TXIO_CTRL_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1813__PHY_SW_TXIO_CTRL_3_WIDTH 4U
+#define LPDDR4__PHY_SW_TXIO_CTRL_3__REG DENALI_PHY_1813
+#define LPDDR4__PHY_SW_TXIO_CTRL_3__FLD LPDDR4__DENALI_PHY_1813__PHY_SW_TXIO_CTRL_3
+
+#define LPDDR4__DENALI_PHY_1813__PHY_MEMCLK_SW_TXIO_CTRL_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_1813__PHY_MEMCLK_SW_TXIO_CTRL_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1813__PHY_MEMCLK_SW_TXIO_CTRL_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1813__PHY_MEMCLK_SW_TXIO_CTRL_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1813__PHY_MEMCLK_SW_TXIO_CTRL_WOSET 0U
+#define LPDDR4__PHY_MEMCLK_SW_TXIO_CTRL__REG DENALI_PHY_1813
+#define LPDDR4__PHY_MEMCLK_SW_TXIO_CTRL__FLD LPDDR4__DENALI_PHY_1813__PHY_MEMCLK_SW_TXIO_CTRL
+
+#define LPDDR4__DENALI_PHY_1813__PHY_ADRCTL_SW_TXPWR_CTRL_0_MASK 0x0F000000U
+#define LPDDR4__DENALI_PHY_1813__PHY_ADRCTL_SW_TXPWR_CTRL_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1813__PHY_ADRCTL_SW_TXPWR_CTRL_0_WIDTH 4U
+#define LPDDR4__PHY_ADRCTL_SW_TXPWR_CTRL_0__REG DENALI_PHY_1813
+#define LPDDR4__PHY_ADRCTL_SW_TXPWR_CTRL_0__FLD LPDDR4__DENALI_PHY_1813__PHY_ADRCTL_SW_TXPWR_CTRL_0
+
+#define LPDDR4__DENALI_PHY_1814_READ_MASK 0x010F0F0FU
+#define LPDDR4__DENALI_PHY_1814_WRITE_MASK 0x010F0F0FU
+#define LPDDR4__DENALI_PHY_1814__PHY_ADRCTL_SW_TXPWR_CTRL_1_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_1814__PHY_ADRCTL_SW_TXPWR_CTRL_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1814__PHY_ADRCTL_SW_TXPWR_CTRL_1_WIDTH 4U
+#define LPDDR4__PHY_ADRCTL_SW_TXPWR_CTRL_1__REG DENALI_PHY_1814
+#define LPDDR4__PHY_ADRCTL_SW_TXPWR_CTRL_1__FLD LPDDR4__DENALI_PHY_1814__PHY_ADRCTL_SW_TXPWR_CTRL_1
+
+#define LPDDR4__DENALI_PHY_1814__PHY_ADRCTL_SW_TXPWR_CTRL_2_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_1814__PHY_ADRCTL_SW_TXPWR_CTRL_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1814__PHY_ADRCTL_SW_TXPWR_CTRL_2_WIDTH 4U
+#define LPDDR4__PHY_ADRCTL_SW_TXPWR_CTRL_2__REG DENALI_PHY_1814
+#define LPDDR4__PHY_ADRCTL_SW_TXPWR_CTRL_2__FLD LPDDR4__DENALI_PHY_1814__PHY_ADRCTL_SW_TXPWR_CTRL_2
+
+#define LPDDR4__DENALI_PHY_1814__PHY_ADRCTL_SW_TXPWR_CTRL_3_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_1814__PHY_ADRCTL_SW_TXPWR_CTRL_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1814__PHY_ADRCTL_SW_TXPWR_CTRL_3_WIDTH 4U
+#define LPDDR4__PHY_ADRCTL_SW_TXPWR_CTRL_3__REG DENALI_PHY_1814
+#define LPDDR4__PHY_ADRCTL_SW_TXPWR_CTRL_3__FLD LPDDR4__DENALI_PHY_1814__PHY_ADRCTL_SW_TXPWR_CTRL_3
+
+#define LPDDR4__DENALI_PHY_1814__PHY_MEMCLK_SW_TXPWR_CTRL_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_1814__PHY_MEMCLK_SW_TXPWR_CTRL_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1814__PHY_MEMCLK_SW_TXPWR_CTRL_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1814__PHY_MEMCLK_SW_TXPWR_CTRL_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1814__PHY_MEMCLK_SW_TXPWR_CTRL_WOSET 0U
+#define LPDDR4__PHY_MEMCLK_SW_TXPWR_CTRL__REG DENALI_PHY_1814
+#define LPDDR4__PHY_MEMCLK_SW_TXPWR_CTRL__FLD LPDDR4__DENALI_PHY_1814__PHY_MEMCLK_SW_TXPWR_CTRL
+
+#define LPDDR4__DENALI_PHY_1815_READ_MASK 0xFFFF0101U
+#define LPDDR4__DENALI_PHY_1815_WRITE_MASK 0xFFFF0101U
+#define LPDDR4__DENALI_PHY_1815__PHY_TOP_STATIC_TOG_DISABLE_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1815__PHY_TOP_STATIC_TOG_DISABLE_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1815__PHY_TOP_STATIC_TOG_DISABLE_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1815__PHY_TOP_STATIC_TOG_DISABLE_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1815__PHY_TOP_STATIC_TOG_DISABLE_WOSET 0U
+#define LPDDR4__PHY_TOP_STATIC_TOG_DISABLE__REG DENALI_PHY_1815
+#define LPDDR4__PHY_TOP_STATIC_TOG_DISABLE__FLD LPDDR4__DENALI_PHY_1815__PHY_TOP_STATIC_TOG_DISABLE
+
+#define LPDDR4__DENALI_PHY_1815__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_1815__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1815__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1815__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1815__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE_WOSET 0U
+#define LPDDR4__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE__REG DENALI_PHY_1815
+#define LPDDR4__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE__FLD LPDDR4__DENALI_PHY_1815__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE
+
+#define LPDDR4__DENALI_PHY_1815__PHY_STATIC_TOG_CONTROL_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_PHY_1815__PHY_STATIC_TOG_CONTROL_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1815__PHY_STATIC_TOG_CONTROL_WIDTH 16U
+#define LPDDR4__PHY_STATIC_TOG_CONTROL__REG DENALI_PHY_1815
+#define LPDDR4__PHY_STATIC_TOG_CONTROL__FLD LPDDR4__DENALI_PHY_1815__PHY_STATIC_TOG_CONTROL
+
+#define LPDDR4__DENALI_PHY_1816_READ_MASK 0x0001010FU
+#define LPDDR4__DENALI_PHY_1816_WRITE_MASK 0x0001010FU
+#define LPDDR4__DENALI_PHY_1816__PHY_ADRCTL_STATIC_TOG_DISABLE_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_1816__PHY_ADRCTL_STATIC_TOG_DISABLE_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1816__PHY_ADRCTL_STATIC_TOG_DISABLE_WIDTH 4U
+#define LPDDR4__PHY_ADRCTL_STATIC_TOG_DISABLE__REG DENALI_PHY_1816
+#define LPDDR4__PHY_ADRCTL_STATIC_TOG_DISABLE__FLD LPDDR4__DENALI_PHY_1816__PHY_ADRCTL_STATIC_TOG_DISABLE
+
+#define LPDDR4__DENALI_PHY_1816__PHY_MEMCLK_STATIC_TOG_DISABLE_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_1816__PHY_MEMCLK_STATIC_TOG_DISABLE_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1816__PHY_MEMCLK_STATIC_TOG_DISABLE_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1816__PHY_MEMCLK_STATIC_TOG_DISABLE_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1816__PHY_MEMCLK_STATIC_TOG_DISABLE_WOSET 0U
+#define LPDDR4__PHY_MEMCLK_STATIC_TOG_DISABLE__REG DENALI_PHY_1816
+#define LPDDR4__PHY_MEMCLK_STATIC_TOG_DISABLE__FLD LPDDR4__DENALI_PHY_1816__PHY_MEMCLK_STATIC_TOG_DISABLE
+
+#define LPDDR4__DENALI_PHY_1816__PHY_LP4_BOOT_PLL_BYPASS_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_1816__PHY_LP4_BOOT_PLL_BYPASS_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1816__PHY_LP4_BOOT_PLL_BYPASS_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1816__PHY_LP4_BOOT_PLL_BYPASS_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1816__PHY_LP4_BOOT_PLL_BYPASS_WOSET 0U
+#define LPDDR4__PHY_LP4_BOOT_PLL_BYPASS__REG DENALI_PHY_1816
+#define LPDDR4__PHY_LP4_BOOT_PLL_BYPASS__FLD LPDDR4__DENALI_PHY_1816__PHY_LP4_BOOT_PLL_BYPASS
+
+#define LPDDR4__DENALI_PHY_1817_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1817_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1817__PHY_CLK_SWITCH_OBS_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1817__PHY_CLK_SWITCH_OBS_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1817__PHY_CLK_SWITCH_OBS_WIDTH 32U
+#define LPDDR4__PHY_CLK_SWITCH_OBS__REG DENALI_PHY_1817
+#define LPDDR4__PHY_CLK_SWITCH_OBS__FLD LPDDR4__DENALI_PHY_1817__PHY_CLK_SWITCH_OBS
+
+#define LPDDR4__DENALI_PHY_1818_READ_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1818_WRITE_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1818__PHY_PLL_WAIT_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1818__PHY_PLL_WAIT_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1818__PHY_PLL_WAIT_WIDTH 16U
+#define LPDDR4__PHY_PLL_WAIT__REG DENALI_PHY_1818
+#define LPDDR4__PHY_PLL_WAIT__FLD LPDDR4__DENALI_PHY_1818__PHY_PLL_WAIT
+
+#define LPDDR4__DENALI_PHY_1819_READ_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1819_WRITE_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1819__PHY_SW_PLL_BYPASS_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1819__PHY_SW_PLL_BYPASS_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1819__PHY_SW_PLL_BYPASS_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1819__PHY_SW_PLL_BYPASS_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1819__PHY_SW_PLL_BYPASS_WOSET 0U
+#define LPDDR4__PHY_SW_PLL_BYPASS__REG DENALI_PHY_1819
+#define LPDDR4__PHY_SW_PLL_BYPASS__FLD LPDDR4__DENALI_PHY_1819__PHY_SW_PLL_BYPASS
+
+#define LPDDR4__DENALI_PHY_1820_READ_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_1820_WRITE_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_1820__PHY_SET_DFI_INPUT_0_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_1820__PHY_SET_DFI_INPUT_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1820__PHY_SET_DFI_INPUT_0_WIDTH 4U
+#define LPDDR4__PHY_SET_DFI_INPUT_0__REG DENALI_PHY_1820
+#define LPDDR4__PHY_SET_DFI_INPUT_0__FLD LPDDR4__DENALI_PHY_1820__PHY_SET_DFI_INPUT_0
+
+#define LPDDR4__DENALI_PHY_1820__PHY_SET_DFI_INPUT_1_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_1820__PHY_SET_DFI_INPUT_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1820__PHY_SET_DFI_INPUT_1_WIDTH 4U
+#define LPDDR4__PHY_SET_DFI_INPUT_1__REG DENALI_PHY_1820
+#define LPDDR4__PHY_SET_DFI_INPUT_1__FLD LPDDR4__DENALI_PHY_1820__PHY_SET_DFI_INPUT_1
+
+#define LPDDR4__DENALI_PHY_1820__PHY_SET_DFI_INPUT_2_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_1820__PHY_SET_DFI_INPUT_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1820__PHY_SET_DFI_INPUT_2_WIDTH 4U
+#define LPDDR4__PHY_SET_DFI_INPUT_2__REG DENALI_PHY_1820
+#define LPDDR4__PHY_SET_DFI_INPUT_2__FLD LPDDR4__DENALI_PHY_1820__PHY_SET_DFI_INPUT_2
+
+#define LPDDR4__DENALI_PHY_1820__PHY_SET_DFI_INPUT_3_MASK 0x0F000000U
+#define LPDDR4__DENALI_PHY_1820__PHY_SET_DFI_INPUT_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1820__PHY_SET_DFI_INPUT_3_WIDTH 4U
+#define LPDDR4__PHY_SET_DFI_INPUT_3__REG DENALI_PHY_1820
+#define LPDDR4__PHY_SET_DFI_INPUT_3__FLD LPDDR4__DENALI_PHY_1820__PHY_SET_DFI_INPUT_3
+
+#define LPDDR4__DENALI_PHY_1821_READ_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_1821_WRITE_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_1821__PHY_CS_ACS_ALLOCATION_BIT0_0_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_1821__PHY_CS_ACS_ALLOCATION_BIT0_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1821__PHY_CS_ACS_ALLOCATION_BIT0_0_WIDTH 4U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT0_0__REG DENALI_PHY_1821
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT0_0__FLD LPDDR4__DENALI_PHY_1821__PHY_CS_ACS_ALLOCATION_BIT0_0
+
+#define LPDDR4__DENALI_PHY_1821__PHY_CS_ACS_ALLOCATION_BIT1_0_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_1821__PHY_CS_ACS_ALLOCATION_BIT1_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1821__PHY_CS_ACS_ALLOCATION_BIT1_0_WIDTH 4U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_0__REG DENALI_PHY_1821
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_0__FLD LPDDR4__DENALI_PHY_1821__PHY_CS_ACS_ALLOCATION_BIT1_0
+
+#define LPDDR4__DENALI_PHY_1821__PHY_CS_ACS_ALLOCATION_BIT2_0_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_1821__PHY_CS_ACS_ALLOCATION_BIT2_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1821__PHY_CS_ACS_ALLOCATION_BIT2_0_WIDTH 4U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT2_0__REG DENALI_PHY_1821
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT2_0__FLD LPDDR4__DENALI_PHY_1821__PHY_CS_ACS_ALLOCATION_BIT2_0
+
+#define LPDDR4__DENALI_PHY_1821__PHY_CS_ACS_ALLOCATION_BIT3_0_MASK 0x0F000000U
+#define LPDDR4__DENALI_PHY_1821__PHY_CS_ACS_ALLOCATION_BIT3_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1821__PHY_CS_ACS_ALLOCATION_BIT3_0_WIDTH 4U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT3_0__REG DENALI_PHY_1821
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT3_0__FLD LPDDR4__DENALI_PHY_1821__PHY_CS_ACS_ALLOCATION_BIT3_0
+
+#define LPDDR4__DENALI_PHY_1822_READ_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_1822_WRITE_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_1822__PHY_CS_ACS_ALLOCATION_BIT0_1_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_1822__PHY_CS_ACS_ALLOCATION_BIT0_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1822__PHY_CS_ACS_ALLOCATION_BIT0_1_WIDTH 4U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT0_1__REG DENALI_PHY_1822
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT0_1__FLD LPDDR4__DENALI_PHY_1822__PHY_CS_ACS_ALLOCATION_BIT0_1
+
+#define LPDDR4__DENALI_PHY_1822__PHY_CS_ACS_ALLOCATION_BIT1_1_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_1822__PHY_CS_ACS_ALLOCATION_BIT1_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1822__PHY_CS_ACS_ALLOCATION_BIT1_1_WIDTH 4U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_1__REG DENALI_PHY_1822
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_1__FLD LPDDR4__DENALI_PHY_1822__PHY_CS_ACS_ALLOCATION_BIT1_1
+
+#define LPDDR4__DENALI_PHY_1822__PHY_CS_ACS_ALLOCATION_BIT2_1_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_1822__PHY_CS_ACS_ALLOCATION_BIT2_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1822__PHY_CS_ACS_ALLOCATION_BIT2_1_WIDTH 4U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT2_1__REG DENALI_PHY_1822
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT2_1__FLD LPDDR4__DENALI_PHY_1822__PHY_CS_ACS_ALLOCATION_BIT2_1
+
+#define LPDDR4__DENALI_PHY_1822__PHY_CS_ACS_ALLOCATION_BIT3_1_MASK 0x0F000000U
+#define LPDDR4__DENALI_PHY_1822__PHY_CS_ACS_ALLOCATION_BIT3_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1822__PHY_CS_ACS_ALLOCATION_BIT3_1_WIDTH 4U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT3_1__REG DENALI_PHY_1822
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT3_1__FLD LPDDR4__DENALI_PHY_1822__PHY_CS_ACS_ALLOCATION_BIT3_1
+
+#define LPDDR4__DENALI_PHY_1823_READ_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_1823_WRITE_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_1823__PHY_CS_ACS_ALLOCATION_BIT0_2_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_1823__PHY_CS_ACS_ALLOCATION_BIT0_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1823__PHY_CS_ACS_ALLOCATION_BIT0_2_WIDTH 4U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT0_2__REG DENALI_PHY_1823
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT0_2__FLD LPDDR4__DENALI_PHY_1823__PHY_CS_ACS_ALLOCATION_BIT0_2
+
+#define LPDDR4__DENALI_PHY_1823__PHY_CS_ACS_ALLOCATION_BIT1_2_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_1823__PHY_CS_ACS_ALLOCATION_BIT1_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1823__PHY_CS_ACS_ALLOCATION_BIT1_2_WIDTH 4U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_2__REG DENALI_PHY_1823
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_2__FLD LPDDR4__DENALI_PHY_1823__PHY_CS_ACS_ALLOCATION_BIT1_2
+
+#define LPDDR4__DENALI_PHY_1823__PHY_CS_ACS_ALLOCATION_BIT2_2_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_1823__PHY_CS_ACS_ALLOCATION_BIT2_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1823__PHY_CS_ACS_ALLOCATION_BIT2_2_WIDTH 4U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT2_2__REG DENALI_PHY_1823
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT2_2__FLD LPDDR4__DENALI_PHY_1823__PHY_CS_ACS_ALLOCATION_BIT2_2
+
+#define LPDDR4__DENALI_PHY_1823__PHY_CS_ACS_ALLOCATION_BIT3_2_MASK 0x0F000000U
+#define LPDDR4__DENALI_PHY_1823__PHY_CS_ACS_ALLOCATION_BIT3_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1823__PHY_CS_ACS_ALLOCATION_BIT3_2_WIDTH 4U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT3_2__REG DENALI_PHY_1823
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT3_2__FLD LPDDR4__DENALI_PHY_1823__PHY_CS_ACS_ALLOCATION_BIT3_2
+
+#define LPDDR4__DENALI_PHY_1824_READ_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_1824_WRITE_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_1824__PHY_CS_ACS_ALLOCATION_BIT0_3_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_1824__PHY_CS_ACS_ALLOCATION_BIT0_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1824__PHY_CS_ACS_ALLOCATION_BIT0_3_WIDTH 4U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT0_3__REG DENALI_PHY_1824
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT0_3__FLD LPDDR4__DENALI_PHY_1824__PHY_CS_ACS_ALLOCATION_BIT0_3
+
+#define LPDDR4__DENALI_PHY_1824__PHY_CS_ACS_ALLOCATION_BIT1_3_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_1824__PHY_CS_ACS_ALLOCATION_BIT1_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1824__PHY_CS_ACS_ALLOCATION_BIT1_3_WIDTH 4U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_3__REG DENALI_PHY_1824
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_3__FLD LPDDR4__DENALI_PHY_1824__PHY_CS_ACS_ALLOCATION_BIT1_3
+
+#define LPDDR4__DENALI_PHY_1824__PHY_CS_ACS_ALLOCATION_BIT2_3_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_1824__PHY_CS_ACS_ALLOCATION_BIT2_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1824__PHY_CS_ACS_ALLOCATION_BIT2_3_WIDTH 4U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT2_3__REG DENALI_PHY_1824
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT2_3__FLD LPDDR4__DENALI_PHY_1824__PHY_CS_ACS_ALLOCATION_BIT2_3
+
+#define LPDDR4__DENALI_PHY_1824__PHY_CS_ACS_ALLOCATION_BIT3_3_MASK 0x0F000000U
+#define LPDDR4__DENALI_PHY_1824__PHY_CS_ACS_ALLOCATION_BIT3_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1824__PHY_CS_ACS_ALLOCATION_BIT3_3_WIDTH 4U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT3_3__REG DENALI_PHY_1824
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT3_3__FLD LPDDR4__DENALI_PHY_1824__PHY_CS_ACS_ALLOCATION_BIT3_3
+
+#define LPDDR4__DENALI_PHY_1825_READ_MASK 0x00FF01FFU
+#define LPDDR4__DENALI_PHY_1825_WRITE_MASK 0x00FF01FFU
+#define LPDDR4__DENALI_PHY_1825__PHY_CLK_DC_ADJUST_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_1825__PHY_CLK_DC_ADJUST_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1825__PHY_CLK_DC_ADJUST_0_WIDTH 8U
+#define LPDDR4__PHY_CLK_DC_ADJUST_0__REG DENALI_PHY_1825
+#define LPDDR4__PHY_CLK_DC_ADJUST_0__FLD LPDDR4__DENALI_PHY_1825__PHY_CLK_DC_ADJUST_0
+
+#define LPDDR4__DENALI_PHY_1825__PHY_CLK_DC_INIT_DISABLE_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_1825__PHY_CLK_DC_INIT_DISABLE_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1825__PHY_CLK_DC_INIT_DISABLE_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1825__PHY_CLK_DC_INIT_DISABLE_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1825__PHY_CLK_DC_INIT_DISABLE_WOSET 0U
+#define LPDDR4__PHY_CLK_DC_INIT_DISABLE__REG DENALI_PHY_1825
+#define LPDDR4__PHY_CLK_DC_INIT_DISABLE__FLD LPDDR4__DENALI_PHY_1825__PHY_CLK_DC_INIT_DISABLE
+
+#define LPDDR4__DENALI_PHY_1825__PHY_CLK_DC_DM_THRSHLD_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_1825__PHY_CLK_DC_DM_THRSHLD_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1825__PHY_CLK_DC_DM_THRSHLD_WIDTH 8U
+#define LPDDR4__PHY_CLK_DC_DM_THRSHLD__REG DENALI_PHY_1825
+#define LPDDR4__PHY_CLK_DC_DM_THRSHLD__FLD LPDDR4__DENALI_PHY_1825__PHY_CLK_DC_DM_THRSHLD
+
+#define LPDDR4__DENALI_PHY_1826_READ_MASK 0xFFFF1FFFU
+#define LPDDR4__DENALI_PHY_1826_WRITE_MASK 0xFFFF1FFFU
+#define LPDDR4__DENALI_PHY_1826__PHY_LP4_BOOT_PLL_CTRL_MASK 0x00001FFFU
+#define LPDDR4__DENALI_PHY_1826__PHY_LP4_BOOT_PLL_CTRL_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1826__PHY_LP4_BOOT_PLL_CTRL_WIDTH 13U
+#define LPDDR4__PHY_LP4_BOOT_PLL_CTRL__REG DENALI_PHY_1826
+#define LPDDR4__PHY_LP4_BOOT_PLL_CTRL__FLD LPDDR4__DENALI_PHY_1826__PHY_LP4_BOOT_PLL_CTRL
+
+#define LPDDR4__DENALI_PHY_1826__PHY_PLL_CTRL_OVERRIDE_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_PHY_1826__PHY_PLL_CTRL_OVERRIDE_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1826__PHY_PLL_CTRL_OVERRIDE_WIDTH 16U
+#define LPDDR4__PHY_PLL_CTRL_OVERRIDE__REG DENALI_PHY_1826
+#define LPDDR4__PHY_PLL_CTRL_OVERRIDE__FLD LPDDR4__DENALI_PHY_1826__PHY_PLL_CTRL_OVERRIDE
+
+#define LPDDR4__DENALI_PHY_1827_READ_MASK 0x0000FF01U
+#define LPDDR4__DENALI_PHY_1827_WRITE_MASK 0x0000FF01U
+#define LPDDR4__DENALI_PHY_1827__PHY_USE_PLL_DSKEWCALLOCK_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1827__PHY_USE_PLL_DSKEWCALLOCK_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1827__PHY_USE_PLL_DSKEWCALLOCK_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1827__PHY_USE_PLL_DSKEWCALLOCK_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1827__PHY_USE_PLL_DSKEWCALLOCK_WOSET 0U
+#define LPDDR4__PHY_USE_PLL_DSKEWCALLOCK__REG DENALI_PHY_1827
+#define LPDDR4__PHY_USE_PLL_DSKEWCALLOCK__FLD LPDDR4__DENALI_PHY_1827__PHY_USE_PLL_DSKEWCALLOCK
+
+#define LPDDR4__DENALI_PHY_1827__PHY_PLL_SPO_CAL_CTRL_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_1827__PHY_PLL_SPO_CAL_CTRL_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1827__PHY_PLL_SPO_CAL_CTRL_WIDTH 8U
+#define LPDDR4__PHY_PLL_SPO_CAL_CTRL__REG DENALI_PHY_1827
+#define LPDDR4__PHY_PLL_SPO_CAL_CTRL__FLD LPDDR4__DENALI_PHY_1827__PHY_PLL_SPO_CAL_CTRL
+
+#define LPDDR4__DENALI_PHY_1827__SC_PHY_PLL_SPO_CAL_SNAP_OBS_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_1827__SC_PHY_PLL_SPO_CAL_SNAP_OBS_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1827__SC_PHY_PLL_SPO_CAL_SNAP_OBS_WIDTH 2U
+#define LPDDR4__SC_PHY_PLL_SPO_CAL_SNAP_OBS__REG DENALI_PHY_1827
+#define LPDDR4__SC_PHY_PLL_SPO_CAL_SNAP_OBS__FLD LPDDR4__DENALI_PHY_1827__SC_PHY_PLL_SPO_CAL_SNAP_OBS
+
+#define LPDDR4__DENALI_PHY_1828_READ_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1828_WRITE_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1828__PHY_PLL_OBS_0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1828__PHY_PLL_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1828__PHY_PLL_OBS_0_WIDTH 16U
+#define LPDDR4__PHY_PLL_OBS_0__REG DENALI_PHY_1828
+#define LPDDR4__PHY_PLL_OBS_0__FLD LPDDR4__DENALI_PHY_1828__PHY_PLL_OBS_0
+
+#define LPDDR4__DENALI_PHY_1829_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1829_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1829__PHY_PLL_SPO_CAL_OBS_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1829__PHY_PLL_SPO_CAL_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1829__PHY_PLL_SPO_CAL_OBS_0_WIDTH 17U
+#define LPDDR4__PHY_PLL_SPO_CAL_OBS_0__REG DENALI_PHY_1829
+#define LPDDR4__PHY_PLL_SPO_CAL_OBS_0__FLD LPDDR4__DENALI_PHY_1829__PHY_PLL_SPO_CAL_OBS_0
+
+#define LPDDR4__DENALI_PHY_1830_READ_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_PHY_1830_WRITE_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_PHY_1830__PHY_PLL_DESKEWCALIN_0_MASK 0x00000FFFU
+#define LPDDR4__DENALI_PHY_1830__PHY_PLL_DESKEWCALIN_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1830__PHY_PLL_DESKEWCALIN_0_WIDTH 12U
+#define LPDDR4__PHY_PLL_DESKEWCALIN_0__REG DENALI_PHY_1830
+#define LPDDR4__PHY_PLL_DESKEWCALIN_0__FLD LPDDR4__DENALI_PHY_1830__PHY_PLL_DESKEWCALIN_0
+
+#define LPDDR4__DENALI_PHY_1830__PHY_LP4_BOOT_PLL_DESKEWCALIN_0_MASK 0x0FFF0000U
+#define LPDDR4__DENALI_PHY_1830__PHY_LP4_BOOT_PLL_DESKEWCALIN_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1830__PHY_LP4_BOOT_PLL_DESKEWCALIN_0_WIDTH 12U
+#define LPDDR4__PHY_LP4_BOOT_PLL_DESKEWCALIN_0__REG DENALI_PHY_1830
+#define LPDDR4__PHY_LP4_BOOT_PLL_DESKEWCALIN_0__FLD LPDDR4__DENALI_PHY_1830__PHY_LP4_BOOT_PLL_DESKEWCALIN_0
+
+#define LPDDR4__DENALI_PHY_1831_READ_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1831_WRITE_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1831__PHY_PLL_OBS_1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1831__PHY_PLL_OBS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1831__PHY_PLL_OBS_1_WIDTH 16U
+#define LPDDR4__PHY_PLL_OBS_1__REG DENALI_PHY_1831
+#define LPDDR4__PHY_PLL_OBS_1__FLD LPDDR4__DENALI_PHY_1831__PHY_PLL_OBS_1
+
+#define LPDDR4__DENALI_PHY_1832_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1832_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1832__PHY_PLL_SPO_CAL_OBS_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1832__PHY_PLL_SPO_CAL_OBS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1832__PHY_PLL_SPO_CAL_OBS_1_WIDTH 17U
+#define LPDDR4__PHY_PLL_SPO_CAL_OBS_1__REG DENALI_PHY_1832
+#define LPDDR4__PHY_PLL_SPO_CAL_OBS_1__FLD LPDDR4__DENALI_PHY_1832__PHY_PLL_SPO_CAL_OBS_1
+
+#define LPDDR4__DENALI_PHY_1833_READ_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_PHY_1833_WRITE_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_PHY_1833__PHY_PLL_DESKEWCALIN_1_MASK 0x00000FFFU
+#define LPDDR4__DENALI_PHY_1833__PHY_PLL_DESKEWCALIN_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1833__PHY_PLL_DESKEWCALIN_1_WIDTH 12U
+#define LPDDR4__PHY_PLL_DESKEWCALIN_1__REG DENALI_PHY_1833
+#define LPDDR4__PHY_PLL_DESKEWCALIN_1__FLD LPDDR4__DENALI_PHY_1833__PHY_PLL_DESKEWCALIN_1
+
+#define LPDDR4__DENALI_PHY_1833__PHY_LP4_BOOT_PLL_DESKEWCALIN_1_MASK 0x0FFF0000U
+#define LPDDR4__DENALI_PHY_1833__PHY_LP4_BOOT_PLL_DESKEWCALIN_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1833__PHY_LP4_BOOT_PLL_DESKEWCALIN_1_WIDTH 12U
+#define LPDDR4__PHY_LP4_BOOT_PLL_DESKEWCALIN_1__REG DENALI_PHY_1833
+#define LPDDR4__PHY_LP4_BOOT_PLL_DESKEWCALIN_1__FLD LPDDR4__DENALI_PHY_1833__PHY_LP4_BOOT_PLL_DESKEWCALIN_1
+
+#define LPDDR4__DENALI_PHY_1834_READ_MASK 0x0F010101U
+#define LPDDR4__DENALI_PHY_1834_WRITE_MASK 0x0F010101U
+#define LPDDR4__DENALI_PHY_1834__PHY_PLL_TESTOUT_SEL_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1834__PHY_PLL_TESTOUT_SEL_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1834__PHY_PLL_TESTOUT_SEL_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1834__PHY_PLL_TESTOUT_SEL_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1834__PHY_PLL_TESTOUT_SEL_WOSET 0U
+#define LPDDR4__PHY_PLL_TESTOUT_SEL__REG DENALI_PHY_1834
+#define LPDDR4__PHY_PLL_TESTOUT_SEL__FLD LPDDR4__DENALI_PHY_1834__PHY_PLL_TESTOUT_SEL
+
+#define LPDDR4__DENALI_PHY_1834__PHY_PLL_REFOUT_SEL_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_1834__PHY_PLL_REFOUT_SEL_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1834__PHY_PLL_REFOUT_SEL_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1834__PHY_PLL_REFOUT_SEL_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1834__PHY_PLL_REFOUT_SEL_WOSET 0U
+#define LPDDR4__PHY_PLL_REFOUT_SEL__REG DENALI_PHY_1834
+#define LPDDR4__PHY_PLL_REFOUT_SEL__FLD LPDDR4__DENALI_PHY_1834__PHY_PLL_REFOUT_SEL
+
+#define LPDDR4__DENALI_PHY_1834__PHY_LP4_BOOT_LOW_FREQ_SEL_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_1834__PHY_LP4_BOOT_LOW_FREQ_SEL_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1834__PHY_LP4_BOOT_LOW_FREQ_SEL_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1834__PHY_LP4_BOOT_LOW_FREQ_SEL_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1834__PHY_LP4_BOOT_LOW_FREQ_SEL_WOSET 0U
+#define LPDDR4__PHY_LP4_BOOT_LOW_FREQ_SEL__REG DENALI_PHY_1834
+#define LPDDR4__PHY_LP4_BOOT_LOW_FREQ_SEL__FLD LPDDR4__DENALI_PHY_1834__PHY_LP4_BOOT_LOW_FREQ_SEL
+
+#define LPDDR4__DENALI_PHY_1834__PHY_TCKSRE_WAIT_MASK 0x0F000000U
+#define LPDDR4__DENALI_PHY_1834__PHY_TCKSRE_WAIT_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1834__PHY_TCKSRE_WAIT_WIDTH 4U
+#define LPDDR4__PHY_TCKSRE_WAIT__REG DENALI_PHY_1834
+#define LPDDR4__PHY_TCKSRE_WAIT__FLD LPDDR4__DENALI_PHY_1834__PHY_TCKSRE_WAIT
+
+#define LPDDR4__DENALI_PHY_1835_READ_MASK 0x03FF01FFU
+#define LPDDR4__DENALI_PHY_1835_WRITE_MASK 0x03FF01FFU
+#define LPDDR4__DENALI_PHY_1835__PHY_LP_WAKEUP_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_1835__PHY_LP_WAKEUP_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1835__PHY_LP_WAKEUP_WIDTH 8U
+#define LPDDR4__PHY_LP_WAKEUP__REG DENALI_PHY_1835
+#define LPDDR4__PHY_LP_WAKEUP__FLD LPDDR4__DENALI_PHY_1835__PHY_LP_WAKEUP
+
+#define LPDDR4__DENALI_PHY_1835__PHY_LS_IDLE_EN_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_1835__PHY_LS_IDLE_EN_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1835__PHY_LS_IDLE_EN_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1835__PHY_LS_IDLE_EN_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1835__PHY_LS_IDLE_EN_WOSET 0U
+#define LPDDR4__PHY_LS_IDLE_EN__REG DENALI_PHY_1835
+#define LPDDR4__PHY_LS_IDLE_EN__FLD LPDDR4__DENALI_PHY_1835__PHY_LS_IDLE_EN
+
+#define LPDDR4__DENALI_PHY_1835__PHY_LP_CTRLUPD_CNTR_CFG_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_1835__PHY_LP_CTRLUPD_CNTR_CFG_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1835__PHY_LP_CTRLUPD_CNTR_CFG_WIDTH 10U
+#define LPDDR4__PHY_LP_CTRLUPD_CNTR_CFG__REG DENALI_PHY_1835
+#define LPDDR4__PHY_LP_CTRLUPD_CNTR_CFG__FLD LPDDR4__DENALI_PHY_1835__PHY_LP_CTRLUPD_CNTR_CFG
+
+#define LPDDR4__DENALI_PHY_1836_READ_MASK 0x0101FFFFU
+#define LPDDR4__DENALI_PHY_1836_WRITE_MASK 0x0101FFFFU
+#define LPDDR4__DENALI_PHY_1836__PHY_DS_EXIT_CTRL_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1836__PHY_DS_EXIT_CTRL_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1836__PHY_DS_EXIT_CTRL_WIDTH 17U
+#define LPDDR4__PHY_DS_EXIT_CTRL__REG DENALI_PHY_1836
+#define LPDDR4__PHY_DS_EXIT_CTRL__FLD LPDDR4__DENALI_PHY_1836__PHY_DS_EXIT_CTRL
+
+#define LPDDR4__DENALI_PHY_1836__PHY_TDFI_PHY_WRDELAY_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_1836__PHY_TDFI_PHY_WRDELAY_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1836__PHY_TDFI_PHY_WRDELAY_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1836__PHY_TDFI_PHY_WRDELAY_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1836__PHY_TDFI_PHY_WRDELAY_WOSET 0U
+#define LPDDR4__PHY_TDFI_PHY_WRDELAY__REG DENALI_PHY_1836
+#define LPDDR4__PHY_TDFI_PHY_WRDELAY__FLD LPDDR4__DENALI_PHY_1836__PHY_TDFI_PHY_WRDELAY
+
+#define LPDDR4__DENALI_PHY_1837_READ_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1837_WRITE_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1837__PHY_PAD_FDBK_TERM_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1837__PHY_PAD_FDBK_TERM_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1837__PHY_PAD_FDBK_TERM_WIDTH 18U
+#define LPDDR4__PHY_PAD_FDBK_TERM__REG DENALI_PHY_1837
+#define LPDDR4__PHY_PAD_FDBK_TERM__FLD LPDDR4__DENALI_PHY_1837__PHY_PAD_FDBK_TERM
+
+#define LPDDR4__DENALI_PHY_1838_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1838_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1838__PHY_PAD_DATA_TERM_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1838__PHY_PAD_DATA_TERM_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1838__PHY_PAD_DATA_TERM_WIDTH 17U
+#define LPDDR4__PHY_PAD_DATA_TERM__REG DENALI_PHY_1838
+#define LPDDR4__PHY_PAD_DATA_TERM__FLD LPDDR4__DENALI_PHY_1838__PHY_PAD_DATA_TERM
+
+#define LPDDR4__DENALI_PHY_1839_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1839_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1839__PHY_PAD_DQS_TERM_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1839__PHY_PAD_DQS_TERM_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1839__PHY_PAD_DQS_TERM_WIDTH 17U
+#define LPDDR4__PHY_PAD_DQS_TERM__REG DENALI_PHY_1839
+#define LPDDR4__PHY_PAD_DQS_TERM__FLD LPDDR4__DENALI_PHY_1839__PHY_PAD_DQS_TERM
+
+#define LPDDR4__DENALI_PHY_1840_READ_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1840_WRITE_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1840__PHY_PAD_ADDR_TERM_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1840__PHY_PAD_ADDR_TERM_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1840__PHY_PAD_ADDR_TERM_WIDTH 18U
+#define LPDDR4__PHY_PAD_ADDR_TERM__REG DENALI_PHY_1840
+#define LPDDR4__PHY_PAD_ADDR_TERM__FLD LPDDR4__DENALI_PHY_1840__PHY_PAD_ADDR_TERM
+
+#define LPDDR4__DENALI_PHY_1841_READ_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1841_WRITE_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1841__PHY_PAD_CLK_TERM_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1841__PHY_PAD_CLK_TERM_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1841__PHY_PAD_CLK_TERM_WIDTH 18U
+#define LPDDR4__PHY_PAD_CLK_TERM__REG DENALI_PHY_1841
+#define LPDDR4__PHY_PAD_CLK_TERM__FLD LPDDR4__DENALI_PHY_1841__PHY_PAD_CLK_TERM
+
+#define LPDDR4__DENALI_PHY_1842_READ_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1842_WRITE_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1842__PHY_PAD_ERR_TERM_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1842__PHY_PAD_ERR_TERM_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1842__PHY_PAD_ERR_TERM_WIDTH 18U
+#define LPDDR4__PHY_PAD_ERR_TERM__REG DENALI_PHY_1842
+#define LPDDR4__PHY_PAD_ERR_TERM__FLD LPDDR4__DENALI_PHY_1842__PHY_PAD_ERR_TERM
+
+#define LPDDR4__DENALI_PHY_1843_READ_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1843_WRITE_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1843__PHY_PAD_CKE_TERM_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1843__PHY_PAD_CKE_TERM_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1843__PHY_PAD_CKE_TERM_WIDTH 18U
+#define LPDDR4__PHY_PAD_CKE_TERM__REG DENALI_PHY_1843
+#define LPDDR4__PHY_PAD_CKE_TERM__FLD LPDDR4__DENALI_PHY_1843__PHY_PAD_CKE_TERM
+
+#define LPDDR4__DENALI_PHY_1844_READ_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1844_WRITE_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1844__PHY_PAD_RST_TERM_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1844__PHY_PAD_RST_TERM_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1844__PHY_PAD_RST_TERM_WIDTH 18U
+#define LPDDR4__PHY_PAD_RST_TERM__REG DENALI_PHY_1844
+#define LPDDR4__PHY_PAD_RST_TERM__FLD LPDDR4__DENALI_PHY_1844__PHY_PAD_RST_TERM
+
+#define LPDDR4__DENALI_PHY_1845_READ_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1845_WRITE_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1845__PHY_PAD_CS_TERM_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1845__PHY_PAD_CS_TERM_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1845__PHY_PAD_CS_TERM_WIDTH 18U
+#define LPDDR4__PHY_PAD_CS_TERM__REG DENALI_PHY_1845
+#define LPDDR4__PHY_PAD_CS_TERM__FLD LPDDR4__DENALI_PHY_1845__PHY_PAD_CS_TERM
+
+#define LPDDR4__DENALI_PHY_1846_READ_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1846_WRITE_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1846__PHY_PAD_ODT_TERM_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1846__PHY_PAD_ODT_TERM_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1846__PHY_PAD_ODT_TERM_WIDTH 18U
+#define LPDDR4__PHY_PAD_ODT_TERM__REG DENALI_PHY_1846
+#define LPDDR4__PHY_PAD_ODT_TERM__FLD LPDDR4__DENALI_PHY_1846__PHY_PAD_ODT_TERM
+
+#define LPDDR4__DENALI_PHY_1847_READ_MASK 0x1FFF03FFU
+#define LPDDR4__DENALI_PHY_1847_WRITE_MASK 0x1FFF03FFU
+#define LPDDR4__DENALI_PHY_1847__PHY_ADRCTL_RX_CAL_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_1847__PHY_ADRCTL_RX_CAL_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1847__PHY_ADRCTL_RX_CAL_WIDTH 10U
+#define LPDDR4__PHY_ADRCTL_RX_CAL__REG DENALI_PHY_1847
+#define LPDDR4__PHY_ADRCTL_RX_CAL__FLD LPDDR4__DENALI_PHY_1847__PHY_ADRCTL_RX_CAL
+
+#define LPDDR4__DENALI_PHY_1847__PHY_ADRCTL_LP3_RX_CAL_MASK 0x1FFF0000U
+#define LPDDR4__DENALI_PHY_1847__PHY_ADRCTL_LP3_RX_CAL_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1847__PHY_ADRCTL_LP3_RX_CAL_WIDTH 13U
+#define LPDDR4__PHY_ADRCTL_LP3_RX_CAL__REG DENALI_PHY_1847
+#define LPDDR4__PHY_ADRCTL_LP3_RX_CAL__FLD LPDDR4__DENALI_PHY_1847__PHY_ADRCTL_LP3_RX_CAL
+
+#define LPDDR4__DENALI_PHY_1848_READ_MASK 0x00001FFFU
+#define LPDDR4__DENALI_PHY_1848_WRITE_MASK 0x00001FFFU
+#define LPDDR4__DENALI_PHY_1848__PHY_CAL_MODE_0_MASK 0x00001FFFU
+#define LPDDR4__DENALI_PHY_1848__PHY_CAL_MODE_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1848__PHY_CAL_MODE_0_WIDTH 13U
+#define LPDDR4__PHY_CAL_MODE_0__REG DENALI_PHY_1848
+#define LPDDR4__PHY_CAL_MODE_0__FLD LPDDR4__DENALI_PHY_1848__PHY_CAL_MODE_0
+
+#define LPDDR4__DENALI_PHY_1848__PHY_CAL_CLEAR_0_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_1848__PHY_CAL_CLEAR_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1848__PHY_CAL_CLEAR_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1848__PHY_CAL_CLEAR_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1848__PHY_CAL_CLEAR_0_WOSET 0U
+#define LPDDR4__PHY_CAL_CLEAR_0__REG DENALI_PHY_1848
+#define LPDDR4__PHY_CAL_CLEAR_0__FLD LPDDR4__DENALI_PHY_1848__PHY_CAL_CLEAR_0
+
+#define LPDDR4__DENALI_PHY_1848__PHY_CAL_START_0_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_1848__PHY_CAL_START_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1848__PHY_CAL_START_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1848__PHY_CAL_START_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1848__PHY_CAL_START_0_WOSET 0U
+#define LPDDR4__PHY_CAL_START_0__REG DENALI_PHY_1848
+#define LPDDR4__PHY_CAL_START_0__FLD LPDDR4__DENALI_PHY_1848__PHY_CAL_START_0
+
+#define LPDDR4__DENALI_PHY_1849_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1849_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1849__PHY_CAL_INTERVAL_COUNT_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1849__PHY_CAL_INTERVAL_COUNT_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1849__PHY_CAL_INTERVAL_COUNT_0_WIDTH 32U
+#define LPDDR4__PHY_CAL_INTERVAL_COUNT_0__REG DENALI_PHY_1849
+#define LPDDR4__PHY_CAL_INTERVAL_COUNT_0__FLD LPDDR4__DENALI_PHY_1849__PHY_CAL_INTERVAL_COUNT_0
+
+#define LPDDR4__DENALI_PHY_1850_READ_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1850_WRITE_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1850__PHY_CAL_SAMPLE_WAIT_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_1850__PHY_CAL_SAMPLE_WAIT_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1850__PHY_CAL_SAMPLE_WAIT_0_WIDTH 8U
+#define LPDDR4__PHY_CAL_SAMPLE_WAIT_0__REG DENALI_PHY_1850
+#define LPDDR4__PHY_CAL_SAMPLE_WAIT_0__FLD LPDDR4__DENALI_PHY_1850__PHY_CAL_SAMPLE_WAIT_0
+
+#define LPDDR4__DENALI_PHY_1850__PHY_LP4_BOOT_CAL_CLK_SELECT_0_MASK 0x00000700U
+#define LPDDR4__DENALI_PHY_1850__PHY_LP4_BOOT_CAL_CLK_SELECT_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1850__PHY_LP4_BOOT_CAL_CLK_SELECT_0_WIDTH 3U
+#define LPDDR4__PHY_LP4_BOOT_CAL_CLK_SELECT_0__REG DENALI_PHY_1850
+#define LPDDR4__PHY_LP4_BOOT_CAL_CLK_SELECT_0__FLD LPDDR4__DENALI_PHY_1850__PHY_LP4_BOOT_CAL_CLK_SELECT_0
+
+#define LPDDR4__DENALI_PHY_1851_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1851_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1851__PHY_CAL_RESULT_OBS_0_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1851__PHY_CAL_RESULT_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1851__PHY_CAL_RESULT_OBS_0_WIDTH 24U
+#define LPDDR4__PHY_CAL_RESULT_OBS_0__REG DENALI_PHY_1851
+#define LPDDR4__PHY_CAL_RESULT_OBS_0__FLD LPDDR4__DENALI_PHY_1851__PHY_CAL_RESULT_OBS_0
+
+#define LPDDR4__DENALI_PHY_1852_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1852_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1852__PHY_CAL_RESULT2_OBS_0_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1852__PHY_CAL_RESULT2_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1852__PHY_CAL_RESULT2_OBS_0_WIDTH 24U
+#define LPDDR4__PHY_CAL_RESULT2_OBS_0__REG DENALI_PHY_1852
+#define LPDDR4__PHY_CAL_RESULT2_OBS_0__FLD LPDDR4__DENALI_PHY_1852__PHY_CAL_RESULT2_OBS_0
+
+#define LPDDR4__DENALI_PHY_1853_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1853_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1853__PHY_CAL_RESULT4_OBS_0_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1853__PHY_CAL_RESULT4_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1853__PHY_CAL_RESULT4_OBS_0_WIDTH 24U
+#define LPDDR4__PHY_CAL_RESULT4_OBS_0__REG DENALI_PHY_1853
+#define LPDDR4__PHY_CAL_RESULT4_OBS_0__FLD LPDDR4__DENALI_PHY_1853__PHY_CAL_RESULT4_OBS_0
+
+#define LPDDR4__DENALI_PHY_1854_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1854_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1854__PHY_CAL_RESULT5_OBS_0_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1854__PHY_CAL_RESULT5_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1854__PHY_CAL_RESULT5_OBS_0_WIDTH 24U
+#define LPDDR4__PHY_CAL_RESULT5_OBS_0__REG DENALI_PHY_1854
+#define LPDDR4__PHY_CAL_RESULT5_OBS_0__FLD LPDDR4__DENALI_PHY_1854__PHY_CAL_RESULT5_OBS_0
+
+#define LPDDR4__DENALI_PHY_1855_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1855_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1855__PHY_CAL_RESULT6_OBS_0_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1855__PHY_CAL_RESULT6_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1855__PHY_CAL_RESULT6_OBS_0_WIDTH 24U
+#define LPDDR4__PHY_CAL_RESULT6_OBS_0__REG DENALI_PHY_1855
+#define LPDDR4__PHY_CAL_RESULT6_OBS_0__FLD LPDDR4__DENALI_PHY_1855__PHY_CAL_RESULT6_OBS_0
+
+#define LPDDR4__DENALI_PHY_1856_READ_MASK 0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_1856_WRITE_MASK 0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_1856__PHY_CAL_RESULT7_OBS_0_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1856__PHY_CAL_RESULT7_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1856__PHY_CAL_RESULT7_OBS_0_WIDTH 24U
+#define LPDDR4__PHY_CAL_RESULT7_OBS_0__REG DENALI_PHY_1856
+#define LPDDR4__PHY_CAL_RESULT7_OBS_0__FLD LPDDR4__DENALI_PHY_1856__PHY_CAL_RESULT7_OBS_0
+
+#define LPDDR4__DENALI_PHY_1856__PHY_CAL_CPTR_CNT_0_MASK 0x7F000000U
+#define LPDDR4__DENALI_PHY_1856__PHY_CAL_CPTR_CNT_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1856__PHY_CAL_CPTR_CNT_0_WIDTH 7U
+#define LPDDR4__PHY_CAL_CPTR_CNT_0__REG DENALI_PHY_1856
+#define LPDDR4__PHY_CAL_CPTR_CNT_0__FLD LPDDR4__DENALI_PHY_1856__PHY_CAL_CPTR_CNT_0
+
+#define LPDDR4__DENALI_PHY_1857_READ_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_PHY_1857_WRITE_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_PHY_1857__PHY_CAL_PU_FINE_ADJ_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_1857__PHY_CAL_PU_FINE_ADJ_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1857__PHY_CAL_PU_FINE_ADJ_0_WIDTH 8U
+#define LPDDR4__PHY_CAL_PU_FINE_ADJ_0__REG DENALI_PHY_1857
+#define LPDDR4__PHY_CAL_PU_FINE_ADJ_0__FLD LPDDR4__DENALI_PHY_1857__PHY_CAL_PU_FINE_ADJ_0
+
+#define LPDDR4__DENALI_PHY_1857__PHY_CAL_PD_FINE_ADJ_0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_1857__PHY_CAL_PD_FINE_ADJ_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1857__PHY_CAL_PD_FINE_ADJ_0_WIDTH 8U
+#define LPDDR4__PHY_CAL_PD_FINE_ADJ_0__REG DENALI_PHY_1857
+#define LPDDR4__PHY_CAL_PD_FINE_ADJ_0__FLD LPDDR4__DENALI_PHY_1857__PHY_CAL_PD_FINE_ADJ_0
+
+#define LPDDR4__DENALI_PHY_1857__PHY_CAL_RCV_FINE_ADJ_0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_1857__PHY_CAL_RCV_FINE_ADJ_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1857__PHY_CAL_RCV_FINE_ADJ_0_WIDTH 8U
+#define LPDDR4__PHY_CAL_RCV_FINE_ADJ_0__REG DENALI_PHY_1857
+#define LPDDR4__PHY_CAL_RCV_FINE_ADJ_0__FLD LPDDR4__DENALI_PHY_1857__PHY_CAL_RCV_FINE_ADJ_0
+
+#define LPDDR4__DENALI_PHY_1857__PHY_CAL_DBG_CFG_0_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_1857__PHY_CAL_DBG_CFG_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1857__PHY_CAL_DBG_CFG_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1857__PHY_CAL_DBG_CFG_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1857__PHY_CAL_DBG_CFG_0_WOSET 0U
+#define LPDDR4__PHY_CAL_DBG_CFG_0__REG DENALI_PHY_1857
+#define LPDDR4__PHY_CAL_DBG_CFG_0__FLD LPDDR4__DENALI_PHY_1857__PHY_CAL_DBG_CFG_0
+
+#define LPDDR4__DENALI_PHY_1858__SC_PHY_PAD_DBG_CONT_0_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1858__SC_PHY_PAD_DBG_CONT_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1858__SC_PHY_PAD_DBG_CONT_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1858__SC_PHY_PAD_DBG_CONT_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1858__SC_PHY_PAD_DBG_CONT_0_WOSET 0U
+#define LPDDR4__SC_PHY_PAD_DBG_CONT_0__REG DENALI_PHY_1858
+#define LPDDR4__SC_PHY_PAD_DBG_CONT_0__FLD LPDDR4__DENALI_PHY_1858__SC_PHY_PAD_DBG_CONT_0
+
+#define LPDDR4__DENALI_PHY_1859_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1859_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1859__PHY_CAL_RESULT3_OBS_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1859__PHY_CAL_RESULT3_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1859__PHY_CAL_RESULT3_OBS_0_WIDTH 32U
+#define LPDDR4__PHY_CAL_RESULT3_OBS_0__REG DENALI_PHY_1859
+#define LPDDR4__PHY_CAL_RESULT3_OBS_0__FLD LPDDR4__DENALI_PHY_1859__PHY_CAL_RESULT3_OBS_0
+
+#define LPDDR4__DENALI_PHY_1860_READ_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1860_WRITE_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1860__PHY_ADRCTL_PVT_MAP_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_1860__PHY_ADRCTL_PVT_MAP_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1860__PHY_ADRCTL_PVT_MAP_0_WIDTH 8U
+#define LPDDR4__PHY_ADRCTL_PVT_MAP_0__REG DENALI_PHY_1860
+#define LPDDR4__PHY_ADRCTL_PVT_MAP_0__FLD LPDDR4__DENALI_PHY_1860__PHY_ADRCTL_PVT_MAP_0
+
+#define LPDDR4__DENALI_PHY_1860__PHY_CAL_SLOPE_ADJ_0_MASK 0x0FFFFF00U
+#define LPDDR4__DENALI_PHY_1860__PHY_CAL_SLOPE_ADJ_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1860__PHY_CAL_SLOPE_ADJ_0_WIDTH 20U
+#define LPDDR4__PHY_CAL_SLOPE_ADJ_0__REG DENALI_PHY_1860
+#define LPDDR4__PHY_CAL_SLOPE_ADJ_0__FLD LPDDR4__DENALI_PHY_1860__PHY_CAL_SLOPE_ADJ_0
+
+#define LPDDR4__DENALI_PHY_1861_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1861_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1861__PHY_CAL_SLOPE_ADJ_PASS2_0_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1861__PHY_CAL_SLOPE_ADJ_PASS2_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1861__PHY_CAL_SLOPE_ADJ_PASS2_0_WIDTH 20U
+#define LPDDR4__PHY_CAL_SLOPE_ADJ_PASS2_0__REG DENALI_PHY_1861
+#define LPDDR4__PHY_CAL_SLOPE_ADJ_PASS2_0__FLD LPDDR4__DENALI_PHY_1861__PHY_CAL_SLOPE_ADJ_PASS2_0
+
+#define LPDDR4__DENALI_PHY_1862_READ_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_PHY_1862_WRITE_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_PHY_1862__PHY_CAL_TWO_PASS_CFG_0_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_PHY_1862__PHY_CAL_TWO_PASS_CFG_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1862__PHY_CAL_TWO_PASS_CFG_0_WIDTH 25U
+#define LPDDR4__PHY_CAL_TWO_PASS_CFG_0__REG DENALI_PHY_1862
+#define LPDDR4__PHY_CAL_TWO_PASS_CFG_0__FLD LPDDR4__DENALI_PHY_1862__PHY_CAL_TWO_PASS_CFG_0
+
+#define LPDDR4__DENALI_PHY_1863_READ_MASK 0x3F7FFFFFU
+#define LPDDR4__DENALI_PHY_1863_WRITE_MASK 0x3F7FFFFFU
+#define LPDDR4__DENALI_PHY_1863__PHY_CAL_SW_CAL_CFG_0_MASK 0x007FFFFFU
+#define LPDDR4__DENALI_PHY_1863__PHY_CAL_SW_CAL_CFG_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1863__PHY_CAL_SW_CAL_CFG_0_WIDTH 23U
+#define LPDDR4__PHY_CAL_SW_CAL_CFG_0__REG DENALI_PHY_1863
+#define LPDDR4__PHY_CAL_SW_CAL_CFG_0__FLD LPDDR4__DENALI_PHY_1863__PHY_CAL_SW_CAL_CFG_0
+
+#define LPDDR4__DENALI_PHY_1863__PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0_MASK 0x3F000000U
+#define LPDDR4__DENALI_PHY_1863__PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1863__PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0_WIDTH 6U
+#define LPDDR4__PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0__REG DENALI_PHY_1863
+#define LPDDR4__PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0__FLD LPDDR4__DENALI_PHY_1863__PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0
+
+#define LPDDR4__DENALI_PHY_1864_READ_MASK 0x3F3F1F3FU
+#define LPDDR4__DENALI_PHY_1864_WRITE_MASK 0x3F3F1F3FU
+#define LPDDR4__DENALI_PHY_1864__PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_1864__PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1864__PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0_WIDTH 6U
+#define LPDDR4__PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0__REG DENALI_PHY_1864
+#define LPDDR4__PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0__FLD LPDDR4__DENALI_PHY_1864__PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0
+
+#define LPDDR4__DENALI_PHY_1864__PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0_MASK 0x00001F00U
+#define LPDDR4__DENALI_PHY_1864__PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1864__PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0_WIDTH 5U
+#define LPDDR4__PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0__REG DENALI_PHY_1864
+#define LPDDR4__PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0__FLD LPDDR4__DENALI_PHY_1864__PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0
+
+#define LPDDR4__DENALI_PHY_1864__PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0_MASK 0x003F0000U
+#define LPDDR4__DENALI_PHY_1864__PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1864__PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0_WIDTH 6U
+#define LPDDR4__PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0__REG DENALI_PHY_1864
+#define LPDDR4__PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0__FLD LPDDR4__DENALI_PHY_1864__PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0
+
+#define LPDDR4__DENALI_PHY_1864__PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0_MASK 0x3F000000U
+#define LPDDR4__DENALI_PHY_1864__PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1864__PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0_WIDTH 6U
+#define LPDDR4__PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0__REG DENALI_PHY_1864
+#define LPDDR4__PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0__FLD LPDDR4__DENALI_PHY_1864__PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0
+
+#define LPDDR4__DENALI_PHY_1865_READ_MASK 0x1F3F3F1FU
+#define LPDDR4__DENALI_PHY_1865_WRITE_MASK 0x1F3F3F1FU
+#define LPDDR4__DENALI_PHY_1865__PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0_MASK 0x0000001FU
+#define LPDDR4__DENALI_PHY_1865__PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1865__PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0_WIDTH 5U
+#define LPDDR4__PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0__REG DENALI_PHY_1865
+#define LPDDR4__PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0__FLD LPDDR4__DENALI_PHY_1865__PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0
+
+#define LPDDR4__DENALI_PHY_1865__PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0_MASK 0x00003F00U
+#define LPDDR4__DENALI_PHY_1865__PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1865__PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0_WIDTH 6U
+#define LPDDR4__PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0__REG DENALI_PHY_1865
+#define LPDDR4__PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0__FLD LPDDR4__DENALI_PHY_1865__PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0
+
+#define LPDDR4__DENALI_PHY_1865__PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0_MASK 0x003F0000U
+#define LPDDR4__DENALI_PHY_1865__PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1865__PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0_WIDTH 6U
+#define LPDDR4__PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0__REG DENALI_PHY_1865
+#define LPDDR4__PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0__FLD LPDDR4__DENALI_PHY_1865__PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0
+
+#define LPDDR4__DENALI_PHY_1865__PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_1865__PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1865__PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0_WIDTH 5U
+#define LPDDR4__PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0__REG DENALI_PHY_1865
+#define LPDDR4__PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0__FLD LPDDR4__DENALI_PHY_1865__PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0
+
+#define LPDDR4__DENALI_PHY_1866_READ_MASK 0x001F3F3FU
+#define LPDDR4__DENALI_PHY_1866_WRITE_MASK 0x001F3F3FU
+#define LPDDR4__DENALI_PHY_1866__PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_1866__PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1866__PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0_WIDTH 6U
+#define LPDDR4__PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0__REG DENALI_PHY_1866
+#define LPDDR4__PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0__FLD LPDDR4__DENALI_PHY_1866__PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0
+
+#define LPDDR4__DENALI_PHY_1866__PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0_MASK 0x00003F00U
+#define LPDDR4__DENALI_PHY_1866__PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1866__PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0_WIDTH 6U
+#define LPDDR4__PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0__REG DENALI_PHY_1866
+#define LPDDR4__PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0__FLD LPDDR4__DENALI_PHY_1866__PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0
+
+#define LPDDR4__DENALI_PHY_1866__PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_1866__PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1866__PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0_WIDTH 5U
+#define LPDDR4__PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0__REG DENALI_PHY_1866
+#define LPDDR4__PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0__FLD LPDDR4__DENALI_PHY_1866__PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0
+
+#define LPDDR4__DENALI_PHY_1867_READ_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1867_WRITE_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1867__PHY_PAD_ATB_CTRL_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1867__PHY_PAD_ATB_CTRL_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1867__PHY_PAD_ATB_CTRL_WIDTH 16U
+#define LPDDR4__PHY_PAD_ATB_CTRL__REG DENALI_PHY_1867
+#define LPDDR4__PHY_PAD_ATB_CTRL__FLD LPDDR4__DENALI_PHY_1867__PHY_PAD_ATB_CTRL
+
+#define LPDDR4__DENALI_PHY_1867__PHY_ADRCTL_MANUAL_UPDATE_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_1867__PHY_ADRCTL_MANUAL_UPDATE_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1867__PHY_ADRCTL_MANUAL_UPDATE_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1867__PHY_ADRCTL_MANUAL_UPDATE_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1867__PHY_ADRCTL_MANUAL_UPDATE_WOSET 0U
+#define LPDDR4__PHY_ADRCTL_MANUAL_UPDATE__REG DENALI_PHY_1867
+#define LPDDR4__PHY_ADRCTL_MANUAL_UPDATE__FLD LPDDR4__DENALI_PHY_1867__PHY_ADRCTL_MANUAL_UPDATE
+
+#define LPDDR4__DENALI_PHY_1867__PHY_AC_LPBK_ERR_CLEAR_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_1867__PHY_AC_LPBK_ERR_CLEAR_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1867__PHY_AC_LPBK_ERR_CLEAR_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1867__PHY_AC_LPBK_ERR_CLEAR_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1867__PHY_AC_LPBK_ERR_CLEAR_WOSET 0U
+#define LPDDR4__PHY_AC_LPBK_ERR_CLEAR__REG DENALI_PHY_1867
+#define LPDDR4__PHY_AC_LPBK_ERR_CLEAR__FLD LPDDR4__DENALI_PHY_1867__PHY_AC_LPBK_ERR_CLEAR
+
+#define LPDDR4__DENALI_PHY_1868_READ_MASK 0x01FF0F03U
+#define LPDDR4__DENALI_PHY_1868_WRITE_MASK 0x01FF0F03U
+#define LPDDR4__DENALI_PHY_1868__PHY_AC_LPBK_OBS_SELECT_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_1868__PHY_AC_LPBK_OBS_SELECT_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1868__PHY_AC_LPBK_OBS_SELECT_WIDTH 2U
+#define LPDDR4__PHY_AC_LPBK_OBS_SELECT__REG DENALI_PHY_1868
+#define LPDDR4__PHY_AC_LPBK_OBS_SELECT__FLD LPDDR4__DENALI_PHY_1868__PHY_AC_LPBK_OBS_SELECT
+
+#define LPDDR4__DENALI_PHY_1868__PHY_AC_LPBK_ENABLE_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_1868__PHY_AC_LPBK_ENABLE_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1868__PHY_AC_LPBK_ENABLE_WIDTH 4U
+#define LPDDR4__PHY_AC_LPBK_ENABLE__REG DENALI_PHY_1868
+#define LPDDR4__PHY_AC_LPBK_ENABLE__FLD LPDDR4__DENALI_PHY_1868__PHY_AC_LPBK_ENABLE
+
+#define LPDDR4__DENALI_PHY_1868__PHY_AC_LPBK_CONTROL_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_1868__PHY_AC_LPBK_CONTROL_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1868__PHY_AC_LPBK_CONTROL_WIDTH 9U
+#define LPDDR4__PHY_AC_LPBK_CONTROL__REG DENALI_PHY_1868
+#define LPDDR4__PHY_AC_LPBK_CONTROL__FLD LPDDR4__DENALI_PHY_1868__PHY_AC_LPBK_CONTROL
+
+#define LPDDR4__DENALI_PHY_1869_READ_MASK 0x00000F7FU
+#define LPDDR4__DENALI_PHY_1869_WRITE_MASK 0x00000F7FU
+#define LPDDR4__DENALI_PHY_1869__PHY_AC_PRBS_PATTERN_START_MASK 0x0000007FU
+#define LPDDR4__DENALI_PHY_1869__PHY_AC_PRBS_PATTERN_START_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1869__PHY_AC_PRBS_PATTERN_START_WIDTH 7U
+#define LPDDR4__PHY_AC_PRBS_PATTERN_START__REG DENALI_PHY_1869
+#define LPDDR4__PHY_AC_PRBS_PATTERN_START__FLD LPDDR4__DENALI_PHY_1869__PHY_AC_PRBS_PATTERN_START
+
+#define LPDDR4__DENALI_PHY_1869__PHY_AC_PRBS_PATTERN_MASK_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_1869__PHY_AC_PRBS_PATTERN_MASK_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1869__PHY_AC_PRBS_PATTERN_MASK_WIDTH 4U
+#define LPDDR4__PHY_AC_PRBS_PATTERN_MASK__REG DENALI_PHY_1869
+#define LPDDR4__PHY_AC_PRBS_PATTERN_MASK__FLD LPDDR4__DENALI_PHY_1869__PHY_AC_PRBS_PATTERN_MASK
+
+#define LPDDR4__DENALI_PHY_1870_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1870_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1870__PHY_AC_LPBK_RESULT_OBS_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1870__PHY_AC_LPBK_RESULT_OBS_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1870__PHY_AC_LPBK_RESULT_OBS_WIDTH 32U
+#define LPDDR4__PHY_AC_LPBK_RESULT_OBS__REG DENALI_PHY_1870
+#define LPDDR4__PHY_AC_LPBK_RESULT_OBS__FLD LPDDR4__DENALI_PHY_1870__PHY_AC_LPBK_RESULT_OBS
+
+#define LPDDR4__DENALI_PHY_1871_READ_MASK 0x003F0101U
+#define LPDDR4__DENALI_PHY_1871_WRITE_MASK 0x003F0101U
+#define LPDDR4__DENALI_PHY_1871__PHY_AC_CLK_LPBK_OBS_SELECT_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1871__PHY_AC_CLK_LPBK_OBS_SELECT_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1871__PHY_AC_CLK_LPBK_OBS_SELECT_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1871__PHY_AC_CLK_LPBK_OBS_SELECT_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1871__PHY_AC_CLK_LPBK_OBS_SELECT_WOSET 0U
+#define LPDDR4__PHY_AC_CLK_LPBK_OBS_SELECT__REG DENALI_PHY_1871
+#define LPDDR4__PHY_AC_CLK_LPBK_OBS_SELECT__FLD LPDDR4__DENALI_PHY_1871__PHY_AC_CLK_LPBK_OBS_SELECT
+
+#define LPDDR4__DENALI_PHY_1871__PHY_AC_CLK_LPBK_ENABLE_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_1871__PHY_AC_CLK_LPBK_ENABLE_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1871__PHY_AC_CLK_LPBK_ENABLE_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1871__PHY_AC_CLK_LPBK_ENABLE_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1871__PHY_AC_CLK_LPBK_ENABLE_WOSET 0U
+#define LPDDR4__PHY_AC_CLK_LPBK_ENABLE__REG DENALI_PHY_1871
+#define LPDDR4__PHY_AC_CLK_LPBK_ENABLE__FLD LPDDR4__DENALI_PHY_1871__PHY_AC_CLK_LPBK_ENABLE
+
+#define LPDDR4__DENALI_PHY_1871__PHY_AC_CLK_LPBK_CONTROL_MASK 0x003F0000U
+#define LPDDR4__DENALI_PHY_1871__PHY_AC_CLK_LPBK_CONTROL_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1871__PHY_AC_CLK_LPBK_CONTROL_WIDTH 6U
+#define LPDDR4__PHY_AC_CLK_LPBK_CONTROL__REG DENALI_PHY_1871
+#define LPDDR4__PHY_AC_CLK_LPBK_CONTROL__FLD LPDDR4__DENALI_PHY_1871__PHY_AC_CLK_LPBK_CONTROL
+
+#define LPDDR4__DENALI_PHY_1872_READ_MASK 0x0101FFFFU
+#define LPDDR4__DENALI_PHY_1872_WRITE_MASK 0x0101FFFFU
+#define LPDDR4__DENALI_PHY_1872__PHY_AC_CLK_LPBK_RESULT_OBS_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1872__PHY_AC_CLK_LPBK_RESULT_OBS_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1872__PHY_AC_CLK_LPBK_RESULT_OBS_WIDTH 16U
+#define LPDDR4__PHY_AC_CLK_LPBK_RESULT_OBS__REG DENALI_PHY_1872
+#define LPDDR4__PHY_AC_CLK_LPBK_RESULT_OBS__FLD LPDDR4__DENALI_PHY_1872__PHY_AC_CLK_LPBK_RESULT_OBS
+
+#define LPDDR4__DENALI_PHY_1872__PHY_AC_PWR_RDC_DISABLE_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_1872__PHY_AC_PWR_RDC_DISABLE_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1872__PHY_AC_PWR_RDC_DISABLE_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1872__PHY_AC_PWR_RDC_DISABLE_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1872__PHY_AC_PWR_RDC_DISABLE_WOSET 0U
+#define LPDDR4__PHY_AC_PWR_RDC_DISABLE__REG DENALI_PHY_1872
+#define LPDDR4__PHY_AC_PWR_RDC_DISABLE__FLD LPDDR4__DENALI_PHY_1872__PHY_AC_PWR_RDC_DISABLE
+
+#define LPDDR4__DENALI_PHY_1872__PHY_TOP_PWR_RDC_DISABLE_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_1872__PHY_TOP_PWR_RDC_DISABLE_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1872__PHY_TOP_PWR_RDC_DISABLE_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1872__PHY_TOP_PWR_RDC_DISABLE_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1872__PHY_TOP_PWR_RDC_DISABLE_WOSET 0U
+#define LPDDR4__PHY_TOP_PWR_RDC_DISABLE__REG DENALI_PHY_1872
+#define LPDDR4__PHY_TOP_PWR_RDC_DISABLE__FLD LPDDR4__DENALI_PHY_1872__PHY_TOP_PWR_RDC_DISABLE
+
+#define LPDDR4__DENALI_PHY_1873_READ_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1873_WRITE_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1873__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1873__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1873__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1873__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1873__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE_WOSET 0U
+#define LPDDR4__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE__REG DENALI_PHY_1873
+#define LPDDR4__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE__FLD LPDDR4__DENALI_PHY_1873__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE
+
+#define LPDDR4__DENALI_PHY_1874_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1874_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1874__PHY_DATA_BYTE_ORDER_SEL_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1874__PHY_DATA_BYTE_ORDER_SEL_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1874__PHY_DATA_BYTE_ORDER_SEL_WIDTH 32U
+#define LPDDR4__PHY_DATA_BYTE_ORDER_SEL__REG DENALI_PHY_1874
+#define LPDDR4__PHY_DATA_BYTE_ORDER_SEL__FLD LPDDR4__DENALI_PHY_1874__PHY_DATA_BYTE_ORDER_SEL
+
+#define LPDDR4__DENALI_PHY_1875_READ_MASK 0x071F01FFU
+#define LPDDR4__DENALI_PHY_1875_WRITE_MASK 0x071F01FFU
+#define LPDDR4__DENALI_PHY_1875__PHY_DATA_BYTE_ORDER_SEL_HIGH_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_1875__PHY_DATA_BYTE_ORDER_SEL_HIGH_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1875__PHY_DATA_BYTE_ORDER_SEL_HIGH_WIDTH 8U
+#define LPDDR4__PHY_DATA_BYTE_ORDER_SEL_HIGH__REG DENALI_PHY_1875
+#define LPDDR4__PHY_DATA_BYTE_ORDER_SEL_HIGH__FLD LPDDR4__DENALI_PHY_1875__PHY_DATA_BYTE_ORDER_SEL_HIGH
+
+#define LPDDR4__DENALI_PHY_1875__PHY_LPDDR4_CONNECT_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_1875__PHY_LPDDR4_CONNECT_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1875__PHY_LPDDR4_CONNECT_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1875__PHY_LPDDR4_CONNECT_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1875__PHY_LPDDR4_CONNECT_WOSET 0U
+#define LPDDR4__PHY_LPDDR4_CONNECT__REG DENALI_PHY_1875
+#define LPDDR4__PHY_LPDDR4_CONNECT__FLD LPDDR4__DENALI_PHY_1875__PHY_LPDDR4_CONNECT
+
+#define LPDDR4__DENALI_PHY_1875__PHY_CALVL_DEVICE_MAP_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_1875__PHY_CALVL_DEVICE_MAP_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1875__PHY_CALVL_DEVICE_MAP_WIDTH 5U
+#define LPDDR4__PHY_CALVL_DEVICE_MAP__REG DENALI_PHY_1875
+#define LPDDR4__PHY_CALVL_DEVICE_MAP__FLD LPDDR4__DENALI_PHY_1875__PHY_CALVL_DEVICE_MAP
+
+#define LPDDR4__DENALI_PHY_1875__PHY_ADR_DISABLE_MASK 0x07000000U
+#define LPDDR4__DENALI_PHY_1875__PHY_ADR_DISABLE_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1875__PHY_ADR_DISABLE_WIDTH 3U
+#define LPDDR4__PHY_ADR_DISABLE__REG DENALI_PHY_1875
+#define LPDDR4__PHY_ADR_DISABLE__FLD LPDDR4__DENALI_PHY_1875__PHY_ADR_DISABLE
+
+#define LPDDR4__DENALI_PHY_1876_READ_MASK 0x03030303U
+#define LPDDR4__DENALI_PHY_1876_WRITE_MASK 0x03030303U
+#define LPDDR4__DENALI_PHY_1876__PHY_ADRCTL_MSTR_DLY_ENC_SEL_0_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_1876__PHY_ADRCTL_MSTR_DLY_ENC_SEL_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1876__PHY_ADRCTL_MSTR_DLY_ENC_SEL_0_WIDTH 2U
+#define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_0__REG DENALI_PHY_1876
+#define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_0__FLD LPDDR4__DENALI_PHY_1876__PHY_ADRCTL_MSTR_DLY_ENC_SEL_0
+
+#define LPDDR4__DENALI_PHY_1876__PHY_ADRCTL_MSTR_DLY_ENC_SEL_1_MASK 0x00000300U
+#define LPDDR4__DENALI_PHY_1876__PHY_ADRCTL_MSTR_DLY_ENC_SEL_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1876__PHY_ADRCTL_MSTR_DLY_ENC_SEL_1_WIDTH 2U
+#define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_1__REG DENALI_PHY_1876
+#define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_1__FLD LPDDR4__DENALI_PHY_1876__PHY_ADRCTL_MSTR_DLY_ENC_SEL_1
+
+#define LPDDR4__DENALI_PHY_1876__PHY_ADRCTL_MSTR_DLY_ENC_SEL_2_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_1876__PHY_ADRCTL_MSTR_DLY_ENC_SEL_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1876__PHY_ADRCTL_MSTR_DLY_ENC_SEL_2_WIDTH 2U
+#define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_2__REG DENALI_PHY_1876
+#define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_2__FLD LPDDR4__DENALI_PHY_1876__PHY_ADRCTL_MSTR_DLY_ENC_SEL_2
+
+#define LPDDR4__DENALI_PHY_1876__PHY_ADRCTL_MSTR_DLY_ENC_SEL_3_MASK 0x03000000U
+#define LPDDR4__DENALI_PHY_1876__PHY_ADRCTL_MSTR_DLY_ENC_SEL_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1876__PHY_ADRCTL_MSTR_DLY_ENC_SEL_3_WIDTH 2U
+#define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_3__REG DENALI_PHY_1876
+#define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_3__FLD LPDDR4__DENALI_PHY_1876__PHY_ADRCTL_MSTR_DLY_ENC_SEL_3
+
+#define LPDDR4__DENALI_PHY_1877_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1877_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1877__PHY_DDL_AC_ENABLE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1877__PHY_DDL_AC_ENABLE_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1877__PHY_DDL_AC_ENABLE_WIDTH 32U
+#define LPDDR4__PHY_DDL_AC_ENABLE__REG DENALI_PHY_1877
+#define LPDDR4__PHY_DDL_AC_ENABLE__FLD LPDDR4__DENALI_PHY_1877__PHY_DDL_AC_ENABLE
+
+#define LPDDR4__DENALI_PHY_1878_READ_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_1878_WRITE_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_1878__PHY_DDL_AC_MODE_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_1878__PHY_DDL_AC_MODE_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1878__PHY_DDL_AC_MODE_WIDTH 26U
+#define LPDDR4__PHY_DDL_AC_MODE__REG DENALI_PHY_1878
+#define LPDDR4__PHY_DDL_AC_MODE__FLD LPDDR4__DENALI_PHY_1878__PHY_DDL_AC_MODE
+
+#define LPDDR4__DENALI_PHY_1879_READ_MASK 0x00FF073FU
+#define LPDDR4__DENALI_PHY_1879_WRITE_MASK 0x00FF073FU
+#define LPDDR4__DENALI_PHY_1879__PHY_DDL_AC_MASK_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_1879__PHY_DDL_AC_MASK_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1879__PHY_DDL_AC_MASK_WIDTH 6U
+#define LPDDR4__PHY_DDL_AC_MASK__REG DENALI_PHY_1879
+#define LPDDR4__PHY_DDL_AC_MASK__FLD LPDDR4__DENALI_PHY_1879__PHY_DDL_AC_MASK
+
+#define LPDDR4__DENALI_PHY_1879__PHY_INIT_UPDATE_CONFIG_MASK 0x00000700U
+#define LPDDR4__DENALI_PHY_1879__PHY_INIT_UPDATE_CONFIG_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1879__PHY_INIT_UPDATE_CONFIG_WIDTH 3U
+#define LPDDR4__PHY_INIT_UPDATE_CONFIG__REG DENALI_PHY_1879
+#define LPDDR4__PHY_INIT_UPDATE_CONFIG__FLD LPDDR4__DENALI_PHY_1879__PHY_INIT_UPDATE_CONFIG
+
+#define LPDDR4__DENALI_PHY_1879__PHY_DDL_TRACK_UPD_THRESHOLD_AC_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_1879__PHY_DDL_TRACK_UPD_THRESHOLD_AC_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1879__PHY_DDL_TRACK_UPD_THRESHOLD_AC_WIDTH 8U
+#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_AC__REG DENALI_PHY_1879
+#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_AC__FLD LPDDR4__DENALI_PHY_1879__PHY_DDL_TRACK_UPD_THRESHOLD_AC
+
+#define LPDDR4__DENALI_PHY_1880_READ_MASK 0x0707FFFFU
+#define LPDDR4__DENALI_PHY_1880_WRITE_MASK 0x0707FFFFU
+#define LPDDR4__DENALI_PHY_1880__PHY_CA_PARITY_ERR_PULSE_MIN_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1880__PHY_CA_PARITY_ERR_PULSE_MIN_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1880__PHY_CA_PARITY_ERR_PULSE_MIN_WIDTH 16U
+#define LPDDR4__PHY_CA_PARITY_ERR_PULSE_MIN__REG DENALI_PHY_1880
+#define LPDDR4__PHY_CA_PARITY_ERR_PULSE_MIN__FLD LPDDR4__DENALI_PHY_1880__PHY_CA_PARITY_ERR_PULSE_MIN
+
+#define LPDDR4__DENALI_PHY_1880__PHY_ERR_MASK_EN_MASK 0x00070000U
+#define LPDDR4__DENALI_PHY_1880__PHY_ERR_MASK_EN_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1880__PHY_ERR_MASK_EN_WIDTH 3U
+#define LPDDR4__PHY_ERR_MASK_EN__REG DENALI_PHY_1880
+#define LPDDR4__PHY_ERR_MASK_EN__FLD LPDDR4__DENALI_PHY_1880__PHY_ERR_MASK_EN
+
+#define LPDDR4__DENALI_PHY_1880__PHY_ERR_STATUS_MASK 0x07000000U
+#define LPDDR4__DENALI_PHY_1880__PHY_ERR_STATUS_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1880__PHY_ERR_STATUS_WIDTH 3U
+#define LPDDR4__PHY_ERR_STATUS__REG DENALI_PHY_1880
+#define LPDDR4__PHY_ERR_STATUS__FLD LPDDR4__DENALI_PHY_1880__PHY_ERR_STATUS
+
+#define LPDDR4__DENALI_PHY_1881_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1881_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1881__PHY_DS0_DQS_ERR_COUNTER_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1881__PHY_DS0_DQS_ERR_COUNTER_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1881__PHY_DS0_DQS_ERR_COUNTER_WIDTH 32U
+#define LPDDR4__PHY_DS0_DQS_ERR_COUNTER__REG DENALI_PHY_1881
+#define LPDDR4__PHY_DS0_DQS_ERR_COUNTER__FLD LPDDR4__DENALI_PHY_1881__PHY_DS0_DQS_ERR_COUNTER
+
+#define LPDDR4__DENALI_PHY_1882_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1882_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1882__PHY_DS1_DQS_ERR_COUNTER_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1882__PHY_DS1_DQS_ERR_COUNTER_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1882__PHY_DS1_DQS_ERR_COUNTER_WIDTH 32U
+#define LPDDR4__PHY_DS1_DQS_ERR_COUNTER__REG DENALI_PHY_1882
+#define LPDDR4__PHY_DS1_DQS_ERR_COUNTER__FLD LPDDR4__DENALI_PHY_1882__PHY_DS1_DQS_ERR_COUNTER
+
+#define LPDDR4__DENALI_PHY_1883_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1883_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1883__PHY_DS2_DQS_ERR_COUNTER_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1883__PHY_DS2_DQS_ERR_COUNTER_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1883__PHY_DS2_DQS_ERR_COUNTER_WIDTH 32U
+#define LPDDR4__PHY_DS2_DQS_ERR_COUNTER__REG DENALI_PHY_1883
+#define LPDDR4__PHY_DS2_DQS_ERR_COUNTER__FLD LPDDR4__DENALI_PHY_1883__PHY_DS2_DQS_ERR_COUNTER
+
+#define LPDDR4__DENALI_PHY_1884_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1884_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1884__PHY_DS3_DQS_ERR_COUNTER_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1884__PHY_DS3_DQS_ERR_COUNTER_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1884__PHY_DS3_DQS_ERR_COUNTER_WIDTH 32U
+#define LPDDR4__PHY_DS3_DQS_ERR_COUNTER__REG DENALI_PHY_1884
+#define LPDDR4__PHY_DS3_DQS_ERR_COUNTER__FLD LPDDR4__DENALI_PHY_1884__PHY_DS3_DQS_ERR_COUNTER
+
+#define LPDDR4__DENALI_PHY_1885_READ_MASK 0x0F0FFF03U
+#define LPDDR4__DENALI_PHY_1885_WRITE_MASK 0x0F0FFF03U
+#define LPDDR4__DENALI_PHY_1885__PHY_DLL_RST_EN_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_1885__PHY_DLL_RST_EN_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1885__PHY_DLL_RST_EN_WIDTH 2U
+#define LPDDR4__PHY_DLL_RST_EN__REG DENALI_PHY_1885
+#define LPDDR4__PHY_DLL_RST_EN__FLD LPDDR4__DENALI_PHY_1885__PHY_DLL_RST_EN
+
+#define LPDDR4__DENALI_PHY_1885__PHY_AC_INIT_COMPLETE_OBS_MASK 0x000FFF00U
+#define LPDDR4__DENALI_PHY_1885__PHY_AC_INIT_COMPLETE_OBS_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1885__PHY_AC_INIT_COMPLETE_OBS_WIDTH 12U
+#define LPDDR4__PHY_AC_INIT_COMPLETE_OBS__REG DENALI_PHY_1885
+#define LPDDR4__PHY_AC_INIT_COMPLETE_OBS__FLD LPDDR4__DENALI_PHY_1885__PHY_AC_INIT_COMPLETE_OBS
+
+#define LPDDR4__DENALI_PHY_1885__PHY_DS_INIT_COMPLETE_OBS_MASK 0x0F000000U
+#define LPDDR4__DENALI_PHY_1885__PHY_DS_INIT_COMPLETE_OBS_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1885__PHY_DS_INIT_COMPLETE_OBS_WIDTH 4U
+#define LPDDR4__PHY_DS_INIT_COMPLETE_OBS__REG DENALI_PHY_1885
+#define LPDDR4__PHY_DS_INIT_COMPLETE_OBS__FLD LPDDR4__DENALI_PHY_1885__PHY_DS_INIT_COMPLETE_OBS
+
+#define LPDDR4__DENALI_PHY_1886_READ_MASK 0x1F010101U
+#define LPDDR4__DENALI_PHY_1886_WRITE_MASK 0x1F010101U
+#define LPDDR4__DENALI_PHY_1886__PHY_UPDATE_MASK_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1886__PHY_UPDATE_MASK_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1886__PHY_UPDATE_MASK_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1886__PHY_UPDATE_MASK_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1886__PHY_UPDATE_MASK_WOSET 0U
+#define LPDDR4__PHY_UPDATE_MASK__REG DENALI_PHY_1886
+#define LPDDR4__PHY_UPDATE_MASK__FLD LPDDR4__DENALI_PHY_1886__PHY_UPDATE_MASK
+
+#define LPDDR4__DENALI_PHY_1886__PHY_ERR_IE_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_1886__PHY_ERR_IE_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1886__PHY_ERR_IE_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1886__PHY_ERR_IE_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1886__PHY_ERR_IE_WOSET 0U
+#define LPDDR4__PHY_ERR_IE__REG DENALI_PHY_1886
+#define LPDDR4__PHY_ERR_IE__FLD LPDDR4__DENALI_PHY_1886__PHY_ERR_IE
+
+#define LPDDR4__DENALI_PHY_1886__PHY_AC_DCC_RXCAL_CTRL_GATE_DISABLE_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_1886__PHY_AC_DCC_RXCAL_CTRL_GATE_DISABLE_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1886__PHY_AC_DCC_RXCAL_CTRL_GATE_DISABLE_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1886__PHY_AC_DCC_RXCAL_CTRL_GATE_DISABLE_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1886__PHY_AC_DCC_RXCAL_CTRL_GATE_DISABLE_WOSET 0U
+#define LPDDR4__PHY_AC_DCC_RXCAL_CTRL_GATE_DISABLE__REG DENALI_PHY_1886
+#define LPDDR4__PHY_AC_DCC_RXCAL_CTRL_GATE_DISABLE__FLD LPDDR4__DENALI_PHY_1886__PHY_AC_DCC_RXCAL_CTRL_GATE_DISABLE
+
+#define LPDDR4__DENALI_PHY_1886__PHY_GRP_SLV_DLY_ENC_OBS_SELECT_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_1886__PHY_GRP_SLV_DLY_ENC_OBS_SELECT_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1886__PHY_GRP_SLV_DLY_ENC_OBS_SELECT_WIDTH 5U
+#define LPDDR4__PHY_GRP_SLV_DLY_ENC_OBS_SELECT__REG DENALI_PHY_1886
+#define LPDDR4__PHY_GRP_SLV_DLY_ENC_OBS_SELECT__FLD LPDDR4__DENALI_PHY_1886__PHY_GRP_SLV_DLY_ENC_OBS_SELECT
+
+#define LPDDR4__DENALI_PHY_1887_READ_MASK 0x0707FF0FU
+#define LPDDR4__DENALI_PHY_1887_WRITE_MASK 0x0707FF0FU
+#define LPDDR4__DENALI_PHY_1887__PHY_GRP_SHIFT_OBS_SELECT_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_1887__PHY_GRP_SHIFT_OBS_SELECT_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1887__PHY_GRP_SHIFT_OBS_SELECT_WIDTH 4U
+#define LPDDR4__PHY_GRP_SHIFT_OBS_SELECT__REG DENALI_PHY_1887
+#define LPDDR4__PHY_GRP_SHIFT_OBS_SELECT__FLD LPDDR4__DENALI_PHY_1887__PHY_GRP_SHIFT_OBS_SELECT
+
+#define LPDDR4__DENALI_PHY_1887__PHY_GRP_SLV_DLY_ENC_OBS_MASK 0x0007FF00U
+#define LPDDR4__DENALI_PHY_1887__PHY_GRP_SLV_DLY_ENC_OBS_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1887__PHY_GRP_SLV_DLY_ENC_OBS_WIDTH 11U
+#define LPDDR4__PHY_GRP_SLV_DLY_ENC_OBS__REG DENALI_PHY_1887
+#define LPDDR4__PHY_GRP_SLV_DLY_ENC_OBS__FLD LPDDR4__DENALI_PHY_1887__PHY_GRP_SLV_DLY_ENC_OBS
+
+#define LPDDR4__DENALI_PHY_1887__PHY_GRP_SHIFT_OBS_MASK 0x07000000U
+#define LPDDR4__DENALI_PHY_1887__PHY_GRP_SHIFT_OBS_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1887__PHY_GRP_SHIFT_OBS_WIDTH 3U
+#define LPDDR4__PHY_GRP_SHIFT_OBS__REG DENALI_PHY_1887
+#define LPDDR4__PHY_GRP_SHIFT_OBS__FLD LPDDR4__DENALI_PHY_1887__PHY_GRP_SHIFT_OBS
+
+#define LPDDR4__DENALI_PHY_1888_READ_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1888_WRITE_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1888__PHY_PAD_CAL_IO_CFG_0_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1888__PHY_PAD_CAL_IO_CFG_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1888__PHY_PAD_CAL_IO_CFG_0_WIDTH 18U
+#define LPDDR4__PHY_PAD_CAL_IO_CFG_0__REG DENALI_PHY_1888
+#define LPDDR4__PHY_PAD_CAL_IO_CFG_0__FLD LPDDR4__DENALI_PHY_1888__PHY_PAD_CAL_IO_CFG_0
+
+#define LPDDR4__DENALI_PHY_1889_READ_MASK 0x0703FFFFU
+#define LPDDR4__DENALI_PHY_1889_WRITE_MASK 0x0703FFFFU
+#define LPDDR4__DENALI_PHY_1889__PHY_PAD_ACS_IO_CFG_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1889__PHY_PAD_ACS_IO_CFG_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1889__PHY_PAD_ACS_IO_CFG_WIDTH 18U
+#define LPDDR4__PHY_PAD_ACS_IO_CFG__REG DENALI_PHY_1889
+#define LPDDR4__PHY_PAD_ACS_IO_CFG__FLD LPDDR4__DENALI_PHY_1889__PHY_PAD_ACS_IO_CFG
+
+#define LPDDR4__DENALI_PHY_1889__PHY_PAD_ACS_RX_PCLK_CLK_SEL_MASK 0x07000000U
+#define LPDDR4__DENALI_PHY_1889__PHY_PAD_ACS_RX_PCLK_CLK_SEL_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1889__PHY_PAD_ACS_RX_PCLK_CLK_SEL_WIDTH 3U
+#define LPDDR4__PHY_PAD_ACS_RX_PCLK_CLK_SEL__REG DENALI_PHY_1889
+#define LPDDR4__PHY_PAD_ACS_RX_PCLK_CLK_SEL__FLD LPDDR4__DENALI_PHY_1889__PHY_PAD_ACS_RX_PCLK_CLK_SEL
+
+#define LPDDR4__DENALI_PHY_1890_READ_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1890_WRITE_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1890__PHY_PLL_BYPASS_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1890__PHY_PLL_BYPASS_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1890__PHY_PLL_BYPASS_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1890__PHY_PLL_BYPASS_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1890__PHY_PLL_BYPASS_WOSET 0U
+#define LPDDR4__PHY_PLL_BYPASS__REG DENALI_PHY_1890
+#define LPDDR4__PHY_PLL_BYPASS__FLD LPDDR4__DENALI_PHY_1890__PHY_PLL_BYPASS
+
+#define LPDDR4__DENALI_PHY_1891_READ_MASK 0x00011FFFU
+#define LPDDR4__DENALI_PHY_1891_WRITE_MASK 0x00011FFFU
+#define LPDDR4__DENALI_PHY_1891__PHY_PLL_CTRL_MASK 0x00001FFFU
+#define LPDDR4__DENALI_PHY_1891__PHY_PLL_CTRL_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1891__PHY_PLL_CTRL_WIDTH 13U
+#define LPDDR4__PHY_PLL_CTRL__REG DENALI_PHY_1891
+#define LPDDR4__PHY_PLL_CTRL__FLD LPDDR4__DENALI_PHY_1891__PHY_PLL_CTRL
+
+#define LPDDR4__DENALI_PHY_1891__PHY_LOW_FREQ_SEL_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_1891__PHY_LOW_FREQ_SEL_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1891__PHY_LOW_FREQ_SEL_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1891__PHY_LOW_FREQ_SEL_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1891__PHY_LOW_FREQ_SEL_WOSET 0U
+#define LPDDR4__PHY_LOW_FREQ_SEL__REG DENALI_PHY_1891
+#define LPDDR4__PHY_LOW_FREQ_SEL__FLD LPDDR4__DENALI_PHY_1891__PHY_LOW_FREQ_SEL
+
+#define LPDDR4__DENALI_PHY_1892_READ_MASK 0x0F0F0FFFU
+#define LPDDR4__DENALI_PHY_1892_WRITE_MASK 0x0F0F0FFFU
+#define LPDDR4__DENALI_PHY_1892__PHY_PAD_VREF_CTRL_AC_MASK 0x00000FFFU
+#define LPDDR4__DENALI_PHY_1892__PHY_PAD_VREF_CTRL_AC_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1892__PHY_PAD_VREF_CTRL_AC_WIDTH 12U
+#define LPDDR4__PHY_PAD_VREF_CTRL_AC__REG DENALI_PHY_1892
+#define LPDDR4__PHY_PAD_VREF_CTRL_AC__FLD LPDDR4__DENALI_PHY_1892__PHY_PAD_VREF_CTRL_AC
+
+#define LPDDR4__DENALI_PHY_1892__PHY_CSLVL_CAPTURE_CNT_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_1892__PHY_CSLVL_CAPTURE_CNT_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1892__PHY_CSLVL_CAPTURE_CNT_WIDTH 4U
+#define LPDDR4__PHY_CSLVL_CAPTURE_CNT__REG DENALI_PHY_1892
+#define LPDDR4__PHY_CSLVL_CAPTURE_CNT__FLD LPDDR4__DENALI_PHY_1892__PHY_CSLVL_CAPTURE_CNT
+
+#define LPDDR4__DENALI_PHY_1892__PHY_CSLVL_DLY_STEP_MASK 0x0F000000U
+#define LPDDR4__DENALI_PHY_1892__PHY_CSLVL_DLY_STEP_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1892__PHY_CSLVL_DLY_STEP_WIDTH 4U
+#define LPDDR4__PHY_CSLVL_DLY_STEP__REG DENALI_PHY_1892
+#define LPDDR4__PHY_CSLVL_DLY_STEP__FLD LPDDR4__DENALI_PHY_1892__PHY_CSLVL_DLY_STEP
+
+#define LPDDR4__DENALI_PHY_1893_READ_MASK 0x010103FFU
+#define LPDDR4__DENALI_PHY_1893_WRITE_MASK 0x010103FFU
+#define LPDDR4__DENALI_PHY_1893__PHY_SW_CSLVL_DVW_MIN_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_1893__PHY_SW_CSLVL_DVW_MIN_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1893__PHY_SW_CSLVL_DVW_MIN_WIDTH 10U
+#define LPDDR4__PHY_SW_CSLVL_DVW_MIN__REG DENALI_PHY_1893
+#define LPDDR4__PHY_SW_CSLVL_DVW_MIN__FLD LPDDR4__DENALI_PHY_1893__PHY_SW_CSLVL_DVW_MIN
+
+#define LPDDR4__DENALI_PHY_1893__PHY_SW_CSLVL_DVW_MIN_EN_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_1893__PHY_SW_CSLVL_DVW_MIN_EN_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1893__PHY_SW_CSLVL_DVW_MIN_EN_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1893__PHY_SW_CSLVL_DVW_MIN_EN_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1893__PHY_SW_CSLVL_DVW_MIN_EN_WOSET 0U
+#define LPDDR4__PHY_SW_CSLVL_DVW_MIN_EN__REG DENALI_PHY_1893
+#define LPDDR4__PHY_SW_CSLVL_DVW_MIN_EN__FLD LPDDR4__DENALI_PHY_1893__PHY_SW_CSLVL_DVW_MIN_EN
+
+#define LPDDR4__DENALI_PHY_1893__PHY_LVL_MEAS_DLY_STEP_ENABLE_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_1893__PHY_LVL_MEAS_DLY_STEP_ENABLE_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1893__PHY_LVL_MEAS_DLY_STEP_ENABLE_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1893__PHY_LVL_MEAS_DLY_STEP_ENABLE_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1893__PHY_LVL_MEAS_DLY_STEP_ENABLE_WOSET 0U
+#define LPDDR4__PHY_LVL_MEAS_DLY_STEP_ENABLE__REG DENALI_PHY_1893
+#define LPDDR4__PHY_LVL_MEAS_DLY_STEP_ENABLE__FLD LPDDR4__DENALI_PHY_1893__PHY_LVL_MEAS_DLY_STEP_ENABLE
+
+#define LPDDR4__DENALI_PHY_1894_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1894_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1894__PHY_GRP0_SLAVE_DELAY_0_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1894__PHY_GRP0_SLAVE_DELAY_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1894__PHY_GRP0_SLAVE_DELAY_0_WIDTH 11U
+#define LPDDR4__PHY_GRP0_SLAVE_DELAY_0__REG DENALI_PHY_1894
+#define LPDDR4__PHY_GRP0_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1894__PHY_GRP0_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_1894__PHY_GRP1_SLAVE_DELAY_0_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_1894__PHY_GRP1_SLAVE_DELAY_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1894__PHY_GRP1_SLAVE_DELAY_0_WIDTH 11U
+#define LPDDR4__PHY_GRP1_SLAVE_DELAY_0__REG DENALI_PHY_1894
+#define LPDDR4__PHY_GRP1_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1894__PHY_GRP1_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_1895_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1895_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1895__PHY_GRP2_SLAVE_DELAY_0_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1895__PHY_GRP2_SLAVE_DELAY_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1895__PHY_GRP2_SLAVE_DELAY_0_WIDTH 11U
+#define LPDDR4__PHY_GRP2_SLAVE_DELAY_0__REG DENALI_PHY_1895
+#define LPDDR4__PHY_GRP2_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1895__PHY_GRP2_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_1895__PHY_GRP3_SLAVE_DELAY_0_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_1895__PHY_GRP3_SLAVE_DELAY_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1895__PHY_GRP3_SLAVE_DELAY_0_WIDTH 11U
+#define LPDDR4__PHY_GRP3_SLAVE_DELAY_0__REG DENALI_PHY_1895
+#define LPDDR4__PHY_GRP3_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1895__PHY_GRP3_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_1896_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1896_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1896__PHY_GRP0_SLAVE_DELAY_1_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1896__PHY_GRP0_SLAVE_DELAY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1896__PHY_GRP0_SLAVE_DELAY_1_WIDTH 11U
+#define LPDDR4__PHY_GRP0_SLAVE_DELAY_1__REG DENALI_PHY_1896
+#define LPDDR4__PHY_GRP0_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1896__PHY_GRP0_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_1896__PHY_GRP1_SLAVE_DELAY_1_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_1896__PHY_GRP1_SLAVE_DELAY_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1896__PHY_GRP1_SLAVE_DELAY_1_WIDTH 11U
+#define LPDDR4__PHY_GRP1_SLAVE_DELAY_1__REG DENALI_PHY_1896
+#define LPDDR4__PHY_GRP1_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1896__PHY_GRP1_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_1897_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1897_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1897__PHY_GRP2_SLAVE_DELAY_1_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1897__PHY_GRP2_SLAVE_DELAY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1897__PHY_GRP2_SLAVE_DELAY_1_WIDTH 11U
+#define LPDDR4__PHY_GRP2_SLAVE_DELAY_1__REG DENALI_PHY_1897
+#define LPDDR4__PHY_GRP2_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1897__PHY_GRP2_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_1897__PHY_GRP3_SLAVE_DELAY_1_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_1897__PHY_GRP3_SLAVE_DELAY_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1897__PHY_GRP3_SLAVE_DELAY_1_WIDTH 11U
+#define LPDDR4__PHY_GRP3_SLAVE_DELAY_1__REG DENALI_PHY_1897
+#define LPDDR4__PHY_GRP3_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1897__PHY_GRP3_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_1898_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1898_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1898__PHY_GRP0_SLAVE_DELAY_2_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1898__PHY_GRP0_SLAVE_DELAY_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1898__PHY_GRP0_SLAVE_DELAY_2_WIDTH 11U
+#define LPDDR4__PHY_GRP0_SLAVE_DELAY_2__REG DENALI_PHY_1898
+#define LPDDR4__PHY_GRP0_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1898__PHY_GRP0_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_1898__PHY_GRP1_SLAVE_DELAY_2_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_1898__PHY_GRP1_SLAVE_DELAY_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1898__PHY_GRP1_SLAVE_DELAY_2_WIDTH 11U
+#define LPDDR4__PHY_GRP1_SLAVE_DELAY_2__REG DENALI_PHY_1898
+#define LPDDR4__PHY_GRP1_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1898__PHY_GRP1_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_1899_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1899_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1899__PHY_GRP2_SLAVE_DELAY_2_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1899__PHY_GRP2_SLAVE_DELAY_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1899__PHY_GRP2_SLAVE_DELAY_2_WIDTH 11U
+#define LPDDR4__PHY_GRP2_SLAVE_DELAY_2__REG DENALI_PHY_1899
+#define LPDDR4__PHY_GRP2_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1899__PHY_GRP2_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_1899__PHY_GRP3_SLAVE_DELAY_2_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_1899__PHY_GRP3_SLAVE_DELAY_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1899__PHY_GRP3_SLAVE_DELAY_2_WIDTH 11U
+#define LPDDR4__PHY_GRP3_SLAVE_DELAY_2__REG DENALI_PHY_1899
+#define LPDDR4__PHY_GRP3_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1899__PHY_GRP3_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_1900_READ_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1900_WRITE_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1900__PHY_GRP0_SLAVE_DELAY_3_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1900__PHY_GRP0_SLAVE_DELAY_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1900__PHY_GRP0_SLAVE_DELAY_3_WIDTH 11U
+#define LPDDR4__PHY_GRP0_SLAVE_DELAY_3__REG DENALI_PHY_1900
+#define LPDDR4__PHY_GRP0_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_1900__PHY_GRP0_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_1901_READ_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1901_WRITE_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1901__PHY_GRP1_SLAVE_DELAY_3_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1901__PHY_GRP1_SLAVE_DELAY_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1901__PHY_GRP1_SLAVE_DELAY_3_WIDTH 11U
+#define LPDDR4__PHY_GRP1_SLAVE_DELAY_3__REG DENALI_PHY_1901
+#define LPDDR4__PHY_GRP1_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_1901__PHY_GRP1_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_1902_READ_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1902_WRITE_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1902__PHY_GRP2_SLAVE_DELAY_3_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1902__PHY_GRP2_SLAVE_DELAY_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1902__PHY_GRP2_SLAVE_DELAY_3_WIDTH 11U
+#define LPDDR4__PHY_GRP2_SLAVE_DELAY_3__REG DENALI_PHY_1902
+#define LPDDR4__PHY_GRP2_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_1902__PHY_GRP2_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_1903_READ_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1903_WRITE_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1903__PHY_GRP3_SLAVE_DELAY_3_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1903__PHY_GRP3_SLAVE_DELAY_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1903__PHY_GRP3_SLAVE_DELAY_3_WIDTH 11U
+#define LPDDR4__PHY_GRP3_SLAVE_DELAY_3__REG DENALI_PHY_1903
+#define LPDDR4__PHY_GRP3_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_1903__PHY_GRP3_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_1904_READ_MASK 0x00000007U
+#define LPDDR4__DENALI_PHY_1904_WRITE_MASK 0x00000007U
+#define LPDDR4__DENALI_PHY_1904__PHY_CLK_DC_CAL_CLK_SEL_MASK 0x00000007U
+#define LPDDR4__DENALI_PHY_1904__PHY_CLK_DC_CAL_CLK_SEL_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1904__PHY_CLK_DC_CAL_CLK_SEL_WIDTH 3U
+#define LPDDR4__PHY_CLK_DC_CAL_CLK_SEL__REG DENALI_PHY_1904
+#define LPDDR4__PHY_CLK_DC_CAL_CLK_SEL__FLD LPDDR4__DENALI_PHY_1904__PHY_CLK_DC_CAL_CLK_SEL
+
+#define LPDDR4__DENALI_PHY_1905_READ_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1905_WRITE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1905__PHY_PAD_FDBK_DRIVE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1905__PHY_PAD_FDBK_DRIVE_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1905__PHY_PAD_FDBK_DRIVE_WIDTH 30U
+#define LPDDR4__PHY_PAD_FDBK_DRIVE__REG DENALI_PHY_1905
+#define LPDDR4__PHY_PAD_FDBK_DRIVE__FLD LPDDR4__DENALI_PHY_1905__PHY_PAD_FDBK_DRIVE
+
+#define LPDDR4__DENALI_PHY_1906_READ_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1906_WRITE_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1906__PHY_PAD_FDBK_DRIVE2_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1906__PHY_PAD_FDBK_DRIVE2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1906__PHY_PAD_FDBK_DRIVE2_WIDTH 18U
+#define LPDDR4__PHY_PAD_FDBK_DRIVE2__REG DENALI_PHY_1906
+#define LPDDR4__PHY_PAD_FDBK_DRIVE2__FLD LPDDR4__DENALI_PHY_1906__PHY_PAD_FDBK_DRIVE2
+
+#define LPDDR4__DENALI_PHY_1907_READ_MASK 0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_1907_WRITE_MASK 0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_1907__PHY_PAD_DATA_DRIVE_MASK 0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_1907__PHY_PAD_DATA_DRIVE_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1907__PHY_PAD_DATA_DRIVE_WIDTH 31U
+#define LPDDR4__PHY_PAD_DATA_DRIVE__REG DENALI_PHY_1907
+#define LPDDR4__PHY_PAD_DATA_DRIVE__FLD LPDDR4__DENALI_PHY_1907__PHY_PAD_DATA_DRIVE
+
+#define LPDDR4__DENALI_PHY_1908_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1908_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1908__PHY_PAD_DQS_DRIVE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1908__PHY_PAD_DQS_DRIVE_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1908__PHY_PAD_DQS_DRIVE_WIDTH 32U
+#define LPDDR4__PHY_PAD_DQS_DRIVE__REG DENALI_PHY_1908
+#define LPDDR4__PHY_PAD_DQS_DRIVE__FLD LPDDR4__DENALI_PHY_1908__PHY_PAD_DQS_DRIVE
+
+#define LPDDR4__DENALI_PHY_1909_READ_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1909_WRITE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1909__PHY_PAD_ADDR_DRIVE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1909__PHY_PAD_ADDR_DRIVE_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1909__PHY_PAD_ADDR_DRIVE_WIDTH 30U
+#define LPDDR4__PHY_PAD_ADDR_DRIVE__REG DENALI_PHY_1909
+#define LPDDR4__PHY_PAD_ADDR_DRIVE__FLD LPDDR4__DENALI_PHY_1909__PHY_PAD_ADDR_DRIVE
+
+#define LPDDR4__DENALI_PHY_1910_READ_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1910_WRITE_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1910__PHY_PAD_ADDR_DRIVE2_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1910__PHY_PAD_ADDR_DRIVE2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1910__PHY_PAD_ADDR_DRIVE2_WIDTH 28U
+#define LPDDR4__PHY_PAD_ADDR_DRIVE2__REG DENALI_PHY_1910
+#define LPDDR4__PHY_PAD_ADDR_DRIVE2__FLD LPDDR4__DENALI_PHY_1910__PHY_PAD_ADDR_DRIVE2
+
+#define LPDDR4__DENALI_PHY_1911_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1911_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1911__PHY_PAD_CLK_DRIVE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1911__PHY_PAD_CLK_DRIVE_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1911__PHY_PAD_CLK_DRIVE_WIDTH 32U
+#define LPDDR4__PHY_PAD_CLK_DRIVE__REG DENALI_PHY_1911
+#define LPDDR4__PHY_PAD_CLK_DRIVE__FLD LPDDR4__DENALI_PHY_1911__PHY_PAD_CLK_DRIVE
+
+#define LPDDR4__DENALI_PHY_1912_READ_MASK 0x0007FFFFU
+#define LPDDR4__DENALI_PHY_1912_WRITE_MASK 0x0007FFFFU
+#define LPDDR4__DENALI_PHY_1912__PHY_PAD_CLK_DRIVE2_MASK 0x0007FFFFU
+#define LPDDR4__DENALI_PHY_1912__PHY_PAD_CLK_DRIVE2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1912__PHY_PAD_CLK_DRIVE2_WIDTH 19U
+#define LPDDR4__PHY_PAD_CLK_DRIVE2__REG DENALI_PHY_1912
+#define LPDDR4__PHY_PAD_CLK_DRIVE2__FLD LPDDR4__DENALI_PHY_1912__PHY_PAD_CLK_DRIVE2
+
+#define LPDDR4__DENALI_PHY_1913_READ_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1913_WRITE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1913__PHY_PAD_ERR_DRIVE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1913__PHY_PAD_ERR_DRIVE_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1913__PHY_PAD_ERR_DRIVE_WIDTH 30U
+#define LPDDR4__PHY_PAD_ERR_DRIVE__REG DENALI_PHY_1913
+#define LPDDR4__PHY_PAD_ERR_DRIVE__FLD LPDDR4__DENALI_PHY_1913__PHY_PAD_ERR_DRIVE
+
+#define LPDDR4__DENALI_PHY_1914_READ_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1914_WRITE_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1914__PHY_PAD_ERR_DRIVE2_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1914__PHY_PAD_ERR_DRIVE2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1914__PHY_PAD_ERR_DRIVE2_WIDTH 28U
+#define LPDDR4__PHY_PAD_ERR_DRIVE2__REG DENALI_PHY_1914
+#define LPDDR4__PHY_PAD_ERR_DRIVE2__FLD LPDDR4__DENALI_PHY_1914__PHY_PAD_ERR_DRIVE2
+
+#define LPDDR4__DENALI_PHY_1915_READ_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1915_WRITE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1915__PHY_PAD_CKE_DRIVE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1915__PHY_PAD_CKE_DRIVE_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1915__PHY_PAD_CKE_DRIVE_WIDTH 30U
+#define LPDDR4__PHY_PAD_CKE_DRIVE__REG DENALI_PHY_1915
+#define LPDDR4__PHY_PAD_CKE_DRIVE__FLD LPDDR4__DENALI_PHY_1915__PHY_PAD_CKE_DRIVE
+
+#define LPDDR4__DENALI_PHY_1916_READ_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1916_WRITE_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1916__PHY_PAD_CKE_DRIVE2_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1916__PHY_PAD_CKE_DRIVE2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1916__PHY_PAD_CKE_DRIVE2_WIDTH 28U
+#define LPDDR4__PHY_PAD_CKE_DRIVE2__REG DENALI_PHY_1916
+#define LPDDR4__PHY_PAD_CKE_DRIVE2__FLD LPDDR4__DENALI_PHY_1916__PHY_PAD_CKE_DRIVE2
+
+#define LPDDR4__DENALI_PHY_1917_READ_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1917_WRITE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1917__PHY_PAD_RST_DRIVE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1917__PHY_PAD_RST_DRIVE_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1917__PHY_PAD_RST_DRIVE_WIDTH 30U
+#define LPDDR4__PHY_PAD_RST_DRIVE__REG DENALI_PHY_1917
+#define LPDDR4__PHY_PAD_RST_DRIVE__FLD LPDDR4__DENALI_PHY_1917__PHY_PAD_RST_DRIVE
+
+#define LPDDR4__DENALI_PHY_1918_READ_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1918_WRITE_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1918__PHY_PAD_RST_DRIVE2_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1918__PHY_PAD_RST_DRIVE2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1918__PHY_PAD_RST_DRIVE2_WIDTH 28U
+#define LPDDR4__PHY_PAD_RST_DRIVE2__REG DENALI_PHY_1918
+#define LPDDR4__PHY_PAD_RST_DRIVE2__FLD LPDDR4__DENALI_PHY_1918__PHY_PAD_RST_DRIVE2
+
+#define LPDDR4__DENALI_PHY_1919_READ_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1919_WRITE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1919__PHY_PAD_CS_DRIVE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1919__PHY_PAD_CS_DRIVE_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1919__PHY_PAD_CS_DRIVE_WIDTH 30U
+#define LPDDR4__PHY_PAD_CS_DRIVE__REG DENALI_PHY_1919
+#define LPDDR4__PHY_PAD_CS_DRIVE__FLD LPDDR4__DENALI_PHY_1919__PHY_PAD_CS_DRIVE
+
+#define LPDDR4__DENALI_PHY_1920_READ_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1920_WRITE_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1920__PHY_PAD_CS_DRIVE2_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1920__PHY_PAD_CS_DRIVE2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1920__PHY_PAD_CS_DRIVE2_WIDTH 28U
+#define LPDDR4__PHY_PAD_CS_DRIVE2__REG DENALI_PHY_1920
+#define LPDDR4__PHY_PAD_CS_DRIVE2__FLD LPDDR4__DENALI_PHY_1920__PHY_PAD_CS_DRIVE2
+
+#define LPDDR4__DENALI_PHY_1921_READ_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1921_WRITE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1921__PHY_PAD_ODT_DRIVE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1921__PHY_PAD_ODT_DRIVE_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1921__PHY_PAD_ODT_DRIVE_WIDTH 30U
+#define LPDDR4__PHY_PAD_ODT_DRIVE__REG DENALI_PHY_1921
+#define LPDDR4__PHY_PAD_ODT_DRIVE__FLD LPDDR4__DENALI_PHY_1921__PHY_PAD_ODT_DRIVE
+
+#define LPDDR4__DENALI_PHY_1922_READ_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1922_WRITE_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1922__PHY_PAD_ODT_DRIVE2_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1922__PHY_PAD_ODT_DRIVE2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1922__PHY_PAD_ODT_DRIVE2_WIDTH 28U
+#define LPDDR4__PHY_PAD_ODT_DRIVE2__REG DENALI_PHY_1922
+#define LPDDR4__PHY_PAD_ODT_DRIVE2__FLD LPDDR4__DENALI_PHY_1922__PHY_PAD_ODT_DRIVE2
+
+#define LPDDR4__DENALI_PHY_1923_READ_MASK 0x7FFFFF07U
+#define LPDDR4__DENALI_PHY_1923_WRITE_MASK 0x7FFFFF07U
+#define LPDDR4__DENALI_PHY_1923__PHY_CAL_CLK_SELECT_0_MASK 0x00000007U
+#define LPDDR4__DENALI_PHY_1923__PHY_CAL_CLK_SELECT_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1923__PHY_CAL_CLK_SELECT_0_WIDTH 3U
+#define LPDDR4__PHY_CAL_CLK_SELECT_0__REG DENALI_PHY_1923
+#define LPDDR4__PHY_CAL_CLK_SELECT_0__FLD LPDDR4__DENALI_PHY_1923__PHY_CAL_CLK_SELECT_0
+
+#define LPDDR4__DENALI_PHY_1923__PHY_CAL_VREF_SWITCH_TIMER_0_MASK 0x00FFFF00U
+#define LPDDR4__DENALI_PHY_1923__PHY_CAL_VREF_SWITCH_TIMER_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1923__PHY_CAL_VREF_SWITCH_TIMER_0_WIDTH 16U
+#define LPDDR4__PHY_CAL_VREF_SWITCH_TIMER_0__REG DENALI_PHY_1923
+#define LPDDR4__PHY_CAL_VREF_SWITCH_TIMER_0__FLD LPDDR4__DENALI_PHY_1923__PHY_CAL_VREF_SWITCH_TIMER_0
+
+#define LPDDR4__DENALI_PHY_1923__PHY_CAL_SETTLING_PRD_0_MASK 0x7F000000U
+#define LPDDR4__DENALI_PHY_1923__PHY_CAL_SETTLING_PRD_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1923__PHY_CAL_SETTLING_PRD_0_WIDTH 7U
+#define LPDDR4__PHY_CAL_SETTLING_PRD_0__REG DENALI_PHY_1923
+#define LPDDR4__PHY_CAL_SETTLING_PRD_0__FLD LPDDR4__DENALI_PHY_1923__PHY_CAL_SETTLING_PRD_0
+
+#endif /* REG_LPDDR4_PHY_CORE_MACROS_H_ */
diff --git a/drivers/ram/k3-ddrss/am62a/lpddr4_pi_macros.h b/drivers/ram/k3-ddrss/am62a/lpddr4_pi_macros.h
new file mode 100644
index 00000000000..e36327f6445
--- /dev/null
+++ b/drivers/ram/k3-ddrss/am62a/lpddr4_pi_macros.h
@@ -0,0 +1,6892 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef REG_LPDDR4_PI_MACROS_H_
+#define REG_LPDDR4_PI_MACROS_H_
+
+#define LPDDR4__DENALI_PI_0_READ_MASK 0x00000F01U
+#define LPDDR4__DENALI_PI_0_WRITE_MASK 0x00000F01U
+#define LPDDR4__DENALI_PI_0__PI_START_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_0__PI_START_SHIFT 0U
+#define LPDDR4__DENALI_PI_0__PI_START_WIDTH 1U
+#define LPDDR4__DENALI_PI_0__PI_START_WOCLR 0U
+#define LPDDR4__DENALI_PI_0__PI_START_WOSET 0U
+#define LPDDR4__PI_START__REG DENALI_PI_0
+#define LPDDR4__PI_START__FLD LPDDR4__DENALI_PI_0__PI_START
+
+#define LPDDR4__DENALI_PI_0__PI_DRAM_CLASS_MASK 0x00000F00U
+#define LPDDR4__DENALI_PI_0__PI_DRAM_CLASS_SHIFT 8U
+#define LPDDR4__DENALI_PI_0__PI_DRAM_CLASS_WIDTH 4U
+#define LPDDR4__PI_DRAM_CLASS__REG DENALI_PI_0
+#define LPDDR4__PI_DRAM_CLASS__FLD LPDDR4__DENALI_PI_0__PI_DRAM_CLASS
+
+#define LPDDR4__DENALI_PI_1_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_1_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_1__PI_VERSION_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_1__PI_VERSION_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_1__PI_VERSION_0_WIDTH 32U
+#define LPDDR4__PI_VERSION_0__REG DENALI_PI_1
+#define LPDDR4__PI_VERSION_0__FLD LPDDR4__DENALI_PI_1__PI_VERSION_0
+
+#define LPDDR4__DENALI_PI_2_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_2_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_2__PI_VERSION_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_2__PI_VERSION_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_2__PI_VERSION_1_WIDTH 32U
+#define LPDDR4__PI_VERSION_1__REG DENALI_PI_2
+#define LPDDR4__PI_VERSION_1__FLD LPDDR4__DENALI_PI_2__PI_VERSION_1
+
+#define LPDDR4__DENALI_PI_3_READ_MASK 0x0101FFFFU
+#define LPDDR4__DENALI_PI_3_WRITE_MASK 0x0101FFFFU
+#define LPDDR4__DENALI_PI_3__PI_ID_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PI_3__PI_ID_SHIFT 0U
+#define LPDDR4__DENALI_PI_3__PI_ID_WIDTH 16U
+#define LPDDR4__PI_ID__REG DENALI_PI_3
+#define LPDDR4__PI_ID__FLD LPDDR4__DENALI_PI_3__PI_ID
+
+#define LPDDR4__DENALI_PI_3__PI_RELEASE_DFI_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_3__PI_RELEASE_DFI_SHIFT 16U
+#define LPDDR4__DENALI_PI_3__PI_RELEASE_DFI_WIDTH 1U
+#define LPDDR4__DENALI_PI_3__PI_RELEASE_DFI_WOCLR 0U
+#define LPDDR4__DENALI_PI_3__PI_RELEASE_DFI_WOSET 0U
+#define LPDDR4__PI_RELEASE_DFI__REG DENALI_PI_3
+#define LPDDR4__PI_RELEASE_DFI__FLD LPDDR4__DENALI_PI_3__PI_RELEASE_DFI
+
+#define LPDDR4__DENALI_PI_3__PI_NORMAL_LVL_SEQ_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_3__PI_NORMAL_LVL_SEQ_SHIFT 24U
+#define LPDDR4__DENALI_PI_3__PI_NORMAL_LVL_SEQ_WIDTH 1U
+#define LPDDR4__DENALI_PI_3__PI_NORMAL_LVL_SEQ_WOCLR 0U
+#define LPDDR4__DENALI_PI_3__PI_NORMAL_LVL_SEQ_WOSET 0U
+#define LPDDR4__PI_NORMAL_LVL_SEQ__REG DENALI_PI_3
+#define LPDDR4__PI_NORMAL_LVL_SEQ__FLD LPDDR4__DENALI_PI_3__PI_NORMAL_LVL_SEQ
+
+#define LPDDR4__DENALI_PI_4_READ_MASK 0xFFFF0301U
+#define LPDDR4__DENALI_PI_4_WRITE_MASK 0xFFFF0301U
+#define LPDDR4__DENALI_PI_4__PI_INIT_LVL_EN_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_4__PI_INIT_LVL_EN_SHIFT 0U
+#define LPDDR4__DENALI_PI_4__PI_INIT_LVL_EN_WIDTH 1U
+#define LPDDR4__DENALI_PI_4__PI_INIT_LVL_EN_WOCLR 0U
+#define LPDDR4__DENALI_PI_4__PI_INIT_LVL_EN_WOSET 0U
+#define LPDDR4__PI_INIT_LVL_EN__REG DENALI_PI_4
+#define LPDDR4__PI_INIT_LVL_EN__FLD LPDDR4__DENALI_PI_4__PI_INIT_LVL_EN
+
+#define LPDDR4__DENALI_PI_4__PI_NOTCARE_PHYUPD_MASK 0x00000300U
+#define LPDDR4__DENALI_PI_4__PI_NOTCARE_PHYUPD_SHIFT 8U
+#define LPDDR4__DENALI_PI_4__PI_NOTCARE_PHYUPD_WIDTH 2U
+#define LPDDR4__PI_NOTCARE_PHYUPD__REG DENALI_PI_4
+#define LPDDR4__PI_NOTCARE_PHYUPD__FLD LPDDR4__DENALI_PI_4__PI_NOTCARE_PHYUPD
+
+#define LPDDR4__DENALI_PI_4__PI_TCMD_GAP_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_PI_4__PI_TCMD_GAP_SHIFT 16U
+#define LPDDR4__DENALI_PI_4__PI_TCMD_GAP_WIDTH 16U
+#define LPDDR4__PI_TCMD_GAP__REG DENALI_PI_4
+#define LPDDR4__PI_TCMD_GAP__FLD LPDDR4__DENALI_PI_4__PI_TCMD_GAP
+
+#define LPDDR4__DENALI_PI_5_READ_MASK 0x030100FFU
+#define LPDDR4__DENALI_PI_5_WRITE_MASK 0x030100FFU
+#define LPDDR4__DENALI_PI_5__PI_RESERVED0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_5__PI_RESERVED0_SHIFT 0U
+#define LPDDR4__DENALI_PI_5__PI_RESERVED0_WIDTH 8U
+#define LPDDR4__PI_RESERVED0__REG DENALI_PI_5
+#define LPDDR4__PI_RESERVED0__FLD LPDDR4__DENALI_PI_5__PI_RESERVED0
+
+#define LPDDR4__DENALI_PI_5__PI_TRAIN_ALL_FREQ_REQ_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_5__PI_TRAIN_ALL_FREQ_REQ_SHIFT 8U
+#define LPDDR4__DENALI_PI_5__PI_TRAIN_ALL_FREQ_REQ_WIDTH 1U
+#define LPDDR4__DENALI_PI_5__PI_TRAIN_ALL_FREQ_REQ_WOCLR 0U
+#define LPDDR4__DENALI_PI_5__PI_TRAIN_ALL_FREQ_REQ_WOSET 0U
+#define LPDDR4__PI_TRAIN_ALL_FREQ_REQ__REG DENALI_PI_5
+#define LPDDR4__PI_TRAIN_ALL_FREQ_REQ__FLD LPDDR4__DENALI_PI_5__PI_TRAIN_ALL_FREQ_REQ
+
+#define LPDDR4__DENALI_PI_5__PI_DFI_VERSION_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_5__PI_DFI_VERSION_SHIFT 16U
+#define LPDDR4__DENALI_PI_5__PI_DFI_VERSION_WIDTH 1U
+#define LPDDR4__DENALI_PI_5__PI_DFI_VERSION_WOCLR 0U
+#define LPDDR4__DENALI_PI_5__PI_DFI_VERSION_WOSET 0U
+#define LPDDR4__PI_DFI_VERSION__REG DENALI_PI_5
+#define LPDDR4__PI_DFI_VERSION__FLD LPDDR4__DENALI_PI_5__PI_DFI_VERSION
+
+#define LPDDR4__DENALI_PI_5__PI_DFI_PHYMSTR_TYPE_MASK 0x03000000U
+#define LPDDR4__DENALI_PI_5__PI_DFI_PHYMSTR_TYPE_SHIFT 24U
+#define LPDDR4__DENALI_PI_5__PI_DFI_PHYMSTR_TYPE_WIDTH 2U
+#define LPDDR4__PI_DFI_PHYMSTR_TYPE__REG DENALI_PI_5
+#define LPDDR4__PI_DFI_PHYMSTR_TYPE__FLD LPDDR4__DENALI_PI_5__PI_DFI_PHYMSTR_TYPE
+
+#define LPDDR4__DENALI_PI_6_READ_MASK 0x00000101U
+#define LPDDR4__DENALI_PI_6_WRITE_MASK 0x00000101U
+#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_CS_STATE_R_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_CS_STATE_R_SHIFT 0U
+#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_CS_STATE_R_WIDTH 1U
+#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_CS_STATE_R_WOCLR 0U
+#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_CS_STATE_R_WOSET 0U
+#define LPDDR4__PI_DFI_PHYMSTR_CS_STATE_R__REG DENALI_PI_6
+#define LPDDR4__PI_DFI_PHYMSTR_CS_STATE_R__FLD LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_CS_STATE_R
+
+#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_STATE_SEL_R_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_STATE_SEL_R_SHIFT 8U
+#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_STATE_SEL_R_WIDTH 1U
+#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_STATE_SEL_R_WOCLR 0U
+#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_STATE_SEL_R_WOSET 0U
+#define LPDDR4__PI_DFI_PHYMSTR_STATE_SEL_R__REG DENALI_PI_6
+#define LPDDR4__PI_DFI_PHYMSTR_STATE_SEL_R__FLD LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_STATE_SEL_R
+
+#define LPDDR4__DENALI_PI_7_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_7_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_7__PI_TDFI_PHYMSTR_MAX_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_7__PI_TDFI_PHYMSTR_MAX_SHIFT 0U
+#define LPDDR4__DENALI_PI_7__PI_TDFI_PHYMSTR_MAX_WIDTH 32U
+#define LPDDR4__PI_TDFI_PHYMSTR_MAX__REG DENALI_PI_7
+#define LPDDR4__PI_TDFI_PHYMSTR_MAX__FLD LPDDR4__DENALI_PI_7__PI_TDFI_PHYMSTR_MAX
+
+#define LPDDR4__DENALI_PI_8_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PI_8_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PI_8__PI_TDFI_PHYMSTR_RESP_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PI_8__PI_TDFI_PHYMSTR_RESP_SHIFT 0U
+#define LPDDR4__DENALI_PI_8__PI_TDFI_PHYMSTR_RESP_WIDTH 20U
+#define LPDDR4__PI_TDFI_PHYMSTR_RESP__REG DENALI_PI_8
+#define LPDDR4__PI_TDFI_PHYMSTR_RESP__FLD LPDDR4__DENALI_PI_8__PI_TDFI_PHYMSTR_RESP
+
+#define LPDDR4__DENALI_PI_9_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PI_9_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PI_9__PI_TDFI_PHYUPD_RESP_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PI_9__PI_TDFI_PHYUPD_RESP_SHIFT 0U
+#define LPDDR4__DENALI_PI_9__PI_TDFI_PHYUPD_RESP_WIDTH 20U
+#define LPDDR4__PI_TDFI_PHYUPD_RESP__REG DENALI_PI_9
+#define LPDDR4__PI_TDFI_PHYUPD_RESP__FLD LPDDR4__DENALI_PI_9__PI_TDFI_PHYUPD_RESP
+
+#define LPDDR4__DENALI_PI_10_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_10_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_10__PI_TDFI_PHYUPD_MAX_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_10__PI_TDFI_PHYUPD_MAX_SHIFT 0U
+#define LPDDR4__DENALI_PI_10__PI_TDFI_PHYUPD_MAX_WIDTH 32U
+#define LPDDR4__PI_TDFI_PHYUPD_MAX__REG DENALI_PI_10
+#define LPDDR4__PI_TDFI_PHYUPD_MAX__FLD LPDDR4__DENALI_PI_10__PI_TDFI_PHYUPD_MAX
+
+#define LPDDR4__DENALI_PI_11_READ_MASK 0x0000011FU
+#define LPDDR4__DENALI_PI_11_WRITE_MASK 0x0000011FU
+#define LPDDR4__DENALI_PI_11__PI_INIT_WORK_FREQ_MASK 0x0000001FU
+#define LPDDR4__DENALI_PI_11__PI_INIT_WORK_FREQ_SHIFT 0U
+#define LPDDR4__DENALI_PI_11__PI_INIT_WORK_FREQ_WIDTH 5U
+#define LPDDR4__PI_INIT_WORK_FREQ__REG DENALI_PI_11
+#define LPDDR4__PI_INIT_WORK_FREQ__FLD LPDDR4__DENALI_PI_11__PI_INIT_WORK_FREQ
+
+#define LPDDR4__DENALI_PI_11__PI_INIT_DFS_CALVL_ONLY_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_11__PI_INIT_DFS_CALVL_ONLY_SHIFT 8U
+#define LPDDR4__DENALI_PI_11__PI_INIT_DFS_CALVL_ONLY_WIDTH 1U
+#define LPDDR4__DENALI_PI_11__PI_INIT_DFS_CALVL_ONLY_WOCLR 0U
+#define LPDDR4__DENALI_PI_11__PI_INIT_DFS_CALVL_ONLY_WOSET 0U
+#define LPDDR4__PI_INIT_DFS_CALVL_ONLY__REG DENALI_PI_11
+#define LPDDR4__PI_INIT_DFS_CALVL_ONLY__FLD LPDDR4__DENALI_PI_11__PI_INIT_DFS_CALVL_ONLY
+
+#define LPDDR4__DENALI_PI_12_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_12_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_12__PI_FREQ_MAP_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_12__PI_FREQ_MAP_SHIFT 0U
+#define LPDDR4__DENALI_PI_12__PI_FREQ_MAP_WIDTH 32U
+#define LPDDR4__PI_FREQ_MAP__REG DENALI_PI_12
+#define LPDDR4__PI_FREQ_MAP__FLD LPDDR4__DENALI_PI_12__PI_FREQ_MAP
+
+#define LPDDR4__DENALI_PI_13_READ_MASK 0x010F0101U
+#define LPDDR4__DENALI_PI_13_WRITE_MASK 0x010F0101U
+#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_SHIFT 0U
+#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_WIDTH 1U
+#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_WOCLR 0U
+#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_WOSET 0U
+#define LPDDR4__PI_SW_RST_N__REG DENALI_PI_13
+#define LPDDR4__PI_SW_RST_N__FLD LPDDR4__DENALI_PI_13__PI_SW_RST_N
+
+#define LPDDR4__DENALI_PI_13__PI_RESERVED1_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_13__PI_RESERVED1_SHIFT 8U
+#define LPDDR4__DENALI_PI_13__PI_RESERVED1_WIDTH 1U
+#define LPDDR4__DENALI_PI_13__PI_RESERVED1_WOCLR 0U
+#define LPDDR4__DENALI_PI_13__PI_RESERVED1_WOSET 0U
+#define LPDDR4__PI_RESERVED1__REG DENALI_PI_13
+#define LPDDR4__PI_RESERVED1__FLD LPDDR4__DENALI_PI_13__PI_RESERVED1
+
+#define LPDDR4__DENALI_PI_13__PI_CS_MAP_MASK 0x000F0000U
+#define LPDDR4__DENALI_PI_13__PI_CS_MAP_SHIFT 16U
+#define LPDDR4__DENALI_PI_13__PI_CS_MAP_WIDTH 4U
+#define LPDDR4__PI_CS_MAP__REG DENALI_PI_13
+#define LPDDR4__PI_CS_MAP__FLD LPDDR4__DENALI_PI_13__PI_CS_MAP
+
+#define LPDDR4__DENALI_PI_13__PI_SWLVL_CS_SEL_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_13__PI_SWLVL_CS_SEL_SHIFT 24U
+#define LPDDR4__DENALI_PI_13__PI_SWLVL_CS_SEL_WIDTH 1U
+#define LPDDR4__DENALI_PI_13__PI_SWLVL_CS_SEL_WOCLR 0U
+#define LPDDR4__DENALI_PI_13__PI_SWLVL_CS_SEL_WOSET 0U
+#define LPDDR4__PI_SWLVL_CS_SEL__REG DENALI_PI_13
+#define LPDDR4__PI_SWLVL_CS_SEL__FLD LPDDR4__DENALI_PI_13__PI_SWLVL_CS_SEL
+
+#define LPDDR4__DENALI_PI_14_READ_MASK 0x0F011F0FU
+#define LPDDR4__DENALI_PI_14_WRITE_MASK 0x0F011F0FU
+#define LPDDR4__DENALI_PI_14__PI_CS_MASK_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_14__PI_CS_MASK_SHIFT 0U
+#define LPDDR4__DENALI_PI_14__PI_CS_MASK_WIDTH 4U
+#define LPDDR4__PI_CS_MASK__REG DENALI_PI_14
+#define LPDDR4__PI_CS_MASK__FLD LPDDR4__DENALI_PI_14__PI_CS_MASK
+
+#define LPDDR4__DENALI_PI_14__PI_RANK_NUM_PER_CKE_MASK 0x00001F00U
+#define LPDDR4__DENALI_PI_14__PI_RANK_NUM_PER_CKE_SHIFT 8U
+#define LPDDR4__DENALI_PI_14__PI_RANK_NUM_PER_CKE_WIDTH 5U
+#define LPDDR4__PI_RANK_NUM_PER_CKE__REG DENALI_PI_14
+#define LPDDR4__PI_RANK_NUM_PER_CKE__FLD LPDDR4__DENALI_PI_14__PI_RANK_NUM_PER_CKE
+
+#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_SHIFT 16U
+#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_WIDTH 1U
+#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_WOCLR 0U
+#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_WOSET 0U
+#define LPDDR4__PI_SRX_LVL_TARGET_CS_EN__REG DENALI_PI_14
+#define LPDDR4__PI_SRX_LVL_TARGET_CS_EN__FLD LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN
+
+#define LPDDR4__DENALI_PI_14__PI_TMRR_MASK 0x0F000000U
+#define LPDDR4__DENALI_PI_14__PI_TMRR_SHIFT 24U
+#define LPDDR4__DENALI_PI_14__PI_TMRR_WIDTH 4U
+#define LPDDR4__PI_TMRR__REG DENALI_PI_14
+#define LPDDR4__PI_TMRR__FLD LPDDR4__DENALI_PI_14__PI_TMRR
+
+#define LPDDR4__DENALI_PI_15_READ_MASK 0x0101070FU
+#define LPDDR4__DENALI_PI_15_WRITE_MASK 0x0101070FU
+#define LPDDR4__DENALI_PI_15__PI_TMPRR_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_15__PI_TMPRR_SHIFT 0U
+#define LPDDR4__DENALI_PI_15__PI_TMPRR_WIDTH 4U
+#define LPDDR4__PI_TMPRR__REG DENALI_PI_15
+#define LPDDR4__PI_TMPRR__FLD LPDDR4__DENALI_PI_15__PI_TMPRR
+
+#define LPDDR4__DENALI_PI_15__PI_VRCG_EN_MASK 0x00000700U
+#define LPDDR4__DENALI_PI_15__PI_VRCG_EN_SHIFT 8U
+#define LPDDR4__DENALI_PI_15__PI_VRCG_EN_WIDTH 3U
+#define LPDDR4__PI_VRCG_EN__REG DENALI_PI_15
+#define LPDDR4__PI_VRCG_EN__FLD LPDDR4__DENALI_PI_15__PI_VRCG_EN
+
+#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_SHIFT 16U
+#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_WIDTH 1U
+#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_WOCLR 0U
+#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_WOSET 0U
+#define LPDDR4__PI_MCAREF_FORWARD_ONLY__REG DENALI_PI_15
+#define LPDDR4__PI_MCAREF_FORWARD_ONLY__FLD LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY
+
+#define LPDDR4__DENALI_PI_15__PI_RESERVED2_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_15__PI_RESERVED2_SHIFT 24U
+#define LPDDR4__DENALI_PI_15__PI_RESERVED2_WIDTH 1U
+#define LPDDR4__DENALI_PI_15__PI_RESERVED2_WOCLR 0U
+#define LPDDR4__DENALI_PI_15__PI_RESERVED2_WOSET 0U
+#define LPDDR4__PI_RESERVED2__REG DENALI_PI_15
+#define LPDDR4__PI_RESERVED2__FLD LPDDR4__DENALI_PI_15__PI_RESERVED2
+
+#define LPDDR4__DENALI_PI_16_READ_MASK 0x010FFFFFU
+#define LPDDR4__DENALI_PI_16_WRITE_MASK 0x010FFFFFU
+#define LPDDR4__DENALI_PI_16__PI_TREF_INTERVAL_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PI_16__PI_TREF_INTERVAL_SHIFT 0U
+#define LPDDR4__DENALI_PI_16__PI_TREF_INTERVAL_WIDTH 20U
+#define LPDDR4__PI_TREF_INTERVAL__REG DENALI_PI_16
+#define LPDDR4__PI_TREF_INTERVAL__FLD LPDDR4__DENALI_PI_16__PI_TREF_INTERVAL
+
+#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_SHIFT 24U
+#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_WIDTH 1U
+#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_WOCLR 0U
+#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_WOSET 0U
+#define LPDDR4__PI_ON_DFIBUS__REG DENALI_PI_16
+#define LPDDR4__PI_ON_DFIBUS__FLD LPDDR4__DENALI_PI_16__PI_ON_DFIBUS
+
+#define LPDDR4__DENALI_PI_17_READ_MASK 0x01010001U
+#define LPDDR4__DENALI_PI_17_WRITE_MASK 0x01010001U
+#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_SHIFT 0U
+#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_WIDTH 1U
+#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_WOCLR 0U
+#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_WOSET 0U
+#define LPDDR4__PI_DATA_RETENTION__REG DENALI_PI_17
+#define LPDDR4__PI_DATA_RETENTION__FLD LPDDR4__DENALI_PI_17__PI_DATA_RETENTION
+
+#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_SHIFT 8U
+#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_WIDTH 1U
+#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_WOCLR 0U
+#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_WOSET 0U
+#define LPDDR4__PI_SWLVL_LOAD__REG DENALI_PI_17
+#define LPDDR4__PI_SWLVL_LOAD__FLD LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD
+
+#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_SHIFT 16U
+#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_WIDTH 1U
+#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_WOCLR 0U
+#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_WOSET 0U
+#define LPDDR4__PI_SWLVL_OP_DONE__REG DENALI_PI_17
+#define LPDDR4__PI_SWLVL_OP_DONE__FLD LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE
+
+#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_SHIFT 24U
+#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_WIDTH 1U
+#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_WOCLR 0U
+#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_WOSET 0U
+#define LPDDR4__PI_SW_WRLVL_RESP_0__REG DENALI_PI_17
+#define LPDDR4__PI_SW_WRLVL_RESP_0__FLD LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0
+
+#define LPDDR4__DENALI_PI_18_READ_MASK 0x03010101U
+#define LPDDR4__DENALI_PI_18_WRITE_MASK 0x03010101U
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_WIDTH 1U
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_WOCLR 0U
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_WOSET 0U
+#define LPDDR4__PI_SW_WRLVL_RESP_1__REG DENALI_PI_18
+#define LPDDR4__PI_SW_WRLVL_RESP_1__FLD LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1
+
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_2_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_2_SHIFT 8U
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_2_WIDTH 1U
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_2_WOCLR 0U
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_2_WOSET 0U
+#define LPDDR4__PI_SW_WRLVL_RESP_2__REG DENALI_PI_18
+#define LPDDR4__PI_SW_WRLVL_RESP_2__FLD LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_2
+
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_3_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_3_SHIFT 16U
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_3_WIDTH 1U
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_3_WOCLR 0U
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_3_WOSET 0U
+#define LPDDR4__PI_SW_WRLVL_RESP_3__REG DENALI_PI_18
+#define LPDDR4__PI_SW_WRLVL_RESP_3__FLD LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_3
+
+#define LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_0_MASK 0x03000000U
+#define LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_0_SHIFT 24U
+#define LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_0_WIDTH 2U
+#define LPDDR4__PI_SW_RDLVL_RESP_0__REG DENALI_PI_18
+#define LPDDR4__PI_SW_RDLVL_RESP_0__FLD LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_0
+
+#define LPDDR4__DENALI_PI_19_READ_MASK 0x03030303U
+#define LPDDR4__DENALI_PI_19_WRITE_MASK 0x03030303U
+#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_1_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_1_WIDTH 2U
+#define LPDDR4__PI_SW_RDLVL_RESP_1__REG DENALI_PI_19
+#define LPDDR4__PI_SW_RDLVL_RESP_1__FLD LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_1
+
+#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_2_MASK 0x00000300U
+#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_2_SHIFT 8U
+#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_2_WIDTH 2U
+#define LPDDR4__PI_SW_RDLVL_RESP_2__REG DENALI_PI_19
+#define LPDDR4__PI_SW_RDLVL_RESP_2__FLD LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_2
+
+#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_3_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_3_SHIFT 16U
+#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_3_WIDTH 2U
+#define LPDDR4__PI_SW_RDLVL_RESP_3__REG DENALI_PI_19
+#define LPDDR4__PI_SW_RDLVL_RESP_3__FLD LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_3
+
+#define LPDDR4__DENALI_PI_19__PI_SW_CALVL_RESP_0_MASK 0x03000000U
+#define LPDDR4__DENALI_PI_19__PI_SW_CALVL_RESP_0_SHIFT 24U
+#define LPDDR4__DENALI_PI_19__PI_SW_CALVL_RESP_0_WIDTH 2U
+#define LPDDR4__PI_SW_CALVL_RESP_0__REG DENALI_PI_19
+#define LPDDR4__PI_SW_CALVL_RESP_0__FLD LPDDR4__DENALI_PI_19__PI_SW_CALVL_RESP_0
+
+#define LPDDR4__DENALI_PI_20_READ_MASK 0x00000007U
+#define LPDDR4__DENALI_PI_20_WRITE_MASK 0x00000007U
+#define LPDDR4__DENALI_PI_20__PI_SW_LEVELING_MODE_MASK 0x00000007U
+#define LPDDR4__DENALI_PI_20__PI_SW_LEVELING_MODE_SHIFT 0U
+#define LPDDR4__DENALI_PI_20__PI_SW_LEVELING_MODE_WIDTH 3U
+#define LPDDR4__PI_SW_LEVELING_MODE__REG DENALI_PI_20
+#define LPDDR4__PI_SW_LEVELING_MODE__FLD LPDDR4__DENALI_PI_20__PI_SW_LEVELING_MODE
+
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_START_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_START_SHIFT 8U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_START_WIDTH 1U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_START_WOCLR 0U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_START_WOSET 0U
+#define LPDDR4__PI_SWLVL_START__REG DENALI_PI_20
+#define LPDDR4__PI_SWLVL_START__FLD LPDDR4__DENALI_PI_20__PI_SWLVL_START
+
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_EXIT_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_EXIT_SHIFT 16U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_EXIT_WIDTH 1U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_EXIT_WOCLR 0U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_EXIT_WOSET 0U
+#define LPDDR4__PI_SWLVL_EXIT__REG DENALI_PI_20
+#define LPDDR4__PI_SWLVL_EXIT__FLD LPDDR4__DENALI_PI_20__PI_SWLVL_EXIT
+
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_0_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_0_SHIFT 24U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_0_WIDTH 1U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_0_WOCLR 0U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_0_WOSET 0U
+#define LPDDR4__PI_SWLVL_WR_SLICE_0__REG DENALI_PI_20
+#define LPDDR4__PI_SWLVL_WR_SLICE_0__FLD LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_0
+
+#define LPDDR4__DENALI_PI_21_READ_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_21_WRITE_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_0_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_0_WIDTH 1U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_0_WOCLR 0U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_0_WOSET 0U
+#define LPDDR4__PI_SWLVL_RD_SLICE_0__REG DENALI_PI_21
+#define LPDDR4__PI_SWLVL_RD_SLICE_0__FLD LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_0
+
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_0_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_0_SHIFT 8U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_0_WIDTH 1U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_0_WOCLR 0U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_0_WOSET 0U
+#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_0__REG DENALI_PI_21
+#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_0__FLD LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_0
+
+#define LPDDR4__DENALI_PI_21__PI_SW_WDQLVL_RESP_0_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_21__PI_SW_WDQLVL_RESP_0_SHIFT 16U
+#define LPDDR4__DENALI_PI_21__PI_SW_WDQLVL_RESP_0_WIDTH 2U
+#define LPDDR4__PI_SW_WDQLVL_RESP_0__REG DENALI_PI_21
+#define LPDDR4__PI_SW_WDQLVL_RESP_0__FLD LPDDR4__DENALI_PI_21__PI_SW_WDQLVL_RESP_0
+
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_WR_SLICE_1_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_WR_SLICE_1_SHIFT 24U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_WR_SLICE_1_WIDTH 1U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_WR_SLICE_1_WOCLR 0U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_WR_SLICE_1_WOSET 0U
+#define LPDDR4__PI_SWLVL_WR_SLICE_1__REG DENALI_PI_21
+#define LPDDR4__PI_SWLVL_WR_SLICE_1__FLD LPDDR4__DENALI_PI_21__PI_SWLVL_WR_SLICE_1
+
+#define LPDDR4__DENALI_PI_22_READ_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_22_WRITE_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_RD_SLICE_1_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_RD_SLICE_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_RD_SLICE_1_WIDTH 1U
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_RD_SLICE_1_WOCLR 0U
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_RD_SLICE_1_WOSET 0U
+#define LPDDR4__PI_SWLVL_RD_SLICE_1__REG DENALI_PI_22
+#define LPDDR4__PI_SWLVL_RD_SLICE_1__FLD LPDDR4__DENALI_PI_22__PI_SWLVL_RD_SLICE_1
+
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_VREF_UPDATE_SLICE_1_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_VREF_UPDATE_SLICE_1_SHIFT 8U
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_VREF_UPDATE_SLICE_1_WIDTH 1U
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_VREF_UPDATE_SLICE_1_WOCLR 0U
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_VREF_UPDATE_SLICE_1_WOSET 0U
+#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_1__REG DENALI_PI_22
+#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_1__FLD LPDDR4__DENALI_PI_22__PI_SWLVL_VREF_UPDATE_SLICE_1
+
+#define LPDDR4__DENALI_PI_22__PI_SW_WDQLVL_RESP_1_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_22__PI_SW_WDQLVL_RESP_1_SHIFT 16U
+#define LPDDR4__DENALI_PI_22__PI_SW_WDQLVL_RESP_1_WIDTH 2U
+#define LPDDR4__PI_SW_WDQLVL_RESP_1__REG DENALI_PI_22
+#define LPDDR4__PI_SW_WDQLVL_RESP_1__FLD LPDDR4__DENALI_PI_22__PI_SW_WDQLVL_RESP_1
+
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_WR_SLICE_2_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_WR_SLICE_2_SHIFT 24U
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_WR_SLICE_2_WIDTH 1U
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_WR_SLICE_2_WOCLR 0U
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_WR_SLICE_2_WOSET 0U
+#define LPDDR4__PI_SWLVL_WR_SLICE_2__REG DENALI_PI_22
+#define LPDDR4__PI_SWLVL_WR_SLICE_2__FLD LPDDR4__DENALI_PI_22__PI_SWLVL_WR_SLICE_2
+
+#define LPDDR4__DENALI_PI_23_READ_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_23_WRITE_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_23__PI_SWLVL_RD_SLICE_2_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_23__PI_SWLVL_RD_SLICE_2_SHIFT 0U
+#define LPDDR4__DENALI_PI_23__PI_SWLVL_RD_SLICE_2_WIDTH 1U
+#define LPDDR4__DENALI_PI_23__PI_SWLVL_RD_SLICE_2_WOCLR 0U
+#define LPDDR4__DENALI_PI_23__PI_SWLVL_RD_SLICE_2_WOSET 0U
+#define LPDDR4__PI_SWLVL_RD_SLICE_2__REG DENALI_PI_23
+#define LPDDR4__PI_SWLVL_RD_SLICE_2__FLD LPDDR4__DENALI_PI_23__PI_SWLVL_RD_SLICE_2
+
+#define LPDDR4__DENALI_PI_23__PI_SWLVL_VREF_UPDATE_SLICE_2_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_23__PI_SWLVL_VREF_UPDATE_SLICE_2_SHIFT 8U
+#define LPDDR4__DENALI_PI_23__PI_SWLVL_VREF_UPDATE_SLICE_2_WIDTH 1U
+#define LPDDR4__DENALI_PI_23__PI_SWLVL_VREF_UPDATE_SLICE_2_WOCLR 0U
+#define LPDDR4__DENALI_PI_23__PI_SWLVL_VREF_UPDATE_SLICE_2_WOSET 0U
+#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_2__REG DENALI_PI_23
+#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_2__FLD LPDDR4__DENALI_PI_23__PI_SWLVL_VREF_UPDATE_SLICE_2
+
+#define LPDDR4__DENALI_PI_23__PI_SW_WDQLVL_RESP_2_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_23__PI_SW_WDQLVL_RESP_2_SHIFT 16U
+#define LPDDR4__DENALI_PI_23__PI_SW_WDQLVL_RESP_2_WIDTH 2U
+#define LPDDR4__PI_SW_WDQLVL_RESP_2__REG DENALI_PI_23
+#define LPDDR4__PI_SW_WDQLVL_RESP_2__FLD LPDDR4__DENALI_PI_23__PI_SW_WDQLVL_RESP_2
+
+#define LPDDR4__DENALI_PI_23__PI_SWLVL_WR_SLICE_3_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_23__PI_SWLVL_WR_SLICE_3_SHIFT 24U
+#define LPDDR4__DENALI_PI_23__PI_SWLVL_WR_SLICE_3_WIDTH 1U
+#define LPDDR4__DENALI_PI_23__PI_SWLVL_WR_SLICE_3_WOCLR 0U
+#define LPDDR4__DENALI_PI_23__PI_SWLVL_WR_SLICE_3_WOSET 0U
+#define LPDDR4__PI_SWLVL_WR_SLICE_3__REG DENALI_PI_23
+#define LPDDR4__PI_SWLVL_WR_SLICE_3__FLD LPDDR4__DENALI_PI_23__PI_SWLVL_WR_SLICE_3
+
+#define LPDDR4__DENALI_PI_24_READ_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_24_WRITE_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_24__PI_SWLVL_RD_SLICE_3_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_24__PI_SWLVL_RD_SLICE_3_SHIFT 0U
+#define LPDDR4__DENALI_PI_24__PI_SWLVL_RD_SLICE_3_WIDTH 1U
+#define LPDDR4__DENALI_PI_24__PI_SWLVL_RD_SLICE_3_WOCLR 0U
+#define LPDDR4__DENALI_PI_24__PI_SWLVL_RD_SLICE_3_WOSET 0U
+#define LPDDR4__PI_SWLVL_RD_SLICE_3__REG DENALI_PI_24
+#define LPDDR4__PI_SWLVL_RD_SLICE_3__FLD LPDDR4__DENALI_PI_24__PI_SWLVL_RD_SLICE_3
+
+#define LPDDR4__DENALI_PI_24__PI_SWLVL_VREF_UPDATE_SLICE_3_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_24__PI_SWLVL_VREF_UPDATE_SLICE_3_SHIFT 8U
+#define LPDDR4__DENALI_PI_24__PI_SWLVL_VREF_UPDATE_SLICE_3_WIDTH 1U
+#define LPDDR4__DENALI_PI_24__PI_SWLVL_VREF_UPDATE_SLICE_3_WOCLR 0U
+#define LPDDR4__DENALI_PI_24__PI_SWLVL_VREF_UPDATE_SLICE_3_WOSET 0U
+#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_3__REG DENALI_PI_24
+#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_3__FLD LPDDR4__DENALI_PI_24__PI_SWLVL_VREF_UPDATE_SLICE_3
+
+#define LPDDR4__DENALI_PI_24__PI_SW_WDQLVL_RESP_3_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_24__PI_SW_WDQLVL_RESP_3_SHIFT 16U
+#define LPDDR4__DENALI_PI_24__PI_SW_WDQLVL_RESP_3_WIDTH 2U
+#define LPDDR4__PI_SW_WDQLVL_RESP_3__REG DENALI_PI_24
+#define LPDDR4__PI_SW_WDQLVL_RESP_3__FLD LPDDR4__DENALI_PI_24__PI_SW_WDQLVL_RESP_3
+
+#define LPDDR4__DENALI_PI_24__PI_SWLVL_SM2_START_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_24__PI_SWLVL_SM2_START_SHIFT 24U
+#define LPDDR4__DENALI_PI_24__PI_SWLVL_SM2_START_WIDTH 1U
+#define LPDDR4__DENALI_PI_24__PI_SWLVL_SM2_START_WOCLR 0U
+#define LPDDR4__DENALI_PI_24__PI_SWLVL_SM2_START_WOSET 0U
+#define LPDDR4__PI_SWLVL_SM2_START__REG DENALI_PI_24
+#define LPDDR4__PI_SWLVL_SM2_START__FLD LPDDR4__DENALI_PI_24__PI_SWLVL_SM2_START
+
+#define LPDDR4__DENALI_PI_25_READ_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_25_WRITE_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_WR_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_WR_SHIFT 0U
+#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_WR_WIDTH 1U
+#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_WR_WOCLR 0U
+#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_WR_WOSET 0U
+#define LPDDR4__PI_SWLVL_SM2_WR__REG DENALI_PI_25
+#define LPDDR4__PI_SWLVL_SM2_WR__FLD LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_WR
+
+#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_RD_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_RD_SHIFT 8U
+#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_RD_WIDTH 1U
+#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_RD_WOCLR 0U
+#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_RD_WOSET 0U
+#define LPDDR4__PI_SWLVL_SM2_RD__REG DENALI_PI_25
+#define LPDDR4__PI_SWLVL_SM2_RD__FLD LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_RD
+
+#define LPDDR4__DENALI_PI_25__PI_SEQUENTIAL_LVL_REQ_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_25__PI_SEQUENTIAL_LVL_REQ_SHIFT 16U
+#define LPDDR4__DENALI_PI_25__PI_SEQUENTIAL_LVL_REQ_WIDTH 1U
+#define LPDDR4__DENALI_PI_25__PI_SEQUENTIAL_LVL_REQ_WOCLR 0U
+#define LPDDR4__DENALI_PI_25__PI_SEQUENTIAL_LVL_REQ_WOSET 0U
+#define LPDDR4__PI_SEQUENTIAL_LVL_REQ__REG DENALI_PI_25
+#define LPDDR4__PI_SEQUENTIAL_LVL_REQ__FLD LPDDR4__DENALI_PI_25__PI_SEQUENTIAL_LVL_REQ
+
+#define LPDDR4__DENALI_PI_25__PI_DFS_PERIOD_EN_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_25__PI_DFS_PERIOD_EN_SHIFT 24U
+#define LPDDR4__DENALI_PI_25__PI_DFS_PERIOD_EN_WIDTH 1U
+#define LPDDR4__DENALI_PI_25__PI_DFS_PERIOD_EN_WOCLR 0U
+#define LPDDR4__DENALI_PI_25__PI_DFS_PERIOD_EN_WOSET 0U
+#define LPDDR4__PI_DFS_PERIOD_EN__REG DENALI_PI_25
+#define LPDDR4__PI_DFS_PERIOD_EN__FLD LPDDR4__DENALI_PI_25__PI_DFS_PERIOD_EN
+
+#define LPDDR4__DENALI_PI_26_READ_MASK 0x01010101U
+#define LPDDR4__DENALI_PI_26_WRITE_MASK 0x01010101U
+#define LPDDR4__DENALI_PI_26__PI_SRE_PERIOD_EN_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_26__PI_SRE_PERIOD_EN_SHIFT 0U
+#define LPDDR4__DENALI_PI_26__PI_SRE_PERIOD_EN_WIDTH 1U
+#define LPDDR4__DENALI_PI_26__PI_SRE_PERIOD_EN_WOCLR 0U
+#define LPDDR4__DENALI_PI_26__PI_SRE_PERIOD_EN_WOSET 0U
+#define LPDDR4__PI_SRE_PERIOD_EN__REG DENALI_PI_26
+#define LPDDR4__PI_SRE_PERIOD_EN__FLD LPDDR4__DENALI_PI_26__PI_SRE_PERIOD_EN
+
+#define LPDDR4__DENALI_PI_26__PI_MPD_PERIOD_EN_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_26__PI_MPD_PERIOD_EN_SHIFT 8U
+#define LPDDR4__DENALI_PI_26__PI_MPD_PERIOD_EN_WIDTH 1U
+#define LPDDR4__DENALI_PI_26__PI_MPD_PERIOD_EN_WOCLR 0U
+#define LPDDR4__DENALI_PI_26__PI_MPD_PERIOD_EN_WOSET 0U
+#define LPDDR4__PI_MPD_PERIOD_EN__REG DENALI_PI_26
+#define LPDDR4__PI_MPD_PERIOD_EN__FLD LPDDR4__DENALI_PI_26__PI_MPD_PERIOD_EN
+
+#define LPDDR4__DENALI_PI_26__PI_DFI40_POLARITY_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_26__PI_DFI40_POLARITY_SHIFT 16U
+#define LPDDR4__DENALI_PI_26__PI_DFI40_POLARITY_WIDTH 1U
+#define LPDDR4__DENALI_PI_26__PI_DFI40_POLARITY_WOCLR 0U
+#define LPDDR4__DENALI_PI_26__PI_DFI40_POLARITY_WOSET 0U
+#define LPDDR4__PI_DFI40_POLARITY__REG DENALI_PI_26
+#define LPDDR4__PI_DFI40_POLARITY__FLD LPDDR4__DENALI_PI_26__PI_DFI40_POLARITY
+
+#define LPDDR4__DENALI_PI_26__PI_16BIT_DRAM_CONNECT_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_26__PI_16BIT_DRAM_CONNECT_SHIFT 24U
+#define LPDDR4__DENALI_PI_26__PI_16BIT_DRAM_CONNECT_WIDTH 1U
+#define LPDDR4__DENALI_PI_26__PI_16BIT_DRAM_CONNECT_WOCLR 0U
+#define LPDDR4__DENALI_PI_26__PI_16BIT_DRAM_CONNECT_WOSET 0U
+#define LPDDR4__PI_16BIT_DRAM_CONNECT__REG DENALI_PI_26
+#define LPDDR4__PI_16BIT_DRAM_CONNECT__FLD LPDDR4__DENALI_PI_26__PI_16BIT_DRAM_CONNECT
+
+#define LPDDR4__DENALI_PI_27_READ_MASK 0x3F030F00U
+#define LPDDR4__DENALI_PI_27_WRITE_MASK 0x3F030F00U
+#define LPDDR4__DENALI_PI_27__PI_WRLVL_REQ_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_27__PI_WRLVL_REQ_SHIFT 0U
+#define LPDDR4__DENALI_PI_27__PI_WRLVL_REQ_WIDTH 1U
+#define LPDDR4__DENALI_PI_27__PI_WRLVL_REQ_WOCLR 0U
+#define LPDDR4__DENALI_PI_27__PI_WRLVL_REQ_WOSET 0U
+#define LPDDR4__PI_WRLVL_REQ__REG DENALI_PI_27
+#define LPDDR4__PI_WRLVL_REQ__FLD LPDDR4__DENALI_PI_27__PI_WRLVL_REQ
+
+#define LPDDR4__DENALI_PI_27__PI_WRLVL_CS_SW_MASK 0x00000F00U
+#define LPDDR4__DENALI_PI_27__PI_WRLVL_CS_SW_SHIFT 8U
+#define LPDDR4__DENALI_PI_27__PI_WRLVL_CS_SW_WIDTH 4U
+#define LPDDR4__PI_WRLVL_CS_SW__REG DENALI_PI_27
+#define LPDDR4__PI_WRLVL_CS_SW__FLD LPDDR4__DENALI_PI_27__PI_WRLVL_CS_SW
+
+#define LPDDR4__DENALI_PI_27__PI_WRLVL_CS_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_27__PI_WRLVL_CS_SHIFT 16U
+#define LPDDR4__DENALI_PI_27__PI_WRLVL_CS_WIDTH 2U
+#define LPDDR4__PI_WRLVL_CS__REG DENALI_PI_27
+#define LPDDR4__PI_WRLVL_CS__FLD LPDDR4__DENALI_PI_27__PI_WRLVL_CS
+
+#define LPDDR4__DENALI_PI_27__PI_WLDQSEN_MASK 0x3F000000U
+#define LPDDR4__DENALI_PI_27__PI_WLDQSEN_SHIFT 24U
+#define LPDDR4__DENALI_PI_27__PI_WLDQSEN_WIDTH 6U
+#define LPDDR4__PI_WLDQSEN__REG DENALI_PI_27
+#define LPDDR4__PI_WLDQSEN__FLD LPDDR4__DENALI_PI_27__PI_WLDQSEN
+
+#define LPDDR4__DENALI_PI_28_READ_MASK 0x01FFFF3FU
+#define LPDDR4__DENALI_PI_28_WRITE_MASK 0x01FFFF3FU
+#define LPDDR4__DENALI_PI_28__PI_WLMRD_MASK 0x0000003FU
+#define LPDDR4__DENALI_PI_28__PI_WLMRD_SHIFT 0U
+#define LPDDR4__DENALI_PI_28__PI_WLMRD_WIDTH 6U
+#define LPDDR4__PI_WLMRD__REG DENALI_PI_28
+#define LPDDR4__PI_WLMRD__FLD LPDDR4__DENALI_PI_28__PI_WLMRD
+
+#define LPDDR4__DENALI_PI_28__PI_WRLVL_INTERVAL_MASK 0x00FFFF00U
+#define LPDDR4__DENALI_PI_28__PI_WRLVL_INTERVAL_SHIFT 8U
+#define LPDDR4__DENALI_PI_28__PI_WRLVL_INTERVAL_WIDTH 16U
+#define LPDDR4__PI_WRLVL_INTERVAL__REG DENALI_PI_28
+#define LPDDR4__PI_WRLVL_INTERVAL__FLD LPDDR4__DENALI_PI_28__PI_WRLVL_INTERVAL
+
+#define LPDDR4__DENALI_PI_28__PI_WRLVL_ON_SREF_EXIT_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_28__PI_WRLVL_ON_SREF_EXIT_SHIFT 24U
+#define LPDDR4__DENALI_PI_28__PI_WRLVL_ON_SREF_EXIT_WIDTH 1U
+#define LPDDR4__DENALI_PI_28__PI_WRLVL_ON_SREF_EXIT_WOCLR 0U
+#define LPDDR4__DENALI_PI_28__PI_WRLVL_ON_SREF_EXIT_WOSET 0U
+#define LPDDR4__PI_WRLVL_ON_SREF_EXIT__REG DENALI_PI_28
+#define LPDDR4__PI_WRLVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_28__PI_WRLVL_ON_SREF_EXIT
+
+#define LPDDR4__DENALI_PI_29_READ_MASK 0x0F010F01U
+#define LPDDR4__DENALI_PI_29_WRITE_MASK 0x0F010F01U
+#define LPDDR4__DENALI_PI_29__PI_WRLVL_DISABLE_DFS_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_29__PI_WRLVL_DISABLE_DFS_SHIFT 0U
+#define LPDDR4__DENALI_PI_29__PI_WRLVL_DISABLE_DFS_WIDTH 1U
+#define LPDDR4__DENALI_PI_29__PI_WRLVL_DISABLE_DFS_WOCLR 0U
+#define LPDDR4__DENALI_PI_29__PI_WRLVL_DISABLE_DFS_WOSET 0U
+#define LPDDR4__PI_WRLVL_DISABLE_DFS__REG DENALI_PI_29
+#define LPDDR4__PI_WRLVL_DISABLE_DFS__FLD LPDDR4__DENALI_PI_29__PI_WRLVL_DISABLE_DFS
+
+#define LPDDR4__DENALI_PI_29__PI_WRLVL_RESP_MASK_MASK 0x00000F00U
+#define LPDDR4__DENALI_PI_29__PI_WRLVL_RESP_MASK_SHIFT 8U
+#define LPDDR4__DENALI_PI_29__PI_WRLVL_RESP_MASK_WIDTH 4U
+#define LPDDR4__PI_WRLVL_RESP_MASK__REG DENALI_PI_29
+#define LPDDR4__PI_WRLVL_RESP_MASK__FLD LPDDR4__DENALI_PI_29__PI_WRLVL_RESP_MASK
+
+#define LPDDR4__DENALI_PI_29__PI_WRLVL_ROTATE_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_29__PI_WRLVL_ROTATE_SHIFT 16U
+#define LPDDR4__DENALI_PI_29__PI_WRLVL_ROTATE_WIDTH 1U
+#define LPDDR4__DENALI_PI_29__PI_WRLVL_ROTATE_WOCLR 0U
+#define LPDDR4__DENALI_PI_29__PI_WRLVL_ROTATE_WOSET 0U
+#define LPDDR4__PI_WRLVL_ROTATE__REG DENALI_PI_29
+#define LPDDR4__PI_WRLVL_ROTATE__FLD LPDDR4__DENALI_PI_29__PI_WRLVL_ROTATE
+
+#define LPDDR4__DENALI_PI_29__PI_WRLVL_CS_MAP_MASK 0x0F000000U
+#define LPDDR4__DENALI_PI_29__PI_WRLVL_CS_MAP_SHIFT 24U
+#define LPDDR4__DENALI_PI_29__PI_WRLVL_CS_MAP_WIDTH 4U
+#define LPDDR4__PI_WRLVL_CS_MAP__REG DENALI_PI_29
+#define LPDDR4__PI_WRLVL_CS_MAP__FLD LPDDR4__DENALI_PI_29__PI_WRLVL_CS_MAP
+
+#define LPDDR4__DENALI_PI_30_READ_MASK 0x00FF0101U
+#define LPDDR4__DENALI_PI_30_WRITE_MASK 0x00FF0101U
+#define LPDDR4__DENALI_PI_30__PI_WRLVL_ON_MPD_EXIT_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_30__PI_WRLVL_ON_MPD_EXIT_SHIFT 0U
+#define LPDDR4__DENALI_PI_30__PI_WRLVL_ON_MPD_EXIT_WIDTH 1U
+#define LPDDR4__DENALI_PI_30__PI_WRLVL_ON_MPD_EXIT_WOCLR 0U
+#define LPDDR4__DENALI_PI_30__PI_WRLVL_ON_MPD_EXIT_WOSET 0U
+#define LPDDR4__PI_WRLVL_ON_MPD_EXIT__REG DENALI_PI_30
+#define LPDDR4__PI_WRLVL_ON_MPD_EXIT__FLD LPDDR4__DENALI_PI_30__PI_WRLVL_ON_MPD_EXIT
+
+#define LPDDR4__DENALI_PI_30__PI_WRLVL_ERROR_STATUS_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_30__PI_WRLVL_ERROR_STATUS_SHIFT 8U
+#define LPDDR4__DENALI_PI_30__PI_WRLVL_ERROR_STATUS_WIDTH 1U
+#define LPDDR4__DENALI_PI_30__PI_WRLVL_ERROR_STATUS_WOCLR 0U
+#define LPDDR4__DENALI_PI_30__PI_WRLVL_ERROR_STATUS_WOSET 0U
+#define LPDDR4__PI_WRLVL_ERROR_STATUS__REG DENALI_PI_30
+#define LPDDR4__PI_WRLVL_ERROR_STATUS__FLD LPDDR4__DENALI_PI_30__PI_WRLVL_ERROR_STATUS
+
+#define LPDDR4__DENALI_PI_30__PI_TDFI_WRLVL_EN_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_30__PI_TDFI_WRLVL_EN_SHIFT 16U
+#define LPDDR4__DENALI_PI_30__PI_TDFI_WRLVL_EN_WIDTH 8U
+#define LPDDR4__PI_TDFI_WRLVL_EN__REG DENALI_PI_30
+#define LPDDR4__PI_TDFI_WRLVL_EN__FLD LPDDR4__DENALI_PI_30__PI_TDFI_WRLVL_EN
+
+#define LPDDR4__DENALI_PI_31_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_31_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_31__PI_TDFI_WRLVL_RESP_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_31__PI_TDFI_WRLVL_RESP_SHIFT 0U
+#define LPDDR4__DENALI_PI_31__PI_TDFI_WRLVL_RESP_WIDTH 32U
+#define LPDDR4__PI_TDFI_WRLVL_RESP__REG DENALI_PI_31
+#define LPDDR4__PI_TDFI_WRLVL_RESP__FLD LPDDR4__DENALI_PI_31__PI_TDFI_WRLVL_RESP
+
+#define LPDDR4__DENALI_PI_32_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_32_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_32__PI_TDFI_WRLVL_MAX_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_32__PI_TDFI_WRLVL_MAX_SHIFT 0U
+#define LPDDR4__DENALI_PI_32__PI_TDFI_WRLVL_MAX_WIDTH 32U
+#define LPDDR4__PI_TDFI_WRLVL_MAX__REG DENALI_PI_32
+#define LPDDR4__PI_TDFI_WRLVL_MAX__FLD LPDDR4__DENALI_PI_32__PI_TDFI_WRLVL_MAX
+
+#define LPDDR4__DENALI_PI_33_READ_MASK 0x0F0F0F1FU
+#define LPDDR4__DENALI_PI_33_WRITE_MASK 0x0F0F0F1FU
+#define LPDDR4__DENALI_PI_33__PI_WRLVL_STROBE_NUM_MASK 0x0000001FU
+#define LPDDR4__DENALI_PI_33__PI_WRLVL_STROBE_NUM_SHIFT 0U
+#define LPDDR4__DENALI_PI_33__PI_WRLVL_STROBE_NUM_WIDTH 5U
+#define LPDDR4__PI_WRLVL_STROBE_NUM__REG DENALI_PI_33
+#define LPDDR4__PI_WRLVL_STROBE_NUM__FLD LPDDR4__DENALI_PI_33__PI_WRLVL_STROBE_NUM
+
+#define LPDDR4__DENALI_PI_33__PI_TODTH_WR_MASK 0x00000F00U
+#define LPDDR4__DENALI_PI_33__PI_TODTH_WR_SHIFT 8U
+#define LPDDR4__DENALI_PI_33__PI_TODTH_WR_WIDTH 4U
+#define LPDDR4__PI_TODTH_WR__REG DENALI_PI_33
+#define LPDDR4__PI_TODTH_WR__FLD LPDDR4__DENALI_PI_33__PI_TODTH_WR
+
+#define LPDDR4__DENALI_PI_33__PI_TODTH_RD_MASK 0x000F0000U
+#define LPDDR4__DENALI_PI_33__PI_TODTH_RD_SHIFT 16U
+#define LPDDR4__DENALI_PI_33__PI_TODTH_RD_WIDTH 4U
+#define LPDDR4__PI_TODTH_RD__REG DENALI_PI_33
+#define LPDDR4__PI_TODTH_RD__FLD LPDDR4__DENALI_PI_33__PI_TODTH_RD
+
+#define LPDDR4__DENALI_PI_33__PI_ODT_VALUE_MASK 0x0F000000U
+#define LPDDR4__DENALI_PI_33__PI_ODT_VALUE_SHIFT 24U
+#define LPDDR4__DENALI_PI_33__PI_ODT_VALUE_WIDTH 4U
+#define LPDDR4__PI_ODT_VALUE__REG DENALI_PI_33
+#define LPDDR4__PI_ODT_VALUE__FLD LPDDR4__DENALI_PI_33__PI_ODT_VALUE
+
+#define LPDDR4__DENALI_PI_34_READ_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_34_WRITE_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_34__PI_ADDRESS_MIRRORING_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_34__PI_ADDRESS_MIRRORING_SHIFT 0U
+#define LPDDR4__DENALI_PI_34__PI_ADDRESS_MIRRORING_WIDTH 4U
+#define LPDDR4__PI_ADDRESS_MIRRORING__REG DENALI_PI_34
+#define LPDDR4__PI_ADDRESS_MIRRORING__FLD LPDDR4__DENALI_PI_34__PI_ADDRESS_MIRRORING
+
+#define LPDDR4__DENALI_PI_35_READ_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_PI_35_WRITE_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_PI_35__PI_CA_PARITY_ERROR_INJECT_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_PI_35__PI_CA_PARITY_ERROR_INJECT_SHIFT 0U
+#define LPDDR4__DENALI_PI_35__PI_CA_PARITY_ERROR_INJECT_WIDTH 26U
+#define LPDDR4__PI_CA_PARITY_ERROR_INJECT__REG DENALI_PI_35
+#define LPDDR4__PI_CA_PARITY_ERROR_INJECT__FLD LPDDR4__DENALI_PI_35__PI_CA_PARITY_ERROR_INJECT
+
+#define LPDDR4__DENALI_PI_36_READ_MASK 0x00000F07U
+#define LPDDR4__DENALI_PI_36_WRITE_MASK 0x00000F07U
+#define LPDDR4__DENALI_PI_36__PI_RESERVED3_MASK 0x00000007U
+#define LPDDR4__DENALI_PI_36__PI_RESERVED3_SHIFT 0U
+#define LPDDR4__DENALI_PI_36__PI_RESERVED3_WIDTH 3U
+#define LPDDR4__PI_RESERVED3__REG DENALI_PI_36
+#define LPDDR4__PI_RESERVED3__FLD LPDDR4__DENALI_PI_36__PI_RESERVED3
+
+#define LPDDR4__DENALI_PI_36__PI_RESERVED4_MASK 0x00000F00U
+#define LPDDR4__DENALI_PI_36__PI_RESERVED4_SHIFT 8U
+#define LPDDR4__DENALI_PI_36__PI_RESERVED4_WIDTH 4U
+#define LPDDR4__PI_RESERVED4__REG DENALI_PI_36
+#define LPDDR4__PI_RESERVED4__FLD LPDDR4__DENALI_PI_36__PI_RESERVED4
+
+#define LPDDR4__DENALI_PI_36__PI_RDLVL_REQ_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_36__PI_RDLVL_REQ_SHIFT 16U
+#define LPDDR4__DENALI_PI_36__PI_RDLVL_REQ_WIDTH 1U
+#define LPDDR4__DENALI_PI_36__PI_RDLVL_REQ_WOCLR 0U
+#define LPDDR4__DENALI_PI_36__PI_RDLVL_REQ_WOSET 0U
+#define LPDDR4__PI_RDLVL_REQ__REG DENALI_PI_36
+#define LPDDR4__PI_RDLVL_REQ__FLD LPDDR4__DENALI_PI_36__PI_RDLVL_REQ
+
+#define LPDDR4__DENALI_PI_36__PI_RDLVL_GATE_REQ_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_36__PI_RDLVL_GATE_REQ_SHIFT 24U
+#define LPDDR4__DENALI_PI_36__PI_RDLVL_GATE_REQ_WIDTH 1U
+#define LPDDR4__DENALI_PI_36__PI_RDLVL_GATE_REQ_WOCLR 0U
+#define LPDDR4__DENALI_PI_36__PI_RDLVL_GATE_REQ_WOSET 0U
+#define LPDDR4__PI_RDLVL_GATE_REQ__REG DENALI_PI_36
+#define LPDDR4__PI_RDLVL_GATE_REQ__FLD LPDDR4__DENALI_PI_36__PI_RDLVL_GATE_REQ
+
+#define LPDDR4__DENALI_PI_37_READ_MASK 0x0000030FU
+#define LPDDR4__DENALI_PI_37_WRITE_MASK 0x0000030FU
+#define LPDDR4__DENALI_PI_37__PI_RDLVL_CS_SW_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_37__PI_RDLVL_CS_SW_SHIFT 0U
+#define LPDDR4__DENALI_PI_37__PI_RDLVL_CS_SW_WIDTH 4U
+#define LPDDR4__PI_RDLVL_CS_SW__REG DENALI_PI_37
+#define LPDDR4__PI_RDLVL_CS_SW__FLD LPDDR4__DENALI_PI_37__PI_RDLVL_CS_SW
+
+#define LPDDR4__DENALI_PI_37__PI_RDLVL_CS_MASK 0x00000300U
+#define LPDDR4__DENALI_PI_37__PI_RDLVL_CS_SHIFT 8U
+#define LPDDR4__DENALI_PI_37__PI_RDLVL_CS_WIDTH 2U
+#define LPDDR4__PI_RDLVL_CS__REG DENALI_PI_37
+#define LPDDR4__PI_RDLVL_CS__FLD LPDDR4__DENALI_PI_37__PI_RDLVL_CS
+
+#define LPDDR4__DENALI_PI_38_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_38_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_38__PI_RDLVL_PAT_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_38__PI_RDLVL_PAT_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_38__PI_RDLVL_PAT_0_WIDTH 32U
+#define LPDDR4__PI_RDLVL_PAT_0__REG DENALI_PI_38
+#define LPDDR4__PI_RDLVL_PAT_0__FLD LPDDR4__DENALI_PI_38__PI_RDLVL_PAT_0
+
+#define LPDDR4__DENALI_PI_39_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_39_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_39__PI_RDLVL_PAT_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_39__PI_RDLVL_PAT_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_39__PI_RDLVL_PAT_1_WIDTH 32U
+#define LPDDR4__PI_RDLVL_PAT_1__REG DENALI_PI_39
+#define LPDDR4__PI_RDLVL_PAT_1__FLD LPDDR4__DENALI_PI_39__PI_RDLVL_PAT_1
+
+#define LPDDR4__DENALI_PI_40_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_40_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_40__PI_RDLVL_PAT_2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_40__PI_RDLVL_PAT_2_SHIFT 0U
+#define LPDDR4__DENALI_PI_40__PI_RDLVL_PAT_2_WIDTH 32U
+#define LPDDR4__PI_RDLVL_PAT_2__REG DENALI_PI_40
+#define LPDDR4__PI_RDLVL_PAT_2__FLD LPDDR4__DENALI_PI_40__PI_RDLVL_PAT_2
+
+#define LPDDR4__DENALI_PI_41_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_41_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_41__PI_RDLVL_PAT_3_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_41__PI_RDLVL_PAT_3_SHIFT 0U
+#define LPDDR4__DENALI_PI_41__PI_RDLVL_PAT_3_WIDTH 32U
+#define LPDDR4__PI_RDLVL_PAT_3__REG DENALI_PI_41
+#define LPDDR4__PI_RDLVL_PAT_3__FLD LPDDR4__DENALI_PI_41__PI_RDLVL_PAT_3
+
+#define LPDDR4__DENALI_PI_42_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_42_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_42__PI_RDLVL_PAT_4_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_42__PI_RDLVL_PAT_4_SHIFT 0U
+#define LPDDR4__DENALI_PI_42__PI_RDLVL_PAT_4_WIDTH 32U
+#define LPDDR4__PI_RDLVL_PAT_4__REG DENALI_PI_42
+#define LPDDR4__PI_RDLVL_PAT_4__FLD LPDDR4__DENALI_PI_42__PI_RDLVL_PAT_4
+
+#define LPDDR4__DENALI_PI_43_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_43_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_PAT_5_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_PAT_5_SHIFT 0U
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_PAT_5_WIDTH 32U
+#define LPDDR4__PI_RDLVL_PAT_5__REG DENALI_PI_43
+#define LPDDR4__PI_RDLVL_PAT_5__FLD LPDDR4__DENALI_PI_43__PI_RDLVL_PAT_5
+
+#define LPDDR4__DENALI_PI_44_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_44_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_PAT_6_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_PAT_6_SHIFT 0U
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_PAT_6_WIDTH 32U
+#define LPDDR4__PI_RDLVL_PAT_6__REG DENALI_PI_44
+#define LPDDR4__PI_RDLVL_PAT_6__FLD LPDDR4__DENALI_PI_44__PI_RDLVL_PAT_6
+
+#define LPDDR4__DENALI_PI_45_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_45_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_45__PI_RDLVL_PAT_7_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_45__PI_RDLVL_PAT_7_SHIFT 0U
+#define LPDDR4__DENALI_PI_45__PI_RDLVL_PAT_7_WIDTH 32U
+#define LPDDR4__PI_RDLVL_PAT_7__REG DENALI_PI_45
+#define LPDDR4__PI_RDLVL_PAT_7__FLD LPDDR4__DENALI_PI_45__PI_RDLVL_PAT_7
+
+#define LPDDR4__DENALI_PI_46_READ_MASK 0x0101010FU
+#define LPDDR4__DENALI_PI_46_WRITE_MASK 0x0101010FU
+#define LPDDR4__DENALI_PI_46__PI_RDLVL_SEQ_EN_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_46__PI_RDLVL_SEQ_EN_SHIFT 0U
+#define LPDDR4__DENALI_PI_46__PI_RDLVL_SEQ_EN_WIDTH 4U
+#define LPDDR4__PI_RDLVL_SEQ_EN__REG DENALI_PI_46
+#define LPDDR4__PI_RDLVL_SEQ_EN__FLD LPDDR4__DENALI_PI_46__PI_RDLVL_SEQ_EN
+
+#define LPDDR4__DENALI_PI_46__PI_RDLVL_ON_SREF_EXIT_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_46__PI_RDLVL_ON_SREF_EXIT_SHIFT 8U
+#define LPDDR4__DENALI_PI_46__PI_RDLVL_ON_SREF_EXIT_WIDTH 1U
+#define LPDDR4__DENALI_PI_46__PI_RDLVL_ON_SREF_EXIT_WOCLR 0U
+#define LPDDR4__DENALI_PI_46__PI_RDLVL_ON_SREF_EXIT_WOSET 0U
+#define LPDDR4__PI_RDLVL_ON_SREF_EXIT__REG DENALI_PI_46
+#define LPDDR4__PI_RDLVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_46__PI_RDLVL_ON_SREF_EXIT
+
+#define LPDDR4__DENALI_PI_46__PI_RDLVL_DISABLE_DFS_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_46__PI_RDLVL_DISABLE_DFS_SHIFT 16U
+#define LPDDR4__DENALI_PI_46__PI_RDLVL_DISABLE_DFS_WIDTH 1U
+#define LPDDR4__DENALI_PI_46__PI_RDLVL_DISABLE_DFS_WOCLR 0U
+#define LPDDR4__DENALI_PI_46__PI_RDLVL_DISABLE_DFS_WOSET 0U
+#define LPDDR4__PI_RDLVL_DISABLE_DFS__REG DENALI_PI_46
+#define LPDDR4__PI_RDLVL_DISABLE_DFS__FLD LPDDR4__DENALI_PI_46__PI_RDLVL_DISABLE_DFS
+
+#define LPDDR4__DENALI_PI_46__PI_RDLVL_GATE_ON_SREF_EXIT_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_46__PI_RDLVL_GATE_ON_SREF_EXIT_SHIFT 24U
+#define LPDDR4__DENALI_PI_46__PI_RDLVL_GATE_ON_SREF_EXIT_WIDTH 1U
+#define LPDDR4__DENALI_PI_46__PI_RDLVL_GATE_ON_SREF_EXIT_WOCLR 0U
+#define LPDDR4__DENALI_PI_46__PI_RDLVL_GATE_ON_SREF_EXIT_WOSET 0U
+#define LPDDR4__PI_RDLVL_GATE_ON_SREF_EXIT__REG DENALI_PI_46
+#define LPDDR4__PI_RDLVL_GATE_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_46__PI_RDLVL_GATE_ON_SREF_EXIT
+
+#define LPDDR4__DENALI_PI_47_READ_MASK 0x01010101U
+#define LPDDR4__DENALI_PI_47_WRITE_MASK 0x01010101U
+#define LPDDR4__DENALI_PI_47__PI_RDLVL_GATE_DISABLE_DFS_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_47__PI_RDLVL_GATE_DISABLE_DFS_SHIFT 0U
+#define LPDDR4__DENALI_PI_47__PI_RDLVL_GATE_DISABLE_DFS_WIDTH 1U
+#define LPDDR4__DENALI_PI_47__PI_RDLVL_GATE_DISABLE_DFS_WOCLR 0U
+#define LPDDR4__DENALI_PI_47__PI_RDLVL_GATE_DISABLE_DFS_WOSET 0U
+#define LPDDR4__PI_RDLVL_GATE_DISABLE_DFS__REG DENALI_PI_47
+#define LPDDR4__PI_RDLVL_GATE_DISABLE_DFS__FLD LPDDR4__DENALI_PI_47__PI_RDLVL_GATE_DISABLE_DFS
+
+#define LPDDR4__DENALI_PI_47__PI_RDLVL_ON_MPD_EXIT_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_47__PI_RDLVL_ON_MPD_EXIT_SHIFT 8U
+#define LPDDR4__DENALI_PI_47__PI_RDLVL_ON_MPD_EXIT_WIDTH 1U
+#define LPDDR4__DENALI_PI_47__PI_RDLVL_ON_MPD_EXIT_WOCLR 0U
+#define LPDDR4__DENALI_PI_47__PI_RDLVL_ON_MPD_EXIT_WOSET 0U
+#define LPDDR4__PI_RDLVL_ON_MPD_EXIT__REG DENALI_PI_47
+#define LPDDR4__PI_RDLVL_ON_MPD_EXIT__FLD LPDDR4__DENALI_PI_47__PI_RDLVL_ON_MPD_EXIT
+
+#define LPDDR4__DENALI_PI_47__PI_RDLVL_GATE_ON_MPD_EXIT_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_47__PI_RDLVL_GATE_ON_MPD_EXIT_SHIFT 16U
+#define LPDDR4__DENALI_PI_47__PI_RDLVL_GATE_ON_MPD_EXIT_WIDTH 1U
+#define LPDDR4__DENALI_PI_47__PI_RDLVL_GATE_ON_MPD_EXIT_WOCLR 0U
+#define LPDDR4__DENALI_PI_47__PI_RDLVL_GATE_ON_MPD_EXIT_WOSET 0U
+#define LPDDR4__PI_RDLVL_GATE_ON_MPD_EXIT__REG DENALI_PI_47
+#define LPDDR4__PI_RDLVL_GATE_ON_MPD_EXIT__FLD LPDDR4__DENALI_PI_47__PI_RDLVL_GATE_ON_MPD_EXIT
+
+#define LPDDR4__DENALI_PI_47__PI_RDLVL_ROTATE_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_47__PI_RDLVL_ROTATE_SHIFT 24U
+#define LPDDR4__DENALI_PI_47__PI_RDLVL_ROTATE_WIDTH 1U
+#define LPDDR4__DENALI_PI_47__PI_RDLVL_ROTATE_WOCLR 0U
+#define LPDDR4__DENALI_PI_47__PI_RDLVL_ROTATE_WOSET 0U
+#define LPDDR4__PI_RDLVL_ROTATE__REG DENALI_PI_47
+#define LPDDR4__PI_RDLVL_ROTATE__FLD LPDDR4__DENALI_PI_47__PI_RDLVL_ROTATE
+
+#define LPDDR4__DENALI_PI_48_READ_MASK 0x000F0F01U
+#define LPDDR4__DENALI_PI_48_WRITE_MASK 0x000F0F01U
+#define LPDDR4__DENALI_PI_48__PI_RDLVL_GATE_ROTATE_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_48__PI_RDLVL_GATE_ROTATE_SHIFT 0U
+#define LPDDR4__DENALI_PI_48__PI_RDLVL_GATE_ROTATE_WIDTH 1U
+#define LPDDR4__DENALI_PI_48__PI_RDLVL_GATE_ROTATE_WOCLR 0U
+#define LPDDR4__DENALI_PI_48__PI_RDLVL_GATE_ROTATE_WOSET 0U
+#define LPDDR4__PI_RDLVL_GATE_ROTATE__REG DENALI_PI_48
+#define LPDDR4__PI_RDLVL_GATE_ROTATE__FLD LPDDR4__DENALI_PI_48__PI_RDLVL_GATE_ROTATE
+
+#define LPDDR4__DENALI_PI_48__PI_RDLVL_CS_MAP_MASK 0x00000F00U
+#define LPDDR4__DENALI_PI_48__PI_RDLVL_CS_MAP_SHIFT 8U
+#define LPDDR4__DENALI_PI_48__PI_RDLVL_CS_MAP_WIDTH 4U
+#define LPDDR4__PI_RDLVL_CS_MAP__REG DENALI_PI_48
+#define LPDDR4__PI_RDLVL_CS_MAP__FLD LPDDR4__DENALI_PI_48__PI_RDLVL_CS_MAP
+
+#define LPDDR4__DENALI_PI_48__PI_RDLVL_GATE_CS_MAP_MASK 0x000F0000U
+#define LPDDR4__DENALI_PI_48__PI_RDLVL_GATE_CS_MAP_SHIFT 16U
+#define LPDDR4__DENALI_PI_48__PI_RDLVL_GATE_CS_MAP_WIDTH 4U
+#define LPDDR4__PI_RDLVL_GATE_CS_MAP__REG DENALI_PI_48
+#define LPDDR4__PI_RDLVL_GATE_CS_MAP__FLD LPDDR4__DENALI_PI_48__PI_RDLVL_GATE_CS_MAP
+
+#define LPDDR4__DENALI_PI_49_READ_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_49_WRITE_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_49__PI_TDFI_RDLVL_RR_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_49__PI_TDFI_RDLVL_RR_SHIFT 0U
+#define LPDDR4__DENALI_PI_49__PI_TDFI_RDLVL_RR_WIDTH 10U
+#define LPDDR4__PI_TDFI_RDLVL_RR__REG DENALI_PI_49
+#define LPDDR4__PI_TDFI_RDLVL_RR__FLD LPDDR4__DENALI_PI_49__PI_TDFI_RDLVL_RR
+
+#define LPDDR4__DENALI_PI_50_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_50_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_50__PI_TDFI_RDLVL_RESP_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_50__PI_TDFI_RDLVL_RESP_SHIFT 0U
+#define LPDDR4__DENALI_PI_50__PI_TDFI_RDLVL_RESP_WIDTH 32U
+#define LPDDR4__PI_TDFI_RDLVL_RESP__REG DENALI_PI_50
+#define LPDDR4__PI_TDFI_RDLVL_RESP__FLD LPDDR4__DENALI_PI_50__PI_TDFI_RDLVL_RESP
+
+#define LPDDR4__DENALI_PI_51_READ_MASK 0x0000FF0FU
+#define LPDDR4__DENALI_PI_51_WRITE_MASK 0x0000FF0FU
+#define LPDDR4__DENALI_PI_51__PI_RDLVL_RESP_MASK_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_51__PI_RDLVL_RESP_MASK_SHIFT 0U
+#define LPDDR4__DENALI_PI_51__PI_RDLVL_RESP_MASK_WIDTH 4U
+#define LPDDR4__PI_RDLVL_RESP_MASK__REG DENALI_PI_51
+#define LPDDR4__PI_RDLVL_RESP_MASK__FLD LPDDR4__DENALI_PI_51__PI_RDLVL_RESP_MASK
+
+#define LPDDR4__DENALI_PI_51__PI_TDFI_RDLVL_EN_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_51__PI_TDFI_RDLVL_EN_SHIFT 8U
+#define LPDDR4__DENALI_PI_51__PI_TDFI_RDLVL_EN_WIDTH 8U
+#define LPDDR4__PI_TDFI_RDLVL_EN__REG DENALI_PI_51
+#define LPDDR4__PI_TDFI_RDLVL_EN__FLD LPDDR4__DENALI_PI_51__PI_TDFI_RDLVL_EN
+
+#define LPDDR4__DENALI_PI_52_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_52_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_52__PI_TDFI_RDLVL_MAX_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_52__PI_TDFI_RDLVL_MAX_SHIFT 0U
+#define LPDDR4__DENALI_PI_52__PI_TDFI_RDLVL_MAX_WIDTH 32U
+#define LPDDR4__PI_TDFI_RDLVL_MAX__REG DENALI_PI_52
+#define LPDDR4__PI_TDFI_RDLVL_MAX__FLD LPDDR4__DENALI_PI_52__PI_TDFI_RDLVL_MAX
+
+#define LPDDR4__DENALI_PI_53_READ_MASK 0x00FFFF01U
+#define LPDDR4__DENALI_PI_53_WRITE_MASK 0x00FFFF01U
+#define LPDDR4__DENALI_PI_53__PI_RDLVL_ERROR_STATUS_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_53__PI_RDLVL_ERROR_STATUS_SHIFT 0U
+#define LPDDR4__DENALI_PI_53__PI_RDLVL_ERROR_STATUS_WIDTH 1U
+#define LPDDR4__DENALI_PI_53__PI_RDLVL_ERROR_STATUS_WOCLR 0U
+#define LPDDR4__DENALI_PI_53__PI_RDLVL_ERROR_STATUS_WOSET 0U
+#define LPDDR4__PI_RDLVL_ERROR_STATUS__REG DENALI_PI_53
+#define LPDDR4__PI_RDLVL_ERROR_STATUS__FLD LPDDR4__DENALI_PI_53__PI_RDLVL_ERROR_STATUS
+
+#define LPDDR4__DENALI_PI_53__PI_RDLVL_INTERVAL_MASK 0x00FFFF00U
+#define LPDDR4__DENALI_PI_53__PI_RDLVL_INTERVAL_SHIFT 8U
+#define LPDDR4__DENALI_PI_53__PI_RDLVL_INTERVAL_WIDTH 16U
+#define LPDDR4__PI_RDLVL_INTERVAL__REG DENALI_PI_53
+#define LPDDR4__PI_RDLVL_INTERVAL__FLD LPDDR4__DENALI_PI_53__PI_RDLVL_INTERVAL
+
+#define LPDDR4__DENALI_PI_54_READ_MASK 0x0F0FFFFFU
+#define LPDDR4__DENALI_PI_54_WRITE_MASK 0x0F0FFFFFU
+#define LPDDR4__DENALI_PI_54__PI_RDLVL_GATE_INTERVAL_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PI_54__PI_RDLVL_GATE_INTERVAL_SHIFT 0U
+#define LPDDR4__DENALI_PI_54__PI_RDLVL_GATE_INTERVAL_WIDTH 16U
+#define LPDDR4__PI_RDLVL_GATE_INTERVAL__REG DENALI_PI_54
+#define LPDDR4__PI_RDLVL_GATE_INTERVAL__FLD LPDDR4__DENALI_PI_54__PI_RDLVL_GATE_INTERVAL
+
+#define LPDDR4__DENALI_PI_54__PI_RDLVL_PATTERN_START_MASK 0x000F0000U
+#define LPDDR4__DENALI_PI_54__PI_RDLVL_PATTERN_START_SHIFT 16U
+#define LPDDR4__DENALI_PI_54__PI_RDLVL_PATTERN_START_WIDTH 4U
+#define LPDDR4__PI_RDLVL_PATTERN_START__REG DENALI_PI_54
+#define LPDDR4__PI_RDLVL_PATTERN_START__FLD LPDDR4__DENALI_PI_54__PI_RDLVL_PATTERN_START
+
+#define LPDDR4__DENALI_PI_54__PI_RDLVL_PATTERN_NUM_MASK 0x0F000000U
+#define LPDDR4__DENALI_PI_54__PI_RDLVL_PATTERN_NUM_SHIFT 24U
+#define LPDDR4__DENALI_PI_54__PI_RDLVL_PATTERN_NUM_WIDTH 4U
+#define LPDDR4__PI_RDLVL_PATTERN_NUM__REG DENALI_PI_54
+#define LPDDR4__PI_RDLVL_PATTERN_NUM__FLD LPDDR4__DENALI_PI_54__PI_RDLVL_PATTERN_NUM
+
+#define LPDDR4__DENALI_PI_55_READ_MASK 0x01011F1FU
+#define LPDDR4__DENALI_PI_55_WRITE_MASK 0x01011F1FU
+#define LPDDR4__DENALI_PI_55__PI_RDLVL_STROBE_NUM_MASK 0x0000001FU
+#define LPDDR4__DENALI_PI_55__PI_RDLVL_STROBE_NUM_SHIFT 0U
+#define LPDDR4__DENALI_PI_55__PI_RDLVL_STROBE_NUM_WIDTH 5U
+#define LPDDR4__PI_RDLVL_STROBE_NUM__REG DENALI_PI_55
+#define LPDDR4__PI_RDLVL_STROBE_NUM__FLD LPDDR4__DENALI_PI_55__PI_RDLVL_STROBE_NUM
+
+#define LPDDR4__DENALI_PI_55__PI_RDLVL_GATE_STROBE_NUM_MASK 0x00001F00U
+#define LPDDR4__DENALI_PI_55__PI_RDLVL_GATE_STROBE_NUM_SHIFT 8U
+#define LPDDR4__DENALI_PI_55__PI_RDLVL_GATE_STROBE_NUM_WIDTH 5U
+#define LPDDR4__PI_RDLVL_GATE_STROBE_NUM__REG DENALI_PI_55
+#define LPDDR4__PI_RDLVL_GATE_STROBE_NUM__FLD LPDDR4__DENALI_PI_55__PI_RDLVL_GATE_STROBE_NUM
+
+#define LPDDR4__DENALI_PI_55__PI_RD_PREAMBLE_TRAINING_EN_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_55__PI_RD_PREAMBLE_TRAINING_EN_SHIFT 16U
+#define LPDDR4__DENALI_PI_55__PI_RD_PREAMBLE_TRAINING_EN_WIDTH 1U
+#define LPDDR4__DENALI_PI_55__PI_RD_PREAMBLE_TRAINING_EN_WOCLR 0U
+#define LPDDR4__DENALI_PI_55__PI_RD_PREAMBLE_TRAINING_EN_WOSET 0U
+#define LPDDR4__PI_RD_PREAMBLE_TRAINING_EN__REG DENALI_PI_55
+#define LPDDR4__PI_RD_PREAMBLE_TRAINING_EN__FLD LPDDR4__DENALI_PI_55__PI_RD_PREAMBLE_TRAINING_EN
+
+#define LPDDR4__DENALI_PI_55__PI_REG_DIMM_ENABLE_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_55__PI_REG_DIMM_ENABLE_SHIFT 24U
+#define LPDDR4__DENALI_PI_55__PI_REG_DIMM_ENABLE_WIDTH 1U
+#define LPDDR4__DENALI_PI_55__PI_REG_DIMM_ENABLE_WOCLR 0U
+#define LPDDR4__DENALI_PI_55__PI_REG_DIMM_ENABLE_WOSET 0U
+#define LPDDR4__PI_REG_DIMM_ENABLE__REG DENALI_PI_55
+#define LPDDR4__PI_REG_DIMM_ENABLE__FLD LPDDR4__DENALI_PI_55__PI_REG_DIMM_ENABLE
+
+#define LPDDR4__DENALI_PI_56_READ_MASK 0x0F00FFFFU
+#define LPDDR4__DENALI_PI_56_WRITE_MASK 0x0F00FFFFU
+#define LPDDR4__DENALI_PI_56__PI_TDFI_RDDATA_EN_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_56__PI_TDFI_RDDATA_EN_SHIFT 0U
+#define LPDDR4__DENALI_PI_56__PI_TDFI_RDDATA_EN_WIDTH 8U
+#define LPDDR4__PI_TDFI_RDDATA_EN__REG DENALI_PI_56
+#define LPDDR4__PI_TDFI_RDDATA_EN__FLD LPDDR4__DENALI_PI_56__PI_TDFI_RDDATA_EN
+
+#define LPDDR4__DENALI_PI_56__PI_TDFI_PHY_WRLAT_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_56__PI_TDFI_PHY_WRLAT_SHIFT 8U
+#define LPDDR4__DENALI_PI_56__PI_TDFI_PHY_WRLAT_WIDTH 8U
+#define LPDDR4__PI_TDFI_PHY_WRLAT__REG DENALI_PI_56
+#define LPDDR4__PI_TDFI_PHY_WRLAT__FLD LPDDR4__DENALI_PI_56__PI_TDFI_PHY_WRLAT
+
+#define LPDDR4__DENALI_PI_56__PI_CALVL_REQ_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_56__PI_CALVL_REQ_SHIFT 16U
+#define LPDDR4__DENALI_PI_56__PI_CALVL_REQ_WIDTH 1U
+#define LPDDR4__DENALI_PI_56__PI_CALVL_REQ_WOCLR 0U
+#define LPDDR4__DENALI_PI_56__PI_CALVL_REQ_WOSET 0U
+#define LPDDR4__PI_CALVL_REQ__REG DENALI_PI_56
+#define LPDDR4__PI_CALVL_REQ__FLD LPDDR4__DENALI_PI_56__PI_CALVL_REQ
+
+#define LPDDR4__DENALI_PI_56__PI_CALVL_CS_SW_MASK 0x0F000000U
+#define LPDDR4__DENALI_PI_56__PI_CALVL_CS_SW_SHIFT 24U
+#define LPDDR4__DENALI_PI_56__PI_CALVL_CS_SW_WIDTH 4U
+#define LPDDR4__PI_CALVL_CS_SW__REG DENALI_PI_56
+#define LPDDR4__PI_CALVL_CS_SW__FLD LPDDR4__DENALI_PI_56__PI_CALVL_CS_SW
+
+#define LPDDR4__DENALI_PI_57_READ_MASK 0x030F0103U
+#define LPDDR4__DENALI_PI_57_WRITE_MASK 0x030F0103U
+#define LPDDR4__DENALI_PI_57__PI_CALVL_CS_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_57__PI_CALVL_CS_SHIFT 0U
+#define LPDDR4__DENALI_PI_57__PI_CALVL_CS_WIDTH 2U
+#define LPDDR4__PI_CALVL_CS__REG DENALI_PI_57
+#define LPDDR4__PI_CALVL_CS__FLD LPDDR4__DENALI_PI_57__PI_CALVL_CS
+
+#define LPDDR4__DENALI_PI_57__PI_RESERVED5_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_57__PI_RESERVED5_SHIFT 8U
+#define LPDDR4__DENALI_PI_57__PI_RESERVED5_WIDTH 1U
+#define LPDDR4__DENALI_PI_57__PI_RESERVED5_WOCLR 0U
+#define LPDDR4__DENALI_PI_57__PI_RESERVED5_WOSET 0U
+#define LPDDR4__PI_RESERVED5__REG DENALI_PI_57
+#define LPDDR4__PI_RESERVED5__FLD LPDDR4__DENALI_PI_57__PI_RESERVED5
+
+#define LPDDR4__DENALI_PI_57__PI_RESERVED6_MASK 0x000F0000U
+#define LPDDR4__DENALI_PI_57__PI_RESERVED6_SHIFT 16U
+#define LPDDR4__DENALI_PI_57__PI_RESERVED6_WIDTH 4U
+#define LPDDR4__PI_RESERVED6__REG DENALI_PI_57
+#define LPDDR4__PI_RESERVED6__FLD LPDDR4__DENALI_PI_57__PI_RESERVED6
+
+#define LPDDR4__DENALI_PI_57__PI_CALVL_SEQ_EN_MASK 0x03000000U
+#define LPDDR4__DENALI_PI_57__PI_CALVL_SEQ_EN_SHIFT 24U
+#define LPDDR4__DENALI_PI_57__PI_CALVL_SEQ_EN_WIDTH 2U
+#define LPDDR4__PI_CALVL_SEQ_EN__REG DENALI_PI_57
+#define LPDDR4__PI_CALVL_SEQ_EN__FLD LPDDR4__DENALI_PI_57__PI_CALVL_SEQ_EN
+
+#define LPDDR4__DENALI_PI_58_READ_MASK 0x01010101U
+#define LPDDR4__DENALI_PI_58_WRITE_MASK 0x01010101U
+#define LPDDR4__DENALI_PI_58__PI_CALVL_PERIODIC_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_58__PI_CALVL_PERIODIC_SHIFT 0U
+#define LPDDR4__DENALI_PI_58__PI_CALVL_PERIODIC_WIDTH 1U
+#define LPDDR4__DENALI_PI_58__PI_CALVL_PERIODIC_WOCLR 0U
+#define LPDDR4__DENALI_PI_58__PI_CALVL_PERIODIC_WOSET 0U
+#define LPDDR4__PI_CALVL_PERIODIC__REG DENALI_PI_58
+#define LPDDR4__PI_CALVL_PERIODIC__FLD LPDDR4__DENALI_PI_58__PI_CALVL_PERIODIC
+
+#define LPDDR4__DENALI_PI_58__PI_CALVL_ON_SREF_EXIT_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_58__PI_CALVL_ON_SREF_EXIT_SHIFT 8U
+#define LPDDR4__DENALI_PI_58__PI_CALVL_ON_SREF_EXIT_WIDTH 1U
+#define LPDDR4__DENALI_PI_58__PI_CALVL_ON_SREF_EXIT_WOCLR 0U
+#define LPDDR4__DENALI_PI_58__PI_CALVL_ON_SREF_EXIT_WOSET 0U
+#define LPDDR4__PI_CALVL_ON_SREF_EXIT__REG DENALI_PI_58
+#define LPDDR4__PI_CALVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_58__PI_CALVL_ON_SREF_EXIT
+
+#define LPDDR4__DENALI_PI_58__PI_CALVL_DISABLE_DFS_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_58__PI_CALVL_DISABLE_DFS_SHIFT 16U
+#define LPDDR4__DENALI_PI_58__PI_CALVL_DISABLE_DFS_WIDTH 1U
+#define LPDDR4__DENALI_PI_58__PI_CALVL_DISABLE_DFS_WOCLR 0U
+#define LPDDR4__DENALI_PI_58__PI_CALVL_DISABLE_DFS_WOSET 0U
+#define LPDDR4__PI_CALVL_DISABLE_DFS__REG DENALI_PI_58
+#define LPDDR4__PI_CALVL_DISABLE_DFS__FLD LPDDR4__DENALI_PI_58__PI_CALVL_DISABLE_DFS
+
+#define LPDDR4__DENALI_PI_58__PI_CALVL_ROTATE_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_58__PI_CALVL_ROTATE_SHIFT 24U
+#define LPDDR4__DENALI_PI_58__PI_CALVL_ROTATE_WIDTH 1U
+#define LPDDR4__DENALI_PI_58__PI_CALVL_ROTATE_WOCLR 0U
+#define LPDDR4__DENALI_PI_58__PI_CALVL_ROTATE_WOSET 0U
+#define LPDDR4__PI_CALVL_ROTATE__REG DENALI_PI_58
+#define LPDDR4__PI_CALVL_ROTATE__FLD LPDDR4__DENALI_PI_58__PI_CALVL_ROTATE
+
+#define LPDDR4__DENALI_PI_59_READ_MASK 0x0000FF0FU
+#define LPDDR4__DENALI_PI_59_WRITE_MASK 0x0000FF0FU
+#define LPDDR4__DENALI_PI_59__PI_CALVL_CS_MAP_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_59__PI_CALVL_CS_MAP_SHIFT 0U
+#define LPDDR4__DENALI_PI_59__PI_CALVL_CS_MAP_WIDTH 4U
+#define LPDDR4__PI_CALVL_CS_MAP__REG DENALI_PI_59
+#define LPDDR4__PI_CALVL_CS_MAP__FLD LPDDR4__DENALI_PI_59__PI_CALVL_CS_MAP
+
+#define LPDDR4__DENALI_PI_59__PI_TDFI_CALVL_EN_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_59__PI_TDFI_CALVL_EN_SHIFT 8U
+#define LPDDR4__DENALI_PI_59__PI_TDFI_CALVL_EN_WIDTH 8U
+#define LPDDR4__PI_TDFI_CALVL_EN__REG DENALI_PI_59
+#define LPDDR4__PI_TDFI_CALVL_EN__FLD LPDDR4__DENALI_PI_59__PI_TDFI_CALVL_EN
+
+#define LPDDR4__DENALI_PI_60_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_60_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_60__PI_TDFI_CALVL_RESP_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_60__PI_TDFI_CALVL_RESP_SHIFT 0U
+#define LPDDR4__DENALI_PI_60__PI_TDFI_CALVL_RESP_WIDTH 32U
+#define LPDDR4__PI_TDFI_CALVL_RESP__REG DENALI_PI_60
+#define LPDDR4__PI_TDFI_CALVL_RESP__FLD LPDDR4__DENALI_PI_60__PI_TDFI_CALVL_RESP
+
+#define LPDDR4__DENALI_PI_61_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_61_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_61__PI_TDFI_CALVL_MAX_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_61__PI_TDFI_CALVL_MAX_SHIFT 0U
+#define LPDDR4__DENALI_PI_61__PI_TDFI_CALVL_MAX_WIDTH 32U
+#define LPDDR4__PI_TDFI_CALVL_MAX__REG DENALI_PI_61
+#define LPDDR4__PI_TDFI_CALVL_MAX__FLD LPDDR4__DENALI_PI_61__PI_TDFI_CALVL_MAX
+
+#define LPDDR4__DENALI_PI_62_READ_MASK 0xFFFF0301U
+#define LPDDR4__DENALI_PI_62_WRITE_MASK 0xFFFF0301U
+#define LPDDR4__DENALI_PI_62__PI_CALVL_RESP_MASK_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_62__PI_CALVL_RESP_MASK_SHIFT 0U
+#define LPDDR4__DENALI_PI_62__PI_CALVL_RESP_MASK_WIDTH 1U
+#define LPDDR4__DENALI_PI_62__PI_CALVL_RESP_MASK_WOCLR 0U
+#define LPDDR4__DENALI_PI_62__PI_CALVL_RESP_MASK_WOSET 0U
+#define LPDDR4__PI_CALVL_RESP_MASK__REG DENALI_PI_62
+#define LPDDR4__PI_CALVL_RESP_MASK__FLD LPDDR4__DENALI_PI_62__PI_CALVL_RESP_MASK
+
+#define LPDDR4__DENALI_PI_62__PI_CALVL_ERROR_STATUS_MASK 0x00000300U
+#define LPDDR4__DENALI_PI_62__PI_CALVL_ERROR_STATUS_SHIFT 8U
+#define LPDDR4__DENALI_PI_62__PI_CALVL_ERROR_STATUS_WIDTH 2U
+#define LPDDR4__PI_CALVL_ERROR_STATUS__REG DENALI_PI_62
+#define LPDDR4__PI_CALVL_ERROR_STATUS__FLD LPDDR4__DENALI_PI_62__PI_CALVL_ERROR_STATUS
+
+#define LPDDR4__DENALI_PI_62__PI_CALVL_INTERVAL_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_PI_62__PI_CALVL_INTERVAL_SHIFT 16U
+#define LPDDR4__DENALI_PI_62__PI_CALVL_INTERVAL_WIDTH 16U
+#define LPDDR4__PI_CALVL_INTERVAL__REG DENALI_PI_62
+#define LPDDR4__PI_CALVL_INTERVAL__FLD LPDDR4__DENALI_PI_62__PI_CALVL_INTERVAL
+
+#define LPDDR4__DENALI_PI_63_READ_MASK 0x1F1F3F1FU
+#define LPDDR4__DENALI_PI_63_WRITE_MASK 0x1F1F3F1FU
+#define LPDDR4__DENALI_PI_63__PI_TCACKEL_MASK 0x0000001FU
+#define LPDDR4__DENALI_PI_63__PI_TCACKEL_SHIFT 0U
+#define LPDDR4__DENALI_PI_63__PI_TCACKEL_WIDTH 5U
+#define LPDDR4__PI_TCACKEL__REG DENALI_PI_63
+#define LPDDR4__PI_TCACKEL__FLD LPDDR4__DENALI_PI_63__PI_TCACKEL
+
+#define LPDDR4__DENALI_PI_63__PI_TCAMRD_MASK 0x00003F00U
+#define LPDDR4__DENALI_PI_63__PI_TCAMRD_SHIFT 8U
+#define LPDDR4__DENALI_PI_63__PI_TCAMRD_WIDTH 6U
+#define LPDDR4__PI_TCAMRD__REG DENALI_PI_63
+#define LPDDR4__PI_TCAMRD__FLD LPDDR4__DENALI_PI_63__PI_TCAMRD
+
+#define LPDDR4__DENALI_PI_63__PI_TCACKEH_MASK 0x001F0000U
+#define LPDDR4__DENALI_PI_63__PI_TCACKEH_SHIFT 16U
+#define LPDDR4__DENALI_PI_63__PI_TCACKEH_WIDTH 5U
+#define LPDDR4__PI_TCACKEH__REG DENALI_PI_63
+#define LPDDR4__PI_TCACKEH__FLD LPDDR4__DENALI_PI_63__PI_TCACKEH
+
+#define LPDDR4__DENALI_PI_63__PI_TCAEXT_MASK 0x1F000000U
+#define LPDDR4__DENALI_PI_63__PI_TCAEXT_SHIFT 24U
+#define LPDDR4__DENALI_PI_63__PI_TCAEXT_WIDTH 5U
+#define LPDDR4__PI_TCAEXT__REG DENALI_PI_63
+#define LPDDR4__PI_TCAEXT__FLD LPDDR4__DENALI_PI_63__PI_TCAEXT
+
+#define LPDDR4__DENALI_PI_64_READ_MASK 0xFF0F0F01U
+#define LPDDR4__DENALI_PI_64_WRITE_MASK 0xFF0F0F01U
+#define LPDDR4__DENALI_PI_64__PI_CA_TRAIN_VREF_EN_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_64__PI_CA_TRAIN_VREF_EN_SHIFT 0U
+#define LPDDR4__DENALI_PI_64__PI_CA_TRAIN_VREF_EN_WIDTH 1U
+#define LPDDR4__DENALI_PI_64__PI_CA_TRAIN_VREF_EN_WOCLR 0U
+#define LPDDR4__DENALI_PI_64__PI_CA_TRAIN_VREF_EN_WOSET 0U
+#define LPDDR4__PI_CA_TRAIN_VREF_EN__REG DENALI_PI_64
+#define LPDDR4__PI_CA_TRAIN_VREF_EN__FLD LPDDR4__DENALI_PI_64__PI_CA_TRAIN_VREF_EN
+
+#define LPDDR4__DENALI_PI_64__PI_CALVL_VREF_INITIAL_STEPSIZE_MASK 0x00000F00U
+#define LPDDR4__DENALI_PI_64__PI_CALVL_VREF_INITIAL_STEPSIZE_SHIFT 8U
+#define LPDDR4__DENALI_PI_64__PI_CALVL_VREF_INITIAL_STEPSIZE_WIDTH 4U
+#define LPDDR4__PI_CALVL_VREF_INITIAL_STEPSIZE__REG DENALI_PI_64
+#define LPDDR4__PI_CALVL_VREF_INITIAL_STEPSIZE__FLD LPDDR4__DENALI_PI_64__PI_CALVL_VREF_INITIAL_STEPSIZE
+
+#define LPDDR4__DENALI_PI_64__PI_CALVL_VREF_NORMAL_STEPSIZE_MASK 0x000F0000U
+#define LPDDR4__DENALI_PI_64__PI_CALVL_VREF_NORMAL_STEPSIZE_SHIFT 16U
+#define LPDDR4__DENALI_PI_64__PI_CALVL_VREF_NORMAL_STEPSIZE_WIDTH 4U
+#define LPDDR4__PI_CALVL_VREF_NORMAL_STEPSIZE__REG DENALI_PI_64
+#define LPDDR4__PI_CALVL_VREF_NORMAL_STEPSIZE__FLD LPDDR4__DENALI_PI_64__PI_CALVL_VREF_NORMAL_STEPSIZE
+
+#define LPDDR4__DENALI_PI_64__PI_TDFI_INIT_START_MIN_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_64__PI_TDFI_INIT_START_MIN_SHIFT 24U
+#define LPDDR4__DENALI_PI_64__PI_TDFI_INIT_START_MIN_WIDTH 8U
+#define LPDDR4__PI_TDFI_INIT_START_MIN__REG DENALI_PI_64
+#define LPDDR4__PI_TDFI_INIT_START_MIN__FLD LPDDR4__DENALI_PI_64__PI_TDFI_INIT_START_MIN
+
+#define LPDDR4__DENALI_PI_65_READ_MASK 0x017F1FFFU
+#define LPDDR4__DENALI_PI_65_WRITE_MASK 0x017F1FFFU
+#define LPDDR4__DENALI_PI_65__PI_TCKCKEH_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_65__PI_TCKCKEH_SHIFT 0U
+#define LPDDR4__DENALI_PI_65__PI_TCKCKEH_WIDTH 8U
+#define LPDDR4__PI_TCKCKEH__REG DENALI_PI_65
+#define LPDDR4__PI_TCKCKEH__FLD LPDDR4__DENALI_PI_65__PI_TCKCKEH
+
+#define LPDDR4__DENALI_PI_65__PI_CALVL_STROBE_NUM_MASK 0x00001F00U
+#define LPDDR4__DENALI_PI_65__PI_CALVL_STROBE_NUM_SHIFT 8U
+#define LPDDR4__DENALI_PI_65__PI_CALVL_STROBE_NUM_WIDTH 5U
+#define LPDDR4__PI_CALVL_STROBE_NUM__REG DENALI_PI_65
+#define LPDDR4__PI_CALVL_STROBE_NUM__FLD LPDDR4__DENALI_PI_65__PI_CALVL_STROBE_NUM
+
+#define LPDDR4__DENALI_PI_65__PI_SW_CA_TRAIN_VREF_MASK 0x007F0000U
+#define LPDDR4__DENALI_PI_65__PI_SW_CA_TRAIN_VREF_SHIFT 16U
+#define LPDDR4__DENALI_PI_65__PI_SW_CA_TRAIN_VREF_WIDTH 7U
+#define LPDDR4__PI_SW_CA_TRAIN_VREF__REG DENALI_PI_65
+#define LPDDR4__PI_SW_CA_TRAIN_VREF__FLD LPDDR4__DENALI_PI_65__PI_SW_CA_TRAIN_VREF
+
+#define LPDDR4__DENALI_PI_65__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_65__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_SHIFT 24U
+#define LPDDR4__DENALI_PI_65__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_WIDTH 1U
+#define LPDDR4__DENALI_PI_65__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_WOCLR 0U
+#define LPDDR4__DENALI_PI_65__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_WOSET 0U
+#define LPDDR4__PI_REFRESH_BETWEEN_SEGMENT_DISABLE__REG DENALI_PI_65
+#define LPDDR4__PI_REFRESH_BETWEEN_SEGMENT_DISABLE__FLD LPDDR4__DENALI_PI_65__PI_REFRESH_BETWEEN_SEGMENT_DISABLE
+
+#define LPDDR4__DENALI_PI_66_READ_MASK 0xFF01FFFFU
+#define LPDDR4__DENALI_PI_66_WRITE_MASK 0xFF01FFFFU
+#define LPDDR4__DENALI_PI_66__PI_CLKDISABLE_2_INIT_START_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_66__PI_CLKDISABLE_2_INIT_START_SHIFT 0U
+#define LPDDR4__DENALI_PI_66__PI_CLKDISABLE_2_INIT_START_WIDTH 8U
+#define LPDDR4__PI_CLKDISABLE_2_INIT_START__REG DENALI_PI_66
+#define LPDDR4__PI_CLKDISABLE_2_INIT_START__FLD LPDDR4__DENALI_PI_66__PI_CLKDISABLE_2_INIT_START
+
+#define LPDDR4__DENALI_PI_66__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_66__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE_SHIFT 8U
+#define LPDDR4__DENALI_PI_66__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE_WIDTH 8U
+#define LPDDR4__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE__REG DENALI_PI_66
+#define LPDDR4__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE__FLD LPDDR4__DENALI_PI_66__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE
+
+#define LPDDR4__DENALI_PI_66__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_66__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_SHIFT 16U
+#define LPDDR4__DENALI_PI_66__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_WIDTH 1U
+#define LPDDR4__DENALI_PI_66__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_WOCLR 0U
+#define LPDDR4__DENALI_PI_66__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_WOSET 0U
+#define LPDDR4__PI_DRAM_CLK_DISABLE_DEASSERT_SEL__REG DENALI_PI_66
+#define LPDDR4__PI_DRAM_CLK_DISABLE_DEASSERT_SEL__FLD LPDDR4__DENALI_PI_66__PI_DRAM_CLK_DISABLE_DEASSERT_SEL
+
+#define LPDDR4__DENALI_PI_66__PI_TDFI_INIT_COMPLETE_MIN_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_66__PI_TDFI_INIT_COMPLETE_MIN_SHIFT 24U
+#define LPDDR4__DENALI_PI_66__PI_TDFI_INIT_COMPLETE_MIN_WIDTH 8U
+#define LPDDR4__PI_TDFI_INIT_COMPLETE_MIN__REG DENALI_PI_66
+#define LPDDR4__PI_TDFI_INIT_COMPLETE_MIN__FLD LPDDR4__DENALI_PI_66__PI_TDFI_INIT_COMPLETE_MIN
+
+#define LPDDR4__DENALI_PI_67_READ_MASK 0x01010103U
+#define LPDDR4__DENALI_PI_67_WRITE_MASK 0x01010103U
+#define LPDDR4__DENALI_PI_67__PI_VREF_CS_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_67__PI_VREF_CS_SHIFT 0U
+#define LPDDR4__DENALI_PI_67__PI_VREF_CS_WIDTH 2U
+#define LPDDR4__PI_VREF_CS__REG DENALI_PI_67
+#define LPDDR4__PI_VREF_CS__FLD LPDDR4__DENALI_PI_67__PI_VREF_CS
+
+#define LPDDR4__DENALI_PI_67__PI_VREF_PDA_EN_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_67__PI_VREF_PDA_EN_SHIFT 8U
+#define LPDDR4__DENALI_PI_67__PI_VREF_PDA_EN_WIDTH 1U
+#define LPDDR4__DENALI_PI_67__PI_VREF_PDA_EN_WOCLR 0U
+#define LPDDR4__DENALI_PI_67__PI_VREF_PDA_EN_WOSET 0U
+#define LPDDR4__PI_VREF_PDA_EN__REG DENALI_PI_67
+#define LPDDR4__PI_VREF_PDA_EN__FLD LPDDR4__DENALI_PI_67__PI_VREF_PDA_EN
+
+#define LPDDR4__DENALI_PI_67__PI_VREFLVL_DISABLE_DFS_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_67__PI_VREFLVL_DISABLE_DFS_SHIFT 16U
+#define LPDDR4__DENALI_PI_67__PI_VREFLVL_DISABLE_DFS_WIDTH 1U
+#define LPDDR4__DENALI_PI_67__PI_VREFLVL_DISABLE_DFS_WOCLR 0U
+#define LPDDR4__DENALI_PI_67__PI_VREFLVL_DISABLE_DFS_WOSET 0U
+#define LPDDR4__PI_VREFLVL_DISABLE_DFS__REG DENALI_PI_67
+#define LPDDR4__PI_VREFLVL_DISABLE_DFS__FLD LPDDR4__DENALI_PI_67__PI_VREFLVL_DISABLE_DFS
+
+#define LPDDR4__DENALI_PI_67__PI_MC_DFS_PI_SET_VREF_ENABLE_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_67__PI_MC_DFS_PI_SET_VREF_ENABLE_SHIFT 24U
+#define LPDDR4__DENALI_PI_67__PI_MC_DFS_PI_SET_VREF_ENABLE_WIDTH 1U
+#define LPDDR4__DENALI_PI_67__PI_MC_DFS_PI_SET_VREF_ENABLE_WOCLR 0U
+#define LPDDR4__DENALI_PI_67__PI_MC_DFS_PI_SET_VREF_ENABLE_WOSET 0U
+#define LPDDR4__PI_MC_DFS_PI_SET_VREF_ENABLE__REG DENALI_PI_67
+#define LPDDR4__PI_MC_DFS_PI_SET_VREF_ENABLE__FLD LPDDR4__DENALI_PI_67__PI_MC_DFS_PI_SET_VREF_ENABLE
+
+#define LPDDR4__DENALI_PI_68_READ_MASK 0x0F0701FFU
+#define LPDDR4__DENALI_PI_68_WRITE_MASK 0x0F0701FFU
+#define LPDDR4__DENALI_PI_68__PI_INIT_COMPLETE_TO_MC_DELAY_COUNT_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_68__PI_INIT_COMPLETE_TO_MC_DELAY_COUNT_SHIFT 0U
+#define LPDDR4__DENALI_PI_68__PI_INIT_COMPLETE_TO_MC_DELAY_COUNT_WIDTH 8U
+#define LPDDR4__PI_INIT_COMPLETE_TO_MC_DELAY_COUNT__REG DENALI_PI_68
+#define LPDDR4__PI_INIT_COMPLETE_TO_MC_DELAY_COUNT__FLD LPDDR4__DENALI_PI_68__PI_INIT_COMPLETE_TO_MC_DELAY_COUNT
+
+#define LPDDR4__DENALI_PI_68__PI_WDQLVL_VREF_EN_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_68__PI_WDQLVL_VREF_EN_SHIFT 8U
+#define LPDDR4__DENALI_PI_68__PI_WDQLVL_VREF_EN_WIDTH 1U
+#define LPDDR4__DENALI_PI_68__PI_WDQLVL_VREF_EN_WOCLR 0U
+#define LPDDR4__DENALI_PI_68__PI_WDQLVL_VREF_EN_WOSET 0U
+#define LPDDR4__PI_WDQLVL_VREF_EN__REG DENALI_PI_68
+#define LPDDR4__PI_WDQLVL_VREF_EN__FLD LPDDR4__DENALI_PI_68__PI_WDQLVL_VREF_EN
+
+#define LPDDR4__DENALI_PI_68__PI_WDQLVL_BST_NUM_MASK 0x00070000U
+#define LPDDR4__DENALI_PI_68__PI_WDQLVL_BST_NUM_SHIFT 16U
+#define LPDDR4__DENALI_PI_68__PI_WDQLVL_BST_NUM_WIDTH 3U
+#define LPDDR4__PI_WDQLVL_BST_NUM__REG DENALI_PI_68
+#define LPDDR4__PI_WDQLVL_BST_NUM__FLD LPDDR4__DENALI_PI_68__PI_WDQLVL_BST_NUM
+
+#define LPDDR4__DENALI_PI_68__PI_WDQLVL_RESP_MASK_MASK 0x0F000000U
+#define LPDDR4__DENALI_PI_68__PI_WDQLVL_RESP_MASK_SHIFT 24U
+#define LPDDR4__DENALI_PI_68__PI_WDQLVL_RESP_MASK_WIDTH 4U
+#define LPDDR4__PI_WDQLVL_RESP_MASK__REG DENALI_PI_68
+#define LPDDR4__PI_WDQLVL_RESP_MASK__FLD LPDDR4__DENALI_PI_68__PI_WDQLVL_RESP_MASK
+
+#define LPDDR4__DENALI_PI_69_READ_MASK 0x1F1F0F01U
+#define LPDDR4__DENALI_PI_69_WRITE_MASK 0x1F1F0F01U
+#define LPDDR4__DENALI_PI_69__PI_WDQLVL_ROTATE_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_69__PI_WDQLVL_ROTATE_SHIFT 0U
+#define LPDDR4__DENALI_PI_69__PI_WDQLVL_ROTATE_WIDTH 1U
+#define LPDDR4__DENALI_PI_69__PI_WDQLVL_ROTATE_WOCLR 0U
+#define LPDDR4__DENALI_PI_69__PI_WDQLVL_ROTATE_WOSET 0U
+#define LPDDR4__PI_WDQLVL_ROTATE__REG DENALI_PI_69
+#define LPDDR4__PI_WDQLVL_ROTATE__FLD LPDDR4__DENALI_PI_69__PI_WDQLVL_ROTATE
+
+#define LPDDR4__DENALI_PI_69__PI_WDQLVL_CS_MAP_MASK 0x00000F00U
+#define LPDDR4__DENALI_PI_69__PI_WDQLVL_CS_MAP_SHIFT 8U
+#define LPDDR4__DENALI_PI_69__PI_WDQLVL_CS_MAP_WIDTH 4U
+#define LPDDR4__PI_WDQLVL_CS_MAP__REG DENALI_PI_69
+#define LPDDR4__PI_WDQLVL_CS_MAP__FLD LPDDR4__DENALI_PI_69__PI_WDQLVL_CS_MAP
+
+#define LPDDR4__DENALI_PI_69__PI_WDQLVL_VREF_INITIAL_STEPSIZE_MASK 0x001F0000U
+#define LPDDR4__DENALI_PI_69__PI_WDQLVL_VREF_INITIAL_STEPSIZE_SHIFT 16U
+#define LPDDR4__DENALI_PI_69__PI_WDQLVL_VREF_INITIAL_STEPSIZE_WIDTH 5U
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STEPSIZE__REG DENALI_PI_69
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STEPSIZE__FLD LPDDR4__DENALI_PI_69__PI_WDQLVL_VREF_INITIAL_STEPSIZE
+
+#define LPDDR4__DENALI_PI_69__PI_WDQLVL_VREF_NORMAL_STEPSIZE_MASK 0x1F000000U
+#define LPDDR4__DENALI_PI_69__PI_WDQLVL_VREF_NORMAL_STEPSIZE_SHIFT 24U
+#define LPDDR4__DENALI_PI_69__PI_WDQLVL_VREF_NORMAL_STEPSIZE_WIDTH 5U
+#define LPDDR4__PI_WDQLVL_VREF_NORMAL_STEPSIZE__REG DENALI_PI_69
+#define LPDDR4__PI_WDQLVL_VREF_NORMAL_STEPSIZE__FLD LPDDR4__DENALI_PI_69__PI_WDQLVL_VREF_NORMAL_STEPSIZE
+
+#define LPDDR4__DENALI_PI_70_READ_MASK 0x030F0001U
+#define LPDDR4__DENALI_PI_70_WRITE_MASK 0x030F0001U
+#define LPDDR4__DENALI_PI_70__PI_WDQLVL_PERIODIC_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_70__PI_WDQLVL_PERIODIC_SHIFT 0U
+#define LPDDR4__DENALI_PI_70__PI_WDQLVL_PERIODIC_WIDTH 1U
+#define LPDDR4__DENALI_PI_70__PI_WDQLVL_PERIODIC_WOCLR 0U
+#define LPDDR4__DENALI_PI_70__PI_WDQLVL_PERIODIC_WOSET 0U
+#define LPDDR4__PI_WDQLVL_PERIODIC__REG DENALI_PI_70
+#define LPDDR4__PI_WDQLVL_PERIODIC__FLD LPDDR4__DENALI_PI_70__PI_WDQLVL_PERIODIC
+
+#define LPDDR4__DENALI_PI_70__PI_WDQLVL_REQ_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_70__PI_WDQLVL_REQ_SHIFT 8U
+#define LPDDR4__DENALI_PI_70__PI_WDQLVL_REQ_WIDTH 1U
+#define LPDDR4__DENALI_PI_70__PI_WDQLVL_REQ_WOCLR 0U
+#define LPDDR4__DENALI_PI_70__PI_WDQLVL_REQ_WOSET 0U
+#define LPDDR4__PI_WDQLVL_REQ__REG DENALI_PI_70
+#define LPDDR4__PI_WDQLVL_REQ__FLD LPDDR4__DENALI_PI_70__PI_WDQLVL_REQ
+
+#define LPDDR4__DENALI_PI_70__PI_WDQLVL_CS_SW_MASK 0x000F0000U
+#define LPDDR4__DENALI_PI_70__PI_WDQLVL_CS_SW_SHIFT 16U
+#define LPDDR4__DENALI_PI_70__PI_WDQLVL_CS_SW_WIDTH 4U
+#define LPDDR4__PI_WDQLVL_CS_SW__REG DENALI_PI_70
+#define LPDDR4__PI_WDQLVL_CS_SW__FLD LPDDR4__DENALI_PI_70__PI_WDQLVL_CS_SW
+
+#define LPDDR4__DENALI_PI_70__PI_WDQLVL_CS_MASK 0x03000000U
+#define LPDDR4__DENALI_PI_70__PI_WDQLVL_CS_SHIFT 24U
+#define LPDDR4__DENALI_PI_70__PI_WDQLVL_CS_WIDTH 2U
+#define LPDDR4__PI_WDQLVL_CS__REG DENALI_PI_70
+#define LPDDR4__PI_WDQLVL_CS__FLD LPDDR4__DENALI_PI_70__PI_WDQLVL_CS
+
+#define LPDDR4__DENALI_PI_71_READ_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_71_WRITE_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_71__PI_TDFI_WDQLVL_EN_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_71__PI_TDFI_WDQLVL_EN_SHIFT 0U
+#define LPDDR4__DENALI_PI_71__PI_TDFI_WDQLVL_EN_WIDTH 8U
+#define LPDDR4__PI_TDFI_WDQLVL_EN__REG DENALI_PI_71
+#define LPDDR4__PI_TDFI_WDQLVL_EN__FLD LPDDR4__DENALI_PI_71__PI_TDFI_WDQLVL_EN
+
+#define LPDDR4__DENALI_PI_72_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_72_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_72__PI_TDFI_WDQLVL_RESP_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_72__PI_TDFI_WDQLVL_RESP_SHIFT 0U
+#define LPDDR4__DENALI_PI_72__PI_TDFI_WDQLVL_RESP_WIDTH 32U
+#define LPDDR4__PI_TDFI_WDQLVL_RESP__REG DENALI_PI_72
+#define LPDDR4__PI_TDFI_WDQLVL_RESP__FLD LPDDR4__DENALI_PI_72__PI_TDFI_WDQLVL_RESP
+
+#define LPDDR4__DENALI_PI_73_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_73_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_73__PI_TDFI_WDQLVL_MAX_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_73__PI_TDFI_WDQLVL_MAX_SHIFT 0U
+#define LPDDR4__DENALI_PI_73__PI_TDFI_WDQLVL_MAX_WIDTH 32U
+#define LPDDR4__PI_TDFI_WDQLVL_MAX__REG DENALI_PI_73
+#define LPDDR4__PI_TDFI_WDQLVL_MAX__FLD LPDDR4__DENALI_PI_73__PI_TDFI_WDQLVL_MAX
+
+#define LPDDR4__DENALI_PI_74_READ_MASK 0x0101FFFFU
+#define LPDDR4__DENALI_PI_74_WRITE_MASK 0x0101FFFFU
+#define LPDDR4__DENALI_PI_74__PI_WDQLVL_INTERVAL_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PI_74__PI_WDQLVL_INTERVAL_SHIFT 0U
+#define LPDDR4__DENALI_PI_74__PI_WDQLVL_INTERVAL_WIDTH 16U
+#define LPDDR4__PI_WDQLVL_INTERVAL__REG DENALI_PI_74
+#define LPDDR4__PI_WDQLVL_INTERVAL__FLD LPDDR4__DENALI_PI_74__PI_WDQLVL_INTERVAL
+
+#define LPDDR4__DENALI_PI_74__PI_WDQLVL_ON_SREF_EXIT_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_74__PI_WDQLVL_ON_SREF_EXIT_SHIFT 16U
+#define LPDDR4__DENALI_PI_74__PI_WDQLVL_ON_SREF_EXIT_WIDTH 1U
+#define LPDDR4__DENALI_PI_74__PI_WDQLVL_ON_SREF_EXIT_WOCLR 0U
+#define LPDDR4__DENALI_PI_74__PI_WDQLVL_ON_SREF_EXIT_WOSET 0U
+#define LPDDR4__PI_WDQLVL_ON_SREF_EXIT__REG DENALI_PI_74
+#define LPDDR4__PI_WDQLVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_74__PI_WDQLVL_ON_SREF_EXIT
+
+#define LPDDR4__DENALI_PI_74__PI_WDQLVL_ON_MPD_EXIT_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_74__PI_WDQLVL_ON_MPD_EXIT_SHIFT 24U
+#define LPDDR4__DENALI_PI_74__PI_WDQLVL_ON_MPD_EXIT_WIDTH 1U
+#define LPDDR4__DENALI_PI_74__PI_WDQLVL_ON_MPD_EXIT_WOCLR 0U
+#define LPDDR4__DENALI_PI_74__PI_WDQLVL_ON_MPD_EXIT_WOSET 0U
+#define LPDDR4__PI_WDQLVL_ON_MPD_EXIT__REG DENALI_PI_74
+#define LPDDR4__PI_WDQLVL_ON_MPD_EXIT__FLD LPDDR4__DENALI_PI_74__PI_WDQLVL_ON_MPD_EXIT
+
+#define LPDDR4__DENALI_PI_75_READ_MASK 0x00030301U
+#define LPDDR4__DENALI_PI_75_WRITE_MASK 0x00030301U
+#define LPDDR4__DENALI_PI_75__PI_WDQLVL_DISABLE_DFS_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_75__PI_WDQLVL_DISABLE_DFS_SHIFT 0U
+#define LPDDR4__DENALI_PI_75__PI_WDQLVL_DISABLE_DFS_WIDTH 1U
+#define LPDDR4__DENALI_PI_75__PI_WDQLVL_DISABLE_DFS_WOCLR 0U
+#define LPDDR4__DENALI_PI_75__PI_WDQLVL_DISABLE_DFS_WOSET 0U
+#define LPDDR4__PI_WDQLVL_DISABLE_DFS__REG DENALI_PI_75
+#define LPDDR4__PI_WDQLVL_DISABLE_DFS__FLD LPDDR4__DENALI_PI_75__PI_WDQLVL_DISABLE_DFS
+
+#define LPDDR4__DENALI_PI_75__PI_WDQLVL_ERROR_STATUS_MASK 0x00000300U
+#define LPDDR4__DENALI_PI_75__PI_WDQLVL_ERROR_STATUS_SHIFT 8U
+#define LPDDR4__DENALI_PI_75__PI_WDQLVL_ERROR_STATUS_WIDTH 2U
+#define LPDDR4__PI_WDQLVL_ERROR_STATUS__REG DENALI_PI_75
+#define LPDDR4__PI_WDQLVL_ERROR_STATUS__FLD LPDDR4__DENALI_PI_75__PI_WDQLVL_ERROR_STATUS
+
+#define LPDDR4__DENALI_PI_75__PI_WDQLVL_NEED_SAVE_RESTORE_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_75__PI_WDQLVL_NEED_SAVE_RESTORE_SHIFT 16U
+#define LPDDR4__DENALI_PI_75__PI_WDQLVL_NEED_SAVE_RESTORE_WIDTH 2U
+#define LPDDR4__PI_WDQLVL_NEED_SAVE_RESTORE__REG DENALI_PI_75
+#define LPDDR4__PI_WDQLVL_NEED_SAVE_RESTORE__FLD LPDDR4__DENALI_PI_75__PI_WDQLVL_NEED_SAVE_RESTORE
+
+#define LPDDR4__DENALI_PI_76_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_76_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_76__PI_WDQLVL_DRAM_LVL_START_ADDR_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_76__PI_WDQLVL_DRAM_LVL_START_ADDR_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_76__PI_WDQLVL_DRAM_LVL_START_ADDR_0_WIDTH 32U
+#define LPDDR4__PI_WDQLVL_DRAM_LVL_START_ADDR_0__REG DENALI_PI_76
+#define LPDDR4__PI_WDQLVL_DRAM_LVL_START_ADDR_0__FLD LPDDR4__DENALI_PI_76__PI_WDQLVL_DRAM_LVL_START_ADDR_0
+
+#define LPDDR4__DENALI_PI_77_READ_MASK 0x00010107U
+#define LPDDR4__DENALI_PI_77_WRITE_MASK 0x00010107U
+#define LPDDR4__DENALI_PI_77__PI_WDQLVL_DRAM_LVL_START_ADDR_1_MASK 0x00000007U
+#define LPDDR4__DENALI_PI_77__PI_WDQLVL_DRAM_LVL_START_ADDR_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_77__PI_WDQLVL_DRAM_LVL_START_ADDR_1_WIDTH 3U
+#define LPDDR4__PI_WDQLVL_DRAM_LVL_START_ADDR_1__REG DENALI_PI_77
+#define LPDDR4__PI_WDQLVL_DRAM_LVL_START_ADDR_1__FLD LPDDR4__DENALI_PI_77__PI_WDQLVL_DRAM_LVL_START_ADDR_1
+
+#define LPDDR4__DENALI_PI_77__PI_WDQLVL_DM_LEVEL_EN_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_77__PI_WDQLVL_DM_LEVEL_EN_SHIFT 8U
+#define LPDDR4__DENALI_PI_77__PI_WDQLVL_DM_LEVEL_EN_WIDTH 1U
+#define LPDDR4__DENALI_PI_77__PI_WDQLVL_DM_LEVEL_EN_WOCLR 0U
+#define LPDDR4__DENALI_PI_77__PI_WDQLVL_DM_LEVEL_EN_WOSET 0U
+#define LPDDR4__PI_WDQLVL_DM_LEVEL_EN__REG DENALI_PI_77
+#define LPDDR4__PI_WDQLVL_DM_LEVEL_EN__FLD LPDDR4__DENALI_PI_77__PI_WDQLVL_DM_LEVEL_EN
+
+#define LPDDR4__DENALI_PI_77__PI_NO_MEMORY_DM_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_77__PI_NO_MEMORY_DM_SHIFT 16U
+#define LPDDR4__DENALI_PI_77__PI_NO_MEMORY_DM_WIDTH 1U
+#define LPDDR4__DENALI_PI_77__PI_NO_MEMORY_DM_WOCLR 0U
+#define LPDDR4__DENALI_PI_77__PI_NO_MEMORY_DM_WOSET 0U
+#define LPDDR4__PI_NO_MEMORY_DM__REG DENALI_PI_77
+#define LPDDR4__PI_NO_MEMORY_DM__FLD LPDDR4__DENALI_PI_77__PI_NO_MEMORY_DM
+
+#define LPDDR4__DENALI_PI_78_READ_MASK 0x010003FFU
+#define LPDDR4__DENALI_PI_78_WRITE_MASK 0x010003FFU
+#define LPDDR4__DENALI_PI_78__PI_TDFI_WDQLVL_WW_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_78__PI_TDFI_WDQLVL_WW_SHIFT 0U
+#define LPDDR4__DENALI_PI_78__PI_TDFI_WDQLVL_WW_WIDTH 10U
+#define LPDDR4__PI_TDFI_WDQLVL_WW__REG DENALI_PI_78
+#define LPDDR4__PI_TDFI_WDQLVL_WW__FLD LPDDR4__DENALI_PI_78__PI_TDFI_WDQLVL_WW
+
+#define LPDDR4__DENALI_PI_78__PI_SWLVL_SM2_DM_NIBBLE_START_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_78__PI_SWLVL_SM2_DM_NIBBLE_START_SHIFT 16U
+#define LPDDR4__DENALI_PI_78__PI_SWLVL_SM2_DM_NIBBLE_START_WIDTH 1U
+#define LPDDR4__DENALI_PI_78__PI_SWLVL_SM2_DM_NIBBLE_START_WOCLR 0U
+#define LPDDR4__DENALI_PI_78__PI_SWLVL_SM2_DM_NIBBLE_START_WOSET 0U
+#define LPDDR4__PI_SWLVL_SM2_DM_NIBBLE_START__REG DENALI_PI_78
+#define LPDDR4__PI_SWLVL_SM2_DM_NIBBLE_START__FLD LPDDR4__DENALI_PI_78__PI_SWLVL_SM2_DM_NIBBLE_START
+
+#define LPDDR4__DENALI_PI_78__PI_WDQLVL_NIBBLE_MODE_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_78__PI_WDQLVL_NIBBLE_MODE_SHIFT 24U
+#define LPDDR4__DENALI_PI_78__PI_WDQLVL_NIBBLE_MODE_WIDTH 1U
+#define LPDDR4__DENALI_PI_78__PI_WDQLVL_NIBBLE_MODE_WOCLR 0U
+#define LPDDR4__DENALI_PI_78__PI_WDQLVL_NIBBLE_MODE_WOSET 0U
+#define LPDDR4__PI_WDQLVL_NIBBLE_MODE__REG DENALI_PI_78
+#define LPDDR4__PI_WDQLVL_NIBBLE_MODE__FLD LPDDR4__DENALI_PI_78__PI_WDQLVL_NIBBLE_MODE
+
+#define LPDDR4__DENALI_PI_79_READ_MASK 0x01010101U
+#define LPDDR4__DENALI_PI_79_WRITE_MASK 0x01010101U
+#define LPDDR4__DENALI_PI_79__PI_WDQLVL_OSC_EN_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_79__PI_WDQLVL_OSC_EN_SHIFT 0U
+#define LPDDR4__DENALI_PI_79__PI_WDQLVL_OSC_EN_WIDTH 1U
+#define LPDDR4__DENALI_PI_79__PI_WDQLVL_OSC_EN_WOCLR 0U
+#define LPDDR4__DENALI_PI_79__PI_WDQLVL_OSC_EN_WOSET 0U
+#define LPDDR4__PI_WDQLVL_OSC_EN__REG DENALI_PI_79
+#define LPDDR4__PI_WDQLVL_OSC_EN__FLD LPDDR4__DENALI_PI_79__PI_WDQLVL_OSC_EN
+
+#define LPDDR4__DENALI_PI_79__PI_DQS_OSC_PERIOD_EN_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_79__PI_DQS_OSC_PERIOD_EN_SHIFT 8U
+#define LPDDR4__DENALI_PI_79__PI_DQS_OSC_PERIOD_EN_WIDTH 1U
+#define LPDDR4__DENALI_PI_79__PI_DQS_OSC_PERIOD_EN_WOCLR 0U
+#define LPDDR4__DENALI_PI_79__PI_DQS_OSC_PERIOD_EN_WOSET 0U
+#define LPDDR4__PI_DQS_OSC_PERIOD_EN__REG DENALI_PI_79
+#define LPDDR4__PI_DQS_OSC_PERIOD_EN__FLD LPDDR4__DENALI_PI_79__PI_DQS_OSC_PERIOD_EN
+
+#define LPDDR4__DENALI_PI_79__PI_WDQLVL_PDA_EN_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_79__PI_WDQLVL_PDA_EN_SHIFT 16U
+#define LPDDR4__DENALI_PI_79__PI_WDQLVL_PDA_EN_WIDTH 1U
+#define LPDDR4__DENALI_PI_79__PI_WDQLVL_PDA_EN_WOCLR 0U
+#define LPDDR4__DENALI_PI_79__PI_WDQLVL_PDA_EN_WOSET 0U
+#define LPDDR4__PI_WDQLVL_PDA_EN__REG DENALI_PI_79
+#define LPDDR4__PI_WDQLVL_PDA_EN__FLD LPDDR4__DENALI_PI_79__PI_WDQLVL_PDA_EN
+
+#define LPDDR4__DENALI_PI_79__PI_WDQLVL_PDA_VREF_TRAIN_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_79__PI_WDQLVL_PDA_VREF_TRAIN_SHIFT 24U
+#define LPDDR4__DENALI_PI_79__PI_WDQLVL_PDA_VREF_TRAIN_WIDTH 1U
+#define LPDDR4__DENALI_PI_79__PI_WDQLVL_PDA_VREF_TRAIN_WOCLR 0U
+#define LPDDR4__DENALI_PI_79__PI_WDQLVL_PDA_VREF_TRAIN_WOSET 0U
+#define LPDDR4__PI_WDQLVL_PDA_VREF_TRAIN__REG DENALI_PI_79
+#define LPDDR4__PI_WDQLVL_PDA_VREF_TRAIN__FLD LPDDR4__DENALI_PI_79__PI_WDQLVL_PDA_VREF_TRAIN
+
+#define LPDDR4__DENALI_PI_80_READ_MASK 0x07030F01U
+#define LPDDR4__DENALI_PI_80_WRITE_MASK 0x07030F01U
+#define LPDDR4__DENALI_PI_80__PI_PARALLEL_WDQLVL_EN_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_80__PI_PARALLEL_WDQLVL_EN_SHIFT 0U
+#define LPDDR4__DENALI_PI_80__PI_PARALLEL_WDQLVL_EN_WIDTH 1U
+#define LPDDR4__DENALI_PI_80__PI_PARALLEL_WDQLVL_EN_WOCLR 0U
+#define LPDDR4__DENALI_PI_80__PI_PARALLEL_WDQLVL_EN_WOSET 0U
+#define LPDDR4__PI_PARALLEL_WDQLVL_EN__REG DENALI_PI_80
+#define LPDDR4__PI_PARALLEL_WDQLVL_EN__FLD LPDDR4__DENALI_PI_80__PI_PARALLEL_WDQLVL_EN
+
+#define LPDDR4__DENALI_PI_80__PI_DBILVL_RESP_MASK_MASK 0x00000F00U
+#define LPDDR4__DENALI_PI_80__PI_DBILVL_RESP_MASK_SHIFT 8U
+#define LPDDR4__DENALI_PI_80__PI_DBILVL_RESP_MASK_WIDTH 4U
+#define LPDDR4__PI_DBILVL_RESP_MASK__REG DENALI_PI_80
+#define LPDDR4__PI_DBILVL_RESP_MASK__FLD LPDDR4__DENALI_PI_80__PI_DBILVL_RESP_MASK
+
+#define LPDDR4__DENALI_PI_80__PI_BANK_DIFF_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_80__PI_BANK_DIFF_SHIFT 16U
+#define LPDDR4__DENALI_PI_80__PI_BANK_DIFF_WIDTH 2U
+#define LPDDR4__PI_BANK_DIFF__REG DENALI_PI_80
+#define LPDDR4__PI_BANK_DIFF__FLD LPDDR4__DENALI_PI_80__PI_BANK_DIFF
+
+#define LPDDR4__DENALI_PI_80__PI_ROW_DIFF_MASK 0x07000000U
+#define LPDDR4__DENALI_PI_80__PI_ROW_DIFF_SHIFT 24U
+#define LPDDR4__DENALI_PI_80__PI_ROW_DIFF_WIDTH 3U
+#define LPDDR4__PI_ROW_DIFF__REG DENALI_PI_80
+#define LPDDR4__PI_ROW_DIFF__FLD LPDDR4__DENALI_PI_80__PI_ROW_DIFF
+
+#define LPDDR4__DENALI_PI_81_READ_MASK 0x0F0F0F1FU
+#define LPDDR4__DENALI_PI_81_WRITE_MASK 0x0F0F0F1FU
+#define LPDDR4__DENALI_PI_81__PI_TCCD_MASK 0x0000001FU
+#define LPDDR4__DENALI_PI_81__PI_TCCD_SHIFT 0U
+#define LPDDR4__DENALI_PI_81__PI_TCCD_WIDTH 5U
+#define LPDDR4__PI_TCCD__REG DENALI_PI_81
+#define LPDDR4__PI_TCCD__FLD LPDDR4__DENALI_PI_81__PI_TCCD
+
+#define LPDDR4__DENALI_PI_81__PI_RESERVED7_MASK 0x00000F00U
+#define LPDDR4__DENALI_PI_81__PI_RESERVED7_SHIFT 8U
+#define LPDDR4__DENALI_PI_81__PI_RESERVED7_WIDTH 4U
+#define LPDDR4__PI_RESERVED7__REG DENALI_PI_81
+#define LPDDR4__PI_RESERVED7__FLD LPDDR4__DENALI_PI_81__PI_RESERVED7
+
+#define LPDDR4__DENALI_PI_81__PI_RESERVED8_MASK 0x000F0000U
+#define LPDDR4__DENALI_PI_81__PI_RESERVED8_SHIFT 16U
+#define LPDDR4__DENALI_PI_81__PI_RESERVED8_WIDTH 4U
+#define LPDDR4__PI_RESERVED8__REG DENALI_PI_81
+#define LPDDR4__PI_RESERVED8__FLD LPDDR4__DENALI_PI_81__PI_RESERVED8
+
+#define LPDDR4__DENALI_PI_81__PI_RESERVED9_MASK 0x0F000000U
+#define LPDDR4__DENALI_PI_81__PI_RESERVED9_SHIFT 24U
+#define LPDDR4__DENALI_PI_81__PI_RESERVED9_WIDTH 4U
+#define LPDDR4__PI_RESERVED9__REG DENALI_PI_81
+#define LPDDR4__PI_RESERVED9__FLD LPDDR4__DENALI_PI_81__PI_RESERVED9
+
+#define LPDDR4__DENALI_PI_82_READ_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_82_WRITE_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_82__PI_RESERVED10_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_82__PI_RESERVED10_SHIFT 0U
+#define LPDDR4__DENALI_PI_82__PI_RESERVED10_WIDTH 4U
+#define LPDDR4__PI_RESERVED10__REG DENALI_PI_82
+#define LPDDR4__PI_RESERVED10__FLD LPDDR4__DENALI_PI_82__PI_RESERVED10
+
+#define LPDDR4__DENALI_PI_82__PI_RESERVED11_MASK 0x00000F00U
+#define LPDDR4__DENALI_PI_82__PI_RESERVED11_SHIFT 8U
+#define LPDDR4__DENALI_PI_82__PI_RESERVED11_WIDTH 4U
+#define LPDDR4__PI_RESERVED11__REG DENALI_PI_82
+#define LPDDR4__PI_RESERVED11__FLD LPDDR4__DENALI_PI_82__PI_RESERVED11
+
+#define LPDDR4__DENALI_PI_82__PI_RESERVED12_MASK 0x000F0000U
+#define LPDDR4__DENALI_PI_82__PI_RESERVED12_SHIFT 16U
+#define LPDDR4__DENALI_PI_82__PI_RESERVED12_WIDTH 4U
+#define LPDDR4__PI_RESERVED12__REG DENALI_PI_82
+#define LPDDR4__PI_RESERVED12__FLD LPDDR4__DENALI_PI_82__PI_RESERVED12
+
+#define LPDDR4__DENALI_PI_82__PI_RESERVED13_MASK 0x0F000000U
+#define LPDDR4__DENALI_PI_82__PI_RESERVED13_SHIFT 24U
+#define LPDDR4__DENALI_PI_82__PI_RESERVED13_WIDTH 4U
+#define LPDDR4__PI_RESERVED13__REG DENALI_PI_82
+#define LPDDR4__PI_RESERVED13__FLD LPDDR4__DENALI_PI_82__PI_RESERVED13
+
+#define LPDDR4__DENALI_PI_83_READ_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_83_WRITE_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_83__PI_RESERVED14_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_83__PI_RESERVED14_SHIFT 0U
+#define LPDDR4__DENALI_PI_83__PI_RESERVED14_WIDTH 4U
+#define LPDDR4__PI_RESERVED14__REG DENALI_PI_83
+#define LPDDR4__PI_RESERVED14__FLD LPDDR4__DENALI_PI_83__PI_RESERVED14
+
+#define LPDDR4__DENALI_PI_83__PI_RESERVED15_MASK 0x00000F00U
+#define LPDDR4__DENALI_PI_83__PI_RESERVED15_SHIFT 8U
+#define LPDDR4__DENALI_PI_83__PI_RESERVED15_WIDTH 4U
+#define LPDDR4__PI_RESERVED15__REG DENALI_PI_83
+#define LPDDR4__PI_RESERVED15__FLD LPDDR4__DENALI_PI_83__PI_RESERVED15
+
+#define LPDDR4__DENALI_PI_83__PI_RESERVED16_MASK 0x000F0000U
+#define LPDDR4__DENALI_PI_83__PI_RESERVED16_SHIFT 16U
+#define LPDDR4__DENALI_PI_83__PI_RESERVED16_WIDTH 4U
+#define LPDDR4__PI_RESERVED16__REG DENALI_PI_83
+#define LPDDR4__PI_RESERVED16__FLD LPDDR4__DENALI_PI_83__PI_RESERVED16
+
+#define LPDDR4__DENALI_PI_83__PI_RESERVED17_MASK 0x0F000000U
+#define LPDDR4__DENALI_PI_83__PI_RESERVED17_SHIFT 24U
+#define LPDDR4__DENALI_PI_83__PI_RESERVED17_WIDTH 4U
+#define LPDDR4__PI_RESERVED17__REG DENALI_PI_83
+#define LPDDR4__PI_RESERVED17__FLD LPDDR4__DENALI_PI_83__PI_RESERVED17
+
+#define LPDDR4__DENALI_PI_84_READ_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_84_WRITE_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_84__PI_RESERVED18_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_84__PI_RESERVED18_SHIFT 0U
+#define LPDDR4__DENALI_PI_84__PI_RESERVED18_WIDTH 4U
+#define LPDDR4__PI_RESERVED18__REG DENALI_PI_84
+#define LPDDR4__PI_RESERVED18__FLD LPDDR4__DENALI_PI_84__PI_RESERVED18
+
+#define LPDDR4__DENALI_PI_84__PI_RESERVED19_MASK 0x00000F00U
+#define LPDDR4__DENALI_PI_84__PI_RESERVED19_SHIFT 8U
+#define LPDDR4__DENALI_PI_84__PI_RESERVED19_WIDTH 4U
+#define LPDDR4__PI_RESERVED19__REG DENALI_PI_84
+#define LPDDR4__PI_RESERVED19__FLD LPDDR4__DENALI_PI_84__PI_RESERVED19
+
+#define LPDDR4__DENALI_PI_84__PI_RESERVED20_MASK 0x000F0000U
+#define LPDDR4__DENALI_PI_84__PI_RESERVED20_SHIFT 16U
+#define LPDDR4__DENALI_PI_84__PI_RESERVED20_WIDTH 4U
+#define LPDDR4__PI_RESERVED20__REG DENALI_PI_84
+#define LPDDR4__PI_RESERVED20__FLD LPDDR4__DENALI_PI_84__PI_RESERVED20
+
+#define LPDDR4__DENALI_PI_84__PI_RESERVED21_MASK 0x0F000000U
+#define LPDDR4__DENALI_PI_84__PI_RESERVED21_SHIFT 24U
+#define LPDDR4__DENALI_PI_84__PI_RESERVED21_WIDTH 4U
+#define LPDDR4__PI_RESERVED21__REG DENALI_PI_84
+#define LPDDR4__PI_RESERVED21__FLD LPDDR4__DENALI_PI_84__PI_RESERVED21
+
+#define LPDDR4__DENALI_PI_85_READ_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_85_WRITE_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_85__PI_RESERVED22_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_85__PI_RESERVED22_SHIFT 0U
+#define LPDDR4__DENALI_PI_85__PI_RESERVED22_WIDTH 4U
+#define LPDDR4__PI_RESERVED22__REG DENALI_PI_85
+#define LPDDR4__PI_RESERVED22__FLD LPDDR4__DENALI_PI_85__PI_RESERVED22
+
+#define LPDDR4__DENALI_PI_85__PI_RESERVED23_MASK 0x00000F00U
+#define LPDDR4__DENALI_PI_85__PI_RESERVED23_SHIFT 8U
+#define LPDDR4__DENALI_PI_85__PI_RESERVED23_WIDTH 4U
+#define LPDDR4__PI_RESERVED23__REG DENALI_PI_85
+#define LPDDR4__PI_RESERVED23__FLD LPDDR4__DENALI_PI_85__PI_RESERVED23
+
+#define LPDDR4__DENALI_PI_85__PI_RESERVED24_MASK 0x000F0000U
+#define LPDDR4__DENALI_PI_85__PI_RESERVED24_SHIFT 16U
+#define LPDDR4__DENALI_PI_85__PI_RESERVED24_WIDTH 4U
+#define LPDDR4__PI_RESERVED24__REG DENALI_PI_85
+#define LPDDR4__PI_RESERVED24__FLD LPDDR4__DENALI_PI_85__PI_RESERVED24
+
+#define LPDDR4__DENALI_PI_85__PI_RESERVED25_MASK 0x0F000000U
+#define LPDDR4__DENALI_PI_85__PI_RESERVED25_SHIFT 24U
+#define LPDDR4__DENALI_PI_85__PI_RESERVED25_WIDTH 4U
+#define LPDDR4__PI_RESERVED25__REG DENALI_PI_85
+#define LPDDR4__PI_RESERVED25__FLD LPDDR4__DENALI_PI_85__PI_RESERVED25
+
+#define LPDDR4__DENALI_PI_86_READ_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_86_WRITE_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_86__PI_RESERVED26_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_86__PI_RESERVED26_SHIFT 0U
+#define LPDDR4__DENALI_PI_86__PI_RESERVED26_WIDTH 4U
+#define LPDDR4__PI_RESERVED26__REG DENALI_PI_86
+#define LPDDR4__PI_RESERVED26__FLD LPDDR4__DENALI_PI_86__PI_RESERVED26
+
+#define LPDDR4__DENALI_PI_87_READ_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_87_WRITE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_87__PI_INT_STATUS_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_87__PI_INT_STATUS_SHIFT 0U
+#define LPDDR4__DENALI_PI_87__PI_INT_STATUS_WIDTH 30U
+#define LPDDR4__PI_INT_STATUS__REG DENALI_PI_87
+#define LPDDR4__PI_INT_STATUS__FLD LPDDR4__DENALI_PI_87__PI_INT_STATUS
+
+#define LPDDR4__DENALI_PI_88__PI_INT_ACK_MASK 0x1FFFFFFFU
+#define LPDDR4__DENALI_PI_88__PI_INT_ACK_SHIFT 0U
+#define LPDDR4__DENALI_PI_88__PI_INT_ACK_WIDTH 29U
+#define LPDDR4__PI_INT_ACK__REG DENALI_PI_88
+#define LPDDR4__PI_INT_ACK__FLD LPDDR4__DENALI_PI_88__PI_INT_ACK
+
+#define LPDDR4__DENALI_PI_89_READ_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_89_WRITE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_89__PI_INT_MASK_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_89__PI_INT_MASK_SHIFT 0U
+#define LPDDR4__DENALI_PI_89__PI_INT_MASK_WIDTH 30U
+#define LPDDR4__PI_INT_MASK__REG DENALI_PI_89
+#define LPDDR4__PI_INT_MASK__FLD LPDDR4__DENALI_PI_89__PI_INT_MASK
+
+#define LPDDR4__DENALI_PI_90_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_90_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_90__PI_BIST_EXP_DATA_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_90__PI_BIST_EXP_DATA_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_90__PI_BIST_EXP_DATA_0_WIDTH 32U
+#define LPDDR4__PI_BIST_EXP_DATA_0__REG DENALI_PI_90
+#define LPDDR4__PI_BIST_EXP_DATA_0__FLD LPDDR4__DENALI_PI_90__PI_BIST_EXP_DATA_0
+
+#define LPDDR4__DENALI_PI_91_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_91_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_91__PI_BIST_EXP_DATA_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_91__PI_BIST_EXP_DATA_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_91__PI_BIST_EXP_DATA_1_WIDTH 32U
+#define LPDDR4__PI_BIST_EXP_DATA_1__REG DENALI_PI_91
+#define LPDDR4__PI_BIST_EXP_DATA_1__FLD LPDDR4__DENALI_PI_91__PI_BIST_EXP_DATA_1
+
+#define LPDDR4__DENALI_PI_92_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_92_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_92__PI_BIST_EXP_DATA_2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_92__PI_BIST_EXP_DATA_2_SHIFT 0U
+#define LPDDR4__DENALI_PI_92__PI_BIST_EXP_DATA_2_WIDTH 32U
+#define LPDDR4__PI_BIST_EXP_DATA_2__REG DENALI_PI_92
+#define LPDDR4__PI_BIST_EXP_DATA_2__FLD LPDDR4__DENALI_PI_92__PI_BIST_EXP_DATA_2
+
+#define LPDDR4__DENALI_PI_93_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_93_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_93__PI_BIST_EXP_DATA_3_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_93__PI_BIST_EXP_DATA_3_SHIFT 0U
+#define LPDDR4__DENALI_PI_93__PI_BIST_EXP_DATA_3_WIDTH 32U
+#define LPDDR4__PI_BIST_EXP_DATA_3__REG DENALI_PI_93
+#define LPDDR4__PI_BIST_EXP_DATA_3__FLD LPDDR4__DENALI_PI_93__PI_BIST_EXP_DATA_3
+
+#define LPDDR4__DENALI_PI_94_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_94_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_94__PI_BIST_FAIL_DATA_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_94__PI_BIST_FAIL_DATA_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_94__PI_BIST_FAIL_DATA_0_WIDTH 32U
+#define LPDDR4__PI_BIST_FAIL_DATA_0__REG DENALI_PI_94
+#define LPDDR4__PI_BIST_FAIL_DATA_0__FLD LPDDR4__DENALI_PI_94__PI_BIST_FAIL_DATA_0
+
+#define LPDDR4__DENALI_PI_95_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_95_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_95__PI_BIST_FAIL_DATA_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_95__PI_BIST_FAIL_DATA_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_95__PI_BIST_FAIL_DATA_1_WIDTH 32U
+#define LPDDR4__PI_BIST_FAIL_DATA_1__REG DENALI_PI_95
+#define LPDDR4__PI_BIST_FAIL_DATA_1__FLD LPDDR4__DENALI_PI_95__PI_BIST_FAIL_DATA_1
+
+#define LPDDR4__DENALI_PI_96_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_96_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_96__PI_BIST_FAIL_DATA_2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_96__PI_BIST_FAIL_DATA_2_SHIFT 0U
+#define LPDDR4__DENALI_PI_96__PI_BIST_FAIL_DATA_2_WIDTH 32U
+#define LPDDR4__PI_BIST_FAIL_DATA_2__REG DENALI_PI_96
+#define LPDDR4__PI_BIST_FAIL_DATA_2__FLD LPDDR4__DENALI_PI_96__PI_BIST_FAIL_DATA_2
+
+#define LPDDR4__DENALI_PI_97_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_97_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_97__PI_BIST_FAIL_DATA_3_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_97__PI_BIST_FAIL_DATA_3_SHIFT 0U
+#define LPDDR4__DENALI_PI_97__PI_BIST_FAIL_DATA_3_WIDTH 32U
+#define LPDDR4__PI_BIST_FAIL_DATA_3__REG DENALI_PI_97
+#define LPDDR4__PI_BIST_FAIL_DATA_3__FLD LPDDR4__DENALI_PI_97__PI_BIST_FAIL_DATA_3
+
+#define LPDDR4__DENALI_PI_98_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_98_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_98__PI_BIST_FAIL_ADDR_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_98__PI_BIST_FAIL_ADDR_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_98__PI_BIST_FAIL_ADDR_0_WIDTH 32U
+#define LPDDR4__PI_BIST_FAIL_ADDR_0__REG DENALI_PI_98
+#define LPDDR4__PI_BIST_FAIL_ADDR_0__FLD LPDDR4__DENALI_PI_98__PI_BIST_FAIL_ADDR_0
+
+#define LPDDR4__DENALI_PI_99_READ_MASK 0x011F3F07U
+#define LPDDR4__DENALI_PI_99_WRITE_MASK 0x011F3F07U
+#define LPDDR4__DENALI_PI_99__PI_BIST_FAIL_ADDR_1_MASK 0x00000007U
+#define LPDDR4__DENALI_PI_99__PI_BIST_FAIL_ADDR_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_99__PI_BIST_FAIL_ADDR_1_WIDTH 3U
+#define LPDDR4__PI_BIST_FAIL_ADDR_1__REG DENALI_PI_99
+#define LPDDR4__PI_BIST_FAIL_ADDR_1__FLD LPDDR4__DENALI_PI_99__PI_BIST_FAIL_ADDR_1
+
+#define LPDDR4__DENALI_PI_99__PI_BSTLEN_MASK 0x00003F00U
+#define LPDDR4__DENALI_PI_99__PI_BSTLEN_SHIFT 8U
+#define LPDDR4__DENALI_PI_99__PI_BSTLEN_WIDTH 6U
+#define LPDDR4__PI_BSTLEN__REG DENALI_PI_99
+#define LPDDR4__PI_BSTLEN__FLD LPDDR4__DENALI_PI_99__PI_BSTLEN
+
+#define LPDDR4__DENALI_PI_99__PI_LONG_COUNT_MASK_MASK 0x001F0000U
+#define LPDDR4__DENALI_PI_99__PI_LONG_COUNT_MASK_SHIFT 16U
+#define LPDDR4__DENALI_PI_99__PI_LONG_COUNT_MASK_WIDTH 5U
+#define LPDDR4__PI_LONG_COUNT_MASK__REG DENALI_PI_99
+#define LPDDR4__PI_LONG_COUNT_MASK__FLD LPDDR4__DENALI_PI_99__PI_LONG_COUNT_MASK
+
+#define LPDDR4__DENALI_PI_99__PI_CMD_SWAP_EN_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_99__PI_CMD_SWAP_EN_SHIFT 24U
+#define LPDDR4__DENALI_PI_99__PI_CMD_SWAP_EN_WIDTH 1U
+#define LPDDR4__DENALI_PI_99__PI_CMD_SWAP_EN_WOCLR 0U
+#define LPDDR4__DENALI_PI_99__PI_CMD_SWAP_EN_WOSET 0U
+#define LPDDR4__PI_CMD_SWAP_EN__REG DENALI_PI_99
+#define LPDDR4__PI_CMD_SWAP_EN__FLD LPDDR4__DENALI_PI_99__PI_CMD_SWAP_EN
+
+#define LPDDR4__DENALI_PI_100_READ_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_PI_100_WRITE_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_PI_100__PI_PARITY_IN_MUX_MASK 0x0000001FU
+#define LPDDR4__DENALI_PI_100__PI_PARITY_IN_MUX_SHIFT 0U
+#define LPDDR4__DENALI_PI_100__PI_PARITY_IN_MUX_WIDTH 5U
+#define LPDDR4__PI_PARITY_IN_MUX__REG DENALI_PI_100
+#define LPDDR4__PI_PARITY_IN_MUX__FLD LPDDR4__DENALI_PI_100__PI_PARITY_IN_MUX
+
+#define LPDDR4__DENALI_PI_100__PI_ACT_N_MUX_MASK 0x00001F00U
+#define LPDDR4__DENALI_PI_100__PI_ACT_N_MUX_SHIFT 8U
+#define LPDDR4__DENALI_PI_100__PI_ACT_N_MUX_WIDTH 5U
+#define LPDDR4__PI_ACT_N_MUX__REG DENALI_PI_100
+#define LPDDR4__PI_ACT_N_MUX__FLD LPDDR4__DENALI_PI_100__PI_ACT_N_MUX
+
+#define LPDDR4__DENALI_PI_100__PI_BG_MUX_0_MASK 0x001F0000U
+#define LPDDR4__DENALI_PI_100__PI_BG_MUX_0_SHIFT 16U
+#define LPDDR4__DENALI_PI_100__PI_BG_MUX_0_WIDTH 5U
+#define LPDDR4__PI_BG_MUX_0__REG DENALI_PI_100
+#define LPDDR4__PI_BG_MUX_0__FLD LPDDR4__DENALI_PI_100__PI_BG_MUX_0
+
+#define LPDDR4__DENALI_PI_100__PI_BG_MUX_1_MASK 0x1F000000U
+#define LPDDR4__DENALI_PI_100__PI_BG_MUX_1_SHIFT 24U
+#define LPDDR4__DENALI_PI_100__PI_BG_MUX_1_WIDTH 5U
+#define LPDDR4__PI_BG_MUX_1__REG DENALI_PI_100
+#define LPDDR4__PI_BG_MUX_1__FLD LPDDR4__DENALI_PI_100__PI_BG_MUX_1
+
+#define LPDDR4__DENALI_PI_101_READ_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_PI_101_WRITE_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_PI_101__PI_RAS_N_MUX_MASK 0x0000001FU
+#define LPDDR4__DENALI_PI_101__PI_RAS_N_MUX_SHIFT 0U
+#define LPDDR4__DENALI_PI_101__PI_RAS_N_MUX_WIDTH 5U
+#define LPDDR4__PI_RAS_N_MUX__REG DENALI_PI_101
+#define LPDDR4__PI_RAS_N_MUX__FLD LPDDR4__DENALI_PI_101__PI_RAS_N_MUX
+
+#define LPDDR4__DENALI_PI_101__PI_CAS_N_MUX_MASK 0x00001F00U
+#define LPDDR4__DENALI_PI_101__PI_CAS_N_MUX_SHIFT 8U
+#define LPDDR4__DENALI_PI_101__PI_CAS_N_MUX_WIDTH 5U
+#define LPDDR4__PI_CAS_N_MUX__REG DENALI_PI_101
+#define LPDDR4__PI_CAS_N_MUX__FLD LPDDR4__DENALI_PI_101__PI_CAS_N_MUX
+
+#define LPDDR4__DENALI_PI_101__PI_WE_N_MUX_MASK 0x001F0000U
+#define LPDDR4__DENALI_PI_101__PI_WE_N_MUX_SHIFT 16U
+#define LPDDR4__DENALI_PI_101__PI_WE_N_MUX_WIDTH 5U
+#define LPDDR4__PI_WE_N_MUX__REG DENALI_PI_101
+#define LPDDR4__PI_WE_N_MUX__FLD LPDDR4__DENALI_PI_101__PI_WE_N_MUX
+
+#define LPDDR4__DENALI_PI_101__PI_BANK_MUX_0_MASK 0x1F000000U
+#define LPDDR4__DENALI_PI_101__PI_BANK_MUX_0_SHIFT 24U
+#define LPDDR4__DENALI_PI_101__PI_BANK_MUX_0_WIDTH 5U
+#define LPDDR4__PI_BANK_MUX_0__REG DENALI_PI_101
+#define LPDDR4__PI_BANK_MUX_0__FLD LPDDR4__DENALI_PI_101__PI_BANK_MUX_0
+
+#define LPDDR4__DENALI_PI_102_READ_MASK 0x0303011FU
+#define LPDDR4__DENALI_PI_102_WRITE_MASK 0x0303011FU
+#define LPDDR4__DENALI_PI_102__PI_BANK_MUX_1_MASK 0x0000001FU
+#define LPDDR4__DENALI_PI_102__PI_BANK_MUX_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_102__PI_BANK_MUX_1_WIDTH 5U
+#define LPDDR4__PI_BANK_MUX_1__REG DENALI_PI_102
+#define LPDDR4__PI_BANK_MUX_1__FLD LPDDR4__DENALI_PI_102__PI_BANK_MUX_1
+
+#define LPDDR4__DENALI_PI_102__PI_DATA_BYTE_SWAP_EN_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_102__PI_DATA_BYTE_SWAP_EN_SHIFT 8U
+#define LPDDR4__DENALI_PI_102__PI_DATA_BYTE_SWAP_EN_WIDTH 1U
+#define LPDDR4__DENALI_PI_102__PI_DATA_BYTE_SWAP_EN_WOCLR 0U
+#define LPDDR4__DENALI_PI_102__PI_DATA_BYTE_SWAP_EN_WOSET 0U
+#define LPDDR4__PI_DATA_BYTE_SWAP_EN__REG DENALI_PI_102
+#define LPDDR4__PI_DATA_BYTE_SWAP_EN__FLD LPDDR4__DENALI_PI_102__PI_DATA_BYTE_SWAP_EN
+
+#define LPDDR4__DENALI_PI_102__PI_DATA_BYTE_SWAP_SLICE0_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_102__PI_DATA_BYTE_SWAP_SLICE0_SHIFT 16U
+#define LPDDR4__DENALI_PI_102__PI_DATA_BYTE_SWAP_SLICE0_WIDTH 2U
+#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE0__REG DENALI_PI_102
+#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE0__FLD LPDDR4__DENALI_PI_102__PI_DATA_BYTE_SWAP_SLICE0
+
+#define LPDDR4__DENALI_PI_102__PI_DATA_BYTE_SWAP_SLICE1_MASK 0x03000000U
+#define LPDDR4__DENALI_PI_102__PI_DATA_BYTE_SWAP_SLICE1_SHIFT 24U
+#define LPDDR4__DENALI_PI_102__PI_DATA_BYTE_SWAP_SLICE1_WIDTH 2U
+#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE1__REG DENALI_PI_102
+#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE1__FLD LPDDR4__DENALI_PI_102__PI_DATA_BYTE_SWAP_SLICE1
+
+#define LPDDR4__DENALI_PI_103_READ_MASK 0x00010303U
+#define LPDDR4__DENALI_PI_103_WRITE_MASK 0x00010303U
+#define LPDDR4__DENALI_PI_103__PI_DATA_BYTE_SWAP_SLICE2_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_103__PI_DATA_BYTE_SWAP_SLICE2_SHIFT 0U
+#define LPDDR4__DENALI_PI_103__PI_DATA_BYTE_SWAP_SLICE2_WIDTH 2U
+#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE2__REG DENALI_PI_103
+#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE2__FLD LPDDR4__DENALI_PI_103__PI_DATA_BYTE_SWAP_SLICE2
+
+#define LPDDR4__DENALI_PI_103__PI_DATA_BYTE_SWAP_SLICE3_MASK 0x00000300U
+#define LPDDR4__DENALI_PI_103__PI_DATA_BYTE_SWAP_SLICE3_SHIFT 8U
+#define LPDDR4__DENALI_PI_103__PI_DATA_BYTE_SWAP_SLICE3_WIDTH 2U
+#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE3__REG DENALI_PI_103
+#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE3__FLD LPDDR4__DENALI_PI_103__PI_DATA_BYTE_SWAP_SLICE3
+
+#define LPDDR4__DENALI_PI_103__PI_CTRLUPD_REQ_PER_AREF_EN_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_103__PI_CTRLUPD_REQ_PER_AREF_EN_SHIFT 16U
+#define LPDDR4__DENALI_PI_103__PI_CTRLUPD_REQ_PER_AREF_EN_WIDTH 1U
+#define LPDDR4__DENALI_PI_103__PI_CTRLUPD_REQ_PER_AREF_EN_WOCLR 0U
+#define LPDDR4__DENALI_PI_103__PI_CTRLUPD_REQ_PER_AREF_EN_WOSET 0U
+#define LPDDR4__PI_CTRLUPD_REQ_PER_AREF_EN__REG DENALI_PI_103
+#define LPDDR4__PI_CTRLUPD_REQ_PER_AREF_EN__FLD LPDDR4__DENALI_PI_103__PI_CTRLUPD_REQ_PER_AREF_EN
+
+#define LPDDR4__DENALI_PI_104_READ_MASK 0x0703FFFFU
+#define LPDDR4__DENALI_PI_104_WRITE_MASK 0x0703FFFFU
+#define LPDDR4__DENALI_PI_104__PI_TDFI_CTRLUPD_MIN_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PI_104__PI_TDFI_CTRLUPD_MIN_SHIFT 0U
+#define LPDDR4__DENALI_PI_104__PI_TDFI_CTRLUPD_MIN_WIDTH 16U
+#define LPDDR4__PI_TDFI_CTRLUPD_MIN__REG DENALI_PI_104
+#define LPDDR4__PI_TDFI_CTRLUPD_MIN__FLD LPDDR4__DENALI_PI_104__PI_TDFI_CTRLUPD_MIN
+
+#define LPDDR4__DENALI_PI_104__PI_UPDATE_ERROR_STATUS_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_104__PI_UPDATE_ERROR_STATUS_SHIFT 16U
+#define LPDDR4__DENALI_PI_104__PI_UPDATE_ERROR_STATUS_WIDTH 2U
+#define LPDDR4__PI_UPDATE_ERROR_STATUS__REG DENALI_PI_104
+#define LPDDR4__PI_UPDATE_ERROR_STATUS__FLD LPDDR4__DENALI_PI_104__PI_UPDATE_ERROR_STATUS
+
+#define LPDDR4__DENALI_PI_104__PI_TDFI_PARIN_LAT_MASK 0x07000000U
+#define LPDDR4__DENALI_PI_104__PI_TDFI_PARIN_LAT_SHIFT 24U
+#define LPDDR4__DENALI_PI_104__PI_TDFI_PARIN_LAT_WIDTH 3U
+#define LPDDR4__PI_TDFI_PARIN_LAT__REG DENALI_PI_104
+#define LPDDR4__PI_TDFI_PARIN_LAT__FLD LPDDR4__DENALI_PI_104__PI_TDFI_PARIN_LAT
+
+#define LPDDR4__DENALI_PI_105_READ_MASK 0xFF010301U
+#define LPDDR4__DENALI_PI_105_WRITE_MASK 0xFF010301U
+#define LPDDR4__DENALI_PI_105__PI_BIST_GO_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_105__PI_BIST_GO_SHIFT 0U
+#define LPDDR4__DENALI_PI_105__PI_BIST_GO_WIDTH 1U
+#define LPDDR4__DENALI_PI_105__PI_BIST_GO_WOCLR 0U
+#define LPDDR4__DENALI_PI_105__PI_BIST_GO_WOSET 0U
+#define LPDDR4__PI_BIST_GO__REG DENALI_PI_105
+#define LPDDR4__PI_BIST_GO__FLD LPDDR4__DENALI_PI_105__PI_BIST_GO
+
+#define LPDDR4__DENALI_PI_105__PI_BIST_RESULT_MASK 0x00000300U
+#define LPDDR4__DENALI_PI_105__PI_BIST_RESULT_SHIFT 8U
+#define LPDDR4__DENALI_PI_105__PI_BIST_RESULT_WIDTH 2U
+#define LPDDR4__PI_BIST_RESULT__REG DENALI_PI_105
+#define LPDDR4__PI_BIST_RESULT__FLD LPDDR4__DENALI_PI_105__PI_BIST_RESULT
+
+#define LPDDR4__DENALI_PI_105__PI_BIST_LFSR_PATTERN_DONE_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_105__PI_BIST_LFSR_PATTERN_DONE_SHIFT 16U
+#define LPDDR4__DENALI_PI_105__PI_BIST_LFSR_PATTERN_DONE_WIDTH 1U
+#define LPDDR4__DENALI_PI_105__PI_BIST_LFSR_PATTERN_DONE_WOCLR 0U
+#define LPDDR4__DENALI_PI_105__PI_BIST_LFSR_PATTERN_DONE_WOSET 0U
+#define LPDDR4__PI_BIST_LFSR_PATTERN_DONE__REG DENALI_PI_105
+#define LPDDR4__PI_BIST_LFSR_PATTERN_DONE__FLD LPDDR4__DENALI_PI_105__PI_BIST_LFSR_PATTERN_DONE
+
+#define LPDDR4__DENALI_PI_105__PI_ADDR_SPACE_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_105__PI_ADDR_SPACE_SHIFT 24U
+#define LPDDR4__DENALI_PI_105__PI_ADDR_SPACE_WIDTH 8U
+#define LPDDR4__PI_ADDR_SPACE__REG DENALI_PI_105
+#define LPDDR4__PI_ADDR_SPACE__FLD LPDDR4__DENALI_PI_105__PI_ADDR_SPACE
+
+#define LPDDR4__DENALI_PI_106_READ_MASK 0x00000101U
+#define LPDDR4__DENALI_PI_106_WRITE_MASK 0x00000101U
+#define LPDDR4__DENALI_PI_106__PI_BIST_DATA_CHECK_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_106__PI_BIST_DATA_CHECK_SHIFT 0U
+#define LPDDR4__DENALI_PI_106__PI_BIST_DATA_CHECK_WIDTH 1U
+#define LPDDR4__DENALI_PI_106__PI_BIST_DATA_CHECK_WOCLR 0U
+#define LPDDR4__DENALI_PI_106__PI_BIST_DATA_CHECK_WOSET 0U
+#define LPDDR4__PI_BIST_DATA_CHECK__REG DENALI_PI_106
+#define LPDDR4__PI_BIST_DATA_CHECK__FLD LPDDR4__DENALI_PI_106__PI_BIST_DATA_CHECK
+
+#define LPDDR4__DENALI_PI_106__PI_BIST_ADDR_CHECK_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_106__PI_BIST_ADDR_CHECK_SHIFT 8U
+#define LPDDR4__DENALI_PI_106__PI_BIST_ADDR_CHECK_WIDTH 1U
+#define LPDDR4__DENALI_PI_106__PI_BIST_ADDR_CHECK_WOCLR 0U
+#define LPDDR4__DENALI_PI_106__PI_BIST_ADDR_CHECK_WOSET 0U
+#define LPDDR4__PI_BIST_ADDR_CHECK__REG DENALI_PI_106
+#define LPDDR4__PI_BIST_ADDR_CHECK__FLD LPDDR4__DENALI_PI_106__PI_BIST_ADDR_CHECK
+
+#define LPDDR4__DENALI_PI_107_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_107_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_107__PI_BIST_START_ADDRESS_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_107__PI_BIST_START_ADDRESS_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_107__PI_BIST_START_ADDRESS_0_WIDTH 32U
+#define LPDDR4__PI_BIST_START_ADDRESS_0__REG DENALI_PI_107
+#define LPDDR4__PI_BIST_START_ADDRESS_0__FLD LPDDR4__DENALI_PI_107__PI_BIST_START_ADDRESS_0
+
+#define LPDDR4__DENALI_PI_108_READ_MASK 0x0000FF07U
+#define LPDDR4__DENALI_PI_108_WRITE_MASK 0x0000FF07U
+#define LPDDR4__DENALI_PI_108__PI_BIST_START_ADDRESS_1_MASK 0x00000007U
+#define LPDDR4__DENALI_PI_108__PI_BIST_START_ADDRESS_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_108__PI_BIST_START_ADDRESS_1_WIDTH 3U
+#define LPDDR4__PI_BIST_START_ADDRESS_1__REG DENALI_PI_108
+#define LPDDR4__PI_BIST_START_ADDRESS_1__FLD LPDDR4__DENALI_PI_108__PI_BIST_START_ADDRESS_1
+
+#define LPDDR4__DENALI_PI_108__PI_MBIST_INIT_PATTERN_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_108__PI_MBIST_INIT_PATTERN_SHIFT 8U
+#define LPDDR4__DENALI_PI_108__PI_MBIST_INIT_PATTERN_WIDTH 8U
+#define LPDDR4__PI_MBIST_INIT_PATTERN__REG DENALI_PI_108
+#define LPDDR4__PI_MBIST_INIT_PATTERN__FLD LPDDR4__DENALI_PI_108__PI_MBIST_INIT_PATTERN
+
+#define LPDDR4__DENALI_PI_109_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_109_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_109__PI_BIST_DATA_MASK_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_109__PI_BIST_DATA_MASK_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_109__PI_BIST_DATA_MASK_0_WIDTH 32U
+#define LPDDR4__PI_BIST_DATA_MASK_0__REG DENALI_PI_109
+#define LPDDR4__PI_BIST_DATA_MASK_0__FLD LPDDR4__DENALI_PI_109__PI_BIST_DATA_MASK_0
+
+#define LPDDR4__DENALI_PI_110_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_110_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_110__PI_BIST_DATA_MASK_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_110__PI_BIST_DATA_MASK_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_110__PI_BIST_DATA_MASK_1_WIDTH 32U
+#define LPDDR4__PI_BIST_DATA_MASK_1__REG DENALI_PI_110
+#define LPDDR4__PI_BIST_DATA_MASK_1__FLD LPDDR4__DENALI_PI_110__PI_BIST_DATA_MASK_1
+
+#define LPDDR4__DENALI_PI_111_READ_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_PI_111_WRITE_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_PI_111__PI_BIST_ERR_COUNT_MASK 0x00000FFFU
+#define LPDDR4__DENALI_PI_111__PI_BIST_ERR_COUNT_SHIFT 0U
+#define LPDDR4__DENALI_PI_111__PI_BIST_ERR_COUNT_WIDTH 12U
+#define LPDDR4__PI_BIST_ERR_COUNT__REG DENALI_PI_111
+#define LPDDR4__PI_BIST_ERR_COUNT__FLD LPDDR4__DENALI_PI_111__PI_BIST_ERR_COUNT
+
+#define LPDDR4__DENALI_PI_111__PI_BIST_ERR_STOP_MASK 0x0FFF0000U
+#define LPDDR4__DENALI_PI_111__PI_BIST_ERR_STOP_SHIFT 16U
+#define LPDDR4__DENALI_PI_111__PI_BIST_ERR_STOP_WIDTH 12U
+#define LPDDR4__PI_BIST_ERR_STOP__REG DENALI_PI_111
+#define LPDDR4__PI_BIST_ERR_STOP__FLD LPDDR4__DENALI_PI_111__PI_BIST_ERR_STOP
+
+#define LPDDR4__DENALI_PI_112_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_112_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_112__PI_BIST_ADDR_MASK_0_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_112__PI_BIST_ADDR_MASK_0_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_112__PI_BIST_ADDR_MASK_0_0_WIDTH 32U
+#define LPDDR4__PI_BIST_ADDR_MASK_0_0__REG DENALI_PI_112
+#define LPDDR4__PI_BIST_ADDR_MASK_0_0__FLD LPDDR4__DENALI_PI_112__PI_BIST_ADDR_MASK_0_0
+
+#define LPDDR4__DENALI_PI_113_READ_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_113_WRITE_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_113__PI_BIST_ADDR_MASK_0_1_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_113__PI_BIST_ADDR_MASK_0_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_113__PI_BIST_ADDR_MASK_0_1_WIDTH 4U
+#define LPDDR4__PI_BIST_ADDR_MASK_0_1__REG DENALI_PI_113
+#define LPDDR4__PI_BIST_ADDR_MASK_0_1__FLD LPDDR4__DENALI_PI_113__PI_BIST_ADDR_MASK_0_1
+
+#define LPDDR4__DENALI_PI_114_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_114_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_114__PI_BIST_ADDR_MASK_1_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_114__PI_BIST_ADDR_MASK_1_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_114__PI_BIST_ADDR_MASK_1_0_WIDTH 32U
+#define LPDDR4__PI_BIST_ADDR_MASK_1_0__REG DENALI_PI_114
+#define LPDDR4__PI_BIST_ADDR_MASK_1_0__FLD LPDDR4__DENALI_PI_114__PI_BIST_ADDR_MASK_1_0
+
+#define LPDDR4__DENALI_PI_115_READ_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_115_WRITE_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_115__PI_BIST_ADDR_MASK_1_1_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_115__PI_BIST_ADDR_MASK_1_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_115__PI_BIST_ADDR_MASK_1_1_WIDTH 4U
+#define LPDDR4__PI_BIST_ADDR_MASK_1_1__REG DENALI_PI_115
+#define LPDDR4__PI_BIST_ADDR_MASK_1_1__FLD LPDDR4__DENALI_PI_115__PI_BIST_ADDR_MASK_1_1
+
+#define LPDDR4__DENALI_PI_116_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_116_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_116__PI_BIST_ADDR_MASK_2_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_116__PI_BIST_ADDR_MASK_2_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_116__PI_BIST_ADDR_MASK_2_0_WIDTH 32U
+#define LPDDR4__PI_BIST_ADDR_MASK_2_0__REG DENALI_PI_116
+#define LPDDR4__PI_BIST_ADDR_MASK_2_0__FLD LPDDR4__DENALI_PI_116__PI_BIST_ADDR_MASK_2_0
+
+#define LPDDR4__DENALI_PI_117_READ_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_117_WRITE_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_117__PI_BIST_ADDR_MASK_2_1_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_117__PI_BIST_ADDR_MASK_2_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_117__PI_BIST_ADDR_MASK_2_1_WIDTH 4U
+#define LPDDR4__PI_BIST_ADDR_MASK_2_1__REG DENALI_PI_117
+#define LPDDR4__PI_BIST_ADDR_MASK_2_1__FLD LPDDR4__DENALI_PI_117__PI_BIST_ADDR_MASK_2_1
+
+#define LPDDR4__DENALI_PI_118_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_118_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_118__PI_BIST_ADDR_MASK_3_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_118__PI_BIST_ADDR_MASK_3_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_118__PI_BIST_ADDR_MASK_3_0_WIDTH 32U
+#define LPDDR4__PI_BIST_ADDR_MASK_3_0__REG DENALI_PI_118
+#define LPDDR4__PI_BIST_ADDR_MASK_3_0__FLD LPDDR4__DENALI_PI_118__PI_BIST_ADDR_MASK_3_0
+
+#define LPDDR4__DENALI_PI_119_READ_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_119_WRITE_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_119__PI_BIST_ADDR_MASK_3_1_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_119__PI_BIST_ADDR_MASK_3_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_119__PI_BIST_ADDR_MASK_3_1_WIDTH 4U
+#define LPDDR4__PI_BIST_ADDR_MASK_3_1__REG DENALI_PI_119
+#define LPDDR4__PI_BIST_ADDR_MASK_3_1__FLD LPDDR4__DENALI_PI_119__PI_BIST_ADDR_MASK_3_1
+
+#define LPDDR4__DENALI_PI_120_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_120_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MASK_4_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MASK_4_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MASK_4_0_WIDTH 32U
+#define LPDDR4__PI_BIST_ADDR_MASK_4_0__REG DENALI_PI_120
+#define LPDDR4__PI_BIST_ADDR_MASK_4_0__FLD LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MASK_4_0
+
+#define LPDDR4__DENALI_PI_121_READ_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_121_WRITE_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_121__PI_BIST_ADDR_MASK_4_1_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_121__PI_BIST_ADDR_MASK_4_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_121__PI_BIST_ADDR_MASK_4_1_WIDTH 4U
+#define LPDDR4__PI_BIST_ADDR_MASK_4_1__REG DENALI_PI_121
+#define LPDDR4__PI_BIST_ADDR_MASK_4_1__FLD LPDDR4__DENALI_PI_121__PI_BIST_ADDR_MASK_4_1
+
+#define LPDDR4__DENALI_PI_122_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_122_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_122__PI_BIST_ADDR_MASK_5_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_122__PI_BIST_ADDR_MASK_5_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_122__PI_BIST_ADDR_MASK_5_0_WIDTH 32U
+#define LPDDR4__PI_BIST_ADDR_MASK_5_0__REG DENALI_PI_122
+#define LPDDR4__PI_BIST_ADDR_MASK_5_0__FLD LPDDR4__DENALI_PI_122__PI_BIST_ADDR_MASK_5_0
+
+#define LPDDR4__DENALI_PI_123_READ_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_123_WRITE_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_123__PI_BIST_ADDR_MASK_5_1_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_123__PI_BIST_ADDR_MASK_5_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_123__PI_BIST_ADDR_MASK_5_1_WIDTH 4U
+#define LPDDR4__PI_BIST_ADDR_MASK_5_1__REG DENALI_PI_123
+#define LPDDR4__PI_BIST_ADDR_MASK_5_1__FLD LPDDR4__DENALI_PI_123__PI_BIST_ADDR_MASK_5_1
+
+#define LPDDR4__DENALI_PI_124_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_124_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_124__PI_BIST_ADDR_MASK_6_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_124__PI_BIST_ADDR_MASK_6_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_124__PI_BIST_ADDR_MASK_6_0_WIDTH 32U
+#define LPDDR4__PI_BIST_ADDR_MASK_6_0__REG DENALI_PI_124
+#define LPDDR4__PI_BIST_ADDR_MASK_6_0__FLD LPDDR4__DENALI_PI_124__PI_BIST_ADDR_MASK_6_0
+
+#define LPDDR4__DENALI_PI_125_READ_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_125_WRITE_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_125__PI_BIST_ADDR_MASK_6_1_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_125__PI_BIST_ADDR_MASK_6_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_125__PI_BIST_ADDR_MASK_6_1_WIDTH 4U
+#define LPDDR4__PI_BIST_ADDR_MASK_6_1__REG DENALI_PI_125
+#define LPDDR4__PI_BIST_ADDR_MASK_6_1__FLD LPDDR4__DENALI_PI_125__PI_BIST_ADDR_MASK_6_1
+
+#define LPDDR4__DENALI_PI_126_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_126_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_126__PI_BIST_ADDR_MASK_7_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_126__PI_BIST_ADDR_MASK_7_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_126__PI_BIST_ADDR_MASK_7_0_WIDTH 32U
+#define LPDDR4__PI_BIST_ADDR_MASK_7_0__REG DENALI_PI_126
+#define LPDDR4__PI_BIST_ADDR_MASK_7_0__FLD LPDDR4__DENALI_PI_126__PI_BIST_ADDR_MASK_7_0
+
+#define LPDDR4__DENALI_PI_127_READ_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_127_WRITE_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_127__PI_BIST_ADDR_MASK_7_1_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_127__PI_BIST_ADDR_MASK_7_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_127__PI_BIST_ADDR_MASK_7_1_WIDTH 4U
+#define LPDDR4__PI_BIST_ADDR_MASK_7_1__REG DENALI_PI_127
+#define LPDDR4__PI_BIST_ADDR_MASK_7_1__FLD LPDDR4__DENALI_PI_127__PI_BIST_ADDR_MASK_7_1
+
+#define LPDDR4__DENALI_PI_128_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_128_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_128__PI_BIST_ADDR_MASK_8_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_128__PI_BIST_ADDR_MASK_8_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_128__PI_BIST_ADDR_MASK_8_0_WIDTH 32U
+#define LPDDR4__PI_BIST_ADDR_MASK_8_0__REG DENALI_PI_128
+#define LPDDR4__PI_BIST_ADDR_MASK_8_0__FLD LPDDR4__DENALI_PI_128__PI_BIST_ADDR_MASK_8_0
+
+#define LPDDR4__DENALI_PI_129_READ_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_129_WRITE_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_129__PI_BIST_ADDR_MASK_8_1_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_129__PI_BIST_ADDR_MASK_8_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_129__PI_BIST_ADDR_MASK_8_1_WIDTH 4U
+#define LPDDR4__PI_BIST_ADDR_MASK_8_1__REG DENALI_PI_129
+#define LPDDR4__PI_BIST_ADDR_MASK_8_1__FLD LPDDR4__DENALI_PI_129__PI_BIST_ADDR_MASK_8_1
+
+#define LPDDR4__DENALI_PI_130_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_130_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_130__PI_BIST_ADDR_MASK_9_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_130__PI_BIST_ADDR_MASK_9_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_130__PI_BIST_ADDR_MASK_9_0_WIDTH 32U
+#define LPDDR4__PI_BIST_ADDR_MASK_9_0__REG DENALI_PI_130
+#define LPDDR4__PI_BIST_ADDR_MASK_9_0__FLD LPDDR4__DENALI_PI_130__PI_BIST_ADDR_MASK_9_0
+
+#define LPDDR4__DENALI_PI_131_READ_MASK 0x0303070FU
+#define LPDDR4__DENALI_PI_131_WRITE_MASK 0x0303070FU
+#define LPDDR4__DENALI_PI_131__PI_BIST_ADDR_MASK_9_1_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_131__PI_BIST_ADDR_MASK_9_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_131__PI_BIST_ADDR_MASK_9_1_WIDTH 4U
+#define LPDDR4__PI_BIST_ADDR_MASK_9_1__REG DENALI_PI_131
+#define LPDDR4__PI_BIST_ADDR_MASK_9_1__FLD LPDDR4__DENALI_PI_131__PI_BIST_ADDR_MASK_9_1
+
+#define LPDDR4__DENALI_PI_131__PI_BIST_MODE_MASK 0x00000700U
+#define LPDDR4__DENALI_PI_131__PI_BIST_MODE_SHIFT 8U
+#define LPDDR4__DENALI_PI_131__PI_BIST_MODE_WIDTH 3U
+#define LPDDR4__PI_BIST_MODE__REG DENALI_PI_131
+#define LPDDR4__PI_BIST_MODE__FLD LPDDR4__DENALI_PI_131__PI_BIST_MODE
+
+#define LPDDR4__DENALI_PI_131__PI_BIST_ADDR_MODE_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_131__PI_BIST_ADDR_MODE_SHIFT 16U
+#define LPDDR4__DENALI_PI_131__PI_BIST_ADDR_MODE_WIDTH 2U
+#define LPDDR4__PI_BIST_ADDR_MODE__REG DENALI_PI_131
+#define LPDDR4__PI_BIST_ADDR_MODE__FLD LPDDR4__DENALI_PI_131__PI_BIST_ADDR_MODE
+
+#define LPDDR4__DENALI_PI_131__PI_BIST_PAT_MODE_MASK 0x03000000U
+#define LPDDR4__DENALI_PI_131__PI_BIST_PAT_MODE_SHIFT 24U
+#define LPDDR4__DENALI_PI_131__PI_BIST_PAT_MODE_WIDTH 2U
+#define LPDDR4__PI_BIST_PAT_MODE__REG DENALI_PI_131
+#define LPDDR4__PI_BIST_PAT_MODE__FLD LPDDR4__DENALI_PI_131__PI_BIST_PAT_MODE
+
+#define LPDDR4__DENALI_PI_132_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_132_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_132__PI_BIST_USER_PAT_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_132__PI_BIST_USER_PAT_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_132__PI_BIST_USER_PAT_0_WIDTH 32U
+#define LPDDR4__PI_BIST_USER_PAT_0__REG DENALI_PI_132
+#define LPDDR4__PI_BIST_USER_PAT_0__FLD LPDDR4__DENALI_PI_132__PI_BIST_USER_PAT_0
+
+#define LPDDR4__DENALI_PI_133_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_133_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_133__PI_BIST_USER_PAT_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_133__PI_BIST_USER_PAT_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_133__PI_BIST_USER_PAT_1_WIDTH 32U
+#define LPDDR4__PI_BIST_USER_PAT_1__REG DENALI_PI_133
+#define LPDDR4__PI_BIST_USER_PAT_1__FLD LPDDR4__DENALI_PI_133__PI_BIST_USER_PAT_1
+
+#define LPDDR4__DENALI_PI_134_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_134_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_134__PI_BIST_USER_PAT_2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_134__PI_BIST_USER_PAT_2_SHIFT 0U
+#define LPDDR4__DENALI_PI_134__PI_BIST_USER_PAT_2_WIDTH 32U
+#define LPDDR4__PI_BIST_USER_PAT_2__REG DENALI_PI_134
+#define LPDDR4__PI_BIST_USER_PAT_2__FLD LPDDR4__DENALI_PI_134__PI_BIST_USER_PAT_2
+
+#define LPDDR4__DENALI_PI_135_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_135_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_135__PI_BIST_USER_PAT_3_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_135__PI_BIST_USER_PAT_3_SHIFT 0U
+#define LPDDR4__DENALI_PI_135__PI_BIST_USER_PAT_3_WIDTH 32U
+#define LPDDR4__PI_BIST_USER_PAT_3__REG DENALI_PI_135
+#define LPDDR4__PI_BIST_USER_PAT_3__FLD LPDDR4__DENALI_PI_135__PI_BIST_USER_PAT_3
+
+#define LPDDR4__DENALI_PI_136_READ_MASK 0x0000007FU
+#define LPDDR4__DENALI_PI_136_WRITE_MASK 0x0000007FU
+#define LPDDR4__DENALI_PI_136__PI_BIST_PAT_NUM_MASK 0x0000007FU
+#define LPDDR4__DENALI_PI_136__PI_BIST_PAT_NUM_SHIFT 0U
+#define LPDDR4__DENALI_PI_136__PI_BIST_PAT_NUM_WIDTH 7U
+#define LPDDR4__PI_BIST_PAT_NUM__REG DENALI_PI_136
+#define LPDDR4__PI_BIST_PAT_NUM__FLD LPDDR4__DENALI_PI_136__PI_BIST_PAT_NUM
+
+#define LPDDR4__DENALI_PI_137_READ_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_137_WRITE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_137__PI_BIST_STAGE_0_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_137__PI_BIST_STAGE_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_137__PI_BIST_STAGE_0_WIDTH 30U
+#define LPDDR4__PI_BIST_STAGE_0__REG DENALI_PI_137
+#define LPDDR4__PI_BIST_STAGE_0__FLD LPDDR4__DENALI_PI_137__PI_BIST_STAGE_0
+
+#define LPDDR4__DENALI_PI_138_READ_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_138_WRITE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_138__PI_BIST_STAGE_1_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_138__PI_BIST_STAGE_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_138__PI_BIST_STAGE_1_WIDTH 30U
+#define LPDDR4__PI_BIST_STAGE_1__REG DENALI_PI_138
+#define LPDDR4__PI_BIST_STAGE_1__FLD LPDDR4__DENALI_PI_138__PI_BIST_STAGE_1
+
+#define LPDDR4__DENALI_PI_139_READ_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_139_WRITE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_139__PI_BIST_STAGE_2_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_139__PI_BIST_STAGE_2_SHIFT 0U
+#define LPDDR4__DENALI_PI_139__PI_BIST_STAGE_2_WIDTH 30U
+#define LPDDR4__PI_BIST_STAGE_2__REG DENALI_PI_139
+#define LPDDR4__PI_BIST_STAGE_2__FLD LPDDR4__DENALI_PI_139__PI_BIST_STAGE_2
+
+#define LPDDR4__DENALI_PI_140_READ_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_140_WRITE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_140__PI_BIST_STAGE_3_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_140__PI_BIST_STAGE_3_SHIFT 0U
+#define LPDDR4__DENALI_PI_140__PI_BIST_STAGE_3_WIDTH 30U
+#define LPDDR4__PI_BIST_STAGE_3__REG DENALI_PI_140
+#define LPDDR4__PI_BIST_STAGE_3__FLD LPDDR4__DENALI_PI_140__PI_BIST_STAGE_3
+
+#define LPDDR4__DENALI_PI_141_READ_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_141_WRITE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_141__PI_BIST_STAGE_4_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_141__PI_BIST_STAGE_4_SHIFT 0U
+#define LPDDR4__DENALI_PI_141__PI_BIST_STAGE_4_WIDTH 30U
+#define LPDDR4__PI_BIST_STAGE_4__REG DENALI_PI_141
+#define LPDDR4__PI_BIST_STAGE_4__FLD LPDDR4__DENALI_PI_141__PI_BIST_STAGE_4
+
+#define LPDDR4__DENALI_PI_142_READ_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_142_WRITE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_142__PI_BIST_STAGE_5_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_142__PI_BIST_STAGE_5_SHIFT 0U
+#define LPDDR4__DENALI_PI_142__PI_BIST_STAGE_5_WIDTH 30U
+#define LPDDR4__PI_BIST_STAGE_5__REG DENALI_PI_142
+#define LPDDR4__PI_BIST_STAGE_5__FLD LPDDR4__DENALI_PI_142__PI_BIST_STAGE_5
+
+#define LPDDR4__DENALI_PI_143_READ_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_143_WRITE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_143__PI_BIST_STAGE_6_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_143__PI_BIST_STAGE_6_SHIFT 0U
+#define LPDDR4__DENALI_PI_143__PI_BIST_STAGE_6_WIDTH 30U
+#define LPDDR4__PI_BIST_STAGE_6__REG DENALI_PI_143
+#define LPDDR4__PI_BIST_STAGE_6__FLD LPDDR4__DENALI_PI_143__PI_BIST_STAGE_6
+
+#define LPDDR4__DENALI_PI_144_READ_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_144_WRITE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_144__PI_BIST_STAGE_7_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_144__PI_BIST_STAGE_7_SHIFT 0U
+#define LPDDR4__DENALI_PI_144__PI_BIST_STAGE_7_WIDTH 30U
+#define LPDDR4__PI_BIST_STAGE_7__REG DENALI_PI_144
+#define LPDDR4__PI_BIST_STAGE_7__FLD LPDDR4__DENALI_PI_144__PI_BIST_STAGE_7
+
+#define LPDDR4__DENALI_PI_145_READ_MASK 0x0101010FU
+#define LPDDR4__DENALI_PI_145_WRITE_MASK 0x0101010FU
+#define LPDDR4__DENALI_PI_145__PI_COL_DIFF_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_145__PI_COL_DIFF_SHIFT 0U
+#define LPDDR4__DENALI_PI_145__PI_COL_DIFF_WIDTH 4U
+#define LPDDR4__PI_COL_DIFF__REG DENALI_PI_145
+#define LPDDR4__PI_COL_DIFF__FLD LPDDR4__DENALI_PI_145__PI_COL_DIFF
+
+#define LPDDR4__DENALI_PI_145__PI_BG_ROTATE_EN_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_145__PI_BG_ROTATE_EN_SHIFT 8U
+#define LPDDR4__DENALI_PI_145__PI_BG_ROTATE_EN_WIDTH 1U
+#define LPDDR4__DENALI_PI_145__PI_BG_ROTATE_EN_WOCLR 0U
+#define LPDDR4__DENALI_PI_145__PI_BG_ROTATE_EN_WOSET 0U
+#define LPDDR4__PI_BG_ROTATE_EN__REG DENALI_PI_145
+#define LPDDR4__PI_BG_ROTATE_EN__FLD LPDDR4__DENALI_PI_145__PI_BG_ROTATE_EN
+
+#define LPDDR4__DENALI_PI_145__PI_CRC_CALC_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_145__PI_CRC_CALC_SHIFT 16U
+#define LPDDR4__DENALI_PI_145__PI_CRC_CALC_WIDTH 1U
+#define LPDDR4__DENALI_PI_145__PI_CRC_CALC_WOCLR 0U
+#define LPDDR4__DENALI_PI_145__PI_CRC_CALC_WOSET 0U
+#define LPDDR4__PI_CRC_CALC__REG DENALI_PI_145
+#define LPDDR4__PI_CRC_CALC__FLD LPDDR4__DENALI_PI_145__PI_CRC_CALC
+
+#define LPDDR4__DENALI_PI_145__PI_SELF_REFRESH_EN_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_145__PI_SELF_REFRESH_EN_SHIFT 24U
+#define LPDDR4__DENALI_PI_145__PI_SELF_REFRESH_EN_WIDTH 1U
+#define LPDDR4__DENALI_PI_145__PI_SELF_REFRESH_EN_WOCLR 0U
+#define LPDDR4__DENALI_PI_145__PI_SELF_REFRESH_EN_WOSET 0U
+#define LPDDR4__PI_SELF_REFRESH_EN__REG DENALI_PI_145
+#define LPDDR4__PI_SELF_REFRESH_EN__FLD LPDDR4__DENALI_PI_145__PI_SELF_REFRESH_EN
+
+#define LPDDR4__DENALI_PI_146_READ_MASK 0x00010101U
+#define LPDDR4__DENALI_PI_146_WRITE_MASK 0x00010101U
+#define LPDDR4__DENALI_PI_146__PI_MC_PWRUP_SREFRESH_EXIT_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_146__PI_MC_PWRUP_SREFRESH_EXIT_SHIFT 0U
+#define LPDDR4__DENALI_PI_146__PI_MC_PWRUP_SREFRESH_EXIT_WIDTH 1U
+#define LPDDR4__DENALI_PI_146__PI_MC_PWRUP_SREFRESH_EXIT_WOCLR 0U
+#define LPDDR4__DENALI_PI_146__PI_MC_PWRUP_SREFRESH_EXIT_WOSET 0U
+#define LPDDR4__PI_MC_PWRUP_SREFRESH_EXIT__REG DENALI_PI_146
+#define LPDDR4__PI_MC_PWRUP_SREFRESH_EXIT__FLD LPDDR4__DENALI_PI_146__PI_MC_PWRUP_SREFRESH_EXIT
+
+#define LPDDR4__DENALI_PI_146__PI_PWRUP_SREFRESH_EXIT_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_146__PI_PWRUP_SREFRESH_EXIT_SHIFT 8U
+#define LPDDR4__DENALI_PI_146__PI_PWRUP_SREFRESH_EXIT_WIDTH 1U
+#define LPDDR4__DENALI_PI_146__PI_PWRUP_SREFRESH_EXIT_WOCLR 0U
+#define LPDDR4__DENALI_PI_146__PI_PWRUP_SREFRESH_EXIT_WOSET 0U
+#define LPDDR4__PI_PWRUP_SREFRESH_EXIT__REG DENALI_PI_146
+#define LPDDR4__PI_PWRUP_SREFRESH_EXIT__FLD LPDDR4__DENALI_PI_146__PI_PWRUP_SREFRESH_EXIT
+
+#define LPDDR4__DENALI_PI_146__PI_SREFRESH_EXIT_NO_REFRESH_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_146__PI_SREFRESH_EXIT_NO_REFRESH_SHIFT 16U
+#define LPDDR4__DENALI_PI_146__PI_SREFRESH_EXIT_NO_REFRESH_WIDTH 1U
+#define LPDDR4__DENALI_PI_146__PI_SREFRESH_EXIT_NO_REFRESH_WOCLR 0U
+#define LPDDR4__DENALI_PI_146__PI_SREFRESH_EXIT_NO_REFRESH_WOSET 0U
+#define LPDDR4__PI_SREFRESH_EXIT_NO_REFRESH__REG DENALI_PI_146
+#define LPDDR4__PI_SREFRESH_EXIT_NO_REFRESH__FLD LPDDR4__DENALI_PI_146__PI_SREFRESH_EXIT_NO_REFRESH
+
+#define LPDDR4__DENALI_PI_146__PI_SREF_ENTRY_REQ_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_146__PI_SREF_ENTRY_REQ_SHIFT 24U
+#define LPDDR4__DENALI_PI_146__PI_SREF_ENTRY_REQ_WIDTH 1U
+#define LPDDR4__DENALI_PI_146__PI_SREF_ENTRY_REQ_WOCLR 0U
+#define LPDDR4__DENALI_PI_146__PI_SREF_ENTRY_REQ_WOSET 0U
+#define LPDDR4__PI_SREF_ENTRY_REQ__REG DENALI_PI_146
+#define LPDDR4__PI_SREF_ENTRY_REQ__FLD LPDDR4__DENALI_PI_146__PI_SREF_ENTRY_REQ
+
+#define LPDDR4__DENALI_PI_147_READ_MASK 0x01010101U
+#define LPDDR4__DENALI_PI_147_WRITE_MASK 0x01010101U
+#define LPDDR4__DENALI_PI_147__PI_NO_MRW_BT_INIT_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_147__PI_NO_MRW_BT_INIT_SHIFT 0U
+#define LPDDR4__DENALI_PI_147__PI_NO_MRW_BT_INIT_WIDTH 1U
+#define LPDDR4__DENALI_PI_147__PI_NO_MRW_BT_INIT_WOCLR 0U
+#define LPDDR4__DENALI_PI_147__PI_NO_MRW_BT_INIT_WOSET 0U
+#define LPDDR4__PI_NO_MRW_BT_INIT__REG DENALI_PI_147
+#define LPDDR4__PI_NO_MRW_BT_INIT__FLD LPDDR4__DENALI_PI_147__PI_NO_MRW_BT_INIT
+
+#define LPDDR4__DENALI_PI_147__PI_NO_MRW_INIT_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_147__PI_NO_MRW_INIT_SHIFT 8U
+#define LPDDR4__DENALI_PI_147__PI_NO_MRW_INIT_WIDTH 1U
+#define LPDDR4__DENALI_PI_147__PI_NO_MRW_INIT_WOCLR 0U
+#define LPDDR4__DENALI_PI_147__PI_NO_MRW_INIT_WOSET 0U
+#define LPDDR4__PI_NO_MRW_INIT__REG DENALI_PI_147
+#define LPDDR4__PI_NO_MRW_INIT__FLD LPDDR4__DENALI_PI_147__PI_NO_MRW_INIT
+
+#define LPDDR4__DENALI_PI_147__PI_NO_PHY_IND_TRAIN_INIT_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_147__PI_NO_PHY_IND_TRAIN_INIT_SHIFT 16U
+#define LPDDR4__DENALI_PI_147__PI_NO_PHY_IND_TRAIN_INIT_WIDTH 1U
+#define LPDDR4__DENALI_PI_147__PI_NO_PHY_IND_TRAIN_INIT_WOCLR 0U
+#define LPDDR4__DENALI_PI_147__PI_NO_PHY_IND_TRAIN_INIT_WOSET 0U
+#define LPDDR4__PI_NO_PHY_IND_TRAIN_INIT__REG DENALI_PI_147
+#define LPDDR4__PI_NO_PHY_IND_TRAIN_INIT__FLD LPDDR4__DENALI_PI_147__PI_NO_PHY_IND_TRAIN_INIT
+
+#define LPDDR4__DENALI_PI_147__PI_NO_AUTO_MRR_INIT_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_147__PI_NO_AUTO_MRR_INIT_SHIFT 24U
+#define LPDDR4__DENALI_PI_147__PI_NO_AUTO_MRR_INIT_WIDTH 1U
+#define LPDDR4__DENALI_PI_147__PI_NO_AUTO_MRR_INIT_WOCLR 0U
+#define LPDDR4__DENALI_PI_147__PI_NO_AUTO_MRR_INIT_WOSET 0U
+#define LPDDR4__PI_NO_AUTO_MRR_INIT__REG DENALI_PI_147
+#define LPDDR4__PI_NO_AUTO_MRR_INIT__FLD LPDDR4__DENALI_PI_147__PI_NO_AUTO_MRR_INIT
+
+#define LPDDR4__DENALI_PI_148_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_148_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_148__PI_TRST_PWRON_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_148__PI_TRST_PWRON_SHIFT 0U
+#define LPDDR4__DENALI_PI_148__PI_TRST_PWRON_WIDTH 32U
+#define LPDDR4__PI_TRST_PWRON__REG DENALI_PI_148
+#define LPDDR4__PI_TRST_PWRON__FLD LPDDR4__DENALI_PI_148__PI_TRST_PWRON
+
+#define LPDDR4__DENALI_PI_149_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_149_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_149__PI_CKE_INACTIVE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_149__PI_CKE_INACTIVE_SHIFT 0U
+#define LPDDR4__DENALI_PI_149__PI_CKE_INACTIVE_WIDTH 32U
+#define LPDDR4__PI_CKE_INACTIVE__REG DENALI_PI_149
+#define LPDDR4__PI_CKE_INACTIVE__FLD LPDDR4__DENALI_PI_149__PI_CKE_INACTIVE
+
+#define LPDDR4__DENALI_PI_150_READ_MASK 0xFFFF0101U
+#define LPDDR4__DENALI_PI_150_WRITE_MASK 0xFFFF0101U
+#define LPDDR4__DENALI_PI_150__PI_DLL_RST_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_150__PI_DLL_RST_SHIFT 0U
+#define LPDDR4__DENALI_PI_150__PI_DLL_RST_WIDTH 1U
+#define LPDDR4__DENALI_PI_150__PI_DLL_RST_WOCLR 0U
+#define LPDDR4__DENALI_PI_150__PI_DLL_RST_WOSET 0U
+#define LPDDR4__PI_DLL_RST__REG DENALI_PI_150
+#define LPDDR4__PI_DLL_RST__FLD LPDDR4__DENALI_PI_150__PI_DLL_RST
+
+#define LPDDR4__DENALI_PI_150__PI_DRAM_INIT_EN_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_150__PI_DRAM_INIT_EN_SHIFT 8U
+#define LPDDR4__DENALI_PI_150__PI_DRAM_INIT_EN_WIDTH 1U
+#define LPDDR4__DENALI_PI_150__PI_DRAM_INIT_EN_WOCLR 0U
+#define LPDDR4__DENALI_PI_150__PI_DRAM_INIT_EN_WOSET 0U
+#define LPDDR4__PI_DRAM_INIT_EN__REG DENALI_PI_150
+#define LPDDR4__PI_DRAM_INIT_EN__FLD LPDDR4__DENALI_PI_150__PI_DRAM_INIT_EN
+
+#define LPDDR4__DENALI_PI_150__PI_DLL_RST_DELAY_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_PI_150__PI_DLL_RST_DELAY_SHIFT 16U
+#define LPDDR4__DENALI_PI_150__PI_DLL_RST_DELAY_WIDTH 16U
+#define LPDDR4__PI_DLL_RST_DELAY__REG DENALI_PI_150
+#define LPDDR4__PI_DLL_RST_DELAY__FLD LPDDR4__DENALI_PI_150__PI_DLL_RST_DELAY
+
+#define LPDDR4__DENALI_PI_151_READ_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_151_WRITE_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_151__PI_DLL_RST_ADJ_DLY_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_151__PI_DLL_RST_ADJ_DLY_SHIFT 0U
+#define LPDDR4__DENALI_PI_151__PI_DLL_RST_ADJ_DLY_WIDTH 8U
+#define LPDDR4__PI_DLL_RST_ADJ_DLY__REG DENALI_PI_151
+#define LPDDR4__PI_DLL_RST_ADJ_DLY__FLD LPDDR4__DENALI_PI_151__PI_DLL_RST_ADJ_DLY
+
+#define LPDDR4__DENALI_PI_152_READ_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_PI_152_WRITE_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_PI_152__PI_WRITE_MODEREG_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_PI_152__PI_WRITE_MODEREG_SHIFT 0U
+#define LPDDR4__DENALI_PI_152__PI_WRITE_MODEREG_WIDTH 26U
+#define LPDDR4__PI_WRITE_MODEREG__REG DENALI_PI_152
+#define LPDDR4__PI_WRITE_MODEREG__FLD LPDDR4__DENALI_PI_152__PI_WRITE_MODEREG
+
+#define LPDDR4__DENALI_PI_153_READ_MASK 0x000001FFU
+#define LPDDR4__DENALI_PI_153_WRITE_MASK 0x000001FFU
+#define LPDDR4__DENALI_PI_153__PI_MRW_STATUS_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_153__PI_MRW_STATUS_SHIFT 0U
+#define LPDDR4__DENALI_PI_153__PI_MRW_STATUS_WIDTH 8U
+#define LPDDR4__PI_MRW_STATUS__REG DENALI_PI_153
+#define LPDDR4__PI_MRW_STATUS__FLD LPDDR4__DENALI_PI_153__PI_MRW_STATUS
+
+#define LPDDR4__DENALI_PI_153__PI_RESERVED27_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_153__PI_RESERVED27_SHIFT 8U
+#define LPDDR4__DENALI_PI_153__PI_RESERVED27_WIDTH 1U
+#define LPDDR4__DENALI_PI_153__PI_RESERVED27_WOCLR 0U
+#define LPDDR4__DENALI_PI_153__PI_RESERVED27_WOSET 0U
+#define LPDDR4__PI_RESERVED27__REG DENALI_PI_153
+#define LPDDR4__PI_RESERVED27__FLD LPDDR4__DENALI_PI_153__PI_RESERVED27
+
+#define LPDDR4__DENALI_PI_154_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_154_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_154__PI_READ_MODEREG_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_154__PI_READ_MODEREG_SHIFT 0U
+#define LPDDR4__DENALI_PI_154__PI_READ_MODEREG_WIDTH 17U
+#define LPDDR4__PI_READ_MODEREG__REG DENALI_PI_154
+#define LPDDR4__PI_READ_MODEREG__FLD LPDDR4__DENALI_PI_154__PI_READ_MODEREG
+
+#define LPDDR4__DENALI_PI_155_READ_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_PI_155_WRITE_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_PI_155__PI_PERIPHERAL_MRR_DATA_0_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_155__PI_PERIPHERAL_MRR_DATA_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_155__PI_PERIPHERAL_MRR_DATA_0_WIDTH 24U
+#define LPDDR4__PI_PERIPHERAL_MRR_DATA_0__REG DENALI_PI_155
+#define LPDDR4__PI_PERIPHERAL_MRR_DATA_0__FLD LPDDR4__DENALI_PI_155__PI_PERIPHERAL_MRR_DATA_0
+
+#define LPDDR4__DENALI_PI_155__PI_NO_ZQ_INIT_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_155__PI_NO_ZQ_INIT_SHIFT 24U
+#define LPDDR4__DENALI_PI_155__PI_NO_ZQ_INIT_WIDTH 1U
+#define LPDDR4__DENALI_PI_155__PI_NO_ZQ_INIT_WOCLR 0U
+#define LPDDR4__DENALI_PI_155__PI_NO_ZQ_INIT_WOSET 0U
+#define LPDDR4__PI_NO_ZQ_INIT__REG DENALI_PI_155
+#define LPDDR4__PI_NO_ZQ_INIT__FLD LPDDR4__DENALI_PI_155__PI_NO_ZQ_INIT
+
+#define LPDDR4__DENALI_PI_156_READ_MASK 0x0101000FU
+#define LPDDR4__DENALI_PI_156_WRITE_MASK 0x0101000FU
+#define LPDDR4__DENALI_PI_156__PI_RESERVED28_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_156__PI_RESERVED28_SHIFT 0U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED28_WIDTH 4U
+#define LPDDR4__PI_RESERVED28__REG DENALI_PI_156
+#define LPDDR4__PI_RESERVED28__FLD LPDDR4__DENALI_PI_156__PI_RESERVED28
+
+#define LPDDR4__DENALI_PI_156__PI_RESERVED29_MASK 0x00000F00U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED29_SHIFT 8U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED29_WIDTH 4U
+#define LPDDR4__PI_RESERVED29__REG DENALI_PI_156
+#define LPDDR4__PI_RESERVED29__FLD LPDDR4__DENALI_PI_156__PI_RESERVED29
+
+#define LPDDR4__DENALI_PI_156__PI_ZQ_REQ_PENDING_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_156__PI_ZQ_REQ_PENDING_SHIFT 16U
+#define LPDDR4__DENALI_PI_156__PI_ZQ_REQ_PENDING_WIDTH 1U
+#define LPDDR4__DENALI_PI_156__PI_ZQ_REQ_PENDING_WOCLR 0U
+#define LPDDR4__DENALI_PI_156__PI_ZQ_REQ_PENDING_WOSET 0U
+#define LPDDR4__PI_ZQ_REQ_PENDING__REG DENALI_PI_156
+#define LPDDR4__PI_ZQ_REQ_PENDING__FLD LPDDR4__DENALI_PI_156__PI_ZQ_REQ_PENDING
+
+#define LPDDR4__DENALI_PI_156__PI_RESERVED30_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED30_SHIFT 24U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED30_WIDTH 1U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED30_WOCLR 0U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED30_WOSET 0U
+#define LPDDR4__PI_RESERVED30__REG DENALI_PI_156
+#define LPDDR4__PI_RESERVED30__FLD LPDDR4__DENALI_PI_156__PI_RESERVED30
+
+#define LPDDR4__DENALI_PI_157_READ_MASK 0xFF010F07U
+#define LPDDR4__DENALI_PI_157_WRITE_MASK 0xFF010F07U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED31_MASK 0x00000007U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED31_SHIFT 0U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED31_WIDTH 3U
+#define LPDDR4__PI_RESERVED31__REG DENALI_PI_157
+#define LPDDR4__PI_RESERVED31__FLD LPDDR4__DENALI_PI_157__PI_RESERVED31
+
+#define LPDDR4__DENALI_PI_157__PI_MONITOR_SRC_SEL_0_MASK 0x00000F00U
+#define LPDDR4__DENALI_PI_157__PI_MONITOR_SRC_SEL_0_SHIFT 8U
+#define LPDDR4__DENALI_PI_157__PI_MONITOR_SRC_SEL_0_WIDTH 4U
+#define LPDDR4__PI_MONITOR_SRC_SEL_0__REG DENALI_PI_157
+#define LPDDR4__PI_MONITOR_SRC_SEL_0__FLD LPDDR4__DENALI_PI_157__PI_MONITOR_SRC_SEL_0
+
+#define LPDDR4__DENALI_PI_157__PI_MONITOR_CAP_SEL_0_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_157__PI_MONITOR_CAP_SEL_0_SHIFT 16U
+#define LPDDR4__DENALI_PI_157__PI_MONITOR_CAP_SEL_0_WIDTH 1U
+#define LPDDR4__DENALI_PI_157__PI_MONITOR_CAP_SEL_0_WOCLR 0U
+#define LPDDR4__DENALI_PI_157__PI_MONITOR_CAP_SEL_0_WOSET 0U
+#define LPDDR4__PI_MONITOR_CAP_SEL_0__REG DENALI_PI_157
+#define LPDDR4__PI_MONITOR_CAP_SEL_0__FLD LPDDR4__DENALI_PI_157__PI_MONITOR_CAP_SEL_0
+
+#define LPDDR4__DENALI_PI_157__PI_MONITOR_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_157__PI_MONITOR_0_SHIFT 24U
+#define LPDDR4__DENALI_PI_157__PI_MONITOR_0_WIDTH 8U
+#define LPDDR4__PI_MONITOR_0__REG DENALI_PI_157
+#define LPDDR4__PI_MONITOR_0__FLD LPDDR4__DENALI_PI_157__PI_MONITOR_0
+
+#define LPDDR4__DENALI_PI_158_READ_MASK 0x0FFF010FU
+#define LPDDR4__DENALI_PI_158_WRITE_MASK 0x0FFF010FU
+#define LPDDR4__DENALI_PI_158__PI_MONITOR_SRC_SEL_1_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_158__PI_MONITOR_SRC_SEL_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_158__PI_MONITOR_SRC_SEL_1_WIDTH 4U
+#define LPDDR4__PI_MONITOR_SRC_SEL_1__REG DENALI_PI_158
+#define LPDDR4__PI_MONITOR_SRC_SEL_1__FLD LPDDR4__DENALI_PI_158__PI_MONITOR_SRC_SEL_1
+
+#define LPDDR4__DENALI_PI_158__PI_MONITOR_CAP_SEL_1_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_158__PI_MONITOR_CAP_SEL_1_SHIFT 8U
+#define LPDDR4__DENALI_PI_158__PI_MONITOR_CAP_SEL_1_WIDTH 1U
+#define LPDDR4__DENALI_PI_158__PI_MONITOR_CAP_SEL_1_WOCLR 0U
+#define LPDDR4__DENALI_PI_158__PI_MONITOR_CAP_SEL_1_WOSET 0U
+#define LPDDR4__PI_MONITOR_CAP_SEL_1__REG DENALI_PI_158
+#define LPDDR4__PI_MONITOR_CAP_SEL_1__FLD LPDDR4__DENALI_PI_158__PI_MONITOR_CAP_SEL_1
+
+#define LPDDR4__DENALI_PI_158__PI_MONITOR_1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_158__PI_MONITOR_1_SHIFT 16U
+#define LPDDR4__DENALI_PI_158__PI_MONITOR_1_WIDTH 8U
+#define LPDDR4__PI_MONITOR_1__REG DENALI_PI_158
+#define LPDDR4__PI_MONITOR_1__FLD LPDDR4__DENALI_PI_158__PI_MONITOR_1
+
+#define LPDDR4__DENALI_PI_158__PI_MONITOR_SRC_SEL_2_MASK 0x0F000000U
+#define LPDDR4__DENALI_PI_158__PI_MONITOR_SRC_SEL_2_SHIFT 24U
+#define LPDDR4__DENALI_PI_158__PI_MONITOR_SRC_SEL_2_WIDTH 4U
+#define LPDDR4__PI_MONITOR_SRC_SEL_2__REG DENALI_PI_158
+#define LPDDR4__PI_MONITOR_SRC_SEL_2__FLD LPDDR4__DENALI_PI_158__PI_MONITOR_SRC_SEL_2
+
+#define LPDDR4__DENALI_PI_159_READ_MASK 0x010FFF01U
+#define LPDDR4__DENALI_PI_159_WRITE_MASK 0x010FFF01U
+#define LPDDR4__DENALI_PI_159__PI_MONITOR_CAP_SEL_2_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_159__PI_MONITOR_CAP_SEL_2_SHIFT 0U
+#define LPDDR4__DENALI_PI_159__PI_MONITOR_CAP_SEL_2_WIDTH 1U
+#define LPDDR4__DENALI_PI_159__PI_MONITOR_CAP_SEL_2_WOCLR 0U
+#define LPDDR4__DENALI_PI_159__PI_MONITOR_CAP_SEL_2_WOSET 0U
+#define LPDDR4__PI_MONITOR_CAP_SEL_2__REG DENALI_PI_159
+#define LPDDR4__PI_MONITOR_CAP_SEL_2__FLD LPDDR4__DENALI_PI_159__PI_MONITOR_CAP_SEL_2
+
+#define LPDDR4__DENALI_PI_159__PI_MONITOR_2_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_159__PI_MONITOR_2_SHIFT 8U
+#define LPDDR4__DENALI_PI_159__PI_MONITOR_2_WIDTH 8U
+#define LPDDR4__PI_MONITOR_2__REG DENALI_PI_159
+#define LPDDR4__PI_MONITOR_2__FLD LPDDR4__DENALI_PI_159__PI_MONITOR_2
+
+#define LPDDR4__DENALI_PI_159__PI_MONITOR_SRC_SEL_3_MASK 0x000F0000U
+#define LPDDR4__DENALI_PI_159__PI_MONITOR_SRC_SEL_3_SHIFT 16U
+#define LPDDR4__DENALI_PI_159__PI_MONITOR_SRC_SEL_3_WIDTH 4U
+#define LPDDR4__PI_MONITOR_SRC_SEL_3__REG DENALI_PI_159
+#define LPDDR4__PI_MONITOR_SRC_SEL_3__FLD LPDDR4__DENALI_PI_159__PI_MONITOR_SRC_SEL_3
+
+#define LPDDR4__DENALI_PI_159__PI_MONITOR_CAP_SEL_3_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_159__PI_MONITOR_CAP_SEL_3_SHIFT 24U
+#define LPDDR4__DENALI_PI_159__PI_MONITOR_CAP_SEL_3_WIDTH 1U
+#define LPDDR4__DENALI_PI_159__PI_MONITOR_CAP_SEL_3_WOCLR 0U
+#define LPDDR4__DENALI_PI_159__PI_MONITOR_CAP_SEL_3_WOSET 0U
+#define LPDDR4__PI_MONITOR_CAP_SEL_3__REG DENALI_PI_159
+#define LPDDR4__PI_MONITOR_CAP_SEL_3__FLD LPDDR4__DENALI_PI_159__PI_MONITOR_CAP_SEL_3
+
+#define LPDDR4__DENALI_PI_160_READ_MASK 0xFF010FFFU
+#define LPDDR4__DENALI_PI_160_WRITE_MASK 0xFF010FFFU
+#define LPDDR4__DENALI_PI_160__PI_MONITOR_3_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_160__PI_MONITOR_3_SHIFT 0U
+#define LPDDR4__DENALI_PI_160__PI_MONITOR_3_WIDTH 8U
+#define LPDDR4__PI_MONITOR_3__REG DENALI_PI_160
+#define LPDDR4__PI_MONITOR_3__FLD LPDDR4__DENALI_PI_160__PI_MONITOR_3
+
+#define LPDDR4__DENALI_PI_160__PI_MONITOR_SRC_SEL_4_MASK 0x00000F00U
+#define LPDDR4__DENALI_PI_160__PI_MONITOR_SRC_SEL_4_SHIFT 8U
+#define LPDDR4__DENALI_PI_160__PI_MONITOR_SRC_SEL_4_WIDTH 4U
+#define LPDDR4__PI_MONITOR_SRC_SEL_4__REG DENALI_PI_160
+#define LPDDR4__PI_MONITOR_SRC_SEL_4__FLD LPDDR4__DENALI_PI_160__PI_MONITOR_SRC_SEL_4
+
+#define LPDDR4__DENALI_PI_160__PI_MONITOR_CAP_SEL_4_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_160__PI_MONITOR_CAP_SEL_4_SHIFT 16U
+#define LPDDR4__DENALI_PI_160__PI_MONITOR_CAP_SEL_4_WIDTH 1U
+#define LPDDR4__DENALI_PI_160__PI_MONITOR_CAP_SEL_4_WOCLR 0U
+#define LPDDR4__DENALI_PI_160__PI_MONITOR_CAP_SEL_4_WOSET 0U
+#define LPDDR4__PI_MONITOR_CAP_SEL_4__REG DENALI_PI_160
+#define LPDDR4__PI_MONITOR_CAP_SEL_4__FLD LPDDR4__DENALI_PI_160__PI_MONITOR_CAP_SEL_4
+
+#define LPDDR4__DENALI_PI_160__PI_MONITOR_4_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_160__PI_MONITOR_4_SHIFT 24U
+#define LPDDR4__DENALI_PI_160__PI_MONITOR_4_WIDTH 8U
+#define LPDDR4__PI_MONITOR_4__REG DENALI_PI_160
+#define LPDDR4__PI_MONITOR_4__FLD LPDDR4__DENALI_PI_160__PI_MONITOR_4
+
+#define LPDDR4__DENALI_PI_161_READ_MASK 0x0FFF010FU
+#define LPDDR4__DENALI_PI_161_WRITE_MASK 0x0FFF010FU
+#define LPDDR4__DENALI_PI_161__PI_MONITOR_SRC_SEL_5_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_161__PI_MONITOR_SRC_SEL_5_SHIFT 0U
+#define LPDDR4__DENALI_PI_161__PI_MONITOR_SRC_SEL_5_WIDTH 4U
+#define LPDDR4__PI_MONITOR_SRC_SEL_5__REG DENALI_PI_161
+#define LPDDR4__PI_MONITOR_SRC_SEL_5__FLD LPDDR4__DENALI_PI_161__PI_MONITOR_SRC_SEL_5
+
+#define LPDDR4__DENALI_PI_161__PI_MONITOR_CAP_SEL_5_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_161__PI_MONITOR_CAP_SEL_5_SHIFT 8U
+#define LPDDR4__DENALI_PI_161__PI_MONITOR_CAP_SEL_5_WIDTH 1U
+#define LPDDR4__DENALI_PI_161__PI_MONITOR_CAP_SEL_5_WOCLR 0U
+#define LPDDR4__DENALI_PI_161__PI_MONITOR_CAP_SEL_5_WOSET 0U
+#define LPDDR4__PI_MONITOR_CAP_SEL_5__REG DENALI_PI_161
+#define LPDDR4__PI_MONITOR_CAP_SEL_5__FLD LPDDR4__DENALI_PI_161__PI_MONITOR_CAP_SEL_5
+
+#define LPDDR4__DENALI_PI_161__PI_MONITOR_5_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_161__PI_MONITOR_5_SHIFT 16U
+#define LPDDR4__DENALI_PI_161__PI_MONITOR_5_WIDTH 8U
+#define LPDDR4__PI_MONITOR_5__REG DENALI_PI_161
+#define LPDDR4__PI_MONITOR_5__FLD LPDDR4__DENALI_PI_161__PI_MONITOR_5
+
+#define LPDDR4__DENALI_PI_161__PI_MONITOR_SRC_SEL_6_MASK 0x0F000000U
+#define LPDDR4__DENALI_PI_161__PI_MONITOR_SRC_SEL_6_SHIFT 24U
+#define LPDDR4__DENALI_PI_161__PI_MONITOR_SRC_SEL_6_WIDTH 4U
+#define LPDDR4__PI_MONITOR_SRC_SEL_6__REG DENALI_PI_161
+#define LPDDR4__PI_MONITOR_SRC_SEL_6__FLD LPDDR4__DENALI_PI_161__PI_MONITOR_SRC_SEL_6
+
+#define LPDDR4__DENALI_PI_162_READ_MASK 0x010FFF01U
+#define LPDDR4__DENALI_PI_162_WRITE_MASK 0x010FFF01U
+#define LPDDR4__DENALI_PI_162__PI_MONITOR_CAP_SEL_6_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_162__PI_MONITOR_CAP_SEL_6_SHIFT 0U
+#define LPDDR4__DENALI_PI_162__PI_MONITOR_CAP_SEL_6_WIDTH 1U
+#define LPDDR4__DENALI_PI_162__PI_MONITOR_CAP_SEL_6_WOCLR 0U
+#define LPDDR4__DENALI_PI_162__PI_MONITOR_CAP_SEL_6_WOSET 0U
+#define LPDDR4__PI_MONITOR_CAP_SEL_6__REG DENALI_PI_162
+#define LPDDR4__PI_MONITOR_CAP_SEL_6__FLD LPDDR4__DENALI_PI_162__PI_MONITOR_CAP_SEL_6
+
+#define LPDDR4__DENALI_PI_162__PI_MONITOR_6_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_162__PI_MONITOR_6_SHIFT 8U
+#define LPDDR4__DENALI_PI_162__PI_MONITOR_6_WIDTH 8U
+#define LPDDR4__PI_MONITOR_6__REG DENALI_PI_162
+#define LPDDR4__PI_MONITOR_6__FLD LPDDR4__DENALI_PI_162__PI_MONITOR_6
+
+#define LPDDR4__DENALI_PI_162__PI_MONITOR_SRC_SEL_7_MASK 0x000F0000U
+#define LPDDR4__DENALI_PI_162__PI_MONITOR_SRC_SEL_7_SHIFT 16U
+#define LPDDR4__DENALI_PI_162__PI_MONITOR_SRC_SEL_7_WIDTH 4U
+#define LPDDR4__PI_MONITOR_SRC_SEL_7__REG DENALI_PI_162
+#define LPDDR4__PI_MONITOR_SRC_SEL_7__FLD LPDDR4__DENALI_PI_162__PI_MONITOR_SRC_SEL_7
+
+#define LPDDR4__DENALI_PI_162__PI_MONITOR_CAP_SEL_7_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_162__PI_MONITOR_CAP_SEL_7_SHIFT 24U
+#define LPDDR4__DENALI_PI_162__PI_MONITOR_CAP_SEL_7_WIDTH 1U
+#define LPDDR4__DENALI_PI_162__PI_MONITOR_CAP_SEL_7_WOCLR 0U
+#define LPDDR4__DENALI_PI_162__PI_MONITOR_CAP_SEL_7_WOSET 0U
+#define LPDDR4__PI_MONITOR_CAP_SEL_7__REG DENALI_PI_162
+#define LPDDR4__PI_MONITOR_CAP_SEL_7__FLD LPDDR4__DENALI_PI_162__PI_MONITOR_CAP_SEL_7
+
+#define LPDDR4__DENALI_PI_163_READ_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_163_WRITE_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_163__PI_MONITOR_7_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_163__PI_MONITOR_7_SHIFT 0U
+#define LPDDR4__DENALI_PI_163__PI_MONITOR_7_WIDTH 8U
+#define LPDDR4__PI_MONITOR_7__REG DENALI_PI_163
+#define LPDDR4__PI_MONITOR_7__FLD LPDDR4__DENALI_PI_163__PI_MONITOR_7
+
+#define LPDDR4__DENALI_PI_164__PI_MONITOR_STROBE_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_164__PI_MONITOR_STROBE_SHIFT 0U
+#define LPDDR4__DENALI_PI_164__PI_MONITOR_STROBE_WIDTH 8U
+#define LPDDR4__PI_MONITOR_STROBE__REG DENALI_PI_164
+#define LPDDR4__PI_MONITOR_STROBE__FLD LPDDR4__DENALI_PI_164__PI_MONITOR_STROBE
+
+#define LPDDR4__DENALI_PI_165_READ_MASK 0x011F1F01U
+#define LPDDR4__DENALI_PI_165_WRITE_MASK 0x011F1F01U
+#define LPDDR4__DENALI_PI_165__PI_DLL_LOCK_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_165__PI_DLL_LOCK_SHIFT 0U
+#define LPDDR4__DENALI_PI_165__PI_DLL_LOCK_WIDTH 1U
+#define LPDDR4__DENALI_PI_165__PI_DLL_LOCK_WOCLR 0U
+#define LPDDR4__DENALI_PI_165__PI_DLL_LOCK_WOSET 0U
+#define LPDDR4__PI_DLL_LOCK__REG DENALI_PI_165
+#define LPDDR4__PI_DLL_LOCK__FLD LPDDR4__DENALI_PI_165__PI_DLL_LOCK
+
+#define LPDDR4__DENALI_PI_165__PI_FREQ_NUMBER_STATUS_MASK 0x00001F00U
+#define LPDDR4__DENALI_PI_165__PI_FREQ_NUMBER_STATUS_SHIFT 8U
+#define LPDDR4__DENALI_PI_165__PI_FREQ_NUMBER_STATUS_WIDTH 5U
+#define LPDDR4__PI_FREQ_NUMBER_STATUS__REG DENALI_PI_165
+#define LPDDR4__PI_FREQ_NUMBER_STATUS__FLD LPDDR4__DENALI_PI_165__PI_FREQ_NUMBER_STATUS
+
+#define LPDDR4__DENALI_PI_165__PI_FREQ_RETENTION_NUM_MASK 0x001F0000U
+#define LPDDR4__DENALI_PI_165__PI_FREQ_RETENTION_NUM_SHIFT 16U
+#define LPDDR4__DENALI_PI_165__PI_FREQ_RETENTION_NUM_WIDTH 5U
+#define LPDDR4__PI_FREQ_RETENTION_NUM__REG DENALI_PI_165
+#define LPDDR4__PI_FREQ_RETENTION_NUM__FLD LPDDR4__DENALI_PI_165__PI_FREQ_RETENTION_NUM
+
+#define LPDDR4__DENALI_PI_165__PI_RESERVED32_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_165__PI_RESERVED32_SHIFT 24U
+#define LPDDR4__DENALI_PI_165__PI_RESERVED32_WIDTH 1U
+#define LPDDR4__DENALI_PI_165__PI_RESERVED32_WOCLR 0U
+#define LPDDR4__DENALI_PI_165__PI_RESERVED32_WOSET 0U
+#define LPDDR4__PI_RESERVED32__REG DENALI_PI_165
+#define LPDDR4__PI_RESERVED32__FLD LPDDR4__DENALI_PI_165__PI_RESERVED32
+
+#define LPDDR4__DENALI_PI_166_READ_MASK 0x01010103U
+#define LPDDR4__DENALI_PI_166_WRITE_MASK 0x01010103U
+#define LPDDR4__DENALI_PI_166__PI_PHYMSTR_TYPE_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_166__PI_PHYMSTR_TYPE_SHIFT 0U
+#define LPDDR4__DENALI_PI_166__PI_PHYMSTR_TYPE_WIDTH 2U
+#define LPDDR4__PI_PHYMSTR_TYPE__REG DENALI_PI_166
+#define LPDDR4__PI_PHYMSTR_TYPE__FLD LPDDR4__DENALI_PI_166__PI_PHYMSTR_TYPE
+
+#define LPDDR4__DENALI_PI_166__PI_RESERVED33_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_166__PI_RESERVED33_SHIFT 8U
+#define LPDDR4__DENALI_PI_166__PI_RESERVED33_WIDTH 1U
+#define LPDDR4__DENALI_PI_166__PI_RESERVED33_WOCLR 0U
+#define LPDDR4__DENALI_PI_166__PI_RESERVED33_WOSET 0U
+#define LPDDR4__PI_RESERVED33__REG DENALI_PI_166
+#define LPDDR4__PI_RESERVED33__FLD LPDDR4__DENALI_PI_166__PI_RESERVED33
+
+#define LPDDR4__DENALI_PI_166__PI_POWER_REDUC_EN_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_166__PI_POWER_REDUC_EN_SHIFT 16U
+#define LPDDR4__DENALI_PI_166__PI_POWER_REDUC_EN_WIDTH 1U
+#define LPDDR4__DENALI_PI_166__PI_POWER_REDUC_EN_WOCLR 0U
+#define LPDDR4__DENALI_PI_166__PI_POWER_REDUC_EN_WOSET 0U
+#define LPDDR4__PI_POWER_REDUC_EN__REG DENALI_PI_166
+#define LPDDR4__PI_POWER_REDUC_EN__FLD LPDDR4__DENALI_PI_166__PI_POWER_REDUC_EN
+
+#define LPDDR4__DENALI_PI_166__PI_RESERVED34_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_166__PI_RESERVED34_SHIFT 24U
+#define LPDDR4__DENALI_PI_166__PI_RESERVED34_WIDTH 1U
+#define LPDDR4__DENALI_PI_166__PI_RESERVED34_WOCLR 0U
+#define LPDDR4__DENALI_PI_166__PI_RESERVED34_WOSET 0U
+#define LPDDR4__PI_RESERVED34__REG DENALI_PI_166
+#define LPDDR4__PI_RESERVED34__FLD LPDDR4__DENALI_PI_166__PI_RESERVED34
+
+#define LPDDR4__DENALI_PI_167_READ_MASK 0x01010101U
+#define LPDDR4__DENALI_PI_167_WRITE_MASK 0x01010101U
+#define LPDDR4__DENALI_PI_167__PI_RESERVED35_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_167__PI_RESERVED35_SHIFT 0U
+#define LPDDR4__DENALI_PI_167__PI_RESERVED35_WIDTH 1U
+#define LPDDR4__DENALI_PI_167__PI_RESERVED35_WOCLR 0U
+#define LPDDR4__DENALI_PI_167__PI_RESERVED35_WOSET 0U
+#define LPDDR4__PI_RESERVED35__REG DENALI_PI_167
+#define LPDDR4__PI_RESERVED35__FLD LPDDR4__DENALI_PI_167__PI_RESERVED35
+
+#define LPDDR4__DENALI_PI_167__PI_RESERVED36_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_167__PI_RESERVED36_SHIFT 8U
+#define LPDDR4__DENALI_PI_167__PI_RESERVED36_WIDTH 1U
+#define LPDDR4__DENALI_PI_167__PI_RESERVED36_WOCLR 0U
+#define LPDDR4__DENALI_PI_167__PI_RESERVED36_WOSET 0U
+#define LPDDR4__PI_RESERVED36__REG DENALI_PI_167
+#define LPDDR4__PI_RESERVED36__FLD LPDDR4__DENALI_PI_167__PI_RESERVED36
+
+#define LPDDR4__DENALI_PI_167__PI_RESERVED37_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_167__PI_RESERVED37_SHIFT 16U
+#define LPDDR4__DENALI_PI_167__PI_RESERVED37_WIDTH 1U
+#define LPDDR4__DENALI_PI_167__PI_RESERVED37_WOCLR 0U
+#define LPDDR4__DENALI_PI_167__PI_RESERVED37_WOSET 0U
+#define LPDDR4__PI_RESERVED37__REG DENALI_PI_167
+#define LPDDR4__PI_RESERVED37__FLD LPDDR4__DENALI_PI_167__PI_RESERVED37
+
+#define LPDDR4__DENALI_PI_167__PI_RESERVED38_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_167__PI_RESERVED38_SHIFT 24U
+#define LPDDR4__DENALI_PI_167__PI_RESERVED38_WIDTH 1U
+#define LPDDR4__DENALI_PI_167__PI_RESERVED38_WOCLR 0U
+#define LPDDR4__DENALI_PI_167__PI_RESERVED38_WOSET 0U
+#define LPDDR4__PI_RESERVED38__REG DENALI_PI_167
+#define LPDDR4__PI_RESERVED38__FLD LPDDR4__DENALI_PI_167__PI_RESERVED38
+
+#define LPDDR4__DENALI_PI_168_READ_MASK 0x01010101U
+#define LPDDR4__DENALI_PI_168_WRITE_MASK 0x01010101U
+#define LPDDR4__DENALI_PI_168__PI_RESERVED39_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_168__PI_RESERVED39_SHIFT 0U
+#define LPDDR4__DENALI_PI_168__PI_RESERVED39_WIDTH 1U
+#define LPDDR4__DENALI_PI_168__PI_RESERVED39_WOCLR 0U
+#define LPDDR4__DENALI_PI_168__PI_RESERVED39_WOSET 0U
+#define LPDDR4__PI_RESERVED39__REG DENALI_PI_168
+#define LPDDR4__PI_RESERVED39__FLD LPDDR4__DENALI_PI_168__PI_RESERVED39
+
+#define LPDDR4__DENALI_PI_168__PI_RESERVED40_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_168__PI_RESERVED40_SHIFT 8U
+#define LPDDR4__DENALI_PI_168__PI_RESERVED40_WIDTH 1U
+#define LPDDR4__DENALI_PI_168__PI_RESERVED40_WOCLR 0U
+#define LPDDR4__DENALI_PI_168__PI_RESERVED40_WOSET 0U
+#define LPDDR4__PI_RESERVED40__REG DENALI_PI_168
+#define LPDDR4__PI_RESERVED40__FLD LPDDR4__DENALI_PI_168__PI_RESERVED40
+
+#define LPDDR4__DENALI_PI_168__PI_RESERVED41_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_168__PI_RESERVED41_SHIFT 16U
+#define LPDDR4__DENALI_PI_168__PI_RESERVED41_WIDTH 1U
+#define LPDDR4__DENALI_PI_168__PI_RESERVED41_WOCLR 0U
+#define LPDDR4__DENALI_PI_168__PI_RESERVED41_WOSET 0U
+#define LPDDR4__PI_RESERVED41__REG DENALI_PI_168
+#define LPDDR4__PI_RESERVED41__FLD LPDDR4__DENALI_PI_168__PI_RESERVED41
+
+#define LPDDR4__DENALI_PI_168__PI_RESERVED42_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_168__PI_RESERVED42_SHIFT 24U
+#define LPDDR4__DENALI_PI_168__PI_RESERVED42_WIDTH 1U
+#define LPDDR4__DENALI_PI_168__PI_RESERVED42_WOCLR 0U
+#define LPDDR4__DENALI_PI_168__PI_RESERVED42_WOSET 0U
+#define LPDDR4__PI_RESERVED42__REG DENALI_PI_168
+#define LPDDR4__PI_RESERVED42__FLD LPDDR4__DENALI_PI_168__PI_RESERVED42
+
+#define LPDDR4__DENALI_PI_169_READ_MASK 0x01010101U
+#define LPDDR4__DENALI_PI_169_WRITE_MASK 0x01010101U
+#define LPDDR4__DENALI_PI_169__PI_RESERVED43_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_169__PI_RESERVED43_SHIFT 0U
+#define LPDDR4__DENALI_PI_169__PI_RESERVED43_WIDTH 1U
+#define LPDDR4__DENALI_PI_169__PI_RESERVED43_WOCLR 0U
+#define LPDDR4__DENALI_PI_169__PI_RESERVED43_WOSET 0U
+#define LPDDR4__PI_RESERVED43__REG DENALI_PI_169
+#define LPDDR4__PI_RESERVED43__FLD LPDDR4__DENALI_PI_169__PI_RESERVED43
+
+#define LPDDR4__DENALI_PI_169__PI_RESERVED44_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_169__PI_RESERVED44_SHIFT 8U
+#define LPDDR4__DENALI_PI_169__PI_RESERVED44_WIDTH 1U
+#define LPDDR4__DENALI_PI_169__PI_RESERVED44_WOCLR 0U
+#define LPDDR4__DENALI_PI_169__PI_RESERVED44_WOSET 0U
+#define LPDDR4__PI_RESERVED44__REG DENALI_PI_169
+#define LPDDR4__PI_RESERVED44__FLD LPDDR4__DENALI_PI_169__PI_RESERVED44
+
+#define LPDDR4__DENALI_PI_169__PI_RESERVED45_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_169__PI_RESERVED45_SHIFT 16U
+#define LPDDR4__DENALI_PI_169__PI_RESERVED45_WIDTH 1U
+#define LPDDR4__DENALI_PI_169__PI_RESERVED45_WOCLR 0U
+#define LPDDR4__DENALI_PI_169__PI_RESERVED45_WOSET 0U
+#define LPDDR4__PI_RESERVED45__REG DENALI_PI_169
+#define LPDDR4__PI_RESERVED45__FLD LPDDR4__DENALI_PI_169__PI_RESERVED45
+
+#define LPDDR4__DENALI_PI_169__PI_RESERVED46_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_169__PI_RESERVED46_SHIFT 24U
+#define LPDDR4__DENALI_PI_169__PI_RESERVED46_WIDTH 1U
+#define LPDDR4__DENALI_PI_169__PI_RESERVED46_WOCLR 0U
+#define LPDDR4__DENALI_PI_169__PI_RESERVED46_WOSET 0U
+#define LPDDR4__PI_RESERVED46__REG DENALI_PI_169
+#define LPDDR4__PI_RESERVED46__FLD LPDDR4__DENALI_PI_169__PI_RESERVED46
+
+#define LPDDR4__DENALI_PI_170_READ_MASK 0x01010101U
+#define LPDDR4__DENALI_PI_170_WRITE_MASK 0x01010101U
+#define LPDDR4__DENALI_PI_170__PI_RESERVED47_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_170__PI_RESERVED47_SHIFT 0U
+#define LPDDR4__DENALI_PI_170__PI_RESERVED47_WIDTH 1U
+#define LPDDR4__DENALI_PI_170__PI_RESERVED47_WOCLR 0U
+#define LPDDR4__DENALI_PI_170__PI_RESERVED47_WOSET 0U
+#define LPDDR4__PI_RESERVED47__REG DENALI_PI_170
+#define LPDDR4__PI_RESERVED47__FLD LPDDR4__DENALI_PI_170__PI_RESERVED47
+
+#define LPDDR4__DENALI_PI_170__PI_RESERVED48_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_170__PI_RESERVED48_SHIFT 8U
+#define LPDDR4__DENALI_PI_170__PI_RESERVED48_WIDTH 1U
+#define LPDDR4__DENALI_PI_170__PI_RESERVED48_WOCLR 0U
+#define LPDDR4__DENALI_PI_170__PI_RESERVED48_WOSET 0U
+#define LPDDR4__PI_RESERVED48__REG DENALI_PI_170
+#define LPDDR4__PI_RESERVED48__FLD LPDDR4__DENALI_PI_170__PI_RESERVED48
+
+#define LPDDR4__DENALI_PI_170__PI_RESERVED49_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_170__PI_RESERVED49_SHIFT 16U
+#define LPDDR4__DENALI_PI_170__PI_RESERVED49_WIDTH 1U
+#define LPDDR4__DENALI_PI_170__PI_RESERVED49_WOCLR 0U
+#define LPDDR4__DENALI_PI_170__PI_RESERVED49_WOSET 0U
+#define LPDDR4__PI_RESERVED49__REG DENALI_PI_170
+#define LPDDR4__PI_RESERVED49__FLD LPDDR4__DENALI_PI_170__PI_RESERVED49
+
+#define LPDDR4__DENALI_PI_170__PI_RESERVED50_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_170__PI_RESERVED50_SHIFT 24U
+#define LPDDR4__DENALI_PI_170__PI_RESERVED50_WIDTH 1U
+#define LPDDR4__DENALI_PI_170__PI_RESERVED50_WOCLR 0U
+#define LPDDR4__DENALI_PI_170__PI_RESERVED50_WOSET 0U
+#define LPDDR4__PI_RESERVED50__REG DENALI_PI_170
+#define LPDDR4__PI_RESERVED50__FLD LPDDR4__DENALI_PI_170__PI_RESERVED50
+
+#define LPDDR4__DENALI_PI_171_READ_MASK 0x00FF0101U
+#define LPDDR4__DENALI_PI_171_WRITE_MASK 0x00FF0101U
+#define LPDDR4__DENALI_PI_171__PI_RESERVED51_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_171__PI_RESERVED51_SHIFT 0U
+#define LPDDR4__DENALI_PI_171__PI_RESERVED51_WIDTH 1U
+#define LPDDR4__DENALI_PI_171__PI_RESERVED51_WOCLR 0U
+#define LPDDR4__DENALI_PI_171__PI_RESERVED51_WOSET 0U
+#define LPDDR4__PI_RESERVED51__REG DENALI_PI_171
+#define LPDDR4__PI_RESERVED51__FLD LPDDR4__DENALI_PI_171__PI_RESERVED51
+
+#define LPDDR4__DENALI_PI_171__PI_RESERVED52_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_171__PI_RESERVED52_SHIFT 8U
+#define LPDDR4__DENALI_PI_171__PI_RESERVED52_WIDTH 1U
+#define LPDDR4__DENALI_PI_171__PI_RESERVED52_WOCLR 0U
+#define LPDDR4__DENALI_PI_171__PI_RESERVED52_WOSET 0U
+#define LPDDR4__PI_RESERVED52__REG DENALI_PI_171
+#define LPDDR4__PI_RESERVED52__FLD LPDDR4__DENALI_PI_171__PI_RESERVED52
+
+#define LPDDR4__DENALI_PI_171__PI_WRLVL_MAX_STROBE_PEND_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_171__PI_WRLVL_MAX_STROBE_PEND_SHIFT 16U
+#define LPDDR4__DENALI_PI_171__PI_WRLVL_MAX_STROBE_PEND_WIDTH 8U
+#define LPDDR4__PI_WRLVL_MAX_STROBE_PEND__REG DENALI_PI_171
+#define LPDDR4__PI_WRLVL_MAX_STROBE_PEND__FLD LPDDR4__DENALI_PI_171__PI_WRLVL_MAX_STROBE_PEND
+
+#define LPDDR4__DENALI_PI_172_READ_MASK 0x000001FFU
+#define LPDDR4__DENALI_PI_172_WRITE_MASK 0x000001FFU
+#define LPDDR4__DENALI_PI_172__PI_TREFBW_THR_MASK 0x000001FFU
+#define LPDDR4__DENALI_PI_172__PI_TREFBW_THR_SHIFT 0U
+#define LPDDR4__DENALI_PI_172__PI_TREFBW_THR_WIDTH 9U
+#define LPDDR4__PI_TREFBW_THR__REG DENALI_PI_172
+#define LPDDR4__PI_TREFBW_THR__FLD LPDDR4__DENALI_PI_172__PI_TREFBW_THR
+
+#define LPDDR4__DENALI_PI_173_READ_MASK 0x0000001FU
+#define LPDDR4__DENALI_PI_173_WRITE_MASK 0x0000001FU
+#define LPDDR4__DENALI_PI_173__PI_FREQ_CHANGE_REG_COPY_MASK 0x0000001FU
+#define LPDDR4__DENALI_PI_173__PI_FREQ_CHANGE_REG_COPY_SHIFT 0U
+#define LPDDR4__DENALI_PI_173__PI_FREQ_CHANGE_REG_COPY_WIDTH 5U
+#define LPDDR4__PI_FREQ_CHANGE_REG_COPY__REG DENALI_PI_173
+#define LPDDR4__PI_FREQ_CHANGE_REG_COPY__FLD LPDDR4__DENALI_PI_173__PI_FREQ_CHANGE_REG_COPY
+
+#define LPDDR4__DENALI_PI_174_READ_MASK 0x0F011F01U
+#define LPDDR4__DENALI_PI_174_WRITE_MASK 0x0F011F01U
+#define LPDDR4__DENALI_PI_174__PI_FREQ_SEL_FROM_REGIF_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_174__PI_FREQ_SEL_FROM_REGIF_SHIFT 0U
+#define LPDDR4__DENALI_PI_174__PI_FREQ_SEL_FROM_REGIF_WIDTH 1U
+#define LPDDR4__DENALI_PI_174__PI_FREQ_SEL_FROM_REGIF_WOCLR 0U
+#define LPDDR4__DENALI_PI_174__PI_FREQ_SEL_FROM_REGIF_WOSET 0U
+#define LPDDR4__PI_FREQ_SEL_FROM_REGIF__REG DENALI_PI_174
+#define LPDDR4__PI_FREQ_SEL_FROM_REGIF__FLD LPDDR4__DENALI_PI_174__PI_FREQ_SEL_FROM_REGIF
+
+#define LPDDR4__DENALI_PI_174__PI_RESERVED53_MASK 0x00001F00U
+#define LPDDR4__DENALI_PI_174__PI_RESERVED53_SHIFT 8U
+#define LPDDR4__DENALI_PI_174__PI_RESERVED53_WIDTH 5U
+#define LPDDR4__PI_RESERVED53__REG DENALI_PI_174
+#define LPDDR4__PI_RESERVED53__FLD LPDDR4__DENALI_PI_174__PI_RESERVED53
+
+#define LPDDR4__DENALI_PI_174__PI_PARALLEL_CALVL_EN_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_174__PI_PARALLEL_CALVL_EN_SHIFT 16U
+#define LPDDR4__DENALI_PI_174__PI_PARALLEL_CALVL_EN_WIDTH 1U
+#define LPDDR4__DENALI_PI_174__PI_PARALLEL_CALVL_EN_WOCLR 0U
+#define LPDDR4__DENALI_PI_174__PI_PARALLEL_CALVL_EN_WOSET 0U
+#define LPDDR4__PI_PARALLEL_CALVL_EN__REG DENALI_PI_174
+#define LPDDR4__PI_PARALLEL_CALVL_EN__FLD LPDDR4__DENALI_PI_174__PI_PARALLEL_CALVL_EN
+
+#define LPDDR4__DENALI_PI_174__PI_CATR_MASK 0x0F000000U
+#define LPDDR4__DENALI_PI_174__PI_CATR_SHIFT 24U
+#define LPDDR4__DENALI_PI_174__PI_CATR_WIDTH 4U
+#define LPDDR4__PI_CATR__REG DENALI_PI_174
+#define LPDDR4__PI_CATR__FLD LPDDR4__DENALI_PI_174__PI_CATR
+
+#define LPDDR4__DENALI_PI_175_READ_MASK 0x01010101U
+#define LPDDR4__DENALI_PI_175_WRITE_MASK 0x01010101U
+#define LPDDR4__DENALI_PI_175__PI_NO_CATR_READ_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_175__PI_NO_CATR_READ_SHIFT 0U
+#define LPDDR4__DENALI_PI_175__PI_NO_CATR_READ_WIDTH 1U
+#define LPDDR4__DENALI_PI_175__PI_NO_CATR_READ_WOCLR 0U
+#define LPDDR4__DENALI_PI_175__PI_NO_CATR_READ_WOSET 0U
+#define LPDDR4__PI_NO_CATR_READ__REG DENALI_PI_175
+#define LPDDR4__PI_NO_CATR_READ__FLD LPDDR4__DENALI_PI_175__PI_NO_CATR_READ
+
+#define LPDDR4__DENALI_PI_175__PI_MASK_INIT_COMPLETE_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_175__PI_MASK_INIT_COMPLETE_SHIFT 8U
+#define LPDDR4__DENALI_PI_175__PI_MASK_INIT_COMPLETE_WIDTH 1U
+#define LPDDR4__DENALI_PI_175__PI_MASK_INIT_COMPLETE_WOCLR 0U
+#define LPDDR4__DENALI_PI_175__PI_MASK_INIT_COMPLETE_WOSET 0U
+#define LPDDR4__PI_MASK_INIT_COMPLETE__REG DENALI_PI_175
+#define LPDDR4__PI_MASK_INIT_COMPLETE__FLD LPDDR4__DENALI_PI_175__PI_MASK_INIT_COMPLETE
+
+#define LPDDR4__DENALI_PI_175__PI_DISCONNECT_MC_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_175__PI_DISCONNECT_MC_SHIFT 16U
+#define LPDDR4__DENALI_PI_175__PI_DISCONNECT_MC_WIDTH 1U
+#define LPDDR4__DENALI_PI_175__PI_DISCONNECT_MC_WOCLR 0U
+#define LPDDR4__DENALI_PI_175__PI_DISCONNECT_MC_WOSET 0U
+#define LPDDR4__PI_DISCONNECT_MC__REG DENALI_PI_175
+#define LPDDR4__PI_DISCONNECT_MC__FLD LPDDR4__DENALI_PI_175__PI_DISCONNECT_MC
+
+#define LPDDR4__DENALI_PI_175__PI_DISABLE_PHYMSTR_REQ_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_175__PI_DISABLE_PHYMSTR_REQ_SHIFT 24U
+#define LPDDR4__DENALI_PI_175__PI_DISABLE_PHYMSTR_REQ_WIDTH 1U
+#define LPDDR4__DENALI_PI_175__PI_DISABLE_PHYMSTR_REQ_WOCLR 0U
+#define LPDDR4__DENALI_PI_175__PI_DISABLE_PHYMSTR_REQ_WOSET 0U
+#define LPDDR4__PI_DISABLE_PHYMSTR_REQ__REG DENALI_PI_175
+#define LPDDR4__PI_DISABLE_PHYMSTR_REQ__FLD LPDDR4__DENALI_PI_175__PI_DISABLE_PHYMSTR_REQ
+
+#define LPDDR4__DENALI_PI_176_READ_MASK 0xFFFF0701U
+#define LPDDR4__DENALI_PI_176_WRITE_MASK 0xFFFF0701U
+#define LPDDR4__DENALI_PI_176__PI_NOTCARE_MC_INIT_START_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_176__PI_NOTCARE_MC_INIT_START_SHIFT 0U
+#define LPDDR4__DENALI_PI_176__PI_NOTCARE_MC_INIT_START_WIDTH 1U
+#define LPDDR4__DENALI_PI_176__PI_NOTCARE_MC_INIT_START_WOCLR 0U
+#define LPDDR4__DENALI_PI_176__PI_NOTCARE_MC_INIT_START_WOSET 0U
+#define LPDDR4__PI_NOTCARE_MC_INIT_START__REG DENALI_PI_176
+#define LPDDR4__PI_NOTCARE_MC_INIT_START__FLD LPDDR4__DENALI_PI_176__PI_NOTCARE_MC_INIT_START
+
+#define LPDDR4__DENALI_PI_176__PI_PHYMSTR_REQ_ACK_LOOP_DELAY_MASK 0x00000700U
+#define LPDDR4__DENALI_PI_176__PI_PHYMSTR_REQ_ACK_LOOP_DELAY_SHIFT 8U
+#define LPDDR4__DENALI_PI_176__PI_PHYMSTR_REQ_ACK_LOOP_DELAY_WIDTH 3U
+#define LPDDR4__PI_PHYMSTR_REQ_ACK_LOOP_DELAY__REG DENALI_PI_176
+#define LPDDR4__PI_PHYMSTR_REQ_ACK_LOOP_DELAY__FLD LPDDR4__DENALI_PI_176__PI_PHYMSTR_REQ_ACK_LOOP_DELAY
+
+#define LPDDR4__DENALI_PI_176__PI_TVREF_F0_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_PI_176__PI_TVREF_F0_SHIFT 16U
+#define LPDDR4__DENALI_PI_176__PI_TVREF_F0_WIDTH 16U
+#define LPDDR4__PI_TVREF_F0__REG DENALI_PI_176
+#define LPDDR4__PI_TVREF_F0__FLD LPDDR4__DENALI_PI_176__PI_TVREF_F0
+
+#define LPDDR4__DENALI_PI_177_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_177_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_177__PI_TVREF_F1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PI_177__PI_TVREF_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_177__PI_TVREF_F1_WIDTH 16U
+#define LPDDR4__PI_TVREF_F1__REG DENALI_PI_177
+#define LPDDR4__PI_TVREF_F1__FLD LPDDR4__DENALI_PI_177__PI_TVREF_F1
+
+#define LPDDR4__DENALI_PI_177__PI_TVREF_F2_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_PI_177__PI_TVREF_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_177__PI_TVREF_F2_WIDTH 16U
+#define LPDDR4__PI_TVREF_F2__REG DENALI_PI_177
+#define LPDDR4__PI_TVREF_F2__FLD LPDDR4__DENALI_PI_177__PI_TVREF_F2
+
+#define LPDDR4__DENALI_PI_178_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_178_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_178__PI_TSDO_F0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_178__PI_TSDO_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_178__PI_TSDO_F0_WIDTH 8U
+#define LPDDR4__PI_TSDO_F0__REG DENALI_PI_178
+#define LPDDR4__PI_TSDO_F0__FLD LPDDR4__DENALI_PI_178__PI_TSDO_F0
+
+#define LPDDR4__DENALI_PI_178__PI_TSDO_F1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_178__PI_TSDO_F1_SHIFT 8U
+#define LPDDR4__DENALI_PI_178__PI_TSDO_F1_WIDTH 8U
+#define LPDDR4__PI_TSDO_F1__REG DENALI_PI_178
+#define LPDDR4__PI_TSDO_F1__FLD LPDDR4__DENALI_PI_178__PI_TSDO_F1
+
+#define LPDDR4__DENALI_PI_178__PI_TSDO_F2_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_178__PI_TSDO_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_178__PI_TSDO_F2_WIDTH 8U
+#define LPDDR4__PI_TSDO_F2__REG DENALI_PI_178
+#define LPDDR4__PI_TSDO_F2__FLD LPDDR4__DENALI_PI_178__PI_TSDO_F2
+
+#define LPDDR4__DENALI_PI_179_READ_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_179_WRITE_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_179__PI_TDELAY_RDWR_2_BUS_IDLE_F0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_179__PI_TDELAY_RDWR_2_BUS_IDLE_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_179__PI_TDELAY_RDWR_2_BUS_IDLE_F0_WIDTH 8U
+#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F0__REG DENALI_PI_179
+#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F0__FLD LPDDR4__DENALI_PI_179__PI_TDELAY_RDWR_2_BUS_IDLE_F0
+
+#define LPDDR4__DENALI_PI_180_READ_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_180_WRITE_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_180__PI_TDELAY_RDWR_2_BUS_IDLE_F1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_180__PI_TDELAY_RDWR_2_BUS_IDLE_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_180__PI_TDELAY_RDWR_2_BUS_IDLE_F1_WIDTH 8U
+#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F1__REG DENALI_PI_180
+#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F1__FLD LPDDR4__DENALI_PI_180__PI_TDELAY_RDWR_2_BUS_IDLE_F1
+
+#define LPDDR4__DENALI_PI_181_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PI_181_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PI_181__PI_TDELAY_RDWR_2_BUS_IDLE_F2_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_181__PI_TDELAY_RDWR_2_BUS_IDLE_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_181__PI_TDELAY_RDWR_2_BUS_IDLE_F2_WIDTH 8U
+#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F2__REG DENALI_PI_181
+#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F2__FLD LPDDR4__DENALI_PI_181__PI_TDELAY_RDWR_2_BUS_IDLE_F2
+
+#define LPDDR4__DENALI_PI_181__PI_ZQINIT_F0_MASK 0x000FFF00U
+#define LPDDR4__DENALI_PI_181__PI_ZQINIT_F0_SHIFT 8U
+#define LPDDR4__DENALI_PI_181__PI_ZQINIT_F0_WIDTH 12U
+#define LPDDR4__PI_ZQINIT_F0__REG DENALI_PI_181
+#define LPDDR4__PI_ZQINIT_F0__FLD LPDDR4__DENALI_PI_181__PI_ZQINIT_F0
+
+#define LPDDR4__DENALI_PI_182_READ_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_PI_182_WRITE_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_PI_182__PI_ZQINIT_F1_MASK 0x00000FFFU
+#define LPDDR4__DENALI_PI_182__PI_ZQINIT_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_182__PI_ZQINIT_F1_WIDTH 12U
+#define LPDDR4__PI_ZQINIT_F1__REG DENALI_PI_182
+#define LPDDR4__PI_ZQINIT_F1__FLD LPDDR4__DENALI_PI_182__PI_ZQINIT_F1
+
+#define LPDDR4__DENALI_PI_182__PI_ZQINIT_F2_MASK 0x0FFF0000U
+#define LPDDR4__DENALI_PI_182__PI_ZQINIT_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_182__PI_ZQINIT_F2_WIDTH 12U
+#define LPDDR4__PI_ZQINIT_F2__REG DENALI_PI_182
+#define LPDDR4__PI_ZQINIT_F2__FLD LPDDR4__DENALI_PI_182__PI_ZQINIT_F2
+
+#define LPDDR4__DENALI_PI_183_READ_MASK 0xFF0F3F7FU
+#define LPDDR4__DENALI_PI_183_WRITE_MASK 0xFF0F3F7FU
+#define LPDDR4__DENALI_PI_183__PI_WRLAT_F0_MASK 0x0000007FU
+#define LPDDR4__DENALI_PI_183__PI_WRLAT_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_183__PI_WRLAT_F0_WIDTH 7U
+#define LPDDR4__PI_WRLAT_F0__REG DENALI_PI_183
+#define LPDDR4__PI_WRLAT_F0__FLD LPDDR4__DENALI_PI_183__PI_WRLAT_F0
+
+#define LPDDR4__DENALI_PI_183__PI_ADDITIVE_LAT_F0_MASK 0x00003F00U
+#define LPDDR4__DENALI_PI_183__PI_ADDITIVE_LAT_F0_SHIFT 8U
+#define LPDDR4__DENALI_PI_183__PI_ADDITIVE_LAT_F0_WIDTH 6U
+#define LPDDR4__PI_ADDITIVE_LAT_F0__REG DENALI_PI_183
+#define LPDDR4__PI_ADDITIVE_LAT_F0__FLD LPDDR4__DENALI_PI_183__PI_ADDITIVE_LAT_F0
+
+#define LPDDR4__DENALI_PI_183__PI_CA_PARITY_LAT_F0_MASK 0x000F0000U
+#define LPDDR4__DENALI_PI_183__PI_CA_PARITY_LAT_F0_SHIFT 16U
+#define LPDDR4__DENALI_PI_183__PI_CA_PARITY_LAT_F0_WIDTH 4U
+#define LPDDR4__PI_CA_PARITY_LAT_F0__REG DENALI_PI_183
+#define LPDDR4__PI_CA_PARITY_LAT_F0__FLD LPDDR4__DENALI_PI_183__PI_CA_PARITY_LAT_F0
+
+#define LPDDR4__DENALI_PI_183__PI_TPARITY_ERROR_CMD_INHIBIT_F0_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_183__PI_TPARITY_ERROR_CMD_INHIBIT_F0_SHIFT 24U
+#define LPDDR4__DENALI_PI_183__PI_TPARITY_ERROR_CMD_INHIBIT_F0_WIDTH 8U
+#define LPDDR4__PI_TPARITY_ERROR_CMD_INHIBIT_F0__REG DENALI_PI_183
+#define LPDDR4__PI_TPARITY_ERROR_CMD_INHIBIT_F0__FLD LPDDR4__DENALI_PI_183__PI_TPARITY_ERROR_CMD_INHIBIT_F0
+
+#define LPDDR4__DENALI_PI_184_READ_MASK 0x0F3F7F7FU
+#define LPDDR4__DENALI_PI_184_WRITE_MASK 0x0F3F7F7FU
+#define LPDDR4__DENALI_PI_184__PI_CASLAT_LIN_F0_MASK 0x0000007FU
+#define LPDDR4__DENALI_PI_184__PI_CASLAT_LIN_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_184__PI_CASLAT_LIN_F0_WIDTH 7U
+#define LPDDR4__PI_CASLAT_LIN_F0__REG DENALI_PI_184
+#define LPDDR4__PI_CASLAT_LIN_F0__FLD LPDDR4__DENALI_PI_184__PI_CASLAT_LIN_F0
+
+#define LPDDR4__DENALI_PI_184__PI_WRLAT_F1_MASK 0x00007F00U
+#define LPDDR4__DENALI_PI_184__PI_WRLAT_F1_SHIFT 8U
+#define LPDDR4__DENALI_PI_184__PI_WRLAT_F1_WIDTH 7U
+#define LPDDR4__PI_WRLAT_F1__REG DENALI_PI_184
+#define LPDDR4__PI_WRLAT_F1__FLD LPDDR4__DENALI_PI_184__PI_WRLAT_F1
+
+#define LPDDR4__DENALI_PI_184__PI_ADDITIVE_LAT_F1_MASK 0x003F0000U
+#define LPDDR4__DENALI_PI_184__PI_ADDITIVE_LAT_F1_SHIFT 16U
+#define LPDDR4__DENALI_PI_184__PI_ADDITIVE_LAT_F1_WIDTH 6U
+#define LPDDR4__PI_ADDITIVE_LAT_F1__REG DENALI_PI_184
+#define LPDDR4__PI_ADDITIVE_LAT_F1__FLD LPDDR4__DENALI_PI_184__PI_ADDITIVE_LAT_F1
+
+#define LPDDR4__DENALI_PI_184__PI_CA_PARITY_LAT_F1_MASK 0x0F000000U
+#define LPDDR4__DENALI_PI_184__PI_CA_PARITY_LAT_F1_SHIFT 24U
+#define LPDDR4__DENALI_PI_184__PI_CA_PARITY_LAT_F1_WIDTH 4U
+#define LPDDR4__PI_CA_PARITY_LAT_F1__REG DENALI_PI_184
+#define LPDDR4__PI_CA_PARITY_LAT_F1__FLD LPDDR4__DENALI_PI_184__PI_CA_PARITY_LAT_F1
+
+#define LPDDR4__DENALI_PI_185_READ_MASK 0x3F7F7FFFU
+#define LPDDR4__DENALI_PI_185_WRITE_MASK 0x3F7F7FFFU
+#define LPDDR4__DENALI_PI_185__PI_TPARITY_ERROR_CMD_INHIBIT_F1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_185__PI_TPARITY_ERROR_CMD_INHIBIT_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_185__PI_TPARITY_ERROR_CMD_INHIBIT_F1_WIDTH 8U
+#define LPDDR4__PI_TPARITY_ERROR_CMD_INHIBIT_F1__REG DENALI_PI_185
+#define LPDDR4__PI_TPARITY_ERROR_CMD_INHIBIT_F1__FLD LPDDR4__DENALI_PI_185__PI_TPARITY_ERROR_CMD_INHIBIT_F1
+
+#define LPDDR4__DENALI_PI_185__PI_CASLAT_LIN_F1_MASK 0x00007F00U
+#define LPDDR4__DENALI_PI_185__PI_CASLAT_LIN_F1_SHIFT 8U
+#define LPDDR4__DENALI_PI_185__PI_CASLAT_LIN_F1_WIDTH 7U
+#define LPDDR4__PI_CASLAT_LIN_F1__REG DENALI_PI_185
+#define LPDDR4__PI_CASLAT_LIN_F1__FLD LPDDR4__DENALI_PI_185__PI_CASLAT_LIN_F1
+
+#define LPDDR4__DENALI_PI_185__PI_WRLAT_F2_MASK 0x007F0000U
+#define LPDDR4__DENALI_PI_185__PI_WRLAT_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_185__PI_WRLAT_F2_WIDTH 7U
+#define LPDDR4__PI_WRLAT_F2__REG DENALI_PI_185
+#define LPDDR4__PI_WRLAT_F2__FLD LPDDR4__DENALI_PI_185__PI_WRLAT_F2
+
+#define LPDDR4__DENALI_PI_185__PI_ADDITIVE_LAT_F2_MASK 0x3F000000U
+#define LPDDR4__DENALI_PI_185__PI_ADDITIVE_LAT_F2_SHIFT 24U
+#define LPDDR4__DENALI_PI_185__PI_ADDITIVE_LAT_F2_WIDTH 6U
+#define LPDDR4__PI_ADDITIVE_LAT_F2__REG DENALI_PI_185
+#define LPDDR4__PI_ADDITIVE_LAT_F2__FLD LPDDR4__DENALI_PI_185__PI_ADDITIVE_LAT_F2
+
+#define LPDDR4__DENALI_PI_186_READ_MASK 0x007FFF0FU
+#define LPDDR4__DENALI_PI_186_WRITE_MASK 0x007FFF0FU
+#define LPDDR4__DENALI_PI_186__PI_CA_PARITY_LAT_F2_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_186__PI_CA_PARITY_LAT_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_186__PI_CA_PARITY_LAT_F2_WIDTH 4U
+#define LPDDR4__PI_CA_PARITY_LAT_F2__REG DENALI_PI_186
+#define LPDDR4__PI_CA_PARITY_LAT_F2__FLD LPDDR4__DENALI_PI_186__PI_CA_PARITY_LAT_F2
+
+#define LPDDR4__DENALI_PI_186__PI_TPARITY_ERROR_CMD_INHIBIT_F2_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_186__PI_TPARITY_ERROR_CMD_INHIBIT_F2_SHIFT 8U
+#define LPDDR4__DENALI_PI_186__PI_TPARITY_ERROR_CMD_INHIBIT_F2_WIDTH 8U
+#define LPDDR4__PI_TPARITY_ERROR_CMD_INHIBIT_F2__REG DENALI_PI_186
+#define LPDDR4__PI_TPARITY_ERROR_CMD_INHIBIT_F2__FLD LPDDR4__DENALI_PI_186__PI_TPARITY_ERROR_CMD_INHIBIT_F2
+
+#define LPDDR4__DENALI_PI_186__PI_CASLAT_LIN_F2_MASK 0x007F0000U
+#define LPDDR4__DENALI_PI_186__PI_CASLAT_LIN_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_186__PI_CASLAT_LIN_F2_WIDTH 7U
+#define LPDDR4__PI_CASLAT_LIN_F2__REG DENALI_PI_186
+#define LPDDR4__PI_CASLAT_LIN_F2__FLD LPDDR4__DENALI_PI_186__PI_CASLAT_LIN_F2
+
+#define LPDDR4__DENALI_PI_187_READ_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_187_WRITE_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_187__PI_TRFC_F0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_187__PI_TRFC_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_187__PI_TRFC_F0_WIDTH 10U
+#define LPDDR4__PI_TRFC_F0__REG DENALI_PI_187
+#define LPDDR4__PI_TRFC_F0__FLD LPDDR4__DENALI_PI_187__PI_TRFC_F0
+
+#define LPDDR4__DENALI_PI_188_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PI_188_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PI_188__PI_TREF_F0_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PI_188__PI_TREF_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_188__PI_TREF_F0_WIDTH 20U
+#define LPDDR4__PI_TREF_F0__REG DENALI_PI_188
+#define LPDDR4__PI_TREF_F0__FLD LPDDR4__DENALI_PI_188__PI_TREF_F0
+
+#define LPDDR4__DENALI_PI_189_READ_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_189_WRITE_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_189__PI_TRFC_F1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_189__PI_TRFC_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_189__PI_TRFC_F1_WIDTH 10U
+#define LPDDR4__PI_TRFC_F1__REG DENALI_PI_189
+#define LPDDR4__PI_TRFC_F1__FLD LPDDR4__DENALI_PI_189__PI_TRFC_F1
+
+#define LPDDR4__DENALI_PI_190_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PI_190_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PI_190__PI_TREF_F1_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PI_190__PI_TREF_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_190__PI_TREF_F1_WIDTH 20U
+#define LPDDR4__PI_TREF_F1__REG DENALI_PI_190
+#define LPDDR4__PI_TREF_F1__FLD LPDDR4__DENALI_PI_190__PI_TREF_F1
+
+#define LPDDR4__DENALI_PI_191_READ_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_191_WRITE_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_191__PI_TRFC_F2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_191__PI_TRFC_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_191__PI_TRFC_F2_WIDTH 10U
+#define LPDDR4__PI_TRFC_F2__REG DENALI_PI_191
+#define LPDDR4__PI_TRFC_F2__FLD LPDDR4__DENALI_PI_191__PI_TRFC_F2
+
+#define LPDDR4__DENALI_PI_192_READ_MASK 0x0F0FFFFFU
+#define LPDDR4__DENALI_PI_192_WRITE_MASK 0x0F0FFFFFU
+#define LPDDR4__DENALI_PI_192__PI_TREF_F2_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PI_192__PI_TREF_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_192__PI_TREF_F2_WIDTH 20U
+#define LPDDR4__PI_TREF_F2__REG DENALI_PI_192
+#define LPDDR4__PI_TREF_F2__FLD LPDDR4__DENALI_PI_192__PI_TREF_F2
+
+#define LPDDR4__DENALI_PI_192__PI_TDFI_CTRL_DELAY_F0_MASK 0x0F000000U
+#define LPDDR4__DENALI_PI_192__PI_TDFI_CTRL_DELAY_F0_SHIFT 24U
+#define LPDDR4__DENALI_PI_192__PI_TDFI_CTRL_DELAY_F0_WIDTH 4U
+#define LPDDR4__PI_TDFI_CTRL_DELAY_F0__REG DENALI_PI_192
+#define LPDDR4__PI_TDFI_CTRL_DELAY_F0__FLD LPDDR4__DENALI_PI_192__PI_TDFI_CTRL_DELAY_F0
+
+#define LPDDR4__DENALI_PI_193_READ_MASK 0x03030F0FU
+#define LPDDR4__DENALI_PI_193_WRITE_MASK 0x03030F0FU
+#define LPDDR4__DENALI_PI_193__PI_TDFI_CTRL_DELAY_F1_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_193__PI_TDFI_CTRL_DELAY_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_193__PI_TDFI_CTRL_DELAY_F1_WIDTH 4U
+#define LPDDR4__PI_TDFI_CTRL_DELAY_F1__REG DENALI_PI_193
+#define LPDDR4__PI_TDFI_CTRL_DELAY_F1__FLD LPDDR4__DENALI_PI_193__PI_TDFI_CTRL_DELAY_F1
+
+#define LPDDR4__DENALI_PI_193__PI_TDFI_CTRL_DELAY_F2_MASK 0x00000F00U
+#define LPDDR4__DENALI_PI_193__PI_TDFI_CTRL_DELAY_F2_SHIFT 8U
+#define LPDDR4__DENALI_PI_193__PI_TDFI_CTRL_DELAY_F2_WIDTH 4U
+#define LPDDR4__PI_TDFI_CTRL_DELAY_F2__REG DENALI_PI_193
+#define LPDDR4__PI_TDFI_CTRL_DELAY_F2__FLD LPDDR4__DENALI_PI_193__PI_TDFI_CTRL_DELAY_F2
+
+#define LPDDR4__DENALI_PI_193__PI_WRLVL_EN_F0_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_193__PI_WRLVL_EN_F0_SHIFT 16U
+#define LPDDR4__DENALI_PI_193__PI_WRLVL_EN_F0_WIDTH 2U
+#define LPDDR4__PI_WRLVL_EN_F0__REG DENALI_PI_193
+#define LPDDR4__PI_WRLVL_EN_F0__FLD LPDDR4__DENALI_PI_193__PI_WRLVL_EN_F0
+
+#define LPDDR4__DENALI_PI_193__PI_WRLVL_EN_F1_MASK 0x03000000U
+#define LPDDR4__DENALI_PI_193__PI_WRLVL_EN_F1_SHIFT 24U
+#define LPDDR4__DENALI_PI_193__PI_WRLVL_EN_F1_WIDTH 2U
+#define LPDDR4__PI_WRLVL_EN_F1__REG DENALI_PI_193
+#define LPDDR4__PI_WRLVL_EN_F1__FLD LPDDR4__DENALI_PI_193__PI_WRLVL_EN_F1
+
+#define LPDDR4__DENALI_PI_194_READ_MASK 0x0003FF03U
+#define LPDDR4__DENALI_PI_194_WRITE_MASK 0x0003FF03U
+#define LPDDR4__DENALI_PI_194__PI_WRLVL_EN_F2_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_194__PI_WRLVL_EN_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_194__PI_WRLVL_EN_F2_WIDTH 2U
+#define LPDDR4__PI_WRLVL_EN_F2__REG DENALI_PI_194
+#define LPDDR4__PI_WRLVL_EN_F2__FLD LPDDR4__DENALI_PI_194__PI_WRLVL_EN_F2
+
+#define LPDDR4__DENALI_PI_194__PI_TDFI_WRLVL_WW_F0_MASK 0x0003FF00U
+#define LPDDR4__DENALI_PI_194__PI_TDFI_WRLVL_WW_F0_SHIFT 8U
+#define LPDDR4__DENALI_PI_194__PI_TDFI_WRLVL_WW_F0_WIDTH 10U
+#define LPDDR4__PI_TDFI_WRLVL_WW_F0__REG DENALI_PI_194
+#define LPDDR4__PI_TDFI_WRLVL_WW_F0__FLD LPDDR4__DENALI_PI_194__PI_TDFI_WRLVL_WW_F0
+
+#define LPDDR4__DENALI_PI_195_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PI_195_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PI_195__PI_TDFI_WRLVL_WW_F1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_195__PI_TDFI_WRLVL_WW_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_195__PI_TDFI_WRLVL_WW_F1_WIDTH 10U
+#define LPDDR4__PI_TDFI_WRLVL_WW_F1__REG DENALI_PI_195
+#define LPDDR4__PI_TDFI_WRLVL_WW_F1__FLD LPDDR4__DENALI_PI_195__PI_TDFI_WRLVL_WW_F1
+
+#define LPDDR4__DENALI_PI_195__PI_TDFI_WRLVL_WW_F2_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PI_195__PI_TDFI_WRLVL_WW_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_195__PI_TDFI_WRLVL_WW_F2_WIDTH 10U
+#define LPDDR4__PI_TDFI_WRLVL_WW_F2__REG DENALI_PI_195
+#define LPDDR4__PI_TDFI_WRLVL_WW_F2__FLD LPDDR4__DENALI_PI_195__PI_TDFI_WRLVL_WW_F2
+
+#define LPDDR4__DENALI_PI_196_READ_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PI_196_WRITE_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PI_196__PI_TODTL_2CMD_F0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_196__PI_TODTL_2CMD_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_196__PI_TODTL_2CMD_F0_WIDTH 8U
+#define LPDDR4__PI_TODTL_2CMD_F0__REG DENALI_PI_196
+#define LPDDR4__PI_TODTL_2CMD_F0__FLD LPDDR4__DENALI_PI_196__PI_TODTL_2CMD_F0
+
+#define LPDDR4__DENALI_PI_196__PI_ODT_EN_F0_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_196__PI_ODT_EN_F0_SHIFT 8U
+#define LPDDR4__DENALI_PI_196__PI_ODT_EN_F0_WIDTH 1U
+#define LPDDR4__DENALI_PI_196__PI_ODT_EN_F0_WOCLR 0U
+#define LPDDR4__DENALI_PI_196__PI_ODT_EN_F0_WOSET 0U
+#define LPDDR4__PI_ODT_EN_F0__REG DENALI_PI_196
+#define LPDDR4__PI_ODT_EN_F0__FLD LPDDR4__DENALI_PI_196__PI_ODT_EN_F0
+
+#define LPDDR4__DENALI_PI_196__PI_TODTL_2CMD_F1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_196__PI_TODTL_2CMD_F1_SHIFT 16U
+#define LPDDR4__DENALI_PI_196__PI_TODTL_2CMD_F1_WIDTH 8U
+#define LPDDR4__PI_TODTL_2CMD_F1__REG DENALI_PI_196
+#define LPDDR4__PI_TODTL_2CMD_F1__FLD LPDDR4__DENALI_PI_196__PI_TODTL_2CMD_F1
+
+#define LPDDR4__DENALI_PI_196__PI_ODT_EN_F1_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_196__PI_ODT_EN_F1_SHIFT 24U
+#define LPDDR4__DENALI_PI_196__PI_ODT_EN_F1_WIDTH 1U
+#define LPDDR4__DENALI_PI_196__PI_ODT_EN_F1_WOCLR 0U
+#define LPDDR4__DENALI_PI_196__PI_ODT_EN_F1_WOSET 0U
+#define LPDDR4__PI_ODT_EN_F1__REG DENALI_PI_196
+#define LPDDR4__PI_ODT_EN_F1__FLD LPDDR4__DENALI_PI_196__PI_ODT_EN_F1
+
+#define LPDDR4__DENALI_PI_197_READ_MASK 0x0F0F01FFU
+#define LPDDR4__DENALI_PI_197_WRITE_MASK 0x0F0F01FFU
+#define LPDDR4__DENALI_PI_197__PI_TODTL_2CMD_F2_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_197__PI_TODTL_2CMD_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_197__PI_TODTL_2CMD_F2_WIDTH 8U
+#define LPDDR4__PI_TODTL_2CMD_F2__REG DENALI_PI_197
+#define LPDDR4__PI_TODTL_2CMD_F2__FLD LPDDR4__DENALI_PI_197__PI_TODTL_2CMD_F2
+
+#define LPDDR4__DENALI_PI_197__PI_ODT_EN_F2_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_197__PI_ODT_EN_F2_SHIFT 8U
+#define LPDDR4__DENALI_PI_197__PI_ODT_EN_F2_WIDTH 1U
+#define LPDDR4__DENALI_PI_197__PI_ODT_EN_F2_WOCLR 0U
+#define LPDDR4__DENALI_PI_197__PI_ODT_EN_F2_WOSET 0U
+#define LPDDR4__PI_ODT_EN_F2__REG DENALI_PI_197
+#define LPDDR4__PI_ODT_EN_F2__FLD LPDDR4__DENALI_PI_197__PI_ODT_EN_F2
+
+#define LPDDR4__DENALI_PI_197__PI_ODTLON_F0_MASK 0x000F0000U
+#define LPDDR4__DENALI_PI_197__PI_ODTLON_F0_SHIFT 16U
+#define LPDDR4__DENALI_PI_197__PI_ODTLON_F0_WIDTH 4U
+#define LPDDR4__PI_ODTLON_F0__REG DENALI_PI_197
+#define LPDDR4__PI_ODTLON_F0__FLD LPDDR4__DENALI_PI_197__PI_ODTLON_F0
+
+#define LPDDR4__DENALI_PI_197__PI_TODTON_MIN_F0_MASK 0x0F000000U
+#define LPDDR4__DENALI_PI_197__PI_TODTON_MIN_F0_SHIFT 24U
+#define LPDDR4__DENALI_PI_197__PI_TODTON_MIN_F0_WIDTH 4U
+#define LPDDR4__PI_TODTON_MIN_F0__REG DENALI_PI_197
+#define LPDDR4__PI_TODTON_MIN_F0__FLD LPDDR4__DENALI_PI_197__PI_TODTON_MIN_F0
+
+#define LPDDR4__DENALI_PI_198_READ_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_198_WRITE_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_198__PI_ODTLON_F1_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_198__PI_ODTLON_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_198__PI_ODTLON_F1_WIDTH 4U
+#define LPDDR4__PI_ODTLON_F1__REG DENALI_PI_198
+#define LPDDR4__PI_ODTLON_F1__FLD LPDDR4__DENALI_PI_198__PI_ODTLON_F1
+
+#define LPDDR4__DENALI_PI_198__PI_TODTON_MIN_F1_MASK 0x00000F00U
+#define LPDDR4__DENALI_PI_198__PI_TODTON_MIN_F1_SHIFT 8U
+#define LPDDR4__DENALI_PI_198__PI_TODTON_MIN_F1_WIDTH 4U
+#define LPDDR4__PI_TODTON_MIN_F1__REG DENALI_PI_198
+#define LPDDR4__PI_TODTON_MIN_F1__FLD LPDDR4__DENALI_PI_198__PI_TODTON_MIN_F1
+
+#define LPDDR4__DENALI_PI_198__PI_ODTLON_F2_MASK 0x000F0000U
+#define LPDDR4__DENALI_PI_198__PI_ODTLON_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_198__PI_ODTLON_F2_WIDTH 4U
+#define LPDDR4__PI_ODTLON_F2__REG DENALI_PI_198
+#define LPDDR4__PI_ODTLON_F2__FLD LPDDR4__DENALI_PI_198__PI_ODTLON_F2
+
+#define LPDDR4__DENALI_PI_198__PI_TODTON_MIN_F2_MASK 0x0F000000U
+#define LPDDR4__DENALI_PI_198__PI_TODTON_MIN_F2_SHIFT 24U
+#define LPDDR4__DENALI_PI_198__PI_TODTON_MIN_F2_WIDTH 4U
+#define LPDDR4__PI_TODTON_MIN_F2__REG DENALI_PI_198
+#define LPDDR4__PI_TODTON_MIN_F2__FLD LPDDR4__DENALI_PI_198__PI_TODTON_MIN_F2
+
+#define LPDDR4__DENALI_PI_199_READ_MASK 0x3F3F3F3FU
+#define LPDDR4__DENALI_PI_199_WRITE_MASK 0x3F3F3F3FU
+#define LPDDR4__DENALI_PI_199__PI_WR_TO_ODTH_F0_MASK 0x0000003FU
+#define LPDDR4__DENALI_PI_199__PI_WR_TO_ODTH_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_199__PI_WR_TO_ODTH_F0_WIDTH 6U
+#define LPDDR4__PI_WR_TO_ODTH_F0__REG DENALI_PI_199
+#define LPDDR4__PI_WR_TO_ODTH_F0__FLD LPDDR4__DENALI_PI_199__PI_WR_TO_ODTH_F0
+
+#define LPDDR4__DENALI_PI_199__PI_WR_TO_ODTH_F1_MASK 0x00003F00U
+#define LPDDR4__DENALI_PI_199__PI_WR_TO_ODTH_F1_SHIFT 8U
+#define LPDDR4__DENALI_PI_199__PI_WR_TO_ODTH_F1_WIDTH 6U
+#define LPDDR4__PI_WR_TO_ODTH_F1__REG DENALI_PI_199
+#define LPDDR4__PI_WR_TO_ODTH_F1__FLD LPDDR4__DENALI_PI_199__PI_WR_TO_ODTH_F1
+
+#define LPDDR4__DENALI_PI_199__PI_WR_TO_ODTH_F2_MASK 0x003F0000U
+#define LPDDR4__DENALI_PI_199__PI_WR_TO_ODTH_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_199__PI_WR_TO_ODTH_F2_WIDTH 6U
+#define LPDDR4__PI_WR_TO_ODTH_F2__REG DENALI_PI_199
+#define LPDDR4__PI_WR_TO_ODTH_F2__FLD LPDDR4__DENALI_PI_199__PI_WR_TO_ODTH_F2
+
+#define LPDDR4__DENALI_PI_199__PI_RD_TO_ODTH_F0_MASK 0x3F000000U
+#define LPDDR4__DENALI_PI_199__PI_RD_TO_ODTH_F0_SHIFT 24U
+#define LPDDR4__DENALI_PI_199__PI_RD_TO_ODTH_F0_WIDTH 6U
+#define LPDDR4__PI_RD_TO_ODTH_F0__REG DENALI_PI_199
+#define LPDDR4__PI_RD_TO_ODTH_F0__FLD LPDDR4__DENALI_PI_199__PI_RD_TO_ODTH_F0
+
+#define LPDDR4__DENALI_PI_200_READ_MASK 0x03033F3FU
+#define LPDDR4__DENALI_PI_200_WRITE_MASK 0x03033F3FU
+#define LPDDR4__DENALI_PI_200__PI_RD_TO_ODTH_F1_MASK 0x0000003FU
+#define LPDDR4__DENALI_PI_200__PI_RD_TO_ODTH_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_200__PI_RD_TO_ODTH_F1_WIDTH 6U
+#define LPDDR4__PI_RD_TO_ODTH_F1__REG DENALI_PI_200
+#define LPDDR4__PI_RD_TO_ODTH_F1__FLD LPDDR4__DENALI_PI_200__PI_RD_TO_ODTH_F1
+
+#define LPDDR4__DENALI_PI_200__PI_RD_TO_ODTH_F2_MASK 0x00003F00U
+#define LPDDR4__DENALI_PI_200__PI_RD_TO_ODTH_F2_SHIFT 8U
+#define LPDDR4__DENALI_PI_200__PI_RD_TO_ODTH_F2_WIDTH 6U
+#define LPDDR4__PI_RD_TO_ODTH_F2__REG DENALI_PI_200
+#define LPDDR4__PI_RD_TO_ODTH_F2__FLD LPDDR4__DENALI_PI_200__PI_RD_TO_ODTH_F2
+
+#define LPDDR4__DENALI_PI_200__PI_RDLVL_EN_F0_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_200__PI_RDLVL_EN_F0_SHIFT 16U
+#define LPDDR4__DENALI_PI_200__PI_RDLVL_EN_F0_WIDTH 2U
+#define LPDDR4__PI_RDLVL_EN_F0__REG DENALI_PI_200
+#define LPDDR4__PI_RDLVL_EN_F0__FLD LPDDR4__DENALI_PI_200__PI_RDLVL_EN_F0
+
+#define LPDDR4__DENALI_PI_200__PI_RDLVL_GATE_EN_F0_MASK 0x03000000U
+#define LPDDR4__DENALI_PI_200__PI_RDLVL_GATE_EN_F0_SHIFT 24U
+#define LPDDR4__DENALI_PI_200__PI_RDLVL_GATE_EN_F0_WIDTH 2U
+#define LPDDR4__PI_RDLVL_GATE_EN_F0__REG DENALI_PI_200
+#define LPDDR4__PI_RDLVL_GATE_EN_F0__FLD LPDDR4__DENALI_PI_200__PI_RDLVL_GATE_EN_F0
+
+#define LPDDR4__DENALI_PI_201_READ_MASK 0x03030303U
+#define LPDDR4__DENALI_PI_201_WRITE_MASK 0x03030303U
+#define LPDDR4__DENALI_PI_201__PI_RDLVL_EN_F1_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_201__PI_RDLVL_EN_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_201__PI_RDLVL_EN_F1_WIDTH 2U
+#define LPDDR4__PI_RDLVL_EN_F1__REG DENALI_PI_201
+#define LPDDR4__PI_RDLVL_EN_F1__FLD LPDDR4__DENALI_PI_201__PI_RDLVL_EN_F1
+
+#define LPDDR4__DENALI_PI_201__PI_RDLVL_GATE_EN_F1_MASK 0x00000300U
+#define LPDDR4__DENALI_PI_201__PI_RDLVL_GATE_EN_F1_SHIFT 8U
+#define LPDDR4__DENALI_PI_201__PI_RDLVL_GATE_EN_F1_WIDTH 2U
+#define LPDDR4__PI_RDLVL_GATE_EN_F1__REG DENALI_PI_201
+#define LPDDR4__PI_RDLVL_GATE_EN_F1__FLD LPDDR4__DENALI_PI_201__PI_RDLVL_GATE_EN_F1
+
+#define LPDDR4__DENALI_PI_201__PI_RDLVL_EN_F2_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_201__PI_RDLVL_EN_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_201__PI_RDLVL_EN_F2_WIDTH 2U
+#define LPDDR4__PI_RDLVL_EN_F2__REG DENALI_PI_201
+#define LPDDR4__PI_RDLVL_EN_F2__FLD LPDDR4__DENALI_PI_201__PI_RDLVL_EN_F2
+
+#define LPDDR4__DENALI_PI_201__PI_RDLVL_GATE_EN_F2_MASK 0x03000000U
+#define LPDDR4__DENALI_PI_201__PI_RDLVL_GATE_EN_F2_SHIFT 24U
+#define LPDDR4__DENALI_PI_201__PI_RDLVL_GATE_EN_F2_WIDTH 2U
+#define LPDDR4__PI_RDLVL_GATE_EN_F2__REG DENALI_PI_201
+#define LPDDR4__PI_RDLVL_GATE_EN_F2__FLD LPDDR4__DENALI_PI_201__PI_RDLVL_GATE_EN_F2
+
+#define LPDDR4__DENALI_PI_202_READ_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_PI_202_WRITE_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_PI_202__PI_TWR_MPR_F0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_202__PI_TWR_MPR_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_202__PI_TWR_MPR_F0_WIDTH 8U
+#define LPDDR4__PI_TWR_MPR_F0__REG DENALI_PI_202
+#define LPDDR4__PI_TWR_MPR_F0__FLD LPDDR4__DENALI_PI_202__PI_TWR_MPR_F0
+
+#define LPDDR4__DENALI_PI_202__PI_TWR_MPR_F1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_202__PI_TWR_MPR_F1_SHIFT 8U
+#define LPDDR4__DENALI_PI_202__PI_TWR_MPR_F1_WIDTH 8U
+#define LPDDR4__PI_TWR_MPR_F1__REG DENALI_PI_202
+#define LPDDR4__PI_TWR_MPR_F1__FLD LPDDR4__DENALI_PI_202__PI_TWR_MPR_F1
+
+#define LPDDR4__DENALI_PI_202__PI_TWR_MPR_F2_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_202__PI_TWR_MPR_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_202__PI_TWR_MPR_F2_WIDTH 8U
+#define LPDDR4__PI_TWR_MPR_F2__REG DENALI_PI_202
+#define LPDDR4__PI_TWR_MPR_F2__FLD LPDDR4__DENALI_PI_202__PI_TWR_MPR_F2
+
+#define LPDDR4__DENALI_PI_202__PI_RDLVL_PAT0_EN_F0_MASK 0x03000000U
+#define LPDDR4__DENALI_PI_202__PI_RDLVL_PAT0_EN_F0_SHIFT 24U
+#define LPDDR4__DENALI_PI_202__PI_RDLVL_PAT0_EN_F0_WIDTH 2U
+#define LPDDR4__PI_RDLVL_PAT0_EN_F0__REG DENALI_PI_202
+#define LPDDR4__PI_RDLVL_PAT0_EN_F0__FLD LPDDR4__DENALI_PI_202__PI_RDLVL_PAT0_EN_F0
+
+#define LPDDR4__DENALI_PI_203_READ_MASK 0x03030303U
+#define LPDDR4__DENALI_PI_203_WRITE_MASK 0x03030303U
+#define LPDDR4__DENALI_PI_203__PI_RDLVL_RXCAL_EN_F0_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_203__PI_RDLVL_RXCAL_EN_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_203__PI_RDLVL_RXCAL_EN_F0_WIDTH 2U
+#define LPDDR4__PI_RDLVL_RXCAL_EN_F0__REG DENALI_PI_203
+#define LPDDR4__PI_RDLVL_RXCAL_EN_F0__FLD LPDDR4__DENALI_PI_203__PI_RDLVL_RXCAL_EN_F0
+
+#define LPDDR4__DENALI_PI_203__PI_RDLVL_DFE_EN_F0_MASK 0x00000300U
+#define LPDDR4__DENALI_PI_203__PI_RDLVL_DFE_EN_F0_SHIFT 8U
+#define LPDDR4__DENALI_PI_203__PI_RDLVL_DFE_EN_F0_WIDTH 2U
+#define LPDDR4__PI_RDLVL_DFE_EN_F0__REG DENALI_PI_203
+#define LPDDR4__PI_RDLVL_DFE_EN_F0__FLD LPDDR4__DENALI_PI_203__PI_RDLVL_DFE_EN_F0
+
+#define LPDDR4__DENALI_PI_203__PI_RDLVL_MULTI_EN_F0_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_203__PI_RDLVL_MULTI_EN_F0_SHIFT 16U
+#define LPDDR4__DENALI_PI_203__PI_RDLVL_MULTI_EN_F0_WIDTH 2U
+#define LPDDR4__PI_RDLVL_MULTI_EN_F0__REG DENALI_PI_203
+#define LPDDR4__PI_RDLVL_MULTI_EN_F0__FLD LPDDR4__DENALI_PI_203__PI_RDLVL_MULTI_EN_F0
+
+#define LPDDR4__DENALI_PI_203__PI_RDLVL_PAT0_EN_F1_MASK 0x03000000U
+#define LPDDR4__DENALI_PI_203__PI_RDLVL_PAT0_EN_F1_SHIFT 24U
+#define LPDDR4__DENALI_PI_203__PI_RDLVL_PAT0_EN_F1_WIDTH 2U
+#define LPDDR4__PI_RDLVL_PAT0_EN_F1__REG DENALI_PI_203
+#define LPDDR4__PI_RDLVL_PAT0_EN_F1__FLD LPDDR4__DENALI_PI_203__PI_RDLVL_PAT0_EN_F1
+
+#define LPDDR4__DENALI_PI_204_READ_MASK 0x03030303U
+#define LPDDR4__DENALI_PI_204_WRITE_MASK 0x03030303U
+#define LPDDR4__DENALI_PI_204__PI_RDLVL_RXCAL_EN_F1_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_204__PI_RDLVL_RXCAL_EN_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_204__PI_RDLVL_RXCAL_EN_F1_WIDTH 2U
+#define LPDDR4__PI_RDLVL_RXCAL_EN_F1__REG DENALI_PI_204
+#define LPDDR4__PI_RDLVL_RXCAL_EN_F1__FLD LPDDR4__DENALI_PI_204__PI_RDLVL_RXCAL_EN_F1
+
+#define LPDDR4__DENALI_PI_204__PI_RDLVL_DFE_EN_F1_MASK 0x00000300U
+#define LPDDR4__DENALI_PI_204__PI_RDLVL_DFE_EN_F1_SHIFT 8U
+#define LPDDR4__DENALI_PI_204__PI_RDLVL_DFE_EN_F1_WIDTH 2U
+#define LPDDR4__PI_RDLVL_DFE_EN_F1__REG DENALI_PI_204
+#define LPDDR4__PI_RDLVL_DFE_EN_F1__FLD LPDDR4__DENALI_PI_204__PI_RDLVL_DFE_EN_F1
+
+#define LPDDR4__DENALI_PI_204__PI_RDLVL_MULTI_EN_F1_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_204__PI_RDLVL_MULTI_EN_F1_SHIFT 16U
+#define LPDDR4__DENALI_PI_204__PI_RDLVL_MULTI_EN_F1_WIDTH 2U
+#define LPDDR4__PI_RDLVL_MULTI_EN_F1__REG DENALI_PI_204
+#define LPDDR4__PI_RDLVL_MULTI_EN_F1__FLD LPDDR4__DENALI_PI_204__PI_RDLVL_MULTI_EN_F1
+
+#define LPDDR4__DENALI_PI_204__PI_RDLVL_PAT0_EN_F2_MASK 0x03000000U
+#define LPDDR4__DENALI_PI_204__PI_RDLVL_PAT0_EN_F2_SHIFT 24U
+#define LPDDR4__DENALI_PI_204__PI_RDLVL_PAT0_EN_F2_WIDTH 2U
+#define LPDDR4__PI_RDLVL_PAT0_EN_F2__REG DENALI_PI_204
+#define LPDDR4__PI_RDLVL_PAT0_EN_F2__FLD LPDDR4__DENALI_PI_204__PI_RDLVL_PAT0_EN_F2
+
+#define LPDDR4__DENALI_PI_205_READ_MASK 0xFF030303U
+#define LPDDR4__DENALI_PI_205_WRITE_MASK 0xFF030303U
+#define LPDDR4__DENALI_PI_205__PI_RDLVL_RXCAL_EN_F2_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_205__PI_RDLVL_RXCAL_EN_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_205__PI_RDLVL_RXCAL_EN_F2_WIDTH 2U
+#define LPDDR4__PI_RDLVL_RXCAL_EN_F2__REG DENALI_PI_205
+#define LPDDR4__PI_RDLVL_RXCAL_EN_F2__FLD LPDDR4__DENALI_PI_205__PI_RDLVL_RXCAL_EN_F2
+
+#define LPDDR4__DENALI_PI_205__PI_RDLVL_DFE_EN_F2_MASK 0x00000300U
+#define LPDDR4__DENALI_PI_205__PI_RDLVL_DFE_EN_F2_SHIFT 8U
+#define LPDDR4__DENALI_PI_205__PI_RDLVL_DFE_EN_F2_WIDTH 2U
+#define LPDDR4__PI_RDLVL_DFE_EN_F2__REG DENALI_PI_205
+#define LPDDR4__PI_RDLVL_DFE_EN_F2__FLD LPDDR4__DENALI_PI_205__PI_RDLVL_DFE_EN_F2
+
+#define LPDDR4__DENALI_PI_205__PI_RDLVL_MULTI_EN_F2_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_205__PI_RDLVL_MULTI_EN_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_205__PI_RDLVL_MULTI_EN_F2_WIDTH 2U
+#define LPDDR4__PI_RDLVL_MULTI_EN_F2__REG DENALI_PI_205
+#define LPDDR4__PI_RDLVL_MULTI_EN_F2__FLD LPDDR4__DENALI_PI_205__PI_RDLVL_MULTI_EN_F2
+
+#define LPDDR4__DENALI_PI_205__PI_RDLAT_ADJ_F0_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_205__PI_RDLAT_ADJ_F0_SHIFT 24U
+#define LPDDR4__DENALI_PI_205__PI_RDLAT_ADJ_F0_WIDTH 8U
+#define LPDDR4__PI_RDLAT_ADJ_F0__REG DENALI_PI_205
+#define LPDDR4__PI_RDLAT_ADJ_F0__FLD LPDDR4__DENALI_PI_205__PI_RDLAT_ADJ_F0
+
+#define LPDDR4__DENALI_PI_206_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_206_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_206__PI_RDLAT_ADJ_F1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_206__PI_RDLAT_ADJ_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_206__PI_RDLAT_ADJ_F1_WIDTH 8U
+#define LPDDR4__PI_RDLAT_ADJ_F1__REG DENALI_PI_206
+#define LPDDR4__PI_RDLAT_ADJ_F1__FLD LPDDR4__DENALI_PI_206__PI_RDLAT_ADJ_F1
+
+#define LPDDR4__DENALI_PI_206__PI_RDLAT_ADJ_F2_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_206__PI_RDLAT_ADJ_F2_SHIFT 8U
+#define LPDDR4__DENALI_PI_206__PI_RDLAT_ADJ_F2_WIDTH 8U
+#define LPDDR4__PI_RDLAT_ADJ_F2__REG DENALI_PI_206
+#define LPDDR4__PI_RDLAT_ADJ_F2__FLD LPDDR4__DENALI_PI_206__PI_RDLAT_ADJ_F2
+
+#define LPDDR4__DENALI_PI_206__PI_WRLAT_ADJ_F0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_206__PI_WRLAT_ADJ_F0_SHIFT 16U
+#define LPDDR4__DENALI_PI_206__PI_WRLAT_ADJ_F0_WIDTH 8U
+#define LPDDR4__PI_WRLAT_ADJ_F0__REG DENALI_PI_206
+#define LPDDR4__PI_WRLAT_ADJ_F0__FLD LPDDR4__DENALI_PI_206__PI_WRLAT_ADJ_F0
+
+#define LPDDR4__DENALI_PI_206__PI_WRLAT_ADJ_F1_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_206__PI_WRLAT_ADJ_F1_SHIFT 24U
+#define LPDDR4__DENALI_PI_206__PI_WRLAT_ADJ_F1_WIDTH 8U
+#define LPDDR4__PI_WRLAT_ADJ_F1__REG DENALI_PI_206
+#define LPDDR4__PI_WRLAT_ADJ_F1__FLD LPDDR4__DENALI_PI_206__PI_WRLAT_ADJ_F1
+
+#define LPDDR4__DENALI_PI_207_READ_MASK 0x070707FFU
+#define LPDDR4__DENALI_PI_207_WRITE_MASK 0x070707FFU
+#define LPDDR4__DENALI_PI_207__PI_WRLAT_ADJ_F2_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_207__PI_WRLAT_ADJ_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_207__PI_WRLAT_ADJ_F2_WIDTH 8U
+#define LPDDR4__PI_WRLAT_ADJ_F2__REG DENALI_PI_207
+#define LPDDR4__PI_WRLAT_ADJ_F2__FLD LPDDR4__DENALI_PI_207__PI_WRLAT_ADJ_F2
+
+#define LPDDR4__DENALI_PI_207__PI_TDFI_PHY_WRDATA_F0_MASK 0x00000700U
+#define LPDDR4__DENALI_PI_207__PI_TDFI_PHY_WRDATA_F0_SHIFT 8U
+#define LPDDR4__DENALI_PI_207__PI_TDFI_PHY_WRDATA_F0_WIDTH 3U
+#define LPDDR4__PI_TDFI_PHY_WRDATA_F0__REG DENALI_PI_207
+#define LPDDR4__PI_TDFI_PHY_WRDATA_F0__FLD LPDDR4__DENALI_PI_207__PI_TDFI_PHY_WRDATA_F0
+
+#define LPDDR4__DENALI_PI_207__PI_TDFI_PHY_WRDATA_F1_MASK 0x00070000U
+#define LPDDR4__DENALI_PI_207__PI_TDFI_PHY_WRDATA_F1_SHIFT 16U
+#define LPDDR4__DENALI_PI_207__PI_TDFI_PHY_WRDATA_F1_WIDTH 3U
+#define LPDDR4__PI_TDFI_PHY_WRDATA_F1__REG DENALI_PI_207
+#define LPDDR4__PI_TDFI_PHY_WRDATA_F1__FLD LPDDR4__DENALI_PI_207__PI_TDFI_PHY_WRDATA_F1
+
+#define LPDDR4__DENALI_PI_207__PI_TDFI_PHY_WRDATA_F2_MASK 0x07000000U
+#define LPDDR4__DENALI_PI_207__PI_TDFI_PHY_WRDATA_F2_SHIFT 24U
+#define LPDDR4__DENALI_PI_207__PI_TDFI_PHY_WRDATA_F2_WIDTH 3U
+#define LPDDR4__PI_TDFI_PHY_WRDATA_F2__REG DENALI_PI_207
+#define LPDDR4__PI_TDFI_PHY_WRDATA_F2__FLD LPDDR4__DENALI_PI_207__PI_TDFI_PHY_WRDATA_F2
+
+#define LPDDR4__DENALI_PI_208_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PI_208_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PI_208__PI_TDFI_CALVL_CC_F0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_208__PI_TDFI_CALVL_CC_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_208__PI_TDFI_CALVL_CC_F0_WIDTH 10U
+#define LPDDR4__PI_TDFI_CALVL_CC_F0__REG DENALI_PI_208
+#define LPDDR4__PI_TDFI_CALVL_CC_F0__FLD LPDDR4__DENALI_PI_208__PI_TDFI_CALVL_CC_F0
+
+#define LPDDR4__DENALI_PI_208__PI_TDFI_CALVL_CAPTURE_F0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PI_208__PI_TDFI_CALVL_CAPTURE_F0_SHIFT 16U
+#define LPDDR4__DENALI_PI_208__PI_TDFI_CALVL_CAPTURE_F0_WIDTH 10U
+#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F0__REG DENALI_PI_208
+#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F0__FLD LPDDR4__DENALI_PI_208__PI_TDFI_CALVL_CAPTURE_F0
+
+#define LPDDR4__DENALI_PI_209_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PI_209_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PI_209__PI_TDFI_CALVL_CC_F1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_209__PI_TDFI_CALVL_CC_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_209__PI_TDFI_CALVL_CC_F1_WIDTH 10U
+#define LPDDR4__PI_TDFI_CALVL_CC_F1__REG DENALI_PI_209
+#define LPDDR4__PI_TDFI_CALVL_CC_F1__FLD LPDDR4__DENALI_PI_209__PI_TDFI_CALVL_CC_F1
+
+#define LPDDR4__DENALI_PI_209__PI_TDFI_CALVL_CAPTURE_F1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PI_209__PI_TDFI_CALVL_CAPTURE_F1_SHIFT 16U
+#define LPDDR4__DENALI_PI_209__PI_TDFI_CALVL_CAPTURE_F1_WIDTH 10U
+#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F1__REG DENALI_PI_209
+#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F1__FLD LPDDR4__DENALI_PI_209__PI_TDFI_CALVL_CAPTURE_F1
+
+#define LPDDR4__DENALI_PI_210_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PI_210_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PI_210__PI_TDFI_CALVL_CC_F2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_210__PI_TDFI_CALVL_CC_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_210__PI_TDFI_CALVL_CC_F2_WIDTH 10U
+#define LPDDR4__PI_TDFI_CALVL_CC_F2__REG DENALI_PI_210
+#define LPDDR4__PI_TDFI_CALVL_CC_F2__FLD LPDDR4__DENALI_PI_210__PI_TDFI_CALVL_CC_F2
+
+#define LPDDR4__DENALI_PI_210__PI_TDFI_CALVL_CAPTURE_F2_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PI_210__PI_TDFI_CALVL_CAPTURE_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_210__PI_TDFI_CALVL_CAPTURE_F2_WIDTH 10U
+#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F2__REG DENALI_PI_210
+#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F2__FLD LPDDR4__DENALI_PI_210__PI_TDFI_CALVL_CAPTURE_F2
+
+#define LPDDR4__DENALI_PI_211_READ_MASK 0x1F030303U
+#define LPDDR4__DENALI_PI_211_WRITE_MASK 0x1F030303U
+#define LPDDR4__DENALI_PI_211__PI_CALVL_EN_F0_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_211__PI_CALVL_EN_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_211__PI_CALVL_EN_F0_WIDTH 2U
+#define LPDDR4__PI_CALVL_EN_F0__REG DENALI_PI_211
+#define LPDDR4__PI_CALVL_EN_F0__FLD LPDDR4__DENALI_PI_211__PI_CALVL_EN_F0
+
+#define LPDDR4__DENALI_PI_211__PI_CALVL_EN_F1_MASK 0x00000300U
+#define LPDDR4__DENALI_PI_211__PI_CALVL_EN_F1_SHIFT 8U
+#define LPDDR4__DENALI_PI_211__PI_CALVL_EN_F1_WIDTH 2U
+#define LPDDR4__PI_CALVL_EN_F1__REG DENALI_PI_211
+#define LPDDR4__PI_CALVL_EN_F1__FLD LPDDR4__DENALI_PI_211__PI_CALVL_EN_F1
+
+#define LPDDR4__DENALI_PI_211__PI_CALVL_EN_F2_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_211__PI_CALVL_EN_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_211__PI_CALVL_EN_F2_WIDTH 2U
+#define LPDDR4__PI_CALVL_EN_F2__REG DENALI_PI_211
+#define LPDDR4__PI_CALVL_EN_F2__FLD LPDDR4__DENALI_PI_211__PI_CALVL_EN_F2
+
+#define LPDDR4__DENALI_PI_211__PI_TMRZ_F0_MASK 0x1F000000U
+#define LPDDR4__DENALI_PI_211__PI_TMRZ_F0_SHIFT 24U
+#define LPDDR4__DENALI_PI_211__PI_TMRZ_F0_WIDTH 5U
+#define LPDDR4__PI_TMRZ_F0__REG DENALI_PI_211
+#define LPDDR4__PI_TMRZ_F0__FLD LPDDR4__DENALI_PI_211__PI_TMRZ_F0
+
+#define LPDDR4__DENALI_PI_212_READ_MASK 0x001F3FFFU
+#define LPDDR4__DENALI_PI_212_WRITE_MASK 0x001F3FFFU
+#define LPDDR4__DENALI_PI_212__PI_TCAENT_F0_MASK 0x00003FFFU
+#define LPDDR4__DENALI_PI_212__PI_TCAENT_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_212__PI_TCAENT_F0_WIDTH 14U
+#define LPDDR4__PI_TCAENT_F0__REG DENALI_PI_212
+#define LPDDR4__PI_TCAENT_F0__FLD LPDDR4__DENALI_PI_212__PI_TCAENT_F0
+
+#define LPDDR4__DENALI_PI_212__PI_TMRZ_F1_MASK 0x001F0000U
+#define LPDDR4__DENALI_PI_212__PI_TMRZ_F1_SHIFT 16U
+#define LPDDR4__DENALI_PI_212__PI_TMRZ_F1_WIDTH 5U
+#define LPDDR4__PI_TMRZ_F1__REG DENALI_PI_212
+#define LPDDR4__PI_TMRZ_F1__FLD LPDDR4__DENALI_PI_212__PI_TMRZ_F1
+
+#define LPDDR4__DENALI_PI_213_READ_MASK 0x001F3FFFU
+#define LPDDR4__DENALI_PI_213_WRITE_MASK 0x001F3FFFU
+#define LPDDR4__DENALI_PI_213__PI_TCAENT_F1_MASK 0x00003FFFU
+#define LPDDR4__DENALI_PI_213__PI_TCAENT_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_213__PI_TCAENT_F1_WIDTH 14U
+#define LPDDR4__PI_TCAENT_F1__REG DENALI_PI_213
+#define LPDDR4__PI_TCAENT_F1__FLD LPDDR4__DENALI_PI_213__PI_TCAENT_F1
+
+#define LPDDR4__DENALI_PI_213__PI_TMRZ_F2_MASK 0x001F0000U
+#define LPDDR4__DENALI_PI_213__PI_TMRZ_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_213__PI_TMRZ_F2_WIDTH 5U
+#define LPDDR4__PI_TMRZ_F2__REG DENALI_PI_213
+#define LPDDR4__PI_TMRZ_F2__FLD LPDDR4__DENALI_PI_213__PI_TMRZ_F2
+
+#define LPDDR4__DENALI_PI_214_READ_MASK 0x1F1F3FFFU
+#define LPDDR4__DENALI_PI_214_WRITE_MASK 0x1F1F3FFFU
+#define LPDDR4__DENALI_PI_214__PI_TCAENT_F2_MASK 0x00003FFFU
+#define LPDDR4__DENALI_PI_214__PI_TCAENT_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_214__PI_TCAENT_F2_WIDTH 14U
+#define LPDDR4__PI_TCAENT_F2__REG DENALI_PI_214
+#define LPDDR4__PI_TCAENT_F2__FLD LPDDR4__DENALI_PI_214__PI_TCAENT_F2
+
+#define LPDDR4__DENALI_PI_214__PI_TDFI_CACSCA_F0_MASK 0x001F0000U
+#define LPDDR4__DENALI_PI_214__PI_TDFI_CACSCA_F0_SHIFT 16U
+#define LPDDR4__DENALI_PI_214__PI_TDFI_CACSCA_F0_WIDTH 5U
+#define LPDDR4__PI_TDFI_CACSCA_F0__REG DENALI_PI_214
+#define LPDDR4__PI_TDFI_CACSCA_F0__FLD LPDDR4__DENALI_PI_214__PI_TDFI_CACSCA_F0
+
+#define LPDDR4__DENALI_PI_214__PI_TDFI_CASEL_F0_MASK 0x1F000000U
+#define LPDDR4__DENALI_PI_214__PI_TDFI_CASEL_F0_SHIFT 24U
+#define LPDDR4__DENALI_PI_214__PI_TDFI_CASEL_F0_WIDTH 5U
+#define LPDDR4__PI_TDFI_CASEL_F0__REG DENALI_PI_214
+#define LPDDR4__PI_TDFI_CASEL_F0__FLD LPDDR4__DENALI_PI_214__PI_TDFI_CASEL_F0
+
+#define LPDDR4__DENALI_PI_215_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PI_215_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PI_215__PI_TVREF_SHORT_F0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_215__PI_TVREF_SHORT_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_215__PI_TVREF_SHORT_F0_WIDTH 10U
+#define LPDDR4__PI_TVREF_SHORT_F0__REG DENALI_PI_215
+#define LPDDR4__PI_TVREF_SHORT_F0__FLD LPDDR4__DENALI_PI_215__PI_TVREF_SHORT_F0
+
+#define LPDDR4__DENALI_PI_215__PI_TVREF_LONG_F0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PI_215__PI_TVREF_LONG_F0_SHIFT 16U
+#define LPDDR4__DENALI_PI_215__PI_TVREF_LONG_F0_WIDTH 10U
+#define LPDDR4__PI_TVREF_LONG_F0__REG DENALI_PI_215
+#define LPDDR4__PI_TVREF_LONG_F0__FLD LPDDR4__DENALI_PI_215__PI_TVREF_LONG_F0
+
+#define LPDDR4__DENALI_PI_216_READ_MASK 0x03FF1F1FU
+#define LPDDR4__DENALI_PI_216_WRITE_MASK 0x03FF1F1FU
+#define LPDDR4__DENALI_PI_216__PI_TDFI_CACSCA_F1_MASK 0x0000001FU
+#define LPDDR4__DENALI_PI_216__PI_TDFI_CACSCA_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_216__PI_TDFI_CACSCA_F1_WIDTH 5U
+#define LPDDR4__PI_TDFI_CACSCA_F1__REG DENALI_PI_216
+#define LPDDR4__PI_TDFI_CACSCA_F1__FLD LPDDR4__DENALI_PI_216__PI_TDFI_CACSCA_F1
+
+#define LPDDR4__DENALI_PI_216__PI_TDFI_CASEL_F1_MASK 0x00001F00U
+#define LPDDR4__DENALI_PI_216__PI_TDFI_CASEL_F1_SHIFT 8U
+#define LPDDR4__DENALI_PI_216__PI_TDFI_CASEL_F1_WIDTH 5U
+#define LPDDR4__PI_TDFI_CASEL_F1__REG DENALI_PI_216
+#define LPDDR4__PI_TDFI_CASEL_F1__FLD LPDDR4__DENALI_PI_216__PI_TDFI_CASEL_F1
+
+#define LPDDR4__DENALI_PI_216__PI_TVREF_SHORT_F1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PI_216__PI_TVREF_SHORT_F1_SHIFT 16U
+#define LPDDR4__DENALI_PI_216__PI_TVREF_SHORT_F1_WIDTH 10U
+#define LPDDR4__PI_TVREF_SHORT_F1__REG DENALI_PI_216
+#define LPDDR4__PI_TVREF_SHORT_F1__FLD LPDDR4__DENALI_PI_216__PI_TVREF_SHORT_F1
+
+#define LPDDR4__DENALI_PI_217_READ_MASK 0x1F1F03FFU
+#define LPDDR4__DENALI_PI_217_WRITE_MASK 0x1F1F03FFU
+#define LPDDR4__DENALI_PI_217__PI_TVREF_LONG_F1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_217__PI_TVREF_LONG_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_217__PI_TVREF_LONG_F1_WIDTH 10U
+#define LPDDR4__PI_TVREF_LONG_F1__REG DENALI_PI_217
+#define LPDDR4__PI_TVREF_LONG_F1__FLD LPDDR4__DENALI_PI_217__PI_TVREF_LONG_F1
+
+#define LPDDR4__DENALI_PI_217__PI_TDFI_CACSCA_F2_MASK 0x001F0000U
+#define LPDDR4__DENALI_PI_217__PI_TDFI_CACSCA_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_217__PI_TDFI_CACSCA_F2_WIDTH 5U
+#define LPDDR4__PI_TDFI_CACSCA_F2__REG DENALI_PI_217
+#define LPDDR4__PI_TDFI_CACSCA_F2__FLD LPDDR4__DENALI_PI_217__PI_TDFI_CACSCA_F2
+
+#define LPDDR4__DENALI_PI_217__PI_TDFI_CASEL_F2_MASK 0x1F000000U
+#define LPDDR4__DENALI_PI_217__PI_TDFI_CASEL_F2_SHIFT 24U
+#define LPDDR4__DENALI_PI_217__PI_TDFI_CASEL_F2_WIDTH 5U
+#define LPDDR4__PI_TDFI_CASEL_F2__REG DENALI_PI_217
+#define LPDDR4__PI_TDFI_CASEL_F2__FLD LPDDR4__DENALI_PI_217__PI_TDFI_CASEL_F2
+
+#define LPDDR4__DENALI_PI_218_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PI_218_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PI_218__PI_TVREF_SHORT_F2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_218__PI_TVREF_SHORT_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_218__PI_TVREF_SHORT_F2_WIDTH 10U
+#define LPDDR4__PI_TVREF_SHORT_F2__REG DENALI_PI_218
+#define LPDDR4__PI_TVREF_SHORT_F2__FLD LPDDR4__DENALI_PI_218__PI_TVREF_SHORT_F2
+
+#define LPDDR4__DENALI_PI_218__PI_TVREF_LONG_F2_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PI_218__PI_TVREF_LONG_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_218__PI_TVREF_LONG_F2_WIDTH 10U
+#define LPDDR4__PI_TVREF_LONG_F2__REG DENALI_PI_218
+#define LPDDR4__PI_TVREF_LONG_F2__FLD LPDDR4__DENALI_PI_218__PI_TVREF_LONG_F2
+
+#define LPDDR4__DENALI_PI_219_READ_MASK 0x7F7F7F7FU
+#define LPDDR4__DENALI_PI_219_WRITE_MASK 0x7F7F7F7FU
+#define LPDDR4__DENALI_PI_219__PI_CALVL_VREF_INITIAL_START_POINT_F0_MASK 0x0000007FU
+#define LPDDR4__DENALI_PI_219__PI_CALVL_VREF_INITIAL_START_POINT_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_219__PI_CALVL_VREF_INITIAL_START_POINT_F0_WIDTH 7U
+#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F0__REG DENALI_PI_219
+#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F0__FLD LPDDR4__DENALI_PI_219__PI_CALVL_VREF_INITIAL_START_POINT_F0
+
+#define LPDDR4__DENALI_PI_219__PI_CALVL_VREF_INITIAL_STOP_POINT_F0_MASK 0x00007F00U
+#define LPDDR4__DENALI_PI_219__PI_CALVL_VREF_INITIAL_STOP_POINT_F0_SHIFT 8U
+#define LPDDR4__DENALI_PI_219__PI_CALVL_VREF_INITIAL_STOP_POINT_F0_WIDTH 7U
+#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F0__REG DENALI_PI_219
+#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F0__FLD LPDDR4__DENALI_PI_219__PI_CALVL_VREF_INITIAL_STOP_POINT_F0
+
+#define LPDDR4__DENALI_PI_219__PI_CALVL_VREF_INITIAL_START_POINT_F1_MASK 0x007F0000U
+#define LPDDR4__DENALI_PI_219__PI_CALVL_VREF_INITIAL_START_POINT_F1_SHIFT 16U
+#define LPDDR4__DENALI_PI_219__PI_CALVL_VREF_INITIAL_START_POINT_F1_WIDTH 7U
+#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F1__REG DENALI_PI_219
+#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F1__FLD LPDDR4__DENALI_PI_219__PI_CALVL_VREF_INITIAL_START_POINT_F1
+
+#define LPDDR4__DENALI_PI_219__PI_CALVL_VREF_INITIAL_STOP_POINT_F1_MASK 0x7F000000U
+#define LPDDR4__DENALI_PI_219__PI_CALVL_VREF_INITIAL_STOP_POINT_F1_SHIFT 24U
+#define LPDDR4__DENALI_PI_219__PI_CALVL_VREF_INITIAL_STOP_POINT_F1_WIDTH 7U
+#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F1__REG DENALI_PI_219
+#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F1__FLD LPDDR4__DENALI_PI_219__PI_CALVL_VREF_INITIAL_STOP_POINT_F1
+
+#define LPDDR4__DENALI_PI_220_READ_MASK 0x0F0F7F7FU
+#define LPDDR4__DENALI_PI_220_WRITE_MASK 0x0F0F7F7FU
+#define LPDDR4__DENALI_PI_220__PI_CALVL_VREF_INITIAL_START_POINT_F2_MASK 0x0000007FU
+#define LPDDR4__DENALI_PI_220__PI_CALVL_VREF_INITIAL_START_POINT_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_220__PI_CALVL_VREF_INITIAL_START_POINT_F2_WIDTH 7U
+#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F2__REG DENALI_PI_220
+#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F2__FLD LPDDR4__DENALI_PI_220__PI_CALVL_VREF_INITIAL_START_POINT_F2
+
+#define LPDDR4__DENALI_PI_220__PI_CALVL_VREF_INITIAL_STOP_POINT_F2_MASK 0x00007F00U
+#define LPDDR4__DENALI_PI_220__PI_CALVL_VREF_INITIAL_STOP_POINT_F2_SHIFT 8U
+#define LPDDR4__DENALI_PI_220__PI_CALVL_VREF_INITIAL_STOP_POINT_F2_WIDTH 7U
+#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F2__REG DENALI_PI_220
+#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F2__FLD LPDDR4__DENALI_PI_220__PI_CALVL_VREF_INITIAL_STOP_POINT_F2
+
+#define LPDDR4__DENALI_PI_220__PI_CALVL_VREF_DELTA_F0_MASK 0x000F0000U
+#define LPDDR4__DENALI_PI_220__PI_CALVL_VREF_DELTA_F0_SHIFT 16U
+#define LPDDR4__DENALI_PI_220__PI_CALVL_VREF_DELTA_F0_WIDTH 4U
+#define LPDDR4__PI_CALVL_VREF_DELTA_F0__REG DENALI_PI_220
+#define LPDDR4__PI_CALVL_VREF_DELTA_F0__FLD LPDDR4__DENALI_PI_220__PI_CALVL_VREF_DELTA_F0
+
+#define LPDDR4__DENALI_PI_220__PI_CALVL_VREF_DELTA_F1_MASK 0x0F000000U
+#define LPDDR4__DENALI_PI_220__PI_CALVL_VREF_DELTA_F1_SHIFT 24U
+#define LPDDR4__DENALI_PI_220__PI_CALVL_VREF_DELTA_F1_WIDTH 4U
+#define LPDDR4__PI_CALVL_VREF_DELTA_F1__REG DENALI_PI_220
+#define LPDDR4__PI_CALVL_VREF_DELTA_F1__FLD LPDDR4__DENALI_PI_220__PI_CALVL_VREF_DELTA_F1
+
+#define LPDDR4__DENALI_PI_221_READ_MASK 0xFF1F0F0FU
+#define LPDDR4__DENALI_PI_221_WRITE_MASK 0xFF1F0F0FU
+#define LPDDR4__DENALI_PI_221__PI_CALVL_VREF_DELTA_F2_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_221__PI_CALVL_VREF_DELTA_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_221__PI_CALVL_VREF_DELTA_F2_WIDTH 4U
+#define LPDDR4__PI_CALVL_VREF_DELTA_F2__REG DENALI_PI_221
+#define LPDDR4__PI_CALVL_VREF_DELTA_F2__FLD LPDDR4__DENALI_PI_221__PI_CALVL_VREF_DELTA_F2
+
+#define LPDDR4__DENALI_PI_221__PI_TDFI_CALVL_STROBE_F0_MASK 0x00000F00U
+#define LPDDR4__DENALI_PI_221__PI_TDFI_CALVL_STROBE_F0_SHIFT 8U
+#define LPDDR4__DENALI_PI_221__PI_TDFI_CALVL_STROBE_F0_WIDTH 4U
+#define LPDDR4__PI_TDFI_CALVL_STROBE_F0__REG DENALI_PI_221
+#define LPDDR4__PI_TDFI_CALVL_STROBE_F0__FLD LPDDR4__DENALI_PI_221__PI_TDFI_CALVL_STROBE_F0
+
+#define LPDDR4__DENALI_PI_221__PI_TXP_F0_MASK 0x001F0000U
+#define LPDDR4__DENALI_PI_221__PI_TXP_F0_SHIFT 16U
+#define LPDDR4__DENALI_PI_221__PI_TXP_F0_WIDTH 5U
+#define LPDDR4__PI_TXP_F0__REG DENALI_PI_221
+#define LPDDR4__PI_TXP_F0__FLD LPDDR4__DENALI_PI_221__PI_TXP_F0
+
+#define LPDDR4__DENALI_PI_221__PI_TMRWCKEL_F0_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_221__PI_TMRWCKEL_F0_SHIFT 24U
+#define LPDDR4__DENALI_PI_221__PI_TMRWCKEL_F0_WIDTH 8U
+#define LPDDR4__PI_TMRWCKEL_F0__REG DENALI_PI_221
+#define LPDDR4__PI_TMRWCKEL_F0__FLD LPDDR4__DENALI_PI_221__PI_TMRWCKEL_F0
+
+#define LPDDR4__DENALI_PI_222_READ_MASK 0xFF1F0F1FU
+#define LPDDR4__DENALI_PI_222_WRITE_MASK 0xFF1F0F1FU
+#define LPDDR4__DENALI_PI_222__PI_TCKELCK_F0_MASK 0x0000001FU
+#define LPDDR4__DENALI_PI_222__PI_TCKELCK_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_222__PI_TCKELCK_F0_WIDTH 5U
+#define LPDDR4__PI_TCKELCK_F0__REG DENALI_PI_222
+#define LPDDR4__PI_TCKELCK_F0__FLD LPDDR4__DENALI_PI_222__PI_TCKELCK_F0
+
+#define LPDDR4__DENALI_PI_222__PI_TDFI_CALVL_STROBE_F1_MASK 0x00000F00U
+#define LPDDR4__DENALI_PI_222__PI_TDFI_CALVL_STROBE_F1_SHIFT 8U
+#define LPDDR4__DENALI_PI_222__PI_TDFI_CALVL_STROBE_F1_WIDTH 4U
+#define LPDDR4__PI_TDFI_CALVL_STROBE_F1__REG DENALI_PI_222
+#define LPDDR4__PI_TDFI_CALVL_STROBE_F1__FLD LPDDR4__DENALI_PI_222__PI_TDFI_CALVL_STROBE_F1
+
+#define LPDDR4__DENALI_PI_222__PI_TXP_F1_MASK 0x001F0000U
+#define LPDDR4__DENALI_PI_222__PI_TXP_F1_SHIFT 16U
+#define LPDDR4__DENALI_PI_222__PI_TXP_F1_WIDTH 5U
+#define LPDDR4__PI_TXP_F1__REG DENALI_PI_222
+#define LPDDR4__PI_TXP_F1__FLD LPDDR4__DENALI_PI_222__PI_TXP_F1
+
+#define LPDDR4__DENALI_PI_222__PI_TMRWCKEL_F1_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_222__PI_TMRWCKEL_F1_SHIFT 24U
+#define LPDDR4__DENALI_PI_222__PI_TMRWCKEL_F1_WIDTH 8U
+#define LPDDR4__PI_TMRWCKEL_F1__REG DENALI_PI_222
+#define LPDDR4__PI_TMRWCKEL_F1__FLD LPDDR4__DENALI_PI_222__PI_TMRWCKEL_F1
+
+#define LPDDR4__DENALI_PI_223_READ_MASK 0xFF1F0F1FU
+#define LPDDR4__DENALI_PI_223_WRITE_MASK 0xFF1F0F1FU
+#define LPDDR4__DENALI_PI_223__PI_TCKELCK_F1_MASK 0x0000001FU
+#define LPDDR4__DENALI_PI_223__PI_TCKELCK_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_223__PI_TCKELCK_F1_WIDTH 5U
+#define LPDDR4__PI_TCKELCK_F1__REG DENALI_PI_223
+#define LPDDR4__PI_TCKELCK_F1__FLD LPDDR4__DENALI_PI_223__PI_TCKELCK_F1
+
+#define LPDDR4__DENALI_PI_223__PI_TDFI_CALVL_STROBE_F2_MASK 0x00000F00U
+#define LPDDR4__DENALI_PI_223__PI_TDFI_CALVL_STROBE_F2_SHIFT 8U
+#define LPDDR4__DENALI_PI_223__PI_TDFI_CALVL_STROBE_F2_WIDTH 4U
+#define LPDDR4__PI_TDFI_CALVL_STROBE_F2__REG DENALI_PI_223
+#define LPDDR4__PI_TDFI_CALVL_STROBE_F2__FLD LPDDR4__DENALI_PI_223__PI_TDFI_CALVL_STROBE_F2
+
+#define LPDDR4__DENALI_PI_223__PI_TXP_F2_MASK 0x001F0000U
+#define LPDDR4__DENALI_PI_223__PI_TXP_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_223__PI_TXP_F2_WIDTH 5U
+#define LPDDR4__PI_TXP_F2__REG DENALI_PI_223
+#define LPDDR4__PI_TXP_F2__FLD LPDDR4__DENALI_PI_223__PI_TXP_F2
+
+#define LPDDR4__DENALI_PI_223__PI_TMRWCKEL_F2_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_223__PI_TMRWCKEL_F2_SHIFT 24U
+#define LPDDR4__DENALI_PI_223__PI_TMRWCKEL_F2_WIDTH 8U
+#define LPDDR4__PI_TMRWCKEL_F2__REG DENALI_PI_223
+#define LPDDR4__PI_TMRWCKEL_F2__FLD LPDDR4__DENALI_PI_223__PI_TMRWCKEL_F2
+
+#define LPDDR4__DENALI_PI_224_READ_MASK 0xFFFFFF1FU
+#define LPDDR4__DENALI_PI_224_WRITE_MASK 0xFFFFFF1FU
+#define LPDDR4__DENALI_PI_224__PI_TCKELCK_F2_MASK 0x0000001FU
+#define LPDDR4__DENALI_PI_224__PI_TCKELCK_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_224__PI_TCKELCK_F2_WIDTH 5U
+#define LPDDR4__PI_TCKELCK_F2__REG DENALI_PI_224
+#define LPDDR4__PI_TCKELCK_F2__FLD LPDDR4__DENALI_PI_224__PI_TCKELCK_F2
+
+#define LPDDR4__DENALI_PI_224__PI_TDFI_INIT_START_F0_MASK 0xFFFFFF00U
+#define LPDDR4__DENALI_PI_224__PI_TDFI_INIT_START_F0_SHIFT 8U
+#define LPDDR4__DENALI_PI_224__PI_TDFI_INIT_START_F0_WIDTH 24U
+#define LPDDR4__PI_TDFI_INIT_START_F0__REG DENALI_PI_224
+#define LPDDR4__PI_TDFI_INIT_START_F0__FLD LPDDR4__DENALI_PI_224__PI_TDFI_INIT_START_F0
+
+#define LPDDR4__DENALI_PI_225_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_225_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_225__PI_TDFI_INIT_COMPLETE_F0_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_225__PI_TDFI_INIT_COMPLETE_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_225__PI_TDFI_INIT_COMPLETE_F0_WIDTH 24U
+#define LPDDR4__PI_TDFI_INIT_COMPLETE_F0__REG DENALI_PI_225
+#define LPDDR4__PI_TDFI_INIT_COMPLETE_F0__FLD LPDDR4__DENALI_PI_225__PI_TDFI_INIT_COMPLETE_F0
+
+#define LPDDR4__DENALI_PI_226_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_226_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_226__PI_TDFI_INIT_START_F1_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_226__PI_TDFI_INIT_START_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_226__PI_TDFI_INIT_START_F1_WIDTH 24U
+#define LPDDR4__PI_TDFI_INIT_START_F1__REG DENALI_PI_226
+#define LPDDR4__PI_TDFI_INIT_START_F1__FLD LPDDR4__DENALI_PI_226__PI_TDFI_INIT_START_F1
+
+#define LPDDR4__DENALI_PI_227_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_227_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_227__PI_TDFI_INIT_COMPLETE_F1_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_227__PI_TDFI_INIT_COMPLETE_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_227__PI_TDFI_INIT_COMPLETE_F1_WIDTH 24U
+#define LPDDR4__PI_TDFI_INIT_COMPLETE_F1__REG DENALI_PI_227
+#define LPDDR4__PI_TDFI_INIT_COMPLETE_F1__FLD LPDDR4__DENALI_PI_227__PI_TDFI_INIT_COMPLETE_F1
+
+#define LPDDR4__DENALI_PI_228_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_228_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_228__PI_TDFI_INIT_START_F2_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_228__PI_TDFI_INIT_START_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_228__PI_TDFI_INIT_START_F2_WIDTH 24U
+#define LPDDR4__PI_TDFI_INIT_START_F2__REG DENALI_PI_228
+#define LPDDR4__PI_TDFI_INIT_START_F2__FLD LPDDR4__DENALI_PI_228__PI_TDFI_INIT_START_F2
+
+#define LPDDR4__DENALI_PI_229_READ_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_229_WRITE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_229__PI_TDFI_INIT_COMPLETE_F2_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_229__PI_TDFI_INIT_COMPLETE_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_229__PI_TDFI_INIT_COMPLETE_F2_WIDTH 24U
+#define LPDDR4__PI_TDFI_INIT_COMPLETE_F2__REG DENALI_PI_229
+#define LPDDR4__PI_TDFI_INIT_COMPLETE_F2__FLD LPDDR4__DENALI_PI_229__PI_TDFI_INIT_COMPLETE_F2
+
+#define LPDDR4__DENALI_PI_229__PI_TCKEHDQS_F0_MASK 0x3F000000U
+#define LPDDR4__DENALI_PI_229__PI_TCKEHDQS_F0_SHIFT 24U
+#define LPDDR4__DENALI_PI_229__PI_TCKEHDQS_F0_WIDTH 6U
+#define LPDDR4__PI_TCKEHDQS_F0__REG DENALI_PI_229
+#define LPDDR4__PI_TCKEHDQS_F0__FLD LPDDR4__DENALI_PI_229__PI_TCKEHDQS_F0
+
+#define LPDDR4__DENALI_PI_230_READ_MASK 0x003F03FFU
+#define LPDDR4__DENALI_PI_230_WRITE_MASK 0x003F03FFU
+#define LPDDR4__DENALI_PI_230__PI_TFC_F0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_230__PI_TFC_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_230__PI_TFC_F0_WIDTH 10U
+#define LPDDR4__PI_TFC_F0__REG DENALI_PI_230
+#define LPDDR4__PI_TFC_F0__FLD LPDDR4__DENALI_PI_230__PI_TFC_F0
+
+#define LPDDR4__DENALI_PI_230__PI_TCKEHDQS_F1_MASK 0x003F0000U
+#define LPDDR4__DENALI_PI_230__PI_TCKEHDQS_F1_SHIFT 16U
+#define LPDDR4__DENALI_PI_230__PI_TCKEHDQS_F1_WIDTH 6U
+#define LPDDR4__PI_TCKEHDQS_F1__REG DENALI_PI_230
+#define LPDDR4__PI_TCKEHDQS_F1__FLD LPDDR4__DENALI_PI_230__PI_TCKEHDQS_F1
+
+#define LPDDR4__DENALI_PI_231_READ_MASK 0x003F03FFU
+#define LPDDR4__DENALI_PI_231_WRITE_MASK 0x003F03FFU
+#define LPDDR4__DENALI_PI_231__PI_TFC_F1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_231__PI_TFC_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_231__PI_TFC_F1_WIDTH 10U
+#define LPDDR4__PI_TFC_F1__REG DENALI_PI_231
+#define LPDDR4__PI_TFC_F1__FLD LPDDR4__DENALI_PI_231__PI_TFC_F1
+
+#define LPDDR4__DENALI_PI_231__PI_TCKEHDQS_F2_MASK 0x003F0000U
+#define LPDDR4__DENALI_PI_231__PI_TCKEHDQS_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_231__PI_TCKEHDQS_F2_WIDTH 6U
+#define LPDDR4__PI_TCKEHDQS_F2__REG DENALI_PI_231
+#define LPDDR4__PI_TCKEHDQS_F2__FLD LPDDR4__DENALI_PI_231__PI_TCKEHDQS_F2
+
+#define LPDDR4__DENALI_PI_232_READ_MASK 0x030303FFU
+#define LPDDR4__DENALI_PI_232_WRITE_MASK 0x030303FFU
+#define LPDDR4__DENALI_PI_232__PI_TFC_F2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_232__PI_TFC_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_232__PI_TFC_F2_WIDTH 10U
+#define LPDDR4__PI_TFC_F2__REG DENALI_PI_232
+#define LPDDR4__PI_TFC_F2__FLD LPDDR4__DENALI_PI_232__PI_TFC_F2
+
+#define LPDDR4__DENALI_PI_232__PI_VREF_EN_F0_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_232__PI_VREF_EN_F0_SHIFT 16U
+#define LPDDR4__DENALI_PI_232__PI_VREF_EN_F0_WIDTH 2U
+#define LPDDR4__PI_VREF_EN_F0__REG DENALI_PI_232
+#define LPDDR4__PI_VREF_EN_F0__FLD LPDDR4__DENALI_PI_232__PI_VREF_EN_F0
+
+#define LPDDR4__DENALI_PI_232__PI_VREF_EN_F1_MASK 0x03000000U
+#define LPDDR4__DENALI_PI_232__PI_VREF_EN_F1_SHIFT 24U
+#define LPDDR4__DENALI_PI_232__PI_VREF_EN_F1_WIDTH 2U
+#define LPDDR4__PI_VREF_EN_F1__REG DENALI_PI_232
+#define LPDDR4__PI_VREF_EN_F1__FLD LPDDR4__DENALI_PI_232__PI_VREF_EN_F1
+
+#define LPDDR4__DENALI_PI_233_READ_MASK 0x0003FF03U
+#define LPDDR4__DENALI_PI_233_WRITE_MASK 0x0003FF03U
+#define LPDDR4__DENALI_PI_233__PI_VREF_EN_F2_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_233__PI_VREF_EN_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_233__PI_VREF_EN_F2_WIDTH 2U
+#define LPDDR4__PI_VREF_EN_F2__REG DENALI_PI_233
+#define LPDDR4__PI_VREF_EN_F2__FLD LPDDR4__DENALI_PI_233__PI_VREF_EN_F2
+
+#define LPDDR4__DENALI_PI_233__PI_TDFI_WDQLVL_WR_F0_MASK 0x0003FF00U
+#define LPDDR4__DENALI_PI_233__PI_TDFI_WDQLVL_WR_F0_SHIFT 8U
+#define LPDDR4__DENALI_PI_233__PI_TDFI_WDQLVL_WR_F0_WIDTH 10U
+#define LPDDR4__PI_TDFI_WDQLVL_WR_F0__REG DENALI_PI_233
+#define LPDDR4__PI_TDFI_WDQLVL_WR_F0__FLD LPDDR4__DENALI_PI_233__PI_TDFI_WDQLVL_WR_F0
+
+#define LPDDR4__DENALI_PI_234_READ_MASK 0x7F7F03FFU
+#define LPDDR4__DENALI_PI_234_WRITE_MASK 0x7F7F03FFU
+#define LPDDR4__DENALI_PI_234__PI_TDFI_WDQLVL_RW_F0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_234__PI_TDFI_WDQLVL_RW_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_234__PI_TDFI_WDQLVL_RW_F0_WIDTH 10U
+#define LPDDR4__PI_TDFI_WDQLVL_RW_F0__REG DENALI_PI_234
+#define LPDDR4__PI_TDFI_WDQLVL_RW_F0__FLD LPDDR4__DENALI_PI_234__PI_TDFI_WDQLVL_RW_F0
+
+#define LPDDR4__DENALI_PI_234__PI_WDQLVL_VREF_INITIAL_START_POINT_F0_MASK 0x007F0000U
+#define LPDDR4__DENALI_PI_234__PI_WDQLVL_VREF_INITIAL_START_POINT_F0_SHIFT 16U
+#define LPDDR4__DENALI_PI_234__PI_WDQLVL_VREF_INITIAL_START_POINT_F0_WIDTH 7U
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F0__REG DENALI_PI_234
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F0__FLD LPDDR4__DENALI_PI_234__PI_WDQLVL_VREF_INITIAL_START_POINT_F0
+
+#define LPDDR4__DENALI_PI_234__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0_MASK 0x7F000000U
+#define LPDDR4__DENALI_PI_234__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0_SHIFT 24U
+#define LPDDR4__DENALI_PI_234__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0_WIDTH 7U
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0__REG DENALI_PI_234
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0__FLD LPDDR4__DENALI_PI_234__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0
+
+#define LPDDR4__DENALI_PI_235_READ_MASK 0x1F03030FU
+#define LPDDR4__DENALI_PI_235_WRITE_MASK 0x1F03030FU
+#define LPDDR4__DENALI_PI_235__PI_WDQLVL_VREF_DELTA_F0_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_235__PI_WDQLVL_VREF_DELTA_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_235__PI_WDQLVL_VREF_DELTA_F0_WIDTH 4U
+#define LPDDR4__PI_WDQLVL_VREF_DELTA_F0__REG DENALI_PI_235
+#define LPDDR4__PI_WDQLVL_VREF_DELTA_F0__FLD LPDDR4__DENALI_PI_235__PI_WDQLVL_VREF_DELTA_F0
+
+#define LPDDR4__DENALI_PI_235__PI_WDQLVL_EN_F0_MASK 0x00000300U
+#define LPDDR4__DENALI_PI_235__PI_WDQLVL_EN_F0_SHIFT 8U
+#define LPDDR4__DENALI_PI_235__PI_WDQLVL_EN_F0_WIDTH 2U
+#define LPDDR4__PI_WDQLVL_EN_F0__REG DENALI_PI_235
+#define LPDDR4__PI_WDQLVL_EN_F0__FLD LPDDR4__DENALI_PI_235__PI_WDQLVL_EN_F0
+
+#define LPDDR4__DENALI_PI_235__PI_NTP_TRAIN_EN_F0_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_235__PI_NTP_TRAIN_EN_F0_SHIFT 16U
+#define LPDDR4__DENALI_PI_235__PI_NTP_TRAIN_EN_F0_WIDTH 2U
+#define LPDDR4__PI_NTP_TRAIN_EN_F0__REG DENALI_PI_235
+#define LPDDR4__PI_NTP_TRAIN_EN_F0__FLD LPDDR4__DENALI_PI_235__PI_NTP_TRAIN_EN_F0
+
+#define LPDDR4__DENALI_PI_235__PI_WDQLVL_CL_F0_MASK 0x1F000000U
+#define LPDDR4__DENALI_PI_235__PI_WDQLVL_CL_F0_SHIFT 24U
+#define LPDDR4__DENALI_PI_235__PI_WDQLVL_CL_F0_WIDTH 5U
+#define LPDDR4__PI_WDQLVL_CL_F0__REG DENALI_PI_235
+#define LPDDR4__PI_WDQLVL_CL_F0__FLD LPDDR4__DENALI_PI_235__PI_WDQLVL_CL_F0
+
+#define LPDDR4__DENALI_PI_236_READ_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_PI_236_WRITE_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_PI_236__PI_WDQLVL_RDLAT_ADJ_F0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_236__PI_WDQLVL_RDLAT_ADJ_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_236__PI_WDQLVL_RDLAT_ADJ_F0_WIDTH 8U
+#define LPDDR4__PI_WDQLVL_RDLAT_ADJ_F0__REG DENALI_PI_236
+#define LPDDR4__PI_WDQLVL_RDLAT_ADJ_F0__FLD LPDDR4__DENALI_PI_236__PI_WDQLVL_RDLAT_ADJ_F0
+
+#define LPDDR4__DENALI_PI_236__PI_WDQLVL_WRLAT_ADJ_F0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_236__PI_WDQLVL_WRLAT_ADJ_F0_SHIFT 8U
+#define LPDDR4__DENALI_PI_236__PI_WDQLVL_WRLAT_ADJ_F0_WIDTH 8U
+#define LPDDR4__PI_WDQLVL_WRLAT_ADJ_F0__REG DENALI_PI_236
+#define LPDDR4__PI_WDQLVL_WRLAT_ADJ_F0__FLD LPDDR4__DENALI_PI_236__PI_WDQLVL_WRLAT_ADJ_F0
+
+#define LPDDR4__DENALI_PI_236__PI_TDFI_WDQLVL_WR_F1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PI_236__PI_TDFI_WDQLVL_WR_F1_SHIFT 16U
+#define LPDDR4__DENALI_PI_236__PI_TDFI_WDQLVL_WR_F1_WIDTH 10U
+#define LPDDR4__PI_TDFI_WDQLVL_WR_F1__REG DENALI_PI_236
+#define LPDDR4__PI_TDFI_WDQLVL_WR_F1__FLD LPDDR4__DENALI_PI_236__PI_TDFI_WDQLVL_WR_F1
+
+#define LPDDR4__DENALI_PI_237_READ_MASK 0x7F7F03FFU
+#define LPDDR4__DENALI_PI_237_WRITE_MASK 0x7F7F03FFU
+#define LPDDR4__DENALI_PI_237__PI_TDFI_WDQLVL_RW_F1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_237__PI_TDFI_WDQLVL_RW_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_237__PI_TDFI_WDQLVL_RW_F1_WIDTH 10U
+#define LPDDR4__PI_TDFI_WDQLVL_RW_F1__REG DENALI_PI_237
+#define LPDDR4__PI_TDFI_WDQLVL_RW_F1__FLD LPDDR4__DENALI_PI_237__PI_TDFI_WDQLVL_RW_F1
+
+#define LPDDR4__DENALI_PI_237__PI_WDQLVL_VREF_INITIAL_START_POINT_F1_MASK 0x007F0000U
+#define LPDDR4__DENALI_PI_237__PI_WDQLVL_VREF_INITIAL_START_POINT_F1_SHIFT 16U
+#define LPDDR4__DENALI_PI_237__PI_WDQLVL_VREF_INITIAL_START_POINT_F1_WIDTH 7U
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F1__REG DENALI_PI_237
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F1__FLD LPDDR4__DENALI_PI_237__PI_WDQLVL_VREF_INITIAL_START_POINT_F1
+
+#define LPDDR4__DENALI_PI_237__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1_MASK 0x7F000000U
+#define LPDDR4__DENALI_PI_237__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1_SHIFT 24U
+#define LPDDR4__DENALI_PI_237__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1_WIDTH 7U
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1__REG DENALI_PI_237
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1__FLD LPDDR4__DENALI_PI_237__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1
+
+#define LPDDR4__DENALI_PI_238_READ_MASK 0x1F03030FU
+#define LPDDR4__DENALI_PI_238_WRITE_MASK 0x1F03030FU
+#define LPDDR4__DENALI_PI_238__PI_WDQLVL_VREF_DELTA_F1_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_238__PI_WDQLVL_VREF_DELTA_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_238__PI_WDQLVL_VREF_DELTA_F1_WIDTH 4U
+#define LPDDR4__PI_WDQLVL_VREF_DELTA_F1__REG DENALI_PI_238
+#define LPDDR4__PI_WDQLVL_VREF_DELTA_F1__FLD LPDDR4__DENALI_PI_238__PI_WDQLVL_VREF_DELTA_F1
+
+#define LPDDR4__DENALI_PI_238__PI_WDQLVL_EN_F1_MASK 0x00000300U
+#define LPDDR4__DENALI_PI_238__PI_WDQLVL_EN_F1_SHIFT 8U
+#define LPDDR4__DENALI_PI_238__PI_WDQLVL_EN_F1_WIDTH 2U
+#define LPDDR4__PI_WDQLVL_EN_F1__REG DENALI_PI_238
+#define LPDDR4__PI_WDQLVL_EN_F1__FLD LPDDR4__DENALI_PI_238__PI_WDQLVL_EN_F1
+
+#define LPDDR4__DENALI_PI_238__PI_NTP_TRAIN_EN_F1_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_238__PI_NTP_TRAIN_EN_F1_SHIFT 16U
+#define LPDDR4__DENALI_PI_238__PI_NTP_TRAIN_EN_F1_WIDTH 2U
+#define LPDDR4__PI_NTP_TRAIN_EN_F1__REG DENALI_PI_238
+#define LPDDR4__PI_NTP_TRAIN_EN_F1__FLD LPDDR4__DENALI_PI_238__PI_NTP_TRAIN_EN_F1
+
+#define LPDDR4__DENALI_PI_238__PI_WDQLVL_CL_F1_MASK 0x1F000000U
+#define LPDDR4__DENALI_PI_238__PI_WDQLVL_CL_F1_SHIFT 24U
+#define LPDDR4__DENALI_PI_238__PI_WDQLVL_CL_F1_WIDTH 5U
+#define LPDDR4__PI_WDQLVL_CL_F1__REG DENALI_PI_238
+#define LPDDR4__PI_WDQLVL_CL_F1__FLD LPDDR4__DENALI_PI_238__PI_WDQLVL_CL_F1
+
+#define LPDDR4__DENALI_PI_239_READ_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_PI_239_WRITE_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_PI_239__PI_WDQLVL_RDLAT_ADJ_F1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_239__PI_WDQLVL_RDLAT_ADJ_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_239__PI_WDQLVL_RDLAT_ADJ_F1_WIDTH 8U
+#define LPDDR4__PI_WDQLVL_RDLAT_ADJ_F1__REG DENALI_PI_239
+#define LPDDR4__PI_WDQLVL_RDLAT_ADJ_F1__FLD LPDDR4__DENALI_PI_239__PI_WDQLVL_RDLAT_ADJ_F1
+
+#define LPDDR4__DENALI_PI_239__PI_WDQLVL_WRLAT_ADJ_F1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_239__PI_WDQLVL_WRLAT_ADJ_F1_SHIFT 8U
+#define LPDDR4__DENALI_PI_239__PI_WDQLVL_WRLAT_ADJ_F1_WIDTH 8U
+#define LPDDR4__PI_WDQLVL_WRLAT_ADJ_F1__REG DENALI_PI_239
+#define LPDDR4__PI_WDQLVL_WRLAT_ADJ_F1__FLD LPDDR4__DENALI_PI_239__PI_WDQLVL_WRLAT_ADJ_F1
+
+#define LPDDR4__DENALI_PI_239__PI_TDFI_WDQLVL_WR_F2_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PI_239__PI_TDFI_WDQLVL_WR_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_239__PI_TDFI_WDQLVL_WR_F2_WIDTH 10U
+#define LPDDR4__PI_TDFI_WDQLVL_WR_F2__REG DENALI_PI_239
+#define LPDDR4__PI_TDFI_WDQLVL_WR_F2__FLD LPDDR4__DENALI_PI_239__PI_TDFI_WDQLVL_WR_F2
+
+#define LPDDR4__DENALI_PI_240_READ_MASK 0x7F7F03FFU
+#define LPDDR4__DENALI_PI_240_WRITE_MASK 0x7F7F03FFU
+#define LPDDR4__DENALI_PI_240__PI_TDFI_WDQLVL_RW_F2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_240__PI_TDFI_WDQLVL_RW_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_240__PI_TDFI_WDQLVL_RW_F2_WIDTH 10U
+#define LPDDR4__PI_TDFI_WDQLVL_RW_F2__REG DENALI_PI_240
+#define LPDDR4__PI_TDFI_WDQLVL_RW_F2__FLD LPDDR4__DENALI_PI_240__PI_TDFI_WDQLVL_RW_F2
+
+#define LPDDR4__DENALI_PI_240__PI_WDQLVL_VREF_INITIAL_START_POINT_F2_MASK 0x007F0000U
+#define LPDDR4__DENALI_PI_240__PI_WDQLVL_VREF_INITIAL_START_POINT_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_240__PI_WDQLVL_VREF_INITIAL_START_POINT_F2_WIDTH 7U
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F2__REG DENALI_PI_240
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F2__FLD LPDDR4__DENALI_PI_240__PI_WDQLVL_VREF_INITIAL_START_POINT_F2
+
+#define LPDDR4__DENALI_PI_240__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2_MASK 0x7F000000U
+#define LPDDR4__DENALI_PI_240__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2_SHIFT 24U
+#define LPDDR4__DENALI_PI_240__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2_WIDTH 7U
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2__REG DENALI_PI_240
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2__FLD LPDDR4__DENALI_PI_240__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2
+
+#define LPDDR4__DENALI_PI_241_READ_MASK 0x1F03030FU
+#define LPDDR4__DENALI_PI_241_WRITE_MASK 0x1F03030FU
+#define LPDDR4__DENALI_PI_241__PI_WDQLVL_VREF_DELTA_F2_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_241__PI_WDQLVL_VREF_DELTA_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_241__PI_WDQLVL_VREF_DELTA_F2_WIDTH 4U
+#define LPDDR4__PI_WDQLVL_VREF_DELTA_F2__REG DENALI_PI_241
+#define LPDDR4__PI_WDQLVL_VREF_DELTA_F2__FLD LPDDR4__DENALI_PI_241__PI_WDQLVL_VREF_DELTA_F2
+
+#define LPDDR4__DENALI_PI_241__PI_WDQLVL_EN_F2_MASK 0x00000300U
+#define LPDDR4__DENALI_PI_241__PI_WDQLVL_EN_F2_SHIFT 8U
+#define LPDDR4__DENALI_PI_241__PI_WDQLVL_EN_F2_WIDTH 2U
+#define LPDDR4__PI_WDQLVL_EN_F2__REG DENALI_PI_241
+#define LPDDR4__PI_WDQLVL_EN_F2__FLD LPDDR4__DENALI_PI_241__PI_WDQLVL_EN_F2
+
+#define LPDDR4__DENALI_PI_241__PI_NTP_TRAIN_EN_F2_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_241__PI_NTP_TRAIN_EN_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_241__PI_NTP_TRAIN_EN_F2_WIDTH 2U
+#define LPDDR4__PI_NTP_TRAIN_EN_F2__REG DENALI_PI_241
+#define LPDDR4__PI_NTP_TRAIN_EN_F2__FLD LPDDR4__DENALI_PI_241__PI_NTP_TRAIN_EN_F2
+
+#define LPDDR4__DENALI_PI_241__PI_WDQLVL_CL_F2_MASK 0x1F000000U
+#define LPDDR4__DENALI_PI_241__PI_WDQLVL_CL_F2_SHIFT 24U
+#define LPDDR4__DENALI_PI_241__PI_WDQLVL_CL_F2_WIDTH 5U
+#define LPDDR4__PI_WDQLVL_CL_F2__REG DENALI_PI_241
+#define LPDDR4__PI_WDQLVL_CL_F2__FLD LPDDR4__DENALI_PI_241__PI_WDQLVL_CL_F2
+
+#define LPDDR4__DENALI_PI_242_READ_MASK 0x0303FFFFU
+#define LPDDR4__DENALI_PI_242_WRITE_MASK 0x0303FFFFU
+#define LPDDR4__DENALI_PI_242__PI_WDQLVL_RDLAT_ADJ_F2_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_242__PI_WDQLVL_RDLAT_ADJ_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_242__PI_WDQLVL_RDLAT_ADJ_F2_WIDTH 8U
+#define LPDDR4__PI_WDQLVL_RDLAT_ADJ_F2__REG DENALI_PI_242
+#define LPDDR4__PI_WDQLVL_RDLAT_ADJ_F2__FLD LPDDR4__DENALI_PI_242__PI_WDQLVL_RDLAT_ADJ_F2
+
+#define LPDDR4__DENALI_PI_242__PI_WDQLVL_WRLAT_ADJ_F2_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_242__PI_WDQLVL_WRLAT_ADJ_F2_SHIFT 8U
+#define LPDDR4__DENALI_PI_242__PI_WDQLVL_WRLAT_ADJ_F2_WIDTH 8U
+#define LPDDR4__PI_WDQLVL_WRLAT_ADJ_F2__REG DENALI_PI_242
+#define LPDDR4__PI_WDQLVL_WRLAT_ADJ_F2__FLD LPDDR4__DENALI_PI_242__PI_WDQLVL_WRLAT_ADJ_F2
+
+#define LPDDR4__DENALI_PI_242__PI_RD_DBI_LEVEL_EN_F0_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_242__PI_RD_DBI_LEVEL_EN_F0_SHIFT 16U
+#define LPDDR4__DENALI_PI_242__PI_RD_DBI_LEVEL_EN_F0_WIDTH 2U
+#define LPDDR4__PI_RD_DBI_LEVEL_EN_F0__REG DENALI_PI_242
+#define LPDDR4__PI_RD_DBI_LEVEL_EN_F0__FLD LPDDR4__DENALI_PI_242__PI_RD_DBI_LEVEL_EN_F0
+
+#define LPDDR4__DENALI_PI_242__PI_RD_DBI_LEVEL_EN_F1_MASK 0x03000000U
+#define LPDDR4__DENALI_PI_242__PI_RD_DBI_LEVEL_EN_F1_SHIFT 24U
+#define LPDDR4__DENALI_PI_242__PI_RD_DBI_LEVEL_EN_F1_WIDTH 2U
+#define LPDDR4__PI_RD_DBI_LEVEL_EN_F1__REG DENALI_PI_242
+#define LPDDR4__PI_RD_DBI_LEVEL_EN_F1__FLD LPDDR4__DENALI_PI_242__PI_RD_DBI_LEVEL_EN_F1
+
+#define LPDDR4__DENALI_PI_243_READ_MASK 0xFFFFFF03U
+#define LPDDR4__DENALI_PI_243_WRITE_MASK 0xFFFFFF03U
+#define LPDDR4__DENALI_PI_243__PI_RD_DBI_LEVEL_EN_F2_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_243__PI_RD_DBI_LEVEL_EN_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_243__PI_RD_DBI_LEVEL_EN_F2_WIDTH 2U
+#define LPDDR4__PI_RD_DBI_LEVEL_EN_F2__REG DENALI_PI_243
+#define LPDDR4__PI_RD_DBI_LEVEL_EN_F2__FLD LPDDR4__DENALI_PI_243__PI_RD_DBI_LEVEL_EN_F2
+
+#define LPDDR4__DENALI_PI_243__PI_TRTP_F0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_243__PI_TRTP_F0_SHIFT 8U
+#define LPDDR4__DENALI_PI_243__PI_TRTP_F0_WIDTH 8U
+#define LPDDR4__PI_TRTP_F0__REG DENALI_PI_243
+#define LPDDR4__PI_TRTP_F0__FLD LPDDR4__DENALI_PI_243__PI_TRTP_F0
+
+#define LPDDR4__DENALI_PI_243__PI_TRP_F0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_243__PI_TRP_F0_SHIFT 16U
+#define LPDDR4__DENALI_PI_243__PI_TRP_F0_WIDTH 8U
+#define LPDDR4__PI_TRP_F0__REG DENALI_PI_243
+#define LPDDR4__PI_TRP_F0__FLD LPDDR4__DENALI_PI_243__PI_TRP_F0
+
+#define LPDDR4__DENALI_PI_243__PI_TRCD_F0_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_243__PI_TRCD_F0_SHIFT 24U
+#define LPDDR4__DENALI_PI_243__PI_TRCD_F0_WIDTH 8U
+#define LPDDR4__PI_TRCD_F0__REG DENALI_PI_243
+#define LPDDR4__PI_TRCD_F0__FLD LPDDR4__DENALI_PI_243__PI_TRCD_F0
+
+#define LPDDR4__DENALI_PI_244_READ_MASK 0x00FF3F1FU
+#define LPDDR4__DENALI_PI_244_WRITE_MASK 0x00FF3F1FU
+#define LPDDR4__DENALI_PI_244__PI_TCCD_L_F0_MASK 0x0000001FU
+#define LPDDR4__DENALI_PI_244__PI_TCCD_L_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_244__PI_TCCD_L_F0_WIDTH 5U
+#define LPDDR4__PI_TCCD_L_F0__REG DENALI_PI_244
+#define LPDDR4__PI_TCCD_L_F0__FLD LPDDR4__DENALI_PI_244__PI_TCCD_L_F0
+
+#define LPDDR4__DENALI_PI_244__PI_TWTR_F0_MASK 0x00003F00U
+#define LPDDR4__DENALI_PI_244__PI_TWTR_F0_SHIFT 8U
+#define LPDDR4__DENALI_PI_244__PI_TWTR_F0_WIDTH 6U
+#define LPDDR4__PI_TWTR_F0__REG DENALI_PI_244
+#define LPDDR4__PI_TWTR_F0__FLD LPDDR4__DENALI_PI_244__PI_TWTR_F0
+
+#define LPDDR4__DENALI_PI_244__PI_TWR_F0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_244__PI_TWR_F0_SHIFT 16U
+#define LPDDR4__DENALI_PI_244__PI_TWR_F0_WIDTH 8U
+#define LPDDR4__PI_TWR_F0__REG DENALI_PI_244
+#define LPDDR4__PI_TWR_F0__FLD LPDDR4__DENALI_PI_244__PI_TWR_F0
+
+#define LPDDR4__DENALI_PI_245_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PI_245_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PI_245__PI_TRAS_MAX_F0_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PI_245__PI_TRAS_MAX_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_245__PI_TRAS_MAX_F0_WIDTH 20U
+#define LPDDR4__PI_TRAS_MAX_F0__REG DENALI_PI_245
+#define LPDDR4__PI_TRAS_MAX_F0__FLD LPDDR4__DENALI_PI_245__PI_TRAS_MAX_F0
+
+#define LPDDR4__DENALI_PI_246_READ_MASK 0x3F0F01FFU
+#define LPDDR4__DENALI_PI_246_WRITE_MASK 0x3F0F01FFU
+#define LPDDR4__DENALI_PI_246__PI_TRAS_MIN_F0_MASK 0x000001FFU
+#define LPDDR4__DENALI_PI_246__PI_TRAS_MIN_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_246__PI_TRAS_MIN_F0_WIDTH 9U
+#define LPDDR4__PI_TRAS_MIN_F0__REG DENALI_PI_246
+#define LPDDR4__PI_TRAS_MIN_F0__FLD LPDDR4__DENALI_PI_246__PI_TRAS_MIN_F0
+
+#define LPDDR4__DENALI_PI_246__PI_TDQSCK_MAX_F0_MASK 0x000F0000U
+#define LPDDR4__DENALI_PI_246__PI_TDQSCK_MAX_F0_SHIFT 16U
+#define LPDDR4__DENALI_PI_246__PI_TDQSCK_MAX_F0_WIDTH 4U
+#define LPDDR4__PI_TDQSCK_MAX_F0__REG DENALI_PI_246
+#define LPDDR4__PI_TDQSCK_MAX_F0__FLD LPDDR4__DENALI_PI_246__PI_TDQSCK_MAX_F0
+
+#define LPDDR4__DENALI_PI_246__PI_TCCDMW_F0_MASK 0x3F000000U
+#define LPDDR4__DENALI_PI_246__PI_TCCDMW_F0_SHIFT 24U
+#define LPDDR4__DENALI_PI_246__PI_TCCDMW_F0_WIDTH 6U
+#define LPDDR4__PI_TCCDMW_F0__REG DENALI_PI_246
+#define LPDDR4__PI_TCCDMW_F0__FLD LPDDR4__DENALI_PI_246__PI_TCCDMW_F0
+
+#define LPDDR4__DENALI_PI_247_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_247_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_247__PI_TSR_F0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_247__PI_TSR_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_247__PI_TSR_F0_WIDTH 8U
+#define LPDDR4__PI_TSR_F0__REG DENALI_PI_247
+#define LPDDR4__PI_TSR_F0__FLD LPDDR4__DENALI_PI_247__PI_TSR_F0
+
+#define LPDDR4__DENALI_PI_247__PI_TMRD_F0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_247__PI_TMRD_F0_SHIFT 8U
+#define LPDDR4__DENALI_PI_247__PI_TMRD_F0_WIDTH 8U
+#define LPDDR4__PI_TMRD_F0__REG DENALI_PI_247
+#define LPDDR4__PI_TMRD_F0__FLD LPDDR4__DENALI_PI_247__PI_TMRD_F0
+
+#define LPDDR4__DENALI_PI_247__PI_TMRW_F0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_247__PI_TMRW_F0_SHIFT 16U
+#define LPDDR4__DENALI_PI_247__PI_TMRW_F0_WIDTH 8U
+#define LPDDR4__PI_TMRW_F0__REG DENALI_PI_247
+#define LPDDR4__PI_TMRW_F0__FLD LPDDR4__DENALI_PI_247__PI_TMRW_F0
+
+#define LPDDR4__DENALI_PI_247__PI_TMOD_F0_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_247__PI_TMOD_F0_SHIFT 24U
+#define LPDDR4__DENALI_PI_247__PI_TMOD_F0_WIDTH 8U
+#define LPDDR4__PI_TMOD_F0__REG DENALI_PI_247
+#define LPDDR4__PI_TMOD_F0__FLD LPDDR4__DENALI_PI_247__PI_TMOD_F0
+
+#define LPDDR4__DENALI_PI_248_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_248_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_248__PI_TMOD_PAR_F0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_248__PI_TMOD_PAR_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_248__PI_TMOD_PAR_F0_WIDTH 8U
+#define LPDDR4__PI_TMOD_PAR_F0__REG DENALI_PI_248
+#define LPDDR4__PI_TMOD_PAR_F0__FLD LPDDR4__DENALI_PI_248__PI_TMOD_PAR_F0
+
+#define LPDDR4__DENALI_PI_248__PI_TMRD_PAR_F0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_248__PI_TMRD_PAR_F0_SHIFT 8U
+#define LPDDR4__DENALI_PI_248__PI_TMRD_PAR_F0_WIDTH 8U
+#define LPDDR4__PI_TMRD_PAR_F0__REG DENALI_PI_248
+#define LPDDR4__PI_TMRD_PAR_F0__FLD LPDDR4__DENALI_PI_248__PI_TMRD_PAR_F0
+
+#define LPDDR4__DENALI_PI_248__PI_TRTP_F1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_248__PI_TRTP_F1_SHIFT 16U
+#define LPDDR4__DENALI_PI_248__PI_TRTP_F1_WIDTH 8U
+#define LPDDR4__PI_TRTP_F1__REG DENALI_PI_248
+#define LPDDR4__PI_TRTP_F1__FLD LPDDR4__DENALI_PI_248__PI_TRTP_F1
+
+#define LPDDR4__DENALI_PI_248__PI_TRP_F1_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_248__PI_TRP_F1_SHIFT 24U
+#define LPDDR4__DENALI_PI_248__PI_TRP_F1_WIDTH 8U
+#define LPDDR4__PI_TRP_F1__REG DENALI_PI_248
+#define LPDDR4__PI_TRP_F1__FLD LPDDR4__DENALI_PI_248__PI_TRP_F1
+
+#define LPDDR4__DENALI_PI_249_READ_MASK 0xFF3F1FFFU
+#define LPDDR4__DENALI_PI_249_WRITE_MASK 0xFF3F1FFFU
+#define LPDDR4__DENALI_PI_249__PI_TRCD_F1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_249__PI_TRCD_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_249__PI_TRCD_F1_WIDTH 8U
+#define LPDDR4__PI_TRCD_F1__REG DENALI_PI_249
+#define LPDDR4__PI_TRCD_F1__FLD LPDDR4__DENALI_PI_249__PI_TRCD_F1
+
+#define LPDDR4__DENALI_PI_249__PI_TCCD_L_F1_MASK 0x00001F00U
+#define LPDDR4__DENALI_PI_249__PI_TCCD_L_F1_SHIFT 8U
+#define LPDDR4__DENALI_PI_249__PI_TCCD_L_F1_WIDTH 5U
+#define LPDDR4__PI_TCCD_L_F1__REG DENALI_PI_249
+#define LPDDR4__PI_TCCD_L_F1__FLD LPDDR4__DENALI_PI_249__PI_TCCD_L_F1
+
+#define LPDDR4__DENALI_PI_249__PI_TWTR_F1_MASK 0x003F0000U
+#define LPDDR4__DENALI_PI_249__PI_TWTR_F1_SHIFT 16U
+#define LPDDR4__DENALI_PI_249__PI_TWTR_F1_WIDTH 6U
+#define LPDDR4__PI_TWTR_F1__REG DENALI_PI_249
+#define LPDDR4__PI_TWTR_F1__FLD LPDDR4__DENALI_PI_249__PI_TWTR_F1
+
+#define LPDDR4__DENALI_PI_249__PI_TWR_F1_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_249__PI_TWR_F1_SHIFT 24U
+#define LPDDR4__DENALI_PI_249__PI_TWR_F1_WIDTH 8U
+#define LPDDR4__PI_TWR_F1__REG DENALI_PI_249
+#define LPDDR4__PI_TWR_F1__FLD LPDDR4__DENALI_PI_249__PI_TWR_F1
+
+#define LPDDR4__DENALI_PI_250_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PI_250_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PI_250__PI_TRAS_MAX_F1_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PI_250__PI_TRAS_MAX_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_250__PI_TRAS_MAX_F1_WIDTH 20U
+#define LPDDR4__PI_TRAS_MAX_F1__REG DENALI_PI_250
+#define LPDDR4__PI_TRAS_MAX_F1__FLD LPDDR4__DENALI_PI_250__PI_TRAS_MAX_F1
+
+#define LPDDR4__DENALI_PI_251_READ_MASK 0x3F0F01FFU
+#define LPDDR4__DENALI_PI_251_WRITE_MASK 0x3F0F01FFU
+#define LPDDR4__DENALI_PI_251__PI_TRAS_MIN_F1_MASK 0x000001FFU
+#define LPDDR4__DENALI_PI_251__PI_TRAS_MIN_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_251__PI_TRAS_MIN_F1_WIDTH 9U
+#define LPDDR4__PI_TRAS_MIN_F1__REG DENALI_PI_251
+#define LPDDR4__PI_TRAS_MIN_F1__FLD LPDDR4__DENALI_PI_251__PI_TRAS_MIN_F1
+
+#define LPDDR4__DENALI_PI_251__PI_TDQSCK_MAX_F1_MASK 0x000F0000U
+#define LPDDR4__DENALI_PI_251__PI_TDQSCK_MAX_F1_SHIFT 16U
+#define LPDDR4__DENALI_PI_251__PI_TDQSCK_MAX_F1_WIDTH 4U
+#define LPDDR4__PI_TDQSCK_MAX_F1__REG DENALI_PI_251
+#define LPDDR4__PI_TDQSCK_MAX_F1__FLD LPDDR4__DENALI_PI_251__PI_TDQSCK_MAX_F1
+
+#define LPDDR4__DENALI_PI_251__PI_TCCDMW_F1_MASK 0x3F000000U
+#define LPDDR4__DENALI_PI_251__PI_TCCDMW_F1_SHIFT 24U
+#define LPDDR4__DENALI_PI_251__PI_TCCDMW_F1_WIDTH 6U
+#define LPDDR4__PI_TCCDMW_F1__REG DENALI_PI_251
+#define LPDDR4__PI_TCCDMW_F1__FLD LPDDR4__DENALI_PI_251__PI_TCCDMW_F1
+
+#define LPDDR4__DENALI_PI_252_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_252_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_252__PI_TSR_F1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_252__PI_TSR_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_252__PI_TSR_F1_WIDTH 8U
+#define LPDDR4__PI_TSR_F1__REG DENALI_PI_252
+#define LPDDR4__PI_TSR_F1__FLD LPDDR4__DENALI_PI_252__PI_TSR_F1
+
+#define LPDDR4__DENALI_PI_252__PI_TMRD_F1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_252__PI_TMRD_F1_SHIFT 8U
+#define LPDDR4__DENALI_PI_252__PI_TMRD_F1_WIDTH 8U
+#define LPDDR4__PI_TMRD_F1__REG DENALI_PI_252
+#define LPDDR4__PI_TMRD_F1__FLD LPDDR4__DENALI_PI_252__PI_TMRD_F1
+
+#define LPDDR4__DENALI_PI_252__PI_TMRW_F1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_252__PI_TMRW_F1_SHIFT 16U
+#define LPDDR4__DENALI_PI_252__PI_TMRW_F1_WIDTH 8U
+#define LPDDR4__PI_TMRW_F1__REG DENALI_PI_252
+#define LPDDR4__PI_TMRW_F1__FLD LPDDR4__DENALI_PI_252__PI_TMRW_F1
+
+#define LPDDR4__DENALI_PI_252__PI_TMOD_F1_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_252__PI_TMOD_F1_SHIFT 24U
+#define LPDDR4__DENALI_PI_252__PI_TMOD_F1_WIDTH 8U
+#define LPDDR4__PI_TMOD_F1__REG DENALI_PI_252
+#define LPDDR4__PI_TMOD_F1__FLD LPDDR4__DENALI_PI_252__PI_TMOD_F1
+
+#define LPDDR4__DENALI_PI_253_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_253_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_253__PI_TMOD_PAR_F1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_253__PI_TMOD_PAR_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_253__PI_TMOD_PAR_F1_WIDTH 8U
+#define LPDDR4__PI_TMOD_PAR_F1__REG DENALI_PI_253
+#define LPDDR4__PI_TMOD_PAR_F1__FLD LPDDR4__DENALI_PI_253__PI_TMOD_PAR_F1
+
+#define LPDDR4__DENALI_PI_253__PI_TMRD_PAR_F1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_253__PI_TMRD_PAR_F1_SHIFT 8U
+#define LPDDR4__DENALI_PI_253__PI_TMRD_PAR_F1_WIDTH 8U
+#define LPDDR4__PI_TMRD_PAR_F1__REG DENALI_PI_253
+#define LPDDR4__PI_TMRD_PAR_F1__FLD LPDDR4__DENALI_PI_253__PI_TMRD_PAR_F1
+
+#define LPDDR4__DENALI_PI_253__PI_TRTP_F2_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_253__PI_TRTP_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_253__PI_TRTP_F2_WIDTH 8U
+#define LPDDR4__PI_TRTP_F2__REG DENALI_PI_253
+#define LPDDR4__PI_TRTP_F2__FLD LPDDR4__DENALI_PI_253__PI_TRTP_F2
+
+#define LPDDR4__DENALI_PI_253__PI_TRP_F2_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_253__PI_TRP_F2_SHIFT 24U
+#define LPDDR4__DENALI_PI_253__PI_TRP_F2_WIDTH 8U
+#define LPDDR4__PI_TRP_F2__REG DENALI_PI_253
+#define LPDDR4__PI_TRP_F2__FLD LPDDR4__DENALI_PI_253__PI_TRP_F2
+
+#define LPDDR4__DENALI_PI_254_READ_MASK 0xFF3F1FFFU
+#define LPDDR4__DENALI_PI_254_WRITE_MASK 0xFF3F1FFFU
+#define LPDDR4__DENALI_PI_254__PI_TRCD_F2_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_254__PI_TRCD_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_254__PI_TRCD_F2_WIDTH 8U
+#define LPDDR4__PI_TRCD_F2__REG DENALI_PI_254
+#define LPDDR4__PI_TRCD_F2__FLD LPDDR4__DENALI_PI_254__PI_TRCD_F2
+
+#define LPDDR4__DENALI_PI_254__PI_TCCD_L_F2_MASK 0x00001F00U
+#define LPDDR4__DENALI_PI_254__PI_TCCD_L_F2_SHIFT 8U
+#define LPDDR4__DENALI_PI_254__PI_TCCD_L_F2_WIDTH 5U
+#define LPDDR4__PI_TCCD_L_F2__REG DENALI_PI_254
+#define LPDDR4__PI_TCCD_L_F2__FLD LPDDR4__DENALI_PI_254__PI_TCCD_L_F2
+
+#define LPDDR4__DENALI_PI_254__PI_TWTR_F2_MASK 0x003F0000U
+#define LPDDR4__DENALI_PI_254__PI_TWTR_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_254__PI_TWTR_F2_WIDTH 6U
+#define LPDDR4__PI_TWTR_F2__REG DENALI_PI_254
+#define LPDDR4__PI_TWTR_F2__FLD LPDDR4__DENALI_PI_254__PI_TWTR_F2
+
+#define LPDDR4__DENALI_PI_254__PI_TWR_F2_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_254__PI_TWR_F2_SHIFT 24U
+#define LPDDR4__DENALI_PI_254__PI_TWR_F2_WIDTH 8U
+#define LPDDR4__PI_TWR_F2__REG DENALI_PI_254
+#define LPDDR4__PI_TWR_F2__FLD LPDDR4__DENALI_PI_254__PI_TWR_F2
+
+#define LPDDR4__DENALI_PI_255_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PI_255_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PI_255__PI_TRAS_MAX_F2_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PI_255__PI_TRAS_MAX_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_255__PI_TRAS_MAX_F2_WIDTH 20U
+#define LPDDR4__PI_TRAS_MAX_F2__REG DENALI_PI_255
+#define LPDDR4__PI_TRAS_MAX_F2__FLD LPDDR4__DENALI_PI_255__PI_TRAS_MAX_F2
+
+#define LPDDR4__DENALI_PI_256_READ_MASK 0x3F0F01FFU
+#define LPDDR4__DENALI_PI_256_WRITE_MASK 0x3F0F01FFU
+#define LPDDR4__DENALI_PI_256__PI_TRAS_MIN_F2_MASK 0x000001FFU
+#define LPDDR4__DENALI_PI_256__PI_TRAS_MIN_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_256__PI_TRAS_MIN_F2_WIDTH 9U
+#define LPDDR4__PI_TRAS_MIN_F2__REG DENALI_PI_256
+#define LPDDR4__PI_TRAS_MIN_F2__FLD LPDDR4__DENALI_PI_256__PI_TRAS_MIN_F2
+
+#define LPDDR4__DENALI_PI_256__PI_TDQSCK_MAX_F2_MASK 0x000F0000U
+#define LPDDR4__DENALI_PI_256__PI_TDQSCK_MAX_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_256__PI_TDQSCK_MAX_F2_WIDTH 4U
+#define LPDDR4__PI_TDQSCK_MAX_F2__REG DENALI_PI_256
+#define LPDDR4__PI_TDQSCK_MAX_F2__FLD LPDDR4__DENALI_PI_256__PI_TDQSCK_MAX_F2
+
+#define LPDDR4__DENALI_PI_256__PI_TCCDMW_F2_MASK 0x3F000000U
+#define LPDDR4__DENALI_PI_256__PI_TCCDMW_F2_SHIFT 24U
+#define LPDDR4__DENALI_PI_256__PI_TCCDMW_F2_WIDTH 6U
+#define LPDDR4__PI_TCCDMW_F2__REG DENALI_PI_256
+#define LPDDR4__PI_TCCDMW_F2__FLD LPDDR4__DENALI_PI_256__PI_TCCDMW_F2
+
+#define LPDDR4__DENALI_PI_257_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_257_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_257__PI_TSR_F2_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_257__PI_TSR_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_257__PI_TSR_F2_WIDTH 8U
+#define LPDDR4__PI_TSR_F2__REG DENALI_PI_257
+#define LPDDR4__PI_TSR_F2__FLD LPDDR4__DENALI_PI_257__PI_TSR_F2
+
+#define LPDDR4__DENALI_PI_257__PI_TMRD_F2_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_257__PI_TMRD_F2_SHIFT 8U
+#define LPDDR4__DENALI_PI_257__PI_TMRD_F2_WIDTH 8U
+#define LPDDR4__PI_TMRD_F2__REG DENALI_PI_257
+#define LPDDR4__PI_TMRD_F2__FLD LPDDR4__DENALI_PI_257__PI_TMRD_F2
+
+#define LPDDR4__DENALI_PI_257__PI_TMRW_F2_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_257__PI_TMRW_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_257__PI_TMRW_F2_WIDTH 8U
+#define LPDDR4__PI_TMRW_F2__REG DENALI_PI_257
+#define LPDDR4__PI_TMRW_F2__FLD LPDDR4__DENALI_PI_257__PI_TMRW_F2
+
+#define LPDDR4__DENALI_PI_257__PI_TMOD_F2_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_257__PI_TMOD_F2_SHIFT 24U
+#define LPDDR4__DENALI_PI_257__PI_TMOD_F2_WIDTH 8U
+#define LPDDR4__PI_TMOD_F2__REG DENALI_PI_257
+#define LPDDR4__PI_TMOD_F2__FLD LPDDR4__DENALI_PI_257__PI_TMOD_F2
+
+#define LPDDR4__DENALI_PI_258_READ_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PI_258_WRITE_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PI_258__PI_TMOD_PAR_F2_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_258__PI_TMOD_PAR_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_258__PI_TMOD_PAR_F2_WIDTH 8U
+#define LPDDR4__PI_TMOD_PAR_F2__REG DENALI_PI_258
+#define LPDDR4__PI_TMOD_PAR_F2__FLD LPDDR4__DENALI_PI_258__PI_TMOD_PAR_F2
+
+#define LPDDR4__DENALI_PI_258__PI_TMRD_PAR_F2_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_258__PI_TMRD_PAR_F2_SHIFT 8U
+#define LPDDR4__DENALI_PI_258__PI_TMRD_PAR_F2_WIDTH 8U
+#define LPDDR4__PI_TMRD_PAR_F2__REG DENALI_PI_258
+#define LPDDR4__PI_TMRD_PAR_F2__FLD LPDDR4__DENALI_PI_258__PI_TMRD_PAR_F2
+
+#define LPDDR4__DENALI_PI_259_READ_MASK 0x001FFFFFU
+#define LPDDR4__DENALI_PI_259_WRITE_MASK 0x001FFFFFU
+#define LPDDR4__DENALI_PI_259__PI_TDFI_CTRLUPD_MAX_F0_MASK 0x001FFFFFU
+#define LPDDR4__DENALI_PI_259__PI_TDFI_CTRLUPD_MAX_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_259__PI_TDFI_CTRLUPD_MAX_F0_WIDTH 21U
+#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F0__REG DENALI_PI_259
+#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F0__FLD LPDDR4__DENALI_PI_259__PI_TDFI_CTRLUPD_MAX_F0
+
+#define LPDDR4__DENALI_PI_260_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_260_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_260__PI_TDFI_CTRLUPD_INTERVAL_F0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_260__PI_TDFI_CTRLUPD_INTERVAL_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_260__PI_TDFI_CTRLUPD_INTERVAL_F0_WIDTH 32U
+#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F0__REG DENALI_PI_260
+#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F0__FLD LPDDR4__DENALI_PI_260__PI_TDFI_CTRLUPD_INTERVAL_F0
+
+#define LPDDR4__DENALI_PI_261_READ_MASK 0x001FFFFFU
+#define LPDDR4__DENALI_PI_261_WRITE_MASK 0x001FFFFFU
+#define LPDDR4__DENALI_PI_261__PI_TDFI_CTRLUPD_MAX_F1_MASK 0x001FFFFFU
+#define LPDDR4__DENALI_PI_261__PI_TDFI_CTRLUPD_MAX_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_261__PI_TDFI_CTRLUPD_MAX_F1_WIDTH 21U
+#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F1__REG DENALI_PI_261
+#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F1__FLD LPDDR4__DENALI_PI_261__PI_TDFI_CTRLUPD_MAX_F1
+
+#define LPDDR4__DENALI_PI_262_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_262_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_262__PI_TDFI_CTRLUPD_INTERVAL_F1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_262__PI_TDFI_CTRLUPD_INTERVAL_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_262__PI_TDFI_CTRLUPD_INTERVAL_F1_WIDTH 32U
+#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F1__REG DENALI_PI_262
+#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F1__FLD LPDDR4__DENALI_PI_262__PI_TDFI_CTRLUPD_INTERVAL_F1
+
+#define LPDDR4__DENALI_PI_263_READ_MASK 0x001FFFFFU
+#define LPDDR4__DENALI_PI_263_WRITE_MASK 0x001FFFFFU
+#define LPDDR4__DENALI_PI_263__PI_TDFI_CTRLUPD_MAX_F2_MASK 0x001FFFFFU
+#define LPDDR4__DENALI_PI_263__PI_TDFI_CTRLUPD_MAX_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_263__PI_TDFI_CTRLUPD_MAX_F2_WIDTH 21U
+#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F2__REG DENALI_PI_263
+#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F2__FLD LPDDR4__DENALI_PI_263__PI_TDFI_CTRLUPD_MAX_F2
+
+#define LPDDR4__DENALI_PI_264_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_264_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_264__PI_TDFI_CTRLUPD_INTERVAL_F2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_264__PI_TDFI_CTRLUPD_INTERVAL_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_264__PI_TDFI_CTRLUPD_INTERVAL_F2_WIDTH 32U
+#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F2__REG DENALI_PI_264
+#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F2__FLD LPDDR4__DENALI_PI_264__PI_TDFI_CTRLUPD_INTERVAL_F2
+
+#define LPDDR4__DENALI_PI_265_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_265_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_265__PI_TXSR_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PI_265__PI_TXSR_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_265__PI_TXSR_F0_WIDTH 16U
+#define LPDDR4__PI_TXSR_F0__REG DENALI_PI_265
+#define LPDDR4__PI_TXSR_F0__FLD LPDDR4__DENALI_PI_265__PI_TXSR_F0
+
+#define LPDDR4__DENALI_PI_265__PI_TXSR_F1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_PI_265__PI_TXSR_F1_SHIFT 16U
+#define LPDDR4__DENALI_PI_265__PI_TXSR_F1_WIDTH 16U
+#define LPDDR4__PI_TXSR_F1__REG DENALI_PI_265
+#define LPDDR4__PI_TXSR_F1__FLD LPDDR4__DENALI_PI_265__PI_TXSR_F1
+
+#define LPDDR4__DENALI_PI_266_READ_MASK 0x3F3FFFFFU
+#define LPDDR4__DENALI_PI_266_WRITE_MASK 0x3F3FFFFFU
+#define LPDDR4__DENALI_PI_266__PI_TXSR_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PI_266__PI_TXSR_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_266__PI_TXSR_F2_WIDTH 16U
+#define LPDDR4__PI_TXSR_F2__REG DENALI_PI_266
+#define LPDDR4__PI_TXSR_F2__FLD LPDDR4__DENALI_PI_266__PI_TXSR_F2
+
+#define LPDDR4__DENALI_PI_266__PI_TEXCKE_F0_MASK 0x003F0000U
+#define LPDDR4__DENALI_PI_266__PI_TEXCKE_F0_SHIFT 16U
+#define LPDDR4__DENALI_PI_266__PI_TEXCKE_F0_WIDTH 6U
+#define LPDDR4__PI_TEXCKE_F0__REG DENALI_PI_266
+#define LPDDR4__PI_TEXCKE_F0__FLD LPDDR4__DENALI_PI_266__PI_TEXCKE_F0
+
+#define LPDDR4__DENALI_PI_266__PI_TEXCKE_F1_MASK 0x3F000000U
+#define LPDDR4__DENALI_PI_266__PI_TEXCKE_F1_SHIFT 24U
+#define LPDDR4__DENALI_PI_266__PI_TEXCKE_F1_WIDTH 6U
+#define LPDDR4__PI_TEXCKE_F1__REG DENALI_PI_266
+#define LPDDR4__PI_TEXCKE_F1__FLD LPDDR4__DENALI_PI_266__PI_TEXCKE_F1
+
+#define LPDDR4__DENALI_PI_267_READ_MASK 0x00FFFF3FU
+#define LPDDR4__DENALI_PI_267_WRITE_MASK 0x00FFFF3FU
+#define LPDDR4__DENALI_PI_267__PI_TEXCKE_F2_MASK 0x0000003FU
+#define LPDDR4__DENALI_PI_267__PI_TEXCKE_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_267__PI_TEXCKE_F2_WIDTH 6U
+#define LPDDR4__PI_TEXCKE_F2__REG DENALI_PI_267
+#define LPDDR4__PI_TEXCKE_F2__FLD LPDDR4__DENALI_PI_267__PI_TEXCKE_F2
+
+#define LPDDR4__DENALI_PI_267__PI_TDLL_F0_MASK 0x00FFFF00U
+#define LPDDR4__DENALI_PI_267__PI_TDLL_F0_SHIFT 8U
+#define LPDDR4__DENALI_PI_267__PI_TDLL_F0_WIDTH 16U
+#define LPDDR4__PI_TDLL_F0__REG DENALI_PI_267
+#define LPDDR4__PI_TDLL_F0__FLD LPDDR4__DENALI_PI_267__PI_TDLL_F0
+
+#define LPDDR4__DENALI_PI_268_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_268_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_268__PI_TDLL_F1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PI_268__PI_TDLL_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_268__PI_TDLL_F1_WIDTH 16U
+#define LPDDR4__PI_TDLL_F1__REG DENALI_PI_268
+#define LPDDR4__PI_TDLL_F1__FLD LPDDR4__DENALI_PI_268__PI_TDLL_F1
+
+#define LPDDR4__DENALI_PI_268__PI_TDLL_F2_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_PI_268__PI_TDLL_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_268__PI_TDLL_F2_WIDTH 16U
+#define LPDDR4__PI_TDLL_F2__REG DENALI_PI_268
+#define LPDDR4__PI_TDLL_F2__FLD LPDDR4__DENALI_PI_268__PI_TDLL_F2
+
+#define LPDDR4__DENALI_PI_269_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_269_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_269__PI_TCKSRX_F0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_269__PI_TCKSRX_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_269__PI_TCKSRX_F0_WIDTH 8U
+#define LPDDR4__PI_TCKSRX_F0__REG DENALI_PI_269
+#define LPDDR4__PI_TCKSRX_F0__FLD LPDDR4__DENALI_PI_269__PI_TCKSRX_F0
+
+#define LPDDR4__DENALI_PI_269__PI_TCKSRE_F0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_269__PI_TCKSRE_F0_SHIFT 8U
+#define LPDDR4__DENALI_PI_269__PI_TCKSRE_F0_WIDTH 8U
+#define LPDDR4__PI_TCKSRE_F0__REG DENALI_PI_269
+#define LPDDR4__PI_TCKSRE_F0__FLD LPDDR4__DENALI_PI_269__PI_TCKSRE_F0
+
+#define LPDDR4__DENALI_PI_269__PI_TCKSRX_F1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_269__PI_TCKSRX_F1_SHIFT 16U
+#define LPDDR4__DENALI_PI_269__PI_TCKSRX_F1_WIDTH 8U
+#define LPDDR4__PI_TCKSRX_F1__REG DENALI_PI_269
+#define LPDDR4__PI_TCKSRX_F1__FLD LPDDR4__DENALI_PI_269__PI_TCKSRX_F1
+
+#define LPDDR4__DENALI_PI_269__PI_TCKSRE_F1_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_269__PI_TCKSRE_F1_SHIFT 24U
+#define LPDDR4__DENALI_PI_269__PI_TCKSRE_F1_WIDTH 8U
+#define LPDDR4__PI_TCKSRE_F1__REG DENALI_PI_269
+#define LPDDR4__PI_TCKSRE_F1__FLD LPDDR4__DENALI_PI_269__PI_TCKSRE_F1
+
+#define LPDDR4__DENALI_PI_270_READ_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PI_270_WRITE_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PI_270__PI_TCKSRX_F2_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_270__PI_TCKSRX_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_270__PI_TCKSRX_F2_WIDTH 8U
+#define LPDDR4__PI_TCKSRX_F2__REG DENALI_PI_270
+#define LPDDR4__PI_TCKSRX_F2__FLD LPDDR4__DENALI_PI_270__PI_TCKSRX_F2
+
+#define LPDDR4__DENALI_PI_270__PI_TCKSRE_F2_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_270__PI_TCKSRE_F2_SHIFT 8U
+#define LPDDR4__DENALI_PI_270__PI_TCKSRE_F2_WIDTH 8U
+#define LPDDR4__PI_TCKSRE_F2__REG DENALI_PI_270
+#define LPDDR4__PI_TCKSRE_F2__FLD LPDDR4__DENALI_PI_270__PI_TCKSRE_F2
+
+#define LPDDR4__DENALI_PI_271_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_271_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_271__PI_TINIT_F0_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_271__PI_TINIT_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_271__PI_TINIT_F0_WIDTH 24U
+#define LPDDR4__PI_TINIT_F0__REG DENALI_PI_271
+#define LPDDR4__PI_TINIT_F0__FLD LPDDR4__DENALI_PI_271__PI_TINIT_F0
+
+#define LPDDR4__DENALI_PI_272_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_272_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_272__PI_TINIT3_F0_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_272__PI_TINIT3_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_272__PI_TINIT3_F0_WIDTH 24U
+#define LPDDR4__PI_TINIT3_F0__REG DENALI_PI_272
+#define LPDDR4__PI_TINIT3_F0__FLD LPDDR4__DENALI_PI_272__PI_TINIT3_F0
+
+#define LPDDR4__DENALI_PI_273_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_273_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_273__PI_TINIT4_F0_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_273__PI_TINIT4_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_273__PI_TINIT4_F0_WIDTH 24U
+#define LPDDR4__PI_TINIT4_F0__REG DENALI_PI_273
+#define LPDDR4__PI_TINIT4_F0__FLD LPDDR4__DENALI_PI_273__PI_TINIT4_F0
+
+#define LPDDR4__DENALI_PI_274_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_274_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_274__PI_TINIT5_F0_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_274__PI_TINIT5_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_274__PI_TINIT5_F0_WIDTH 24U
+#define LPDDR4__PI_TINIT5_F0__REG DENALI_PI_274
+#define LPDDR4__PI_TINIT5_F0__FLD LPDDR4__DENALI_PI_274__PI_TINIT5_F0
+
+#define LPDDR4__DENALI_PI_275_READ_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PI_275_WRITE_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PI_275__PI_TXSNR_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PI_275__PI_TXSNR_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_275__PI_TXSNR_F0_WIDTH 16U
+#define LPDDR4__PI_TXSNR_F0__REG DENALI_PI_275
+#define LPDDR4__PI_TXSNR_F0__FLD LPDDR4__DENALI_PI_275__PI_TXSNR_F0
+
+#define LPDDR4__DENALI_PI_276_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_276_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_276__PI_TINIT_F1_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_276__PI_TINIT_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_276__PI_TINIT_F1_WIDTH 24U
+#define LPDDR4__PI_TINIT_F1__REG DENALI_PI_276
+#define LPDDR4__PI_TINIT_F1__FLD LPDDR4__DENALI_PI_276__PI_TINIT_F1
+
+#define LPDDR4__DENALI_PI_277_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_277_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_277__PI_TINIT3_F1_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_277__PI_TINIT3_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_277__PI_TINIT3_F1_WIDTH 24U
+#define LPDDR4__PI_TINIT3_F1__REG DENALI_PI_277
+#define LPDDR4__PI_TINIT3_F1__FLD LPDDR4__DENALI_PI_277__PI_TINIT3_F1
+
+#define LPDDR4__DENALI_PI_278_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_278_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_278__PI_TINIT4_F1_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_278__PI_TINIT4_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_278__PI_TINIT4_F1_WIDTH 24U
+#define LPDDR4__PI_TINIT4_F1__REG DENALI_PI_278
+#define LPDDR4__PI_TINIT4_F1__FLD LPDDR4__DENALI_PI_278__PI_TINIT4_F1
+
+#define LPDDR4__DENALI_PI_279_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_279_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_279__PI_TINIT5_F1_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_279__PI_TINIT5_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_279__PI_TINIT5_F1_WIDTH 24U
+#define LPDDR4__PI_TINIT5_F1__REG DENALI_PI_279
+#define LPDDR4__PI_TINIT5_F1__FLD LPDDR4__DENALI_PI_279__PI_TINIT5_F1
+
+#define LPDDR4__DENALI_PI_280_READ_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PI_280_WRITE_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PI_280__PI_TXSNR_F1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PI_280__PI_TXSNR_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_280__PI_TXSNR_F1_WIDTH 16U
+#define LPDDR4__PI_TXSNR_F1__REG DENALI_PI_280
+#define LPDDR4__PI_TXSNR_F1__FLD LPDDR4__DENALI_PI_280__PI_TXSNR_F1
+
+#define LPDDR4__DENALI_PI_281_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_281_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_281__PI_TINIT_F2_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_281__PI_TINIT_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_281__PI_TINIT_F2_WIDTH 24U
+#define LPDDR4__PI_TINIT_F2__REG DENALI_PI_281
+#define LPDDR4__PI_TINIT_F2__FLD LPDDR4__DENALI_PI_281__PI_TINIT_F2
+
+#define LPDDR4__DENALI_PI_282_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_282_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_282__PI_TINIT3_F2_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_282__PI_TINIT3_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_282__PI_TINIT3_F2_WIDTH 24U
+#define LPDDR4__PI_TINIT3_F2__REG DENALI_PI_282
+#define LPDDR4__PI_TINIT3_F2__FLD LPDDR4__DENALI_PI_282__PI_TINIT3_F2
+
+#define LPDDR4__DENALI_PI_283_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_283_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_283__PI_TINIT4_F2_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_283__PI_TINIT4_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_283__PI_TINIT4_F2_WIDTH 24U
+#define LPDDR4__PI_TINIT4_F2__REG DENALI_PI_283
+#define LPDDR4__PI_TINIT4_F2__FLD LPDDR4__DENALI_PI_283__PI_TINIT4_F2
+
+#define LPDDR4__DENALI_PI_284_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_284_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_284__PI_TINIT5_F2_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_284__PI_TINIT5_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_284__PI_TINIT5_F2_WIDTH 24U
+#define LPDDR4__PI_TINIT5_F2__REG DENALI_PI_284
+#define LPDDR4__PI_TINIT5_F2__FLD LPDDR4__DENALI_PI_284__PI_TINIT5_F2
+
+#define LPDDR4__DENALI_PI_285_READ_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PI_285_WRITE_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PI_285__PI_TXSNR_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PI_285__PI_TXSNR_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_285__PI_TXSNR_F2_WIDTH 16U
+#define LPDDR4__PI_TXSNR_F2__REG DENALI_PI_285
+#define LPDDR4__PI_TXSNR_F2__FLD LPDDR4__DENALI_PI_285__PI_TXSNR_F2
+
+#define LPDDR4__DENALI_PI_285__PI_RESERVED54_MASK 0x0FFF0000U
+#define LPDDR4__DENALI_PI_285__PI_RESERVED54_SHIFT 16U
+#define LPDDR4__DENALI_PI_285__PI_RESERVED54_WIDTH 12U
+#define LPDDR4__PI_RESERVED54__REG DENALI_PI_285
+#define LPDDR4__PI_RESERVED54__FLD LPDDR4__DENALI_PI_285__PI_RESERVED54
+
+#define LPDDR4__DENALI_PI_286_READ_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_PI_286_WRITE_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_PI_286__PI_RESERVED55_MASK 0x00000FFFU
+#define LPDDR4__DENALI_PI_286__PI_RESERVED55_SHIFT 0U
+#define LPDDR4__DENALI_PI_286__PI_RESERVED55_WIDTH 12U
+#define LPDDR4__PI_RESERVED55__REG DENALI_PI_286
+#define LPDDR4__PI_RESERVED55__FLD LPDDR4__DENALI_PI_286__PI_RESERVED55
+
+#define LPDDR4__DENALI_PI_286__PI_TZQCAL_F0_MASK 0x0FFF0000U
+#define LPDDR4__DENALI_PI_286__PI_TZQCAL_F0_SHIFT 16U
+#define LPDDR4__DENALI_PI_286__PI_TZQCAL_F0_WIDTH 12U
+#define LPDDR4__PI_TZQCAL_F0__REG DENALI_PI_286
+#define LPDDR4__PI_TZQCAL_F0__FLD LPDDR4__DENALI_PI_286__PI_TZQCAL_F0
+
+#define LPDDR4__DENALI_PI_287_READ_MASK 0x000FFF7FU
+#define LPDDR4__DENALI_PI_287_WRITE_MASK 0x000FFF7FU
+#define LPDDR4__DENALI_PI_287__PI_TZQLAT_F0_MASK 0x0000007FU
+#define LPDDR4__DENALI_PI_287__PI_TZQLAT_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_287__PI_TZQLAT_F0_WIDTH 7U
+#define LPDDR4__PI_TZQLAT_F0__REG DENALI_PI_287
+#define LPDDR4__PI_TZQLAT_F0__FLD LPDDR4__DENALI_PI_287__PI_TZQLAT_F0
+
+#define LPDDR4__DENALI_PI_287__PI_RESERVED56_MASK 0x000FFF00U
+#define LPDDR4__DENALI_PI_287__PI_RESERVED56_SHIFT 8U
+#define LPDDR4__DENALI_PI_287__PI_RESERVED56_WIDTH 12U
+#define LPDDR4__PI_RESERVED56__REG DENALI_PI_287
+#define LPDDR4__PI_RESERVED56__FLD LPDDR4__DENALI_PI_287__PI_RESERVED56
+
+#define LPDDR4__DENALI_PI_288_READ_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_PI_288_WRITE_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_PI_288__PI_RESERVED57_MASK 0x00000FFFU
+#define LPDDR4__DENALI_PI_288__PI_RESERVED57_SHIFT 0U
+#define LPDDR4__DENALI_PI_288__PI_RESERVED57_WIDTH 12U
+#define LPDDR4__PI_RESERVED57__REG DENALI_PI_288
+#define LPDDR4__PI_RESERVED57__FLD LPDDR4__DENALI_PI_288__PI_RESERVED57
+
+#define LPDDR4__DENALI_PI_288__PI_TZQCAL_F1_MASK 0x0FFF0000U
+#define LPDDR4__DENALI_PI_288__PI_TZQCAL_F1_SHIFT 16U
+#define LPDDR4__DENALI_PI_288__PI_TZQCAL_F1_WIDTH 12U
+#define LPDDR4__PI_TZQCAL_F1__REG DENALI_PI_288
+#define LPDDR4__PI_TZQCAL_F1__FLD LPDDR4__DENALI_PI_288__PI_TZQCAL_F1
+
+#define LPDDR4__DENALI_PI_289_READ_MASK 0x000FFF7FU
+#define LPDDR4__DENALI_PI_289_WRITE_MASK 0x000FFF7FU
+#define LPDDR4__DENALI_PI_289__PI_TZQLAT_F1_MASK 0x0000007FU
+#define LPDDR4__DENALI_PI_289__PI_TZQLAT_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_289__PI_TZQLAT_F1_WIDTH 7U
+#define LPDDR4__PI_TZQLAT_F1__REG DENALI_PI_289
+#define LPDDR4__PI_TZQLAT_F1__FLD LPDDR4__DENALI_PI_289__PI_TZQLAT_F1
+
+#define LPDDR4__DENALI_PI_289__PI_RESERVED58_MASK 0x000FFF00U
+#define LPDDR4__DENALI_PI_289__PI_RESERVED58_SHIFT 8U
+#define LPDDR4__DENALI_PI_289__PI_RESERVED58_WIDTH 12U
+#define LPDDR4__PI_RESERVED58__REG DENALI_PI_289
+#define LPDDR4__PI_RESERVED58__FLD LPDDR4__DENALI_PI_289__PI_RESERVED58
+
+#define LPDDR4__DENALI_PI_290_READ_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_PI_290_WRITE_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_PI_290__PI_RESERVED59_MASK 0x00000FFFU
+#define LPDDR4__DENALI_PI_290__PI_RESERVED59_SHIFT 0U
+#define LPDDR4__DENALI_PI_290__PI_RESERVED59_WIDTH 12U
+#define LPDDR4__PI_RESERVED59__REG DENALI_PI_290
+#define LPDDR4__PI_RESERVED59__FLD LPDDR4__DENALI_PI_290__PI_RESERVED59
+
+#define LPDDR4__DENALI_PI_290__PI_TZQCAL_F2_MASK 0x0FFF0000U
+#define LPDDR4__DENALI_PI_290__PI_TZQCAL_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_290__PI_TZQCAL_F2_WIDTH 12U
+#define LPDDR4__PI_TZQCAL_F2__REG DENALI_PI_290
+#define LPDDR4__PI_TZQCAL_F2__FLD LPDDR4__DENALI_PI_290__PI_TZQCAL_F2
+
+#define LPDDR4__DENALI_PI_291_READ_MASK 0x000FFF7FU
+#define LPDDR4__DENALI_PI_291_WRITE_MASK 0x000FFF7FU
+#define LPDDR4__DENALI_PI_291__PI_TZQLAT_F2_MASK 0x0000007FU
+#define LPDDR4__DENALI_PI_291__PI_TZQLAT_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_291__PI_TZQLAT_F2_WIDTH 7U
+#define LPDDR4__PI_TZQLAT_F2__REG DENALI_PI_291
+#define LPDDR4__PI_TZQLAT_F2__FLD LPDDR4__DENALI_PI_291__PI_TZQLAT_F2
+
+#define LPDDR4__DENALI_PI_291__PI_RESERVED60_MASK 0x000FFF00U
+#define LPDDR4__DENALI_PI_291__PI_RESERVED60_SHIFT 8U
+#define LPDDR4__DENALI_PI_291__PI_RESERVED60_WIDTH 12U
+#define LPDDR4__PI_RESERVED60__REG DENALI_PI_291
+#define LPDDR4__PI_RESERVED60__FLD LPDDR4__DENALI_PI_291__PI_RESERVED60
+
+#define LPDDR4__DENALI_PI_292_READ_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_PI_292_WRITE_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_PI_292__PI_RESERVED61_MASK 0x00000FFFU
+#define LPDDR4__DENALI_PI_292__PI_RESERVED61_SHIFT 0U
+#define LPDDR4__DENALI_PI_292__PI_RESERVED61_WIDTH 12U
+#define LPDDR4__PI_RESERVED61__REG DENALI_PI_292
+#define LPDDR4__PI_RESERVED61__FLD LPDDR4__DENALI_PI_292__PI_RESERVED61
+
+#define LPDDR4__DENALI_PI_292__PI_RESERVED62_MASK 0x0FFF0000U
+#define LPDDR4__DENALI_PI_292__PI_RESERVED62_SHIFT 16U
+#define LPDDR4__DENALI_PI_292__PI_RESERVED62_WIDTH 12U
+#define LPDDR4__PI_RESERVED62__REG DENALI_PI_292
+#define LPDDR4__PI_RESERVED62__FLD LPDDR4__DENALI_PI_292__PI_RESERVED62
+
+#define LPDDR4__DENALI_PI_293_READ_MASK 0x030F0F0FU
+#define LPDDR4__DENALI_PI_293_WRITE_MASK 0x030F0F0FU
+#define LPDDR4__DENALI_PI_293__PI_WDQ_OSC_DELTA_INDEX_F0_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_293__PI_WDQ_OSC_DELTA_INDEX_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_293__PI_WDQ_OSC_DELTA_INDEX_F0_WIDTH 4U
+#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F0__REG DENALI_PI_293
+#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F0__FLD LPDDR4__DENALI_PI_293__PI_WDQ_OSC_DELTA_INDEX_F0
+
+#define LPDDR4__DENALI_PI_293__PI_WDQ_OSC_DELTA_INDEX_F1_MASK 0x00000F00U
+#define LPDDR4__DENALI_PI_293__PI_WDQ_OSC_DELTA_INDEX_F1_SHIFT 8U
+#define LPDDR4__DENALI_PI_293__PI_WDQ_OSC_DELTA_INDEX_F1_WIDTH 4U
+#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F1__REG DENALI_PI_293
+#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F1__FLD LPDDR4__DENALI_PI_293__PI_WDQ_OSC_DELTA_INDEX_F1
+
+#define LPDDR4__DENALI_PI_293__PI_WDQ_OSC_DELTA_INDEX_F2_MASK 0x000F0000U
+#define LPDDR4__DENALI_PI_293__PI_WDQ_OSC_DELTA_INDEX_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_293__PI_WDQ_OSC_DELTA_INDEX_F2_WIDTH 4U
+#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F2__REG DENALI_PI_293
+#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F2__FLD LPDDR4__DENALI_PI_293__PI_WDQ_OSC_DELTA_INDEX_F2
+
+#define LPDDR4__DENALI_PI_293__PI_PREAMBLE_SUPPORT_F0_MASK 0x03000000U
+#define LPDDR4__DENALI_PI_293__PI_PREAMBLE_SUPPORT_F0_SHIFT 24U
+#define LPDDR4__DENALI_PI_293__PI_PREAMBLE_SUPPORT_F0_WIDTH 2U
+#define LPDDR4__PI_PREAMBLE_SUPPORT_F0__REG DENALI_PI_293
+#define LPDDR4__PI_PREAMBLE_SUPPORT_F0__FLD LPDDR4__DENALI_PI_293__PI_PREAMBLE_SUPPORT_F0
+
+#define LPDDR4__DENALI_PI_294_READ_MASK 0x07070303U
+#define LPDDR4__DENALI_PI_294_WRITE_MASK 0x07070303U
+#define LPDDR4__DENALI_PI_294__PI_PREAMBLE_SUPPORT_F1_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_294__PI_PREAMBLE_SUPPORT_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_294__PI_PREAMBLE_SUPPORT_F1_WIDTH 2U
+#define LPDDR4__PI_PREAMBLE_SUPPORT_F1__REG DENALI_PI_294
+#define LPDDR4__PI_PREAMBLE_SUPPORT_F1__FLD LPDDR4__DENALI_PI_294__PI_PREAMBLE_SUPPORT_F1
+
+#define LPDDR4__DENALI_PI_294__PI_PREAMBLE_SUPPORT_F2_MASK 0x00000300U
+#define LPDDR4__DENALI_PI_294__PI_PREAMBLE_SUPPORT_F2_SHIFT 8U
+#define LPDDR4__DENALI_PI_294__PI_PREAMBLE_SUPPORT_F2_WIDTH 2U
+#define LPDDR4__PI_PREAMBLE_SUPPORT_F2__REG DENALI_PI_294
+#define LPDDR4__PI_PREAMBLE_SUPPORT_F2__FLD LPDDR4__DENALI_PI_294__PI_PREAMBLE_SUPPORT_F2
+
+#define LPDDR4__DENALI_PI_294__PI_MEMDATA_RATIO_0_MASK 0x00070000U
+#define LPDDR4__DENALI_PI_294__PI_MEMDATA_RATIO_0_SHIFT 16U
+#define LPDDR4__DENALI_PI_294__PI_MEMDATA_RATIO_0_WIDTH 3U
+#define LPDDR4__PI_MEMDATA_RATIO_0__REG DENALI_PI_294
+#define LPDDR4__PI_MEMDATA_RATIO_0__FLD LPDDR4__DENALI_PI_294__PI_MEMDATA_RATIO_0
+
+#define LPDDR4__DENALI_PI_294__PI_MEMDATA_RATIO_1_MASK 0x07000000U
+#define LPDDR4__DENALI_PI_294__PI_MEMDATA_RATIO_1_SHIFT 24U
+#define LPDDR4__DENALI_PI_294__PI_MEMDATA_RATIO_1_WIDTH 3U
+#define LPDDR4__PI_MEMDATA_RATIO_1__REG DENALI_PI_294
+#define LPDDR4__PI_MEMDATA_RATIO_1__FLD LPDDR4__DENALI_PI_294__PI_MEMDATA_RATIO_1
+
+#define LPDDR4__DENALI_PI_295_READ_MASK 0x0F0F0707U
+#define LPDDR4__DENALI_PI_295_WRITE_MASK 0x0F0F0707U
+#define LPDDR4__DENALI_PI_295__PI_MEMDATA_RATIO_2_MASK 0x00000007U
+#define LPDDR4__DENALI_PI_295__PI_MEMDATA_RATIO_2_SHIFT 0U
+#define LPDDR4__DENALI_PI_295__PI_MEMDATA_RATIO_2_WIDTH 3U
+#define LPDDR4__PI_MEMDATA_RATIO_2__REG DENALI_PI_295
+#define LPDDR4__PI_MEMDATA_RATIO_2__FLD LPDDR4__DENALI_PI_295__PI_MEMDATA_RATIO_2
+
+#define LPDDR4__DENALI_PI_295__PI_MEMDATA_RATIO_3_MASK 0x00000700U
+#define LPDDR4__DENALI_PI_295__PI_MEMDATA_RATIO_3_SHIFT 8U
+#define LPDDR4__DENALI_PI_295__PI_MEMDATA_RATIO_3_WIDTH 3U
+#define LPDDR4__PI_MEMDATA_RATIO_3__REG DENALI_PI_295
+#define LPDDR4__PI_MEMDATA_RATIO_3__FLD LPDDR4__DENALI_PI_295__PI_MEMDATA_RATIO_3
+
+#define LPDDR4__DENALI_PI_295__PI_ODT_RD_MAP_CS0_MASK 0x000F0000U
+#define LPDDR4__DENALI_PI_295__PI_ODT_RD_MAP_CS0_SHIFT 16U
+#define LPDDR4__DENALI_PI_295__PI_ODT_RD_MAP_CS0_WIDTH 4U
+#define LPDDR4__PI_ODT_RD_MAP_CS0__REG DENALI_PI_295
+#define LPDDR4__PI_ODT_RD_MAP_CS0__FLD LPDDR4__DENALI_PI_295__PI_ODT_RD_MAP_CS0
+
+#define LPDDR4__DENALI_PI_295__PI_ODT_WR_MAP_CS0_MASK 0x0F000000U
+#define LPDDR4__DENALI_PI_295__PI_ODT_WR_MAP_CS0_SHIFT 24U
+#define LPDDR4__DENALI_PI_295__PI_ODT_WR_MAP_CS0_WIDTH 4U
+#define LPDDR4__PI_ODT_WR_MAP_CS0__REG DENALI_PI_295
+#define LPDDR4__PI_ODT_WR_MAP_CS0__FLD LPDDR4__DENALI_PI_295__PI_ODT_WR_MAP_CS0
+
+#define LPDDR4__DENALI_PI_296_READ_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_296_WRITE_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_296__PI_ODT_RD_MAP_CS1_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_296__PI_ODT_RD_MAP_CS1_SHIFT 0U
+#define LPDDR4__DENALI_PI_296__PI_ODT_RD_MAP_CS1_WIDTH 4U
+#define LPDDR4__PI_ODT_RD_MAP_CS1__REG DENALI_PI_296
+#define LPDDR4__PI_ODT_RD_MAP_CS1__FLD LPDDR4__DENALI_PI_296__PI_ODT_RD_MAP_CS1
+
+#define LPDDR4__DENALI_PI_296__PI_ODT_WR_MAP_CS1_MASK 0x00000F00U
+#define LPDDR4__DENALI_PI_296__PI_ODT_WR_MAP_CS1_SHIFT 8U
+#define LPDDR4__DENALI_PI_296__PI_ODT_WR_MAP_CS1_WIDTH 4U
+#define LPDDR4__PI_ODT_WR_MAP_CS1__REG DENALI_PI_296
+#define LPDDR4__PI_ODT_WR_MAP_CS1__FLD LPDDR4__DENALI_PI_296__PI_ODT_WR_MAP_CS1
+
+#define LPDDR4__DENALI_PI_296__PI_ODT_RD_MAP_CS2_MASK 0x000F0000U
+#define LPDDR4__DENALI_PI_296__PI_ODT_RD_MAP_CS2_SHIFT 16U
+#define LPDDR4__DENALI_PI_296__PI_ODT_RD_MAP_CS2_WIDTH 4U
+#define LPDDR4__PI_ODT_RD_MAP_CS2__REG DENALI_PI_296
+#define LPDDR4__PI_ODT_RD_MAP_CS2__FLD LPDDR4__DENALI_PI_296__PI_ODT_RD_MAP_CS2
+
+#define LPDDR4__DENALI_PI_296__PI_ODT_WR_MAP_CS2_MASK 0x0F000000U
+#define LPDDR4__DENALI_PI_296__PI_ODT_WR_MAP_CS2_SHIFT 24U
+#define LPDDR4__DENALI_PI_296__PI_ODT_WR_MAP_CS2_WIDTH 4U
+#define LPDDR4__PI_ODT_WR_MAP_CS2__REG DENALI_PI_296
+#define LPDDR4__PI_ODT_WR_MAP_CS2__FLD LPDDR4__DENALI_PI_296__PI_ODT_WR_MAP_CS2
+
+#define LPDDR4__DENALI_PI_297_READ_MASK 0x7F7F0F0FU
+#define LPDDR4__DENALI_PI_297_WRITE_MASK 0x7F7F0F0FU
+#define LPDDR4__DENALI_PI_297__PI_ODT_RD_MAP_CS3_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_297__PI_ODT_RD_MAP_CS3_SHIFT 0U
+#define LPDDR4__DENALI_PI_297__PI_ODT_RD_MAP_CS3_WIDTH 4U
+#define LPDDR4__PI_ODT_RD_MAP_CS3__REG DENALI_PI_297
+#define LPDDR4__PI_ODT_RD_MAP_CS3__FLD LPDDR4__DENALI_PI_297__PI_ODT_RD_MAP_CS3
+
+#define LPDDR4__DENALI_PI_297__PI_ODT_WR_MAP_CS3_MASK 0x00000F00U
+#define LPDDR4__DENALI_PI_297__PI_ODT_WR_MAP_CS3_SHIFT 8U
+#define LPDDR4__DENALI_PI_297__PI_ODT_WR_MAP_CS3_WIDTH 4U
+#define LPDDR4__PI_ODT_WR_MAP_CS3__REG DENALI_PI_297
+#define LPDDR4__PI_ODT_WR_MAP_CS3__FLD LPDDR4__DENALI_PI_297__PI_ODT_WR_MAP_CS3
+
+#define LPDDR4__DENALI_PI_297__PI_VREF_VAL_DEV0_0_MASK 0x007F0000U
+#define LPDDR4__DENALI_PI_297__PI_VREF_VAL_DEV0_0_SHIFT 16U
+#define LPDDR4__DENALI_PI_297__PI_VREF_VAL_DEV0_0_WIDTH 7U
+#define LPDDR4__PI_VREF_VAL_DEV0_0__REG DENALI_PI_297
+#define LPDDR4__PI_VREF_VAL_DEV0_0__FLD LPDDR4__DENALI_PI_297__PI_VREF_VAL_DEV0_0
+
+#define LPDDR4__DENALI_PI_297__PI_VREF_VAL_DEV0_1_MASK 0x7F000000U
+#define LPDDR4__DENALI_PI_297__PI_VREF_VAL_DEV0_1_SHIFT 24U
+#define LPDDR4__DENALI_PI_297__PI_VREF_VAL_DEV0_1_WIDTH 7U
+#define LPDDR4__PI_VREF_VAL_DEV0_1__REG DENALI_PI_297
+#define LPDDR4__PI_VREF_VAL_DEV0_1__FLD LPDDR4__DENALI_PI_297__PI_VREF_VAL_DEV0_1
+
+#define LPDDR4__DENALI_PI_298_READ_MASK 0x7F7F7F7FU
+#define LPDDR4__DENALI_PI_298_WRITE_MASK 0x7F7F7F7FU
+#define LPDDR4__DENALI_PI_298__PI_VREF_VAL_DEV0_2_MASK 0x0000007FU
+#define LPDDR4__DENALI_PI_298__PI_VREF_VAL_DEV0_2_SHIFT 0U
+#define LPDDR4__DENALI_PI_298__PI_VREF_VAL_DEV0_2_WIDTH 7U
+#define LPDDR4__PI_VREF_VAL_DEV0_2__REG DENALI_PI_298
+#define LPDDR4__PI_VREF_VAL_DEV0_2__FLD LPDDR4__DENALI_PI_298__PI_VREF_VAL_DEV0_2
+
+#define LPDDR4__DENALI_PI_298__PI_VREF_VAL_DEV0_3_MASK 0x00007F00U
+#define LPDDR4__DENALI_PI_298__PI_VREF_VAL_DEV0_3_SHIFT 8U
+#define LPDDR4__DENALI_PI_298__PI_VREF_VAL_DEV0_3_WIDTH 7U
+#define LPDDR4__PI_VREF_VAL_DEV0_3__REG DENALI_PI_298
+#define LPDDR4__PI_VREF_VAL_DEV0_3__FLD LPDDR4__DENALI_PI_298__PI_VREF_VAL_DEV0_3
+
+#define LPDDR4__DENALI_PI_298__PI_VREF_VAL_DEV1_0_MASK 0x007F0000U
+#define LPDDR4__DENALI_PI_298__PI_VREF_VAL_DEV1_0_SHIFT 16U
+#define LPDDR4__DENALI_PI_298__PI_VREF_VAL_DEV1_0_WIDTH 7U
+#define LPDDR4__PI_VREF_VAL_DEV1_0__REG DENALI_PI_298
+#define LPDDR4__PI_VREF_VAL_DEV1_0__FLD LPDDR4__DENALI_PI_298__PI_VREF_VAL_DEV1_0
+
+#define LPDDR4__DENALI_PI_298__PI_VREF_VAL_DEV1_1_MASK 0x7F000000U
+#define LPDDR4__DENALI_PI_298__PI_VREF_VAL_DEV1_1_SHIFT 24U
+#define LPDDR4__DENALI_PI_298__PI_VREF_VAL_DEV1_1_WIDTH 7U
+#define LPDDR4__PI_VREF_VAL_DEV1_1__REG DENALI_PI_298
+#define LPDDR4__PI_VREF_VAL_DEV1_1__FLD LPDDR4__DENALI_PI_298__PI_VREF_VAL_DEV1_1
+
+#define LPDDR4__DENALI_PI_299_READ_MASK 0x7F7F7F7FU
+#define LPDDR4__DENALI_PI_299_WRITE_MASK 0x7F7F7F7FU
+#define LPDDR4__DENALI_PI_299__PI_VREF_VAL_DEV1_2_MASK 0x0000007FU
+#define LPDDR4__DENALI_PI_299__PI_VREF_VAL_DEV1_2_SHIFT 0U
+#define LPDDR4__DENALI_PI_299__PI_VREF_VAL_DEV1_2_WIDTH 7U
+#define LPDDR4__PI_VREF_VAL_DEV1_2__REG DENALI_PI_299
+#define LPDDR4__PI_VREF_VAL_DEV1_2__FLD LPDDR4__DENALI_PI_299__PI_VREF_VAL_DEV1_2
+
+#define LPDDR4__DENALI_PI_299__PI_VREF_VAL_DEV1_3_MASK 0x00007F00U
+#define LPDDR4__DENALI_PI_299__PI_VREF_VAL_DEV1_3_SHIFT 8U
+#define LPDDR4__DENALI_PI_299__PI_VREF_VAL_DEV1_3_WIDTH 7U
+#define LPDDR4__PI_VREF_VAL_DEV1_3__REG DENALI_PI_299
+#define LPDDR4__PI_VREF_VAL_DEV1_3__FLD LPDDR4__DENALI_PI_299__PI_VREF_VAL_DEV1_3
+
+#define LPDDR4__DENALI_PI_299__PI_VREF_VAL_DEV2_0_MASK 0x007F0000U
+#define LPDDR4__DENALI_PI_299__PI_VREF_VAL_DEV2_0_SHIFT 16U
+#define LPDDR4__DENALI_PI_299__PI_VREF_VAL_DEV2_0_WIDTH 7U
+#define LPDDR4__PI_VREF_VAL_DEV2_0__REG DENALI_PI_299
+#define LPDDR4__PI_VREF_VAL_DEV2_0__FLD LPDDR4__DENALI_PI_299__PI_VREF_VAL_DEV2_0
+
+#define LPDDR4__DENALI_PI_299__PI_VREF_VAL_DEV2_1_MASK 0x7F000000U
+#define LPDDR4__DENALI_PI_299__PI_VREF_VAL_DEV2_1_SHIFT 24U
+#define LPDDR4__DENALI_PI_299__PI_VREF_VAL_DEV2_1_WIDTH 7U
+#define LPDDR4__PI_VREF_VAL_DEV2_1__REG DENALI_PI_299
+#define LPDDR4__PI_VREF_VAL_DEV2_1__FLD LPDDR4__DENALI_PI_299__PI_VREF_VAL_DEV2_1
+
+#define LPDDR4__DENALI_PI_300_READ_MASK 0x7F7F7F7FU
+#define LPDDR4__DENALI_PI_300_WRITE_MASK 0x7F7F7F7FU
+#define LPDDR4__DENALI_PI_300__PI_VREF_VAL_DEV2_2_MASK 0x0000007FU
+#define LPDDR4__DENALI_PI_300__PI_VREF_VAL_DEV2_2_SHIFT 0U
+#define LPDDR4__DENALI_PI_300__PI_VREF_VAL_DEV2_2_WIDTH 7U
+#define LPDDR4__PI_VREF_VAL_DEV2_2__REG DENALI_PI_300
+#define LPDDR4__PI_VREF_VAL_DEV2_2__FLD LPDDR4__DENALI_PI_300__PI_VREF_VAL_DEV2_2
+
+#define LPDDR4__DENALI_PI_300__PI_VREF_VAL_DEV2_3_MASK 0x00007F00U
+#define LPDDR4__DENALI_PI_300__PI_VREF_VAL_DEV2_3_SHIFT 8U
+#define LPDDR4__DENALI_PI_300__PI_VREF_VAL_DEV2_3_WIDTH 7U
+#define LPDDR4__PI_VREF_VAL_DEV2_3__REG DENALI_PI_300
+#define LPDDR4__PI_VREF_VAL_DEV2_3__FLD LPDDR4__DENALI_PI_300__PI_VREF_VAL_DEV2_3
+
+#define LPDDR4__DENALI_PI_300__PI_VREF_VAL_DEV3_0_MASK 0x007F0000U
+#define LPDDR4__DENALI_PI_300__PI_VREF_VAL_DEV3_0_SHIFT 16U
+#define LPDDR4__DENALI_PI_300__PI_VREF_VAL_DEV3_0_WIDTH 7U
+#define LPDDR4__PI_VREF_VAL_DEV3_0__REG DENALI_PI_300
+#define LPDDR4__PI_VREF_VAL_DEV3_0__FLD LPDDR4__DENALI_PI_300__PI_VREF_VAL_DEV3_0
+
+#define LPDDR4__DENALI_PI_300__PI_VREF_VAL_DEV3_1_MASK 0x7F000000U
+#define LPDDR4__DENALI_PI_300__PI_VREF_VAL_DEV3_1_SHIFT 24U
+#define LPDDR4__DENALI_PI_300__PI_VREF_VAL_DEV3_1_WIDTH 7U
+#define LPDDR4__PI_VREF_VAL_DEV3_1__REG DENALI_PI_300
+#define LPDDR4__PI_VREF_VAL_DEV3_1__FLD LPDDR4__DENALI_PI_300__PI_VREF_VAL_DEV3_1
+
+#define LPDDR4__DENALI_PI_301_READ_MASK 0x03037F7FU
+#define LPDDR4__DENALI_PI_301_WRITE_MASK 0x03037F7FU
+#define LPDDR4__DENALI_PI_301__PI_VREF_VAL_DEV3_2_MASK 0x0000007FU
+#define LPDDR4__DENALI_PI_301__PI_VREF_VAL_DEV3_2_SHIFT 0U
+#define LPDDR4__DENALI_PI_301__PI_VREF_VAL_DEV3_2_WIDTH 7U
+#define LPDDR4__PI_VREF_VAL_DEV3_2__REG DENALI_PI_301
+#define LPDDR4__PI_VREF_VAL_DEV3_2__FLD LPDDR4__DENALI_PI_301__PI_VREF_VAL_DEV3_2
+
+#define LPDDR4__DENALI_PI_301__PI_VREF_VAL_DEV3_3_MASK 0x00007F00U
+#define LPDDR4__DENALI_PI_301__PI_VREF_VAL_DEV3_3_SHIFT 8U
+#define LPDDR4__DENALI_PI_301__PI_VREF_VAL_DEV3_3_WIDTH 7U
+#define LPDDR4__PI_VREF_VAL_DEV3_3__REG DENALI_PI_301
+#define LPDDR4__PI_VREF_VAL_DEV3_3__FLD LPDDR4__DENALI_PI_301__PI_VREF_VAL_DEV3_3
+
+#define LPDDR4__DENALI_PI_301__PI_SLICE_PER_DEV_0_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_301__PI_SLICE_PER_DEV_0_SHIFT 16U
+#define LPDDR4__DENALI_PI_301__PI_SLICE_PER_DEV_0_WIDTH 2U
+#define LPDDR4__PI_SLICE_PER_DEV_0__REG DENALI_PI_301
+#define LPDDR4__PI_SLICE_PER_DEV_0__FLD LPDDR4__DENALI_PI_301__PI_SLICE_PER_DEV_0
+
+#define LPDDR4__DENALI_PI_301__PI_SLICE_PER_DEV_1_MASK 0x03000000U
+#define LPDDR4__DENALI_PI_301__PI_SLICE_PER_DEV_1_SHIFT 24U
+#define LPDDR4__DENALI_PI_301__PI_SLICE_PER_DEV_1_WIDTH 2U
+#define LPDDR4__PI_SLICE_PER_DEV_1__REG DENALI_PI_301
+#define LPDDR4__PI_SLICE_PER_DEV_1__FLD LPDDR4__DENALI_PI_301__PI_SLICE_PER_DEV_1
+
+#define LPDDR4__DENALI_PI_302_READ_MASK 0x3F3F0303U
+#define LPDDR4__DENALI_PI_302_WRITE_MASK 0x3F3F0303U
+#define LPDDR4__DENALI_PI_302__PI_SLICE_PER_DEV_2_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_302__PI_SLICE_PER_DEV_2_SHIFT 0U
+#define LPDDR4__DENALI_PI_302__PI_SLICE_PER_DEV_2_WIDTH 2U
+#define LPDDR4__PI_SLICE_PER_DEV_2__REG DENALI_PI_302
+#define LPDDR4__PI_SLICE_PER_DEV_2__FLD LPDDR4__DENALI_PI_302__PI_SLICE_PER_DEV_2
+
+#define LPDDR4__DENALI_PI_302__PI_SLICE_PER_DEV_3_MASK 0x00000300U
+#define LPDDR4__DENALI_PI_302__PI_SLICE_PER_DEV_3_SHIFT 8U
+#define LPDDR4__DENALI_PI_302__PI_SLICE_PER_DEV_3_WIDTH 2U
+#define LPDDR4__PI_SLICE_PER_DEV_3__REG DENALI_PI_302
+#define LPDDR4__PI_SLICE_PER_DEV_3__FLD LPDDR4__DENALI_PI_302__PI_SLICE_PER_DEV_3
+
+#define LPDDR4__DENALI_PI_302__PI_MR6_VREF_0_0_MASK 0x003F0000U
+#define LPDDR4__DENALI_PI_302__PI_MR6_VREF_0_0_SHIFT 16U
+#define LPDDR4__DENALI_PI_302__PI_MR6_VREF_0_0_WIDTH 6U
+#define LPDDR4__PI_MR6_VREF_0_0__REG DENALI_PI_302
+#define LPDDR4__PI_MR6_VREF_0_0__FLD LPDDR4__DENALI_PI_302__PI_MR6_VREF_0_0
+
+#define LPDDR4__DENALI_PI_302__PI_MR6_VREF_0_1_MASK 0x3F000000U
+#define LPDDR4__DENALI_PI_302__PI_MR6_VREF_0_1_SHIFT 24U
+#define LPDDR4__DENALI_PI_302__PI_MR6_VREF_0_1_WIDTH 6U
+#define LPDDR4__PI_MR6_VREF_0_1__REG DENALI_PI_302
+#define LPDDR4__PI_MR6_VREF_0_1__FLD LPDDR4__DENALI_PI_302__PI_MR6_VREF_0_1
+
+#define LPDDR4__DENALI_PI_303_READ_MASK 0x3F3F3F3FU
+#define LPDDR4__DENALI_PI_303_WRITE_MASK 0x3F3F3F3FU
+#define LPDDR4__DENALI_PI_303__PI_MR6_VREF_0_2_MASK 0x0000003FU
+#define LPDDR4__DENALI_PI_303__PI_MR6_VREF_0_2_SHIFT 0U
+#define LPDDR4__DENALI_PI_303__PI_MR6_VREF_0_2_WIDTH 6U
+#define LPDDR4__PI_MR6_VREF_0_2__REG DENALI_PI_303
+#define LPDDR4__PI_MR6_VREF_0_2__FLD LPDDR4__DENALI_PI_303__PI_MR6_VREF_0_2
+
+#define LPDDR4__DENALI_PI_303__PI_MR6_VREF_0_3_MASK 0x00003F00U
+#define LPDDR4__DENALI_PI_303__PI_MR6_VREF_0_3_SHIFT 8U
+#define LPDDR4__DENALI_PI_303__PI_MR6_VREF_0_3_WIDTH 6U
+#define LPDDR4__PI_MR6_VREF_0_3__REG DENALI_PI_303
+#define LPDDR4__PI_MR6_VREF_0_3__FLD LPDDR4__DENALI_PI_303__PI_MR6_VREF_0_3
+
+#define LPDDR4__DENALI_PI_303__PI_MR6_VREF_1_0_MASK 0x003F0000U
+#define LPDDR4__DENALI_PI_303__PI_MR6_VREF_1_0_SHIFT 16U
+#define LPDDR4__DENALI_PI_303__PI_MR6_VREF_1_0_WIDTH 6U
+#define LPDDR4__PI_MR6_VREF_1_0__REG DENALI_PI_303
+#define LPDDR4__PI_MR6_VREF_1_0__FLD LPDDR4__DENALI_PI_303__PI_MR6_VREF_1_0
+
+#define LPDDR4__DENALI_PI_303__PI_MR6_VREF_1_1_MASK 0x3F000000U
+#define LPDDR4__DENALI_PI_303__PI_MR6_VREF_1_1_SHIFT 24U
+#define LPDDR4__DENALI_PI_303__PI_MR6_VREF_1_1_WIDTH 6U
+#define LPDDR4__PI_MR6_VREF_1_1__REG DENALI_PI_303
+#define LPDDR4__PI_MR6_VREF_1_1__FLD LPDDR4__DENALI_PI_303__PI_MR6_VREF_1_1
+
+#define LPDDR4__DENALI_PI_304_READ_MASK 0x3F3F3F3FU
+#define LPDDR4__DENALI_PI_304_WRITE_MASK 0x3F3F3F3FU
+#define LPDDR4__DENALI_PI_304__PI_MR6_VREF_1_2_MASK 0x0000003FU
+#define LPDDR4__DENALI_PI_304__PI_MR6_VREF_1_2_SHIFT 0U
+#define LPDDR4__DENALI_PI_304__PI_MR6_VREF_1_2_WIDTH 6U
+#define LPDDR4__PI_MR6_VREF_1_2__REG DENALI_PI_304
+#define LPDDR4__PI_MR6_VREF_1_2__FLD LPDDR4__DENALI_PI_304__PI_MR6_VREF_1_2
+
+#define LPDDR4__DENALI_PI_304__PI_MR6_VREF_1_3_MASK 0x00003F00U
+#define LPDDR4__DENALI_PI_304__PI_MR6_VREF_1_3_SHIFT 8U
+#define LPDDR4__DENALI_PI_304__PI_MR6_VREF_1_3_WIDTH 6U
+#define LPDDR4__PI_MR6_VREF_1_3__REG DENALI_PI_304
+#define LPDDR4__PI_MR6_VREF_1_3__FLD LPDDR4__DENALI_PI_304__PI_MR6_VREF_1_3
+
+#define LPDDR4__DENALI_PI_304__PI_MR6_VREF_2_0_MASK 0x003F0000U
+#define LPDDR4__DENALI_PI_304__PI_MR6_VREF_2_0_SHIFT 16U
+#define LPDDR4__DENALI_PI_304__PI_MR6_VREF_2_0_WIDTH 6U
+#define LPDDR4__PI_MR6_VREF_2_0__REG DENALI_PI_304
+#define LPDDR4__PI_MR6_VREF_2_0__FLD LPDDR4__DENALI_PI_304__PI_MR6_VREF_2_0
+
+#define LPDDR4__DENALI_PI_304__PI_MR6_VREF_2_1_MASK 0x3F000000U
+#define LPDDR4__DENALI_PI_304__PI_MR6_VREF_2_1_SHIFT 24U
+#define LPDDR4__DENALI_PI_304__PI_MR6_VREF_2_1_WIDTH 6U
+#define LPDDR4__PI_MR6_VREF_2_1__REG DENALI_PI_304
+#define LPDDR4__PI_MR6_VREF_2_1__FLD LPDDR4__DENALI_PI_304__PI_MR6_VREF_2_1
+
+#define LPDDR4__DENALI_PI_305_READ_MASK 0x3F3F3F3FU
+#define LPDDR4__DENALI_PI_305_WRITE_MASK 0x3F3F3F3FU
+#define LPDDR4__DENALI_PI_305__PI_MR6_VREF_2_2_MASK 0x0000003FU
+#define LPDDR4__DENALI_PI_305__PI_MR6_VREF_2_2_SHIFT 0U
+#define LPDDR4__DENALI_PI_305__PI_MR6_VREF_2_2_WIDTH 6U
+#define LPDDR4__PI_MR6_VREF_2_2__REG DENALI_PI_305
+#define LPDDR4__PI_MR6_VREF_2_2__FLD LPDDR4__DENALI_PI_305__PI_MR6_VREF_2_2
+
+#define LPDDR4__DENALI_PI_305__PI_MR6_VREF_2_3_MASK 0x00003F00U
+#define LPDDR4__DENALI_PI_305__PI_MR6_VREF_2_3_SHIFT 8U
+#define LPDDR4__DENALI_PI_305__PI_MR6_VREF_2_3_WIDTH 6U
+#define LPDDR4__PI_MR6_VREF_2_3__REG DENALI_PI_305
+#define LPDDR4__PI_MR6_VREF_2_3__FLD LPDDR4__DENALI_PI_305__PI_MR6_VREF_2_3
+
+#define LPDDR4__DENALI_PI_305__PI_MR6_VREF_3_0_MASK 0x003F0000U
+#define LPDDR4__DENALI_PI_305__PI_MR6_VREF_3_0_SHIFT 16U
+#define LPDDR4__DENALI_PI_305__PI_MR6_VREF_3_0_WIDTH 6U
+#define LPDDR4__PI_MR6_VREF_3_0__REG DENALI_PI_305
+#define LPDDR4__PI_MR6_VREF_3_0__FLD LPDDR4__DENALI_PI_305__PI_MR6_VREF_3_0
+
+#define LPDDR4__DENALI_PI_305__PI_MR6_VREF_3_1_MASK 0x3F000000U
+#define LPDDR4__DENALI_PI_305__PI_MR6_VREF_3_1_SHIFT 24U
+#define LPDDR4__DENALI_PI_305__PI_MR6_VREF_3_1_WIDTH 6U
+#define LPDDR4__PI_MR6_VREF_3_1__REG DENALI_PI_305
+#define LPDDR4__PI_MR6_VREF_3_1__FLD LPDDR4__DENALI_PI_305__PI_MR6_VREF_3_1
+
+#define LPDDR4__DENALI_PI_306_READ_MASK 0xFFFF3F3FU
+#define LPDDR4__DENALI_PI_306_WRITE_MASK 0xFFFF3F3FU
+#define LPDDR4__DENALI_PI_306__PI_MR6_VREF_3_2_MASK 0x0000003FU
+#define LPDDR4__DENALI_PI_306__PI_MR6_VREF_3_2_SHIFT 0U
+#define LPDDR4__DENALI_PI_306__PI_MR6_VREF_3_2_WIDTH 6U
+#define LPDDR4__PI_MR6_VREF_3_2__REG DENALI_PI_306
+#define LPDDR4__PI_MR6_VREF_3_2__FLD LPDDR4__DENALI_PI_306__PI_MR6_VREF_3_2
+
+#define LPDDR4__DENALI_PI_306__PI_MR6_VREF_3_3_MASK 0x00003F00U
+#define LPDDR4__DENALI_PI_306__PI_MR6_VREF_3_3_SHIFT 8U
+#define LPDDR4__DENALI_PI_306__PI_MR6_VREF_3_3_WIDTH 6U
+#define LPDDR4__PI_MR6_VREF_3_3__REG DENALI_PI_306
+#define LPDDR4__PI_MR6_VREF_3_3__FLD LPDDR4__DENALI_PI_306__PI_MR6_VREF_3_3
+
+#define LPDDR4__DENALI_PI_306__PI_MR13_DATA_0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_306__PI_MR13_DATA_0_SHIFT 16U
+#define LPDDR4__DENALI_PI_306__PI_MR13_DATA_0_WIDTH 8U
+#define LPDDR4__PI_MR13_DATA_0__REG DENALI_PI_306
+#define LPDDR4__PI_MR13_DATA_0__FLD LPDDR4__DENALI_PI_306__PI_MR13_DATA_0
+
+#define LPDDR4__DENALI_PI_306__PI_MR15_DATA_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_306__PI_MR15_DATA_0_SHIFT 24U
+#define LPDDR4__DENALI_PI_306__PI_MR15_DATA_0_WIDTH 8U
+#define LPDDR4__PI_MR15_DATA_0__REG DENALI_PI_306
+#define LPDDR4__PI_MR15_DATA_0__FLD LPDDR4__DENALI_PI_306__PI_MR15_DATA_0
+
+#define LPDDR4__DENALI_PI_307_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_307_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_307__PI_MR16_DATA_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_307__PI_MR16_DATA_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_307__PI_MR16_DATA_0_WIDTH 8U
+#define LPDDR4__PI_MR16_DATA_0__REG DENALI_PI_307
+#define LPDDR4__PI_MR16_DATA_0__FLD LPDDR4__DENALI_PI_307__PI_MR16_DATA_0
+
+#define LPDDR4__DENALI_PI_307__PI_MR17_DATA_0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_307__PI_MR17_DATA_0_SHIFT 8U
+#define LPDDR4__DENALI_PI_307__PI_MR17_DATA_0_WIDTH 8U
+#define LPDDR4__PI_MR17_DATA_0__REG DENALI_PI_307
+#define LPDDR4__PI_MR17_DATA_0__FLD LPDDR4__DENALI_PI_307__PI_MR17_DATA_0
+
+#define LPDDR4__DENALI_PI_307__PI_MR20_DATA_0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_307__PI_MR20_DATA_0_SHIFT 16U
+#define LPDDR4__DENALI_PI_307__PI_MR20_DATA_0_WIDTH 8U
+#define LPDDR4__PI_MR20_DATA_0__REG DENALI_PI_307
+#define LPDDR4__PI_MR20_DATA_0__FLD LPDDR4__DENALI_PI_307__PI_MR20_DATA_0
+
+#define LPDDR4__DENALI_PI_308_READ_MASK 0xFF01FFFFU
+#define LPDDR4__DENALI_PI_308_WRITE_MASK 0xFF01FFFFU
+#define LPDDR4__DENALI_PI_308__PI_MR32_DATA_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_308__PI_MR32_DATA_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_308__PI_MR32_DATA_0_WIDTH 17U
+#define LPDDR4__PI_MR32_DATA_0__REG DENALI_PI_308
+#define LPDDR4__PI_MR32_DATA_0__FLD LPDDR4__DENALI_PI_308__PI_MR32_DATA_0
+
+#define LPDDR4__DENALI_PI_308__PI_MR40_DATA_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_308__PI_MR40_DATA_0_SHIFT 24U
+#define LPDDR4__DENALI_PI_308__PI_MR40_DATA_0_WIDTH 8U
+#define LPDDR4__PI_MR40_DATA_0__REG DENALI_PI_308
+#define LPDDR4__PI_MR40_DATA_0__FLD LPDDR4__DENALI_PI_308__PI_MR40_DATA_0
+
+#define LPDDR4__DENALI_PI_309_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_309_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_309__PI_MR13_DATA_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_309__PI_MR13_DATA_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_309__PI_MR13_DATA_1_WIDTH 8U
+#define LPDDR4__PI_MR13_DATA_1__REG DENALI_PI_309
+#define LPDDR4__PI_MR13_DATA_1__FLD LPDDR4__DENALI_PI_309__PI_MR13_DATA_1
+
+#define LPDDR4__DENALI_PI_309__PI_MR15_DATA_1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_309__PI_MR15_DATA_1_SHIFT 8U
+#define LPDDR4__DENALI_PI_309__PI_MR15_DATA_1_WIDTH 8U
+#define LPDDR4__PI_MR15_DATA_1__REG DENALI_PI_309
+#define LPDDR4__PI_MR15_DATA_1__FLD LPDDR4__DENALI_PI_309__PI_MR15_DATA_1
+
+#define LPDDR4__DENALI_PI_309__PI_MR16_DATA_1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_309__PI_MR16_DATA_1_SHIFT 16U
+#define LPDDR4__DENALI_PI_309__PI_MR16_DATA_1_WIDTH 8U
+#define LPDDR4__PI_MR16_DATA_1__REG DENALI_PI_309
+#define LPDDR4__PI_MR16_DATA_1__FLD LPDDR4__DENALI_PI_309__PI_MR16_DATA_1
+
+#define LPDDR4__DENALI_PI_309__PI_MR17_DATA_1_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_309__PI_MR17_DATA_1_SHIFT 24U
+#define LPDDR4__DENALI_PI_309__PI_MR17_DATA_1_WIDTH 8U
+#define LPDDR4__PI_MR17_DATA_1__REG DENALI_PI_309
+#define LPDDR4__PI_MR17_DATA_1__FLD LPDDR4__DENALI_PI_309__PI_MR17_DATA_1
+
+#define LPDDR4__DENALI_PI_310_READ_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_PI_310_WRITE_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_PI_310__PI_MR20_DATA_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_310__PI_MR20_DATA_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_310__PI_MR20_DATA_1_WIDTH 8U
+#define LPDDR4__PI_MR20_DATA_1__REG DENALI_PI_310
+#define LPDDR4__PI_MR20_DATA_1__FLD LPDDR4__DENALI_PI_310__PI_MR20_DATA_1
+
+#define LPDDR4__DENALI_PI_310__PI_MR32_DATA_1_MASK 0x01FFFF00U
+#define LPDDR4__DENALI_PI_310__PI_MR32_DATA_1_SHIFT 8U
+#define LPDDR4__DENALI_PI_310__PI_MR32_DATA_1_WIDTH 17U
+#define LPDDR4__PI_MR32_DATA_1__REG DENALI_PI_310
+#define LPDDR4__PI_MR32_DATA_1__FLD LPDDR4__DENALI_PI_310__PI_MR32_DATA_1
+
+#define LPDDR4__DENALI_PI_311_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_311_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_311__PI_MR40_DATA_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_311__PI_MR40_DATA_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_311__PI_MR40_DATA_1_WIDTH 8U
+#define LPDDR4__PI_MR40_DATA_1__REG DENALI_PI_311
+#define LPDDR4__PI_MR40_DATA_1__FLD LPDDR4__DENALI_PI_311__PI_MR40_DATA_1
+
+#define LPDDR4__DENALI_PI_311__PI_MR13_DATA_2_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_311__PI_MR13_DATA_2_SHIFT 8U
+#define LPDDR4__DENALI_PI_311__PI_MR13_DATA_2_WIDTH 8U
+#define LPDDR4__PI_MR13_DATA_2__REG DENALI_PI_311
+#define LPDDR4__PI_MR13_DATA_2__FLD LPDDR4__DENALI_PI_311__PI_MR13_DATA_2
+
+#define LPDDR4__DENALI_PI_311__PI_MR15_DATA_2_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_311__PI_MR15_DATA_2_SHIFT 16U
+#define LPDDR4__DENALI_PI_311__PI_MR15_DATA_2_WIDTH 8U
+#define LPDDR4__PI_MR15_DATA_2__REG DENALI_PI_311
+#define LPDDR4__PI_MR15_DATA_2__FLD LPDDR4__DENALI_PI_311__PI_MR15_DATA_2
+
+#define LPDDR4__DENALI_PI_311__PI_MR16_DATA_2_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_311__PI_MR16_DATA_2_SHIFT 24U
+#define LPDDR4__DENALI_PI_311__PI_MR16_DATA_2_WIDTH 8U
+#define LPDDR4__PI_MR16_DATA_2__REG DENALI_PI_311
+#define LPDDR4__PI_MR16_DATA_2__FLD LPDDR4__DENALI_PI_311__PI_MR16_DATA_2
+
+#define LPDDR4__DENALI_PI_312_READ_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PI_312_WRITE_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PI_312__PI_MR17_DATA_2_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_312__PI_MR17_DATA_2_SHIFT 0U
+#define LPDDR4__DENALI_PI_312__PI_MR17_DATA_2_WIDTH 8U
+#define LPDDR4__PI_MR17_DATA_2__REG DENALI_PI_312
+#define LPDDR4__PI_MR17_DATA_2__FLD LPDDR4__DENALI_PI_312__PI_MR17_DATA_2
+
+#define LPDDR4__DENALI_PI_312__PI_MR20_DATA_2_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_312__PI_MR20_DATA_2_SHIFT 8U
+#define LPDDR4__DENALI_PI_312__PI_MR20_DATA_2_WIDTH 8U
+#define LPDDR4__PI_MR20_DATA_2__REG DENALI_PI_312
+#define LPDDR4__PI_MR20_DATA_2__FLD LPDDR4__DENALI_PI_312__PI_MR20_DATA_2
+
+#define LPDDR4__DENALI_PI_313_READ_MASK 0xFF01FFFFU
+#define LPDDR4__DENALI_PI_313_WRITE_MASK 0xFF01FFFFU
+#define LPDDR4__DENALI_PI_313__PI_MR32_DATA_2_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_313__PI_MR32_DATA_2_SHIFT 0U
+#define LPDDR4__DENALI_PI_313__PI_MR32_DATA_2_WIDTH 17U
+#define LPDDR4__PI_MR32_DATA_2__REG DENALI_PI_313
+#define LPDDR4__PI_MR32_DATA_2__FLD LPDDR4__DENALI_PI_313__PI_MR32_DATA_2
+
+#define LPDDR4__DENALI_PI_313__PI_MR40_DATA_2_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_313__PI_MR40_DATA_2_SHIFT 24U
+#define LPDDR4__DENALI_PI_313__PI_MR40_DATA_2_WIDTH 8U
+#define LPDDR4__PI_MR40_DATA_2__REG DENALI_PI_313
+#define LPDDR4__PI_MR40_DATA_2__FLD LPDDR4__DENALI_PI_313__PI_MR40_DATA_2
+
+#define LPDDR4__DENALI_PI_314_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_314_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_314__PI_MR13_DATA_3_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_314__PI_MR13_DATA_3_SHIFT 0U
+#define LPDDR4__DENALI_PI_314__PI_MR13_DATA_3_WIDTH 8U
+#define LPDDR4__PI_MR13_DATA_3__REG DENALI_PI_314
+#define LPDDR4__PI_MR13_DATA_3__FLD LPDDR4__DENALI_PI_314__PI_MR13_DATA_3
+
+#define LPDDR4__DENALI_PI_314__PI_MR15_DATA_3_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_314__PI_MR15_DATA_3_SHIFT 8U
+#define LPDDR4__DENALI_PI_314__PI_MR15_DATA_3_WIDTH 8U
+#define LPDDR4__PI_MR15_DATA_3__REG DENALI_PI_314
+#define LPDDR4__PI_MR15_DATA_3__FLD LPDDR4__DENALI_PI_314__PI_MR15_DATA_3
+
+#define LPDDR4__DENALI_PI_314__PI_MR16_DATA_3_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_314__PI_MR16_DATA_3_SHIFT 16U
+#define LPDDR4__DENALI_PI_314__PI_MR16_DATA_3_WIDTH 8U
+#define LPDDR4__PI_MR16_DATA_3__REG DENALI_PI_314
+#define LPDDR4__PI_MR16_DATA_3__FLD LPDDR4__DENALI_PI_314__PI_MR16_DATA_3
+
+#define LPDDR4__DENALI_PI_314__PI_MR17_DATA_3_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_314__PI_MR17_DATA_3_SHIFT 24U
+#define LPDDR4__DENALI_PI_314__PI_MR17_DATA_3_WIDTH 8U
+#define LPDDR4__PI_MR17_DATA_3__REG DENALI_PI_314
+#define LPDDR4__PI_MR17_DATA_3__FLD LPDDR4__DENALI_PI_314__PI_MR17_DATA_3
+
+#define LPDDR4__DENALI_PI_315_READ_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_PI_315_WRITE_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_PI_315__PI_MR20_DATA_3_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_315__PI_MR20_DATA_3_SHIFT 0U
+#define LPDDR4__DENALI_PI_315__PI_MR20_DATA_3_WIDTH 8U
+#define LPDDR4__PI_MR20_DATA_3__REG DENALI_PI_315
+#define LPDDR4__PI_MR20_DATA_3__FLD LPDDR4__DENALI_PI_315__PI_MR20_DATA_3
+
+#define LPDDR4__DENALI_PI_315__PI_MR32_DATA_3_MASK 0x01FFFF00U
+#define LPDDR4__DENALI_PI_315__PI_MR32_DATA_3_SHIFT 8U
+#define LPDDR4__DENALI_PI_315__PI_MR32_DATA_3_WIDTH 17U
+#define LPDDR4__PI_MR32_DATA_3__REG DENALI_PI_315
+#define LPDDR4__PI_MR32_DATA_3__FLD LPDDR4__DENALI_PI_315__PI_MR32_DATA_3
+
+#define LPDDR4__DENALI_PI_316_READ_MASK 0x1F1F1FFFU
+#define LPDDR4__DENALI_PI_316_WRITE_MASK 0x1F1F1FFFU
+#define LPDDR4__DENALI_PI_316__PI_MR40_DATA_3_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_316__PI_MR40_DATA_3_SHIFT 0U
+#define LPDDR4__DENALI_PI_316__PI_MR40_DATA_3_WIDTH 8U
+#define LPDDR4__PI_MR40_DATA_3__REG DENALI_PI_316
+#define LPDDR4__PI_MR40_DATA_3__FLD LPDDR4__DENALI_PI_316__PI_MR40_DATA_3
+
+#define LPDDR4__DENALI_PI_316__PI_CKE_MUX_0_MASK 0x00001F00U
+#define LPDDR4__DENALI_PI_316__PI_CKE_MUX_0_SHIFT 8U
+#define LPDDR4__DENALI_PI_316__PI_CKE_MUX_0_WIDTH 5U
+#define LPDDR4__PI_CKE_MUX_0__REG DENALI_PI_316
+#define LPDDR4__PI_CKE_MUX_0__FLD LPDDR4__DENALI_PI_316__PI_CKE_MUX_0
+
+#define LPDDR4__DENALI_PI_316__PI_CKE_MUX_1_MASK 0x001F0000U
+#define LPDDR4__DENALI_PI_316__PI_CKE_MUX_1_SHIFT 16U
+#define LPDDR4__DENALI_PI_316__PI_CKE_MUX_1_WIDTH 5U
+#define LPDDR4__PI_CKE_MUX_1__REG DENALI_PI_316
+#define LPDDR4__PI_CKE_MUX_1__FLD LPDDR4__DENALI_PI_316__PI_CKE_MUX_1
+
+#define LPDDR4__DENALI_PI_316__PI_CKE_MUX_2_MASK 0x1F000000U
+#define LPDDR4__DENALI_PI_316__PI_CKE_MUX_2_SHIFT 24U
+#define LPDDR4__DENALI_PI_316__PI_CKE_MUX_2_WIDTH 5U
+#define LPDDR4__PI_CKE_MUX_2__REG DENALI_PI_316
+#define LPDDR4__PI_CKE_MUX_2__FLD LPDDR4__DENALI_PI_316__PI_CKE_MUX_2
+
+#define LPDDR4__DENALI_PI_317_READ_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_PI_317_WRITE_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_PI_317__PI_CKE_MUX_3_MASK 0x0000001FU
+#define LPDDR4__DENALI_PI_317__PI_CKE_MUX_3_SHIFT 0U
+#define LPDDR4__DENALI_PI_317__PI_CKE_MUX_3_WIDTH 5U
+#define LPDDR4__PI_CKE_MUX_3__REG DENALI_PI_317
+#define LPDDR4__PI_CKE_MUX_3__FLD LPDDR4__DENALI_PI_317__PI_CKE_MUX_3
+
+#define LPDDR4__DENALI_PI_317__PI_CS_MUX_0_MASK 0x00001F00U
+#define LPDDR4__DENALI_PI_317__PI_CS_MUX_0_SHIFT 8U
+#define LPDDR4__DENALI_PI_317__PI_CS_MUX_0_WIDTH 5U
+#define LPDDR4__PI_CS_MUX_0__REG DENALI_PI_317
+#define LPDDR4__PI_CS_MUX_0__FLD LPDDR4__DENALI_PI_317__PI_CS_MUX_0
+
+#define LPDDR4__DENALI_PI_317__PI_CS_MUX_1_MASK 0x001F0000U
+#define LPDDR4__DENALI_PI_317__PI_CS_MUX_1_SHIFT 16U
+#define LPDDR4__DENALI_PI_317__PI_CS_MUX_1_WIDTH 5U
+#define LPDDR4__PI_CS_MUX_1__REG DENALI_PI_317
+#define LPDDR4__PI_CS_MUX_1__FLD LPDDR4__DENALI_PI_317__PI_CS_MUX_1
+
+#define LPDDR4__DENALI_PI_317__PI_CS_MUX_2_MASK 0x1F000000U
+#define LPDDR4__DENALI_PI_317__PI_CS_MUX_2_SHIFT 24U
+#define LPDDR4__DENALI_PI_317__PI_CS_MUX_2_WIDTH 5U
+#define LPDDR4__PI_CS_MUX_2__REG DENALI_PI_317
+#define LPDDR4__PI_CS_MUX_2__FLD LPDDR4__DENALI_PI_317__PI_CS_MUX_2
+
+#define LPDDR4__DENALI_PI_318_READ_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_PI_318_WRITE_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_PI_318__PI_CS_MUX_3_MASK 0x0000001FU
+#define LPDDR4__DENALI_PI_318__PI_CS_MUX_3_SHIFT 0U
+#define LPDDR4__DENALI_PI_318__PI_CS_MUX_3_WIDTH 5U
+#define LPDDR4__PI_CS_MUX_3__REG DENALI_PI_318
+#define LPDDR4__PI_CS_MUX_3__FLD LPDDR4__DENALI_PI_318__PI_CS_MUX_3
+
+#define LPDDR4__DENALI_PI_318__PI_ODT_MUX_0_MASK 0x00001F00U
+#define LPDDR4__DENALI_PI_318__PI_ODT_MUX_0_SHIFT 8U
+#define LPDDR4__DENALI_PI_318__PI_ODT_MUX_0_WIDTH 5U
+#define LPDDR4__PI_ODT_MUX_0__REG DENALI_PI_318
+#define LPDDR4__PI_ODT_MUX_0__FLD LPDDR4__DENALI_PI_318__PI_ODT_MUX_0
+
+#define LPDDR4__DENALI_PI_318__PI_ODT_MUX_1_MASK 0x001F0000U
+#define LPDDR4__DENALI_PI_318__PI_ODT_MUX_1_SHIFT 16U
+#define LPDDR4__DENALI_PI_318__PI_ODT_MUX_1_WIDTH 5U
+#define LPDDR4__PI_ODT_MUX_1__REG DENALI_PI_318
+#define LPDDR4__PI_ODT_MUX_1__FLD LPDDR4__DENALI_PI_318__PI_ODT_MUX_1
+
+#define LPDDR4__DENALI_PI_318__PI_ODT_MUX_2_MASK 0x1F000000U
+#define LPDDR4__DENALI_PI_318__PI_ODT_MUX_2_SHIFT 24U
+#define LPDDR4__DENALI_PI_318__PI_ODT_MUX_2_WIDTH 5U
+#define LPDDR4__PI_ODT_MUX_2__REG DENALI_PI_318
+#define LPDDR4__PI_ODT_MUX_2__FLD LPDDR4__DENALI_PI_318__PI_ODT_MUX_2
+
+#define LPDDR4__DENALI_PI_319_READ_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_PI_319_WRITE_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_PI_319__PI_ODT_MUX_3_MASK 0x0000001FU
+#define LPDDR4__DENALI_PI_319__PI_ODT_MUX_3_SHIFT 0U
+#define LPDDR4__DENALI_PI_319__PI_ODT_MUX_3_WIDTH 5U
+#define LPDDR4__PI_ODT_MUX_3__REG DENALI_PI_319
+#define LPDDR4__PI_ODT_MUX_3__FLD LPDDR4__DENALI_PI_319__PI_ODT_MUX_3
+
+#define LPDDR4__DENALI_PI_319__PI_RESET_N_MUX_0_MASK 0x00001F00U
+#define LPDDR4__DENALI_PI_319__PI_RESET_N_MUX_0_SHIFT 8U
+#define LPDDR4__DENALI_PI_319__PI_RESET_N_MUX_0_WIDTH 5U
+#define LPDDR4__PI_RESET_N_MUX_0__REG DENALI_PI_319
+#define LPDDR4__PI_RESET_N_MUX_0__FLD LPDDR4__DENALI_PI_319__PI_RESET_N_MUX_0
+
+#define LPDDR4__DENALI_PI_319__PI_RESET_N_MUX_1_MASK 0x001F0000U
+#define LPDDR4__DENALI_PI_319__PI_RESET_N_MUX_1_SHIFT 16U
+#define LPDDR4__DENALI_PI_319__PI_RESET_N_MUX_1_WIDTH 5U
+#define LPDDR4__PI_RESET_N_MUX_1__REG DENALI_PI_319
+#define LPDDR4__PI_RESET_N_MUX_1__FLD LPDDR4__DENALI_PI_319__PI_RESET_N_MUX_1
+
+#define LPDDR4__DENALI_PI_319__PI_RESET_N_MUX_2_MASK 0x1F000000U
+#define LPDDR4__DENALI_PI_319__PI_RESET_N_MUX_2_SHIFT 24U
+#define LPDDR4__DENALI_PI_319__PI_RESET_N_MUX_2_WIDTH 5U
+#define LPDDR4__PI_RESET_N_MUX_2__REG DENALI_PI_319
+#define LPDDR4__PI_RESET_N_MUX_2__FLD LPDDR4__DENALI_PI_319__PI_RESET_N_MUX_2
+
+#define LPDDR4__DENALI_PI_320_READ_MASK 0x01FFFF1FU
+#define LPDDR4__DENALI_PI_320_WRITE_MASK 0x01FFFF1FU
+#define LPDDR4__DENALI_PI_320__PI_RESET_N_MUX_3_MASK 0x0000001FU
+#define LPDDR4__DENALI_PI_320__PI_RESET_N_MUX_3_SHIFT 0U
+#define LPDDR4__DENALI_PI_320__PI_RESET_N_MUX_3_WIDTH 5U
+#define LPDDR4__PI_RESET_N_MUX_3__REG DENALI_PI_320
+#define LPDDR4__PI_RESET_N_MUX_3__FLD LPDDR4__DENALI_PI_320__PI_RESET_N_MUX_3
+
+#define LPDDR4__DENALI_PI_320__PI_MRSINGLE_DATA_0_MASK 0x01FFFF00U
+#define LPDDR4__DENALI_PI_320__PI_MRSINGLE_DATA_0_SHIFT 8U
+#define LPDDR4__DENALI_PI_320__PI_MRSINGLE_DATA_0_WIDTH 17U
+#define LPDDR4__PI_MRSINGLE_DATA_0__REG DENALI_PI_320
+#define LPDDR4__PI_MRSINGLE_DATA_0__FLD LPDDR4__DENALI_PI_320__PI_MRSINGLE_DATA_0
+
+#define LPDDR4__DENALI_PI_321_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_321_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_321__PI_MRSINGLE_DATA_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_321__PI_MRSINGLE_DATA_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_321__PI_MRSINGLE_DATA_1_WIDTH 17U
+#define LPDDR4__PI_MRSINGLE_DATA_1__REG DENALI_PI_321
+#define LPDDR4__PI_MRSINGLE_DATA_1__FLD LPDDR4__DENALI_PI_321__PI_MRSINGLE_DATA_1
+
+#define LPDDR4__DENALI_PI_322_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_322_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_322__PI_MRSINGLE_DATA_2_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_322__PI_MRSINGLE_DATA_2_SHIFT 0U
+#define LPDDR4__DENALI_PI_322__PI_MRSINGLE_DATA_2_WIDTH 17U
+#define LPDDR4__PI_MRSINGLE_DATA_2__REG DENALI_PI_322
+#define LPDDR4__PI_MRSINGLE_DATA_2__FLD LPDDR4__DENALI_PI_322__PI_MRSINGLE_DATA_2
+
+#define LPDDR4__DENALI_PI_323_READ_MASK 0x0F01FFFFU
+#define LPDDR4__DENALI_PI_323_WRITE_MASK 0x0F01FFFFU
+#define LPDDR4__DENALI_PI_323__PI_MRSINGLE_DATA_3_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_323__PI_MRSINGLE_DATA_3_SHIFT 0U
+#define LPDDR4__DENALI_PI_323__PI_MRSINGLE_DATA_3_WIDTH 17U
+#define LPDDR4__PI_MRSINGLE_DATA_3__REG DENALI_PI_323
+#define LPDDR4__PI_MRSINGLE_DATA_3__FLD LPDDR4__DENALI_PI_323__PI_MRSINGLE_DATA_3
+
+#define LPDDR4__DENALI_PI_323__PI_ZQ_CAL_START_MAP_0_MASK 0x0F000000U
+#define LPDDR4__DENALI_PI_323__PI_ZQ_CAL_START_MAP_0_SHIFT 24U
+#define LPDDR4__DENALI_PI_323__PI_ZQ_CAL_START_MAP_0_WIDTH 4U
+#define LPDDR4__PI_ZQ_CAL_START_MAP_0__REG DENALI_PI_323
+#define LPDDR4__PI_ZQ_CAL_START_MAP_0__FLD LPDDR4__DENALI_PI_323__PI_ZQ_CAL_START_MAP_0
+
+#define LPDDR4__DENALI_PI_324_READ_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_324_WRITE_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_324__PI_ZQ_CAL_LATCH_MAP_0_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_324__PI_ZQ_CAL_LATCH_MAP_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_324__PI_ZQ_CAL_LATCH_MAP_0_WIDTH 4U
+#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_0__REG DENALI_PI_324
+#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_0__FLD LPDDR4__DENALI_PI_324__PI_ZQ_CAL_LATCH_MAP_0
+
+#define LPDDR4__DENALI_PI_324__PI_ZQ_CAL_START_MAP_1_MASK 0x00000F00U
+#define LPDDR4__DENALI_PI_324__PI_ZQ_CAL_START_MAP_1_SHIFT 8U
+#define LPDDR4__DENALI_PI_324__PI_ZQ_CAL_START_MAP_1_WIDTH 4U
+#define LPDDR4__PI_ZQ_CAL_START_MAP_1__REG DENALI_PI_324
+#define LPDDR4__PI_ZQ_CAL_START_MAP_1__FLD LPDDR4__DENALI_PI_324__PI_ZQ_CAL_START_MAP_1
+
+#define LPDDR4__DENALI_PI_324__PI_ZQ_CAL_LATCH_MAP_1_MASK 0x000F0000U
+#define LPDDR4__DENALI_PI_324__PI_ZQ_CAL_LATCH_MAP_1_SHIFT 16U
+#define LPDDR4__DENALI_PI_324__PI_ZQ_CAL_LATCH_MAP_1_WIDTH 4U
+#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_1__REG DENALI_PI_324
+#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_1__FLD LPDDR4__DENALI_PI_324__PI_ZQ_CAL_LATCH_MAP_1
+
+#define LPDDR4__DENALI_PI_324__PI_ZQ_CAL_START_MAP_2_MASK 0x0F000000U
+#define LPDDR4__DENALI_PI_324__PI_ZQ_CAL_START_MAP_2_SHIFT 24U
+#define LPDDR4__DENALI_PI_324__PI_ZQ_CAL_START_MAP_2_WIDTH 4U
+#define LPDDR4__PI_ZQ_CAL_START_MAP_2__REG DENALI_PI_324
+#define LPDDR4__PI_ZQ_CAL_START_MAP_2__FLD LPDDR4__DENALI_PI_324__PI_ZQ_CAL_START_MAP_2
+
+#define LPDDR4__DENALI_PI_325_READ_MASK 0x000F0F0FU
+#define LPDDR4__DENALI_PI_325_WRITE_MASK 0x000F0F0FU
+#define LPDDR4__DENALI_PI_325__PI_ZQ_CAL_LATCH_MAP_2_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_325__PI_ZQ_CAL_LATCH_MAP_2_SHIFT 0U
+#define LPDDR4__DENALI_PI_325__PI_ZQ_CAL_LATCH_MAP_2_WIDTH 4U
+#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_2__REG DENALI_PI_325
+#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_2__FLD LPDDR4__DENALI_PI_325__PI_ZQ_CAL_LATCH_MAP_2
+
+#define LPDDR4__DENALI_PI_325__PI_ZQ_CAL_START_MAP_3_MASK 0x00000F00U
+#define LPDDR4__DENALI_PI_325__PI_ZQ_CAL_START_MAP_3_SHIFT 8U
+#define LPDDR4__DENALI_PI_325__PI_ZQ_CAL_START_MAP_3_WIDTH 4U
+#define LPDDR4__PI_ZQ_CAL_START_MAP_3__REG DENALI_PI_325
+#define LPDDR4__PI_ZQ_CAL_START_MAP_3__FLD LPDDR4__DENALI_PI_325__PI_ZQ_CAL_START_MAP_3
+
+#define LPDDR4__DENALI_PI_325__PI_ZQ_CAL_LATCH_MAP_3_MASK 0x000F0000U
+#define LPDDR4__DENALI_PI_325__PI_ZQ_CAL_LATCH_MAP_3_SHIFT 16U
+#define LPDDR4__DENALI_PI_325__PI_ZQ_CAL_LATCH_MAP_3_WIDTH 4U
+#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_3__REG DENALI_PI_325
+#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_3__FLD LPDDR4__DENALI_PI_325__PI_ZQ_CAL_LATCH_MAP_3
+
+#define LPDDR4__DENALI_PI_326_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_326_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_326__PI_DQS_OSC_BASE_VALUE_0_0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PI_326__PI_DQS_OSC_BASE_VALUE_0_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_326__PI_DQS_OSC_BASE_VALUE_0_0_WIDTH 16U
+#define LPDDR4__PI_DQS_OSC_BASE_VALUE_0_0__REG DENALI_PI_326
+#define LPDDR4__PI_DQS_OSC_BASE_VALUE_0_0__FLD LPDDR4__DENALI_PI_326__PI_DQS_OSC_BASE_VALUE_0_0
+
+#define LPDDR4__DENALI_PI_326__PI_DQS_OSC_BASE_VALUE_1_0_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_PI_326__PI_DQS_OSC_BASE_VALUE_1_0_SHIFT 16U
+#define LPDDR4__DENALI_PI_326__PI_DQS_OSC_BASE_VALUE_1_0_WIDTH 16U
+#define LPDDR4__PI_DQS_OSC_BASE_VALUE_1_0__REG DENALI_PI_326
+#define LPDDR4__PI_DQS_OSC_BASE_VALUE_1_0__FLD LPDDR4__DENALI_PI_326__PI_DQS_OSC_BASE_VALUE_1_0
+
+#define LPDDR4__DENALI_PI_327_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_327_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_327__PI_DQS_OSC_BASE_VALUE_0_1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PI_327__PI_DQS_OSC_BASE_VALUE_0_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_327__PI_DQS_OSC_BASE_VALUE_0_1_WIDTH 16U
+#define LPDDR4__PI_DQS_OSC_BASE_VALUE_0_1__REG DENALI_PI_327
+#define LPDDR4__PI_DQS_OSC_BASE_VALUE_0_1__FLD LPDDR4__DENALI_PI_327__PI_DQS_OSC_BASE_VALUE_0_1
+
+#define LPDDR4__DENALI_PI_327__PI_DQS_OSC_BASE_VALUE_1_1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_PI_327__PI_DQS_OSC_BASE_VALUE_1_1_SHIFT 16U
+#define LPDDR4__DENALI_PI_327__PI_DQS_OSC_BASE_VALUE_1_1_WIDTH 16U
+#define LPDDR4__PI_DQS_OSC_BASE_VALUE_1_1__REG DENALI_PI_327
+#define LPDDR4__PI_DQS_OSC_BASE_VALUE_1_1__FLD LPDDR4__DENALI_PI_327__PI_DQS_OSC_BASE_VALUE_1_1
+
+#define LPDDR4__DENALI_PI_328_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_328_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_328__PI_MR0_DATA_F0_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_328__PI_MR0_DATA_F0_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_328__PI_MR0_DATA_F0_0_WIDTH 17U
+#define LPDDR4__PI_MR0_DATA_F0_0__REG DENALI_PI_328
+#define LPDDR4__PI_MR0_DATA_F0_0__FLD LPDDR4__DENALI_PI_328__PI_MR0_DATA_F0_0
+
+#define LPDDR4__DENALI_PI_329_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_329_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_329__PI_MR1_DATA_F0_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_329__PI_MR1_DATA_F0_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_329__PI_MR1_DATA_F0_0_WIDTH 17U
+#define LPDDR4__PI_MR1_DATA_F0_0__REG DENALI_PI_329
+#define LPDDR4__PI_MR1_DATA_F0_0__FLD LPDDR4__DENALI_PI_329__PI_MR1_DATA_F0_0
+
+#define LPDDR4__DENALI_PI_330_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_330_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_330__PI_MR2_DATA_F0_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_330__PI_MR2_DATA_F0_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_330__PI_MR2_DATA_F0_0_WIDTH 17U
+#define LPDDR4__PI_MR2_DATA_F0_0__REG DENALI_PI_330
+#define LPDDR4__PI_MR2_DATA_F0_0__FLD LPDDR4__DENALI_PI_330__PI_MR2_DATA_F0_0
+
+#define LPDDR4__DENALI_PI_331_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_331_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_331__PI_MR3_DATA_F0_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_331__PI_MR3_DATA_F0_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_331__PI_MR3_DATA_F0_0_WIDTH 17U
+#define LPDDR4__PI_MR3_DATA_F0_0__REG DENALI_PI_331
+#define LPDDR4__PI_MR3_DATA_F0_0__FLD LPDDR4__DENALI_PI_331__PI_MR3_DATA_F0_0
+
+#define LPDDR4__DENALI_PI_332_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_332_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_332__PI_MR4_DATA_F0_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_332__PI_MR4_DATA_F0_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_332__PI_MR4_DATA_F0_0_WIDTH 17U
+#define LPDDR4__PI_MR4_DATA_F0_0__REG DENALI_PI_332
+#define LPDDR4__PI_MR4_DATA_F0_0__FLD LPDDR4__DENALI_PI_332__PI_MR4_DATA_F0_0
+
+#define LPDDR4__DENALI_PI_333_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_333_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_333__PI_MR5_DATA_F0_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_333__PI_MR5_DATA_F0_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_333__PI_MR5_DATA_F0_0_WIDTH 17U
+#define LPDDR4__PI_MR5_DATA_F0_0__REG DENALI_PI_333
+#define LPDDR4__PI_MR5_DATA_F0_0__FLD LPDDR4__DENALI_PI_333__PI_MR5_DATA_F0_0
+
+#define LPDDR4__DENALI_PI_334_READ_MASK 0xFF01FFFFU
+#define LPDDR4__DENALI_PI_334_WRITE_MASK 0xFF01FFFFU
+#define LPDDR4__DENALI_PI_334__PI_MR6_DATA_F0_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_334__PI_MR6_DATA_F0_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_334__PI_MR6_DATA_F0_0_WIDTH 17U
+#define LPDDR4__PI_MR6_DATA_F0_0__REG DENALI_PI_334
+#define LPDDR4__PI_MR6_DATA_F0_0__FLD LPDDR4__DENALI_PI_334__PI_MR6_DATA_F0_0
+
+#define LPDDR4__DENALI_PI_334__PI_MR11_DATA_F0_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_334__PI_MR11_DATA_F0_0_SHIFT 24U
+#define LPDDR4__DENALI_PI_334__PI_MR11_DATA_F0_0_WIDTH 8U
+#define LPDDR4__PI_MR11_DATA_F0_0__REG DENALI_PI_334
+#define LPDDR4__PI_MR11_DATA_F0_0__FLD LPDDR4__DENALI_PI_334__PI_MR11_DATA_F0_0
+
+#define LPDDR4__DENALI_PI_335_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_335_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_335__PI_MR12_DATA_F0_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_335__PI_MR12_DATA_F0_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_335__PI_MR12_DATA_F0_0_WIDTH 8U
+#define LPDDR4__PI_MR12_DATA_F0_0__REG DENALI_PI_335
+#define LPDDR4__PI_MR12_DATA_F0_0__FLD LPDDR4__DENALI_PI_335__PI_MR12_DATA_F0_0
+
+#define LPDDR4__DENALI_PI_335__PI_MR14_DATA_F0_0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_335__PI_MR14_DATA_F0_0_SHIFT 8U
+#define LPDDR4__DENALI_PI_335__PI_MR14_DATA_F0_0_WIDTH 8U
+#define LPDDR4__PI_MR14_DATA_F0_0__REG DENALI_PI_335
+#define LPDDR4__PI_MR14_DATA_F0_0__FLD LPDDR4__DENALI_PI_335__PI_MR14_DATA_F0_0
+
+#define LPDDR4__DENALI_PI_335__PI_MR22_DATA_F0_0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_335__PI_MR22_DATA_F0_0_SHIFT 16U
+#define LPDDR4__DENALI_PI_335__PI_MR22_DATA_F0_0_WIDTH 8U
+#define LPDDR4__PI_MR22_DATA_F0_0__REG DENALI_PI_335
+#define LPDDR4__PI_MR22_DATA_F0_0__FLD LPDDR4__DENALI_PI_335__PI_MR22_DATA_F0_0
+
+#define LPDDR4__DENALI_PI_335__PI_MR23_DATA_F0_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_335__PI_MR23_DATA_F0_0_SHIFT 24U
+#define LPDDR4__DENALI_PI_335__PI_MR23_DATA_F0_0_WIDTH 8U
+#define LPDDR4__PI_MR23_DATA_F0_0__REG DENALI_PI_335
+#define LPDDR4__PI_MR23_DATA_F0_0__FLD LPDDR4__DENALI_PI_335__PI_MR23_DATA_F0_0
+
+#define LPDDR4__DENALI_PI_336_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_336_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_336__PI_MR0_DATA_F1_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_336__PI_MR0_DATA_F1_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_336__PI_MR0_DATA_F1_0_WIDTH 17U
+#define LPDDR4__PI_MR0_DATA_F1_0__REG DENALI_PI_336
+#define LPDDR4__PI_MR0_DATA_F1_0__FLD LPDDR4__DENALI_PI_336__PI_MR0_DATA_F1_0
+
+#define LPDDR4__DENALI_PI_337_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_337_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_337__PI_MR1_DATA_F1_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_337__PI_MR1_DATA_F1_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_337__PI_MR1_DATA_F1_0_WIDTH 17U
+#define LPDDR4__PI_MR1_DATA_F1_0__REG DENALI_PI_337
+#define LPDDR4__PI_MR1_DATA_F1_0__FLD LPDDR4__DENALI_PI_337__PI_MR1_DATA_F1_0
+
+#define LPDDR4__DENALI_PI_338_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_338_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_338__PI_MR2_DATA_F1_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_338__PI_MR2_DATA_F1_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_338__PI_MR2_DATA_F1_0_WIDTH 17U
+#define LPDDR4__PI_MR2_DATA_F1_0__REG DENALI_PI_338
+#define LPDDR4__PI_MR2_DATA_F1_0__FLD LPDDR4__DENALI_PI_338__PI_MR2_DATA_F1_0
+
+#define LPDDR4__DENALI_PI_339_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_339_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_339__PI_MR3_DATA_F1_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_339__PI_MR3_DATA_F1_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_339__PI_MR3_DATA_F1_0_WIDTH 17U
+#define LPDDR4__PI_MR3_DATA_F1_0__REG DENALI_PI_339
+#define LPDDR4__PI_MR3_DATA_F1_0__FLD LPDDR4__DENALI_PI_339__PI_MR3_DATA_F1_0
+
+#define LPDDR4__DENALI_PI_340_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_340_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_340__PI_MR4_DATA_F1_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_340__PI_MR4_DATA_F1_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_340__PI_MR4_DATA_F1_0_WIDTH 17U
+#define LPDDR4__PI_MR4_DATA_F1_0__REG DENALI_PI_340
+#define LPDDR4__PI_MR4_DATA_F1_0__FLD LPDDR4__DENALI_PI_340__PI_MR4_DATA_F1_0
+
+#define LPDDR4__DENALI_PI_341_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_341_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_341__PI_MR5_DATA_F1_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_341__PI_MR5_DATA_F1_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_341__PI_MR5_DATA_F1_0_WIDTH 17U
+#define LPDDR4__PI_MR5_DATA_F1_0__REG DENALI_PI_341
+#define LPDDR4__PI_MR5_DATA_F1_0__FLD LPDDR4__DENALI_PI_341__PI_MR5_DATA_F1_0
+
+#define LPDDR4__DENALI_PI_342_READ_MASK 0xFF01FFFFU
+#define LPDDR4__DENALI_PI_342_WRITE_MASK 0xFF01FFFFU
+#define LPDDR4__DENALI_PI_342__PI_MR6_DATA_F1_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_342__PI_MR6_DATA_F1_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_342__PI_MR6_DATA_F1_0_WIDTH 17U
+#define LPDDR4__PI_MR6_DATA_F1_0__REG DENALI_PI_342
+#define LPDDR4__PI_MR6_DATA_F1_0__FLD LPDDR4__DENALI_PI_342__PI_MR6_DATA_F1_0
+
+#define LPDDR4__DENALI_PI_342__PI_MR11_DATA_F1_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_342__PI_MR11_DATA_F1_0_SHIFT 24U
+#define LPDDR4__DENALI_PI_342__PI_MR11_DATA_F1_0_WIDTH 8U
+#define LPDDR4__PI_MR11_DATA_F1_0__REG DENALI_PI_342
+#define LPDDR4__PI_MR11_DATA_F1_0__FLD LPDDR4__DENALI_PI_342__PI_MR11_DATA_F1_0
+
+#define LPDDR4__DENALI_PI_343_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_343_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_343__PI_MR12_DATA_F1_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_343__PI_MR12_DATA_F1_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_343__PI_MR12_DATA_F1_0_WIDTH 8U
+#define LPDDR4__PI_MR12_DATA_F1_0__REG DENALI_PI_343
+#define LPDDR4__PI_MR12_DATA_F1_0__FLD LPDDR4__DENALI_PI_343__PI_MR12_DATA_F1_0
+
+#define LPDDR4__DENALI_PI_343__PI_MR14_DATA_F1_0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_343__PI_MR14_DATA_F1_0_SHIFT 8U
+#define LPDDR4__DENALI_PI_343__PI_MR14_DATA_F1_0_WIDTH 8U
+#define LPDDR4__PI_MR14_DATA_F1_0__REG DENALI_PI_343
+#define LPDDR4__PI_MR14_DATA_F1_0__FLD LPDDR4__DENALI_PI_343__PI_MR14_DATA_F1_0
+
+#define LPDDR4__DENALI_PI_343__PI_MR22_DATA_F1_0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_343__PI_MR22_DATA_F1_0_SHIFT 16U
+#define LPDDR4__DENALI_PI_343__PI_MR22_DATA_F1_0_WIDTH 8U
+#define LPDDR4__PI_MR22_DATA_F1_0__REG DENALI_PI_343
+#define LPDDR4__PI_MR22_DATA_F1_0__FLD LPDDR4__DENALI_PI_343__PI_MR22_DATA_F1_0
+
+#define LPDDR4__DENALI_PI_343__PI_MR23_DATA_F1_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_343__PI_MR23_DATA_F1_0_SHIFT 24U
+#define LPDDR4__DENALI_PI_343__PI_MR23_DATA_F1_0_WIDTH 8U
+#define LPDDR4__PI_MR23_DATA_F1_0__REG DENALI_PI_343
+#define LPDDR4__PI_MR23_DATA_F1_0__FLD LPDDR4__DENALI_PI_343__PI_MR23_DATA_F1_0
+
+#define LPDDR4__DENALI_PI_344_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_344_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_344__PI_MR0_DATA_F2_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_344__PI_MR0_DATA_F2_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_344__PI_MR0_DATA_F2_0_WIDTH 17U
+#define LPDDR4__PI_MR0_DATA_F2_0__REG DENALI_PI_344
+#define LPDDR4__PI_MR0_DATA_F2_0__FLD LPDDR4__DENALI_PI_344__PI_MR0_DATA_F2_0
+
+#define LPDDR4__DENALI_PI_345_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_345_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_345__PI_MR1_DATA_F2_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_345__PI_MR1_DATA_F2_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_345__PI_MR1_DATA_F2_0_WIDTH 17U
+#define LPDDR4__PI_MR1_DATA_F2_0__REG DENALI_PI_345
+#define LPDDR4__PI_MR1_DATA_F2_0__FLD LPDDR4__DENALI_PI_345__PI_MR1_DATA_F2_0
+
+#define LPDDR4__DENALI_PI_346_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_346_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_346__PI_MR2_DATA_F2_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_346__PI_MR2_DATA_F2_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_346__PI_MR2_DATA_F2_0_WIDTH 17U
+#define LPDDR4__PI_MR2_DATA_F2_0__REG DENALI_PI_346
+#define LPDDR4__PI_MR2_DATA_F2_0__FLD LPDDR4__DENALI_PI_346__PI_MR2_DATA_F2_0
+
+#define LPDDR4__DENALI_PI_347_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_347_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_347__PI_MR3_DATA_F2_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_347__PI_MR3_DATA_F2_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_347__PI_MR3_DATA_F2_0_WIDTH 17U
+#define LPDDR4__PI_MR3_DATA_F2_0__REG DENALI_PI_347
+#define LPDDR4__PI_MR3_DATA_F2_0__FLD LPDDR4__DENALI_PI_347__PI_MR3_DATA_F2_0
+
+#define LPDDR4__DENALI_PI_348_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_348_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_348__PI_MR4_DATA_F2_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_348__PI_MR4_DATA_F2_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_348__PI_MR4_DATA_F2_0_WIDTH 17U
+#define LPDDR4__PI_MR4_DATA_F2_0__REG DENALI_PI_348
+#define LPDDR4__PI_MR4_DATA_F2_0__FLD LPDDR4__DENALI_PI_348__PI_MR4_DATA_F2_0
+
+#define LPDDR4__DENALI_PI_349_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_349_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_349__PI_MR5_DATA_F2_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_349__PI_MR5_DATA_F2_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_349__PI_MR5_DATA_F2_0_WIDTH 17U
+#define LPDDR4__PI_MR5_DATA_F2_0__REG DENALI_PI_349
+#define LPDDR4__PI_MR5_DATA_F2_0__FLD LPDDR4__DENALI_PI_349__PI_MR5_DATA_F2_0
+
+#define LPDDR4__DENALI_PI_350_READ_MASK 0xFF01FFFFU
+#define LPDDR4__DENALI_PI_350_WRITE_MASK 0xFF01FFFFU
+#define LPDDR4__DENALI_PI_350__PI_MR6_DATA_F2_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_350__PI_MR6_DATA_F2_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_350__PI_MR6_DATA_F2_0_WIDTH 17U
+#define LPDDR4__PI_MR6_DATA_F2_0__REG DENALI_PI_350
+#define LPDDR4__PI_MR6_DATA_F2_0__FLD LPDDR4__DENALI_PI_350__PI_MR6_DATA_F2_0
+
+#define LPDDR4__DENALI_PI_350__PI_MR11_DATA_F2_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_350__PI_MR11_DATA_F2_0_SHIFT 24U
+#define LPDDR4__DENALI_PI_350__PI_MR11_DATA_F2_0_WIDTH 8U
+#define LPDDR4__PI_MR11_DATA_F2_0__REG DENALI_PI_350
+#define LPDDR4__PI_MR11_DATA_F2_0__FLD LPDDR4__DENALI_PI_350__PI_MR11_DATA_F2_0
+
+#define LPDDR4__DENALI_PI_351_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_351_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_351__PI_MR12_DATA_F2_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_351__PI_MR12_DATA_F2_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_351__PI_MR12_DATA_F2_0_WIDTH 8U
+#define LPDDR4__PI_MR12_DATA_F2_0__REG DENALI_PI_351
+#define LPDDR4__PI_MR12_DATA_F2_0__FLD LPDDR4__DENALI_PI_351__PI_MR12_DATA_F2_0
+
+#define LPDDR4__DENALI_PI_351__PI_MR14_DATA_F2_0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_351__PI_MR14_DATA_F2_0_SHIFT 8U
+#define LPDDR4__DENALI_PI_351__PI_MR14_DATA_F2_0_WIDTH 8U
+#define LPDDR4__PI_MR14_DATA_F2_0__REG DENALI_PI_351
+#define LPDDR4__PI_MR14_DATA_F2_0__FLD LPDDR4__DENALI_PI_351__PI_MR14_DATA_F2_0
+
+#define LPDDR4__DENALI_PI_351__PI_MR22_DATA_F2_0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_351__PI_MR22_DATA_F2_0_SHIFT 16U
+#define LPDDR4__DENALI_PI_351__PI_MR22_DATA_F2_0_WIDTH 8U
+#define LPDDR4__PI_MR22_DATA_F2_0__REG DENALI_PI_351
+#define LPDDR4__PI_MR22_DATA_F2_0__FLD LPDDR4__DENALI_PI_351__PI_MR22_DATA_F2_0
+
+#define LPDDR4__DENALI_PI_351__PI_MR23_DATA_F2_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_351__PI_MR23_DATA_F2_0_SHIFT 24U
+#define LPDDR4__DENALI_PI_351__PI_MR23_DATA_F2_0_WIDTH 8U
+#define LPDDR4__PI_MR23_DATA_F2_0__REG DENALI_PI_351
+#define LPDDR4__PI_MR23_DATA_F2_0__FLD LPDDR4__DENALI_PI_351__PI_MR23_DATA_F2_0
+
+#define LPDDR4__DENALI_PI_352_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_352_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_352__PI_MR0_DATA_F0_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_352__PI_MR0_DATA_F0_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_352__PI_MR0_DATA_F0_1_WIDTH 17U
+#define LPDDR4__PI_MR0_DATA_F0_1__REG DENALI_PI_352
+#define LPDDR4__PI_MR0_DATA_F0_1__FLD LPDDR4__DENALI_PI_352__PI_MR0_DATA_F0_1
+
+#define LPDDR4__DENALI_PI_353_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_353_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_353__PI_MR1_DATA_F0_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_353__PI_MR1_DATA_F0_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_353__PI_MR1_DATA_F0_1_WIDTH 17U
+#define LPDDR4__PI_MR1_DATA_F0_1__REG DENALI_PI_353
+#define LPDDR4__PI_MR1_DATA_F0_1__FLD LPDDR4__DENALI_PI_353__PI_MR1_DATA_F0_1
+
+#define LPDDR4__DENALI_PI_354_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_354_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_354__PI_MR2_DATA_F0_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_354__PI_MR2_DATA_F0_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_354__PI_MR2_DATA_F0_1_WIDTH 17U
+#define LPDDR4__PI_MR2_DATA_F0_1__REG DENALI_PI_354
+#define LPDDR4__PI_MR2_DATA_F0_1__FLD LPDDR4__DENALI_PI_354__PI_MR2_DATA_F0_1
+
+#define LPDDR4__DENALI_PI_355_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_355_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_355__PI_MR3_DATA_F0_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_355__PI_MR3_DATA_F0_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_355__PI_MR3_DATA_F0_1_WIDTH 17U
+#define LPDDR4__PI_MR3_DATA_F0_1__REG DENALI_PI_355
+#define LPDDR4__PI_MR3_DATA_F0_1__FLD LPDDR4__DENALI_PI_355__PI_MR3_DATA_F0_1
+
+#define LPDDR4__DENALI_PI_356_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_356_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_356__PI_MR4_DATA_F0_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_356__PI_MR4_DATA_F0_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_356__PI_MR4_DATA_F0_1_WIDTH 17U
+#define LPDDR4__PI_MR4_DATA_F0_1__REG DENALI_PI_356
+#define LPDDR4__PI_MR4_DATA_F0_1__FLD LPDDR4__DENALI_PI_356__PI_MR4_DATA_F0_1
+
+#define LPDDR4__DENALI_PI_357_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_357_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_357__PI_MR5_DATA_F0_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_357__PI_MR5_DATA_F0_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_357__PI_MR5_DATA_F0_1_WIDTH 17U
+#define LPDDR4__PI_MR5_DATA_F0_1__REG DENALI_PI_357
+#define LPDDR4__PI_MR5_DATA_F0_1__FLD LPDDR4__DENALI_PI_357__PI_MR5_DATA_F0_1
+
+#define LPDDR4__DENALI_PI_358_READ_MASK 0xFF01FFFFU
+#define LPDDR4__DENALI_PI_358_WRITE_MASK 0xFF01FFFFU
+#define LPDDR4__DENALI_PI_358__PI_MR6_DATA_F0_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_358__PI_MR6_DATA_F0_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_358__PI_MR6_DATA_F0_1_WIDTH 17U
+#define LPDDR4__PI_MR6_DATA_F0_1__REG DENALI_PI_358
+#define LPDDR4__PI_MR6_DATA_F0_1__FLD LPDDR4__DENALI_PI_358__PI_MR6_DATA_F0_1
+
+#define LPDDR4__DENALI_PI_358__PI_MR11_DATA_F0_1_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_358__PI_MR11_DATA_F0_1_SHIFT 24U
+#define LPDDR4__DENALI_PI_358__PI_MR11_DATA_F0_1_WIDTH 8U
+#define LPDDR4__PI_MR11_DATA_F0_1__REG DENALI_PI_358
+#define LPDDR4__PI_MR11_DATA_F0_1__FLD LPDDR4__DENALI_PI_358__PI_MR11_DATA_F0_1
+
+#define LPDDR4__DENALI_PI_359_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_359_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_359__PI_MR12_DATA_F0_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_359__PI_MR12_DATA_F0_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_359__PI_MR12_DATA_F0_1_WIDTH 8U
+#define LPDDR4__PI_MR12_DATA_F0_1__REG DENALI_PI_359
+#define LPDDR4__PI_MR12_DATA_F0_1__FLD LPDDR4__DENALI_PI_359__PI_MR12_DATA_F0_1
+
+#define LPDDR4__DENALI_PI_359__PI_MR14_DATA_F0_1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_359__PI_MR14_DATA_F0_1_SHIFT 8U
+#define LPDDR4__DENALI_PI_359__PI_MR14_DATA_F0_1_WIDTH 8U
+#define LPDDR4__PI_MR14_DATA_F0_1__REG DENALI_PI_359
+#define LPDDR4__PI_MR14_DATA_F0_1__FLD LPDDR4__DENALI_PI_359__PI_MR14_DATA_F0_1
+
+#define LPDDR4__DENALI_PI_359__PI_MR22_DATA_F0_1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_359__PI_MR22_DATA_F0_1_SHIFT 16U
+#define LPDDR4__DENALI_PI_359__PI_MR22_DATA_F0_1_WIDTH 8U
+#define LPDDR4__PI_MR22_DATA_F0_1__REG DENALI_PI_359
+#define LPDDR4__PI_MR22_DATA_F0_1__FLD LPDDR4__DENALI_PI_359__PI_MR22_DATA_F0_1
+
+#define LPDDR4__DENALI_PI_359__PI_MR23_DATA_F0_1_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_359__PI_MR23_DATA_F0_1_SHIFT 24U
+#define LPDDR4__DENALI_PI_359__PI_MR23_DATA_F0_1_WIDTH 8U
+#define LPDDR4__PI_MR23_DATA_F0_1__REG DENALI_PI_359
+#define LPDDR4__PI_MR23_DATA_F0_1__FLD LPDDR4__DENALI_PI_359__PI_MR23_DATA_F0_1
+
+#define LPDDR4__DENALI_PI_360_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_360_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_360__PI_MR0_DATA_F1_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_360__PI_MR0_DATA_F1_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_360__PI_MR0_DATA_F1_1_WIDTH 17U
+#define LPDDR4__PI_MR0_DATA_F1_1__REG DENALI_PI_360
+#define LPDDR4__PI_MR0_DATA_F1_1__FLD LPDDR4__DENALI_PI_360__PI_MR0_DATA_F1_1
+
+#define LPDDR4__DENALI_PI_361_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_361_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_361__PI_MR1_DATA_F1_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_361__PI_MR1_DATA_F1_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_361__PI_MR1_DATA_F1_1_WIDTH 17U
+#define LPDDR4__PI_MR1_DATA_F1_1__REG DENALI_PI_361
+#define LPDDR4__PI_MR1_DATA_F1_1__FLD LPDDR4__DENALI_PI_361__PI_MR1_DATA_F1_1
+
+#define LPDDR4__DENALI_PI_362_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_362_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_362__PI_MR2_DATA_F1_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_362__PI_MR2_DATA_F1_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_362__PI_MR2_DATA_F1_1_WIDTH 17U
+#define LPDDR4__PI_MR2_DATA_F1_1__REG DENALI_PI_362
+#define LPDDR4__PI_MR2_DATA_F1_1__FLD LPDDR4__DENALI_PI_362__PI_MR2_DATA_F1_1
+
+#define LPDDR4__DENALI_PI_363_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_363_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_363__PI_MR3_DATA_F1_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_363__PI_MR3_DATA_F1_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_363__PI_MR3_DATA_F1_1_WIDTH 17U
+#define LPDDR4__PI_MR3_DATA_F1_1__REG DENALI_PI_363
+#define LPDDR4__PI_MR3_DATA_F1_1__FLD LPDDR4__DENALI_PI_363__PI_MR3_DATA_F1_1
+
+#define LPDDR4__DENALI_PI_364_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_364_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_364__PI_MR4_DATA_F1_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_364__PI_MR4_DATA_F1_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_364__PI_MR4_DATA_F1_1_WIDTH 17U
+#define LPDDR4__PI_MR4_DATA_F1_1__REG DENALI_PI_364
+#define LPDDR4__PI_MR4_DATA_F1_1__FLD LPDDR4__DENALI_PI_364__PI_MR4_DATA_F1_1
+
+#define LPDDR4__DENALI_PI_365_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_365_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_365__PI_MR5_DATA_F1_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_365__PI_MR5_DATA_F1_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_365__PI_MR5_DATA_F1_1_WIDTH 17U
+#define LPDDR4__PI_MR5_DATA_F1_1__REG DENALI_PI_365
+#define LPDDR4__PI_MR5_DATA_F1_1__FLD LPDDR4__DENALI_PI_365__PI_MR5_DATA_F1_1
+
+#define LPDDR4__DENALI_PI_366_READ_MASK 0xFF01FFFFU
+#define LPDDR4__DENALI_PI_366_WRITE_MASK 0xFF01FFFFU
+#define LPDDR4__DENALI_PI_366__PI_MR6_DATA_F1_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_366__PI_MR6_DATA_F1_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_366__PI_MR6_DATA_F1_1_WIDTH 17U
+#define LPDDR4__PI_MR6_DATA_F1_1__REG DENALI_PI_366
+#define LPDDR4__PI_MR6_DATA_F1_1__FLD LPDDR4__DENALI_PI_366__PI_MR6_DATA_F1_1
+
+#define LPDDR4__DENALI_PI_366__PI_MR11_DATA_F1_1_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_366__PI_MR11_DATA_F1_1_SHIFT 24U
+#define LPDDR4__DENALI_PI_366__PI_MR11_DATA_F1_1_WIDTH 8U
+#define LPDDR4__PI_MR11_DATA_F1_1__REG DENALI_PI_366
+#define LPDDR4__PI_MR11_DATA_F1_1__FLD LPDDR4__DENALI_PI_366__PI_MR11_DATA_F1_1
+
+#define LPDDR4__DENALI_PI_367_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_367_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_367__PI_MR12_DATA_F1_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_367__PI_MR12_DATA_F1_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_367__PI_MR12_DATA_F1_1_WIDTH 8U
+#define LPDDR4__PI_MR12_DATA_F1_1__REG DENALI_PI_367
+#define LPDDR4__PI_MR12_DATA_F1_1__FLD LPDDR4__DENALI_PI_367__PI_MR12_DATA_F1_1
+
+#define LPDDR4__DENALI_PI_367__PI_MR14_DATA_F1_1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_367__PI_MR14_DATA_F1_1_SHIFT 8U
+#define LPDDR4__DENALI_PI_367__PI_MR14_DATA_F1_1_WIDTH 8U
+#define LPDDR4__PI_MR14_DATA_F1_1__REG DENALI_PI_367
+#define LPDDR4__PI_MR14_DATA_F1_1__FLD LPDDR4__DENALI_PI_367__PI_MR14_DATA_F1_1
+
+#define LPDDR4__DENALI_PI_367__PI_MR22_DATA_F1_1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_367__PI_MR22_DATA_F1_1_SHIFT 16U
+#define LPDDR4__DENALI_PI_367__PI_MR22_DATA_F1_1_WIDTH 8U
+#define LPDDR4__PI_MR22_DATA_F1_1__REG DENALI_PI_367
+#define LPDDR4__PI_MR22_DATA_F1_1__FLD LPDDR4__DENALI_PI_367__PI_MR22_DATA_F1_1
+
+#define LPDDR4__DENALI_PI_367__PI_MR23_DATA_F1_1_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_367__PI_MR23_DATA_F1_1_SHIFT 24U
+#define LPDDR4__DENALI_PI_367__PI_MR23_DATA_F1_1_WIDTH 8U
+#define LPDDR4__PI_MR23_DATA_F1_1__REG DENALI_PI_367
+#define LPDDR4__PI_MR23_DATA_F1_1__FLD LPDDR4__DENALI_PI_367__PI_MR23_DATA_F1_1
+
+#define LPDDR4__DENALI_PI_368_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_368_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_368__PI_MR0_DATA_F2_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_368__PI_MR0_DATA_F2_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_368__PI_MR0_DATA_F2_1_WIDTH 17U
+#define LPDDR4__PI_MR0_DATA_F2_1__REG DENALI_PI_368
+#define LPDDR4__PI_MR0_DATA_F2_1__FLD LPDDR4__DENALI_PI_368__PI_MR0_DATA_F2_1
+
+#define LPDDR4__DENALI_PI_369_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_369_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_369__PI_MR1_DATA_F2_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_369__PI_MR1_DATA_F2_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_369__PI_MR1_DATA_F2_1_WIDTH 17U
+#define LPDDR4__PI_MR1_DATA_F2_1__REG DENALI_PI_369
+#define LPDDR4__PI_MR1_DATA_F2_1__FLD LPDDR4__DENALI_PI_369__PI_MR1_DATA_F2_1
+
+#define LPDDR4__DENALI_PI_370_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_370_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_370__PI_MR2_DATA_F2_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_370__PI_MR2_DATA_F2_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_370__PI_MR2_DATA_F2_1_WIDTH 17U
+#define LPDDR4__PI_MR2_DATA_F2_1__REG DENALI_PI_370
+#define LPDDR4__PI_MR2_DATA_F2_1__FLD LPDDR4__DENALI_PI_370__PI_MR2_DATA_F2_1
+
+#define LPDDR4__DENALI_PI_371_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_371_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_371__PI_MR3_DATA_F2_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_371__PI_MR3_DATA_F2_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_371__PI_MR3_DATA_F2_1_WIDTH 17U
+#define LPDDR4__PI_MR3_DATA_F2_1__REG DENALI_PI_371
+#define LPDDR4__PI_MR3_DATA_F2_1__FLD LPDDR4__DENALI_PI_371__PI_MR3_DATA_F2_1
+
+#define LPDDR4__DENALI_PI_372_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_372_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_372__PI_MR4_DATA_F2_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_372__PI_MR4_DATA_F2_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_372__PI_MR4_DATA_F2_1_WIDTH 17U
+#define LPDDR4__PI_MR4_DATA_F2_1__REG DENALI_PI_372
+#define LPDDR4__PI_MR4_DATA_F2_1__FLD LPDDR4__DENALI_PI_372__PI_MR4_DATA_F2_1
+
+#define LPDDR4__DENALI_PI_373_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_373_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_373__PI_MR5_DATA_F2_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_373__PI_MR5_DATA_F2_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_373__PI_MR5_DATA_F2_1_WIDTH 17U
+#define LPDDR4__PI_MR5_DATA_F2_1__REG DENALI_PI_373
+#define LPDDR4__PI_MR5_DATA_F2_1__FLD LPDDR4__DENALI_PI_373__PI_MR5_DATA_F2_1
+
+#define LPDDR4__DENALI_PI_374_READ_MASK 0xFF01FFFFU
+#define LPDDR4__DENALI_PI_374_WRITE_MASK 0xFF01FFFFU
+#define LPDDR4__DENALI_PI_374__PI_MR6_DATA_F2_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_374__PI_MR6_DATA_F2_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_374__PI_MR6_DATA_F2_1_WIDTH 17U
+#define LPDDR4__PI_MR6_DATA_F2_1__REG DENALI_PI_374
+#define LPDDR4__PI_MR6_DATA_F2_1__FLD LPDDR4__DENALI_PI_374__PI_MR6_DATA_F2_1
+
+#define LPDDR4__DENALI_PI_374__PI_MR11_DATA_F2_1_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_374__PI_MR11_DATA_F2_1_SHIFT 24U
+#define LPDDR4__DENALI_PI_374__PI_MR11_DATA_F2_1_WIDTH 8U
+#define LPDDR4__PI_MR11_DATA_F2_1__REG DENALI_PI_374
+#define LPDDR4__PI_MR11_DATA_F2_1__FLD LPDDR4__DENALI_PI_374__PI_MR11_DATA_F2_1
+
+#define LPDDR4__DENALI_PI_375_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_375_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_375__PI_MR12_DATA_F2_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_375__PI_MR12_DATA_F2_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_375__PI_MR12_DATA_F2_1_WIDTH 8U
+#define LPDDR4__PI_MR12_DATA_F2_1__REG DENALI_PI_375
+#define LPDDR4__PI_MR12_DATA_F2_1__FLD LPDDR4__DENALI_PI_375__PI_MR12_DATA_F2_1
+
+#define LPDDR4__DENALI_PI_375__PI_MR14_DATA_F2_1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_375__PI_MR14_DATA_F2_1_SHIFT 8U
+#define LPDDR4__DENALI_PI_375__PI_MR14_DATA_F2_1_WIDTH 8U
+#define LPDDR4__PI_MR14_DATA_F2_1__REG DENALI_PI_375
+#define LPDDR4__PI_MR14_DATA_F2_1__FLD LPDDR4__DENALI_PI_375__PI_MR14_DATA_F2_1
+
+#define LPDDR4__DENALI_PI_375__PI_MR22_DATA_F2_1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_375__PI_MR22_DATA_F2_1_SHIFT 16U
+#define LPDDR4__DENALI_PI_375__PI_MR22_DATA_F2_1_WIDTH 8U
+#define LPDDR4__PI_MR22_DATA_F2_1__REG DENALI_PI_375
+#define LPDDR4__PI_MR22_DATA_F2_1__FLD LPDDR4__DENALI_PI_375__PI_MR22_DATA_F2_1
+
+#define LPDDR4__DENALI_PI_375__PI_MR23_DATA_F2_1_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_375__PI_MR23_DATA_F2_1_SHIFT 24U
+#define LPDDR4__DENALI_PI_375__PI_MR23_DATA_F2_1_WIDTH 8U
+#define LPDDR4__PI_MR23_DATA_F2_1__REG DENALI_PI_375
+#define LPDDR4__PI_MR23_DATA_F2_1__FLD LPDDR4__DENALI_PI_375__PI_MR23_DATA_F2_1
+
+#define LPDDR4__DENALI_PI_376_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_376_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_376__PI_MR0_DATA_F0_2_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_376__PI_MR0_DATA_F0_2_SHIFT 0U
+#define LPDDR4__DENALI_PI_376__PI_MR0_DATA_F0_2_WIDTH 17U
+#define LPDDR4__PI_MR0_DATA_F0_2__REG DENALI_PI_376
+#define LPDDR4__PI_MR0_DATA_F0_2__FLD LPDDR4__DENALI_PI_376__PI_MR0_DATA_F0_2
+
+#define LPDDR4__DENALI_PI_377_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_377_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_377__PI_MR1_DATA_F0_2_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_377__PI_MR1_DATA_F0_2_SHIFT 0U
+#define LPDDR4__DENALI_PI_377__PI_MR1_DATA_F0_2_WIDTH 17U
+#define LPDDR4__PI_MR1_DATA_F0_2__REG DENALI_PI_377
+#define LPDDR4__PI_MR1_DATA_F0_2__FLD LPDDR4__DENALI_PI_377__PI_MR1_DATA_F0_2
+
+#define LPDDR4__DENALI_PI_378_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_378_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_378__PI_MR2_DATA_F0_2_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_378__PI_MR2_DATA_F0_2_SHIFT 0U
+#define LPDDR4__DENALI_PI_378__PI_MR2_DATA_F0_2_WIDTH 17U
+#define LPDDR4__PI_MR2_DATA_F0_2__REG DENALI_PI_378
+#define LPDDR4__PI_MR2_DATA_F0_2__FLD LPDDR4__DENALI_PI_378__PI_MR2_DATA_F0_2
+
+#define LPDDR4__DENALI_PI_379_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_379_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_379__PI_MR3_DATA_F0_2_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_379__PI_MR3_DATA_F0_2_SHIFT 0U
+#define LPDDR4__DENALI_PI_379__PI_MR3_DATA_F0_2_WIDTH 17U
+#define LPDDR4__PI_MR3_DATA_F0_2__REG DENALI_PI_379
+#define LPDDR4__PI_MR3_DATA_F0_2__FLD LPDDR4__DENALI_PI_379__PI_MR3_DATA_F0_2
+
+#define LPDDR4__DENALI_PI_380_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_380_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_380__PI_MR4_DATA_F0_2_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_380__PI_MR4_DATA_F0_2_SHIFT 0U
+#define LPDDR4__DENALI_PI_380__PI_MR4_DATA_F0_2_WIDTH 17U
+#define LPDDR4__PI_MR4_DATA_F0_2__REG DENALI_PI_380
+#define LPDDR4__PI_MR4_DATA_F0_2__FLD LPDDR4__DENALI_PI_380__PI_MR4_DATA_F0_2
+
+#define LPDDR4__DENALI_PI_381_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_381_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_381__PI_MR5_DATA_F0_2_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_381__PI_MR5_DATA_F0_2_SHIFT 0U
+#define LPDDR4__DENALI_PI_381__PI_MR5_DATA_F0_2_WIDTH 17U
+#define LPDDR4__PI_MR5_DATA_F0_2__REG DENALI_PI_381
+#define LPDDR4__PI_MR5_DATA_F0_2__FLD LPDDR4__DENALI_PI_381__PI_MR5_DATA_F0_2
+
+#define LPDDR4__DENALI_PI_382_READ_MASK 0xFF01FFFFU
+#define LPDDR4__DENALI_PI_382_WRITE_MASK 0xFF01FFFFU
+#define LPDDR4__DENALI_PI_382__PI_MR6_DATA_F0_2_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_382__PI_MR6_DATA_F0_2_SHIFT 0U
+#define LPDDR4__DENALI_PI_382__PI_MR6_DATA_F0_2_WIDTH 17U
+#define LPDDR4__PI_MR6_DATA_F0_2__REG DENALI_PI_382
+#define LPDDR4__PI_MR6_DATA_F0_2__FLD LPDDR4__DENALI_PI_382__PI_MR6_DATA_F0_2
+
+#define LPDDR4__DENALI_PI_382__PI_MR11_DATA_F0_2_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_382__PI_MR11_DATA_F0_2_SHIFT 24U
+#define LPDDR4__DENALI_PI_382__PI_MR11_DATA_F0_2_WIDTH 8U
+#define LPDDR4__PI_MR11_DATA_F0_2__REG DENALI_PI_382
+#define LPDDR4__PI_MR11_DATA_F0_2__FLD LPDDR4__DENALI_PI_382__PI_MR11_DATA_F0_2
+
+#define LPDDR4__DENALI_PI_383_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_383_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_383__PI_MR12_DATA_F0_2_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_383__PI_MR12_DATA_F0_2_SHIFT 0U
+#define LPDDR4__DENALI_PI_383__PI_MR12_DATA_F0_2_WIDTH 8U
+#define LPDDR4__PI_MR12_DATA_F0_2__REG DENALI_PI_383
+#define LPDDR4__PI_MR12_DATA_F0_2__FLD LPDDR4__DENALI_PI_383__PI_MR12_DATA_F0_2
+
+#define LPDDR4__DENALI_PI_383__PI_MR14_DATA_F0_2_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_383__PI_MR14_DATA_F0_2_SHIFT 8U
+#define LPDDR4__DENALI_PI_383__PI_MR14_DATA_F0_2_WIDTH 8U
+#define LPDDR4__PI_MR14_DATA_F0_2__REG DENALI_PI_383
+#define LPDDR4__PI_MR14_DATA_F0_2__FLD LPDDR4__DENALI_PI_383__PI_MR14_DATA_F0_2
+
+#define LPDDR4__DENALI_PI_383__PI_MR22_DATA_F0_2_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_383__PI_MR22_DATA_F0_2_SHIFT 16U
+#define LPDDR4__DENALI_PI_383__PI_MR22_DATA_F0_2_WIDTH 8U
+#define LPDDR4__PI_MR22_DATA_F0_2__REG DENALI_PI_383
+#define LPDDR4__PI_MR22_DATA_F0_2__FLD LPDDR4__DENALI_PI_383__PI_MR22_DATA_F0_2
+
+#define LPDDR4__DENALI_PI_383__PI_MR23_DATA_F0_2_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_383__PI_MR23_DATA_F0_2_SHIFT 24U
+#define LPDDR4__DENALI_PI_383__PI_MR23_DATA_F0_2_WIDTH 8U
+#define LPDDR4__PI_MR23_DATA_F0_2__REG DENALI_PI_383
+#define LPDDR4__PI_MR23_DATA_F0_2__FLD LPDDR4__DENALI_PI_383__PI_MR23_DATA_F0_2
+
+#define LPDDR4__DENALI_PI_384_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_384_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_384__PI_MR0_DATA_F1_2_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_384__PI_MR0_DATA_F1_2_SHIFT 0U
+#define LPDDR4__DENALI_PI_384__PI_MR0_DATA_F1_2_WIDTH 17U
+#define LPDDR4__PI_MR0_DATA_F1_2__REG DENALI_PI_384
+#define LPDDR4__PI_MR0_DATA_F1_2__FLD LPDDR4__DENALI_PI_384__PI_MR0_DATA_F1_2
+
+#define LPDDR4__DENALI_PI_385_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_385_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_385__PI_MR1_DATA_F1_2_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_385__PI_MR1_DATA_F1_2_SHIFT 0U
+#define LPDDR4__DENALI_PI_385__PI_MR1_DATA_F1_2_WIDTH 17U
+#define LPDDR4__PI_MR1_DATA_F1_2__REG DENALI_PI_385
+#define LPDDR4__PI_MR1_DATA_F1_2__FLD LPDDR4__DENALI_PI_385__PI_MR1_DATA_F1_2
+
+#define LPDDR4__DENALI_PI_386_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_386_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_386__PI_MR2_DATA_F1_2_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_386__PI_MR2_DATA_F1_2_SHIFT 0U
+#define LPDDR4__DENALI_PI_386__PI_MR2_DATA_F1_2_WIDTH 17U
+#define LPDDR4__PI_MR2_DATA_F1_2__REG DENALI_PI_386
+#define LPDDR4__PI_MR2_DATA_F1_2__FLD LPDDR4__DENALI_PI_386__PI_MR2_DATA_F1_2
+
+#define LPDDR4__DENALI_PI_387_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_387_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_387__PI_MR3_DATA_F1_2_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_387__PI_MR3_DATA_F1_2_SHIFT 0U
+#define LPDDR4__DENALI_PI_387__PI_MR3_DATA_F1_2_WIDTH 17U
+#define LPDDR4__PI_MR3_DATA_F1_2__REG DENALI_PI_387
+#define LPDDR4__PI_MR3_DATA_F1_2__FLD LPDDR4__DENALI_PI_387__PI_MR3_DATA_F1_2
+
+#define LPDDR4__DENALI_PI_388_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_388_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_388__PI_MR4_DATA_F1_2_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_388__PI_MR4_DATA_F1_2_SHIFT 0U
+#define LPDDR4__DENALI_PI_388__PI_MR4_DATA_F1_2_WIDTH 17U
+#define LPDDR4__PI_MR4_DATA_F1_2__REG DENALI_PI_388
+#define LPDDR4__PI_MR4_DATA_F1_2__FLD LPDDR4__DENALI_PI_388__PI_MR4_DATA_F1_2
+
+#define LPDDR4__DENALI_PI_389_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_389_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_389__PI_MR5_DATA_F1_2_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_389__PI_MR5_DATA_F1_2_SHIFT 0U
+#define LPDDR4__DENALI_PI_389__PI_MR5_DATA_F1_2_WIDTH 17U
+#define LPDDR4__PI_MR5_DATA_F1_2__REG DENALI_PI_389
+#define LPDDR4__PI_MR5_DATA_F1_2__FLD LPDDR4__DENALI_PI_389__PI_MR5_DATA_F1_2
+
+#define LPDDR4__DENALI_PI_390_READ_MASK 0xFF01FFFFU
+#define LPDDR4__DENALI_PI_390_WRITE_MASK 0xFF01FFFFU
+#define LPDDR4__DENALI_PI_390__PI_MR6_DATA_F1_2_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_390__PI_MR6_DATA_F1_2_SHIFT 0U
+#define LPDDR4__DENALI_PI_390__PI_MR6_DATA_F1_2_WIDTH 17U
+#define LPDDR4__PI_MR6_DATA_F1_2__REG DENALI_PI_390
+#define LPDDR4__PI_MR6_DATA_F1_2__FLD LPDDR4__DENALI_PI_390__PI_MR6_DATA_F1_2
+
+#define LPDDR4__DENALI_PI_390__PI_MR11_DATA_F1_2_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_390__PI_MR11_DATA_F1_2_SHIFT 24U
+#define LPDDR4__DENALI_PI_390__PI_MR11_DATA_F1_2_WIDTH 8U
+#define LPDDR4__PI_MR11_DATA_F1_2__REG DENALI_PI_390
+#define LPDDR4__PI_MR11_DATA_F1_2__FLD LPDDR4__DENALI_PI_390__PI_MR11_DATA_F1_2
+
+#define LPDDR4__DENALI_PI_391_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_391_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_391__PI_MR12_DATA_F1_2_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_391__PI_MR12_DATA_F1_2_SHIFT 0U
+#define LPDDR4__DENALI_PI_391__PI_MR12_DATA_F1_2_WIDTH 8U
+#define LPDDR4__PI_MR12_DATA_F1_2__REG DENALI_PI_391
+#define LPDDR4__PI_MR12_DATA_F1_2__FLD LPDDR4__DENALI_PI_391__PI_MR12_DATA_F1_2
+
+#define LPDDR4__DENALI_PI_391__PI_MR14_DATA_F1_2_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_391__PI_MR14_DATA_F1_2_SHIFT 8U
+#define LPDDR4__DENALI_PI_391__PI_MR14_DATA_F1_2_WIDTH 8U
+#define LPDDR4__PI_MR14_DATA_F1_2__REG DENALI_PI_391
+#define LPDDR4__PI_MR14_DATA_F1_2__FLD LPDDR4__DENALI_PI_391__PI_MR14_DATA_F1_2
+
+#define LPDDR4__DENALI_PI_391__PI_MR22_DATA_F1_2_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_391__PI_MR22_DATA_F1_2_SHIFT 16U
+#define LPDDR4__DENALI_PI_391__PI_MR22_DATA_F1_2_WIDTH 8U
+#define LPDDR4__PI_MR22_DATA_F1_2__REG DENALI_PI_391
+#define LPDDR4__PI_MR22_DATA_F1_2__FLD LPDDR4__DENALI_PI_391__PI_MR22_DATA_F1_2
+
+#define LPDDR4__DENALI_PI_391__PI_MR23_DATA_F1_2_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_391__PI_MR23_DATA_F1_2_SHIFT 24U
+#define LPDDR4__DENALI_PI_391__PI_MR23_DATA_F1_2_WIDTH 8U
+#define LPDDR4__PI_MR23_DATA_F1_2__REG DENALI_PI_391
+#define LPDDR4__PI_MR23_DATA_F1_2__FLD LPDDR4__DENALI_PI_391__PI_MR23_DATA_F1_2
+
+#define LPDDR4__DENALI_PI_392_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_392_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_392__PI_MR0_DATA_F2_2_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_392__PI_MR0_DATA_F2_2_SHIFT 0U
+#define LPDDR4__DENALI_PI_392__PI_MR0_DATA_F2_2_WIDTH 17U
+#define LPDDR4__PI_MR0_DATA_F2_2__REG DENALI_PI_392
+#define LPDDR4__PI_MR0_DATA_F2_2__FLD LPDDR4__DENALI_PI_392__PI_MR0_DATA_F2_2
+
+#define LPDDR4__DENALI_PI_393_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_393_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_393__PI_MR1_DATA_F2_2_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_393__PI_MR1_DATA_F2_2_SHIFT 0U
+#define LPDDR4__DENALI_PI_393__PI_MR1_DATA_F2_2_WIDTH 17U
+#define LPDDR4__PI_MR1_DATA_F2_2__REG DENALI_PI_393
+#define LPDDR4__PI_MR1_DATA_F2_2__FLD LPDDR4__DENALI_PI_393__PI_MR1_DATA_F2_2
+
+#define LPDDR4__DENALI_PI_394_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_394_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_394__PI_MR2_DATA_F2_2_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_394__PI_MR2_DATA_F2_2_SHIFT 0U
+#define LPDDR4__DENALI_PI_394__PI_MR2_DATA_F2_2_WIDTH 17U
+#define LPDDR4__PI_MR2_DATA_F2_2__REG DENALI_PI_394
+#define LPDDR4__PI_MR2_DATA_F2_2__FLD LPDDR4__DENALI_PI_394__PI_MR2_DATA_F2_2
+
+#define LPDDR4__DENALI_PI_395_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_395_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_395__PI_MR3_DATA_F2_2_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_395__PI_MR3_DATA_F2_2_SHIFT 0U
+#define LPDDR4__DENALI_PI_395__PI_MR3_DATA_F2_2_WIDTH 17U
+#define LPDDR4__PI_MR3_DATA_F2_2__REG DENALI_PI_395
+#define LPDDR4__PI_MR3_DATA_F2_2__FLD LPDDR4__DENALI_PI_395__PI_MR3_DATA_F2_2
+
+#define LPDDR4__DENALI_PI_396_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_396_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_396__PI_MR4_DATA_F2_2_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_396__PI_MR4_DATA_F2_2_SHIFT 0U
+#define LPDDR4__DENALI_PI_396__PI_MR4_DATA_F2_2_WIDTH 17U
+#define LPDDR4__PI_MR4_DATA_F2_2__REG DENALI_PI_396
+#define LPDDR4__PI_MR4_DATA_F2_2__FLD LPDDR4__DENALI_PI_396__PI_MR4_DATA_F2_2
+
+#define LPDDR4__DENALI_PI_397_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_397_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_397__PI_MR5_DATA_F2_2_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_397__PI_MR5_DATA_F2_2_SHIFT 0U
+#define LPDDR4__DENALI_PI_397__PI_MR5_DATA_F2_2_WIDTH 17U
+#define LPDDR4__PI_MR5_DATA_F2_2__REG DENALI_PI_397
+#define LPDDR4__PI_MR5_DATA_F2_2__FLD LPDDR4__DENALI_PI_397__PI_MR5_DATA_F2_2
+
+#define LPDDR4__DENALI_PI_398_READ_MASK 0xFF01FFFFU
+#define LPDDR4__DENALI_PI_398_WRITE_MASK 0xFF01FFFFU
+#define LPDDR4__DENALI_PI_398__PI_MR6_DATA_F2_2_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_398__PI_MR6_DATA_F2_2_SHIFT 0U
+#define LPDDR4__DENALI_PI_398__PI_MR6_DATA_F2_2_WIDTH 17U
+#define LPDDR4__PI_MR6_DATA_F2_2__REG DENALI_PI_398
+#define LPDDR4__PI_MR6_DATA_F2_2__FLD LPDDR4__DENALI_PI_398__PI_MR6_DATA_F2_2
+
+#define LPDDR4__DENALI_PI_398__PI_MR11_DATA_F2_2_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_398__PI_MR11_DATA_F2_2_SHIFT 24U
+#define LPDDR4__DENALI_PI_398__PI_MR11_DATA_F2_2_WIDTH 8U
+#define LPDDR4__PI_MR11_DATA_F2_2__REG DENALI_PI_398
+#define LPDDR4__PI_MR11_DATA_F2_2__FLD LPDDR4__DENALI_PI_398__PI_MR11_DATA_F2_2
+
+#define LPDDR4__DENALI_PI_399_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_399_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_399__PI_MR12_DATA_F2_2_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_399__PI_MR12_DATA_F2_2_SHIFT 0U
+#define LPDDR4__DENALI_PI_399__PI_MR12_DATA_F2_2_WIDTH 8U
+#define LPDDR4__PI_MR12_DATA_F2_2__REG DENALI_PI_399
+#define LPDDR4__PI_MR12_DATA_F2_2__FLD LPDDR4__DENALI_PI_399__PI_MR12_DATA_F2_2
+
+#define LPDDR4__DENALI_PI_399__PI_MR14_DATA_F2_2_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_399__PI_MR14_DATA_F2_2_SHIFT 8U
+#define LPDDR4__DENALI_PI_399__PI_MR14_DATA_F2_2_WIDTH 8U
+#define LPDDR4__PI_MR14_DATA_F2_2__REG DENALI_PI_399
+#define LPDDR4__PI_MR14_DATA_F2_2__FLD LPDDR4__DENALI_PI_399__PI_MR14_DATA_F2_2
+
+#define LPDDR4__DENALI_PI_399__PI_MR22_DATA_F2_2_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_399__PI_MR22_DATA_F2_2_SHIFT 16U
+#define LPDDR4__DENALI_PI_399__PI_MR22_DATA_F2_2_WIDTH 8U
+#define LPDDR4__PI_MR22_DATA_F2_2__REG DENALI_PI_399
+#define LPDDR4__PI_MR22_DATA_F2_2__FLD LPDDR4__DENALI_PI_399__PI_MR22_DATA_F2_2
+
+#define LPDDR4__DENALI_PI_399__PI_MR23_DATA_F2_2_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_399__PI_MR23_DATA_F2_2_SHIFT 24U
+#define LPDDR4__DENALI_PI_399__PI_MR23_DATA_F2_2_WIDTH 8U
+#define LPDDR4__PI_MR23_DATA_F2_2__REG DENALI_PI_399
+#define LPDDR4__PI_MR23_DATA_F2_2__FLD LPDDR4__DENALI_PI_399__PI_MR23_DATA_F2_2
+
+#define LPDDR4__DENALI_PI_400_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_400_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_400__PI_MR0_DATA_F0_3_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_400__PI_MR0_DATA_F0_3_SHIFT 0U
+#define LPDDR4__DENALI_PI_400__PI_MR0_DATA_F0_3_WIDTH 17U
+#define LPDDR4__PI_MR0_DATA_F0_3__REG DENALI_PI_400
+#define LPDDR4__PI_MR0_DATA_F0_3__FLD LPDDR4__DENALI_PI_400__PI_MR0_DATA_F0_3
+
+#define LPDDR4__DENALI_PI_401_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_401_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_401__PI_MR1_DATA_F0_3_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_401__PI_MR1_DATA_F0_3_SHIFT 0U
+#define LPDDR4__DENALI_PI_401__PI_MR1_DATA_F0_3_WIDTH 17U
+#define LPDDR4__PI_MR1_DATA_F0_3__REG DENALI_PI_401
+#define LPDDR4__PI_MR1_DATA_F0_3__FLD LPDDR4__DENALI_PI_401__PI_MR1_DATA_F0_3
+
+#define LPDDR4__DENALI_PI_402_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_402_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_402__PI_MR2_DATA_F0_3_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_402__PI_MR2_DATA_F0_3_SHIFT 0U
+#define LPDDR4__DENALI_PI_402__PI_MR2_DATA_F0_3_WIDTH 17U
+#define LPDDR4__PI_MR2_DATA_F0_3__REG DENALI_PI_402
+#define LPDDR4__PI_MR2_DATA_F0_3__FLD LPDDR4__DENALI_PI_402__PI_MR2_DATA_F0_3
+
+#define LPDDR4__DENALI_PI_403_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_403_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_403__PI_MR3_DATA_F0_3_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_403__PI_MR3_DATA_F0_3_SHIFT 0U
+#define LPDDR4__DENALI_PI_403__PI_MR3_DATA_F0_3_WIDTH 17U
+#define LPDDR4__PI_MR3_DATA_F0_3__REG DENALI_PI_403
+#define LPDDR4__PI_MR3_DATA_F0_3__FLD LPDDR4__DENALI_PI_403__PI_MR3_DATA_F0_3
+
+#define LPDDR4__DENALI_PI_404_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_404_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_404__PI_MR4_DATA_F0_3_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_404__PI_MR4_DATA_F0_3_SHIFT 0U
+#define LPDDR4__DENALI_PI_404__PI_MR4_DATA_F0_3_WIDTH 17U
+#define LPDDR4__PI_MR4_DATA_F0_3__REG DENALI_PI_404
+#define LPDDR4__PI_MR4_DATA_F0_3__FLD LPDDR4__DENALI_PI_404__PI_MR4_DATA_F0_3
+
+#define LPDDR4__DENALI_PI_405_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_405_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_405__PI_MR5_DATA_F0_3_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_405__PI_MR5_DATA_F0_3_SHIFT 0U
+#define LPDDR4__DENALI_PI_405__PI_MR5_DATA_F0_3_WIDTH 17U
+#define LPDDR4__PI_MR5_DATA_F0_3__REG DENALI_PI_405
+#define LPDDR4__PI_MR5_DATA_F0_3__FLD LPDDR4__DENALI_PI_405__PI_MR5_DATA_F0_3
+
+#define LPDDR4__DENALI_PI_406_READ_MASK 0xFF01FFFFU
+#define LPDDR4__DENALI_PI_406_WRITE_MASK 0xFF01FFFFU
+#define LPDDR4__DENALI_PI_406__PI_MR6_DATA_F0_3_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_406__PI_MR6_DATA_F0_3_SHIFT 0U
+#define LPDDR4__DENALI_PI_406__PI_MR6_DATA_F0_3_WIDTH 17U
+#define LPDDR4__PI_MR6_DATA_F0_3__REG DENALI_PI_406
+#define LPDDR4__PI_MR6_DATA_F0_3__FLD LPDDR4__DENALI_PI_406__PI_MR6_DATA_F0_3
+
+#define LPDDR4__DENALI_PI_406__PI_MR11_DATA_F0_3_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_406__PI_MR11_DATA_F0_3_SHIFT 24U
+#define LPDDR4__DENALI_PI_406__PI_MR11_DATA_F0_3_WIDTH 8U
+#define LPDDR4__PI_MR11_DATA_F0_3__REG DENALI_PI_406
+#define LPDDR4__PI_MR11_DATA_F0_3__FLD LPDDR4__DENALI_PI_406__PI_MR11_DATA_F0_3
+
+#define LPDDR4__DENALI_PI_407_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_407_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_407__PI_MR12_DATA_F0_3_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_407__PI_MR12_DATA_F0_3_SHIFT 0U
+#define LPDDR4__DENALI_PI_407__PI_MR12_DATA_F0_3_WIDTH 8U
+#define LPDDR4__PI_MR12_DATA_F0_3__REG DENALI_PI_407
+#define LPDDR4__PI_MR12_DATA_F0_3__FLD LPDDR4__DENALI_PI_407__PI_MR12_DATA_F0_3
+
+#define LPDDR4__DENALI_PI_407__PI_MR14_DATA_F0_3_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_407__PI_MR14_DATA_F0_3_SHIFT 8U
+#define LPDDR4__DENALI_PI_407__PI_MR14_DATA_F0_3_WIDTH 8U
+#define LPDDR4__PI_MR14_DATA_F0_3__REG DENALI_PI_407
+#define LPDDR4__PI_MR14_DATA_F0_3__FLD LPDDR4__DENALI_PI_407__PI_MR14_DATA_F0_3
+
+#define LPDDR4__DENALI_PI_407__PI_MR22_DATA_F0_3_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_407__PI_MR22_DATA_F0_3_SHIFT 16U
+#define LPDDR4__DENALI_PI_407__PI_MR22_DATA_F0_3_WIDTH 8U
+#define LPDDR4__PI_MR22_DATA_F0_3__REG DENALI_PI_407
+#define LPDDR4__PI_MR22_DATA_F0_3__FLD LPDDR4__DENALI_PI_407__PI_MR22_DATA_F0_3
+
+#define LPDDR4__DENALI_PI_407__PI_MR23_DATA_F0_3_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_407__PI_MR23_DATA_F0_3_SHIFT 24U
+#define LPDDR4__DENALI_PI_407__PI_MR23_DATA_F0_3_WIDTH 8U
+#define LPDDR4__PI_MR23_DATA_F0_3__REG DENALI_PI_407
+#define LPDDR4__PI_MR23_DATA_F0_3__FLD LPDDR4__DENALI_PI_407__PI_MR23_DATA_F0_3
+
+#define LPDDR4__DENALI_PI_408_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_408_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_408__PI_MR0_DATA_F1_3_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_408__PI_MR0_DATA_F1_3_SHIFT 0U
+#define LPDDR4__DENALI_PI_408__PI_MR0_DATA_F1_3_WIDTH 17U
+#define LPDDR4__PI_MR0_DATA_F1_3__REG DENALI_PI_408
+#define LPDDR4__PI_MR0_DATA_F1_3__FLD LPDDR4__DENALI_PI_408__PI_MR0_DATA_F1_3
+
+#define LPDDR4__DENALI_PI_409_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_409_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_409__PI_MR1_DATA_F1_3_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_409__PI_MR1_DATA_F1_3_SHIFT 0U
+#define LPDDR4__DENALI_PI_409__PI_MR1_DATA_F1_3_WIDTH 17U
+#define LPDDR4__PI_MR1_DATA_F1_3__REG DENALI_PI_409
+#define LPDDR4__PI_MR1_DATA_F1_3__FLD LPDDR4__DENALI_PI_409__PI_MR1_DATA_F1_3
+
+#define LPDDR4__DENALI_PI_410_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_410_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_410__PI_MR2_DATA_F1_3_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_410__PI_MR2_DATA_F1_3_SHIFT 0U
+#define LPDDR4__DENALI_PI_410__PI_MR2_DATA_F1_3_WIDTH 17U
+#define LPDDR4__PI_MR2_DATA_F1_3__REG DENALI_PI_410
+#define LPDDR4__PI_MR2_DATA_F1_3__FLD LPDDR4__DENALI_PI_410__PI_MR2_DATA_F1_3
+
+#define LPDDR4__DENALI_PI_411_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_411_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_411__PI_MR3_DATA_F1_3_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_411__PI_MR3_DATA_F1_3_SHIFT 0U
+#define LPDDR4__DENALI_PI_411__PI_MR3_DATA_F1_3_WIDTH 17U
+#define LPDDR4__PI_MR3_DATA_F1_3__REG DENALI_PI_411
+#define LPDDR4__PI_MR3_DATA_F1_3__FLD LPDDR4__DENALI_PI_411__PI_MR3_DATA_F1_3
+
+#define LPDDR4__DENALI_PI_412_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_412_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_412__PI_MR4_DATA_F1_3_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_412__PI_MR4_DATA_F1_3_SHIFT 0U
+#define LPDDR4__DENALI_PI_412__PI_MR4_DATA_F1_3_WIDTH 17U
+#define LPDDR4__PI_MR4_DATA_F1_3__REG DENALI_PI_412
+#define LPDDR4__PI_MR4_DATA_F1_3__FLD LPDDR4__DENALI_PI_412__PI_MR4_DATA_F1_3
+
+#define LPDDR4__DENALI_PI_413_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_413_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_413__PI_MR5_DATA_F1_3_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_413__PI_MR5_DATA_F1_3_SHIFT 0U
+#define LPDDR4__DENALI_PI_413__PI_MR5_DATA_F1_3_WIDTH 17U
+#define LPDDR4__PI_MR5_DATA_F1_3__REG DENALI_PI_413
+#define LPDDR4__PI_MR5_DATA_F1_3__FLD LPDDR4__DENALI_PI_413__PI_MR5_DATA_F1_3
+
+#define LPDDR4__DENALI_PI_414_READ_MASK 0xFF01FFFFU
+#define LPDDR4__DENALI_PI_414_WRITE_MASK 0xFF01FFFFU
+#define LPDDR4__DENALI_PI_414__PI_MR6_DATA_F1_3_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_414__PI_MR6_DATA_F1_3_SHIFT 0U
+#define LPDDR4__DENALI_PI_414__PI_MR6_DATA_F1_3_WIDTH 17U
+#define LPDDR4__PI_MR6_DATA_F1_3__REG DENALI_PI_414
+#define LPDDR4__PI_MR6_DATA_F1_3__FLD LPDDR4__DENALI_PI_414__PI_MR6_DATA_F1_3
+
+#define LPDDR4__DENALI_PI_414__PI_MR11_DATA_F1_3_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_414__PI_MR11_DATA_F1_3_SHIFT 24U
+#define LPDDR4__DENALI_PI_414__PI_MR11_DATA_F1_3_WIDTH 8U
+#define LPDDR4__PI_MR11_DATA_F1_3__REG DENALI_PI_414
+#define LPDDR4__PI_MR11_DATA_F1_3__FLD LPDDR4__DENALI_PI_414__PI_MR11_DATA_F1_3
+
+#define LPDDR4__DENALI_PI_415_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_415_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_415__PI_MR12_DATA_F1_3_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_415__PI_MR12_DATA_F1_3_SHIFT 0U
+#define LPDDR4__DENALI_PI_415__PI_MR12_DATA_F1_3_WIDTH 8U
+#define LPDDR4__PI_MR12_DATA_F1_3__REG DENALI_PI_415
+#define LPDDR4__PI_MR12_DATA_F1_3__FLD LPDDR4__DENALI_PI_415__PI_MR12_DATA_F1_3
+
+#define LPDDR4__DENALI_PI_415__PI_MR14_DATA_F1_3_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_415__PI_MR14_DATA_F1_3_SHIFT 8U
+#define LPDDR4__DENALI_PI_415__PI_MR14_DATA_F1_3_WIDTH 8U
+#define LPDDR4__PI_MR14_DATA_F1_3__REG DENALI_PI_415
+#define LPDDR4__PI_MR14_DATA_F1_3__FLD LPDDR4__DENALI_PI_415__PI_MR14_DATA_F1_3
+
+#define LPDDR4__DENALI_PI_415__PI_MR22_DATA_F1_3_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_415__PI_MR22_DATA_F1_3_SHIFT 16U
+#define LPDDR4__DENALI_PI_415__PI_MR22_DATA_F1_3_WIDTH 8U
+#define LPDDR4__PI_MR22_DATA_F1_3__REG DENALI_PI_415
+#define LPDDR4__PI_MR22_DATA_F1_3__FLD LPDDR4__DENALI_PI_415__PI_MR22_DATA_F1_3
+
+#define LPDDR4__DENALI_PI_415__PI_MR23_DATA_F1_3_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_415__PI_MR23_DATA_F1_3_SHIFT 24U
+#define LPDDR4__DENALI_PI_415__PI_MR23_DATA_F1_3_WIDTH 8U
+#define LPDDR4__PI_MR23_DATA_F1_3__REG DENALI_PI_415
+#define LPDDR4__PI_MR23_DATA_F1_3__FLD LPDDR4__DENALI_PI_415__PI_MR23_DATA_F1_3
+
+#define LPDDR4__DENALI_PI_416_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_416_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_416__PI_MR0_DATA_F2_3_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_416__PI_MR0_DATA_F2_3_SHIFT 0U
+#define LPDDR4__DENALI_PI_416__PI_MR0_DATA_F2_3_WIDTH 17U
+#define LPDDR4__PI_MR0_DATA_F2_3__REG DENALI_PI_416
+#define LPDDR4__PI_MR0_DATA_F2_3__FLD LPDDR4__DENALI_PI_416__PI_MR0_DATA_F2_3
+
+#define LPDDR4__DENALI_PI_417_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_417_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_417__PI_MR1_DATA_F2_3_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_417__PI_MR1_DATA_F2_3_SHIFT 0U
+#define LPDDR4__DENALI_PI_417__PI_MR1_DATA_F2_3_WIDTH 17U
+#define LPDDR4__PI_MR1_DATA_F2_3__REG DENALI_PI_417
+#define LPDDR4__PI_MR1_DATA_F2_3__FLD LPDDR4__DENALI_PI_417__PI_MR1_DATA_F2_3
+
+#define LPDDR4__DENALI_PI_418_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_418_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_418__PI_MR2_DATA_F2_3_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_418__PI_MR2_DATA_F2_3_SHIFT 0U
+#define LPDDR4__DENALI_PI_418__PI_MR2_DATA_F2_3_WIDTH 17U
+#define LPDDR4__PI_MR2_DATA_F2_3__REG DENALI_PI_418
+#define LPDDR4__PI_MR2_DATA_F2_3__FLD LPDDR4__DENALI_PI_418__PI_MR2_DATA_F2_3
+
+#define LPDDR4__DENALI_PI_419_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_419_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_419__PI_MR3_DATA_F2_3_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_419__PI_MR3_DATA_F2_3_SHIFT 0U
+#define LPDDR4__DENALI_PI_419__PI_MR3_DATA_F2_3_WIDTH 17U
+#define LPDDR4__PI_MR3_DATA_F2_3__REG DENALI_PI_419
+#define LPDDR4__PI_MR3_DATA_F2_3__FLD LPDDR4__DENALI_PI_419__PI_MR3_DATA_F2_3
+
+#define LPDDR4__DENALI_PI_420_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_420_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_420__PI_MR4_DATA_F2_3_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_420__PI_MR4_DATA_F2_3_SHIFT 0U
+#define LPDDR4__DENALI_PI_420__PI_MR4_DATA_F2_3_WIDTH 17U
+#define LPDDR4__PI_MR4_DATA_F2_3__REG DENALI_PI_420
+#define LPDDR4__PI_MR4_DATA_F2_3__FLD LPDDR4__DENALI_PI_420__PI_MR4_DATA_F2_3
+
+#define LPDDR4__DENALI_PI_421_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_421_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_421__PI_MR5_DATA_F2_3_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_421__PI_MR5_DATA_F2_3_SHIFT 0U
+#define LPDDR4__DENALI_PI_421__PI_MR5_DATA_F2_3_WIDTH 17U
+#define LPDDR4__PI_MR5_DATA_F2_3__REG DENALI_PI_421
+#define LPDDR4__PI_MR5_DATA_F2_3__FLD LPDDR4__DENALI_PI_421__PI_MR5_DATA_F2_3
+
+#define LPDDR4__DENALI_PI_422_READ_MASK 0xFF01FFFFU
+#define LPDDR4__DENALI_PI_422_WRITE_MASK 0xFF01FFFFU
+#define LPDDR4__DENALI_PI_422__PI_MR6_DATA_F2_3_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_422__PI_MR6_DATA_F2_3_SHIFT 0U
+#define LPDDR4__DENALI_PI_422__PI_MR6_DATA_F2_3_WIDTH 17U
+#define LPDDR4__PI_MR6_DATA_F2_3__REG DENALI_PI_422
+#define LPDDR4__PI_MR6_DATA_F2_3__FLD LPDDR4__DENALI_PI_422__PI_MR6_DATA_F2_3
+
+#define LPDDR4__DENALI_PI_422__PI_MR11_DATA_F2_3_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_422__PI_MR11_DATA_F2_3_SHIFT 24U
+#define LPDDR4__DENALI_PI_422__PI_MR11_DATA_F2_3_WIDTH 8U
+#define LPDDR4__PI_MR11_DATA_F2_3__REG DENALI_PI_422
+#define LPDDR4__PI_MR11_DATA_F2_3__FLD LPDDR4__DENALI_PI_422__PI_MR11_DATA_F2_3
+
+#define LPDDR4__DENALI_PI_423_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_423_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_423__PI_MR12_DATA_F2_3_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_423__PI_MR12_DATA_F2_3_SHIFT 0U
+#define LPDDR4__DENALI_PI_423__PI_MR12_DATA_F2_3_WIDTH 8U
+#define LPDDR4__PI_MR12_DATA_F2_3__REG DENALI_PI_423
+#define LPDDR4__PI_MR12_DATA_F2_3__FLD LPDDR4__DENALI_PI_423__PI_MR12_DATA_F2_3
+
+#define LPDDR4__DENALI_PI_423__PI_MR14_DATA_F2_3_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_423__PI_MR14_DATA_F2_3_SHIFT 8U
+#define LPDDR4__DENALI_PI_423__PI_MR14_DATA_F2_3_WIDTH 8U
+#define LPDDR4__PI_MR14_DATA_F2_3__REG DENALI_PI_423
+#define LPDDR4__PI_MR14_DATA_F2_3__FLD LPDDR4__DENALI_PI_423__PI_MR14_DATA_F2_3
+
+#define LPDDR4__DENALI_PI_423__PI_MR22_DATA_F2_3_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_423__PI_MR22_DATA_F2_3_SHIFT 16U
+#define LPDDR4__DENALI_PI_423__PI_MR22_DATA_F2_3_WIDTH 8U
+#define LPDDR4__PI_MR22_DATA_F2_3__REG DENALI_PI_423
+#define LPDDR4__PI_MR22_DATA_F2_3__FLD LPDDR4__DENALI_PI_423__PI_MR22_DATA_F2_3
+
+#define LPDDR4__DENALI_PI_423__PI_MR23_DATA_F2_3_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_423__PI_MR23_DATA_F2_3_SHIFT 24U
+#define LPDDR4__DENALI_PI_423__PI_MR23_DATA_F2_3_WIDTH 8U
+#define LPDDR4__PI_MR23_DATA_F2_3__REG DENALI_PI_423
+#define LPDDR4__PI_MR23_DATA_F2_3__FLD LPDDR4__DENALI_PI_423__PI_MR23_DATA_F2_3
+
+#endif /* REG_LPDDR4_PI_MACROS_H_ */
diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_address_slice_0_macros.h b/drivers/ram/k3-ddrss/am64/lpddr4_address_slice_0_macros.h
index f22a20a07c0..e233c5b1a30 100644
--- a/drivers/ram/k3-ddrss/16bit/lpddr4_address_slice_0_macros.h
+++ b/drivers/ram/k3-ddrss/am64/lpddr4_address_slice_0_macros.h
@@ -2,8 +2,8 @@
/*
* Cadence DDR Driver
*
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef REG_LPDDR4_ADDRESS_SLICE_0_MACROS_H_
diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_address_slice_1_macros.h b/drivers/ram/k3-ddrss/am64/lpddr4_address_slice_1_macros.h
index df5ab951669..8d5196a6ce0 100644
--- a/drivers/ram/k3-ddrss/16bit/lpddr4_address_slice_1_macros.h
+++ b/drivers/ram/k3-ddrss/am64/lpddr4_address_slice_1_macros.h
@@ -2,8 +2,8 @@
/*
* Cadence DDR Driver
*
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef REG_LPDDR4_ADDRESS_SLICE_1_MACROS_H_
diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_address_slice_2_macros.h b/drivers/ram/k3-ddrss/am64/lpddr4_address_slice_2_macros.h
index 924013e355d..5e781e68153 100644
--- a/drivers/ram/k3-ddrss/16bit/lpddr4_address_slice_2_macros.h
+++ b/drivers/ram/k3-ddrss/am64/lpddr4_address_slice_2_macros.h
@@ -2,8 +2,8 @@
/*
* Cadence DDR Driver
*
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef REG_LPDDR4_ADDRESS_SLICE_2_MACROS_H_
diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_ctl_regs_rw_masks.h b/drivers/ram/k3-ddrss/am64/lpddr4_am64_ctl_regs_rw_masks.h
index d46b77b23f3..9ea46fe48a4 100644
--- a/drivers/ram/k3-ddrss/16bit/lpddr4_ctl_regs_rw_masks.h
+++ b/drivers/ram/k3-ddrss/am64/lpddr4_am64_ctl_regs_rw_masks.h
@@ -2,8 +2,8 @@
/*
* Cadence DDR Driver
*
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef LPDDR4_RW_MASKS_H_
diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_16bit_if.h b/drivers/ram/k3-ddrss/am64/lpddr4_am64_if.h
index 94202c9d94b..4db31259523 100644
--- a/drivers/ram/k3-ddrss/16bit/lpddr4_16bit_if.h
+++ b/drivers/ram/k3-ddrss/am64/lpddr4_am64_if.h
@@ -2,12 +2,12 @@
/*
* Cadence DDR Driver
*
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
*/
-#ifndef LPDDR4_16BIT_IF_H
-#define LPDDR4_16BIT_IF_H
+#ifndef LPDDR4_AM64_IF_H
+#define LPDDR4_AM64_IF_H
#include <linux/types.h>
@@ -105,4 +105,4 @@ typedef enum {
LPDDR4_INTR_PHY_INDEP_ANY_VALID_BIT = 28U
} lpddr4_intr_phyindepinterrupt;
-#endif /* LPDDR4_16BIT_IF_H */
+#endif /* LPDDR4_AM64_IF_H */
diff --git a/drivers/ram/k3-ddrss/am64/lpddr4_am64_obj_if.h b/drivers/ram/k3-ddrss/am64/lpddr4_am64_obj_if.h
new file mode 100644
index 00000000000..e2a23c3637d
--- /dev/null
+++ b/drivers/ram/k3-ddrss/am64/lpddr4_am64_obj_if.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef LPDDR4_AM64_OBJ_IF_H
+#define LPDDR4_AM64_OBJ_IF_H
+
+#include "lpddr4_am64_if.h"
+
+#endif /* LPDDR4_AM64_OBJ_IF_H */
diff --git a/drivers/ram/k3-ddrss/am64/lpddr4_am64_structs_if.h b/drivers/ram/k3-ddrss/am64/lpddr4_am64_structs_if.h
new file mode 100644
index 00000000000..53b76f0888c
--- /dev/null
+++ b/drivers/ram/k3-ddrss/am64/lpddr4_am64_structs_if.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef LPDDR4_AM64_STRUCTS_IF_H
+#define LPDDR4_AM64_STRUCTS_IF_H
+
+#include <linux/types.h>
+#include "lpddr4_am64_if.h"
+
+#endif /* LPDDR4_AM64_STRUCTS_IF_H */
diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_ctl_regs.h b/drivers/ram/k3-ddrss/am64/lpddr4_ctl_regs.h
index 21e96c9a904..bd29fad1856 100644
--- a/drivers/ram/k3-ddrss/16bit/lpddr4_ctl_regs.h
+++ b/drivers/ram/k3-ddrss/am64/lpddr4_ctl_regs.h
@@ -2,8 +2,8 @@
/*
* Cadence DDR Driver
*
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef REG_LPDDR4_CTL_REGS_H_
diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_data_slice_0_macros.h b/drivers/ram/k3-ddrss/am64/lpddr4_data_slice_0_macros.h
index d3bf24e677b..c7358586c5b 100644
--- a/drivers/ram/k3-ddrss/16bit/lpddr4_data_slice_0_macros.h
+++ b/drivers/ram/k3-ddrss/am64/lpddr4_data_slice_0_macros.h
@@ -2,8 +2,8 @@
/*
* Cadence DDR Driver
*
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef REG_LPDDR4_DATA_SLICE_0_MACROS_H_
diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_data_slice_1_macros.h b/drivers/ram/k3-ddrss/am64/lpddr4_data_slice_1_macros.h
index d60bb6afe82..bf919afeea5 100644
--- a/drivers/ram/k3-ddrss/16bit/lpddr4_data_slice_1_macros.h
+++ b/drivers/ram/k3-ddrss/am64/lpddr4_data_slice_1_macros.h
@@ -2,8 +2,8 @@
/*
* Cadence DDR Driver
*
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef REG_LPDDR4_DATA_SLICE_1_MACROS_H_
diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_ddr_controller_macros.h b/drivers/ram/k3-ddrss/am64/lpddr4_ddr_controller_macros.h
index 3df803e9ef7..b0065268087 100644
--- a/drivers/ram/k3-ddrss/16bit/lpddr4_ddr_controller_macros.h
+++ b/drivers/ram/k3-ddrss/am64/lpddr4_ddr_controller_macros.h
@@ -2,8 +2,8 @@
/*
* Cadence DDR Driver
*
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef REG_LPDDR4_DDR_CONTROLLER_MACROS_H_
diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_phy_core_macros.h b/drivers/ram/k3-ddrss/am64/lpddr4_phy_core_macros.h
index dcfd7d9e860..1cf952913e1 100644
--- a/drivers/ram/k3-ddrss/16bit/lpddr4_phy_core_macros.h
+++ b/drivers/ram/k3-ddrss/am64/lpddr4_phy_core_macros.h
@@ -2,8 +2,8 @@
/*
* Cadence DDR Driver
*
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef REG_LPDDR4_PHY_CORE_MACROS_H_
diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_pi_macros.h b/drivers/ram/k3-ddrss/am64/lpddr4_pi_macros.h
index 9aa281af219..9c240d3a79d 100644
--- a/drivers/ram/k3-ddrss/16bit/lpddr4_pi_macros.h
+++ b/drivers/ram/k3-ddrss/am64/lpddr4_pi_macros.h
@@ -2,8 +2,8 @@
/*
* Cadence DDR Driver
*
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef REG_LPDDR4_PI_MACROS_H_
diff --git a/drivers/ram/k3-ddrss/cps_drv_lpddr4.h b/drivers/ram/k3-ddrss/cps_drv_lpddr4.h
index 298aa5e6cb8..94a16199c5a 100644
--- a/drivers/ram/k3-ddrss/cps_drv_lpddr4.h
+++ b/drivers/ram/k3-ddrss/cps_drv_lpddr4.h
@@ -2,8 +2,8 @@
/*
* Cadence DDR Driver
*
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef CPS_DRV_H_
diff --git a/drivers/ram/k3-ddrss/32bit/lpddr4_address_slice_0_macros.h b/drivers/ram/k3-ddrss/j721e/lpddr4_address_slice_0_macros.h
index 58ba340e787..7fd3f1a8ac6 100644
--- a/drivers/ram/k3-ddrss/32bit/lpddr4_address_slice_0_macros.h
+++ b/drivers/ram/k3-ddrss/j721e/lpddr4_address_slice_0_macros.h
@@ -2,8 +2,8 @@
/*
* Cadence DDR Driver
*
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef REG_LPDDR4_ADDRESS_SLICE_0_MACROS_H_
diff --git a/drivers/ram/k3-ddrss/32bit/lpddr4_ctl_regs.h b/drivers/ram/k3-ddrss/j721e/lpddr4_ctl_regs.h
index 4113608434c..9363035d29b 100644
--- a/drivers/ram/k3-ddrss/32bit/lpddr4_ctl_regs.h
+++ b/drivers/ram/k3-ddrss/j721e/lpddr4_ctl_regs.h
@@ -2,8 +2,8 @@
/*
* Cadence DDR Driver
*
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef REG_LPDDR4_CTL_REGS_H_
diff --git a/drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_0_macros.h b/drivers/ram/k3-ddrss/j721e/lpddr4_data_slice_0_macros.h
index ad45dd98d79..73c027b3382 100644
--- a/drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_0_macros.h
+++ b/drivers/ram/k3-ddrss/j721e/lpddr4_data_slice_0_macros.h
@@ -2,8 +2,8 @@
/*
* Cadence DDR Driver
*
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef REG_LPDDR4_DATA_SLICE_0_MACROS_H_
diff --git a/drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_1_macros.h b/drivers/ram/k3-ddrss/j721e/lpddr4_data_slice_1_macros.h
index 5385e1e87b1..c1999750a2d 100644
--- a/drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_1_macros.h
+++ b/drivers/ram/k3-ddrss/j721e/lpddr4_data_slice_1_macros.h
@@ -2,8 +2,8 @@
/*
* Cadence DDR Driver
*
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef REG_LPDDR4_DATA_SLICE_1_MACROS_H_
diff --git a/drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_2_macros.h b/drivers/ram/k3-ddrss/j721e/lpddr4_data_slice_2_macros.h
index f6edad4eab9..ff534b007b6 100644
--- a/drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_2_macros.h
+++ b/drivers/ram/k3-ddrss/j721e/lpddr4_data_slice_2_macros.h
@@ -2,8 +2,8 @@
/*
* Cadence DDR Driver
*
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef REG_LPDDR4_DATA_SLICE_2_MACROS_H_
diff --git a/drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_3_macros.h b/drivers/ram/k3-ddrss/j721e/lpddr4_data_slice_3_macros.h
index 73e5f71df97..800c2a8e407 100644
--- a/drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_3_macros.h
+++ b/drivers/ram/k3-ddrss/j721e/lpddr4_data_slice_3_macros.h
@@ -2,8 +2,8 @@
/*
* Cadence DDR Driver
*
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef REG_LPDDR4_DATA_SLICE_3_MACROS_H_
diff --git a/drivers/ram/k3-ddrss/32bit/lpddr4_ddr_controller_macros.h b/drivers/ram/k3-ddrss/j721e/lpddr4_ddr_controller_macros.h
index 4e33d04d1c2..f0a4fa00c74 100644
--- a/drivers/ram/k3-ddrss/32bit/lpddr4_ddr_controller_macros.h
+++ b/drivers/ram/k3-ddrss/j721e/lpddr4_ddr_controller_macros.h
@@ -2,8 +2,8 @@
/*
* Cadence DDR Driver
*
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef REG_LPDDR4_DDR_CONTROLLER_MACROS_H_
diff --git a/drivers/ram/k3-ddrss/32bit/lpddr4_ctl_regs_rw_masks.h b/drivers/ram/k3-ddrss/j721e/lpddr4_j721e_ctl_regs_rw_masks.h
index 71122946b44..f760ed84200 100644
--- a/drivers/ram/k3-ddrss/32bit/lpddr4_ctl_regs_rw_masks.h
+++ b/drivers/ram/k3-ddrss/j721e/lpddr4_j721e_ctl_regs_rw_masks.h
@@ -2,8 +2,8 @@
/*
* Cadence DDR Driver
*
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef LPDDR4_RW_MASKS_H_
diff --git a/drivers/ram/k3-ddrss/32bit/lpddr4_32bit_if.h b/drivers/ram/k3-ddrss/j721e/lpddr4_j721e_if.h
index f14ca245ee9..3d738c5763d 100644
--- a/drivers/ram/k3-ddrss/32bit/lpddr4_32bit_if.h
+++ b/drivers/ram/k3-ddrss/j721e/lpddr4_j721e_if.h
@@ -2,12 +2,12 @@
/*
* Cadence DDR Driver
*
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
*/
-#ifndef LPDDR4_32BIT_IF_H
-#define LPDDR4_32BIT_IF_H
+#ifndef LPDDR4_J721E_IF_H
+#define LPDDR4_J721E_IF_H
#include <linux/types.h>
@@ -88,4 +88,4 @@ typedef enum {
LPDDR4_INTR_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT = 17U
} lpddr4_intr_phyindepinterrupt;
-#endif /* LPDDR4_32BIT_IF_H */
+#endif /* LPDDR4_J721E_IF_H */
diff --git a/drivers/ram/k3-ddrss/j721e/lpddr4_j721e_obj_if.h b/drivers/ram/k3-ddrss/j721e/lpddr4_j721e_obj_if.h
new file mode 100644
index 00000000000..8b38cebb0f6
--- /dev/null
+++ b/drivers/ram/k3-ddrss/j721e/lpddr4_j721e_obj_if.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef LPDDR4_J721E_OBJ_IF_H
+#define LPDDR4_J721E_OBJ_IF_H
+
+#include "lpddr4_j721e_if.h"
+
+#endif /* LPDDR4_J721E_OBJ_IF_H */
diff --git a/drivers/ram/k3-ddrss/j721e/lpddr4_j721e_structs_if.h b/drivers/ram/k3-ddrss/j721e/lpddr4_j721e_structs_if.h
new file mode 100644
index 00000000000..c8771952817
--- /dev/null
+++ b/drivers/ram/k3-ddrss/j721e/lpddr4_j721e_structs_if.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef LPDDR4_J721E_STRUCTS_IF_H
+#define LPDDR4_J721E_STRUCTS_IF_H
+
+#include <linux/types.h>
+#include "lpddr4_j721e_if.h"
+
+#endif /* LPDDR4_J721E_STRUCTS_IF_H */
diff --git a/drivers/ram/k3-ddrss/32bit/lpddr4_phy_core_macros.h b/drivers/ram/k3-ddrss/j721e/lpddr4_phy_core_macros.h
index d8c7a5222e5..d1a9e74a47a 100644
--- a/drivers/ram/k3-ddrss/32bit/lpddr4_phy_core_macros.h
+++ b/drivers/ram/k3-ddrss/j721e/lpddr4_phy_core_macros.h
@@ -2,8 +2,8 @@
/*
* Cadence DDR Driver
*
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef REG_LPDDR4_PHY_CORE_MACROS_H_
diff --git a/drivers/ram/k3-ddrss/32bit/lpddr4_pi_macros.h b/drivers/ram/k3-ddrss/j721e/lpddr4_pi_macros.h
index 7f1754a499f..8e428cb8486 100644
--- a/drivers/ram/k3-ddrss/32bit/lpddr4_pi_macros.h
+++ b/drivers/ram/k3-ddrss/j721e/lpddr4_pi_macros.h
@@ -2,8 +2,8 @@
/*
* Cadence DDR Driver
*
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef REG_LPDDR4_PI_MACROS_H_
diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c b/drivers/ram/k3-ddrss/k3-ddrss.c
index e8b7aec9e0b..7e445d2b737 100644
--- a/drivers/ram/k3-ddrss/k3-ddrss.c
+++ b/drivers/ram/k3-ddrss/k3-ddrss.c
@@ -706,6 +706,7 @@ static const struct k3_ddrss_data j721s2_data = {
};
static const struct udevice_id k3_ddrss_ids[] = {
+ {.compatible = "ti,am62a-ddrss", .data = (ulong)&k3_data, },
{.compatible = "ti,am64-ddrss", .data = (ulong)&k3_data, },
{.compatible = "ti,j721e-ddrss", .data = (ulong)&k3_data, },
{.compatible = "ti,j721s2-ddrss", .data = (ulong)&j721s2_data, },
diff --git a/drivers/ram/k3-ddrss/lpddr4.c b/drivers/ram/k3-ddrss/lpddr4.c
index 78ad966a175..11ef242a37b 100644
--- a/drivers/ram/k3-ddrss/lpddr4.c
+++ b/drivers/ram/k3-ddrss/lpddr4.c
@@ -2,8 +2,8 @@
/*
* Cadence DDR Driver
*
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <errno.h>
@@ -13,14 +13,6 @@
#include "lpddr4.h"
#include "lpddr4_structs_if.h"
-#ifndef LPDDR4_CUSTOM_TIMEOUT_DELAY
-#define LPDDR4_CUSTOM_TIMEOUT_DELAY 100000000U
-#endif
-
-#ifndef LPDDR4_CPS_NS_DELAY_TIME
-#define LPDDR4_CPS_NS_DELAY_TIME 10000000U
-#endif
-
static u32 lpddr4_pollphyindepirq(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt irqbit, u32 delay);
static u32 lpddr4_pollandackirq(const lpddr4_privatedata *pd);
static u32 lpddr4_startsequencecontroller(const lpddr4_privatedata *pd);
@@ -51,10 +43,7 @@ static void lpddr4_writelpiwakeuptime(lpddr4_ctlregs *ctlregbase, const lpddr4_l
static void lpddr4_updatefsp2refrateparams(const lpddr4_privatedata *pd, const u32 *tref, const u32 *tras_max);
static void lpddr4_updatefsp1refrateparams(const lpddr4_privatedata *pd, const u32 *tref, const u32 *tras_max);
static void lpddr4_updatefsp0refrateparams(const lpddr4_privatedata *pd, const u32 *tref, const u32 *tras_max);
-#ifdef REG_WRITE_VERIF
static u32 lpddr4_getphyrwmask(u32 regoffset);
-static u32 lpddr4_verifyregwrite(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoffset, u32 regvalue);
-#endif
u32 lpddr4_pollctlirq(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt irqbit, u32 delay)
{
@@ -202,8 +191,6 @@ u32 lpddr4_readreg(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoff
return result;
}
-#ifdef REG_WRITE_VERIF
-
static u32 lpddr4_getphyrwmask(u32 regoffset)
{
u32 rwmask = 0U;
@@ -231,33 +218,43 @@ static u32 lpddr4_getphyrwmask(u32 regoffset)
return rwmask;
}
-static u32 lpddr4_verifyregwrite(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoffset, u32 regvalue)
+u32 lpddr4_deferredregverify(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regvalues[], u16 regnum[], u16 regcount)
{
u32 result = (u32)0;
+ u32 aindex;
u32 regreadval = 0U;
u32 rwmask = 0U;
- result = lpddr4_readreg(pd, cpp, regoffset, &regreadval);
+ result = lpddr4_deferredregverifysf(pd, cpp);
+ if ((regvalues == (u32 *)NULL) || (regnum == (u16 *)NULL))
+ result = EINVAL;
if (result == (u32)0) {
- switch (cpp) {
- case LPDDR4_PHY_INDEP_REGS:
- rwmask = g_lpddr4_pi_rw_mask[regoffset];
- break;
- case LPDDR4_PHY_REGS:
- rwmask = lpddr4_getphyrwmask(regoffset);
- break;
- default:
- rwmask = g_lpddr4_ddr_controller_rw_mask[regoffset];
- break;
+ for (aindex = 0; aindex < regcount; aindex++) {
+ result = lpddr4_readreg(pd, cpp, (u32)regnum[aindex], &regreadval);
+
+ if (result == (u32)0) {
+ switch (cpp) {
+ case LPDDR4_PHY_INDEP_REGS:
+ rwmask = g_lpddr4_pi_rw_mask[(u32)regnum[aindex]];
+ break;
+ case LPDDR4_PHY_REGS:
+ rwmask = lpddr4_getphyrwmask((u32)regnum[aindex]);
+ break;
+ default:
+ rwmask = g_lpddr4_ddr_controller_rw_mask[(u32)regnum[aindex]];
+ break;
+ }
+
+ if ((rwmask & regreadval) != ((u32)(regvalues[aindex]) & rwmask)) {
+ result = EIO;
+ break;
+ }
+ }
}
-
- if ((rwmask & regreadval) != (regvalue & rwmask))
- result = EIO;
}
return result;
}
-#endif
u32 lpddr4_writereg(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoffset, u32 regvalue)
{
@@ -284,11 +281,6 @@ u32 lpddr4_writereg(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regof
CPS_REG_WRITE(lpddr4_addoffset(&(ctlregbase->DENALI_PI_0), regoffset), regvalue);
}
}
-#ifdef REG_WRITE_VERIF
- if (result == (u32)0)
- result = lpddr4_verifyregwrite(pd, cpp, regoffset, regvalue);
-
-#endif
return result;
}
@@ -346,9 +338,6 @@ u32 lpddr4_setmmrregister(const lpddr4_privatedata *pd, u32 writemoderegval, u8
}
}
-#ifdef ASILC
-#endif
-
return result;
}
diff --git a/drivers/ram/k3-ddrss/lpddr4.h b/drivers/ram/k3-ddrss/lpddr4.h
index 5b77ea9e6e9..0fcd6d78ef8 100644
--- a/drivers/ram/k3-ddrss/lpddr4.h
+++ b/drivers/ram/k3-ddrss/lpddr4.h
@@ -2,8 +2,8 @@
/*
* Cadence DDR Driver
*
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef LPDDR4_H
@@ -11,19 +11,13 @@
#include "lpddr4_ctl_regs.h"
#include "lpddr4_sanity.h"
-#ifdef CONFIG_K3_AM64_DDRSS
-#include "lpddr4_16bit.h"
-#include "lpddr4_16bit_sanity.h"
-#else
-#include "lpddr4_32bit.h"
-#include "lpddr4_32bit_sanity.h"
-#endif
-#ifdef REG_WRITE_VERIF
-#include "lpddr4_ctl_regs_rw_masks.h"
-#endif
-#ifdef __cplusplus
-extern "C" {
+#if defined (CONFIG_K3_AM64_DDRSS) || defined (CONFIG_K3_AM62A_DDRSS)
+#include "lpddr4_am6x.h"
+#include "lpddr4_am6x_sanity.h"
+#else
+#include "lpddr4_j721e.h"
+#include "lpddr4_j721e_sanity.h"
#endif
#define PRODUCT_ID (0x1046U)
@@ -56,6 +50,14 @@ extern "C" {
#define CDN_TRUE 1U
#define CDN_FALSE 0U
+#ifndef LPDDR4_CUSTOM_TIMEOUT_DELAY
+#define LPDDR4_CUSTOM_TIMEOUT_DELAY 100000000U
+#endif
+
+#ifndef LPDDR4_CPS_NS_DELAY_TIME
+#define LPDDR4_CPS_NS_DELAY_TIME 10000000U
+#endif
+
void lpddr4_setsettings(lpddr4_ctlregs *ctlregbase, const bool errorfound);
volatile u32 *lpddr4_addoffset(volatile u32 *addr, u32 regoffset);
u32 lpddr4_pollctlirq(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt irqbit, u32 delay);
@@ -66,8 +68,5 @@ u32 lpddr4_enablepiinitiator(const lpddr4_privatedata *pd);
void lpddr4_checkwrlvlerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr);
u32 lpddr4_checkmmrreaderror(const lpddr4_privatedata *pd, u64 *mmrvalue, u8 *mrrstatus);
u32 lpddr4_getdslicemask(u32 dslicenum, u32 arrayoffset);
-#ifdef __cplusplus
-}
-#endif
#endif /* LPDDR4_H */
diff --git a/drivers/ram/k3-ddrss/lpddr4_16bit.h b/drivers/ram/k3-ddrss/lpddr4_16bit.h
deleted file mode 100644
index d663389e608..00000000000
--- a/drivers/ram/k3-ddrss/lpddr4_16bit.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Cadence DDR Driver
- *
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-#ifndef LPDDR4_16BIT_H
-#define LPDDR4_16BIT_H
-
-#define DSLICE_NUM (2U)
-#define ASLICE_NUM (3U)
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define DSLICE0_REG_COUNT (126U)
-#define DSLICE1_REG_COUNT (126U)
-#define ASLICE0_REG_COUNT (42U)
-#define ASLICE1_REG_COUNT (42U)
-#define ASLICE2_REG_COUNT (42U)
-#define PHY_CORE_REG_COUNT (126U)
-
-#define GRP_SHIFT 1
-#define INT_SHIFT 2
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LPDDR4_16BIT_H */
diff --git a/drivers/ram/k3-ddrss/lpddr4_am62a_ctl_regs_rw_masks.c b/drivers/ram/k3-ddrss/lpddr4_am62a_ctl_regs_rw_masks.c
new file mode 100644
index 00000000000..2b871cc76d7
--- /dev/null
+++ b/drivers/ram/k3-ddrss/lpddr4_am62a_ctl_regs_rw_masks.c
@@ -0,0 +1,1726 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include <linux/types.h>
+#include <lpddr4_am62a_ctl_regs_rw_masks.h>
+
+u32 g_lpddr4_ddr_controller_rw_mask[] = {
+ 0x00000F01U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x01FFFFFFU,
+ 0x03030300U,
+ 0x01030100U,
+ 0x1F1F013FU,
+ 0x0303031FU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x0000FFFFU,
+ 0xFFFFFF01U,
+ 0x0001FFFFU,
+ 0x000F7FFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFF00FFFFU,
+ 0x0000FFFFU,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x0F3F7F7FU,
+ 0xFFFFFFFFU,
+ 0x0F3F7F7FU,
+ 0xFFFFFFFFU,
+ 0x0F3F7F7FU,
+ 0xFFFFFFFFU,
+ 0xFF1F1F07U,
+ 0x0001FFFFU,
+ 0x3F3F01FFU,
+ 0x1F01FFFFU,
+ 0x01FFFFFFU,
+ 0x3F3F01FFU,
+ 0x1F01FFFFU,
+ 0x01FFFFFFU,
+ 0x3F3F01FFU,
+ 0xFF01FFFFU,
+ 0x00FFFFFFU,
+ 0x1F0FFFFFU,
+ 0xFFFF3FFFU,
+ 0x0000FFFFU,
+ 0x1F0FFFFFU,
+ 0xFFFF3FFFU,
+ 0x0000FFFFU,
+ 0x1F0FFFFFU,
+ 0x07073FFFU,
+ 0xFFFF0107U,
+ 0xFFFFFFFFU,
+ 0x0101010FU,
+ 0x3FFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x0301FFFFU,
+ 0x00010101U,
+ 0x03FFFFFFU,
+ 0x01000000U,
+ 0x03FF3F07U,
+ 0x000FFFFFU,
+ 0x000003FFU,
+ 0x000FFFFFU,
+ 0x000003FFU,
+ 0x000FFFFFU,
+ 0x000FFFFFU,
+ 0x000003FFU,
+ 0x000FFFFFU,
+ 0x000003FFU,
+ 0x000FFFFFU,
+ 0x000003FFU,
+ 0x010FFFFFU,
+ 0x0FFFFF01U,
+ 0x001F1F01U,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x1F1F1FFFU,
+ 0x1F1F1F0FU,
+ 0x1F1F1F0FU,
+ 0x1F011F0FU,
+ 0x00011F01U,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x07FFFFFFU,
+ 0x1F1F1F1FU,
+ 0x1F07FF1FU,
+ 0x1F1F1F1FU,
+ 0x1F1F07FFU,
+ 0x1F1F1F1FU,
+ 0x01011F1FU,
+ 0x7F000701U,
+ 0x00FFFF01U,
+ 0xFFFFFFFFU,
+ 0xFF070700U,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x0000FFFFU,
+ 0x000FFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x0000FFFFU,
+ 0x000FFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x0000FFFFU,
+ 0x010FFFFFU,
+ 0x00010100U,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x01FFFFFFU,
+ 0x0000FF00U,
+ 0x0001FFFFU,
+ 0x0F03FFFFU,
+ 0x00000001U,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFF0100U,
+ 0xFFFFFFFFU,
+ 0x0F0F0003U,
+ 0x0F0F0F0FU,
+ 0x0F0F0F0FU,
+ 0x0F0F0F0FU,
+ 0x0F0F0F0FU,
+ 0x0F0F0F0FU,
+ 0x0F0F0F0FU,
+ 0x00013F0FU,
+ 0x0FFF0FFFU,
+ 0x0F0F0007U,
+ 0x000FFF07U,
+ 0xFFFF0FFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x01010101U,
+ 0x0101FF01U,
+ 0x00000107U,
+ 0xFFFFFFFFU,
+ 0x00FFFF0FU,
+ 0x00000303U,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x07FFFFFFU,
+ 0x01FFFF00U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x03010000U,
+ 0x03FF03FFU,
+ 0x1F1F03FFU,
+ 0x000FFFFFU,
+ 0x03FF03FFU,
+ 0x1F1F03FFU,
+ 0x000FFFFFU,
+ 0x03FF03FFU,
+ 0x1F1F03FFU,
+ 0x000FFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x01FFFF01U,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x01FFFF00U,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0xFF01FFFFU,
+ 0xFFFFFFFFU,
+ 0x01FFFFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0xFF01FFFFU,
+ 0xFFFFFFFFU,
+ 0x01FFFFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0101FFFFU,
+ 0x00000101U,
+ 0x01010101U,
+ 0x03010101U,
+ 0x3F000003U,
+ 0x00000101U,
+ 0xFFFFFFFFU,
+ 0x00000007U,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x00000007U,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x000FFF00U,
+ 0x1F000000U,
+ 0x1F1F1F1FU,
+ 0xFFFF070FU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x000FFF00U,
+ 0x0FFF0FFFU,
+ 0x007F0FFFU,
+ 0x0FFF0FFFU,
+ 0x0FFF0FFFU,
+ 0x000FFF7FU,
+ 0x0FFF0FFFU,
+ 0x037F0FFFU,
+ 0x0FFF0000U,
+ 0x0FFF0FFFU,
+ 0x03030101U,
+ 0x03030303U,
+ 0x0F0F0707U,
+ 0xFFFFFFFFU,
+ 0x00FFFF03U,
+ 0xFFFFFFFFU,
+ 0x03FFFF03U,
+ 0x1F011F01U,
+ 0x0101FFFFU,
+ 0x01010101U,
+ 0x03010101U,
+ 0x0301011FU,
+ 0x07010F03U,
+ 0x0F0F0F07U,
+ 0x0F0F0F0FU,
+ 0x03011F0FU,
+ 0x01010000U,
+ 0x01030303U,
+ 0x00000101U,
+ 0x01000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0xFFFFFFFFU,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x0000FFFFU,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0xFF000000U,
+ 0x0FFF0F0FU,
+ 0x0F0FFF0FU,
+ 0x01010101U,
+ 0x033F3F3FU,
+ 0x3F030303U,
+ 0x1F1F3F3FU,
+ 0x1F1F1F1FU,
+ 0x1F1F1F1FU,
+ 0x1F1F1F1FU,
+ 0x1F1F1F1FU,
+ 0x0F1F1F1FU,
+ 0x0F070F07U,
+ 0x07010107U,
+ 0xFF000007U,
+ 0x001FFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x007FFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFF070FU,
+ 0xFF7FFFFFU,
+ 0x001FFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x007FFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFF070FU,
+ 0xFF7FFFFFU,
+ 0x001FFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x007FFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFF070FU,
+ 0x007FFFFFU,
+ 0x00FFFFFFU,
+ 0x0FFFFF03U,
+ 0x01FF070FU,
+ 0x07070701U,
+ 0x0F070707U,
+ 0x0F0F0F0FU,
+ 0x0F0F0F0FU,
+ 0x0F0F0F0FU,
+ 0x0F0F0F0FU,
+ 0xFF0F0F0FU,
+ 0x0000FFFFU
+};
+
+u32 g_lpddr4_pi_rw_mask[] = {
+ 0x00000F01U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x01000000U,
+ 0xFFFF0301U,
+ 0x030100FFU,
+ 0x00000101U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x0000011FU,
+ 0xFFFFFFFFU,
+ 0x010F0101U,
+ 0x0F011F0FU,
+ 0x0101070FU,
+ 0x000FFFFFU,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000007U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x01000000U,
+ 0x01010101U,
+ 0x3F030F00U,
+ 0x01FFFF3FU,
+ 0x0F010F01U,
+ 0x00FF0001U,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x0F0F0F1FU,
+ 0x0000000FU,
+ 0x03FFFFFFU,
+ 0x00000F07U,
+ 0x0000030FU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x0101010FU,
+ 0x01010101U,
+ 0x000F0F01U,
+ 0x000003FFU,
+ 0xFFFFFFFFU,
+ 0x0000FF0FU,
+ 0xFFFFFFFFU,
+ 0x00FFFF00U,
+ 0x0F0FFFFFU,
+ 0x01011F1FU,
+ 0x0F000000U,
+ 0x030F0103U,
+ 0x01010101U,
+ 0x0000FF0FU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFF0001U,
+ 0x1F1F3F1FU,
+ 0xFF0F0F01U,
+ 0x017F1FFFU,
+ 0xFF01FFFFU,
+ 0x01010103U,
+ 0x0F0701FFU,
+ 0x1F1F0F01U,
+ 0x030F0001U,
+ 0x000000FFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x0101FFFFU,
+ 0x00030001U,
+ 0xFFFFFFFFU,
+ 0x00010107U,
+ 0x010003FFU,
+ 0x01010101U,
+ 0x07030F01U,
+ 0x0F0F0F1FU,
+ 0x0F0F0F0FU,
+ 0x0F0F0F0FU,
+ 0x0F0F0F0FU,
+ 0x0F0F0F0FU,
+ 0x0000000FU,
+ 0x00000000U,
+ 0x00000000U,
+ 0x3FFFFFFFU,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x011F3F00U,
+ 0x1F1F1F1FU,
+ 0x1F1F1F1FU,
+ 0x0303011FU,
+ 0x00010303U,
+ 0x0700FFFFU,
+ 0xFF000001U,
+ 0x00000101U,
+ 0xFFFFFFFFU,
+ 0x0000FF07U,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x0FFF0000U,
+ 0xFFFFFFFFU,
+ 0x0000000FU,
+ 0xFFFFFFFFU,
+ 0x0000000FU,
+ 0xFFFFFFFFU,
+ 0x0000000FU,
+ 0xFFFFFFFFU,
+ 0x0000000FU,
+ 0xFFFFFFFFU,
+ 0x0000000FU,
+ 0xFFFFFFFFU,
+ 0x0000000FU,
+ 0xFFFFFFFFU,
+ 0x0000000FU,
+ 0xFFFFFFFFU,
+ 0x0000000FU,
+ 0xFFFFFFFFU,
+ 0x0000000FU,
+ 0xFFFFFFFFU,
+ 0x0303070FU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x0000007FU,
+ 0x3FFFFFFFU,
+ 0x3FFFFFFFU,
+ 0x3FFFFFFFU,
+ 0x3FFFFFFFU,
+ 0x3FFFFFFFU,
+ 0x3FFFFFFFU,
+ 0x3FFFFFFFU,
+ 0x3FFFFFFFU,
+ 0x0101010FU,
+ 0x00010101U,
+ 0x01010101U,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFF0101U,
+ 0x000000FFU,
+ 0x03FFFFFFU,
+ 0x00000100U,
+ 0x0001FFFFU,
+ 0x01000000U,
+ 0x0100000FU,
+ 0x00010F07U,
+ 0x0F00010FU,
+ 0x010F0001U,
+ 0x00010F00U,
+ 0x0F00010FU,
+ 0x010F0001U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x011F0000U,
+ 0x01010103U,
+ 0x01010101U,
+ 0x01010101U,
+ 0x01010101U,
+ 0x01010101U,
+ 0x00FF0101U,
+ 0x000001FFU,
+ 0x0000001FU,
+ 0x0F011F01U,
+ 0x01010101U,
+ 0xFFFF0701U,
+ 0xFFFFFFFFU,
+ 0x00FFFFFFU,
+ 0x000000FFU,
+ 0x000000FFU,
+ 0x000FFFFFU,
+ 0x0FFF0FFFU,
+ 0xFF0F3F7FU,
+ 0x0F3F7F7FU,
+ 0x3F7F7FFFU,
+ 0x007FFF0FU,
+ 0x000003FFU,
+ 0x000FFFFFU,
+ 0x000003FFU,
+ 0x000FFFFFU,
+ 0x000003FFU,
+ 0x0F0FFFFFU,
+ 0x03030F0FU,
+ 0x0003FF03U,
+ 0x03FF03FFU,
+ 0x01FF01FFU,
+ 0x0F0F01FFU,
+ 0x0F0F0F0FU,
+ 0x3F3F3F3FU,
+ 0x03033F3FU,
+ 0x03030303U,
+ 0x03FFFFFFU,
+ 0x03030303U,
+ 0x03030303U,
+ 0xFF030303U,
+ 0xFFFFFFFFU,
+ 0x070707FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x1F030303U,
+ 0x001F3FFFU,
+ 0x001F3FFFU,
+ 0x1F1F3FFFU,
+ 0x03FF03FFU,
+ 0x03FF1F1FU,
+ 0x1F1F03FFU,
+ 0x03FF03FFU,
+ 0x7F7F7F7FU,
+ 0x0F0F7F7FU,
+ 0xFF1F0F0FU,
+ 0xFF1F0F1FU,
+ 0xFF1F0F1FU,
+ 0xFFFFFF1FU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x3FFFFFFFU,
+ 0x003F03FFU,
+ 0x003F03FFU,
+ 0x030303FFU,
+ 0x0003FF03U,
+ 0x7F7F03FFU,
+ 0x1F03030FU,
+ 0x03FFFFFFU,
+ 0x7F7F03FFU,
+ 0x1F03030FU,
+ 0x03FFFFFFU,
+ 0x7F7F03FFU,
+ 0x1F03030FU,
+ 0x0303FFFFU,
+ 0xFFFFFF03U,
+ 0x00FF3F1FU,
+ 0x000FFFFFU,
+ 0x3F0F01FFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFF3F1FFFU,
+ 0x000FFFFFU,
+ 0x3F0F01FFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFF3F1FFFU,
+ 0x000FFFFFU,
+ 0x3F0F01FFU,
+ 0xFFFFFFFFU,
+ 0x0000FFFFU,
+ 0x001FFFFFU,
+ 0xFFFFFFFFU,
+ 0x001FFFFFU,
+ 0xFFFFFFFFU,
+ 0x001FFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x3F3FFFFFU,
+ 0x00FFFF3FU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x0000FFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x0000FFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x0000FFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x0FFFFFFFU,
+ 0x0FFF0FFFU,
+ 0x000FFF7FU,
+ 0x0FFF0FFFU,
+ 0x000FFF7FU,
+ 0x0FFF0FFFU,
+ 0x000FFF7FU,
+ 0x0FFF0FFFU,
+ 0x030F0F0FU,
+ 0x07070303U,
+ 0x0F0F0707U,
+ 0x0F0F0F0FU,
+ 0x7F7F0F0FU,
+ 0x7F7F7F7FU,
+ 0x7F7F7F7FU,
+ 0x7F7F7F7FU,
+ 0x03037F7FU,
+ 0x00000303U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0xFFFF0000U,
+ 0x00FFFFFFU,
+ 0xFF01FFFFU,
+ 0xFFFFFFFFU,
+ 0x01FFFFFFU,
+ 0xFFFFFFFFU,
+ 0x0000FFFFU,
+ 0xFF01FFFFU,
+ 0xFFFFFFFFU,
+ 0x01FFFFFFU,
+ 0x1F1F1FFFU,
+ 0x1F1F1F1FU,
+ 0x1F1F1F1FU,
+ 0x1F1F1F1FU,
+ 0x01FFFF1FU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0F01FFFFU,
+ 0x0F0F0F0FU,
+ 0x000F0F0FU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0xFF01FFFFU,
+ 0xFFFFFFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0xFF01FFFFU,
+ 0xFFFFFFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0xFF01FFFFU,
+ 0xFFFFFFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0xFF01FFFFU,
+ 0xFFFFFFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0xFF01FFFFU,
+ 0xFFFFFFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0xFF01FFFFU,
+ 0xFFFFFFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0xFF01FFFFU,
+ 0xFFFFFFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0xFF01FFFFU,
+ 0xFFFFFFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0xFF01FFFFU,
+ 0xFFFFFFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0xFF01FFFFU,
+ 0xFFFFFFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0xFF01FFFFU,
+ 0xFFFFFFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0xFF01FFFFU,
+ 0xFFFFFFFFU
+};
+
+u32 g_lpddr4_data_slice_0_rw_mask[] = {
+ 0x07FF7F07U,
+ 0x0703FF0FU,
+ 0x010303FFU,
+ 0x3F3F3F3FU,
+ 0x3F3F3F3FU,
+ 0x01030F3FU,
+ 0x1F1F0301U,
+ 0x1F030F0FU,
+ 0x0101FF03U,
+ 0x00000001U,
+ 0xFFFFFFFFU,
+ 0x00000000U,
+ 0x7F0101FFU,
+ 0x010101FFU,
+ 0x03FF003FU,
+ 0x01FF000FU,
+ 0x01FF0701U,
+ 0x00000003U,
+ 0x00000000U,
+ 0x00000301U,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x070F0107U,
+ 0x0F0F0F0FU,
+ 0x3F030001U,
+ 0x0F3FFF0FU,
+ 0x1F030F3FU,
+ 0x03FFFFFFU,
+ 0x00073FFFU,
+ 0x0F0F07FFU,
+ 0x000FFFFFU,
+ 0x000001FFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x0001FFFFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x00000001U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x7FFFFFFFU,
+ 0x0000003FU,
+ 0x00000000U,
+ 0x00000000U,
+ 0x01FF01FFU,
+ 0x01FF01FFU,
+ 0x01FF01FFU,
+ 0x01FF01FFU,
+ 0x000001FFU,
+ 0x0003FFFFU,
+ 0x01FF01FFU,
+ 0xFF1F07FFU,
+ 0xFF3F03FFU,
+ 0x010101FFU,
+ 0x01010703U,
+ 0x00000101U,
+ 0x07FFFF07U,
+ 0x7F03FFFFU,
+ 0xFF01037FU,
+ 0x07FF07FFU,
+ 0x0103FFFFU,
+ 0x1F1F0F3FU,
+ 0x1F1F1F1FU,
+ 0x1F1F1F1FU,
+ 0x007F1F1FU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x1F0703FFU,
+ 0x00000007U,
+ 0xFFFFFFFFU,
+ 0xFFFFFF0FU,
+ 0x0FFFFFFFU,
+ 0x03FFFF01U,
+ 0x1F010303U,
+ 0x0F1F1F1FU,
+ 0xFF3F07FFU,
+ 0x0FFF0FFFU,
+ 0x001F0F3FU,
+ 0x03FF03FFU,
+ 0x01FF0FFFU,
+ 0x00000F01U,
+ 0x000003FFU,
+ 0x00030703U,
+ 0x07FF03FFU,
+ 0xFFFF0101U,
+ 0x001F7F7FU,
+ 0xFFFFFFFFU,
+ 0x0000000FU,
+ 0x07FF07FFU,
+ 0x07FF07FFU,
+ 0x07FF07FFU,
+ 0x07FF07FFU,
+ 0x03FF07FFU,
+ 0x0003FF03U,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF070FU,
+ 0x000103FFU,
+ 0x000F03FFU,
+ 0x010F07FFU,
+ 0x000003FFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x0003033FU
+};
+
+u32 g_lpddr4_data_slice_1_rw_mask[] = {
+ 0x07FF7F07U,
+ 0x0703FF0FU,
+ 0x010303FFU,
+ 0x3F3F3F3FU,
+ 0x3F3F3F3FU,
+ 0x01030F3FU,
+ 0x1F1F0301U,
+ 0x1F030F0FU,
+ 0x0101FF03U,
+ 0x00000001U,
+ 0xFFFFFFFFU,
+ 0x00000000U,
+ 0x7F0101FFU,
+ 0x010101FFU,
+ 0x03FF003FU,
+ 0x01FF000FU,
+ 0x01FF0701U,
+ 0x00000003U,
+ 0x00000000U,
+ 0x00000301U,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x070F0107U,
+ 0x0F0F0F0FU,
+ 0x3F030001U,
+ 0x0F3FFF0FU,
+ 0x1F030F3FU,
+ 0x03FFFFFFU,
+ 0x00073FFFU,
+ 0x0F0F07FFU,
+ 0x000FFFFFU,
+ 0x000001FFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x0001FFFFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x00000001U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x7FFFFFFFU,
+ 0x0000003FU,
+ 0x00000000U,
+ 0x00000000U,
+ 0x01FF01FFU,
+ 0x01FF01FFU,
+ 0x01FF01FFU,
+ 0x01FF01FFU,
+ 0x000001FFU,
+ 0x0003FFFFU,
+ 0x01FF01FFU,
+ 0xFF1F07FFU,
+ 0xFF3F03FFU,
+ 0x010101FFU,
+ 0x01010703U,
+ 0x00000101U,
+ 0x07FFFF07U,
+ 0x7F03FFFFU,
+ 0xFF01037FU,
+ 0x07FF07FFU,
+ 0x0103FFFFU,
+ 0x1F1F0F3FU,
+ 0x1F1F1F1FU,
+ 0x1F1F1F1FU,
+ 0x007F1F1FU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x1F0703FFU,
+ 0x00000007U,
+ 0xFFFFFFFFU,
+ 0xFFFFFF0FU,
+ 0x0FFFFFFFU,
+ 0x03FFFF01U,
+ 0x1F010303U,
+ 0x0F1F1F1FU,
+ 0xFF3F07FFU,
+ 0x0FFF0FFFU,
+ 0x001F0F3FU,
+ 0x03FF03FFU,
+ 0x01FF0FFFU,
+ 0x00000F01U,
+ 0x000003FFU,
+ 0x00030703U,
+ 0x07FF03FFU,
+ 0xFFFF0101U,
+ 0x001F7F7FU,
+ 0xFFFFFFFFU,
+ 0x0000000FU,
+ 0x07FF07FFU,
+ 0x07FF07FFU,
+ 0x07FF07FFU,
+ 0x07FF07FFU,
+ 0x03FF07FFU,
+ 0x0003FF03U,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF070FU,
+ 0x000103FFU,
+ 0x000F03FFU,
+ 0x010F07FFU,
+ 0x000003FFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x0003033FU
+};
+
+u32 g_lpddr4_data_slice_2_rw_mask[] = {
+ 0x07FF7F07U,
+ 0x0703FF0FU,
+ 0x010303FFU,
+ 0x3F3F3F3FU,
+ 0x3F3F3F3FU,
+ 0x01030F3FU,
+ 0x1F1F0301U,
+ 0x1F030F0FU,
+ 0x0101FF03U,
+ 0x00000001U,
+ 0xFFFFFFFFU,
+ 0x00000000U,
+ 0x7F0101FFU,
+ 0x010101FFU,
+ 0x03FF003FU,
+ 0x01FF000FU,
+ 0x01FF0701U,
+ 0x00000003U,
+ 0x00000000U,
+ 0x00000301U,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x070F0107U,
+ 0x0F0F0F0FU,
+ 0x3F030001U,
+ 0x0F3FFF0FU,
+ 0x1F030F3FU,
+ 0x03FFFFFFU,
+ 0x00073FFFU,
+ 0x0F0F07FFU,
+ 0x000FFFFFU,
+ 0x000001FFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x0001FFFFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x00000001U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x7FFFFFFFU,
+ 0x0000003FU,
+ 0x00000000U,
+ 0x00000000U,
+ 0x01FF01FFU,
+ 0x01FF01FFU,
+ 0x01FF01FFU,
+ 0x01FF01FFU,
+ 0x000001FFU,
+ 0x0003FFFFU,
+ 0x01FF01FFU,
+ 0xFF1F07FFU,
+ 0xFF3F03FFU,
+ 0x010101FFU,
+ 0x01010703U,
+ 0x00000101U,
+ 0x07FFFF07U,
+ 0x7F03FFFFU,
+ 0xFF01037FU,
+ 0x07FF07FFU,
+ 0x0103FFFFU,
+ 0x1F1F0F3FU,
+ 0x1F1F1F1FU,
+ 0x1F1F1F1FU,
+ 0x007F1F1FU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x1F0703FFU,
+ 0x00000007U,
+ 0xFFFFFFFFU,
+ 0xFFFFFF0FU,
+ 0x0FFFFFFFU,
+ 0x03FFFF01U,
+ 0x1F010303U,
+ 0x0F1F1F1FU,
+ 0xFF3F07FFU,
+ 0x0FFF0FFFU,
+ 0x001F0F3FU,
+ 0x03FF03FFU,
+ 0x01FF0FFFU,
+ 0x00000F01U,
+ 0x000003FFU,
+ 0x00030703U,
+ 0x07FF03FFU,
+ 0xFFFF0101U,
+ 0x001F7F7FU,
+ 0xFFFFFFFFU,
+ 0x0000000FU,
+ 0x07FF07FFU,
+ 0x07FF07FFU,
+ 0x07FF07FFU,
+ 0x07FF07FFU,
+ 0x03FF07FFU,
+ 0x0003FF03U,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF070FU,
+ 0x000103FFU,
+ 0x000F03FFU,
+ 0x010F07FFU,
+ 0x000003FFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x0003033FU
+};
+
+u32 g_lpddr4_data_slice_3_rw_mask[] = {
+ 0x07FF7F07U,
+ 0x0703FF0FU,
+ 0x010303FFU,
+ 0x3F3F3F3FU,
+ 0x3F3F3F3FU,
+ 0x01030F3FU,
+ 0x1F1F0301U,
+ 0x1F030F0FU,
+ 0x0101FF03U,
+ 0x00000001U,
+ 0xFFFFFFFFU,
+ 0x00000000U,
+ 0x7F0101FFU,
+ 0x010101FFU,
+ 0x03FF003FU,
+ 0x01FF000FU,
+ 0x01FF0701U,
+ 0x00000003U,
+ 0x00000000U,
+ 0x00000301U,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x070F0107U,
+ 0x0F0F0F0FU,
+ 0x3F030001U,
+ 0x0F3FFF0FU,
+ 0x1F030F3FU,
+ 0x03FFFFFFU,
+ 0x00073FFFU,
+ 0x0F0F07FFU,
+ 0x000FFFFFU,
+ 0x000001FFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x0001FFFFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x00000001U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x7FFFFFFFU,
+ 0x0000003FU,
+ 0x00000000U,
+ 0x00000000U,
+ 0x01FF01FFU,
+ 0x01FF01FFU,
+ 0x01FF01FFU,
+ 0x01FF01FFU,
+ 0x000001FFU,
+ 0x0003FFFFU,
+ 0x01FF01FFU,
+ 0xFF1F07FFU,
+ 0xFF3F03FFU,
+ 0x010101FFU,
+ 0x01010703U,
+ 0x00000101U,
+ 0x07FFFF07U,
+ 0x7F03FFFFU,
+ 0xFF01037FU,
+ 0x07FF07FFU,
+ 0x0103FFFFU,
+ 0x1F1F0F3FU,
+ 0x1F1F1F1FU,
+ 0x1F1F1F1FU,
+ 0x007F1F1FU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x1F0703FFU,
+ 0x00000007U,
+ 0xFFFFFFFFU,
+ 0xFFFFFF0FU,
+ 0x0FFFFFFFU,
+ 0x03FFFF01U,
+ 0x1F010303U,
+ 0x0F1F1F1FU,
+ 0xFF3F07FFU,
+ 0x0FFF0FFFU,
+ 0x001F0F3FU,
+ 0x03FF03FFU,
+ 0x01FF0FFFU,
+ 0x00000F01U,
+ 0x000003FFU,
+ 0x00030703U,
+ 0x07FF03FFU,
+ 0xFFFF0101U,
+ 0x001F7F7FU,
+ 0xFFFFFFFFU,
+ 0x0000000FU,
+ 0x07FF07FFU,
+ 0x07FF07FFU,
+ 0x07FF07FFU,
+ 0x07FF07FFU,
+ 0x03FF07FFU,
+ 0x0003FF03U,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF070FU,
+ 0x000103FFU,
+ 0x000F03FFU,
+ 0x010F07FFU,
+ 0x000003FFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x0003033FU
+};
+
+u32 g_lpddr4_address_slice_0_rw_mask[] = {
+ 0x000107FFU,
+ 0x00000000U,
+ 0x0F000000U,
+ 0x00000000U,
+ 0x01000707U,
+ 0x011F7F7FU,
+ 0x01000301U,
+ 0x07FFFFFFU,
+ 0x0000003FU,
+ 0x00000000U,
+ 0x00000000U,
+ 0x07FF07FFU,
+ 0x000007FFU,
+ 0x00FFFFFFU,
+ 0x03FFFFFFU,
+ 0x01FF0F03U,
+ 0x07000001U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x000FFFFFU,
+ 0x000FFFFFU,
+ 0x000FFFFFU,
+ 0x000FFFFFU,
+ 0x000FFFFFU,
+ 0x000FFFFFU,
+ 0x000FFFFFU,
+ 0x000FFFFFU,
+ 0x3FFFFFFFU,
+ 0x3F3F03FFU,
+ 0x3F0F3F3FU,
+ 0xFFFFFF03U,
+ 0x01FFFFFFU,
+ 0x3F03FFFFU,
+ 0x0101FFFFU,
+ 0x00003F01U,
+ 0x07FF07FFU,
+ 0x07FF1F07U,
+ 0x1F07FF1FU,
+ 0x001F07FFU,
+ 0x001F07FFU,
+ 0x001F07FFU,
+ 0x000F07FFU,
+ 0xFF3F07FFU,
+ 0x0103FFFFU,
+ 0x0000000FU,
+ 0x03FF010FU,
+ 0x0000FF01U
+};
+
+u32 g_lpddr4_address_slice_1_rw_mask[] = {
+ 0x000107FFU,
+ 0x00000000U,
+ 0x0F000000U,
+ 0x00000000U,
+ 0x01000707U,
+ 0x011F7F7FU,
+ 0x01000301U,
+ 0x07FFFFFFU,
+ 0x0000003FU,
+ 0x00000000U,
+ 0x00000000U,
+ 0x07FF07FFU,
+ 0x000007FFU,
+ 0x00FFFFFFU,
+ 0x03FFFFFFU,
+ 0x01FF0F03U,
+ 0x07000001U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x000FFFFFU,
+ 0x000FFFFFU,
+ 0x000FFFFFU,
+ 0x000FFFFFU,
+ 0x000FFFFFU,
+ 0x000FFFFFU,
+ 0x000FFFFFU,
+ 0x000FFFFFU,
+ 0x3FFFFFFFU,
+ 0x3F3F03FFU,
+ 0x3F0F3F3FU,
+ 0xFFFFFF03U,
+ 0x01FFFFFFU,
+ 0x3F03FFFFU,
+ 0x0101FFFFU,
+ 0x00003F01U,
+ 0x07FF07FFU,
+ 0x07FF1F07U,
+ 0x1F07FF1FU,
+ 0x001F07FFU,
+ 0x001F07FFU,
+ 0x001F07FFU,
+ 0x000F07FFU,
+ 0xFF3F07FFU,
+ 0x0103FFFFU,
+ 0x0000000FU,
+ 0x03FF010FU,
+ 0x0000FF01U
+};
+
+u32 g_lpddr4_address_slice_2_rw_mask[] = {
+ 0x000107FFU,
+ 0x00000000U,
+ 0x0F000000U,
+ 0x00000000U,
+ 0x01000707U,
+ 0x011F7F7FU,
+ 0x01000301U,
+ 0x07FFFFFFU,
+ 0x0000003FU,
+ 0x00000000U,
+ 0x00000000U,
+ 0x07FF07FFU,
+ 0x000007FFU,
+ 0x00FFFFFFU,
+ 0x03FFFFFFU,
+ 0x01FF0F03U,
+ 0x07000001U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x000FFFFFU,
+ 0x000FFFFFU,
+ 0x000FFFFFU,
+ 0x000FFFFFU,
+ 0x000FFFFFU,
+ 0x000FFFFFU,
+ 0x000FFFFFU,
+ 0x000FFFFFU,
+ 0x3FFFFFFFU,
+ 0x3F3F03FFU,
+ 0x3F0F3F3FU,
+ 0xFFFFFF03U,
+ 0x01FFFFFFU,
+ 0x3F03FFFFU,
+ 0x0101FFFFU,
+ 0x00003F01U,
+ 0x07FF07FFU,
+ 0x07FF1F07U,
+ 0x1F07FF1FU,
+ 0x001F07FFU,
+ 0x001F07FFU,
+ 0x001F07FFU,
+ 0x000F07FFU,
+ 0xFF3F07FFU,
+ 0x0103FFFFU,
+ 0x0000000FU,
+ 0x03FF010FU,
+ 0x0000FF01U
+};
+
+u32 g_lpddr4_phy_core_rw_mask[] = {
+ 0x00000003U,
+ 0x1F030101U,
+ 0x1F1F1F1FU,
+ 0x1F1F1F1FU,
+ 0x1F1F1F1FU,
+ 0x001F1F1FU,
+ 0x011F07FFU,
+ 0x07FF0100U,
+ 0x000107FFU,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x0101FF01U,
+ 0x0007FF0FU,
+ 0xFF0F07FFU,
+ 0x01030007U,
+ 0xFFFF0101U,
+ 0xFF3F0103U,
+ 0x010101FFU,
+ 0x0F0F0100U,
+ 0x0F010F0FU,
+ 0x010F0F0FU,
+ 0xFFFF0101U,
+ 0x0001010FU,
+ 0x00000000U,
+ 0x0000FFFFU,
+ 0x00000001U,
+ 0x0F0F0F0FU,
+ 0x0F0F0F0FU,
+ 0x0F0F0F0FU,
+ 0x0F0F0F0FU,
+ 0x0F0F0F0FU,
+ 0x00FF01FFU,
+ 0xFFFF1FFFU,
+ 0x0000FF01U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x0FFF0FFFU,
+ 0x00000000U,
+ 0x00000000U,
+ 0x0FFF0FFFU,
+ 0x0F010101U,
+ 0x03FF01FFU,
+ 0x0101FFFFU,
+ 0x0003FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0003FFFFU,
+ 0x0003FFFFU,
+ 0x0003FFFFU,
+ 0x0003FFFFU,
+ 0x0003FFFFU,
+ 0x0003FFFFU,
+ 0x0003FFFFU,
+ 0x1FFF03FFU,
+ 0x00001FFFU,
+ 0xFFFFFFFFU,
+ 0x000007FFU,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x7F000000U,
+ 0x01FFFFFFU,
+ 0x00000000U,
+ 0x00000000U,
+ 0x0FFFFFFFU,
+ 0x000FFFFFU,
+ 0x01FFFFFFU,
+ 0x3F7FFFFFU,
+ 0x3F3F1F3FU,
+ 0x1F3F3F1FU,
+ 0x001F3F3FU,
+ 0x0000FFFFU,
+ 0x01FF0F03U,
+ 0x00000F7FU,
+ 0x00000000U,
+ 0x003F0101U,
+ 0x01010000U,
+ 0x00000001U,
+ 0xFFFFFFFFU,
+ 0x071F01FFU,
+ 0x03030303U,
+ 0xFFFFFFFFU,
+ 0x03FFFFFFU,
+ 0x00FF073FU,
+ 0x0707FFFFU,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000003U,
+ 0x1F010101U,
+ 0x0000000FU,
+ 0x0003FFFFU,
+ 0x0703FFFFU,
+ 0x00000001U,
+ 0x00011FFFU,
+ 0x0F0F0FFFU,
+ 0x010103FFU,
+ 0x07FF07FFU,
+ 0x07FF07FFU,
+ 0x07FF07FFU,
+ 0x07FF07FFU,
+ 0x07FF07FFU,
+ 0x07FF07FFU,
+ 0x000007FFU,
+ 0x000007FFU,
+ 0x000007FFU,
+ 0x000007FFU,
+ 0x00000007U,
+ 0x3FFFFFFFU,
+ 0x0003FFFFU,
+ 0x7FFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x3FFFFFFFU,
+ 0x0FFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x0007FFFFU,
+ 0x3FFFFFFFU,
+ 0x0FFFFFFFU,
+ 0x3FFFFFFFU,
+ 0x0FFFFFFFU,
+ 0x3FFFFFFFU,
+ 0x0FFFFFFFU,
+ 0x3FFFFFFFU,
+ 0x0FFFFFFFU,
+ 0x3FFFFFFFU,
+ 0x0FFFFFFFU,
+ 0x7FFFFF07U
+};
diff --git a/drivers/ram/k3-ddrss/lpddr4_16bit_ctl_regs_rw_masks.c b/drivers/ram/k3-ddrss/lpddr4_am64_ctl_regs_rw_masks.c
index 09b0e3c5a00..249b56db65f 100644
--- a/drivers/ram/k3-ddrss/lpddr4_16bit_ctl_regs_rw_masks.c
+++ b/drivers/ram/k3-ddrss/lpddr4_am64_ctl_regs_rw_masks.c
@@ -2,12 +2,12 @@
/*
* Cadence DDR Driver
*
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <linux/types.h>
-#include "lpddr4_ctl_regs_rw_masks.h"
+#include <lpddr4_am64_ctl_regs_rw_masks.h>
u32 g_lpddr4_ddr_controller_rw_mask[] = {
0x00000F01U,
diff --git a/drivers/ram/k3-ddrss/lpddr4_16bit.c b/drivers/ram/k3-ddrss/lpddr4_am6x.c
index b749b748973..8ccc1f1aff1 100644
--- a/drivers/ram/k3-ddrss/lpddr4_16bit.c
+++ b/drivers/ram/k3-ddrss/lpddr4_am6x.c
@@ -2,19 +2,18 @@
/*
* Cadence DDR Driver
*
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <errno.h>
-
#include "cps_drv_lpddr4.h"
#include "lpddr4_ctl_regs.h"
#include "lpddr4_if.h"
#include "lpddr4.h"
#include "lpddr4_structs_if.h"
-static u32 ctlintmap[51][3] = {
+static u16 ctlintmap[51][3] = {
{ 0, 0, 7 },
{ 1, 0, 8 },
{ 2, 0, 9 },
@@ -86,6 +85,7 @@ u32 lpddr4_enablepiinitiator(const lpddr4_privatedata *pd)
CPS_REG_WRITE((&(ctlregbase->LPDDR4__PI_NORMAL_LVL_SEQ__REG)), regval);
regval = CPS_FLD_SET(LPDDR4__PI_INIT_LVL_EN__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__PI_INIT_LVL_EN__REG)));
CPS_REG_WRITE((&(ctlregbase->LPDDR4__PI_INIT_LVL_EN__REG)), regval);
+
return result;
}
@@ -345,15 +345,18 @@ u32 lpddr4_checkmmrreaderror(const lpddr4_privatedata *pd, u64 *mmrvalue, u8 *mr
result = (u32)EIO;
} else {
*mrrstatus = (u8)0;
+#ifdef CONFIG_K3_AM64_DDRSS
lowerdata = CPS_REG_READ(&(ctlregbase->LPDDR4__PERIPHERAL_MRR_DATA__REG));
+#else
+ lowerdata = CPS_REG_READ(&(ctlregbase->LPDDR4__PERIPHERAL_MRR_DATA_0__REG));
+ *mmrvalue = CPS_REG_READ(&(ctlregbase->LPDDR4__PERIPHERAL_MRR_DATA_1__REG));
+#endif
*mmrvalue = (u64)((*mmrvalue << WORD_SHIFT) | lowerdata);
result = lpddr4_ackctlinterrupt(pd, LPDDR4_INTR_MR_READ_DONE);
}
return result;
}
-#ifdef REG_WRITE_VERIF
-
u32 lpddr4_getdslicemask(u32 dslicenum, u32 arrayoffset)
{
u32 rwmask = 0U;
@@ -370,7 +373,6 @@ u32 lpddr4_getdslicemask(u32 dslicenum, u32 arrayoffset)
}
return rwmask;
}
-#endif
u32 lpddr4_geteccenable(const lpddr4_privatedata *pd, lpddr4_eccenable *eccparam)
{
diff --git a/drivers/ram/k3-ddrss/lpddr4_am6x.h b/drivers/ram/k3-ddrss/lpddr4_am6x.h
new file mode 100644
index 00000000000..bc707d99056
--- /dev/null
+++ b/drivers/ram/k3-ddrss/lpddr4_am6x.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef LPDDR4_AM6X_H
+#define LPDDR4_AM6X_H
+
+#ifdef CONFIG_K3_AM64_DDRSS
+#include "lpddr4_am64_ctl_regs_rw_masks.h"
+#elif CONFIG_K3_AM62A_DDRSS
+#include "lpddr4_am62a_ctl_regs_rw_masks.h"
+#endif
+
+#ifdef CONFIG_K3_AM64_DDRSS
+#define DSLICE_NUM (2U)
+#define ASLICE_NUM (2U)
+#define DSLICE0_REG_COUNT (126U)
+#define DSLICE1_REG_COUNT (126U)
+#define ASLICE0_REG_COUNT (42U)
+#define ASLICE1_REG_COUNT (42U)
+#define ASLICE2_REG_COUNT (42U)
+#define PHY_CORE_REG_COUNT (126U)
+
+#elif CONFIG_K3_AM62A_DDRSS
+#define DSLICE_NUM (4U)
+#define ASLICE_NUM (3U)
+#define DSLICE0_REG_COUNT (136U)
+#define DSLICE1_REG_COUNT (136U)
+#define DSLICE2_REG_COUNT (136U)
+#define DSLICE3_REG_COUNT (136U)
+#define ASLICE0_REG_COUNT (48U)
+#define ASLICE1_REG_COUNT (48U)
+#define ASLICE2_REG_COUNT (48U)
+#define PHY_CORE_REG_COUNT (132U)
+
+#endif
+
+#define GRP_SHIFT 1
+#define INT_SHIFT 2
+
+#endif /* LPDDR4_AM6X_H */
diff --git a/drivers/ram/k3-ddrss/lpddr4_16bit_sanity.h b/drivers/ram/k3-ddrss/lpddr4_am6x_sanity.h
index fde05cea1f1..18762cbb288 100644
--- a/drivers/ram/k3-ddrss/lpddr4_16bit_sanity.h
+++ b/drivers/ram/k3-ddrss/lpddr4_am6x_sanity.h
@@ -2,19 +2,19 @@
/*
* Cadence DDR Driver
*
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
*/
-#ifndef LPDDR4_16BIT_SANITY_H
-#define LPDDR4_16BIT_SANITY_H
+#ifndef LPDDR4_AM6X_SANITY_H
+#define LPDDR4_AM6X_SANITY_H
#include <errno.h>
#include <linux/types.h>
#include <lpddr4_if.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
+#include <lpddr4_if.h>
+#include <lpddr4_if.h>
+#include <lpddr4_if.h>
static inline u32 lpddr4_intr_sanityfunction1(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr, const bool *irqstatus);
static inline u32 lpddr4_intr_sanityfunction2(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr);
@@ -250,8 +250,4 @@ static inline u32 lpddr4_intr_sanityfunction4(const lpddr4_privatedata *pd, cons
return ret;
}
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LPDDR4_16BIT_SANITY_H */
+#endif /* LPDDR4_AM6X_SANITY_H */
diff --git a/drivers/ram/k3-ddrss/lpddr4_if.h b/drivers/ram/k3-ddrss/lpddr4_if.h
index 7562989d998..1d8bcf7d38b 100644
--- a/drivers/ram/k3-ddrss/lpddr4_if.h
+++ b/drivers/ram/k3-ddrss/lpddr4_if.h
@@ -2,8 +2,8 @@
/*
* Cadence DDR Driver
*
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef LPDDR4_IF_H
@@ -11,9 +11,11 @@
#include <linux/types.h>
#ifdef CONFIG_K3_AM64_DDRSS
-#include <lpddr4_16bit_if.h>
+#include <lpddr4_am64_if.h>
+#elif CONFIG_K3_AM62A_DDRSS
+#include <lpddr4_am62a_if.h>
#else
-#include <lpddr4_32bit_if.h>
+#include <lpddr4_j721e_if.h>
#endif
typedef struct lpddr4_config_s lpddr4_config;
@@ -141,4 +143,6 @@ u32 lpddr4_setrefreshrate(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *
u32 lpddr4_refreshperchipselect(const lpddr4_privatedata *pd, const u32 trefinterval);
+u32 lpddr4_deferredregverify(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regvalues[], u16 regnum[], u16 regcount);
+
#endif /* LPDDR4_IF_H */
diff --git a/drivers/ram/k3-ddrss/lpddr4_32bit.c b/drivers/ram/k3-ddrss/lpddr4_j721e.c
index ab2e44891d9..5db7e5c2287 100644
--- a/drivers/ram/k3-ddrss/lpddr4_32bit.c
+++ b/drivers/ram/k3-ddrss/lpddr4_j721e.c
@@ -2,8 +2,8 @@
/*
* Cadence DDR Driver
*
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <errno.h>
@@ -273,8 +273,6 @@ u32 lpddr4_checkmmrreaderror(const lpddr4_privatedata *pd, u64 *mmrvalue, u8 *mr
return result;
}
-#ifdef REG_WRITE_VERIF
-
u32 lpddr4_getdslicemask(u32 dslicenum, u32 arrayoffset)
{
u32 rwmask = 0U;
@@ -299,4 +297,3 @@ u32 lpddr4_getdslicemask(u32 dslicenum, u32 arrayoffset)
}
return rwmask;
}
-#endif
diff --git a/drivers/ram/k3-ddrss/lpddr4_32bit.h b/drivers/ram/k3-ddrss/lpddr4_j721e.h
index 1f7fe658af8..f115af77857 100644
--- a/drivers/ram/k3-ddrss/lpddr4_32bit.h
+++ b/drivers/ram/k3-ddrss/lpddr4_j721e.h
@@ -2,20 +2,18 @@
/*
* Cadence DDR Driver
*
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
*/
-#ifndef LPDDR4_32BIT_H
-#define LPDDR4_32BIT_H
+#ifndef LPDDR4_J721E_H
+#define LPDDR4_J721E_H
+
+#include "lpddr4_j721e_ctl_regs_rw_masks.h"
#define DSLICE_NUM (4U)
#define ASLICE_NUM (1U)
-#ifdef __cplusplus
-extern "C" {
-#endif
-
#define DSLICE0_REG_COUNT (140U)
#define DSLICE1_REG_COUNT (140U)
#define DSLICE2_REG_COUNT (140U)
@@ -23,8 +21,4 @@ extern "C" {
#define ASLICE0_REG_COUNT (52U)
#define PHY_CORE_REG_COUNT (140U)
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LPDDR4_32BIT_H */
+#endif /* LPDDR4_J721E_H */
diff --git a/drivers/ram/k3-ddrss/lpddr4_32bit_ctl_regs_rw_masks.c b/drivers/ram/k3-ddrss/lpddr4_j721e_ctl_regs_rw_masks.c
index 70f0ef5942a..24394747da2 100644
--- a/drivers/ram/k3-ddrss/lpddr4_32bit_ctl_regs_rw_masks.c
+++ b/drivers/ram/k3-ddrss/lpddr4_j721e_ctl_regs_rw_masks.c
@@ -2,12 +2,12 @@
/*
* Cadence DDR Driver
*
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <linux/types.h>
-#include "lpddr4_ctl_regs_rw_masks.h"
+#include <lpddr4_j721e_ctl_regs_rw_masks.h>
u32 g_lpddr4_ddr_controller_rw_mask[] = {
0x00000F01U,
diff --git a/drivers/ram/k3-ddrss/lpddr4_32bit_sanity.h b/drivers/ram/k3-ddrss/lpddr4_j721e_sanity.h
index 334eecc8aaa..174002f1201 100644
--- a/drivers/ram/k3-ddrss/lpddr4_32bit_sanity.h
+++ b/drivers/ram/k3-ddrss/lpddr4_j721e_sanity.h
@@ -2,19 +2,16 @@
/*
* Cadence DDR Driver
*
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
*/
-#ifndef LPDDR4_32BIT_SANITY_H
-#define LPDDR4_32BIT_SANITY_H
+#ifndef LPDDR4_J721E_SANITY_H
+#define LPDDR4_J721E_SANITY_H
#include <errno.h>
#include <linux/types.h>
#include <lpddr4_if.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
static inline u32 lpddr4_intr_sanityfunction1(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr, const bool *irqstatus);
static inline u32 lpddr4_intr_sanityfunction2(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr);
@@ -216,8 +213,4 @@ static inline u32 lpddr4_intr_sanityfunction4(const lpddr4_privatedata *pd, cons
return ret;
}
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LPDDR4_32BIT_SANITY_H */
+#endif /* LPDDR4_J721E_SANITY_H */
diff --git a/drivers/ram/k3-ddrss/lpddr4_obj_if.c b/drivers/ram/k3-ddrss/lpddr4_obj_if.c
index 370242f5bd2..63b259c33d4 100644
--- a/drivers/ram/k3-ddrss/lpddr4_obj_if.c
+++ b/drivers/ram/k3-ddrss/lpddr4_obj_if.c
@@ -2,8 +2,8 @@
/*
* Cadence DDR Driver
*
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "lpddr4_obj_if.h"
@@ -45,6 +45,7 @@ lpddr4_obj *lpddr4_getinstance(void)
.getrefreshrate = lpddr4_getrefreshrate,
.setrefreshrate = lpddr4_setrefreshrate,
.refreshperchipselect = lpddr4_refreshperchipselect,
+ .deferredregverify = lpddr4_deferredregverify,
};
return &driver;
diff --git a/drivers/ram/k3-ddrss/lpddr4_obj_if.h b/drivers/ram/k3-ddrss/lpddr4_obj_if.h
index d538e61b747..b1bbb5cc1a7 100644
--- a/drivers/ram/k3-ddrss/lpddr4_obj_if.h
+++ b/drivers/ram/k3-ddrss/lpddr4_obj_if.h
@@ -2,8 +2,8 @@
/*
* Cadence DDR Driver
*
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef lpddr4_obj_if_h
@@ -79,6 +79,8 @@ typedef struct lpddr4_obj_s {
u32 (*setrefreshrate)(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref, const u32 *tras_max);
u32 (*refreshperchipselect)(const lpddr4_privatedata *pd, const u32 trefinterval);
+
+ u32 (*deferredregverify)(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regvalues[], u16 regnum[], u16 regcount);
} lpddr4_obj;
extern lpddr4_obj *lpddr4_getinstance(void);
diff --git a/drivers/ram/k3-ddrss/lpddr4_private.h b/drivers/ram/k3-ddrss/lpddr4_private.h
deleted file mode 100644
index 3d5017ea476..00000000000
--- a/drivers/ram/k3-ddrss/lpddr4_private.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/**********************************************************************
- * Copyright (C) 2012-2018 Cadence Design Systems, Inc.
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
- **********************************************************************
- * Cadence Core Driver for LPDDR4.
- **********************************************************************
- */
-
-#ifndef LPDDR4_PRIV_H
-#define LPDDR4_PRIV_H
-
-#define PRODUCT_ID (0x1046U)
-#define VERSION_0 (0x54d5da40U)
-#define VERSION_1 (0xc1865a1U)
-
-#define LPDDR4_BIT_MASK (0x1U)
-#define BYTE_MASK (0xffU)
-#define NIBBLE_MASK (0xfU)
-
-#define WORD_SHIFT (32U)
-#define WORD_MASK (0xffffffffU)
-#define SLICE_WIDTH (0x100)
-/* Number of Data slices */
-#define DSLICE_NUM (4U)
-/*Number of Address Slices */
-#define ASLICE_NUM (1U)
-
-/* Number of accessible registers in each slice */
-#define DSLICE0_REG_COUNT (140U)
-#define DSLICE1_REG_COUNT (140U)
-#define DSLICE2_REG_COUNT (140U)
-#define DSLICE3_REG_COUNT (140U)
-#define ASLICE0_REG_COUNT (52U)
-#define PHY_CORE_REG_COUNT (140U)
-
-#define CTL_OFFSET 0
-#define PI_OFFSET (((uint32_t)1) << 11)
-#define PHY_OFFSET (((uint32_t)1) << 12)
-
-/* BIT[17] on INT_MASK_1 register. */
-#define CTL_INT_MASK_ALL ((uint32_t)LPDDR4_LOR_BITS - WORD_SHIFT)
-
-/* Init Error information bits */
-#define PLL_READY (0x3U)
-#define IO_CALIB_DONE ((uint32_t)0x1U << 23U)
-#define IO_CALIB_FIELD ((uint32_t)NIBBLE_MASK << 28U)
-#define IO_CALIB_STATE ((uint32_t)0xBU << 28U)
-#define RX_CAL_DONE ((uint32_t)LPDDR4_BIT_MASK << 4U)
-#define CA_TRAIN_RL (((uint32_t)LPDDR4_BIT_MASK << 5U) | \
- ((uint32_t)LPDDR4_BIT_MASK << 4U))
-#define WR_LVL_STATE (((uint32_t)NIBBLE_MASK) << 13U)
-#define GATE_LVL_ERROR_FIELDS (((uint32_t)LPDDR4_BIT_MASK << 7U) | \
- ((uint32_t)LPDDR4_BIT_MASK << 6U))
-#define READ_LVL_ERROR_FIELDS ((((uint32_t)NIBBLE_MASK) << 28U) | \
- (((uint32_t)BYTE_MASK) << 16U))
-#define DQ_LVL_STATUS (((uint32_t)LPDDR4_BIT_MASK << 26U) | \
- (((uint32_t)BYTE_MASK) << 18U))
-
-#endif /* LPDDR4_PRIV_H */
diff --git a/drivers/ram/k3-ddrss/lpddr4_sanity.h b/drivers/ram/k3-ddrss/lpddr4_sanity.h
index 750e00d3f5c..d5e61ff5ea8 100644
--- a/drivers/ram/k3-ddrss/lpddr4_sanity.h
+++ b/drivers/ram/k3-ddrss/lpddr4_sanity.h
@@ -2,8 +2,8 @@
/*
* Cadence DDR Driver
*
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef LPDDR4_SANITY_H
@@ -12,9 +12,6 @@
#include <errno.h>
#include <linux/types.h>
#include "lpddr4_if.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
static inline u32 lpddr4_configsf(const lpddr4_config *obj);
static inline u32 lpddr4_privatedatasf(const lpddr4_privatedata *obj);
@@ -37,7 +34,7 @@ static inline u32 lpddr4_sanityfunction23(const lpddr4_privatedata *pd, const lp
static inline u32 lpddr4_sanityfunction24(const lpddr4_privatedata *pd, const lpddr4_reducmode *mode);
static inline u32 lpddr4_sanityfunction25(const lpddr4_privatedata *pd, const bool *on_off);
static inline u32 lpddr4_sanityfunction27(const lpddr4_privatedata *pd, const lpddr4_dbimode *mode);
-static inline u32 lpddr4_sanityfunction28(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref, const u32 *tras_max);
+static inline u32 lpddr4_sanityfunction28(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref_val, const u32 *tras_max_val);
static inline u32 lpddr4_sanityfunction29(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref, const u32 *tras_max);
#define lpddr4_probesf lpddr4_sanityfunction1
@@ -70,6 +67,7 @@ static inline u32 lpddr4_sanityfunction29(const lpddr4_privatedata *pd, const lp
#define lpddr4_getrefreshratesf lpddr4_sanityfunction28
#define lpddr4_setrefreshratesf lpddr4_sanityfunction29
#define lpddr4_refreshperchipselectsf lpddr4_sanityfunction3
+#define lpddr4_deferredregverifysf lpddr4_sanityfunction5
static inline u32 lpddr4_configsf(const lpddr4_config *obj)
{
@@ -390,15 +388,15 @@ static inline u32 lpddr4_sanityfunction27(const lpddr4_privatedata *pd, const lp
return ret;
}
-static inline u32 lpddr4_sanityfunction28(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref, const u32 *tras_max)
+static inline u32 lpddr4_sanityfunction28(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref_val, const u32 *tras_max_val)
{
u32 ret = 0;
if (fspnum == NULL) {
ret = EINVAL;
- } else if (tref == NULL) {
+ } else if (tref_val == NULL) {
ret = EINVAL;
- } else if (tras_max == NULL) {
+ } else if (tras_max_val == NULL) {
ret = EINVAL;
} else if (lpddr4_privatedatasf(pd) == EINVAL) {
ret = EINVAL;
@@ -438,8 +436,4 @@ static inline u32 lpddr4_sanityfunction29(const lpddr4_privatedata *pd, const lp
return ret;
}
-#ifdef __cplusplus
-}
-#endif
-
#endif /* LPDDR4_SANITY_H */
diff --git a/drivers/ram/k3-ddrss/lpddr4_structs_if.h b/drivers/ram/k3-ddrss/lpddr4_structs_if.h
index f2f1210c3c4..b09e708de42 100644
--- a/drivers/ram/k3-ddrss/lpddr4_structs_if.h
+++ b/drivers/ram/k3-ddrss/lpddr4_structs_if.h
@@ -2,8 +2,8 @@
/*
* Cadence DDR Driver
*
- * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef LPDDR4_STRUCTS_IF_H
diff --git a/drivers/ram/mpc83xx_sdram.c b/drivers/ram/mpc83xx_sdram.c
index a53ff93a6b0..11676d4fae7 100644
--- a/drivers/ram/mpc83xx_sdram.c
+++ b/drivers/ram/mpc83xx_sdram.c
@@ -118,12 +118,7 @@ int dram_init(void)
phys_size_t get_effective_memsize(void)
{
- if (!IS_ENABLED(CONFIG_VERY_BIG_RAM))
- return gd->ram_size;
-
- /* Limit stack to what we can reasonable map */
- return ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ?
- CONFIG_MAX_MEM_MAPPED : gd->ram_size);
+ return gd->ram_size;
}
/**
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index b6987225698..35b6ed4d7c7 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -260,4 +260,13 @@ config RTC_ZYNQMP
Say "yes" here to support the on chip real time clock
present on Xilinx ZynqMP SoC.
+config RTC_HT1380
+ bool "Enable Holtek HT1380/HT1381 RTC driver"
+ depends on DM_RTC && DM_GPIO
+ help
+ Say "yes" here to get support for Holtek HT1380/HT1381
+ Serial Timekeeper IC which provides seconds, minutes, hours,
+ day of the week, date, month and year information. It is to be
+ connected via 3 GPIO pins which work as reset, clock, and data.
+
endmenu
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index 2089086551d..acfd130bbc9 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -21,6 +21,7 @@ obj-$(CONFIG_RTC_DS3231) += ds3231.o
obj-$(CONFIG_RTC_DS3232) += ds3232.o
obj-$(CONFIG_RTC_EMULATION) += emul_rtc.o
obj-$(CONFIG_RTC_FTRTC010) += ftrtc010.o
+obj-$(CONFIG_RTC_HT1380) += ht1380.o
obj-$(CONFIG_SANDBOX) += i2c_rtc_emul.o
obj-$(CONFIG_RTC_IMXDI) += imxdi.o
obj-$(CONFIG_RTC_ISL1208) += isl1208.o
diff --git a/drivers/rtc/ftrtc010.c b/drivers/rtc/ftrtc010.c
index 67c2b6e320a..e384922f473 100644
--- a/drivers/rtc/ftrtc010.c
+++ b/drivers/rtc/ftrtc010.c
@@ -80,9 +80,9 @@ int rtc_get(struct rtc_time *tmp)
debug("%s(): record register: %x\n",
__func__, readl(&rtc->record));
-#ifdef CONFIG_FTRTC010_PCLK
+#ifdef CFG_FTRTC010_PCLK
now = (ftrtc010_time() + readl(&rtc->record)) / RTC_DIV_COUNT;
-#else /* CONFIG_FTRTC010_EXTCLK */
+#else /* CFG_FTRTC010_EXTCLK */
now = ftrtc010_time() + readl(&rtc->record);
#endif
diff --git a/drivers/rtc/ht1380.c b/drivers/rtc/ht1380.c
new file mode 100644
index 00000000000..85fcee3e71e
--- /dev/null
+++ b/drivers/rtc/ht1380.c
@@ -0,0 +1,329 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Holtek HT1380/HT1381 Serial Timekeeper Chip
+ *
+ * Communication with the chip is vendor-specific.
+ * It is done via 3 GPIO pins: reset, clock, and data.
+ * Describe in .dts this way:
+ *
+ * rtc {
+ * compatible = "holtek,ht1380";
+ * rst-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
+ * clk-gpios = <&gpio 20 GPIO_ACTIVE_HIGH>;
+ * dat-gpios = <&gpio 21 GPIO_ACTIVE_HIGH>;
+ * };
+ *
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <rtc.h>
+#include <bcd.h>
+#include <asm/gpio.h>
+#include <linux/delay.h>
+
+struct ht1380_priv {
+ struct gpio_desc rst_desc;
+ struct gpio_desc clk_desc;
+ struct gpio_desc dat_desc;
+};
+
+enum registers {
+ SEC,
+ MIN,
+ HOUR,
+ MDAY,
+ MONTH,
+ WDAY,
+ YEAR,
+ WP,
+ N_REGS
+};
+
+enum hour_mode {
+ AMPM_MODE = 0x80, /* RTC is in AM/PM mode */
+ PM_NOW = 0x20, /* set if PM, clear if AM */
+};
+
+static const int BURST = 0xbe;
+static const int READ = 1;
+
+static void ht1380_half_period_delay(void)
+{
+ /*
+ * Delay for half a period. 1 us complies with the 500 KHz maximum
+ * input serial clock limit given by the datasheet.
+ */
+ udelay(1);
+}
+
+static int ht1380_send_byte(struct ht1380_priv *priv, int byte)
+{
+ int ret;
+
+ for (int bit = 0; bit < 8; bit++) {
+ ret = dm_gpio_set_value(&priv->dat_desc, byte >> bit & 1);
+ if (ret)
+ break;
+ ht1380_half_period_delay();
+
+ ret = dm_gpio_set_value(&priv->clk_desc, 1);
+ if (ret)
+ break;
+ ht1380_half_period_delay();
+
+ ret = dm_gpio_set_value(&priv->clk_desc, 0);
+ if (ret)
+ break;
+ }
+
+ return ret;
+}
+
+/*
+ * Leave reset state. The transfer operation can then be started.
+ */
+static int ht1380_reset_off(struct ht1380_priv *priv)
+{
+ const unsigned int T_CC = 4; /* us, Reset to Clock Setup */
+ int ret;
+
+ /*
+ * Leave RESET state.
+ * Make sure we make the minimal delay required by the datasheet.
+ */
+ ret = dm_gpio_set_value(&priv->rst_desc, 0);
+ udelay(T_CC);
+
+ return ret;
+}
+
+/*
+ * Enter reset state. Completes the transfer operation.
+ */
+static int ht1380_reset_on(struct ht1380_priv *priv)
+{
+ const unsigned int T_CWH = 4; /* us, Reset Inactive Time */
+ int ret;
+
+ /*
+ * Enter RESET state.
+ * Make sure we make the minimal delay required by the datasheet.
+ */
+ ret = dm_gpio_set_value(&priv->rst_desc, 1);
+ udelay(T_CWH);
+
+ return ret;
+}
+
+static int ht1380_rtc_get(struct udevice *dev, struct rtc_time *tm)
+{
+ struct ht1380_priv *priv = dev_get_priv(dev);
+ int ret, i, bit, reg[N_REGS];
+
+ ret = dm_gpio_set_value(&priv->clk_desc, 0);
+ if (ret)
+ return ret;
+
+ ret = dm_gpio_set_dir_flags(&priv->dat_desc, GPIOD_IS_OUT);
+ if (ret)
+ return ret;
+
+ ret = ht1380_reset_off(priv);
+ if (ret)
+ goto exit;
+
+ ret = ht1380_send_byte(priv, BURST + READ);
+ if (ret)
+ goto exit;
+
+ ret = dm_gpio_set_dir_flags(&priv->dat_desc, GPIOD_IS_IN);
+ if (ret)
+ goto exit;
+
+ for (i = 0; i < N_REGS; i++) {
+ reg[i] = 0;
+
+ for (bit = 0; bit < 8; bit++) {
+ ht1380_half_period_delay();
+
+ ret = dm_gpio_set_value(&priv->clk_desc, 1);
+ if (ret)
+ goto exit;
+ ht1380_half_period_delay();
+
+ reg[i] |= dm_gpio_get_value(&priv->dat_desc) << bit;
+ ret = dm_gpio_set_value(&priv->clk_desc, 0);
+ if (ret)
+ goto exit;
+ }
+ }
+
+ ret = -EINVAL;
+
+ /* Correctness check: some bits are always zero */
+ if (reg[MIN] & 0x80 || reg[HOUR] & 0x40 || reg[MDAY] & 0xc0 ||
+ reg[MONTH] & 0xe0 || reg[WDAY] & 0xf8 || reg[WP] & 0x7f)
+ goto exit;
+
+ /* Correctness check: some registers are always non-zero */
+ if (!reg[MDAY] || !reg[MONTH] || !reg[WDAY])
+ goto exit;
+
+ tm->tm_sec = bcd2bin(reg[SEC]);
+ tm->tm_min = bcd2bin(reg[MIN]);
+ if (reg[HOUR] & AMPM_MODE) {
+ /* AM-PM Mode, range is 01-12 */
+ tm->tm_hour = bcd2bin(reg[HOUR] & 0x1f) % 12;
+ if (reg[HOUR] & PM_NOW) {
+ /* it is PM (otherwise AM) */
+ tm->tm_hour += 12;
+ }
+ } else {
+ /* 24-hour Mode, range is 0-23 */
+ tm->tm_hour = bcd2bin(reg[HOUR]);
+ }
+ tm->tm_mday = bcd2bin(reg[MDAY]);
+ tm->tm_mon = bcd2bin(reg[MONTH]);
+ tm->tm_year = 2000 + bcd2bin(reg[YEAR]);
+ tm->tm_wday = bcd2bin(reg[WDAY]) - 1;
+ tm->tm_yday = 0;
+ tm->tm_isdst = 0;
+
+ ret = 0;
+
+exit:
+ ht1380_reset_on(priv);
+
+ return ret;
+}
+
+static int ht1380_write_protection_off(struct ht1380_priv *priv)
+{
+ int ret;
+ const int PROTECT = 0x8e;
+
+ ret = ht1380_reset_off(priv);
+ if (ret)
+ return ret;
+
+ ret = ht1380_send_byte(priv, PROTECT);
+ if (ret)
+ return ret;
+ ret = ht1380_send_byte(priv, 0); /* WP bit is 0 */
+ if (ret)
+ return ret;
+
+ return ht1380_reset_on(priv);
+}
+
+static int ht1380_rtc_set(struct udevice *dev, const struct rtc_time *tm)
+{
+ struct ht1380_priv *priv = dev_get_priv(dev);
+ int ret, i, reg[N_REGS];
+
+ ret = dm_gpio_set_value(&priv->clk_desc, 0);
+ if (ret)
+ return ret;
+
+ ret = dm_gpio_set_dir_flags(&priv->dat_desc, GPIOD_IS_OUT);
+ if (ret)
+ goto exit;
+
+ ret = ht1380_write_protection_off(priv);
+ if (ret)
+ goto exit;
+
+ reg[SEC] = bin2bcd(tm->tm_sec);
+ reg[MIN] = bin2bcd(tm->tm_min);
+ reg[HOUR] = bin2bcd(tm->tm_hour);
+ reg[MDAY] = bin2bcd(tm->tm_mday);
+ reg[MONTH] = bin2bcd(tm->tm_mon);
+ reg[WDAY] = bin2bcd(tm->tm_wday) + 1;
+ reg[YEAR] = bin2bcd(tm->tm_year - 2000);
+ reg[WP] = 0x80; /* WP bit is 1 */
+
+ ret = ht1380_reset_off(priv);
+ if (ret)
+ goto exit;
+
+ ret = ht1380_send_byte(priv, BURST);
+ for (i = 0; i < N_REGS && ret; i++)
+ ret = ht1380_send_byte(priv, reg[i]);
+
+exit:
+ ht1380_reset_on(priv);
+
+ return ret;
+}
+
+static int ht1380_probe(struct udevice *dev)
+{
+ int ret;
+ struct ht1380_priv *priv;
+
+ priv = dev_get_priv(dev);
+ if (!priv)
+ return -EINVAL;
+
+ ret = gpio_request_by_name(dev, "rst-gpios", 0,
+ &priv->rst_desc, GPIOD_IS_OUT);
+ if (ret)
+ goto fail_rst;
+
+ ret = gpio_request_by_name(dev, "clk-gpios", 0,
+ &priv->clk_desc, GPIOD_IS_OUT);
+ if (ret)
+ goto fail_clk;
+
+ ret = gpio_request_by_name(dev, "dat-gpios", 0,
+ &priv->dat_desc, 0);
+ if (ret)
+ goto fail_dat;
+
+ ret = ht1380_reset_on(priv);
+ if (ret)
+ goto fail;
+
+ return 0;
+
+fail:
+ dm_gpio_free(dev, &priv->dat_desc);
+fail_dat:
+ dm_gpio_free(dev, &priv->clk_desc);
+fail_clk:
+ dm_gpio_free(dev, &priv->rst_desc);
+fail_rst:
+ return ret;
+}
+
+static int ht1380_remove(struct udevice *dev)
+{
+ struct ht1380_priv *priv = dev_get_priv(dev);
+
+ dm_gpio_free(dev, &priv->rst_desc);
+ dm_gpio_free(dev, &priv->clk_desc);
+ dm_gpio_free(dev, &priv->dat_desc);
+
+ return 0;
+}
+
+static const struct rtc_ops ht1380_rtc_ops = {
+ .get = ht1380_rtc_get,
+ .set = ht1380_rtc_set,
+};
+
+static const struct udevice_id ht1380_rtc_ids[] = {
+ { .compatible = "holtek,ht1380" },
+ { }
+};
+
+U_BOOT_DRIVER(rtc_ht1380) = {
+ .name = "rtc-ht1380",
+ .id = UCLASS_RTC,
+ .probe = ht1380_probe,
+ .remove = ht1380_remove,
+ .of_match = ht1380_rtc_ids,
+ .ops = &ht1380_rtc_ops,
+ .priv_auto = sizeof(struct ht1380_priv),
+};
diff --git a/drivers/rtc/mc146818.c b/drivers/rtc/mc146818.c
index 122691b9784..03ce081d576 100644
--- a/drivers/rtc/mc146818.c
+++ b/drivers/rtc/mc146818.c
@@ -13,7 +13,7 @@
#include <dm.h>
#include <rtc.h>
-#if defined(CONFIG_X86) || defined(CONFIG_MALTA)
+#if defined(CONFIG_X86) || defined(CONFIG_TARGET_MALTA)
#include <asm/io.h>
#define in8(p) inb(p)
#define out8(p, v) outb(v, p)
diff --git a/drivers/scsi/scsi.c b/drivers/scsi/scsi.c
index 3e769b0843f..a020a7da23a 100644
--- a/drivers/scsi/scsi.c
+++ b/drivers/scsi/scsi.c
@@ -18,8 +18,8 @@
#include <dm/uclass-internal.h>
#if !defined(CONFIG_DM_SCSI)
-# ifdef CONFIG_SCSI_DEV_LIST
-# define SCSI_DEV_LIST CONFIG_SCSI_DEV_LIST
+# ifdef CFG_SCSI_DEV_LIST
+# define SCSI_DEV_LIST CFG_SCSI_DEV_LIST
# else
# ifdef CONFIG_SATA_ULI5288
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 14b0febd1a5..bb5083201b3 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -827,6 +827,15 @@ config S5P_SERIAL
help
Select this to enable Samsung S5P UART support.
+config S5P4418_PL011_SERIAL
+ bool "Extended PL011 driver for S5P4418"
+ depends on DM_SERIAL && PL01X_SERIAL && ARCH_NEXELL
+ default y
+ help
+ Select this to enable support of the PL011 UARTs in the S5P4418 SOC.
+ With this driver the UART-clocks are set to the appropriate rate
+ (if not 'skip-init').
+
config SANDBOX_SERIAL
bool "Sandbox UART support"
depends on SANDBOX
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 33fa5682211..01fef3f323b 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -3,30 +3,15 @@
# (C) Copyright 2006-2009
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-ifdef CONFIG_SPL_BUILD
-
-ifeq ($(CONFIG_$(SPL_TPL_)BUILD)$(CONFIG_$(SPL_TPL_)DM_SERIAL),yy)
-obj-y += serial-uclass.o
-else
-obj-y += serial.o
-endif
-
-else
-
-ifdef CONFIG_DM_SERIAL
+ifeq ($(CONFIG_$(SPL_TPL_)DM_SERIAL),y)
obj-y += serial-uclass.o
else
obj-y += serial.o
endif
-endif
-
-ifdef CONFIG_DM_SERIAL
obj-$(CONFIG_PL01X_SERIAL) += serial_pl01x.o
-else
obj-$(CONFIG_PL011_SERIAL) += serial_pl01x.o
obj-$(CONFIG_$(SPL_)SYS_NS16550_SERIAL) += serial_ns16550.o
-endif
obj-$(CONFIG_ALTERA_UART) += altera_uart.o
obj-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o
@@ -74,6 +59,7 @@ obj-$(CONFIG_MT7620_SERIAL) += serial_mt7620.o
obj-$(CONFIG_HTIF_CONSOLE) += serial_htif.o
obj-$(CONFIG_SIFIVE_SERIAL) += serial_sifive.o
obj-$(CONFIG_XEN_SERIAL) += serial_xen.o
+obj-$(CONFIG_S5P4418_PL011_SERIAL) += serial_s5p4418_pl011.o
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_USB_TTY) += usbtty.o
diff --git a/drivers/serial/atmel_usart.c b/drivers/serial/atmel_usart.c
index 90ccdf6b294..9853f49c94f 100644
--- a/drivers/serial/atmel_usart.c
+++ b/drivers/serial/atmel_usart.c
@@ -18,7 +18,7 @@
#include <linux/delay.h>
#include <asm/io.h>
-#ifdef CONFIG_DM_SERIAL
+#if CONFIG_IS_ENABLED(DM_SERIAL)
#include <asm/arch/atmel_serial.h>
#endif
#include <asm/arch/clk.h>
@@ -28,7 +28,7 @@
DECLARE_GLOBAL_DATA_PTR;
-#ifndef CONFIG_DM_SERIAL
+#if !CONFIG_IS_ENABLED(DM_SERIAL)
static void atmel_serial_setbrg_internal(atmel_usart3_t *usart, int id,
int baudrate)
{
@@ -72,13 +72,13 @@ static void atmel_serial_activate(atmel_usart3_t *usart)
static void atmel_serial_setbrg(void)
{
- atmel_serial_setbrg_internal((atmel_usart3_t *)CONFIG_USART_BASE,
- CONFIG_USART_ID, gd->baudrate);
+ atmel_serial_setbrg_internal((atmel_usart3_t *)CFG_USART_BASE,
+ CFG_USART_ID, gd->baudrate);
}
static int atmel_serial_init(void)
{
- atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;
+ atmel_usart3_t *usart = (atmel_usart3_t *)CFG_USART_BASE;
atmel_serial_init_internal(usart);
serial_setbrg();
@@ -89,7 +89,7 @@ static int atmel_serial_init(void)
static void atmel_serial_putc(char c)
{
- atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;
+ atmel_usart3_t *usart = (atmel_usart3_t *)CFG_USART_BASE;
if (c == '\n')
serial_putc('\r');
@@ -100,7 +100,7 @@ static void atmel_serial_putc(char c)
static int atmel_serial_getc(void)
{
- atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;
+ atmel_usart3_t *usart = (atmel_usart3_t *)CFG_USART_BASE;
while (!(readl(&usart->csr) & USART3_BIT(RXRDY)))
schedule();
@@ -109,7 +109,7 @@ static int atmel_serial_getc(void)
static int atmel_serial_tstc(void)
{
- atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;
+ atmel_usart3_t *usart = (atmel_usart3_t *)CFG_USART_BASE;
return (readl(&usart->csr) & USART3_BIT(RXRDY)) != 0;
}
@@ -133,9 +133,7 @@ __weak struct serial_device *default_serial_console(void)
{
return &atmel_serial_drv;
}
-#endif
-
-#ifdef CONFIG_DM_SERIAL
+#else
enum serial_clk_type {
CLK_TYPE_NORMAL = 0,
CLK_TYPE_DBGU,
diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c
index c02106747a0..77d3f373721 100644
--- a/drivers/serial/serial-uclass.c
+++ b/drivers/serial/serial-uclass.c
@@ -407,7 +407,7 @@ void serial_stdio_init(void)
{
}
-#if defined(CONFIG_DM_STDIO)
+#if CONFIG_IS_ENABLED(DM_STDIO)
#if CONFIG_IS_ENABLED(SERIAL_PRESENT)
static void serial_stub_putc(struct stdio_dev *sdev, const char ch)
@@ -505,7 +505,7 @@ U_BOOT_ENV_CALLBACK(baudrate, on_baudrate);
static int serial_post_probe(struct udevice *dev)
{
struct dm_serial_ops *ops = serial_get_ops(dev);
-#ifdef CONFIG_DM_STDIO
+#if CONFIG_IS_ENABLED(DM_STDIO)
struct serial_dev_priv *upriv = dev_get_uclass_priv(dev);
struct stdio_dev sdev;
#endif
@@ -526,7 +526,7 @@ static int serial_post_probe(struct udevice *dev)
ops->getconfig += gd->reloc_off;
if (ops->setconfig)
ops->setconfig += gd->reloc_off;
-#if CFG_POST & CONFIG_SYS_POST_UART
+#if CFG_POST & CFG_SYS_POST_UART
if (ops->loop)
ops->loop += gd->reloc_off;
#endif
@@ -540,7 +540,7 @@ static int serial_post_probe(struct udevice *dev)
return ret;
}
-#ifdef CONFIG_DM_STDIO
+#if CONFIG_IS_ENABLED(DM_STDIO)
if (!(gd->flags & GD_FLG_RELOC))
return 0;
memset(&sdev, '\0', sizeof(sdev));
diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c
index 369a8e38e3e..9a380d7c5e7 100644
--- a/drivers/serial/serial.c
+++ b/drivers/serial/serial.c
@@ -458,7 +458,7 @@ void default_serial_puts(const char *s)
dev->putc(*s++);
}
-#if CFG_POST & CONFIG_SYS_POST_UART
+#if CFG_POST & CFG_SYS_POST_UART
static const int bauds[] = CFG_SYS_BAUDRATE_TABLE;
/**
diff --git a/drivers/serial/serial_arc.c b/drivers/serial/serial_arc.c
index b2d95bdbe18..c2fc8a901e2 100644
--- a/drivers/serial/serial_arc.c
+++ b/drivers/serial/serial_arc.c
@@ -53,8 +53,8 @@ static int arc_serial_putc(struct udevice *dev, const char c)
struct arc_serial_plat *plat = dev_get_plat(dev);
struct arc_serial_regs *const regs = plat->reg;
- while (!(readb(&regs->status) & UART_TXEMPTY))
- ;
+ if (!(readb(&regs->status) & UART_TXEMPTY))
+ return -EAGAIN;
writeb(c, &regs->data);
@@ -83,8 +83,8 @@ static int arc_serial_getc(struct udevice *dev)
struct arc_serial_plat *plat = dev_get_plat(dev);
struct arc_serial_regs *const regs = plat->reg;
- while (!arc_serial_tstc(regs))
- ;
+ if (!arc_serial_tstc(regs))
+ return -EAGAIN;
/* Check for overflow errors */
if (readb(&regs->status) & UART_OVERFLOW_ERR)
diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c
index ff576da516d..51e66abdbc1 100644
--- a/drivers/serial/serial_lpuart.c
+++ b/drivers/serial/serial_lpuart.c
@@ -168,23 +168,24 @@ static void _lpuart_serial_setbrg(struct udevice *dev,
static int _lpuart_serial_getc(struct lpuart_serial_plat *plat)
{
struct lpuart_fsl *base = plat->reg;
- while (!(__raw_readb(&base->us1) & (US1_RDRF | US1_OR)))
- schedule();
+ if (!(__raw_readb(&base->us1) & (US1_RDRF | US1_OR)))
+ return -EAGAIN;
barrier();
return __raw_readb(&base->ud);
}
-static void _lpuart_serial_putc(struct lpuart_serial_plat *plat,
+static int _lpuart_serial_putc(struct lpuart_serial_plat *plat,
const char c)
{
struct lpuart_fsl *base = plat->reg;
- while (!(__raw_readb(&base->us1) & US1_TDRE))
- schedule();
+ if (!(__raw_readb(&base->us1) & US1_TDRE))
+ return -EAGAIN;
__raw_writeb(c, &base->ud);
+ return 0;
}
/* Test whether a character is in the RX buffer */
@@ -328,10 +329,9 @@ static int _lpuart32_serial_getc(struct lpuart_serial_plat *plat)
u32 stat, val;
lpuart_read32(plat->flags, &base->stat, &stat);
- while ((stat & STAT_RDRF) == 0) {
+ if ((stat & STAT_RDRF) == 0) {
lpuart_write32(plat->flags, &base->stat, STAT_FLAGS);
- schedule();
- lpuart_read32(plat->flags, &base->stat, &stat);
+ return -EAGAIN;
}
lpuart_read32(plat->flags, &base->data, &val);
@@ -343,25 +343,18 @@ static int _lpuart32_serial_getc(struct lpuart_serial_plat *plat)
return val & 0x3ff;
}
-static void _lpuart32_serial_putc(struct lpuart_serial_plat *plat,
+static int _lpuart32_serial_putc(struct lpuart_serial_plat *plat,
const char c)
{
struct lpuart_fsl_reg32 *base = plat->reg;
u32 stat;
- if (c == '\n')
- serial_putc('\r');
-
- while (true) {
- lpuart_read32(plat->flags, &base->stat, &stat);
-
- if ((stat & STAT_TDRE))
- break;
-
- schedule();
- }
+ lpuart_read32(plat->flags, &base->stat, &stat);
+ if (!(stat & STAT_TDRE))
+ return -EAGAIN;
lpuart_write32(plat->flags, &base->data, c);
+ return 0;
}
/* Test whether a character is in the RX buffer */
@@ -456,11 +449,9 @@ static int lpuart_serial_putc(struct udevice *dev, const char c)
struct lpuart_serial_plat *plat = dev_get_plat(dev);
if (is_lpuart32(dev))
- _lpuart32_serial_putc(plat, c);
- else
- _lpuart_serial_putc(plat, c);
+ return _lpuart32_serial_putc(plat, c);
- return 0;
+ return _lpuart_serial_putc(plat, c);
}
static int lpuart_serial_pending(struct udevice *dev, bool input)
diff --git a/drivers/serial/serial_mpc8xx.c b/drivers/serial/serial_mpc8xx.c
index aeae6ae6cd2..b8d6a81b650 100644
--- a/drivers/serial/serial_mpc8xx.c
+++ b/drivers/serial/serial_mpc8xx.c
@@ -176,19 +176,15 @@ static int serial_mpc8xx_putc(struct udevice *dev, const char c)
cpm8xx_t __iomem *cpmp = &(im->im_cpm);
struct serialbuffer __iomem *rtx;
- if (c == '\n')
- serial_mpc8xx_putc(dev, '\r');
-
rtx = (struct serialbuffer __iomem *)&cpmp->cp_dpmem[CPM_SERIAL_BASE];
- /* Wait for last character to go. */
+ if (in_be16(&rtx->txbd.cbd_sc) & BD_SC_READY)
+ return -EAGAIN;
+
out_8(&rtx->txbuf, c);
out_be16(&rtx->txbd.cbd_datlen, 1);
setbits_be16(&rtx->txbd.cbd_sc, BD_SC_READY);
- while (in_be16(&rtx->txbd.cbd_sc) & BD_SC_READY)
- schedule();
-
return 0;
}
@@ -202,9 +198,8 @@ static int serial_mpc8xx_getc(struct udevice *dev)
rtx = (struct serialbuffer __iomem *)&cpmp->cp_dpmem[CPM_SERIAL_BASE];
- /* Wait for character to show up. */
- while (in_be16(&rtx->rxbd.cbd_sc) & BD_SC_EMPTY)
- schedule();
+ if (in_be16(&rtx->rxbd.cbd_sc) & BD_SC_EMPTY)
+ return -EAGAIN;
/* the characters are read one by one,
* use the rxindex to know the next char to deliver
diff --git a/drivers/serial/serial_mtk.c b/drivers/serial/serial_mtk.c
index 6fb4cb65c29..ded7346a13f 100644
--- a/drivers/serial/serial_mtk.c
+++ b/drivers/serial/serial_mtk.c
@@ -173,8 +173,7 @@ static int _mtk_serial_pending(struct mtk_serial_priv *priv, bool input)
return (readl(&priv->regs->lsr) & UART_LSR_THRE) ? 0 : 1;
}
-#if defined(CONFIG_DM_SERIAL) && \
- (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_DM))
+#if CONFIG_IS_ENABLED(DM_SERIAL)
static int mtk_serial_setbrg(struct udevice *dev, int baudrate)
{
struct mtk_serial_priv *priv = dev_get_priv(dev);
diff --git a/drivers/serial/serial_mvebu_a3700.c b/drivers/serial/serial_mvebu_a3700.c
index 0fcd7e88ace..b2017c64556 100644
--- a/drivers/serial/serial_mvebu_a3700.c
+++ b/drivers/serial/serial_mvebu_a3700.c
@@ -40,8 +40,8 @@ static int mvebu_serial_putc(struct udevice *dev, const char ch)
struct mvebu_plat *plat = dev_get_plat(dev);
void __iomem *base = plat->base;
- while (readl(base + UART_STATUS_REG) & UART_STATUS_TXFIFO_FULL)
- ;
+ if (readl(base + UART_STATUS_REG) & UART_STATUS_TXFIFO_FULL)
+ return -EAGAIN;
writel(ch, base + UART_TX_REG);
@@ -53,8 +53,8 @@ static int mvebu_serial_getc(struct udevice *dev)
struct mvebu_plat *plat = dev_get_plat(dev);
void __iomem *base = plat->base;
- while (!(readl(base + UART_STATUS_REG) & UART_STATUS_RX_RDY))
- ;
+ if (!(readl(base + UART_STATUS_REG) & UART_STATUS_RX_RDY))
+ return -EAGAIN;
return readl(base + UART_RX_REG) & 0xff;
}
diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c
index 82c0d84628d..8bcbbf2bbfc 100644
--- a/drivers/serial/serial_mxc.c
+++ b/drivers/serial/serial_mxc.c
@@ -194,11 +194,11 @@ static void _mxc_serial_setbrg(struct mxc_uart *base, unsigned long clk,
#if !CONFIG_IS_ENABLED(DM_SERIAL)
-#ifndef CONFIG_MXC_UART_BASE
-#error "define CONFIG_MXC_UART_BASE to use the MXC UART driver"
+#ifndef CFG_MXC_UART_BASE
+#error "define CFG_MXC_UART_BASE to use the MXC UART driver"
#endif
-#define mxc_base ((struct mxc_uart *)CONFIG_MXC_UART_BASE)
+#define mxc_base ((struct mxc_uart *)CFG_MXC_UART_BASE)
static void mxc_serial_setbrg(void)
{
diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c
index d3c3d3e2d18..f5468353e10 100644
--- a/drivers/serial/serial_pl01x.c
+++ b/drivers/serial/serial_pl01x.c
@@ -27,9 +27,8 @@
DECLARE_GLOBAL_DATA_PTR;
-#ifndef CONFIG_DM_SERIAL
-
-static volatile unsigned char *const port[] = CONFIG_PL01x_PORTS;
+#if !CONFIG_IS_ENABLED(DM_SERIAL)
+static volatile unsigned char *const port[] = CFG_PL01x_PORTS;
static enum pl01x_type pl01x_type __section(".data");
static struct pl01x_regs *base_regs __section(".data");
#define NUM_PORTS (sizeof(port)/sizeof(port[0]))
@@ -186,14 +185,14 @@ static int pl01x_generic_setbrg(struct pl01x_regs *regs, enum pl01x_type type,
return 0;
}
-#ifndef CONFIG_DM_SERIAL
+#if !CONFIG_IS_ENABLED(DM_SERIAL)
static void pl01x_serial_init_baud(int baudrate)
{
int clock = 0;
#if defined(CONFIG_PL011_SERIAL)
pl01x_type = TYPE_PL011;
- clock = CONFIG_PL011_CLOCK;
+ clock = CFG_PL011_CLOCK;
#endif
base_regs = (struct pl01x_regs *)port[CONFIG_CONS_INDEX];
@@ -273,11 +272,7 @@ __weak struct serial_device *default_serial_console(void)
{
return &pl01x_serial_drv;
}
-
-#endif /* nCONFIG_DM_SERIAL */
-
-#ifdef CONFIG_DM_SERIAL
-
+#else
int pl01x_serial_setbrg(struct udevice *dev, int baudrate)
{
struct pl01x_serial_plat *plat = dev_get_plat(dev);
@@ -343,8 +338,8 @@ static const struct udevice_id pl01x_serial_id[] ={
{}
};
-#ifndef CONFIG_PL011_CLOCK
-#define CONFIG_PL011_CLOCK 0
+#ifndef CFG_PL011_CLOCK
+#define CFG_PL011_CLOCK 0
#endif
int pl01x_serial_of_to_plat(struct udevice *dev)
@@ -359,7 +354,7 @@ int pl01x_serial_of_to_plat(struct udevice *dev)
return -EINVAL;
plat->base = addr;
- plat->clock = dev_read_u32_default(dev, "clock", CONFIG_PL011_CLOCK);
+ plat->clock = dev_read_u32_default(dev, "clock", CFG_PL011_CLOCK);
ret = clk_get_by_index(dev, 0, &clk);
if (!ret) {
ret = clk_enable(&clk);
diff --git a/drivers/serial/serial_pl01x_internal.h b/drivers/serial/serial_pl01x_internal.h
index dfd95a0b77c..71c52bb5312 100644
--- a/drivers/serial/serial_pl01x_internal.h
+++ b/drivers/serial/serial_pl01x_internal.h
@@ -38,7 +38,7 @@ struct pl01x_regs {
u32 pl011_cr; /* 0x30 Control register */
};
-#ifdef CONFIG_DM_SERIAL
+#if CONFIG_IS_ENABLED(DM_SERIAL)
int pl01x_serial_of_to_plat(struct udevice *dev);
int pl01x_serial_probe(struct udevice *dev);
diff --git a/drivers/serial/serial_s5p4418_pl011.c b/drivers/serial/serial_s5p4418_pl011.c
new file mode 100644
index 00000000000..e4492e662e9
--- /dev/null
+++ b/drivers/serial/serial_s5p4418_pl011.c
@@ -0,0 +1,94 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 Stefan Bosch <stefan_b@posteo.net>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/reset.h>
+#include <linux/delay.h>
+
+#include <dm/platform_data/serial_pl01x.h>
+#include <serial.h>
+#include "serial_pl01x_internal.h"
+
+int s5p4418_pl011_serial_probe(struct udevice *dev)
+{
+ struct pl01x_serial_plat *plat = dev_get_plat(dev);
+ struct clk *nx_clk;
+ ulong rate_act;
+ char uart_clk_name[10];
+ int uart_num = -1;
+ int rst_id, ret;
+
+ if (!plat->skip_init) {
+ uart_num = dev->seq_;
+ rst_id = RESET_ID_UART0 + uart_num;
+
+ if (uart_num < 0 || rst_id > RESET_ID_UART5) {
+ /* invalid UART-number */
+ debug("%s: sequence/uart number %d is invalid!\n", __func__, uart_num);
+ return -ENODEV;
+ }
+
+ sprintf(uart_clk_name, "nx-uart.%d", uart_num);
+ nx_clk = clk_get(uart_clk_name);
+ if (!nx_clk) {
+ debug("%s: clk_get('%s') failed!\n", __func__, uart_clk_name);
+ return -ENODEV;
+ }
+
+ /* wait to make sure all pending characters have been sent */
+ mdelay(100);
+ }
+
+ /*
+ * Note: Unless !plat->skip_init, the UART is disabled here, so printf()
+ * or debug() must not be used until pl01x_serial_setbrg() has been called
+ * (enables the UART). Otherwise u-boot is hanging!
+ */
+ ret = pl01x_serial_probe(dev);
+ if (ret)
+ return ret;
+
+ if (!plat->skip_init) {
+ /* do reset UART */
+ nx_rstcon_setrst(rst_id, RSTCON_ASSERT);
+ udelay(10);
+ nx_rstcon_setrst(rst_id, RSTCON_NEGATE);
+ udelay(10);
+ clk_disable(nx_clk);
+
+ rate_act = clk_set_rate(nx_clk, plat->clock);
+ clk_enable(nx_clk);
+
+ plat->clock = rate_act;
+ }
+
+ return 0;
+}
+
+static const struct dm_serial_ops s5p4418_pl011_serial_ops = {
+ .putc = pl01x_serial_putc,
+ .pending = pl01x_serial_pending,
+ .getc = pl01x_serial_getc,
+ .setbrg = pl01x_serial_setbrg,
+};
+
+static const struct udevice_id s5p4418_pl011_serial_id[] = {
+ {.compatible = "nexell,s5p4418-pl011", .data = TYPE_PL011},
+ {}
+};
+
+U_BOOT_DRIVER(s5p4418_pl011_uart) = {
+ .name = "s5p4418_pl011",
+ .id = UCLASS_SERIAL,
+ .of_match = of_match_ptr(s5p4418_pl011_serial_id),
+ .of_to_plat = of_match_ptr(pl01x_serial_of_to_plat),
+ .plat_auto = sizeof(struct pl01x_serial_plat),
+ .probe = s5p4418_pl011_serial_probe,
+ .ops = &s5p4418_pl011_serial_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+ .priv_auto = sizeof(struct pl01x_priv),
+};
diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c
index e6c23cedff1..4671217b59a 100644
--- a/drivers/serial/serial_sh.c
+++ b/drivers/serial/serial_sh.c
@@ -274,7 +274,7 @@ U_BOOT_DRIVER(serial_sh) = {
# error "Default SCIF doesn't set....."
#endif
-#if defined(CONFIG_SCIF_A)
+#if defined(CFG_SCIF_A)
#define SCIF_BASE_PORT PORT_SCIFA
#elif defined(CONFIG_SCI)
#define SCIF_BASE_PORT PORT_SCI
diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h
index 11deaa95116..e6ab6f1b9b7 100644
--- a/drivers/serial/serial_sh.h
+++ b/drivers/serial/serial_sh.h
@@ -92,7 +92,7 @@ struct uart_port {
# define SCIF_ORER 0x0001 /* overrun error bit */
#elif defined(CONFIG_RCAR_GEN2) || defined(CONFIG_RCAR_GEN3) || \
defined(CONFIG_R7S72100)
-# if defined(CONFIG_SCIF_A)
+# if defined(CFG_SCIF_A)
# define SCIF_ORER 0x0200
# else
# define SCIF_ORER 0x0001
@@ -164,7 +164,7 @@ struct uart_port {
# define SCIF2_TXROOM_MAX 16
#elif defined(CONFIG_RCAR_GEN2)
# define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
-# if defined(CONFIG_SCIF_A)
+# if defined(CFG_SCIF_A)
# define SCIF_RFDC_MASK 0x007f
# else
# define SCIF_RFDC_MASK 0x001f
@@ -380,7 +380,7 @@ SCIF_FNS(SCFDR, 0, 0, 0x1C, 16)
SCIF_FNS(SCSPTR, 0, 0, 0x20, 16)
SCIF_FNS(DL, 0, 0, 0x30, 16)
SCIF_FNS(CKS, 0, 0, 0x34, 16)
-#if defined(CONFIG_SCIF_A)
+#if defined(CFG_SCIF_A)
SCIF_FNS(SCLSR, 0, 0, 0x14, 16)
#else
SCIF_FNS(SCLSR, 0, 0, 0x24, 16)
@@ -491,7 +491,7 @@ static inline int scbrr_calc(struct uart_port *port, int bps, int clk)
#define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk)
#elif defined(CONFIG_RCAR_GEN2)
#define DL_VALUE(bps, clk) (clk / bps / 16) /* External Clock */
- #if defined(CONFIG_SCIF_A)
+ #if defined(CFG_SCIF_A)
#define SCBRR_VALUE(bps, clk) (clk / bps / 16 - 1) /* Internal Clock */
#else
#define SCBRR_VALUE(bps, clk) (clk / bps / 32 - 1) /* Internal Clock */
diff --git a/drivers/serial/usbtty.c b/drivers/serial/usbtty.c
index 4f4eb02de08..07a59ec9607 100644
--- a/drivers/serial/usbtty.c
+++ b/drivers/serial/usbtty.c
@@ -120,20 +120,6 @@ static struct usb_device_descriptor device_descriptor = {
.bNumConfigurations = NUM_CONFIGS
};
-
-#if defined(CONFIG_USBD_HS)
-static struct usb_qualifier_descriptor qualifier_descriptor = {
- .bLength = sizeof(struct usb_qualifier_descriptor),
- .bDescriptorType = USB_DT_QUAL,
- .bcdUSB = cpu_to_le16(USB_BCD_VERSION),
- .bDeviceClass = COMMUNICATIONS_DEVICE_CLASS,
- .bDeviceSubClass = 0x00,
- .bDeviceProtocol = 0x00,
- .bMaxPacketSize0 = EP0_MAX_PACKET_SIZE,
- .bNumConfigurations = NUM_CONFIGS
-};
-#endif
-
/*
* Static CDC ACM specific descriptors
*/
@@ -639,9 +625,6 @@ static void usbtty_init_instances (void)
memset (device_instance, 0, sizeof (struct usb_device_instance));
device_instance->device_state = STATE_INIT;
device_instance->device_descriptor = &device_descriptor;
-#if defined(CONFIG_USBD_HS)
- device_instance->qualifier_descriptor = &qualifier_descriptor;
-#endif
device_instance->event = usbtty_event_handler;
device_instance->cdc_recv_setup = usbtty_cdc_setup;
device_instance->bus = bus_instance;
@@ -755,10 +738,6 @@ static void usbtty_init_terminal_type(short type)
device_descriptor.idProduct =
cpu_to_le16(CONFIG_USBD_PRODUCTID_CDCACM);
-#if defined(CONFIG_USBD_HS)
- qualifier_descriptor.bDeviceClass =
- COMMUNICATIONS_DEVICE_CLASS;
-#endif
/* Assign endpoint indices */
tx_endpoint = ACM_TX_ENDPOINT;
rx_endpoint = ACM_RX_ENDPOINT;
@@ -787,9 +766,6 @@ static void usbtty_init_terminal_type(short type)
device_descriptor.bDeviceClass = 0xFF;
device_descriptor.idProduct =
cpu_to_le16(CONFIG_USBD_PRODUCTID_GSERIAL);
-#if defined(CONFIG_USBD_HS)
- qualifier_descriptor.bDeviceClass = 0xFF;
-#endif
/* Assign endpoint indices */
tx_endpoint = GSERIAL_TX_ENDPOINT;
rx_endpoint = GSERIAL_RX_ENDPOINT;
@@ -937,9 +913,6 @@ static int usbtty_configured (void)
static void usbtty_event_handler (struct usb_device_instance *device,
usb_device_event_t event, int data)
{
-#if defined(CONFIG_USBD_HS)
- int i;
-#endif
switch (event) {
case DEVICE_RESET:
case DEVICE_BUS_INACTIVE:
@@ -950,29 +923,6 @@ static void usbtty_event_handler (struct usb_device_instance *device,
break;
case DEVICE_ADDRESS_ASSIGNED:
-#if defined(CONFIG_USBD_HS)
- /*
- * is_usbd_high_speed routine needs to be defined by
- * specific gadget driver
- * It returns true if device enumerates at High speed
- * Retuns false otherwise
- */
- for (i = 0; i < NUM_ENDPOINTS; i++) {
- if (((ep_descriptor_ptrs[i]->bmAttributes &
- USB_ENDPOINT_XFERTYPE_MASK) ==
- USB_ENDPOINT_XFER_BULK)
- && is_usbd_high_speed()) {
-
- ep_descriptor_ptrs[i]->wMaxPacketSize =
- CONFIG_USBD_SERIAL_BULK_HS_PKTSIZE;
- }
-
- endpoint_instance[i + 1].tx_packetSize =
- ep_descriptor_ptrs[i]->wMaxPacketSize;
- endpoint_instance[i + 1].rcv_packetSize =
- ep_descriptor_ptrs[i]->wMaxPacketSize;
- }
-#endif
usbtty_init_endpoints ();
default:
diff --git a/drivers/serial/usbtty.h b/drivers/serial/usbtty.h
index e27aa368c9a..ac4d22044d3 100644
--- a/drivers/serial/usbtty.h
+++ b/drivers/serial/usbtty.h
@@ -51,10 +51,6 @@
#define CONFIG_USBD_SERIAL_INT_PKTSIZE UDC_INT_PACKET_SIZE
#define CONFIG_USBD_SERIAL_BULK_PKTSIZE UDC_BULK_PACKET_SIZE
-#if defined(CONFIG_USBD_HS)
-#define CONFIG_USBD_SERIAL_BULK_HS_PKTSIZE UDC_BULK_HS_PACKET_SIZE
-#endif
-
#define USBTTY_DEVICE_CLASS COMMUNICATIONS_DEVICE_CLASS
#define USBTTY_BCD_DEVICE 0x00
diff --git a/drivers/soc/soc_ti_k3.c b/drivers/soc/soc_ti_k3.c
index b1e7c4ae5f6..8af0ac70519 100644
--- a/drivers/soc/soc_ti_k3.c
+++ b/drivers/soc/soc_ti_k3.c
@@ -16,6 +16,7 @@
#define AM64X 0xbb38
#define J721S2 0xbb75
#define AM62X 0xbb7e
+#define AM62AX 0xbb8d
#define JTAG_ID_VARIANT_SHIFT 28
#define JTAG_ID_VARIANT_MASK (0xf << 28)
@@ -53,6 +54,9 @@ static const char *get_family_string(u32 idreg)
case AM62X:
family = "AM62X";
break;
+ case AM62AX:
+ family = "AM62AX";
+ break;
default:
family = "Unknown Silicon";
};
diff --git a/drivers/sound/sandbox.c b/drivers/sound/sandbox.c
index 4a2c87a84c6..c6cbd81fdbc 100644
--- a/drivers/sound/sandbox.c
+++ b/drivers/sound/sandbox.c
@@ -29,6 +29,7 @@ struct sandbox_i2s_priv {
struct sandbox_sound_priv {
int setup_called; /* Incremented when setup() method is called */
bool active; /* TX data is being sent */
+ int count; /* Use to count the provided audio data */
int sum; /* Use to sum the provided audio data */
bool allow_beep; /* true to allow the start_beep() interface */
int frequency_hz; /* Beep frequency if active, else 0 */
@@ -68,6 +69,13 @@ int sandbox_get_sound_active(struct udevice *dev)
return priv->active;
}
+int sandbox_get_sound_count(struct udevice *dev)
+{
+ struct sandbox_sound_priv *priv = dev_get_priv(dev);
+
+ return priv->count;
+}
+
int sandbox_get_sound_sum(struct udevice *dev)
{
struct sandbox_sound_priv *priv = dev_get_priv(dev);
@@ -168,6 +176,7 @@ static int sandbox_sound_play(struct udevice *dev, void *data, uint data_size)
for (i = 0; i < data_size; i++)
priv->sum += ((uint8_t *)data)[i];
+ priv->count += data_size;
return i2s_tx_data(uc_priv->i2s, data, data_size);
}
diff --git a/drivers/sound/sound.c b/drivers/sound/sound.c
index 041dfdccfeb..c0fc50c99da 100644
--- a/drivers/sound/sound.c
+++ b/drivers/sound/sound.c
@@ -15,7 +15,10 @@ void sound_create_square_wave(uint sample_rate, unsigned short *data, int size,
const int period = freq ? sample_rate / freq : 0;
const int half = period / 2;
- assert(freq);
+ if (!half) {
+ memset(data, 0, size);
+ return;
+ }
/* Make sure we don't overflow our buffer */
if (size % 2)
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index c6900f449d5..64ceed12ce4 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -429,6 +429,16 @@ config SANDBOX_SPI
};
};
+config SANDBOX_SPI_MAX_BUS
+ int
+ depends on SANDBOX
+ default 1
+
+config SANDBOX_SPI_MAX_CS
+ int
+ depends on SANDBOX
+ default 10
+
config SPI_ASPEED_SMC
bool "ASPEED SPI flash controller driver"
depends on DM_SPI && SPI_MEM
diff --git a/drivers/spi/cf_spi.c b/drivers/spi/cf_spi.c
index ea23357090f..1a841b5dcef 100644
--- a/drivers/spi/cf_spi.c
+++ b/drivers/spi/cf_spi.c
@@ -32,11 +32,11 @@ struct coldfire_spi_priv {
DECLARE_GLOBAL_DATA_PTR;
-#ifndef CONFIG_SPI_IDLE_VAL
+#ifndef SPI_IDLE_VAL
#if defined(CONFIG_SPI_MMC)
-#define CONFIG_SPI_IDLE_VAL 0xFFFF
+#define SPI_IDLE_VAL 0xFFFF
#else
-#define CONFIG_SPI_IDLE_VAL 0x0
+#define SPI_IDLE_VAL 0x0
#endif
#endif
@@ -184,7 +184,7 @@ static int coldfire_spi_xfer(struct udevice *dev, unsigned int bitlen,
}
if (din) {
- cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL);
+ cfspi_tx(cfspi, ctrl, SPI_IDLE_VAL);
if (cfspi->charbit == 16)
*spi_rd16++ = cfspi_rx(cfspi);
else
@@ -208,7 +208,7 @@ static int coldfire_spi_xfer(struct udevice *dev, unsigned int bitlen,
}
if (din) {
- cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL);
+ cfspi_tx(cfspi, ctrl, SPI_IDLE_VAL);
if (cfspi->charbit == 16)
*spi_rd16 = cfspi_rx(cfspi);
else
@@ -216,7 +216,7 @@ static int coldfire_spi_xfer(struct udevice *dev, unsigned int bitlen,
}
} else {
/* dummy read */
- cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL);
+ cfspi_tx(cfspi, ctrl, SPI_IDLE_VAL);
cfspi_rx(cfspi);
}
diff --git a/drivers/spi/sandbox_spi.c b/drivers/spi/sandbox_spi.c
index 0564d8b55e7..f844597d04c 100644
--- a/drivers/spi/sandbox_spi.c
+++ b/drivers/spi/sandbox_spi.c
@@ -24,10 +24,6 @@
#include <dm/acpi.h>
#include <dm/device-internal.h>
-#ifndef CONFIG_SPI_IDLE_VAL
-# define CONFIG_SPI_IDLE_VAL 0xFF
-#endif
-
/**
* struct sandbox_spi_priv - Sandbox SPI private data
*
diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig
index 3afb45d5ccb..8efd4614573 100644
--- a/drivers/usb/Kconfig
+++ b/drivers/usb/Kconfig
@@ -93,7 +93,6 @@ comment "USB peripherals"
config USB_STORAGE
bool "USB Mass Storage support"
- depends on !(BLK && !DM_USB)
---help---
Say Y here if you want to connect USB mass storage devices to your
board's USB port.
diff --git a/drivers/usb/eth/asix.c b/drivers/usb/eth/asix.c
index 674f78e214d..26dd312b7d0 100644
--- a/drivers/usb/eth/asix.c
+++ b/drivers/usb/eth/asix.c
@@ -101,16 +101,9 @@
/* driver private */
struct asix_private {
int flags;
-#ifdef CONFIG_DM_ETH
struct ueth_data ueth;
-#endif
};
-#ifndef CONFIG_DM_ETH
-/* local vars */
-static int curr_eth_dev; /* index for name of next device detected */
-#endif
-
/*
* Asix infrastructure commands
*/
@@ -494,253 +487,6 @@ static int asix_send_common(struct ueth_data *dev, void *packet, int length)
return err;
}
-#ifndef CONFIG_DM_ETH
-/*
- * Asix callbacks
- */
-static int asix_init(struct eth_device *eth, struct bd_info *bd)
-{
- struct ueth_data *dev = (struct ueth_data *)eth->priv;
-
- return asix_init_common(dev, eth->enetaddr);
-}
-
-static int asix_send(struct eth_device *eth, void *packet, int length)
-{
- struct ueth_data *dev = (struct ueth_data *)eth->priv;
-
- return asix_send_common(dev, packet, length);
-}
-
-static int asix_recv(struct eth_device *eth)
-{
- struct ueth_data *dev = (struct ueth_data *)eth->priv;
- ALLOC_CACHE_ALIGN_BUFFER(unsigned char, recv_buf, AX_RX_URB_SIZE);
- unsigned char *buf_ptr;
- int err;
- int actual_len;
- u32 packet_len;
-
- debug("** %s()\n", __func__);
-
- err = usb_bulk_msg(dev->pusb_dev,
- usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in),
- (void *)recv_buf,
- AX_RX_URB_SIZE,
- &actual_len,
- USB_BULK_RECV_TIMEOUT);
- debug("Rx: len = %u, actual = %u, err = %d\n", AX_RX_URB_SIZE,
- actual_len, err);
- if (err != 0) {
- debug("Rx: failed to receive\n");
- return -1;
- }
- if (actual_len > AX_RX_URB_SIZE) {
- debug("Rx: received too many bytes %d\n", actual_len);
- return -1;
- }
-
- buf_ptr = recv_buf;
- while (actual_len > 0) {
- /*
- * 1st 4 bytes contain the length of the actual data as two
- * complementary 16-bit words. Extract the length of the data.
- */
- if (actual_len < sizeof(packet_len)) {
- debug("Rx: incomplete packet length\n");
- return -1;
- }
- memcpy(&packet_len, buf_ptr, sizeof(packet_len));
- le32_to_cpus(&packet_len);
- if (((~packet_len >> 16) & 0x7ff) != (packet_len & 0x7ff)) {
- debug("Rx: malformed packet length: %#x (%#x:%#x)\n",
- packet_len, (~packet_len >> 16) & 0x7ff,
- packet_len & 0x7ff);
- return -1;
- }
- packet_len = packet_len & 0x7ff;
- if (packet_len > actual_len - sizeof(packet_len)) {
- debug("Rx: too large packet: %d\n", packet_len);
- return -1;
- }
-
- /* Notify net stack */
- net_process_received_packet(buf_ptr + sizeof(packet_len),
- packet_len);
-
- /* Adjust for next iteration. Packets are padded to 16-bits */
- if (packet_len & 1)
- packet_len++;
- actual_len -= sizeof(packet_len) + packet_len;
- buf_ptr += sizeof(packet_len) + packet_len;
- }
-
- return err;
-}
-
-static void asix_halt(struct eth_device *eth)
-{
- debug("** %s()\n", __func__);
-}
-
-static int asix_write_hwaddr(struct eth_device *eth)
-{
- struct ueth_data *dev = (struct ueth_data *)eth->priv;
-
- return asix_write_hwaddr_common(dev, eth->enetaddr);
-}
-
-/*
- * Asix probing functions
- */
-void asix_eth_before_probe(void)
-{
- curr_eth_dev = 0;
-}
-
-struct asix_dongle {
- unsigned short vendor;
- unsigned short product;
- int flags;
-};
-
-static const struct asix_dongle asix_dongles[] = {
- { 0x05ac, 0x1402, FLAG_TYPE_AX88772 }, /* Apple USB Ethernet Adapter */
- { 0x07d1, 0x3c05, FLAG_TYPE_AX88772 }, /* D-Link DUB-E100 H/W Ver B1 */
- { 0x2001, 0x1a02, FLAG_TYPE_AX88772 }, /* D-Link DUB-E100 H/W Ver C1 */
- /* Cables-to-Go USB Ethernet Adapter */
- { 0x0b95, 0x772a, FLAG_TYPE_AX88772 },
- { 0x0b95, 0x7720, FLAG_TYPE_AX88772 }, /* Trendnet TU2-ET100 V3.0R */
- { 0x0b95, 0x1720, FLAG_TYPE_AX88172 }, /* SMC */
- { 0x0db0, 0xa877, FLAG_TYPE_AX88772 }, /* MSI - ASIX 88772a */
- { 0x13b1, 0x0018, FLAG_TYPE_AX88172 }, /* Linksys 200M v2.1 */
- { 0x1557, 0x7720, FLAG_TYPE_AX88772 }, /* 0Q0 cable ethernet */
- /* DLink DUB-E100 H/W Ver B1 Alternate */
- { 0x2001, 0x3c05, FLAG_TYPE_AX88772 },
- /* ASIX 88772B */
- { 0x0b95, 0x772b, FLAG_TYPE_AX88772B | FLAG_EEPROM_MAC },
- { 0x0b95, 0x7e2b, FLAG_TYPE_AX88772B },
- { 0x0000, 0x0000, FLAG_NONE } /* END - Do not remove */
-};
-
-/* Probe to see if a new device is actually an asix device */
-int asix_eth_probe(struct usb_device *dev, unsigned int ifnum,
- struct ueth_data *ss)
-{
- struct usb_interface *iface;
- struct usb_interface_descriptor *iface_desc;
- int ep_in_found = 0, ep_out_found = 0;
- int i;
-
- /* let's examine the device now */
- iface = &dev->config.if_desc[ifnum];
- iface_desc = &dev->config.if_desc[ifnum].desc;
-
- for (i = 0; asix_dongles[i].vendor != 0; i++) {
- if (dev->descriptor.idVendor == asix_dongles[i].vendor &&
- dev->descriptor.idProduct == asix_dongles[i].product)
- /* Found a supported dongle */
- break;
- }
-
- if (asix_dongles[i].vendor == 0)
- return 0;
-
- memset(ss, 0, sizeof(struct ueth_data));
-
- /* At this point, we know we've got a live one */
- debug("\n\nUSB Ethernet device detected: %#04x:%#04x\n",
- dev->descriptor.idVendor, dev->descriptor.idProduct);
-
- /* Initialize the ueth_data structure with some useful info */
- ss->ifnum = ifnum;
- ss->pusb_dev = dev;
- ss->subclass = iface_desc->bInterfaceSubClass;
- ss->protocol = iface_desc->bInterfaceProtocol;
-
- /* alloc driver private */
- ss->dev_priv = calloc(1, sizeof(struct asix_private));
- if (!ss->dev_priv)
- return 0;
-
- ((struct asix_private *)ss->dev_priv)->flags = asix_dongles[i].flags;
-
- /*
- * We are expecting a minimum of 3 endpoints - in, out (bulk), and
- * int. We will ignore any others.
- */
- for (i = 0; i < iface_desc->bNumEndpoints; i++) {
- /* is it an BULK endpoint? */
- if ((iface->ep_desc[i].bmAttributes &
- USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK) {
- u8 ep_addr = iface->ep_desc[i].bEndpointAddress;
- if (ep_addr & USB_DIR_IN) {
- if (!ep_in_found) {
- ss->ep_in = ep_addr &
- USB_ENDPOINT_NUMBER_MASK;
- ep_in_found = 1;
- }
- } else {
- if (!ep_out_found) {
- ss->ep_out = ep_addr &
- USB_ENDPOINT_NUMBER_MASK;
- ep_out_found = 1;
- }
- }
- }
-
- /* is it an interrupt endpoint? */
- if ((iface->ep_desc[i].bmAttributes &
- USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) {
- ss->ep_int = iface->ep_desc[i].bEndpointAddress &
- USB_ENDPOINT_NUMBER_MASK;
- ss->irqinterval = iface->ep_desc[i].bInterval;
- }
- }
- debug("Endpoints In %d Out %d Int %d\n",
- ss->ep_in, ss->ep_out, ss->ep_int);
-
- /* Do some basic sanity checks, and bail if we find a problem */
- if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) ||
- !ss->ep_in || !ss->ep_out || !ss->ep_int) {
- debug("Problems with device\n");
- return 0;
- }
- dev->privptr = (void *)ss;
- return 1;
-}
-
-int asix_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
- struct eth_device *eth)
-{
- struct asix_private *priv = (struct asix_private *)ss->dev_priv;
-
- if (!eth) {
- debug("%s: missing parameter.\n", __func__);
- return 0;
- }
- sprintf(eth->name, "%s%d", ASIX_BASE_NAME, curr_eth_dev++);
- eth->init = asix_init;
- eth->send = asix_send;
- eth->recv = asix_recv;
- eth->halt = asix_halt;
- if (!(priv->flags & FLAG_TYPE_AX88172))
- eth->write_hwaddr = asix_write_hwaddr;
- eth->priv = ss;
-
- if (asix_basic_reset(ss))
- return 0;
-
- /* Get the MAC address */
- if (asix_read_mac_common(ss, priv, eth->enetaddr))
- return 0;
- debug("MAC %pM\n", eth->enetaddr);
-
- return 1;
-}
-#endif
-
-#ifdef CONFIG_DM_ETH
static int asix_eth_start(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_plat(dev);
@@ -909,4 +655,3 @@ static const struct usb_device_id asix_eth_id_table[] = {
};
U_BOOT_USB_DEVICE(asix_eth, asix_eth_id_table);
-#endif
diff --git a/drivers/usb/eth/asix88179.c b/drivers/usb/eth/asix88179.c
index 4742a95af93..2e737e60668 100644
--- a/drivers/usb/eth/asix88179.c
+++ b/drivers/usb/eth/asix88179.c
@@ -199,18 +199,12 @@ static const struct {
{7, 0xcc, 0x4c, 0x04, 8},
};
-#ifndef CONFIG_DM_ETH
-static int curr_eth_dev; /* index for name of next device detected */
-#endif
-
/* driver private */
struct asix_private {
-#ifdef CONFIG_DM_ETH
struct ueth_data ueth;
unsigned pkt_cnt;
uint8_t *pkt_data;
uint32_t *pkt_hdr;
-#endif
int flags;
int rx_urb_size;
int maxpacketsize;
@@ -505,249 +499,6 @@ static int asix_send_common(struct ueth_data *dev,
return err;
}
-#ifndef CONFIG_DM_ETH
-/*
- * Asix callbacks
- */
-static int asix_init(struct eth_device *eth, struct bd_info *bd)
-{
- struct ueth_data *dev = (struct ueth_data *)eth->priv;
- struct asix_private *dev_priv = (struct asix_private *)dev->dev_priv;
-
- return asix_init_common(dev, dev_priv);
-}
-
-static int asix_write_hwaddr(struct eth_device *eth)
-{
- struct ueth_data *dev = (struct ueth_data *)eth->priv;
-
- return asix_write_mac(dev, eth->enetaddr);
-}
-
-static int asix_send(struct eth_device *eth, void *packet, int length)
-{
- struct ueth_data *dev = (struct ueth_data *)eth->priv;
- struct asix_private *dev_priv = (struct asix_private *)dev->dev_priv;
-
- return asix_send_common(dev, dev_priv, packet, length);
-}
-
-static int asix_recv(struct eth_device *eth)
-{
- struct ueth_data *dev = (struct ueth_data *)eth->priv;
- struct asix_private *dev_priv = (struct asix_private *)dev->dev_priv;
-
- u16 frame_pos;
- int err;
- int actual_len;
-
- int pkt_cnt;
- u32 rx_hdr;
- u16 hdr_off;
- u32 *pkt_hdr;
- ALLOC_CACHE_ALIGN_BUFFER(u8, recv_buf, dev_priv->rx_urb_size);
-
- actual_len = -1;
-
- debug("** %s()\n", __func__);
-
- err = usb_bulk_msg(dev->pusb_dev,
- usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in),
- (void *)recv_buf,
- dev_priv->rx_urb_size,
- &actual_len,
- USB_BULK_RECV_TIMEOUT);
- debug("Rx: len = %u, actual = %u, err = %d\n", dev_priv->rx_urb_size,
- actual_len, err);
-
- if (err != 0) {
- debug("Rx: failed to receive\n");
- return -ECOMM;
- }
- if (actual_len > dev_priv->rx_urb_size) {
- debug("Rx: received too many bytes %d\n", actual_len);
- return -EMSGSIZE;
- }
-
-
- rx_hdr = *(u32 *)(recv_buf + actual_len - 4);
- le32_to_cpus(&rx_hdr);
-
- pkt_cnt = (u16)rx_hdr;
- hdr_off = (u16)(rx_hdr >> 16);
- pkt_hdr = (u32 *)(recv_buf + hdr_off);
-
-
- frame_pos = 0;
-
- while (pkt_cnt--) {
- u16 pkt_len;
-
- le32_to_cpus(pkt_hdr);
- pkt_len = (*pkt_hdr >> 16) & 0x1fff;
-
- frame_pos += 2;
-
- net_process_received_packet(recv_buf + frame_pos, pkt_len);
-
- pkt_hdr++;
- frame_pos += ((pkt_len + 7) & 0xFFF8)-2;
-
- if (pkt_cnt == 0)
- return 0;
- }
- return err;
-}
-
-static void asix_halt(struct eth_device *eth)
-{
- debug("** %s()\n", __func__);
-}
-
-/*
- * Asix probing functions
- */
-void ax88179_eth_before_probe(void)
-{
- curr_eth_dev = 0;
-}
-
-struct asix_dongle {
- unsigned short vendor;
- unsigned short product;
- int flags;
-};
-
-static const struct asix_dongle asix_dongles[] = {
- { 0x0b95, 0x1790, FLAG_TYPE_AX88179 },
- { 0x0b95, 0x178a, FLAG_TYPE_AX88178a },
- { 0x2001, 0x4a00, FLAG_TYPE_DLINK_DUB1312 },
- { 0x0df6, 0x0072, FLAG_TYPE_SITECOM },
- { 0x04e8, 0xa100, FLAG_TYPE_SAMSUNG },
- { 0x17ef, 0x304b, FLAG_TYPE_LENOVO },
- { 0x04b4, 0x3610, FLAG_TYPE_GX3 },
- { 0x0000, 0x0000, FLAG_NONE } /* END - Do not remove */
-};
-
-/* Probe to see if a new device is actually an asix device */
-int ax88179_eth_probe(struct usb_device *dev, unsigned int ifnum,
- struct ueth_data *ss)
-{
- struct usb_interface *iface;
- struct usb_interface_descriptor *iface_desc;
- struct asix_private *dev_priv;
- int ep_in_found = 0, ep_out_found = 0;
- int i;
-
- /* let's examine the device now */
- iface = &dev->config.if_desc[ifnum];
- iface_desc = &dev->config.if_desc[ifnum].desc;
-
- for (i = 0; asix_dongles[i].vendor != 0; i++) {
- if (dev->descriptor.idVendor == asix_dongles[i].vendor &&
- dev->descriptor.idProduct == asix_dongles[i].product)
- /* Found a supported dongle */
- break;
- }
-
- if (asix_dongles[i].vendor == 0)
- return 0;
-
- memset(ss, 0, sizeof(struct ueth_data));
-
- /* At this point, we know we've got a live one */
- debug("\n\nUSB Ethernet device detected: %#04x:%#04x\n",
- dev->descriptor.idVendor, dev->descriptor.idProduct);
-
- /* Initialize the ueth_data structure with some useful info */
- ss->ifnum = ifnum;
- ss->pusb_dev = dev;
- ss->subclass = iface_desc->bInterfaceSubClass;
- ss->protocol = iface_desc->bInterfaceProtocol;
-
- /* alloc driver private */
- ss->dev_priv = calloc(1, sizeof(struct asix_private));
- if (!ss->dev_priv)
- return 0;
- dev_priv = ss->dev_priv;
- dev_priv->flags = asix_dongles[i].flags;
-
- /*
- * We are expecting a minimum of 3 endpoints - in, out (bulk), and
- * int. We will ignore any others.
- */
- for (i = 0; i < iface_desc->bNumEndpoints; i++) {
- /* is it an interrupt endpoint? */
- if ((iface->ep_desc[i].bmAttributes &
- USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) {
- ss->ep_int = iface->ep_desc[i].bEndpointAddress &
- USB_ENDPOINT_NUMBER_MASK;
- ss->irqinterval = iface->ep_desc[i].bInterval;
- continue;
- }
-
- /* is it an BULK endpoint? */
- if (!((iface->ep_desc[i].bmAttributes &
- USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK))
- continue;
-
- u8 ep_addr = iface->ep_desc[i].bEndpointAddress;
- if ((ep_addr & USB_DIR_IN) && !ep_in_found) {
- ss->ep_in = ep_addr &
- USB_ENDPOINT_NUMBER_MASK;
- ep_in_found = 1;
- }
- if (!(ep_addr & USB_DIR_IN) && !ep_out_found) {
- ss->ep_out = ep_addr &
- USB_ENDPOINT_NUMBER_MASK;
- dev_priv->maxpacketsize =
- dev->epmaxpacketout[AX_ENDPOINT_OUT];
- ep_out_found = 1;
- }
- }
- debug("Endpoints In %d Out %d Int %d\n",
- ss->ep_in, ss->ep_out, ss->ep_int);
-
- /* Do some basic sanity checks, and bail if we find a problem */
- if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) ||
- !ss->ep_in || !ss->ep_out || !ss->ep_int) {
- debug("Problems with device\n");
- return 0;
- }
- dev->privptr = (void *)ss;
- return 1;
-}
-
-int ax88179_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
- struct eth_device *eth)
-{
- struct asix_private *dev_priv = (struct asix_private *)ss->dev_priv;
-
- if (!eth) {
- debug("%s: missing parameter.\n", __func__);
- return 0;
- }
- sprintf(eth->name, "%s%d", ASIX_BASE_NAME, curr_eth_dev++);
- eth->init = asix_init;
- eth->send = asix_send;
- eth->recv = asix_recv;
- eth->halt = asix_halt;
- eth->write_hwaddr = asix_write_hwaddr;
- eth->priv = ss;
-
- if (asix_basic_reset(ss, dev_priv))
- return 0;
-
- /* Get the MAC address */
- if (asix_read_mac(ss, eth->enetaddr))
- return 0;
- debug("MAC %pM\n", eth->enetaddr);
-
- return 1;
-}
-
-#else /* !CONFIG_DM_ETH */
-
static int ax88179_eth_start(struct udevice *dev)
{
struct asix_private *priv = dev_get_priv(dev);
@@ -918,4 +669,3 @@ static const struct usb_device_id ax88179_eth_id_table[] = {
};
U_BOOT_USB_DEVICE(ax88179_eth, ax88179_eth_id_table);
-#endif /* !CONFIG_DM_ETH */
diff --git a/drivers/usb/eth/mcs7830.c b/drivers/usb/eth/mcs7830.c
index 783ab62f6b7..8a256b3e346 100644
--- a/drivers/usb/eth/mcs7830.c
+++ b/drivers/usb/eth/mcs7830.c
@@ -86,10 +86,8 @@ struct mcs7830_regs {
* @mchash: shadow for the network adapter's multicast hash registers
*/
struct mcs7830_private {
-#ifdef CONFIG_DM_ETH
uint8_t rx_buf[MCS7830_RX_URB_SIZE];
struct ueth_data ueth;
-#endif
uint8_t config;
uint8_t mchash[8];
};
@@ -575,279 +573,6 @@ static int mcs7830_recv_common(struct ueth_data *ueth, uint8_t *buf)
return -EIO;
}
-#ifndef CONFIG_DM_ETH
-/*
- * mcs7830_init() - network interface's init callback
- * @udev: network device to initialize
- * @bd: board information
- * Return: zero upon success, negative upon error
- *
- * after initial setup during probe() and get_info(), this init() callback
- * ensures that the link is up and subsequent send() and recv() calls can
- * exchange ethernet frames
- */
-static int mcs7830_init(struct eth_device *eth, struct bd_info *bd)
-{
- struct ueth_data *dev = eth->priv;
-
- return mcs7830_init_common(dev->pusb_dev);
-}
-
-/*
- * mcs7830_send() - network interface's send callback
- * @eth: network device to send the frame from
- * @packet: ethernet frame content
- * @length: ethernet frame length
- * Return: zero upon success, negative upon error
- *
- * this routine send an ethernet frame out of the network interface
- */
-static int mcs7830_send(struct eth_device *eth, void *packet, int length)
-{
- struct ueth_data *dev = eth->priv;
-
- return mcs7830_send_common(dev, packet, length);
-}
-
-/*
- * mcs7830_recv() - network interface's recv callback
- * @eth: network device to receive frames from
- * Return: zero upon success, negative upon error
- *
- * this routine checks for available ethernet frames that the network
- * interface might have received, and notifies the network stack
- */
-static int mcs7830_recv(struct eth_device *eth)
-{
- ALLOC_CACHE_ALIGN_BUFFER(uint8_t, buf, MCS7830_RX_URB_SIZE);
- struct ueth_data *ueth = eth->priv;
- int len;
-
- len = mcs7830_recv_common(ueth, buf);
- if (len >= 0) {
- net_process_received_packet(buf, len);
- return 0;
- }
-
- return len;
-}
-
-/*
- * mcs7830_halt() - network interface's halt callback
- * @eth: network device to cease operation of
- * Return: none
- *
- * this routine is supposed to undo the effect of previous initialization and
- * ethernet frames exchange; in this implementation it's a NOP
- */
-static void mcs7830_halt(struct eth_device *eth)
-{
- debug("%s()\n", __func__);
-}
-
-/*
- * mcs7830_write_mac() - write an ethernet adapter's MAC address
- * @eth: network device to write to
- * Return: zero upon success, negative upon error
- *
- * this routine takes the MAC address from the ethernet interface's data
- * structure, and writes it into the ethernet adapter such that subsequent
- * exchange of ethernet frames uses this address
- */
-static int mcs7830_write_mac(struct eth_device *eth)
-{
- struct ueth_data *ueth = eth->priv;
-
- return mcs7830_write_mac_common(ueth->pusb_dev, eth->enetaddr);
-}
-
-/*
- * mcs7830_iface_idx - index of detected network interfaces
- *
- * this counter keeps track of identified supported interfaces,
- * to assign unique names as more interfaces are found
- */
-static int mcs7830_iface_idx;
-
-/*
- * mcs7830_eth_before_probe() - network driver's before_probe callback
- * Return: none
- *
- * this routine initializes driver's internal data in preparation of
- * subsequent probe callbacks
- */
-void mcs7830_eth_before_probe(void)
-{
- mcs7830_iface_idx = 0;
-}
-
-/*
- * struct mcs7830_dongle - description of a supported Moschip ethernet dongle
- * @vendor: 16bit USB vendor identification
- * @product: 16bit USB product identification
- *
- * this structure describes a supported USB ethernet dongle by means of the
- * vendor and product codes found during USB enumeration; no flags are held
- * here since all supported dongles have identical behaviour, and required
- * fixups get determined at runtime, such that no manual configuration is
- * needed
- */
-struct mcs7830_dongle {
- uint16_t vendor;
- uint16_t product;
-};
-
-/*
- * mcs7830_dongles - the list of supported Moschip based USB ethernet dongles
- */
-static const struct mcs7830_dongle mcs7830_dongles[] = {
- { 0x9710, 0x7832, }, /* Moschip 7832 */
- { 0x9710, 0x7830, }, /* Moschip 7830 */
- { 0x9710, 0x7730, }, /* Moschip 7730 */
- { 0x0df6, 0x0021, }, /* Sitecom LN 30 */
-};
-
-/*
- * mcs7830_eth_probe() - network driver's probe callback
- * @dev: detected USB device to check
- * @ifnum: detected USB interface to check
- * @ss: USB ethernet data structure to fill in upon match
- * Return: #1 upon match, #0 upon mismatch or error
- *
- * this routine checks whether the found USB device is supported by
- * this ethernet driver, and upon match fills in the USB ethernet
- * data structure which later is passed to the get_info callback
- */
-int mcs7830_eth_probe(struct usb_device *dev, unsigned int ifnum,
- struct ueth_data *ss)
-{
- struct usb_interface *iface;
- struct usb_interface_descriptor *iface_desc;
- int i;
- struct mcs7830_private *priv;
- int ep_in_found, ep_out_found, ep_intr_found;
-
- debug("%s()\n", __func__);
-
- /* iterate the list of supported dongles */
- iface = &dev->config.if_desc[ifnum];
- iface_desc = &iface->desc;
- for (i = 0; i < ARRAY_SIZE(mcs7830_dongles); i++) {
- if (dev->descriptor.idVendor == mcs7830_dongles[i].vendor &&
- dev->descriptor.idProduct == mcs7830_dongles[i].product)
- break;
- }
- if (i == ARRAY_SIZE(mcs7830_dongles))
- return 0;
- debug("detected USB ethernet device: %04X:%04X\n",
- dev->descriptor.idVendor, dev->descriptor.idProduct);
-
- /* fill in driver private data */
- priv = calloc(1, sizeof(*priv));
- if (!priv)
- return 0;
-
- /* fill in the ueth_data structure, attach private data */
- memset(ss, 0, sizeof(*ss));
- ss->ifnum = ifnum;
- ss->pusb_dev = dev;
- ss->subclass = iface_desc->bInterfaceSubClass;
- ss->protocol = iface_desc->bInterfaceProtocol;
- ss->dev_priv = priv;
-
- /*
- * a minimum of three endpoints is expected: in (bulk),
- * out (bulk), and interrupt; ignore all others
- */
- ep_in_found = ep_out_found = ep_intr_found = 0;
- for (i = 0; i < iface_desc->bNumEndpoints; i++) {
- uint8_t eptype, epaddr;
- bool is_input;
-
- eptype = iface->ep_desc[i].bmAttributes;
- eptype &= USB_ENDPOINT_XFERTYPE_MASK;
-
- epaddr = iface->ep_desc[i].bEndpointAddress;
- is_input = epaddr & USB_DIR_IN;
- epaddr &= USB_ENDPOINT_NUMBER_MASK;
-
- if (eptype == USB_ENDPOINT_XFER_BULK) {
- if (is_input && !ep_in_found) {
- ss->ep_in = epaddr;
- ep_in_found++;
- }
- if (!is_input && !ep_out_found) {
- ss->ep_out = epaddr;
- ep_out_found++;
- }
- }
-
- if (eptype == USB_ENDPOINT_XFER_INT) {
- if (is_input && !ep_intr_found) {
- ss->ep_int = epaddr;
- ss->irqinterval = iface->ep_desc[i].bInterval;
- ep_intr_found++;
- }
- }
- }
- debug("endpoints: in %d, out %d, intr %d\n",
- ss->ep_in, ss->ep_out, ss->ep_int);
-
- /* apply basic sanity checks */
- if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) ||
- !ss->ep_in || !ss->ep_out || !ss->ep_int) {
- debug("device probe incomplete\n");
- return 0;
- }
-
- dev->privptr = ss;
- return 1;
-}
-
-/*
- * mcs7830_eth_get_info() - network driver's get_info callback
- * @dev: detected USB device
- * @ss: USB ethernet data structure filled in at probe()
- * @eth: ethernet interface data structure to fill in
- * Return: #1 upon success, #0 upon error
- *
- * this routine registers the mandatory init(), send(), recv(), and
- * halt() callbacks with the ethernet interface, can register the
- * optional write_hwaddr() callback with the ethernet interface,
- * and initiates configuration of the interface such that subsequent
- * calls to those callbacks results in network communication
- */
-int mcs7830_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
- struct eth_device *eth)
-{
- debug("%s()\n", __func__);
- if (!eth) {
- debug("%s: missing parameter.\n", __func__);
- return 0;
- }
-
- snprintf(eth->name, sizeof(eth->name), "%s%d",
- MCS7830_BASE_NAME, mcs7830_iface_idx++);
- eth->init = mcs7830_init;
- eth->send = mcs7830_send;
- eth->recv = mcs7830_recv;
- eth->halt = mcs7830_halt;
- eth->write_hwaddr = mcs7830_write_mac;
- eth->priv = ss;
-
- if (mcs7830_basic_reset(ss->pusb_dev, ss->dev_priv))
- return 0;
-
- if (mcs7830_read_mac(ss->pusb_dev, eth->enetaddr))
- return 0;
- debug("MAC %pM\n", eth->enetaddr);
-
- return 1;
-}
-#endif
-
-
-#ifdef CONFIG_DM_ETH
static int mcs7830_eth_start(struct udevice *dev)
{
struct usb_device *udev = dev_get_parent_priv(dev);
@@ -942,4 +667,3 @@ static const struct usb_device_id mcs7830_eth_id_table[] = {
};
U_BOOT_USB_DEVICE(mcs7830_eth, mcs7830_eth_id_table);
-#endif
diff --git a/drivers/usb/eth/r8152.c b/drivers/usb/eth/r8152.c
index 1aaa5a79b3f..3c866f4f1e2 100644
--- a/drivers/usb/eth/r8152.c
+++ b/drivers/usb/eth/r8152.c
@@ -18,43 +18,6 @@
#include "usb_ether.h"
#include "r8152.h"
-#ifndef CONFIG_DM_ETH
-/* local vars */
-static int curr_eth_dev; /* index for name of next device detected */
-
-struct r8152_dongle {
- unsigned short vendor;
- unsigned short product;
-};
-
-static const struct r8152_dongle r8152_dongles[] = {
- /* Realtek */
- { 0x0bda, 0x8050 },
- { 0x0bda, 0x8152 },
- { 0x0bda, 0x8153 },
-
- /* Samsung */
- { 0x04e8, 0xa101 },
-
- /* Lenovo */
- { 0x17ef, 0x304f },
- { 0x17ef, 0x3052 },
- { 0x17ef, 0x3054 },
- { 0x17ef, 0x3057 },
- { 0x17ef, 0x7205 },
- { 0x17ef, 0x720a },
- { 0x17ef, 0x720b },
- { 0x17ef, 0x720c },
-
- /* TP-LINK */
- { 0x2357, 0x0601 },
- { 0x2357, 0x0602 },
-
- /* Nvidia */
- { 0x0955, 0x09ff },
-};
-#endif
-
struct r8152_version {
unsigned short tcr;
unsigned short version;
@@ -1479,243 +1442,6 @@ static int r8152_send_common(struct ueth_data *ueth, void *packet, int length)
return err;
}
-#ifndef CONFIG_DM_ETH
-static int r8152_init(struct eth_device *eth, struct bd_info *bd)
-{
- struct ueth_data *dev = (struct ueth_data *)eth->priv;
- struct r8152 *tp = (struct r8152 *)dev->dev_priv;
-
- return r8152_init_common(tp);
-}
-
-static int r8152_send(struct eth_device *eth, void *packet, int length)
-{
- struct ueth_data *dev = (struct ueth_data *)eth->priv;
-
- return r8152_send_common(dev, packet, length);
-}
-
-static int r8152_recv(struct eth_device *eth)
-{
- struct ueth_data *dev = (struct ueth_data *)eth->priv;
-
- ALLOC_CACHE_ALIGN_BUFFER(uint8_t, recv_buf, RTL8152_AGG_BUF_SZ);
- unsigned char *pkt_ptr;
- int err;
- int actual_len;
- u16 packet_len;
-
- u32 bytes_process = 0;
- struct rx_desc *rx_desc;
-
- debug("** %s()\n", __func__);
-
- err = usb_bulk_msg(dev->pusb_dev,
- usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in),
- (void *)recv_buf,
- RTL8152_AGG_BUF_SZ,
- &actual_len,
- USB_BULK_RECV_TIMEOUT);
- debug("Rx: len = %u, actual = %u, err = %d\n", RTL8152_AGG_BUF_SZ,
- actual_len, err);
- if (err != 0) {
- debug("Rx: failed to receive\n");
- return -1;
- }
- if (actual_len > RTL8152_AGG_BUF_SZ) {
- debug("Rx: received too many bytes %d\n", actual_len);
- return -1;
- }
-
- while (bytes_process < actual_len) {
- rx_desc = (struct rx_desc *)(recv_buf + bytes_process);
- pkt_ptr = recv_buf + sizeof(struct rx_desc) + bytes_process;
-
- packet_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
- packet_len -= CRC_SIZE;
-
- net_process_received_packet(pkt_ptr, packet_len);
-
- bytes_process +=
- (packet_len + sizeof(struct rx_desc) + CRC_SIZE);
-
- if (bytes_process % 8)
- bytes_process = bytes_process + 8 - (bytes_process % 8);
- }
-
- return 0;
-}
-
-static void r8152_halt(struct eth_device *eth)
-{
- struct ueth_data *dev = (struct ueth_data *)eth->priv;
- struct r8152 *tp = (struct r8152 *)dev->dev_priv;
-
- debug("** %s()\n", __func__);
-
- tp->rtl_ops.disable(tp);
-}
-
-static int r8152_write_hwaddr(struct eth_device *eth)
-{
- struct ueth_data *dev = (struct ueth_data *)eth->priv;
- struct r8152 *tp = (struct r8152 *)dev->dev_priv;
-
- unsigned char enetaddr[8] = {0};
-
- memcpy(enetaddr, eth->enetaddr, ETH_ALEN);
-
- ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
- pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, enetaddr);
- ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
-
- debug("MAC %pM\n", eth->enetaddr);
- return 0;
-}
-
-void r8152_eth_before_probe(void)
-{
- curr_eth_dev = 0;
-}
-
-/* Probe to see if a new device is actually an realtek device */
-int r8152_eth_probe(struct usb_device *dev, unsigned int ifnum,
- struct ueth_data *ss)
-{
- struct usb_interface *iface;
- struct usb_interface_descriptor *iface_desc;
- int ep_in_found = 0, ep_out_found = 0;
- struct r8152 *tp;
- int i;
-
- /* let's examine the device now */
- iface = &dev->config.if_desc[ifnum];
- iface_desc = &dev->config.if_desc[ifnum].desc;
-
- for (i = 0; i < ARRAY_SIZE(r8152_dongles); i++) {
- if (dev->descriptor.idVendor == r8152_dongles[i].vendor &&
- dev->descriptor.idProduct == r8152_dongles[i].product)
- /* Found a supported dongle */
- break;
- }
-
- if (i == ARRAY_SIZE(r8152_dongles))
- return 0;
-
- memset(ss, 0, sizeof(struct ueth_data));
-
- /* At this point, we know we've got a live one */
- debug("\n\nUSB Ethernet device detected: %#04x:%#04x\n",
- dev->descriptor.idVendor, dev->descriptor.idProduct);
-
- /* Initialize the ueth_data structure with some useful info */
- ss->ifnum = ifnum;
- ss->pusb_dev = dev;
- ss->subclass = iface_desc->bInterfaceSubClass;
- ss->protocol = iface_desc->bInterfaceProtocol;
-
- /* alloc driver private */
- ss->dev_priv = calloc(1, sizeof(struct r8152));
-
- if (!ss->dev_priv)
- return 0;
-
- /*
- * We are expecting a minimum of 3 endpoints - in, out (bulk), and
- * int. We will ignore any others.
- */
- for (i = 0; i < iface_desc->bNumEndpoints; i++) {
- /* is it an BULK endpoint? */
- if ((iface->ep_desc[i].bmAttributes &
- USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK) {
- u8 ep_addr = iface->ep_desc[i].bEndpointAddress;
-
- if (ep_addr & USB_DIR_IN) {
- if (!ep_in_found) {
- ss->ep_in = ep_addr &
- USB_ENDPOINT_NUMBER_MASK;
- ep_in_found = 1;
- }
- } else {
- if (!ep_out_found) {
- ss->ep_out = ep_addr &
- USB_ENDPOINT_NUMBER_MASK;
- ep_out_found = 1;
- }
- }
- }
-
- /* is it an interrupt endpoint? */
- if ((iface->ep_desc[i].bmAttributes &
- USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) {
- ss->ep_int = iface->ep_desc[i].bEndpointAddress &
- USB_ENDPOINT_NUMBER_MASK;
- ss->irqinterval = iface->ep_desc[i].bInterval;
- }
- }
-
- debug("Endpoints In %d Out %d Int %d\n",
- ss->ep_in, ss->ep_out, ss->ep_int);
-
- /* Do some basic sanity checks, and bail if we find a problem */
- if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) ||
- !ss->ep_in || !ss->ep_out || !ss->ep_int) {
- debug("Problems with device\n");
- goto error;
- }
-
- dev->privptr = (void *)ss;
-
- tp = ss->dev_priv;
- tp->udev = dev;
- tp->intf = iface;
-
- r8152b_get_version(tp);
-
- if (rtl_ops_init(tp))
- goto error;
-
- tp->rtl_ops.init(tp);
- tp->rtl_ops.up(tp);
-
- rtl8152_set_speed(tp, AUTONEG_ENABLE,
- tp->supports_gmii ? SPEED_1000 : SPEED_100,
- DUPLEX_FULL);
-
- return 1;
-
-error:
- cfree(ss->dev_priv);
- ss->dev_priv = 0;
- return 0;
-}
-
-int r8152_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
- struct eth_device *eth)
-{
- if (!eth) {
- debug("%s: missing parameter.\n", __func__);
- return 0;
- }
-
- sprintf(eth->name, "%s#%d", R8152_BASE_NAME, curr_eth_dev++);
- eth->init = r8152_init;
- eth->send = r8152_send;
- eth->recv = r8152_recv;
- eth->halt = r8152_halt;
- eth->write_hwaddr = r8152_write_hwaddr;
- eth->priv = ss;
-
- /* Get the MAC address */
- if (r8152_read_mac(ss->dev_priv, eth->enetaddr) < 0)
- return 0;
-
- debug("MAC %pM\n", eth->enetaddr);
- return 1;
-}
-#endif /* !CONFIG_DM_ETH */
-
-#ifdef CONFIG_DM_ETH
static int r8152_eth_start(struct udevice *dev)
{
struct r8152 *tp = dev_get_priv(dev);
@@ -1895,4 +1621,3 @@ static const struct usb_device_id r8152_eth_id_table[] = {
};
U_BOOT_USB_DEVICE(r8152_eth, r8152_eth_id_table);
-#endif /* CONFIG_DM_ETH */
diff --git a/drivers/usb/eth/r8152.h b/drivers/usb/eth/r8152.h
index 45172c055f4..7b128b1934b 100644
--- a/drivers/usb/eth/r8152.h
+++ b/drivers/usb/eth/r8152.h
@@ -642,9 +642,7 @@ struct r8152 {
u8 version;
-#ifdef CONFIG_DM_ETH
struct ueth_data ueth;
-#endif
};
int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
diff --git a/drivers/usb/eth/smsc95xx.c b/drivers/usb/eth/smsc95xx.c
index 283c52c16ac..de6586e6263 100644
--- a/drivers/usb/eth/smsc95xx.c
+++ b/drivers/usb/eth/smsc95xx.c
@@ -143,16 +143,9 @@
#define TURBO_MODE
-#ifndef CONFIG_DM_ETH
-/* local vars */
-static int curr_eth_dev; /* index for name of next device detected */
-#endif
-
/* driver private */
struct smsc95xx_private {
-#ifdef CONFIG_DM_ETH
struct ueth_data ueth;
-#endif
size_t rx_urb_size; /* maximum USB URB size */
u32 mac_cr; /* MAC control register value */
int have_hwaddr; /* 1 if we have a hardware MAC address */
@@ -521,11 +514,6 @@ static int smsc95xx_init_common(struct usb_device *udev, struct ueth_data *dev,
debug("timeout waiting for PHY Reset\n");
return -ETIMEDOUT;
}
-#ifndef CONFIG_DM_ETH
- if (!priv->have_hwaddr && smsc95xx_init_mac_address(enetaddr, udev) ==
- 0)
- priv->have_hwaddr = 1;
-#endif
if (!priv->have_hwaddr) {
puts("Error: SMSC95xx: No MAC address set - set usbethaddr\n");
return -EADDRNOTAVAIL;
@@ -712,227 +700,6 @@ static int smsc95xx_send_common(struct ueth_data *dev, void *packet, int length)
return err;
}
-#ifndef CONFIG_DM_ETH
-/*
- * Smsc95xx callbacks
- */
-static int smsc95xx_init(struct eth_device *eth, struct bd_info *bd)
-{
- struct ueth_data *dev = (struct ueth_data *)eth->priv;
- struct usb_device *udev = dev->pusb_dev;
- struct smsc95xx_private *priv =
- (struct smsc95xx_private *)dev->dev_priv;
-
- return smsc95xx_init_common(udev, dev, priv, eth->enetaddr);
-}
-
-static int smsc95xx_send(struct eth_device *eth, void *packet, int length)
-{
- struct ueth_data *dev = (struct ueth_data *)eth->priv;
-
- return smsc95xx_send_common(dev, packet, length);
-}
-
-static int smsc95xx_recv(struct eth_device *eth)
-{
- struct ueth_data *dev = (struct ueth_data *)eth->priv;
- DEFINE_CACHE_ALIGN_BUFFER(unsigned char, recv_buf, RX_URB_SIZE);
- unsigned char *buf_ptr;
- int err;
- int actual_len;
- u32 packet_len;
- int cur_buf_align;
-
- debug("** %s()\n", __func__);
- err = usb_bulk_msg(dev->pusb_dev,
- usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in),
- (void *)recv_buf, RX_URB_SIZE, &actual_len,
- USB_BULK_RECV_TIMEOUT);
- debug("Rx: len = %u, actual = %u, err = %d\n", RX_URB_SIZE,
- actual_len, err);
- if (err != 0) {
- debug("Rx: failed to receive\n");
- return -err;
- }
- if (actual_len > RX_URB_SIZE) {
- debug("Rx: received too many bytes %d\n", actual_len);
- return -ENOSPC;
- }
-
- buf_ptr = recv_buf;
- while (actual_len > 0) {
- /*
- * 1st 4 bytes contain the length of the actual data plus error
- * info. Extract data length.
- */
- if (actual_len < sizeof(packet_len)) {
- debug("Rx: incomplete packet length\n");
- return -EIO;
- }
- memcpy(&packet_len, buf_ptr, sizeof(packet_len));
- le32_to_cpus(&packet_len);
- if (packet_len & RX_STS_ES_) {
- debug("Rx: Error header=%#x", packet_len);
- return -EIO;
- }
- packet_len = ((packet_len & RX_STS_FL_) >> 16);
-
- if (packet_len > actual_len - sizeof(packet_len)) {
- debug("Rx: too large packet: %d\n", packet_len);
- return -EIO;
- }
-
- /* Notify net stack */
- net_process_received_packet(buf_ptr + sizeof(packet_len),
- packet_len - 4);
-
- /* Adjust for next iteration */
- actual_len -= sizeof(packet_len) + packet_len;
- buf_ptr += sizeof(packet_len) + packet_len;
- cur_buf_align = (ulong)buf_ptr - (ulong)recv_buf;
-
- if (cur_buf_align & 0x03) {
- int align = 4 - (cur_buf_align & 0x03);
-
- actual_len -= align;
- buf_ptr += align;
- }
- }
- return err;
-}
-
-static void smsc95xx_halt(struct eth_device *eth)
-{
- debug("** %s()\n", __func__);
-}
-
-static int smsc95xx_write_hwaddr(struct eth_device *eth)
-{
- struct ueth_data *dev = eth->priv;
- struct usb_device *udev = dev->pusb_dev;
- struct smsc95xx_private *priv = dev->dev_priv;
-
- return smsc95xx_write_hwaddr_common(udev, priv, eth->enetaddr);
-}
-
-/*
- * SMSC probing functions
- */
-void smsc95xx_eth_before_probe(void)
-{
- curr_eth_dev = 0;
-}
-
-struct smsc95xx_dongle {
- unsigned short vendor;
- unsigned short product;
-};
-
-static const struct smsc95xx_dongle smsc95xx_dongles[] = {
- { 0x0424, 0xec00 }, /* LAN9512/LAN9514 Ethernet */
- { 0x0424, 0x9500 }, /* LAN9500 Ethernet */
- { 0x0424, 0x9730 }, /* LAN9730 Ethernet (HSIC) */
- { 0x0424, 0x9900 }, /* SMSC9500 USB Ethernet Device (SAL10) */
- { 0x0424, 0x9e00 }, /* LAN9500A Ethernet */
- { 0x0000, 0x0000 } /* END - Do not remove */
-};
-
-/* Probe to see if a new device is actually an SMSC device */
-int smsc95xx_eth_probe(struct usb_device *dev, unsigned int ifnum,
- struct ueth_data *ss)
-{
- struct usb_interface *iface;
- struct usb_interface_descriptor *iface_desc;
- int i;
-
- /* let's examine the device now */
- iface = &dev->config.if_desc[ifnum];
- iface_desc = &dev->config.if_desc[ifnum].desc;
-
- for (i = 0; smsc95xx_dongles[i].vendor != 0; i++) {
- if (dev->descriptor.idVendor == smsc95xx_dongles[i].vendor &&
- dev->descriptor.idProduct == smsc95xx_dongles[i].product)
- /* Found a supported dongle */
- break;
- }
- if (smsc95xx_dongles[i].vendor == 0)
- return 0;
-
- /* At this point, we know we've got a live one */
- debug("\n\nUSB Ethernet device detected\n");
- memset(ss, '\0', sizeof(struct ueth_data));
-
- /* Initialize the ueth_data structure with some useful info */
- ss->ifnum = ifnum;
- ss->pusb_dev = dev;
- ss->subclass = iface_desc->bInterfaceSubClass;
- ss->protocol = iface_desc->bInterfaceProtocol;
-
- /*
- * We are expecting a minimum of 3 endpoints - in, out (bulk), and int.
- * We will ignore any others.
- */
- for (i = 0; i < iface_desc->bNumEndpoints; i++) {
- /* is it an BULK endpoint? */
- if ((iface->ep_desc[i].bmAttributes &
- USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK) {
- if (iface->ep_desc[i].bEndpointAddress & USB_DIR_IN)
- ss->ep_in =
- iface->ep_desc[i].bEndpointAddress &
- USB_ENDPOINT_NUMBER_MASK;
- else
- ss->ep_out =
- iface->ep_desc[i].bEndpointAddress &
- USB_ENDPOINT_NUMBER_MASK;
- }
-
- /* is it an interrupt endpoint? */
- if ((iface->ep_desc[i].bmAttributes &
- USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) {
- ss->ep_int = iface->ep_desc[i].bEndpointAddress &
- USB_ENDPOINT_NUMBER_MASK;
- ss->irqinterval = iface->ep_desc[i].bInterval;
- }
- }
- debug("Endpoints In %d Out %d Int %d\n",
- ss->ep_in, ss->ep_out, ss->ep_int);
-
- /* Do some basic sanity checks, and bail if we find a problem */
- if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) ||
- !ss->ep_in || !ss->ep_out || !ss->ep_int) {
- debug("Problems with device\n");
- return 0;
- }
- dev->privptr = (void *)ss;
-
- /* alloc driver private */
- ss->dev_priv = calloc(1, sizeof(struct smsc95xx_private));
- if (!ss->dev_priv)
- return 0;
-
- return 1;
-}
-
-int smsc95xx_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
- struct eth_device *eth)
-{
- debug("** %s()\n", __func__);
- if (!eth) {
- debug("%s: missing parameter.\n", __func__);
- return 0;
- }
- sprintf(eth->name, "%s%d", SMSC95XX_BASE_NAME, curr_eth_dev++);
- eth->init = smsc95xx_init;
- eth->send = smsc95xx_send;
- eth->recv = smsc95xx_recv;
- eth->halt = smsc95xx_halt;
- eth->write_hwaddr = smsc95xx_write_hwaddr;
- eth->priv = ss;
- return 1;
-}
-#endif /* !CONFIG_DM_ETH */
-
-#ifdef CONFIG_DM_ETH
static int smsc95xx_eth_start(struct udevice *dev)
{
struct usb_device *udev = dev_get_parent_priv(dev);
@@ -1077,4 +844,3 @@ static const struct usb_device_id smsc95xx_eth_id_table[] = {
};
U_BOOT_USB_DEVICE(smsc95xx_eth, smsc95xx_eth_id_table);
-#endif
diff --git a/drivers/usb/eth/usb_ether.c b/drivers/usb/eth/usb_ether.c
index e368ecda0d7..2e9af54fd63 100644
--- a/drivers/usb/eth/usb_ether.c
+++ b/drivers/usb/eth/usb_ether.c
@@ -15,8 +15,6 @@
#include "usb_ether.h"
-#ifdef CONFIG_DM_ETH
-
#define USB_BULK_RECV_TIMEOUT 500
int usb_ether_register(struct udevice *dev, struct ueth_data *ueth, int rxsize)
@@ -137,200 +135,3 @@ int usb_ether_get_rx_bytes(struct ueth_data *ueth, uint8_t **ptrp)
return ueth->rxlen - ueth->rxptr;
}
-
-#else
-
-typedef void (*usb_eth_before_probe)(void);
-typedef int (*usb_eth_probe)(struct usb_device *dev, unsigned int ifnum,
- struct ueth_data *ss);
-typedef int (*usb_eth_get_info)(struct usb_device *dev, struct ueth_data *ss,
- struct eth_device *dev_desc);
-
-struct usb_eth_prob_dev {
- usb_eth_before_probe before_probe; /* optional */
- usb_eth_probe probe;
- usb_eth_get_info get_info;
-};
-
-/* driver functions go here, each bracketed by #ifdef CONFIG_USB_ETHER_xxx */
-static const struct usb_eth_prob_dev prob_dev[] = {
-#ifdef CONFIG_USB_ETHER_ASIX
- {
- .before_probe = asix_eth_before_probe,
- .probe = asix_eth_probe,
- .get_info = asix_eth_get_info,
- },
-#endif
-#ifdef CONFIG_USB_ETHER_ASIX88179
- {
- .before_probe = ax88179_eth_before_probe,
- .probe = ax88179_eth_probe,
- .get_info = ax88179_eth_get_info,
- },
-#endif
-#ifdef CONFIG_USB_ETHER_MCS7830
- {
- .before_probe = mcs7830_eth_before_probe,
- .probe = mcs7830_eth_probe,
- .get_info = mcs7830_eth_get_info,
- },
-#endif
-#ifdef CONFIG_USB_ETHER_SMSC95XX
- {
- .before_probe = smsc95xx_eth_before_probe,
- .probe = smsc95xx_eth_probe,
- .get_info = smsc95xx_eth_get_info,
- },
-#endif
-#ifdef CONFIG_USB_ETHER_RTL8152
- {
- .before_probe = r8152_eth_before_probe,
- .probe = r8152_eth_probe,
- .get_info = r8152_eth_get_info,
- },
-#endif
- { }, /* END */
-};
-
-static int usb_max_eth_dev; /* number of highest available usb eth device */
-static struct ueth_data usb_eth[USB_MAX_ETH_DEV];
-
-/*******************************************************************************
- * tell if current ethernet device is a usb dongle
- */
-int is_eth_dev_on_usb_host(void)
-{
- int i;
- struct eth_device *dev = eth_get_dev();
-
- if (dev) {
- for (i = 0; i < usb_max_eth_dev; i++)
- if (&usb_eth[i].eth_dev == dev)
- return 1;
- }
- return 0;
-}
-
-/*
- * Given a USB device, ask each driver if it can support it, and attach it
- * to the first driver that says 'yes'
- */
-static void probe_valid_drivers(struct usb_device *dev)
-{
- struct eth_device *eth;
- int j;
-
- for (j = 0; prob_dev[j].probe && prob_dev[j].get_info; j++) {
- if (!prob_dev[j].probe(dev, 0, &usb_eth[usb_max_eth_dev]))
- continue;
- /*
- * ok, it is a supported eth device. Get info and fill it in
- */
- eth = &usb_eth[usb_max_eth_dev].eth_dev;
- if (prob_dev[j].get_info(dev,
- &usb_eth[usb_max_eth_dev],
- eth)) {
- /* found proper driver */
- /* register with networking stack */
- usb_max_eth_dev++;
-
- /*
- * usb_max_eth_dev must be incremented prior to this
- * call since eth_current_changed (internally called)
- * relies on it
- */
- eth_register(eth);
- if (eth_write_hwaddr(eth, "usbeth",
- usb_max_eth_dev - 1))
- puts("Warning: failed to set MAC address\n");
- break;
- }
- }
- }
-
-/*******************************************************************************
- * scan the usb and reports device info
- * to the user if mode = 1
- * returns current device or -1 if no
- */
-int usb_host_eth_scan(int mode)
-{
- int i, old_async;
-
- if (mode == 1)
- printf(" scanning usb for ethernet devices... ");
-
- old_async = usb_disable_asynch(1); /* asynch transfer not allowed */
-
- /* unregister a previously detected device */
- for (i = 0; i < usb_max_eth_dev; i++)
- eth_unregister(&usb_eth[i].eth_dev);
-
- memset(usb_eth, 0, sizeof(usb_eth));
-
- for (i = 0; prob_dev[i].probe; i++) {
- if (prob_dev[i].before_probe)
- prob_dev[i].before_probe();
- }
-
- usb_max_eth_dev = 0;
-#if CONFIG_IS_ENABLED(DM_USB)
- /*
- * TODO: We should add U_BOOT_USB_DEVICE() declarations to each USB
- * Ethernet driver and then most of this file can be removed.
- */
- struct udevice *bus;
- struct uclass *uc;
- int ret;
-
- ret = uclass_get(UCLASS_USB, &uc);
- if (ret)
- return ret;
- uclass_foreach_dev(bus, uc) {
- for (i = 0; i < USB_MAX_DEVICE; i++) {
- struct usb_device *dev;
-
- dev = usb_get_dev_index(bus, i); /* get device */
- debug("i=%d, %s\n", i, dev ? dev->dev->name : "(done)");
- if (!dev)
- break; /* no more devices available */
-
- /*
- * find valid usb_ether driver for this device,
- * if any
- */
- probe_valid_drivers(dev);
-
- /* check limit */
- if (usb_max_eth_dev == USB_MAX_ETH_DEV)
- break;
- } /* for */
- }
-#else
- for (i = 0; i < USB_MAX_DEVICE; i++) {
- struct usb_device *dev;
-
- dev = usb_get_dev_index(i); /* get device */
- debug("i=%d\n", i);
- if (!dev)
- break; /* no more devices available */
-
- /* find valid usb_ether driver for this device, if any */
- probe_valid_drivers(dev);
-
- /* check limit */
- if (usb_max_eth_dev == USB_MAX_ETH_DEV)
- break;
- } /* for */
-#endif
- if (usb_max_eth_dev == USB_MAX_ETH_DEV) {
- printf("max USB Ethernet Device reached: %d stopping\n",
- usb_max_eth_dev);
- }
- usb_disable_asynch(old_async); /* restore asynch value */
- printf("%d Ethernet Device(s) found\n", usb_max_eth_dev);
- if (usb_max_eth_dev > 0)
- return 0;
- return -1;
-}
-#endif
diff --git a/drivers/usb/gadget/ep0.c b/drivers/usb/gadget/ep0.c
index 6624f61b763..c256cc31fbd 100644
--- a/drivers/usb/gadget/ep0.c
+++ b/drivers/usb/gadget/ep0.c
@@ -371,26 +371,7 @@ static int ep0_get_descriptor (struct usb_device_instance *device,
}
break;
case USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER:
-#if defined(CONFIG_USBD_HS)
- {
- struct usb_qualifier_descriptor *qualifier_descriptor =
- device->qualifier_descriptor;
-
- if (!qualifier_descriptor)
- return -1;
-
- /* copy descriptor for this device */
- copy_config(urb, qualifier_descriptor,
- sizeof(struct usb_qualifier_descriptor),
- max);
-
- }
- dbg_ep0(3, "copied qualifier descriptor, actual_length: 0x%x",
- urb->actual_length);
-#else
return -1;
-#endif
- break;
default:
return -1;
diff --git a/drivers/usb/gadget/ether.c b/drivers/usb/gadget/ether.c
index 43aec7ffa70..85c971e4c43 100644
--- a/drivers/usb/gadget/ether.c
+++ b/drivers/usb/gadget/ether.c
@@ -109,11 +109,7 @@ struct eth_dev {
struct usb_request *tx_req, *rx_req;
-#ifndef CONFIG_DM_ETH
- struct eth_device *net;
-#else
struct udevice *net;
-#endif
struct net_device_stats stats;
unsigned int tx_qlen;
@@ -140,11 +136,7 @@ struct eth_dev {
/*-------------------------------------------------------------------------*/
struct ether_priv {
struct eth_dev ethdev;
-#ifndef CONFIG_DM_ETH
- struct eth_device netdev;
-#else
struct udevice *netdev;
-#endif
struct usb_gadget_driver eth_driver;
};
@@ -1827,22 +1819,14 @@ static void rndis_control_ack_complete(struct usb_ep *ep,
static char rndis_resp_buf[8] __attribute__((aligned(sizeof(__le32))));
-#ifndef CONFIG_DM_ETH
-static int rndis_control_ack(struct eth_device *net)
-#else
static int rndis_control_ack(struct udevice *net)
-#endif
{
struct ether_priv *priv;
struct eth_dev *dev;
int length;
struct usb_request *resp;
-#ifndef CONFIG_DM_ETH
- priv = (struct ether_priv *)net->priv;
-#else
priv = dev_get_priv(net);
-#endif
dev = &priv->ethdev;
resp = dev->stat_req;
@@ -1989,9 +1973,7 @@ static int eth_bind(struct usb_gadget *gadget)
int status = -ENOMEM;
int gcnum;
u8 tmp[7];
-#ifdef CONFIG_DM_ETH
struct eth_pdata *pdata = dev_get_plat(l_priv->netdev);
-#endif
/* these flags are only ever cleared; compiler take note */
#ifndef CONFIG_USB_ETH_CDC
@@ -2168,11 +2150,7 @@ autoconf_fail:
/* network device setup */
-#ifndef CONFIG_DM_ETH
- dev->net = &l_priv->netdev;
-#else
dev->net = l_priv->netdev;
-#endif
dev->cdc = cdc;
dev->zlp = zlp;
@@ -2189,13 +2167,8 @@ autoconf_fail:
* host side code for the SAFE thing cares -- its original BLAN
* thing didn't, Sharp never assigned those addresses on Zaurii.
*/
-#ifndef CONFIG_DM_ETH
- get_ether_addr(dev_addr, dev->net->enetaddr);
- memcpy(tmp, dev->net->enetaddr, sizeof(dev->net->enetaddr));
-#else
get_ether_addr(dev_addr, pdata->enetaddr);
memcpy(tmp, pdata->enetaddr, sizeof(pdata->enetaddr));
-#endif
get_ether_addr(host_addr, dev->host_mac);
@@ -2256,11 +2229,7 @@ autoconf_fail:
status_ep ? " STATUS " : "",
status_ep ? status_ep->name : ""
);
-#ifndef CONFIG_DM_ETH
- printf("MAC %pM\n", dev->net->enetaddr);
-#else
printf("MAC %pM\n", pdata->enetaddr);
-#endif
if (cdc || rndis)
printf("HOST MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
@@ -2490,71 +2459,6 @@ static void _usb_eth_halt(struct ether_priv *priv)
usb_gadget_release(0);
}
-#ifndef CONFIG_DM_ETH
-static int usb_eth_init(struct eth_device *netdev, struct bd_info *bd)
-{
- struct ether_priv *priv = (struct ether_priv *)netdev->priv;
-
- return _usb_eth_init(priv);
-}
-
-static int usb_eth_send(struct eth_device *netdev, void *packet, int length)
-{
- struct ether_priv *priv = (struct ether_priv *)netdev->priv;
-
- return _usb_eth_send(priv, packet, length);
-}
-
-static int usb_eth_recv(struct eth_device *netdev)
-{
- struct ether_priv *priv = (struct ether_priv *)netdev->priv;
- struct eth_dev *dev = &priv->ethdev;
- int ret;
-
- ret = _usb_eth_recv(priv);
- if (ret) {
- pr_err("error packet receive\n");
- return ret;
- }
-
- if (!packet_received)
- return 0;
-
- if (dev->rx_req) {
- net_process_received_packet(net_rx_packets[0],
- dev->rx_req->length);
- } else {
- pr_err("dev->rx_req invalid");
- }
- packet_received = 0;
- rx_submit(dev, dev->rx_req, 0);
-
- return 0;
-}
-
-void usb_eth_halt(struct eth_device *netdev)
-{
- struct ether_priv *priv = (struct ether_priv *)netdev->priv;
-
- _usb_eth_halt(priv);
-}
-
-int usb_eth_initialize(struct bd_info *bi)
-{
- struct eth_device *netdev = &l_priv->netdev;
-
- strlcpy(netdev->name, USB_NET_NAME, sizeof(netdev->name));
-
- netdev->init = usb_eth_init;
- netdev->send = usb_eth_send;
- netdev->recv = usb_eth_recv;
- netdev->halt = usb_eth_halt;
- netdev->priv = l_priv;
-
- eth_register(netdev);
- return 0;
-}
-#else
static int usb_eth_start(struct udevice *dev)
{
struct ether_priv *priv = dev_get_priv(dev);
@@ -2663,4 +2567,3 @@ U_BOOT_DRIVER(eth_usb) = {
.plat_auto = sizeof(struct eth_pdata),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
-#endif /* CONFIG_DM_ETH */
diff --git a/drivers/usb/gadget/f_dfu.c b/drivers/usb/gadget/f_dfu.c
index 33ef62f8bab..44877df4ec6 100644
--- a/drivers/usb/gadget/f_dfu.c
+++ b/drivers/usb/gadget/f_dfu.c
@@ -325,7 +325,7 @@ static int state_dfu_idle(struct f_dfu *f_dfu,
switch (ctrl->bRequest) {
case USB_REQ_DFU_DNLOAD:
- if (ctrl->bRequestType == USB_DIR_OUT) {
+ if (!(ctrl->bRequestType & USB_DIR_IN)) {
if (len == 0) {
f_dfu->dfu_state = DFU_STATE_dfuERROR;
value = RET_STALL;
@@ -337,7 +337,7 @@ static int state_dfu_idle(struct f_dfu *f_dfu,
}
break;
case USB_REQ_DFU_UPLOAD:
- if (ctrl->bRequestType == USB_DIR_IN) {
+ if (ctrl->bRequestType & USB_DIR_IN) {
f_dfu->dfu_state = DFU_STATE_dfuUPLOAD_IDLE;
f_dfu->blk_seq_num = 0;
value = handle_upload(req, len);
@@ -436,7 +436,7 @@ static int state_dfu_dnload_idle(struct f_dfu *f_dfu,
switch (ctrl->bRequest) {
case USB_REQ_DFU_DNLOAD:
- if (ctrl->bRequestType == USB_DIR_OUT) {
+ if (!(ctrl->bRequestType & USB_DIR_IN)) {
f_dfu->dfu_state = DFU_STATE_dfuDNLOAD_SYNC;
f_dfu->blk_seq_num = w_value;
value = handle_dnload(gadget, len);
@@ -527,7 +527,7 @@ static int state_dfu_upload_idle(struct f_dfu *f_dfu,
switch (ctrl->bRequest) {
case USB_REQ_DFU_UPLOAD:
- if (ctrl->bRequestType == USB_DIR_IN) {
+ if (ctrl->bRequestType & USB_DIR_IN) {
/* state transition if less data then requested */
f_dfu->blk_seq_num = w_value;
value = handle_upload(req, len);
diff --git a/drivers/usb/gadget/f_sdp.c b/drivers/usb/gadget/f_sdp.c
index af4b167e17a..5ae5b62741a 100644
--- a/drivers/usb/gadget/f_sdp.c
+++ b/drivers/usb/gadget/f_sdp.c
@@ -868,7 +868,7 @@ static int sdp_handle_in_ep(struct spl_image_info *spl_image,
jump_to_image_no_args(&spl_image);
#else
/* In U-Boot, allow jumps to scripts */
- image_source_script(sdp_func->jmp_address, "script@1");
+ image_source_script(sdp_func->jmp_address, NULL, NULL);
#endif
}
diff --git a/drivers/usb/gadget/rndis.c b/drivers/usb/gadget/rndis.c
index 13c327ea38a..e7276ccd37a 100644
--- a/drivers/usb/gadget/rndis.c
+++ b/drivers/usb/gadget/rndis.c
@@ -855,14 +855,17 @@ static int rndis_set_response(int configNr, rndis_set_msg_type *buf)
rndis_set_cmplt_type *resp;
rndis_resp_t *r;
+ BufLength = get_unaligned_le32(&buf->InformationBufferLength);
+ BufOffset = get_unaligned_le32(&buf->InformationBufferOffset);
+ if ((BufOffset > RNDIS_MAX_TOTAL_SIZE - 8) ||
+ (BufLength > RNDIS_MAX_TOTAL_SIZE - 8 - BufOffset))
+ return -EINVAL;
+
r = rndis_add_response(configNr, sizeof(rndis_set_cmplt_type));
if (!r)
return -ENOMEM;
resp = (rndis_set_cmplt_type *) r->buf;
- BufLength = get_unaligned_le32(&buf->InformationBufferLength);
- BufOffset = get_unaligned_le32(&buf->InformationBufferOffset);
-
#ifdef VERBOSE
debug("%s: Length: %d\n", __func__, BufLength);
debug("%s: Offset: %d\n", __func__, BufOffset);
@@ -1115,11 +1118,7 @@ int rndis_msg_parser(u8 configNr, u8 *buf)
return -ENOTSUPP;
}
-#ifndef CONFIG_DM_ETH
-int rndis_register(int (*rndis_control_ack)(struct eth_device *))
-#else
int rndis_register(int (*rndis_control_ack)(struct udevice *))
-#endif
{
u8 i;
@@ -1147,13 +1146,8 @@ void rndis_deregister(int configNr)
return;
}
-#ifndef CONFIG_DM_ETH
-int rndis_set_param_dev(u8 configNr, struct eth_device *dev, int mtu,
- struct net_device_stats *stats, u16 *cdc_filter)
-#else
int rndis_set_param_dev(u8 configNr, struct udevice *dev, int mtu,
struct net_device_stats *stats, u16 *cdc_filter)
-#endif
{
debug("%s: configNr = %d\n", __func__, configNr);
if (!dev || !stats)
diff --git a/drivers/usb/gadget/rndis.h b/drivers/usb/gadget/rndis.h
index e827af0be4a..77db55a563f 100644
--- a/drivers/usb/gadget/rndis.h
+++ b/drivers/usb/gadget/rndis.h
@@ -226,13 +226,8 @@ typedef struct rndis_params {
u32 vendorID;
const char *vendorDescr;
-#ifndef CONFIG_DM_ETH
- struct eth_device *dev;
- int (*ack)(struct eth_device *);
-#else
struct udevice *dev;
int (*ack)(struct udevice *);
-#endif
struct list_head resp_queue;
} rndis_params;
@@ -240,15 +235,9 @@ typedef struct rndis_params {
int rndis_msg_parser(u8 configNr, u8 *buf);
enum rndis_state rndis_get_state(int configNr);
void rndis_deregister(int configNr);
-#ifndef CONFIG_DM_ETH
-int rndis_register(int (*rndis_control_ack)(struct eth_device *));
-int rndis_set_param_dev(u8 configNr, struct eth_device *dev, int mtu,
- struct net_device_stats *stats, u16 *cdc_filter);
-#else
int rndis_register(int (*rndis_control_ack)(struct udevice *));
int rndis_set_param_dev(u8 configNr, struct udevice *dev, int mtu,
struct net_device_stats *stats, u16 *cdc_filter);
-#endif
int rndis_set_param_vendor(u8 configNr, u32 vendorID,
const char *vendorDescr);
int rndis_set_param_medium(u8 configNr, u32 medium, u32 speed);
diff --git a/drivers/usb/host/ehci-mx5.c b/drivers/usb/host/ehci-mx5.c
index 964a53bb7c0..c11279867c7 100644
--- a/drivers/usb/host/ehci-mx5.c
+++ b/drivers/usb/host/ehci-mx5.c
@@ -299,10 +299,10 @@ static int ehci_usb_probe(struct udevice *dev)
HC_LENGTH(ehci_readl(&(hccr)->cr_capbase)));
setbits_le32(&ehci->usbmode, CM_HOST);
- __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
+ __raw_writel(CFG_MXC_USB_PORTSC, &ehci->portsc);
setbits_le32(&ehci->portsc, USB_EN);
- mxc_set_usbcontrol(priv->portnr, CONFIG_MXC_USB_FLAGS);
+ mxc_set_usbcontrol(priv->portnr, CFG_MXC_USB_FLAGS);
mdelay(10);
return ehci_register(dev, hccr, hcor, &mx5_ehci_ops, 0,
diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c
index fa2ca2a1d91..0a12db614ff 100644
--- a/drivers/usb/host/ehci-mx6.c
+++ b/drivers/usb/host/ehci-mx6.c
@@ -70,8 +70,8 @@ DECLARE_GLOBAL_DATA_PTR;
#define UCMD_RESET (1 << 1) /* controller reset */
/* If this is not defined, assume MX6/MX7/MX8M SoC default */
-#ifndef CONFIG_MXC_USB_PORTSC
-#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+#ifndef CFG_MXC_USB_PORTSC
+#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#endif
/* Base address for this IP block is 0x02184800 */
@@ -411,7 +411,7 @@ int ehci_hcd_init(int index, enum usb_init_type init,
return 0;
setbits_le32(&ehci->usbmode, CM_HOST);
- writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
+ writel(CFG_MXC_USB_PORTSC, &ehci->portsc);
setbits_le32(&ehci->portsc, USB_EN);
mdelay(10);
@@ -454,7 +454,7 @@ static u32 mx6_portsc(enum usb_phy_interface phy_type)
case USBPHY_INTERFACE_MODE_HSIC:
return PORT_PTS_HSIC;
default:
- return CONFIG_MXC_USB_PORTSC;
+ return CFG_MXC_USB_PORTSC;
}
}
diff --git a/drivers/usb/host/ohci-lpc32xx.c b/drivers/usb/host/ohci-lpc32xx.c
index 3be0b311a36..a04b2961b96 100644
--- a/drivers/usb/host/ohci-lpc32xx.c
+++ b/drivers/usb/host/ohci-lpc32xx.c
@@ -69,7 +69,7 @@ struct otg_regs {
#define OTG1_DM_PULLDOWN (1 << 3)
#define OTG1_VBUS_DRV (1 << 5)
-#define ISP1301_I2C_ADDR CONFIG_USB_ISP1301_I2C_ADDR
+#define ISP1301_I2C_ADDR CFG_USB_ISP1301_I2C_ADDR
#define ISP1301_I2C_MODE_CONTROL_1_SET 0x04
#define ISP1301_I2C_MODE_CONTROL_1_CLR 0x05
diff --git a/drivers/usb/host/usb-uclass.c b/drivers/usb/host/usb-uclass.c
index 060f3441df0..956e2a4e8e4 100644
--- a/drivers/usb/host/usb-uclass.c
+++ b/drivers/usb/host/usb-uclass.c
@@ -346,49 +346,6 @@ int usb_init(void)
return usb_started ? 0 : -1;
}
-/*
- * TODO(sjg@chromium.org): Remove this legacy function. At present it is needed
- * to support boards which use driver model for USB but not Ethernet, and want
- * to use USB Ethernet.
- *
- * The #if clause is here to ensure that remains the only case.
- */
-#if !defined(CONFIG_DM_ETH) && defined(CONFIG_USB_HOST_ETHER)
-static struct usb_device *find_child_devnum(struct udevice *parent, int devnum)
-{
- struct usb_device *udev;
- struct udevice *dev;
-
- if (!device_active(parent))
- return NULL;
- udev = dev_get_parent_priv(parent);
- if (udev->devnum == devnum)
- return udev;
-
- for (device_find_first_child(parent, &dev);
- dev;
- device_find_next_child(&dev)) {
- udev = find_child_devnum(dev, devnum);
- if (udev)
- return udev;
- }
-
- return NULL;
-}
-
-struct usb_device *usb_get_dev_index(struct udevice *bus, int index)
-{
- struct udevice *dev;
- int devnum = index + 1; /* Addresses are allocated from 1 on USB */
-
- device_find_first_child(bus, &dev);
- if (!dev)
- return NULL;
-
- return find_child_devnum(dev, devnum);
-}
-#endif
-
int usb_setup_ehci_gadget(struct ehci_ctrl **ctlrp)
{
struct usb_plat *plat;
diff --git a/drivers/video/nexell_display.c b/drivers/video/nexell_display.c
index 5595796a678..af2698ffca8 100644
--- a/drivers/video/nexell_display.c
+++ b/drivers/video/nexell_display.c
@@ -560,7 +560,7 @@ static int nx_display_bind(struct udevice *dev)
/* Datasheet S5p4418:
* Resolution up to 2048 x 1280, up to 12 Bit per color (HDMI)
* Actual (max.) size is 0x1000000 because in U-Boot nanopi2-2016.01
- * "#define CONFIG_FB_ADDR 0x77000000" and next address is
+ * "#define CFG_FB_ADDR 0x77000000" and next address is
* "#define BMP_LOAD_ADDR 0x78000000"
*/
plat->size = 0x1000000;
diff --git a/drivers/watchdog/designware_wdt.c b/drivers/watchdog/designware_wdt.c
index f8df1916b5f..447a22d3b36 100644
--- a/drivers/watchdog/designware_wdt.c
+++ b/drivers/watchdog/designware_wdt.c
@@ -132,7 +132,7 @@ static int designware_wdt_probe(struct udevice *dev)
goto err;
}
#else
- priv->clk_khz = CONFIG_DW_WDT_CLOCK_KHZ;
+ priv->clk_khz = CFG_DW_WDT_CLOCK_KHZ;
#endif
if (CONFIG_IS_ENABLED(DM_RESET) &&