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-rw-r--r--drivers/crypto/rsa_mod_exp/Makefile3
-rw-r--r--drivers/misc/Kconfig8
-rw-r--r--drivers/misc/Makefile1
-rw-r--r--drivers/misc/fsl_sec_mon.c146
-rw-r--r--drivers/mtd/nand/omap_gpmc.c28
-rw-r--r--drivers/net/designware.c9
-rw-r--r--drivers/net/designware.h4
-rw-r--r--drivers/video/am335x-fb.c13
-rw-r--r--drivers/video/am335x-fb.h9
9 files changed, 209 insertions, 12 deletions
diff --git a/drivers/crypto/rsa_mod_exp/Makefile b/drivers/crypto/rsa_mod_exp/Makefile
index 915b751dbe1..ae3dcf3d7ae 100644
--- a/drivers/crypto/rsa_mod_exp/Makefile
+++ b/drivers/crypto/rsa_mod_exp/Makefile
@@ -4,4 +4,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_RSA) += mod_exp_uclass.o mod_exp_sw.o
+obj-$(CONFIG_RSA) += mod_exp_uclass.o
+obj-$(CONFIG_RSA_SOFTWARE_EXP) += mod_exp_sw.o
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 0df25c331ff..36a8f0d098e 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -53,3 +53,11 @@ config DM_CROS_EC
but otherwise makes few changes. Since cros_ec also supports
LPC (which doesn't support driver model yet), a full
conversion is not yet possible.
+
+config CONFIG_FSL_SEC_MON
+ bool "Enable FSL SEC_MON Driver"
+ help
+ Freescale Security Monitor block is responsible for monitoring
+ system states.
+ Security Monitor can be transitioned on any security failures,
+ like software violations or hardware security violations.
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index a34972df4ee..6028cd43fb1 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -28,3 +28,4 @@ obj-$(CONFIG_SMSC_LPC47M) += smsc_lpc47m.o
obj-$(CONFIG_STATUS_LED) += status_led.o
obj-$(CONFIG_TWL4030_LED) += twl4030_led.o
obj-$(CONFIG_FSL_IFC) += fsl_ifc.o
+obj-$(CONFIG_FSL_SEC_MON) += fsl_sec_mon.o
diff --git a/drivers/misc/fsl_sec_mon.c b/drivers/misc/fsl_sec_mon.c
new file mode 100644
index 00000000000..d482a7db9ca
--- /dev/null
+++ b/drivers/misc/fsl_sec_mon.c
@@ -0,0 +1,146 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <fsl_sec_mon.h>
+
+int change_sec_mon_state(u32 initial_state, u32 final_state)
+{
+ struct ccsr_sec_mon_regs *sec_mon_regs = (void *)
+ (CONFIG_SYS_SEC_MON_ADDR);
+ u32 sts = sec_mon_in32(&sec_mon_regs->hp_stat);
+ int timeout = 10;
+
+ if ((sts & HPSR_SSM_ST_MASK) != initial_state)
+ return -1;
+
+ if (initial_state == HPSR_SSM_ST_TRUST) {
+ switch (final_state) {
+ case HPSR_SSM_ST_NON_SECURE:
+ printf("SEC_MON state transitioning to Soft Fail.\n");
+ sec_mon_setbits32(&sec_mon_regs->hp_com, HPCOMR_SW_SV);
+
+ /*
+ * poll till SEC_MON is in
+ * Soft Fail state
+ */
+ while (((sts & HPSR_SSM_ST_MASK) !=
+ HPSR_SSM_ST_SOFT_FAIL)) {
+ while (timeout) {
+ sts = sec_mon_in32
+ (&sec_mon_regs->hp_stat);
+
+ if ((sts & HPSR_SSM_ST_MASK) ==
+ HPSR_SSM_ST_SOFT_FAIL)
+ break;
+
+ udelay(10);
+ timeout--;
+ }
+ }
+
+ if (timeout == 0) {
+ printf("SEC_MON state transition timeout.\n");
+ return -1;
+ }
+
+ timeout = 10;
+
+ printf("SEC_MON state transitioning to Non Secure.\n");
+ sec_mon_setbits32(&sec_mon_regs->hp_com, HPCOMR_SSM_ST);
+
+ /*
+ * poll till SEC_MON is in
+ * Non Secure state
+ */
+ while (((sts & HPSR_SSM_ST_MASK) !=
+ HPSR_SSM_ST_NON_SECURE)) {
+ while (timeout) {
+ sts = sec_mon_in32
+ (&sec_mon_regs->hp_stat);
+
+ if ((sts & HPSR_SSM_ST_MASK) ==
+ HPSR_SSM_ST_NON_SECURE)
+ break;
+
+ udelay(10);
+ timeout--;
+ }
+ }
+
+ if (timeout == 0) {
+ printf("SEC_MON state transition timeout.\n");
+ return -1;
+ }
+ break;
+ case HPSR_SSM_ST_SOFT_FAIL:
+ printf("SEC_MON state transitioning to Soft Fail.\n");
+ sec_mon_setbits32(&sec_mon_regs->hp_com, HPCOMR_SW_FSV);
+
+ /*
+ * polling loop till SEC_MON is in
+ * Soft Fail state
+ */
+ while (((sts & HPSR_SSM_ST_MASK) !=
+ HPSR_SSM_ST_SOFT_FAIL)) {
+ while (timeout) {
+ sts = sec_mon_in32
+ (&sec_mon_regs->hp_stat);
+
+ if ((sts & HPSR_SSM_ST_MASK) ==
+ HPSR_SSM_ST_SOFT_FAIL)
+ break;
+
+ udelay(10);
+ timeout--;
+ }
+ }
+
+ if (timeout == 0) {
+ printf("SEC_MON state transition timeout.\n");
+ return -1;
+ }
+ break;
+ default:
+ return -1;
+ }
+ } else if (initial_state == HPSR_SSM_ST_NON_SECURE) {
+ switch (final_state) {
+ case HPSR_SSM_ST_SOFT_FAIL:
+ printf("SEC_MON state transitioning to Soft Fail.\n");
+ sec_mon_setbits32(&sec_mon_regs->hp_com, HPCOMR_SW_FSV);
+
+ /*
+ * polling loop till SEC_MON is in
+ * Soft Fail state
+ */
+ while (((sts & HPSR_SSM_ST_MASK) !=
+ HPSR_SSM_ST_SOFT_FAIL)) {
+ while (timeout) {
+ sts = sec_mon_in32
+ (&sec_mon_regs->hp_stat);
+
+ if ((sts & HPSR_SSM_ST_MASK) ==
+ HPSR_SSM_ST_SOFT_FAIL)
+ break;
+
+ udelay(10);
+ timeout--;
+ }
+ }
+
+ if (timeout == 0) {
+ printf("SEC_MON state transition timeout.\n");
+ return -1;
+ }
+ break;
+ default:
+ return -1;
+ }
+ }
+
+ return 0;
+}
diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c
index 24123fcfe53..610f9698e15 100644
--- a/drivers/mtd/nand/omap_gpmc.c
+++ b/drivers/mtd/nand/omap_gpmc.c
@@ -30,13 +30,22 @@ static u8 bch8_polynomial[] = {0xef, 0x51, 0x2e, 0x09, 0xed, 0x93, 0x9a, 0xc2,
static uint8_t cs_next;
static __maybe_unused struct nand_ecclayout omap_ecclayout;
+#if defined(CONFIG_NAND_OMAP_GPMC_WSCFG)
+static const int8_t wscfg[CONFIG_SYS_MAX_NAND_DEVICE] =
+ { CONFIG_NAND_OMAP_GPMC_WSCFG };
+#else
+/* wscfg is preset to zero since its a static variable */
+static const int8_t wscfg[CONFIG_SYS_MAX_NAND_DEVICE];
+#endif
+
/*
* Driver configurations
*/
struct omap_nand_info {
struct bch_control *control;
enum omap_ecc ecc_scheme;
- int cs;
+ uint8_t cs;
+ uint8_t ws; /* wait status pin (0,1) */
};
/* We are wasting a bit of memory but al least we are safe */
@@ -76,7 +85,9 @@ static void omap_nand_hwcontrol(struct mtd_info *mtd, int32_t cmd,
/* Check wait pin as dev ready indicator */
static int omap_dev_ready(struct mtd_info *mtd)
{
- return gpmc_cfg->status & (1 << 8);
+ register struct nand_chip *this = mtd->priv;
+ struct omap_nand_info *info = this->priv;
+ return gpmc_cfg->status & (1 << (8 + info->ws));
}
/*
@@ -901,8 +912,18 @@ int __maybe_unused omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength)
return -EINVAL;
}
} else {
- err = omap_select_ecc_scheme(nand, OMAP_ECC_HAM1_CODE_SW,
+ if (eccstrength == 1) {
+ err = omap_select_ecc_scheme(nand,
+ OMAP_ECC_HAM1_CODE_SW,
mtd->writesize, mtd->oobsize);
+ } else if (eccstrength == 8) {
+ err = omap_select_ecc_scheme(nand,
+ OMAP_ECC_BCH8_CODE_HW_DETECTION_SW,
+ mtd->writesize, mtd->oobsize);
+ } else {
+ printf("nand: error: unsupported ECC scheme\n");
+ return -EINVAL;
+ }
}
/* Update NAND handling after ECC mode switch */
@@ -962,6 +983,7 @@ int board_nand_init(struct nand_chip *nand)
nand->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
omap_nand_info[cs].control = NULL;
omap_nand_info[cs].cs = cs;
+ omap_nand_info[cs].ws = wscfg[cs];
nand->priv = &omap_nand_info[cs];
nand->cmd_ctrl = omap_nand_hwcontrol;
nand->options |= NAND_NO_PADDING | NAND_CACHEPRG;
diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index c03e935e2fb..cc01604e602 100644
--- a/drivers/net/designware.c
+++ b/drivers/net/designware.c
@@ -253,11 +253,20 @@ static int dw_eth_init(struct eth_device *dev, bd_t *bis)
writel(FIXEDBURST | PRIORXTX_41 | DMA_PBL, &dma_p->busmode);
+#ifndef CONFIG_DW_MAC_FORCE_THRESHOLD_MODE
writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD,
&dma_p->opmode);
+#else
+ writel(readl(&dma_p->opmode) | FLUSHTXFIFO,
+ &dma_p->opmode);
+#endif
writel(readl(&dma_p->opmode) | RXSTART | TXSTART, &dma_p->opmode);
+#ifdef CONFIG_DW_AXI_BURST_LEN
+ writel((CONFIG_DW_AXI_BURST_LEN & 0x1FF >> 1), &dma_p->axibus);
+#endif
+
/* Start up the PHY */
if (phy_startup(priv->phydev)) {
printf("Could not initialize PHY %s\n",
diff --git a/drivers/net/designware.h b/drivers/net/designware.h
index ce51102052e..49d900cb3f9 100644
--- a/drivers/net/designware.h
+++ b/drivers/net/designware.h
@@ -68,7 +68,9 @@ struct eth_dma_regs {
u32 status; /* 0x14 */
u32 opmode; /* 0x18 */
u32 intenable; /* 0x1c */
- u8 reserved[40];
+ u32 reserved1[2];
+ u32 axibus; /* 0x28 */
+ u32 reserved2[7];
u32 currhosttxdesc; /* 0x48 */
u32 currhostrxdesc; /* 0x4c */
u32 currhosttxbuffaddr; /* 0x50 */
diff --git a/drivers/video/am335x-fb.c b/drivers/video/am335x-fb.c
index ab9894102dc..6f956499d75 100644
--- a/drivers/video/am335x-fb.c
+++ b/drivers/video/am335x-fb.c
@@ -127,6 +127,12 @@ int am335xfb_init(struct am335x_lcdpanel *panel)
memset((void *)gd->fb_base, 0, 0x20);
*(unsigned int *)gd->fb_base = 0x4000;
+ /* turn ON display through powercontrol function if accessible */
+ if (0 != panel->panel_power_ctrl)
+ panel->panel_power_ctrl(1);
+
+ debug("am335x-fb: wait for stable power ...\n");
+ mdelay(panel->pup_delay);
lcdhw->clkc_enable = LCD_CORECLKEN | LCD_LIDDCLKEN | LCD_DMACLKEN;
lcdhw->raster_ctrl = 0;
lcdhw->ctrl = LCD_CLK_DIVISOR(panel->pxl_clk_div) | LCD_RASTER_MODE;
@@ -159,11 +165,8 @@ int am335xfb_init(struct am335x_lcdpanel *panel)
gd->fb_base += 0x20; /* point fb behind palette */
- /* turn ON display through powercontrol function if accessible */
- if (0 != panel->panel_power_ctrl) {
- mdelay(panel->pon_delay);
- panel->panel_power_ctrl(1);
- }
+ debug("am335x-fb: waiting picture to be stable.\n.");
+ mdelay(panel->pon_delay);
return 0;
}
diff --git a/drivers/video/am335x-fb.h b/drivers/video/am335x-fb.h
index 8a0b1314958..7f799d1f31c 100644
--- a/drivers/video/am335x-fb.h
+++ b/drivers/video/am335x-fb.h
@@ -55,9 +55,14 @@ struct am335x_lcdpanel {
unsigned int vsw; /* Vertical Sync Pulse Width */
unsigned int pxl_clk_div; /* Pixel clock divider*/
unsigned int pol; /* polarity of sync, clock signals */
+ unsigned int pup_delay; /*
+ * time in ms after power on to
+ * initialization of lcd-controller
+ * (VCC ramp up time)
+ */
unsigned int pon_delay; /*
- * time in ms for turning on lcd after
- * initializing lcd-controller
+ * time in ms after initialization of
+ * lcd-controller (pic stabilization)
*/
void (*panel_power_ctrl)(int); /* fp for power on/off display */
};
generated by cgit v1.2.3 (git 2.0.4) at 2025-10-12 17:00:28 +0000