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-rw-r--r--drivers/Kconfig2
-rw-r--r--drivers/core/device.c30
-rw-r--r--drivers/core/uclass.c2
-rw-r--r--drivers/ddr/Kconfig1
-rw-r--r--drivers/ddr/altera/Kconfig5
-rw-r--r--drivers/ddr/altera/Makefile4
-rw-r--r--drivers/ddr/fsl/main.c4
-rw-r--r--drivers/gpio/Kconfig13
-rw-r--r--drivers/gpio/at91_gpio.c170
-rw-r--r--drivers/mmc/Kconfig15
-rw-r--r--drivers/mmc/Makefile1
-rw-r--r--drivers/mmc/bcm2835_sdhci.c8
-rw-r--r--drivers/mmc/gen_atmel_mci.c158
-rw-r--r--drivers/mmc/meson_gx_mmc.c291
-rw-r--r--drivers/mmc/sdhci.c15
-rw-r--r--drivers/mtd/nand/atmel_nand.c5
-rw-r--r--drivers/net/at91_emac.c4
-rw-r--r--drivers/net/phy/Kconfig13
-rw-r--r--drivers/pinctrl/Kconfig14
-rw-r--r--drivers/pinctrl/Makefile1
-rw-r--r--drivers/pinctrl/pinctrl-at91.c453
-rw-r--r--drivers/serial/ns16550.c13
-rw-r--r--drivers/serial/serial_pl01x.c2
-rw-r--r--drivers/video/mxsfb.c2
24 files changed, 1158 insertions, 68 deletions
diff --git a/drivers/Kconfig b/drivers/Kconfig
index 0e5d97d1664..3e6bbacd15c 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -14,6 +14,8 @@ source "drivers/cpu/Kconfig"
source "drivers/crypto/Kconfig"
+source "drivers/ddr/Kconfig"
+
source "drivers/demo/Kconfig"
source "drivers/ddr/fsl/Kconfig"
diff --git a/drivers/core/device.c b/drivers/core/device.c
index e1b0ebffc55..09a115f753d 100644
--- a/drivers/core/device.c
+++ b/drivers/core/device.c
@@ -255,8 +255,36 @@ static void *alloc_priv(int size, uint flags)
if (flags & DM_FLAG_ALLOC_PRIV_DMA) {
priv = memalign(ARCH_DMA_MINALIGN, size);
- if (priv)
+ if (priv) {
memset(priv, '\0', size);
+
+ /*
+ * Ensure that the zero bytes are flushed to memory.
+ * This prevents problems if the driver uses this as
+ * both an input and an output buffer:
+ *
+ * 1. Zeroes written to buffer (here) and sit in the
+ * cache
+ * 2. Driver issues a read command to DMA
+ * 3. CPU runs out of cache space and evicts some cache
+ * data in the buffer, writing zeroes to RAM from
+ * the memset() above
+ * 4. DMA completes
+ * 5. Buffer now has some DMA data and some zeroes
+ * 6. Data being read is now incorrect
+ *
+ * To prevent this, ensure that the cache is clean
+ * within this range at the start. The driver can then
+ * use normal flush-after-write, invalidate-before-read
+ * procedures.
+ *
+ * TODO(sjg@chromium.org): Drop this microblaze
+ * exception.
+ */
+#ifndef CONFIG_MICROBLAZE
+ flush_dcache_range((ulong)priv, (ulong)priv + size);
+#endif
+ }
} else {
priv = calloc(1, size);
}
diff --git a/drivers/core/uclass.c b/drivers/core/uclass.c
index d94d43a98d2..04fb45b01a5 100644
--- a/drivers/core/uclass.c
+++ b/drivers/core/uclass.c
@@ -250,7 +250,7 @@ int uclass_find_device_by_seq(enum uclass_id id, int seq_or_req_seq,
return ret;
list_for_each_entry(dev, &uc->dev_head, uclass_node) {
- debug(" - %d %d\n", dev->req_seq, dev->seq);
+ debug(" - %d %d '%s'\n", dev->req_seq, dev->seq, dev->name);
if ((find_req_seq ? dev->req_seq : dev->seq) ==
seq_or_req_seq) {
*devp = dev;
diff --git a/drivers/ddr/Kconfig b/drivers/ddr/Kconfig
new file mode 100644
index 00000000000..b764add060e
--- /dev/null
+++ b/drivers/ddr/Kconfig
@@ -0,0 +1 @@
+source "drivers/ddr/altera/Kconfig"
diff --git a/drivers/ddr/altera/Kconfig b/drivers/ddr/altera/Kconfig
new file mode 100644
index 00000000000..021ec1d8577
--- /dev/null
+++ b/drivers/ddr/altera/Kconfig
@@ -0,0 +1,5 @@
+config ALTERA_SDRAM
+ bool "SoCFPGA DDR SDRAM driver"
+ depends on TARGET_SOCFPGA_GEN5
+ help
+ Enable DDR SDRAM controller for the SoCFPGA devices.
diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile
index 1ca705856d2..bdd28722a98 100644
--- a/drivers/ddr/altera/Makefile
+++ b/drivers/ddr/altera/Makefile
@@ -8,4 +8,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_ALTERA_SDRAM) += sdram.o sequencer.o
+ifdef CONFIG_ALTERA_SDRAM
+obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram.o sequencer.o
+endif
diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c
index 9aa3eecd34f..d0a7b3f1076 100644
--- a/drivers/ddr/fsl/main.c
+++ b/drivers/ddr/fsl/main.c
@@ -786,7 +786,7 @@ phys_size_t __fsl_ddr_sdram(fsl_ddr_info_t *pinfo)
print_size(total_memory, " of memory\n");
printf(" This U-Boot only supports < 4G of DDR\n");
printf(" You could rebuild it with CONFIG_PHYS_64BIT\n");
- printf(" "); /* re-align to match init_func_ram print */
+ printf(" "); /* re-align to match init_dram print */
total_memory = CONFIG_MAX_MEM_MAPPED;
}
#endif
@@ -796,7 +796,7 @@ phys_size_t __fsl_ddr_sdram(fsl_ddr_info_t *pinfo)
/*
* fsl_ddr_sdram(void) -- this is the main function to be
- * called by initdram() in the board file.
+ * called by dram_init() in the board file.
*
* It returns amount of memory configured in bytes.
*/
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index dc4108f378f..c95e9acd5f7 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -28,6 +28,19 @@ config DWAPB_GPIO
help
Support for the Designware APB GPIO driver.
+config AT91_GPIO
+ bool "AT91 PIO GPIO driver"
+ depends on DM_GPIO
+ default n
+ help
+ Say yes here to select AT91 PIO GPIO driver. AT91 PIO
+ controller manages up to 32 fully programmable input/output
+ lines. Each I/O line may be dedicated as a general-purpose
+ I/O or be assigned to a function of an embedded peripheral.
+ The assignment to a function of an embedded peripheral is
+ the responsibility of AT91 Pinctrl driver. This driver is
+ responsible for the general-purpose I/O.
+
config ATMEL_PIO4
bool "ATMEL PIO4 driver"
depends on DM_GPIO
diff --git a/drivers/gpio/at91_gpio.c b/drivers/gpio/at91_gpio.c
index 8e52e3dad0a..98dbd8210eb 100644
--- a/drivers/gpio/at91_gpio.c
+++ b/drivers/gpio/at91_gpio.c
@@ -10,6 +10,7 @@
#include <config.h>
#include <common.h>
+#include <clk.h>
#include <dm.h>
#include <asm/io.h>
#include <linux/sizes.h>
@@ -59,11 +60,6 @@ int at91_set_pio_pullup(unsigned port, unsigned pin, int use_pullup)
{
struct at91_port *at91_port = at91_pio_get_port(port);
-#if defined(CPU_HAS_PIO3)
- if (use_pullup)
- at91_set_pio_pulldown(port, pin, 0);
-#endif
-
if (at91_port && (pin < GPIO_PER_BANK))
at91_set_port_pullup(at91_port, pin, use_pullup);
@@ -100,14 +96,7 @@ int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup)
mask = 1 << pin;
writel(mask, &at91_port->idr);
at91_set_pio_pullup(port, pin, use_pullup);
-#if defined(CPU_HAS_PIO3)
- writel(readl(&at91_port->abcdsr1) & ~mask,
- &at91_port->abcdsr1);
- writel(readl(&at91_port->abcdsr2) & ~mask,
- &at91_port->abcdsr2);
-#else
- writel(mask, &at91_port->asr);
-#endif
+ writel(mask, &at91_port->mux.pio2.asr);
writel(mask, &at91_port->pdr);
}
@@ -126,25 +115,62 @@ int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup)
mask = 1 << pin;
writel(mask, &at91_port->idr);
at91_set_pio_pullup(port, pin, use_pullup);
-#if defined(CPU_HAS_PIO3)
- writel(readl(&at91_port->abcdsr1) | mask,
- &at91_port->abcdsr1);
- writel(readl(&at91_port->abcdsr2) & ~mask,
- &at91_port->abcdsr2);
-#else
- writel(mask, &at91_port->bsr);
-#endif
+ writel(mask, &at91_port->mux.pio2.bsr);
writel(mask, &at91_port->pdr);
}
return 0;
}
-#if defined(CPU_HAS_PIO3)
+/*
+ * mux the pin to the "A" internal peripheral role.
+ */
+int at91_pio3_set_a_periph(unsigned port, unsigned pin, int use_pullup)
+{
+ struct at91_port *at91_port = at91_pio_get_port(port);
+ u32 mask;
+
+ if (at91_port && (pin < GPIO_PER_BANK)) {
+ mask = 1 << pin;
+ writel(mask, &at91_port->idr);
+ at91_set_pio_pullup(port, pin, use_pullup);
+ writel(readl(&at91_port->mux.pio3.abcdsr1) & ~mask,
+ &at91_port->mux.pio3.abcdsr1);
+ writel(readl(&at91_port->mux.pio3.abcdsr2) & ~mask,
+ &at91_port->mux.pio3.abcdsr2);
+
+ writel(mask, &at91_port->pdr);
+ }
+
+ return 0;
+}
+
+/*
+ * mux the pin to the "B" internal peripheral role.
+ */
+int at91_pio3_set_b_periph(unsigned port, unsigned pin, int use_pullup)
+{
+ struct at91_port *at91_port = at91_pio_get_port(port);
+ u32 mask;
+
+ if (at91_port && (pin < GPIO_PER_BANK)) {
+ mask = 1 << pin;
+ writel(mask, &at91_port->idr);
+ at91_set_pio_pullup(port, pin, use_pullup);
+ writel(readl(&at91_port->mux.pio3.abcdsr1) | mask,
+ &at91_port->mux.pio3.abcdsr1);
+ writel(readl(&at91_port->mux.pio3.abcdsr2) & ~mask,
+ &at91_port->mux.pio3.abcdsr2);
+
+ writel(mask, &at91_port->pdr);
+ }
+
+ return 0;
+}
/*
* mux the pin to the "C" internal peripheral role.
*/
-int at91_set_c_periph(unsigned port, unsigned pin, int use_pullup)
+int at91_pio3_set_c_periph(unsigned port, unsigned pin, int use_pullup)
{
struct at91_port *at91_port = at91_pio_get_port(port);
u32 mask;
@@ -153,10 +179,10 @@ int at91_set_c_periph(unsigned port, unsigned pin, int use_pullup)
mask = 1 << pin;
writel(mask, &at91_port->idr);
at91_set_pio_pullup(port, pin, use_pullup);
- writel(readl(&at91_port->abcdsr1) & ~mask,
- &at91_port->abcdsr1);
- writel(readl(&at91_port->abcdsr2) | mask,
- &at91_port->abcdsr2);
+ writel(readl(&at91_port->mux.pio3.abcdsr1) & ~mask,
+ &at91_port->mux.pio3.abcdsr1);
+ writel(readl(&at91_port->mux.pio3.abcdsr2) | mask,
+ &at91_port->mux.pio3.abcdsr2);
writel(mask, &at91_port->pdr);
}
@@ -166,7 +192,7 @@ int at91_set_c_periph(unsigned port, unsigned pin, int use_pullup)
/*
* mux the pin to the "D" internal peripheral role.
*/
-int at91_set_d_periph(unsigned port, unsigned pin, int use_pullup)
+int at91_pio3_set_d_periph(unsigned port, unsigned pin, int use_pullup)
{
struct at91_port *at91_port = at91_pio_get_port(port);
u32 mask;
@@ -175,16 +201,15 @@ int at91_set_d_periph(unsigned port, unsigned pin, int use_pullup)
mask = 1 << pin;
writel(mask, &at91_port->idr);
at91_set_pio_pullup(port, pin, use_pullup);
- writel(readl(&at91_port->abcdsr1) | mask,
- &at91_port->abcdsr1);
- writel(readl(&at91_port->abcdsr2) | mask,
- &at91_port->abcdsr2);
+ writel(readl(&at91_port->mux.pio3.abcdsr1) | mask,
+ &at91_port->mux.pio3.abcdsr1);
+ writel(readl(&at91_port->mux.pio3.abcdsr2) | mask,
+ &at91_port->mux.pio3.abcdsr2);
writel(mask, &at91_port->pdr);
}
return 0;
}
-#endif
#ifdef CONFIG_DM_GPIO
static bool at91_get_port_output(struct at91_port *at91_port, int offset)
@@ -263,10 +288,27 @@ int at91_set_pio_deglitch(unsigned port, unsigned pin, int is_on)
if (at91_port && (pin < GPIO_PER_BANK)) {
mask = 1 << pin;
+ if (is_on)
+ writel(mask, &at91_port->ifer);
+ else
+ writel(mask, &at91_port->ifdr);
+ }
+
+ return 0;
+}
+
+/*
+ * enable/disable the glitch filter. mostly used with IRQ handling.
+ */
+int at91_pio3_set_pio_deglitch(unsigned port, unsigned pin, int is_on)
+{
+ struct at91_port *at91_port = at91_pio_get_port(port);
+ u32 mask;
+
+ if (at91_port && (pin < GPIO_PER_BANK)) {
+ mask = 1 << pin;
if (is_on) {
-#if defined(CPU_HAS_PIO3)
- writel(mask, &at91_port->ifscdr);
-#endif
+ writel(mask, &at91_port->mux.pio3.ifscdr);
writel(mask, &at91_port->ifer);
} else {
writel(mask, &at91_port->ifdr);
@@ -276,11 +318,10 @@ int at91_set_pio_deglitch(unsigned port, unsigned pin, int is_on)
return 0;
}
-#if defined(CPU_HAS_PIO3)
/*
* enable/disable the debounce filter.
*/
-int at91_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div)
+int at91_pio3_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div)
{
struct at91_port *at91_port = at91_pio_get_port(port);
u32 mask;
@@ -288,8 +329,8 @@ int at91_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div)
if (at91_port && (pin < GPIO_PER_BANK)) {
mask = 1 << pin;
if (is_on) {
- writel(mask, &at91_port->ifscer);
- writel(div & PIO_SCDR_DIV, &at91_port->scdr);
+ writel(mask, &at91_port->mux.pio3.ifscer);
+ writel(div & PIO_SCDR_DIV, &at91_port->mux.pio3.scdr);
writel(mask, &at91_port->ifer);
} else {
writel(mask, &at91_port->ifdr);
@@ -303,7 +344,7 @@ int at91_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div)
* enable/disable the pull-down.
* If pull-up already enabled while calling the function, we disable it.
*/
-int at91_set_pio_pulldown(unsigned port, unsigned pin, int is_on)
+int at91_pio3_set_pio_pulldown(unsigned port, unsigned pin, int is_on)
{
struct at91_port *at91_port = at91_pio_get_port(port);
u32 mask;
@@ -312,18 +353,31 @@ int at91_set_pio_pulldown(unsigned port, unsigned pin, int is_on)
mask = 1 << pin;
if (is_on) {
at91_set_pio_pullup(port, pin, 0);
- writel(mask, &at91_port->ppder);
+ writel(mask, &at91_port->mux.pio3.ppder);
} else
- writel(mask, &at91_port->ppddr);
+ writel(mask, &at91_port->mux.pio3.ppddr);
}
return 0;
}
+int at91_pio3_set_pio_pullup(unsigned port, unsigned pin, int use_pullup)
+{
+ struct at91_port *at91_port = at91_pio_get_port(port);
+
+ if (use_pullup)
+ at91_pio3_set_pio_pulldown(port, pin, 0);
+
+ if (at91_port && (pin < GPIO_PER_BANK))
+ at91_set_port_pullup(at91_port, pin, use_pullup);
+
+ return 0;
+}
+
/*
* disable Schmitt trigger
*/
-int at91_set_pio_disable_schmitt_trig(unsigned port, unsigned pin)
+int at91_pio3_set_pio_disable_schmitt_trig(unsigned port, unsigned pin)
{
struct at91_port *at91_port = at91_pio_get_port(port);
u32 mask;
@@ -336,7 +390,6 @@ int at91_set_pio_disable_schmitt_trig(unsigned port, unsigned pin)
return 0;
}
-#endif
/*
* enable/disable the multi-driver. This is only valid for output and
@@ -517,17 +570,44 @@ static int at91_gpio_probe(struct udevice *dev)
struct at91_port_priv *port = dev_get_priv(dev);
struct at91_port_platdata *plat = dev_get_platdata(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct clk clk;
+ int ret;
+
+ ret = clk_get_by_index(dev, 0, &clk);
+ if (ret)
+ return ret;
+
+ ret = clk_enable(&clk);
+ if (ret)
+ return ret;
+
+ clk_free(&clk);
uc_priv->bank_name = plat->bank_name;
uc_priv->gpio_count = GPIO_PER_BANK;
+
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+ plat->base_addr = (uint32_t)dev_get_addr_ptr(dev);
+#endif
port->regs = (struct at91_port *)plat->base_addr;
return 0;
}
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+static const struct udevice_id at91_gpio_ids[] = {
+ { .compatible = "atmel,at91rm9200-gpio" },
+ { }
+};
+#endif
+
U_BOOT_DRIVER(gpio_at91) = {
.name = "gpio_at91",
.id = UCLASS_GPIO,
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+ .of_match = at91_gpio_ids,
+ .platdata_auto_alloc_size = sizeof(struct at91_port_platdata),
+#endif
.ops = &gpio_at91_ops,
.probe = at91_gpio_probe,
.priv_auto_alloc_size = sizeof(struct at91_port_priv),
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 560391fae24..6ac26dd137c 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -105,6 +105,12 @@ config MMC_DW_SOCFPGA
Synopsys DesignWare Memory Card Interface driver. Select this option
for platforms based on Altera SOCFPGA.
+config MMC_MESON_GX
+ bool "Meson GX EMMC controller support"
+ depends on DM_MMC && BLK && DM_MMC_OPS && ARCH_MESON
+ help
+ Support for EMMC host controller on Meson GX ARM SoCs platform (S905)
+
config MMC_MXC
bool "Freescale i.MX21/27/31 or MPC512x Multimedia Card support"
help
@@ -365,6 +371,15 @@ config MMC_SUNXI
This selects support for the SD/MMC Host Controller on
Allwinner sunxi SoCs.
+config GENERIC_ATMEL_MCI
+ bool "Atmel Multimedia Card Interface support"
+ depends on DM_MMC && BLK && DM_MMC_OPS && ARCH_AT91
+ help
+ This enables support for Atmel High Speed Multimedia Card Interface
+ (HSMCI), which supports the MultiMedia Card (MMC) Specification V4.3,
+ the SD Memory Card Specification V2.0, the SDIO V2.0 specification
+ and CE-ATA V1.1.
+
endif
config TEGRA124_MMC_DISABLE_EXT_LOOPBACK
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 6a26a52c282..a61a9e9ca6c 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -29,6 +29,7 @@ ifdef CONFIG_SUPPORT_EMMC_BOOT
obj-$(CONFIG_GENERIC_MMC) += mmc_boot.o
endif
obj-$(CONFIG_GENERIC_ATMEL_MCI) += gen_atmel_mci.o
+obj-$(CONFIG_MMC_MESON_GX) += meson_gx_mmc.o
obj-$(CONFIG_MMC_SPI) += mmc_spi.o
obj-$(CONFIG_MVEBU_MMC) += mvebu_mmc.o
obj-$(CONFIG_MMC_OMAP_HS) += omap_hsmmc.o
diff --git a/drivers/mmc/bcm2835_sdhci.c b/drivers/mmc/bcm2835_sdhci.c
index 29c2a85812f..20079bce48b 100644
--- a/drivers/mmc/bcm2835_sdhci.c
+++ b/drivers/mmc/bcm2835_sdhci.c
@@ -44,6 +44,7 @@
/* 400KHz is max freq for card ID etc. Use that as min */
#define MIN_FREQ 400000
+#define SDHCI_BUFFER 0x20
struct bcm2835_sdhci_host {
struct sdhci_host host;
@@ -69,8 +70,11 @@ static inline void bcm2835_sdhci_raw_writel(struct sdhci_host *host, u32 val,
* (Which is just as well - otherwise we'd have to nobble the DMA engine
* too)
*/
- while (timer_get_us() - bcm_host->last_write < bcm_host->twoticks_delay)
- ;
+ if (reg != SDHCI_BUFFER) {
+ while (timer_get_us() - bcm_host->last_write <
+ bcm_host->twoticks_delay)
+ ;
+ }
writel(val, host->ioaddr + reg);
bcm_host->last_write = timer_get_us();
diff --git a/drivers/mmc/gen_atmel_mci.c b/drivers/mmc/gen_atmel_mci.c
index 7dc4a5de74e..c25d9ed96ed 100644
--- a/drivers/mmc/gen_atmel_mci.c
+++ b/drivers/mmc/gen_atmel_mci.c
@@ -10,6 +10,7 @@
*/
#include <common.h>
+#include <clk.h>
#include <mmc.h>
#include <part.h>
#include <malloc.h>
@@ -18,8 +19,11 @@
#include <asm/byteorder.h>
#include <asm/arch/clk.h>
#include <asm/arch/hardware.h>
+#include <dm/device.h>
#include "atmel_mci.h"
+DECLARE_GLOBAL_DATA_PTR;
+
#ifndef CONFIG_SYS_MMC_CLK_OD
# define CONFIG_SYS_MMC_CLK_OD 150000
#endif
@@ -37,6 +41,10 @@ struct atmel_mci_priv {
struct atmel_mci *mci;
unsigned int initialized:1;
unsigned int curr_clk;
+#ifdef CONFIG_DM_MMC
+ struct mmc mmc;
+ ulong bus_clk_rate;
+#endif
};
/* Read Atmel MCI IP version */
@@ -58,11 +66,19 @@ static void dump_cmd(u32 cmdr, u32 arg, u32 status, const char* msg)
}
/* Setup for MCI Clock and Block Size */
+#ifdef CONFIG_DM_MMC
+static void mci_set_mode(struct atmel_mci_priv *priv, u32 hz, u32 blklen)
+{
+ struct mmc *mmc = &priv->mmc;
+ u32 bus_hz = priv->bus_clk_rate;
+#else
static void mci_set_mode(struct mmc *mmc, u32 hz, u32 blklen)
{
struct atmel_mci_priv *priv = mmc->priv;
- atmel_mci_t *mci = priv->mci;
u32 bus_hz = get_mci_clk_rate();
+#endif
+
+ atmel_mci_t *mci = priv->mci;
u32 clkdiv = 255;
unsigned int version = atmel_mci_get_version(mci);
u32 clkodd = 0;
@@ -202,10 +218,18 @@ io_fail:
* Sends a command out on the bus and deals with the block data.
* Takes the mmc pointer, a command pointer, and an optional data pointer.
*/
+#ifdef CONFIG_DM_MMC
+static int atmel_mci_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
+ struct mmc_data *data)
+{
+ struct atmel_mci_priv *priv = dev_get_priv(dev);
+ struct mmc *mmc = mmc_get_mmc_dev(dev);
+#else
static int
mci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
{
struct atmel_mci_priv *priv = mmc->priv;
+#endif
atmel_mci_t *mci = priv->mci;
u32 cmdr;
u32 error_flags = 0;
@@ -335,17 +359,28 @@ mci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
return 0;
}
+#ifdef CONFIG_DM_MMC
+static int atmel_mci_set_ios(struct udevice *dev)
+{
+ struct atmel_mci_priv *priv = dev_get_priv(dev);
+ struct mmc *mmc = mmc_get_mmc_dev(dev);
+#else
/* Entered into mmc structure during driver init */
static int mci_set_ios(struct mmc *mmc)
{
struct atmel_mci_priv *priv = mmc->priv;
+#endif
atmel_mci_t *mci = priv->mci;
int bus_width = mmc->bus_width;
unsigned int version = atmel_mci_get_version(mci);
int busw;
/* Set the clock speed */
+#ifdef CONFIG_DM_MMC
+ mci_set_mode(priv, mmc->clock, MMC_DEFAULT_BLKLEN);
+#else
mci_set_mode(mmc, mmc->clock, MMC_DEFAULT_BLKLEN);
+#endif
/*
* set the bus width and select slot for this interface
@@ -374,10 +409,15 @@ static int mci_set_ios(struct mmc *mmc)
return 0;
}
+#ifdef CONFIG_DM_MMC
+static int atmel_mci_hw_init(struct atmel_mci_priv *priv)
+{
+#else
/* Entered into mmc structure during driver init */
static int mci_init(struct mmc *mmc)
{
struct atmel_mci_priv *priv = mmc->priv;
+#endif
atmel_mci_t *mci = priv->mci;
/* Initialize controller */
@@ -392,11 +432,16 @@ static int mci_init(struct mmc *mmc)
writel(~0UL, &mci->idr);
/* Set default clocks and blocklen */
+#ifdef CONFIG_DM_MMC
+ mci_set_mode(priv, CONFIG_SYS_MMC_CLK_OD, MMC_DEFAULT_BLKLEN);
+#else
mci_set_mode(mmc, CONFIG_SYS_MMC_CLK_OD, MMC_DEFAULT_BLKLEN);
+#endif
return 0;
}
+#ifndef CONFIG_DM_MMC
static const struct mmc_ops atmel_mci_ops = {
.send_cmd = mci_send_cmd,
.set_ios = mci_set_ios,
@@ -456,3 +501,114 @@ int atmel_mci_init(void *regs)
return 0;
}
+#endif
+
+#ifdef CONFIG_DM_MMC
+static const struct dm_mmc_ops atmel_mci_mmc_ops = {
+ .send_cmd = atmel_mci_send_cmd,
+ .set_ios = atmel_mci_set_ios,
+};
+
+static void atmel_mci_setup_cfg(struct atmel_mci_priv *priv)
+{
+ struct mmc_config *cfg;
+ u32 version;
+
+ cfg = &priv->cfg;
+ cfg->name = "Atmel mci";
+ cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
+
+ /*
+ * If the version is above 3.0, the capabilities of the 8-bit
+ * bus width and high speed are supported.
+ */
+ version = atmel_mci_get_version(priv->mci);
+ if ((version & 0xf00) >= 0x300) {
+ cfg->host_caps = MMC_MODE_8BIT |
+ MMC_MODE_HS | MMC_MODE_HS_52MHz;
+ }
+
+ cfg->host_caps |= MMC_MODE_4BIT;
+ cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
+ cfg->f_min = priv->bus_clk_rate / (2 * 256);
+ cfg->f_max = priv->bus_clk_rate / 2;
+}
+
+static int atmel_mci_enable_clk(struct udevice *dev)
+{
+ struct atmel_mci_priv *priv = dev_get_priv(dev);
+ struct clk clk;
+ ulong clk_rate;
+ int ret = 0;
+
+ ret = clk_get_by_index(dev, 0, &clk);
+ if (ret) {
+ ret = -EINVAL;
+ goto failed;
+ }
+
+ ret = clk_enable(&clk);
+ if (ret)
+ goto failed;
+
+ clk_rate = clk_get_rate(&clk);
+ if (!clk_rate) {
+ ret = -EINVAL;
+ goto failed;
+ }
+
+ priv->bus_clk_rate = clk_rate;
+
+failed:
+ clk_free(&clk);
+
+ return ret;
+}
+
+static int atmel_mci_probe(struct udevice *dev)
+{
+ struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+ struct atmel_mci_priv *priv = dev_get_priv(dev);
+ struct mmc *mmc;
+ int ret;
+
+ ret = atmel_mci_enable_clk(dev);
+ if (ret)
+ return ret;
+
+ priv->mci = (struct atmel_mci *)dev_get_addr_ptr(dev);
+
+ atmel_mci_setup_cfg(priv);
+
+ mmc = &priv->mmc;
+ mmc->cfg = &priv->cfg;
+ mmc->dev = dev;
+ upriv->mmc = mmc;
+
+ atmel_mci_hw_init(priv);
+
+ return 0;
+}
+
+static int atmel_mci_bind(struct udevice *dev)
+{
+ struct atmel_mci_priv *priv = dev_get_priv(dev);
+
+ return mmc_bind(dev, &priv->mmc, &priv->cfg);
+}
+
+static const struct udevice_id atmel_mci_ids[] = {
+ { .compatible = "atmel,hsmci" },
+ { }
+};
+
+U_BOOT_DRIVER(atmel_mci) = {
+ .name = "atmel-mci",
+ .id = UCLASS_MMC,
+ .of_match = atmel_mci_ids,
+ .bind = atmel_mci_bind,
+ .probe = atmel_mci_probe,
+ .priv_auto_alloc_size = sizeof(struct atmel_mci_priv),
+ .ops = &atmel_mci_mmc_ops,
+};
+#endif
diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
new file mode 100644
index 00000000000..8e28ab70f5e
--- /dev/null
+++ b/drivers/mmc/meson_gx_mmc.c
@@ -0,0 +1,291 @@
+/*
+ * (C) Copyright 2016 Carlo Caione <carlo@caione.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <asm/io.h>
+#include <asm/arch/sd_emmc.h>
+#include <dm/device.h>
+#include <linux/log2.h>
+
+static inline void *get_regbase(const struct mmc *mmc)
+{
+ struct meson_mmc_platdata *pdata = mmc->priv;
+
+ return pdata->regbase;
+}
+
+static inline uint32_t meson_read(struct mmc *mmc, int offset)
+{
+ return readl(get_regbase(mmc) + offset);
+}
+
+static inline void meson_write(struct mmc *mmc, uint32_t val, int offset)
+{
+ writel(val, get_regbase(mmc) + offset);
+}
+
+static void meson_mmc_config_clock(struct mmc *mmc)
+{
+ uint32_t meson_mmc_clk = 0;
+ unsigned int clk, clk_src, clk_div;
+
+ /* 1GHz / CLK_MAX_DIV = 15,9 MHz */
+ if (mmc->clock > 16000000) {
+ clk = SD_EMMC_CLKSRC_DIV2;
+ clk_src = CLK_SRC_DIV2;
+ } else {
+ clk = SD_EMMC_CLKSRC_24M;
+ clk_src = CLK_SRC_24M;
+ }
+ clk_div = DIV_ROUND_UP(clk, mmc->clock);
+
+ /* 180 phase core clock */
+ meson_mmc_clk |= CLK_CO_PHASE_180;
+
+ /* 180 phase tx clock */
+ meson_mmc_clk |= CLK_TX_PHASE_000;
+
+ /* clock settings */
+ meson_mmc_clk |= clk_src;
+ meson_mmc_clk |= clk_div;
+
+ meson_write(mmc, meson_mmc_clk, MESON_SD_EMMC_CLOCK);
+}
+
+static int meson_dm_mmc_set_ios(struct udevice *dev)
+{
+ struct mmc *mmc = mmc_get_mmc_dev(dev);
+ uint32_t meson_mmc_cfg;
+
+ meson_mmc_config_clock(mmc);
+
+ meson_mmc_cfg = meson_read(mmc, MESON_SD_EMMC_CFG);
+
+ meson_mmc_cfg &= ~CFG_BUS_WIDTH_MASK;
+ if (mmc->bus_width == 1)
+ meson_mmc_cfg |= CFG_BUS_WIDTH_1;
+ else if (mmc->bus_width == 4)
+ meson_mmc_cfg |= CFG_BUS_WIDTH_4;
+ else if (mmc->bus_width == 8)
+ meson_mmc_cfg |= CFG_BUS_WIDTH_8;
+ else
+ return -EINVAL;
+
+ /* 512 bytes block length */
+ meson_mmc_cfg &= ~CFG_BL_LEN_MASK;
+ meson_mmc_cfg |= CFG_BL_LEN_512;
+
+ /* Response timeout 256 clk */
+ meson_mmc_cfg &= ~CFG_RESP_TIMEOUT_MASK;
+ meson_mmc_cfg |= CFG_RESP_TIMEOUT_256;
+
+ /* Command-command gap 16 clk */
+ meson_mmc_cfg &= ~CFG_RC_CC_MASK;
+ meson_mmc_cfg |= CFG_RC_CC_16;
+
+ meson_write(mmc, meson_mmc_cfg, MESON_SD_EMMC_CFG);
+
+ return 0;
+}
+
+static void meson_mmc_setup_cmd(struct mmc *mmc, struct mmc_data *data,
+ struct mmc_cmd *cmd)
+{
+ uint32_t meson_mmc_cmd = 0, cfg;
+
+ meson_mmc_cmd |= cmd->cmdidx << CMD_CFG_CMD_INDEX_SHIFT;
+
+ if (cmd->resp_type & MMC_RSP_PRESENT) {
+ if (cmd->resp_type & MMC_RSP_136)
+ meson_mmc_cmd |= CMD_CFG_RESP_128;
+
+ if (cmd->resp_type & MMC_RSP_BUSY)
+ meson_mmc_cmd |= CMD_CFG_R1B;
+
+ if (!(cmd->resp_type & MMC_RSP_CRC))
+ meson_mmc_cmd |= CMD_CFG_RESP_NOCRC;
+ } else {
+ meson_mmc_cmd |= CMD_CFG_NO_RESP;
+ }
+
+ if (data) {
+ cfg = meson_read(mmc, MESON_SD_EMMC_CFG);
+ cfg &= ~CFG_BL_LEN_MASK;
+ cfg |= ilog2(data->blocksize) << CFG_BL_LEN_SHIFT;
+ meson_write(mmc, cfg, MESON_SD_EMMC_CFG);
+
+ if (data->flags == MMC_DATA_WRITE)
+ meson_mmc_cmd |= CMD_CFG_DATA_WR;
+
+ meson_mmc_cmd |= CMD_CFG_DATA_IO | CMD_CFG_BLOCK_MODE |
+ data->blocks;
+ }
+
+ meson_mmc_cmd |= CMD_CFG_TIMEOUT_4S | CMD_CFG_OWNER |
+ CMD_CFG_END_OF_CHAIN;
+
+ meson_write(mmc, meson_mmc_cmd, MESON_SD_EMMC_CMD_CFG);
+}
+
+static void meson_mmc_setup_addr(struct mmc *mmc, struct mmc_data *data)
+{
+ struct meson_mmc_platdata *pdata = mmc->priv;
+ unsigned int data_size;
+ uint32_t data_addr = 0;
+
+ if (data) {
+ data_size = data->blocks * data->blocksize;
+
+ if (data->flags == MMC_DATA_READ) {
+ data_addr = (ulong) data->dest;
+ invalidate_dcache_range(data_addr,
+ data_addr + data_size);
+ } else {
+ pdata->w_buf = calloc(data_size, sizeof(char));
+ data_addr = (ulong) pdata->w_buf;
+ memcpy(pdata->w_buf, data->src, data_size);
+ flush_dcache_range(data_addr, data_addr + data_size);
+ }
+ }
+
+ meson_write(mmc, data_addr, MESON_SD_EMMC_CMD_DAT);
+}
+
+static void meson_mmc_read_response(struct mmc *mmc, struct mmc_cmd *cmd)
+{
+ if (cmd->resp_type & MMC_RSP_136) {
+ cmd->response[0] = meson_read(mmc, MESON_SD_EMMC_CMD_RSP3);
+ cmd->response[1] = meson_read(mmc, MESON_SD_EMMC_CMD_RSP2);
+ cmd->response[2] = meson_read(mmc, MESON_SD_EMMC_CMD_RSP1);
+ cmd->response[3] = meson_read(mmc, MESON_SD_EMMC_CMD_RSP);
+ } else {
+ cmd->response[0] = meson_read(mmc, MESON_SD_EMMC_CMD_RSP);
+ }
+}
+
+static int meson_dm_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
+ struct mmc_data *data)
+{
+ struct mmc *mmc = mmc_get_mmc_dev(dev);
+ struct meson_mmc_platdata *pdata = mmc->priv;
+ uint32_t status;
+ ulong start;
+ int ret = 0;
+
+ /* max block size supported by chip is 512 byte */
+ if (data && data->blocksize > 512)
+ return -EINVAL;
+
+ meson_mmc_setup_cmd(mmc, data, cmd);
+ meson_mmc_setup_addr(mmc, data);
+
+ meson_write(mmc, cmd->cmdarg, MESON_SD_EMMC_CMD_ARG);
+
+ /* use 10s timeout */
+ start = get_timer(0);
+ do {
+ status = meson_read(mmc, MESON_SD_EMMC_STATUS);
+ } while(!(status & STATUS_END_OF_CHAIN) && get_timer(start) < 10000);
+
+ if (!(status & STATUS_END_OF_CHAIN))
+ ret = -ETIMEDOUT;
+ else if (status & STATUS_RESP_TIMEOUT)
+ ret = -ETIMEDOUT;
+ else if (status & STATUS_ERR_MASK)
+ ret = -EIO;
+
+ meson_mmc_read_response(mmc, cmd);
+
+ if (data && data->flags == MMC_DATA_WRITE)
+ free(pdata->w_buf);
+
+ /* reset status bits */
+ meson_write(mmc, STATUS_MASK, MESON_SD_EMMC_STATUS);
+
+ return ret;
+}
+
+static const struct dm_mmc_ops meson_dm_mmc_ops = {
+ .send_cmd = meson_dm_mmc_send_cmd,
+ .set_ios = meson_dm_mmc_set_ios,
+};
+
+static int meson_mmc_ofdata_to_platdata(struct udevice *dev)
+{
+ struct meson_mmc_platdata *pdata = dev_get_platdata(dev);
+ fdt_addr_t addr;
+
+ addr = dev_get_addr(dev);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ pdata->regbase = (void *)addr;
+
+ return 0;
+}
+
+static int meson_mmc_probe(struct udevice *dev)
+{
+ struct meson_mmc_platdata *pdata = dev_get_platdata(dev);
+ struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+ struct mmc *mmc = &pdata->mmc;
+ struct mmc_config *cfg = &pdata->cfg;
+ uint32_t val;
+
+ cfg->voltages = MMC_VDD_33_34 | MMC_VDD_32_33 |
+ MMC_VDD_31_32 | MMC_VDD_165_195;
+ cfg->host_caps = MMC_MODE_8BIT | MMC_MODE_4BIT |
+ MMC_MODE_HS_52MHz | MMC_MODE_HS;
+ cfg->f_min = DIV_ROUND_UP(SD_EMMC_CLKSRC_24M, CLK_MAX_DIV);
+ cfg->f_max = 100000000; /* 100 MHz */
+ cfg->b_max = 256; /* max 256 blocks */
+ cfg->name = dev->name;
+
+ mmc->priv = pdata;
+ upriv->mmc = mmc;
+
+ mmc_set_clock(mmc, cfg->f_min);
+
+ /* reset all status bits */
+ meson_write(mmc, STATUS_MASK, MESON_SD_EMMC_STATUS);
+
+ /* disable interrupts */
+ meson_write(mmc, 0, MESON_SD_EMMC_IRQ_EN);
+
+ /* enable auto clock mode */
+ val = meson_read(mmc, MESON_SD_EMMC_CFG);
+ val &= ~CFG_SDCLK_ALWAYS_ON;
+ val |= CFG_AUTO_CLK;
+ meson_write(mmc, val, MESON_SD_EMMC_CFG);
+
+ return 0;
+}
+
+int meson_mmc_bind(struct udevice *dev)
+{
+ struct meson_mmc_platdata *pdata = dev_get_platdata(dev);
+
+ return mmc_bind(dev, &pdata->mmc, &pdata->cfg);
+}
+
+static const struct udevice_id meson_mmc_match[] = {
+ { .compatible = "amlogic,meson-gx-mmc" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(meson_mmc) = {
+ .name = "meson_gx_mmc",
+ .id = UCLASS_MMC,
+ .of_match = meson_mmc_match,
+ .ops = &meson_dm_mmc_ops,
+ .probe = meson_mmc_probe,
+ .bind = meson_mmc_bind,
+ .ofdata_to_platdata = meson_mmc_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct meson_mmc_platdata),
+};
diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index c94d58db65c..b745977b3fb 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -72,6 +72,7 @@ static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data,
unsigned int start_addr)
{
unsigned int stat, rdy, mask, timeout, block = 0;
+ bool transfer_done = false;
#ifdef CONFIG_MMC_SDHCI_SDMA
unsigned char ctrl;
ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
@@ -89,17 +90,23 @@ static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data,
__func__, stat);
return -EIO;
}
- if (stat & rdy) {
+ if (!transfer_done && (stat & rdy)) {
if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
continue;
sdhci_writel(host, rdy, SDHCI_INT_STATUS);
sdhci_transfer_pio(host, data);
data->dest += data->blocksize;
- if (++block >= data->blocks)
- break;
+ if (++block >= data->blocks) {
+ /* Keep looping until the SDHCI_INT_DATA_END is
+ * cleared, even if we finished sending all the
+ * blocks.
+ */
+ transfer_done = true;
+ continue;
+ }
}
#ifdef CONFIG_MMC_SDHCI_SDMA
- if (stat & SDHCI_INT_DMA_END) {
+ if (!transfer_done && (stat & SDHCI_INT_DMA_END)) {
sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index 8669432debb..21d5d0e70d0 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -1222,7 +1222,8 @@ static void at91_nand_hwcontrol(struct mtd_info *mtd,
IO_ADDR_W |= CONFIG_SYS_NAND_MASK_ALE;
#ifdef CONFIG_SYS_NAND_ENABLE_PIN
- gpio_set_value(CONFIG_SYS_NAND_ENABLE_PIN, !(ctrl & NAND_NCE));
+ at91_set_gpio_value(CONFIG_SYS_NAND_ENABLE_PIN,
+ !(ctrl & NAND_NCE));
#endif
this->IO_ADDR_W = (void *) IO_ADDR_W;
}
@@ -1234,7 +1235,7 @@ static void at91_nand_hwcontrol(struct mtd_info *mtd,
#ifdef CONFIG_SYS_NAND_READY_PIN
static int at91_nand_ready(struct mtd_info *mtd)
{
- return gpio_get_value(CONFIG_SYS_NAND_READY_PIN);
+ return at91_get_gpio_value(CONFIG_SYS_NAND_READY_PIN);
}
#endif
diff --git a/drivers/net/at91_emac.c b/drivers/net/at91_emac.c
index be3d82e67ea..eb8d2b31ecb 100644
--- a/drivers/net/at91_emac.c
+++ b/drivers/net/at91_emac.c
@@ -333,7 +333,7 @@ static int at91emac_init(struct eth_device *netdev, bd_t *bd)
ATMEL_PMX_AA_ETXEN | ATMEL_PMX_AA_EREFCK;
writel(value, &pio->pioa.pdr);
- writel(value, &pio->pioa.asr);
+ writel(value, &pio->pioa.mux.pio2.asr);
#ifdef CONFIG_RMII
value = ATMEL_PMX_BA_ERXCK;
@@ -344,7 +344,7 @@ static int at91emac_init(struct eth_device *netdev, bd_t *bd)
ATMEL_PMX_BA_ETX3 | ATMEL_PMX_BA_ETX2;
#endif
writel(value, &pio->piob.pdr);
- writel(value, &pio->piob.bsr);
+ writel(value, &pio->piob.mux.pio2.bsr);
at91_periph_clk_enable(ATMEL_ID_EMAC);
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index e562a8ac1a7..aca3990aebf 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -15,6 +15,19 @@ if PHYLIB
config MV88E61XX_SWITCH
bool "Marvel MV88E61xx Ethernet switch PHY support."
+if MV88E61XX_SWITCH
+
+config MV88E61XX_CPU_PORT
+ int "CPU Port"
+
+config MV88E61XX_PHY_PORTS
+ hex "Bitmask of PHY Ports"
+
+config MV88E61XX_FIXED_PORTS
+ hex "Bitmask of PHYless serdes Ports"
+
+endif # MV88E61XX_SWITCH
+
config PHYLIB_10G
bool "Generic 10G PHY support"
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 9d0f5016ca4..355aeae854d 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -150,6 +150,20 @@ config ROCKCHIP_RK3288_PINCTRL
definitions and pin control functions for each available multiplex
function.
+config PINCTRL_AT91
+ bool "AT91 pinctrl driver"
+ depends on DM
+ help
+ This option is to enable the AT91 pinctrl driver for AT91 PIO
+ controller. AT91 PIO controller is a combined gpio-controller,
+ pin-mux and pin-config module. Each I/O pin may be dedicated as
+ a general-purpose I/O or be assigned to a function of an embedded
+ peripheral. Each I/O pin has a glitch filter providing rejection of
+ glitches lower than one-half of peripheral clock cycle and
+ a debouncing filter providing rejection of unwanted pulses from key
+ or push button operations. You can also control the multi-driver
+ capability, pull-up and pull-down feature on each I/O pin.
+
config PINCTRL_AT91PIO4
bool "AT91 PIO4 pinctrl driver"
depends on DM
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 2ac9c19734e..bbb2480e865 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -5,6 +5,7 @@
obj-y += pinctrl-uclass.o
obj-$(CONFIG_$(SPL_)PINCTRL_GENERIC) += pinctrl-generic.o
+obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o
obj-$(CONFIG_PINCTRL_AT91PIO4) += pinctrl-at91-pio4.o
obj-y += nxp/
obj-$(CONFIG_ARCH_ATH79) += ath79/
diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
new file mode 100644
index 00000000000..904e1bdc681
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-at91.c
@@ -0,0 +1,453 @@
+/*
+ * Atmel PIO pinctrl driver
+ *
+ * Copyright (C) 2016 Atmel Corporation
+ * Wenyou.Yang <wenyou.yang@atmel.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm/device.h>
+#include <dm/pinctrl.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <mach/at91_pio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define MAX_GPIO_BANKS 5
+#define MAX_NB_GPIO_PER_BANK 32
+
+#define MAX_PINMUX_ENTRIES 200
+
+struct at91_pinctrl_priv {
+ struct at91_port *reg_base[MAX_GPIO_BANKS];
+ u32 nbanks;
+};
+
+#define PULL_UP BIT(0)
+#define MULTI_DRIVE BIT(1)
+#define DEGLITCH BIT(2)
+#define PULL_DOWN BIT(3)
+#define DIS_SCHMIT BIT(4)
+#define DRIVE_STRENGTH_SHIFT 5
+#define DRIVE_STRENGTH_MASK 0x3
+#define DRIVE_STRENGTH (DRIVE_STRENGTH_MASK << DRIVE_STRENGTH_SHIFT)
+#define OUTPUT BIT(7)
+#define OUTPUT_VAL_SHIFT 8
+#define OUTPUT_VAL (0x1 << OUTPUT_VAL_SHIFT)
+#define DEBOUNCE BIT(16)
+#define DEBOUNCE_VAL_SHIFT 17
+#define DEBOUNCE_VAL (0x3fff << DEBOUNCE_VAL_SHIFT)
+
+/**
+ * These defines will translated the dt binding settings to our internal
+ * settings. They are not necessarily the same value as the register setting.
+ * The actual drive strength current of low, medium and high must be looked up
+ * from the corresponding device datasheet. This value is different for pins
+ * that are even in the same banks. It is also dependent on VCC.
+ * DRIVE_STRENGTH_DEFAULT is just a placeholder to avoid changing the drive
+ * strength when there is no dt config for it.
+ */
+#define DRIVE_STRENGTH_DEFAULT (0 << DRIVE_STRENGTH_SHIFT)
+#define DRIVE_STRENGTH_LOW (1 << DRIVE_STRENGTH_SHIFT)
+#define DRIVE_STRENGTH_MED (2 << DRIVE_STRENGTH_SHIFT)
+#define DRIVE_STRENGTH_HI (3 << DRIVE_STRENGTH_SHIFT)
+
+enum at91_mux {
+ AT91_MUX_GPIO = 0,
+ AT91_MUX_PERIPH_A = 1,
+ AT91_MUX_PERIPH_B = 2,
+ AT91_MUX_PERIPH_C = 3,
+ AT91_MUX_PERIPH_D = 4,
+};
+
+/**
+ * struct at91_pinctrl_mux_ops - describes an AT91 mux ops group
+ * on new IP with support for periph C and D the way to mux in
+ * periph A and B has changed
+ * So provide the right callbacks
+ * if not present means the IP does not support it
+ * @mux_A_periph: assign the corresponding pin to the peripheral A function.
+ * @mux_B_periph: assign the corresponding pin to the peripheral B function.
+ * @mux_C_periph: assign the corresponding pin to the peripheral C function.
+ * @mux_D_periph: assign the corresponding pin to the peripheral D function.
+ * @set_deglitch: enable/disable the deglitch feature.
+ * @set_debounce: enable/disable the debounce feature.
+ * @set_pulldown: enable/disable the pulldown feature.
+ * @disable_schmitt_trig: disable schmitt trigger
+ */
+struct at91_pinctrl_mux_ops {
+ void (*mux_A_periph)(struct at91_port *pio, u32 mask);
+ void (*mux_B_periph)(struct at91_port *pio, u32 mask);
+ void (*mux_C_periph)(struct at91_port *pio, u32 mask);
+ void (*mux_D_periph)(struct at91_port *pio, u32 mask);
+ void (*set_deglitch)(struct at91_port *pio, u32 mask, bool is_on);
+ void (*set_debounce)(struct at91_port *pio, u32 mask, bool is_on,
+ u32 div);
+ void (*set_pulldown)(struct at91_port *pio, u32 mask, bool is_on);
+ void (*disable_schmitt_trig)(struct at91_port *pio, u32 mask);
+ void (*set_drivestrength)(struct at91_port *pio, u32 pin,
+ u32 strength);
+};
+
+static u32 two_bit_pin_value_shift_amount(u32 pin)
+{
+ /* return the shift value for a pin for "two bit" per pin registers,
+ * i.e. drive strength */
+ return 2 * ((pin >= MAX_NB_GPIO_PER_BANK/2)
+ ? pin - MAX_NB_GPIO_PER_BANK/2 : pin);
+}
+
+static void at91_mux_disable_interrupt(struct at91_port *pio, u32 mask)
+{
+ writel(mask, &pio->idr);
+}
+
+static void at91_mux_set_pullup(struct at91_port *pio, u32 mask, bool on)
+{
+ if (on)
+ writel(mask, &pio->mux.pio3.ppddr);
+
+ writel(mask, (on ? &pio->puer : &pio->pudr));
+}
+
+static void at91_mux_set_output(struct at91_port *pio, unsigned mask,
+ bool is_on, bool val)
+{
+ writel(mask, (val ? &pio->sodr : &pio->codr));
+ writel(mask, (is_on ? &pio->oer : &pio->odr));
+}
+
+static void at91_mux_set_multidrive(struct at91_port *pio, u32 mask, bool on)
+{
+ writel(mask, (on ? &pio->mder : &pio->mddr));
+}
+
+static void at91_mux_set_A_periph(struct at91_port *pio, u32 mask)
+{
+ writel(mask, &pio->mux.pio2.asr);
+}
+
+static void at91_mux_set_B_periph(struct at91_port *pio, u32 mask)
+{
+ writel(mask, &pio->mux.pio2.bsr);
+}
+
+static void at91_mux_pio3_set_A_periph(struct at91_port *pio, u32 mask)
+{
+ writel(readl(&pio->mux.pio3.abcdsr1) & ~mask, &pio->mux.pio3.abcdsr1);
+ writel(readl(&pio->mux.pio3.abcdsr2) & ~mask, &pio->mux.pio3.abcdsr2);
+}
+
+static void at91_mux_pio3_set_B_periph(struct at91_port *pio, u32 mask)
+{
+ writel(readl(&pio->mux.pio3.abcdsr1) | mask, &pio->mux.pio3.abcdsr1);
+ writel(readl(&pio->mux.pio3.abcdsr2) & ~mask, &pio->mux.pio3.abcdsr2);
+}
+
+static void at91_mux_pio3_set_C_periph(struct at91_port *pio, u32 mask)
+{
+ writel(readl(&pio->mux.pio3.abcdsr1) & ~mask, &pio->mux.pio3.abcdsr1);
+ writel(readl(&pio->mux.pio3.abcdsr2) | mask, &pio->mux.pio3.abcdsr2);
+}
+
+static void at91_mux_pio3_set_D_periph(struct at91_port *pio, u32 mask)
+{
+ writel(readl(&pio->mux.pio3.abcdsr1) | mask, &pio->mux.pio3.abcdsr1);
+ writel(readl(&pio->mux.pio3.abcdsr2) | mask, &pio->mux.pio3.abcdsr2);
+}
+
+static void at91_mux_set_deglitch(struct at91_port *pio, u32 mask, bool is_on)
+{
+ writel(mask, (is_on ? &pio->ifer : &pio->ifdr));
+}
+
+static void at91_mux_pio3_set_deglitch(struct at91_port *pio,
+ u32 mask, bool is_on)
+{
+ if (is_on)
+ writel(mask, &pio->mux.pio3.ifscdr);
+ at91_mux_set_deglitch(pio, mask, is_on);
+}
+
+static void at91_mux_pio3_set_debounce(struct at91_port *pio, u32 mask,
+ bool is_on, u32 div)
+{
+ if (is_on) {
+ writel(mask, &pio->mux.pio3.ifscer);
+ writel(div & PIO_SCDR_DIV, &pio->mux.pio3.scdr);
+ writel(mask, &pio->ifer);
+ } else {
+ writel(mask, &pio->mux.pio3.ifscdr);
+ }
+}
+
+static void at91_mux_pio3_set_pulldown(struct at91_port *pio,
+ u32 mask, bool is_on)
+{
+ if (is_on)
+ writel(mask, &pio->pudr);
+
+ writel(mask, (is_on ? &pio->mux.pio3.ppder : &pio->mux.pio3.ppddr));
+}
+
+static void at91_mux_pio3_disable_schmitt_trig(struct at91_port *pio,
+ u32 mask)
+{
+ writel(readl(&pio->schmitt) | mask, &pio->schmitt);
+}
+
+static void set_drive_strength(void *reg, u32 pin, u32 strength)
+{
+ u32 shift = two_bit_pin_value_shift_amount(pin);
+
+ clrsetbits_le32(reg, DRIVE_STRENGTH_MASK << shift, strength << shift);
+}
+
+static void at91_mux_sama5d3_set_drivestrength(struct at91_port *pio,
+ u32 pin, u32 setting)
+{
+ void *reg;
+
+ reg = &pio->driver12;
+ if (pin >= MAX_NB_GPIO_PER_BANK / 2)
+ reg = &pio->driver2;
+
+ /* do nothing if setting is zero */
+ if (!setting)
+ return;
+
+ /* strength is 1 to 1 with setting for SAMA5 */
+ set_drive_strength(reg, pin, setting);
+}
+
+static void at91_mux_sam9x5_set_drivestrength(struct at91_port *pio,
+ u32 pin, u32 setting)
+{
+ void *reg;
+
+ reg = &pio->driver1;
+ if (pin >= MAX_NB_GPIO_PER_BANK / 2)
+ reg = &pio->driver12;
+
+ /* do nothing if setting is zero */
+ if (!setting)
+ return;
+
+ /* strength is inverse on SAM9x5s with our defines
+ * 0 = hi, 1 = med, 2 = low, 3 = rsvd */
+ setting = DRIVE_STRENGTH_HI - setting;
+
+ set_drive_strength(reg, pin, setting);
+}
+
+static struct at91_pinctrl_mux_ops at91rm9200_ops = {
+ .mux_A_periph = at91_mux_set_A_periph,
+ .mux_B_periph = at91_mux_set_B_periph,
+ .set_deglitch = at91_mux_set_deglitch,
+};
+
+static struct at91_pinctrl_mux_ops at91sam9x5_ops = {
+ .mux_A_periph = at91_mux_pio3_set_A_periph,
+ .mux_B_periph = at91_mux_pio3_set_B_periph,
+ .mux_C_periph = at91_mux_pio3_set_C_periph,
+ .mux_D_periph = at91_mux_pio3_set_D_periph,
+ .set_deglitch = at91_mux_pio3_set_deglitch,
+ .set_debounce = at91_mux_pio3_set_debounce,
+ .set_pulldown = at91_mux_pio3_set_pulldown,
+ .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
+ .set_drivestrength = at91_mux_sam9x5_set_drivestrength,
+};
+
+static struct at91_pinctrl_mux_ops sama5d3_ops = {
+ .mux_A_periph = at91_mux_pio3_set_A_periph,
+ .mux_B_periph = at91_mux_pio3_set_B_periph,
+ .mux_C_periph = at91_mux_pio3_set_C_periph,
+ .mux_D_periph = at91_mux_pio3_set_D_periph,
+ .set_deglitch = at91_mux_pio3_set_deglitch,
+ .set_debounce = at91_mux_pio3_set_debounce,
+ .set_pulldown = at91_mux_pio3_set_pulldown,
+ .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
+ .set_drivestrength = at91_mux_sama5d3_set_drivestrength,
+};
+
+static void at91_mux_gpio_disable(struct at91_port *pio, u32 mask)
+{
+ writel(mask, &pio->pdr);
+}
+
+static void at91_mux_gpio_enable(struct at91_port *pio, u32 mask, bool input)
+{
+ writel(mask, &pio->per);
+ writel(mask, (input ? &pio->odr : &pio->oer));
+}
+
+static int at91_pmx_set(struct at91_pinctrl_mux_ops *ops,
+ struct at91_port *pio, u32 mask, enum at91_mux mux)
+{
+ at91_mux_disable_interrupt(pio, mask);
+ switch (mux) {
+ case AT91_MUX_GPIO:
+ at91_mux_gpio_enable(pio, mask, 1);
+ break;
+ case AT91_MUX_PERIPH_A:
+ ops->mux_A_periph(pio, mask);
+ break;
+ case AT91_MUX_PERIPH_B:
+ ops->mux_B_periph(pio, mask);
+ break;
+ case AT91_MUX_PERIPH_C:
+ if (!ops->mux_C_periph)
+ return -EINVAL;
+ ops->mux_C_periph(pio, mask);
+ break;
+ case AT91_MUX_PERIPH_D:
+ if (!ops->mux_D_periph)
+ return -EINVAL;
+ ops->mux_D_periph(pio, mask);
+ break;
+ }
+ if (mux)
+ at91_mux_gpio_disable(pio, mask);
+
+ return 0;
+}
+
+static int at91_pinconf_set(struct at91_pinctrl_mux_ops *ops,
+ struct at91_port *pio, u32 pin, u32 config)
+{
+ u32 mask = BIT(pin);
+
+ if ((config & PULL_UP) && (config & PULL_DOWN))
+ return -EINVAL;
+
+ at91_mux_set_output(pio, mask, config & OUTPUT,
+ (config & OUTPUT_VAL) >> OUTPUT_VAL_SHIFT);
+ at91_mux_set_pullup(pio, mask, config & PULL_UP);
+ at91_mux_set_multidrive(pio, mask, config & MULTI_DRIVE);
+ if (ops->set_deglitch)
+ ops->set_deglitch(pio, mask, config & DEGLITCH);
+ if (ops->set_debounce)
+ ops->set_debounce(pio, mask, config & DEBOUNCE,
+ (config & DEBOUNCE_VAL) >> DEBOUNCE_VAL_SHIFT);
+ if (ops->set_pulldown)
+ ops->set_pulldown(pio, mask, config & PULL_DOWN);
+ if (ops->disable_schmitt_trig && config & DIS_SCHMIT)
+ ops->disable_schmitt_trig(pio, mask);
+ if (ops->set_drivestrength)
+ ops->set_drivestrength(pio, pin,
+ (config & DRIVE_STRENGTH) >> DRIVE_STRENGTH_SHIFT);
+
+ return 0;
+}
+
+static int at91_pin_check_config(struct udevice *dev, u32 bank, u32 pin)
+{
+ struct at91_pinctrl_priv *priv = dev_get_priv(dev);
+
+ if (bank >= priv->nbanks) {
+ debug("pin conf bank %d >= nbanks %d\n", bank, priv->nbanks);
+ return -EINVAL;
+ }
+
+ if (pin >= MAX_NB_GPIO_PER_BANK) {
+ debug("pin conf pin %d >= %d\n", pin, MAX_NB_GPIO_PER_BANK);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int at91_pinctrl_set_state(struct udevice *dev, struct udevice *config)
+{
+ struct at91_pinctrl_priv *priv = dev_get_priv(dev);
+ const void *blob = gd->fdt_blob;
+ int node = config->of_offset;
+ u32 cells[MAX_PINMUX_ENTRIES];
+ const u32 *list = cells;
+ u32 bank, pin;
+ u32 conf, mask, count, i;
+ int size;
+ int ret;
+ enum at91_mux mux;
+ struct at91_port *pio;
+ struct at91_pinctrl_mux_ops *ops =
+ (struct at91_pinctrl_mux_ops *)dev_get_driver_data(dev);
+
+ /*
+ * the binding format is atmel,pins = <bank pin mux CONFIG ...>,
+ * do sanity check and calculate pins number
+ */
+ size = fdtdec_get_int_array_count(blob, node, "atmel,pins",
+ cells, ARRAY_SIZE(cells));
+
+ /* we do not check return since it's safe node passed down */
+ count = size >> 2;
+ if (!count)
+ return -EINVAL;
+
+ for (i = 0; i < count; i++) {
+ bank = *list++;
+ pin = *list++;
+ mux = *list++;
+ conf = *list++;
+
+ ret = at91_pin_check_config(dev, bank, pin);
+ if (ret)
+ return ret;
+
+ pio = priv->reg_base[bank];
+ mask = BIT(pin);
+
+ ret = at91_pmx_set(ops, pio, mask, mux);
+ if (ret)
+ return ret;
+
+ ret = at91_pinconf_set(ops, pio, pin, conf);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+const struct pinctrl_ops at91_pinctrl_ops = {
+ .set_state = at91_pinctrl_set_state,
+};
+
+static int at91_pinctrl_probe(struct udevice *dev)
+{
+ struct at91_pinctrl_priv *priv = dev_get_priv(dev);
+ fdt_addr_t addr_base;
+ int index;
+
+ for (index = 0; index < MAX_GPIO_BANKS; index++) {
+ addr_base = dev_get_addr_index(dev, index);
+ if (addr_base == FDT_ADDR_T_NONE)
+ break;
+
+ priv->reg_base[index] = (struct at91_port *)addr_base;
+ }
+
+ priv->nbanks = index;
+
+ return 0;
+}
+
+static const struct udevice_id at91_pinctrl_match[] = {
+ { .compatible = "atmel,sama5d3-pinctrl", .data = (ulong)&sama5d3_ops },
+ { .compatible = "atmel,at91sam9x5-pinctrl", .data = (ulong)&at91sam9x5_ops },
+ { .compatible = "atmel,at91rm9200-pinctrl", .data = (ulong)&at91rm9200_ops },
+ {}
+};
+
+U_BOOT_DRIVER(at91_pinctrl) = {
+ .name = "pinctrl_at91",
+ .id = UCLASS_PINCTRL,
+ .of_match = at91_pinctrl_match,
+ .probe = at91_pinctrl_probe,
+ .priv_auto_alloc_size = sizeof(struct at91_pinctrl_priv),
+ .ops = &at91_pinctrl_ops,
+};
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 1f819d487b6..4f86780cb12 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -452,8 +452,7 @@ const struct dm_serial_ops ns16550_serial_ops = {
.setbrg = ns16550_serial_setbrg,
};
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
-#if CONFIG_IS_ENABLED(OF_CONTROL)
+#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
/*
* Please consider existing compatible strings before adding a new
* one to keep this table compact. Or you may add a generic "ns16550"
@@ -473,13 +472,16 @@ static const struct udevice_id ns16550_serial_ids[] = {
{ .compatible = "ti,dra742-uart", .data = PORT_NS16550 },
{}
};
-#endif
+#endif /* OF_CONTROL && !OF_PLATDATA */
#if CONFIG_IS_ENABLED(SERIAL_PRESENT)
+
+/* TODO(sjg@chromium.org): Integrate this into a macro like CONFIG_IS_ENABLED */
+#if !defined(CONFIG_TPL_BUILD) || defined(CONFIG_TPL_DM_SERIAL)
U_BOOT_DRIVER(ns16550_serial) = {
.name = "ns16550_serial",
.id = UCLASS_SERIAL,
-#if CONFIG_IS_ENABLED(OF_CONTROL)
+#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
.of_match = ns16550_serial_ids,
.ofdata_to_platdata = ns16550_serial_ofdata_to_platdata,
.platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
@@ -490,5 +492,6 @@ U_BOOT_DRIVER(ns16550_serial) = {
.flags = DM_FLAG_PRE_RELOC,
};
#endif
-#endif /* !OF_PLATDATA */
+#endif /* SERIAL_PRESENT */
+
#endif /* CONFIG_DM_SERIAL */
diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c
index a49134a95a8..941b424a4c6 100644
--- a/drivers/serial/serial_pl01x.c
+++ b/drivers/serial/serial_pl01x.c
@@ -117,7 +117,7 @@ static int pl01x_generic_setbrg(struct pl01x_regs *regs, enum pl01x_type type,
divisor = UART_PL010_BAUD_9600;
break;
case 19200:
- divisor = UART_PL010_BAUD_9600;
+ divisor = UART_PL010_BAUD_19200;
break;
case 38400:
divisor = UART_PL010_BAUD_38400;
diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c
index 32ecbe2b099..20455ffb542 100644
--- a/drivers/video/mxsfb.c
+++ b/drivers/video/mxsfb.c
@@ -36,7 +36,7 @@ __weak void mxsfb_system_setup(void)
}
/*
- * DENX M28EVK:
+ * ARIES M28EVK:
* setenv videomode
* video=ctfb:x:800,y:480,depth:18,mode:0,pclk:30066,
* le:0,ri:256,up:0,lo:45,hs:1,vs:1,sync:100663296,vmode:0
generated by cgit v1.2.3 (git 2.0.4) at 2025-10-18 14:06:19 +0000