19 files changed, 10 insertions, 376 deletions

diff --git a/drivers/ddr/fsl/Kconfig b/drivers/ddr/fsl/Kconfig
index 8b480dfd690..8246f627982 100644
--- a/drivers/ddr/fsl/Kconfig
+++ b/drivers/ddr/fsl/Kconfig
@@ -2,8 +2,8 @@ config SYS_FSL_DDR
 	bool
 	help
 	  Select Freescale General DDR driver, shared between most Freescale
-	  PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM-
-	  based Layerscape SoCs (such as ls2080a).
+	  PowerPC- based SoCs (such as mpc83xx, mpc85xx and ARM- based
+	  Layerscape SoCs (such as ls2080a).
 
 config SYS_FSL_MMDC
 	bool
@@ -41,13 +41,10 @@ config SYS_NUM_DDR_CTLRS
 			ARCH_T4240
 	default 2 if	ARCH_B4860	|| \
 			ARCH_BSC9132	|| \
-			ARCH_MPC8572	|| \
-			ARCH_MPC8641	|| \
 			ARCH_P4080	|| \
 			ARCH_P5040	|| \
 			ARCH_LX2160A	|| \
-			ARCH_LX2162A	|| \
-			ARCH_T4160
+			ARCH_LX2162A
 	default 1
 
 config SYS_FSL_DDR_VER
@@ -80,12 +77,6 @@ config SYS_FSL_DDRC_GEN2
 	help
 	  Enable Freescale DDR2 controller.
 
-config SYS_FSL_DDRC_86XX_GEN2
-	bool
-	depends on MPC86xx
-	help
-	  Enable Freescale DDR2 controller for MPC86xx SoCs.
-
 config SYS_FSL_DDRC_GEN3
 	bool
 	depends on PPC
@@ -137,7 +128,6 @@ config SYS_FSL_DDR2
 	bool "Freescale DDR2 controller"
 	depends on SYS_FSL_HAS_DDR2
 	select SYS_FSL_DDRC_GEN2 if (!MPC86xx && !SYS_FSL_DDRC_GEN3)
-	select SYS_FSL_DDRC_86XX_GEN2 if MPC86xx
 
 config SYS_FSL_DDR1
 	bool "Freescale DDR1 controller"
diff --git a/drivers/ddr/fsl/Makefile b/drivers/ddr/fsl/Makefile
index c675f44ab00..8081d0cd82f 100644
--- a/drivers/ddr/fsl/Makefile
+++ b/drivers/ddr/fsl/Makefile
@@ -28,7 +28,6 @@ obj-$(CONFIG_FSL_DDR_INTERACTIVE)	+= interactive.o
 obj-$(CONFIG_SYS_FSL_DDRC_GEN1)	+= mpc85xx_ddr_gen1.o
 obj-$(CONFIG_SYS_FSL_DDRC_GEN2)	+= mpc85xx_ddr_gen2.o
 obj-$(CONFIG_SYS_FSL_DDRC_GEN3)	+= mpc85xx_ddr_gen3.o
-obj-$(CONFIG_SYS_FSL_DDRC_86XX_GEN2)	+= mpc86xx_ddr.o
 obj-$(CONFIG_SYS_FSL_DDRC_ARM_GEN3)	+= arm_ddr_gen3.o
 obj-$(CONFIG_SYS_FSL_DDRC_GEN4) += fsl_ddr_gen4.o
 obj-$(CONFIG_SYS_FSL_MMDC) += fsl_mmdc.o
diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index c849ef3a4c7..b5122d1a1c3 100644
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -1863,25 +1863,13 @@ static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr)
 static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
 					 const memctl_options_t *popts)
 {
-	unsigned int clk_adjust;	/* Clock adjust */
-	unsigned int ss_en = 0;		/* Source synchronous enable */
-
-#if defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_ARCH_MPC8555)
-	/* Per FSL Application Note: AN2805 */
-	ss_en = 1;
-#endif
-	if (fsl_ddr_get_version(0) >= 0x40701) {
+	if (fsl_ddr_get_version(0) >= 0x40701)
 		/* clk_adjust in 5-bits on T-series and LS-series */
-		clk_adjust = (popts->clk_adjust & 0x1F) << 22;
-	} else {
+		ddr->ddr_sdram_clk_cntl = (popts->clk_adjust & 0x1F) << 22;
+	else
 		/* clk_adjust in 4-bits on earlier MPC85xx and P-series */
-		clk_adjust = (popts->clk_adjust & 0xF) << 23;
-	}
+		ddr->ddr_sdram_clk_cntl = (popts->clk_adjust & 0xF) << 23;
 
-	ddr->ddr_sdram_clk_cntl = (0
-				   | ((ss_en & 0x1) << 31)
-				   | clk_adjust
-				   );
 	debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl);
 }
 
diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen1.c b/drivers/ddr/fsl/mpc85xx_ddr_gen1.c
index 572f3703d51..9c2ddeaf932 100644
--- a/drivers/ddr/fsl/mpc85xx_ddr_gen1.c
+++ b/drivers/ddr/fsl/mpc85xx_ddr_gen1.c
@@ -48,9 +48,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 	out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
 	out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
 	out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
-#if defined(CONFIG_ARCH_MPC8555) || defined(CONFIG_ARCH_MPC8541)
-	out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
-#endif
 
 	/*
 	 * 200 painful micro-seconds must elapse between
diff --git a/drivers/ddr/fsl/mpc86xx_ddr.c b/drivers/ddr/fsl/mpc86xx_ddr.c
deleted file mode 100644
index 43ed1ba432d..00000000000
--- a/drivers/ddr/fsl/mpc86xx_ddr.c
+++ /dev/null
@@ -1,84 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <log.h>
-#include <asm/io.h>
-#include <fsl_ddr_sdram.h>
-#include <linux/delay.h>
-
-#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
-#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
-#endif
-
-void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
-			     unsigned int ctrl_num, int step)
-{
-	unsigned int i;
-	struct ccsr_ddr __iomem *ddr;
-
-	switch (ctrl_num) {
-	case 0:
-		ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
-		break;
-	case 1:
-		ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
-		break;
-	default:
-		printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
-		return;
-	}
-
-	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
-		if (i == 0) {
-			out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
-			out_be32(&ddr->cs0_config, regs->cs[i].config);
-
-		} else if (i == 1) {
-			out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
-			out_be32(&ddr->cs1_config, regs->cs[i].config);
-
-		} else if (i == 2) {
-			out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
-			out_be32(&ddr->cs2_config, regs->cs[i].config);
-
-		} else if (i == 3) {
-			out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
-			out_be32(&ddr->cs3_config, regs->cs[i].config);
-		}
-	}
-
-	out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);
-	out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
-	out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
-	out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
-	out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
-	out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
-	out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
-	out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
-	out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
-	out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
-	out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
-	out_be32(&ddr->init_addr, regs->ddr_init_addr);
-	out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
-
-	debug("before go\n");
-
-	/*
-	 * 200 painful micro-seconds must elapse between
-	 * the DDR clock setup and the DDR config enable.
-	 */
-	udelay(200);
-	asm volatile("sync;isync");
-
-	out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg);
-
-	/*
-	 * Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done
-	 */
-	while (in_be32(&ddr->sdram_cfg_2) & 0x10) {
-		udelay(10000);		/* throttle polling rate */
-	}
-}
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 8541ba0b0ae..06dfc32fa54 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -33,7 +33,6 @@ obj-$(CONFIG_RCAR_GPIO)		+= gpio-rcar.o
 obj-$(CONFIG_RZA1_GPIO)		+= gpio-rza1.o
 obj-$(CONFIG_S5P)		+= s5p_gpio.o
 obj-$(CONFIG_SANDBOX_GPIO)	+= sandbox.o
-obj-$(CONFIG_SPEAR_GPIO)	+= spear_gpio.o
 obj-$(CONFIG_TEGRA_GPIO)	+= tegra_gpio.o
 obj-$(CONFIG_TEGRA186_GPIO)	+= tegra186_gpio.o
 obj-$(CONFIG_DA8XX_GPIO)	+= da8xx_gpio.o
diff --git a/drivers/gpio/spear_gpio.c b/drivers/gpio/spear_gpio.c
deleted file mode 100644
index 4e4cd125457..00000000000
--- a/drivers/gpio/spear_gpio.c
+++ /dev/null
@@ -1,89 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2012 Stefan Roese <sr@denx.de>
- */
-
-/*
- * Driver for SPEAr600 GPIO controller
- */
-
-#include <common.h>
-#include <malloc.h>
-#include <asm/arch/hardware.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include <errno.h>
-
-static int gpio_direction(unsigned gpio,
-			  enum gpio_direction direction)
-{
-	struct gpio_regs *regs = (struct gpio_regs *)CONFIG_GPIO_BASE;
-	u32 val;
-
-	val = readl(&regs->gpiodir);
-
-	if (direction == GPIO_DIRECTION_OUT)
-		val |= 1 << gpio;
-	else
-		val &= ~(1 << gpio);
-
-	writel(val, &regs->gpiodir);
-
-	return 0;
-}
-
-int gpio_set_value(unsigned gpio, int value)
-{
-	struct gpio_regs *regs = (struct gpio_regs *)CONFIG_GPIO_BASE;
-
-	if (value)
-		writel(1 << gpio, &regs->gpiodata[DATA_REG_ADDR(gpio)]);
-	else
-		writel(0, &regs->gpiodata[DATA_REG_ADDR(gpio)]);
-
-	return 0;
-}
-
-int gpio_get_value(unsigned gpio)
-{
-	struct gpio_regs *regs = (struct gpio_regs *)CONFIG_GPIO_BASE;
-	u32 val;
-
-	val = readl(&regs->gpiodata[DATA_REG_ADDR(gpio)]);
-
-	return !!val;
-}
-
-int gpio_request(unsigned gpio, const char *label)
-{
-	if (gpio >= SPEAR_GPIO_COUNT)
-		return -EINVAL;
-
-	return 0;
-}
-
-int gpio_free(unsigned gpio)
-{
-	return 0;
-}
-
-void gpio_toggle_value(unsigned gpio)
-{
-	gpio_set_value(gpio, !gpio_get_value(gpio));
-}
-
-int gpio_direction_input(unsigned gpio)
-{
-	return gpio_direction(gpio, GPIO_DIRECTION_IN);
-}
-
-int gpio_direction_output(unsigned gpio, int value)
-{
-	int ret = gpio_direction(gpio, GPIO_DIRECTION_OUT);
-
-	if (ret < 0)
-		return ret;
-
-	gpio_set_value(gpio, value);
-	return 0;
-}
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 41065dd5026..35d6e2c8ec5 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -136,16 +136,6 @@ config SYS_I2C_DW
 	  controller is used in various SoCs, e.g. the ST SPEAr, Altera
 	  SoCFPGA, Synopsys ARC700 and some Intel x86 SoCs.
 
-config SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
-	bool "DW I2C Enable Status Register not supported"
-	depends on SYS_I2C_DW && (TARGET_SPEAR300 || TARGET_SPEAR310 || \
-		TARGET_SPEAR320 || TARGET_SPEAR600 || TARGET_X600)
-	default y
-	help
-	  Some versions of the Designware I2C controller do not support the
-	  enable status register. This config option can be enabled in such
-	  cases.
-
 config SYS_I2C_ASPEED
 	bool "Aspeed I2C Controller"
 	depends on DM_I2C && ARCH_ASPEED
diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c
index 072803691e3..e57eed0f6cd 100644
--- a/drivers/i2c/designware_i2c.c
+++ b/drivers/i2c/designware_i2c.c
@@ -24,16 +24,6 @@
  */
 #define DW_I2C_COMP_TYPE	0x44570140
 
-#ifdef CONFIG_SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
-static int  dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
-{
-	u32 ena = enable ? IC_ENABLE_0B : 0;
-
-	writel(ena, &i2c_base->ic_enable);
-
-	return 0;
-}
-#else
 static int dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
 {
 	u32 ena = enable ? IC_ENABLE_0B : 0;
@@ -55,7 +45,6 @@ static int dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
 
 	return -ETIMEDOUT;
 }
-#endif
 
 /* High and low times in different speed modes (in ns) */
 enum {
diff --git a/drivers/mtd/nand/raw/fsmc_nand.c b/drivers/mtd/nand/raw/fsmc_nand.c
index 1f4c74f0f63..1c24710b2db 100644
--- a/drivers/mtd/nand/raw/fsmc_nand.c
+++ b/drivers/mtd/nand/raw/fsmc_nand.c
@@ -389,55 +389,6 @@ static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
 	return 0;
 }
 
-#ifndef CONFIG_SPL_BUILD
-/*
- * fsmc_nand_switch_ecc - switch the ECC operation between different engines
- *
- * @eccstrength		- the number of bits that could be corrected
- *			  (1 - HW, 4 - SW BCH4)
- */
-int fsmc_nand_switch_ecc(uint32_t eccstrength)
-{
-	struct nand_chip *nand;
-	struct mtd_info *mtd;
-	int err;
-
-	/*
-	 * This functions is only called on SPEAr600 platforms, supporting
-	 * 1 bit HW ECC. The BCH8 HW ECC (FSMC_VER8) from the ST-Ericsson
-	 * Nomadik SoC is currently supporting this fsmc_nand_switch_ecc()
-	 * function, as it doesn't need to switch to a different ECC layout.
-	 */
-	mtd = get_nand_dev_by_index(nand_curr_device);
-	nand = mtd_to_nand(mtd);
-
-	/* Setup the ecc configurations again */
-	if (eccstrength == 1) {
-		nand->ecc.mode = NAND_ECC_HW;
-		nand->ecc.bytes = 3;
-		nand->ecc.strength = 1;
-		nand->ecc.layout = &fsmc_ecc1_layout;
-		nand->ecc.calculate = fsmc_read_hwecc;
-		nand->ecc.correct = nand_correct_data;
-	} else if (eccstrength == 4) {
-		/*
-		 * .calculate .correct and .bytes will be set in
-		 * nand_scan_tail()
-		 */
-		nand->ecc.mode = NAND_ECC_SOFT_BCH;
-		nand->ecc.strength = 4;
-		nand->ecc.layout = NULL;
-	} else {
-		printf("Error: ECC strength %d not supported!\n", eccstrength);
-	}
-
-	/* Update NAND handling after ECC mode switch */
-	err = nand_scan_tail(mtd);
-
-	return err;
-}
-#endif /* CONFIG_SPL_BUILD */
-
 int fsmc_nand_init(struct nand_chip *nand)
 {
 	static int chip_nr;
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 2a7c8f9a7ff..483401681d8 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -733,13 +733,11 @@ config SYS_DPAA_QBMAN
 		     ARCH_B4420 || \
 		     ARCH_P1023 || \
 		     ARCH_P2041 || \
-		     ARCH_T1023 || \
 		     ARCH_T1024 || \
 		     ARCH_T1040 || \
 		     ARCH_T1042 || \
 		     ARCH_T2080 || \
 		     ARCH_T4240 || \
-		     ARCH_T4160 || \
 		     ARCH_P4080 || \
 		     ARCH_P3041 || \
 		     ARCH_P5040 || \
diff --git a/drivers/net/fm/Makefile b/drivers/net/fm/Makefile
index b4ede61113f..ae384121766 100644
--- a/drivers/net/fm/Makefile
+++ b/drivers/net/fm/Makefile
@@ -23,11 +23,9 @@ obj-$(CONFIG_ARCH_P4080) += p4080.o
 obj-$(CONFIG_ARCH_P5040) += p5040.o
 obj-$(CONFIG_ARCH_T1040) += t1040.o
 obj-$(CONFIG_ARCH_T1042)	+= t1040.o
-obj-$(CONFIG_ARCH_T1023) += t1024.o
 obj-$(CONFIG_ARCH_T1024) += t1024.o
 obj-$(CONFIG_ARCH_T2080) += t2080.o
 obj-$(CONFIG_ARCH_T4240) += t4240.o
-obj-$(CONFIG_ARCH_T4160) += t4240.o
 obj-$(CONFIG_ARCH_B4420) += b4860.o
 obj-$(CONFIG_ARCH_B4860) += b4860.o
 obj-$(CONFIG_ARCH_LS1043A)	+= ls1043.o
diff --git a/drivers/net/mcfmii.c b/drivers/net/mcfmii.c
index 0987266c96e..ca06b35316d 100644
--- a/drivers/net/mcfmii.c
+++ b/drivers/net/mcfmii.c
@@ -11,11 +11,7 @@
 #include <asm/global_data.h>
 #include <linux/delay.h>
 
-#ifdef CONFIG_MCF547x_8x
-#include <asm/fsl_mcdmafec.h>
-#else
 #include <asm/fec.h>
-#endif
 #include <asm/immap.h>
 #include <linux/mii.h>
 
diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c
index 05663c72b4b..b128a05dd38 100644
--- a/drivers/pci/pci_auto.c
+++ b/drivers/pci/pci_auto.c
@@ -348,8 +348,7 @@ int dm_pciauto_config_device(struct udevice *dev)
 		      PCI_DEV(dm_pci_get_bdf(dev)));
 		break;
 #endif
-#if defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_TARGET_VME8349) && \
-		!defined(CONFIG_TARGET_CADDY2)
+#if defined(CONFIG_ARCH_MPC834X)
 	case PCI_CLASS_BRIDGE_OTHER:
 		/*
 		 * The host/PCI bridge 1 seems broken in 8349 - it presents
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 9f82467c4e3..961e3fb0314 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -332,7 +332,7 @@ config DEBUG_UART_APBUART
 
 config DEBUG_UART_PL010
 	bool "pl010"
-	depends on PL01X_SERIAL || PL010_SERIAL
+	depends on PL01X_SERIAL
 	help
 	  Select this to enable a debug UART using the pl01x driver with the
 	  PL010 UART type. You will need to provide parameters to make this
@@ -695,12 +695,6 @@ config INTEL_MID_SERIAL
 	  Select this to enable a UART for Intel MID platforms.
 	  This uses the ns16550 driver as a library.
 
-config PL010_SERIAL
-	bool "ARM PL010 driver"
-	depends on !DM_SERIAL
-	help
-	  Select this to enable a UART for platforms using PL010.
-
 config PL011_SERIAL
 	bool "ARM PL011 driver"
 	depends on !DM_SERIAL
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 6c0fdca5861..3cbea8156f8 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -24,7 +24,6 @@ endif
 ifdef CONFIG_DM_SERIAL
 obj-$(CONFIG_PL01X_SERIAL) += serial_pl01x.o
 else
-obj-$(CONFIG_PL010_SERIAL) += serial_pl01x.o
 obj-$(CONFIG_PL011_SERIAL) += serial_pl01x.o
 obj-$(CONFIG_SYS_NS16550_SERIAL) += serial_ns16550.o
 endif
diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c
index 5283d5ed118..76b96ad414c 100644
--- a/drivers/serial/serial_pl01x.c
+++ b/drivers/serial/serial_pl01x.c
@@ -191,9 +191,7 @@ static void pl01x_serial_init_baud(int baudrate)
 {
 	int clock = 0;
 
-#if defined(CONFIG_PL010_SERIAL)
-	pl01x_type = TYPE_PL010;
-#elif defined(CONFIG_PL011_SERIAL)
+#if defined(CONFIG_PL011_SERIAL)
 	pl01x_type = TYPE_PL011;
 	clock = CONFIG_PL011_CLOCK;
 #endif
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index a12e8f27025..eb6fe9f6b30 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -36,7 +36,6 @@ obj-$(CONFIG_USB_EHCI_OMAP) += ehci-omap.o
 obj-$(CONFIG_USB_EHCI_MARVELL) += ehci-marvell.o
 obj-$(CONFIG_USB_EHCI_MSM) += ehci-msm.o
 obj-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o
-obj-$(CONFIG_USB_EHCI_SPEAR) += ehci-spear.o
 obj-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o
 obj-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o
 obj-$(CONFIG_USB_EHCI_VF) += ehci-vf.o
diff --git a/drivers/usb/host/ehci-spear.c b/drivers/usb/host/ehci-spear.c
deleted file mode 100644
index 3e87e0c7fd8..00000000000
--- a/drivers/usb/host/ehci-spear.c
+++ /dev/null
@@ -1,77 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2010
- * Armando Visconti, ST Micoelectronics, <armando.visconti@st.com>.
- *
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- */
-
-#include <common.h>
-#include <log.h>
-#include <asm/io.h>
-#include <usb.h>
-#include <linux/delay.h>
-#include "ehci.h"
-#include <asm/arch/hardware.h>
-#include <asm/arch/spr_misc.h>
-
-static void spear6xx_usbh_stop(void)
-{
-	struct misc_regs *const misc_p =
-	    (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
-	u32 periph1_rst = readl(misc_p->periph1_rst);
-
-	periph1_rst |= PERIPH_USBH1 | PERIPH_USBH2;
-	writel(periph1_rst, misc_p->periph1_rst);
-
-	udelay(1000);
-	periph1_rst &= ~(PERIPH_USBH1 | PERIPH_USBH2);
-	writel(periph1_rst, misc_p->periph1_rst);
-}
-
-/*
- * Create the appropriate control structures to manage
- * a new EHCI host controller.
- */
-int ehci_hcd_init(int index, enum usb_init_type init,
-		struct ehci_hccr **hccr, struct ehci_hcor **hcor)
-{
-	u32 ehci = 0;
-
-	switch (index) {
-	case 0:
-		ehci = CONFIG_SYS_UHC0_EHCI_BASE;
-		break;
-	case 1:
-		ehci = CONFIG_SYS_UHC1_EHCI_BASE;
-		break;
-	default:
-		printf("ERROR: wrong controller index!\n");
-		break;
-	};
-
-	*hccr = (struct ehci_hccr *)(ehci + 0x100);
-	*hcor = (struct ehci_hcor *)((uint32_t) *hccr +
-			HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
-
-	debug("SPEAr-ehci: init hccr %x and hcor %x hc_length %d\n",
-		(uint32_t)*hccr, (uint32_t)*hcor,
-		(uint32_t)HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
-
-	return 0;
-}
-
-/*
- * Destroy the appropriate control structures corresponding
- * the the EHCI host controller.
- */
-int ehci_hcd_stop(int index)
-{
-#if defined(CONFIG_SPEAR600)
-	spear6xx_usbh_stop();
-#endif
-
-	return 0;
-}