diff options
Diffstat (limited to 'drivers')
29 files changed, 1393 insertions, 223 deletions
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig index 4fbb63a148a..29ceab849c0 100644 --- a/drivers/ata/Kconfig +++ b/drivers/ata/Kconfig @@ -1,6 +1,7 @@ config AHCI bool "Support SATA controllers with driver model" depends on DM + select BLK help This enables a uclass for disk controllers in U-Boot. Various driver types can use this, such as AHCI/SATA. It does not provide any standard @@ -9,6 +10,7 @@ config AHCI config SATA bool "Support SATA controllers" + select BLK help This enables support for SATA (Serial Advanced Technology Attachment), a serial bus standard for connecting to hard drives and diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig index 5283d8981e0..cc75bad02b8 100644 --- a/drivers/block/Kconfig +++ b/drivers/block/Kconfig @@ -1,8 +1,5 @@ config BLK - bool # "Support block devices" - depends on DM - def_bool y if MMC || USB || SCSI || NVME || IDE || AHCI || SATA - def_bool y if EFI_MEDIA || VIRTIO_BLK || PVBLOCK + bool help Enable support for block devices, such as SCSI, MMC and USB flash sticks. These provide a block-level interface which permits @@ -100,6 +97,7 @@ config TPL_BLOCK_CACHE config EFI_MEDIA bool "Support EFI media drivers" default y if EFI || SANDBOX + select BLK help Enable this to support media devices on top of UEFI. This enables just the uclass so you also need a specific driver to make this do @@ -139,6 +137,7 @@ endif # EFI_MEDIA config IDE bool "Support IDE controllers" + select BLK help Enables support for IDE (Integrated Drive Electronics) hard drives. This allows access to raw blocks and filesystems on an IDE drive diff --git a/drivers/core/root.c b/drivers/core/root.c index c7fb58285ca..15b8c83fee9 100644 --- a/drivers/core/root.c +++ b/drivers/core/root.c @@ -288,26 +288,40 @@ void *dm_priv_to_rw(void *priv) } #endif -static int dm_probe_devices(struct udevice *dev, bool pre_reloc_only) +/** + * dm_probe_devices() - Check whether to probe a device and all children + * + * Probes the device if DM_FLAG_PROBE_AFTER_BIND is enabled for it. Then scans + * all its children recursively to do the same. + * + * @dev: Device to (maybe) probe + * Return 0 if OK, -ve on error + */ +static int dm_probe_devices(struct udevice *dev) { - ofnode node = dev_ofnode(dev); struct udevice *child; - int ret; - - if (pre_reloc_only && - (!ofnode_valid(node) || !ofnode_pre_reloc(node)) && - !(dev->driver->flags & DM_FLAG_PRE_RELOC)) - goto probe_children; if (dev_get_flags(dev) & DM_FLAG_PROBE_AFTER_BIND) { + int ret; + ret = device_probe(dev); if (ret) return ret; } -probe_children: list_for_each_entry(child, &dev->child_head, sibling_node) - dm_probe_devices(child, pre_reloc_only); + dm_probe_devices(child); + + return 0; +} + +int dm_autoprobe(void) +{ + int ret; + + ret = dm_probe_devices(gd->dm_root); + if (ret) + return log_msg_ret("pro", ret); return 0; } @@ -344,7 +358,7 @@ static int dm_scan(bool pre_reloc_only) if (ret) return ret; - return dm_probe_devices(gd->dm_root, pre_reloc_only); + return 0; } int dm_init_and_scan(bool pre_reloc_only) diff --git a/drivers/gpio/adp5585_gpio.c b/drivers/gpio/adp5585_gpio.c index ea0cb75459b..114583b3c3b 100644 --- a/drivers/gpio/adp5585_gpio.c +++ b/drivers/gpio/adp5585_gpio.c @@ -224,7 +224,7 @@ static int adp5585_probe(struct udevice *dev) } static const struct udevice_id adp5585_ids[] = { - { .compatible = "adp5585" }, + { .compatible = "adi,adp5585" }, { } }; diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 6009d55f400..da84b35e804 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -568,7 +568,7 @@ config QFW_MMIO config QFW_SMBIOS bool default y - depends on QFW && SMBIOS && !SANDBOX + depends on QFW && SMBIOS && !SANDBOX && !SYSINFO_SMBIOS help Hidden option to read SMBIOS tables from QEMU. diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index f4fdf15242c..4827834b4aa 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -3,7 +3,8 @@ menu "MMC Host controller Support" config MMC bool "MMC/SD/SDIO card support" default ARM || PPC || SANDBOX - select DM_MMC if DM + select BLK + select DM_MMC help This selects MultiMediaCard, Secure Digital and Secure Digital I/O support. @@ -39,14 +40,14 @@ config MMC_BROKEN_CD If card detection feature is broken, just poll to detect. config DM_MMC - bool "Enable MMC controllers using Driver Model" + bool depends on DM help - This enables the MultiMediaCard (MMC) uclass which supports MMC and - Secure Digital I/O (SDIO) cards. Both removable (SD, micro-SD, etc.) - and non-removable (e.g. eMMC chip) devices are supported. These - appear as block devices in U-Boot and can support filesystems such - as EXT4 and FAT. + This enables the MultiMediaCard (MMC) driver model uclass which + supports MMC and Secure Digital I/O (SDIO) cards. Both removable (SD, + micro-SD, etc.) and non-removable (e.g. eMMC chip) devices are + supported. These appear as block devices in U-Boot and can support + filesystems such as EXT4 and FAT. config SPL_DM_MMC bool "Enable MMC controllers using Driver Model in SPL" @@ -79,7 +80,7 @@ config MMC_SDHCI_ADMA_HELPERS config MMC_SPI bool "Support for SPI-based MMC controller" - depends on DM_MMC && DM_SPI + depends on DM_SPI help This selects SPI-based MMC controllers. If you have an MMC controller on a SPI bus, say Y here. @@ -97,7 +98,6 @@ config MMC_SPI_CRC_ON config ARM_PL180_MMCI bool "ARM AMBA Multimedia Card Interface and compatible support" - depends on DM_MMC help This selects the ARM(R) AMBA(R) PrimeCell Multimedia Card Interface (PL180, PL181 and compatible) support. @@ -258,7 +258,6 @@ config MMC_DW config MMC_DW_CORTINA bool "Cortina specific extensions for Synopsys DW Memory Card Interface" - depends on DM_MMC depends on MMC_DW help This selects support for Cortina SoC specific extensions to the @@ -285,7 +284,7 @@ config MMC_DW_K3 config MMC_DW_ROCKCHIP bool "Rockchip SD/MMC controller support" - depends on DM_MMC && OF_CONTROL + depends on OF_CONTROL depends on MMC_DW help This enables support for the Rockchip SD/MMM controller, which is @@ -306,7 +305,6 @@ config MMC_DW_SOCFPGA config MMC_DW_SNPS bool "Extensions for DW Memory Card Interface used in Synopsys ARC devboards" depends on MMC_DW - depends on DM_MMC depends on OF_CONTROL depends on CLK help @@ -317,13 +315,12 @@ config NEXELL_DWMMC bool "Nexell SD/MMC controller support" depends on ARCH_NEXELL depends on MMC_DW - depends on DM_MMC depends on PINCTRL_NEXELL default y config MMC_MESON_GX bool "Meson GX EMMC controller support" - depends on DM_MMC && ARCH_MESON + depends on ARCH_MESON help Support for EMMC host controller on Meson GX ARM SoCs platform (S905) @@ -338,7 +335,7 @@ config MMC_MXC config MMC_OWL bool "Actions OWL Multimedia Card Interface support" - depends on ARCH_OWL && DM_MMC && BLK + depends on ARCH_OWL help This selects the OWL SD/MMC host controller found on board based on Actions S700/S900 SoC. @@ -366,7 +363,6 @@ config MMC_PCI config MMC_OCTEONTX bool "Marvell Octeon Multimedia Card Interface support" depends on (ARCH_OCTEON || ARCH_OCTEONTX || ARCH_OCTEONTX2) - depends on DM_MMC select MMC_SUPPORTS_TUNING if ARCH_OCTEONTX2 help This selects the Octeon Multimedia card Interface. @@ -377,7 +373,7 @@ config MMC_OCTEONTX config MVEBU_MMC bool "Kirkwood MMC controller support" - depends on DM_MMC && ARCH_KIRKWOOD + depends on ARCH_KIRKWOOD help Support for MMC host controller on Kirkwood SoCs. If you are on a Kirkwood architecture, say Y here. @@ -386,8 +382,7 @@ config MVEBU_MMC config MMC_OMAP_HS bool "TI OMAP High Speed Multimedia Card Interface support" - select DM_REGULATOR_PBIAS if DM_MMC && DM_REGULATOR - select DM_REGULATOR_PBIAS if DM_MMC && DM_REGULATOR + select DM_REGULATOR_PBIAS if DM_REGULATOR help This selects the TI OMAP High Speed Multimedia card Interface. If you have an omap2plus board with a Multimedia Card slot, @@ -430,7 +425,6 @@ config SH_MMCIF config MMC_UNIPHIER bool "UniPhier SD/MMC Host Controller support" depends on ARCH_UNIPHIER - depends on DM_MMC depends on OF_CONTROL help This selects support for the Matsushita SD/MMC Host Controller on @@ -439,7 +433,6 @@ config MMC_UNIPHIER config RENESAS_SDHI bool "Renesas R-Car SD/MMC Host Controller support" depends on ARCH_RENESAS - depends on DM_MMC depends on OF_CONTROL select BOUNCE_BUFFER help @@ -449,7 +442,6 @@ config RENESAS_SDHI config MMC_BCM2835 bool "BCM2835 family custom SD/MMC Host Controller support" depends on ARCH_BCM283X - depends on DM_MMC depends on OF_CONTROL default y help @@ -469,7 +461,7 @@ config JZ47XX_MMC config MMC_SANDBOX bool "Sandbox MMC support" depends on SANDBOX - depends on DM_MMC && OF_CONTROL + depends on OF_CONTROL help This select a dummy sandbox MMC driver. At present this does nothing other than allow sandbox to be build with MMC support. This @@ -559,7 +551,6 @@ config FIXED_SDHCI_ALIGNED_BUFFER config MMC_SDHCI_ASPEED bool "Aspeed SDHCI controller" depends on ARCH_ASPEED - depends on DM_MMC depends on MMC_SDHCI select MISC help @@ -571,7 +562,7 @@ config MMC_SDHCI_ASPEED config MMC_SDHCI_ATMEL bool "Atmel SDHCI controller support" depends on ARCH_AT91 - depends on DM_MMC && ARCH_AT91 + depends on ARCH_AT91 depends on MMC_SDHCI help This enables support for the Atmel SDHCI controller, which supports @@ -606,7 +597,6 @@ config MMC_SDHCI_BCMSTB config MMC_SDHCI_CADENCE bool "SDHCI support for the Cadence SD/SDIO/eMMC controller" - depends on DM_MMC depends on MMC_SDHCI depends on OF_CONTROL help @@ -618,7 +608,6 @@ config MMC_SDHCI_CADENCE config MMC_SDHCI_CV1800B bool "SDHCI support for the CV1800B SD/SDIO/eMMC controller" - depends on DM_MMC depends on MMC_SDHCI depends on OF_CONTROL help @@ -633,7 +622,7 @@ config MMC_SDHCI_AM654 bool "SDHCI Controller on TI's Am654 devices" depends on ARCH_K3 depends on MMC_SDHCI - depends on DM_MMC && OF_CONTROL && BLK + depends on OF_CONTROL depends on REGMAP select MMC_SDHCI_IO_ACCESSORS help @@ -653,7 +642,6 @@ config MMC_SDHCI_IPROC config MMC_SDHCI_F_SDH30 bool "SDHCI support for Fujitsu Semiconductor/Socionext F_SDH30" - depends on DM_MMC depends on MMC_SDHCI help This selects the Secure Digital Host Controller Interface (SDHCI) @@ -673,7 +661,6 @@ config MMC_SDHCI_KONA config MMC_SDHCI_MSM bool "Qualcomm SDHCI controller" - depends on DM_MMC depends on MMC_SDHCI help Enables support for SDHCI 2.0 controller present on some Qualcomm @@ -685,7 +672,6 @@ config MMC_SDHCI_MV bool "SDHCI support on Marvell platform" depends on ARCH_MVEBU depends on MMC_SDHCI - depends on DM_MMC help This selects the Secure Digital Host Controller Interface on Marvell platform. @@ -697,7 +683,6 @@ config MMC_SDHCI_MV config MMC_SDHCI_NPCM bool "SDHCI support on Nuvoton NPCM device" depends on MMC_SDHCI - depends on DM_MMC help This selects the Secure Digital Host Controller Interface (SDHCI) on Nuvoton NPCM device. @@ -708,7 +693,7 @@ config MMC_SDHCI_NPCM config MMC_SDHCI_PIC32 bool "Microchip PIC32 on-chip SDHCI support" - depends on DM_MMC && MACH_PIC32 + depends on MACH_PIC32 depends on MMC_SDHCI help Support for Microchip PIC32 SDHCI controller. @@ -716,7 +701,6 @@ config MMC_SDHCI_PIC32 config MMC_SDHCI_ROCKCHIP bool "Arasan SDHCI controller for Rockchip support" depends on ARCH_ROCKCHIP - depends on DM_MMC && BLK depends on MMC_SDHCI help Support for Arasan SDHCI host controller on Rockchip ARM SoCs platform @@ -735,7 +719,6 @@ config MMC_SDHCI_S5P config MMC_SDHCI_SNPS bool "Synopsys DesignWare SDHCI controller" depends on MMC_SDHCI - depends on DM_MMC help Support for DesignWare SDHCI host controller on Alibaba TH1520 SoC. This is a highly configurable and programmable, high performance @@ -753,7 +736,7 @@ config MMC_SDHCI_STI config MMC_SDHCI_XENON bool "SDHCI support for the Xenon SDHCI controller" - depends on MMC_SDHCI && DM_MMC && OF_CONTROL + depends on MMC_SDHCI && OF_CONTROL help Support for Xenon SDHCI host controller on Marvell Armada 3700 7k/8k ARM SoCs platforms @@ -764,7 +747,6 @@ config MMC_SDHCI_XENON config MMC_SDHCI_TANGIER bool "Tangier SDHCI controller support" - depends on DM_MMC && BLK depends on MMC_SDHCI help This selects support for SDHCI controller on Tanginer @@ -800,7 +782,7 @@ config TEGRA124_MMC_DISABLE_EXT_LOOPBACK config MMC_SDHCI_ZYNQ bool "Arasan SDHCI controller support" - depends on DM_MMC && OF_CONTROL && BLK + depends on OF_CONTROL depends on MMC_SDHCI help Support for Arasan SDHCI host controller on Zynq/ZynqMP ARM SoCs platform @@ -842,7 +824,6 @@ config MMC_SUNXI_HAS_MODE_SWITCH config MMC_PITON bool "MMC support for OpenPiton SoC" - depends on DM_MMC && BLK help This selects support for the SD host controller on OpenPiton SoC. Note that this SD controller directly exposes the contents of the @@ -851,7 +832,7 @@ config MMC_PITON config GENERIC_ATMEL_MCI bool "Atmel Multimedia Card Interface support" - depends on DM_MMC && ARCH_AT91 + depends on ARCH_AT91 help This enables support for Atmel High Speed Multimedia Card Interface (HSMCI), which supports the MultiMedia Card (MMC) Specification V4.3, @@ -860,7 +841,7 @@ config GENERIC_ATMEL_MCI config STM32_SDMMC2 bool "STMicroelectronics STM32H7 SD/MMC Host Controller support" - depends on DM_MMC && OF_CONTROL + depends on OF_CONTROL help This selects support for the SD/MMC controller on STM32H7 SoCs. If you have a board based on such a SoC and with a SD/MMC slot, @@ -880,7 +861,6 @@ config FTSDC010_SDIO config MMC_MTK bool "MediaTek SD/MMC Card Interface support" depends on ARCH_MEDIATEK || ARCH_MTMIPS - depends on DM_MMC depends on OF_CONTROL help This selects the MediaTek(R) Secure digital and Multimedia card Interface. @@ -911,7 +891,7 @@ config FSL_ESDHC_SUPPORT_ADMA2 config FSL_ESDHC_33V_IO_RELIABILITY_WORKAROUND bool "enable eSDHC workaround for 3.3v IO reliability issue" - depends on FSL_ESDHC && DM_MMC + depends on FSL_ESDHC help When eSDHC operates at 3.3v, damage can accumulate in an internal level shifter at a higher than expected rate. The faster the interface diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig index c71c1e5547c..185e8346213 100644 --- a/drivers/mtd/Kconfig +++ b/drivers/mtd/Kconfig @@ -34,7 +34,7 @@ config MTD_CONCAT config MTD_BLOCK bool "Enable block device access to MTD devices" - depends on BLK + select BLK help Enable support for block device access to MTD devices using blk_ops abstraction. diff --git a/drivers/mtd/ubi/Kconfig b/drivers/mtd/ubi/Kconfig index c027d898a64..ba77c034736 100644 --- a/drivers/mtd/ubi/Kconfig +++ b/drivers/mtd/ubi/Kconfig @@ -116,7 +116,7 @@ config MTD_UBI_FM_DEBUG config UBI_BLOCK bool "Enable UBI block device support" - depends on BLK + select BLK help Enable UBI block device support using blk_ops abstraction. diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 88ff025a37b..dcf6b4c81fc 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -1019,6 +1019,20 @@ config FSL_ENETC This driver supports the NXP ENETC Ethernet controller found on some of the NXP SoCs. +config FSL_ENETC_NETC_BLK_CTRL + bool "NXP ENETC NETC blocks control driver" + depends on FSL_ENETC && IMX95 + default y if IMX95 + help + This driver configures Integrated Endpoint Register Block (IERB) and + Privileged Register Block (PRB) of NETC. For i.MX platforms, it also + includes the configuration of NETCMIX block. + The IERB contains registers that are used for pre-boot initialization, + debug, and non-customer configuration. The PRB controls global reset + and global error handling for NETC. The NETCMIX block is mainly used + to set MII protocol and PCS protocol of the links, it also contains + settings for some other functions. + config MDIO_GPIO_BITBANG bool "GPIO bitbanging MDIO driver" depends on DM_MDIO && DM_GPIO diff --git a/drivers/net/Makefile b/drivers/net/Makefile index e51a917933e..c6217f08f14 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -44,6 +44,7 @@ obj-$(CONFIG_FEC_MXC) += fec_mxc.o obj-$(CONFIG_FMAN_ENET) += fm/ obj-$(CONFIG_FMAN_ENET) += fsl_mdio.o obj-$(CONFIG_FSL_ENETC) += fsl_enetc.o fsl_enetc_mdio.o +obj-$(CONFIG_FSL_ENETC_NETC_BLK_CTRL) += fsl_enetc_netc_blk_ctrl.o obj-$(CONFIG_FSL_LS_MDIO) += fsl_ls_mdio.o obj-$(CONFIG_FSL_MC_ENET) += fsl-mc/ obj-$(CONFIG_FSL_MC_ENET) += ldpaa_eth/ diff --git a/drivers/net/fsl_enetc.c b/drivers/net/fsl_enetc.c index a6b0bafc8c6..67ef5f34a8a 100644 --- a/drivers/net/fsl_enetc.c +++ b/drivers/net/fsl_enetc.c @@ -2,6 +2,7 @@ /* * ENETC ethernet controller driver * Copyright 2017-2021 NXP + * Copyright 2023-2025 NXP */ #include <dm.h> @@ -16,52 +17,267 @@ #include <miiphy.h> #include <linux/bug.h> #include <linux/delay.h> +#include <linux/build_bug.h> + +#ifdef CONFIG_ARCH_IMX9 +#include <asm/mach-imx/sys_proto.h> +#include <cpu_func.h> +#endif #include "fsl_enetc.h" #define ENETC_DRIVER_NAME "enetc_eth" +/* + * Calculate number of buffer descriptors per cacheline, and compile-time + * validate that: + * - the RX and TX descriptors are the same size + * - the descriptors fit exactly into cachelines without overlap + * - all descriptors fit exactly into cachelines + */ +#define ENETC_NUM_BD_IN_CL \ + ((ARCH_DMA_MINALIGN / sizeof(struct enetc_tx_bd)) + \ + BUILD_BUG_ON_ZERO(sizeof(struct enetc_tx_bd) != \ + sizeof(union enetc_rx_bd)) + \ + BUILD_BUG_ON_ZERO(ARCH_DMA_MINALIGN % sizeof(struct enetc_tx_bd)) + \ + BUILD_BUG_ON_ZERO(ARCH_DMA_MINALIGN % sizeof(union enetc_rx_bd)) + \ + BUILD_BUG_ON_ZERO(ENETC_BD_CNT % \ + (ARCH_DMA_MINALIGN / sizeof(struct enetc_tx_bd)))) + static int enetc_remove(struct udevice *dev); +static int enetc_is_imx95(struct udevice *dev) +{ + struct pci_child_plat *pplat = dev_get_parent_plat(dev); + + /* Test whether this is i.MX95 ENETCv4. This may be optimized out. */ + return IS_ENABLED(CONFIG_ARCH_IMX9) && + pplat->vendor == PCI_VENDOR_ID_PHILIPS; +} + +static int enetc_is_ls1028a(struct udevice *dev) +{ + struct pci_child_plat *pplat = dev_get_parent_plat(dev); + + /* Test whether this is LS1028A ENETC. This may be optimized out. */ + return IS_ENABLED(CONFIG_ARCH_LS1028A) && + pplat->vendor == PCI_VENDOR_ID_FREESCALE; +} + +static int enetc_dev_id(struct udevice *dev) +{ + if (enetc_is_imx95(dev)) + return PCI_DEV(pci_get_devfn(dev)) >> 3; + if (enetc_is_ls1028a(dev)) + return PCI_FUNC(pci_get_devfn(dev)); + + return 0; +} + +static void enetc_inval_rxbd(struct udevice *dev) +{ + struct enetc_priv *priv = dev_get_priv(dev); + union enetc_rx_bd *desc = &priv->enetc_rxbd[priv->rx_bdr.next_prod_idx]; + unsigned long start = rounddown((unsigned long)desc, ARCH_DMA_MINALIGN); + unsigned long end = roundup((unsigned long)desc + sizeof(*desc), + ARCH_DMA_MINALIGN); + + if (enetc_is_imx95(dev)) + invalidate_dcache_range(start, end); +} + +static void enetc_flush_bd(struct udevice *dev, int pi, bool tx) +{ + struct enetc_priv *priv = dev_get_priv(dev); + union enetc_rx_bd *rxdesc = &priv->enetc_rxbd[pi]; + struct enetc_tx_bd *txdesc = &priv->enetc_txbd[pi]; + unsigned long desc = tx ? (unsigned long)txdesc : (unsigned long)rxdesc; + unsigned long size = tx ? sizeof(*txdesc) : sizeof(*rxdesc); + unsigned long start = rounddown(desc, ARCH_DMA_MINALIGN); + unsigned long end = roundup(desc + size, ARCH_DMA_MINALIGN); + + if (enetc_is_imx95(dev)) + flush_dcache_range(start, end); +} + +static void enetc_inval_buffer(struct udevice *dev, void *buf, size_t size) +{ + unsigned long start = rounddown((unsigned long)buf, ARCH_DMA_MINALIGN); + unsigned long end = roundup((unsigned long)buf + size, + ARCH_DMA_MINALIGN); + + if (enetc_is_imx95(dev)) + invalidate_dcache_range(start, end); +} + +static void enetc_flush_buffer(struct udevice *dev, void *buf, size_t size) +{ + unsigned long start = rounddown((unsigned long)buf, ARCH_DMA_MINALIGN); + unsigned long end = roundup((unsigned long)buf + size, + ARCH_DMA_MINALIGN); + + if (enetc_is_imx95(dev)) + flush_dcache_range(start, end); +} + +/* register accessors */ +static u32 enetc_read_reg(void __iomem *addr) +{ + return readl(addr); +} + +static void enetc_write_reg(void __iomem *addr, u32 val) +{ + writel(val, addr); +} + +static void enetc_write(struct enetc_priv *priv, u32 off, u32 val) +{ + enetc_write_reg(priv->regs_base + off, val); +} + +/* base port register accessors */ +static void enetc_write_pmr(struct udevice *dev, u32 val) +{ + struct enetc_data *data = (struct enetc_data *)dev_get_driver_data(dev); + struct enetc_priv *priv = dev_get_priv(dev); + const u32 off = ENETC_PMR + data->reg_offset_pmr; + + enetc_write_reg(priv->port_regs + off, val); +} + +static void enetc_write_psipmar(struct udevice *dev, int n, u32 val) +{ + struct enetc_data *data = (struct enetc_data *)dev_get_driver_data(dev); + struct enetc_priv *priv = dev_get_priv(dev); + const u32 off = (n ? ENETC_PSIPMAR1 : ENETC_PSIPMAR0) + + data->reg_offset_psipmar; + + enetc_write_reg(priv->port_regs + off, val); +} + +/* port station register accessors */ +static void enetc_write_psicfgr(struct udevice *dev, int port, u32 val) +{ + struct enetc_data *data = (struct enetc_data *)dev_get_driver_data(dev); + struct enetc_priv *priv = dev_get_priv(dev); + const u32 off = ENETC_PSICFGR(port, ENETC_PSICFGR_SHIFT_LS) + + data->reg_offset_psicfgr; + + enetc_write_reg(priv->port_regs + off, val); +} + +/* port register accessors */ +static u32 enetc_read_pcapr_mdio(struct udevice *dev) +{ + struct enetc_data *data = (struct enetc_data *)dev_get_driver_data(dev); + struct enetc_priv *priv = dev_get_priv(dev); + const u32 off = ENETC_PCAPR0 + data->reg_offset_pcapr; + const u32 reg = enetc_read_reg(priv->port_regs + off); + + if (enetc_is_imx95(dev)) + return reg & ENETC_PCS_PROT; + else if (enetc_is_ls1028a(dev)) + return reg & ENETC_PCAPRO_MDIO; + + return 0; +} + +static void enetc_write_port(struct enetc_priv *priv, u32 off, u32 val) +{ + enetc_write_reg(priv->port_regs + off, val); +} + +/* MAC port register accessors */ +static u32 enetc_read_mac_port(struct udevice *dev, u32 off) +{ + struct enetc_data *data = (struct enetc_data *)dev_get_driver_data(dev); + struct enetc_priv *priv = dev_get_priv(dev); + + return enetc_read_reg(priv->port_regs + data->reg_offset_mac + off); +} + +static void enetc_write_mac_port(struct udevice *dev, u32 off, u32 val) +{ + struct enetc_data *data = (struct enetc_data *)dev_get_driver_data(dev); + struct enetc_priv *priv = dev_get_priv(dev); + + enetc_write_reg(priv->port_regs + data->reg_offset_mac + off, val); +} + +/* BDR register accessor, see also ENETC_BDR() */ +static void enetc_bdr_write(struct enetc_priv *priv, int type, int n, + u32 off, u32 val) +{ + enetc_write(priv, ENETC_BDR(type, n, off), val); +} + /* * sets the MAC address in IERB registers, this setting is persistent and * carried over to Linux. */ -static void enetc_set_ierb_primary_mac(struct udevice *dev, int devfn, - const u8 *enetaddr) -{ -#ifdef CONFIG_ARCH_LS1028A -/* - * LS1028A is the only part with IERB at this time and there are plans to change - * its structure, keep this LS1028A specific for now - */ #define IERB_BASE 0x1f0800000ULL #define IERB_PFMAC(pf, vf, n) (IERB_BASE + 0x8000 + (pf) * 0x100 + (vf) * 8 \ + (n) * 4) -static int ierb_fn_to_pf[] = {0, 1, 2, -1, -1, -1, 3}; - +static void enetc_set_ierb_primary_mac(struct udevice *dev, void *blob) +{ + static int ierb_fn_to_pf[] = { 0, 1, 2, -1, -1, -1, 3 }; + struct pci_child_plat *ppdata = dev_get_parent_plat(dev); + struct eth_pdata *pdata = dev_get_plat(dev); + struct enetc_priv *priv = dev_get_priv(dev); + const u8 *enetaddr = pdata->enetaddr; u16 lower = *(const u16 *)(enetaddr + 4); u32 upper = *(const u32 *)enetaddr; + int devfn, offset; + char path[256]; + + if (enetc_is_imx95(dev)) { + /* + * Configure the ENETC primary MAC addresses - Set register + * PMAR0/1 for SI 0 and PSIaPMAR0/1 for SI 1, 2 .. a + * (optionally pre-configured in IERB). + */ + devfn = enetc_dev_id(dev); + if (devfn > 2) + return; + + enetc_write(priv, IMX95_ENETC_SIPMAR0, upper); + enetc_write(priv, IMX95_ENETC_SIPMAR1, lower); + + snprintf(path, 256, "/soc/pcie@%x/ethernet@%x,%x", + PCI_BUS(dm_pci_get_bdf(dev)), PCI_DEV(ppdata->devfn), + PCI_FUNC(ppdata->devfn)); + } else if (enetc_is_ls1028a(dev)) { + /* + * LS1028A is the only part with IERB at this time and + * there are plans to change its structure, keep this + * LS1028A specific for now. + */ + devfn = PCI_FUNC(ppdata->devfn); + + if (ierb_fn_to_pf[devfn] < 0) + return; - if (ierb_fn_to_pf[devfn] < 0) + out_le32(IERB_PFMAC(ierb_fn_to_pf[devfn], 0, 0), upper); + out_le32(IERB_PFMAC(ierb_fn_to_pf[devfn], 0, 1), (u32)lower); + + snprintf(path, 256, "/soc/pcie@1f0000000/ethernet@%x,%x", + PCI_DEV(ppdata->devfn), PCI_FUNC(ppdata->devfn)); + } else { return; + } - out_le32(IERB_PFMAC(ierb_fn_to_pf[devfn], 0, 0), upper); - out_le32(IERB_PFMAC(ierb_fn_to_pf[devfn], 0, 1), (u32)lower); -#endif + offset = fdt_path_offset(blob, path); + if (offset >= 0) + fdt_setprop(blob, offset, "mac-address", pdata->enetaddr, 6); } /* sets up primary MAC addresses in DT/IERB */ void fdt_fixup_enetc_mac(void *blob) { - struct pci_child_plat *ppdata; - struct eth_pdata *pdata; struct udevice *dev; struct uclass *uc; - char path[256]; - int offset; - int devfn; uclass_get(UCLASS_ETH, &uc); uclass_foreach_dev(dev, uc) { @@ -69,18 +285,7 @@ void fdt_fixup_enetc_mac(void *blob) strcmp(dev->driver->name, ENETC_DRIVER_NAME)) continue; - pdata = dev_get_plat(dev); - ppdata = dev_get_parent_plat(dev); - devfn = PCI_FUNC(ppdata->devfn); - - enetc_set_ierb_primary_mac(dev, devfn, pdata->enetaddr); - - snprintf(path, 256, "/soc/pcie@1f0000000/ethernet@%x,%x", - PCI_DEV(ppdata->devfn), PCI_FUNC(ppdata->devfn)); - offset = fdt_path_offset(blob, path); - if (offset < 0) - continue; - fdt_setprop(blob, offset, "mac-address", pdata->enetaddr, 6); + enetc_set_ierb_primary_mac(dev, blob); } } @@ -101,7 +306,7 @@ static int enetc_bind(struct udevice *dev) * PCI function # and enetc#N based on interface count */ if (ofnode_valid(dev_ofnode(dev))) - sprintf(name, "enetc-%u", PCI_FUNC(pci_get_devfn(dev))); + sprintf(name, "enetc-%u", enetc_dev_id(dev)); else sprintf(name, "enetc#%u", eth_num_devices++); device_set_name(dev, name); @@ -181,10 +386,9 @@ static int enetc_init_sgmii(struct udevice *dev) /* set up MAC for RGMII */ static void enetc_init_rgmii(struct udevice *dev, struct phy_device *phydev) { - struct enetc_priv *priv = dev_get_priv(dev); - u32 old_val, val; + u32 old_val, val, dpx = 0; - old_val = val = enetc_read_port(priv, ENETC_PM_IF_MODE); + old_val = val = enetc_read_mac_port(dev, ENETC_PM_IF_MODE); /* disable unreliable RGMII in-band signaling and force the MAC into * the speed negotiated by the PHY. @@ -202,15 +406,20 @@ static void enetc_init_rgmii(struct udevice *dev, struct phy_device *phydev) val |= ENETC_PM_IFM_SSP_10; } + if (enetc_is_imx95(dev)) + dpx = ENETC_PM_IFM_FULL_DPX_IMX; + else if (enetc_is_ls1028a(dev)) + dpx = ENETC_PM_IFM_FULL_DPX_LS; + if (phydev->duplex == DUPLEX_FULL) - val |= ENETC_PM_IFM_FULL_DPX; + val |= dpx; else - val &= ~ENETC_PM_IFM_FULL_DPX; + val &= ~dpx; if (val == old_val) return; - enetc_write_port(priv, ENETC_PM_IF_MODE, val); + enetc_write_mac_port(dev, ENETC_PM_IF_MODE, val); } /* set up MAC configuration for the given interface type */ @@ -230,9 +439,12 @@ static void enetc_setup_mac_iface(struct udevice *dev, case PHY_INTERFACE_MODE_USXGMII: case PHY_INTERFACE_MODE_10GBASER: /* set ifmode to (US)XGMII */ - if_mode = enetc_read_port(priv, ENETC_PM_IF_MODE); - if_mode &= ~ENETC_PM_IF_IFMODE_MASK; - enetc_write_port(priv, ENETC_PM_IF_MODE, if_mode); + if_mode = enetc_read_mac_port(dev, ENETC_PM_IF_MODE); + if (enetc_is_imx95(dev)) + if_mode &= ~ENETC_PM_IF_IFMODE_MASK_IMX; + else if (enetc_is_ls1028a(dev)) + if_mode &= ~ENETC_PM_IF_IFMODE_MASK_LS; + enetc_write_mac_port(dev, ENETC_PM_IF_MODE, if_mode); break; }; } @@ -263,7 +475,7 @@ static void enetc_start_pcs(struct udevice *dev) struct enetc_priv *priv = dev_get_priv(dev); /* register internal MDIO for debug purposes */ - if (enetc_read_port(priv, ENETC_PCAPR0) & ENETC_PCAPRO_MDIO) { + if (enetc_read_pcapr_mdio(dev)) { priv->imdio.read = enetc_mdio_read; priv->imdio.write = enetc_mdio_write; priv->imdio.priv = priv->port_regs + ENETC_PM_IMDIO_BASE; @@ -375,6 +587,21 @@ static int enetc_remove(struct udevice *dev) return 0; } +static int enetc_imx95_write_hwaddr(struct udevice *dev) +{ + struct eth_pdata *plat = dev_get_plat(dev); + struct enetc_priv *priv = dev_get_priv(dev); + u8 *addr = plat->enetaddr; + + u16 lower = *(const u16 *)(addr + 4); + u32 upper = *(const u32 *)addr; + + enetc_write_port(priv, IMX95_ENETC_PMAR0, upper); + enetc_write_port(priv, IMX95_ENETC_PMAR1, lower); + + return 0; +} + /* * LS1028A is the only part with IERB at this time and there are plans to * change its structure, keep this LS1028A specific for now. @@ -413,39 +640,46 @@ static int enetc_ls1028a_write_hwaddr(struct udevice *dev) static int enetc_write_hwaddr(struct udevice *dev) { struct eth_pdata *plat = dev_get_plat(dev); - struct enetc_priv *priv = dev_get_priv(dev); u8 *addr = plat->enetaddr; - if (IS_ENABLED(CONFIG_ARCH_LS1028A)) + if (enetc_is_imx95(dev)) + return enetc_imx95_write_hwaddr(dev); + if (enetc_is_ls1028a(dev)) return enetc_ls1028a_write_hwaddr(dev); u16 lower = *(const u16 *)(addr + 4); u32 upper = *(const u32 *)addr; - enetc_write_port(priv, ENETC_PSIPMAR0, upper); - enetc_write_port(priv, ENETC_PSIPMAR1, lower); + enetc_write_psipmar(dev, 0, upper); + enetc_write_psipmar(dev, 1, lower); return 0; } /* Configure port parameters (# of rings, frame size, enable port) */ -static void enetc_enable_si_port(struct enetc_priv *priv) +static void enetc_enable_si_port(struct udevice *dev) { - u32 val; + struct enetc_priv *priv = dev_get_priv(dev); + u32 val = ENETC_PM_CC_TXP_IMX | ENETC_PM_CC_TX | ENETC_PM_CC_RX; /* set Rx/Tx BDR count */ - val = ENETC_PSICFGR_SET_TXBDR(ENETC_TX_BDR_CNT); - val |= ENETC_PSICFGR_SET_RXBDR(ENETC_RX_BDR_CNT); - enetc_write_port(priv, ENETC_PSICFGR(0), val); + enetc_write_psicfgr(dev, 0, ENETC_PSICFGR_SET_BDR(ENETC_RX_BDR_CNT, + ENETC_TX_BDR_CNT)); /* set Rx max frame size */ - enetc_write_port(priv, ENETC_PM_MAXFRM, ENETC_RX_MAXFRM_SIZE); + enetc_write_mac_port(dev, ENETC_PM_MAXFRM, ENETC_RX_MAXFRM_SIZE); /* enable MAC port */ - enetc_write_port(priv, ENETC_PM_CC, ENETC_PM_CC_RX_TX_EN); + if (enetc_is_ls1028a(dev)) + val |= ENETC_PM_CC_TXP_LS | ENETC_PM_CC_PROMIS; + enetc_write_mac_port(dev, ENETC_PM_CC, val); /* enable port */ - enetc_write_port(priv, ENETC_PMR, ENETC_PMR_SI0_EN); + if (enetc_is_imx95(dev)) + enetc_write_port(priv, ENETC_POR, 0x0); + enetc_write_pmr(dev, ENETC_PMR_SI0_EN); /* set SI cache policy */ - enetc_write(priv, ENETC_SICAR0, - ENETC_SICAR_RD_CFG | ENETC_SICAR_WR_CFG); + enetc_write(priv, ENETC_SICAR0, ENETC_SICAR_WR_CFG | + (enetc_is_imx95(dev) ? + ENETC_SICAR_RD_CFG_IMX : + ENETC_SICAR_RD_CFG_LS)); /* enable SI */ enetc_write(priv, ENETC_SIMR, ENETC_SIMR_EN); } @@ -536,6 +770,8 @@ static void enetc_setup_rx_bdr(struct udevice *dev) priv->enetc_rxbd[i].w.addr = enetc_rxb_address(dev, i); /* each RX buffer must be aligned to 64B */ WARN_ON(priv->enetc_rxbd[i].w.addr & (ARCH_DMA_MINALIGN - 1)); + + enetc_flush_bd(dev, i, false); } /* reset producer (ENETC owned) and consumer (SW owned) index */ @@ -556,6 +792,7 @@ static void enetc_setup_rx_bdr(struct udevice *dev) */ static int enetc_start(struct udevice *dev) { + int ret; struct enetc_priv *priv = dev_get_priv(dev); /* reset and enable the PCI device */ @@ -563,15 +800,19 @@ static int enetc_start(struct udevice *dev) dm_pci_clrset_config16(dev, PCI_COMMAND, 0, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); - enetc_enable_si_port(priv); + enetc_enable_si_port(dev); /* setup Tx/Rx buffer descriptors */ enetc_setup_tx_bdr(dev); enetc_setup_rx_bdr(dev); + ret = phy_startup(priv->phy); + if (ret) + return ret; + enetc_setup_mac_iface(dev, priv->phy); - return phy_startup(priv->phy); + return 0; } /* @@ -614,6 +855,8 @@ static int enetc_send(struct udevice *dev, void *packet, int length) enetc_dbg(dev, "TxBD[%d]send: pkt_len=%d, buff @0x%x%08x\n", pi, length, upper_32_bits((u64)nv_packet), lower_32_bits((u64)nv_packet)); + enetc_flush_buffer(dev, packet, length); + /* prepare Tx BD */ memset(&priv->enetc_txbd[pi], 0x0, sizeof(struct enetc_tx_bd)); priv->enetc_txbd[pi].addr = @@ -621,7 +864,10 @@ static int enetc_send(struct udevice *dev, void *packet, int length) priv->enetc_txbd[pi].buf_len = cpu_to_le16(length); priv->enetc_txbd[pi].frm_len = cpu_to_le16(length); priv->enetc_txbd[pi].flags = cpu_to_le16(ENETC_TXBD_FLAGS_F); + dmb(); + enetc_flush_bd(dev, pi, true); + /* send frame: increment producer index */ pi = (pi + 1) % txr->bd_count; txr->next_prod_idx = pi; @@ -643,15 +889,15 @@ static int enetc_recv(struct udevice *dev, int flags, uchar **packetp) { struct enetc_priv *priv = dev_get_priv(dev); struct bd_ring *rxr = &priv->rx_bdr; - int tries = ENETC_POLL_TRIES; int pi = rxr->next_prod_idx; - int ci = rxr->next_cons_idx; + int tries = ENETC_POLL_TRIES; u32 status; int len; u8 rdy; do { dmb(); + enetc_inval_rxbd(dev); status = le32_to_cpu(priv->enetc_rxbd[pi].r.lstatus); /* check if current BD is ready to be consumed */ rdy = ENETC_RXBD_STATUS_R(status); @@ -663,45 +909,142 @@ static int enetc_recv(struct udevice *dev, int flags, uchar **packetp) dmb(); len = le16_to_cpu(priv->enetc_rxbd[pi].r.buf_len); *packetp = (uchar *)enetc_rxb_address(dev, pi); + enetc_inval_buffer(dev, *packetp, len); enetc_dbg(dev, "RxBD[%d]: len=%d err=%d pkt=0x%x%08x\n", pi, len, ENETC_RXBD_STATUS_ERRORS(status), upper_32_bits((u64)*packetp), lower_32_bits((u64)*packetp)); - /* BD clean up and advance to next in ring */ - memset(&priv->enetc_rxbd[pi], 0, sizeof(union enetc_rx_bd)); - priv->enetc_rxbd[pi].w.addr = enetc_rxb_address(dev, pi); + return len; +} + +static int enetc_free_pkt(struct udevice *dev, uchar *packet, int length) +{ + const int bd_num_in_cl = enetc_is_imx95(dev) ? ENETC_NUM_BD_IN_CL : 1; + struct enetc_priv *priv = dev_get_priv(dev); + struct bd_ring *rxr = &priv->rx_bdr; + int pi = rxr->next_prod_idx; + int ci = rxr->next_cons_idx; + uchar *packet_expected; + int i; + + packet_expected = (uchar *)enetc_rxb_address(dev, pi); + if (packet != packet_expected) { + printf("%s: Unexpected packet (expected %p)\n", __func__, + packet_expected); + return -EINVAL; + } + rxr->next_prod_idx = (pi + 1) % rxr->bd_count; ci = (ci + 1) % rxr->bd_count; rxr->next_cons_idx = ci; dmb(); - /* free up the slot in the ring for HW */ - enetc_write_reg(rxr->cons_idx, ci); - return len; + if ((pi + 1) % bd_num_in_cl == 0) { + /* BD clean up and advance to next in ring */ + for (i = 0; i < bd_num_in_cl; i++) { + memset(&priv->enetc_rxbd[pi - i], 0, sizeof(union enetc_rx_bd)); + priv->enetc_rxbd[pi - i].w.addr = enetc_rxb_address(dev, pi - i); + } + + /* Will flush all bds in one cacheline */ + enetc_flush_bd(dev, pi - bd_num_in_cl + 1, false); + + /* free up the slot in the ring for HW */ + enetc_write_reg(rxr->cons_idx, ci); + } + + return 0; } -static const struct eth_ops enetc_ops = { +#if IS_ENABLED(CONFIG_ARCH_IMX9) +static int enetc_read_rom_hwaddr(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_plat(dev); + unsigned int dev_id = enetc_dev_id(dev); + unsigned char *mac = pdata->enetaddr; + + if (dev_id > 2) + return -EINVAL; + + imx_get_mac_from_fuse(dev_id, mac); + + return !is_valid_ethaddr(mac); +} + +static const struct eth_ops enetc_ops_imx = { + .start = enetc_start, + .send = enetc_send, + .recv = enetc_recv, + .stop = enetc_stop, + .free_pkt = enetc_free_pkt, + .write_hwaddr = enetc_write_hwaddr, + .read_rom_hwaddr = enetc_read_rom_hwaddr, +}; + +U_BOOT_DRIVER(eth_enetc_imx) = { + .name = ENETC_DRIVER_NAME, + .id = UCLASS_ETH, + .bind = enetc_bind, + .probe = enetc_probe, + .remove = enetc_remove, + .ops = &enetc_ops_imx, + .priv_auto = sizeof(struct enetc_priv), + .plat_auto = sizeof(struct eth_pdata), +}; + +static const struct enetc_data enetc_data_imx = { + .reg_offset_pmr = ENETC_PMR_OFFSET_IMX, + .reg_offset_psipmar = ENETC_PSIPMARn_OFFSET_IMX, + .reg_offset_pcapr = ENETC_PCAPR_OFFSET_IMX, + .reg_offset_psicfgr = ENETC_PSICFGR_OFFSET_IMX, + .reg_offset_mac = ENETC_PM_OFFSET_IMX, +}; + +static struct pci_device_id enetc_ids_imx[] = { + { + PCI_DEVICE(PCI_VENDOR_ID_PHILIPS, PCI_DEVICE_ID_ENETC4_ETH), + .driver_data = (ulong)&enetc_data_imx, + }, + {} +}; + +U_BOOT_PCI_DEVICE(eth_enetc_imx, enetc_ids_imx); +#endif + +static const struct eth_ops enetc_ops_ls = { .start = enetc_start, .send = enetc_send, .recv = enetc_recv, .stop = enetc_stop, + .free_pkt = enetc_free_pkt, .write_hwaddr = enetc_write_hwaddr, }; -U_BOOT_DRIVER(eth_enetc) = { +U_BOOT_DRIVER(eth_enetc_ls) = { .name = ENETC_DRIVER_NAME, .id = UCLASS_ETH, .bind = enetc_bind, .probe = enetc_probe, .remove = enetc_remove, - .ops = &enetc_ops, + .ops = &enetc_ops_ls, .priv_auto = sizeof(struct enetc_priv), .plat_auto = sizeof(struct eth_pdata), }; -static struct pci_device_id enetc_ids[] = { - { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, PCI_DEVICE_ID_ENETC_ETH) }, +static const struct enetc_data enetc_data_ls = { + .reg_offset_pmr = ENETC_PMR_OFFSET_LS, + .reg_offset_psipmar = ENETC_PSIPMARn_OFFSET_LS, + .reg_offset_pcapr = ENETC_PCAPR_OFFSET_LS, + .reg_offset_psicfgr = ENETC_PSICFGR_OFFSET_LS, + .reg_offset_mac = ENETC_PM_OFFSET_LS, +}; + +static struct pci_device_id enetc_ids_ls[] = { + { + PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, PCI_DEVICE_ID_ENETC_ETH), + .driver_data = (ulong)&enetc_data_ls, + }, {} }; -U_BOOT_PCI_DEVICE(eth_enetc, enetc_ids); +U_BOOT_PCI_DEVICE(eth_enetc_ls, enetc_ids_ls); diff --git a/drivers/net/fsl_enetc.h b/drivers/net/fsl_enetc.h index f2acf367aa3..804df853bf5 100644 --- a/drivers/net/fsl_enetc.h +++ b/drivers/net/fsl_enetc.h @@ -12,7 +12,9 @@ /* PCI function IDs */ #define PCI_DEVICE_ID_ENETC_ETH 0xE100 +#define PCI_DEVICE_ID_ENETC4_ETH 0xE101 #define PCI_DEVICE_ID_ENETC_MDIO 0xEE01 +#define PCI_DEVICE_ID_ENETC4_EMDIO 0xEE00 /* ENETC Ethernet controller registers */ /* Station interface register offsets */ @@ -22,7 +24,8 @@ /* write cache cfg: snoop, no allocate, data & BD coherent */ #define ENETC_SICAR_WR_CFG 0x6767 /* read cache cfg: coherent copy, look up, don't alloc in cache */ -#define ENETC_SICAR_RD_CFG 0x27270000 +#define ENETC_SICAR_RD_CFG_LS 0x27270000 +#define ENETC_SICAR_RD_CFG_IMX 0x2b2b0000 #define ENETC_SIROCT 0x300 #define ENETC_SIRFRM 0x308 #define ENETC_SITOCT 0x320 @@ -57,32 +60,60 @@ enum enetc_bdr_type {TX, RX}; #define ENETC_PORT_REGS_OFF 0x10000 /* Port registers */ +#define ENETC_PMR_OFFSET_IMX 0x0010 +#define ENETC_PMR_OFFSET_LS 0x0000 #define ENETC_PMR 0x0000 #define ENETC_PMR_SI0_EN BIT(16) #define ENETC_PSIPMMR 0x0018 -#define ENETC_PSIPMAR0 0x0100 -#define ENETC_PSIPMAR1 0x0104 -#define ENETC_PCAPR0 0x0900 -#define ENETC_PCAPRO_MDIO BIT(11) -#define ENETC_PSICFGR(n) (0x0940 + (n) * 0x10) -#define ENETC_PSICFGR_SET_TXBDR(val) ((val) & 0xff) -#define ENETC_PSICFGR_SET_RXBDR(val) (((val) & 0xff) << 16) +#define ENETC_PSIPMARn_OFFSET_IMX 0x0000 +#define ENETC_PSIPMARn_OFFSET_LS 0x0080 +#define ENETC_PSIPMAR0 0x0080 +#define ENETC_PSIPMAR1 0x0084 +#define ENETC_PCAPR_OFFSET_IMX 0x4008 +#define ENETC_PCAPR_OFFSET_LS 0x0900 +#define ENETC_PCAPR0 0x0000 +#define ENETC_PCAPRO_MDIO BIT(11) /* LS only */ +#define ENETC_PCS_PROT GENMASK(15, 0) /* IMX only */ +/* ENETC base registers */ +#define ENETC_PSICFGR_OFFSET_LS 0x0940 +#define ENETC_PSICFGR_SHIFT_LS 0x10 +#define ENETC_PSICFGR_OFFSET_IMX 0x2010 +#define ENETC_PSICFGR_SHIFT_IMX 0x80 +#define ENETC_PSICFGR(n, s) ((n) * (s)) +#define ENETC_PSICFGR_SET_BDR(rx, tx) (((rx) << 16) | (tx)) /* MAC configuration */ -#define ENETC_PM_CC 0x8008 +#define ENETC_PM_OFFSET_IMX 0x5000 +#define ENETC_PM_OFFSET_LS 0x8000 +#define ENETC_PM_CC 0x0008 #define ENETC_PM_CC_DEFAULT 0x0810 -#define ENETC_PM_CC_RX_TX_EN 0x8813 -#define ENETC_PM_MAXFRM 0x8014 +#define ENETC_PM_CC_TXP_IMX BIT(15) +#define ENETC_PM_CC_TXP_LS BIT(11) +#define ENETC_PM_CC_PROMIS BIT(4) +#define ENETC_PM_CC_TX BIT(1) +#define ENETC_PM_CC_RX BIT(0) +#define ENETC_PM_MAXFRM 0x0014 #define ENETC_RX_MAXFRM_SIZE PKTSIZE_ALIGN -#define ENETC_PM_IMDIO_BASE 0x8030 -#define ENETC_PM_IF_MODE 0x8300 +#define ENETC_PM_IMDIO_BASE 0x0030 +#define ENETC_PM_IF_MODE 0x0300 #define ENETC_PM_IF_MODE_RG BIT(2) #define ENETC_PM_IF_MODE_AN_ENA BIT(15) #define ENETC_PM_IFM_SSP_MASK GENMASK(14, 13) #define ENETC_PM_IFM_SSP_1000 (2 << 13) #define ENETC_PM_IFM_SSP_100 (0 << 13) #define ENETC_PM_IFM_SSP_10 (1 << 13) -#define ENETC_PM_IFM_FULL_DPX BIT(12) -#define ENETC_PM_IF_IFMODE_MASK GENMASK(1, 0) +#define ENETC_PM_IFM_FULL_DPX_IMX BIT(6) +#define ENETC_PM_IFM_FULL_DPX_LS BIT(12) +#define ENETC_PM_IF_IFMODE_MASK_IMX GENMASK(2, 0) +#define ENETC_PM_IF_IFMODE_MASK_LS GENMASK(1, 0) + +/* i.MX95 specific registers */ +#define IMX95_ENETC_SIPMAR0 0x80 +#define IMX95_ENETC_SIPMAR1 0x84 + +/* Port registers */ +#define IMX95_ENETC_PMAR0 0x4020 +#define IMX95_ENETC_PMAR1 0x4024 +#define ENETC_POR 0x4100 /* buffer descriptors count must be multiple of 8 and aligned to 128 bytes */ #define ENETC_BD_CNT CONFIG_SYS_RX_ETH_BUFFER @@ -163,25 +194,14 @@ struct enetc_priv { struct phy_device *phy; }; -/* register accessors */ -#define enetc_read_reg(x) readl((x)) -#define enetc_write_reg(x, val) writel((val), (x)) -#define enetc_read(priv, off) enetc_read_reg((priv)->regs_base + (off)) -#define enetc_write(priv, off, v) \ - enetc_write_reg((priv)->regs_base + (off), v) - -/* port register accessors */ -#define enetc_port_regs(priv, off) ((priv)->port_regs + (off)) -#define enetc_read_port(priv, off) \ - enetc_read_reg(enetc_port_regs((priv), (off))) -#define enetc_write_port(priv, off, v) \ - enetc_write_reg(enetc_port_regs((priv), (off)), v) - -/* BDR register accessors, see ENETC_BDR() */ -#define enetc_bdr_read(priv, t, n, off) \ - enetc_read(priv, ENETC_BDR(t, n, off)) -#define enetc_bdr_write(priv, t, n, off, val) \ - enetc_write(priv, ENETC_BDR(t, n, off), val) +struct enetc_data { + /* Register layout offsets */ + u16 reg_offset_pmr; + u16 reg_offset_psipmar; + u16 reg_offset_pcapr; + u16 reg_offset_psicfgr; + u16 reg_offset_mac; +}; /* PCS / internal SoC PHY ID, it defaults to 0 on all interfaces */ #define ENETC_PCS_PHY_ADDR 0 diff --git a/drivers/net/fsl_enetc_mdio.c b/drivers/net/fsl_enetc_mdio.c index 2d5fcbb6dbd..c1d491f2c5a 100644 --- a/drivers/net/fsl_enetc_mdio.c +++ b/drivers/net/fsl_enetc_mdio.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * ENETC ethernet controller driver - * Copyright 2019 NXP + * Copyright 2019-2025 NXP */ #include <dm.h> @@ -14,6 +14,16 @@ #include "fsl_enetc.h" +static u32 enetc_read(struct enetc_mdio_priv *priv, u32 off) +{ + return readl(priv->regs_base + off); +} + +static void enetc_write(struct enetc_mdio_priv *priv, u32 off, u32 val) +{ + writel(val, priv->regs_base + off); +} + static void enetc_mdio_wait_bsy(struct enetc_mdio_priv *priv) { int to = 10000; @@ -122,7 +132,9 @@ static int enetc_mdio_bind(struct udevice *dev) static int enetc_mdio_probe(struct udevice *dev) { + struct pci_child_plat *pplat = dev_get_parent_plat(dev); struct enetc_mdio_priv *priv = dev_get_priv(dev); + u16 cmd = PCI_COMMAND_MEMORY; priv->regs_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_TYPE, 0); if (!priv->regs_base) { @@ -132,7 +144,10 @@ static int enetc_mdio_probe(struct udevice *dev) priv->regs_base += ENETC_MDIO_BASE; - dm_pci_clrset_config16(dev, PCI_COMMAND, 0, PCI_COMMAND_MEMORY); + if (pplat->vendor == PCI_VENDOR_ID_PHILIPS) /* i.MX95 */ + cmd |= PCI_COMMAND_MASTER; + + dm_pci_clrset_config16(dev, PCI_COMMAND, 0, cmd); return 0; } @@ -148,6 +163,7 @@ U_BOOT_DRIVER(enetc_mdio) = { static struct pci_device_id enetc_mdio_ids[] = { { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, PCI_DEVICE_ID_ENETC_MDIO) }, + { PCI_DEVICE(PCI_VENDOR_ID_PHILIPS, PCI_DEVICE_ID_ENETC4_EMDIO) }, { } }; diff --git a/drivers/net/fsl_enetc_netc_blk_ctrl.c b/drivers/net/fsl_enetc_netc_blk_ctrl.c new file mode 100644 index 00000000000..46b68d3d8a4 --- /dev/null +++ b/drivers/net/fsl_enetc_netc_blk_ctrl.c @@ -0,0 +1,346 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * NXP NETC Blocks Control Driver + * + * Copyright 2024 NXP + * + * This driver is used for pre-initialization of NETC, such as PCS and MII + * protocols, LDID, warm reset, etc. Therefore, all NETC device drivers can + * only be probed after the netc-blk-crtl driver has completed initialization. + * In addition, when the system enters suspend mode, IERB, PRB, and NETCMIX + * will be powered off, except for WOL. Therefore, when the system resumes, + * these blocks need to be reinitialized. + */ + +#include <asm/io.h> +#include <clk.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <linux/bitfield.h> +#include <linux/delay.h> +#include <linux/errno.h> +#include <linux/iopoll.h> +#include <phy_interface.h> + +/* NETCMIX registers */ +#define IMX95_CFG_LINK_IO_VAR 0x0 +#define IO_VAR_16FF_16G_SERDES 0x1 +#define IO_VAR(port, var) (((var) & 0xf) << ((port) << 2)) + +#define IMX95_CFG_LINK_MII_PROT 0x4 +#define CFG_LINK_MII_PORT_0 GENMASK(3, 0) +#define CFG_LINK_MII_PORT_1 GENMASK(7, 4) +#define MII_PROT_MII 0x0 +#define MII_PROT_RMII 0x1 +#define MII_PROT_RGMII 0x2 +#define MII_PROT_SERIAL 0x3 +#define MII_PROT(port, prot) (((prot) & 0xf) << ((port) << 2)) + +#define IMX95_CFG_LINK_PCS_PROT(a) (0x8 + (a) * 4) +#define PCS_PROT_1G_SGMII BIT(0) +#define PCS_PROT_2500M_SGMII BIT(1) +#define PCS_PROT_XFI BIT(3) +#define PCS_PROT_SFI BIT(4) +#define PCS_PROT_10G_SXGMII BIT(6) + +/* NETC privileged register block register */ +#define PRB_NETCRR 0x100 +#define NETCRR_SR BIT(0) +#define NETCRR_LOCK BIT(1) + +#define PRB_NETCSR 0x104 +#define NETCSR_ERROR BIT(0) +#define NETCSR_STATE BIT(1) + +/* NETC integrated endpoint register block register */ +#define IERB_EMDIOFAUXR 0x344 +#define IERB_T0FAUXR 0x444 +#define IERB_EFAUXR(a) (0x3044 + 0x100 * (a)) +#define IERB_VFAUXR(a) (0x4004 + 0x40 * (a)) +#define FAUXR_LDID GENMASK(3, 0) + +/* Platform information */ +#define IMX95_ENETC0_BUS_DEVFN 0x0 +#define IMX95_ENETC1_BUS_DEVFN 0x40 +#define IMX95_ENETC2_BUS_DEVFN 0x80 + +/* Flags for different platforms */ +#define NETC_HAS_NETCMIX BIT(0) + +struct netc_blk_ctrl { + void __iomem *prb; + void __iomem *ierb; + void __iomem *netcmix; +}; + +static void netc_reg_write(void __iomem *base, u32 offset, u32 val) +{ + writel(val, base + offset); +} + +static u32 netc_reg_read(void __iomem *base, u32 offset) +{ + return readl(base + offset); +} + +static int netc_of_pci_get_bus_devfn(ofnode node) +{ + u32 reg[5]; + int error; + + error = ofnode_read_u32_array(node, "reg", reg, ARRAY_SIZE(reg)); + if (error) + return error; + + return (reg[0] >> 8) & 0xffff; +} + +static int netc_get_link_mii_protocol(phy_interface_t interface) +{ + switch (interface) { + case PHY_INTERFACE_MODE_MII: + return MII_PROT_MII; + case PHY_INTERFACE_MODE_RMII: + return MII_PROT_RMII; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + return MII_PROT_RGMII; + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_2500BASEX: + case PHY_INTERFACE_MODE_10GBASER: + case PHY_INTERFACE_MODE_XGMII: + case PHY_INTERFACE_MODE_USXGMII: + return MII_PROT_SERIAL; + default: + return -EINVAL; + } +} + +static int imx95_netcmix_init(struct udevice *dev) +{ + struct netc_blk_ctrl *priv = dev_get_priv(dev); + ofnode child, gchild; + phy_interface_t interface; + int bus_devfn, mii_proto; + u32 val; + + /* Default setting of MII protocol */ + val = MII_PROT(0, MII_PROT_RGMII) | MII_PROT(1, MII_PROT_RGMII) | + MII_PROT(2, MII_PROT_SERIAL); + + /* Update the link MII protocol through parsing phy-mode */ + dev_for_each_subnode(child, dev) { + if (!ofnode_is_enabled(child)) + continue; + + ofnode_for_each_subnode(gchild, child) { + if (!ofnode_is_enabled(gchild)) + continue; + + if (!ofnode_device_is_compatible(gchild, "pci1131,e101")) + continue; + + bus_devfn = netc_of_pci_get_bus_devfn(gchild); + if (bus_devfn < 0) + return -EINVAL; + + if (bus_devfn == IMX95_ENETC2_BUS_DEVFN) + continue; + + interface = ofnode_read_phy_mode(gchild); + if (interface == -1) + continue; + + mii_proto = netc_get_link_mii_protocol(interface); + if (mii_proto < 0) + return -EINVAL; + + switch (bus_devfn) { + case IMX95_ENETC0_BUS_DEVFN: + val &= ~CFG_LINK_MII_PORT_0; + val |= FIELD_PREP(CFG_LINK_MII_PORT_0, mii_proto); + break; + case IMX95_ENETC1_BUS_DEVFN: + val &= ~CFG_LINK_MII_PORT_1; + val |= FIELD_PREP(CFG_LINK_MII_PORT_1, mii_proto); + break; + default: + return -EINVAL; + } + } + } + + /* Configure Link I/O variant */ + netc_reg_write(priv->netcmix, IMX95_CFG_LINK_IO_VAR, + IO_VAR(2, IO_VAR_16FF_16G_SERDES)); + /* Configure Link 2 PCS protocol */ + netc_reg_write(priv->netcmix, IMX95_CFG_LINK_PCS_PROT(2), + PCS_PROT_10G_SXGMII); + netc_reg_write(priv->netcmix, IMX95_CFG_LINK_MII_PROT, val); + + return 0; +} + +static bool netc_ierb_is_locked(struct netc_blk_ctrl *priv) +{ + return !!(netc_reg_read(priv->prb, PRB_NETCRR) & NETCRR_LOCK); +} + +static int netc_lock_ierb(struct netc_blk_ctrl *priv) +{ + u32 val; + + netc_reg_write(priv->prb, PRB_NETCRR, NETCRR_LOCK); + + return readl_poll_timeout(priv->prb + PRB_NETCSR, val, + !(val & NETCSR_STATE), 2000); +} + +static int netc_unlock_ierb_with_warm_reset(struct netc_blk_ctrl *priv) +{ + u32 val; + + netc_reg_write(priv->prb, PRB_NETCRR, 0); + + return readl_poll_timeout(priv->prb + PRB_NETCRR, val, + !(val & NETCRR_LOCK), 100000); +} + +static int imx95_ierb_init(struct udevice *dev) +{ + struct netc_blk_ctrl *priv = dev_get_priv(dev); + + /* EMDIO : No MSI-X intterupt */ + netc_reg_write(priv->ierb, IERB_EMDIOFAUXR, 0); + /* ENETC0 PF */ + netc_reg_write(priv->ierb, IERB_EFAUXR(0), 0); + /* ENETC0 VF0 */ + netc_reg_write(priv->ierb, IERB_VFAUXR(0), 1); + /* ENETC0 VF1 */ + netc_reg_write(priv->ierb, IERB_VFAUXR(1), 2); + /* ENETC1 PF */ + netc_reg_write(priv->ierb, IERB_EFAUXR(1), 3); + /* ENETC1 VF0 */ + netc_reg_write(priv->ierb, IERB_VFAUXR(2), 5); + /* ENETC1 VF1 */ + netc_reg_write(priv->ierb, IERB_VFAUXR(3), 6); + /* ENETC2 PF */ + netc_reg_write(priv->ierb, IERB_EFAUXR(2), 4); + /* ENETC2 VF0 */ + netc_reg_write(priv->ierb, IERB_VFAUXR(4), 5); + /* ENETC2 VF1 */ + netc_reg_write(priv->ierb, IERB_VFAUXR(5), 6); + /* NETC TIMER */ + netc_reg_write(priv->ierb, IERB_T0FAUXR, 7); + + return 0; +} + +static int netc_ierb_init(struct udevice *dev) +{ + struct netc_blk_ctrl *priv = dev_get_priv(dev); + int err; + + if (netc_ierb_is_locked(priv)) { + err = netc_unlock_ierb_with_warm_reset(priv); + if (err) { + dev_err(dev, "Unlock IERB failed.\n"); + return err; + } + } + + err = imx95_ierb_init(dev); + if (err) + return err; + + err = netc_lock_ierb(priv); + if (err) { + dev_err(dev, "Lock IERB failed.\n"); + return err; + } + + return 0; +} + +static int netc_prb_check_error(struct netc_blk_ctrl *priv) +{ + if (netc_reg_read(priv->prb, PRB_NETCSR) & NETCSR_ERROR) + return -1; + + return 0; +} + +static const struct udevice_id netc_blk_ctrl_match[] = { + { .compatible = "nxp,imx95-netc-blk-ctrl" }, + {}, +}; + +static int netc_blk_ctrl_probe(struct udevice *dev) +{ + struct netc_blk_ctrl *priv = dev_get_priv(dev); + struct clk *ipg_clk; + fdt_addr_t regs; + int err; + + ipg_clk = devm_clk_get_optional(dev, "ipg"); + if (IS_ERR(ipg_clk)) { + dev_err(dev, "Set ipg clock failed\n"); + return PTR_ERR(ipg_clk); + } + + err = clk_prepare_enable(ipg_clk); + if (err) { + dev_err(dev, "Enable ipg clock failed\n"); + return PTR_ERR(ipg_clk); + } + + regs = dev_read_addr_name(dev, "ierb"); + if (regs == FDT_ADDR_T_NONE) { + dev_err(dev, "Missing IERB resource\n"); + return -EINVAL; + } + + priv->ierb = (void __iomem *)regs; + regs = dev_read_addr_name(dev, "prb"); + if (regs == FDT_ADDR_T_NONE) { + dev_err(dev, "Missing PRB resource\n"); + return -EINVAL; + } + + priv->prb = (void __iomem *)regs; + regs = dev_read_addr_name(dev, "netcmix"); + if (regs == FDT_ADDR_T_NONE) { + dev_err(dev, "Missing NETCMIX resource\n"); + return -EINVAL; + } + + priv->netcmix = (void __iomem *)regs; + + err = imx95_netcmix_init(dev); + if (err) { + dev_err(dev, "Initializing NETCMIX failed\n"); + return err; + } + + err = netc_ierb_init(dev); + if (err) { + dev_err(dev, "Initializing IERB failed\n"); + return err; + } + + if (netc_prb_check_error(priv) < 0) + dev_warn(dev, "The current IERB configuration is invalid\n"); + + return 0; +} + +U_BOOT_DRIVER(netc_blk_ctrl_drv) = { + .name = "netc_blk_ctrl", + .id = UCLASS_SIMPLE_BUS, + .of_match = netc_blk_ctrl_match, + .probe = netc_blk_ctrl_probe, + .priv_auto = sizeof(struct netc_blk_ctrl), + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/nvme/Kconfig b/drivers/nvme/Kconfig index 73edb355160..d138867666b 100644 --- a/drivers/nvme/Kconfig +++ b/drivers/nvme/Kconfig @@ -4,6 +4,7 @@ config NVME bool "NVM Express device support" + select BLK help This option enables support for NVM Express devices. It supports basic functions of NVMe (read/write). diff --git a/drivers/pinctrl/nxp/pinctrl-imx.c b/drivers/pinctrl/nxp/pinctrl-imx.c index b1960c56b51..54cec37327c 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx.c +++ b/drivers/pinctrl/nxp/pinctrl-imx.c @@ -219,7 +219,7 @@ int imx_pinctrl_probe(struct udevice *dev, if (info->flags & IMX8_USE_SCU) return 0; - addr = ofnode_get_addr_size_index(dev_ofnode(dev), 0, &size); + addr = ofnode_get_addr_size_index(node, 0, &size); if (addr == FDT_ADDR_T_NONE) return -EINVAL; @@ -228,7 +228,7 @@ int imx_pinctrl_probe(struct udevice *dev, return -ENOMEM; priv->info = info; - info->mux_mask = ofnode_read_u32(node, "fsl,mux_mask", 0); + info->mux_mask = ofnode_read_u32_default(node, "fsl,mux_mask", 0); /* * Refer to linux documentation for details: * Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt diff --git a/drivers/power/pmic/tps65941.c b/drivers/power/pmic/tps65941.c index c3490db2a08..57d470521fc 100644 --- a/drivers/power/pmic/tps65941.c +++ b/drivers/power/pmic/tps65941.c @@ -74,7 +74,7 @@ static const struct udevice_id tps65941_ids[] = { { .compatible = "ti,tps659412", .data = TPS659411 }, { .compatible = "ti,tps659413", .data = TPS659413 }, { .compatible = "ti,lp876441", .data = LP876441 }, - { .compatible = "ti,tps65224", .data = TPS65224 }, + { .compatible = "ti,tps65224-q1", .data = TPS65224 }, { .compatible = "ti,tps6594-q1", .data = TPS659411 }, { .compatible = "ti,tps6593-q1", .data = TPS659413 }, { .compatible = "ti,lp8764-q1", .data = LP876441 }, diff --git a/drivers/power/regulator/tps65219_regulator.c b/drivers/power/regulator/tps65219_regulator.c index b7124fed024..88abc896b3a 100644 --- a/drivers/power/regulator/tps65219_regulator.c +++ b/drivers/power/regulator/tps65219_regulator.c @@ -72,12 +72,12 @@ static int tps65219_buck_enable(struct udevice *dev, int op, bool *enable) static int tps65219_buck_volt2val(int uV) { - if (uV > TPS65219_BUCK_VOLT_MAX) + if (uV > TPS65219_BUCK_3V4) return -EINVAL; - else if (uV >= 1400000) - return (uV - 1400000) / 100000 + 0x20; - else if (uV >= 600000) - return (uV - 600000) / 25000 + 0x00; + else if (uV >= TPS65219_BUCK_1V4) + return (uV - TPS65219_BUCK_1V4) / TPS65219_VOLT_STEP_100MV + TPS65219_BUCK_REG_1V4; + else if (uV >= TPS65219_BUCK_0V6) + return (uV - TPS65219_BUCK_0V6) / TPS65219_VOLT_STEP_25MV + TPS65219_BUCK_REG_0V6; else return -EINVAL; } @@ -86,12 +86,12 @@ static int tps65219_buck_val2volt(int val) { if (val > TPS65219_VOLT_MASK) return -EINVAL; - else if (val > 0x34) - return TPS65219_BUCK_VOLT_MAX; - else if (val > 0x20) - return 1400000 + (val - 0x20) * 100000; - else if (val >= 0) - return 600000 + val * 25000; + else if (val > TPS65219_BUCK_REG_3V4) + return TPS65219_BUCK_3V4; + else if (val > TPS65219_BUCK_REG_1V4) + return TPS65219_BUCK_1V4 + (val - TPS65219_BUCK_REG_1V4) * TPS65219_VOLT_STEP_100MV; + else if (val >= TPS65219_BUCK_REG_0V6) + return TPS65219_BUCK_0V6 + val * TPS65219_VOLT_STEP_25MV; else return -EINVAL; } @@ -161,7 +161,7 @@ static int tps65219_ldo_volt2val(int idx, int uV) if (uV > max) return -EINVAL; else if (uV >= base) - return (uV - TPS65219_LDO12_VOLT_MIN) / 50000; + return (uV - TPS65219_LDO12_VOLT_MIN) / TPS65219_VOLT_STEP_50MV; else return -EINVAL; } @@ -187,7 +187,7 @@ static int tps65219_ldo_val2volt(int idx, int val) else if (val <= reg_base) return base; else if (val >= 0) - return TPS65219_LDO12_VOLT_MIN + (50000 * val); + return TPS65219_LDO12_VOLT_MIN + (TPS65219_VOLT_STEP_50MV * val); else return -EINVAL; } @@ -250,7 +250,7 @@ static int tps65219_ldo_probe(struct udevice *dev) /* idx must be in 1..TPS65219_LDO_NUM */ idx = dev->driver_data; if (idx < 1 || idx > TPS65219_LDO_NUM) { - printf("Wrong ID for regulator\n"); + pr_err("Wrong ID for regulator\n"); return -EINVAL; } @@ -271,7 +271,7 @@ static int tps65219_buck_probe(struct udevice *dev) /* idx must be in 1..TPS65219_BUCK_NUM */ idx = dev->driver_data; if (idx < 1 || idx > TPS65219_BUCK_NUM) { - printf("Wrong ID for regulator\n"); + pr_err("Wrong ID for regulator\n"); return -EINVAL; } diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig index 2b0cd312883..899d7585489 100644 --- a/drivers/ram/Kconfig +++ b/drivers/ram/Kconfig @@ -116,6 +116,16 @@ config IMXRT_SDRAM to support external memories like sdram, psram & nand. This driver is for the sdram memory interface with the SEMC. +config K3_INLINE_ECC + bool "Enable TI Inline ECC support" + depends on K3_DDRSS + help + Enable Inline ECC support on K3 platforms. 1/9th of the SDRAM space + is used for ECC storage and the rest 8/9th is available for system + use. Enabling ECC increases boot time as the ECC protected regions + need to be primed with a predefined value prior to enabling ECC + check. + source "drivers/ram/aspeed/Kconfig" source "drivers/ram/cadence/Kconfig" source "drivers/ram/octeon/Kconfig" diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c b/drivers/ram/k3-ddrss/k3-ddrss.c index 6e9202b9579..05ea61bbfe9 100644 --- a/drivers/ram/k3-ddrss/k3-ddrss.c +++ b/drivers/ram/k3-ddrss/k3-ddrss.c @@ -6,6 +6,7 @@ */ #include <config.h> +#include <time.h> #include <clk.h> #include <div64.h> #include <dm.h> @@ -44,6 +45,11 @@ #define DDRSS_ECC_R2_STR_ADDR_REG 0x0140 #define DDRSS_ECC_R2_END_ADDR_REG 0x0144 #define DDRSS_ECC_1B_ERR_CNT_REG 0x0150 +#define DDRSS_V2A_INT_SET_REG 0x00a8 + +#define DDRSS_V2A_INT_SET_REG_ECC1BERR_EN BIT(3) +#define DDRSS_V2A_INT_SET_REG_ECC2BERR_EN BIT(4) +#define DDRSS_V2A_INT_SET_REG_ECCM1BERR_EN BIT(5) #define SINGLE_DDR_SUBSYSTEM 0x1 #define MULTI_DDR_SUBSYSTEM 0x2 @@ -120,8 +126,8 @@ struct k3_msmc { #define K3_DDRSS_MAX_ECC_REGIONS 3 struct k3_ddrss_ecc_region { - u32 start; - u32 range; + u64 start; + u64 range; }; struct k3_ddrss_desc { @@ -145,7 +151,9 @@ struct k3_ddrss_desc { lpddr4_privatedata pd; struct k3_ddrss_ecc_region ecc_regions[K3_DDRSS_MAX_ECC_REGIONS]; u64 ecc_reserved_space; - bool ti_ecc_enabled; + u64 ddr_bank_base[CONFIG_NR_DRAM_BANKS]; + u64 ddr_bank_size[CONFIG_NR_DRAM_BANKS]; + u64 ddr_ram_size; }; struct reginitdata { @@ -399,8 +407,6 @@ static int k3_ddrss_ofdata_to_priv(struct udevice *dev) if (ret) dev_err(dev, "ddr fhs cnt not populated %d\n", ret); - ddrss->ti_ecc_enabled = dev_read_bool(dev, "ti,ecc-enable"); - return ret; } @@ -542,27 +548,174 @@ void k3_lpddr4_start(struct k3_ddrss_desc *ddrss) } } -static void k3_ddrss_set_ecc_range_r0(u32 base, u32 start_address, u32 size) +static void k3_ddrss_set_ecc_range_r0(u32 base, u64 start_address, u64 size) { writel((start_address) >> 16, base + DDRSS_ECC_R0_STR_ADDR_REG); writel((start_address + size - 1) >> 16, base + DDRSS_ECC_R0_END_ADDR_REG); } -static void k3_ddrss_preload_ecc_mem_region(u32 *addr, u32 size, u32 word) +#define BIST_MODE_MEM_INIT 4 +#define BIST_MEM_INIT_TIMEOUT 10000 /* 1msec loops per block = 10s */ +static void k3_lpddr4_bist_init_mem_region(struct k3_ddrss_desc *ddrss, + u64 addr, u64 size, + u32 pattern) { - int i; + lpddr4_obj *driverdt = ddrss->driverdt; + lpddr4_privatedata *pd = &ddrss->pd; + u32 status, offset, regval; + bool int_status; + int i = 0; + + /* Set BIST_START_ADDR_0 [31:0] */ + regval = (u32)(addr & TH_FLD_MASK(LPDDR4__BIST_START_ADDRESS_0__FLD)); + TH_OFFSET_FROM_REG(LPDDR4__BIST_START_ADDRESS_0__REG, CTL_SHIFT, offset); + driverdt->writereg(pd, LPDDR4_CTL_REGS, offset, regval); + + /* Set BIST_START_ADDR_1 [32 or 34:32] */ + regval = (u32)(addr >> TH_FLD_WIDTH(LPDDR4__BIST_START_ADDRESS_0__FLD)); + regval &= TH_FLD_MASK(LPDDR4__BIST_START_ADDRESS_1__FLD); + TH_OFFSET_FROM_REG(LPDDR4__BIST_START_ADDRESS_1__REG, CTL_SHIFT, offset); + driverdt->writereg(pd, LPDDR4_CTL_REGS, offset, regval); + + /* Set ADDR_SPACE = log2(size) */ + regval = (u32)(ilog2(size) << TH_FLD_SHIFT(LPDDR4__ADDR_SPACE__FLD)); + TH_OFFSET_FROM_REG(LPDDR4__ADDR_SPACE__REG, CTL_SHIFT, offset); + driverdt->writereg(pd, LPDDR4_CTL_REGS, offset, regval); + + /* Enable the BIST data check. On 32bit lpddr4 (e.g J7) this shares a + * register with ADDR_SPACE and BIST_GO. + */ + TH_OFFSET_FROM_REG(LPDDR4__BIST_DATA_CHECK__REG, CTL_SHIFT, offset); + driverdt->readreg(pd, LPDDR4_CTL_REGS, offset, ®val); + regval |= TH_FLD_MASK(LPDDR4__BIST_DATA_CHECK__FLD); + driverdt->writereg(pd, LPDDR4_CTL_REGS, offset, regval); + /* Clear the address check bit */ + TH_OFFSET_FROM_REG(LPDDR4__BIST_ADDR_CHECK__REG, CTL_SHIFT, offset); + driverdt->readreg(pd, LPDDR4_CTL_REGS, offset, ®val); + regval &= ~TH_FLD_MASK(LPDDR4__BIST_ADDR_CHECK__FLD); + driverdt->writereg(pd, LPDDR4_CTL_REGS, offset, regval); + + /* Set BIST_TEST_MODE[2:0] to memory initialize (4) */ + regval = BIST_MODE_MEM_INIT; + TH_OFFSET_FROM_REG(LPDDR4__BIST_TEST_MODE__REG, CTL_SHIFT, offset); + driverdt->writereg(pd, LPDDR4_CTL_REGS, offset, regval); + + /* Set BIST_DATA_PATTERN[31:0] */ + TH_OFFSET_FROM_REG(LPDDR4__BIST_DATA_PATTERN_0__REG, CTL_SHIFT, offset); + driverdt->writereg(pd, LPDDR4_CTL_REGS, offset, pattern); + + /* Set BIST_DATA_PATTERN[63:32] */ + TH_OFFSET_FROM_REG(LPDDR4__BIST_DATA_PATTERN_1__REG, CTL_SHIFT, offset); + driverdt->writereg(pd, LPDDR4_CTL_REGS, offset, pattern); + + udelay(1000); + + /* Enable the programmed BIST operation - BIST_GO = 1 */ + TH_OFFSET_FROM_REG(LPDDR4__BIST_GO__REG, CTL_SHIFT, offset); + driverdt->readreg(pd, LPDDR4_CTL_REGS, offset, ®val); + regval |= TH_FLD_MASK(LPDDR4__BIST_GO__FLD); + driverdt->writereg(pd, LPDDR4_CTL_REGS, offset, regval); + + /* Wait for the BIST_DONE interrupt */ + while (i < BIST_MEM_INIT_TIMEOUT) { + status = driverdt->checkctlinterrupt(pd, LPDDR4_INTR_BIST_DONE, + &int_status); + if (!status & int_status) { + /* Clear LPDDR4_INTR_BIST_DONE */ + driverdt->ackctlinterrupt(pd, LPDDR4_INTR_BIST_DONE); + break; + } + udelay(1000); + i++; + } + + /* Before continuing we have to stop BIST - BIST_GO = 0 */ + TH_OFFSET_FROM_REG(LPDDR4__BIST_GO__REG, CTL_SHIFT, offset); + driverdt->writereg(pd, LPDDR4_CTL_REGS, offset, 0); + /* Timeout hit while priming the memory. We can't continue, + * since the memory is not fully initialized and we most + * likely get an uncorrectable error exception while booting. + */ + if (i == BIST_MEM_INIT_TIMEOUT) { + printf("ERROR: Timeout while priming the memory.\n"); + hang(); + } +} + +static void k3_ddrss_lpddr4_preload_full_mem(struct k3_ddrss_desc *ddrss, + u64 total_size, u32 pattern) +{ + u32 done, max_size2; + + /* Get the max size (log2) supported in this config (16/32 lpddr4) + * from the start_addess width - 16bit: 8G, 32bit: 32G + */ + max_size2 = TH_FLD_WIDTH(LPDDR4__BIST_START_ADDRESS_0__FLD) + + TH_FLD_WIDTH(LPDDR4__BIST_START_ADDRESS_1__FLD) + 1; + + /* ECC is enabled in dt but we can't preload the memory if + * the memory configuration is recognized and supported. + */ + if (!total_size || total_size > (1ull << max_size2) || + total_size & (total_size - 1)) { + printf("ECC: the memory configuration is not supported\n"); + hang(); + } printf("ECC is enabled, priming DDR which will take several seconds.\n"); + done = get_timer(0); + k3_lpddr4_bist_init_mem_region(ddrss, 0, total_size, pattern); + printf("ECC: priming DDR completed in %lu msec\n", get_timer(done)); +} + +static void k3_ddrss_ddr_bank_base_size_calc(struct k3_ddrss_desc *ddrss) +{ + int bank, na, ns, len, parent; + const fdt32_t *ptr, *end; + + for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { + ddrss->ddr_bank_base[bank] = 0; + ddrss->ddr_bank_size[bank] = 0; + } + + ofnode mem = ofnode_null(); + + do { + mem = ofnode_by_prop_value(mem, "device_type", "memory", 7); + } while (!ofnode_is_enabled(mem)); + + const void *fdt = ofnode_to_fdt(mem); + int node = ofnode_to_offset(mem); + const char *property = "reg"; + + parent = fdt_parent_offset(fdt, node); + na = fdt_address_cells(fdt, parent); + ns = fdt_size_cells(fdt, parent); + ptr = fdt_getprop(fdt, node, property, &len); + end = ptr + len / sizeof(*ptr); + + for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { + if (ptr + na + ns <= end) { + if (CONFIG_IS_ENABLED(OF_TRANSLATE)) + ddrss->ddr_bank_base[bank] = fdt_translate_address(fdt, node, ptr); + else + ddrss->ddr_bank_base[bank] = fdtdec_get_number(ptr, na); + + ddrss->ddr_bank_size[bank] = fdtdec_get_number(&ptr[na], ns); + } - for (i = 0; i < (size / 4); i++) - addr[i] = word; + ptr += na + ns; + } + + for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) + ddrss->ddr_ram_size += ddrss->ddr_bank_size[bank]; } static void k3_ddrss_lpddr4_ecc_calc_reserved_mem(struct k3_ddrss_desc *ddrss) { fdtdec_setup_mem_size_base_lowest(); - ddrss->ecc_reserved_space = gd->ram_size; + ddrss->ecc_reserved_space = ddrss->ddr_ram_size; do_div(ddrss->ecc_reserved_space, 9); /* Round to clean number */ @@ -571,25 +724,29 @@ static void k3_ddrss_lpddr4_ecc_calc_reserved_mem(struct k3_ddrss_desc *ddrss) static void k3_ddrss_lpddr4_ecc_init(struct k3_ddrss_desc *ddrss) { - u32 ecc_region_start = ddrss->ecc_regions[0].start; - u32 ecc_range = ddrss->ecc_regions[0].range; + u64 ecc_region_start = ddrss->ecc_regions[0].start; + u64 ecc_range = ddrss->ecc_regions[0].range; u32 base = (u32)ddrss->ddrss_ss_cfg; u32 val; /* Only Program region 0 which covers full ddr space */ - k3_ddrss_set_ecc_range_r0(base, ecc_region_start - gd->ram_base, ecc_range); + k3_ddrss_set_ecc_range_r0(base, ecc_region_start - ddrss->ddr_bank_base[0], ecc_range); /* Enable ECC, RMW, WR_ALLOC */ writel(DDRSS_ECC_CTRL_REG_ECC_EN | DDRSS_ECC_CTRL_REG_RMW_EN | DDRSS_ECC_CTRL_REG_WR_ALLOC, base + DDRSS_ECC_CTRL_REG); - /* Preload ECC Mem region with 0's */ - k3_ddrss_preload_ecc_mem_region((u32 *)ecc_region_start, ecc_range, - 0x00000000); + /* Preload the full memory with 0's using the BIST engine of + * the LPDDR4 controller. + */ + k3_ddrss_lpddr4_preload_full_mem(ddrss, ddrss->ddr_ram_size, 0); /* Clear Error Count Register */ writel(0x1, base + DDRSS_ECC_1B_ERR_CNT_REG); + writel(DDRSS_V2A_INT_SET_REG_ECC1BERR_EN | DDRSS_V2A_INT_SET_REG_ECC2BERR_EN | + DDRSS_V2A_INT_SET_REG_ECCM1BERR_EN, base + DDRSS_V2A_INT_SET_REG); + /* Enable ECC Check */ val = readl(base + DDRSS_ECC_CTRL_REG); val |= DDRSS_ECC_CTRL_REG_ECC_CK; @@ -630,7 +787,9 @@ static int k3_ddrss_probe(struct udevice *dev) k3_lpddr4_start(ddrss); - if (ddrss->ti_ecc_enabled) { + k3_ddrss_ddr_bank_base_size_calc(ddrss); + + if (IS_ENABLED(CONFIG_K3_INLINE_ECC)) { if (!ddrss->ddrss_ss_cfg) { printf("%s: ss_cfg is required if ecc is enabled but not provided.", __func__); @@ -640,8 +799,8 @@ static int k3_ddrss_probe(struct udevice *dev) k3_ddrss_lpddr4_ecc_calc_reserved_mem(ddrss); /* Always configure one region that covers full DDR space */ - ddrss->ecc_regions[0].start = gd->ram_base; - ddrss->ecc_regions[0].range = gd->ram_size - ddrss->ecc_reserved_space; + ddrss->ecc_regions[0].start = ddrss->ddr_bank_base[0]; + ddrss->ecc_regions[0].range = ddrss->ddr_ram_size - ddrss->ecc_reserved_space; k3_ddrss_lpddr4_ecc_init(ddrss); } @@ -650,30 +809,24 @@ static int k3_ddrss_probe(struct udevice *dev) int k3_ddrss_ddr_fdt_fixup(struct udevice *dev, void *blob, struct bd_info *bd) { - struct k3_ddrss_desc *ddrss = dev_get_priv(dev); - u64 start[CONFIG_NR_DRAM_BANKS]; - u64 size[CONFIG_NR_DRAM_BANKS]; int bank; + struct k3_ddrss_desc *ddrss = dev_get_priv(dev); if (ddrss->ecc_reserved_space == 0) return 0; for (bank = CONFIG_NR_DRAM_BANKS - 1; bank >= 0; bank--) { - if (ddrss->ecc_reserved_space > bd->bi_dram[bank].size) { - ddrss->ecc_reserved_space -= bd->bi_dram[bank].size; - bd->bi_dram[bank].size = 0; + if (ddrss->ecc_reserved_space > ddrss->ddr_bank_size[bank]) { + ddrss->ecc_reserved_space -= ddrss->ddr_bank_size[bank]; + ddrss->ddr_bank_size[bank] = 0; } else { - bd->bi_dram[bank].size -= ddrss->ecc_reserved_space; + ddrss->ddr_bank_size[bank] -= ddrss->ecc_reserved_space; break; } } - for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - start[bank] = bd->bi_dram[bank].start; - size[bank] = bd->bi_dram[bank].size; - } - - return fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS); + return fdt_fixup_memory_banks(blob, ddrss->ddr_bank_base, + ddrss->ddr_bank_size, CONFIG_NR_DRAM_BANKS); } static int k3_ddrss_get_info(struct udevice *dev, struct ram_info *info) diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 9c2d1398247..6467f20422b 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -294,7 +294,7 @@ config RTC_DAVINCI config RTC_ZYNQMP bool "Enable ZynqMP RTC driver" - depends on ARCH_ZYNQMP + depends on DM_RTC && (ARCH_ZYNQMP || ARCH_VERSAL || ARCH_VERSAL_NET || ARCH_VERSAL2) help Say "yes" here to support the on chip real time clock present on Xilinx ZynqMP SoC. diff --git a/drivers/scsi/Kconfig b/drivers/scsi/Kconfig index 7e21c4ae2bb..fc87d34cca3 100644 --- a/drivers/scsi/Kconfig +++ b/drivers/scsi/Kconfig @@ -1,5 +1,6 @@ config SCSI bool "Support SCSI controllers with driver model" + select BLK help This enables support for SCSI (Small Computer System Interface), a parallel interface widely used with storage peripherals such as diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c index 4251bf28cd3..2a095d0c58e 100644 --- a/drivers/spi/zynqmp_gqspi.c +++ b/drivers/spi/zynqmp_gqspi.c @@ -255,7 +255,7 @@ static u32 zynqmp_qspi_bus_select(struct zynqmp_qspi_priv *priv) GQSPI_GFIFO_CS_LOWER | GQSPI_GFIFO_CS_UPPER; else - debug("Wrong Bus selection:0x%x\n", priv->bus); + log_debug("Wrong Bus selection:0x%x\n", priv->bus); } else { if (priv->u_page) gqspi_fifo_reg = GQSPI_GFIFO_LOW_BUS | diff --git a/drivers/sysinfo/sandbox.c b/drivers/sysinfo/sandbox.c index d39720958f0..af54fe87596 100644 --- a/drivers/sysinfo/sandbox.c +++ b/drivers/sysinfo/sandbox.c @@ -13,6 +13,7 @@ struct sysinfo_sandbox_priv { bool called_detect; int test_i1; int test_i2; + u32 test_data[2]; }; char vacation_spots[][64] = {"R'lyeh", "Dreamlands", "Plateau of Leng", @@ -24,6 +25,8 @@ int sysinfo_sandbox_detect(struct udevice *dev) priv->called_detect = true; priv->test_i2 = 100; + priv->test_data[0] = 0xabcdabcd; + priv->test_data[1] = 0xdeadbeef; return 0; } @@ -79,6 +82,21 @@ int sysinfo_sandbox_get_str(struct udevice *dev, int id, size_t size, char *val) return -ENOENT; } +int sysinfo_sandbox_get_data(struct udevice *dev, int id, void **buf, + size_t *size) +{ + struct sysinfo_sandbox_priv *priv = dev_get_priv(dev); + + switch (id) { + case DATA_TEST: + *buf = priv->test_data; + *size = sizeof(priv->test_data); + return 0; + } + + return -ENOENT; +} + static const struct udevice_id sysinfo_sandbox_ids[] = { { .compatible = "sandbox,sysinfo-sandbox" }, { /* sentinel */ } @@ -89,6 +107,7 @@ static const struct sysinfo_ops sysinfo_sandbox_ops = { .get_bool = sysinfo_sandbox_get_bool, .get_int = sysinfo_sandbox_get_int, .get_str = sysinfo_sandbox_get_str, + .get_data = sysinfo_sandbox_get_data, }; int sysinfo_sandbox_probe(struct udevice *dev) diff --git a/drivers/sysinfo/sandbox.h b/drivers/sysinfo/sandbox.h index a7cbac0ce18..47b7f5ef9fe 100644 --- a/drivers/sysinfo/sandbox.h +++ b/drivers/sysinfo/sandbox.h @@ -9,4 +9,5 @@ enum { INT_TEST1, INT_TEST2, STR_VACATIONSPOT, + DATA_TEST, }; diff --git a/drivers/sysinfo/smbios.c b/drivers/sysinfo/smbios.c index a7ac8e3f072..99104274f72 100644 --- a/drivers/sysinfo/smbios.c +++ b/drivers/sysinfo/smbios.c @@ -5,14 +5,240 @@ */ #include <dm.h> +#include <smbios_plat.h> #include <sysinfo.h> +/* platform information storage */ +struct processor_info processor_info; +struct cache_info cache_info[SYSINFO_CACHE_LVL_MAX]; +struct sysinfo_plat sysinfo_smbios_p = { + /* Processor Information */ + .processor = &processor_info, + /* Cache Information */ + .cache = &cache_info[0], +}; + +/* structure for smbios private data storage */ +struct sysinfo_plat_priv { + struct processor_info *t4; + struct smbios_type7 t7[SYSINFO_CACHE_LVL_MAX]; + u16 cache_handles[SYSINFO_CACHE_LVL_MAX]; + u8 cache_level; +}; + +static void smbios_cache_info_dump(struct smbios_type7 *cache_info) +{ + log_debug("SMBIOS Type 7 (Cache Information):\n"); + log_debug("Cache Configuration: 0x%04x\n", cache_info->config.data); + log_debug("Maximum Cache Size: %u KB\n", cache_info->max_size.data); + log_debug("Installed Size: %u KB\n", cache_info->inst_size.data); + log_debug("Supported SRAM Type: 0x%04x\n", + cache_info->supp_sram_type.data); + log_debug("Current SRAM Type: 0x%04x\n", + cache_info->curr_sram_type.data); + log_debug("Cache Speed: %u\n", cache_info->speed); + log_debug("Error Correction Type: %u\n", cache_info->err_corr_type); + log_debug("System Cache Type: %u\n", cache_info->sys_cache_type); + log_debug("Associativity: %u\n", cache_info->associativity); + log_debug("Maximum Cache Size 2: %u KB\n", cache_info->max_size2.data); + log_debug("Installed Cache Size 2: %u KB\n", + cache_info->inst_size2.data); +} + +/* weak function for the platforms not yet supported */ +__weak int sysinfo_get_cache_info(u8 level, struct cache_info *cache_info) +{ + return -ENOSYS; +} + +__weak int sysinfo_get_processor_info(struct processor_info *pinfo) +{ + return -ENOSYS; +} + +void sysinfo_cache_info_default(struct cache_info *ci) +{ + memset(ci, 0, sizeof(*ci)); + ci->config.data = SMBIOS_CACHE_LOCATE_UNKNOWN | SMBIOS_CACHE_OP_UND; + ci->supp_sram_type.fields.unknown = 1; + ci->curr_sram_type.fields.unknown = 1; + ci->speed = SMBIOS_CACHE_SPEED_UNKNOWN; + ci->err_corr_type = SMBIOS_CACHE_ERRCORR_UNKNOWN; + ci->cache_type = SMBIOS_CACHE_SYSCACHE_TYPE_UNKNOWN; +} + +static int sysinfo_plat_detect(struct udevice *dev) +{ + return 0; +} + +static int sysinfo_plat_get_str(struct udevice *dev, int id, + size_t size, char *val) +{ + struct sysinfo_plat_priv *priv = dev_get_priv(dev); + const char *str = NULL; + + switch (id) { + case SYSID_SM_PROCESSOR_MANUFACT: + str = priv->t4->manufacturer; + break; + default: + break; + } + + if (!str) + return -ENOSYS; + + strlcpy(val, str, size); + + return 0; +} + +static int sysinfo_plat_get_int(struct udevice *dev, int id, int *val) +{ + struct sysinfo_plat_priv *priv = dev_get_priv(dev); + u8 i; + + if (id >= SYSID_SM_CACHE_INFO_START && + id <= SYSID_SM_CACHE_INFO_END) { + /* For smbios type 7 */ + for (i = 0; i < priv->cache_level; i++) { + switch (id - i) { + case SYSID_SM_CACHE_MAX_SIZE: + *val = priv->t7[i].max_size.data; + return 0; + case SYSID_SM_CACHE_INST_SIZE: + *val = priv->t7[i].inst_size.data; + return 0; + case SYSID_SM_CACHE_SCACHE_TYPE: + *val = priv->t7[i].sys_cache_type; + return 0; + case SYSID_SM_CACHE_ASSOC: + *val = priv->t7[i].associativity; + return 0; + case SYSID_SM_CACHE_MAX_SIZE2: + *val = priv->t7[i].max_size2.data; + return 0; + case SYSID_SM_CACHE_INST_SIZE2: + *val = priv->t7[i].inst_size2.data; + return 0; + default: + break; + } + } + return -ENOSYS; + } + + switch (id) { + case SYSID_SM_PROCESSOR_CORE_CNT: + *val = priv->t4->core_count; + break; + case SYSID_SM_PROCESSOR_CORE_EN: + *val = priv->t4->core_enabled; + break; + case SYSID_SM_PROCESSOR_CHARA: + *val = priv->t4->characteristics; + break; + case SYSID_SM_CACHE_LEVEL: + if (!priv->cache_level) /* No cache detected */ + return -ENOSYS; + *val = priv->cache_level - 1; + break; + default: + return -ENOSYS; + } + + return 0; +} + +static int sysinfo_plat_get_data(struct udevice *dev, int id, void **buf, + size_t *size) +{ + struct sysinfo_plat_priv *priv = dev_get_priv(dev); + + switch (id) { + case SYSID_SM_PROCESSOR_ID: + *buf = priv->t4->id; + *size = sizeof(priv->t4->id); + break; + case SYSID_SM_CACHE_HANDLE: + *buf = &priv->cache_handles[0]; + *size = sizeof(priv->cache_handles); + break; + default: + return -EOPNOTSUPP; + } + return 0; +} + +static int sysinfo_plat_probe(struct udevice *dev) +{ + struct sysinfo_plat_priv *priv = dev_get_priv(dev); + struct sysinfo_plat *plat = &sysinfo_smbios_p; + u8 level; + + if (!sysinfo_get_processor_info(plat->processor)) + priv->t4 = plat->processor; + + for (level = 0; level < SYSINFO_CACHE_LVL_MAX; level++) { + struct cache_info *pcache = plat->cache + level; + + if (sysinfo_get_cache_info(level, pcache)) + break; /* no more levels */ + + /* + * Fill in the SMBIOS type 7 structure, + * skip the header members (type, length, handle), + * and the ones in DT smbios node. + */ + priv->t7[level].sys_cache_type = pcache->cache_type; + priv->t7[level].associativity = pcache->associativity; + + if (pcache->max_size > SMBIOS_CACHE_SIZE_EXT_KB) { + priv->t7[level].max_size.data = 0xFFFF; + priv->t7[level].max_size2.fields.size = + pcache->max_size / 64; + priv->t7[level].max_size2.fields.granu = + SMBIOS_CACHE_GRANU_64K; + } else { + priv->t7[level].max_size.fields.size = pcache->max_size; + priv->t7[level].max_size.fields.granu = + SMBIOS_CACHE_GRANU_1K; + priv->t7[level].max_size2.data = 0; + } + if (pcache->inst_size > SMBIOS_CACHE_SIZE_EXT_KB) { + priv->t7[level].inst_size.data = 0xFFFF; + priv->t7[level].inst_size2.fields.size = + pcache->inst_size / 64; + priv->t7[level].inst_size2.fields.granu = + SMBIOS_CACHE_GRANU_64K; + } else { + priv->t7[level].inst_size.fields.size = + pcache->inst_size; + priv->t7[level].inst_size.fields.granu = + SMBIOS_CACHE_GRANU_1K; + priv->t7[level].inst_size2.data = 0; + } + smbios_cache_info_dump(&priv->t7[level]); + } + if (!level) /* no cache detected */ + return -ENOSYS; + + priv->cache_level = level; + + return 0; +} + static const struct udevice_id sysinfo_smbios_ids[] = { { .compatible = "u-boot,sysinfo-smbios" }, { /* sentinel */ } }; static const struct sysinfo_ops sysinfo_smbios_ops = { + .detect = sysinfo_plat_detect, + .get_str = sysinfo_plat_get_str, + .get_int = sysinfo_plat_get_int, + .get_data = sysinfo_plat_get_data, }; U_BOOT_DRIVER(sysinfo_smbios) = { @@ -20,4 +246,6 @@ U_BOOT_DRIVER(sysinfo_smbios) = { .id = UCLASS_SYSINFO, .of_match = sysinfo_smbios_ids, .ops = &sysinfo_smbios_ops, + .priv_auto = sizeof(struct sysinfo_plat_priv), + .probe = sysinfo_plat_probe, }; diff --git a/drivers/sysinfo/sysinfo-uclass.c b/drivers/sysinfo/sysinfo-uclass.c index d77d1e3ee44..3c0cd51273e 100644 --- a/drivers/sysinfo/sysinfo-uclass.c +++ b/drivers/sysinfo/sysinfo-uclass.c @@ -99,6 +99,26 @@ int sysinfo_get_str(struct udevice *dev, int id, size_t size, char *val) return ops->get_str(dev, id, size, val); } +int sysinfo_get_data(struct udevice *dev, int id, void **data, size_t *size) +{ + struct sysinfo_priv *priv; + struct sysinfo_ops *ops; + + if (!dev) + return -ENOSYS; + + priv = dev_get_uclass_priv(dev); + ops = sysinfo_get_ops(dev); + + if (!priv->detected) + return -EPERM; + + if (!ops->get_data) + return -ENOSYS; + + return ops->get_data(dev, id, data, size); +} + UCLASS_DRIVER(sysinfo) = { .id = UCLASS_SYSINFO, .name = "sysinfo", diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig index 960b6a906ac..99c6649e417 100644 --- a/drivers/usb/Kconfig +++ b/drivers/usb/Kconfig @@ -1,5 +1,6 @@ menuconfig USB bool "USB support" + select BLK ---help--- Universal Serial Bus (USB) is a specification for a serial bus subsystem which offers higher speeds and more features than the diff --git a/drivers/virtio/Kconfig b/drivers/virtio/Kconfig index 1de68867d52..512ac376f18 100644 --- a/drivers/virtio/Kconfig +++ b/drivers/virtio/Kconfig @@ -64,6 +64,7 @@ config VIRTIO_NET config VIRTIO_BLK bool "virtio block driver" depends on VIRTIO + select BLK help This is the virtual block driver for virtio. It can be used with QEMU based targets. |