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-rw-r--r--drivers/clk/analogbits/wrpll-cln28hpc.c6
-rw-r--r--drivers/clk/sifive/fu540-prci.c7
-rw-r--r--drivers/clk/sifive/fu540-prci.h22
-rw-r--r--drivers/clk/sifive/fu740-prci.c7
-rw-r--r--drivers/clk/sifive/fu740-prci.h22
-rw-r--r--drivers/clk/sifive/sifive-prci.c3
-rw-r--r--drivers/clk/sifive/sifive-prci.h4
-rw-r--r--drivers/mtd/renesas_rpc_hf.c1
-rw-r--r--drivers/spi/renesas_rpc_spi.c23
9 files changed, 39 insertions, 56 deletions
diff --git a/drivers/clk/analogbits/wrpll-cln28hpc.c b/drivers/clk/analogbits/wrpll-cln28hpc.c
index a3cb109d357..537c696b727 100644
--- a/drivers/clk/analogbits/wrpll-cln28hpc.c
+++ b/drivers/clk/analogbits/wrpll-cln28hpc.c
@@ -81,7 +81,7 @@ static int __wrpll_calc_filter_range(unsigned long post_divr_freq)
{
if (post_divr_freq < MIN_POST_DIVR_FREQ ||
post_divr_freq > MAX_POST_DIVR_FREQ) {
- WARN(1, "%s: post-divider reference freq out of range: %lu",
+ WARN(1, "%s: post-divider reference freq out of range: %lu\n",
__func__, post_divr_freq);
return -ERANGE;
}
@@ -229,7 +229,7 @@ int wrpll_configure_for_rate(struct wrpll_cfg *c, u32 target_rate,
int range;
if (c->flags == 0) {
- WARN(1, "%s called with uninitialized PLL config", __func__);
+ WARN(1, "%s called with uninitialized PLL config\n", __func__);
return -EINVAL;
}
@@ -335,7 +335,7 @@ unsigned long wrpll_calc_output_rate(const struct wrpll_cfg *c,
u64 n;
if (c->flags & WRPLL_FLAGS_EXT_FEEDBACK_MASK) {
- WARN(1, "external feedback mode not yet supported");
+ WARN(1, "external feedback mode not yet supported\n");
return ULONG_MAX;
}
diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c
index ceb2c6fab0d..e55a26ab8fd 100644
--- a/drivers/clk/sifive/fu540-prci.c
+++ b/drivers/clk/sifive/fu540-prci.c
@@ -58,7 +58,7 @@ static const struct __prci_clock_ops sifive_fu540_prci_tlclksel_clk_ops = {
};
/* List of clock controls provided by the PRCI */
-struct __prci_clock __prci_init_clocks_fu540[] = {
+static struct __prci_clock __prci_init_clocks_fu540[] = {
[PRCI_CLK_COREPLL] = {
.name = "corepll",
.parent_name = "hfclk",
@@ -83,3 +83,8 @@ struct __prci_clock __prci_init_clocks_fu540[] = {
.ops = &sifive_fu540_prci_tlclksel_clk_ops,
},
};
+
+const struct prci_clk_desc prci_clk_fu540 = {
+ .clks = __prci_init_clocks_fu540,
+ .num_clks = ARRAY_SIZE(__prci_init_clocks_fu540),
+};
diff --git a/drivers/clk/sifive/fu540-prci.h b/drivers/clk/sifive/fu540-prci.h
deleted file mode 100644
index 113301107da..00000000000
--- a/drivers/clk/sifive/fu540-prci.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2020-2021 SiFive, Inc.
- * Zong Li
- * Pragnesh Patel
- */
-
-#ifndef __SIFIVE_CLK_FU540_PRCI_H
-#define __SIFIVE_CLK_FU540_PRCI_H
-
-#include "sifive-prci.h"
-
-#define NUM_CLOCK_FU540 4
-
-extern struct __prci_clock __prci_init_clocks_fu540[NUM_CLOCK_FU540];
-
-static const struct prci_clk_desc prci_clk_fu540 = {
- .clks = __prci_init_clocks_fu540,
- .num_clks = ARRAY_SIZE(__prci_init_clocks_fu540),
-};
-
-#endif /* __SIFIVE_CLK_FU540_PRCI_H */
diff --git a/drivers/clk/sifive/fu740-prci.c b/drivers/clk/sifive/fu740-prci.c
index 5edc864e4bd..4274b215d2f 100644
--- a/drivers/clk/sifive/fu740-prci.c
+++ b/drivers/clk/sifive/fu740-prci.c
@@ -102,7 +102,7 @@ static const struct __prci_clock_ops sifive_fu740_prci_pcieaux_clk_ops = {
};
/* List of clock controls provided by the PRCI */
-struct __prci_clock __prci_init_clocks_fu740[] = {
+static struct __prci_clock __prci_init_clocks_fu740[] = {
[FU740_PRCI_CLK_COREPLL] = {
.name = "corepll",
.parent_name = "hfclk",
@@ -156,3 +156,8 @@ struct __prci_clock __prci_init_clocks_fu740[] = {
.pwd = &__prci_pcieaux_data,
}
};
+
+const struct prci_clk_desc prci_clk_fu740 = {
+ .clks = __prci_init_clocks_fu740,
+ .num_clks = ARRAY_SIZE(__prci_init_clocks_fu740),
+};
diff --git a/drivers/clk/sifive/fu740-prci.h b/drivers/clk/sifive/fu740-prci.h
deleted file mode 100644
index b74f0789061..00000000000
--- a/drivers/clk/sifive/fu740-prci.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2020-2021 SiFive, Inc.
- * Zong Li
- * Pragnesh Patel
- */
-
-#ifndef __SIFIVE_CLK_FU740_PRCI_H
-#define __SIFIVE_CLK_FU740_PRCI_H
-
-#include "sifive-prci.h"
-
-#define NUM_CLOCK_FU740 9
-
-extern struct __prci_clock __prci_init_clocks_fu740[NUM_CLOCK_FU740];
-
-static const struct prci_clk_desc prci_clk_fu740 = {
- .clks = __prci_init_clocks_fu740,
- .num_clks = ARRAY_SIZE(__prci_init_clocks_fu740),
-};
-
-#endif /* __SIFIVE_CLK_FU740_PRCI_H */
diff --git a/drivers/clk/sifive/sifive-prci.c b/drivers/clk/sifive/sifive-prci.c
index 5ea86062800..aa26d3a109b 100644
--- a/drivers/clk/sifive/sifive-prci.c
+++ b/drivers/clk/sifive/sifive-prci.c
@@ -33,8 +33,7 @@
#include <linux/math64.h>
#include <dt-bindings/clock/sifive-fu740-prci.h>
-#include "fu540-prci.h"
-#include "fu740-prci.h"
+#include "sifive-prci.h"
/*
* Private functions
diff --git a/drivers/clk/sifive/sifive-prci.h b/drivers/clk/sifive/sifive-prci.h
index 5ce33d61846..b391698081d 100644
--- a/drivers/clk/sifive/sifive-prci.h
+++ b/drivers/clk/sifive/sifive-prci.h
@@ -320,4 +320,8 @@ unsigned long sifive_prci_hfpclkplldiv_recalc_rate(struct __prci_clock *pc,
int sifive_prci_clock_enable(struct __prci_clock *pc, bool enable);
+/* Clock driver data */
+extern const struct prci_clk_desc prci_clk_fu540;
+extern const struct prci_clk_desc prci_clk_fu740;
+
#endif /* __SIFIVE_CLK_SIFIVE_PRCI_H */
diff --git a/drivers/mtd/renesas_rpc_hf.c b/drivers/mtd/renesas_rpc_hf.c
index 941f2040983..03545822b07 100644
--- a/drivers/mtd/renesas_rpc_hf.c
+++ b/drivers/mtd/renesas_rpc_hf.c
@@ -387,6 +387,7 @@ static int rpc_hf_probe(struct udevice *dev)
static const struct udevice_id rpc_hf_ids[] = {
{ .compatible = "renesas,r7s72100-rpc-if" },
{ .compatible = "renesas,rcar-gen3-rpc-if" },
+ { .compatible = "renesas,rcar-gen4-rpc-if" },
{}
};
diff --git a/drivers/spi/renesas_rpc_spi.c b/drivers/spi/renesas_rpc_spi.c
index e6b602cf7b4..f1e6f9f4e01 100644
--- a/drivers/spi/renesas_rpc_spi.c
+++ b/drivers/spi/renesas_rpc_spi.c
@@ -145,6 +145,12 @@
#define RPC_PHYCNT_WBUF BIT(2)
#define RPC_PHYCNT_MEM(v) (((v) & 0x3) << 0)
+#define RPCIF_PHYOFFSET1 0x0080 /* R/W */
+#define RPCIF_PHYOFFSET1_DDRTMG(v) (((v) & 0x3) << 28)
+
+#define RPCIF_PHYOFFSET2 0x0084 /* R/W */
+#define RPCIF_PHYOFFSET2_OCTTMG(v) (((v) & 0x7) << 8)
+
#define RPC_PHYINT 0x0088 /* R/W */
#define RPC_PHYINT_RSTEN BIT(18)
#define RPC_PHYINT_WPEN BIT(17)
@@ -227,6 +233,12 @@ static int rpc_spi_claim_bus(struct udevice *dev, bool manual)
struct udevice *bus = dev->parent;
struct rpc_spi_priv *priv = dev_get_priv(bus);
+ setbits_le32(priv->regs + RPCIF_PHYOFFSET1,
+ RPCIF_PHYOFFSET1_DDRTMG(3));
+ clrsetbits_le32(priv->regs + RPCIF_PHYOFFSET2,
+ RPCIF_PHYOFFSET2_OCTTMG(7),
+ RPCIF_PHYOFFSET2_OCTTMG(4));
+
/* NOTE: The 0x260 are undocumented bits, but they must be set. */
writel(RPC_PHYCNT_CAL | rpc_spi_get_strobe_delay() | 0x260,
priv->regs + RPC_PHYCNT);
@@ -277,24 +289,24 @@ static int rpc_spi_mem_exec_op(struct spi_slave *spi,
writel(RPC_DRCMR_CMD(op->cmd.opcode), priv->regs + RPC_DRCMR);
smenr |= RPC_DRENR_CDE;
- writel(0, priv->regs + RPC_DREAR);
if (op->addr.nbytes == 4) {
writel(RPC_DREAR_EAV(offset >> 25) | RPC_DREAR_EAC(1),
priv->regs + RPC_DREAR);
smenr |= RPC_DRENR_ADE(0xF);
} else if (op->addr.nbytes == 3) {
+ writel(0, priv->regs + RPC_DREAR);
smenr |= RPC_DRENR_ADE(0x7);
} else {
+ writel(0, priv->regs + RPC_DREAR);
smenr |= RPC_DRENR_ADE(0);
}
- writel(0, priv->regs + RPC_DRDMCR);
- if (op->dummy.nbytes) {
- writel(8 * op->dummy.nbytes - 1, priv->regs + RPC_DRDMCR);
+ if (op->dummy.nbytes)
smenr |= RPC_DRENR_DME;
- }
+ writel(8 * op->dummy.nbytes - 1, priv->regs + RPC_DRDMCR);
writel(0, priv->regs + RPC_DROPR);
+ writel(0, priv->regs + RPC_DRDRENR);
writel(smenr, priv->regs + RPC_DRENR);
memcpy_fromio(din, (void *)(priv->extr + offset), op->data.nbytes);
@@ -453,6 +465,7 @@ static const struct dm_spi_ops rpc_spi_ops = {
static const struct udevice_id rpc_spi_ids[] = {
{ .compatible = "renesas,r7s72100-rpc-if" },
{ .compatible = "renesas,rcar-gen3-rpc-if" },
+ { .compatible = "renesas,rcar-gen4-rpc-if" },
{ }
};
generated by cgit v1.2.3 (git 2.0.4) at 2025-08-04 20:13:11 +0000