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-rw-r--r--drivers/i2c/Kconfig20
-rw-r--r--drivers/i2c/Makefile1
-rw-r--r--drivers/i2c/muxes/Kconfig9
-rw-r--r--drivers/i2c/muxes/Makefile1
-rw-r--r--drivers/i2c/muxes/i2c-mux-gpio.c138
-rw-r--r--drivers/i2c/stm32f7_i2c.c882
-rw-r--r--drivers/mtd/cfi_flash.c8
-rw-r--r--drivers/pci/pci_rom.c41
-rw-r--r--drivers/ram/Kconfig2
-rw-r--r--drivers/serial/Kconfig19
-rw-r--r--drivers/serial/ns16550.c123
-rw-r--r--drivers/serial/serial-uclass.c48
-rw-r--r--drivers/spi/ich.c102
-rw-r--r--drivers/spi/ich.h2
-rw-r--r--drivers/timer/Kconfig8
-rw-r--r--drivers/timer/Makefile1
-rw-r--r--drivers/timer/atmel_pit_timer.c90
17 files changed, 1257 insertions, 238 deletions
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 720e82d5ded..d2d9367bfc4 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -174,6 +174,26 @@ config SYS_I2C_S3C24X0
help
Support for Samsung I2C controller as Samsung SoCs.
+config SYS_I2C_STM32F7
+ bool "STMicroelectronics STM32F7 I2C support"
+ depends on (STM32F7 || STM32H7) && DM_I2C
+ help
+ Enable this option to add support for STM32 I2C controller
+ introduced with STM32F7/H7 SoCs. This I2C controller supports :
+ _ Slave and master modes
+ _ Multimaster capability
+ _ Standard-mode (up to 100 kHz)
+ _ Fast-mode (up to 400 kHz)
+ _ Fast-mode Plus (up to 1 MHz)
+ _ 7-bit and 10-bit addressing mode
+ _ Multiple 7-bit slave addresses (2 addresses, 1 with configurable mask)
+ _ All 7-bit addresses acknowledge mode
+ _ General call
+ _ Programmable setup and hold times
+ _ Easy to use event management
+ _ Optional clock stretching
+ _ Software reset
+
config SYS_I2C_UNIPHIER
bool "UniPhier I2C driver"
depends on ARCH_UNIPHIER && DM_I2C
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 4f754191e2e..e7ade94d918 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -37,6 +37,7 @@ obj-$(CONFIG_SYS_I2C_S3C24X0) += s3c24x0_i2c.o exynos_hs_i2c.o
obj-$(CONFIG_SYS_I2C_SANDBOX) += sandbox_i2c.o i2c-emul-uclass.o
obj-$(CONFIG_SYS_I2C_SH) += sh_i2c.o
obj-$(CONFIG_SYS_I2C_SOFT) += soft_i2c.o
+obj-$(CONFIG_SYS_I2C_STM32F7) += stm32f7_i2c.o
obj-$(CONFIG_SYS_I2C_TEGRA) += tegra_i2c.o
obj-$(CONFIG_SYS_I2C_UNIPHIER) += i2c-uniphier.o
obj-$(CONFIG_SYS_I2C_UNIPHIER_F) += i2c-uniphier-f.o
diff --git a/drivers/i2c/muxes/Kconfig b/drivers/i2c/muxes/Kconfig
index 48900ed2afc..156380c1ccc 100644
--- a/drivers/i2c/muxes/Kconfig
+++ b/drivers/i2c/muxes/Kconfig
@@ -34,3 +34,12 @@ config I2C_MUX_PCA954x
paritioning I2C bus and connect multiple devices with the same address
to the same I2C controller where driver handles proper routing to
target i2c device. PCA9544 and PCA9548 are supported.
+
+config I2C_MUX_GPIO
+ tristate "GPIO-based I2C multiplexer"
+ depends on I2C_MUX && DM_GPIO
+ help
+ If you say yes to this option, support will be included for
+ a GPIO based I2C multiplexer. This driver provides access to
+ I2C busses connected through a MUX, which is controlled
+ through GPIO pins.
diff --git a/drivers/i2c/muxes/Makefile b/drivers/i2c/muxes/Makefile
index 0811add4216..3831f4e4fba 100644
--- a/drivers/i2c/muxes/Makefile
+++ b/drivers/i2c/muxes/Makefile
@@ -6,3 +6,4 @@
obj-$(CONFIG_I2C_ARB_GPIO_CHALLENGE) += i2c-arb-gpio-challenge.o
obj-$(CONFIG_$(SPL_)I2C_MUX) += i2c-mux-uclass.o
obj-$(CONFIG_I2C_MUX_PCA954x) += pca954x.o
+obj-$(CONFIG_I2C_MUX_GPIO) += i2c-mux-gpio.o
diff --git a/drivers/i2c/muxes/i2c-mux-gpio.c b/drivers/i2c/muxes/i2c-mux-gpio.c
new file mode 100644
index 00000000000..0269b3a18ec
--- /dev/null
+++ b/drivers/i2c/muxes/i2c-mux-gpio.c
@@ -0,0 +1,138 @@
+/*
+ * I2C multiplexer using GPIO API
+ *
+ * Copyright 2017 NXP
+ *
+ * Peng Fan <peng.fan@nxp.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/io.h>
+#include <asm-generic/gpio.h>
+#include <common.h>
+#include <dm.h>
+#include <dm/pinctrl.h>
+#include <fdtdec.h>
+#include <i2c.h>
+#include <linux/errno.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/**
+ * struct i2c_mux_gpio_priv - private data for i2c mux gpio
+ *
+ * @values: the reg value of each child node
+ * @n_values: num of regs
+ * @gpios: the mux-gpios array
+ * @n_gpios: num of gpios in mux-gpios
+ * @idle: the value of idle-state
+ */
+struct i2c_mux_gpio_priv {
+ u32 *values;
+ int n_values;
+ struct gpio_desc *gpios;
+ int n_gpios;
+ u32 idle;
+};
+
+
+static int i2c_mux_gpio_select(struct udevice *dev, struct udevice *bus,
+ uint channel)
+{
+ struct i2c_mux_gpio_priv *priv = dev_get_priv(dev);
+ int i, ret;
+
+ for (i = 0; i < priv->n_gpios; i++) {
+ ret = dm_gpio_set_value(&priv->gpios[i], (channel >> i) & 1);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int i2c_mux_gpio_deselect(struct udevice *dev, struct udevice *bus,
+ uint channel)
+{
+ struct i2c_mux_gpio_priv *priv = dev_get_priv(dev);
+ int i, ret;
+
+ for (i = 0; i < priv->n_gpios; i++) {
+ ret = dm_gpio_set_value(&priv->gpios[i], (priv->idle >> i) & 1);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int i2c_mux_gpio_probe(struct udevice *dev)
+{
+ const void *fdt = gd->fdt_blob;
+ int node = dev_of_offset(dev);
+ struct i2c_mux_gpio_priv *mux = dev_get_priv(dev);
+ struct gpio_desc *gpios;
+ u32 *values;
+ int i = 0, subnode, ret;
+
+ mux->n_values = fdtdec_get_child_count(fdt, node);
+ values = devm_kzalloc(dev, sizeof(*mux->values) * mux->n_values,
+ GFP_KERNEL);
+ if (!values) {
+ dev_err(dev, "Cannot alloc values array");
+ return -ENOMEM;
+ }
+
+ fdt_for_each_subnode(subnode, fdt, node) {
+ *(values + i) = fdtdec_get_uint(fdt, subnode, "reg", -1);
+ i++;
+ }
+
+ mux->values = values;
+
+ mux->idle = fdtdec_get_uint(fdt, node, "idle-state", -1);
+
+ mux->n_gpios = gpio_get_list_count(dev, "mux-gpios");
+ if (mux->n_gpios < 0) {
+ dev_err(dev, "Missing mux-gpios property\n");
+ return -EINVAL;
+ }
+
+ gpios = devm_kzalloc(dev, sizeof(struct gpio_desc) * mux->n_gpios,
+ GFP_KERNEL);
+ if (!gpios) {
+ dev_err(dev, "Cannot allocate gpios array\n");
+ return -ENOMEM;
+ }
+
+ ret = gpio_request_list_by_name(dev, "mux-gpios", gpios, mux->n_gpios,
+ GPIOD_IS_OUT_ACTIVE);
+ if (ret <= 0) {
+ dev_err(dev, "Failed to request mux-gpios\n");
+ return ret;
+ }
+
+ mux->gpios = gpios;
+
+ return 0;
+}
+
+static const struct i2c_mux_ops i2c_mux_gpio_ops = {
+ .select = i2c_mux_gpio_select,
+ .deselect = i2c_mux_gpio_deselect,
+};
+
+static const struct udevice_id i2c_mux_gpio_ids[] = {
+ { .compatible = "i2c-mux-gpio", },
+ {}
+};
+
+U_BOOT_DRIVER(i2c_mux_gpio) = {
+ .name = "i2c_mux_gpio",
+ .id = UCLASS_I2C_MUX,
+ .of_match = i2c_mux_gpio_ids,
+ .ops = &i2c_mux_gpio_ops,
+ .probe = i2c_mux_gpio_probe,
+ .priv_auto_alloc_size = sizeof(struct i2c_mux_gpio_priv),
+};
diff --git a/drivers/i2c/stm32f7_i2c.c b/drivers/i2c/stm32f7_i2c.c
new file mode 100644
index 00000000000..bf5fefab7bf
--- /dev/null
+++ b/drivers/i2c/stm32f7_i2c.c
@@ -0,0 +1,882 @@
+/*
+ * (C) Copyright 2017 STMicroelectronics
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <i2c.h>
+#include <reset.h>
+
+#include <dm/device.h>
+#include <linux/io.h>
+
+/* STM32 I2C registers */
+struct stm32_i2c_regs {
+ u32 cr1; /* I2C control register 1 */
+ u32 cr2; /* I2C control register 2 */
+ u32 oar1; /* I2C own address 1 register */
+ u32 oar2; /* I2C own address 2 register */
+ u32 timingr; /* I2C timing register */
+ u32 timeoutr; /* I2C timeout register */
+ u32 isr; /* I2C interrupt and status register */
+ u32 icr; /* I2C interrupt clear register */
+ u32 pecr; /* I2C packet error checking register */
+ u32 rxdr; /* I2C receive data register */
+ u32 txdr; /* I2C transmit data register */
+};
+
+#define STM32_I2C_CR1 0x00
+#define STM32_I2C_CR2 0x04
+#define STM32_I2C_TIMINGR 0x10
+#define STM32_I2C_ISR 0x18
+#define STM32_I2C_ICR 0x1C
+#define STM32_I2C_RXDR 0x24
+#define STM32_I2C_TXDR 0x28
+
+/* STM32 I2C control 1 */
+#define STM32_I2C_CR1_ANFOFF BIT(12)
+#define STM32_I2C_CR1_ERRIE BIT(7)
+#define STM32_I2C_CR1_TCIE BIT(6)
+#define STM32_I2C_CR1_STOPIE BIT(5)
+#define STM32_I2C_CR1_NACKIE BIT(4)
+#define STM32_I2C_CR1_ADDRIE BIT(3)
+#define STM32_I2C_CR1_RXIE BIT(2)
+#define STM32_I2C_CR1_TXIE BIT(1)
+#define STM32_I2C_CR1_PE BIT(0)
+
+/* STM32 I2C control 2 */
+#define STM32_I2C_CR2_AUTOEND BIT(25)
+#define STM32_I2C_CR2_RELOAD BIT(24)
+#define STM32_I2C_CR2_NBYTES_MASK GENMASK(23, 16)
+#define STM32_I2C_CR2_NBYTES(n) ((n & 0xff) << 16)
+#define STM32_I2C_CR2_NACK BIT(15)
+#define STM32_I2C_CR2_STOP BIT(14)
+#define STM32_I2C_CR2_START BIT(13)
+#define STM32_I2C_CR2_HEAD10R BIT(12)
+#define STM32_I2C_CR2_ADD10 BIT(11)
+#define STM32_I2C_CR2_RD_WRN BIT(10)
+#define STM32_I2C_CR2_SADD10_MASK GENMASK(9, 0)
+#define STM32_I2C_CR2_SADD10(n) ((n & STM32_I2C_CR2_SADD10_MASK))
+#define STM32_I2C_CR2_SADD7_MASK GENMASK(7, 1)
+#define STM32_I2C_CR2_SADD7(n) ((n & 0x7f) << 1)
+#define STM32_I2C_CR2_RESET_MASK (STM32_I2C_CR2_HEAD10R \
+ | STM32_I2C_CR2_NBYTES_MASK \
+ | STM32_I2C_CR2_SADD7_MASK \
+ | STM32_I2C_CR2_RELOAD \
+ | STM32_I2C_CR2_RD_WRN)
+
+/* STM32 I2C Interrupt Status */
+#define STM32_I2C_ISR_BUSY BIT(15)
+#define STM32_I2C_ISR_ARLO BIT(9)
+#define STM32_I2C_ISR_BERR BIT(8)
+#define STM32_I2C_ISR_TCR BIT(7)
+#define STM32_I2C_ISR_TC BIT(6)
+#define STM32_I2C_ISR_STOPF BIT(5)
+#define STM32_I2C_ISR_NACKF BIT(4)
+#define STM32_I2C_ISR_ADDR BIT(3)
+#define STM32_I2C_ISR_RXNE BIT(2)
+#define STM32_I2C_ISR_TXIS BIT(1)
+#define STM32_I2C_ISR_TXE BIT(0)
+#define STM32_I2C_ISR_ERRORS (STM32_I2C_ISR_BERR \
+ | STM32_I2C_ISR_ARLO)
+
+/* STM32 I2C Interrupt Clear */
+#define STM32_I2C_ICR_ARLOCF BIT(9)
+#define STM32_I2C_ICR_BERRCF BIT(8)
+#define STM32_I2C_ICR_STOPCF BIT(5)
+#define STM32_I2C_ICR_NACKCF BIT(4)
+
+/* STM32 I2C Timing */
+#define STM32_I2C_TIMINGR_PRESC(n) ((n & 0xf) << 28)
+#define STM32_I2C_TIMINGR_SCLDEL(n) ((n & 0xf) << 20)
+#define STM32_I2C_TIMINGR_SDADEL(n) ((n & 0xf) << 16)
+#define STM32_I2C_TIMINGR_SCLH(n) ((n & 0xff) << 8)
+#define STM32_I2C_TIMINGR_SCLL(n) (n & 0xff)
+
+#define STM32_I2C_MAX_LEN 0xff
+
+#define STM32_I2C_DNF_DEFAULT 0
+#define STM32_I2C_DNF_MAX 16
+
+#define STM32_I2C_ANALOG_FILTER_ENABLE 1
+#define STM32_I2C_ANALOG_FILTER_DELAY_MIN 50 /* ns */
+#define STM32_I2C_ANALOG_FILTER_DELAY_MAX 260 /* ns */
+
+#define STM32_I2C_RISE_TIME_DEFAULT 25 /* ns */
+#define STM32_I2C_FALL_TIME_DEFAULT 10 /* ns */
+
+#define STM32_PRESC_MAX BIT(4)
+#define STM32_SCLDEL_MAX BIT(4)
+#define STM32_SDADEL_MAX BIT(4)
+#define STM32_SCLH_MAX BIT(8)
+#define STM32_SCLL_MAX BIT(8)
+
+#define STM32_NSEC_PER_SEC 1000000000L
+
+#define STANDARD_RATE 100000
+#define FAST_RATE 400000
+#define FAST_PLUS_RATE 1000000
+
+enum stm32_i2c_speed {
+ STM32_I2C_SPEED_STANDARD, /* 100 kHz */
+ STM32_I2C_SPEED_FAST, /* 400 kHz */
+ STM32_I2C_SPEED_FAST_PLUS, /* 1 MHz */
+ STM32_I2C_SPEED_END,
+};
+
+/**
+ * struct stm32_i2c_spec - private i2c specification timing
+ * @rate: I2C bus speed (Hz)
+ * @rate_min: 80% of I2C bus speed (Hz)
+ * @rate_max: 120% of I2C bus speed (Hz)
+ * @fall_max: Max fall time of both SDA and SCL signals (ns)
+ * @rise_max: Max rise time of both SDA and SCL signals (ns)
+ * @hddat_min: Min data hold time (ns)
+ * @vddat_max: Max data valid time (ns)
+ * @sudat_min: Min data setup time (ns)
+ * @l_min: Min low period of the SCL clock (ns)
+ * @h_min: Min high period of the SCL clock (ns)
+ */
+
+struct stm32_i2c_spec {
+ u32 rate;
+ u32 rate_min;
+ u32 rate_max;
+ u32 fall_max;
+ u32 rise_max;
+ u32 hddat_min;
+ u32 vddat_max;
+ u32 sudat_min;
+ u32 l_min;
+ u32 h_min;
+};
+
+/**
+ * struct stm32_i2c_setup - private I2C timing setup parameters
+ * @speed: I2C speed mode (standard, Fast Plus)
+ * @speed_freq: I2C speed frequency (Hz)
+ * @clock_src: I2C clock source frequency (Hz)
+ * @rise_time: Rise time (ns)
+ * @fall_time: Fall time (ns)
+ * @dnf: Digital filter coefficient (0-16)
+ * @analog_filter: Analog filter delay (On/Off)
+ */
+struct stm32_i2c_setup {
+ enum stm32_i2c_speed speed;
+ u32 speed_freq;
+ u32 clock_src;
+ u32 rise_time;
+ u32 fall_time;
+ u8 dnf;
+ bool analog_filter;
+};
+
+/**
+ * struct stm32_i2c_timings - private I2C output parameters
+ * @prec: Prescaler value
+ * @scldel: Data setup time
+ * @sdadel: Data hold time
+ * @sclh: SCL high period (master mode)
+ * @sclh: SCL low period (master mode)
+ */
+struct stm32_i2c_timings {
+ struct list_head node;
+ u8 presc;
+ u8 scldel;
+ u8 sdadel;
+ u8 sclh;
+ u8 scll;
+};
+
+struct stm32_i2c_priv {
+ struct stm32_i2c_regs *regs;
+ struct clk clk;
+ struct stm32_i2c_setup *setup;
+ int speed;
+};
+
+static struct stm32_i2c_spec i2c_specs[] = {
+ [STM32_I2C_SPEED_STANDARD] = {
+ .rate = STANDARD_RATE,
+ .rate_min = 8000,
+ .rate_max = 120000,
+ .fall_max = 300,
+ .rise_max = 1000,
+ .hddat_min = 0,
+ .vddat_max = 3450,
+ .sudat_min = 250,
+ .l_min = 4700,
+ .h_min = 4000,
+ },
+ [STM32_I2C_SPEED_FAST] = {
+ .rate = FAST_RATE,
+ .rate_min = 320000,
+ .rate_max = 480000,
+ .fall_max = 300,
+ .rise_max = 300,
+ .hddat_min = 0,
+ .vddat_max = 900,
+ .sudat_min = 100,
+ .l_min = 1300,
+ .h_min = 600,
+ },
+ [STM32_I2C_SPEED_FAST_PLUS] = {
+ .rate = FAST_PLUS_RATE,
+ .rate_min = 800000,
+ .rate_max = 1200000,
+ .fall_max = 100,
+ .rise_max = 120,
+ .hddat_min = 0,
+ .vddat_max = 450,
+ .sudat_min = 50,
+ .l_min = 500,
+ .h_min = 260,
+ },
+};
+
+static struct stm32_i2c_setup stm32f7_setup = {
+ .rise_time = STM32_I2C_RISE_TIME_DEFAULT,
+ .fall_time = STM32_I2C_FALL_TIME_DEFAULT,
+ .dnf = STM32_I2C_DNF_DEFAULT,
+ .analog_filter = STM32_I2C_ANALOG_FILTER_ENABLE,
+};
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int stm32_i2c_check_device_busy(struct stm32_i2c_priv *i2c_priv)
+{
+ struct stm32_i2c_regs *regs = i2c_priv->regs;
+ u32 status = readl(&regs->isr);
+
+ if (status & STM32_I2C_ISR_BUSY)
+ return -EBUSY;
+
+ return 0;
+}
+
+static void stm32_i2c_message_start(struct stm32_i2c_priv *i2c_priv,
+ struct i2c_msg *msg, bool stop)
+{
+ struct stm32_i2c_regs *regs = i2c_priv->regs;
+ u32 cr2 = readl(&regs->cr2);
+
+ /* Set transfer direction */
+ cr2 &= ~STM32_I2C_CR2_RD_WRN;
+ if (msg->flags & I2C_M_RD)
+ cr2 |= STM32_I2C_CR2_RD_WRN;
+
+ /* Set slave address */
+ cr2 &= ~(STM32_I2C_CR2_HEAD10R | STM32_I2C_CR2_ADD10);
+ if (msg->flags & I2C_M_TEN) {
+ cr2 &= ~STM32_I2C_CR2_SADD10_MASK;
+ cr2 |= STM32_I2C_CR2_SADD10(msg->addr);
+ cr2 |= STM32_I2C_CR2_ADD10;
+ } else {
+ cr2 &= ~STM32_I2C_CR2_SADD7_MASK;
+ cr2 |= STM32_I2C_CR2_SADD7(msg->addr);
+ }
+
+ /* Set nb bytes to transfer and reload or autoend bits */
+ cr2 &= ~(STM32_I2C_CR2_NBYTES_MASK | STM32_I2C_CR2_RELOAD |
+ STM32_I2C_CR2_AUTOEND);
+ if (msg->len > STM32_I2C_MAX_LEN) {
+ cr2 |= STM32_I2C_CR2_NBYTES(STM32_I2C_MAX_LEN);
+ cr2 |= STM32_I2C_CR2_RELOAD;
+ } else {
+ cr2 |= STM32_I2C_CR2_NBYTES(msg->len);
+ }
+
+ /* Write configurations register */
+ writel(cr2, &regs->cr2);
+
+ /* START/ReSTART generation */
+ setbits_le32(&regs->cr2, STM32_I2C_CR2_START);
+}
+
+/*
+ * RELOAD mode must be selected if total number of data bytes to be
+ * sent is greater than MAX_LEN
+ */
+
+static void stm32_i2c_handle_reload(struct stm32_i2c_priv *i2c_priv,
+ struct i2c_msg *msg, bool stop)
+{
+ struct stm32_i2c_regs *regs = i2c_priv->regs;
+ u32 cr2 = readl(&regs->cr2);
+
+ cr2 &= ~STM32_I2C_CR2_NBYTES_MASK;
+
+ if (msg->len > STM32_I2C_MAX_LEN) {
+ cr2 |= STM32_I2C_CR2_NBYTES(STM32_I2C_MAX_LEN);
+ } else {
+ cr2 &= ~STM32_I2C_CR2_RELOAD;
+ cr2 |= STM32_I2C_CR2_NBYTES(msg->len);
+ }
+
+ writel(cr2, &regs->cr2);
+}
+
+static int stm32_i2c_wait_flags(struct stm32_i2c_priv *i2c_priv,
+ u32 flags, u32 *status)
+{
+ struct stm32_i2c_regs *regs = i2c_priv->regs;
+ u32 time_start = get_timer(0);
+
+ *status = readl(&regs->isr);
+ while (!(*status & flags)) {
+ if (get_timer(time_start) > CONFIG_SYS_HZ) {
+ debug("%s: i2c timeout\n", __func__);
+ return -ETIMEDOUT;
+ }
+
+ *status = readl(&regs->isr);
+ }
+
+ return 0;
+}
+
+static int stm32_i2c_check_end_of_message(struct stm32_i2c_priv *i2c_priv)
+{
+ struct stm32_i2c_regs *regs = i2c_priv->regs;
+ u32 mask = STM32_I2C_ISR_ERRORS | STM32_I2C_ISR_NACKF |
+ STM32_I2C_ISR_STOPF;
+ u32 status;
+ int ret;
+
+ ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
+ if (ret)
+ return ret;
+
+ if (status & STM32_I2C_ISR_BERR) {
+ debug("%s: Bus error\n", __func__);
+
+ /* Clear BERR flag */
+ setbits_le32(&regs->icr, STM32_I2C_ICR_BERRCF);
+
+ return -EIO;
+ }
+
+ if (status & STM32_I2C_ISR_ARLO) {
+ debug("%s: Arbitration lost\n", __func__);
+
+ /* Clear ARLO flag */
+ setbits_le32(&regs->icr, STM32_I2C_ICR_ARLOCF);
+
+ return -EAGAIN;
+ }
+
+ if (status & STM32_I2C_ISR_NACKF) {
+ debug("%s: Receive NACK\n", __func__);
+
+ /* Clear NACK flag */
+ setbits_le32(&regs->icr, STM32_I2C_ICR_NACKCF);
+
+ /* Wait until STOPF flag is set */
+ mask = STM32_I2C_ISR_STOPF;
+ ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
+ if (ret)
+ return ret;
+
+ ret = -EIO;
+ }
+
+ if (status & STM32_I2C_ISR_STOPF) {
+ /* Clear STOP flag */
+ setbits_le32(&regs->icr, STM32_I2C_ICR_STOPCF);
+
+ /* Clear control register 2 */
+ setbits_le32(&regs->cr2, STM32_I2C_CR2_RESET_MASK);
+ }
+
+ return ret;
+}
+
+static int stm32_i2c_message_xfer(struct stm32_i2c_priv *i2c_priv,
+ struct i2c_msg *msg, bool stop)
+{
+ struct stm32_i2c_regs *regs = i2c_priv->regs;
+ u32 status;
+ u32 mask = msg->flags & I2C_M_RD ? STM32_I2C_ISR_RXNE :
+ STM32_I2C_ISR_TXIS | STM32_I2C_ISR_NACKF;
+ int bytes_to_rw = msg->len > STM32_I2C_MAX_LEN ?
+ STM32_I2C_MAX_LEN : msg->len;
+ int ret = 0;
+
+ /* Add errors */
+ mask |= STM32_I2C_ISR_ERRORS;
+
+ stm32_i2c_message_start(i2c_priv, msg, stop);
+
+ while (msg->len) {
+ /*
+ * Wait until TXIS/NACKF/BERR/ARLO flags or
+ * RXNE/BERR/ARLO flags are set
+ */
+ ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
+ if (ret)
+ break;
+
+ if (status & (STM32_I2C_ISR_NACKF | STM32_I2C_ISR_ERRORS))
+ break;
+
+ if (status & STM32_I2C_ISR_RXNE) {
+ *msg->buf++ = readb(&regs->rxdr);
+ msg->len--;
+ bytes_to_rw--;
+ }
+
+ if (status & STM32_I2C_ISR_TXIS) {
+ writeb(*msg->buf++, &regs->txdr);
+ msg->len--;
+ bytes_to_rw--;
+ }
+
+ if (!bytes_to_rw && msg->len) {
+ /* Wait until TCR flag is set */
+ mask = STM32_I2C_ISR_TCR;
+ ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
+ if (ret)
+ break;
+
+ bytes_to_rw = msg->len > STM32_I2C_MAX_LEN ?
+ STM32_I2C_MAX_LEN : msg->len;
+ mask = msg->flags & I2C_M_RD ? STM32_I2C_ISR_RXNE :
+ STM32_I2C_ISR_TXIS | STM32_I2C_ISR_NACKF;
+
+ stm32_i2c_handle_reload(i2c_priv, msg, stop);
+ } else if (!bytes_to_rw) {
+ /* Wait until TC flag is set */
+ mask = STM32_I2C_ISR_TC;
+ ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
+ if (ret)
+ break;
+
+ if (!stop)
+ /* Message sent, new message has to be sent */
+ return 0;
+ }
+ }
+
+ /* End of transfer, send stop condition */
+ mask = STM32_I2C_CR2_STOP;
+ setbits_le32(&regs->cr2, mask);
+
+ return stm32_i2c_check_end_of_message(i2c_priv);
+}
+
+static int stm32_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
+ int nmsgs)
+{
+ struct stm32_i2c_priv *i2c_priv = dev_get_priv(bus);
+ int ret;
+
+ ret = stm32_i2c_check_device_busy(i2c_priv);
+ if (ret)
+ return ret;
+
+ for (; nmsgs > 0; nmsgs--, msg++) {
+ ret = stm32_i2c_message_xfer(i2c_priv, msg, nmsgs == 1);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int stm32_i2c_compute_solutions(struct stm32_i2c_setup *setup,
+ struct list_head *solutions)
+{
+ struct stm32_i2c_timings *v;
+ u32 p_prev = STM32_PRESC_MAX;
+ u32 i2cclk = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC,
+ setup->clock_src);
+ u32 af_delay_min, af_delay_max;
+ u16 p, l, a;
+ int sdadel_min, sdadel_max, scldel_min;
+ int ret = 0;
+
+ af_delay_min = setup->analog_filter ?
+ STM32_I2C_ANALOG_FILTER_DELAY_MIN : 0;
+ af_delay_max = setup->analog_filter ?
+ STM32_I2C_ANALOG_FILTER_DELAY_MAX : 0;
+
+ sdadel_min = setup->fall_time - i2c_specs[setup->speed].hddat_min -
+ af_delay_min - (setup->dnf + 3) * i2cclk;
+
+ sdadel_max = i2c_specs[setup->speed].vddat_max - setup->rise_time -
+ af_delay_max - (setup->dnf + 4) * i2cclk;
+
+ scldel_min = setup->rise_time + i2c_specs[setup->speed].sudat_min;
+
+ if (sdadel_min < 0)
+ sdadel_min = 0;
+ if (sdadel_max < 0)
+ sdadel_max = 0;
+
+ debug("%s: SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n", __func__,
+ sdadel_min, sdadel_max, scldel_min);
+
+ /* Compute possible values for PRESC, SCLDEL and SDADEL */
+ for (p = 0; p < STM32_PRESC_MAX; p++) {
+ for (l = 0; l < STM32_SCLDEL_MAX; l++) {
+ u32 scldel = (l + 1) * (p + 1) * i2cclk;
+
+ if (scldel < scldel_min)
+ continue;
+
+ for (a = 0; a < STM32_SDADEL_MAX; a++) {
+ u32 sdadel = (a * (p + 1) + 1) * i2cclk;
+
+ if (((sdadel >= sdadel_min) &&
+ (sdadel <= sdadel_max)) &&
+ (p != p_prev)) {
+ v = kmalloc(sizeof(*v), GFP_KERNEL);
+ if (!v)
+ return -ENOMEM;
+
+ v->presc = p;
+ v->scldel = l;
+ v->sdadel = a;
+ p_prev = p;
+
+ list_add_tail(&v->node, solutions);
+ }
+ }
+ }
+ }
+
+ if (list_empty(solutions)) {
+ error("%s: no Prescaler solution\n", __func__);
+ ret = -EPERM;
+ }
+
+ return ret;
+}
+
+static int stm32_i2c_choose_solution(struct stm32_i2c_setup *setup,
+ struct list_head *solutions,
+ struct stm32_i2c_timings *s)
+{
+ struct stm32_i2c_timings *v;
+ u32 i2cbus = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC,
+ setup->speed_freq);
+ u32 clk_error_prev = i2cbus;
+ u32 i2cclk = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC,
+ setup->clock_src);
+ u32 clk_min, clk_max;
+ u32 af_delay_min;
+ u32 dnf_delay;
+ u32 tsync;
+ u16 l, h;
+ int ret = 0;
+
+ af_delay_min = setup->analog_filter ?
+ STM32_I2C_ANALOG_FILTER_DELAY_MIN : 0;
+ dnf_delay = setup->dnf * i2cclk;
+
+ tsync = af_delay_min + dnf_delay + (2 * i2cclk);
+ clk_max = STM32_NSEC_PER_SEC / i2c_specs[setup->speed].rate_min;
+ clk_min = STM32_NSEC_PER_SEC / i2c_specs[setup->speed].rate_max;
+
+ /*
+ * Among Prescaler possibilities discovered above figures out SCL Low
+ * and High Period. Provided:
+ * - SCL Low Period has to be higher than Low Period of the SCL Clock
+ * defined by I2C Specification. I2C Clock has to be lower than
+ * (SCL Low Period - Analog/Digital filters) / 4.
+ * - SCL High Period has to be lower than High Period of the SCL Clock
+ * defined by I2C Specification
+ * - I2C Clock has to be lower than SCL High Period
+ */
+ list_for_each_entry(v, solutions, node) {
+ u32 prescaler = (v->presc + 1) * i2cclk;
+
+ for (l = 0; l < STM32_SCLL_MAX; l++) {
+ u32 tscl_l = (l + 1) * prescaler + tsync;
+ if ((tscl_l < i2c_specs[setup->speed].l_min) ||
+ (i2cclk >=
+ ((tscl_l - af_delay_min - dnf_delay) / 4))) {
+ continue;
+ }
+
+ for (h = 0; h < STM32_SCLH_MAX; h++) {
+ u32 tscl_h = (h + 1) * prescaler + tsync;
+ u32 tscl = tscl_l + tscl_h +
+ setup->rise_time + setup->fall_time;
+
+ if ((tscl >= clk_min) && (tscl <= clk_max) &&
+ (tscl_h >= i2c_specs[setup->speed].h_min) &&
+ (i2cclk < tscl_h)) {
+ int clk_error = tscl - i2cbus;
+
+ if (clk_error < 0)
+ clk_error = -clk_error;
+
+ if (clk_error < clk_error_prev) {
+ clk_error_prev = clk_error;
+ v->scll = l;
+ v->sclh = h;
+ s = v;
+ }
+ }
+ }
+ }
+ }
+
+ if (!s) {
+ error("%s: no solution at all\n", __func__);
+ ret = -EPERM;
+ }
+
+ return ret;
+}
+
+static int stm32_i2c_compute_timing(struct stm32_i2c_priv *i2c_priv,
+ struct stm32_i2c_setup *setup,
+ struct stm32_i2c_timings *output)
+{
+ struct stm32_i2c_timings *v, *_v, *s;
+ struct list_head solutions;
+ int ret;
+
+ if (setup->speed >= STM32_I2C_SPEED_END) {
+ error("%s: speed out of bound {%d/%d}\n", __func__,
+ setup->speed, STM32_I2C_SPEED_END - 1);
+ return -EINVAL;
+ }
+
+ if ((setup->rise_time > i2c_specs[setup->speed].rise_max) ||
+ (setup->fall_time > i2c_specs[setup->speed].fall_max)) {
+ error("%s :timings out of bound Rise{%d>%d}/Fall{%d>%d}\n",
+ __func__,
+ setup->rise_time, i2c_specs[setup->speed].rise_max,
+ setup->fall_time, i2c_specs[setup->speed].fall_max);
+ return -EINVAL;
+ }
+
+ if (setup->dnf > STM32_I2C_DNF_MAX) {
+ error("%s: DNF out of bound %d/%d\n", __func__,
+ setup->dnf, STM32_I2C_DNF_MAX);
+ return -EINVAL;
+ }
+
+ if (setup->speed_freq > i2c_specs[setup->speed].rate) {
+ error("%s: Freq {%d/%d}\n", __func__,
+ setup->speed_freq, i2c_specs[setup->speed].rate);
+ return -EINVAL;
+ }
+
+ s = NULL;
+ INIT_LIST_HEAD(&solutions);
+ ret = stm32_i2c_compute_solutions(setup, &solutions);
+ if (ret)
+ goto exit;
+
+ ret = stm32_i2c_choose_solution(setup, &solutions, s);
+ if (ret)
+ goto exit;
+
+ output->presc = s->presc;
+ output->scldel = s->scldel;
+ output->sdadel = s->sdadel;
+ output->scll = s->scll;
+ output->sclh = s->sclh;
+
+ debug("%s: Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n",
+ __func__, output->presc,
+ output->scldel, output->sdadel,
+ output->scll, output->sclh);
+
+exit:
+ /* Release list and memory */
+ list_for_each_entry_safe(v, _v, &solutions, node) {
+ list_del(&v->node);
+ kfree(v);
+ }
+
+ return ret;
+}
+
+static int stm32_i2c_setup_timing(struct stm32_i2c_priv *i2c_priv,
+ struct stm32_i2c_timings *timing)
+{
+ struct stm32_i2c_setup *setup = i2c_priv->setup;
+ int ret = 0;
+
+ setup->speed = i2c_priv->speed;
+ setup->speed_freq = i2c_specs[setup->speed].rate;
+ setup->clock_src = clk_get_rate(&i2c_priv->clk);
+
+ if (!setup->clock_src) {
+ error("%s: clock rate is 0\n", __func__);
+ return -EINVAL;
+ }
+
+ do {
+ ret = stm32_i2c_compute_timing(i2c_priv, setup, timing);
+ if (ret) {
+ debug("%s: failed to compute I2C timings.\n",
+ __func__);
+ if (i2c_priv->speed > STM32_I2C_SPEED_STANDARD) {
+ i2c_priv->speed--;
+ setup->speed = i2c_priv->speed;
+ setup->speed_freq =
+ i2c_specs[setup->speed].rate;
+ debug("%s: downgrade I2C Speed Freq to (%i)\n",
+ __func__, i2c_specs[setup->speed].rate);
+ } else {
+ break;
+ }
+ }
+ } while (ret);
+
+ if (ret) {
+ error("%s: impossible to compute I2C timings.\n", __func__);
+ return ret;
+ }
+
+ debug("%s: I2C Speed(%i), Freq(%i), Clk Source(%i)\n", __func__,
+ setup->speed, setup->speed_freq, setup->clock_src);
+ debug("%s: I2C Rise(%i) and Fall(%i) Time\n", __func__,
+ setup->rise_time, setup->fall_time);
+ debug("%s: I2C Analog Filter(%s), DNF(%i)\n", __func__,
+ setup->analog_filter ? "On" : "Off", setup->dnf);
+
+ return 0;
+}
+
+static int stm32_i2c_hw_config(struct stm32_i2c_priv *i2c_priv)
+{
+ struct stm32_i2c_regs *regs = i2c_priv->regs;
+ struct stm32_i2c_timings t;
+ int ret;
+ u32 timing = 0;
+
+ ret = stm32_i2c_setup_timing(i2c_priv, &t);
+ if (ret)
+ return ret;
+
+ /* Disable I2C */
+ clrbits_le32(&regs->cr1, STM32_I2C_CR1_PE);
+
+ /* Timing settings */
+ timing |= STM32_I2C_TIMINGR_PRESC(t.presc);
+ timing |= STM32_I2C_TIMINGR_SCLDEL(t.scldel);
+ timing |= STM32_I2C_TIMINGR_SDADEL(t.sdadel);
+ timing |= STM32_I2C_TIMINGR_SCLH(t.sclh);
+ timing |= STM32_I2C_TIMINGR_SCLL(t.scll);
+ writel(timing, &regs->timingr);
+
+ /* Enable I2C */
+ if (i2c_priv->setup->analog_filter)
+ clrbits_le32(&regs->cr1, STM32_I2C_CR1_ANFOFF);
+ else
+ setbits_le32(&regs->cr1, STM32_I2C_CR1_ANFOFF);
+ setbits_le32(&regs->cr1, STM32_I2C_CR1_PE);
+
+ return 0;
+}
+
+static int stm32_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
+{
+ struct stm32_i2c_priv *i2c_priv = dev_get_priv(bus);
+
+ switch (speed) {
+ case STANDARD_RATE:
+ i2c_priv->speed = STM32_I2C_SPEED_STANDARD;
+ break;
+ case FAST_RATE:
+ i2c_priv->speed = STM32_I2C_SPEED_FAST;
+ break;
+ case FAST_PLUS_RATE:
+ i2c_priv->speed = STM32_I2C_SPEED_FAST_PLUS;
+ break;
+ default:
+ debug("%s: Speed %d not supported\n", __func__, speed);
+ return -EINVAL;
+ }
+
+ return stm32_i2c_hw_config(i2c_priv);
+}
+
+static int stm32_i2c_probe(struct udevice *dev)
+{
+ struct stm32_i2c_priv *i2c_priv = dev_get_priv(dev);
+ struct reset_ctl reset_ctl;
+ fdt_addr_t addr;
+ int ret;
+
+ addr = dev_read_addr(dev);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ i2c_priv->regs = (struct stm32_i2c_regs *)addr;
+
+ ret = clk_get_by_index(dev, 0, &i2c_priv->clk);
+ if (ret)
+ return ret;
+
+ ret = clk_enable(&i2c_priv->clk);
+ if (ret)
+ goto clk_free;
+
+ ret = reset_get_by_index(dev, 0, &reset_ctl);
+ if (ret)
+ goto clk_disable;
+
+ reset_assert(&reset_ctl);
+ udelay(2);
+ reset_deassert(&reset_ctl);
+
+ return 0;
+
+clk_disable:
+ clk_disable(&i2c_priv->clk);
+clk_free:
+ clk_free(&i2c_priv->clk);
+
+ return ret;
+}
+
+static int stm32_ofdata_to_platdata(struct udevice *dev)
+{
+ struct stm32_i2c_priv *i2c_priv = dev_get_priv(dev);
+ u32 rise_time, fall_time;
+
+ i2c_priv->setup = (struct stm32_i2c_setup *)dev_get_driver_data(dev);
+ if (!i2c_priv->setup)
+ return -EINVAL;
+
+ rise_time = dev_read_u32_default(dev, "i2c-scl-rising-time-ns", 0);
+ if (rise_time)
+ i2c_priv->setup->rise_time = rise_time;
+
+ fall_time = dev_read_u32_default(dev, "i2c-scl-falling-time-ns", 0);
+ if (fall_time)
+ i2c_priv->setup->fall_time = fall_time;
+
+ return 0;
+}
+
+static const struct dm_i2c_ops stm32_i2c_ops = {
+ .xfer = stm32_i2c_xfer,
+ .set_bus_speed = stm32_i2c_set_bus_speed,
+};
+
+static const struct udevice_id stm32_i2c_of_match[] = {
+ { .compatible = "st,stm32f7-i2c", .data = (ulong)&stm32f7_setup },
+ {}
+};
+
+U_BOOT_DRIVER(stm32f7_i2c) = {
+ .name = "stm32f7-i2c",
+ .id = UCLASS_I2C,
+ .of_match = stm32_i2c_of_match,
+ .ofdata_to_platdata = stm32_ofdata_to_platdata,
+ .probe = stm32_i2c_probe,
+ .priv_auto_alloc_size = sizeof(struct stm32_i2c_priv),
+ .ops = &stm32_i2c_ops,
+};
diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c
index 42bc2efd90d..f3bb72788a9 100644
--- a/drivers/mtd/cfi_flash.c
+++ b/drivers/mtd/cfi_flash.c
@@ -178,7 +178,7 @@ __maybe_weak u64 flash_read64(void *addr)
/*-----------------------------------------------------------------------
*/
#if defined(CONFIG_ENV_IS_IN_FLASH) || defined(CONFIG_ENV_ADDR_REDUND) || (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE)
-flash_info_t *flash_get_info(ulong base)
+static flash_info_t *flash_get_info(ulong base)
{
int i;
flash_info_t *info;
@@ -355,8 +355,8 @@ static ulong flash_read_long (flash_info_t * info, flash_sect_t sect,
/*
* Write a proper sized command to the correct address
*/
-void flash_write_cmd (flash_info_t * info, flash_sect_t sect,
- uint offset, u32 cmd)
+static void flash_write_cmd(flash_info_t *info, flash_sect_t sect,
+ uint offset, u32 cmd)
{
void *addr;
@@ -2298,7 +2298,7 @@ static void cfi_flash_set_config_reg(u32 base, u16 val)
/*-----------------------------------------------------------------------
*/
-void flash_protect_default(void)
+static void flash_protect_default(void)
{
#if defined(CONFIG_SYS_FLASH_AUTOPROTECT_LIST)
int i;
diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c
index 75fb0933371..46fe5e62471 100644
--- a/drivers/pci/pci_rom.c
+++ b/drivers/pci/pci_rom.c
@@ -202,47 +202,6 @@ static int pci_rom_load(struct pci_rom_header *rom_header,
struct vbe_mode_info mode_info;
-int vbe_get_video_info(struct graphic_device *gdev)
-{
-#ifdef CONFIG_FRAMEBUFFER_SET_VESA_MODE
- struct vesa_mode_info *vesa = &mode_info.vesa;
-
- gdev->winSizeX = vesa->x_resolution;
- gdev->winSizeY = vesa->y_resolution;
-
- gdev->plnSizeX = vesa->x_resolution;
- gdev->plnSizeY = vesa->y_resolution;
-
- gdev->gdfBytesPP = vesa->bits_per_pixel / 8;
-
- switch (vesa->bits_per_pixel) {
- case 32:
- case 24:
- gdev->gdfIndex = GDF_32BIT_X888RGB;
- break;
- case 16:
- gdev->gdfIndex = GDF_16BIT_565RGB;
- break;
- default:
- gdev->gdfIndex = GDF__8BIT_INDEX;
- break;
- }
-
- gdev->isaBase = CONFIG_SYS_ISA_IO_BASE_ADDRESS;
- gdev->pciBase = vesa->phys_base_ptr;
-
- gdev->frameAdrs = vesa->phys_base_ptr;
- gdev->memSize = vesa->bytes_per_scanline * vesa->y_resolution;
-
- gdev->vprBase = vesa->phys_base_ptr;
- gdev->cprBase = vesa->phys_base_ptr;
-
- return gdev->winSizeX ? 0 : -ENOSYS;
-#else
- return -ENOSYS;
-#endif
-}
-
void setup_video(struct screen_info *screen_info)
{
struct vesa_mode_info *vesa = &mode_info.vesa;
diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig
index 836be25507b..47969f3f281 100644
--- a/drivers/ram/Kconfig
+++ b/drivers/ram/Kconfig
@@ -18,7 +18,7 @@ config SPL_RAM
setting up RAM (e.g. SDRAM / DDR) within SPL.
config TPL_RAM
- bool "Enable RAM support in SPL"
+ bool "Enable RAM support in TPL"
depends on RAM && TPL_DM
help
The RAM subsystem adds a small amount of overhead to the image.
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index a8e997834ad..aeed538fa4e 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -64,15 +64,20 @@ config DM_SERIAL
implements serial_putc() etc. The uclass interface is
defined in include/serial.h.
-config SERIAL_IRQ_BUFFER
- bool "Enable RX interrupt buffer for serial input"
+config SERIAL_RX_BUFFER
+ bool "Enable RX buffer for serial input"
depends on DM_SERIAL
- default n
help
- Enable RX interrupt buffer support for the serial driver.
- This enables pasting longer strings, even when the RX FIFO
- of the UART is not big enough (e.g. 16 bytes on the normal
- NS16550).
+ Enable RX buffer support for the serial driver. This enables
+ pasting longer strings, even when the RX FIFO of the UART is
+ not big enough (e.g. 16 bytes on the normal NS16550).
+
+config SERIAL_RX_BUFFER_SIZE
+ int "RX buffer size"
+ depends on SERIAL_RX_BUFFER
+ default 256
+ help
+ The size of the RX buffer (needs to be power of 2)
config SPL_DM_SERIAL
bool "Enable Driver Model for serial drivers in SPL"
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 607a1b8c1de..c702304e79b 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -314,80 +314,6 @@ DEBUG_UART_FUNCS
#endif
#ifdef CONFIG_DM_SERIAL
-
-#if CONFIG_IS_ENABLED(SERIAL_IRQ_BUFFER)
-
-#define BUF_COUNT 256
-
-static void rx_fifo_to_buf(struct udevice *dev)
-{
- struct NS16550 *const com_port = dev_get_priv(dev);
- struct ns16550_platdata *plat = dev->platdata;
-
- /* Read all available chars into buffer */
- while ((serial_in(&com_port->lsr) & UART_LSR_DR)) {
- plat->buf[plat->wr_ptr++] = serial_in(&com_port->rbr);
- plat->wr_ptr %= BUF_COUNT;
- }
-}
-
-static int rx_pending(struct udevice *dev)
-{
- struct ns16550_platdata *plat = dev->platdata;
-
- /*
- * At startup it may happen, that some already received chars are
- * "stuck" in the RX FIFO, even with the interrupt enabled. This
- * RX FIFO flushing makes sure, that these chars are read out and
- * the RX interrupts works as expected.
- */
- rx_fifo_to_buf(dev);
-
- return plat->rd_ptr != plat->wr_ptr ? 1 : 0;
-}
-
-static int rx_get(struct udevice *dev)
-{
- struct ns16550_platdata *plat = dev->platdata;
- char val;
-
- val = plat->buf[plat->rd_ptr++];
- plat->rd_ptr %= BUF_COUNT;
-
- return val;
-}
-
-void ns16550_handle_irq(void *data)
-{
- struct udevice *dev = (struct udevice *)data;
- struct NS16550 *const com_port = dev_get_priv(dev);
-
- /* Check if interrupt is pending */
- if (serial_in(&com_port->iir) & UART_IIR_NO_INT)
- return;
-
- /* Flush all available characters from the RX FIFO into the RX buffer */
- rx_fifo_to_buf(dev);
-}
-
-#else /* CONFIG_SERIAL_IRQ_BUFFER */
-
-static int rx_pending(struct udevice *dev)
-{
- struct NS16550 *const com_port = dev_get_priv(dev);
-
- return serial_in(&com_port->lsr) & UART_LSR_DR ? 1 : 0;
-}
-
-static int rx_get(struct udevice *dev)
-{
- struct NS16550 *const com_port = dev_get_priv(dev);
-
- return serial_in(&com_port->rbr);
-}
-
-#endif /* CONFIG_SERIAL_IRQ_BUFFER */
-
static int ns16550_serial_putc(struct udevice *dev, const char ch)
{
struct NS16550 *const com_port = dev_get_priv(dev);
@@ -413,17 +339,19 @@ static int ns16550_serial_pending(struct udevice *dev, bool input)
struct NS16550 *const com_port = dev_get_priv(dev);
if (input)
- return rx_pending(dev);
+ return serial_in(&com_port->lsr) & UART_LSR_DR ? 1 : 0;
else
return serial_in(&com_port->lsr) & UART_LSR_THRE ? 0 : 1;
}
static int ns16550_serial_getc(struct udevice *dev)
{
- if (!ns16550_serial_pending(dev, true))
+ struct NS16550 *const com_port = dev_get_priv(dev);
+
+ if (!(serial_in(&com_port->lsr) & UART_LSR_DR))
return -EAGAIN;
- return rx_get(dev);
+ return serial_in(&com_port->rbr);
}
static int ns16550_serial_setbrg(struct udevice *dev, int baudrate)
@@ -446,39 +374,8 @@ int ns16550_serial_probe(struct udevice *dev)
com_port->plat = dev_get_platdata(dev);
NS16550_init(com_port, -1);
-#if CONFIG_IS_ENABLED(SERIAL_IRQ_BUFFER)
- if (gd->flags & GD_FLG_RELOC) {
- struct ns16550_platdata *plat = dev->platdata;
-
- /* Allocate the RX buffer */
- plat->buf = malloc(BUF_COUNT);
-
- /* Install the interrupt handler */
- irq_install_handler(plat->irq, ns16550_handle_irq, dev);
-
- /* Enable RX interrupts */
- serial_out(UART_IER_RDI, &com_port->ier);
- }
-#endif
-
- return 0;
-}
-
-#if CONFIG_IS_ENABLED(SERIAL_PRESENT) && \
- (!defined(CONFIG_TPL_BUILD) || defined(CONFIG_TPL_DM_SERIAL))
-static int ns16550_serial_remove(struct udevice *dev)
-{
-#if CONFIG_IS_ENABLED(SERIAL_IRQ_BUFFER)
- if (gd->flags & GD_FLG_RELOC) {
- struct ns16550_platdata *plat = dev->platdata;
-
- irq_free_handler(plat->irq);
- }
-#endif
-
return 0;
}
-#endif
#if CONFIG_IS_ENABLED(OF_CONTROL)
enum {
@@ -561,15 +458,6 @@ int ns16550_serial_ofdata_to_platdata(struct udevice *dev)
if (port_type == PORT_JZ4780)
plat->fcr |= UART_FCR_UME;
-#if CONFIG_IS_ENABLED(SERIAL_IRQ_BUFFER)
- plat->irq = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
- "interrupts", 0);
- if (!plat->irq) {
- debug("ns16550 interrupt not provided\n");
- return -EINVAL;
- }
-#endif
-
return 0;
}
#endif
@@ -617,7 +505,6 @@ U_BOOT_DRIVER(ns16550_serial) = {
#endif
.priv_auto_alloc_size = sizeof(struct NS16550),
.probe = ns16550_serial_probe,
- .remove = ns16550_serial_remove,
.ops = &ns16550_serial_ops,
.flags = DM_FLAG_PRE_RELOC,
};
diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c
index 998d372da6b..2e5116f7cee 100644
--- a/drivers/serial/serial-uclass.c
+++ b/drivers/serial/serial-uclass.c
@@ -160,7 +160,7 @@ static void _serial_puts(struct udevice *dev, const char *str)
_serial_putc(dev, *str++);
}
-static int _serial_getc(struct udevice *dev)
+static int __serial_getc(struct udevice *dev)
{
struct dm_serial_ops *ops = serial_get_ops(dev);
int err;
@@ -174,7 +174,7 @@ static int _serial_getc(struct udevice *dev)
return err >= 0 ? err : 0;
}
-static int _serial_tstc(struct udevice *dev)
+static int __serial_tstc(struct udevice *dev)
{
struct dm_serial_ops *ops = serial_get_ops(dev);
@@ -184,6 +184,44 @@ static int _serial_tstc(struct udevice *dev)
return 1;
}
+#if CONFIG_IS_ENABLED(SERIAL_RX_BUFFER)
+static int _serial_tstc(struct udevice *dev)
+{
+ struct serial_dev_priv *upriv = dev_get_uclass_priv(dev);
+
+ /* Read all available chars into the RX buffer */
+ while (__serial_tstc(dev)) {
+ upriv->buf[upriv->wr_ptr++] = __serial_getc(dev);
+ upriv->wr_ptr %= CONFIG_SERIAL_RX_BUFFER_SIZE;
+ }
+
+ return upriv->rd_ptr != upriv->wr_ptr ? 1 : 0;
+}
+
+static int _serial_getc(struct udevice *dev)
+{
+ struct serial_dev_priv *upriv = dev_get_uclass_priv(dev);
+ char val;
+
+ val = upriv->buf[upriv->rd_ptr++];
+ upriv->rd_ptr %= CONFIG_SERIAL_RX_BUFFER_SIZE;
+
+ return val;
+}
+
+#else /* CONFIG_IS_ENABLED(SERIAL_RX_BUFFER) */
+
+static int _serial_getc(struct udevice *dev)
+{
+ return __serial_getc(dev);
+}
+
+static int _serial_tstc(struct udevice *dev)
+{
+ return __serial_tstc(dev);
+}
+#endif /* CONFIG_IS_ENABLED(SERIAL_RX_BUFFER) */
+
void serial_putc(char ch)
{
if (gd->cur_serial_dev)
@@ -359,6 +397,12 @@ static int serial_post_probe(struct udevice *dev)
sdev.puts = serial_stub_puts;
sdev.getc = serial_stub_getc;
sdev.tstc = serial_stub_tstc;
+
+#if CONFIG_IS_ENABLED(SERIAL_RX_BUFFER)
+ /* Allocate the RX buffer */
+ upriv->buf = malloc(CONFIG_SERIAL_RX_BUFFER_SIZE);
+#endif
+
stdio_register_dev(&sdev, &upriv->sdev);
#endif
return 0;
diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c
index bf2e99b5ccb..373bc2683b0 100644
--- a/drivers/spi/ich.c
+++ b/drivers/spi/ich.c
@@ -126,8 +126,6 @@ static int ich_init_controller(struct udevice *dev,
if (plat->ich_version == ICHV_7) {
struct ich7_spi_regs *ich7_spi = sbase;
- ich7_spi = (struct ich7_spi_regs *)sbase;
- ctlr->ichspi_lock = readw(&ich7_spi->spis) & SPIS_LOCK;
ctlr->opmenu = offsetof(struct ich7_spi_regs, opmenu);
ctlr->menubytes = sizeof(ich7_spi->opmenu);
ctlr->optype = offsetof(struct ich7_spi_regs, optype);
@@ -142,7 +140,6 @@ static int ich_init_controller(struct udevice *dev,
} else if (plat->ich_version == ICHV_9) {
struct ich9_spi_regs *ich9_spi = sbase;
- ctlr->ichspi_lock = readw(&ich9_spi->hsfs) & HSFS_FLOCKDN;
ctlr->opmenu = offsetof(struct ich9_spi_regs, opmenu);
ctlr->menubytes = sizeof(ich9_spi->opmenu);
ctlr->optype = offsetof(struct ich9_spi_regs, optype);
@@ -187,6 +184,23 @@ static inline void spi_use_in(struct spi_trans *trans, unsigned bytes)
trans->bytesin -= bytes;
}
+static bool spi_lock_status(struct ich_spi_platdata *plat, void *sbase)
+{
+ int lock = 0;
+
+ if (plat->ich_version == ICHV_7) {
+ struct ich7_spi_regs *ich7_spi = sbase;
+
+ lock = readw(&ich7_spi->spis) & SPIS_LOCK;
+ } else if (plat->ich_version == ICHV_9) {
+ struct ich9_spi_regs *ich9_spi = sbase;
+
+ lock = readw(&ich9_spi->hsfs) & HSFS_FLOCKDN;
+ }
+
+ return lock != 0;
+}
+
static void spi_setup_type(struct spi_trans *trans, int data_bytes)
{
trans->type = 0xFF;
@@ -220,14 +234,15 @@ static void spi_setup_type(struct spi_trans *trans, int data_bytes)
}
}
-static int spi_setup_opcode(struct ich_spi_priv *ctlr, struct spi_trans *trans)
+static int spi_setup_opcode(struct ich_spi_priv *ctlr, struct spi_trans *trans,
+ bool lock)
{
uint16_t optypes;
uint8_t opmenu[ctlr->menubytes];
trans->opcode = trans->out[0];
spi_use_out(trans, 1);
- if (!ctlr->ichspi_lock) {
+ if (!lock) {
/* The lock is off, so just use index 0. */
ich_writeb(ctlr, trans->opcode, ctlr->opmenu);
optypes = ich_readw(ctlr, ctlr->optype);
@@ -323,6 +338,21 @@ static int ich_status_poll(struct ich_spi_priv *ctlr, u16 bitmask,
return -ETIMEDOUT;
}
+void ich_spi_config_opcode(struct udevice *dev)
+{
+ struct ich_spi_priv *ctlr = dev_get_priv(dev);
+
+ /*
+ * PREOP, OPTYPE, OPMENU1/OPMENU2 registers can be locked down
+ * to prevent accidental or intentional writes. Before they get
+ * locked down, these registers should be initialized properly.
+ */
+ ich_writew(ctlr, SPI_OPPREFIX, ctlr->preop);
+ ich_writew(ctlr, SPI_OPTYPE, ctlr->optype);
+ ich_writel(ctlr, SPI_OPMENU_LOWER, ctlr->opmenu);
+ ich_writel(ctlr, SPI_OPMENU_UPPER, ctlr->opmenu + sizeof(u32));
+}
+
static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen,
const void *dout, void *din, unsigned long flags)
{
@@ -337,6 +367,7 @@ static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen,
struct spi_trans *trans = &ctlr->trans;
unsigned type = flags & (SPI_XFER_BEGIN | SPI_XFER_END);
int using_cmd = 0;
+ bool lock = spi_lock_status(plat, ctlr->base);
int ret;
/* We don't support writing partial bytes */
@@ -400,7 +431,7 @@ static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen,
ich_writeb(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status);
spi_setup_type(trans, using_cmd ? bytes : 0);
- opcode_index = spi_setup_opcode(ctlr, trans);
+ opcode_index = spi_setup_opcode(ctlr, trans, lock);
if (opcode_index < 0)
return -EINVAL;
with_address = spi_setup_offset(trans);
@@ -413,7 +444,7 @@ static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen,
* in order to prevent the Management Engine from
* issuing a transaction between WREN and DATA.
*/
- if (!ctlr->ichspi_lock)
+ if (!lock)
ich_writew(ctlr, trans->opcode, ctlr->preop);
return 0;
}
@@ -539,56 +570,6 @@ static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen,
return 0;
}
-/*
- * This uses the SPI controller from the Intel Cougar Point and Panther Point
- * PCH to write-protect portions of the SPI flash until reboot. The changes
- * don't actually take effect until the HSFS[FLOCKDN] bit is set, but that's
- * done elsewhere.
- */
-int spi_write_protect_region(struct udevice *dev, uint32_t lower_limit,
- uint32_t length, int hint)
-{
- struct udevice *bus = dev->parent;
- struct ich_spi_priv *ctlr = dev_get_priv(bus);
- uint32_t tmplong;
- uint32_t upper_limit;
-
- if (!ctlr->pr) {
- printf("%s: operation not supported on this chipset\n",
- __func__);
- return -ENOSYS;
- }
-
- if (length == 0 ||
- lower_limit > (0xFFFFFFFFUL - length) + 1 ||
- hint < 0 || hint > 4) {
- printf("%s(0x%x, 0x%x, %d): invalid args\n", __func__,
- lower_limit, length, hint);
- return -EPERM;
- }
-
- upper_limit = lower_limit + length - 1;
-
- /*
- * Determine bits to write, as follows:
- * 31 Write-protection enable (includes erase operation)
- * 30:29 reserved
- * 28:16 Upper Limit (FLA address bits 24:12, with 11:0 == 0xfff)
- * 15 Read-protection enable
- * 14:13 reserved
- * 12:0 Lower Limit (FLA address bits 24:12, with 11:0 == 0x000)
- */
- tmplong = 0x80000000 |
- ((upper_limit & 0x01fff000) << 4) |
- ((lower_limit & 0x01fff000) >> 12);
-
- printf("%s: writing 0x%08x to %p\n", __func__, tmplong,
- &ctlr->pr[hint]);
- ctlr->pr[hint] = tmplong;
-
- return 0;
-}
-
static int ich_spi_probe(struct udevice *dev)
{
struct ich_spi_platdata *plat = dev_get_platdata(dev);
@@ -619,16 +600,11 @@ static int ich_spi_probe(struct udevice *dev)
static int ich_spi_remove(struct udevice *bus)
{
- struct ich_spi_priv *ctlr = dev_get_priv(bus);
-
/*
* Configure SPI controller so that the Linux MTD driver can fully
* access the SPI NOR chip
*/
- ich_writew(ctlr, SPI_OPPREFIX, ctlr->preop);
- ich_writew(ctlr, SPI_OPTYPE, ctlr->optype);
- ich_writel(ctlr, SPI_OPMENU_LOWER, ctlr->opmenu);
- ich_writel(ctlr, SPI_OPMENU_UPPER, ctlr->opmenu + sizeof(u32));
+ ich_spi_config_opcode(bus);
return 0;
}
diff --git a/drivers/spi/ich.h b/drivers/spi/ich.h
index dcb8a9048f8..c867c57be9f 100644
--- a/drivers/spi/ich.h
+++ b/drivers/spi/ich.h
@@ -177,8 +177,6 @@ struct ich_spi_platdata {
};
struct ich_spi_priv {
- int ichspi_lock;
- int locked;
int opmenu;
int menubytes;
void *base; /* Base of register set */
diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index 13f122350b2..6305bbf01cd 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -44,6 +44,14 @@ config ALTERA_TIMER
Select this to enable a timer for Altera devices. Please find
details on the "Embedded Peripherals IP User Guide" of Altera.
+config ATMEL_PIT_TIMER
+ bool "Atmel periodic interval timer support"
+ depends on TIMER
+ help
+ Select this to enable a periodic interval timer for Atmel devices,
+ it is designed to offer maximum accuracy and efficient management,
+ even for systems with long response time.
+
config SANDBOX_TIMER
bool "Sandbox timer support"
depends on SANDBOX && TIMER
diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
index fa7ce7c8358..69e8961a7ba 100644
--- a/drivers/timer/Makefile
+++ b/drivers/timer/Makefile
@@ -15,3 +15,4 @@ obj-$(CONFIG_ARC_TIMER) += arc_timer.o
obj-$(CONFIG_AG101P_TIMER) += ag101p_timer.o
obj-$(CONFIG_AE3XX_TIMER) += ae3xx_timer.o
obj-$(CONFIG_ROCKCHIP_TIMER) += rockchip_timer.o
+obj-$(CONFIG_ATMEL_PIT_TIMER) += atmel_pit_timer.o
diff --git a/drivers/timer/atmel_pit_timer.c b/drivers/timer/atmel_pit_timer.c
new file mode 100644
index 00000000000..999717b91ff
--- /dev/null
+++ b/drivers/timer/atmel_pit_timer.c
@@ -0,0 +1,90 @@
+/*
+ * Copyright (C) 2017 Microchip Corporation
+ * Wenyou.Yang <wenyou.yang@microchip.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <timer.h>
+#include <asm/io.h>
+
+#define AT91_PIT_VALUE 0xfffff
+#define AT91_PIT_PITEN BIT(24) /* Timer Enabled */
+
+struct atmel_pit_regs {
+ u32 mode;
+ u32 status;
+ u32 value;
+ u32 value_image;
+};
+
+struct atmel_pit_platdata {
+ struct atmel_pit_regs *regs;
+};
+
+static int atmel_pit_get_count(struct udevice *dev, u64 *count)
+{
+ struct atmel_pit_platdata *plat = dev_get_platdata(dev);
+ struct atmel_pit_regs *const regs = plat->regs;
+ u32 val = readl(&regs->value_image);
+
+ *count = timer_conv_64(val);
+
+ return 0;
+}
+
+static int atmel_pit_probe(struct udevice *dev)
+{
+ struct atmel_pit_platdata *plat = dev_get_platdata(dev);
+ struct atmel_pit_regs *const regs = plat->regs;
+ struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct clk clk;
+ ulong clk_rate;
+ int ret;
+
+ ret = clk_get_by_index(dev, 0, &clk);
+ if (ret)
+ return -EINVAL;
+
+ clk_rate = clk_get_rate(&clk);
+ if (!clk_rate)
+ return -EINVAL;
+
+ uc_priv->clock_rate = clk_rate / 16;
+
+ writel(AT91_PIT_VALUE | AT91_PIT_PITEN, &regs->mode);
+
+ return 0;
+}
+
+static int atmel_pit_ofdata_to_platdata(struct udevice *dev)
+{
+ struct atmel_pit_platdata *plat = dev_get_platdata(dev);
+
+ plat->regs = (struct atmel_pit_regs *)devfdt_get_addr_ptr(dev);
+
+ return 0;
+}
+
+static const struct timer_ops atmel_pit_ops = {
+ .get_count = atmel_pit_get_count,
+};
+
+static const struct udevice_id atmel_pit_ids[] = {
+ { .compatible = "atmel,at91sam9260-pit" },
+ { }
+};
+
+U_BOOT_DRIVER(atmel_pit) = {
+ .name = "atmel_pit",
+ .id = UCLASS_TIMER,
+ .of_match = atmel_pit_ids,
+ .ofdata_to_platdata = atmel_pit_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct atmel_pit_platdata),
+ .probe = atmel_pit_probe,
+ .ops = &atmel_pit_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
generated by cgit v1.2.3 (git 2.0.4) at 2025-07-20 18:55:43 +0000