diff options
Diffstat (limited to 'dts/upstream/Bindings/timer/sifive,clint.yaml')
| -rw-r--r-- | dts/upstream/Bindings/timer/sifive,clint.yaml | 24 |
1 files changed, 23 insertions, 1 deletions
diff --git a/dts/upstream/Bindings/timer/sifive,clint.yaml b/dts/upstream/Bindings/timer/sifive,clint.yaml index 76d83aea4e2..653e2e0ca87 100644 --- a/dts/upstream/Bindings/timer/sifive,clint.yaml +++ b/dts/upstream/Bindings/timer/sifive,clint.yaml @@ -37,6 +37,12 @@ properties: - starfive,jh8100-clint # StarFive JH8100 - const: sifive,clint0 # SiFive CLINT v0 IP block - items: + - {} + - const: sifive,clint2 # SiFive CLINT v2 IP block + description: + SiFive CLINT v2 is the HRT that supports the Zicntr. The control of sifive,clint2 + differs from that of sifive,clint0, making them incompatible. + - items: - enum: - allwinner,sun20i-d1-clint - sophgo,cv1800b-clint @@ -62,6 +68,22 @@ properties: minItems: 1 maxItems: 4095 + sifive,fine-ctr-bits: + maximum: 15 + description: The width in bits of the fine counter. + +if: + properties: + compatible: + contains: + const: sifive,clint2 +then: + required: + - sifive,fine-ctr-bits +else: + properties: + sifive,fine-ctr-bits: false + additionalProperties: false required: @@ -77,6 +99,6 @@ examples: <&cpu2intc 3>, <&cpu2intc 7>, <&cpu3intc 3>, <&cpu3intc 7>, <&cpu4intc 3>, <&cpu4intc 7>; - reg = <0x2000000 0x10000>; + reg = <0x2000000 0x10000>; }; ... |