diff options
Diffstat (limited to 'dts/upstream/src/arm64/rockchip')
73 files changed, 4387 insertions, 154 deletions
diff --git a/dts/upstream/src/arm64/rockchip/px30-engicam-common.dtsi b/dts/upstream/src/arm64/rockchip/px30-engicam-common.dtsi index 1edfd643b25..a334ef0629d 100644 --- a/dts/upstream/src/arm64/rockchip/px30-engicam-common.dtsi +++ b/dts/upstream/src/arm64/rockchip/px30-engicam-common.dtsi @@ -31,7 +31,7 @@ }; vcc3v3_btreg: vcc3v3-btreg { - compatible = "regulator-gpio"; + compatible = "regulator-fixed"; enable-active-high; pinctrl-names = "default"; pinctrl-0 = <&bt_enable_h>; @@ -39,7 +39,6 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; - states = <3300000 0x0>; }; vcc3v3_rf_aux_mod: regulator-vcc3v3-rf-aux-mod { diff --git a/dts/upstream/src/arm64/rockchip/px30-engicam-ctouch2.dtsi b/dts/upstream/src/arm64/rockchip/px30-engicam-ctouch2.dtsi index 80db778c968..b60e68faa83 100644 --- a/dts/upstream/src/arm64/rockchip/px30-engicam-ctouch2.dtsi +++ b/dts/upstream/src/arm64/rockchip/px30-engicam-ctouch2.dtsi @@ -26,5 +26,5 @@ }; &vcc3v3_btreg { - enable-gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>; + gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>; }; diff --git a/dts/upstream/src/arm64/rockchip/px30-engicam-px30-core-edimm2.2.dts b/dts/upstream/src/arm64/rockchip/px30-engicam-px30-core-edimm2.2.dts index 165d09ccb94..5886b802c52 100644 --- a/dts/upstream/src/arm64/rockchip/px30-engicam-px30-core-edimm2.2.dts +++ b/dts/upstream/src/arm64/rockchip/px30-engicam-px30-core-edimm2.2.dts @@ -39,5 +39,5 @@ }; &vcc3v3_btreg { - enable-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; + gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; }; diff --git a/dts/upstream/src/arm64/rockchip/px30-ringneck-haikou-lvds-9904379.dtso b/dts/upstream/src/arm64/rockchip/px30-ringneck-haikou-lvds-9904379.dtso new file mode 100644 index 00000000000..3fc088a5636 --- /dev/null +++ b/dts/upstream/src/arm64/rockchip/px30-ringneck-haikou-lvds-9904379.dtso @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Cherry Embedded Solutions GmbH + * + * HAIKOU-LVDS-9904379 adapter for PX30 Ringneck and Haikou carrierboard. + * + * This adapter needs to be plugged in the fake PCIe connector called Video + * Connector on Haikou carrierboard. + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pinctrl/rockchip.h> + +&{/} { + backlight_lvds: backlight-lvds { + compatible = "pwm-backlight"; + brightness-levels = <0 255>; + default-brightness-level = <255>; + num-interpolated-steps = <255>; + power-supply = <&vcc3v3_baseboard>; + pwms = <&pwm0 0 25000 0>; + }; + + panel { + compatible = "admatec,9904379", "panel-lvds"; + backlight = <&backlight_lvds>; + data-mapping = "vesa-24"; + height-mm = <126>; + power-supply = <&vcc3v3_baseboard>; + width-mm = <224>; + + panel-timing { + clock-frequency = <49500000>; + hactive = <1024>; + hback-porch = <90>; + hfront-porch = <90>; + hsync-len = <90>; + vactive = <600>; + vback-porch = <10>; + vfront-porch = <10>; + vsync-len = <10>; + }; + + port { + panel_in_lvds: endpoint { + remote-endpoint = <&lvds_out_panel>; + }; + }; + }; +}; + +&display_subsystem { + status = "okay"; +}; + +&dsi_dphy { + status = "okay"; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + /* EEPROM and GT928 are limited to 400KHz */ + clock-frequency = <400000>; + + touchscreen@14 { + compatible = "goodix,gt928"; + reg = <0x14>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA0 IRQ_TYPE_LEVEL_LOW>; + irq-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&touch_int &touch_rst>; + pinctrl-names = "default"; + touchscreen-inverted-x; + touchscreen-inverted-y; + AVDD28-supply = <&vcc3v3_baseboard>; + VDDIO-supply = <&vcc3v3_baseboard>; + }; + + eeprom@54 { + reg = <0x54>; + compatible = "st,24c04", "atmel,24c04"; + pagesize = <16>; + size = <512>; + vcc-supply = <&vcc3v3_baseboard>; + }; +}; + +&lvds { + status = "okay"; +}; + +&lvds_out { + lvds_out_panel: endpoint { + remote-endpoint = <&panel_in_lvds>; + }; +}; + +&pinctrl { + touch { + touch_int: touch-int { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + touch_rst: touch-rst { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; diff --git a/dts/upstream/src/arm64/rockchip/px30-ringneck-haikou-video-demo.dtso b/dts/upstream/src/arm64/rockchip/px30-ringneck-haikou-video-demo.dtso new file mode 100644 index 00000000000..7d9ea5aa598 --- /dev/null +++ b/dts/upstream/src/arm64/rockchip/px30-ringneck-haikou-video-demo.dtso @@ -0,0 +1,190 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Cherry Embedded Solutions GmbH + * + * DEVKIT ADDON CAM-TS-A01 + * https://embedded.cherry.de/product/development-kit/ + * + * DT-overlay for the camera / DSI demo appliance for Haikou boards. + * In the flavour for use with a Ringneck system-on-module. + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/clock/px30-cru.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/rockchip.h> + +&{/} { + backlight: backlight { + compatible = "pwm-backlight"; + power-supply = <&dc_12v>; + pwms = <&pwm0 0 25000 0>; + }; + + cam_afvdd_2v8: regulator-cam-afvdd-2v8 { + compatible = "regulator-fixed"; + gpio = <&pca9670 2 GPIO_ACTIVE_LOW>; + regulator-max-microvolt = <2800000>; + regulator-min-microvolt = <2800000>; + regulator-name = "cam-afvdd-2v8"; + vin-supply = <&vcc2v8_video>; + }; + + cam_avdd_2v8: regulator-cam-avdd-2v8 { + compatible = "regulator-fixed"; + gpio = <&pca9670 4 GPIO_ACTIVE_LOW>; + regulator-max-microvolt = <2800000>; + regulator-min-microvolt = <2800000>; + regulator-name = "cam-avdd-2v8"; + vin-supply = <&vcc2v8_video>; + }; + + cam_dovdd_1v8: regulator-cam-dovdd-1v8 { + compatible = "regulator-fixed"; + gpio = <&pca9670 3 GPIO_ACTIVE_LOW>; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "cam-dovdd-1v8"; + vin-supply = <&vcc1v8_video>; + }; + + cam_dvdd_1v2: regulator-cam-dvdd-1v2 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&pca9670 5 GPIO_ACTIVE_HIGH>; + regulator-max-microvolt = <1200000>; + regulator-min-microvolt = <1200000>; + regulator-name = "cam-dvdd-1v2"; + vin-supply = <&vcc3v3_baseboard>; + }; + + vcc1v8_video: regulator-vcc1v8-video { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "vcc1v8-video"; + vin-supply = <&vcc3v3_baseboard>; + }; + + vcc2v8_video: regulator-vcc2v8-video { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <2800000>; + regulator-min-microvolt = <2800000>; + regulator-name = "vcc2v8-video"; + vin-supply = <&vcc3v3_baseboard>; + }; + + video-adapter-leds { + compatible = "gpio-leds"; + + video-adapter-led { + color = <LED_COLOR_ID_BLUE>; + gpios = <&pca9670 7 GPIO_ACTIVE_HIGH>; + label = "video-adapter-led"; + linux,default-trigger = "none"; + }; + }; +}; + +&display_subsystem { + status = "okay"; +}; + +&dsi { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + panel@0 { + compatible = "leadtek,ltk050h3148w"; + reg = <0>; + backlight = <&backlight>; + iovcc-supply = <&vcc1v8_video>; + reset-gpios = <&pca9670 0 GPIO_ACTIVE_LOW>; + vci-supply = <&vcc2v8_video>; + + port { + mipi_in_panel: endpoint { + remote-endpoint = <&mipi_out_panel>; + }; + }; + }; +}; + +&dsi_dphy { + status = "okay"; +}; + +&dsi_out { + mipi_out_panel: endpoint { + remote-endpoint = <&mipi_in_panel>; + }; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + /* OV5675, GT911, DW9714 are limited to 400KHz */ + clock-frequency = <400000>; + + touchscreen@14 { + compatible = "goodix,gt911"; + reg = <0x14>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA0 IRQ_TYPE_LEVEL_LOW>; + irq-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&touch_int>; + pinctrl-names = "default"; + reset-gpios = <&pca9670 1 GPIO_ACTIVE_HIGH>; + AVDD28-supply = <&vcc2v8_video>; + VDDIO-supply = <&vcc3v3_baseboard>; + }; + + pca9670: gpio@27 { + compatible = "nxp,pca9670"; + reg = <0x27>; + gpio-controller; + #gpio-cells = <2>; + pinctrl-0 = <&pca9670_resetn>; + pinctrl-names = "default"; + reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + pca9670 { + pca9670_resetn: pca9670-resetn { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + touch { + touch_int: touch-int { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; diff --git a/dts/upstream/src/arm64/rockchip/px30-ringneck-haikou.dts b/dts/upstream/src/arm64/rockchip/px30-ringneck-haikou.dts index 1a59e8b1dc4..91cf4cd3fae 100644 --- a/dts/upstream/src/arm64/rockchip/px30-ringneck-haikou.dts +++ b/dts/upstream/src/arm64/rockchip/px30-ringneck-haikou.dts @@ -154,6 +154,8 @@ }; &i2c3 { + status = "okay"; + eeprom@50 { reg = <0x50>; compatible = "atmel,24c01"; diff --git a/dts/upstream/src/arm64/rockchip/px30-ringneck.dtsi b/dts/upstream/src/arm64/rockchip/px30-ringneck.dtsi index e80412abec0..142244d5270 100644 --- a/dts/upstream/src/arm64/rockchip/px30-ringneck.dtsi +++ b/dts/upstream/src/arm64/rockchip/px30-ringneck.dtsi @@ -325,10 +325,6 @@ }; }; -&i2c3 { - status = "okay"; -}; - &i2s0_8ch { rockchip,trcm-sync-tx-only; diff --git a/dts/upstream/src/arm64/rockchip/rk3308-roc-cc.dts b/dts/upstream/src/arm64/rockchip/rk3308-roc-cc.dts index 629121de5a1..5e718194899 100644 --- a/dts/upstream/src/arm64/rockchip/rk3308-roc-cc.dts +++ b/dts/upstream/src/arm64/rockchip/rk3308-roc-cc.dts @@ -147,7 +147,7 @@ &pwm5 { status = "okay"; - pinctrl-names = "active"; + pinctrl-names = "default"; pinctrl-0 = <&pwm5_pin_pull_down>; }; diff --git a/dts/upstream/src/arm64/rockchip/rk3318-a95x-z2.dts b/dts/upstream/src/arm64/rockchip/rk3318-a95x-z2.dts index a94114fb7cc..96c27fc5005 100644 --- a/dts/upstream/src/arm64/rockchip/rk3318-a95x-z2.dts +++ b/dts/upstream/src/arm64/rockchip/rk3318-a95x-z2.dts @@ -274,13 +274,13 @@ &pwm0 { pinctrl-0 = <&pwm0_pin_pull_up>; - pinctrl-names = "active"; + pinctrl-names = "default"; status = "okay"; }; &pwm1 { pinctrl-0 = <&pwm1_pin_pull_up>; - pinctrl-names = "active"; + pinctrl-names = "default"; status = "okay"; }; diff --git a/dts/upstream/src/arm64/rockchip/rk3328-rock-pi-e.dts b/dts/upstream/src/arm64/rockchip/rk3328-rock-pi-e.dts index 6310b58de77..a4bdd87d072 100644 --- a/dts/upstream/src/arm64/rockchip/rk3328-rock-pi-e.dts +++ b/dts/upstream/src/arm64/rockchip/rk3328-rock-pi-e.dts @@ -428,10 +428,18 @@ status = "okay"; }; +&u2phy_otg { + status = "okay"; +}; + &uart2 { status = "okay"; }; +&usb20_otg { + status = "okay"; +}; + &usbdrd3 { dr_mode = "host"; status = "okay"; diff --git a/dts/upstream/src/arm64/rockchip/rk3399-nanopi4.dtsi b/dts/upstream/src/arm64/rockchip/rk3399-nanopi4.dtsi index b169be06d4d..c8eb5481f43 100644 --- a/dts/upstream/src/arm64/rockchip/rk3399-nanopi4.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3399-nanopi4.dtsi @@ -603,7 +603,7 @@ }; &pwm2 { - pinctrl-names = "active"; + pinctrl-names = "default"; pinctrl-0 = <&pwm2_pin_pull_down>; status = "okay"; }; diff --git a/dts/upstream/src/arm64/rockchip/rk3399-puma-haikou-video-demo.dtso b/dts/upstream/src/arm64/rockchip/rk3399-puma-haikou-video-demo.dtso new file mode 100644 index 00000000000..0377ec860d3 --- /dev/null +++ b/dts/upstream/src/arm64/rockchip/rk3399-puma-haikou-video-demo.dtso @@ -0,0 +1,166 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Cherry Embedded Solutions GmbH + * + * DEVKIT ADDON CAM-TS-A01 + * https://embedded.cherry.de/product/development-kit/ + * + * DT-overlay for the camera / DSI demo appliance for Haikou boards. + * In the flavour for use with a Puma system-on-module. + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/clock/rk3399-cru.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/rockchip.h> + +&{/} { + backlight: backlight { + compatible = "pwm-backlight"; + power-supply = <&dc_12v>; + pwms = <&pwm0 0 25000 0>; + }; + + cam_afvdd_2v8: regulator-cam-afvdd-2v8 { + compatible = "regulator-fixed"; + gpio = <&pca9670 2 GPIO_ACTIVE_LOW>; + regulator-max-microvolt = <2800000>; + regulator-min-microvolt = <2800000>; + regulator-name = "cam-afvdd-2v8"; + vin-supply = <&vcc2v8_video>; + }; + + cam_avdd_2v8: regulator-cam-avdd-2v8 { + compatible = "regulator-fixed"; + gpio = <&pca9670 4 GPIO_ACTIVE_LOW>; + regulator-max-microvolt = <2800000>; + regulator-min-microvolt = <2800000>; + regulator-name = "cam-avdd-2v8"; + vin-supply = <&vcc2v8_video>; + }; + + cam_dovdd_1v8: regulator-cam-dovdd-1v8 { + compatible = "regulator-fixed"; + gpio = <&pca9670 3 GPIO_ACTIVE_LOW>; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "cam-dovdd-1v8"; + vin-supply = <&vcc1v8_video>; + }; + + cam_dvdd_1v2: regulator-cam-dvdd-1v2 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&pca9670 5 GPIO_ACTIVE_HIGH>; + regulator-max-microvolt = <1200000>; + regulator-min-microvolt = <1200000>; + regulator-name = "cam-dvdd-1v2"; + vin-supply = <&vcc3v3_baseboard>; + }; + + vcc1v8_video: regulator-vcc1v8-video { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "vcc1v8-video"; + vin-supply = <&vcc3v3_baseboard>; + }; + + vcc2v8_video: regulator-vcc2v8-video { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <2800000>; + regulator-min-microvolt = <2800000>; + regulator-name = "vcc2v8-video"; + vin-supply = <&vcc3v3_baseboard>; + }; + + video-adapter-leds { + compatible = "gpio-leds"; + + video-adapter-led { + color = <LED_COLOR_ID_BLUE>; + gpios = <&pca9670 7 GPIO_ACTIVE_HIGH>; + label = "video-adapter-led"; + linux,default-trigger = "none"; + }; + }; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + /* OV5675, GT911, DW9714 are limited to 400KHz */ + clock-frequency = <400000>; + + touchscreen@14 { + compatible = "goodix,gt911"; + reg = <0x14>; + interrupt-parent = <&gpio1>; + interrupts = <RK_PC7 IRQ_TYPE_LEVEL_LOW>; + irq-gpios = <&gpio1 RK_PC7 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&touch_int>; + pinctrl-names = "default"; + reset-gpios = <&pca9670 1 GPIO_ACTIVE_HIGH>; + AVDD28-supply = <&vcc2v8_video>; + VDDIO-supply = <&vcc3v3_baseboard>; + }; + + pca9670: gpio@27 { + compatible = "nxp,pca9670"; + reg = <0x27>; + gpio-controller; + #gpio-cells = <2>; + pinctrl-0 = <&pca9670_resetn>; + pinctrl-names = "default"; + reset-gpios = <&gpio4 RK_PD6 GPIO_ACTIVE_LOW>; + }; +}; + +&mipi_out { + mipi_out_panel: endpoint { + remote-endpoint = <&mipi_in_panel>; + }; +}; + +&mipi_dsi { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + panel@0 { + compatible = "leadtek,ltk050h3148w"; + reg = <0>; + backlight = <&backlight>; + iovcc-supply = <&vcc1v8_video>; + reset-gpios = <&pca9670 0 GPIO_ACTIVE_LOW>; + vci-supply = <&vcc2v8_video>; + + port { + mipi_in_panel: endpoint { + remote-endpoint = <&mipi_out_panel>; + }; + }; + }; +}; + +&pinctrl { + pca9670 { + pca9670_resetn: pca9670-resetn { + rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + touch { + touch_int: touch-int { + rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/dts/upstream/src/arm64/rockchip/rk3399-puma-haikou.dts b/dts/upstream/src/arm64/rockchip/rk3399-puma-haikou.dts index 947bbd62a6b..f2234dabd66 100644 --- a/dts/upstream/src/arm64/rockchip/rk3399-puma-haikou.dts +++ b/dts/upstream/src/arm64/rockchip/rk3399-puma-haikou.dts @@ -149,8 +149,15 @@ }; }; +&gmac { + status = "okay"; +}; + &hdmi { - ddc-i2c-bus = <&i2c3>; + status = "okay"; +}; + +&hdmi_sound { status = "okay"; }; @@ -186,9 +193,22 @@ }; }; -&i2c6 { +&i2c7 { + eeprom@50 { + reg = <0x50>; + compatible = "atmel,24c01"; + pagesize = <8>; + size = <128>; + vcc-supply = <&vcc3v3_baseboard>; + }; +}; + +&i2s0 { + status = "okay"; +}; + +&i2s2 { status = "okay"; - clock-frequency = <400000>; }; &pcie_phy { diff --git a/dts/upstream/src/arm64/rockchip/rk3399-puma.dtsi b/dts/upstream/src/arm64/rockchip/rk3399-puma.dtsi index 995b30a7aae..e00fbaa8acc 100644 --- a/dts/upstream/src/arm64/rockchip/rk3399-puma.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3399-puma.dtsi @@ -183,7 +183,6 @@ snps,reset-delays-us = <0 10000 50000>; tx_delay = <0x10>; rx_delay = <0x23>; - status = "okay"; }; &gpu { @@ -389,6 +388,14 @@ }; }; +&hdmi { + ddc-i2c-bus = <&i2c3>; +}; + +&i2c6 { + clock-frequency = <400000>; +}; + &i2c7 { status = "okay"; clock-frequency = <400000>; @@ -439,7 +446,6 @@ pinctrl-1 = <&i2s0_2ch_bus_bclk_off>; rockchip,playback-channels = <2>; rockchip,capture-channels = <2>; - status = "okay"; }; /* diff --git a/dts/upstream/src/arm64/rockchip/rk3399-roc-pc-plus.dts b/dts/upstream/src/arm64/rockchip/rk3399-roc-pc-plus.dts index e2e9279fa26..8e3858cf988 100644 --- a/dts/upstream/src/arm64/rockchip/rk3399-roc-pc-plus.dts +++ b/dts/upstream/src/arm64/rockchip/rk3399-roc-pc-plus.dts @@ -112,7 +112,7 @@ &i2c1 { es8388: es8388@11 { - compatible = "everest,es8388"; + compatible = "everest,es8388", "everest,es8328"; reg = <0x11>; clocks = <&cru SCLK_I2S_8CH_OUT>; #sound-dai-cells = <0>; diff --git a/dts/upstream/src/arm64/rockchip/rk3399-rock-pi-4.dtsi b/dts/upstream/src/arm64/rockchip/rk3399-rock-pi-4.dtsi index 541dca12bf1..046dbe32901 100644 --- a/dts/upstream/src/arm64/rockchip/rk3399-rock-pi-4.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3399-rock-pi-4.dtsi @@ -43,7 +43,7 @@ sdio_pwrseq: sdio-pwrseq { compatible = "mmc-pwrseq-simple"; clocks = <&rk808 1>; - clock-names = "lpo"; + clock-names = "ext_clock"; pinctrl-names = "default"; pinctrl-0 = <&wifi_enable_h>; reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; diff --git a/dts/upstream/src/arm64/rockchip/rk3566-bigtreetech-cb2.dtsi b/dts/upstream/src/arm64/rockchip/rk3566-bigtreetech-cb2.dtsi index a4835147176..e7ba477e75f 100644 --- a/dts/upstream/src/arm64/rockchip/rk3566-bigtreetech-cb2.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3566-bigtreetech-cb2.dtsi @@ -775,7 +775,7 @@ rockchip,default-sample-phase = <90>; status = "okay"; - sdio-wifi@1 { + wifi@1 { compatible = "brcm,bcm4329-fmac"; reg = <1>; interrupt-parent = <&gpio2>; diff --git a/dts/upstream/src/arm64/rockchip/rk3566-pinenote.dtsi b/dts/upstream/src/arm64/rockchip/rk3566-pinenote.dtsi index 2d3ae154482..3613661417b 100644 --- a/dts/upstream/src/arm64/rockchip/rk3566-pinenote.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3566-pinenote.dtsi @@ -9,6 +9,8 @@ #include "rk3566.dtsi" / { + chassis-type = "tablet"; + aliases { mmc0 = &sdhci; }; diff --git a/dts/upstream/src/arm64/rockchip/rk3566-quartz64-a.dts b/dts/upstream/src/arm64/rockchip/rk3566-quartz64-a.dts index 98e75df8b15..3c127c5c260 100644 --- a/dts/upstream/src/arm64/rockchip/rk3566-quartz64-a.dts +++ b/dts/upstream/src/arm64/rockchip/rk3566-quartz64-a.dts @@ -265,8 +265,12 @@ }; &gmac1 { - assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>; - assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>; + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, + <&cru SCLK_GMAC1_RGMII_SPEED>, + <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, + <&cru SCLK_GMAC1>, + <&gmac1_clkin>; clock_in_out = "input"; phy-supply = <&vcc_3v3>; phy-mode = "rgmii"; diff --git a/dts/upstream/src/arm64/rockchip/rk3566-quartz64-b.dts b/dts/upstream/src/arm64/rockchip/rk3566-quartz64-b.dts index 24928a12944..5707321a114 100644 --- a/dts/upstream/src/arm64/rockchip/rk3566-quartz64-b.dts +++ b/dts/upstream/src/arm64/rockchip/rk3566-quartz64-b.dts @@ -173,8 +173,12 @@ }; &gmac1 { - assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>; - assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>; + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, + <&cru SCLK_GMAC1_RGMII_SPEED>, + <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, + <&cru SCLK_GMAC1>, + <&gmac1_clkin>; clock_in_out = "input"; phy-mode = "rgmii"; phy-supply = <&vcc_3v3>; diff --git a/dts/upstream/src/arm64/rockchip/rk3568-photonicat.dts b/dts/upstream/src/arm64/rockchip/rk3568-photonicat.dts new file mode 100644 index 00000000000..58c1052ba8e --- /dev/null +++ b/dts/upstream/src/arm64/rockchip/rk3568-photonicat.dts @@ -0,0 +1,588 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/soc/rockchip,vop2.h> +#include "rk3568.dtsi" + +/ { + model = "Ariaboard Photonicat"; + compatible = "ariaboard,photonicat", "rockchip,rk3568"; + + aliases { + ethernet0 = &gmac0; + ethernet1 = &gmac1; + mmc0 = &sdhci; + mmc1 = &sdmmc0; + mmc2 = &sdmmc1; + }; + + battery: battery { + compatible = "simple-battery"; + device-chemistry = "lithium-ion"; + charge-full-design-microamp-hours = <6800000>; + energy-full-design-microwatt-hours = <25000000>; + voltage-max-design-microvolt = <4200000>; + voltage-min-design-microvolt = <3400000>; + + ocv-capacity-celsius = <25>; + ocv-capacity-table-0 = <4100000 100>, <4040000 90>, + <3980000 80>, <3920000 70>, + <3870000 60>, <3820000 50>, + <3790000 40>, <3770000 30>, + <3740000 20>, <3680000 10>, + <3450000 0>; + }; + + chosen: chosen { + stdout-path = "serial2:1500000n8"; + }; + + hdmi_con: hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + vcc_1v8: regulator-vcc-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc_3v3: regulator-vcc-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + }; + + /* actually fed by vcc_syson, dependent + * on pi6c clock generator + */ + vcc3v3_pcie: regulator-vcc3v3-pcie { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_pi6c>; + }; + + /* pi6c pcie clock generator */ + vcc3v3_pi6c: regulator-vcc3v3-pi6c { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pwren_h>; + regulator-name = "vcc3v3_pi6c"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_syson>; + }; + + vcc3v3_sd: regulator-vcc3v3-sd { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_pwren>; + regulator-boot-on; + regulator-name = "vcc3v3_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3>; + }; + + vcc3v3_sys: regulator-vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_syson>; + }; + + vcc3v4_rf: regulator-vcc3v4-rf { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&rf_pwr_en>; + regulator-name = "vcc3v4_rf"; + regulator-min-microvolt = <3400000>; + regulator-max-microvolt = <3400000>; + vin-supply = <&vccin_5v>; + }; + + vcc5v0_usb30_otg0: regulator-vcc5v0-usb30-otg0 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_host_pwren_h>; + regulator-name = "vcc5v0_usb30_otg0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vccin_5v>; + }; + + vccin_5v: regulator-vccin-5v { + compatible = "regulator-fixed"; + regulator-name = "vccin_5v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc_sysin: regulator-vcc-sysin { + compatible = "regulator-fixed"; + regulator-name = "vcc_sysin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vccin_5v>; + }; + + vcc_syson: regulator-vcc-syson { + compatible = "regulator-fixed"; + regulator-name = "vcc_syson"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_sysin>; + }; + + vcca_1v8: regulator-vcca-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_sys>; + }; + + vdda_0v9: regulator-vdda-0v9 { + compatible = "regulator-fixed"; + regulator-name = "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc3v3_sys>; + }; + + vdd_gpu: regulator-vdd-gpu { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 5000 1>; + pwm-supply = <&vcc_syson>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-settling-time-up-us = <250>; + }; + + vdd_logic: regulator-vdd-logic { + compatible = "pwm-regulator"; + pwms = <&pwm1 0 5000 1>; + pwm-supply = <&vcc_syson>; + regulator-name = "vdd_logic"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-settling-time-up-us = <250>; + }; + + rfkill-modem { + compatible = "rfkill-gpio"; + label = "M.2 USB Modem"; + radio-type = "wwan"; + shutdown-gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&pmucru CLK_RTC_32K>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_reg_on_h &clk32k_out1>; + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; + }; +}; + +&combphy0 { + status = "okay"; +}; + +&combphy1 { + status = "okay"; +}; + +&combphy2 { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +/* Motorcomm YT8521SC LAN port (require SGMII) */ +&gmac0 { + status = "disabled"; +}; + +/* Motorcomm YT8521SC WAN port */ +&gmac1 { + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>; + assigned-clock-rates = <0>, <125000000>; + clock_in_out = "output"; + phy-handle = <&rgmii_phy>; + phy-mode = "rgmii-id"; + phy-supply = <&vcc_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_rgmii_bus>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + avdd-0v9-supply = <&vdda_0v9>; + avdd-1v8-supply = <&vcca_1v8>; + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: regulator@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc_syson>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m1_xfer>; + status = "okay"; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&mdio1 { + rgmii_phy: ethernet-phy@3 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x3>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio4 RK_PC0 GPIO_ACTIVE_LOW>; + rx-internal-delay-ps = <1500>; + tx-internal-delay-ps = <1500>; + }; +}; + +&pcie30phy { + status = "okay"; +}; + +/* M.2 E-Key for PCIe WLAN */ +&pcie3x2 { + max-link-speed = <1>; + num-lanes = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie30x1m0_pins>; + reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pinctrl { + bt { + bt_reg_on_h: bt-reg-on-h { + rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + pcie_pwren_h: pcie-pwren-h { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdmmc0 { + sdmmc0_pwren: sdmmc0-pwren { + rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + rf_pwr_en: rf-pwr-en { + rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb_host_pwren_h: usb-host-pwren-h { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifi { + wifi_reg_on_h: wifi-reg-on-h { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc_3v3>; + pmuio2-supply = <&vcc_3v3>; + vccio1-supply = <&vcc_3v3>; + vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vcc_3v3>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_3v3>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca_1v8>; + status = "okay"; +}; + +/* eMMC */ +&sdhci { + bus-width = <8>; + max-frequency = <200000000>; + mmc-hs200-1_8v; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +/* Micro SD card slot */ +&sdmmc0 { + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_LOW>; + disable-wp; + no-1-8-v; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd>; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vcc_3v3>; + status = "okay"; +}; + +/* Qualcomm Atheros QCA9377 WiFi */ +&sdmmc1 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&wifi_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sys>; + vqmmc-supply = <&vcc_1v8>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wifi: wifi@1 { + reg = <1>; + interrupt-parent = <&gpio2>; + interrupts = <RK_PB2 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + }; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +/* Qualcomm Atheros QCA9377 Bluetooth */ +&uart1 { + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "qcom,qca9377-bt"; + clocks = <&pmucru CLK_RTC_32K>; + enable-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_reg_on_h>; + vddio-supply = <&vcc_1v8>; + }; +}; + +/* Debug UART */ +&uart2 { + status = "okay"; +}; + +&uart3 { + dma-names = "tx", "rx"; + status = "okay"; +}; + +/* Onboard power management MCU */ +&uart4 { + dma-names = "tx", "rx"; + status = "okay"; +}; + +/* M.2 E-Key for USB Bluetooth */ +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +/* USB Type-A Port */ +&usb_host0_xhci { + dr_mode = "host"; + status = "okay"; +}; + +/* M.2 B-Key for USB Modem WWAN */ +&usb_host1_xhci { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_host { + phy-supply = <&vcc3v4_rf>; + status = "okay"; +}; + +&usb2phy0_otg { + phy-supply = <&vcc5v0_usb30_otg0>; + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb2phy1_otg { + phy-supply = <&vcc5v0_usb30_otg0>; + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = <ROCKCHIP_VOP2_EP_HDMI0>; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; + +&xin32k { + pinctrl-names = "default"; + pinctrl-0 = <&clk32k_out1>; +}; diff --git a/dts/upstream/src/arm64/rockchip/rk3568-qnap-ts433.dts b/dts/upstream/src/arm64/rockchip/rk3568-qnap-ts433.dts index 7bd32d230ad..b80d628c426 100644 --- a/dts/upstream/src/arm64/rockchip/rk3568-qnap-ts433.dts +++ b/dts/upstream/src/arm64/rockchip/rk3568-qnap-ts433.dts @@ -619,6 +619,8 @@ bus-width = <8>; max-frequency = <200000000>; non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; status = "okay"; }; diff --git a/dts/upstream/src/arm64/rockchip/rk3568-rock-3a.dts b/dts/upstream/src/arm64/rockchip/rk3568-rock-3a.dts index ac79140a9ec..44cfdfeed66 100644 --- a/dts/upstream/src/arm64/rockchip/rk3568-rock-3a.dts +++ b/dts/upstream/src/arm64/rockchip/rk3568-rock-3a.dts @@ -778,20 +778,6 @@ pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; uart-has-rtscts; status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - clocks = <&rk809 1>; - clock-names = "lpo"; - device-wakeup-gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&bt_host_wake &bt_wake &bt_enable>; - vbat-supply = <&vcc3v3_sys>; - vddio-supply = <&vcc_1v8>; - /* vddio comes from regulator on module, use IO bank voltage instead */ - }; }; &uart2 { diff --git a/dts/upstream/src/arm64/rockchip/rk356x-base.dtsi b/dts/upstream/src/arm64/rockchip/rk356x-base.dtsi index e5539062911..fd2214b6fad 100644 --- a/dts/upstream/src/arm64/rockchip/rk356x-base.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk356x-base.dtsi @@ -174,6 +174,18 @@ method = "smc"; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + scmi_shmem: shmem@10f000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x0010f000 0x0 0x100>; + no-map; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, @@ -199,19 +211,6 @@ #clock-cells = <0>; }; - sram@10f000 { - compatible = "mmio-sram"; - reg = <0x0 0x0010f000 0x0 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x0 0x0010f000 0x100>; - - scmi_shmem: sram@0 { - compatible = "arm,scmi-shmem"; - reg = <0x0 0x100>; - }; - }; - sata1: sata@fc400000 { compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci"; reg = <0 0xfc400000 0 0x1000>; @@ -284,6 +283,18 @@ mbi-alias = <0x0 0xfd410000>; mbi-ranges = <296 24>; msi-controller; + ranges; + #address-cells = <2>; + #size-cells = <2>; + dma-noncoherent; + + its: msi-controller@fd440000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0xfd440000 0 0x20000>; + dma-noncoherent; + msi-controller; + #msi-cells = <1>; + }; }; usb_host0_ehci: usb@fd800000 { @@ -957,7 +968,7 @@ num-ib-windows = <6>; num-ob-windows = <2>; max-link-speed = <2>; - msi-map = <0x0 &gic 0x0 0x1000>; + msi-map = <0x0 &its 0x0 0x1000>; num-lanes = <1>; phys = <&combphy2 PHY_TYPE_PCIE>; phy-names = "pcie-phy"; @@ -1032,6 +1043,11 @@ status = "disabled"; }; + /* + * Testing showed that the HWRNG found in RK3566 produces unacceptably + * low quality of random data, so the HWRNG isn't enabled for all RK356x + * SoC variants despite its presence. + */ rng: rng@fe388000 { compatible = "rockchip,rk3568-rng"; reg = <0x0 0xfe388000 0x0 0x4000>; diff --git a/dts/upstream/src/arm64/rockchip/rk3576-armsom-sige5.dts b/dts/upstream/src/arm64/rockchip/rk3576-armsom-sige5.dts index 7c7331936a7..314067ba6f3 100644 --- a/dts/upstream/src/arm64/rockchip/rk3576-armsom-sige5.dts +++ b/dts/upstream/src/arm64/rockchip/rk3576-armsom-sige5.dts @@ -10,6 +10,7 @@ #include <dt-bindings/leds/common.h> #include <dt-bindings/pinctrl/rockchip.h> #include <dt-bindings/pwm/pwm.h> +#include <dt-bindings/soc/rockchip,vop2.h> #include <dt-bindings/usb/pd.h> #include "rk3576.dtsi" @@ -26,6 +27,17 @@ stdout-path = "serial0:1500000n8"; }; + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds: leds { compatible = "gpio-leds"; @@ -182,8 +194,7 @@ ð0m0_tx_bus2 ð0m0_rx_bus2 ð0m0_rgmii_clk - ð0m0_rgmii_bus - ðm0_clk0_25m_out>; + ð0m0_rgmii_bus>; phy-handle = <&rgmii_phy0>; status = "okay"; @@ -214,6 +225,26 @@ status = "okay"; }; +&hdmi { + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdptxphy { + status = "okay"; +}; + &i2c1 { status = "okay"; @@ -579,7 +610,7 @@ reg = <0x51>; clock-output-names = "hym8563"; interrupt-parent = <&gpio0>; - interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>; + interrupts = <RK_PA0 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "default"; pinctrl-0 = <&hym8563_int>; wakeup-source; @@ -656,3 +687,18 @@ pinctrl-0 = <&uart0m0_xfer>; status = "okay"; }; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = <ROCKCHIP_VOP2_EP_HDMI0>; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; diff --git a/dts/upstream/src/arm64/rockchip/rk3576-evb1-v10.dts b/dts/upstream/src/arm64/rockchip/rk3576-evb1-v10.dts index 782ca000a64..e368691fd28 100644 --- a/dts/upstream/src/arm64/rockchip/rk3576-evb1-v10.dts +++ b/dts/upstream/src/arm64/rockchip/rk3576-evb1-v10.dts @@ -10,6 +10,7 @@ #include <dt-bindings/input/input.h> #include <dt-bindings/leds/common.h> #include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/soc/rockchip,vop2.h> #include "rk3576.dtsi" / { @@ -57,6 +58,17 @@ }; }; + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds: leds { compatible = "gpio-leds"; @@ -270,6 +282,26 @@ status = "okay"; }; +&hdmi { + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdptxphy { + status = "okay"; +}; + &i2c1 { status = "okay"; @@ -729,3 +761,18 @@ dr_mode = "host"; status = "okay"; }; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = <ROCKCHIP_VOP2_EP_HDMI0>; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; diff --git a/dts/upstream/src/arm64/rockchip/rk3576-rock-4d.dts b/dts/upstream/src/arm64/rockchip/rk3576-rock-4d.dts new file mode 100644 index 00000000000..6756403111e --- /dev/null +++ b/dts/upstream/src/arm64/rockchip/rk3576-rock-4d.dts @@ -0,0 +1,751 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Radxa Computer (Shenzhen) Co., Ltd. + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/pwm/pwm.h> +#include <dt-bindings/soc/rockchip,vop2.h> +#include <dt-bindings/usb/pd.h> +#include "rk3576.dtsi" + +/ { + model = "Radxa ROCK 4D"; + compatible = "radxa,rock-4d", "rockchip,rk3576"; + + aliases { + ethernet0 = &gmac0; + mmc0 = &sdmmc; + }; + + chosen { + stdout-path = "serial0:1500000n8"; + }; + + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds: leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_rgb_g &led_rgb_r>; + + power-led { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_STATUS; + gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + user-led { + color = <LED_COLOR_ID_BLUE>; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + }; + + vcc_12v0_dcin: regulator-vcc-12v0-dcin { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-name = "vcc_12v0_dcin"; + }; + + vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vcc_1v1_nldo_s3"; + vin-supply = <&vcc_5v0_sys>; + }; + + vcc_1v2_ufs_vccq_s0: regulator-vcc-1v2-ufs-vccq-s0 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vcc_1v2_ufs_vccq_s0"; + vin-supply = <&vcc_5v0_sys>; + }; + + vcc_1v8_s0: regulator-vcc-1v8-s0 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s0"; + vin-supply = <&vcc_1v8_s3>; + }; + + vcc_1v8_ufs_vccq2_s0: regulator-vcc-1v8-ufs-vccq2-s0 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_ufs_vccq2_s0"; + vin-supply = <&vcc_1v8_s3>; + }; + + vcc_2v0_pldo_s3: regulator-vcc-2v0-pldo-s3 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-name = "vcc_2v0_pldo_s3"; + vin-supply = <&vcc_5v0_sys>; + }; + + vcc_3v3_pcie: regulator-vcc-3v3-pcie { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pwren>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_pcie"; + startup-delay-us = <5000>; + vin-supply = <&vcc_5v0_sys>; + }; + + vcc_3v3_rtc_s5: regulator-vcc-3v3-rtc-s5 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_rtc_s5"; + vin-supply = <&vcc_5v0_sys>; + }; + + vcc_3v3_s0: regulator-vcc-3v3-s0 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s0"; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc_3v3_ufs_s0: regulator-vcc-ufs-s0 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_ufs_s0"; + vin-supply = <&vcc_5v0_sys>; + }; + + vcc_5v0_device: regulator-vcc-5v0-device { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "vcc_5v0_device"; + vin-supply = <&vcc_12v0_dcin>; + }; + + vcc_5v0_host: regulator-vcc-5v0-host { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_host_pwren>; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "vcc5v0_host"; + vin-supply = <&vcc_5v0_device>; + }; + + vcc_5v0_sys: regulator-vcc-5v0-sys { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "vcc_5v0_sys"; + vin-supply = <&vcc_12v0_dcin>; + }; +}; + +&combphy1_psu { + status = "okay"; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&gmac0 { + clock_in_out = "output"; + phy-handle = <&rgmii_phy0>; + phy-mode = "rgmii-id"; + pinctrl-names = "default"; + pinctrl-0 = <ð0m0_miim + ð0m0_tx_bus2 + ð0m0_rx_bus2 + ð0m0_rgmii_clk + ð0m0_rgmii_bus + ðm0_clk0_25m_out>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdptxphy { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + pmic@23 { + compatible = "rockchip,rk806"; + reg = <0x23>; + #gpio-cells = <2>; + gpio-controller; + interrupt-parent = <&gpio0>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins + &rk806_dvs1_null + &rk806_dvs2_null + &rk806_dvs3_null>; + system-power-controller; + vcc1-supply = <&vcc_5v0_sys>; + vcc2-supply = <&vcc_5v0_sys>; + vcc3-supply = <&vcc_5v0_sys>; + vcc4-supply = <&vcc_5v0_sys>; + vcc5-supply = <&vcc_5v0_sys>; + vcc6-supply = <&vcc_5v0_sys>; + vcc7-supply = <&vcc_5v0_sys>; + vcc8-supply = <&vcc_5v0_sys>; + vcc9-supply = <&vcc_5v0_sys>; + vcc10-supply = <&vcc_5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc_5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc_5v0_sys>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun0"; + }; + + rk806_dvs1_pwrdn: dvs1-pwrdn-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun2"; + }; + + rk806_dvs1_rst: dvs1-rst-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun3"; + }; + + rk806_dvs1_slp: dvs1-slp-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun1"; + }; + + rk806_dvs2_dvs: dvs2-dvs-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun4"; + }; + + rk806_dvs2_gpio: dvs2-gpio-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun5"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs2_pwrdn: dvs2-pwrdn-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun2"; + }; + + rk806_dvs2_rst: dvs2-rst-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun3"; + }; + + rk806_dvs2_slp: dvs2-slp-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun1"; + }; + + rk806_dvs3_dvs: dvs3-dvs-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun4"; + }; + + rk806_dvs3_gpio: dvs3-gpio-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun5"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + rk806_dvs3_pwrdn: dvs3-pwrdn-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun2"; + }; + + rk806_dvs3_rst: dvs3-rst-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun3"; + }; + + rk806_dvs3_slp: dvs3-slp-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun1"; + }; + + regulators { + vdd_cpu_big_s0: dcdc-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-enable-ramp-delay = <400>; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-name = "vdd_cpu_big_s0"; + regulator-ramp-delay = <12500>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_npu_s0: dcdc-reg2 { + regulator-boot-on; + regulator-enable-ramp-delay = <400>; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-name = "vdd_npu_s0"; + regulator-ramp-delay = <12500>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-name = "vdd_cpu_lit_s0"; + regulator-ramp-delay = <12500>; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vcc_3v3_s3: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vdd_gpu_s0: dcdc-reg5 { + regulator-boot-on; + regulator-enable-ramp-delay = <400>; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdd_gpu_s0"; + regulator-ramp-delay = <12500>; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vddq_ddr_s0: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_logic_s0: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <800000>; + regulator-name = "vdd_logic_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vdd_ddr_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca_1v8_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pldo2_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pldo2_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_1v2_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vdda_1v2_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcca_3v3_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pldo6_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdda_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdda_ddr_pll_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v75_hdmi_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <837500>; + regulator-max-microvolt = <837500>; + regulator-name = "vdda0v75_hdmi_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v85_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdda_0v85_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v75_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdda_0v75_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&i2c2 { + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "hym8563"; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA0 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + wakeup-source; + }; +}; + +&mdio0 { + rgmii_phy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + clocks = <&cru REFCLKO25M_GMAC0_OUT>; + pinctrl-names = "default"; + pinctrl-0 = <&rtl8211f_rst>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + leds { + led_rgb_g: led-green-en { + rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + led_rgb_r: led-red-en { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + rtl8211f { + rtl8211f_rst: rtl8211f-rst { + rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + pcie_pwren: pcie-pwren { + rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + usb_host_pwren: usb-host-pwren { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + max-frequency = <200000000>; + no-sdio; + no-mmc; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + + +&sfc0 { + pinctrl-names = "default"; + pinctrl-0 = <&fspi0_pins &fspi0_csn0>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + vcc-supply = <&vcc_1v8_s3>; + }; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&uart0 { + pinctrl-0 = <&uart0m0_xfer>; + status = "okay"; +}; + +&usb_drd1_dwc3 { + dr_mode = "host"; + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = <ROCKCHIP_VOP2_EP_HDMI0>; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; diff --git a/dts/upstream/src/arm64/rockchip/rk3576.dtsi b/dts/upstream/src/arm64/rockchip/rk3576.dtsi index 29b47799849..ebb5fc8bb8b 100644 --- a/dts/upstream/src/arm64/rockchip/rk3576.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3576.dtsi @@ -111,7 +111,7 @@ reg = <0x0>; enable-method = "psci"; capacity-dmips-mhz = <485>; - clocks = <&scmi_clk ARMCLK_L>; + clocks = <&scmi_clk SCMI_ARMCLK_L>; operating-points-v2 = <&cluster0_opp_table>; #cooling-cells = <2>; dynamic-power-coefficient = <120>; @@ -124,7 +124,7 @@ reg = <0x1>; enable-method = "psci"; capacity-dmips-mhz = <485>; - clocks = <&scmi_clk ARMCLK_L>; + clocks = <&scmi_clk SCMI_ARMCLK_L>; operating-points-v2 = <&cluster0_opp_table>; cpu-idle-states = <&CPU_SLEEP>; }; @@ -135,7 +135,7 @@ reg = <0x2>; enable-method = "psci"; capacity-dmips-mhz = <485>; - clocks = <&scmi_clk ARMCLK_L>; + clocks = <&scmi_clk SCMI_ARMCLK_L>; operating-points-v2 = <&cluster0_opp_table>; cpu-idle-states = <&CPU_SLEEP>; }; @@ -146,7 +146,7 @@ reg = <0x3>; enable-method = "psci"; capacity-dmips-mhz = <485>; - clocks = <&scmi_clk ARMCLK_L>; + clocks = <&scmi_clk SCMI_ARMCLK_L>; operating-points-v2 = <&cluster0_opp_table>; cpu-idle-states = <&CPU_SLEEP>; }; @@ -157,7 +157,7 @@ reg = <0x100>; enable-method = "psci"; capacity-dmips-mhz = <1024>; - clocks = <&scmi_clk ARMCLK_B>; + clocks = <&scmi_clk SCMI_ARMCLK_B>; operating-points-v2 = <&cluster1_opp_table>; #cooling-cells = <2>; dynamic-power-coefficient = <320>; @@ -170,7 +170,7 @@ reg = <0x101>; enable-method = "psci"; capacity-dmips-mhz = <1024>; - clocks = <&scmi_clk ARMCLK_B>; + clocks = <&scmi_clk SCMI_ARMCLK_B>; operating-points-v2 = <&cluster1_opp_table>; cpu-idle-states = <&CPU_SLEEP>; }; @@ -181,7 +181,7 @@ reg = <0x102>; enable-method = "psci"; capacity-dmips-mhz = <1024>; - clocks = <&scmi_clk ARMCLK_B>; + clocks = <&scmi_clk SCMI_ARMCLK_B>; operating-points-v2 = <&cluster1_opp_table>; cpu-idle-states = <&CPU_SLEEP>; }; @@ -192,7 +192,7 @@ reg = <0x103>; enable-method = "psci"; capacity-dmips-mhz = <1024>; - clocks = <&scmi_clk ARMCLK_B>; + clocks = <&scmi_clk SCMI_ARMCLK_B>; operating-points-v2 = <&cluster1_opp_table>; cpu-idle-states = <&CPU_SLEEP>; }; @@ -393,6 +393,11 @@ }; }; + display_subsystem: display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vop_out>; + }; + firmware { scmi: scmi { compatible = "arm,scmi-smc"; @@ -620,6 +625,11 @@ }; }; + hdptxphy_grf: syscon@26032000 { + compatible = "rockchip,rk3576-hdptxphy-grf", "syscon"; + reg = <0x0 0x26032000 0x0 0x100>; + }; + vo1_grf: syscon@26036000 { compatible = "rockchip,rk3576-vo1-grf", "syscon"; reg = <0x0 0x26036000 0x0 0x100>; @@ -922,7 +932,7 @@ gpu: gpu@27800000 { compatible = "rockchip,rk3576-mali", "arm,mali-bifrost"; reg = <0x0 0x27800000 0x0 0x200000>; - assigned-clocks = <&scmi_clk CLK_GPU>; + assigned-clocks = <&scmi_clk SCMI_CLK_GPU>; assigned-clock-rates = <198000000>; clocks = <&cru CLK_GPU>; clock-names = "core"; @@ -937,6 +947,109 @@ status = "disabled"; }; + vop: vop@27d00000 { + compatible = "rockchip,rk3576-vop"; + reg = <0x0 0x27d00000 0x0 0x3000>, <0x0 0x27d05000 0x0 0x1000>; + reg-names = "vop", "gamma-lut"; + interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "sys", + "vp0", + "vp1", + "vp2"; + clocks = <&cru ACLK_VOP>, + <&cru HCLK_VOP>, + <&cru DCLK_VP0>, + <&cru DCLK_VP1>, + <&cru DCLK_VP2>; + clock-names = "aclk", + "hclk", + "dclk_vp0", + "dclk_vp1", + "dclk_vp2"; + iommus = <&vop_mmu>; + power-domains = <&power RK3576_PD_VOP>; + rockchip,grf = <&sys_grf>; + rockchip,pmu = <&pmu>; + status = "disabled"; + + vop_out: ports { + #address-cells = <1>; + #size-cells = <0>; + + vp0: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + vp1: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + vp2: port@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + }; + }; + + vop_mmu: iommu@27d07e00 { + compatible = "rockchip,rk3576-iommu", "rockchip,rk3568-iommu"; + reg = <0x0 0x27d07e00 0x0 0x100>, <0x0 0x27d07f00 0x0 0x100>; + interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + power-domains = <&power RK3576_PD_VOP>; + status = "disabled"; + }; + + hdmi: hdmi@27da0000 { + compatible = "rockchip,rk3576-dw-hdmi-qp"; + reg = <0x0 0x27da0000 0x0 0x20000>; + clocks = <&cru PCLK_HDMITX0>, + <&cru CLK_HDMITX0_EARC>, + <&cru CLK_HDMITX0_REF>, + <&cru MCLK_SAI6_8CH>, + <&cru CLK_HDMITXHDP>, + <&cru HCLK_VO0_ROOT>; + clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1"; + interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "avp", "cec", "earc", "main", "hpd"; + phys = <&hdptxphy>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_txm0_pins &hdmi_tx_scl &hdmi_tx_sda>; + power-domains = <&power RK3576_PD_VO0>; + resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMITXHDP>; + reset-names = "ref", "hdp"; + rockchip,grf = <&ioc_grf>; + rockchip,vo-grf = <&vo0_grf>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + hdmi_in: port@0 { + reg = <0>; + }; + + hdmi_out: port@1 { + reg = <1>; + }; + }; + }; + qos_hdcp1: qos@27f02000 { compatible = "rockchip,rk3576-qos", "syscon"; reg = <0x0 0x27f02000 0x0 0x20>; @@ -1221,6 +1334,41 @@ }; }; + ufshc: ufshc@2a2d0000 { + compatible = "rockchip,rk3576-ufshc"; + reg = <0x0 0x2a2d0000 0x0 0x10000>, + <0x0 0x2b040000 0x0 0x10000>, + <0x0 0x2601f000 0x0 0x1000>, + <0x0 0x2603c000 0x0 0x1000>, + <0x0 0x2a2e0000 0x0 0x10000>; + reg-names = "hci", "mphy", "hci_grf", "mphy_grf", "hci_apb"; + clocks = <&cru ACLK_UFS_SYS>, <&cru PCLK_USB_ROOT>, <&cru PCLK_MPHY>, + <&cru CLK_REF_UFS_CLKOUT>; + clock-names = "core", "pclk", "pclk_mphy", "ref_out"; + assigned-clocks = <&cru CLK_REF_OSC_MPHY>; + assigned-clock-parents = <&cru CLK_REF_MPHY_26M>; + interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&power RK3576_PD_USB>; + pinctrl-0 = <&ufs_refclk>; + pinctrl-names = "default"; + resets = <&cru SRST_A_UFS_BIU>, <&cru SRST_A_UFS_SYS>, + <&cru SRST_A_UFS>, <&cru SRST_P_UFS_GRF>; + reset-names = "biu", "sys", "ufs", "grf"; + reset-gpios = <&gpio4 RK_PD0 GPIO_ACTIVE_LOW>; + status = "disabled"; + }; + + sfc1: spi@2a300000 { + compatible = "rockchip,sfc"; + reg = <0x0 0x2a300000 0x0 0x4000>; + interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_FSPI1_X2>, <&cru HCLK_FSPI1>; + clock-names = "clk_sfc", "hclk_sfc"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + sdmmc: mmc@2a310000 { compatible = "rockchip,rk3576-dw-mshc"; reg = <0x0 0x2a310000 0x0 0x4000>; @@ -1260,6 +1408,17 @@ status = "disabled"; }; + sfc0: spi@2a340000 { + compatible = "rockchip,sfc"; + reg = <0x0 0x2a340000 0x0 0x4000>; + interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_FSPI_X2>, <&cru HCLK_FSPI>; + clock-names = "clk_sfc", "hclk_sfc"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + otp: otp@2a580000 { compatible = "rockchip,rk3576-otp"; reg = <0x0 0x2a580000 0x0 0x400>; @@ -1795,6 +1954,19 @@ status = "disabled"; }; + hdptxphy: hdmiphy@2b000000 { + compatible = "rockchip,rk3576-hdptx-phy", "rockchip,rk3588-hdptx-phy"; + reg = <0x0 0x2b000000 0x0 0x2000>; + clocks = <&cru CLK_PHY_REF_SRC>, <&cru PCLK_HDPTX_APB>; + clock-names = "ref", "apb"; + resets = <&cru SRST_P_HDPTX_APB>, <&cru SRST_HDPTX_INIT>, + <&cru SRST_HDPTX_CMN>, <&cru SRST_HDPTX_LANE>; + reset-names = "apb", "init", "cmn", "lane"; + rockchip,grf = <&hdptxphy_grf>; + #phy-cells = <0>; + status = "disabled"; + }; + sram: sram@3ff88000 { compatible = "mmio-sram"; reg = <0x0 0x3ff88000 0x0 0x78000>; diff --git a/dts/upstream/src/arm64/rockchip/rk3588-armsom-lm7.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-armsom-lm7.dtsi index a3138d2d384..e44125e9a8f 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588-armsom-lm7.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3588-armsom-lm7.dtsi @@ -114,6 +114,10 @@ }; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &saradc { vref-supply = <&avcc_1v8_s0>; status = "okay"; diff --git a/dts/upstream/src/arm64/rockchip/rk3588-armsom-sige7.dts b/dts/upstream/src/arm64/rockchip/rk3588-armsom-sige7.dts index 08f09053a06..ae9274365be 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588-armsom-sige7.dts +++ b/dts/upstream/src/arm64/rockchip/rk3588-armsom-sige7.dts @@ -4,6 +4,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/leds/common.h> +#include <dt-bindings/soc/rockchip,vop2.h> #include "rk3588.dtsi" / { @@ -33,6 +34,17 @@ "Headphone", "Headphones"; }; + hdmi0-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi0_con_in: endpoint { + remote-endpoint = <&hdmi0_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -164,6 +176,30 @@ status = "okay"; }; +&hdmi0 { + status = "okay"; +}; + +&hdmi0_in { + hdmi0_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi0>; + }; +}; + +&hdmi0_out { + hdmi0_out_con: endpoint { + remote-endpoint = <&hdmi0_con_in>; + }; +}; + +&hdmi0_sound { + status = "okay"; +}; + +&hdptxphy0 { + status = "okay"; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0m2_xfer>; @@ -258,6 +294,10 @@ }; }; +&i2s5_8ch { + status = "okay"; +}; + /* phy1 - right ethernet port */ &pcie2x1l0 { reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; @@ -268,6 +308,22 @@ &pcie2x1l1 { reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; status = "okay"; + + pcie@0,0 { + reg = <0x300000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + device_type = "pci"; + bus-range = <0x30 0x3f>; + + wifi: wifi@0,0 { + compatible = "pci14e4,449d"; + reg = <0x310000 0 0 0 0>; + clocks = <&hym8563>; + clock-names = "lpo"; + }; + }; }; /* phy0 - left ethernet port */ @@ -286,6 +342,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { hym8563 { hym8563_int: hym8563-int { @@ -723,3 +783,18 @@ dr_mode = "host"; status = "okay"; }; + +&vop_mmu { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = <ROCKCHIP_VOP2_EP_HDMI0>; + remote-endpoint = <&hdmi0_in_vp0>; + }; +}; diff --git a/dts/upstream/src/arm64/rockchip/rk3588-base.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-base.dtsi index 2623afa7963..1e18ad93ba0 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588-base.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3588-base.dtsi @@ -358,11 +358,6 @@ }; firmware { - optee: optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - scmi: scmi { compatible = "arm,scmi-smc"; arm,smc-id = <0x82000010>; @@ -382,6 +377,22 @@ }; }; + hdmi0_sound: hdmi0-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,name = "hdmi0"; + status = "disabled"; + + simple-audio-card,codec { + sound-dai = <&hdmi0>; + }; + + simple-audio-card,cpu { + sound-dai = <&i2s5_8ch>; + }; + }; + pmu-a55 { compatible = "arm,cortex-a55-pmu"; interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition0>; @@ -864,7 +875,7 @@ }; }; /* These power domains are grouped by VD_GPU */ - power-domain@RK3588_PD_GPU { + pd_gpu: power-domain@RK3588_PD_GPU { reg = <RK3588_PD_GPU>; clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>, @@ -1261,14 +1272,16 @@ <&cru DCLK_VOP1>, <&cru DCLK_VOP2>, <&cru DCLK_VOP3>, - <&cru PCLK_VOP_ROOT>; + <&cru PCLK_VOP_ROOT>, + <&hdptxphy0>; clock-names = "aclk", "hclk", "dclk_vp0", "dclk_vp1", "dclk_vp2", "dclk_vp3", - "pclk_vop"; + "pclk_vop", + "pll_hdmiphy0"; iommus = <&vop_mmu>; power-domains = <&power RK3588_PD_VOP>; rockchip,grf = <&sys_grf>; @@ -1318,6 +1331,21 @@ status = "disabled"; }; + spdif_tx2: spdif-tx@fddb0000 { + compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; + reg = <0x0 0xfddb0000 0x0 0x1000>; + assigned-clock-parents = <&cru PLL_AUPLL>; + assigned-clocks = <&cru CLK_SPDIF2_DP0_SRC>; + clock-names = "mclk", "hclk"; + clocks = <&cru MCLK_SPDIF2>, <&cru HCLK_SPDIF2_DP0>; + dma-names = "tx"; + dmas = <&dmac1 6>; + interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&power RK3588_PD_VO0>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + i2s4_8ch: i2s@fddc0000 { compatible = "rockchip,rk3588-i2s-tdm"; reg = <0x0 0xfddc0000 0x0 0x1000>; @@ -1335,6 +1363,21 @@ status = "disabled"; }; + spdif_tx3: spdif-tx@fdde0000 { + compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; + reg = <0x0 0xfdde0000 0x0 0x1000>; + assigned-clock-parents = <&cru PLL_AUPLL>; + assigned-clocks = <&cru CLK_SPDIF3_SRC>; + clock-names = "mclk", "hclk"; + clocks = <&cru MCLK_SPDIF3>, <&cru HCLK_SPDIF3>; + dma-names = "tx"; + dmas = <&dmac1 7>; + interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&power RK3588_PD_VO1>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + i2s5_8ch: i2s@fddf0000 { compatible = "rockchip,rk3588-i2s-tdm"; reg = <0x0 0xfddf0000 0x0 0x1000>; @@ -1385,7 +1428,7 @@ <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH 0>, <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH 0>; interrupt-names = "avp", "cec", "earc", "main", "hpd"; - phys = <&hdptxphy_hdmi0>; + phys = <&hdptxphy0>; pinctrl-names = "default"; pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd &hdmim0_tx0_scl &hdmim0_tx0_sda>; @@ -1394,6 +1437,7 @@ reset-names = "ref", "hdp"; rockchip,grf = <&sys_grf>; rockchip,vo-grf = <&vo1_grf>; + #sound-dai-cells = <0>; status = "disabled"; ports { @@ -2024,12 +2068,47 @@ status = "disabled"; }; + spdif_tx0: spdif-tx@fe4e0000 { + compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; + reg = <0x0 0xfe4e0000 0x0 0x1000>; + assigned-clock-parents = <&cru PLL_AUPLL>; + assigned-clocks = <&cru CLK_SPDIF0_SRC>; + clock-names = "mclk", "hclk"; + clocks = <&cru MCLK_SPDIF0>, <&cru HCLK_SPDIF0>; + dma-names = "tx"; + dmas = <&dmac0 5>; + interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&spdif0m0_tx>; + pinctrl-names = "default"; + power-domains = <&power RK3588_PD_AUDIO>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + spdif_tx1: spdif-tx@fe4f0000 { + compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; + reg = <0x0 0xfe4f0000 0x0 0x1000>; + assigned-clock-parents = <&cru PLL_AUPLL>; + assigned-clocks = <&cru CLK_SPDIF1_SRC>; + clock-names = "mclk", "hclk"; + clocks = <&cru MCLK_SPDIF1>, <&cru HCLK_SPDIF1>; + dma-names = "tx"; + dmas = <&dmac1 5>; + interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&spdif1m0_tx>; + pinctrl-names = "default"; + power-domains = <&power RK3588_PD_AUDIO>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + gic: interrupt-controller@fe600000 { compatible = "arm,gic-v3"; reg = <0x0 0xfe600000 0 0x10000>, /* GICD */ <0x0 0xfe680000 0 0x100000>; /* GICR */ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; interrupt-controller; + dma-noncoherent; mbi-alias = <0x0 0xfe610000>; mbi-ranges = <424 56>; msi-controller; @@ -2041,6 +2120,7 @@ its0: msi-controller@fe640000 { compatible = "arm,gic-v3-its"; reg = <0x0 0xfe640000 0x0 0x20000>; + dma-noncoherent; msi-controller; #msi-cells = <1>; }; @@ -2048,6 +2128,7 @@ its1: msi-controller@fe660000 { compatible = "arm,gic-v3-its"; reg = <0x0 0xfe660000 0x0 0x20000>; + dma-noncoherent; msi-controller; #msi-cells = <1>; }; @@ -2815,11 +2896,12 @@ #dma-cells = <1>; }; - hdptxphy_hdmi0: phy@fed60000 { + hdptxphy0: phy@fed60000 { compatible = "rockchip,rk3588-hdptx-phy"; reg = <0x0 0xfed60000 0x0 0x2000>; clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>; clock-names = "ref", "apb"; + #clock-cells = <0>; #phy-cells = <0>; resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>, <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>, diff --git a/dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5-evb.dts b/dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5-evb.dts index 9d525c8ff72..9eda6972266 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5-evb.dts +++ b/dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5-evb.dts @@ -129,7 +129,7 @@ }; }; -&hdptxphy_hdmi0 { +&hdptxphy0 { status = "okay"; }; diff --git a/dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5-genbook.dts b/dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5-genbook.dts index bc6b43a7715..6dc10da5215 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5-genbook.dts +++ b/dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5-genbook.dts @@ -166,7 +166,7 @@ }; }; -&hdptxphy_hdmi0 { +&hdptxphy0 { status = "okay"; }; diff --git a/dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5.dtsi index 71ed680621b..cc37f082ade 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5.dtsi @@ -277,6 +277,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { hym8563 { hym8563_int: hym8563-int { diff --git a/dts/upstream/src/arm64/rockchip/rk3588-edgeble-neu6a-common.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-edgeble-neu6a-common.dtsi index 5e72d0eff0e..8a783dc64c0 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588-edgeble-neu6a-common.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3588-edgeble-neu6a-common.dtsi @@ -126,6 +126,10 @@ }; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { leds { led_user_en: led_user_en { diff --git a/dts/upstream/src/arm64/rockchip/rk3588-edgeble-neu6a-io.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-edgeble-neu6a-io.dtsi index 7125790bbed..08920344a4b 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588-edgeble-neu6a-io.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3588-edgeble-neu6a-io.dtsi @@ -4,12 +4,24 @@ */ #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/soc/rockchip,vop2.h> / { chosen { stdout-path = "serial2:1500000n8"; }; + hdmi1-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi1_con_in: endpoint { + remote-endpoint = <&hdmi1_out_con>; + }; + }; + }; + /* Unnamed gated oscillator: 100MHz,3.3V,3225 */ pcie30_port0_refclk: pcie30_port1_refclk: pcie-oscillator { compatible = "gated-fixed-clock"; @@ -81,6 +93,26 @@ status = "okay"; }; +&hdmi1 { + status = "okay"; +}; + +&hdmi1_in { + hdmi1_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi1>; + }; +}; + +&hdmi1_out { + hdmi1_out_con: endpoint { + remote-endpoint = <&hdmi1_con_in>; + }; +}; + +&hdptxphy1 { + status = "okay"; +}; + &i2c6 { status = "okay"; @@ -275,3 +307,18 @@ &usb_host2_xhci { status = "okay"; }; + +&vop_mmu { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { + reg = <ROCKCHIP_VOP2_EP_HDMI1>; + remote-endpoint = <&hdmi1_in_vp0>; + }; +}; diff --git a/dts/upstream/src/arm64/rockchip/rk3588-evb1-v10.dts b/dts/upstream/src/arm64/rockchip/rk3588-evb1-v10.dts index ba49f0bbaac..8e912da299a 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588-evb1-v10.dts +++ b/dts/upstream/src/arm64/rockchip/rk3588-evb1-v10.dts @@ -132,6 +132,17 @@ }; }; + hdmi1-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi1_con_in: endpoint { + remote-endpoint = <&hdmi1_out_con>; + }; + }; + }; + pcie20_avdd0v85: regulator-pcie20-avdd0v85 { compatible = "regulator-fixed"; regulator-name = "pcie20_avdd0v85"; @@ -364,7 +375,27 @@ }; }; -&hdptxphy_hdmi0 { +&hdmi1 { + status = "okay"; +}; + +&hdmi1_in { + hdmi1_in_vp1: endpoint { + remote-endpoint = <&vp1_out_hdmi1>; + }; +}; + +&hdmi1_out { + hdmi1_out_con: endpoint { + remote-endpoint = <&hdmi1_con_in>; + }; +}; + +&hdptxphy0 { + status = "okay"; +}; + +&hdptxphy1 { status = "okay"; }; @@ -441,7 +472,7 @@ status = "okay"; es8388: audio-codec@11 { - compatible = "everest,es8388"; + compatible = "everest,es8388", "everest,es8328"; reg = <0x11>; clocks = <&cru I2S0_8CH_MCLKOUT>; assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; @@ -519,6 +550,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { audio { hp_detect: headphone-detect { @@ -1371,11 +1406,11 @@ status = "okay"; }; -&vop_mmu { +&vop { status = "okay"; }; -&vop { +&vop_mmu { status = "okay"; }; @@ -1385,3 +1420,10 @@ remote-endpoint = <&hdmi0_in_vp0>; }; }; + +&vp1 { + vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { + reg = <ROCKCHIP_VOP2_EP_HDMI1>; + remote-endpoint = <&hdmi1_in_vp1>; + }; +}; diff --git a/dts/upstream/src/arm64/rockchip/rk3588-extra.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-extra.dtsi index 840b638af1c..099edb3fd0f 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588-extra.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3588-extra.dtsi @@ -7,6 +7,46 @@ #include "rk3588-extra-pinctrl.dtsi" / { + hdmi1_sound: hdmi1-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,name = "hdmi1"; + status = "disabled"; + + simple-audio-card,codec { + sound-dai = <&hdmi1>; + }; + + simple-audio-card,cpu { + sound-dai = <&i2s6_8ch>; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* + * The 4k HDMI capture controller works only with 32bit + * phys addresses and doesn't support IOMMU. HDMI RX CMA + * must be reserved below 4GB. + * The size of 160MB was determined as follows: + * (3840 * 2160 pixels) * (4 bytes/pixel) * (2 frames/buffer) / 10^6 = 66MB + * To ensure sufficient support for practical use-cases, + * we doubled the 66MB value. + */ + hdmi_receiver_cma: hdmi-receiver-cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x0 0x0 0xffffffff>; + size = <0x0 (160 * 0x100000)>; /* 160MiB */ + alignment = <0x0 0x40000>; /* 64K */ + no-map; + status = "disabled"; + }; + }; + usb_host1_xhci: usb@fc400000 { compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; reg = <0x0 0xfc400000 0x0 0x400000>; @@ -67,6 +107,26 @@ }; }; + hdptxphy1_grf: syscon@fd5e4000 { + compatible = "rockchip,rk3588-hdptxphy-grf", "syscon"; + reg = <0x0 0xfd5e4000 0x0 0x100>; + }; + + spdif_tx5: spdif-tx@fddb8000 { + compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; + reg = <0x0 0xfddb8000 0x0 0x1000>; + assigned-clock-parents = <&cru PLL_AUPLL>; + assigned-clocks = <&cru CLK_SPDIF5_DP1_SRC>; + clock-names = "mclk", "hclk"; + clocks = <&cru MCLK_SPDIF5>, <&cru HCLK_SPDIF5_DP1>; + dma-names = "tx"; + dmas = <&dmac1 22>; + interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&power RK3588_PD_VO0>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + i2s8_8ch: i2s@fddc8000 { compatible = "rockchip,rk3588-i2s-tdm"; reg = <0x0 0xfddc8000 0x0 0x1000>; @@ -84,6 +144,21 @@ status = "disabled"; }; + spdif_tx4: spdif-tx@fdde8000 { + compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; + reg = <0x0 0xfdde8000 0x0 0x1000>; + assigned-clock-parents = <&cru PLL_AUPLL>; + assigned-clocks = <&cru CLK_SPDIF4_SRC>; + clock-names = "mclk", "hclk"; + clocks = <&cru MCLK_SPDIF4>, <&cru HCLK_SPDIF4>; + dma-names = "tx"; + dmas = <&dmac1 8>; + interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&power RK3588_PD_VO1>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + i2s6_8ch: i2s@fddf4000 { compatible = "rockchip,rk3588-i2s-tdm"; reg = <0x0 0xfddf4000 0x0 0x1000>; @@ -135,6 +210,79 @@ status = "disabled"; }; + hdmi1: hdmi@fdea0000 { + compatible = "rockchip,rk3588-dw-hdmi-qp"; + reg = <0x0 0xfdea0000 0x0 0x20000>; + clocks = <&cru PCLK_HDMITX1>, + <&cru CLK_HDMITX1_EARC>, + <&cru CLK_HDMITX1_REF>, + <&cru MCLK_I2S6_8CH_TX>, + <&cru CLK_HDMIHDP1>, + <&cru HCLK_VO1>; + clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1"; + interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "avp", "cec", "earc", "main", "hpd"; + phys = <&hdptxphy1>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmim2_tx1_cec &hdmim0_tx1_hpd + &hdmim1_tx1_scl &hdmim1_tx1_sda>; + power-domains = <&power RK3588_PD_VO1>; + resets = <&cru SRST_HDMITX1_REF>, <&cru SRST_HDMIHDP1>; + reset-names = "ref", "hdp"; + rockchip,grf = <&sys_grf>; + rockchip,vo-grf = <&vo1_grf>; + #sound-dai-cells = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + hdmi1_in: port@0 { + reg = <0>; + }; + + hdmi1_out: port@1 { + reg = <1>; + }; + }; + }; + + hdmi_receiver: hdmi_receiver@fdee0000 { + compatible = "rockchip,rk3588-hdmirx-ctrler", "snps,dw-hdmi-rx"; + reg = <0x0 0xfdee0000 0x0 0x6000>; + interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "cec", "hdmi", "dma"; + clocks = <&cru ACLK_HDMIRX>, + <&cru CLK_HDMIRX_AUD>, + <&cru CLK_CR_PARA>, + <&cru PCLK_HDMIRX>, + <&cru CLK_HDMIRX_REF>, + <&cru PCLK_S_HDMIRX>, + <&cru HCLK_VO1>; + clock-names = "aclk", + "audio", + "cr_para", + "pclk", + "ref", + "hclk_s_hdmirx", + "hclk_vo1"; + memory-region = <&hdmi_receiver_cma>; + power-domains = <&power RK3588_PD_VO1>; + resets = <&cru SRST_A_HDMIRX>, <&cru SRST_P_HDMIRX>, + <&cru SRST_HDMIRX_REF>, <&cru SRST_A_HDMIRX_BIU>; + reset-names = "axi", "apb", "ref", "biu"; + rockchip,grf = <&sys_grf>; + rockchip,vo1-grf = <&vo1_grf>; + status = "disabled"; + }; + pcie3x4: pcie@fe150000 { compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; #address-cells = <3>; @@ -398,6 +546,23 @@ }; }; + hdptxphy1: phy@fed70000 { + compatible = "rockchip,rk3588-hdptx-phy"; + reg = <0x0 0xfed70000 0x0 0x2000>; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX1>; + clock-names = "ref", "apb"; + #clock-cells = <0>; + #phy-cells = <0>; + resets = <&cru SRST_HDPTX1>, <&cru SRST_P_HDPTX1>, + <&cru SRST_HDPTX1_INIT>, <&cru SRST_HDPTX1_CMN>, + <&cru SRST_HDPTX1_LANE>, <&cru SRST_HDPTX1_ROPLL>, + <&cru SRST_HDPTX1_LCPLL>; + reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", + "lcpll"; + rockchip,grf = <&hdptxphy1_grf>; + status = "disabled"; + }; + usbdp_phy1: phy@fed90000 { compatible = "rockchip,rk3588-usbdp-phy"; reg = <0x0 0xfed90000 0x0 0x10000>; @@ -449,3 +614,24 @@ status = "disabled"; }; }; + +&vop { + clocks = <&cru ACLK_VOP>, + <&cru HCLK_VOP>, + <&cru DCLK_VOP0>, + <&cru DCLK_VOP1>, + <&cru DCLK_VOP2>, + <&cru DCLK_VOP3>, + <&cru PCLK_VOP_ROOT>, + <&hdptxphy0>, + <&hdptxphy1>; + clock-names = "aclk", + "hclk", + "dclk_vp0", + "dclk_vp1", + "dclk_vp2", + "dclk_vp3", + "pclk_vop", + "pll_hdmiphy0", + "pll_hdmiphy1"; +}; diff --git a/dts/upstream/src/arm64/rockchip/rk3588-fet3588-c.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-fet3588-c.dtsi index 39005131738..4331cdc70f9 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588-fet3588-c.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3588-fet3588-c.dtsi @@ -205,6 +205,10 @@ }; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { leds { led_rgb_b: led-rgb-b { diff --git a/dts/upstream/src/arm64/rockchip/rk3588-firefly-core-3588j.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-firefly-core-3588j.dtsi index 42c523b553c..80e16ea4154 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588-firefly-core-3588j.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3588-firefly-core-3588j.dtsi @@ -108,6 +108,10 @@ }; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &sdhci { bus-width = <8>; no-sdio; diff --git a/dts/upstream/src/arm64/rockchip/rk3588-firefly-icore-3588q.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-firefly-icore-3588q.dtsi new file mode 100644 index 00000000000..6726eeb4925 --- /dev/null +++ b/dts/upstream/src/arm64/rockchip/rk3588-firefly-icore-3588q.dtsi @@ -0,0 +1,443 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/rockchip.h> + +#include "rk3588.dtsi" + +/ { + compatible = "firefly,icore-3588q", "rockchip,rk3588"; + + aliases { + mmc0 = &sdhci; + }; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + status = "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible = "rockchip,rk8603", "rockchip,rk8602"; + reg = <0x43>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1m2_xfer>; + status = "okay"; + + vdd_npu_s0: vdd_npu_mem_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-name = "vdd_npu_s0"; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <150000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&spi2 { + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + num-cs = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + status = "okay"; + + pmic@0 { + compatible = "rockchip,rk806"; + reg = <0x0>; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + gpio-controller; + #gpio-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + spi-max-frequency = <1000000>; + system-power-controller; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_gpu_s0"; + regulator-enable-ramp-delay = <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_lit_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_log_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_vdenc_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-name = "vdd_2v0_pldo_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "avcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "avdd_1v2_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s0"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "pldo6_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_ddr_pll_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "avdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_0v85_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; diff --git a/dts/upstream/src/arm64/rockchip/rk3588-firefly-itx-3588j.dts b/dts/upstream/src/arm64/rockchip/rk3588-firefly-itx-3588j.dts index 2be5251d3e3..e086114c763 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588-firefly-itx-3588j.dts +++ b/dts/upstream/src/arm64/rockchip/rk3588-firefly-itx-3588j.dts @@ -337,7 +337,7 @@ }; }; -&hdptxphy_hdmi0 { +&hdptxphy0 { status = "okay"; }; diff --git a/dts/upstream/src/arm64/rockchip/rk3588-friendlyelec-cm3588-nas.dts b/dts/upstream/src/arm64/rockchip/rk3588-friendlyelec-cm3588-nas.dts index b3a04ca370b..8171fbfd819 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588-friendlyelec-cm3588-nas.dts +++ b/dts/upstream/src/arm64/rockchip/rk3588-friendlyelec-cm3588-nas.dts @@ -335,7 +335,7 @@ }; }; -&hdptxphy_hdmi0 { +&hdptxphy0 { status = "okay"; }; diff --git a/dts/upstream/src/arm64/rockchip/rk3588-friendlyelec-cm3588.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-friendlyelec-cm3588.dtsi index e3a9598b99f..af431fdcbea 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588-friendlyelec-cm3588.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3588-friendlyelec-cm3588.dtsi @@ -222,6 +222,10 @@ compatible = "realtek,rt5616"; reg = <0x1b>; #sound-dai-cells = <0>; + assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; + assigned-clock-rates = <12288000>; + clocks = <&cru I2S0_8CH_MCLKOUT>; + clock-names = "mclk"; }; }; @@ -256,6 +260,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { gpio-leds { led_sys_pin: led-sys-pin { diff --git a/dts/upstream/src/arm64/rockchip/rk3588-h96-max-v58.dts b/dts/upstream/src/arm64/rockchip/rk3588-h96-max-v58.dts index 4791b77f357..73d8ce4fde2 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588-h96-max-v58.dts +++ b/dts/upstream/src/arm64/rockchip/rk3588-h96-max-v58.dts @@ -140,6 +140,24 @@ regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; }; + + spdif_dit: spdif-dit { + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + spdif_sound: spdif-sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "SPDIF"; + + simple-audio-card,cpu { + sound-dai = <&spdif_tx0>; + }; + + simple-audio-card,codec { + sound-dai = <&spdif_dit>; + }; + }; }; &combphy0_ps { @@ -207,7 +225,7 @@ }; }; -&hdptxphy_hdmi0 { +&hdptxphy0 { status = "okay"; }; @@ -316,6 +334,10 @@ }; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { hym8563 { hym8563_int: hym8563-int { @@ -400,6 +422,12 @@ status = "okay"; }; +&spdif_tx0 { + pinctrl-names = "default"; + pinctrl-0 = <&spdif0m1_tx>; + status = "okay"; +}; + &spi2 { assigned-clocks = <&cru CLK_SPI2>; assigned-clock-rates = <200000000>; diff --git a/dts/upstream/src/arm64/rockchip/rk3588-jaguar-pre-ict-tester.dtso b/dts/upstream/src/arm64/rockchip/rk3588-jaguar-pre-ict-tester.dtso new file mode 100644 index 00000000000..9d44dfe2f30 --- /dev/null +++ b/dts/upstream/src/arm64/rockchip/rk3588-jaguar-pre-ict-tester.dtso @@ -0,0 +1,171 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2024 Cherry Embedded Solutions GmbH + * + * Device Tree Overlay for the Pre-ICT tester adapter for the Mezzanine + * connector on RK3588 Jaguar. + * + * This adapter has a PCIe Gen2 x1 M.2 M-Key connector and two proprietary + * camera connectors (each their own I2C bus, clock, reset and PWM lines as well + * as 2-lane CSI). + * + * This adapter routes some GPIOs to power rails and loops together some other + * GPIOs. + * + * This adapter is used during manufacturing for validating proper soldering of + * the mezzanine connector. + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/rockchip.h> + +&{/} { + pre_ict_tester_vcc_1v2: regulator-pre-ict-tester-vcc-1v2 { + compatible = "regulator-fixed"; + regulator-name = "pre_ict_tester_vcc_1v2"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + vin-supply = <&vcc_3v3_s3>; + }; + + pre_ict_tester_vcc_2v8: regulator-pre-ict-tester-vcc-2v8 { + compatible = "regulator-fixed"; + regulator-name = "pre_ict_tester_vcc_2v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + vin-supply = <&vcc_3v3_s3>; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&gpio3 { + pinctrl-0 = <&pre_ict_pwr2gpio>; + pinctrl-names = "default"; +}; + +&pcie2x1l2 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie2x1l2_perstn_m0>; + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; /* PCIE20X1_2_PERSTN_M0 */ + vpcie3v3-supply = <&vcc_3v3_s3>; + status = "okay"; +}; + +&pinctrl { + pcie2x1l2 { + pcie2x1l2_perstn_m0: pcie2x1l2-perstn-m0 { + rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pre-ict-tester { + pre_ict_pwr2gpio: pre-ict-pwr2gpio-pins { + rockchip,pins = + /* + * GPIO3_A3 requires two power rails to be properly + * routed to the mezzanine connector to report a proper + * value: VCC_1V8_S0_1 and VCC_IN_2. It may report an + * incorrect value if VCC_1V8_S0_1 isn't properly routed, + * but GPIO3_C6 would catch this HW soldering issue. + * If VCC_IN_2 is properly routed, GPIO3_A3 should be + * LOW. The signal shall not read HIGH in the event + * GPIO3_A3 isn't properly routed due to soldering + * issue. Therefore, let's enforce a pull-up (which is + * the SoC default for this pin). + */ + <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>, + /* + * GPIO3_A4 is directly routed to VCC_1V8_S0_2 power + * rail. It should be HIGH if all is properly soldered. + * To guarantee that, a pull-down is enforced (which is + * the SoC default for this pin) so that LOW is read if + * the loop doesn't exist on HW (soldering issue on + * either signals). + */ + <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>, + /* + * GPIO3_B2 requires two power rails to be properly + * routed to the mezzanine connector to report a proper + * value: VCC_1V8_S0_1 and VCC_IN_1. It may report an + * incorrect value if VCC_1V8_S0_1 isn't properly routed, + * but GPIO3_C6 would catch this HW soldering issue. + * If VCC_IN_1 is properly routed, GPIO3_B2 should be + * LOW. This is an issue if GPIO3_B2 isn't properly + * routed due to soldering issue, because GPIO3_B2 + * default bias is pull-down therefore being LOW. So + * the worst case scenario and the pass scenario expect + * the same value. Make GPIO3_B2 a pull-up so that a + * soldering issue on GPIO3_B2 reports HIGH but proper + * soldering reports LOW. + */ + <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>, + /* + * GPIO3_C6 is directly routed to VCC_1V8_S0_1 power + * rail. It should be HIGH if all is properly soldered. + * This is an issue if GPIO3_C6 or VCC_1V8_S0_1 isn't + * properly routed due to soldering issue, because + * GPIO3_C6 default bias is pull-up therefore being HIGH + * in all cases: + * - GPIO3_C6 is floating (so HIGH) if GPIO3_C6 is not + * routed properly, + * - GPIO3_C6 is floating (so HIGH) if VCC_1V8_S0_1 is + * not routed properly, + * - GPIO3_C6 is HIGH if everything is proper, + * Make GPIO3_C6 a pull-down so that a soldering issue + * on GPIO3_C6 or VCC_1V8_S0_1 reports LOW but proper + * soldering reports HIGH. + */ + <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_down>, + /* + * GPIO3_D2 is routed to VCC_5V0_1 power rail through a + * voltage divider on the adapter. + * It should be HIGH if all is properly soldered. + * To guarantee that, a pull-down is enforced (which is + * the SoC default for this pin) so that LOW is read if + * the loop doesn't exist on HW (soldering issue on + * either signals). + */ + <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_down>, + /* + * GPIO3_D3 is routed to VCC_5V0_2 power rail through a + * voltage divider on the adapter. + * It should be HIGH if all is properly soldered. + * To guarantee that, a pull-down is enforced (which is + * the SoC default for this pin) so that LOW is read if + * the loop doesn't exist on HW (soldering issue on + * either signals). + */ + <3 RK_PD3 RK_FUNC_GPIO &pcfg_pull_down>, + /* + * GPIO3_D4 is routed to VCC_3V3_S3_1 power rail through + * a voltage divider on the adapter. + * It should be HIGH if all is properly soldered. + * To guarantee that, a pull-down is enforced (which is + * the SoC default for this pin) so that LOW is read if + * the loop doesn't exist on HW (soldering issue on + * either signals). + */ + <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_down>, + /* + * GPIO3_D5 is routed to VCC_3V3_S3_2 power rail through + * a voltage divider on the adapter. + * It should be HIGH if all is properly soldered. + * To guarantee that, a pull-down is enforced (which is + * the SoC default for this pin) so that LOW is read if + * the loop doesn't exist on HW (soldering issue on + * either signals). + */ + <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; diff --git a/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts b/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts index 7f457ab7801..9fceea6c139 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts +++ b/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts @@ -303,7 +303,7 @@ }; }; -&hdptxphy_hdmi0 { +&hdptxphy0 { status = "okay"; }; @@ -333,6 +333,56 @@ }; }; + typec-portc@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio4>; + interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&cc_int1>; + vbus-supply = <&vcc_5v0_usb_c1>; + + connector { + compatible = "usb-c-connector"; + data-role = "dual"; + label = "USBC-1 P11"; + power-role = "source"; + self-powered; + source-pdos = + <PDO_FIXED(5000, 1500, PDO_FIXED_DATA_SWAP | PDO_FIXED_USB_COMM)>; + vbus-supply = <&vcc_5v0_usb_c1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usbc0_hs: endpoint { + remote-endpoint = <&usb_host0_xhci_drd_sw>; + }; + }; + + port@1 { + reg = <1>; + + usbc0_ss: endpoint { + remote-endpoint = <&usbdp_phy0_typec_ss>; + }; + }; + + port@2 { + reg = <2>; + + usbc0_sbu: endpoint { + remote-endpoint = <&usbdp_phy0_typec_sbu>; + }; + }; + }; + }; + }; + vdd_npu_s0: regulator@42 { compatible = "rockchip,rk8602"; reg = <0x42>; @@ -394,6 +444,56 @@ pinctrl-0 = <&i2c8m2_xfer>; status = "okay"; + typec-portc@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio4>; + interrupts = <RK_PA4 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&cc_int2>; + vbus-supply = <&vcc_5v0_usb_c2>; + + connector { + compatible = "usb-c-connector"; + data-role = "dual"; + label = "USBC-2 P12"; + power-role = "source"; + self-powered; + source-pdos = + <PDO_FIXED(5000, 1500, PDO_FIXED_DATA_SWAP | PDO_FIXED_USB_COMM)>; + vbus-supply = <&vcc_5v0_usb_c2>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usbc1_hs: endpoint { + remote-endpoint = <&usb_host1_xhci_drd_sw>; + }; + }; + + port@1 { + reg = <1>; + + usbc1_ss: endpoint { + remote-endpoint = <&usbdp_phy1_typec_ss>; + }; + }; + + port@2 { + reg = <2>; + + usbc1_sbu: endpoint { + remote-endpoint = <&usbdp_phy1_typec_sbu>; + }; + }; + }; + }; + }; + vdd_cpu_big0_s0: regulator@42 { compatible = "rockchip,rk8602"; reg = <0x42>; @@ -451,6 +551,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { emmc { emmc_reset: emmc-reset { @@ -483,6 +587,26 @@ rockchip,pins = <0 RK_PC7 12 &pcfg_pull_none>; }; }; + + usb3 { + cc_int1: cc-int1 { + rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + cc_int2: cc-int2 { + rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + typec0_sbu_dc_pins: typec0-sbu-dc-pins { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>, + <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + typec1_sbu_dc_pins: typec1-sbu-dc-pins { + rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_down>, + <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; }; &saradc { @@ -850,6 +974,24 @@ status = "okay"; }; +/* USB-C P11 connector */ +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +/* USB-C P12 connector */ +&u2phy1 { + status = "okay"; +}; + +&u2phy1_otg { + status = "okay"; +}; + &u2phy2 { status = "okay"; }; @@ -892,6 +1034,56 @@ status = "okay"; }; +/* Type-C on P11 */ +&usbdp_phy0 { + orientation-switch; + pinctrl-names = "default"; + pinctrl-0 = <&typec0_sbu_dc_pins>; + sbu1-dc-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; /* Q7_USB_C0_SBU1_DC */ + sbu2-dc-gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>; /* Q7_USB_C0_SBU2_DC */ + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + usbdp_phy0_typec_ss: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_ss>; + }; + + usbdp_phy0_typec_sbu: endpoint@1 { + reg = <1>; + remote-endpoint = <&usbc0_sbu>; + }; + }; +}; + +/* Type-C on P12 */ +&usbdp_phy1 { + orientation-switch; + pinctrl-names = "default"; + pinctrl-0 = <&typec1_sbu_dc_pins>; + sbu1-dc-gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; /* Q7_USB_C1_SBU1_DC */ + sbu2-dc-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; /* Q7_USB_C1_SBU2_DC */ + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + usbdp_phy1_typec_ss: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc1_ss>; + }; + + usbdp_phy1_typec_sbu: endpoint@1 { + reg = <1>; + remote-endpoint = <&usbc1_sbu>; + }; + }; +}; + /* host0 on P10 USB-A */ &usb_host0_ehci { status = "okay"; @@ -902,6 +1094,36 @@ status = "okay"; }; +/* host0 on P11 USB-C */ +&usb_host0_xhci { + usb-role-switch; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + usb_host0_xhci_drd_sw: endpoint { + remote-endpoint = <&usbc0_hs>; + }; + }; +}; + +/* host1 on P12 USB-C */ +&usb_host1_xhci { + usb-role-switch; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + usb_host1_xhci_drd_sw: endpoint { + remote-endpoint = <&usbc1_hs>; + }; + }; +}; + /* host1 on M.2 E-key */ &usb_host1_ehci { status = "okay"; diff --git a/dts/upstream/src/arm64/rockchip/rk3588-mnt-reform2.dts b/dts/upstream/src/arm64/rockchip/rk3588-mnt-reform2.dts new file mode 100644 index 00000000000..78a4e896f66 --- /dev/null +++ b/dts/upstream/src/arm64/rockchip/rk3588-mnt-reform2.dts @@ -0,0 +1,336 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Copyright (c) 2024 MNT Research GmbH + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/soc/rockchip,vop2.h> +#include <dt-bindings/usb/pd.h> + +#include "rk3588-firefly-icore-3588q.dtsi" + +/ { + model = "MNT Reform 2 with RCORE RK3588 Module"; + compatible = "mntre,reform2-rcore", "firefly,icore-3588q", "rockchip,rk3588"; + chassis-type = "laptop"; + + aliases { + ethernet0 = &gmac0; + mmc1 = &sdmmc; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = <0 8 16 32 64 128 160 200 255>; + default-brightness-level = <128>; + enable-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>; + pwms = <&pwm8 0 10000 0>; + }; + + gmac0_clkin: external-gmac0-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + clock-output-names = "gmac0_clkin"; + }; + + pcie30_avdd1v8: regulator-pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "pcie30_avdd1v8"; + vin-supply = <&avcc_1v8_s0>; + }; + + pcie30_avdd0v75: regulator-pcie30-avdd0v75 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "pcie30_avdd0v75"; + vin-supply = <&avdd_0v75_s0>; + }; + + vcc12v_dcin: regulator-vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-name = "vcc12v_dcin"; + }; + + vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_pcie30: regulator-vcc3v3-pcie30 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pcie30"; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_host: regulator-vcc5v0-host { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "vcc5v0_host"; + }; + + vcc5v0_sys: regulator-vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "vcc5v0_sys"; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usb: regulator-vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "vcc5v0_usb"; + vin-supply = <&vcc12v_dcin>; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&gmac0 { + clock_in_out = "output"; + phy-handle = <&rgmii_phy>; + phy-mode = "rgmii-id"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus + &gmac0_clkinout + ð_phy_reset>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + sram-supply = <&vdd_gpu_mem_s0>; + status = "okay"; +}; + +&hdmi0 { + status = "okay"; +}; + +&hdmi0_in { + hdmi0_in_vp2: endpoint { + remote-endpoint = <&vp2_out_hdmi0>; + }; +}; + +&hdptxphy0 { + status = "okay"; +}; + +&i2c6 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m0_xfer>; + status = "okay"; + + rtc@68 { + compatible = "nxp,pcf8523"; + reg = <0x68>; + }; +}; + +&mdio0 { + rgmii_phy: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; +}; + +&pcie2x1l2 { + pinctrl-0 = <&pcie2_0_rst>; + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x4 { + num-lanes = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie3_reset>; + reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; + +&pinctrl { + dp { + dp1_hpd: dp1-hpd { + rockchip,pins = <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie2 { + pcie2_0_rst: pcie2-0-rst { + rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie3 { + pcie3_reset: pcie3-reset { + rockchip,pins = <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + eth_phy { + eth_phy_reset: eth-phy-reset { + rockchip,pins = <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm8 { + pinctrl-0 = <&pwm8m2_pins>; + status = "okay"; +}; + +&saradc { + vref-supply = <&avcc_1v8_s0>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; + max-frequency = <40000000>; + no-1-8-v; + no-mmc; + no-sdio; + vmmc-supply = <&vcc3v3_pcie30>; + vqmmc-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy1_otg { + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&usbdp_phy0 { + status = "okay"; +}; + +&usbdp_phy1 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host0_xhci { + dr_mode = "host"; + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host1_xhci { + dr_mode = "host"; + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp2 { + vp2_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = <ROCKCHIP_VOP2_EP_HDMI0>; + remote-endpoint = <&hdmi0_in_vp2>; + }; +}; diff --git a/dts/upstream/src/arm64/rockchip/rk3588-nanopc-t6.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-nanopc-t6.dtsi index cb350727d11..bbe500cc924 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588-nanopc-t6.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3588-nanopc-t6.dtsi @@ -360,7 +360,7 @@ }; }; -&hdptxphy_hdmi0 { +&hdptxphy0 { status = "okay"; }; @@ -565,6 +565,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { gpio-leds { sys_led_pin: sys-led-pin { diff --git a/dts/upstream/src/arm64/rockchip/rk3588-ok3588-c.dts b/dts/upstream/src/arm64/rockchip/rk3588-ok3588-c.dts index 1c0851b45eb..fbe1d5c06d9 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588-ok3588-c.dts +++ b/dts/upstream/src/arm64/rockchip/rk3588-ok3588-c.dts @@ -312,6 +312,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { pcie2 { pcie2_0_rst: pcie2-0-rst { diff --git a/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5-compact.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5-compact.dtsi index 87090cb9802..f748c6f760d 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5-compact.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5-compact.dtsi @@ -7,9 +7,6 @@ #include "rk3588-orangepi-5.dtsi" / { - model = "Xunlong Orange Pi 5 Max"; - compatible = "xunlong,orangepi-5-max", "rockchip,rk3588"; - vcc5v0_usb30_otg: vcc5v0-usb30-otg-regulator { compatible = "regulator-fixed"; enable-active-high; @@ -62,18 +59,12 @@ &led_blue_pwm { /* PWM_LED1 */ - pwms = <&pwm4 0 25000 0>; status = "okay"; }; -&led_green_pwm { - /* PWM_LED2 */ - pwms = <&pwm5 0 25000 0>; -}; - /* phy2 */ &pcie2x1l1 { - reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_pcie_eth>; status = "okay"; }; diff --git a/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5-max.dts b/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5-max.dts index ce44549babf..8b1d35760c3 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5-max.dts +++ b/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5-max.dts @@ -21,6 +21,17 @@ }; }; }; + + hdmi1-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi1_con_in: endpoint { + remote-endpoint = <&hdmi1_out_con>; + }; + }; + }; }; &hdmi0 { @@ -39,10 +50,57 @@ }; }; -&hdptxphy_hdmi0 { +&hdmi0_sound { + status = "okay"; +}; + +&hdmi1 { + pinctrl-names = "default"; + pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd + &hdmim1_tx1_scl &hdmim1_tx1_sda>; + status = "okay"; +}; + +&hdmi1_in { + hdmi1_in_vp1: endpoint { + remote-endpoint = <&vp1_out_hdmi1>; + }; +}; + +&hdmi1_out { + hdmi1_out_con: endpoint { + remote-endpoint = <&hdmi1_con_in>; + }; +}; + +&hdmi1_sound { status = "okay"; }; +&hdptxphy0 { + status = "okay"; +}; + +&hdptxphy1 { + status = "okay"; +}; + +&i2s5_8ch { + status = "okay"; +}; + +&i2s6_8ch { + status = "okay"; +}; + +&led_blue_pwm { + pwms = <&pwm4 0 25000 0>; +}; + +&led_green_pwm { + pwms = <&pwm5 0 25000 0>; +}; + &pinctrl { usb { @@ -58,3 +116,10 @@ remote-endpoint = <&hdmi0_in_vp0>; }; }; + +&vp1 { + vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { + reg = <ROCKCHIP_VOP2_EP_HDMI1>; + remote-endpoint = <&hdmi1_in_vp1>; + }; +}; diff --git a/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5-plus.dts b/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5-plus.dts index 255e33c5dbd..121e4d1c3fa 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5-plus.dts +++ b/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5-plus.dts @@ -26,6 +26,17 @@ }; }; + hdmi1-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi1_con_in: endpoint { + remote-endpoint = <&hdmi1_out_con>; + }; + }; + }; + ir-receiver { compatible = "gpio-ir-receiver"; gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; @@ -113,6 +124,10 @@ status = "okay"; }; +&hdmi0_sound { + status = "okay"; +}; + &hdmi0_in { hdmi0_in_vp0: endpoint { remote-endpoint = <&vp0_out_hdmi0>; @@ -125,7 +140,31 @@ }; }; -&hdptxphy_hdmi0 { +&hdmi1 { + status = "okay"; +}; + +&hdmi1_in { + hdmi1_in_vp1: endpoint { + remote-endpoint = <&vp1_out_hdmi1>; + }; +}; + +&hdmi1_out { + hdmi1_out_con: endpoint { + remote-endpoint = <&hdmi1_con_in>; + }; +}; + +&hdmi1_sound { + status = "okay"; +}; + +&hdptxphy0 { + status = "okay"; +}; + +&hdptxphy1 { status = "okay"; }; @@ -189,6 +228,14 @@ }; }; +&i2s5_8ch { + status = "okay"; +}; + +&i2s6_8ch { + status = "okay"; +}; + &led_blue_gpio { gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; status = "okay"; @@ -342,3 +389,10 @@ remote-endpoint = <&hdmi0_in_vp0>; }; }; + +&vp1 { + vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { + reg = <ROCKCHIP_VOP2_EP_HDMI1>; + remote-endpoint = <&hdmi1_in_vp1>; + }; +}; diff --git a/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5-ultra.dts b/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5-ultra.dts new file mode 100644 index 00000000000..f8c6c080e41 --- /dev/null +++ b/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5-ultra.dts @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/pwm/pwm.h> +#include <dt-bindings/soc/rockchip,vop2.h> +#include "rk3588-orangepi-5-compact.dtsi" + +/ { + model = "Xunlong Orange Pi 5 Ultra"; + compatible = "xunlong,orangepi-5-ultra", "rockchip,rk3588"; + + hdmi1-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi1_con_in: endpoint { + remote-endpoint = <&hdmi1_out_con>; + }; + }; + }; +}; + +&hdmi1 { + pinctrl-names = "default"; + pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd + &hdmim1_tx1_scl &hdmim1_tx1_sda>; + status = "okay"; +}; + +&hdmi1_in { + hdmi1_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi1>; + }; +}; + +&hdmi1_out { + hdmi1_out_con: endpoint { + remote-endpoint = <&hdmi1_con_in>; + }; +}; + +&hdmi1_sound { + status = "okay"; +}; + +&hdptxphy1 { + status = "okay"; +}; + +&i2s6_8ch { + status = "okay"; +}; + +&led_blue_pwm { + pwms = <&pwm4 0 25000 PWM_POLARITY_INVERTED>; +}; + +&led_green_pwm { + pwms = <&pwm5 0 25000 PWM_POLARITY_INVERTED>; +}; + +&pinctrl { + usb { + usb_otg_pwren: usb-otg-pwren { + rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&vcc5v0_usb30_otg { + gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; +}; + +&vp0 { + vp0_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { + reg = <ROCKCHIP_VOP2_EP_HDMI1>; + remote-endpoint = <&hdmi1_in_vp0>; + }; +}; diff --git a/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5.dtsi index a98e804a094..91d56c34a1e 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5.dtsi @@ -276,7 +276,7 @@ /* PLDO2 vcca 1.8V, BUCK8 gated by PLDO2 being enabled */ es8388: audio-codec@11 { - compatible = "everest,es8388"; + compatible = "everest,es8388", "everest,es8328"; reg = <0x11>; clocks = <&cru I2S0_8CH_MCLKOUT>; AVDD-supply = <&vcc_3v3_s0>; @@ -348,6 +348,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &saradc { vref-supply = <&vcc_1v8_s0>; status = "okay"; diff --git a/dts/upstream/src/arm64/rockchip/rk3588-quartzpro64.dts b/dts/upstream/src/arm64/rockchip/rk3588-quartzpro64.dts index 088cfade6f6..78aaa6635b5 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588-quartzpro64.dts +++ b/dts/upstream/src/arm64/rockchip/rk3588-quartzpro64.dts @@ -311,7 +311,7 @@ status = "okay"; es8388: audio-codec@11 { - compatible = "everest,es8388"; + compatible = "everest,es8388", "everest,es8328"; reg = <0x11>; assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; assigned-clock-rates = <12288000>; @@ -347,6 +347,10 @@ }; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { hym8563 { hym8563_int: hym8563-int { diff --git a/dts/upstream/src/arm64/rockchip/rk3588-rock-5-itx.dts b/dts/upstream/src/arm64/rockchip/rk3588-rock-5-itx.dts index 2a059020946..7de17117df7 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588-rock-5-itx.dts +++ b/dts/upstream/src/arm64/rockchip/rk3588-rock-5-itx.dts @@ -11,6 +11,7 @@ #include <dt-bindings/leds/common.h> #include <dt-bindings/pinctrl/rockchip.h> #include <dt-bindings/pwm/pwm.h> +#include <dt-bindings/soc/rockchip,vop2.h> #include "dt-bindings/usb/pd.h" #include "rk3588.dtsi" @@ -72,6 +73,17 @@ }; }; + hdmi1-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi1_con_in: endpoint { + remote-endpoint = <&hdmi1_out_con>; + }; + }; + }; + /* Unnamed gated oscillator: 100MHz,3.3V,3225 */ pcie30_port0_refclk: pcie30_port1_refclk: pcie-oscillator { compatible = "gated-fixed-clock"; @@ -261,6 +273,28 @@ status = "okay"; }; +&hdmi1 { + pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd + &hdmim1_tx1_scl &hdmim1_tx1_sda>; + status = "okay"; +}; + +&hdmi1_in { + hdmi1_in_vp1: endpoint { + remote-endpoint = <&vp1_out_hdmi1>; + }; +}; + +&hdmi1_out { + hdmi1_out_con: endpoint { + remote-endpoint = <&hdmi1_con_in>; + }; +}; + +&hdptxphy1 { + status = "okay"; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0m2_xfer>; @@ -564,6 +598,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { hym8563 { rtc_int: rtc-int { @@ -1208,3 +1246,18 @@ rockchip,dp-lane-mux = <2 3>; status = "okay"; }; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp1 { + vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { + reg = <ROCKCHIP_VOP2_EP_HDMI1>; + remote-endpoint = <&hdmi1_in_vp1>; + }; +}; diff --git a/dts/upstream/src/arm64/rockchip/rk3588-rock-5b.dts b/dts/upstream/src/arm64/rockchip/rk3588-rock-5b.dts index d597112f1d5..d22068475c5 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588-rock-5b.dts +++ b/dts/upstream/src/arm64/rockchip/rk3588-rock-5b.dts @@ -49,6 +49,17 @@ }; }; + hdmi1-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi1_con_in: endpoint { + remote-endpoint = <&hdmi1_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -220,7 +231,48 @@ }; }; -&hdptxphy_hdmi0 { +&hdmi0_sound { + status = "okay"; +}; + +&hdmi1 { + pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd + &hdmim1_tx1_scl &hdmim1_tx1_sda>; + status = "okay"; +}; + +&hdmi1_in { + hdmi1_in_vp1: endpoint { + remote-endpoint = <&vp1_out_hdmi1>; + }; +}; + +&hdmi1_out { + hdmi1_out_con: endpoint { + remote-endpoint = <&hdmi1_con_in>; + }; +}; + +&hdmi1_sound { + status = "okay"; +}; + +&hdmi_receiver_cma { + status = "okay"; +}; + +&hdmi_receiver { + hpd-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_hpd>; + pinctrl-names = "default"; + status = "okay"; +}; + +&hdptxphy0 { + status = "okay"; +}; + +&hdptxphy1 { status = "okay"; }; @@ -318,6 +370,14 @@ }; }; +&i2s5_8ch { + status = "okay"; +}; + +&i2s6_8ch { + status = "okay"; +}; + &package_thermal { polling-delay = <1000>; @@ -376,7 +436,17 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { + hdmirx { + hdmirx_hpd: hdmirx-5v-detection { + rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + hym8563 { hym8563_int: hym8563-int { rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; @@ -891,11 +961,11 @@ status = "okay"; }; -&vop_mmu { +&vop { status = "okay"; }; -&vop { +&vop_mmu { status = "okay"; }; @@ -905,3 +975,10 @@ remote-endpoint = <&hdmi0_in_vp0>; }; }; + +&vp1 { + vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { + reg = <ROCKCHIP_VOP2_EP_HDMI1>; + remote-endpoint = <&hdmi1_in_vp1>; + }; +}; diff --git a/dts/upstream/src/arm64/rockchip/rk3588-tiger-haikou.dts b/dts/upstream/src/arm64/rockchip/rk3588-tiger-haikou.dts index 3187b4918a3..a3d8ff64783 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588-tiger-haikou.dts +++ b/dts/upstream/src/arm64/rockchip/rk3588-tiger-haikou.dts @@ -189,7 +189,7 @@ }; }; -&hdptxphy_hdmi0 { +&hdptxphy0 { status = "okay"; }; @@ -310,8 +310,10 @@ status = "okay"; }; +/* DB9 RS232/RS485 when SW2 in "UART1" mode */ &uart5 { rts-gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>; + status = "okay"; }; &usbdp_phy0 { diff --git a/dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi index e8fa449517c..c4933a08dd1 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi @@ -173,7 +173,6 @@ &i2c2 { pinctrl-0 = <&i2c2m3_xfer>; - status = "okay"; }; &i2c2m3_xfer { @@ -336,6 +335,10 @@ reset-gpios = <&gpio3 RK_PB6 GPIO_ACTIVE_HIGH>; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { emmc { emmc_reset: emmc-reset { diff --git a/dts/upstream/src/arm64/rockchip/rk3588-toybrick-x0.dts b/dts/upstream/src/arm64/rockchip/rk3588-toybrick-x0.dts index 3cbee5b9747..5a428e00ab9 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588-toybrick-x0.dts +++ b/dts/upstream/src/arm64/rockchip/rk3588-toybrick-x0.dts @@ -289,6 +289,10 @@ }; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { rtl8211f { rtl8211f_rst: rtl8211f-rst { diff --git a/dts/upstream/src/arm64/rockchip/rk3588-turing-rk1.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-turing-rk1.dtsi index 6bc46734cc1..60ad272982a 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588-turing-rk1.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3588-turing-rk1.dtsi @@ -214,6 +214,8 @@ }; &package_thermal { + polling-delay = <1000>; + trips { package_active1: trip-active1 { temperature = <45000>; @@ -287,6 +289,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { fan { fan_int: fan-int { diff --git a/dts/upstream/src/arm64/rockchip/rk3588j.dtsi b/dts/upstream/src/arm64/rockchip/rk3588j.dtsi index bce72bac450..3045cb3bd68 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588j.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3588j.dtsi @@ -11,20 +11,15 @@ compatible = "operating-points-v2"; opp-shared; - opp-1416000000 { - opp-hz = /bits/ 64 <1416000000>; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; opp-microvolt = <750000 750000 950000>; clock-latency-ns = <40000>; opp-suspend; }; - opp-1608000000 { - opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <887500 887500 950000>; - clock-latency-ns = <40000>; - }; - opp-1704000000 { - opp-hz = /bits/ 64 <1704000000>; - opp-microvolt = <937500 937500 950000>; + opp-1296000000 { + opp-hz = /bits/ 64 <1296000000>; + opp-microvolt = <775000 775000 950000>; clock-latency-ns = <40000>; }; }; @@ -33,9 +28,14 @@ compatible = "operating-points-v2"; opp-shared; + opp-1200000000{ + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <750000 750000 950000>; + clock-latency-ns = <40000>; + }; opp-1416000000 { opp-hz = /bits/ 64 <1416000000>; - opp-microvolt = <750000 750000 950000>; + opp-microvolt = <762500 762500 950000>; clock-latency-ns = <40000>; }; opp-1608000000 { @@ -43,25 +43,20 @@ opp-microvolt = <787500 787500 950000>; clock-latency-ns = <40000>; }; - opp-1800000000 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <875000 875000 950000>; - clock-latency-ns = <40000>; - }; - opp-2016000000 { - opp-hz = /bits/ 64 <2016000000>; - opp-microvolt = <950000 950000 950000>; - clock-latency-ns = <40000>; - }; }; cluster2_opp_table: opp-table-cluster2 { compatible = "operating-points-v2"; opp-shared; + opp-1200000000{ + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <750000 750000 950000>; + clock-latency-ns = <40000>; + }; opp-1416000000 { opp-hz = /bits/ 64 <1416000000>; - opp-microvolt = <750000 750000 950000>; + opp-microvolt = <762500 762500 950000>; clock-latency-ns = <40000>; }; opp-1608000000 { @@ -69,16 +64,6 @@ opp-microvolt = <787500 787500 950000>; clock-latency-ns = <40000>; }; - opp-1800000000 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <875000 875000 950000>; - clock-latency-ns = <40000>; - }; - opp-2016000000 { - opp-hz = /bits/ 64 <2016000000>; - opp-microvolt = <950000 950000 950000>; - clock-latency-ns = <40000>; - }; }; gpu_opp_table: opp-table { @@ -104,10 +89,6 @@ opp-hz = /bits/ 64 <700000000>; opp-microvolt = <750000 750000 850000>; }; - opp-850000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <787500 787500 850000>; - }; }; }; diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-coolpi-4b.dts b/dts/upstream/src/arm64/rockchip/rk3588s-coolpi-4b.dts index 9c394f733bb..8b717c4017a 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588s-coolpi-4b.dts +++ b/dts/upstream/src/arm64/rockchip/rk3588s-coolpi-4b.dts @@ -236,7 +236,7 @@ }; }; -&hdptxphy_hdmi0 { +&hdptxphy0 { status = "okay"; }; @@ -361,6 +361,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { hym8563 { hym8563_int: hym8563-int { @@ -429,7 +433,7 @@ }; &pwm13 { - pinctrl-names = "active"; + pinctrl-names = "default"; pinctrl-0 = <&pwm13m2_pins>; status = "okay"; }; @@ -803,6 +807,14 @@ status = "okay"; }; +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + &u2phy2 { status = "okay"; }; @@ -832,6 +844,16 @@ pinctrl-0 = <&uart9m2_xfer &uart9m2_ctsn>; }; +&usbdp_phy0 { + /* + * USBDP PHY0 is wired to a USB3 Type-A OTG connector. Additionally + * the differential pairs 0+1 and the aux channel are wired to a + * mini DP connector. + */ + rockchip,dp-lane-mux = <0 1>; + status = "okay"; +}; + &usb_host0_ehci { status = "okay"; }; @@ -840,6 +862,11 @@ status = "okay"; }; +&usb_host0_xhci { + extcon = <&u2phy0>; + status = "okay"; +}; + &usb_host1_ehci { status = "okay"; }; diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-evb1-v10.dts b/dts/upstream/src/arm64/rockchip/rk3588s-evb1-v10.dts index bc4077575be..9f4aca9c2e3 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588s-evb1-v10.dts +++ b/dts/upstream/src/arm64/rockchip/rk3588s-evb1-v10.dts @@ -242,7 +242,7 @@ status = "okay"; es8388: audio-codec@11 { - compatible = "everest,es8388"; + compatible = "everest,es8388", "everest,es8328"; reg = <0x11>; clocks = <&cru I2S0_8CH_MCLKOUT>; assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; @@ -340,6 +340,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { audio { hp_detect: headphone-detect { diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-gameforce-ace.dts b/dts/upstream/src/arm64/rockchip/rk3588s-gameforce-ace.dts index 812bba0aef1..873a2bd6a6d 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588s-gameforce-ace.dts +++ b/dts/upstream/src/arm64/rockchip/rk3588s-gameforce-ace.dts @@ -611,7 +611,7 @@ status = "okay"; es8388: audio-codec@11 { - compatible = "everest,es8388"; + compatible = "everest,es8388", "everest,es8328"; reg = <0x11>; assigned-clock-rates = <12288000>; assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; @@ -675,6 +675,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { audio-amplifier { headphone_amplifier_en: headphone-amplifier-en { diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-indiedroid-nova.dts b/dts/upstream/src/arm64/rockchip/rk3588s-indiedroid-nova.dts index 4a3aa80f222..4189a88ecf4 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588s-indiedroid-nova.dts +++ b/dts/upstream/src/arm64/rockchip/rk3588s-indiedroid-nova.dts @@ -278,7 +278,7 @@ }; }; -&hdptxphy_hdmi0 { +&hdptxphy0 { status = "okay"; }; @@ -412,7 +412,7 @@ status = "okay"; es8388: audio-codec@11 { - compatible = "everest,es8388"; + compatible = "everest,es8388", "everest,es8328"; reg = <0x11>; assigned-clock-rates = <12288000>; assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; @@ -455,6 +455,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { bluetooth-pins { bt_reset: bt-reset { diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-khadas-edge2.dts b/dts/upstream/src/arm64/rockchip/rk3588s-khadas-edge2.dts index ac48e7fd392..88a5e822ed1 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588s-khadas-edge2.dts +++ b/dts/upstream/src/arm64/rockchip/rk3588s-khadas-edge2.dts @@ -233,6 +233,10 @@ }; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { vdd_sd { vdd_sd_en: vdd-sd-en { diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-nanopi-r6.dtsi b/dts/upstream/src/arm64/rockchip/rk3588s-nanopi-r6.dtsi index d2eddea1840..fbf062ec3bf 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588s-nanopi-r6.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3588s-nanopi-r6.dtsi @@ -251,7 +251,7 @@ }; }; -&hdptxphy_hdmi0 { +&hdptxphy0 { status = "okay"; }; @@ -359,6 +359,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { gpio-key { key1_pin: key1-pin { diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-odroid-m2.dts b/dts/upstream/src/arm64/rockchip/rk3588s-odroid-m2.dts index 8f034c6d494..a72063c5514 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588s-odroid-m2.dts +++ b/dts/upstream/src/arm64/rockchip/rk3588s-odroid-m2.dts @@ -264,7 +264,7 @@ }; }; -&hdptxphy_hdmi0 { +&hdptxphy0 { status = "okay"; }; @@ -433,6 +433,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { lcd { lcd_pwren: lcd-pwren { diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-orangepi-5.dtsi b/dts/upstream/src/arm64/rockchip/rk3588s-orangepi-5.dtsi index d86aeacca23..4fedc50cce8 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588s-orangepi-5.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3588s-orangepi-5.dtsi @@ -197,7 +197,11 @@ }; }; -&hdptxphy_hdmi0 { +&hdmi0_sound { + status = "okay"; +}; + +&hdptxphy0 { status = "okay"; }; @@ -268,7 +272,7 @@ status = "okay"; es8388: audio-codec@10 { - compatible = "everest,es8388"; + compatible = "everest,es8388", "everest,es8328"; reg = <0x10>; clocks = <&cru I2S1_8CH_MCLKOUT>; AVDD-supply = <&vcc_3v3_s0>; @@ -355,6 +359,10 @@ status = "okay"; }; +&i2s5_8ch { + status = "okay"; +}; + &mdio1 { rgmii_phy1: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; @@ -365,6 +373,10 @@ }; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { hym8563 { hym8563_int: hym8563-int { diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts b/dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts index 70a43432bdc..f894742b1eb 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts +++ b/dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts @@ -334,7 +334,7 @@ }; }; -&hdptxphy_hdmi0 { +&hdptxphy0 { status = "okay"; }; @@ -359,6 +359,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { leds { io_led: io-led { diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-rock-5c.dts b/dts/upstream/src/arm64/rockchip/rk3588s-rock-5c.dts index 9b14d5383cd..dd7317bab61 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588s-rock-5c.dts +++ b/dts/upstream/src/arm64/rockchip/rk3588s-rock-5c.dts @@ -68,10 +68,10 @@ }; }; - fan { + fan: fan { compatible = "pwm-fan"; #cooling-cells = <2>; - cooling-levels = <0 64 128 192 255>; + cooling-levels = <0 24 44 64 128 192 255>; fan-supply = <&vcc_5v0>; pwms = <&pwm3 0 10000 0>; }; @@ -278,7 +278,7 @@ }; }; -&hdptxphy_hdmi0 { +&hdptxphy0 { status = "okay"; }; @@ -417,6 +417,36 @@ }; }; +&package_thermal { + polling-delay = <1000>; + + trips { + package_fan0: package-fan0 { + temperature = <55000>; + hysteresis = <2000>; + type = "active"; + }; + + package_fan1: package-fan1 { + temperature = <65000>; + hysteresis = <2000>; + type = "active"; + }; + }; + + cooling-maps { + map0 { + trip = <&package_fan0>; + cooling-device = <&fan THERMAL_NO_LIMIT 1>; + }; + + map1 { + trip = <&package_fan1>; + cooling-device = <&fan 2 THERMAL_NO_LIMIT>; + }; + }; +}; + &pcie2x1l2 { pinctrl-names = "default"; pinctrl-0 = <&pcie20x1_2_perstn_m0>; @@ -425,6 +455,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { leds { led_pins: led-pins { @@ -843,6 +877,8 @@ }; &tsadc { + rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ status = "okay"; }; |