diff options
Diffstat (limited to 'include/asm-ppc/immap_85xx.h')
| -rw-r--r-- | include/asm-ppc/immap_85xx.h | 80 |
1 files changed, 44 insertions, 36 deletions
diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index 559d6ea6caa..e5046bef321 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -13,6 +13,7 @@ #include <asm/types.h> #include <asm/fsl_i2c.h> +#include <asm/fsl_lbc.h> /* * Local-Access Registers and ECM Registers(0x0000-0x2000) @@ -1552,6 +1553,13 @@ typedef struct par_io { */ typedef struct ccsr_gur { uint porpllsr; /* 0xe0000 - POR PLL ratio status register */ +#ifdef CONFIG_MPC8536 +#define MPC85xx_PORPLLSR_DDR_RATIO 0x3e000000 +#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 25 +#else +#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003e00 +#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 9 +#endif uint porbmsr; /* 0xe0004 - POR boot mode status register */ #define MPC85xx_PORBMSR_HA 0x00070000 uint porimpscr; /* 0xe0008 - POR I/O impedance status and control register */ @@ -1561,7 +1569,8 @@ typedef struct ccsr_gur { #define MPC85xx_PORDEVSR_SGMII3_DIS 0x08000000 #define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000 #define MPC85xx_PORDEVSR_SRDS2_IO_SEL 0x38000000 -#define MPC85xx_PORDEVSR_IO_SEL 0x00380000 +#define MPC85xx_PORDEVSR_PCI1 0x00800000 +#define MPC85xx_PORDEVSR_IO_SEL 0x00780000 #define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000 #define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000 #define MPC85xx_PORDEVSR_PCI1_PCI32 0x00010000 @@ -1572,7 +1581,8 @@ typedef struct ccsr_gur { #define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007 uint pordbgmsr; /* 0xe0010 - POR debug mode status register */ uint pordevsr2; /* 0xe0014 - POR I/O device status regsiter 2 */ -#define MPC85xx_PORDEVSR2_SEC_CFG 0x00000020 +/* The 8544 RM says this is bit 26, but it's really bit 24 */ +#define MPC85xx_PORDEVSR2_SEC_CFG 0x00000080 char res1[8]; uint gpporcr; /* 0xe0020 - General-purpose POR configuration register */ char res2[12]; @@ -1638,39 +1648,37 @@ typedef struct ccsr_gur { char res15[61648]; /* 0xe0f30 to 0xefffff */ } ccsr_gur_t; -#define PORDEVSR_PCI (0x00800000) /* PCI Mode */ - -#define CFG_MPC85xx_GUTS_OFFSET (0xE0000) -#define CFG_MPC85xx_GUTS_ADDR (CFG_IMMR + CFG_MPC85xx_GUTS_OFFSET) -#define CFG_MPC85xx_ECM_OFFSET (0x0000) -#define CFG_MPC85xx_ECM_ADDR (CFG_IMMR + CFG_MPC85xx_ECM_OFFSET) -#define CFG_MPC85xx_DDR_OFFSET (0x2000) -#define CFG_MPC85xx_DDR_ADDR (CFG_IMMR + CFG_MPC85xx_DDR_OFFSET) -#define CFG_MPC85xx_DDR2_OFFSET (0x6000) -#define CFG_MPC85xx_DDR2_ADDR (CFG_IMMR + CFG_MPC85xx_DDR2_OFFSET) -#define CFG_MPC85xx_LBC_OFFSET (0x5000) -#define CFG_MPC85xx_LBC_ADDR (CFG_IMMR + CFG_MPC85xx_LBC_OFFSET) -#define CFG_MPC85xx_PCIX_OFFSET (0x8000) -#define CFG_MPC85xx_PCIX_ADDR (CFG_IMMR + CFG_MPC85xx_PCIX_OFFSET) -#define CFG_MPC85xx_PCIX2_OFFSET (0x9000) -#define CFG_MPC85xx_PCIX2_ADDR (CFG_IMMR + CFG_MPC85xx_PCIX2_OFFSET) -#define CFG_MPC85xx_SATA1_OFFSET (0x18000) -#define CFG_MPC85xx_SATA1_ADDR (CFG_IMMR + CFG_MPC85xx_SATA1_OFFSET) -#define CFG_MPC85xx_SATA2_OFFSET (0x19000) -#define CFG_MPC85xx_SATA2_ADDR (CFG_IMMR + CFG_MPC85xx_SATA2_OFFSET) -#define CFG_MPC85xx_L2_OFFSET (0x20000) -#define CFG_MPC85xx_L2_ADDR (CFG_IMMR + CFG_MPC85xx_L2_OFFSET) -#define CFG_MPC85xx_DMA_OFFSET (0x21000) -#define CFG_MPC85xx_DMA_ADDR (CFG_IMMR + CFG_MPC85xx_DMA_OFFSET) -#define CFG_MPC85xx_ESDHC_OFFSET (0x2e000) -#define CFG_MPC85xx_ESDHC_ADDR (CFG_IMMR + CFG_MPC85xx_ESDHC_OFFSET) -#define CFG_MPC85xx_PIC_OFFSET (0x40000) -#define CFG_MPC85xx_PIC_ADDR (CFG_IMMR + CFG_MPC85xx_PIC_OFFSET) -#define CFG_MPC85xx_CPM_OFFSET (0x80000) -#define CFG_MPC85xx_CPM_ADDR (CFG_IMMR + CFG_MPC85xx_CPM_OFFSET) -#define CFG_MPC85xx_SERDES1_OFFSET (0xE3000) -#define CFG_MPC85xx_SERDES1_ADDR (CFG_IMMR + CFG_MPC85xx_SERDES2_OFFSET) -#define CFG_MPC85xx_SERDES2_OFFSET (0xE3100) -#define CFG_MPC85xx_SERDES2_ADDR (CFG_IMMR + CFG_MPC85xx_SERDES2_OFFSET) +#define CONFIG_SYS_MPC85xx_GUTS_OFFSET (0xE0000) +#define CONFIG_SYS_MPC85xx_GUTS_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET) +#define CONFIG_SYS_MPC85xx_ECM_OFFSET (0x0000) +#define CONFIG_SYS_MPC85xx_ECM_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ECM_OFFSET) +#define CONFIG_SYS_MPC85xx_DDR_OFFSET (0x2000) +#define CONFIG_SYS_MPC85xx_DDR_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR_OFFSET) +#define CONFIG_SYS_MPC85xx_DDR2_OFFSET (0x6000) +#define CONFIG_SYS_MPC85xx_DDR2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR2_OFFSET) +#define CONFIG_SYS_MPC85xx_LBC_OFFSET (0x5000) +#define CONFIG_SYS_MPC85xx_LBC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET) +#define CONFIG_SYS_MPC85xx_PCIX_OFFSET (0x8000) +#define CONFIG_SYS_MPC85xx_PCIX_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX_OFFSET) +#define CONFIG_SYS_MPC85xx_PCIX2_OFFSET (0x9000) +#define CONFIG_SYS_MPC85xx_PCIX2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX2_OFFSET) +#define CONFIG_SYS_MPC85xx_SATA1_OFFSET (0x18000) +#define CONFIG_SYS_MPC85xx_SATA1_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA1_OFFSET) +#define CONFIG_SYS_MPC85xx_SATA2_OFFSET (0x19000) +#define CONFIG_SYS_MPC85xx_SATA2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA2_OFFSET) +#define CONFIG_SYS_MPC85xx_L2_OFFSET (0x20000) +#define CONFIG_SYS_MPC85xx_L2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_L2_OFFSET) +#define CONFIG_SYS_MPC85xx_DMA_OFFSET (0x21000) +#define CONFIG_SYS_MPC85xx_DMA_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DMA_OFFSET) +#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET (0x2e000) +#define CONFIG_SYS_MPC85xx_ESDHC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESDHC_OFFSET) +#define CONFIG_SYS_MPC85xx_PIC_OFFSET (0x40000) +#define CONFIG_SYS_MPC85xx_PIC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET) +#define CONFIG_SYS_MPC85xx_CPM_OFFSET (0x80000) +#define CONFIG_SYS_MPC85xx_CPM_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_CPM_OFFSET) +#define CONFIG_SYS_MPC85xx_SERDES1_OFFSET (0xE3000) +#define CONFIG_SYS_MPC85xx_SERDES1_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET) +#define CONFIG_SYS_MPC85xx_SERDES2_OFFSET (0xE3100) +#define CONFIG_SYS_MPC85xx_SERDES2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET) #endif /*__IMMAP_85xx__*/ |