diff options
Diffstat (limited to 'include/configs/DB64360.h')
| -rw-r--r-- | include/configs/DB64360.h | 290 |
1 files changed, 145 insertions, 145 deletions
diff --git a/include/configs/DB64360.h b/include/configs/DB64360.h index 0edd51abfa4..daed9342b37 100644 --- a/include/configs/DB64360.h +++ b/include/configs/DB64360.h @@ -132,13 +132,13 @@ if we use PCI it has its own MAC addr */ #define CONFIG_MISC_INIT_R /* initialize the icache L1 */ #define CONFIG_BOARD_EARLY_INIT_F -#define CFG_BOARD_NAME "DB64360" +#define CONFIG_SYS_BOARD_NAME "DB64360" #define CONFIG_IDENT_STRING "Marvell DB64360 (1.1)" -/*#define CFG_HUSH_PARSER */ -#undef CFG_HUSH_PARSER +/*#define CONFIG_SYS_HUSH_PARSER */ +#undef CONFIG_SYS_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " /* * The following defines let you select what serial you want to use @@ -146,7 +146,7 @@ if we use PCI it has its own MAC addr */ * * what to do: * to use the DUART, undef CONFIG_MPSC. If you have hacked a serial - * cable onto the second DUART channel, change the CFG_DUART port from 1 + * cable onto the second DUART channel, change the CONFIG_SYS_DUART port from 1 * to 0 below. * * to use the MPSC, #define CONFIG_MPSC. If you have wired up another @@ -210,7 +210,7 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0" /* --------------------------------------------------------------------------------------------------------------- */ #define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ -#define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */ #undef CONFIG_WATCHDOG /* watchdog disabled */ #undef CONFIG_ALTIVEC /* undef to disable */ @@ -265,74 +265,74 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0" /* * Miscellaneous configurable options */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 -#define CFG_I2C_MULTI_EEPROMS -#define CFG_I2C_SPEED 40000 /* I2C speed default */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_I2C_MULTI_EEPROMS +#define CONFIG_SYS_I2C_SPEED 40000 /* I2C speed default */ -/* #define CFG_GT_DUAL_CPU also for JTAG even with one cpu */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +/* #define CONFIG_SYS_GT_DUAL_CPU also for JTAG even with one cpu */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ #endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -/*#define CFG_MEMTEST_START 0x00400000 memtest works on */ -/*#define CFG_MEMTEST_END 0x00C00000 4 ... 12 MB in DRAM */ -/*#define CFG_MEMTEST_END 0x07c00000 4 ... 124 MB in DRAM */ +/*#define CONFIG_SYS_MEMTEST_START 0x00400000 memtest works on */ +/*#define CONFIG_SYS_MEMTEST_END 0x00C00000 4 ... 12 MB in DRAM */ +/*#define CONFIG_SYS_MEMTEST_END 0x07c00000 4 ... 124 MB in DRAM */ /* -#define CFG_DRAM_TEST +#define CONFIG_SYS_DRAM_TEST * DRAM tests - * CFG_DRAM_TEST - enables the following tests. + * CONFIG_SYS_DRAM_TEST - enables the following tests. * - * CFG_DRAM_TEST_DATA - Enables test for shorted or open data lines + * CONFIG_SYS_DRAM_TEST_DATA - Enables test for shorted or open data lines * Environment variable 'test_dram_data' must be * set to 'y'. - * CFG_DRAM_TEST_DATA - Enables test to verify that each word is uniquely + * CONFIG_SYS_DRAM_TEST_DATA - Enables test to verify that each word is uniquely * addressable. Environment variable * 'test_dram_address' must be set to 'y'. - * CFG_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test. + * CONFIG_SYS_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test. * This test takes about 6 minutes to test 64 MB. * Environment variable 'test_dram_walk' must be * set to 'y'. */ -#define CFG_DRAM_TEST -#if defined(CFG_DRAM_TEST) -#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ -/* #define CFG_MEMTEST_END 0x00C00000 4 ... 12 MB in DRAM */ -#define CFG_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */ -#define CFG_DRAM_TEST_DATA -#define CFG_DRAM_TEST_ADDRESS -#define CFG_DRAM_TEST_WALK -#endif /* CFG_DRAM_TEST */ +#define CONFIG_SYS_DRAM_TEST +#if defined(CONFIG_SYS_DRAM_TEST) +#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ +/* #define CONFIG_SYS_MEMTEST_END 0x00C00000 4 ... 12 MB in DRAM */ +#define CONFIG_SYS_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */ +#define CONFIG_SYS_DRAM_TEST_DATA +#define CONFIG_SYS_DRAM_TEST_ADDRESS +#define CONFIG_SYS_DRAM_TEST_WALK +#endif /* CONFIG_SYS_DRAM_TEST */ #undef CONFIG_DISPLAY_MEMMAP /* at the end of the bootprocess show the memory map */ -#undef CFG_DISPLAY_DIMM_SPD_CONTENT /* show SPD content during boot */ +#undef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT /* show SPD content during boot */ -#define CFG_LOAD_ADDR 0x00400000 /* default load address */ +#define CONFIG_SYS_LOAD_ADDR 0x00400000 /* default load address */ -#define CFG_HZ 1000 /* decr freq: 1ms ticks */ +#define CONFIG_SYS_HZ 1000 /* decr freq: 1ms ticks */ /*ronen - this the Sys clock (cpu bus,internal dram and SDRAM) */ -#define CFG_BUS_HZ 133000000 /* 133 MHz (CPU = 5*Bus = 666MHz) */ -#define CFG_BUS_CLK CFG_BUS_HZ +#define CONFIG_SYS_BUS_HZ 133000000 /* 133 MHz (CPU = 5*Bus = 666MHz) */ +#define CONFIG_SYS_BUS_CLK CONFIG_SYS_BUS_HZ -#define CFG_DDR_SDRAM_CYCLE_COUNT_LOP 7 /* define the SDRAM cycle count */ -#define CFG_DDR_SDRAM_CYCLE_COUNT_ROP 50 /* for 400MHZ -> 5.0 ns, for 133MHZ -> 7.50 ns */ +#define CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP 7 /* define the SDRAM cycle count */ +#define CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP 50 /* for 400MHZ -> 5.0 ns, for 133MHZ -> 7.50 ns */ /*ronen - this is the Tclk (MV64360 core) */ -#define CFG_TCLK 133000000 +#define CONFIG_SYS_TCLK 133000000 -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } -#define CFG_750FX_HID0 0x8000c084 -#define CFG_750FX_HID1 0x54800000 -#define CFG_750FX_HID2 0x00000000 +#define CONFIG_SYS_750FX_HID0 0x8000c084 +#define CONFIG_SYS_750FX_HID1 0x54800000 +#define CONFIG_SYS_750FX_HID2 0x00000000 /* * Low Level Configuration Settings @@ -345,51 +345,51 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0" */ /* - * When locking data in cache you should point the CFG_INIT_RAM_ADDRESS + * When locking data in cache you should point the CONFIG_SYS_INIT_RAM_ADDRESS * To an unused memory region. The stack will remain in cache until RAM * is initialized */ -#define CFG_INIT_RAM_LOCK -#define CFG_INIT_RAM_ADDR 0x40000000 /* unused memory region */ -#define CFG_INIT_RAM_END 0x1000 -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* unused memory region */ +#define CONFIG_SYS_INIT_RAM_END 0x1000 +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) #define RELOCATE_INTERNAL_RAM_ADDR #ifdef RELOCATE_INTERNAL_RAM_ADDR - #define CFG_INTERNAL_RAM_ADDR 0xf8000000 + #define CONFIG_SYS_INTERNAL_RAM_ADDR 0xf8000000 #endif /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 + * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 */ -#define CFG_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* Dummies for BAT 4-7 */ -#define CFG_SDRAM1_BASE 0x10000000 /* each 256 MByte */ -#define CFG_SDRAM2_BASE 0x20000000 -#define CFG_SDRAM3_BASE 0x30000000 -#define CFG_SDRAM4_BASE 0x40000000 -#define CFG_FLASH_BASE 0xfff00000 +#define CONFIG_SYS_SDRAM1_BASE 0x10000000 /* each 256 MByte */ +#define CONFIG_SYS_SDRAM2_BASE 0x20000000 +#define CONFIG_SYS_SDRAM3_BASE 0x30000000 +#define CONFIG_SYS_SDRAM4_BASE 0x40000000 +#define CONFIG_SYS_FLASH_BASE 0xfff00000 -#define CFG_DFL_BOOTCS_BASE 0xff800000 +#define CONFIG_SYS_DFL_BOOTCS_BASE 0xff800000 #define CONFIG_VERY_BIG_RAM /* we will use up to 256M memory for cause we are short of BATS*/ #define BRIDGE_REG_BASE_BOOTM 0xfbe00000 /* this paramaters are used when booting the linux kernel */ #define UART_BASE_BOOTM 0xfbb00000 /* in order to be sync with the kernel parameters. */ #define PCI0_IO_BASE_BOOTM 0xfd000000 -#define CFG_RESET_ADDRESS 0xfff00100 -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */ +#define CONFIG_SYS_RESET_ADDRESS 0xfff00100 +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */ /* areas to map different things with the GT in physical space */ -#define CFG_DRAM_BANKS 4 +#define CONFIG_SYS_DRAM_BANKS 4 /* What to put in the bats. */ -#define CFG_MISC_REGION_BASE 0xf0000000 +#define CONFIG_SYS_MISC_REGION_BASE 0xf0000000 /* Peripheral Device section */ @@ -403,30 +403,30 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0" /* Data flash on external device module */ /* Boot flash on external device module */ /*******************************************************/ -#define CFG_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */ -#define CFG_DB64360_RESET_ADDR 0x14000000 /* After power on Reset the DB64360 is here */ +#define CONFIG_SYS_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */ +#define CONFIG_SYS_DB64360_RESET_ADDR 0x14000000 /* After power on Reset the DB64360 is here */ /*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ -#define CFG_GT_REGS 0xf1000000 /* GT Registers will be mapped here */ -#define CFG_DEV_BASE 0xfc000000 /* GT Devices CS start here */ - -#define CFG_DEV0_SPACE CFG_DEV_BASE /* DEV_CS0 device modul sram */ -#define CFG_DEV1_SPACE (CFG_DEV0_SPACE + CFG_DEV0_SIZE) /* DEV_CS1 device modul real time clock (rtc) */ -#define CFG_DEV2_SPACE (CFG_DEV1_SPACE + CFG_DEV1_SIZE) /* DEV_CS2 device modul doubel uart (duart) */ -#define CFG_DEV3_SPACE (CFG_DEV2_SPACE + CFG_DEV2_SIZE) /* DEV_CS3 device modul large flash */ - -#define CFG_DEV0_SIZE _8M /* db64360 sram @ 0xfc00.0000 */ -#define CFG_DEV1_SIZE _8M /* db64360 rtc @ 0xfc80.0000 */ -#define CFG_DEV2_SIZE _16M /* db64360 duart @ 0xfd00.0000 */ -#define CFG_DEV3_SIZE _16M /* db64360 flash @ 0xfe00.0000 */ +#define CONFIG_SYS_GT_REGS 0xf1000000 /* GT Registers will be mapped here */ +#define CONFIG_SYS_DEV_BASE 0xfc000000 /* GT Devices CS start here */ + +#define CONFIG_SYS_DEV0_SPACE CONFIG_SYS_DEV_BASE /* DEV_CS0 device modul sram */ +#define CONFIG_SYS_DEV1_SPACE (CONFIG_SYS_DEV0_SPACE + CONFIG_SYS_DEV0_SIZE) /* DEV_CS1 device modul real time clock (rtc) */ +#define CONFIG_SYS_DEV2_SPACE (CONFIG_SYS_DEV1_SPACE + CONFIG_SYS_DEV1_SIZE) /* DEV_CS2 device modul doubel uart (duart) */ +#define CONFIG_SYS_DEV3_SPACE (CONFIG_SYS_DEV2_SPACE + CONFIG_SYS_DEV2_SIZE) /* DEV_CS3 device modul large flash */ + +#define CONFIG_SYS_DEV0_SIZE _8M /* db64360 sram @ 0xfc00.0000 */ +#define CONFIG_SYS_DEV1_SIZE _8M /* db64360 rtc @ 0xfc80.0000 */ +#define CONFIG_SYS_DEV2_SIZE _16M /* db64360 duart @ 0xfd00.0000 */ +#define CONFIG_SYS_DEV3_SIZE _16M /* db64360 flash @ 0xfe00.0000 */ /*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ /* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected by device width */ -#define CFG_DEV0_PAR 0x8FEFFFFF /* 32Bit sram */ -#define CFG_DEV1_PAR 0x8FCFFFFF /* 8Bit rtc */ -#define CFG_DEV2_PAR 0x8FCFFFFF /* 8Bit duart */ -#define CFG_8BIT_BOOT_PAR 0x8FCFFFFF /* 8Bit flash */ -#define CFG_32BIT_BOOT_PAR 0x8FEFFFFF /* 32Bit flash */ +#define CONFIG_SYS_DEV0_PAR 0x8FEFFFFF /* 32Bit sram */ +#define CONFIG_SYS_DEV1_PAR 0x8FCFFFFF /* 8Bit rtc */ +#define CONFIG_SYS_DEV2_PAR 0x8FCFFFFF /* 8Bit duart */ +#define CONFIG_SYS_8BIT_BOOT_PAR 0x8FCFFFFF /* 8Bit flash */ +#define CONFIG_SYS_32BIT_BOOT_PAR 0x8FEFFFFF /* 32Bit flash */ /* c 4 a 8 2 4 1 c */ /* 33 22|2222|22 22|111 1|11 11|1 1 | | */ @@ -436,28 +436,28 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0" /* ronen - update MPP Control MV64360*/ -#define CFG_MPP_CONTROL_0 0x02222222 -#define CFG_MPP_CONTROL_1 0x11333011 -#define CFG_MPP_CONTROL_2 0x40431111 -#define CFG_MPP_CONTROL_3 0x00000044 +#define CONFIG_SYS_MPP_CONTROL_0 0x02222222 +#define CONFIG_SYS_MPP_CONTROL_1 0x11333011 +#define CONFIG_SYS_MPP_CONTROL_2 0x40431111 +#define CONFIG_SYS_MPP_CONTROL_3 0x00000044 -/*# define CFG_SERIAL_PORT_MUX 0x00000102 0=hiZ 1=MPSC0 2=ETH 0 and 2 RMII */ +/*# define CONFIG_SYS_SERIAL_PORT_MUX 0x00000102 0=hiZ 1=MPSC0 2=ETH 0 and 2 RMII */ -# define CFG_GPP_LEVEL_CONTROL 0x2c600000 /* 1111 1001 0000 1111 1100 0000 0000 0000*/ +# define CONFIG_SYS_GPP_LEVEL_CONTROL 0x2c600000 /* 1111 1001 0000 1111 1100 0000 0000 0000*/ /* gpp[31] gpp[30] gpp[29] gpp[28] */ /* gpp[27] gpp[24]*/ /* gpp[19:14] */ /* setup new config_value for MV64360 DDR-RAM !! */ -# define CFG_SDRAM_CONFIG 0x58200400 /* 0x1400 copied from Dink32 bzw. VxWorks*/ +# define CONFIG_SYS_SDRAM_CONFIG 0x58200400 /* 0x1400 copied from Dink32 bzw. VxWorks*/ -#define CFG_DUART_IO CFG_DEV2_SPACE -#define CFG_DUART_CHAN 1 /* channel to use for console */ -#define CFG_INIT_CHAN1 -#define CFG_INIT_CHAN2 +#define CONFIG_SYS_DUART_IO CONFIG_SYS_DEV2_SPACE +#define CONFIG_SYS_DUART_CHAN 1 /* channel to use for console */ +#define CONFIG_SYS_INIT_CHAN1 +#define CONFIG_SYS_INIT_CHAN2 -#define SRAM_BASE CFG_DEV0_SPACE +#define SRAM_BASE CONFIG_SYS_DEV0_SPACE #define SRAM_SIZE 0x00100000 /* 1 MB of sram */ @@ -476,29 +476,29 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0" #define CONFIG_EEPRO100 /* ronen - Support for Intel 82557/82559/82559ER chips */ /* PCI MEMORY MAP section */ -#define CFG_PCI0_MEM_BASE 0x80000000 -#define CFG_PCI0_MEM_SIZE _128M -#define CFG_PCI1_MEM_BASE 0x88000000 -#define CFG_PCI1_MEM_SIZE _128M +#define CONFIG_SYS_PCI0_MEM_BASE 0x80000000 +#define CONFIG_SYS_PCI0_MEM_SIZE _128M +#define CONFIG_SYS_PCI1_MEM_BASE 0x88000000 +#define CONFIG_SYS_PCI1_MEM_SIZE _128M -#define CFG_PCI0_0_MEM_SPACE (CFG_PCI0_MEM_BASE) -#define CFG_PCI1_0_MEM_SPACE (CFG_PCI1_MEM_BASE) +#define CONFIG_SYS_PCI0_0_MEM_SPACE (CONFIG_SYS_PCI0_MEM_BASE) +#define CONFIG_SYS_PCI1_0_MEM_SPACE (CONFIG_SYS_PCI1_MEM_BASE) /* PCI I/O MAP section */ -#define CFG_PCI0_IO_BASE 0xfa000000 -#define CFG_PCI0_IO_SIZE _16M -#define CFG_PCI1_IO_BASE 0xfb000000 -#define CFG_PCI1_IO_SIZE _16M +#define CONFIG_SYS_PCI0_IO_BASE 0xfa000000 +#define CONFIG_SYS_PCI0_IO_SIZE _16M +#define CONFIG_SYS_PCI1_IO_BASE 0xfb000000 +#define CONFIG_SYS_PCI1_IO_SIZE _16M -#define CFG_PCI0_IO_SPACE (CFG_PCI0_IO_BASE) -#define CFG_PCI0_IO_SPACE_PCI (CFG_PCI0_IO_BASE) /* ronen we want phy=bus 0x00000000 */ -#define CFG_PCI1_IO_SPACE (CFG_PCI1_IO_BASE) -#define CFG_PCI1_IO_SPACE_PCI (CFG_PCI1_IO_BASE) /* ronen we want phy=bus 0x00000000 */ +#define CONFIG_SYS_PCI0_IO_SPACE (CONFIG_SYS_PCI0_IO_BASE) +#define CONFIG_SYS_PCI0_IO_SPACE_PCI (CONFIG_SYS_PCI0_IO_BASE) /* ronen we want phy=bus 0x00000000 */ +#define CONFIG_SYS_PCI1_IO_SPACE (CONFIG_SYS_PCI1_IO_BASE) +#define CONFIG_SYS_PCI1_IO_SPACE_PCI (CONFIG_SYS_PCI1_IO_BASE) /* ronen we want phy=bus 0x00000000 */ #if defined (CONFIG_750CX) -#define CFG_PCI_IDSEL 0x0 +#define CONFIG_SYS_PCI_IDSEL 0x0 #else -#define CFG_PCI_IDSEL 0x30 +#define CONFIG_SYS_PCI_IDSEL 0x30 #endif /*---------------------------------------------------------------------- * Initial BAT mappings @@ -510,28 +510,28 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0" */ /* SDRAM */ -#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_DBAT0U CFG_IBAT0U +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U /* init ram */ -#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) -#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP) -#define CFG_DBAT1L CFG_IBAT1L -#define CFG_DBAT1U CFG_IBAT1U +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L +#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U /* PCI0, PCI1 in one BAT */ -#define CFG_IBAT2L BATL_NO_ACCESS -#define CFG_IBAT2U CFG_DBAT2U -#define CFG_DBAT2L (CFG_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CFG_DBAT2U (CFG_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS +#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U +#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) /* GT regs, bootrom, all the devices, PCI I/O */ -#define CFG_IBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW) -#define CFG_IBAT3U (CFG_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M) -#define CFG_DBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CFG_DBAT3U CFG_IBAT3U +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW) +#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M) +#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U /* I2C addresses for the two DIMM SPD chips */ #define DIMM0_I2C_ADDR 0x56 @@ -542,35 +542,35 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0" * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ /*----------------------------------------------------------------------- * FLASH organization */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ -#define CFG_EXTRA_FLASH_DEVICE DEVICE3 /* extra flash at device 3 */ -#define CFG_EXTRA_FLASH_WIDTH 4 /* 32 bit */ -#define CFG_BOOT_FLASH_WIDTH 1 /* 8 bit */ +#define CONFIG_SYS_EXTRA_FLASH_DEVICE DEVICE3 /* extra flash at device 3 */ +#define CONFIG_SYS_EXTRA_FLASH_WIDTH 4 /* 32 bit */ +#define CONFIG_SYS_BOOT_FLASH_WIDTH 1 /* 8 bit */ -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ -#define CFG_FLASH_LOCK_TOUT 500 /* Timeout for Flash Lock (in ms) */ -#define CFG_FLASH_CFI 1 +#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +#define CONFIG_SYS_FLASH_LOCK_TOUT 500 /* Timeout for Flash Lock (in ms) */ +#define CONFIG_SYS_FLASH_CFI 1 #define CONFIG_ENV_IS_IN_FLASH 1 #define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ #define CONFIG_ENV_SECT_SIZE 0x10000 #define CONFIG_ENV_ADDR 0xFFF78000 /* Marvell 8-Bit Bootflash last sector */ -/* #define CONFIG_ENV_ADDR (CFG_FLASH_BASE+CFG_MONITOR_LEN-CONFIG_ENV_SECT_SIZE) */ +/* #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-CONFIG_ENV_SECT_SIZE) */ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ +#define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ #if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif /*----------------------------------------------------------------------- @@ -578,7 +578,7 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0" * look in include/mpc74xx.h for the defines used here */ -#define CFG_L2 +#define CONFIG_SYS_L2 #if defined (CONFIG_750CX) || defined (CONFIG_750FX) @@ -602,6 +602,6 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0" #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#define CFG_BOARD_ASM_INIT 1 +#define CONFIG_SYS_BOARD_ASM_INIT 1 #endif /* __CONFIG_H */ |