diff options
Diffstat (limited to 'include/configs/mx1fs2.h')
| -rw-r--r-- | include/configs/mx1fs2.h | 96 |
1 files changed, 48 insertions, 48 deletions
diff --git a/include/configs/mx1fs2.h b/include/configs/mx1fs2.h index 39950dc5411..aaa4e985220 100644 --- a/include/configs/mx1fs2.h +++ b/include/configs/mx1fs2.h @@ -70,22 +70,22 @@ /* * General options for u-boot. Modify to save memory foot print */ -#define CFG_LONGHELP /* undef saves memory */ -#define CFG_PROMPT "mx1fs2> " /* prompt string */ -#define CFG_CBSIZE 256 /* console I/O buffer */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* print buffer size */ -#define CFG_MAXARGS 16 /* max command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* boot args buf size */ +#define CONFIG_SYS_LONGHELP /* undef saves memory */ +#define CONFIG_SYS_PROMPT "mx1fs2> " /* prompt string */ +#define CONFIG_SYS_CBSIZE 256 /* console I/O buffer */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* print buffer size */ +#define CONFIG_SYS_MAXARGS 16 /* max command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* boot args buf size */ -#define CFG_MEMTEST_START 0x08100000 /* memtest test area */ -#define CFG_MEMTEST_END 0x08F00000 +#define CONFIG_SYS_MEMTEST_START 0x08100000 /* memtest test area */ +#define CONFIG_SYS_MEMTEST_END 0x08F00000 -#undef CFG_CLKS_IN_HZ /* use HZ for freq. display */ +#undef CONFIG_SYS_CLKS_IN_HZ /* use HZ for freq. display */ -#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ -#define CFG_CPUSPEED 0x141 /* core clock - register value */ +#define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */ +#define CONFIG_SYS_CPUSPEED 0x141 /* core clock - register value */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } #define CONFIG_BAUDRATE 115200 /* * Definitions related to passing arguments to kernel. @@ -98,10 +98,10 @@ /* * Malloc pool need to host env + 128 Kb reserve for other allocations. */ -#define CFG_MALLOC_LEN (CONFIG_ENV_SIZE + (128<<10) ) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128<<10) ) -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ #define CONFIG_STACKSIZE (120<<10) /* stack size */ @@ -135,8 +135,8 @@ * Flash Controller settings */ -#define CFG_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/ -#define CFG_MAX_FLASH_SECT 256 /* number of sector in FLASH bank */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/ +#define CONFIG_SYS_MAX_FLASH_SECT 256 /* number of sector in FLASH bank */ #ifdef BUS32BIT_VERSION #define MX1FS2_FLASH_BUS_WIDTH 4 /* we use 32 bit FLASH memory... */ @@ -156,12 +156,12 @@ is not so clear to me. In other words we can provide more informations to user, but this expects more complex flash handling we do not provide now.*/ -#undef CFG_FLASH_CFI +#undef CONFIG_SYS_FLASH_CFI -#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* timeout for Erase operation */ -#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* timeout for Write operation */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* timeout for Erase operation */ +#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* timeout for Write operation */ -#define CFG_FLASH_BASE MX1FS2_FLASH_BASE +#define CONFIG_SYS_FLASH_BASE MX1FS2_FLASH_BASE /* * This is setting for JFFS2 support in u-boot. @@ -205,8 +205,8 @@ * env. has no sense to us. */ -#define CFG_MONITOR_BASE 0x10000000 -#define CFG_MONITOR_LEN 0x20000 /* 128b ( 1 flash sector ) */ +#define CONFIG_SYS_MONITOR_BASE 0x10000000 +#define CONFIG_SYS_MONITOR_LEN 0x20000 /* 128b ( 1 flash sector ) */ #define CONFIG_ENV_IS_IN_FLASH 1 #define CONFIG_ENV_ADDR 0x10020000 /* absolute address for now */ #define CONFIG_ENV_SIZE 0x20000 @@ -214,7 +214,7 @@ #define CONFIG_ENV_OVERWRITE 1 /* env is not writable now */ /* Setup CS4 and CS5 */ -#define CFG_GIUS_A_VAL 0x0003fffe +#define CONFIG_SYS_GIUS_A_VAL 0x0003fffe /* * CSxU_VAL: @@ -226,14 +226,14 @@ * | OEA | OEN | WEA | WEN | CSA |EBC| DSZ | 0|SP|0|WP| 0 0|PA|CSEN| */ -#define CFG_CS0U_VAL 0x00008C00 -#define CFG_CS0L_VAL 0x22222601 -#define CFG_CS1U_VAL 0x00008C00 -#define CFG_CS1L_VAL 0x22222301 -#define CFG_CS4U_VAL 0x00008C00 -#define CFG_CS4L_VAL 0x22222301 -#define CFG_CS5U_VAL 0x00008C00 -#define CFG_CS5L_VAL 0x22222301 +#define CONFIG_SYS_CS0U_VAL 0x00008C00 +#define CONFIG_SYS_CS0L_VAL 0x22222601 +#define CONFIG_SYS_CS1U_VAL 0x00008C00 +#define CONFIG_SYS_CS1L_VAL 0x22222301 +#define CONFIG_SYS_CS4U_VAL 0x00008C00 +#define CONFIG_SYS_CS4L_VAL 0x22222301 +#define CONFIG_SYS_CS5U_VAL 0x00008C00 +#define CONFIG_SYS_CS5L_VAL 0x22222301 /* f_{dpll}=2*f{ref}*(MFI+MFN/(MFD+1))/(PD+1) f_ref=16,777MHz @@ -252,25 +252,25 @@ 31 |x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x| 0 |XXX|--PD---|-------MFD---------|XXX|--MFI--|-----MFN-----------| */ -#define CFG_MPCTL0_VAL 0x07E723AD -#define CFG_MPCTL1_VAL 0x00000040 -#define CFG_PCDR_VAL 0x00010005 -#define CFG_GPCR_VAL 0x00000FFB +#define CONFIG_SYS_MPCTL0_VAL 0x07E723AD +#define CONFIG_SYS_MPCTL1_VAL 0x00000040 +#define CONFIG_SYS_PCDR_VAL 0x00010005 +#define CONFIG_SYS_GPCR_VAL 0x00000FFB #define USE_16M_OSZI /* If you have one, you want to use it The internal 32kHz oszillator jitters */ #ifdef USE_16M_OSZI -#define CFG_SPCTL0_VAL 0x04001401 -#define CFG_SPCTL1_VAL 0x0C000040 -#define CFG_CSCR_VAL 0x07030003 +#define CONFIG_SYS_SPCTL0_VAL 0x04001401 +#define CONFIG_SYS_SPCTL1_VAL 0x0C000040 +#define CONFIG_SYS_CSCR_VAL 0x07030003 #define CONFIG_SYS_CLK_FREQ 16780000 #define CONFIG_SYSPLL_CLK_FREQ 16000000 #else -#define CFG_SPCTL0_VAL 0x07E716D1 -#define CFG_CSCR_VAL 0x06000003 +#define CONFIG_SYS_SPCTL0_VAL 0x07E716D1 +#define CONFIG_SYS_CSCR_VAL 0x06000003 #define CONFIG_SYS_CLK_FREQ 16780000 #define CONFIG_SYSPLL_CLK_FREQ 16780000 @@ -281,9 +281,9 @@ * one may expect. For instance loadb command do not cares :-) * So advice is - do not relay on this... */ -#define CFG_LOAD_ADDR 0x08400000 +#define CONFIG_SYS_LOAD_ADDR 0x08400000 -#define CFG_FMCR_VAL 0x00000003 /* Reset Default */ +#define CONFIG_SYS_FMCR_VAL 0x00000003 /* Reset Default */ /* Bit[0:3] contain PERCLK1DIV for UART 1 0x000b00b ->b<- -> 192MHz/12=16MHz @@ -296,15 +296,15 @@ #define CONFIG_IMX_SERIAL2 #elif defined _CONFIG_UART3 | defined _CONFIG_UART4 #define CONFIG_IMX_SERIAL_NONE -#define CFG_NS16550 -#define CFG_NS16550_SERIAL -#define CFG_NS16550_CLK 3686400 -#define CFG_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_CLK 3686400 +#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_CONS_INDEX 1 #ifdef _CONFIG_UART3 -#define CFG_NS16550_COM1 0x15000000 +#define CONFIG_SYS_NS16550_COM1 0x15000000 #elif defined _CONFIG_UART4 -#define CFG_NS16550_COM1 0x16000000 +#define CONFIG_SYS_NS16550_COM1 0x16000000 #endif #endif |