diff options
Diffstat (limited to 'include/configs/socrates.h')
| -rw-r--r-- | include/configs/socrates.h | 212 |
1 files changed, 106 insertions, 106 deletions
diff --git a/include/configs/socrates.h b/include/configs/socrates.h index c4255f14e70..c67db8f25d9 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -84,20 +84,20 @@ #define CONFIG_BTB /* toggle branch predition */ #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ -#define CFG_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ +#define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ -#undef CFG_DRAM_TEST /* memory test, takes time */ -#define CFG_MEMTEST_START 0x00400000 -#define CFG_MEMTEST_END 0x00C00000 +#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ +#define CONFIG_SYS_MEMTEST_START 0x00400000 +#define CONFIG_SYS_MEMTEST_END 0x00C00000 /* * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) */ -#define CFG_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */ -#define CFG_CCSRBAR 0xE0000000 /* relocated CCSRBAR */ -#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ -#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */ +#define CONFIG_SYS_CCSRBAR 0xE0000000 /* relocated CCSRBAR */ +#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ +#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ /* DDR Setup */ #define CONFIG_FSL_DDR2 @@ -108,8 +108,8 @@ #undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef -#define CFG_DDR_SDRAM_BASE 0x00000000 -#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_VERY_BIG_RAM #define CONFIG_NUM_DDR_CONTROLLERS 1 @@ -122,80 +122,80 @@ #define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */ /* Hardcoded values, to use instead of SPD */ -#define CFG_DDR_CS0_BNDS 0x0000000f -#define CFG_DDR_CS0_CONFIG 0x80010102 -#define CFG_DDR_TIMING_0 0x00260802 -#define CFG_DDR_TIMING_1 0x3935D322 -#define CFG_DDR_TIMING_2 0x14904CC8 -#define CFG_DDR_MODE 0x00480432 -#define CFG_DDR_INTERVAL 0x030C0100 -#define CFG_DDR_CONFIG_2 0x04400000 -#define CFG_DDR_CONFIG 0xC3008000 -#define CFG_DDR_CLK_CONTROL 0x03800000 -#define CFG_SDRAM_SIZE 256 /* in Megs */ +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f +#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 +#define CONFIG_SYS_DDR_TIMING_0 0x00260802 +#define CONFIG_SYS_DDR_TIMING_1 0x3935D322 +#define CONFIG_SYS_DDR_TIMING_2 0x14904CC8 +#define CONFIG_SYS_DDR_MODE 0x00480432 +#define CONFIG_SYS_DDR_INTERVAL 0x030C0100 +#define CONFIG_SYS_DDR_CONFIG_2 0x04400000 +#define CONFIG_SYS_DDR_CONFIG 0xC3008000 +#define CONFIG_SYS_DDR_CLK_CONTROL 0x03800000 +#define CONFIG_SYS_SDRAM_SIZE 256 /* in Megs */ /* * Flash on the LocalBus */ -#define CFG_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */ +#define CONFIG_SYS_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */ -#define CFG_FLASH0 0xFE000000 -#define CFG_FLASH1 0xFC000000 -#define CFG_FLASH_BANKS_LIST { CFG_FLASH1, CFG_FLASH0 } +#define CONFIG_SYS_FLASH0 0xFE000000 +#define CONFIG_SYS_FLASH1 0xFC000000 +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 } -#define CFG_LBC_FLASH_BASE CFG_FLASH1 /* Localbus flash start */ -#define CFG_FLASH_BASE CFG_LBC_FLASH_BASE /* start of FLASH */ +#define CONFIG_SYS_LBC_FLASH_BASE CONFIG_SYS_FLASH1 /* Localbus flash start */ +#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_LBC_FLASH_BASE /* start of FLASH */ -#define CFG_BR0_PRELIM 0xfe001001 /* port size 16bit */ -#define CFG_OR0_PRELIM 0xfe000030 /* 32MB Flash */ -#define CFG_BR1_PRELIM 0xfc001001 /* port size 16bit */ -#define CFG_OR1_PRELIM 0xfe000030 /* 32MB Flash */ +#define CONFIG_SYS_BR0_PRELIM 0xfe001001 /* port size 16bit */ +#define CONFIG_SYS_OR0_PRELIM 0xfe000030 /* 32MB Flash */ +#define CONFIG_SYS_BR1_PRELIM 0xfc001001 /* port size 16bit */ +#define CONFIG_SYS_OR1_PRELIM 0xfe000030 /* 32MB Flash */ -#define CFG_FLASH_CFI /* flash is CFI compat. */ +#define CONFIG_SYS_FLASH_CFI /* flash is CFI compat. */ #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver*/ -#define CFG_MAX_FLASH_BANKS 2 /* number of banks */ -#define CFG_MAX_FLASH_SECT 256 /* sectors per device */ -#undef CFG_FLASH_CHECKSUM -#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */ +#undef CONFIG_SYS_FLASH_CHECKSUM +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ -#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ -#define CFG_LBC_LBCR 0x00000000 /* LB config reg */ -#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ -#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/ +#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ +#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ +#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ +#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/ #define CONFIG_L1_INIT_RAM -#define CFG_INIT_RAM_LOCK 1 -#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x4000 /* End used area in RAM */ +#define CONFIG_SYS_INIT_RAM_LOCK 1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data*/ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data*/ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256kB for Mon */ -#define CFG_MALLOC_LEN (4 << 20) /* Reserve 4 MB for malloc */ +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256kB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 4 MB for malloc */ /* FPGA and NAND */ -#define CFG_FPGA_BASE 0xc0000000 -#define CFG_FPGA_SIZE 0x00100000 /* 1 MB */ -#define CFG_HMI_BASE 0xc0010000 -#define CFG_BR3_PRELIM 0xc0001881 /* UPMA, 32-bit */ -#define CFG_OR3_PRELIM 0xfff00000 /* 1 MB */ - -#define CFG_NAND_BASE (CFG_FPGA_BASE + 0x70) -#define CFG_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_FPGA_BASE 0xc0000000 +#define CONFIG_SYS_FPGA_SIZE 0x00100000 /* 1 MB */ +#define CONFIG_SYS_HMI_BASE 0xc0010000 +#define CONFIG_SYS_BR3_PRELIM 0xc0001881 /* UPMA, 32-bit */ +#define CONFIG_SYS_OR3_PRELIM 0xfff00000 /* 1 MB */ + +#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_FPGA_BASE + 0x70) +#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define NAND_MAX_CHIPS 1 #define CONFIG_CMD_NAND /* LIME GDC */ -#define CFG_LIME_BASE 0xc8000000 -#define CFG_LIME_SIZE 0x04000000 /* 64 MB */ -#define CFG_BR2_PRELIM 0xc80018a1 /* UPMB, 32-bit */ -#define CFG_OR2_PRELIM 0xfc000000 /* 64 MB */ +#define CONFIG_SYS_LIME_BASE 0xc8000000 +#define CONFIG_SYS_LIME_SIZE 0x04000000 /* 64 MB */ +#define CONFIG_SYS_BR2_PRELIM 0xc80018a1 /* UPMB, 32-bit */ +#define CONFIG_SYS_OR2_PRELIM 0xfc000000 /* 64 MB */ #define CONFIG_VIDEO #define CONFIG_VIDEO_MB862xx @@ -205,33 +205,33 @@ #define CONFIG_CONSOLE_EXTRA_INFO #define VIDEO_FB_16BPP_PIXEL_SWAP #define CONFIG_VGA_AS_SINGLE_DEVICE -#define CFG_CONSOLE_IS_IN_ENV +#define CONFIG_SYS_CONSOLE_IS_IN_ENV #define CONFIG_VIDEO_SW_CURSOR #define CONFIG_SPLASH_SCREEN #define CONFIG_VIDEO_BMP_GZIP -#define CFG_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */ +#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */ /* Serial Port */ #define CONFIG_CONS_INDEX 1 #undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CFG_NS16550 -#define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE 1 -#define CFG_NS16550_CLK get_bus_freq(0) +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) -#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) -#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) #define CONFIG_BAUDRATE 115200 -#define CFG_BAUDRATE_TABLE \ +#define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ +#ifdef CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " #endif @@ -241,44 +241,44 @@ #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ #define CONFIG_HARD_I2C /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 102124 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C_SPEED 102124 /* I2C speed and slave address */ +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_OFFSET 0x3000 #define CONFIG_I2C_MULTI_BUS #define CONFIG_I2C_CMD_TREE -#define CFG_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_I2C2_OFFSET 0x3100 /* I2C RTC */ #define CONFIG_RTC_RX8025 /* Use Epson rx8025 rtc via i2c */ -#define CFG_I2C_RTC_ADDR 0x32 /* at address 0x32 */ +#define CONFIG_SYS_I2C_RTC_ADDR 0x32 /* at address 0x32 */ /* I2C W83782G HW-Monitoring IC */ -#define CFG_I2C_W83782G_ADDR 0x28 /* W83782G address */ +#define CONFIG_SYS_I2C_W83782G_ADDR 0x28 /* W83782G address */ /* I2C temp sensor */ /* Socrates uses Maxim's DS75, which is compatible with LM75 */ #define CONFIG_DTT_LM75 1 #define CONFIG_DTT_SENSORS {4} /* Sensor addresses */ -#define CFG_DTT_MAX_TEMP 125 -#define CFG_DTT_LOW_TEMP -55 -#define CFG_DTT_HYSTERESIS 3 -#define CFG_EEPROM_PAGE_WRITE_BITS 4 +#define CONFIG_SYS_DTT_MAX_TEMP 125 +#define CONFIG_SYS_DTT_LOW_TEMP -55 +#define CONFIG_SYS_DTT_HYSTERESIS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* * General PCI * Memory space is mapped 1-1. */ -#define CFG_PCI_PHYS 0x80000000 /* 1G PCI TLB */ +#define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */ /* PCI is clocked by the external source at 33 MHz */ #define CONFIG_PCI_CLK_FREQ 33000000 -#define CFG_PCI1_MEM_BASE 0x80000000 -#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE -#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI1_IO_BASE 0xE2000000 -#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE -#define CFG_PCI1_IO_SIZE 0x01000000 /* 16M */ +#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCI1_IO_BASE 0xE2000000 +#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE +#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */ #if defined(CONFIG_PCI) #define CONFIG_PCI_PNP /* do pci plug-and-play */ @@ -314,13 +314,13 @@ */ #define CONFIG_ENV_IS_IN_FLASH 1 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ -#define CONFIG_ENV_ADDR (CFG_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) #define CONFIG_ENV_SIZE 0x4000 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ #define CONFIG_TIMESTAMP /* Print image info with ts */ @@ -362,27 +362,27 @@ /* * Miscellaneous configurable options */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_LOAD_ADDR 0x2000000 /* default load address */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) - #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ + #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else - #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ + #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ #endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buf Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buf Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ /* * Internal Definitions @@ -473,9 +473,9 @@ #define CONFIG_PCI_OHCI 1 #define CONFIG_PCI_OHCI_DEVNO 3 /* Number in PCI list */ #define CONFIG_PCI_EHCI_DEVNO (CONFIG_PCI_OHCI_DEVNO / 2) -#define CFG_USB_OHCI_MAX_ROOT_PORTS 15 -#define CFG_USB_OHCI_SLOT_NAME "ohci_pci" -#define CFG_OHCI_SWAP_REG_ACCESS 1 +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci" +#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 #define CONFIG_DOS_PARTITION 1 #define CONFIG_USB_STORAGE 1 |